diff -ruw linux-6.4/Makefile linux-6.4-fbx/Makefile --- linux-6.4/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/Makefile 2024-04-19 18:18:34.037535416 +0200 @@ -386,6 +386,8 @@ # CROSS_COMPILE can be set on the command line # make CROSS_COMPILE=ia64-linux- # Alternatively CROSS_COMPILE can be set in the environment. +# A third alternative is to store a setting in .config so that plain +# "make" in the configured kernel build directory always uses that. # Default value for CROSS_COMPILE is not to prefix executables # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile ARCH ?= $(SUBARCH) @@ -423,6 +425,9 @@ KCONFIG_CONFIG ?= .config export KCONFIG_CONFIG +CONFIG_CROSS_COMPILE := $(shell grep ^CONFIG_CROSS_COMPILE= $(KCONFIG_CONFIG) | cut -f 2 -d = | tr -d '"') +CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%) + # SHELL used by kbuild CONFIG_SHELL := sh @@ -1366,7 +1371,7 @@ quiet_cmd_headers_install = INSTALL $(INSTALL_HDR_PATH)/include cmd_headers_install = \ mkdir -p $(INSTALL_HDR_PATH); \ - rsync -mrl --include='*/' --include='*\.h' --exclude='*' \ + rsync -cmrl --include='*/' --include='*\.h' --exclude='*' \ usr/include $(INSTALL_HDR_PATH) PHONY += headers_install diff -ruw linux-6.4/arch/arm64/Kconfig linux-6.4-fbx/arch/arm64/Kconfig --- linux-6.4/arch/arm64/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/Kconfig 2024-04-19 18:18:34.037535416 +0200 @@ -2327,4 +2327,3 @@ source "drivers/acpi/Kconfig" source "arch/arm64/kvm/Kconfig" - diff -ruw linux-6.4/arch/arm64/Kconfig.platforms linux-6.4-fbx/arch/arm64/Kconfig.platforms --- linux-6.4/arch/arm64/Kconfig.platforms 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/Kconfig.platforms 2023-11-16 15:32:31.909611440 +0100 @@ -63,6 +63,8 @@ config ARCH_BCMBCA bool "Broadcom Broadband Carrier Access (BCA) origin SoC" select GPIOLIB + select PINCTRL + select PINCTRL_BCM63138 help Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based BCA chipset. @@ -78,6 +80,14 @@ help This enables support for Broadcom's ARMv8 Set Top Box SoCs +config ARCH_BCM63XX_SHARED_OSH + bool "Make shared pages and translation table walks outer shareable" + depends on ARCH_BCMBCA + default y + help + This is required for HW coherency on bcm63158. Say Y here if + you are compiling a kernel for a bcm63158 board. + endif config ARCH_BERLIN @@ -243,6 +253,16 @@ help This enables support for the ARMv8 based Qualcomm chipsets. +config ARCH_QCOM_DTB + bool "build qualcomm platforms DTB" + depends on ARCH_QCOM + default y + +config ARCH_QCOM_FBX_DTB + bool "build freebox DTB on qualcomm platform" + depends on ARCH_QCOM + default y + config ARCH_REALTEK bool "Realtek Platforms" select RESET_CONTROLLER diff -ruw linux-6.4/arch/arm64/boot/Makefile linux-6.4-fbx/arch/arm64/boot/Makefile --- linux-6.4/arch/arm64/boot/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/boot/Makefile 2023-05-22 20:06:36.515648243 +0200 @@ -48,3 +48,5 @@ $(NM) vmlinux|grep _kernel_codesize|cut -d' ' -f1) include $(srctree)/drivers/firmware/efi/libstub/Makefile.zboot + +subdir-y += dts/ diff -ruw linux-6.4/arch/arm64/boot/dts/amlogic/Makefile linux-6.4-fbx/arch/arm64/boot/dts/amlogic/Makefile --- linux-6.4/arch/arm64/boot/dts/amlogic/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/boot/dts/amlogic/Makefile 2023-11-27 19:13:52.958343154 +0100 @@ -1,8 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 +fbx-boards += \ + fbxwmr.dtb \ + fbxwmr-r1.dtb fbxwmr-r2.dtb \ + fbxwmr-r3.dtb fbxwmr-r4.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-3.dtb +DTC_FLAGS += -@ +dtb-$(CONFIG_ARCH_MESON) += $(fbx-boards) dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb diff -ruw linux-6.4/arch/arm64/boot/dts/broadcom/Makefile linux-6.4-fbx/arch/arm64/boot/dts/broadcom/Makefile --- linux-6.4/arch/arm64/boot/dts/broadcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/Makefile 2023-05-22 20:06:36.535648775 +0200 @@ -11,3 +11,4 @@ subdir-y += bcmbca subdir-y += northstar2 subdir-y += stingray +subdir-y += bcm63xx diff -ruw linux-6.4/arch/arm64/boot/dts/marvell/Makefile linux-6.4-fbx/arch/arm64/boot/dts/marvell/Makefile --- linux-6.4/arch/arm64/boot/dts/marvell/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/boot/dts/marvell/Makefile 2023-05-22 20:06:36.575649839 +0200 @@ -27,3 +27,19 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_dsl_lte.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_pon.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_pcie_pine_pericom.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_pcie_pine_asmedia.dtb + +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp2_ftth_p2p.dtb + +# export symbols in DTBs file to allow overlay usage +DTC_FLAGS += -@ diff -ruw linux-6.4/arch/arm64/boot/dts/qcom/Makefile linux-6.4-fbx/arch/arm64/boot/dts/qcom/Makefile --- linux-6.4/arch/arm64/boot/dts/qcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/boot/dts/qcom/Makefile 2023-11-24 18:39:54.353042707 +0100 @@ -1,204 +1,208 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt510.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt58.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5x.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-tissot.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-vince.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-huawei-angler-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3t.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-natrium.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-scorpio.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-cheeseburger.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb -dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-kb.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-wifi.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd-pro.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-samsung-starqltechn.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-ebbg.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-tianma.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-csot.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8094-sony-xperia-kitakami-karin_windy.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8096-db820c.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq5332-mi01.2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq5332-rdp468.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq6018-cp01-c1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq8074-hk10-c1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp418.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp433.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp449.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM_FBX_DTB) += fbxgw9r.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-acer-a1-724.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-alcatel-idol347.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-asus-z00l.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-gplus-fl8005a.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-huawei-g7.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-longcheer-l8150.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-longcheer-l8910.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-a3u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-e5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-e7.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-grandmax.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-gt510.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-gt58.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-j5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-j5x.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-serranove.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-thwc-uf896.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-thwc-ufi001c.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-motorola-potter.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-daisy.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-mido.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-tissot.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-vince.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8956-sony-xperia-loire-kugo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8956-sony-xperia-loire-suzu.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-lg-bullhead-rev-10.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-lg-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-msft-lumia-octagon-talkman.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-xiaomi-libra.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-huawei-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-msft-lumia-octagon-cityman.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-ivy.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-karin.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-satsuki.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-sumire.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-suzuran.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-oneplus3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-oneplus3t.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-sony-xperia-tone-dora.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-sony-xperia-tone-kagura.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-sony-xperia-tone-keyaki.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-xiaomi-gemini.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996pro-xiaomi-natrium.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996pro-xiaomi-scorpio.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-asus-novago-tp370ql.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-fxtec-pro1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-hp-envy-x2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-lenovo-miix-630.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-oneplus-cheeseburger.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-oneplus-dumpling.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-sony-xperia-yoshino-lilac.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-sony-xperia-yoshino-maple.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-sony-xperia-yoshino-poplar.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-xiaomi-sagit.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qcs404-evb-1000.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb2210-rb1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb4210-rb2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb5165-rb5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb5165-rb5-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qru1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8295p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8540p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8775p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-homestar-r2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-homestar-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-homestar-r4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-kingoftown.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r1-kb.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r3-kb.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r9.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r9-kb.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r9-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-r4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-r9.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-lte-parade.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-lte-ti.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-parade.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-ti.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel360-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel360-wifi.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r2-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-quackingstick-r0.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-quackingstick-r0-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-inx.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-crd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-crd-pro.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-evoker.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-evoker-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-herobrine-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-villager-r0.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-villager-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-villager-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie-nvme.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie-nvme-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-idp2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc8280xp-crd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc8280xp-lenovo-thinkpad-x13s.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sda660-inforce-ifc6560.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm450-motorola-ali.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-ganges-kirin.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-nile-discovery.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-nile-pioneer.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-nile-voyager.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm632-fairphone-fp3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm632-motorola-ocean.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm636-sony-xperia-ganges-mermaid.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm660-xiaomi-lavender.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm670-google-sargo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-cheza-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-cheza-r2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-cheza-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-db845c.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-lg-judyln.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-lg-judyp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-oneplus-enchilada.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-oneplus-fajita.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-samsung-starqltechn.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-sony-xperia-tama-akari.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-sony-xperia-tama-akatsuki.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-sony-xperia-tama-apollo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-xiaomi-beryllium-ebbg.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-xiaomi-beryllium-tianma.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-xiaomi-polaris.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-shift-axolotl.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6115p-lenovo-j606f.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6125-sony-xperia-seine-pdx201.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6125-xiaomi-laurel-sprout.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6350-sony-xperia-lena-pdx213.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6375-sony-xperia-murray-pdx225.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm7225-fairphone-fp4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-microsoft-surface-duo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-sony-xperia-kumano-bahamut.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-sony-xperia-kumano-griffin.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-sony-xperia-edo-pdx203.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-sony-xperia-edo-pdx206.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-xiaomi-elish-boe.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-xiaomi-elish-csot.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-microsoft-surface-duo2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-sony-xperia-sagami-pdx214.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-sony-xperia-sagami-pdx215.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-sony-xperia-nagara-pdx223.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-sony-xperia-nagara-pdx224.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8550-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8550-qrd.dtb diff -ruw linux-6.4/arch/arm64/include/asm/assembler.h linux-6.4-fbx/arch/arm64/include/asm/assembler.h --- linux-6.4/arch/arm64/include/asm/assembler.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/include/asm/assembler.h 2024-01-19 17:01:19.841846374 +0100 @@ -428,6 +428,45 @@ /* * Macro to perform a data cache maintenance for the interval + * [kaddr, kaddr + size) + * This macro does not do "data synchronization barrier". Caller should + * do "dsb" after transaction. + * + * op: operation passed to dc instruction + * kaddr: starting virtual address of the region + * size: size of the region + * Corrupts: kaddr, size, tmp1, tmp2 + */ + .macro dcache_by_line_op_no_dsb op, kaddr, size, tmp1, tmp2 + dcache_line_size \tmp1, \tmp2 + add \size, \kaddr, \size + sub \tmp2, \tmp1, #1 + bic \kaddr, \kaddr, \tmp2 +9998: + .ifc \op, cvau + __dcache_op_workaround_clean_cache \op, \kaddr + .else + .ifc \op, cvac + __dcache_op_workaround_clean_cache \op, \kaddr + .else + .ifc \op, cvap + sys 3, c7, c12, 1, \kaddr // dc cvap + .else + .ifc \op, cvadp + sys 3, c7, c13, 1, \kaddr // dc cvadp + .else + dc \op, \kaddr + .endif + .endif + .endif + .endif + add \kaddr, \kaddr, \tmp1 + cmp \kaddr, \size + b.lo 9998b + .endm + +/* + * Macro to perform a data cache maintenance for the interval * [start, end) * * op: operation passed to dc instruction diff -ruw linux-6.4/arch/arm64/include/asm/cacheflush.h linux-6.4-fbx/arch/arm64/include/asm/cacheflush.h --- linux-6.4/arch/arm64/include/asm/cacheflush.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/include/asm/cacheflush.h 2024-01-19 17:01:19.841846374 +0100 @@ -79,6 +79,17 @@ extern long caches_clean_inval_user_pou(unsigned long start, unsigned long end); extern void sync_icache_aliases(unsigned long start, unsigned long end); +extern void dmac_flush_range(const void *start, const void *end); +extern void dmac_inv_range(const void *start, const void *end); +extern void dmac_clean_range(const void *start, const void *end); +extern void __dma_flush_area_no_dsb(const void *start, size_t size); +extern void __dma_inv_area_no_dsb(const void *start, size_t size); +extern void __dma_clean_area_no_dsb(const void *start, size_t size); + +extern void dmac_flush_range_no_dsb(const void *start, const void *end); +extern void dmac_inv_range_no_dsb(const void *start, const void *end); +extern void dmac_clean_range_no_dsb(const void *start, const void *end); + static inline void flush_icache_range(unsigned long start, unsigned long end) { caches_clean_inval_pou(start, end); diff -ruw linux-6.4/arch/arm64/include/asm/memory.h linux-6.4-fbx/arch/arm64/include/asm/memory.h --- linux-6.4/arch/arm64/include/asm/memory.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/include/asm/memory.h 2023-05-22 20:06:36.727653882 +0200 @@ -74,7 +74,7 @@ #define KASAN_SHADOW_END ((UL(1) << (64 - KASAN_SHADOW_SCALE_SHIFT)) \ + KASAN_SHADOW_OFFSET) #define PAGE_END (KASAN_SHADOW_END - (1UL << (vabits_actual - KASAN_SHADOW_SCALE_SHIFT))) -#define KASAN_THREAD_SHIFT 1 +#define KASAN_THREAD_SHIFT 2 #else #define KASAN_THREAD_SHIFT 0 #define PAGE_END (_PAGE_END(VA_BITS_MIN)) diff -ruw linux-6.4/arch/arm64/include/asm/pgtable-hwdef.h linux-6.4-fbx/arch/arm64/include/asm/pgtable-hwdef.h --- linux-6.4/arch/arm64/include/asm/pgtable-hwdef.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/include/asm/pgtable-hwdef.h 2023-05-22 20:06:36.727653882 +0200 @@ -146,7 +146,11 @@ #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ +#ifdef CONFIG_ARCH_BCM63XX_SHARED_OSH +#define PTE_SHARED (_AT(pteval_t, 2) << 8) /* SH[1:0], outer shareable */ +#else #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#endif #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ #define PTE_GP (_AT(pteval_t, 1) << 50) /* BTI guarded */ @@ -242,12 +246,19 @@ #define TCR_SH0_SHIFT 12 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT) +#define TCR_SH0_OUTER (UL(2) << TCR_SH0_SHIFT) #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT) #define TCR_SH1_SHIFT 28 #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT) +#define TCR_SH1_OUTER (UL(2) << TCR_SH1_SHIFT) #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT) + +#ifdef CONFIG_ARCH_BCM63XX_SHARED_OSH +#define TCR_SHARED (TCR_SH0_OUTER | TCR_SH1_OUTER) +#else #define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER) +#endif #define TCR_TG0_SHIFT 14 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) diff -ruw linux-6.4/arch/arm64/mm/cache.S linux-6.4-fbx/arch/arm64/mm/cache.S --- linux-6.4/arch/arm64/mm/cache.S 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/mm/cache.S 2024-01-19 17:01:19.841846374 +0100 @@ -164,6 +164,64 @@ SYM_FUNC_ALIAS(dcache_inval_poc, __pi_dcache_inval_poc) /* + * __dma_inv_area_no_dsb(start, size) + * + * This macro does not do "data synchronization barrier". Caller should + * do "dsb" after transaction. + * + * start - virtual start address of region + * size - size in question + */ +SYM_FUNC_START(__dma_inv_area_no_dsb) + add x1, x1, x0 + dcache_line_size x2, x3 + sub x3, x2, #1 + tst x1, x3 // end cache line aligned? + bic x1, x1, x3 + b.eq 1f + dc civac, x1 // clean & invalidate D / U line +1: tst x0, x3 // start cache line aligned? + bic x0, x0, x3 + b.eq 2f + dc civac, x0 // clean & invalidate D / U line + b 3f +2: dc ivac, x0 // invalidate D / U line +3: add x0, x0, x2 + cmp x0, x1 + b.lo 2b + ret +SYM_FUNC_END(__dma_inv_area_no_dsb) + +/* + * __dma_clean_area_no_dsb(start, size) + * + * his macro does not do "data synchronization barrier". Caller should + * o "dsb" after transaction. + * + * start - virtual start address of region + * size - size in question + */ +SYM_FUNC_START(__dma_clean_area_no_dsb) + dcache_by_line_op_no_dsb cvac, x0, x1, x2, x3 + ret +SYM_FUNC_END(__dma_clean_area_no_dsb) + +/* + * __dma_flush_area_no_dsb(start, size) + * + * clean & invalidate D / U line + * his macro does not do "data synchronization barrier". Caller should + * o "dsb" after transaction. + * + * start - virtual start address of region + * size - size in question + */ +SYM_FUNC_START(__dma_flush_area_no_dsb) + dcache_by_line_op_no_dsb civac, x0, x1, x2, x3 + ret +SYM_FUNC_END(__dma_flush_area_no_dsb) + +/* * dcache_clean_poc(start, end) * * Ensure that any D-cache lines for the interval [start, end) diff -ruw linux-6.4/arch/arm64/mm/flush.c linux-6.4-fbx/arch/arm64/mm/flush.c --- linux-6.4/arch/arm64/mm/flush.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/arch/arm64/mm/flush.c 2024-01-19 17:01:19.841846374 +0100 @@ -107,3 +107,39 @@ } EXPORT_SYMBOL_GPL(arch_invalidate_pmem); #endif + +void dmac_flush_range(const void *start, const void *end) +{ + dcache_clean_inval_poc((unsigned long)start, (unsigned long)end); +} +EXPORT_SYMBOL(dmac_flush_range); + +void dmac_flush_range_no_dsb(const void *start, const void *end) +{ + __dma_flush_area_no_dsb(start, (void *)(end) - (void *)(start)); +} +EXPORT_SYMBOL(dmac_flush_range_no_dsb); + +void dmac_inv_range(const void *start, const void *end) +{ + dcache_inval_poc((unsigned long)start, (unsigned long)(end)); +} +EXPORT_SYMBOL(dmac_inv_range); + +void dmac_inv_range_no_dsb(const void *start, const void *end) +{ + __dma_inv_area_no_dsb(start, (void *)(end) - (void *)(start)); +} +EXPORT_SYMBOL(dmac_inv_range_no_dsb); + +void dmac_clean_range(const void *start, const void *end) +{ + dcache_clean_poc((unsigned long)start, (unsigned long)end); +} +EXPORT_SYMBOL(dmac_clean_range); + +void dmac_clean_range_no_dsb(const void *start, const void *end) +{ + __dma_clean_area_no_dsb(start, (void *)(end) - (void *)(start)); +} +EXPORT_SYMBOL(dmac_clean_range_no_dsb); diff -ruw linux-6.4/block/blk-flush.c linux-6.4-fbx/block/blk-flush.c --- linux-6.4/block/blk-flush.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/blk-flush.c 2023-05-22 20:06:37.459673353 +0200 @@ -172,10 +172,21 @@ rq->flush.seq |= seq; cmd_flags = rq->cmd_flags; - if (likely(!error)) + if (likely(!error)) { seq = blk_flush_cur_seq(rq); - else + } else { seq = REQ_FSEQ_DONE; + printk_once(KERN_ERR "%s: flush failed: data integrity problem\n", + rq->q->disk ? rq->q->disk->disk_name : "?"); + /* + * returning an error to the FS is wrong: the data is all + * there, it just might not be written out in the expected + * order and thus have a window where the integrity is suspect + * in a crash. Given the small likelihood of actually + * crashing, we should just log a warning here. + */ + error = 0; + } switch (seq) { case REQ_FSEQ_PREFLUSH: diff -ruw linux-6.4/block/blk-mq.c linux-6.4-fbx/block/blk-mq.c --- linux-6.4/block/blk-mq.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/blk-mq.c 2023-06-27 11:47:15.663855962 +0200 @@ -955,7 +955,7 @@ } EXPORT_SYMBOL_GPL(blk_update_request); -static inline void blk_account_io_done(struct request *req, u64 now) +static inline void blk_account_io_done(struct request *req, u64 now, blk_status_t error) { /* * Account IO completion. flush_rq isn't accounted as a @@ -970,6 +970,8 @@ update_io_ticks(req->part, jiffies, true); part_stat_inc(req->part, ios[sgrp]); part_stat_add(req->part, nsecs[sgrp], now - req->start_time_ns); + if (error) + part_stat_inc(req->part, io_errors[rq_data_dir(req)]); part_stat_unlock(); } } @@ -994,19 +996,19 @@ } } -static inline void __blk_mq_end_request_acct(struct request *rq, u64 now) +static inline void __blk_mq_end_request_acct(struct request *rq, u64 now, blk_status_t error) { if (rq->rq_flags & RQF_STATS) blk_stat_add(rq, now); blk_mq_sched_completed_request(rq, now); - blk_account_io_done(rq, now); + blk_account_io_done(rq, now, error); } inline void __blk_mq_end_request(struct request *rq, blk_status_t error) { if (blk_mq_need_time_stamp(rq)) - __blk_mq_end_request_acct(rq, ktime_get_ns()); + __blk_mq_end_request_acct(rq, ktime_get_ns(), error); if (rq->end_io) { rq_qos_done(rq->q, rq); @@ -1060,7 +1062,7 @@ blk_complete_request(rq); if (iob->need_ts) - __blk_mq_end_request_acct(rq, now); + __blk_mq_end_request_acct(rq, now, 0); rq_qos_done(rq->q, rq); @@ -3049,7 +3051,7 @@ blk_mq_run_dispatch_ops(q, ret = blk_mq_request_issue_directly(rq, true)); if (ret) - blk_account_io_done(rq, ktime_get_ns()); + blk_account_io_done(rq, ktime_get_ns(), 0); return ret; } EXPORT_SYMBOL_GPL(blk_insert_cloned_request); diff -ruw linux-6.4/block/blk.h linux-6.4-fbx/block/blk.h --- linux-6.4/block/blk.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/blk.h 2023-05-22 20:06:37.475673778 +0200 @@ -404,6 +404,7 @@ #define ADDPART_FLAG_NONE 0 #define ADDPART_FLAG_RAID 1 #define ADDPART_FLAG_WHOLEDISK 2 +#define ADDPART_FLAG_RO 4 int bdev_add_partition(struct gendisk *disk, int partno, sector_t start, sector_t length); int bdev_del_partition(struct gendisk *disk, int partno); diff -ruw linux-6.4/block/genhd.c linux-6.4-fbx/block/genhd.c --- linux-6.4/block/genhd.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/genhd.c 2023-05-22 20:06:37.475673778 +0200 @@ -984,6 +984,7 @@ "%8u %8u %8u " "%8lu %8lu %8llu %8u " "%8lu %8u" + "%8lu %8lu" "\n", stat.ios[STAT_READ], stat.merges[STAT_READ], @@ -1005,7 +1006,9 @@ (unsigned long long)stat.sectors[STAT_DISCARD], (unsigned int)div_u64(stat.nsecs[STAT_DISCARD], NSEC_PER_MSEC), stat.ios[STAT_FLUSH], - (unsigned int)div_u64(stat.nsecs[STAT_FLUSH], NSEC_PER_MSEC)); + (unsigned int)div_u64(stat.nsecs[STAT_FLUSH], NSEC_PER_MSEC), + part_stat_read(bdev, io_errors[READ]), + part_stat_read(bdev, io_errors[WRITE])); } ssize_t part_inflight_show(struct device *dev, struct device_attribute *attr, diff -ruw linux-6.4/block/partitions/Kconfig linux-6.4-fbx/block/partitions/Kconfig --- linux-6.4/block/partitions/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/partitions/Kconfig 2023-05-22 20:06:37.479673885 +0200 @@ -270,4 +270,12 @@ Say Y here if you want to read the partition table from bootargs. The format for the command line is just like mtdparts. +config OF_PARTITION + bool "Device tree partition support" if PARTITION_ADVANCED + depends on OF + +config OF_PARTITION_IGNORE_RO + bool "ignore read-only flag" + depends on OF_PARTITION + endmenu diff -ruw linux-6.4/block/partitions/Makefile linux-6.4-fbx/block/partitions/Makefile --- linux-6.4/block/partitions/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/partitions/Makefile 2023-02-24 19:09:45.669973308 +0100 @@ -20,3 +20,4 @@ obj-$(CONFIG_EFI_PARTITION) += efi.o obj-$(CONFIG_KARMA_PARTITION) += karma.o obj-$(CONFIG_SYSV68_PARTITION) += sysv68.o +obj-$(CONFIG_OF_PARTITION) += dt.o diff -ruw linux-6.4/block/partitions/check.h linux-6.4-fbx/block/partitions/check.h --- linux-6.4/block/partitions/check.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/partitions/check.h 2023-05-22 20:06:37.479673885 +0200 @@ -67,3 +67,4 @@ int sun_partition(struct parsed_partitions *state); int sysv68_partition(struct parsed_partitions *state); int ultrix_partition(struct parsed_partitions *state); +int dt_partition(struct parsed_partitions *); diff -ruw linux-6.4/block/partitions/core.c linux-6.4-fbx/block/partitions/core.c --- linux-6.4/block/partitions/core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/block/partitions/core.c 2023-05-22 20:06:37.479673885 +0200 @@ -13,6 +13,10 @@ #include "check.h" static int (*check_part[])(struct parsed_partitions *) = { +#ifdef CONFIG_OF_PARTITION + dt_partition, +#endif + /* * Probe partition formats with tables at disk address 0 * that also have an ADFS boot block at 0xdc0. @@ -341,6 +345,7 @@ bdev->bd_start_sect = start; bdev_set_nr_sectors(bdev, len); + bdev->bd_read_only = (flags & ADDPART_FLAG_RO); pdev = &bdev->bd_device; dname = dev_name(ddev); diff -ruw linux-6.4/drivers/Kconfig linux-6.4-fbx/drivers/Kconfig --- linux-6.4/drivers/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/Kconfig 2023-05-22 20:06:37.519674949 +0200 @@ -21,6 +21,8 @@ source "drivers/gnss/Kconfig" +source "drivers/fbxprocfs/Kconfig" + source "drivers/mtd/Kconfig" source "drivers/of/Kconfig" @@ -77,6 +79,10 @@ source "drivers/gpio/Kconfig" +source "drivers/fbxgpio/Kconfig" + +source "drivers/fbxjtag/Kconfig" + source "drivers/w1/Kconfig" source "drivers/power/Kconfig" @@ -85,6 +91,8 @@ source "drivers/thermal/Kconfig" +source "drivers/fbxwatchdog/Kconfig" + source "drivers/watchdog/Kconfig" source "drivers/ssb/Kconfig" diff -ruw linux-6.4/drivers/Makefile linux-6.4-fbx/drivers/Makefile --- linux-6.4/drivers/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/Makefile 2023-05-22 20:06:37.519674949 +0200 @@ -21,7 +21,9 @@ obj-$(CONFIG_GPIOLIB) += gpio/ obj-y += pwm/ +obj-$(CONFIG_FREEBOX_GPIO) += fbxgpio/ obj-y += pci/ +obj-$(CONFIG_FREEBOX_JTAG) += fbxjtag/ obj-$(CONFIG_PARISC) += parisc/ obj-$(CONFIG_RAPIDIO) += rapidio/ @@ -121,6 +123,7 @@ obj-y += power/ obj-$(CONFIG_HWMON) += hwmon/ obj-$(CONFIG_THERMAL) += thermal/ +obj-$(CONFIG_FREEBOX_WATCHDOG) += fbxwatchdog/ obj-$(CONFIG_WATCHDOG) += watchdog/ obj-$(CONFIG_MD) += md/ obj-$(CONFIG_BT) += bluetooth/ @@ -195,3 +198,5 @@ obj-$(CONFIG_HTE) += hte/ obj-$(CONFIG_DRM_ACCEL) += accel/ obj-$(CONFIG_CDX_BUS) += cdx/ + +obj-$(CONFIG_FREEBOX_PROCFS) += fbxprocfs/ diff -ruw linux-6.4/drivers/base/regmap/internal.h linux-6.4-fbx/drivers/base/regmap/internal.h --- linux-6.4/drivers/base/regmap/internal.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/base/regmap/internal.h 2023-05-22 20:06:37.743680907 +0200 @@ -326,5 +326,6 @@ #define regmap_init_ram(config, data) \ __regmap_lockdep_wrapper(__regmap_init_ram, #config, config, data) +void *regmap_mmio_ctx_get_base(const void *priv); #endif diff -ruw linux-6.4/drivers/base/regmap/regmap-mmio.c linux-6.4-fbx/drivers/base/regmap/regmap-mmio.c --- linux-6.4/drivers/base/regmap/regmap-mmio.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/base/regmap/regmap-mmio.c 2023-05-22 20:06:37.747681013 +0200 @@ -633,4 +633,10 @@ } EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk); +void *regmap_mmio_ctx_get_base(const void *priv) +{ + struct regmap_mmio_context *ctx = (struct regmap_mmio_context *)priv; + return ctx->regs; +} + MODULE_LICENSE("GPL v2"); diff -ruw linux-6.4/drivers/base/regmap/regmap.c linux-6.4-fbx/drivers/base/regmap/regmap.c --- linux-6.4/drivers/base/regmap/regmap.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/base/regmap/regmap.c 2023-06-27 11:47:15.675856288 +0200 @@ -3542,6 +3542,15 @@ } EXPORT_SYMBOL_GPL(regmap_parse_val); +#ifdef CONFIG_REGMAP_MMIO +void *regmap_get_mmio_base_address(struct regmap *map) +{ + return regmap_mmio_ctx_get_base(map->bus_context); +} + +EXPORT_SYMBOL_GPL(regmap_get_mmio_base_address); +#endif + static int __init regmap_initcall(void) { regmap_debugfs_initcall(); diff -ruw linux-6.4/drivers/bluetooth/btrtl.c linux-6.4-fbx/drivers/bluetooth/btrtl.c --- linux-6.4/drivers/bluetooth/btrtl.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/bluetooth/btrtl.c 2023-05-22 20:06:37.787682077 +0200 @@ -188,6 +188,15 @@ .fw_name = "rtl_bt/rtl8821cs_fw.bin", .cfg_name = "rtl_bt/rtl8821cs_config" }, + /* 8761BTV */ + { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV, + .lmp_subver = RTL_ROM_LMP_8761A, + .hci_rev = 0xb, + .config_needed = false, + .has_rom_version = true, + .fw_name = "rtl_bt/rtl8761b_fw.bin", + .cfg_name = "rtl_bt/rtl8761b_config" }, + /* 8761A */ { IC_INFO(RTL_ROM_LMP_8761A, 0xa, 0x6, HCI_USB), .config_needed = false, @@ -945,6 +954,27 @@ return 0; } +void btrtl_show_version(struct hci_dev *hdev) +{ + + struct sk_buff *skb; + struct hci_rp_read_local_version *resp; + + skb = btrtl_read_local_version(hdev); + if (IS_ERR(skb)) + return; + + resp = (struct hci_rp_read_local_version *)skb->data; + rtl_dev_info(hdev, + "rtl: hci_ver=%02x hci_rev=%04x lmp_ver=%02x lmp_subver=%04x", + resp->hci_ver, + le16_to_cpu(resp->hci_rev), + resp->lmp_ver, + le16_to_cpu(resp->lmp_subver)); + kfree_skb(skb); +} +EXPORT_SYMBOL_GPL(btrtl_show_version); + void btrtl_free(struct btrtl_device_info *btrtl_dev) { struct rtl_subsection *entry, *tmp; @@ -1371,6 +1401,8 @@ MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin"); MODULE_FIRMWARE("rtl_bt/rtl8761a_config.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8761b_fw.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8761b_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8821a_fw.bin"); MODULE_FIRMWARE("rtl_bt/rtl8821a_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8822b_fw.bin"); diff -ruw linux-6.4/drivers/bluetooth/btrtl.h linux-6.4-fbx/drivers/bluetooth/btrtl.h --- linux-6.4/drivers/bluetooth/btrtl.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/bluetooth/btrtl.h 2023-05-22 20:06:37.787682077 +0200 @@ -140,6 +140,7 @@ unsigned int *controller_baudrate, u32 *device_baudrate, bool *flow_control); +void btrtl_show_version(struct hci_dev *hdev); #else static inline struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, diff -ruw linux-6.4/drivers/bluetooth/hci_h5.c linux-6.4-fbx/drivers/bluetooth/hci_h5.c --- linux-6.4/drivers/bluetooth/hci_h5.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/bluetooth/hci_h5.c 2023-05-22 20:06:37.791682184 +0200 @@ -98,6 +98,7 @@ const struct h5_vnd *vnd; const char *id; + struct gpio_desc *reset_gpio; struct gpio_desc *enable_gpio; struct gpio_desc *device_wake_gpio; }; @@ -849,6 +850,9 @@ return -ENODEV; h5->vnd = data->vnd; + + of_property_read_string(serdev->dev.of_node, + "firmware-postfix", &h5->id); } if (data->driver_info & H5_INFO_WAKEUP_DISABLE) @@ -863,6 +867,10 @@ if (IS_ERR(h5->device_wake_gpio)) return PTR_ERR(h5->device_wake_gpio); + h5->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(h5->reset_gpio)) + return PTR_ERR(h5->reset_gpio); + return hci_uart_register_device(&h5->serdev_hu, &h5p); } @@ -941,6 +949,8 @@ if (err) goto out_free; + /* show version after download */ + btrtl_show_version(h5->hu->hdev); btrtl_set_quirks(h5->hu->hdev, btrtl_dev); out_free: @@ -977,8 +987,15 @@ gpiod_set_value_cansleep(h5->device_wake_gpio, 0); msleep(100); + /* make sure reset is held */ + gpiod_set_value_cansleep(h5->reset_gpio, 1); + msleep(10); + /* The controller needs up to 500ms to wakeup */ gpiod_set_value_cansleep(h5->enable_gpio, 1); + /* Take it out of reset */ + gpiod_set_value_cansleep(h5->reset_gpio, 0); + msleep(100); gpiod_set_value_cansleep(h5->device_wake_gpio, 1); msleep(500); } @@ -989,6 +1006,7 @@ pm_runtime_disable(&h5->hu->serdev->dev); gpiod_set_value_cansleep(h5->device_wake_gpio, 0); + gpiod_set_value_cansleep(h5->reset_gpio, 1); gpiod_set_value_cansleep(h5->enable_gpio, 0); } @@ -1063,7 +1081,7 @@ {}, }; -static struct h5_vnd rtl_vnd = { +static __maybe_unused struct h5_vnd rtl_vnd = { .setup = h5_btrtl_setup, .open = h5_btrtl_open, .close = h5_btrtl_close, @@ -1108,6 +1126,8 @@ .data = (const void *)&h5_data_rtl8723bs }, { .compatible = "realtek,rtl8723ds-bt", .data = (const void *)&h5_data_rtl8723bs }, + { .compatible = "realtek,rtl8761btv-bt", + .data = (const void *)&h5_data_rtl8822cs }, #endif { }, }; diff -ruw linux-6.4/drivers/char/Kconfig linux-6.4-fbx/drivers/char/Kconfig --- linux-6.4/drivers/char/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/char/Kconfig 2023-05-22 20:06:37.807682609 +0200 @@ -315,6 +315,15 @@ memory. When in doubt, say "Y". +config DEVPHYSMEM + bool "/dev/physmem virtual device support" + default n + help + Say Y here if you want to support the /dev/physmem device. The + /dev/physmem device allows unprivileged access to physical memory + unused by the kernel. + When in doubt, say "N". + config NVRAM tristate "/dev/nvram support" depends on X86 || HAVE_ARCH_NVRAM_OPS @@ -422,3 +431,5 @@ driver include crash and makedumpfile. endmenu + +source "drivers/char/diag/Kconfig" diff -ruw linux-6.4/drivers/char/Makefile linux-6.4-fbx/drivers/char/Makefile --- linux-6.4/drivers/char/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/char/Makefile 2023-05-22 20:06:37.807682609 +0200 @@ -44,3 +44,5 @@ obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o + +obj-$(CONFIG_DIAG_CHAR) += diag/ diff -ruw linux-6.4/drivers/char/hw_random/Kconfig linux-6.4-fbx/drivers/char/hw_random/Kconfig --- linux-6.4/drivers/char/hw_random/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/char/hw_random/Kconfig 2023-05-22 20:30:14.537853935 +0200 @@ -98,6 +98,11 @@ If unsure, say Y. +config HW_RANDOM_BCM63XX + tristate "Broadcom BCM63xx Random Number Generator support" + depends on ARCH_BCMBCA || BCM63XX + default HW_RANDOM + config HW_RANDOM_IPROC_RNG200 tristate "Broadcom iProc/STB RNG200 support" depends on ARCH_BCM_IPROC || ARCH_BCM2835 || ARCH_BRCMSTB || COMPILE_TEST @@ -559,6 +564,13 @@ To compile this driver as a module, choose M here. The module will be called jh7110-trng. +config HW_RANDOM_QCOM + tristate "Qualcomm Random Number Generator Driver" + depends on ARCH_QCOM || COMPILE_TEST + help + This driver provides support for the Random Number + Generator hardware found on Qualcomm SoCs. + endif # HW_RANDOM config UML_RANDOM diff -ruw linux-6.4/drivers/char/hw_random/Makefile linux-6.4-fbx/drivers/char/hw_random/Makefile --- linux-6.4/drivers/char/hw_random/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/char/hw_random/Makefile 2023-05-22 20:30:14.537853935 +0200 @@ -30,6 +30,7 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o obj-$(CONFIG_HW_RANDOM_HISI) += hisi-rng.o obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o +obj-$(CONFIG_HW_RANDOM_BCM63XX) += bcm63xx-rng.o obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o @@ -48,3 +49,4 @@ obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o +obj-$(CONFIG_HW_RANDOM_QCOM) += qcom-rng.o diff -ruw linux-6.4/drivers/char/mem.c linux-6.4-fbx/drivers/char/mem.c --- linux-6.4/drivers/char/mem.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/char/mem.c 2023-05-22 20:06:37.819682928 +0200 @@ -28,6 +28,8 @@ #include #include #include +#include + #include #include @@ -402,6 +404,14 @@ return 0; } +static int mmap_physmem(struct file * file, struct vm_area_struct * vma) +{ + if (vma->vm_pgoff < max_pfn && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + return mmap_mem(file, vma); +} + static ssize_t read_port(struct file *file, char __user *buf, size_t count, loff_t *ppos) { @@ -643,6 +653,11 @@ return 0; } +static int open_physmem(struct inode * inode, struct file * filp) +{ + return 0; +} + #define zero_lseek null_lseek #define full_lseek null_lseek #define write_zero write_null @@ -697,6 +712,14 @@ .write = write_full, }; +static const struct file_operations __maybe_unused physmem_fops = { + .mmap = mmap_physmem, + .open = open_physmem, +#ifndef CONFIG_MMU + .get_unmapped_area = get_unmapped_area_mem, +#endif +}; + static const struct memdev { const char *name; umode_t mode; @@ -717,6 +740,9 @@ #ifdef CONFIG_PRINTK [11] = { "kmsg", 0644, &kmsg_fops, 0 }, #endif +#ifdef CONFIG_DEVPHYSMEM + [16] = { "physmem", 0, &physmem_fops, FMODE_UNSIGNED_OFFSET }, +#endif }; static int memory_open(struct inode *inode, struct file *filp) diff -ruw linux-6.4/drivers/clk/qcom/Kconfig linux-6.4-fbx/drivers/clk/qcom/Kconfig --- linux-6.4/drivers/clk/qcom/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/clk/qcom/Kconfig 2023-05-22 20:30:14.537853935 +0200 @@ -189,6 +189,12 @@ i2c, USB, SD/eMMC, etc. Select this for the root clock of ipq9574. +config IPQ_NSSCC_9574 + tristate "IPQ9574 NSS Clock Controller" + depends on IPQ_GCC_9574 + help + Support for NSS clock controller on ipq9574 devices. + config MSM_GCC_8660 tristate "MSM8660 Global Clock Controller" help diff -ruw linux-6.4/drivers/clk/qcom/Makefile linux-6.4-fbx/drivers/clk/qcom/Makefile --- linux-6.4/drivers/clk/qcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/clk/qcom/Makefile 2023-05-22 20:30:14.537853935 +0200 @@ -29,6 +29,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o diff -ruw linux-6.4/drivers/cpufreq/Kconfig linux-6.4-fbx/drivers/cpufreq/Kconfig --- linux-6.4/drivers/cpufreq/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/cpufreq/Kconfig 2023-05-22 20:06:38.023688355 +0200 @@ -311,5 +311,10 @@ This adds the CPUFreq driver support for Freescale QorIQ SoCs which are capable of changing the CPU's frequency dynamically. +config BCM63158_CPUFREQ + tristate "CPU frequency scaling driver for BCM63158 SoC" + depends on ARCH_BCMBCA + endif + endmenu diff -ruw linux-6.4/drivers/cpufreq/Makefile linux-6.4-fbx/drivers/cpufreq/Makefile --- linux-6.4/drivers/cpufreq/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/cpufreq/Makefile 2023-05-22 20:06:38.023688355 +0200 @@ -107,3 +107,5 @@ obj-$(CONFIG_SH_CPU_FREQ) += sh-cpufreq.o obj-$(CONFIG_SPARC_US2E_CPUFREQ) += sparc-us2e-cpufreq.o obj-$(CONFIG_SPARC_US3_CPUFREQ) += sparc-us3-cpufreq.o + +obj-$(CONFIG_BCM63158_CPUFREQ) += bcm63158-cpufreq.o diff -ruw linux-6.4/drivers/gpio/Kconfig linux-6.4-fbx/drivers/gpio/Kconfig --- linux-6.4/drivers/gpio/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/gpio/Kconfig 2023-12-05 13:51:11.322098873 +0100 @@ -1018,6 +1018,11 @@ enough to represent all pins, but the driver will assume a register layout for 64 pins (8 registers). +config GPIO_FBXGWR_PMU + tristate "Freebox PMU I2C GPIO expander" + depends on MFD_FBXGWR_PMU + select GPIOLIB_IRQCHIP + config GPIO_FXL6408 tristate "FXL6408 I2C GPIO expander" select GPIO_REGMAP diff -ruw linux-6.4/drivers/gpio/Makefile linux-6.4-fbx/drivers/gpio/Makefile --- linux-6.4/drivers/gpio/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/gpio/Makefile 2023-12-05 13:50:59.101765002 +0100 @@ -60,6 +60,7 @@ obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o +obj-$(CONFIG_GPIO_FBXGWR_PMU) += gpio-fbxgwr-pmu.o obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o obj-$(CONFIG_GPIO_FXL6408) += gpio-fxl6408.o obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o diff -ruw linux-6.4/drivers/hid/Kconfig linux-6.4-fbx/drivers/hid/Kconfig --- linux-6.4/drivers/hid/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/hid/Kconfig 2023-05-22 20:06:40.203746341 +0200 @@ -484,6 +484,11 @@ Adds support for side buttons of Xiaomi Mi Dual Mode Wireless Mouse Silent Edition. +config HID_FBX_REMOTE_AUDIO + tristate "Freebox BLE remote audio driver" + depends on HID && SND + select SND_PCM + config HID_GYRATION tristate "Gyration remote control" help diff -ruw linux-6.4/drivers/hid/Makefile linux-6.4-fbx/drivers/hid/Makefile --- linux-6.4/drivers/hid/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/hid/Makefile 2023-05-22 20:06:40.207746447 +0200 @@ -57,6 +57,7 @@ obj-$(CONFIG_HID_GOOGLE_HAMMER) += hid-google-hammer.o obj-$(CONFIG_HID_VIVALDI) += hid-vivaldi.o obj-$(CONFIG_HID_GT683R) += hid-gt683r.o +obj-$(CONFIG_HID_FBX_REMOTE_AUDIO) += hid-fbx-remote-audio.o obj-$(CONFIG_HID_GYRATION) += hid-gyration.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-kbd.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-mouse.o diff -ruw linux-6.4/drivers/hid/hid-quirks.c linux-6.4-fbx/drivers/hid/hid-quirks.c --- linux-6.4/drivers/hid/hid-quirks.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/hid/hid-quirks.c 2023-05-22 20:06:40.223746873 +0200 @@ -719,6 +719,7 @@ #if IS_ENABLED(CONFIG_HID_ZYDACRON) { HID_USB_DEVICE(USB_VENDOR_ID_ZYDACRON, USB_DEVICE_ID_ZYDACRON_REMOTE_CONTROL) }, #endif + { HID_BLUETOOTH_DEVICE(0x10eb, 0x0023) }, { } }; diff -ruw linux-6.4/drivers/hwmon/Kconfig linux-6.4-fbx/drivers/hwmon/Kconfig --- linux-6.4/drivers/hwmon/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/hwmon/Kconfig 2023-06-22 21:43:23.070921124 +0200 @@ -344,6 +344,10 @@ This driver can also be built as a module. If so, the module will be called fam15h_power. +config SENSORS_FBXGWR_PMU + tristate "Freebox GWR PMU hardware monitoring driver" + depends on MFD_FBXGWR_PMU + config SENSORS_APPLESMC tristate "Apple SMC (Motion sensor, light sensor, keyboard backlight)" depends on INPUT && X86 @@ -2359,6 +2363,17 @@ sensors monitor various telemetry data of different components on the card, e.g. board temperature, FPGA core temperature/voltage/current. +config SENSORS_KIRKWOOD_CORETEMP + tristate "Kirkwood core temperature censor" + depends on MACH_KIRKWOOD + +config SENSORS_LD6710_FBX + tristate "LD6710 hardware monitoring driver (as seen on Freebox hardware)" + depends on I2C + +config SENSORS_AP806 + tristate "Marvell AP806/CP110 hardware monitoring driver" + if ACPI comment "ACPI drivers" diff -ruw linux-6.4/drivers/hwmon/Makefile linux-6.4-fbx/drivers/hwmon/Makefile --- linux-6.4/drivers/hwmon/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/hwmon/Makefile 2023-06-22 21:43:23.074921233 +0200 @@ -74,6 +74,7 @@ obj-$(CONFIG_SENSORS_F71805F) += f71805f.o obj-$(CONFIG_SENSORS_F71882FG) += f71882fg.o obj-$(CONFIG_SENSORS_F75375S) += f75375s.o +obj-$(CONFIG_SENSORS_FBXGWR_PMU) += fbxgwr_pmu_hwmon.o obj-$(CONFIG_SENSORS_FAM15H_POWER) += fam15h_power.o obj-$(CONFIG_SENSORS_FSCHMD) += fschmd.o obj-$(CONFIG_SENSORS_FTSTEUTATES) += ftsteutates.o @@ -102,6 +103,7 @@ obj-$(CONFIG_SENSORS_K8TEMP) += k8temp.o obj-$(CONFIG_SENSORS_K10TEMP) += k10temp.o obj-$(CONFIG_SENSORS_LAN966X) += lan966x-hwmon.o +obj-$(CONFIG_SENSORS_LD6710_FBX) += ld6710-fbx.o obj-$(CONFIG_SENSORS_LINEAGE) += lineage-pem.o obj-$(CONFIG_SENSORS_LOCHNAGAR) += lochnagar-hwmon.o obj-$(CONFIG_SENSORS_LM63) += lm63.o @@ -218,6 +220,8 @@ obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o obj-$(CONFIG_SENSORS_XGENE) += xgene-hwmon.o +obj-$(CONFIG_SENSORS_KIRKWOOD_CORETEMP)+= kirkwood-coretemp.o +obj-$(CONFIG_SENSORS_AP806) += ap806-hwmon.o obj-$(CONFIG_SENSORS_OCC) += occ/ obj-$(CONFIG_SENSORS_PECI) += peci/ diff -ruw linux-6.4/drivers/hwmon/adt7475.c linux-6.4-fbx/drivers/hwmon/adt7475.c --- linux-6.4/drivers/hwmon/adt7475.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/hwmon/adt7475.c 2023-05-22 20:06:40.251747618 +0200 @@ -131,7 +131,19 @@ /* Macro to read the registers */ -#define adt7475_read(reg) i2c_smbus_read_byte_data(client, (reg)) +static inline s32 __adt7475_read(const struct i2c_client *client, u8 cmd) +{ + s32 ret; + + ret = i2c_smbus_read_byte_data(client, cmd); + if (ret < 0) { + printk("__adt7475_read error: %d\n", ret); + return 0; + } + return ret; +} + +#define adt7475_read(reg) __adt7475_read(client, (reg)) /* Macros to easily index the registers */ diff -ruw linux-6.4/drivers/i2c/busses/Kconfig linux-6.4-fbx/drivers/i2c/busses/Kconfig --- linux-6.4/drivers/i2c/busses/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/i2c/busses/Kconfig 2023-05-22 20:06:40.343750065 +0200 @@ -1433,6 +1433,10 @@ to SLIMpro (On chip coprocessor) mailbox mechanism. If unsure, say N. +config I2C_WP3 + tristate "Wintegra WP3 I2C controll" + depends on WINTEGRA_WINPATH3 + config SCx200_ACB tristate "Geode ACCESS.bus support" depends on X86_32 && PCI diff -ruw linux-6.4/drivers/i2c/busses/Makefile linux-6.4-fbx/drivers/i2c/busses/Makefile --- linux-6.4/drivers/i2c/busses/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/i2c/busses/Makefile 2023-05-22 20:06:40.343750065 +0200 @@ -129,6 +129,7 @@ obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o obj-$(CONFIG_I2C_GXP) += i2c-gxp.o +obj-$(CONFIG_I2C_WP3) += i2c-wp3.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o diff -ruw linux-6.4/drivers/i2c/i2c-core-base.c linux-6.4-fbx/drivers/i2c/i2c-core-base.c --- linux-6.4/drivers/i2c/i2c-core-base.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/i2c/i2c-core-base.c 2023-05-22 20:06:40.379751022 +0200 @@ -249,12 +249,14 @@ bri->set_sda(adap, scl); ndelay(RECOVERY_NDELAY / 2); + if (0) { if (scl) { ret = i2c_generic_bus_free(adap); if (ret == 0) break; } } + } /* If we can't check bus status, assume recovery worked */ if (ret == -EOPNOTSUPP) diff -ruw linux-6.4/drivers/input/misc/Kconfig linux-6.4-fbx/drivers/input/misc/Kconfig --- linux-6.4/drivers/input/misc/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/input/misc/Kconfig 2023-05-22 20:06:40.643758045 +0200 @@ -939,4 +939,9 @@ To compile this driver as a module, choose M here: the module will be called stpmic1_onkey. +config INPUT_SMSC_CAP1066 + tristate "SMSC CAP1066 capacitive sensor driver" + select I2C + select INPUT_POLLDEV + endif diff -ruw linux-6.4/drivers/input/misc/Makefile linux-6.4-fbx/drivers/input/misc/Makefile --- linux-6.4/drivers/input/misc/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/input/misc/Makefile 2023-05-22 20:06:40.643758045 +0200 @@ -90,3 +90,4 @@ obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_INPUT_IDEAPAD_SLIDEBAR) += ideapad_slidebar.o +obj-$(CONFIG_INPUT_SMSC_CAP1066) += smsc_cap1066.o diff -ruw linux-6.4/drivers/leds/Kconfig linux-6.4-fbx/drivers/leds/Kconfig --- linux-6.4/drivers/leds/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/leds/Kconfig 2023-11-27 19:13:52.966343373 +0100 @@ -328,6 +328,10 @@ defined as platform devices and/or OpenFirmware platform devices. The code to use these bindings can be selected below. +config LEDS_FBXGWR_PMU + tristate "Freebox GWR PMU LED controller" + depends on MFD_FBXGWR_PMU + config LEDS_LP3944 tristate "LED Support for N.S. LP3944 (Fun Light) I2C chip" depends on LEDS_CLASS @@ -710,6 +714,13 @@ LED controllers. They are I2C devices with multiple constant-current channels, each with independent 256-level PWM control. +config LEDS_IS31FL3299 + tristate "LED support for ISSI IS31FL3299 I2C LED controller" + depends on LEDS_CLASS && I2C && OF + select REGMAP_I2C + help + This option enables support for the IS31FL3299 LED driver. + config LEDS_SC27XX_BLTC tristate "LED support for the SC27xx breathing light controller" depends on LEDS_CLASS && MFD_SC27XX_PMIC @@ -859,6 +870,17 @@ This option enables support for the Power Button LED of Acer Iconia Tab A500. +config LEDS_LED1202 + tristate "LED support for STMicroElectronics LED1202" + depends on LEDS_CLASS && I2C && OF + select REGMAP_I2C + help + This option enables support for the LED1202 12-channel + LED driver. + + To compile this driver as a module, choose M here: the module + will be called leds-led1202. + source "drivers/leds/blink/Kconfig" comment "Flash and Torch LED drivers" diff -ruw linux-6.4/drivers/leds/Makefile linux-6.4-fbx/drivers/leds/Makefile --- linux-6.4/drivers/leds/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/leds/Makefile 2023-11-27 19:13:52.966343373 +0100 @@ -28,12 +28,14 @@ obj-$(CONFIG_LEDS_DA9052) += leds-da9052.o obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o obj-$(CONFIG_LEDS_GPIO_REGISTER) += leds-gpio-register.o +obj-$(CONFIG_LEDS_FBXGWR_PMU) += leds-fbxgwr-pmu.o obj-$(CONFIG_LEDS_HP6XX) += leds-hp6xx.o obj-$(CONFIG_LEDS_INTEL_SS4200) += leds-ss4200.o obj-$(CONFIG_LEDS_IP30) += leds-ip30.o obj-$(CONFIG_LEDS_IPAQ_MICRO) += leds-ipaq-micro.o obj-$(CONFIG_LEDS_IS31FL319X) += leds-is31fl319x.o obj-$(CONFIG_LEDS_IS31FL32XX) += leds-is31fl32xx.o +obj-$(CONFIG_LEDS_IS31FL3299) += leds-is31fl3299.o obj-$(CONFIG_LEDS_LM3530) += leds-lm3530.o obj-$(CONFIG_LEDS_LM3532) += leds-lm3532.o obj-$(CONFIG_LEDS_LM3533) += leds-lm3533.o @@ -85,6 +87,7 @@ obj-$(CONFIG_LEDS_WM831X_STATUS) += leds-wm831x-status.o obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o +obj-$(CONFIG_LEDS_LED1202) += leds-led1202.o # LED SPI Drivers obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o diff -ruw linux-6.4/drivers/media/dvb-core/dvb_frontend.c linux-6.4-fbx/drivers/media/dvb-core/dvb_frontend.c --- linux-6.4/drivers/media/dvb-core/dvb_frontend.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/media/dvb-core/dvb_frontend.c 2023-06-27 11:47:15.779859115 +0200 @@ -820,6 +820,7 @@ if (fe->exit != DVB_FE_DEVICE_REMOVED) fe->exit = DVB_FE_NORMAL_EXIT; mb(); + wake_up_all(&fepriv->events.wait_queue); if (!fepriv->thread) return; @@ -2755,6 +2756,9 @@ poll_wait(file, &fepriv->events.wait_queue, wait); + if (fe->exit) + return POLLERR | POLLHUP; + if (fepriv->events.eventw != fepriv->events.eventr) return (EPOLLIN | EPOLLRDNORM | EPOLLPRI); diff -ruw linux-6.4/drivers/media/rc/keymaps/Makefile linux-6.4-fbx/drivers/media/rc/keymaps/Makefile --- linux-6.4/drivers/media/rc/keymaps/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/media/rc/keymaps/Makefile 2023-05-22 20:06:41.083769748 +0200 @@ -103,6 +103,7 @@ rc-purpletv.o \ rc-pv951.o \ rc-rc6-mce.o \ + rc-rc6-freebox.o \ rc-real-audio-220-32-keys.o \ rc-reddo.o \ rc-snapstream-firefly.o \ diff -ruw linux-6.4/drivers/media/usb/dvb-usb/dib0700_devices.c linux-6.4-fbx/drivers/media/usb/dvb-usb/dib0700_devices.c --- linux-6.4/drivers/media/usb/dvb-usb/dib0700_devices.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/media/usb/dvb-usb/dib0700_devices.c 2023-05-22 20:06:41.115770599 +0200 @@ -3897,6 +3897,7 @@ DIBCOM_STK8096PVR, HAMA_DVBT_HYBRID, MICROSOFT_XBOX_ONE_TUNER, + DIBCOM_HOOK_DEFAULT_STK7770P, }; struct usb_device_id dib0700_usb_id_table[] = { @@ -3987,6 +3988,7 @@ DVB_USB_DEV(DIBCOM, DIBCOM_STK8096PVR), DVB_USB_DEV(HAMA, HAMA_DVBT_HYBRID), DVB_USB_DEV(MICROSOFT, MICROSOFT_XBOX_ONE_TUNER), + DVB_USB_DEV(DIBCOM, DIBCOM_HOOK_DEFAULT_STK7770P), { } }; @@ -5230,6 +5232,30 @@ { NULL }, }, }, + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, + .num_adapters = 1, + .adapter = { + { + DIB0700_NUM_FRONTENDS(1), + .fe = {{ + .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, + .pid_filter_count = 32, + .pid_filter = stk70x0p_pid_filter, + .pid_filter_ctrl = stk70x0p_pid_filter_ctrl, + .frontend_attach = stk7770p_frontend_attach, + .tuner_attach = dib7770p_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x02), + }}, + }, + }, + .num_device_descs = 1, + .devices = { + { "DiBcom STK7770P reference design no IR", + { &dib0700_usb_id_table[DIBCOM_HOOK_DEFAULT_STK7770P], NULL }, + { NULL }, + }, + }, }, }; diff -ruw linux-6.4/drivers/mfd/Kconfig linux-6.4-fbx/drivers/mfd/Kconfig --- linux-6.4/drivers/mfd/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mfd/Kconfig 2023-06-12 14:21:20.824611302 +0200 @@ -2052,6 +2052,24 @@ additional drivers must be enabled in order to use the functionality of the device. +config MFD_FBXGW7R_PANEL + tristate "Freebox fbxgw7r panel support" + depends on FB + depends on SPI_MASTER + depends on OF + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_DEFERRED_IO + +config MFD_FBXGWR_PMU + tristate "Freebox fbxgwr PMU" + depends on I2C + depends on OF + select MFD_CORE + select REGMAP_I2C + config MFD_WCD934X tristate "Support for WCD9340/WCD9341 Codec" depends on SLIMBUS diff -ruw linux-6.4/drivers/mfd/Makefile linux-6.4-fbx/drivers/mfd/Makefile --- linux-6.4/drivers/mfd/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mfd/Makefile 2023-06-12 14:21:20.824611302 +0200 @@ -270,6 +270,8 @@ obj-$(CONFIG_MFD_ATC260X) += atc260x-core.o obj-$(CONFIG_MFD_ATC260X_I2C) += atc260x-i2c.o +obj-$(CONFIG_MFD_FBXGW7R_PANEL) += fbxgw7r-panel.o +obj-$(CONFIG_MFD_FBXGWR_PMU) += fbxgwr-pmu.o rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o rsmu-spi-objs := rsmu_core.o rsmu_spi.o diff -ruw linux-6.4/drivers/misc/Kconfig linux-6.4-fbx/drivers/misc/Kconfig --- linux-6.4/drivers/misc/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/misc/Kconfig 2023-09-01 15:04:29.529632893 +0200 @@ -5,6 +5,9 @@ menu "Misc devices" +config WINTEGRA_MMAP + bool "wintegra mmap driver" + config SENSORS_LIS3LV02D tristate depends on INPUT @@ -403,6 +406,18 @@ To compile this driver as a module, choose M here: the module will be called vmw_balloon. +config INTELCE_PIC16PMU + tristate "PIC16 PMU, LED, hwmon support" + select INPUT_POLLDEV + select NEW_LEDS + select I2C + select HWMON + select ARCH_REQUIRE_GPIOLIB + help + Freebox v6 HD PIC16 PMU interface support, enables + control of the on-board LEDs and reports the power status, + reset status and button status. + config PCH_PHUB tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) PHUB" select GENERIC_NET_UTILS @@ -424,6 +439,11 @@ To compile this driver as a module, choose M here: the module will be called pch_phub. +config FBXSERIAL_OF + bool "read fbxserial through DT chosen node" + depends on OF + select ARCH_HAS_FBXSERIAL + config LATTICE_ECP3_CONFIG tristate "Lattice ECP3 FPGA bitstream configuration via SPI" depends on SPI && SYSFS @@ -538,6 +558,9 @@ Say N here unless you know what you are doing. +config DGASP + bool "dying gasp infrastructure" + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" @@ -555,4 +578,6 @@ source "drivers/misc/uacce/Kconfig" source "drivers/misc/pvpanic/Kconfig" source "drivers/misc/mchp_pci1xxxx/Kconfig" +source "drivers/misc/remoti/Kconfig" +source "drivers/misc/hdmi-cec/Kconfig" endmenu diff -ruw linux-6.4/drivers/misc/Makefile linux-6.4-fbx/drivers/misc/Makefile --- linux-6.4/drivers/misc/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/misc/Makefile 2023-09-01 15:04:29.529632893 +0200 @@ -3,6 +3,7 @@ # Makefile for misc devices that really don't fit anywhere else. # +obj-$(CONFIG_WINTEGRA_MMAP) += wintegra_mmap.o obj-$(CONFIG_IBM_ASM) += ibmasm/ obj-$(CONFIG_IBMVMC) += ibmvmc.o obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot.o @@ -21,7 +22,9 @@ obj-$(CONFIG_SENSORS_APDS990X) += apds990x.o obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o obj-$(CONFIG_KGDB_TESTS) += kgdbts.o +obj-$(CONFIG_FBXSERIAL_OF) += fbxserial_of.o obj-$(CONFIG_SGI_XP) += sgi-xp/ +obj-$(CONFIG_INTELCE_PIC16PMU) += pic16-pmu.o obj-$(CONFIG_SGI_GRU) += sgi-gru/ obj-$(CONFIG_SMPRO_ERRMON) += smpro-errmon.o obj-$(CONFIG_SMPRO_MISC) += smpro-misc.o @@ -39,6 +42,7 @@ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmw_balloon.o obj-$(CONFIG_PCH_PHUB) += pch_phub.o +obj-y += hdmi-cec/ obj-y += ti-st/ obj-y += lis3lv02d/ obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/ @@ -65,3 +69,5 @@ obj-$(CONFIG_VCPU_STALL_DETECTOR) += vcpu_stall_detector.o obj-$(CONFIG_TMR_MANAGER) += xilinx_tmr_manager.o obj-$(CONFIG_TMR_INJECT) += xilinx_tmr_inject.o +obj-y += remoti/ +obj-$(CONFIG_DGASP) += dgasp.o diff -ruw linux-6.4/drivers/misc/eeprom/Kconfig linux-6.4-fbx/drivers/misc/eeprom/Kconfig --- linux-6.4/drivers/misc/eeprom/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/misc/eeprom/Kconfig 2023-06-27 11:47:15.783859224 +0200 @@ -131,4 +131,8 @@ This driver can also be built as a module. If so, the module will be called ee1004. +config EEPROM_EE1004_RAW + tristate "SPD EEPROMs on DDR4 memory modules (non smbus)" + depends on I2C && SYSFS + endmenu diff -ruw linux-6.4/drivers/misc/eeprom/Makefile linux-6.4-fbx/drivers/misc/eeprom/Makefile --- linux-6.4/drivers/misc/eeprom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/misc/eeprom/Makefile 2023-03-09 16:41:54.887957334 +0100 @@ -8,3 +8,4 @@ obj-$(CONFIG_EEPROM_DIGSY_MTC_CFG) += digsy_mtc_eeprom.o obj-$(CONFIG_EEPROM_IDT_89HPESX) += idt_89hpesx.o obj-$(CONFIG_EEPROM_EE1004) += ee1004.o +obj-$(CONFIG_EEPROM_EE1004_RAW) += ee1004_raw.o diff -ruw linux-6.4/drivers/misc/eeprom/at24.c linux-6.4-fbx/drivers/misc/eeprom/at24.c --- linux-6.4/drivers/misc/eeprom/at24.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/misc/eeprom/at24.c 2023-05-22 20:06:41.207773046 +0200 @@ -594,7 +594,6 @@ bool full_power; struct regmap *regmap; bool writable; - u8 test_byte; int err; i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C); @@ -615,8 +614,10 @@ page_size = 1; flags = cdata->flags; +#ifndef CONFIG_NVMEM_IGNORE_RO if (device_property_present(dev, "read-only")) flags |= AT24_FLAG_READONLY; +#endif if (device_property_present(dev, "no-read-rollover")) flags |= AT24_FLAG_NO_RDROL; @@ -764,21 +765,6 @@ return PTR_ERR(at24->nvmem); } - /* - * Perform a one-byte test read to verify that the chip is functional, - * unless powering on the device is to be avoided during probe (i.e. - * it's powered off right now). - */ - if (full_power) { - err = at24_read(at24, 0, &test_byte, 1); - if (err) { - pm_runtime_disable(dev); - if (!pm_runtime_status_suspended(dev)) - regulator_disable(at24->vcc_reg); - return -ENODEV; - } - } - pm_runtime_idle(dev); if (writable) diff -ruw linux-6.4/drivers/mmc/core/block.c linux-6.4-fbx/drivers/mmc/core/block.c --- linux-6.4/drivers/mmc/core/block.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mmc/core/block.c 2023-06-27 11:47:15.783859224 +0200 @@ -2463,7 +2463,7 @@ md->disk->private_data = md; md->parent = parent; set_disk_ro(md->disk, md->read_only || default_ro); - if (area_type & (MMC_BLK_DATA_AREA_RPMB | MMC_BLK_DATA_AREA_BOOT)) + if (area_type & (MMC_BLK_DATA_AREA_RPMB)) md->disk->flags |= GENHD_FL_NO_PART; /* diff -ruw linux-6.4/drivers/mmc/host/Kconfig linux-6.4-fbx/drivers/mmc/host/Kconfig --- linux-6.4/drivers/mmc/host/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mmc/host/Kconfig 2023-05-22 20:06:41.243774004 +0200 @@ -997,7 +997,7 @@ config MMC_SDHCI_BRCMSTB tristate "Broadcom SDIO/SD/MMC support" - depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST + depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCMBCA || COMPILE_TEST depends on MMC_SDHCI_PLTFM select MMC_CQHCI default ARCH_BRCMSTB || BMIPS_GENERIC diff -ruw linux-6.4/drivers/mmc/host/sdhci-brcmstb.c linux-6.4-fbx/drivers/mmc/host/sdhci-brcmstb.c --- linux-6.4/drivers/mmc/host/sdhci-brcmstb.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mmc/host/sdhci-brcmstb.c 2023-05-22 20:06:41.255774323 +0200 @@ -30,7 +30,6 @@ #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 struct sdhci_brcmstb_priv { - void __iomem *cfg_regs; unsigned int flags; struct clk *base_clk; u32 base_freq_hz; @@ -183,6 +182,7 @@ { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, + { .compatible = "brcm,bcm63xx-sdhci", .data = &match_priv_7445 }, {}, }; @@ -289,13 +289,6 @@ match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; } - /* Map in the non-standard CFG registers */ - priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(priv->cfg_regs)) { - res = PTR_ERR(priv->cfg_regs); - goto err; - } - sdhci_get_of_property(pdev); res = mmc_of_parse(host->mmc); if (res) diff -ruw linux-6.4/drivers/mtd/Kconfig linux-6.4-fbx/drivers/mtd/Kconfig --- linux-6.4/drivers/mtd/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/Kconfig 2023-02-24 19:08:06.439275900 +0100 @@ -23,6 +23,9 @@ WARNING: some of the tests will ERASE entire MTD device which they test. Do not use these tests unless you really know what you do. +config MTD_ERASE_PRINTK + bool "write to kernel log when a block is erased" + menu "Partition parsers" source "drivers/mtd/parsers/Kconfig" endmenu diff -ruw linux-6.4/drivers/mtd/mtdchar.c linux-6.4-fbx/drivers/mtd/mtdchar.c --- linux-6.4/drivers/mtd/mtdchar.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/mtdchar.c 2023-06-27 11:47:15.791859441 +0200 @@ -168,6 +168,7 @@ { struct mtd_oob_ops ops = {}; + memset(&ops, 0, sizeof (ops)); ops.mode = MTD_OPS_RAW; ops.datbuf = kbuf; ops.oobbuf = NULL; @@ -262,6 +263,7 @@ { struct mtd_oob_ops ops = {}; + memset(&ops, 0, sizeof (ops)); ops.mode = MTD_OPS_RAW; ops.datbuf = kbuf; ops.oobbuf = NULL; @@ -947,6 +949,11 @@ erase->len = einfo32.length; } +#ifdef CONFIG_MTD_ERASE_PRINTK + printk(KERN_DEBUG "mtd: %s: ERASE offset=@%08llx\n", + mtd->name, erase->addr); +#endif + ret = mtd_erase(mtd, erase); kfree(erase); } diff -ruw linux-6.4/drivers/mtd/mtdcore.c linux-6.4-fbx/drivers/mtd/mtdcore.c --- linux-6.4/drivers/mtd/mtdcore.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/mtdcore.c 2023-05-22 20:06:41.279774962 +0200 @@ -308,6 +308,56 @@ } MTD_DEVICE_ATTR_RO(bbt_blocks); +static ssize_t mtd_nand_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mtd->nand_type); +} +static DEVICE_ATTR(nand_type, S_IRUGO, mtd_nand_type_show, NULL); + +static ssize_t mtd_nand_manufacturer_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mtd->nand_manufacturer); +} +static DEVICE_ATTR(nand_manufacturer, S_IRUGO, mtd_nand_manufacturer_show, NULL); + +static ssize_t mtd_nand_onfi_ecc_bits_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", mtd->onfi_ecc_bits); +} +static DEVICE_ATTR(onfi_ecc_bits, S_IRUGO, mtd_nand_onfi_ecc_bits_show, NULL); + +static ssize_t mtd_nand_onfi_model_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", + mtd->onfi_model ? mtd->onfi_model : "unknown"); +} +static DEVICE_ATTR(onfi_model, S_IRUGO, mtd_nand_onfi_model_show, NULL); + +static ssize_t mtd_nand_ids_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%02x%02x%02x%02x%02x%02x%02x%02x\n", + mtd->nand_ids[0], mtd->nand_ids[1], + mtd->nand_ids[2], mtd->nand_ids[3], + mtd->nand_ids[4], mtd->nand_ids[5], + mtd->nand_ids[6], mtd->nand_ids[7]); +} +static DEVICE_ATTR(nand_ids, S_IRUGO, mtd_nand_ids_show, NULL); + static struct attribute *mtd_attrs[] = { &dev_attr_type.attr, &dev_attr_flags.attr, @@ -326,6 +376,11 @@ &dev_attr_bad_blocks.attr, &dev_attr_bbt_blocks.attr, &dev_attr_bitflip_threshold.attr, + &dev_attr_nand_type.attr, + &dev_attr_nand_manufacturer.attr, + &dev_attr_onfi_ecc_bits.attr, + &dev_attr_onfi_model.attr, + &dev_attr_nand_ids.attr, NULL, }; ATTRIBUTE_GROUPS(mtd); diff -ruw linux-6.4/drivers/mtd/mtdpart.c linux-6.4-fbx/drivers/mtd/mtdpart.c --- linux-6.4/drivers/mtd/mtdpart.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/mtdpart.c 2023-05-22 20:06:41.279774962 +0200 @@ -68,6 +68,11 @@ child->oobsize = parent->oobsize; child->oobavail = parent->oobavail; child->subpage_sft = parent->subpage_sft; + child->nand_type = parent->nand_type; + child->nand_manufacturer = parent->nand_manufacturer; + child->onfi_ecc_bits = parent->onfi_ecc_bits; + child->onfi_model = parent->onfi_model; + memcpy(child->nand_ids, parent->nand_ids, 8); child->name = name; child->owner = parent->owner; diff -ruw linux-6.4/drivers/mtd/nand/raw/Kconfig linux-6.4-fbx/drivers/mtd/nand/raw/Kconfig --- linux-6.4/drivers/mtd/nand/raw/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/nand/raw/Kconfig 2023-05-22 20:06:41.283775068 +0200 @@ -12,6 +12,14 @@ comment "Raw/parallel NAND flash controllers" +config MTD_FORCE_BAD_BLOCK_ERASE + bool "Force erase on bad blocks (useful for bootloader parts)" + default n + help + Enable this option only when you need to force an erase on + blocks being marked as "bad" by Linux (i.e: other ECC/bad block + marker layout). + config MTD_NAND_DENALI tristate @@ -31,6 +39,18 @@ Enable the driver for NAND flash on platforms using a Denali NAND controller as a DT device. +config MTD_NAND_DENALI_FBX + tristate "NAND Denali controller support" + depends on PCI + select BCH_CONST_PARAMS + +if MTD_NAND_DENALI_FBX + config BCH_CONST_M + default 13 + config BCH_CONST_T + default 4 +endif + config MTD_NAND_AMS_DELTA tristate "Amstrad E3 NAND controller" depends on MACH_AMS_DELTA || COMPILE_TEST diff -ruw linux-6.4/drivers/mtd/nand/raw/Makefile linux-6.4-fbx/drivers/mtd/nand/raw/Makefile --- linux-6.4/drivers/mtd/nand/raw/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/nand/raw/Makefile 2023-05-22 20:06:41.283775068 +0200 @@ -8,6 +8,7 @@ obj-$(CONFIG_MTD_NAND_DENALI) += denali.o obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o +obj-$(CONFIG_MTD_NAND_DENALI_FBX) += denali_nand.o obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o diff -ruw linux-6.4/drivers/mtd/parsers/Kconfig linux-6.4-fbx/drivers/mtd/parsers/Kconfig --- linux-6.4/drivers/mtd/parsers/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/parsers/Kconfig 2023-05-22 20:06:41.307775706 +0200 @@ -96,6 +96,10 @@ two "firmware" partitions. Currently used firmware has to be detected using CFE environment variable. +config MTD_OF_PARTS_IGNORE_RO + bool "ignore read-only flag" + depends on MTD_OF_PARTS + config MTD_PARSER_IMAGETAG tristate "Parser for BCM963XX Image Tag format partitions" depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST @@ -220,3 +224,14 @@ partition map. This partition table contains real partition offsets, which may differ from device to device depending on the number and location of bad blocks on NAND. + +config MTD_FBX6HD_PARTS + tristate "Freebox V6 HD partitioning support" + help + Freebox V6 HD partitioning support + +config MTD_FBX6HD_PARTS_WRITE_ALL + bool "make all partitions writeable" + depends on MTD_FBX6HD_PARTS + help + Freebox V6 HD partitions support diff -ruw linux-6.4/drivers/mtd/parsers/Makefile linux-6.4-fbx/drivers/mtd/parsers/Makefile --- linux-6.4/drivers/mtd/parsers/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/parsers/Makefile 2023-05-22 20:06:41.307775706 +0200 @@ -16,3 +16,4 @@ obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o +obj-$(CONFIG_MTD_FBX6HD_PARTS) += fbx6hd-mtdparts.o diff -ruw linux-6.4/drivers/mtd/parsers/ofpart_core.c linux-6.4-fbx/drivers/mtd/parsers/ofpart_core.c --- linux-6.4/drivers/mtd/parsers/ofpart_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/parsers/ofpart_core.c 2023-05-22 20:06:41.307775706 +0200 @@ -157,8 +157,10 @@ partname = of_get_property(pp, "name", &len); parts[i].name = partname; +#ifndef CONFIG_MTD_OF_PARTS_IGNORE_RO if (of_get_property(pp, "read-only", &len)) parts[i].mask_flags |= MTD_WRITEABLE; +#endif if (of_get_property(pp, "lock", &len)) parts[i].mask_flags |= MTD_POWERUP_LOCK; diff -ruw linux-6.4/drivers/mtd/spi-nor/atmel.c linux-6.4-fbx/drivers/mtd/spi-nor/atmel.c --- linux-6.4/drivers/mtd/spi-nor/atmel.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/spi-nor/atmel.c 2023-05-22 20:06:41.311775813 +0200 @@ -202,6 +202,10 @@ .fixups = &atmel_nor_global_protection_fixups }, { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16) NO_SFDP_FLAGS(SECT_4K) }, + + /* Used on Freebox Gateways ... */ + { "at25f512b", INFO(0x1f6500, 0x1f65, 32 * 1024, 2) + FLAGS(ALT_PROBE_ATMEL) }, }; const struct spi_nor_manufacturer spi_nor_atmel = { diff -ruw linux-6.4/drivers/mtd/spi-nor/core.c linux-6.4-fbx/drivers/mtd/spi-nor/core.c --- linux-6.4/drivers/mtd/spi-nor/core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/spi-nor/core.c 2023-06-27 11:47:15.795859550 +0200 @@ -784,6 +784,18 @@ return spi_nor_wait_till_ready(nor); } +static void sst_ewrsr(struct spi_nor *nor) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_EWRSR, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + + BUG_ON(!nor->spimem); + spi_mem_exec_op(nor->spimem, &op); +} + /** * spi_nor_write_sr() - Write the Status Register. * @nor: pointer to 'struct spi_nor'. @@ -800,6 +812,9 @@ if (ret) return ret; + if (nor->info->flags & SST_EWRSR) + sst_ewrsr(nor); + if (nor->spimem) { struct spi_mem_op op = SPI_NOR_WRSR_OP(sr, len); @@ -2047,6 +2062,40 @@ return NULL; } +static const struct flash_info * +spi_nor_search_part_by_alt_id(const struct flash_info *parts, + unsigned int nparts, + const u32 id) + +{ + int i; + + for (i = 0; i < nparts; i++) { + const struct flash_info *info = &parts[i]; + if ((info->flags & ALT_PROBE) && (info->ext_id == id)) + return info; + } + + return NULL; +} + +static const struct flash_info * +spi_nor_search_part_by_atmel_id(const struct flash_info *parts, + unsigned int nparts, + const u32 id) + +{ + int i; + + for (i = 0; i < nparts; i++) { + const struct flash_info *info = &parts[i]; + if ((info->flags & ALT_PROBE_ATMEL) && (info->ext_id == id)) + return info; + } + + return NULL; +} + static const struct flash_info *spi_nor_detect(struct spi_nor *nor) { const struct flash_info *info; @@ -2081,6 +2130,80 @@ return info; } +static const struct flash_info *spi_nor_alt_read_id(struct spi_nor *nor) +{ + u8 *data = nor->bouncebuf; + u16 id; + int err; + size_t i; + const struct flash_info *info; + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID_ALT, 1), + SPI_MEM_OP_ADDR(3, 0, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(2, data, 1)); + + BUG_ON(!nor->spimem); + + err = spi_mem_exec_op(nor->spimem, &op); + if (err < 0) { + dev_err(nor->dev, "error %d reading alt ID\n", err); + return ERR_PTR(err); + } + + id = (data[1] << 8) | data[0]; + + for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { + info = spi_nor_search_part_by_alt_id(manufacturers[i]->parts, + manufacturers[i]->nparts, + id); + if (info) { + nor->manufacturer = manufacturers[i]; + return info; + } + } + + + dev_err(nor->dev, "unrecognized ALT id %04x\n", id); + return ERR_PTR(-ENODEV); +} + +static const struct flash_info *spi_nor_atmel_id(struct spi_nor *nor) +{ + u8 *data = nor->bouncebuf; + u16 id; + int err; + size_t i; + const struct flash_info *info; + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(0x15, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(2, data, 1)); + + BUG_ON(!nor->spimem); + + err = spi_mem_exec_op(nor->spimem, &op); + if (err < 0) { + dev_err(nor->dev, "error %d reading atmel ID\n", err); + return ERR_PTR(err); + } + id = (data[1] << 8) | data[0]; + + for (i = 0; i < ARRAY_SIZE(manufacturers); i++) { + info = spi_nor_search_part_by_atmel_id(manufacturers[i]->parts, + manufacturers[i]->nparts, + id); + if (info) { + nor->manufacturer = manufacturers[i]; + return info; + } + } + + dev_err(nor->dev, "unrecognized ATMEL id %04x\n", id); + return ERR_PTR(-ENODEV); +} + static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { @@ -3359,6 +3482,17 @@ return NULL; } +static void sst_write_enable(struct spi_nor *nor) +{ + u8 *pzero = nor->bouncebuf; + + spi_nor_write_enable(nor); + sst_ewrsr(nor); + + pzero[0] = 0; + spi_nor_write_sr(nor, pzero, 1); +} + static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, const char *name) { @@ -3377,6 +3511,12 @@ if (name && info->id_len) { const struct flash_info *jinfo; + jinfo = spi_nor_alt_read_id(nor); + if (IS_ERR(jinfo)) + /* try ATMEL */ + jinfo = spi_nor_atmel_id(nor); + if (IS_ERR(jinfo)) + /* try JEDEC */ jinfo = spi_nor_detect(nor); if (IS_ERR(jinfo)) { return jinfo; @@ -3503,6 +3643,9 @@ if (spi_nor_use_parallel_locking(nor)) init_waitqueue_head(&nor->rww.wait); + if (info->flags & SST_EWRSR) + sst_write_enable(nor); + /* * Configure the SPI memory: * - select op codes for (Fast) Read, Page Program and Sector Erase. diff -ruw linux-6.4/drivers/mtd/spi-nor/core.h linux-6.4-fbx/drivers/mtd/spi-nor/core.h --- linux-6.4/drivers/mtd/spi-nor/core.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/spi-nor/core.h 2023-05-22 20:06:41.311775813 +0200 @@ -500,6 +500,7 @@ */ struct flash_info { char *name; + uint32_t ext_id; u8 id[SPI_NOR_MAX_ID_LEN]; u8 id_len; unsigned sector_size; @@ -521,6 +522,9 @@ #define SPI_NOR_NO_FR BIT(8) #define SPI_NOR_QUAD_PP BIT(9) #define SPI_NOR_RWW BIT(10) +#define ALT_PROBE BIT(11) /* only match during alt_probe */ +#define ALT_PROBE_ATMEL BIT(12) /* only match during alt_probe_atmel */ +#define SST_EWRSR BIT(13) /* EWRSR opcode before WRSR */ u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) @@ -546,11 +550,13 @@ #define SPI_NOR_ID(_jedec_id, _ext_id) \ .id = { SPI_NOR_ID_3ITEMS(_jedec_id), SPI_NOR_ID_2ITEMS(_ext_id) }, \ - .id_len = !(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0)) + .id_len = !(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0)), \ + .ext_id = (_ext_id) #define SPI_NOR_ID6(_jedec_id, _ext_id) \ .id = { SPI_NOR_ID_3ITEMS(_jedec_id), SPI_NOR_ID_3ITEMS(_ext_id) }, \ - .id_len = 6 + .id_len = 6, \ + .ext_id = (_ext_id) #define SPI_NOR_GEOMETRY(_sector_size, _n_sectors, _n_banks) \ .sector_size = (_sector_size), \ diff -ruw linux-6.4/drivers/mtd/spi-nor/eon.c linux-6.4-fbx/drivers/mtd/spi-nor/eon.c --- linux-6.4/drivers/mtd/spi-nor/eon.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/spi-nor/eon.c 2023-05-22 20:06:41.311775813 +0200 @@ -29,6 +29,10 @@ PARSE_SFDP }, { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128) NO_SFDP_FLAGS(SECT_4K) }, + + /* Used on Freebox Gateways ... */ + { "en25f05", INFO(0x1c0500, 0x1c05, 64 * 1024, 1) + FLAGS(ALT_PROBE) NO_SFDP_FLAGS(SECT_4K) }, }; const struct spi_nor_manufacturer spi_nor_eon = { diff -ruw linux-6.4/drivers/mtd/spi-nor/macronix.c linux-6.4-fbx/drivers/mtd/spi-nor/macronix.c --- linux-6.4/drivers/mtd/spi-nor/macronix.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/spi-nor/macronix.c 2023-05-22 20:06:41.311775813 +0200 @@ -103,6 +103,10 @@ { "mx66u2g45g", INFO(0xc2253c, 0, 64 * 1024, 4096) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) FIXUP_FLAGS(SPI_NOR_4B_OPCODES) }, + + /* Used on Freebox Gateways ... */ + { "mx25l512", INFO(0xc20500, 0xc205, 64 * 1024, 1) + FLAGS(ALT_PROBE) NO_SFDP_FLAGS(SECT_4K) }, }; static void macronix_nor_default_init(struct spi_nor *nor) diff -ruw linux-6.4/drivers/mtd/spi-nor/sst.c linux-6.4-fbx/drivers/mtd/spi-nor/sst.c --- linux-6.4/drivers/mtd/spi-nor/sst.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/mtd/spi-nor/sst.c 2023-05-22 20:06:41.311775813 +0200 @@ -115,6 +115,9 @@ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_SWP_IS_VOLATILE) NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) .fixups = &sst26vf_nor_fixups }, + + /* Used on Freebox Gateways ... */ + { "sst25vf512a", INFO(0xbf4800, 0xbf48, 32 * 1024, 2) FLAGS(ALT_PROBE | SST_EWRSR) }, }; static int sst_nor_write(struct mtd_info *mtd, loff_t to, size_t len, diff -ruw linux-6.4/drivers/net/ethernet/Kconfig linux-6.4-fbx/drivers/net/ethernet/Kconfig --- linux-6.4/drivers/net/ethernet/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ethernet/Kconfig 2023-05-22 20:06:41.395778047 +0200 @@ -190,6 +190,7 @@ source "drivers/net/ethernet/via/Kconfig" source "drivers/net/ethernet/wangxun/Kconfig" source "drivers/net/ethernet/wiznet/Kconfig" +source "drivers/net/ethernet/wintegra/Kconfig" source "drivers/net/ethernet/xilinx/Kconfig" source "drivers/net/ethernet/xircom/Kconfig" diff -ruw linux-6.4/drivers/net/ethernet/Makefile linux-6.4-fbx/drivers/net/ethernet/Makefile --- linux-6.4/drivers/net/ethernet/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ethernet/Makefile 2023-05-22 20:06:41.395778047 +0200 @@ -100,6 +100,7 @@ obj-$(CONFIG_NET_VENDOR_VIA) += via/ obj-$(CONFIG_NET_VENDOR_WANGXUN) += wangxun/ obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/ +obj-$(CONFIG_NET_VENDOR_WINTEGRA) += wintegra/ obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/ obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/ obj-$(CONFIG_NET_VENDOR_SYNOPSYS) += synopsys/ diff -ruw linux-6.4/drivers/net/ethernet/broadcom/Kconfig linux-6.4-fbx/drivers/net/ethernet/broadcom/Kconfig --- linux-6.4/drivers/net/ethernet/broadcom/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/Kconfig 2023-05-22 20:06:41.431779005 +0200 @@ -68,6 +68,39 @@ This driver supports the ethernet MACs in the Broadcom 63xx MIPS chipset family (BCM63XX). +config BCM63XX_ENET_RUNNER + tristate "Broadcom 63xx (63138) runner ethernet support" + select MII + select FIXED_PHY + select PHYLIB + select BCM7XXX_PHY + select BROADCOM_PHY + select SOC_BCM63XX_RDP + +config BCM63158_SF2 + tristate "Broadcom 63158 SF2 support" + select MII + select PHYLINK + select BCM7XXX_PHY + select BROADCOM_PHY + select NET_DSA + select NET_DSA_TAG_BRCM_FBX + +config BCM63158_ENET_RUNNER + tristate "Broadcom 63158 runner ethernet support" + select MII + select PHYLINK + select SOC_BCM63XX_XRDP + +config BCM63158_ENET_RUNNER_FF + bool "fastpath support for freebox boards" + depends on BCM63158_ENET_RUNNER + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config BCMGENET tristate "Broadcom GENET internal MAC support" depends on HAS_IOMEM diff -ruw linux-6.4/drivers/net/ethernet/broadcom/Makefile linux-6.4-fbx/drivers/net/ethernet/broadcom/Makefile --- linux-6.4/drivers/net/ethernet/broadcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/Makefile 2023-03-09 15:06:11.356234011 +0100 @@ -17,3 +17,5 @@ obj-$(CONFIG_BGMAC_PLATFORM) += bgmac-platform.o obj-$(CONFIG_SYSTEMPORT) += bcmsysport.o obj-$(CONFIG_BNXT) += bnxt/ +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_enet_runner/ +obj-y += bcm63158/ diff -ruw linux-6.4/drivers/net/ethernet/marvell/Kconfig linux-6.4-fbx/drivers/net/ethernet/marvell/Kconfig --- linux-6.4/drivers/net/ethernet/marvell/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ethernet/marvell/Kconfig 2023-05-22 20:06:41.719786665 +0200 @@ -23,6 +23,7 @@ depends on INET select PHYLIB select MVMDIO + select MII help This driver supports the gigabit ethernet MACs in the Marvell Discovery PPC/MIPS chipset family (MV643XX) and @@ -31,6 +32,15 @@ Some boards that use the Discovery chipset are the Momenco Ocelot C and Jaguar ATX and Pegasos II. +config MV643XX_ETH_FBX_FF + bool "fastpath support for freebox boards" + depends on MV643XX_ETH + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config MVMDIO tristate "Marvell MDIO interface support" depends on HAS_IOMEM @@ -90,6 +100,7 @@ select MVMDIO select PHYLINK select PAGE_POOL + select MII help This driver supports the network interface units in the Marvell ARMADA 375, 7K and 8K SoCs. @@ -99,6 +110,15 @@ depends on (PTP_1588_CLOCK = y && MVPP2 = y) || \ (PTP_1588_CLOCK && MVPP2 = m) +config MVPP2_FBX_FF + bool "fastpath support for freebox boards" + depends on MVPP2 + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config PXA168_ETH tristate "Marvell pxa168 ethernet support" depends on HAS_IOMEM diff -ruw linux-6.4/drivers/net/ethernet/qualcomm/Kconfig linux-6.4-fbx/drivers/net/ethernet/qualcomm/Kconfig --- linux-6.4/drivers/net/ethernet/qualcomm/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ethernet/qualcomm/Kconfig 2023-05-22 20:30:14.537853935 +0200 @@ -62,5 +62,6 @@ Precision Clock Synchronization Protocol. source "drivers/net/ethernet/qualcomm/rmnet/Kconfig" +source "drivers/net/ethernet/qualcomm/ipq95xx/Kconfig" endif # NET_VENDOR_QUALCOMM diff -ruw linux-6.4/drivers/net/ethernet/qualcomm/Makefile linux-6.4-fbx/drivers/net/ethernet/qualcomm/Makefile --- linux-6.4/drivers/net/ethernet/qualcomm/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ethernet/qualcomm/Makefile 2023-05-22 20:30:14.537853935 +0200 @@ -12,3 +12,4 @@ obj-y += emac/ obj-$(CONFIG_RMNET) += rmnet/ +obj-y += ipq95xx/ diff -ruw linux-6.4/drivers/net/mdio/of_mdio.c linux-6.4-fbx/drivers/net/mdio/of_mdio.c --- linux-6.4/drivers/net/mdio/of_mdio.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/mdio/of_mdio.c 2023-05-31 17:11:03.417680605 +0200 @@ -173,6 +173,8 @@ mdio->reset_post_delay_us = 0; of_property_read_u32(np, "reset-post-delay-us", &mdio->reset_post_delay_us); + mdio->keep_broken_phy = of_property_read_bool(np, "keep-broken-phy"); + /* Register the MDIO bus */ rc = __mdiobus_register(mdio, owner); if (rc) diff -ruw linux-6.4/drivers/net/phy/Kconfig linux-6.4-fbx/drivers/net/phy/Kconfig --- linux-6.4/drivers/net/phy/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/Kconfig 2023-05-31 17:11:03.417680605 +0200 @@ -309,6 +309,12 @@ Currently supports the AR8030, AR8031, AR8033, AR8035 and internal QCA8337(Internal qca8k PHY) model +config QCA807X_PHY + tristate "Qualcomm QCA870x PHYs" + +config QCA8084_PHY + tristate "Qualcomm QCA8084 Quad-PHY" + config QSEMI_PHY tristate "Quality Semiconductor PHYs" help diff -ruw linux-6.4/drivers/net/phy/Makefile linux-6.4-fbx/drivers/net/phy/Makefile --- linux-6.4/drivers/net/phy/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/Makefile 2023-05-31 17:11:03.417680605 +0200 @@ -82,7 +82,13 @@ obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o +obj-$(CONFIG_QCA807X_PHY) += qca807x.o +obj-$(CONFIG_QCA8084_PHY) += qca8084.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o +realtek-objs += realtek.o +ifdef CONFIG_HWMON +realtek-objs += realtek-hwmon.o +endif obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_RENESAS_PHY) += uPD60620.o obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o diff -ruw linux-6.4/drivers/net/phy/aquantia_main.c linux-6.4-fbx/drivers/net/phy/aquantia_main.c --- linux-6.4/drivers/net/phy/aquantia_main.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/aquantia_main.c 2023-05-22 20:30:14.541854042 +0200 @@ -12,6 +12,7 @@ #include #include #include +#include #include "aquantia.h" @@ -20,6 +21,7 @@ #define PHY_ID_AQR105 0x03a1b4a2 #define PHY_ID_AQR106 0x03a1b4d0 #define PHY_ID_AQR107 0x03a1b4e0 +#define PHY_ID_AQR112C 0x31c31d12 #define PHY_ID_AQCS109 0x03a1b5c2 #define PHY_ID_AQR405 0x03a1b4b0 #define PHY_ID_AQR112 0x03a1b662 @@ -37,6 +39,9 @@ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 +#define MDIO_PHYXS_VEND_PROV2 0xC441 +#define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3) + #define MDIO_AN_VEND_PROV 0xc400 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) @@ -112,6 +117,27 @@ #define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1 #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2 +#define VEND1_GLOBAL_MAILBOX_CONTROL 0x0200 +#define VEND1_GLOBAL_MAILBOX_EXECUTE BIT(15) +#define VEND1_GLOBAL_MAILBOX_WRITE BIT(14) +#define VEND1_GLOBAL_MAILBOX_RESET_CRC BIT(12) +#define VEND1_GLOBAL_MAILBOX_BUSY BIT(8) + +#define VEND1_GLOBAL_MAILBOX_CRC 0x0201 + +#define VEND1_GLOBAL_MAILBOX_ADDR_MSW 0x0202 +#define VEND1_GLOBAL_MAILBOX_ADDR_LSW 0x0203 + +#define VEND1_GLOBAL_MAILBOX_DATA_MSW 0x0204 +#define VEND1_GLOBAL_MAILBOX_DATA_LSW 0x0205 + +#define VEND1_GLOBAL_UP_CONTROL 0xc001 +#define VEND1_GLOBAL_UP_RESET BIT(15) +#define VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE BIT(6) +#define VEND1_GLOBAL_UP_RUN_STALL BIT(0) + +#define VEND1_GLOBAL_FAULT 0xc850 + #define VEND1_GLOBAL_RSVD_STAT1 0xc885 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) @@ -152,6 +178,46 @@ #define AQR107_OP_IN_PROG_SLEEP 1000 #define AQR107_OP_IN_PROG_TIMEOUT 100000 +/* registers in MDIO_MMD_VEND1 region */ +#define AQUANTIA_VND1_GLOBAL_SC 0x000 +#define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb) + +/* global start rate, the protocol associated with this speed is used by default + * on SI. + */ +#define AQUANTIA_VND1_GSTART_RATE 0x31a +#define AQUANTIA_VND1_GSTART_RATE_OFF 0 +#define AQUANTIA_VND1_GSTART_RATE_100M 1 +#define AQUANTIA_VND1_GSTART_RATE_1G 2 +#define AQUANTIA_VND1_GSTART_RATE_10G 3 +#define AQUANTIA_VND1_GSTART_RATE_2_5G 4 +#define AQUANTIA_VND1_GSTART_RATE_5G 5 + +/* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */ +#define AQUANTIA_VND1_GSYSCFG_BASE 0x31b +#define AQUANTIA_VND1_GSYSCFG_100M 0 +#define AQUANTIA_VND1_GSYSCFG_1G 1 +#define AQUANTIA_VND1_GSYSCFG_2_5G 2 +#define AQUANTIA_VND1_GSYSCFG_5G 3 +#define AQUANTIA_VND1_GSYSCFG_10G 4 + +/* addresses of memory segments in the phy */ +#define DRAM_BASE_ADDR 0x3FFE0000 +#define IRAM_BASE_ADDR 0x40000000 + +/* firmware image format constants */ +#define VERSION_STRING_SIZE 0x40 +#define VERSION_STRING_OFFSET 0x0200 +#define HEADER_OFFSET 0x300 + +struct aqr_fw_header { + u8 padding[4]; + u8 iram_offset[3]; + u8 iram_size[3]; + u8 dram_offset[3]; + u8 dram_size[3]; +}; + struct aqr107_hw_stat { const char *name; int reg; @@ -556,7 +622,7 @@ build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); - phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", + phydev_info(phydev, "FW %u.%u, Build %u, Provisioning %u\n", fw_major, fw_minor, build_id, prov_id); } @@ -586,6 +652,482 @@ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); } +static const u16 _crc16_lookuptable[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + +static u16 crc16_ccitt(u16 crc, const u8 *buf, size_t len) +{ + while (len--) { + crc = ((crc << 8) ^ _crc16_lookuptable[((crc >> 8) ^ + ((*buf++) & 0x00FF))]); + } + return crc; +} + +/* load data into the phy's memory */ +static int aqr112_load_chunk(struct phy_device *phydev, uint32_t addr, + const uint8_t *data, size_t len) +{ + u16 crc = 0; + int up_crc; + size_t pos; + int err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_CONTROL, + VEND1_GLOBAL_MAILBOX_RESET_CRC); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_ADDR_MSW, addr >> 16); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_ADDR_LSW, addr & 0xfffc); + if (err < 0) + return err; + + for (pos = 0; pos < len; pos += min_t(u32, sizeof(u32), len - pos)) { + u32 word = 0; + + memcpy(&word, &data[pos], min_t(u32, sizeof(u32), len - pos)); + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_DATA_MSW, + word >> 16); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_DATA_LSW, + word & 0xffff); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_CONTROL, + (VEND1_GLOBAL_MAILBOX_EXECUTE | + VEND1_GLOBAL_MAILBOX_WRITE)); + if (err < 0) + return err; + + /* keep a big endian CRC to match the phy processor */ + word = cpu_to_be32(word); + crc = crc16_ccitt(crc, (uint8_t *)&word, sizeof(word)); + } + + up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_CRC); + if (up_crc < 0) + return up_crc; + + if (crc != up_crc) { + dev_err(&phydev->mdio.dev, + "crc mismatch: calculated 0x%04hx phy 0x%04hx\n", + crc, up_crc); + return -EIO; + } + return 0; +} + +static u32 unpack_u24(const u8 *data) +{ + return (data[2] << 16) + (data[1] << 8) + data[0]; +} + +static int aqr_upload_firmware(struct phy_device *phydev, + const char *name) +{ + struct device *dev = &phydev->mdio.dev; + const struct firmware *fw; + const struct aqr_fw_header *header; + char file_name[64]; + char version[VERSION_STRING_SIZE + 1]; + u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size; + u16 calculated_crc, read_crc; + int ret; + + scnprintf(file_name, sizeof (file_name), "aquantia_phy/%s.uc", name); + ret = request_firmware_direct(&fw, file_name, dev); + if (ret) { + dev_err(dev, "failed to load firmware %s, ret: %d\n", + file_name, ret); + return ret; + } + + if (fw->size < 16) { + dev_err(dev, "firmware too small\n"); + ret = -EINVAL; + goto fail; + } + + read_crc = (fw->data[fw->size - 2] << 8) | fw->data[fw->size - 1]; + calculated_crc = crc16_ccitt(0, fw->data, fw->size - 2); + if (read_crc != calculated_crc) { + dev_err(dev, "bad firmware crc: file 0x%04x " + "calculated 0x%04x\n", + read_crc, calculated_crc); + ret = -EINVAL; + goto fail; + } + + /* Find the DRAM and IRAM sections within the firmware file. */ + primary_offset = ((fw->data[9] & 0xf) << 8 | fw->data[8]) << 12; + header = (const struct aqr_fw_header *) + &fw->data[primary_offset + HEADER_OFFSET]; + + iram_offset = primary_offset + unpack_u24(header->iram_offset); + iram_size = unpack_u24(header->iram_size); + + dram_offset = primary_offset + unpack_u24(header->dram_offset); + dram_size = unpack_u24(header->dram_size); + + strlcpy(version, + (char *)&fw->data[dram_offset + VERSION_STRING_OFFSET], + VERSION_STRING_SIZE); + version[VERSION_STRING_SIZE] = 0; + + dev_info(dev, "loading firmare version '%s'...\n", version); + + /* stall the microcprocessor */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_UP_CONTROL, + (VEND1_GLOBAL_UP_RUN_STALL | + VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE)); + if (ret < 0) + goto fail; + + ret = aqr112_load_chunk(phydev, DRAM_BASE_ADDR, + &fw->data[dram_offset], + dram_size); + if (ret) + goto fail; + + ret = aqr112_load_chunk(phydev, IRAM_BASE_ADDR, + &fw->data[iram_offset], + iram_size); + if (ret) + goto fail; + + /* make sure soft reset and low power mode are clear */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0, 0); + if (ret) + goto fail; + + /* Release the microprocessor. UP_RESET must be held for 100 usec. */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_UP_CONTROL, + (VEND1_GLOBAL_UP_RUN_STALL | + VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE | + VEND1_GLOBAL_UP_RESET)); + if (ret) + goto fail; + + msleep(10); + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_UP_CONTROL, + VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE); + if (ret) + goto fail; + + ret = 0; + +fail: + release_firmware(fw); + return ret; +} + +static int aqr112_config_init(struct phy_device *phydev) +{ + int ret; + + /* Check that the PHY interface type is compatible */ + if (phydev->interface != PHY_INTERFACE_MODE_NA && + phydev->interface != PHY_INTERFACE_MODE_SGMII && + phydev->interface != PHY_INTERFACE_MODE_2500BASEX) { + phydev_err(phydev, "requested interface mode not supp\n"); + return -ENODEV; + } + + ret = aqr_upload_firmware(phydev, "aqr112"); + if (ret) + return ret; + + aqr107_wait_reset_complete(phydev); + aqr107_chip_info(phydev); + + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); +} + +static int aqr112_get_features(struct phy_device *phydev) +{ + int ret; + + ret = genphy_c45_pma_read_abilities(phydev); + if (ret) + return ret; + + phy_set_max_speed(phydev, SPEED_2500); + return 0; +} + +static void dump_rate_config(struct phy_device *phydev, + const char *str, u32 val) +{ + phydev_info(phydev, + "cfg %s: " + "serdes_mode:%u aneg:%d training:%d rstt:%d ra:%d\n", + str, + val & 0x7, + (val >> 3) & 0x1, + (val >> 4) & 0x1, + (val >> 5) & 0x1, + (val >> 7) & 0x3); +} + +static void dump_rates_config(struct phy_device *phydev) +{ + dump_rate_config(phydev, "100M", phy_read_mmd(phydev, 0x1e, 0x31b)); + dump_rate_config(phydev, "1G ", phy_read_mmd(phydev, 0x1e, 0x31c)); + dump_rate_config(phydev, "2.5G", phy_read_mmd(phydev, 0x1e, 0x31d)); + dump_rate_config(phydev, "5G ", phy_read_mmd(phydev, 0x1e, 0x31e)); + dump_rate_config(phydev, "10G ", phy_read_mmd(phydev, 0x1e, 0x31f)); +} + +#define SERDES_MODE_XFI 0 +#define SERDES_MODE_XAUI 1 +#define SERDES_MODE_RXAUI 2 +#define SERDES_MODE_SGMII 3 +#define SERDES_MODE_OCSGMII 4 +#define SERDES_MODE_LOW_POWER 5 + +#define RA_METHOD_NONE 0 +#define RA_METHOD_USX 1 +#define RA_METHOD_PAUSE 2 + +enum system_if_rate { + SIF_RATE_100, + SIF_RATE_1G, + SIF_RATE_2_5G, + SIF_RATE_5G, + SIF_RATE_10G, + SIF_RATE_MAX, +}; + +struct system_if_cfg { + bool used; + u32 serdes_mode; + bool autoneg_en; + bool training_en; + bool serdes_rst_transition_en; + bool serdes_silence_en; + u32 ra_method; +}; + +static u32 gen_system_if_cfg(const struct system_if_cfg *cfg) +{ + u32 val; + + if (!cfg->used) + return (SERDES_MODE_LOW_POWER << 0); + + val = cfg->serdes_mode << 0; + if (cfg->autoneg_en) + val |= (1 << 3); + if (cfg->training_en) + val |= (1 << 4); + if (cfg->serdes_rst_transition_en) + val |= (1 << 5); + if (cfg->serdes_silence_en) + val |= (1 << 6); + val |= (cfg->ra_method << 7); + return val; +} + +static int aqr113_config_init(struct phy_device *phydev) +{ + struct system_if_cfg scfgs[SIF_RATE_MAX]; + bool use_inband_aneg; + int ret, val; + + /* Check that the PHY interface type is compatible */ + if (phydev->interface != PHY_INTERFACE_MODE_SGMII && + phydev->interface != PHY_INTERFACE_MODE_2500BASEX && + phydev->interface != PHY_INTERFACE_MODE_XGMII && + phydev->interface != PHY_INTERFACE_MODE_USXGMII && + phydev->interface != PHY_INTERFACE_MODE_10GKR && + phydev->interface != PHY_INTERFACE_MODE_10GBASER) + return -ENODEV; + + /* check if a valid firmware is loaded */ + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); + if (!val) { + ret = aqr_upload_firmware(phydev, "aqr113"); + if (ret) + return ret; + } + + ret = aqr107_wait_reset_complete(phydev); + if (ret) { + phydev_err(phydev, "phy firmware load timeout\n"); + return -ENODEV; + } + + aqr107_chip_info(phydev); + + /* set PHY in low power mode so we can configure protocols */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, + AQUANTIA_VND1_GLOBAL_SC, + AQUANTIA_VND1_GLOBAL_SC_LP); + msleep(10); + + /* set the default rate to enable the SI link */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE, + AQUANTIA_VND1_GSTART_RATE_OFF); + + /* unfortunately we don't know if phylink uses MLO_AN_INBAND + * or MLO_AN_PHY from here, so this needs to be tuned + * manually, depending on the device tree node managed = + * "in-band-status" presence */ + use_inband_aneg = false; + + memset(scfgs, 0, sizeof (scfgs)); + switch (phydev->interface) { + case PHY_INTERFACE_MODE_SGMII: + scfgs[SIF_RATE_100] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_SGMII, + .autoneg_en = use_inband_aneg, + }; + scfgs[SIF_RATE_1G] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_SGMII, + .autoneg_en = use_inband_aneg, + }; + break; + case PHY_INTERFACE_MODE_2500BASEX: + scfgs[SIF_RATE_2_5G] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_OCSGMII, + .autoneg_en = false, + }; + break; + case PHY_INTERFACE_MODE_10GBASER: + scfgs[SIF_RATE_10G] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_XFI, + .autoneg_en = false, + }; + break; + case PHY_INTERFACE_MODE_10GKR: + scfgs[SIF_RATE_10G] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_XFI, + .autoneg_en = true, + }; + break; + case PHY_INTERFACE_MODE_USXGMII: + scfgs[SIF_RATE_10G] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_XFI, + .ra_method = RA_METHOD_USX, + .autoneg_en = false, + }; + scfgs[SIF_RATE_2_5G] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_XFI, + .ra_method = RA_METHOD_USX, + .autoneg_en = false, + }; + scfgs[SIF_RATE_1G] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_XFI, + .ra_method = RA_METHOD_USX, + .autoneg_en = false, + }; + scfgs[SIF_RATE_100] = (struct system_if_cfg) { + .used = true, + .serdes_mode = SERDES_MODE_XFI, + .ra_method = RA_METHOD_USX, + .autoneg_en = false, + }; + break; + default: + break; + } + + phy_write_mmd(phydev, MDIO_MMD_VEND1, + AQUANTIA_VND1_GSYSCFG_BASE + AQUANTIA_VND1_GSYSCFG_100M, + gen_system_if_cfg(&scfgs[SIF_RATE_100])); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, + AQUANTIA_VND1_GSYSCFG_BASE + AQUANTIA_VND1_GSYSCFG_1G, + gen_system_if_cfg(&scfgs[SIF_RATE_1G])); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, + AQUANTIA_VND1_GSYSCFG_BASE + AQUANTIA_VND1_GSYSCFG_2_5G, + gen_system_if_cfg(&scfgs[SIF_RATE_2_5G])); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, + AQUANTIA_VND1_GSYSCFG_BASE + AQUANTIA_VND1_GSYSCFG_5G, + gen_system_if_cfg(&scfgs[SIF_RATE_5G])); + + phy_write_mmd(phydev, MDIO_MMD_VEND1, + AQUANTIA_VND1_GSYSCFG_BASE + AQUANTIA_VND1_GSYSCFG_10G, + gen_system_if_cfg(&scfgs[SIF_RATE_10G])); + + val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_PROV2); + if (phydev->interface == PHY_INTERFACE_MODE_USXGMII && + use_inband_aneg) + val |= MDIO_PHYXS_VEND_PROV2_USX_AN; + else + val &= ~MDIO_PHYXS_VEND_PROV2_USX_AN; + + phy_write_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_PROV2, val); + + /* wake PHY back up */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0); + mdelay(10); + + dump_rates_config(phydev); + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); +} + static int aqcs109_config_init(struct phy_device *phydev) { int ret; @@ -776,6 +1318,20 @@ .link_change_notify = aqr107_link_change_notify, }, { + PHY_ID_MATCH_MODEL(PHY_ID_AQR112C), + .name = "Aquantia AQR112C", + .probe = aqr107_probe, + .config_init = aqr112_config_init, + .config_aneg = aqr_config_aneg, + .read_status = aqr107_read_status, + .get_features = aqr112_get_features, + .suspend = aqr107_suspend, + .resume = aqr107_resume, + .get_sset_count = aqr107_get_sset_count, + .get_strings = aqr107_get_strings, + .get_stats = aqr107_get_stats, +}, +{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), .name = "Aquantia AQCS109", .probe = aqr107_probe, @@ -843,7 +1399,7 @@ .name = "Aquantia AQR113C", .probe = aqr107_probe, .get_rate_matching = aqr107_get_rate_matching, - .config_init = aqr107_config_init, + .config_init = aqr113_config_init, .config_aneg = aqr_config_aneg, .config_intr = aqr_config_intr, .handle_interrupt = aqr_handle_interrupt, @@ -867,6 +1423,7 @@ { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, diff -ruw linux-6.4/drivers/net/phy/bcm7xxx.c linux-6.4-fbx/drivers/net/phy/bcm7xxx.c --- linux-6.4/drivers/net/phy/bcm7xxx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/bcm7xxx.c 2023-05-22 20:06:42.123797411 +0200 @@ -45,6 +45,7 @@ struct bcm7xxx_phy_priv { u64 *stats; + bool printed; }; static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) @@ -142,6 +143,7 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev) { + struct bcm7xxx_phy_priv *priv = phydev->priv; u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); u8 count; @@ -153,8 +155,11 @@ if (rev == 0) rev = phydev->phy_id & ~phydev->drv->phy_id_mask; - pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n", + if (!priv->printed) { + pr_info("%s: %s PHY revision: 0x%02x, patch: %d\n", phydev_name(phydev), phydev->drv->name, rev, patch); + priv->printed = true; + } /* Dummy read to a register to workaround an issue upon reset where the * internal inverter may not allow the first MDIO transaction to pass @@ -387,11 +392,15 @@ static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev) { + struct bcm7xxx_phy_priv *priv = phydev->priv; u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; int ret = 0; - pr_info_once("%s: %s PHY revision: 0x%02x\n", + if (!priv->printed) { + pr_info("%s: %s PHY revision: 0x%02x\n", phydev_name(phydev), phydev->drv->name, rev); + priv->printed = true; + } /* Dummy read to a register to workaround a possible issue upon reset * where the internal inverter may not allow the first MDIO transaction @@ -917,6 +926,7 @@ BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"), BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"), BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"), + BCM7XXX_28NM_GPHY(PHY_ID_BCM63138, "Broadcom BCM63138"), BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"), BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"), BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"), @@ -946,6 +956,7 @@ { PHY_ID_BCM7435, 0xfffffff0, }, { PHY_ID_BCM7445, 0xfffffff0, }, { PHY_ID_BCM7712, 0xfffffff0, }, + { PHY_ID_BCM63138, 0xfffffff0, }, { } }; diff -ruw linux-6.4/drivers/net/phy/broadcom.c linux-6.4-fbx/drivers/net/phy/broadcom.c --- linux-6.4/drivers/net/phy/broadcom.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/broadcom.c 2023-05-22 20:06:42.127797518 +0200 @@ -16,6 +16,7 @@ #include #include #include +#include #define BRCM_PHY_MODEL(phydev) \ ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask) @@ -862,6 +863,477 @@ bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret); } +#define BRCM_MIIEXT_BANK 0x1f +# define BRCM_MIIEXT_BANK_MASK 0xfff0 +# define BRCM_MIIEXT_ADDR_RANGE 0xffe0 +# define BRCM_MIIEXT_DEF_BANK 0x8000 +#define BRCM_MIIEXT_OFFSET 0x10 +# define BRCM_MIIEXT_OFF_MASK 0xf + +static int bcm63138_ephy_read(struct phy_device *phydev, int reg) +{ + uint32_t bank; + uint32_t offset; + int val; + int error; + + if (reg < 0x20) + return phy_read(phydev, reg); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = phy_write(phydev, BRCM_MIIEXT_BANK, bank); + val = phy_read(phydev, offset); + if (val < 0) + error = val; + + error |= phy_write(phydev, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + return (error < 0) ? error : val; +} + +static int bcm63138_ephy_write(struct phy_device *phydev, int reg, u16 value) +{ + uint32_t bank; + uint32_t offset; + int error; + + if (reg < 0x20) + return phy_write(phydev, reg, value); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = phy_write(phydev, BRCM_MIIEXT_BANK, bank); + error |= phy_write(phydev, offset, value); + error |= phy_write(phydev, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + + return error; +} + +static int bcm63138s_get_features(struct phy_device *phydev) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(features) = { 0, }; + + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, features); + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, features); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, features); + + linkmode_copy(phydev->supported, features); + linkmode_copy(phydev->advertising, features); + + return 0; +} + +/* + * BCM63138 SerDes phy amplitude setting registers. + * + * serdes_amplitude for bcm63138s attribute is of the form: + * full|half + * + * it can be read and written. + * + * official limits are 0x3f-0x0c for amplitude values (unchecked + * here). + * + * values written to the attribute are reset to default after the + * interface is brought down & up. + */ +#define BCM63138S_AMP_VALUE_REG 0x8065 +#define AMP_VALUE_MASK (0x3f << 8) +#define AMP_VALUE_SHIFT (8) + +#define BCM63138S_AMP_SCALE_REG 0x8066 +#define AMP_SCALE_MASK (1 << 1) +#define AMP_SCALE_1V (0 << 1) +#define AMP_SCALE_0_5V (1 << 1) + +/* + * + */ +static ssize_t bcm63138s_read_serdes_amplitude(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + char buf[64]; + struct phy_device *phydev = file->private_data; + bool amp_scale_full; + u32 amp_value; + u32 reg; + + reg = bcm63138_ephy_read(phydev, BCM63138S_AMP_SCALE_REG); + amp_scale_full = (reg & AMP_SCALE_MASK) == AMP_SCALE_1V; + + reg = bcm63138_ephy_read(phydev, BCM63138S_AMP_VALUE_REG); + amp_value = (reg & AMP_VALUE_MASK) >> AMP_VALUE_SHIFT; + + snprintf(buf, sizeof (buf), "%s 0x%02x\n", + (amp_scale_full) ? "full" : "half", amp_value); + + return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf)); +} + +#define SCALE_FULL_STR "full " +#define SCALE_HALF_STR "half " + +/* + * + */ +static ssize_t bcm63138s_write_serdes_amplitude(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + int err; + char buf[32] = {0}; + const char *val_start; + struct phy_device *phydev = file->private_data; + u32 scale_val; + u32 amp_val; + u32 reg; + + /* + * Yay, string parsing in the kernel. + */ + err = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, + count); + if (err < 0) + return err; + + if (!strncmp(buf, SCALE_FULL_STR, strlen(SCALE_FULL_STR))) { + scale_val = AMP_SCALE_1V; + val_start = buf + strlen(SCALE_FULL_STR); + } else if (!strncmp(buf, SCALE_HALF_STR, strlen(SCALE_HALF_STR))) { + scale_val = AMP_SCALE_0_5V; + val_start = buf + strlen(SCALE_HALF_STR); + } else { + return -EINVAL; + } + + err = kstrtou32(val_start, 16, &_val); + if (err) + return err; + + /* + * all done with parsing, now write the registers. + */ + amp_val = (amp_val << AMP_VALUE_SHIFT) & AMP_VALUE_MASK; + + reg = bcm63138_ephy_read(phydev, BCM63138S_AMP_SCALE_REG); + reg &= ~AMP_SCALE_MASK; + reg |= scale_val; + bcm63138_ephy_write(phydev, BCM63138S_AMP_SCALE_REG, reg); + + reg = bcm63138_ephy_read(phydev, BCM63138S_AMP_VALUE_REG); + reg &= ~AMP_VALUE_MASK; + reg |= amp_val; + bcm63138_ephy_write(phydev, BCM63138S_AMP_VALUE_REG, reg); + + return count; +} + +static const struct file_operations fops_serdes_amplitude = { + .read = bcm63138s_read_serdes_amplitude, + .write = bcm63138s_write_serdes_amplitude, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +/* + * probe for bcm63138s phy, just create the debugfs entries for serdes + * amplitude tunning. + * + * won't work for more than one 63138s phy in the system. + */ +static int bcm63138s_probe(struct phy_device *phydev) +{ + struct dentry *dent; + + dent = debugfs_create_dir("bcm63138s_phy", NULL); + if (IS_ERR(dent) && PTR_ERR(dent) != -EEXIST) { + WARN_ON("unable to create debugfs entry for bcm63138s phy"); + return PTR_ERR(dent); + } + + debugfs_create_file("serdes_amplitude", + 0600, dent, phydev, &fops_serdes_amplitude); + + return 0; +} + +static int bcm63138s_config_init(struct phy_device *phydev) +{ + static const unsigned short cfg_1000x[] = { + 0x0010, 0x0c2f, + 0x8182, 0x4000, + 0x8186, 0x003c, + 0x8300, 0x015d, + 0x8301, 0x7, + 0x0, 0x1140, + 0x0010, 0x2c2f + }; + int err; + size_t i; + + err = genphy_soft_reset(phydev); + if (err < 0) + return err; + + for (i = 0; i < ARRAY_SIZE(cfg_1000x); i += 2) + bcm63138_ephy_write(phydev, cfg_1000x[i], cfg_1000x[i + 1]); + + return 0; +} + +/** + * ethtool_adv_to_fiber_adv_t + * @ethadv: the ethtool advertisement settings + * + * A small helper function that translates ethtool advertisement + * settings to phy autonegotiation advertisements for the + * MII_ADV register for fiber link. + */ +static inline u32 ethtool_adv_to_fiber_adv_t(unsigned long *adv) +{ + u32 result = 0; + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, adv)) + result |= ADVERTISE_1000XFULL; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, adv)) + result |= ADVERTISE_1000XFULL; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, adv)) + result |= ADVERTISE_1000XHALF; + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, adv) && + linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, adv)) + result |= ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM; + else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, adv)) + result |= ADVERTISE_1000XPAUSE; + + return result; +} + +static int bcm63138s_config_aneg(struct phy_device *phydev) +{ + int oldadv, adv, err; + int changed; + + if (phydev->autoneg != AUTONEG_ENABLE) + return genphy_setup_forced(phydev); + + /* Setup fiber advertisement */ + adv = phy_read(phydev, MII_ADVERTISE); + if (adv < 0) + return adv; + + oldadv = adv; + adv &= ~(ADVERTISE_1000XFULL | + ADVERTISE_1000XHALF | + ADVERTISE_1000XPSE_ASYM | + ADVERTISE_1000XPAUSE); + adv |= ethtool_adv_to_fiber_adv_t(phydev->advertising); + + if (adv != oldadv) { + err = phy_write(phydev, MII_ADVERTISE, adv); + if (err < 0) + return err; + + changed = 1; + } + + if (changed == 0) { + /* Advertisement hasn't changed, but maybe aneg was never on to + * begin with? Or maybe phy was isolated? + */ + int ctl = phy_read(phydev, MII_BMCR); + + if (ctl < 0) + return ctl; + + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) + changed = 1; /* do restart aneg */ + } + + /* Only restart aneg if we are advertising something different + * than we were before. + */ + if (changed > 0) + changed = genphy_restart_aneg(phydev); + + return changed; +} + +/** + * fiber_lpa_to_ethtool_lpa_t + * @lpa: value of the MII_LPA register for fiber link + * + * A small helper function that translates MII_LPA + * bits to ethtool LP advertisement settings. + */ +static void fiber_lpa_to_ethtool_lpa_t(u32 lpa, unsigned long *res) +{ + linkmode_zero(res); + + if (lpa & LPA_1000XHALF) + linkmode_set_bit( ADVERTISED_1000baseT_Half, res); + if (lpa & LPA_1000XFULL) + linkmode_set_bit(ADVERTISED_1000baseT_Full, res); +} + +static int bcm63138s_read_status_page_an(struct phy_device *phydev) +{ + int lpa, adv, common_adv; + + lpa = phy_read(phydev, MII_LPA); + if (lpa < 0) + return lpa; + + adv = phy_read(phydev, MII_ADVERTISE); + if (adv < 0) + return adv; + + common_adv = lpa & adv; + + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + fiber_lpa_to_ethtool_lpa_t(lpa, phydev->lp_advertising); + + phydev->pause = 0; + phydev->asym_pause = 0; + + if (common_adv & (LPA_1000XHALF | LPA_1000XFULL)) { + phydev->speed = SPEED_1000; + if (common_adv & LPA_1000XFULL) + phydev->duplex = DUPLEX_FULL; + } + + if (phydev->duplex == DUPLEX_FULL) { + if (!(lpa & LPA_1000XPAUSE)) { + phydev->pause = 0; + phydev->asym_pause = 0; + } else if ((lpa & LPA_1000XPAUSE_ASYM)) { + phydev->pause = 1; + phydev->asym_pause = 1; + } else { + phydev->pause = 1; + phydev->asym_pause = 0; + } + } + + return 0; +} + +static int bcm63138s_read_status_page_fixed(struct phy_device *phydev) +{ + int bmcr = phy_read(phydev, MII_BMCR); + + if (bmcr < 0) + return bmcr; + + if (bmcr & BMCR_FULLDPLX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + phydev->speed = SPEED_1000; + phydev->pause = 0; + phydev->asym_pause = 0; + + return 0; +} + +static int bcm63138s_read_status(struct phy_device *phydev) +{ + int err; + + genphy_update_link(phydev); + + if (phydev->autoneg == AUTONEG_ENABLE) + err = bcm63138s_read_status_page_an(phydev); + else + err = bcm63138s_read_status_page_fixed(phydev); + + return err; +} + +#define MISC_ADDR(base, channel) base, channel + +#define AFE_TXCONFIG_0 MISC_ADDR(0x39, 1) +#define AFE_TXCONFIG_1 MISC_ADDR(0x3a, 2) +#define AFE_TX_IQ_RX_LP MISC_ADDR(0x39, 0) +#define AFE_TEMPSEN_OTHERS MISC_ADDR(0x3b, 0) + +static void r_rc_cal_reset(struct phy_device *phydev) +{ + /* Reset R_CAL/RC_CAL Engine */ + bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010); + + /* Disable Reset R_AL/RC_CAL Engine */ + bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000); +} + +static int bcm63158_config_init(struct phy_device *phydev) +{ + /* Turn off AOF */ + bcm_phy_write_misc(phydev, AFE_TXCONFIG_0, 0x0000); + + /* 1g AB symmetry Iq */ + bcm_phy_write_misc(phydev, AFE_TXCONFIG_1, 0x0BCC); + + /* LPF BW */ + bcm_phy_write_misc(phydev, AFE_TX_IQ_RX_LP, 0x233F); + + /* RCAL +6LSB to make impedance from 112 to 100ohm */ + bcm_phy_write_misc(phydev, AFE_TEMPSEN_OTHERS, 0xAD40); + + /* since rcal make R smaller, make master current -4% */ + bcm_phy_write_misc(phydev, DSP_TAP10, 0x091B); + + /* From EEE excel config file for Vitesse fix */ + /* rx_on_tune 8 -> 0xf */ + bcm_phy_write_misc(phydev, 0x0021, 0x0002, 0x87F6); + + /* 100tx EEE bandwidth */ + bcm_phy_write_misc(phydev, 0x0022, 0x0002, 0x017D); + + /* enable ffe zero det for Vitesse interop */ + bcm_phy_write_misc(phydev, 0x0026, 0x0002, 0x0015); + + /* Reset R_CAL/RC_CAL engine */ + r_rc_cal_reset(phydev); + + return 0; +} + +static int bcm63158_read_mmd(struct phy_device *phydev, + int devnum, u16 regnum) +{ + struct mii_bus *bus = phydev->mdio.bus; + int phy_addr = phydev->mdio.addr; + int val; + + /* MDIO_MMD_PCS/MDIO_PCS_EEE_ABLE is not set in broadcom PHY, + * so we divert read_mmd to return fake value for this + * register */ + if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) + return MDIO_EEE_100TX | MDIO_EEE_1000T; + + /* Write the desired MMD Devad */ + __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, devnum); + + /* Write the desired MMD register address */ + __mdiobus_write(bus, phy_addr, MII_MMD_DATA, regnum); + + /* Select the Function : DATA with no post increment */ + __mdiobus_write(bus, phy_addr, MII_MMD_CTRL, + devnum | MII_MMD_CTRL_NOINCR); + + /* Read the content of the MMD's selected register */ + val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA); + return val; +} + + static struct phy_driver broadcom_drivers[] = { { .phy_id = PHY_ID_BCM5411, @@ -1132,6 +1604,29 @@ .config_intr = bcm_phy_config_intr, .handle_interrupt = bcm_phy_handle_interrupt, .link_change_notify = bcm54xx_link_change_notify, +}, { + .phy_id = PHY_ID_BCM63138S, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM63138S", + .probe = bcm63138s_probe, + .get_features = bcm63138s_get_features, + .config_init = bcm63138s_config_init, + .config_aneg = bcm63138s_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = bcm63138s_read_status, +}, { + .phy_id = PHY_ID_BCM63158, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM63158", + .features = PHY_GBIT_FEATURES, + .flags = PHY_IS_INTERNAL, + .config_init = bcm63158_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_mmd = bcm63158_read_mmd, } }; module_phy_driver(broadcom_drivers); @@ -1157,6 +1652,8 @@ { PHY_ID_BCM53125, 0xfffffff0 }, { PHY_ID_BCM53128, 0xfffffff0 }, { PHY_ID_BCM89610, 0xfffffff0 }, + { PHY_ID_BCM63138S, 0xfffffff0 }, + { PHY_ID_BCM63158, 0xfffffff0 }, { } }; diff -ruw linux-6.4/drivers/net/phy/mdio_bus.c linux-6.4-fbx/drivers/net/phy/mdio_bus.c --- linux-6.4/drivers/net/phy/mdio_bus.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/mdio_bus.c 2023-06-27 11:47:15.859861290 +0200 @@ -650,7 +650,7 @@ int __mdiobus_register(struct mii_bus *bus, struct module *owner) { struct mdio_device *mdiodev; - struct gpio_desc *gpiod; + struct gpio_descs *gpiod; bool prevent_c45_scan; int i, err; @@ -696,7 +696,7 @@ mutex_init(&bus->shared_lock); /* assert bus level PHY GPIO reset */ - gpiod = devm_gpiod_get_optional(&bus->dev, "reset", GPIOD_OUT_HIGH); + gpiod = devm_gpiod_get_array_optional(&bus->dev, "reset", GPIOD_OUT_HIGH); if (IS_ERR(gpiod)) { err = dev_err_probe(&bus->dev, PTR_ERR(gpiod), "mii_bus %s couldn't get reset GPIO\n", @@ -706,7 +706,8 @@ } else if (gpiod) { bus->reset_gpiod = gpiod; fsleep(bus->reset_delay_us); - gpiod_set_value_cansleep(gpiod, 0); + for (i = 0; i < gpiod->ndescs; i++) + gpiod_set_value_cansleep(gpiod->desc[i], 0); if (bus->reset_post_delay_us > 0) fsleep(bus->reset_post_delay_us); } @@ -748,8 +749,10 @@ } error_reset_gpiod: /* Put PHYs in RESET to save power */ - if (bus->reset_gpiod) - gpiod_set_value_cansleep(bus->reset_gpiod, 1); + if (bus->reset_gpiod) { + for (i = 0; i < bus->reset_gpiod->ndescs; i++) + gpiod_set_value_cansleep(bus->reset_gpiod->desc[i], 1); + } device_del(&bus->dev); return err; @@ -778,8 +781,10 @@ } /* Put PHYs in RESET to save power */ - if (bus->reset_gpiod) - gpiod_set_value_cansleep(bus->reset_gpiod, 1); + if (bus->reset_gpiod) { + for (i = 0; i < bus->reset_gpiod->ndescs; i++) + gpiod_set_value_cansleep(bus->reset_gpiod->desc[i], 1); + } device_del(&bus->dev); } diff -ruw linux-6.4/drivers/net/phy/phy-c45.c linux-6.4-fbx/drivers/net/phy/phy-c45.c --- linux-6.4/drivers/net/phy/phy-c45.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/phy-c45.c 2023-12-05 17:14:42.299715016 +0100 @@ -748,6 +748,16 @@ mii_10base_t1_adv_mod_linkmode_t(adv, val); } + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->supported_eee)) { + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); + if (val < 0) + return val; + + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + adv, val & MDIO_EEE_2_5GT); + } + return 0; } @@ -784,6 +794,16 @@ mii_10base_t1_adv_mod_linkmode_t(lpa, val); } + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->supported_eee)) { + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); + if (val < 0) + return val; + + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + lpa, val & MDIO_EEE_2_5GT); + } + return 0; } @@ -1477,3 +1497,25 @@ .name = "Generic Clause 45 PHY", .read_status = genphy_c45_read_status, }; + +static int genphy_broken_c45_get_tunable(struct phy_device *phydev, + struct ethtool_tunable *tuna, + void *data) +{ + switch (tuna->id) { + case ETHTOOL_PHY_BROKEN: + *(u8*)data = 1; + return 0; + default: + return -ENOTSUPP; + } + return 0; +} + +struct phy_driver genphy_broken_c45_driver = { + .phy_id = 0xffffffff, + .phy_id_mask = 0xffffffff, + .name = "Generic Broken Clause 45 PHY", + .read_status = genphy_c45_read_status, + .get_tunable = genphy_broken_c45_get_tunable, +}; diff -ruw linux-6.4/drivers/net/phy/phy-core.c linux-6.4-fbx/drivers/net/phy/phy-core.c --- linux-6.4/drivers/net/phy/phy-core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/phy-core.c 2023-05-22 20:30:14.541854042 +0200 @@ -13,7 +13,7 @@ */ const char *phy_speed_to_str(int speed) { - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 102, + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 108, "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "If a speed or mode has been added please update phy_speed_to_str " "and the PHY settings array.\n"); @@ -138,10 +138,19 @@ case PHY_INTERFACE_MODE_RXAUI: case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_1000BASEKX: + case PHY_INTERFACE_MODE_1000BASEPX_D: + case PHY_INTERFACE_MODE_1000BASEPX_U: + case PHY_INTERFACE_MODE_10000BASEPR_D: + case PHY_INTERFACE_MODE_10000BASEPR_U: + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_D: + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 4; + case PHY_INTERFACE_MODE_PSGMII: + return 5; case PHY_INTERFACE_MODE_MAX: WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode"); return 0; @@ -230,6 +239,10 @@ PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), /* 10G */ + PHY_SETTING( 10000, FULL, 10000_1000basePRX_D_Full ), + PHY_SETTING( 10000, FULL, 10000_1000basePRX_U_Full ), + PHY_SETTING( 10000, FULL, 10000basePR_D_Full ), + PHY_SETTING( 10000, FULL, 10000basePR_U_Full ), PHY_SETTING( 10000, FULL, 10000baseCR_Full ), PHY_SETTING( 10000, FULL, 10000baseER_Full ), PHY_SETTING( 10000, FULL, 10000baseKR_Full ), @@ -245,6 +258,8 @@ PHY_SETTING( 2500, FULL, 2500baseT_Full ), PHY_SETTING( 2500, FULL, 2500baseX_Full ), /* 1G */ + PHY_SETTING( 1000, FULL, 1000basePX_D_Full ), + PHY_SETTING( 1000, FULL, 1000basePX_U_Full ), PHY_SETTING( 1000, FULL, 1000baseT_Full ), PHY_SETTING( 1000, HALF, 1000baseT_Half ), PHY_SETTING( 1000, FULL, 1000baseT1_Full ), diff -ruw linux-6.4/drivers/net/phy/phy.c linux-6.4-fbx/drivers/net/phy/phy.c --- linux-6.4/drivers/net/phy/phy.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/phy.c 2023-05-22 20:06:42.135797731 +0200 @@ -36,7 +36,7 @@ #include #include -#define PHY_STATE_TIME HZ +#define PHY_STATE_TIME (HZ / 2) #define PHY_STATE_STR(_state) \ case PHY_##_state: \ diff -ruw linux-6.4/drivers/net/phy/phy_device.c linux-6.4-fbx/drivers/net/phy/phy_device.c --- linux-6.4/drivers/net/phy/phy_device.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/phy_device.c 2023-06-27 11:47:15.859861290 +0200 @@ -812,7 +812,8 @@ return -EIO; } - if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff) { + if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff || + !devs_in_pkg) { /* If mostly Fs, there is no device there, then let's probe * MMD 0, as some 10G PHYs have zero Devices In package, * e.g. Cortina CS4315/CS4340 PHY. @@ -822,9 +823,13 @@ return -EIO; /* no device there, let's get out of here */ - if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff) + if ((devs_in_pkg & 0x1fffffff) == 0x1fffffff || + !devs_in_pkg) { + if (bus->keep_broken_phy) + return 0; return -ENODEV; } + } /* Now probe Device Identifiers for each device present. */ for (i = 1; i < num_ids; i++) { @@ -1454,6 +1459,9 @@ */ if (!d->driver) { if (phydev->is_c45) + if (!phydev->c45_ids.mmds_present) + d->driver = &genphy_broken_c45_driver.mdiodrv.driver; + else d->driver = &genphy_c45_driver.mdiodrv.driver; else d->driver = &genphy_driver.mdiodrv.driver; @@ -3463,9 +3471,15 @@ if (rc) goto err_c45; + rc = phy_driver_register(&genphy_broken_c45_driver, THIS_MODULE); + if (rc) + goto err_c45_broken; + rc = phy_driver_register(&genphy_driver, THIS_MODULE); if (rc) { phy_driver_unregister(&genphy_c45_driver); +err_c45_broken: + phy_driver_unregister(&genphy_broken_c45_driver); err_c45: mdio_bus_exit(); } @@ -3475,6 +3489,7 @@ static void __exit phy_exit(void) { + phy_driver_unregister(&genphy_broken_c45_driver); phy_driver_unregister(&genphy_c45_driver); phy_driver_unregister(&genphy_driver); mdio_bus_exit(); diff -ruw linux-6.4/drivers/net/phy/phylink.c linux-6.4-fbx/drivers/net/phy/phylink.c --- linux-6.4/drivers/net/phy/phylink.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/phylink.c 2023-11-24 15:30:07.781950177 +0100 @@ -191,9 +191,13 @@ case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_PSGMII: + case PHY_INTERFACE_MODE_1000BASEPX_D: + case PHY_INTERFACE_MODE_1000BASEPX_U: return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10G_QXGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -205,6 +209,10 @@ case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10000BASEPR_D: + case PHY_INTERFACE_MODE_10000BASEPR_U: + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_D: + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: return SPEED_10000; case PHY_INTERFACE_MODE_25GBASER: @@ -213,6 +221,7 @@ case PHY_INTERFACE_MODE_XLGMII: return SPEED_40000; + case PHY_INTERFACE_MODE_INTERNAL: case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_MAX: @@ -445,7 +454,11 @@ switch (interface) { case PHY_INTERFACE_MODE_USXGMII: - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; + caps |= MAC_10000FD | MAC_5000FD; + fallthrough; + + case PHY_INTERFACE_MODE_10G_QXGMII: + caps |= MAC_2500FD; fallthrough; case PHY_INTERFACE_MODE_RGMII_TXID: @@ -456,6 +469,7 @@ case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_PSGMII: caps |= MAC_1000HD | MAC_1000FD; fallthrough; @@ -479,6 +493,8 @@ fallthrough; case PHY_INTERFACE_MODE_1000BASEKX: case PHY_INTERFACE_MODE_TRGMII: + case PHY_INTERFACE_MODE_1000BASEPX_D: + case PHY_INTERFACE_MODE_1000BASEPX_U: caps |= MAC_1000FD; break; @@ -495,6 +511,10 @@ case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_10GKR: + case PHY_INTERFACE_MODE_10000BASEPR_D: + case PHY_INTERFACE_MODE_10000BASEPR_U: + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_D: + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: caps |= MAC_10000FD; break; @@ -507,10 +527,10 @@ break; case PHY_INTERFACE_MODE_INTERNAL: + case PHY_INTERFACE_MODE_NA: caps |= ~0; break; - case PHY_INTERFACE_MODE_NA: case PHY_INTERFACE_MODE_MAX: break; } @@ -846,8 +866,13 @@ pl->cfg_link_an_mode = MLO_AN_INBAND; switch (pl->link_config.interface) { + case PHY_INTERFACE_MODE_10G_QXGMII: + phylink_set(pl->supported, 2500baseT_Full); + phylink_set(pl->supported, 2500baseX_Full); + fallthrough; case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_PSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: @@ -930,6 +955,25 @@ phylink_set(pl->supported, 100000baseDR2_Full); break; + case PHY_INTERFACE_MODE_1000BASEPX_D: + phylink_set(pl->supported, 1000basePX_D_Full); + break; + case PHY_INTERFACE_MODE_1000BASEPX_U: + phylink_set(pl->supported, 1000basePX_U_Full); + break; + case PHY_INTERFACE_MODE_10000BASEPR_D: + phylink_set(pl->supported, 10000basePR_D_Full); + break; + case PHY_INTERFACE_MODE_10000BASEPR_U: + phylink_set(pl->supported, 10000basePR_U_Full); + break; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_D: + phylink_set(pl->supported, 10000_1000basePRX_D_Full); + break; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + phylink_set(pl->supported, 10000_1000basePRX_U_Full); + break; + default: phylink_err(pl, "incorrect link mode %s for in-band status\n", @@ -1916,12 +1960,13 @@ * desired link mode(s) and negotiation style. This should be called from the * network device driver's &struct net_device_ops ndo_open() method. */ -void phylink_start(struct phylink *pl) +static void __phylink_start(struct phylink *pl, bool silent) { bool poll = false; ASSERT_RTNL(); + if (!silent) phylink_info(pl, "configuring for %s/%s link mode\n", phylink_an_mode_str(pl->cur_link_an_mode), phy_modes(pl->link_config.interface)); @@ -1976,6 +2021,18 @@ } EXPORT_SYMBOL_GPL(phylink_start); +void phylink_start(struct phylink *pl) +{ + return __phylink_start(pl, false); +} + +void phylink_start_silent(struct phylink *pl) +{ + return __phylink_start(pl, true); +} + +EXPORT_SYMBOL_GPL(phylink_start_silent); + /** * phylink_stop() - stop a phylink instance * @pl: a pointer to a &struct phylink returned from phylink_create() @@ -2946,10 +3003,10 @@ phy_interface_t iface; int ret; - linkmode_copy(support, phy->supported); + linkmode_copy(support, pl->sfp_support); memset(&config, 0, sizeof(config)); - linkmode_copy(config.advertising, phy->advertising); + linkmode_copy(config.advertising, pl->sfp_support); config.interface = PHY_INTERFACE_MODE_NA; config.speed = SPEED_UNKNOWN; config.duplex = DUPLEX_UNKNOWN; @@ -3370,6 +3427,7 @@ case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_PSGMII: phylink_decode_sgmii_word(state, lpa); break; case PHY_INTERFACE_MODE_QUSGMII: @@ -3551,6 +3609,121 @@ } EXPORT_SYMBOL_GPL(phylink_mii_c45_pcs_get_state); +/* + * designed to be called from userland to override current link + * interface, used for both testing and to handle SFP from userland. + * + * While it could theoritically be used on phylink instance with a + * phy, phylink_of_phy_connect() or equivalent is called at netdevice + * probe time, so it's too late to override phy_interface, thus we + * restrict this to instances without phydev. + * + * For the same reasons, we don't allow this to be set on instance + * attached to an SFP bus, since the kernel will do the right thing + * when an SFP is plugged. + * + * The an_enabled has to be given because some devices either don't or + * only support autoneg for some interface, so we cannot rely on + * further ethtool call to enable/disable it, both the interface and + * autoneg have to be changed atomically. + */ +int phylink_set_interface(struct phylink *pl, + phy_interface_t interface, + bool an_enabled) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); + __ETHTOOL_DECLARE_LINK_MODE_MASK(supported1); + struct phylink_link_state config; + bool changed, changed_intf; + int ret; + + if (pl->phydev) + return -ENOTSUPP; + + if (pl->sfp_bus && pl->sfp_port) + return -ENOTSUPP; + + memset(&config, 0, sizeof(config)); + config.interface = PHY_INTERFACE_MODE_NA; + config.speed = SPEED_UNKNOWN; + config.duplex = DUPLEX_UNKNOWN; + config.pause = MLO_PAUSE_AN; + bitmap_fill(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + linkmode_copy(config.advertising, supported); + + if (!an_enabled) + phylink_clear(config.advertising, Autoneg); + + phylink_validate(pl, supported, &config); + + config.interface = interface; + linkmode_copy(supported1, supported); + + ret = phylink_validate(pl, supported1, &config); + if (ret) { + phylink_err(pl, + "validation of %s/%s with support %*pb failed: %d\n", + phylink_an_mode_str(pl->cfg_link_an_mode), + phy_modes(config.interface), + __ETHTOOL_LINK_MODE_MASK_NBITS, supported, ret); + return ret; + } + + changed = !linkmode_equal(pl->supported, supported1) || + !linkmode_equal(pl->link_config.advertising, + config.advertising); + + if (changed) { + linkmode_copy(pl->supported, supported1); + linkmode_copy(pl->link_config.advertising, config.advertising); + } + + changed_intf = (pl->link_config.interface != config.interface); + + if (changed || changed_intf) { + if (pl->old_link_state) { + phylink_link_down(pl); + pl->old_link_state = false; + } + } + + if (changed_intf) { + pl->link_config.interface = config.interface; + phylink_info(pl, "switched to %s/%s link mode (userland)\n", + phylink_an_mode_str(pl->cur_link_an_mode), + phy_modes(pl->link_config.interface)); + } + + if ((changed || changed_intf) && + !test_bit(PHYLINK_DISABLE_STOPPED, + &pl->phylink_disable_state)) { + cancel_work_sync(&pl->resolve); + phylink_mac_initial_config(pl, false); + phylink_run_resolve(pl); + } + + return 0; + +} + +EXPORT_SYMBOL_GPL(phylink_set_interface); + +/* + * retrieve current interface & mode + */ +void phylink_get_interface(struct phylink *pl, + phy_interface_t *interface, + int *an_en, + int *mode) +{ + *interface = pl->link_config.interface; + *an_en = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, + pl->link_config.advertising); + *mode = pl->cfg_link_an_mode; +} + +EXPORT_SYMBOL_GPL(phylink_get_interface); + static int __init phylink_init(void) { for (int i = 0; i < ARRAY_SIZE(phylink_sfp_interface_preference); ++i) diff -ruw linux-6.4/drivers/net/phy/realtek.c linux-6.4-fbx/drivers/net/phy/realtek.c --- linux-6.4/drivers/net/phy/realtek.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/realtek.c 2023-05-22 20:06:42.135797731 +0200 @@ -12,6 +12,10 @@ #include #include #include +#include +#include + +#include "realtek.h" #define RTL821x_PHYSR 0x11 #define RTL821x_PHYSR_DUPLEX BIT(13) @@ -72,6 +76,75 @@ #define RTL_GENERIC_PHYID 0x001cc800 #define RTL_8211FVD_PHYID 0x001cc878 +#define RTL8221B_SERDES_OPT_REG 0x697a +#define RTL8221B_SERDES_OPT_MODE_MASK 0x3f +#define RTL8221B_SERDES_OPT_MODE_2G5_SGMII 0x00 +#define RTL8221B_SERDES_OPT_MODE_HISGMII_SGMII 0x01 +#define RTL8221B_SERDES_OPT_MODE_2G5_ONLY 0x02 +#define RTL8221B_SERDES_OPT_MODE_HISGMII_ONLY 0x03 + +#define RTL8221B_SERDES_CTRL3_REG 0x7580 +#define RTL8221B_SERDES_CTRL3_MODE_MASK 0x1f +#define RTL8221B_SERDES_CTRL3_MODE_SGMII 0x02 +#define RTL8221B_SERDES_CTRL3_MODE_HISGMII 0x12 +#define RTL8221B_SERDES_CTRL3_MODE_2G5BX 0x16 +#define RTL8221B_SERDES_CTRL3_MODE_OFF 0x1f + +#define RTL8221B_SERDES_CTRL5_REG 0x7582 +#define RTL8221B_SERDES_CTRL5_FDPX (1 << 2) +#define RTL8221B_SERDES_CTRL5_SPEED_MASK 0x3003 +#define RTL8221B_SERDES_CTRL5_SPEED_10 0x0000 +#define RTL8221B_SERDES_CTRL5_SPEED_100 0x0001 +#define RTL8221B_SERDES_CTRL5_SPEED_1000 0x0002 +#define RTL8221B_SERDES_CTRL5_SPEED_2G5 0x1001 +#define RTL8221B_SERDES_CTRL5_SPEED_2G5LITE 0x1003 + +#define RTL8221B_FEDCR_REG 0xa400 +#define RTL8221B_FEDCR_PCS_LB_EN (1 << 14) + +#define RTL8221B_GBCR_REG 0xa412 +#define RTL8221B_GBCR_ADV_1000BaseT (1 << 9) + +#define RTL8221B_GANLPAR_REG 0xa414 +#define RTL8221B_GANLPAR_LP_1000BaseTFD (1 << 11) +#define RTL8221B_GANLPAR_LP_1000BaseTHD (1 << 10) + +#define RTL8221B_LCR4_REG 0xd036 +#define LCR4_SELECT_2G5 (1 << 5) +#define LCR4_SELECT_1G (1 << 2) +#define LCR4_SELECT_100M (1 << 1) +#define LCR4_SELECT_10M (1 << 0) + +#define RTL8221B_LCR6_REG 0xd040 +#define LCR6_BLINK_FREQ_MASK (0x3 << 8) +#define LCR6_BLINK_FREQ_20MS (0x0 << 8) +#define LCR6_BLINK_FREQ_40MS (0x1 << 8) +#define LCR6_BLINK_FREQ_60MS (0x2 << 8) +#define LCR6_BLINK_PATTERN_MODE_B (0x1 << 5) + +#define RTL8221B_LCR7_REG 0xd044 +#define LCR7_LED_EN_MASK(led) (1 << (4 + (led))) +#define LCR7_LED_POL_HI_MASK(led) (1 << (led)) + +#define RTL8221B_RX_STATS_SELECT_REG 0xc800 +#define RX_STATS_SELECT_UTP 0x5a02 +#define RX_STATS_SELECT_SERDES 0x5a06 + +#define RTL8221B_RX_STATS_CLEAR_REG 0xc802 +#define RX_STATS_CLEAR_VAL 0x0073 + +#define RTL8221B_RX_STATS_GOOD_PKT_LSB 0xc810 +#define RTL8221B_RX_STATS_GOOD_PKT_MSB 0xc812 +#define RTL8221B_RX_STATS_CRC_PKT 0xc814 + +#define RTL8221B_UNKOWN_0xc40a 0xc40a +#define RTL8221B_UNKOWN_0xc466 0xc466 + +#define RTL8211F_LCR_PAGE 0xd04 +#define RTL8211F_LCR_REG 0x10 +#define RTL8211F_LED_MODE_MASK(num) (0x1b << ((num) * 5)) +#define RTL8211F_LED_MODE_SEL(num, mode) ((mode) << ((num) * 5)) + MODULE_DESCRIPTION("Realtek PHY driver"); MODULE_AUTHOR("Johnson Leung"); MODULE_LICENSE("GPL"); @@ -80,6 +153,8 @@ u16 phycr1; u16 phycr2; bool has_phycr2; +#define MAX_LEDS 3 + u8 leds_mode[MAX_LEDS]; }; static int rtl821x_read_page(struct phy_device *phydev) @@ -335,12 +410,27 @@ CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); } +static void rtl8211f_config_led(struct phy_device *phydev) +{ + struct rtl821x_priv *priv = phydev->priv; + size_t i; + + /* Configure led */ + for (i = 0; i < MAX_LEDS; ++i) { + phy_modify_paged(phydev, RTL8211F_LCR_PAGE, RTL8211F_LCR_REG, + RTL8211F_LED_MODE_MASK(i), + RTL8211F_LED_MODE_SEL(i, priv->leds_mode[i])); + } +} + static int rtl8211f_config_init(struct phy_device *phydev) { struct rtl821x_priv *priv = phydev->priv; struct device *dev = &phydev->mdio.dev; - u16 val_txdly, val_rxdly; int ret; + u16 val_txdly, val_rxdly; + + rtl8211f_config_led(phydev); ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF, @@ -432,6 +522,70 @@ return 0; } +#ifdef CONFIG_OF_MDIO +static int rtl8211f_dt_led_modes_get(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct device_node *of_node = dev->of_node; + struct rtl821x_priv *priv = phydev->priv; + int nr, i, ret; + char *led_dt_prop = "rtl8211f,led-mode"; + uint8_t mode[MAX_LEDS << 1]; + + if (!of_node) + return -ENODEV; + + nr = of_property_read_variable_u8_array(of_node, led_dt_prop, mode, 0, + ARRAY_SIZE(mode)); + + /* nr should be even */ + if (nr & 0x1) + return -EINVAL; + + ret = -EINVAL; + for (i = 0; i < nr; i += 2) { + if (mode[i] >= MAX_LEDS) + goto out; + if ((mode[i + 1] & ~RTL8211F_LED_MODE_MASK(0)) != 0) + goto out; + priv->leds_mode[mode[i]] = mode[i + 1]; + } + + ret = 0; + +out: + return ret; +} + + +#else +static int rtl8211f_dt_led_modes_get(struct phy_device *phydev) +{ + return 0; +} +#endif /* CONFIG_OF_MDIO */ + +static int rtl8211f_probe(struct phy_device *phydev) +{ + struct rtl821x_priv *priv; + int error; + u8 default_mode[MAX_LEDS] = { + [0] = RTL8211F_LED_MODE_10M | RTL8211F_LED_MODE_100M | + RTL8211F_LED_MODE_1000M | RTL8211F_LED_MODE_ACT, + [1] = RTL8211F_LED_MODE_10M | RTL8211F_LED_MODE_100M | + RTL8211F_LED_MODE_1000M, + [2] = RTL8211F_LED_MODE_1000M | RTL8211F_LED_MODE_ACT, + }; + + error = rtl821x_probe(phydev); + if (error) + return error; + + priv = phydev->priv; + memcpy(priv->leds_mode, default_mode, sizeof(priv->leds_mode)); + return rtl8211f_dt_led_modes_get(phydev); +} + static int rtl8211e_config_init(struct phy_device *phydev) { int ret = 0, oldpage; @@ -849,6 +1003,311 @@ return IRQ_HANDLED; } +enum { + RTL8221B_SERDES_STATS_RX_GOOD_PACKETS, + RTL8221B_SERDES_STATS_RX_BAD_CRC_PACKETS, + + RTL8221B_SERDES_STATS_COUNT, +}; + +struct rtl8221b_stat { + u64 v; +}; + +struct rtl8221b_priv { + struct rtl8221b_stat stats[RTL8221B_SERDES_STATS_COUNT]; +}; + +static int rtl8221b_get_sset_count(struct phy_device *phydev) +{ + return RTL8221B_SERDES_STATS_COUNT; +} + +struct rtl8221b_stat_desc { + const char *name; + int reg; + int size; +}; + +enum { + E_STAT_SIZE_U16, + E_STAT_SIZE_U32, +}; + +struct rtl8221b_stat_desc rtl8221b_stats[RTL8221B_SERDES_STATS_COUNT] = { + { + .name = "sgmii_rx_good_frames", + .reg = RTL8221B_RX_STATS_GOOD_PKT_LSB, + .size = E_STAT_SIZE_U32 + }, + { + .name = "sgmii_rx_crc_frames", + .reg = RTL8221B_RX_STATS_CRC_PKT, + .size = E_STAT_SIZE_U16 + }, +}; + +static void rtl8221b_get_strings(struct phy_device *phydev, u8 *data) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(rtl8221b_stats); ++i) { + strscpy(data + i * ETH_GSTRING_LEN, rtl8221b_stats[i].name, + ETH_GSTRING_LEN); + } +} + +static void rtl8221b_get_stats(struct phy_device *phydev, + struct ethtool_stats *stats, + u64 *data) +{ + struct rtl8221b_priv *priv = phydev->priv; + size_t i; + + for (i = 0; i < ARRAY_SIZE(rtl8221b_stats); ++i) { + struct rtl8221b_stat_desc *st_desc = &rtl8221b_stats[i]; + struct rtl8221b_stat *st = &priv->stats[i]; + u32 v; + + switch (st_desc->size) { + case E_STAT_SIZE_U16: + default: + v = phy_read_mmd(phydev, MDIO_MMD_VEND2, st_desc->reg); + break; + case E_STAT_SIZE_U32: + v = phy_read_mmd(phydev, MDIO_MMD_VEND2, st_desc->reg) | + (phy_read_mmd(phydev, MDIO_MMD_VEND2, + st_desc->reg + 2) << 16); + break; + } + + st->v += v; + data[i] = st->v; + } + + /* + * FIXME: ask for autoclear feature of counters. clear + * counters explicitely in the mean time. + */ + phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_RX_STATS_CLEAR_REG, + RX_STATS_CLEAR_VAL); +} + +static int rtl8221b_probe(struct phy_device *phydev) +{ + phydev->priv = devm_kzalloc(&phydev->mdio.dev, + sizeof (struct rtl8221b_priv), GFP_KERNEL); + if (!phydev->priv) + return -ENOMEM; + + return realtek_hwmon_probe(phydev); +} + +static int rtl8221b_config_init(struct phy_device *phydev) +{ + /* + * reset autoneg and PMA/PMD MMD. + */ + phy_set_bits_mmd(phydev, MDIO_MMD_AN, MII_BMCR, BMCR_RESET); + phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MII_BMCR, BMCR_RESET); + + + /* + * configure serdes side of the phy so that its speed is + * chosen depending on the copper side autonegotiation. + */ + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, BIT(0)); + phy_modify_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_SERDES_OPT_REG, + RTL8221B_SERDES_OPT_MODE_MASK, + RTL8221B_SERDES_OPT_MODE_2G5_SGMII); + + /* + * serdes mode change will be considered once copper link goes + * down. make it go down by briefly activating the PCS + * loopback feature. + */ + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_FEDCR_REG, + RTL8221B_FEDCR_PCS_LB_EN); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_FEDCR_REG, + RTL8221B_FEDCR_PCS_LB_EN); + + /* + * led configuration: enable only LED 2, active low. + */ + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_LCR7_REG, + LCR7_LED_EN_MASK(2)); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_LCR7_REG, + LCR7_LED_POL_HI_MASK(2)); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_LCR7_REG, + LCR7_LED_EN_MASK(1) | LCR7_LED_EN_MASK(0)); + + /* + * led blink frequency: 60 ms. + */ + phy_modify_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_LCR6_REG, + LCR6_BLINK_FREQ_MASK, LCR6_BLINK_FREQ_60MS); + + /* + * led2 selects all possible speeds + */ + phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_LCR4_REG, + LCR4_SELECT_10M | LCR4_SELECT_100M | LCR4_SELECT_1G | + LCR4_SELECT_2G5); + + /* + * select SerDes side for RX stats. + */ + phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_RX_STATS_SELECT_REG, + RX_STATS_SELECT_SERDES); + phy_write_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_RX_STATS_CLEAR_REG, + RX_STATS_CLEAR_VAL); + + return 0; +} + +static int rtl8221b_get_features(struct phy_device *phydev) +{ + int err; + + err = genphy_c45_pma_read_abilities(phydev); + if (err) + return err; + + phy_set_max_speed(phydev, SPEED_2500); + + return 0; +} + +static int rtl8221b_config_aneg(struct phy_device *phydev) +{ + bool changed = false; + int err; + u16 v; + + if (phydev->autoneg == AUTONEG_DISABLE) + return genphy_c45_pma_setup_forced(phydev); + + err = genphy_c45_an_config_aneg(phydev); + if (err < 0) + return err; + changed = (err > 0) || changed; + + if (err > 0) + changed = true; + + /* + * 802.3-C45 doesn't provide a standardised way of advertising + * 1000Base-T support, we have to use use vendor registers for + * this. + */ + v = 0; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + phydev->advertising) || + linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, + phydev->advertising)) + v |= RTL8221B_GBCR_ADV_1000BaseT; + + err = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL8221B_GBCR_REG, + RTL8221B_GBCR_ADV_1000BaseT, v); + if (err < 0) + return err; + changed = (err > 0) || changed; + + return genphy_c45_check_and_restart_aneg(phydev, changed); +} + +static int rtl8221b_read_status(struct phy_device *phydev) +{ + int err; + int v; + bool fdpx; + + if (phydev->autoneg == AUTONEG_ENABLE) { + /* + * 802.3-C45 doesn't provide a standardised way of + * getting LPA 1000Base-T support, we have to use use + * vendor registers for this. + */ + v = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_GANLPAR_REG); + if (v < 0) + return v; + } + + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, + phydev->lp_advertising, + v & RTL8221B_GANLPAR_LP_1000BaseTFD); + linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, + phydev->lp_advertising, + v & RTL8221B_GANLPAR_LP_1000BaseTHD); + + + err = genphy_c45_read_status(phydev); + if (err) + return err; + + + if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) + return 0; + + /* + * sort out phydev interface depending on the current mode of + * the SERDES on the PHY side. + */ + v = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_SERDES_CTRL3_REG); + v &= RTL8221B_SERDES_CTRL3_MODE_MASK; + + switch (v) { + case RTL8221B_SERDES_CTRL3_MODE_SGMII: + phydev->interface = PHY_INTERFACE_MODE_SGMII; + break; + case RTL8221B_SERDES_CTRL3_MODE_2G5BX: + phydev->interface = PHY_INTERFACE_MODE_2500BASEX; + break; + default: + phydev_warn(phydev, "invalid SERDES mode: %u\n", v); + return -EIO; + } + + v = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL8221B_SERDES_CTRL5_REG); + fdpx = !!(v & RTL8221B_SERDES_CTRL5_FDPX); + v &= RTL8221B_SERDES_CTRL5_SPEED_MASK; + + switch (v) { + case RTL8221B_SERDES_CTRL5_SPEED_2G5: + phydev->speed = SPEED_2500; + break; + case RTL8221B_SERDES_CTRL5_SPEED_1000: + phydev->speed = SPEED_1000; + break; + case RTL8221B_SERDES_CTRL5_SPEED_100: + phydev->speed = SPEED_100; + break; + case RTL8221B_SERDES_CTRL5_SPEED_10: + phydev->speed = SPEED_10; + break; + default: + phydev_warn(phydev, "invalid device speed: %04x\n", v); + } + + /* + * XXX: as recommended by realtek for SerDes RX stats. + */ + if (phydev->speed == 2500) { + phy_write_mmd(phydev, MDIO_MMD_VEND2, + RTL8221B_UNKOWN_0xc40a, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND2, + RTL8221B_UNKOWN_0xc466, 0x2); + } else { + phy_write_mmd(phydev, MDIO_MMD_VEND2, + RTL8221B_UNKOWN_0xc40a, 0x0); + phy_write_mmd(phydev, MDIO_MMD_VEND2, + RTL8221B_UNKOWN_0xc466, 0x0); + } + + phydev->duplex = fdpx ? DUPLEX_FULL : DUPLEX_HALF; + return 0; +} + static struct phy_driver realtek_drvs[] = { { PHY_ID_MATCH_EXACT(0x00008201), @@ -922,7 +1381,7 @@ }, { PHY_ID_MATCH_EXACT(0x001cc916), .name = "RTL8211F Gigabit Ethernet", - .probe = rtl821x_probe, + .probe = &rtl8211f_probe, .config_init = &rtl8211f_config_init, .read_status = rtlgen_read_status, .config_intr = &rtl8211f_config_intr, @@ -998,6 +1457,7 @@ .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, }, { +#if 0 PHY_ID_MATCH_EXACT(0x001cc849), .name = "RTL8221B-VB-CG 2.5Gbps PHY", .get_features = rtl822x_get_features, @@ -1008,6 +1468,7 @@ .read_page = rtl821x_read_page, .write_page = rtl821x_write_page, }, { +#endif PHY_ID_MATCH_EXACT(0x001cc84a), .name = "RTL8221B-VM-CG 2.5Gbps PHY", .get_features = rtl822x_get_features, @@ -1051,6 +1512,19 @@ .handle_interrupt = genphy_handle_interrupt_no_ack, .suspend = genphy_suspend, .resume = genphy_resume, + }, { + PHY_ID_MATCH_EXACT(0x001cc849), + .name = "RTL8221B 2.5 Gigabit Ethernet", + .probe = rtl8221b_probe, + .config_init = rtl8221b_config_init, + .suspend = genphy_suspend, + .resume = genphy_resume, + .config_aneg = rtl8221b_config_aneg, + .read_status = rtl8221b_read_status, + .get_features = rtl8221b_get_features, + .get_sset_count = rtl8221b_get_sset_count, + .get_strings = rtl8221b_get_strings, + .get_stats = rtl8221b_get_stats, }, }; diff -ruw linux-6.4/drivers/net/phy/sfp.h linux-6.4-fbx/drivers/net/phy/sfp.h --- linux-6.4/drivers/net/phy/sfp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/sfp.h 2023-05-22 20:06:42.139797837 +0200 @@ -25,6 +25,7 @@ int (*module_eeprom_by_page)(struct sfp *sfp, const struct ethtool_module_eeprom *page, struct netlink_ext_ack *extack); + int (*get_sfp_state)(struct sfp *sfp, struct ethtool_sfp_state *st); }; int sfp_add_phy(struct sfp_bus *bus, struct phy_device *phydev); diff -ruw linux-6.4/drivers/net/phy/swphy.c linux-6.4-fbx/drivers/net/phy/swphy.c --- linux-6.4/drivers/net/phy/swphy.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/phy/swphy.c 2023-03-09 15:06:11.372234439 +0100 @@ -29,6 +29,7 @@ SWMII_SPEED_10 = 0, SWMII_SPEED_100, SWMII_SPEED_1000, + SWMII_SPEED_2500, SWMII_DUPLEX_HALF = 0, SWMII_DUPLEX_FULL, }; @@ -51,6 +52,10 @@ .lpagb = LPA_1000FULL | LPA_1000HALF, .estat = ESTATUS_1000_TFULL | ESTATUS_1000_THALF, }, + [SWMII_SPEED_2500] = { + .bmsr = BMSR_ESTATEN, + .lpagb = LPA_1000FULL | LPA_1000HALF, + }, }; static const struct swmii_regs duplex[] = { @@ -71,6 +76,8 @@ static int swphy_decode_speed(int speed) { switch (speed) { + case 2500: + return SWMII_SPEED_2500; case 1000: return SWMII_SPEED_1000; case 100: diff -ruw linux-6.4/drivers/net/ppp/ppp_generic.c linux-6.4-fbx/drivers/net/ppp/ppp_generic.c --- linux-6.4/drivers/net/ppp/ppp_generic.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ppp/ppp_generic.c 2023-05-22 20:06:42.139797837 +0200 @@ -178,6 +178,7 @@ netns_tracker ns_tracker; struct list_head clist; /* link in list of channels per unit */ rwlock_t upl; /* protects `ppp' and 'bridge' */ + int stopped; /* channel is stopped */ struct channel __rcu *bridge; /* "bridged" ppp channel */ #ifdef CONFIG_PPP_MULTILINK u8 avail; /* flag used in multilink stuff */ @@ -1646,10 +1647,28 @@ ppp_send_frame(ppp, skb); /* If there's no work left to do, tell the core net code that we can accept some more. */ - if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq)) + if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq)) { + /* only enable net queue if at least one + * channel is not stopped */ + struct list_head *list; + struct channel *pch; + bool need_wake; + + list = &ppp->channels; + need_wake = false; + while ((list = list->next) != &ppp->channels) { + pch = list_entry(list, struct channel, clist); + if (!pch->stopped) { + need_wake = true; + break; + } + } + + if (need_wake) netif_wake_queue(ppp->dev); else netif_stop_queue(ppp->dev); + } } else { kfree_skb(skb); } @@ -3005,10 +3024,24 @@ if (!pch) return; + pch->stopped = 0; ppp_channel_push(pch); } /* + * Callback from a channel when it want to prevent further transmit on it + */ +void +ppp_output_stop(struct ppp_channel *chan) +{ + struct channel *pch = chan->ppp; + + if (pch == 0) + return; + pch->stopped = 1; +} + +/* * Compression control. */ @@ -3602,6 +3635,7 @@ EXPORT_SYMBOL(ppp_input); EXPORT_SYMBOL(ppp_input_error); EXPORT_SYMBOL(ppp_output_wakeup); +EXPORT_SYMBOL(ppp_output_stop); EXPORT_SYMBOL(ppp_register_compressor); EXPORT_SYMBOL(ppp_unregister_compressor); MODULE_LICENSE("GPL"); diff -ruw linux-6.4/drivers/net/ppp/pptp.c linux-6.4-fbx/drivers/net/ppp/pptp.c --- linux-6.4/drivers/net/ppp/pptp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/ppp/pptp.c 2023-02-27 19:50:24.224303473 +0100 @@ -356,6 +356,7 @@ po = lookup_chan(ntohs(header->call_id), iph->saddr); if (po) { skb_dst_drop(skb); + skb->mark = 0; nf_reset_ct(skb); return sk_receive_skb(sk_pppox(po), skb, 0); } diff -ruw linux-6.4/drivers/net/tun.c linux-6.4-fbx/drivers/net/tun.c --- linux-6.4/drivers/net/tun.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/tun.c 2023-05-22 20:06:42.143797943 +0200 @@ -77,6 +77,10 @@ #include #include #include +#include +#include +#include +#include #include #include @@ -163,6 +167,31 @@ unsigned long updated ____cacheline_aligned_in_smp; }; +/* + * smalltun definitions + */ +#define SMALLTUN_MAGIC 0x6660 +#define SMALLTUN_VERSION 0x1 + +#define TYPE_MASK 0xf +#define TYPE_CLT (1 << 3) + +#define TYPE_TRIGGER 0x0 +#define TYPE_CHALLENGE 0x1 +#define TYPE_CLIENT_HELLO 0x2 +#define TYPE_SERVER_HELLO 0x3 + +#define TYPE_CLT_DATA (TYPE_CLT | 0x0) +#define TYPE_CLT_GET_PARAMS (TYPE_CLT | 0x1) +#define TYPE_CLT_PARAMS (TYPE_CLT | 0x2) + +struct smalltun_pkt_hdr { + u16 magic; + u8 version; + u8 flag_type; + u8 data[0]; +}; + #define TUN_NUM_FLOW_ENTRIES 1024 #define TUN_MASK_FLOW_ENTRIES (TUN_NUM_FLOW_ENTRIES - 1) @@ -182,6 +211,11 @@ kuid_t owner; kgid_t group; + struct smalltun_fp smalltun_fps[4]; + unsigned int smalltun_valid_count; + unsigned int smalltun_valid[4]; + struct rtable *smalltun_rt_cache[4]; + struct net_device *dev; netdev_features_t set_features; #define TUN_USER_FEATURES (NETIF_F_HW_CSUM|NETIF_F_TSO_ECN|NETIF_F_TSO| \ @@ -1035,6 +1069,184 @@ return 0; } +static int smalltun_is_fastpath(struct tun_struct *tun, + struct sk_buff *skb) +{ + struct iphdr *iph; + const struct smalltun_fp *fp; + struct rtable **prt_cache, *rt_cache; + struct flowi4 fl; + bool match; + size_t i; + + if (!tun->smalltun_valid_count) + return 0; + + if (skb->protocol != htons(ETH_P_IP)) + return 0; + + if (!pskb_may_pull(skb, sizeof(struct iphdr))) + return 0; + + iph = ip_hdr(skb); + + /* lookup smalltun fastpath */ + fp = NULL; + rt_cache = NULL; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) + continue; + + if (iph->daddr == tun->smalltun_fps[i].inner_dst) { + fp = &tun->smalltun_fps[i]; + prt_cache = &tun->smalltun_rt_cache[i]; + break; + } + } + + if (!fp) + return 0; + + if (fp->af != AF_INET) { + /* FIXME: implement IPv6 transport */ + return 0; + } + + if (!pskb_may_pull(skb, iph->ihl * 4)) + return 0; + + match = false; + for (i = 0; i < fp->rule_count; i++) { + const struct smalltun_rule *r = &fp->rules[i]; + unsigned int sport, dport; + + if (iph->protocol != r->proto) + continue; + + switch (iph->protocol) { + case IPPROTO_UDP: + { + const struct udphdr *udp; + udp = (struct udphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = ntohs(udp->source); + dport = ntohs(udp->dest); + break; + } + case IPPROTO_TCP: + { + const struct tcphdr *tcp; + tcp = (struct tcphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = ntohs(tcp->source); + dport = ntohs(tcp->dest); + break; + } + default: + match = true; + break; + } + + if (match) + break; + + if (r->src_port_start && r->src_port_end) { + if (sport < ntohs(r->src_port_start) || + sport > ntohs(r->src_port_end)) + continue; + } + + if (r->dst_port_start && r->dst_port_end) { + if (dport < ntohs(r->dst_port_start) || + dport > ntohs(r->dst_port_end)) + continue; + } + match = true; + } + + if (!match) + return 0; + + if (fp->af == AF_INET) { + struct iphdr *oiph; + struct udphdr *oudph; + struct smalltun_pkt_hdr *pkt; + unsigned int payload_len; + + payload_len = skb->len; + + if (skb_cow_head(skb, + sizeof (struct iphdr) + + sizeof (struct udphdr) + + sizeof (struct smalltun_pkt_hdr))) + return 0; + + pkt = skb_push(skb, sizeof (struct smalltun_pkt_hdr)); + oudph = skb_push(skb, sizeof (struct udphdr)); + skb_reset_transport_header(skb); + oiph = skb_push(skb, sizeof (struct iphdr)); + skb_reset_network_header(skb); + + /* ip */ + oiph->version = 4; + oiph->tos = 0; + oiph->id = 0; + oiph->ihl = 5; + oiph->frag_off = 0; + oiph->ttl = 64; + oiph->protocol = IPPROTO_UDP; + memcpy(&oiph->saddr, fp->outer_src, 4); + memcpy(&oiph->daddr, fp->outer_dst, 4); + + /* udp */ + oudph->source = fp->outer_src_port; + oudph->dest = fp->outer_dst_port; + oudph->len = htons(payload_len + sizeof (*oudph) + + sizeof (*pkt)); + oudph->check = 0; + + /* smalltun */ + pkt->magic = htons(SMALLTUN_MAGIC); + pkt->version = SMALLTUN_VERSION; + pkt->flag_type = TYPE_CLT_DATA; + + memset(&fl, 0x00, sizeof (fl)); + memcpy(&fl.saddr, fp->outer_src, 4); + memcpy(&fl.daddr, fp->outer_dst, 4); + + if (*prt_cache && (*prt_cache)->dst.obsolete > 0) { + rt_cache = *prt_cache; + *prt_cache = NULL; + ip_rt_put(rt_cache); + } + + rt_cache = *prt_cache; + if (!rt_cache) { + rt_cache = ip_route_output_key(&init_net, &fl); + if (IS_ERR(rt_cache)) { + pr_err("ip_route_output_key(%pI4): %li\n", + &fl.daddr, PTR_ERR(rt_cache)); + return 0; + } + + if (!rt_cache->dst.dev) { + pr_err("ip_route_output_key(%pI4): no dev\n", + &fl.daddr); + return 0; + } + + *prt_cache = rt_cache; + } + + skb_dst_set(skb, dst_clone(&rt_cache->dst)); + skb->dev = skb_dst(skb)->dev; + ip_local_out(&init_net, NULL, skb); + return 1; + } + + /* find route */ + + return 0; +} + /* Net device start xmit */ static void tun_automq_xmit(struct tun_struct *tun, struct sk_buff *skb) { @@ -1127,6 +1339,11 @@ */ skb_orphan(skb); + if (smalltun_is_fastpath(tun, skb)) { + rcu_read_unlock(); + return NETDEV_TX_OK; + } + nf_reset_ct(skb); if (ptr_ring_produce(&tfile->tx_ring, skb)) { @@ -3377,6 +3594,104 @@ ret = open_related_ns(&net->ns, get_net_ns); break; + case TUNSMALLTUNSETFP: + { + struct smalltun_fp fp; + unsigned int i; + int free_idx; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* look for duplicate */ + ret = 0; + free_idx = -1; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) { + if (free_idx == -1) + free_idx = i; + continue; + } + + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = -EEXIST; + break; + } + } + + if (ret) + break; + + if (free_idx == -1) { + ret = -ENOSPC; + break; + } + + memcpy(&tun->smalltun_fps[free_idx], &fp, sizeof (fp)); + tun->smalltun_valid[free_idx] = 1; + tun->smalltun_valid_count++; + netif_info(tun, tx_queued, tun->dev, + "new fp rule for %pI4 <=> %pI4 (%u rules)\n", + &fp.inner_src, + &fp.inner_dst, + fp.rule_count); + + if (fp.af == AF_INET) { + netif_info(tun, tx_queued, tun->dev, + "outer %pI4:%u <=> %pI4:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } else { + netif_info(tun, tx_queued, tun->dev, + "outer %pI6:%u <=> %pI6:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } + break; + } + + case TUNSMALLTUNDELFP: + { + struct smalltun_fp fp; + unsigned int i; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* lookup */ + ret = -ENOENT; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = 0; + break; + } + } + + if (ret) + break; + + tun->smalltun_valid[i] = 0; + tun->smalltun_valid_count--; + if (tun->smalltun_rt_cache[i]) { + ip_rt_put(tun->smalltun_rt_cache[i]); + tun->smalltun_rt_cache[i] = NULL; + } + + netif_info(tun, tx_queued, tun->dev, + "removed fp rule for %pI4 <=> %pI4\n", + &fp.inner_src, + &fp.inner_dst); + break; + } + default: ret = -EINVAL; break; diff -ruw linux-6.4/drivers/net/wireguard/device.c linux-6.4-fbx/drivers/net/wireguard/device.c --- linux-6.4/drivers/net/wireguard/device.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireguard/device.c 2023-11-07 13:38:43.994254834 +0100 @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff -ruw linux-6.4/drivers/net/wireless/ath/Kconfig linux-6.4-fbx/drivers/net/wireless/ath/Kconfig --- linux-6.4/drivers/net/wireless/ath/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/Kconfig 2023-05-22 20:06:42.179798901 +0200 @@ -37,6 +37,9 @@ This option enables tracepoints for atheros wireless drivers. Currently, ath9k makes use of this facility. +config ATH_REG_IGNORE + bool "ignore all eeprom regulation" + config ATH_REG_DYNAMIC_USER_REG_HINTS bool "Atheros dynamic user regulatory hints" depends on CFG80211_CERTIFICATION_ONUS diff -ruw linux-6.4/drivers/net/wireless/ath/ath.h linux-6.4-fbx/drivers/net/wireless/ath/ath.h --- linux-6.4/drivers/net/wireless/ath/ath.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath.h 2023-05-22 20:06:42.183799007 +0200 @@ -47,6 +47,7 @@ u32 rx_busy; u32 rx_frame; u32 tx_frame; + u32 rx_bss_frame; }; enum ath_device_state { @@ -186,6 +187,8 @@ int last_rssi; struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; + + int dfs_pulse_valid_diff_ts; }; static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common) diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/core.c linux-6.4-fbx/drivers/net/wireless/ath/ath10k/core.c --- linux-6.4/drivers/net/wireless/ath/ath10k/core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/core.c 2023-05-22 20:06:42.183799007 +0200 @@ -83,8 +83,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -95,6 +94,7 @@ .hw_filter_reset_required = true, .fw_diag_ce_download = false, .credit_size_workaround = false, + .uart_pin_workaround = true, .tx_stats_over_pktlog = true, .dynamic_sar_support = false, .hw_restart_disconnect = false, @@ -123,8 +123,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -164,8 +163,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -240,8 +238,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -280,8 +277,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -320,8 +316,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -363,8 +358,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -410,8 +404,7 @@ .decap_align_bytes = 1, .spectral_bin_discard = 4, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 11, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -463,8 +456,9 @@ /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz * or 2x2 160Mhz, long-guard-interval. */ - .vht160_mcs_rx_highest = 1560, - .vht160_mcs_tx_highest = 1560, + .vht_need_ext_nss = true, + .vht_over_supp_chan_width = 0, + .vht_over_ext_nss_bw = 2, .n_cipher_suites = 11, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -513,8 +507,9 @@ /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or * 1x1 160Mhz, long-guard-interval. */ - .vht160_mcs_rx_highest = 780, - .vht160_mcs_tx_highest = 780, + .vht_need_ext_nss = true, + .vht_over_supp_chan_width = 0, + .vht_over_ext_nss_bw = 2, .n_cipher_suites = 11, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -553,8 +548,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -595,8 +589,7 @@ .decap_align_bytes = 4, .spectral_bin_discard = 0, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 8, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -675,8 +668,7 @@ .decap_align_bytes = 1, .spectral_bin_discard = 4, .spectral_bin_offset = 0, - .vht160_mcs_rx_highest = 0, - .vht160_mcs_tx_highest = 0, + .vht_need_ext_nss = false, .n_cipher_suites = 11, .ast_skid_limit = 0x10, .num_wds_entries = 0x20, @@ -1241,6 +1233,7 @@ static int ath10k_fetch_cal_file(struct ath10k *ar) { char filename[100]; + unsigned int i; /* pre-cal--.bin */ scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", @@ -1254,6 +1247,11 @@ scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); + for (i = 0; filename[i]; i++) { + if (filename[i] == ':') + filename[i] = '_'; + } + ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); if (IS_ERR(ar->cal_file)) /* calibration file is optional, don't print any warnings */ @@ -1465,6 +1463,7 @@ const char *boardname, const char *fallback_boardname1, const char *fallback_boardname2, + const char *pci_boardname, const char *filename) { size_t len, magic_len; @@ -1509,7 +1508,11 @@ data += magic_len; len -= magic_len; - /* attempt to find boardname in the IE list */ + /* attempt to find pci_boardname in the IE list */ + ret = ath10k_core_search_bd(ar, pci_boardname, data, len); + + /* if we didn't find it try board name that */ + if (ret == -ENOENT) ret = ath10k_core_search_bd(ar, boardname, data, len); /* if we didn't find it and have a fallback name, try that */ @@ -1521,8 +1524,8 @@ if (ret == -ENOENT) { ath10k_err(ar, - "failed to fetch board data for %s from %s/%s\n", - boardname, ar->hw_params.fw.dir, filename); + "failed to fetch board data for %s or %s from %s/%s\n", + boardname, pci_boardname, ar->hw_params.fw.dir, filename); ret = -ENODATA; } @@ -1538,7 +1541,8 @@ static int ath10k_core_create_board_name(struct ath10k *ar, char *name, size_t name_len, bool with_variant, - bool with_chip_id) + bool with_chip_id, + bool force_pci_id) { /* strlen(',variant=') + strlen(ar->id.bdf_ext) */ char variant[9 + ATH10K_SMBIOS_BDF_EXT_STR_LENGTH] = { 0 }; @@ -1547,7 +1551,7 @@ scnprintf(variant, sizeof(variant), ",variant=%s", ar->id.bdf_ext); - if (ar->id.bmi_ids_valid) { + if (ar->id.bmi_ids_valid && !force_pci_id) { scnprintf(name, name_len, "bus=%s,bmi-chip-id=%d,bmi-board-id=%d%s", ath10k_bus_str(ar->hif.bus), @@ -1556,7 +1560,7 @@ goto out; } - if (ar->id.qmi_ids_valid) { + if (ar->id.qmi_ids_valid && !force_pci_id) { if (with_chip_id) scnprintf(name, name_len, "bus=%s,qmi-board-id=%x,qmi-chip-id=%x%s", @@ -1601,14 +1605,15 @@ int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type) { - char boardname[100], fallback_boardname1[100], fallback_boardname2[100]; + char boardname[100], fallback_boardname1[100], fallback_boardname2[100], + pci_boardname[100]; int ret; if (bd_ie_type == ATH10K_BD_IE_BOARD) { /* With variant and chip id */ ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname), true, - true); + true, false); if (ret) { ath10k_err(ar, "failed to create board name: %d", ret); return ret; @@ -1617,7 +1622,7 @@ /* Without variant and only chip-id */ ret = ath10k_core_create_board_name(ar, fallback_boardname1, sizeof(boardname), false, - true); + true, false); if (ret) { ath10k_err(ar, "failed to create 1st fallback board name: %d", ret); @@ -1627,12 +1632,20 @@ /* Without variant and without chip-id */ ret = ath10k_core_create_board_name(ar, fallback_boardname2, sizeof(boardname), false, - false); + false, false); if (ret) { ath10k_err(ar, "failed to create 2nd fallback board name: %d", ret); return ret; } + + ret = ath10k_core_create_board_name(ar, pci_boardname, + sizeof(pci_boardname), + false, false, true); + if (ret) { + ath10k_err(ar, "failed to create pci board name: %d", ret); + return ret; + } } else if (bd_ie_type == ATH10K_BD_IE_BOARD_EXT) { ret = ath10k_core_create_eboard_name(ar, boardname, sizeof(boardname)); @@ -1646,6 +1659,7 @@ ret = ath10k_core_fetch_board_data_api_n(ar, boardname, fallback_boardname1, fallback_boardname2, + pci_boardname, ATH10K_BOARD_API2_FILE); if (!ret) goto success; @@ -2540,6 +2554,7 @@ switch (ar->state) { case ATH10K_STATE_ON: + case ATH10K_STATE_PRE_ON: ar->state = ATH10K_STATE_RESTARTING; ath10k_halt(ar); ath10k_scan_finish(ar); diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/core.h linux-6.4-fbx/drivers/net/wireless/ath/ath10k/core.h --- linux-6.4/drivers/net/wireless/ath/ath10k/core.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/core.h 2023-05-22 20:06:42.183799007 +0200 @@ -698,10 +698,12 @@ void *cal_data; u32 enable_extd_tx_stats; u8 fw_dbglog_mode; + u32 burst_dur[4]; }; enum ath10k_state { ATH10K_STATE_OFF = 0, + ATH10K_STATE_PRE_ON, ATH10K_STATE_ON, /* When doing firmware recovery the device is first powered down. @@ -1018,6 +1020,7 @@ void *vaddr; } msa; u8 mac_addr[ETH_ALEN]; + const char *fem_name; enum ath10k_hw_rev hw_rev; u16 dev_id; @@ -1203,6 +1206,8 @@ struct work_struct restart_work; struct work_struct bundle_tx_work; struct work_struct tx_complete_work; + struct work_struct powerup_work; + bool powerup_pending; /* cycle count is reported twice for each visited channel during scan. * access protected by data_lock diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/debug.c linux-6.4-fbx/drivers/net/wireless/ath/ath10k/debug.c --- linux-6.4/drivers/net/wireless/ath/ath10k/debug.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/debug.c 2023-05-22 20:06:42.183799007 +0200 @@ -2513,6 +2513,79 @@ .llseek = default_llseek, }; +static ssize_t ath10k_write_burst_dur(struct file *file, const char __user *user_buf, + size_t count, loff_t *ppos) +{ + + struct ath10k *ar = file->private_data; + u32 dur[4]; + int ret; + int ac; + char buf[128]; + + simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count); + + /* make sure that buf is null terminated */ + buf[sizeof(buf) - 1] = 0; + + ret = sscanf(buf, "%u %u %u %u", &dur[0], &dur[1], &dur[2], &dur[3]); + + if (!ret) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_ON && + ar->state != ATH10K_STATE_RESTARTED) { + ret = -ENETDOWN; + goto exit; + } + + for (ac = 0; ac < 4; ac++) { + if (dur[ac] < MIN_BURST_DUR || dur[ac] > MAX_BURST_DUR) { + ret = -EINVAL; + goto exit; + } + + ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->aggr_burst, + (SM(ac, ATH10K_AGGR_BURST_AC) | + SM(dur[ac], ATH10K_AGGR_BURST_DUR))); + if (ret) { + ath10k_warn(ar, "failed to set aggr burst duration for ac %d: %d\n", ac, ret); + goto exit; + } + ar->debug.burst_dur[ac] = dur[ac]; + } + + ret = count; + +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath10k_read_burst_dur(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + int len = 0; + char buf[128]; + + len = scnprintf(buf, sizeof(buf) - len, "%u %u %u %u\n", + ar->debug.burst_dur[0], ar->debug.burst_dur[1], + ar->debug.burst_dur[2], ar->debug.burst_dur[3]); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_burst_dur = { + .read = ath10k_read_burst_dur, + .write = ath10k_write_burst_dur, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + int ath10k_debug_create(struct ath10k *ar) { ar->debug.cal_data = vzalloc(ATH10K_DEBUG_CAL_DATA_LEN); @@ -2600,6 +2673,9 @@ debugfs_create_file("ani_enable", 0600, ar->debug.debugfs_phy, ar, &fops_ani_enable); + debugfs_create_file("burst_dur", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_burst_dur); + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { debugfs_create_file("dfs_simulate_radar", 0200, ar->debug.debugfs_phy, ar, &fops_simulate_radar); diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/debug.h linux-6.4-fbx/drivers/net/wireless/ath/ath10k/debug.h --- linux-6.4/drivers/net/wireless/ath/ath10k/debug.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/debug.h 2023-02-27 20:52:16.423384193 +0100 @@ -81,6 +81,15 @@ __printf(2, 3) void ath10k_err(struct ath10k *ar, const char *fmt, ...); __printf(2, 3) void ath10k_warn(struct ath10k *ar, const char *fmt, ...); +#define ATH10K_AGGR_BURST_AC_MASK 0xff000000 +#define ATH10K_AGGR_BURST_AC_LSB 24 +#define ATH10K_AGGR_BURST_DUR_MASK 0x00ffffff +#define ATH10K_AGGR_BURST_DUR_LSB 0 + +/* burst duration in usec */ +#define MIN_BURST_DUR 0 +#define MAX_BURST_DUR 8000 + void ath10k_debug_print_hwfw_info(struct ath10k *ar); void ath10k_debug_print_board_info(struct ath10k *ar); void ath10k_debug_print_boot_info(struct ath10k *ar); diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/hw.h linux-6.4-fbx/drivers/net/wireless/ath/ath10k/hw.h --- linux-6.4/drivers/net/wireless/ath/ath10k/hw.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/hw.h 2023-05-22 20:06:42.187799114 +0200 @@ -579,11 +579,14 @@ /* Number of bytes to be discarded for each FFT sample */ int spectral_bin_discard; - /* The board may have a restricted NSS for 160 or 80+80 vs what it - * can do for 80Mhz. + /* The board may have a restricted NSS for 160 or 80+80 vs + * what it can do for 80Mhz. To handle this, we have to use + * Extended NSS support and overrides VHT capabilities from + * firmware */ - int vht160_mcs_rx_highest; - int vht160_mcs_tx_highest; + bool vht_need_ext_nss; + u32 vht_over_supp_chan_width; + u32 vht_over_ext_nss_bw; /* Number of ciphers supported (i.e First N) in cipher_suites array */ int n_cipher_suites; diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/mac.c linux-6.4-fbx/drivers/net/wireless/ath/ath10k/mac.c --- linux-6.4/drivers/net/wireless/ath/ath10k/mac.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/mac.c 2023-05-22 20:06:42.191799220 +0200 @@ -2524,30 +2524,6 @@ return tx_mcs_set; } -static u32 get_160mhz_nss_from_maxrate(int rate) -{ - u32 nss; - - switch (rate) { - case 780: - nss = 1; - break; - case 1560: - nss = 2; - break; - case 2106: - nss = 3; /* not support MCS9 from spec*/ - break; - case 3120: - nss = 4; - break; - default: - nss = 1; - } - - return nss; -} - static void ath10k_peer_assoc_h_vht(struct ath10k *ar, struct ieee80211_vif *vif, struct ieee80211_sta *sta, @@ -2555,13 +2531,16 @@ { const struct ieee80211_sta_vht_cap *vht_cap = &sta->deflink.vht_cap; struct ath10k_vif *arvif = (void *)vif->drv_priv; - struct ath10k_hw_params *hw = &ar->hw_params; + enum ieee80211_vht_chanwidth bw; struct cfg80211_chan_def def; enum nl80211_band band; const u16 *vht_mcs_mask; u8 ampdu_factor; - u8 max_nss, vht_mcs; - int i; + u8 rx_nss; + struct ieee80211_vht_cap ieee_vht_cap = { + .vht_cap_info = cpu_to_le32(vht_cap->cap), + .supp_mcs = vht_cap->vht_mcs, + }; if (WARN_ON(ath10k_mac_vif_chan(vif, &def))) return; @@ -2604,15 +2583,20 @@ /* Calculate peer NSS capability from VHT capabilities if STA * supports VHT. */ - for (i = 0, max_nss = 0, vht_mcs = 0; i < NL80211_VHT_NSS_MAX; i++) { - vht_mcs = __le16_to_cpu(vht_cap->vht_mcs.rx_mcs_map) >> - (2 * i) & 3; - - if ((vht_mcs != IEEE80211_VHT_MCS_NOT_SUPPORTED) && - vht_mcs_mask[i]) - max_nss = i + 1; + switch (arg->peer_phymode) { + case MODE_11AC_VHT160: + bw = IEEE80211_VHT_CHANWIDTH_160MHZ; + break; + case MODE_11AC_VHT80_80: + bw = IEEE80211_VHT_CHANWIDTH_80P80MHZ; + break; + default: + bw = IEEE80211_VHT_CHANWIDTH_80MHZ; + break; } - arg->peer_num_spatial_streams = min(sta->deflink.rx_nss, max_nss); + + rx_nss = ieee80211_get_vht_max_nss(&ieee_vht_cap, bw, 0, true, 0); + arg->peer_num_spatial_streams = rx_nss; arg->peer_vht_rates.rx_max_rate = __le16_to_cpu(vht_cap->vht_mcs.rx_highest); arg->peer_vht_rates.rx_mcs_set = @@ -2627,20 +2611,6 @@ */ if (arg->peer_phymode == MODE_11AC_VHT160 || arg->peer_phymode == MODE_11AC_VHT80_80) { - u32 rx_nss; - u32 max_rate; - - max_rate = arg->peer_vht_rates.rx_max_rate; - rx_nss = get_160mhz_nss_from_maxrate(max_rate); - - if (rx_nss == 0) - rx_nss = arg->peer_num_spatial_streams; - else - rx_nss = min(arg->peer_num_spatial_streams, rx_nss); - - max_rate = hw->vht160_mcs_tx_highest; - rx_nss = min(rx_nss, get_160mhz_nss_from_maxrate(max_rate)); - arg->peer_bw_rxnss_override = FIELD_PREP(WMI_PEER_NSS_MAP_ENABLE, 1) | FIELD_PREP(WMI_PEER_NSS_160MHZ_MASK, (rx_nss - 1)); @@ -4904,14 +4874,18 @@ vht_cap.vht_mcs.tx_mcs_map = cpu_to_le16(mcs_map); /* If we are supporting 160Mhz or 80+80, then the NIC may be able to do - * a restricted NSS for 160 or 80+80 vs what it can do for 80Mhz. Give - * user-space a clue if that is the case. + * a restricted NSS for 160 or 80+80 vs what it can do for 80Mhz. */ if ((vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) && - (hw->vht160_mcs_rx_highest != 0 || - hw->vht160_mcs_tx_highest != 0)) { - vht_cap.vht_mcs.rx_highest = cpu_to_le16(hw->vht160_mcs_rx_highest); - vht_cap.vht_mcs.tx_highest = cpu_to_le16(hw->vht160_mcs_tx_highest); + hw->vht_need_ext_nss) { + vht_cap.cap &= ~(IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK | + IEEE80211_VHT_CAP_EXT_NSS_BW_MASK); + vht_cap.cap |= hw->vht_over_supp_chan_width << + IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_SHIFT; + vht_cap.cap |= hw->vht_over_ext_nss_bw << + IEEE80211_VHT_CAP_EXT_NSS_BW_SHIFT; + vht_cap.vht_mcs.tx_highest |= + cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); } return vht_cap; @@ -5064,13 +5038,18 @@ const char *fem_name; int ret; + if (ar->fem_name) + fem_name = ar->fem_name; + else { node = ar->dev->of_node; if (!node) return -ENOENT; - ret = of_property_read_string_index(node, "ext-fem-name", 0, &fem_name); + ret = of_property_read_string_index(node, "ext-fem-name", + 0, &fem_name); if (ret) return -ENOENT; + } /* * If external Front End module used in hardware, then default base band timing @@ -5146,12 +5125,83 @@ return 0; } +static int ath10k_get_powered(struct ieee80211_hw *hw, bool *up, bool *busy) +{ + struct ath10k *ar = hw->priv; + *up = (ar->state == ATH10K_STATE_ON || + ar->state == ATH10K_STATE_PRE_ON); + *busy = ar->powerup_pending; + return 0; +} + +static int ath10k_set_powered(struct ieee80211_hw *hw) +{ + struct ath10k *ar = hw->priv; + + switch (ar->state) { + case ATH10K_STATE_OFF: + case ATH10K_STATE_PRE_ON: + break; + default: + return 0; + } + + if (ar->powerup_pending) + return 0; + + queue_work(ar->workqueue, &ar->powerup_work); + ar->powerup_pending = true; + return 0; +} + +static void ath10k_powerup_work(struct work_struct *work) +{ + struct ath10k *ar = container_of(work, struct ath10k, powerup_work); + int ret; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_OFF) { + mutex_unlock(&ar->conf_mutex); + return; + } + + ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); + if (ret) { + ath10k_err(ar, "Could not init hif: %d\n", ret); + goto err_off; + } + + ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, + &ar->normal_mode_fw); + if (ret) { + ath10k_err(ar, "Could not init core: %d\n", ret); + goto err_power_down; + } + + ar->state = ATH10K_STATE_PRE_ON; + ar->powerup_pending = false; + mutex_unlock(&ar->conf_mutex); + return; + +err_power_down: + ath10k_hif_power_down(ar); + +err_off: + ar->state = ATH10K_STATE_OFF; + + ar->powerup_pending = false; + mutex_unlock(&ar->conf_mutex); + return; +} + static int ath10k_start(struct ieee80211_hw *hw) { struct ath10k *ar = hw->priv; u32 param; int ret = 0; struct wmi_bb_timing_cfg_arg bb_timing = {0}; + bool skip_core_start = false; /* * This makes sense only when restarting hw. It is harmless to call @@ -5166,6 +5216,10 @@ case ATH10K_STATE_OFF: ar->state = ATH10K_STATE_ON; break; + case ATH10K_STATE_PRE_ON: + skip_core_start = true; + ar->state = ATH10K_STATE_ON; + break; case ATH10K_STATE_RESTARTING: ar->state = ATH10K_STATE_RESTARTED; break; @@ -5190,6 +5244,7 @@ spin_unlock_bh(&ar->data_lock); + if (!skip_core_start) { ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); if (ret) { ath10k_err(ar, "Could not init hif: %d\n", ret); @@ -5202,6 +5257,7 @@ ath10k_err(ar, "Could not init core: %d\n", ret); goto err_power_down; } + } if (ar->sys_cap_info & WMI_TLV_SYS_CAP_INFO_RFKILL) { ret = ath10k_mac_rfkill_config(ar); @@ -5370,6 +5426,9 @@ ath10k_drain_tx(ar); + cancel_work_sync(&ar->powerup_work); + ar->powerup_pending = false; + mutex_lock(&ar->conf_mutex); if (ar->state != ATH10K_STATE_OFF) { if (!ar->hw_rfkill_on) { @@ -9412,6 +9471,8 @@ static const struct ieee80211_ops ath10k_ops = { .tx = ath10k_mac_op_tx, .wake_tx_queue = ath10k_mac_op_wake_tx_queue, + .get_powered = ath10k_get_powered, + .set_powered = ath10k_set_powered, .start = ath10k_start, .stop = ath10k_stop, .config = ath10k_config, @@ -9626,6 +9687,7 @@ .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT(NL80211_CHAN_WIDTH_20) | BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_160) | BIT(NL80211_CHAN_WIDTH_80), #endif }, @@ -9809,6 +9871,8 @@ #define WRD_METHOD "WRDD" #define WRDD_WIFI (0x07) +#define ATH10K_DFS_PULSE_VALID_DIFF_TS 100 + static u32 ath10k_mac_wrdd_get_mcc(struct ath10k *ar, union acpi_object *wrdd) { union acpi_object *mcc_pkg; @@ -10022,11 +10086,13 @@ ieee80211_hw_set(ar->hw, SUPPORT_FAST_XMIT); ieee80211_hw_set(ar->hw, CONNECTION_MONITOR); ieee80211_hw_set(ar->hw, SUPPORTS_PER_STA_GTK); + ieee80211_hw_set(ar->hw, APVLAN_NEED_MCAST_TO_UCAST); ieee80211_hw_set(ar->hw, WANT_MONITOR_VIF); ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); ieee80211_hw_set(ar->hw, QUEUE_CONTROL); ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG); ieee80211_hw_set(ar->hw, REPORTS_LOW_ACK); + ieee80211_hw_set(ar->hw, SUPPORTS_VHT_EXT_NSS_BW); if (!test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) ieee80211_hw_set(ar->hw, SW_CRYPTO_CONTROL); @@ -10219,6 +10285,8 @@ if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { /* Init ath dfs pattern detector */ ar->ath_common.debug_mask = ATH_DBG_DFS; + ar->ath_common.dfs_pulse_valid_diff_ts = + ATH10K_DFS_PULSE_VALID_DIFF_TS; ar->dfs_detector = dfs_pattern_detector_init(&ar->ath_common, NL80211_DFS_UNSET); @@ -10266,6 +10334,9 @@ ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; + INIT_WORK(&ar->powerup_work, ath10k_powerup_work); + ar->powerup_pending = false; + ret = ieee80211_register_hw(ar->hw); if (ret) { ath10k_err(ar, "failed to register ieee80211: %d\n", ret); @@ -10277,6 +10348,7 @@ ar->hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_AP_VLAN); } +#ifndef CONFIG_ATH_REG_IGNORE if (!ath_is_world_regd(&ar->ath_common.reg_world_copy) && !ath_is_world_regd(&ar->ath_common.regulatory)) { ret = regulatory_hint(ar->hw->wiphy, @@ -10284,10 +10356,13 @@ if (ret) goto err_unregister; } +#endif return 0; +#ifndef CONFIG_ATH_REG_IGNORE err_unregister: +#endif ieee80211_unregister_hw(ar->hw); err_dfs_detector_exit: @@ -10305,6 +10380,7 @@ void ath10k_mac_unregister(struct ath10k *ar) { ieee80211_unregister_hw(ar->hw); + cancel_work_sync(&ar->powerup_work); if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) ar->dfs_detector->exit(ar->dfs_detector); diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/pci.c linux-6.4-fbx/drivers/net/wireless/ath/ath10k/pci.c --- linux-6.4/drivers/net/wireless/ath/ath10k/pci.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/pci.c 2024-01-19 17:01:19.849846593 +0100 @@ -9,6 +9,7 @@ #include #include #include +#include #include "core.h" #include "debug.h" @@ -30,6 +31,7 @@ static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; +static char *fem_name; module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); @@ -37,6 +39,9 @@ module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); +module_param(fem_name, charp, 0660); +MODULE_PARM_DESC(fem_name, "force FEM type"); + /* how long wait to wait for target to initialise, in ms */ #define ATH10K_PCI_TARGET_WAIT 3000 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 @@ -714,7 +719,8 @@ /* Check if the shared legacy irq is for us */ cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CAUSE_ADDRESS); - if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) + if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL) && + cause != 0xdeadbeef) return true; return false; @@ -2655,12 +2661,6 @@ return 0; } -static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) -{ - ath10k_pci_irq_disable(ar); - return ath10k_pci_qca99x0_chip_reset(ar); -} - static int ath10k_pci_safe_chip_reset(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); @@ -3524,7 +3524,7 @@ .get_num_banks = ath10k_pci_get_num_banks, }; -static int ath10k_pci_probe(struct pci_dev *pdev, +static int __ath10k_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_dev) { int ret = 0; @@ -3565,21 +3565,21 @@ case QCA99X0_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA99X0; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9984_1_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9984; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9888_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9888; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; @@ -3618,6 +3618,7 @@ ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; ar->ce_priv = &ar_pci->ce; + ar->fem_name = fem_name; ar->id.vendor = pdev->vendor; ar->id.device = pdev->device; ar->id.subsystem_vendor = pdev->subsystem_vendor; @@ -3776,6 +3777,23 @@ ath10k_pci_pm_suspend, ath10k_pci_pm_resume); +static int ath10k_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *pci_dev) +{ + int cnt = 0; + int rv; + do { + rv = __ath10k_pci_probe(pdev, pci_dev); + if (rv == 0) + return rv; + + pr_err("ath10k: failed to probe PCI : %d, retry-count: %d\n", rv, cnt); + mdelay(10); /* let the ath10k firmware gerbil take a small break */ + } while (cnt++ < 3); + + return rv; +} + static struct pci_driver ath10k_pci_driver = { .name = "ath10k_pci", .id_table = ath10k_pci_id_table, diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/thermal.c linux-6.4-fbx/drivers/net/wireless/ath/ath10k/thermal.c --- linux-6.4/drivers/net/wireless/ath/ath10k/thermal.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/thermal.c 2023-05-22 20:06:42.195799326 +0200 @@ -160,7 +160,9 @@ if (!test_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map)) return 0; - cdev = thermal_cooling_device_register("ath10k_thermal", ar, + cdev = thermal_cooling_device_register_with_parent(ar->dev, + "ath10k_thermal", + ar, &ath10k_thermal_ops); if (IS_ERR(cdev)) { diff -ruw linux-6.4/drivers/net/wireless/ath/ath10k/wmi.c linux-6.4-fbx/drivers/net/wireless/ath/ath10k/wmi.c --- linux-6.4/drivers/net/wireless/ath/ath10k/wmi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath10k/wmi.c 2023-05-22 20:06:42.199799433 +0200 @@ -5815,12 +5815,14 @@ survey->noise = noise_floor; survey->time = div_u64(total, cc_freq_hz); survey->time_busy = div_u64(busy, cc_freq_hz); - survey->time_rx = div_u64(rx_bss, cc_freq_hz); + survey->time_rx = div_u64(rx, cc_freq_hz); survey->time_tx = div_u64(tx, cc_freq_hz); + survey->time_bss_rx = div_u64(rx_bss, cc_freq_hz); survey->filled |= (SURVEY_INFO_NOISE_DBM | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY | SURVEY_INFO_TIME_RX | + SURVEY_INFO_TIME_BSS_RX | SURVEY_INFO_TIME_TX); exit: spin_unlock_bh(&ar->data_lock); diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/Kconfig linux-6.4-fbx/drivers/net/wireless/ath/ath11k/Kconfig --- linux-6.4/drivers/net/wireless/ath/ath11k/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/Kconfig 2023-05-22 20:06:42.199799433 +0200 @@ -57,3 +57,15 @@ Enable ath11k spectral scan support Say Y to enable access to the FFT/spectral data via debugfs. + +config ATH11K_SMALL_DP_RINGS + bool "ath11k small datapath DMA rings for memory challenged platforms" + depends on ATH11K + help + Select this to lower the memory requirements for DMA rings + in the datapath code. This can free up to 17 MiB of RAM per + chip. + +config ATH11K_QCN9074_FIXED_MEM_REGION + bool "QCA ath11k fixed memory region mode on QCN9074" + depends on ATH11K diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/core.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/core.c --- linux-6.4/drivers/net/wireless/ath/ath11k/core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/core.c 2024-03-18 14:40:14.839741005 +0100 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -32,6 +32,15 @@ MODULE_PARM_DESC(frame_mode, "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); +bool ath11k_ftm_mode; +module_param_named(ftm_mode, ath11k_ftm_mode, bool, 0644); +MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); + +static char *ath11k_board_variant; +module_param_named(board_variant, ath11k_board_variant, charp, 0644); +MODULE_PARM_DESC(board_variant, "board variant to use for bdf lookup"); + + static const struct ath11k_hw_params ath11k_hw_params[] = { { .hw_rev = ATH11K_HW_IPQ8074, @@ -51,7 +60,7 @@ .host_ce_config = ath11k_host_ce_config_ipq8074, .ce_count = 12, .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, - .target_ce_count = 11, + .target_ce_count = 12, .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq8074, .svc_to_ce_map_len = 21, .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, @@ -88,6 +97,7 @@ .num_vdevs = 16 + 1, .num_peers = 512, .supports_suspend = false, + .supports_ap_vlan = true, .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), .supports_regdb = false, .fix_l1ss = true, @@ -116,6 +126,7 @@ .tcl_ring_retry = true, .tx_ring_size = DP_TCL_DATA_RING_SIZE, .smp2p_wow_exit = false, + .ce_fwlog_enable = false, }, { .hw_rev = ATH11K_HW_IPQ6018_HW10, @@ -135,7 +146,7 @@ .host_ce_config = ath11k_host_ce_config_ipq8074, .ce_count = 12, .target_ce_config = ath11k_target_ce_config_wlan_ipq8074, - .target_ce_count = 11, + .target_ce_count = 12, .svc_to_ce_map = ath11k_target_service_to_ce_map_wlan_ipq6018, .svc_to_ce_map_len = 19, .ce_ie_addr = &ath11k_ce_ie_addr_ipq8074, @@ -169,6 +180,7 @@ .num_vdevs = 16 + 1, .num_peers = 512, .supports_suspend = false, + .supports_ap_vlan = true, .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), .supports_regdb = false, .fix_l1ss = true, @@ -198,6 +210,7 @@ .tx_ring_size = DP_TCL_DATA_RING_SIZE, .smp2p_wow_exit = false, .support_fw_mac_sequence = false, + .ce_fwlog_enable = false, }, { .name = "qca6390 hw2.0", @@ -250,6 +263,7 @@ .num_vdevs = 16 + 1, .num_peers = 512, .supports_suspend = true, + .supports_ap_vlan = false, .hal_desc_sz = sizeof(struct hal_rx_desc_ipq8074), .supports_regdb = false, .fix_l1ss = true, @@ -282,6 +296,7 @@ .tx_ring_size = DP_TCL_DATA_RING_SIZE, .smp2p_wow_exit = false, .support_fw_mac_sequence = true, + .ce_fwlog_enable = false, }, { .name = "qcn9074 hw1.0", @@ -334,6 +349,7 @@ .num_vdevs = 8, .num_peers = 128, .supports_suspend = false, + .supports_ap_vlan = true, .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), .supports_regdb = false, .fix_l1ss = true, @@ -350,7 +366,7 @@ .bios_sar_capa = NULL, .m3_fw_support = true, .fixed_bdf_addr = false, - .fixed_mem_region = false, + .fixed_mem_region = IS_ENABLED(CONFIG_ATH11K_QCN9074_FIXED_MEM_REGION), .static_window_map = true, .hybrid_bus_type = false, .fixed_fw_mem = false, @@ -363,6 +379,7 @@ .tx_ring_size = DP_TCL_DATA_RING_SIZE, .smp2p_wow_exit = false, .support_fw_mac_sequence = false, + .ce_fwlog_enable = true, }, { .name = "wcn6855 hw2.0", @@ -415,6 +432,7 @@ .num_vdevs = 16 + 1, .num_peers = 512, .supports_suspend = true, + .supports_ap_vlan = false, .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), .supports_regdb = true, .fix_l1ss = false, @@ -497,6 +515,7 @@ .num_vdevs = 16 + 1, .num_peers = 512, .supports_suspend = true, + .supports_ap_vlan = false, .hal_desc_sz = sizeof(struct hal_rx_desc_wcn6855), .supports_regdb = true, .fix_l1ss = false, @@ -580,6 +599,7 @@ .num_vdevs = 16 + 1, .num_peers = 512, .supports_suspend = false, + .supports_ap_vlan = false, .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), .supports_regdb = true, .fix_l1ss = false, @@ -621,6 +641,7 @@ .max_radios = MAX_RADIOS_5018, .bdf_addr = 0x4BA00000, /* hal_desc_sz and hw ops are similar to qcn9074 */ + .supports_ap_vlan = false, .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9074), .qmi_service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074, .ring_mask = &ath11k_hw_ring_mask_ipq8074, @@ -966,7 +987,10 @@ /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ char variant[9 + ATH11K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; - if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') + if (ath11k_board_variant) + scnprintf(variant, sizeof(variant), ",variant=%s", + ath11k_board_variant); + else if (with_variant && ab->qmi.target.bdf_ext[0] != '\0') scnprintf(variant, sizeof(variant), ",variant=%s", ab->qmi.target.bdf_ext); @@ -1032,9 +1056,14 @@ void ath11k_core_free_bdf(struct ath11k_base *ab, struct ath11k_board_data *bd) { + struct ath11k_bid_override *ov, *tmp; + if (!IS_ERR(bd->fw)) release_firmware(bd->fw); + list_for_each_entry_safe(ov, tmp, &ab->board_id_overrides, next) + kfree(ov); + memset(bd, 0, sizeof(*bd)); } @@ -1354,6 +1383,11 @@ { int ret; + if (ath11k_ftm_mode) { + ab->fw_mode = ATH11K_FIRMWARE_MODE_FTM; + ath11k_info(ab, "Booting in factory test mode\n"); + } + ret = ath11k_qmi_init_service(ab); if (ret) { ath11k_err(ab, "failed to initialize qmi :%d\n", ret); @@ -1576,11 +1610,15 @@ return ret; } +unsigned int ce_fwlog = 1; +module_param_named(ce_fwlog, ce_fwlog, uint, 0644); +MODULE_PARM_DESC(ce_fwlog, "Enable/Disable CE based FW logging"); + int ath11k_core_qmi_firmware_ready(struct ath11k_base *ab) { int ret; - ret = ath11k_core_start_firmware(ab, ATH11K_FIRMWARE_MODE_NORMAL); + ret = ath11k_core_start_firmware(ab, ab->fw_mode); if (ret) { ath11k_err(ab, "failed to start firmware: %d\n", ret); return ret; @@ -1628,6 +1666,15 @@ goto err_core_stop; } ath11k_hif_irq_enable(ab); + + if (ab->hw_params.ce_fwlog_enable && ce_fwlog) { + ret = ath11k_enable_fwlog(ab); + if (ret < 0) { + ath11k_err(ab, "failed to enable fwlog: %d\n", ret); + goto err_core_stop; + } + } + mutex_unlock(&ab->core_lock); return 0; @@ -1745,7 +1792,8 @@ for (i = 0; i < ab->num_radios; i++) { pdev = &ab->pdevs[i]; ar = pdev->ar; - if (!ar || ar->state == ATH11K_STATE_OFF) + if (!ar || ar->state == ATH11K_STATE_OFF || + ar->state == ATH11K_STATE_FTM) continue; ieee80211_stop_queues(ar->hw); @@ -1814,6 +1862,10 @@ ath11k_warn(ab, "device is wedged, will not restart radio %d\n", i); break; + case ATH11K_STATE_FTM: + ath11k_dbg(ab, ATH11K_DBG_TESTMODE, + "fw mode reset done radio %d\n", i); + break; } mutex_unlock(&ar->conf_mutex); } @@ -1932,6 +1984,104 @@ return 0; } +static int load_board_id_override(struct ath11k_base *ab) +{ + struct ath11k_bid_override *ov, *tmp; + const struct firmware *fw; + const char *p, *end; + size_t len; + int ret, count; + + fw = ath11k_core_firmware_request(ab, ATH11K_BOARD_OVERRIDE_FILE); + if (IS_ERR(fw)) { + /* file is optional */ + if (PTR_ERR(fw) == -ENOENT) + return 0; + return PTR_ERR(fw); + } + + /* format is = [...] */ + p = fw->data; + len = fw->size; + end = p + len; + count = 0; + + while (1) { + const char *pstart; + char *ppath, *pbid, endc; + unsigned int seg, bus, slot, func; + u16 board_id; + + while (p != end && isspace(*p)) + p++; + if (p == end) + break; + + pstart = p; + while (p != end && !isspace(*p)) + p++; + + if (p == end) { + ret = -EINVAL; + goto fail; + } + + ppath = kstrndup(pstart, p - pstart, GFP_KERNEL); + if (!pstart) { + ret = -ENOMEM; + goto fail; + } + + pbid = strchr(ppath, '='); + if (!pbid) { + ath11k_err(ab, "bad key=value in override file\n"); + ret = -EINVAL; + kfree(ppath); + goto fail; + } + + *pbid++ = 0; + + ret = sscanf(ppath, "pci:%x:%x:%x.%x%c", &seg, &bus, &slot, + &func, &endc); + if (ret != 4) { + ath11k_err(ab, "invalid pci dev in override file\n"); + kfree(ppath); + ret = -EINVAL; + goto fail; + } + + if (kstrtou16(pbid, 0, &board_id)) { + ath11k_err(ab, "invalid board-id in override file\n"); + kfree(ppath); + ret = -EINVAL; + goto fail; + } + + ov = kzalloc(sizeof (*ov), GFP_KERNEL); + ov->domain = seg; + ov->bus_nr = bus; + ov->slot = slot; + ov->func = func; + ov->board_id = board_id; + list_add_tail(&ov->next, &ab->board_id_overrides); + count++; + } + + ath11k_info(ab, "loaded %d entries from board-id override file\n", + count); + release_firmware(fw); + return 0; + +fail: + ath11k_err(ab, "invalid board-id override file content\n"); + release_firmware(fw); + list_for_each_entry_safe(ov, tmp, &ab->board_id_overrides, next) + kfree(ov); + INIT_LIST_HEAD(&ab->board_id_overrides); + return ret; +} + int ath11k_core_pre_init(struct ath11k_base *ab) { int ret; @@ -1942,6 +2092,10 @@ return ret; } + ret = load_board_id_override(ab); + if (ret) + return ret; + return 0; } EXPORT_SYMBOL(ath11k_core_pre_init); @@ -2011,6 +2165,7 @@ init_completion(&ab->reconfigure_complete); init_completion(&ab->recovery_start); + INIT_LIST_HEAD(&ab->board_id_overrides); INIT_LIST_HEAD(&ab->peers); init_waitqueue_head(&ab->peer_mapping_wq); init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/core.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/core.h --- linux-6.4/drivers/net/wireless/ath/ath11k/core.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/core.h 2023-10-25 17:59:16.188036994 +0200 @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH11K_CORE_H @@ -157,12 +157,14 @@ }; extern bool ath11k_cold_boot_cal; +extern bool ath11k_ftm_mode; #define ATH11K_IRQ_NUM_MAX 52 #define ATH11K_EXT_IRQ_NUM_MAX 16 struct ath11k_ext_irq_grp { struct ath11k_base *ab; + char *name; u32 irqs[ATH11K_EXT_IRQ_NUM_MAX]; u32 num_irq; u32 grp_id; @@ -277,6 +279,7 @@ ATH11K_FLAG_FIXED_MEM_RGN, ATH11K_FLAG_DEVICE_INIT_DONE, ATH11K_FLAG_MULTI_MSI_VECTORS, + ATH11K_FLAG_FTM_SEGMENTED, }; enum ath11k_monitor_flags { @@ -367,6 +370,8 @@ #ifdef CONFIG_ATH11K_DEBUGFS struct dentry *debugfs_twt; #endif /* CONFIG_ATH11K_DEBUGFS */ + u64 tbtt_offset; + struct work_struct update_bcn_template_work; }; struct ath11k_vif_iter { @@ -530,6 +535,7 @@ ATH11K_STATE_RESTARTING, ATH11K_STATE_RESTARTED, ATH11K_STATE_WEDGED, + ATH11K_STATE_FTM, /* Add other states as required */ }; @@ -540,6 +546,12 @@ #define ATH11K_INVALID_RSSI_EMPTY -128 +struct ath11k_ftm_event_obj { + u32 data_pos; + u32 expected_seq; + u8 *eventdata; +}; + struct ath11k_fw_stats { struct dentry *debugfs_fwstats; u32 pdev_id; @@ -572,6 +584,7 @@ u32 mem_offset; u32 module_id_bitmap[MAX_MODULE_ID_BITMAP_WORDS]; struct ath11k_debug_dbr *dbr_debug[WMI_DIRECT_BUF_MAX]; + u32 mem_addr; }; struct ath11k_per_peer_tx_stats { @@ -709,6 +722,8 @@ u32 last_ppdu_id; u32 cached_ppdu_id; int monitor_vdev_id; + struct completion fw_mode_reset; + u8 ftm_msgref; #ifdef CONFIG_ATH11K_DEBUGFS struct ath11k_debug debug; #endif @@ -835,9 +850,19 @@ u16 hw_rev; }; +struct ath11k_bid_override { + unsigned int domain; + unsigned int bus_nr; + unsigned int slot; + unsigned int func; + u16 board_id; + struct list_head next; +}; + /* Master structure to hold the hw data which may be used in core module */ struct ath11k_base { enum ath11k_hw_rev hw_rev; + enum ath11k_firmware_mode fw_mode; struct platform_device *pdev; struct device *dev; struct ath11k_qmi qmi; @@ -847,6 +872,7 @@ /* HW channel counters frequency value in hertz common to all MACs */ u32 cc_freq_hz; + struct list_head board_id_overrides; struct ath11k_htc htc; struct ath11k_dp dp; @@ -898,10 +924,12 @@ bool wmi_ready; u32 wlan_init_status; int irq_num[ATH11K_IRQ_NUM_MAX]; + char *irq_name[ATH11K_IRQ_NUM_MAX]; struct ath11k_ext_irq_grp ext_irq_grp[ATH11K_EXT_IRQ_GRP_NUM_MAX]; struct ath11k_targ_cap target_caps; u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; bool pdevs_macaddr_valid; + bool enable_cold_boot_cal; int bd_api; struct ath11k_hw_params hw_params; @@ -948,6 +976,7 @@ u32 fw_crash_counter; } stats; u32 pktlog_defs_checksum; + struct ath11k_ftm_event_obj ftm_event_obj; struct ath11k_dbring_cap *db_caps; u32 num_db_cap; diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/dbring.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dbring.c --- linux-6.4/drivers/net/wireless/ath/ath11k/dbring.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dbring.c 2023-05-22 20:06:42.203799539 +0200 @@ -80,6 +80,8 @@ buff->paddr = paddr; + dma_sync_single_for_device(ab->dev, paddr, ring->buf_sz, DMA_FROM_DEVICE); + cookie = FIELD_PREP(DP_RXDMA_BUF_COOKIE_PDEV_ID, ar->pdev_idx) | FIELD_PREP(DP_RXDMA_BUF_COOKIE_BUF_ID, buf_id); diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/debugfs.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/debugfs.c --- linux-6.4/drivers/net/wireless/ath/ath11k/debugfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/debugfs.c 2023-05-22 20:06:42.203799539 +0200 @@ -15,6 +15,7 @@ #include "debugfs_htt_stats.h" #include "peer.h" #include "hif.h" +#include "qmi.h" static const char *htt_bp_umac_ring[HTT_SW_UMAC_RING_IDX_MAX] = { "REO2SW1_RING", @@ -556,6 +557,104 @@ .llseek = default_llseek, }; + +static ssize_t ath11k_athdiag_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath11k *ar = file->private_data; + u8 *buf; + int ret; + + if (*ppos <= 0) + return -EINVAL; + + if (!count) + return 0; + + mutex_lock(&ar->conf_mutex); + + buf = vmalloc(count); + if (!buf) { + ret = -ENOMEM; + goto exit; + } + + ret = ath11k_qmi_mem_read(ar->ab, *ppos, buf, count); + if (ret < 0) { + ath11k_warn(ar->ab, "failed to read address 0x%08x via diagnose window from debugfs: %d\n", + (u32)(*ppos), ret); + goto exit; + } + + ret = copy_to_user(user_buf, buf, count); + if (ret) { + ret = -EFAULT; + goto exit; + } + + count -= ret; + *ppos += count; + ret = count; +exit: + vfree(buf); + mutex_unlock(&ar->conf_mutex); + + return ret; +} + +static ssize_t ath11k_athdiag_write(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath11k *ar = file->private_data; + u8 *buf; + int ret; + + if (*ppos <= 0) + return -EINVAL; + + if (!count) + return 0; + + mutex_lock(&ar->conf_mutex); + + buf = vmalloc(count); + if (!buf) { + ret = -ENOMEM; + goto exit; + } + + ret = copy_from_user(buf, user_buf, count); + if (ret) { + ret = -EFAULT; + goto exit; + } + + ret = ath11k_qmi_mem_write(ar->ab, *ppos, buf, count); + if (ret < 0) { + ath11k_warn(ar->ab, "failed to write address 0x%08x via diagnose window from debugfs: %d\n", + (u32)(*ppos), ret); + goto exit; + } + + *ppos += count; + ret = count; + +exit: + vfree(buf); + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_athdiag = { + .read = ath11k_athdiag_read, + .write = ath11k_athdiag_write, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + static ssize_t ath11k_write_enable_extd_tx_stats(struct file *file, const char __user *ubuf, size_t count, loff_t *ppos) @@ -1648,6 +1747,10 @@ &fops_reset_ps_duration); } + debugfs_create_file("athdiag", S_IRUSR | S_IWUSR, + ar->debug.debugfs_pdev, ar, + &fops_athdiag); + return 0; } diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/dp.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp.c --- linux-6.4/drivers/net/wireless/ath/ath11k/dp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp.c 2023-11-07 18:01:55.969707425 +0100 @@ -281,8 +281,18 @@ case HAL_RXDMA_MONITOR_STATUS: params.low_threshold = num_entries >> 3; params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; - params.intr_batch_cntr_thres_entries = 0; params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; + /* In case of PCI chipsets, we dont have PPDU end interrupts, + * so MONITOR STATUS ring is reaped by receiving MSI from srng. + * Keep batch threshold as 8 so that an interrupt is received for + * every 4 frames in MONITOR_STATUS ring. + */ + if ((type == HAL_RXDMA_MONITOR_STATUS) && + (params.flags & HAL_SRNG_FLAGS_MSI_INTR)) + params.intr_batch_cntr_thres_entries = 4; + else + params.intr_batch_cntr_thres_entries = 0; + break; case HAL_WBM2SW_RELEASE: if (ring_num < 3) { diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/dp.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp.h --- linux-6.4/drivers/net/wireless/ath/ath11k/dp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp.h 2023-05-22 20:06:42.207799646 +0200 @@ -205,7 +205,6 @@ #define DP_WBM_RELEASE_RING_SIZE 64 #define DP_TCL_DATA_RING_SIZE 512 #define DP_TCL_DATA_RING_SIZE_WCN6750 2048 -#define DP_TX_COMP_RING_SIZE 32768 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE #define DP_TCL_CMD_RING_SIZE 32 #define DP_TCL_STATUS_RING_SIZE 32 @@ -219,13 +218,22 @@ #define DP_RXDMA_BUF_RING_SIZE 4096 #define DP_RXDMA_REFILL_RING_SIZE 2048 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 -#define DP_RXDMA_MON_STATUS_RING_SIZE 1024 -#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 -#define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 #define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 #define DP_RX_RELEASE_RING_NUM 3 +#ifdef CONFIG_ATH11K_SMALL_DP_RINGS +# define DP_TX_COMP_RING_SIZE 8192 +# define DP_RXDMA_MON_STATUS_RING_SIZE 512 +# define DP_RXDMA_MONITOR_BUF_RING_SIZE 128 +# define DP_RXDMA_MONITOR_DST_RING_SIZE 128 +#else +# define DP_TX_COMP_RING_SIZE 32768 +# define DP_RXDMA_MON_STATUS_RING_SIZE 1024 +# define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 +# define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 +#endif + #define DP_RX_BUFFER_SIZE 2048 #define DP_RX_BUFFER_SIZE_LITE 1024 #define DP_RX_BUFFER_ALIGN_SIZE 128 diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/dp_rx.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_rx.c --- linux-6.4/drivers/net/wireless/ath/ath11k/dp_rx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_rx.c 2024-03-27 19:01:35.032950662 +0100 @@ -783,6 +783,7 @@ dp->reo_cmd_cache_flush_count++; /* Flush and invalidate aged REO desc from HW cache */ +retry: list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, list) { if (dp->reo_cmd_cache_flush_count > DP_REO_DESC_FREE_THRESHOLD || @@ -795,6 +796,7 @@ ath11k_dp_reo_cache_flush(ab, &elem->data); kfree(elem); spin_lock_bh(&dp->reo_cmd_lock); + goto retry; } } spin_unlock_bh(&dp->reo_cmd_lock); @@ -1621,14 +1623,20 @@ u8 pdev_id; pdev_id = FIELD_GET(HTT_T2H_PPDU_STATS_INFO_PDEV_ID, data->hdr); + + rcu_read_lock(); + ar = ath11k_mac_get_ar_by_pdev_id(ab, pdev_id); if (!ar) { ath11k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); - return; + goto out; } trace_ath11k_htt_pktlog(ar, data->payload, hdr->size, ar->ab->pktlog_defs_checksum); + +out: + rcu_read_unlock(); } static void ath11k_htt_backpressure_event_handler(struct ath11k_base *ab, @@ -5233,10 +5241,13 @@ pmon->mon_ppdu_status == DP_PPDU_STATUS_START && hal_status == HAL_TLV_STATUS_PPDU_DONE) { rx_mon_stats->status_ppdu_done++; + if (!ab->hw_params.full_monitor_mode) { pmon->mon_ppdu_status = DP_PPDU_STATUS_DONE; - ath11k_dp_rx_mon_dest_process(ar, mac_id, budget, napi); + ath11k_dp_rx_mon_dest_process(ar, mac_id, + budget, napi); pmon->mon_ppdu_status = DP_PPDU_STATUS_START; } + } if (ppdu_info->peer_id == HAL_INVALID_PEERID || hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/dp_rx.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_rx.h --- linux-6.4/drivers/net/wireless/ath/ath11k/dp_rx.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_rx.h 2023-03-15 19:52:23.533979623 +0100 @@ -9,7 +9,7 @@ #include "rx_desc.h" #include "debug.h" -#define DP_MAX_NWIFI_HDR_LEN 30 +#define DP_MAX_NWIFI_HDR_LEN 36 #define DP_RX_MPDU_ERR_FCS BIT(0) #define DP_RX_MPDU_ERR_DECRYPT BIT(1) diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/dp_tx.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_tx.c --- linux-6.4/drivers/net/wireless/ath/ath11k/dp_tx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_tx.c 2023-12-05 17:14:42.303715125 +0100 @@ -79,6 +79,47 @@ } } +#define HTT_META_DATA_ALIGNMENT 0x8 + +static int ath11k_dp_metadata_align_skb(struct sk_buff *skb, u8 align_len) +{ + int ret; + + ret = skb_cow_head(skb, align_len); + if (unlikely(ret)) + return ret; + + skb_push(skb, align_len); + memset(skb->data, 0, align_len); + return 0; +} + +static int ath11k_dp_prepare_htt_metadata(struct sk_buff *skb, + u8 *htt_metadata_size) +{ + u8 htt_desc_size; + /* Size rounded of multiple of 8 bytes */ + u8 htt_desc_size_aligned; + struct htt_tx_msdu_desc_ext *desc_ext; + int ret; + + htt_desc_size = sizeof(*desc_ext); + htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT); + + ret = ath11k_dp_metadata_align_skb(skb, htt_desc_size_aligned); + if (unlikely(ret)) + return ret; + + desc_ext = (struct htt_tx_msdu_desc_ext *)skb->data; + desc_ext->info0 = + __cpu_to_le32(FIELD_PREP(HTT_TX_MSDU_DESC_INFO0_VALID_ENCRYPT_TYPE, 1) | + FIELD_PREP(HTT_TX_MSDU_DESC_INFO0_ENCRYPT_TYPE, 0) | + FIELD_PREP(HTT_TX_MSDU_DESC_INFO0_HOST_TX_DESC_POOL, 1)); + *htt_metadata_size = htt_desc_size_aligned; + + return 0; +} + int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, struct ath11k_sta *arsta, struct sk_buff *skb) { @@ -97,9 +138,7 @@ u32 ring_selector = 0; u8 ring_map = 0; bool tcl_ring_retry; - - if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) - return -ESHUTDOWN; + u8 align_pad, htt_meta_size = 0; if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && !ieee80211_is_data(hdr->frame_control))) @@ -208,15 +247,42 @@ goto fail_remove_idr; } + /* Add metadata for sw encrypted vlan group traffic */ + if (!test_bit(ATH11K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags) && + !(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && + !info->control.hw_key && + ieee80211_has_protected(hdr->frame_control)) { + /* HW requirement is that metadata should always point to a + * 8-byte aligned address. So we add alignment pad to start of + * buffer. HTT Metadata should be ensured to be multiple of 8-bytes + * to get 8-byte aligned start address along with align_pad added + */ + align_pad = ((unsigned long)skb->data) & (HTT_META_DATA_ALIGNMENT - 1); + ret = ath11k_dp_metadata_align_skb(skb, align_pad); + if (unlikely(ret)) + goto fail_remove_idr; + + ti.pkt_offset += align_pad; + ret = ath11k_dp_prepare_htt_metadata(skb, &htt_meta_size); + if (unlikely(ret)) + goto fail_pull_skb; + + ti.pkt_offset += htt_meta_size; + ti.meta_data_flags |= HTT_TCL_META_DATA_VALID_HTT; + ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1); + ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; + ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; + } + ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) { atomic_inc(&ab->soc_stats.tx_err.misc_fail); ath11k_warn(ab, "failed to DMA map data Tx buffer\n"); ret = -ENOMEM; - goto fail_remove_idr; + goto fail_pull_skb; } - ti.data_len = skb->len; + ti.data_len = skb->len - ti.pkt_offset; skb_cb->paddr = ti.paddr; skb_cb->vif = arvif->vif; skb_cb->ar = ar; @@ -271,6 +337,10 @@ fail_unmap_dma: dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); +fail_pull_skb: + if (ti.pkt_offset) + skb_pull(skb, ti.pkt_offset); + fail_remove_idr: spin_lock_bh(&tx_ring->tx_idr_lock); idr_remove(&tx_ring->txbuf_idr, @@ -344,7 +414,7 @@ dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); if (!skb_cb->vif) { - dev_kfree_skb_any(msdu); + ieee80211_free_txskb(ar->hw, msdu); return; } @@ -369,7 +439,7 @@ "dp_tx: failed to find the peer with peer_id %d\n", ts->peer_id); spin_unlock_bh(&ab->base_lock); - dev_kfree_skb_any(msdu); + ieee80211_free_txskb(ar->hw, msdu); return; } spin_unlock_bh(&ab->base_lock); @@ -566,12 +636,12 @@ dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) { - dev_kfree_skb_any(msdu); + ieee80211_free_txskb(ar->hw, msdu); return; } if (unlikely(!skb_cb->vif)) { - dev_kfree_skb_any(msdu); + ieee80211_free_txskb(ar->hw, msdu); return; } @@ -624,7 +694,7 @@ "dp_tx: failed to find the peer with peer_id %d\n", ts->peer_id); spin_unlock_bh(&ab->base_lock); - dev_kfree_skb_any(msdu); + ieee80211_free_txskb(ar->hw, msdu); return; } arsta = (struct ath11k_sta *)peer->sta->drv_priv; diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/dp_tx.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_tx.h --- linux-6.4/drivers/net/wireless/ath/ath11k/dp_tx.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/dp_tx.h 2023-05-22 20:06:42.211799752 +0200 @@ -16,6 +16,20 @@ u16 peer_id; }; +#define HTT_TX_MSDU_DESC_INFO0_VALID_ENCRYPT_TYPE BIT(8) +#define HTT_TX_MSDU_DESC_INFO0_ENCRYPT_TYPE GENMASK(16, 15) +#define HTT_TX_MSDU_DESC_INFO0_HOST_TX_DESC_POOL BIT(31) + +struct htt_tx_msdu_desc_ext { + __le32 info0; + __le32 info1; + __le32 info2; + __le32 info3; + __le32 info4; + __le32 info5; + __le32 info6; +} __packed; + void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts); int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab); int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif, diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/hw.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/hw.c --- linux-6.4/drivers/net/wireless/ath/ath11k/hw.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/hw.c 2023-05-22 20:06:42.211799752 +0200 @@ -1396,6 +1396,14 @@ }, /* CE11 Not used */ + { + .pipenum = __cpu_to_le32(11), + .pipedir = __cpu_to_le32(0), + .nentries = __cpu_to_le32(0), + .nbytes_max = __cpu_to_le32(0), + .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), + .reserved = __cpu_to_le32(0), + }, }; /* Map from service/endpoint to Copy Engine. diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/hw.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/hw.h --- linux-6.4/drivers/net/wireless/ath/ath11k/hw.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/hw.h 2023-10-25 17:59:16.188036994 +0200 @@ -74,6 +74,7 @@ #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD" #define ATH11K_BOARD_API2_FILE "board-2.bin" +#define ATH11K_BOARD_OVERRIDE_FILE "board-id-override.txt" #define ATH11K_DEFAULT_BOARD_FILE "board.bin" #define ATH11K_DEFAULT_CAL_FILE "caldata.bin" #define ATH11K_AMSS_FILE "amss.bin" @@ -192,6 +193,7 @@ u32 num_vdevs; u32 num_peers; bool supports_suspend; + bool supports_ap_vlan; u32 hal_desc_sz; bool supports_regdb; bool fix_l1ss; @@ -224,6 +226,7 @@ u32 tx_ring_size; bool smp2p_wow_exit; bool support_fw_mac_sequence; + bool ce_fwlog_enable; }; struct ath11k_hw_ops { diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/mac.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/mac.c --- linux-6.4/drivers/net/wireless/ath/ath11k/mac.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/mac.c 2024-03-08 17:37:03.608237373 +0100 @@ -1,10 +1,11 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include +#include #include #include #include @@ -433,7 +434,7 @@ } static u32 -ath11k_mac_max_ht_nss(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN]) +ath11k_mac_max_ht_nss(const u8 *ht_mcs_mask) { int nss; @@ -445,7 +446,7 @@ } static u32 -ath11k_mac_max_vht_nss(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX]) +ath11k_mac_max_vht_nss(const u16 *vht_mcs_mask) { int nss; @@ -457,7 +458,7 @@ } static u32 -ath11k_mac_max_he_nss(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) +ath11k_mac_max_he_nss(const u16 *he_mcs_mask) { int nss; @@ -643,6 +644,9 @@ return NULL; for (i = 0; i < ab->num_radios; i++) { + if (ab->fw_mode == ATH11K_FIRMWARE_MODE_FTM) + pdev = &ab->pdevs[i]; + else pdev = rcu_dereference(ab->pdevs_active[i]); if (pdev && pdev->pdev_id == pdev_id) @@ -1351,7 +1355,7 @@ return ret; } -static int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif) +int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif) { struct ath11k *ar = arvif->ar; struct ath11k_base *ab = ar->ab; @@ -1362,6 +1366,7 @@ struct ieee80211_mgmt *mgmt; u8 *ies; int ret; + u64 adjusted_tsf; if (arvif->vdev_type != WMI_VDEV_TYPE_AP) return 0; @@ -1387,6 +1392,15 @@ else arvif->wpaie_present = false; + /* Make the TSF offset negative so beacons in the same + * staggered batch have the same TSF. + */ + if (arvif->tbtt_offset) { + adjusted_tsf = cpu_to_le64(0ULL - arvif->tbtt_offset); + mgmt = (void *)bcn->data; + memcpy(&mgmt->u.beacon.timestamp, &adjusted_tsf, sizeof(adjusted_tsf)); + } + ret = ath11k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn); kfree_skb(bcn); @@ -1416,7 +1430,7 @@ if (vif->bss_conf.color_change_active) ieee80211_beacon_update_cntdwn(vif); - ath11k_mac_setup_bcn_tmpl(arvif); + ieee80211_queue_work(arvif->ar->hw, &arvif->update_bcn_template_work); } static void ath11k_control_beaconing(struct ath11k_vif *arvif, @@ -1599,7 +1613,7 @@ } /* FIXME: base on RSN IE/WPA IE is a correct idea? */ - if (rsnie || wpaie) { + if (ar->supports_6ghz || rsnie || wpaie) { ath11k_dbg(ar->ab, ATH11K_DBG_WMI, "%s: rsn ie found\n", __func__); arg->need_ptk_4_way = true; @@ -1658,7 +1672,7 @@ } static bool -ath11k_peer_assoc_h_ht_masked(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN]) +ath11k_peer_assoc_h_ht_masked(const u8 *ht_mcs_mask) { int nss; @@ -1670,7 +1684,7 @@ } static bool -ath11k_peer_assoc_h_vht_masked(const u16 vht_mcs_mask[]) +ath11k_peer_assoc_h_vht_masked(const u16 *vht_mcs_mask) { int nss; @@ -2065,7 +2079,7 @@ } static bool -ath11k_peer_assoc_h_he_masked(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) +ath11k_peer_assoc_h_he_masked(const u16 *he_mcs_mask) { int nss; @@ -3068,7 +3082,8 @@ { u32 bitmap[2], param_id, param_val, pdev_id; int ret; - s8 non_srg_th = 0, srg_th = 0; + s8 non_srg_th = ATH11K_OBSS_PD_THRESHOLD_DISABLED; + s8 srg_th = 0; pdev_id = ar->pdev->pdev_id; @@ -3097,8 +3112,6 @@ if (he_obss_pd->sr_ctrl & IEEE80211_HE_SPR_NON_SRG_OFFSET_PRESENT) non_srg_th = (ATH11K_OBSS_PD_MAX_THRESHOLD + he_obss_pd->non_srg_max_offset); - else - non_srg_th = ATH11K_OBSS_PD_NON_SRG_MAX_THRESHOLD; param_val |= ATH11K_OBSS_PD_NON_SRG_EN; } @@ -3113,6 +3126,7 @@ param_val |= ATH11K_OBSS_PD_THRESHOLD_IN_DBM; param_val |= FIELD_PREP(GENMASK(15, 8), srg_th); } else { + if ((non_srg_th & 0xff) != ATH11K_OBSS_PD_THRESHOLD_DISABLED) non_srg_th -= ATH11K_DEFAULT_NOISE_FLOOR; /* SRG not supported and threshold in dB */ param_val &= ~(ATH11K_OBSS_PD_SRG_EN | @@ -4078,7 +4092,25 @@ */ if (peer && sta && cmd == SET_KEY) ath11k_peer_frags_flush(ar, peer); + + /* Reset peer authorized flag in FW before deleting keys + * to avoid races in FW during encryption of queued packets. + */ + if (peer && sta && cmd == DISABLE_KEY && peer->is_authorized) { + peer->is_authorized = false; + spin_unlock_bh(&ab->base_lock); + ret = ath11k_wmi_set_peer_param(ar, sta->addr, + arvif->vdev_id, + WMI_PEER_AUTHORIZE, + 0); + if (ret) { + ath11k_warn(ar->ab, "Unable to reset authorize flag for " + "peer (%pM) vdev %d: %d\n", + sta->addr, arvif->vdev_id, ret); + } + } else { spin_unlock_bh(&ab->base_lock); + } if (!peer) { if (cmd == SET_KEY) { @@ -4882,10 +4914,21 @@ spin_lock_bh(&ar->ab->base_lock); peer = ath11k_peer_find(ar->ab, arvif->vdev_id, sta->addr); - if (peer) + if (peer) { peer->is_authorized = false; - spin_unlock_bh(&ar->ab->base_lock); + ret = ath11k_wmi_set_peer_param(ar, sta->addr, + arvif->vdev_id, + WMI_PEER_AUTHORIZE, + 0); + if (ret) { + ath11k_warn(ar->ab, "Unable to reset authorize flag for " + "peer (%pM) vdev %d: %d\n", + sta->addr, arvif->vdev_id, ret); + } + } else { + spin_unlock_bh(&ar->ab->base_lock); + } } else if (old_state == IEEE80211_STA_ASSOC && new_state == IEEE80211_STA_AUTH && (vif->type == NL80211_IFTYPE_AP || @@ -5920,8 +5963,15 @@ struct ieee80211_key_conf *key = info->control.hw_key; struct ath11k_sta *arsta = NULL; u32 info_flags = info->flags; + struct ieee80211_mgmt *mgmt; bool is_prb_rsp; int ret; + u64 adjusted_tsf; + + if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) { + ieee80211_free_txskb(ar->hw, skb); + return; + } memset(skb_cb, 0, sizeof(*skb_cb)); skb_cb->vif = vif; @@ -5935,6 +5985,12 @@ skb_cb->flags |= ATH11K_SKB_HW_80211_ENCAP; } else if (ieee80211_is_mgmt(hdr->frame_control)) { is_prb_rsp = ieee80211_is_probe_resp(hdr->frame_control); + if (is_prb_rsp && arvif->tbtt_offset) { + mgmt = (struct ieee80211_mgmt *)skb->data; + adjusted_tsf = cpu_to_le64(0ULL - arvif->tbtt_offset); + memcpy(&mgmt->u.probe_resp.timestamp, &adjusted_tsf, + sizeof(adjusted_tsf)); + } ret = ath11k_mac_mgmt_tx(ar, skb, is_prb_rsp); if (ret) { ath11k_warn(ar->ab, "failed to queue management frame %d\n", @@ -6020,6 +6076,11 @@ struct ath11k_pdev *pdev = ar->pdev; int ret; + if (ath11k_ftm_mode) { + ath11k_warn(ab, "mac operations not supported in factory test mode\n"); + return -EOPNOTSUPP; + } + ath11k_mac_drain_tx(ar); mutex_lock(&ar->conf_mutex); @@ -6034,6 +6095,7 @@ case ATH11K_STATE_RESTARTED: case ATH11K_STATE_WEDGED: case ATH11K_STATE_ON: + case ATH11K_STATE_FTM: WARN_ON(1); ret = -EINVAL; goto err; @@ -6140,6 +6202,22 @@ return ret; } +static void ath11k_update_bcn_template_work(struct work_struct *work) +{ + struct ath11k_vif *arvif = container_of(work, struct ath11k_vif, + update_bcn_template_work); + struct ath11k *ar = arvif->ar; + int ret = 0; + + mutex_lock(&ar->conf_mutex); + if (arvif->is_up) + ret = ath11k_mac_setup_bcn_tmpl(arvif); + mutex_unlock(&ar->conf_mutex); + if (ret) + ath11k_warn(ar->ab, "failed to submit beacon template for vdev_id : %d ret : %d\n", + arvif->vdev_id, ret); +} + static void ath11k_mac_op_stop(struct ieee80211_hw *hw) { struct ath11k *ar = hw->priv; @@ -6455,6 +6533,7 @@ INIT_LIST_HEAD(&arvif->list); INIT_DELAYED_WORK(&arvif->connection_loss_work, ath11k_mac_vif_sta_connection_loss_work); + INIT_WORK(&arvif->update_bcn_template_work, ath11k_update_bcn_template_work); for (i = 0; i < ARRAY_SIZE(arvif->bitrate_mask.control); i++) { arvif->bitrate_mask.control[i].legacy = 0xffffffff; @@ -6675,7 +6754,7 @@ int i; cancel_delayed_work_sync(&arvif->connection_loss_work); - + cancel_work_sync(&arvif->update_bcn_template_work); mutex_lock(&ar->conf_mutex); ath11k_dbg(ab, ATH11K_DBG_MAC, "mac remove interface (vdev %d)\n", @@ -6882,6 +6961,7 @@ struct wmi_vdev_start_req_arg arg = {}; const struct cfg80211_chan_def *chandef = &ctx->def; int ret = 0; + unsigned int dfs_cac_time; lockdep_assert_held(&ar->conf_mutex); @@ -6950,20 +7030,21 @@ ath11k_dbg(ab, ATH11K_DBG_MAC, "vdev %pM started, vdev_id %d\n", arvif->vif->addr, arvif->vdev_id); - /* Enable CAC Flag in the driver by checking the channel DFS cac time, - * i.e dfs_cac_ms value which will be valid only for radar channels - * and state as NL80211_DFS_USABLE which indicates CAC needs to be + /* Enable CAC Flag in the driver by checking the all sub-channel's DFS + * state as NL80211_DFS_USABLE which indicates CAC needs to be * done before channel usage. This flags is used to drop rx packets. * during CAC. */ /* TODO Set the flag for other interface types as required */ - if (arvif->vdev_type == WMI_VDEV_TYPE_AP && - chandef->chan->dfs_cac_ms && - chandef->chan->dfs_state == NL80211_DFS_USABLE) { + if (arvif->vdev_type == WMI_VDEV_TYPE_AP && ctx->radar_enabled && + cfg80211_chandef_dfs_usable(ar->hw->wiphy, chandef)) { set_bit(ATH11K_CAC_RUNNING, &ar->dev_flags); + dfs_cac_time = cfg80211_chandef_dfs_cac_time(ar->hw->wiphy, + chandef); ath11k_dbg(ab, ATH11K_DBG_MAC, - "CAC Started in chan_freq %d for vdev %d\n", - arg.channel.freq, arg.vdev_id); + "cac started dfs_cac_time %u center_freq %d center_freq1 %d for vdev %d\n", + dfs_cac_time, arg.channel.freq, chandef->center_freq1, + arg.vdev_id); } ret = ath11k_mac_set_txbf_conf(arvif); @@ -8725,6 +8806,14 @@ if (ar->state != ATH11K_STATE_ON) goto err_fallback; + /* Firmware doesn't provide Tx power during CAC hence no need to fetch + * the stats. + */ + if (test_bit(ATH11K_CAC_RUNNING, &ar->dev_flags)) { + mutex_unlock(&ar->conf_mutex); + return -EAGAIN; + } + req_param.pdev_id = ar->pdev->pdev_id; req_param.stats_id = WMI_REQUEST_PDEV_STAT; @@ -8835,6 +8924,28 @@ } } +#define ATH11k_5_DOT_9_MIN_FREQ 5845 +#define ATH11k_5_DOT_9_MAX_FREQ 5885 + +static void ath11k_mac_update_5_dot_9_ch_list(struct ath11k *ar, + struct ieee80211_supported_band *band) +{ + int i; + + if (test_bit(WMI_TLV_SERVICE_5_DOT_9GHZ_SUPPORT, + ar->ab->wmi_ab.svc_map)) + return; + + if (ar->ab->dfs_region != ATH11K_DFS_REG_FCC) + return; + + for (i = 0; i < band->n_channels; i++) { + if (band->channels[i].center_freq >= ATH11k_5_DOT_9_MIN_FREQ && + band->channels[i].center_freq <= ATH11k_5_DOT_9_MAX_FREQ) + band->channels[i].flags |= IEEE80211_CHAN_DISABLED; + } +} + static u32 ath11k_get_phy_id(struct ath11k *ar, u32 band) { struct ath11k_pdev *pdev = ar->pdev; @@ -8892,7 +9003,7 @@ } if (supported_bands & WMI_HOST_WLAN_5G_CAP) { - if (reg_cap->high_5ghz_chan >= ATH11K_MAX_6G_FREQ) { + if (reg_cap->high_5ghz_chan >= ATH11K_MIN_6G_FREQ) { channels = kmemdup(ath11k_6ghz_channels, sizeof(ath11k_6ghz_channels), GFP_KERNEL); if (!channels) { @@ -8945,6 +9056,7 @@ ath11k_mac_update_ch_list(ar, band, temp_reg_cap->low_5ghz_chan, temp_reg_cap->high_5ghz_chan); + ath11k_mac_update_5_dot_9_ch_list(ar, band); } } @@ -9277,6 +9389,11 @@ */ ar->hw->wiphy->interface_modes &= ~BIT(NL80211_IFTYPE_MONITOR); + if (ab->hw_params.supports_ap_vlan) { + ar->hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP_VLAN); + ar->hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_AP_VLAN); + } + /* Apply the regd received during initialization */ ret = ath11k_regd_update(ar); if (ret) { @@ -9383,6 +9500,7 @@ struct ieee80211_hw *hw; struct ath11k *ar; struct ath11k_pdev *pdev; + struct ieee80211_ops *ops; int ret; int i; @@ -9390,17 +9508,25 @@ return 0; for (i = 0; i < ab->num_radios; i++) { + ops = kmemdup(&ath11k_ops, sizeof(ath11k_ops), GFP_KERNEL); + if (!ops) { + ret = -ENOMEM; + goto err_free_mac; + } + pdev = &ab->pdevs[i]; - hw = ieee80211_alloc_hw(sizeof(struct ath11k), &ath11k_ops); + hw = ieee80211_alloc_hw(sizeof(struct ath11k), ops); if (!hw) { ath11k_warn(ab, "failed to allocate mac80211 hw device\n"); ret = -ENOMEM; + kfree(ops); goto err_free_mac; } ar = hw->priv; ar->hw = hw; ar->ab = ab; + ar->ops = ops; ar->pdev = pdev; ar->pdev_idx = i; ar->lmac_id = ath11k_hw_get_mac_from_pdev_id(&ab->hw_params, i); @@ -9460,6 +9586,7 @@ { struct ath11k *ar; struct ath11k_pdev *pdev; + struct ieee80211_ops *ops; int i; for (i = 0; i < ab->num_radios; i++) { @@ -9468,7 +9595,9 @@ if (!ar) continue; + ops = ar->ops; ieee80211_free_hw(ar->hw); + kfree(ops); pdev->ar = NULL; } } diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/mac.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/mac.h --- linux-6.4/drivers/net/wireless/ath/ath11k/mac.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/mac.h 2023-05-22 20:06:42.215799858 +0200 @@ -121,7 +121,7 @@ #define ATH11K_PEER_RX_NSS_80_80MHZ GENMASK(5, 3) #define ATH11K_OBSS_PD_MAX_THRESHOLD -82 -#define ATH11K_OBSS_PD_NON_SRG_MAX_THRESHOLD -62 +#define ATH11K_OBSS_PD_THRESHOLD_DISABLED 128 #define ATH11K_OBSS_PD_THRESHOLD_IN_DBM BIT(29) #define ATH11K_OBSS_PD_SRG_EN BIT(30) #define ATH11K_OBSS_PD_NON_SRG_EN BIT(31) @@ -175,4 +175,6 @@ int ath11k_mac_vif_set_keepalive(struct ath11k_vif *arvif, enum wmi_sta_keepalive_method method, u32 interval); +int ath11k_mac_setup_bcn_tmpl(struct ath11k_vif *arvif); + #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/mhi.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/mhi.c --- linux-6.4/drivers/net/wireless/ath/ath11k/mhi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/mhi.c 2024-03-22 17:24:19.738851749 +0100 @@ -372,7 +372,7 @@ if (ret) return ret; - mhi_ctrl->iova_start = res.start + 0x1000000; + mhi_ctrl->iova_start = res.start; mhi_ctrl->iova_stop = res.end; return 0; @@ -414,7 +414,7 @@ goto free_controller; } else { mhi_ctrl->iova_start = 0; - mhi_ctrl->iova_stop = 0xFFFFFFFF; + mhi_ctrl->iova_stop = ab_pci->dma_mask; } mhi_ctrl->rddm_size = RDDM_DUMP_SIZE; diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/pci.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pci.c --- linux-6.4/drivers/net/wireless/ath/ath11k/pci.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pci.c 2024-03-22 17:24:19.742851858 +0100 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -15,9 +15,12 @@ #include "mhi.h" #include "debug.h" #include "pcic.h" +#include "qmi.h" +#include #define ATH11K_PCI_BAR_NUM 0 -#define ATH11K_PCI_DMA_MASK 32 +#define ATH11K_PCI_DMA_MASK 36 +#define ATH11K_PCI_COHERENT_DMA_MASK 32 #define TCSR_SOC_HW_VERSION 0x0224 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) @@ -27,6 +30,8 @@ #define QCN9074_DEVICE_ID 0x1104 #define WCN6855_DEVICE_ID 0x1103 +#define ATH11K_PCIE_LOCAL_REG_PCIE_LOCAL_RSV0 0x1E03164 + static const struct pci_device_id ath11k_pci_id_table[] = { { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, @@ -173,8 +178,16 @@ static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) { + struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); u32 val, delay; + /* + * reset will reinitialise SoC registers to their default + * values, we must not assume that the actual window cached + * there is going to be valid after global reset. + */ + ab_pci->register_window = 0x00; + val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); val |= PCIE_SOC_GLOBAL_RESET_V; @@ -367,9 +380,14 @@ ath11k_mhi_set_mhictrl_reset(ab); } +#define ATH11K_QRTR_INSTANCE_PCI_DOMAIN GENMASK(3, 0) +#define ATH11K_QRTR_INSTANCE_PCI_BUS_NUM GENMASK(7, 4) + static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) { struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; + struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); + struct pci_bus *bus = ab_pci->pdev->bus; cfg->tgt_ce = ab->hw_params.target_ce_config; cfg->tgt_ce_len = ab->hw_params.target_ce_count; @@ -380,6 +398,13 @@ ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, &cfg->shadow_reg_v2_len); + + ab_pci->instance_id = + FIELD_PREP(ATH11K_QRTR_INSTANCE_PCI_DOMAIN, + pci_domain_nr(bus)) | + FIELD_PREP(ATH11K_QRTR_INSTANCE_PCI_BUS_NUM, + bus->number); + ab->qmi.service_ins_id += ab_pci->instance_id; } static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable) @@ -525,13 +550,22 @@ goto disable_device; } - ret = dma_set_mask_and_coherent(&pdev->dev, + ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); if (ret) { ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", ATH11K_PCI_DMA_MASK, ret); goto release_region; } + ab_pci->dma_mask = DMA_BIT_MASK(ATH11K_PCI_DMA_MASK); + + ret = dma_set_coherent_mask(&pdev->dev, + DMA_BIT_MASK(ATH11K_PCI_COHERENT_DMA_MASK)); + if (ret) { + ath11k_err(ab, "failed to set pci coherent dma mask to %d: %d\n", + ATH11K_PCI_COHERENT_DMA_MASK, ret); + goto release_region; + } pci_set_master(pdev); @@ -594,6 +628,18 @@ ab_pci->link_ctl); } +static void ath11k_pci_update_qrtr_node_id(struct ath11k_base *ab) +{ + struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); + u32 reg; + + reg = ATH11K_PCIE_LOCAL_REG_PCIE_LOCAL_RSV0 & ATH11K_PCI_WINDOW_RANGE_MASK; + ath11k_pcic_write32(ab, reg, ab_pci->instance_id); + + ath11k_dbg(ab, ATH11K_DBG_PCI, "pci reg 0x%x instance_id 0x%x read val 0x%x\n", + reg, ab_pci->instance_id, ath11k_pcic_read32(ab, reg)); +} + static int ath11k_pci_power_up(struct ath11k_base *ab) { struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); @@ -610,6 +656,8 @@ ath11k_pci_msi_enable(ab_pci); + ath11k_pci_update_qrtr_node_id(ab); + ret = ath11k_mhi_start(ab_pci); if (ret) { ath11k_err(ab, "failed to start mhi: %d\n", ret); @@ -745,6 +793,7 @@ ab_pci->ab = ab; ab_pci->pdev = pdev; ab->hif.ops = &ath11k_pci_hif_ops; + ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL; pci_set_drvdata(pdev, ab); spin_lock_init(&ab_pci->window_lock); @@ -791,6 +840,7 @@ case QCN9074_DEVICE_ID: pci_ops = &ath11k_pci_ops_qcn9074; ab->hw_rev = ATH11K_HW_QCN9074_HW10; + ab->enable_cold_boot_cal = ath11k_cold_boot_cal; break; case WCN6855_DEVICE_ID: ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD; @@ -868,7 +918,7 @@ ath11k_pci_init_qmi_ce_config(ab); - ret = ath11k_pcic_config_irq(ab); + ret = ath11k_pcic_config_irq(ab, pci_name(pdev)); if (ret) { ath11k_err(ab, "failed to config irq: %d\n", ret); goto err_ce_free; @@ -896,6 +946,7 @@ ath11k_err(ab, "failed to init core: %d\n", ret); goto err_irq_affinity_cleanup; } + ath11k_qmi_fwreset_from_cold_boot(ab); return 0; err_irq_affinity_cleanup: diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/pci.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pci.h --- linux-6.4/drivers/net/wireless/ath/ath11k/pci.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pci.h 2024-03-22 17:24:19.742851858 +0100 @@ -72,6 +72,8 @@ /* enum ath11k_pci_flags */ unsigned long flags; u16 link_ctl; + u32 instance_id; + u64 dma_mask; }; static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/pcic.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pcic.c --- linux-6.4/drivers/net/wireless/ath/ath11k/pcic.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pcic.c 2023-05-22 20:06:42.215799858 +0200 @@ -8,10 +8,7 @@ #include "pcic.h" #include "debug.h" -static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { - "bhi", - "mhi-er0", - "mhi-er1", +static const char *ce_irq_name[] = { "ce0", "ce1", "ce2", @@ -24,42 +21,20 @@ "ce9", "ce10", "ce11", - "host2wbm-desc-feed", - "host2reo-re-injection", - "host2reo-command", - "host2rxdma-monitor-ring3", - "host2rxdma-monitor-ring2", - "host2rxdma-monitor-ring1", - "reo2ost-exception", - "wbm2host-rx-release", - "reo2host-status", - "reo2host-destination-ring4", - "reo2host-destination-ring3", - "reo2host-destination-ring2", - "reo2host-destination-ring1", - "rxdma2host-monitor-destination-mac3", - "rxdma2host-monitor-destination-mac2", - "rxdma2host-monitor-destination-mac1", - "ppdu-end-interrupts-mac3", - "ppdu-end-interrupts-mac2", - "ppdu-end-interrupts-mac1", - "rxdma2host-monitor-status-ring-mac3", - "rxdma2host-monitor-status-ring-mac2", - "rxdma2host-monitor-status-ring-mac1", - "host2rxdma-host-buf-ring-mac3", - "host2rxdma-host-buf-ring-mac2", - "host2rxdma-host-buf-ring-mac1", - "rxdma2host-destination-ring-mac3", - "rxdma2host-destination-ring-mac2", - "rxdma2host-destination-ring-mac1", - "host2tcl-input-ring4", - "host2tcl-input-ring3", - "host2tcl-input-ring2", - "host2tcl-input-ring1", - "wbm2host-tx-completions-ring3", - "wbm2host-tx-completions-ring2", - "wbm2host-tx-completions-ring1", - "tcl2host-status-ring", +}; + +static const char *dp_irq_name[ATH11K_EXT_IRQ_NUM_MAX] = { + "wbm2host_tx_completions_ring1", + "wbm2host_tx_completions_ring2", + "wbm2host_tx_completions_ring3", + "lmac_reo_misc_irq", + "reo2host_destination_ring1", + "reo2host_destination_ring2", + "reo2host_destination_ring3", + "reo2host_destination_ring4", + "dp_res1", + "dp_res2", + "dp_res3", }; static const struct ath11k_msi_config ath11k_msi_config[] = { @@ -305,6 +280,8 @@ free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); netif_napi_del(&irq_grp->napi); + kfree(irq_grp->name); + irq_grp->name = NULL; } } @@ -317,6 +294,8 @@ continue; irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); + kfree(ab->irq_name[i]); + ab->irq_name[i] = NULL; } ath11k_pcic_free_ext_irq(ab); @@ -546,7 +525,8 @@ return ab->pci.ops->get_msi_irq(ab, vector); } -static int ath11k_pcic_ext_irq_config(struct ath11k_base *ab) +static int ath11k_pcic_ext_irq_config(struct ath11k_base *ab, + const char *dev_name) { int i, j, ret, num_vectors = 0; u32 user_base_data = 0, base_vector = 0; @@ -583,6 +563,13 @@ num_irq = 1; } + irq_grp->name = kasprintf(GFP_KERNEL, + "%s-%s", + dev_name, + dp_irq_name[i]); + if (!irq_grp->name) + return -ENOMEM; + irq_grp->num_irq = num_irq; irq_grp->irqs[0] = ATH11K_PCI_IRQ_DP_OFFSET + i; @@ -601,7 +588,7 @@ irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); ret = request_irq(irq, ath11k_pcic_ext_interrupt_handler, - irq_flags, "DP_EXT_IRQ", irq_grp); + irq_flags, irq_grp->name, irq_grp); if (ret) { ath11k_err(ab, "failed request irq %d: %d\n", vector, ret); @@ -614,7 +601,8 @@ return 0; } -int ath11k_pcic_config_irq(struct ath11k_base *ab) +int ath11k_pcic_config_irq(struct ath11k_base *ab, + const char *dev_name) { struct ath11k_ce_pipe *ce_pipe; u32 msi_data_start; @@ -643,6 +631,13 @@ if (irq < 0) return irq; + ab->irq_name[i] = kasprintf(GFP_KERNEL, + "%s-%s", + dev_name, + ce_irq_name[i]); + if (!ab->irq_name[i]) + return -ENOMEM; + ce_pipe = &ab->ce.ce_pipe[i]; irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; @@ -650,7 +645,7 @@ tasklet_setup(&ce_pipe->intr_tq, ath11k_pcic_ce_tasklet); ret = request_irq(irq, ath11k_pcic_ce_interrupt_handler, - irq_flags, irq_name[irq_idx], ce_pipe); + irq_flags, ab->irq_name[i], ce_pipe); if (ret) { ath11k_err(ab, "failed to request irq %d: %d\n", irq_idx, ret); @@ -663,7 +658,7 @@ ath11k_pcic_ce_irq_disable(ab, i); } - ret = ath11k_pcic_ext_irq_config(ab); + ret = ath11k_pcic_ext_irq_config(ab, dev_name); if (ret) return ret; diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/pcic.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pcic.h --- linux-6.4/drivers/net/wireless/ath/ath11k/pcic.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/pcic.h 2023-05-22 20:06:42.215799858 +0200 @@ -35,7 +35,7 @@ u32 *msi_addr_hi); void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx); void ath11k_pcic_free_irq(struct ath11k_base *ab); -int ath11k_pcic_config_irq(struct ath11k_base *ab); +int ath11k_pcic_config_irq(struct ath11k_base *ab, const char *dev_name); void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab); void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab); void ath11k_pcic_stop(struct ath11k_base *ab); diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/qmi.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/qmi.c --- linux-6.4/drivers/net/wireless/ath/ath11k/qmi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/qmi.c 2023-10-25 17:59:16.192037103 +0200 @@ -1,20 +1,23 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include "qmi.h" #include "core.h" +#include "pci.h" #include "debug.h" +#include "hif.h" #include #include #include #include #include #include +#include #define SLEEP_CLOCK_SELECT_INTERNAL_BIT 0x02 #define HOST_CSTATE_BIT 0x04 @@ -29,6 +32,10 @@ MODULE_PARM_DESC(cold_boot_cal, "Decrease the channel switch time but increase the driver load time (Default: true)"); +bool ath11k_skip_caldata = 0; +module_param_named(skip_caldata, ath11k_skip_caldata, bool, 0644); +MODULE_PARM_DESC(ath11k_skip_caldata, "Skip caldata download"); + static const struct qmi_elem_info qmi_wlanfw_host_cap_req_msg_v01_ei[] = { { .data_type = QMI_OPT_FLAG, @@ -1704,6 +1711,201 @@ }, }; +struct qmi_elem_info wlfw_ini_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_ini_req_msg_v01, + enablefwlog_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_ini_req_msg_v01, + enablefwlog), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_ini_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_ini_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_read_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct qmi_wlanfw_mem_read_req_msg_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_mem_read_req_msg_v01, + mem_type), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct qmi_wlanfw_mem_read_req_msg_v01, + data_len), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_read_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLANFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_write_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + mem_type), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLANFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_write_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_mem_write_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + static int ath11k_qmi_host_cap_send(struct ath11k_base *ab) { struct qmi_wlanfw_host_cap_req_msg_v01 req; @@ -2180,11 +2382,69 @@ return ret; } +static bool ath11k_pci_has_board_id_override(struct ath11k_base *ab, + u16 *ov_board_id) +{ + struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); + struct pci_dev *pdev = ab_pci->pdev; + const struct ath11k_bid_override *ov; + + list_for_each_entry(ov, &ab->board_id_overrides, next) { + if (ov->domain != pci_domain_nr(pdev->bus)) + continue; + + if (ov->bus_nr != pdev->bus->number) + continue; + + if (pdev->devfn != PCI_DEVFN(ov->slot, ov->func)) + continue; + + *ov_board_id = ov->board_id; + return true; + } + return false; +} + +static int ath11k_override_board_id(struct ath11k_base *ab, u16 *ov_board_id) +{ + struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); + int ret = 0; + + if (ab->hif.bus != ATH11K_BUS_PCI) { + /* + * on AHB: just override to 0xff. we don't now how to + * override otherwise. + */ + ab->qmi.target.board_id = 0xff; + return 0; + } + + if (ath11k_pci_has_board_id_override(ab, ov_board_id)) { + ath11k_info(ab, + "overriding board-id to 0x%x (%d)\n", + *ov_board_id, *ov_board_id); + } else { + ath11k_err(ab, + "device has invalid board-id, " + "to use this card you need to setup " + "%s/%s/%s file with " + "this line:\n pci:%s=\n", + ATH11K_FW_DIR, ab->hw_params.fw.dir, + ATH11K_BOARD_OVERRIDE_FILE, + pci_name(ab_pci->pdev)); + ret = -EIO; + } + + return ret; +} + static int ath11k_qmi_request_target_cap(struct ath11k_base *ab) { + struct device *dev = ab->dev; struct qmi_wlanfw_cap_req_msg_v01 req; struct qmi_wlanfw_cap_resp_msg_v01 resp; struct qmi_txn txn; + unsigned int board_id; int ret = 0; int r; char *fw_build_id; @@ -2229,10 +2489,19 @@ ab->qmi.target.chip_family = resp.chip_info.chip_family; } - if (resp.board_info_valid) + if (!of_property_read_u32(dev->of_node, "qcom,board_id", &board_id) && board_id != 0xFF) { + ab->qmi.target.board_id = board_id; + } else if (resp.board_info_valid) { ab->qmi.target.board_id = resp.board_info.board_id; - else - ab->qmi.target.board_id = 0xFF; + } else { + u16 ov_board_id; + + ret = ath11k_override_board_id(ab, &ov_board_id); + if (ret) + goto out; + + ab->qmi.target.board_id = ov_board_id; + } if (resp.soc_info_valid) ab->qmi.target.soc_id = resp.soc_info.soc_id; @@ -2441,6 +2710,11 @@ if (bdf_type == ATH11K_QMI_BDF_TYPE_ELF || bdf_type == ATH11K_QMI_BDF_TYPE_REGDB) goto out; + if (ath11k_skip_caldata) { + ath11k_warn(ab, "Skipping caldata download\n"); + goto out; + } + if (ab->qmi.target.eeprom_caldata) { file_type = ATH11K_QMI_FILE_TYPE_EEPROM; tmp = filename; @@ -2457,11 +2731,18 @@ fw_entry = ath11k_core_firmware_request(ab, ATH11K_DEFAULT_CAL_FILE); if (IS_ERR(fw_entry)) { + /* Caldata may not be present during first time calibration in + * factory hence allow to boot without loading caldata in ftm mode + */ + if (ath11k_ftm_mode) { + ath11k_info(ab, + "Booting without cal data file in FTM mode\n"); + return 0; + } ret = PTR_ERR(fw_entry); ath11k_warn(ab, - "qmi failed to load CAL data file:%s\n", - filename); - goto out; + "qmi failed to load CAL data file:%s booting with minimal performance\n",ATH11K_DEFAULT_CAL_FILE); + return 0; } success: fw_size = min_t(u32, ab->hw_params.fw.board_size, fw_entry->size); @@ -2826,6 +3107,33 @@ return 0; } +int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab) +{ + int timeout; + + if (ath11k_cold_boot_cal == 0 || ab->qmi.cal_done || + ab->hw_params.cold_boot_calib == 0 || + ab->hw_params.cbcal_restart_fw == 0) + return 0; + + ath11k_dbg(ab, ATH11K_DBG_AHB, "wait for cold boot done\n"); + timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, + (ab->qmi.cal_done == 1), + ATH11K_COLD_BOOT_FW_RESET_DELAY); + if (timeout <= 0) { + ath11k_cold_boot_cal = 0; + ath11k_warn(ab, "Coldboot Calibration failed timed out\n"); + } + + /* reset the firmware */ + ath11k_hif_power_down(ab); + ath11k_hif_power_up(ab); + + ath11k_dbg(ab, ATH11K_DBG_AHB, "exited from cold boot mode\n"); + return 0; +} +EXPORT_SYMBOL(ath11k_qmi_fwreset_from_cold_boot); + static int ath11k_qmi_process_coldboot_calibration(struct ath11k_base *ab) { int timeout; @@ -3052,6 +3360,130 @@ ath11k_dbg(ab, ATH11K_DBG_QMI, "qmi firmware init done\n"); } +int ath11k_qmi_mem_read(struct ath11k_base *ab, u32 mem_addr, void *mem_value,size_t count) +{ + struct qmi_wlanfw_mem_read_req_msg_v01 *req; + struct qmi_wlanfw_mem_read_resp_msg_v01 *resp; + struct qmi_txn txn = {}; + int ret = 0; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->offset = mem_addr; + + /* Firmware uses mem type to map to various memory regions. + * If this is set to 0, firmware uses automatic mapping of regions. + * i.e, if mem address is given and mem_type is 0, firmware will + * find under which memory region that address belongs + */ + req->mem_type = QMI_MEM_REGION_TYPE; + req->data_len = count; + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_mem_read_resp_msg_v01_ei, resp); + if (ret < 0) + goto out; + + ret = + qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_MEM_READ_REQ_V01, + QMI_WLANFW_MEM_READ_REQ_MSG_V01_MAX_MSG_LEN, + qmi_wlanfw_mem_read_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + ath11k_warn(ab, "Failed to send mem read request, err %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH11K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + ath11k_warn(ab, "qmi mem read req failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -EINVAL; + goto out; + } + + if (!resp->data_valid || resp->data_len != req->data_len) { + ath11k_warn(ab, "qmi mem read is invalid\n"); + ret = -EINVAL; + goto out; + } + memcpy(mem_value, resp->data, resp->data_len); + +out: + kfree(req); + kfree(resp); + return ret; +} + +int ath11k_qmi_mem_write(struct ath11k_base *ab, u32 mem_addr, void* mem_value, size_t count) +{ + struct qmi_wlanfw_mem_write_req_msg_v01 *req; + struct qmi_wlanfw_mem_write_resp_msg_v01 *resp; + struct qmi_txn txn = {}; + int ret = 0; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->offset = mem_addr; + req->mem_type = QMI_MEM_REGION_TYPE; + req->data_len = count; + memcpy(req->data, mem_value, req->data_len); + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_mem_write_resp_msg_v01_ei, resp); + if (ret < 0) + goto out; + + ret = + qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_MEM_WRITE_REQ_V01, + QMI_WLANFW_MEM_WRITE_REQ_MSG_V01_MAX_MSG_LEN, + qmi_wlanfw_mem_write_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + ath11k_warn(ab, "Failed to send mem write request, err %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH11K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + ath11k_warn(ab, "qmi mem write req failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -EINVAL; + goto out; + } + +out: + kfree(req); + kfree(resp); + return ret; +} + static const struct qmi_msg_handler ath11k_qmi_msg_handlers[] = { { .type = QMI_INDICATION, @@ -3196,7 +3628,7 @@ break; } - if (ath11k_cold_boot_cal && ab->qmi.cal_done == 0 && + if (ab->enable_cold_boot_cal && ab->qmi.cal_done == 0 && ab->hw_params.cold_boot_calib) { ath11k_qmi_process_coldboot_calibration(ab); } else { @@ -3240,6 +3672,55 @@ spin_unlock(&qmi->event_lock); } +int ath11k_enable_fwlog(struct ath11k_base *ab) +{ + struct wlfw_ini_req_msg_v01 *req; + struct wlfw_ini_resp_msg_v01 resp; + struct qmi_txn txn = {}; + int ret = 0; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + memset(&resp, 0, sizeof(resp)); + + req->enablefwlog_valid = 1; + req->enablefwlog = 1; + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + wlfw_ini_resp_msg_v01_ei, &resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLFW_INI_REQ_V01, + WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_ini_req_msg_v01_ei, req); + + if (ret < 0) { + ath11k_warn(ab, "Failed to send init request for enabling fwlog = %d\n", ret); + qmi_txn_cancel(&txn); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH11K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) { + ath11k_warn(ab, "fwlog enable wait for resp failed: %d\n", ret); + goto out; + } + + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ath11k_warn(ab, "fwlog enable request failed, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } +out: + kfree(req); + return ret; +} + int ath11k_qmi_init_service(struct ath11k_base *ab) { int ret; @@ -3256,8 +3737,7 @@ return ret; } - ab->qmi.event_wq = alloc_workqueue("ath11k_qmi_driver_event", - WQ_UNBOUND, 1); + ab->qmi.event_wq = alloc_ordered_workqueue("ath11k_qmi_driver_event", 0); if (!ab->qmi.event_wq) { ath11k_err(ab, "failed to allocate workqueue\n"); return -EFAULT; diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/qmi.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/qmi.h --- linux-6.4/drivers/net/wireless/ath/ath11k/qmi.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/qmi.h 2023-05-22 20:06:42.215799858 +0200 @@ -37,7 +37,7 @@ #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 #define ATH11K_FIRMWARE_MODE_OFF 4 -#define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) +#define ATH11K_COLD_BOOT_FW_RESET_DELAY (60 * HZ) #define ATH11K_QMI_DEVICE_BAR_SIZE 0x200000 @@ -154,6 +154,7 @@ #define BDF_MEM_REGION_TYPE 0x2 #define M3_DUMP_REGION_TYPE 0x3 #define CALDB_MEM_REGION_TYPE 0x4 +#define QMI_MEM_REGION_TYPE 0 struct qmi_wlanfw_host_cap_req_msg_v01 { u8 num_clients_valid; @@ -228,6 +229,18 @@ u64 fw_status; }; +struct wlfw_ini_req_msg_v01 { + u8 enablefwlog_valid; + u8 enablefwlog; +}; + +struct wlfw_ini_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define QMI_WLFW_INI_REQ_V01 0x002F +#define WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN 4 + #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 @@ -235,6 +248,11 @@ #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 +#define QMI_WLANFW_MAX_STR_LEN_V01 16 +#define QMI_WLANFW_MEM_WRITE_REQ_V01 0x0031 +#define QMI_WLANFW_MEM_WRITE_REQ_MSG_V01_MAX_MSG_LEN 6163 +#define QMI_WLANFW_MEM_READ_REQ_V01 0x0030 +#define QMI_WLANFW_MEM_READ_REQ_MSG_V01_MAX_MSG_LEN 21 struct qmi_wlanfw_mem_cfg_s_v01 { u64 offset; @@ -511,6 +529,30 @@ struct qmi_response_type_v01 resp; }; +struct qmi_wlanfw_mem_read_req_msg_v01 { + u32 offset; + u32 mem_type; + u32 data_len; +}; + +struct qmi_wlanfw_mem_read_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; +}; + +struct qmi_wlanfw_mem_write_req_msg_v01 { + u32 offset; + u32 mem_type; + u32 data_len; + u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; +}; + +struct qmi_wlanfw_mem_write_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + int ath11k_qmi_firmware_start(struct ath11k_base *ab, u32 mode); void ath11k_qmi_firmware_stop(struct ath11k_base *ab); @@ -519,5 +561,9 @@ void ath11k_qmi_deinit_service(struct ath11k_base *ab); int ath11k_qmi_init_service(struct ath11k_base *ab); void ath11k_qmi_free_resource(struct ath11k_base *ab); +int ath11k_qmi_fwreset_from_cold_boot(struct ath11k_base *ab); +int ath11k_enable_fwlog(struct ath11k_base *ab); +int ath11k_qmi_mem_read(struct ath11k_base *ab, u32 mem_addr, void *mem_value, size_t count); +int ath11k_qmi_mem_write(struct ath11k_base *ab, u32 mem_addr, void* mem_value, size_t count); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/testmode.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/testmode.c --- linux-6.4/drivers/net/wireless/ath/ath11k/testmode.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/testmode.c 2023-11-07 13:38:44.002255052 +0100 @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "testmode.h" @@ -9,69 +10,218 @@ #include "wmi.h" #include "hw.h" #include "core.h" -#include "testmode_i.h" +#include "../testmode_i.h" -static const struct nla_policy ath11k_tm_policy[ATH11K_TM_ATTR_MAX + 1] = { - [ATH11K_TM_ATTR_CMD] = { .type = NLA_U32 }, - [ATH11K_TM_ATTR_DATA] = { .type = NLA_BINARY, - .len = ATH11K_TM_DATA_MAX_LEN }, - [ATH11K_TM_ATTR_WMI_CMDID] = { .type = NLA_U32 }, - [ATH11K_TM_ATTR_VERSION_MAJOR] = { .type = NLA_U32 }, - [ATH11K_TM_ATTR_VERSION_MINOR] = { .type = NLA_U32 }, +#define ATH11K_FTM_SEGHDR_CURRENT_SEQ GENMASK(3, 0) +#define ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS GENMASK(7, 4) + +#define ATH11K_FWLOG_MAX_LEN 2048 + +static const struct nla_policy ath11k_tm_policy[ATH_TM_ATTR_MAX + 1] = { + [ATH_TM_ATTR_CMD] = { .type = NLA_U32 }, + [ATH_TM_ATTR_DATA] = { .type = NLA_BINARY, + .len = ATH_TM_DATA_MAX_LEN }, + [ATH_TM_ATTR_WMI_CMDID] = { .type = NLA_U32 }, + [ATH_TM_ATTR_VERSION_MAJOR] = { .type = NLA_U32 }, + [ATH_TM_ATTR_VERSION_MINOR] = { .type = NLA_U32 }, + [ATH_TM_ATTR_FWLOG] = { .type = NLA_BINARY, + .len = ATH11K_FWLOG_MAX_LEN }, }; -/* Returns true if callee consumes the skb and the skb should be discarded. - * Returns false if skb is not used. Does not sleep. - */ -bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, struct sk_buff *skb) +void ath11k_fwlog_write(struct ath11k_base *ab, u8 *data, int len) { struct sk_buff *nl_skb; - bool consumed; - int ret; + int ret, i; + struct ath11k *ar = NULL; + struct ath11k_pdev *pdev; - ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, - "testmode event wmi cmd_id %d skb %pK skb->len %d\n", - cmd_id, skb, skb->len); + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (pdev && pdev->ar) { + ar = pdev->ar; + break; + } + } - ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", skb->data, skb->len); + if (!ar) + return; - spin_lock_bh(&ar->data_lock); + nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy, + len, GFP_ATOMIC); + if (!nl_skb) { + ath11k_warn(ab, + "failed to allocate skb for fwlog event\n"); + return; + } + + ret = nla_put(nl_skb, ATH_TM_ATTR_FWLOG, len, data); + if (ret) { + ath11k_warn(ab, + "failed to to put fwlog wmi event to nl: %d\n", + ret); + kfree_skb(nl_skb); + return; + } + + cfg80211_testmode_event(nl_skb, GFP_ATOMIC); +} - consumed = true; +static struct ath11k *ath11k_tm_get_ar(struct ath11k_base *ab) +{ + struct ath11k_pdev *pdev; + struct ath11k *ar = NULL; + int i; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + if (ar) { + if (ar->state == ATH11K_STATE_FTM) + break; + } + } + + return ar; +} + +/* This function handles unsegmented events. Data in various events are aggregated + * in application layer, this event is unsegmented from host perspective. + */ +void ath11k_tm_wmi_event_unsegmented(struct ath11k_base *ab, u32 cmd_id, + struct sk_buff *skb) +{ + struct sk_buff *nl_skb; + struct ath11k *ar; + + ath11k_dbg(ab, ATH11K_DBG_TESTMODE, + "testmode event wmi cmd_id %d skb length %d\n", + cmd_id, skb->len); + ath11k_dbg_dump(ab, ATH11K_DBG_TESTMODE, NULL, "", skb->data, skb->len); + + ar = ath11k_tm_get_ar(ab); + if (!ar) { + ath11k_warn(ab, "testmode event not handled due to invalid pdev\n"); + return; + } + + spin_lock_bh(&ar->data_lock); nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy, - 2 * sizeof(u32) + skb->len, + 2 * nla_total_size(sizeof(u32)) + + nla_total_size(skb->len), GFP_ATOMIC); if (!nl_skb) { - ath11k_warn(ar->ab, + ath11k_warn(ab, "failed to allocate skb for testmode wmi event\n"); goto out; } - ret = nla_put_u32(nl_skb, ATH11K_TM_ATTR_CMD, ATH11K_TM_CMD_WMI); - if (ret) { - ath11k_warn(ar->ab, - "failed to put testmode wmi event cmd attribute: %d\n", - ret); + if (nla_put_u32(nl_skb, ATH_TM_ATTR_CMD, ATH_TM_CMD_WMI) || + nla_put_u32(nl_skb, ATH_TM_ATTR_WMI_CMDID, cmd_id) || + nla_put(nl_skb, ATH_TM_ATTR_DATA, skb->len, skb->data)) { + ath11k_warn(ab, "failed to populate testmode unsegmented event\n"); kfree_skb(nl_skb); goto out; } - ret = nla_put_u32(nl_skb, ATH11K_TM_ATTR_WMI_CMDID, cmd_id); - if (ret) { - ath11k_warn(ar->ab, - "failed to put testmode wmi even cmd_id: %d\n", - ret); - kfree_skb(nl_skb); + cfg80211_testmode_event(nl_skb, GFP_ATOMIC); + spin_unlock_bh(&ar->data_lock); + return; + +out: + spin_unlock_bh(&ar->data_lock); + ath11k_warn(ab, "Failed to send testmode event to higher layers\n"); +} + +/* This function handles segmented events. + * Data of various events received from fw is aggregated and + * sent to application layer + */ +int ath11k_tm_process_event(struct ath11k_base *ab, u32 cmd_id, + const struct wmi_ftm_event_msg *ftm_msg, + u16 length) +{ + struct sk_buff *nl_skb; + int ret = 0; + struct ath11k *ar; + u8 const *buf_pos; + u16 datalen; + u8 total_segments, current_seq; + u32 data_pos; + u32 pdev_id; + + ath11k_dbg(ab, ATH11K_DBG_TESTMODE, + "testmode event wmi cmd_id %d ftm event msg %pK datalen %d\n", + cmd_id, ftm_msg, length); + ath11k_dbg_dump(ab, ATH11K_DBG_TESTMODE, NULL, "", ftm_msg, length); + pdev_id = DP_HW2SW_MACID(ftm_msg->seg_hdr.pdev_id); + + if (pdev_id >= ab->num_radios) { + ath11k_warn(ab, "testmode event not handled due to invalid pdev id\n"); + return -EINVAL; + } + + ar = ab->pdevs[pdev_id].ar; + if (!ar) { + ath11k_warn(ab, "testmode event not handled due to absence of pdev\n"); + return -ENODEV; + } + + current_seq = FIELD_GET(ATH11K_FTM_SEGHDR_CURRENT_SEQ, + ftm_msg->seg_hdr.segmentinfo); + total_segments = FIELD_GET(ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS, + ftm_msg->seg_hdr.segmentinfo); + datalen = length - (sizeof(struct wmi_ftm_seg_hdr)); + buf_pos = ftm_msg->data; + + spin_lock_bh(&ar->data_lock); + if (current_seq == 0) { + ab->ftm_event_obj.expected_seq = 0; + ab->ftm_event_obj.data_pos = 0; + } + + data_pos = ab->ftm_event_obj.data_pos; + + if ((data_pos + datalen) > ATH_FTM_EVENT_MAX_BUF_LENGTH) { + ath11k_warn(ab, + "Invalid event length date_pos[%d] datalen[%d]\n", + data_pos, datalen); + ret = -EINVAL; goto out; } - ret = nla_put(nl_skb, ATH11K_TM_ATTR_DATA, skb->len, skb->data); - if (ret) { - ath11k_warn(ar->ab, - "failed to copy skb to testmode wmi event: %d\n", - ret); + memcpy(&ab->ftm_event_obj.eventdata[data_pos], buf_pos, datalen); + data_pos += datalen; + + if (++ab->ftm_event_obj.expected_seq != total_segments) { + ab->ftm_event_obj.data_pos = data_pos; + ath11k_dbg(ab, ATH11K_DBG_TESTMODE, + "partial data received current_seq[%d], total_seg[%d]\n", + current_seq, total_segments); + goto out; + } + + ath11k_dbg(ab, ATH11K_DBG_TESTMODE, + "total data length[%d] = [%d]\n", + data_pos, ftm_msg->seg_hdr.len); + nl_skb = cfg80211_testmode_alloc_event_skb(ar->hw->wiphy, + 2 * nla_total_size(sizeof(u32)) + + nla_total_size(data_pos), + GFP_ATOMIC); + if (!nl_skb) { + ath11k_warn(ab, + "failed to allocate skb for testmode wmi event\n"); + ret = -ENOMEM; + goto out; + } + + if (nla_put_u32(nl_skb, ATH_TM_ATTR_CMD, ATH_TM_CMD_WMI_FTM) || + nla_put_u32(nl_skb, ATH_TM_ATTR_WMI_CMDID, cmd_id) || + nla_put(nl_skb, ATH_TM_ATTR_DATA, data_pos, + &ab->ftm_event_obj.eventdata[0])) { + ath11k_warn(ab, "failed to populate testmode event"); kfree_skb(nl_skb); + ret = -ENOBUFS; goto out; } @@ -79,74 +229,133 @@ out: spin_unlock_bh(&ar->data_lock); - - return consumed; + return ret; } static int ath11k_tm_cmd_get_version(struct ath11k *ar, struct nlattr *tb[]) { struct sk_buff *skb; - int ret; ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, "testmode cmd get version_major %d version_minor %d\n", - ATH11K_TESTMODE_VERSION_MAJOR, - ATH11K_TESTMODE_VERSION_MINOR); + ATH_TESTMODE_VERSION_MAJOR, + ATH_TESTMODE_VERSION_MINOR); skb = cfg80211_testmode_alloc_reply_skb(ar->hw->wiphy, nla_total_size(sizeof(u32))); if (!skb) return -ENOMEM; - ret = nla_put_u32(skb, ATH11K_TM_ATTR_VERSION_MAJOR, - ATH11K_TESTMODE_VERSION_MAJOR); - if (ret) { + if (nla_put_u32(skb, ATH_TM_ATTR_VERSION_MAJOR, + ATH_TESTMODE_VERSION_MAJOR) || + nla_put_u32(skb, ATH_TM_ATTR_VERSION_MINOR, + ATH_TESTMODE_VERSION_MINOR)) { kfree_skb(skb); - return ret; + return -ENOBUFS; } - ret = nla_put_u32(skb, ATH11K_TM_ATTR_VERSION_MINOR, - ATH11K_TESTMODE_VERSION_MINOR); - if (ret) { - kfree_skb(skb); - return ret; + return cfg80211_testmode_reply(skb); } - return cfg80211_testmode_reply(skb); +static int ath11k_tm_cmd_testmode_start(struct ath11k *ar, struct nlattr *tb[]) +{ + int ret; + + ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, " enter testmode cmd fw start\n"); + mutex_lock(&ar->conf_mutex); + + if (ar->state == ATH11K_STATE_FTM) { + ret = -EALREADY; + goto err; + } + + /* start utf only when the driver is not in use */ + if (ar->state != ATH11K_STATE_OFF) { + ret = -EBUSY; + goto err; + } + + ar->ab->ftm_event_obj.eventdata = + kzalloc(ATH_FTM_EVENT_MAX_BUF_LENGTH, GFP_KERNEL); + if (!ar->ab->ftm_event_obj.eventdata) { + ret = -ENOMEM; + goto err; + } + + ar->state = ATH11K_STATE_FTM; + ar->ftm_msgref = 0; + mutex_unlock(&ar->conf_mutex); + ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, " enter testmode cmd started\n"); + return 0; +err: + mutex_unlock(&ar->conf_mutex); + return ret; } -static int ath11k_tm_cmd_wmi(struct ath11k *ar, struct nlattr *tb[]) +static int ath11k_tm_cmd_wmi(struct ath11k *ar, struct nlattr *tb[], + struct ieee80211_vif *vif) { struct ath11k_pdev_wmi *wmi = ar->wmi; struct sk_buff *skb; + struct ath11k_vif *arvif; u32 cmd_id, buf_len; - int ret; + int ret, tag; void *buf; + u32 *ptr; mutex_lock(&ar->conf_mutex); - if (ar->state != ATH11K_STATE_ON) { - ret = -ENETDOWN; + if (!tb[ATH_TM_ATTR_DATA]) { + ret = -EINVAL; goto out; } - if (!tb[ATH11K_TM_ATTR_DATA]) { + if (!tb[ATH_TM_ATTR_WMI_CMDID]) { ret = -EINVAL; goto out; } - if (!tb[ATH11K_TM_ATTR_WMI_CMDID]) { + buf = nla_data(tb[ATH_TM_ATTR_DATA]); + buf_len = nla_len(tb[ATH_TM_ATTR_DATA]); + if (!buf_len) { + ath11k_warn(ar->ab, "No data present in testmode command\n"); ret = -EINVAL; goto out; } - buf = nla_data(tb[ATH11K_TM_ATTR_DATA]); - buf_len = nla_len(tb[ATH11K_TM_ATTR_DATA]); - cmd_id = nla_get_u32(tb[ATH11K_TM_ATTR_WMI_CMDID]); + cmd_id = nla_get_u32(tb[ATH_TM_ATTR_WMI_CMDID]); + + /* Make sure that the buffer length is long enough to + * hold TLV and pdev/vdev id. + */ + if (buf_len < sizeof(struct wmi_tlv) + sizeof(u32)) { + ret = -EINVAL; + goto out; + } + + ptr = buf; + tag = FIELD_GET(WMI_TLV_TAG, *ptr); + + /* pdev/vdev id start after TLV header */ + ptr++; + + if (tag == WMI_TAG_PDEV_SET_PARAM_CMD) + *ptr = ar->pdev->pdev_id; + + if (ar->ab->fw_mode != ATH11K_FIRMWARE_MODE_FTM && + (tag == WMI_TAG_VDEV_SET_PARAM_CMD || tag == WMI_TAG_UNIT_TEST_CMD)) { + if (vif) { + arvif = (struct ath11k_vif *)vif->drv_priv; + *ptr = arvif->vdev_id; + } else { + ret = -EINVAL; + goto out; + } + } ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, - "testmode cmd wmi cmd_id %d buf %pK buf_len %d\n", - cmd_id, buf, buf_len); + "testmode cmd wmi cmd_id %d buf length %d\n", + cmd_id, buf_len); ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", buf, buf_len); @@ -173,26 +382,112 @@ return ret; } +static int ath11k_tm_cmd_process_ftm(struct ath11k *ar, struct nlattr *tb[]) +{ + struct ath11k_pdev_wmi *wmi = ar->wmi; + struct sk_buff *skb; + u32 cmd_id, buf_len, hdr_info; + int ret; + void *buf; + u8 segnumber = 0, seginfo; + u16 chunk_len, total_bytes, num_segments; + u8 *bufpos; + struct wmi_ftm_cmd *ftm_cmd; + + mutex_lock(&ar->conf_mutex); + ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, "ar->state %d\n", ar->state); + + if (ar->state != ATH11K_STATE_FTM) { + ret = -ENETDOWN; + goto out; + } + + if (!tb[ATH_TM_ATTR_DATA]) { + ret = -EINVAL; + goto out; + } + + buf = nla_data(tb[ATH_TM_ATTR_DATA]); + buf_len = nla_len(tb[ATH_TM_ATTR_DATA]); + cmd_id = WMI_PDEV_UTF_CMDID; + ath11k_dbg(ar->ab, ATH11K_DBG_TESTMODE, + "testmode cmd wmi cmd_id %d buffer length %d\n", + cmd_id, buf_len); + ath11k_dbg_dump(ar->ab, ATH11K_DBG_TESTMODE, NULL, "", buf, buf_len); + bufpos = buf; + total_bytes = buf_len; + num_segments = total_bytes / MAX_WMI_UTF_LEN; + + if (buf_len - (num_segments * MAX_WMI_UTF_LEN)) + num_segments++; + + while (buf_len) { + if (buf_len > MAX_WMI_UTF_LEN) + chunk_len = MAX_WMI_UTF_LEN; /* MAX message */ + else + chunk_len = buf_len; + + skb = ath11k_wmi_alloc_skb(wmi->wmi_ab, (chunk_len + + sizeof(struct wmi_ftm_cmd))); + if (!skb) { + ret = -ENOMEM; + goto out; + } + + ftm_cmd = (struct wmi_ftm_cmd *)skb->data; + hdr_info = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_BYTE) | + FIELD_PREP(WMI_TLV_LEN, (chunk_len + + sizeof(struct wmi_ftm_seg_hdr))); + ftm_cmd->tlv_header = hdr_info; + ftm_cmd->seg_hdr.len = total_bytes; + ftm_cmd->seg_hdr.msgref = ar->ftm_msgref; + seginfo = FIELD_PREP(ATH11K_FTM_SEGHDR_TOTAL_SEGMENTS, num_segments) | + FIELD_PREP(ATH11K_FTM_SEGHDR_CURRENT_SEQ, segnumber); + ftm_cmd->seg_hdr.segmentinfo = seginfo; + segnumber++; + memcpy(&ftm_cmd->data, bufpos, chunk_len); + ret = ath11k_wmi_cmd_send(wmi, skb, cmd_id); + if (ret) { + ath11k_warn(ar->ab, "ftm wmi command fail: %d\n", ret); + goto out; + } + + buf_len -= chunk_len; + bufpos += chunk_len; + } + ++ar->ftm_msgref; + ret = 0; +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, void *data, int len) { struct ath11k *ar = hw->priv; - struct nlattr *tb[ATH11K_TM_ATTR_MAX + 1]; + struct ath11k_base *ab = ar->ab; + struct nlattr *tb[ATH_TM_ATTR_MAX + 1]; int ret; - ret = nla_parse(tb, ATH11K_TM_ATTR_MAX, data, len, ath11k_tm_policy, + ret = nla_parse(tb, ATH_TM_ATTR_MAX, data, len, ath11k_tm_policy, NULL); if (ret) return ret; - if (!tb[ATH11K_TM_ATTR_CMD]) + if (!tb[ATH_TM_ATTR_CMD]) return -EINVAL; - switch (nla_get_u32(tb[ATH11K_TM_ATTR_CMD])) { - case ATH11K_TM_CMD_GET_VERSION: + switch (nla_get_u32(tb[ATH_TM_ATTR_CMD])) { + case ATH_TM_CMD_GET_VERSION: return ath11k_tm_cmd_get_version(ar, tb); - case ATH11K_TM_CMD_WMI: - return ath11k_tm_cmd_wmi(ar, tb); + case ATH_TM_CMD_TESTMODE_START: + return ath11k_tm_cmd_testmode_start(ar, tb); + case ATH_TM_CMD_WMI: + return ath11k_tm_cmd_wmi(ar, tb, vif); + case ATH_TM_CMD_WMI_FTM: + set_bit(ATH11K_FLAG_FTM_SEGMENTED, &ab->dev_flags); + return ath11k_tm_cmd_process_ftm(ar, tb); default: return -EOPNOTSUPP; } diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/testmode.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/testmode.h --- linux-6.4/drivers/net/wireless/ath/ath11k/testmode.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/testmode.h 2023-05-22 20:06:42.219799965 +0200 @@ -1,22 +1,35 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "core.h" #ifdef CONFIG_NL80211_TESTMODE -bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, struct sk_buff *skb); +void ath11k_tm_wmi_event_unsegmented(struct ath11k_base *ab, u32 cmd_id, + struct sk_buff *skb); +int ath11k_tm_process_event(struct ath11k_base *ab, u32 cmd_id, + const struct wmi_ftm_event_msg *ftm_msg, + u16 length); int ath11k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, void *data, int len); +void ath11k_fwlog_write(struct ath11k_base *ab, u8 *data, int len); #else -static inline bool ath11k_tm_event_wmi(struct ath11k *ar, u32 cmd_id, +static inline void ath11k_tm_wmi_event_unsegmented(struct ath11k_base *ab, + u32 cmd_id, struct sk_buff *skb) { - return false; +} + +static inline int ath11k_tm_process_event(struct ath11k_base *ab, u32 cmd_id, + const struct wmi_ftm_event_msg *msg, + u16 length) +{ + return 0; } static inline int ath11k_tm_cmd(struct ieee80211_hw *hw, @@ -26,4 +39,9 @@ return 0; } +static inline void ath11k_fwlog_write(struct ath11k_base *ab, u8 *data, + int len) +{ + +} #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/wmi.c linux-6.4-fbx/drivers/net/wireless/ath/ath11k/wmi.c --- linux-6.4/drivers/net/wireless/ath/ath11k/wmi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/wmi.c 2023-12-05 17:14:42.307715234 +0100 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021, 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -19,6 +19,7 @@ #include "mac.h" #include "hw.h" #include "peer.h" +#include "testmode.h" struct wmi_tlv_policy { size_t min_len; @@ -3871,7 +3872,7 @@ switch (ev->evt_type) { case WMI_BSS_COLOR_COLLISION_DETECTION: ieee80211_obss_color_collision_notify(arvif->vif, ev->obss_color_bitmap, - GFP_KERNEL); + GFP_ATOMIC); ath11k_dbg(ab, ATH11K_DBG_WMI, "OBSS color collision detected vdev:%d, event:%d, bitmap:%08llx\n", ev->vdev_id, ev->evt_type, ev->obss_color_bitmap); @@ -7917,12 +7918,14 @@ survey->noise = bss_ch_info_ev.noise_floor; survey->time = div_u64(total, cc_freq_hz); survey->time_busy = div_u64(busy, cc_freq_hz); - survey->time_rx = div_u64(rx_bss, cc_freq_hz); + survey->time_rx = div_u64(rx, cc_freq_hz); survey->time_tx = div_u64(tx, cc_freq_hz); + survey->time_bss_rx = div_u64(rx_bss, cc_freq_hz); survey->filled |= (SURVEY_INFO_NOISE_DBM | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY | SURVEY_INFO_TIME_RX | + SURVEY_INFO_TIME_BSS_RX | SURVEY_INFO_TIME_TX); exit: spin_unlock_bh(&ar->data_lock); @@ -8237,6 +8240,8 @@ ev->detector_id, ev->segment_id, ev->timestamp, ev->is_chirp, ev->freq_offset, ev->sidx); + rcu_read_lock(); + ar = ath11k_mac_get_ar_by_pdev_id(ab, ev->pdev_id); if (!ar) { @@ -8254,6 +8259,39 @@ ieee80211_radar_detected(ar->hw); exit: + rcu_read_unlock(); + + kfree(tb); +} + +static void +ath11k_wmi_tm_event_segmented(struct ath11k_base *ab, u32 cmd_id, + struct sk_buff *skb) +{ + const void **tb; + const struct wmi_ftm_event_msg *ev; + u16 length; + int ret; + + tb = ath11k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath11k_warn(ab, "failed to parse ftm event tlv: %d\n", ret); + return; + } + + ev = tb[WMI_TAG_ARRAY_BYTE]; + if (!ev) { + ath11k_warn(ab, "failed to fetch ftm msg\n"); + kfree(tb); + return; + } + + length = skb->len - TLV_HDR_SIZE; + ret = ath11k_tm_process_event(ab, cmd_id, ev, length); + if (ret) + ath11k_warn(ab, "Failed to process ftm event\n"); + kfree(tb); } @@ -8283,15 +8321,19 @@ ath11k_dbg(ab, ATH11K_DBG_WMI, "pdev temperature ev temp %d pdev_id %d\n", ev->temp, ev->pdev_id); + rcu_read_lock(); + ar = ath11k_mac_get_ar_by_pdev_id(ab, ev->pdev_id); if (!ar) { ath11k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev->pdev_id); - kfree(tb); - return; + goto exit; } ath11k_thermal_event_temperature(ar, ev->temp); +exit: + rcu_read_unlock(); + kfree(tb); } @@ -8410,13 +8452,6 @@ complete(&ab->wow.wakeup_completed); } -static void -ath11k_wmi_diag_event(struct ath11k_base *ab, - struct sk_buff *skb) -{ - trace_ath11k_wmi_diag(ab, skb->data, skb->len); -} - static const char *ath11k_wmi_twt_add_dialog_event_status(u32 status) { switch (status) { @@ -8445,6 +8480,130 @@ } } +static int ath11k_wmi_tbtt_offset_subtlv_parser(struct ath11k_base *ab, u16 tag, + u16 len, const void *ptr, + void *data) +{ + int ret = 0; + struct ath11k *ar; + u64 tx_delay = 0; + struct wmi_tbtt_offset_info *tbtt_offset_info; + struct ieee80211_chanctx_conf *conf; + struct ath11k_vif *arvif; + + tbtt_offset_info = (struct wmi_tbtt_offset_info *)ptr; + + rcu_read_lock(); + ar = ath11k_mac_get_ar_by_vdev_id(ab, tbtt_offset_info->vdev_id); + if (!ar) { + ath11k_warn(ab, "ar not found, vdev_id %d\n", tbtt_offset_info->vdev_id); + ret = -EINVAL; + goto exit; + } + + arvif = ath11k_mac_get_arvif(ar, tbtt_offset_info->vdev_id); + if (!arvif) { + ath11k_warn(ab, "arvif not found, vdev_id %d\n", + tbtt_offset_info->vdev_id); + ret = -EINVAL; + goto exit; + } + + if (arvif->vdev_type != WMI_VDEV_TYPE_AP) { + ret = 0; + goto exit; + } + + arvif->tbtt_offset = tbtt_offset_info->tbtt_offset; + + conf = rcu_dereference(arvif->vif->bss_conf.chanctx_conf); + if (conf && conf->def.chan->band == NL80211_BAND_2GHZ) { + /* 1Mbps Beacon: */ + /* 144 us ( LPREAMBLE) + 48 (PLCP Header) + * + 192 (1Mbps, 24 ytes) + * = 384 us + 2us(MAC/BB DELAY + */ + tx_delay = 386; + } else if (conf && (conf->def.chan->band == NL80211_BAND_5GHZ || + conf->def.chan->band == NL80211_BAND_6GHZ)) { + /* 6Mbps Beacon: */ + /*20(lsig)+2(service)+32(6mbps, 24 bytes) + *= 54us + 2us(MAC/BB DELAY) + */ + tx_delay = 56; + } + arvif->tbtt_offset -= tx_delay; + + ieee80211_queue_work(ar->hw, &arvif->update_bcn_template_work); +exit: + rcu_read_unlock(); + return ret; +} + +static int ath11k_wmi_tbtt_offset_event_parser(struct ath11k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + int ret = 0; + + ath11k_dbg(ab, ATH11K_DBG_WMI, "wmi tbtt offset event tag 0x%x of len %d rcvd\n", + tag, len); + + switch (tag) { + case WMI_TAG_TBTT_OFFSET_EXT_EVENT: + break; + case WMI_TAG_ARRAY_STRUCT: + ret = ath11k_wmi_tlv_iter(ab, ptr, len, + ath11k_wmi_tbtt_offset_subtlv_parser, + data); + break; + default: + ath11k_warn(ab, "Received invalid tag for wmi tbtt offset event\n"); + ret = -EINVAL; + break; + } + + return ret; +} + +static int ath11k_wmi_pull_tbtt_offset(struct ath11k_base *ab, struct sk_buff *skb, + struct wmi_tbtt_offset_ev_arg *arg) +{ + struct wmi_tbtt_offset_event *ev = NULL; + struct wmi_tbtt_offset_info tbtt_offset_info = {0}; + struct wmi_tlv *tlv; + int ret; + u8 *ptr; + u16 tlv_tag; + + ptr = skb->data; + + if (skb->len < (sizeof(*ev) + TLV_HDR_SIZE)) { + ath11k_warn(ab, "wmi_tbtt_offset event size invalid\n"); + return -EINVAL; + } + + tlv = (struct wmi_tlv *)ptr; + tlv_tag = FIELD_GET(WMI_TLV_TAG, tlv->header); + ptr += sizeof(*tlv); + + if (tlv_tag == WMI_TAG_TBTT_OFFSET_EXT_EVENT) { + ev = (struct wmi_tbtt_offset_event *)ptr; + } else { + ath11k_warn(ab, "tbtt event received with invalid tag\n"); + return -EINVAL; + } + + ret = ath11k_wmi_tlv_iter(ab, skb->data, skb->len, + ath11k_wmi_tbtt_offset_event_parser, + &tbtt_offset_info); + if (ret) { + ath11k_warn(ab, "failed to parse tbtt tlv %d\n", ret); + return -EINVAL; + } + return 0; +} + static void ath11k_wmi_twt_add_dialog_event(struct ath11k_base *ab, struct sk_buff *skb) { @@ -8501,12 +8660,13 @@ return; } + rcu_read_lock(); + arvif = ath11k_mac_get_arvif_by_vdev_id(ab, ev->vdev_id); if (!arvif) { ath11k_warn(ab, "failed to get arvif for vdev_id:%d\n", ev->vdev_id); - kfree(tb); - return; + goto exit; } ath11k_dbg(ab, ATH11K_DBG_WMI, "wmi gtk offload event refresh_cnt %d\n", @@ -8523,10 +8683,45 @@ ieee80211_gtk_rekey_notify(arvif->vif, arvif->bssid, (void *)&replay_ctr_be, GFP_ATOMIC); +exit: + rcu_read_unlock(); kfree(tb); } +static void ath11k_wmi_diag_event(struct ath11k_base *ab, struct sk_buff *skb) +{ + const struct wmi_tlv *tlv; + u16 tlv_tag, tlv_len; + uint32_t *dev_id; + u8 *data; + + tlv = (struct wmi_tlv *)skb->data; + tlv_tag = FIELD_GET(WMI_TLV_TAG, tlv->header); + tlv_len = FIELD_GET(WMI_TLV_LEN, tlv->header); + + if (tlv_tag == WMI_TAG_ARRAY_BYTE) { + data = skb->data + sizeof(struct wmi_tlv); + dev_id = (uint32_t *)data; + *dev_id = ab->hw_params.hw_rev; + } else { + ath11k_warn(ab, "WMI Diag Event missing required tlv\n"); + return; + } + + ath11k_fwlog_write(ab,data, tlv_len); +} + +void ath11k_wmi_event_tbttoffset_update(struct ath11k_base *ab, struct sk_buff *skb) +{ + struct wmi_tbtt_offset_ev_arg arg = {}; + int ret; + + ret = ath11k_wmi_pull_tbtt_offset(ab, skb, &arg); + if (ret) + ath11k_warn(ab, "failed to parse tbtt offset event: %d\n", ret); +} + static void ath11k_wmi_tlv_op_rx(struct ath11k_base *ab, struct sk_buff *skb) { struct wmi_cmd_hdr *cmd_hdr; @@ -8612,6 +8807,12 @@ case WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID: ath11k_wmi_pdev_csa_switch_count_status_event(ab, skb); break; + case WMI_PDEV_UTF_EVENTID: + if (test_bit(ATH11K_FLAG_FTM_SEGMENTED, &ab->dev_flags)) + ath11k_wmi_tm_event_segmented(ab, id, skb); + else + ath11k_tm_wmi_event_unsegmented(ab, id, skb); + break; case WMI_PDEV_TEMPERATURE_EVENTID: ath11k_wmi_pdev_temperature_event(ab, skb); break; @@ -8630,8 +8831,10 @@ case WMI_TWT_ADD_DIALOG_EVENTID: ath11k_wmi_twt_add_dialog_event(ab, skb); break; - /* add Unsupported events here */ case WMI_TBTTOFFSET_EXT_UPDATE_EVENTID: + ath11k_wmi_event_tbttoffset_update(ab, skb); + break; + /* add Unsupported events here */ case WMI_PEER_OPER_MODE_CHANGE_EVENTID: case WMI_TWT_ENABLE_EVENTID: case WMI_TWT_DISABLE_EVENTID: diff -ruw linux-6.4/drivers/net/wireless/ath/ath11k/wmi.h linux-6.4-fbx/drivers/net/wireless/ath/ath11k/wmi.h --- linux-6.4/drivers/net/wireless/ath/ath11k/wmi.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath11k/wmi.h 2023-05-22 20:06:42.223800071 +0200 @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH11K_WMI_H @@ -68,6 +69,7 @@ #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 +#define MAX_WMI_UTF_LEN 252 #define WMI_BA_MODE_BUFFER_SIZE_256 3 /* * HW mode config type replicated from FW header @@ -2095,6 +2097,7 @@ WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, WMI_TLV_SERVICE_EXT2_MSG = 220, WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, + WMI_TLV_SERVICE_5_DOT_9GHZ_SUPPORT = 247, WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, @@ -3541,6 +3544,24 @@ u32 pdev_id; } __packed; +struct wmi_ftm_seg_hdr { + u32 len; + u32 msgref; + u32 segmentinfo; + u32 pdev_id; +} __packed; + +struct wmi_ftm_cmd { + u32 tlv_header; + struct wmi_ftm_seg_hdr seg_hdr; + u8 data[]; +} __packed; + +struct wmi_ftm_event_msg { + struct wmi_ftm_seg_hdr seg_hdr; + u8 data[]; +} __packed; + #define WMI_BEACON_TX_BUFFER_SIZE 512 struct wmi_bcn_tmpl_cmd { @@ -4395,6 +4416,24 @@ u32 flag_info; }; +struct wmi_tbtt_offset_info { + u32 vdev_id; + u32 tbtt_offset; + u32 tbtt_qtime_low_us; + u32 tbtt_qtime_high_us; +} __packed; + +struct wmi_tbtt_offset_event { + u32 num_vdevs; +} __packed; + +struct wmi_tbtt_offset_ev_arg { + u32 vdev_id; + u32 tbtt_offset; + u32 tbtt_qtime_low_us; + u32 tbtt_qtime_high_us; +} __packed; + #define WMI_REG_CLIENT_MAX 4 struct wmi_reg_chan_list_cc_ext_event { diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/Kconfig linux-6.4-fbx/drivers/net/wireless/ath/ath12k/Kconfig --- linux-6.4/drivers/net/wireless/ath/ath12k/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/Kconfig 2024-04-04 13:46:08.942952695 +0200 @@ -32,3 +32,11 @@ If unsure, say Y to make it easier to debug problems. But if you want optimal performance choose N. + +config ATH12K_DEBUGFS + bool "ath12k custom debugfs support" + depends on ATH12K + +config ATH12K_MEM_PROFILE_512M + bool "ath12k low memory profile" + depends on ATH12K diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/Makefile linux-6.4-fbx/drivers/net/wireless/ath/ath12k/Makefile --- linux-6.4/drivers/net/wireless/ath/ath12k/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/Makefile 2024-01-19 17:01:19.849846593 +0100 @@ -18,10 +18,23 @@ dbring.o \ hw.o \ mhi.o \ + pcic.o \ pci.o \ - dp_mon.o + dp_mon.o \ + vendor.o \ + umac_reset.o +ath12k-$(CONFIG_ATH12K_DEBUGFS) += debugfs.o debugfs_htt_stats.o debugfs_sta.o +ath12k-$(CONFIG_NL80211_TESTMODE) += testmode.o ath12k-$(CONFIG_ATH12K_TRACING) += trace.o +ath12k-$(CONFIG_THERMAL) += thermal.o +ath12k-$(CONFIG_ATH12K_SPECTRAL) += spectral.o +ath12k-$(CONFIG_WANT_DEV_COREDUMP) += coredump.o +ath12k-$(CONFIG_ATH12K_PKTLOG) += pktlog.o +ath12k-$(CONFIG_ATH12K_AHB) += ahb.o +ath12k-$(CONFIG_ATH12K_PPE_DS_SUPPORT) += ppe.o +ath12k-$(CONFIG_ATH12K_BONDED_DS_SUPPORT) += bondif.o +ath12k-$(CONFIG_ATH12K_SAWF) += sawf.o telemetry.o telemetry_agent_if.o # for tracing framework to find trace.h CFLAGS_trace.o := -I$(src) diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/ce.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/ce.c --- linux-6.4/drivers/net/wireless/ath/ath12k/ce.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/ce.c 2024-01-19 17:01:19.853846702 +0100 @@ -41,6 +41,7 @@ .src_nentries = 32, .src_sz_max = 2048, .dest_nentries = 0, + .send_cb = ath12k_htc_tx_completion_handler, }, /* CE4: host->target HTT */ @@ -74,6 +75,7 @@ .src_nentries = 32, .src_sz_max = 2048, .dest_nentries = 0, + .send_cb = ath12k_htc_tx_completion_handler, }, /* CE8: target autonomous hif_memcpy */ @@ -140,6 +142,14 @@ .src_sz_max = 0, .dest_nentries = 0, }, + + /* CE15: reserved for customer use */ + { + .flags = (CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, }; const struct ce_attr ath12k_host_ce_config_wcn7850[] = { @@ -219,6 +229,98 @@ }; +const struct ce_attr ath12k_host_ce_config_ipq5332[] = { + /* CE0: host->target HTC control and raw streams */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 16, + .src_sz_max = 2048, + .dest_nentries = 0, + }, + /* CE1: target->host HTT + HTC control */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 512, + .recv_cb = ath12k_htc_rx_completion_handler, + }, + /* CE2: target->host WMI */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 128, + .recv_cb = ath12k_htc_rx_completion_handler, + }, + /* CE3: host->target WMI */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 32, + .src_sz_max = 2048, + .dest_nentries = 0, + .send_cb = ath12k_htc_tx_completion_handler, + }, + /* CE4: host->target HTT */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 2048, + .src_sz_max = 256, + .dest_nentries = 0, + }, + /* CE5: target -> host PKTLOG */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 512, + .recv_cb = ath12k_dp_htt_htc_t2h_msg_handler, + }, + /* CE6: Target autonomous HIF_memcpy */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, + /* CE7: CV Prefetch */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + .send_cb = ath12k_htc_tx_completion_handler, + }, + /* CE8: Target HIF memcpy (Generic HIF memcypy) */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, + /* CE9: WMI logging/CFR/Spectral/Radar */ + { + .flags = CE_ATTR_FLAGS, + .src_nentries = 0, + .src_sz_max = 2048, + .dest_nentries = 128, + }, + /* CE10: Unused */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, + /* CE11: Unused */ + { + .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, + .src_nentries = 0, + .src_sz_max = 0, + .dest_nentries = 0, + }, +}; + static int ath12k_ce_rx_buf_enqueue_pipe(struct ath12k_ce_pipe *pipe, struct sk_buff *skb, dma_addr_t paddr) { @@ -447,18 +549,31 @@ return skb; } -static void ath12k_ce_send_done_cb(struct ath12k_ce_pipe *pipe) +static void ath12k_ce_tx_process_cb(struct ath12k_ce_pipe *pipe) { struct ath12k_base *ab = pipe->ab; struct sk_buff *skb; + struct sk_buff_head list; + __skb_queue_head_init(&list); while (!IS_ERR(skb = ath12k_ce_completed_send_next(pipe))) { if (!skb) continue; dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, skb->len, DMA_TO_DEVICE); + if ((!pipe->send_cb) || ab->hw_params->credit_flow) { dev_kfree_skb_any(skb); + continue; + } + + __skb_queue_tail(&list, skb); + } + + while ((skb = __skb_dequeue(&list))) { + ath12k_dbg(ab, ATH12K_DBG_PCI, "tx ce pipe %d len %d\n", + pipe->pipe_num, skb->len); + pipe->send_cb(ab, skb); } } @@ -484,6 +599,9 @@ ring_params->msi_addr = addr_lo; ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); + if (ab->hif.bus == ATH12K_BUS_HYBRID) + ring_params->msi_data = ab->ipci.ce_msi_data[ce_id]; + else ring_params->msi_data = (msi_data_idx % msi_data_count) + msi_data_start; ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; } @@ -528,7 +646,7 @@ /* TODO: Init other params needed by HAL to init the ring */ - ret = ath12k_hal_srng_setup(ab, type, ce_id, 0, ¶ms); + ret = ath12k_hal_srng_setup_idx(ab, type, ce_id, 0, ¶ms, 0); if (ret < 0) { ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n", ret, ce_id); @@ -588,7 +706,7 @@ pipe->attr_flags = attr->flags; if (attr->src_nentries) { - pipe->send_cb = ath12k_ce_send_done_cb; + pipe->send_cb = attr->send_cb; nentries = roundup_pow_of_two(attr->src_nentries); desc_sz = ath12k_hal_ce_get_desc_size(HAL_CE_DESC_SRC); ring = ath12k_ce_alloc_ring(ab, nentries, desc_sz); @@ -619,9 +737,10 @@ void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id) { struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[ce_id]; + const struct ce_attr *attr = &ab->hw_params->host_ce_config[ce_id]; - if (pipe->send_cb) - pipe->send_cb(pipe); + if (attr->src_nentries) + ath12k_ce_tx_process_cb(pipe); if (pipe->recv_cb) ath12k_ce_recv_process_cb(pipe); @@ -630,9 +749,33 @@ void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id) { struct ath12k_ce_pipe *pipe = &ab->ce.ce_pipe[pipe_id]; + const struct ce_attr *attr = &ab->hw_params->host_ce_config[pipe_id]; - if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && pipe->send_cb) - pipe->send_cb(pipe); + if ((pipe->attr_flags & CE_ATTR_DIS_INTR) && attr->src_nentries) + ath12k_ce_tx_process_cb(pipe); +} + +#define CE_RING_FULL_THRESHOLD_TIME_MS 500 +#define ATH12K_MAX_CE_MANUAL_RETRY 3 +/* Ths function is called from ce_send path. Returns true If there is no buffer + * to send packet via HTC, then check if interrupts are not processed from that + * CE for last 500ms. If so, poll manually to reap available entries. + */ +static bool ath12k_is_manual_ce_poll_needed(struct ath12k_base *ab, struct ath12k_ce_pipe *pipe, struct hal_srng *srng) +{ + if (!ab->hw_params->support_ce_manual_poll) + return false; + + if (time_after + (jiffies, pipe->timestamp + msecs_to_jiffies(CE_RING_FULL_THRESHOLD_TIME_MS)) && + (srng->u.src_ring.hp == srng->u.src_ring.reap_hp) && + (srng->u.src_ring.reap_hp == *srng->u.src_ring.tp_addr)) { + pipe->ce_manual_poll_count++; + pipe->last_ce_manual_poll_ts = jiffies; + return true; + } + + return false; } int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id, @@ -645,7 +788,7 @@ unsigned int nentries_mask; int ret = 0; u8 byte_swap_data = 0; - int num_used; + int num_used, retry = 0; /* Check if some entries could be regained by handling tx completion if * the CE has interrupts disabled and the used entries is more than the @@ -671,7 +814,7 @@ if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags)) return -ESHUTDOWN; - +retry: spin_lock_bh(&ab->ce.ce_lock); write_index = pipe->src_ring->write_index; @@ -692,9 +835,18 @@ desc = ath12k_hal_srng_src_get_next_reaped(ab, srng); if (!desc) { ath12k_hal_srng_access_end(ab, srng); + if (retry++ < ATH12K_MAX_CE_MANUAL_RETRY && + ath12k_is_manual_ce_poll_needed(ab, pipe, srng)) { + spin_unlock_bh(&srng->lock); + spin_unlock_bh(&ab->ce.ce_lock); + + ath12k_ce_tx_process_cb(pipe); + goto retry; + } else { ret = -ENOBUFS; goto unlock; } + } if (pipe->attr_flags & CE_ATTR_BYTE_SWAP_DATA) byte_swap_data = 1; @@ -880,6 +1032,8 @@ } } + ab->ce_pipe_init_done = true; + return 0; } @@ -926,6 +1080,8 @@ pipe->status_ring = NULL; } } + + ab->ce_pipe_init_done = false; } int ath12k_ce_alloc_pipes(struct ath12k_base *ab) diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/ce.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/ce.h --- linux-6.4/drivers/net/wireless/ath/ath12k/ce.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/ce.h 2024-01-19 17:01:19.853846702 +0100 @@ -8,6 +8,8 @@ #define ATH12K_CE_H #define CE_COUNT_MAX 16 +#define ATH12K_QCN6432_CE_COUNT 12 +#define ATH12K_QCN6432_EXT_IRQ_GRP_NUM_MAX 12 /* Byte swap data words */ #define CE_ATTR_BYTE_SWAP_DATA 2 @@ -39,8 +41,8 @@ #define PIPEDIR_INOUT_H2H 4 /* bidirectional, host to host */ /* CE address/mask */ -#define CE_HOST_IE_ADDRESS 0x00A1803C -#define CE_HOST_IE_2_ADDRESS 0x00A18040 +#define CE_HOST_IE_ADDRESS 0x75804c +#define CE_HOST_IE_2_ADDRESS 0x758050 #define CE_HOST_IE_3_ADDRESS CE_HOST_IE_ADDRESS #define CE_HOST_IE_3_SHIFT 0xC @@ -76,6 +78,17 @@ __le32 reserved; }; +struct ce_ie_addr { + u32 ie1_reg_addr; + u32 ie2_reg_addr; + u32 ie3_reg_addr; +}; + +struct ce_remap { + u32 base; + u32 size; +}; + struct ce_attr { /* CE_ATTR_* values */ unsigned int flags; @@ -92,6 +105,8 @@ unsigned int dest_nentries; void (*recv_cb)(struct ath12k_base *ab, struct sk_buff *skb); + + void (*send_cb)(struct ath12k_base *, struct sk_buff *); }; #define CE_DESC_RING_ALIGN 8 @@ -145,14 +160,16 @@ unsigned int buf_sz; unsigned int rx_buf_needed; - void (*send_cb)(struct ath12k_ce_pipe *pipe); + void (*send_cb)(struct ath12k_base *, struct sk_buff *); void (*recv_cb)(struct ath12k_base *ab, struct sk_buff *skb); struct tasklet_struct intr_tq; struct ath12k_ce_ring *src_ring; struct ath12k_ce_ring *dest_ring; struct ath12k_ce_ring *status_ring; - u64 timestamp; + unsigned long timestamp; + u32 ce_manual_poll_count; + u64 last_ce_manual_poll_ts; }; struct ath12k_ce { @@ -164,6 +181,7 @@ extern const struct ce_attr ath12k_host_ce_config_qcn9274[]; extern const struct ce_attr ath12k_host_ce_config_wcn7850[]; +extern const struct ce_attr ath12k_host_ce_config_ipq5332[]; void ath12k_ce_cleanup_pipes(struct ath12k_base *ab); void ath12k_ce_rx_replenish_retry(struct timer_list *t); diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/core.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/core.c --- linux-6.4/drivers/net/wireless/ath/ath12k/core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/core.c 2024-03-18 14:40:14.843741115 +0100 @@ -8,17 +8,364 @@ #include #include #include +#include #include +#include + +#include "peer.h" #include "core.h" +#include "coredump.h" #include "dp_tx.h" #include "dp_rx.h" #include "debug.h" #include "hif.h" +#include "sawf.h" +#include "ppe.h" +#include "ahb.h" +#include "telemetry.h" +#include "peer.h" + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#include +#include "bondif.h" +#endif unsigned int ath12k_debug_mask; module_param_named(debug_mask, ath12k_debug_mask, uint, 0644); MODULE_PARM_DESC(debug_mask, "Debugging mask"); +static unsigned int ath12k_crypto_mode; +module_param_named(crypto_mode, ath12k_crypto_mode, uint, 0644); +MODULE_PARM_DESC(crypto_mode, "crypto mode: 0-hardware, 1-software"); + +/* frame mode values are mapped as per enum ath12k_hw_txrx_mode */ +unsigned int ath12k_frame_mode = ATH12K_HW_TXRX_ETHERNET; +module_param_named(frame_mode, ath12k_frame_mode, uint, 0644); +MODULE_PARM_DESC(frame_mode, + "Datapath frame mode (0: raw, 1: native wifi (default), 2: ethernet)"); + +unsigned int ath12k_ftm_mode; +module_param_named(ftm_mode, ath12k_ftm_mode, uint, 0444); +MODULE_PARM_DESC(ftm_mode, "Boots up in factory test mode"); + +unsigned int ath12k_mlo_capable = 0; +module_param_named(mlo_capable, ath12k_mlo_capable, uint, 0644); +MODULE_PARM_DESC(mlo_capable, "mlo capable: 0-disable, 1-enable"); + +static unsigned int ath12k_en_fwlog = true; +module_param_named(en_fwlog, ath12k_en_fwlog, uint, 0644); +MODULE_PARM_DESC(en_fwlog, "fwlog: 0-disable, 1-enable"); + +unsigned int ath12k_ppe_ds_enabled = false; +module_param_named(ppe_ds_enable, ath12k_ppe_ds_enabled, uint, 0644); +MODULE_PARM_DESC(ppe_ds_enable, "ppe_ds_enable: 0-disable, 1-enable"); + +unsigned int ath12k_ssr_failsafe_mode = true; +module_param_named(ssr_failsafe_mode, ath12k_ssr_failsafe_mode, uint, 0644); +MODULE_PARM_DESC(ssr_failsafe_mode, "ssr failsafe mode: 0-disable, 1-enable"); + +bool ath12k_mgmt_rx_reordering = false; +module_param_named(mgmt_rx_reorder, ath12k_mgmt_rx_reordering, bool, 0644); +MODULE_PARM_DESC(mgmt_rx_reorder, "Mgmt Rx Re-Ordering (0 - disable, 1 - enable)"); + +bool ath12k_debug_critical = false; +module_param_named(debug_critical, ath12k_debug_critical, bool, 0644); +MODULE_PARM_DESC(debug_critical, "Debug critical issue (0 - disable, 1 - enable)"); + +static char *ath12k_board_variant; +module_param_named(board_variant, ath12k_board_variant, charp, 0444); +MODULE_PARM_DESC(board_variant, "board variant to use for bdf lookup"); + +bool ath12k_en_shutdown; +module_param_named(en_shutdown, ath12k_en_shutdown, bool, 0644); +MODULE_PARM_DESC(en_shutdown, "enable pcie shutdown callback"); + +bool ath12k_stats_disable; +module_param_named(stats_disable, ath12k_stats_disable, bool, 0644); +MODULE_PARM_DESC(stats_disable, "disable all HTT stats"); + +static DEFINE_MUTEX(ath12k_hw_lock); +static struct list_head ath12k_hw_groups = LIST_HEAD_INIT(ath12k_hw_groups); + +extern struct ath12k_coredump_info ath12k_coredump_ram_info; + +/* This function needs to be used only when dt has multi chip grouping information */ +static struct ath12k_hw_group *ath12k_core_hw_group_find_by_id(u8 group_id) +{ + struct ath12k_hw_group *ag; + + lockdep_assert_held(&ath12k_hw_lock); + + /* group ids will be unique only for multi chip group */ + list_for_each_entry(ag, &ath12k_hw_groups, list) { + if (group_id == ag->id && ag->num_chip > 1) + return ag; + } + + return NULL; +} + +static void ath12k_core_hw_group_free(struct ath12k_hw_group *ag) +{ + mutex_lock(&ath12k_hw_lock); + + list_del(&ag->list); + kfree(ag); + + mutex_unlock(&ath12k_hw_lock); +} + +void ath12k_core_put_hw_group(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + u8 chip_id = ab->chip_id; + int num_probed; + + if (!ag) + return; + + mutex_lock(&ag->mutex_lock); + + if (chip_id >= ag->num_chip) { + ath12k_err(ab, "failed to put Invalid chip id %d in the group id %d max chip %d\n", + chip_id, ag->id, ag->num_chip); + + return; + } + + if (ag->ab[chip_id] != ab) { + ath12k_err(ab, "failed to put chip id %d in the group id %d\n", + chip_id, ag->id); + + return; + } + + ag->ab[chip_id] = NULL; + ab->ag = NULL; + ab->chip_id = ATH12K_INVALID_CHIP_ID; + + if (ag->num_probed) + ag->num_probed--; + + num_probed = ag->num_probed; + + mutex_unlock(&ag->mutex_lock); + + if (!num_probed) + ath12k_core_hw_group_free(ag); + +} + +static void ath12k_core_hw_group_reset(struct work_struct *work) +{ + struct ath12k_hw_group *ag = container_of(work, struct ath12k_hw_group, reset_work); + struct ath12k_base *ab; + int i; + + if (ag->recovery_mode != ATH12K_MLO_RECOVERY_MODE0) + return; + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + if (ab->hif.bus == ATH12K_BUS_PCI) { + ag->crash_type = ATH12K_RPROC_ROOTPD_AHB_CRASH; + continue; + } + + if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->ag->dev_flags))) { + set_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags); + set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); + queue_work(ab->workqueue_aux, &ab->reset_work); + } + + ath12k_hal_dump_srng_stats(ab); + } +} + +static struct ath12k_hw_group * +ath12k_core_hw_group_alloc(u8 id, u8 max_chip) +{ + struct ath12k_hw_group *ag = NULL; + + lockdep_assert_held(&ath12k_hw_lock); + + ag = kzalloc(sizeof(*ag), GFP_KERNEL); + if (!ag) + return NULL; + + ag->id = id; + ag->num_chip = max_chip; + ag->mlo_capable = !!ath12k_mlo_capable; + atomic_set(&ag->num_dp_tx_pending, 0); + list_add(&ag->list, &ath12k_hw_groups); + mutex_init(&ag->mutex_lock); + mutex_init(&ag->mlomem_arena.mutex_lock); + spin_lock_init(&ag->mlo_umac_reset.lock); + ag->hw_queues_stopped = false; + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE0; + INIT_WORK(&ag->reset_work, ath12k_core_hw_group_reset); + + return ag; +} + +static struct ath12k_hw_group *ath12k_core_get_hw_group(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = NULL; + struct device_node *mlo; + struct device *dev = ab->dev; + u32 group_id, num_chips; + int ret; + + lockdep_assert_held(&ath12k_hw_lock); + + /* If there is no grouping info in the dt, we don't enable + * multi soc hw grouping and registration, rather the single + * soc is added to hw group and based on the number of links + * within the soc, all links are combined into a single wiphy. + */ + mlo = of_parse_phandle(dev->of_node, "qcom,wsi", 0); + if (mlo && ath12k_mlo_capable && !ath12k_ftm_mode) { + ret = of_property_read_u32(mlo, "id", &group_id); + if (ret) + group_id = ATH12K_INVALID_GRP_ID; + } else { + group_id = ATH12K_INVALID_GRP_ID; + } + +again: + if (group_id == ATH12K_INVALID_GRP_ID) { + ath12k_info(ab, "Grouping of multiple SoC not done\n"); + + ag = ath12k_core_hw_group_alloc(group_id, 1); + + if (!ag) { + ath12k_warn(ab, "unable to create new hw group\n"); + return NULL; + } + + if (ab->hw_params->support_umac_reset) + spin_lock_init(&ag->mlo_umac_reset.lock); + } else { + if (of_property_read_u32(mlo, "num_chip", &num_chips)) { + ath12k_err(ab, "num_chip is not configured\n"); + group_id = ATH12K_INVALID_GRP_ID; + goto again; + } + + if (num_chips > ATH12K_MAX_SOCS) { + ath12k_warn(ab, "num_chip advertised %d is more than limit %d\n", + num_chips, ATH12K_MAX_SOCS); + group_id = ATH12K_INVALID_GRP_ID; + goto again; + } + + /* currently only one group of multiple socs are supported, + * since we use group id ATH12K_INVALID_GRP_ID for single + * chip group which didn't have dt entry, there could be many + * groups with same group id, i.e ATH12K_INVALID_GRP_ID. So + * default group id of ATH12K_INVALID_GRP_ID combined with + * num chips in ath12k_hw_group determines if the group is + * multisoc or single soc group + */ + ag = ath12k_core_hw_group_find_by_id(group_id); + if (!ag) { + ag = ath12k_core_hw_group_alloc(group_id, num_chips); + + if (!ag) { + ath12k_warn(ab, "unable to create new hw group\n"); + return NULL; + } + + if (ab->hw_params->support_umac_reset) + spin_lock_init(&ag->mlo_umac_reset.lock); + + } else if (test_bit(ATH12K_FLAG_UNREGISTERING, &ag->dev_flags)) { + ath12k_dbg(ab, ATH12K_DBG_BOOT, "group id %d in unregister state\n", + ag->id); + group_id = ATH12K_INVALID_GRP_ID; + goto again; + } + } + + if (ag->num_probed >= ag->num_chip) { + ath12k_warn(ab, "unable to add new chip to group, max limit reached\n"); + group_id = ATH12K_INVALID_GRP_ID; + goto again; + } + + ab->chip_id = ag->num_probed; + ag->ab[ag->num_probed++] = ab; + ab->ag = ag; + return ag; +} + +static inline +bool ath12k_core_hw_group_create_ready(struct ath12k_hw_group *ag) +{ + lockdep_assert_held(&ag->mutex_lock); + + return (ag->num_probed == ag->num_chip); +} + +static inline +bool ath12k_core_hw_group_start_ready(struct ath12k_hw_group *ag) +{ + lockdep_assert_held(&ag->mutex_lock); + + return (ag->num_started == ag->num_chip); +} + +void ath12k_fw_stats_pdevs_free(struct list_head *head) +{ + struct ath12k_fw_stats_pdev *i, *tmp; + + list_for_each_entry_safe(i, tmp, head, list) { + list_del(&i->list); + kfree(i); + } +} + +static void ath12k_fw_stats_vdevs_free(struct list_head *head) +{ + struct ath12k_fw_stats_vdev *i, *tmp; + + list_for_each_entry_safe(i, tmp, head, list) { + list_del(&i->list); + kfree(i); + } +} + +void ath12k_fw_stats_bcn_free(struct list_head *head) +{ + struct ath12k_fw_stats_bcn *i, *tmp; + + list_for_each_entry_safe(i, tmp, head, list) { + list_del(&i->list); + kfree(i); + } +} + +void ath12k_fw_stats_init(struct ath12k *ar) +{ + INIT_LIST_HEAD(&ar->fw_stats.vdevs); + INIT_LIST_HEAD(&ar->fw_stats.pdevs); + INIT_LIST_HEAD(&ar->fw_stats.bcn); + init_completion(&ar->fw_stats_complete); +} + +void ath12k_fw_stats_reset(struct ath12k *ar) +{ + ath12k_fw_stats_pdevs_free(&ar->fw_stats.pdevs); + ath12k_fw_stats_vdevs_free(&ar->fw_stats.vdevs); +} + +void ath12k_fw_stats_free(struct ath12k_fw_stats *stats) +{ + ath12k_fw_stats_pdevs_free(&stats->pdevs); + ath12k_fw_stats_vdevs_free(&stats->vdevs); + ath12k_fw_stats_bcn_free(&stats->bcn); +} + int ath12k_core_suspend(struct ath12k_base *ab) { int ret; @@ -83,23 +430,87 @@ return 0; } -static int ath12k_core_create_board_name(struct ath12k_base *ab, char *name, - size_t name_len) +int ath12k_core_check_dt(struct ath12k_base *ab) +{ + size_t max_len = sizeof(ab->qmi.target.bdf_ext); + const char *variant = NULL; + struct device_node *node; + + node = ab->dev->of_node; + if (!node) + return -ENOENT; + + of_property_read_string(node, "qcom,ath12k-calibration-variant", + &variant); + if (!variant) + return -ENODATA; + + if (strscpy(ab->qmi.target.bdf_ext, variant, max_len) < 0) + ath12k_dbg(ab, ATH12K_DBG_BOOT, + "bdf variant string is longer than the buffer can accommodate (variant: %s)\n", + variant); + + return 0; +} + +static int ath12k_core_create_board_name(struct ath12k_base *ab, + char *boardname, + char *defaultboardname) { /* strlen(',variant=') + strlen(ab->qmi.target.bdf_ext) */ char variant[9 + ATH12K_QMI_BDF_EXT_STR_LENGTH] = { 0 }; - if (ab->qmi.target.bdf_ext[0] != '\0') + if (ath12k_board_variant) + scnprintf(variant, sizeof(variant), ",variant=%s", + ath12k_board_variant); + else if (ab->qmi.target.bdf_ext[0] != '\0') scnprintf(variant, sizeof(variant), ",variant=%s", ab->qmi.target.bdf_ext); + switch (ab->id.bdf_search) { + case ATH12K_BDF_SEARCH_BUS_AND_BOARD: + snprintf(boardname, BOARD_NAME_SIZE, + "bus=%s,vendor=%04x,device=%04x," + "subsystem-vendor=%04x," + "subsystem-device=%04x," + "qmi-chip-id=%d,qmi-board-id=%d%s", + ath12k_bus_str(ab->hif.bus), + ab->id.vendor, ab->id.device, + ab->id.subsystem_vendor, + ab->id.subsystem_device, + ab->qmi.target.chip_id, + ab->qmi.target.board_id, variant); - scnprintf(name, name_len, + snprintf(defaultboardname, BOARD_NAME_SIZE, + "bus=%s,vendor=%04x,device=%04x," + "subsystem-vendor=%04x," + "subsystem-device=%04x," + "qmi-chip-id=%d,qmi-board-id=%d%s", + ath12k_bus_str(ab->hif.bus), + ab->id.vendor, ab->id.device, + ab->id.subsystem_vendor, + ab->id.subsystem_device, + ab->qmi.target.chip_id, + ab->qmi.target.board_id, + variant); + break; + default: + snprintf(boardname, BOARD_NAME_SIZE, "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", ath12k_bus_str(ab->hif.bus), ab->qmi.target.chip_id, ab->qmi.target.board_id, variant); - ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot using board name '%s'\n", name); + snprintf(defaultboardname, BOARD_NAME_SIZE, + "bus=%s,qmi-chip-id=%d,qmi-board-id=%d%s", + ath12k_bus_str(ab->hif.bus), + ab->qmi.target.chip_id, + ATH12K_DEFAULT_ID, variant); + break; + } + + ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot using board name : '%s'\t" + "default boardname : '%s'\n", boardname, + defaultboardname); return 0; } @@ -128,17 +539,15 @@ void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd) { - if (!IS_ERR(bd->fw)) + if (!IS_ERR(bd->fw)) { release_firmware(bd->fw); - - memset(bd, 0, sizeof(*bd)); + bd->fw = NULL; + } } static int ath12k_core_parse_bd_ie_board(struct ath12k_base *ab, struct ath12k_board_data *bd, - const void *buf, size_t buf_len, - const char *boardname, - int bd_ie_type) + const void *buf, size_t buf_len) { const struct ath12k_fw_ie *hdr; bool name_match_found; @@ -148,7 +557,7 @@ name_match_found = false; - /* go through ATH12K_BD_IE_BOARD_ elements */ + /* go through ATH12K_BD_IE_BOARD_/ATH12K_BD_IE_REGDB_ elements */ while (buf_len > sizeof(struct ath12k_fw_ie)) { hdr = buf; board_ie_id = le32_to_cpu(hdr->id); @@ -159,48 +568,51 @@ buf += sizeof(*hdr); if (buf_len < ALIGN(board_ie_len, 4)) { - ath12k_err(ab, "invalid ATH12K_BD_IE_BOARD length: %zu < %zu\n", + ath12k_err(ab, "invalid %s length: %zu < %zu\n", + ath12k_bd_ie_type_str(bd->ie_id), buf_len, ALIGN(board_ie_len, 4)); ret = -EINVAL; goto out; } - switch (board_ie_id) { - case ATH12K_BD_IE_BOARD_NAME: + if (board_ie_id == bd->name_id) { ath12k_dbg_dump(ab, ATH12K_DBG_BOOT, "board name", "", board_ie_data, board_ie_len); - if (board_ie_len != strlen(boardname)) - break; + if (board_ie_len != strlen(bd->boardname)) + goto next; - ret = memcmp(board_ie_data, boardname, strlen(boardname)); + ret = memcmp(board_ie_data, bd->boardname, strlen(bd->boardname)); if (ret) - break; + goto next; name_match_found = true; ath12k_dbg(ab, ATH12K_DBG_BOOT, - "boot found match for name '%s'", - boardname); - break; - case ATH12K_BD_IE_BOARD_DATA: + "boot found match %s for name '%s'", + ath12k_bd_ie_type_str(bd->ie_id), + bd->boardname); + } else if (board_ie_id == bd->data_id) { if (!name_match_found) /* no match found */ - break; + goto next; ath12k_dbg(ab, ATH12K_DBG_BOOT, - "boot found board data for '%s'", boardname); + "boot found %s for '%s'", + ath12k_bd_ie_type_str(bd->ie_id), + bd->boardname); bd->data = board_ie_data; bd->len = board_ie_len; ret = 0; goto out; - default: - ath12k_warn(ab, "unknown ATH12K_BD_IE_BOARD found: %d\n", + } else { + ath12k_warn(ab, "unknown %s id found: %d\n", + ath12k_bd_ie_type_str(bd->ie_id), board_ie_id); - break; } +next: /* jump over the padding */ board_ie_len = ALIGN(board_ie_len, 4); @@ -216,8 +628,7 @@ } static int ath12k_core_fetch_board_data_api_n(struct ath12k_base *ab, - struct ath12k_board_data *bd, - const char *boardname) + struct ath12k_board_data *bd) { size_t len, magic_len; const u8 *data; @@ -282,15 +693,12 @@ goto err; } - switch (ie_id) { - case ATH12K_BD_IE_BOARD: + if (ie_id == bd->ie_id) { ret = ath12k_core_parse_bd_ie_board(ab, bd, data, - ie_len, - boardname, - ATH12K_BD_IE_BOARD); + ie_len); if (ret == -ENOENT) /* no match found, continue */ - break; + goto next; else if (ret) /* there was an error, bail out */ goto err; @@ -298,6 +706,7 @@ goto out; } +next: /* jump over the padding */ ie_len = ALIGN(ie_len, 4); @@ -307,9 +716,10 @@ out: if (!bd->data || !bd->len) { - ath12k_err(ab, - "failed to fetch board data for %s from %s\n", - boardname, filepath); + ath12k_dbg(ab, ATH12K_DBG_BOOT, + "failed to fetch %s for %s from %s\n", + ath12k_bd_ie_type_str(bd->ie_id), + bd->boardname, filepath); ret = -ENODATA; goto err; } @@ -326,6 +736,7 @@ char *filename) { bd->fw = ath12k_core_firmware_request(ab, filename); + if (IS_ERR(bd->fw)) return PTR_ERR(bd->fw); @@ -335,41 +746,179 @@ return 0; } -#define BOARD_NAME_SIZE 100 int ath12k_core_fetch_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd) { - char boardname[BOARD_NAME_SIZE]; + char boardname[BOARD_NAME_SIZE] = {}; + char defaultboardname[BOARD_NAME_SIZE] = {}; + u8 bd_api; int ret; - ret = ath12k_core_create_board_name(ab, boardname, BOARD_NAME_SIZE); + ret = ath12k_core_create_board_name(ab, boardname, defaultboardname); if (ret) { ath12k_err(ab, "failed to create board name: %d", ret); return ret; } - ab->bd_api = 2; - ret = ath12k_core_fetch_board_data_api_n(ab, bd, boardname); + bd_api = 2; + bd->ie_id = ATH12K_BD_IE_BOARD; + bd->name_id = ATH12K_BD_IE_BOARD_NAME; + bd->data_id = ATH12K_BD_IE_BOARD_DATA; + memcpy(bd->boardname, boardname, BOARD_NAME_SIZE); + + ret = ath12k_core_fetch_board_data_api_n(ab, bd); if (!ret) goto success; - ab->bd_api = 1; + memcpy(bd->boardname, defaultboardname, BOARD_NAME_SIZE); + + ret = ath12k_core_fetch_board_data_api_n(ab, bd); + if (!ret) + goto success; + + bd_api = 1; ret = ath12k_core_fetch_board_data_api_1(ab, bd, ATH12K_DEFAULT_BOARD_FILE); if (ret) { - ath12k_err(ab, "failed to fetch board-2.bin or board.bin from %s\n", + ath12k_err(ab, "failed to fetch board-2.bin from %s\n", + ab->hw_params->fw.dir); + } else { + ret = ath12k_core_fetch_board_data_api_1(ab, bd, ATH12K_BOARD_API2_FILE); + if (ret) + ath12k_err(ab, "failed to fetch board-2.bin from %s\n", ab->hw_params->fw.dir); return ret; } success: - ath12k_dbg(ab, ATH12K_DBG_BOOT, "using board api %d\n", ab->bd_api); + ath12k_dbg(ab, ATH12K_DBG_BOOT, "using board api %hhu\n", bd_api); + return 0; +} + +int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd) +{ + char regdbname[BOARD_NAME_SIZE] = {}; + char defaultregdbname[BOARD_NAME_SIZE] = {}; + u8 bd_api; + int ret; + + ret = ath12k_core_create_board_name(ab, regdbname, defaultregdbname); + if (ret) { + ath12k_err(ab, "failed to create regdb name: %d", ret); + return ret; + } + + bd_api = 2; + bd->ie_id = ATH12K_BD_IE_REGDB; + bd->name_id = ATH12K_BD_IE_REGDB_NAME; + bd->data_id = ATH12K_BD_IE_REGDB_DATA; + memcpy(bd->boardname, regdbname, BOARD_NAME_SIZE); + + ret = ath12k_core_fetch_board_data_api_n(ab, bd); + if (!ret) + goto success; + + memcpy(bd->boardname, defaultregdbname, BOARD_NAME_SIZE); + + ret = ath12k_core_fetch_board_data_api_n(ab, bd); + if (!ret) + goto success; + + bd_api = 1; + ret = ath12k_core_fetch_board_data_api_1(ab, bd, ATH12K_REGDB_FILE_NAME); + if (ret) { + ath12k_err(ab, "failed to fetch %s file from %s\n", + ATH12K_REGDB_FILE_NAME, ab->hw_params->fw.dir); + return ret; + } + +success: + ath12k_dbg(ab, ATH12K_DBG_BOOT, "using board api %hhu\n", bd_api); + return 0; +} + +int ath12k_core_fetch_fw_cfg(struct ath12k_base *ab, + struct ath12k_board_data *bd) +{ + int ret; + + ret = ath12k_core_fetch_board_data_api_1(ab, bd, ATH12K_FW_CFG_FILE); + if (ret) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "failed to fetch %s from %s\n", + ATH12K_FW_CFG_FILE, ab->hw_params->fw.dir); + return -ENOENT; + } + + ath12k_info(ab, "fetching %s from %s\n", ATH12K_FW_CFG_FILE, + ab->hw_params->fw.dir); + + return 0; +} + +int ath12k_core_fetch_rxgainlut(struct ath12k_base *ab, struct ath12k_board_data *bd) +{ + char rxgainlutname[BOARD_NAME_SIZE] = {}; + char rxgainlutdefaultname[BOARD_NAME_SIZE] = {}; + int ret; + u8 bd_api; + + ret = ath12k_core_create_board_name(ab, rxgainlutname, + rxgainlutdefaultname); + if (ret) { + ath12k_err(ab, "failed to create rxgainlut name: %d", ret); + return ret; + } + + bd_api = 2; + bd->ie_id = ATH12K_BD_IE_RXGAINLUT; + bd->name_id = ATH12K_BD_IE_RXGAINLUT_NAME; + bd->data_id = ATH12K_BD_IE_RXGAINLUT_DATA; + memcpy(bd->boardname, rxgainlutname, BOARD_NAME_SIZE); + + ret = ath12k_core_fetch_board_data_api_n(ab, bd); + + if (!ret) + goto success; + + memcpy(bd->boardname, rxgainlutdefaultname, BOARD_NAME_SIZE); + + ret = ath12k_core_fetch_board_data_api_n(ab, bd); + + if (!ret) + goto success; + + bd_api = 1; + snprintf(rxgainlutname, sizeof(rxgainlutname), "%s%04x", + ATH12K_RXGAINLUT_FILE_PREFIX, ab->qmi.target.board_id); + + ret = ath12k_core_fetch_board_data_api_1(ab, bd, rxgainlutname); + if (ret) { + ath12k_dbg(ab, ATH12K_DBG_BOOT, "failed to fetch %s from %s\n", + rxgainlutname, ab->hw_params->fw.dir); + + ret = ath12k_core_fetch_board_data_api_1(ab, bd, + ATH12K_RXGAINLUT_FILE); + if (ret) { + ath12k_warn(ab, "failed to fetch default %s from %s\n", + ATH12K_RXGAINLUT_FILE, ab->hw_params->fw.dir); + return -ENOENT; + } + } + +success: + ath12k_dbg(ab, ATH12K_DBG_BOOT, "using board api %hhu\n", bd_api); return 0; } static void ath12k_core_stop(struct ath12k_base *ab) { + lockdep_assert_held(&ab->ag->mutex_lock); + lockdep_assert_held(&ab->core_lock); + + ab->ag->num_started--; + if (!test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags)) ath12k_qmi_firmware_stop(ab); + ath12k_mgmt_rx_reo_deinit_context(ab); ath12k_hif_stop(ab); ath12k_wmi_detach(ab); ath12k_dp_rx_pdev_reo_cleanup(ab); @@ -381,6 +930,11 @@ { int ret; + if (ath12k_ftm_mode) { + ab->fw_mode = ATH12K_FIRMWARE_MODE_FTM; + ath12k_info(ab, "Booting in ftm mode\n"); + } + ret = ath12k_qmi_init_service(ab); if (ret) { ath12k_err(ab, "failed to initialize qmi :%d\n", ret); @@ -402,40 +956,397 @@ static void ath12k_core_soc_destroy(struct ath12k_base *ab) { - ath12k_dp_free(ab); - ath12k_reg_free(ab); ath12k_qmi_deinit_service(ab); } +/** + * ath12k_core_mgmt_rx_reo_init_ss_params() - Initialize a given snapshot + * params object + * @snapshot_params: Pointer to snapshot params object + * + * Return: void + */ +static void +ath12k_core_mgmt_rx_reo_init_ss_params( + struct ath12k_mgmt_rx_reo_snapshot_params *snapshot_params) +{ + snapshot_params->valid = false; + snapshot_params->mgmt_pkt_ctr = 0; + snapshot_params->global_timestamp = 0; +} + +/** + * ath12k_core_rx_reo_init_ss_value() - Initialize management Rx reorder + * snapshot values for a given pdev + * @pdev: pointer to pdev object + * + * Return: 0 for success, non-zero for failure + */ +static int +ath12k_core_rx_reo_init_ss_value(struct ath12k *ar) +{ + enum ath12k_mgmt_rx_reo_shared_snapshot_id snapshot_id; + struct ath12k_mgmt_rx_reo_pdev_info *mgmt_rx_reo_pdev_ctx; + + mgmt_rx_reo_pdev_ctx = &ar->rx_reo_pdev_ctx; + snapshot_id = 0; + while (snapshot_id < ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX) { + ath12k_core_mgmt_rx_reo_init_ss_params + (&mgmt_rx_reo_pdev_ctx->last_valid_shared_snapshot + [snapshot_id]); + snapshot_id++; + } + + /* Initialize Host snapshot params */ + ath12k_core_mgmt_rx_reo_init_ss_params + (&mgmt_rx_reo_pdev_ctx->host_snapshot); + + return 0; +} + +void *ath12k_core_mgmt_rx_reo_get_ss_address( + struct ath12k_base *ab, + u8 link_id, + enum ath12k_mgmt_rx_reo_shared_snapshot_id snapshot_id) +{ + struct ath12k_host_mlo_mem_arena *mlomem_arena_ctx; + struct ath12k_host_mlo_glb_rx_reo_snapshot_info *snapshot_info; + struct ath12k_host_mlo_glb_rx_reo_per_link_info *snapshot_link_info; + u8 link; + + if (snapshot_id >= ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX) { + ath12k_err(ab, "Invalid snapshot ID: %d\n", snapshot_id); + return NULL; + } + + mlomem_arena_ctx = &ab->ag->mlomem_arena; + snapshot_info = &mlomem_arena_ctx->rx_reo_snapshot_info; + + for (link = 0; link < snapshot_info->num_links; ++link) { + snapshot_link_info = &snapshot_info->link_info[link]; + + if (link_id == snapshot_link_info->link_id) + break; + } + + if (link == snapshot_info->num_links) { + ath12k_err(ab, "Couldn't find the snapshot link info corresponding to the link %d\n", + link_id); + return NULL; + } + + switch (snapshot_id) { + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAC_HW: + return snapshot_link_info->hw_forwarded; + + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_CONSUMED: + return snapshot_link_info->fw_consumed; + + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_FORWARDED: + return snapshot_link_info->fw_forwarded; + + default: + WARN_ON(1); + } + + return NULL; +} + +static int ath12k_mgmt_rx_reo_get_snapshot_version(struct ath12k_base *ab, + enum ath12k_mgmt_rx_reo_shared_snapshot_id id) +{ + struct ath12k_host_mlo_mem_arena *mlomem_arena_ctx; + struct ath12k_host_mlo_glb_rx_reo_snapshot_info *snapshot_info; + int snapshot_version; + + if (id >= ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX) { + ath12k_err(ab, "Invalid snapshot ID: %d\n", id); + return ATH12K_MGMT_RX_REO_INVALID_SNAPSHOT_VERSION; + } + + mlomem_arena_ctx = &ab->ag->mlomem_arena; + snapshot_info = &mlomem_arena_ctx->rx_reo_snapshot_info; + + switch (id) { + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAC_HW: + snapshot_version = snapshot_info->hw_forwarded_snapshot_ver; + break; + + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_CONSUMED: + snapshot_version = snapshot_info->fw_consumed_snapshot_ver; + break; + + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_FORWARDED: + snapshot_version = snapshot_info->fw_forwarded_snapshot_ver; + break; + + default: + snapshot_version = ATH12K_MGMT_RX_REO_INVALID_SNAPSHOT_VERSION; + break; + } + + return snapshot_version; +} + +static int +ath12k_core_mgmt_rx_reo_get_snapshot_info + (struct ath12k *ar, + enum ath12k_mgmt_rx_reo_shared_snapshot_id id, + struct ath12k_mgmt_rx_reo_snapshot_info *snapshot_info) +{ + u8 link_id; + u8 snapshot_version; + struct ath12k_base *ab; + + ab = ar->ab; + + if (id >= ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX) { + ath12k_err(ab, "Mgmt RX REO snapshot id invalid %d\n", id); + return -EINVAL; + } + + if (!snapshot_info) { + ath12k_err(ab, "Ref to mgmt RX REO snapshot info is null\n"); + return -EINVAL; + } + + link_id = ar->pdev->hw_link_id; + + snapshot_info->address = + ath12k_core_mgmt_rx_reo_get_ss_address(ab, link_id, id); + if (!snapshot_info->address) { + ath12k_err(ab, "NULL snapshot address\n"); + return -EINVAL; + } + + snapshot_version = ath12k_mgmt_rx_reo_get_snapshot_version(ab, id); + if (snapshot_version < 0) { + ath12k_err(ab, "Invalid snapshot version %d\n", + snapshot_version); + return -EINVAL; + } + + snapshot_info->version = snapshot_version; + + return 0; +} + +/** + * ath12k_mgmt_rx_reo_initialize_snapshot_address() - Initialize management Rx reorder + * snapshot addresses for a given pdev + * @pdev: pointer to pdev object + * + * Return: 0 for success, non-zero for failure + */ +static int +ath12k_core_mgmt_rx_reo_init_ss_address(struct ath12k *ar) +{ + enum ath12k_mgmt_rx_reo_shared_snapshot_id snapshot_id; + struct ath12k_mgmt_rx_reo_pdev_info *mgmt_rx_reo_pdev_ctx; + int status; + + mgmt_rx_reo_pdev_ctx = &ar->rx_reo_pdev_ctx; + snapshot_id = 0; + while (snapshot_id < ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX) { + struct ath12k_mgmt_rx_reo_snapshot_info *snapshot_info; + + snapshot_info = + &mgmt_rx_reo_pdev_ctx->host_target_shared_snapshot_info + [snapshot_id]; + status = ath12k_core_mgmt_rx_reo_get_snapshot_info + (ar, snapshot_id, snapshot_info); + if (status) { + ath12k_err(ar->ab, "Get snapshot info failed, id = %u\n", + snapshot_id); + return status; + } + + snapshot_id++; + } + + return 0; +} + +static int ath12k_core_mgmt_rx_reordering_init(struct ath12k_base *ab) +{ + int i, ret; + struct ath12k *ar; + struct ath12k_pdev *pdev; + struct ath12k_hw_group *ag = ab->ag; + + if (!(ag->mlo_mem.is_mlo_mem_avail && ag->mgmt_rx_reorder)) + return 0; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + if (!ar) + continue; + ret = ath12k_core_rx_reo_init_ss_value(ar); + if (ret) { + ath12k_err(ab, "Failed to initialize snapshot value\n"); + return ret; + } + + ret = ath12k_core_mgmt_rx_reo_init_ss_address(ar); + if (ret) { + ath12k_err(ab, "Failed to initialize snapshot address\n"); + return ret; + } + + ar->rx_reo_pdev_ctx.init_complete = true; + } + + return 0; +} + +static int ath12k_core_mlo_shmem_per_chip_crash_info_addresses( + struct ath12k_base *ab, + struct ath12k_host_mlo_glb_chip_crash_info *global_chip_crash_info, + int chip_id) +{ + int i; + struct ath12k_host_mlo_glb_per_chip_crash_info *per_chip_crash_info = NULL; + + for (i = 0; i < global_chip_crash_info->no_of_chips; i++) + { + per_chip_crash_info = &global_chip_crash_info->per_chip_crash_info[i]; + + if (!per_chip_crash_info) + return -EINVAL; + + if (chip_id == per_chip_crash_info->chip_id) + break; + } + + if (i >= global_chip_crash_info->no_of_chips) { + ath12k_err(ab, "error in chip id:%d\n", chip_id); + return 0; + } + + if (!per_chip_crash_info || + !per_chip_crash_info->crash_reason || + !per_chip_crash_info->recovery_mode) { + ath12k_err(ab, "crash_reason address is null\n"); + return 0; + } + + ab->crash_info_address = per_chip_crash_info->crash_reason; + ab->recovery_mode_address = per_chip_crash_info->recovery_mode; + + return 0; +} + +static int ath12k_core_mlo_shmem_crash_info_init(struct ath12k_base *ab, int index) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_host_mlo_mem_arena *mlomem_arena_ctx; + struct ath12k_host_mlo_glb_chip_crash_info *global_chip_crash_info; + + mlomem_arena_ctx = &ab->ag->mlomem_arena; + + if (!(ag->mlo_mem.is_mlo_mem_avail)) + return 0; + + global_chip_crash_info = &mlomem_arena_ctx->global_chip_crash_info; + + if (ath12k_core_mlo_shmem_per_chip_crash_info_addresses(ab, + global_chip_crash_info, + index) < 0) { + ath12k_warn(ab, "per_chip_crash_info is not set\n"); + return -EINVAL; + } + + return 0; +} + +static int ath12k_core_pdev_init(struct ath12k_base *ab) +{ + int ret; + + ret = ath12k_thermal_register(ab); + if (ret) { + ath12k_err(ab, "could not register thermal device: %d\n", + ret); + return ret; + } + + ret = ath12k_spectral_init(ab); + if (ret) { + ath12k_err(ab, "failed to init spectral %d\n", ret); + goto err_thermal_unregister; + } + + ret = ath12k_core_mgmt_rx_reordering_init(ab); + if (ret) { + ath12k_err(ab, "failed to rx reo reordering %d\n", ret); + goto err_spectral_deinit; + } + + ath12k_sawf_init(ab); + ath12k_telemetry_init(ab); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ret = ath12k_dp_ppeds_start(ab); + if (ret) { + ath12k_err(ab, "failed to start DP PPEDS \n"); + goto err_dp_ppeds_stop; + } +#endif + return 0; + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +err_dp_ppeds_stop: + ath12k_dp_ppeds_stop(ab); +#endif +err_spectral_deinit: + ath12k_spectral_deinit(ab); +err_thermal_unregister: + ath12k_thermal_unregister(ab); + return ret; +} + +static void ath12k_core_pdev_deinit(struct ath12k_base *ab) +{ +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ath12k_dp_ppeds_stop(ab); +#endif + ath12k_spectral_deinit(ab); + ath12k_thermal_unregister(ab); + ath12k_telemetry_deinit(ab); + ath12k_sawf_deinit(ab); +} + static int ath12k_core_pdev_create(struct ath12k_base *ab) { int ret; - ret = ath12k_mac_register(ab); + ret = ath12k_debugfs_pdev_create(ab); if (ret) { - ath12k_err(ab, "failed register the radio with mac80211: %d\n", ret); + ath12k_err(ab, "failed to create core pdev debugfs: %d\n", ret); + /* Free any previously allocated ab info */ return ret; } ret = ath12k_dp_pdev_alloc(ab); if (ret) { ath12k_err(ab, "failed to attach DP pdev: %d\n", ret); - goto err_mac_unregister; + /* Free current debugfs and any previously allocated info */ + goto err_debugfs_pdev; } return 0; -err_mac_unregister: - ath12k_mac_unregister(ab); +err_debugfs_pdev: + ath12k_debugfs_pdev_destroy(ab); return ret; } static void ath12k_core_pdev_destroy(struct ath12k_base *ab) { - ath12k_mac_unregister(ab); - ath12k_hif_irq_disable(ab); ath12k_dp_pdev_free(ab); + ath12k_debugfs_pdev_destroy(ab); } static int ath12k_core_start(struct ath12k_base *ab, @@ -443,6 +1354,9 @@ { int ret; + lockdep_assert_held(&ab->ag->mutex_lock); + lockdep_assert_held(&ab->core_lock); + ret = ath12k_wmi_attach(ab); if (ret) { ath12k_err(ab, "failed to attach wmi: %d\n", ret); @@ -492,21 +1406,12 @@ goto err_hif_stop; } - ret = ath12k_mac_allocate(ab); - if (ret) { - ath12k_err(ab, "failed to create new hw device with mac80211 :%d\n", - ret); - goto err_hif_stop; - } - ath12k_dp_cc_config(ab); - ath12k_dp_pdev_pre_alloc(ab); - ret = ath12k_dp_rx_pdev_reo_setup(ab); if (ret) { ath12k_err(ab, "failed to initialize reo destination rings: %d\n", ret); - goto err_mac_destroy; + goto err_hif_stop; } ret = ath12k_wmi_cmd_init(ab); @@ -522,6 +1427,8 @@ goto err_reo_cleanup; } + WARN_ON(test_bit(ATH12K_FLAG_WMI_INIT_DONE, &ab->dev_flags)); + set_bit(ATH12K_FLAG_WMI_INIT_DONE, &ab->dev_flags); /* put hardware to DBS mode */ if (ab->hw_params->single_pdev_only) { ret = ath12k_wmi_set_hw_mode(ab, WMI_HOST_HW_MODE_DBS); @@ -538,12 +1445,13 @@ goto err_reo_cleanup; } + /* Indicate the core start in the appropriate group */ + ab->ag->num_started++; + return 0; err_reo_cleanup: ath12k_dp_rx_pdev_reo_cleanup(ab); -err_mac_destroy: - ath12k_mac_destroy(ab); err_hif_stop: ath12k_hif_stop(ab); err_wmi_detach: @@ -551,6 +1459,225 @@ return ret; } +static int ath12k_core_mlo_teardown(struct ath12k_hw_group *ag) +{ + struct ath12k_hw *ah; + int ret; + int i; + + if (!ag->mlo_capable) + return 0; + + for (i = ag->num_hw - 1; i >= 0; i--) { + ah = ag->ah[i]; + if (!ah) + continue; + + ret = ath12k_mac_mlo_teardown(ah); + if (ret) + goto out; + } + +out: + return ret; +} + +static int ath12k_core_mlo_setup(struct ath12k_hw_group *ag) +{ + struct ath12k_hw *ah; + int ret; + int i; + + if (!ag->mlo_capable) + return 0; + + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; + + ret = ath12k_mac_mlo_setup(ah); + if (ret) + goto err_setup; + } + + for (i = 0; i < ag->num_chip; i++) + ath12k_dp_partner_cc_init(ag->ab[i]); + + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; + + ret = ath12k_mac_mlo_ready(ah); + if (ret) + goto err_ready; + } + + return 0; + +err_ready: + i = ag->num_hw; +err_setup: + for (i = i - 1; i >= 0; i--) { + ah = ag->ah[i]; + if (!ah) + continue; + + ath12k_mac_mlo_teardown(ah); + } + + return ret; +} + +static int ath12k_core_hw_group_start(struct ath12k_hw_group *ag) +{ + struct ath12k_base *ab = ag->ab[0]; + int ret, i; + bool is_registered = false; + + lockdep_assert_held(&ag->mutex_lock); + + /* Check If already registered or not, since same flow + * execute for HW restart case. + */ + if (test_bit(ATH12K_FLAG_REGISTERED, &ag->dev_flags)) + is_registered = true; + + if (!is_registered) { + ret = ath12k_mac_allocate(ag); + if (ret) { + ath12k_err(ab, "failed to create new hw device with mac80211 :%d\n", + ret); + return ret; + } + } + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + /* pdev create needs to be done only for recovered + * ab during Mode1 scenario + */ + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1 && !ab->recovery_start) + continue; + + mutex_lock(&ab->core_lock); + ret = ath12k_core_pdev_create(ab); + if (ret) { + mutex_unlock(&ab->core_lock); + ath12k_err(ab, "failed to create pdev core %d\n", ret); + goto err_pdev_destroy; + } + mutex_unlock(&ab->core_lock); + } + + ret = ath12k_core_mlo_setup(ag); + if (ret) { + ath12k_err(NULL, "failed to setup MLO: %d\n", ret); + goto err_pdev_destroy; + } + + if (!is_registered) { + ret = ath12k_mac_register(ag); + if (ret) { + ath12k_err(ab, "failed register the radio with mac80211: %d\n", ret); + goto err_mlo_teardown; + } + } + + /* Setup pdev features for all ab */ + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + /* pdev init needs to be done only for recovered + * ab during Mode1 scenario + */ + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1 && !ab->recovery_start) + continue; + + mutex_lock(&ab->core_lock); + + ret = ath12k_core_pdev_init(ab); + if (ret) { + mutex_unlock(&ab->core_lock); + ath12k_err(ab, "failed to init pdev features\n"); + goto pdev_cleanup; + } + ath12k_hif_irq_enable(ab); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ath12k_hif_ppeds_irq_enable(ab, PPEDS_IRQ_PPE2TCL); + ath12k_hif_ppeds_irq_enable(ab, PPEDS_IRQ_REO2PPE); + ath12k_hif_ppeds_irq_enable(ab, PPEDS_IRQ_PPE_WBM2SW_REL); +#endif + if (ab->hw_params->en_qdsslog) { + ath12k_info(ab, "QDSS trace enabled\n"); + ath12k_config_qdss(ab); + } + + if (ath12k_en_fwlog == true) { + ret = ath12k_enable_fwlog(ab); + if (ret < 0) { + mutex_unlock(&ab->core_lock); + ath12k_err(ab, "failed to enable fwlog: %d\n", ret); + goto pdev_cleanup; + } + } + + ret = ath12k_dp_umac_reset_init(ab); + if (ret) { + mutex_unlock(&ab->core_lock); + ath12k_warn(ab, "Failed to initialize UMAC RESET: %d\n", ret); + goto pdev_cleanup; + } + + ret = ath12k_core_mlo_shmem_crash_info_init(ab, i); + if (ret) { + ath12k_err(ab, "failed to parse crash info %d\n", ret); + } + + set_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags); + + mutex_unlock(&ab->core_lock); + } + + if (!is_registered) { + set_bit(ATH12K_FLAG_REGISTERED, &ag->dev_flags); + init_completion(&ag->umac_reset_complete); + } + + return 0; + +pdev_cleanup: + for (i = i - 1; i >= 0; i--) { + ab = ag->ab[i]; + + mutex_lock(&ab->core_lock); + + ath12k_core_pdev_deinit(ab); + ath12k_hif_irq_disable(ab); + ath12k_dp_umac_reset_deinit(ab); + + mutex_unlock(&ab->core_lock); + } + + ath12k_mac_unregister(ag); +err_mlo_teardown: + ath12k_core_mlo_teardown(ag); + i = ag->num_chip; +err_pdev_destroy: + for (i = i - 1; i >= 0; i--) { + ab = ag->ab[i]; + + mutex_lock(&ab->core_lock); + ath12k_core_pdev_destroy(ab); + mutex_unlock(&ab->core_lock); + } + + ath12k_mac_destroy(ag); + return ret; +} + static int ath12k_core_start_firmware(struct ath12k_base *ab, enum ath12k_firmware_mode mode) { @@ -568,11 +1695,37 @@ return ret; } +static void ath12k_core_trigger_partner(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_base *partner_ab; + int i; + bool found = false; + + lockdep_assert_held(&ag->mutex_lock); + + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + if (!partner_ab) + continue; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "QMI Trigger Host Cap AB:%p Partner AB:%p Found:%d Num Radios: %d ag->num_chip:%d\n", + ab, partner_ab, found, + ab->qmi.num_radios, ag->num_chip); + + if (found) + ath12k_qmi_trigger_host_cap(partner_ab); + + found = (partner_ab == ab) ? true : false; + } +} + int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab) { + struct ath12k_hw_group *ag; int ret; - ret = ath12k_core_start_firmware(ab, ATH12K_FIRMWARE_MODE_NORMAL); + ret = ath12k_core_start_firmware(ab, ab->fw_mode); if (ret) { ath12k_err(ab, "failed to start firmware: %d\n", ret); return ret; @@ -584,47 +1737,329 @@ goto err_firmware_stop; } +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (ath12k_ppe_ds_enabled) { + if (ath12k_frame_mode != ATH12K_HW_TXRX_ETHERNET) { + ath12k_warn(ab, + "Force enabling Ethernet frame mode in PPE DS for" \ + " AP and STA modes.\n"); + /* MESH and WDS VAPs will still use NATIVE_WIFI mode + * @ath12k_mac_update_vif_offload() + * TODO: add device capability check + */ + ath12k_frame_mode = ATH12K_HW_TXRX_ETHERNET; + } + if (ab->hif.bus == ATH12K_BUS_PCI || ab->hif.bus == ATH12K_BUS_HYBRID) + set_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags); + } +#endif + ret = ath12k_dp_alloc(ab); if (ret) { ath12k_err(ab, "failed to init DP: %d\n", ret); goto err_firmware_stop; } + ag = ab->ag; + + switch (ath12k_crypto_mode) { + case ATH12K_CRYPT_MODE_SW: + set_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ag->dev_flags); + set_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags); + break; + case ATH12K_CRYPT_MODE_HW: + clear_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ag->dev_flags); + clear_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags); + break; + default: + ath12k_info(ab, "invalid crypto_mode: %d\n", ath12k_crypto_mode); + return -EINVAL; + } + + if (ath12k_frame_mode == ATH12K_HW_TXRX_RAW) + set_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags); + + mutex_lock(&ag->mutex_lock); mutex_lock(&ab->core_lock); - ret = ath12k_core_start(ab, ATH12K_FIRMWARE_MODE_NORMAL); + + /* This should be the last function, add core related + * initializations within this function + */ + ret = ath12k_core_start(ab, ab->fw_mode); if (ret) { ath12k_err(ab, "failed to start core: %d\n", ret); goto err_dp_free; } - ret = ath12k_core_pdev_create(ab); + set_bit(ATH12K_FLAG_CORE_REGISTERED, &ab->dev_flags); + mutex_unlock(&ab->core_lock); + + if (ath12k_core_hw_group_start_ready(ag)) { + + /* initialize the mgmt rx re-order after + * mlo mem is available + */ + ath12k_mgmt_rx_reo_init_context(ab); + ath12k_qmi_mlo_global_snapshot_mem_init(ab); + + ret = ath12k_core_hw_group_start(ag); if (ret) { - ath12k_err(ab, "failed to create pdev core: %d\n", ret); + ath12k_warn(ab, "unable to start hw group\n"); goto err_core_stop; } - ath12k_hif_irq_enable(ab); - mutex_unlock(&ab->core_lock); + ath12k_dbg(ab, ATH12K_DBG_BOOT, "group %d started\n", ag->id); + } else { + ath12k_core_trigger_partner(ab); + } + + mutex_unlock(&ag->mutex_lock); + + /* Add code here carefully */ return 0; err_core_stop: + mutex_lock(&ab->core_lock); ath12k_core_stop(ab); - ath12k_mac_destroy(ab); + clear_bit(ATH12K_FLAG_CORE_REGISTERED, &ab->dev_flags); err_dp_free: ath12k_dp_free(ab); mutex_unlock(&ab->core_lock); + mutex_unlock(&ag->mutex_lock); err_firmware_stop: ath12k_qmi_firmware_stop(ab); return ret; } +#define ATH12K_COLLECT_DUMP_TIMEOUT (120 * HZ) + +void ath12k_core_wait_dump_collect(struct ath12k_base *ab) +{ + int timeout; + + if (ab->collect_dump) { + timeout = wait_event_timeout(ab->ssr_dump_wq, + (ab->collect_dump == false), + ATH12K_COLLECT_DUMP_TIMEOUT); + if (timeout <= 0) + ath12k_warn(ab, "dump collection timed out\n"); + } + return; +} +EXPORT_SYMBOL(ath12k_core_wait_dump_collect); + +void ath12k_core_issue_bug_on(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + + if (ab->in_panic) + goto out; + + /* set in_panic to true to avoid multiple rddm download during + * firmware crash + */ + ab->in_panic = true; + + if (!ag->mlo_capable) + BUG_ON(1); + + if (atomic_read(&ath12k_coredump_ram_info.num_chip) >= ab->ag->num_started) + BUG_ON(1); + else + goto out; + +out: + ath12k_info(ab, + "%d chip dump collected and waiting for partner chips\n", + atomic_read(&ath12k_coredump_ram_info.num_chip)); + +} + +static void ath12k_coredump_download_ahb(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + int dump_count; + struct ath12k_ahb *ab_ahb = ath12k_ahb_priv(ab); + struct ath12k_base *partner_ab; + int i; + + /* Crash the system once all the stats are dumped */ + if (ab->fw_recovery_support && !ab->in_panic) + return; + + if (ag->mlo_capable ) { + dump_count = atomic_read(&ath12k_coredump_ram_info.num_chip); + if (dump_count >= ATH12K_MAX_SOCS) { + ath12k_err(ab, "invalid chip number %d\n", + dump_count); + return; + } + } + if (ab_ahb->tgt_rrproc->state == RPROC_CRASHED && ab->multi_pd_arch) { + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + if (partner_ab->multi_pd_arch) + atomic_inc(&ath12k_coredump_ram_info.num_chip); + } + } else { + atomic_inc(&ath12k_coredump_ram_info.num_chip); + } + + ath12k_core_issue_bug_on(ab); +} + +/* Print the driver stats and crash the system on receiving this notification */ +static int ath12k_core_ssr_notifier_cb(struct notifier_block *nb, + const unsigned long event, + void *data) +{ + struct ath12k_base *ab = container_of(nb, struct ath12k_base, ssr_nb); + + if (ab->collect_dump && event == ATH12K_SSR_POWERUP) { + ab->collect_dump = false; + wake_up(&ab->ssr_dump_wq); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static int ath12k_core_rpd_ssr_notifier_cb(struct notifier_block *nb, + const unsigned long event, + void *data) +{ + struct ath12k_base *ab = container_of(nb, struct ath12k_base, rpd_ssr_nb); + + if (ab->collect_dump && event == ATH12K_SSR_POWERUP) { + ab->collect_dump = false; + wake_up(&ab->ssr_dump_wq); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static int ath12k_core_check_ssr_notifier_as_expected(struct ath12k_base *ab, + void *data, + const char *node) +{ + phandle rproc_phandle; + struct device *dev = ab->dev; + struct platform_device *pdev; + struct device_node *rproc_node; + struct platform_device *ssr_pdev = data; + + if (of_property_read_u32(dev->of_node, node, &rproc_phandle)) + return -EINVAL; + + rproc_node = of_find_node_by_phandle(rproc_phandle); + if (!rproc_node) { + ath12k_warn(ab, "ssr notification failed to get rproc_node\n"); + return -EINVAL; + } + + pdev = of_find_device_by_node(rproc_node); + if (!pdev) { + ath12k_warn(ab, "Failed to get pdev from device node\n"); + return -EINVAL; + } + + if (!ab->in_panic && (strcmp(ssr_pdev->name, pdev->name) != 0)) { + ath12k_warn(ab, "SSR notification mismatch %s pdev name:%s\n", + ssr_pdev->name, pdev->name); + return -EINVAL; + } + + return 0; +} + +static int ath12k_core_atomic_ssr_notifier_cb(struct notifier_block *nb, + const unsigned long event, + void *data) +{ + struct ath12k_base *ab = container_of(nb, struct ath12k_base, atomic_ssr_nb); + struct ath12k_ahb *ab_ahb = ath12k_ahb_priv(ab); + struct platform_device *ssr_pdev = data; + int ret; + + if (event != ATH12K_SSR_PREPARE_SHUTDOWN) + return NOTIFY_DONE; + + if (!test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags)) + return NOTIFY_DONE; + + ab->collect_dump = true; + + ret = ath12k_core_check_ssr_notifier_as_expected(ab, data, "qcom,rproc"); + if (ret) + return NOTIFY_DONE; + + if (strcmp(ssr_pdev->name, ab_ahb->tgt_rproc->name) == 0) { + ab->ag->crash_type = ATH12K_RPROC_USERPD_HYBRID_CRASH; + ab_ahb->tgt_rproc->state = RPROC_CRASHED; + } + + if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->ag->dev_flags))) { + set_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags); + set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); + queue_work(ab->workqueue_aux, &ab->reset_work); + } + + ath12k_hal_dump_srng_stats(ab); + + return NOTIFY_OK; +} + +/* Print the driver stats and crash the system on receiving this notification */ +static int ath12k_core_rpd_atomic_ssr_notifier_cb(struct notifier_block *nb, + const unsigned long event, + void *data) +{ + struct ath12k_base *ab = container_of(nb, struct ath12k_base, rpd_atomic_ssr_nb); + struct ath12k_hw_group *ag = ab->ag; + struct platform_device *ssr_pdev = data; + struct ath12k_ahb *ab_ahb = ath12k_ahb_priv(ab); + int ret; + + if (event != ATH12K_SSR_PREPARE_SHUTDOWN) + return NOTIFY_DONE; + + if (!test_bit(ATH12K_FLAG_REGISTERED, &ag->dev_flags)) + return NOTIFY_DONE; + + ab->collect_dump = true; + + ret = ath12k_core_check_ssr_notifier_as_expected(ab, data, "qcom,rproc_rpd"); + if (ret) + return NOTIFY_DONE; + + /* Changing the rrpoc->state to crashed disabled the + * remoteproc module to do the recovery process. + * This module will take care of the rrproc recovery process. + */ + if (strcmp(ssr_pdev->name, ab_ahb->tgt_rrproc->name) == 0) { + ag->crash_type = ATH12K_RPROC_ROOTPD_HYBRID_CRASH; + ab_ahb->tgt_rrproc->state = RPROC_CRASHED; + } + + if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ag->dev_flags))) { + set_bit(ATH12K_FLAG_RECOVERY, &ag->dev_flags); + set_bit(ATH12K_FLAG_CRASH_FLUSH, &ag->dev_flags); + queue_work(ab->workqueue_aux, &ag->reset_work); + } + + /* TODO Add more driver stats */ + + return NOTIFY_OK; +} + static int ath12k_core_reconfigure_on_crash(struct ath12k_base *ab) { int ret; mutex_lock(&ab->core_lock); - ath12k_hif_irq_disable(ab); + ath12k_core_pdev_deinit(ab); ath12k_dp_pdev_free(ab); ath12k_hif_stop(ab); ath12k_wmi_detach(ab); @@ -633,21 +2068,20 @@ ath12k_dp_free(ab); ath12k_hal_srng_deinit(ab); + ath12k_dp_umac_reset_deinit(ab); + ath12k_umac_reset_completion(ab); ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS)) - 1; + ab->num_db_cap = 0; ret = ath12k_hal_srng_init(ab); if (ret) return ret; - clear_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); - ret = ath12k_core_qmi_firmware_ready(ab); if (ret) goto err_hal_srng_deinit; - clear_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags); - return 0; err_hal_srng_deinit: @@ -655,61 +2089,99 @@ return ret; } -void ath12k_core_halt(struct ath12k *ar) +static void ath12k_core_mlo_hw_queues_stop(struct ath12k_hw_group *ag, + struct ath12k_base *block_ab) { - struct ath12k_base *ab = ar->ab; + struct ath12k_base *ab; + struct ath12k_hw *ah; + int i; - lockdep_assert_held(&ar->conf_mutex); + lockdep_assert_held(&ag->mutex_lock); - ar->num_created_vdevs = 0; - ar->allocated_vdev_map = 0; + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; - ath12k_mac_scan_finish(ar); - ath12k_mac_peer_cleanup_all(ar); - cancel_delayed_work_sync(&ar->scan.timeout); - cancel_work_sync(&ar->regd_update_work); + ieee80211_stop_queues(ah->hw); + } + ag->hw_queues_stopped = true; - rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); - synchronize_rcu(); - INIT_LIST_HEAD(&ar->arvifs); - idr_init(&ar->txmgmt_idr); + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1) { + block_ab->qmi.num_radios = ATH12K_QMI_INVALID_RADIO; + clear_bit(ATH12K_FLAG_QMI_HOST_CAP_SENT, &block_ab->dev_flags); + return; + } + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + /* + * In Mode0, partner chips are expected to be asserted, hence reset + * qmi.num_radios count to ensure avoiding duplicate host cap triggers. + */ + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0) { + ab->qmi.num_radios = ATH12K_QMI_INVALID_RADIO; + clear_bit(ATH12K_FLAG_QMI_HOST_CAP_SENT, &ab->dev_flags); + } + } } static void ath12k_core_pre_reconfigure_recovery(struct ath12k_base *ab) { struct ath12k *ar; struct ath12k_pdev *pdev; + struct ath12k_link_vif *arvif; + struct ath12k_mac_tx_mgmt_free_arg arg; int i; spin_lock_bh(&ab->base_lock); ab->stats.fw_crash_counter++; spin_unlock_bh(&ab->base_lock); + if (ab->is_reset) + set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); + for (i = 0; i < ab->num_radios; i++) { pdev = &ab->pdevs[i]; ar = pdev->ar; if (!ar || ar->state == ATH12K_STATE_OFF) continue; - ieee80211_stop_queues(ar->hw); - ath12k_mac_drain_tx(ar); + list_for_each_entry(arvif, &ar->arvifs, list) + if (arvif->is_started) + ath12k_debugfs_remove_interface(arvif); + + ath12k_mac_radio_drain_tx(ar); complete(&ar->scan.started); complete(&ar->scan.completed); + complete(&ar->scan.on_channel); complete(&ar->peer_assoc_done); complete(&ar->peer_delete_done); + if (!list_empty(&ab->neighbor_peers)) + ath12k_debugfs_nrp_cleanup_all(ar); complete(&ar->install_key_done); complete(&ar->vdev_setup_done); complete(&ar->vdev_delete_done); complete(&ar->bss_survey_done); + complete(&ar->thermal.wmi_sync); - wake_up(&ar->dp.tx_empty_waitq); + memset(&arg, 0, sizeof(arg)); + arg.ar = ar; + arg.type = u8_encode_bits(true, ATH12K_MAC_TX_MGMT_FREE_TYPE_PDEV); idr_for_each(&ar->txmgmt_idr, - ath12k_mac_tx_mgmt_pending_free, ar); + ath12k_mac_tx_mgmt_pending_free, &arg); idr_destroy(&ar->txmgmt_idr); + wake_up(&ar->tx_empty_waitq); + + ar->monitor_vdev_id = -1; + clear_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags); + clear_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags); } wake_up(&ab->wmi_ab.tx_credits_wq); wake_up(&ab->peer_mapping_wq); + } static void ath12k_core_post_reconfigure_recovery(struct ath12k_base *ab) @@ -721,7 +2193,8 @@ for (i = 0; i < ab->num_radios; i++) { pdev = &ab->pdevs[i]; ar = pdev->ar; - if (!ar || ar->state == ATH12K_STATE_OFF) + if (!ar || ar->state == ATH12K_STATE_OFF || + ar->state == ATH12K_STATE_TM) continue; mutex_lock(&ar->conf_mutex); @@ -729,8 +2202,15 @@ switch (ar->state) { case ATH12K_STATE_ON: ar->state = ATH12K_STATE_RESTARTING; + if (ar->scan.state == ATH12K_SCAN_RUNNING || + ar->scan.state == ATH12K_SCAN_STARTING) + ar->scan.state = ATH12K_SCAN_ABORTING; + ath12k_mac_scan_finish(ar); + mutex_unlock(&ar->conf_mutex); + cancel_delayed_work_sync(&ar->scan.timeout); + cancel_work_sync(&ar->scan.vdev_del_wk); + mutex_lock(&ar->conf_mutex); ath12k_core_halt(ar); - ieee80211_restart_hw(ar->hw); break; case ATH12K_STATE_OFF: ath12k_warn(ab, @@ -738,6 +2218,7 @@ i); break; case ATH12K_STATE_RESTARTING: + ar->state = ATH12K_STATE_RESTARTED; break; case ATH12K_STATE_RESTARTED: ar->state = ATH12K_STATE_WEDGED; @@ -746,16 +2227,901 @@ ath12k_warn(ab, "device is wedged, will not restart radio %d\n", i); break; + case ATH12K_STATE_TM: + ath12k_warn(ab, "fw mode reset done radio %d\n", i); + break; } mutex_unlock(&ar->conf_mutex); } - complete(&ab->driver_recovery); +} + +void ath12k_core_halt(struct ath12k *ar) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_hw_group *ag = ab->ag; + + lockdep_assert_held(&ar->conf_mutex); + + ar->num_created_vdevs = 0; + ar->allocated_vdev_map = 0; + + ath12k_mac_peer_cleanup_all(ar); + cancel_work_sync(&ar->regd_update_work); + rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); + + if(!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->ag->dev_flags))) + synchronize_rcu(); + + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0) + INIT_LIST_HEAD(&ar->arvifs); + + idr_init(&ar->txmgmt_idr); +} + +static void ath12k_core_mode1_recovery_sta_list(void *data, + struct ieee80211_sta *sta) +{ + struct ath12k_link_sta *arsta; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_vif *arvif = (struct ath12k_link_vif *)data; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + struct ath12k *ar = arvif->ar; + struct ath12k_base *ab = arvif->ab; + struct ath12k_key_conf *key_conf = NULL; + struct ath12k_peer *peer; + struct ieee80211_key_conf *key; + int ret = -1, key_idx; + u8 link_id = arvif->link_id; + enum ieee80211_sta_state state, prev_state; + bool sta_added = false; + + if (ahsta->ahvif != arvif->ahvif) + return; + + /* Check if there is a link sta in the vif link */ + if (!(BIT(link_id) & ahsta->links_map)) + return; + + /* From iterator, rcu_read_lock is acquired. Will be revisited + * later to use local list + */ + arsta = ahsta->link[link_id]; + + key_conf = container_of((void *)sta, struct ath12k_key_conf, sta); + + if (vif->type != NL80211_IFTYPE_AP && + vif->type != NL80211_IFTYPE_AP_VLAN && + vif->type != NL80211_IFTYPE_STATION && + vif->type != NL80211_IFTYPE_MESH_POINT) + return; + + peer = ath12k_peer_find(ar->ab, arvif->vdev_id, arsta->addr); + if (peer) { + sta_added = true; + goto key_add; + } + + prev_state = arsta->state; + for (state = IEEE80211_STA_NOTEXIST; + state < prev_state; state++) { + /* all station set case */ + /* TODO: Iterator API is called with rcu lock + * hence need for this unlock/lock statement. + * Need to revisit in next version + */ + rcu_read_unlock(); + ath12k_mac_update_sta_state(ar->ah->hw, arvif->ahvif->vif, sta, + state, (state + 1)); + rcu_read_lock(); + sta_added = true; + } + +key_add: + if (sta_added) + for (key_idx = 0; key_idx < WMI_MAX_KEY_INDEX; key_idx++) { + key = arsta->keys[key_idx]; + + if (key) { + /* BIP needs to be done in software */ + if (key->cipher == WLAN_CIPHER_SUITE_AES_CMAC || + key->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_128 || + key->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_256 || + key->cipher == WLAN_CIPHER_SUITE_BIP_CMAC_256) { + ret = 1; + goto out; + } + + if (test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->ag->dev_flags)) { + ret = 1; + goto out; + } + + if (!arvif->is_created) { + key_conf = kzalloc(sizeof(*key_conf), GFP_ATOMIC); + + if (!key_conf) { + goto out; + } + + key_conf->cmd = SET_KEY; + key_conf->sta = sta; + key_conf->key = key; + + list_add_tail(&key_conf->list, + &ahvif->cache[link_id].key_conf.list); + + ath12k_info(ab, "set key param cached since vif not assign to radio\n"); + goto out; + } + + if (sta->mlo) { + unsigned long links = sta->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + if (WARN_ON(!arvif || !arsta)) + continue; + + /* TODO: Iterator API is called with rcu lock + * hence need for this unlock/lock statement. + * Need to revisit in next version + */ + rcu_read_unlock(); + ret = ath12k_mac_set_key(arvif->ar, SET_KEY, arvif, arsta, key); + rcu_read_lock(); + if (ret) + break; + arsta->keys[key->keyidx] = key; + } + } else { + arsta = &ahsta->deflink; + arvif = arsta->arvif; + if (WARN_ON(!arvif)) + goto out; + + /* TODO: Iterator API is called with rcu lock + * hence need for this unlock/lock statement. + * Need to revisit in next version + */ + rcu_read_unlock(); + ret = ath12k_mac_set_key(arvif->ar, SET_KEY, arvif, arsta, key); + rcu_read_lock(); + arsta->keys[key->keyidx] = key; + } + } + } + + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "Recovered sta:%pM link_id:%d, num_sta:%d\n", + arsta->addr, arsta->link_id, arvif->ar->num_stations); + + ret = 0; +out: + return; +} + +static void ath12k_core_iterate_sta_list(struct ath12k *ar, + struct ath12k_link_vif *arvif) +{ + /* unlock ar mutex here as the iterator will be called + * within rcu lock. + */ + mutex_unlock(&ar->conf_mutex); + ieee80211_iterate_stations_atomic(ar->ah->hw, + ath12k_core_mode1_recovery_sta_list, + arvif); + mutex_lock(&ar->conf_mutex); +} + +static void ath12k_core_ml_sta_add(struct ath12k *ar) +{ + struct ath12k_link_vif *arvif, *tmp; + struct ieee80211_bss_conf *info; + struct ath12k_vif *ahvif; + struct ieee80211_vif *vif; + + mutex_lock(&ar->conf_mutex); + list_for_each_entry_safe_reverse(arvif, tmp, &ar->arvifs, list) { + ahvif = arvif->ahvif; + + if (!ahvif) + continue; + + vif = ahvif->vif; + if (ahvif->vdev_type != WMI_VDEV_TYPE_STA) + continue; + + if (!vif->valid_links) + continue; + + ath12k_core_iterate_sta_list(ar, arvif); + + info = vif->link_conf[arvif->link_id]; + /* Set is_up to false as we will do + * recovery for that vif in the + * upcoming executions + */ + arvif->is_up = false; + if (vif->cfg.assoc && info) + ath12k_bss_assoc(ar, arvif, info); + else + ath12k_bss_disassoc(ar, arvif, false); + ath12k_dbg(ar->ab, ATH12K_DBG_MODE1_RECOVERY, + "station vif:%pM recovered\n", + arvif->addr); + } + mutex_unlock(&ar->conf_mutex); +} + +/* API to recovery station VIF enabled in non-asserted links */ +static void ath12k_core_mlo_recover_station(struct ath12k_hw_group *ag, + struct ath12k_base *assert_ab) +{ + struct ath12k_base *ab; + struct ath12k_pdev *pdev; + struct ath12k *ar; + int i, j; + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + if (ab == assert_ab) + continue; + + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + + if (list_empty(&ar->arvifs)) + continue; + + /* Re-add all MLD station VIF which are + * in non-asserted link + */ + ath12k_core_ml_sta_add(ar); + } + } +} + +static int ath12k_mlo_recovery_link_vif_reconfig(struct ath12k *ar, + struct ath12k_vif *ahvif, + struct ath12k_link_vif *arvif, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *link_conf) +{ + int i; + int link_id = arvif->link_id; + struct ath12k_hw *ah = ar->ah; + struct ieee80211_tx_queue_params params; + struct wmi_wmm_params_arg *p = NULL; + struct ieee80211_bss_conf *info; + u64 changed = 0; + + switch (vif->type) { + case NL80211_IFTYPE_AP_VLAN: + case NL80211_IFTYPE_MONITOR: + break; + case NL80211_IFTYPE_ADHOC: + fallthrough; + default: + ieee80211_iterate_stations_atomic(ar->ah->hw, + ath12k_core_mode1_recovery_sta_list, + arvif); + fallthrough; + case NL80211_IFTYPE_AP: /* AP stations are handled later */ + for (i = 0; i < IEEE80211_NUM_ACS; i++) { + + if ((vif->active_links && + !(vif->active_links & BIT(link_id))) || + link_id >= IEEE80211_MLD_MAX_NUM_LINKS) + break; + + switch (i) { + case IEEE80211_AC_VO: + p = &arvif->wmm_params.ac_vo; + break; + case IEEE80211_AC_VI: + p = &arvif->wmm_params.ac_vi; + break; + case IEEE80211_AC_BE: + p = &arvif->wmm_params.ac_be; + break; + case IEEE80211_AC_BK: + p = &arvif->wmm_params.ac_bk; + break; + } + + params.cw_min = p->cwmin; + params.cw_max = p->cwmax; + params.aifs = p->aifs; + params.txop = p->txop; + + mutex_lock(&ar->conf_mutex); + ath12k_mac_conf_tx(ar, arvif, i, ¶ms); + mutex_unlock(&ar->conf_mutex); + } + break; + } + + mutex_lock(&ah->conf_mutex); + + /* common change flags for all interface types */ + changed = BSS_CHANGED_ERP_CTS_PROT | + BSS_CHANGED_ERP_PREAMBLE | + BSS_CHANGED_ERP_SLOT | + BSS_CHANGED_HT | + BSS_CHANGED_BASIC_RATES | + BSS_CHANGED_BEACON_INT | + BSS_CHANGED_BSSID | + BSS_CHANGED_CQM | + BSS_CHANGED_QOS | + BSS_CHANGED_TXPOWER | + BSS_CHANGED_MCAST_RATE; + + if (link_conf->mu_mimo_owner) + changed |= BSS_CHANGED_MU_GROUPS; + + switch (vif->type) { +#ifdef CONFIG_MAC80211_BONDED_SUPPORT + case NL80211_IFTYPE_DUMMY: + mutex_unlock(&ah->conf_mutex); + return 0; +#endif + case NL80211_IFTYPE_STATION: + if (!vif->valid_links) { + /* Set this only for legacy stations */ + changed |= BSS_CHANGED_ASSOC | + BSS_CHANGED_ARP_FILTER | + BSS_CHANGED_PS; + + /* Assume re-send beacon info report to the driver */ + changed |= BSS_CHANGED_BEACON_INFO; + + if (link_conf->max_idle_period || + link_conf->protected_keep_alive) + changed |= BSS_CHANGED_KEEP_ALIVE; + + if (!arvif->is_created) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "bss info parameter changes %llx cached to apply after vdev create on channel assign\n", + changed); + ahvif->cache[link_id].bss_conf_changed |= changed; + + mutex_unlock(&ah->conf_mutex); + return 0; + } + } + + mutex_lock(&ar->conf_mutex); + /* Set is_up to false as we will do + * recovery for that vif in the + * upcoming executions + */ + arvif->is_up = false; + ath12k_mac_bss_info_changed(ar, arvif, link_conf, changed); + if (vif->valid_links) { + info = vif->link_conf[link_id]; + if (vif->cfg.assoc) { + if (info) + ath12k_bss_assoc(ar, arvif, info); + } else { + ath12k_bss_disassoc(ar, arvif, false); + } + } + mutex_unlock(&ar->conf_mutex); + break; + case NL80211_IFTYPE_OCB: + changed |= BSS_CHANGED_OCB; + + mutex_lock(&ar->conf_mutex); + ath12k_mac_bss_info_changed(ar, arvif, link_conf, changed); + mutex_unlock(&ar->conf_mutex); + break; + case NL80211_IFTYPE_ADHOC: + changed |= BSS_CHANGED_IBSS; + fallthrough; + case NL80211_IFTYPE_AP: + changed |= BSS_CHANGED_P2P_PS; + + if (vif->type == NL80211_IFTYPE_AP) { + changed |= BSS_CHANGED_AP_PROBE_RESP; + ahvif->u.ap.ssid_len = vif->cfg.ssid_len; + if (vif->cfg.ssid_len) + memcpy(ahvif->u.ap.ssid, vif->cfg.ssid, vif->cfg.ssid_len); + } + fallthrough; + case NL80211_IFTYPE_MESH_POINT: + if (link_conf->enable_beacon) { + changed |= BSS_CHANGED_BEACON | + BSS_CHANGED_BEACON_ENABLED; + + mutex_lock(&ar->conf_mutex); + ath12k_mac_bss_info_changed(ar, arvif, link_conf, + changed & ~BSS_CHANGED_IDLE); + mutex_unlock(&ar->conf_mutex); + + } + break; + case NL80211_IFTYPE_NAN: + case NL80211_IFTYPE_AP_VLAN: + case NL80211_IFTYPE_MONITOR: + case NL80211_IFTYPE_P2P_DEVICE: + /* nothing to do */ + break; + case NL80211_IFTYPE_UNSPECIFIED: + case NUM_NL80211_IFTYPES: + case NL80211_IFTYPE_P2P_CLIENT: + case NL80211_IFTYPE_P2P_GO: + case NL80211_IFTYPE_WDS: + WARN_ON(1); + break; + } + + mutex_unlock(&ah->conf_mutex); + ath12k_dbg(ar->ab, ATH12K_DBG_MODE1_RECOVERY, + "Reconfig link vif done:type:%d\n", vif->type); + + return 0; +} + +static int ath12k_mlo_core_recovery_reconfig_link_bss(struct ath12k *ar, + struct ieee80211_bss_conf *link_conf, + struct ath12k_vif *ahvif, + struct ath12k_link_vif *arvif) +{ + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ath12k_base *ab = ar->ab; + struct ath12k_hw *ah = ar->ah; + enum ieee80211_ap_reg_power power_type; + struct ath12k_wmi_peer_create_arg param; + struct ieee80211_chanctx_conf *ctx = &arvif->chanctx; + int ret = -1; + u8 link_id = link_conf->link_id; + + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "Recovering: link_id:%d [vif->link_id:%d] type:%d\n", + link_id, arvif->link_id, vif->type); + + mutex_lock(&ah->conf_mutex); + + if (vif->type == NL80211_IFTYPE_AP && + ar->num_peers > (ar->max_num_peers - 1)) { + ath12k_err(ab, "Error in peers:%d\n", + ar->num_peers); + goto exit; + } + + if (ar->num_created_vdevs > (TARGET_NUM_VDEVS - 1)) { + ath12k_err(ab, "failed to create vdev, reached max vdev limit %d[%d]\n", + ar->num_created_vdevs, + TARGET_NUM_VDEVS); + goto exit; + } + + mutex_lock(&ar->conf_mutex); + + ret = ath12k_mac_vdev_create(ar, arvif); + if (!ret) + ath12k_mac_vif_cache_flush(ar, vif, arvif->link_id); + + if (ar->supports_6ghz && ctx->def.chan->band == NL80211_BAND_6GHZ && + (ahvif->vdev_type == WMI_VDEV_TYPE_STA || + ahvif->vdev_type == WMI_VDEV_TYPE_AP)) { + power_type = link_conf->power_type; + ath12k_dbg(ab, ATH12K_DBG_MAC, "mac chanctx power type %d\n", + power_type); + if (power_type == IEEE80211_REG_UNSET_AP) + power_type = IEEE80211_REG_LPI_AP; + + /* TODO: Transmit Power Envelope specification for 320 is not + * available yet. Need to add TPE 320 support when spec is ready + */ + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA && + ctx->def.width != NL80211_CHAN_WIDTH_320) { + ath12k_mac_parse_tx_pwr_env(ar, arvif, ctx); + } + } + + /* for some targets bss peer must be created before vdev_start */ + if (ab->hw_params->vdev_start_delay && + ahvif->vdev_type != WMI_VDEV_TYPE_AP && + ahvif->vdev_type != WMI_VDEV_TYPE_MONITOR && + !ath12k_peer_find_by_vdev_id(ab, arvif->vdev_id)) { + ret = 0; + goto exit; + } + + if (ab->hw_params->vdev_start_delay && + (ahvif->vdev_type == WMI_VDEV_TYPE_AP || + ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR)) { + param.vdev_id = arvif->vdev_id; + param.peer_type = WMI_PEER_TYPE_DEFAULT; + param.peer_addr = ar->mac_addr; + + ret = ath12k_peer_create(ar, arvif, NULL, ¶m); + if (ret) { + ath12k_warn(ab, "failed to create peer after vdev start delay: %d", + ret); + goto exit; + } + } + + if (ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { + ret = ath12k_mac_monitor_start(ar); + if (ret) + goto exit; + arvif->is_started = true; + goto exit; + } + + ret = ath12k_mac_vdev_start(arvif, &ctx->def, ctx->radar_enabled); + if (ret) { + ath12k_err(ab, "vdev start failed during recovery\n"); + goto exit; + } + + if (ahvif->vdev_type != WMI_VDEV_TYPE_MONITOR && + test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags)) + ath12k_mac_monitor_start(ar); + + arvif->is_started = true; + arvif->is_created = true; + + ret = 0; +exit: + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "ret:%d No. of vdev created:%d, links_map:%lu, flag:%d\n", + ret, + ahvif->num_vdev_created, + ahvif->links_map, + arvif->is_created); + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + + return ret; +} + +static void ath12k_core_peer_disassoc(struct ath12k_hw_group *ag, + struct ath12k_base *assert_ab) +{ + struct ath12k_base *ab; + struct ath12k_peer *peer, *tmp; + struct ath12k_sta *ahsta; + struct ieee80211_sta *sta; + int i; + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + list_for_each_entry_safe(peer, tmp, &ab->peers, list) { + if (!peer->sta || !peer->vif) + continue; + + /* Allow sending disassoc to legacy peer + * only for asserted radio + */ + if (!peer->mlo && ab != assert_ab) + continue; + + sta = peer->sta; + ahsta = (struct ath12k_sta *)sta->drv_priv; + + /* Send low ack to disassoc the MLD station + * Need to check on the sequence as FW has + * discarded the management packet at this + * sequence. + */ + if (!ahsta->low_ack_sent) { + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "sending low ack for/disassoc:%pM\n", + sta->addr); + /* set num of packets to maximum so + * that we distinguish in the hostapd + * to send disassoc irrespective of + * hostapd conf + */ + ieee80211_report_low_ack(sta, 0xFFFF); + /* Using this flag to avoid certain + * known warnings which will be + * triggerred when umac reset is + * happening + */ + ahsta->low_ack_sent = true; + } + } + } +} + +/* Wrapper function for recovery after crash */ +int ath12k_mode1_recovery_reconfig(struct ath12k_base *ab) +{ + struct ath12k *ar = NULL; + struct ath12k_pdev *pdev; + struct ath12k_link_vif *arvif, *tmp; + struct ath12k_vif *ahvif ; + struct ieee80211_bss_conf *link; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_base *partner_ab; + struct ath12k_hw *ah; + struct ieee80211_key_conf *key; + int i, j, key_idx; + int ret = -EINVAL; + bool started = false; + + + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + ar = pdev->ar; + if (WARN_ON(!ar)) + continue; + + if (!ath12k_ftm_mode) { + if (ath12k_mac_radio_start(ar)) { + ath12k_err(ab, "mac radio start failed\n"); + return ret; + } + ar->ah->in_recovery = true; + started = true; + } + + if (list_empty(&ar->arvifs)) + continue; + + /* Decrement number of vdev created for all the arvif + * under a ar + */ + list_for_each_entry_safe_reverse(arvif, tmp, &ar->arvifs, list) { + arvif->ahvif->num_vdev_created--; + } + } + + /* add chanctx/hw_config/filter part */ + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + + mutex_lock(&ar->conf_mutex); + + list_for_each_entry_safe_reverse(arvif, tmp, &ar->arvifs, list) { + ahvif = arvif->ahvif; + + if (!ahvif) + continue; + + arvif->is_started = false; + arvif->is_created = false; + + rcu_read_lock(); + link = rcu_dereference(ahvif->vif->link_conf[arvif->link_id]); + + /* Not expected */ + if (WARN_ON(!link)) { + rcu_read_unlock(); + continue; + } + rcu_read_unlock(); + spin_lock_bh(&ar->data_lock); + + ar->rx_channel = link->chandef.chan; + spin_unlock_bh(&ar->data_lock); + + /* hw_config */ + if (ar->ah->hw->conf.flags & IEEE80211_CONF_MONITOR) { + set_bit(MONITOR_CONF_ENABLED, &ar->monitor_flags); + + if (test_bit(MONITOR_VDEV_CREATED, + &ar->monitor_flags)) { + ret = ath12k_mac_monitor_vdev_create(ar); + if (!ret && ath12k_mac_monitor_start(ar)) { + ath12k_err(ab, "unable to start monitor vdev\n"); + ath12k_mac_monitor_vdev_delete(ar); + } else { + ath12k_err(ab, "unable to create monitor vdev\n"); + } + } + } else { + clear_bit(MONITOR_CONF_ENABLED, &ar->monitor_flags); + if (test_bit(MONITOR_VDEV_CREATED, + &ar->monitor_flags)) { + ret = ath12k_mac_monitor_stop(ar); + if (!ret && ath12k_mac_monitor_vdev_delete(ar)) + ath12k_err(ab, "monitor vdev delete failed\n"); + else + ath12k_err(ab, "failed to stop monitor stop\n"); + } + } + + + /* configure filter - we can use the same flag*/ + } + mutex_unlock(&ar->conf_mutex); + } + + /* assign chanctx part */ + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + + mutex_lock(&ar->conf_mutex); + + list_for_each_entry_safe_reverse(arvif, tmp, &ar->arvifs, list) { + ahvif = arvif->ahvif; + + if (!ahvif) + continue; + + rcu_read_lock(); + link = rcu_dereference(ahvif->vif->link_conf[arvif->link_id]); + + /* Not expected */ + if (WARN_ON(!link)) { + rcu_read_unlock(); + continue; + } + rcu_read_unlock(); + + /* unlock ar mutex here since we will take ah mutex in + * the reconfig link API thus maintaining same order + * as we use in other places. + */ + mutex_unlock(&ar->conf_mutex); + ret = ath12k_mlo_core_recovery_reconfig_link_bss(ar, link, ahvif, arvif); + if (ret) { + ath12k_err(ab, "ERROR in reconfig link:%d\n", + ret); + return ret; + } + mutex_lock(&ar->conf_mutex); + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "vdev_created getting incremented:%d\n", + ahvif->num_vdev_created); + } + mutex_unlock(&ar->conf_mutex); + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, "assign chanctx is completed\n"); + } + + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + + clear_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &partner_ab->dev_flags); + } + + /* reconfig_link_bss */ + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + + mutex_lock(&ar->conf_mutex); + + list_for_each_entry_safe_reverse(arvif, tmp, &ar->arvifs, list) { + ahvif = arvif->ahvif; + + if (!ahvif) + continue; + + rcu_read_lock(); + link = rcu_dereference(ahvif->vif->link_conf[arvif->link_id]); + + /* Not expected */ + if (WARN_ON(!link)) { + rcu_read_unlock(); + } + rcu_read_unlock(); + + /* unlock ar mutex here since we will take ah mutex in + * the reconfig link API thus maintaining same order + * as we use in other places. + */ + mutex_unlock(&ar->conf_mutex); + ret = ath12k_mlo_recovery_link_vif_reconfig(ar, ahvif, + arvif, + arvif->ahvif->vif, + link); + if (ret) { + ath12k_err(ab, "Failed to update reconfig_bss\n"); + return ret; + } + mutex_lock(&ar->conf_mutex); + } + mutex_unlock(&ar->conf_mutex); + } + + /* recover station VIF enabled in non-asserted links */ + ath12k_core_mlo_recover_station(ag, ab); + + /* sta state part */ + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + + for (j = 0; j < partner_ab->num_radios; j++) { + pdev = &partner_ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + + mutex_lock(&ar->conf_mutex); + + if (list_empty(&ar->arvifs)) { + mutex_unlock(&ar->conf_mutex); + continue; + } + list_for_each_entry_safe_reverse(arvif, tmp, &ar->arvifs, list) { + ahvif = arvif->ahvif; + + if (!ahvif) + continue; + + /* unlock ar mutex here as the iterator will be called + * within rcu lock. + */ + if (ahvif->vdev_type != WMI_VDEV_TYPE_STA) { + ath12k_core_iterate_sta_list(ar, arvif); + } + + for (key_idx = 0; key_idx < WMI_MAX_KEY_INDEX; key_idx++) { + key = arvif->keys[key_idx]; + if (key) { + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "key:%p cipher:%d idx:%d flags:%d\n", + key, key->cipher, key->keyidx, key->flags); + ret = ath12k_mac_set_key(arvif->ar, SET_KEY, arvif, NULL, key); + } + } + } + mutex_unlock(&ar->conf_mutex); + ar->ah->in_recovery = false; + } + } + + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; + + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + + ath12k_mac_reconfig_complete(ah->hw, + IEEE80211_RECONFIG_TYPE_RESTART, + ar); + } + } + + /* Send disassoc to MLD STA */ + ath12k_core_peer_disassoc(ag, ab); + ab->recovery_start = false; + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE0; + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, "Mode1 recovery completed\n"); + return ret; } static void ath12k_core_restart(struct work_struct *work) { struct ath12k_base *ab = container_of(work, struct ath12k_base, restart_work); + struct ath12k_hw_group *ag = ab->ag; int ret; + struct ath12k_hw *ah; + struct ath12k *ar; + int i; if (!ab->is_reset) ath12k_core_pre_reconfigure_recovery(ab); @@ -763,38 +3129,402 @@ ret = ath12k_core_reconfigure_on_crash(ab); if (ret) { ath12k_err(ab, "failed to reconfigure driver on crash recovery\n"); + /* + * If for any reason, reconfiguration fails, issue bug on for + * Mode 0 + */ + if (ath12k_ssr_failsafe_mode && ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0) + BUG_ON(1); return; } - if (ab->is_reset) - complete_all(&ab->reconfigure_complete); + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "ab->is_reset[%d]\n", ab->is_reset); + ar = ab->pdevs[0].ar; if (!ab->is_reset) ath12k_core_post_reconfigure_recovery(ab); + + if (ath12k_core_hw_group_start_ready(ag) && + ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0) { + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; + + mutex_lock(&ah->conf_mutex); + ieee80211_restart_hw(ah->hw); + mutex_unlock(&ah->conf_mutex); + } + } +#ifdef CONFIG_ATH12K_SAWF + if (ath12k_sawf_reconfigure_on_crash(ab)) + ath12k_warn(ab, "SAWF SLA reconfiguring failed\n"); +#endif /* CONFIG_ATH12K_SAWF */ + + if (ath12k_core_hw_group_start_ready(ag) && + ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1) { + queue_work(ab->workqueue_aux, &ab->recovery_work); + } +} + +static void ath12k_core_mode1_recovery_work(struct work_struct *work) +{ + struct ath12k_base *ab = container_of(work, struct ath12k_base, recovery_work); + + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "queued recovery work\n"); + ath12k_mode1_recovery_reconfig(ab); +} + +static int ath12k_core_rproc_stop(struct rproc *rproc) +{ + int ret = 0; + + if (!rproc) + return ret; + + if (rproc->state != RPROC_OFFLINE) { + ret = rproc_shutdown(rproc); + if (ret < 0) { + ath12k_err(NULL, "rproc:%s stop failed:%d\n", + rproc->name, ret); + } + } + return ret; } +static int ath12k_core_rproc_start(struct rproc *rproc) +{ + const struct firmware *firmware_p = NULL; + struct device *dev; + int ret = 0; + + if (rproc && rproc->state != RPROC_RUNNING) { + dev = &rproc->dev; + ret = request_firmware(&firmware_p, rproc->firmware, dev); + if (ret < 0) { + ath12k_err(NULL, "rproc:%s request_firmware failed: %d\n", + rproc->name, ret); + return ret; + } + ret = rproc_boot(rproc); + if (ret < 0) { + ath12k_err(NULL, "rproc:%s start failed: %d\n", + rproc->name, ret); + } + release_firmware(firmware_p); + } + return ret; +} + +static void ath12k_core_rproc_coredump(struct ath12k_base *ab, + struct rproc *rproc) +{ + if (rproc) { + ath12k_info(ab, "WLAN target is restarting"); + rproc->ops->coredump(rproc); + } +} + +/* Asserted target's reboot handling for crash type ATH12K_RPROC_ROOTPD_AHB_CRASH */ +static void ath12k_core_rproc_boot_recovery(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_ahb *ab_ahb = ath12k_ahb_priv(ab); + + if (ag->crash_type != ATH12K_RPROC_ROOTPD_AHB_CRASH) + return; + + /* + * Stop user pd + * Collect coredump using user pd if enabled + * Stop root pd + * Collect coredump using root pd + * Free Target memory chunk + * Start root pd, then start user pd + */ + + ab_ahb->tgt_rproc->state = RPROC_CRASHED; + ath12k_core_rproc_stop(ab_ahb->tgt_rproc); + + ab_ahb->tgt_rproc->state = RPROC_SUSPENDED; + ath12k_core_rproc_coredump(ab, ab_ahb->tgt_rproc); + + ab_ahb->tgt_rrproc->state = RPROC_RUNNING; + ath12k_core_rproc_stop(ab_ahb->tgt_rrproc); + ath12k_core_rproc_coredump(ab, ab_ahb->tgt_rrproc); + + ath12k_qmi_free_target_mem_chunk(ab); + + ath12k_core_rproc_start(ab_ahb->tgt_rrproc); + ath12k_core_rproc_start(ab_ahb->tgt_rproc); + ag->crash_type = ATH12K_NO_CRASH; + ath12k_core_wait_dump_collect(ab); +} + +/* Asserted target's reboot handling for crash type ATH12K_RPROC_USERPD_HYBRID_CRASH */ +static void ath12k_core_upd_rproc_boot_recovery(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_ahb *ab_ahb = ath12k_ahb_priv(ab); + + if (ag->crash_type != ATH12K_RPROC_USERPD_HYBRID_CRASH) + return; + + /* + * Stop user pd + * Collect coredump using user pd + * Free Target memory chunk + * Start root pd + */ + ath12k_core_rproc_stop(ab_ahb->tgt_rproc); + ath12k_core_rproc_coredump(ab, ab_ahb->tgt_rproc); + ath12k_qmi_free_target_mem_chunk(ab); + ath12k_core_rproc_start(ab_ahb->tgt_rproc); + ag->crash_type = ATH12K_NO_CRASH; + ath12k_core_wait_dump_collect(ab); +} + +/* Asserted target's reboot handling for crash type ATH12K_RPROC_ROOTPD_HYBRID_CRASH */ +static void ath12k_core_rpd_rproc_boot_recovery(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_ahb *ab_ahb = ath12k_ahb_priv(ab); + struct rproc *rootpd_rproc = ab_ahb->tgt_rrproc; + struct rproc *txtpd_rproc = ab_ahb->tgt_text_rproc; + struct rproc *usrpd_rproc = ab_ahb->tgt_rproc; + struct ath12k_base *tmp_ab; + int user_pd, ret; + + if (ag->crash_type != ATH12K_RPROC_ROOTPD_HYBRID_CRASH) + return; + + if (!rootpd_rproc || !usrpd_rproc) { + ath12k_err(ab, "rproc(s) are null\n"); + return; + } + + if (rootpd_rproc->state == RPROC_OFFLINE) { + ath12k_err(ab, "rootpd rproc:%s is already stopped.\n", + rootpd_rproc->name); + return; + } + + if (usrpd_rproc->state == RPROC_OFFLINE) { + ath12k_err(ab, "userpd rproc:%s is already stopped.\n", + usrpd_rproc->name); + return; + } + + usrpd_rproc->state = RPROC_CRASHED; + ret = ath12k_core_rproc_stop(usrpd_rproc); + if (ret) + ath12k_err(ab, "failed to stop user_pd:%s ret:%d\n", + usrpd_rproc->name, ret); + + /* Reboot Sequence of all remoteproc pds + * 1. Stop all user pds + * 2. In case of text device present, stop text pd + * 3. Stop the root pd + * 4. Do the coredump using root pd handle once all user pds and root + * pd are stopped: + * Root pd handle coredump will take care of all the userpd data + * collection as part of the coredump + * 5. Free Target memory chunk + * 6. Power up the remote processor again as per below sequence + * Start the rootpd device + * Start textpd device if present + * Start all userpd devices + */ + if (!ag->num_started) { + if (txtpd_rproc && txtpd_rproc->state != RPROC_OFFLINE) { + txtpd_rproc->state = RPROC_CRASHED; + ret = ath12k_core_rproc_stop(txtpd_rproc); + if (ret) + ath12k_err(ab, "failed to stop text_pd:%s ret:%d\n", + txtpd_rproc->name, ret); + } + rootpd_rproc->state = RPROC_RUNNING; + ret = ath12k_core_rproc_stop(rootpd_rproc); + if (ret) + ath12k_err(ab, "failed to stop root_pd:%s ret:%d\n", + rootpd_rproc->name, ret); + + ath12k_core_rproc_coredump(ab, rootpd_rproc); + } + + ath12k_qmi_free_target_mem_chunk(ab); + + if (!ag->num_started) { + ret = ath12k_core_rproc_start(rootpd_rproc); + if (ret) + ath12k_err(ab, "failed to start root_pd:%s ret:%d\n", + rootpd_rproc->name, ret); + + ath12k_core_wait_dump_collect(ab); + + if (txtpd_rproc) { + ret = ath12k_core_rproc_start(txtpd_rproc); + if (ret) + ath12k_err(ab, "failed to start text_pd:%s ret:%d\n", + txtpd_rproc->name, ret); + } + + for (user_pd = 0; user_pd < ag->num_chip; user_pd++) { + tmp_ab = ag->ab[user_pd]; + if (tmp_ab->hif.bus == ATH12K_BUS_PCI) + continue; + + ab_ahb = ath12k_ahb_priv(tmp_ab); + usrpd_rproc = ab_ahb->tgt_rproc; + ret = ath12k_core_rproc_start(usrpd_rproc); + if (ret) { + ath12k_err(tmp_ab, "failed to start user_pd:%s ret:%d\n", + usrpd_rproc->name, ret); + } + } + + ag->crash_type = ATH12K_NO_CRASH; + } +} + +/* + * Trigger umac_reset with umac_reset flag set. This is a + * waiting function which will return only after UMAC reset + * is complete on non-asserted chip set. UMAC reset completion + * is identified by waiting for MLO Teardown complete for all + * chipsets + */ +static int ath12k_core_trigger_umac_reset(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + long time_left; + int ret = 0; + + reinit_completion(&ag->umac_reset_complete); + + ath12k_mac_mlo_teardown_with_umac_reset(ab); + + time_left = wait_for_completion_timeout(&ag->umac_reset_complete, + msecs_to_jiffies(ATH12K_UMAC_RESET_TIMEOUT_IN_MS)); + + if (!time_left) { + ath12k_warn(ab, "UMAC reset didn't get completed within 200 ms\n"); + ret = -ETIMEDOUT; + } + + ag->trigger_umac_reset = false; + return ret; +} + +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT +static void ath12k_core_disable_ppe_rtnl_bond_release(struct ath12k_base *ab) +{ + struct ath12k *ar; + struct ath12k_pdev *pdev; + struct ath12k_link_vif *arvif; + struct net_device *link_ndev; + int i; + + rtnl_lock(); + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + + if (!ar || ar->state == ATH12K_STATE_OFF) + continue; + + mutex_lock(&ar->conf_mutex); + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->ndev_pvt) { + link_ndev = arvif->ndev_pvt->link_ndev; + if (arvif->ndev_pvt->bond_dev && + arvif->ndev_pvt->bond_dev->flags & IFF_UP) { + netif_tx_stop_all_queues(arvif->ndev_pvt->bond_dev); + arvif->ndev_pvt->bond_dev->flags &= ~IFF_UP; + } + + if (link_ndev) { + netif_tx_stop_all_queues(link_ndev); + if (ab->ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0) { + ath12k_bond_link_release(arvif); + ath12k_disable_ppe_for_link_netdev(ab, + arvif, + link_ndev); + } + } + } + } + mutex_unlock(&ar->conf_mutex); + } + + rtnl_unlock(); +} +#endif + static void ath12k_core_reset(struct work_struct *work) { struct ath12k_base *ab = container_of(work, struct ath12k_base, reset_work); - int reset_count, fail_cont_count; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_hw *ah; + struct ath12k_base *partner_ab; +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + struct ath12k_pdev *pdev; + struct ath12k *ar; + int j; +#endif + int reset_count, fail_cont_count, i; long time_left; + bool teardown = false; - if (!(test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags))) { - ath12k_warn(ab, "ignore reset dev flags 0x%lx\n", ab->dev_flags); - return; + if (ab->recovery_mode_address) { + switch (*ab->recovery_mode_address) { + case ATH12K_MLO_RECOVERY_MODE1: + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE1; + break; + case ATH12K_MLO_RECOVERY_MODE0: + fallthrough; + default: + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE0; } + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "mode:%d\n", ag->recovery_mode); + } else { + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE0; + } + ath12k_info(ab, "Recovery is initiated with Mode%s\n", + (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0 ? "0" : "1")); + +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + if (!ab->is_reset) { + ath12k_hif_ppeds_irq_disable(ab, PPEDS_IRQ_PPE2TCL); + ath12k_hif_ppeds_irq_disable(ab, PPEDS_IRQ_REO2PPE); + ath12k_hif_ppeds_irq_disable(ab, PPEDS_IRQ_PPE_WBM2SW_REL); + ath12k_core_disable_ppe_rtnl_bond_release(ab); + } +#endif /* Sometimes the recovery will fail and then the next all recovery fail, - * this is to avoid infinite recovery since it can not recovery success + * this is to avoid infinite recovery since it can not recovery success. */ fail_cont_count = atomic_read(&ab->fail_cont_count); - if (fail_cont_count >= ATH12K_RESET_MAX_FAIL_COUNT_FINAL) + if (fail_cont_count >= ATH12K_RESET_MAX_FAIL_COUNT_FINAL) { + ath12k_warn(ab, "Recovery Failed, Fail count:%d MAX_FAIL_COUNT final:%d\n", + fail_cont_count, + ATH12K_RESET_MAX_FAIL_COUNT_FINAL); return; + } if (fail_cont_count >= ATH12K_RESET_MAX_FAIL_COUNT_FIRST && - time_before(jiffies, ab->reset_fail_timeout)) + time_before(jiffies, ab->reset_fail_timeout)) { + ath12k_warn(ab, "Recovery Failed, Fail count:%d MAX_FAIL_COUNT first:%d\n", + fail_cont_count, + ATH12K_RESET_MAX_FAIL_COUNT_FIRST); return; + } reset_count = atomic_inc_return(&ab->reset_count); @@ -805,6 +3535,9 @@ */ ath12k_warn(ab, "already resetting count %d\n", reset_count); + if (ath12k_ssr_failsafe_mode && ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0) + BUG_ON(1); + reinit_completion(&ab->reset_complete); time_left = wait_for_completion_timeout(&ab->reset_complete, ATH12K_RESET_TIMEOUT_HZ); @@ -816,32 +3549,286 @@ ab->reset_fail_timeout = jiffies + ATH12K_RESET_FAIL_TIMEOUT_HZ; /* Record the continuous recovery fail count when recovery failed*/ - fail_cont_count = atomic_inc_return(&ab->fail_cont_count); + atomic_inc(&ab->fail_cont_count); } ath12k_dbg(ab, ATH12K_DBG_BOOT, "reset starting\n"); + ab->recovery_start_time = jiffies; + + mutex_lock(&ag->mutex_lock); + + if (!ab->is_reset) + ath12k_hif_irq_disable(ab); ab->is_reset = true; atomic_set(&ab->recovery_count, 0); + /* Incase recovery fails and FW asserts again, this is to prevent invalid operation. */ + if (ag->num_started && ab->fw_recovery_support) + ag->num_started--; + + if (!ag->hw_queues_stopped) { + ath12k_core_mlo_hw_queues_stop(ag, ab); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1) { + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + if (ab == partner_ab) + continue; + for (j = 0; j < partner_ab->num_radios; j++) { + pdev = &partner_ab->pdevs[j]; + ar = pdev->ar; + if (!ar) + continue; + ath12k_ppeds_partner_link_stop_queues(ar); + } + } + } +#endif + } + + + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + if (ab == partner_ab) + continue; + + teardown = false; + /* Need to check partner_ab flag to select recovery mode + * as Mode0, if continuous reset has happened + */ + + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1) { + if (test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &partner_ab->dev_flags) || + test_bit(ATH12K_FLAG_RECOVERY, &partner_ab->dev_flags)) { + /* On receiving MHI Interrupt for pdev which is + * already in UMAC Recovery, then fallback to + * MODE0 + */ + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE0; + } else if ((!test_bit(ATH12K_FLAG_RECOVERY, &partner_ab->dev_flags)) && + (!(test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &partner_ab->dev_flags)))) { + /* Set dev flags to UMAC recovery START + * and set flag to send teardown later + */ + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "setting teardown to true\n"); + set_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &partner_ab->dev_flags); + teardown = true; + continue; + } else { + /* if one of the ab is already in recovery, or + * in UMAC recovery start phase + * then fall back to MODE0 + */ + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE0; + } + ath12k_info(ab, "Recovery is falling back to Mode0 as one of the partner chip is already in recovery\n"); + } + } + + if (teardown) { + if (ath12k_core_trigger_umac_reset(ab) || + ath12k_mac_partner_peer_cleanup(ab)) { + /* Fallback to Mode0 if umac reset/peer_cleanup is + * failed + */ + ag->recovery_mode = ATH12K_MLO_RECOVERY_MODE0; +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ath12k_core_disable_ppe_rtnl_bond_release(ab); +#endif + ath12k_info(ab, "Recovery is falling back to Mode0\n"); + } else { + /* wake queues here as ping should continue for + * legacy clients in non-asserted chipsets + */ + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; + + ieee80211_wake_queues(ah->hw); + } +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + if (ab == partner_ab) + continue; + for (j = 0; j < partner_ab->num_radios; j++) { + pdev = &partner_ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + ath12k_ppeds_partner_link_start_queues(ar); + } + } +#endif + ath12k_dbg(ab, ATH12K_DBG_MODE1_RECOVERY, + "Queues are started as umac reset is completed for partner chipset\n"); + } + } + + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + if (ab == partner_ab) + continue; + + /* issue FW Hang command on partner chips for Mode0. This is a fool proof + * method to ensure recovery of all partner chips in MODE0 instead of + * relying on firmware to crash partner chips + */ + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0 && + !test_bit(ATH12K_FLAG_RECOVERY, &partner_ab->dev_flags)) { + ath12k_info(ab, "sending fw_hang cmd to partner chipset(s)\n"); + ath12k_wmi_force_fw_hang_cmd(partner_ab->pdevs[0].ar, + ATH12K_WMI_FW_HANG_ASSERT_TYPE, + ATH12K_WMI_FW_HANG_DELAY, true); + } + } + ath12k_core_pre_reconfigure_recovery(ab); - reinit_completion(&ab->reconfigure_complete); ath12k_core_post_reconfigure_recovery(ab); - reinit_completion(&ab->recovery_start); - atomic_set(&ab->recovery_start_count, 0); - - ath12k_dbg(ab, ATH12K_DBG_BOOT, "waiting recovery start...\n"); + /* reset host fixed mem off to zero */ + ab->host_ddr_fixed_mem_off = 0; - time_left = wait_for_completion_timeout(&ab->recovery_start, - ATH12K_RECOVER_START_TIMEOUT_HZ); + /* prepare coredump when bus is PCI + * In case of AHB, the coredump occurs in rproc module + */ + if (ab->hif.bus == ATH12K_BUS_PCI) { + ath12k_coredump_download_rddm(ab); + } else if (ab->hif.bus == ATH12K_BUS_AHB || ab->hif.bus == ATH12K_BUS_HYBRID) { + ath12k_coredump_download_ahb(ab); + } + if (ab->is_qdss_tracing) + ab->is_qdss_tracing = false; + if (ab->fw_recovery_support) { + if (ab->hif.bus == ATH12K_BUS_PCI) { ath12k_hif_power_down(ab); ath12k_hif_power_up(ab); - + } else if (ab->hif.bus == ATH12K_BUS_AHB || + ab->hif.bus == ATH12K_BUS_HYBRID) { + if (IS_ENABLED(CONFIG_REMOTEPROC)) { + /* When crash type ATH12K_RPROC_USERPD_HYBRID_CRASH is set */ + ath12k_core_upd_rproc_boot_recovery(ab); + /* When crash type ATH12K_RPROC_ROOTPD_AHB_CRASH is set */ + ath12k_core_rproc_boot_recovery(ab); + /* When crash type ATH12K_RPROC_ROOTPD_HYBRID_CRASH is set */ + ath12k_core_rpd_rproc_boot_recovery(ab); + } + } ath12k_dbg(ab, ATH12K_DBG_BOOT, "reset started\n"); } + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1) + ab->recovery_start = true; + + ab->recovery_mode_address = NULL; + ab->crash_info_address = NULL; + + mutex_unlock(&ag->mutex_lock); +} + +static int load_board_id_override(struct ath12k_base *ab) +{ + struct ath12k_bid_override *ov, *tmp; + const struct firmware *fw; + const char *p, *end; + size_t len; + int ret, count; + + fw = ath12k_core_firmware_request(ab, ATH12K_BOARD_OVERRIDE_FILE); + if (IS_ERR(fw)) { + /* file is optional */ + if (PTR_ERR(fw) == -ENOENT) + return 0; + return PTR_ERR(fw); + } + + /* format is = [...] */ + p = fw->data; + len = fw->size; + end = p + len; + count = 0; + + while (1) { + const char *pstart; + char *ppath, *pbid, endc; + unsigned int seg, bus, slot, func; + u16 board_id; + + while (p != end && isspace(*p)) + p++; + if (p == end) + break; + + pstart = p; + while (p != end && !isspace(*p)) + p++; + + if (p == end) { + ret = -EINVAL; + goto fail; + } + + ppath = kstrndup(pstart, p - pstart, GFP_KERNEL); + if (!pstart) { + ret = -ENOMEM; + goto fail; + } + + pbid = strchr(ppath, '='); + if (!pbid) { + ath12k_err(ab, "bad key=value in override file\n"); + ret = -EINVAL; + kfree(ppath); + goto fail; + } + + *pbid++ = 0; + + ret = sscanf(ppath, "pci:%x:%x:%x.%x%c", &seg, &bus, &slot, + &func, &endc); + if (ret != 4) { + ath12k_err(ab, "invalid pci dev in override file\n"); + kfree(ppath); + ret = -EINVAL; + goto fail; + } + + if (kstrtou16(pbid, 0, &board_id)) { + ath12k_err(ab, "invalid board-id in override file\n"); + kfree(ppath); + ret = -EINVAL; + goto fail; + } + + ov = kzalloc(sizeof (*ov), GFP_KERNEL); + ov->domain = seg; + ov->bus_nr = bus; + ov->slot = slot; + ov->func = func; + ov->board_id = board_id; + list_add_tail(&ov->next, &ab->board_id_overrides); + count++; + } + + if (count) + ath12k_info(ab, "loaded %d entries from board-id " + "override file\n", count); + release_firmware(fw); + return 0; + +fail: + ath12k_err(ab, "invalid board-id override file content\n"); + release_firmware(fw); + list_for_each_entry_safe(ov, tmp, &ab->board_id_overrides, next) + kfree(ov); + INIT_LIST_HEAD(&ab->board_id_overrides); + return ret; +} int ath12k_core_pre_init(struct ath12k_base *ab) { @@ -853,45 +3840,289 @@ return ret; } + ret = load_board_id_override(ab); + if (ret) + return ret; + return 0; } -int ath12k_core_init(struct ath12k_base *ab) +static int ath12k_core_get_chip(struct ath12k_hw_group *ag, + struct ath12k_base **ab, + u8 max_ab, u8 *num_ab) { - int ret; + int i; + + lockdep_assert_held(&ag->mutex_lock); + + if (ag->num_chip != ag->num_probed) + return -EINVAL; + + if (max_ab < ag->num_probed) + return -ENOMEM; + + *num_ab = 0; + for (i = 0; i < ag->num_probed; i++) { + ab[i] = ag->ab[i]; + *num_ab = *num_ab + 1; + } + + return 0; +} + +static int ath12k_core_hw_group_create(struct ath12k_base **ab_group, u8 num_ab) +{ + int i, ret = 0; + struct ath12k_base *ab; + + for(i = 0; i < num_ab; i++) { + ab = ab_group[i]; + mutex_lock(&ab->core_lock); ret = ath12k_core_soc_create(ab); if (ret) { + mutex_unlock(&ab->core_lock); ath12k_err(ab, "failed to create soc core: %d\n", ret); + goto out; + } + set_bit(ATH12K_FLAG_HW_GROUP_ATTACHED, &ab->dev_flags); + mutex_unlock(&ab->core_lock); + + ath12k_qmi_fwreset_from_cold_boot(ab); + + } + +out: return ret; } +int ath12k_core_init(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag; + struct ath12k_base *ab_group[ATH12K_MAX_SOCS]; + bool is_ready = false; + u8 num_ab; + int ret; + + /* Register a notifier after core init + * to be called on fw crash + */ + init_waitqueue_head(&ab->ipci.gic_msi_waitq); + ab->ssr_nb.notifier_call = ath12k_core_ssr_notifier_cb; + ab->atomic_ssr_nb.notifier_call = ath12k_core_atomic_ssr_notifier_cb; + ab->rpd_ssr_nb.notifier_call = ath12k_core_rpd_ssr_notifier_cb; + ab->rpd_atomic_ssr_nb.notifier_call = ath12k_core_rpd_atomic_ssr_notifier_cb; + + ret = ath12k_hif_ssr_notifier_reg(ab); + if (ret) { + ath12k_err(ab, "failed to register ssr notifier callback\n"); + return ret; + } + ab->multi_pd_arch = of_property_read_bool(ab->dev->of_node, "qcom,multipd_arch"); + ret = ath12k_debugfs_soc_create(ab); + if (ret) { + ath12k_err(ab, "failed to create debugfs\n"); + return ret; + } + + mutex_lock(&ath12k_hw_lock); + + ag = ath12k_core_get_hw_group(ab); + if (!ag) { + mutex_unlock(&ath12k_hw_lock); + ath12k_err(ab, "unable to get hw group\n"); + goto err_debugfs; + } + mutex_unlock(&ath12k_hw_lock); + + mutex_lock(&ag->mutex_lock); + + ath12k_dbg(ab, ATH12K_DBG_BOOT, "num chips in group %d, num probed %d\n", + ag->num_chip, ag->num_probed); + + is_ready = ath12k_core_hw_group_create_ready(ag); + if (is_ready) { + ret = ath12k_core_get_chip(ag, ab_group, ATH12K_MAX_SOCS, &num_ab); + if (ret) { + mutex_unlock(&ag->mutex_lock); + ath12k_err(ab, "unable to get chip from hw group %d\n", ret); + goto err_debugfs; + } + } + + mutex_unlock(&ag->mutex_lock); + + if (is_ready) { + ret = ath12k_core_hw_group_create(ab_group, num_ab); + if (ret) { + ath12k_warn(ab, "unable to create hw group\n"); + goto err_hw_group; + } + } + + ag->mgmt_rx_reorder = ath12k_mgmt_rx_reordering; + return 0; + +err_hw_group: + ath12k_core_put_hw_group(ab); +err_debugfs: + ath12k_debugfs_soc_destroy(ab); + return ret; } -void ath12k_core_deinit(struct ath12k_base *ab) +static void ath12k_core_hw_group_destroy(struct ath12k_hw_group *ag) +{ + struct ath12k_base *ab; + int i; + + lockdep_assert_held(&ag->mutex_lock); + + for(i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + mutex_lock(&ab->core_lock); + if (test_bit(ATH12K_FLAG_HW_GROUP_ATTACHED, &ab->dev_flags)) { + clear_bit(ATH12K_FLAG_HW_GROUP_ATTACHED, &ab->dev_flags); + ath12k_reg_free(ab); + ath12k_dp_free(ab); + ath12k_core_soc_destroy(ab); + } + mutex_unlock(&ab->core_lock); + } +} + +static void ath12k_core_hw_group_stop(struct ath12k_hw_group *ag) { + struct ath12k_base *ab; + struct ath12k_dp *dp; + u32 address; + int i; + + lockdep_assert_held(&ag->mutex_lock); + + if (!test_bit(ATH12K_FLAG_REGISTERED, &ag->dev_flags)) + return; + + clear_bit(ATH12K_FLAG_REGISTERED, &ag->dev_flags); + + for (i = ag->num_chip - 1; i >= 0; i--) { + ab = ag->ab[i]; + + mutex_lock(&ab->core_lock); + + ath12k_core_pdev_deinit(ab); + + mutex_unlock(&ab->core_lock); + } + + ath12k_mac_unregister(ag); + + ath12k_core_mlo_teardown(ag); + + for (i = ag->num_chip - 1; i >= 0; i--) { + ab = ag->ab[i]; + mutex_lock(&ab->core_lock); + ath12k_hif_irq_disable(ab); ath12k_core_pdev_destroy(ab); ath12k_core_stop(ab); + ath12k_dp_umac_reset_deinit(ab); + clear_bit(ATH12K_FLAG_CORE_REGISTERED, &ab->dev_flags); + + mutex_unlock(&ab->core_lock); + } + + for (i = ag->num_chip - 1; i >= 0; i--) { + ab = ag->ab[i]; + dp = &ab->dp; + + mutex_lock(&ab->core_lock); + + if (!ab->hw_params->reoq_lut_support) + break; + + if (!dp->reoq_lut.vaddr) + break; + + if (dp->reoq_lut.vaddr) { + address = HAL_SEQ_WCSS_UMAC_REO_REG +\ + HAL_REO1_QDESC_LUT_BASE0(ab); + ath12k_hif_write32(ab, address, 0); + } + + if (dp->ml_reoq_lut.vaddr) { + address = HAL_SEQ_WCSS_UMAC_REO_REG +\ + HAL_REO1_QDESC_LUT_BASE1(ab); + ath12k_hif_write32(ab, address, 0); + } + + ath12k_hif_power_down(ab); mutex_unlock(&ab->core_lock); + } + ath12k_mac_destroy(ag); + + ath12k_core_hw_group_destroy(ag); +} + +void ath12k_core_deinit(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + int ret; + + mutex_lock(&ag->mutex_lock); + if (test_bit(ATH12K_FLAG_REGISTERED, &ag->dev_flags)) { + ath12k_core_hw_group_stop(ag); + } else if (test_bit(ATH12K_FLAG_HW_GROUP_ATTACHED, &ab->dev_flags)) { + mutex_lock(&ab->core_lock); + + clear_bit(ATH12K_FLAG_HW_GROUP_ATTACHED, &ab->dev_flags); + if (test_bit(ATH12K_FLAG_CORE_REGISTERED, &ab->dev_flags)) { + ath12k_core_stop(ab); + ath12k_reg_free(ab); + ath12k_dp_free(ab); + clear_bit(ATH12K_FLAG_CORE_REGISTERED, &ab->dev_flags); + } ath12k_hif_power_down(ab); - ath12k_mac_destroy(ab); ath12k_core_soc_destroy(ab); + + mutex_unlock(&ab->core_lock); + } + + ath12k_debugfs_soc_destroy(ab); + + /* Unregister the ssr notifier as we are not intersted + * in receving these notifications after mac is unregistered. + */ + ret = ath12k_hif_ssr_notifier_unreg(ab); + if (ret) + ath12k_err(ab, "failed to un-register ssr notifier callback\n"); + + mutex_unlock(&ag->mutex_lock); + + ath12k_core_put_hw_group(ab); } void ath12k_core_free(struct ath12k_base *ab) { + struct ath12k_bid_override *ov, *tmp; + del_timer_sync(&ab->rx_replenish_retry); + flush_workqueue(ab->workqueue_aux); destroy_workqueue(ab->workqueue_aux); + + flush_workqueue(ab->workqueue); destroy_workqueue(ab->workqueue); + list_for_each_entry_safe(ov, tmp, &ab->board_id_overrides, next) + kfree(ov); kfree(ab); } struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, - enum ath12k_bus bus) + enum ath12k_bus bus, + const struct ath12k_bus_params *bus_params) { struct ath12k_base *ab; @@ -899,8 +4130,6 @@ if (!ab) return NULL; - init_completion(&ab->driver_recovery); - ab->workqueue = create_singlethread_workqueue("ath12k_wq"); if (!ab->workqueue) goto err_sc_free; @@ -909,23 +4138,34 @@ if (!ab->workqueue_aux) goto err_free_wq; + ab->stats_disable = ath12k_stats_disable; mutex_init(&ab->core_lock); + mutex_init(&ab->tbl_mtx_lock); spin_lock_init(&ab->base_lock); init_completion(&ab->reset_complete); - init_completion(&ab->reconfigure_complete); - init_completion(&ab->recovery_start); + INIT_LIST_HEAD(&ab->board_id_overrides); INIT_LIST_HEAD(&ab->peers); + INIT_LIST_HEAD(&ab->neighbor_peers); init_waitqueue_head(&ab->peer_mapping_wq); init_waitqueue_head(&ab->wmi_ab.tx_credits_wq); + init_waitqueue_head(&ab->qmi.cold_boot_waitq); + init_waitqueue_head(&ab->ssr_dump_wq); INIT_WORK(&ab->restart_work, ath12k_core_restart); INIT_WORK(&ab->reset_work, ath12k_core_reset); + INIT_WORK(&ab->recovery_work, ath12k_core_mode1_recovery_work); timer_setup(&ab->rx_replenish_retry, ath12k_ce_rx_replenish_retry, 0); init_completion(&ab->htc_suspend); + init_completion(&ab->rddm_reset_done); ab->dev = dev; + ab->bus_params = *bus_params; ab->hif.bus = bus; + ab->qmi.num_radios = ATH12K_QMI_INVALID_RADIO; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ab->ppeds_node_idx = -1; +#endif return ab; err_free_wq: @@ -935,5 +4175,174 @@ return NULL; } -MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11be wireless LAN cards."); +#ifdef CONFIG_ATH12K_SAWF + +int ath12k_send_sawf_configs_soc(struct ath12k_sawf_svc_params *new_param) +{ + struct ath12k_hw_group *ag; + struct ath12k_base *ab; + struct ath12k *ar; + int soc, ret = 0; + + mutex_lock(&ath12k_hw_lock); + list_for_each_entry(ag, &ath12k_hw_groups, list) { + if (!ag) { + ath12k_warn(NULL, "unable to fetch hw group\n"); + mutex_unlock(&ath12k_hw_lock); + return -ENODEV; + } + for (soc = ag->num_probed; soc > 0; soc--) { + ab = ag->ab[soc - 1]; + ar = ab->pdevs[0].ar; + if (!ar) { + /* Control should not reach here */ + ath12k_info(ab, "Radio not initialized in the SOC\n"); + continue; + } + ret = ath12k_wmi_svc_config_send(ar, new_param); + if (ret) { + mutex_unlock(&ath12k_hw_lock); + return ret; + } + } + } + mutex_unlock(&ath12k_hw_lock); + return ret; +} + +int ath12k_sawf_send_disable_soc(u8 svc_id) +{ + struct ath12k_hw_group *ag; + struct ath12k_base *ab; + struct ath12k *ar; + int soc, ret = 0; + + mutex_lock(&ath12k_hw_lock); + list_for_each_entry(ag, &ath12k_hw_groups, list) { + if (!ag) { + ath12k_warn(NULL, "unable to fetch hw group\n"); + mutex_unlock(&ath12k_hw_lock); + return -ENODEV; + } + for (soc = ag->num_probed; soc > 0; soc--) { + ab = ag->ab[soc - 1]; + ar = ab->pdevs[0].ar; + if (!ar) { + /* Control should not reach here */ + ath12k_info(ab, "Radio not initialized in the SOC\n"); + continue; + } + ret = ath12k_wmi_svc_send_disable(ar, svc_id); + if (ret) { + mutex_unlock(&ath12k_hw_lock); + return ret; + } + } + } + mutex_unlock(&ath12k_hw_lock); + return ret; +} + +int ath12k_core_sawf_ul_config(struct net_device *dev, struct ath12k_sawf_wmi_peer_latency_param *latency_info) +{ + struct ath12k_base *ab; + u16 peer_id; + int ret = -EOPNOTSUPP; + + if (!latency_info) + return -EINVAL; + + ab = ath12k_sawf_get_ab_from_netdev(dev, latency_info->peer_mac, &peer_id); + if (ab) + ret = ath12k_sawf_wmi_config_ul(ab, latency_info); + return ret; +} + +void *ath12k_get_ab_nd_peer_from_peer_mac(u8 *peer_mac, struct ath12k_base **ab_ref) +{ + struct ath12k_hw_group *ag = NULL; + struct ath12k_base *ab = NULL; + void *peer = NULL; + int soc; + + mutex_lock(&ath12k_hw_lock); + list_for_each_entry(ag, &ath12k_hw_groups, list) { + if (!ag) { + ath12k_warn(NULL, "unable to fetch hw group\n"); + mutex_unlock(&ath12k_hw_lock); + return -ENODEV; + } + for (soc = ag->num_probed; soc > 0; soc--) { + + ab = ag->ab[soc - 1]; + if (!ab) { + /* Control should not reach here */ + ath12k_info(NULL, "SOC not initialized\n"); + continue; + } + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_addr(ab, peer_mac); + spin_unlock_bh(&ab->base_lock); + if (peer) { + mutex_unlock(&ath12k_hw_lock); + *ab_ref = ab; + return peer; + } + ab = NULL; + } + } + mutex_unlock(&ath12k_hw_lock); + return peer; +} + +#endif /* CONFIG_ATH12K_SAWF */ + +static int ath12k_init(void) +{ + int ret; + + ret = ath12k_debugfs_create(); + if (ret) { + pr_err("Failed to register debugfs ath12k driver: %d\n", ret); + return ret; + } + + ret = ath12k_ahb_init(); + if (ret) { + ret = -ENODEV; + pr_err("Failed to initialize ath12k AHB device: %d\n", ret); + goto error; + } + + ret = ath12k_pci_init(); + if (ret) { + ret = -ENODEV; + pr_err("Failed to initialize ath12k PCI device: %d\n", ret); + goto error_ahb; + } + + return 0; + +error_ahb: + ath12k_ahb_exit(); +error: + ath12k_debugfs_destroy(); + + return ret; +} + +static void ath12k_exit(void) +{ + ath12k_pci_exit(); + ath12k_ahb_exit(); + ath12k_debugfs_destroy(); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ath12k_bond_disable_ppe_ds(); +#endif +} + +module_init(ath12k_init) +module_exit(ath12k_exit) + +MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11be WLAN PCIe/AHB devices"); MODULE_LICENSE("Dual BSD/GPL"); diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/core.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/core.h --- linux-6.4/drivers/net/wireless/ath/ath12k/core.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/core.h 2024-04-19 16:04:28.953735667 +0200 @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH12K_CORE_H @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include "qmi.h" #include "htc.h" #include "wmi.h" @@ -21,10 +23,22 @@ #include "hw.h" #include "hal_rx.h" #include "reg.h" +#include "thermal.h" #include "dbring.h" +#include "spectral.h" +#include "pktlog.h" +#include "sawf.h" +#include "vendor.h" +#include "telemetry_agent_if.h" +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#include +#include +#endif #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) +#define ATH12K_MAX_NUM_PWR_LEVEL 16 + #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 @@ -36,13 +50,31 @@ #define ATH12K_RX_RATE_TABLE_NUM 320 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 +extern unsigned int ath12k_frame_mode; + + +extern bool ath12k_debug_critical; #define ATH12K_MON_TIMER_INTERVAL 10 -#define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) +#define ATH12K_RESET_TIMEOUT_HZ (180 * HZ) #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) +#define ATH12K_UMAC_RESET_TIMEOUT_IN_MS 200 + +#define INVALID_CIPHER 0xFFFFFFFF + +#define ATH12K_MAX_MLO_PEERS 256 +#define ATH12K_MLO_PEER_ID_INVALID 0xFFFF + +#define ATH12K_SSR_POWERUP QCOM_SSR_AFTER_POWERUP +#define ATH12K_SSR_PREPARE_SHUTDOWN 5 + +enum ath12k_bdf_search { + ATH12K_BDF_SEARCH_DEFAULT, + ATH12K_BDF_SEARCH_BUS_AND_BOARD, +}; enum wme_ac { WME_AC_BE, @@ -53,8 +85,10 @@ }; #define ATH12K_HT_MCS_MAX 7 -#define ATH12K_VHT_MCS_MAX 9 +#define ATH12K_VHT_MCS_MAX 11 #define ATH12K_HE_MCS_MAX 11 +#define ATH12K_HE_EXTRA_MCS_MAX 13 +#define ATH12K_EHT_MCS_MAX 15 enum ath12k_crypt_mode { /* Only use hardware crypto engine */ @@ -74,15 +108,19 @@ enum ath12k_skb_flags { ATH12K_SKB_HW_80211_ENCAP = BIT(0), ATH12K_SKB_CIPHER_SET = BIT(1), + ATH12K_SKB_TX_STATUS = BIT(2), + ATH12K_SKB_MGMT_LINK_AGNOSTIC = BIT(3), }; struct ath12k_skb_cb { dma_addr_t paddr; - struct ath12k *ar; + u8 eid; struct ieee80211_vif *vif; dma_addr_t paddr_ext_desc; u32 cipher; u8 flags; + u8 link_id; + u16 pkt_offset; }; struct ath12k_skb_rxcb { @@ -92,32 +130,44 @@ bool is_continuation; bool is_mcbc; bool is_eapol; + bool is_end_of_ppdu; struct hal_rx_desc *rx_desc; u8 err_rel_src; u8 err_code; - u8 mac_id; + u8 hw_link_id; u8 unmapped; u8 is_frag; u8 tid; u16 peer_id; + struct napi_struct *napi; }; enum ath12k_hw_rev { - ATH12K_HW_QCN9274_HW10, + ATH12K_HW_QCN9274_HW10 = 0, ATH12K_HW_QCN9274_HW20, - ATH12K_HW_WCN7850_HW20 + ATH12K_HW_WCN7850_HW20, + ATH12K_HW_IPQ5332_HW10, + ATH12K_HW_QCN6432_HW10, }; +#define ATH12K_DIAG_HW_ID_OFFSET 16 + enum ath12k_firmware_mode { /* the default mode, standard 802.11 functionality */ ATH12K_FIRMWARE_MODE_NORMAL, /* factory tests etc */ ATH12K_FIRMWARE_MODE_FTM, + + /* Cold boot calibration */ + ATH12K_FIRMWARE_MODE_COLD_BOOT = 7, }; +extern bool ath12k_cold_boot_cal; + #define ATH12K_IRQ_NUM_MAX 57 #define ATH12K_EXT_IRQ_NUM_MAX 16 +#define ATH12K_MAX_TCL_RING_NUM 3 struct ath12k_ext_irq_grp { struct ath12k_base *ab; @@ -125,6 +175,7 @@ u32 num_irq; u32 grp_id; u64 timestamp; + bool napi_enabled; struct napi_struct napi; struct net_device napi_ndev; }; @@ -137,6 +188,11 @@ #define HE_PPET16_PPET8_SIZE 8 +enum ath12k_msi_supported_hw { + ATH12K_MSI_CONFIG_PCI, + ATH12K_MSI_CONFIG_IPCI, +}; + /* 802.11ax PPE (PPDU packet Extension) threshold */ struct he_ppe_threshold { u32 numss_m1; @@ -154,6 +210,11 @@ }; #define MAX_RADIOS 3 +#define ATH12K_MAX_SOCS 3 +#define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_SOCS * MAX_RADIOS) +#define ATH12K_INVALID_GRP_ID 0xFF +#define ATH12K_INVALID_CHIP_ID 0xFF +#define ATH12K_MAX_MLO_PEER 0x100 enum { WMI_HOST_TP_SCALE_MAX = 0, @@ -173,40 +234,238 @@ enum ath12k_dev_flags { ATH12K_CAC_RUNNING, + ATH12K_FLAG_CORE_REGISTERED, ATH12K_FLAG_CRASH_FLUSH, ATH12K_FLAG_RAW_MODE, ATH12K_FLAG_HW_CRYPTO_DISABLED, + ATH12K_FLAG_BTCOEX, ATH12K_FLAG_RECOVERY, ATH12K_FLAG_UNREGISTERING, ATH12K_FLAG_REGISTERED, ATH12K_FLAG_QMI_FAIL, ATH12K_FLAG_HTC_SUSPEND_COMPLETE, + ATH12K_FLAG_QMI_FW_READY_COMPLETE, + ATH12K_FLAG_QMI_HOST_CAP_SENT, + ATH12K_FLAG_HW_GROUP_ATTACHED, + ATH12K_FLAG_FTM_SEGMENTED, + ATH12K_FLAG_PPE_DS_ENABLED, + ATH12K_FLAG_WMI_INIT_DONE, + ATH12K_FLAG_UMAC_PRERESET_START, + ATH12K_FLAG_UMAC_RESET_COMPLETE, + ATH12K_FLAG_UMAC_RECOVERY_START, }; enum ath12k_monitor_flags { ATH12K_FLAG_MONITOR_ENABLED, + MONITOR_VDEV_CREATED, + MONITOR_VDEV_STARTED, + MONITOR_CONF_ENABLED, +}; + +struct ath12k_fw_vdev_ol_stats { + u64 rx_msdu_byte_cnt; + u64 rx_msdu_pkt_cnt; + u64 tx_msdu_byte_cnt; + u64 tx_msdu_pkt_cnt; + u64 tx_retry_byte_cnt; + u64 tx_retry_pkt_cnt; + u64 tx_drop_byte_cnt; + u64 tx_drop_pkt_cnt; + u64 tx_msdu_ttl_byte_cnt; + u64 tx_msdu_ttl_pkt_cnt; +}; + +/** + * struct chan_power_info - TPE containing power info per channel chunk + * @chan_cfreq: channel center freq (MHz) + * e.g. + * channel 37/20MHz, it is 6135 + * channel 37/40MHz, it is 6125 + * channel 37/80MHz, it is 6145 + * channel 37/160MHz, it is 6185 + * @tx_power: transmit power (dBm) + */ +struct chan_power_info { + u16 chan_cfreq; + s8 tx_power; }; -struct ath12k_vif { +/** + * struct reg_tpc_power_info - regulatory TPC power info + * @is_psd_power: is PSD power or not + * @eirp_power: Maximum EIRP power (dBm), valid only if power is PSD + * @power_type_6g: type of power (SP/LPI/VLP) + * @num_pwr_levels: number of power levels + * @reg_max: Array of maximum TX power (dBm) per PSD value + * @ap_constraint_power: AP constraint power (dBm) + * @tpe: TPE values processed from TPE IE + * @chan_power_info: power info to send to FW + */ +struct ath12k_reg_tpc_power_info { + bool is_psd_power; + u8 eirp_power; + enum wmi_reg_6g_ap_type power_type_6g; + u8 num_pwr_levels; + u8 reg_max[ATH12K_MAX_NUM_PWR_LEVEL]; + u8 ap_constraint_power; + s8 tpe[ATH12K_MAX_NUM_PWR_LEVEL]; + struct chan_power_info chan_power_info[ATH12K_MAX_NUM_PWR_LEVEL]; +}; + +#define ATH12K_STATS_MGMT_FRM_TYPE_MAX 16 + +struct ath12k_mgmt_frame_stats { + u32 tx_succ_cnt[ATH12K_STATS_MGMT_FRM_TYPE_MAX]; + u32 tx_fail_cnt[ATH12K_STATS_MGMT_FRM_TYPE_MAX]; + u32 rx_cnt[ATH12K_STATS_MGMT_FRM_TYPE_MAX]; + u32 tx_compl_succ[ATH12K_STATS_MGMT_FRM_TYPE_MAX]; + u32 tx_compl_fail[ATH12K_STATS_MGMT_FRM_TYPE_MAX]; +}; + +struct ath12k_tx_conf { + bool changed; + u16 ac; + struct ieee80211_tx_queue_params tx_queue_params; +}; + +struct ath12k_key_conf { + enum set_key_cmd cmd; + struct list_head list; + struct ieee80211_sta *sta; + struct ieee80211_key_conf *key; +}; + +struct ath12k_recovery_cache { + struct ath12k_tx_conf tx_conf; + struct ath12k_key_conf key_conf; + struct list_head recovery_sta_list; + u64 bss_conf_changed; +}; + +struct ath12k_vif_cache { + struct ath12k_tx_conf tx_conf; + struct ath12k_key_conf key_conf; + u64 bss_conf_changed; +}; + +struct ath12k_vif_tcl_desc_template { + u32 info0; + u32 info1; + u32 info2; + u32 info3; + u32 info4; +}; + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +struct ath12k_link_vif_pvt { + struct ath12k_base *ab; + struct ath12k_link_vif *arvif; + struct net_device *link_ndev; + struct net_device *bond_dev; + struct ieee80211_hw *hw; + bool is_started; + bool is_bond_enslaved; + int ppe_vp_profile_idx; + int vp_num; +}; +#endif + +struct ath12k_peer_ch_width_switch_data { + int count; + struct wmi_chan_width_peer_arg peer_arg[]; +}; + +struct ath12k_prb_resp_tmpl_ml_info { + u32 hw_link_id; + u32 cu_vdev_map_cat1_lo; + u32 cu_vdev_map_cat1_hi; + u32 cu_vdev_map_cat2_lo; + u32 cu_vdev_map_cat2_hi; +}; + +struct ath12k_link_vif { + struct ath12k_base *ab; + struct ath12k_dp *dp; + struct ath12k_vif_tcl_desc_template desc; + struct ieee80211_vif *vif; + struct device *dev; + struct ath12k *ar; + bool assoc_link; + bool vdev_stop_notify_done; + u8 pdev_idx; u32 vdev_id; - enum wmi_vdev_type vdev_type; - enum wmi_vdev_subtype vdev_subtype; u32 beacon_interval; u32 dtim_period; + u8 addr[ETH_ALEN]; u16 ast_hash; u16 ast_idx; u16 tcl_metadata; u8 hal_addr_search_flags; u8 search_type; - - struct ath12k *ar; - struct ieee80211_vif *vif; - int bank_id; u8 vdev_id_check_en; + bool beacon_prot; struct wmi_wmm_params_all_arg wmm_params; struct list_head list; + + bool is_created; + bool is_started; + bool is_scan_vif; + bool is_up; + bool pending_up; + bool pending_stop; + bool spectral_enabled; + u8 bssid[ETH_ALEN]; + struct cfg80211_bitrate_mask bitrate_mask; + int num_legacy_stations; + int rtscts_prot_mode; + int txpower; + struct ieee80211_chanctx_conf chanctx; + struct ath12k_reg_tpc_power_info reg_tpc_info; + u8 vdev_stats_id; + struct ath12k_fw_vdev_ol_stats vdev_stats; + struct host_link_stats link_stats; + bool bcca_zero_sent; + bool do_not_send_tmpl; + u32 vht_cap; +#ifdef CONFIG_ATH12K_DEBUGFS + struct dentry *debugfs_twt; + struct dentry *debugfs_rtsthreshold; +#endif /* CONFIG_ATH12K_DEBUGFS */ + struct work_struct update_bcn_template_work; + u64 obss_color_bitmap; + struct work_struct update_obss_color_notify_work; + u32 tx_vdev_id; + u8 link_id; + struct ath12k_vif *ahvif; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + struct ath12k_link_vif_pvt *ndev_pvt; + struct net_device *link_ndev; + int ppe_vp_type; + int ppe_vp_num; +#endif + + bool mvr_processing; + bool pending_csa_up; + int num_stations; + + struct completion peer_ch_width_switch_send; + struct work_struct peer_ch_width_switch_work; + struct ath12k_peer_ch_width_switch_data *peer_ch_width_switch_data; + struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; + struct ath12k_prb_resp_tmpl_ml_info ml_info; +}; + +struct ath12k_vif { + enum wmi_vdev_type vdev_type; + enum wmi_vdev_subtype vdev_subtype; + struct ieee80211_vif *vif; + struct ath12k_hw *ah; + bool rsnie_present; + bool wpaie_present; + u8 tx_encap_type; + u32 key_cipher; union { struct { u32 uapsd; @@ -224,25 +483,30 @@ } ap; } u; - bool is_started; - bool is_up; + struct ath12k_link_vif deflink; + struct ath12k_link_vif *link[ATH12K_NUM_MAX_LINKS]; + /* indicates bitmap of link vdev created in FW */ + unsigned long links_map; u32 aid; - u8 bssid[ETH_ALEN]; - struct cfg80211_bitrate_mask bitrate_mask; - int num_legacy_stations; - int rtscts_prot_mode; - int txpower; - bool rsnie_present; - bool wpaie_present; - struct ieee80211_chanctx_conf chanctx; - u32 key_cipher; - u8 tx_encap_type; - u8 vdev_stats_id; + struct ath12k_mgmt_frame_stats mgmt_stats; + u8 num_vdev_created; + u16 mcbc_gsn; + spinlock_t mcbc_gsn_lock; /* Protect mcbc_gsn */ + struct ath12k_vif_cache cache[IEEE80211_MLD_MAX_NUM_LINKS]; + u8 last_scan_link; + u8 primary_link_id; +#ifdef CONFIG_ATH12K_DEBUGFS + struct dentry *debugfs_linkstats; + struct dentry *debugfs_primary_link; +#endif /* CONFIG_ATH12K_DEBUGFS */ + bool mcast_to_ucast_en; + bool chanctx_peer_del_done; }; struct ath12k_vif_iter { u32 vdev_id; - struct ath12k_vif *arvif; + struct ath12k *ar; + struct ath12k_link_vif *arvif; }; #define HAL_AST_IDX_INVALID 0xFFFF @@ -250,20 +514,23 @@ #define HAL_RX_MAX_MCS_HT 31 #define HAL_RX_MAX_MCS_VHT 9 #define HAL_RX_MAX_MCS_HE 11 +#define HAL_RX_MAX_MCS_BE 15 #define HAL_RX_MAX_NSS 8 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 #define ATH12K_RX_RATE_TABLE_NUM 320 +#define ATH12K_STATS_MGMT_FRM_TYPE_MAX 16 struct ath12k_rx_peer_rate_stats { u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; + u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1]; u64 nss_count[HAL_RX_MAX_NSS]; u64 bw_count[HAL_RX_BW_MAX]; u64 gi_count[HAL_RX_GI_MAX]; u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; - u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; + u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1]; }; struct ath12k_rx_peer_stats { @@ -293,6 +560,7 @@ }; #define ATH12K_HE_MCS_NUM 12 +#define ATH12K_EHT_MCS_NUM 16 #define ATH12K_VHT_MCS_NUM 10 #define ATH12K_BW_NUM 5 #define ATH12K_NSS_NUM 4 @@ -347,6 +615,7 @@ u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; + u64 eht[ATH12K_COUNTER_TYPE_MAX][ATH12K_EHT_MCS_NUM]; u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; @@ -373,36 +642,112 @@ u32 retry_bytes; }; +DECLARE_EWMA(avg_rssi, 10, 8) + struct ath12k_wbm_tx_stats { u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; }; -struct ath12k_sta { - struct ath12k_vif *arvif; +struct ath12k_driver_tx_pkts_flow { + atomic_t pkts_in; + atomic_t pkts_out; +}; + +struct ath12k_driver_rx_pkts_flow { + atomic_t pkts_frm_hw; + atomic_t pkts_out; +}; + +struct ath12k_link_sta { + struct ath12k_link_vif *arvif; + struct ath12k_sta *ahsta; + /* link address similar to ieee80211_link_sta */ + u8 addr[ETH_ALEN]; /* the following are protected by ar->data_lock */ u32 changed; /* IEEE80211_RC_* */ u32 bw; u32 nss; u32 smps; - enum hal_pn_type pn_type; struct work_struct update_wk; struct rate_info txrate; + u32 peer_nss; struct rate_info last_txrate; u64 rx_duration; u64 tx_duration; u8 rssi_comb; + struct ewma_avg_rssi avg_rssi; + + struct ath12k_htt_tx_stats *tx_stats; struct ath12k_rx_peer_stats *rx_stats; + struct ath12k_driver_tx_pkts_flow drv_tx_pkts; + struct ath12k_driver_rx_pkts_flow drv_rx_pkts; struct ath12k_wbm_tx_stats *wbm_tx_stats; u32 bw_prev; + + u16 tcl_metadata; + u8 link_id; /* IEEE link id */ + u8 link_idx; /* for fw use only */ + u32 last_tx_pkt_bw; + + /* For now the assoc link will be considered primary */ + bool is_assoc_link; + + /* For check disable fixed rate check for peer */ + bool disable_fixed_rate; + u8 sawf_svc_id; + /* will be saved to use during recovery */ + struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; + enum ieee80211_sta_state state; +}; + +struct ath12k_sta { + struct ath12k_vif *ahvif; + #ifdef CONFIG_MAC80211_DEBUGFS + /* protected by conf_mutex */ + bool aggr_mode; + #endif + bool use_4addr_set; + struct work_struct set_4addr_wk; + enum hal_pn_type pn_type; + + struct ath12k_link_sta deflink; + struct ath12k_link_sta *link[IEEE80211_MLD_MAX_NUM_LINKS]; + /* indicates bitmap of link sta created in FW */ + unsigned long links_map; + u16 ml_peer_id; + u8 assoc_link_id; + u8 primary_link_id; + u8 num_peer; + /* Indicates whether disassoc is sent after recovery + * ONLY used currently in recovery case + */ + bool low_ack_sent; }; -#define ATH12K_MIN_5G_FREQ 4150 -#define ATH12K_MIN_6G_FREQ 5945 -#define ATH12K_MAX_6G_FREQ 7115 -#define ATH12K_NUM_CHANS 100 -#define ATH12K_MAX_5G_CHAN 173 +#define ATH12K_HALF_20MHZ_BW 10 +#define ATH12K_2G_MIN_CENTER 2412 +#define ATH12K_2G_MAX_CENTER 2484 +#define ATH12K_5G_MIN_CENTER 4900 +#define ATH12K_5G_MAX_CENTER 5920 +#define ATH12K_6G_MIN_CENTER 5935 +#define ATH12K_6G_MAX_CENTER 7115 +#define ATH12K_MIN_2G_FREQ (ATH12K_2G_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1) +#define ATH12K_MAX_2G_FREQ (ATH12K_2G_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1) +#define ATH12K_MIN_5G_FREQ (ATH12K_5G_MIN_CENTER - ATH12K_HALF_20MHZ_BW) +#define ATH12K_MAX_5G_FREQ (ATH12K_5G_MAX_CENTER + ATH12K_HALF_20MHZ_BW) +#define ATH12K_MIN_6G_FREQ (ATH12K_6G_MIN_CENTER - ATH12K_HALF_20MHZ_BW) +#define ATH12K_MAX_6G_FREQ (ATH12K_6G_MAX_CENTER + ATH12K_HALF_20MHZ_BW) + +#define ATH12K_MAX_5G_LOW_BAND_FREQ 5330 +#define ATH12K_MIN_5G_HIGH_BAND_FREQ 5490 + +#define ATH12K_NUM_CHANS 102 +#define ATH12K_MIN_5G_CHAN 36 +#define ATH12K_MAX_5G_CHAN 177 +#define ATH12K_MIN_2G_CHAN 1 +#define ATH12K_MAX_2G_CHAN 11 enum ath12k_state { ATH12K_STATE_OFF, @@ -410,20 +755,69 @@ ATH12K_STATE_RESTARTING, ATH12K_STATE_RESTARTED, ATH12K_STATE_WEDGED, + ATH12K_STATE_TM, /* Add other states as required */ }; /* Antenna noise floor */ #define ATH12K_DEFAULT_NOISE_FLOOR -95 +struct ath12k_ftm_event_obj { + u32 data_pos; + u32 expected_seq; + u8 *eventdata; +}; + struct ath12k_fw_stats { + struct dentry *debugfs_fwstats; u32 pdev_id; u32 stats_id; struct list_head pdevs; struct list_head vdevs; struct list_head bcn; + bool en_vdev_stats_ol; }; +struct ath12k_dbg_htt_stats { + u32 type; + u32 cfg_param[4]; + u8 reset; + struct debug_htt_stats_req *stats_req; + /* protects shared stats req buffer */ + spinlock_t lock; +}; + +#define ATH12K_MAX_COEX_PRIORITY_LEVEL 3 + +struct ath12k_debug { + struct dentry *debugfs_pdev; + struct ath12k_dbg_htt_stats htt_stats; + u32 extd_tx_stats; + u32 extd_rx_stats; +#ifdef CONFIG_ATH12K_SAWF + u32 sawf_stats; +#endif + u32 pktlog_filter; + u32 pktlog_mode; + u32 pktlog_peer_valid; + u8 pktlog_peer_addr[ETH_ALEN]; +#ifdef CONFIG_ATH12K_PKTLOG + struct dentry *debugfs_pktlog; + struct ath12k_pktlog pktlog; + bool is_pkt_logging; +#endif + u32 rx_filter; + struct list_head wmi_list; + struct completion wmi_ctrl_path_stats_rcvd; + u32 wmi_ctrl_path_stats_tagid; + struct dentry *debugfs_nrp; + u32 coex_priority_level[ATH12K_MAX_COEX_PRIORITY_LEVEL]; +}; + +int ath12k_pktlog_rx_filter_setting(struct ath12k *ar, + struct htt_rx_ring_tlv_filter + *tlv_filter); + struct ath12k_per_peer_tx_stats { u32 succ_bytes; u32 retry_bytes; @@ -441,17 +835,73 @@ bool is_ampdu; }; +struct ath12k_btcoex_info { + bool coex_support; + u32 pta_num; + u32 coex_mode; + u32 bt_active_time_slot; + u32 bt_priority_time_slot; + u32 coex_algo_type; + u32 pta_priority; + u32 pta_algorithm; + u32 wlan_prio_mask; + u32 wlan_weight; + u32 bt_weight; + u32 duty_cycle; + u32 wlan_duration; + u32 wlan_pkt_type; + u32 wlan_pkt_type_continued; +}; + +enum btcoex_algo { + COEX_ALGO_UNCONS_FREERUN = 0, + COEX_ALGO_FREERUN, + COEX_ALGO_OCS, + COEX_ALGO_MAX_SUPPORTED, +}; + +enum ath12k_ap_ps_state { + ATH12K_AP_PS_STATE_OFF, + ATH12K_AP_PS_STATE_ON, +}; + +enum ath12k_fw_recovery_option { + ATH12K_FW_RECOVERY_DISABLE = 0, + ATH12K_FW_RECOVERY_ENABLE_AUTO, /* Automatically recover after FW assert */ + ATH12K_FW_RECOVERY_ENABLE_MODE1_AUTO, /* Automatically recover after FW assert through Mode1 */ + /* Enable only recovery. Send MPD SSR WMI */ + /* command to unlink UserPD assert from RootPD */ + ATH12K_FW_RECOVERY_ENABLE_SSR_ONLY, +}; + +struct ath12k_chan_info { + u32 low_freq; + u32 high_freq; + u32 num_channels; +}; + +struct ath12k_wmm_stats { + int tx_type; + int rx_type; + u64 total_wmm_tx_pkts[WME_NUM_AC]; + u64 total_wmm_rx_pkts[WME_NUM_AC]; + u64 total_wmm_tx_drop[WME_NUM_AC]; + u64 total_wmm_rx_drop[WME_NUM_AC]; +}; + +#define ATH12K_DSCP_PRIORITY 7 + #define ATH12K_FLUSH_TIMEOUT (5 * HZ) #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) struct ath12k { struct ath12k_base *ab; + struct ath12k_hw *ah; struct ath12k_pdev *pdev; - struct ieee80211_hw *hw; - struct ieee80211_ops *ops; struct ath12k_wmi_pdev *wmi; struct ath12k_pdev_dp dp; u8 mac_addr[ETH_ALEN]; + struct ath12k_chan_info chan_info; u32 ht_cap_info; u32 vht_cap_info; struct ath12k_he ar_he; @@ -467,6 +917,7 @@ int vdev_id; int roc_freq; bool roc_notify; + struct work_struct vdev_del_wk; } scan; struct { @@ -482,6 +933,7 @@ u32 max_tx_power; u32 txpower_limit_2g; u32 txpower_limit_5g; + u32 txpower_limit_6g; u32 txpower_scale; u32 power_scale; u32 chan_tx_pwr; @@ -512,6 +964,8 @@ /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ u8 pdev_idx; u8 lmac_id; + /* link_idx unique across the group of hw used to lookup in ah */ + u8 link_idx; struct completion peer_assoc_done; struct completion peer_delete_done; @@ -522,6 +976,7 @@ int last_wmi_vdev_start_status; struct completion vdev_setup_done; struct completion vdev_delete_done; + struct ath12k_wmm_stats wmm_stats; int num_peers; int max_num_peers; @@ -532,7 +987,9 @@ struct idr txmgmt_idr; /* protects txmgmt_idr data */ spinlock_t txmgmt_idr_lock; + atomic_t flush_request; atomic_t num_pending_mgmt_tx; + wait_queue_head_t tx_empty_waitq; /* cycle count is reported twice for each visited channel during scan. * access protected by data_lock @@ -562,12 +1019,93 @@ struct ath12k_per_peer_tx_stats cached_stats; u32 last_ppdu_id; u32 cached_ppdu_id; - +#ifdef CONFIG_ATH12K_DEBUGFS + struct ath12k_debug debug; + struct dentry *wmi_ctrl_stat; + /* To protect wmi_list manipulation */ + struct mutex wmi_ctrl_path_stats_lock; + /* TODO: Add mac_filter, ampdu_aggr_size and wbm_tx_completion_stats stats*/ +#endif + struct ath12k_btcoex_info coex; + +#ifdef CONFIG_ATH12K_SPECTRAL + struct ath12k_spectral spectral; +#endif bool dfs_block_radar_events; - bool monitor_conf_enabled; - bool monitor_vdev_created; - bool monitor_started; + struct ath12k_thermal thermal; int monitor_vdev_id; + u8 twt_enabled; + s8 max_allowed_tx_power; + struct completion fw_mode_reset; + u8 ftm_msgref; + bool ap_ps_enabled; + enum ath12k_ap_ps_state ap_ps_state; + + struct cfg80211_chan_def awgn_chandef; + u32 chan_bw_interference_bitmap; + bool awgn_intf_handling_in_prog; + + struct wmi_rssi_dbm_conv_offsets rssi_offsets; + + u8 tpc_stats_type; + /* tpc_stats ptr is protected by data lock */ + struct wmi_tpc_stats_event *tpc_stats; + struct completion tpc_complete; + bool tpc_request; + + struct completion mlo_setup_done; + u32 mlo_setup_status; + + struct ath12k_fw_stats fw_stats; + struct completion fw_stats_complete; + bool fw_stats_done; + + unsigned long last_tx_power_update; + + struct completion mvr_complete; + struct cfg80211_chan_def agile_chandef; + struct ath12k_mgmt_rx_reo_pdev_info rx_reo_pdev_ctx; + + u64 delta_tsf2; + u64 delta_tqm; + + bool mlo_complete_event; + + bool ani_enabled; + u32 ani_poll_period; + u32 ani_listen_period; + int ani_ofdm_level; + struct completion ani_ofdm_event; +}; + +struct ath12k_hw { + struct ieee80211_hw *hw; + const struct ieee80211_ops *ops; + struct ath12k_hw_group *ag; + + /* To synchronize concurrent synchronous mac80211 callback operations, + * concurrent debugfs configuration and concurrent FW statistics events. + */ + struct mutex conf_mutex; + bool regd_updated; + u8 supported_band_mask; + u8 num_radio; + DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS); + + /* Used for protecting objects used at ah level, ex. ath12k_ml_peer */ + spinlock_t data_lock; + + /* protected by ah->data_lock */ + struct list_head ml_peers; + bool in_recovery; + struct ath12k radio[0] __aligned(sizeof(void *)); +}; + +struct ath12k_mlo_memory { + struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; + struct reserved_mem *rsv; + bool init_done; + bool is_mlo_mem_avail; }; struct ath12k_band_cap { @@ -579,6 +1117,14 @@ u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; struct ath12k_wmi_ppe_threshold_arg he_ppet; u16 he_6ghz_capa; + u32 eht_cap_mac_info[PSOC_HOST_MAX_MAC_SIZE]; + u32 eht_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; + u32 eht_mcs_20_only; + u32 eht_mcs_80; + u32 eht_mcs_160; + u32 eht_mcs_320; + struct ath12k_ppe_threshold eht_ppet; + u32 eht_cap_info_internal; }; struct ath12k_pdev_cap { @@ -591,7 +1137,14 @@ u32 rx_chain_mask; u32 tx_chain_mask_shift; u32 rx_chain_mask_shift; + u32 chainmask_table_id; + unsigned long adfs_chain_mask; struct ath12k_band_cap band[NUM_NL80211_BANDS]; + bool nss_ratio_enabled; + u8 nss_ratio_info; + u32 ru_punct_supp_bw; + u32 eml_cap; + u32 mld_cap; }; struct mlo_timestamp { @@ -607,21 +1160,70 @@ struct ath12k_pdev { struct ath12k *ar; - u32 pdev_id; + u16 pdev_id; + u16 hw_link_id; struct ath12k_pdev_cap cap; u8 mac_addr[ETH_ALEN]; struct mlo_timestamp timestamp; }; +struct pmm_remap { + u32 base; + u32 size; +}; + +struct cmem_remap { + u32 base; + u32 size; +}; + +#define BOARD_NAME_SIZE 100 + struct ath12k_board_data { const struct firmware *fw; const void *data; size_t len; + char boardname[BOARD_NAME_SIZE]; + u32 ie_id; + u32 name_id; + u32 data_id; +}; + +struct ath12k_bp_stats { + /* Head Pointer reported by the last HTT Backpressure event for the ring */ + u16 hp; + + /* Tail Pointer reported by the last HTT Backpressure event for the ring */ + u16 tp; + + /* Number of Backpressure events received for the ring */ + u32 count; + + /* Last recorded event timestamp */ + unsigned long jiffies; +}; + +struct ath12k_dp_ring_bp_stats { + struct ath12k_bp_stats umac_ring_bp_stats[HTT_SW_UMAC_RING_IDX_MAX]; + struct ath12k_bp_stats lmac_ring_bp_stats[HTT_SW_LMAC_RING_IDX_MAX][MAX_RADIOS]; +}; + +struct ath12k_bus_params { + bool fixed_bdf_addr; + bool fixed_mem_region; }; struct ath12k_soc_dp_tx_err_stats { /* TCL Ring Descriptor unavailable */ u32 desc_na[DP_TCL_NUM_RING_MAX]; + /* TCL Ring Buffers unavailable */ + u32 txbuf_na[DP_TCL_NUM_RING_MAX]; + + u32 peers_not_present; + + u32 pdev_threshold_limit; + u32 group_threshold_limit; + /* Other failures during dp_tx due to mem allocation failure * idr unavailable etc. */ @@ -632,28 +1234,209 @@ u32 err_ring_pkts; u32 invalid_rbm; u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; + u32 rxdma_error_drop[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; + u32 reo_error_drop[HAL_REO_DEST_RING_ERROR_CODE_MAX]; u32 hal_reo_error[DP_REO_DST_RING_MAX]; + u32 mon_drop_desc; + u32 hal_reo_cmd_drain; + u32 reo_cmd_cache_error; + u32 mcast_enqueued; + u32 ucast_enqueued; + u32 mcast_reinject; + u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX]; + u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON]; + u32 fw_tx_status[MAX_FW_TX_STATUS]; + u32 tx_enqueued[MAX_TCL_RING]; + u32 tx_completed[MAX_TCL_RING]; + u32 null_tx_complete[MAX_TCL_RING]; + u32 bond_tx_ucast_enqueued[MAX_TCL_RING]; + u32 bond_tx_mcast_enqueued[MAX_TCL_RING]; + u32 bond_tx_ucast_dropped[MAX_TCL_RING]; + u32 bond_tx_mcast_dropped[MAX_TCL_RING]; + /* Number of frames successfully converted to ucast from mcast */ + u32 bond_mcast2ucast_converted[MAX_TCL_RING]; + /* Number of mcast frames tried for ucast conversion*/ + u32 bond_mcast2ucast_tried[MAX_TCL_RING]; + /* Number of times mcast to ucast conversion failed*/ + u32 bond_mcast2ucast_drop[MAX_TCL_RING]; + u32 reo_rx[DP_REO_DST_RING_MAX] [ATH12K_MAX_SOCS]; + u32 fast_rx[DP_REO_DST_RING_MAX] [ATH12K_MAX_SOCS]; + u32 non_fast_rx[DP_REO_DST_RING_MAX] [ATH12K_MAX_SOCS]; + u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX] [ATH12K_MAX_SOCS]; + struct ath12k_soc_dp_tx_err_stats tx_err; + struct ath12k_dp_ring_bp_stats bp_stats; + u32 reo_cmd_update_rx_queue_error; + u32 first_and_last_msdu_bit_miss; + u32 reo_excep_msdu_buf_type; +}; + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +struct ath12k_ppeds_stats { + u32 tcl_prod_cnt; + u32 tcl_cons_cnt; + u32 reo_prod_cnt; + u32 reo_cons_cnt; + u32 get_tx_desc_cnt; + u32 tx_desc_allocated; + u32 tx_desc_freed; + u32 fw2wbm_pkt_drops; + u32 enable_intr_cnt; + u32 disable_intr_cnt; + u32 release_tx_single_cnt; + u32 release_rx_desc_cnt; + u32 num_rx_desc_freed; + u32 num_rx_desc_realloc; +}; + +struct ath12k_ppeds_napi { + struct napi_struct napi; + struct net_device ndev; +}; +#endif + +struct ath12k_reg_freq { + u32 start_freq; + u32 end_freq; +}; + +struct vendor_info { + enum ath12k_bdf_search bdf_search; + u32 vendor; + u32 device; + u32 subsystem_vendor; + u32 subsystem_device; +}; + +/* Fatal error notification type based on specific platform type */ +enum ath12k_core_crash_type { + /* Fatal error notification unknown or fatal error notification + * is honored. + */ + ATH12K_NO_CRASH, + + /* Fatal error notification from MHI message */ + ATH12K_MHI_CRASH, + + /* Fatal error notification from remoteproc user pd for ahb based + * internal radio + */ + ATH12K_RPROC_USERPD_AHB_CRASH, + + /* Fatal error notification from remoteproc user pd for platform with + * ahb based internal radio and pcic based external radios + */ + ATH12K_RPROC_USERPD_HYBRID_CRASH, + + /* Fatal error notification from remoteproc root pd for ahb based + * internal radio + */ + ATH12K_RPROC_ROOTPD_AHB_CRASH, + + /* Fatal error notification from remoteproc root pd for platform with + * ahb based internal radio and pcic based external radios + */ + ATH12K_RPROC_ROOTPD_HYBRID_CRASH +}; + +enum ath12k_mlo_recovery_mode { + ATH12K_MLO_RECOVERY_MODE0 = 1, + ATH12K_MLO_RECOVERY_MODE1 = 2, +}; + +struct ath12k_internal_pci { + bool gic_enabled; + wait_queue_head_t gic_msi_waitq; + u32 dp_msi_data[ATH12K_QCN6432_EXT_IRQ_GRP_NUM_MAX]; + u32 ce_msi_data[ATH12K_QCN6432_CE_COUNT]; + u32 dp_irq_num[ATH12K_QCN6432_EXT_IRQ_GRP_NUM_MAX]; +}; + +struct ath12k_mlo_dp_umac_reset { + atomic_t response_chip; + spinlock_t lock; + u8 umac_reset_info; + u8 initiator_chip; + u8 is_intr_bkup; + struct ath12k_hw_ring_mask intr_bkup; +}; + +#define ATH12K_UMAC_RESET_IPC 451 +#define ATH12K_IS_UMAC_RESET_IN_PROGRESS BIT(0) + +/* Holds info on the group of SOCs that are registered as a single wiphy + * or single SOC where each radio registered as separate wiphy in non-MLO + */ +struct ath12k_hw_group { + /* Keep this always as first member */ + struct list_head list; + u8 id; + u8 num_chip; + u8 num_probed; + u8 num_started; + u8 num_hw; + bool mlo_capable; + bool hw_queues_stopped; + bool mgmt_rx_reorder; + unsigned long dev_flags; + enum ath12k_mlo_recovery_mode recovery_mode; + enum ath12k_core_crash_type crash_type; + struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO]; + struct ath12k_base *ab[ATH12K_MAX_SOCS]; + struct ath12k __rcu *hw_links[ATH12K_GROUP_MAX_RADIO]; + struct ath12k_mlo_memory mlo_mem; + struct mutex mutex_lock; + struct ath12k_mgmt_rx_reo_context rx_reo; + struct ath12k_host_mlo_mem_arena mlomem_arena; + atomic_t num_dp_tx_pending; + u64 mlo_tstamp_offset; + struct work_struct reset_work; + struct work_struct recovery_work; + struct ath12k_mlo_dp_umac_reset mlo_umac_reset; + struct completion umac_reset_complete; + bool trigger_umac_reset; +}; + +struct ath12k_bid_override { + unsigned int domain; + unsigned int bus_nr; + unsigned int slot; + unsigned int func; + u16 board_id; + struct list_head next; }; /* Master structure to hold the hw data which may be used in core module */ struct ath12k_base { enum ath12k_hw_rev hw_rev; + enum ath12k_firmware_mode fw_mode; struct platform_device *pdev; struct device *dev; + struct ath12k_hw_group *ag; struct ath12k_qmi qmi; struct ath12k_wmi_base wmi_ab; struct completion fw_ready; int num_radios; + u8 chip_id; /* HW channel counters frequency value in hertz common to all MACs */ u32 cc_freq_hz; + struct list_head board_id_overrides; struct ath12k_htc htc; struct ath12k_dp dp; void __iomem *mem; + void __iomem *mem_ce; + void __iomem *mem_cmem; + void __iomem *mem_pmm; + u32 ce_remap_base_addr; + u32 cmem_remap_base_addr; + u32 pmm_remap_base_addr; + bool ce_remap; + bool cmem_remap; + bool pmm_remap; unsigned long mem_len; struct { @@ -673,13 +1456,25 @@ struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; unsigned long long free_vdev_map; unsigned long long free_vdev_stats_id_map; + + /* To synchronize rhash tbl write operation */ + struct mutex tbl_mtx_lock; + + /* The rhashtable containing struct ath12k_peer keyed by mac addr */ + struct rhashtable *rhead_peer_addr; + struct rhashtable_params rhash_peer_addr_param; + + /* The rhashtable containing struct ath12k_peer keyed by id */ + struct rhashtable *rhead_peer_id; + struct rhashtable_params rhash_peer_id_param; + struct list_head peers; wait_queue_head_t peer_mapping_wq; u8 mac_addr[ETH_ALEN]; bool wmi_ready; u32 wlan_init_status; int irq_num[ATH12K_IRQ_NUM_MAX]; - struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; + struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; struct napi_struct *napi; struct ath12k_wmi_target_cap_arg target_caps; u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; @@ -687,6 +1482,8 @@ int bd_api; const struct ath12k_hw_params *hw_params; + struct ath12k_bus_params bus_params; + bool is_qdss_tracing; const struct firmware *cal_file; @@ -698,10 +1495,20 @@ /* This regd is set during dynamic country setting * This may or may not be used during the runtime */ + bool regd_change_user_request[MAX_RADIOS]; struct ieee80211_regdomain *new_regd[MAX_RADIOS]; /* Current DFS Regulatory */ enum ath12k_dfs_region dfs_region; + struct ath12k_reg_freq reg_freq_2g; + struct ath12k_reg_freq reg_freq_5g; + struct ath12k_reg_freq reg_freq_6g; +#ifdef CONFIG_ATH12K_DEBUGFS + struct dentry *debugfs_soc; +#endif + struct list_head neighbor_peers; + int num_nrps; + struct ath12k_soc_dp_stats soc_stats; unsigned long dev_flags; @@ -710,20 +1517,35 @@ struct work_struct restart_work; struct workqueue_struct *workqueue_aux; struct work_struct reset_work; - atomic_t reset_count; + struct work_struct recovery_work; atomic_t recovery_count; - atomic_t recovery_start_count; + atomic_t reset_count; bool is_reset; struct completion reset_complete; + wait_queue_head_t ssr_dump_wq; + bool collect_dump; + struct notifier_block ssr_nb; + struct notifier_block atomic_ssr_nb; + struct notifier_block rpd_ssr_nb; + struct notifier_block rpd_atomic_ssr_nb; + void *ssr_upd_handle; + void *ssr_txt_handle; + void *ssr_rpd_handle; + void *ssr_atomic_rpd_handle; + void *ssr_atomic_txt_handle; + void *ssr_atomic_upd_handle; struct completion reconfigure_complete; - struct completion recovery_start; + unsigned long reset_fail_timeout; /* continuous recovery fail count */ atomic_t fail_cont_count; - unsigned long reset_fail_timeout; + u32 recovery_start_time; struct { /* protected by data_lock */ u32 fw_crash_counter; + u32 last_recovery_time; } stats; + bool ftm_segment_handler; + struct ath12k_ftm_event_obj ftm_event_obj; u32 pktlog_defs_checksum; struct ath12k_dbring_cap *db_caps; @@ -733,35 +1555,247 @@ struct completion htc_suspend; + enum ath12k_fw_recovery_option fw_recovery_support; + + u32 fw_dbglog_param; + u64 fw_dbglog_val; + u64 fw_soc_drop_count; bool static_window_map; + struct completion rddm_reset_done; + + struct device_node *hremote_node; + u32 host_ddr_fixed_mem_off; + bool stats_disable; + u32 rx_hash_ix2; + u32 rx_hash_ix3; + + struct vendor_info id; + u32 max_msduq_per_tid; + u32 default_msduq_per_tid; + bool in_panic; + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ppe_ds_wlan_handle_t *ppeds_handle; + /* used for per node enumeration*/ + int ppeds_node_idx; + int ppe_vp_tbl_registered[PPE_VP_ENTRIES_MAX]; + int ppe_vp_search_idx_tbl_set[PPE_VP_ENTRIES_MAX]; + struct ath12k_ppeds_napi ppeds_napi_ctxt; + struct mutex ppe_vp_tbl_lock; + u8 num_ppe_vp_profiles; + u8 num_ppe_vp_search_idx_entries; + u8 num_ppe_vp_entries; + u8 ppeds_int_mode_enabled; + u8 ppeds_stopped; + struct ath12k_ppeds_stats ppeds_stats; + u16 *ppeds_rx_idx[ATH12K_MAX_SOCS]; + u16 ppeds_rx_num_elem; +#endif + + int userpd_id; + struct { + const struct ath12k_msi_config *config; + u32 ep_base_data; + u32 irqs[32]; + u32 addr_lo; + u32 addr_hi; + } msi; + + struct ath12k_internal_pci ipci; + u32 chwidth_num_peer_caps; + struct ath12k_dp_umac_reset dp_umac_reset; + + u32 *crash_info_address; + u32 *recovery_mode_address; + + /* to identify multipd_architecture */ + bool multi_pd_arch; + /* Mode1 specific flag to identify recovering pdev */ + bool recovery_start; + bool fw_cfg_support; + bool ce_pipe_init_done; + bool rxgainlut_support; /* must be last */ u8 drv_priv[] __aligned(sizeof(void *)); }; +struct ath12k_fw_stats_pdev { + struct list_head list; + + /* PDEV stats */ + s32 ch_noise_floor; + /* Cycles spent transmitting frames */ + u32 tx_frame_count; + /* Cycles spent receiving frames */ + u32 rx_frame_count; + /* Total channel busy time, evidently */ + u32 rx_clear_count; + /* Total on-channel time */ + u32 cycle_count; + u32 phy_err_count; + u32 chan_tx_power; + u32 ack_rx_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 no_beacons; + u32 mib_int_count; + + /* PDEV TX stats */ + /* Num HTT cookies queued to dispatch list */ + s32 comp_queued; + /* Num HTT cookies dispatched */ + s32 comp_delivered; + /* Num MSDU queued to WAL */ + s32 msdu_enqued; + /* Num MPDU queue to WAL */ + s32 mpdu_enqued; + /* Num MSDUs dropped by WMM limit */ + s32 wmm_drop; + /* Num Local frames queued */ + s32 local_enqued; + /* Num Local frames done */ + s32 local_freed; + /* Num queued to HW */ + s32 hw_queued; + /* Num PPDU reaped from HW */ + s32 hw_reaped; + /* Num underruns */ + s32 underrun; + /* Num PPDUs cleaned up in TX abort */ + s32 tx_abort; + /* Num MPDUs requeued by SW */ + s32 mpdus_requed; + /* excessive retries */ + u32 tx_ko; + /* data hw rate code */ + u32 data_rc; + /* Scheduler self triggers */ + u32 self_triggers; + /* frames dropped due to excessive sw retries */ + u32 sw_retry_failure; + /* illegal rate phy errors */ + u32 illgl_rate_phy_err; + /* wal pdev continuous xretry */ + u32 pdev_cont_xretry; + /* wal pdev tx timeouts */ + u32 pdev_tx_timeout; + /* wal pdev resets */ + u32 pdev_resets; + /* frames dropped due to non-availability of stateless TIDs */ + u32 stateless_tid_alloc_failure; + /* PhY/BB underrun */ + u32 phy_underrun; + /* MPDU is more than txop limit */ + u32 txop_ovf; + + /* PDEV RX stats */ + /* Cnts any change in ring routing mid-ppdu */ + s32 mid_ppdu_route_change; + /* Total number of statuses processed */ + s32 status_rcvd; + /* Extra frags on rings 0-3 */ + s32 r0_frags; + s32 r1_frags; + s32 r2_frags; + s32 r3_frags; + /* MSDUs / MPDUs delivered to HTT */ + s32 htt_msdus; + s32 htt_mpdus; + /* MSDUs / MPDUs delivered to local stack */ + s32 loc_msdus; + s32 loc_mpdus; + /* AMSDUs that have more MSDUs than the status ring size */ + s32 oversize_amsdu; + /* Number of PHY errors */ + s32 phy_errs; + /* Number of PHY errors drops */ + s32 phy_err_drop; + /* Number of mpdu errors - FCS, MIC, ENC etc. */ + s32 mpdu_errs; +}; + +struct ath12k_fw_stats_vdev { + struct list_head list; + + u32 vdev_id; + u32 beacon_snr; + u32 data_snr; + u32 num_tx_frames[WLAN_MAX_AC]; + u32 num_rx_frames; + u32 num_tx_frames_retries[WLAN_MAX_AC]; + u32 num_tx_frames_failures[WLAN_MAX_AC]; + u32 num_rts_fail; + u32 num_rts_success; + u32 num_rx_err; + u32 num_rx_discard; + u32 num_tx_not_acked; + u32 tx_rate_history[MAX_TX_RATE_VALUES]; + u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; +}; + +struct ath12k_fw_stats_bcn { + struct list_head list; + + u32 vdev_id; + u32 tx_bcn_succ_cnt; + u32 tx_bcn_outage_cnt; +}; + int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); int ath12k_core_pre_init(struct ath12k_base *ab); int ath12k_core_init(struct ath12k_base *ath12k); void ath12k_core_deinit(struct ath12k_base *ath12k); struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, - enum ath12k_bus bus); + enum ath12k_bus bus, + const struct ath12k_bus_params *bus_params); void ath12k_core_free(struct ath12k_base *ath12k); int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, struct ath12k_board_data *bd, char *filename); int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, struct ath12k_board_data *bd); +int ath12k_core_fetch_regdb(struct ath12k_base *ath12k, + struct ath12k_board_data *bd); +int ath12k_core_fetch_fw_cfg(struct ath12k_base *ath12k, + struct ath12k_board_data *bd); +int ath12k_core_fetch_rxgainlut(struct ath12k_base *ath12k, + struct ath12k_board_data *bd); void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); int ath12k_core_check_dt(struct ath12k_base *ath12k); void ath12k_core_halt(struct ath12k *ar); int ath12k_core_resume(struct ath12k_base *ab); int ath12k_core_suspend(struct ath12k_base *ab); +int ath12k_config_qdss(struct ath12k_base *ab); + +void ath12k_core_put_hw_group(struct ath12k_base *ab); const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, const char *filename); +void ath12k_core_wait_dump_collect(struct ath12k_base *ab); +void ath12k_core_issue_bug_on(struct ath12k_base *ab); + +void ath12k_fw_stats_init(struct ath12k *ar); +void ath12k_fw_stats_pdevs_free(struct list_head *head); +void ath12k_fw_stats_bcn_free(struct list_head *head); +void ath12k_fw_stats_reset(struct ath12k *ar); +void ath12k_fw_stats_free(struct ath12k_fw_stats *stats); +#ifdef CONFIG_ATH12K_SAWF +int ath12k_send_sawf_configs_soc(struct ath12k_sawf_svc_params *new_param); +int ath12k_sawf_send_disable_soc(u8 svc_id); +int ath12k_core_sawf_ul_config(struct net_device *dev, struct ath12k_sawf_wmi_peer_latency_param *latency_info); +void *ath12k_get_ab_nd_peer_from_peer_mac(u8 *peer_mac, struct ath12k_base **ab_ref); +#endif /* CONFIG_ATH12K_SAWF */ +void ath12k_dp_umac_reset_handle(struct ath12k_base *ab); +int ath12k_dp_umac_reset_init(struct ath12k_base *ab); +void ath12k_dp_umac_reset_deinit(struct ath12k_base *ab); +void ath12k_umac_reset_completion(struct ath12k_base *ab); +void ath12k_umac_reset_notify_pre_reset_done(struct ath12k_base *ab); + static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) { switch (state) { @@ -791,11 +1825,16 @@ return (struct ath12k_skb_rxcb *)skb->cb; } -static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) +static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif) { return (struct ath12k_vif *)vif->drv_priv; } +static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta) +{ + return (struct ath12k_sta *)sta->drv_priv; +} + static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, int mac_id) { @@ -815,9 +1854,27 @@ switch (bus) { case ATH12K_BUS_PCI: return "pci"; + case ATH12K_BUS_AHB: + return "ahb"; + case ATH12K_BUS_HYBRID: + return "ahb"; } return "unknown"; } +int ath12k_pci_init(void); +void ath12k_pci_exit(void); +#ifdef CONFIG_ATH12K_AHB +int ath12k_ahb_init(void); +void ath12k_ahb_exit(void); +#else +static inline int ath12k_ahb_init(void) +{ + return 0; +}; + +static inline void ath12k_ahb_exit(void) {}; +#endif + #endif /* _CORE_H_ */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dbring.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dbring.c --- linux-6.4/drivers/net/wireless/ath/ath12k/dbring.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dbring.c 2024-01-19 17:01:19.853846702 +0100 @@ -7,6 +7,34 @@ #include "core.h" #include "debug.h" +#define ATH12K_DB_MAGIC_VALUE 0xdeadbeaf + +int ath12k_dbring_validate_buffer(struct ath12k *ar, void *buffer, u32 size) +{ + u32 *temp; + int idx; + size = size >> 2; + + for (idx = 0, temp = buffer; idx < size; idx++, temp++) { + if (*temp == ATH12K_DB_MAGIC_VALUE) + return -EINVAL; + } + + return 0; +} + +static void ath12k_dbring_fill_magic_value(struct ath12k *ar, + void *buffer, u32 size) +{ + /* memset32 function fills buffer payload with the ATH12K_DB_MAGIC_VALUE + * and the variable size is expected to be the number of u32 values + * to be stored, not the number of bytes. + */ + size = size / sizeof(u32); + + memset32(buffer, ATH12K_DB_MAGIC_VALUE, size); +} + static int ath12k_dbring_bufs_replenish(struct ath12k *ar, struct ath12k_dbring *ring, struct ath12k_dbring_element *buff, @@ -28,6 +56,7 @@ ptr_unaligned = buff->payload; ptr_aligned = PTR_ALIGN(ptr_unaligned, ring->buf_align); + ath12k_dbring_fill_magic_value(ar, ptr_aligned, ring->buf_sz); paddr = dma_map_single(ab->dev, ptr_aligned, ring->buf_sz, DMA_FROM_DEVICE); @@ -51,8 +80,9 @@ buff->paddr = paddr; - cookie = u32_encode_bits(ar->pdev_idx, DP_RXDMA_BUF_COOKIE_PDEV_ID) | - u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID); + dma_sync_single_for_device(ab->dev, paddr, ring->buf_sz, DMA_FROM_DEVICE); + cookie = u32_encode_bits(ar->pdev_idx, DP_DIR_BUF_COOKIE_PDEV_ID) | + u32_encode_bits(buf_id, DP_DIR_BUF_COOKIE_BUF_ID); ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, 0); @@ -178,7 +208,7 @@ ring->hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); ring->tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); - ret = ath12k_dbring_fill_bufs(ar, ring, GFP_KERNEL); + ret = ath12k_dbring_fill_bufs(ar, ring, GFP_ATOMIC); return ret; } @@ -270,6 +300,7 @@ switch (ev->fixed.module_id) { case WMI_DIRECT_BUF_SPECTRAL: + ring = ath12k_spectral_get_dbring(ar); break; default: ring = NULL; @@ -299,7 +330,7 @@ ath12k_hal_rx_buf_addr_info_get(&desc, &paddr, &cookie, &rbm); - buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); + buf_id = u32_get_bits(cookie, DP_DIR_BUF_COOKIE_BUF_ID); spin_lock_bh(&ring->idr_lock); buff = idr_find(&ring->bufs_idr, buf_id); diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dbring.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dbring.h --- linux-6.4/drivers/net/wireless/ath/ath12k/dbring.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dbring.h 2024-01-19 17:01:19.853846702 +0100 @@ -31,6 +31,20 @@ u32 num_meta; }; +struct wmi_pdev_sscan_fw_param_event { + struct ath12k_wmi_pdev_sscan_fw_cmd_fixed_param fixed; + struct ath12k_wmi_pdev_sscan_fft_bin_index *bin; + struct ath12k_wmi_pdev_sscan_chan_info ch_info; + struct ath12k_wmi_pdev_sscan_per_detector_info *det_info; +}; + +struct wmi_spectral_capabilities_event { + struct ath12k_wmi_spectral_scan_bw_capabilities *sscan_bw_caps; + struct ath12k_wmi_spectral_fft_size_capabilities *fft_size_caps; + u32 num_bw_caps_entry; + u32 num_fft_size_caps_entry; +}; + struct ath12k_dbring_cap { u32 pdev_id; enum wmi_direct_buffer_module id; @@ -77,4 +91,5 @@ struct ath12k_dbring_cap *db_cap); void ath12k_dbring_srng_cleanup(struct ath12k *ar, struct ath12k_dbring *ring); void ath12k_dbring_buf_cleanup(struct ath12k *ar, struct ath12k_dbring *ring); +int ath12k_dbring_validate_buffer(struct ath12k *ar, void *data, u32 size); #endif /* ATH12K_DBRING_H */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/debug.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debug.c --- linux-6.4/drivers/net/wireless/ath/ath12k/debug.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debug.c 2024-01-26 16:32:21.055710360 +0100 @@ -4,6 +4,7 @@ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. */ +#define DEBUG #include #include "core.h" #include "debug.h" @@ -17,7 +18,10 @@ va_start(args, fmt); vaf.va = &args; + if (ab) dev_info(ab->dev, "%pV", &vaf); + else + pr_info("ath12k: %pV", &vaf); /* TODO: Trace the log */ va_end(args); } @@ -31,7 +35,10 @@ va_start(args, fmt); vaf.va = &args; + if (ab) dev_err(ab->dev, "%pV", &vaf); + else + pr_err("ath12k: %pV", &vaf); /* TODO: Trace the log */ va_end(args); } @@ -45,7 +52,10 @@ va_start(args, fmt); vaf.va = &args; + if (ab) dev_warn_ratelimited(ab->dev, "%pV", &vaf); + else + pr_warn_ratelimited("ath12k: %pV", &vaf); /* TODO: Trace the log */ va_end(args); } @@ -55,6 +65,10 @@ void __ath12k_dbg(struct ath12k_base *ab, enum ath12k_debug_mask mask, const char *fmt, ...) { +#define LEVEL_MASK GENMASK(31,28) +#define debug_mask GENMASK(27,0) + u32 local_mask_level = mask & LEVEL_MASK; + u32 global_mask_level = ath12k_debug_mask & LEVEL_MASK; struct va_format vaf; va_list args; @@ -63,8 +77,15 @@ vaf.fmt = fmt; vaf.va = &args; - if (ath12k_debug_mask & mask) + if ((mask & debug_mask) & ath12k_debug_mask) { + if (((local_mask_level) && (global_mask_level >= local_mask_level)) || + (!global_mask_level && (local_mask_level == ATH12K_DBG_L0))) { + if (ab) dev_dbg(ab->dev, "%pV", &vaf); + else + pr_devel("ath12k: %pV", &vaf); + } + } /* TODO: trace log */ @@ -99,4 +120,35 @@ } } +void ath12k_err_dump(struct ath12k_base *ab, const char *msg, + const char *prefix, const void *buf, + size_t len, struct hal_srng *srng) +{ + char linebuf[512]; + size_t linebuflen; + const void *ptr; + + if (msg) + ath12k_err(ab, msg); + + for (ptr = buf; (ptr - buf) < len; ptr += 16) { + linebuflen = 0; + linebuflen += scnprintf(linebuf + linebuflen, + sizeof(linebuf) - linebuflen, + "%s%08x: ", + (prefix ? prefix : ""), + (unsigned int)(ptr - buf)); + hex_dump_to_buffer(ptr, len - (ptr - buf), 16, 1, + linebuf + linebuflen, + sizeof(linebuf) - linebuflen, true); + dev_err(ab->dev, "%s\n", linebuf); + } + + if (srng && srng->ring_dir == HAL_SRNG_DIR_DST) + dev_err(ab->dev, "ring_base_vaddr=%px tp=0x%X size=0x%X cached_hp=0x%X", + srng->ring_base_vaddr, + srng->u.dst_ring.tp, + srng->ring_size, + srng->u.dst_ring.cached_hp); +} #endif /* CONFIG_ATH12K_DEBUG */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/debug.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debug.h --- linux-6.4/drivers/net/wireless/ath/ath12k/debug.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debug.h 2024-01-19 17:01:19.853846702 +0100 @@ -8,6 +8,7 @@ #define _ATH12K_DEBUG_H_ #include "trace.h" +#include "debugfs.h" enum ath12k_debug_mask { ATH12K_DBG_AHB = 0x00000001, @@ -25,14 +26,32 @@ ATH12K_DBG_PCI = 0x00001000, ATH12K_DBG_DP_TX = 0x00002000, ATH12K_DBG_DP_RX = 0x00004000, + ATH12K_DBG_OFFSET = 0x00008000, + ATH12K_DBG_RX_REO = 0x00010000, + ATH12K_DBG_PEER = 0x00020000, + + /* keep last*/ + ATH12K_DBG_SAWF = 0x00040000, + ATH12K_DBG_PPE = 0x00080000, + ATH12K_DBG_DP_UMAC_RESET = 0x00100000, + ATH12K_DBG_MODE1_RECOVERY = 0x00200000, ATH12K_DBG_ANY = 0xffffffff, }; +enum ath12k_debug_mask_level { + ATH12K_DBG_L0 = 0x00000000, + ATH12K_DBG_L1 = 0x10000000, + ATH12K_DBG_L2 = 0x20000000, + ATH12K_DBG_L3 = 0x30000000, +}; + __printf(2, 3) void ath12k_info(struct ath12k_base *ab, const char *fmt, ...); __printf(2, 3) void ath12k_err(struct ath12k_base *ab, const char *fmt, ...); __printf(2, 3) void ath12k_warn(struct ath12k_base *ab, const char *fmt, ...); extern unsigned int ath12k_debug_mask; +extern unsigned int ath12k_ftm_mode; +extern bool ath12k_en_shutdown; #ifdef CONFIG_ATH12K_DEBUG __printf(3, 4) void __ath12k_dbg(struct ath12k_base *ab, @@ -42,6 +61,9 @@ enum ath12k_debug_mask mask, const char *msg, const char *prefix, const void *buf, size_t len); +void ath12k_err_dump(struct ath12k_base *ab, const char *msg, + const char *prefix, const void *buf, + size_t len, struct hal_srng *srng); #else /* CONFIG_ATH12K_DEBUG */ static inline void __ath12k_dbg(struct ath12k_base *ab, enum ath12k_debug_mask dbg_mask, @@ -55,8 +77,16 @@ const void *buf, size_t len) { } + +static inline void ath12k_err_dump(struct ath12k_base *ab, const char *msg, + const char *prefix, const void *buf, + size_t len, struct hal_srng *srng) +{ +} #endif /* CONFIG_ATH12K_DEBUG */ +#define ATH12K_DBG_SET(mask, level) ATH12K_DBG_##mask | ATH12K_DBG_##level + #define ath12k_dbg(ar, dbg_mask, fmt, ...) \ do { \ typeof(dbg_mask) mask = (dbg_mask); \ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp.c --- linux-6.4/drivers/net/wireless/ath/ath12k/dp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp.c 2024-03-18 14:40:14.847741224 +0100 @@ -13,6 +13,17 @@ #include "dp_rx.h" #include "peer.h" #include "dp_mon.h" +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#include "ppe.h" +#endif + +#define ATH12K_DP_LMAC_PEER_ID_LEGACY 2 +#define ATH12K_DP_LMAC_PEER_ID_MLO 3 +#define ATH12K_DP_PEER_ROUTING_LMAC_ID_MASK GENMASK(7,6) + +#ifdef CONFIG_MAC80211_BONDED_SUPPORT +extern int g_bonded_interface_model; +#endif static void ath12k_dp_htt_htc_tx_complete(struct ath12k_base *ab, struct sk_buff *skb) @@ -36,63 +47,118 @@ return; } + if (!peer->primary_link) { + spin_unlock_bh(&ab->base_lock); + return; + } + ath12k_dp_rx_peer_tid_cleanup(ar, peer); crypto_free_shash(peer->tfm_mmic); + peer->dp_setup_done = false; spin_unlock_bh(&ab->base_lock); } -int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr) +int ath12k_dp_peer_default_route_setup(struct ath12k *ar, struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) { struct ath12k_base *ab = ar->ab; - struct ath12k_peer *peer; - u32 reo_dest; - int ret = 0, tid; + struct ieee80211_sta *sta; + u32 reo_dest, param_value; + u32 lmac_peer_routing_id = ATH12K_DP_LMAC_PEER_ID_LEGACY; + int ret; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + struct ath12k_vif *ahvif = arvif->ahvif; +#endif + + sta = container_of((void *)arsta->ahsta, struct ieee80211_sta, drv_priv); /* NOTE: reo_dest ring id starts from 1 unlike mac_id which starts from 0 */ reo_dest = ar->dp.mac_id + 1; - ret = ath12k_wmi_set_peer_param(ar, addr, vdev_id, - WMI_PEER_SET_DEFAULT_ROUTING, - DP_RX_HASH_ENABLE | (reo_dest << 1)); + param_value = (reo_dest << 1 | DP_RX_HASH_ENABLE); + + /* For MLO supported peers and it has multi link capablity, use MLO conf */ + if (hweight16(sta->valid_links) > 1) + lmac_peer_routing_id = ATH12K_DP_LMAC_PEER_ID_MLO; + + param_value |= FIELD_PREP(ATH12K_DP_PEER_ROUTING_LMAC_ID_MASK, + lmac_peer_routing_id); + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, + WMI_PEER_SET_DEFAULT_ROUTING, param_value); if (ret) { ath12k_warn(ab, "failed to set default routing %d peer :%pM vdev_id :%d\n", - ret, addr, vdev_id); + ret, arsta->addr, arvif->vdev_id); return ret; } + ath12k_dbg(ab, ATH12K_DBG_DP_RX, "peer %pM set def route id %d sta_link %d\n", + arsta->addr, lmac_peer_routing_id, + hweight16(sta->valid_links)); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + /* keep last - override any PPE DS specific routing config */ + if ((ahvif->vdev_type == WMI_VDEV_TYPE_AP) && !((ahvif->vdev_type == WMI_VDEV_TYPE_AP) && (ahvif->vdev_subtype == WMI_VDEV_SUBTYPE_MESH_11S))) + ath12k_dp_peer_ppeds_route_setup(ar, arvif, arsta); +#endif + + return 0; +} + +int ath12k_dp_peer_setup(struct ath12k *ar, struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_peer *peer; + struct crypto_shash *tfm; + int ret = 0, tid; + + tfm = crypto_alloc_shash("michael_mic", 0, 0); + if (IS_ERR(tfm)) + return PTR_ERR(tfm); + + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find(ab, arvif->vdev_id, arsta->addr); + if (!peer) { + ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n", + arsta->addr, arvif->vdev_id); + ret = -ENOENT; + goto free_shash; + } + + if (peer->mlo && peer->link_id != arsta->ahsta->primary_link_id) { + ret = 0; + peer->primary_link = false; + goto free_shash; + } + + peer->primary_link = true; + for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { - ret = ath12k_dp_rx_peer_tid_setup(ar, addr, vdev_id, tid, 1, 0, - HAL_PN_TYPE_NONE); + ret = ath12k_dp_rx_peer_tid_setup(ar, tid, 1, 0, HAL_PN_TYPE_NONE, peer); if (ret) { ath12k_warn(ab, "failed to setup rxd tid queue for tid %d: %d\n", tid, ret); - goto peer_clean; + goto peer_tid_clean; } } - ret = ath12k_dp_rx_peer_frag_setup(ar, addr, vdev_id); + ret = ath12k_dp_rx_peer_frag_setup(ar, peer, tfm); if (ret) { ath12k_warn(ab, "failed to setup rx defrag context\n"); - goto peer_clean; + goto peer_tid_clean; } /* TODO: Setup other peer specific resource used in data path */ - return 0; - -peer_clean: - spin_lock_bh(&ab->base_lock); - - peer = ath12k_peer_find(ab, vdev_id, addr); - if (!peer) { - ath12k_warn(ab, "failed to find the peer to del rx tid\n"); spin_unlock_bh(&ab->base_lock); - return -ENOENT; - } - for (; tid >= 0; tid--) + return 0; + +peer_tid_clean: + for (tid--; tid >= 0; tid--) ath12k_dp_rx_peer_tid_delete(ar, peer, tid); +free_shash: + crypto_free_shash(tfm); spin_unlock_bh(&ab->base_lock); return ret; @@ -103,6 +169,9 @@ if (!ring->vaddr_unaligned) return; + if (ring->cached) + kfree(ring->vaddr_unaligned); + else dma_free_coherent(ab->dev, ring->size, ring->vaddr_unaligned, ring->paddr_unaligned); @@ -114,7 +183,7 @@ int ext_group_num; u8 mask = 1 << ring_num; - for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_GRP_NUM_MAX; + for (ext_group_num = 0; ext_group_num < ATH12K_EXT_IRQ_DP_NUM_VECTORS; ext_group_num++) { if (mask & grp_mask[ext_group_num]) return ext_group_num; @@ -123,38 +192,76 @@ return -ENOENT; } +bool ath12k_dp_umac_reset_in_progress(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset = &ag->mlo_umac_reset; + bool umac_in_progress = false; + + if (!ab->hw_params->support_umac_reset) + return umac_in_progress; + + spin_lock_bh(&mlo_umac_reset->lock); + if (mlo_umac_reset->umac_reset_info & + ATH12K_IS_UMAC_RESET_IN_PROGRESS) + umac_in_progress = true; + spin_unlock_bh(&mlo_umac_reset->lock); + + return umac_in_progress; +} + static int ath12k_dp_srng_calculate_msi_group(struct ath12k_base *ab, enum hal_ring_type type, int ring_num) { const u8 *grp_mask; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *umac_reset; + struct ath12k_hw_ring_mask *ring_mask; + + umac_reset = &ag->mlo_umac_reset; + if (ath12k_dp_umac_reset_in_progress(ab) && umac_reset) + ring_mask = &umac_reset->intr_bkup; + else + ring_mask = ab->hw_params->ring_mask; switch (type) { case HAL_WBM2SW_RELEASE: if (ring_num == HAL_WBM2SW_REL_ERR_RING_NUM) { - grp_mask = &ab->hw_params->ring_mask->rx_wbm_rel[0]; + grp_mask = &ring_mask->rx_wbm_rel[0]; ring_num = 0; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + } else if (ring_num == HAL_WBM2SW_PPEDS_TX_CMPLN_RING_NUM) { + grp_mask = &ring_mask->wbm2sw6_ppeds_tx_cmpln[0]; + ring_num = 0; +#endif } else { - grp_mask = &ab->hw_params->ring_mask->tx[0]; + grp_mask = &ring_mask->tx[0]; } break; case HAL_REO_EXCEPTION: - grp_mask = &ab->hw_params->ring_mask->rx_err[0]; + grp_mask = &ring_mask->rx_err[0]; break; case HAL_REO_DST: - grp_mask = &ab->hw_params->ring_mask->rx[0]; + grp_mask = &ring_mask->rx[0]; break; case HAL_REO_STATUS: - grp_mask = &ab->hw_params->ring_mask->reo_status[0]; + grp_mask = &ring_mask->reo_status[0]; break; case HAL_RXDMA_MONITOR_STATUS: case HAL_RXDMA_MONITOR_DST: - grp_mask = &ab->hw_params->ring_mask->rx_mon_dest[0]; + grp_mask = &ring_mask->rx_mon_dest[0]; break; case HAL_TX_MONITOR_DST: - grp_mask = &ab->hw_params->ring_mask->tx_mon_dest[0]; + grp_mask = &ring_mask->tx_mon_dest[0]; break; case HAL_RXDMA_BUF: - grp_mask = &ab->hw_params->ring_mask->host2rxdma[0]; + grp_mask = &ring_mask->host2rxdma[0]; + break; + case HAL_PPE2TCL: + grp_mask = &ring_mask->ppe2tcl[0]; + break; + case HAL_REO2PPE: + grp_mask = &ring_mask->reo2ppe[0]; break; case HAL_RXDMA_MONITOR_BUF: case HAL_TCL_DATA: @@ -181,6 +288,7 @@ int msi_group_number, msi_data_count; u32 msi_data_start, msi_irq_start, addr_lo, addr_hi; int ret; + int vector; ret = ath12k_hif_get_user_msi_vector(ab, "DP", &msi_data_count, &msi_data_start, @@ -209,11 +317,197 @@ ring_params->msi_addr = addr_lo; ring_params->msi_addr |= (dma_addr_t)(((uint64_t)addr_hi) << 32); + if (ab->hif.bus == ATH12K_BUS_HYBRID) + ring_params->msi_data = ab->ipci.dp_msi_data[msi_group_number]; + else ring_params->msi_data = (msi_group_number % msi_data_count) + msi_data_start; ring_params->flags |= HAL_SRNG_FLAGS_MSI_INTR; + + vector = msi_irq_start + (msi_group_number % msi_data_count); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + /* Interrupt will not be freed for non-asserted chips + * during UMAC reset + */ + if (!ath12k_dp_umac_reset_in_progress(ab)) + ath12k_hif_ppeds_register_interrupts(ab, type, vector, ring_num); +#endif +} + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +static int ath12k_dp_srng_alloc(struct ath12k_base *ab, struct dp_srng *ring, + enum hal_ring_type type, int ring_num, + int num_entries) +{ + int entry_sz = ath12k_hal_srng_get_entrysize(ab, type); + int max_entries = ath12k_hal_srng_get_max_entries(ab, type); + bool cached = false; + + if (max_entries < 0 || entry_sz < 0) + return -EINVAL; + + if (num_entries > max_entries) + num_entries = max_entries; + + ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1; + if (ab->hw_params->alloc_cacheable_memory) { + /* Allocate the reo dst and tx completion rings from cacheable memory */ + switch (type) { + case HAL_REO_DST: + case HAL_WBM2SW_RELEASE: + cached = true; + break; + default: + cached = false; + } + + if (cached) { + ring->vaddr_unaligned = kzalloc(ring->size, GFP_KERNEL); + ring->paddr_unaligned = virt_to_phys(ring->vaddr_unaligned); + } + } + if (!cached) + ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size, + &ring->paddr_unaligned, + GFP_KERNEL); + if (!ring->vaddr_unaligned) + return -ENOMEM; + + memset(ring->vaddr_unaligned, 0, ring->size); + ring->vaddr = PTR_ALIGN(ring->vaddr_unaligned, HAL_RING_BASE_ALIGN); + ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr - + (unsigned long)ring->vaddr_unaligned); + + return 0; } +static int ath12k_dp_srng_init_idx(struct ath12k_base *ab, struct dp_srng *ring, + enum hal_ring_type type, int ring_num, + int mac_id, + int num_entries, u32 idx) +{ + struct hal_srng_params params = { 0 }; + bool cached = false; + int ret; + + params.ring_base_vaddr = ring->vaddr; + params.ring_base_paddr = ring->paddr; + params.num_entries = num_entries; + ath12k_dp_srng_msi_setup(ab, ¶ms, type, ring_num + mac_id); + + switch (type) { + case HAL_REO_DST: + case HAL_REO2PPE: + params.intr_batch_cntr_thres_entries = + HAL_SRNG_INT_BATCH_THRESHOLD_RX; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; + break; + case HAL_RXDMA_BUF: + params.intr_batch_cntr_thres_entries = 0; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; + break; + case HAL_RXDMA_MONITOR_BUF: + case HAL_RXDMA_MONITOR_STATUS: + if (type == HAL_RXDMA_MONITOR_BUF) + params.low_threshold = DP_RX_MONITOR_BUF_LOW_TH; + else + params.low_threshold = num_entries >> 3; + + params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; + + params.intr_batch_cntr_thres_entries = 0; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; + break; + case HAL_TX_MONITOR_BUF: + case HAL_TX_MONITOR_DST: + params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3; + params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; + params.intr_batch_cntr_thres_entries = 0; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; + break; + case HAL_WBM2SW_RELEASE: + if (ab->hw_params->hw_ops->dp_srng_is_tx_comp_ring(ring_num)) { + params.intr_batch_cntr_thres_entries = + HAL_SRNG_INT_BATCH_THRESHOLD_TX; + params.intr_timer_thres_us = + HAL_SRNG_INT_TIMER_THRESHOLD_TX; + break; + } + /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */ + fallthrough; + case HAL_REO_EXCEPTION: + case HAL_REO_REINJECT: + case HAL_REO_CMD: + case HAL_REO_STATUS: + case HAL_TCL_DATA: + case HAL_TCL_CMD: + case HAL_TCL_STATUS: + case HAL_WBM_IDLE_LINK: + case HAL_SW2WBM_RELEASE: + case HAL_RXDMA_DST: + case HAL_RXDMA_MONITOR_DST: + params.intr_batch_cntr_thres_entries = + HAL_SRNG_INT_BATCH_THRESHOLD_OTHER; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER; + break; + case HAL_RXDMA_DIR_BUF: + break; + case HAL_PPE2TCL: + params.intr_batch_cntr_thres_entries = + HAL_SRNG_INT_BATCH_THRESHOLD_PPE2TCL; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_PPE2TCL; + break; + default: + ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type); + return -EINVAL; + } + + if (cached) { + params.flags |= HAL_SRNG_FLAGS_CACHED; + ring->cached = 1; + } + + ret = ath12k_hal_srng_setup_idx(ab, type, ring_num, mac_id, ¶ms, idx); + if (ret < 0) { + ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n", + ret, ring_num); + return ret; + } + + ring->ring_id = ret; + + return 0; + +} + +int ath12k_ppeds_dp_srng_alloc(struct ath12k_base *ab, struct dp_srng *ring, + enum hal_ring_type type, int ring_num, + int num_entries) +{ + int ret; + + ret = ath12k_dp_srng_alloc(ab, ring, type, ring_num, num_entries); + if (ret != 0) + ath12k_warn(ab, "Failed to allocate dp srng ring.\n"); + + return 0; +} + +int ath12k_ppeds_dp_srng_init(struct ath12k_base *ab, struct dp_srng *ring, + enum hal_ring_type type, int ring_num, + int mac_id, int num_entries, u32 idx) +{ + int ret; + + ret = ath12k_dp_srng_init_idx(ab, ring, type, ring_num, mac_id, num_entries, idx); + if (ret != 0) + ath12k_warn(ab, "Failed to initialize dp srng ring.\n"); + + return 0; +} +#endif + int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, enum hal_ring_type type, int ring_num, int mac_id, int num_entries) @@ -222,6 +516,7 @@ int entry_sz = ath12k_hal_srng_get_entrysize(ab, type); int max_entries = ath12k_hal_srng_get_max_entries(ab, type); int ret; + bool cached = false; if (max_entries < 0 || entry_sz < 0) return -EINVAL; @@ -230,9 +525,30 @@ num_entries = max_entries; ring->size = (num_entries * entry_sz) + HAL_RING_BASE_ALIGN - 1; + if (ab->hw_params->alloc_cacheable_memory) { + /* Allocate the reo dst and tx completion rings from cacheable memory */ + switch (type) { + case HAL_REO_DST: + case HAL_WBM2SW_RELEASE: + cached = true; + break; + default: + cached = false; + } + } + + if (ath12k_dp_umac_reset_in_progress(ab)) + goto skip_dma_alloc; + + if (cached) { + ring->vaddr_unaligned = kzalloc(ring->size, GFP_KERNEL); + ring->paddr_unaligned = virt_to_phys(ring->vaddr_unaligned); + } else { ring->vaddr_unaligned = dma_alloc_coherent(ab->dev, ring->size, &ring->paddr_unaligned, GFP_KERNEL); + } + if (!ring->vaddr_unaligned) return -ENOMEM; @@ -240,6 +556,8 @@ ring->paddr = ring->paddr_unaligned + ((unsigned long)ring->vaddr - (unsigned long)ring->vaddr_unaligned); +skip_dma_alloc: + memset(ring->vaddr_unaligned, 0, ring->size); params.ring_base_vaddr = ring->vaddr; params.ring_base_paddr = ring->paddr; params.num_entries = num_entries; @@ -247,18 +565,28 @@ switch (type) { case HAL_REO_DST: + case HAL_REO2PPE: params.intr_batch_cntr_thres_entries = HAL_SRNG_INT_BATCH_THRESHOLD_RX; params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; break; case HAL_RXDMA_BUF: + params.intr_batch_cntr_thres_entries = 0; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; + break; case HAL_RXDMA_MONITOR_BUF: case HAL_RXDMA_MONITOR_STATUS: + if (type == HAL_RXDMA_MONITOR_BUF) + params.low_threshold = DP_RX_MONITOR_BUF_LOW_TH; + else params.low_threshold = num_entries >> 3; + params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; + params.intr_batch_cntr_thres_entries = 0; params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_RX; break; + case HAL_TX_MONITOR_BUF: case HAL_TX_MONITOR_DST: params.low_threshold = DP_TX_MONITOR_BUF_SIZE_MAX >> 3; params.flags |= HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN; @@ -272,6 +600,12 @@ params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_TX; break; + } else if (ring_num == HAL_WBM2SW_PPEDS_TX_CMPLN_RING_NUM) { + params.intr_batch_cntr_thres_entries = + HAL_SRNG_INT_BATCH_THRESHOLD_PPE_WBM2SW_REL; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_TX; + + break; } /* follow through when ring_num != HAL_WBM2SW_REL_ERR_RING_NUM */ fallthrough; @@ -286,19 +620,28 @@ case HAL_SW2WBM_RELEASE: case HAL_RXDMA_DST: case HAL_RXDMA_MONITOR_DST: - case HAL_RXDMA_MONITOR_DESC: params.intr_batch_cntr_thres_entries = HAL_SRNG_INT_BATCH_THRESHOLD_OTHER; params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_OTHER; break; case HAL_RXDMA_DIR_BUF: break; + case HAL_PPE2TCL: + params.intr_batch_cntr_thres_entries = + HAL_SRNG_INT_BATCH_THRESHOLD_PPE2TCL; + params.intr_timer_thres_us = HAL_SRNG_INT_TIMER_THRESHOLD_PPE2TCL; + break; default: ath12k_warn(ab, "Not a valid ring type in dp :%d\n", type); return -EINVAL; } - ret = ath12k_hal_srng_setup(ab, type, ring_num, mac_id, ¶ms); + if (cached) { + params.flags |= HAL_SRNG_FLAGS_CACHED; + ring->cached = 1; + } + + ret = ath12k_hal_srng_setup_idx(ab, type, ring_num, mac_id, ¶ms, 0); if (ret < 0) { ath12k_warn(ab, "failed to setup srng: %d ring_id %d\n", ret, ring_num); @@ -311,26 +654,36 @@ } static -u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, struct ath12k_vif *arvif) +u32 ath12k_dp_tx_get_vdev_bank_config(struct ath12k_base *ab, struct ath12k_link_vif *arvif) { + struct ath12k_vif *ahvif = arvif->ahvif; u32 bank_config = 0; + struct ath12k_hw_group *ag = ab->ag; + enum hal_encrypt_type encrypt_type = 0; /* Only valid for raw frames with HW crypto enabled. * With SW crypto, mac80211 sets key per packet */ - if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && - test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ab->dev_flags)) - bank_config |= - u32_encode_bits(ath12k_dp_tx_get_encrypt_type(arvif->key_cipher), + if (ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && + test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ag->dev_flags) && + ahvif->key_cipher != INVALID_CIPHER) + encrypt_type = ath12k_dp_tx_get_encrypt_type(ahvif->key_cipher); + else + encrypt_type = HAL_ENCRYPT_TYPE_OPEN; + + bank_config |= u32_encode_bits(ahvif->tx_encap_type, + HAL_TX_BANK_CONFIG_ENCAP_TYPE) | + u32_encode_bits(encrypt_type, HAL_TX_BANK_CONFIG_ENCRYPT_TYPE); - bank_config |= u32_encode_bits(arvif->tx_encap_type, - HAL_TX_BANK_CONFIG_ENCAP_TYPE); bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP) | u32_encode_bits(0, HAL_TX_BANK_CONFIG_LINK_META_SWAP) | u32_encode_bits(0, HAL_TX_BANK_CONFIG_EPD); /* only valid if idx_lookup_override is not set in tcl_data_cmd */ + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) + bank_config |= u32_encode_bits(1, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN); + else bank_config |= u32_encode_bits(0, HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN); bank_config |= u32_encode_bits(arvif->hal_addr_search_flags & HAL_TX_ADDRX_EN, @@ -339,7 +692,7 @@ HAL_TX_ADDRY_EN), HAL_TX_BANK_CONFIG_ADDRY_EN); - bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(arvif->vif) ? 3 : 0, + bank_config |= u32_encode_bits(ieee80211_vif_is_mesh(ahvif->vif) ? 3 : 0, HAL_TX_BANK_CONFIG_MESH_EN) | u32_encode_bits(arvif->vdev_id_check_en, HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN); @@ -349,7 +702,7 @@ return bank_config; } -static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, struct ath12k_vif *arvif, +static int ath12k_dp_tx_get_bank_profile(struct ath12k_base *ab, struct ath12k_link_vif *arvif, struct ath12k_dp *dp) { int bank_id = DP_INVALID_BANK_ID; @@ -406,6 +759,20 @@ spin_unlock_bh(&dp->tx_bank_lock); } +void ath12k_dp_tx_update_bank_profile(struct ath12k_link_vif *arvif) +{ + struct ath12k_base *ab = arvif->ar->ab; + struct ath12k_dp *dp = &ab->dp; + + ath12k_dp_tx_put_bank_profile(dp, arvif->bank_id); + arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, dp); + arvif->desc.info0 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_BANK_ID, + arvif->bank_id); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ath12k_dp_ppeds_update_vp_entry(arvif->ar, arvif); +#endif +} + static void ath12k_dp_deinit_bank_profiles(struct ath12k_base *ab) { struct ath12k_dp *dp = &ab->dp; @@ -437,6 +804,49 @@ return 0; } +static void ath12k_dp_srng_hw_disable(struct ath12k_base *ab, struct dp_srng *ring) +{ + struct hal_srng *srng = &ab->hal.srng_list[ring->ring_id]; + u32 reg_base, val, addr; + + reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; + if (srng->ring_dir == HAL_SRNG_DIR_SRC) { + if (srng->ring_id == HAL_SRNG_RING_ID_WBM_IDLE_LINK) + addr = HAL_SEQ_WCSS_UMAC_WBM_REG + + HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab); + else + addr = reg_base + HAL_TCL1_RING_MISC_OFFSET(ab); + val = ath12k_hif_read32(ab, addr); + val &= ~HAL_TCL1_RING_MISC_SRNG_ENABLE; + ath12k_hif_write32(ab, addr, val); + } else { + val = ath12k_hif_read32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET); + val &= ~HAL_REO1_RING_MISC_SRNG_ENABLE; + ath12k_hif_write32(ab , reg_base + HAL_REO1_RING_MISC_OFFSET, val); + } +} + +void ath12k_dp_srng_hw_ring_disable(struct ath12k_base *ab) +{ + struct ath12k_dp *dp = &ab->dp; + int i; + + for (i = 0; i < DP_REO_DST_RING_MAX; i++) + ath12k_dp_srng_hw_disable(ab, &dp->reo_dst_ring[i]); + ath12k_dp_srng_hw_disable(ab, &dp->wbm_desc_rel_ring); + + for(i = 0; i < ab->hw_params->max_tx_ring; i++) { + ath12k_dp_srng_hw_disable(ab, &dp->tx_ring[i].tcl_data_ring); + ath12k_dp_srng_hw_disable(ab, &dp->tx_ring[i].tcl_comp_ring); + } + ath12k_dp_srng_hw_disable(ab, &dp->reo_reinject_ring); + ath12k_dp_srng_hw_disable(ab, &dp->rx_rel_ring); + ath12k_dp_srng_hw_disable(ab, &dp->reo_except_ring); + ath12k_dp_srng_hw_disable(ab, &dp->reo_cmd_ring); + ath12k_dp_srng_hw_disable(ab, &dp->reo_status_ring); + ath12k_dp_srng_hw_disable(ab, &dp->wbm_idle_ring); +} + static void ath12k_dp_srng_common_cleanup(struct ath12k_base *ab) { struct ath12k_dp *dp = &ab->dp; @@ -451,9 +861,11 @@ ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_comp_ring); ath12k_dp_srng_cleanup(ab, &dp->tx_ring[i].tcl_data_ring); } - ath12k_dp_srng_cleanup(ab, &dp->tcl_status_ring); - ath12k_dp_srng_cleanup(ab, &dp->tcl_cmd_ring); ath12k_dp_srng_cleanup(ab, &dp->wbm_desc_rel_ring); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ath12k_dp_srng_ppeds_cleanup(ab); +#endif } static int ath12k_dp_srng_common_setup(struct ath12k_base *ab) @@ -463,6 +875,7 @@ struct hal_srng *srng; int i, ret, tx_comp_ring_num; u32 ring_hash_map; + u8 rbm_id; ret = ath12k_dp_srng_setup(ab, &dp->wbm_desc_rel_ring, HAL_SW2WBM_RELEASE, 0, 0, @@ -473,23 +886,10 @@ goto err; } - ret = ath12k_dp_srng_setup(ab, &dp->tcl_cmd_ring, HAL_TCL_CMD, 0, 0, - DP_TCL_CMD_RING_SIZE); - if (ret) { - ath12k_warn(ab, "failed to set up tcl_cmd ring :%d\n", ret); - goto err; - } - - ret = ath12k_dp_srng_setup(ab, &dp->tcl_status_ring, HAL_TCL_STATUS, - 0, 0, DP_TCL_STATUS_RING_SIZE); - if (ret) { - ath12k_warn(ab, "failed to set up tcl_status ring :%d\n", ret); - goto err; - } - for (i = 0; i < ab->hw_params->max_tx_ring; i++) { map = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map; tx_comp_ring_num = map[i].wbm_ring_num; + rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[i].rbm_id; ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_data_ring, HAL_TCL_DATA, i, 0, @@ -499,6 +899,7 @@ i, ret); goto err; } + ath12k_hal_tx_config_rbm_mapping(ab, i, rbm_id, HAL_TCL_DATA); ret = ath12k_dp_srng_setup(ab, &dp->tx_ring[i].tcl_comp_ring, HAL_WBM2SW_RELEASE, tx_comp_ring_num, 0, @@ -551,6 +952,9 @@ goto err; } + if (ath12k_dp_umac_reset_in_progress(ab)) + goto skip_reo_setup; + /* When hash based routing of rx packet is enabled, 32 entries to map * the hash values to the ring will be configured. Each hash entry uses * four bits to map to a particular ring. The ring mapping will be @@ -568,6 +972,15 @@ ath12k_hal_reo_hw_setup(ab, ring_hash_map); +skip_reo_setup: +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ret = ath12k_dp_srng_ppeds_setup(ab); + if (ret) { + ath12k_warn(ab, "failed to set up ppe-ds srngs :%d\n", ret); + goto err; + } +#endif + return 0; err: @@ -610,6 +1023,7 @@ int i; int ret = 0; u32 end_offset, cookie; + u8 rbm_id; n_entries_per_buf = HAL_WBM_IDLE_SCATTER_BUF_SIZE / ath12k_hal_srng_get_entrysize(ab, HAL_WBM_IDLE_LINK); @@ -618,6 +1032,7 @@ if (num_scatter_buf > DP_IDLE_SCATTER_BUFS_MAX) return -EINVAL; + if (!ath12k_dp_umac_reset_in_progress(ab)) { for (i = 0; i < num_scatter_buf; i++) { slist[i].vaddr = dma_alloc_coherent(ab->dev, HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX, @@ -627,10 +1042,12 @@ goto err; } } + } scatter_idx = 0; scatter_buf = slist[scatter_idx].vaddr; rem_entries = n_entries_per_buf; + rbm_id = dp->idle_link_rbm_id; for (i = 0; i < n_link_desc_bank; i++) { align_bytes = link_desc_banks[i].vaddr - @@ -640,7 +1057,8 @@ paddr = link_desc_banks[i].paddr; while (n_entries) { cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); - ath12k_hal_set_link_desc_addr(scatter_buf, cookie, paddr); + ath12k_hal_set_link_desc_addr(scatter_buf, cookie, + paddr, rbm_id); n_entries--; paddr += HAL_LINK_DESC_SIZE; if (rem_entries) { @@ -729,12 +1147,9 @@ u32 ring_type, struct dp_srng *ring) { ath12k_dp_link_desc_bank_free(ab, desc_bank); - - if (ring_type != HAL_RXDMA_MONITOR_DESC) { ath12k_dp_srng_cleanup(ab, ring); ath12k_dp_scatter_idle_link_desc_cleanup(ab); } -} static int ath12k_wbm_idle_ring_setup(struct ath12k_base *ab, u32 *n_link_desc) { @@ -784,6 +1199,7 @@ u32 paddr; int i, ret; u32 cookie; + u8 rbm_id; tot_mem_sz = n_link_desc * HAL_LINK_DESC_SIZE; tot_mem_sz += HAL_LINK_DESC_ALIGN; @@ -806,18 +1222,20 @@ if (n_link_desc_bank > DP_LINK_DESC_BANKS_MAX) return -EINVAL; + if (!ath12k_dp_umac_reset_in_progress(ab)) { ret = ath12k_dp_link_desc_bank_alloc(ab, link_desc_banks, n_link_desc_bank, last_bank_sz); if (ret) return ret; + } /* Setup link desc idle list for HW internal usage */ entry_sz = ath12k_hal_srng_get_entrysize(ab, ring_type); tot_mem_sz = entry_sz * n_link_desc; + rbm_id = ab->dp.idle_link_rbm_id; /* Setup scatter desc list when the total memory requirement is more */ - if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH && - ring_type != HAL_RXDMA_MONITOR_DESC) { + if (tot_mem_sz > DP_LINK_DESC_ALLOC_SIZE_THRESH) { ret = ath12k_dp_scatter_idle_link_desc_setup(ab, tot_mem_sz, n_link_desc_bank, n_link_desc, @@ -845,7 +1263,7 @@ (desc = ath12k_hal_srng_src_get_next_entry(ab, srng))) { cookie = DP_LINK_DESC_COOKIE_SET(n_entries, i); ath12k_hal_set_link_desc_addr(desc, - cookie, paddr); + cookie, paddr, rbm_id); n_entries--; paddr += HAL_LINK_DESC_SIZE; } @@ -873,16 +1291,35 @@ int i = 0, j; int tot_work_done = 0; enum dp_monitor_mode monitor_mode; - u8 ring_mask; + u8 ring_mask_val; + struct ath12k_hw_ring_mask *ring_mask = ab->hw_params->ring_mask; + u8 tx_mask = ring_mask->tx[grp_id]; + u8 rx_err_mask = ring_mask->rx_err[grp_id]; + u8 rx_wbm_rel_mask = ring_mask->rx_wbm_rel[grp_id]; + u8 rx_mask = ring_mask->rx[grp_id]; + u8 reo_status_mask = ring_mask->reo_status[grp_id]; + u8 host2rxdma_mask = ring_mask->host2rxdma[grp_id]; + u8 rx_mon_dest_mask = ring_mask->rx_mon_dest[grp_id]; + u8 tx_mon_dest_mask = ring_mask->tx_mon_dest[grp_id]; + u8 misc_intr_mask = rx_mon_dest_mask | + tx_mon_dest_mask | + reo_status_mask | + host2rxdma_mask; while (i < ab->hw_params->max_tx_ring) { - if (ab->hw_params->ring_mask->tx[grp_id] & - BIT(ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[i].wbm_ring_num)) - ath12k_dp_tx_completion_handler(ab, i); + if (tx_mask & + BIT(ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[i].wbm_ring_num)) { + work_done = ath12k_dp_tx_completion_handler(ab, i, + budget); + budget -= work_done; + tot_work_done += work_done; + if (budget <= 0) + goto done; + } i++; } - if (ab->hw_params->ring_mask->rx_err[grp_id]) { + if (rx_err_mask) { work_done = ath12k_dp_rx_process_err(ab, napi, budget); budget -= work_done; tot_work_done += work_done; @@ -890,7 +1327,7 @@ goto done; } - if (ab->hw_params->ring_mask->rx_wbm_rel[grp_id]) { + if (rx_wbm_rel_mask) { work_done = ath12k_dp_rx_process_wbm_err(ab, napi, budget); @@ -901,8 +1338,9 @@ goto done; } - if (ab->hw_params->ring_mask->rx[grp_id]) { - i = fls(ab->hw_params->ring_mask->rx[grp_id]) - 1; + while (rx_mask) { + i = fls(rx_mask) - 1; + rx_mask ^= 1 << i; work_done = ath12k_dp_rx_process(ab, i, napi, budget); budget -= work_done; @@ -911,14 +1349,17 @@ goto done; } - if (ab->hw_params->ring_mask->rx_mon_dest[grp_id]) { + if (!misc_intr_mask) + goto done; + + if (rx_mon_dest_mask) { monitor_mode = ATH12K_DP_RX_MONITOR_MODE; - ring_mask = ab->hw_params->ring_mask->rx_mon_dest[grp_id]; + ring_mask_val = ab->hw_params->ring_mask->rx_mon_dest[grp_id]; for (i = 0; i < ab->num_radios; i++) { for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) { int id = i * ab->hw_params->num_rxmda_per_pdev + j; - if (ring_mask & BIT(id)) { + if (ring_mask_val & BIT(id)) { work_done = ath12k_dp_mon_process_ring(ab, id, napi, budget, monitor_mode); @@ -932,14 +1373,14 @@ } } - if (ab->hw_params->ring_mask->tx_mon_dest[grp_id]) { + if (tx_mon_dest_mask) { monitor_mode = ATH12K_DP_TX_MONITOR_MODE; - ring_mask = ab->hw_params->ring_mask->tx_mon_dest[grp_id]; + ring_mask_val = ab->hw_params->ring_mask->tx_mon_dest[grp_id]; for (i = 0; i < ab->num_radios; i++) { for (j = 0; j < ab->hw_params->num_rxmda_per_pdev; j++) { int id = i * ab->hw_params->num_rxmda_per_pdev + j; - if (ring_mask & BIT(id)) { + if (ring_mask_val & BIT(id)) { work_done = ath12k_dp_mon_process_ring(ab, id, napi, budget, monitor_mode); @@ -953,16 +1394,15 @@ } } - if (ab->hw_params->ring_mask->reo_status[grp_id]) + if (reo_status_mask) ath12k_dp_rx_process_reo_status(ab); - if (ab->hw_params->ring_mask->host2rxdma[grp_id]) { + if (host2rxdma_mask) { struct ath12k_dp *dp = &ab->dp; struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; + LIST_HEAD(list); - ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, 0, - ab->hw_params->hal_params->rx_buf_rbm, - true); + ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); } /* TODO: Implement handler for other interrupts */ @@ -973,12 +1413,18 @@ void ath12k_dp_pdev_free(struct ath12k_base *ab) { + struct ath12k *ar; int i; del_timer_sync(&ab->mon_reap_timer); - for (i = 0; i < ab->num_radios; i++) + for (i = 0; i < ab->num_radios; i++) { + ar = ab->pdevs[i].ar; ath12k_dp_rx_pdev_free(ab, i); + ath12k_dp_rx_pdev_mon_detach(ab, i); + ath12k_fw_stats_free(&ar->fw_stats); + ath12k_debugfs_unregister(ar); + } } void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab) @@ -992,7 +1438,7 @@ dp = &ar->dp; dp->mac_id = i; atomic_set(&dp->num_tx_pending, 0); - init_waitqueue_head(&dp->tx_empty_waitq); + atomic_set(&ar->flush_request, 0); /* TODO: Add any RXDMA setup required per pdev */ } @@ -1013,11 +1459,38 @@ static void ath12k_dp_mon_reap_timer_init(struct ath12k_base *ab) { + timer_setup(&ab->mon_reap_timer, ath12k_dp_service_mon_ring, 0); + if (ab->hw_params->rxdma1_enable) return; +} - timer_setup(&ab->mon_reap_timer, ath12k_dp_service_mon_ring, 0); +#ifdef CONFIG_MAC80211_BONDED_SUPPORT +static int ath12k_dp_ppe_rxole_rxdma_cfg(struct ath12k_base *ab) +{ + struct ath12k_dp_htt_rxdma_ppe_cfg_param param = {0}; + int ret; + + if (!g_bonded_interface_model) + return 0; + + param.override = 1; + param.reo_dst_ind = HAL_REO2PPE_DST_IND; + param.multi_buffer_msdu_override_en = 0; + + /* Override use_ppe to 0 in RxOLE for the following cases */ + param.intra_bss_override = 1; + param.decap_raw_override = 1; + param.decap_nwifi_override = 1; + param.ip_frag_override = 1; + + ret = ath12k_dp_rx_htt_rxdma_rxole_ppe_cfg_set(ab, ¶m); + if (ret) + ath12k_err(ab, "RxOLE and RxDMA PPE config failed %d\n", ret); + + return ret; } +#endif int ath12k_dp_pdev_alloc(struct ath12k_base *ab) { @@ -1025,6 +1498,15 @@ int ret; int i; +#ifdef CONFIG_MAC80211_BONDED_SUPPORT + ret = ath12k_dp_ppe_rxole_rxdma_cfg(ab); + if (ret) { + ath12k_err(ab, "Failed to send htt RxOLE and RxDMA messages to target :%d\n", + ret); + goto out; + } +#endif + ret = ath12k_dp_rx_htt_setup(ab); if (ret) goto out; @@ -1077,15 +1559,14 @@ return 0; } -static void ath12k_dp_update_vdev_search(struct ath12k_vif *arvif) +static void ath12k_dp_update_vdev_search(struct ath12k_link_vif *arvif) { - switch (arvif->vdev_type) { + struct ath12k_vif *ahvif = arvif->ahvif; + + switch (ahvif->vdev_type) { case WMI_VDEV_TYPE_STA: - /* TODO: Verify the search type and flags since ast hash - * is not part of peer mapv3 - */ - arvif->hal_addr_search_flags = HAL_TX_ADDRY_EN; - arvif->search_type = HAL_TX_ADDR_SEARCH_DEFAULT; + arvif->hal_addr_search_flags = HAL_TX_ADDRX_EN; + arvif->search_type = HAL_TX_ADDR_SEARCH_INDEX; break; case WMI_VDEV_TYPE_AP: case WMI_VDEV_TYPE_IBSS: @@ -1098,14 +1579,14 @@ } } -void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif) +void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif) { struct ath12k_base *ab = ar->ab; - arvif->tcl_metadata |= u32_encode_bits(1, HTT_TCL_META_DATA_TYPE) | - u32_encode_bits(arvif->vdev_id, + arvif->tcl_metadata = HTT_TCL_META_DATA_GET(1, HTT_TCL_META_DATA_TYPE) | + HTT_TCL_META_DATA_GET(arvif->vdev_id, HTT_TCL_META_DATA_VDEV_ID) | - u32_encode_bits(ar->pdev->pdev_id, + HTT_TCL_META_DATA_GET(ar->pdev->pdev_id, HTT_TCL_META_DATA_PDEV_ID); /* set HTT extension valid bit to 0 by default */ @@ -1115,20 +1596,109 @@ arvif->vdev_id_check_en = true; arvif->bank_id = ath12k_dp_tx_get_bank_profile(ab, arvif, &ab->dp); + arvif->desc.info0 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_BANK_ID, + arvif->bank_id); + arvif->desc.info1 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_CMD_NUM, + arvif->tcl_metadata); + arvif->desc.info3 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_PMAC_ID, + ar->lmac_id) | + FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_VDEV_ID, + arvif->vdev_id); + arvif->desc.info4 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX, + arvif->ast_idx) | + FIELD_PREP(HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM, + arvif->ast_hash); + /* TODO: error path for bank id failure */ if (arvif->bank_id == DP_INVALID_BANK_ID) { ath12k_err(ar->ab, "Failed to initialize DP TX Banks"); return; } + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ath12k_dp_ppeds_update_vp_entry(ar, arvif); +#endif +} + +void ath12k_dp_umac_txrx_desc_cleanup(struct ath12k_base *ab) +{ + struct ath12k_rx_desc_info *desc_info; + struct ath12k_tx_desc_info *tx_desc_info; + struct ath12k_dp *dp = &ab->dp; + struct sk_buff *skb; + int i, j, k; + u32 tx_spt_page; + + /* RX Descriptor cleanup */ + spin_lock_bh(&dp->rx_desc_lock); + + for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { + desc_info = dp->spt_info->rxbaddr[i]; + + for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { + if (!desc_info[j].in_use) + continue; + + skb = desc_info[j].skb; + desc_info[j].skb = NULL; + desc_info[j].paddr = 0; + desc_info[j].in_use = false; + list_add_tail(&desc_info[j].list, &dp->rx_desc_free_list); + + if (!skb) + continue; + + dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, + skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); + dev_kfree_skb_any(skb); + } + } + + spin_unlock_bh(&dp->rx_desc_lock); + + /* TX Descriptor cleanup */ + for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { + spin_lock_bh(&dp->tx_desc_lock[i]); + + for (j = 0; j < ATH12K_TX_SPT_PAGES_PER_POOL; j++) { + tx_spt_page = j + i * ATH12K_TX_SPT_PAGES_PER_POOL; + tx_desc_info = dp->spt_info->txbaddr[tx_spt_page]; + + for (k = 0; k < ATH12K_MAX_SPT_ENTRIES; k++) { + if (!tx_desc_info[k].in_use) + continue; + + skb = tx_desc_info[k].skb; + if (!skb) + continue; + + tx_desc_info[k].skb = NULL; + tx_desc_info[k].skb_ext_desc = NULL; + tx_desc_info[k].in_use = false; + list_add_tail(&tx_desc_info[k].list, &dp->tx_desc_free_list[i]); + dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, + skb->len, DMA_TO_DEVICE); + if (tx_desc_info[k].skb_ext_desc) { + dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr_ext_desc, + tx_desc_info[k].skb_ext_desc->len, DMA_TO_DEVICE); + dev_kfree_skb_any(tx_desc_info[k].skb_ext_desc); + } + dev_kfree_skb_any(skb); + } + } + + spin_unlock_bh(&dp->tx_desc_lock[i]); + } } static void ath12k_dp_cc_cleanup(struct ath12k_base *ab) { - struct ath12k_rx_desc_info *desc_info, *tmp; - struct ath12k_tx_desc_info *tx_desc_info, *tmp1; + struct ath12k_rx_desc_info *desc_info; + struct ath12k_tx_desc_info *tx_desc_info; struct ath12k_dp *dp = &ab->dp; struct sk_buff *skb; - int i; + int i, j, k; + u32 pool_id, tx_spt_page; if (!dp->spt_info) return; @@ -1136,10 +1706,16 @@ /* RX Descriptor cleanup */ spin_lock_bh(&dp->rx_desc_lock); - list_for_each_entry_safe(desc_info, tmp, &dp->rx_desc_used_list, list) { - list_del(&desc_info->list); - skb = desc_info->skb; + for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { + desc_info = dp->spt_info->rxbaddr[i]; + for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { + if (!desc_info[j].in_use) { + list_del(&desc_info[j].list); + continue; + } + + skb = desc_info[j].skb; if (!skb) continue; @@ -1147,6 +1723,14 @@ skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } + } + + for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { + if (!dp->spt_info->rxbaddr[i]) + continue; + + kfree(dp->spt_info->rxbaddr[i]); + } spin_unlock_bh(&dp->rx_desc_lock); @@ -1154,22 +1738,53 @@ for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { spin_lock_bh(&dp->tx_desc_lock[i]); - list_for_each_entry_safe(tx_desc_info, tmp1, &dp->tx_desc_used_list[i], - list) { - list_del(&tx_desc_info->list); - skb = tx_desc_info->skb; + for (j = 0; j < ATH12K_TX_SPT_PAGES_PER_POOL; j++) { + tx_spt_page = j + i * ATH12K_TX_SPT_PAGES_PER_POOL; + tx_desc_info = dp->spt_info->txbaddr[tx_spt_page]; + for (k = 0; k < ATH12K_MAX_SPT_ENTRIES; k++) { + if (!tx_desc_info[k].in_use) + continue; + + skb = tx_desc_info[k].skb; if (!skb) continue; + tx_desc_info[k].skb = NULL; dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, skb->len, DMA_TO_DEVICE); + + if (tx_desc_info[k].skb_ext_desc) { + dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr_ext_desc, + tx_desc_info[k].skb_ext_desc->len, DMA_TO_DEVICE); + dev_kfree_skb_any(tx_desc_info[k].skb_ext_desc); + } dev_kfree_skb_any(skb); } + } spin_unlock_bh(&dp->tx_desc_lock[i]); } + for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { + spin_lock_bh(&dp->tx_desc_lock[pool_id]); + + for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) { + tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; + if (!dp->spt_info->txbaddr[tx_spt_page]) + continue; + + kfree(dp->spt_info->txbaddr[tx_spt_page]); + } + + spin_unlock_bh(&dp->tx_desc_lock[pool_id]); + } + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) + ath12k_ppeds_detach(ab); +#endif + /* unmap SPT pages */ for (i = 0; i < dp->num_spt_pages; i++) { if (!dp->spt_info[i].vaddr) @@ -1193,18 +1808,22 @@ if (!dp->reoq_lut.vaddr) return; + if (dp->reoq_lut.vaddr) { dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE, dp->reoq_lut.vaddr, dp->reoq_lut.paddr); dp->reoq_lut.vaddr = NULL; + } - ath12k_hif_write32(ab, - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), 0); + if (dp->ml_reoq_lut.vaddr) { + dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE, + dp->ml_reoq_lut.vaddr, dp->ml_reoq_lut.paddr); + dp->ml_reoq_lut.vaddr = NULL; + } } void ath12k_dp_free(struct ath12k_base *ab) { struct ath12k_dp *dp = &ab->dp; - int i; ath12k_dp_link_desc_cleanup(ab, dp->link_desc_banks, HAL_WBM_IDLE_LINK, &dp->wbm_idle_ring); @@ -1216,9 +1835,6 @@ ath12k_dp_rx_reo_cmd_list_cleanup(ab); - for (i = 0; i < ab->hw_params->max_tx_ring; i++) - kfree(dp->tx_ring[i].tx_status); - ath12k_dp_rx_free(ab); /* Deinit any SOC level resource */ } @@ -1230,6 +1846,9 @@ u32 wbm_base = HAL_SEQ_WCSS_UMAC_WBM_REG; u32 val = 0; + if (ath12k_ftm_mode) + return; + ath12k_hif_write32(ab, reo_base + HAL_REO1_SW_COOKIE_CFG0(ab), cmem_base); val |= u32_encode_bits(ATH12K_CMEM_ADDR_MSB, @@ -1283,12 +1902,13 @@ { struct ath12k_dp *dp = &ab->dp; - return dp->spt_info[ppt_idx].vaddr + spt_idx; + return dp->spt_info[ppt_idx].vaddr + (spt_idx * sizeof(u64)); } struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, u32 cookie) { + struct ath12k_dp *dp = &ab->dp; struct ath12k_rx_desc_info **desc_addr_ptr; u16 ppt_idx, spt_idx; @@ -1299,6 +1919,11 @@ spt_idx > ATH12K_MAX_SPT_ENTRIES) return NULL; + if (WARN_ON(spt_idx < dp->rx_spt_base)) + return NULL; + + spt_idx = spt_idx - dp->rx_spt_base; + desc_addr_ptr = ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, spt_idx); return *desc_addr_ptr; @@ -1323,16 +1948,270 @@ return *desc_addr_ptr; } +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +static u8 *ath12k_dp_cc_find_desc(struct ath12k_base *ab, u32 cookie, bool is_rx) +{ + struct ath12k_dp *dp = &ab->dp; + u16 spt_page_id, spt_idx; + u8 *spt_va; + spt_idx = u32_get_bits(cookie, ATH12k_DP_CC_COOKIE_SPT); + spt_page_id = u32_get_bits(cookie, ATH12K_DP_CC_COOKIE_PPT); + if (is_rx) { + if (WARN_ON(spt_page_id < dp->rx_spt_base)) + return NULL; + spt_page_id = spt_page_id - dp->rx_spt_base; + } + spt_va = (u8 *)dp->spt_info[spt_page_id].vaddr; + return (spt_va + spt_idx * sizeof(u64)); +} + +struct ath12k_ppeds_tx_desc_info *ath12k_dp_get_ppeds_tx_desc(struct ath12k_base *ab, + u32 desc_id) +{ + u8 *desc_addr_ptr; + + desc_addr_ptr = ath12k_dp_cc_find_desc(ab, desc_id, false); + return *(struct ath12k_ppeds_tx_desc_info **)desc_addr_ptr; +} +#endif + +static void ath12k_dp_tx_cmem_init(struct ath12k_base *ab, struct ath12k_dp *dp) +{ + u32 cmem_base; + int i; + + cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; + + for (i = ATH12K_TX_SPT_PAGE_OFFSET; + i < (ATH12K_TX_SPT_PAGE_OFFSET + ATH12K_NUM_TX_SPT_PAGES); i++) { + /* Write to PPT in CMEM */ + if (ab->hif.ops->cmem_write32) + ath12k_hif_cmem_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), + dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); + else + ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), + dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); + } +} + +static void ath12k_dp_rx_cmem_init(struct ath12k_base *ab, struct ath12k_dp *dp) +{ + u32 cmem_base; + int i; + + cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; + cmem_base += ATH12K_PPT_ADDR_OFFSET(dp->rx_spt_base); + + for (i = ATH12K_RX_SPT_PAGE_OFFSET; + i < (ATH12K_RX_SPT_PAGE_OFFSET + ATH12K_NUM_RX_SPT_PAGES); i++) { + /* Write to PPT in CMEM */ + if (ab->hif.ops->cmem_write32) + ath12k_hif_cmem_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), + dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); + else + ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), + dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); + } +} + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +void ath12k_dp_ppeds_tx_cmem_init(struct ath12k_base *ab, struct ath12k_dp *dp) +{ + u32 cmem_base; + int i; + + cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; + + for (i = ATH12K_PPEDS_TX_SPT_PAGE_OFFSET; + i < (ATH12K_PPEDS_TX_SPT_PAGE_OFFSET + ATH12K_NUM_PPEDS_TX_SPT_PAGES); i++) { + /* Write to PPT in CMEM */ + if (ab->hif.ops->cmem_write32) + ath12k_hif_cmem_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), + dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); + else + ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), + dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); + } +} + +static void ath12k_dp_ppeds_tx_desc_cleanup(struct ath12k_base *ab) +{ + struct ath12k_ppeds_tx_desc_info *ppeds_tx_desc_info, *tmp2; + struct ath12k_dp *dp = &ab->dp; + struct sk_buff *skb; + int i; + + /* PPEDS TX Descriptor cleanup */ + for (i = 0; i < ATH12K_HW_MAX_QUEUES_PPEDS; i++) { + spin_lock_bh(&dp->ppeds_tx_desc_lock[i]); + + /* clean up used desc list */ + list_for_each_entry_safe(ppeds_tx_desc_info, tmp2, + &dp->ppeds_tx_desc_used_list[i], + list) { + list_move_tail(&ppeds_tx_desc_info->list, + &dp->ppeds_tx_desc_free_list[i]); + skb = ppeds_tx_desc_info->skb; + ppeds_tx_desc_info->skb = NULL; + if (!skb) { + WARN_ON_ONCE(1); + continue; + } + dma_unmap_single_attrs(ab->dev, ATH12K_SKB_CB(skb)->paddr, + skb->len, DMA_TO_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + dev_kfree_skb_any(skb); + } + + /* clean up descriptors and skbs from reuse list */ + list_for_each_entry_safe(ppeds_tx_desc_info, tmp2, + &dp->ppeds_tx_desc_reuse_list[i], + list) { + list_move_tail(&ppeds_tx_desc_info->list, + &dp->ppeds_tx_desc_free_list[i]); + skb = ppeds_tx_desc_info->skb; + ppeds_tx_desc_info->skb = NULL; + if (!skb) { + WARN_ON_ONCE(1); + continue; + } + dma_unmap_single_attrs(ab->dev, ppeds_tx_desc_info->paddr, + skb->len, DMA_TO_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + dev_kfree_skb_any(skb); + } + dp->ppeds_tx_desc_reuse_list_len[i] = 0; + + spin_unlock_bh(&dp->ppeds_tx_desc_lock[i]); + } +} + +int ath12k_dp_cc_ppeds_desc_cleanup(struct ath12k_base *ab) +{ + struct ath12k_ppeds_tx_desc_info *ppeds_tx_desc_info, *tmp2; + struct ath12k_dp *dp = &ab->dp; + struct sk_buff *skb; + int i; + u32 pool_id, ppeds_tx_spt_page; + + if (!dp->spt_info) { + ath12k_err(ab,"ath12k_dp_cc_ppeds_desc_cleanup failed"); + return -EINVAL; + } + + /* PPEDS TX Descriptor cleanup */ + for (i = 0; i < ATH12K_HW_MAX_QUEUES_PPEDS; i++) { + spin_lock_bh(&dp->ppeds_tx_desc_lock[i]); + + /* clean up used desc list */ + list_for_each_entry_safe(ppeds_tx_desc_info, tmp2, + &dp->ppeds_tx_desc_used_list[i], + list) { + list_del(&ppeds_tx_desc_info->list); + skb = ppeds_tx_desc_info->skb; + if (!skb) + continue; + + dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, + skb->len, DMA_TO_DEVICE); + dev_kfree_skb_any(skb); + } + + /* clean up descriptors and skbs from reuse list */ + list_for_each_entry_safe(ppeds_tx_desc_info, tmp2, + &dp->ppeds_tx_desc_reuse_list[i], + list) { + list_del(&ppeds_tx_desc_info->list); + skb = ppeds_tx_desc_info->skb; + if (!skb) + continue; + + dma_unmap_single(ab->dev, ppeds_tx_desc_info->paddr, + skb->len, DMA_TO_DEVICE); + dev_kfree_skb_any(skb); + } + + spin_unlock_bh(&dp->ppeds_tx_desc_lock[i]); + } + + for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES_PPEDS; pool_id++) { + spin_lock_bh(&dp->ppeds_tx_desc_lock[pool_id]); + + for (i = 0; i < ATH12K_PPEDS_TX_SPT_PAGES_PER_POOL; i++) { + ppeds_tx_spt_page = i + pool_id * ATH12K_PPEDS_TX_SPT_PAGES_PER_POOL; + if (!dp->spt_info->ppedstxbaddr[ppeds_tx_spt_page]) + continue; + + kfree(dp->spt_info->ppedstxbaddr[ppeds_tx_spt_page]); + } + + spin_unlock_bh(&dp->ppeds_tx_desc_lock[pool_id]); + } + ath12k_dbg(ab, ATH12K_DBG_PPE, "ath12k_dp_cc_ppeds_desc_cleanup success\n"); + + return 0; +} + +int ath12k_dp_cc_ppeds_desc_init(struct ath12k_base *ab) +{ + struct ath12k_dp *dp = &ab->dp; + struct ath12k_ppeds_tx_desc_info *ppeds_tx_descs; + struct ath12k_spt_info *ppeds_tx_spt_pages; + u32 i, j, pool_id, ppeds_tx_spt_page; + u32 ppt_idx; + + /* pointer to start of TX pages */ + ppeds_tx_spt_pages = &dp->spt_info[ATH12K_PPEDS_TX_SPT_PAGE_OFFSET]; + + for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES_PPEDS; pool_id++) { + spin_lock_bh(&dp->ppeds_tx_desc_lock[pool_id]); + for (i = 0; i < ATH12K_PPEDS_TX_SPT_PAGES_PER_POOL; i++) { + ppeds_tx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*ppeds_tx_descs), + GFP_ATOMIC); + + if (!ppeds_tx_descs) { + spin_unlock_bh(&dp->ppeds_tx_desc_lock[pool_id]); + ath12k_dp_cc_ppeds_desc_cleanup(ab); + return -ENOMEM; + } + + ppeds_tx_spt_page = i + pool_id * ATH12K_PPEDS_TX_SPT_PAGES_PER_POOL; + dp->spt_info->ppedstxbaddr[ppeds_tx_spt_page] = &ppeds_tx_descs[0]; + + for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { + ppt_idx = ATH12K_PPEDS_TX_SPT_PAGE_OFFSET + ppeds_tx_spt_page; + ppeds_tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j); + ppeds_tx_descs[j].pool_id = pool_id; + list_add_tail(&ppeds_tx_descs[j].list, + &dp->ppeds_tx_desc_free_list[pool_id]); + + /* Update descriptor VA in SPT */ + *(struct ath12k_ppeds_tx_desc_info **) + ((u8 *)ppeds_tx_spt_pages[ppeds_tx_spt_page].vaddr + + (j * sizeof(u64))) = &ppeds_tx_descs[j]; + } + } + spin_unlock_bh(&dp->ppeds_tx_desc_lock[pool_id]); + } + ath12k_dbg(ab, ATH12K_DBG_PPE, "ath12k_dp_cc_ppeds_desc_init success\n"); + + return 0; +} +#endif + static int ath12k_dp_cc_desc_init(struct ath12k_base *ab) { struct ath12k_dp *dp = &ab->dp; - struct ath12k_rx_desc_info *rx_descs, **rx_desc_addr; - struct ath12k_tx_desc_info *tx_descs, **tx_desc_addr; + struct ath12k_rx_desc_info *rx_descs; + struct ath12k_tx_desc_info *tx_descs; + struct ath12k_spt_info *tx_spt_pages, *rx_spt_pages; u32 i, j, pool_id, tx_spt_page; u32 ppt_idx; spin_lock_bh(&dp->rx_desc_lock); + rx_spt_pages = &dp->spt_info[ATH12K_RX_SPT_PAGE_OFFSET]; + /* First ATH12K_NUM_RX_SPT_PAGES of allocated SPT pages are used for RX */ for (i = 0; i < ATH12K_NUM_RX_SPT_PAGES; i++) { rx_descs = kcalloc(ATH12K_MAX_SPT_ENTRIES, sizeof(*rx_descs), @@ -1343,19 +2222,26 @@ return -ENOMEM; } + dp->spt_info->rxbaddr[i] = &rx_descs[0]; + ppt_idx = dp->rx_spt_base + ATH12K_RX_SPT_PAGE_OFFSET + i; + for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { - rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(i, j); + rx_descs[j].cookie = ath12k_dp_cc_cookie_gen(ppt_idx, j); rx_descs[j].magic = ATH12K_DP_RX_DESC_MAGIC; + rx_descs[j].chip_id = ab->chip_id; list_add_tail(&rx_descs[j].list, &dp->rx_desc_free_list); /* Update descriptor VA in SPT */ - rx_desc_addr = ath12k_dp_cc_get_desc_addr_ptr(ab, i, j); - *rx_desc_addr = &rx_descs[j]; + *(struct ath12k_rx_desc_info **)((u8 *)rx_spt_pages[i].vaddr + + (j * sizeof(u64))) = &rx_descs[j]; } } spin_unlock_bh(&dp->rx_desc_lock); + /* pointer to start of TX pages */ + tx_spt_pages = &dp->spt_info[ATH12K_TX_SPT_PAGE_OFFSET]; + for (pool_id = 0; pool_id < ATH12K_HW_MAX_QUEUES; pool_id++) { spin_lock_bh(&dp->tx_desc_lock[pool_id]); for (i = 0; i < ATH12K_TX_SPT_PAGES_PER_POOL; i++) { @@ -1368,18 +2254,20 @@ return -ENOMEM; } - for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { tx_spt_page = i + pool_id * ATH12K_TX_SPT_PAGES_PER_POOL; - ppt_idx = ATH12K_NUM_RX_SPT_PAGES + tx_spt_page; + dp->spt_info->txbaddr[tx_spt_page] = &tx_descs[0]; + + for (j = 0; j < ATH12K_MAX_SPT_ENTRIES; j++) { + ppt_idx = ATH12K_TX_SPT_PAGE_OFFSET + tx_spt_page; tx_descs[j].desc_id = ath12k_dp_cc_cookie_gen(ppt_idx, j); tx_descs[j].pool_id = pool_id; list_add_tail(&tx_descs[j].list, &dp->tx_desc_free_list[pool_id]); /* Update descriptor VA in SPT */ - tx_desc_addr = - ath12k_dp_cc_get_desc_addr_ptr(ab, ppt_idx, j); - *tx_desc_addr = &tx_descs[j]; + *(struct ath12k_tx_desc_info **) + ((u8 *)tx_spt_pages[tx_spt_page].vaddr + + (j * sizeof(u64))) = &tx_descs[j]; } } spin_unlock_bh(&dp->tx_desc_lock[pool_id]); @@ -1387,6 +2275,23 @@ return 0; } +void ath12k_dp_partner_cc_init(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_base *partner_ab; + struct ath12k_dp *dp; + int i; + + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + if (partner_ab == ab) + continue; + + dp = &partner_ab->dp; + ath12k_dp_rx_cmem_init(ab, dp); + } +} + static int ath12k_dp_cc_init(struct ath12k_base *ab) { struct ath12k_dp *dp = &ab->dp; @@ -1394,7 +2299,6 @@ u32 cmem_base; INIT_LIST_HEAD(&dp->rx_desc_free_list); - INIT_LIST_HEAD(&dp->rx_desc_used_list); spin_lock_init(&dp->rx_desc_lock); for (i = 0; i < ATH12K_HW_MAX_QUEUES; i++) { @@ -1415,6 +2319,7 @@ return -ENOMEM; } + dp->rx_spt_base = ab->chip_id * ATH12K_NUM_RX_SPT_PAGES; cmem_base = ab->qmi.dev_mem[ATH12K_QMI_DEVMEM_CMEM_INDEX].start; for (i = 0; i < dp->num_spt_pages; i++) { @@ -1433,18 +2338,31 @@ ret = -EINVAL; goto free; } - - /* Write to PPT in CMEM */ - ath12k_hif_write32(ab, cmem_base + ATH12K_PPT_ADDR_OFFSET(i), - dp->spt_info[i].paddr >> ATH12K_SPT_4K_ALIGN_OFFSET); } + ath12k_dp_tx_cmem_init(ab, dp); + + ath12k_dp_rx_cmem_init(ab, dp); + ret = ath12k_dp_cc_desc_init(ab); if (ret) { ath12k_warn(ab, "HW CC desc init failed %d", ret); goto free; } +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) { + for (i = 0; i < ATH12K_HW_MAX_QUEUES_PPEDS; i++) { + INIT_LIST_HEAD(&dp->ppeds_tx_desc_free_list[i]); + INIT_LIST_HEAD(&dp->ppeds_tx_desc_reuse_list[i]); + INIT_LIST_HEAD(&dp->ppeds_tx_desc_used_list[i]); + spin_lock_init(&dp->ppeds_tx_desc_lock[i]); + dp->ppeds_tx_desc_reuse_list_len[i] = 0; + } + ath12k_ppeds_attach(ab); + } +#endif + return 0; free: ath12k_dp_cc_cleanup(ab); @@ -1454,6 +2372,7 @@ static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab) { struct ath12k_dp *dp = &ab->dp; + u32 val; if (!ab->hw_params->reoq_lut_support) return 0; @@ -1467,8 +2386,38 @@ return -ENOMEM; } + dp->ml_reoq_lut.vaddr = dma_alloc_coherent(ab->dev, + DP_REOQ_LUT_SIZE, + &dp->ml_reoq_lut.paddr, + GFP_KERNEL); + + if (!dp->ml_reoq_lut.vaddr) { + ath12k_warn(ab, "failed to allocate memory for ML reoq table"); + + /* cleanup non-ML REOQ LUT allocated above */ + dma_free_coherent(ab->dev, DP_REOQ_LUT_SIZE, + dp->reoq_lut.vaddr, dp->reoq_lut.paddr); + dp->reoq_lut.vaddr = NULL; + return -ENOMEM; + } + + memset(dp->reoq_lut.vaddr, 0, DP_REOQ_LUT_SIZE); + memset(dp->ml_reoq_lut.vaddr, 0, DP_REOQ_LUT_SIZE); + ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0(ab), - dp->reoq_lut.paddr); + dp->reoq_lut.paddr >> 8); + + ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE1(ab), + dp->ml_reoq_lut.paddr >> 8); + + val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR_READ(ab)); + + ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR_READ(ab), + val | HAL_REO_QDESC_ADDR_READ_LUT_ENABLE); + + ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID(ab), + HAL_REO_QDESC_MAX_PEERID); + return 0; } @@ -1480,14 +2429,19 @@ u32 n_link_desc = 0; int ret; int i; + u8 chip_id; dp->ab = ab; INIT_LIST_HEAD(&dp->reo_cmd_list); INIT_LIST_HEAD(&dp->reo_cmd_cache_flush_list); + INIT_LIST_HEAD(&dp->reo_cmd_update_rx_queue_list); spin_lock_init(&dp->reo_cmd_lock); + spin_lock_init(&dp->reo_cmd_update_rx_queue_lock); dp->reo_cmd_cache_flush_count = 0; + chip_id = (ab->ag->mlo_capable) ? ab->chip_id : 0; + dp->idle_link_rbm_id = HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST + chip_id; ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc); if (ret) { @@ -1530,17 +2484,6 @@ for (i = 0; i < ab->hw_params->max_tx_ring; i++) { dp->tx_ring[i].tcl_data_ring_id = i; - - dp->tx_ring[i].tx_status_head = 0; - dp->tx_ring[i].tx_status_tail = DP_TX_COMP_RING_SIZE - 1; - dp->tx_ring[i].tx_status = kmalloc(size, GFP_KERNEL); - if (!dp->tx_ring[i].tx_status) { - ret = -ENOMEM; - /* FIXME: The allocated tx status is not freed - * properly here - */ - goto fail_cmn_reoq_cleanup; - } } for (i = 0; i < HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX; i++) @@ -1556,8 +2499,6 @@ fail_dp_rx_free: ath12k_dp_rx_free(ab); - -fail_cmn_reoq_cleanup: ath12k_dp_reoq_lut_cleanup(ab); fail_cmn_srng_cleanup: @@ -1575,3 +2516,81 @@ return ret; } + +int ath12k_dp_rxdma_ring_setup(struct ath12k_base *ab) +{ + struct ath12k_dp *dp = &ab->dp; + int ret; + struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; + LIST_HEAD(list); + + ret = ath12k_dp_srng_setup(ab, + &dp->rx_refill_buf_ring.refill_buf_ring, + HAL_RXDMA_BUF, 0, 0, + DP_RXDMA_BUF_RING_SIZE); + + if (ret) { + ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); + return ret; + } + + ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); + return 0; +} + +void ath12k_umac_reset_handle_post_reset_start(struct ath12k_base *ab) +{ + struct ath12k_dp *dp = &ab->dp; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset = &ag->mlo_umac_reset; + int i, n_link_desc, ret; + struct hal_srng *srng = NULL; + unsigned long end; + + ath12k_dp_srng_hw_ring_disable(ab); + + /* Busy wait for 2 ms to make sure the rings are + * in idle state before enabling it + */ + end = jiffies + msecs_to_jiffies(2); + while (time_before(jiffies, end)) + ; + + ret = ath12k_wbm_idle_ring_setup(ab, &n_link_desc); + + if (ret) + ath12k_warn(ab, "failed to setup wbm_idle_ring: %d\n", ret); + + srng = &ab->hal.srng_list[dp->wbm_idle_ring.ring_id]; + + ret = ath12k_dp_link_desc_setup(ab, dp->link_desc_banks, + HAL_WBM_IDLE_LINK, srng, n_link_desc); + if (ret) + ath12k_warn(ab, "failed to setup link desc: %d\n", ret); + + ath12k_dp_srng_common_setup(ab); + ath12k_dp_umac_txrx_desc_cleanup(ab); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (ab->ppeds_handle) + ath12k_dp_ppeds_tx_desc_cleanup(ab); +#endif + ath12k_dp_rxdma_ring_setup(ab); + + for (i = 0; i < DP_REO_DST_RING_MAX; i++) { + ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], + HAL_REO_DST, i, 0, + DP_REO_DST_RING_SIZE); + if (ret) + ath12k_warn(ab, "failed to setup reo_dst_ring\n"); + } + + ath12k_dp_rx_reo_cmd_list_cleanup(ab); + + ath12k_dp_tid_cleanup(ab); + + atomic_inc(&mlo_umac_reset->response_chip); + ath12k_umac_reset_notify_target_sync_and_send(ab, ATH12K_UMAC_RESET_TX_CMD_POST_RESET_START_DONE); + + return; +} diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp.h --- linux-6.4/drivers/net/wireless/ath/ath12k/dp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp.h 2024-03-18 14:40:14.847741224 +0100 @@ -6,7 +6,7 @@ #ifndef ATH12K_DP_H #define ATH12K_DP_H - +#include "core.h" #include "hal_rx.h" #include "hw.h" @@ -15,7 +15,8 @@ struct ath12k_base; struct ath12k_peer; struct ath12k_dp; -struct ath12k_vif; +struct ath12k_link_vif; +struct ath12k_link_sta; struct hal_tcl_status_ring; struct ath12k_ext_irq_grp; @@ -29,6 +30,7 @@ dma_addr_t paddr; int size; u32 ring_id; + u8 cached; }; struct dp_rxdma_ring { @@ -39,15 +41,19 @@ int bufs_max; }; -#define ATH12K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +struct dp_ppeds_tx_comp_ring { + struct dp_srng ppe_wbm2sw_ring; + struct hal_wbm_completion_ring_tx *tx_status; + int tx_status_head; + int tx_status_tail; +}; +#endif struct dp_tx_ring { u8 tcl_data_ring_id; struct dp_srng tcl_data_ring; struct dp_srng tcl_comp_ring; - struct hal_wbm_completion_ring_tx *tx_status; - int tx_status_head; - int tx_status_tail; }; struct ath12k_pdev_mon_stats { @@ -127,12 +133,11 @@ struct ath12k_pdev_dp { u32 mac_id; atomic_t num_tx_pending; - wait_queue_head_t tx_empty_waitq; struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; struct ieee80211_rx_status rx_status; - struct ath12k_mon_data mon_data; + struct ath12k_mon_data *mon_data; }; #define DP_NUM_CLIENTS_MAX 64 @@ -145,32 +150,51 @@ #define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ -#define DP_BA_WIN_SZ_MAX 256 +#define DP_BA_WIN_SZ_MAX 1024 #define DP_TCL_NUM_RING_MAX 4 #define DP_IDLE_SCATTER_BUFS_MAX 16 +#ifdef CONFIG_ATH12K_MEM_PROFILE_512M + +#define DP_TX_COMP_RING_SIZE 8192 +#define DP_RXDMA_MON_STATUS_RING_SIZE 512 +#define DP_RXDMA_MONITOR_BUF_RING_SIZE 256 +#define DP_RXDMA_MONITOR_DST_RING_SIZE 512 +#define ATH12K_NUM_POOL_TX_DESC 8192 +#define DP_REO2PPE_RING_SIZE 2048 +/* TODO revisit this count during testing */ +#define ATH12K_RX_DESC_COUNT (4096) + +#else +#define DP_TX_COMP_RING_SIZE 32768 +#define DP_RXDMA_MON_STATUS_RING_SIZE 2048 +#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 +#define DP_RXDMA_MONITOR_DST_RING_SIZE 8192 +#define ATH12K_NUM_POOL_TX_DESC 32768 +#define DP_REO2PPE_RING_SIZE 16384 +/* TODO revisit this count during testing */ +#define ATH12K_RX_DESC_COUNT (12288) +#endif + #define DP_WBM_RELEASE_RING_SIZE 64 #define DP_TCL_DATA_RING_SIZE 512 -#define DP_TX_COMP_RING_SIZE 32768 #define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE #define DP_TCL_CMD_RING_SIZE 32 #define DP_TCL_STATUS_RING_SIZE 32 -#define DP_REO_DST_RING_MAX 8 +#define DP_REO_DST_RING_MAX 4 #define DP_REO_DST_RING_SIZE 2048 #define DP_REO_REINJECT_RING_SIZE 32 -#define DP_RX_RELEASE_RING_SIZE 1024 +#define DP_RX_RELEASE_RING_SIZE 4096 #define DP_REO_EXCEPTION_RING_SIZE 128 -#define DP_REO_CMD_RING_SIZE 128 +#define DP_REO_CMD_RING_SIZE 256 #define DP_REO_STATUS_RING_SIZE 2048 -#define DP_RXDMA_BUF_RING_SIZE 4096 +#define DP_RXDMA_BUF_RING_SIZE 8192 #define DP_RXDMA_REFILL_RING_SIZE 2048 #define DP_RXDMA_ERR_DST_RING_SIZE 1024 -#define DP_RXDMA_MON_STATUS_RING_SIZE 1024 -#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 -#define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 -#define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 +#define DP_RXDMA_MONITOR_DESC_RING_SIZE 8192 +#define DP_RX_MONITOR_BUF_LOW_TH 32 #define DP_TX_MONITOR_BUF_RING_SIZE 4096 #define DP_TX_MONITOR_DEST_RING_SIZE 2048 @@ -182,8 +206,14 @@ #define DP_RX_BUFFER_SIZE_LITE 1024 #define DP_RX_BUFFER_ALIGN_SIZE 128 -#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) -#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) +#define DP_PPE2TCL_RING_SIZE 2048 +#define DP_PPE_WBM2SW_RING_SIZE 8192 +#define HAL_REO2PPE_DST_IND 6 + +#define DP_DIR_BUF_COOKIE_BUF_ID GENMASK(17, 0) +#define DP_DIR_BUF_COOKIE_PDEV_ID GENMASK(19, 18) + +#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(19, 0) #define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) #define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) @@ -195,10 +225,11 @@ #define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 #define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 -#define ATH12K_NUM_POOL_TX_DESC 32768 - -/* TODO: revisit this count during testing */ -#define ATH12K_RX_DESC_COUNT (12288) +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#define ATH12K_NUM_POOL_PPEDS_TX_DESC 0x10000 +#else +#define ATH12K_NUM_POOL_PPEDS_TX_DESC 0 +#endif #define ATH12K_PAGE_SIZE PAGE_SIZE @@ -215,7 +246,19 @@ #define ATH12K_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_TX_DESC / \ ATH12K_MAX_SPT_ENTRIES) #define ATH12K_NUM_TX_SPT_PAGES (ATH12K_TX_SPT_PAGES_PER_POOL * ATH12K_HW_MAX_QUEUES) -#define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_RX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES) + +#define ATH12K_PPEDS_TX_SPT_PAGE_OFFSET 0 +#define ATH12K_TX_SPT_PAGE_OFFSET ATH12K_NUM_PPEDS_TX_SPT_PAGES +#define ATH12K_RX_SPT_PAGE_OFFSET ATH12K_NUM_PPEDS_TX_SPT_PAGES + ATH12K_NUM_TX_SPT_PAGES + + +#define ATH12K_PPEDS_TX_SPT_PAGES_PER_POOL (ATH12K_NUM_POOL_PPEDS_TX_DESC / \ + ATH12K_MAX_SPT_ENTRIES) +#define ATH12K_NUM_PPEDS_TX_SPT_PAGES (ATH12K_PPEDS_TX_SPT_PAGES_PER_POOL *\ + ATH12K_HW_MAX_QUEUES_PPEDS) + +#define ATH12K_NUM_SPT_PAGES (ATH12K_NUM_TX_SPT_PAGES + ATH12K_NUM_RX_SPT_PAGES + \ + ATH12K_NUM_PPEDS_TX_SPT_PAGES) /* The SPT pages are divided for RX and TX, first block for RX * and remaining for TX @@ -245,6 +288,9 @@ #define DP_REO_QREF_NUM GENMASK(31, 16) #define DP_MAX_PEER_ID 2047 +#define ATH12K_DP_PDEV_TX_LIMIT 24000 +#define ATH12K_DP_GROUP_TX_LIMIT 32000 + /* Total size of the LUT is based on 2K peers, each having reference * for 17tids, note each entry is of type ath12k_reo_queue_ref * hence total size is 2048 * 17 * 8 = 278528 @@ -254,6 +300,10 @@ /* Invalid TX Bank ID value */ #define DP_INVALID_BANK_ID -1 +#define MAX_TQM_RELEASE_REASON 15 +#define MAX_FW_TX_STATUS 7 +#define MAX_TCL_RING 4 + struct ath12k_dp_tx_bank_profile { u8 is_configured; u32 num_users; @@ -273,22 +323,44 @@ struct ath12k_rx_desc_info { struct list_head list; - struct sk_buff *skb; u32 cookie; + dma_addr_t paddr; + u8 chip_id : 3, + in_use : 1; + struct sk_buff *skb; u32 magic; }; struct ath12k_tx_desc_info { struct list_head list; struct sk_buff *skb; + struct sk_buff *skb_ext_desc; + u32 desc_id; /* Cookie */ + u8 mac_id : 5, + in_use : 1; + u8 pool_id; + u8 recycler_fast_xmit; + ktime_t timestamp; +}; + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +struct ath12k_ppeds_tx_desc_info { + struct list_head list; + struct sk_buff *skb; + dma_addr_t paddr; u32 desc_id; /* Cookie */ u8 mac_id; u8 pool_id; + u8 flags; }; +#endif struct ath12k_spt_info { dma_addr_t paddr; u64 *vaddr; + struct ath12k_rx_desc_info *rxbaddr[ATH12K_NUM_RX_SPT_PAGES]; + struct ath12k_tx_desc_info *txbaddr[ATH12K_NUM_TX_SPT_PAGES]; + struct ath12k_ppeds_tx_desc_info *ppedstxbaddr[ATH12K_NUM_PPEDS_TX_SPT_PAGES]; }; struct ath12k_reo_queue_ref { @@ -301,6 +373,32 @@ u32 *vaddr; }; +struct host_link_stats { + u32 tx_enqueued; + u32 tx_completed; + u32 tx_bcast_mcast; + u32 tx_dropped; + u32 tx_encap_type[HAL_TCL_ENCAP_TYPE_MAX]; + u32 tx_encrypt_type[HAL_ENCRYPT_TYPE_MAX]; + u32 tx_desc_type[HAL_TCL_DESC_TYPE_MAX]; +}; + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#define PPE_VP_ENTRIES_MAX 32 +#define MAX_PPEDS_IRQ_NAME_LEN 20 +#define MAX_PPEDS_IRQS 3 +struct ath12k_dp_ppe_vp_profile { + bool is_configured; + u8 vp_num; + u8 ppe_vp_num_idx; + u8 search_idx_reg_num; + u8 drop_prec_enable; + u8 to_fw; + u8 use_ppe_int_pri; + struct ath12k_link_vif *arvif; +}; +#endif + struct ath12k_dp { struct ath12k_base *ab; u8 num_bank_profiles; @@ -312,14 +410,18 @@ u8 htt_tgt_ver_major; u8 htt_tgt_ver_minor; struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; + u8 idle_link_rbm_id; struct dp_srng wbm_idle_ring; struct dp_srng wbm_desc_rel_ring; - struct dp_srng tcl_cmd_ring; - struct dp_srng tcl_status_ring; struct dp_srng reo_reinject_ring; struct dp_srng rx_rel_ring; struct dp_srng reo_except_ring; struct dp_srng reo_cmd_ring; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + struct dp_srng reo2ppe_ring; + struct dp_srng ppe2tcl_ring; + struct dp_ppeds_tx_comp_ring ppeds_comp_ring; +#endif struct dp_srng reo_status_ring; struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; @@ -334,12 +436,19 @@ * - reo_cmd_cache_flush_count */ spinlock_t reo_cmd_lock; + struct list_head reo_cmd_update_rx_queue_list; + /** + * protects access to below field, + * - reo_cmd_update_rx_queue_list + */ + spinlock_t reo_cmd_update_rx_queue_lock; struct ath12k_hp_update_timer reo_cmd_timer; struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; struct ath12k_spt_info *spt_info; u32 num_spt_pages; + u32 rx_spt_base; struct list_head rx_desc_free_list; - struct list_head rx_desc_used_list; + struct list_head rx_ppeds_reuse_list; /* protects the free and used desc list */ spinlock_t rx_desc_lock; @@ -348,30 +457,72 @@ /* protects the free and used desc lists */ spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + struct list_head ppeds_tx_desc_free_list[ATH12K_HW_MAX_QUEUES_PPEDS]; + struct list_head ppeds_tx_desc_reuse_list[ATH12K_HW_MAX_QUEUES_PPEDS]; + struct list_head ppeds_tx_desc_used_list[ATH12K_HW_MAX_QUEUES_PPEDS]; + int ppeds_tx_desc_reuse_list_len[ATH12K_HW_MAX_QUEUES_PPEDS]; + /* protects the free and used desc lists */ + spinlock_t ppeds_tx_desc_lock[ATH12K_HW_MAX_QUEUES_PPEDS]; + + struct ath12k_dp_ppe_vp_profile ppe_vp_profile[PPE_VP_ENTRIES_MAX]; + char ppeds_irq_name[MAX_PPEDS_IRQS][MAX_PPEDS_IRQ_NAME_LEN]; + int ppeds_irq[MAX_PPEDS_IRQS]; +#endif + struct dp_rxdma_ring rx_refill_buf_ring; struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; struct dp_rxdma_ring rxdma_mon_buf_ring; struct dp_rxdma_ring tx_mon_buf_ring; struct ath12k_reo_q_addr_lut reoq_lut; + struct ath12k_reo_q_addr_lut ml_reoq_lut; + unsigned long ppeds_service_running; }; /* HTT definitions */ +#define HTT_TAG_TCL_METADATA_VERSION 5 + +#define HTT_TCL_META_DATA_TYPE_FTM BIT(0) +#define HTT_TCL_META_DATA_TYPE_MISSION GENMASK(1, 0) -#define HTT_TCL_META_DATA_TYPE BIT(0) -#define HTT_TCL_META_DATA_VALID_HTT BIT(1) +#define HTT_TCL_META_DATA_VALID_HTT_FTM BIT(1) +#define HTT_TCL_META_DATA_VALID_HTT_MISSION BIT(2) + +#define HTT_TCL_META_DATA_VALID_HTT \ + (ath12k_ftm_mode ? HTT_TCL_META_DATA_VALID_HTT_FTM : \ + HTT_TCL_META_DATA_VALID_HTT_MISSION) /* vdev meta data */ -#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) -#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) -#define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) +#define HTT_TCL_META_DATA_VDEV_ID_FTM GENMASK(9, 2) +#define HTT_TCL_META_DATA_PDEV_ID_FTM GENMASK(11, 10) +#define HTT_TCL_META_DATA_HOST_INSPECTED_FTM BIT(12) +#define HTT_TCL_META_DATA_VDEV_ID_MISSION GENMASK(10, 3) +#define HTT_TCL_META_DATA_PDEV_ID_MISSION GENMASK(12, 11) +#define HTT_TCL_META_DATA_HOST_INSPECTED_MISSION BIT(13) /* peer meta data */ -#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) +#define HTT_TCL_META_DATA_PEER_ID_FTM GENMASK(15, 2) +#define HTT_TCL_META_DATA_PEER_ID_MISSION GENMASK(15, 3) + +#define HTT_TCL_META_DATA_GET(_val, _mask) \ + (ath12k_ftm_mode ? u32_encode_bits(_val, _mask##_FTM) : \ + u32_encode_bits(_val, _mask##_MISSION)) #define HTT_TX_WBM_COMP_STATUS_OFFSET 8 -/* HTT tx completion is overlaid in wbm_release_ring */ +/* Global sequence number */ +#define HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM 3 +#define HTT_TCL_META_DATA_GLOBAL_SEQ_HOST_INSPECTED BIT(2) +#define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3) +#define HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID 128 + +/* Service Class meta data */ +#define HTT_TCL_META_DATA_TYPE_SVC_ID_BASED 2 +#define HTT_TCL_META_DATA_SAWF_SVC_ID GENMASK(10, 3) +#define HTT_TCL_META_DATA_SAWF_TID_OVERRIDE BIT(12) + +/* HTT tx completion is overlayed in wbm_release_ring v3 version */ #define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) #define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) #define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) @@ -379,7 +530,6 @@ #define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) struct htt_tx_wbm_completion { - __le32 rsvd0[2]; __le32 info0; __le32 info1; __le32 info2; @@ -395,14 +545,27 @@ HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, + HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG = 0x19, HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, + HTT_H2T_MSG_TYPE_SAWF_DEF_Q_MAP_REQ = 0x1c, + HTT_H2T_MSG_TYPE_SAWF_DEF_Q_UNMAP_REQ = 0x1d, + HTT_H2T_MSG_TYPE_SAWF_DEF_Q_MAP_REPORT_REQ = 0x1e, + HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, + HTT_H2T_MSG_TYPE_UMAC_RESET_PREREQUISITE_SETUP = 0x21, + HTT_H2T_MSG_TYPE_UMAC_RESET_START_PRE_RESET = 0x22, }; #define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) +#define HTT_OPTION_TCL_METADATA_VER_V2 2 +#define HTT_OPTION_TAG GENMASK(7, 0) +#define HTT_OPTION_LEN GENMASK(15, 8) +#define HTT_OPTION_VALUE GENMASK(31, 16) +#define HTT_TCL_METADATA_VER_SZ 4 struct htt_ver_req_cmd { __le32 ver_reg_info; + __le32 tcl_metadata_version; } __packed; enum htt_srng_ring_type { @@ -417,11 +580,14 @@ HTT_RXDMA_MONITOR_BUF_RING, HTT_RXDMA_MONITOR_DESC_RING, HTT_RXDMA_MONITOR_DEST_RING, + HTT_RXDMA_HOST_BUF_RING2, HTT_HOST1_TO_FW_RXBUF_RING, HTT_HOST2_TO_FW_RXBUF_RING, HTT_RXDMA_NON_MONITOR_DEST_RING, HTT_TX_MON_HOST2MON_BUF_RING, HTT_TX_MON_MON2HOST_DEST_RING, + HTT_RX_MON_HOST2MON_BUF_RING, + HTT_RX_MON_MON2HOST_DEST_RING, }; /* host -> target HTT_SRING_SETUP message @@ -747,8 +913,15 @@ #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) #define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) + #define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) +#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16) +#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19) +#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22) + #define HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID BIT(26) +#define HTT_RX_RING_SELECTION_CFG_CMD_DROP_THRES_VAL BIT(27) +#define HTT_RX_RING_SELECTION_CFG_CMD_RXMON_GCONF_EN BIT(28) #define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) #define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) @@ -758,6 +931,11 @@ #define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) #define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) +#define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET BIT(23) +#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0) +#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16) +#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0) + enum htt_rx_filter_tlv_flags { HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), @@ -772,6 +950,7 @@ HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), + HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO = BIT(13), }; enum htt_rx_mgmt_pkt_filter_tlv_flags0 { @@ -1060,6 +1239,21 @@ HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ HTT_RX_FILTER_TLV_FLAGS_ATTENTION) +#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \ + (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ + HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ + HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ + HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ + HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ + HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ + HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO) + /* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ #define HTT_RX_TLV_FLAGS_RXDMA_RING \ (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ @@ -1081,8 +1275,25 @@ __le32 rx_mpdu_offset; __le32 rx_msdu_offset; __le32 rx_attn_offset; + __le32 info2; + __le32 reserved[2]; + __le16 rx_mpdu_start_word_mask; + __le16 rx_mpdu_end_word_mask; + __le32 rx_msdu_end_word_mask; + __le32 info3; } __packed; +#define HTT_RX_TLV_FILTER_INFO0_RX_DROP_THRESHOLD GENMASK(9, 0) +#define HTT_RX_TLV_FILTER_INFO0_EN_MSDU_MPDU_LOG_MGMT_TYPE BIT(17) +#define HTT_RX_TLV_FILTER_INFO0_EN_MSDU_MPDU_LOG_CTRL_TYPE BIT(18) +#define HTT_RX_TLV_FILTER_INFO0_EN_MSDU_MPDU_LOG_DATA_TYPE BIT(19) +#define HTT_RX_TLV_FILTER_INFO1_EN_RX_TLV_PKT_OFFSET BIT(0) +#define HTT_RX_TLV_FILTER_INFO1_RX_PKT_TLV_OFFSET GENMASK(14, 1) + +#define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE 32 +#define HTT_RX_RING_DEFAULT_DMA_LENGTH 0x7 +#define HTT_RX_RING_PKT_TLV_OFFSET 0x1 + struct htt_rx_ring_tlv_filter { u32 rx_filter; /* see htt_rx_filter_tlv_flags */ u32 pkt_filter_flags0; /* MGMT */ @@ -1097,6 +1308,17 @@ u16 rx_msdu_end_offset; u16 rx_msdu_start_offset; u16 rx_attn_offset; + u32 rx_drop_threshold; + u32 conf_len_ctrl; + u32 conf_len_mgmt; + u32 conf_len_data; + u32 info0; + u32 info1; + bool drop_threshold_valid; + bool rxmon_disable; + u16 rx_mpdu_start_wmask; + u16 rx_mpdu_end_wmask; + u32 rx_msdu_end_wmask; }; #define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 @@ -1195,8 +1417,13 @@ HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, + HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP = 0x29, + HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP = 0x2a, HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, + HTT_T2H_MSG_TYPE_SAWF_DEF_QUEUES_MAP_REPORT_CONF = 0x2d, + HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND = 0x2e, + HTT_T2H_MSG_TYPE_STREAMING_STATS_IND = 0x2f, }; #define HTT_TARGET_VERSION_MAJOR 3 @@ -1214,6 +1441,8 @@ #define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) #define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) #define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) +#define HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID GENMASK(15, 0) +#define HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL GENMASK(31, 16) #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) #define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 @@ -1249,8 +1478,7 @@ (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) #define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) #define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) -#define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) -#define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) +#define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(23, 16) #define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 #define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 @@ -1283,6 +1511,124 @@ __le32 soc_drop_count_hi; } __packed; +#define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) +#define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) +#define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) + +#define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) +#define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) + +#define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 +#define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 + +enum htt_backpressure_umac_ringid { + HTT_SW_RING_IDX_REO_REO2SW1_RING, + HTT_SW_RING_IDX_REO_REO2SW2_RING, + HTT_SW_RING_IDX_REO_REO2SW3_RING, + HTT_SW_RING_IDX_REO_REO2SW4_RING, + HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, + HTT_SW_RING_IDX_REO_REO2TCL_RING, + HTT_SW_RING_IDX_REO_REO2FW_RING, + HTT_SW_RING_IDX_REO_REO_RELEASE_RING, + HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, + HTT_SW_RING_IDX_TCL_TCL2TQM_RING, + HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, + HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, + HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, + HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, + HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, + HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, + HTT_SW_RING_IDX_REO_REO_CMD_RING, + HTT_SW_RING_IDX_REO_REO_STATUS_RING, + HTT_SW_UMAC_RING_IDX_MAX, +}; + +enum htt_backpressure_lmac_ringid { + HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, + HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, + HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, + HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, + HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, + HTT_SW_RING_IDX_RXDMA2FW_RING, + HTT_SW_RING_IDX_RXDMA2SW_RING, + HTT_SW_RING_IDX_RXDMA2RELEASE_RING, + HTT_SW_RING_IDX_RXDMA2REO_RING, + HTT_SW_RING_IDX_MONITOR_STATUS_RING, + HTT_SW_RING_IDX_MONITOR_BUF_RING, + HTT_SW_RING_IDX_MONITOR_DESC_RING, + HTT_SW_RING_IDX_MONITOR_DEST_RING, + HTT_SW_LMAC_RING_IDX_MAX, +}; + +/* MSG_TYPE => HTT_T2H_SAWF_MSDUQ_INFO_IND + * + * @details + * When SAWF is enabled and a flow is mapped to a policy during the traffic + * flow if the flow is seen the associated service class is conveyed to the + * target via TCL Data Command. Target on the other hand internally creates the + * MSDUQ. Once the target creates the MSDUQ the target sends the information + * of the newly created MSDUQ and some other identifiers to uniquely identity + * the newly created MSDUQ + * + * |31 27| 24|23 16|15|14 11|10|9 8|7 4|3 0| + * |------------------------------+------------------------+--------------| + * | peer ID | HTT qtype | msg type | + * |---------------------------------+--------------+--+---+-------+------| + * | reserved |AST list index|FO|WC | HLOS | remap| + * | | | | | TID | TID | + * |---------------------+------------------------------------------------| + * | reserved1 | tgt_opaque_id | + * |---------------------+------------------------------------------------| + * + * Header fields: + * + * info0 - b'7:0 - msg_type: This will be set to + * 0x2e (HTT_T2H_SAWF_MSDUQ_INFO_IND) + * b'15:8 - HTT qtype + * b'31:16 - peer ID + * + * info1 - b'3:0 - remap TID, as assigned in firmware + * b'7:4 - HLOS TID, as sent by host in TCL Data Command + * hlos_tid : Common to Lithium and Beryllium + * b'9:8 - who_classify_info_sel (WC), as sent by host in + * TCL Data Command : Beryllium + * b10 - flow_override (FO), as sent by host in + * TCL Data Command: Beryllium + * b11:14 - ast_list_idx + * Array index into the list of extension AST entries + * (not the actual AST 16-bit index). + * The ast_list_idx is one-based, with the following + * range of values: + * - legacy targets supporting 16 user-defined + * MSDU queues: 1-2 + * - legacy targets supporting 48 user-defined + * MSDU queues: 1-6 + * - new targets: 0 (peer_id is used instead) + * Note that since ast_list_idx is one-based, + * the host will need to subtract 1 to use it as an + * index into a list of extension AST entries. + * b15:31 - reserved + * + * info2 - b'23:0 - tgt_opaque_id Opaque Tx flow number which is a + * unique MSDUQ id in firmware + * b'24:31 - reserved1 + */ + +#define HTT_T2H_SAWF_MSDUQ_INFO_0_IND_HTT_QTYPE_ID GENMASK(15, 8) +#define HTT_T2H_SAWF_MSDUQ_INFO_0_IND_PEER_ID GENMASK(31, 16) +#define HTT_T2H_SAWF_MSDUQ_INFO_1_IND_REMAP_TID_ID GENMASK(3, 0) +#define HTT_T2H_SAWF_MSDUQ_INFO_1_IND_HLOS_TID_ID GENMASK(7, 4) +#define HTT_T2H_SAWF_MSDUQ_INFO_1_IND_WHO_CLSFY_INFO_SEL_ID GENMASK(9, 8) +#define HTT_T2H_SAWF_MSDUQ_INFO_1_IND_FLOW_OVERRIDE_ID BIT(10) +#define HTT_T2H_SAWF_MSDUQ_INFO_1_IND_AST_INDEX_ID GENMASK(14, 11) +#define HTT_T2H_SAWF_MSDUQ_INFO_2_IND_TGT_OPAQUE_ID GENMASK(23, 0) + +struct htt_t2h_sawf_info_ind { + __le32 info0; + __le32 info1; + __le32 info2; +} __packed; + /* ppdu stats * * @details @@ -1352,6 +1698,8 @@ HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ HTT_PPDU_STATS_BANDWIDTH_DYN = 6, + HTT_PPDU_STATS_BANDWIDTH_DYN_PATTERNS = 7, + HTT_PPDU_STATS_BANDWIDTH_320MHZ = 8, }; #define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) @@ -1386,6 +1734,7 @@ #define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) #define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) +#define HTT_PPDU_STATS_USER_RATE_INFO0_RU_SIZE GENMASK(15, 12) enum HTT_PPDU_STATS_PPDU_TYPE { HTT_PPDU_STATS_PPDU_TYPE_SU, @@ -1400,7 +1749,12 @@ HTT_PPDU_STATS_PPDU_TYPE_MAX }; -#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) +enum HTT_PPDU_STATS_RESP_PPDU_TYPE { + HTT_PPDU_STATS_RESP_PPDU_TYPE_MU_MIMO_UL, + HTT_PPDU_STATS_RESP_PPDU_TYPE_MU_OFDMA_UL, +}; + +#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALID BIT(0) #define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) #define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) @@ -1427,6 +1781,8 @@ le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) #define HTT_USR_RATE_DCM(_val) \ le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) +#define HTT_USR_RATE_PPDU_TYPE(_val) \ + u32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M) #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) @@ -1439,6 +1795,10 @@ #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) #define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) +#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PPDU_TYPE GENMASK(31, 30) + +#define HTT_USR_RESP_RATE_PPDU_TYPE(_val) \ + u32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PPDU_TYPE) struct htt_ppdu_stats_user_rate { u8 tid_num; @@ -1453,6 +1813,8 @@ __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ /* Note: resp_rate_info is only valid for if resp_type is UL */ __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ + __le16 punctured; + __le16 reserved1; } __packed; #define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) @@ -1519,6 +1881,7 @@ #define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) #define HTT_PPDU_STATS_NON_QOS_TID 16 +#define HTT_PPDU_STATS_PPDU_ID GENMASK(24, 0) struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { __le32 ppdu_id; @@ -1559,6 +1922,44 @@ struct list_head list; }; +/* @brief target -> host packet log message + * + * @details + * The following field definitions describe the format of the packet log + * message sent from the target to the host. + * The message consists of a 4-octet header,followed by a variable number + * of 32-bit character values. + * + * |31 16|15 12|11 10|9 8|7 0| + * |------------------------------------------------------------------| + * | payload_size | rsvd |pdev_id|mac_id| msg type | + * |------------------------------------------------------------------| + * | payload | + * |------------------------------------------------------------------| + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as a pktlog message + * Value: HTT_T2H_MSG_TYPE_PKTLOG + * - mac_id + * Bits 9:8 + * Purpose: identifies which MAC/PHY instance generated this pktlog info + * Value: 0-3 + * - pdev_id + * Bits 11:10 + * Purpose: pdev_id + * Value: 0-3 + * 0 (for rings at SOC level), + * 1/2/3 PDEV -> 0/1/2 + * - payload_size + * Bits 31:16 + * Purpose: explicitly specify the payload size + * Value: payload size in bytes (payload size is a multiple of 4 bytes) + */ +struct htt_pktlog_msg { + u32 hdr; + u8 payload[0]; +}; + /* @brief target -> host MLO offset indiciation message * * @details @@ -1756,12 +2157,13 @@ * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv * 5 bit htt_rx_tid_stats_tlv * 6 bit htt_msdu_flow_stats_tlv + * 7 bit htt_peer_sched_stats_tlv * @config_param2: [Bit31 : Bit0] mac_addr31to0 * @config_param3: [Bit15 : Bit0] mac_addr47to32 * [Bit31 : Bit16] reserved */ #define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) -#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f +#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0xff /* Used to set different configs to the specified stats type.*/ struct htt_ext_stats_cfg_params { @@ -1771,10 +2173,128 @@ u32 cfg3; }; -enum vdev_stats_offload_timer_duration { - ATH12K_STATS_TIMER_DUR_500MS = 1, - ATH12K_STATS_TIMER_DUR_1SEC = 2, - ATH12K_STATS_TIMER_DUR_2SEC = 3, +struct htt_h2t_msg_type_vdev_txrx_stats_req { + u32 hdr; + u32 vdev_id_lo_bitmask; + u32 vdev_id_hi_bitmask; +}; + +#define HTT_H2T_RXOLE_PPE_CFG_MSG_TYPE GENMASK(7, 0) +#define HTT_H2T_RXOLE_PPE_CFG_OVERRIDE BIT(8) +#define HTT_H2T_RXOLE_PPE_CFG_REO_DST_IND GENMASK(13, 9) +#define HTT_H2T_RXOLE_PPE_CFG_MULTI_BUF_MSDU_OVRD_EN BIT(14) +#define HTT_H2T_RXOLE_PPE_CFG_INTRA_BUS_OVRD BIT(15) +#define HTT_H2T_RXOLE_PPE_CFG_DECAP_RAW_OVRD BIT(16) +#define HTT_H2T_RXOLE_PPE_CFG_NWIFI_OVRD BIT(17) +#define HTT_H2T_RXOLE_PPE_CFG_IP_FRAG_OVRD BIT(18) + +struct htt_h2t_msg_type_rxdma_rxole_ppe_cfg { + u32 info0; +}; + +#define HTT_H2T_VDEV_TXRX_HDR_MSG_TYPE GENMASK(7, 0) +#define HTT_H2T_VDEV_TXRX_HDR_PDEV_ID GENMASK(15, 8) +#define HTT_H2T_VDEV_TXRX_HDR_ENABLE BIT(16) +#define HTT_H2T_VDEV_TXRX_HDR_INTERVAL GENMASK(24, 17) +#define HTT_H2T_VDEV_TXRX_HDR_RESET_STATS GENMASK(26, 25) +#define HTT_H2T_VDEV_TXRX_LO_BITMASK GENMASK(31, 0) +#define HTT_H2T_VDEV_TXRX_HI_BITMASK GENMASK_ULL(63, 32) + +#define ATH12K_STATS_TIMER_DUR_1SEC 1000 +/* @brief target -> host extended statistics upload + * + * @details + * The following field definitions describe the format of the HTT target + * to host stats upload confirmation message. + * The message contains a cookie echoed from the HTT host->target stats + * upload request, which identifies which request the confirmation is + * for, and a single stats can span over multiple HTT stats indication + * due to the HTT message size limitation so every HTT ext stats indication + * will have tag-length-value stats information elements. + * The tag-length header for each HTT stats IND message also includes a + * status field, to indicate whether the request for the stat type in + * question was fully met, partially met, unable to be met, or invalid + * (if the stat type in question is disabled in the target). + * A Done bit 1's indicate the end of the of stats info elements. + * + * + * |31 16|15 12|11|10 8|7 5|4 0| + * |--------------------------------------------------------------| + * | reserved | msg type | + * |--------------------------------------------------------------| + * | cookie LSBs | + * |--------------------------------------------------------------| + * | cookie MSBs | + * |--------------------------------------------------------------| + * | stats entry length | rsvd | D| S | stat type | + * |--------------------------------------------------------------| + * | type-specific stats info | + * | (see htt_stats.h) | + * |--------------------------------------------------------------| + * Header fields: + * - MSG_TYPE + * Bits 7:0 + * Purpose: Identifies this is a extended statistics upload confirmation + * message. + * Value: 0x1c + * - COOKIE_LSBS + * Bits 31:0 + * Purpose: Provide a mechanism to match a target->host stats confirmation + * message with its preceding host->target stats request message. + * Value: LSBs of the opaque cookie specified by the host-side requestor + * - COOKIE_MSBS + * Bits 31:0 + * Purpose: Provide a mechanism to match a target->host stats confirmation + * message with its preceding host->target stats request message. + * Value: MSBs of the opaque cookie specified by the host-side requestor + * + * Stats Information Element tag-length header fields: + * - STAT_TYPE + * Bits 7:0 + * Purpose: identifies the type of statistics info held in the + * following information element + * Value: htt_dbg_ext_stats_type + * - STATUS + * Bits 10:8 + * Purpose: indicate whether the requested stats are present + * Value: htt_dbg_ext_stats_status + * - DONE + * Bits 11 + * Purpose: + * Indicates the completion of the stats entry, this will be the last + * stats conf HTT segment for the requested stats type. + * Value: + * 0 -> the stats retrieval is ongoing + * 1 -> the stats retrieval is complete + * - LENGTH + * Bits 31:16 + * Purpose: indicate the stats information size + * Value: This field specifies the number of bytes of stats information + * that follows the element tag-length header. + * It is expected but not required that this length is a multiple of + * 4 bytes. + */ + +#define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) +#define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) + +struct ath12k_htt_extd_stats_msg { + u32 info0; + u64 cookie; + u32 info1; + u8 data[0]; +} __packed; + +#define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) +#define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) +#define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) +#define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) +#define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) +#define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) + +struct htt_mac_addr { + u32 mac_addr_l32; + u32 mac_addr_h16; }; static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) @@ -1783,20 +2303,287 @@ memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); } +#define ATH12K_ML_PEER_ID GENMASK(13, 0) +#define ATH12K_ML_PEER_ID_VALID BIT(13) + +#define ATH12K_PEER_ID_INVALID 0x3FFF + +#define ATH12K_HTT_MLO_PEER_MAP_TLV_LINK_INFO_TAG 0 +#define ATH12K_HTT_MAX_MLO_LINKS 3 +#define ATH12K_HTT_MLO_CHIP_ID GENMASK(2, 0) + +struct ath11k_htt_mlo_link_peer_info { + struct htt_tlv tlv_hdr; + u16 sw_peer_id; + u8 vdev_id; + u8 chip_id; +} __packed; + +#define ATH12K_HTT_MLO_PEER_MAP_INFO0_PEER_ID GENMASK(23, 8) +#define ATH12K_HTT_MLO_PEER_MAP_MAC_ADDR_H16 GENMASK(15, 0) + +struct ath11k_htt_mlo_peer_map_msg { + u32 info0; + struct htt_mac_addr mac_addr; + u32 info1; + u32 info2; + u32 info3; + u32 rsvd0; + u32 rsvd1; + struct ath11k_htt_mlo_link_peer_info link_peer[ATH12K_HTT_MAX_MLO_LINKS]; +} __packed; + +#define ATH12K_HTT_MLO_PEER_UNMAP_PEER_ID GENMASK(23, 8) +struct ath11k_htt_mlo_peer_unmap_msg { + u32 info0; +} __packed; + +/** + * struct ath12k_dp_htt_rxdma_ppe_cfg_param - Rx DMA and RxOLE PPE config + * @override: RxDMA override to override the reo_destinatoin_indication + * @reo_dst_ind: REO destination indication value + * @multi_buffer_msdu_override_en: Override the indication for SG + * @intra_bss_override: Rx OLE IntraBSS override + * @decap_raw_override: Rx Decap Raw override + * @decap_nwifi_override: Rx Native override + * @ip_frag_override: IP fragments override + */ +struct ath12k_dp_htt_rxdma_ppe_cfg_param { + u8 override; + u8 reo_dst_ind; + u8 multi_buffer_msdu_override_en; + u8 intra_bss_override; + u8 decap_raw_override; + u8 decap_nwifi_override; + u8 ip_frag_override; +}; + +#define HTT_ATH12K_UMAC_RESET_T2H_DO_PRE_RESET BIT(0) +#define HTT_ATH12K_UMAC_RESET_T2H_DO_POST_RESET_START BIT(1) +#define HTT_ATH12K_UMAC_RESET_T2H_DO_POST_RESET_COMPLETE BIT(2) +#define HTT_ATH12K_UMAC_RESET_T2H_INIT_UMAC_RECOVERY BIT(3) +#define HTT_ATH12K_UMAC_RESET_T2H_INIT_TARGET_RECOVERY_SYNC_USING_UMAC BIT(4) + +enum dp_umac_reset_recover_action { + ATH12K_UMAC_RESET_RX_EVENT_NONE, + ATH12K_UMAC_RESET_INIT_UMAC_RECOVERY, + ATH12K_UMAC_RESET_INIT_TARGET_RECOVERY_SYNC_USING_UMAC, + ATH12K_UMAC_RESET_DO_PRE_RESET, + ATH12K_UMAC_RESET_DO_POST_RESET_START, + ATH12K_UMAC_RESET_DO_POST_RESET_COMPLETE, +}; + +enum dp_umac_reset_tx_cmd { + ATH12K_UMAC_RESET_TX_CMD_TRIGGER_DONE, + ATH12K_UMAC_RESET_TX_CMD_PRE_RESET_DONE, + ATH12K_UMAC_RESET_TX_CMD_POST_RESET_START_DONE, + ATH12K_UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE, +}; + +#define ATH12K_HTT_UMAC_RESET_MSG_SHMEM_PRE_RESET_DONE_SET BIT(0) +#define ATH12K_HTT_UMAC_RESET_MSG_SHMEM_POST_RESET_START_DONE_SET BIT(1) +#define ATH12K_HTT_UMAC_RESET_MSG_SHMEM_POST_RESET_COMPLETE_DONE BIT(2) + +struct ath12k_dp_htt_umac_reset_recovery_msg_shmem_t { + u32 magic_num; + union { + /* + * BIT [0] :- T2H msg to do pre-reset + * BIT [1] :- T2H msg to do post-reset start + * BIT [2] :- T2H msg to do post-reset complete + * BIT [3] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for UMAC hang. + * BIT [4] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for Mode-1 Target Recovery. + * BIT [31 : 5] :- reserved + */ + u32 t2h_msg; + u32 recovery_action; + }; + union { + /* + * BIT [0] :- H2T msg to send pre-reset done + * BIT [1] :- H2T msg to send post-reset start done + * BIT [2] :- H2T msg to send post-reset complete done + * BIT [3] :- H2T msg to start pre-reset. This is deprecated. + * BIT [31 : 4] :- reserved + */ + u32 h2t_msg; + u32 recovery_action_done; + }; +}; + +struct ath12k_umac_reset_ts { + u64 trigger_start; + u64 trigger_done; + u64 pre_reset_start; + u64 pre_reset_done; + u64 post_reset_start; + u64 post_reset_done; + u64 post_reset_complete_start; + u64 post_reset_complete_done; +}; + +struct ath12k_dp_umac_reset { + struct ath12k_base *ab; + dma_addr_t shmem_paddr_unaligned; + void *shmem_vaddr_unaligned; + dma_addr_t shmem_paddr_aligned; + struct ath12k_dp_htt_umac_reset_recovery_msg_shmem_t *shmem_vaddr_aligned; + size_t shmem_size; + uint32_t magic_num; + int intr_offset; + struct tasklet_struct intr_tq; + int irq_num; + struct ath12k_umac_reset_ts ts; + bool umac_pre_reset_in_prog; +}; + +struct ath12k_htt_umac_reset_setup_cmd_params { + uint32_t msi_data; + uint32_t addr_lo; + uint32_t addr_hi; +}; + +struct htt_h2t_paddr_size { + u32 size; + u32 addr_lo; + u32 addr_hi; +}; + +#define HTT_H2T_MSG_TYPE_SET GENMASK(7, 0) +#define HTT_H2T_MSG_METHOD GENMASK(11, 8) +#define HTT_T2H_MSG_METHOD GENMASK(15, 12) + +#define ATH12K_DP_UMAC_RESET_SHMEM_MAGIC_NUM 0xDEADBEEF +#define ATH12K_DP_UMAC_RESET_SHMEM_ALIGN 8 + +/** + * @brief HTT_H2T_MSG_TYPE_UMAC_RESET_PREREQUISITE_SETUP message + * + * @details + * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP message is sent + * by the host to provide prerequisite info to target for the UMAC hang + * recovery feature. + * The info sent in this H2T message are T2H message method, H2T message + * method, T2H MSI interrupt number and physical start address, size of + * the shared memory (refers to the shared memory dedicated for messaging + * between host and target when the DUT is in UMAC hang recovery mode). + * This H2T message is expected to be only sent if the WMI service bit + * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target. + * + * |31 16|15 12|11 8|7 0| + * |-------------------------------+--------------+--------------+------------| + * | reserved |h2t msg method|t2h msg method| msg_type | + * |--------------------------------------------------------------------------| + * | t2h msi interrupt number | + * |--------------------------------------------------------------------------| + * | shared memory area size | + * |--------------------------------------------------------------------------| + * | shared memory area physical address low | + * |--------------------------------------------------------------------------| + * | shared memory area physical address high | + * |--------------------------------------------------------------------------| + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type + * (HTT_H2T_MSG_TYPE_UMAC_RESET_PREREQUISITE_SETUP) + * b'8:11 - t2h_msg_method: indicates method to be used for + * T2H communication in UMAC hang recovery mode. + * Value zero indicates MSI interrupt (default method). + * Refer to htt_umac_hang_recovery_msg_method enum. + * b'12:15 - h2t_msg_method: indicates method to be used for + * H2T communication in UMAC hang recovery mode. + * Value zero indicates polling by target for this h2t msg + * during UMAC hang recovery mode. + * Refer to htt_umac_hang_recovery_msg_method enum. + * b'16:31 - reserved. + * dword1 - b'0:31 - t2h_msi_data: MSI data to be used for + * T2H communication in UMAC hang recovery mode. + * dword2 - b'0:31 - size: size of shared memory dedicated for messaging + * only when in UMAC hang recovery mode. + * This refers to size in bytes. + * dword3 - b'0:31 - physical_address_lo: lower 32 bit physical address + * of the shared memory dedicated for messaging only when + * in UMAC hang recovery mode. + * dword4 - b'0:31 - physical_address_hi: higher 32 bit physical address + * of the shared memory dedicated for messaging only when + * in UMAC hang recovery mode. + */ + +struct htt_dp_umac_reset_setup_req_cmd { + u32 msg_info; + u32 msi_data; + struct htt_h2t_paddr_size msg_shared_mem; +}__packed; + +/** + * @brief HTT_H2T_MSG_TYPE_UMAC_RESET_START_PRE_RESET message + * + * @details + * The HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET is a SOC level + * HTT message sent by the host to indicate that the target needs to start the + * UMAC hang recovery feature from the point of pre-reset routine. + * The purpose of this H2T message is to have host synchronize and trigger + * UMAC recovery across all targets. + * The info sent in this H2T message is the flag to indicate whether the + * target needs to execute UMAC-recovery in context of the Initiator or + * Non-Initiator. + * This H2T message is expected to be sent as response to the + * initiate_umac_recovery indication from the Initiator target attached to + * this same host. + * This H2T message is expected to be only sent if the WMI service bit + * WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT was firstly indicated by the target + * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent + * beforehand. + * + * |31 10|9|8|7 0| + * |-----------------------------------------------------------| + * | reserved |U|I| msg_type | + * |-----------------------------------------------------------| + * Where: + * I = is_initiator + * U = is_umac_hang + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type + * (HTT_H2T_MSG_TYPE_UMAC_RESET_START_PRE_RESET) + * b'8 - is_initiator: indicates whether the target needs to + * execute the UMAC-recovery in context of the Initiator or + * Non-Initiator. + * The value zero indicates this target is Non-Initiator. + * b'9 - is_umac_hang: indicates whether MLO UMAC recovery + * executed in context of UMAC hang or Target recovery. + * b'10:31 - reserved. + */ +struct h2t_umac_hang_recovery_start_pre_reset { + u8 hdr; +} __packed; + +#define HTT_H2T_UMAC_RESET_MSG_TYPE GENMASK(7, 0) +#define HTT_H2T_UMAC_RESET_IS_INITIATOR_SET BIT(8) +#define HTT_H2T_UMAC_RESET_IS_TARGET_RECOVERY_SET BIT(9) + int ath12k_dp_service_srng(struct ath12k_base *ab, struct ath12k_ext_irq_grp *irq_grp, int budget); int ath12k_dp_htt_connect(struct ath12k_dp *dp); -void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_vif *arvif); +void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif); void ath12k_dp_free(struct ath12k_base *ab); int ath12k_dp_alloc(struct ath12k_base *ab); void ath12k_dp_cc_config(struct ath12k_base *ab); +void ath12k_dp_partner_cc_init(struct ath12k_base *ab); int ath12k_dp_pdev_alloc(struct ath12k_base *ab); void ath12k_dp_pdev_pre_alloc(struct ath12k_base *ab); void ath12k_dp_pdev_free(struct ath12k_base *ab); int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, int mac_id, enum hal_ring_type ring_type); -int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); +int ath12k_dp_peer_default_route_setup(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta); +int ath12k_dp_peer_setup(struct ath12k *ar, struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta); void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, @@ -1813,4 +2600,24 @@ u32 cookie); struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, u32 desc_id); +void ath12k_dp_tx_update_bank_profile(struct ath12k_link_vif *arvif); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +int ath12k_ppeds_dp_srng_alloc(struct ath12k_base *ab, struct dp_srng *ring, + enum hal_ring_type type, int ring_num, + int num_entries); +int ath12k_ppeds_dp_srng_init(struct ath12k_base *ab, struct dp_srng *ring, + enum hal_ring_type type, int ring_num, + int mac_id, int num_entries, u32 idx); +struct ath12k_ppeds_tx_desc_info *ath12k_dp_get_ppeds_tx_desc(struct ath12k_base *ab, + u32 desc_id); +int ath12k_dp_cc_ppeds_desc_init(struct ath12k_base *ab); +int ath12k_dp_cc_ppeds_desc_cleanup(struct ath12k_base *ab); +void ath12k_dp_ppeds_tx_cmem_init(struct ath12k_base *ab, struct ath12k_dp *dp); +#endif +void ath12k_umac_reset_handle_post_reset_start(struct ath12k_base *ab); +void ath12k_umac_reset_notify_target_sync_and_send(struct ath12k_base *ab, + enum dp_umac_reset_tx_cmd tx_event); +void ath12k_dp_reset_interrupt_mask(struct ath12k_base *ab); +void ath12k_dp_restore_interrupt_mask(struct ath12k_base *ab); +bool ath12k_dp_umac_reset_in_progress(struct ath12k_base *ab); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp_mon.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_mon.c --- linux-6.4/drivers/net/wireless/ath/ath12k/dp_mon.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_mon.c 2024-03-18 14:40:14.851741333 +0100 @@ -10,6 +10,22 @@ #include "dp_tx.h" #include "peer.h" +#define ATH12K_LE32_DEC_ENC(value, decode_bits, encode_bits) \ + le32_encode_bits(le32_get_bits(value, decode_bits), encode_bits) + +#define ATH12K_LE64_DEC_ENC(value, decode_bits, encode_bits) \ + le64_encode_bits(le64_get_bits(value, decode_bits), encode_bits) + +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT +extern int g_bonded_interface_model; +#endif + +#define LE32_DEC_ENC(value, dec_bits, enc_bits) \ + le32_encode_bits(le32_get_bits(value, dec_bits), enc_bits) + +#define LE64_DEC_ENC(value, dec_bits, enc_bits) \ + le64_encode_bits(le64_get_bits(value, dec_bits), enc_bits) + static void ath12k_dp_mon_rx_handle_ofdma_info(void *rx_tlv, struct hal_rx_user_status *rx_user_status) { @@ -33,10 +49,10 @@ rx_user_status->mpdu_ok_byte_count = u32_get_bits(mpdu_ok_byte_count, - HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT); + HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT); rx_user_status->mpdu_err_byte_count = u32_get_bits(mpdu_err_byte_count, - HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT); + HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT); } static void @@ -107,15 +123,11 @@ if (ppdu_info->is_stbc && nsts > 0) nsts = ((nsts + 1) >> 1) - 1; - ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK); + ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK) + 1; ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW); ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED); group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID); - if (group_id == 0 || group_id == 63) - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; - else - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; ppdu_info->vht_flag_values5 = group_id; ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) | ppdu_info->nss); @@ -137,8 +149,7 @@ ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC); ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING); ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI); - ppdu_info->nss = (ppdu_info->mcs >> 3); - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; + ppdu_info->nss = (ppdu_info->mcs >> 3) + 1; } static void ath12k_dp_mon_parse_l_sig_b(u8 *tlv_data, @@ -172,7 +183,6 @@ ppdu_info->rate = rate; ppdu_info->cck_flag = 1; - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; } static void ath12k_dp_mon_parse_l_sig_a(u8 *tlv_data, @@ -214,7 +224,6 @@ } ppdu_info->rate = rate; - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; } static void ath12k_dp_mon_parse_he_sig_b2_ofdma(u8 *tlv_data, @@ -249,10 +258,9 @@ value = value << HE_STA_ID_SHIFT; ppdu_info->he_data4 |= value; - ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS); + ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS) + 1; ppdu_info->beamformed = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF); - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; } static void ath12k_dp_mon_parse_he_sig_b2_mu(u8 *tlv_data, @@ -279,7 +287,7 @@ value = value << HE_STA_ID_SHIFT; ppdu_info->he_data4 |= value; - ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS); + ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS) + 1; } static void ath12k_dp_mon_parse_he_sig_b1_mu(u8 *tlv_data, @@ -292,9 +300,8 @@ ru_tones = u32_get_bits(info0, HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION); - ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); + ppdu_info->ru_alloc = ath12k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); ppdu_info->he_RU[0] = ru_tones; - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; } static void ath12k_dp_mon_parse_he_sig_mu(u8 *tlv_data, @@ -429,7 +436,6 @@ ppdu_info->is_stbc = info1 & HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC; - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; } static void ath12k_dp_mon_parse_he_sig_su(u8 *tlv_data, @@ -577,18 +583,877 @@ ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); - ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); + ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS) + 1; ppdu_info->dcm = dcm; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_u_sig_cmn(u8 *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; + struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; + + ppdu_info->usig_common |= + IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER_KNOWN | + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN | + IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL_KNOWN | + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR_KNOWN | + IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP_KNOWN | + ATH12K_LE32_DEC_ENC(usig->usig_2.tb.info0, + HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC) | + ATH12K_LE32_DEC_ENC(usig_1->info0, + HAL_RX_USIG_CMN_INFO0_PHY_VERSION, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER) | + ATH12K_LE32_DEC_ENC(usig_1->info0, + HAL_RX_USIG_CMN_INFO0_BW, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW) | + ATH12K_LE32_DEC_ENC(usig_1->info0, + HAL_RX_USIG_CMN_INFO0_UL_DL, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL) | + ATH12K_LE32_DEC_ENC(usig_1->info0, + HAL_RX_USIG_CMN_INFO0_BSS_COLOR, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR) | + ATH12K_LE32_DEC_ENC(usig_1->info0, + HAL_RX_USIG_CMN_INFO0_TXOP, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP); + + ppdu_info->u_sig_info.bw = le32_get_bits(usig_1->info0, + HAL_RX_USIG_CMN_INFO0_BW); + + ppdu_info->bw = ppdu_info->u_sig_info.bw; + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + + +static inline u32 +ath12k_dp_mon_hal_rx_parse_u_sig_tb(u8 *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; + struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb; + + ppdu_info->usig_mask |= + IEEE80211_RADIOTAP_EHT_USIG1_TB_B20_B25_DISREGARD | + ATH12K_LE32_DEC_ENC(usig_tb->info0, + HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE, + IEEE80211_RADIOTAP_EHT_USIG2_TB_B0_B1_PPDU_TYPE) | + IEEE80211_RADIOTAP_EHT_USIG2_TB_B2_VALIDATE | + ATH12K_LE32_DEC_ENC(usig_tb->info0, + HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1, + IEEE80211_RADIOTAP_EHT_USIG2_TB_B3_B6_SPATIAL_REUSE_1) | + ATH12K_LE32_DEC_ENC(usig_tb->info0, + HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2, + IEEE80211_RADIOTAP_EHT_USIG2_TB_B7_B10_SPATIAL_REUSE_2) | + IEEE80211_RADIOTAP_EHT_USIG2_TB_B11_B15_DISREGARD | + ATH12K_LE32_DEC_ENC(usig_tb->info0, + HAL_RX_USIG_TB_INFO0_CRC, + IEEE80211_RADIOTAP_EHT_USIG2_TB_B16_B19_CRC) | + ATH12K_LE32_DEC_ENC(usig_tb->info0, + HAL_RX_USIG_TB_INFO0_TAIL, + IEEE80211_RADIOTAP_EHT_USIG2_TB_B20_B25_TAIL); + + ppdu_info->u_sig_info.ppdu_type_comp_mode = + le32_get_bits(usig_tb->info0, + HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE); + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline uint32_t +ath12k_dp_mon_hal_rx_parse_u_sig_mu(u8 *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; + struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu; + + ppdu_info->usig_mask |= + IEEE80211_RADIOTAP_EHT_USIG1_MU_B20_B24_DISREGARD | + IEEE80211_RADIOTAP_EHT_USIG1_MU_B25_VALIDATE | + ATH12K_LE32_DEC_ENC(usig_mu->info0, + HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE, + IEEE80211_RADIOTAP_EHT_USIG2_MU_B0_B1_PPDU_TYPE) | + IEEE80211_RADIOTAP_EHT_USIG2_MU_B2_VALIDATE | + ATH12K_LE32_DEC_ENC(usig_mu->info0, + HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO, + IEEE80211_RADIOTAP_EHT_USIG2_MU_B3_B7_PUNCTURED_INFO) | + IEEE80211_RADIOTAP_EHT_USIG2_MU_B8_VALIDATE | + ATH12K_LE32_DEC_ENC(usig_mu->info0, + HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS, + IEEE80211_RADIOTAP_EHT_USIG2_MU_B9_B10_SIG_MCS) | + ATH12K_LE32_DEC_ENC(usig_mu->info0, + HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM, + IEEE80211_RADIOTAP_EHT_USIG2_MU_B11_B15_EHT_SIG_SYMBOLS) | + ATH12K_LE32_DEC_ENC(usig_mu->info0, + HAL_RX_USIG_MU_INFO0_CRC, + IEEE80211_RADIOTAP_EHT_USIG2_MU_B16_B19_CRC) | + ATH12K_LE32_DEC_ENC(usig_mu->info0, + HAL_RX_USIG_TB_INFO0_TAIL, + IEEE80211_RADIOTAP_EHT_USIG2_MU_B20_B25_TAIL); + + ppdu_info->u_sig_info.ppdu_type_comp_mode = + le32_get_bits(usig_mu->info0, + HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE); + ppdu_info->u_sig_info.eht_sig_mcs = + le32_get_bits(usig_mu->info0, + HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS); + ppdu_info->u_sig_info.num_eht_sig_sym = + le32_get_bits(usig_mu->info0, + HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM); + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_u_sig_hdr(u8 *rx_tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; + struct hal_mon_usig_cmn *usig_cmn = &usig->usig_1; + u8 comp_mode; + bool ul_dl; + + ppdu_info->usig_flags = 1; + + ath12k_dp_mon_hal_rx_parse_u_sig_cmn(rx_tlv, ppdu_info); + + ul_dl = u32_get_bits(__le32_to_cpu(usig_cmn->info0), HAL_RX_USIG_CMN_INFO0_UL_DL); + + comp_mode = u32_get_bits(__le32_to_cpu(usig->usig_2.mu.info0), + HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE); + + if (comp_mode == 0 && ul_dl) + return ath12k_dp_mon_hal_rx_parse_u_sig_tb(rx_tlv, ppdu_info); + else + return ath12k_dp_mon_hal_rx_parse_u_sig_mu(rx_tlv, ppdu_info); +} + +static enum hal_rx_mon_status +ath12k_dp_mon_hal_aggr_tlv(struct hal_rx_mon_ppdu_info *ppdu_info, + u16 tlv_len, u8 *tlv_data) +{ + if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { + memcpy(ppdu_info->tlv_aggr.buf + ppdu_info->tlv_aggr.cur_len, + tlv_data, tlv_len); + ppdu_info->tlv_aggr.cur_len += tlv_len; + } + + return HAL_RX_MON_STATUS_PPDU_NOT_DONE; +} + +static inline bool +ath12k_dp_mon_hal_rx_is_mu_mimo_user(struct hal_rx_mon_ppdu_info *ppdu_info) +{ + if (ppdu_info->u_sig_info.ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_SU && + ppdu_info->u_sig_info.ul_dl == 1) + return true; + + return false; +} + +static inline bool +ath12k_dp_mon_hal_rx_is_frame_type_ndp(struct hal_rx_mon_ppdu_info *ppdu_info) +{ + if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 && + ppdu_info->u_sig_info.eht_sig_mcs == 0 && + ppdu_info->u_sig_info.num_eht_sig_sym == 0) + return true; + + return false; +} + +static inline bool +ath12k_dp_mon_hal_rx_is_non_ofdma(struct hal_rx_mon_ppdu_info *ppdu_info) +{ + u32 ppdu_type_comp_mode = ppdu_info->u_sig_info.ppdu_type_comp_mode; + u32 ul_dl = ppdu_info->u_sig_info.ul_dl; + + if ((ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 0) || + (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_OFDMA && ul_dl == 0) || + (ppdu_type_comp_mode == HAL_RX_RECEPTION_TYPE_MU_MIMO && ul_dl == 1)) + return true; + + return false; +} + +static inline bool +ath12k_dp_mon_hal_rx_is_ofdma(struct hal_rx_mon_ppdu_info *ppdu_info) +{ + if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && + ppdu_info->u_sig_info.ul_dl == 0) + return true; + + return false; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_eht_sig_ndp(u8 *tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp = + (struct hal_eht_sig_ndp_cmn_eb *)tlv; + + ppdu_info->eht_known |= + IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE | + IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF | + IEEE80211_RADIOTAP_EHT_KNOWN_NSS_S | + IEEE80211_RADIOTAP_EHT_KNOWN_BEAMFORMED_S | + IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_S | + IEEE80211_RADIOTAP_EHT_KNOWN_CRC1 | + IEEE80211_RADIOTAP_EHT_KNOWN_TAIL1; + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, + HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE, + IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE); + /* + * GI and LTF size are separately indicated in radiotap header + * and hence will be parsed from other TLV + */ + + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, + HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM, + IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF); + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, + HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC, + IEEE80211_RADIOTAP_EHT_DATA0_CRC1_O); + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, + HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD, + IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_S); + + ppdu_info->eht_data[7] |= + ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, + HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS, + IEEE80211_RADIOTAP_EHT_DATA7_NSS_S); + + ppdu_info->eht_data[7] |= + ATH12K_LE32_DEC_ENC(eht_sig_ndp->info0, + HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED, + IEEE80211_RADIOTAP_EHT_DATA7_BEAMFORMED_S); + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_usig_overflow(u8 *tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_eht_sig_cc_usig_overflow *usig_ovflow = + (struct hal_eht_sig_cc_usig_overflow *)tlv; + + ppdu_info->eht_known |= + IEEE80211_RADIOTAP_EHT_KNOWN_SPATIAL_REUSE | + IEEE80211_RADIOTAP_EHT_KNOWN_EHT_LTF | + IEEE80211_RADIOTAP_EHT_KNOWN_LDPC_EXTRA_SYM_OM | + IEEE80211_RADIOTAP_EHT_KNOWN_PRE_PADD_FACOR_OM | + IEEE80211_RADIOTAP_EHT_KNOWN_PE_DISAMBIGUITY_OM | + IEEE80211_RADIOTAP_EHT_KNOWN_DISREGARD_O; + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(usig_ovflow->info0, + HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE, + IEEE80211_RADIOTAP_EHT_DATA0_SPATIAL_REUSE); + + /* + * GI and LTF size are separately indicated in radiotap header + * and hence will be parsed from other TLV + */ + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(usig_ovflow->info0, + HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM, + IEEE80211_RADIOTAP_EHT_DATA0_EHT_LTF); + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(usig_ovflow->info0, + HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM, + IEEE80211_RADIOTAP_EHT_DATA0_LDPC_EXTRA_SYM_OM); + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(usig_ovflow->info0, + HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR, + IEEE80211_RADIOTAP_EHT_DATA0_PRE_PADD_FACOR_OM); + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(usig_ovflow->info0, + HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY, + IEEE80211_RADIOTAP_EHT_DATA0_PE_DISAMBIGUITY_OM); + + ppdu_info->eht_data[0] |= + ATH12K_LE32_DEC_ENC(usig_ovflow->info0, + HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD, + IEEE80211_RADIOTAP_EHT_DATA0_DISREGARD_O); + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_ru_allocation(u8 *tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + u64 *ehtsig_tlv = (u64 *)tlv; + struct hal_eht_sig_ofdma_cmn_eb1 *ofdma_cmn_eb1; + struct hal_eht_sig_ofdma_cmn_eb2 *ofdma_cmn_eb2; + + ofdma_cmn_eb1 = (struct hal_eht_sig_ofdma_cmn_eb1 *)ehtsig_tlv; + ofdma_cmn_eb2 = (struct hal_eht_sig_ofdma_cmn_eb2 *)(ehtsig_tlv + 1); + +/*FIX ME to get CC2 values*/ + + switch (ppdu_info->u_sig_info.bw) { + case HAL_EHT_BW_320_2: + case HAL_EHT_BW_320_1: + /* CC1 2::3 */ + ppdu_info->eht_data[4] |= + IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, + HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3, + IEEE80211_RADIOTAP_EHT_DATA4_RU_ALLOC_CC_1_2_3); + + /* CC1 2::4 */ + ppdu_info->eht_data[5] |= + IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, + HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4, + IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_4); + + /* CC1 2::5 */ + ppdu_info->eht_data[5] |= + IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, + HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5, + IEEE80211_RADIOTAP_EHT_DATA5_RU_ALLOC_CC_1_2_5); + + /* CC1 2::6 */ + ppdu_info->eht_data[6] |= + IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, + HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6, + IEEE80211_RADIOTAP_EHT_DATA6_RU_ALLOC_CC_1_2_6); + + /* fallthrough */ + fallthrough; + + case HAL_EHT_BW_160: + /* CC1 2::1 */ + ppdu_info->eht_data[3] |= + IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, + HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1, + IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_1); + /* CC1 2::2 */ + ppdu_info->eht_data[3] |= + IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb2->info0, + HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2, + IEEE80211_RADIOTAP_EHT_DATA3_RU_ALLOC_CC_1_2_2); + + /* fallthrough */ + fallthrough; + + case HAL_EHT_BW_80: + /* CC1 1::2 */ + ppdu_info->eht_data[2] |= + IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0, + HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2, + IEEE80211_RADIOTAP_EHT_DATA2_RU_ALLOC_CC_1_1_2); + + /* fallthrough */ + fallthrough; + + case HAL_EHT_BW_40: + fallthrough; + case HAL_EHT_BW_20: + /* CC1 1::1 */ + ppdu_info->eht_data[1] |= + IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1_KNOWN | + ATH12K_LE64_DEC_ENC(ofdma_cmn_eb1->info0, + HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1, + IEEE80211_RADIOTAP_EHT_DATA1_RU_ALLOC_CC_1_1_1); + break; + default: + break; + } + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline uint32_t +ath12k_dp_mon_hal_rx_parse_non_ofdma_users(u8 *tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb = + (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv; + + ppdu_info->eht_known |= IEEE80211_RADIOTAP_EHT_KNOWN_NR_NON_OFDMA_USERS_M; + ppdu_info->eht_data[7] |= + ATH12K_LE32_DEC_ENC(non_ofdma_cmn_eb->info0, + HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS, + IEEE80211_RADIOTAP_EHT_DATA7_NUM_OF_NON_OFDMA_USERS); + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_eht_sig_mumimo_user_info(u8 *tlv, + struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_eht_sig_mu_mimo_user_info *user_info; + u32 user_idx = ppdu_info->num_eht_user_info_valid; + + if (ppdu_info->num_eht_user_info_valid >= ARRAY_SIZE(ppdu_info->eht_user_info)) + return HAL_TLV_STATUS_PPDU_NOT_DONE; + + user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv; + + ppdu_info->eht_user_info[user_idx] |= + IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN | + IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | + IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN | + IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_KNOWN_M | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID, + IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING, + IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS, + IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING, + IEEE80211_RADIOTAP_EHT_USER_INFO_SPATIAL_CONFIG_M); + + ppdu_info->mcs = le32_get_bits(user_info->info0, + HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS); + + /* FIXME: get USER_ENCODING_BLOCK_CRC */ + + ppdu_info->num_eht_user_info_valid++; + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_eht_sig_non_mumimo_user(u8 *tlv, + struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_eht_sig_non_mu_mimo_user_info *user_info; + u32 user_idx = ppdu_info->num_eht_user_info_valid; + + if (ppdu_info->num_eht_user_info_valid >= ARRAY_SIZE(ppdu_info->eht_user_info)) + return HAL_TLV_STATUS_PPDU_NOT_DONE; + + user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv; + + ppdu_info->eht_user_info[user_idx] |= + IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID_KNOWN | + IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | + IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN | + IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | + IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_KNOWN_O | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID, + IEEE80211_RADIOTAP_EHT_USER_INFO_STA_ID) | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING, + IEEE80211_RADIOTAP_EHT_USER_INFO_CODING) | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS, + IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS, + IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O) | + ATH12K_LE32_DEC_ENC(user_info->info0, + HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED, + IEEE80211_RADIOTAP_EHT_USER_INFO_BEAMFORMING_O); + + ppdu_info->mcs = le32_get_bits(user_info->info0, + HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS); + + ppdu_info->nss = le32_get_bits(user_info->info0, + HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS) + 1; + + ppdu_info->num_eht_user_info_valid++; + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_eht_sig_non_ofdma(u8 *tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + void *user_info = (void *)((u8 *)tlv + HTT_TLV_HDR_LEN); + + ath12k_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info); + ath12k_dp_mon_hal_rx_parse_non_ofdma_users(tlv, ppdu_info); + + if (ath12k_dp_mon_hal_rx_is_mu_mimo_user(ppdu_info)) + ath12k_dp_mon_hal_rx_parse_eht_sig_mumimo_user_info(user_info, + ppdu_info); + else + ath12k_dp_mon_hal_rx_parse_eht_sig_non_mumimo_user(user_info, + ppdu_info); + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline u32 +ath12k_dp_mon_hal_rx_parse_eht_sig_ofdma(u8 *tlv, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + u64 *eht_sig_tlv = (u64 *)tlv; + void *user_info = (void *)(eht_sig_tlv + 2); + + ath12k_dp_mon_hal_rx_parse_usig_overflow(tlv, ppdu_info); + ath12k_dp_mon_hal_rx_parse_ru_allocation (tlv, ppdu_info); + ath12k_dp_mon_hal_rx_parse_eht_sig_non_mumimo_user(user_info, + ppdu_info); + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static void +ath12k_dp_mon_parse_eht_sig_hdr(struct hal_rx_mon_ppdu_info *ppdu_info, + u8 *tlv_data) +{ + ppdu_info->eht_flags = 1; + + if (ath12k_dp_mon_hal_rx_is_frame_type_ndp(ppdu_info)) + ath12k_dp_mon_hal_rx_parse_eht_sig_ndp(tlv_data, ppdu_info); + else if (ath12k_dp_mon_hal_rx_is_non_ofdma(ppdu_info)) + ath12k_dp_mon_hal_rx_parse_eht_sig_non_ofdma(tlv_data, ppdu_info); + else if (ath12k_dp_mon_hal_rx_is_ofdma(ppdu_info)) + ath12k_dp_mon_hal_rx_parse_eht_sig_ofdma(tlv_data, ppdu_info); +} + +static u32 +ath12k_dp_mon_hal_rx_status_process_aggr_tlv(struct hal_rx_mon_ppdu_info *ppdu_info) +{ + u32 aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag; + + if (aggr_tlv_tag == HAL_PHYRX_GENERIC_EHT_SIG) + ath12k_dp_mon_parse_eht_sig_hdr(ppdu_info, ppdu_info->tlv_aggr.buf); + + ppdu_info->tlv_aggr.in_progress = 0; + ppdu_info->tlv_aggr.cur_len = 0; + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +static inline enum ath12k_eht_ru_size +hal_rx_mon_hal_ru_size_to_ath12k_ru_size(u32 hal_ru_size) +{ + switch (hal_ru_size) { + case HAL_EHT_RU_26: + return ATH12K_EHT_RU_26; + case HAL_EHT_RU_52: + return ATH12K_EHT_RU_52; + case HAL_EHT_RU_78: + return ATH12K_EHT_RU_52_26; + case HAL_EHT_RU_106: + return ATH12K_EHT_RU_106; + case HAL_EHT_RU_132: + return ATH12K_EHT_RU_106_26; + case HAL_EHT_RU_242: + return ATH12K_EHT_RU_242; + case HAL_EHT_RU_484: + return ATH12K_EHT_RU_484; + case HAL_EHT_RU_726: + return ATH12K_EHT_RU_484_242; + case HAL_EHT_RU_996: + return ATH12K_EHT_RU_996; + case HAL_EHT_RU_996x2: + return ATH12K_EHT_RU_996x2; + case HAL_EHT_RU_996x3: + return ATH12K_EHT_RU_996x3; + case HAL_EHT_RU_996x4: + return ATH12K_EHT_RU_996x4; + case HAL_EHT_RU_NONE: + return ATH12K_EHT_RU_INVALID; + case HAL_EHT_RU_996_484: + return ATH12K_EHT_RU_996_484; + case HAL_EHT_RU_996x2_484: + return ATH12K_EHT_RU_996x2_484; + case HAL_EHT_RU_996x3_484: + return ATH12K_EHT_RU_996x3_484; + case HAL_EHT_RU_996_484_242: + return ATH12K_EHT_RU_996_484_242; + default: + return ATH12K_EHT_RU_INVALID; + } +} + +static inline void hal_rx_ul_ofdma_ru_size_to_width(u32 ru_size, u32 *ru_width) +{ + uint32_t width = 0; + + switch (ru_size) { + case ATH12K_EHT_RU_26: + width = RU_26; + break; + case ATH12K_EHT_RU_52: + width = RU_52; + break; + case ATH12K_EHT_RU_52_26: + width = RU_52_26; + break; + case ATH12K_EHT_RU_106: + width = RU_106; + break; + case ATH12K_EHT_RU_106_26: + width = RU_106_26; + break; + case ATH12K_EHT_RU_242: + width = RU_242; + break; + case ATH12K_EHT_RU_484: + width = RU_484; + break; + case ATH12K_EHT_RU_484_242: + width = RU_484_242; + break; + case ATH12K_EHT_RU_996: + width = RU_996; + break; + case ATH12K_EHT_RU_996_484: + width = RU_996_484; + break; + case ATH12K_EHT_RU_996_484_242: + width = RU_996_484_242; + break; + case ATH12K_EHT_RU_996x2: + width = RU_2X996; + break; + case ATH12K_EHT_RU_996x2_484: + width = RU_2X996_484; + break; + case ATH12K_EHT_RU_996x3: + width = RU_3X996; + break; + case ATH12K_EHT_RU_996x3_484: + width = RU_3X996_484; + break; + case ATH12K_EHT_RU_996x4: + width = RU_4X996; + break; + default: + break; + } + + *ru_width = width; +} + +static u32 +ath12k_dp_mon_hal_rx_parse_receive_user_info(u8 *tlv, u16 user_id, + struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct hal_receive_user_info *rx_usr_info = (struct hal_receive_user_info *)tlv; + struct hal_rx_user_status *mon_rx_user_status = NULL; + u64 ru_index_320mhz = 0; + u32 ru_index_per80mhz; + u32 ru_size = 0, num_80mhz_with_ru = 0, ru_start_index_80_0; + u32 ru_index = HAL_EHT_RU_INVALID; + u32 rtap_ru_size = ATH12K_EHT_RU_INVALID; + u32 ru_width, reception_type, ru_type_80_0; + u32 ru_type_80_1, ru_start_index_80_1, ru_type_80_2, ru_start_index_80_2; + u32 ru_type_80_3, ru_start_index_80_3; + + reception_type = u32_get_bits(__le32_to_cpu(rx_usr_info->info0), + HAL_RX_USR_INFO0_RECEPTION_TYPE); + + switch (reception_type) { + case HAL_RECEPTION_TYPE_SU: ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; + break; + case HAL_RECEPTION_TYPE_DL_MU_MIMO: + case HAL_RECEPTION_TYPE_UL_MU_MIMO: + ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; + break; + case HAL_RECEPTION_TYPE_DL_MU_OFMA: + case HAL_RECEPTION_TYPE_UL_MU_OFDMA: + ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; + break; + case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: + case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: + ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO; + } + + ppdu_info->is_stbc = u32_get_bits(__le32_to_cpu(rx_usr_info->info0), + HAL_RX_USR_INFO0_STBC); + ppdu_info->ldpc = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO2_LDPC); + ppdu_info->dcm = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO2_STA_DCM); + ppdu_info->bw = u32_get_bits(__le32_to_cpu(rx_usr_info->info1), + HAL_RX_USR_INFO1_RX_BW); + ppdu_info->mcs = u32_get_bits(__le32_to_cpu(rx_usr_info->info1), + HAL_RX_USR_INFO1_MCS); + ppdu_info->nss = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO2_NSS) + 1; + + if (user_id < HAL_MAX_UL_MU_USERS) { + mon_rx_user_status = + &ppdu_info->userstats[user_id]; + mon_rx_user_status->mcs = ppdu_info->mcs; + mon_rx_user_status->nss = ppdu_info->nss; + } + + if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO || + ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || + ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)) + return HAL_TLV_STATUS_PPDU_NOT_DONE; + + /* RU allocation present only for OFDMA reception */ + ru_type_80_0 = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO2_RU_TYPE_80_0); + ru_start_index_80_0 = u32_get_bits(__le32_to_cpu(rx_usr_info->info3), + HAL_RX_USR_INFO3_RU_START_IDX_80_0); + if (ru_type_80_0 != HAL_EHT_RU_NONE) { + ru_size += ru_type_80_0; + ru_index = ru_index_per80mhz = ru_start_index_80_0; + HAL_SET_RU_PER80(ru_index_320mhz, ru_type_80_0, ru_index_per80mhz, 0); + num_80mhz_with_ru++; + } + + ru_type_80_1 = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO2_RU_TYPE_80_1); + ru_start_index_80_1 = u32_get_bits(__le32_to_cpu(rx_usr_info->info3), + HAL_RX_USR_INFO3_RU_START_IDX_80_1); + if (ru_type_80_1 != HAL_EHT_RU_NONE) { + ru_size += ru_type_80_1; + ru_index = ru_index_per80mhz = ru_start_index_80_1; + HAL_SET_RU_PER80(ru_index_320mhz, ru_type_80_1, ru_index_per80mhz, 1); + num_80mhz_with_ru++; + } + + ru_type_80_2 = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO2_RU_TYPE_80_2); + ru_start_index_80_2 = u32_get_bits(__le32_to_cpu(rx_usr_info->info3), + HAL_RX_USR_INFO3_RU_START_IDX_80_2); + if (ru_type_80_2 != HAL_EHT_RU_NONE) { + ru_size += ru_type_80_2; + ru_index = ru_index_per80mhz = ru_start_index_80_2; + HAL_SET_RU_PER80(ru_index_320mhz, ru_type_80_2, ru_index_per80mhz, 2); + num_80mhz_with_ru++; + } + + ru_type_80_3 = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO2_RU_TYPE_80_3); + ru_start_index_80_3 = u32_get_bits(__le32_to_cpu(rx_usr_info->info2), + HAL_RX_USR_INFO3_RU_START_IDX_80_3); + if (ru_type_80_3 != HAL_EHT_RU_NONE) { + ru_size += ru_type_80_3; + ru_index = ru_index_per80mhz = ru_start_index_80_3; + HAL_SET_RU_PER80(ru_index_320mhz, ru_type_80_3, ru_index_per80mhz, 3); + num_80mhz_with_ru++; + } + + if (num_80mhz_with_ru > 1) { + /* Calculate the MRU index */ + switch (ru_index_320mhz) { + case HAL_EHT_RU_996_484_0: + case HAL_EHT_RU_996x2_484_0: + case HAL_EHT_RU_996x3_484_0: + ru_index = 0; + break; + case HAL_EHT_RU_996_484_1: + case HAL_EHT_RU_996x2_484_1: + case HAL_EHT_RU_996x3_484_1: + ru_index = 1; + break; + case HAL_EHT_RU_996_484_2: + case HAL_EHT_RU_996x2_484_2: + case HAL_EHT_RU_996x3_484_2: + ru_index = 2; + break; + case HAL_EHT_RU_996_484_3: + case HAL_EHT_RU_996x2_484_3: + case HAL_EHT_RU_996x3_484_3: + ru_index = 3; + break; + case HAL_EHT_RU_996_484_4: + case HAL_EHT_RU_996x2_484_4: + case HAL_EHT_RU_996x3_484_4: + ru_index = 4; + break; + case HAL_EHT_RU_996_484_5: + case HAL_EHT_RU_996x2_484_5: + case HAL_EHT_RU_996x3_484_5: + ru_index = 5; + break; + case HAL_EHT_RU_996_484_6: + case HAL_EHT_RU_996x2_484_6: + case HAL_EHT_RU_996x3_484_6: + ru_index = 6; + break; + case HAL_EHT_RU_996_484_7: + case HAL_EHT_RU_996x2_484_7: + case HAL_EHT_RU_996x3_484_7: + ru_index = 7; + break; + case HAL_EHT_RU_996x2_484_8: + ru_index = 8; + break; + case HAL_EHT_RU_996x2_484_9: + ru_index = 9; + break; + case HAL_EHT_RU_996x2_484_10: + ru_index = 10; + break; + case HAL_EHT_RU_996x2_484_11: + ru_index = 11; + break; + default: + ru_index = HAL_EHT_RU_INVALID; + break; + } + + ru_size += 4; + } + + rtap_ru_size = hal_rx_mon_hal_ru_size_to_ath12k_ru_size(ru_size); + if (rtap_ru_size != ATH12K_EHT_RU_INVALID) { + ppdu_info->eht_known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_SIZE_OM; + ppdu_info->eht_data[1] |= + le32_encode_bits(rtap_ru_size, + IEEE80211_RADIOTAP_EHT_DATA1_RU_SIZE); + } + + if (ru_index != HAL_EHT_RU_INVALID) { + ppdu_info->eht_known |= IEEE80211_RADIOTAP_EHT_KNOWN_RU_MRU_INDEX_OM; + ppdu_info->eht_data[1] |= + le32_encode_bits(rtap_ru_size, + IEEE80211_RADIOTAP_EHT_DATA1_RU_INDEX); + } + + if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && + rtap_ru_size != ATH12K_EHT_RU_INVALID) { + mon_rx_user_status->ul_ofdma_ru_start_index = ru_index; + mon_rx_user_status->ul_ofdma_ru_size = rtap_ru_size; + hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width); + mon_rx_user_status->ul_ofdma_ru_width = ru_width; + mon_rx_user_status->ofdma_info_valid = 1; + } + + return HAL_TLV_STATUS_PPDU_NOT_DONE; } static enum hal_rx_mon_status ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab, - struct ath12k_mon_data *pmon, - u32 tlv_tag, u8 *tlv_data, u32 userid) + struct hal_rx_mon_ppdu_info *ppdu_info, + struct hal_tlv_parsed_hdr *tlv_parsed_hdr) { - struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; u32 info[7]; + u16 tlv_tag = tlv_parsed_hdr->tlv_tag; + u16 tlv_len = tlv_parsed_hdr->tlv_len; + u16 userid = tlv_parsed_hdr->tlv_userid; + u8 *tlv_data = tlv_parsed_hdr->tlv_data; + + if (ppdu_info->tlv_aggr.in_progress) { + if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) { + return ath12k_dp_mon_hal_aggr_tlv(ppdu_info, + tlv_len, tlv_data); + } else { + ath12k_dp_mon_hal_rx_status_process_aggr_tlv(ppdu_info); + } + } switch (tlv_tag) { case HAL_RX_PPDU_START: { @@ -596,11 +1461,16 @@ (struct hal_rx_ppdu_start *)tlv_data; info[0] = __le32_to_cpu(ppdu_start->info0); - ppdu_info->ppdu_id = u32_get_bits(info[0], HAL_RX_PPDU_START_INFO0_PPDU_ID); - ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num); - ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts); + + info[1] = __le32_to_cpu(ppdu_start->info1); + ppdu_info->chan_num = u32_get_bits(info[1], + HAL_RX_PPDU_START_INFO1_CHAN_NUM); + ppdu_info->freq = u32_get_bits(info[1], + HAL_RX_PPDU_START_INFO1_CHAN_FREQ); + ppdu_info->ppdu_ts = ((__le32_to_cpu(ppdu_start->ppdu_start_ts_31_0) | + (__le32_to_cpu(ppdu_start->ppdu_start_ts_63_32) << 31))); if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) { ppdu_info->last_ppdu_id = ppdu_info->ppdu_id; @@ -628,8 +1498,8 @@ u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID); ppdu_info->tid = ffs(u32_get_bits(info[6], - HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP) - - 1); + HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP)) + - 1; ppdu_info->tcp_msdu_count = u32_get_bits(info[4], HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT); @@ -651,6 +1521,12 @@ ppdu_info->num_mpdu_fcs_err = u32_get_bits(info[0], HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR); + ppdu_info->peer_id = + u32_get_bits(info[0], HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID); + + if ((ppdu_info->num_mpdu_fcs_ok | ppdu_info->num_mpdu_fcs_err) > 1) + ppdu_info->userstats[userid].ampdu_present = true; + switch (ppdu_info->preamble_type) { case HAL_RX_PREAMBLE_11N: ppdu_info->ht_flags = 1; @@ -661,6 +1537,9 @@ case HAL_RX_PREAMBLE_11AX: ppdu_info->he_flags = 1; break; + case HAL_RX_PREAMBLE_11BE: + ppdu_info->eht_flags = 1; + break; default: break; } @@ -728,10 +1607,9 @@ case HAL_PHYRX_RSSI_LEGACY: { struct hal_rx_phyrx_rssi_legacy_info *rssi = (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data; - u32 reception_type = 0; - u32 rssi_legacy_info = __le32_to_cpu(rssi->rsvd[0]); + u32 rssi_legacy_info = __le32_to_cpu(rssi->info0); - info[0] = __le32_to_cpu(rssi->info0); + info[0] = __le32_to_cpu(rssi->info1); /* TODO: Please note that the combined rssi will not be accurate * in MU case. Rssi in MU needs to be retrieved from @@ -739,22 +1617,9 @@ */ ppdu_info->rssi_comb = u32_get_bits(info[0], - HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB); - reception_type = - u32_get_bits(rssi_legacy_info, - HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION); - - switch (reception_type) { - case HAL_RECEPTION_TYPE_ULOFMDA: - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; - break; - case HAL_RECEPTION_TYPE_ULMIMO: - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; - break; - default: - ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; - break; - } + HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB); + ppdu_info->bw = u32_get_bits(rssi_legacy_info, + HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW); break; } case HAL_RXPCU_PPDU_END_INFO: { @@ -772,9 +1637,9 @@ case HAL_RX_MPDU_START: { struct hal_rx_mpdu_start *mpdu_start = (struct hal_rx_mpdu_start *)tlv_data; - struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; u16 peer_id; + info[0] = __le32_to_cpu(mpdu_start->info0); info[1] = __le32_to_cpu(mpdu_start->info1); peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID); if (peer_id) @@ -783,73 +1648,52 @@ ppdu_info->mpdu_len += u32_get_bits(info[1], HAL_RX_MPDU_START_INFO2_MPDU_LEN); if (userid < HAL_MAX_UL_MU_USERS) { - info[0] = __le32_to_cpu(mpdu_start->info0); + info[1] = __le32_to_cpu(mpdu_start->info1); ppdu_info->userid = userid; - ppdu_info->ampdu_id[userid] = - u32_get_bits(info[0], HAL_RX_MPDU_START_INFO1_PEERID); + ppdu_info->userstats[userid].ampdu_id = + u32_get_bits(info[0], HAL_RX_MPDU_START_INFO0_PPDU_ID); } - mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); - if (!mon_mpdu) - return HAL_RX_MON_STATUS_PPDU_NOT_DONE; - break; } - case HAL_RX_MSDU_START: - /* TODO: add msdu start parsing logic */ + case HAL_RX_PPDU_START_USER_INFO: { + ath12k_dp_mon_hal_rx_parse_receive_user_info(tlv_data, userid, ppdu_info); break; - case HAL_MON_BUF_ADDR: { - struct dp_rxdma_ring *buf_ring = &ab->dp.rxdma_mon_buf_ring; - struct dp_mon_packet_info *packet_info = - (struct dp_mon_packet_info *)tlv_data; - int buf_id = u32_get_bits(packet_info->cookie, - DP_RXDMA_BUF_COOKIE_BUF_ID); - struct sk_buff *msdu; - struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; - struct ath12k_skb_rxcb *rxcb; - - spin_lock_bh(&buf_ring->idr_lock); - msdu = idr_remove(&buf_ring->bufs_idr, buf_id); - spin_unlock_bh(&buf_ring->idr_lock); - - if (unlikely(!msdu)) { - ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", - buf_id); - return HAL_RX_MON_STATUS_PPDU_NOT_DONE; } - - rxcb = ATH12K_SKB_RXCB(msdu); - dma_unmap_single(ab->dev, rxcb->paddr, - msdu->len + skb_tailroom(msdu), - DMA_FROM_DEVICE); - - if (mon_mpdu->tail) - mon_mpdu->tail->next = msdu; - else - mon_mpdu->tail = msdu; - - ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); - + case HAL_PHYRX_OTHER_RECEIVE_INFO: { + struct phyrx_common_user_info *cmn_usr_info = + (struct phyrx_common_user_info *)tlv_data; + ppdu_info->gi = u32_get_bits(__le32_to_cpu(cmn_usr_info->info0), + HAL_RX_PHY_CMN_USER_INFO0_GI); break; } - case HAL_RX_MSDU_END: { - struct rx_msdu_end_qcn9274 *msdu_end = - (struct rx_msdu_end_qcn9274 *)tlv_data; - bool is_first_msdu_in_mpdu; - u16 msdu_end_info; - - msdu_end_info = __le16_to_cpu(msdu_end->info5); - is_first_msdu_in_mpdu = u32_get_bits(msdu_end_info, - RX_MSDU_END_INFO5_FIRST_MSDU); - if (is_first_msdu_in_mpdu) { - pmon->mon_mpdu->head = pmon->mon_mpdu->tail; - pmon->mon_mpdu->tail = NULL; - } + case HAL_MON_DROP: + /* TODO: Drop mpdu counts for the current ppdu can be recorded for + * statistics + */ break; - } + case HAL_MON_BUF_ADDR: + return HAL_RX_MON_STATUS_BUF_ADDR; case HAL_RX_MPDU_END: - list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list); + return HAL_RX_MON_STATUS_MPDU_END; + case HAL_PHYRX_GENERIC_U_SIG: + ath12k_dp_mon_hal_rx_parse_u_sig_hdr(tlv_data, ppdu_info); + break; + case HAL_PHYRX_GENERIC_EHT_SIG: { + /* + * Handle the case where aggregation is in progress + * or the current TLV is one of the TLVs which should be + * aggregated + */ + ppdu_info->tlv_aggr.in_progress = 1; + ppdu_info->tlv_aggr.tlv_tag = tlv_tag; + ppdu_info->tlv_aggr.cur_len = 0; + ppdu_info->eht_flags = 1; + + ath12k_dp_mon_hal_aggr_tlv(ppdu_info, tlv_len, tlv_data); + break; + } case HAL_DUMMY: return HAL_RX_MON_STATUS_BUF_DONE; case HAL_RX_PPDU_END_STATUS_DONE: @@ -862,25 +1706,152 @@ return HAL_RX_MON_STATUS_PPDU_NOT_DONE; } -static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar, struct sk_buff *msdu) +static void +ath12k_dp_mon_fill_rx_rate(struct ath12k *ar, struct hal_rx_mon_ppdu_info *ppdu_info, + struct ieee80211_rx_status *rx_status) +{ + struct ieee80211_supported_band *sband; + enum rx_msdu_start_pkt_type pkt_type; + u8 rate_mcs, nss, sgi; + bool is_cck; + + pkt_type = ppdu_info->preamble_type; + rate_mcs = ppdu_info->rate; + nss = ppdu_info->nss; + sgi = ppdu_info->gi; + + switch (pkt_type) { + case RX_MSDU_START_PKT_TYPE_11A: + case RX_MSDU_START_PKT_TYPE_11B: + is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); + if (rx_status->band < NUM_NL80211_BANDS) { + sband = &ar->mac.sbands[rx_status->band]; + rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, + is_cck); + } + break; + case RX_MSDU_START_PKT_TYPE_11N: + rx_status->encoding = RX_ENC_HT; + if (rate_mcs > ATH12K_HT_MCS_MAX) { + ath12k_warn(ar->ab, + "Received with invalid mcs in HT mode %d\n", + rate_mcs); + break; + } + rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); + if (sgi) + rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; + break; + case RX_MSDU_START_PKT_TYPE_11AC: + rx_status->encoding = RX_ENC_VHT; + rx_status->rate_idx = rate_mcs; + if (rate_mcs > ATH12K_VHT_MCS_MAX) { + ath12k_warn(ar->ab, + "Received with invalid mcs in VHT mode %d\n", + rate_mcs); + break; + } + if (sgi) + rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; + break; + case RX_MSDU_START_PKT_TYPE_11AX: + rx_status->rate_idx = rate_mcs; + if (rate_mcs > ATH12K_HE_MCS_MAX) { + ath12k_warn(ar->ab, + "Received with invalid mcs in HE mode %d\n", + rate_mcs); + break; + } + rx_status->encoding = RX_ENC_HE; + rx_status->he_gi = ath12k_mac_he_gi_to_nl80211_he_gi(sgi); + break; + case RX_MSDU_START_PKT_TYPE_11BE: + rx_status->rate_idx = rate_mcs; + if (rate_mcs > ATH12K_EHT_MCS_MAX) { + ath12k_warn(ar->ab, + "Received with invalid mcs in EHT mode %d\n", + rate_mcs); + break; + } + rx_status->encoding = RX_ENC_EHT; + rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); + break; + default: + ath12k_dbg(ar->ab, ATH12K_DBG_DATA, + "monitor receives invalid preamble type %d" + ,pkt_type); + break; + } +} + +static void +ath12k_dp_mon_fill_rx_stats(struct ath12k *ar, struct hal_rx_mon_ppdu_info *ppdu_info, + struct ieee80211_rx_status *rx_status) { - u32 rx_pkt_offset, l2_hdr_offset; + struct ieee80211_channel *channel; + u32 center_freq; + u8 channel_num; + + rx_status->freq = ppdu_info->freq; + rx_status->bw = ath12k_mac_bw_to_mac80211_bw(ppdu_info->bw); + rx_status->nss = ppdu_info->nss; + rx_status->rate_idx = 0; + rx_status->encoding = RX_ENC_LEGACY; + + rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; + + channel_num = ppdu_info->chan_num; + center_freq = ppdu_info->freq; + + rx_status->band = NUM_NL80211_BANDS; + + if (center_freq >= ATH12K_MIN_6G_FREQ && + center_freq <= ATH12K_MAX_6G_FREQ) { + rx_status->band = NL80211_BAND_6GHZ; + rx_status->freq = center_freq; + } else if (channel_num >= ATH12K_MIN_2G_CHAN && + channel_num <= ATH12K_MAX_2G_CHAN) { + rx_status->band = NL80211_BAND_2GHZ; + } else if (channel_num >= ATH12K_MIN_5G_CHAN && + channel_num <= ATH12K_MAX_5G_CHAN) { + rx_status->band = NL80211_BAND_5GHZ; + } + + if (unlikely(rx_status->band == NUM_NL80211_BANDS || + !ar->ah->hw->wiphy->bands[rx_status->band])) { + ath12k_dbg(ar->ab, ATH12K_DBG_DATA, + "sband is NULL for status band 1 %d channel_num %d center_freq %d pdev_id %d\n", + rx_status->band, channel_num, center_freq, ar->pdev_idx); + spin_lock_bh(&ar->data_lock); + channel = ar->rx_channel; + if (channel) { + rx_status->band = channel->band; + channel_num = + ieee80211_frequency_to_channel(channel->center_freq); + } else { + ath12k_err(ar->ab, "unable to determine channel, band for rx packet"); + } + spin_unlock_bh(&ar->data_lock); + } + + if (rx_status->band < NUM_NL80211_BANDS) + rx_status->freq = ieee80211_channel_to_frequency(channel_num, + rx_status->band); - rx_pkt_offset = ar->ab->hw_params->hal_desc_sz; - l2_hdr_offset = ath12k_dp_rx_h_l3pad(ar->ab, - (struct hal_rx_desc *)msdu->data); - skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); + ath12k_dp_mon_fill_rx_rate(ar, ppdu_info, rx_status); } +#define DP_MON_RX_PKT_OFFSET 8 +#define DP_MON_RX_L2_HDR_OFFSET 2 + static struct sk_buff * -ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar, - u32 mac_id, struct sk_buff *head_msdu, - struct ieee80211_rx_status *rxs, bool *fcs_err) +ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar, u32 mpdu_idx, + struct sk_buff *head_msdu, struct ieee80211_rx_status *rxs, + bool *fcs_err, struct hal_rx_mon_ppdu_info *ppdu_info) { struct ath12k_base *ab = ar->ab; struct sk_buff *msdu, *mpdu_buf, *prev_buf; - struct hal_rx_desc *rx_desc; - u8 *hdr_desc, *dest, decap_format; + u8 *dest, *msdu_payload, decap_format; struct ieee80211_hdr_3addr *wh; u32 err_bitmap; @@ -889,24 +1860,23 @@ if (!head_msdu) goto err_merge_fail; - rx_desc = (struct hal_rx_desc *)head_msdu->data; - err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); + err_bitmap = ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_idx].msdu_info[0].errmap; if (err_bitmap & HAL_RX_MPDU_ERR_FCS) *fcs_err = true; - decap_format = ath12k_dp_rx_h_decap_type(ab, rx_desc); + decap_format = ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_idx].msdu_info[0].decap_format; - ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); + ath12k_dp_mon_fill_rx_stats(ar, ppdu_info, rxs); if (decap_format == DP_RX_DECAP_TYPE_RAW) { - ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu); + skb_pull(head_msdu, DP_MON_RX_PKT_OFFSET); prev_buf = head_msdu; msdu = head_msdu->next; while (msdu) { - ath12k_dp_mon_rx_msdus_set_payload(ar, msdu); + skb_pull(msdu, DP_MON_RX_PKT_OFFSET); prev_buf = msdu; msdu = msdu->next; @@ -914,15 +1884,14 @@ prev_buf->next = NULL; - skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); + skb_trim(prev_buf, prev_buf->len); } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { u8 qos_pkt = 0; - rx_desc = (struct hal_rx_desc *)head_msdu->data; - hdr_desc = ab->hw_params->hal_ops->rx_desc_get_msdu_payload(rx_desc); + msdu_payload = head_msdu->data; /* Base size */ - wh = (struct ieee80211_hdr_3addr *)hdr_desc; + wh = (struct ieee80211_hdr_3addr *)msdu_payload; if (ieee80211_is_data_qos(wh->frame_control)) qos_pkt = 1; @@ -930,12 +1899,13 @@ msdu = head_msdu; while (msdu) { - ath12k_dp_mon_rx_msdus_set_payload(ar, msdu); + skb_pull(msdu, DP_MON_RX_L2_HDR_OFFSET); if (qos_pkt) { dest = skb_push(msdu, sizeof(__le16)); if (!dest) goto err_merge_fail; - memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr)); + memcpy(dest, msdu_payload, + sizeof(struct ieee80211_qos_hdr)); } prev_buf = msdu; msdu = msdu->next; @@ -1014,6 +1984,88 @@ rtap_buf[rtap_len] = rx_status->he_RU[3]; } +static enum nl80211_eht_ru_alloc +ath12k_dp_mon_rx_mon_ru_size_to_nl_ru_size(u32 ru_size) +{ + switch(ru_size) { + case ATH12K_EHT_RU_26: + return NL80211_RATE_INFO_EHT_RU_ALLOC_26; + case ATH12K_EHT_RU_52: + return NL80211_RATE_INFO_EHT_RU_ALLOC_52; + case ATH12K_EHT_RU_52_26: + return NL80211_RATE_INFO_EHT_RU_ALLOC_52P26; + case ATH12K_EHT_RU_106: + return NL80211_RATE_INFO_EHT_RU_ALLOC_106; + case ATH12K_EHT_RU_106_26: + return NL80211_RATE_INFO_EHT_RU_ALLOC_106P26; + case ATH12K_EHT_RU_242: + return NL80211_RATE_INFO_EHT_RU_ALLOC_242; + case ATH12K_EHT_RU_484: + return NL80211_RATE_INFO_EHT_RU_ALLOC_484; + case ATH12K_EHT_RU_484_242: + return NL80211_RATE_INFO_EHT_RU_ALLOC_484P242; + case ATH12K_EHT_RU_996: + return NL80211_RATE_INFO_EHT_RU_ALLOC_996; + case ATH12K_EHT_RU_996x2: + return NL80211_RATE_INFO_EHT_RU_ALLOC_2x996; + case ATH12K_EHT_RU_996x3: + return NL80211_RATE_INFO_EHT_RU_ALLOC_3x996; + case ATH12K_EHT_RU_996x4: + return NL80211_RATE_INFO_EHT_RU_ALLOC_4x996; + case ATH12K_EHT_RU_996_484: + return NL80211_RATE_INFO_EHT_RU_ALLOC_996P484; + case ATH12K_EHT_RU_996x2_484: + return NL80211_RATE_INFO_EHT_RU_ALLOC_2x996P484; + case ATH12K_EHT_RU_996x3_484: + return NL80211_RATE_INFO_EHT_RU_ALLOC_3x996P484; + case ATH12K_EHT_RU_996_484_242: + return NL80211_RATE_INFO_EHT_RU_ALLOC_996P484P242; + default: + return NL80211_RATE_INFO_EHT_RU_ALLOC_26; + } +} + +static void +ath12k_dp_mon_rx_update_radiotap_u_sig(struct hal_rx_mon_ppdu_info *rx_status, + u8 *rtap_buf) +{ + u32 rtap_len = 0; + + put_unaligned_le32(rx_status->usig_common, &rtap_buf[rtap_len]); + rtap_len += 4; + + put_unaligned_le32(rx_status->usig_value, &rtap_buf[rtap_len]); + rtap_len += 4; + + put_unaligned_le32(rx_status->usig_mask, &rtap_buf[rtap_len]); +} + +static void +ath12k_dp_mon_rx_update_radiotap_eht(struct hal_rx_mon_ppdu_info *rx_status, + u8 *rtap_buf) +{ + u32 rtap_len = 0, user, i; + + put_unaligned_le32(rx_status->eht_known, &rtap_buf[rtap_len]); + rtap_len += 4; + + for (i = 0; i < ARRAY_SIZE(rx_status->eht_data); i++) { + put_unaligned_le32(rx_status->eht_data[i], + &rtap_buf[rtap_len]); + rtap_len += 4; + } + + if (rx_status->num_eht_user_info_valid > EHT_MAX_USER_INFO) + return; + + for (user = 0; user < rx_status->num_eht_user_info_valid; user++) { + put_unaligned_le32(rx_status->eht_user_info[user], + &rtap_buf[rtap_len]); + rtap_len += 4; + } +} + + static void ath12k_dp_mon_update_radiotap(struct ath12k *ar, struct hal_rx_mon_ppdu_info *ppduinfo, struct sk_buff *mon_skb, @@ -1022,24 +2074,67 @@ struct ieee80211_supported_band *sband; u8 *ptr = NULL; u16 ampdu_id = ppduinfo->ampdu_id[ppduinfo->userid]; + u32 ru_size; + bool ampdu_present = ppduinfo->userstats[ppduinfo->userid].ampdu_present; rxs->flag |= RX_FLAG_MACTIME_START; - rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR; + rxs->signal = ppduinfo->rssi_comb + ar->rssi_offsets.rssi_offset; rxs->nss = ppduinfo->nss + 1; - if (ampdu_id) { + if (ampdu_present) { rxs->flag |= RX_FLAG_AMPDU_DETAILS; rxs->ampdu_reference = ampdu_id; } - if (ppduinfo->he_mu_flags) { + if (ppduinfo->usig_flags) { + struct ieee80211_radiotap_tlv *tlv; + struct ieee80211_radiotap_eht_usig *usig; + int usig_len = sizeof (*usig); + int len; + + if (!(rxs->flag & RX_FLAG_RADIOTAP_TLV_AT_END)) + skb_reset_mac_header(mon_skb); + rxs->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; + rxs->encoding = RX_ENC_EHT; + len = sizeof(*tlv) + ALIGN(usig_len, 4); + tlv = skb_push(mon_skb, len); + memset(tlv, 0, len); + tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); + tlv->len = cpu_to_le16(usig_len); + ptr = tlv->data; + ath12k_dp_mon_rx_update_radiotap_u_sig(ppduinfo, ptr); + } + + if (ppduinfo->eht_flags) { + struct ieee80211_radiotap_tlv *tlv; + struct ieee80211_radiotap_eht *eht; + int eht_len = struct_size(eht, user_info, + ppduinfo->num_eht_user_info_valid); + int len; + + rxs->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; + rxs->encoding = RX_ENC_EHT; + + len = sizeof(*tlv) + ALIGN(eht_len, 4); + skb_reset_mac_header(mon_skb); + tlv = skb_push(mon_skb, len); + memset(tlv, 0, len); + tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); + tlv->len = cpu_to_le16(eht_len); + ptr = tlv->data; + ath12k_dp_mon_rx_update_radiotap_eht(ppduinfo, ptr); + } else if (ppduinfo->he_mu_flags) { rxs->flag |= RX_FLAG_RADIOTAP_HE_MU; rxs->encoding = RX_ENC_HE; - ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)); + ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)) +; ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr); + rxs->ampdu_reference = ampdu_id; } else if (ppduinfo->he_flags) { rxs->flag |= RX_FLAG_RADIOTAP_HE; rxs->encoding = RX_ENC_HE; + ru_size = ppduinfo->userstats[ppduinfo->userid].ul_ofdma_ru_size; + rxs->eht.ru = ath12k_dp_mon_rx_mon_ru_size_to_nl_ru_size(ru_size); ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he)); ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr); rxs->rate_idx = ppduinfo->rate; @@ -1060,15 +2155,16 @@ } static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, - struct sk_buff *msdu, - struct ieee80211_rx_status *status) + struct sk_buff *msdu, u32 mpdu_idx, + struct hal_rx_mon_ppdu_info *ppduinfo, + struct ath12k_dp_rx_info *rx_info) { static const struct ieee80211_radiotap_he known = { .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), }; - struct ieee80211_rx_status *rx_status; + struct ieee80211_rx_status *rx_status, *status = rx_info->rx_status; struct ieee80211_radiotap_he *he = NULL; struct ieee80211_sta *pubsta = NULL; struct ath12k_peer *peer; @@ -1084,16 +2180,24 @@ status->flag |= RX_FLAG_RADIOTAP_HE; } + status->link_valid = 0; + status->link_id = 0; + if (!(status->flag & RX_FLAG_ONLY_MONITOR)) - decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc); + decap = ppduinfo->cmn_mpdu_info.mon_mpdu[mpdu_idx].msdu_info[0].decap_format; spin_lock_bh(&ar->ab->base_lock); - peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); - if (peer && peer->sta) + peer = ath12k_peer_find_by_id(ar->ab, ppduinfo->peer_id); + if (peer && peer->sta) { pubsta = peer->sta; + if (pubsta->valid_links) { + status->link_valid = 1; + status->link_id = peer->link_id; + } + } spin_unlock_bh(&ar->ab->base_lock); ath12k_dbg(ar->ab, ATH12K_DBG_DATA, - "rx skb %pK len %u peer %pM %u %s %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", + "rx skb %pK len %u peer %pM %u %s %s%s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", msdu, msdu->len, peer ? peer->addr : NULL, @@ -1106,6 +2210,7 @@ (status->bw == RATE_INFO_BW_40) ? "40" : "", (status->bw == RATE_INFO_BW_80) ? "80" : "", (status->bw == RATE_INFO_BW_160) ? "160" : "", + (status->bw == RATE_INFO_BW_320) ? "320" : "", status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", status->rate_idx, status->nss, @@ -1131,10 +2236,10 @@ !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) rx_status->flag |= RX_FLAG_8023; - ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); + ieee80211_rx_napi(ar->ah->hw, pubsta, msdu, napi); } -static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id, +static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mpdu_idx, struct sk_buff *head_msdu, struct hal_rx_mon_ppdu_info *ppduinfo, struct napi_struct *napi) @@ -1142,10 +2247,14 @@ struct ath12k_pdev_dp *dp = &ar->dp; struct sk_buff *mon_skb, *skb_next, *header; struct ieee80211_rx_status *rxs = &dp->rx_status; + struct ath12k_dp_rx_info rx_info; bool fcs_err = false; - mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id, head_msdu, - rxs, &fcs_err); + rx_info.filled = 0; + rx_info.rx_status = rxs; + + mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mpdu_idx, head_msdu, + rxs, &fcs_err, ppduinfo); if (!mon_skb) goto mon_deliver_fail; @@ -1170,7 +2279,8 @@ } rxs->flag |= RX_FLAG_ONLY_MONITOR; ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs); - ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs); + ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, mpdu_idx, + ppduinfo, &rx_info); mon_skb = skb_next; } while (mon_skb); rxs->flag = 0; @@ -1187,24 +2297,159 @@ return -EINVAL; } +static int ath12k_dp_pkt_set_pktlen(struct sk_buff *skb, u32 len) +{ + if (skb->len > len) { + skb_trim(skb, len); + } else { + if (skb_tailroom(skb) < len - skb->len) { + if ((pskb_expand_head(skb, 0, + len - skb->len - skb_tailroom(skb), + GFP_ATOMIC))) { + dev_kfree_skb_any(skb); + return -ENOMEM; + } + } + + skb_put(skb, (len - skb->len)); + } + + return 0; +} + +static void +ath12k_dp_mon_parse_rx_msdu_end(u8 *tlv_data, struct hal_rx_mon_ppdu_info *ppdu_info) +{ + struct rx_msdu_end_qcn9274 *msdu_end = + (struct rx_msdu_end_qcn9274 *)tlv_data; + u32 info = __le32_to_cpu(msdu_end->info13); + u32 errmap = 0, mpdu_idx, msdu_idx, decap_format; + + if (info & RX_MSDU_END_INFO13_FCS_ERR) + errmap |= HAL_RX_MPDU_ERR_FCS; + + if (info & RX_MSDU_END_INFO13_DECRYPT_ERR) + errmap |= HAL_RX_MPDU_ERR_DECRYPT; + + if (info & RX_MSDU_END_INFO13_TKIP_MIC_ERR) + errmap |= HAL_RX_MPDU_ERR_TKIP_MIC; + + if (info & RX_MSDU_END_INFO13_A_MSDU_ERROR) + errmap |= HAL_RX_MPDU_ERR_AMSDU_ERR; + + if (info & RX_MSDU_END_INFO13_OVERFLOW_ERR) + errmap |= HAL_RX_MPDU_ERR_OVERFLOW; + + if (info & RX_MSDU_END_INFO13_MSDU_LEN_ERR) + errmap |= HAL_RX_MPDU_ERR_MSDU_LEN; + + if (info & RX_MSDU_END_INFO13_MPDU_LEN_ERR) + errmap |= HAL_RX_MPDU_ERR_MPDU_LEN; + + decap_format = u32_get_bits(info, RX_MSDU_END_INFO11_DECAP_FORMAT); + + mpdu_idx = ppdu_info->cmn_mpdu_info.mpdu_count; + msdu_idx = ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_idx].msdu_count; + ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_idx].msdu_info[msdu_idx].errmap = errmap; + ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_idx].msdu_info[msdu_idx].decap_format = decap_format; +} + +static void +ath12k_dp_mon_parse_rx_dest_tlv(struct ath12k *ar, + struct hal_rx_mon_ppdu_info *ppdu_info, + enum hal_rx_mon_status hal_status, u8 *tlv_data) +{ + int offset; + + if (ppdu_info->cmn_mpdu_info.mpdu_count > HAL_RX_MAX_MPDU) { + ath12k_warn(ar->ab, "MPDU count reached max limit\n"); + return; + } + + switch (hal_status) { + case HAL_RX_MON_STATUS_BUF_ADDR: { + struct dp_mon_packet_info *packet_info = + (struct dp_mon_packet_info *)tlv_data; + int buf_id = u32_get_bits(packet_info->cookie, + DP_RXDMA_BUF_COOKIE_BUF_ID); + struct sk_buff *msdu; + struct ath12k_skb_rxcb *rxcb; + struct dp_rxdma_ring *buf_ring; + struct ath12k_dp *dp = &ar->ab->dp; + u16 msdu_count, mpdu_count; + + buf_ring = &dp->rxdma_mon_buf_ring; + spin_lock_bh(&buf_ring->idr_lock); + msdu = idr_remove(&buf_ring->bufs_idr, buf_id); + spin_unlock_bh(&buf_ring->idr_lock); + + if (unlikely(!msdu)) { + ath12k_warn(ar->ab, + "mon buf_addr: dest desc with inval buf_id %d\n", + buf_id); + return; + } + + rxcb = ATH12K_SKB_RXCB(msdu); + dma_unmap_single(ar->ab->dev, rxcb->paddr, + msdu->len + skb_tailroom(msdu), + DMA_FROM_DEVICE); + + offset = packet_info->dma_length + ATH12K_WIFIRX_DOT11_OFFSET; + + mpdu_count = ppdu_info->cmn_mpdu_info.mpdu_count; + msdu_count = ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_count].msdu_count; + if (ath12k_dp_pkt_set_pktlen(msdu, offset) || + msdu_count >= HAL_RX_MAX_MSDU) { + dev_kfree_skb_any(msdu); + return; + } + + if (!msdu_count) + ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_count].head_msdu = msdu; + else + ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_count].tail_msdu->next = msdu; + + ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_count].tail_msdu = msdu; + ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_count].msdu_count++; + + ath12k_dp_mon_buf_replenish(ar->ab, buf_ring, 1); + break; + } + case HAL_RX_MON_STATUS_MPDU_END: { + u16 mpdu_count = ppdu_info->cmn_mpdu_info.mpdu_count; + + if (ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_count].msdu_count) + ppdu_info->cmn_mpdu_info.mon_mpdu[mpdu_count].tail_msdu->next = NULL; + ppdu_info->cmn_mpdu_info.mpdu_count++; + break; + } + case HAL_RX_MON_STATUS_MSDU_END: + ath12k_dp_mon_parse_rx_msdu_end(tlv_data, ppdu_info); + default: + break; + } +} + static enum hal_rx_mon_status -ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon, +ath12k_dp_mon_parse_rx_dest(struct ath12k *ar, struct hal_rx_mon_ppdu_info *ppdu_info, struct sk_buff *skb) { - struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; - struct hal_tlv_hdr *tlv; - enum hal_rx_mon_status hal_status; + struct hal_tlv_64_hdr *tlv; + struct hal_tlv_parsed_hdr tlv_parsed_hdr = {0}; + struct ath12k_skb_rxcb *rxcb; + enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; u32 tlv_userid = 0; u16 tlv_tag, tlv_len; u8 *ptr = skb->data; - memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info)); + bool montior_started = test_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags); do { - tlv = (struct hal_tlv_hdr *)ptr; - tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); - tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN); - tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID); + tlv = (struct hal_tlv_64_hdr *)ptr; + tlv_tag = u64_get_bits(tlv->tl, HAL_TLV_64_HDR_TAG); + tlv_len = u64_get_bits(tlv->tl, HAL_TLV_64_HDR_LEN); + tlv_userid = u64_get_bits(tlv->tl, HAL_TLV_USR_ID); ptr += sizeof(*tlv); /* The actual length of PPDU_END is the combined length of many PHY @@ -1216,46 +2461,62 @@ if (tlv_tag == HAL_RX_PPDU_END) tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); - hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon, - tlv_tag, ptr, tlv_userid); + tlv_parsed_hdr.tlv_tag = tlv_tag; + tlv_parsed_hdr.tlv_len = tlv_len; + tlv_parsed_hdr.tlv_userid = tlv_userid; + tlv_parsed_hdr.tlv_data = ptr; + + hal_status = ath12k_dp_mon_rx_parse_status_tlv(ar->ab, ppdu_info, + &tlv_parsed_hdr); + + if (montior_started) + ath12k_dp_mon_parse_rx_dest_tlv(ar, ppdu_info, + hal_status, ptr); + ptr += tlv_len; - ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); + ptr = PTR_ALIGN(ptr, HAL_TLV_64_ALIGN); - if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE) + if ((ptr - skb->data) >= skb->len + 1) break; - } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE); + } while ((hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE) || + (hal_status == HAL_RX_MON_STATUS_BUF_ADDR) || + (hal_status == HAL_RX_MON_STATUS_MPDU_END) || + (hal_status == HAL_RX_MON_STATUS_MSDU_END)); + + rxcb = ATH12K_SKB_RXCB(skb); + if (rxcb->is_end_of_ppdu) + hal_status = HAL_RX_MON_STATUS_PPDU_DONE; return hal_status; } enum hal_rx_mon_status ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar, - struct ath12k_mon_data *pmon, + struct hal_rx_mon_ppdu_info *ppdu_info, int mac_id, struct sk_buff *skb, struct napi_struct *napi) { - struct ath12k_base *ab = ar->ab; - struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; - struct dp_mon_mpdu *tmp; - struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; - struct sk_buff *head_msdu, *tail_msdu; + struct mon_mpdu_data *mon_mpdu; + struct sk_buff *head_msdu; enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; + int i; - ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); + hal_status = ath12k_dp_mon_parse_rx_dest(ar, ppdu_info, skb); + if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE) + return hal_status; - list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) { - list_del(&mon_mpdu->list); - head_msdu = mon_mpdu->head; - tail_msdu = mon_mpdu->tail; + for (i = 0; i < ppdu_info->cmn_mpdu_info.mpdu_count; i++) { + mon_mpdu = &ppdu_info->cmn_mpdu_info.mon_mpdu[i]; + if (!mon_mpdu) + continue; - if (head_msdu && tail_msdu) { - ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, - ppdu_info, napi); - } + head_msdu = mon_mpdu->head_msdu; - kfree(mon_mpdu); + if (head_msdu) + ath12k_dp_mon_rx_deliver(ar, i, head_msdu, + ppdu_info, napi); } return hal_status; } @@ -1312,6 +2573,7 @@ mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr)); mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr)); mon_buf->cookie = cpu_to_le64(cookie); + mon_buf->magic = DP_MON_MAGIC_VALUE; req_entries--; } @@ -1604,6 +2866,9 @@ tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag); + if (tlv_tag == HAL_MON_BUF_ADDR && !ab->hw_params->supports_tx_monitor) + return status; + switch (tlv_tag) { case HAL_TX_FES_SETUP: { struct hal_tx_fes_setup *tx_fes_setup = @@ -2056,163 +3321,122 @@ return tlv_status; } -int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget, - enum dp_monitor_mode monitor_mode, - struct napi_struct *napi) +static void +ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats, + struct hal_rx_mon_ppdu_info *ppdu_info, + struct hal_rx_user_status *user_stats, + u32 num_msdu) { - struct hal_mon_dest_desc *mon_dst_desc; - struct ath12k_pdev_dp *pdev_dp = &ar->dp; - struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; - struct ath12k_base *ab = ar->ab; - struct ath12k_dp *dp = &ab->dp; - struct sk_buff *skb; - struct ath12k_skb_rxcb *rxcb; - struct dp_srng *mon_dst_ring; - struct hal_srng *srng; - struct dp_rxdma_ring *buf_ring; - u64 cookie; - u32 ppdu_id; - int num_buffs_reaped = 0, srng_id, buf_id; - u8 dest_idx = 0, i; - bool end_of_ppdu; - struct hal_rx_mon_ppdu_info *ppdu_info; - struct ath12k_peer *peer = NULL; + u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs; + u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1; + u32 bw_idx = ppdu_info->bw; + u32 gi_idx = ppdu_info->gi; - ppdu_info = &pmon->mon_ppdu_info; - memset(ppdu_info, 0, sizeof(*ppdu_info)); - ppdu_info->peer_id = HAL_INVALID_PEERID; + if (mcs_idx > HAL_RX_MAX_MCS_BE || nss_idx >= HAL_RX_MAX_NSS || + bw_idx >= HAL_RX_BW_MAX || gi_idx >= HAL_RX_GI_MAX) { + return; + } - srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); + if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX || + ppdu_info->preamble_type == HAL_RX_PREAMBLE_11BE) + gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi); - if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) { - mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; - buf_ring = &dp->rxdma_mon_buf_ring; - } else { - mon_dst_ring = &pdev_dp->tx_mon_dst_ring[srng_id]; - buf_ring = &dp->tx_mon_buf_ring; + rx_stats->pkt_stats.rx_rate[bw_idx][gi_idx][nss_idx][mcs_idx] += num_msdu; + if (user_stats) + rx_stats->byte_stats.rx_rate[bw_idx][gi_idx][nss_idx][mcs_idx] += user_stats->mpdu_ok_byte_count; + else + rx_stats->byte_stats.rx_rate[bw_idx][gi_idx][nss_idx][mcs_idx] += ppdu_info->mpdu_len; } - srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; - - spin_lock_bh(&srng->lock); - ath12k_hal_srng_access_begin(ab, srng); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT +static void ath12k_dp_mon_rx_update_peer_stats_bonded(struct ath12k *ar, + struct ath12k_link_sta *arsta, + struct hal_rx_mon_ppdu_info *ppdu_info, + struct ieee80211_rx_status *rx_status) +{ + struct ieee80211_rx_status status; + struct ieee80211_sta *sta; + u32 uid; - while (likely(*budget)) { - *budget -= 1; - mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); - if (unlikely(!mon_dst_desc)) - break; + if (ar->ab->stats_disable || !g_bonded_interface_model || + !test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ar->ab->dev_flags)) + return; - cookie = le32_to_cpu(mon_dst_desc->cookie); - buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); + memset(&status, 0 , sizeof(status)); - spin_lock_bh(&buf_ring->idr_lock); - skb = idr_remove(&buf_ring->bufs_idr, buf_id); - spin_unlock_bh(&buf_ring->idr_lock); + lockdep_assert_held(&ar->ab->base_lock); + if (arsta) { // SU stats + if (arsta->arvif && (arsta->arvif->ppe_vp_num == -1 || + (arsta->arvif->ahvif && + hweight16(arsta->arvif->ahvif->links_map) <= 1))) + return; - if (unlikely(!skb)) { - ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", - buf_id); - goto move_next; + if (!rx_status) { + ath12k_dp_mon_fill_rx_stats(ar, ppdu_info, &status); + rx_status = &status; } - rxcb = ATH12K_SKB_RXCB(skb); - dma_unmap_single(ab->dev, rxcb->paddr, - skb->len + skb_tailroom(skb), - DMA_FROM_DEVICE); - - pmon->dest_skb_q[dest_idx] = skb; - dest_idx++; - ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id); - end_of_ppdu = le32_get_bits(mon_dst_desc->info0, - HAL_MON_DEST_INFO0_END_OF_PPDU); - if (!end_of_ppdu) - continue; + sta = container_of((void *)arsta->ahsta, struct ieee80211_sta, drv_priv); + ieee80211_rx_update_stats(ar->ah->hw, sta, arsta->link_id, + ppdu_info->mpdu_len, rx_status); + return; + } - for (i = 0; i < dest_idx; i++) { - skb = pmon->dest_skb_q[i]; + for (uid = 0; uid < ppdu_info->num_users; uid++) { // MU stats + struct ath12k_peer *peer; - if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) - ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id, - skb, napi); - else - ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id, - skb, napi, ppdu_id); + if (uid == HAL_MAX_UL_MU_USERS) + break; - peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); + if (ppdu_info->peer_id == HAL_INVALID_PEERID) + return; + peer = ath12k_peer_find_by_id(ar->ab, ppdu_info->peer_id); - if (!peer || !peer->sta) { - ath12k_dbg(ab, ATH12K_DBG_DATA, - "failed to find the peer with peer_id %d\n", + if (!peer) { + ath12k_warn(ar->ab, "peer with peer id %d can't be found\n", ppdu_info->peer_id); - dev_kfree_skb_any(skb); continue; } - dev_kfree_skb_any(skb); - pmon->dest_skb_q[i] = NULL; - } - - dest_idx = 0; -move_next: - ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); - ath12k_hal_srng_src_get_next_entry(ab, srng); - num_buffs_reaped++; - } - - ath12k_hal_srng_access_end(ab, srng); - spin_unlock_bh(&srng->lock); - - return num_buffs_reaped; + arsta = ath12k_peer_get_link_sta(ar->ab, peer); + if (!arsta) { + ath12k_warn(ar->ab, "link sta not found on peer %pM id %d\n", + peer->addr, peer->peer_id); + continue; } -static void -ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats, - struct hal_rx_mon_ppdu_info *ppdu_info, - struct hal_rx_user_status *user_stats, - u32 num_msdu) -{ - u32 rate_idx = 0; - u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs; - u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1; - u32 bw_idx = ppdu_info->bw; - u32 gi_idx = ppdu_info->gi; + if (arsta->arvif && (arsta->arvif->ppe_vp_num == -1 || + (arsta->arvif->ahvif && + hweight16(arsta->arvif->ahvif->links_map) <= 1))) + continue; - if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) || - (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) { - return; + if (!rx_status) { + ath12k_dp_mon_fill_rx_stats(ar, ppdu_info, &status); + rx_status = &status; } - if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N || - ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) { - rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx; - rate_idx += bw_idx * 2 + gi_idx; - } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) { - gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi); - rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx; - rate_idx += bw_idx * 3 + gi_idx; - } else { - return; + sta = container_of((void *)arsta->ahsta, struct ieee80211_sta, drv_priv); + ieee80211_rx_update_stats(ar->ah->hw, sta, arsta->link_id, + ppdu_info->mpdu_len, rx_status); } - - rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu; - if (user_stats) - rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count; - else - rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len; } +#endif /* CONFIG_ATH12K_BONDED_DS_SUPPORT */ static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar, - struct ath12k_sta *arsta, + struct ath12k_link_sta *arsta, struct hal_rx_mon_ppdu_info *ppdu_info) { struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats; u32 num_msdu; + u32 bw_offset; - if (!rx_stats) - return; - + arsta->last_tx_pkt_bw = ppdu_info->bw; + bw_offset = arsta->last_tx_pkt_bw * 3; arsta->rssi_comb = ppdu_info->rssi_comb; + ewma_avg_rssi_add(&arsta->avg_rssi, ppdu_info->rssi_comb + bw_offset); + + if (!ath12k_debugfs_is_extd_rx_stats_enabled(ar) || !rx_stats) + return; num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; @@ -2285,6 +3509,12 @@ rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; } + if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11BE && + ppdu_info->mcs <= HAL_RX_MAX_MCS_BE) { + rx_stats->pkt_stats.be_mcs_count[ppdu_info->mcs] += num_msdu; + rx_stats->byte_stats.be_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; + } + if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) && ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) { @@ -2359,26 +3589,31 @@ struct hal_rx_mon_ppdu_info *ppdu_info, u32 uid) { - struct ath12k_sta *arsta = NULL; + struct ath12k_link_sta *arsta; struct ath12k_rx_peer_stats *rx_stats = NULL; struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid]; struct ath12k_peer *peer; u32 num_msdu; - if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF) + if (ppdu_info->peer_id == HAL_INVALID_PEERID) return; - peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index); + peer = ath12k_peer_find_by_id(ar->ab, ppdu_info->peer_id); if (!peer) { - ath12k_warn(ar->ab, "peer ast idx %d can't be found\n", - user_stats->ast_index); + ath12k_warn(ar->ab, "peer with peer id %d can't be found\n", + ppdu_info->peer_id); return; } - arsta = (struct ath12k_sta *)peer->sta->drv_priv; - rx_stats = arsta->rx_stats; + arsta = ath12k_peer_get_link_sta(ar->ab, peer); + if (!arsta) { + ath12k_warn(ar->ab, "link sta not found on peer %pM id %d\n", + peer->addr, peer->peer_id); + return; + } + rx_stats = arsta->rx_stats; if (!rx_stats) return; @@ -2461,6 +3696,9 @@ { u32 num_users, i; + if (!ath12k_debugfs_is_extd_rx_stats_enabled(ar)) + return; + num_users = ppdu_info->num_users; if (num_users > HAL_MAX_UL_MU_USERS) num_users = HAL_MAX_UL_MU_USERS; @@ -2469,12 +3707,213 @@ ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i); } +static inline void +ath12k_dp_mon_rx_memset_ppdu_info(struct hal_rx_mon_ppdu_info *ppdu_info) +{ + int i, len; + + len = (sizeof(struct hal_rx_mon_ppdu_info) - + sizeof(struct hal_rx_mon_cmn_mpdu_info)); + + memset(ppdu_info, 0, len); + for (i = 0; i < ppdu_info->cmn_mpdu_info.mpdu_count; i++) { + ppdu_info->cmn_mpdu_info.mon_mpdu[i].msdu_count = 0; + ppdu_info->cmn_mpdu_info.mon_mpdu[i].head_msdu = NULL; + ppdu_info->cmn_mpdu_info.mon_mpdu[i].tail_msdu = NULL; + } + ppdu_info->cmn_mpdu_info.mpdu_count = 0; +} + +int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget, + enum dp_monitor_mode dp_mon_mode, struct napi_struct *napi) +{ + struct hal_mon_dest_desc *mon_dst_desc; + struct ath12k_pdev_dp *pdev_dp = &ar->dp; + struct ath12k_mon_data *pmon = pdev_dp->mon_data; + struct ath12k_base *ab = ar->ab; + struct ath12k_dp *dp = &ab->dp; + struct sk_buff *skb; + struct ath12k_skb_rxcb *rxcb; + struct dp_srng *mon_dst_ring; + struct hal_srng *srng; + struct dp_rxdma_ring *buf_ring; + struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; + struct sk_buff_head skb_list; + struct ath12k_peer *peer = NULL; + struct ath12k_link_sta *arsta; + u64 cookie; + u32 hal_status, end_reason, ppdu_id, end_offset; + int num_buffs_reaped = 0, srng_id, buf_id; + char buf[64] = {0}; + + __skb_queue_head_init(&skb_list); + + srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); + + if (dp_mon_mode == ATH12K_DP_RX_MONITOR_MODE) { + mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; + buf_ring = &dp->rxdma_mon_buf_ring; + } else { + if (!ab->hw_params->supports_tx_monitor) + return 0; + + mon_dst_ring = &pdev_dp->tx_mon_dst_ring[srng_id]; + buf_ring = &dp->tx_mon_buf_ring; + } + + srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; + spin_lock_bh(&srng->lock); + ath12k_hal_srng_access_begin(ab, srng); + + while (likely(*budget)) { + mon_dst_desc = (struct hal_mon_dest_desc *) + ath12k_hal_srng_dst_peek(ab, srng); + if (unlikely(!mon_dst_desc)) + break; + + if (u32_get_bits(mon_dst_desc->info0, HAL_MON_DEST_INFO0_EMPTY_DESC)) { + ab->soc_stats.mon_drop_desc++; + goto move_next; + } + + if (unlikely(mon_dst_desc->magic != DP_MON_MAGIC_VALUE)) { + scnprintf(buf, sizeof(buf), "invalid mon dest desc in mon srng process\n"); + ath12k_err_dump(ab, buf, "mon dest desc: ", mon_dst_desc, + sizeof(*mon_dst_desc), srng); + BUG_ON(1); + } + + cookie = mon_dst_desc->cookie; + ppdu_id = mon_dst_desc->ppdu_id; + buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); + + spin_lock_bh(&buf_ring->idr_lock); + skb = idr_remove(&buf_ring->bufs_idr, buf_id); + spin_unlock_bh(&buf_ring->idr_lock); + + if (unlikely(!skb)) { + ath12k_warn(ab, "mon: dest desc with inval buf_id %d\n", + buf_id); + goto move_next; + } + + rxcb = ATH12K_SKB_RXCB(skb); + dma_unmap_single(ab->dev, rxcb->paddr, + skb->len + skb_tailroom(skb), + DMA_FROM_DEVICE); + end_reason = u32_get_bits(mon_dst_desc->info0, + HAL_MON_DEST_INFO0_END_REASON); + if ((end_reason == HAL_MON_FLUSH_DETECTED) || + (end_reason == HAL_MON_PPDU_TRUNCATED)) { + ath12k_dbg(ab, ATH12K_DBG_DATA, + "Monitor dest descriptor end reason %d", end_reason); + dev_kfree_skb_any(skb); + goto move_next; + } + + if (end_reason == HAL_MON_END_OF_PPDU) { + *budget -= 1; + rxcb->is_end_of_ppdu = true; + } + + end_offset = u32_get_bits(mon_dst_desc->info0, + HAL_MON_DEST_INFO0_END_OFFSET); + + if (likely(end_offset < DP_RX_BUFFER_SIZE)) { + skb_put(skb, end_offset); + } else { + ath12k_warn(ab, "invalid offset received from mon dest %u\n", + end_offset); + skb_put(skb, DP_RX_BUFFER_SIZE); + } + + __skb_queue_tail(&skb_list, skb); +move_next: + ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); + ath12k_hal_srng_dst_get_next_entry(ab, srng); + num_buffs_reaped++; + } + + ath12k_hal_srng_access_end(ab, srng); + spin_unlock_bh(&srng->lock); + + if (!num_buffs_reaped) + return 0; + + if (!ppdu_info->ppdu_continuation) + ath12k_dp_mon_rx_memset_ppdu_info(ppdu_info); + + while ((skb = __skb_dequeue(&skb_list))) { + if (dp_mon_mode == ATH12K_DP_RX_MONITOR_MODE) + hal_status = + ath12k_dp_mon_rx_parse_mon_status(ar, ppdu_info, mac_id, + skb, napi); + else + hal_status = + ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id, + skb, napi, ppdu_id); + + if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { + ppdu_info->ppdu_continuation = true; + dev_kfree_skb_any(skb); + continue; + } + + if (ppdu_info->peer_id == HAL_INVALID_PEERID) + goto free_skb; + + rcu_read_lock(); + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); + if (!peer || !peer->sta) { + ath12k_dbg(ab, ATH12K_DBG_DATA, + "failed to find the peer with link id %d peer_id %d\n", + peer ? peer->link_id : -1, ppdu_info->peer_id); + goto next_skb; + } + + if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) { + arsta = ath12k_peer_get_link_sta(ar->ab, peer); + if (!arsta) { + ath12k_warn(ar->ab, "link sta not found on peer %pM id %d\n", + peer->addr, peer->peer_id); + goto next_skb; + } + + ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta, + ppdu_info); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ath12k_dp_mon_rx_update_peer_stats_bonded(ar, arsta, ppdu_info, + &ar->dp.rx_status); +#endif /* CONFIG_ATH12K_BONDED_DS_SUPPORT */ + } else if ((ppdu_info->fc_valid) && + (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) { + ath12k_dp_mon_rx_process_ulofdma(ppdu_info); + ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ath12k_dp_mon_rx_update_peer_stats_bonded(ar, NULL, ppdu_info, + &ar->dp.rx_status); +#endif /* CONFIG_ATH12K_BONDED_DS_SUPPORT */ + } + +next_skb: + spin_unlock_bh(&ab->base_lock); + rcu_read_unlock(); +free_skb: + dev_kfree_skb_any(skb); + ath12k_dp_mon_rx_memset_ppdu_info(ppdu_info); + ppdu_info->peer_id = HAL_INVALID_PEERID; + } + + return num_buffs_reaped; +} + int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id, struct napi_struct *napi, int *budget) { struct ath12k_base *ab = ar->ab; struct ath12k_pdev_dp *pdev_dp = &ar->dp; - struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; + struct ath12k_mon_data *pmon = pdev_dp->mon_data; struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; struct ath12k_dp *dp = &ab->dp; struct hal_mon_dest_desc *mon_dst_desc; @@ -2483,13 +3922,17 @@ struct dp_srng *mon_dst_ring; struct hal_srng *srng; struct dp_rxdma_ring *buf_ring; - struct ath12k_sta *arsta = NULL; + struct ath12k_link_sta *arsta = NULL; struct ath12k_peer *peer; + struct sk_buff_head skb_list; + struct ath12k_neighbor_peer *nrp, *tmp; u64 cookie; int num_buffs_reaped = 0, srng_id, buf_id; - u8 dest_idx = 0, i; - bool end_of_ppdu; - u32 hal_status; + u32 hal_status, end_reason, end_offset, rx_buf_sz; + char buf[64] = {0}; + u16 log_type = 0; + + __skb_queue_head_init(&skb_list); srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; @@ -2500,10 +3943,22 @@ ath12k_hal_srng_access_begin(ab, srng); while (likely(*budget)) { - *budget -= 1; mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); if (unlikely(!mon_dst_desc)) break; + + if (u32_get_bits(mon_dst_desc->info0, HAL_MON_DEST_INFO0_EMPTY_DESC)) { + ab->soc_stats.mon_drop_desc++; + goto move_next; + } + + if (unlikely(mon_dst_desc->magic != DP_MON_MAGIC_VALUE)) { + scnprintf(buf, sizeof(buf), "invalid mon dest desc in mon stats process\n"); + ath12k_err_dump(ab, buf, "mon dest desc: ", mon_dst_desc, + sizeof(*mon_dst_desc), srng); + BUG_ON(1); + } + cookie = le32_to_cpu(mon_dst_desc->cookie); buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); @@ -2512,7 +3967,7 @@ spin_unlock_bh(&buf_ring->idr_lock); if (unlikely(!skb)) { - ath12k_warn(ab, "monitor destination with invalid buf_id %d\n", + ath12k_warn(ab, "mon stats: dest ring with inval buf_id %d\n", buf_id); goto move_next; } @@ -2521,62 +3976,132 @@ dma_unmap_single(ab->dev, rxcb->paddr, skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); - pmon->dest_skb_q[dest_idx] = skb; - dest_idx++; - end_of_ppdu = le32_get_bits(mon_dst_desc->info0, - HAL_MON_DEST_INFO0_END_OF_PPDU); - if (!end_of_ppdu) - continue; + end_reason = u32_get_bits(mon_dst_desc->info0, + HAL_MON_DEST_INFO0_END_REASON); + if ((end_reason == HAL_MON_FLUSH_DETECTED) || + (end_reason == HAL_MON_PPDU_TRUNCATED)) { + ath12k_dbg(ab, ATH12K_DBG_DATA, + "Monitor dest descriptor end reason %d", end_reason); + dev_kfree_skb_any(skb); + goto move_next; + } - for (i = 0; i < dest_idx; i++) { - skb = pmon->dest_skb_q[i]; - hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); + if (end_reason == HAL_MON_END_OF_PPDU) + *budget -= 1; - if (ppdu_info->peer_id == HAL_INVALID_PEERID || - hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { + end_offset = u32_get_bits(mon_dst_desc->info0, + HAL_MON_DEST_INFO0_END_OFFSET); + + if (likely(end_offset < DP_RX_BUFFER_SIZE)) { + skb_put(skb, end_offset); + } else { + ath12k_warn(ab, "invalid offset received on mon stats dest %u\n", + end_offset); + skb_put(skb, DP_RX_BUFFER_SIZE); + } + + __skb_queue_tail(&skb_list, skb); +move_next: + ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); + ath12k_hal_srng_dst_get_next_entry(ab, srng); + num_buffs_reaped++; + } + + ath12k_hal_srng_access_end(ab, srng); + spin_unlock_bh(&srng->lock); + if (!num_buffs_reaped) + return 0; + + if (!ppdu_info->ppdu_continuation) + ath12k_dp_mon_rx_memset_ppdu_info(ppdu_info); + + while ((skb = __skb_dequeue(&skb_list))) { + if (ath12k_debugfs_is_pktlog_lite_mode_enabled(ar)) { + log_type = ATH12K_PKTLOG_TYPE_LITE_RX; + rx_buf_sz = DP_RX_BUFFER_SIZE_LITE; + } else if (ath12k_debugfs_is_pktlog_rx_stats_enabled(ar)) { + log_type = ATH12K_PKTLOG_TYPE_RX_STATBUF; + rx_buf_sz = DP_RX_BUFFER_SIZE; + ath12k_rx_stats_buf_pktlog_process(ar, skb->data, log_type, + rx_buf_sz); + } + if (log_type) + trace_ath12k_htt_rxdesc(ar, skb->data, log_type, + rx_buf_sz); + + hal_status = ath12k_dp_mon_parse_rx_dest(ar, ppdu_info, skb); + if (hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { + ppdu_info->ppdu_continuation = true; dev_kfree_skb_any(skb); continue; } + if (ppdu_info->peer_id == HAL_INVALID_PEERID) + goto free_skb; + rcu_read_lock(); spin_lock_bh(&ab->base_lock); peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); + if (!list_empty(&ab->neighbor_peers)) { + if (peer && !peer->sta) { + list_for_each_entry_safe(nrp, tmp, &ab->neighbor_peers, list) { + if (nrp->is_filter_on && ether_addr_equal(nrp->addr, peer->addr)) { + nrp->rssi = ppdu_info->rssi_comb + + ar->rssi_offsets.rssi_offset; + nrp->timestamp = ktime_to_ms(ktime_get_real()); + complete(&nrp->filter_done); + } + } + goto next_skb; + } + } + if (!peer || !peer->sta) { ath12k_dbg(ab, ATH12K_DBG_DATA, - "failed to find the peer with peer_id %d\n", - ppdu_info->peer_id); - spin_unlock_bh(&ab->base_lock); - rcu_read_unlock(); - dev_kfree_skb_any(skb); - continue; + "failed to find the peer with monitor link id %d peer_id %d\n", + peer ? peer->link_id : -1, ppdu_info->peer_id); + goto next_skb; } if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) { - arsta = (struct ath12k_sta *)peer->sta->drv_priv; + arsta = ath12k_peer_get_link_sta(ar->ab, peer); + if (!arsta) { + ath12k_warn(ab, "link sta not found on peer %pM id %d\n", + peer->addr, peer->peer_id); + goto next_skb; + } + ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta, ppdu_info); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ath12k_dp_mon_rx_update_peer_stats_bonded(ar, arsta, ppdu_info, + NULL); +#endif /* CONFIG_ATH12K_BONDED_DS_SUPPORT */ } else if ((ppdu_info->fc_valid) && (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) { ath12k_dp_mon_rx_process_ulofdma(ppdu_info); ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ath12k_dp_mon_rx_update_peer_stats_bonded(ar, NULL, ppdu_info, + NULL); +#endif /* CONFIG_ATH12K_BONDED_DS_SUPPORT */ + } + + if (ath12k_debugfs_is_pktlog_peer_valid(ar, peer->addr)) { + trace_ath12k_htt_rxdesc(ar, skb->data, log_type, rx_buf_sz); + ath12k_rx_stats_buf_pktlog_process(ar, skb->data, log_type, + rx_buf_sz); } +next_skb: spin_unlock_bh(&ab->base_lock); rcu_read_unlock(); +free_skb: dev_kfree_skb_any(skb); - memset(ppdu_info, 0, sizeof(*ppdu_info)); + ath12k_dp_mon_rx_memset_ppdu_info(ppdu_info); ppdu_info->peer_id = HAL_INVALID_PEERID; } - dest_idx = 0; -move_next: - ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); - ath12k_hal_srng_src_get_next_entry(ab, srng); - num_buffs_reaped++; - } - - ath12k_hal_srng_access_end(ab, srng); - spin_unlock_bh(&srng->lock); return num_buffs_reaped; } @@ -2587,8 +4112,9 @@ struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id); int num_buffs_reaped = 0; - if (!ar->monitor_started) - ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget); + if (!test_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags)) + num_buffs_reaped = ath12k_dp_mon_rx_process_stats(ar, mac_id, + napi, &budget); else num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget, monitor_mode, napi); diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp_mon.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_mon.h --- linux-6.4/drivers/net/wireless/ath/ath12k/dp_mon.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_mon.h 2024-01-19 17:01:19.861846921 +0100 @@ -8,12 +8,17 @@ #define ATH12K_DP_MON_H #include "core.h" +#include "debugfs_htt_stats.h" enum dp_monitor_mode { ATH12K_DP_TX_MONITOR_MODE, ATH12K_DP_RX_MONITOR_MODE }; +#define ATH12K_WIFIRX_DOT11_OFFSET 5 + +#define DP_MON_MAGIC_VALUE 0xDECAFEED + enum dp_mon_tx_ppdu_info_type { DP_MON_TX_PROT_PPDU_INFO, DP_MON_TX_DATA_PPDU_INFO @@ -76,7 +81,7 @@ enum hal_rx_mon_status ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar, - struct ath12k_mon_data *pmon, + struct hal_rx_mon_ppdu_info *ppdu_info, int mac_id, struct sk_buff *skb, struct napi_struct *napi); int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab, diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp_rx.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_rx.c --- linux-6.4/drivers/net/wireless/ath/ath12k/dp_rx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_rx.c 2024-03-18 14:40:14.851741333 +0100 @@ -1,15 +1,18 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include #include #include +#include #include "core.h" #include "debug.h" +#include "debugfs_htt_stats.h" +#include "debugfs_sta.h" #include "hal_desc.h" #include "hw.h" #include "dp_rx.h" @@ -17,9 +20,19 @@ #include "dp_tx.h" #include "peer.h" #include "dp_mon.h" +#include "hif.h" +#include "sawf.h" +#ifdef CONFIG_MAC80211_PPE_SUPPORT +#include +#include +#endif + #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) +static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, + enum hal_reo_cmd_status status); + static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, struct hal_rx_desc *desc) { @@ -83,18 +96,6 @@ return ab->hw_params->hal_ops->dp_rx_h_msdu_done(desc); } -static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return ab->hw_params->hal_ops->dp_rx_h_l4_cksum_fail(desc); -} - -static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return ab->hw_params->hal_ops->dp_rx_h_ip_cksum_fail(desc); -} - static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, struct hal_rx_desc *desc) { @@ -113,42 +114,6 @@ return ab->hw_params->hal_ops->rx_desc_get_msdu_len(desc); } -static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return ab->hw_params->hal_ops->rx_desc_get_msdu_sgi(desc); -} - -static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return ab->hw_params->hal_ops->rx_desc_get_msdu_rate_mcs(desc); -} - -static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return ab->hw_params->hal_ops->rx_desc_get_msdu_rx_bw(desc); -} - -static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return ab->hw_params->hal_ops->rx_desc_get_msdu_freq(desc); -} - -static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return ab->hw_params->hal_ops->rx_desc_get_msdu_pkt_type(desc); -} - -static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return hweight8(ab->hw_params->hal_ops->rx_desc_get_msdu_nss(desc)); -} - static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, struct hal_rx_desc *desc) { @@ -193,17 +158,11 @@ ab->hw_params->hal_ops->rx_desc_set_msdu_len(desc, len); } -static bool ath12k_dp_rx_h_is_mcbc(struct ath12k_base *ab, - struct hal_rx_desc *desc) -{ - return (ath12k_dp_rx_h_first_msdu(ab, desc) && - ab->hw_params->hal_ops->rx_desc_is_mcbc(desc)); -} - static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, struct hal_rx_desc *desc) { - return ab->hw_params->hal_ops->rx_desc_mac_addr2_valid(desc); + return (ath12k_dp_rx_h_first_msdu(ab, desc) && + ab->hw_params->hal_ops->rx_desc_mac_addr2_valid(desc)); } static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, @@ -227,10 +186,20 @@ ab->hw_params->hal_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); } -static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab, +static inline u8 ath12k_dp_rx_h_msdu_end_ip_valid(struct ath12k_base *ab, + struct hal_rx_desc *desc) +{ + return ab->hw_params->hal_ops->rx_desc_get_ip_valid(desc); +} + +static inline u8 ath12k_dp_rx_get_msdu_src_link(struct ath12k_base *ab, struct hal_rx_desc *desc) { - return ab->hw_params->hal_ops->rx_desc_get_mpdu_frame_ctl(desc); + /* If the ops unassigned, return the first pdev idx */ + if (!ab->hw_params->hal_ops->rx_desc_get_msdu_src_link_id) + return 0; + + return ab->hw_params->hal_ops->rx_desc_get_msdu_src_link_id(desc); } static int ath12k_dp_purge_mon_ring(struct ath12k_base *ab) @@ -255,23 +224,70 @@ return -ETIMEDOUT; } +static size_t ath12k_dp_list_cut_nodes(struct list_head *list, + struct list_head *head, + size_t count) +{ + struct list_head *cur; + struct ath12k_rx_desc_info *rx_desc; + size_t nodes = 0; + + if (!count) { + INIT_LIST_HEAD(list); + goto out; + } + + list_for_each(cur, head) { + if (!count) + break; + + rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); + rx_desc->in_use = true; + + count--; + nodes++; + } + + list_cut_before(list, head, cur); +out: + return nodes; +} + +static void ath12k_dp_rx_enqueue_free(struct ath12k_dp *dp, + struct list_head *used_list) +{ + struct list_head *cur; + struct ath12k_rx_desc_info *rx_desc; + + spin_lock_bh(&dp->rx_desc_lock); + + /* Reset the use flag */ + list_for_each(cur, used_list) { + rx_desc = list_entry(cur, struct ath12k_rx_desc_info, list); + rx_desc->in_use = false; + } + + list_splice_tail(used_list, &dp->rx_desc_free_list); + + spin_unlock_bh(&dp->rx_desc_lock); +} + /* Returns number of Rx buffers replenished */ -int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, int mac_id, +int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, struct dp_rxdma_ring *rx_ring, - int req_entries, - enum hal_rx_buf_return_buf_manager mgr, - bool hw_cc) + struct list_head *used_list, + int req_entries) { struct ath12k_buffer_addr *desc; struct hal_srng *srng; struct sk_buff *skb; int num_free; int num_remain; - int buf_id; u32 cookie; dma_addr_t paddr; struct ath12k_dp *dp = &ab->dp; struct ath12k_rx_desc_info *rx_desc; + enum hal_rx_buf_return_buf_manager mgr = ab->hw_params->hal_params->rx_buf_rbm; req_entries = min(req_entries, rx_ring->bufs_max); @@ -288,10 +304,23 @@ req_entries = min(num_free, req_entries); num_remain = req_entries; + if (!num_remain) + goto skip_replenish; + + /* Get the descriptor from free list */ + if (list_empty(used_list)) { + spin_lock_bh(&dp->rx_desc_lock); + req_entries = ath12k_dp_list_cut_nodes(used_list, + &dp->rx_desc_free_list, + num_remain); + spin_unlock_bh(&dp->rx_desc_lock); + num_remain = req_entries; + } + while (num_remain > 0) { skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE); - if (!skb) + if (unlikely(!skb)) break; if (!IS_ALIGNED((unsigned long)skb->data, @@ -301,52 +330,27 @@ skb->data); } - paddr = dma_map_single(ab->dev, skb->data, + paddr = dma_map_single_attrs(ab->dev, skb->data, skb->len + skb_tailroom(skb), - DMA_FROM_DEVICE); + DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); if (dma_mapping_error(ab->dev, paddr)) goto fail_free_skb; - if (hw_cc) { - spin_lock_bh(&dp->rx_desc_lock); - - /* Get desc from free list and store in used list - * for cleanup purposes - * - * TODO: pass the removed descs rather than - * add/read to optimize - */ - rx_desc = list_first_entry_or_null(&dp->rx_desc_free_list, + rx_desc = list_first_entry_or_null(used_list, struct ath12k_rx_desc_info, list); - if (!rx_desc) { - spin_unlock_bh(&dp->rx_desc_lock); + if (!rx_desc) goto fail_dma_unmap; - } rx_desc->skb = skb; + rx_desc->paddr = paddr; cookie = rx_desc->cookie; - list_del(&rx_desc->list); - list_add_tail(&rx_desc->list, &dp->rx_desc_used_list); - - spin_unlock_bh(&dp->rx_desc_lock); - } else { - spin_lock_bh(&rx_ring->idr_lock); - buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, - rx_ring->bufs_max * 3, GFP_ATOMIC); - spin_unlock_bh(&rx_ring->idr_lock); - if (buf_id < 0) - goto fail_dma_unmap; - cookie = u32_encode_bits(mac_id, - DP_RXDMA_BUF_COOKIE_PDEV_ID) | - u32_encode_bits(buf_id, - DP_RXDMA_BUF_COOKIE_BUF_ID); - } desc = ath12k_hal_srng_src_get_next_entry(ab, srng); if (!desc) - goto fail_buf_unassign; + goto fail_dma_unmap; + list_del(&rx_desc->list); ATH12K_SKB_RXCB(skb)->paddr = paddr; num_remain--; @@ -354,32 +358,27 @@ ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); } +skip_replenish: ath12k_hal_srng_access_end(ab, srng); + if (!list_empty(used_list)) + ath12k_dp_rx_enqueue_free(dp, used_list); + spin_unlock_bh(&srng->lock); return req_entries - num_remain; -fail_buf_unassign: - if (hw_cc) { - spin_lock_bh(&dp->rx_desc_lock); - list_del(&rx_desc->list); - list_add_tail(&rx_desc->list, &dp->rx_desc_free_list); - rx_desc->skb = NULL; - spin_unlock_bh(&dp->rx_desc_lock); - } else { - spin_lock_bh(&rx_ring->idr_lock); - idr_remove(&rx_ring->bufs_idr, buf_id); - spin_unlock_bh(&rx_ring->idr_lock); - } fail_dma_unmap: - dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), - DMA_FROM_DEVICE); + dma_unmap_single_attrs(ab->dev, paddr, skb->len + skb_tailroom(skb), + DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); fail_free_skb: dev_kfree_skb_any(skb); ath12k_hal_srng_access_end(ab, srng); + if (!list_empty(used_list)) + ath12k_dp_rx_enqueue_free(dp, used_list); + spin_unlock_bh(&srng->lock); return req_entries - num_remain; @@ -418,8 +417,10 @@ rx_ring = &dp->rxdma_mon_buf_ring; ath12k_dp_rxdma_buf_ring_free(ab, rx_ring); + if (ab->hw_params->supports_tx_monitor) { rx_ring = &dp->tx_mon_buf_ring; ath12k_dp_rxdma_buf_ring_free(ab, rx_ring); + } return 0; } @@ -428,6 +429,7 @@ struct dp_rxdma_ring *rx_ring, u32 ringtype) { + LIST_HEAD(list); int num_entries; num_entries = rx_ring->refill_buf_ring.size / @@ -437,9 +439,7 @@ if ((ringtype == HAL_RXDMA_MONITOR_BUF) || (ringtype == HAL_TX_MONITOR_BUF)) ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); else - ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_entries, - ab->hw_params->hal_params->rx_buf_rbm, - ringtype == HAL_RXDMA_BUF); + ath12k_dp_rx_bufs_replenish(ab, rx_ring, &list, 0); return 0; } @@ -467,6 +467,7 @@ return ret; } + if (ab->hw_params->supports_tx_monitor) { rx_ring = &dp->tx_mon_buf_ring; ret = ath12k_dp_rxdma_ring_buf_setup(ab, rx_ring, HAL_TX_MONITOR_BUF); @@ -476,6 +477,7 @@ return ret; } } + } return 0; } @@ -488,6 +490,7 @@ for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); + if (ab->hw_params->supports_tx_monitor) ath12k_dp_srng_cleanup(ab, &dp->tx_mon_dst_ring[i]); } } @@ -545,6 +548,7 @@ return ret; } + if (ab->hw_params->supports_tx_monitor) { ret = ath12k_dp_srng_setup(ar->ab, &dp->tx_mon_dst_ring[i], HAL_TX_MONITOR_DST, @@ -556,50 +560,56 @@ return ret; } } + } return 0; } -void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) +static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) { + struct ath12k_reo_queue_ref *qref; struct ath12k_dp *dp = &ab->dp; - struct ath12k_dp_rx_reo_cmd *cmd, *tmp; - struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; + bool ml_peer = false; - spin_lock_bh(&dp->reo_cmd_lock); - list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { - list_del(&cmd->list); - dma_unmap_single(ab->dev, cmd->data.paddr, - cmd->data.size, DMA_BIDIRECTIONAL); - kfree(cmd->data.vaddr); - kfree(cmd); - } + if (!ab->hw_params->reoq_lut_support) + return; - list_for_each_entry_safe(cmd_cache, tmp_cache, - &dp->reo_cmd_cache_flush_list, list) { - list_del(&cmd_cache->list); - dp->reo_cmd_cache_flush_count--; - dma_unmap_single(ab->dev, cmd_cache->data.paddr, - cmd_cache->data.size, DMA_BIDIRECTIONAL); - kfree(cmd_cache->data.vaddr); - kfree(cmd_cache); + if (peer_id & ATH12K_ML_PEER_ID_VALID) { + peer_id &= ~ATH12K_ML_PEER_ID_VALID; + ml_peer = true; } - spin_unlock_bh(&dp->reo_cmd_lock); + + if (ml_peer) + qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + + (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); + else + qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + + (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); + + qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); + qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR); } -static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, - enum hal_reo_cmd_status status) +void ath12k_dp_tid_cleanup(struct ath12k_base *ab) { - struct ath12k_dp_rx_tid *rx_tid = ctx; - - if (status != HAL_REO_CMD_SUCCESS) - ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", - rx_tid->tid, status); + struct ath12k_peer *peer; + struct ath12k_dp_rx_tid *rx_tid; + int tid; + void *vaddr; + u32 *addr_aligned; - dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, - DMA_BIDIRECTIONAL); - kfree(rx_tid->vaddr); - rx_tid->vaddr = NULL; + spin_lock_bh(&ab->base_lock); + list_for_each_entry(peer, &ab->peers, list) { + for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { + rx_tid = &peer->rx_tid[tid]; + if (rx_tid->active) { + vaddr = rx_tid->vaddr; + addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); + ath12k_dp_reset_rx_reo_tid_q(addr_aligned, rx_tid->ba_win_sz, tid); + } + } + } + spin_unlock_bh(&ab->base_lock); } static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, @@ -613,6 +623,10 @@ struct hal_srng *cmd_ring; int cmd_num; + if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags) || + test_bit(ATH12K_FLAG_UMAC_PRERESET_START, &ab->dev_flags)) + return -ESHUTDOWN; + cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); @@ -647,54 +661,137 @@ return 0; } -static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, - struct ath12k_dp_rx_tid *rx_tid) +static int ath12k_peer_rx_tid_delete_handler(struct ath12k_base *ab, + struct ath12k_dp_rx_tid *rx_tid, u8 tid) { struct ath12k_hal_reo_cmd cmd = {0}; - unsigned long tot_desc_sz, desc_sz; - int ret; + struct ath12k_dp *dp = &ab->dp; - tot_desc_sz = rx_tid->size; - desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); + lockdep_assert_held(&dp->reo_cmd_update_rx_queue_lock); - while (tot_desc_sz > desc_sz) { - tot_desc_sz -= desc_sz; - cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); + rx_tid->active = false; + cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; + cmd.addr_lo = lower_32_bits(rx_tid->paddr); cmd.addr_hi = upper_32_bits(rx_tid->paddr); - ret = ath12k_dp_reo_cmd_send(ab, rx_tid, - HAL_REO_CMD_FLUSH_CACHE, &cmd, - NULL); - if (ret) - ath12k_warn(ab, - "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", - rx_tid->tid, ret); + cmd.upd0 |= HAL_REO_CMD_UPD0_VLD; + cmd.upd0 |= HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; + cmd.ba_window_size = (tid == HAL_DESC_REO_NON_QOS_TID) ? + rx_tid->ba_win_sz : DP_BA_WIN_SZ_MAX; + cmd.upd1 |= HAL_REO_CMD_UPD1_VLD; + + return ath12k_dp_reo_cmd_send(ab, rx_tid, + HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, + ath12k_dp_rx_tid_del_func); +} + +void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) +{ + struct ath12k_dp *dp = &ab->dp; + struct ath12k_dp_rx_reo_cmd *cmd, *tmp; + struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; + struct dp_reo_update_rx_queue_elem *cmd_queue, *tmp_queue; + struct ath12k_dp_rx_tid *rx_tid; + + spin_lock_bh(&dp->reo_cmd_update_rx_queue_lock); + list_for_each_entry_safe(cmd_queue, tmp_queue, &dp->reo_cmd_update_rx_queue_list, + list) { + list_del(&cmd_queue->list); + rx_tid = &cmd_queue->data; + if (rx_tid->vaddr) { + dma_unmap_single(ab->dev, rx_tid->paddr, + rx_tid->size, DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); + rx_tid->vaddr = NULL; + } + kfree(cmd_queue); + } + spin_unlock_bh(&dp->reo_cmd_update_rx_queue_lock); + + spin_lock_bh(&dp->reo_cmd_lock); + list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { + list_del(&cmd->list); + rx_tid = &cmd->data; + if (rx_tid->vaddr) { + dma_unmap_single(ab->dev, rx_tid->paddr, + rx_tid->size, DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); + rx_tid->vaddr = NULL; + } + kfree(cmd); + } + + list_for_each_entry_safe(cmd_cache, tmp_cache, + &dp->reo_cmd_cache_flush_list, list) { + list_del(&cmd_cache->list); + dp->reo_cmd_cache_flush_count--; + rx_tid = &cmd_cache->data; + if (rx_tid->vaddr) { + dma_unmap_single(ab->dev, rx_tid->paddr, + rx_tid->size, DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); + rx_tid->vaddr = NULL; + } + kfree(cmd_cache); } + spin_unlock_bh(&dp->reo_cmd_lock); +} + +static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, + enum hal_reo_cmd_status status) +{ + struct ath12k_dp_rx_tid *rx_tid = ctx; + + if (status != HAL_REO_CMD_SUCCESS) + ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", + rx_tid->tid, status); + + ath12k_hal_reo_shared_qaddr_cache_clear(dp->ab); + + if (rx_tid->vaddr) { + dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, + DMA_BIDIRECTIONAL); + kfree(rx_tid->vaddr); + rx_tid->vaddr = NULL; + } +} + +static int ath12k_dp_reo_cache_flush(struct ath12k_base *ab, + struct ath12k_dp_rx_tid *rx_tid) +{ + struct ath12k_hal_reo_cmd cmd = {0}; + int ret; memset(&cmd, 0, sizeof(cmd)); cmd.addr_lo = lower_32_bits(rx_tid->paddr); cmd.addr_hi = upper_32_bits(rx_tid->paddr); - cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; + cmd.flag |= HAL_REO_CMD_FLG_NEED_STATUS | + HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS; + + /* For all NON_QOS tid, driver allocates max window + * size of 1024. For this, driver can send flush 1K Desc + * in one command instead of sending 11 cmd for + * single NON_QOS tid(s). + */ + if (rx_tid->tid != HAL_DESC_REO_NON_QOS_TID) + cmd.flag |= HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC; + ret = ath12k_dp_reo_cmd_send(ab, rx_tid, HAL_REO_CMD_FLUSH_CACHE, &cmd, ath12k_dp_reo_cmd_free); - if (ret) { - ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", - rx_tid->tid, ret); - dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, - DMA_BIDIRECTIONAL); - kfree(rx_tid->vaddr); - rx_tid->vaddr = NULL; - } + + return ret; } static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, enum hal_reo_cmd_status status) { struct ath12k_base *ab = dp->ab; - struct ath12k_dp_rx_tid *rx_tid = ctx; + struct ath12k_dp_rx_tid *rx_tid = ctx, *update_rx_tid; struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; + struct dp_reo_update_rx_queue_elem *qelem, *qtmp; if (status == HAL_REO_CMD_DRAIN) { + ab->soc_stats.hal_reo_cmd_drain++; goto free_desc; } else if (status != HAL_REO_CMD_SUCCESS) { /* Shouldn't happen! Cleanup in case of other failure? */ @@ -703,10 +800,39 @@ return; } + /* Check if there is any pending rx_queue, if yes then update it */ + spin_lock_bh(&dp->reo_cmd_update_rx_queue_lock); + list_for_each_entry_safe(qelem, qtmp, &dp->reo_cmd_update_rx_queue_list, + list) { + if (qelem->reo_cmd_update_rx_queue_resend_flag && + qelem->data.active) { + update_rx_tid = &qelem->data; + + if (ath12k_peer_rx_tid_delete_handler(ab, update_rx_tid, qelem->tid)) { + update_rx_tid->active = true; + break; + } + ath12k_peer_rx_tid_qref_reset(ab, + qelem->is_ml_peer ? qelem->ml_peer_id : qelem->peer_id, + qelem->tid); + ath12k_hal_reo_shared_qaddr_cache_clear(ab); + update_rx_tid->vaddr = NULL; + update_rx_tid->paddr = 0; + update_rx_tid->size = 0; + update_rx_tid->pending_desc_size = 0; + + list_del(&qelem->list); + kfree(qelem); + } + } + spin_unlock_bh(&dp->reo_cmd_update_rx_queue_lock); + elem = kzalloc(sizeof(*elem), GFP_ATOMIC); - if (!elem) + if (!elem) { + ath12k_warn(ab, "failed to alloc reo_cache_flush_elem, rx tid %d\n", + rx_tid->tid); goto free_desc; - + } elem->ts = jiffies; memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); @@ -720,9 +846,6 @@ if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || time_after(jiffies, elem->ts + msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { - list_del(&elem->list); - dp->reo_cmd_cache_flush_count--; - /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list * is used in only two contexts, one is in this function called @@ -732,10 +855,18 @@ * delete to this list. Hence unlock-lock is safe here. */ spin_unlock_bh(&dp->reo_cmd_lock); - - ath12k_dp_reo_cache_flush(ab, &elem->data); - kfree(elem); + if (ath12k_dp_reo_cache_flush(ab, &elem->data)) { + ab->soc_stats.reo_cmd_cache_error++; + /* In failure case, just update the timestamp + * for flush cache elem and continue */ + spin_lock_bh(&dp->reo_cmd_lock); + elem->ts = jiffies; + break; + } spin_lock_bh(&dp->reo_cmd_lock); + list_del(&elem->list); + dp->reo_cmd_cache_flush_count--; + kfree(elem); } } spin_unlock_bh(&dp->reo_cmd_lock); @@ -753,13 +884,20 @@ { struct ath12k_reo_queue_ref *qref; struct ath12k_dp *dp = &ab->dp; + bool ml_peer = false; if (!ab->hw_params->reoq_lut_support) return; - /* TODO: based on ML peer or not, select the LUT. below assumes non - * ML peer - */ + if (peer_id & ATH12K_ML_PEER_ID_VALID) { + peer_id &= ~ATH12K_ML_PEER_ID_VALID; + ml_peer = true; + } + + if (ml_peer) + qref = (struct ath12k_reo_queue_ref *)dp->ml_reoq_lut.vaddr + + (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); + else qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); @@ -768,56 +906,63 @@ qref->info1 = u32_encode_bits(upper_32_bits(paddr), BUFFER_ADDR_INFO1_ADDR) | u32_encode_bits(tid, DP_REO_QREF_NUM); -} - -static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) -{ - struct ath12k_reo_queue_ref *qref; - struct ath12k_dp *dp = &ab->dp; - if (!ab->hw_params->reoq_lut_support) - return; - - /* TODO: based on ML peer or not, select the LUT. below assumes non - * ML peer - */ - qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + - (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); - - qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); - qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | - u32_encode_bits(tid, DP_REO_QREF_NUM); + ath12k_hal_reo_shared_qaddr_cache_clear(ab); } void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, struct ath12k_peer *peer, u8 tid) { - struct ath12k_hal_reo_cmd cmd = {0}; struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; - int ret; + struct dp_reo_update_rx_queue_elem *elem, *tmp; + struct ath12k_base *ab = ar->ab; + struct ath12k_dp *dp = &ab->dp; if (!rx_tid->active) return; - cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; - cmd.addr_lo = lower_32_bits(rx_tid->paddr); - cmd.addr_hi = upper_32_bits(rx_tid->paddr); - cmd.upd0 = HAL_REO_CMD_UPD0_VLD; - ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, - HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, - ath12k_dp_rx_tid_del_func); - if (ret) { - ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", - tid, ret); - dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, - DMA_BIDIRECTIONAL); - kfree(rx_tid->vaddr); - rx_tid->vaddr = NULL; + elem = kzalloc(sizeof(*elem), GFP_ATOMIC); + if (!elem) { + ath12k_warn(ar->ab, "failed to alloc reo_update_rx_queue_elem, rx tid %d\n", + rx_tid->tid); + return; } + elem->reo_cmd_update_rx_queue_resend_flag = false; + elem->peer_id = peer->peer_id; + elem->tid = tid; + elem->is_ml_peer = peer->mlo ? true : false; + elem->ml_peer_id = peer->ml_peer_id; + + memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); - ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); + spin_lock_bh(&dp->reo_cmd_update_rx_queue_lock); + list_add_tail(&elem->list, &dp->reo_cmd_update_rx_queue_list); - rx_tid->active = false; + list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_update_rx_queue_list, + list) { + rx_tid = &elem->data; + + if (ath12k_peer_rx_tid_delete_handler(ab, rx_tid, elem->tid)) { + rx_tid->active = true; + ab->soc_stats.reo_cmd_update_rx_queue_error++; + elem->reo_cmd_update_rx_queue_resend_flag = true; + break; + } + ath12k_peer_rx_tid_qref_reset(ab, + elem->is_ml_peer ? elem->ml_peer_id : elem->peer_id, + elem->tid); + ath12k_hal_reo_shared_qaddr_cache_clear(ab); + rx_tid->vaddr = NULL; + rx_tid->paddr = 0; + rx_tid->size = 0; + rx_tid->pending_desc_size = 0; + + list_del(&elem->list); + kfree(elem); + } + spin_unlock_bh(&dp->reo_cmd_update_rx_queue_lock); + + return; } /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted @@ -889,14 +1034,13 @@ ath12k_dp_rx_peer_tid_delete(ar, peer, i); ath12k_dp_rx_frags_cleanup(rx_tid, true); - spin_unlock_bh(&ar->ab->base_lock); del_timer_sync(&rx_tid->frag_timer); spin_lock_bh(&ar->ab->base_lock); } } -static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, +static int ath12k_peer_rx_tid_reo_update(struct ath12k_base *ab, struct ath12k_peer *peer, struct ath12k_dp_rx_tid *rx_tid, u32 ba_win_sz, u16 ssn, @@ -916,11 +1060,11 @@ cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); } - ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, + ret = ath12k_dp_reo_cmd_send(ab, rx_tid, HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, NULL); if (ret) { - ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", + ath12k_warn(ab, "failed to update rx tid queue, tid %d (%d)\n", rx_tid->tid, ret); return ret; } @@ -930,31 +1074,79 @@ return 0; } -int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, - u8 tid, u32 ba_win_sz, u16 ssn, - enum hal_pn_type pn_type) +void ath12k_dp_peer_reo_tid_setup(struct ath12k_base *ab, + struct ath12k_link_sta *arsta) +{ + struct ath12k_dp_rx_tid *rx_tid; + struct ath12k_peer *peer; + u8 tid; + int ret; + + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_addr(ab, arsta->addr); + if (peer) { + for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { + rx_tid = &peer->rx_tid[tid]; + if (rx_tid->active) { + ret = ath12k_peer_rx_tid_reo_update(ab, peer, rx_tid, + rx_tid->ba_win_sz, 0, false); + if (ret) { + ath12k_warn(ab, "failed to update reo for peer %pM rx tid %d\n", + peer->addr, tid); + } + } + } + } + spin_unlock_bh(&ab->base_lock); +} + +void ath12k_dp_tid_setup(void *data, struct ieee80211_sta *sta) +{ + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_base *ab = data; + struct ath12k_link_sta *arsta; + struct ath12k_link_vif *arvif; + u8 link_id; + + if (sta->mlo) + return; + + for_each_set_bit(link_id, &ahsta->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arsta = ahsta->link[link_id]; + if (!arsta) + continue; + arvif = arsta->arvif; + if (arvif->ab == ab) + ath12k_dp_peer_reo_tid_setup(ab, arsta); + } +} + +void ath12k_dp_peer_tid_setup(struct ath12k_base *ab) +{ + struct ath12k *ar; + int i; + + for (i = 0; i < ab->num_radios; i++) { + ar = ab->pdevs[i].ar; + ieee80211_iterate_stations_atomic(ar->ah->hw, + ath12k_dp_tid_setup, + ab); + } +} + +int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, u8 tid, u32 ba_win_sz, u16 ssn, + enum hal_pn_type pn_type, struct ath12k_peer *peer) { struct ath12k_base *ab = ar->ab; struct ath12k_dp *dp = &ab->dp; struct hal_rx_reo_queue *addr_aligned; - struct ath12k_peer *peer; struct ath12k_dp_rx_tid *rx_tid; u32 hw_desc_sz; void *vaddr; dma_addr_t paddr; int ret; - spin_lock_bh(&ab->base_lock); - - peer = ath12k_peer_find(ab, vdev_id, peer_mac); - if (!peer) { - spin_unlock_bh(&ab->base_lock); - ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); - return -ENOENT; - } - - if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) { - spin_unlock_bh(&ab->base_lock); + if (ab->hw_params->reoq_lut_support && (!dp->reoq_lut.vaddr || !dp->ml_reoq_lut.vaddr)) { ath12k_warn(ab, "reo qref table is not setup\n"); return -EINVAL; } @@ -962,7 +1154,6 @@ if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", peer->peer_id, tid); - spin_unlock_bh(&ab->base_lock); return -EINVAL; } @@ -970,16 +1161,28 @@ /* Update the tid queue if it is already setup */ if (rx_tid->active) { paddr = rx_tid->paddr; - ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, + ret = ath12k_peer_rx_tid_reo_update(ab, peer, rx_tid, ba_win_sz, ssn, true); - spin_unlock_bh(&ab->base_lock); if (ret) { - ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); + ath12k_warn(ab, "failed to update reo for peer %pM rx tid %d\n", + peer->addr, tid); return ret; } + if (!ab->hw_params->reoq_lut_support) { + ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, peer->vdev_id, + peer->addr, + paddr, tid, 1, + ba_win_sz); + if (ret) { + ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", + tid, ret); return ret; } + } + + return 0; + } rx_tid->tid = tid; @@ -995,7 +1198,6 @@ vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); if (!vaddr) { - spin_unlock_bh(&ab->base_lock); return -ENOMEM; } @@ -1009,7 +1211,8 @@ ret = dma_mapping_error(ab->dev, paddr); if (ret) { - spin_unlock_bh(&ab->base_lock); + ath12k_warn(ab, "failed to dma map for peer %pM rx tid :%d setup\n", + peer->addr, tid); goto err_mem_free; } @@ -1022,52 +1225,87 @@ /* Update the REO queue LUT at the corresponding peer id * and tid with qaddr. */ + if (peer->mlo) + ath12k_peer_rx_tid_qref_setup(ab, peer->ml_peer_id, tid, paddr); + else ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr); - spin_unlock_bh(&ab->base_lock); } else { spin_unlock_bh(&ab->base_lock); - ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, + ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, peer->vdev_id, peer->addr, paddr, tid, 1, ba_win_sz); + spin_lock_bh(&ab->base_lock); } return ret; err_mem_free: - kfree(vaddr); - + kfree(rx_tid->vaddr); + rx_tid->vaddr = NULL; return ret; } int ath12k_dp_rx_ampdu_start(struct ath12k *ar, - struct ieee80211_ampdu_params *params) + struct ieee80211_ampdu_params *params, + u8 link_id) { struct ath12k_base *ab = ar->ab; - struct ath12k_sta *arsta = (void *)params->sta->drv_priv; - int vdev_id = arsta->arvif->vdev_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); + struct ath12k_link_sta *arsta; + struct ath12k_peer *peer; + int vdev_id; int ret; - ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id, - params->tid, params->buf_size, - params->ssn, arsta->pn_type); + arsta = ahsta->link[link_id]; + + if (!arsta) + return -ENOENT; + + vdev_id = arsta->arvif->vdev_id; + + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find(ab, vdev_id, arsta->addr); + if (!peer) { + ath12k_warn(ab, "failed to lookup peer %pM on vdev %d\n", + arsta->addr, vdev_id); + spin_unlock_bh(&ab->base_lock); + return -ENOENT; + } + + if (!peer->primary_link) { + spin_unlock_bh(&ab->base_lock); + return 0; + } + + ret = ath12k_dp_rx_peer_tid_setup(ar, params->tid, params->buf_size, + params->ssn, ahsta->pn_type, peer); if (ret) ath12k_warn(ab, "failed to setup rx tid %d\n", ret); + spin_unlock_bh(&ab->base_lock); return ret; } int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, - struct ieee80211_ampdu_params *params) + struct ieee80211_ampdu_params *params, + u8 link_id) { struct ath12k_base *ab = ar->ab; struct ath12k_peer *peer; - struct ath12k_sta *arsta = (void *)params->sta->drv_priv; - int vdev_id = arsta->arvif->vdev_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(params->sta); + struct ath12k_link_sta *arsta; + int vdev_id; bool active; int ret; + arsta = ahsta->link[link_id]; + + if (!arsta) + return -ENOENT; + + vdev_id = arsta->arvif->vdev_id; spin_lock_bh(&ab->base_lock); - peer = ath12k_peer_find(ab, vdev_id, params->sta->addr); + peer = ath12k_peer_find(ab, vdev_id, arsta->addr); if (!peer) { spin_unlock_bh(&ab->base_lock); ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); @@ -1081,7 +1319,7 @@ return 0; } - ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); + ret = ath12k_peer_rx_tid_reo_update(ab, peer, peer->rx_tid, 1, 0, false); spin_unlock_bh(&ab->base_lock); if (ret) { ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", @@ -1092,7 +1330,7 @@ return ret; } -int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif, +int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif, const u8 *peer_addr, enum set_key_cmd key_cmd, struct ieee80211_key_conf *key) @@ -1182,6 +1420,26 @@ return -EINVAL; } +static void ath12k_htt_pktlog(struct ath12k_base *ab, struct sk_buff *skb) +{ + struct htt_pktlog_msg *data = (struct htt_pktlog_msg *)skb->data; + struct ath12k_pktlog_hdr *hdr = (struct ath12k_pktlog_hdr *)data; + struct ath12k *ar; + u8 pdev_id; + + pdev_id = u32_get_bits(data->hdr, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); + ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); + if (!ar) { + ath12k_warn(ab, "invalid pdev id %d on htt pktlog\n", pdev_id); + return; + } + hdr->m_timestamp = ar->pdev->timestamp; + + trace_ath12k_htt_pktlog(ar, data->payload, hdr->size, + ar->ab->pktlog_defs_checksum); + ath12k_htt_pktlog_process(ar, (u8 *)data->payload); +} + static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, u16 tag, u16 len, const void *ptr, void *data) @@ -1193,6 +1451,7 @@ struct htt_ppdu_user_stats *user_stats; int cur_user; u16 peer_id; + u32 ppdu_id; ppdu_info = data; @@ -1223,7 +1482,7 @@ user_stats->is_valid_peer_id = true; memcpy(&user_stats->rate, ptr, sizeof(struct htt_ppdu_stats_user_rate)); - user_stats->tlv_flags |= BIT(tag); + ppdu_info->tlv_bitmap |= BIT(tag); break; case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { @@ -1243,7 +1502,7 @@ user_stats->is_valid_peer_id = true; memcpy(&user_stats->cmpltn_cmn, ptr, sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); - user_stats->tlv_flags |= BIT(tag); + ppdu_info->tlv_bitmap |= BIT(tag); break; case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: if (len < @@ -1254,6 +1513,8 @@ } ba_status = ptr; + ppdu_id = + ((struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *)ptr)->ppdu_id; peer_id = le16_to_cpu(ba_status->sw_peer_id); cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, peer_id); @@ -1262,24 +1523,34 @@ user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; user_stats->peer_id = peer_id; user_stats->is_valid_peer_id = true; + ppdu_info->ppdu_id = FIELD_GET(HTT_PPDU_STATS_PPDU_ID, ppdu_id); memcpy(&user_stats->ack_ba, ptr, sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); - user_stats->tlv_flags |= BIT(tag); + ppdu_info->tlv_bitmap |= BIT(tag); + break; + case HTT_PPDU_STATS_TAG_SCH_CMD_STATUS: + ppdu_info->tlv_bitmap |= BIT(tag); break; } return 0; } -static int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, +int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, const void *ptr, void *data), void *data) { + struct htt_ppdu_stats_info *ppdu_info = NULL; const struct htt_tlv *tlv; const void *begin = ptr; u16 tlv_tag, tlv_len; int ret = -EINVAL; + if (!data) + return ret; + + ppdu_info = (struct htt_ppdu_stats_info *)data; + while (len > 0) { if (len < sizeof(*tlv)) { ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", @@ -1297,7 +1568,7 @@ tlv_tag, ptr - begin, len, tlv_len); return -EINVAL; } - ret = iter(ab, tlv_tag, tlv_len, ptr, data); + ret = iter(ab, tlv_tag, tlv_len, ptr, ppdu_info); if (ret == -ENOMEM) return ret; @@ -1307,68 +1578,162 @@ return 0; } +static u32 ath12k_dp_rx_ru_alloc_from_ru_size(u16 ru_size) +{ + u32 width = 0; + + switch (ru_size) { + case HTT_PPDU_STATS_RU_26: + width = NL80211_RATE_INFO_HE_RU_ALLOC_26; + break; + case HTT_PPDU_STATS_RU_52: + width = NL80211_RATE_INFO_HE_RU_ALLOC_52; + break; + case HTT_PPDU_STATS_RU_106: + width = NL80211_RATE_INFO_HE_RU_ALLOC_106; + break; + case HTT_PPDU_STATS_RU_242: + width = NL80211_RATE_INFO_HE_RU_ALLOC_242; + break; + case HTT_PPDU_STATS_RU_484: + width = NL80211_RATE_INFO_HE_RU_ALLOC_484; + break; + case HTT_PPDU_STATS_RU_996: + width = NL80211_RATE_INFO_HE_RU_ALLOC_996; + break; + default: + width = NL80211_RATE_INFO_HE_RU_ALLOC_26; + break; + } + + return width; +} + +/* Align bw value as per host data structures */ +static u8 ath12k_htt_bw_to_mac_bw(u32 rate_flags) +{ + u8 bw = HTT_USR_RATE_BW(rate_flags); + + switch (bw) { + case HTT_PPDU_STATS_BANDWIDTH_320MHZ: + bw = ATH12K_BW_320; + break; + case HTT_PPDU_STATS_BANDWIDTH_160MHZ: + bw = ATH12K_BW_160; + break; + case HTT_PPDU_STATS_BANDWIDTH_80MHZ: + bw = ATH12K_BW_80; + break; + case HTT_PPDU_STATS_BANDWIDTH_40MHZ: + bw = ATH12K_BW_40; + break; + default: + bw = ATH12K_BW_20; + break; + } + + return bw; +} + static void ath12k_update_per_peer_tx_stats(struct ath12k *ar, - struct htt_ppdu_stats *ppdu_stats, u8 user) + struct htt_ppdu_stats_info *ppdu_info, u8 user) { struct ath12k_base *ab = ar->ab; struct ath12k_peer *peer; struct ieee80211_sta *sta; - struct ath12k_sta *arsta; + struct ath12k_link_sta *arsta; struct htt_ppdu_stats_user_rate *user_rate; + struct htt_ppdu_stats *ppdu_stats = &ppdu_info->ppdu_stats; struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; struct htt_ppdu_stats_common *common = &ppdu_stats->common; int ret; u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; - u32 v, succ_bytes = 0; - u16 tones, rate = 0, succ_pkts = 0; - u32 tx_duration = 0; + u32 v, succ_bytes = 0, ppdu_type; + u16 rate = 0, succ_pkts = 0, ru_start, ru_end; + u32 tx_duration = 0, ru_tones, ru_format, tlv_bitmap, rate_flags; + bool is_ampdu = false, resp_type_valid; + u8 tid = HTT_PPDU_STATS_NON_QOS_TID; - bool is_ampdu = false; if (!usr_stats) return; - if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) + tlv_bitmap = ppdu_info->tlv_bitmap; + + if (!(tlv_bitmap & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) return; - if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) + if (tlv_bitmap & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) { is_ampdu = HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); + if (tlv_bitmap & BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS)) { + succ_pkts = usr_stats->cmpltn_cmn.mpdu_success; + tid = usr_stats->cmpltn_cmn.tid_num; + } + } - if (usr_stats->tlv_flags & - BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { + if (tlv_bitmap & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); succ_pkts = le32_get_bits(usr_stats->ack_ba.info, HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); tid = le32_get_bits(usr_stats->ack_ba.info, HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); + ar->wmm_stats.tx_type = ath12k_tid_to_ac(tid > ATH12K_DSCP_PRIORITY ? 0: tid); + ar->wmm_stats.total_wmm_tx_pkts[ar->wmm_stats.tx_type]++; } if (common->fes_duration_us) tx_duration = le32_to_cpu(common->fes_duration_us); user_rate = &usr_stats->rate; - flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); - bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; - nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; - mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); - sgi = HTT_USR_RATE_GI(user_rate->rate_flags); - dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); + ppdu_type = HTT_USR_RATE_PPDU_TYPE(user_rate->info1); + + resp_type_valid = u32_get_bits(user_rate->info1, + HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALID); + if (resp_type_valid) { + rate_flags = user_rate->resp_rate_flags; + ru_start = user_rate->resp_ru_start; + ru_end = user_rate->ru_end; + ppdu_type = HTT_USR_RESP_RATE_PPDU_TYPE(user_rate->resp_rate_flags); + if (ppdu_type == HTT_PPDU_STATS_RESP_PPDU_TYPE_MU_OFDMA_UL) + ppdu_type = HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA; + else + ppdu_type = HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO; + } else { + rate_flags = user_rate->rate_flags; + ru_start = user_rate->ru_start; + ru_end = user_rate->ru_end; + } + + flags = HTT_USR_RATE_PREAMBLE(rate_flags); + bw = ath12k_htt_bw_to_mac_bw(rate_flags); + nss = HTT_USR_RATE_NSS(rate_flags) + 1; + mcs = HTT_USR_RATE_MCS(rate_flags); + sgi = HTT_USR_RATE_GI(rate_flags); + dcm = HTT_USR_RATE_DCM(rate_flags); + ru_format = FIELD_GET(HTT_PPDU_STATS_USER_RATE_INFO0_RU_SIZE, + user_rate->info0); + if (ru_format == 1) + ru_tones = ath12k_dp_rx_ru_alloc_from_ru_size(ru_start); + else if (!ru_format) + ru_tones = ru_end - ru_start + 1; + else + ru_tones = ath12k_dp_rx_ru_alloc_from_ru_size(HTT_PPDU_STATS_RU_26); /* Note: If host configured fixed rates and in some other special * cases, the broadcast/management frames are sent in different rates. * Firmware rate's control to be skipped for this? */ - if (flags == WMI_RATE_PREAMBLE_HE && mcs > 11) { + if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); return; } - if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { - ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); + if (flags == WMI_RATE_PREAMBLE_EHT && mcs > ATH12K_EHT_MCS_MAX) { + ath12k_warn(ab, "Invalid EHT mcs %d peer stats", mcs); return; } @@ -1403,7 +1768,12 @@ } sta = peer->sta; - arsta = (struct ath12k_sta *)sta->drv_priv; + arsta = ath12k_peer_get_link_sta(ab, peer); + if (!arsta) { + spin_unlock_bh(&ab->base_lock); + rcu_read_unlock(); + return; + } memset(&arsta->txrate, 0, sizeof(arsta->txrate)); @@ -1431,10 +1801,21 @@ arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; arsta->txrate.he_dcm = dcm; arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); - tones = le16_to_cpu(user_rate->ru_end) - - le16_to_cpu(user_rate->ru_start) + 1; - v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); - arsta->txrate.he_ru_alloc = v; + arsta->txrate.he_ru_alloc = ru_tones; + peer_stats->ru_tones = arsta->txrate.he_ru_alloc; + break; + case WMI_RATE_PREAMBLE_EHT: + arsta->txrate.mcs = mcs; + arsta->txrate.flags = RATE_INFO_FLAGS_EHT_MCS; + arsta->txrate.he_dcm = dcm; + arsta->txrate.eht_gi = ath12k_eht_gi_to_nl80211_eht_gi(sgi); + v = ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc((ru_end - + ru_start) + 1); + arsta->txrate.eht_ru_alloc = v; + ru_tones = v; + peer_stats->ru_tones = arsta->txrate.eht_ru_alloc; + break; + default: break; } @@ -1452,9 +1833,13 @@ peer_stats->succ_bytes = succ_bytes; peer_stats->is_ampdu = is_ampdu; peer_stats->duration = tx_duration; + peer_stats->ru_tones = ru_tones; peer_stats->ba_fails = HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); + peer_stats->ppdu_type = ppdu_type; + if (ath12k_debugfs_is_extd_tx_stats_enabled(ar)) + ath12k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); } spin_unlock_bh(&ab->base_lock); @@ -1462,12 +1847,12 @@ } static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, - struct htt_ppdu_stats *ppdu_stats) + struct htt_ppdu_stats_info *ppdu_info) { u8 user; for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) - ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); + ath12k_update_per_peer_tx_stats(ar, ppdu_info, user); } static @@ -1488,7 +1873,7 @@ typeof(*ppdu_info), list); list_del(&ppdu_info->list); ar->ppdu_stat_list_depth--; - ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); + ath12k_htt_update_ppdu_stats(ar, ppdu_info); kfree(ppdu_info); } } @@ -1558,6 +1943,11 @@ goto exit; } + if (ath12k_debugfs_is_pktlog_lite_mode_enabled(ar)) { + trace_ath12k_htt_ppdu_stats(ar, skb->data, len); + ath12k_htt_ppdu_pktlog_process(ar, (u8 *)skb->data, DP_RX_BUFFER_SIZE); + } + spin_lock_bh(&ar->data_lock); ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); if (!ppdu_info) { @@ -1623,23 +2013,72 @@ return ret; } +static void ath12k_htt_backpressure_event_handler(struct ath12k_base *ab, + struct sk_buff *skb) +{ + u32 *data = (u32 *)skb->data; + u8 pdev_id, ring_type, ring_id, pdev_idx; + u16 hp, tp; + u32 backpressure_time; + struct ath12k_bp_stats *bp_stats; + + pdev_id = u32_get_bits(*data, HTT_BACKPRESSURE_EVENT_PDEV_ID_M); + ring_type = u32_get_bits(*data, HTT_BACKPRESSURE_EVENT_RING_TYPE_M); + ring_id = u32_get_bits(*data, HTT_BACKPRESSURE_EVENT_RING_ID_M); + ++data; + + hp = u32_get_bits(*data, HTT_BACKPRESSURE_EVENT_HP_M); + tp = u32_get_bits(*data, HTT_BACKPRESSURE_EVENT_TP_M); + ++data; + + backpressure_time = *data; + + ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "htt backpressure event, pdev %d, ring type %d,ring id %d, hp %d tp %d, backpressure time %d\n", + pdev_id, ring_type, ring_id, hp, tp, backpressure_time); + + if (ring_type == HTT_BACKPRESSURE_UMAC_RING_TYPE) { + if (ring_id >= HTT_SW_UMAC_RING_IDX_MAX) + return; + + bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[ring_id]; + } else if (ring_type == HTT_BACKPRESSURE_LMAC_RING_TYPE) { + pdev_idx = DP_HW2SW_MACID(pdev_id); + + if (ring_id >= HTT_SW_LMAC_RING_IDX_MAX || pdev_idx >= MAX_RADIOS) + return; + + bp_stats = &ab->soc_stats.bp_stats.lmac_ring_bp_stats[ring_id][pdev_idx]; + } else { + ath12k_warn(ab, "unknown ring type received in htt bp event %d\n", + ring_type); + return; + } + + spin_lock_bh(&ab->base_lock); + bp_stats->hp = hp; + bp_stats->tp = tp; + bp_stats->count++; + bp_stats->jiffies = jiffies; + spin_unlock_bh(&ab->base_lock); +} + static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, struct sk_buff *skb) { struct ath12k_htt_mlo_offset_msg *msg; + struct ath12k_hw_group *ag = ab->ag; struct ath12k_pdev *pdev; struct ath12k *ar; u8 pdev_id; + int i, j; msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; pdev_id = u32_get_bits(__le32_to_cpu(msg->info), HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); - if (!ar) { - ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id); + if (!ar) return; - } spin_lock_bh(&ar->data_lock); pdev = ar->pdev; @@ -1653,9 +2092,160 @@ pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); + ag->mlo_tstamp_offset = ((u64)pdev->timestamp.mlo_offset_hi << 32 | pdev->timestamp.mlo_offset_lo); + + /* MLO TSAMP OFFSET is common for all chips and + * fetch delta_tsf2 for all the radios for this event + */ + for (i = 0; i < ag->num_chip; i++) { + struct ath12k_base *tmp_ab = ag->ab[i]; + + for (j = 0; j < tmp_ab->num_radios; j++) { + struct ath12k *tmp_ar; + + pdev = &tmp_ab->pdevs[j]; + tmp_ar = pdev->ar; + if (!tmp_ar) + continue; + + if (tmp_ab->hw_params->hal_ops->hal_get_tsf2_scratch_reg) + tmp_ab->hw_params->hal_ops->hal_get_tsf2_scratch_reg(tmp_ab, tmp_ar->lmac_id, + &tmp_ar->delta_tsf2); + } + } + + spin_unlock_bh(&ar->data_lock); } +static void ath12k_htt_vdev_txrx_stats_handler(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct htt_t2h_vdev_txrx_stats_ind *vdev_tlv; + struct htt_t2h_vdev_common_stats_tlv *soc_tlv; + struct ath12k_link_vif *arvif; + u32 *data = (u32 *)skb->data; + u32 vdev_id; + u16 payload_bytes, tlv_tag, tlv_len; + + payload_bytes = u32_get_bits(*data, HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES); + data += 3; + + if (payload_bytes > skb->len) + return; + + while (payload_bytes > 0) { + tlv_tag = u32_get_bits(*data, HAL_TLV_HDR_TAG); + tlv_len = u32_get_bits(*data, HAL_TLV_HDR_LEN); + data++; + + if (tlv_tag == HTT_VDEV_TXRX_STATS_HW_STATS_TLV) { + vdev_tlv = (struct htt_t2h_vdev_txrx_stats_ind *)data; + vdev_id = __le32_to_cpu(vdev_tlv->vdev_id); + arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_id); + + arvif->vdev_stats.rx_msdu_byte_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->rx_msdu_byte_cnt_lo, + vdev_tlv->rx_msdu_byte_cnt_hi); + arvif->vdev_stats.rx_msdu_pkt_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->rx_msdu_cnt_lo, + vdev_tlv->rx_msdu_cnt_hi); + arvif->vdev_stats.tx_msdu_byte_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->tx_msdu_byte_cnt_lo, + vdev_tlv->tx_msdu_byte_cnt_hi); + arvif->vdev_stats.tx_msdu_pkt_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->tx_msdu_cnt_lo, + vdev_tlv->tx_msdu_cnt_hi); + arvif->vdev_stats.tx_retry_byte_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->tx_retry_byte_cnt_lo, + vdev_tlv->tx_retry_byte_cnt_hi); + arvif->vdev_stats.tx_retry_pkt_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->tx_retry_cnt_lo, + vdev_tlv->tx_retry_cnt_hi); + arvif->vdev_stats.tx_drop_byte_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->tx_drop_byte_cnt_lo, + vdev_tlv->tx_drop_byte_cnt_hi); + arvif->vdev_stats.tx_msdu_ttl_byte_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->msdu_ttl_byte_cnt_lo, + vdev_tlv->msdu_ttl_byte_cnt_hi); + arvif->vdev_stats.tx_msdu_ttl_pkt_cnt = + HTT_VDEV_GET_STATS_U64(vdev_tlv->msdu_ttl_cnt_lo, + vdev_tlv->msdu_ttl_cnt_hi); + } + + if (tlv_tag == HTT_VDEV_TXRX_STATS_COMMON_TLV) { + soc_tlv = (struct htt_t2h_vdev_common_stats_tlv *)data; + ab->fw_soc_drop_count = + HTT_VDEV_GET_STATS_U64(soc_tlv->soc_drop_count_lo, + soc_tlv->soc_drop_count_hi); + } + data += tlv_len >> 2; + payload_bytes -= tlv_len; + } +} + +#ifdef CONFIG_ATH12K_SAWF +static void ath12k_htt_sawf_info_ind_handler(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct htt_t2h_sawf_info_ind *resp = (struct htt_t2h_sawf_info_ind *)skb->data; + struct ath12k_peer *peer = NULL; + u32 htt_qtype, remapped_tid, peer_id, default_msduq_per_tid, default_msduq_max, sawf_msduq_per_tid; + u32 hlos_tid, flow_or, ast_idx, who_cl, tgt_opaque_id, sawf_msduq_max; + u8 msduq_index; + + htt_qtype = u32_get_bits(__le32_to_cpu(resp->info0), + HTT_T2H_SAWF_MSDUQ_INFO_0_IND_HTT_QTYPE_ID); + peer_id = u32_get_bits(__le32_to_cpu(resp->info0), + HTT_T2H_SAWF_MSDUQ_INFO_0_IND_PEER_ID); + + remapped_tid = u32_get_bits(__le32_to_cpu(resp->info1), + HTT_T2H_SAWF_MSDUQ_INFO_1_IND_REMAP_TID_ID); + hlos_tid = u32_get_bits(__le32_to_cpu(resp->info1), + HTT_T2H_SAWF_MSDUQ_INFO_1_IND_HLOS_TID_ID); + who_cl = u32_get_bits(__le32_to_cpu(resp->info1), + HTT_T2H_SAWF_MSDUQ_INFO_1_IND_WHO_CLSFY_INFO_SEL_ID); + flow_or = u32_get_bits(__le32_to_cpu(resp->info1), + HTT_T2H_SAWF_MSDUQ_INFO_1_IND_FLOW_OVERRIDE_ID); + ast_idx = u32_get_bits(__le32_to_cpu(resp->info1), + HTT_T2H_SAWF_MSDUQ_INFO_1_IND_AST_INDEX_ID); + + tgt_opaque_id = u32_get_bits(__le32_to_cpu(resp->info2), + HTT_T2H_SAWF_MSDUQ_INFO_2_IND_TGT_OPAQUE_ID); + + ath12k_dbg(ab, ATH12K_DBG_SAWF, "Sawf Info ind:\n"); + ath12k_dbg(ab, ATH12K_DBG_SAWF, + "htt_qtype[0x%x]Peer_Id[0x%x]Remp_Tid[0x%x]Hlos_Tid[0x%x]\n", + htt_qtype, + peer_id, + remapped_tid, + hlos_tid); + ath12k_dbg(ab, ATH12K_DBG_SAWF, + "who_cl[0x%x]flow_or[0x%x]Ast[0x%x]Op[0x%x]\n", + who_cl, + flow_or, + ast_idx, + tgt_opaque_id); + spin_lock_bh(&ab->base_lock); + + default_msduq_per_tid = ab->default_msduq_per_tid; + sawf_msduq_per_tid = ab->max_msduq_per_tid - ab->default_msduq_per_tid; + default_msduq_max = default_msduq_per_tid * ATH12K_SAWF_MAX_TID_SUPPORT; + sawf_msduq_max = sawf_msduq_per_tid * ATH12K_SAWF_MAX_TID_SUPPORT; + msduq_index = ((who_cl * default_msduq_max) + + (flow_or * ATH12K_SAWF_MAX_TID_SUPPORT) + hlos_tid) - + default_msduq_max; + + peer = ath12k_peer_find_by_id(ab, peer_id); + if ((msduq_index < sawf_msduq_max) && peer) { + if (peer->sawf_ctx_peer.telemetry_peer_ctx) + ath12k_telemetry_update_tid_msduq(peer->sawf_ctx_peer.telemetry_peer_ctx, + msduq_index ,remapped_tid, + (htt_qtype - default_msduq_per_tid)); + } + spin_unlock_bh(&ab->base_lock); +} +#endif /* CONFIG_ATH12K_SAWF */ void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, struct sk_buff *skb) { @@ -1691,6 +2281,8 @@ HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), peer_mac_h16, mac_addr); + ast_hash = FIELD_GET(HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL, + resp->peer_map_ev.info2); ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); break; case HTT_T2H_MSG_TYPE_PEER_MAP2: @@ -1718,8 +2310,12 @@ HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), peer_mac_h16, mac_addr); + ast_hash = FIELD_GET(HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL, + resp->peer_map_ev.info2); + hw_peer_id = FIELD_GET(HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID, + resp->peer_map_ev.info2); ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, - peer_id); + hw_peer_id); break; case HTT_T2H_MSG_TYPE_PEER_UNMAP: case HTT_T2H_MSG_TYPE_PEER_UNMAP2: @@ -1727,14 +2323,41 @@ HTT_T2H_PEER_UNMAP_INFO_PEER_ID); ath12k_peer_unmap_event(ab, peer_id); break; + case HTT_T2H_MSG_TYPE_MLO_RX_PEER_MAP: + ath12k_peer_mlo_map_event(ab, skb); + break; + case HTT_T2H_MSG_TYPE_MLO_RX_PEER_UNMAP: + ath12k_peer_mlo_unmap_event(ab, skb); + break; case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: ath12k_htt_pull_ppdu_stats(ab, skb); break; case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: + ath12k_debugfs_htt_ext_stats_handler(ab, skb); + break; + case HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND: + ath12k_htt_backpressure_event_handler(ab, skb); + break; + case HTT_T2H_MSG_TYPE_PKTLOG: + ath12k_htt_pktlog(ab, skb); break; case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: ath12k_htt_mlo_offset_event_handler(ab, skb); break; + case HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND: + ath12k_htt_vdev_txrx_stats_handler(ab, skb); + break; +#ifdef CONFIG_ATH12K_SAWF + case HTT_T2H_MSG_TYPE_SAWF_MSDUQ_INFO_IND: + ath12k_htt_sawf_info_ind_handler(ab, skb); + break; + case HTT_T2H_MSG_TYPE_SAWF_DEF_QUEUES_MAP_REPORT_CONF: + ath12k_htt_sawf_def_q_map_report_handler(ab, skb); + break; + case HTT_T2H_MSG_TYPE_STREAMING_STATS_IND: + ath12k_htt_sawf_streaming_stats_ind_handler(ab, skb); + break; +#endif /* CONFIG_ATH12K_SAWF */ default: ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", type); @@ -1747,7 +2370,8 @@ static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, struct sk_buff_head *msdu_list, struct sk_buff *first, struct sk_buff *last, - u8 l3pad_bytes, int msdu_len) + u8 l3pad_bytes, int msdu_len, + struct ath12k_dp_rx_info *rx_info) { struct ath12k_base *ab = ar->ab; struct sk_buff *skb; @@ -1756,6 +2380,7 @@ struct hal_rx_desc *ldesc; int space_extra, rem_len, buf_len; u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; + bool is_continuation; /* As the msdu is spread across multiple rx buffers, * find the offset to the start of msdu for computing @@ -1771,8 +2396,9 @@ } ldesc = (struct hal_rx_desc *)last->data; - rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); - rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); + ab->hw_params->hal_ops->rx_desc_get_first_last_msdu(ldesc, rx_info); + rxcb->is_first_msdu = rx_info->is_first_msdu; + rxcb->is_last_msdu = rx_info->is_last_msdu; /* MSDU spans over multiple buffers because the length of the MSDU * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data @@ -1804,7 +2430,8 @@ rem_len = msdu_len - buf_first_len; while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { rxcb = ATH12K_SKB_RXCB(skb); - if (rxcb->is_continuation) + is_continuation = rxcb->is_continuation; + if (is_continuation) buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; else buf_len = rem_len; @@ -1822,8 +2449,15 @@ dev_kfree_skb_any(skb); rem_len -= buf_len; - if (!rxcb->is_continuation) + if (!is_continuation) break; + + skb = msdu_list->next; + if (likely(skb)) { + prefetch(skb); + prefetch(skb->data + 64); + prefetch(skb->data + 128); + } } return 0; @@ -1847,14 +2481,13 @@ return NULL; } -static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu) +static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu, + struct ath12k_dp_rx_info *rx_info) { - struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); - struct ath12k_base *ab = ar->ab; bool ip_csum_fail, l4_csum_fail; - ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc); - l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc); + ip_csum_fail = rx_info->ip_csum_fail; + l4_csum_fail = rx_info->l4_csum_fail; msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? CHECKSUM_NONE : CHECKSUM_UNNECESSARY; @@ -2000,7 +2633,9 @@ if (!rxcb->is_first_msdu || !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { - WARN_ON_ONCE(1); + /* TODO: Change below stats increment back to WARN_ON_ONCE(1) + */ + ar->ab->soc_stats.first_and_last_msdu_bit_miss++; return; } @@ -2055,10 +2690,9 @@ struct hal_rx_desc *rx_desc = rxcb->rx_desc; struct ath12k_base *ab = ar->ab; size_t hdr_len, crypto_len; - struct ieee80211_hdr *hdr; + struct ieee80211_hdr hdr; + u8 *crypto_hdr, mesh_ctrl; u16 qos_ctl; - __le16 fc; - u8 *crypto_hdr; if (!(status->flag & RX_FLAG_IV_STRIPPED)) { crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); @@ -2066,26 +2700,25 @@ ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); } - fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc)); - hdr_len = ieee80211_hdrlen(fc); - skb_push(msdu, hdr_len); - hdr = (struct ieee80211_hdr *)msdu->data; - hdr->frame_control = fc; - /* Get wifi header from rx_desc */ - ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr); + ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, &hdr); + + hdr_len = ieee80211_hdrlen(hdr.frame_control); + mesh_ctrl = ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc); + skb_push(msdu, hdr_len); + memcpy(msdu->data, &hdr, min(hdr_len, sizeof(hdr))); if (rxcb->is_mcbc) status->flag &= ~RX_FLAG_PN_VALIDATED; /* Add QOS header */ - if (ieee80211_is_data_qos(hdr->frame_control)) { + if (ieee80211_is_data_qos(hdr.frame_control)) { qos_ctl = rxcb->tid; - if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc)) + if (mesh_ctrl) qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; /* TODO: Add other QoS ctl fields when required */ - memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN), + memcpy(ieee80211_get_qos_ctl((struct ieee80211_hdr *)msdu->data), &qos_ctl, IEEE80211_QOS_CTL_LEN); } } @@ -2143,7 +2776,8 @@ ehdr = (struct ethhdr *)msdu->data; /* mac80211 allows fast path only for authorized STA */ - if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { + if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE) || + enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) { ATH12K_SKB_RXCB(msdu)->is_eapol = true; ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); break; @@ -2159,10 +2793,12 @@ /* TODO: Handle undecap for these formats */ break; } + ar->wmm_stats.total_wmm_rx_pkts[ar->wmm_stats.rx_type]++; } struct ath12k_peer * -ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu) +ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu, + struct ath12k_dp_rx_info *rx_info) { struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); struct hal_rx_desc *rx_desc = rxcb->rx_desc; @@ -2176,19 +2812,83 @@ if (peer) return peer; - if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) - return NULL; - - peer = ath12k_peer_find_by_addr(ab, + if (!(rx_info->filled & BIT_ULL(ATH12K_RX_INFO_ADDR2))) { + if (rx_desc && ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)) { + ether_addr_copy(rx_info->addr2, ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, rx_desc)); + rx_info->filled |= BIT_ULL(ATH12K_RX_INFO_ADDR2); + } else { + return NULL; + } + } + + peer = ath12k_peer_find_by_addr(ab, rx_info->addr2); return peer; } +static bool ath12k_dp_rx_check_fast_rx(struct ath12k *ar, + struct sk_buff *msdu, + struct hal_rx_desc *rx_desc, + struct ath12k_peer *peer, + struct ath12k_dp_rx_info *rx_info) +{ + struct ethhdr *ehdr; + struct ath12k_peer *f_peer; + struct ath12k_skb_rxcb *rxcb; + u8 decap; + bool ip_is_valid; + + lockdep_assert_held(&ar->ab->base_lock); + + decap = rx_info->decap_type; + ip_is_valid = rx_info->ip_is_valid; + + rxcb = ATH12K_SKB_RXCB(msdu); + + if (unlikely(!ar->ab->stats_disable || + decap != DP_RX_DECAP_TYPE_ETHERNET2_DIX || + peer->vif->type != NL80211_IFTYPE_AP)) + return false; + + /* mcbc packets go through mac80211 for PN validation */ + if (unlikely(rxcb->is_mcbc)) + return false; + + if (unlikely(!peer->is_authorized)) + return false; + + if (unlikely(!ip_is_valid)) + return false; + + /* fast rx is supported only on ethernet decap, so + * we can directly gfet the ethernet header + */ + ehdr = (struct ethhdr *)msdu->data; + + /* requires rebroadcast from mac80211 */ + if (is_multicast_ether_addr(ehdr->h_dest)) + return false; + + /* TODO: make use of hw assisted intra-bss bit in msdu_end + * to skip peer lookup and forward frames directly. + */ + + /* check if the msdu needs to be bridged to our connected peer */ + f_peer = ath12k_peer_find_by_addr(ar->ab, ehdr->h_dest); + + if (f_peer && f_peer != peer) + return false; + + /* allow direct rx */ + return true; +} + static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, struct sk_buff *msdu, struct hal_rx_desc *rx_desc, - struct ieee80211_rx_status *rx_status) + struct ath12k_dp_rx_info *rx_info, + bool *fast_rx) { bool fill_crypto_hdr; struct ath12k_base *ab = ar->ab; @@ -2197,19 +2897,62 @@ bool is_decrypted = false; struct ieee80211_hdr *hdr; struct ath12k_peer *peer; + struct ieee80211_rx_status *rx_status = rx_info->rx_status; u32 err_bitmap; + struct ath12k_dp_rx_tid *rx_tid; + u8 tid; +#if defined(CONFIG_MAC80211_PPE_SUPPORT) || defined(CONFIG_ATH12K_BONDED_DS_SUPPORT) + int vp; +#endif + struct wireless_dev *wdev = NULL; /* PN for multicast packets will be checked in mac80211 */ rxcb = ATH12K_SKB_RXCB(msdu); - fill_crypto_hdr = ath12k_dp_rx_h_is_mcbc(ar->ab, rx_desc); + fill_crypto_hdr = rx_info->is_mcbc; rxcb->is_mcbc = fill_crypto_hdr; if (rxcb->is_mcbc) - rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc); + rxcb->peer_id = rx_info->peer_id; spin_lock_bh(&ar->ab->base_lock); - peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); + peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu, rx_info); if (peer) { + /* If the pkt is a valid IP packet and peer supports + * fast rx, deliver directly to net, also note that + * pkts with crypto error are not expected to arrive in this + * path, so its safe to skip checking errors here */ + if (*fast_rx && + ath12k_dp_rx_check_fast_rx(ar, msdu, rx_desc, peer, rx_info)) { + wdev = ieee80211_vif_to_wdev(peer->vif); + if (wdev) { +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + vp = peer->ppe_vp_num; + if (unlikely(wdev->bond_netdev)) + msdu->dev = wdev->bond_netdev; + else +#endif + msdu->dev = wdev->netdev; + + spin_unlock_bh(&ar->ab->base_lock); + ath12k_dp_rx_h_csum_offload(ar, msdu, rx_info); +#if defined(CONFIG_MAC80211_PPE_SUPPORT) || defined(CONFIG_ATH12K_BONDED_DS_SUPPORT) + if (vp > 0) { + if (likely(ppe_vp_tx_to_ppe(vp, msdu))) + return; + } +#endif + msdu->protocol = eth_type_trans(msdu, msdu->dev); + netif_receive_skb(msdu); + return; + } + } + + tid = rx_info->tid; + rx_tid = &peer->rx_tid[tid]; + ar->wmm_stats.rx_type = + ath12k_tid_to_ac(rx_tid->tid > ATH12K_DSCP_PRIORITY ? 0: rx_tid->tid); + ar->wmm_stats.total_wmm_rx_pkts[ar->wmm_stats.rx_type]++; + if (rxcb->is_mcbc) enctype = peer->sec_type_grp; else @@ -2219,6 +2962,16 @@ } spin_unlock_bh(&ar->ab->base_lock); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + if (peer) { + wdev = ieee80211_vif_to_wdev(peer->vif); + if (wdev && wdev->bond_netdev) + msdu->dev = wdev->bond_netdev; + } +#endif + + *fast_rx = false; + err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); @@ -2246,36 +2999,43 @@ RX_FLAG_PN_VALIDATED; } - ath12k_dp_rx_h_csum_offload(ar, msdu); + ath12k_dp_rx_h_csum_offload(ar, msdu, rx_info); ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, enctype, rx_status, is_decrypted); if (!is_decrypted || fill_crypto_hdr) return; - if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) != - DP_RX_DECAP_TYPE_ETHERNET2_DIX) { + if (rx_info->decap_type != DP_RX_DECAP_TYPE_ETHERNET2_DIX) { hdr = (void *)msdu->data; hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); } } -static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc, - struct ieee80211_rx_status *rx_status) +static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct ath12k_dp_rx_info *rx_info) { - struct ath12k_base *ab = ar->ab; + struct ieee80211_rx_status *rx_status = rx_info->rx_status; struct ieee80211_supported_band *sband; - enum rx_msdu_start_pkt_type pkt_type; - u8 bw; - u8 rate_mcs, nss; - u8 sgi; + enum rx_msdu_start_pkt_type pkt_type = RX_MSDU_START_PKT_TYPE_11A; + u8 bw = 0; + u8 rate_mcs = 0, nss = 0; + u8 sgi = 0; bool is_cck; - pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); - bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); - rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); - nss = ath12k_dp_rx_h_nss(ab, rx_desc); - sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); + if (rx_info->filled & BIT_ULL(ATH12K_RX_INFO_PKT_TYPE)) + pkt_type = rx_info->pkt_type; + + if (rx_info->filled & BIT_ULL(ATH12K_RX_INFO_BW)) + bw = rx_info->bw; + + if (rx_info->filled & BIT_ULL(ATH12K_RX_INFO_RATE_MCS)) + rate_mcs = rx_info->rate_mcs; + + if (rx_info->filled & BIT_ULL(ATH12K_RX_INFO_NSS)) + nss = rx_info->nss; + + if (rx_info->filled & BIT_ULL(ATH12K_RX_INFO_SGI)) + sgi = rx_info->sgi; switch (pkt_type) { case RX_MSDU_START_PKT_TYPE_11A: @@ -2322,18 +3082,55 @@ } rx_status->encoding = RX_ENC_HE; rx_status->nss = nss; + rx_status->he_gi = ath12k_mac_he_gi_to_nl80211_he_gi(sgi); + rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); + break; + case RX_MSDU_START_PKT_TYPE_11BE: + rx_status->rate_idx = rate_mcs; + if (rate_mcs > ATH12K_EHT_MCS_MAX) { + ath12k_warn(ar->ab, + "Received with invalid mcs in EHT mode %d\n", + rate_mcs); + break; + } + rx_status->encoding = RX_ENC_EHT; + rx_status->nss = nss; rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); break; + default: + break; } } -void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc, - struct ieee80211_rx_status *rx_status) +static void ath12k_dp_rx_h_fetch_info(struct ath12k_base *ab, + struct hal_rx_desc *rx_desc, + struct ath12k_dp_rx_info *rx_info) { - struct ath12k_base *ab = ar->ab; + ab->hw_params->hal_ops->rx_get_desc_info(rx_desc, rx_info); + rx_info->filled |= BIT_ULL(ATH12K_RX_INFO_PHY_META_DATA) | + BIT_ULL(ATH12K_RX_INFO_DECAP_TYPE) | + BIT_ULL(ATH12K_RX_INFO_PKT_TYPE) | + BIT_ULL(ATH12K_RX_INFO_SGI) | + BIT_ULL(ATH12K_RX_INFO_RATE_MCS) | + BIT_ULL(ATH12K_RX_INFO_BW) | + BIT_ULL(ATH12K_RX_INFO_NSS); + + if (ab->stats_disable) + return; + + if (ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc)) { + ether_addr_copy(rx_info->addr2, + ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, rx_desc)); + rx_info->filled |= BIT_ULL(ATH12K_RX_INFO_ADDR2); + } +} + +void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct ath12k_dp_rx_info *rx_info) +{ + struct ieee80211_rx_status *rx_status = rx_info->rx_status; u8 channel_num; - u32 center_freq, meta_data; + u32 center_freq, meta_data = 0; struct ieee80211_channel *channel; rx_status->freq = 0; @@ -2345,38 +3142,52 @@ rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; - meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); + if (rx_info->filled & BIT_ULL(ATH12K_RX_INFO_PHY_META_DATA)) + meta_data = rx_info->phy_meta_data; + channel_num = meta_data; center_freq = meta_data >> 16; - if (center_freq >= 5935 && center_freq <= 7105) { + rx_status->band = NUM_NL80211_BANDS; + + if (center_freq >= ATH12K_MIN_6G_FREQ && + center_freq <= ATH12K_MAX_6G_FREQ) { rx_status->band = NL80211_BAND_6GHZ; - } else if (channel_num >= 1 && channel_num <= 14) { + rx_status->freq = center_freq; + } else if (channel_num >= ATH12K_MIN_2G_CHAN && + channel_num <= ATH12K_MAX_2G_CHAN) { rx_status->band = NL80211_BAND_2GHZ; - } else if (channel_num >= 36 && channel_num <= 173) { + } else if (channel_num >= ATH12K_MIN_5G_CHAN && + channel_num <= ATH12K_MAX_5G_CHAN) { rx_status->band = NL80211_BAND_5GHZ; - } else { + } + + if (unlikely(rx_status->band == NUM_NL80211_BANDS || !ar->ah->hw->wiphy->bands[rx_status->band])) { + ath12k_err(ar->ab, "sband is NULL for status band %d channel_num %d center_freq %d pdev_id %d\n", + rx_status->band, channel_num, center_freq, ar->pdev_idx); + spin_lock_bh(&ar->data_lock); channel = ar->rx_channel; if (channel) { rx_status->band = channel->band; channel_num = ieee80211_frequency_to_channel(channel->center_freq); + } else { + ath12k_err(ar->ab, "unable to determine channel, band for rx packet"); } spin_unlock_bh(&ar->data_lock); - ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", - rx_desc, sizeof(*rx_desc)); } + if (rx_status->band != NL80211_BAND_6GHZ) rx_status->freq = ieee80211_channel_to_frequency(channel_num, rx_status->band); - ath12k_dp_rx_h_rate(ar, rx_desc, rx_status); + ath12k_dp_rx_h_rate(ar, rx_info); } static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, struct sk_buff *msdu, - struct ieee80211_rx_status *status) + struct ath12k_dp_rx_info *rx_info) { struct ath12k_base *ab = ar->ab; static const struct ieee80211_radiotap_he known = { @@ -2386,12 +3197,14 @@ }; struct ieee80211_radiotap_he *he; struct ieee80211_rx_status *rx_status; - struct ieee80211_sta *pubsta; - struct ath12k_peer *peer; + struct ieee80211_sta *pubsta = NULL; + struct ath12k_peer *peer = NULL; struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); u8 decap = DP_RX_DECAP_TYPE_RAW; bool is_mcbc = rxcb->is_mcbc; bool is_eapol = rxcb->is_eapol; + struct ath12k_link_sta *arsta = NULL; + struct ieee80211_rx_status *status = rx_info->rx_status; if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) && !(status->flag & RX_FLAG_SKIP_MONITOR)) { @@ -2400,31 +3213,42 @@ status->flag |= RX_FLAG_RADIOTAP_HE; } - if (!(status->flag & RX_FLAG_ONLY_MONITOR)) - decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc); + if (!(status->flag & RX_FLAG_ONLY_MONITOR) && + rx_info->filled & BIT_ULL(ATH12K_RX_INFO_DECAP_TYPE)) + decap = rx_info->decap_type; spin_lock_bh(&ab->base_lock); - peer = ath12k_dp_rx_h_find_peer(ab, msdu); + if (rxcb->peer_id) + peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); + if (!peer && (rx_info->filled & BIT_ULL(ATH12K_RX_INFO_ADDR2))) + peer = ath12k_peer_find_by_addr(ab, rx_info->addr2); - pubsta = peer ? peer->sta : NULL; + if (peer && peer->sta) { + pubsta = peer->sta; + if (pubsta->valid_links) { + status->link_valid = 1; + status->link_id = peer->link_id; + } + } spin_unlock_bh(&ab->base_lock); ath12k_dbg(ab, ATH12K_DBG_DATA, - "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", + "rx skb %pK len %u peer %pM %d %s %s%s%s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", msdu, msdu->len, peer ? peer->addr : NULL, rxcb->tid, is_mcbc ? "mcast" : "ucast", - ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", (status->encoding == RX_ENC_HT) ? "ht" : "", (status->encoding == RX_ENC_VHT) ? "vht" : "", (status->encoding == RX_ENC_HE) ? "he" : "", + (status->encoding == RX_ENC_EHT) ? "eht" : "", (status->bw == RATE_INFO_BW_40) ? "40" : "", (status->bw == RATE_INFO_BW_80) ? "80" : "", (status->bw == RATE_INFO_BW_160) ? "160" : "", + (status->bw == RATE_INFO_BW_320) ? "320" : "", status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", status->rate_idx, status->nss, @@ -2451,13 +3275,47 @@ !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) rx_status->flag |= RX_FLAG_8023; - ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); + ieee80211_rx_napi(ar->ah->hw, pubsta, msdu, napi); + + if (ath12k_debugfs_is_extd_rx_stats_enabled(ar)) { + if (!(status->flag & RX_FLAG_ONLY_MONITOR)) { + spin_lock_bh(&ar->ab->base_lock); + if (peer && peer->sta) + arsta = ath12k_peer_get_link_sta(ar->ab, peer); + spin_unlock_bh(&ar->ab->base_lock); + if (arsta) + atomic_inc(&arsta->drv_rx_pkts.pkts_out); + } + } +} + +static bool ath12k_dp_rx_check_max_nwifi_hdr_len(struct ath12k_base *ab, + struct hal_rx_desc *rx_desc, + struct sk_buff *msdu, + const char *msg) +{ + struct ieee80211_hdr *hdr; + u32 hdr_len; + + hdr = (struct ieee80211_hdr *)msdu->data; + hdr_len = ieee80211_hdrlen(hdr->frame_control); + if (unlikely(hdr_len > DP_MAX_NWIFI_HDR_LEN)) { + ab->soc_stats.invalid_rbm++; + ath12k_err_dump(ab, msg, "msdu_data: ", msdu->data, msdu->len, + NULL); + ath12k_err_dump(ab, NULL, "rx_desc: ", rx_desc, sizeof(*rx_desc), + NULL); + return true; + } + + return false; } static int ath12k_dp_rx_process_msdu(struct ath12k *ar, struct sk_buff *msdu, struct sk_buff_head *msdu_list, - struct ieee80211_rx_status *rx_status) + struct ath12k_dp_rx_info *rx_info, + bool *fast_rx) { struct ath12k_base *ab = ar->ab; struct hal_rx_desc *rx_desc, *lrx_desc; @@ -2478,7 +3336,8 @@ rx_desc = (struct hal_rx_desc *)msdu->data; lrx_desc = (struct hal_rx_desc *)last_buf->data; - if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { + ab->hw_params->hal_ops->rx_get_desc_msdulen_l3pad(lrx_desc, rx_info); + if (!rx_info->msdu_done) { ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); ret = -EIO; goto free_out; @@ -2486,8 +3345,8 @@ rxcb = ATH12K_SKB_RXCB(msdu); rxcb->rx_desc = rx_desc; - msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); - l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); + msdu_len = rx_info->msdu_len; + l3_pad_bytes = rx_info->l3_pad_bytes; if (rxcb->is_frag) { skb_pull(msdu, hal_rx_desc_sz); @@ -2504,7 +3363,8 @@ } else { ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, msdu, last_buf, - l3_pad_bytes, msdu_len); + l3_pad_bytes, msdu_len, + rx_info); if (ret) { ath12k_warn(ab, "failed to coalesce msdu rx buffer%d\n", ret); @@ -2512,10 +3372,23 @@ } } - ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status); - ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); + ath12k_dp_rx_h_fetch_info(ab, rx_desc, rx_info); + + if (rx_info->decap_type == DP_RX_DECAP_TYPE_NATIVE_WIFI && + ath12k_dp_rx_check_max_nwifi_hdr_len(ab, rx_desc, msdu, + "Invalid len in Rx\n")) { + WARN_ON_ONCE(1); + ret = -EINVAL; + goto free_out; + } + + ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_info, fast_rx); + if (*fast_rx) + return 0; + + ath12k_dp_rx_h_ppdu(ar, rx_info); - rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; + rx_info->rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; return 0; @@ -2530,131 +3403,255 @@ { struct ieee80211_rx_status rx_status = {0}; struct ath12k_skb_rxcb *rxcb; + struct ath12k_dp_rx_info rx_info; struct sk_buff *msdu; struct ath12k *ar; - u8 mac_id; + u8 mac_id, hw_link_id; int ret; + bool fast_rx; + struct sk_buff *skb; if (skb_queue_empty(msdu_list)) return; + rx_info.filled = 0; + rx_info.rx_status = &rx_status; + rcu_read_lock(); while ((msdu = __skb_dequeue(msdu_list))) { + skb = msdu_list->next; + if (likely(skb)) { + prefetch(skb); + prefetch(&skb->protocol); + prefetch(&skb->data); + prefetch(skb->data); + prefetch(skb->data + 64); + prefetch(skb->data + 128); + } rxcb = ATH12K_SKB_RXCB(msdu); - mac_id = rxcb->mac_id; - ar = ab->pdevs[mac_id].ar; - if (!rcu_dereference(ab->pdevs_active[mac_id])) { + /* Enable fast rx by default, the value will cahnge based on peer cap + * and packet type */ + fast_rx = true; + rxcb->napi = napi; + + hw_link_id = rxcb->hw_link_id; + if (hw_link_id >= ATH12K_GROUP_MAX_RADIO) { dev_kfree_skb_any(msdu); + ath12k_warn(ab, "invalid hw link id %d\n", hw_link_id); continue; } - if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { + ar = rcu_dereference(ab->ag->hw_links[hw_link_id]); + if (!ar) { + dev_kfree_skb_any(msdu); + ath12k_warn(ab, "invalid pdev for hw link id %d\n", hw_link_id); + continue; + } + + mac_id = ar->pdev_idx; + if (!rcu_dereference(ar->ab->pdevs_active[mac_id])) { + dev_kfree_skb_any(msdu); + continue; + } + + if (unlikely(test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags))) { dev_kfree_skb_any(msdu); continue; } - ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); + ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_info, + &fast_rx); if (ret) { ath12k_dbg(ab, ATH12K_DBG_DATA, - "Unable to process msdu %d", ret); + "Unable to process %s chip_id %d msdu %d", + (ab != ar->ab) ? "partner" : "own", + ar->ab->chip_id, ret); dev_kfree_skb_any(msdu); continue; } - ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); + if (!fast_rx) { + ab->soc_stats.non_fast_rx[ring_id][ar->ab->chip_id]++; + ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_info); + } else { + ab->soc_stats.fast_rx[ring_id][ar->ab->chip_id]++; + } } rcu_read_unlock(); } +/* Sends WMI config to filter packets to route packets to WBM release ring */ +int ath12k_dp_rx_pkt_type_filter(struct ath12k *ar, + enum ath12k_routing_pkt_type pkt_type, + u32 meta_data) +{ + struct ath12k_wmi_pkt_route_param param; + int ret; + + /* Routing Eapol/ARP packets to CCE is only allowed now */ + if (pkt_type != ATH12K_PKT_TYPE_EAP && + pkt_type != ATH12K_PKT_TYPE_ARP_IPV4) + return -EINVAL; + + param.opcode = ATH12K_WMI_PKTROUTE_ADD; + param.meta_data = meta_data; + param.dst_ring = ATH12K_ROUTE_WBM_RELEASE(ar->ab); + param.dst_ring_handler = ATH12K_WMI_PKTROUTE_USE_CCE; + param.route_type_bmap = 1 << pkt_type; + + ret = ath12k_wmi_send_pdev_pkt_route(ar, ¶m); + if (ret) + ath12k_warn(ar->ab, "failed to configure pkt route %d", ret); + + return ret; +} + int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, struct napi_struct *napi, int budget) { + struct ath12k_base *src_ab; struct ath12k_rx_desc_info *desc_info; struct ath12k_dp *dp = &ab->dp; struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; - struct hal_reo_dest_ring *desc; - int num_buffs_reaped = 0; + int i, num_buffs_reaped[ATH12K_MAX_SOCS] = { }; struct sk_buff_head msdu_list; struct ath12k_skb_rxcb *rxcb; int total_msdu_reaped = 0; struct hal_srng *srng; struct sk_buff *msdu; + u32 *rx_desc; bool done = false; - int mac_id; u64 desc_va; + struct ath12k_link_sta *arsta = NULL; + struct ath12k_peer *peer = NULL; + struct ath12k *ar; + u8 hw_link_id, chip_id; + int valid_entries; + struct list_head rx_desc_used_list[ATH12K_MAX_SOCS]; __skb_queue_head_init(&msdu_list); + for (i = 0; i < ATH12K_MAX_SOCS; i++) + INIT_LIST_HEAD(&rx_desc_used_list[i]); + srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; spin_lock_bh(&srng->lock); try_again: ath12k_hal_srng_access_begin(ab, srng); + valid_entries = ath12k_hal_srng_dst_num_free(ab, srng, false); + if (unlikely(!valid_entries)) { + ath12k_hal_srng_access_end(ab, srng); + spin_unlock_bh(&srng->lock); + return -EINVAL; + } + ath12k_hal_srng_dst_invalidate_entry(ab, srng, valid_entries); - while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { + while (likely((rx_desc = ath12k_hal_srng_dst_get_next_cache_entry(ab, srng)))) { + struct hal_reo_dest_ring desc = *(struct hal_reo_dest_ring *)rx_desc; enum hal_reo_dest_ring_push_reason push_reason; u32 cookie; - cookie = le32_get_bits(desc->buf_addr_info.info1, + cookie = le32_get_bits(desc.buf_addr_info.info1, BUFFER_ADDR_INFO1_SW_COOKIE); - mac_id = le32_get_bits(desc->info0, - HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); - desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | - le32_to_cpu(desc->buf_va_lo)); + hw_link_id = le32_get_bits(desc.info0, + HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); + desc_va = ((u64)le32_to_cpu(desc.buf_va_hi) << 32 | + le32_to_cpu(desc.buf_va_lo)); desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); + rcu_read_lock(); + + if (hw_link_id < ATH12K_GROUP_MAX_RADIO) + ar = rcu_dereference(ab->ag->hw_links[hw_link_id]); + else + ar = NULL; + + if (!ar) { + rcu_read_unlock(); + + ab->soc_stats.hal_reo_error[ring_id]++; + ath12k_warn(ab, "Rx with invalid/inactive hw_link_id %d cookie 0x%x\n", hw_link_id, cookie); + + if (desc_info) { + dev_kfree_skb_any(desc_info->skb); + desc_info->skb = NULL; + } + continue; + } + + src_ab = ar->ab; + rcu_read_unlock(); + /* retry manual desc retrieval */ + if (unlikely(!desc_info)) { + desc_info = ath12k_dp_get_rx_desc(src_ab, cookie); if (!desc_info) { - desc_info = ath12k_dp_get_rx_desc(ab, cookie); - if (!desc_info) { - ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); + ath12k_warn(ab, "Invalid cookie in manual desc retrieval cookie 0x%x", cookie); continue; } } - if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) + if (unlikely(desc_info->magic != ATH12K_DP_RX_DESC_MAGIC)) ath12k_warn(ab, "Check HW CC implementation"); + chip_id = src_ab->chip_id; + msdu = desc_info->skb; desc_info->skb = NULL; + desc_info->paddr = 0; - spin_lock_bh(&dp->rx_desc_lock); - list_move_tail(&desc_info->list, &dp->rx_desc_free_list); - spin_unlock_bh(&dp->rx_desc_lock); + list_add_tail(&desc_info->list, &rx_desc_used_list[chip_id]); rxcb = ATH12K_SKB_RXCB(msdu); - dma_unmap_single(ab->dev, rxcb->paddr, + dmac_inv_range_no_dsb(msdu->data, msdu->data + (msdu->len + skb_tailroom(msdu))); + dma_unmap_single_attrs(src_ab->dev, rxcb->paddr, msdu->len + skb_tailroom(msdu), - DMA_FROM_DEVICE); + DMA_FROM_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); - num_buffs_reaped++; + num_buffs_reaped[chip_id]++; + ab->soc_stats.reo_rx[ring_id][chip_id]++; - push_reason = le32_get_bits(desc->info0, + push_reason = le32_get_bits(desc.info0, HAL_REO_DEST_RING_INFO0_PUSH_REASON); - if (push_reason != - HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { + if (unlikely(push_reason != + HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION)) { dev_kfree_skb_any(msdu); - ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; + ab->soc_stats.hal_reo_error[ring_id]++; continue; } - rxcb->is_first_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & + rxcb->is_first_msdu = !!(le32_to_cpu(desc.rx_msdu_info.info0) & RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); - rxcb->is_last_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & + rxcb->is_last_msdu = !!(le32_to_cpu(desc.rx_msdu_info.info0) & RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); - rxcb->is_continuation = !!(le32_to_cpu(desc->rx_msdu_info.info0) & + rxcb->is_continuation = !!(le32_to_cpu(desc.rx_msdu_info.info0) & RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); - rxcb->mac_id = mac_id; - rxcb->peer_id = le32_get_bits(desc->rx_mpdu_info.peer_meta_data, + rxcb->hw_link_id = hw_link_id; + rxcb->peer_id = le32_get_bits(desc.rx_mpdu_info.peer_meta_data, RX_MPDU_DESC_META_DATA_PEER_ID); - rxcb->tid = le32_get_bits(desc->rx_mpdu_info.info0, + rxcb->tid = le32_get_bits(desc.rx_mpdu_info.info0, RX_MPDU_DESC_INFO0_TID); + ar->wmm_stats.rx_type = ath12k_tid_to_ac(rxcb->tid > ATH12K_DSCP_PRIORITY ? 0: rxcb->tid); + + if (ath12k_debugfs_is_extd_rx_stats_enabled(ar) && rxcb->peer_id) { + rcu_read_lock(); + spin_lock_bh(&src_ab->base_lock); + peer = ath12k_peer_find_by_id(src_ab, rxcb->peer_id); + if (peer && peer->sta) + arsta = ath12k_peer_get_link_sta(src_ab, peer); + spin_unlock_bh(&src_ab->base_lock); + if (arsta) + atomic_inc(&arsta->drv_rx_pkts.pkts_frm_hw); + rcu_read_unlock(); + } + __skb_queue_tail(&msdu_list, msdu); if (!rxcb->is_continuation) { @@ -2683,12 +3680,23 @@ spin_unlock_bh(&srng->lock); - if (!total_msdu_reaped) + if (unlikely(!total_msdu_reaped)) goto exit; - /* TODO: Move to implicit BM? */ - ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_buffs_reaped, - ab->hw_params->hal_params->rx_buf_rbm, true); + for (i = 0; i < ab->ag->num_chip; i++) { + if (!num_buffs_reaped[i]) + continue; + + src_ab = ab->ag->ab[i]; + if (!src_ab) + continue; + + rx_ring = &src_ab->dp.rx_refill_buf_ring; + + ath12k_dp_rx_bufs_replenish(src_ab, rx_ring, + &rx_desc_used_list[i], + num_buffs_reaped[i]); + } ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, ring_id); @@ -2711,27 +3719,13 @@ spin_unlock_bh(&rx_tid->ab->base_lock); } -int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) +int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, struct ath12k_peer *peer, + struct crypto_shash *tfm) { struct ath12k_base *ab = ar->ab; - struct crypto_shash *tfm; - struct ath12k_peer *peer; struct ath12k_dp_rx_tid *rx_tid; int i; - tfm = crypto_alloc_shash("michael_mic", 0, 0); - if (IS_ERR(tfm)) - return PTR_ERR(tfm); - - spin_lock_bh(&ab->base_lock); - - peer = ath12k_peer_find(ab, vdev_id, peer_mac); - if (!peer) { - spin_unlock_bh(&ab->base_lock); - ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); - return -ENOENT; - } - for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { rx_tid = &peer->rx_tid[i]; rx_tid->ab = ab; @@ -2740,7 +3734,7 @@ } peer->tfm_mmic = tfm; - spin_unlock_bh(&ab->base_lock); + peer->dp_setup_done = true; return 0; } @@ -2795,6 +3789,7 @@ struct ieee80211_key_conf *key_conf; struct ieee80211_hdr *hdr; u8 mic[IEEE80211_CCMP_MIC_LEN]; + struct ath12k_dp_rx_info rx_info; int head_len, tail_len, ret; size_t data_len; u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; @@ -2804,6 +3799,9 @@ if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) return 0; + rx_info.filled = 0; + rx_info.rx_status = rxs; + hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); hdr_len = ieee80211_hdrlen(hdr->frame_control); head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; @@ -2830,14 +3828,23 @@ (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; + ath12k_dp_rx_h_fetch_info(ab, rx_desc, &rx_info); + rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; skb_pull(msdu, hal_rx_desc_sz); - ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); + if (rx_info.decap_type == DP_RX_DECAP_TYPE_NATIVE_WIFI && + ath12k_dp_rx_check_max_nwifi_hdr_len(ab, rx_desc, msdu, + "Invalid len in verify tkip\n")) { + WARN_ON_ONCE(1); + return -EINVAL; + } + + ath12k_dp_rx_h_ppdu(ar, &rx_info); ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); - ieee80211_rx(ar->hw, msdu); + ieee80211_rx(ar->ah->hw, msdu); return -EINVAL; } @@ -2992,7 +3999,7 @@ buf_paddr = dma_map_single(ab->dev, defrag_skb->data, defrag_skb->len + skb_tailroom(defrag_skb), - DMA_FROM_DEVICE); + DMA_TO_DEVICE); if (dma_mapping_error(ab->dev, buf_paddr)) return -ENOMEM; @@ -3008,9 +4015,9 @@ } desc_info->skb = defrag_skb; + desc_info->in_use = true; list_del(&desc_info->list); - list_add_tail(&desc_info->list, &dp->rx_desc_used_list); spin_unlock_bh(&dp->rx_desc_lock); ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; @@ -3036,7 +4043,7 @@ ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, cookie, - HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST); + dp->idle_link_rbm_id); mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | @@ -3072,13 +4079,13 @@ err_free_desc: spin_lock_bh(&dp->rx_desc_lock); - list_del(&desc_info->list); - list_add_tail(&desc_info->list, &dp->rx_desc_free_list); desc_info->skb = NULL; + desc_info->in_use = false; + list_add_tail(&desc_info->list, &dp->rx_desc_free_list); spin_unlock_bh(&dp->rx_desc_lock); err_unmap_dma: dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), - DMA_FROM_DEVICE); + DMA_TO_DEVICE); return ret; } @@ -3206,6 +4213,14 @@ ret = -ENOENT; goto out_unlock; } + + if (!peer->dp_setup_done) { + ath12k_warn(ab, "The peer %pM [%d] has not initialized its datapath\n", + peer->addr, peer_id); + ret = -ENOENT; + goto out_unlock; + } + rx_tid = &peer->rx_tid[tid]; if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || @@ -3221,7 +4236,7 @@ goto out_unlock; } - if (frag_no > __fls(rx_tid->rx_frag_bitmap)) + if (!rx_tid->rx_frag_bitmap || (frag_no > __fls(rx_tid->rx_frag_bitmap))) __skb_queue_tail(&rx_tid->rx_frags, msdu); else ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); @@ -3283,7 +4298,8 @@ static int ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, - bool drop, u32 cookie) + bool drop, u32 cookie, + struct list_head *list) { struct ath12k_base *ab = ar->ab; struct sk_buff *msdu; @@ -3302,7 +4318,7 @@ if (!desc_info) { desc_info = ath12k_dp_get_rx_desc(ab, cookie); if (!desc_info) { - ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); + ath12k_warn(ab, "Invalid cookie in manual desc retrieval cookie 0x%x", cookie); return -EINVAL; } } @@ -3312,9 +4328,7 @@ msdu = desc_info->skb; desc_info->skb = NULL; - spin_lock_bh(&ab->dp.rx_desc_lock); - list_move_tail(&desc_info->list, &ab->dp.rx_desc_free_list); - spin_unlock_bh(&ab->dp.rx_desc_lock); + list_add_tail(&desc_info->list, list); rxcb = ATH12K_SKB_RXCB(msdu); dma_unmap_single(ar->ab->dev, rxcb->paddr, @@ -3359,11 +4373,46 @@ return 0; } +static int ath12k_dp_h_msdu_buffer_type(struct ath12k_base *ab, + struct hal_reo_dest_ring *desc, + struct list_head *list) +{ + struct ath12k_rx_desc_info *desc_info; + struct sk_buff *msdu; + struct ath12k_skb_rxcb *rxcb; + u64 desc_va; + + ab->soc_stats.reo_excep_msdu_buf_type++; + + desc_va = ((u64)desc->buf_va_hi << 32 | desc->buf_va_lo); + desc_info = (struct ath12k_rx_desc_info *)(uintptr_t)desc_va; + if (!desc_info) { + ath12k_warn(ab, " rx exception, hw cookie conversion failed"); + return -EINVAL; + } + + if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) { + ath12k_warn(ab, " rx exception, magic check failed"); + return -EINVAL; + } + + msdu = desc_info->skb; + desc_info->skb = NULL; + list_add_tail(&desc_info->list, list); + rxcb = ATH12K_SKB_RXCB(msdu); + dma_unmap_single(ab->dev, rxcb->paddr, msdu->len + skb_tailroom(msdu), + DMA_FROM_DEVICE); + dev_kfree_skb_any(msdu); + + return 0; +} + int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, int budget) { u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; struct dp_link_desc_bank *link_desc_banks; + struct ath12k_base *src_ab; enum hal_rx_buf_return_buf_manager rbm; struct hal_rx_msdu_link *link_desc_va; int tot_n_bufs_reaped, quota, ret, i; @@ -3373,18 +4422,22 @@ u32 desc_bank, num_msdus; struct hal_srng *srng; struct ath12k_dp *dp; - int mac_id; - struct ath12k *ar; + struct ath12k *ar = NULL; dma_addr_t paddr; - bool is_frag; - bool drop = false; + bool is_frag, drop; + char buf[64] = {0}; + u8 hw_link_id, chip_id; + int num_buffs_reaped[ATH12K_MAX_SOCS] = { }; + struct list_head rx_desc_used_list[ATH12K_MAX_SOCS]; tot_n_bufs_reaped = 0; quota = budget; dp = &ab->dp; reo_except = &dp->reo_except_ring; - link_desc_banks = dp->link_desc_banks; + + for (i = 0; i < ATH12K_MAX_SOCS; i++) + INIT_LIST_HEAD(&rx_desc_used_list[i]); srng = &ab->hal.srng_list[reo_except->ring_id]; @@ -3398,20 +4451,61 @@ ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, &desc_bank); if (ret) { - ath12k_warn(ab, "failed to parse error reo desc %d\n", - ret); - continue; + scnprintf(buf, sizeof(buf), "failed to parse error reo desc %d\n", ret); + ath12k_err_dump(ab, buf, "rx err desc: ", reo_desc, + sizeof(*reo_desc), srng); + BUG_ON(1); } + + hw_link_id = u32_get_bits(reo_desc->info0, + HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); + + rcu_read_lock(); + if (hw_link_id < ATH12K_GROUP_MAX_RADIO) + ar = rcu_dereference(ab->ag->hw_links[hw_link_id]); + else + ar = NULL; + rcu_read_unlock(); + + if (!ar) { + ath12k_err(ab, "invalid src link id %d on chip id %d err process\n", + hw_link_id, ab->chip_id); + + ath12k_err_dump(ab, NULL, "rx err desc: ", reo_desc, + sizeof(*reo_desc), srng); + BUG_ON(1); + } + + src_ab = ar->ab; + chip_id = src_ab->chip_id; + + /* Below case is added to handle data packet from un-associated clients. + * As it is expected that AST lookup will fail for + * un-associated station's data packets. + */ + if (u32_get_bits(reo_desc->info0, HAL_REO_DEST_RING_INFO0_BUFFER_TYPE) == + HAL_REO_DEST_RING_BUFFER_TYPE_MSDU) { + if (!ath12k_dp_h_msdu_buffer_type(src_ab, reo_desc, + &rx_desc_used_list[chip_id])) { + num_buffs_reaped[chip_id]++; + tot_n_bufs_reaped++; + } + + goto end_loop; + } + + dp = &src_ab->dp; + link_desc_banks = dp->link_desc_banks; link_desc_va = link_desc_banks[desc_bank].vaddr + (paddr - link_desc_banks[desc_bank].paddr); ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, &rbm); - if (rbm != HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST && + if (rbm != dp->idle_link_rbm_id && rbm != HAL_RX_BUF_RBM_SW3_BM && - rbm != ab->hw_params->hal_params->rx_buf_rbm) { + rbm != src_ab->hw_params->hal_params->rx_buf_rbm) { ab->soc_stats.invalid_rbm++; ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); - ath12k_dp_rx_link_desc_return(ab, reo_desc, + ath12k_dp_rx_link_desc_return(src_ab, reo_desc, HAL_WBM_REL_BM_ACT_REL_MSDU); continue; } @@ -3421,25 +4515,31 @@ /* Process only rx fragments with one msdu per link desc below, and drop * msdu's indicated due to error reasons. + * Dynamic fragmentation not supported in Multi-link client, so drop. */ - if (!is_frag || num_msdus > 1) { + if (!is_frag || num_msdus > 1 || src_ab != ab) drop = true; + else + drop = false; + + if (drop) { /* Return the link desc back to wbm idle list */ - ath12k_dp_rx_link_desc_return(ab, reo_desc, + ath12k_dp_rx_link_desc_return(src_ab, reo_desc, HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); + + ar->wmm_stats.total_wmm_rx_drop[ar->wmm_stats.rx_type] += num_msdus; } for (i = 0; i < num_msdus; i++) { - mac_id = le32_get_bits(reo_desc->info0, - HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); - - ar = ab->pdevs[mac_id].ar; - if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, drop, - msdu_cookies[i])) + msdu_cookies[i], + &rx_desc_used_list[chip_id])) { + num_buffs_reaped[chip_id]++; tot_n_bufs_reaped++; } + } +end_loop: if (tot_n_bufs_reaped >= quota) { tot_n_bufs_reaped = quota; goto exit; @@ -3453,10 +4553,20 @@ spin_unlock_bh(&srng->lock); - rx_ring = &dp->rx_refill_buf_ring; + for (i = 0; i < ab->ag->num_chip; i++) { + if (!num_buffs_reaped[i]) + continue; - ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, tot_n_bufs_reaped, - ab->hw_params->hal_params->rx_buf_rbm, true); + src_ab = ab->ag->ab[i]; + if (!src_ab) + continue; + + rx_ring = &src_ab->dp.rx_refill_buf_ring; + + ath12k_dp_rx_bufs_replenish(src_ab, rx_ring, + &rx_desc_used_list[i], + num_buffs_reaped[i]); + } return tot_n_bufs_reaped; } @@ -3486,7 +4596,7 @@ } static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, - struct ieee80211_rx_status *status, + struct ath12k_dp_rx_info *rx_info, struct sk_buff_head *msdu_list) { struct ath12k_base *ab = ar->ab; @@ -3495,19 +4605,13 @@ u8 l3pad_bytes; struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; + bool fast_rx; + struct ath12k_link_sta *arsta = NULL; + struct ath12k_peer *peer = NULL; msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); peer_id = ath12k_dp_rx_h_peer_id(ab, desc); - spin_lock(&ab->base_lock); - if (!ath12k_peer_find_by_id(ab, peer_id)) { - spin_unlock(&ab->base_lock); - ath12k_dbg(ab, ATH12K_DBG_DATA, "invalid peer id received in wbm err pkt%d\n", - peer_id); - return -EINVAL; - } - spin_unlock(&ab->base_lock); - if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { /* First buffer will be freed by the caller, so deduct it's length */ msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); @@ -3549,9 +4653,19 @@ skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); } - ath12k_dp_rx_h_ppdu(ar, desc, status); - ath12k_dp_rx_h_mpdu(ar, msdu, desc, status); + ath12k_dp_rx_h_fetch_info(ab, desc, rx_info); + + if (rx_info->decap_type == DP_RX_DECAP_TYPE_NATIVE_WIFI && + ath12k_dp_rx_check_max_nwifi_hdr_len(ab, desc, msdu, + "Invalid len in Null queue\n")) { + WARN_ON_ONCE(1); + return -EINVAL; + } + + ath12k_dp_rx_h_ppdu(ar, rx_info); + fast_rx = false; + ath12k_dp_rx_h_mpdu(ar, msdu, desc, rx_info, &fast_rx); rxcb->tid = ath12k_dp_rx_h_tid(ab, desc); @@ -3559,21 +4673,31 @@ * rx with mac80211. Need not worry about cleaning up amsdu_list. */ + if (ath12k_debugfs_is_extd_rx_stats_enabled(ar)) { + peer_id = ath12k_dp_rx_h_peer_id(ar->ab, desc); + spin_lock_bh(&ar->ab->base_lock); + if (peer_id) + peer = ath12k_peer_find_by_id(ar->ab, rxcb->peer_id); + if (peer && peer->sta) + arsta = ath12k_peer_get_link_sta(ar->ab, peer); + spin_unlock_bh(&ar->ab->base_lock); + if (arsta) + atomic_inc(&arsta->drv_rx_pkts.pkts_frm_hw); + } + return 0; } static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, - struct ieee80211_rx_status *status, + struct ath12k_dp_rx_info *rx_info, struct sk_buff_head *msdu_list) { struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); bool drop = false; - ar->ab->soc_stats.reo_error[rxcb->err_code]++; - switch (rxcb->err_code) { case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: - if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) + if (ath12k_dp_rx_h_null_q_desc(ar, msdu, rx_info, msdu_list)) drop = true; break; case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: @@ -3590,11 +4714,16 @@ break; } + if (drop) + ar->ab->soc_stats.reo_error_drop[rxcb->err_code]++; + else + ar->ab->soc_stats.reo_error[rxcb->err_code]++; + return drop; } -static void ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, - struct ieee80211_rx_status *status) +static bool ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, + struct ath12k_dp_rx_info *rx_info) { struct ath12k_base *ab = ar->ab; u16 msdu_len; @@ -3608,20 +4737,94 @@ l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); + + if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) { + ath12k_warn(ab, "invalid msdu len in tkip mirc err %u\n", msdu_len); + ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", desc, + sizeof(struct hal_rx_desc)); + return true; + } + skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); - ath12k_dp_rx_h_ppdu(ar, desc, status); + if (rx_info->decap_type == DP_RX_DECAP_TYPE_NATIVE_WIFI && + ath12k_dp_rx_check_max_nwifi_hdr_len(ab, desc, msdu, + "Invalid len in tkip mic err\n")) { + WARN_ON_ONCE(1); + return true; + } + + ath12k_dp_rx_h_ppdu(ar, rx_info); - status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | + rx_info->rx_status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | RX_FLAG_DECRYPTED); ath12k_dp_rx_h_undecap(ar, msdu, desc, - HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); + HAL_ENCRYPT_TYPE_TKIP_MIC, rx_info->rx_status, false); + return false; +} + +static bool ath12k_dp_rx_h_4addr_null_frame_handler(struct ath12k *ar, + struct sk_buff *msdu, + struct ath12k_dp_rx_info *rx_info) +{ + struct ath12k_base *ab = ar->ab; + u16 msdu_len, peer_id; + u8 l3pad_bytes; + struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); + struct hal_rx_desc *rx_desc = (struct hal_rx_desc*)msdu->data; + u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; + struct ieee80211_hdr *hdr; + size_t hdr_len; + struct ath12k_dp_rx_rfc1042_hdr *llc; + bool drop = false; + bool fast_rx = false; + + msdu_len = ath12k_dp_rx_h_msdu_len(ab, rx_desc); + peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); + + spin_lock_bh(&ab->base_lock); + if(!ath12k_peer_find_by_id(ab, peer_id)) { + spin_unlock_bh(&ab->base_lock); + ath12k_dbg(ab, ATH12K_DBG_DATA, "invalid peer id received in wbm err pkt%d\n", + peer_id); + return -EINVAL; + } + spin_unlock_bh(&ab->base_lock); + l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, rx_desc); + + if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) + return -EINVAL; + + skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); + skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); + + if (rx_info->decap_type == DP_RX_DECAP_TYPE_NATIVE_WIFI && + ath12k_dp_rx_check_max_nwifi_hdr_len(ab, rx_desc, msdu, + "Invalid len in 4addr Null frame\n")) { + WARN_ON_ONCE(1); + return true; } + ath12k_dp_rx_h_ppdu(ar, rx_info); + + ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_info, &fast_rx); + + rxcb->tid = ath12k_dp_rx_h_tid(ab, rx_desc); + + hdr = (struct ieee80211_hdr *)msdu->data; + hdr_len = ieee80211_hdrlen(hdr->frame_control); + llc = (struct ath12k_dp_rx_rfc1042_hdr *)(msdu->data + hdr_len); + + if (!(llc->snap_type == cpu_to_be16(ETH_P_PAE) || + ieee80211_is_qos_nullfunc(hdr->frame_control))) + drop = true; + + return drop; +} static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, - struct ieee80211_rx_status *status) + struct ath12k_dp_rx_info *rx_info) { struct ath12k_base *ab = ar->ab; struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); @@ -3629,14 +4832,19 @@ bool drop = false; u32 err_bitmap; - ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; - switch (rxcb->err_code) { + case HAL_REO_ENTR_RING_RXDMA_ECODE_UNAUTH_WDS_ERR: + ath12k_dp_rx_h_fetch_info(ab, rx_desc, rx_info); + + drop = ath12k_dp_rx_h_4addr_null_frame_handler(ar, msdu, rx_info); + break; case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { - ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status); + ath12k_dp_rx_h_fetch_info(ab, rx_desc, rx_info); + + drop = ath12k_dp_rx_h_tkip_mic_err(ar, msdu, rx_info); break; } fallthrough; @@ -3648,6 +4856,11 @@ break; } + if (drop) + ar->ab->soc_stats.rxdma_error_drop[rxcb->err_code]++; + else + ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; + return drop; } @@ -3658,14 +4871,18 @@ { struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); struct ieee80211_rx_status rxs = {0}; + struct ath12k_dp_rx_info rx_info; bool drop = true; + rx_info.filled = 0; + rx_info.rx_status = &rxs; + switch (rxcb->err_rel_src) { case HAL_WBM_REL_SRC_MODULE_REO: - drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); + drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rx_info, msdu_list); break; case HAL_WBM_REL_SRC_MODULE_RXDMA: - drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs); + drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rx_info); break; default: /* msdu will get freed */ @@ -3677,31 +4894,38 @@ return; } - ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); + ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_info); } int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, struct napi_struct *napi, int budget) { struct ath12k *ar; + struct ath12k_base *src_ab; struct ath12k_dp *dp = &ab->dp; struct dp_rxdma_ring *rx_ring; struct hal_rx_wbm_rel_info err_info; struct hal_srng *srng; struct sk_buff *msdu; - struct sk_buff_head msdu_list[MAX_RADIOS]; + struct sk_buff_head msdu_list, scatter_msdu_list; struct ath12k_skb_rxcb *rxcb; void *rx_desc; - int mac_id; - int num_buffs_reaped = 0; + int i, num_buffs_reaped[ATH12K_MAX_SOCS] = { 0 }; struct ath12k_rx_desc_info *desc_info; - int ret, i; + struct ath12k_soc_dp_stats *soc_stats = &ab->soc_stats; + int total_num_buffs_reaped = 0; + int ret; + u8 hw_link_id, chip_id; + char buf[64] = {0}; + struct list_head rx_desc_used_list[ATH12K_MAX_SOCS]; + + __skb_queue_head_init(&msdu_list); + __skb_queue_head_init(&scatter_msdu_list); - for (i = 0; i < ab->num_radios; i++) - __skb_queue_head_init(&msdu_list[i]); + for (i = 0; i < ATH12K_MAX_SOCS; i++) + INIT_LIST_HEAD(&rx_desc_used_list[i]); srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; - rx_ring = &dp->rx_refill_buf_ring; spin_lock_bh(&srng->lock); @@ -3714,10 +4938,10 @@ ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); if (ret) { - ath12k_warn(ab, - "failed to parse rx error in wbm_rel ring desc %d\n", - ret); - continue; + scnprintf(buf, sizeof(buf), "failed to parse rx error in wbm_rel ring desc %d\n", ret); + ath12k_err_dump(ab, buf, "wbm err desc: ", rx_desc, + sizeof(struct hal_wbm_release_ring), srng); + BUG_ON(1); } desc_info = (struct ath12k_rx_desc_info *)err_info.rx_desc; @@ -3726,32 +4950,29 @@ if (!desc_info) { desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); if (!desc_info) { - ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); + ath12k_warn(ab, "Invalid cookie in manual desc retrieval cookie 0x%x", err_info.cookie); continue; } } - /* FIXME: Extract mac id correctly. Since descs are not tied - * to mac, we can extract from vdev id in ring desc. - */ - mac_id = 0; - if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); msdu = desc_info->skb; desc_info->skb = NULL; + src_ab = ab->ag->ab[desc_info->chip_id]; + dp = &src_ab->dp; + chip_id = src_ab->chip_id; - spin_lock_bh(&dp->rx_desc_lock); - list_move_tail(&desc_info->list, &dp->rx_desc_free_list); - spin_unlock_bh(&dp->rx_desc_lock); + list_add_tail(&desc_info->list, &rx_desc_used_list[chip_id]); rxcb = ATH12K_SKB_RXCB(msdu); - dma_unmap_single(ab->dev, rxcb->paddr, + dma_unmap_single(src_ab->dev, rxcb->paddr, msdu->len + skb_tailroom(msdu), DMA_FROM_DEVICE); - num_buffs_reaped++; + num_buffs_reaped[chip_id]++; + total_num_buffs_reaped++; if (!err_info.continuation) budget--; @@ -3764,44 +4985,101 @@ rxcb->err_rel_src = err_info.err_rel_src; rxcb->err_code = err_info.err_code; - rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; - __skb_queue_tail(&msdu_list[mac_id], msdu); - rxcb->is_first_msdu = err_info.first_msdu; rxcb->is_last_msdu = err_info.last_msdu; rxcb->is_continuation = err_info.continuation; + rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; + + if (!err_info.continuation) { + hw_link_id = ath12k_dp_rx_get_msdu_src_link(src_ab, (struct hal_rx_desc *)msdu->data); + if (hw_link_id >= ATH12K_GROUP_MAX_RADIO) { + if (ath12k_debug_critical) { + ath12k_err(ab, "WBM Err: invalid hw link id %d\n", + hw_link_id); + ath12k_err_dump(ab, NULL, "WBM err desc: ", rx_desc, + sizeof(struct hal_wbm_release_ring_cc_rx), srng); + ath12k_err_dump(ab, NULL, "WBM Rx TLV: ", msdu->data, + sizeof(struct hal_rx_desc), srng); + dev_kfree_skb_any(msdu); + BUG_ON(1); + } else { + dev_kfree_skb_any(msdu); + } + continue; + } + + if (!skb_queue_empty(&scatter_msdu_list)) { + __skb_queue_tail(&scatter_msdu_list, msdu); + + skb_queue_walk(&scatter_msdu_list, msdu) { + rxcb = ATH12K_SKB_RXCB(msdu); + rxcb->hw_link_id = hw_link_id; + } + + skb_queue_splice_tail_init(&scatter_msdu_list, &msdu_list); + } else { + rxcb->hw_link_id = hw_link_id; + __skb_queue_tail(&msdu_list, msdu); + } + } else { + __skb_queue_tail(&scatter_msdu_list, msdu); + } } ath12k_hal_srng_access_end(ab, srng); spin_unlock_bh(&srng->lock); - if (!num_buffs_reaped) + if (!total_num_buffs_reaped) goto done; - ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_buffs_reaped, - ab->hw_params->hal_params->rx_buf_rbm, true); + for (i = 0; i < ab->ag->num_chip; i++) { + if (!num_buffs_reaped[i]) + continue; + + src_ab = ab->ag->ab[i]; + if (!src_ab) + continue; + + rx_ring = &src_ab->dp.rx_refill_buf_ring; + + ath12k_dp_rx_bufs_replenish(src_ab, rx_ring, + &rx_desc_used_list[i], + num_buffs_reaped[i]); + } rcu_read_lock(); - for (i = 0; i < ab->num_radios; i++) { - if (!rcu_dereference(ab->pdevs_active[i])) { - __skb_queue_purge(&msdu_list[i]); + while ((msdu = __skb_dequeue(&msdu_list)) != NULL) { + + rxcb = ATH12K_SKB_RXCB(msdu); + hw_link_id = rxcb->hw_link_id; + + ar = rcu_dereference(ab->ag->hw_links[hw_link_id]); + if (!ar) { + dev_kfree_skb_any(msdu); + ath12k_warn(ab, "WBM Rx: invalid pdev for hw link id %d\n", + hw_link_id); continue; } - ar = ab->pdevs[i].ar; + if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { + dev_kfree_skb_any(msdu); + continue; + } if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { - __skb_queue_purge(&msdu_list[i]); + dev_kfree_skb_any(msdu); continue; } - while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) - ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); + if (rxcb->err_rel_src < HAL_WBM_REL_SRC_MODULE_MAX) + soc_stats->rx_wbm_rel_source[rxcb->err_rel_src][ar->ab->chip_id]++; + + ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list); } rcu_read_unlock(); done: - return num_buffs_reaped; + return total_num_buffs_reaped; } void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) @@ -3899,6 +5177,8 @@ ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); + + if (ab->hw_params->supports_tx_monitor) ath12k_dp_srng_cleanup(ab, &dp->tx_mon_buf_ring.refill_buf_ring); ath12k_dp_rxdma_buf_free(ab); @@ -3934,10 +5214,18 @@ tlv_filter.rx_msdu_end_offset = ab->hw_params->hal_ops->rx_desc_get_msdu_end_offset(); - /* TODO: Selectively subscribe to required qwords within msdu_end - * and mpdu_start and setup the mask in below msg - * and modify the rx_desc struct - */ + if (ab->hw_params->compact_rx_tlv) { + if (ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start) + tlv_filter.rx_mpdu_start_wmask = + ab->hw_params->hal_ops->rxdma_ring_wmask_rx_mpdu_start(); + if (ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end) + tlv_filter.rx_msdu_end_wmask = + ab->hw_params->hal_ops->rxdma_ring_wmask_rx_msdu_end(); + ath12k_dbg(ab, ATH12K_DBG_DATA, + "Configuring compact tlv masks rx_mpdu_start_wmask 0x%x rx_msdu_end_wmask 0x%x\n", + tlv_filter.rx_mpdu_start_wmask, tlv_filter.rx_msdu_end_wmask); + } + ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, HAL_RXDMA_BUF, DP_RXDMA_REFILL_RING_SIZE, @@ -3988,6 +5276,55 @@ return ret; } +int +ath12k_dp_rx_htt_rxdma_rxole_ppe_cfg_set(struct ath12k_base *ab, + struct ath12k_dp_htt_rxdma_ppe_cfg_param *param) +{ + struct htt_h2t_msg_type_rxdma_rxole_ppe_cfg *cmd; + struct ath12k_dp *dp = &ab->dp; + struct sk_buff *skb; + int len = sizeof(*cmd), ret, val; + + skb = ath12k_htc_alloc_skb(ab, len); + if (!skb) + return -ENOMEM; + + skb_put(skb, len); + + cmd = (struct htt_h2t_msg_type_rxdma_rxole_ppe_cfg *)skb->data; + memset(cmd, 0, sizeof(*cmd)); + + cmd->info0 = + u32_encode_bits(HTT_H2T_MSG_TYPE_RXDMA_RXOLE_PPE_CFG, + HTT_H2T_RXOLE_PPE_CFG_MSG_TYPE) | + u32_encode_bits(param->override, HTT_H2T_RXOLE_PPE_CFG_OVERRIDE) | + u32_encode_bits(param->reo_dst_ind, + HTT_H2T_RXOLE_PPE_CFG_REO_DST_IND) | + u32_encode_bits(param->multi_buffer_msdu_override_en, + HTT_H2T_RXOLE_PPE_CFG_MULTI_BUF_MSDU_OVRD_EN) | + u32_encode_bits(param->intra_bss_override, + HTT_H2T_RXOLE_PPE_CFG_INTRA_BUS_OVRD) | + u32_encode_bits(param->decap_raw_override, + HTT_H2T_RXOLE_PPE_CFG_DECAP_RAW_OVRD) | + u32_encode_bits(param->decap_nwifi_override, + HTT_H2T_RXOLE_PPE_CFG_NWIFI_OVRD) | + u32_encode_bits(param->ip_frag_override, + HTT_H2T_RXOLE_PPE_CFG_IP_FRAG_OVRD); + + val = cmd->info0; + ret = ath12k_htc_send(&ab->htc, dp->eid, skb); + if(ret) { + ath12k_warn(ab, "failed to send htt type H2T rx ole ppe config request: %d", + ret); + dev_kfree_skb_any(skb); + return ret; + } + + ath12k_dbg(ab, ATH12K_DBG_PPE, "RXOLE ppe config request sent val 0x%x\n", val); + + return 0; +} + int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) { struct ath12k_dp *dp = &ab->dp; @@ -4037,6 +5374,7 @@ return ret; } + if (ab->hw_params->supports_tx_monitor) { ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id; ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_TX_MONITOR_BUF); @@ -4046,6 +5384,7 @@ return ret; } } + } ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); if (ret) { @@ -4067,8 +5406,10 @@ idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); + if (ab->hw_params->supports_tx_monitor) { idr_init(&dp->tx_mon_buf_ring.bufs_idr); spin_lock_init(&dp->tx_mon_buf_ring.idr_lock); + } ret = ath12k_dp_srng_setup(ab, &dp->rx_refill_buf_ring.refill_buf_ring, @@ -4113,6 +5454,7 @@ return ret; } + if (ab->hw_params->supports_tx_monitor) { ret = ath12k_dp_srng_setup(ab, &dp->tx_mon_buf_ring.refill_buf_ring, HAL_TX_MONITOR_BUF, 0, 0, @@ -4122,6 +5464,7 @@ return ret; } } + } ret = ath12k_dp_rxdma_buf_setup(ab); if (ret) { @@ -4161,6 +5504,7 @@ return ret; } + if (ab->hw_params->supports_tx_monitor) { ring_id = dp->tx_mon_dst_ring[i].ring_id; ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, mac_id + i, @@ -4172,14 +5516,39 @@ return ret; } } + } out: return 0; } +static int ath12k_dp_rx_pdev_mon_status_detach(struct ath12k *ar) +{ + struct ath12k_pdev_dp *dp = &ar->dp; + struct ath12k_mon_data *pmon = dp->mon_data; + + if (!pmon) { + ath12k_err(ar->ab, "pmon is NULL\n"); + return -EINVAL; + } + + vfree(pmon); + dp->mon_data = NULL; + + return 0; +} + static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) { struct ath12k_pdev_dp *dp = &ar->dp; - struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; + struct ath12k_mon_data *pmon; + + pmon = vzalloc(sizeof(*pmon)); + if (!pmon) { + ath12k_warn(ar->ab, "pmon allocation failed \n"); + return -ENOMEM; + } + + dp->mon_data = pmon; skb_queue_head_init(&pmon->rx_status_q); @@ -4193,7 +5562,6 @@ int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) { struct ath12k_pdev_dp *dp = &ar->dp; - struct ath12k_mon_data *pmon = &dp->mon_data; int ret = 0; ret = ath12k_dp_rx_pdev_mon_status_attach(ar); @@ -4208,13 +5576,23 @@ if (!ar->ab->hw_params->rxdma1_enable) return 0; - pmon->mon_last_linkdesc_paddr = 0; - pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; - spin_lock_init(&pmon->mon_lock); + dp->mon_data->mon_last_linkdesc_paddr = 0; + dp->mon_data->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; + spin_lock_init(&dp->mon_data->mon_lock); return 0; } +void ath12k_dp_rx_pdev_mon_detach(struct ath12k_base *ab, const int pdev_idx) +{ + struct ath12k *ar = ab->pdevs[pdev_idx].ar; + int ret; + + ret = ath12k_dp_rx_pdev_mon_status_detach(ar); + if (ret) + ath12k_warn(ar->ab, "pdev_mon_status_detach() failed %d\n", ret); +} + int ath12k_dp_rx_pktlog_start(struct ath12k_base *ab) { /* start reap timer */ @@ -4240,3 +5618,4 @@ return 0; } + diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp_rx.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_rx.h --- linux-6.4/drivers/net/wireless/ath/ath12k/dp_rx.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_rx.h 2024-03-18 14:40:14.851741333 +0100 @@ -9,14 +9,47 @@ #include "core.h" #include "rx_desc.h" #include "debug.h" +#include "crypto/hash.h" #define DP_MAX_NWIFI_HDR_LEN 30 + +/* different supported pkt types for routing */ +enum ath12k_routing_pkt_type { + ATH12K_PKT_TYPE_ARP_IPV4, + ATH12K_PKT_TYPE_NS_IPV6, + ATH12K_PKT_TYPE_IGMP_IPV4, + ATH12K_PKT_TYPE_MLD_IPV6, + ATH12K_PKT_TYPE_DHCP_IPV4, + ATH12K_PKT_TYPE_DHCP_IPV6, + ATH12K_PKT_TYPE_DNS_TCP_IPV4, + ATH12K_PKT_TYPE_DNS_TCP_IPV6, + ATH12K_PKT_TYPE_DNS_UDP_IPV4, + ATH12K_PKT_TYPE_DNS_UDP_IPV6, + ATH12K_PKT_TYPE_ICMP_IPV4, + ATH12K_PKT_TYPE_ICMP_IPV6, + ATH12K_PKT_TYPE_TCP_IPV4, + ATH12K_PKT_TYPE_TCP_IPV6, + ATH12K_PKT_TYPE_UDP_IPV4, + ATH12K_PKT_TYPE_UDP_IPV6, + ATH12K_PKT_TYPE_IPV4, + ATH12K_PKT_TYPE_IPV6, + ATH12K_PKT_TYPE_EAP, + ATH12K_PKT_TYPE_MAX +}; + +#define ATH12K_RX_PROTOCOL_TAG_START_OFFSET 128 +#define ATH12K_ROUTE_WBM_RELEASE(ab) \ + ((ab)->hw_params->route_wbm_release) +#define ATH12K_ROUTE_EAP_METADATA (ATH12K_RX_PROTOCOL_TAG_START_OFFSET + ATH12K_PKT_TYPE_EAP) +#define ATH12K_ROUTE_ARP_METADATA (ATH12K_RX_PROTOCOL_TAG_START_OFFSET + ATH12K_PKT_TYPE_ARP_IPV4) + struct ath12k_dp_rx_tid { u8 tid; u32 *vaddr; dma_addr_t paddr; u32 size; + u32 pending_desc_size; u32 ba_win_sz; bool active; @@ -39,6 +72,16 @@ unsigned long ts; }; +struct dp_reo_update_rx_queue_elem { + struct list_head list; + struct ath12k_dp_rx_tid data; + int peer_id; + u8 tid; + bool reo_cmd_update_rx_queue_resend_flag; + bool is_ml_peer; + u16 ml_peer_id; +}; + struct ath12k_dp_rx_reo_cmd { struct list_head list; struct ath12k_dp_rx_tid data; @@ -65,6 +108,45 @@ __be16 snap_type; } __packed; +enum ath12k_dp_rx_info_type { + ATH12K_RX_INFO_DECAP_TYPE, + ATH12K_RX_INFO_PKT_TYPE, + ATH12K_RX_INFO_SGI, + ATH12K_RX_INFO_RATE_MCS, + ATH12K_RX_INFO_BW, + ATH12K_RX_INFO_NSS, + ATH12K_RX_INFO_PHY_META_DATA, + ATH12K_RX_INFO_ADDR2, + + /* keep last */ + ATH12K_RX_INFO_MAX +}; + +struct ath12k_dp_rx_info { + u64 filled; + u8 decap_type; + u8 pkt_type; + u8 sgi; + u8 rate_mcs; + u8 bw; + u8 nss; + u32 phy_meta_data; + u8 addr2[ETH_ALEN]; + bool ip_csum_fail; + bool l4_csum_fail; + u8 ip_is_valid; + u8 decap; + u16 peer_id; + bool is_mcbc; + u8 l3_pad_bytes; + u16 msdu_len; + u8 tid; + bool msdu_done; + bool is_first_msdu; + bool is_last_msdu; + struct ieee80211_rx_status *rx_status; +}; + static inline u32 ath12k_he_gi_to_nl80211_he_gi(u8 sgi) { u32 ret = 0; @@ -84,20 +166,40 @@ return ret; } +static inline u32 ath12k_eht_gi_to_nl80211_eht_gi(u8 sgi) +{ + u32 ret = 0; + + switch (sgi) { + case RX_MSDU_START_SGI_0_8_US: + ret = NL80211_RATE_INFO_EHT_GI_0_8; + break; + case RX_MSDU_START_SGI_1_6_US: + ret = NL80211_RATE_INFO_EHT_GI_1_6; + break; + case RX_MSDU_START_SGI_3_2_US: + ret = NL80211_RATE_INFO_EHT_GI_3_2; + break; + } + + return ret; +} + int ath12k_dp_rx_ampdu_start(struct ath12k *ar, - struct ieee80211_ampdu_params *params); + struct ieee80211_ampdu_params *params, + u8 link_id); int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, - struct ieee80211_ampdu_params *params); -int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif, + struct ieee80211_ampdu_params *params, + u8 link_id); +int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_link_vif *arvif, const u8 *peer_addr, enum set_key_cmd key_cmd, struct ieee80211_key_conf *key); void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer); void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, struct ath12k_peer *peer, u8 tid); -int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, - u8 tid, u32 ba_win_sz, u16 ssn, - enum hal_pn_type pn_type); +int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, u8 tid, u32 ba_win_sz, u16 ssn, + enum hal_pn_type pn_type, struct ath12k_peer *peer); void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, struct sk_buff *skb); int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab); @@ -116,30 +218,43 @@ int ath12k_dp_rx_process(struct ath12k_base *ab, int mac_id, struct napi_struct *napi, int budget); -int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, int mac_id, +int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, struct dp_rxdma_ring *rx_ring, - int req_entries, - enum hal_rx_buf_return_buf_manager mgr, - bool hw_cc); + struct list_head *used_list, + int req_entries); int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar); -int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id); - +void ath12k_dp_rx_pdev_mon_detach(struct ath12k_base *ab, const int pdev_idx); +int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, struct ath12k_peer *peer, + struct crypto_shash *tfm); int ath12k_dp_rx_pktlog_start(struct ath12k_base *ab); int ath12k_dp_rx_pktlog_stop(struct ath12k_base *ab, bool stop_timer); u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, struct hal_rx_desc *desc); struct ath12k_peer * -ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu); +ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu, + struct ath12k_dp_rx_info *rx_info); u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, struct hal_rx_desc *desc); u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, struct hal_rx_desc *desc); -void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc, - struct ieee80211_rx_status *rx_status); -struct ath12k_peer * -ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu); +void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct ath12k_dp_rx_info *rx_info); int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab); int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab); - +int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, + int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, + const void *ptr, void *data), + void *data); +int +ath12k_dp_rx_htt_rxdma_rxole_ppe_cfg_set(struct ath12k_base *ab, + struct ath12k_dp_htt_rxdma_ppe_cfg_param *param); +int ath12k_dp_rx_pkt_type_filter(struct ath12k *ar, + enum ath12k_routing_pkt_type pkt_type, + u32 meta_data); +void ath12k_dp_tid_cleanup(struct ath12k_base *ab); +void ath12k_dp_peer_tid_setup(struct ath12k_base *ab); +void ath12k_dp_peer_reo_tid_setup(struct ath12k_base *ab, struct ath12k_link_sta *arsta); +void ath12k_dp_tid_setup(void *data, struct ieee80211_sta *sta); +void ath12k_dp_reset_rx_reo_tid_q(void *vaddr, u32 ba_window_size, + u8 tid); #endif /* ATH12K_DP_RX_H */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp_tx.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_tx.c --- linux-6.4/drivers/net/wireless/ath/ath12k/dp_tx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_tx.c 2024-04-19 16:04:28.953735667 +0200 @@ -7,15 +7,52 @@ #include "core.h" #include "dp_tx.h" #include "debug.h" +#include "debugfs_sta.h" #include "hw.h" +#include "peer.h" +#include "ppe.h" +#include +#include +#ifdef CONFIG_ATH12K_SAWF +static inline u32 ath12k_sawf_get_tcl_metadata_update(u32 sk_buff_mark) +{ + u32 tcl_metadata = 0; + u32 svc_id = u32_get_bits(sk_buff_mark, SAWF_SERVICE_CLASS_ID); + + tcl_metadata = u32_encode_bits(HTT_TCL_META_DATA_TYPE_SVC_ID_BASED, + HTT_TCL_META_DATA_TYPE_MISSION) | + u32_encode_bits(1, HTT_TCL_META_DATA_SAWF_TID_OVERRIDE) | + u32_encode_bits(svc_id - 1, HTT_TCL_META_DATA_SAWF_SVC_ID); + return tcl_metadata; +} + +static inline u32 ath12k_sawf_get_tcl_cmd_info3_update(u32 msduq_id) +{ + u32 tid, flow_override, who_classify_info_sel, update = 0; + + tid = u32_get_bits(msduq_id, TID_FROM_Q_ID); + flow_override = u32_get_bits(msduq_id, FLOW_OVERRIDE_FROM_Q_ID); + who_classify_info_sel = u32_get_bits(msduq_id, WHO_CLASSIFY_INFO_FROM_Q_ID); + + update = u32_encode_bits(tid, HAL_TCL_DATA_CMD_INFO3_TID) | + u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE) | + u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE_EN) | + u32_encode_bits(who_classify_info_sel, + HAL_TCL_DATA_CMD_INFO3_CLASSIFY_INFO_SEL) | + u32_encode_bits(flow_override, + HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE); + + return update; +} + +#endif /* CONFIG_ATH12K_SAWF */ static enum hal_tcl_encap_type -ath12k_dp_tx_get_encap_type(struct ath12k_vif *arvif, struct sk_buff *skb) +ath12k_dp_tx_get_encap_type(struct ath12k_base *ab, struct sk_buff *skb) { struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); - struct ath12k_base *ab = arvif->ar->ab; - if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) + if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->ag->dev_flags)) return HAL_TCL_ENCAP_TYPE_RAW; if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) @@ -41,19 +78,6 @@ hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); } -static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) -{ - struct ieee80211_hdr *hdr = (void *)skb->data; - struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); - - if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) - return skb->priority & IEEE80211_QOS_CTL_TID_MASK; - else if (!ieee80211_is_data_qos(hdr->frame_control)) - return HAL_DESC_REO_NON_QOS_TID; - else - return skb->priority & IEEE80211_QOS_CTL_TID_MASK; -} - enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) { switch (cipher) { @@ -76,31 +100,104 @@ } } +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#define ATH12K_PPEDS_HOTLIST_LEN_MAX 1024 +struct sk_buff * +ath12k_dp_ppeds_tx_release_desc_nolock(struct ath12k_dp *dp, + struct ath12k_ppeds_tx_desc_info *tx_desc, + u8 ring_id) +{ + struct sk_buff *skb = NULL; + + lockdep_assert_held(&dp->ppeds_tx_desc_lock[ATH12K_PPEDS_DEFAULT_POOL_ID]); + if (dp->ppeds_tx_desc_reuse_list_len[ring_id] < ATH12K_PPEDS_HOTLIST_LEN_MAX && + tx_desc->skb) { + list_move_tail(&tx_desc->list, &dp->ppeds_tx_desc_reuse_list[ring_id]); + dp->ppeds_tx_desc_reuse_list_len[ring_id]++; + } else { + skb = tx_desc->skb; + tx_desc->skb = NULL; + list_move_tail(&tx_desc->list, &dp->ppeds_tx_desc_free_list[ring_id]); + } + + return skb; +} + +struct ath12k_ppeds_tx_desc_info * +ath12k_dp_ppeds_tx_assign_desc_nolock(struct ath12k_dp *dp, + u8 ring_id) +{ + struct ath12k_ppeds_tx_desc_info *desc, *next; + + lockdep_assert_held(&dp->ppeds_tx_desc_lock[ATH12K_PPEDS_DEFAULT_POOL_ID]); + /* first try to fetch descriptor from hotlist if not use free list */ + desc = list_first_entry_or_null(&dp->ppeds_tx_desc_reuse_list[ring_id], + struct ath12k_ppeds_tx_desc_info, + list); + if (desc) { + list_move_tail(&desc->list, &dp->ppeds_tx_desc_used_list[ring_id]); + dp->ppeds_tx_desc_reuse_list_len[ring_id]--; + /* Prefetch next hotlist descriptor */ + if (dp->ppeds_tx_desc_reuse_list_len[ring_id]) + next = list_first_entry_or_null(&dp->ppeds_tx_desc_reuse_list[ring_id], + struct ath12k_ppeds_tx_desc_info, + list); + else + next = list_first_entry_or_null(&dp->ppeds_tx_desc_free_list[ring_id], + struct ath12k_ppeds_tx_desc_info, + list); + prefetch(next); + + return desc; + } + + /* Fetch desc from Freelist if hotlist is empty */ + desc = list_first_entry_or_null(&dp->ppeds_tx_desc_free_list[ring_id], + struct ath12k_ppeds_tx_desc_info, + list); + if (unlikely(!desc)) { + ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); + return NULL; + } + + list_move_tail(&desc->list, &dp->ppeds_tx_desc_used_list[ring_id]); + + return desc; +} + +#endif + static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, struct ath12k_tx_desc_info *tx_desc, - u8 pool_id) + u8 ring_id) { - spin_lock_bh(&dp->tx_desc_lock[pool_id]); - list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); - spin_unlock_bh(&dp->tx_desc_lock[pool_id]); + tx_desc->skb = NULL; + tx_desc->skb_ext_desc = NULL; + spin_lock_bh(&dp->tx_desc_lock[ring_id]); + tx_desc->in_use = false; + list_add_tail(&tx_desc->list, &dp->tx_desc_free_list[ring_id]); + spin_unlock_bh(&dp->tx_desc_lock[ring_id]); } -static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, +static inline +struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, u8 pool_id) { - struct ath12k_tx_desc_info *desc; + struct ath12k_tx_desc_info *desc = NULL; spin_lock_bh(&dp->tx_desc_lock[pool_id]); desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], struct ath12k_tx_desc_info, list); if (!desc) { + ath12k_dbg(dp->ab, ATH12K_DBG_DP_TX, "failed to allocate data Tx desc\n"); spin_unlock_bh(&dp->tx_desc_lock[pool_id]); - ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); return NULL; } - list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); + prefetch(desc); + list_del(&desc->list); + desc->in_use = true; spin_unlock_bh(&dp->tx_desc_lock[pool_id]); return desc; @@ -118,21 +215,222 @@ le32_encode_bits(ti->data_len, HAL_TX_MSDU_EXT_INFO1_BUF_LEN); - tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | + tcl_ext_cmd->info1 |= le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | le32_encode_bits(ti->encap_type, HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | le32_encode_bits(ti->encrypt_type, HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); } -int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif, - struct sk_buff *skb) +#define HTT_META_DATA_ALIGNMENT 0x8 + +static void *ath12k_dp_metadata_align_skb(struct sk_buff *skb, u8 tail_len) +{ + struct sk_buff *tail; + void *metadata; + + if (unlikely(skb_cow_data(skb, tail_len, &tail) < 0)) + return NULL; + + metadata = pskb_put(skb, tail, tail_len); + memset(metadata, 0, tail_len); + return metadata; +} + +/* Preparing HTT Metadata when utilized with ext MSDU */ +static int ath12k_dp_prepare_htt_metadata(struct sk_buff *skb) +{ + struct htt_tx_msdu_desc_ext *desc_ext; + void *metadata; + u8 htt_desc_size; + /* Size rounded of multiple of 8 bytes */ + u8 htt_desc_size_aligned; + + + htt_desc_size = sizeof(struct htt_tx_msdu_desc_ext); + htt_desc_size_aligned = ALIGN(htt_desc_size, HTT_META_DATA_ALIGNMENT); + + metadata = ath12k_dp_metadata_align_skb(skb, htt_desc_size_aligned); + if (!metadata) + return -ENOMEM; + + desc_ext = (struct htt_tx_msdu_desc_ext *)metadata; + desc_ext->valid_encrypt_type = 1; + desc_ext->encrypt_type = HAL_ENCRYPT_TYPE_WEP_40; + desc_ext->host_tx_desc_pool = 1; + + return 0; +} + + +int ath12k_dp_tx_direct(struct ath12k_link_vif *arvif, struct sk_buff *skb) { + struct ath12k *ar = arvif->ar; + struct ath12k_base *ab = arvif->ab; + struct ath12k_dp *dp = arvif->dp; + struct ath12k_tx_desc_info *tx_desc = NULL; + struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); + struct hal_srng *tcl_ring; + struct dp_tx_ring *tx_ring; + struct device *dev = arvif->dev; + void *hal_tcl_desc; + struct hal_tcl_data_cmd tcl_desc; + u8 hal_ring_id, ring_id; +#ifdef CONFIG_ATH12K_SAWF + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + struct ath12k_peer *peer; +#endif + dma_addr_t paddr; + int ret; +#ifdef CONFIG_MAC80211_SFE_SUPPORT + int len = skb->fast_xmit ? 256 : skb->len; +#elif defined(CONFIG_IP_FFN) + int len = skb->ffn_ff_done ? skb->ffn_ff_dirty_len : skb->len; +#else + int len = skb->len; +#endif + + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) + return -ESHUTDOWN; + + ring_id = smp_processor_id(); + + tx_ring = &dp->tx_ring[ring_id]; + + tx_desc = ath12k_dp_tx_assign_buffer(dp, ring_id); + if (unlikely(!tx_desc)) { + ab->soc_stats.tx_err.txbuf_na[ring_id]++; + return -ENOSPC; + } + + dmac_clean_range_no_dsb(skb->data, skb->data + len); + paddr = dma_map_single_attrs(dev, skb->data, len, + DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); + if (unlikely(dma_mapping_error(dev, paddr))) { + atomic_inc(&ab->soc_stats.tx_err.misc_fail); + ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); + ret = -ENOMEM; + goto fail_remove_tx_buf; + } + + tx_desc->skb = skb; + tx_desc->mac_id = arvif->pdev_idx; + tx_desc->recycler_fast_xmit = 0; + tx_desc->timestamp = ktime_get_real(); + +#ifdef CONFIG_MAC80211_SFE_SUPPORT + /* the edma driver uses this flags to optimize the cache invalidation */ + skb->fast_recycled = 1; + if (skb->is_from_recycler) + tx_desc->recycler_fast_xmit = 1; +#elif defined(CONFIG_IP_FFN) + /* mark it so page pool recycler will remember this */ + if (skb->ffn_ff_done) + skb->ffn_ff_done |= BIT(1); +#endif + + skb_cb->vif = arvif->ahvif->vif; + skb_cb->paddr = paddr; + + hal_ring_id = ring_id + HAL_SRNG_RING_ID_SW2TCL1; + tcl_ring = &ab->hal.srng_list[hal_ring_id]; + spin_lock_bh(&tcl_ring->lock); + ath12k_hal_srng_access_src_ring_begin_nolock(tcl_ring); + + hal_tcl_desc = (void *)ath12k_hal_srng_src_get_next_entry_nolock(ab, tcl_ring); + if (unlikely(!hal_tcl_desc)) { + /* NOTE: It is highly unlikely we'll be running out of tcl_ring + * desc because the desc is directly enqueued onto hw queue. + */ + ath12k_hal_srng_access_umac_src_ring_end_nolock(tcl_ring); + spin_unlock_bh(&tcl_ring->lock); + ab->soc_stats.tx_err.desc_na[ring_id]++; + ret = -ENOMEM; + goto fail_unmap_dma; + } + + ab->soc_stats.tx_enqueued[ring_id]++; + + tcl_desc.buf_addr_info.info0 = (u32)paddr; + tcl_desc.buf_addr_info.info1 = (tx_desc->desc_id << 12); + tcl_desc.info0 = arvif->desc.info0; + tcl_desc.info1 = arvif->desc.info1; + tcl_desc.info2 = skb->len; + + if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) + tcl_desc.info2 |= TX_IP_CHECKSUM; + + tcl_desc.info3 = arvif->desc.info3; + tcl_desc.info4 = arvif->desc.info4; + tcl_desc.info5 = 0; +#ifdef CONFIG_ATH12K_SAWF + /* SAWF */ + if (u32_get_bits(skb->mark, SAWF_TAG_ID) == SAWF_VALID_TAG) { + u32 msduq_id = u32_get_bits(skb->mark, SAWF_MSDUQ_ID); + + if (msduq_id < (ab->max_msduq_per_tid * ATH12K_SAWF_MAX_TID_SUPPORT)) { + u32 meta_data_flags; + tcl_desc.info3 |= ath12k_sawf_get_tcl_cmd_info3_update(msduq_id); + meta_data_flags = + ath12k_sawf_get_tcl_metadata_update(skb->mark); + tcl_desc.info1 = u32_encode_bits(meta_data_flags, + HAL_TCL_DATA_CMD_INFO1_CMD_NUM); + } + + if (unlikely(ath12k_debugfs_is_sawf_stats_enabled(ar) & ATH12K_SAWF_STATS_BASIC)) { + u16 peer_id = u32_get_bits(skb->mark, SAWF_PEER_ID); + u32 len = skb_headlen(skb); + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_id(ab, peer_id); + if (unlikely(!peer || !peer->sta)) + ath12k_dbg(ab, ATH12K_DBG_SAWF, + "peer_id %u not found \n", peer_id); + else + ath12k_sawf_tx_enqueue_peer_stats(ab, peer, msduq_id, len); + spin_unlock_bh(&ab->base_lock); + } + /* Store the NWDELAY to skb->mark which can be fetched + * during tx completion + */ + if (info->sawf.nw_delay > SAWF_NW_DELAY_MAX) + info->sawf.nw_delay = SAWF_NW_DELAY_MAX; + skb->mark = (SAWF_VALID_TAG << SAWF_TAG_SHIFT) | (info->sawf.nw_delay << SAWF_NW_DELAY_SHIFT) | msduq_id; + } +#endif + memcpy(hal_tcl_desc, &tcl_desc, sizeof(tcl_desc)); + dsb(st); + ath12k_hal_srng_access_umac_src_ring_end_nolock(tcl_ring); + spin_unlock_bh(&tcl_ring->lock); + + atomic_inc(&ar->dp.num_tx_pending); + atomic_inc(&ab->ag->num_dp_tx_pending); + + return 0; + +fail_unmap_dma: + dma_unmap_single(ab->dev, skb_cb->paddr, 256, DMA_TO_DEVICE); + +fail_remove_tx_buf: + ath12k_dp_tx_release_txbuf(dp, tx_desc, ring_id); + + return ret; +} +EXPORT_SYMBOL(ath12k_dp_tx_direct); + +int ath12k_dp_tx(struct ath12k *ar, struct ath12k_link_vif *arvif, + struct ath12k_sta *ahsta, struct sk_buff *skb, + bool gsn_valid, int mcbc_gsn) +{ + struct ath12k_vif *ahvif = arvif->ahvif; struct ath12k_base *ab = ar->ab; + struct ath12k_hw_group *ag = ab->ag; struct ath12k_dp *dp = &ab->dp; + struct ath12k_peer *peer; struct hal_tx_info ti = {0}; struct ath12k_tx_desc_info *tx_desc; +#ifdef CONFIG_ATH12K_SAWF struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); +#endif struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); struct hal_tcl_data_cmd *hal_tcl_desc; struct hal_tx_msdu_ext_desc *msg; @@ -140,92 +438,107 @@ struct hal_srng *tcl_ring; struct ieee80211_hdr *hdr = (void *)skb->data; struct dp_tx_ring *tx_ring; - u8 pool_id; + struct hal_tcl_data_cmd *tcl_cmd; u8 hal_ring_id; int ret; - u8 ring_selector, ring_map = 0; - bool tcl_ring_retry; + u16 peer_id; bool msdu_ext_desc = false; + bool is_diff_encap = false, is_qos_null = false; + bool add_htt_metadata = false; - if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) || + unlikely(test_bit(ATH12K_FLAG_UMAC_PRERESET_START, &ab->dev_flags))) return -ESHUTDOWN; - if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && - !ieee80211_is_data(hdr->frame_control)) + if (unlikely(!(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) && + !ieee80211_is_data(hdr->frame_control))) return -ENOTSUPP; - pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); - - /* Let the default ring selection be based on current processor - * number, where one of the 3 tcl rings are selected based on - * the smp_processor_id(). In case that ring - * is full/busy, we resort to other available rings. - * If all rings are full, we drop the packet. - * TODO: Add throttling logic when all rings are full - */ - ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); - -tcl_ring_sel: - tcl_ring_retry = false; - ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; - - ring_map |= BIT(ti.ring_id); - ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; + ti.ring_id = + ab->hw_params->hw_ops->get_ring_selector(skb); tx_ring = &dp->tx_ring[ti.ring_id]; - tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); - if (!tx_desc) + tx_desc = ath12k_dp_tx_assign_buffer(dp, ti.ring_id); + if (unlikely(!tx_desc)) { + ab->soc_stats.tx_err.txbuf_na[ti.ring_id]++; return -ENOMEM; + } ti.bank_id = arvif->bank_id; - ti.meta_data_flags = arvif->tcl_metadata; - if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && - test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { - if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { - ti.encrypt_type = - ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); + if (ieee80211_has_a4(hdr->frame_control) && + is_multicast_ether_addr(hdr->addr3) && ahsta && + ahsta->use_4addr_set) { + if (unlikely(!ahsta->link[ahsta->primary_link_id])) { + ath12k_err(ab, "arsta not found on primary link"); + ret = -EINVAL; + goto fail_remove_tx_buf; + } + ti.meta_data_flags = ahsta->link[ahsta->primary_link_id]->tcl_metadata; + ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TO_FW, 1); + spin_lock_bh(&ab->base_lock); + peer_id = FIELD_GET(HTT_TCL_META_DATA_PEER_ID_MISSION, + ti.meta_data_flags); + peer = ath12k_peer_find_by_id(ab, peer_id); + if (!peer || !peer->sta) { + spin_unlock_bh(&ab->base_lock); + ath12k_dbg(ab, ATH12K_DBG_DP_TX, + "Dropped packet with non existent peer id %u\n", peer_id); + ret = -EINVAL; + goto fail_remove_tx_buf; + } + spin_unlock_bh(&ab->base_lock); - if (ieee80211_has_protected(hdr->frame_control)) - skb_put(skb, IEEE80211_CCMP_MIC_LEN); } else { - ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; + ti.meta_data_flags = arvif->tcl_metadata; } - msdu_ext_desc = true; + /* TCL Meta data flags are shared for both SAWF and Global Seq Number updates. + * SAWF and Global Seq Number are mutually exclusive. + * Global Seq Number - Multicast, SAWF - Unicast + */ +#ifdef CONFIG_ATH12K_SAWF + if (u32_get_bits(skb->mark, SAWF_TAG_ID) == SAWF_VALID_TAG) { + u32 msduq_id = u32_get_bits(skb->mark, SAWF_MSDUQ_ID); + if (msduq_id < (ab->max_msduq_per_tid * ATH12K_SAWF_MAX_TID_SUPPORT)) { + ti.meta_data_flags = + ath12k_sawf_get_tcl_metadata_update(skb->mark); + } + } else if (gsn_valid) { +#else + if (gsn_valid) { +#endif /* CONFIG_ATH12K_SAWF */ + ti.meta_data_flags = u32_encode_bits(HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM, + HTT_TCL_META_DATA_TYPE_MISSION) | + u32_encode_bits(mcbc_gsn, HTT_TCL_META_DATA_GLOBAL_SEQ_NUM); + ti.vdev_id = arvif->vdev_id + + HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID; + } else { + ti.vdev_id = arvif->vdev_id; } - ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb); + ti.encap_type = ath12k_dp_tx_get_encap_type(ab, skb); ti.addr_search_flags = arvif->hal_addr_search_flags; ti.search_type = arvif->search_type; ti.type = HAL_TCL_DESC_TYPE_BUFFER; - ti.pkt_offset = 0; - ti.lmac_id = ar->lmac_id; - ti.vdev_id = arvif->vdev_id; - ti.bss_ast_hash = arvif->ast_hash; - ti.bss_ast_idx = arvif->ast_idx; - ti.dscp_tid_tbl_idx = 0; - - if (skb->ip_summed == CHECKSUM_PARTIAL && - ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { - ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | - u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | - u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | - u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | - u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); - } - ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); - - ti.tid = ath12k_dp_tx_get_tid(skb); + if (likely(skb->ip_summed == CHECKSUM_PARTIAL && + ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) { + ti.flags0 |= TX_IP_CHECKSUM; + } switch (ti.encap_type) { case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: + if ((ahvif->vif->offload_flags & IEEE80211_OFFLOAD_ENCAP_ENABLED) && + (skb->protocol == cpu_to_be16(ETH_P_PAE) || + (is_qos_null = ieee80211_is_qos_nullfunc(hdr->frame_control)))) + is_diff_encap = true; + else ath12k_dp_tx_encap_nwifi(skb); break; case HAL_TCL_ENCAP_TYPE_RAW: - if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { + if (!test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) { ret = -EINVAL; goto fail_remove_tx_buf; } @@ -241,8 +554,55 @@ goto fail_remove_tx_buf; } + if (unlikely((ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_ETHERNET && + !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP)))) { + msdu_ext_desc = true; + + if (skb->protocol == cpu_to_be16(ETH_P_PAE)) { + ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; + ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; + } + } + + if (unlikely(ahvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW)) { + if (skb->protocol == cpu_to_be16(ETH_P_ARP)) { + ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; + ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; + msdu_ext_desc = true; + } + + if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { + ti.encrypt_type = + ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); + + if (ieee80211_has_protected(hdr->frame_control)) + skb_put(skb, IEEE80211_CCMP_MIC_LEN); + } else { + ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; + } + } + + if ((!test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->ag->dev_flags) && + !(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP) && + !(skb_cb->flags & ATH12K_SKB_CIPHER_SET) && + ieee80211_has_protected(hdr->frame_control)) || + is_diff_encap) { + if (is_qos_null && msdu_ext_desc) + goto skip_htt_meta; + + /* Add metadata for sw encrypted vlan group traffic */ + add_htt_metadata = true; + msdu_ext_desc = true; + + ti.meta_data_flags |= HTT_TCL_META_DATA_VALID_HTT; +skip_htt_meta: + ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TO_FW, 1); + ti.encap_type = HAL_TCL_ENCAP_TYPE_RAW; + ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; + } + ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); - if (dma_mapping_error(ab->dev, ti.paddr)) { + if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) { atomic_inc(&ab->soc_stats.tx_err.misc_fail); ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); ret = -ENOMEM; @@ -251,13 +611,14 @@ tx_desc->skb = skb; tx_desc->mac_id = ar->pdev_idx; + tx_desc->recycler_fast_xmit = 0; + tx_desc->timestamp = ktime_get_real(); ti.desc_id = tx_desc->desc_id; ti.data_len = skb->len; skb_cb->paddr = ti.paddr; - skb_cb->vif = arvif->vif; - skb_cb->ar = ar; + skb_cb->vif = ahvif->vif; - if (msdu_ext_desc) { + if (unlikely(msdu_ext_desc)) { skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); if (!skb_ext_desc) { ret = -ENOMEM; @@ -270,11 +631,22 @@ msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); + if (add_htt_metadata) { + ret = ath12k_dp_prepare_htt_metadata(skb_ext_desc); + if (ret < 0) { + ath12k_dbg(ab, ATH12K_DBG_DP_TX, + "Failed to add HTT meta data, dropping packet\n"); + goto fail_unmap_dma; + } + } + ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, skb_ext_desc->len, DMA_TO_DEVICE); ret = dma_mapping_error(ab->dev, ti.paddr); if (ret) { - kfree_skb(skb_ext_desc); + atomic_inc(&ab->soc_stats.tx_err.misc_fail); + ath12k_warn(ab, "Failed to DMA map data Tx buffer\n"); + dev_kfree_skb_any(skb_ext_desc); goto fail_unmap_dma; } @@ -282,115 +654,270 @@ ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; skb_cb->paddr_ext_desc = ti.paddr; + tx_desc->skb_ext_desc = skb_ext_desc; } hal_ring_id = tx_ring->tcl_data_ring.ring_id; tcl_ring = &ab->hal.srng_list[hal_ring_id]; - spin_lock_bh(&tcl_ring->lock); - - ath12k_hal_srng_access_begin(ab, tcl_ring); - + ath12k_hal_srng_access_src_ring_begin_nolock(tcl_ring); hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); - if (!hal_tcl_desc) { + if (unlikely(!hal_tcl_desc)) { /* NOTE: It is highly unlikely we'll be running out of tcl_ring * desc because the desc is directly enqueued onto hw queue. */ - ath12k_hal_srng_access_end(ab, tcl_ring); - ab->soc_stats.tx_err.desc_na[ti.ring_id]++; + ath12k_hal_srng_access_umac_src_ring_end_nolock(tcl_ring); spin_unlock_bh(&tcl_ring->lock); + ab->soc_stats.tx_err.desc_na[ti.ring_id]++; ret = -ENOMEM; - /* Checking for available tcl descritors in another ring in - * case of failure due to full tcl ring now, is better than - * checking this ring earlier for each pkt tx. - * Restart ring selection if some rings are not checked yet. - */ - if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && - ab->hw_params->tcl_ring_retry) { - tcl_ring_retry = true; - ring_selector++; - } - - goto fail_unmap_dma; + goto fail_unmap_dma_ext_desc; } - ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); + ab->soc_stats.tx_enqueued[ti.ring_id]++; + arvif->link_stats.tx_encap_type[ti.encap_type]++; + arvif->link_stats.tx_encrypt_type[ti.encrypt_type]++; + arvif->link_stats.tx_desc_type[ti.type]++; + tcl_cmd = (struct hal_tcl_data_cmd *)hal_tcl_desc; + + tcl_cmd->buf_addr_info.info0 = (u32)ti.paddr; + /* TODO: Copy the upper 8 bits here */ + tcl_cmd->buf_addr_info.info1 = (ti.desc_id << 12); + tcl_cmd->info0 = (ti.type << 1) | arvif->desc.info0; + tcl_cmd->info1 = ti.meta_data_flags << 16; + tcl_cmd->info2 = ti.flags0 | ti.data_len; - ath12k_hal_srng_access_end(ab, tcl_ring); + /* In tcl_cmd->info3, Bit 24 to 31 represents vdev_id + * LSH 24 times to add updated vdev_id to info3 + */ + tcl_cmd->info3 = (ti.vdev_id << 24) | arvif->desc.info3; + tcl_cmd->info4 = arvif->desc.info4; + tcl_cmd->info5 = 0; + +#ifdef CONFIG_ATH12K_SAWF + /* SAWF */ + if (u32_get_bits(skb->mark, SAWF_TAG_ID) == SAWF_VALID_TAG) { + u32 msduq_id = u32_get_bits(skb->mark, SAWF_MSDUQ_ID); + + if (msduq_id < (ab->max_msduq_per_tid * ATH12K_SAWF_MAX_TID_SUPPORT)) { + tcl_cmd->info3 |= + ath12k_sawf_get_tcl_cmd_info3_update(msduq_id); + } + if (unlikely(ath12k_debugfs_is_sawf_stats_enabled(ar) & ATH12K_SAWF_STATS_BASIC)) { + peer_id = u32_get_bits(skb->mark, SAWF_PEER_ID); + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_id(ab, peer_id); + if (unlikely(!peer || !peer->sta)) + ath12k_dbg(ab, ATH12K_DBG_SAWF, + "peer_id %u not found\n", peer_id); + else + ath12k_sawf_tx_enqueue_peer_stats(ab, peer, msduq_id, ti.data_len); + spin_unlock_bh(&ab->base_lock); + } + /* Store the NWDELAY to skb->mark which can be fetched + * during tx completion + */ + if (info->sawf.nw_delay > SAWF_NW_DELAY_MAX) + info->sawf.nw_delay = SAWF_NW_DELAY_MAX; + skb->mark = (SAWF_VALID_TAG << SAWF_TAG_SHIFT) | (info->sawf.nw_delay << SAWF_NW_DELAY_SHIFT) | msduq_id; + } +#endif /* CONFIG_ATH12K_SAWF */ + dsb(st); + ath12k_hal_srng_access_umac_src_ring_end_nolock(tcl_ring); spin_unlock_bh(&tcl_ring->lock); ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", skb->data, skb->len); + if (gsn_valid) + arvif->link_stats.tx_bcast_mcast++; + else + arvif->link_stats.tx_enqueued++; + atomic_inc(&ar->dp.num_tx_pending); + atomic_inc(&ab->ag->num_dp_tx_pending); return 0; +fail_unmap_dma_ext_desc: + if (unlikely(msdu_ext_desc)) { + dma_unmap_single(ab->dev, ti.paddr, + skb_ext_desc->len, DMA_TO_DEVICE); + dev_kfree_skb_any(skb_ext_desc); + } + fail_unmap_dma: - dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); - dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, - sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); + dma_unmap_single(ab->dev, skb_cb->paddr, skb->len, DMA_TO_DEVICE); fail_remove_tx_buf: - ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); - if (tcl_ring_retry) - goto tcl_ring_sel; + ath12k_dp_tx_release_txbuf(dp, tx_desc, ti.ring_id); + + arvif->link_stats.tx_dropped++; return ret; } +static inline void ath12k_dp_tx_decrement(struct ath12k *ar) +{ + atomic_dec(&ar->ab->ag->num_dp_tx_pending); + + if (atomic_read(&ar->flush_request)) { + if (atomic_dec_and_test(&ar->dp.num_tx_pending)) + wake_up(&ar->tx_empty_waitq); + } else { + atomic_dec(&ar->dp.num_tx_pending); + } +} + static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, struct sk_buff *msdu, u8 mac_id, - struct dp_tx_ring *tx_ring) + struct dp_tx_ring *tx_ring, + struct sk_buff *skb_ext_desc) { - struct ath12k *ar; struct ath12k_skb_cb *skb_cb; + struct ath12k *ar; skb_cb = ATH12K_SKB_CB(msdu); + ar = ab->pdevs[mac_id].ar; - dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); - if (skb_cb->paddr_ext_desc) - dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, - sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); + dma_unmap_single_attrs(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + if (unlikely(skb_ext_desc)) { + dma_unmap_single_attrs(ab->dev, skb_cb->paddr_ext_desc, + skb_ext_desc->len, + DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); + dev_kfree_skb_any(skb_ext_desc); + } - dev_kfree_skb_any(msdu); + ieee80211_free_txskb(ar->ah->hw, msdu); - ar = ab->pdevs[mac_id].ar; - if (atomic_dec_and_test(&ar->dp.num_tx_pending)) - wake_up(&ar->dp.tx_empty_waitq); + ath12k_dp_tx_decrement(ar); +} + +static inline void ath12k_dp_tx_status_parse(struct ath12k_base *ab, + struct hal_wbm_completion_ring_tx *desc, + struct hal_tx_status *ts) +{ + ts->buf_rel_source = + FIELD_GET(HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE, desc->info0); + if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && + ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) + return; + + if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) + return; + + ts->status = FIELD_GET(HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON, + desc->info0); + ts->ppdu_id = FIELD_GET(HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER, + desc->info1); + ts->ack_rssi = FIELD_GET(HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI, + desc->info2); + if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID) + ts->rate_stats = desc->rate_stats.info0; + else + ts->rate_stats = 0; + ts->tid = FIELD_GET(HAL_WBM_RELEASE_TX_INFO3_TID, desc->info3); + + ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_TX_INFO3_PEER_ID, desc->info3); + ts->flags = FIELD_GET(HAL_WBM_RELEASE_TX_INFO2_FIRST_MSDU, desc->info2) | + FIELD_GET(HAL_WBM_RELEASE_TX_INFO2_LAST_MSDU, desc->info2); + ts->buffer_timestamp = FIELD_GET(HAL_WBM_RELEASE_TX_INFO2_BUFFER_TIMESTAMP, + desc->info2); + ts->tsf = desc->rate_stats.tsf; } static void ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, struct sk_buff *msdu, struct dp_tx_ring *tx_ring, - struct ath12k_dp_htt_wbm_tx_status *ts) + struct ath12k_dp_htt_wbm_tx_status *ts, + struct sk_buff *skb_ext_desc, u8 mac_id, + void *desc, ktime_t timestamp) { struct ieee80211_tx_info *info; struct ath12k_skb_cb *skb_cb; struct ath12k *ar; + struct ieee80211_vif *vif; + struct ath12k_vif *ahvif; + struct ath12k_peer *peer; + struct hal_tx_status ts_status = { 0 }; + unsigned long attrs = 0; + u8 flags = 0; + bool drop_disable = false; skb_cb = ATH12K_SKB_CB(msdu); info = IEEE80211_SKB_CB(msdu); - ar = skb_cb->ar; + ar = ab->pdevs[mac_id].ar; + ab->soc_stats.tx_completed[tx_ring->tcl_data_ring_id]++; - if (atomic_dec_and_test(&ar->dp.num_tx_pending)) - wake_up(&ar->dp.tx_empty_waitq); + ath12k_dp_tx_decrement(ar); + + flags = skb_cb->flags; + drop_disable = (ab->stats_disable && !(flags & ATH12K_SKB_TX_STATUS)); + + /* If drop disable case, avoid cpu_sync since we are not passed + * the skb to mac80211 + */ + if (drop_disable) + attrs |= DMA_ATTR_SKIP_CPU_SYNC; + + dma_unmap_single_attrs(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE, attrs); - dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); - if (skb_cb->paddr_ext_desc) - dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, - sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); + if (unlikely(skb_ext_desc)) { + dma_unmap_single_attrs(ab->dev, skb_cb->paddr_ext_desc, + skb_ext_desc->len, DMA_TO_DEVICE, attrs); + dev_kfree_skb_any(skb_ext_desc); + } + + /* Free skb here if stats is disabled */ + if (drop_disable) { + if (skb_cb->vif) { + ahvif = (void *)skb_cb->vif->drv_priv; + if (ahvif->links_map & BIT(skb_cb->link_id)) { + if (ahvif->link[skb_cb->link_id]) + ahvif->link[skb_cb->link_id]->link_stats.tx_completed++; + } else { + ath12k_warn(ab, + "invalid linkid 0x%X in htt tx complete buf linkmap %lu\n", + skb_cb->link_id, + ahvif->links_map); + } + } + + if (msdu->destructor) { + msdu->wifi_acked_valid = 1; + msdu->wifi_acked = ts->acked; + } + ieee80211_free_txskb(ar->ah->hw, msdu); + return; + } + + if (unlikely(!skb_cb->vif)) { + ieee80211_free_txskb(ar->ah->hw, msdu); + return; + } + + vif = skb_cb->vif; + ahvif = (void *)vif->drv_priv; + if (ahvif->links_map & BIT(skb_cb->link_id)) { + if (ahvif->link[skb_cb->link_id]) + ahvif->link[skb_cb->link_id]->link_stats.tx_completed++; + } else { + ath12k_warn(ab, + "invalid linkid 0x%X in htt tx complete buf linkmap %lu\n", + skb_cb->link_id, + ahvif->links_map); + } memset(&info->status, 0, sizeof(info->status)); if (ts->acked) { if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { info->flags |= IEEE80211_TX_STAT_ACK; - info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + + info->status.ack_signal = ar->rssi_offsets.rssi_offset + ts->ack_rssi; info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; } else { @@ -398,36 +925,58 @@ } } - ieee80211_tx_status(ar->hw, msdu); + if (unlikely(ath12k_debugfs_is_sawf_stats_enabled(ar))) { + spin_lock_bh(&ab->base_lock); + ath12k_dp_tx_status_parse(ab, desc, &ts_status); + peer = ath12k_peer_find_by_id(ab, ts_status.peer_id); + if (unlikely(!peer || !peer->sta)) + ath12k_dbg(ab, ATH12K_DBG_DATA, + "dp_tx: failed to find the peer with peer_id %d\n", + ts_status.peer_id); + else + ath12k_sawf_stats_update(ar, msdu, &ts_status, peer, timestamp); + spin_unlock_bh(&ab->base_lock); + } + + if ((!flags & ATH12K_SKB_HW_80211_ENCAP)) + ieee80211_tx_status_8023(ar->ah->hw, vif, msdu); + else + ieee80211_tx_status(ar->ah->hw, msdu); } static void ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, void *desc, u8 mac_id, struct sk_buff *msdu, - struct dp_tx_ring *tx_ring) + struct dp_tx_ring *tx_ring, + struct sk_buff *skb_ext_desc, + ktime_t timestamp) { struct htt_tx_wbm_completion *status_desc; struct ath12k_dp_htt_wbm_tx_status ts = {0}; - enum hal_wbm_htt_tx_comp_status wbm_status; + int htt_status; status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; - wbm_status = le32_get_bits(status_desc->info0, + htt_status = le32_get_bits(status_desc->info0, HTT_TX_WBM_COMP_INFO0_STATUS); - switch (wbm_status) { + ab->soc_stats.fw_tx_status[htt_status]++; + + switch (htt_status) { case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: - case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: - case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: - ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); + ts.acked = (htt_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); ts.ack_rssi = le32_get_bits(status_desc->info2, HTT_TX_WBM_COMP_INFO2_ACK_RSSI); - ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts); + ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts, skb_ext_desc, mac_id, desc, timestamp); + break; + case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: + case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: - ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring); + case HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH: + ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring, skb_ext_desc); break; case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: /* This event is to be handled only when the driver decides to @@ -435,41 +984,195 @@ */ break; default: - ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status); + ath12k_warn(ab, "Unknown htt tx status %d\n", htt_status); break; } } -static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, +static void ath12k_dp_tx_cache_peer_stats(struct ath12k *ar, struct sk_buff *msdu, struct hal_tx_status *ts) { + struct ath12k_per_peer_tx_stats *peer_stats = &ar->cached_stats; + + if (ts->try_cnt > 1) { + peer_stats->retry_pkts += ts->try_cnt - 1; + peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len; + + if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { + peer_stats->failed_pkts += 1; + peer_stats->failed_bytes += msdu->len; + } + } +} + +void ath12k_dp_tx_update_txcompl(struct ath12k *ar, struct hal_tx_status *ts) +{ struct ath12k_base *ab = ar->ab; - struct ieee80211_tx_info *info; - struct ath12k_skb_cb *skb_cb; + struct ath12k_per_peer_tx_stats *peer_stats = &ar->cached_stats; + enum hal_tx_rate_stats_pkt_type pkt_type; + enum hal_tx_rate_stats_sgi sgi; + enum hal_tx_rate_stats_bw bw; + struct ath12k_peer *peer; + struct ath12k_link_sta *arsta; + u16 rate, ru_tones; + u8 mcs, rate_idx, ofdma; + int ret; - if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { - /* Must not happen */ - return; + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_id(ab, ts->peer_id); + if (!peer || !peer->sta) { + ath12k_dbg(ab, ATH12K_DBG_DP_TX, + "failed to find the peer by id %u\n", ts->peer_id); + goto err_out; + } + + arsta = ath12k_peer_get_link_sta(ab, peer); + if (!arsta) { + ath12k_warn(ab, "link sta not found on peer %pM id %d\n", + peer->addr, peer->peer_id); + goto err_out; + } + + memset(&arsta->txrate, 0, sizeof(arsta->txrate)); + pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE, + ts->rate_stats); + mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS, + ts->rate_stats); + sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI, + ts->rate_stats); + bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, ts->rate_stats); + ru_tones = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, ts->rate_stats); + ofdma = FIELD_GET(HAL_TX_RATE_STATS_INFO0_OFDMA_TX, ts->rate_stats); + + /* This is to prefer choose the real NSS value arsta->last_txrate.nss, + * if it is invalid, then choose the NSS value while assoc. + */ + if (arsta->last_txrate.nss) + arsta->txrate.nss = arsta->last_txrate.nss; + else + arsta->txrate.nss = arsta->peer_nss; + + if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11A || + pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11B) { + ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, + pkt_type, + &rate_idx, + &rate); + if (ret < 0) + goto err_out; + arsta->txrate.legacy = rate; + } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11N) { + if (mcs > 7) { + ath12k_warn(ab, "Invalid HT mcs index %d\n", mcs); + goto err_out; + } + + if (arsta->txrate.nss != 0) + arsta->txrate.mcs = mcs + 8 * (arsta->txrate.nss - 1); + arsta->txrate.flags = RATE_INFO_FLAGS_MCS; + if (sgi) + arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; + } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AC) { + if (mcs > 9) { + ath12k_warn(ab, "Invalid VHT mcs index %d\n", mcs); + goto err_out; + } + + arsta->txrate.mcs = mcs; + arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; + if (sgi) + arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; + } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { + if (mcs > 11) { + ath12k_warn(ab, "Invalid HE mcs index %d\n", mcs); + goto err_out; + } + + arsta->txrate.mcs = mcs; + arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; + arsta->txrate.he_gi = ath12k_mac_he_gi_to_nl80211_he_gi(sgi); + } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11BE) { + if (mcs > 13) { + ath12k_warn(ab, "Invalid EHT mcs index %d\n", mcs); + goto err_out; + } + + arsta->txrate.mcs = mcs; + arsta->txrate.flags = RATE_INFO_FLAGS_EHT_MCS; + arsta->txrate.he_gi = ath12k_mac_he_gi_to_nl80211_he_gi(sgi); + } + + arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); + if (ofdma && pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) { + arsta->txrate.bw = RATE_INFO_BW_HE_RU; + arsta->txrate.he_ru_alloc = + ath12k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); + } + + if (ath12k_debugfs_is_extd_tx_stats_enabled(ar)) + ath12k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx); + +err_out: + spin_unlock_bh(&ab->base_lock); } +static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, + struct sk_buff *msdu, + struct hal_wbm_release_ring *tx_status, + enum hal_wbm_rel_src_module buf_rel_source, + int ring, ktime_t timestamp) +{ + struct ieee80211_tx_status status = { 0 }; + struct ieee80211_rate_status status_rate = { 0 }; + struct ath12k_base *ab = ar->ab; + struct ieee80211_tx_info *info; + struct ath12k_skb_cb *skb_cb; + struct ath12k_peer *peer; + struct ath12k_link_sta *arsta; + struct rate_info rate; + struct hal_tx_status ts = { 0 }; + enum hal_wbm_htt_tx_comp_status wbm_status; + struct ieee80211_vif *vif; + struct ath12k_vif *ahvif; + u8 flags = 0; + skb_cb = ATH12K_SKB_CB(msdu); + ab->soc_stats.tx_completed[ring]++; - dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); - if (skb_cb->paddr_ext_desc) - dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, - sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); + flags = skb_cb->flags; - rcu_read_lock(); + if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) { + ieee80211_free_txskb(ar->ah->hw, msdu); + return; + } - if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { - dev_kfree_skb_any(msdu); - goto exit; + if (unlikely(!skb_cb->vif)) { + ieee80211_free_txskb(ar->ah->hw, msdu); + return; } - if (!skb_cb->vif) { - dev_kfree_skb_any(msdu); - goto exit; + ath12k_dp_tx_status_parse(ab, (struct hal_wbm_completion_ring_tx *)tx_status, &ts); + + ar->wmm_stats.tx_type = ath12k_tid_to_ac(ts.tid > ATH12K_DSCP_PRIORITY ? 0:ts.tid); + if (ar->wmm_stats.tx_type) { + if (ts.status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) + ar->wmm_stats.total_wmm_tx_drop[ar->wmm_stats.tx_type]++; + } + + wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, + tx_status->info0); + + vif = skb_cb->vif; + ahvif = (void *)vif->drv_priv; + if (ahvif->links_map & BIT(skb_cb->link_id)) { + if (ahvif->link[skb_cb->link_id]) + ahvif->link[skb_cb->link_id]->link_stats.tx_completed++; + } else { + ath12k_warn(ar->ab, + "invalid linkid 0x%X in tx complete msdu linkmap %lu\n", + skb_cb->link_id, + ahvif->links_map); } info = IEEE80211_SKB_CB(msdu); @@ -478,142 +1181,520 @@ /* skip tx rate update from ieee80211_status*/ info->status.rates[0].idx = -1; - if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && + if (ts.status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { info->flags |= IEEE80211_TX_STAT_ACK; - info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + - ts->ack_rssi; + info->status.ack_signal = ar->rssi_offsets.rssi_offset + + ts.ack_rssi; info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; } - if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && + if (ts.status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && (info->flags & IEEE80211_TX_CTL_NO_ACK)) info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; - /* NOTE: Tx rate status reporting. Tx completion status does not have - * necessary information (for example nss) to build the tx rate. - * Might end up reporting it out-of-band from HTT stats. - */ + if (ts.status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { + switch (ts.status) { + case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: + case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: + case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: + case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: + if (unlikely(ath12k_debugfs_is_sawf_stats_enabled(ar))) { + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_id(ab, ts.peer_id); + if (unlikely(!peer || !peer->sta)) + ath12k_dbg(ab, ATH12K_DBG_DATA, + "dp_tx: failed to find the peer with peer_id %d\n", + ts.peer_id); + else + ath12k_sawf_stats_update(ar, msdu, &ts, peer, timestamp); + spin_unlock_bh(&ab->base_lock); + } + ieee80211_free_txskb(ar->ah->hw, msdu); + return; + default: + //TODO: Remove this print and add as a stats + ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n", ts.status); + } + } - ieee80211_tx_status(ar->hw, msdu); + if (unlikely(ath12k_debugfs_is_extd_tx_stats_enabled(ar)) || + ab->hw_params->single_pdev_only) { + if (ts.flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) { + if (ar->last_ppdu_id == 0) { + ar->last_ppdu_id = ts.ppdu_id; + } else if (ar->last_ppdu_id == ts.ppdu_id || + ar->cached_ppdu_id == ar->last_ppdu_id) { + ar->cached_ppdu_id = ar->last_ppdu_id; + ar->cached_stats.is_ampdu = true; + ath12k_dp_tx_update_txcompl(ar, &ts); + memset(&ar->cached_stats, 0, + sizeof(struct ath12k_per_peer_tx_stats)); + } else { + ar->cached_stats.is_ampdu = false; + ath12k_dp_tx_update_txcompl(ar, &ts); + memset(&ar->cached_stats, 0, + sizeof(struct ath12k_per_peer_tx_stats)); + } + ar->last_ppdu_id = ts.ppdu_id; + } -exit: - rcu_read_unlock(); + ath12k_dp_tx_cache_peer_stats(ar, msdu, &ts); } -static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, - struct hal_wbm_completion_ring_tx *desc, - struct hal_tx_status *ts) -{ - ts->buf_rel_source = - le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); - if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && - ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_id(ab, ts.peer_id); + if (unlikely(!peer || !peer->sta)) { + ath12k_dbg(ab, ATH12K_DBG_DATA, + "dp_tx: failed to find the peer with peer_id %d\n", + ts.peer_id); + spin_unlock_bh(&ab->base_lock); + ieee80211_free_txskb(ar->ah->hw, msdu); return; + } - if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) + arsta = ath12k_peer_get_link_sta(ab, peer); + if (!arsta) { + ath12k_warn(ab, "link sta not found on peer %pM id %d\n", + peer->addr, peer->peer_id); + + spin_unlock_bh(&ab->base_lock); + ieee80211_free_txskb(ar->ah->hw, msdu); return; + } + + status.sta = peer->sta; + status.skb = msdu; + status.info = info; + rate = arsta->last_txrate; + + status_rate.rate_idx = rate; + status_rate.try_count = 1; - ts->status = le32_get_bits(desc->info0, - HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); + status.rates = &status_rate; + status.n_rates = 1; - ts->ppdu_id = le32_get_bits(desc->info1, - HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); - if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID) - ts->rate_stats = le32_to_cpu(desc->rate_stats.info0); + + if (unlikely(ath12k_debugfs_is_extd_tx_stats_enabled(ar))) { + if(arsta->wbm_tx_stats && wbm_status < HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX) + arsta->wbm_tx_stats->wbm_tx_comp_stats[wbm_status]++; + } + + if (unlikely(ath12k_debugfs_is_sawf_stats_enabled(ar))) + ath12k_sawf_stats_update(ar, msdu, &ts, peer, timestamp); + + spin_unlock_bh(&ab->base_lock); + + if (flags & ATH12K_SKB_HW_80211_ENCAP) + ieee80211_tx_status_8023(ar->ah->hw, vif, msdu); else - ts->rate_stats = 0; + ieee80211_tx_status_ext(ar->ah->hw, &status); } -void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) +static inline bool ath12k_dp_tx_completion_valid(struct hal_wbm_release_ring *desc) +{ + struct htt_tx_wbm_completion *status_desc; + + if (FIELD_GET(HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE, desc->info0) == + HAL_WBM_REL_SRC_MODULE_FW) { + status_desc = (struct htt_tx_wbm_completion *)(((u8 *)desc) + HTT_TX_WBM_COMP_STATUS_OFFSET); + + /* Dont consider HTT_TX_COMP_STATUS_MEC_NOTIFY */ + if (FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS, status_desc->info0) == + HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY) + return false; + } + return true; +} + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +static void ath12k_ppeds_tx_update_stats(struct ath12k *ar, struct sk_buff *msdu, + struct hal_wbm_release_ring *tx_status) +{ + struct ath12k_base *ab = ar->ab; + struct ieee80211_tx_info *info; + struct ath12k_peer *peer; + struct ath12k_link_sta *arsta; + struct hal_tx_status ts = { 0 }; + + info = IEEE80211_SKB_CB(msdu); + memset(&info->status, 0, sizeof(info->status)); + info->status.rates[0].idx = -1; + + ath12k_dp_tx_status_parse(ab, (struct hal_wbm_completion_ring_tx *)tx_status, &ts); + if (ts.status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && + !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { + info->flags |= IEEE80211_TX_STAT_ACK; + info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + + ts.ack_rssi; + info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; + } + + if (ts.status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && + (info->flags & IEEE80211_TX_CTL_NO_ACK)) + info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; + + if (ts.status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) { + switch (ts.status) { + case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: + case HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: + case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: + case HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: + return; + default: + //TODO: Remove this print and add as a stats + ath12k_dbg(ab, ATH12K_DBG_DP_TX, "tx frame is not acked status %d\n", ts.status); + } + } + + spin_lock_bh(&ab->base_lock); + + peer = ath12k_peer_find_by_id(ab, ts.peer_id); + if (unlikely(!peer || !peer->sta)) { + ath12k_dbg(ab, ATH12K_DBG_DATA, + "dp_tx: failed to find the peer with peer_id %d\n", + ts.peer_id); + spin_unlock_bh(&ab->base_lock); + return; + } + + arsta = ath12k_peer_get_link_sta(ab, peer); + if (!arsta) { + ath12k_warn(ab, "link sta not found on peer %pM id %d\n", + peer->addr, peer->peer_id); + spin_unlock_bh(&ab->base_lock); + return; + } + + ieee80211_ppeds_tx_update_stats(ar->ah->hw, peer->sta, info, arsta->txrate, + peer->link_id, msdu->len); + + spin_unlock_bh(&ab->base_lock); +} + +static inline +void ath12k_dp_ppeds_tx_comp_get_desc(struct ath12k_base *ab, + struct hal_wbm_completion_ring_tx *tx_status, + struct ath12k_ppeds_tx_desc_info **tx_desc) +{ + u64 desc_va = 0; + u32 desc_id; + + if (likely(HAL_WBM_COMPL_TX_INFO0_CC_DONE & tx_status->info0)) { + /* HW done cookie conversion */ + desc_va = ((u64)tx_status->buf_va_hi << 32 | + tx_status->buf_va_lo); + *tx_desc = (struct ath12k_ppeds_tx_desc_info *)((unsigned long)desc_va); + } else { + /* SW does cookie conversion to VA */ + desc_id = u32_get_bits(tx_status->buf_va_hi, + BUFFER_ADDR_INFO1_SW_COOKIE); + + *tx_desc = ath12k_dp_get_ppeds_tx_desc(ab, desc_id); + } +} + +int ath12k_ppeds_tx_completion_handler(struct ath12k_base *ab, int budget) { - struct ath12k *ar; struct ath12k_dp *dp = &ab->dp; - int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; + struct dp_ppeds_tx_comp_ring *tx_ring = &dp->ppeds_comp_ring.ppe_wbm2sw_ring; + int hal_ring_id = tx_ring->ppe_wbm2sw_ring.ring_id; struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; - struct ath12k_tx_desc_info *tx_desc = NULL; + struct ath12k_ppeds_tx_desc_info *tx_desc = NULL; struct sk_buff *msdu; - struct hal_tx_status ts = { 0 }; - struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; - struct hal_wbm_release_ring *desc; + u32 *desc; u8 mac_id; - u64 desc_va; + int valid_entries, count = 0, i = 0; + struct hal_wbm_completion_ring_tx *tx_status; + struct htt_tx_wbm_completion *status_desc; + enum hal_wbm_rel_src_module buf_rel_source; + struct sk_buff_head free_list_head; + int work_done = 0, htt_status; + size_t stat_size; + + if (likely(ab->stats_disable)) + /* only need buf_addr_info and info0 */ + stat_size = 3 * sizeof(u32); + else + stat_size = sizeof(struct hal_wbm_release_ring); spin_lock_bh(&status_ring->lock); - ath12k_hal_srng_access_begin(ab, status_ring); + ath12k_hal_srng_access_dst_ring_begin_nolock(ab, status_ring); + + valid_entries = ath12k_hal_srng_dst_num_free(ab, status_ring, false); + if (!valid_entries) { + ath12k_hal_srng_access_dst_ring_end_nolock(status_ring); + spin_unlock_bh(&status_ring->lock); + return work_done; + } + + if (valid_entries >= budget) + valid_entries = budget; + + ath12k_hal_srng_ppeds_dst_inv_entry(ab, status_ring, valid_entries); + skb_queue_head_init(&free_list_head); - while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { - desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); - if (!desc) + while (likely(valid_entries--)) { + desc = (struct hal_wbm_completion_ring_tx *)ath12k_hal_srng_dst_get_next_cache_entry(ab, status_ring); + if (!desc || !ath12k_dp_tx_completion_valid(desc)) + continue; + + memcpy(&tx_ring->tx_status[count], desc, stat_size); + count++; + + if (count == valid_entries) break; + } + + ath12k_hal_srng_access_dst_ring_end_nolock(status_ring); + + spin_lock_bh(&dp->ppeds_tx_desc_lock[ATH12K_PPEDS_DEFAULT_POOL_ID]); + spin_unlock_bh(&status_ring->lock); + + while (count--) { + tx_status = &tx_ring->tx_status[i++]; - memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], - desc, sizeof(*desc)); - tx_ring->tx_status_head = - ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); + ath12k_dp_ppeds_tx_comp_get_desc(ab, tx_status, &tx_desc); + if (unlikely(!tx_desc)) { + ath12k_warn(ab, "unable to retrieve ppe ds tx_desc!"); + continue; } - if (ath12k_hal_srng_dst_peek(ab, status_ring) && - (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { - /* TODO: Process pending tx_status messages when kfifo_is_full() */ - ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); + mac_id = tx_desc->mac_id; + + if (unlikely(!ab->stats_disable)) + ath12k_ppeds_tx_update_stats(ab->pdevs[mac_id].ar, tx_desc->skb, + tx_status); + + /* Release descriptor as soon as extracting necessary info + * to reduce contention + */ + msdu = ath12k_dp_ppeds_tx_release_desc_nolock(dp, tx_desc, + ATH12K_PPEDS_DEFAULT_POOL_ID); + buf_rel_source = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, + tx_status->info0); + if (unlikely(buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) { + status_desc = ((void *)tx_status) + HTT_TX_WBM_COMP_STATUS_OFFSET; + htt_status = u32_get_bits(status_desc->info0, + HTT_TX_WBM_COMP_INFO0_STATUS); + if (htt_status != HAL_WBM_REL_HTT_TX_COMP_STATUS_OK && + !ab->stats_disable) { + ab->ppeds_stats.fw2wbm_pkt_drops++; + } + dev_kfree_skb_any(msdu); + ath12k_warn(ab, "ath12k: Frame received from unexpected source %d status %d!\n", + buf_rel_source, htt_status); + continue; } - ath12k_hal_srng_access_end(ab, status_ring); + /* is skb is being reused, avoid freeing it */ + if (!msdu) + continue; - spin_unlock_bh(&status_ring->lock); + if (skb_has_frag_list(msdu)) { + kfree_skb_list(skb_shinfo(msdu)->frag_list); + skb_shinfo(msdu)->frag_list = NULL; + } - while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { - struct hal_wbm_completion_ring_tx *tx_status; +#ifdef CONFIG_MAC80211_SFE_SUPPORT + if (likely(msdu->is_from_recycler)) { + __skb_queue_head(&free_list_head, msdu); + } else { + dev_kfree_skb(msdu); + } +#else + dev_kfree_skb(msdu); +#endif + + work_done++; + } + spin_unlock_bh(&dp->ppeds_tx_desc_lock[ATH12K_PPEDS_DEFAULT_POOL_ID]); + dev_kfree_skb_list_fast(&free_list_head); + + return work_done; +} +#endif + +int ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id, + int budget) +{ + struct ath12k *ar; + struct ath12k_dp *dp = &ab->dp; + int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; + struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; + struct ath12k_tx_desc_info *tx_desc = NULL; + struct list_head desc_free_list, *cur; + struct sk_buff *msdu, *skb_ext_desc; + struct ath12k_skb_cb *skb_cb; + struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; + u8 mac_id; + u64 desc_va; + struct ath12k_vif *ahvif; u32 desc_id; + u8 flags = 0; + int valid_entries; + int orig_budget = budget; + struct hal_wbm_completion_ring_tx *tx_status; + ktime_t timestamp; + enum hal_wbm_rel_src_module buf_rel_source; + enum hal_wbm_tqm_rel_reason rel_status; + struct sk_buff_head free_list_head; + int recycler_fast_xmit; + + + INIT_LIST_HEAD(&desc_free_list); + + ath12k_hal_srng_access_dst_ring_begin_nolock(ab, status_ring); + + valid_entries = ath12k_hal_srng_dst_num_free(ab, status_ring, false); + if (!valid_entries) { + ath12k_hal_srng_access_dst_ring_end_nolock(status_ring); + return 0; + } + + if (valid_entries > budget) + valid_entries = budget; - tx_ring->tx_status_tail = - ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); - tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; - ath12k_dp_tx_status_parse(ab, tx_status, &ts); + ath12k_hal_srng_dst_invalidate_entry(ab, status_ring, valid_entries); + skb_queue_head_init(&free_list_head); - if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { + while (budget && (tx_status = (struct hal_wbm_completion_ring_tx *)ath12k_hal_srng_dst_get_next_cache_entry(ab, status_ring))) { + budget--; + if (!ath12k_dp_tx_completion_valid((struct hal_wbm_release_ring *)tx_status)) + continue; + + if (likely(HAL_WBM_COMPL_TX_INFO0_CC_DONE & tx_status->info0)) { /* HW done cookie conversion */ - desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | - le32_to_cpu(tx_status->buf_va_lo)); + desc_va = ((u64)tx_status->buf_va_hi << 32 | + tx_status->buf_va_lo); tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); } else { /* SW does cookie conversion to VA */ - desc_id = le32_get_bits(tx_status->buf_va_hi, + desc_id = u32_get_bits(tx_status->buf_va_hi, BUFFER_ADDR_INFO1_SW_COOKIE); tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); } - if (!tx_desc) { + if (unlikely(!tx_desc)) { ath12k_warn(ab, "unable to retrieve tx_desc!"); continue; } msdu = tx_desc->skb; mac_id = tx_desc->mac_id; + recycler_fast_xmit = tx_desc->recycler_fast_xmit; + skb_ext_desc = tx_desc->skb_ext_desc; + timestamp = tx_desc->timestamp; /* Release descriptor as soon as extracting necessary info * to reduce contention */ - ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); - if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { + list_add_tail(&tx_desc->list, &desc_free_list); + + if (unlikely(!msdu)) { + ab->soc_stats.null_tx_complete[tx_ring->tcl_data_ring_id]++; + + ath12k_err_dump(ab, "Null msdu\n", "Tx compl Desc: ", tx_status, + sizeof(*tx_status), NULL); + + if (ath12k_debug_critical) + BUG_ON(1); + + continue; + } + + prefetch(msdu); + prefetch( (u8 *) msdu + 64); + + /* Find the HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE value */ + buf_rel_source = tx_status->info0 & HAL_WBM_RELEASE_INFO0_REL_SRC_MASK; + ab->soc_stats.tx_wbm_rel_source[buf_rel_source]++; + + rel_status = FIELD_GET(HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON, + tx_status->info0); + ab->soc_stats.tqm_rel_reason[rel_status]++; + + if (unlikely(buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) { ath12k_dp_tx_process_htt_tx_complete(ab, (void *)tx_status, mac_id, msdu, - tx_ring); + tx_ring, + skb_ext_desc, + timestamp); continue; } - ar = ab->pdevs[mac_id].ar; - if (atomic_dec_and_test(&ar->dp.num_tx_pending)) - wake_up(&ar->dp.tx_empty_waitq); + ath12k_dp_tx_decrement(ar); + + if (unlikely(WARN_ON_ONCE(buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM))) { + /* Must not happen */ + continue; + } + + skb_cb = (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(msdu)->driver_data; + flags = skb_cb->flags; + dma_unmap_single_attrs(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + if (unlikely(skb_ext_desc)) { + dma_unmap_single_attrs(ab->dev, skb_cb->paddr_ext_desc, + skb_ext_desc->len, + DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); + dev_kfree_skb_any(skb_ext_desc); + } + /* Free skb here if stats is disabled */ + if (ab->stats_disable && !(flags & ATH12K_SKB_TX_STATUS)) { + ar->ab->soc_stats.tx_completed[tx_ring->tcl_data_ring_id]++; + + if (skb_cb->vif) { + ahvif = (void *)skb_cb->vif->drv_priv; + if (ahvif->links_map & BIT(skb_cb->link_id)) { + if (ahvif->link[skb_cb->link_id]) + ahvif->link[skb_cb->link_id]->link_stats.tx_completed++; + } else { + ath12k_warn(ab, + "invalid linkid 0x%X in tx completion handler for linkmap %lu\n", + skb_cb->link_id, + ahvif->links_map); + } + } + + if (unlikely(msdu->destructor)) { + msdu->wifi_acked_valid = 1; + msdu->wifi_acked = rel_status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED; + } + if (unlikely(skb_has_frag_list(msdu))) { + kfree_skb_list(skb_shinfo(msdu)->frag_list); + skb_shinfo(msdu)->frag_list = NULL; + } + if (likely(recycler_fast_xmit)) { + __skb_queue_head(&free_list_head, msdu); + } else { + dev_kfree_skb(msdu); + } + } else { - ath12k_dp_tx_complete_msdu(ar, msdu, &ts); + ath12k_dp_tx_complete_msdu(ar, msdu, (struct hal_wbm_release_ring *)tx_status, + buf_rel_source, + tx_ring->tcl_data_ring_id, timestamp); } } + spin_lock_bh(&dp->tx_desc_lock[ring_id]); + list_for_each(cur, &desc_free_list) { + tx_desc = list_entry(cur, struct ath12k_tx_desc_info, list); + tx_desc->skb = NULL; + tx_desc->skb_ext_desc = NULL; + tx_desc->in_use = false; + } + list_splice_tail(&desc_free_list, &dp->tx_desc_free_list[ring_id]); + spin_unlock_bh(&dp->tx_desc_lock[ring_id]); + + ath12k_hal_srng_access_dst_ring_end_nolock(status_ring); + return (orig_budget - budget); +} + static int ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, int mac_id, u32 ring_id, @@ -623,6 +1704,10 @@ { int ret = 0; + if ((ring_type == HAL_TX_MONITOR_BUF || ring_type == HAL_TX_MONITOR_DST) && + !ab->hw_params->supports_tx_monitor) + return ret; + switch (ring_type) { case HAL_RXDMA_BUF: /* for some targets, host fills rx buffer to fw and fw fills to @@ -650,7 +1735,7 @@ *htt_ring_type = HTT_HW_TO_SW_RING; break; case HAL_RXDMA_MONITOR_BUF: - *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; + *htt_ring_id = HTT_RX_MON_HOST2MON_BUF_RING; *htt_ring_type = HTT_SW_TO_HW_RING; break; case HAL_RXDMA_MONITOR_STATUS: @@ -658,13 +1743,9 @@ *htt_ring_type = HTT_SW_TO_HW_RING; break; case HAL_RXDMA_MONITOR_DST: - *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; + *htt_ring_id = HTT_RX_MON_MON2HOST_DEST_RING; *htt_ring_type = HTT_HW_TO_SW_RING; break; - case HAL_RXDMA_MONITOR_DESC: - *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; - *htt_ring_type = HTT_SW_TO_HW_RING; - break; case HAL_TX_MONITOR_BUF: *htt_ring_id = HTT_TX_MON_HOST2MON_BUF_RING; *htt_ring_type = HTT_SW_TO_HW_RING; @@ -815,7 +1896,16 @@ skb_put(skb, len); cmd = (struct htt_ver_req_cmd *)skb->data; cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, - HTT_VER_REQ_INFO_MSG_ID); + HTT_OPTION_TAG); + + if (!ath12k_ftm_mode) { + cmd->tcl_metadata_version = u32_encode_bits(HTT_TAG_TCL_METADATA_VERSION, + HTT_OPTION_TAG); + cmd->tcl_metadata_version |= u32_encode_bits(HTT_TCL_METADATA_VER_SZ, + HTT_OPTION_LEN); + cmd->tcl_metadata_version |= u32_encode_bits(HTT_OPTION_TCL_METADATA_VER_V2, + HTT_OPTION_VALUE); + } ret = ath12k_htc_send(&ab->htc, dp->eid, skb); if (ret) { @@ -860,7 +1950,7 @@ cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, HTT_PPDU_STATS_CFG_MSG_TYPE); - pdev_mask = 1 << (i + 1); + pdev_mask = DP_SW2HW_MACID(ar->pdev_idx) + i; cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); @@ -922,13 +2012,27 @@ HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID); + cmd->info0 |= u32_encode_bits(tlv_filter->drop_threshold_valid, + HTT_RX_RING_SELECTION_CFG_CMD_DROP_THRES_VAL); + if (!tlv_filter->rxmon_disable) + cmd->info0 |= u32_encode_bits(true, + HTT_RX_RING_SELECTION_CFG_CMD_RXMON_GCONF_EN); + cmd->info1 = le32_encode_bits(rx_buf_size, HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); + cmd->info1 |= u32_encode_bits(tlv_filter->conf_len_mgmt, + HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); + cmd->info1 |= u32_encode_bits(tlv_filter->conf_len_ctrl, + HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); + cmd->info1 |= u32_encode_bits(tlv_filter->conf_len_data, + HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); + cmd->info2 = tlv_filter->info0; + cmd->info3 = tlv_filter->info1; if (tlv_filter->offset_valid) { cmd->rx_packet_offset = @@ -960,6 +2064,25 @@ HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); } + if (tlv_filter->rx_mpdu_start_wmask > 0 && + tlv_filter->rx_msdu_end_wmask > 0) { + cmd->info2 |= + u32_encode_bits(true, + HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET); + cmd->rx_mpdu_start_word_mask = + u32_encode_bits(tlv_filter->rx_mpdu_start_wmask, + HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK); + /* mpdu_end is not used for any hardwares so far + * please assign it in future if any chip is + * using through hal ops + */ + cmd->rx_mpdu_end_word_mask = + u32_encode_bits(tlv_filter->rx_mpdu_end_wmask, + HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK); + cmd->rx_msdu_end_word_mask = + u32_encode_bits(tlv_filter->rx_msdu_end_wmask, + HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK); + } ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); if (ret) goto err_free; @@ -973,6 +2096,49 @@ } int +ath12k_dp_tx_htt_h2t_vdev_stats_ol_req(struct ath12k *ar, u64 reset_bitmask) +{ + struct ath12k_base *ab = ar->ab; + struct htt_h2t_msg_type_vdev_txrx_stats_req *cmd; + struct ath12k_dp *dp = &ab->dp; + struct sk_buff *skb; + int len = sizeof(*cmd), ret; + + skb = ath12k_htc_alloc_skb(ab, len); + if (!skb) + return -ENOMEM; + + skb_put(skb, len); + cmd = (struct htt_h2t_msg_type_vdev_txrx_stats_req *)skb->data; + memset(cmd, 0, sizeof(*cmd)); + cmd->hdr = FIELD_PREP(HTT_H2T_VDEV_TXRX_HDR_MSG_TYPE, + HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG); + cmd->hdr |= FIELD_PREP(HTT_H2T_VDEV_TXRX_HDR_PDEV_ID, + ar->pdev->pdev_id); + cmd->hdr |= FIELD_PREP(HTT_H2T_VDEV_TXRX_HDR_ENABLE, true); + + /* Periodic interval is calculated as 1 units = 8 ms. + * Ex: 125 -> 1000 ms + */ + cmd->hdr |= FIELD_PREP(HTT_H2T_VDEV_TXRX_HDR_INTERVAL, + (ATH12K_STATS_TIMER_DUR_1SEC >> 3)); + cmd->hdr |= FIELD_PREP(HTT_H2T_VDEV_TXRX_HDR_RESET_STATS, true); + cmd->vdev_id_lo_bitmask = (reset_bitmask & HTT_H2T_VDEV_TXRX_LO_BITMASK); + cmd->vdev_id_hi_bitmask = ((reset_bitmask & + HTT_H2T_VDEV_TXRX_HI_BITMASK) >> 32); + + ret = ath12k_htc_send(&ab->htc, dp->eid, skb); + if (ret) { + ath12k_warn(ab, "failed to send htt type vdev stats offload request: %d", + ret); + dev_kfree_skb_any(skb); + return ret; + } + + return 0; +} + +int ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, struct htt_ext_stats_cfg_params *cfg_params, u64 cookie) @@ -1020,13 +2186,15 @@ struct ath12k_base *ab = ar->ab; int ret; + if (ab->hw_params->supports_tx_monitor) { ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); if (ret) { ath12k_err(ab, "failed to setup tx monitor filter %d\n", ret); return ret; } + } - ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); + ret = ath12k_dp_tx_htt_rx_monitor_mode_ring_config(ar, reset); if (ret) { ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); return ret; @@ -1038,15 +2206,13 @@ int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) { struct ath12k_base *ab = ar->ab; - struct ath12k_dp *dp = &ab->dp; struct htt_rx_ring_tlv_filter tlv_filter = {0}; - int ret, ring_id; + int ret = 0, ring_id = 0, i; - ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; tlv_filter.offset_valid = false; if (!reset) { - tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; + tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING; tlv_filter.pkt_filter_flags0 = HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; @@ -1061,11 +2227,38 @@ HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | HTT_RX_MON_FP_DATA_FILTER_FLASG3 | HTT_RX_MON_MO_DATA_FILTER_FLASG3; + + tlv_filter.drop_threshold_valid = true; + tlv_filter.info0 = + u32_encode_bits(HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE, + HTT_RX_TLV_FILTER_INFO0_RX_DROP_THRESHOLD); + tlv_filter.info0 |= + u32_encode_bits(true, + HTT_RX_TLV_FILTER_INFO0_EN_MSDU_MPDU_LOG_MGMT_TYPE); + tlv_filter.info0 |= + u32_encode_bits(true, + HTT_RX_TLV_FILTER_INFO0_EN_MSDU_MPDU_LOG_CTRL_TYPE); + tlv_filter.info0 |= + u32_encode_bits(true, + HTT_RX_TLV_FILTER_INFO0_EN_MSDU_MPDU_LOG_DATA_TYPE); + + tlv_filter.conf_len_ctrl = HTT_RX_RING_DEFAULT_DMA_LENGTH; + tlv_filter.conf_len_mgmt = HTT_RX_RING_DEFAULT_DMA_LENGTH; + tlv_filter.conf_len_data = HTT_RX_RING_DEFAULT_DMA_LENGTH; + + tlv_filter.info1 = + FIELD_PREP(HTT_RX_TLV_FILTER_INFO1_EN_RX_TLV_PKT_OFFSET, + true); + tlv_filter.info1 |= + FIELD_PREP(HTT_RX_TLV_FILTER_INFO1_RX_PKT_TLV_OFFSET, + HTT_RX_RING_PKT_TLV_OFFSET); } - if (ab->hw_params->rxdma1_enable) { - ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0, - HAL_RXDMA_MONITOR_BUF, + for (i = 0; i < ar->ab->hw_params->num_rxmda_per_pdev; i++) { + ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; + + ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, ar->dp.mac_id + i, + HAL_RXDMA_MONITOR_DST, DP_RXDMA_REFILL_RING_SIZE, &tlv_filter); if (ret) { diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/dp_tx.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_tx.h --- linux-6.4/drivers/net/wireless/ath/ath12k/dp_tx.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/dp_tx.h 2024-04-19 16:04:28.953735667 +0200 @@ -15,11 +15,217 @@ int ack_rssi; }; -int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab); -int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif, - struct sk_buff *skb); -void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id); +/* htt_tx_msdu_desc_ext + * + * valid_pwr + * if set, tx pwr spec is valid + * + * valid_mcs_mask + * if set, tx MCS mask is valid + * + * valid_nss_mask + * if set, tx Nss mask is valid + * + * valid_preamble_type + * if set, tx preamble spec is valid + * + * valid_retries + * if set, tx retries spec is valid + * + * valid_bw_info + * if set, tx dyn_bw and bw_mask are valid + * + * valid_guard_interval + * if set, tx guard intv spec is valid + * + * valid_chainmask + * if set, tx chainmask is valid + * + * valid_encrypt_type + * if set, encrypt type is valid + * + * valid_key_flags + * if set, key flags is valid + * + * valid_expire_tsf + * if set, tx expire TSF spec is valid + * + * valid_chanfreq + * if set, chanfreq is valid + * + * is_dsrc + * if set, MSDU is a DSRC frame + * + * guard_interval + * 0.4us, 0.8us, 1.6us, 3.2us + * + * encrypt_type + * 0 = NO_ENCRYPT, + * 1 = ENCRYPT, + * 2 ~ 3 - Reserved + * + * retry_limit + * Specify the maximum number of transmissions, including the + * initial transmission, to attempt before giving up if no ack + * is received. + * If the tx rate is specified, then all retries shall use the + * same rate as the initial transmission. + * If no tx rate is specified, the target can choose whether to + * retain the original rate during the retransmissions, or to + * fall back to a more robust rate. + * + * use_dcm_11ax + * If set, Use Dual subcarrier modulation. + * Valid only for 11ax preamble types HE_SU + * and HE_EXT_SU + * + * ltf_subtype_11ax + * Takes enum values of htt_11ax_ltf_subtype_t + * Valid only for 11ax preamble types HE_SU + * and HE_EXT_SU + * + * dyn_bw + * 0 = static bw, 1 = dynamic bw + * + * bw_mask + * Valid only if dyn_bw == 0 (static bw). + * + * host_tx_desc_pool + * If set, Firmware allocates tx_descriptors + * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead + * of WAL_BUFFERID_TX_TCL_DATA_EXP. + * Use cases: + * Any time firmware uses TQM-BYPASS for Data + * TID, firmware expect host to set this bit. + * + * power + * unit of the power field is 0.5 dbm + * signed value ranging from -64dbm to 63.5 dbm + * + * mcs_mask + * mcs bit mask of 0 ~ 11 + * Setting more than one MCS isn't currently + * supported by the target (but is supported + * in the interface in case in the future + * the target supports specifications of + * a limited set of MCS values. + * + * nss_mask + * Nss bit mask 0 ~ 7 + * Setting more than one Nss isn't currently + * supported by the target (but is supported + * in the interface in case in the future + * the target supports specifications of + * a limited set of Nss values. + * + * pream_type + * Preamble types + * + * update_peer_cache + * When set these custom values will be + * used for all packets, until the next + * update via this ext header. + * This is to make sure not all packets + * need to include this header. + * + * chain_mask + * specify which chains to transmit from + * + * key_flags + * Key Index and related flags - used in mesh mode + * + * chanfreq + * Channel frequency: This identifies the desired channel + * frequency (in MHz) for tx frames. This is used by FW to help + * determine when it is safe to transmit or drop frames for + * off-channel operation. + * The default value of zero indicates to FW that the corresponding + * VDEV's home channel (if there is one) is the desired channel + * frequency. + * + * expire_tsf_lo + * tx expiry time (TSF) LSBs + * + * expire_tsf_hi + * tx expiry time (TSF) MSBs + * + * learning_frame + * When this flag is set, this frame will be dropped by FW + * rather than being enqueued to the Transmit Queue Manager (TQM) HW. + * + * send_as_standalone + * This will indicate if the msdu needs to be sent as a singleton PPDU, + * i.e. with no A-MSDU or A-MPDU aggregation. + * The scope is extended to other use-cases. + * + * is_host_opaque_valid + * set this bit to 1 if the host_opaque_cookie is populated + * with valid information. + * + * host_opaque_cookie + * Host opaque cookie for special frames + */ + +struct htt_tx_msdu_desc_ext { + u32 + valid_pwr : 1, + valid_mcs_mask : 1, + valid_nss_mask : 1, + valid_preamble_type : 1, + valid_retries : 1, + valid_bw_info : 1, + valid_guard_interval : 1, + valid_chainmask : 1, + valid_encrypt_type : 1, + valid_key_flags : 1, + valid_expire_tsf : 1, + valid_chanfreq : 1, + is_dsrc : 1, + guard_interval : 2, + encrypt_type : 2, + retry_limit : 4, + use_dcm_11ax : 1, + ltf_subtype_11ax : 2, + dyn_bw : 1, + bw_mask : 6, + host_tx_desc_pool : 1; + u32 + power : 8, + mcs_mask : 12, + nss_mask : 8, + pream_type : 3, + update_peer_cache : 1; + u32 + chain_mask : 8, + key_flags : 8, + chanfreq : 16; + + u32 expire_tsf_lo; + u32 expire_tsf_hi; + u32 + learning_frame : 1, + send_as_standalone : 1, + is_host_opaque_valid : 1, + rsvd0 : 29; + u32 + host_opaque_cookie : 16, + rsvd1 : 16; +} __packed; + +void ath12k_dp_tx_update_txcompl(struct ath12k *ar, struct hal_tx_status *ts); +int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab); +int ath12k_dp_tx(struct ath12k *ar, struct ath12k_link_vif *arvif, + struct ath12k_sta *ahsta, struct sk_buff *skb, + bool gsn_valid, int mcbc_gsn); +int ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id, + int tx_comp_budget); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +int ath12k_ppeds_tx_completion_handler(struct ath12k_base *ab, int ring_id); +struct ath12k_ppeds_tx_desc_info * +ath12k_dp_ppeds_tx_assign_desc_nolock(struct ath12k_dp *dp, + u8 ring_id); +#endif int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask); int ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, @@ -38,4 +244,6 @@ struct htt_tx_ring_tlv_filter *htt_tlv_filter); int ath12k_dp_tx_htt_tx_monitor_mode_ring_config(struct ath12k *ar, bool reset); int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset); +int ath12k_dp_tx_htt_h2t_vdev_stats_ol_req(struct ath12k *ar, u64 reset_bitmask); +int ath12k_dp_tx_direct(struct ath12k_link_vif *arvif, struct sk_buff *skb); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hal.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal.c --- linux-6.4/drivers/net/wireless/ath/ath12k/hal.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal.c 2024-03-18 14:40:14.851741333 +0100 @@ -4,11 +4,17 @@ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include +#include #include "hal_tx.h" #include "hal_rx.h" #include "debug.h" #include "hal_desc.h" #include "hif.h" +#include "dp_rx.h" + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#define RING_HALT_TIMEOUT 10 +#endif static const struct hal_srng_config hw_srng_config_template[] = { /* TODO: max_rings can populated by querying HW capabilities */ @@ -57,6 +63,14 @@ .ring_dir = HAL_SRNG_DIR_DST, .max_size = HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE, }, + [HAL_REO2PPE] = { + .start_ring_id = HAL_SRNG_RING_ID_REO2PPE, + .max_rings = 1, + .entry_size = sizeof(struct hal_reo_dest_ring) >> 2, + .mac_type = ATH12K_HAL_SRNG_UMAC, + .ring_dir = HAL_SRNG_DIR_DST, + .max_size = HAL_REO2PPE_RING_BASE_MSB_RING_SIZE, + }, [HAL_TCL_DATA] = { .start_ring_id = HAL_SRNG_RING_ID_SW2TCL1, .max_rings = 6, @@ -147,7 +161,7 @@ .max_size = HAL_RXDMA_RING_MAX_SIZE_BE, }, [HAL_RXDMA_MONITOR_BUF] = { - .start_ring_id = HAL_SRNG_SW2RXMON_BUF0, + .start_ring_id = HAL_SRNG_SW2RXMON_BUF0, /* HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, */ .max_rings = 1, .entry_size = sizeof(struct hal_mon_buf_ring) >> 2, .mac_type = ATH12K_HAL_SRNG_PMAC, @@ -168,20 +182,20 @@ .start_ring_id = HAL_SRNG_RING_ID_PPE2TCL1, .max_rings = 1, .entry_size = sizeof(struct hal_tcl_entrance_from_ppe_ring) >> 2, - .mac_type = ATH12K_HAL_SRNG_PMAC, + .mac_type = ATH12K_HAL_SRNG_UMAC, .ring_dir = HAL_SRNG_DIR_SRC, - .max_size = HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE, + .max_size = HAL_PPE2TCL_RING_BASE_MSB_RING_SIZE, }, [HAL_PPE_RELEASE] = { .start_ring_id = HAL_SRNG_RING_ID_WBM_PPE_RELEASE, .max_rings = 1, .entry_size = sizeof(struct hal_wbm_release_ring) >> 2, - .mac_type = ATH12K_HAL_SRNG_PMAC, + .mac_type = ATH12K_HAL_SRNG_UMAC, .ring_dir = HAL_SRNG_DIR_SRC, .max_size = HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE, }, [HAL_TX_MONITOR_BUF] = { - .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, + .start_ring_id = HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, .max_rings = 1, .entry_size = sizeof(struct hal_mon_buf_ring) >> 2, .mac_type = ATH12K_HAL_SRNG_PMAC, @@ -394,9 +408,16 @@ RX_MSDU_END_INFO5_TID); } +static u8 ath12k_hw_qcn9274_rx_desc_get_msdu_intra_bss_bit(struct hal_rx_desc *desc) +{ + /* TODO - msdu_end info9 */ + return 0; +} + static u16 ath12k_hw_qcn9274_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) { - return __le16_to_cpu(desc->u.qcn9274.mpdu_start.sw_peer_id); + return le16_get_bits(desc->u.qcn9274.mpdu_start.sw_peer_id, + RX_MPDU_START_SW_PEER_ID_PEER); } static void ath12k_hw_qcn9274_rx_desc_copy_end_tlv(struct hal_rx_desc *fdesc, @@ -447,7 +468,7 @@ return desc->u.qcn9274.mpdu_start.addr2; } -static bool ath12k_hw_qcn9274_rx_desc_is_mcbc(struct hal_rx_desc *desc) +static bool ath12k_hw_qcn9274_rx_desc_is_da_mcbc(struct hal_rx_desc *desc) { return __le32_to_cpu(desc->u.qcn9274.mpdu_start.info6) & RX_MPDU_START_INFO6_MCAST_BCAST; @@ -511,9 +532,91 @@ crypto_hdr[7] = HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.qcn9274.mpdu_start.pn[1]); } -static u16 ath12k_hw_qcn9274_rx_desc_get_mpdu_frame_ctl(struct hal_rx_desc *desc) +static u8 ath12k_hal_qcn9274_rx_desc_get_ip_valid(struct hal_rx_desc *desc) +{ + bool ipv4, ipv6; + ipv4 = FIELD_GET(RX_MSDU_END_INFO11_IPV4, + __le32_to_cpu(desc->u.qcn9274.msdu_end.info11)); + ipv6 = FIELD_GET(RX_MSDU_END_INFO11_IPV6, + __le32_to_cpu(desc->u.qcn9274.msdu_end.info11)); + return (ipv4 || ipv6); +} + +#define MPDU_START_WMASK 0x7FC +#define MSDU_END_WMASK 0x13441 + +static inline u16 ath12k_hal_rx_mpdu_start_wmask_get(void) +{ + return MPDU_START_WMASK; +} + +static inline u32 ath12k_hal_rx_msdu_end_wmask_get(void) +{ + return MSDU_END_WMASK; +} + +static u8 ath12k_hw_qcn9274_rx_desc_get_msdu_src_link(struct hal_rx_desc *desc) +{ + return le64_get_bits(desc->u.qcn9274.msdu_end.msdu_end_tag, + RX_MSDU_END_64_TLV_SRC_LINK_ID); +} + +#define PMM_REG_OFFSET 4 + +static void ath12k_hal_get_tsf_reg(u8 mac_id, enum hal_scratch_reg_enum *tsf_enum_low, + enum hal_scratch_reg_enum *tsf_enum_hi) +{ + if (!mac_id) { + *tsf_enum_low = PMM_MAC0_TSF2_OFFSET_LO_US; + *tsf_enum_hi = PMM_MAC0_TSF2_OFFSET_HI_US; + } else if (mac_id == 1) { + *tsf_enum_low = PMM_MAC1_TSF2_OFFSET_LO_US; + *tsf_enum_hi = PMM_MAC1_TSF2_OFFSET_HI_US; + } +} + +static void ath12k_hal_qcn9274_get_tsf2_scratch_reg(struct ath12k_base *ab, + u8 mac_id, u64 *value) +{ + enum hal_scratch_reg_enum enum_lo, enum_hi; + u32 offset_lo, offset_hi; + + ath12k_hal_get_tsf_reg(mac_id, &enum_lo, &enum_hi); + + if (ab->hif.ops->pmm_read32) { + offset_lo = ath12k_hif_pmm_read32(ab, ATH12K_PPT_ADDR_OFFSET(enum_lo)); + offset_hi = ath12k_hif_pmm_read32(ab, ATH12K_PPT_ADDR_OFFSET(enum_hi)); + } else if (ab->hw_rev == ATH12K_HW_QCN6432_HW10) { + offset_lo = ath12k_hif_cmem_read32(ab, PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(enum_lo)); + offset_hi = ath12k_hif_cmem_read32(ab, PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(enum_hi)); + } else { + offset_lo = ath12k_hif_read32(ab, PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(enum_lo)); + offset_hi = ath12k_hif_read32(ab, PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(enum_hi)); + } + + *value = ((u64)(offset_hi) << 32 | offset_lo); +} + +static void ath12k_hal_qcn9274_get_tqm_scratch_reg(struct ath12k_base *ab, u64 *value) { - return __le16_to_cpu(desc->u.qcn9274.mpdu_start.frame_ctrl); + u32 offset_lo, offset_hi; + + if (ab->hif.ops->pmm_read32) { + offset_lo = ath12k_hif_pmm_read32(ab, ATH12K_PPT_ADDR_OFFSET(PMM_TQM_CLOCK_OFFSET_LO_US)); + offset_hi = ath12k_hif_pmm_read32(ab, ATH12K_PPT_ADDR_OFFSET(PMM_TQM_CLOCK_OFFSET_HI_US)); + } else if (ab->hw_rev == ATH12K_HW_QCN6432_HW10) { + offset_lo = ath12k_hif_cmem_read32(ab, + PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(PMM_TQM_CLOCK_OFFSET_LO_US)); + offset_hi = ath12k_hif_cmem_read32(ab, + PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(PMM_TQM_CLOCK_OFFSET_HI_US)); + } else { + offset_lo = ath12k_hif_read32(ab, + PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(PMM_TQM_CLOCK_OFFSET_LO_US)); + offset_hi = ath12k_hif_read32(ab, + PMM_REG_BASE_QCN9224 + ATH12K_PPT_ADDR_OFFSET(PMM_TQM_CLOCK_OFFSET_HI_US)); + } + + *value = ((u64)(offset_hi) << 32 | offset_lo); } static int ath12k_hal_srng_create_config_qcn9274(struct ath12k_base *ab) @@ -551,10 +654,16 @@ s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB(ab); s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; + s = &hal->srng_config[HAL_REO2PPE]; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO2PPE_RING_BASE_LSB(ab); + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO2PPE_HP; + s->reg_size[0] = HAL_REO2_RING_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab); + s->reg_size[1] = HAL_REO2_RING_HP - HAL_REO1_RING_HP; + s = &hal->srng_config[HAL_TCL_DATA]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; - s->reg_size[0] = HAL_TCL2_RING_BASE_LSB - HAL_TCL1_RING_BASE_LSB; + s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab); s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; s = &hal->srng_config[HAL_TCL_CMD]; @@ -566,29 +675,29 @@ s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; s = &hal->srng_config[HAL_CE_SRC]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP; - s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG - - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; - s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG - - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB; + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP; + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); s = &hal->srng_config[HAL_CE_DST]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP; - s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB; + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP; + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); s = &hal->srng_config[HAL_CE_DST_STATUS]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_STATUS_RING_HP; - s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP; + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); s = &hal->srng_config[HAL_WBM_IDLE_LINK]; s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); @@ -615,14 +724,9 @@ * RXDMA_RX_MONITOR_BUF, TX_MONITOR_BUF, TX_MONITOR_DST, SW2RXDMA */ s = &hal->srng_config[HAL_PPE2TCL]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_BASE_LSB; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_BASE_LSB(ab); s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_PPE2TCL1_RING_HP; - s = &hal->srng_config[HAL_PPE_RELEASE]; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + - HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab); - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_PPE_RELEASE_RING_HP; - return 0; } @@ -680,6 +784,59 @@ return errmap; } +static void ath12k_hw_qcn9274_get_rx_first_last_msdu(struct hal_rx_desc *desc, + struct ath12k_dp_rx_info *rx_info) +{ + rx_info->is_first_msdu = !!le16_get_bits(desc->u.qcn9274.msdu_end.info5, + RX_MSDU_END_INFO5_FIRST_MSDU); + rx_info->is_last_msdu = !!le16_get_bits(desc->u.qcn9274.msdu_end.info5, + RX_MSDU_END_INFO5_LAST_MSDU); +} + +static void ath12k_hw_qcn9274_get_rx_msdulen_l3pad(struct hal_rx_desc *desc, + struct ath12k_dp_rx_info *rx_info) +{ + + rx_info->msdu_done = !!le32_get_bits(desc->u.qcn9274.msdu_end.info14, + RX_MSDU_END_INFO14_MSDU_DONE); + rx_info->msdu_len = le32_get_bits(desc->u.qcn9274.msdu_end.info10, + RX_MSDU_END_INFO10_MSDU_LENGTH); + rx_info->l3_pad_bytes = le16_get_bits(desc->u.qcn9274.msdu_end.info5, + RX_MSDU_END_INFO5_L3_HDR_PADDING); +} + +static void ath12k_hw_qcn9274_get_rx_desc_info(struct hal_rx_desc *desc, + struct ath12k_dp_rx_info *rx_info) +{ + __le32 info12 = desc->u.qcn9274.msdu_end.info12; + __le32 info13 = desc->u.qcn9274.msdu_end.info13; + __le32 info11 = desc->u.qcn9274.msdu_end.info11; + + rx_info->pkt_type = le32_get_bits(info12, RX_MSDU_END_INFO12_PKT_TYPE); + rx_info->sgi = le32_get_bits(info12, RX_MSDU_END_INFO12_SGI); + rx_info->rate_mcs = le32_get_bits(info12, RX_MSDU_END_INFO12_RATE_MCS); + rx_info->bw = le32_get_bits(info12, RX_MSDU_END_INFO12_RECV_BW); + rx_info->nss = hweight8(le32_get_bits(info12, RX_MSDU_END_INFO12_MIMO_SS_BITMAP)); + rx_info->phy_meta_data = __le32_to_cpu(desc->u.qcn9274.msdu_end.phy_meta_data); + + rx_info->ip_csum_fail = !!le32_get_bits(info13, RX_MSDU_END_INFO13_IP_CKSUM_FAIL); + rx_info->l4_csum_fail = !!le32_get_bits(info13, RX_MSDU_END_INFO13_TCP_UDP_CKSUM_FAIL); + rx_info->ip_is_valid = (le32_get_bits(__le32_to_cpu(info11), RX_MSDU_END_INFO11_IPV4) || + le32_get_bits(__le32_to_cpu(info11), RX_MSDU_END_INFO11_IPV6)); + + rx_info->decap_type = le32_get_bits(info11, RX_MSDU_END_INFO11_DECAP_FORMAT); + + rx_info->is_mcbc = ((!!le16_get_bits(desc->u.qcn9274.msdu_end.info5, + RX_MSDU_END_INFO5_FIRST_MSDU)) && + (__le32_to_cpu(desc->u.qcn9274.mpdu_start.info6) & + RX_MPDU_START_INFO6_MCAST_BCAST)); + + rx_info->peer_id = le16_get_bits(desc->u.qcn9274.mpdu_start.sw_peer_id, + RX_MPDU_START_SW_PEER_ID_PEER); + rx_info->tid = le16_get_bits(desc->u.qcn9274.msdu_end.info5, + RX_MSDU_END_INFO5_TID); +} + const struct hal_ops hal_qcn9274_ops = { .rx_desc_get_first_msdu = ath12k_hw_qcn9274_rx_desc_get_first_msdu, .rx_desc_get_last_msdu = ath12k_hw_qcn9274_rx_desc_get_last_msdu, @@ -706,12 +863,12 @@ .rx_desc_get_msdu_payload = ath12k_hw_qcn9274_rx_desc_get_msdu_payload, .rx_desc_get_mpdu_start_offset = ath12k_hw_qcn9274_rx_desc_get_mpdu_start_offset, .rx_desc_get_msdu_end_offset = ath12k_hw_qcn9274_rx_desc_get_msdu_end_offset, + .rx_desc_get_msdu_intra_bss_bit = ath12k_hw_qcn9274_rx_desc_get_msdu_intra_bss_bit, .rx_desc_mac_addr2_valid = ath12k_hw_qcn9274_rx_desc_mac_addr2_valid, .rx_desc_mpdu_start_addr2 = ath12k_hw_qcn9274_rx_desc_mpdu_start_addr2, - .rx_desc_is_mcbc = ath12k_hw_qcn9274_rx_desc_is_mcbc, + .rx_desc_is_da_mcbc = ath12k_hw_qcn9274_rx_desc_is_da_mcbc, .rx_desc_get_dot11_hdr = ath12k_hw_qcn9274_rx_desc_get_dot11_hdr, .rx_desc_get_crypto_header = ath12k_hw_qcn9274_rx_desc_get_crypto_hdr, - .rx_desc_get_mpdu_frame_ctl = ath12k_hw_qcn9274_rx_desc_get_mpdu_frame_ctl, .create_srng_config = ath12k_hal_srng_create_config_qcn9274, .tcl_to_wbm_rbm_map = ath12k_hal_qcn9274_tcl_to_wbm_rbm_map, .dp_rx_h_msdu_done = ath12k_hw_qcn9274_dp_rx_h_msdu_done, @@ -719,6 +876,65 @@ .dp_rx_h_ip_cksum_fail = ath12k_hw_qcn9274_dp_rx_h_ip_cksum_fail, .dp_rx_h_is_decrypted = ath12k_hw_qcn9274_dp_rx_h_is_decrypted, .dp_rx_h_mpdu_err = ath12k_hw_qcn9274_dp_rx_h_mpdu_err, + .rx_desc_get_ip_valid = ath12k_hal_qcn9274_rx_desc_get_ip_valid, + .rxdma_ring_wmask_rx_mpdu_start = ath12k_hal_rx_mpdu_start_wmask_get, + .rxdma_ring_wmask_rx_msdu_end = ath12k_hal_rx_msdu_end_wmask_get, + .rx_desc_get_msdu_src_link_id = ath12k_hw_qcn9274_rx_desc_get_msdu_src_link, + .rx_get_desc_info = ath12k_hw_qcn9274_get_rx_desc_info, + .rx_get_desc_msdulen_l3pad = ath12k_hw_qcn9274_get_rx_msdulen_l3pad, + .rx_desc_get_first_last_msdu = ath12k_hw_qcn9274_get_rx_first_last_msdu, + .hal_get_tsf2_scratch_reg = ath12k_hal_qcn9274_get_tsf2_scratch_reg, + .hal_get_tqm_scratch_reg = ath12k_hal_qcn9274_get_tqm_scratch_reg, +}; + +const struct hal_ops hal_qcn6432_ops = { + .rx_desc_get_first_msdu = ath12k_hw_qcn9274_rx_desc_get_first_msdu, + .rx_desc_get_last_msdu = ath12k_hw_qcn9274_rx_desc_get_last_msdu, + .rx_desc_get_l3_pad_bytes = ath12k_hw_qcn9274_rx_desc_get_l3_pad_bytes, + .rx_desc_encrypt_valid = ath12k_hw_qcn9274_rx_desc_encrypt_valid, + .rx_desc_get_encrypt_type = ath12k_hw_qcn9274_rx_desc_get_encrypt_type, + .rx_desc_get_decap_type = ath12k_hw_qcn9274_rx_desc_get_decap_type, + .rx_desc_get_mesh_ctl = ath12k_hw_qcn9274_rx_desc_get_mesh_ctl, + .rx_desc_get_mpdu_seq_ctl_vld = ath12k_hw_qcn9274_rx_desc_get_mpdu_seq_ctl_vld, + .rx_desc_get_mpdu_fc_valid = ath12k_hw_qcn9274_rx_desc_get_mpdu_fc_valid, + .rx_desc_get_mpdu_start_seq_no = ath12k_hw_qcn9274_rx_desc_get_mpdu_start_seq_no, + .rx_desc_get_msdu_len = ath12k_hw_qcn9274_rx_desc_get_msdu_len, + .rx_desc_get_msdu_sgi = ath12k_hw_qcn9274_rx_desc_get_msdu_sgi, + .rx_desc_get_msdu_rate_mcs = ath12k_hw_qcn9274_rx_desc_get_msdu_rate_mcs, + .rx_desc_get_msdu_rx_bw = ath12k_hw_qcn9274_rx_desc_get_msdu_rx_bw, + .rx_desc_get_msdu_freq = ath12k_hw_qcn9274_rx_desc_get_msdu_freq, + .rx_desc_get_msdu_pkt_type = ath12k_hw_qcn9274_rx_desc_get_msdu_pkt_type, + .rx_desc_get_msdu_nss = ath12k_hw_qcn9274_rx_desc_get_msdu_nss, + .rx_desc_get_mpdu_tid = ath12k_hw_qcn9274_rx_desc_get_mpdu_tid, + .rx_desc_get_mpdu_peer_id = ath12k_hw_qcn9274_rx_desc_get_mpdu_peer_id, + .rx_desc_copy_end_tlv = ath12k_hw_qcn9274_rx_desc_copy_end_tlv, + .rx_desc_get_mpdu_ppdu_id = ath12k_hw_qcn9274_rx_desc_get_mpdu_ppdu_id, + .rx_desc_set_msdu_len = ath12k_hw_qcn9274_rx_desc_set_msdu_len, + .rx_desc_get_msdu_payload = ath12k_hw_qcn9274_rx_desc_get_msdu_payload, + .rx_desc_get_mpdu_start_offset = ath12k_hw_qcn9274_rx_desc_get_mpdu_start_offset, + .rx_desc_get_msdu_end_offset = ath12k_hw_qcn9274_rx_desc_get_msdu_end_offset, + .rx_desc_get_msdu_intra_bss_bit = ath12k_hw_qcn9274_rx_desc_get_msdu_intra_bss_bit, + .rx_desc_mac_addr2_valid = ath12k_hw_qcn9274_rx_desc_mac_addr2_valid, + .rx_desc_mpdu_start_addr2 = ath12k_hw_qcn9274_rx_desc_mpdu_start_addr2, + .rx_desc_is_da_mcbc = ath12k_hw_qcn9274_rx_desc_is_da_mcbc, + .rx_desc_get_dot11_hdr = ath12k_hw_qcn9274_rx_desc_get_dot11_hdr, + .rx_desc_get_crypto_header = ath12k_hw_qcn9274_rx_desc_get_crypto_hdr, + .create_srng_config = ath12k_hal_srng_create_config_qcn9274, + .tcl_to_wbm_rbm_map = ath12k_hal_qcn9274_tcl_to_wbm_rbm_map, + .dp_rx_h_msdu_done = ath12k_hw_qcn9274_dp_rx_h_msdu_done, + .dp_rx_h_l4_cksum_fail = ath12k_hw_qcn9274_dp_rx_h_l4_cksum_fail, + .dp_rx_h_ip_cksum_fail = ath12k_hw_qcn9274_dp_rx_h_ip_cksum_fail, + .dp_rx_h_is_decrypted = ath12k_hw_qcn9274_dp_rx_h_is_decrypted, + .dp_rx_h_mpdu_err = ath12k_hw_qcn9274_dp_rx_h_mpdu_err, + .rx_desc_get_ip_valid = ath12k_hal_qcn9274_rx_desc_get_ip_valid, + .rxdma_ring_wmask_rx_mpdu_start = ath12k_hal_rx_mpdu_start_wmask_get, + .rxdma_ring_wmask_rx_msdu_end = ath12k_hal_rx_msdu_end_wmask_get, + .rx_desc_get_msdu_src_link_id = ath12k_hw_qcn9274_rx_desc_get_msdu_src_link, + .rx_get_desc_info = ath12k_hw_qcn9274_get_rx_desc_info, + .rx_get_desc_msdulen_l3pad = ath12k_hw_qcn9274_get_rx_msdulen_l3pad, + .rx_desc_get_first_last_msdu = ath12k_hw_qcn9274_get_rx_first_last_msdu, + .hal_get_tsf2_scratch_reg = ath12k_hal_qcn9274_get_tsf2_scratch_reg, + .hal_get_tqm_scratch_reg = ath12k_hal_qcn9274_get_tqm_scratch_reg, }; static bool ath12k_hw_wcn7850_rx_desc_get_first_msdu(struct hal_rx_desc *desc) @@ -887,10 +1103,10 @@ return desc->u.wcn7850.mpdu_start.addr2; } -static bool ath12k_hw_wcn7850_rx_desc_is_mcbc(struct hal_rx_desc *desc) +static bool ath12k_hw_wcn7850_rx_desc_is_da_mcbc(struct hal_rx_desc *desc) { - return __le32_to_cpu(desc->u.wcn7850.mpdu_start.info6) & - RX_MPDU_START_INFO6_MCAST_BCAST; + return __le16_to_cpu(desc->u.wcn7850.msdu_end.info5) & + RX_MSDU_END_INFO5_DA_IS_MCBC; } static void ath12k_hw_wcn7850_rx_desc_get_dot11_hdr(struct hal_rx_desc *desc, @@ -951,11 +1167,6 @@ crypto_hdr[7] = HAL_RX_MPDU_INFO_PN_GET_BYTE2(desc->u.wcn7850.mpdu_start.pn[1]); } -static u16 ath12k_hw_wcn7850_rx_desc_get_mpdu_frame_ctl(struct hal_rx_desc *desc) -{ - return __le16_to_cpu(desc->u.wcn7850.mpdu_start.frame_ctrl); -} - static int ath12k_hal_srng_create_config_wcn7850(struct ath12k_base *ab) { struct ath12k_hal *hal = &ab->hal; @@ -992,9 +1203,9 @@ s = &hal->srng_config[HAL_TCL_DATA]; s->max_rings = 5; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB(ab); s->reg_start[1] = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; - s->reg_size[0] = HAL_TCL2_RING_BASE_LSB - HAL_TCL1_RING_BASE_LSB; + s->reg_size[0] = HAL_TCL2_RING_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab); s->reg_size[1] = HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; s = &hal->srng_config[HAL_TCL_CMD]; @@ -1007,31 +1218,31 @@ s = &hal->srng_config[HAL_CE_SRC]; s->max_rings = 12; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP; - s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG - - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; - s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG - - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_BASE_LSB; + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) + HAL_CE_DST_RING_HP; + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab); s = &hal->srng_config[HAL_CE_DST]; s->max_rings = 12; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP; - s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_BASE_LSB; + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_RING_HP; + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); s = &hal->srng_config[HAL_CE_DST_STATUS]; s->max_rings = 12; - s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + + s->reg_start[0] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_BASE_LSB; - s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_STATUS_RING_HP; - s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG - - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; + s->reg_start[1] = HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) + HAL_CE_DST_STATUS_RING_HP; + s->reg_size[0] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); + s->reg_size[1] = HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) - + HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab); s = &hal->srng_config[HAL_WBM_IDLE_LINK]; s->reg_start[0] = HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab); @@ -1163,10 +1374,9 @@ .rx_desc_get_msdu_end_offset = ath12k_hw_wcn7850_rx_desc_get_msdu_end_offset, .rx_desc_mac_addr2_valid = ath12k_hw_wcn7850_rx_desc_mac_addr2_valid, .rx_desc_mpdu_start_addr2 = ath12k_hw_wcn7850_rx_desc_mpdu_start_addr2, - .rx_desc_is_mcbc = ath12k_hw_wcn7850_rx_desc_is_mcbc, + .rx_desc_is_da_mcbc = ath12k_hw_wcn7850_rx_desc_is_da_mcbc, .rx_desc_get_dot11_hdr = ath12k_hw_wcn7850_rx_desc_get_dot11_hdr, .rx_desc_get_crypto_header = ath12k_hw_wcn7850_rx_desc_get_crypto_hdr, - .rx_desc_get_mpdu_frame_ctl = ath12k_hw_wcn7850_rx_desc_get_mpdu_frame_ctl, .create_srng_config = ath12k_hal_srng_create_config_wcn7850, .tcl_to_wbm_rbm_map = ath12k_hal_wcn7850_tcl_to_wbm_rbm_map, .dp_rx_h_msdu_done = ath12k_hw_wcn7850_dp_rx_h_msdu_done, @@ -1251,7 +1461,8 @@ } static void ath12k_hal_srng_dst_hw_init(struct ath12k_base *ab, - struct hal_srng *srng) + struct hal_srng *srng, + u32 idx) { struct ath12k_hal *hal = &ab->hal; u32 val; @@ -1260,6 +1471,12 @@ reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; + val = ath12k_hif_read32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET) & + ~HAL_REO1_RING_MISC_SRNG_ENABLE; + + ath12k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET, val); + val = 0; + if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { ath12k_hif_write32(ab, reg_base + ath12k_hal_reo1_ring_msi1_base_lsb_offset(ab), @@ -1309,9 +1526,10 @@ /* Initialize head and tail pointers to indicate ring is empty */ reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; - ath12k_hif_write32(ab, reg_base, 0); - ath12k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET, 0); - *srng->u.dst_ring.hp_addr = 0; + ath12k_hif_write32(ab, reg_base, idx * srng->entry_size); + ath12k_hif_write32(ab, reg_base + HAL_REO1_RING_TP_OFFSET, idx * srng->entry_size); + *srng->u.dst_ring.hp_addr = idx * srng->entry_size; + srng->u.dst_ring.tp = idx * srng->entry_size; reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; val = 0; @@ -1327,7 +1545,8 @@ } static void ath12k_hal_srng_src_hw_init(struct ath12k_base *ab, - struct hal_srng *srng) + struct hal_srng *srng, + u32 idx) { struct ath12k_hal *hal = &ab->hal; u32 val; @@ -1336,6 +1555,12 @@ reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; + val = ath12k_hif_read32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab)) & + ~HAL_TCL1_RING_MISC_SRNG_ENABLE; + + ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET(ab), val); + val = 0; + if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab), @@ -1397,9 +1622,10 @@ /* Initialize head and tail pointers to indicate ring is empty */ reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; - ath12k_hif_write32(ab, reg_base, 0); - ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, 0); - *srng->u.src_ring.tp_addr = 0; + ath12k_hif_write32(ab, reg_base, idx * srng->entry_size); + ath12k_hif_write32(ab, reg_base + HAL_TCL1_RING_TP_OFFSET, idx * srng->entry_size); + *srng->u.src_ring.tp_addr = idx * srng->entry_size; + srng->u.src_ring.hp = idx * srng->entry_size; reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R0]; val = 0; @@ -1422,12 +1648,13 @@ } static void ath12k_hal_srng_hw_init(struct ath12k_base *ab, - struct hal_srng *srng) + struct hal_srng *srng, + u32 idx) { if (srng->ring_dir == HAL_SRNG_DIR_SRC) - ath12k_hal_srng_src_hw_init(ab, srng); + ath12k_hal_srng_src_hw_init(ab, srng, idx); else - ath12k_hal_srng_dst_hw_init(ab, srng); + ath12k_hal_srng_dst_hw_init(ab, srng, idx); } static int ath12k_hal_srng_get_ring_id(struct ath12k_base *ab, @@ -1572,14 +1799,14 @@ } void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, - dma_addr_t paddr) + dma_addr_t paddr, u8 rbm_id) { desc->buf_addr_info.info0 = le32_encode_bits((paddr & HAL_ADDR_LSB_REG_MASK), BUFFER_ADDR_INFO0_ADDR); desc->buf_addr_info.info1 = le32_encode_bits(((u64)paddr >> HAL_ADDR_MSB_REG_SHIFT), BUFFER_ADDR_INFO1_ADDR) | - le32_encode_bits(1, BUFFER_ADDR_INFO1_RET_BUF_MGR) | + u32_encode_bits(rbm_id, BUFFER_ADDR_INFO1_RET_BUF_MGR) | le32_encode_bits(cookie, BUFFER_ADDR_INFO1_SW_COOKIE); } @@ -1593,6 +1820,21 @@ return NULL; } +void ath12k_hal_srng_prefetch_desc(struct ath12k_base *ab, + struct hal_srng *srng) +{ + u32 *desc; + + /* prefetch only if desc is available */ + desc = ath12k_hal_srng_dst_peek(ab, srng); + if (likely(desc)) { + dma_sync_single_for_cpu(ab->dev, virt_to_phys(desc), + (srng->entry_size * sizeof(u32)), + DMA_FROM_DEVICE); + prefetch(desc); + } +} + void *ath12k_hal_srng_dst_get_next_entry(struct ath12k_base *ab, struct hal_srng *srng) { @@ -1605,12 +1847,108 @@ desc = srng->ring_base_vaddr + srng->u.dst_ring.tp; - srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size) % - srng->ring_size; + srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size); + + /* wrap around to start of ring*/ + if (srng->u.dst_ring.tp == srng->ring_size) + srng->u.dst_ring.tp = 0; + + /* Try to prefetch the next descriptor in the ring */ + if (srng->flags & HAL_SRNG_FLAGS_CACHED) + ath12k_hal_srng_prefetch_desc(ab, srng); return desc; } +u32 *ath12k_hal_srng_dst_get_next_cache_entry(struct ath12k_base *ab, + struct hal_srng *srng) +{ + u32 *desc,*desc_next; + lockdep_assert_held(&srng->lock); + + if (srng->u.dst_ring.tp == srng->u.dst_ring.cached_hp) + return NULL; + + desc = srng->ring_base_vaddr + srng->u.dst_ring.tp; + + srng->u.dst_ring.tp = (srng->u.dst_ring.tp + srng->entry_size); + + /* wrap around to start of ring*/ + if (srng->u.dst_ring.tp == srng->ring_size) + srng->u.dst_ring.tp = 0; + + /* Try to prefetch the next descriptor in the ring */ + if (srng->u.dst_ring.tp != srng->u.dst_ring.cached_hp) { + /* prefetch only if desc is available */ + desc_next = srng->ring_base_vaddr + srng->u.dst_ring.tp; + prefetch(desc_next); + } + return desc; +} + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +void ath12k_hal_srng_ppeds_dst_inv_entry(struct ath12k_base *ab, + struct hal_srng *srng, int entries) +{ + u32 *desc, *last_desc; + u32 tp, hp; + u32 remaining_entries; + + if (!(srng->flags & HAL_SRNG_FLAGS_CACHED) || !entries) + return; + + tp = srng->u.dst_ring.tp; + hp = srng->u.dst_ring.cached_hp; + + desc = srng->ring_base_vaddr + tp; + if (hp > tp) { + last_desc = ((void *)desc + entries * srng->entry_size * sizeof(u32)); + dmac_inv_range_no_dsb((void *)desc, + (void *)last_desc); + } else { + remaining_entries = srng->ring_size - tp; + last_desc = ((void *)desc + remaining_entries * sizeof(u32)); + dmac_inv_range_no_dsb((void *)desc, (void *)last_desc); + + last_desc = ((void *)srng->ring_base_vaddr + hp * sizeof(u32)); + dmac_inv_range_no_dsb((void *)srng->ring_base_vaddr, (void *)last_desc); + } + + dsb(st); +} +#endif + +void ath12k_hal_srng_dst_invalidate_entry(struct ath12k_base *ab, + struct hal_srng *srng, int entries) +{ + u32 *desc; + u32 tp, hp; + + + if (!(srng->flags & HAL_SRNG_FLAGS_CACHED) || !entries) + return; + + tp = srng->u.dst_ring.tp; + hp = srng->u.dst_ring.cached_hp; + + desc = srng->ring_base_vaddr + tp; + if (hp > tp) { + dma_sync_single_for_cpu(ab->dev, virt_to_phys(desc), + entries * srng->entry_size * sizeof(u32), + DMA_FROM_DEVICE); + } else { + entries = srng->ring_size - tp; + dma_sync_single_for_cpu(ab->dev, virt_to_phys(desc), + entries * sizeof(u32), + DMA_FROM_DEVICE); + + entries = hp; + dma_sync_single_for_cpu(ab->dev, virt_to_phys(srng->ring_base_vaddr), + entries * sizeof(u32), + DMA_FROM_DEVICE); + } +} + int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng, bool sync_hw_ptr) { @@ -1730,11 +2068,15 @@ { lockdep_assert_held(&srng->lock); - if (srng->ring_dir == HAL_SRNG_DIR_SRC) + if (srng->ring_dir == HAL_SRNG_DIR_SRC) { srng->u.src_ring.cached_tp = *(volatile u32 *)srng->u.src_ring.tp_addr; - else + } else { srng->u.dst_ring.cached_hp = *srng->u.dst_ring.hp_addr; + /* Try to prefetch the next descriptor in the ring */ + if (srng->flags & HAL_SRNG_FLAGS_CACHED) + ath12k_hal_srng_prefetch_desc(ab, srng); + } } /* Update cached ring head/tail pointers to HW. ath12k_hal_srng_access_begin() @@ -1883,9 +2225,65 @@ val); } -int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type, +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +static void hal_tx_ppe2tcl_ring_halt_set(struct ath12k_base *ab) +{ + u32 cmn_reg_addr; + u32 regval; + + cmn_reg_addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_CMN_CTRL_REG; + regval = ath12k_hif_read32(ab, cmn_reg_addr); + + regval |= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT); + + /* Enable ring halt for the ppe2tcl ring */ + ath12k_hif_write32(ab, cmn_reg_addr, regval); +} + +static void hal_tx_ppe2tcl_ring_halt_reset(struct ath12k_base *ab) +{ + u32 cmn_reg_addr; + u32 regval; + + cmn_reg_addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_CMN_CTRL_REG; + regval = ath12k_hif_read32(ab, cmn_reg_addr); + + regval &= ~(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT); + + /* Disable ring halt for the ppe2tcl ring */ + ath12k_hif_write32(ab, cmn_reg_addr, regval); +} + +static bool hal_tx_ppe2tcl_ring_halt_done(struct ath12k_base *ab) +{ + u32 cmn_reg_addr; + u32 regval; + + cmn_reg_addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_CMN_CTRL_REG; + + regval = ath12k_hif_read32(ab, cmn_reg_addr); + + regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT); + + return !!regval; +} + +static bool hal_tx_ppe2tcl_ring_halt_get(struct ath12k_base *ab) +{ + u32 cmn_reg_addr; + u32 regval; + + cmn_reg_addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_CMN_CTRL_REG; + regval = ath12k_hif_read32(ab, cmn_reg_addr); + + return (regval & + 1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT); +} +#endif + +int ath12k_hal_srng_setup_idx(struct ath12k_base *ab, enum hal_ring_type type, int ring_num, int mac_id, - struct hal_srng_params *params) + struct hal_srng_params *params, u32 res_idx) { struct ath12k_hal *hal = &ab->hal; struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; @@ -1894,6 +2292,9 @@ u32 idx; int i; u32 reg_base; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + u32 retry_count = 0; +#endif ring_id = ath12k_hal_srng_get_ring_id(ab, type, ring_num, mac_id); if (ring_id < 0) @@ -1928,6 +2329,12 @@ memset(srng->ring_base_vaddr, 0, (srng->entry_size * srng->num_entries) << 2); + if (srng->flags & HAL_SRNG_FLAGS_CACHED) { + dmac_inv_range_no_dsb(srng->ring_base_vaddr, + srng->ring_base_vaddr + + ((srng->entry_size * srng->num_entries))); + } + reg_base = srng->hwreg_base[HAL_SRNG_REG_GRP_R2]; if (srng->ring_dir == HAL_SRNG_DIR_SRC) { @@ -1937,21 +2344,42 @@ srng->u.src_ring.tp_addr = (void *)(hal->rdp.vaddr + ring_id); srng->u.src_ring.low_threshold = params->low_threshold * srng->entry_size; + + if (srng->u.src_ring.tp_addr) + *srng->u.src_ring.tp_addr = 0; + if (srng_config->mac_type == ATH12K_HAL_SRNG_UMAC) { - if (!ab->hw_params->supports_shadow_regs) + if (!ab->hw_params->supports_shadow_regs) { srng->u.src_ring.hp_addr = (u32 *)((unsigned long)ab->mem + reg_base); - else + if (type == HAL_TCL_DATA) { + if (ab->hif.bus == ATH12K_BUS_PCI || + ab->hif.bus == ATH12K_BUS_HYBRID){ + srng->u.src_ring.hp_addr_direct = + (u32 *)((unsigned long)ab->mem + + HAL_DP_REG_WINDOW_OFFSET + + (reg_base & WINDOW_RANGE_MASK)); + } else { + srng->u.src_ring.hp_addr_direct = + srng->u.src_ring.hp_addr; + } + } + } else { ath12k_dbg(ab, ATH12K_DBG_HAL, "hal type %d ring_num %d reg_base 0x%x shadow 0x%lx\n", type, ring_num, reg_base, (unsigned long)srng->u.src_ring.hp_addr - (unsigned long)ab->mem); + } } else { idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START; srng->u.src_ring.hp_addr = (void *)(hal->wrp.vaddr + idx); + + if (srng->u.src_ring.hp_addr) + *srng->u.src_ring.hp_addr = 0; + srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; } } else { @@ -1967,18 +2395,36 @@ srng->u.dst_ring.tp = 0; srng->u.dst_ring.cached_hp = 0; srng->u.dst_ring.hp_addr = (void *)(hal->rdp.vaddr + ring_id); + + if (srng->u.dst_ring.hp_addr) + *srng->u.dst_ring.hp_addr = 0; + if (srng_config->mac_type == ATH12K_HAL_SRNG_UMAC) { - if (!ab->hw_params->supports_shadow_regs) + if (!ab->hw_params->supports_shadow_regs) { srng->u.dst_ring.tp_addr = (u32 *)((unsigned long)ab->mem + reg_base + (HAL_REO1_RING_TP - HAL_REO1_RING_HP)); - else + if (type == HAL_WBM2SW_RELEASE) { + if (ab->hif.bus == ATH12K_BUS_PCI || + ab->hif.bus == ATH12K_BUS_HYBRID) { + srng->u.dst_ring.tp_addr_direct = + (u32 *)((unsigned long)ab->mem + + (reg_base & WINDOW_RANGE_MASK) + + HAL_DP_REG_WINDOW_OFFSET + + (HAL_REO1_RING_TP - HAL_REO1_RING_HP)); + } else { + srng->u.dst_ring.tp_addr_direct = + srng->u.dst_ring.tp_addr; + } + } + } else { ath12k_dbg(ab, ATH12K_DBG_HAL, "type %d ring_num %d target_reg 0x%x shadow 0x%lx\n", type, ring_num, reg_base + HAL_REO1_RING_TP - HAL_REO1_RING_HP, (unsigned long)srng->u.dst_ring.tp_addr - (unsigned long)ab->mem); + } } else { /* For PMAC & DMAC rings, tail pointer updates will be done * through FW by writing to a shared memory location @@ -1986,6 +2432,10 @@ idx = ring_id - HAL_SRNG_RING_ID_DMAC_CMN_ID_START; srng->u.dst_ring.tp_addr = (void *)(hal->wrp.vaddr + idx); + + if (srng->u.dst_ring.tp_addr) + *srng->u.dst_ring.tp_addr = 0; + srng->flags |= HAL_SRNG_FLAGS_LMAC_RING; } } @@ -1993,8 +2443,41 @@ if (srng_config->mac_type != ATH12K_HAL_SRNG_UMAC) return ring_id; - ath12k_hal_srng_hw_init(ab, srng); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (res_idx) { + /* During UMAC reset Tx ring halt is set + * by Wi-Fi FW during pre-reset stage. + * Hence skip halting the rings again + */ + if (ath12k_dp_umac_reset_in_progress(ab)) { + if (!(hal_tx_ppe2tcl_ring_halt_get(ab))) { + ath12k_warn(ab, "TX ring halt not set\n"); + WARN_ON(1); + } + ath12k_hal_srng_hw_init(ab, srng, res_idx); + } else { + hal_tx_ppe2tcl_ring_halt_set(ab); + do { + ath12k_warn(ab, "Waiting for ring reset, retried count: %d\n", + retry_count); + mdelay(RING_HALT_TIMEOUT); + retry_count++; + } while (!(hal_tx_ppe2tcl_ring_halt_done(ab)) && + (retry_count < RNG_HALT_STAT_RETRY_COUNT)); + + if (retry_count >= RNG_HALT_STAT_RETRY_COUNT) + ath12k_err(ab, "Ring halt is failed, retried count: %d\n", + retry_count); + ath12k_hal_srng_hw_init(ab, srng, res_idx); + hal_tx_ppe2tcl_ring_halt_reset(ab); + } + } + else + ath12k_hal_srng_hw_init(ab, srng, 0); +#else + ath12k_hal_srng_hw_init(ab, srng, 0); +#endif if (type == HAL_CE_DST) { srng->u.dst_ring.max_buffer_length = params->max_buffer_len; ath12k_hal_ce_dst_setup(ab, srng, ring_num); @@ -2088,6 +2571,15 @@ } } +void ath12k_hal_reo_config_reo2ppe_dest_info(struct ath12k_base *ab) +{ + u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; + u32 val = HAL_REO1_REO2PPE_DST_VAL; + + ath12k_hif_write32(ab, reo_base + HAL_REO1_REO2PPE_DST_INFO, + val); +} + void ath12k_hal_srng_get_shadow_config(struct ath12k_base *ab, u32 **cfg, u32 *len) { @@ -2183,13 +2675,16 @@ if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) continue; - ath12k_err(ab, "CE_id %d pipe_num %d %ums before\n", + ath12k_err(ab,"CE_id %d pipe_num %d %ums before ce_manual_poll_count %d " + "ce_last_manual_tasklet_schedule_ts %ums before\n", i, ce_pipe->pipe_num, - jiffies_to_msecs(jiffies - ce_pipe->timestamp)); + jiffies_to_msecs(jiffies - ce_pipe->timestamp), + ce_pipe->ce_manual_poll_count, + jiffies_to_msecs(jiffies - ce_pipe->last_ce_manual_poll_ts)); } ath12k_err(ab, "\nLast interrupt received for each group:\n"); - for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { irq_grp = &ab->ext_irq_grp[i]; ath12k_err(ab, "group_id %d %ums before\n", irq_grp->grp_id, @@ -2220,3 +2715,67 @@ jiffies_to_msecs(jiffies - srng->timestamp)); } } + +ssize_t ath12k_debugfs_hal_dump_srng_stats(struct ath12k_base *ab, char *buf, int size) +{ + struct hal_srng *srng; + struct ath12k_ext_irq_grp *irq_grp; + struct ath12k_ce_pipe *ce_pipe; + unsigned int len = 0; + int i; + + len += scnprintf(buf + len, size - len, "Last interrupt received for each CE:\n"); + for (i = 0; i < ab->hw_params->ce_count; i++) { + ce_pipe = &ab->ce.ce_pipe[i]; + + if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) + continue; + + spin_lock_bh(&ab->ce.ce_lock); + len += scnprintf(buf + len, size - len, + "CE_id %d pipe_num %d %ums before ce_manual_poll_count %d ce_last_manual_tasklet_schedule_ts %ums before\n", + i, ce_pipe->pipe_num, + jiffies_to_msecs(jiffies - ce_pipe->timestamp), + ce_pipe->ce_manual_poll_count, + jiffies_to_msecs(jiffies - ce_pipe->last_ce_manual_poll_ts)); + spin_unlock_bh(&ab->ce.ce_lock); + } + + len += scnprintf(buf + len, size - len, "\nLast interrupt received for each group:\n"); + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { + irq_grp = &ab->ext_irq_grp[i]; + len += scnprintf(buf + len, size - len, "group_id %d %ums before\n", + irq_grp->grp_id, + jiffies_to_msecs(jiffies - irq_grp->timestamp)); + } + + for (i = 0; i < HAL_SRNG_RING_ID_MAX; i++) { + srng = &ab->hal.srng_list[i]; + + spin_lock_bh(&srng->lock); + if (!srng->initialized) { + spin_unlock_bh(&srng->lock); + continue; + } + + if (srng->ring_dir == HAL_SRNG_DIR_SRC) + len += scnprintf(buf + len, size - len, + "src srng id %u hp %u, reap_hp %u, cur tp %u, cached tp %u last tp %u napi processed before %ums\n", + srng->ring_id, srng->u.src_ring.hp, + srng->u.src_ring.reap_hp, + *srng->u.src_ring.tp_addr, srng->u.src_ring.cached_tp, + srng->u.src_ring.last_tp, + jiffies_to_msecs(jiffies - srng->timestamp)); + else if (srng->ring_dir == HAL_SRNG_DIR_DST) + len += scnprintf(buf + len, size - len, + "dst srng id %u tp %u, cur hp %u, cached hp %u last hp %u napi processed before %ums\n", + srng->ring_id, srng->u.dst_ring.tp, + *srng->u.dst_ring.hp_addr, + srng->u.dst_ring.cached_hp, + srng->u.dst_ring.last_hp, + jiffies_to_msecs(jiffies - srng->timestamp)); + spin_unlock_bh(&srng->lock); + } + + return len; +} diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hal.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal.h --- linux-6.4/drivers/net/wireless/ath/ath12k/hal.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal.h 2024-01-19 17:01:19.861846921 +0100 @@ -9,8 +9,11 @@ #include "hal_desc.h" #include "rx_desc.h" +#include "core.h" struct ath12k_base; +struct ath12k_dp_rx_info; +#define HAL_CE_REMAP_REG_BASE (ab->ce_remap_base_addr) #define HAL_LINK_DESC_SIZE (32 << 2) #define HAL_LINK_DESC_ALIGN 128 @@ -40,25 +43,42 @@ #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x))) +#define HAL_REO_QDESC_MAX_PEERID 8191 + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT 10 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT 18 +#define RNG_HALT_STAT_RETRY_COUNT 10 +#endif + /* WCSS Relative address */ #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 -#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000 -#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x01b81000 -#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x01b82000 -#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x01b83000 + +#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab) \ + ((ab)->hw_params->regs->hal_umac_ce0_src_reg_base) +#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(ab) \ + ((ab)->hw_params->regs->hal_umac_ce0_dest_reg_base) +#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(ab) \ + ((ab)->hw_params->regs->hal_umac_ce1_src_reg_base) +#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(ab) \ + ((ab)->hw_params->regs->hal_umac_ce1_dest_reg_base) + #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 +#define HAL_DP_REG_WINDOW_OFFSET 0x180000 #define HAL_TCL_SW_CONFIG_BANK_ADDR 0x00a4408c /* SW2TCL(x) R0 ring configuration address */ #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000020 #define HAL_TCL1_RING_DSCP_TID_MAP 0x00000240 -#define HAL_TCL1_RING_BASE_LSB 0x00000900 -#define HAL_TCL1_RING_BASE_MSB 0x00000904 +#define HAL_TCL1_RING_BASE_LSB(ab) \ + ((ab)->hw_params->regs->hal_tcl1_ring_base_lsb) +#define HAL_TCL1_RING_BASE_MSB(ab) \ + ((ab)->hw_params->regs->hal_tcl1_ring_base_msb) #define HAL_TCL1_RING_ID(ab) ((ab)->hw_params->regs->hal_tcl1_ring_id) #define HAL_TCL1_RING_MISC(ab) \ ((ab)->hw_params->regs->hal_tcl1_ring_misc) @@ -76,30 +96,31 @@ ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_msb) #define HAL_TCL1_RING_MSI1_DATA(ab) \ ((ab)->hw_params->regs->hal_tcl1_ring_msi1_data) -#define HAL_TCL2_RING_BASE_LSB 0x00000978 +#define HAL_TCL2_RING_BASE_LSB(ab) \ + ((ab)->hw_params->regs->hal_tcl2_ring_base_lsb) #define HAL_TCL_RING_BASE_LSB(ab) \ ((ab)->hw_params->regs->hal_tcl_ring_base_lsb) #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) \ - (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) \ - (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) \ - (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_BASE_MSB_OFFSET \ - (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_ID_OFFSET(ab) \ - (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) \ - (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \ - (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \ - (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \ - (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab)) #define HAL_TCL1_RING_MISC_OFFSET(ab) \ - (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB) + (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab)) /* SW2TCL(x) R2 ring pointers (head/tail) address */ #define HAL_TCL1_RING_HP 0x00002000 @@ -110,20 +131,22 @@ #define HAL_TCL1_RING_TP_OFFSET \ (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) +#define HAL_TCL_RBM_MAPPING0_ADDR_OFFSET 0x00000088 +#define HAL_TCL_RBM_MAPPING_SHFT 4 +#define HAL_TCL_RBM_MAPPING_BMSK 0xF +#define HAL_TCL_RBM_MAPPING_PPE2TCL_OFFSET 7 +#define HAL_TCL_RBM_MAPPING_TCL_CMD_CREDIT_OFFSET 6 + /* TCL STATUS ring address */ #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \ ((ab)->hw_params->regs->hal_tcl_status_ring_base_lsb) #define HAL_TCL_STATUS_RING_HP 0x00002048 /* PPE2TCL1 Ring address */ -#define HAL_TCL_PPE2TCL1_RING_BASE_LSB 0x00000c48 +#define HAL_TCL_PPE2TCL1_RING_BASE_LSB(ab) \ + ((ab)->hw_params->regs->hal_tcl_ppe2tcl_ring_base_lsb) #define HAL_TCL_PPE2TCL1_RING_HP 0x00002038 -/* WBM PPE Release Ring address */ -#define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab) \ - ((ab)->hw_params->regs->hal_ppe_rel_ring_base) -#define HAL_WBM_PPE_RELEASE_RING_HP 0x00003020 - /* REO2SW(x) R0 ring configuration address */ #define HAL_REO1_GEN_ENABLE 0x00000000 #define HAL_REO1_MISC_CTRL_ADDR(ab) \ @@ -132,6 +155,8 @@ #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 +#define HAL_REO1_QDESC_ADDR_READ(ab) (ab)->hw_params->regs->hal_reo1_qdesc_addr_read +#define HAL_REO1_QDESC_MAX_PEERID(ab) (ab)->hw_params->regs->hal_reo1_qdesc_max_peerid #define HAL_REO1_SW_COOKIE_CFG0(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg0) #define HAL_REO1_SW_COOKIE_CFG1(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg1) #define HAL_REO1_QDESC_LUT_BASE0(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base0) @@ -155,6 +180,28 @@ #define HAL_REO1_AGING_THRESH_IX_2(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix2) #define HAL_REO1_AGING_THRESH_IX_3(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix3) +#define HAL_REO1_REO2PPE_DST_VAL 0x2000 +#define HAL_REO1_REO2PPE_DST_INFO 0x00000cf0 + +#define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET \ + (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET \ + (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_MSI1_DATA_OFFSET \ + (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_BASE_MSB_OFFSET \ + (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET \ + (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_HP_ADDR_LSB_OFFSET \ + (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_HP_ADDR_MSB_OFFSET \ + (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab)) +#define HAL_REO1_RING_MISC_OFFSET \ + (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab)) + +/* REO2SW(x) R2 ring pointers (head/tail) address */ /* REO2SW(x) R2 ring pointers (head/tail) address */ #define HAL_REO1_RING_HP 0x00003048 #define HAL_REO1_RING_TP 0x0000304c @@ -201,6 +248,12 @@ ((ab)->hw_params->regs->hal_reo_status_ring_base) #define HAL_REO_STATUS_HP 0x000030a8 + +/* REO2PPE address */ +#define HAL_REO2PPE_RING_BASE_LSB(ab) \ + ((ab)->hw_params->regs->hal_reo2ppe_ring_base) +#define HAL_REO2PPE_HP 0x00003090 + /* WBM Idle R0 address */ #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab) \ ((ab)->hw_params->regs->hal_wbm_idle_ring_base_lsb) @@ -268,6 +321,7 @@ #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3) #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4) #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5) +#define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW6_EN BIT(7) #define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8) /* TCL ring field mask and offset */ @@ -319,6 +373,8 @@ #define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18) #define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19) #define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20) +#define HAL_REO_QDESC_ADDR_READ_LUT_ENABLE BIT(7) +#define HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY BIT(6) /* CE ring bit field mask and shift */ #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) @@ -347,6 +403,8 @@ #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff +#define HAL_REO2PPE_RING_BASE_MSB_RING_SIZE 0xffffffff +#define HAL_PPE2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff @@ -358,13 +416,32 @@ #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff #define HAL_RXDMA_RING_MAX_SIZE_BE 0x000fffff -#define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff +#define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff #define HAL_WBM2SW_REL_ERR_RING_NUM 3 +#define HAL_WBM2SW_PPEDS_TX_CMPLN_MAP_ID 11 +#define HAL_WBM2SW_PPEDS_TX_CMPLN_RING_NUM 6 /* Add any other errors here and return them in * ath12k_hal_rx_desc_get_err(). */ +#define HAL_IPQ5332_CE_WFSS_REG_BASE 0x740000 +#define HAL_IPQ5332_CE_SIZE 0x200000 + +#define HAL_IPQ5332_CMEM_REG_BASE 0xC100000 +#define HAL_IPQ5332_CMEM_SIZE 0x40000 +#define HAL_IPQ5332_CMEM_BASE 0x100000 + +#define HAL_IPQ5332_PMM_REG_BASE 0xCB500FC +#define HAL_IPQ5332_PMM_SIZE 0x100 + +#define HAL_QCN6432_CE_WFSS_REG_BASE 0x1B80000 +#define HAL_QCN6432_CE_SIZE 0x200000 + +#define HAL_QCN6432_CMEM_REG_BASE 0x00100000 +#define HAL_QCN6432_CMEM_SIZE 0x40000 +#define HAL_QCN6432_CMEM_BASE 0x100000 + enum hal_srng_ring_id { HAL_SRNG_RING_ID_REO2SW0 = 0, HAL_SRNG_RING_ID_REO2SW1, @@ -485,8 +562,8 @@ HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, HAL_SRNG_RING_ID_RXDMA_DIR_BUF, - HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0, + HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0, HAL_SRNG_RING_ID_PMAC1_ID_END, }; @@ -512,6 +589,7 @@ HAL_REO_REINJECT, HAL_REO_CMD, HAL_REO_STATUS, + HAL_REO2PPE, HAL_TCL_DATA, HAL_TCL_CMD, HAL_TCL_STATUS, @@ -523,18 +601,41 @@ HAL_WBM2SW_RELEASE, HAL_RXDMA_BUF, HAL_RXDMA_DST, - HAL_RXDMA_MONITOR_BUF, - HAL_RXDMA_MONITOR_STATUS, - HAL_RXDMA_MONITOR_DST, HAL_RXDMA_MONITOR_DESC, + HAL_RXDMA_MONITOR_STATUS, HAL_RXDMA_DIR_BUF, HAL_PPE2TCL, HAL_PPE_RELEASE, + HAL_RXDMA_MONITOR_BUF, HAL_TX_MONITOR_BUF, + HAL_RXDMA_MONITOR_DST, HAL_TX_MONITOR_DST, HAL_MAX_RING_TYPES, }; +#define PMM_REG_BASE_QCN9224 0xB500FC + +enum hal_scratch_reg_enum { + PMM_QTIMER_GLOBAL_OFFSET_LO_US, + PMM_QTIMER_GLOBAL_OFFSET_HI_US, + PMM_MAC0_TSF1_OFFSET_LO_US, + PMM_MAC0_TSF1_OFFSET_HI_US, + PMM_MAC0_TSF2_OFFSET_LO_US, + PMM_MAC0_TSF2_OFFSET_HI_US, + PMM_MAC1_TSF1_OFFSET_LO_US, + PMM_MAC1_TSF1_OFFSET_HI_US, + PMM_MAC1_TSF2_OFFSET_LO_US, + PMM_MAC1_TSF2_OFFSET_HI_US, + PMM_MLO_OFFSET_LO_US, + PMM_MLO_OFFSET_HI_US, + PMM_TQM_CLOCK_OFFSET_LO_US, + PMM_TQM_CLOCK_OFFSET_HI_US, + PMM_Q6_CRASH_REASON, + PMM_SCRATCH_TWT_OFFSET, + PMM_PMM_REG_MAX +}; + +#define WINDOW_RANGE_MASK GENMASK(18, 0) #define HAL_RX_MAX_BA_WINDOW 256 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000) @@ -613,6 +714,7 @@ #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 +#define HAL_SRNG_FLAGS_CACHED 0x20000000 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) @@ -699,6 +801,7 @@ * accessed through SW structure */ u32 *tp_addr; + u32 *tp_addr_direct; /* Current SW loop cnt */ u32 loop_cnt; @@ -728,6 +831,7 @@ * through SW structure */ u32 *hp_addr; + u32 *hp_addr_direct; /* Low threshold - in number of ring entries */ u32 low_threshold; @@ -739,13 +843,16 @@ }; /* Interrupt mitigation - Batch threshold in terms of number of frames */ -#define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 -#define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 +#define HAL_SRNG_INT_BATCH_THRESHOLD_PPE_WBM2SW_REL 256 +#define HAL_SRNG_INT_BATCH_THRESHOLD_TX 64 +#define HAL_SRNG_INT_BATCH_THRESHOLD_RX 64 +#define HAL_SRNG_INT_BATCH_THRESHOLD_PPE2TCL 0 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 /* Interrupt mitigation - timer threshold in us */ -#define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 -#define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 +#define HAL_SRNG_INT_TIMER_THRESHOLD_TX 200 +#define HAL_SRNG_INT_TIMER_THRESHOLD_RX 200 +#define HAL_SRNG_INT_TIMER_THRESHOLD_PPE2TCL 30 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256 enum hal_srng_mac_type { @@ -812,6 +919,7 @@ #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) +#define HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC BIT(9) /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */ #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) @@ -1061,12 +1169,12 @@ u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc); u32 (*rx_desc_get_mpdu_start_offset)(void); u32 (*rx_desc_get_msdu_end_offset)(void); + u8 (*rx_desc_get_msdu_intra_bss_bit)(struct hal_rx_desc *desc); bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc); u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc); - bool (*rx_desc_is_mcbc)(struct hal_rx_desc *desc); + bool (*rx_desc_is_da_mcbc)(struct hal_rx_desc *desc); void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc, struct ieee80211_hdr *hdr); - u16 (*rx_desc_get_mpdu_frame_ctl)(struct hal_rx_desc *desc); void (*rx_desc_get_crypto_header)(struct hal_rx_desc *desc, u8 *crypto_hdr, enum hal_encrypt_type enctype); @@ -1076,11 +1184,25 @@ bool (*dp_rx_h_ip_cksum_fail)(struct hal_rx_desc *desc); bool (*dp_rx_h_is_decrypted)(struct hal_rx_desc *desc); u32 (*dp_rx_h_mpdu_err)(struct hal_rx_desc *desc); + u8 (*rx_desc_get_ip_valid)(struct hal_rx_desc *desc); const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map; + u16 (*rxdma_ring_wmask_rx_mpdu_start)(void); + u32 (*rxdma_ring_wmask_rx_msdu_end)(void); + u8 (*rx_desc_get_msdu_src_link_id)(struct hal_rx_desc *desc); + void (*rx_get_desc_info)(struct hal_rx_desc *desc, + struct ath12k_dp_rx_info *info); + void (*rx_get_desc_msdulen_l3pad)(struct hal_rx_desc *desc, + struct ath12k_dp_rx_info *info); + void (*rx_desc_get_first_last_msdu)(struct hal_rx_desc *desc, + struct ath12k_dp_rx_info *info); + void (*hal_get_tsf2_scratch_reg)(struct ath12k_base *ab, u8 mac_id, + u64 *value); + void (*hal_get_tqm_scratch_reg)(struct ath12k_base *ab, u64 *value); }; extern const struct hal_ops hal_qcn9274_ops; extern const struct hal_ops hal_wcn7850_ops; +extern const struct hal_ops hal_qcn6432_ops; u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc, @@ -1098,8 +1220,8 @@ struct hal_srng *srng); dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab, struct hal_srng *srng); -void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, - dma_addr_t paddr); +void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, + u32 cookie, dma_addr_t paddr, u8 rbm_id); u32 ath12k_hal_ce_get_desc_size(enum hal_ce_desc type); void ath12k_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc, dma_addr_t paddr, u32 len, u32 id, u8 byte_swap_data); @@ -1125,9 +1247,9 @@ void ath12k_hal_srng_access_begin(struct ath12k_base *ab, struct hal_srng *srng); void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng); -int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type, +int ath12k_hal_srng_setup_idx(struct ath12k_base *ab, enum hal_ring_type type, int ring_num, int mac_id, - struct hal_srng_params *params); + struct hal_srng_params *params, u32 idx); int ath12k_hal_srng_init(struct ath12k_base *ath12k); void ath12k_hal_srng_deinit(struct ath12k_base *ath12k); void ath12k_hal_dump_srng_stats(struct ath12k_base *ab); @@ -1139,4 +1261,95 @@ void ath12k_hal_srng_shadow_config(struct ath12k_base *ab); void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab, struct hal_srng *srng); +u32 *ath12k_hal_srng_dst_get_next_cache_entry(struct ath12k_base *ab, + struct hal_srng *srng); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +void ath12k_hal_srng_ppeds_dst_inv_entry(struct ath12k_base *ab, + struct hal_srng *srng, int entries); +#endif +void ath12k_hal_srng_dst_invalidate_entry(struct ath12k_base *ab, + struct hal_srng *srng, int entries); +void ath12k_hal_reo_ring_ctrl_hash_ix3_setup(struct ath12k_base *ab, + u32 ring_hash_map); +void ath12k_hal_reo_ring_ctrl_hash_ix2_setup(struct ath12k_base *ab, + u32 ring_hash_map); +void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab); +void ath12k_hal_srng_prefetch_desc(struct ath12k_base *ab, + struct hal_srng *srng); +void ath12k_hal_reo_config_reo2ppe_dest_info(struct ath12k_base *ab); + +static inline +u32 *ath12k_hal_srng_src_get_next_entry_nolock(struct ath12k_base *ab, + struct hal_srng *srng) +{ + u32 *desc; + u32 next_hp; + + /* TODO: Using % is expensive, but we have to do this since size of some + * SRNG rings is not power of 2 (due to descriptor sizes). Need to see + * if separate function is defined for rings having power of 2 ring size + * (TCL2SW, REO2SW, SW2RXDMA and CE rings) so that we can avoid the + * overhead of % by using mask (with &). + */ + next_hp = (srng->u.src_ring.hp + srng->entry_size) % srng->ring_size; + + if (next_hp == srng->u.src_ring.cached_tp) + return NULL; + + desc = srng->ring_base_vaddr + srng->u.src_ring.hp; + srng->u.src_ring.hp = next_hp; + + /* TODO: Reap functionality is not used by all rings. If particular + * ring does not use reap functionality, we need not update reap_hp + * with next_hp pointer. Need to make sure a separate function is used + * before doing any optimization by removing below code updating + * reap_hp. + */ + srng->u.src_ring.reap_hp = next_hp; + + return desc; +} + +static inline +void ath12k_hal_srng_access_src_ring_begin_nolock(struct hal_srng *srng) +{ + srng->u.src_ring.cached_tp = *(volatile u32 *)srng->u.src_ring.tp_addr; +} + +static inline +void ath12k_hal_srng_access_dst_ring_begin_nolock(struct ath12k_base *ab, + struct hal_srng *srng) +{ + srng->u.dst_ring.cached_hp = *srng->u.dst_ring.hp_addr; + /* Try to prefetch the next descriptor in the ring */ + if (srng->flags & HAL_SRNG_FLAGS_CACHED) + ath12k_hal_srng_prefetch_desc(ab, srng); +} + +static inline +void ath12k_hal_srng_access_umac_src_ring_end_nolock(struct hal_srng *srng) +{ + srng->u.src_ring.last_tp = + *(volatile u32 *)srng->u.src_ring.tp_addr; + writel_relaxed(srng->u.src_ring.hp, srng->u.src_ring.hp_addr_direct); + srng->timestamp = jiffies; +} + +static inline +void ath12k_hal_srng_access_dst_ring_end_nolock(struct hal_srng *srng) +{ + srng->u.dst_ring.last_hp = *srng->u.dst_ring.hp_addr; + writel_relaxed(srng->u.dst_ring.tp, srng->u.dst_ring.tp_addr_direct); + srng->timestamp = jiffies; +} + +static inline +void ath12k_hal_srng_access_lmac_src_ring_end_nolock(struct hal_srng *srng) +{ + srng->u.src_ring.last_tp = *(volatile u32 *)srng->u.src_ring.tp_addr; + *srng->u.src_ring.hp_addr = srng->u.src_ring.hp; +} + + +ssize_t ath12k_debugfs_hal_dump_srng_stats(struct ath12k_base *ab, char *buf, int size); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hal_desc.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_desc.h --- linux-6.4/drivers/net/wireless/ath/ath12k/hal_desc.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_desc.h 2024-01-19 17:01:19.865847030 +0100 @@ -522,7 +522,7 @@ HAL_PHYRXHT_SIG_USR_SU = 468 /* 0x1d4 */, HAL_PHYRXHT_SIG_USR_MU_MIMO = 469 /* 0x1d5 */, HAL_PHYRX_GENERIC_U_SIG = 470 /* 0x1d6 */, - HAL_PHYRX_GENERICHT_SIG = 471 /* 0x1d7 */, + HAL_PHYRX_GENERIC_EHT_SIG = 471 /* 0x1d7 */, HAL_OVERWRITE_RESP_START = 472 /* 0x1d8 */, HAL_OVERWRITE_RESP_PREAMBLE_INFO = 473 /* 0x1d9 */, HAL_OVERWRITE_RESP_FRAME_INFO = 474 /* 0x1da */, @@ -580,11 +580,20 @@ #define HAL_TLV_64_HDR_TAG GENMASK(9, 1) #define HAL_TLV_64_HDR_LEN GENMASK(21, 10) +#define HAL_TLV_64_ALIGN 8 + struct hal_tlv_64_hdr { u64 tl; u8 value[]; } __packed; +struct hal_tlv_parsed_hdr { + u16 tlv_tag; + u16 tlv_len; + u16 tlv_userid; + u8 *tlv_data; +}; + #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(8) #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(9) @@ -597,8 +606,7 @@ #define RX_MPDU_DESC_INFO0_MPDU_QOS_CTRL_VALID BIT(27) #define RX_MPDU_DESC_INFO0_TID GENMASK(31, 28) -/* TODO revisit after meta data is concluded */ -#define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0) +#define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(13, 0) struct rx_mpdu_desc { __le32 info0; /* %RX_MPDU_DESC_INFO */ @@ -915,53 +923,6 @@ * this ring has looped around the ring. */ -#define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH GENMASK(15, 0) -#define HAL_REO_TO_PPE_RING_INFO0_DATA_OFFSET GENMASK(23, 16) -#define HAL_REO_TO_PPE_RING_INFO0_POOL_ID GENMASK(28, 24) -#define HAL_REO_TO_PPE_RING_INFO0_PREHEADER BIT(29) -#define HAL_REO_TO_PPE_RING_INFO0_TSO_EN BIT(30) -#define HAL_REO_TO_PPE_RING_INFO0_MORE BIT(31) - -struct hal_reo_to_ppe_ring { - __le32 buffer_addr; - __le32 info0; /* %HAL_REO_TO_PPE_RING_INFO0_ */ -} __packed; - -/* hal_reo_to_ppe_ring - * - * Producer: REO - * Consumer: PPE - * - * buf_addr_info - * Details of the physical address of a buffer or MSDU - * link descriptor. - * - * data_length - * Length of valid data in bytes - * - * data_offset - * Offset to the data from buffer pointer. Can be used to - * strip header in the data for tunnel termination etc. - * - * pool_id - * REO has global configuration register for this field. - * It may have several free buffer pools, each - * RX-Descriptor ring can fetch free buffer from specific - * buffer pool; pool id will indicate which pool the buffer - * will be released to; POOL_ID Zero returned to SW - * - * preheader - * Disabled: 0 (Default) - * Enabled: 1 - * - * tso_en - * Disabled: 0 (Default) - * Enabled: 1 - * - * more - * More Segments followed - */ - enum hal_reo_entr_rxdma_push_reason { HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ERR_DETECTED, HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ROUTING_INSTRUCTION, @@ -984,6 +945,10 @@ HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_FRAG_ERR, + HAL_REO_ENTR_RING_RXDMA_ECODE_MULTICAST_ECHO_ERR, + HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_ADDR_MISMATCH_ERR, + HAL_REO_ENTR_RING_RXDMA_ECODE_UNAUTH_WDS_ERR, + HAL_REO_ENTR_RING_RXDMA_ECODE_GROUPCAST_AMSDU_OR_WDS_ERR, HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, }; @@ -1197,6 +1162,7 @@ #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) +#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC BIT(15) struct hal_reo_flush_cache { struct hal_reo_cmd_hdr cmd; @@ -1239,6 +1205,7 @@ #define HAL_TCL_DATA_CMD_INFO5_RING_ID GENMASK(27, 20) #define HAL_TCL_DATA_CMD_INFO5_LOOPING_COUNT GENMASK(31, 28) +#define HAL_ENCRYPT_TYPE_MAX 12 enum hal_encrypt_type { HAL_ENCRYPT_TYPE_WEP_40, @@ -1260,11 +1227,13 @@ HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, HAL_TCL_ENCAP_TYPE_ETHERNET, HAL_TCL_ENCAP_TYPE_802_3 = 3, + HAL_TCL_ENCAP_TYPE_MAX }; enum hal_tcl_desc_type { HAL_TCL_DESC_TYPE_BUFFER, HAL_TCL_DESC_TYPE_EXT_DESC, + HAL_TCL_DESC_TYPE_MAX, }; enum hal_wbm_htt_tx_comp_status { @@ -1274,9 +1243,16 @@ HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, + HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH, HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX, }; +#define TX_IP_CHECKSUM (HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN | \ + HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN | \ + HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN | \ + HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN | \ + HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN) + struct hal_tcl_data_cmd { struct ath12k_buffer_addr buf_addr_info; __le32 info0; @@ -1782,6 +1758,7 @@ HAL_WBM_REL_SRC_MODULE_REO, HAL_WBM_REL_SRC_MODULE_FW, HAL_WBM_REL_SRC_MODULE_SW, + HAL_WBM_REL_SRC_MODULE_MAX, }; enum hal_wbm_rel_desc_type { @@ -1863,7 +1840,7 @@ #define HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) #define HAL_WBM_COMPL_TX_INFO0_RBM_OVERRIDE_VLD BIT(17) #define HAL_WBM_COMPL_TX_INFO0_SW_COOKIE_LO GENMASK(29, 18) -#define HAL_WBM_COMPL_TX_INFO0_CC_DONE BIT(30) +#define HAL_WBM_COMPL_TX_INFO0_CC_DONE 0x40000000 #define HAL_WBM_COMPL_TX_INFO0_WBM_INTERNAL_ERROR BIT(31) #define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) @@ -1960,6 +1937,7 @@ __le32 info1; } __packed; +#define HAL_WBM_RELEASE_INFO0_REL_SRC_MASK 0x7 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) @@ -2048,6 +2026,19 @@ * fw with fw_reason2. * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by * fw with fw_reason3. + * @HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE: Remove command initiated by + * fw with disable queue. + * @HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING: Remove command initiated by + * fw to remove all mpdu until 1st non-match. + * @HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: Dropped due to drop threshold + * criteria + * @HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL: Dropped due to link desc + * not available + * @HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU: Dropped due drop bit set or + * null flow + * @HAL_WBM_TQM_REL_REASON_MULTICAST_DROP: Dropped due mcast drop set for VDEV + * @HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP: Dropped due to being set with + * 'TCL_drop_reason' */ enum hal_wbm_tqm_rel_reason { HAL_WBM_TQM_REL_REASON_FRAME_ACKED, @@ -2058,6 +2049,16 @@ HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, + HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE, + HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING, + HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD, + HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL, + HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU, + HAL_WBM_TQM_REL_REASON_MULTICAST_DROP, + HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP, + + /* Keep Last */ + HAL_WBM_TQM_REL_REASON_MAX, }; struct hal_wbm_buffer_ring { @@ -2314,6 +2315,34 @@ struct hal_rx_mpdu_link_ptr mpdu_link[15]; } __packed; +struct hal_rx_reo_queue_1k { + struct hal_desc_header desc_hdr; + u32 rx_bitmap_319_288; + u32 rx_bitmap_351_320; + u32 rx_bitmap_383_352; + u32 rx_bitmap_415_384; + u32 rx_bitmap_447_416; + u32 rx_bitmap_479_448; + u32 rx_bitmap_511_480; + u32 rx_bitmap_543_512; + u32 rx_bitmap_575_544; + u32 rx_bitmap_607_576; + u32 rx_bitmap_639_608; + u32 rx_bitmap_671_640; + u32 rx_bitmap_703_672; + u32 rx_bitmap_735_704; + u32 rx_bitmap_767_736; + u32 rx_bitmap_799_768; + u32 rx_bitmap_831_800; + u32 rx_bitmap_863_832; + u32 rx_bitmap_895_864; + u32 rx_bitmap_927_896; + u32 rx_bitmap_959_928; + u32 rx_bitmap_991_960; + u32 rx_bitmap_1023_992; + u32 rsvd[8]; +}__packed; + /* hal_rx_reo_queue_ext * Consumer: REO * Producer: REO @@ -2500,13 +2529,13 @@ #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) -#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) -#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) -#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) -#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) -#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) -#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) -#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) +#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(9, 0) +#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(11, 10) +#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(12) +#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(24, 13) +#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(25) +#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(26) +#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(27) struct hal_reo_update_rx_queue { struct hal_reo_cmd_hdr cmd; @@ -2883,24 +2912,22 @@ * entries into this Ring has looped around the ring. */ -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH GENMASK(13, 0) -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L4_CSUM_STATUS BIT(14) -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L3_CSUM_STATUS BIT(15) -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_PID GENMASK(27, 24) -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_QDISC BIT(28) -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MULTICAST BIT(29) -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MORE BIT(30) -#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_VALID_TOGGLE BIT(31) - struct hal_tcl_entrance_from_ppe_ring { __le32 buffer_addr; __le32 info0; + __le32 opaque_lo; + __le32 opaque_hi; + __le32 info1; + __le32 info2; + __le32 info3; + __le32 info4; } __packed; struct hal_mon_buf_ring { __le32 paddr_lo; __le32 paddr_hi; - __le64 cookie; + __le32 cookie; + __le32 magic; }; /* hal_mon_buf_ring @@ -2918,9 +2945,8 @@ #define HAL_MON_DEST_COOKIE_BUF_ID GENMASK(17, 0) -#define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(15, 0) -#define HAL_MON_DEST_INFO0_FLUSH_DETECTED BIT(16) -#define HAL_MON_DEST_INFO0_END_OF_PPDU BIT(17) +#define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(11, 0) +#define HAL_MON_DEST_INFO0_END_REASON GENMASK(17, 16) #define HAL_MON_DEST_INFO0_INITIATOR BIT(18) #define HAL_MON_DEST_INFO0_EMPTY_DESC BIT(19) #define HAL_MON_DEST_INFO0_RING_ID GENMASK(27, 20) @@ -2928,7 +2954,7 @@ struct hal_mon_dest_desc { __le32 cookie; - __le32 reserved; + __le32 magic; __le32 ppdu_id; __le32 info0; }; diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hal_rx.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_rx.c --- linux-6.4/drivers/net/wireless/ath/ath12k/hal_rx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_rx.c 2024-01-19 17:01:19.865847030 +0100 @@ -89,6 +89,9 @@ if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL); + if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC) + desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC; + return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); } @@ -320,7 +323,7 @@ { enum hal_reo_dest_ring_push_reason push_reason; enum hal_reo_dest_ring_error_code err_code; - u32 cookie, val; + u32 cookie; push_reason = le32_get_bits(desc->info0, HAL_REO_DEST_RING_INFO0_PUSH_REASON); @@ -335,12 +338,6 @@ return -EINVAL; } - val = le32_get_bits(desc->info0, HAL_REO_DEST_RING_INFO0_BUFFER_TYPE); - if (val != HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) { - ath12k_warn(ab, "expected buffer type link_desc"); - return -EINVAL; - } - ath12k_hal_rx_reo_ent_paddr_get(ab, &desc->buf_addr_info, paddr, &cookie); *desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); @@ -689,6 +686,7 @@ u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid) { u32 num_ext_desc; + u32 num_1k_desc = 0; if (ba_window_size <= 1) { if (tid != HAL_DESC_REO_NON_QOS_TID) @@ -699,12 +697,16 @@ num_ext_desc = 1; } else if (ba_window_size <= 210) { num_ext_desc = 2; - } else { + } else if (ba_window_size <= 256) { num_ext_desc = 3; + } else { + num_ext_desc = 10; + num_1k_desc = 1; } return sizeof(struct hal_rx_reo_queue) + - (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)); + (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)) + + (num_1k_desc * sizeof(struct hal_rx_reo_queue_1k)); } void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc, @@ -813,6 +815,38 @@ } } +void ath12k_hal_reo_ring_ctrl_hash_ix0_setup(struct ath12k_base *ab) +{ + u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; + u32 curr, val; + + curr = ath12k_hif_read32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0); + val = curr & ~(REO_DEST_CTRL_IX_0_RING6_MAP_MASK << + REO_DEST_CTRL_IX_0_RING6_MAP_SHFT); + val |= (REO2PPE_DST_RING_MAP << REO_DEST_CTRL_IX_0_RING6_MAP_SHFT); + + ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, + val); +} + +void ath12k_hal_reo_ring_ctrl_hash_ix2_setup(struct ath12k_base *ab, + u32 ring_hash_map) +{ + u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; + + ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, + ring_hash_map); +} + +void ath12k_hal_reo_ring_ctrl_hash_ix3_setup(struct ath12k_base *ab, + u32 ring_hash_map) +{ + u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; + + ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, + ring_hash_map); +} + void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map) { u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; @@ -843,8 +877,75 @@ ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), HAL_DEFAULT_VO_REO_TIMEOUT_USEC); - ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, - ring_hash_map); - ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, - ring_hash_map); + ath12k_hal_reo_ring_ctrl_hash_ix0_setup(ab); + ath12k_hal_reo_ring_ctrl_hash_ix2_setup(ab, ring_hash_map); + ath12k_hal_reo_ring_ctrl_hash_ix3_setup(ab, ring_hash_map); +} + +/* + * Setting CLEAR_DESC_ARRAY field of WCSS_UMAC_REO_R0_QDESC_ADDR_READ + * and resetting back, to erase stale entries in reo storage. + */ +void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab) +{ + u32 val; + + val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + + HAL_REO1_QDESC_ADDR_READ(ab)); + + val |= u32_encode_bits(1, HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY); + ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + + HAL_REO1_QDESC_ADDR_READ(ab), val); + + val &= ~HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY; + ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + + HAL_REO1_QDESC_ADDR_READ(ab), val); +} + +void ath12k_dp_reset_rx_reo_tid_q(void *vaddr, u32 ba_window_size, + u8 tid) +{ + struct hal_rx_reo_queue *qdesc = (struct hal_rx_reo_queue *)vaddr; + struct hal_rx_reo_queue_ext *ext_desc; + u32 size, info0, info1, rx_queue_num; + + size = ath12k_hal_reo_qdesc_size(ba_window_size, tid); + + rx_queue_num = qdesc->rx_queue_num; + info0 = qdesc->info0; + info1 = qdesc->info1; + + memset(qdesc, 0, size); + + ath12k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED, + HAL_DESC_REO_QUEUE_DESC, + REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0); + + qdesc->rx_queue_num = rx_queue_num; + qdesc->info0 = info0; + qdesc->info1 = info1; + + qdesc->info1 |= u32_encode_bits(0, HAL_RX_REO_QUEUE_INFO1_SVLD); + qdesc->info1 |= u32_encode_bits(0, + HAL_RX_REO_QUEUE_INFO1_SSN); + + if (tid == HAL_DESC_REO_NON_QOS_TID) + return; + + ext_desc = qdesc->ext_desc; + memset(ext_desc, 0, 3 * sizeof(*ext_desc)); + + ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, + HAL_DESC_REO_QUEUE_EXT_DESC, + REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1); + ext_desc++; + + ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, + HAL_DESC_REO_QUEUE_EXT_DESC, + REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2); + ext_desc++; + + ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, + HAL_DESC_REO_QUEUE_EXT_DESC, + REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3); } diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hal_rx.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_rx.h --- linux-6.4/drivers/net/wireless/ath/ath12k/hal_rx.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_rx.h 2024-03-18 14:40:14.851741333 +0100 @@ -19,7 +19,7 @@ bool hw_cc_done; }; -#define HAL_INVALID_PEERID 0xffff +#define HAL_INVALID_PEERID 0x3fff #define VHT_SIG_SU_NSS_MASK 0x7 #define HAL_RX_MAX_MCS 12 @@ -61,6 +61,8 @@ HAL_RX_BW_40MHZ, HAL_RX_BW_80MHZ, HAL_RX_BW_160MHZ, + HAL_RX_BW_240MHZ, + HAL_RX_BW_320MHZ, HAL_RX_BW_MAX, }; @@ -70,6 +72,7 @@ HAL_RX_PREAMBLE_11N, HAL_RX_PREAMBLE_11AC, HAL_RX_PREAMBLE_11AX, + HAL_RX_PREAMBLE_11BE = 6, HAL_RX_PREAMBLE_MAX, }; @@ -107,9 +110,12 @@ HAL_RX_MON_STATUS_PPDU_NOT_DONE, HAL_RX_MON_STATUS_PPDU_DONE, HAL_RX_MON_STATUS_BUF_DONE, + HAL_RX_MON_STATUS_BUF_ADDR, + HAL_RX_MON_STATUS_MPDU_END, + HAL_RX_MON_STATUS_MSDU_END, }; -#define HAL_RX_MAX_MPDU 256 +#define HAL_RX_MAX_MPDU 1024 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5) struct hal_rx_user_status { @@ -142,9 +148,48 @@ u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP]; u32 mpdu_ok_byte_count; u32 mpdu_err_byte_count; + u32 ampdu_id; + bool ampdu_present; +}; + +struct msdu_info { + u32 errmap; + u32 decap_format; }; #define HAL_MAX_UL_MU_USERS 37 +#define HAL_RX_MAX_MSDU 256 + +struct mon_mpdu_data { + struct sk_buff *head_msdu; + struct sk_buff *tail_msdu; + struct msdu_info msdu_info[HAL_RX_MAX_MSDU]; + u16 msdu_count; +}; + +#define HAL_RX_MON_MAX_AGGR_SIZE 128 + +struct hal_rx_tlv_aggr_info { + u8 in_progress; + u8 cur_len; + u16 tlv_tag; + u8 buf[HAL_RX_MON_MAX_AGGR_SIZE]; +}; + +struct hal_rx_u_sig_info { + bool ul_dl; + u8 bw; + u8 ppdu_type_comp_mode; + u8 eht_sig_mcs; + u8 num_eht_sig_sym; +}; + +struct hal_rx_mon_cmn_mpdu_info { + struct mon_mpdu_data mon_mpdu[HAL_RX_MAX_MPDU]; + u16 mpdu_count; +}; + +#define EHT_MAX_USER_INFO 4 struct hal_rx_mon_ppdu_info { u32 ppdu_id; @@ -155,6 +200,7 @@ u32 preamble_type; u32 mpdu_len; u16 chan_num; + u16 freq; u16 tcp_msdu_count; u16 tcp_ack_msdu_count; u16 udp_msdu_count; @@ -229,23 +275,43 @@ bool first_msdu_in_mpdu; bool is_ampdu; u8 medium_prot_type; + bool ppdu_continuation; + struct hal_rx_tlv_aggr_info tlv_aggr; + u16 usig_flags; + u16 eht_flags; + u8 num_eht_user_info_valid; + u16 punctured_pattern; + u32 usig_common; + u32 usig_value; + u32 usig_mask; + u32 eht_known; + u32 eht_data[9]; + u32 eht_user_info[EHT_MAX_USER_INFO]; + struct hal_rx_u_sig_info u_sig_info; + struct hal_rx_mon_cmn_mpdu_info cmn_mpdu_info; }; #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0) +#define HAL_RX_PPDU_START_INFO1_CHAN_NUM GENMASK(15, 0) +#define HAL_RX_PPDU_START_INFO1_CHAN_FREQ GENMASK(31, 16) struct hal_rx_ppdu_start { __le32 info0; - __le32 chan_num; - __le32 ppdu_start_ts; + __le32 info1; + __le32 ppdu_start_ts_31_0; + __le32 ppdu_start_ts_63_32; + __le32 reserverd[2]; } __packed; -#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16) - -#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0) -#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9) -#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10) -#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11) -#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20) +#define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID GENMASK(13, 0) +#define HAL_RX_PPDU_END_USER_STATS_INFO0_CHIP_ID GENMASK(15, 14) +#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(26, 16) + +#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(10, 0) +#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(11) +#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(12) +#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(13) +#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(24, 21) #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0) #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16) @@ -261,8 +327,8 @@ #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0) #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16) -#define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT GENMASK(24, 0) -#define HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT GENMASK(24, 0) +#define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT GENMASK(24, 0) +#define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0) struct hal_rx_ppdu_end_user_stats { __le32 rsvd0[2]; @@ -293,6 +359,7 @@ __le32 info4; __le32 info5; __le32 info6; + __le32 rsvd; } __packed; #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0) @@ -389,11 +456,9 @@ #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION BIT(25) #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION GENMASK(6, 0) -#define HAL_RX_HE_SIG_A_MU_DL_INFO1_CODING BIT(7) #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB GENMASK(10, 8) #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA BIT(11) #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC BIT(12) -#define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXBF BIT(10) #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR GENMASK(14, 13) #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM BIT(15) @@ -419,7 +484,7 @@ #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0) #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11) -#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19) +#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(14) #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15) #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19) #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20) @@ -435,30 +500,35 @@ HAL_RECEPTION_TYPE_FRAMELESS }; -#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB GENMASK(15, 8) -#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION GENMASK(3, 0) +#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION GENMASK(3, 0) +#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW GENMASK(7, 5) +#define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8) struct hal_rx_phyrx_rssi_legacy_info { - __le32 rsvd[35]; __le32 info0; + __le32 rsvd0[39]; + __le32 info1; + __le32 rsvd2; } __packed; #define HAL_RX_MPDU_START_INFO0_PPDU_ID GENMASK(31, 16) -#define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(31, 16) +#define HAL_RX_MPDU_START_INFO1_PEERID GENMASK(29, 16) +#define HAL_RX_MPDU_START_INFO1_CHIPID GENMASK(31, 30) #define HAL_RX_MPDU_START_INFO2_MPDU_LEN GENMASK(13, 0) struct hal_rx_mpdu_start { + __le32 rsvd0[9]; __le32 info0; __le32 info1; - __le32 rsvd1[11]; + __le32 rsvd1[2]; __le32 info2; - __le32 rsvd2[9]; + __le32 rsvd2[16]; } __packed; #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0) struct hal_rx_ppdu_end_duration { __le32 rsvd0[9]; __le32 info0; - __le32 rsvd1[4]; + __le32 rsvd1[18]; } __packed; struct hal_rx_rxpcu_classification_overview { @@ -629,35 +699,435 @@ #define HAL_RX_MPDU_ERR_MPDU_LEN BIT(6) #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME BIT(7) -static inline -enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) -{ - enum nl80211_he_ru_alloc ret; - - switch (ru_tones) { - case RU_52: - ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; - break; - case RU_106: - ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; - break; - case RU_242: - ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; - break; - case RU_484: - ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; - break; - case RU_996: - ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; - break; - case RU_26: - fallthrough; - default: - ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; - break; - } - return ret; -} +#define HAL_RX_PHY_CMN_USER_INFO0_GI GENMASK(17, 16) +struct phyrx_common_user_info { + __le32 rsvd[2]; + __le32 info0; + __le32 rsvd1; +}; + +#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE GENMASK(3, 0) +#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_GI_LTF GENMASK(5, 4) +#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM GENMASK(8, 6) +#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS GENMASK(10, 7) +#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED BIT(11) +#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD GENMASK(13, 12) +#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC GENMASK(17, 14) + +struct hal_eht_sig_ndp_cmn_eb { + __le32 info0; +} __packed; + +#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE GENMASK(3, 0) +#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_GI_LTF GENMASK(5, 4) +#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM GENMASK(8, 6) +#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM BIT(9) +#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10) +#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY BIT(12) +#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD GENMASK(16, 13) + +struct hal_eht_sig_cc_usig_overflow { + __le32 info0; +} __packed; + +#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0) +#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS GENMASK(14, 11) +#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_VALIDATE BIT(15) +#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS GENMASK(19, 16) +#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED BIT(20) +#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING BIT(21) +#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CRC GENMASK(25, 22) + +struct hal_eht_sig_non_mu_mimo_user_info { + __le32 info0; +} __packed; + +#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID GENMASK(10, 0) +#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS GENMASK(14, 11) +#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING BIT(15) +#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING GENMASK(22, 16) +#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CRC GENMASK(26, 23) + +struct hal_eht_sig_mu_mimo_user_info { + __le32 info0; +} __packed; + +union hal_eht_sig_user_field { + struct hal_eht_sig_mu_mimo_user_info mu_mimo_usr; + struct hal_eht_sig_non_mu_mimo_user_info non_mu_mimo_usr; +}; + +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_SPATIAL_REUSE GENMASK(3, 0) +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_GI_LTF GENMASK(5, 4) +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_LTF_SYM GENMASK(8, 6) +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_LDPC_EXTA_SYM BIT(9) +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_PRE_FEC_PAD_FACTOR GENMASK(11, 10) +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISAMBIGUITY BIT(12) +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISREGARD GENMASK(16, 13) +#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS GENMASK(19, 17) + +struct hal_eht_sig_non_ofdma_cmn_eb { + __le32 info0; + union hal_eht_sig_user_field user_field; +} __packed; + +#define HAL_RX_EHT_SIG_OFDMA_EB1_SPATIAL_REUSE GENMASK_ULL(3, 0) +#define HAL_RX_EHT_SIG_OFDMA_EB1_GI_LTF GENMASK_ULL(5, 4) +#define HAL_RX_EHT_SIG_OFDMA_EB1_NUM_LFT_SYM GENMASK_ULL(8, 6) +#define HAL_RX_EHT_SIG_OFDMA_EB1_LDPC_EXTRA_SYM BIT(9) +#define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_FEC_PAD_FACTOR GENMASK_ULL(11, 10) +#define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_DISAMBIGUITY BIT(12) +#define HAL_RX_EHT_SIG_OFDMA_EB1_DISREGARD GENMASK_ULL(16, 13) +#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1 GENMASK_ULL(25, 17) +#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2 GENMASK_ULL(34, 26) +#define HAL_RX_EHT_SIG_OFDMA_EB1_CRC GENMASK_ULL(30, 27) + +struct hal_eht_sig_ofdma_cmn_eb1 { + __le64 info0; +} __packed; + +#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1 GENMASK_ULL(8, 0) +#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2 GENMASK_ULL(17, 9) +#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3 GENMASK_ULL(26, 18) +#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4 GENMASK_ULL(35, 27) +#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5 GENMASK_ULL(44, 36) +#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6 GENMASK_ULL(53, 45) +#define HAL_RX_EHT_SIG_OFDMA_EB2_MCS GNEMASK_ULL(57, 54) + +struct hal_eht_sig_ofdma_cmn_eb2 { + __le64 info0; +} __packed; + +enum hal_eht_bw { + HAL_EHT_BW_20, + HAL_EHT_BW_40, + HAL_EHT_BW_80, + HAL_EHT_BW_160, + HAL_EHT_BW_320_1, + HAL_EHT_BW_320_2, +}; + +#define HAL_RX_USIG_CMN_INFO0_PHY_VERSION GENMASK(2, 0) +#define HAL_RX_USIG_CMN_INFO0_BW GENMASK(5, 3) +#define HAL_RX_USIG_CMN_INFO0_UL_DL BIT(6) +#define HAL_RX_USIG_CMN_INFO0_BSS_COLOR GENMASK(12, 7) +#define HAL_RX_USIG_CMN_INFO0_TXOP GENMASK(19, 13) +#define HAL_RX_USIG_CMN_INFO0_DISREGARD GENMASK(25, 20) +#define HAL_RX_USIG_CMN_INFO0_VALIDATE BIT(26) + +struct hal_mon_usig_cmn { + __le32 info0; +} __packed; + +#define HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0) +#define HAL_RX_USIG_TB_INFO0_VALIDATE BIT(2) +#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1 GENMASK(6, 3) +#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2 GENMASK(10, 7) +#define HAL_RX_USIG_TB_INFO0_DISREGARD_1 GENMASK(15, 11) +#define HAL_RX_USIG_TB_INFO0_CRC GENMASK(19, 16) +#define HAL_RX_USIG_TB_INFO0_TAIL GENMASK(25, 20) +#define HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS BIT(31) + +struct hal_mon_usig_tb { + __le32 info0; +} __packed; + +#define HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE GENMASK(1, 0) +#define HAL_RX_USIG_MU_INFO0_VALIDATE_1 BIT(2) +#define HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO GENMASK(7, 3) +#define HAL_RX_USIG_MU_INFO0_VALIDATE_2 BIT(8) +#define HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS GENMASK(10, 9) +#define HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM GENMASK(15, 11) +#define HAL_RX_USIG_MU_INFO0_CRC GENMASK(20, 16) +#define HAL_RX_USIG_MU_INFO0_TAIL GENMASK(26, 21) +#define HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS BIT(31) + +struct hal_mon_usig_mu { + __le32 info0; +} __packed; + +union hal_mon_usig_non_cmn { + struct hal_mon_usig_tb tb; + struct hal_mon_usig_mu mu; +}; + +struct hal_mon_usig_hdr { + struct hal_mon_usig_cmn usig_1; + union hal_mon_usig_non_cmn usig_2; +} __packed; + +#define HAL_RX_USR_INFO0_PHY_PPDU_ID GENMASK(15, 0) +#define HAL_RX_USR_INFO0_USR_RSSI GENMASK(23, 16) +#define HAL_RX_USR_INFO0_PKT_TYPE GENMASK(27, 24) +#define HAL_RX_USR_INFO0_STBC BIT(28) +#define HAL_RX_USR_INFO0_RECEPTION_TYPE GENMASK(31, 29) + +#define HAL_RX_USR_INFO1_MCS GENMASK(3, 0) +#define HAL_RX_USR_INFO1_SGI GENMASK(5, 4) +#define HAL_RX_USR_INFO1_HE_RANGING_NDP BIT(6) +#define HAL_RX_USR_INFO1_MIMO_SS_BITMAP GENMASK(15, 8) +#define HAL_RX_USR_INFO1_RX_BW GENMASK(18, 16) +#define HAL_RX_USR_INFO1_DL_OFMDA_USR_IDX GENMASK(31, 24) + +#define HAL_RX_USR_INFO2_DL_OFDMA_CONTENT_CHAN BIT(0) +#define HAL_RX_USR_INFO2_NSS GENMASK(10, 8) +#define HAL_RX_USR_INFO2_STREAM_OFFSET GENMASK(13, 11) +#define HAL_RX_USR_INFO2_STA_DCM BIT(14) +#define HAL_RX_USR_INFO2_LDPC BIT(15) +#define HAL_RX_USR_INFO2_RU_TYPE_80_0 GENMASK(19, 16) +#define HAL_RX_USR_INFO2_RU_TYPE_80_1 GENMASK(23, 20) +#define HAL_RX_USR_INFO2_RU_TYPE_80_2 GENMASK(27, 24) +#define HAL_RX_USR_INFO2_RU_TYPE_80_3 GENMASK(31, 28) + +#define HAL_RX_USR_INFO3_RU_START_IDX_80_0 GENMASK(5, 0) +#define HAL_RX_USR_INFO3_RU_START_IDX_80_1 GENMASK(13, 8) +#define HAL_RX_USR_INFO3_RU_START_IDX_80_2 GENMASK(21, 16) +#define HAL_RX_USR_INFO3_RU_START_IDX_80_3 GENMASK(29, 24) + +struct hal_receive_user_info { + __le32 info0; + __le32 info1; + __le32 info2; + __le32 info3; + __le32 user_fd_rssi_seg0; + __le32 user_fd_rssi_seg1; + __le32 user_fd_rssi_seg2; + __le32 user_fd_rssi_seg3; +} __packed; + +enum hal_mon_reception_type{ + HAL_RECEPTION_TYPE_SU, + HAL_RECEPTION_TYPE_DL_MU_MIMO, + HAL_RECEPTION_TYPE_DL_MU_OFMA, + HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO, + HAL_RECEPTION_TYPE_UL_MU_MIMO, + HAL_RECEPTION_TYPE_UL_MU_OFDMA, + HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, +}; +/* Different allowed RU in 11BE */ +#define HAL_EHT_RU_26 0ULL +#define HAL_EHT_RU_52 1ULL +#define HAL_EHT_RU_78 2ULL +#define HAL_EHT_RU_106 3ULL +#define HAL_EHT_RU_132 4ULL +#define HAL_EHT_RU_242 5ULL +#define HAL_EHT_RU_484 6ULL +#define HAL_EHT_RU_726 7ULL +#define HAL_EHT_RU_996 8ULL +#define HAL_EHT_RU_996x2 9ULL +#define HAL_EHT_RU_996x3 10ULL +#define HAL_EHT_RU_996x4 11ULL +#define HAL_EHT_RU_NONE 15ULL +#define HAL_EHT_RU_INVALID 31ULL +/* + * MRUs spanning above 80Mhz + * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved) + */ +#define HAL_EHT_RU_996_484 18ULL +#define HAL_EHT_RU_996x2_484 28ULL +#define HAL_EHT_RU_996x3_484 40ULL +#define HAL_EHT_RU_996_484_242 23ULL + +#define NUM_RU_BITS_PER80 16 +#define NUM_RU_BITS_PER20 4 + +/* Different per_80Mhz band in 320Mhz bandwidth */ +#define HAL_80_0 0 +#define HAL_80_1 1 +#define HAL_80_2 2 +#define HAL_80_3 3 + +#define HAL_RU_SHIFT(num_80mhz_band, ru_index_per_80) \ + ((NUM_RU_BITS_PER80 * (num_80mhz_band)) + \ + (NUM_RU_BITS_PER20 * (ru_index_per_80))) + +/* MRU-996+484 */ +#define HAL_EHT_RU_996_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ + (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) +#define HAL_EHT_RU_996_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_1, 0))) +#define HAL_EHT_RU_996_484_2 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1))) +#define HAL_EHT_RU_996_484_3 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0))) +#define HAL_EHT_RU_996_484_4 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ + (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996_484_5 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996_484_6 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) +#define HAL_EHT_RU_996_484_7 ((HAL_EHT_RU_996 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) + +/* MRU-996x2+484 */ +#define HAL_EHT_RU_996x2_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) +#define HAL_EHT_RU_996x2_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) +#define HAL_EHT_RU_996x2_484_2 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) +#define HAL_EHT_RU_996x2_484_3 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0))) +#define HAL_EHT_RU_996x2_484_4 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1))) +#define HAL_EHT_RU_996x2_484_5 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0))) +#define HAL_EHT_RU_996x2_484_6 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x2_484_7 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x2_484_8 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x2_484_9 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x2_484_10 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) +#define HAL_EHT_RU_996x2_484_11 ((HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x2 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) + +/* MRU-996x3+484 */ +#define HAL_EHT_RU_996x3_484_0 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 1)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x3_484_1 ((HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x3_484_2 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 1)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x3_484_3 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x3_484_4 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 1)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x3_484_5 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_3, 0))) +#define HAL_EHT_RU_996x3_484_6 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 1))) +#define HAL_EHT_RU_996x3_484_7 ((HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_0, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_1, 0)) | \ + (HAL_EHT_RU_996x3 << HAL_RU_SHIFT(HAL_80_2, 0)) | \ + (HAL_EHT_RU_484 << HAL_RU_SHIFT(HAL_80_3, 0))) + +#define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \ + ((ru_320mhz) |= ((uint64_t)(ru_per80) << \ + (((num_80mhz) * NUM_RU_BITS_PER80) + \ + ((ru_idx_per80mhz) * NUM_RU_BITS_PER20)))) + +#define RU_26 1 +#define RU_52 2 +#define RU_106 4 +#define RU_242 9 +#define RU_484 18 +#define RU_996 37 +#define RU_2X996 74 +#define RU_3X996 111 +#define RU_4X996 148 +#define RU_52_26 RU_52 + RU_26 +#define RU_106_26 RU_106 + RU_26 +#define RU_484_242 RU_484 + RU_242 +#define RU_996_484 RU_996 + RU_484 +#define RU_996_484_242 RU_996 + RU_484_242 +#define RU_2X996_484 RU_2X996 + RU_484 +#define RU_3X996_484 RU_3X996 + RU_484 + +enum ath12k_eht_ru_size { + ATH12K_EHT_RU_26, + ATH12K_EHT_RU_52, + ATH12K_EHT_RU_106, + ATH12K_EHT_RU_242, + ATH12K_EHT_RU_484, + ATH12K_EHT_RU_996, + ATH12K_EHT_RU_996x2, + ATH12K_EHT_RU_996x4, + ATH12K_EHT_RU_52_26, + ATH12K_EHT_RU_106_26, + ATH12K_EHT_RU_484_242, + ATH12K_EHT_RU_996_484, + ATH12K_EHT_RU_996_484_242, + ATH12K_EHT_RU_996x2_484, + ATH12K_EHT_RU_996x3, + ATH12K_EHT_RU_996x3_484, + ATH12K_EHT_RU_INVALID, +}; + +#define REO2PPE_DST_RING_MAP 11 +#define REO_DEST_CTRL_IX_0_RING6_MAP_MASK 0xF +#define REO_DEST_CTRL_IX_0_RING6_MAP_SHFT 24 + +#define REO2PPE_DST_RING_MAP 11 +#define REO_DEST_CTRL_IX_0_RING6_MAP_MASK 0xF +#define REO_DEST_CTRL_IX_0_RING6_MAP_SHFT 24 + +/* U-SIG Common Mask */ +#define USIG_PHY_VERSION_KNOWN 0x00000001 +#define USIG_BW_KNOWN 0x00000002 +#define USIG_UL_DL_KNOWN 0x00000004 +#define USIG_BSS_COLOR_KNOWN 0x00000008 +#define USIG_TXOP_KNOWN 0x00000010 + +#define USIG_PHY_VERSION_SHIFT 12 +#define USIG_BW_SHIFT 15 +#define USIG_UL_DL_SHIFT 18 +#define USIG_BSS_COLOR_SHIFT 19 +#define USIG_TXOP_SHIFT 25 + +/* U-SIG MU/TB Value */ +#define USIG_DISREGARD_SHIFT 0 +#define USIG_PPDU_TYPE_N_COMP_MODE_SHIFT 6 +#define USIG_VALIDATE_SHIFT 8 + +#define USIG_MU_VALIDATE1_SHIFT 5 +#define USIG_MU_PUNCTURE_CH_INFO_SHIFT 9 +#define USIG_MU_VALIDATE2_SHIFT 12 +#define USIG_MU_EHT_SIG_MCS_SHIFT 15 +#define USIG_MU_NUM_EHT_SIG_SYM_SHIFT 17 + +#define USIG_TB_SPATIAL_REUSE_1_SHIFT 9 +#define USIG_TB_SPATIAL_REUSE_2_SHIFT 13 +#define USIG_TB_DISREGARD1_SHIFT 17 + +#define USIG_CRC_SHIFT 22 +#define USIG_TAIL_SHIFT 26 + +/* U-SIG MU/TB Mask */ +#define USIG_DISREGARD_KNOWN 0x00000001 +#define USIG_PPDU_TYPE_N_COMP_MODE_KNOWN 0x00000004 +#define USIG_VALIDATE_KNOWN 0x00000008 + +#define USIG_MU_VALIDATE1_KNOWN 0x00000002 +#define USIG_MU_PUNCTURE_CH_INFO_KNOWN 0x00000010 +#define USIG_MU_VALIDATE2_KNOWN 0x00000020 +#define USIG_MU_EHT_SIG_MCS_KNOWN 0x00000040 +#define USIG_MU_NUM_EHT_SIG_SYM_KNOWN 0x00000080 +#define USIG_TB_SPATIAL_REUSE_1_KNOWN 0x00000010 +#define USIG_TB_SPATIAL_REUSE_2_KNOWN 0x00000020 +#define USIG_TB_DISREGARD1_KNOWN 0x00000040 + +#define USIG_CRC_KNOWN 0x00000100 +#define USIG_TAIL_KNOWN 0x00000200 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hal_tx.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_tx.c --- linux-6.4/drivers/net/wireless/ath/ath12k/hal_tx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_tx.c 2024-01-19 17:01:19.865847030 +0100 @@ -29,43 +29,6 @@ return dscp >> 3; } -void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab, - struct hal_tcl_data_cmd *tcl_cmd, - struct hal_tx_info *ti) -{ - tcl_cmd->buf_addr_info.info0 = - le32_encode_bits(ti->paddr, BUFFER_ADDR_INFO0_ADDR); - tcl_cmd->buf_addr_info.info1 = - le32_encode_bits(((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT), - BUFFER_ADDR_INFO1_ADDR); - tcl_cmd->buf_addr_info.info1 |= - le32_encode_bits((ti->rbm_id), BUFFER_ADDR_INFO1_RET_BUF_MGR) | - le32_encode_bits(ti->desc_id, BUFFER_ADDR_INFO1_SW_COOKIE); - - tcl_cmd->info0 = - le32_encode_bits(ti->type, HAL_TCL_DATA_CMD_INFO0_DESC_TYPE) | - le32_encode_bits(ti->bank_id, HAL_TCL_DATA_CMD_INFO0_BANK_ID); - - tcl_cmd->info1 = - le32_encode_bits(ti->meta_data_flags, - HAL_TCL_DATA_CMD_INFO1_CMD_NUM); - - tcl_cmd->info2 = cpu_to_le32(ti->flags0) | - le32_encode_bits(ti->data_len, HAL_TCL_DATA_CMD_INFO2_DATA_LEN) | - le32_encode_bits(ti->pkt_offset, HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET); - - tcl_cmd->info3 = cpu_to_le32(ti->flags1) | - le32_encode_bits(ti->tid, HAL_TCL_DATA_CMD_INFO3_TID) | - le32_encode_bits(ti->lmac_id, HAL_TCL_DATA_CMD_INFO3_PMAC_ID) | - le32_encode_bits(ti->vdev_id, HAL_TCL_DATA_CMD_INFO3_VDEV_ID); - - tcl_cmd->info4 = le32_encode_bits(ti->bss_ast_idx, - HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX) | - le32_encode_bits(ti->bss_ast_hash, - HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM); - tcl_cmd->info5 = 0; -} - void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id) { u32 ctrl_reg_val; @@ -143,3 +106,36 @@ ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id, bank_config); } + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +void ath12k_hal_tx_set_ppe_vp_entry(struct ath12k_base *ab, u32 ppe_vp_config, + u32 ppe_vp_idx) +{ + ath12k_hif_write32(ab, HAL_TX_PPE_VP_CONFIG_TABLE_ADDR + + HAL_TX_PPE_VP_CONFIG_TABLE_OFFSET * ppe_vp_idx, + ppe_vp_config); +} +#endif + +void ath12k_hal_tx_config_rbm_mapping(struct ath12k_base *ab,u8 ring_num, + u8 rbm_id, int ring_type) +{ + u32 curr_map, new_map; + + if (ring_type == HAL_PPE2TCL) + ring_num = ring_num + HAL_TCL_RBM_MAPPING_PPE2TCL_OFFSET; + else if (ring_type == HAL_TCL_CMD) + ring_num = ring_num + HAL_TCL_RBM_MAPPING_TCL_CMD_CREDIT_OFFSET; + + curr_map = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + + HAL_TCL_RBM_MAPPING0_ADDR_OFFSET); + + /* Protect the other values and clear the specific fields to be updated */ + curr_map &= (~(HAL_TCL_RBM_MAPPING_BMSK << + (HAL_TCL_RBM_MAPPING_SHFT * ring_num))); + new_map = curr_map | ((HAL_TCL_RBM_MAPPING_BMSK & rbm_id) << + (HAL_TCL_RBM_MAPPING_SHFT * ring_num)); + + ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + + HAL_TCL_RBM_MAPPING0_ADDR_OFFSET, new_map); +} diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hal_tx.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_tx.h --- linux-6.4/drivers/net/wireless/ath/ath12k/hal_tx.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hal_tx.h 2024-01-19 17:01:19.865847030 +0100 @@ -64,6 +64,8 @@ u8 tid; u16 peer_id; u32 rate_stats; + u32 buffer_timestamp; + u32 tsf; }; #define HAL_TX_PHY_DESC_INFO0_BF_TYPE GENMASK(17, 16) @@ -182,13 +184,28 @@ /* STA mode will have MCAST_PKT_CTRL instead of DSCP_TID_MAP bitfield */ #define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID GENMASK(22, 17) -void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab, - struct hal_tcl_data_cmd *tcl_cmd, - struct hal_tx_info *ti); +#define HAL_TX_PPE_VP_CONFIG_TABLE_ADDR 0x00a44194 +#define HAL_TX_PPE_VP_CONFIG_TABLE_OFFSET 4 + +#define HAL_TX_PPE_VP_CFG_VP_NUM GENMASK(7, 0) +#define HAL_TX_PPE_VP_CFG_PMAC_ID GENMASK(9, 8) +#define HAL_TX_PPE_VP_CFG_BANK_ID GENMASK(15, 10) +#define HAL_TX_PPE_VP_CFG_VDEV_ID GENMASK(23, 16) +#define HAL_TX_PPE_VP_CFG_SRCH_IDX_REG_NUM GENMASK(26, 24) +#define HAL_TX_PPE_VP_CFG_USE_PPE_INT_PRI BIT(27) +#define HAL_TX_PPE_VP_CFG_TO_FW BIT(28) +#define HAL_TX_PPE_VP_CFG_DROP_PREC_EN BIT(29) + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +void ath12k_hal_tx_set_ppe_vp_entry(struct ath12k_base *ab, u32 ppe_vp_config, + u32 ppe_vp_index); +#endif void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id); int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng, enum hal_reo_cmd_type type, struct ath12k_hal_reo_cmd *cmd); void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config, u8 bank_id); +void ath12k_hal_tx_config_rbm_mapping(struct ath12k_base *ab,u8 ring_num, + u8 rbm_id, int ring_type); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hif.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hif.h --- linux-6.4/drivers/net/wireless/ath/ath12k/hif.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hif.h 2024-01-19 17:01:19.865847030 +0100 @@ -8,10 +8,14 @@ #define ATH12K_HIF_H #include "core.h" +#include "pci.h" struct ath12k_hif_ops { u32 (*read32)(struct ath12k_base *sc, u32 address); void (*write32)(struct ath12k_base *sc, u32 address, u32 data); + u32 (*cmem_read32)(struct ath12k_base *sc, u32 address); + void (*cmem_write32)(struct ath12k_base *sc, u32 address, u32 data); + u32 (*pmm_read32)(struct ath12k_base *sc, u32 address); void (*irq_enable)(struct ath12k_base *sc); void (*irq_disable)(struct ath12k_base *sc); int (*start)(struct ath12k_base *sc); @@ -30,8 +34,64 @@ void (*ce_irq_enable)(struct ath12k_base *ab); void (*ce_irq_disable)(struct ath12k_base *ab); void (*get_ce_msi_idx)(struct ath12k_base *ab, u32 ce_id, u32 *msi_idx); + int (*ssr_notifier_reg)(struct ath12k_base *ab); + int (*ssr_notifier_unreg)(struct ath12k_base *ab); + void (*config_static_window)(struct ath12k_base *ab); + int (*get_msi_irq)(struct ath12k_base *ab, unsigned int vector); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + int (*ppeds_register_interrupts)(struct ath12k_base *ab, int type, int vector, + int ring_num); + void (*ppeds_free_interrupts)(struct ath12k_base *ab); + void (*ppeds_irq_enable)(struct ath12k_base *ab, enum ppeds_irq_type type); + void (*ppeds_irq_disable)(struct ath12k_base *ab, enum ppeds_irq_type type); +#endif + int (*dp_umac_reset_irq_config)(struct ath12k_base *ab); + void (*dp_umac_reset_enable_irq)(struct ath12k_base *ab); + void (*dp_umac_reset_free_irq)(struct ath12k_base *ab); }; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +static inline int ath12k_hif_ppeds_register_interrupts(struct ath12k_base *ab, int type, int vector, + int ring_num) +{ + if (!test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) + return 0; + + if (ab->hif.ops->ppeds_register_interrupts) + return ab->hif.ops->ppeds_register_interrupts(ab, type, vector, + ring_num); + return 0; +} + +static inline void ath12k_hif_ppeds_free_interrupts(struct ath12k_base *ab) +{ + if (!test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) + return; + + if (ab->hif.ops->ppeds_register_interrupts) + ab->hif.ops->ppeds_free_interrupts(ab); +} + +static inline void ath12k_hif_ppeds_irq_enable(struct ath12k_base *ab, enum ppeds_irq_type type) +{ + if (!test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) + return; + + if (ab->hif.ops->ppeds_irq_enable) + ab->hif.ops->ppeds_irq_enable(ab, type); +} + +static inline void ath12k_hif_ppeds_irq_disable(struct ath12k_base *ab, enum ppeds_irq_type type) +{ + if (!test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) + return; + + if (ab->hif.ops->ppeds_irq_disable) + ab->hif.ops->ppeds_irq_disable(ab, type); +} +#endif + static inline int ath12k_hif_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, u8 *ul_pipe, u8 *dl_pipe) { @@ -72,6 +132,22 @@ *msi_data_idx = ce_id; } +static inline int ath12k_hif_ssr_notifier_reg(struct ath12k_base *ab) +{ + if (!ab->hif.ops->ssr_notifier_reg) + return 0; + + return ab->hif.ops->ssr_notifier_reg(ab); +} + +static inline int ath12k_hif_ssr_notifier_unreg(struct ath12k_base *ab) +{ + if (!ab->hif.ops->ssr_notifier_unreg) + return 0; + + return ab->hif.ops->ssr_notifier_unreg(ab); +} + static inline void ath12k_hif_ce_irq_enable(struct ath12k_base *ab) { if (ab->hif.ops->ce_irq_enable) @@ -131,6 +207,23 @@ ab->hif.ops->write32(ab, address, data); } +static inline u32 ath12k_hif_cmem_read32(struct ath12k_base *ab, u32 address) +{ + return ab->hif.ops->cmem_read32(ab, address); +} + +static inline u32 ath12k_hif_pmm_read32(struct ath12k_base *ab, u32 offset) +{ + return ab->hif.ops->pmm_read32(ab, offset); +} + +static inline void ath12k_hif_cmem_write32(struct ath12k_base *ab, u32 address, + u32 data) +{ + ab->hif.ops->cmem_write32(ab, address, data); +} + + static inline int ath12k_hif_power_up(struct ath12k_base *ab) { return ab->hif.ops->power_up(ab); @@ -141,4 +234,43 @@ ab->hif.ops->power_down(ab); } +static inline void ath12k_hif_config_static_window(struct ath12k_base *ab) +{ + if (!ab->hif.ops->config_static_window) + return; + + ab->hif.ops->config_static_window(ab); +} + +static inline int ath12k_hif_get_msi_irq(struct ath12k_base *ab, unsigned int vector) +{ + if (!ab->hif.ops->get_msi_irq) + return -EOPNOTSUPP; + + return ab->hif.ops->get_msi_irq(ab, vector); +} + +static inline int ath12k_hif_dp_umac_reset_irq_config(struct ath12k_base *ab) +{ + if (ab->hif.ops->dp_umac_reset_irq_config) + return ab->hif.ops->dp_umac_reset_irq_config(ab); + + return 0; +} + +static inline void ath12k_hif_dp_umac_reset_enable_irq(struct ath12k_base *ab) +{ + if (ab->hif.ops->dp_umac_reset_enable_irq) + return ab->hif.ops->dp_umac_reset_enable_irq(ab); + + return; +} + +static inline void ath12k_hif_dp_umac_reset_free_irq(struct ath12k_base *ab) +{ + if (ab->hif.ops->dp_umac_reset_free_irq) + return ab->hif.ops->dp_umac_reset_free_irq(ab); + + return; +} #endif /* ATH12K_HIF_H */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/htc.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/htc.c --- linux-6.4/drivers/net/wireless/ath/ath12k/htc.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/htc.c 2024-01-19 17:01:19.865847030 +0100 @@ -81,6 +81,8 @@ struct ath12k_base *ab = htc->ab; int credits = 0; int ret; + bool credit_flow_enabled = (ab->hw_params->credit_flow && + ep->tx_credit_flow_enabled); if (eid >= ATH12K_HTC_EP_COUNT) { ath12k_warn(ab, "Invalid endpoint id: %d\n", eid); @@ -89,7 +91,7 @@ skb_push(skb, sizeof(struct ath12k_htc_hdr)); - if (ep->tx_credit_flow_enabled) { + if (credit_flow_enabled) { credits = DIV_ROUND_UP(skb->len, htc->target_credit_size); spin_lock_bh(&htc->tx_lock); if (ep->tx_credits < credits) { @@ -109,6 +111,7 @@ ath12k_htc_prepare_tx_skb(ep, skb); + skb_cb->eid = eid; skb_cb->paddr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE); ret = dma_mapping_error(dev, skb_cb->paddr); if (ret) { @@ -125,7 +128,7 @@ err_unmap: dma_unmap_single(dev, skb_cb->paddr, skb->len, DMA_TO_DEVICE); err_credits: - if (ep->tx_credit_flow_enabled) { + if (credit_flow_enabled) { spin_lock_bh(&htc->tx_lock); ep->tx_credits += credits; ath12k_dbg(ab, ATH12K_DBG_HTC, @@ -202,6 +205,7 @@ break; } + if (ab->hw_params->credit_flow) { switch (record->hdr.id) { case ATH12K_HTC_RECORD_CREDITS: len = sizeof(struct ath12k_htc_credit_report); @@ -220,6 +224,7 @@ record->hdr.id, record->hdr.len); break; } + } if (status) break; @@ -244,6 +249,29 @@ complete(&ab->htc_suspend); } +void ath12k_htc_tx_completion_handler(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct ath12k_htc *htc = &ab->htc; + struct ath12k_htc_ep *ep; + void (*ep_tx_complete)(struct ath12k_base *, struct sk_buff *); + u8 eid; + + eid = ATH12K_SKB_CB(skb)->eid; + if (eid >= ATH12K_HTC_EP_COUNT) + return; + + ep = &htc->endpoint[eid]; + spin_lock_bh(&htc->tx_lock); + ep_tx_complete = ep->ep_ops.ep_tx_complete; + spin_unlock_bh(&htc->tx_lock); + if (!ep_tx_complete) { + dev_kfree_skb_any(skb); + return; + } + ep_tx_complete(htc->ab, skb); +} + void ath12k_htc_rx_completion_handler(struct ath12k_base *ab, struct sk_buff *skb) { @@ -606,12 +634,19 @@ disable_credit_flow_ctrl = true; } + if (!ab->hw_params->credit_flow) { + flags |= ATH12K_HTC_CONN_FLAGS_DISABLE_CREDIT_FLOW_CTRL; + disable_credit_flow_ctrl = true; + } + req_msg->flags_len = le32_encode_bits(flags, HTC_SVC_MSG_CONNECTIONFLAGS); req_msg->msg_svc_id |= le32_encode_bits(conn_req->service_id, HTC_SVC_MSG_SERVICE_ID); reinit_completion(&htc->ctl_resp); + if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags)) + clear_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); status = ath12k_htc_send(htc, ATH12K_HTC_EP_0, skb); if (status) { kfree_skb(skb); @@ -730,7 +765,10 @@ msg->msg_id = le32_encode_bits(ATH12K_HTC_MSG_SETUP_COMPLETE_EX_ID, HTC_MSG_MESSAGEID); + if (ab->hw_params->credit_flow) ath12k_dbg(ab, ATH12K_DBG_HTC, "HTC is using TX credit flow control\n"); + else + msg->flags |= ATH12K_GLOBAL_DISABLE_CREDIT_FLOW; status = ath12k_htc_send(htc, ATH12K_HTC_EP_0, skb); if (status) { diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/htc.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/htc.h --- linux-6.4/drivers/net/wireless/ath/ath12k/htc.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/htc.h 2024-01-19 17:01:19.865847030 +0100 @@ -81,6 +81,8 @@ ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_ONE_HALF, ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS, ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_UNITY, + ATH12K_HTC_CONN_FLAGS_REDUCE_CREDIT_DRIBBLE = 0x4, + ATH12K_HTC_CONN_FLAGS_DISABLE_CREDIT_FLOW_CTRL = 0x8, }; #define ATH12K_HTC_CONN_FLAGS_THRESHOLD_LEVEL_MASK GENMASK(1, 0) @@ -117,6 +119,8 @@ __le32 svc_meta_pad; } __packed; +#define ATH12K_GLOBAL_DISABLE_CREDIT_FLOW BIT(1) + struct ath12k_htc_setup_complete_extended { __le32 msg_id; __le32 flags; @@ -312,5 +316,7 @@ struct sk_buff *ath12k_htc_alloc_skb(struct ath12k_base *ar, int size); void ath12k_htc_rx_completion_handler(struct ath12k_base *ar, struct sk_buff *skb); +void ath12k_htc_tx_completion_handler(struct ath12k_base *ab, + struct sk_buff *skb); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hw.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hw.c --- linux-6.4/drivers/net/wireless/ath/ath12k/hw.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hw.c 2024-04-11 15:53:51.048030965 +0200 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -45,6 +45,37 @@ return false; } +static u8 ath12k_hw_ipq5332_mac_from_pdev_id(int pdev_idx) +{ + return pdev_idx; +} + +static int ath12k_hw_mac_id_to_pdev_id_ipq5332(const struct ath12k_hw_params *hw, + int mac_id) +{ + return mac_id; +} + +static int ath12k_hw_mac_id_to_srng_id_ipq5332(const struct ath12k_hw_params *hw, + int mac_id) +{ + return 0; +} + +static u8 ath12k_hw_get_ring_selector_ipq5332(struct sk_buff *skb) +{ + return smp_processor_id(); +} + +static bool ath12k_dp_srng_is_comp_ring_ipq5332(int ring_num) +{ + if (ring_num < 3 || ring_num == 4) + return true; + + return false; +} + + static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw, int mac_id) { @@ -88,10 +119,24 @@ .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850, }; +static const struct ath12k_hw_ops ipq5332_ops = { + .get_hw_mac_from_pdev_id = ath12k_hw_ipq5332_mac_from_pdev_id, + .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_ipq5332, + .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_ipq5332, + .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274, + .get_ring_selector = ath12k_hw_get_ring_selector_ipq5332, + .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_ipq5332, +}; + + #define ATH12K_TX_RING_MASK_0 0x1 #define ATH12K_TX_RING_MASK_1 0x2 #define ATH12K_TX_RING_MASK_2 0x4 #define ATH12K_TX_RING_MASK_3 0x8 +/* ATH12K_TX_RING_MASK_4 corresponds to the interrupt mask + * for the 4th TX Data ring which uses WBM2SW4RELEASE and + * hence uses the mask with 4th bit set + */ #define ATH12K_TX_RING_MASK_4 0x10 #define ATH12K_RX_RING_MASK_0 0x1 @@ -106,6 +151,8 @@ #define ATH12K_REO_STATUS_RING_MASK_0 0x1 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1 +#define ATH12K_HOST2RXDMA_RING_MASK_1 0x2 +#define ATH12K_HOST2RXDMA_RING_MASK_2 0x4 #define ATH12K_RX_MON_RING_MASK_0 0x1 #define ATH12K_RX_MON_RING_MASK_1 0x2 @@ -114,6 +161,12 @@ #define ATH12K_TX_MON_RING_MASK_0 0x1 #define ATH12K_TX_MON_RING_MASK_1 0x2 +#define ATH12K_PPE2TCL_RING_MASK_0 0x1 +#define ATH12K_REO2PPE_RING_MASK_0 0x1 +#define ATH12K_PPE_WBM2SW_RELEASE_RING_MASK_0 0x1 +#define ATH12K_PPE_WBM2SW_RELEASE_RING_MASK_0 0x1 +#define ATH12K_UMAC_RESET_INTR_MASK_0 0x1 + /* Target firmware's Copy Engine configuration. */ static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = { /* CE0: host->target HTC control and raw streams */ @@ -531,18 +584,304 @@ }, }; -static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = { +static const struct ce_pipe_config ath12k_target_ce_config_wlan_ipq5332[] = { + /* host->target HTC control and raw streams */ + { + .pipenum = __cpu_to_le32(0), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* target->host HTT */ + { + .pipenum = __cpu_to_le32(1), + .pipedir = __cpu_to_le32(PIPEDIR_IN), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* target->host WMI + HTC control */ + { + .pipenum = __cpu_to_le32(2), + .pipedir = __cpu_to_le32(PIPEDIR_IN), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* host->target WMI */ + { + .pipenum = __cpu_to_le32(3), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* host->target HTT */ + { + .pipenum = __cpu_to_le32(4), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(256), + .nbytes_max = __cpu_to_le32(256), + .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), + .reserved = __cpu_to_le32(0), + }, + /* Target -> host PKTLOG */ + { + .pipenum = __cpu_to_le32(5), + .pipedir = __cpu_to_le32(PIPEDIR_IN), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* Reserved for target autonomous HIF_memcpy */ + { + .pipenum = __cpu_to_le32(6), + .pipedir = __cpu_to_le32(PIPEDIR_INOUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(16384), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* CE7 Reserved for CV Prefetch */ + { + .pipenum = __cpu_to_le32(7), + .pipedir = __cpu_to_le32(PIPEDIR_OUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* CE8 Reserved for target generic HIF memcpy */ + { + .pipenum = __cpu_to_le32(8), + .pipedir = __cpu_to_le32(PIPEDIR_INOUT), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(16384), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* CE9 WMI logging/CFR/Spectral/Radar/ */ + { + .pipenum = __cpu_to_le32(9), + .pipedir = __cpu_to_le32(PIPEDIR_IN), + .nentries = __cpu_to_le32(32), + .nbytes_max = __cpu_to_le32(2048), + .flags = __cpu_to_le32(CE_ATTR_FLAGS), + .reserved = __cpu_to_le32(0), + }, + /* Unused TBD */ + { + .pipenum = __cpu_to_le32(10), + .pipedir = __cpu_to_le32(PIPEDIR_NONE), + .nentries = __cpu_to_le32(0), + .nbytes_max = __cpu_to_le32(0), + .flags = __cpu_to_le32(0), + .reserved = __cpu_to_le32(0), + }, + /* Unused TBD */ + { + .pipenum = __cpu_to_le32(11), + .pipedir = __cpu_to_le32(PIPEDIR_NONE), + .nentries = __cpu_to_le32(0), + .nbytes_max = __cpu_to_le32(0), + .flags = __cpu_to_le32(0), + .reserved = __cpu_to_le32(0), + }, +}; + +static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_ipq5332[] = { + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(3), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(2), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(3), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(2), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(3), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(2), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(3), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(2), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(3), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(2), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(0), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(1), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(0), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(1), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), + __cpu_to_le32(PIPEDIR_OUT), + __cpu_to_le32(4), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(1), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(5), + }, + { + __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG), + __cpu_to_le32(PIPEDIR_IN), + __cpu_to_le32(9), + }, + /* (Additions here) */ + + { /* must be last */ + __cpu_to_le32(0), + __cpu_to_le32(0), + __cpu_to_le32(0), + }, +}; + +static struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = { .tx = { ATH12K_TX_RING_MASK_0, ATH12K_TX_RING_MASK_1, ATH12K_TX_RING_MASK_2, - ATH12K_TX_RING_MASK_3, + 0, 0, 0, 0, 0, 0, 0, 0, + ATH12K_TX_RING_MASK_4, + 0, 0, 0 }, .rx_mon_dest = { - 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, ATH12K_RX_MON_RING_MASK_0, ATH12K_RX_MON_RING_MASK_1, ATH12K_RX_MON_RING_MASK_2, + 0, 0, 0, 0 + }, + .rx = { + 0, 0, 0, 0, + ATH12K_RX_RING_MASK_0, + ATH12K_RX_RING_MASK_1, + ATH12K_RX_RING_MASK_2, + ATH12K_RX_RING_MASK_3, + 0, 0, 0, 0, + 0, 0, 0 + }, + .rx_err = { + 0, 0, 0, + ATH12K_RX_ERR_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + .rx_wbm_rel = { + 0, 0, 0, + ATH12K_RX_WBM_REL_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + .reo_status = { + 0, 0, 0, + ATH12K_REO_STATUS_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + .host2rxdma = { + 0, 0, 0, + ATH12K_HOST2RXDMA_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + .tx_mon_dest = { + ATH12K_TX_MON_RING_MASK_0, + ATH12K_TX_MON_RING_MASK_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + .ppe2tcl = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + ATH12K_PPE2TCL_RING_MASK_0, 0, 0 + }, + .reo2ppe = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, ATH12K_REO2PPE_RING_MASK_0, 0 + }, +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + .wbm2sw6_ppeds_tx_cmpln = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, ATH12K_PPE_WBM2SW_RELEASE_RING_MASK_0 + }, +#endif + .umac_dp_reset = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + ATH12K_UMAC_RESET_INTR_MASK_0 + }, +}; + +static struct ath12k_hw_ring_mask ath12k_hw_ring_mask_ipq5332 = { + .tx = { + ATH12K_TX_RING_MASK_0, + ATH12K_TX_RING_MASK_1, + ATH12K_TX_RING_MASK_2, + ATH12K_TX_RING_MASK_4, + 0, 0, 0, 0, 0, 0, 0, 0, + }, + .rx_mon_dest = { + 0, 0, 0, 0, 0, 0, 0, 0, + ATH12K_RX_MON_RING_MASK_0, + 0, 0, 0, }, .rx = { 0, 0, 0, 0, @@ -550,30 +889,36 @@ ATH12K_RX_RING_MASK_1, ATH12K_RX_RING_MASK_2, ATH12K_RX_RING_MASK_3, + 0, 0, 0, 0, }, .rx_err = { 0, 0, 0, ATH12K_RX_ERR_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, }, .rx_wbm_rel = { 0, 0, 0, ATH12K_RX_WBM_REL_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, }, .reo_status = { 0, 0, 0, ATH12K_REO_STATUS_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, }, .host2rxdma = { 0, 0, 0, ATH12K_HOST2RXDMA_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, }, .tx_mon_dest = { ATH12K_TX_MON_RING_MASK_0, ATH12K_TX_MON_RING_MASK_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, }; -static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = { +static struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = { .tx = { ATH12K_TX_RING_MASK_0, ATH12K_TX_RING_MASK_2, @@ -603,6 +948,70 @@ }, }; +static struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn6432 = { + .tx = { + ATH12K_TX_RING_MASK_0, + ATH12K_TX_RING_MASK_1, + ATH12K_TX_RING_MASK_2 | ATH12K_TX_RING_MASK_4, + 0, 0, 0, 0, 0, 0, 0, 0, + }, + .rx_mon_dest = { + 0, 0, + ATH12K_RX_MON_RING_MASK_0, + ATH12K_RX_MON_RING_MASK_1, + ATH12K_RX_MON_RING_MASK_2, + 0, 0, 0, 0, 0, 0, 0, + }, + .rx = { + 0, 0, 0, + ATH12K_RX_RING_MASK_0, + ATH12K_RX_RING_MASK_1, + ATH12K_RX_RING_MASK_2 | ATH12K_RX_RING_MASK_3, + 0, 0, 0, 0, 0, 0, + }, + .rx_err = { + 0, 0, + ATH12K_RX_ERR_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + .rx_wbm_rel = { + 0, 0, + ATH12K_RX_WBM_REL_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + .reo_status = { + 0, 0, + ATH12K_REO_STATUS_RING_MASK_0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + .host2rxdma = { + 0, 0, + ATH12K_HOST2RXDMA_RING_MASK_0, + ATH12K_HOST2RXDMA_RING_MASK_1, + ATH12K_HOST2RXDMA_RING_MASK_2, + 0, 0, 0, 0, 0, 0, 0, + }, + .tx_mon_dest = { + ATH12K_TX_MON_RING_MASK_0, + ATH12K_TX_MON_RING_MASK_1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + .ppe2tcl = { + 0, 0, 0, 0, + 0, 0, ATH12K_PPE2TCL_RING_MASK_0, 0, 0, 0, 0, 0, + }, + .reo2ppe = { + 0, 0, 0, 0, + 0, 0, 0, ATH12K_REO2PPE_RING_MASK_0, 0, 0, 0, 0, + }, + .wbm2sw6_ppeds_tx_cmpln = { + 0, 0, 0, 0, + 0, 0, 0, 0, ATH12K_PPE_WBM2SW_RELEASE_RING_MASK_0, 0, 0, 0, + }, +#endif +}; + static const struct ath12k_hw_regs qcn9274_v1_regs = { /* SW2TCL(x) R0 ring configuration address */ .hal_tcl1_ring_id = 0x00000908, @@ -615,34 +1024,14 @@ .hal_tcl1_ring_msi1_base_msb = 0x0000094c, .hal_tcl1_ring_msi1_data = 0x00000950, .hal_tcl_ring_base_lsb = 0x00000b58, + .hal_tcl1_ring_base_lsb = 0x00000900, + .hal_tcl1_ring_base_msb = 0x00000904, + .hal_tcl2_ring_base_lsb = 0x00000978, + /* TCL STATUS ring address */ .hal_tcl_status_ring_base_lsb = 0x00000d38, - .hal_wbm_idle_ring_base_lsb = 0x00000d0c, - .hal_wbm_idle_ring_misc_addr = 0x00000d1c, - .hal_wbm_r0_idle_list_cntl_addr = 0x00000210, - .hal_wbm_r0_idle_list_size_addr = 0x00000214, - .hal_wbm_scattered_ring_base_lsb = 0x00000220, - .hal_wbm_scattered_ring_base_msb = 0x00000224, - .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230, - .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234, - .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240, - .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244, - .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c, - - .hal_wbm_sw_release_ring_base_lsb = 0x0000034c, - .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4, - .hal_wbm0_release_ring_base_lsb = 0x00000dd8, - .hal_wbm1_release_ring_base_lsb = 0x00000e50, - - /* PCIe base address */ - .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, - .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, - - /* PPE release ring address */ - .hal_ppe_rel_ring_base = 0x0000043c, - /* REO DEST ring address */ .hal_reo2_ring_base = 0x0000055c, .hal_reo1_misc_ctrl_addr = 0x00000b7c, @@ -650,6 +1039,8 @@ .hal_reo1_sw_cookie_cfg1 = 0x00000054, .hal_reo1_qdesc_lut_base0 = 0x00000058, .hal_reo1_qdesc_lut_base1 = 0x0000005c, + .hal_reo1_qdesc_addr_read = 0x00000060, + .hal_reo1_ring_base_lsb = 0x000004e4, .hal_reo1_ring_base_msb = 0x000004e8, .hal_reo1_ring_id = 0x000004ec, @@ -677,6 +1068,43 @@ /* REO status ring address */ .hal_reo_status_ring_base = 0x00000a84, + + /* WBM idle link ring address */ + .hal_wbm_idle_ring_base_lsb = 0x00000d0c, + .hal_wbm_idle_ring_misc_addr = 0x00000d1c, + .hal_wbm_r0_idle_list_cntl_addr = 0x00000210, + .hal_wbm_r0_idle_list_size_addr = 0x00000214, + .hal_wbm_scattered_ring_base_lsb = 0x00000220, + .hal_wbm_scattered_ring_base_msb = 0x00000224, + .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230, + .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234, + .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240, + .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244, + .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c, + + /* SW2WBM release ring address */ + .hal_wbm_sw_release_ring_base_lsb = 0x0000034c, + .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4, + + /* WBM2SW release ring address */ + .hal_wbm0_release_ring_base_lsb = 0x00000dd8, + .hal_wbm1_release_ring_base_lsb = 0x00000e50, + + /* reo2ppe ring address */ + .hal_reo2ppe_ring_base = 0x00000938, + + /* ppe2tcl ring base address */ + .hal_tcl_ppe2tcl_ring_base_lsb = 0x00000c48, + + /* PCIe base address */ + .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, + .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, + + /* CE base address */ + .hal_umac_ce0_src_reg_base = 0x01b80000, + .hal_umac_ce0_dest_reg_base = 0x01b81000, + .hal_umac_ce1_src_reg_base = 0x01b82000, + .hal_umac_ce1_dest_reg_base = 0x01b83000, }; static const struct ath12k_hw_regs qcn9274_v2_regs = { @@ -691,10 +1119,52 @@ .hal_tcl1_ring_msi1_base_msb = 0x0000094c, .hal_tcl1_ring_msi1_data = 0x00000950, .hal_tcl_ring_base_lsb = 0x00000b58, + .hal_tcl1_ring_base_lsb = 0x00000900, + .hal_tcl1_ring_base_msb = 0x00000904, + .hal_tcl2_ring_base_lsb = 0x00000978, /* TCL STATUS ring address */ .hal_tcl_status_ring_base_lsb = 0x00000d38, + /* REO DEST ring address */ + .hal_reo2_ring_base = 0x00000578, + .hal_reo1_misc_ctrl_addr = 0x00000b9c, + .hal_reo1_sw_cookie_cfg0 = 0x0000006c, + .hal_reo1_sw_cookie_cfg1 = 0x00000070, + .hal_reo1_qdesc_lut_base0 = 0x00000074, + .hal_reo1_qdesc_lut_base1 = 0x00000078, + .hal_reo1_qdesc_addr_read = 0x0000007c, + .hal_reo1_qdesc_max_peerid = 0x00000088, + .hal_reo1_ring_base_lsb = 0x00000500, + .hal_reo1_ring_base_msb = 0x00000504, + .hal_reo1_ring_id = 0x00000508, + .hal_reo1_ring_misc = 0x00000510, + .hal_reo1_ring_hp_addr_lsb = 0x00000514, + .hal_reo1_ring_hp_addr_msb = 0x00000518, + .hal_reo1_ring_producer_int_setup = 0x00000524, + .hal_reo1_ring_msi1_base_lsb = 0x00000548, + .hal_reo1_ring_msi1_base_msb = 0x0000054C, + .hal_reo1_ring_msi1_data = 0x00000550, + .hal_reo1_aging_thres_ix0 = 0x00000B28, + .hal_reo1_aging_thres_ix1 = 0x00000B2C, + .hal_reo1_aging_thres_ix2 = 0x00000B30, + .hal_reo1_aging_thres_ix3 = 0x00000B34, + + /* REO Exception ring address */ + .hal_reo2_sw0_ring_base = 0x000008c0, + + /* REO Reinject ring address */ + .hal_sw2reo_ring_base = 0x00000320, + .hal_sw2reo1_ring_base = 0x00000398, + + /* REO cmd ring address */ + .hal_reo_cmd_ring_base = 0x000002A8, + + /* REO status ring address */ + .hal_reo_status_ring_base = 0x00000aa0, + + .hal_reo1_qdesc_addr_read = 0x0000007c, + /* WBM idle link ring address */ .hal_wbm_idle_ring_base_lsb = 0x00000d3c, .hal_wbm_idle_ring_misc_addr = 0x00000d4c, @@ -716,12 +1186,41 @@ .hal_wbm0_release_ring_base_lsb = 0x00000e08, .hal_wbm1_release_ring_base_lsb = 0x00000e80, + /* reo2ppe ring base address */ + .hal_reo2ppe_ring_base = 0x00000938, + + /* ppe2tcl ring base address */ + .hal_tcl_ppe2tcl_ring_base_lsb = 0x00000c48, + /* PCIe base address */ .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, - /* PPE release ring address */ - .hal_ppe_rel_ring_base = 0x0000046c, + /* CE base address */ + .hal_umac_ce0_src_reg_base = 0x01b80000, + .hal_umac_ce0_dest_reg_base = 0x01b81000, + .hal_umac_ce1_src_reg_base = 0x01b82000, + .hal_umac_ce1_dest_reg_base = 0x01b83000, +}; + +const struct ath12k_hw_regs ipq5332_regs = { + /* SW2TCL(x) R0 ring configuration address */ + .hal_tcl1_ring_id = 0x00000918, + .hal_tcl1_ring_misc = 0x00000920, + .hal_tcl1_ring_tp_addr_lsb = 0x0000092c, + .hal_tcl1_ring_tp_addr_msb = 0x00000930, + .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000940, + .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000944, + .hal_tcl1_ring_msi1_base_lsb = 0x00000958, + .hal_tcl1_ring_msi1_base_msb = 0x0000095c, + .hal_tcl1_ring_base_lsb = 0x00000910, + .hal_tcl1_ring_base_msb = 0x00000914, + .hal_tcl1_ring_msi1_data = 0x00000960, + .hal_tcl2_ring_base_lsb = 0x00000988, + .hal_tcl_ring_base_lsb = 0x00000b68, + + /* TCL STATUS ring address */ + .hal_tcl_status_ring_base_lsb = 0x00000d48, /* REO DEST ring address */ .hal_reo2_ring_base = 0x00000578, @@ -730,6 +1229,8 @@ .hal_reo1_sw_cookie_cfg1 = 0x00000070, .hal_reo1_qdesc_lut_base0 = 0x00000074, .hal_reo1_qdesc_lut_base1 = 0x00000078, + .hal_reo1_qdesc_addr_read = 0x0000007c, + .hal_reo1_qdesc_max_peerid = 0x00000088, .hal_reo1_ring_base_lsb = 0x00000500, .hal_reo1_ring_base_msb = 0x00000504, .hal_reo1_ring_id = 0x00000508, @@ -757,6 +1258,33 @@ /* REO status ring address */ .hal_reo_status_ring_base = 0x00000aa0, + + /* WBM idle link ring address */ + .hal_wbm_idle_ring_base_lsb = 0x00000d3c, + .hal_wbm_idle_ring_misc_addr = 0x00000d4c, + .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, + .hal_wbm_r0_idle_list_size_addr = 0x00000244, + .hal_wbm_scattered_ring_base_lsb = 0x00000250, + .hal_wbm_scattered_ring_base_msb = 0x00000254, + .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, + .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, + .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, + .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, + .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c, + + /* SW2WBM release ring address */ + .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, + + /* WBM2SW release ring address */ + .hal_wbm0_release_ring_base_lsb = 0x00000e08, + .hal_wbm1_release_ring_base_lsb = 0x00000e80, + + /* CE base address */ + .hal_umac_ce0_src_reg_base = 0x00740000, + .hal_umac_ce0_dest_reg_base = 0x00741000, + .hal_umac_ce1_src_reg_base = 0x00742000, + .hal_umac_ce1_dest_reg_base = 0x00743000, + }; static const struct ath12k_hw_regs wcn7850_regs = { @@ -771,6 +1299,9 @@ .hal_tcl1_ring_msi1_base_msb = 0x0000094c, .hal_tcl1_ring_msi1_data = 0x00000950, .hal_tcl_ring_base_lsb = 0x00000b58, + .hal_tcl1_ring_base_lsb = 0x00000900, + .hal_tcl1_ring_base_msb = 0x00000904, + .hal_tcl2_ring_base_lsb = 0x00000978, /* TCL STATUS ring address */ .hal_tcl_status_ring_base_lsb = 0x00000d38, @@ -796,9 +1327,6 @@ .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, - /* PPE release ring address */ - .hal_ppe_rel_ring_base = 0x0000043c, - /* REO DEST ring address */ .hal_reo2_ring_base = 0x0000055c, .hal_reo1_misc_ctrl_addr = 0x00000b7c, @@ -833,6 +1361,105 @@ /* REO status ring address */ .hal_reo_status_ring_base = 0x00000a84, + + /* CE base address */ + .hal_umac_ce0_src_reg_base = 0x01b80000, + .hal_umac_ce0_dest_reg_base = 0x01b81000, + .hal_umac_ce1_src_reg_base = 0x01b82000, + .hal_umac_ce1_dest_reg_base = 0x01b83000, +}; + +const struct ath12k_hw_regs qcn6432_regs = { + /* SW2TCL(x) R0 ring configuration address */ + .hal_tcl1_ring_id = 0x00000918, + .hal_tcl1_ring_misc = 0x00000920, + .hal_tcl1_ring_tp_addr_lsb = 0x0000092c, + .hal_tcl1_ring_tp_addr_msb = 0x00000930, + .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000940, + .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000944, + .hal_tcl1_ring_msi1_base_lsb = 0x00000958, + .hal_tcl1_ring_msi1_base_msb = 0x0000095c, + .hal_tcl1_ring_base_lsb = 0x00000910, + .hal_tcl1_ring_base_msb = 0x00000914, + .hal_tcl1_ring_msi1_data = 0x00000960, + .hal_tcl2_ring_base_lsb = 0x00000988, + .hal_tcl_ring_base_lsb = 0x00000b68, + + /* TCL STATUS ring address */ + .hal_tcl_status_ring_base_lsb = 0x00000d48, + + /* REO DEST ring address */ + .hal_reo2_ring_base = 0x00000578, + .hal_reo1_misc_ctrl_addr = 0x00000b9c, + .hal_reo1_sw_cookie_cfg0 = 0x0000006c, + .hal_reo1_sw_cookie_cfg1 = 0x00000070, + .hal_reo1_qdesc_lut_base0 = 0x00000074, + .hal_reo1_qdesc_lut_base1 = 0x00000078, + .hal_reo1_qdesc_addr_read = 0x0000007c, + .hal_reo1_qdesc_max_peerid = 0x00000088, + .hal_reo1_ring_base_lsb = 0x00000500, + .hal_reo1_ring_base_msb = 0x00000504, + .hal_reo1_ring_id = 0x00000508, + .hal_reo1_ring_misc = 0x00000510, + .hal_reo1_ring_hp_addr_lsb = 0x00000514, + .hal_reo1_ring_hp_addr_msb = 0x00000518, + .hal_reo1_ring_producer_int_setup = 0x00000524, + .hal_reo1_ring_msi1_base_lsb = 0x00000548, + .hal_reo1_ring_msi1_base_msb = 0x0000054C, + .hal_reo1_ring_msi1_data = 0x00000550, + .hal_reo1_aging_thres_ix0 = 0x00000B28, + .hal_reo1_aging_thres_ix1 = 0x00000B2C, + .hal_reo1_aging_thres_ix2 = 0x00000B30, + .hal_reo1_aging_thres_ix3 = 0x00000B34, + + /* REO Exception ring address */ + .hal_reo2_sw0_ring_base = 0x000008c0, + + /* REO Reinject ring address */ + .hal_sw2reo_ring_base = 0x00000320, + .hal_sw2reo1_ring_base = 0x00000398, + + /* REO cmd ring address */ + .hal_reo_cmd_ring_base = 0x000002A8, + + /* REO status ring address */ + .hal_reo_status_ring_base = 0x00000aa0, + + /* WBM idle link ring address */ + .hal_wbm_idle_ring_base_lsb = 0x00000d3c, + .hal_wbm_idle_ring_misc_addr = 0x00000d4c, + .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, + .hal_wbm_r0_idle_list_size_addr = 0x00000244, + .hal_wbm_scattered_ring_base_lsb = 0x00000250, + .hal_wbm_scattered_ring_base_msb = 0x00000254, + .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, + .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, + .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, + .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, + .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c, + + /* SW2WBM release ring address */ + .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, + + /* WBM2SW release ring address */ + .hal_wbm0_release_ring_base_lsb = 0x00000e08, + .hal_wbm1_release_ring_base_lsb = 0x00000e80, + + /* reo2ppe ring base address */ + .hal_reo2ppe_ring_base = 0x00000938, + + /* ppe2tcl ring base address */ + .hal_tcl_ppe2tcl_ring_base_lsb = 0x00000c58, + + /* PCIe base address */ + .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, + .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, + + /* CE base address */ + .hal_umac_ce0_src_reg_base = 0x01B80000, + .hal_umac_ce0_dest_reg_base = 0x01B81000, + .hal_umac_ce1_src_reg_base = 0x01B82000, + .hal_umac_ce1_dest_reg_base = 0x01B83000, }; static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = { @@ -841,7 +1468,8 @@ HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | - HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, + HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN | + HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW6_EN, }; static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = { @@ -852,12 +1480,42 @@ HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, }; -static const struct ath12k_hw_params ath12k_hw_params[] = { +const struct ce_ie_addr ath12k_ce_ie_addr_ipq5332 = { + .ie1_reg_addr = CE_HOST_IE_ADDRESS, + .ie2_reg_addr = CE_HOST_IE_2_ADDRESS, + .ie3_reg_addr = CE_HOST_IE_3_ADDRESS, +}; + +const struct ce_remap ath12k_ce_remap_ipq5332 = { + .base = HAL_IPQ5332_CE_WFSS_REG_BASE, + .size = HAL_IPQ5332_CE_SIZE, +}; + +const struct cmem_remap ath12k_cmem_ipq5332 = { + .base = HAL_IPQ5332_CMEM_REG_BASE, + .size = HAL_IPQ5332_CMEM_SIZE, +}; + +const struct pmm_remap ath12k_pmm_ipq5332 = { + .base = HAL_IPQ5332_PMM_REG_BASE, + .size = HAL_IPQ5332_PMM_SIZE, +}; + +static const struct ath12k_hw_hal_params ath12k_hw_hal_params_ipq5332 = { + .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, + .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | + HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | + HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | + HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | + HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, +}; + +static struct ath12k_hw_params ath12k_hw_params[] = { { .name = "qcn9274 hw1.0", .hw_rev = ATH12K_HW_QCN9274_HW10, .fw = { - .dir = "QCN9274/hw1.0", + .dir = "QCN92XX/hw1.0", .board_size = 256 * 1024, .cal_offset = 128 * 1024, }, @@ -869,6 +1527,8 @@ .hw_ops = &qcn9274_ops, .ring_mask = &ath12k_hw_ring_mask_qcn9274, .regs = &qcn9274_v1_regs, + .ext_irq_grp_num_max = 12, + .route_wbm_release = 3, .host_ce_config = ath12k_host_ce_config_qcn9274, .ce_count = 16, @@ -879,21 +1539,23 @@ .hal_params = &ath12k_hw_hal_params_qcn9274, - .rxdma1_enable = false, + .rxdma1_enable = true, .num_rxmda_per_pdev = 1, .num_rxdma_dst_ring = 0, .rx_mac_buf_ring = false, .vdev_start_delay = false, .interface_modes = BIT(NL80211_IFTYPE_STATION) | - BIT(NL80211_IFTYPE_AP), - .supports_monitor = false, + BIT(NL80211_IFTYPE_AP) | + BIT(NL80211_IFTYPE_MESH_POINT), + .supports_monitor = true, .idle_ps = false, + .cold_boot_calib = false, .download_calib = true, .supports_suspend = false, .tcl_ring_retry = true, - .reoq_lut_support = false, + .reoq_lut_support = true, .supports_shadow_regs = false, .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), @@ -906,6 +1568,31 @@ .hal_ops = &hal_qcn9274_ops, + .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), + + .fix_l1ss = false, + + .supports_ap_ps = true, + .alloc_cacheable_memory = true, + .spectral = { + .fft_sz = 0, + .fft_pad_sz = 0, + .summary_pad_sz = 0, + .fft_hdr_len = 0, + .max_fft_bins = 0, + .fragment_160mhz = false, + }, + .max_mlo_peer = ATH12K_MAX_MLO_PEER, + .num_local_link = 0, + .m3_fw_support = true, + .compact_rx_tlv = true, + .send_platform_model = false, + .en_fwlog = true, + .support_umac_reset = false, + .en_qdsslog = true, + .supports_tx_monitor = false, + .fw_mem_mode = ATH12K_QMI_TARGET_MEM_MODE, + .is_plink_preferable = true, }, { .name = "wcn7850 hw2.0", @@ -925,6 +1612,8 @@ .hw_ops = &wcn7850_ops, .ring_mask = &ath12k_hw_ring_mask_wcn7850, .regs = &wcn7850_regs, + .ext_irq_grp_num_max = 12, + .route_wbm_release = 3, .host_ce_config = ath12k_host_ce_config_wcn7850, .ce_count = 9, @@ -960,6 +1649,22 @@ .wmi_init = ath12k_wmi_init_wcn7850, .hal_ops = &hal_wcn7850_ops, + + .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) | + BIT(CNSS_PCIE_PERST_NO_PULL_V01), + + .fix_l1ss = false, + .supports_ap_ps = true, + .credit_flow = false, + .m3_fw_support = true, + .compact_rx_tlv = false, + .send_platform_model = false, + .en_fwlog = true, + .support_umac_reset = false, + .en_qdsslog = true, + .supports_tx_monitor = false, + .fw_mem_mode = ATH12K_QMI_TARGET_MEM_MODE, + .is_plink_preferable = true, }, { .name = "qcn9274 hw2.0", @@ -969,7 +1674,7 @@ .board_size = 256 * 1024, .cal_offset = 128 * 1024, }, - .max_radios = 1, + .max_radios = 2, .single_pdev_only = false, .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, .internal_sleep_clock = false, @@ -977,6 +1682,8 @@ .hw_ops = &qcn9274_ops, .ring_mask = &ath12k_hw_ring_mask_qcn9274, .regs = &qcn9274_v2_regs, + .ext_irq_grp_num_max = 12, + .route_wbm_release = 3, .host_ce_config = ath12k_host_ce_config_qcn9274, .ce_count = 16, @@ -987,21 +1694,23 @@ .hal_params = &ath12k_hw_hal_params_qcn9274, - .rxdma1_enable = false, + .rxdma1_enable = true, .num_rxmda_per_pdev = 1, .num_rxdma_dst_ring = 0, .rx_mac_buf_ring = false, .vdev_start_delay = false, .interface_modes = BIT(NL80211_IFTYPE_STATION) | - BIT(NL80211_IFTYPE_AP), - .supports_monitor = false, + BIT(NL80211_IFTYPE_AP) | + BIT(NL80211_IFTYPE_MESH_POINT), + .supports_monitor = true, .idle_ps = false, + .cold_boot_calib = true, .download_calib = true, .supports_suspend = false, .tcl_ring_retry = true, - .reoq_lut_support = false, + .reoq_lut_support = true, .supports_shadow_regs = false, .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), @@ -1013,9 +1722,261 @@ .wmi_init = ath12k_wmi_init_qcn9274, .hal_ops = &hal_qcn9274_ops, + + .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), + + .fix_l1ss = false, + .supports_ap_ps = true, + .credit_flow = false, + .alloc_cacheable_memory = true, + .spectral = { + .fft_sz = 7, + .fft_pad_sz = 0, + .summary_pad_sz = 16, + .fft_hdr_len = 24, + .max_fft_bins = 512, + .fragment_160mhz = true, + }, + .max_mlo_peer = ATH12K_MAX_MLO_PEER, + .num_local_link = 0, + .m3_fw_support = true, + .compact_rx_tlv = true, + .send_platform_model = false, + .en_fwlog = true, + .support_umac_reset = true, + .en_qdsslog = false, + .supports_tx_monitor = false, + .fw_mem_mode = ATH12K_QMI_TARGET_MEM_MODE, + .is_plink_preferable = true, + }, + { + .name = "ipq5332 hw1.0", + .hw_rev = ATH12K_HW_IPQ5332_HW10, + .bdf_addr = 0x4B500000, + .fw = { + .dir = "IPQ5332/hw1.0", + .board_size = 256 * 1024, + .cal_offset = 128 * 1024, + }, + .max_radios = 1, + .single_pdev_only = false, + .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332, + .internal_sleep_clock = false, + + .hw_ops = &ipq5332_ops, + .regs = &ipq5332_regs, + .ext_irq_grp_num_max = 12, + .ring_mask = &ath12k_hw_ring_mask_ipq5332, + .route_wbm_release = 3, + + .host_ce_config = ath12k_host_ce_config_ipq5332, + .ce_count = 12, + .target_ce_config = ath12k_target_ce_config_wlan_ipq5332, + .target_ce_count = 12, + .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_ipq5332, + .svc_to_ce_map_len = 19, + + .hal_params = &ath12k_hw_hal_params_ipq5332, + + .rxdma1_enable = true, + .num_rxmda_per_pdev = 1, + .num_rxdma_dst_ring = 0, + .rx_mac_buf_ring = false, + .vdev_start_delay = false, + .fixed_fw_mem = false, + .smp2p_wow_exit = false, + + .interface_modes = BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_AP) | + BIT(NL80211_IFTYPE_MESH_POINT), + .supports_monitor = true, + + .idle_ps = false, + .cold_boot_calib = true, + .download_calib = true, + .supports_suspend = false, + .tcl_ring_retry = true, + .reoq_lut_support = true, + .supports_shadow_regs = false, + + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), + .num_tcl_banks = 48, + .max_tx_ring = 4, + + + .wmi_init = ath12k_wmi_init_ipq5332, + + .hal_ops = &hal_qcn9274_ops, + + .supports_ap_ps = true, + .credit_flow = false, + .alloc_cacheable_memory = true, + .spectral = { + .fft_sz = 7, + .fft_pad_sz = 0, + .summary_pad_sz = 16, + .fft_hdr_len = 24, + .max_fft_bins = 512, + .fragment_160mhz = false, + }, + .max_mlo_peer = ATH12K_MAX_MLO_PEER, + .num_local_link = 0, + .m3_fw_support = false, + .compact_rx_tlv = true, + .ce_ie_addr = &ath12k_ce_ie_addr_ipq5332, + .ce_remap = &ath12k_ce_remap_ipq5332, + .cmem_remap = &ath12k_cmem_ipq5332, + .pmm_remap = &ath12k_pmm_ipq5332, + .send_platform_model = true, + .en_fwlog = true, + .support_umac_reset = false, + .support_ce_manual_poll=true, + .en_qdsslog = true, + .supports_tx_monitor = false, + .fw_mem_mode = ATH12K_QMI_TARGET_MEM_MODE, + .is_plink_preferable = false, + }, + { + .name = "qcn6432 hw1.0", + .hw_rev = ATH12K_HW_QCN6432_HW10, + .fw = { + .dir = "QCN6432/hw1.0", + .board_size = 256 * 1024, + .cal_offset = 128 * 1024, + }, + .max_radios = 1, + .single_pdev_only = false, + .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN6432, + .internal_sleep_clock = false, + + .hw_ops = &ipq5332_ops, + .regs = &qcn6432_regs, + .ext_irq_grp_num_max = 6, + .ring_mask = &ath12k_hw_ring_mask_qcn6432, + .route_wbm_release = 2, + + .host_ce_config = ath12k_host_ce_config_ipq5332, + .ce_count = 12, + .target_ce_config = ath12k_target_ce_config_wlan_ipq5332, + .target_ce_count = 12, + .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_ipq5332, + .svc_to_ce_map_len = 19, + + .hal_params = &ath12k_hw_hal_params_ipq5332, + + .rxdma1_enable = true, + .num_rxmda_per_pdev = 1, + .num_rxdma_dst_ring = 0, + .rx_mac_buf_ring = false, + .vdev_start_delay = false, + .fixed_fw_mem = false, + .smp2p_wow_exit = false, + + .interface_modes = BIT(NL80211_IFTYPE_STATION) | + BIT(NL80211_IFTYPE_AP) | + BIT(NL80211_IFTYPE_MESH_POINT), + .supports_monitor = true, + + .idle_ps = false, + .cold_boot_calib = true, + .download_calib = true, + .supports_suspend = false, + .tcl_ring_retry = true, + .reoq_lut_support = true, + .supports_shadow_regs = false, + + .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), + .num_tcl_banks = 48, + .max_tx_ring = 4, + .static_window_map = true, + + .wmi_init = ath12k_wmi_init_ipq5332, + + .hal_ops = &hal_qcn6432_ops, + + .supports_ap_ps = true, + .credit_flow = false, + .alloc_cacheable_memory = true, + .spectral = { + .fft_sz = 7, + .fft_pad_sz = 0, + .summary_pad_sz = 16, + .fft_hdr_len = 24, + .max_fft_bins = 512, + .fragment_160mhz = false, + }, + .max_mlo_peer = ATH12K_MAX_MLO_PEER, + .num_local_link = 0, + .m3_fw_support = false, + .compact_rx_tlv = true, + .send_platform_model = true, + .en_fwlog = false, + .support_umac_reset = false, + .en_qdsslog = true, + .fw_mem_mode = ATH12K_QMI_TARGET_MEM_MODE, + .is_plink_preferable = true, }, }; +void ath12k_dp_reset_interrupt_mask(struct ath12k_base *ab) +{ + struct ath12k_hw_ring_mask *ring_mask = ab->hw_params->ring_mask; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *umac_reset = &ag->mlo_umac_reset; + int i; + + if (ag->mlo_umac_reset.is_intr_bkup) + return; + + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { + umac_reset->intr_bkup.tx[i] = ring_mask->tx[i]; + + umac_reset->intr_bkup.rx_mon_dest[i] = ring_mask->rx_mon_dest[i]; + umac_reset->intr_bkup.rx[i] = ring_mask->rx[i]; + umac_reset->intr_bkup.rx_err[i] = ring_mask->rx_err[i]; + umac_reset->intr_bkup.rx_wbm_rel[i] = ring_mask->rx_wbm_rel[i]; + umac_reset->intr_bkup.reo_status[i] = ring_mask->reo_status[i]; + umac_reset->intr_bkup.host2rxdma[i] = ring_mask->host2rxdma[i]; + umac_reset->intr_bkup.tx_mon_dest[i] = ring_mask->tx_mon_dest[i]; + + ring_mask->tx[i] = 0; + ring_mask->rx_mon_dest[i] = 0; + ring_mask->rx[i] = 0; + ring_mask->rx_err[i] = 0; + ring_mask->rx_wbm_rel[i] = 0; + ring_mask->reo_status[i] = 0; + ring_mask->host2rxdma[i] = 0; + ring_mask->tx_mon_dest[i] = 0; + } + + ag->mlo_umac_reset.is_intr_bkup = true; +} + +void ath12k_dp_restore_interrupt_mask(struct ath12k_base *ab) +{ + struct ath12k_hw_ring_mask *ring_mask = ab->hw_params->ring_mask; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *umac_reset = &ag->mlo_umac_reset; + int i; + + if (!ag->mlo_umac_reset.is_intr_bkup) + return; + + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { + ring_mask->tx[i] = umac_reset->intr_bkup.tx[i]; + ring_mask->rx_mon_dest[i] = umac_reset->intr_bkup.rx_mon_dest[i]; + ring_mask->rx[i] = umac_reset->intr_bkup.rx[i]; + ring_mask->rx_err[i] = umac_reset->intr_bkup.rx_err[i]; + ring_mask->rx_wbm_rel[i] = umac_reset->intr_bkup.rx_wbm_rel[i]; + ring_mask->reo_status[i] = umac_reset->intr_bkup.reo_status[i]; + ring_mask->host2rxdma[i] = umac_reset->intr_bkup.host2rxdma[i]; + ring_mask->tx_mon_dest[i] = umac_reset->intr_bkup.tx_mon_dest[i]; + } + + ag->mlo_umac_reset.is_intr_bkup = false; + +} + int ath12k_hw_init(struct ath12k_base *ab) { const struct ath12k_hw_params *hw_params = NULL; @@ -1039,3 +2000,4 @@ return 0; } + diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/hw.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hw.h --- linux-6.4/drivers/net/wireless/ath/ath12k/hw.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/hw.h 2024-03-18 14:40:14.851741333 +0100 @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH12K_HW_H @@ -14,10 +14,17 @@ /* Target configuration defines */ +#ifdef CONFIG_ATH12K_MEM_PROFILE_512M +/* Num VDEVS per radio */ +#define TARGET_NUM_VDEVS (8 + 1) +#define ATH12K_QMI_TARGET_MEM_MODE ATH12K_QMI_TARGET_MEM_MODE_512M +#else /* Num VDEVS per radio */ #define TARGET_NUM_VDEVS (16 + 1) +#define ATH12K_QMI_TARGET_MEM_MODE ATH12K_QMI_TARGET_MEM_MODE_DEFAULT +#endif -#define TARGET_NUM_PEERS_PDEV (512 + TARGET_NUM_VDEVS) +#define TARGET_NUM_PEERS_PDEV (TARGET_NUM_STATIONS + TARGET_NUM_VDEVS) /* Num of peers for Single Radio mode */ #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV) @@ -29,7 +36,7 @@ #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV) /* Max num of stations (per radio) */ -#define TARGET_NUM_STATIONS 512 +#define TARGET_NUM_STATIONS 128 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x #define TARGET_NUM_PEER_KEYS 2 @@ -66,8 +73,14 @@ #define TARGET_NUM_WDS_ENTRIES 32 #define TARGET_DMA_BURST_SIZE 1 #define TARGET_RX_BATCHMODE 1 +#define TARGET_EMA_MAX_PROFILE_PERIOD 8 +#define TARGET_RX_PEER_METADATA_VER_V1A 2 +#define TARGET_RX_PEER_METADATA_VER_V1B 3 + +#define ATH12K_HW_DEFAULT_QUEUE 0 #define ATH12K_HW_MAX_QUEUES 4 +#define ATH12K_HW_MAX_QUEUES_PPEDS 1 #define ATH12K_QUEUE_LEN 4096 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 @@ -76,11 +89,20 @@ #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD" #define ATH12K_BOARD_API2_FILE "board-2.bin" +#define ATH12K_BOARD_OVERRIDE_FILE "board-id-override.txt" #define ATH12K_DEFAULT_BOARD_FILE "board.bin" #define ATH12K_DEFAULT_CAL_FILE "caldata.bin" +#define ATH12K_QMI_DEF_CAL_FILE_PREFIX "caldata_" +#define ATH12K_QMI_DEF_CAL_FILE_SUFFIX ".bin" #define ATH12K_AMSS_FILE "amss.bin" +#define ATH12K_AMSS_DUALMAC_FILE "amss_dualmac.bin" #define ATH12K_M3_FILE "m3.bin" #define ATH12K_REGDB_FILE_NAME "regdb.bin" +#define ATH12K_REGDB_BINARY "regdb" +#define ATH12K_RXGAINLUT_FILE_PREFIX "rxgainlut.b" +#define ATH12K_RXGAINLUT_FILE "rxgainlut.bin" +#define ATH12K_DEFAULT_ID 255 +#define ATH12K_FW_CFG_FILE "firmware.dat" enum ath12k_hw_rate_cck { ATH12K_HW_RATE_CCK_LP_11M = 0, @@ -105,24 +127,34 @@ enum ath12k_bus { ATH12K_BUS_PCI, + ATH12K_BUS_AHB, + ATH12K_BUS_HYBRID, }; -#define ATH12K_EXT_IRQ_GRP_NUM_MAX 11 - +/* Regular 12 Host DP interrupts + 3 PPEDS interrupts + 1 DP UMAC RESET interrupt*/ +#define ATH12K_EXT_IRQ_DP_NUM_VECTORS 16 +#define ATH12K_EXT_IRQ_GRP_NUM_MAX(ab)\ + ((ab)->hw_params->ext_irq_grp_num_max) struct hal_rx_desc; struct hal_tcl_data_cmd; struct htt_rx_ring_tlv_filter; enum hal_encrypt_type; struct ath12k_hw_ring_mask { - u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; - u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; - u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; - u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX]; - u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX]; - u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; - u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX]; - u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; + u8 tx[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 rx_mon_dest[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 rx[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 rx_err[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 rx_wbm_rel[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 reo_status[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 host2rxdma[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 tx_mon_dest[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 ppe2tcl[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; + u8 reo2ppe[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + u8 wbm2sw6_ppeds_tx_cmpln[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; +#endif + u8 umac_dp_reset[ATH12K_EXT_IRQ_DP_NUM_VECTORS]; }; struct ath12k_hw_hal_params { @@ -133,6 +165,7 @@ struct ath12k_hw_params { const char *name; u16 hw_rev; + u32 bdf_addr; struct { const char *dir; @@ -146,8 +179,10 @@ bool internal_sleep_clock:1; const struct ath12k_hw_ops *hw_ops; - const struct ath12k_hw_ring_mask *ring_mask; + struct ath12k_hw_ring_mask *ring_mask; const struct ath12k_hw_regs *regs; + u8 ext_irq_grp_num_max; + u8 route_wbm_release; const struct ce_attr *host_ce_config; u32 ce_count; @@ -164,10 +199,21 @@ bool rx_mac_buf_ring:1; bool vdev_start_delay:1; + struct { + u8 fft_sz; + u8 fft_pad_sz; + u8 summary_pad_sz; + u8 fft_hdr_len; + u16 max_fft_bins; + bool fragment_160mhz; + } spectral; + u16 interface_modes; bool supports_monitor:1; + bool supports_tx_monitor; bool idle_ps:1; + bool cold_boot_calib:1; bool download_calib:1; bool supports_suspend:1; bool tcl_ring_retry:1; @@ -177,6 +223,7 @@ u32 hal_desc_sz; u32 num_tcl_banks; u32 max_tx_ring; + bool static_window_map; const struct mhi_controller_config *mhi_config; @@ -184,6 +231,30 @@ struct ath12k_wmi_resource_config_arg *config); const struct hal_ops *hal_ops; + + u64 qmi_cnss_feature_bitmap; + + bool fix_l1ss; + bool supports_ap_ps; + bool credit_flow; + bool alloc_cacheable_memory; + u16 max_mlo_peer; + u8 num_local_link; + const struct ce_ie_addr *ce_ie_addr; + bool smp2p_wow_exit; + bool fixed_fw_mem; + bool m3_fw_support; + bool send_platform_model; + bool en_fwlog; + bool en_qdsslog; + const struct ce_remap *ce_remap; + const struct cmem_remap *cmem_remap; + bool compact_rx_tlv; + bool support_ce_manual_poll; + const struct pmm_remap *pmm_remap; + bool support_umac_reset; + int fw_mem_mode; + bool is_plink_preferable; }; struct ath12k_hw_ops { @@ -234,12 +305,40 @@ ATH12K_BD_IE_BOARD_DATA = 1, }; +enum ath12k_bd_ie_regdb_type { + ATH12K_BD_IE_REGDB_NAME = 0, + ATH12K_BD_IE_REGDB_DATA = 1, +}; + +enum ath12k_bd_ie_rxgainlut_type { + ATH12K_BD_IE_RXGAINLUT_NAME = 0, + ATH12K_BD_IE_RXGAINLUT_DATA = 1, +}; + enum ath12k_bd_ie_type { /* contains sub IEs of enum ath12k_bd_ie_board_type */ ATH12K_BD_IE_BOARD = 0, - ATH12K_BD_IE_BOARD_EXT = 1, + ATH12K_BD_IE_REGDB = 1, + ATH12K_BD_IE_BOARD_EXT = 2, + ATH12K_BD_IE_RXGAINLUT = 3, }; +static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type) +{ + switch (type) { + case ATH12K_BD_IE_BOARD: + return "board data"; + case ATH12K_BD_IE_REGDB: + return "regdb data"; + case ATH12K_BD_IE_BOARD_EXT: + return "board data ext"; + case ATH12K_BD_IE_RXGAINLUT: + return "rxgainlut data"; + } + + return "unknown"; +} + struct ath12k_hw_regs { u32 hal_tcl1_ring_id; u32 hal_tcl1_ring_misc; @@ -251,9 +350,16 @@ u32 hal_tcl1_ring_msi1_base_msb; u32 hal_tcl1_ring_msi1_data; u32 hal_tcl_ring_base_lsb; + u32 hal_tcl1_ring_base_lsb; + u32 hal_tcl1_ring_base_msb; + u32 hal_tcl2_ring_base_lsb; u32 hal_tcl_status_ring_base_lsb; + u32 hal_reo1_qdesc_addr_read; + u32 hal_reo1_qdesc_max_peerid; + u32 hal_ppe_rel_ring_base; + u32 hal_wbm_idle_ring_base_lsb; u32 hal_wbm_idle_ring_misc_addr; u32 hal_wbm_r0_idle_list_cntl_addr; @@ -274,9 +380,14 @@ u32 pcie_qserdes_sysclk_en_sel; u32 pcie_pcs_osc_dtct_config_base; - u32 hal_ppe_rel_ring_base; + u32 hal_umac_ce0_src_reg_base; + u32 hal_umac_ce0_dest_reg_base; + u32 hal_umac_ce1_src_reg_base; + u32 hal_umac_ce1_dest_reg_base; u32 hal_reo2_ring_base; + u32 hal_reo2ppe_ring_base; + u32 hal_tcl_ppe2tcl_ring_base_lsb; u32 hal_reo1_misc_ctrl_addr; u32 hal_reo1_sw_cookie_cfg0; u32 hal_reo1_sw_cookie_cfg1; diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/mac.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mac.c --- linux-6.4/drivers/net/wireless/ath/ath12k/mac.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mac.c 2024-04-19 16:04:28.957735776 +0200 @@ -5,7 +5,15 @@ */ #include +#include #include +#include +#include +#include +#include +#include +#include + #include "mac.h" #include "core.h" #include "debug.h" @@ -13,7 +21,19 @@ #include "hw.h" #include "dp_tx.h" #include "dp_rx.h" +#include "testmode.h" #include "peer.h" +#include "debugfs_sta.h" +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT +#include "bondif.h" +#endif + +#define IEEE80211_EHT_PPE_THRES_NSS_POS 0 +#define IEEE80211_EHT_PPE_THRES_NSS_MASK 0xf +#define IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_MASK 0x1f0 +#define IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_POS 4 +#define IEEE80211_EHT_PPE_THRES_INFO_PPET_SIZE 3 +#define IEEE80211_EHT_PPE_THRES_INFO_HEADER_SIZE 9 #define CHAN2G(_channel, _freq, _flags) { \ .band = NL80211_BAND_2GHZ, \ @@ -42,6 +62,16 @@ .max_power = 30, \ } +static void ath12k_mac_remove_link_interface(struct ieee80211_hw *hw, + struct ath12k_link_vif *arvif); + +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT +int ath12k_mac_op_change_vif_links(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + u16 old_links, u16 new_links, + struct ieee80211_bss_conf *old[IEEE80211_MLD_MAX_NUM_LINKS]); +extern int g_bonded_interface_model; +#endif static const struct ieee80211_channel ath12k_2ghz_channels[] = { CHAN2G(1, 2412, 0), CHAN2G(2, 2417, 0), @@ -87,10 +117,12 @@ CHAN5G(165, 5825, 0), CHAN5G(169, 5845, 0), CHAN5G(173, 5865, 0), + CHAN5G(177, 5885, 0), }; static const struct ieee80211_channel ath12k_6ghz_channels[] = { CHAN6G(1, 5955, 0), + CHAN6G(2, 5935, 0), CHAN6G(5, 5975, 0), CHAN6G(9, 5995, 0), CHAN6G(13, 6015, 0), @@ -182,32 +214,35 @@ [NL80211_BAND_2GHZ] = { [NL80211_CHAN_WIDTH_5] = MODE_UNKNOWN, [NL80211_CHAN_WIDTH_10] = MODE_UNKNOWN, - [NL80211_CHAN_WIDTH_20_NOHT] = MODE_11AX_HE20_2G, - [NL80211_CHAN_WIDTH_20] = MODE_11AX_HE20_2G, - [NL80211_CHAN_WIDTH_40] = MODE_11AX_HE40_2G, - [NL80211_CHAN_WIDTH_80] = MODE_11AX_HE80_2G, + [NL80211_CHAN_WIDTH_20_NOHT] = MODE_11BE_EHT20_2G, + [NL80211_CHAN_WIDTH_20] = MODE_11BE_EHT20_2G, + [NL80211_CHAN_WIDTH_40] = MODE_11BE_EHT40_2G, + [NL80211_CHAN_WIDTH_80] = MODE_UNKNOWN, [NL80211_CHAN_WIDTH_80P80] = MODE_UNKNOWN, [NL80211_CHAN_WIDTH_160] = MODE_UNKNOWN, + [NL80211_CHAN_WIDTH_320] = MODE_UNKNOWN, }, [NL80211_BAND_5GHZ] = { [NL80211_CHAN_WIDTH_5] = MODE_UNKNOWN, [NL80211_CHAN_WIDTH_10] = MODE_UNKNOWN, - [NL80211_CHAN_WIDTH_20_NOHT] = MODE_11AX_HE20, - [NL80211_CHAN_WIDTH_20] = MODE_11AX_HE20, - [NL80211_CHAN_WIDTH_40] = MODE_11AX_HE40, - [NL80211_CHAN_WIDTH_80] = MODE_11AX_HE80, - [NL80211_CHAN_WIDTH_160] = MODE_11AX_HE160, - [NL80211_CHAN_WIDTH_80P80] = MODE_11AX_HE80_80, + [NL80211_CHAN_WIDTH_20_NOHT] = MODE_11BE_EHT20, + [NL80211_CHAN_WIDTH_20] = MODE_11BE_EHT20, + [NL80211_CHAN_WIDTH_40] = MODE_11BE_EHT40, + [NL80211_CHAN_WIDTH_80] = MODE_11BE_EHT80, + [NL80211_CHAN_WIDTH_160] = MODE_11BE_EHT160, + [NL80211_CHAN_WIDTH_80P80] = MODE_11BE_EHT80_80, + [NL80211_CHAN_WIDTH_320] = MODE_11BE_EHT320, }, [NL80211_BAND_6GHZ] = { [NL80211_CHAN_WIDTH_5] = MODE_UNKNOWN, [NL80211_CHAN_WIDTH_10] = MODE_UNKNOWN, - [NL80211_CHAN_WIDTH_20_NOHT] = MODE_11AX_HE20, - [NL80211_CHAN_WIDTH_20] = MODE_11AX_HE20, - [NL80211_CHAN_WIDTH_40] = MODE_11AX_HE40, - [NL80211_CHAN_WIDTH_80] = MODE_11AX_HE80, - [NL80211_CHAN_WIDTH_160] = MODE_11AX_HE160, - [NL80211_CHAN_WIDTH_80P80] = MODE_11AX_HE80_80, + [NL80211_CHAN_WIDTH_20_NOHT] = MODE_11BE_EHT20, + [NL80211_CHAN_WIDTH_20] = MODE_11BE_EHT20, + [NL80211_CHAN_WIDTH_40] = MODE_11BE_EHT40, + [NL80211_CHAN_WIDTH_80] = MODE_11BE_EHT80, + [NL80211_CHAN_WIDTH_160] = MODE_11BE_EHT160, + [NL80211_CHAN_WIDTH_80P80] = MODE_11BE_EHT80_80, + [NL80211_CHAN_WIDTH_320] = MODE_11BE_EHT320, }, }; @@ -238,8 +273,162 @@ [WLAN_HT_CAP_SM_PS_DISABLED] = WMI_PEER_SMPS_PS_NONE, }; -static int ath12k_start_vdev_delay(struct ieee80211_hw *hw, +static int ath12k_start_vdev_delay(struct ath12k *ar, struct ieee80211_vif *vif); +static void ath12k_update_bcn_template_work(struct work_struct *work); +static void ath12k_update_obss_color_notify_work(struct work_struct *work); +static void ath12k_mac_remove_link_interface(struct ieee80211_hw *hw, + struct ath12k_link_vif *arvif); +static int ath12k_fw_stats_request(struct ath12k *ar, + struct stats_request_params *req_param); + +enum nl80211_he_ru_alloc ath12k_mac_phy_he_ru_to_nl80211_he_ru_alloc(u16 ru_phy) +{ + enum nl80211_he_ru_alloc ret; + + switch (ru_phy) { + case RU_26: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; + break; + case RU_52: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; + break; + case RU_106: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; + break; + case RU_242: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; + break; + case RU_484: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; + break; + case RU_996: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; + break; + default: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; + break; + } + + return ret; +} + +enum nl80211_he_ru_alloc ath12k_mac_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones) +{ + enum nl80211_he_ru_alloc ret; + + switch (ru_tones) { + case 26: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; + break; + case 52: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_52; + break; + case 106: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_106; + break; + case 242: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_242; + break; + case 484: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_484; + break; + case 996: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_996; + break; + case (996 * 2): + ret = NL80211_RATE_INFO_HE_RU_ALLOC_2x996; + break; + default: + ret = NL80211_RATE_INFO_HE_RU_ALLOC_26; + break; + } + + return ret; +} + +enum nl80211_eht_ru_alloc ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(u16 ru_tones) +{ + enum nl80211_eht_ru_alloc ret; + + switch (ru_tones) { + case 26: + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_26; + break; + case 52: + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_52; + break; + case (52 + 26): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_52P26; + break; + case 106: + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_106; + break; + case (106 + 26): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_106P26; + break; + case 242: + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_242; + break; + case 484: + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_484; + break; + case (484 + 242): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_484P242; + break; + case 996: + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_996; + break; + case (996 + 484): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_996P484; + break; + case (996 + 484 + 242): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_996P484P242; + break; + case (996 * 2): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_2x996; + break; + case (996 * 2 + 484): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_2x996P484; + break; + case (996 * 3): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_3x996; + break; + case (996 * 3 + 484): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_3x996P484; + break; + case (996 * 4): + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_4x996; + break; + default: + ret = NL80211_RATE_INFO_EHT_RU_ALLOC_26; + break; + } + + return ret; +} + +enum nl80211_he_gi ath12k_mac_he_gi_to_nl80211_he_gi(u8 sgi) +{ + enum nl80211_he_gi ret; + + switch (sgi) { + case RX_MSDU_START_SGI_0_8_US: + ret = NL80211_RATE_INFO_HE_GI_0_8; + break; + case RX_MSDU_START_SGI_1_6_US: + ret = NL80211_RATE_INFO_HE_GI_1_6; + break; + case RX_MSDU_START_SGI_3_2_US: + ret = NL80211_RATE_INFO_HE_GI_3_2; + break; + default: + ret = NL80211_RATE_INFO_HE_GI_0_8; + break; + } + + return ret; +} static const char *ath12k_mac_phymode_str(enum wmi_phy_mode mode) { @@ -292,6 +481,24 @@ return "11ax-he40-2g"; case MODE_11AX_HE80_2G: return "11ax-he80-2g"; + case MODE_11BE_EHT20: + return "11be-eht20"; + case MODE_11BE_EHT40: + return "11be-eht40"; + case MODE_11BE_EHT80: + return "11be-eht80"; + case MODE_11BE_EHT80_80: + return "11be-eht80+80"; + case MODE_11BE_EHT160: + return "11be-eht160"; + case MODE_11BE_EHT160_160: + return "11be-eht160+160"; + case MODE_11BE_EHT320: + return "11be-eht320"; + case MODE_11BE_EHT20_2G: + return "11be-eht20-2g"; + case MODE_11BE_EHT40_2G: + return "11be-eht40-2g"; case MODE_UNKNOWN: /* skip */ break; @@ -322,6 +529,8 @@ case ATH12K_BW_160: ret = RATE_INFO_BW_160; break; + case ATH12K_BW_320: + ret = RATE_INFO_BW_320; } return ret; @@ -338,6 +547,8 @@ return ATH12K_BW_80; case RATE_INFO_BW_160: return ATH12K_BW_160; + case RATE_INFO_BW_320: + return ATH12K_BW_320; default: return ATH12K_BW_20; } @@ -368,6 +579,19 @@ return -EINVAL; } +static int get_num_chains(u32 mask) +{ + int num_chains = 0; + + while (mask) { + if (mask & BIT(0)) + num_chains++; + mask >>= 1; + } + + return num_chains; +} + u8 ath12k_mac_bitrate_to_idx(const struct ieee80211_supported_band *sband, u32 bitrate) { @@ -381,7 +605,7 @@ } static u32 -ath12k_mac_max_ht_nss(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN]) +ath12k_mac_max_ht_nss(const u8 *ht_mcs_mask) { int nss; @@ -393,7 +617,7 @@ } static u32 -ath12k_mac_max_vht_nss(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX]) +ath12k_mac_max_vht_nss(const u16 *vht_mcs_mask) { int nss; @@ -404,6 +628,42 @@ return 1; } +static u32 +ath12k_mac_max_he_nss(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) +{ + int nss; + + for (nss = NL80211_HE_NSS_MAX - 1; nss >= 0; nss--) + if (he_mcs_mask[nss]) + return nss + 1; + + return 1; +} + +static u32 +ath12k_mac_max_eht_nss(const u16 eht_mcs_mask[NL80211_EHT_NSS_MAX]) +{ + int nss; + + for (nss = NL80211_EHT_NSS_MAX - 1; nss >= 0; nss--) + if (eht_mcs_mask[nss]) + return nss + 1; + + return 1; +} + +static u32 +ath12k_mac_max_eht_mcs_nss(const u8 *eht_mcs, int eht_mcs_set_size) +{ + int i; + u8 nss = 0; + + for (i = 0; i < eht_mcs_set_size; i++) + nss = max(nss, u8_get_bits(eht_mcs[i], IEEE80211_EHT_MCS_NSS_RX)); + + return nss; +} + static u8 ath12k_parse_mpdudensity(u8 mpdudensity) { /* From IEEE Std 802.11-2020 defined values for "Minimum MPDU Start Spacing": @@ -440,12 +700,26 @@ } static int ath12k_mac_vif_chan(struct ieee80211_vif *vif, - struct cfg80211_chan_def *def) + struct cfg80211_chan_def *def, + u8 link_id) { + struct ieee80211_bss_conf *link_conf; struct ieee80211_chanctx_conf *conf; + /* non-MLO connection, link id 0 pointer to def link */ + if (!vif->link_conf[link_id]) + return -ENOENT; + rcu_read_lock(); - conf = rcu_dereference(vif->bss_conf.chanctx_conf); + + link_conf = rcu_dereference(vif->link_conf[link_id]); + + if (!link_conf) { + rcu_read_unlock(); + return -ENOENT; + } + + conf = rcu_dereference(link_conf->chanctx_conf); if (!conf) { rcu_read_unlock(); return -ENOENT; @@ -457,6 +731,72 @@ return 0; } +static int ath12k_mac_get_max_he_mcs_map(u16 mcs_map, int nss) +{ + switch ((mcs_map >> (2 * nss)) & 0x3) { + case IEEE80211_HE_MCS_SUPPORT_0_7: return BIT(8) - 1; + case IEEE80211_HE_MCS_SUPPORT_0_9: return BIT(10) - 1; + case IEEE80211_HE_MCS_SUPPORT_0_11: return BIT(12) - 1; + } + return 0; +} + +static u16 ath12k_peer_assoc_h_he_limit(u16 tx_mcs_set, + const u16 he_mcs_limit[NL80211_HE_NSS_MAX]) +{ + int idx_limit; + int nss; + u16 mcs_map; + u16 mcs; + + for (nss = 0; nss < NL80211_HE_NSS_MAX; nss++) { + mcs_map = ath12k_mac_get_max_he_mcs_map(tx_mcs_set, nss) & + he_mcs_limit[nss]; + + if (mcs_map) + idx_limit = fls(mcs_map) - 1; + else + idx_limit = -1; + + switch (idx_limit) { + case 0 ... 7: + mcs = IEEE80211_HE_MCS_SUPPORT_0_7; + break; + case 8: + case 9: + mcs = IEEE80211_HE_MCS_SUPPORT_0_9; + break; + case 10: + case 11: + mcs = IEEE80211_HE_MCS_SUPPORT_0_11; + break; + default: + WARN_ON(1); + fallthrough; + case -1: + mcs = IEEE80211_HE_MCS_NOT_SUPPORTED; + break; + } + + tx_mcs_set &= ~(0x3 << (nss * 2)); + tx_mcs_set |= mcs << (nss * 2); + } + + return tx_mcs_set; +} + +static bool +ath12k_peer_assoc_h_he_masked(const u16 he_mcs_mask[NL80211_HE_NSS_MAX]) +{ + int nss; + + for (nss = 0; nss < NL80211_HE_NSS_MAX; nss++) + if (he_mcs_mask[nss]) + return false; + + return true; +} + static bool ath12k_mac_bitrate_is_cck(int bitrate) { switch (bitrate) { @@ -498,46 +838,94 @@ (ath12k_mac_bitrate_is_cck(bitrate) ? BIT(7) : 0); } +struct +ieee80211_bss_conf *ath12k_get_link_bss_conf(struct ath12k_link_vif *arvif) +{ + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ieee80211_bss_conf *link_conf = NULL; + + WARN_ON(!rcu_read_lock_held()); + + if (arvif->link_id > IEEE80211_MLD_MAX_NUM_LINKS) + return NULL; + + link_conf = rcu_dereference(vif->link_conf[arvif->link_id]); + + return link_conf; +} + +static struct +ieee80211_link_sta *ath12k_get_link_sta(struct ath12k_link_sta *arsta) +{ + struct ieee80211_sta *sta; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + WARN_ON(!rcu_read_lock_held()); + + if (arsta->link_id > IEEE80211_MLD_MAX_NUM_LINKS) + return NULL; + + link_sta = rcu_dereference(sta->link[arsta->link_id]); + + return link_sta; +} + static void ath12k_get_arvif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) { struct ath12k_vif_iter *arvif_iter = data; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + u8 link_id; + + /* TODO Revisit lock usage for ahvif->link. Currently this is + * used with vif protected by rcu lock and since the ahvif->links_map + * or link wont be modified it is safe to access below without its mutex + */ + for_each_set_bit(link_id, &ahvif->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; - if (arvif->vdev_id == arvif_iter->vdev_id) + if (WARN_ON(arvif == NULL)) + continue; + + if ((arvif->vdev_id == arvif_iter->vdev_id) && + (arvif->ar == arvif_iter->ar)) { arvif_iter->arvif = arvif; + break; + } + } } -struct ath12k_vif *ath12k_mac_get_arvif(struct ath12k *ar, u32 vdev_id) +struct ath12k_link_vif *ath12k_mac_get_arvif(struct ath12k *ar, u32 vdev_id) { struct ath12k_vif_iter arvif_iter = {}; u32 flags; arvif_iter.vdev_id = vdev_id; + arvif_iter.ar = ar; flags = IEEE80211_IFACE_ITER_RESUME_ALL; - ieee80211_iterate_active_interfaces_atomic(ar->hw, + ieee80211_iterate_active_interfaces_atomic(ar->ah->hw, flags, ath12k_get_arvif_iter, &arvif_iter); - if (!arvif_iter.arvif) { - ath12k_warn(ar->ab, "No VIF found for vdev %d\n", vdev_id); - return NULL; - } - return arvif_iter.arvif; } -struct ath12k_vif *ath12k_mac_get_arvif_by_vdev_id(struct ath12k_base *ab, +struct ath12k_link_vif *ath12k_mac_get_arvif_by_vdev_id(struct ath12k_base *ab, u32 vdev_id) { int i; struct ath12k_pdev *pdev; - struct ath12k_vif *arvif; + struct ath12k_link_vif *arvif; for (i = 0; i < ab->num_radios; i++) { pdev = rcu_dereference(ab->pdevs_active[i]); - if (pdev && pdev->ar) { + if (pdev && pdev->ar && + (pdev->ar->allocated_vdev_map & (1LL << vdev_id))) { arvif = ath12k_mac_get_arvif(pdev->ar, vdev_id); if (arvif) return arvif; @@ -547,6 +935,80 @@ return NULL; } +static struct ath12k *ath12k_mac_get_ar_by_agile_chandef(struct ieee80211_hw *hw, + enum nl80211_band band) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + int i; + + if (band != NL80211_BAND_5GHZ) + return NULL; + + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { + if (!ar->agile_chandef.chan) + continue; + if (ar->agile_chandef.chan->center_freq > ar->chan_info.low_freq && + ar->agile_chandef.chan->center_freq < ar->chan_info.high_freq) + return ar; + ar++; + } + return NULL; +} + +static struct ath12k *ath12k_mac_get_ar_by_chan(struct ieee80211_hw *hw, + struct ieee80211_channel *channel) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + int i; + + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { + if (channel->center_freq >= ar->chan_info.low_freq && + channel->center_freq <= ar->chan_info.high_freq) + return ar; + ar++; + } + return NULL; +} + +static struct ath12k *ath12k_get_ar_by_ctx(struct ieee80211_hw *hw, + struct ieee80211_chanctx_conf *ctx) +{ + if (!ctx) + return NULL; + + return ath12k_mac_get_ar_by_chan(hw, ctx->def.chan); +} + +struct ath12k *ath12k_get_ar_by_vif(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u8 link_id) +{ + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar = NULL; + + lockdep_assert_held(&ah->conf_mutex); + + if (!vif) + return NULL; + + ahvif = ath12k_vif_to_ahvif(vif); + + if (!(ahvif->links_map & BIT(link_id))) + return NULL; + + arvif = ahvif->link[link_id]; + + if (arvif && arvif->is_created) + ar = arvif->ar; + + return ar; +} + struct ath12k *ath12k_mac_get_ar_by_vdev_id(struct ath12k_base *ab, u32 vdev_id) { int i; @@ -577,6 +1039,9 @@ return NULL; for (i = 0; i < ab->num_radios; i++) { + if (ab->fw_mode == ATH12K_FIRMWARE_MODE_FTM) + pdev = &ab->pdevs[i]; + else pdev = rcu_dereference(ab->pdevs_active[i]); if (pdev && pdev->pdev_id == pdev_id) @@ -586,6 +1051,19 @@ return NULL; } +bool ath12k_mac_is_ml_arvif(struct ath12k_link_vif *arvif) +{ + struct ath12k *ar = arvif->ar; + struct ath12k_vif *ahvif = arvif->ahvif; + + lockdep_assert_held(&ar->conf_mutex); + + if (ahvif->vif->valid_links & BIT(arvif->link_id)) + return true; + + return false; +} + static void ath12k_pdev_caps_update(struct ath12k *ar) { struct ath12k_base *ab = ar->ab; @@ -601,13 +1079,14 @@ ar->txpower_limit_2g = ar->max_tx_power; ar->txpower_limit_5g = ar->max_tx_power; + ar->txpower_limit_6g = ar->max_tx_power; ar->txpower_scale = WMI_HOST_TP_SCALE_MAX; } static int ath12k_mac_txpower_recalc(struct ath12k *ar) { struct ath12k_pdev *pdev = ar->pdev; - struct ath12k_vif *arvif; + struct ath12k_link_vif *arvif; int ret, txpower = -1; u32 param; @@ -653,6 +1132,16 @@ ar->txpower_limit_5g = txpower; } + if ((ar->ah->hw->wiphy->bands[NL80211_BAND_6GHZ]) && + ar->txpower_limit_6g != txpower) { + param = WMI_PDEV_PARAM_TXPOWER_LIMIT5G; + ret = ath12k_wmi_pdev_set_param(ar, param, + txpower, ar->pdev->pdev_id); + if (ret) + goto fail; + ar->txpower_limit_6g = txpower; + } + return 0; fail: @@ -661,7 +1150,7 @@ return ret; } -static int ath12k_recalc_rtscts_prot(struct ath12k_vif *arvif) +static int ath12k_recalc_rtscts_prot(struct ath12k_link_vif *arvif) { struct ath12k *ar = arvif->ar; u32 vdev_param, rts_cts; @@ -700,7 +1189,7 @@ return ret; } -static int ath12k_mac_set_kickout(struct ath12k_vif *arvif) +static int ath12k_mac_set_kickout(struct ath12k_link_vif *arvif) { struct ath12k *ar = arvif->ar; u32 param; @@ -745,23 +1234,130 @@ return 0; } +static void ath12k_mac_dec_num_stations(struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k *ar = arvif->ar; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + lockdep_assert_held(&ar->conf_mutex); + + if (!ar->num_stations) + return; + + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA && !sta->tdls) + return; + + ar->num_stations--; +} + +int ath12k_mac_partner_peer_cleanup(struct ath12k_base *ab) +{ + + struct ath12k_base *partner_ab; + struct ath12k *ar; + struct ath12k_hw_group *ag; + struct ath12k_link_vif *arvif; + struct ath12k_vif *ahvif; + struct ieee80211_sta *sta; + struct ieee80211_vif *vif; + struct ath12k_sta *ahsta; + struct ath12k_link_sta *arsta; + struct ath12k_peer *peer, *tmp; + int idx, ret = 0; + u8 link_id; + + ag = ab->ag; + + for (idx = 0; idx < ag->num_chip; idx++) { + partner_ab = ag->ab[idx]; + + if (ab == partner_ab) + continue; + + list_for_each_entry_safe(peer, tmp, &partner_ab->peers, list) { + if (!peer->sta || !peer->mlo || !peer->vif) + continue; + + link_id = peer->link_id; + /* get arsta */ + sta = peer->sta; + ahsta = ath12k_sta_to_ahsta(sta); + arsta = ahsta->link[link_id]; + + /* get arvif */ + vif = peer->vif; + ahvif = (struct ath12k_vif *)vif->drv_priv; + arvif = ahvif->link[link_id]; + + ar = arvif->ar; + if (!ar) + continue; + + mutex_lock(&ar->conf_mutex); + ret = ath12k_peer_delete_send(ar, arvif->vdev_id, arsta->addr); + if (ret) { + mutex_unlock(&ar->conf_mutex); + ath12k_warn(ar->ab, + "failed to delete peer vdev_id %d addr %pM ret %d\n", + arvif->vdev_id, arsta->addr, ret); + continue; + } + ret = ath12k_wait_for_peer_delete_done(ar, arvif->vdev_id, arsta->addr); + if (ret) { + mutex_unlock(&ar->conf_mutex); + continue; + } + + ar->num_peers--; + arvif->num_stations--; + ath12k_mac_dec_num_stations(arvif, arsta); + mutex_unlock(&ar->conf_mutex); + cancel_work_sync(&arsta->update_wk); + } + } + return ret; +} + void ath12k_mac_peer_cleanup_all(struct ath12k *ar) { struct ath12k_peer *peer, *tmp; struct ath12k_base *ab = ar->ab; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_link_vif *arvif, *tmp_vif; lockdep_assert_held(&ar->conf_mutex); + mutex_lock(&ab->tbl_mtx_lock); spin_lock_bh(&ab->base_lock); list_for_each_entry_safe(peer, tmp, &ab->peers, list) { ath12k_dp_rx_peer_tid_cleanup(ar, peer); + ath12k_peer_rhash_delete(ab, peer); list_del(&peer->list); +#ifdef CONFIG_ATH12K_SAWF + if (peer->sawf_ctx_peer.telemetry_peer_ctx) + ath12k_telemetry_peer_ctx_free(peer->sawf_ctx_peer.telemetry_peer_ctx); +#endif kfree(peer); } spin_unlock_bh(&ab->base_lock); + mutex_unlock(&ab->tbl_mtx_lock); + + if (!list_empty(&ab->neighbor_peers)) + ath12k_debugfs_nrp_cleanup_all(ar); ar->num_peers = 0; ar->num_stations = 0; + + if (ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1) { + list_for_each_entry_safe_reverse(arvif, tmp_vif, &ar->arvifs, list) + arvif->num_stations = 0; + } + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "ath12k mac peer cleanup done\n"); } static int ath12k_mac_vdev_setup_sync(struct ath12k *ar) @@ -771,9 +1367,14 @@ if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) return -ESHUTDOWN; + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "ath12k vdev setup timeout %d\n", + ATH12K_VDEV_SETUP_TIMEOUT_HZ); + if (!wait_for_completion_timeout(&ar->vdev_setup_done, - ATH12K_VDEV_SETUP_TIMEOUT_HZ)) + ATH12K_VDEV_SETUP_TIMEOUT_HZ)){ + WARN_ON(1); return -ETIMEDOUT; + } return ar->last_wmi_vdev_start_status ? -EINVAL : 0; } @@ -781,8 +1382,11 @@ static int ath12k_monitor_vdev_up(struct ath12k *ar, int vdev_id) { int ret; + struct vdev_up_params params = { 0 }; - ret = ath12k_wmi_vdev_up(ar, vdev_id, 0, ar->mac_addr); + params.vdev_id = vdev_id; + params.bssid = ar->mac_addr; + ret = ath12k_wmi_vdev_up(ar, ¶ms); if (ret) { ath12k_warn(ar->ab, "failed to put up monitor vdev %i: %d\n", vdev_id, ret); @@ -800,26 +1404,30 @@ struct ieee80211_channel *channel; struct wmi_vdev_start_req_arg arg = {}; int ret; + struct vdev_up_params params = { 0 }; lockdep_assert_held(&ar->conf_mutex); channel = chandef->chan; arg.vdev_id = vdev_id; - arg.freq = channel->center_freq; - arg.band_center_freq1 = chandef->center_freq1; - arg.band_center_freq2 = chandef->center_freq2; - arg.mode = ath12k_phymodes[chandef->chan->band][chandef->width]; - arg.chan_radar = !!(channel->flags & IEEE80211_CHAN_RADAR); - - arg.min_power = 0; - arg.max_power = channel->max_power; - arg.max_reg_power = channel->max_reg_power; - arg.max_antenna_gain = channel->max_antenna_gain; + arg.channel.freq = channel->center_freq; + arg.channel.band_center_freq1 = chandef->center_freq1; + arg.channel.band_center_freq2 = chandef->center_freq2; + arg.channel.mode = ath12k_phymodes[chandef->chan->band][chandef->width]; + arg.channel.chan_radar = + !!(channel->flags & IEEE80211_CHAN_RADAR); + + arg.channel.min_power = 0; + arg.channel.max_power = channel->max_power; + arg.channel.max_reg_power = channel->max_reg_power; + arg.channel.max_antenna_gain = channel->max_antenna_gain; arg.pref_tx_streams = ar->num_tx_chains; arg.pref_rx_streams = ar->num_rx_chains; - arg.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR); + arg.channel.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR); + + arg.ru_punct_bitmap = 0xFFFFFFFF; reinit_completion(&ar->vdev_setup_done); reinit_completion(&ar->vdev_delete_done); @@ -838,7 +1446,9 @@ return ret; } - ret = ath12k_wmi_vdev_up(ar, vdev_id, 0, ar->mac_addr); + params.vdev_id = vdev_id; + params.bssid = ar->mac_addr; + ret = ath12k_wmi_vdev_up(ar, ¶ms); if (ret) { ath12k_warn(ar->ab, "failed to put up monitor vdev %i: %d\n", vdev_id, ret); @@ -885,17 +1495,16 @@ return ret; } -static int ath12k_mac_monitor_vdev_create(struct ath12k *ar) +int ath12k_mac_monitor_vdev_create(struct ath12k *ar) { struct ath12k_pdev *pdev = ar->pdev; struct ath12k_wmi_vdev_create_arg arg = {}; int bit, ret; - u8 tmp_addr[6]; u16 nss; lockdep_assert_held(&ar->conf_mutex); - if (ar->monitor_vdev_created) + if (test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags)) return 0; if (ar->ab->free_vdev_map == 0) { @@ -903,7 +1512,10 @@ return -ENOMEM; } + spin_lock_bh(&ar->ab->base_lock); bit = __ffs64(ar->ab->free_vdev_map); + ar->ab->free_vdev_map &= ~(1LL << bit); + spin_unlock_bh(&ar->ab->base_lock); ar->monitor_vdev_id = bit; @@ -923,10 +1535,13 @@ arg.chains[NL80211_BAND_5GHZ].rx = ar->num_rx_chains; } - ret = ath12k_wmi_vdev_create(ar, tmp_addr, &arg); + ret = ath12k_wmi_vdev_create(ar, ar->mac_addr, &arg); if (ret) { ath12k_warn(ar->ab, "failed to request monitor vdev %i creation: %d\n", ar->monitor_vdev_id, ret); + spin_lock_bh(&ar->ab->base_lock); + ar->ab->free_vdev_map |= 1LL << (ar->monitor_vdev_id); + spin_unlock_bh(&ar->ab->base_lock); ar->monitor_vdev_id = -1; return ret; } @@ -945,23 +1560,23 @@ return ret; ar->allocated_vdev_map |= 1LL << ar->monitor_vdev_id; - ar->ab->free_vdev_map &= ~(1LL << ar->monitor_vdev_id); ar->num_created_vdevs++; - ar->monitor_vdev_created = true; + set_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac monitor vdev %d created\n", ar->monitor_vdev_id); return 0; } -static int ath12k_mac_monitor_vdev_delete(struct ath12k *ar) +int ath12k_mac_monitor_vdev_delete(struct ath12k *ar) { int ret; unsigned long time_left; lockdep_assert_held(&ar->conf_mutex); - if (!ar->monitor_vdev_created) + if (!test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags)) return 0; reinit_completion(&ar->vdev_delete_done); @@ -979,42 +1594,55 @@ ath12k_warn(ar->ab, "Timeout in receiving vdev delete response\n"); } else { ar->allocated_vdev_map &= ~(1LL << ar->monitor_vdev_id); + spin_lock_bh(&ar->ab->base_lock); ar->ab->free_vdev_map |= 1LL << (ar->monitor_vdev_id); ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac monitor vdev %d deleted\n", ar->monitor_vdev_id); + spin_unlock_bh(&ar->ab->base_lock); ar->num_created_vdevs--; ar->monitor_vdev_id = -1; - ar->monitor_vdev_created = false; + clear_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags); } return ret; } -static void +void ath12k_mac_get_any_chandef_iter(struct ieee80211_hw *hw, struct ieee80211_chanctx_conf *conf, void *data) { - struct cfg80211_chan_def **def = data; + struct ath12k_mac_any_chandef_arg *arg = + (struct ath12k_mac_any_chandef_arg *)data; + struct ath12k *ctx_ar, *ar = arg->ar; + + ctx_ar = ath12k_get_ar_by_ctx(ar->ah->hw, conf); - *def = &conf->def; + if (ctx_ar == ar) + arg->def = &conf->def; } -static int ath12k_mac_monitor_start(struct ath12k *ar) +int ath12k_mac_monitor_start(struct ath12k *ar) { - struct cfg80211_chan_def *chandef = NULL; + struct cfg80211_chan_def *chandef; + struct ath12k_mac_any_chandef_arg arg = { .ar = ar, .def = NULL}; int ret; lockdep_assert_held(&ar->conf_mutex); - if (ar->monitor_started) + if (test_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags)) return 0; - ieee80211_iter_chan_contexts_atomic(ar->hw, + ieee80211_iter_chan_contexts_atomic(ar->ah->hw, ath12k_mac_get_any_chandef_iter, - &chandef); + &arg); + chandef = arg.def; if (!chandef) - return 0; + return -EINVAL; + + /* TODO 5G low high split changes */ + if (!ar->mac.sbands[chandef->chan->band].channels) + return -EINVAL; ret = ath12k_mac_monitor_vdev_start(ar, ar->monitor_vdev_id, chandef); if (ret) { @@ -1023,21 +1651,28 @@ return ret; } - ar->monitor_started = true; - ar->num_started_vdevs++; ret = ath12k_dp_tx_htt_monitor_mode_ring_config(ar, false); + if (ret) { + ath12k_warn(ar->ab, + "fail to set monitor filter: %d\n", ret); + return ret; + } + + set_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags); + ar->num_started_vdevs++; + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac monitor started ret %d\n", ret); return ret; } -static int ath12k_mac_monitor_stop(struct ath12k *ar) +int ath12k_mac_monitor_stop(struct ath12k *ar) { int ret; lockdep_assert_held(&ar->conf_mutex); - if (!ar->monitor_started) + if (!test_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags)) return 0; ret = ath12k_mac_monitor_vdev_stop(ar); @@ -1046,7 +1681,7 @@ return ret; } - ar->monitor_started = false; + clear_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags); ar->num_started_vdevs--; ret = ath12k_dp_tx_htt_monitor_mode_ring_config(ar, true); ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac monitor stopped ret %d\n", ret); @@ -1055,92 +1690,421 @@ static int ath12k_mac_op_config(struct ieee80211_hw *hw, u32 changed) { - struct ath12k *ar = hw->priv; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; struct ieee80211_conf *conf = &hw->conf; - int ret = 0; + int ret, i; - mutex_lock(&ar->conf_mutex); + mutex_lock(&ah->conf_mutex); + ar = ah->radio; + + for (i = 0; i < ah->num_radio; i++) { + mutex_lock(&ar->conf_mutex); if (changed & IEEE80211_CONF_CHANGE_MONITOR) { - ar->monitor_conf_enabled = conf->flags & IEEE80211_CONF_MONITOR; - if (ar->monitor_conf_enabled) { - if (ar->monitor_vdev_created) - goto exit; + if (conf->flags & IEEE80211_CONF_MONITOR) { + set_bit(MONITOR_CONF_ENABLED, &ar->monitor_flags); + if (test_bit(MONITOR_VDEV_CREATED, + &ar->monitor_flags)) + goto out; + ret = ath12k_mac_monitor_vdev_create(ar); if (ret) - goto exit; + goto out; ret = ath12k_mac_monitor_start(ar); - if (ret) - goto err_mon_del; + if (ret) { + ath12k_mac_monitor_vdev_delete(ar); + goto out; + } } else { - if (!ar->monitor_vdev_created) - goto exit; + clear_bit(MONITOR_CONF_ENABLED, &ar->monitor_flags); + if (!test_bit(MONITOR_VDEV_CREATED, + &ar->monitor_flags)) + goto out; + ret = ath12k_mac_monitor_stop(ar); if (ret) - goto exit; + goto out; + ath12k_mac_monitor_vdev_delete(ar); } } - -exit: +out: mutex_unlock(&ar->conf_mutex); - return ret; + ar++; + } + + mutex_unlock(&ah->conf_mutex); -err_mon_del: - ath12k_mac_monitor_vdev_delete(ar); - mutex_unlock(&ar->conf_mutex); return ret; } -static int ath12k_mac_setup_bcn_tmpl(struct ath12k_vif *arvif) +static void ath12k_mac_setup_bcn_tmpl_vif_params(struct ath12k_link_vif *arvif, + struct sk_buff *bcn) { - struct ath12k *ar = arvif->ar; - struct ath12k_base *ab = ar->ab; - struct ieee80211_hw *hw = ar->hw; - struct ieee80211_vif *vif = arvif->vif; - struct ieee80211_mutable_offsets offs = {}; - struct sk_buff *bcn; struct ieee80211_mgmt *mgmt; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vht_cap *vht_cap; u8 *ies; - int ret; + const u8 *vht_cap_ie; - if (arvif->vdev_type != WMI_VDEV_TYPE_AP) - return 0; + ies = bcn->data + ieee80211_get_hdrlen_from_skb(bcn); + mgmt = (struct ieee80211_mgmt *)bcn->data; + ies += sizeof(mgmt->u.beacon); - bcn = ieee80211_beacon_get_template(hw, vif, &offs, 0); - if (!bcn) { - ath12k_warn(ab, "failed to get beacon template from mac80211\n"); - return -EPERM; + /* avoid ie parsing if already done for this ahvif */ + if (!ahvif->rsnie_present && + cfg80211_find_ie(WLAN_EID_RSN, ies, (skb_tail_pointer(bcn) - ies))) + ahvif->rsnie_present = true; + + vht_cap_ie = cfg80211_find_ie(WLAN_EID_VHT_CAPABILITY, ies, (skb_tail_pointer(bcn) - ies)); + if (vht_cap_ie && vht_cap_ie[1] >= sizeof(*vht_cap)) { + vht_cap = (void *)(vht_cap_ie + 2); + arvif->vht_cap = vht_cap->vht_cap_info; } + /* avoid ie parsing if already done for this ahvif */ + if (!ahvif->wpaie_present && + cfg80211_find_vendor_ie(WLAN_OUI_MICROSOFT, + WLAN_OUI_TYPE_MICROSOFT_WPA, + ies, (skb_tail_pointer(bcn) - ies))) + ahvif->wpaie_present = true; +} + +static bool ath12k_mac_setup_bcn_tmpl_nontx_vif_params(struct ath12k_link_vif *tx_arvif, + struct ath12k_link_vif *arvif, + struct sk_buff *bcn) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_mgmt *mgmt; + const u8 *ies, *profile, *next_profile; + int ies_len; + + if (arvif == tx_arvif) + return true; + + ahvif->rsnie_present = ahvif->rsnie_present; + ies = bcn->data + ieee80211_get_hdrlen_from_skb(bcn); ies += sizeof(mgmt->u.beacon); + ies_len = skb_tail_pointer(bcn) - ies; - if (cfg80211_find_ie(WLAN_EID_RSN, ies, (skb_tail_pointer(bcn) - ies))) - arvif->rsnie_present = true; + ies = cfg80211_find_ie(WLAN_EID_MULTIPLE_BSSID, ies, ies_len); - if (cfg80211_find_vendor_ie(WLAN_OUI_MICROSOFT, - WLAN_OUI_TYPE_MICROSOFT_WPA, - ies, (skb_tail_pointer(bcn) - ies))) - arvif->wpaie_present = true; + while (ies) { + u8 mbssid_len; - ret = ath12k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn); + ies_len -= (2 + ies[1]); + mbssid_len = ies[1] - 1; + profile = &ies[3]; + + while (mbssid_len) { + u8 profile_len, nie_len; + const u8 *nie; + + profile_len = profile[1]; + next_profile = profile + (2 + profile_len); + mbssid_len -= (2 + profile_len); + + profile += 2; + profile_len -= (2 + profile[1]); + profile += (2 + profile[1]); /* nontx capabilities */ + profile_len -= (2 + profile[1]); + profile += (2 + profile[1]); /* SSID */ + if (profile[2] == ahvif->vif->bss_conf.bssid_index) { + profile_len -= 5; + profile = profile + 5; + + if (cfg80211_find_ie(WLAN_EID_RSN, profile, + profile_len)) + ahvif->rsnie_present = true; + else if (ahvif->rsnie_present) { + nie = cfg80211_find_ext_ie(WLAN_EID_EXT_NON_INHERITANCE, + profile, + profile_len); + if (nie) { + int i; - kfree_skb(bcn); + nie_len = nie[1]; + nie += 2; + for (i = 0; i < nie_len; i++) { + if (nie[i] == + WLAN_EID_RSN) { + ahvif->rsnie_present = false; + break; + } + } + } + } + return true; + } + profile = next_profile; + } + ies = cfg80211_find_ie(WLAN_EID_MULTIPLE_BSSID, profile, + ies_len); + } + + return false; +} + +static int __ath12k_mac_setup_bcn_tmpl(struct ath12k_link_vif *arvif, + struct sk_buff *bcn, + struct ieee80211_mutable_offsets offs, + int ema_idx, int ema_cnt) +{ + struct ath12k *ar = arvif->ar; + u32 ema_param = 0; + + if (ema_cnt) { + ema_param = (ema_cnt << WMI_BEACON_EMA_PARAM_PERIODICITY_SHIFT); + ema_param |= (ema_idx << WMI_BEACON_EMA_PARAM_TMPL_IDX_SHIFT); + ema_param |= ((!ema_idx ? 1 : 0) << + WMI_BEACON_EMA_PARAM_FIRST_TMPL_SHIFT); + ema_param |= ((ema_idx + 1 == ema_cnt ? 1 : 0) << + WMI_BEACON_EMA_PARAM_LAST_TMPL_SHIFT); + } + + return ath12k_wmi_bcn_tmpl(ar, arvif->vdev_id, &offs, bcn, ema_param); +} + +static int ath12k_mac_setup_bcn_tmpl_ema(struct ath12k_link_vif *arvif) +{ + struct ath12k_link_vif *tx_arvif; + struct ath12k_vif *tx_ahvif, *ahvif = arvif->ahvif; + struct ieee80211_ema_beacons *beacons; + struct ieee80211_bss_conf *link; + u8 i = 0; + int ret = 0; + bool found_vdev = false; + + rcu_read_lock(); + link = ath12k_get_link_bss_conf(arvif); + if (!link->mbssid_tx_vif) { + rcu_read_unlock(); + return -1; + } + tx_ahvif = (void *)link->mbssid_tx_vif->drv_priv; + if (!tx_ahvif) { + rcu_read_unlock(); + return -ENOLINK; + } + /* both TX an NON_TX arvif's should be under same ar and hw + * hence current acquired lock's should suffice for opertaing + * with tx arvif also + */ + lockdep_assert_held(&tx_ahvif->ah->conf_mutex); + tx_arvif = tx_ahvif->link[link->mbssid_tx_vif_linkid]; + if (!tx_arvif) { + rcu_read_unlock(); + return -ENOLINK; + } + if (arvif != tx_arvif && !tx_arvif->is_started) { + rcu_read_unlock(); + ath12k_warn(arvif->ar->ab, + "Transmit vif is not started before this non Tx beacon setup for vdev %d\n", + arvif->vdev_id); + return -EINVAL; + } + + lockdep_assert_held(&tx_arvif->ar->conf_mutex); + beacons = ieee80211_beacon_get_template_ema_list(tx_arvif->ar->ah->hw, + tx_ahvif->vif, + tx_arvif->link_id); + rcu_read_unlock(); + if (!beacons || !beacons->cnt) { + ath12k_warn(arvif->ar->ab, + "failed to get ema beacon templates from mac80211\n"); + return -EPERM; + } + + if (tx_arvif == arvif) { + ath12k_mac_setup_bcn_tmpl_vif_params(tx_arvif, + beacons->bcn[0].skb); + found_vdev = true; + } else { + ahvif->wpaie_present = ahvif->wpaie_present; + } + + for (i = 0; i < beacons->cnt; i++) { + if (found_vdev == false) + found_vdev = + ath12k_mac_setup_bcn_tmpl_nontx_vif_params(tx_arvif, + arvif, + beacons->bcn[i].skb); + + ret = __ath12k_mac_setup_bcn_tmpl(tx_arvif, beacons->bcn[i].skb, + beacons->bcn[i].offs, + i, beacons->cnt); + if (ret) { + ath12k_warn(arvif->ar->ab, + "failed to set ema beacon template id %i error %d\n", + i, ret); + break; + } + } + + ieee80211_beacon_free_ema_list(beacons); + return ret; +} + +static int ath12k_mac_setup_bcn_tmpl_non_ema(struct ath12k_link_vif *arvif) +{ + struct ath12k_link_vif *tx_arvif = arvif; + struct ath12k_vif *tx_ahvif = arvif->ahvif; + struct ieee80211_mutable_offsets offs = {}; + struct sk_buff *bcn; + struct ieee80211_bss_conf *link; + int ret; + + rcu_read_lock(); + link = ath12k_get_link_bss_conf(arvif); + if (!link) { + rcu_read_unlock(); + return -ENOLINK; + } + + if (link->mbssid_tx_vif) { + tx_ahvif = (void *)link->mbssid_tx_vif->drv_priv; + if (!tx_ahvif) { + rcu_read_unlock(); + return -ENOLINK; + } + lockdep_assert_held(&tx_ahvif->ah->conf_mutex); + tx_arvif = tx_ahvif->link[link->mbssid_tx_vif_linkid]; + } + + if (!tx_arvif) { + rcu_read_unlock(); + return -ENOLINK; + } + + if (arvif != tx_arvif && !tx_arvif->is_started) { + rcu_read_unlock(); + ath12k_warn(arvif->ar->ab, + "Transmit vif is not started before this non Tx beacon setup for vdev %d\n", + arvif->vdev_id); + return -EINVAL; + } + + lockdep_assert_held(&tx_arvif->ar->conf_mutex); + bcn = ieee80211_beacon_get_template(tx_arvif->ar->ah->hw, tx_ahvif->vif, + &offs, tx_arvif->link_id); + rcu_read_unlock(); + if (!bcn) { + ath12k_warn(arvif->ar->ab, + "failed to get beacon template from mac80211\n"); + return -EPERM; + } + + if (tx_arvif == arvif) + ath12k_mac_setup_bcn_tmpl_vif_params(tx_arvif, bcn); + else + (void) ath12k_mac_setup_bcn_tmpl_nontx_vif_params(tx_arvif, + arvif, + bcn); + + ret = __ath12k_mac_setup_bcn_tmpl(tx_arvif, bcn, offs, 0, 0); if (ret) - ath12k_warn(ab, "failed to submit beacon template command: %d\n", + ath12k_warn(tx_arvif->ar->ab, + "failed to submit beacon template command: %d\n", ret); + kfree_skb(bcn); return ret; } -static void ath12k_control_beaconing(struct ath12k_vif *arvif, +static int ath12k_mac_setup_bcn_tmpl(struct ath12k_link_vif *arvif) +{ + struct ath12k_vif *tx_ahvif, *ahvif = arvif->ahvif; + struct ieee80211_bss_conf *link; + bool is_ema; + + if (ahvif->vdev_type != WMI_VDEV_TYPE_AP) + return 0; + + rcu_read_lock(); + link = ath12k_get_link_bss_conf(arvif); + if (!link) { + rcu_read_unlock(); + return -ENOLINK; + } + if (link->mbssid_tx_vif) { + tx_ahvif = (void *)link->mbssid_tx_vif->drv_priv; + if (ahvif != tx_ahvif && arvif->is_up) { + rcu_read_unlock(); + return 0; + } + } + is_ema = link->ema_ap; + rcu_read_unlock(); + + if (is_ema) + return ath12k_mac_setup_bcn_tmpl_ema(arvif); + else + return ath12k_mac_setup_bcn_tmpl_non_ema(arvif); +} + + +void ath12k_mac_bcn_tx_event(struct ath12k_link_vif *arvif) +{ + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ath12k *ar = arvif->ar; + struct ieee80211_bss_conf* link_conf; + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + ath12k_warn(ar->ab, "unable to access bss link conf in bcn tx event\n"); + return; + } + + if (!link_conf->color_change_active && !arvif->bcca_zero_sent) + return; + + if (link_conf->color_change_active && + ieee80211_beacon_cntdwn_is_complete_mlo(vif, arvif->link_id)) { + arvif->bcca_zero_sent = true; + ieee80211_color_change_finish_mlo(vif, arvif->link_id); + return; + } + + arvif->bcca_zero_sent = false; + + if (link_conf->color_change_active && !link_conf->ema_ap) + ieee80211_beacon_update_cntdwn_mlo(vif, arvif->link_id); + ieee80211_queue_work(ar->ah->hw, &arvif->update_bcn_template_work); +} + +static void ath12k_control_beaconing(struct ath12k_link_vif *arvif, struct ieee80211_bss_conf *info) { struct ath12k *ar = arvif->ar; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k_vif *tx_ahvif = NULL; + struct ath12k_link_vif *tx_arvif = NULL; + struct ieee80211_bss_conf *link; int ret; + struct vdev_up_params params = { 0 }; + rcu_read_lock(); + link = ath12k_get_link_bss_conf(arvif); + if (!link) { + rcu_read_unlock(); + return; + } + + if (link->mbssid_tx_vif) { + tx_ahvif = (void *)link->mbssid_tx_vif->drv_priv; + if (tx_ahvif) { + lockdep_assert_held(&tx_ahvif->ah->conf_mutex); + tx_arvif = tx_ahvif->link[link->mbssid_tx_vif_linkid]; + if (tx_arvif) + lockdep_assert_held(&tx_arvif->ar->conf_mutex); + } + } + + rcu_read_unlock(); lockdep_assert_held(&arvif->ar->conf_mutex); if (!info->enable_beacon) { @@ -1150,6 +2114,7 @@ arvif->vdev_id, ret); arvif->is_up = false; + return; } @@ -1161,12 +2126,19 @@ return; } - arvif->aid = 0; + ahvif->aid = 0; - ether_addr_copy(arvif->bssid, info->bssid); + ether_addr_copy(arvif->bssid, info->addr); - ret = ath12k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid, - arvif->bssid); + params.vdev_id = arvif->vdev_id; + params.aid = ahvif->aid; + params.bssid = arvif->bssid; + if (tx_arvif) { + params.tx_bssid = tx_arvif->bssid; + params.profile_idx = info->bssid_index; + params.profile_count = BIT(info->bssid_indicator); + } + ret = ath12k_wmi_vdev_up(arvif->ar, ¶ms); if (ret) { ath12k_warn(ar->ab, "failed to bring up vdev %d: %i\n", arvif->vdev_id, ret); @@ -1179,12 +2151,16 @@ } static void ath12k_peer_assoc_h_basic(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ieee80211_vif *vif = arvif->ahvif->vif; u32 aid; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); lockdep_assert_held(&ar->conf_mutex); @@ -1193,44 +2169,58 @@ else aid = sta->aid; - ether_addr_copy(arg->peer_mac, sta->addr); + ether_addr_copy(arg->peer_mac, arsta->addr); arg->vdev_id = arvif->vdev_id; arg->peer_associd = aid; arg->auth_flag = true; /* TODO: STA WAR in ath10k for listen interval required? */ - arg->peer_listen_intval = ar->hw->conf.listen_interval; + arg->peer_listen_intval = ar->ah->hw->conf.listen_interval; arg->peer_nss = 1; arg->peer_caps = vif->bss_conf.assoc_capability; } static void ath12k_peer_assoc_h_crypto(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - struct ieee80211_bss_conf *info = &vif->bss_conf; + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_bss_conf *info; struct cfg80211_chan_def def; struct cfg80211_bss *bss; - struct ath12k_vif *arvif = (struct ath12k_vif *)vif->drv_priv; const u8 *rsnie = NULL; const u8 *wpaie = NULL; + struct ieee80211_hw *hw; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); lockdep_assert_held(&ar->conf_mutex); - if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + info = ath12k_get_link_bss_conf(arvif); + + if (!info) { + ath12k_warn(ar->ab, "unable to access bss link conf for peer assoc send\n"); + return; + } + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) return; - bss = cfg80211_get_bss(ar->hw->wiphy, def.chan, info->bssid, NULL, 0, + hw = ar->ah->hw; + bss = cfg80211_get_bss(hw->wiphy, def.chan, info->bssid, NULL, 0, IEEE80211_BSS_TYPE_ANY, IEEE80211_PRIVACY_ANY); - if (arvif->rsnie_present || arvif->wpaie_present) { + if (ahvif->rsnie_present || ahvif->wpaie_present) { arg->need_ptk_4_way = true; - if (arvif->wpaie_present) + if (ahvif->wpaie_present) arg->need_gtk_2_way = true; } else if (bss) { const struct cfg80211_bss_ies *ies; - rcu_read_lock(); rsnie = ieee80211_bss_get_ie(bss, WLAN_EID_RSN); ies = rcu_dereference(bss->ies); @@ -1239,12 +2229,11 @@ WLAN_OUI_TYPE_MICROSOFT_WPA, ies->data, ies->len); - rcu_read_unlock(); - cfg80211_put_bss(ar->hw->wiphy, bss); + cfg80211_put_bss(hw->wiphy, bss); } /* FIXME: base on RSN IE/WPA IE is a correct idea? */ - if (rsnie || wpaie) { + if (ar->supports_6ghz || rsnie || wpaie) { ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "%s: rsn ie found\n", __func__); arg->need_ptk_4_way = true; @@ -1264,12 +2253,100 @@ /* TODO: safe_mode_enabled (bypass 4-way handshake) flag req? */ } +static enum ieee80211_sta_rx_bandwidth +ath12k_get_radio_max_bw_caps(struct ath12k *ar, + enum nl80211_band band, + enum ieee80211_sta_rx_bandwidth sta_bw, + enum nl80211_iftype iftype) +{ + struct ieee80211_supported_band *sband; + struct ieee80211_sband_iftype_data *iftype_data; + const struct ieee80211_sta_eht_cap *eht_cap; + const struct ieee80211_sta_he_cap *he_cap; + int i, idx = 0; + + sband = &ar->mac.sbands[band]; + iftype_data = ar->mac.iftype[band]; + + if (!sband || !iftype_data) { + WARN_ONCE(1, "Invalid band specified :%d\n", band); + return sta_bw; + } + + for (i = 0; i < NUM_NL80211_IFTYPES && i != iftype; i++) { + switch(i) { + case NL80211_IFTYPE_STATION: + case NL80211_IFTYPE_AP: + case NL80211_IFTYPE_MESH_POINT: + idx++; + break; + default: + break; + } + } + + eht_cap = &iftype_data[idx].eht_cap; + he_cap = &iftype_data[idx].he_cap; + + if (!eht_cap || !he_cap) + return sta_bw; + + /* EHT Caps */ + if (band != NL80211_BAND_2GHZ && eht_cap->has_eht && + (eht_cap->eht_cap_elem.phy_cap_info[0] & + IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ)) + return IEEE80211_STA_RX_BW_320; + + /* HE Caps */ + switch (band) { + case NL80211_BAND_5GHZ: + case NL80211_BAND_6GHZ: + if (he_cap->has_he) { + if (he_cap->he_cap_elem.phy_cap_info[0] & + (IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)) { + return IEEE80211_STA_RX_BW_160; + } else if (he_cap->he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G) { + return IEEE80211_STA_RX_BW_80; + } + } + break; + case NL80211_BAND_2GHZ: + if (he_cap->has_he && + (he_cap->he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G)) + return IEEE80211_STA_RX_BW_40; + break; + default: + break; + } + + if (sband->vht_cap.vht_supported) { + switch (sband->vht_cap.cap & + IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) { + case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ: + case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ: + return IEEE80211_STA_RX_BW_160; + default: + return sta_bw; + } + } + + /* Keep Last */ + if (sband->ht_cap.ht_supported && + (sband->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) + return IEEE80211_STA_RX_BW_40; + + return sta_bw; +} + static void ath12k_peer_assoc_h_rates(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ieee80211_vif *vif = arvif->ahvif->vif; struct wmi_rate_set_arg *rateset = &arg->peer_legacy_rates; struct cfg80211_chan_def def; const struct ieee80211_supported_band *sband; @@ -1278,15 +2355,28 @@ u32 ratemask; u8 rate; int i; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); lockdep_assert_held(&ar->conf_mutex); - if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) + return; + + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc rate set\n"); return; + } band = def.chan->band; - sband = ar->hw->wiphy->bands[band]; - ratemask = sta->deflink.supp_rates[band]; + sband = ar->ah->hw->wiphy->bands[band]; + ratemask = link_sta->supp_rates[band]; ratemask &= arvif->bitrate_mask.control[band].legacy; rates = sband->bitrates; @@ -1303,7 +2393,7 @@ } static bool -ath12k_peer_assoc_h_ht_masked(const u8 ht_mcs_mask[IEEE80211_HT_MCS_MASK_LEN]) +ath12k_peer_assoc_h_ht_masked(const u8 *ht_mcs_mask) { int nss; @@ -1315,7 +2405,7 @@ } static bool -ath12k_peer_assoc_h_vht_masked(const u16 vht_mcs_mask[NL80211_VHT_NSS_MAX]) +ath12k_peer_assoc_h_vht_masked(const u16 *vht_mcs_mask) { int nss; @@ -1327,22 +2417,37 @@ } static void ath12k_peer_assoc_h_ht(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - const struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + const struct ieee80211_sta_ht_cap *ht_cap; + struct ieee80211_vif *vif = arvif->ahvif->vif; struct cfg80211_chan_def def; enum nl80211_band band; const u8 *ht_mcs_mask; int i, n; u8 max_nss; u32 stbc; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc ht set\n"); + return; + } + + ht_cap = &link_sta->ht_cap; lockdep_assert_held(&ar->conf_mutex); - if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) return; if (!ht_cap->ht_supported) @@ -1368,11 +2473,19 @@ if (ht_cap->cap & IEEE80211_HT_CAP_LDPC_CODING) arg->ldpc_flag = true; - if (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) { + if (link_sta->bandwidth >= IEEE80211_STA_RX_BW_40) { arg->bw_40 = true; arg->peer_rate_caps |= WMI_HOST_RC_CW40_FLAG; } + /* As firmware handles this two flags (IEEE80211_HT_CAP_SGI_20 + * and IEEE80211_HT_CAP_SGI_40) for enabling SGI, we reset + * both flags if guard interval is Default GI + */ + if (arvif->bitrate_mask.control[band].gi == NL80211_TXRATE_DEFAULT_GI) + arg->peer_ht_caps &= ~(IEEE80211_HT_CAP_SGI_20 | + IEEE80211_HT_CAP_SGI_40); + if (arvif->bitrate_mask.control[band].gi != NL80211_TXRATE_FORCE_LGI) { if (ht_cap->cap & (IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40)) @@ -1418,7 +2531,7 @@ arg->peer_ht_rates.rates[i] = i; } else { arg->peer_ht_rates.num_rates = n; - arg->peer_nss = min(sta->deflink.rx_nss, max_nss); + arg->peer_nss = min(link_sta->rx_nss, max_nss); } ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac ht peer %pM mcs cnt %d nss %d\n", @@ -1487,23 +2600,66 @@ return tx_mcs_set; } +static u8 ath12k_get_nss_160mhz(struct ath12k *ar, + u8 max_nss) +{ + u8 nss_ratio_info = ar->pdev->cap.nss_ratio_info; + u8 max_sup_nss = 0; + + switch (nss_ratio_info) { + case WMI_NSS_RATIO_1BY2_NSS: + max_sup_nss = max_nss >> 1; + break; + case WMI_NSS_RATIO_3BY4_NSS: + ath12k_warn(ar->ab, "WMI_NSS_RATIO_3BY4_NSS not supported\n"); + break; + case WMI_NSS_RATIO_1_NSS: + max_sup_nss = max_nss; + break; + case WMI_NSS_RATIO_2_NSS: + ath12k_warn(ar->ab, "WMI_NSS_RATIO_2_NSS not supported\n"); + break; + default: + ath12k_warn(ar->ab, "invalid nss ratio received from fw\n"); + break; + } + + return max_sup_nss; +} + static void ath12k_peer_assoc_h_vht(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - const struct ieee80211_sta_vht_cap *vht_cap = &sta->deflink.vht_cap; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + const struct ieee80211_sta_vht_cap *vht_cap; + struct ieee80211_vif *vif = arvif->ahvif->vif; struct cfg80211_chan_def def; enum nl80211_band band; - const u16 *vht_mcs_mask; + u16 *vht_mcs_mask; u16 tx_mcs_map; u8 ampdu_factor; u8 max_nss, vht_mcs; - int i; + int i, vht_nss, nss_idx; + bool user_rate_valid = true; + u32 rx_nss, tx_nss, nss_160; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); - if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc vht set\n"); return; + } + vht_cap = &link_sta->vht_cap; + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) { + return; + } if (!vht_cap->vht_supported) return; @@ -1537,12 +2693,31 @@ (1U << (IEEE80211_HT_MAX_AMPDU_FACTOR + ampdu_factor)) - 1); - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_80) arg->bw_80 = true; - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_160) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_160) arg->bw_160 = true; + vht_nss = ath12k_mac_max_vht_nss(vht_mcs_mask); + + if (vht_nss > link_sta->rx_nss) { + user_rate_valid = false; + for (nss_idx = link_sta->rx_nss - 1; nss_idx >= 0; nss_idx--) { + if (vht_mcs_mask[nss_idx]) { + user_rate_valid = true; + break; + } + } + } + + if (!user_rate_valid) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Setting vht range MCS value to peer supported nss:%d for peer %pM\n", + link_sta->rx_nss, arsta->addr); + vht_mcs_mask[link_sta->rx_nss - 1] = vht_mcs_mask[vht_nss - 1]; + } + /* Calculate peer NSS capability from VHT capabilities if STA * supports VHT. */ @@ -1554,7 +2729,7 @@ vht_mcs_mask[i]) max_nss = i + 1; } - arg->peer_nss = min(sta->deflink.rx_nss, max_nss); + arg->peer_nss = min(link_sta->rx_nss, max_nss); arg->rx_max_rate = __le16_to_cpu(vht_cap->vht_mcs.rx_highest); arg->rx_mcs_set = __le16_to_cpu(vht_cap->vht_mcs.rx_mcs_map); arg->tx_max_rate = __le16_to_cpu(vht_cap->vht_mcs.tx_highest); @@ -1576,27 +2751,91 @@ /* TODO: Check */ arg->tx_max_mcs_nss = 0xFF; - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac vht peer %pM max_mpdu %d flags 0x%x\n", - sta->addr, arg->peer_max_mpdu, arg->peer_flags); + if (arg->peer_phymode == MODE_11AC_VHT160 || + arg->peer_phymode == MODE_11AC_VHT80_80) { + tx_nss = ath12k_get_nss_160mhz(ar, max_nss); + rx_nss = min(arg->peer_nss, tx_nss); + arg->peer_bw_rxnss_override = ATH12K_BW_NSS_MAP_ENABLE; + + if (!rx_nss) { + ath12k_warn(ar->ab, "invalid max_nss\n"); + return; + } + + if (arg->peer_phymode == MODE_11AC_VHT160) + nss_160 = FIELD_PREP(ATH12K_PEER_RX_NSS_160MHZ, rx_nss - 1); + else + nss_160 = FIELD_PREP(ATH12K_PEER_RX_NSS_80_80MHZ, rx_nss - 1); - /* TODO: rxnss_override */ + arg->peer_bw_rxnss_override |= nss_160; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac vht peer %pM max_mpdu %d flags 0x%x nss_override 0x%x\n", + arsta->addr, arg->peer_max_mpdu, arg->peer_flags, + arg->peer_bw_rxnss_override); } static void ath12k_peer_assoc_h_he(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - const struct ieee80211_sta_he_cap *he_cap = &sta->deflink.he_cap; + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct cfg80211_chan_def def; + const struct ieee80211_sta_he_cap *he_cap; int i; u8 ampdu_factor, rx_mcs_80, rx_mcs_160, max_nss; u16 mcs_160_map, mcs_80_map; bool support_160; - u16 v; + enum nl80211_band band; + u16 *he_mcs_mask; + u8 he_mcs; + u16 he_tx_mcs = 0, v = 0; + int he_nss, nss_idx; + bool user_rate_valid = true; + u32 rx_nss, tx_nss, nss_160; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_bss_conf* link_conf; + struct ieee80211_link_sta *link_sta; + u32 peer_he_ops; + enum ieee80211_sta_rx_bandwidth radio_max_bw_caps; + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + ath12k_warn(ar->ab, "unable to access bss link conf in peer assoc\n"); + return; + } + + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc he set\n"); + return; + } + + peer_he_ops = link_conf->he_oper.params; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + he_cap = &link_sta->he_cap; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) + return; if (!he_cap->has_he) return; + band = def.chan->band; + he_mcs_mask = arvif->bitrate_mask.control[band].he_mcs; + radio_max_bw_caps = ath12k_get_radio_max_bw_caps(ar, band, link_sta->bandwidth, + vif->type); + + if (ath12k_peer_assoc_h_he_masked(he_mcs_mask)) + return; + arg->he_flag = true; support_160 = !!(he_cap->he_cap_elem.phy_cap_info[0] & @@ -1631,13 +2870,15 @@ else max_nss = rx_mcs_80; - arg->peer_nss = min(sta->deflink.rx_nss, max_nss); + arg->peer_nss = min(link_sta->rx_nss, max_nss); memcpy(&arg->peer_he_cap_macinfo, he_cap->he_cap_elem.mac_cap_info, sizeof(arg->peer_he_cap_macinfo)); memcpy(&arg->peer_he_cap_phyinfo, he_cap->he_cap_elem.phy_cap_info, sizeof(arg->peer_he_cap_phyinfo)); - arg->peer_he_ops = vif->bss_conf.he_oper.params; + + arg->peer_he_ops = peer_he_ops; + /* the top most byte is used to indicate BSS color info */ arg->peer_he_ops &= 0xffffff; @@ -1659,10 +2900,10 @@ IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK; if (ampdu_factor) { - if (sta->deflink.vht_cap.vht_supported) + if (link_sta->vht_cap.vht_supported) arg->peer_max_mpdu = (1 << (IEEE80211_HE_VHT_MAX_AMPDU_FACTOR + ampdu_factor)) - 1; - else if (sta->deflink.ht_cap.ht_supported) + else if (link_sta->ht_cap.ht_supported) arg->peer_max_mpdu = (1 << (IEEE80211_HE_HT_MAX_AMPDU_FACTOR + ampdu_factor)) - 1; } @@ -1703,25 +2944,49 @@ if (he_cap->he_cap_elem.mac_cap_info[0] & IEEE80211_HE_MAC_CAP0_TWT_REQ) arg->twt_requester = true; - switch (sta->deflink.bandwidth) { + he_nss = ath12k_mac_max_he_nss(he_mcs_mask); + + if (he_nss > link_sta->rx_nss) { + user_rate_valid = false; + for (nss_idx = link_sta->rx_nss - 1; nss_idx >= 0; nss_idx--) { + if (he_mcs_mask[nss_idx]) { + user_rate_valid = true; + break; + } + } + } + + if (!user_rate_valid) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Setting he range MCS value to peer supported nss:%d for peer %pM\n", + link_sta->rx_nss, arsta->addr); + he_mcs_mask[link_sta->rx_nss - 1] = he_mcs_mask[he_nss - 1]; + } + + switch (min(link_sta->sta_max_bandwidth, radio_max_bw_caps)) { case IEEE80211_STA_RX_BW_160: if (he_cap->he_cap_elem.phy_cap_info[0] & IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) { v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_80p80); + v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask); arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v; v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80p80); arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80_80] = v; arg->peer_he_mcs_count++; + he_tx_mcs = v; } v = le16_to_cpu(he_cap->he_mcs_nss_supp.rx_mcs_160); arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v; v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_160); + v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask); arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_160] = v; arg->peer_he_mcs_count++; + if (!he_tx_mcs) + he_tx_mcs = v; fallthrough; default: @@ -1729,24 +2994,463 @@ arg->peer_he_rx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v; v = le16_to_cpu(he_cap->he_mcs_nss_supp.tx_mcs_80); + v = ath12k_peer_assoc_h_he_limit(v, he_mcs_mask); arg->peer_he_tx_mcs_set[WMI_HECAP_TXRX_MCS_NSS_IDX_80] = v; arg->peer_he_mcs_count++; + if (!he_tx_mcs) + he_tx_mcs = v; + break; + } + + /* Calculate peer NSS capability from HE capabilities if STA + * supports HE. + */ + for (i = 0, max_nss = 0, he_mcs = 0; i < NL80211_HE_NSS_MAX; i++) { + he_mcs = he_tx_mcs >> (2 * i) & 3; + + /* In case of fixed rates, MCS Range in he_tx_mcs might have + * unsupported range, with he_mcs_mask set, so check either of them + * to find nss. + */ + if (he_mcs != IEEE80211_HE_MCS_NOT_SUPPORTED || + he_mcs_mask[i]) + max_nss = i + 1; + } + arg->peer_nss = min(link_sta->rx_nss, max_nss); + + if (arg->peer_phymode == MODE_11AX_HE160 || + arg->peer_phymode == MODE_11AX_HE80_80) { + tx_nss = ath12k_get_nss_160mhz(ar, ar->num_tx_chains); + rx_nss = min(arg->peer_nss, tx_nss); + + arg->peer_nss = min(link_sta->rx_nss, ar->num_rx_chains); + arg->peer_bw_rxnss_override = ATH12K_BW_NSS_MAP_ENABLE; + + if (!rx_nss) { + ath12k_warn(ar->ab, "invalid max_nss\n"); + return; + } + + if (arg->peer_phymode == MODE_11AX_HE160) + nss_160 = FIELD_PREP(ATH12K_PEER_RX_NSS_160MHZ, rx_nss - 1); + else + nss_160 = FIELD_PREP(ATH12K_PEER_RX_NSS_80_80MHZ, rx_nss - 1); + + arg->peer_bw_rxnss_override |= nss_160; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac he peer %pM nss %d mcs cnt %d nss_override 0x%x\n", + arsta->addr, arg->peer_nss, + arg->peer_he_mcs_count, + arg->peer_bw_rxnss_override); +} + +static void ath12k_peer_assoc_h_he_6ghz(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, + struct ath12k_wmi_peer_assoc_arg *arg) +{ + struct ieee80211_vif *vif = arvif->ahvif->vif; + const struct ieee80211_sta_he_cap *he_cap; + struct cfg80211_chan_def def; + enum nl80211_band band; + u8 ampdu_factor; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc he-6ghz set\n"); + return; + } + he_cap = &link_sta->he_cap; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) + return; + + band = def.chan->band; + + if (!arg->he_flag || band != NL80211_BAND_6GHZ || !link_sta->he_6ghz_capa.capa) + return; + + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) + arg->bw_40 = true; + + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_80) + arg->bw_80 = true; + + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_160) + arg->bw_160 = true; + + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_320) + arg->bw_320 = true; + + arg->peer_he_caps_6ghz = le16_to_cpu(link_sta->he_6ghz_capa.capa); + arg->peer_mpdu_density = + ath12k_parse_mpdudensity(FIELD_GET(IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START, + arg->peer_he_caps_6ghz)); + + /* From IEEE Std 802.11ax-2021 - Section 10.12.2: An HE STA shall be capable of + * receiving A-MPDU where the A-MPDU pre-EOF padding length is up to the value + * indicated by the Maximum A-MPDU Length Exponent Extension field in the HE + * Capabilities element and the Maximum A-MPDU Length Exponent field in HE 6 GHz + * Band Capabilities element in the 6 GHz band. + * + * Here, we are extracting the Max A-MPDU Exponent Extension from HE caps and + * factor is the Maximum A-MPDU Length Exponent from HE 6 GHZ Band capability. + */ + ampdu_factor = FIELD_GET(IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_MASK, + he_cap->he_cap_elem.mac_cap_info[3]) + + FIELD_GET(IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP, + arg->peer_he_caps_6ghz); + + arg->peer_max_mpdu = (1u << (IEEE80211_HE_6GHZ_MAX_AMPDU_FACTOR + + ampdu_factor)) - 1; +} + +static void +ath12k_mac_set_eht_mcs_nss_bitmap_20mhz_only( + const struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcsnss, + u32 *rx_mcs, u32 *tx_mcs, + const u16 eht_mcs_limit[NL80211_EHT_NSS_MAX]) +{ + int nss; + u8 mcs_7 = 0, mcs_9 = 0, mcs_11 = 0, mcs_13 = 0; + u8 peer_mcs_7 = 0, peer_mcs_9 = 0, peer_mcs_11 = 0, peer_mcs_13 = 0; + + for (nss = 0; nss < NL80211_EHT_NSS_MAX; nss++) { + if (eht_mcs_limit[nss] & 0x00FF) + mcs_7++; + if (eht_mcs_limit[nss] & 0x0300) + mcs_9++; + if (eht_mcs_limit[nss] & 0x0C00) + mcs_11++; + if (eht_mcs_limit[nss] & 0x3000) + mcs_13++; + } + + peer_mcs_7 = u8_get_bits(mcsnss->rx_tx_mcs7_max_nss, IEEE80211_EHT_MCS_NSS_RX); + peer_mcs_9 = u8_get_bits(mcsnss->rx_tx_mcs9_max_nss, IEEE80211_EHT_MCS_NSS_RX); + peer_mcs_11 = u8_get_bits(mcsnss->rx_tx_mcs11_max_nss, IEEE80211_EHT_MCS_NSS_RX); + peer_mcs_13 = u8_get_bits(mcsnss->rx_tx_mcs13_max_nss, IEEE80211_EHT_MCS_NSS_RX); + + *rx_mcs = FIELD_PREP(WMI_MCS_NSS_MAP_0_7, min(peer_mcs_7, mcs_7)) | + FIELD_PREP(WMI_MCS_NSS_MAP_8_9, min(peer_mcs_9, mcs_9)) | + FIELD_PREP(WMI_MCS_NSS_MAP_10_11, min(peer_mcs_11, mcs_11)) | + FIELD_PREP(WMI_MCS_NSS_MAP_12_13, min (peer_mcs_13, mcs_13)); + + peer_mcs_7 = u8_get_bits(mcsnss->rx_tx_mcs7_max_nss, IEEE80211_EHT_MCS_NSS_TX); + peer_mcs_9 = u8_get_bits(mcsnss->rx_tx_mcs9_max_nss, IEEE80211_EHT_MCS_NSS_TX); + peer_mcs_11 = u8_get_bits(mcsnss->rx_tx_mcs11_max_nss, IEEE80211_EHT_MCS_NSS_TX); + peer_mcs_13 = u8_get_bits(mcsnss->rx_tx_mcs13_max_nss, IEEE80211_EHT_MCS_NSS_TX); + + *tx_mcs = FIELD_PREP(WMI_MCS_NSS_MAP_0_7, min(peer_mcs_7, mcs_7)) | + FIELD_PREP(WMI_MCS_NSS_MAP_8_9, min(peer_mcs_9, mcs_9)) | + FIELD_PREP(WMI_MCS_NSS_MAP_10_11, min(peer_mcs_11, mcs_11)) | + FIELD_PREP(WMI_MCS_NSS_MAP_12_13, min (peer_mcs_13, mcs_13)); +} + +static void +ath12k_mac_set_eht_mcs_nss_bitmap(const struct ieee80211_eht_mcs_nss_supp_bw *mcsnss, + u32 *rx_mcs, u32 *tx_mcs, + const u16 eht_mcs_limit[NL80211_EHT_NSS_MAX]) +{ + int nss; + u8 mcs_7 = 0, mcs_9 = 0, mcs_11 = 0, mcs_13 = 0; + u8 peer_mcs_7 = 0, peer_mcs_9 = 0, peer_mcs_11 = 0, peer_mcs_13 = 0; + + for (nss = 0; nss < NL80211_EHT_NSS_MAX; nss++) { + if (eht_mcs_limit[nss] & 0x00FF) + mcs_7++; + if (eht_mcs_limit[nss] & 0x0300) + mcs_9++; + if (eht_mcs_limit[nss] & 0x0C00) + mcs_11++; + if (eht_mcs_limit[nss] & 0x3000) + mcs_13++; + } + + peer_mcs_7 = u8_get_bits(mcsnss->rx_tx_mcs9_max_nss, IEEE80211_EHT_MCS_NSS_RX); + peer_mcs_9 = u8_get_bits(mcsnss->rx_tx_mcs9_max_nss, IEEE80211_EHT_MCS_NSS_RX); + peer_mcs_11 = u8_get_bits(mcsnss->rx_tx_mcs11_max_nss, IEEE80211_EHT_MCS_NSS_RX); + peer_mcs_13 = u8_get_bits(mcsnss->rx_tx_mcs13_max_nss, IEEE80211_EHT_MCS_NSS_RX); + + *rx_mcs = FIELD_PREP(WMI_MCS_NSS_MAP_0_7, min(peer_mcs_7, mcs_7)) | + FIELD_PREP(WMI_MCS_NSS_MAP_8_9, min(peer_mcs_9, mcs_9)) | + FIELD_PREP(WMI_MCS_NSS_MAP_10_11, min(peer_mcs_11, mcs_11)) | + FIELD_PREP(WMI_MCS_NSS_MAP_12_13, min (peer_mcs_13, mcs_13)); + + peer_mcs_7 = u8_get_bits(mcsnss->rx_tx_mcs9_max_nss, IEEE80211_EHT_MCS_NSS_TX); + peer_mcs_9 = u8_get_bits(mcsnss->rx_tx_mcs9_max_nss, IEEE80211_EHT_MCS_NSS_TX); + peer_mcs_11 = u8_get_bits(mcsnss->rx_tx_mcs11_max_nss, IEEE80211_EHT_MCS_NSS_TX); + peer_mcs_13 = u8_get_bits(mcsnss->rx_tx_mcs13_max_nss, IEEE80211_EHT_MCS_NSS_TX); + + *tx_mcs = FIELD_PREP(WMI_MCS_NSS_MAP_0_7, min(peer_mcs_7, mcs_7)) | + FIELD_PREP(WMI_MCS_NSS_MAP_8_9, min(peer_mcs_9, mcs_9)) | + FIELD_PREP(WMI_MCS_NSS_MAP_10_11, min(peer_mcs_11, mcs_11)) | + FIELD_PREP(WMI_MCS_NSS_MAP_12_13, min (peer_mcs_13, mcs_13)); +} + +static void ath12k_mac_set_eht_ppe_threshold(const u8 *ppe_thres, + struct ath12k_ppe_threshold *ppet) +{ + u32 bit_pos = IEEE80211_EHT_PPE_THRES_INFO_HEADER_SIZE; + u8 nss; + + ppet->numss_m1 = ppe_thres[0] & IEEE80211_EHT_PPE_THRES_NSS_MASK; + ppet->ru_bit_mask = FIELD_GET(IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_MASK, + __cpu_to_le16(ppe_thres[0])); + + for (nss = 0; nss <= ppet->numss_m1; nss++) { + u8 ru; + + for (ru = 0; + ru < hweight8(IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_MASK); + ru++) { + u32 val = 0; + u8 i; + + if ((ppet->ru_bit_mask & BIT(ru)) == 0) + continue; + + for (i = 0; i < IEEE80211_EHT_PPE_THRES_INFO_PPET_SIZE; + i++) { + val >>= 1; + val |= ((ppe_thres[bit_pos / 8] >> + (bit_pos % 8)) & 0x1) << 5; + bit_pos++; + } + ppet->ppet16_ppet8_ru3_ru0[nss] |= + (val << + (ru * IEEE80211_EHT_PPE_THRES_INFO_PPET_SIZE)); + } + } +} + +static bool +ath12k_peer_assoc_h_eht_masked(const u16 eht_mcs_mask[NL80211_EHT_NSS_MAX]) +{ + int nss; + + for (nss = 0; nss < NL80211_EHT_NSS_MAX; nss++) + if (eht_mcs_mask[nss]) + return false; + + return true; +} + +static void ath12k_peer_assoc_h_eht(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, + struct ath12k_wmi_peer_assoc_arg *arg) +{ + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct cfg80211_chan_def def; + const struct ieee80211_sta_eht_cap *eht_cap; + const struct ieee80211_eht_mcs_nss_supp *mcs_nss; + const struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss_supp_bw; + u8 mcs_idx = WMI_EHTCAP_TXRX_MCS_NSS_IDX_80; + enum nl80211_band band; + u16 *eht_mcs_mask; + u8 max_nss; + int eht_nss, nss_idx; + bool user_rate_valid = true; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_bss_conf* link_conf; + struct ieee80211_link_sta *link_sta; + const struct ieee80211_sta_eht_cap *own_eht_cap; + const struct ieee80211_eht_mcs_nss_supp *own_eht_mcs_nss_supp; + enum ieee80211_sta_rx_bandwidth radio_max_bw_caps; + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + ath12k_warn(ar->ab, "unable to access bss link conf in peer assoc\n"); + return; + } + + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc eht set\n"); + return; + } + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + eht_cap = &link_sta->eht_cap; + mcs_nss = &eht_cap->eht_mcs_nss_supp; + mcs_nss_supp_bw = &mcs_nss->bw._80; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) + return; + + band = def.chan->band; + eht_mcs_mask = arvif->bitrate_mask.control[band].eht_mcs; + + radio_max_bw_caps = ath12k_get_radio_max_bw_caps(ar, band, link_sta->bandwidth, + vif->type); + + own_eht_cap = &ar->mac.sbands[band].iftype_data->eht_cap; + own_eht_mcs_nss_supp = &own_eht_cap->eht_mcs_nss_supp; + + if (ath12k_peer_assoc_h_eht_masked((const u16*) eht_mcs_mask)) + return; + + if (!link_sta->he_cap.has_he || !eht_cap->has_eht) + return; + + arg->eht_flag = true; + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_320) { + arg->bw_40 = true; + arg->bw_80 = true; + arg->bw_160 = true; + arg->bw_320 = true; + } + if (eht_cap->eht_cap_elem.phy_cap_info[5] & + IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT && + eht_cap->eht_ppe_thres[0] != 0) + ath12k_mac_set_eht_ppe_threshold(eht_cap->eht_ppe_thres, + &arg->peer_eht_ppet); + memcpy(arg->peer_eht_cap_mac, eht_cap->eht_cap_elem.mac_cap_info, + sizeof(eht_cap->eht_cap_elem.mac_cap_info)); + memcpy(arg->peer_eht_cap_phy, eht_cap->eht_cap_elem.phy_cap_info, + sizeof(eht_cap->eht_cap_elem.phy_cap_info)); + arg->peer_eht_ops = 0; + + eht_nss = ath12k_mac_max_eht_mcs_nss((void *)own_eht_mcs_nss_supp, + sizeof(*own_eht_mcs_nss_supp)); + + if (eht_nss > link_sta->rx_nss) { + user_rate_valid = false; + for (nss_idx = (link_sta->rx_nss - 1); nss_idx >= 0; nss_idx--) { + if (eht_mcs_mask[nss_idx]) { + user_rate_valid = true; + break; + } + } + } + + if (!user_rate_valid) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Setting eht range MCS value to peer supported nss:%d for peer %pM\n", + link_sta->rx_nss, arsta->addr); + eht_mcs_mask[link_sta->rx_nss - 1] = eht_mcs_mask[eht_nss - 1]; + } + + switch (min(link_sta->sta_max_bandwidth, radio_max_bw_caps)) { + case IEEE80211_STA_RX_BW_320: + mcs_nss_supp_bw = &mcs_nss->bw._320; + mcs_idx = WMI_EHTCAP_TXRX_MCS_NSS_IDX_320; + arg->peer_eht_mcs_count++; + ath12k_mac_set_eht_mcs_nss_bitmap(&mcs_nss->bw._320, + &arg->peer_eht_rx_mcs_set[mcs_idx], + &arg->peer_eht_tx_mcs_set[mcs_idx], + eht_mcs_mask); + fallthrough; + + case IEEE80211_STA_RX_BW_160: + mcs_nss_supp_bw = &mcs_nss->bw._160; + mcs_idx = WMI_EHTCAP_TXRX_MCS_NSS_IDX_160; + arg->peer_eht_mcs_count++; + ath12k_mac_set_eht_mcs_nss_bitmap(&mcs_nss->bw._160, + &arg->peer_eht_rx_mcs_set[mcs_idx], + &arg->peer_eht_tx_mcs_set[mcs_idx], + eht_mcs_mask); + fallthrough; + + default: + if (arg->peer_phymode == MODE_11BE_EHT20) { + mcs_idx = WMI_EHTCAP_TXRX_MCS_NSS_IDX_80; + ath12k_mac_set_eht_mcs_nss_bitmap_20mhz_only(&mcs_nss->only_20mhz, + &arg->peer_eht_rx_mcs_set[mcs_idx], + &arg->peer_eht_tx_mcs_set[mcs_idx], + eht_mcs_mask); + } else { + mcs_idx = WMI_EHTCAP_TXRX_MCS_NSS_IDX_80; + ath12k_mac_set_eht_mcs_nss_bitmap(&mcs_nss->bw._80, + &arg->peer_eht_rx_mcs_set[mcs_idx], + &arg->peer_eht_tx_mcs_set[mcs_idx], + eht_mcs_mask); + } + + arg->peer_eht_mcs_count++; break; } + + if (!(link_sta->he_cap.he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) { + if (mcs_nss->only_20mhz.rx_tx_mcs13_max_nss) + max_nss = mcs_nss->only_20mhz.rx_tx_mcs13_max_nss; + else if (mcs_nss->only_20mhz.rx_tx_mcs11_max_nss) + max_nss = mcs_nss->only_20mhz.rx_tx_mcs11_max_nss; + else if (mcs_nss->only_20mhz.rx_tx_mcs9_max_nss) + max_nss = mcs_nss->only_20mhz.rx_tx_mcs9_max_nss; + else + max_nss = mcs_nss->only_20mhz.rx_tx_mcs7_max_nss; + } else { + if (mcs_nss_supp_bw->rx_tx_mcs13_max_nss) + max_nss = u8_get_bits(mcs_nss_supp_bw->rx_tx_mcs13_max_nss, + IEEE80211_EHT_MCS_NSS_RX); + if (mcs_nss_supp_bw->rx_tx_mcs11_max_nss) + max_nss = max(max_nss, u8_get_bits(mcs_nss_supp_bw->rx_tx_mcs11_max_nss, + IEEE80211_EHT_MCS_NSS_RX)); + if (mcs_nss_supp_bw->rx_tx_mcs9_max_nss) + max_nss = max(max_nss, u8_get_bits(mcs_nss_supp_bw->rx_tx_mcs9_max_nss, + IEEE80211_EHT_MCS_NSS_RX)); + } + + max_nss = min(max_nss, (uint8_t)eht_nss); + + arg->peer_nss = min(link_sta->rx_nss, max_nss); + arg->ru_punct_bitmap = ~def.ru_punct_bitmap; + if (ieee80211_vif_is_mesh(vif) && link_sta->ru_punct_bitmap) + arg->ru_punct_bitmap = ~link_sta->ru_punct_bitmap; + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac eht peer %pM nss %d mcs cnt %d ru_punct_bitmap 0x%x\n", + arsta->addr, arg->peer_nss, arg->peer_eht_mcs_count, arg->ru_punct_bitmap); } -static void ath12k_peer_assoc_h_smps(struct ieee80211_sta *sta, +static void ath12k_peer_assoc_h_smps(struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - const struct ieee80211_sta_ht_cap *ht_cap = &sta->deflink.ht_cap; + const struct ieee80211_sta_ht_cap *ht_cap; int smps; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + struct ath12k *ar = arsta->arvif->ar; - if (!ht_cap->ht_supported) + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc smps set\n"); return; + } + + ht_cap = &link_sta->ht_cap; + if (!ht_cap->ht_supported && !link_sta->he_6ghz_capa.capa) + return; + + if (ht_cap->ht_supported) { smps = ht_cap->cap & IEEE80211_HT_CAP_SM_PS; smps >>= IEEE80211_HT_CAP_SM_PS_SHIFT; + } else { + smps = FIELD_GET(IEEE80211_HE_6GHZ_CAP_SM_PS, + le16_to_cpu(link_sta->he_6ghz_capa.capa)); + } switch (smps) { case WLAN_HT_CAP_SM_PS_STATIC: @@ -1764,13 +3468,17 @@ } static void ath12k_peer_assoc_h_qos(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); - switch (arvif->vdev_type) { + switch (ahvif->vdev_type) { case WMI_VDEV_TYPE_AP: if (sta->wme) { /* TODO: Check WME vs QoS */ @@ -1796,17 +3504,78 @@ } ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac peer %pM qos %d\n", - sta->addr, arg->qos_flag); + arsta->addr, arg->qos_flag); +} + +static void ath12k_peer_assoc_h_mlo(struct ath12k_link_sta *arsta, + struct ath12k_wmi_peer_assoc_arg *arg) +{ + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta_p; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + unsigned long links; + struct peer_assoc_mlo_params *ml = &arg->ml; + u8 i = 0, link_id; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + if (!sta->mlo || ahsta->ml_peer_id == ATH12K_MLO_PEER_ID_INVALID) + return; + + ml->enabled = true; + ml->assoc_link = arsta->is_assoc_link; + if (arsta->link_id == ahsta->primary_link_id) + ml->primary_umac = true; + else + ml->primary_umac = false; + ml->peer_id_valid = true; + ml->logical_link_idx_valid = true; + + ether_addr_copy(ml->mld_addr, sta->addr); + ml->logical_link_idx = arsta->link_idx; + ml->ml_peer_id = ahsta->ml_peer_id; + ml->ieee_link_id = arsta->link_id; + ml->num_partner_links = 0; + /*emlsr */ + /* ml->eml_caps = sta->eml_cap; */ + ml->eml_caps = 0; + + links = sta->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + if (i > ATH12K_WMI_MLO_MAX_LINKS) + break; + arsta_p = ahsta->link[link_id]; + arvif = arsta_p->arvif; + + if (arsta_p == arsta) + continue; + ml->partner_info[i].vdev_id = arvif->vdev_id; + ml->partner_info[i].hw_link_id = arvif->ar->pdev->hw_link_id; + ml->partner_info[i].assoc_link = arsta_p->is_assoc_link; + if (arsta_p->link_id == ahsta->primary_link_id) + ml->partner_info[i].primary_umac = true; + else + ml->partner_info[i].primary_umac = false; + ml->partner_info[i].logical_link_idx_valid = true; + ml->partner_info[i].logical_link_idx = arsta_p->link_idx; + ml->num_partner_links++; + i++; + } } static int ath12k_peer_assoc_qos_ap(struct ath12k *ar, - struct ath12k_vif *arvif, - struct ieee80211_sta *sta) + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) { struct ath12k_wmi_ap_ps_arg arg; u32 max_sp; u32 uapsd; int ret; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); lockdep_assert_held(&ar->conf_mutex); @@ -1835,26 +3604,26 @@ arg.param = WMI_AP_PS_PEER_PARAM_UAPSD; arg.value = uapsd; - ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, sta->addr, &arg); + ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, arsta->addr, &arg); if (ret) goto err; arg.param = WMI_AP_PS_PEER_PARAM_MAX_SP; arg.value = max_sp; - ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, sta->addr, &arg); + ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, arsta->addr, &arg); if (ret) goto err; /* TODO: revisit during testing */ arg.param = WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE; arg.value = DISABLE_SIFS_RESPONSE_TRIGGER; - ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, sta->addr, &arg); + ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, arsta->addr, &arg); if (ret) goto err; arg.param = WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD; arg.value = DISABLE_SIFS_RESPONSE_TRIGGER; - ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, sta->addr, &arg); + ret = ath12k_wmi_send_set_ap_ps_param_cmd(ar, arsta->addr, &arg); if (ret) goto err; @@ -1866,17 +3635,29 @@ return ret; } -static bool ath12k_mac_sta_has_ofdm_only(struct ieee80211_sta *sta) +static bool ath12k_mac_sta_has_ofdm_only(struct ath12k_link_sta *arsta) { - return sta->deflink.supp_rates[NL80211_BAND_2GHZ] >> + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + struct ath12k *ar = arsta->arvif->ar; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in ofdm rate check\n"); + return false; + } + return link_sta->supp_rates[NL80211_BAND_2GHZ] >> ATH12K_MAC_FIRST_OFDM_RATE_IDX; } -static enum wmi_phy_mode ath12k_mac_get_phymode_vht(struct ath12k *ar, - struct ieee80211_sta *sta) +static enum wmi_phy_mode ath12k_mac_get_phymode_vht(struct ieee80211_link_sta *link_sta) { - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_160) { - switch (sta->deflink.vht_cap.cap & + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_160) { + switch (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) { case IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ: return MODE_11AC_VHT160; @@ -1888,85 +3669,137 @@ } } - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_80) return MODE_11AC_VHT80; - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) return MODE_11AC_VHT40; - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_20) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20) return MODE_11AC_VHT20; return MODE_UNKNOWN; } -static enum wmi_phy_mode ath12k_mac_get_phymode_he(struct ath12k *ar, - struct ieee80211_sta *sta) +static enum wmi_phy_mode ath12k_mac_get_phymode_he(struct ieee80211_link_sta *link_sta) { - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_160) { - if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[0] & + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_160) { + if (link_sta->he_cap.he_cap_elem.phy_cap_info[0] & IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) return MODE_11AX_HE160; - else if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[0] & + else if (link_sta->he_cap.he_cap_elem.phy_cap_info[0] & IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) return MODE_11AX_HE80_80; /* not sure if this is a valid case? */ return MODE_11AX_HE160; } - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_80) return MODE_11AX_HE80; - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) return MODE_11AX_HE40; - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_20) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20) return MODE_11AX_HE20; return MODE_UNKNOWN; } +static enum wmi_phy_mode ath12k_mac_get_phymode_eht(struct ieee80211_link_sta *link_sta) +{ + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_320) + if (link_sta->eht_cap.eht_cap_elem.phy_cap_info[0] & + IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ) + return MODE_11BE_EHT320; + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_160) { + if (link_sta->he_cap.he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) + return MODE_11BE_EHT160; + else if (link_sta->he_cap.he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) + return MODE_11BE_EHT80_80; + /* not sure if this is a valid case? */ + return MODE_11BE_EHT160; + } + + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_80) + return MODE_11BE_EHT80; + + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) + return MODE_11BE_EHT40; + + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20) + return MODE_11BE_EHT20; + + return MODE_UNKNOWN; +} + static void ath12k_peer_assoc_h_phymode(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg) { - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ieee80211_vif *vif = arvif->ahvif->vif; struct cfg80211_chan_def def; enum nl80211_band band; const u8 *ht_mcs_mask; const u16 *vht_mcs_mask; + const u16 *he_mcs_mask; + const u16 *eht_mcs_mask; enum wmi_phy_mode phymode = MODE_UNKNOWN; + u8 link_id = arvif->link_id; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); - if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) return; + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer assoc phymode set\n"); + return; + } + band = def.chan->band; ht_mcs_mask = arvif->bitrate_mask.control[band].ht_mcs; vht_mcs_mask = arvif->bitrate_mask.control[band].vht_mcs; + he_mcs_mask = arvif->bitrate_mask.control[band].he_mcs; + eht_mcs_mask = arvif->bitrate_mask.control[band].eht_mcs; switch (band) { case NL80211_BAND_2GHZ: - if (sta->deflink.he_cap.has_he) { - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_80) + if (link_sta->eht_cap.has_eht && + !ath12k_peer_assoc_h_eht_masked(eht_mcs_mask)) { + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) + phymode = MODE_11BE_EHT40_2G; + else + phymode = MODE_11BE_EHT20_2G; + } else if (link_sta->he_cap.has_he && + !ath12k_peer_assoc_h_he_masked(he_mcs_mask)) { + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_80) phymode = MODE_11AX_HE80_2G; - else if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40) + else if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) phymode = MODE_11AX_HE40_2G; else phymode = MODE_11AX_HE20_2G; - } else if (sta->deflink.vht_cap.vht_supported && + } else if (link_sta->vht_cap.vht_supported && !ath12k_peer_assoc_h_vht_masked(vht_mcs_mask)) { - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) phymode = MODE_11AC_VHT40; else phymode = MODE_11AC_VHT20; - } else if (sta->deflink.ht_cap.ht_supported && + } else if (link_sta->ht_cap.ht_supported && !ath12k_peer_assoc_h_ht_masked(ht_mcs_mask)) { - if (sta->deflink.bandwidth == IEEE80211_STA_RX_BW_40) + if (link_sta->bandwidth == IEEE80211_STA_RX_BW_40) phymode = MODE_11NG_HT40; else phymode = MODE_11NG_HT20; - } else if (ath12k_mac_sta_has_ofdm_only(sta)) { + } else if (ath12k_mac_sta_has_ofdm_only(arsta)) { phymode = MODE_11G; } else { phymode = MODE_11B; @@ -1974,15 +3807,19 @@ break; case NL80211_BAND_5GHZ: case NL80211_BAND_6GHZ: - /* Check HE first */ - if (sta->deflink.he_cap.has_he) { - phymode = ath12k_mac_get_phymode_he(ar, sta); - } else if (sta->deflink.vht_cap.vht_supported && + /* Check EHT first */ + if (link_sta->eht_cap.has_eht && + !ath12k_peer_assoc_h_eht_masked(eht_mcs_mask)) { + phymode = ath12k_mac_get_phymode_eht(link_sta); + } else if (link_sta->he_cap.has_he && + !ath12k_peer_assoc_h_he_masked(he_mcs_mask)) { + phymode = ath12k_mac_get_phymode_he(link_sta); + } else if (link_sta->vht_cap.vht_supported && !ath12k_peer_assoc_h_vht_masked(vht_mcs_mask)) { - phymode = ath12k_mac_get_phymode_vht(ar, sta); - } else if (sta->deflink.ht_cap.ht_supported && + phymode = ath12k_mac_get_phymode_vht(link_sta); + } else if (link_sta->ht_cap.ht_supported && !ath12k_peer_assoc_h_ht_masked(ht_mcs_mask)) { - if (sta->deflink.bandwidth >= IEEE80211_STA_RX_BW_40) + if (link_sta->bandwidth >= IEEE80211_STA_RX_BW_40) phymode = MODE_11NA_HT40; else phymode = MODE_11NA_HT20; @@ -1995,15 +3832,15 @@ } ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac peer %pM phymode %s\n", - sta->addr, ath12k_mac_phymode_str(phymode)); + arsta->addr, ath12k_wmi_phymode_str(phymode)); arg->peer_phymode = phymode; WARN_ON(phymode == MODE_UNKNOWN); } static void ath12k_peer_assoc_prepare(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ath12k_wmi_peer_assoc_arg *arg, bool reassoc) { @@ -2014,30 +3851,41 @@ reinit_completion(&ar->peer_assoc_done); arg->peer_new_assoc = !reassoc; - ath12k_peer_assoc_h_basic(ar, vif, sta, arg); - ath12k_peer_assoc_h_crypto(ar, vif, sta, arg); - ath12k_peer_assoc_h_rates(ar, vif, sta, arg); - ath12k_peer_assoc_h_ht(ar, vif, sta, arg); - ath12k_peer_assoc_h_vht(ar, vif, sta, arg); - ath12k_peer_assoc_h_he(ar, vif, sta, arg); - ath12k_peer_assoc_h_qos(ar, vif, sta, arg); - ath12k_peer_assoc_h_phymode(ar, vif, sta, arg); - ath12k_peer_assoc_h_smps(sta, arg); + + ath12k_peer_assoc_h_basic(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_crypto(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_rates(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_phymode(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_ht(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_vht(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_he(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_he_6ghz(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_eht(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_qos(ar, arvif, arsta, arg); + ath12k_peer_assoc_h_smps(arsta, arg); + ath12k_peer_assoc_h_mlo(arsta, arg); + + arsta->peer_nss = arg->peer_nss; /* TODO: amsdu_disable req? */ } -static int ath12k_setup_peer_smps(struct ath12k *ar, struct ath12k_vif *arvif, +static int ath12k_setup_peer_smps(struct ath12k *ar, struct ath12k_link_vif *arvif, const u8 *addr, - const struct ieee80211_sta_ht_cap *ht_cap) + const struct ieee80211_sta_ht_cap *ht_cap, + u16 he_6ghz_capa) { int smps; - if (!ht_cap->ht_supported) + if (!ht_cap->ht_supported && !he_6ghz_capa) return 0; + if (ht_cap->ht_supported) { smps = ht_cap->cap & IEEE80211_HT_CAP_SM_PS; smps >>= IEEE80211_HT_CAP_SM_PS_SHIFT; + } else { + smps = FIELD_GET(IEEE80211_HE_6GHZ_CAP_SM_PS, he_6ghz_capa); + } if (smps >= ARRAY_SIZE(ath12k_smps_map)) return -EINVAL; @@ -2047,26 +3895,246 @@ ath12k_smps_map[smps]); } -static void ath12k_bss_assoc(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, +static bool ath12k_mac_set_he_txbf_conf(struct ath12k_link_vif *arvif) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k *ar = arvif->ar; + u32 param = WMI_VDEV_PARAM_SET_HEMU_MODE; + u32 value = 0; + int ret; + struct ieee80211_bss_conf* link_conf; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access bss link conf in txbf conf\n"); + return false; + } + + if (!link_conf->he_support) { + rcu_read_unlock(); + return true; + } + + if (link_conf->he_su_beamformer) { + value |= FIELD_PREP(HE_MODE_SU_TX_BFER, HE_SU_BFER_ENABLE); + if (link_conf->he_mu_beamformer && + ahvif->vdev_type == WMI_VDEV_TYPE_AP) + value |= FIELD_PREP(HE_MODE_MU_TX_BFER, HE_MU_BFER_ENABLE); + } + + if (ahvif->vif->type != NL80211_IFTYPE_MESH_POINT) { + value |= FIELD_PREP(HE_MODE_DL_OFDMA, HE_DL_MUOFDMA_ENABLE) | + FIELD_PREP(HE_MODE_UL_OFDMA, HE_UL_MUOFDMA_ENABLE); + + if (link_conf->he_full_ul_mumimo) + value |= FIELD_PREP(HE_MODE_UL_MUMIMO, HE_UL_MUMIMO_ENABLE); + + if (link_conf->he_su_beamformee) + value |= FIELD_PREP(HE_MODE_SU_TX_BFEE, HE_SU_BFEE_ENABLE); + } + + rcu_read_unlock(); + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, value); + if (ret) { + ath12k_warn(ar->ab, "failed to set vdev %d HE MU mode: %d\n", + arvif->vdev_id, ret); + return false; + } + + param = WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE; + value = + FIELD_PREP(HE_VHT_SOUNDING_MODE, HE_VHT_SOUNDING_MODE_ENABLE) | + FIELD_PREP(HE_TRIG_NONTRIG_SOUNDING_MODE, + HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE); + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, + param, value); + if (ret) { + ath12k_warn(ar->ab, "failed to set vdev %d sounding mode: %d\n", + arvif->vdev_id, ret); + return false; + } + return true; +} + +static bool ath12k_mac_vif_recalc_sta_he_txbf(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ieee80211_sta_he_cap *he_cap) +{ + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ieee80211_he_cap_elem he_cap_elem = {0}; + struct ieee80211_sta_he_cap *cap_band; + struct cfg80211_chan_def def; + u32 param = WMI_VDEV_PARAM_SET_HEMU_MODE; + u32 hemode = 0; + int ret; + u8 link_id = arvif->link_id; + struct ieee80211_bss_conf* link_conf; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access bss link conf in recalc txbf conf\n"); + return false; + } + + if (!link_conf->he_support) { + rcu_read_unlock(); + return true; + } + + rcu_read_unlock(); + + if (vif->type != NL80211_IFTYPE_STATION) + return false; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) + return false; + + if (def.chan->band == NL80211_BAND_2GHZ) + cap_band = &ar->mac.iftype[NL80211_BAND_2GHZ][vif->type].he_cap; + else + cap_band = &ar->mac.iftype[NL80211_BAND_5GHZ][vif->type].he_cap; + + memcpy(&he_cap_elem, &cap_band->he_cap_elem, sizeof(he_cap_elem)); + + if (he_cap_elem.phy_cap_info[HE_PHYCAP_BYTE_4] & + IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE) { + if (he_cap->he_cap_elem.phy_cap_info[HE_PHYCAP_BYTE_3] & + IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) + hemode |= FIELD_PREP(HE_MODE_SU_TX_BFEE, HE_SU_BFEE_ENABLE); + if (he_cap->he_cap_elem.phy_cap_info[HE_PHYCAP_BYTE_4] & + IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER) { + hemode |= FIELD_PREP(HE_MODE_MU_TX_BFEE, HE_MU_BFEE_ENABLE); + } + } + + if (vif->type != NL80211_IFTYPE_MESH_POINT) { + hemode |= FIELD_PREP(HE_MODE_DL_OFDMA, HE_DL_MUOFDMA_ENABLE) | + FIELD_PREP(HE_MODE_UL_OFDMA, HE_UL_MUOFDMA_ENABLE); + + if (he_cap_elem.phy_cap_info[HE_PHYCAP_BYTE_2] & + IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO) + if (he_cap->he_cap_elem.phy_cap_info[HE_PHYCAP_BYTE_2] & + IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO) + hemode |= FIELD_PREP(HE_MODE_UL_MUMIMO, HE_UL_MUMIMO_ENABLE); + + if (FIELD_GET(HE_MODE_MU_TX_BFEE, hemode)) + hemode |= FIELD_PREP(HE_MODE_SU_TX_BFEE, HE_SU_BFEE_ENABLE); + + if (FIELD_GET(HE_MODE_MU_TX_BFER, hemode)) + hemode |= FIELD_PREP(HE_MODE_SU_TX_BFER, HE_SU_BFER_ENABLE); + } + + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, hemode); + if (ret) { + ath12k_warn(ar->ab, "failed to submit vdev param txbf 0x%x: %d\n", + hemode, ret); + return false; + } + + return true; +} + +static bool ath12k_mac_set_eht_txbf_conf(struct ath12k_link_vif *arvif) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k *ar = arvif->ar; + u32 param = WMI_VDEV_PARAM_SET_EHT_MU_MODE; + u32 value = 0; + int ret; + struct ieee80211_bss_conf* link_conf; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access bss link conf in eht txbf conf\n"); + return false; + } + + if (!link_conf->eht_support) { + rcu_read_unlock(); + return true; + } + + if (link_conf->eht_su_beamformer) { + value |= FIELD_PREP(EHT_MODE_SU_TX_BFER, EHT_SU_BFER_ENABLE); + if (link_conf->eht_mu_beamformer && + ahvif->vdev_type == WMI_VDEV_TYPE_AP) + value |= FIELD_PREP(EHT_MODE_MU_TX_BFER, EHT_MU_BFER_ENABLE) | + FIELD_PREP(EHT_MODE_DL_OFDMA_MUMIMO, EHT_DL_MUOFDMA_ENABLE) | + FIELD_PREP(EHT_MODE_UL_OFDMA_MUMIMO, EHT_UL_MUOFDMA_ENABLE); + } + + if (ahvif->vif->type != NL80211_IFTYPE_MESH_POINT) { + value |= FIELD_PREP(EHT_MODE_DL_OFDMA, EHT_DL_MUOFDMA_ENABLE) | + FIELD_PREP(EHT_MODE_UL_OFDMA, EHT_UL_MUOFDMA_ENABLE); + + if (link_conf->eht_80mhz_full_bw_ul_mumimo) + value |= FIELD_PREP(EHT_MODE_MUMIMO, EHT_UL_MUMIMO_ENABLE); + + if (link_conf->eht_su_beamformee) + value |= FIELD_PREP(EHT_MODE_SU_TX_BFEE, EHT_SU_BFEE_ENABLE); + } + + rcu_read_unlock(); + + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param, value); + if (ret) { + ath12k_warn(ar->ab, "failed to set vdev %d EHT MU mode: %d\n", + arvif->vdev_id, ret); + return false; + } + + return true; +} + +void ath12k_bss_assoc(struct ath12k *ar, + struct ath12k_link_vif *arvif, struct ieee80211_bss_conf *bss_conf) { - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; struct ath12k_wmi_peer_assoc_arg peer_arg; struct ieee80211_sta *ap_sta; + struct ath12k_link_sta *arsta; + struct ath12k_sta *ahsta; struct ath12k_peer *peer; + struct ieee80211_sta_he_cap he_cap; bool is_auth = false; int ret; + struct vdev_up_params params = { 0 }; + u8 link_id; + u16 he_6ghz_capa; lockdep_assert_held(&ar->conf_mutex); - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac vdev %i assoc bssid %pM aid %d\n", - arvif->vdev_id, arvif->bssid, arvif->aid); + if (!arvif) + return; + + link_id = bss_conf->link_id; + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac vdev %i link_id:%d assoc bssid %pM aid %d\n", + arvif->vdev_id, link_id, arvif->bssid, ahvif->aid); rcu_read_lock(); - ap_sta = ieee80211_find_sta(vif, bss_conf->bssid); +// ap_sta = ieee80211_find_sta(vif, bss_conf->bssid); + /* TODO, need check correct or not while debug later. + * ieee80211_sta should find by MLO address for MLO + * or bssid for non-MLO. + */ + ap_sta = ieee80211_find_sta(vif,vif->cfg.ap_addr); + if (!ap_sta) { ath12k_warn(ar->ab, "failed to find station entry for bss %pM vdev %i\n", bss_conf->bssid, arvif->vdev_id); @@ -2074,10 +4142,17 @@ return; } - ath12k_peer_assoc_prepare(ar, vif, ap_sta, &peer_arg, false); + ahsta = ath12k_sta_to_ahsta(ap_sta); + arsta = ahsta->link[link_id]; + + /* he_cap here is updated at assoc success for sta mode only */ + he_cap = ap_sta->link[link_id]->he_cap; + + ath12k_peer_assoc_prepare(ar, arvif, arsta, &peer_arg, false); rcu_read_unlock(); + peer_arg.is_assoc = true; ret = ath12k_wmi_send_peer_assoc_cmd(ar, &peer_arg); if (ret) { ath12k_warn(ar->ab, "failed to run peer assoc for %pM vdev %i: %d\n", @@ -2091,26 +4166,53 @@ return; } + he_6ghz_capa = ap_sta->link[link_id]->he_6ghz_capa.capa; + ret = ath12k_setup_peer_smps(ar, arvif, bss_conf->bssid, - &ap_sta->deflink.ht_cap); + &ap_sta->link[link_id]->ht_cap, + le16_to_cpu(he_6ghz_capa)); if (ret) { ath12k_warn(ar->ab, "failed to setup peer SMPS for vdev %d: %d\n", arvif->vdev_id, ret); return; } + if (!ath12k_mac_vif_recalc_sta_he_txbf(ar, arvif, &he_cap)) { + ath12k_warn(ar->ab, "failed to recalc he txbf for vdev %i on bss %pM\n", + arvif->vdev_id, bss_conf->bssid); + return; + } + WARN_ON(arvif->is_up); - arvif->aid = vif->cfg.aid; + ahvif->aid = vif->cfg.aid; ether_addr_copy(arvif->bssid, bss_conf->bssid); - ret = ath12k_wmi_vdev_up(ar, arvif->vdev_id, arvif->aid, arvif->bssid); + params.vdev_id = arvif->vdev_id; + params.aid = ahvif->aid; + params.bssid = arvif->bssid; + + if (bss_conf->nontransmitted) { + params.profile_idx = bss_conf->bssid_index; + params.profile_count = BIT(bss_conf->bssid_indicator) - 1; + params.tx_bssid = bss_conf->transmitter_bssid; + } + + if (ar->ab->ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1 && + !ar->ab->is_reset) + /* Skip sending vdev up for non-asserted links while + * recovering station vif type + */ + goto skip_vdev_up; + + ret = ath12k_wmi_vdev_up(ar, ¶ms); if (ret) { ath12k_warn(ar->ab, "failed to set vdev %d up: %d\n", arvif->vdev_id, ret); return; } +skip_vdev_up: arvif->is_up = true; ath12k_dbg(ar->ab, ATH12K_DBG_MAC, @@ -2142,15 +4244,23 @@ arvif->vdev_id, ret); } -static void ath12k_bss_disassoc(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) -{ - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = (void *)vif->drv_priv; +void ath12k_bss_disassoc(struct ath12k *ar, + struct ath12k_link_vif *arvif, + bool do_vdev_down) +{ + struct ath12k_vif *tx_ahvif; + struct ath12k_link_vif *tx_arvif; + struct ieee80211_bss_conf *link; int ret; lockdep_assert_held(&ar->conf_mutex); + if (do_vdev_down) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac vdev %i disassoc bssid %pM\n", + arvif->vdev_id, arvif->bssid); + return; + } + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac vdev %i disassoc bssid %pM\n", arvif->vdev_id, arvif->bssid); @@ -2161,7 +4271,25 @@ arvif->is_up = false; + rcu_read_lock(); + link = ath12k_get_link_bss_conf(arvif); + if (!link) + goto unlock; + + if (link->mbssid_tx_vif) { + tx_ahvif = (void *)link->mbssid_tx_vif->drv_priv; + if (!tx_ahvif) + goto unlock; + lockdep_assert_held(&tx_ahvif->ah->conf_mutex); + tx_arvif = tx_ahvif->link[link->mbssid_tx_vif_linkid]; + if (!tx_arvif) + goto unlock; + lockdep_assert_held(&tx_arvif->ar->conf_mutex); + } + /* TODO: cancel connection_loss_work */ +unlock: + rcu_read_unlock(); } static u32 ath12k_mac_get_rate_hw_value(int bitrate) @@ -2190,10 +4318,10 @@ } static void ath12k_recalculate_mgmt_rate(struct ath12k *ar, - struct ieee80211_vif *vif, - struct cfg80211_chan_def *def) + struct ath12k_link_vif *arvif, + struct cfg80211_chan_def *def, + struct ieee80211_bss_conf *link_conf) { - struct ath12k_vif *arvif = (void *)vif->drv_priv; const struct ieee80211_supported_band *sband; u8 basic_rate_idx; int hw_rate_code; @@ -2203,8 +4331,10 @@ lockdep_assert_held(&ar->conf_mutex); - sband = ar->hw->wiphy->bands[def->chan->band]; - basic_rate_idx = ffs(vif->bss_conf.basic_rates) - 1; + sband = ar->ah->hw->wiphy->bands[def->chan->band]; + basic_rate_idx = ffs(link_conf->basic_rates); + if (basic_rate_idx) + basic_rate_idx -= 1; bitrate = sband->bitrates[basic_rate_idx].bitrate; hw_rate_code = ath12k_mac_get_rate_hw_value(bitrate); @@ -2226,11 +4356,13 @@ ath12k_warn(ar->ab, "failed to set beacon tx rate %d\n", ret); } -static int ath12k_mac_fils_discovery(struct ath12k_vif *arvif, +static int ath12k_mac_fils_discovery(struct ath12k_link_vif *arvif, struct ieee80211_bss_conf *info) { + struct ath12k_vif *ahvif = arvif->ahvif; struct ath12k *ar = arvif->ar; struct sk_buff *tmpl; + struct ath12k_hw *ah = ar->ah; int ret; u32 interval; bool unsol_bcast_probe_resp_enabled = false; @@ -2238,7 +4370,8 @@ if (info->fils_discovery.max_interval) { interval = info->fils_discovery.max_interval; - tmpl = ieee80211_get_fils_discovery_tmpl(ar->hw, arvif->vif); + tmpl = ieee80211_get_fils_discovery_tmpl_mlo(ah->hw, ahvif->vif, + info->link_id); if (tmpl) ret = ath12k_wmi_fils_discovery_tmpl(ar, arvif->vdev_id, tmpl); @@ -2246,8 +4379,9 @@ unsol_bcast_probe_resp_enabled = 1; interval = info->unsol_bcast_probe_resp_interval; - tmpl = ieee80211_get_unsol_bcast_probe_resp_tmpl(ar->hw, - arvif->vif); + tmpl = ieee80211_get_unsol_bcast_probe_resp_tmpl_mlo(ah->hw, + ahvif->vif, + info->link_id); if (tmpl) ret = ath12k_wmi_probe_resp_tmpl(ar, arvif->vdev_id, tmpl); @@ -2272,14 +4406,192 @@ return ret; } -static void ath12k_mac_op_bss_info_changed(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, +static void ath12k_mac_non_srg_th_config(struct ath12k *ar, + struct ieee80211_he_obss_pd *he_obss_pd, + u32 *param_val) +{ + s8 non_srg_th = ATH12K_OBSS_PD_THRESHOLD_DISABLED; + + if (he_obss_pd->sr_ctrl & + IEEE80211_HE_SPR_NON_SRG_OBSS_PD_SR_DISALLOWED) { + non_srg_th = ATH12K_OBSS_PD_MAX_THRESHOLD; + } else { + if (he_obss_pd->sr_ctrl & + IEEE80211_HE_SPR_NON_SRG_OFFSET_PRESENT) + non_srg_th = (ATH12K_OBSS_PD_MAX_THRESHOLD + + he_obss_pd->non_srg_max_offset); + + *param_val |= ATH12K_OBSS_PD_NON_SRG_EN; + } + + if (!test_bit(WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT, + ar->ab->wmi_ab.svc_map)) { + if (non_srg_th != ATH12K_OBSS_PD_THRESHOLD_DISABLED) + non_srg_th -= ATH12K_DEFAULT_NOISE_FLOOR; + } + + *param_val |= (non_srg_th & GENMASK(7, 0)); +} + +static void ath12k_mac_srg_th_config(struct ath12k *ar, + struct ieee80211_he_obss_pd *he_obss_pd, + u32 *param_val) +{ + s8 srg_th = 0; + + if (he_obss_pd->sr_ctrl & IEEE80211_HE_SPR_SRG_INFORMATION_PRESENT) { + srg_th = ATH12K_OBSS_PD_MAX_THRESHOLD + he_obss_pd->max_offset; + *param_val |= ATH12K_OBSS_PD_SRG_EN; + } + + if (test_bit(WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT, + ar->ab->wmi_ab.svc_map)) { + *param_val |= ATH12K_OBSS_PD_THRESHOLD_IN_DBM; + *param_val |= FIELD_PREP(GENMASK(15, 8), srg_th); + } else { + /* SRG not supported and threshold in dB */ + *param_val &= ~(ATH12K_OBSS_PD_SRG_EN | + ATH12K_OBSS_PD_THRESHOLD_IN_DBM); + } +} + +static int ath12k_mac_config_obss_pd(struct ath12k *ar, + struct ieee80211_he_obss_pd *he_obss_pd) +{ + u32 bitmap[2], param_id, param_val, pdev_id; + int ret; + + pdev_id = ar->pdev->pdev_id; + + /* Set and enable SRG/non-SRG OBSS PD Threshold */ + param_id = WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD; + if (test_bit(MONITOR_CONF_ENABLED, &ar->monitor_flags)) { + ret = ath12k_wmi_pdev_set_param(ar, param_id, 0, pdev_id); + if (ret) + ath12k_warn(ar->ab, + "Failed to set obss_pd_threshold for pdev: %u\n", + pdev_id); + return ret; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "OBSS PD Params: sr_ctrl %x non_srg_thres %u srg_max %u\n", + he_obss_pd->sr_ctrl, he_obss_pd->non_srg_max_offset, + he_obss_pd->max_offset); + + param_val = 0; + + /* Preparing non-SRG OBSS PD Threshold Configurations */ + ath12k_mac_non_srg_th_config(ar, he_obss_pd, ¶m_val); + + /* Preparing SRG OBSS PD Threshold Configurations */ + ath12k_mac_srg_th_config(ar, he_obss_pd, ¶m_val); + + ret = ath12k_wmi_pdev_set_param(ar, param_id, param_val, pdev_id); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set obss_pd_threshold for pdev: %u\n", + pdev_id); + return ret; + } + + /* Enable OBSS PD for all access category */ + param_id = WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC; + param_val = 0xf; + ret = ath12k_wmi_pdev_set_param(ar, param_id, param_val, pdev_id); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set obss_pd_per_ac for pdev: %u\n", + pdev_id); + return ret; + } + + /* Set SR Prohibit */ + param_id = WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT; + param_val = !!(he_obss_pd->sr_ctrl & + IEEE80211_HE_SPR_HESIGA_SR_VAL15_ALLOWED); + ret = ath12k_wmi_pdev_set_param(ar, param_id, param_val, pdev_id); + if (ret) { + ath12k_warn(ar->ab, "Failed to set sr_prohibit for pdev: %u\n", + pdev_id); + return ret; + } + + if (!test_bit(WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT, + ar->ab->wmi_ab.svc_map)) + return 0; + + /* Set SRG BSS Color Bitmap */ + memcpy(bitmap, he_obss_pd->bss_color_bitmap, sizeof(bitmap)); + ret = ath12k_wmi_pdev_set_srg_bss_color_bitmap(ar, bitmap); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set bss_color_bitmap for pdev: %u\n", + pdev_id); + return ret; + } + + /* Set SRG Partial BSSID Bitmap */ + memcpy(bitmap, he_obss_pd->partial_bssid_bitmap, sizeof(bitmap)); + ret = ath12k_wmi_pdev_set_srg_patial_bssid_bitmap(ar, bitmap); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set partial_bssid_bitmap for pdev: %u\n", + pdev_id); + return ret; + } + + memset(bitmap, 0xff, sizeof(bitmap)); + + /* Enable all BSS Colors for SRG */ + ret = ath12k_wmi_pdev_srg_obss_color_enable_bitmap(ar, bitmap); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set srg_color_en_bitmap pdev: %u\n", + pdev_id); + return ret; + } + + /* Enable all patial BSSID mask for SRG */ + ret = ath12k_wmi_pdev_srg_obss_bssid_enable_bitmap(ar, bitmap); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set srg_bssid_en_bitmap pdev: %u\n", + pdev_id); + return ret; + } + + /* Enable all BSS Colors for non-SRG */ + ret = ath12k_wmi_pdev_non_srg_obss_color_enable_bitmap(ar, bitmap); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set non_srg_color_en_bitmap pdev: %u\n", + pdev_id); + return ret; + } + + /* Enable all patial BSSID mask for non-SRG */ + ret = ath12k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(ar, bitmap); + if (ret) { + ath12k_warn(ar->ab, + "Failed to set non_srg_bssid_en_bitmap pdev: %u\n", + pdev_id); + return ret; + } + + return 0; +} + +void ath12k_mac_bss_info_changed(struct ath12k *ar, + struct ath12k_link_vif *arvif, struct ieee80211_bss_conf *info, u64 changed) { - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct ath12k_vif *ahvif = arvif->ahvif, *tx_ahvif; + struct ath12k_link_vif *tx_arvif; + struct ieee80211_vif *vif = ahvif->vif; struct cfg80211_chan_def def; + struct vdev_up_params params = { 0 }; u32 param_id, param_value; enum nl80211_band band; u32 vdev_param; @@ -2290,8 +4602,13 @@ int ret; u8 rateidx; u32 rate; + bool color_collision_detect; + u8 link_id = arvif->link_id; - mutex_lock(&ar->conf_mutex); + lockdep_assert_held(&ar->conf_mutex); + + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) + return; if (changed & BSS_CHANGED_BEACON_INT) { arvif->beacon_interval = info->beacon_int; @@ -2311,7 +4628,7 @@ if (changed & BSS_CHANGED_BEACON) { param_id = WMI_PDEV_PARAM_BEACON_TX_MODE; - param_value = WMI_BEACON_STAGGERED_MODE; + param_value = WMI_BEACON_BURST_MODE; ret = ath12k_wmi_pdev_set_param(ar, param_id, param_value, ar->pdev->pdev_id); if (ret) @@ -2322,10 +4639,87 @@ "Set staggered beacon mode for VDEV: %d\n", arvif->vdev_id); + if ((!arvif->do_not_send_tmpl || !arvif->bcca_zero_sent) && + arvif->is_started) { + /* need to install Transmitting vif's template first */ + ret = ath12k_mac_setup_bcn_tmpl(arvif); if (ret) ath12k_warn(ar->ab, "failed to update bcn template: %d\n", ret); + + if (!arvif->pending_csa_up) + goto skip_pending_cs_up; + + memset(¶ms, 0, sizeof(params)); + params.vdev_id = arvif->vdev_id; + params.aid = ahvif->aid; + params.bssid = arvif->bssid; + + if (info->mbssid_tx_vif) { + tx_ahvif = (void *)info->mbssid_tx_vif->drv_priv; + tx_arvif = tx_ahvif->link[info->mbssid_tx_vif_linkid]; + params.tx_bssid = tx_arvif->bssid; + params.profile_idx = ahvif->vif->bss_conf.bssid_index; + params.profile_count = BIT(info->bssid_indicator); + } + + if (info->mbssid_tx_vif && arvif != tx_arvif && + tx_arvif->pending_csa_up) { + /* skip non tx vif's */ + goto skip_pending_cs_up; + } + ret = ath12k_wmi_vdev_up(arvif->ar, ¶ms); + if (ret) + ath12k_warn(ar->ab, "failed to bring vdev up %d: %d\n", + arvif->vdev_id, ret); + + arvif->pending_csa_up = false; + + if (info->mbssid_tx_vif && arvif == tx_arvif) { + struct ath12k_link_vif *arvif_itr; + list_for_each_entry(arvif_itr, &ar->arvifs, list) { + if (!arvif_itr->pending_csa_up) + continue; + + memset(¶ms, 0, sizeof(params)); + params.vdev_id = arvif_itr->vdev_id; + params.aid = ahvif->aid; + params.bssid = arvif_itr->bssid; + params.tx_bssid = tx_arvif->bssid; + params.profile_idx = + ahvif->vif->bss_conf.bssid_index; + params.profile_count = + BIT(info->bssid_indicator); + ret = ath12k_wmi_vdev_up(arvif_itr->ar, ¶ms); + if (ret) + ath12k_warn(ar->ab, "failed to bring vdev up %d: %d\n", + arvif_itr->vdev_id, ret); + arvif_itr->pending_csa_up = false; + } + } + } +skip_pending_cs_up: + if (arvif->bcca_zero_sent) + arvif->do_not_send_tmpl = true; + else + arvif->do_not_send_tmpl = false; + + if (arvif->is_up && info->he_support) { + param_id = WMI_VDEV_PARAM_BA_MODE; + + if (info->eht_support) + param_value = WMI_BA_MODE_BUFFER_SIZE_1024; + else + param_value = WMI_BA_MODE_BUFFER_SIZE_256; + + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, + param_id, param_value); + if (ret) + ath12k_warn(ar->ab, + "failed to set BA BUFFER SIZE %d for vdev: %d\n", + param_value, arvif->vdev_id); + } } if (changed & (BSS_CHANGED_BEACON_INFO | BSS_CHANGED_BEACON)) { @@ -2347,31 +4741,31 @@ if (changed & BSS_CHANGED_SSID && vif->type == NL80211_IFTYPE_AP) { - arvif->u.ap.ssid_len = vif->cfg.ssid_len; + ahvif->u.ap.ssid_len = vif->cfg.ssid_len; if (vif->cfg.ssid_len) - memcpy(arvif->u.ap.ssid, vif->cfg.ssid, vif->cfg.ssid_len); - arvif->u.ap.hidden_ssid = info->hidden_ssid; + memcpy(ahvif->u.ap.ssid, vif->cfg.ssid, vif->cfg.ssid_len); + ahvif->u.ap.hidden_ssid = info->hidden_ssid; } - if (changed & BSS_CHANGED_BSSID && !is_zero_ether_addr(info->bssid)) + if (changed & BSS_CHANGED_BSSID && info->bssid && !is_zero_ether_addr(info->bssid)) ether_addr_copy(arvif->bssid, info->bssid); - if (changed & BSS_CHANGED_BEACON_ENABLED) { + /* pending_up is not needed for recovered ab during Mode1 scenario */ + if (changed & BSS_CHANGED_BEACON_ENABLED && !arvif->is_started && !ar->ab->recovery_start) + arvif->pending_up = true; + + if (changed & BSS_CHANGED_BEACON_ENABLED && arvif->is_started) { + if (info->enable_beacon) { + ath12k_mac_set_he_txbf_conf(arvif); + ath12k_mac_set_eht_txbf_conf(arvif); + } ath12k_control_beaconing(arvif, info); - if (arvif->is_up && vif->bss_conf.he_support && - vif->bss_conf.he_oper.params) { - /* TODO: Extend to support 1024 BA Bitmap size */ - ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, - WMI_VDEV_PARAM_BA_MODE, - WMI_BA_MODE_BUFFER_SIZE_256); - if (ret) - ath12k_warn(ar->ab, - "failed to set BA BUFFER SIZE 256 for vdev: %d\n", - arvif->vdev_id); + if (arvif->is_up && info->he_support) { + if (info->he_oper.params) { param_id = WMI_VDEV_PARAM_HEOPS_0_31; - param_value = vif->bss_conf.he_oper.params; + param_value = info->he_oper.params; ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param_id, param_value); ath12k_dbg(ar->ab, ATH12K_DBG_MAC, @@ -2381,6 +4775,8 @@ if (ret) ath12k_warn(ar->ab, "Failed to set he oper params %x for VDEV %d: %i\n", param_value, arvif->vdev_id, ret); + + } } } @@ -2447,28 +4843,30 @@ if (changed & BSS_CHANGED_ASSOC) { if (vif->cfg.assoc) - ath12k_bss_assoc(hw, vif, info); + ath12k_bss_assoc(ar, arvif, info); else - ath12k_bss_disassoc(hw, vif); + ath12k_bss_disassoc(ar, arvif, false); } if (changed & BSS_CHANGED_TXPOWER) { ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac vdev_id %i txpower %d\n", arvif->vdev_id, info->txpower); - arvif->txpower = info->txpower; ath12k_mac_txpower_recalc(ar); } if (changed & BSS_CHANGED_MCAST_RATE && - !ath12k_mac_vif_chan(arvif->vif, &def)) { + !ath12k_mac_vif_chan(ahvif->vif, &def, link_id)) { band = def.chan->band; - mcast_rate = vif->bss_conf.mcast_rate[band]; + mcast_rate = info->mcast_rate[band]; - if (mcast_rate > 0) + if (mcast_rate > 0) { rateidx = mcast_rate - 1; - else - rateidx = ffs(vif->bss_conf.basic_rates) - 1; + } else { + rateidx = ffs(info->basic_rates); + if (rateidx) + rateidx -= 1; + } if (ar->pdev->cap.supported_bands & WMI_HOST_WLAN_5G_CAP) rateidx += ATH12K_MAC_FIRST_OFDM_RATE_IDX; @@ -2505,8 +4903,8 @@ } if (changed & BSS_CHANGED_BASIC_RATES && - !ath12k_mac_vif_chan(arvif->vif, &def)) - ath12k_recalculate_mgmt_rate(ar, vif, &def); + !ath12k_mac_vif_chan(ahvif->vif, &def, link_id)) + ath12k_recalculate_mgmt_rate(ar, arvif, &def, info); if (changed & BSS_CHANGED_TWT) { if (info->twt_requester || info->twt_responder) @@ -2516,19 +4914,39 @@ } if (changed & BSS_CHANGED_HE_OBSS_PD) - ath12k_wmi_send_obss_spr_cmd(ar, arvif->vdev_id, - &info->he_obss_pd); + ath12k_mac_config_obss_pd(ar, &info->he_obss_pd); if (changed & BSS_CHANGED_HE_BSS_COLOR) { + color_collision_detect = (info->he_bss_color.enabled && + info->he_bss_color.collision_detection_enabled); if (vif->type == NL80211_IFTYPE_AP) { ret = ath12k_wmi_obss_color_cfg_cmd(ar, arvif->vdev_id, info->he_bss_color.color, ATH12K_BSS_COLOR_AP_PERIODS, - info->he_bss_color.enabled); + info->nontransmitted ? + 0 : color_collision_detect); if (ret) ath12k_warn(ar->ab, "failed to set bss color collision on vdev %i: %d\n", arvif->vdev_id, ret); + + param_id = WMI_VDEV_PARAM_BSS_COLOR; + param_value = info->he_bss_color.color << IEEE80211_HE_OPERATION_BSS_COLOR_OFFSET; + + if (!info->he_bss_color.enabled) + param_value |= IEEE80211_HE_OPERATION_BSS_COLOR_DISABLED; + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, + param_id, + param_value); + if (ret) + ath12k_warn(ar->ab, + "failed to set bss color param on vdev %i: %d\n", + arvif->vdev_id, ret); + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "bss color param 0x%x set on vdev %i\n", + param_value, arvif->vdev_id); + } else if (vif->type == NL80211_IFTYPE_STATION) { ret = ath12k_wmi_send_bss_color_change_enable_cmd(ar, arvif->vdev_id, @@ -2550,12 +4968,330 @@ if (changed & BSS_CHANGED_FILS_DISCOVERY || changed & BSS_CHANGED_UNSOL_BCAST_PROBE_RESP) ath12k_mac_fils_discovery(arvif, info); +} + +static void ath12k_mac_op_vif_cfg_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + u64 changed) +{ + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_link_vif *arvif; + struct ath12k *ar; + unsigned long link_id; + struct ieee80211_bss_conf *info; + + if (changed & BSS_CHANGED_SSID && + vif->type == NL80211_IFTYPE_AP) { + ahvif->u.ap.ssid_len = vif->cfg.ssid_len; + if (vif->cfg.ssid_len) + memcpy(ahvif->u.ap.ssid, vif->cfg.ssid, vif->cfg.ssid_len); + } + + link_id = ahvif->deflink.link_id; + + if (changed & BSS_CHANGED_ASSOC) { + for_each_set_bit(link_id, &ahvif->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + info = vif->link_conf[link_id]; + ar = arvif->ar; + if (vif->cfg.assoc) { + if (info) + ath12k_bss_assoc(ar, arvif, info); + } else { + ath12k_bss_disassoc(ar, arvif, false); + } + } + } +} + +static void ath12k_mac_op_bss_info_changed(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *info, + u64 changed) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_link_vif *arvif; + struct ath12k *ar; + u8 link_id = info->link_id; + + mutex_lock(&ah->conf_mutex); + arvif = ahvif->link[link_id]; + + if (arvif == NULL || !arvif->is_created) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "bss info parameter changes %llx cached to apply after vdev create on channel assign\n", + changed); + + ahvif->cache[link_id].bss_conf_changed |= changed; + mutex_unlock(&ah->conf_mutex); + return; + } + + ar = arvif->ar; + + if (!ar) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "bss info parameter changes %llx cached to apply after vdev create on channel assign\n", + changed); + ahvif->cache[link_id].bss_conf_changed |= changed; + mutex_unlock(&ah->conf_mutex); + return; + } + + mutex_lock(&ar->conf_mutex); + + ath12k_mac_bss_info_changed(ar, arvif, info, changed); mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); +} + +static int ath12k_mac_vdev_delete(struct ath12k *ar, struct ath12k_link_vif *arvif) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + unsigned long time_left; + int ret = 0; + + lockdep_assert_held(&ar->conf_mutex); + + reinit_completion(&ar->vdev_delete_done); + + ret = ath12k_wmi_vdev_delete(ar, arvif->vdev_id); + if (ret) { + ath12k_warn(ar->ab, "failed to delete WMI scan vdev %d: %d\n", + arvif->vdev_id, ret); + goto clean_up; + } + + time_left = wait_for_completion_timeout(&ar->vdev_delete_done, + ATH12K_VDEV_DELETE_TIMEOUT_HZ); + if (time_left == 0) { + ath12k_warn(ar->ab, "Timeout in receiving vdev delete response vdev_id : %d\n", + arvif->vdev_id); + ret = -ETIMEDOUT; + goto clean_up; + } + + spin_lock_bh(&ar->ab->base_lock); + ar->ab->free_vdev_map |= 1LL << arvif->vdev_id; + spin_unlock_bh(&ar->ab->base_lock); + +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + if (arvif->link_id != ATH12K_DEFAULT_SCAN_LINK && arvif->ndev_pvt) { + if (arvif->ndev_pvt->is_bond_enslaved) + ath12k_bond_link_release(arvif); + ath12k_disable_ppe_for_link_netdev(ar->ab, arvif, + arvif->ndev_pvt->link_ndev); + } +#endif + ar->allocated_vdev_map &= ~(1LL << arvif->vdev_id); + ar->ab->free_vdev_stats_id_map &= ~(1LL << arvif->vdev_stats_id); + ar->num_created_vdevs--; + arvif->ahvif->num_vdev_created--; + + ath12k_dbg(ar->ab, ATH12K_DBG_SET(MAC, L1), "mac vdev delete id %d type %d subtype %d map %llx\n", + arvif->vdev_id, ahvif->vdev_type, ahvif->vdev_subtype, + ar->ab->free_vdev_map); +clean_up: + arvif->is_created = false; + arvif->is_scan_vif = false; + arvif->ar = NULL; + spin_lock_bh(&ar->data_lock); + list_del(&arvif->list); + spin_unlock_bh(&ar->data_lock); + + return ret; +} + +static int ath12k_mac_vdev_stop(struct ath12k_link_vif *arvif) +{ + struct ath12k *ar = arvif->ar; + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + if (!arvif->vdev_stop_notify_done) { + reinit_completion(&ar->vdev_setup_done); + + ret = ath12k_wmi_vdev_stop(ar, arvif->vdev_id); + if (ret) { + ath12k_warn(ar->ab, "failed to stop WMI vdev %i: %d\n", + arvif->vdev_id, ret); + return ret; + } + arvif->vdev_stop_notify_done = true; + + ret = ath12k_mac_vdev_setup_sync(ar); + if (ret) { + ath12k_warn(ar->ab, "failed to synchronize setup for vdev %i: %d\n", + arvif->vdev_id, ret); + return ret; + } + } + + memset(&ar->wmm_stats, 0, sizeof(struct ath12k_wmm_stats)); + WARN_ON(ar->num_started_vdevs == 0); + + ar->num_started_vdevs--; + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "vdev %pM stopped, vdev_id %d\n", + arvif->addr, arvif->vdev_id); + + if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { + clear_bit(ATH12K_CAC_RUNNING, &ar->dev_flags); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "CAC Stopped for vdev %d\n", + arvif->vdev_id); + } + + return 0; +} + +static int +ath12k_mac_find_link_id_by_freq(struct ieee80211_vif *vif, struct ath12k *ar, u32 freq) +{ + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + u16 link_id; + + lockdep_assert_held(&ahvif->ah->conf_mutex); + + if (!vif->valid_links) + return 0; + + for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) { + if (!(ahvif->links_map & BIT(link_id)) || + !ahvif->link[link_id]->ar) + continue; + if (freq >= ahvif->link[link_id]->ar->chan_info.low_freq && + freq <= ahvif->link[link_id]->ar->chan_info.high_freq) + return link_id; + } + + /* Use a default link for scan purpose in driver if the request + * cannot be mapped to any of the active links(channel assigned) + */ + return ATH12K_DEFAULT_SCAN_LINK; +} + +void ath12k_mac_unassign_link_vif(struct ath12k_link_vif *arvif) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k_hw *ah = ahvif->ah; + + lockdep_assert_held(&ah->conf_mutex); + + ahvif->link[arvif->link_id] = NULL; + ahvif->links_map &= ~BIT(arvif->link_id); + + if (arvif != &ahvif->deflink) + kfree(arvif); + else + memset(arvif->addr, 0, ETH_ALEN); +} + +struct ath12k_link_vif * +ath12k_mac_assign_link_vif( struct ath12k_hw *ah, struct ieee80211_vif *vif, u8 link_id) +{ + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + int i; + + lockdep_assert_held(&ah->conf_mutex); + + if(ahvif->link[link_id]) + return ahvif->link[link_id]; + + /* Not a ML vif */ + if (!vif->valid_links) { + link_id = 0; + arvif = &ahvif->deflink; + } else { + /* first link vif is fetched from deflink except for scan arvifs */ + if (!ahvif->links_map && link_id != ATH12K_DEFAULT_SCAN_LINK) { + arvif = &ahvif->deflink; + } else { + arvif = (struct ath12k_link_vif *) + kzalloc(sizeof(struct ath12k_link_vif), + GFP_KERNEL); + + if (arvif == NULL) + return NULL; + + INIT_LIST_HEAD(&arvif->list); + INIT_WORK(&arvif->update_obss_color_notify_work, + ath12k_update_obss_color_notify_work); + INIT_WORK(&arvif->update_bcn_template_work, + ath12k_update_bcn_template_work); + arvif->num_stations = 0; + init_completion(&arvif->peer_ch_width_switch_send); + INIT_WORK(&arvif->peer_ch_width_switch_work, + ath12k_wmi_peer_chan_width_switch_work); + } + } + + ahvif->link[link_id] = arvif; + arvif->ahvif = ahvif; + arvif->link_id = link_id; + ahvif->links_map |= BIT(link_id); + + for (i = 0; i < ARRAY_SIZE(arvif->bitrate_mask.control); i++) { + arvif->bitrate_mask.control[i].legacy = 0xffffffff; + arvif->bitrate_mask.control[i].gi = NL80211_TXRATE_FORCE_SGI; + memset(arvif->bitrate_mask.control[i].ht_mcs, 0xff, + sizeof(arvif->bitrate_mask.control[i].ht_mcs)); + memset(arvif->bitrate_mask.control[i].vht_mcs, 0xff, + sizeof(arvif->bitrate_mask.control[i].vht_mcs)); + memset(arvif->bitrate_mask.control[i].he_mcs, 0xff, + sizeof(arvif->bitrate_mask.control[i].he_mcs)); + memset(arvif->bitrate_mask.control[i].eht_mcs, 0xff, + sizeof(arvif->bitrate_mask.control[i].eht_mcs)); + } + + return arvif; +} + +static struct ath12k* +ath12k_mac_select_scan_device(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + u32 center_freq) +{ + struct ath12k_hw *ah = hw->priv; + enum nl80211_band band; + struct ath12k *ar; + int i; + + /* Loop through first channel and determine the scan radio + * NOTE: There could be 5G low/high channels in that case + * split the hw request and perform multiple scans + */ + + if (center_freq < ATH12K_MIN_5G_FREQ) + band = NL80211_BAND_2GHZ; + else if (center_freq < ATH12K_MIN_6G_FREQ) + band = NL80211_BAND_5GHZ; + else + band = NL80211_BAND_6GHZ; + + ar = ah->radio; + + for (i = 0; i < ah->num_radio; i++) { + if (band == NL80211_BAND_5GHZ) { + if (center_freq > ar->chan_info.low_freq && + center_freq < ar->chan_info.high_freq) + if (ar->mac.sbands[band].channels) + return ar; + } else if (ar->mac.sbands[band].channels) { + return ar; + } + ar++; + } + + return NULL; } void __ath12k_mac_scan_finish(struct ath12k *ar) { + struct ath12k_hw *ah = ar->ah; + lockdep_assert_held(&ar->data_lock); switch (ar->scan.state) { @@ -2563,23 +5299,26 @@ break; case ATH12K_SCAN_RUNNING: case ATH12K_SCAN_ABORTING: + if (ar->scan.is_roc && ar->scan.roc_notify) + ieee80211_remain_on_channel_expired(ah->hw); + fallthrough; + case ATH12K_SCAN_STARTING: if (!ar->scan.is_roc) { struct cfg80211_scan_info info = { - .aborted = (ar->scan.state == - ATH12K_SCAN_ABORTING), + .aborted = ((ar->scan.state == + ATH12K_SCAN_ABORTING) || + (ar->scan.state == + ATH12K_SCAN_STARTING)) }; - ieee80211_scan_completed(ar->hw, &info); - } else if (ar->scan.roc_notify) { - ieee80211_remain_on_channel_expired(ar->hw); + ieee80211_scan_completed(ah->hw, &info); } - fallthrough; - case ATH12K_SCAN_STARTING: ar->scan.state = ATH12K_SCAN_IDLE; ar->scan_channel = NULL; ar->scan.roc_freq = 0; cancel_delayed_work(&ar->scan.timeout); complete(&ar->scan.completed); + ieee80211_queue_work(ah->hw, &ar->scan.vdev_del_wk); break; } } @@ -2679,6 +5418,51 @@ mutex_unlock(&ar->conf_mutex); } +static void ath12k_scan_vdev_del_work(struct work_struct *work) +{ + struct ath12k *ar = container_of(work, struct ath12k, + scan.vdev_del_wk); + struct ath12k_hw *ah = ar->ah; + struct ath12k_link_vif *arvif; + + if (unlikely(test_bit(ATH12K_FLAG_RECOVERY, &ar->ab->dev_flags))) + return; + + mutex_lock(&ah->conf_mutex); + mutex_lock(&ar->conf_mutex); + /* scan vdev got deleted already. This can happen when on same vif, new + * scan request was requested with different frequeny which leads to + * movement of scan arvif from one radio to another radio */ + if (ar->scan.vdev_id == -1) + goto work_complete; + + mutex_unlock(&ar->conf_mutex); + + arvif = ath12k_mac_get_arvif(ar, ar->scan.vdev_id); + /* should not happen */ + if (!arvif) { + ath12k_warn(ar->ab, "mac scan vdev del on unknow vdev_id %d\n", + ar->scan.vdev_id); + mutex_unlock(&ah->conf_mutex); + return; + } + + if (arvif->is_started) { + mutex_lock(&ar->conf_mutex); + ar->scan.vdev_id = -1; + goto work_complete; + } + + ath12k_mac_remove_link_interface(ah->hw, arvif); + ath12k_mac_unassign_link_vif(arvif); + + mutex_lock(&ar->conf_mutex); + ar->scan.vdev_id = -1; +work_complete: + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); +} + static int ath12k_start_scan(struct ath12k *ar, struct ath12k_wmi_scan_req_arg *arg) { @@ -2686,6 +5470,9 @@ lockdep_assert_held(&ar->conf_mutex); + if (ath12k_spectral_get_mode(ar) == ATH12K_SPECTRAL_BACKGROUND) + ath12k_spectral_reset_buffer(ar); + ret = ath12k_wmi_send_scan_start_cmd(ar, arg); if (ret) return ret; @@ -2717,12 +5504,92 @@ struct ieee80211_vif *vif, struct ieee80211_scan_request *hw_req) { - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_hw *ah = hw->priv; + struct ath12k_link_vif *arvif; + struct ath12k *ar; struct cfg80211_scan_request *req = &hw_req->req; struct ath12k_wmi_scan_req_arg arg = {}; int ret; - int i; + int i, link_id; + bool create = true; + + mutex_lock(&ah->conf_mutex); + + /* Since the targeted scan device could depend on the frequency + * requested in the hw_req, select the corresponding radio + */ + ar = ath12k_mac_select_scan_device(hw, vif, hw_req->req.channels[0]->center_freq); + if (!ar) { + ath12k_err(NULL, "unable to select device for scan\n"); + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + + if (unlikely(test_bit(ATH12K_FLAG_RECOVERY, &ar->ab->dev_flags))) { + mutex_unlock(&ah->conf_mutex); + return -ESHUTDOWN; + } + + link_id = ath12k_mac_find_link_id_by_freq(vif, ar, + hw_req->req.channels[0]->center_freq); + + arvif = ath12k_mac_assign_link_vif(ah, vif, link_id); + /* If the vif is already assigned to a specific vdev of an ar, + * check whether its already started, vdev which is started + * are not allowed to switch to a new radio. + * If the vdev is not started, but was earlier created on a + * different ar, delete that vdev and create a new one. We don't + * delete at the scan stop as an optimization to avoid redundant + * delete-create vdev's for the same ar, in case the request is + * always on the same band for the vif + */ + if (!arvif) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + if (arvif->link_id == ATH12K_DEFAULT_SCAN_LINK && + (!is_broadcast_ether_addr(req->bssid) && + !is_zero_ether_addr(req->bssid))) { + memcpy(arvif->addr, req->bssid, ETH_ALEN); + } + + if (arvif->is_created) { + if (ar != arvif->ar && arvif->is_started) { + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } else if (ar != arvif->ar) { + if (!arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + mutex_lock(&arvif->ar->conf_mutex); + if (arvif->ar->scan.vdev_id != -1) + arvif->ar->scan.vdev_id = -1; + mutex_unlock(&arvif->ar->conf_mutex); + + ath12k_mac_remove_link_interface(hw, arvif); + ath12k_mac_unassign_link_vif(arvif); + } else { + create = false; + } + } + + if (create) { + arvif = ath12k_mac_assign_link_vif(ah, vif, link_id); + mutex_lock(&ar->conf_mutex); + ret = ath12k_mac_vdev_create(ar, arvif); + if (ret) { + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + ath12k_warn(ar->ab, "unable to create scan vdev %d\n", ret); + return -EINVAL; + } + mutex_unlock(&ar->conf_mutex); + } + + mutex_unlock(&ah->conf_mutex); mutex_lock(&ar->conf_mutex); @@ -2767,6 +5634,14 @@ if (req->n_channels) { arg.num_chan = req->n_channels; + arg.chan_list = kcalloc(arg.num_chan, sizeof(*arg.chan_list), + GFP_KERNEL); + + if (!arg.chan_list) { + ret = -ENOMEM; + goto exit; + } + for (i = 0; i < arg.num_chan; i++) arg.chan_list[i] = req->channels[i]->center_freq; } @@ -2779,12 +5654,21 @@ spin_unlock_bh(&ar->data_lock); } + /* As per cfg80211/mac80211 scan design, it allows only + * scan at a time. Hence last_scan link id is used for + * tracking the link id on which the scan is been done + * on this vif + */ + ahvif->last_scan_link = arvif->link_id; + /* Add a margin to account for event/command processing */ - ieee80211_queue_delayed_work(ar->hw, &ar->scan.timeout, + ieee80211_queue_delayed_work(ar->ah->hw, &ar->scan.timeout, msecs_to_jiffies(arg.max_scan_time + ATH12K_MAC_SCAN_TIMEOUT_MSECS)); exit: + kfree(arg.chan_list); + if (req->ie_len) kfree(arg.extraie.ptr); @@ -2795,7 +5679,35 @@ static void ath12k_mac_op_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif) { - struct ath12k *ar = hw->priv; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_link_vif *arvif; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + u8 link_id = ahvif->last_scan_link; + + mutex_lock(&ah->conf_mutex); + + if (!(ahvif->links_map & BIT(link_id))) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(NULL, "unable to select device to cancel scan\n"); + return; + } + + arvif = ahvif->link[link_id]; + + if (!arvif->is_created) { + ath12k_err(NULL, "unable to select device to cancel scan\n"); + mutex_unlock(&ah->conf_mutex); + return; + } + + ar = arvif->ar; + if (!ar) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(NULL, "unable to select device to cancel scan\n"); + return; + } + mutex_unlock(&ah->conf_mutex); mutex_lock(&ar->conf_mutex); ath12k_scan_abort(ar); @@ -2804,13 +5716,15 @@ cancel_delayed_work_sync(&ar->scan.timeout); } -static int ath12k_install_key(struct ath12k_vif *arvif, +static int ath12k_install_key(struct ath12k_link_vif *arvif, struct ieee80211_key_conf *key, enum set_key_cmd cmd, const u8 *macaddr, u32 flags) { int ret; + struct ath12k_vif *ahvif = arvif->ahvif; struct ath12k *ar = arvif->ar; + struct ath12k_hw_group *ag = ar->ab->ag; struct wmi_vdev_install_key_arg arg = { .vdev_id = arvif->vdev_id, .key_idx = key->keyidx, @@ -2824,7 +5738,7 @@ reinit_completion(&ar->install_key_done); - if (test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) + if (test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ag->dev_flags)) return 0; if (cmd == DISABLE_KEY) { @@ -2852,13 +5766,24 @@ case WLAN_CIPHER_SUITE_GCMP: case WLAN_CIPHER_SUITE_GCMP_256: arg.key_cipher = WMI_CIPHER_AES_GCM; + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV_MGMT; + break; + case WLAN_CIPHER_SUITE_AES_CMAC: + arg.key_cipher = WMI_CIPHER_AES_CMAC; + break; + case WLAN_CIPHER_SUITE_BIP_GMAC_128: + case WLAN_CIPHER_SUITE_BIP_GMAC_256: + arg.key_cipher = WMI_CIPHER_AES_GMAC; + break; + case WLAN_CIPHER_SUITE_BIP_CMAC_256: + arg.key_cipher = WMI_CIPHER_NONE; break; default: ath12k_warn(ar->ab, "cipher %d is not supported\n", key->cipher); return -EOPNOTSUPP; } - if (test_bit(ATH12K_FLAG_RAW_MODE, &ar->ab->dev_flags)) + if (test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV | IEEE80211_KEY_FLAG_RESERVE_TAILROOM; @@ -2871,13 +5796,15 @@ if (!wait_for_completion_timeout(&ar->install_key_done, 1 * HZ)) return -ETIMEDOUT; - if (ether_addr_equal(macaddr, arvif->vif->addr)) - arvif->key_cipher = key->cipher; + if (ether_addr_equal(macaddr, arvif->addr)) { + ahvif->key_cipher = key->cipher; + ath12k_dp_tx_update_bank_profile(arvif); + } return ar->install_key_status ? -EINVAL : 0; } -static int ath12k_clear_peer_keys(struct ath12k_vif *arvif, +static int ath12k_clear_peer_keys(struct ath12k_link_vif *arvif, const u8 *addr) { struct ath12k *ar = arvif->ar; @@ -2919,40 +5846,52 @@ return first_errno; } -static int ath12k_mac_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, - struct ieee80211_vif *vif, struct ieee80211_sta *sta, +int ath12k_mac_set_key(struct ath12k *ar, enum set_key_cmd cmd, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, struct ieee80211_key_conf *key) { - struct ath12k *ar = hw->priv; - struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct ath12k_base *ab; struct ath12k_peer *peer; - struct ath12k_sta *arsta; + struct ath12k_sta *ahsta = NULL; const u8 *peer_addr; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + struct ieee80211_bss_conf *link_conf; int ret = 0; u32 flags = 0; + u8 link_id = arvif->link_id; + struct ieee80211_sta *sta = NULL; - /* BIP needs to be done in software */ - if (key->cipher == WLAN_CIPHER_SUITE_AES_CMAC || - key->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_128 || - key->cipher == WLAN_CIPHER_SUITE_BIP_GMAC_256 || - key->cipher == WLAN_CIPHER_SUITE_BIP_CMAC_256) - return 1; + if (arsta) { + ahsta = arsta->ahsta; + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + } - if (test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) - return 1; + if (sta && sta->mlo && + (test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &ar->ab->dev_flags))) + return 0; - if (key->keyidx > WMI_MAX_KEY_INDEX) - return -ENOSPC; + lockdep_assert_held(&ar->ah->conf_mutex); - mutex_lock(&ar->conf_mutex); + rcu_read_lock(); + link_conf = rcu_dereference(vif->link_conf[link_id]); + + if (!link_conf) { + rcu_read_unlock(); + return -EINVAL; + } + + ab = ar->ab; if (sta) - peer_addr = sta->addr; - else if (arvif->vdev_type == WMI_VDEV_TYPE_STA) - peer_addr = vif->bss_conf.bssid; + peer_addr = arsta->addr; + else if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) + peer_addr = link_conf->bssid; else - peer_addr = vif->addr; + peer_addr = link_conf->addr; + + rcu_read_unlock(); key->hw_key_idx = key->keyidx; @@ -2968,12 +5907,12 @@ ath12k_warn(ab, "cannot install key for non-existent peer %pM\n", peer_addr); ret = -EOPNOTSUPP; - goto exit; + goto out; } else { /* if the peer doesn't exist there is no key to disable * anymore */ - goto exit; + goto out; } } @@ -2984,14 +5923,15 @@ ret = ath12k_install_key(arvif, key, cmd, peer_addr, flags); if (ret) { - ath12k_warn(ab, "ath12k_install_key failed (%d)\n", ret); - goto exit; + ath12k_warn(ab, "ath12k_install_key cmd %d failed (%d) for peer %pM on vdev %d (link id %d)\n", + cmd, ret, peer_addr, arvif->vdev_id, link_id); + goto out; } ret = ath12k_dp_rx_peer_pn_replay_config(arvif, peer_addr, cmd, key); if (ret) { ath12k_warn(ab, "failed to offload PN replay detection %d\n", ret); - goto exit; + goto out; } spin_lock_bh(&ab->base_lock); @@ -3016,8 +5956,6 @@ ath12k_warn(ab, "peer %pM disappeared!\n", peer_addr); if (sta) { - arsta = (struct ath12k_sta *)sta->drv_priv; - switch (key->cipher) { case WLAN_CIPHER_SUITE_TKIP: case WLAN_CIPHER_SUITE_CCMP: @@ -3025,23 +5963,145 @@ case WLAN_CIPHER_SUITE_GCMP: case WLAN_CIPHER_SUITE_GCMP_256: if (cmd == SET_KEY) - arsta->pn_type = HAL_PN_TYPE_WPA; + ahsta->pn_type = HAL_PN_TYPE_WPA; else - arsta->pn_type = HAL_PN_TYPE_NONE; + ahsta->pn_type = HAL_PN_TYPE_NONE; break; default: - arsta->pn_type = HAL_PN_TYPE_NONE; + ahsta->pn_type = HAL_PN_TYPE_NONE; break; } } spin_unlock_bh(&ab->base_lock); -exit: - mutex_unlock(&ar->conf_mutex); +out: return ret; } +static int ath12k_mac_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, + struct ieee80211_vif *vif, struct ieee80211_sta *sta, + struct ieee80211_key_conf *key) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_hw_group *ag = ah->ag; + struct ath12k_key_conf *key_conf = NULL; + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta = NULL; + struct ath12k_sta *ahsta; + int ret = -ENOLINK; + u8 link_id; + + mutex_lock(&ah->conf_mutex); + + /* IGTK needs to be done in host software */ + if (key->keyidx == 4 || key->keyidx == 5) { + ret = 1; + goto out; + } + + if (test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ag->dev_flags)) { + ret = 1; + goto out; + } + + if (key->keyidx > WMI_MAX_KEY_INDEX) { + ret = -ENOSPC; + goto out; + } + + if (sta) { + ahsta = ath12k_sta_to_ahsta(sta); + if (sta->mlo) { + unsigned long links = sta->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + if (WARN_ON(!arvif || !arsta)) + continue; + mutex_lock(&arvif->ar->conf_mutex); + ret = ath12k_mac_set_key(arvif->ar, cmd, arvif, arsta, key); + mutex_unlock(&arvif->ar->conf_mutex); + if (ret) + break; + arsta->keys[key->keyidx] = key; + } + } else { + arsta = &ahsta->deflink; + arvif = arsta->arvif; + if (WARN_ON(!arvif)) + goto out; + mutex_lock(&arvif->ar->conf_mutex); + ret = ath12k_mac_set_key(arvif->ar, cmd, arvif, arsta, key); + mutex_unlock(&arvif->ar->conf_mutex); + arsta->keys[key->keyidx] = key; + } + } else { + if (key->link_id >= 0 && key->link_id < IEEE80211_MLD_MAX_NUM_LINKS) + arvif = ahvif->link[key->link_id]; + else + arvif = &ahvif->deflink; + + if (!arvif || !arvif->is_created) { + key_conf = kzalloc(sizeof(*key_conf), GFP_ATOMIC); + + if (!key_conf) { + ath12k_info(NULL, "failed to alloc cache key config\n"); + goto out; + } + + key_conf->cmd = cmd; + key_conf->sta = sta; + key_conf->key = key; + + list_add_tail(&key_conf->list, + &ahvif->cache[link_id].key_conf.list); + + ath12k_dbg(NULL, ATH12K_DBG_MAC, "set key param cached since vif not assign to radio\n"); + mutex_unlock(&ah->conf_mutex); + + return 0; + } + + if (!(arvif && arvif->ar)) { + ath12k_err(NULL, "Failed to set key.\n"); + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + + if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &arvif->ar->ab->dev_flags)) { + ath12k_dbg(arvif->ar->ab, ATH12K_DBG_MODE1_RECOVERY, + "cmd:%d called for crash flush set ab\n", cmd); + mutex_unlock(&ah->conf_mutex); + return 0; + } + + mutex_lock(&arvif->ar->conf_mutex); + ret = ath12k_mac_set_key(arvif->ar, cmd, arvif, arsta, key); + /* if sta is null, consider it has self peer */ + arvif->keys[key->keyidx] = key; + mutex_unlock(&arvif->ar->conf_mutex); + } +out: + mutex_unlock(&ah->conf_mutex); + return ret; +} + +static int +ath12k_mac_bitrate_mask_num_ht_rates(struct ath12k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +{ + int num_rates = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) + num_rates += hweight16(mask->control[band].ht_mcs[i]); + + return num_rates; +} + static int ath12k_mac_bitrate_mask_num_vht_rates(struct ath12k *ar, enum nl80211_band band, @@ -3057,8 +6117,50 @@ } static int -ath12k_mac_set_peer_vht_fixed_rate(struct ath12k_vif *arvif, - struct ieee80211_sta *sta, +ath12k_mac_bitrate_mask_num_he_rates(struct ath12k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +{ + int num_rates = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].he_mcs); i++) + num_rates += hweight16(mask->control[band].he_mcs[i]); + + return num_rates; +} + +static int +ath12k_mac_bitrate_mask_num_he_ul_rates(struct ath12k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +{ + int num_rates = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].he_ul_mcs); i++) + num_rates += hweight16(mask->control[band].he_ul_mcs[i]); + + return num_rates; +} + +static int +ath12k_mac_bitrate_mask_num_eht_rates(struct ath12k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +{ + int num_rates = 0; + int i; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].eht_mcs); i++) + num_rates += hweight16(mask->control[band].eht_mcs[i]); + + return num_rates; +} + +static int +ath12k_mac_set_peer_vht_fixed_rate(struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, const struct cfg80211_bitrate_mask *mask, enum nl80211_band band) { @@ -3066,6 +6168,11 @@ u8 vht_rate, nss; u32 rate_code; int ret, i; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); lockdep_assert_held(&ar->conf_mutex); @@ -3080,73 +6187,332 @@ if (!nss) { ath12k_warn(ar->ab, "No single VHT Fixed rate found to set for %pM", - sta->addr); + arsta->addr); + return -EINVAL; + } + + /* Avoid updating invalid nss as fixed rate*/ + rcu_read_lock(); + link_sta = rcu_dereference(sta->link[arsta->link_id]); + + if (!link_sta || nss > link_sta->rx_nss) { + rcu_read_unlock(); return -EINVAL; } + rcu_read_unlock(); ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "Setting Fixed VHT Rate for peer %pM. Device will not switch to any other selected rates", - sta->addr); + arsta->addr); rate_code = ATH12K_HW_RATE_CODE(vht_rate, nss - 1, WMI_RATE_PREAMBLE_VHT); - ret = ath12k_wmi_set_peer_param(ar, sta->addr, + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_PARAM_FIXED_RATE, rate_code); if (ret) ath12k_warn(ar->ab, "failed to update STA %pM Fixed Rate %d: %d\n", + arsta->addr, rate_code, ret); + + return ret; +} + +static int +ath12k_mac_set_peer_he_fixed_rate(struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, + const struct cfg80211_bitrate_mask *mask, + enum nl80211_band band) +{ + struct ath12k *ar = arvif->ar; + u8 he_rate, nss; + u32 rate_code; + int ret, i; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + lockdep_assert_held(&ar->conf_mutex); + + nss = 0; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].he_mcs); i++) { + if (hweight16(mask->control[band].he_mcs[i]) == 1) { + nss = i + 1; + he_rate = ffs(mask->control[band].he_mcs[i]) - 1; + } + } + + if (!nss) { + ath12k_warn(ar->ab, "No single HE Fixed rate found to set for %pM", + arsta->addr); + return -EINVAL; + } + + /* Avoid updating invalid nss as fixed rate*/ + rcu_read_lock(); + link_sta = rcu_dereference(sta->link[arsta->link_id]); + + if (!link_sta || nss > link_sta->rx_nss) { + rcu_read_unlock(); + return -EINVAL; + } + + rcu_read_unlock(); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Setting Fixed HE Rate for peer %pM. Device will not switch to any other selected rates", + arsta->addr); + + rate_code = ATH12K_HW_RATE_CODE(he_rate, nss - 1, + WMI_RATE_PREAMBLE_HE); + + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, + arvif->vdev_id, + WMI_PEER_PARAM_FIXED_RATE, + rate_code); + if (ret) + ath12k_warn(ar->ab, + "failed to update STA %pM Fixed Rate %d: %d\n", + arsta->addr, rate_code, ret); + + return ret; +} + +static int +ath12k_mac_set_peer_ht_fixed_rate(struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, + const struct cfg80211_bitrate_mask *mask, + enum nl80211_band band) +{ + struct ath12k *ar = arvif->ar; + u8 ht_rate, nss; + u32 rate_code; + int ret, i; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + lockdep_assert_held(&ar->conf_mutex); + + nss = 0; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) { + if (hweight16(mask->control[band].ht_mcs[i]) == 1) { + nss = i + 1; + ht_rate = ffs(mask->control[band].ht_mcs[i]) - 1; + } + } + + if (!nss) { + ath12k_warn(ar->ab, "No single HT Fixed rate found to set for %pM", + sta->addr); + return -EINVAL; + } + + /* Avoid updating invalid nss as fixed rate*/ + rcu_read_lock(); + link_sta = rcu_dereference(sta->link[arsta->link_id]); + + if (!link_sta || nss > link_sta->rx_nss) { + rcu_read_unlock(); + return -EINVAL; + } + + rcu_read_unlock(); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Setting Fixed HT Rate for peer %pM. Device will not switch to any other selected rates", + sta->addr); + + rate_code = ATH12K_HW_RATE_CODE(ht_rate, nss - 1, + WMI_RATE_PREAMBLE_HT); + ret = ath12k_wmi_set_peer_param(ar, sta->addr, + arvif->vdev_id, + WMI_PEER_PARAM_FIXED_RATE, + rate_code); + + if (ret) + ath12k_warn(ar->ab, + "failed to update STA %pM HT Fixed Rate %d: %d\n", sta->addr, rate_code, ret); return ret; } +static int +ath12k_mac_set_peer_eht_fixed_rate(struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, + const struct cfg80211_bitrate_mask *mask, + enum nl80211_band band) +{ + struct ath12k *ar = arvif->ar; + u8 eht_rate, nss; + u32 rate_code; + int ret, i; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + lockdep_assert_held(&ar->conf_mutex); + + nss = 0; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].eht_mcs); i++) { + if (hweight16(mask->control[band].eht_mcs[i]) == 1) { + nss = i + 1; + eht_rate = ffs(mask->control[band].eht_mcs[i]) - 1; + } + } + + if (!nss) { + ath12k_warn(ar->ab, "No single EHT Fixed rate found to set for %pM", + arsta->addr); + return -EINVAL; + } + + /* Avoid updating invalid nss as fixed rate*/ + rcu_read_lock(); + link_sta = rcu_dereference(sta->link[arsta->link_id]); + + if (!link_sta || nss > link_sta->rx_nss) { + rcu_read_unlock(); + return -EINVAL; + } + + rcu_read_unlock(); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Setting Fixed EHT Rate for peer %pM. Device will not switch to any other selected rates", + arsta->addr); + + rate_code = ATH12K_HW_RATE_CODE(eht_rate, nss - 1, + WMI_RATE_PREAMBLE_EHT); + + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, + arvif->vdev_id, + WMI_PEER_PARAM_FIXED_RATE, + rate_code); + if (ret) + ath12k_warn(ar->ab, + "failed to update STA %pM Fixed Rate %d: %d\n", + arsta->addr, rate_code, ret); + + return ret; +} + static int ath12k_station_assoc(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, bool reassoc) { - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_vif *vif = ahvif->vif; + struct ieee80211_sta *sta; + struct ieee80211_link_sta *link_sta; struct ath12k_wmi_peer_assoc_arg peer_arg; int ret; struct cfg80211_chan_def def; enum nl80211_band band; struct cfg80211_bitrate_mask *mask; - u8 num_vht_rates; + u8 num_vht_rates, num_he_rates, num_eht_rates, num_ht_rates; + u8 link_id = arvif->link_id; + bool ht_supp, vht_supp, has_he, has_eht; + struct ieee80211_sta_ht_cap ht_cap; + enum ieee80211_sta_rx_bandwidth bandwidth; + u16 he_6ghz_capa; + lockdep_assert_held(&ar->conf_mutex); - if (WARN_ON(ath12k_mac_vif_chan(vif, &def))) + if (!arvif) + return -EINVAL; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, link_id))) return -EPERM; + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + if (WARN_ON(rcu_access_pointer(sta->link[link_id]) == NULL)) + return -EINVAL; + band = def.chan->band; mask = &arvif->bitrate_mask; - ath12k_peer_assoc_prepare(ar, vif, sta, &peer_arg, reassoc); + ahsta = ath12k_sta_to_ahsta(sta); + arsta = ahsta->link[link_id]; + + if (WARN_ON(!arsta)) + return -EINVAL; + rcu_read_lock(); + + link_sta = ath12k_get_link_sta(arsta); + + if (!link_sta) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access link sta in station assoc\n"); + return -EINVAL; + } + + he_6ghz_capa = le16_to_cpu(link_sta->he_6ghz_capa.capa); + bandwidth = link_sta->bandwidth; + ht_cap = link_sta->ht_cap; + ht_supp = link_sta->ht_cap.ht_supported; + vht_supp = link_sta->vht_cap.vht_supported; + has_he = link_sta->he_cap.has_he; + has_eht = link_sta->eht_cap.has_eht; + bandwidth = link_sta->bandwidth; + + ath12k_peer_assoc_prepare(ar, arvif, arsta, &peer_arg, reassoc); + + rcu_read_unlock(); + peer_arg.is_assoc = true; ret = ath12k_wmi_send_peer_assoc_cmd(ar, &peer_arg); if (ret) { ath12k_warn(ar->ab, "failed to run peer assoc for STA %pM vdev %i: %d\n", - sta->addr, arvif->vdev_id, ret); + arsta->addr, arvif->vdev_id, ret); return ret; } if (!wait_for_completion_timeout(&ar->peer_assoc_done, 1 * HZ)) { ath12k_warn(ar->ab, "failed to get peer assoc conf event for %pM vdev %i\n", - sta->addr, arvif->vdev_id); + arsta->addr, arvif->vdev_id); return -ETIMEDOUT; } num_vht_rates = ath12k_mac_bitrate_mask_num_vht_rates(ar, band, mask); - - /* If single VHT rate is configured (by set_bitrate_mask()), - * peer_assoc will disable VHT. This is now enabled by a peer specific - * fixed param. + num_he_rates = ath12k_mac_bitrate_mask_num_he_rates(ar, band, mask); + num_eht_rates = ath12k_mac_bitrate_mask_num_eht_rates(ar, band, mask); + num_ht_rates = ath12k_mac_bitrate_mask_num_ht_rates(ar, band, mask); + + /* If single VHT/HE/EHT rate is configured (by set_bitrate_mask()), + * peer_assoc will disable VHT/HE/EHT. This is now enabled by a peer + * specific fixed param. * Note that all other rates and NSS will be disabled for this peer. */ - if (sta->deflink.vht_cap.vht_supported && num_vht_rates == 1) { - ret = ath12k_mac_set_peer_vht_fixed_rate(arvif, sta, mask, + if (vht_supp && num_vht_rates == 1) { + ret = ath12k_mac_set_peer_vht_fixed_rate(arvif, arsta, mask, + band); + if (ret) + return ret; + } else if (has_he && num_he_rates == 1) { + ret = ath12k_mac_set_peer_he_fixed_rate(arvif, arsta, mask, + band); + if (ret) + return ret; + } else if (has_eht && num_eht_rates == 1) { + ret = ath12k_mac_set_peer_eht_fixed_rate(arvif, arsta, mask, + band); + if (ret) + return ret; + } else if (ht_supp && num_ht_rates == 1) { + ret = ath12k_mac_set_peer_ht_fixed_rate(arvif, arsta, mask, band); if (ret) return ret; @@ -3158,14 +6524,24 @@ if (reassoc) return 0; - ret = ath12k_setup_peer_smps(ar, arvif, sta->addr, - &sta->deflink.ht_cap); + ret = ath12k_setup_peer_smps(ar, arvif, arsta->addr, + &ht_cap, + he_6ghz_capa); if (ret) { ath12k_warn(ar->ab, "failed to setup peer SMPS for vdev %d: %d\n", arvif->vdev_id, ret); return ret; } +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ret = ath12k_wmi_set_peer_intra_bss_cmd(ar, arvif->vdev_id, arsta->addr, 1); + if (ret) { + ath12k_warn(ar->ab, "failed to set vdev %i intra bss enable: %d\n", + arvif->vdev_id, ret); + return ret; + } +#endif + if (!sta->wme) { arvif->num_legacy_stations++; ret = ath12k_recalc_rtscts_prot(arvif); @@ -3174,26 +6550,62 @@ } if (sta->wme && sta->uapsd_queues) { - ret = ath12k_peer_assoc_qos_ap(ar, arvif, sta); + ret = ath12k_peer_assoc_qos_ap(ar, arvif, arsta); if (ret) { ath12k_warn(ar->ab, "failed to set qos params for STA %pM for vdev %i: %d\n", - sta->addr, arvif->vdev_id, ret); + arsta->addr, arvif->vdev_id, ret); return ret; } } + spin_lock_bh(&ar->data_lock); + + /* Set arsta bw and prev bw */ + arsta->bw = bandwidth; + arsta->bw_prev = bandwidth; + + arvif->num_stations++; + + ath12k_dbg(ar->ab, ATH12K_DBG_MODE1_RECOVERY, + "mac station %pM connected to vdev %u. num_stations=%u\n", + arsta->addr, arvif->vdev_id, arvif->num_stations); + + + spin_unlock_bh(&ar->data_lock); + return 0; } static int ath12k_station_disassoc(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta) + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) { - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; int ret; lockdep_assert_held(&ar->conf_mutex); + if (!arvif) + return -EINVAL; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + spin_lock_bh(&arvif->ar->data_lock); + + if (!arvif->num_stations) { + ath12k_warn(ar->ab, + "mac station disassoc for vdev %u which does not have any station connected\n", + arvif->vdev_id); + } else { + arvif->num_stations--; + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac station %pM disconnected from vdev %u. num_stations=%u\n", + arsta->addr, arvif->vdev_id, arvif->num_stations); + } + + spin_unlock_bh(&arvif->ar->data_lock); + if (!sta->wme) { arvif->num_legacy_stations--; ret = ath12k_recalc_rtscts_prot(arvif); @@ -3201,42 +6613,201 @@ return ret; } - ret = ath12k_clear_peer_keys(arvif, sta->addr); - if (ret) { + return 0; +} + +static int ath12k_station_authorize(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) +{ + struct ath12k_peer *peer; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + int ret = 0; + + lockdep_assert_held(&ar->conf_mutex); + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + spin_lock_bh(&ar->ab->base_lock); + + peer = ath12k_peer_find(ar->ab, arvif->vdev_id, arsta->addr); + if (peer) + peer->is_authorized = true; + + spin_unlock_bh(&ar->ab->base_lock); + + if (ahvif->vif->type == NL80211_IFTYPE_STATION && arvif->is_up) { + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, + arvif->vdev_id, + WMI_PEER_AUTHORIZE, + 1); + if (ret) + ath12k_warn(ar->ab, "Unable to authorize peer %pM vdev %d: %d\n", + arsta->addr, arvif->vdev_id, ret); + } + + return ret; +} + +static int ath12k_station_unauthorize(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) +{ + struct ath12k_peer *peer; + int ret = 0; + + lockdep_assert_held(&ar->conf_mutex); + spin_lock_bh(&ar->ab->base_lock); + + peer = ath12k_peer_find(ar->ab, arvif->vdev_id, arsta->addr); + if (peer) + peer->is_authorized = false; + + spin_unlock_bh(&ar->ab->base_lock); + + /* Driver should clear the peer keys during mac80211's ref ptr + * gets cleared in __sta_info_destroy_part2 (trans from + * IEEE80211_STA_AUTHORIZED to IEEE80211_STA_ASSOC) + */ + ret = ath12k_clear_peer_keys(arvif, arsta->addr); + if (ret) ath12k_warn(ar->ab, "failed to clear all peer keys for vdev %i: %d\n", arvif->vdev_id, ret); + return ret; } + +static int ath12k_mac_set_peer_ch_switch_data(struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, + enum wmi_phy_mode peer_phymode, + bool is_upgrade) +{ + struct ath12k *ar = arvif->ar; + struct ath12k_peer_ch_width_switch_data *peer_data; + struct wmi_chan_width_peer_arg *peer_arg; + struct ieee80211_link_sta *link_sta; + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct cfg80211_chan_def def; + u16 ru_punct_bitmap; + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + if (!ar->ab->chwidth_num_peer_caps) + return -EOPNOTSUPP; + + if (WARN_ON(ath12k_mac_vif_chan(vif, &def, arvif->link_id))) + return -EINVAL; + + peer_data = arvif->peer_ch_width_switch_data; + + if (!peer_data) { + peer_data = kzalloc(struct_size(peer_data, peer_arg, + arvif->num_stations), + GFP_KERNEL); + if (!peer_data) + return -ENOMEM; + + peer_data->count = 0; + arvif->peer_ch_width_switch_data = peer_data; + } + + /* before adding to the list, if its BW upgrade, phymode should be updated. + * We update now and check because if we fail to update the phymode, no + * point is setting the bandwidth */ + if (is_upgrade) { + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, + arvif->vdev_id, WMI_PEER_PHYMODE, + peer_phymode); + if (ret) { + ath12k_warn(ar->ab, "failed to update STA %pM peer phymode %d: %d\n", + arsta->addr, peer_phymode, ret); + + if (peer_data->count == 0) { + kfree(peer_data); + arvif->peer_ch_width_switch_data = NULL; + } + + return -EINVAL; + } + } + + peer_arg = &peer_data->peer_arg[peer_data->count++]; + + + ru_punct_bitmap = 0; + + rcu_read_lock(); + link_sta = ath12k_get_link_sta(arsta); + + if (link_sta) { + if (link_sta->he_cap.has_he && link_sta->eht_cap.has_eht) + ru_punct_bitmap = def.ru_punct_bitmap; + + if (ieee80211_vif_is_mesh(vif) && link_sta->ru_punct_bitmap) + ru_punct_bitmap = link_sta->ru_punct_bitmap; + } + + rcu_read_unlock(); + + spin_lock_bh(&ar->data_lock); + ether_addr_copy(peer_arg->mac_addr.addr, arsta->addr); + peer_arg->chan_width = arsta->bw; + peer_arg->puncture_20mhz_bitmap = ~ru_punct_bitmap; + peer_arg->peer_phymode = peer_phymode; + peer_arg->is_upgrade = is_upgrade; + spin_unlock_bh(&ar->data_lock); + + if (peer_data->count == 1) { + reinit_completion(&arvif->peer_ch_width_switch_send); + ieee80211_queue_work(ar->ah->hw, &arvif->peer_ch_width_switch_work); + } + + if (peer_data->count == arvif->num_stations) + complete(&arvif->peer_ch_width_switch_send); + return 0; } static void ath12k_sta_rc_update_wk(struct work_struct *wk) { struct ath12k *ar; - struct ath12k_vif *arvif; - struct ath12k_sta *arsta; + struct ath12k_link_vif *arvif; + struct ath12k_vif *ahvif; + struct ath12k_link_sta *arsta; struct ieee80211_sta *sta; struct cfg80211_chan_def def; enum nl80211_band band; const u8 *ht_mcs_mask; const u16 *vht_mcs_mask; + const u16 *he_mcs_mask; + const u16 *eht_mcs_mask; u32 changed, bw, nss, smps, bw_prev; - int err, num_vht_rates; + int err, num_vht_rates, num_he_rates, num_eht_rates, num_ht_rates; const struct cfg80211_bitrate_mask *mask; struct ath12k_wmi_peer_assoc_arg peer_arg; enum wmi_phy_mode peer_phymode; - - arsta = container_of(wk, struct ath12k_sta, update_wk); - sta = container_of((void *)arsta, struct ieee80211_sta, drv_priv); + struct ath12k_sta *ahsta; + struct ieee80211_link_sta *link_sta = NULL; + bool ht_supp, vht_supp, has_he, has_eht; + + arsta = container_of(wk, struct ath12k_link_sta, update_wk); + ahsta = arsta->ahsta; + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); arvif = arsta->arvif; + ahvif = arvif->ahvif; ar = arvif->ar; - if (WARN_ON(ath12k_mac_vif_chan(arvif->vif, &def))) + if (WARN_ON(ath12k_mac_vif_chan(ahvif->vif, &def, arsta->link_id))) return; band = def.chan->band; ht_mcs_mask = arvif->bitrate_mask.control[band].ht_mcs; vht_mcs_mask = arvif->bitrate_mask.control[band].vht_mcs; + he_mcs_mask = arvif->bitrate_mask.control[band].he_mcs; + eht_mcs_mask = arvif->bitrate_mask.control[band].eht_mcs; spin_lock_bh(&ar->data_lock); @@ -3253,13 +6824,20 @@ mutex_lock(&ar->conf_mutex); nss = max_t(u32, 1, nss); - nss = min(nss, max(ath12k_mac_max_ht_nss(ht_mcs_mask), - ath12k_mac_max_vht_nss(vht_mcs_mask))); + nss = min(nss, max(max(max(ath12k_mac_max_ht_nss(ht_mcs_mask), + ath12k_mac_max_vht_nss(vht_mcs_mask)), + ath12k_mac_max_he_nss(he_mcs_mask)), + ath12k_mac_max_eht_nss(eht_mcs_mask))); if (changed & IEEE80211_RC_BW_CHANGED) { - ath12k_peer_assoc_h_phymode(ar, arvif->vif, sta, &peer_arg); + ath12k_peer_assoc_h_phymode(ar, arvif, arsta, &peer_arg); peer_phymode = peer_arg.peer_phymode; + err = ath12k_mac_set_peer_ch_switch_data(arvif, arsta, peer_phymode, + bw > bw_prev ? true : false); + if (!err || err == -EINVAL) + goto err_rc_bw_changed; + if (bw > bw_prev) { /* Phymode shows maximum supported channel width, if we * upgrade bandwidth then due to sanity check of firmware, @@ -3267,13 +6845,13 @@ * WMI_PEER_CHWIDTH */ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac bandwidth upgrade for sta %pM new %d old %d\n", - sta->addr, bw, bw_prev); - err = ath12k_wmi_set_peer_param(ar, sta->addr, + arsta->addr, bw, bw_prev); + err = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_PHYMODE, peer_phymode); if (err) { ath12k_warn(ar->ab, "failed to update STA %pM to peer phymode %d: %d\n", - sta->addr, peer_phymode, err); + arsta->addr, peer_phymode, err); goto err_rc_bw_changed; } err = ath12k_wmi_set_peer_param(ar, sta->addr, @@ -3281,57 +6859,75 @@ bw); if (err) ath12k_warn(ar->ab, "failed to update STA %pM to peer bandwidth %d: %d\n", - sta->addr, bw, err); + arsta->addr, bw, err); } else { /* When we downgrade bandwidth this will conflict with phymode * and cause to trigger firmware crash. In this case we send * WMI_PEER_CHWIDTH followed by WMI_PEER_PHYMODE */ ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac bandwidth downgrade for sta %pM new %d old %d\n", - sta->addr, bw, bw_prev); - err = ath12k_wmi_set_peer_param(ar, sta->addr, + arsta->addr, bw, bw_prev); + err = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_CHWIDTH, bw); if (err) { ath12k_warn(ar->ab, "failed to update STA %pM peer to bandwidth %d: %d\n", - sta->addr, bw, err); + arsta->addr, bw, err); goto err_rc_bw_changed; } - err = ath12k_wmi_set_peer_param(ar, sta->addr, + err = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_PHYMODE, peer_phymode); if (err) ath12k_warn(ar->ab, "failed to update STA %pM to peer phymode %d: %d\n", - sta->addr, peer_phymode, err); + arsta->addr, peer_phymode, err); } } if (changed & IEEE80211_RC_NSS_CHANGED) { - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac update sta %pM nss %d\n", - sta->addr, nss); + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, "mac update sta %pM nss %d\n", + arsta->addr, nss); - err = ath12k_wmi_set_peer_param(ar, sta->addr, arvif->vdev_id, + err = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_NSS, nss); if (err) ath12k_warn(ar->ab, "failed to update STA %pM nss %d: %d\n", - sta->addr, nss, err); + arsta->addr, nss, err); } if (changed & IEEE80211_RC_SMPS_CHANGED) { - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac update sta %pM smps %d\n", - sta->addr, smps); + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, "mac update sta %pM smps %d\n", + arsta->addr, smps); - err = ath12k_wmi_set_peer_param(ar, sta->addr, arvif->vdev_id, + err = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_MIMO_PS_STATE, smps); if (err) ath12k_warn(ar->ab, "failed to update STA %pM smps %d: %d\n", - sta->addr, smps, err); + arsta->addr, smps, err); } if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) { + if (arsta->disable_fixed_rate) { + err = ath12k_wmi_set_peer_param(ar, arsta->addr, + arvif->vdev_id, + WMI_PEER_PARAM_FIXED_RATE, + WMI_FIXED_RATE_NONE); + if (err) + ath12k_warn(ar->ab, + "failed to disable peer fixed rate for STA %pM ret %d\n", + arsta->addr, err); + + arsta->disable_fixed_rate = false; + } mask = &arvif->bitrate_mask; + num_ht_rates = ath12k_mac_bitrate_mask_num_ht_rates(ar, band, + mask); num_vht_rates = ath12k_mac_bitrate_mask_num_vht_rates(ar, band, mask); + num_he_rates = ath12k_mac_bitrate_mask_num_he_rates(ar, band, + mask); + num_eht_rates = ath12k_mac_bitrate_mask_num_eht_rates(ar, band, + mask); /* Peer_assoc_prepare will reject vht rates in * bitrate_mask if its not available in range format and @@ -3344,39 +6940,110 @@ * TODO: Check RATEMASK_CMDID to support auto rates selection * across HT/VHT and for multiple VHT MCS support. */ - if (sta->deflink.vht_cap.vht_supported && num_vht_rates == 1) { - ath12k_mac_set_peer_vht_fixed_rate(arvif, sta, mask, + rcu_read_lock(); + link_sta = rcu_dereference(sta->link[arsta->link_id]); + + if (!link_sta) { + rcu_read_unlock(); + goto err_rc_bw_changed; + } + + ht_supp = link_sta->ht_cap.ht_supported; + vht_supp = link_sta->vht_cap.vht_supported; + has_he = link_sta->he_cap.has_he; + has_eht = link_sta->eht_cap.has_eht; + rcu_read_unlock(); + + if (vht_supp && num_vht_rates == 1) { + + ath12k_mac_set_peer_vht_fixed_rate(arvif, arsta, mask, + band); + } else if (has_he && num_he_rates == 1) { + ath12k_mac_set_peer_he_fixed_rate(arvif, arsta, mask, + band); + } else if (has_eht && num_eht_rates == 1) { + ath12k_mac_set_peer_eht_fixed_rate(arvif, arsta, mask, + band); + } else if (ht_supp && num_ht_rates == 1) { + ath12k_mac_set_peer_ht_fixed_rate(arvif, arsta, mask, band); } else { - /* If the peer is non-VHT or no fixed VHT rate - * is provided in the new bitrate mask we set the - * other rates using peer_assoc command. + /* If the peer is non-VHT/HE/EHT or no fixed VHT/HE/EHT + * rate is provided in the new bitrate mask we set the + * other rates using peer_assoc command. Also clear + * the peer fixed rate settings as it has higher proprity + * than peer assoc */ - ath12k_peer_assoc_prepare(ar, arvif->vif, sta, + + err = ath12k_wmi_set_peer_param(ar, arsta->addr, + arvif->vdev_id, + WMI_PEER_PARAM_FIXED_RATE, + WMI_FIXED_RATE_NONE); + if (err) + ath12k_warn(ar->ab, + "failed to disable peer fixed rate for STA %pM ret %d\n", + arsta->addr, err); + ath12k_peer_assoc_prepare(ar, arvif, arsta, &peer_arg, true); + peer_arg.is_assoc = false; err = ath12k_wmi_send_peer_assoc_cmd(ar, &peer_arg); if (err) ath12k_warn(ar->ab, "failed to run peer assoc for STA %pM vdev %i: %d\n", - sta->addr, arvif->vdev_id, err); + arsta->addr, arvif->vdev_id, err); if (!wait_for_completion_timeout(&ar->peer_assoc_done, 1 * HZ)) ath12k_warn(ar->ab, "failed to get peer assoc conf event for %pM vdev %i\n", - sta->addr, arvif->vdev_id); + arsta->addr, arvif->vdev_id); } } err_rc_bw_changed: mutex_unlock(&ar->conf_mutex); } -static int ath12k_mac_inc_num_stations(struct ath12k_vif *arvif, - struct ieee80211_sta *sta) +static void ath12k_sta_set_4addr_wk(struct work_struct *wk) { + struct ath12k *ar; + struct ath12k_link_vif *arvif; + struct ath12k_sta *ahsta; + struct ath12k_link_sta *arsta; + struct ieee80211_sta *sta; + int ret = 0; + u8 link_id; + + ahsta = container_of(wk, struct ath12k_sta, set_4addr_wk); + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + for_each_set_bit(link_id, &ahsta->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arsta = ahsta->link[link_id]; + arvif = arsta->arvif; + ar = arvif->ar; + + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, + "setting USE_4ADDR for peer %pM\n", arsta->addr); + + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, + arvif->vdev_id, + WMI_PEER_USE_4ADDR, 1); + if (ret) + ath12k_warn(ar->ab, "failed to set peer %pM 4addr capability: %d\n", + arsta->addr, ret); + } +} + +static int ath12k_mac_inc_num_stations(struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) +{ + struct ath12k_vif *ahvif = arvif->ahvif; struct ath12k *ar = arvif->ar; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); lockdep_assert_held(&ar->conf_mutex); - if (arvif->vdev_type == WMI_VDEV_TYPE_STA && !sta->tdls) + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA && !sta->tdls) return 0; if (ar->num_stations >= ar->max_num_stations) @@ -3384,95 +7051,226 @@ ar->num_stations++; + ath12k_dbg(ar->ab, ATH12K_DBG_MODE1_RECOVERY, + "num_stat incremented:%d\n", ar->num_stations); return 0; } -static void ath12k_mac_dec_num_stations(struct ath12k_vif *arvif, - struct ieee80211_sta *sta) +static void ath12k_mac_station_post_remove(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) { - struct ath12k *ar = arvif->ar; + struct ath12k_peer *peer; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + bool skip_peer_delete; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + ath12k_mac_dec_num_stations(arvif, arsta); + + mutex_lock(&ar->ab->tbl_mtx_lock); + spin_lock_bh(&ar->ab->base_lock); + skip_peer_delete = ar->ab->hw_params->vdev_start_delay && + vif->type == NL80211_IFTYPE_STATION; + + peer = ath12k_peer_find(ar->ab, arvif->vdev_id, arsta->addr); + if (skip_peer_delete && peer) { + peer->sta = NULL; + } else if (peer && peer->sta == sta) { + ath12k_warn(ar->ab, "Found peer entry %pM n vdev %i after it was supposedly removed\n", + arsta->addr, arvif->vdev_id); + ath12k_peer_rhash_delete(ar->ab, peer); + peer->sta = NULL; + list_del(&peer->list); +#ifdef CONFIG_ATH12K_SAWF + if (peer->sawf_ctx_peer.telemetry_peer_ctx) + ath12k_telemetry_peer_ctx_free(peer->sawf_ctx_peer.telemetry_peer_ctx); +#endif + kfree(peer); + ar->num_peers--; + } + spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ar->ab->tbl_mtx_lock); + + kfree(arsta->tx_stats); + arsta->tx_stats = NULL; + + kfree(arsta->rx_stats); + arsta->rx_stats = NULL; + ath12k_mac_ap_ps_recalc(ar); + ahsta->ahvif = NULL; +} + +static int ath12k_mac_station_remove(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) +{ + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + int ret; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + bool skip_peer_delete; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); lockdep_assert_held(&ar->conf_mutex); - if (arvif->vdev_type == WMI_VDEV_TYPE_STA && !sta->tdls) - return; + ath12k_dp_peer_cleanup(ar, arvif->vdev_id, arsta->addr); - ar->num_stations--; + skip_peer_delete = ar->ab->hw_params->vdev_start_delay && + vif->type == NL80211_IFTYPE_STATION; + + if (!skip_peer_delete) { + ret = ath12k_peer_delete(ar, arvif->vdev_id, arsta->addr); + if (ret) + ath12k_warn(ar->ab, "Failed to delete peer: %pM for VDEV: %d\n", + arsta->addr, arvif->vdev_id); + else + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, "Removed peer: %pM for VDEV: %d\n", + arsta->addr, arvif->vdev_id); + + ath12k_mac_station_post_remove(ar, arvif, arsta); + } + + return ret; } static int ath12k_mac_station_add(struct ath12k *ar, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta) + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta) { struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); - struct ath12k_sta *arsta = (struct ath12k_sta *)sta->drv_priv; - struct ath12k_wmi_peer_create_arg peer_param; + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; + struct ath12k_wmi_peer_create_arg peer_param = {0}; + struct ath12k_neighbor_peer *nrp, *tmp; + int nvdev_id; int ret; + bool del_nrp = false; lockdep_assert_held(&ar->conf_mutex); - ret = ath12k_mac_inc_num_stations(arvif, sta); + if (!arvif) + return -EINVAL; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + ath12k_mac_inc_num_stations(arvif, arsta); if (ret) { ath12k_warn(ab, "refusing to associate station: too many connected already (%d)\n", ar->max_num_stations); goto exit; } + if (ath12k_debugfs_is_extd_rx_stats_enabled(ar) && !arsta->rx_stats) { arsta->rx_stats = kzalloc(sizeof(*arsta->rx_stats), GFP_KERNEL); if (!arsta->rx_stats) { ret = -ENOMEM; goto dec_num_station; } + } peer_param.vdev_id = arvif->vdev_id; - peer_param.peer_addr = sta->addr; + peer_param.peer_addr = arsta->addr; peer_param.peer_type = WMI_PEER_TYPE_DEFAULT; + peer_param.ml_enabled = sta->mlo; + + /* + * When the neighbor peer associates with this AP and successfully + * becomes a station, check and clear the corresponding MAC from + * NRP list and failing to do so would inadvertently cause the + * STA association(peer creation for STA) to fail due to the NRP + * having created a peer already for the same MAC address + */ + if (!list_empty(&ab->neighbor_peers)) { + spin_lock_bh(&ab->base_lock); + list_for_each_entry_safe(nrp, tmp, &ab->neighbor_peers, list) { + if (ether_addr_equal(nrp->addr, arsta->addr)) { + nvdev_id = nrp->vdev_id; + list_del(&nrp->list); + kfree(nrp); + del_nrp = true; + break; + } + } + spin_unlock_bh(&ab->base_lock); + + if (del_nrp) { + ath12k_peer_delete(ar, nvdev_id, arsta->addr); + ath12k_debugfs_nrp_clean(ar, arsta->addr); + } + } ret = ath12k_peer_create(ar, arvif, sta, &peer_param); if (ret) { ath12k_warn(ab, "Failed to add peer: %pM for VDEV: %d\n", - sta->addr, arvif->vdev_id); + arsta->addr, arvif->vdev_id); + goto free_rx_stats; + } + + ath12k_dbg(ab, ATH12K_DBG_PEER, "Added peer: %pM for VDEV: %d num_stations : %d\n", + arsta->addr, arvif->vdev_id, ar->num_stations); + + if (ath12k_debugfs_is_extd_tx_stats_enabled(ar) && (!arsta->tx_stats)) { + arsta->tx_stats = kzalloc(sizeof(*arsta->tx_stats), + GFP_KERNEL); + if (!arsta->tx_stats) { + ret = -ENOMEM; goto free_peer; } - ath12k_dbg(ab, ATH12K_DBG_MAC, "Added peer: %pM for VDEV: %d\n", - sta->addr, arvif->vdev_id); + arsta->wbm_tx_stats = kzalloc(sizeof(*arsta->wbm_tx_stats), GFP_KERNEL); + if(!arsta->wbm_tx_stats) { + ret = -ENOMEM; + goto free_peer; + } + } if (ieee80211_vif_is_mesh(vif)) { - ret = ath12k_wmi_set_peer_param(ar, sta->addr, + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_USE_4ADDR, 1); if (ret) { ath12k_warn(ab, "failed to STA %pM 4addr capability: %d\n", - sta->addr, ret); - goto free_peer; + arsta->addr, ret); + goto free_tx_stats; } } - ret = ath12k_dp_peer_setup(ar, arvif->vdev_id, sta->addr); - if (ret) { - ath12k_warn(ab, "failed to setup dp for peer %pM on vdev %i (%d)\n", - sta->addr, arvif->vdev_id, ret); - goto free_peer; - } - if (ab->hw_params->vdev_start_delay && !arvif->is_started && - arvif->vdev_type != WMI_VDEV_TYPE_AP) { - ret = ath12k_start_vdev_delay(ar->hw, vif); + ahvif->vdev_type != WMI_VDEV_TYPE_AP) { + ret = ath12k_start_vdev_delay(ar, vif); if (ret) { ath12k_warn(ab, "failed to delay vdev start: %d\n", ret); - goto free_peer; + goto free_tx_stats; } } + INIT_WORK(&arsta->update_wk, ath12k_sta_rc_update_wk); + + ahsta->ahvif = ahvif; + ewma_avg_rssi_init(&arsta->avg_rssi); return 0; +free_tx_stats: + kfree(arsta->tx_stats); + arsta->tx_stats = NULL; + kfree(arsta->wbm_tx_stats); + arsta->wbm_tx_stats = NULL; free_peer: - ath12k_peer_delete(ar, arvif->vdev_id, sta->addr); + ath12k_peer_delete(ar, arvif->vdev_id, arsta->addr); +free_rx_stats: + kfree(arsta->rx_stats); + arsta->rx_stats = NULL; dec_num_station: - ath12k_mac_dec_num_stations(arvif, sta); + ath12k_mac_dec_num_stations(arvif, arsta); exit: return ret; } @@ -3495,6 +7293,9 @@ case IEEE80211_STA_RX_BW_160: bw = WMI_PEER_CHWIDTH_160MHZ; break; + case IEEE80211_STA_RX_BW_320: + bw = WMI_PEER_CHWIDTH_320MHZ; + break; default: ath12k_warn(ar->ab, "Invalid bandwidth %d in rc update for %pM\n", sta->deflink.bandwidth, sta->addr); @@ -3505,118 +7306,258 @@ return bw; } -static int ath12k_mac_op_sta_state(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - struct ieee80211_sta *sta, +static int ath12k_mac_assign_link_sta(struct ath12k_hw *ah, + struct ath12k_sta *ahsta, + struct ath12k_link_sta *arsta, + struct ath12k_vif *ahvif, + u8 link_id) +{ + struct ieee80211_link_sta *link_sta; + struct ieee80211_sta *sta; + + lockdep_assert_held(&ah->conf_mutex); + + if (!arsta || link_id > IEEE80211_MLD_MAX_NUM_LINKS) + return -EINVAL; + + if (WARN_ON(!ahvif->link[link_id])) + return -EINVAL; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + memset(arsta, 0, sizeof(*arsta)); + + rcu_read_lock(); + link_sta = rcu_dereference(sta->link[link_id]); + if (!link_sta) { + rcu_read_unlock(); + return -EINVAL; + } + ether_addr_copy(arsta->addr, link_sta->addr); + rcu_read_unlock(); + + /* logical index of the link sta in order of creation */ + arsta->link_idx = ahsta->num_peer++; + + ahsta->link[link_id] = arsta; + ahsta->links_map |= BIT(link_id); + arsta->arvif = ahvif->link[link_id]; + arsta->ahsta = ahsta; + arsta->link_id = link_id; + arsta->state = IEEE80211_STA_NONE; + + return 0; +} + +static int ath12k_mac_unassign_link_sta(struct ath12k_hw *ah, + struct ath12k_sta *ahsta, + u8 link_id) +{ + lockdep_assert_held(&ah->conf_mutex); + + if (link_id > IEEE80211_MLD_MAX_NUM_LINKS) + return -EINVAL; + + ahsta->link[link_id] = NULL; + ahsta->links_map &= ~BIT(link_id); + + return 0; +} + +static struct ath12k_link_sta * +ath12k_mac_alloc_assign_link_sta(struct ath12k_hw *ah, struct ath12k_sta *ahsta, + struct ath12k_vif *ahvif, u8 link_id) +{ + struct ath12k_link_sta *arsta; + + lockdep_assert_held(&ah->conf_mutex); + + if (link_id > IEEE80211_MLD_MAX_NUM_LINKS) + return NULL; + + if (ahsta->link[link_id]) { + WARN_ON(1); + return NULL; + } + + arsta = kzalloc(sizeof(*arsta), GFP_KERNEL); + if (!arsta) + return NULL; + + if (ath12k_mac_assign_link_sta(ah, ahsta, arsta, ahvif, link_id)) { + kfree(arsta); + return NULL; + } + + return arsta; +} + +static int ath12k_mac_free_unassign_link_sta(struct ath12k_hw *ah, + struct ath12k_sta *ahsta, + u8 link_id) +{ + struct ath12k_link_sta *arsta; + + lockdep_assert_held(&ah->conf_mutex); + + if (link_id > IEEE80211_MLD_MAX_NUM_LINKS) + return -EINVAL; + + arsta = ahsta->link[link_id]; + + WARN_ON(arsta == NULL); + + ath12k_mac_unassign_link_sta(ah, ahsta, link_id); + + if (arsta != &ahsta->deflink) + kfree(arsta); + + return 0; +} + +static void ath12k_mac_ml_station_remove(struct ath12k_vif *ahvif, + struct ath12k_sta *ahsta) +{ + struct ieee80211_sta *sta; + struct ath12k_hw *ah = ahvif->ah; + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + unsigned long links; + u8 link_id; + + lockdep_assert_held(&ah->conf_mutex); + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + ath12k_ml_link_peers_delete(ahvif, ahsta); + + /* validate link station removal and clear arsta links */ + links = sta->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + + if (!arvif || !arsta) + continue; + + ar = arvif->ar; + + mutex_lock(&ar->conf_mutex); + + ath12k_mac_station_post_remove(ar, arvif, arsta); + mutex_unlock(&ar->conf_mutex); + + ath12k_mac_free_unassign_link_sta(ah, ahsta, link_id); + } + ath12k_ml_peer_delete(ah, sta); +} + +static int ath12k_mac_handle_link_sta_state(struct ieee80211_hw *hw, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, enum ieee80211_sta_state old_state, enum ieee80211_sta_state new_state) { - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); - struct ath12k_sta *arsta = (struct ath12k_sta *)sta->drv_priv; - struct ath12k_peer *peer; + struct ath12k *ar = arvif->ar; + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ath12k_sta *ahsta = arsta->ahsta; + struct ieee80211_sta *sta; int ret = 0; - /* cancel must be done outside the mutex to avoid deadlock */ + if (!ar) { + ath12k_err(NULL, "unable to determine device to set sta state\n"); + return -EINVAL; + } + + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) + return -ESHUTDOWN; + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + if (sta->mlo && + (test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &ar->ab->dev_flags))) + /* Shouldn't allow MLO STA assoc until UMAC_RECOVERY bit is cleared */ + return 0; + + /* cancel must be done outside the ar mutex to avoid deadlock */ if ((old_state == IEEE80211_STA_NONE && - new_state == IEEE80211_STA_NOTEXIST)) + new_state == IEEE80211_STA_NOTEXIST)) { + /* ML sta needs separate handling */ + if (sta->mlo) + return 0; cancel_work_sync(&arsta->update_wk); + } mutex_lock(&ar->conf_mutex); if (old_state == IEEE80211_STA_NOTEXIST && new_state == IEEE80211_STA_NONE) { - memset(arsta, 0, sizeof(*arsta)); - arsta->arvif = arvif; - INIT_WORK(&arsta->update_wk, ath12k_sta_rc_update_wk); - - ret = ath12k_mac_station_add(ar, vif, sta); + ret = ath12k_mac_station_add(ar, arvif, arsta); if (ret) ath12k_warn(ar->ab, "Failed to add station: %pM for VDEV: %d\n", - sta->addr, arvif->vdev_id); + arsta->addr, arvif->vdev_id); + ahsta->low_ack_sent = false; } else if ((old_state == IEEE80211_STA_NONE && new_state == IEEE80211_STA_NOTEXIST)) { - ath12k_dp_peer_cleanup(ar, arvif->vdev_id, sta->addr); - ret = ath12k_peer_delete(ar, arvif->vdev_id, sta->addr); + ret = ath12k_mac_station_remove(ar, arvif, arsta); if (ret) - ath12k_warn(ar->ab, "Failed to delete peer: %pM for VDEV: %d\n", - sta->addr, arvif->vdev_id); - else - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "Removed peer: %pM for VDEV: %d\n", - sta->addr, arvif->vdev_id); + ath12k_warn(ar->ab, "Failed to remove station: %pM for VDEV: %d\n", + arsta->addr, arvif->vdev_id); + if (sta->valid_links) + ath12k_mac_free_unassign_link_sta(arvif->ahvif->ah, + arsta->ahsta, arsta->link_id); + } else if (old_state == IEEE80211_STA_AUTH && + new_state == IEEE80211_STA_ASSOC) { - ath12k_mac_dec_num_stations(arvif, sta); - spin_lock_bh(&ar->ab->base_lock); - peer = ath12k_peer_find(ar->ab, arvif->vdev_id, sta->addr); - if (peer && peer->sta == sta) { - ath12k_warn(ar->ab, "Found peer entry %pM n vdev %i after it was supposedly removed\n", - vif->addr, arvif->vdev_id); - peer->sta = NULL; - list_del(&peer->list); - kfree(peer); - ar->num_peers--; - } - spin_unlock_bh(&ar->ab->base_lock); + ret = ath12k_dp_peer_setup(ar, arvif, arsta); + if (ret) + ath12k_warn(ar->ab, "failed to setup dp for peer %pM on vdev %i (%d)\n", + arsta->addr, arvif->vdev_id, ret); - kfree(arsta->rx_stats); - arsta->rx_stats = NULL; - } else if (old_state == IEEE80211_STA_AUTH && - new_state == IEEE80211_STA_ASSOC && - (vif->type == NL80211_IFTYPE_AP || + ath12k_dp_peer_default_route_setup(ar, arvif, arsta); + + if (vif->type == NL80211_IFTYPE_AP || vif->type == NL80211_IFTYPE_MESH_POINT || - vif->type == NL80211_IFTYPE_ADHOC)) { - ret = ath12k_station_assoc(ar, vif, sta, false); + vif->type == NL80211_IFTYPE_ADHOC) { + ret = ath12k_station_assoc(ar, arvif, arsta, false); if (ret) ath12k_warn(ar->ab, "Failed to associate station: %pM\n", - sta->addr); - - spin_lock_bh(&ar->data_lock); - - arsta->bw = ath12k_mac_ieee80211_sta_bw_to_wmi(ar, sta); - arsta->bw_prev = sta->deflink.bandwidth; - - spin_unlock_bh(&ar->data_lock); + arsta->addr); + } } else if (old_state == IEEE80211_STA_ASSOC && new_state == IEEE80211_STA_AUTHORIZED) { - spin_lock_bh(&ar->ab->base_lock); - - peer = ath12k_peer_find(ar->ab, arvif->vdev_id, sta->addr); - if (peer) - peer->is_authorized = true; - - spin_unlock_bh(&ar->ab->base_lock); - - if (vif->type == NL80211_IFTYPE_STATION && arvif->is_up) { - ret = ath12k_wmi_set_peer_param(ar, sta->addr, - arvif->vdev_id, - WMI_PEER_AUTHORIZE, - 1); + ret = ath12k_station_authorize(ar, arvif, arsta); + } else if (old_state == IEEE80211_STA_AUTHORIZED && + new_state == IEEE80211_STA_ASSOC) { + ath12k_station_unauthorize(ar, arvif, arsta); + } else if (old_state == IEEE80211_STA_ASSOC && + new_state == IEEE80211_STA_AUTHORIZED) { + ret = ath12k_station_authorize(ar, arvif, arsta); if (ret) ath12k_warn(ar->ab, "Unable to authorize peer %pM vdev %d: %d\n", sta->addr, arvif->vdev_id, ret); - } } else if (old_state == IEEE80211_STA_AUTHORIZED && new_state == IEEE80211_STA_ASSOC) { - spin_lock_bh(&ar->ab->base_lock); - - peer = ath12k_peer_find(ar->ab, arvif->vdev_id, sta->addr); - if (peer) - peer->is_authorized = false; - - spin_unlock_bh(&ar->ab->base_lock); + ath12k_station_unauthorize(ar, arvif, arsta); } else if (old_state == IEEE80211_STA_ASSOC && new_state == IEEE80211_STA_AUTH && (vif->type == NL80211_IFTYPE_AP || vif->type == NL80211_IFTYPE_MESH_POINT || vif->type == NL80211_IFTYPE_ADHOC)) { - ret = ath12k_station_disassoc(ar, vif, sta); + ret = ath12k_station_disassoc(ar, arvif, arsta); if (ret) ath12k_warn(ar->ab, "Failed to disassociate station: %pM\n", - sta->addr); + arsta->addr); } + arsta->state = new_state; mutex_unlock(&ar->conf_mutex); + + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, "mac sta %pM old state %d new state :%d\n", + arsta->addr, old_state, new_state); + return ret; } @@ -3624,64 +7565,458 @@ struct ieee80211_vif *vif, struct ieee80211_sta *sta) { - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta; int ret; s16 txpwr; + /* TODO use link id from op after support is available */ + u8 link_id = 0; + + mutex_lock(&ah->conf_mutex); + + /* TODO get arvif based on link id */ + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + + if (!arvif) { + ath12k_err(NULL, "unable to determine device to set sta txpwr\n"); + ret = -EINVAL; + goto out; + } + + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + if (!ar) { + ath12k_err(NULL, "unable to determine device to set sta txpwr\n"); + ret = -EINVAL; + goto out; + } if (sta->deflink.txpwr.type == NL80211_TX_POWER_AUTOMATIC) { txpwr = 0; } else { txpwr = sta->deflink.txpwr.power; - if (!txpwr) - return -EINVAL; + if (!txpwr) { + ret = -EINVAL; + goto out; + } } - if (txpwr > ATH12K_TX_POWER_MAX_VAL || txpwr < ATH12K_TX_POWER_MIN_VAL) - return -EINVAL; + if (txpwr > ATH12K_TX_POWER_MAX_VAL || txpwr < ATH12K_TX_POWER_MIN_VAL) { + ret = -EINVAL; + goto out; + } mutex_lock(&ar->conf_mutex); - ret = ath12k_wmi_set_peer_param(ar, sta->addr, arvif->vdev_id, + ret = ath12k_wmi_set_peer_param(ar, arsta->addr, arvif->vdev_id, WMI_PEER_USE_FIXED_PWR, txpwr); if (ret) { ath12k_warn(ar->ab, "failed to set tx power for station ret: %d\n", ret); - goto out; + goto err; } +err: + mutex_unlock(&ar->conf_mutex); out: + mutex_unlock(&ah->conf_mutex); + return ret; +} + +static inline void ath12k_vdev_stop_notify(struct ath12k_link_vif *arvif) +{ + int ret = 0; + if (WARN_ON(!arvif || !arvif->ar)) + return; + + mutex_lock(&arvif->ar->conf_mutex); + reinit_completion(&arvif->ar->vdev_setup_done); + ret = ath12k_wmi_vdev_stop(arvif->ar, arvif->vdev_id); + + if (ret) { + ath12k_warn(arvif->ar->ab, + "failed to stop WMI vdev %i: %d\n", + arvif->vdev_id, ret); + goto exit; + } + + ret = ath12k_mac_vdev_setup_sync(arvif->ar); + if (ret) + ath12k_warn(arvif->ar->ab, + "failed to synchronize setup for vdev %i: %d\n", + arvif->vdev_id, ret); +exit: + if (!ret) + arvif->vdev_stop_notify_done = true; + + mutex_unlock(&arvif->ar->conf_mutex); +} + +int ath12k_mac_update_sta_state(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + enum ieee80211_sta_state old_state, + enum ieee80211_sta_state new_state) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + unsigned long links; + int ret = 0; + u8 link_id = 0, link; + + mutex_lock(&ah->conf_mutex); + + if (vif->valid_links && sta->valid_links) { + if (!sta->mlo) + WARN_ON(hweight16(sta->valid_links) != 1); + link_id = ffs(sta->valid_links) - 1; + } + + if ((old_state == IEEE80211_STA_NONE && + new_state == IEEE80211_STA_NOTEXIST)) { + cancel_work_sync(&ahsta->set_4addr_wk); + } + + if ((old_state == IEEE80211_STA_NOTEXIST && + new_state == IEEE80211_STA_NONE)) { + INIT_WORK(&ahsta->set_4addr_wk, ath12k_sta_set_4addr_wk); + if (!sta->mlo) { + ret = ath12k_mac_assign_link_sta(ah, ahsta, &ahsta->deflink, + ahvif, link_id); + if (ret) + goto exit; + } + } + + if (!sta->mlo) { + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + + if (WARN_ON(arvif == NULL || arsta == NULL)) { + ret = -EINVAL; + goto exit; + } + if (new_state == IEEE80211_STA_NOTEXIST && + old_state == IEEE80211_STA_NONE && + ahvif->vdev_type == WMI_VDEV_TYPE_STA) + ath12k_vdev_stop_notify(arvif); + + ret = ath12k_mac_handle_link_sta_state(hw, arvif, arsta, + old_state, new_state); + if (arvif->ar && + test_bit(ATH12K_FLAG_RECOVERY, &arvif->ar->ab->dev_flags)) + ret = 0; + + mutex_unlock(&ah->conf_mutex); + return ret; + } + + if (!sta->valid_links && !vif->valid_links) + WARN_ON(1); + + /* assign default link to the first link sta */ + if (!ahsta->links_map && hweight16(sta->valid_links) == 1 && + new_state == IEEE80211_STA_NONE && old_state == IEEE80211_STA_NOTEXIST) { + /* add case to prevent MLO assoc from happening when UMAC recovery + * happens + */ + for_each_set_bit(link, &ahvif->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link]; + + if (!arvif || !arvif->ar || + (test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, + &arvif->ar->ab->dev_flags))){ + ret = -EINVAL; + goto exit; + } + } + + ret = ath12k_ml_peer_create(ah, sta); + if (ret) { + ath12k_err(NULL, "unable to create ML peer for sta %pM", sta->addr); + mutex_unlock(&ah->conf_mutex); + return ret; + } + + ath12k_mac_assign_link_sta(ah, ahsta, &ahsta->deflink, + ahvif, link_id); + + ahsta->deflink.is_assoc_link = true; + ahsta->assoc_link_id = link_id; + ahsta->primary_link_id = link_id; + } + + if (new_state == IEEE80211_STA_NOTEXIST && old_state == IEEE80211_STA_NONE) { + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) { + links = sta->valid_links; + for_each_set_bit(link_id, &links, + IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + ath12k_vdev_stop_notify(arvif); + } + } + ath12k_mac_ml_station_remove(ahvif, ahsta); + goto exit; + } + + /* Reconfig links of arsta during recovery */ + if (ahsta->link[ahsta->assoc_link_id]->state != IEEE80211_STA_NONE && + old_state == IEEE80211_STA_NOTEXIST && + new_state == IEEE80211_STA_NONE) { + ahsta->num_peer = 0; + + for_each_set_bit(link_id, &ahsta->links_map, + IEEE80211_MLD_MAX_NUM_LINKS) { + arsta = ahsta->link[link_id]; + arvif = ahvif->link[link_id]; + + ath12k_mac_assign_link_sta(ah, ahsta, arsta, + ahvif, link_id); + } + ahsta->deflink.is_assoc_link = true; + + if (ahsta->use_4addr_set) + ieee80211_queue_work(ah->hw, &ahsta->set_4addr_wk); + } + + links = sta->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + + /* some assumptions went wrong! */ + if (WARN_ON(!arvif || !arsta)) + continue; + + ret = ath12k_mac_handle_link_sta_state(hw, arvif, arsta, + old_state, new_state); + if (ret) { + if (ret != -ESHUTDOWN) + ath12k_err(NULL, "unable to move link sta %d of sta %pM from state %d to %d", + link_id, arsta->addr, old_state, new_state); + + /* If FW recovery is ongoing, no need to move down sta states + * as FW will wake up with a clean slate. Hence we set the + * return value to 0, so that upper layers are not aware + * of the FW being in recovery state. + */ + if (old_state > new_state) { + if (!arvif->ar) + continue; + if (test_bit(ATH12K_FLAG_RECOVERY, &arvif->ar->ab->dev_flags)) + ret = 0; + } + + if (old_state == IEEE80211_STA_NOTEXIST && new_state == IEEE80211_STA_NONE && + !test_bit(ATH12K_FLAG_RECOVERY, &arvif->ar->ab->dev_flags)) { + + /* Unassign this link sta which couldnt be added to FW and + * cleanup the other link stations added earlier + */ + ath12k_mac_free_unassign_link_sta(ah, ahsta, link_id); + ath12k_mac_ml_station_remove(ahvif, ahsta); + } + + mutex_unlock(&ah->conf_mutex); + return ret; + } + } + + if (old_state == IEEE80211_STA_AUTH && new_state == IEEE80211_STA_ASSOC) { + /* TODO sync wait for ML peer map success, else clear ml peer info on + * all partners? TBD on testing + */ + } + +exit: + mutex_unlock(&ah->conf_mutex); + + return ret; +} + +static int ath12k_mac_op_sta_state(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + enum ieee80211_sta_state old_state, + enum ieee80211_sta_state new_state) +{ + return ath12k_mac_update_sta_state(hw, vif, sta, old_state, + new_state); +} + +static int ath12k_mac_op_change_sta_links(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + u16 old_links, u16 new_links) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + unsigned long valid_links; + u8 link_id; + int ret = 0; + + if (!sta->valid_links) + return -EINVAL; + + /* FW doesnt support removal of one of link stas. All sta would be removed during ML STA + * delete in sta_state(), hence link sta removal is not handled here. + */ + if (new_links < old_links) + return 0; + + mutex_lock(&ah->conf_mutex); + + if (ahsta->ml_peer_id == ATH12K_MLO_PEER_ID_INVALID) { + ath12k_err(NULL, "unable to add link for ml sta %pM", sta->addr); + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + + /* this op is expected only after initial sta insertion with default link */ + WARN_ON(ahsta->links_map == 0); + + valid_links = sta->valid_links; + if ((test_bit(ahvif->primary_link_id, &valid_links))) { + arvif = ahvif->link[ahvif->primary_link_id]; + if (arvif->ar->ab->hw_params->is_plink_preferable) { + ahsta->primary_link_id = ahvif->primary_link_id; + } else { + ahsta->primary_link_id = ahsta->assoc_link_id; + arvif = ahvif->link[ahsta->assoc_link_id]; + if (!arvif->ar->ab->hw_params->is_plink_preferable) { + valid_links = sta->valid_links; + for_each_set_bit(link_id, &valid_links, + IEEE80211_MLD_MAX_NUM_LINKS) { + if (link_id != ahsta->primary_link_id) { + ahsta->primary_link_id = link_id; + break; + } + } + } + } + } + + valid_links = new_links; + for_each_set_bit(link_id, &valid_links, IEEE80211_MLD_MAX_NUM_LINKS) { + if (ahsta->links_map & BIT(link_id)) + continue; + + arvif = ahvif->link[link_id]; + arsta = ath12k_mac_alloc_assign_link_sta(ah, ahsta, ahvif, link_id); + + if (!arvif || !arsta) { + ath12k_err(NULL, "Failed to alloc/assign link sta"); + continue; + } + + ar = arvif->ar; + if (!ar) { + ath12k_err(NULL, + "Failed to get ar to change sta links\n"); + continue; + } + + mutex_lock(&ar->conf_mutex); + ret = ath12k_mac_station_add(ar, arvif, arsta); + if (ret) { + mutex_unlock(&ar->conf_mutex); + ath12k_warn(ar->ab, "Failed to add station: %pM for VDEV: %d\n", + arsta->addr, arvif->vdev_id); + ath12k_mac_free_unassign_link_sta(ah, ahsta, link_id); + break; + } mutex_unlock(&ar->conf_mutex); + } + + mutex_unlock(&ah->conf_mutex); + return ret; } +static void ath12k_mac_op_sta_set_4addr(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, bool enabled) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + + if (enabled && !ahsta->use_4addr_set) { + ieee80211_queue_work(ah->hw, &ahsta->set_4addr_wk); + ahsta->use_4addr_set = true; + } +} + static void ath12k_mac_op_sta_rc_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, - u32 changed) + u32 changed /*, u8 link_id */) { - struct ath12k *ar = hw->priv; - struct ath12k_sta *arsta = (struct ath12k_sta *)sta->drv_priv; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + u8 link_id = 0; + struct ath12k *ar; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta; struct ath12k_peer *peer; u32 bw, smps; + struct ieee80211_link_sta *link_sta; + + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + + if (!arsta) { + ath12k_err(NULL, "unable to determine arsta\n"); + return; + } + + if (!arvif) { + ath12k_err(NULL, "unable to determine device for sta update\n"); + return; + } + + if (arvif->is_created) + ar = arvif->ar; + + if (!ar) { + ath12k_err(NULL, "unable to determine device for sta update\n"); + return; + } spin_lock_bh(&ar->ab->base_lock); - peer = ath12k_peer_find(ar->ab, arvif->vdev_id, sta->addr); + peer = ath12k_peer_find(ar->ab, arvif->vdev_id, arsta->addr); if (!peer) { spin_unlock_bh(&ar->ab->base_lock); ath12k_warn(ar->ab, "mac sta rc update failed to find peer %pM on vdev %i\n", - sta->addr, arvif->vdev_id); + arsta->addr, arvif->vdev_id); return; } spin_unlock_bh(&ar->ab->base_lock); + rcu_read_lock(); + link_sta = rcu_dereference(sta->link[link_id]); + + if (!link_sta) { + rcu_read_unlock(); + return; + } + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac sta rc update for %pM changed %08x bw %d nss %d smps %d\n", - sta->addr, changed, sta->deflink.bandwidth, sta->deflink.rx_nss, - sta->deflink.smps_mode); + arsta->addr, changed, link_sta->bandwidth, link_sta->rx_nss, + link_sta->smps_mode); spin_lock_bh(&ar->data_lock); @@ -3692,12 +8027,12 @@ } if (changed & IEEE80211_RC_NSS_CHANGED) - arsta->nss = sta->deflink.rx_nss; + arsta->nss = link_sta->rx_nss; if (changed & IEEE80211_RC_SMPS_CHANGED) { smps = WMI_PEER_SMPS_PS_NONE; - switch (sta->deflink.smps_mode) { + switch (link_sta->smps_mode) { case IEEE80211_SMPS_AUTOMATIC: case IEEE80211_SMPS_OFF: smps = WMI_PEER_SMPS_PS_NONE; @@ -3710,7 +8045,7 @@ break; default: ath12k_warn(ar->ab, "Invalid smps %d in sta rc update for %pM\n", - sta->deflink.smps_mode, sta->addr); + link_sta->smps_mode, arsta->addr); smps = WMI_PEER_SMPS_PS_NONE; break; } @@ -3721,18 +8056,19 @@ arsta->changed |= changed; spin_unlock_bh(&ar->data_lock); + rcu_read_unlock(); ieee80211_queue_work(hw, &arsta->update_wk); } -static int ath12k_conf_tx_uapsd(struct ath12k *ar, struct ieee80211_vif *vif, +static int ath12k_conf_tx_uapsd(struct ath12k *ar, struct ath12k_link_vif *arvif, u16 ac, bool enable) { - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct ath12k_vif *ahvif = arvif->ahvif; u32 value; int ret; - if (arvif->vdev_type != WMI_VDEV_TYPE_STA) + if (ahvif->vdev_type != WMI_VDEV_TYPE_STA) return 0; switch (ac) { @@ -3754,20 +8090,21 @@ break; } + /* TODO move link specific ? */ if (enable) - arvif->u.sta.uapsd |= value; + ahvif->u.sta.uapsd |= value; else - arvif->u.sta.uapsd &= ~value; + ahvif->u.sta.uapsd &= ~value; ret = ath12k_wmi_set_sta_ps_param(ar, arvif->vdev_id, WMI_STA_PS_PARAM_UAPSD, - arvif->u.sta.uapsd); + ahvif->u.sta.uapsd); if (ret) { ath12k_warn(ar->ab, "could not set uapsd params %d\n", ret); goto exit; } - if (arvif->u.sta.uapsd) + if (ahvif->u.sta.uapsd) value = WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD; else value = WMI_STA_PS_RX_WAKE_POLICY_WAKE; @@ -3782,17 +8119,17 @@ return ret; } -static int ath12k_mac_op_conf_tx(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, - unsigned int link_id, u16 ac, +int ath12k_mac_conf_tx(struct ath12k *ar, + struct ath12k_link_vif *arvif, u16 ac, const struct ieee80211_tx_queue_params *params) { - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = (void *)vif->drv_priv; struct wmi_wmm_params_arg *p = NULL; int ret; - mutex_lock(&ar->conf_mutex); + lockdep_assert_held(&ar->conf_mutex); + + if (!arvif->is_created) + return -EINVAL; switch (ac) { case IEEE80211_AC_VO: @@ -3826,13 +8163,56 @@ goto exit; } - ret = ath12k_conf_tx_uapsd(ar, vif, ac, params->uapsd); + ret = ath12k_conf_tx_uapsd(ar, arvif, ac, params->uapsd); if (ret) ath12k_warn(ar->ab, "failed to set sta uapsd: %d\n", ret); exit: + return ret; +} + +static int ath12k_mac_op_conf_tx(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + unsigned int link_id, u16 ac, + const struct ieee80211_tx_queue_params *params) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + int ret; + + if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS) + return -EINVAL; + + mutex_lock(&ah->conf_mutex); + arvif = ahvif->link[link_id]; + + /* If the tx config is received before a vdev is assigned to vif + * cache the info to be updated once vdev is created + */ + if (arvif == NULL || !arvif->is_created) { + ath12k_dbg(NULL, ATH12K_DBG_MAC, + "tx queue params cached since vif is not assigned to radio\n"); + ahvif->cache[link_id].tx_conf.changed = true; + ahvif->cache[link_id].tx_conf.ac = ac; + ahvif->cache[link_id].tx_conf.tx_queue_params = *params; + mutex_unlock(&ah->conf_mutex); + return 0; + } + mutex_unlock(&ah->conf_mutex); + + ar = arvif->ar; + if (!ar) { + ath12k_err(NULL, "Failed to config tx\n"); + return -EINVAL; + } + + mutex_lock(&ar->conf_mutex); + ret = ath12k_mac_conf_tx(ar, arvif, ac, params); mutex_unlock(&ar->conf_mutex); + return ret; } @@ -3902,10 +8282,11 @@ return ht_cap; } -static int ath12k_mac_set_txbf_conf(struct ath12k_vif *arvif) +static int ath12k_mac_set_txbf_conf(struct ath12k_link_vif *arvif) { u32 value = 0; struct ath12k *ar = arvif->ar; + struct ath12k_vif *ahvif = arvif->ahvif; int nsts; int sound_dim; u32 vht_cap = ar->pdev->cap.vht_cap; @@ -3933,7 +8314,7 @@ value |= WMI_VDEV_PARAM_TXBF_SU_TX_BFER; if ((vht_cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) && - arvif->vdev_type == WMI_VDEV_TYPE_AP) + ahvif->vdev_type == WMI_VDEV_TYPE_AP) value |= WMI_VDEV_PARAM_TXBF_MU_TX_BFER; } @@ -3941,7 +8322,7 @@ value |= WMI_VDEV_PARAM_TXBF_SU_TX_BFEE; if ((vht_cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) && - arvif->vdev_type == WMI_VDEV_TYPE_STA) + ahvif->vdev_type == WMI_VDEV_TYPE_STA) value |= WMI_VDEV_PARAM_TXBF_MU_TX_BFEE; } @@ -4002,12 +8383,11 @@ vht_cap.vht_supported = 1; vht_cap.cap = ar->pdev->cap.vht_cap; - ath12k_set_vht_txbf_cap(ar, &vht_cap.cap); + if (ar->pdev->cap.nss_ratio_enabled) + vht_cap.vht_mcs.tx_highest |= + cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); - /* TODO: Enable back VHT160 mode once association issues are fixed */ - /* Disabling VHT160 and VHT80+80 modes */ - vht_cap.cap &= ~IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK; - vht_cap.cap &= ~IEEE80211_VHT_CAP_SHORT_GI_160; + ath12k_set_vht_txbf_cap(ar, &vht_cap.cap); rxmcs_map = 0; txmcs_map = 0; @@ -4029,6 +8409,12 @@ vht_cap.vht_mcs.rx_mcs_map = cpu_to_le16(rxmcs_map); vht_cap.vht_mcs.tx_mcs_map = cpu_to_le16(txmcs_map); + /* Check if the HW supports 1:1 NSS ratio and reset + * EXT NSS BW Support field to 0 to indicate 1:1 ratio + */ + if (ar->pdev->cap.nss_ratio_info == WMI_NSS_RATIO_1_NSS) + vht_cap.cap &= ~IEEE80211_VHT_CAP_EXT_NSS_BW_MASK; + return vht_cap; } @@ -4051,6 +8437,8 @@ *ht_cap_info = ht_cap; band->ht_cap = ath12k_create_ht_cap(ar, ht_cap, rate_cap_rx_chainmask); + // band->vht_cap = ath12k_create_vht_cap(ar, rate_cap_tx_chainmask, + // rate_cap_rx_chainmask); } if (cap->supported_bands & WMI_HOST_WLAN_5G_CAP && @@ -4067,15 +8455,6 @@ } } -static int ath12k_check_chain_mask(struct ath12k *ar, u32 ant, bool is_tx_ant) -{ - /* TODO: Check the request chainmask against the supported - * chainmask table which is advertised in extented_service_ready event - */ - - return 0; -} - static void ath12k_gen_ppe_thresh(struct ath12k_wmi_ppe_threshold_arg *fw_ppet, u8 *he_ppet) { @@ -4105,6 +8484,48 @@ } } +static void ath12k_gen_eht_ppe_thresh(struct ath12k_ppe_threshold *fw_ppet, + struct ieee80211_sta_eht_cap *cap) +{ + int nss, ru; + u8 len = 0, bit = IEEE80211_EHT_PPE_THRES_INFO_HEADER_SIZE; + + len = hweight8(fw_ppet->ru_bit_mask); + len *= (1 + fw_ppet->numss_m1); + + len = (len * IEEE80211_EHT_PPE_THRES_INFO_PPET_SIZE) + + IEEE80211_EHT_PPE_THRES_INFO_HEADER_SIZE; + len = DIV_ROUND_UP(len, 8); + + cap->eht_ppe_thres[0] = FIELD_PREP(IEEE80211_EHT_PPE_THRES_NSS_MASK, + fw_ppet->numss_m1); + cap->eht_ppe_thres[0] |= FIELD_PREP((u8)IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_MASK, + fw_ppet->ru_bit_mask); + cap->eht_ppe_thres[1] |= (fw_ppet->ru_bit_mask >> + (8 - IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_POS)); + + for (nss = 0; nss <= fw_ppet->numss_m1; nss++) { + for (ru = 0; + ru < hweight8(IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_MASK); + ru++) { + u8 val; + int i; + + if ((fw_ppet->ru_bit_mask & BIT(ru)) == 0) + continue; + val = (fw_ppet->ppet16_ppet8_ru3_ru0[nss] >> (ru * 6)) & + 0x3f; + val = ((val >> 3) & 0x7) | ((val & 0x7) << 3); + for (i = (2 * IEEE80211_EHT_PPE_THRES_INFO_PPET_SIZE) - 1; + i >= 0; i--) { + cap->eht_ppe_thres[bit / 8] |= + ((val >> i) & 0x1) << ((bit % 8)); + bit++; + } + } + } +} + static void ath12k_mac_filter_he_cap_mesh(struct ieee80211_he_cap_elem *he_cap_elem) { @@ -4166,14 +8587,6 @@ IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; he_cap_elem->phy_cap_info[8] &= ~m; - - m = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | - IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | - IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | - IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | - IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | - IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; - he_cap_elem->phy_cap_info[9] &= ~m; } static __le16 ath12k_mac_setup_he_6ghz_cap(struct ath12k_pdev_cap *pcap, @@ -4206,30 +8619,62 @@ return cpu_to_le16(bcap->he_6ghz_capa); } -static int ath12k_mac_copy_he_cap(struct ath12k *ar, +static void ath12k_mac_set_hemcsmap(struct ath12k *ar, struct ath12k_pdev_cap *cap, - struct ieee80211_sband_iftype_data *data, - int band) + struct ieee80211_sta_he_cap *he_cap) { - int i, idx = 0; + u16 txmcs_map = 0, rxmcs_map = 0; + u16 txmcs_map_160 = 0, rxmcs_map_160 = 0; + u32 i = 0; + u8 maxtxnss_160 = ath12k_get_nss_160mhz(ar, ar->num_tx_chains); + u8 maxrxnss_160 = ath12k_get_nss_160mhz(ar, ar->num_rx_chains); - for (i = 0; i < NUM_NL80211_IFTYPES; i++) { - struct ieee80211_sta_he_cap *he_cap = &data[idx].he_cap; - struct ath12k_band_cap *band_cap = &cap->band[band]; - struct ieee80211_he_cap_elem *he_cap_elem = - &he_cap->he_cap_elem; + for (i = 0; i < 8; i++) { + if (i < ar->num_tx_chains && + (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) + txmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); + else + txmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); - switch (i) { - case NL80211_IFTYPE_STATION: - case NL80211_IFTYPE_AP: - case NL80211_IFTYPE_MESH_POINT: - break; + if (i < ar->num_rx_chains && + (ar->cfg_rx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) + rxmcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); + else + rxmcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); - default: - continue; + if (i < maxtxnss_160 && + (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) + txmcs_map_160 |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); + else + txmcs_map_160 |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); + + if (i < maxrxnss_160 && + (ar->cfg_tx_chainmask >> cap->tx_chain_mask_shift) & BIT(i)) + rxmcs_map_160 |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); + else + rxmcs_map_160 |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); } - data[idx].types_mask = BIT(i); + he_cap->he_mcs_nss_supp.rx_mcs_80 = + cpu_to_le16(rxmcs_map & 0xffff); + he_cap->he_mcs_nss_supp.tx_mcs_80 = + cpu_to_le16(txmcs_map & 0xffff); + he_cap->he_mcs_nss_supp.rx_mcs_160 = + cpu_to_le16(rxmcs_map_160 & 0xffff); + he_cap->he_mcs_nss_supp.tx_mcs_160 = + cpu_to_le16(txmcs_map_160 & 0xffff); + he_cap->he_mcs_nss_supp.rx_mcs_80p80 = + cpu_to_le16(rxmcs_map_160 & 0xffff); + he_cap->he_mcs_nss_supp.tx_mcs_80p80 = + cpu_to_le16(txmcs_map_160 & 0xffff); +} + +static void ath12k_mac_copy_he_cap(struct ath12k *ar, + struct ath12k_band_cap *band_cap, + struct ieee80211_sta_he_cap *he_cap, + struct ieee80211_he_cap_elem *he_cap_elem, + int iftype) +{ he_cap->has_he = true; memcpy(he_cap_elem->mac_cap_info, band_cap->he_cap_info, sizeof(he_cap_elem->mac_cap_info)); @@ -4238,27 +8683,25 @@ he_cap_elem->mac_cap_info[1] &= IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_MASK; - + he_cap_elem->phy_cap_info[0] &= + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; + he_cap_elem->phy_cap_info[0] &= + ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G; he_cap_elem->phy_cap_info[5] &= ~IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK; - he_cap_elem->phy_cap_info[5] &= - ~IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; he_cap_elem->phy_cap_info[5] |= ar->num_tx_chains - 1; - switch (i) { + switch (iftype) { case NL80211_IFTYPE_AP: + he_cap_elem->mac_cap_info[2] &= ~IEEE80211_HE_MAC_CAP2_BCAST_TWT; he_cap_elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_MASK; - he_cap_elem->phy_cap_info[9] |= - IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; break; case NL80211_IFTYPE_STATION: - he_cap_elem->mac_cap_info[0] &= - ~IEEE80211_HE_MAC_CAP0_TWT_RES; - he_cap_elem->mac_cap_info[0] |= - IEEE80211_HE_MAC_CAP0_TWT_REQ; - he_cap_elem->phy_cap_info[9] |= - IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; + he_cap_elem->mac_cap_info[0] &= ~IEEE80211_HE_MAC_CAP0_TWT_RES; + he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_REQ; break; case NL80211_IFTYPE_MESH_POINT: ath12k_mac_filter_he_cap_mesh(he_cap_elem); @@ -4278,30 +8721,192 @@ he_cap->he_mcs_nss_supp.tx_mcs_80p80 = cpu_to_le16((band_cap->he_mcs >> 16) & 0xffff); + ath12k_mac_set_hemcsmap(ar, &ar->pdev->cap, he_cap); memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); if (he_cap_elem->phy_cap_info[6] & IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) ath12k_gen_ppe_thresh(&band_cap->he_ppet, he_cap->ppe_thres); +} + +static void ath12k_gen_eht_mcs_nss(struct ath12k_band_cap *band_cap, + struct ieee80211_eht_mcs_nss_supp *mcs_nss, + const struct ieee80211_he_cap_elem *he_cap, + const struct ieee80211_eht_cap_elem_fixed *eht_cap) +{ + if ((he_cap->phy_cap_info[0] & + (IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)) == 0) + memcpy(&mcs_nss->only_20mhz, &band_cap->eht_mcs_20_only, + sizeof(struct ieee80211_eht_mcs_nss_supp_20mhz_only)); + + if (he_cap->phy_cap_info[0] & + (IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G)) + memcpy(&mcs_nss->bw._80, &band_cap->eht_mcs_80, + sizeof(struct ieee80211_eht_mcs_nss_supp_bw)); + + if (he_cap->phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) + memcpy(&mcs_nss->bw._160, &band_cap->eht_mcs_160, + sizeof(struct ieee80211_eht_mcs_nss_supp_bw)); + + if (eht_cap->phy_cap_info[0] & IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ) + memcpy(&mcs_nss->bw._320, &band_cap->eht_mcs_320, + sizeof(struct ieee80211_eht_mcs_nss_supp_bw)); +} + +static void +ath12k_mac_filter_eht_cap_mesh(struct ieee80211_eht_cap_elem_fixed *eht_cap_elem) +{ + u8 m; + + m = IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS; + eht_cap_elem->mac_cap_info[0] &= ~m; + + m = IEEE80211_EHT_MAC_CAP1_TWO_BQRS_SUPP | + IEEE80211_EHT_MAC_CAP1_EHT_LINK_ADAPTATION_SUPP; + eht_cap_elem->mac_cap_info[1] &= ~m; + + m = IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO; + eht_cap_elem->phy_cap_info[0] &= ~m; + + m = IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | + IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | + IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK | + IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK; + eht_cap_elem->phy_cap_info[3] &= ~m; + + m = IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO | + IEEE80211_EHT_PHY_CAP4_PSR_SR_SUPP | + IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | + IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI; + eht_cap_elem->phy_cap_info[4] &= ~m; + + m = IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | + IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP | + IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP | + IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK; + eht_cap_elem->phy_cap_info[5] &= ~m; + + m = IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK; + eht_cap_elem->phy_cap_info[6] &= ~m; + + m = IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | + IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | + IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | + IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | + IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ | + IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; + eht_cap_elem->phy_cap_info[7] &= ~m; + + m = IEEE80211_EHT_PHY_CAP8_20MHZ_ONLY_CAPS | + IEEE80211_EHT_PHY_CAP8_20MHZ_ONLY_TRIGGER_MUBF_FL_BW_FB_DLMUMIMO | + IEEE80211_EHT_PHY_CAP8_20MHZ_ONLY_MRU_SUPP; + eht_cap_elem->phy_cap_info[8] &= ~m; +} + +static void ath12k_mac_copy_eht_cap(struct ath12k *ar, + struct ath12k_band_cap *band_cap, + struct ieee80211_he_cap_elem *he_cap_elem, + struct ieee80211_sta_eht_cap *eht_cap, + struct ieee80211_eht_cap_elem_fixed *eht_cap_elem, + int iftype) +{ + memset(eht_cap, 0, sizeof(struct ieee80211_sta_eht_cap)); + + eht_cap->has_eht = true; + memcpy(eht_cap_elem->mac_cap_info, band_cap->eht_cap_mac_info, + sizeof(eht_cap_elem->mac_cap_info)); + memcpy(eht_cap_elem->phy_cap_info, band_cap->eht_cap_phy_info, + sizeof(eht_cap_elem->phy_cap_info)); + + switch (iftype) { + case NL80211_IFTYPE_AP: + eht_cap_elem->phy_cap_info[0] &= + ~IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ; + eht_cap_elem->phy_cap_info[4] &= + ~IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO; + break; + case NL80211_IFTYPE_STATION: + eht_cap_elem->phy_cap_info[7] &= + ~(IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | + IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | + IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ); + eht_cap_elem->phy_cap_info[7] &= + ~(IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | + IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ | + IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ); + break; + case NL80211_IFTYPE_MESH_POINT: + ath12k_mac_filter_eht_cap_mesh(eht_cap_elem); + break; + default: + break; + } + ath12k_gen_eht_mcs_nss(band_cap, &eht_cap->eht_mcs_nss_supp, + he_cap_elem, eht_cap_elem); + + if (eht_cap_elem->phy_cap_info[5] & + IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT) + ath12k_gen_eht_ppe_thresh(&band_cap->eht_ppet, eht_cap); +} + +static int ath12k_mac_copy_he_eht_cap(struct ath12k *ar, + struct ath12k_pdev_cap *cap, + struct ieee80211_sband_iftype_data *data, + int band) +{ + struct ath12k_band_cap *band_cap = &cap->band[band]; + struct ieee80211_sta_he_cap *he_cap; + struct ieee80211_he_cap_elem *he_cap_elem; + struct ieee80211_sta_eht_cap *eht_cap; + struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; + int i, idx = 0; + + for (i = 0; i < NUM_NL80211_IFTYPES; i++) { + he_cap = &data[idx].he_cap; + he_cap_elem = &he_cap->he_cap_elem; + eht_cap = &data[idx].eht_cap; + eht_cap_elem = &eht_cap->eht_cap_elem; + + switch (i) { + case NL80211_IFTYPE_STATION: + case NL80211_IFTYPE_AP: + case NL80211_IFTYPE_MESH_POINT: + break; + + default: + continue; + } + + data[idx].types_mask = BIT(i); + + ath12k_mac_copy_he_cap(ar, band_cap, he_cap, he_cap_elem, i); if (band == NL80211_BAND_6GHZ) { data[idx].he_6ghz_capa.capa = ath12k_mac_setup_he_6ghz_cap(cap, band_cap); } + ath12k_mac_copy_eht_cap(ar, band_cap, he_cap_elem, eht_cap, + eht_cap_elem, i); + idx++; } return idx; } -static void ath12k_mac_setup_he_cap(struct ath12k *ar, +static void ath12k_mac_setup_he_eht_cap(struct ath12k *ar, struct ath12k_pdev_cap *cap) { struct ieee80211_supported_band *band; int count; if (cap->supported_bands & WMI_HOST_WLAN_2G_CAP) { - count = ath12k_mac_copy_he_cap(ar, cap, + count = ath12k_mac_copy_he_eht_cap(ar, cap, ar->mac.iftype[NL80211_BAND_2GHZ], NL80211_BAND_2GHZ); band = &ar->mac.sbands[NL80211_BAND_2GHZ]; @@ -4309,8 +8914,9 @@ band->n_iftype_data = count; } - if (cap->supported_bands & WMI_HOST_WLAN_5G_CAP) { - count = ath12k_mac_copy_he_cap(ar, cap, + if (cap->supported_bands & WMI_HOST_WLAN_5G_CAP && + !ar->supports_6ghz) { + count = ath12k_mac_copy_he_eht_cap(ar, cap, ar->mac.iftype[NL80211_BAND_5GHZ], NL80211_BAND_5GHZ); band = &ar->mac.sbands[NL80211_BAND_5GHZ]; @@ -4320,13 +8926,14 @@ if (cap->supported_bands & WMI_HOST_WLAN_5G_CAP && ar->supports_6ghz) { - count = ath12k_mac_copy_he_cap(ar, cap, + count = ath12k_mac_copy_he_eht_cap(ar, cap, ar->mac.iftype[NL80211_BAND_6GHZ], NL80211_BAND_6GHZ); band = &ar->mac.sbands[NL80211_BAND_6GHZ]; band->iftype_data = ar->mac.iftype[NL80211_BAND_6GHZ]; band->n_iftype_data = count; } + } static int __ath12k_set_antenna(struct ath12k *ar, u32 tx_ant, u32 rx_ant) @@ -4335,15 +8942,23 @@ lockdep_assert_held(&ar->conf_mutex); - if (ath12k_check_chain_mask(ar, tx_ant, true)) - return -EINVAL; - - if (ath12k_check_chain_mask(ar, rx_ant, false)) - return -EINVAL; + /* Since we advertised the max cap of all radios combined during wiphy + * registration, ensure we dont set the antenna config higher than our + * limits + */ + tx_ant = min_t(u32, tx_ant, ar->pdev->cap.tx_chain_mask); + rx_ant = min_t(u32, rx_ant, ar->pdev->cap.rx_chain_mask); ar->cfg_tx_chainmask = tx_ant; ar->cfg_rx_chainmask = rx_ant; + ar->num_tx_chains = hweight32(tx_ant); + ar->num_rx_chains = hweight32(rx_ant); + + /* Reload HT/VHT/HE capability */ + ath12k_mac_setup_ht_vht_cap(ar, &ar->pdev->cap, NULL); + ath12k_mac_setup_he_eht_cap(ar, &ar->pdev->cap); + if (ar->state != ATH12K_STATE_ON && ar->state != ATH12K_STATE_RESTARTED) return 0; @@ -4351,79 +8966,104 @@ ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_TX_CHAIN_MASK, tx_ant, ar->pdev->pdev_id); if (ret) { - ath12k_warn(ar->ab, "failed to set tx-chainmask: %d, req 0x%x\n", + ath12k_err(ar->ab, "failed to set tx-chainmask: %d, req 0x%x\n", ret, tx_ant); return ret; } - ar->num_tx_chains = hweight32(tx_ant); - ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_RX_CHAIN_MASK, rx_ant, ar->pdev->pdev_id); if (ret) { - ath12k_warn(ar->ab, "failed to set rx-chainmask: %d, req 0x%x\n", + ath12k_err(ar->ab, "failed to set rx-chainmask: %d, req 0x%x\n", ret, rx_ant); return ret; } - ar->num_rx_chains = hweight32(rx_ant); + return 0; +} - /* Reload HT/VHT/HE capability */ - ath12k_mac_setup_ht_vht_cap(ar, &ar->pdev->cap, NULL); - ath12k_mac_setup_he_cap(ar, &ar->pdev->cap); +static void ath12k_mgmt_over_wmi_tx_drop(struct ath12k *ar, struct sk_buff *skb) +{ + int num_mgmt = 0; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); - return 0; + if (!(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) + num_mgmt = atomic_dec_if_positive(&ar->num_pending_mgmt_tx); + + ieee80211_free_txskb(ar->ah->hw, skb); + + if (num_mgmt < 0) + WARN_ON_ONCE(1); + + if (atomic_read(&ar->flush_request) && !num_mgmt) + wake_up(&ar->tx_empty_waitq); } -int ath12k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx) +static void ath12k_mac_tx_mgmt_free(struct ath12k *ar, int buf_id) { - struct sk_buff *msdu = skb; + struct sk_buff *msdu; struct ieee80211_tx_info *info; - struct ath12k *ar = ctx; - struct ath12k_base *ab = ar->ab; spin_lock_bh(&ar->txmgmt_idr_lock); - idr_remove(&ar->txmgmt_idr, buf_id); + msdu = idr_remove(&ar->txmgmt_idr, buf_id); spin_unlock_bh(&ar->txmgmt_idr_lock); - dma_unmap_single(ab->dev, ATH12K_SKB_CB(msdu)->paddr, msdu->len, + + if (!msdu) + return; + + dma_unmap_single(ar->ab->dev, ATH12K_SKB_CB(msdu)->paddr, msdu->len, DMA_TO_DEVICE); info = IEEE80211_SKB_CB(msdu); memset(&info->status, 0, sizeof(info->status)); - ieee80211_free_txskb(ar->hw, msdu); + ath12k_mgmt_over_wmi_tx_drop(ar, msdu); - return 0; } -static int ath12k_mac_vif_txmgmt_idr_remove(int buf_id, void *skb, void *ctx) +int ath12k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx) { - struct ieee80211_vif *vif = ctx; - struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); - struct sk_buff *msdu = skb; - struct ath12k *ar = skb_cb->ar; - struct ath12k_base *ab = ar->ab; + struct ath12k_mac_tx_mgmt_free_arg *arg = ctx; + struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB((struct sk_buff *)skb); + struct ath12k *ar = NULL; - if (skb_cb->vif == vif) { - spin_lock_bh(&ar->txmgmt_idr_lock); - idr_remove(&ar->txmgmt_idr, buf_id); - spin_unlock_bh(&ar->txmgmt_idr_lock); - dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, - DMA_TO_DEVICE); + if (u8_get_bits(arg->type, ATH12K_MAC_TX_MGMT_FREE_TYPE_PDEV)) + ar = arg->ar; + + /* If radio invalid, dont proceed */ + if (!ar) + goto out; + + /* If vif valid, then free the match vif alone */ + if (u8_get_bits(arg->type, ATH12K_MAC_TX_MGMT_FREE_TYPE_VIF)) { + if (skb_cb->vif != arg->vif) + goto out; } + /* If link_id valid, then free the match link_id alone */ + if (u8_get_bits(arg->type, ATH12K_MAC_TX_MGMT_FREE_TYPE_LINK)) { + if ((skb_cb->link_id != arg->link_id) && + (skb_cb->link_id != IEEE80211_MLD_MAX_NUM_LINKS)) + goto out; + } + + ath12k_mac_tx_mgmt_free(arg->ar, buf_id); + +out: return 0; } -static int ath12k_mac_mgmt_tx_wmi(struct ath12k *ar, struct ath12k_vif *arvif, +static int ath12k_mac_mgmt_tx_wmi(struct ath12k *ar, struct ath12k_link_vif *arvif, struct sk_buff *skb) { struct ath12k_base *ab = ar->ab; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; - struct ieee80211_tx_info *info; dma_addr_t paddr; + struct ath12k_skb_cb *skb_cb; int buf_id; int ret; + bool link_agnostic; spin_lock_bh(&ar->txmgmt_idr_lock); buf_id = idr_alloc(&ar->txmgmt_idr, skb, 0, @@ -4432,13 +9072,26 @@ if (buf_id < 0) return -ENOSPC; - info = IEEE80211_SKB_CB(skb); - if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)) { + skb_cb = ATH12K_SKB_CB(skb); + if (!(skb_cb->flags & ATH12K_SKB_HW_80211_ENCAP)) { if ((ieee80211_is_action(hdr->frame_control) || ieee80211_is_deauth(hdr->frame_control) || ieee80211_is_disassoc(hdr->frame_control)) && ieee80211_has_protected(hdr->frame_control)) { - skb_put(skb, IEEE80211_CCMP_MIC_LEN); + int mic_len; + + switch(skb_cb->cipher) { + case WLAN_CIPHER_SUITE_CCMP: + mic_len = IEEE80211_CCMP_MIC_LEN; + break; + case WLAN_CIPHER_SUITE_GCMP: + case WLAN_CIPHER_SUITE_GCMP_256: + mic_len = IEEE80211_GCMP_MIC_LEN; + break; + default: + mic_len = IEEE80211_CCMP_MIC_LEN; + } + skb_put(skb, mic_len); } } @@ -4449,9 +9102,16 @@ goto err_free_idr; } - ATH12K_SKB_CB(skb)->paddr = paddr; + skb_cb->paddr = paddr; - ret = ath12k_wmi_mgmt_send(ar, arvif->vdev_id, buf_id, skb); + if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN) { + ret = ath12k_wmi_offchan_mgmt_send(ar, arvif->vdev_id, buf_id, skb); + } else { + link_agnostic = ATH12K_SKB_CB(skb)->flags & ATH12K_SKB_MGMT_LINK_AGNOSTIC; + + ret = ath12k_wmi_mgmt_send(ar, arvif->vdev_id, buf_id, skb, + link_agnostic); + } if (ret) { ath12k_warn(ar->ab, "failed to send mgmt frame: %d\n", ret); goto err_unmap_buf; @@ -4460,7 +9120,7 @@ return 0; err_unmap_buf: - dma_unmap_single(ab->dev, ATH12K_SKB_CB(skb)->paddr, + dma_unmap_single(ab->dev, skb_cb->paddr, skb->len, DMA_TO_DEVICE); err_free_idr: spin_lock_bh(&ar->txmgmt_idr_lock); @@ -4475,50 +9135,262 @@ struct sk_buff *skb; while ((skb = skb_dequeue(&ar->wmi_mgmt_tx_queue)) != NULL) - ieee80211_free_txskb(ar->hw, skb); + ath12k_mgmt_over_wmi_tx_drop(ar, skb); +} + +static int ath12k_mac_mgmt_action_frame_fill_elem(struct ath12k_link_vif *arvif, + struct sk_buff *skb) +{ + struct ath12k *ar = arvif->ar; + struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + struct ieee80211_mgmt *mgmt; + struct ieee80211_bss_conf *link_conf; + struct stats_request_params req_param; + struct ath12k_fw_stats_pdev *pdev; + int ret, cur_tx_power, max_tx_power; + bool has_protected; + u8 category, *buf, iv_len; + u8 action_code, dialog_token; + + lockdep_assert_held(&ar->conf_mutex); + + /* make sure category field is present */ + if (skb->len < IEEE80211_MIN_ACTION_SIZE) { + skb_cb->flags &= ~ATH12K_SKB_MGMT_LINK_AGNOSTIC; + return -EINVAL; + } + + has_protected = ieee80211_has_protected(hdr->frame_control); + + /* SW_CRYPTO and hdr protected case (PMF), packet will be encrypted, + * we can't put in data in this case + */ + if (test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->ag->dev_flags) && + has_protected) { + skb_cb->flags &= ~ATH12K_SKB_MGMT_LINK_AGNOSTIC; + return -EOPNOTSUPP; + } + + mgmt = (struct ieee80211_mgmt *)hdr; + buf = (u8 *)&mgmt->u.action; + + /* FCTL_PROTECTED frame might have extra space added for HDR_LEN. Offset that + * many bytes if it is there + */ + if (has_protected) { + switch (skb_cb->cipher) { + /* Currently only for CCMP cipher suite, we asked for it via + * setting %IEEE80211_KEY_FLAG_GENERATE_IV_MGMT in key. Check + * ath12k_install_key() + */ + case WLAN_CIPHER_SUITE_CCMP: + iv_len = IEEE80211_CCMP_HDR_LEN; + break; + case WLAN_CIPHER_SUITE_TKIP: + case WLAN_CIPHER_SUITE_CCMP_256: + case WLAN_CIPHER_SUITE_GCMP: + case WLAN_CIPHER_SUITE_GCMP_256: + case WLAN_CIPHER_SUITE_AES_CMAC: + case WLAN_CIPHER_SUITE_BIP_GMAC_128: + case WLAN_CIPHER_SUITE_BIP_GMAC_256: + case WLAN_CIPHER_SUITE_BIP_CMAC_256: + iv_len = 0; + break; + default: + skb_cb->flags &= ~ATH12K_SKB_MGMT_LINK_AGNOSTIC; + return -EINVAL; + } + + buf = buf + iv_len; + } + + category = *buf++; + + switch (category) { + case WLAN_CATEGORY_RADIO_MEASUREMENT: + /* Packet Format: + * Action Code | Dialog Token | Variable Len (based on Action Code) + */ + action_code = *buf++; + dialog_token = *buf++; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access bss link conf\n"); + return -EINVAL; + } + + cur_tx_power = link_conf->txpower; + max_tx_power = min(link_conf->chanctx_conf->def.chan->max_reg_power, + (int)ar->max_tx_power / 2); + + rcu_read_unlock(); + + /* fetch current tx power from FW pdev stats */ + req_param.pdev_id = ar->pdev->pdev_id; + req_param.vdev_id = 0; + req_param.stats_id = WMI_REQUEST_PDEV_STAT; + + ret = ath12k_fw_stats_request(ar, &req_param); + if (ret) { + ath12k_warn(ar->ab, "failed to request fw pdev stats: %d\n", ret); + goto check_rm_action_frame; + } + + spin_lock_bh(&ar->data_lock); + pdev = list_first_entry_or_null(&ar->fw_stats.pdevs, + struct ath12k_fw_stats_pdev, + list); + if (!pdev) { + spin_unlock_bh(&ar->data_lock); + goto check_rm_action_frame; + } + + /* Tx power is set as 2 units per dBm in FW. */ + cur_tx_power = pdev->chan_tx_power / 2; + spin_unlock_bh(&ar->data_lock); + +check_rm_action_frame: + switch (action_code) { + case WLAN_ACTION_RADIO_MSR_LINK_MSR_REQ: + /* Variable Len Format: + * Transmit Power | Max Tx Power + * We fill both of these. + */ + *buf++ = cur_tx_power; + *buf = max_tx_power; + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "RRM: Link Measurement Req dialog_token=%u, cur_tx_power=%d, max_tx_power=%d\n", + dialog_token, cur_tx_power, max_tx_power); + skb_cb->flags &= ~ATH12K_SKB_MGMT_LINK_AGNOSTIC; + break; + case WLAN_ACTION_RADIO_MSR_LINK_MSR_REP: + /* Variable Len Format: + * TPC Report | Variable Fields + * + * TPC Report Format: + * Element ID | Len | Tx Power | Link Margin + * + * We fill Tx power in the TPC Report (2nd index) + */ + buf[2] = cur_tx_power; + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "RRM: Link Measurement Resp dialog_token=%u, cur_tx_power=%d\n", + dialog_token, cur_tx_power); + skb_cb->flags &= ~ATH12K_SKB_MGMT_LINK_AGNOSTIC; + break; + default: + return -EINVAL; + } + break; + default: + /* nothing to fill */ + skb_cb->flags &= ~ATH12K_SKB_MGMT_LINK_AGNOSTIC; + return 0; + } + + return 0; +} + +static int ath12k_mac_mgmt_frame_fill_elem(struct ath12k_link_vif *arvif, + struct sk_buff *skb) +{ + struct ath12k *ar = arvif->ar; + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + + lockdep_assert_held(&ar->conf_mutex); + + if (!ieee80211_is_action(hdr->frame_control)) + return 0; + + return ath12k_mac_mgmt_action_frame_fill_elem(arvif, skb); } static void ath12k_mgmt_over_wmi_tx_work(struct work_struct *work) { struct ath12k *ar = container_of(work, struct ath12k, wmi_mgmt_tx_work); struct ath12k_skb_cb *skb_cb; - struct ath12k_vif *arvif; + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif; struct sk_buff *skb; int ret; + struct ath12k_hw *ah = ar->ah; + mutex_lock(&ah->conf_mutex); while ((skb = skb_dequeue(&ar->wmi_mgmt_tx_queue)) != NULL) { skb_cb = ATH12K_SKB_CB(skb); if (!skb_cb->vif) { ath12k_warn(ar->ab, "no vif found for mgmt frame\n"); - ieee80211_free_txskb(ar->hw, skb); + ath12k_mgmt_over_wmi_tx_drop(ar, skb); continue; } - arvif = ath12k_vif_to_arvif(skb_cb->vif); + ahvif = ath12k_vif_to_ahvif(skb_cb->vif); + if (!(ahvif->links_map & BIT(skb_cb->link_id))) { + ath12k_warn(ar->ab, + "invalid linkid 0x%X in mgmt over wmi tx with linkmap %lu\n", + skb_cb->link_id, + ahvif->links_map); + ath12k_mgmt_over_wmi_tx_drop(ar, skb); + continue; + } + + arvif = ahvif->link[skb_cb->link_id]; + if (!arvif) { + ath12k_warn(ar->ab, "invalid arvif for mgmt tx - link %d\n", + skb_cb->link_id); + ath12k_mgmt_over_wmi_tx_drop(ar, skb); + continue; + } + + mutex_lock(&ar->conf_mutex); if (ar->allocated_vdev_map & (1LL << arvif->vdev_id) && arvif->is_started) { + /* Fill the data which is required to be filled in by the driver + * Example: Max Tx power in Link Measurement Request/Report + */ + ret = ath12k_mac_mgmt_frame_fill_elem(arvif, skb); + if (ret) { + /* If we couldn't fill the data due to any reason, let's not discard + * transmitting the packet. + * For ex: SW crypto and PMF case + */ + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Cant't fill in the required data for the mgmt packet. err=%d\n", + ret); + } + ret = ath12k_mac_mgmt_tx_wmi(ar, arvif, skb); if (ret) { ath12k_warn(ar->ab, "failed to tx mgmt frame, vdev_id %d :%d\n", arvif->vdev_id, ret); - ieee80211_free_txskb(ar->hw, skb); - } else { - atomic_inc(&ar->num_pending_mgmt_tx); + ath12k_mgmt_over_wmi_tx_drop(ar, skb); } } else { ath12k_warn(ar->ab, - "dropping mgmt frame for vdev %d, is_started %d\n", + "dropping mgmt frame for vdev %d, is_started %d link %d\n", arvif->vdev_id, - arvif->is_started); - ieee80211_free_txskb(ar->hw, skb); + arvif->is_started, + skb_cb->link_id); + ath12k_mgmt_over_wmi_tx_drop(ar, skb); } + mutex_unlock(&ar->conf_mutex); } + mutex_unlock(&ah->conf_mutex); } static int ath12k_mac_mgmt_tx(struct ath12k *ar, struct sk_buff *skb, bool is_prb_rsp) { struct sk_buff_head *q = &ar->wmi_mgmt_tx_queue; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) return -ESHUTDOWN; @@ -4530,66 +9402,484 @@ */ if (is_prb_rsp && atomic_read(&ar->num_pending_mgmt_tx) > ATH12K_PRB_RSP_DROP_THRESHOLD) { - ath12k_warn(ar->ab, + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "dropping probe response as pending queue is almost full\n"); - return -ENOSPC; + return -EBUSY; } - if (skb_queue_len(q) == ATH12K_TX_MGMT_NUM_PENDING_MAX) { + if (skb_queue_len_lockless(q) >= ATH12K_TX_MGMT_NUM_PENDING_MAX) { ath12k_warn(ar->ab, "mgmt tx queue is full\n"); return -ENOSPC; } skb_queue_tail(q, skb); - ieee80211_queue_work(ar->hw, &ar->wmi_mgmt_tx_work); + + /* For some of the off chan frames in DPP, host will not receive tx status, + * due to that skipping incrementing pending frames for off channel frames + * only to avoid the leak + */ + if (!(info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) + atomic_inc(&ar->num_pending_mgmt_tx); + + queue_work(ar->ab->workqueue_aux, &ar->wmi_mgmt_tx_work); return 0; } +static void ath12k_mlo_mcast_update_tx_link_address(struct ieee80211_vif *vif, + u8 link, struct sk_buff *skb, + u32 info_flags) +{ + struct ieee80211_bss_conf *bss_conf; + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + + if (info_flags & IEEE80211_TX_CTL_HW_80211_ENCAP) + return; + + bss_conf = rcu_dereference(vif->link_conf[link]); + if (bss_conf) + ether_addr_copy(hdr->addr2, bss_conf->addr); +} + +/* This function should be called only for a mgmt frame to a ML STA, + * hence, such sanity checks are skipped + */ +static bool ath12k_mac_is_mgmt_link_agnostic(struct sk_buff *skb) +{ + struct ieee80211_mgmt *mgmt; + mgmt = (struct ieee80211_mgmt *)skb->data; + + if (ieee80211_is_action(mgmt->frame_control)) + return true; + + /* TODO Extend as per requirement */ + return false; +} + +static u8 ath12k_mac_get_tx_link(struct ieee80211_sta *sta, struct ieee80211_vif *vif, + u8 link, struct sk_buff *skb, u32 info_flags) +{ + struct ath12k_sta *ahsta; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ieee80211_link_sta *link_sta; + struct ieee80211_bss_conf *bss_conf; + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + + /* Use the link id passed or the default vif link */ + if (!sta) { + if (link != IEEE80211_LINK_UNSPECIFIED) + return link; + + return ahvif->deflink.link_id; + } + + ahsta = ath12k_sta_to_ahsta(sta); + + /* Below translation ensures we pass proper A2 & A3 for non ML clients. + * Also it assumes for now support only for MLO AP in this path + */ + if (!sta->mlo) { + link = ahsta->deflink.link_id; + + if (info_flags & IEEE80211_TX_CTL_HW_80211_ENCAP) + return link; + + bss_conf = rcu_dereference(vif->link_conf[link]); + if (bss_conf) { + ether_addr_copy(hdr->addr2, bss_conf->addr); + if (!ieee80211_has_tods(hdr->frame_control) && + !ieee80211_has_fromds(hdr->frame_control)) + ether_addr_copy(hdr->addr3, bss_conf->addr); + } + return link; + } + + /* enqueue eth data frames on primary link */ + if (info_flags & IEEE80211_TX_CTL_HW_80211_ENCAP) + return ahsta->primary_link_id; + else if (ieee80211_is_data(hdr->frame_control)) + return ahsta->primary_link_id; + + /* 802.11 frame cases */ + if (link == IEEE80211_LINK_UNSPECIFIED) + link = ahsta->deflink.link_id; + + if (ieee80211_is_mgmt(hdr->frame_control)) { + /* For MLD STA post FW recovery, sending disassoc + * in other link apart from primary link results in + * disassoc packet getting dropped always, hence as + * a workaround until FW enables it post recovery + * this is needed to send disassoc always in primary + * link + */ + if (ieee80211_is_disassoc(hdr->frame_control)) + link = ahsta->deflink.link_id; + + /* Perform address conversion for ML STA Tx */ + bss_conf = rcu_dereference(vif->link_conf[link]); + link_sta = rcu_dereference(sta->link[link]); + if (bss_conf && link_sta) { + ether_addr_copy(hdr->addr1, link_sta->addr); + ether_addr_copy(hdr->addr2, bss_conf->addr); + if (vif->type == NL80211_IFTYPE_STATION && bss_conf->bssid) + ether_addr_copy(hdr->addr3, bss_conf->bssid); + else if (vif->type == NL80211_IFTYPE_AP) + ether_addr_copy(hdr->addr3, bss_conf->addr); + } else if (bss_conf) { + /* In certain cases where a ML sta associated and added subset of links + * on which the ML AP is active, but now sends some frame (ex. Probe request) + * on a different link which is active in our MLD but was not added during + * previous association, we can still honor the Tx to that ML STA via the + * requested link. + * The control would reach here in such case only when that link address + * is same as the MLD address or in worst case clients used MLD address at TA wrongly + * which would have helped identify the ML sta object and pass it here. + * If the link address of that STA is different from MLD address, then + * the sta object would be NULL and control wont reach here but return at the + * start of the function itself with !sta check. Also this would not need any + * translation at hdr->addr1 from MLD to link address since the RA is the + * MLD address (same as that link address ideally) already. + */ + ether_addr_copy(hdr->addr2, bss_conf->addr); + if (vif->type == NL80211_IFTYPE_STATION && bss_conf->bssid) + ether_addr_copy(hdr->addr3, bss_conf->bssid); + else if (vif->type == NL80211_IFTYPE_AP) + ether_addr_copy(hdr->addr3, bss_conf->addr); + + + ath12k_dbg(NULL, ATH12K_DBG_MAC, + "unable to determine link sta addr for translation - Frame control %x link %d sta links %x ahsta links %lu\n", + hdr->frame_control, link, sta->valid_links, + ahsta->links_map); + } else { + ath12k_err(NULL, "unable to determine Tx link for frame %x link %d\n vif links %x sta links %x ahvif links %lu ahsta links %lu", + hdr->frame_control, link, vif->valid_links, + sta->valid_links, ahvif->links_map, ahsta->links_map); + link = IEEE80211_MLD_MAX_NUM_LINKS; + } + + /* Check if this mgmt frame can be queued at MLD level, in that + * case the FW can decide on which link it needs to be finally + * transmitted based on the power state of that link. + * The link param returned by this function still needs + * to be valid to get queued to one of the valid link FW + */ + if (ath12k_mac_is_mgmt_link_agnostic(skb)) { + ATH12K_SKB_CB(skb)->flags |= ATH12K_SKB_MGMT_LINK_AGNOSTIC; + /* For action frames this will be reset if not needed + * later based on action category. + */ + } + } + + return link; +} + +bool ath12k_mac_tx_check_max_limit(struct ath12k *ar, struct sk_buff *skb) +{ + struct ath12k_base *ab = ar->ab; + + /* Allow EAPOL */ + if (skb->protocol == cpu_to_be16(ETH_P_PAE)) + return false; + + if (atomic_read(&ab->ag->num_dp_tx_pending) > ATH12K_DP_GROUP_TX_LIMIT) { + ab->soc_stats.tx_err.group_threshold_limit++; + return true; + } + + if (atomic_read(&ar->dp.num_tx_pending) > ATH12K_DP_PDEV_TX_LIMIT) { + ar->ab->soc_stats.tx_err.pdev_threshold_limit++; + return true; + } + + return false; +} + static void ath12k_mac_op_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, struct sk_buff *skb) { - struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); - struct ath12k *ar = hw->priv; - struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); - struct ieee80211_vif *vif = info->control.vif; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); - struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; - struct ieee80211_key_conf *key = info->control.hw_key; - u32 info_flags = info->flags; + struct ath12k_skb_cb *skb_cb; + struct ieee80211_tx_info *info; + struct ieee80211_vif *vif; + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif, *tmp_arvif; + struct ath12k *ar, *tmp_ar; + struct ath12k_hw *ah; + struct ieee80211_hdr *hdr; + struct ethhdr *eth = (struct ethhdr *)skb->data; + struct ieee80211_key_conf *key; + struct ath12k_mgmt_frame_stats *mgmt_stats; + struct ath12k_sta *ahsta = NULL; + struct sk_buff *msdu_copied; + struct ath12k_link_sta *arsta = NULL; + struct ieee80211_sta *sta = NULL; + struct ath12k_peer *peer; + u32 info_flags; bool is_prb_rsp; + bool is_mcast = false; + u16 frm_type = 0; + u8 link_id; + u16 mcbc_gsn; int ret; + u8 link; + + info = IEEE80211_SKB_CB(skb); + vif = info->control.vif; + ahvif = ath12k_vif_to_ahvif(vif); + link = u32_get_bits(info->control.flags, IEEE80211_TX_CTRL_MLO_LINK); + info_flags = info->flags; + if (control) + sta = control->sta; + + if (ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { + ieee80211_free_txskb(ah->hw, skb); + return; + } + + skb_cb = ATH12K_SKB_CB(skb); + key = info->control.hw_key; memset(skb_cb, 0, sizeof(*skb_cb)); skb_cb->vif = vif; + /* handle only for MLO case, use deflink for non MLO case */ + if (vif->valid_links) { + link = ath12k_mac_get_tx_link(sta, vif, link, skb, info_flags); + + if (link >= IEEE80211_MLD_MAX_NUM_LINKS) { + ieee80211_free_txskb(hw, skb); + return; + } + } else { + link = 0; + } + + arvif = ahvif->link[link]; + skb_cb->link_id = link; + + if (!arvif || !arvif->ar) { + ieee80211_free_txskb(hw, skb); + return; + } + + ar = arvif->ar; + + ah = ar->ah; + + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) { + ieee80211_free_txskb(ah->hw, skb); + return; + } + +#ifdef CONFIG_MAC80211_SFE_SUPPORT + if (skb->fast_xmit) { + ret = ath12k_mac_tx_check_max_limit(ar, skb); + if (ret) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "failed fast tx due to limit check pdev idx %d\n", + ar->pdev_idx); + ieee80211_free_txskb(hw, skb); + return; + } + + skb_cb->flags = ATH12K_SKB_HW_80211_ENCAP; + ret = ath12k_dp_tx_direct(arvif, skb); + if (unlikely(ret)) { + ath12k_dbg(arvif->ar->ab, ATH12K_DBG_MAC, + "failed to transmit frame %d\n", ret); + ieee80211_free_txskb(hw, skb); + } + return; + } +#endif + +#ifdef CONFIG_IP_FFN + if (skb->ffn_ff_done) { + ret = ath12k_mac_tx_check_max_limit(ar, skb); + if (ret) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "failed fast tx due to limit check pdev idx %d\n", + ar->pdev_idx); + ieee80211_free_txskb(hw, skb); + return; + } + + skb_cb->flags = ATH12K_SKB_HW_80211_ENCAP; + ret = ath12k_dp_tx_direct(arvif, skb); + if (unlikely(ret)) { + ath12k_dbg(arvif->ar->ab, ATH12K_DBG_MAC, + "failed to transmit frame %d\n", ret); + ieee80211_free_txskb(hw, skb); + } + return; + } +#endif + if (key) { skb_cb->cipher = key->cipher; skb_cb->flags |= ATH12K_SKB_CIPHER_SET; } + hdr = (struct ieee80211_hdr *)skb->data; + if (info_flags & IEEE80211_TX_CTL_HW_80211_ENCAP) { skb_cb->flags |= ATH12K_SKB_HW_80211_ENCAP; + is_mcast = is_multicast_ether_addr(eth->h_dest); } else if (ieee80211_is_mgmt(hdr->frame_control)) { + frm_type = FIELD_GET(IEEE80211_FCTL_STYPE, hdr->frame_control); is_prb_rsp = ieee80211_is_probe_resp(hdr->frame_control); + mgmt_stats = &ahvif->mgmt_stats; ret = ath12k_mac_mgmt_tx(ar, skb, is_prb_rsp); if (ret) { - ath12k_warn(ar->ab, "failed to queue management frame %d\n", - ret); - ieee80211_free_txskb(ar->hw, skb); + if (ret != -EBUSY) + ath12k_warn(ar->ab, "failed to queue mgmt stype 0x%x frame %d\n", frm_type, ret); + + ieee80211_free_txskb(ah->hw, skb); + spin_lock_bh(&ar->data_lock); + mgmt_stats->tx_fail_cnt[frm_type]++; + spin_unlock_bh(&ar->data_lock); + } else { + spin_lock_bh(&ar->data_lock); + mgmt_stats->tx_succ_cnt[frm_type]++; + spin_unlock_bh(&ar->data_lock); } return; - } + } else + is_mcast = is_multicast_ether_addr(hdr->addr1); - ret = ath12k_dp_tx(ar, arvif, skb); + if (sta) + ahsta = ath12k_sta_to_ahsta(control->sta); + + /* Must call mac80211 tx status handler, else when stats is disabled we + * free the skb from driver. Own tx packets on monitor will also be + * disabled. + */ + if ((info->flags & (IEEE80211_TX_CTL_REQ_TX_STATUS | + IEEE80211_TX_INTFL_NL80211_FRAME_TX)) || + info->status_data_idr || vif->type == NL80211_IFTYPE_MESH_POINT || + test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags)) + skb_cb->flags |= ATH12K_SKB_TX_STATUS; + + if (!vif->valid_links || !is_mcast || + test_bit(ATH12K_FLAG_RAW_MODE, &ar->ab->ag->dev_flags)) { + ret = ath12k_mac_tx_check_max_limit(ar, skb); if (ret) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "failed due to limit check pdev idx %d\n", + ar->pdev_idx); + ieee80211_free_txskb(hw, skb); + return; + } + + ret = ath12k_dp_tx(ar, arvif, ahsta, skb, false, 0); + if (unlikely(ret)) { + if (ret == -ENOMEM) + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "failed to transmit frame %d\n", ret); + else ath12k_warn(ar->ab, "failed to transmit frame %d\n", ret); - ieee80211_free_txskb(ar->hw, skb); + + ieee80211_free_txskb(ah->hw, skb); } + if (ath12k_debugfs_is_extd_tx_stats_enabled(ar) && ahsta) { + arsta = &ahsta->deflink; + atomic_inc(&arsta->drv_tx_pkts.pkts_in); + if (!ret) + atomic_inc(&arsta->drv_tx_pkts.pkts_out); } + } else { + spin_lock(&ahvif->mcbc_gsn_lock); + mcbc_gsn = ahvif->mcbc_gsn++; + if (ahvif->mcbc_gsn > 0xFFF) + ahvif->mcbc_gsn = 0; + spin_unlock(&ahvif->mcbc_gsn_lock); + + for_each_set_bit(link_id, &ahvif->links_map, + IEEE80211_MLD_MAX_NUM_LINKS) { + tmp_arvif = ahvif->link[link_id]; + if (!(tmp_arvif && tmp_arvif->is_up)) + continue; + + tmp_ar = tmp_arvif->ar; + + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &tmp_ar->ab->dev_flags))) + continue; -void ath12k_mac_drain_tx(struct ath12k *ar) + ret = ath12k_mac_tx_check_max_limit(tmp_ar, skb); + if (ret) { + ath12k_dbg(tmp_ar->ab, ATH12K_DBG_MAC, + "failed mcast tx due to limit check pdev idx %d\n", + tmp_ar->pdev_idx); + continue; + } + + msdu_copied = skb_copy(skb, GFP_ATOMIC); + if (!msdu_copied) { + ath12k_err(ar->ab, + "skb copy failure link_id 0x%X vdevid 0x%X\n", + link_id, tmp_arvif->vdev_id); + continue; + } + + ath12k_mlo_mcast_update_tx_link_address(vif, link_id, + msdu_copied, + info_flags); + /* upper layer would not have handled the keys so + * handle it here */ + skb_cb = ATH12K_SKB_CB(msdu_copied); + skb_cb->link_id = link_id; + + /* For open mode, skip peer find logic */ + if (ahvif->key_cipher == INVALID_CIPHER) + goto skip_peer_find; + + spin_lock_bh(&tmp_ar->ab->base_lock); + peer = ath12k_peer_find_by_addr(tmp_ar->ab, tmp_arvif->addr); + if (!peer) { + spin_unlock_bh(&tmp_ar->ab->base_lock); + ath12k_warn(tmp_ar->ab, + "failed to find peer for vdev_id 0x%X addr %pM link_map %lu\n", + tmp_arvif->vdev_id, tmp_arvif->addr, + ahvif->links_map); + tmp_ar->ab->soc_stats.tx_err.peers_not_present++; + ieee80211_free_txskb(ah->hw, msdu_copied); + continue; + } + + key = peer->keys[peer->mcast_keyidx]; + if (key) { + skb_cb->cipher = key->cipher; + skb_cb->flags |= ATH12K_SKB_CIPHER_SET; + + hdr = (struct ieee80211_hdr *)msdu_copied->data; + if (!ieee80211_has_protected(hdr->frame_control)) + hdr->frame_control |= + cpu_to_le16(IEEE80211_FCTL_PROTECTED); + } + spin_unlock_bh(&tmp_ar->ab->base_lock); +skip_peer_find: + ret = ath12k_dp_tx(tmp_ar, tmp_arvif, ahsta, + msdu_copied, true, mcbc_gsn); + + if (unlikely(ret)) { + if (ret == -ENOMEM) + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "failed to transmit frame %d\n", + ret); + else + ath12k_warn(ar->ab, "failed to transmit frame %d\n", + ret); + + ieee80211_free_txskb(ah->hw, msdu_copied); + } + } + ieee80211_free_txskb(ah->hw, skb); + } + +} + +void ath12k_mac_radio_drain_tx(struct ath12k *ar) { /* make sure rcu-protected mac80211 tx path itself is drained */ synchronize_net(); @@ -4600,40 +9890,227 @@ static int ath12k_mac_config_mon_status_default(struct ath12k *ar, bool enable) { - return -ENOTSUPP; - /* TODO: Need to support new monitor mode */ + struct htt_rx_ring_tlv_filter tlv_filter = {0}; + struct ath12k_base *ab = ar->ab; + int i, ret = 0; + u32 ring_id; + + if (enable) { + tlv_filter = ath12k_mac_mon_status_filter_default; + if (ath12k_debugfs_rx_filter(ar)) + tlv_filter.rx_filter = ath12k_debugfs_rx_filter(ar); + +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + if (g_bonded_interface_model && + test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ar->ab->dev_flags)) + tlv_filter.rx_filter |= (HTT_RX_FILTER_TLV_FLAGS_PPDU_START | + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | + HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO); +#endif /* CONFIG_ATH12K_BONDED_DS_SUPPORT */ + } -static void ath12k_mac_wait_reconfigure(struct ath12k_base *ab) + tlv_filter.offset_valid = false; + + for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { + ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; + ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, + ar->dp.mac_id + i, + HAL_RXDMA_MONITOR_DST, + DP_RXDMA_REFILL_RING_SIZE, + &tlv_filter); + } + + return ret; +} + +static int __ath12k_mac_mlo_ready(struct ath12k *ar) { - int recovery_start_count; + int ret; - if (!ab->is_reset) - return; + ret = ath12k_wmi_mlo_ready(ar); + if (ret) { + ath12k_err(ar->ab, "MLO ready failed for pdev_idx %d: %d\n", + ar->pdev_idx, ret); - recovery_start_count = atomic_inc_return(&ab->recovery_start_count); + return ret; + } - ath12k_dbg(ab, ATH12K_DBG_MAC, "recovery start count %d\n", recovery_start_count); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "MLO ready done for pdev_idx %d\n", + ar->pdev_idx); - if (recovery_start_count == ab->num_radios) { - complete(&ab->recovery_start); - ath12k_dbg(ab, ATH12K_DBG_MAC, "recovery started success\n"); + return 0; } - ath12k_dbg(ab, ATH12K_DBG_MAC, "waiting reconfigure...\n"); +int ath12k_mac_mlo_ready(struct ath12k_hw *ah) +{ + struct ath12k *ar; + int ret; + int i; + + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { + ret = __ath12k_mac_mlo_ready(ar); + if (ret) + goto out; - wait_for_completion_timeout(&ab->reconfigure_complete, - ATH12K_RECONFIGURE_TIMEOUT_HZ); + ar++; } -static int ath12k_mac_op_start(struct ieee80211_hw *hw) +out: + return ret; + +} + +static int __ath12k_mac_mlo_setup(struct ath12k *ar) +{ + struct ath12k_base *partner_ab, *ab = ar->ab; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_pdev *pdev; + struct wmi_mlo_setup_params mlo_params = { 0 }; + u8 num_link = 0, partner_link_id[ATH12K_GROUP_MAX_RADIO] = { 0 }; + int chip_idx, pdev_idx, ret; + unsigned long time_left; + + lockdep_assert_held(&ag->mutex_lock); + + reinit_completion(&ar->mlo_setup_done); + for (chip_idx = 0; chip_idx < ag->num_chip; chip_idx++) { + partner_ab = ag->ab[chip_idx]; + + for (pdev_idx = 0; pdev_idx < partner_ab->num_radios; pdev_idx++) { + pdev = &partner_ab->pdevs[pdev_idx]; + + /* Avoid the self link */ + if (ar == pdev->ar) + continue; + + partner_link_id[num_link] = pdev->hw_link_id; + num_link++; + + ath12k_dbg(ab, ATH12K_DBG_MAC, + "chip_id %d pdev_idx %d link id %d num_link %d\n", + chip_idx, pdev_idx, pdev->hw_link_id, num_link); + } + } + + mlo_params.group_id = ag->id; + mlo_params.partner_link_id = partner_link_id; + mlo_params.num_partner_links = num_link; + ar->mlo_setup_status = 0; + + ath12k_dbg(ab, ATH12K_DBG_MAC, "grp id %d num_link %d\n", ag->id, num_link); + + ret = ath12k_wmi_mlo_setup(ar, &mlo_params); + if (ret) { + ath12k_err(ab, "failed to setup MLO for pdev_idx %d: %d\n", + ar->pdev_idx, ret); + return ret; + } + + time_left = wait_for_completion_timeout(&ar->mlo_setup_done, + WMI_MLO_CMD_TIMEOUT_HZ); + if (!time_left || ar->mlo_setup_status) + return ar->mlo_setup_status ? : -ETIMEDOUT; + + ath12k_dbg(ab, ATH12K_DBG_MAC, "MLO setup done for pdev_idx %d\n", + ar->pdev_idx); + return 0; +} + +static int __ath12k_mac_mlo_teardown(struct ath12k *ar, bool umac_reset) +{ + struct ath12k_base *ab = ar->ab; + int ret; + + // If we receive teardown during ab is down, then exit silently + if (test_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags)) + return 0; + + ret = ath12k_wmi_mlo_teardown(ar, umac_reset); + if (ret) { + ath12k_err(ab, "failed to teardown MLO for pdev_idx %d: %d\n", + ar->pdev_idx, ret); + return ret; + } + + ath12k_dbg(ab, ATH12K_DBG_MAC, "MLO teardown for pdev_idx %d:%d\n", + ar->pdev_idx, umac_reset); + return 0; +} + +int ath12k_mac_mlo_setup(struct ath12k_hw *ah) +{ + struct ath12k *ar; + int ret, fbret; + int i; + + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { + ret = __ath12k_mac_mlo_setup(ar); + if (ret) { + ath12k_err(ar->ab, "failed to setup mlo %d\n", ret); + goto err_setup; + } + + ar++; + } + + return 0; + +err_setup: + ar = ah->radio; + for (i = i - 1; i >= 0; i--) { + fbret = __ath12k_mac_mlo_teardown(ar, false); + if (fbret) + ath12k_err(ar->ab, "MLO teardown failed %d in setup cleanup\n", + fbret); + + ar++; + } + return ret; +} + +static void ath12k_mac_drain_tx(struct ath12k_hw *ah, + struct ath12k *asserted_ar) +{ + struct ath12k *ar; + int i; + + if (asserted_ar) { + /* if asserted ar is NOT NULL, consider it + * is during Mode1 recovery and drain only + * asserted pdev + */ + ath12k_mac_radio_drain_tx(asserted_ar); + return; + } + + ar = ah->radio; + + for (i = 0; i < ah->num_radio; i++) { + ath12k_mac_radio_drain_tx(ar); + ar++; + } +} + +int ath12k_mac_radio_start(struct ath12k *ar) { - struct ath12k *ar = hw->priv; struct ath12k_base *ab = ar->ab; struct ath12k_pdev *pdev = ar->pdev; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_hw *ah = ar->ah; int ret; - ath12k_mac_drain_tx(ar); + /* reo init/drain tx only needed for recovered + * ab during Mode1 scenario + */ + if (ab->recovery_start) { + ath12k_mgmt_rx_reo_init_timer(ag); + ath12k_mac_drain_tx(ah, ar); + } + mutex_lock(&ar->conf_mutex); switch (ar->state) { @@ -4642,11 +10119,11 @@ break; case ATH12K_STATE_RESTARTING: ar->state = ATH12K_STATE_RESTARTED; - ath12k_mac_wait_reconfigure(ab); break; case ATH12K_STATE_RESTARTED: case ATH12K_STATE_WEDGED: case ATH12K_STATE_ON: + case ATH12K_STATE_TM: WARN_ON(1); ret = -EINVAL; goto err; @@ -4656,14 +10133,14 @@ 1, pdev->pdev_id); if (ret) { - ath12k_err(ar->ab, "failed to enable PMF QOS: (%d\n", ret); + ath12k_err(ab, "failed to enable PMF QOS: (%d)\n", ret); goto err; } ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_DYNAMIC_BW, 1, pdev->pdev_id); if (ret) { - ath12k_err(ar->ab, "failed to enable dynamic bw: %d\n", ret); + ath12k_err(ab, "failed to enable dynamic bw: %d\n", ret); goto err; } @@ -4683,6 +10160,7 @@ } ret = ath12k_dp_tx_htt_h2t_ppdu_stats_req(ar, + ab->stats_disable ? 0 : HTT_PPDU_STATS_TAG_DEFAULT); if (ret) { ath12k_err(ab, "failed to req ppdu stats: %d\n", ret); @@ -4693,20 +10171,70 @@ 1, pdev->pdev_id); if (ret) { - ath12k_err(ar->ab, "failed to enable MESH MCAST ENABLE: (%d\n", ret); + ath12k_err(ab, "failed to enable MESH MCAST ENABLE: (%d\n", ret); + goto err; + } + + ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_SET_CONG_CTRL_MAX_MSDUS, + ATH12K_NUM_POOL_TX_DESC, pdev->pdev_id); + + if (ret) { + ath12k_err(ab, "failed to set congestion control MAX MSDUS: %d\n", ret); + goto err; + } + /* Enable(1)/Disable(0) sub channel marking */ + if (pdev->cap.supported_bands & WMI_HOST_WLAN_5G_CAP) { + ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_SUB_CHANNEL_MARKING, + 1, pdev->pdev_id); + if (ret) { + ath12k_err(ab, "failed to enable SUB CHANNEL MARKING: %d\n", ret); + goto err; + } + } + +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + /* program CCE rule for eapol packets to be routed to wbm release ring */ + if (g_bonded_interface_model) { + ret = ath12k_dp_rx_pkt_type_filter(ar, ATH12K_PKT_TYPE_EAP, + ATH12K_ROUTE_EAP_METADATA); + if (ret) { + ath12k_err(ar->ab, "failed to configure EAP pkt route: %d\n", ret); goto err; } + ret = ath12k_dp_rx_pkt_type_filter(ar, ATH12K_PKT_TYPE_ARP_IPV4, + ATH12K_ROUTE_ARP_METADATA); + if (ret) { + ath12k_err(ar->ab, "failed to configure ARP pkt route: %d\n", ret); + goto err; + } + } +#endif + __ath12k_set_antenna(ar, ar->cfg_tx_chainmask, ar->cfg_rx_chainmask); /* TODO: Do we need to enable ANI? */ - ath12k_reg_update_chan_list(ar); + ret = ath12k_reg_update_chan_list(ar); + + /* the ar state alone can be turned off for non supported country without + * returning the error value. As we need to update the channel for the next ar + */ + if (ret) { + if (ret == -ENOTSUPP) + ret = 0; + goto err; + } ar->num_started_vdevs = 0; ar->num_created_vdevs = 0; ar->num_peers = 0; ar->allocated_vdev_map = 0; + ar->chan_tx_pwr = ATH12K_PDEV_TX_POWER_INVALID; + + spin_lock_bh(&ar->data_lock); + ar->awgn_intf_handling_in_prog = false; + spin_unlock_bh(&ar->data_lock); /* Configure monitor status ring with default rx_filter to get rx status * such as rssi, rx_duration. @@ -4719,7 +10247,7 @@ } if (ret == -ENOTSUPP) - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + ath12k_dbg(ab, ATH12K_DBG_MAC, "monitor status config is not yet supported"); /* Configure the hash seed for hash based reo dest ring selection */ @@ -4740,6 +10268,9 @@ rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], &ab->pdevs[ar->pdev_idx]); + /*ani is enabled by default*/ + ar->ani_enabled = true; + return 0; err: @@ -4749,18 +10280,80 @@ return ret; } -static void ath12k_mac_op_stop(struct ieee80211_hw *hw) +int ath12k_mac_mlo_teardown(struct ath12k_hw *ah) { - struct ath12k *ar = hw->priv; - struct htt_ppdu_stats_info *ppdu_stats, *tmp; + struct ath12k *ar; int ret; + int i; + + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { + ret = __ath12k_mac_mlo_teardown(ar, false); + if (ret) + goto out; + + ar++; + } - ath12k_mac_drain_tx(ar); +out: + return ret; +} + +int ath12k_mac_mlo_teardown_with_umac_reset(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_base *partner_ab; + struct ath12k *ar; + struct ath12k_pdev *pdev; + int i, j, ret = 0; + bool umac_reset; + + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + + for (j = 0; j < partner_ab->num_radios; j++) { + pdev = &partner_ab->pdevs[j]; + ar = pdev->ar; + + if (!ar) + continue; + + if (ab == partner_ab) { + /* No need to send teardown event for asserted + * chip, as anyway there will be no completion + * event from FW. + */ + ar->mlo_complete_event = true; + continue; + } + + /* Need to umac_reset as 1 for only one chip */ + umac_reset = false; + if (!ag->trigger_umac_reset) { + umac_reset = true; + ag->trigger_umac_reset = true; + } + + ret = __ath12k_mac_mlo_teardown(ar, umac_reset); + if (ret) + goto out; + } + } + +out: + return ret; +} + +static void ath12k_mac_radio_stop(struct ath12k *ar) +{ + struct ath12k_base *ab = ar->ab; + struct htt_ppdu_stats_info *ppdu_stats, *tmp; + int ret; mutex_lock(&ar->conf_mutex); ret = ath12k_mac_config_mon_status_default(ar, false); if (ret && (ret != -ENOTSUPP)) - ath12k_err(ar->ab, "failed to clear rx_filter for monitor status ring: (%d)\n", + ath12k_err(ab, "failed to clear rx_filter for monitor status ring: (%d)\n", ret); clear_bit(ATH12K_CAC_RUNNING, &ar->dev_flags); @@ -4768,6 +10361,7 @@ mutex_unlock(&ar->conf_mutex); cancel_delayed_work_sync(&ar->scan.timeout); + cancel_work_sync(&ar->scan.vdev_del_wk); cancel_work_sync(&ar->regd_update_work); spin_lock_bh(&ar->data_lock); @@ -4777,15 +10371,131 @@ } spin_unlock_bh(&ar->data_lock); - rcu_assign_pointer(ar->ab->pdevs_active[ar->pdev_idx], NULL); + if (!list_empty(&ab->neighbor_peers)) + ath12k_debugfs_nrp_cleanup_all(ar); + + rcu_assign_pointer(ab->pdevs_active[ar->pdev_idx], NULL); + if(!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->ag->dev_flags))) synchronize_rcu(); atomic_set(&ar->num_pending_mgmt_tx, 0); + atomic_set(&ar->flush_request, 0); + + spin_lock_bh(&ar->data_lock); + ar->awgn_intf_handling_in_prog = false; + spin_unlock_bh(&ar->data_lock); +} + +void ath12k_mgmt_rx_reo_init_timer(struct ath12k_hw_group *ag) +{ + struct ath12k_mgmt_rx_reo_context *reo_context = &ag->rx_reo; + + if (!(ag->mlo_mem.is_mlo_mem_avail && ag->mgmt_rx_reorder)) + return; + + if (reo_context->timer_init_done) + return; + + mod_timer(&reo_context->reo_list.ageout_timer, jiffies + + msecs_to_jiffies(ATH12K_MGMT_RX_REO_AGEOUT_TIMER_PERIOD_MS)); + + mod_timer(&reo_context->reo_list.global_mgmt_rx_inactivity_timer, jiffies + + ATH12K_MGMT_RX_REO_GLOBAL_MGMT_RX_INACTIVITY_TIMEOUT); + + reo_context->timer_init_done = true; +} + +static void ath12k_mgmt_rx_reo_deinit_timer(struct ath12k_hw_group *ag) +{ + struct ath12k_mgmt_rx_reo_context *reo_context = &ag->rx_reo; + + if (!(ag->mlo_mem.is_mlo_mem_avail && ag->mgmt_rx_reorder)) + return; + + if (!reo_context->timer_init_done) + return; + + del_timer_sync(&reo_context->reo_list.global_mgmt_rx_inactivity_timer); + del_timer_sync(&reo_context->reo_list.ageout_timer); + + reo_context->timer_init_done = false; +} + +static int ath12k_mac_op_start(struct ieee80211_hw *hw) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_base *ab; + struct ath12k_hw_group *ag = ah->ag; + int i; + int ret; + + ath12k_mgmt_rx_reo_init_timer(ag); + + ath12k_mac_drain_tx(ah, NULL); + + mutex_lock(&ah->conf_mutex); + ar = ah->radio; + ab = ar->ab; + + if (ath12k_ftm_mode) { + ath12k_err(ab, "fail to start mac operations in ftm mode\n"); + mutex_unlock(&ah->conf_mutex); + return -EWOULDBLOCK; + } + + /* TODO Maintain state for ah? */ + + for (i = 0; i < ah->num_radio; i++) { + ab = ar->ab; + ret = ath12k_mac_radio_start(ar); + if (ret) { + ath12k_err(ab, "fail to start mac operations in radio %d ret %d\n", + i, ret); + goto err; + } + ar++; + } + + mutex_unlock(&ah->conf_mutex); + return 0; + +err: + ar = ah->radio; + for (i = i - 1; i >= 0; i--) { + ath12k_mac_radio_stop(ar); + ar++; + } + mutex_unlock(&ah->conf_mutex); + return ret; +} + +static void ath12k_mac_op_stop(struct ieee80211_hw *hw) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_hw_group *ag = ah->ag; + int i; + + ath12k_mgmt_rx_reo_deinit_timer(ag); + + ath12k_mac_drain_tx(ah, NULL); + + mutex_lock(&ah->conf_mutex); + ar = ah->radio; + + /* TODO Maintain state for ah? */ + for (i = ah->num_radio - 1, ar = ar + (ah->num_radio - 1); i >= 0; i--) { + ath12k_mac_radio_stop(ar); + ar--; + } + + mutex_unlock(&ah->conf_mutex); } static u8 -ath12k_mac_get_vdev_stats_id(struct ath12k_vif *arvif) +ath12k_mac_get_vdev_stats_id(struct ath12k_link_vif *arvif) { struct ath12k_base *ab = arvif->ar->ab; u8 vdev_stats_id = 0; @@ -4793,7 +10503,7 @@ do { if (ab->free_vdev_stats_id_map & (1LL << vdev_stats_id)) { vdev_stats_id++; - if (vdev_stats_id <= ATH12K_INVAL_VDEV_STATS_ID) { + if (vdev_stats_id >= ATH12K_INVAL_VDEV_STATS_ID) { vdev_stats_id = ATH12K_INVAL_VDEV_STATS_ID; break; } @@ -4807,22 +10517,107 @@ return vdev_stats_id; } -static void ath12k_mac_setup_vdev_create_arg(struct ath12k_vif *arvif, +static int ath12k_mac_setup_vdev_args_mbssid(struct ath12k_link_vif *arvif, + u32 *flags, u32 *tx_vdev_id) +{ + struct ath12k *ar = arvif->ar; + struct ath12k_link_vif *tx_arvif; + struct ath12k_vif *tx_ahvif; + struct ieee80211_vif *tx_vif; + struct ieee80211_bss_conf *link_conf; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access bss link conf in mbssid params setup\n"); + return -EINVAL; + } + + *tx_vdev_id = 0; + tx_vif = link_conf->mbssid_tx_vif; + if (!tx_vif) { + /* Since a 6GHz AP is MBSS capable by default, FW expects + * Tx vdev flag to be set even in case of single bss case + * WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP is to be used for non 6GHz + * cases + */ + if (ar->supports_6ghz && arvif->ahvif->vif->type == NL80211_IFTYPE_AP) + *flags = WMI_HOST_VDEV_FLAGS_TRANSMIT_AP; + else + *flags = WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP; + rcu_read_unlock(); + return 0; + } + + tx_ahvif = ath12k_vif_to_ahvif(tx_vif); + if (!tx_ahvif) { + rcu_read_unlock(); + return -EINVAL; + } + lockdep_assert_held(&tx_ahvif->ah->conf_mutex); + tx_arvif = tx_ahvif->link[link_conf->mbssid_tx_vif_linkid]; + if (!tx_arvif) { + rcu_read_unlock(); + return -EINVAL; + } + lockdep_assert_held(&tx_arvif->ar->conf_mutex); + + if (link_conf->nontransmitted) { + if (ar->ah->hw->wiphy != ieee80211_vif_to_wdev(tx_vif)->wiphy) { + rcu_read_unlock(); + return -EINVAL; + } + + *flags = WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP; + *tx_vdev_id = tx_arvif->vdev_id; + } else if (tx_arvif == arvif) { + *flags = WMI_HOST_VDEV_FLAGS_TRANSMIT_AP; + } else { + rcu_read_unlock(); + return -EINVAL; + } + arvif->tx_vdev_id = *tx_vdev_id; + + if (link_conf->ema_ap) + *flags |= WMI_HOST_VDEV_FLAGS_EMA_MODE; + + rcu_read_unlock(); + return 0; +} + +static int ath12k_mac_setup_vdev_create_args(struct ath12k_link_vif *arvif, struct ath12k_wmi_vdev_create_arg *arg) { + struct ath12k_vif *ahvif = arvif->ahvif; struct ath12k *ar = arvif->ar; struct ath12k_pdev *pdev = ar->pdev; + int ret; arg->if_id = arvif->vdev_id; - arg->type = arvif->vdev_type; - arg->subtype = arvif->vdev_subtype; + arg->type = ahvif->vdev_type; + arg->subtype = ahvif->vdev_subtype; arg->pdev_id = pdev->pdev_id; + arg->mbssid_flags = 0; + arg->mbssid_tx_vdev_id = 0; + + if (!test_bit(WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT, + ar->ab->wmi_ab.svc_map)) { + ret = ath12k_mac_setup_vdev_args_mbssid(arvif, + &arg->mbssid_flags, + &arg->mbssid_tx_vdev_id); + if (ret) + return ret; + } if (pdev->cap.supported_bands & WMI_HOST_WLAN_2G_CAP) { arg->chains[NL80211_BAND_2GHZ].tx = ar->num_tx_chains; arg->chains[NL80211_BAND_2GHZ].rx = ar->num_rx_chains; } - if (pdev->cap.supported_bands & WMI_HOST_WLAN_5G_CAP) { + if (pdev->cap.supported_bands & WMI_HOST_WLAN_5G_CAP && + !ar->supports_6ghz) { arg->chains[NL80211_BAND_5GHZ].tx = ar->num_tx_chains; arg->chains[NL80211_BAND_5GHZ].rx = ar->num_rx_chains; } @@ -4833,97 +10628,51 @@ } arg->if_stats_id = ath12k_mac_get_vdev_stats_id(arvif); -} - -static u32 -ath12k_mac_prepare_he_mode(struct ath12k_pdev *pdev, u32 viftype) -{ - struct ath12k_pdev_cap *pdev_cap = &pdev->cap; - struct ath12k_band_cap *cap_band = NULL; - u32 *hecap_phy_ptr = NULL; - u32 hemode; - - if (pdev->cap.supported_bands & WMI_HOST_WLAN_2G_CAP) - cap_band = &pdev_cap->band[NL80211_BAND_2GHZ]; - else - cap_band = &pdev_cap->band[NL80211_BAND_5GHZ]; - - hecap_phy_ptr = &cap_band->he_cap_phy_info[0]; - - hemode = u32_encode_bits(HE_SU_BFEE_ENABLE, HE_MODE_SU_TX_BFEE) | - u32_encode_bits(HECAP_PHY_SUBFMR_GET(hecap_phy_ptr), - HE_MODE_SU_TX_BFER) | - u32_encode_bits(HECAP_PHY_ULMUMIMO_GET(hecap_phy_ptr), - HE_MODE_UL_MUMIMO); - /* TODO: WDS and other modes */ - if (viftype == NL80211_IFTYPE_AP) { - hemode |= u32_encode_bits(HECAP_PHY_MUBFMR_GET(hecap_phy_ptr), - HE_MODE_MU_TX_BFER) | - u32_encode_bits(HE_DL_MUOFDMA_ENABLE, HE_MODE_DL_OFDMA) | - u32_encode_bits(HE_UL_MUOFDMA_ENABLE, HE_MODE_UL_OFDMA); - } else { - hemode |= u32_encode_bits(HE_MU_BFEE_ENABLE, HE_MODE_MU_TX_BFEE); + if (ath12k_mac_is_ml_arvif(arvif)) { + if (hweight16(ahvif->vif->valid_links) > ATH12K_WMI_MLO_MAX_LINKS) { + WARN_ON(1); + return -EINVAL; } - - return hemode; + ether_addr_copy(arg->mld_addr, ahvif->vif->addr); } -static int ath12k_set_he_mu_sounding_mode(struct ath12k *ar, - struct ath12k_vif *arvif) -{ - u32 param_id, param_value; - struct ath12k_base *ab = ar->ab; - int ret; - - param_id = WMI_VDEV_PARAM_SET_HEMU_MODE; - param_value = ath12k_mac_prepare_he_mode(ar->pdev, arvif->vif->type); - ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, - param_id, param_value); - if (ret) { - ath12k_warn(ab, "failed to set vdev %d HE MU mode: %d param_value %x\n", - arvif->vdev_id, ret, param_value); - return ret; - } - param_id = WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE; - param_value = - u32_encode_bits(HE_VHT_SOUNDING_MODE_ENABLE, HE_VHT_SOUNDING_MODE) | - u32_encode_bits(HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE, - HE_TRIG_NONTRIG_SOUNDING_MODE); - ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, - param_id, param_value); - if (ret) { - ath12k_warn(ab, "failed to set vdev %d HE MU mode: %d\n", - arvif->vdev_id, ret); - return ret; - } - return ret; + return 0; } -static void ath12k_mac_op_update_vif_offload(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) +static void ath12k_mac_update_vif_offload(struct ath12k *ar, + struct ath12k_link_vif *arvif) { - struct ath12k *ar = hw->priv; struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; u32 param_id, param_value; int ret; param_id = WMI_VDEV_PARAM_TX_ENCAP_TYPE; - if (vif->type != NL80211_IFTYPE_STATION && - vif->type != NL80211_IFTYPE_AP) + if (ath12k_frame_mode != ATH12K_HW_TXRX_ETHERNET || + (vif->type != NL80211_IFTYPE_STATION && + vif->type != NL80211_IFTYPE_AP)) vif->offload_flags &= ~(IEEE80211_OFFLOAD_ENCAP_ENABLED | IEEE80211_OFFLOAD_DECAP_ENABLED); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (vif->type == NL80211_IFTYPE_AP && arvif->ndev_pvt + && (hweight16(vif->valid_links) > 1)) + vif->offload_flags |= (IEEE80211_OFFLOAD_ENCAP_ENABLED | + IEEE80211_OFFLOAD_DECAP_ENABLED); +#endif + if (vif->offload_flags & IEEE80211_OFFLOAD_ENCAP_ENABLED) - arvif->tx_encap_type = ATH12K_HW_TXRX_ETHERNET; - else if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) - arvif->tx_encap_type = ATH12K_HW_TXRX_RAW; + ahvif->tx_encap_type = ATH12K_HW_TXRX_ETHERNET; + else if (test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) + ahvif->tx_encap_type = ATH12K_HW_TXRX_RAW; else - arvif->tx_encap_type = ATH12K_HW_TXRX_NATIVE_WIFI; + ahvif->tx_encap_type = ATH12K_HW_TXRX_NATIVE_WIFI; ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, - param_id, arvif->tx_encap_type); + param_id, ahvif->tx_encap_type); if (ret) { ath12k_warn(ab, "failed to set vdev %d tx encap mode: %d\n", arvif->vdev_id, ret); @@ -4933,7 +10682,7 @@ param_id = WMI_VDEV_PARAM_RX_DECAP_TYPE; if (vif->offload_flags & IEEE80211_OFFLOAD_DECAP_ENABLED) param_value = ATH12K_HW_TXRX_ETHERNET; - else if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) + else if (test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) param_value = ATH12K_HW_TXRX_RAW; else param_value = ATH12K_HW_TXRX_NATIVE_WIFI; @@ -4947,110 +10696,250 @@ } } -static int ath12k_mac_op_add_interface(struct ieee80211_hw *hw, +static void ath12k_mac_hdl_update_vif_offload(struct ath12k_link_vif *arvif) +{ + if (!arvif->ar) { + ath12k_info(NULL, + "unable to determine device to apply vif encap/decap flags, setting will be applied on channel assignment\n"); + return; + } + + ath12k_mac_update_vif_offload(arvif->ar, arvif); + ath12k_dp_tx_update_bank_profile(arvif); +} + +static void ath12k_mac_op_update_vif_offload(struct ieee80211_hw *hw, struct ieee80211_vif *vif) { - struct ath12k *ar = hw->priv; + struct ath12k_hw *ah = hw->priv; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_link_vif *arvif; + int link_id; + + mutex_lock(&ah->conf_mutex); + if (vif->valid_links) { + unsigned long links = vif->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + if (!(arvif && arvif->ar)) + continue; + + ath12k_mac_hdl_update_vif_offload(arvif); + } + } else { + ath12k_mac_hdl_update_vif_offload(&ahvif->deflink); + } + mutex_unlock(&ah->conf_mutex); +} + +static void ath12k_update_bcn_template_work(struct work_struct *work) +{ + struct ath12k_link_vif *arvif = container_of(work, struct ath12k_link_vif, + update_bcn_template_work); + struct ath12k *ar = arvif->ar; + int ret = -EINVAL; + + if (!ar) + return; + + mutex_lock(&ar->conf_mutex); + if (arvif->is_created) + ret = ath12k_mac_setup_bcn_tmpl(arvif); + mutex_unlock(&ar->conf_mutex); + if (ret) + ath12k_warn(ar->ab, "failed to update bcn tmpl for vdev_id: %d ret: %d\n", + arvif->vdev_id, ret); +} + +static void ath12k_update_obss_color_notify_work(struct work_struct *work) +{ + struct ath12k_link_vif *arvif = container_of(work, struct ath12k_link_vif, + update_obss_color_notify_work); + struct ath12k *ar; + + ar = arvif->ar; + + if (!ar) + return; + + mutex_lock(&ar->conf_mutex); + if (arvif->is_created) + ieee80211_obss_color_collision_notify_mlo(arvif->ahvif->vif, + arvif->obss_color_bitmap, + GFP_KERNEL, + arvif->link_id); + arvif->obss_color_bitmap = 0; + mutex_unlock(&ar->conf_mutex); +} + + int ath12k_mac_vdev_create(struct ath12k *ar, struct ath12k_link_vif *arvif) +{ + struct ieee80211_vif *vif = arvif->ahvif->vif; struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_hw *hw = ar->ah->hw; struct ath12k_wmi_vdev_create_arg vdev_arg = {0}; - struct ath12k_wmi_peer_create_arg peer_param; + struct ath12k_wmi_peer_create_arg peer_param = {0}; + struct ieee80211_bss_conf *link_conf; u32 param_id, param_value; +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + struct wireless_dev *wdev = ieee80211_vif_to_wdev(vif); + struct net_device *link_ndev = NULL; + struct ath12k_link_vif_pvt *link_ndev_pvt = NULL; +#endif u16 nss; int i; - int ret; - int bit; + int ret, fbret, vdev_id; + u8 link_addr[ETH_ALEN]; + int txpower; + u8 link_id; - vif->driver_flags |= IEEE80211_VIF_SUPPORTS_UAPSD; + lockdep_assert_held(&ar->conf_mutex); - mutex_lock(&ar->conf_mutex); + /* If no link is active and scan vdev is requested + * use a default link conf for scan address purpose + */ + if (arvif->link_id == ATH12K_DEFAULT_SCAN_LINK && + vif->valid_links) + link_id = ffs(vif->valid_links) - 1; + else + link_id = arvif->link_id; - if (vif->type == NL80211_IFTYPE_AP && - ar->num_peers > (ar->max_num_peers - 1)) { - ath12k_warn(ab, "failed to create vdev due to insufficient peer entry resource in firmware\n"); - ret = -ENOBUFS; - goto err; - } + rcu_read_lock(); - if (ar->num_created_vdevs > (TARGET_NUM_VDEVS - 1)) { - ath12k_warn(ab, "failed to create vdev, reached max vdev limit %d\n", - TARGET_NUM_VDEVS); - ret = -EBUSY; - goto err; - } + link_conf = rcu_dereference(vif->link_conf[link_id]); - memset(arvif, 0, sizeof(*arvif)); + if (!link_conf) { + rcu_read_unlock(); + return -EINVAL; + } - arvif->ar = ar; - arvif->vif = vif; + if (arvif->link_id == ATH12K_DEFAULT_SCAN_LINK && + !is_zero_ether_addr(arvif->addr)) { + memcpy(link_addr, arvif->addr, ETH_ALEN); + } else { + memcpy(link_addr, link_conf->addr, ETH_ALEN); + memcpy(arvif->addr, link_conf->addr, ETH_ALEN); + } - INIT_LIST_HEAD(&arvif->list); + txpower = link_conf->txpower; + rcu_read_unlock(); - /* Should we initialize any worker to handle connection loss indication - * from firmware in sta mode? + /* Send vdev stats offload commands to firmware before first vdev + * creation. ie., when num_created_vdevs = 0 */ + if (ar->fw_stats.en_vdev_stats_ol && !ar->num_created_vdevs) { + ret = ath12k_dp_tx_htt_h2t_vdev_stats_ol_req(ar, 0); + if (ret) { + ath12k_warn(ar->ab, "failed to request vdev stats offload: %d\n", ret); + goto err; + } + } - for (i = 0; i < ARRAY_SIZE(arvif->bitrate_mask.control); i++) { - arvif->bitrate_mask.control[i].legacy = 0xffffffff; - memset(arvif->bitrate_mask.control[i].ht_mcs, 0xff, - sizeof(arvif->bitrate_mask.control[i].ht_mcs)); - memset(arvif->bitrate_mask.control[i].vht_mcs, 0xff, - sizeof(arvif->bitrate_mask.control[i].vht_mcs)); + spin_lock_bh(&ar->ab->base_lock); + + if (!ab->free_vdev_map) { + spin_unlock_bh(&ar->ab->base_lock); + ath12k_warn(ar->ab, "failed to create vdev. No free vdev id left.\n"); + ret = -EINVAL; + goto err; } - bit = __ffs64(ab->free_vdev_map); + vdev_id = __ffs64(ab->free_vdev_map); + ab->free_vdev_map &= ~(1LL << vdev_id); + spin_unlock_bh(&ar->ab->base_lock); - arvif->vdev_id = bit; - arvif->vdev_subtype = WMI_VDEV_SUBTYPE_NONE; + arvif->vdev_id = vdev_id; + /* Assume it as non-mbssid initially, well overwrite it later. + */ + arvif->tx_vdev_id = vdev_id; + ahvif->vdev_subtype = WMI_VDEV_SUBTYPE_NONE; + arvif->ar = ar; + arvif->ab = ab; + arvif->dp = &ab->dp; + arvif->dev = ab->dev; + arvif->pdev_idx = ar->pdev_idx; +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + if (arvif->link_id != ATH12K_DEFAULT_SCAN_LINK) { + link_ndev = vif->link_ndev[link_id]; + if (link_ndev) { + link_ndev_pvt = netdev_priv(link_ndev); + link_ndev_pvt->ab = ab; + link_ndev_pvt->arvif = arvif; + arvif->ndev_pvt = link_ndev_pvt; + } + } +#endif switch (vif->type) { case NL80211_IFTYPE_UNSPECIFIED: case NL80211_IFTYPE_STATION: - arvif->vdev_type = WMI_VDEV_TYPE_STA; + ahvif->vdev_type = WMI_VDEV_TYPE_STA; break; case NL80211_IFTYPE_MESH_POINT: - arvif->vdev_subtype = WMI_VDEV_SUBTYPE_MESH_11S; + ahvif->vdev_subtype = WMI_VDEV_SUBTYPE_MESH_11S; fallthrough; case NL80211_IFTYPE_AP: - arvif->vdev_type = WMI_VDEV_TYPE_AP; + ahvif->vdev_type = WMI_VDEV_TYPE_AP; break; case NL80211_IFTYPE_MONITOR: - arvif->vdev_type = WMI_VDEV_TYPE_MONITOR; - ar->monitor_vdev_id = bit; + ahvif->vdev_type = WMI_VDEV_TYPE_MONITOR; + ar->monitor_vdev_id = vdev_id; break; default: WARN_ON(1); break; } - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac add interface id %d type %d subtype %d map %llx\n", - arvif->vdev_id, arvif->vdev_type, arvif->vdev_subtype, + ath12k_dbg(ar->ab, ATH12K_DBG_SET(MAC, L1), "mac vdev create id %d type %d subtype %d map %llx\n", + arvif->vdev_id, ahvif->vdev_type, ahvif->vdev_subtype, ab->free_vdev_map); + /* TODO Revisit this sharing of common queues across all ar's */ vif->cab_queue = arvif->vdev_id % (ATH12K_HW_MAX_QUEUES - 1); for (i = 0; i < ARRAY_SIZE(vif->hw_queue); i++) vif->hw_queue[i] = i % (ATH12K_HW_MAX_QUEUES - 1); - ath12k_mac_setup_vdev_create_arg(arvif, &vdev_arg); + ret = ath12k_mac_setup_vdev_create_args(arvif, &vdev_arg); + if (ret) { + ath12k_warn(ab, "failed to create vdev parameters %d: %d\n", + arvif->vdev_id, ret); + goto err; + } - ret = ath12k_wmi_vdev_create(ar, vif->addr, &vdev_arg); + ret = ath12k_wmi_vdev_create(ar, vdev_arg.type == WMI_VDEV_TYPE_MONITOR ? + ar->mac_addr : link_addr, + &vdev_arg); if (ret) { ath12k_warn(ab, "failed to create WMI vdev %d: %d\n", arvif->vdev_id, ret); + spin_lock_bh(&ar->ab->base_lock); + ab->free_vdev_map |= 1LL << arvif->vdev_id; + spin_unlock_bh(&ar->ab->base_lock); + goto err; } ar->num_created_vdevs++; + ahvif->num_vdev_created++; + arvif->is_created = true; ath12k_dbg(ab, ATH12K_DBG_MAC, "vdev %pM created, vdev_id %d\n", - vif->addr, arvif->vdev_id); + link_addr, arvif->vdev_id); + ar->allocated_vdev_map |= 1LL << arvif->vdev_id; - ab->free_vdev_map &= ~(1LL << arvif->vdev_id); spin_lock_bh(&ar->data_lock); + + /* list added is not needed during mode1 recovery + * as the arvif(s) updated are from the existing + * list + */ + if (!ab->recovery_start) list_add(&arvif->list, &ar->arvifs); + spin_unlock_bh(&ar->data_lock); - ath12k_mac_op_update_vif_offload(hw, vif); + ath12k_mac_update_vif_offload(ar, arvif); nss = hweight32(ar->cfg_tx_chainmask) ? : 1; ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, @@ -5061,10 +10950,10 @@ goto err_vdev_del; } - switch (arvif->vdev_type) { + switch (ahvif->vdev_type) { case WMI_VDEV_TYPE_AP: peer_param.vdev_id = arvif->vdev_id; - peer_param.peer_addr = vif->addr; + peer_param.peer_addr = link_addr; peer_param.peer_type = WMI_PEER_TYPE_DEFAULT; ret = ath12k_peer_create(ar, arvif, NULL, &peer_param); if (ret) { @@ -5079,6 +10968,22 @@ arvif->vdev_id, ret); goto err_peer_del; } +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + if (arvif->link_id != ATH12K_DEFAULT_SCAN_LINK) { + if (hweight16(vif->valid_links) <= 1 && link_ndev && !wdev->ml_netdev) { + ath12k_free_bonddev_for_sfe(wdev, vif, link_id); + arvif->ndev_pvt = NULL; + arvif->ppe_vp_num = -1; + } else if (link_ndev && !arvif->ndev_pvt->is_bond_enslaved) { + ath12k_enable_ppe_for_link_netdev(ab, arvif, + arvif->ndev_pvt->link_ndev); + netif_tx_start_all_queues(arvif->ndev_pvt->bond_dev); + netif_tx_start_all_queues(arvif->ndev_pvt->link_ndev); + arvif->ndev_pvt->bond_dev->flags |= IFF_UP; + ath12k_bond_link_enslave(arvif, arvif->ndev_pvt->link_ndev); + } + } +#endif break; case WMI_VDEV_TYPE_STA: param_id = WMI_STA_PS_PARAM_RX_WAKE_POLICY; @@ -5118,17 +11023,20 @@ goto err_peer_del; } break; + case WMI_VDEV_TYPE_MONITOR: + set_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags); + break; default: break; } - arvif->txpower = vif->bss_conf.txpower; + arvif->txpower = txpower; ret = ath12k_mac_txpower_recalc(ar); if (ret) goto err_peer_del; param_id = WMI_VDEV_PARAM_RTS_THRESHOLD; - param_value = ar->hw->wiphy->rts_threshold; + param_value = hw->wiphy->rts_threshold; ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param_id, param_value); if (ret) { @@ -5138,47 +11046,240 @@ ath12k_dp_vdev_tx_attach(ar, arvif); - if (vif->type != NL80211_IFTYPE_MONITOR && ar->monitor_conf_enabled) + ath12k_mac_ap_ps_recalc(ar); + + if (vif->type != NL80211_IFTYPE_MONITOR && + test_bit(MONITOR_CONF_ENABLED, &ar->monitor_flags)) ath12k_mac_monitor_vdev_create(ar); - mutex_unlock(&ar->conf_mutex); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ret = ath12k_wmi_send_vdev_set_intra_bss_cmd(ar, arvif->vdev_id, + 1); + if (ret) { + ath12k_warn(ab, "failed to set vdev %d intra bss enable :%d\n", + arvif->vdev_id, ret); + goto err_peer_del; + } +#endif + + ath12k_debugfs_add_interface(arvif); return ret; err_peer_del: - if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { - reinit_completion(&ar->peer_delete_done); - - ret = ath12k_wmi_send_peer_delete_cmd(ar, vif->addr, - arvif->vdev_id); - if (ret) { - ath12k_warn(ar->ab, "failed to delete peer vdev_id %d addr %pM\n", - arvif->vdev_id, vif->addr); + if (ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + fbret = ath12k_peer_delete(ar, arvif->vdev_id, link_addr); + if (fbret) { + ath12k_warn(ar->ab, "failed to delete peer %pM vdev_id %d ret %d\n", + link_addr, arvif->vdev_id, fbret); goto err; } - - ret = ath12k_wait_for_peer_delete_done(ar, arvif->vdev_id, - vif->addr); - if (ret) - goto err; - - ar->num_peers--; } err_vdev_del: ath12k_wmi_vdev_delete(ar, arvif->vdev_id); ar->num_created_vdevs--; + arvif->is_created = false; ar->allocated_vdev_map &= ~(1LL << arvif->vdev_id); + spin_lock_bh(&ar->ab->base_lock); ab->free_vdev_map |= 1LL << arvif->vdev_id; + spin_unlock_bh(&ar->ab->base_lock); ab->free_vdev_stats_id_map &= ~(1LL << arvif->vdev_stats_id); spin_lock_bh(&ar->data_lock); list_del(&arvif->list); spin_unlock_bh(&ar->data_lock); err: + arvif->is_created = false; + arvif->ar = NULL; + return ret; +} + +void ath12k_mac_vif_cache_flush(struct ath12k *ar, struct ieee80211_vif *vif, + u8 link_id) +{ + struct ath12k_hw *ah = ar->ah; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + struct ath12k_key_conf *key_conf, *tmp; + struct ath12k_link_sta *arsta = NULL; + struct ath12k_sta *ahsta; + struct ath12k_vif_cache *cache; + int ret; + + lockdep_assert_held(&ah->conf_mutex); + + + arvif = ahvif->link[link_id]; + + if (WARN_ON(!arvif)) + return; + + if (WARN_ON(!arvif->is_created)) + return; + + cache = &ahvif->cache[link_id]; + + if (cache->tx_conf.changed) { + ret = ath12k_mac_conf_tx(ar, arvif, cache->tx_conf.ac, + &cache->tx_conf.tx_queue_params); + if (ret) + ath12k_warn(ar->ab, + "unable to apply tx config parameters to vdev %d\n", ret); + + memset(&cache->tx_conf, 0, sizeof(struct ath12k_tx_conf)); + } + + if (cache->bss_conf_changed) { + ath12k_mac_bss_info_changed(ar, arvif, &vif->bss_conf, + cache->bss_conf_changed); + + cache->bss_conf_changed = 0; + } + + if (!list_empty(&cache->key_conf.list)) { + list_for_each_entry_safe(key_conf, tmp, &cache->key_conf.list, list) { + if (key_conf->sta) { + ahsta = ath12k_sta_to_ahsta(key_conf->sta); + arsta = ahsta->link[link_id]; + } + + ret = ath12k_mac_set_key(ar, key_conf->cmd, + arvif, arsta, + key_conf->key); + if (ret) + ath12k_warn(ar->ab, "unable to apply set key param to vdev %d ret %d\n", + arvif->vdev_id, ret); + + list_del(&key_conf->list); + kfree(key_conf); + } + } +} + +static struct ath12k *ath12k_mac_assign_vif_to_vdev(struct ieee80211_hw *hw, + struct ath12k_link_vif *arvif, + struct ieee80211_chanctx_conf *ctx) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_base *ab; + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ath12k_link_vif *scan_arvif; + u8 bit; + int ret; + + lockdep_assert_held(&ah->conf_mutex); + + if (arvif->ar) + goto out; + + ar = ath12k_get_ar_by_ctx(hw, ctx); + + if (!ar) { + ath12k_err(NULL, + "unable to determine device for the passed channel ctx\n"); + goto out; + } + + /* cleanup the scan vdev if we are done scan on that ar + * and now we want to create for actual usage + */ + if (vif->valid_links) { + scan_arvif = arvif->ahvif->link[ATH12K_DEFAULT_SCAN_LINK]; + + if (scan_arvif && scan_arvif->ar == ar) { + mutex_lock(&ar->conf_mutex); + ar->scan.vdev_id = -1; mutex_unlock(&ar->conf_mutex); + ath12k_mac_remove_link_interface(hw, scan_arvif); + ath12k_mac_unassign_link_vif(scan_arvif); + } + } - return ret; + ab = ar->ab; + + mutex_lock(&ar->conf_mutex); + + if (vif->type == NL80211_IFTYPE_AP && + ar->num_peers > (ar->max_num_peers - 1)) { + ath12k_warn(ab, "failed to create vdev due to insufficient peer entry resource in firmware\n"); + ret = -ENOBUFS; + goto unlock; + } + + if (ar->num_created_vdevs > (TARGET_NUM_VDEVS - 1)) { + ath12k_warn(ab, "failed to create vdev, reached max vdev limit %d\n", + TARGET_NUM_VDEVS); + ret = -EBUSY; + goto unlock; + } + + ret = ath12k_mac_vdev_create(ar, arvif); + if (ret) { + ath12k_warn(ab, "failed to create vdev %d ret %d", bit, ret); + goto unlock; + } + + /* Apply any parameters for the vdev which were received after + * add_interface, corresponding to this vif + */ + ath12k_mac_vif_cache_flush(ar, vif, arvif->link_id); + +unlock: + mutex_unlock(&ar->conf_mutex); +out: + return arvif->ar; +} + +static int ath12k_mac_op_add_interface(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_hw *ah = hw->priv; + int i; + + /* The ar in which this vif will be assigned can be determined since + * it depends on the channel in which the vif is brought up. + * For now, prepare the vif/arvif with common changes + * TODO Add checks to ensure at least one ar has a free vdev + * Also if the hw uses only one link/ar the vdev could be created + * here itself + */ + + mutex_lock(&ah->conf_mutex); + memset(ahvif, 0, sizeof(*ahvif)); + + ahvif->vdev_type = vif->type; + ahvif->vif = vif; + ahvif->ah = ah; + + ahvif->deflink.ahvif = ahvif; + ahvif->deflink.link_id = 0; + ahvif->mcbc_gsn = 0; + INIT_LIST_HEAD(&ahvif->deflink.list); + INIT_WORK(&ahvif->deflink.update_obss_color_notify_work, + ath12k_update_obss_color_notify_work); + INIT_WORK(&ahvif->deflink.update_bcn_template_work, + ath12k_update_bcn_template_work); + ahvif->deflink.num_stations = 0; + init_completion(&ahvif->deflink.peer_ch_width_switch_send); + INIT_WORK(&ahvif->deflink.peer_ch_width_switch_work, + ath12k_wmi_peer_chan_width_switch_work); + + ahvif->key_cipher = INVALID_CIPHER; + + /* Allocate Default Queue now and reassign during actual vdev create */ + vif->cab_queue = ATH12K_HW_DEFAULT_QUEUE; + for (i = 0; i < ARRAY_SIZE(vif->hw_queue); i++) + vif->hw_queue[i] = ATH12K_HW_DEFAULT_QUEUE; + + for (i = 0; i < IEEE80211_MLD_MAX_NUM_LINKS; i++) + INIT_LIST_HEAD(&ahvif->cache[i].key_conf.list); + + vif->driver_flags |= IEEE80211_VIF_SUPPORTS_UAPSD; + mutex_unlock(&ah->conf_mutex); + return 0; } static void ath12k_mac_vif_unref(struct ath12k_dp *dp, struct ieee80211_vif *vif) @@ -5206,80 +11307,154 @@ } } -static void ath12k_mac_op_remove_interface(struct ieee80211_hw *hw, - struct ieee80211_vif *vif) +static void ath12k_mac_remove_link_interface(struct ieee80211_hw *hw, + struct ath12k_link_vif *arvif) { - struct ath12k *ar = hw->priv; - struct ath12k_vif *arvif = ath12k_vif_to_arvif(vif); - struct ath12k_base *ab = ar->ab; - unsigned long time_left; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + struct ath12k_key_conf *key_conf, *tmp; + struct ath12k_base *ab; + struct ath12k_mac_tx_mgmt_free_arg arg = { }; int ret; + cancel_work_sync(&arvif->update_obss_color_notify_work); + cancel_work_sync(&arvif->update_bcn_template_work); + cancel_work_sync(&arvif->peer_ch_width_switch_work); + + lockdep_assert_held(&ah->conf_mutex); + + ar = arvif->ar; + if (!ar) { + ath12k_dbg(NULL, ATH12K_DBG_MAC, + "unable to determine device to remove interface\n"); + return; + } + + ab = ar->ab; + mutex_lock(&ar->conf_mutex); ath12k_dbg(ab, ATH12K_DBG_MAC, "mac remove interface (vdev %d)\n", arvif->vdev_id); - if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { - ret = ath12k_peer_delete(ar, arvif->vdev_id, vif->addr); + ret = ath12k_spectral_vif_stop(arvif); if (ret) - ath12k_warn(ab, "failed to submit AP self-peer removal on vdev %d: %d\n", + ath12k_warn(ab, "failed to stop spectral for vdev %i: %d\n", arvif->vdev_id, ret); - } - - reinit_completion(&ar->vdev_delete_done); - ret = ath12k_wmi_vdev_delete(ar, arvif->vdev_id); - if (ret) { - ath12k_warn(ab, "failed to delete WMI vdev %d: %d\n", - arvif->vdev_id, ret); - goto err_vdev_del; + if (ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + ret = ath12k_peer_delete(ar, arvif->vdev_id, arvif->addr); + if (ret) + ath12k_warn(ab, "failed to submit AP self-peer removal on vdev %d: %d" + " num_peer : %d\n", arvif->vdev_id, ret, ar->num_peers); } - time_left = wait_for_completion_timeout(&ar->vdev_delete_done, - ATH12K_VDEV_DELETE_TIMEOUT_HZ); - if (time_left == 0) { - ath12k_warn(ab, "Timeout in receiving vdev delete response\n"); + ret = ath12k_mac_vdev_delete(ar, arvif); + if (ret) goto err_vdev_del; - } - if (arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { + if (ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { ar->monitor_vdev_id = -1; - ar->monitor_vdev_created = false; - } else if (ar->monitor_vdev_created && !ar->monitor_started) { + clear_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags); + } else if (test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags) && + !test_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags)) { ret = ath12k_mac_monitor_vdev_delete(ar); } - ab->free_vdev_map |= 1LL << (arvif->vdev_id); - ar->allocated_vdev_map &= ~(1LL << arvif->vdev_id); - ab->free_vdev_stats_id_map &= ~(1LL << arvif->vdev_stats_id); - ar->num_created_vdevs--; - ath12k_dbg(ab, ATH12K_DBG_MAC, "vdev %pM deleted, vdev_id %d\n", - vif->addr, arvif->vdev_id); + arvif->addr, arvif->vdev_id); err_vdev_del: + ath12k_peer_cleanup(ar, arvif->vdev_id); + spin_lock_bh(&ar->data_lock); - list_del(&arvif->list); - spin_unlock_bh(&ar->data_lock); - ath12k_peer_cleanup(ar, arvif->vdev_id); + arg.ar = ar; + arg.vif = vif; + arg.link_id = arvif->link_id; + arg.type = u8_encode_bits(true, ATH12K_MAC_TX_MGMT_FREE_TYPE_PDEV) | + u8_encode_bits(true, ATH12K_MAC_TX_MGMT_FREE_TYPE_VIF) | + u8_encode_bits(true, ATH12K_MAC_TX_MGMT_FREE_TYPE_LINK); idr_for_each(&ar->txmgmt_idr, - ath12k_mac_vif_txmgmt_idr_remove, vif); + ath12k_mac_tx_mgmt_pending_free, &arg); + + spin_unlock_bh(&ar->data_lock); ath12k_mac_vif_unref(&ab->dp, vif); ath12k_dp_tx_put_bank_profile(&ab->dp, arvif->bank_id); + ahvif->key_cipher = INVALID_CIPHER; /* Recalc txpower for remaining vdev */ ath12k_mac_txpower_recalc(ar); - clear_bit(ATH12K_FLAG_MONITOR_ENABLED, &ar->monitor_flags); + ath12k_mac_ap_ps_recalc(ar); + + ath12k_debugfs_remove_interface(arvif); + + if (arvif->link_id < IEEE80211_MLD_MAX_NUM_LINKS && + !list_empty(&ahvif->cache[arvif->link_id].key_conf.list)) { + list_for_each_entry_safe(key_conf, tmp, + &ahvif->cache[arvif->link_id].key_conf.list, + list) { + list_del(&key_conf->list); + kfree(key_conf); + } + } /* TODO: recal traffic pause state based on the available vdevs */ mutex_unlock(&ar->conf_mutex); } +static void ath12k_mac_op_remove_interface(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + struct ath12k *ar; + u8 link_id; + int ret; + + mutex_lock(&ah->conf_mutex); + + for_each_set_bit(link_id, &ahvif->links_map, ATH12K_NUM_MAX_LINKS) { + arvif = ahvif->link[link_id]; + + if (!arvif) + continue; + + ar = arvif->ar; + + if (!ar) + continue; + + if (WARN_ON(arvif->link_id != link_id)) + continue; + + if (arvif->is_scan_vif && arvif->is_started) { + mutex_lock(&ar->conf_mutex); + ret = ath12k_mac_vdev_stop(arvif); + mutex_unlock(&ar->conf_mutex); + if (ret) { + mutex_unlock(&ah->conf_mutex); + ath12k_warn(ar->ab, "failed to stop vdev %d: %d\n", + arvif->vdev_id, ret); + return; + } + arvif->is_started = false; + arvif->is_scan_vif = false; + } + + ath12k_mac_remove_link_interface(hw, arvif); + ath12k_mac_unassign_link_vif(arvif); + } + + mutex_unlock(&ah->conf_mutex); +} + /* FIXME: Has to be verified. */ #define SUPPORTED_FILTERS \ (FIF_ALLMULTI | \ @@ -5295,77 +11470,107 @@ unsigned int *total_flags, u64 multicast) { - struct ath12k *ar = hw->priv; - bool reset_flag; - int ret; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + int i; + mutex_lock(&ah->conf_mutex); + + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { mutex_lock(&ar->conf_mutex); - changed_flags &= SUPPORTED_FILTERS; *total_flags &= SUPPORTED_FILTERS; ar->filter_flags = *total_flags; - /* For monitor mode */ - reset_flag = !(ar->filter_flags & FIF_BCN_PRBRESP_PROMISC); - - ret = ath12k_dp_tx_htt_monitor_mode_ring_config(ar, reset_flag); - if (!ret) { - if (!reset_flag) - set_bit(ATH12K_FLAG_MONITOR_ENABLED, &ar->monitor_flags); - else - clear_bit(ATH12K_FLAG_MONITOR_ENABLED, &ar->monitor_flags); - } else { - ath12k_warn(ar->ab, - "fail to set monitor filter: %d\n", ret); - } - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, - "changed_flags:0x%x, total_flags:0x%x, reset_flag:%d\n", - changed_flags, *total_flags, reset_flag); - mutex_unlock(&ar->conf_mutex); + ar++; + } + mutex_unlock(&ah->conf_mutex); } +/* TODO Also support link based antenna configs, below might not be accurate */ static int ath12k_mac_op_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant) { - struct ath12k *ar = hw->priv; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + int antennas_rx = 0, antennas_tx = 0, i; + + mutex_lock(&ah->conf_mutex); + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { mutex_lock(&ar->conf_mutex); - *tx_ant = ar->cfg_tx_chainmask; - *rx_ant = ar->cfg_rx_chainmask; + antennas_tx = max_t(u32, antennas_tx, ar->cfg_tx_chainmask); + antennas_rx = max_t(u32, antennas_rx, ar->cfg_rx_chainmask); mutex_unlock(&ar->conf_mutex); + ar++; + } + + *tx_ant = antennas_tx; + *rx_ant = antennas_rx; + + mutex_unlock(&ah->conf_mutex); return 0; } static int ath12k_mac_op_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant) { - struct ath12k *ar = hw->priv; - int ret; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + int ret = 0, i; + + mutex_lock(&ah->conf_mutex); + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { mutex_lock(&ar->conf_mutex); ret = __ath12k_set_antenna(ar, tx_ant, rx_ant); mutex_unlock(&ar->conf_mutex); + ar++; + } + + mutex_unlock(&ah->conf_mutex); + return ret; } -static int ath12k_mac_op_ampdu_action(struct ieee80211_hw *hw, +static int ath12k_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - struct ieee80211_ampdu_params *params) + struct ieee80211_ampdu_params *params, + u8 link_id) { - struct ath12k *ar = hw->priv; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; int ret = -EINVAL; + lockdep_assert_held(&ah->conf_mutex); + + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + if (!ar) { + ath12k_err(NULL, "unable to determine device to set ampdu params\n"); + return -EPERM; + } + + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) + return -ESHUTDOWN; + + if (params->sta->mlo && + (test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &ar->ab->dev_flags))) + return 0; + mutex_lock(&ar->conf_mutex); switch (params->action) { case IEEE80211_AMPDU_RX_START: - ret = ath12k_dp_rx_ampdu_start(ar, params); + ret = ath12k_dp_rx_ampdu_start(ar, params, link_id); break; case IEEE80211_AMPDU_RX_STOP: - ret = ath12k_dp_rx_ampdu_stop(ar, params); + ret = ath12k_dp_rx_ampdu_stop(ar, params, link_id); break; case IEEE80211_AMPDU_TX_START: case IEEE80211_AMPDU_TX_STOP_CONT: @@ -5379,18 +11584,67 @@ break; } + if (ret) + ath12k_warn(ar->ab, "unable to perform ampdu action %d ret %d\n", + params->action, ret); + mutex_unlock(&ar->conf_mutex); return ret; } +static int ath12k_mac_op_ampdu_action(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_ampdu_params *params) +{ + struct ieee80211_sta *sta = params->sta; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = hw->priv; + int ret = -EINVAL; + u8 link_id; + + if (WARN_ON(!ahsta->links_map)) + return -EINVAL; + + mutex_lock(&ah->conf_mutex); + + for_each_set_bit(link_id, &ahsta->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + ret = ath12k_mac_ampdu_action(hw, vif, params, link_id); + if (ret) + break; + } + + mutex_unlock(&ah->conf_mutex); + + return ret; +} + +#ifndef CONFIG_ATH12K_BONDED_DS_SUPPORT +int ath12k_mac_op_change_vif_links(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + u16 old_links, u16 new_links, + struct ieee80211_bss_conf *old[IEEE80211_MLD_MAX_NUM_LINKS]) +{ + ath12k_info(NULL, + "link changed for MLD %pM old %d new %d\n", vif->addr, old_links, new_links); + return 0; +} +#endif + static int ath12k_mac_op_add_chanctx(struct ieee80211_hw *hw, struct ieee80211_chanctx_conf *ctx) { - struct ath12k *ar = hw->priv; - struct ath12k_base *ab = ar->ab; + struct ath12k *ar; - ath12k_dbg(ab, ATH12K_DBG_MAC, + ar = ath12k_get_ar_by_ctx(hw, ctx); + + if (!ar) { + ath12k_err(NULL, + "unable to determine device for the passed channel ctx\n"); + return -EINVAL; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac chanctx add freq %u width %d ptr %pK\n", ctx->def.chan->center_freq, ctx->def.width, ctx); @@ -5403,6 +11657,7 @@ ar->rx_channel = ctx->def.chan; spin_unlock_bh(&ar->data_lock); + ar->chan_tx_pwr = ATH12K_PDEV_TX_POWER_INVALID; mutex_unlock(&ar->conf_mutex); return 0; @@ -5411,10 +11666,17 @@ static void ath12k_mac_op_remove_chanctx(struct ieee80211_hw *hw, struct ieee80211_chanctx_conf *ctx) { - struct ath12k *ar = hw->priv; - struct ath12k_base *ab = ar->ab; + struct ath12k *ar; - ath12k_dbg(ab, ATH12K_DBG_MAC, + ar = ath12k_get_ar_by_ctx(hw, ctx); + + if (!ar) { + ath12k_err(NULL, + "unable to determine device for the passed channel ctx\n"); + return; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac chanctx remove freq %u width %d ptr %pK\n", ctx->def.chan->center_freq, ctx->def.width, ctx); @@ -5427,18 +11689,186 @@ ar->rx_channel = NULL; spin_unlock_bh(&ar->data_lock); + ar->chan_tx_pwr = ATH12K_PDEV_TX_POWER_INVALID; mutex_unlock(&ar->conf_mutex); } +static int ath12k_mac_set_6g_nonht_dup_conf(struct ath12k_link_vif *arvif, + const struct cfg80211_chan_def *chandef) +{ + struct ath12k *ar = arvif->ar; + int param_id, ret = 0; + uint8_t value = 0; + bool is_psc = cfg80211_channel_is_psc(chandef->chan); + enum wmi_phy_mode mode = ath12k_phymodes[chandef->chan->band][chandef->width]; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_bss_conf *link_conf; + u8 link_addr[ETH_ALEN]; + bool nontransmitted; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + return -EINVAL; + } + + memcpy(link_addr, link_conf->addr, ETH_ALEN); + nontransmitted = link_conf->nontransmitted; + rcu_read_unlock(); + + if ((ahvif->vdev_type == WMI_VDEV_TYPE_AP) && + !nontransmitted && + (chandef->chan->band == NL80211_BAND_6GHZ)) { + param_id = WMI_VDEV_PARAM_6GHZ_PARAMS; + if (mode > MODE_11AX_HE20 && !is_psc) { + value |= WMI_VDEV_6GHZ_BITMAP_NON_HT_DUPLICATE_BEACON; + value |= WMI_VDEV_6GHZ_BITMAP_NON_HT_DUPLICATE_BCAST_PROBE_RSP; + value |= WMI_VDEV_6GHZ_BITMAP_NON_HT_DUPLICATE_FD_FRAME; + } + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "Set 6GHz non-ht dup params for vdev %pM ,vdev_id %d param %d value %d\n", + link_addr, arvif->vdev_id, param_id, value); + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, param_id, value); + } + return ret; +} + +static void +ath12k_mac_mlo_get_vdev_args(struct ath12k_link_vif *arvif, + struct wmi_ml_arg *ml_arg) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k_link_vif *arvif_p; + u8 link_id; + struct wmi_ml_partner_info *partner_info; + struct ieee80211_bss_conf *link_conf; + + if (!ath12k_mac_is_ml_arvif(arvif)) + return; + + if (hweight16(ahvif->vif->valid_links) > ATH12K_WMI_MLO_MAX_LINKS) + return; + + rcu_read_lock(); + + ml_arg->enabled = true; + + /* We always add a new link via VDEV START, FW takes + * care of internally adding this link to existing + * link vdevs which are advertised as partners below + */ + ml_arg->link_add = true; + + /* TODO check assoc and mcast vdev for AP mode */ + + partner_info = ml_arg->partner_info; + + for_each_set_bit(link_id, &ahvif->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif_p = ahvif->link[link_id]; + + if (WARN_ON(arvif_p == NULL)) + continue; + + if (arvif == arvif_p) + continue; + + link_conf = rcu_dereference(ahvif->vif->link_conf[arvif_p->link_id]); + + if (!link_conf) + continue; + + partner_info->vdev_id = arvif_p->vdev_id; + partner_info->hw_link_id = arvif_p->ar->pdev->hw_link_id; + ether_addr_copy(partner_info->addr, link_conf->addr); + ml_arg->num_partner_links++; + partner_info++; + } + rcu_read_unlock(); +} + static int -ath12k_mac_vdev_start_restart(struct ath12k_vif *arvif, +ath12k_mac_vdev_config_after_start(struct ath12k_link_vif *arvif, + const struct cfg80211_chan_def *chandef) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ath12k *ar = arvif->ar; + struct ath12k_base *ab = ar->ab; + int ret; + unsigned int dfs_cac_time; + + lockdep_assert_held(&ar->conf_mutex); + + if (ar->supports_6ghz && + chandef->chan->band == NL80211_BAND_6GHZ && + (ahvif->vdev_type == WMI_VDEV_TYPE_STA || ahvif->vdev_type == WMI_VDEV_TYPE_AP) && + test_bit(WMI_TLV_SERVICE_EXT_TPC_REG_SUPPORT, ar->ab->wmi_ab.svc_map)) { + + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) + ath12k_mac_parse_tx_pwr_env(ar, arvif, &arvif->chanctx); + + ath12k_mac_fill_reg_tpc_info(ar, arvif, &arvif->chanctx); + ath12k_wmi_send_vdev_set_tpc_power(ar, arvif->vdev_id, + &arvif->reg_tpc_info); + } + + /* Enable CAC Flag in the driver by checking all sub-channel's DFS + * state as NL80211_DFS_USABLE which indicates CAC needs to be + * done before channel usage. This flags is used to drop rx packets. + * during CAC. + */ + /* TODO Set the flag for other interface types as required */ + if (ahvif->vdev_type == WMI_VDEV_TYPE_AP && arvif->chanctx.radar_enabled && + cfg80211_chandef_dfs_usable(ar->ah->hw->wiphy, chandef)) { + set_bit(ATH12K_CAC_RUNNING, &ar->dev_flags); + dfs_cac_time = cfg80211_chandef_dfs_cac_time(ar->ah->hw->wiphy, + chandef/*, false, false */); + ath12k_dbg(ab, ATH12K_DBG_MAC, + "CAC (for %u ms) Started in center_freq %d center_freq1 %d for vdev %d\n", + dfs_cac_time, chandef->chan->center_freq, + chandef->center_freq1, arvif->vdev_id); + } + + ret = ath12k_mac_set_txbf_conf(arvif); + if (ret) + ath12k_warn(ab, "failed to set txbf conf for vdev %d: %d\n", + arvif->vdev_id, ret); + + ret = ath12k_mac_set_6g_nonht_dup_conf(arvif, chandef); + if (ret) + ath12k_warn(ab, "failed to set 6G non-ht dup conf for vdev %d: %d\n", + arvif->vdev_id, ret); + /* In case of ADFS, we have to abort ongoing backgrorund CAC */ + if ((ar->pdev->cap.supported_bands & WMI_HOST_WLAN_5G_CAP) && + test_bit(ar->cfg_rx_chainmask, &ar->pdev->cap.adfs_chain_mask) && + ar->agile_chandef.chan) { + ath12k_dbg(ab, ATH12K_DBG_MAC, + "Aborting ongoing Agile DFS on freq %d", + ar->agile_chandef.chan->center_freq); + ret = ath12k_wmi_vdev_adfs_ocac_abort_cmd_send(ar,arvif->vdev_id); + if (!ret) { + memset(&ar->agile_chandef, 0, sizeof(struct cfg80211_chan_def)); + ar->agile_chandef.chan = NULL; + ath12k_mac_background_dfs_event(ar, ATH12K_BGDFS_ABORT); + } else { + ath12k_warn(ab, "failed to abort agile CAC for vdev %d", + arvif->vdev_id); + } + } + + return ret; +} + +static int ath12k_mac_vdev_start_restart(struct ath12k_link_vif *arvif, const struct cfg80211_chan_def *chandef, - bool restart) + bool restart, bool radar_enabled) { + struct ath12k_vif *ahvif = arvif->ahvif; struct ath12k *ar = arvif->ar; struct ath12k_base *ab = ar->ab; struct wmi_vdev_start_req_arg arg = {}; - int he_support = arvif->vif->bss_conf.he_support; int ret; lockdep_assert_held(&ar->conf_mutex); @@ -5449,50 +11879,66 @@ arg.dtim_period = arvif->dtim_period; arg.bcn_intval = arvif->beacon_interval; - arg.freq = chandef->chan->center_freq; - arg.band_center_freq1 = chandef->center_freq1; - arg.band_center_freq2 = chandef->center_freq2; - arg.mode = ath12k_phymodes[chandef->chan->band][chandef->width]; - - arg.min_power = 0; - arg.max_power = chandef->chan->max_power * 2; - arg.max_reg_power = chandef->chan->max_reg_power * 2; - arg.max_antenna_gain = chandef->chan->max_antenna_gain * 2; + arg.channel.freq = chandef->chan->center_freq; + arg.channel.band_center_freq1 = chandef->center_freq1; + arg.channel.band_center_freq2 = chandef->center_freq2; + arg.channel.mode = + ath12k_phymodes[chandef->chan->band][chandef->width]; + + arg.channel.min_power = 0; + arg.channel.max_power = chandef->chan->max_power; + arg.channel.max_reg_power = chandef->chan->max_reg_power; + arg.channel.max_antenna_gain = chandef->chan->max_antenna_gain; + arg.ru_punct_bitmap = ~chandef->ru_punct_bitmap; + if (test_bit(WMI_TLV_SERVICE_SW_PROG_DFS_SUPPORT, + ar->ab->wmi_ab.svc_map)) { +#if 0 + arg.width_device = chandef->width_device; + arg.center_freq_device = chandef->center_freq_device; +#endif + } arg.pref_tx_streams = ar->num_tx_chains; arg.pref_rx_streams = ar->num_rx_chains; - if (arvif->vdev_type == WMI_VDEV_TYPE_AP) { - arg.ssid = arvif->u.ap.ssid; - arg.ssid_len = arvif->u.ap.ssid_len; - arg.hidden_ssid = arvif->u.ap.hidden_ssid; + arg.mbssid_flags = 0; + arg.mbssid_tx_vdev_id = 0; + if (test_bit(WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT, + ar->ab->wmi_ab.svc_map)) { + ret = ath12k_mac_setup_vdev_args_mbssid(arvif, + &arg.mbssid_flags, + &arg.mbssid_tx_vdev_id); + if (ret) + return ret; + } + + if (ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + arg.ssid = ahvif->u.ap.ssid; + arg.ssid_len = ahvif->u.ap.ssid_len; + arg.hidden_ssid = ahvif->u.ap.hidden_ssid; /* For now allow DFS for AP mode */ - arg.chan_radar = !!(chandef->chan->flags & IEEE80211_CHAN_RADAR); + arg.channel.chan_radar = + !!(chandef->chan->flags & IEEE80211_CHAN_RADAR); + arg.channel.freq2_radar = radar_enabled; + - arg.passive = arg.chan_radar; + arg.channel.passive = arg.channel.chan_radar; spin_lock_bh(&ab->base_lock); arg.regdomain = ar->ab->dfs_region; spin_unlock_bh(&ab->base_lock); - - /* TODO: Notify if secondary 80Mhz also needs radar detection */ - if (he_support) { - ret = ath12k_set_he_mu_sounding_mode(ar, arvif); - if (ret) { - ath12k_warn(ar->ab, "failed to set he mode vdev %i\n", - arg.vdev_id); - return ret; - } - } } - arg.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR); + arg.channel.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR); + + if (!restart) + ath12k_mac_mlo_get_vdev_args(arvif, &arg.ml); ath12k_dbg(ab, ATH12K_DBG_MAC, - "mac vdev %d start center_freq %d phymode %s\n", - arg.vdev_id, arg.freq, - ath12k_mac_phymode_str(arg.mode)); + "mac vdev %d start center_freq %d punct bitmap 0x%x phymode %s\n", + arg.vdev_id, arg.channel.freq, arg.ru_punct_bitmap, + ath12k_mac_phymode_str(arg.channel.mode)); ret = ath12k_wmi_vdev_start(ar, &arg, restart); if (ret) { @@ -5507,85 +11953,198 @@ arg.vdev_id, restart ? "restart" : "start", ret); return ret; } - + arvif->vdev_stop_notify_done = false; ar->num_started_vdevs++; ath12k_dbg(ab, ATH12K_DBG_MAC, "vdev %pM started, vdev_id %d\n", - arvif->vif->addr, arvif->vdev_id); + arvif->addr, arvif->vdev_id); - /* Enable CAC Flag in the driver by checking the channel DFS cac time, - * i.e dfs_cac_ms value which will be valid only for radar channels - * and state as NL80211_DFS_USABLE which indicates CAC needs to be - * done before channel usage. This flags is used to drop rx packets. - * during CAC. - */ - /* TODO: Set the flag for other interface types as required */ - if (arvif->vdev_type == WMI_VDEV_TYPE_AP && - chandef->chan->dfs_cac_ms && - chandef->chan->dfs_state == NL80211_DFS_USABLE) { - set_bit(ATH12K_CAC_RUNNING, &ar->dev_flags); - ath12k_dbg(ab, ATH12K_DBG_MAC, - "CAC Started in chan_freq %d for vdev %d\n", - arg.freq, arg.vdev_id); - } - - ret = ath12k_mac_set_txbf_conf(arvif); + ret = ath12k_mac_vdev_config_after_start(arvif, chandef); if (ret) - ath12k_warn(ab, "failed to set txbf conf for vdev %d: %d\n", - arvif->vdev_id, ret); + ath12k_warn(ab, "failed to configure vdev %d after %s: %d\n", + arvif->vdev_id, + restart ? "restart" : "start", ret); return 0; } -static int ath12k_mac_vdev_stop(struct ath12k_vif *arvif) +int ath12k_mac_vdev_start(struct ath12k_link_vif *arvif, + const struct cfg80211_chan_def *chandef, + bool radar_enabled) +{ + return ath12k_mac_vdev_start_restart(arvif, chandef, false, + radar_enabled); +} + +static int ath12k_mac_vdev_restart(struct ath12k_link_vif *arvif, + const struct cfg80211_chan_def *chandef, + bool pseudo_restart, bool radar_enabled) { - struct ath12k *ar = arvif->ar; + struct ath12k_base *ab = arvif->ar->ab; int ret; - lockdep_assert_held(&ar->conf_mutex); - - reinit_completion(&ar->vdev_setup_done); + if(!pseudo_restart) + return ath12k_mac_vdev_start_restart(arvif, chandef, true, + radar_enabled); - ret = ath12k_wmi_vdev_stop(ar, arvif->vdev_id); + ret = ath12k_mac_vdev_stop(arvif); if (ret) { - ath12k_warn(ar->ab, "failed to stop WMI vdev %i: %d\n", + ath12k_warn(ab, "failed to stop vdev %d: %d during restart\n", arvif->vdev_id, ret); - goto err; + return ret; } - ret = ath12k_mac_vdev_setup_sync(ar); + ret = ath12k_mac_vdev_start(arvif, chandef, radar_enabled); if (ret) { - ath12k_warn(ar->ab, "failed to synchronize setup for vdev %i: %d\n", + ath12k_warn(ab, "failed to start vdev %d: %d during restart\n", arvif->vdev_id, ret); - goto err; + return ret; } - WARN_ON(ar->num_started_vdevs == 0); + return ret; +} - ar->num_started_vdevs--; - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "vdev %pM stopped, vdev_id %d\n", - arvif->vif->addr, arvif->vdev_id); +static void +ath12k_mac_update_peer_ru_punct_bitmap_iter(void *data, + struct ieee80211_sta *sta) +{ + struct ath12k_link_vif *arvif = data; + struct ath12k *ar = arvif->ar; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta; + struct ieee80211_link_sta *link_sta; + u8 link_id = arvif->link_id; - if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { - clear_bit(ATH12K_CAC_RUNNING, &ar->dev_flags); - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "CAC Stopped for vdev %d\n", - arvif->vdev_id); + if (ahsta->ahvif != arvif->ahvif) + return; + + /* Check if there is a link sta in the vif link */ + if (!(BIT(link_id) & ahsta->links_map)) + return; + + arsta = ahsta->link[link_id]; + link_sta = ath12k_get_link_sta(arsta); + if (!link_sta) { + ath12k_warn(ar->ab, "unable to access link sta in peer ru punct bitmap update\n"); + return; } - return 0; -err: - return ret; + /* Puncturing in only applicable for EHT supported peers */ + if (!link_sta->he_cap.has_he || !link_sta->eht_cap.has_eht) + return; + + spin_lock_bh(&ar->data_lock); + /* RC_BW_CHANGED handler has infra already to send the bitmap. + * Hence we can leverage from the same flag + */ + arsta->changed |= IEEE80211_RC_BW_CHANGED; + spin_unlock_bh(&ar->data_lock); + + ieee80211_queue_work(ar->ah->hw, &arsta->update_wk); } -static int ath12k_mac_vdev_start(struct ath12k_vif *arvif, - const struct cfg80211_chan_def *chandef) +void ath12k_mac_update_ru_punct_bitmap(struct ath12k_link_vif *arvif, + struct ieee80211_chanctx_conf *old_ctx, + struct ieee80211_chanctx_conf *new_ctx) { - return ath12k_mac_vdev_start_restart(arvif, chandef, false); + struct ath12k *ar = arvif->ar; + struct ath12k_hw *ah = ar->ah; + + lockdep_assert_held(&ah->conf_mutex); + lockdep_assert_held(&ar->conf_mutex); + + if (old_ctx->def.ru_punct_bitmap == new_ctx->def.ru_punct_bitmap) + return; + + ieee80211_iterate_stations_atomic(ah->hw, + ath12k_mac_update_peer_ru_punct_bitmap_iter, + arvif); } -static int ath12k_mac_vdev_restart(struct ath12k_vif *arvif, - const struct cfg80211_chan_def *chandef) +static int ath12k_vdev_restart_sequence(struct ath12k_link_vif *arvif, + struct ieee80211_chanctx_conf *new_ctx, + u64 vif_down_failed_map, + int vdev_index) { - return ath12k_mac_vdev_start_restart(arvif, chandef, true); + struct ath12k *ar = arvif->ar; + struct ath12k_link_vif *tx_arvif; + struct ath12k_vif *tx_ahvif; + struct ieee80211_bss_conf *link; + struct ieee80211_chanctx_conf old_chanctx; + struct vdev_up_params params = { 0 }; + int ret = -EINVAL; + struct ath12k_vif *ahvif = arvif->ahvif; + + spin_lock_bh(&ar->data_lock); + old_chanctx = arvif->chanctx; + memcpy(&arvif->chanctx, new_ctx, sizeof(*new_ctx)); + spin_unlock_bh(&ar->data_lock); + + /* vdev is already restarted via mvr, need to setup + * certain config alone after restart */ + if (vdev_index == -1) { + ret = ath12k_mac_vdev_config_after_start(arvif, &new_ctx->def); + if (!ret) + goto beacon_tmpl_setup; + } else if (vif_down_failed_map & BIT_ULL(vdev_index)) { + ret = ath12k_mac_vdev_restart(arvif, &new_ctx->def, false, + new_ctx->radar_enabled); + } else { + ret = ath12k_mac_vdev_restart(arvif, &new_ctx->def, true, + new_ctx->radar_enabled); + } + + if (ret) { + ath12k_warn(ar->ab, "failed to restart vdev %d: %d\n", + arvif->vdev_id, ret); + spin_lock_bh(&ar->data_lock); + arvif->chanctx = old_chanctx; + spin_unlock_bh(&ar->data_lock); + return ret; + } + +beacon_tmpl_setup: + ath12k_mac_update_ru_punct_bitmap(arvif, &old_chanctx, new_ctx); + + if (arvif->pending_csa_up) + return 0; + + if (!arvif->is_up) + return -EOPNOTSUPP; + + ret = ath12k_mac_setup_bcn_tmpl(arvif); + if (ret) { + ath12k_warn(ar->ab, "failed to update bcn tmpl during csa: %d\n", arvif->vdev_id); + return ret; + } + + params.vdev_id = arvif->vdev_id; + params.aid = ahvif->aid; + params.bssid = arvif->bssid; + rcu_read_lock(); + link = rcu_dereference(ahvif->vif->link_conf[arvif->link_id]); + if (link->mbssid_tx_vif) { + tx_ahvif = (void *)link->mbssid_tx_vif->drv_priv; + tx_arvif = tx_ahvif->link[link->mbssid_tx_vif_linkid]; + params.tx_bssid = tx_arvif->bssid; + params.profile_idx = ahvif->vif->bss_conf.bssid_index; + params.profile_count = BIT(link->bssid_indicator); + } + + if (ahvif->vif->type == NL80211_IFTYPE_STATION && link->nontransmitted) { + params.profile_idx = link->bssid_index; + params.profile_count = BIT(link->bssid_indicator) - 1; + params.tx_bssid = link->transmitter_bssid; + } + + rcu_read_unlock(); + ret = ath12k_wmi_vdev_up(arvif->ar, ¶ms); + if (ret) { + ath12k_warn(ar->ab, "failed to bring vdev up %d: %d\n", + arvif->vdev_id, ret); + return ret; + } + + return ret; } struct ath12k_mac_change_chanctx_arg { @@ -5593,30 +12152,74 @@ struct ieee80211_vif_chanctx_switch *vifs; int n_vifs; int next_vif; + bool csa_active; + struct ath12k *ar; }; static void ath12k_mac_change_chanctx_cnt_iter(void *data, u8 *mac, struct ieee80211_vif *vif) { + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_link_vif *arvif; struct ath12k_mac_change_chanctx_arg *arg = data; + u8 link_id; + struct ieee80211_bss_conf *link_conf; + struct ath12k_hw *ah = ahvif->ah; - if (rcu_access_pointer(vif->bss_conf.chanctx_conf) != arg->ctx) - return; + lockdep_assert_held(&ah->conf_mutex); + + for_each_set_bit(link_id, &ahvif->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + + if (WARN_ON(arvif == NULL)) + continue; + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (WARN_ON(link_conf == NULL)) + continue; + + if ((rcu_access_pointer(link_conf->chanctx_conf) != arg->ctx) || + (arvif->ar != arg->ar)) + continue; + + if (link_conf->csa_active) + arg->csa_active = true; arg->n_vifs++; } +} static void ath12k_mac_change_chanctx_fill_iter(void *data, u8 *mac, struct ieee80211_vif *vif) { + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + struct ath12k_link_vif *arvif; struct ath12k_mac_change_chanctx_arg *arg = data; struct ieee80211_chanctx_conf *ctx; + u8 link_id; + struct ieee80211_bss_conf *link_conf; + struct ath12k_hw *ah = ahvif->ah; - ctx = rcu_access_pointer(vif->bss_conf.chanctx_conf); - if (ctx != arg->ctx) - return; + lockdep_assert_held(&ah->conf_mutex); + + for_each_set_bit(link_id, &ahvif->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + + if (WARN_ON(arvif == NULL)) + continue; + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (WARN_ON(link_conf == NULL)) + continue; + + ctx = rcu_access_pointer(link_conf->chanctx_conf); + if ((ctx != arg->ctx) || + (arvif->ar != arg->ar)) + continue; if (WARN_ON(arg->next_vif == arg->n_vifs)) return; @@ -5624,8 +12227,179 @@ arg->vifs[arg->next_vif].vif = vif; arg->vifs[arg->next_vif].old_ctx = ctx; arg->vifs[arg->next_vif].new_ctx = ctx; + arg->vifs[arg->next_vif].link_conf = link_conf; arg->next_vif++; } +} + +static void ath12k_mac_num_chanctxs_iter(struct ieee80211_hw *hw, + struct ieee80211_chanctx_conf *conf, + void *data) +{ + struct ath12k_mac_num_chanctxs_arg *arg = + (struct ath12k_mac_num_chanctxs_arg *)data; + struct ath12k *ctx_ar, *ar = arg->ar; + + ctx_ar = ath12k_get_ar_by_ctx(ar->ah->hw, conf); + + if (ctx_ar == ar) + arg->num++; +} + +static int ath12k_mac_num_chanctxs(struct ath12k *ar) +{ + struct ath12k_mac_num_chanctxs_arg arg = { .ar = ar, .num = 0}; + + ieee80211_iter_chan_contexts_atomic(ar->ah->hw, + ath12k_mac_num_chanctxs_iter, + &arg); + + return arg.num; +} + +static void ath12k_mac_update_rx_channel(struct ath12k *ar, + struct ieee80211_chanctx_conf *ctx, + struct ieee80211_vif_chanctx_switch *vifs, + int n_vifs) +{ + struct ath12k_mac_any_chandef_arg arg = { .ar = ar, .def = NULL}; + + /* Both locks are required because ar->rx_channel is modified. This + * allows readers to hold either lock. + */ + lockdep_assert_held(&ar->conf_mutex); + lockdep_assert_held(&ar->data_lock); + + WARN_ON(ctx && vifs); + WARN_ON(vifs && !n_vifs); + + /* FIXME: Sort of an optimization and a workaround. Peers and vifs are + * on a linked list now. Doing a lookup peer -> vif -> chanctx for each + * ppdu on Rx may reduce performance on low-end systems. It should be + * possible to make tables/hashmaps to speed the lookup up (be vary of + * cpu data cache lines though regarding sizes) but to keep the initial + * implementation simple and less intrusive fallback to the slow lookup + * only for multi-channel cases. Single-channel cases will remain to + * use the old channel derival and thus performance should not be + * affected much. + */ + rcu_read_lock(); + if (!ctx && ath12k_mac_num_chanctxs(ar) == 1) { + ieee80211_iter_chan_contexts_atomic(ar->ah->hw, + ath12k_mac_get_any_chandef_iter, + &arg); + if (vifs) + ar->rx_channel = vifs[0].new_ctx->def.chan; + else if (arg.def) + ar->rx_channel = arg.def->chan; + else + ar->rx_channel = NULL; + } else if ((ctx && ath12k_mac_num_chanctxs(ar) == 0) || + (ctx && (ar->state == ATH12K_STATE_RESTARTED))) { + /* During driver restart due to firmware assert, since mac80211 + * already has valid channel context for given radio, channel + * context iteration return num_chanctx > 0. So fix rx_channel + * when restart is in progress. + */ + ar->rx_channel = ctx->def.chan; + } else { + ar->rx_channel = NULL; + } + rcu_read_unlock(); + ar->chan_tx_pwr = ATH12K_PDEV_TX_POWER_INVALID; +} + +static int +ath12k_mac_multi_vdev_restart(struct ath12k *ar, + const struct cfg80211_chan_def *chandef, + u32 *vdev_id, int len, + bool radar_enabled) +{ + struct ath12k_base *ab = ar->ab; + struct wmi_pdev_multiple_vdev_restart_req_arg arg = {}; + int ret, i; + + lockdep_assert_held(&ar->conf_mutex); + + arg.vdev_ids.id_len = len; + + for (i = 0; i < len; i++) + arg.vdev_ids.id[i] = vdev_id[i]; + + arg.channel.freq = chandef->chan->center_freq; + arg.channel.band_center_freq1 = chandef->center_freq1; + arg.channel.band_center_freq2 = chandef->center_freq2; + arg.channel.mode = + ath12k_phymodes[chandef->chan->band][chandef->width]; + + arg.channel.min_power = 0; + arg.channel.max_power = chandef->chan->max_power; + arg.channel.max_reg_power = chandef->chan->max_reg_power; + arg.channel.max_antenna_gain = chandef->chan->max_antenna_gain; + arg.channel.chan_radar = !!(chandef->chan->flags & IEEE80211_CHAN_RADAR); + arg.channel.passive = arg.channel.chan_radar; + arg.channel.freq2_radar = radar_enabled; + arg.channel.passive |= !!(chandef->chan->flags & IEEE80211_CHAN_NO_IR); + arg.ru_punct_bitmap = ~chandef->ru_punct_bitmap; + + if (test_bit(WMI_TLV_SERVICE_SW_PROG_DFS_SUPPORT, + ar->ab->wmi_ab.svc_map)) { +#if 0 + arg.width_device = chandef->width_device; + arg.center_freq_device = chandef->center_freq_device; +#endif + } + + ret = ath12k_wmi_pdev_multiple_vdev_restart(ar, &arg); + if (ret) + ath12k_warn(ab, "mac failed to do mvr (%d)\n", ret); + + return ret; +} + +static void +ath12k_mac_update_vif_chan_extras(struct ath12k *ar, + struct ieee80211_vif_chanctx_switch *vifs, + int n_vifs) +{ + struct ath12k_base *ab = ar->ab; + struct cfg80211_chan_def *chandef; + lockdep_assert_held(&ar->conf_mutex); + + chandef = &vifs[0].new_ctx->def; + + spin_lock_bh(&ar->data_lock); + if (ar->awgn_intf_handling_in_prog && chandef) { + if (!ar->chan_bw_interference_bitmap || + (ar->chan_bw_interference_bitmap & WMI_DCS_SEG_PRI20)) { + if (ar->awgn_chandef.chan->center_freq != + chandef->chan->center_freq) { + ar->awgn_intf_handling_in_prog = false; + ath12k_dbg(ab, ATH12K_DBG_MAC, + "AWGN : channel switch completed\n"); + } else { + ath12k_warn(ab, "AWGN : channel switch is not done, freq : %d\n", + ar->awgn_chandef.chan->center_freq); + } + } else { + if ((ar->awgn_chandef.chan->center_freq == + chandef->chan->center_freq) && + (ar->awgn_chandef.width != chandef->width)) { + ath12k_dbg(ab, ATH12K_DBG_MAC, + "AWGN : BW reduction is complete\n"); + ar->awgn_intf_handling_in_prog = false; + } else { + ath12k_warn(ab, "AWGN : awgn_freq : %d chan_freq %d" + " awgn_width %d chan_width %d\n", + ar->awgn_chandef.chan->center_freq, + chandef->chan->center_freq, + ar->awgn_chandef.width, + chandef->width); + } + } + } + spin_unlock_bh(&ar->data_lock); +} static void ath12k_mac_update_vif_chan(struct ath12k *ar, @@ -5633,18 +12407,31 @@ int n_vifs) { struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif; + struct ath12k_link_vif *arvif, *tx_arvif; + struct ath12k_vif *ahvif, *tx_ahvif = NULL; int ret; - int i; - bool monitor_vif = false; + int i, trans_vdev_index; + u64 vif_down_failed_map = 0; + struct ieee80211_vif *tx_vif; + struct ieee80211_bss_conf *link; + + /* Each vif is mapped to each bit of vif_down_failed_map. */ + if (n_vifs > sizeof(vif_down_failed_map)*__CHAR_BIT__) { + ath12k_warn(ar->ab, "%d n_vifs are not supported currently\n", + n_vifs); + return; + } lockdep_assert_held(&ar->conf_mutex); + tx_arvif = NULL; + for (i = 0; i < n_vifs; i++) { - arvif = (void *)vifs[i].vif->drv_priv; + ahvif = (void *)vifs[i].vif->drv_priv; + arvif = ahvif->link[vifs[i].link_conf->link_id]; - if (vifs[i].vif->type == NL80211_IFTYPE_MONITOR) - monitor_vif = true; + if (WARN_ON(!arvif)) + continue; ath12k_dbg(ab, ATH12K_DBG_MAC, "mac chanctx switch vdev_id %i freq %u->%u width %d->%d\n", @@ -5654,88 +12441,289 @@ vifs[i].old_ctx->def.width, vifs[i].new_ctx->def.width); - if (WARN_ON(!arvif->is_started)) + if (!arvif->is_started) { + memcpy(&arvif->chanctx, vifs[i].new_ctx, sizeof(*vifs[i].new_ctx)); continue; + } - if (WARN_ON(!arvif->is_up)) + if (!arvif->is_up) continue; + if (vifs[i].link_conf->mbssid_tx_vif && + ahvif == (struct ath12k_vif *)vifs[i].link_conf->mbssid_tx_vif->drv_priv) { + tx_vif = vifs[i].link_conf->mbssid_tx_vif; + tx_ahvif = ath12k_vif_to_ahvif(tx_vif); + tx_arvif = tx_ahvif->link[vifs[i].link_conf->mbssid_tx_vif_linkid]; + trans_vdev_index = i; + } + ret = ath12k_wmi_vdev_down(ar, arvif->vdev_id); if (ret) { + vif_down_failed_map |= BIT_ULL(i); ath12k_warn(ab, "failed to down vdev %d: %d\n", arvif->vdev_id, ret); continue; } } - /* All relevant vdevs are downed and associated channel resources - * should be available for the channel switch now. - */ + ath12k_mac_update_rx_channel(ar, NULL, vifs, n_vifs); - /* TODO: Update ar->rx_channel */ + if (tx_arvif) { + rcu_read_lock(); + link = rcu_dereference(tx_ahvif->vif->link_conf[tx_arvif->link_id]); + + if (link->csa_active && tx_arvif->ahvif->vdev_type == WMI_VDEV_TYPE_AP) + tx_arvif->pending_csa_up = true; + + rcu_read_unlock(); + + ret = ath12k_vdev_restart_sequence(tx_arvif, + vifs[trans_vdev_index].new_ctx, + vif_down_failed_map, + trans_vdev_index); + + if (ret) + ath12k_warn(ab, "failed to restart vdev:%d: %d\n", + tx_arvif->vdev_id, ret); + } for (i = 0; i < n_vifs; i++) { - arvif = (void *)vifs[i].vif->drv_priv; + ahvif = (void *)vifs[i].vif->drv_priv; + arvif = ahvif->link[vifs[i].link_conf->link_id]; - if (WARN_ON(!arvif->is_started)) + if (WARN_ON(!arvif)) continue; - if (WARN_ON(!arvif->is_up)) + if (vifs[i].link_conf->mbssid_tx_vif && + arvif == tx_arvif) continue; - ret = ath12k_mac_vdev_restart(arvif, &vifs[i].new_ctx->def); - if (ret) { - ath12k_warn(ab, "failed to restart vdev %d: %d\n", + rcu_read_lock(); + link = rcu_dereference(ahvif->vif->link_conf[arvif->link_id]); + + if (link->csa_active && arvif->ahvif->vdev_type == WMI_VDEV_TYPE_AP) + arvif->pending_csa_up = true; + + rcu_read_unlock(); + + ret = ath12k_vdev_restart_sequence(arvif, + vifs[i].new_ctx, + vif_down_failed_map, i); + + if (ret && ret != -EOPNOTSUPP) { + ath12k_warn(ab, "failed to bring up vdev %d: %d\n", arvif->vdev_id, ret); + } + } +} + +static void +ath12k_mac_update_vif_chan_mvr(struct ath12k *ar, + struct ieee80211_vif_chanctx_switch *vifs, + int n_vifs) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_link_vif *arvif, *tx_arvif = NULL; + struct ath12k_vif *ahvif, *tx_ahvif = NULL; + struct cfg80211_chan_def *chandef; + struct ieee80211_vif *tx_vif; + int ret, i, time_left, trans_vdev_index, vdev_idx, n_vdevs = 0; + u32 vdev_ids[TARGET_NUM_VDEVS]; + struct ieee80211_bss_conf *link; + bool monitor_vif = false; + int k; + + lockdep_assert_held(&ar->conf_mutex); + + chandef = &vifs[0].new_ctx->def; + tx_arvif = NULL; + + ath12k_dbg(ab, ATH12K_DBG_MAC, "mac chanctx switch via mvr"); + + ath12k_mac_update_rx_channel(ar, NULL, vifs, n_vifs); + + for (i = 0; i < n_vifs; i++) { + ahvif = (void *)vifs[i].vif->drv_priv; + arvif = ahvif->link[vifs[i].link_conf->link_id]; + + if (WARN_ON(!arvif)) + continue; + + ath12k_dbg(ab, ATH12K_DBG_MAC, + "mac chanctx switch vdev_id %i freq %u->%u width %d->%d\n", + arvif->vdev_id, + vifs[i].old_ctx->def.chan->center_freq, + vifs[i].new_ctx->def.chan->center_freq, + vifs[i].old_ctx->def.width, + vifs[i].new_ctx->def.width); + + if (!arvif->is_started) { + memcpy(&arvif->chanctx, vifs[i].new_ctx, sizeof(*vifs[i].new_ctx)); continue; } - ret = ath12k_mac_setup_bcn_tmpl(arvif); - if (ret) - ath12k_warn(ab, "failed to update bcn tmpl during csa: %d\n", - ret); + if (vifs[i].link_conf->mbssid_tx_vif && + ahvif == (struct ath12k_vif *)vifs[i].link_conf->mbssid_tx_vif->drv_priv) { + tx_vif = vifs[i].link_conf->mbssid_tx_vif; + tx_ahvif = ath12k_vif_to_ahvif(tx_vif); + tx_arvif = tx_ahvif->link[vifs[i].link_conf->mbssid_tx_vif_linkid]; + trans_vdev_index = i; + } + + arvif->mvr_processing = true; + vdev_ids[n_vdevs++] = arvif->vdev_id; + } - ret = ath12k_wmi_vdev_up(arvif->ar, arvif->vdev_id, arvif->aid, - arvif->bssid); + for (k = 0; k < n_vifs; k++) { + if (vifs[k].vif->type == NL80211_IFTYPE_MONITOR) { + monitor_vif = true; + break; + } + } + if (!monitor_vif && + test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags)) { + vdev_ids[n_vdevs++] = ar->monitor_vdev_id; + } + + if (!n_vdevs) { + ath12k_dbg(ab, ATH12K_DBG_MAC, + "mac 0 vdevs available to switch chan ctx via mvr\n"); + return; + } + + reinit_completion(&ar->mvr_complete); + + ret = ath12k_mac_multi_vdev_restart(ar, chandef, vdev_ids, n_vdevs, + vifs[0].new_ctx->radar_enabled); if (ret) { - ath12k_warn(ab, "failed to bring vdev up %d: %d\n", - arvif->vdev_id, ret); - continue; + ath12k_warn(ab, "mac failed to send mvr command (%d)\n", ret); + return; } + + time_left = wait_for_completion_timeout(&ar->mvr_complete, + WMI_MVR_CMD_TIMEOUT_HZ); + if (!time_left) { + ath12k_err(ar->ab, "mac mvr cmd response timed out\n"); + /* fallback to restarting one-by-one */ + return ath12k_mac_update_vif_chan(ar, vifs, n_vifs); + } + + if (tx_arvif) { + vdev_idx = -1; + + if (tx_arvif->mvr_processing) { + /* failed to restart tx vif via mvr, fallback */ + arvif->mvr_processing = false; + vdev_idx = trans_vdev_index; + ath12k_err(ab, + "mac failed to restart mbssid tx vdev %d via mvr cmd\n", + tx_arvif->vdev_id); } - /* Restart the internal monitor vdev on new channel */ - if (!monitor_vif && ar->monitor_vdev_created) { - if (!ath12k_mac_monitor_stop(ar)) - ath12k_mac_monitor_start(ar); + rcu_read_lock(); + link = rcu_dereference(tx_ahvif->vif->link_conf[tx_arvif->link_id]); + + if (link->csa_active && tx_arvif->ahvif->vdev_type == WMI_VDEV_TYPE_AP) + tx_arvif->pending_csa_up = true; + + rcu_read_unlock(); + + ret = ath12k_vdev_restart_sequence(tx_arvif, + vifs[trans_vdev_index].new_ctx, + BIT_ULL(trans_vdev_index), + vdev_idx); + if (ret) + ath12k_warn(ab, + "mac failed to bring up mbssid tx vdev %d after mvr (%d)\n", + tx_arvif->vdev_id, ret); + } + + for (i = 0; i < n_vifs; i++) { + ahvif = (void *)vifs[i].vif->drv_priv; + arvif = ahvif->link[vifs[i].link_conf->link_id]; + + if (WARN_ON(!arvif)) + continue; + + vdev_idx = -1; + + if (vifs[i].link_conf->mbssid_tx_vif && arvif == tx_arvif) + continue; + + if (arvif->mvr_processing) { + /* failed to restart vdev via mvr, fallback */ + arvif->mvr_processing = false; + vdev_idx = i; + ath12k_err(ab, "mac failed to restart vdev %d via mvr cmd\n", + arvif->vdev_id); } + + rcu_read_lock(); + link = rcu_dereference(ahvif->vif->link_conf[arvif->link_id]); + + if (link->csa_active && arvif->ahvif->vdev_type == WMI_VDEV_TYPE_AP) + arvif->pending_csa_up = true; + + rcu_read_unlock(); + + ret = ath12k_vdev_restart_sequence(arvif, vifs[i].new_ctx, + BIT_ULL(i), vdev_idx); + if (ret && ret != -EOPNOTSUPP) + ath12k_warn(ab, "mac failed to bring up vdev %d after mvr (%d)\n", + arvif->vdev_id, ret); + } +} + +static void +ath12k_mac_process_update_vif_chan(struct ath12k *ar, + struct ieee80211_vif_chanctx_switch *vifs, + int n_vifs) +{ + struct ath12k_base *ab = ar->ab; + + lockdep_assert_held(&ar->conf_mutex); + + /* should not happen */ + if (WARN_ON(n_vifs > TARGET_NUM_VDEVS)) + return; + + if (ath12k_wmi_is_mvr_supported(ab)) + ath12k_mac_update_vif_chan_mvr(ar, vifs, n_vifs); + else + ath12k_mac_update_vif_chan(ar, vifs, n_vifs); + + ath12k_mac_update_vif_chan_extras(ar, vifs, n_vifs); } static void ath12k_mac_update_active_vif_chan(struct ath12k *ar, struct ieee80211_chanctx_conf *ctx) { - struct ath12k_mac_change_chanctx_arg arg = { .ctx = ctx }; + struct ath12k_mac_change_chanctx_arg arg = { .ctx = ctx, + .csa_active = false, + .ar = ar }; + struct ath12k_hw *ah = ar->ah; lockdep_assert_held(&ar->conf_mutex); - ieee80211_iterate_active_interfaces_atomic(ar->hw, + ieee80211_iterate_active_interfaces_atomic(ah->hw, IEEE80211_IFACE_ITER_NORMAL, ath12k_mac_change_chanctx_cnt_iter, &arg); - if (arg.n_vifs == 0) + + if (arg.n_vifs == 0 || arg.csa_active) return; arg.vifs = kcalloc(arg.n_vifs, sizeof(arg.vifs[0]), GFP_KERNEL); if (!arg.vifs) return; - ieee80211_iterate_active_interfaces_atomic(ar->hw, + ieee80211_iterate_active_interfaces_atomic(ah->hw, IEEE80211_IFACE_ITER_NORMAL, ath12k_mac_change_chanctx_fill_iter, &arg); - ath12k_mac_update_vif_chan(ar, arg.vifs, arg.n_vifs); + ath12k_mac_process_update_vif_chan(ar, arg.vifs, arg.n_vifs); kfree(arg.vifs); } @@ -5744,8 +12732,21 @@ struct ieee80211_chanctx_conf *ctx, u32 changed) { - struct ath12k *ar = hw->priv; - struct ath12k_base *ab = ar->ab; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_base *ab; + + mutex_lock(&ah->conf_mutex); + + ar = ath12k_get_ar_by_ctx(hw, ctx); + + if (!ar) { + ath12k_err(NULL, "unable to determine device for the passed channel ctx\n"); + mutex_unlock(&ah->conf_mutex); + return; + } + + ab = ar->ab; mutex_lock(&ar->conf_mutex); @@ -5759,35 +12760,38 @@ if (WARN_ON(changed & IEEE80211_CHANCTX_CHANGE_CHANNEL)) goto unlock; - if (changed & IEEE80211_CHANCTX_CHANGE_WIDTH) + if (changed & IEEE80211_CHANCTX_CHANGE_WIDTH || + changed & IEEE80211_CHANCTX_CHANGE_RADAR) ath12k_mac_update_active_vif_chan(ar, ctx); /* TODO: Recalc radar detection */ unlock: mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); } -static int ath12k_start_vdev_delay(struct ieee80211_hw *hw, +static int ath12k_start_vdev_delay(struct ath12k *ar, struct ieee80211_vif *vif) { - struct ath12k *ar = hw->priv; struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif = &ahvif->deflink; int ret; if (WARN_ON(arvif->is_started)) return -EBUSY; - ret = ath12k_mac_vdev_start(arvif, &arvif->chanctx.def); + ret = ath12k_mac_vdev_start(arvif, &arvif->chanctx.def, + arvif->chanctx.radar_enabled); if (ret) { ath12k_warn(ab, "failed to start vdev %i addr %pM on freq %d: %d\n", - arvif->vdev_id, vif->addr, + arvif->vdev_id, arvif->addr, arvif->chanctx.def.chan->center_freq, ret); return ret; } - if (arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { + if (ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { ret = ath12k_monitor_vdev_up(ar, arvif->vdev_id); if (ret) { ath12k_warn(ab, "failed put monitor up: %d\n", ret); @@ -5801,17 +12805,636 @@ return 0; } +static u8 ath12k_mac_get_tpe_count(u8 txpwr_intrprt, u8 txpwr_cnt) +{ + switch (txpwr_intrprt) { + /* Refer "Table 9-276-Meaning of Maximum Transmit Power Count subfield + * if the Maximum Transmit Power Interpretation subfield is 0 or 2" of + * "IEEE Std 802.11ax 2021". + */ + case IEEE80211_TPE_LOCAL_EIRP: + case IEEE80211_TPE_REG_CLIENT_EIRP: + txpwr_cnt = txpwr_cnt <= 3 ? txpwr_cnt : 3; + txpwr_cnt = txpwr_cnt + 1; + break; + /* Refer "Table 9-277-Meaning of Maximum Transmit Power Count subfield + * if Maximum Transmit Power Interpretation subfield is 1 or 3" of + * "IEEE Std 802.11ax 2021". + */ + case IEEE80211_TPE_LOCAL_EIRP_PSD: + case IEEE80211_TPE_REG_CLIENT_EIRP_PSD: + txpwr_cnt = txpwr_cnt <= 4 ? txpwr_cnt : 4; + txpwr_cnt = txpwr_cnt ? (BIT(txpwr_cnt - 1)) : 1; + break; + } + + return txpwr_cnt; +} + +static u8 ath12k_mac_get_num_pwr_levels(struct cfg80211_chan_def *chan_def) +{ + u8 num_pwr_levels; + + if (chan_def->chan->flags & IEEE80211_CHAN_PSD) { + switch (chan_def->width) { + case NL80211_CHAN_WIDTH_20: + num_pwr_levels = 1; + break; + case NL80211_CHAN_WIDTH_40: + num_pwr_levels = 2; + break; + case NL80211_CHAN_WIDTH_80: + num_pwr_levels = 4; + break; + case NL80211_CHAN_WIDTH_80P80: + case NL80211_CHAN_WIDTH_160: + num_pwr_levels = 8; + break; + case NL80211_CHAN_WIDTH_320: + num_pwr_levels = 16; + break; + default: + return 1; + } + } else { + switch (chan_def->width) { + case NL80211_CHAN_WIDTH_20: + num_pwr_levels = 1; + break; + case NL80211_CHAN_WIDTH_40: + num_pwr_levels = 2; + break; + case NL80211_CHAN_WIDTH_80: + num_pwr_levels = 3; + break; + case NL80211_CHAN_WIDTH_80P80: + case NL80211_CHAN_WIDTH_160: + num_pwr_levels = 4; + break; + case NL80211_CHAN_WIDTH_320: + num_pwr_levels = 5; + break; + default: + return 1; + } + } + + return num_pwr_levels; +} + +static u16 ath12k_mac_get_6g_start_frequency(struct cfg80211_chan_def *chan_def) +{ + u16 diff_seq; + + /* It is to get the lowest channel number's center frequency of the chan. + * For example, + * bandwidth=40MHz, center frequency is 5965, lowest channel is 1 + * with center frequency 5955, its diff is 5965 - 5955 = 10. + * bandwidth=80MHz, center frequency is 5985, lowest channel is 1 + * with center frequency 5955, its diff is 5985 - 5955 = 30. + * bandwidth=160MHz, center frequency is 6025, lowest channel is 1 + * with center frequency 5955, its diff is 6025 - 5955 = 70. + */ + switch (chan_def->width) { + case NL80211_CHAN_WIDTH_320: + diff_seq = 150; + break; + case NL80211_CHAN_WIDTH_160: + diff_seq = 70; + break; + case NL80211_CHAN_WIDTH_80: + case NL80211_CHAN_WIDTH_80P80: + diff_seq = 30; + break; + case NL80211_CHAN_WIDTH_40: + diff_seq = 10; + break; + default: + diff_seq = 0; + } + + return chan_def->center_freq1 - diff_seq; +} + +static u16 ath12k_mac_get_seg_freq(struct cfg80211_chan_def *chan_def, + u16 start_seq, u8 seq) +{ + u16 seg_seq; + + /* It is to get the center frequency of the specific bandwidth. + * start_seq means the lowest channel number's center freqence. + * seq 0/1/2/3 means 20MHz/40MHz/80MHz/160MHz&80P80. + * For example, + * lowest channel is 1, its center frequency 5955, + * center frequency is 5955 when bandwidth=20MHz, its diff is 5955 - 5955 = 0. + * lowest channel is 1, its center frequency 5955, + * center frequency is 5965 when bandwidth=40MHz, its diff is 5965 - 5955 = 10. + * lowest channel is 1, its center frequency 5955, + * center frequency is 5985 when bandwidth=80MHz, its diff is 5985 - 5955 = 30. + * lowest channel is 1, its center frequency 5955, + * center frequency is 6025 when bandwidth=160MHz, its diff is 6025 - 5955 = 70. + */ + if (chan_def->width == NL80211_CHAN_WIDTH_80P80 && seq == 3) + return chan_def->center_freq2; + + seg_seq = 10 * (BIT(seq) - 1); + return seg_seq + start_seq; +} + +static void ath12k_mac_get_psd_channel(struct ath12k *ar, + u16 step_freq, + u16 *start_freq, + u16 *center_freq, + u8 i, + struct ieee80211_channel **temp_chan, + s8 *tx_power, + u8 reg_6g_power_mode) +{ + /* It is to get the the center frequency for each 20MHz. + * For example, if the chan is 160MHz and center frequency is 6025, + * then it include 8 channels, they are 1/5/9/13/17/21/25/29, + * channel number 1's center frequency is 5955, it is parameter start_freq. + * parameter i is the step of the 8 channels. i is 0~7 for the 8 channels. + * the channel 1/5/9/13/17/21/25/29 maps i=0/1/2/3/4/5/6/7, + * and maps its center frequency is 5955/5975/5995/6015/6035/6055/6075/6095, + * the gap is 20 for each channel, parameter step_freq means the gap. + * after get the center frequency of each channel, it is easy to find the + * struct ieee80211_channel of it and get the max_reg_power. + */ + *center_freq = *start_freq + i * step_freq; + /* -1 to reg_6g_power_mode to make it 0 based indexing */ + *temp_chan = ieee80211_get_channel_khz(ar->ah->hw->wiphy, MHZ_TO_KHZ(*center_freq)); + *tx_power = (*temp_chan)->max_reg_power; +} + +static void ath12k_mac_get_eirp_power(struct ath12k *ar, + u16 *start_freq, + u16 *center_freq, + u8 i, + struct ieee80211_channel **temp_chan, + struct cfg80211_chan_def *def, + s8 *tx_power, + u8 reg_6g_power_mode) +{ + /* It is to get the the center frequency for 40MHz/80MHz/ + * 160MHz&80P80 bandwidth, and then plus 10 to the center frequency, + * it is the center frequency of a channel number. + * For example, when configured channel number is 1. + * center frequency is 5965 when bandwidth=40MHz, after plus 10, it is 5975, + * then it is channel number 5. + * center frequency is 5985 when bandwidth=80MHz, after plus 10, it is 5995, + * then it is channel number 9. + * center frequency is 6025 when bandwidth=160MHz, after plus 10, it is 6035, + * then it is channel number 17. + * after get the center frequency of each channel, it is easy to find the + * struct ieee80211_channel of it and get the max_reg_power. + */ + *center_freq = ath12k_mac_get_seg_freq(def, *start_freq, i); + /* For 20 MHz, no +10 offset is required */ + if (i != 0) + *center_freq += 10; + + /* -1 to reg_6g_power_mode to make it 0 based indexing */ + *temp_chan = ieee80211_get_channel_khz(ar->ah->hw->wiphy, MHZ_TO_KHZ(*center_freq)); + *tx_power = (*temp_chan)->max_reg_power; +} + +void ath12k_mac_fill_reg_tpc_info(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ieee80211_chanctx_conf *ctx) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_bss_conf *bss_conf; + struct ath12k_reg_tpc_power_info *reg_tpc_info = &arvif->reg_tpc_info; + struct ieee80211_channel *chan, *temp_chan; + u8 pwr_lvl_idx, num_pwr_levels, pwr_reduction; + bool is_psd_power = false, is_tpe_present = false; + s8 max_tx_power[ATH12K_MAX_NUM_PWR_LEVEL], + psd_power, tx_power = 0, eirp_power = 0; + u16 oper_freq = 0, start_freq = 0, center_freq = 0; + u8 reg_6g_power_mode; + + rcu_read_lock(); + + bss_conf = ath12k_get_link_bss_conf(arvif); + + if (!bss_conf) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access bss link conf in tpc reg fill\n"); + return; + } + + /* For STA, 6g power mode will be present in the beacon, but for AP, + * AP cant parse its own beacon. Hence, we get the 6g power mode + * from the wdev corresponding to the struct ieee80211_vif + */ + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) { + reg_6g_power_mode = bss_conf->power_type; + if (reg_6g_power_mode == IEEE80211_REG_UNSET_AP) + reg_6g_power_mode = IEEE80211_REG_LPI_AP; + } else if (ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + reg_6g_power_mode = IEEE80211_REG_LPI_AP; + } else + reg_6g_power_mode = IEEE80211_REG_LPI_AP; + + chan = ctx->def.chan; + oper_freq = ctx->def.chan->center_freq; + start_freq = ath12k_mac_get_6g_start_frequency(&ctx->def); + pwr_reduction = bss_conf->pwr_reduction; + + rcu_read_unlock(); + + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA && + arvif->reg_tpc_info.num_pwr_levels) { + is_tpe_present = true; + num_pwr_levels = arvif->reg_tpc_info.num_pwr_levels; + } else { + num_pwr_levels = ath12k_mac_get_num_pwr_levels(&ctx->def); + } + + for (pwr_lvl_idx = 0; pwr_lvl_idx < num_pwr_levels; pwr_lvl_idx++) { + /* STA received TPE IE*/ + if (is_tpe_present) { + /* local power is PSD power*/ + if (chan->flags & IEEE80211_CHAN_PSD) { + /* Connecting AP is psd power */ + if (reg_tpc_info->is_psd_power) { + is_psd_power = true; + ath12k_mac_get_psd_channel(ar, 20, + &start_freq, + ¢er_freq, + pwr_lvl_idx, + &temp_chan, + &tx_power, + reg_6g_power_mode); + psd_power = temp_chan->psd; + eirp_power = tx_power; + max_tx_power[pwr_lvl_idx] = + min_t(s8, + psd_power, + reg_tpc_info->tpe[pwr_lvl_idx]); + /* Connecting AP is not psd power */ + } else { + ath12k_mac_get_eirp_power(ar, + &start_freq, + ¢er_freq, + pwr_lvl_idx, + &temp_chan, + &ctx->def, + &tx_power, + reg_6g_power_mode); + psd_power = temp_chan->psd; + /* convert psd power to EIRP power based + * on channel width + */ + tx_power = + min_t(s8, tx_power, + psd_power + 13 + pwr_lvl_idx * 3); + max_tx_power[pwr_lvl_idx] = + min_t(s8, + tx_power, + reg_tpc_info->tpe[pwr_lvl_idx]); + } + /* local power is not PSD power */ + } else { + /* Connecting AP is psd power */ + if (reg_tpc_info->is_psd_power) { + is_psd_power = true; + ath12k_mac_get_psd_channel(ar, 20, + &start_freq, + ¢er_freq, + pwr_lvl_idx, + &temp_chan, + &tx_power, + reg_6g_power_mode); + eirp_power = tx_power; + max_tx_power[pwr_lvl_idx] = + reg_tpc_info->tpe[pwr_lvl_idx]; + /* Connecting AP is not psd power */ + } else { + ath12k_mac_get_eirp_power(ar, + &start_freq, + ¢er_freq, + pwr_lvl_idx, + &temp_chan, + &ctx->def, + &tx_power, + reg_6g_power_mode); + max_tx_power[pwr_lvl_idx] = + min_t(s8, + tx_power, + reg_tpc_info->tpe[pwr_lvl_idx]); + } + } + /* STA not received TPE IE */ + } else { + /* local power is PSD power*/ + if (chan->flags & IEEE80211_CHAN_PSD) { + is_psd_power = true; + ath12k_mac_get_psd_channel(ar, 20, + &start_freq, + ¢er_freq, + pwr_lvl_idx, + &temp_chan, + &tx_power, + reg_6g_power_mode); + psd_power = temp_chan->psd; + eirp_power = tx_power; + max_tx_power[pwr_lvl_idx] = psd_power; + } else { + ath12k_mac_get_eirp_power(ar, + &start_freq, + ¢er_freq, + pwr_lvl_idx, + &temp_chan, + &ctx->def, + &tx_power, + reg_6g_power_mode); + max_tx_power[pwr_lvl_idx] = tx_power; + } + } + + if (is_psd_power) { + /* If AP local power constraint is present */ + if (pwr_reduction) + eirp_power = eirp_power - pwr_reduction; + + /* If FW updated max tx power is non zero, then take the min of + * firmware updated ap tx power + * and max power derived from above mentioned parameters. + */ + ath12k_dbg(ab, ATH12K_DBG_MAC, + "eirp power : %d firmware report power : %d\n", + eirp_power, ar->max_allowed_tx_power); + if ((ar->max_allowed_tx_power) && (ab->hw_params->idle_ps)) + eirp_power = min_t(s8, + eirp_power, + ar->max_allowed_tx_power); + } else { + /* If AP local power constraint is present */ + if (pwr_reduction) + max_tx_power[pwr_lvl_idx] = + max_tx_power[pwr_lvl_idx] - pwr_reduction; + /* If FW updated max tx power is non zero, then take the min of + * firmware updated ap tx power + * and max power derived from above mentioned parameters. + */ + if ((ar->max_allowed_tx_power) && (ab->hw_params->idle_ps)) + max_tx_power[pwr_lvl_idx] = + min_t(s8, + max_tx_power[pwr_lvl_idx], + ar->max_allowed_tx_power); + } + reg_tpc_info->chan_power_info[pwr_lvl_idx].chan_cfreq = center_freq; + reg_tpc_info->chan_power_info[pwr_lvl_idx].tx_power = + max_tx_power[pwr_lvl_idx]; + } + + reg_tpc_info->num_pwr_levels = num_pwr_levels; + reg_tpc_info->is_psd_power = is_psd_power; + reg_tpc_info->eirp_power = eirp_power; + reg_tpc_info->power_type_6g = + ath12k_ieee80211_ap_pwr_type_convert(reg_6g_power_mode); +} + +void ath12k_mac_parse_tx_pwr_env(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ieee80211_chanctx_conf *ctx) +{ + struct ath12k_base *ab = ar->ab; + struct ieee80211_bss_conf *bss_conf; + struct ieee80211_tx_pwr_env *single_tpe; + enum wmi_reg_6g_client_type client_type; + int i; + u8 pwr_count, pwr_interpret, pwr_category; + u8 psd_index = 0, non_psd_index = 0, local_tpe_count = 0, reg_tpe_count = 0; + bool use_local_tpe, non_psd_set = false, psd_set = false; + + rcu_read_lock(); + + bss_conf = ath12k_get_link_bss_conf(arvif); + + if (!bss_conf) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "unable to access bss link conf in tpc reg fill\n"); + return; + } + + client_type = WMI_REG_DEFAULT_CLIENT; + + for (i = 0; i < bss_conf->tx_pwr_env_num; i++) { + single_tpe = &bss_conf->tx_pwr_env[i]; + pwr_category = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_CATEGORY); + pwr_interpret = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_INTERPRET); + + if (pwr_category == client_type) { + if (pwr_interpret == IEEE80211_TPE_LOCAL_EIRP || + pwr_interpret == IEEE80211_TPE_LOCAL_EIRP_PSD) + local_tpe_count++; + else if (pwr_interpret == IEEE80211_TPE_REG_CLIENT_EIRP || + pwr_interpret == IEEE80211_TPE_REG_CLIENT_EIRP_PSD) + reg_tpe_count++; + } + } + + if (!reg_tpe_count && !local_tpe_count) { + rcu_read_unlock(); + ath12k_warn(ab, + "no transmit power envelope match client power type %d\n", + client_type); + return; + } else if (!reg_tpe_count) { + use_local_tpe = true; + } else { + use_local_tpe = false; + } + for (i = 0; i < bss_conf->tx_pwr_env_num; i++) { + single_tpe = &bss_conf->tx_pwr_env[i]; + pwr_category = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_CATEGORY); + pwr_interpret = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_INTERPRET); + + if (pwr_category != client_type) + continue; + + /* get local transmit power envelope */ + if (use_local_tpe) { + if (pwr_interpret == IEEE80211_TPE_LOCAL_EIRP) { + non_psd_index = i; + non_psd_set = true; + } else if (pwr_interpret == IEEE80211_TPE_LOCAL_EIRP_PSD) { + psd_index = i; + psd_set = true; + } + /* get regulatory transmit power envelope */ + } else { + if (pwr_interpret == IEEE80211_TPE_REG_CLIENT_EIRP) { + non_psd_index = i; + non_psd_set = true; + } else if (pwr_interpret == IEEE80211_TPE_REG_CLIENT_EIRP_PSD) { + psd_index = i; + psd_set = true; + } + } + } + + if (non_psd_set && !psd_set) { + single_tpe = &bss_conf->tx_pwr_env[non_psd_index]; + pwr_count = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_COUNT); + pwr_interpret = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_INTERPRET); + arvif->reg_tpc_info.is_psd_power = false; + arvif->reg_tpc_info.eirp_power = 0; + + arvif->reg_tpc_info.num_pwr_levels = + ath12k_mac_get_tpe_count(pwr_interpret, pwr_count); + for (i = 0; i < arvif->reg_tpc_info.num_pwr_levels; i++) { + ath12k_dbg(ab, ATH12K_DBG_MAC, + "non PSD power[%d] : %d\n", + i, single_tpe->tx_power[i]); + arvif->reg_tpc_info.tpe[i] = single_tpe->tx_power[i] / 2; + } + } + if (psd_set) { + single_tpe = &bss_conf->tx_pwr_env[psd_index]; + pwr_count = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_COUNT); + pwr_interpret = u8_get_bits(single_tpe->tx_power_info, + IEEE80211_TX_PWR_ENV_INFO_INTERPRET); + arvif->reg_tpc_info.is_psd_power = true; + + if (pwr_count == 0) { + ath12k_dbg(ab, ATH12K_DBG_MAC, + "TPE PSD power : %d\n", single_tpe->tx_power[0]); + arvif->reg_tpc_info.num_pwr_levels = + ath12k_mac_get_num_pwr_levels(&ctx->def); + for (i = 0; i < arvif->reg_tpc_info.num_pwr_levels; i++) + arvif->reg_tpc_info.tpe[i] = single_tpe->tx_power[0] / 2; + } else { + arvif->reg_tpc_info.num_pwr_levels = + ath12k_mac_get_tpe_count(pwr_interpret, pwr_count); + for (i = 0; i < arvif->reg_tpc_info.num_pwr_levels; i++) { + ath12k_dbg(ab, ATH12K_DBG_MAC, + "TPE PSD power[%d] : %d\n", + i, single_tpe->tx_power[i]); + arvif->reg_tpc_info.tpe[i] = single_tpe->tx_power[i] / 2; + } + } + } + rcu_read_unlock(); +} + static int ath12k_mac_op_assign_vif_chanctx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_bss_conf *link_conf, struct ieee80211_chanctx_conf *ctx) { - struct ath12k *ar = hw->priv; - struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar, *arvif_ar; + struct ath12k_base *ab; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + struct ieee80211_sta *sta; + struct ath12k_sta *ahsta; + struct ath12k_link_sta *arsta; int ret; struct ath12k_wmi_peer_create_arg param; + enum ieee80211_ap_reg_power power_type; + enum ieee80211_sta_state state, prev_state; + + u8 link_id = link_conf->link_id; + + if (!ctx) + return -EINVAL; + + mutex_lock(&ah->conf_mutex); + + arvif = ath12k_mac_assign_link_vif(ah, vif, link_id); + if (!arvif) { + ath12k_err(NULL, "unable to allocate link vif\n"); + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + if (!arvif->is_created) { + ar = ath12k_mac_assign_vif_to_vdev(hw, arvif, ctx); + if (!ar) { + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + }else if (vif->valid_links){ + ar = arvif->ar; + if (WARN_ON(!ar)) { + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + } else { + ar = ath12k_get_ar_by_ctx(hw, ctx); + if (!ar) { + ath12k_err(NULL, + "unable to determine device for the passed channel ctx\n"); + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + + /* TODO If vif is already assigned, but now the chan is different and belongs + * to a different ar, then delete the old vdev in different ar and create new + * This is not expected for MLO + */ + /* If VIF is created for ROC scan, stop and delete the scan vif + * before creating vdev for new connection + */ + if (ar != arvif->ar || (arvif->is_scan_vif)) { + if (!(arvif->is_scan_vif) && WARN_ON(arvif->is_started)) { + mutex_unlock(&ah->conf_mutex); + return -EBUSY; + } + + arvif_ar = arvif->ar; + if (!arvif_ar) { + mutex_unlock(&ah->conf_mutex); + ath12k_warn(NULL, "arvif_ar not found\n"); + return -EINVAL; + } + + mutex_lock(&arvif_ar->conf_mutex); + if (arvif->is_scan_vif && arvif->is_started) { + ret = ath12k_mac_vdev_stop(arvif); + if (ret) { + mutex_unlock(&arvif_ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + ath12k_warn(arvif_ar->ab, "failed to stop vdev %d: %d\n", + arvif->vdev_id, ret); + return -EINVAL; + } + arvif->is_started = false; + arvif->is_scan_vif = false; + } + + ret = ath12k_mac_vdev_delete(arvif_ar, arvif); + mutex_unlock(&arvif_ar->conf_mutex); + if (ret) + ath12k_warn(arvif_ar->ab, "unable to delete vdev %d\n", ret); + + mutex_lock(&ar->conf_mutex); + ret = ath12k_mac_vdev_create(ar, arvif); + if (ret) { + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + ath12k_warn(ar->ab, "unable to create vdev %d\n", ret); + return -EINVAL; + } + mutex_unlock(&ar->conf_mutex); + } + } + + ab = ar->ab; mutex_lock(&ar->conf_mutex); @@ -5819,10 +13442,28 @@ "mac chanctx assign ptr %pK vdev_id %i\n", ctx, arvif->vdev_id); + if (ar->supports_6ghz && ctx->def.chan->band == NL80211_BAND_6GHZ && + (ahvif->vdev_type == WMI_VDEV_TYPE_STA || + ahvif->vdev_type == WMI_VDEV_TYPE_AP)) { + power_type = link_conf->power_type; + ath12k_dbg(ab, ATH12K_DBG_MAC, "mac chanctx power type %d\n", + power_type); + if (power_type == IEEE80211_REG_UNSET_AP) + power_type = IEEE80211_REG_LPI_AP; + arvif->chanctx = *ctx; + /* TODO: Transmit Power Envelope specification for 320 is not + * available yet. Need to add TPE 320 support when spec is ready + */ + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA && + ctx->def.width != NL80211_CHAN_WIDTH_320) { + ath12k_mac_parse_tx_pwr_env(ar, arvif, ctx); + } + } + /* for some targets bss peer must be created before vdev_start */ if (ab->hw_params->vdev_start_delay && - arvif->vdev_type != WMI_VDEV_TYPE_AP && - arvif->vdev_type != WMI_VDEV_TYPE_MONITOR && + ahvif->vdev_type != WMI_VDEV_TYPE_AP && + ahvif->vdev_type != WMI_VDEV_TYPE_MONITOR && !ath12k_peer_exist_by_vdev_id(ab, arvif->vdev_id)) { memcpy(&arvif->chanctx, ctx, sizeof(*ctx)); ret = 0; @@ -5835,8 +13476,8 @@ } if (ab->hw_params->vdev_start_delay && - (arvif->vdev_type == WMI_VDEV_TYPE_AP || - arvif->vdev_type == WMI_VDEV_TYPE_MONITOR)) { + (ahvif->vdev_type == WMI_VDEV_TYPE_AP || + ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR)) { param.vdev_id = arvif->vdev_id; param.peer_type = WMI_PEER_TYPE_DEFAULT; param.peer_addr = ar->mac_addr; @@ -5849,7 +13490,33 @@ } } - if (arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { + if (!ab->hw_params->vdev_start_delay && + ahvif->vdev_type == WMI_VDEV_TYPE_STA && ahvif->chanctx_peer_del_done) { + rcu_read_lock(); + sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); + if (!sta) { + ath12k_warn(ar->ab, "failed to find station entry for bss vdev\n"); + rcu_read_unlock(); + goto out; + } + + ahsta = ath12k_sta_to_ahsta(sta); + arsta = &ahsta->deflink; + rcu_read_unlock(); + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + prev_state = arsta->state; + for (state = IEEE80211_STA_NOTEXIST; state < prev_state; + state++) + ath12k_mac_update_sta_state(ar->ah->hw, arvif->ahvif->vif, sta, + state, (state + 1)); + mutex_lock(&ah->conf_mutex); + mutex_lock(&ar->conf_mutex); + ahvif->chanctx_peer_del_done = false; + } + + if (ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { ret = ath12k_mac_monitor_start(ar); if (ret) goto out; @@ -5857,15 +13524,18 @@ goto out; } - ret = ath12k_mac_vdev_start(arvif, &ctx->def); + memcpy(&arvif->chanctx, ctx, sizeof(*ctx)); + + ret = ath12k_mac_vdev_start(arvif, &ctx->def, ctx->radar_enabled); if (ret) { ath12k_warn(ab, "failed to start vdev %i addr %pM on freq %d: %d\n", - arvif->vdev_id, vif->addr, + arvif->vdev_id, arvif->addr, ctx->def.chan->center_freq, ret); goto out; } - if (arvif->vdev_type != WMI_VDEV_TYPE_MONITOR && ar->monitor_vdev_created) + if (ahvif->vdev_type != WMI_VDEV_TYPE_MONITOR && + test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags)) ath12k_mac_monitor_start(ar); arvif->is_started = true; @@ -5874,45 +13544,165 @@ out: mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); return ret; } +struct ath12k_link_vif * +ath12k_mac_get_primary_arvif(struct ath12k *ar, + struct ath12k_vif *ahvif) +{ + struct ath12k_link_vif *arvif; + + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->ahvif != ahvif) + continue; + + if (arvif->assoc_link) + return arvif; + } + + return NULL; +} + +static void +ath12k_mac_get_ahvif_status(struct ath12k *ar, + struct ath12k_vif *ahvif, + int *out_started_count, + int *out_up_count, + int *out_pending_stop_count) +{ + struct ath12k_link_vif *arvif; + int started_count = 0; + int up_count = 0; + int pending_stop_count = 0; + + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->ahvif != ahvif) + continue; + + if (arvif->is_started) + started_count++; + + if (arvif->is_up) + up_count++; + + if (arvif->pending_stop) + pending_stop_count++; + } + + *out_started_count = started_count; + *out_up_count = up_count; + *out_pending_stop_count = pending_stop_count; +} + static void ath12k_mac_op_unassign_vif_chanctx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_bss_conf *link_conf, struct ieee80211_chanctx_conf *ctx) { - struct ath12k *ar = hw->priv; - struct ath12k_base *ab = ar->ab; - struct ath12k_vif *arvif = (void *)vif->drv_priv; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; + struct ath12k_link_vif *arvif; + struct ath12k_hw *ah = hw->priv; + struct ath12k_base *ab; + struct ath12k_peer *peer; + struct ath12k *ar; int ret; + bool is_pending_stop = false; + bool to_stop_primary = false; + u8 link_id = link_conf->link_id; + + mutex_lock(&ah->conf_mutex); + + arvif = ahvif->link[link_id]; + + if (!arvif) { + ath12k_err(NULL, + "unable to determine the assigned link vif on link id %d\n", + link_id); + mutex_unlock(&ah->conf_mutex); + return; + } + + ar = arvif->ar; + if (!ar) { + ath12k_err(NULL, + "unable to determine device to stop vdev during channel unassign\n"); + mutex_unlock(&ah->conf_mutex); + WARN_ON(1); + return; + } + ab = ar->ab; mutex_lock(&ar->conf_mutex); - ath12k_dbg(ab, ATH12K_DBG_MAC, + if (unlikely(test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))) + goto out; + + ath12k_dbg(ab, ATH12K_DBG_SET(MAC, L2), "mac chanctx unassign ptr %pK vdev_id %i\n", ctx, arvif->vdev_id); - WARN_ON(!arvif->is_started); + if (!arvif->is_started) + goto out; if (ab->hw_params->vdev_start_delay && - arvif->vdev_type == WMI_VDEV_TYPE_MONITOR && + ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR && ath12k_peer_find_by_addr(ab, ar->mac_addr)) ath12k_peer_delete(ar, arvif->vdev_id, ar->mac_addr); - if (arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { + if (ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) { ret = ath12k_mac_monitor_stop(ar); - if (ret) { + if (ret) + goto out; + + arvif->is_started = false; mutex_unlock(&ar->conf_mutex); - return; + ath12k_mac_remove_link_interface(hw, arvif); + goto unassign_exit; } - arvif->is_started = false; + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac unassign vif links map %lu vdev id %d addr %pM assoc_link %d\n", + ahvif->links_map, arvif->vdev_id, arvif->addr, arvif->assoc_link); + + /* The primary link should be stop vdev and delete peer as last one. */ + if (hweight16(ahvif->links_map) > 1 && + ab->hw_params->vdev_start_delay && + ahvif->vdev_type == WMI_VDEV_TYPE_STA) { + int started_count = 0; + int up_count = 0; + int pending_stop_count = 0; + + ath12k_mac_get_ahvif_status(ar, ahvif, &started_count, + &up_count, + &pending_stop_count); + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac unassign vif status started %d up %d pending stop %d\n", + started_count, up_count, pending_stop_count); + + if (arvif->assoc_link && started_count != 1) + is_pending_stop = true; + + if (pending_stop_count && started_count - pending_stop_count == 1) + to_stop_primary = true; + } + + if (is_pending_stop) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac skip pending stop vdev id %d addr %pM assoc_link %d\n", + arvif->vdev_id, arvif->addr, arvif->assoc_link); + arvif->pending_stop = true; mutex_unlock(&ar->conf_mutex); + return; } +stop_primary: + ath12k_bss_disassoc(ar, arvif, true); + ret = ath12k_mac_vdev_stop(arvif); if (ret) ath12k_warn(ab, "failed to stop vdev %i: %d\n", @@ -5920,15 +13710,62 @@ arvif->is_started = false; + peer = ath12k_peer_find_by_vdev_id(ab, arvif->vdev_id); + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA && peer) { + struct ieee80211_sta *sta; + unsigned int sta_link_id = 0xff; + + if (vif->valid_links) + sta = ieee80211_find_sta_by_link_addrs(hw, peer->addr, + NULL, &sta_link_id); + else + sta = ieee80211_find_sta_by_ifaddr(hw, peer->addr, NULL); + ath12k_dbg(ab, ATH12K_DBG_MAC, + "peer delete check links 0x%x vdev id %i peer %pM link id %d sta %pK\n", + vif->valid_links, arvif->vdev_id, + peer->addr, sta_link_id, sta); + + if ((ab->hw_params->vdev_start_delay && !sta && !peer->sta) || + !ab->hw_params->vdev_start_delay) { + ret = ath12k_peer_delete(ar, arvif->vdev_id, arvif->bssid); + if (ret) { + ath12k_warn(ar->ab, + "failed to delete peer %pM for vdev %d: %d\n", + arvif->bssid, arvif->vdev_id, ret); + } else { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac removed peer %pM vdev %d\n", + arvif->bssid, arvif->vdev_id); + ahvif->chanctx_peer_del_done = true; + } + } + } + if (ab->hw_params->vdev_start_delay && - arvif->vdev_type == WMI_VDEV_TYPE_MONITOR) + ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) ath12k_wmi_vdev_down(ar, arvif->vdev_id); - if (arvif->vdev_type != WMI_VDEV_TYPE_MONITOR && - ar->num_started_vdevs == 1 && ar->monitor_vdev_created) + if (ahvif->vdev_type != WMI_VDEV_TYPE_MONITOR && + ar->num_started_vdevs == 1 && + test_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags)) ath12k_mac_monitor_stop(ar); + if (to_stop_primary) { + to_stop_primary = false; + arvif = ath12k_mac_get_primary_arvif(ar, ahvif); + WARN_ON(!arvif); + link_id = arvif->link_id; + goto stop_primary; + } + + mutex_unlock(&ar->conf_mutex); + ath12k_mac_remove_link_interface(hw, arvif); + ath12k_mac_unassign_link_vif(arvif); + goto unassign_exit; +out: mutex_unlock(&ar->conf_mutex); +unassign_exit: + mutex_unlock(&ah->conf_mutex); } static int @@ -5937,24 +13774,88 @@ int n_vifs, enum ieee80211_chanctx_switch_mode mode) { - struct ath12k *ar = hw->priv; + struct ath12k_hw *ah = hw->priv; + struct ath12k *curr_ar, *new_ar, *ar; + struct ieee80211_chanctx_conf *prev_ctx, *curr_ctx; + int i, ret = 0, idx; + + mutex_lock(&ah->conf_mutex); + + /* TODO Switching a vif between two radios require deleting of vdev + * in its current ar and creating a vdev and applying its cached params + * to the new vdev in ar. So instead of returning error, handle it? + */ + for (i = 0; i < n_vifs; i++) { + if (vifs[i].old_ctx->def.chan->band != + vifs[i].new_ctx->def.chan->band) { + WARN_ON(1); + ret = -EINVAL; + break; + } - mutex_lock(&ar->conf_mutex); + curr_ar = ath12k_get_ar_by_ctx(hw, vifs[i].old_ctx); + new_ar = ath12k_get_ar_by_ctx(hw, vifs[i].new_ctx); + if (!curr_ar || !new_ar) { + ath12k_err(NULL, + "unable to determine device for the passed channel ctx"); + ath12k_err(NULL, + "Old freq %d MHz (device %s) to new freq %d MHz (device %s)\n", + vifs[i].old_ctx->def.chan->center_freq, + curr_ar ? "valid" : "invalid", + vifs[i].new_ctx->def.chan->center_freq, + new_ar ? "valid" : "invalid"); + ret = -EINVAL; + break; + } + /* Switching a vif between two radios is not allowed */ + if (curr_ar != new_ar) { + ath12k_dbg(curr_ar->ab, ATH12K_DBG_MAC, + "mac chanctx switch to another radio not supported."); + ret = -EOPNOTSUPP; + break; + } + } + + if (ret) + goto unlock; + + prev_ctx = vifs[0].old_ctx; + idx = 0; + + for (i = 1; i < n_vifs; i++) { + curr_ctx = vifs[i].old_ctx; + + if (curr_ctx != prev_ctx) { + ar = ath12k_get_ar_by_ctx(hw, prev_ctx); + mutex_lock(&ar->conf_mutex); ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac chanctx switch n_vifs %d mode %d\n", - n_vifs, mode); - ath12k_mac_update_vif_chan(ar, vifs, n_vifs); + i - idx, mode); + ath12k_mac_process_update_vif_chan(ar, vifs + idx, i - idx); + mutex_unlock(&ar->conf_mutex); + prev_ctx = curr_ctx; + idx = i; + } + } + ar = ath12k_get_ar_by_ctx(hw, prev_ctx); + mutex_lock(&ar->conf_mutex); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac chanctx switch n_vifs %d mode %d\n", + i - idx, mode); + ath12k_mac_process_update_vif_chan(ar, vifs + idx, i - idx); mutex_unlock(&ar->conf_mutex); - return 0; +unlock: + mutex_unlock(&ah->conf_mutex); + return ret; } -static int +int ath12k_set_vdev_param_to_all_vifs(struct ath12k *ar, int param, u32 value) { - struct ath12k_vif *arvif; + struct ath12k_link_vif *arvif; int ret = 0; mutex_lock(&ar->conf_mutex); @@ -5976,13 +13877,58 @@ /* mac80211 stores device specific RTS/Fragmentation threshold value, * this is set interface specific to firmware from ath12k driver + * TODO Move to link specific config */ -static int ath12k_mac_op_set_rts_threshold(struct ieee80211_hw *hw, u32 value) +static int ath12k_mac_op_set_rts_threshold(struct ieee80211_hw *hw, u32 value /*, */ + /* struct ieee80211_vif *vif, int link_id */) { - struct ath12k *ar = hw->priv; + u8 link_id = 0; + struct ieee80211_vif *vif = NULL; + struct ath12k_hw *ah = hw->priv; + struct ath12k_vif *ahvif; + struct ath12k *ar; + struct ath12k_link_vif *arvif; + int ret = -1; int param_id = WMI_VDEV_PARAM_RTS_THRESHOLD; - return ath12k_set_vdev_param_to_all_vifs(ar, param_id, value); + if (vif) { + mutex_lock(&ah->conf_mutex); + ahvif = ath12k_vif_to_ahvif(vif); + arvif = ahvif->link[link_id]; + + if (arvif == NULL || !arvif->is_created) { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "bss info parameter changes %d cached to apply after vdev create on channel assign\n", + param_id); + mutex_unlock(&ah->conf_mutex); + return ret; + } + + ar = arvif->ar; + if (!ar) { + ath12k_err(NULL, + "Failed to set rts threshold for link: %d\n", + link_id); + mutex_unlock(&ah->conf_mutex); + return ret; + } + + ret = ath12k_set_vdev_param_to_all_vifs(ar, param_id, value); + if (ret) { + ath12k_warn(ar->ab, "failed to set RTS config for all vdevs of pdev %d", + ar->pdev->pdev_id); + } + + mutex_unlock(&ah->conf_mutex); + } else { + ar = ah->radio; + ret = ath12k_set_vdev_param_to_all_vifs(ar, param_id, value); + if (ret) { + ath12k_warn(ar->ab, "failed to set RTS config for all vdevs of pdev %d", + ar->pdev->pdev_id); + } + } + return ret; } static int ath12k_mac_op_set_frag_threshold(struct ieee80211_hw *hw, u32 value) @@ -6000,34 +13946,75 @@ return -EOPNOTSUPP; } -static void ath12k_mac_op_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, - u32 queues, bool drop) +static void ath12k_mac_flush(struct ath12k *ar) { - struct ath12k *ar = hw->priv; + struct ath12k_base *ab = ar->ab; long time_left; - if (drop) + atomic_inc(&ar->flush_request); + time_left = wait_event_timeout(ar->tx_empty_waitq, + ((atomic_read(&ar->dp.num_tx_pending) == 0) && + (atomic_read(&ar->num_pending_mgmt_tx) == 0)), + ATH12K_FLUSH_TIMEOUT); + atomic_dec(&ar->flush_request); + + if (time_left == 0) { + ath12k_warn(ab, "failed to flush transmit queue pending mgmt %d data %d\n", + atomic_read(&ar->num_pending_mgmt_tx), + atomic_read(&ar->dp.num_tx_pending)); return; + } - time_left = wait_event_timeout(ar->dp.tx_empty_waitq, - (atomic_read(&ar->dp.num_tx_pending) == 0), - ATH12K_FLUSH_TIMEOUT); - if (time_left == 0) - ath12k_warn(ar->ab, "failed to flush transmit queue %ld\n", time_left); + ath12k_dbg(ab, ATH12K_DBG_SET(MAC, L3), + "mac tx flush pending mgmt %d data %d\n", + atomic_read(&ar->num_pending_mgmt_tx), + atomic_read(&ar->dp.num_tx_pending)); } -static int -ath12k_mac_bitrate_mask_num_ht_rates(struct ath12k *ar, - enum nl80211_band band, - const struct cfg80211_bitrate_mask *mask) +static void ath12k_mac_op_flush_sta(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_sta *sta) { - int num_rates = 0; + /* There is no station specific queue, No need to do anything here */ +} + +static void ath12k_mac_op_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u32 queues, bool drop) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_vif *ahvif; int i; + u8 link_id; - for (i = 0; i < ARRAY_SIZE(mask->control[band].ht_mcs); i++) - num_rates += hweight16(mask->control[band].ht_mcs[i]); + if (drop) + return; - return num_rates; + if (!vif) { + /* FIXME: Need to identify which radio to flush. + * Until flush all the device if vif NULL + */ + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { + ath12k_mac_flush(ar); + ar++; + } + } else { + ahvif = (void *)vif->drv_priv; + + for_each_set_bit(link_id, &ahvif->links_map, ATH12K_NUM_MAX_LINKS) { + if (!ahvif->link[link_id]) + continue; + + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + if (!ar) { + ath12k_err(NULL, + "unable to determine device for link_id %d tx flush\n", + link_id); + continue; + } + ath12k_mac_flush(ar); + } + } } static bool @@ -6045,9 +14032,29 @@ if (ath12k_mac_bitrate_mask_num_vht_rates(ar, band, mask)) return false; + if (ath12k_mac_bitrate_mask_num_he_rates(ar, band, mask)) + return false; + + if (ath12k_mac_bitrate_mask_num_eht_rates(ar, band, mask)) + return false; + return num_rates == 1; } +static __le16 +ath12k_mac_get_tx_mcs_map(const struct ieee80211_sta_he_cap *he_cap) +{ + if (he_cap->he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) + return he_cap->he_mcs_nss_supp.tx_mcs_80p80; + + if (he_cap->he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G) + return he_cap->he_mcs_nss_supp.tx_mcs_160; + + return he_cap->he_mcs_nss_supp.tx_mcs_80; +} + static bool ath12k_mac_bitrate_mask_get_single_nss(struct ath12k *ar, enum nl80211_band band, @@ -6056,8 +14063,13 @@ { struct ieee80211_supported_band *sband = &ar->mac.sbands[band]; u16 vht_mcs_map = le16_to_cpu(sband->vht_cap.vht_mcs.tx_mcs_map); + u16 he_mcs_map = 0; + u16 eht_mcs_map = 0; u8 ht_nss_mask = 0; u8 vht_nss_mask = 0; + u8 he_nss_mask = 0; + u8 eht_nss_mask = 0; + u8 mcs_nss_len; int i; /* No need to consider legacy here. Basic rates are always present @@ -6084,7 +14096,71 @@ return false; } - if (ht_nss_mask != vht_nss_mask) + he_mcs_map = le16_to_cpu(ath12k_mac_get_tx_mcs_map(&sband->iftype_data->he_cap)); + + for (i = 0; i < ARRAY_SIZE(mask->control[band].he_mcs); i++) { + if (mask->control[band].he_mcs[i] == 0) + continue; + + if (mask->control[band].he_mcs[i] == + ath12k_mac_get_max_he_mcs_map(he_mcs_map, i)) + he_nss_mask |= BIT(i); + else + return false; + } + + mcs_nss_len = ieee80211_eht_mcs_nss_size(&sband->iftype_data->he_cap.he_cap_elem, + &sband->iftype_data->eht_cap.eht_cap_elem, + false); + if (mcs_nss_len == 4) { + /* 20 MHz only STA case */ + const struct ieee80211_eht_mcs_nss_supp_20mhz_only *eht_mcs_nss = + &sband->iftype_data->eht_cap.eht_mcs_nss_supp.only_20mhz; + if (eht_mcs_nss->rx_tx_mcs13_max_nss) + eht_mcs_map = 0x1fff; + else if (eht_mcs_nss->rx_tx_mcs11_max_nss) + eht_mcs_map = 0x07ff; + else if (eht_mcs_nss->rx_tx_mcs9_max_nss) + eht_mcs_map = 0x01ff; + else + eht_mcs_map = 0x007f; + } else { + const struct ieee80211_eht_mcs_nss_supp_bw *eht_mcs_nss; + + switch (mcs_nss_len) { + case 9: + eht_mcs_nss = &sband->iftype_data->eht_cap.eht_mcs_nss_supp.bw._320; + break; + case 6: + eht_mcs_nss = &sband->iftype_data->eht_cap.eht_mcs_nss_supp.bw._160; + break; + case 3: + eht_mcs_nss = &sband->iftype_data->eht_cap.eht_mcs_nss_supp.bw._80; + break; + default: + return false; + } + + if (eht_mcs_nss->rx_tx_mcs13_max_nss) + eht_mcs_map = 0x1fff; + else if (eht_mcs_nss->rx_tx_mcs11_max_nss) + eht_mcs_map = 0x7ff; + else + eht_mcs_map = 0x1ff; + } + + for (i = 0; i < ARRAY_SIZE(mask->control[band].eht_mcs); i++) { + if (mask->control[band].eht_mcs[i] == 0) + continue; + + if (mask->control[band].eht_mcs[i] < eht_mcs_map) + eht_nss_mask |= BIT(i); + else + return false; + } + + if (ht_nss_mask != vht_nss_mask || ht_nss_mask != he_nss_mask || + ht_nss_mask != eht_nss_mask) return false; if (ht_nss_mask == 0) @@ -6131,18 +14207,157 @@ return 0; } -static int ath12k_mac_set_fixed_rate_params(struct ath12k_vif *arvif, - u32 rate, u8 nss, u8 sgi, u8 ldpc) +static int +ath12k_mac_set_fixed_rate_GI_LTF(struct ath12k_link_vif *arvif, u8 gi, u8 ltf) +{ + struct ieee80211_bss_conf *link_conf; + struct ath12k *ar = arvif->ar; + int param, ret; + bool eht_support; + + /* 0.8 = 0, 1.6 = 2 and 3.2 = 3. */ + if (gi && gi != 0xFF) + gi += 1; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + return -EINVAL; + } + + eht_support = link_conf->eht_support; + + rcu_read_unlock(); + + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, + WMI_VDEV_PARAM_SGI, gi); + if (ret) { + ath12k_warn(ar->ab, "failed to set HE GI:%d, error:%d\n", + gi, ret); + return ret; + } + /* start from 1 */ + if (ltf != 0xFF) + ltf += 1; + + if (eht_support) + param = WMI_VDEV_PARAM_EHT_LTF; + else + param = WMI_VDEV_PARAM_HE_LTF; + + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, + param, ltf); + if (ret) { + ath12k_warn(ar->ab, "failed to set HE LTF:%d, error:%d\n", + ltf, ret); + return ret; + } + + return 0; +} + +static int +ath12k_mac_set_auto_rate_GI_LTF(struct ath12k_link_vif *arvif, u16 gi, u8 ltf) { struct ath12k *ar = arvif->ar; - u32 vdev_param; int ret; + u32 ar_gi_ltf = 0; + + if (gi != 0xFF) { + switch (gi) { + case NL80211_RATE_INFO_HE_GI_0_8: + gi = WMI_AUTORATE_800NS_GI; + break; + case NL80211_RATE_INFO_HE_GI_1_6: + gi = WMI_AUTORATE_1600NS_GI; + break; + case NL80211_RATE_INFO_HE_GI_3_2: + gi = WMI_AUTORATE_3200NS_GI; + break; + default: + ath12k_warn(ar->ab, "Invalid GI\n"); + return -EINVAL; + } + } + + if (ltf != 0xFF) { + switch (ltf) { + case NL80211_RATE_INFO_HE_1XLTF: + ltf = WMI_HE_AUTORATE_LTF_1X; + break; + case NL80211_RATE_INFO_HE_2XLTF: + ltf = WMI_HE_AUTORATE_LTF_2X; + break; + case NL80211_RATE_INFO_HE_4XLTF: + ltf = WMI_HE_AUTORATE_LTF_4X; + break; + default: + ath12k_warn(ar->ab, "Invalid LTF\n"); + return -EINVAL; + } + } + + ar_gi_ltf = gi | ltf; + + + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, + WMI_VDEV_PARAM_AUTORATE_MISC_CFG, + ar_gi_ltf); + if (ret) { + ath12k_warn(ar->ab, + "failed to set HE autorate GI:%u, LTF:%u params, error:%d\n", + gi, ltf, ret); + return ret; + } + + return 0; +} + +static int ath12k_mac_set_rate_params(struct ath12k_link_vif *arvif, + u32 rate, u8 nss, u8 sgi, u8 ldpc, + u8 he_gi, u8 he_ltf, bool he_fixed_rate, + u8 eht_gi, u8 eht_ltf, + bool eht_fixed_rate, + int he_ul_rate, u8 he_ul_nss) +{ + struct ieee80211_bss_conf *link_conf; + struct ath12k *ar = arvif->ar; + u32 vdev_param, rate_code; + int ret; + bool he_support, eht_support; lockdep_assert_held(&ar->conf_mutex); - ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac set fixed rate params vdev %i rate 0x%02x nss %u sgi %u\n", - arvif->vdev_id, rate, nss, sgi); + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + rcu_read_unlock(); + return -EINVAL; + } + + eht_support = link_conf->eht_support; + he_support = link_conf->he_support; + rcu_read_unlock(); + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "mac set rate params vdev %i, rate:0x%02x, nss:0x%02x, sgi:0x%02x, ldpc:0x%02x\n", + arvif->vdev_id, rate, nss, sgi, ldpc); + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "he_gi:0x%02x, he_ltf:0x%02x, he_fixed_rate:%d\n", he_gi, + he_ltf, he_fixed_rate); + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "eht_gi:0x%02x, eht_ltf:0x%02x, eht_fixed_rate:%d\n", eht_gi, + eht_ltf, eht_fixed_rate); + + if (!he_support || !eht_support) { vdev_param = WMI_VDEV_PARAM_FIXED_RATE; ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, vdev_param, rate); @@ -6151,8 +14366,10 @@ rate, ret); return ret; } + } vdev_param = WMI_VDEV_PARAM_NSS; + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, vdev_param, nss); if (ret) { @@ -6161,6 +14378,35 @@ return ret; } + ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, + WMI_VDEV_PARAM_LDPC, ldpc); + if (ret) { + ath12k_warn(ar->ab, "failed to set ldpc param %d: %d\n", + ldpc, ret); + return ret; + } + + if (eht_support) { + if (eht_fixed_rate) { + ret = ath12k_mac_set_fixed_rate_GI_LTF(arvif, eht_gi, + eht_ltf); + } else { + ret = ath12k_mac_set_auto_rate_GI_LTF(arvif, eht_gi, + eht_ltf); + } + if (ret) + return ret; + } else if (he_support) { + if (he_fixed_rate) { + ret = ath12k_mac_set_fixed_rate_GI_LTF(arvif, he_gi, + he_ltf); + } else { + ret = ath12k_mac_set_auto_rate_GI_LTF(arvif, he_gi, + he_ltf); + } + if (ret) + return ret; + } else { vdev_param = WMI_VDEV_PARAM_SGI; ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, vdev_param, sgi); @@ -6169,14 +14415,21 @@ sgi, ret); return ret; } + } - vdev_param = WMI_VDEV_PARAM_LDPC; + if ((he_ul_rate < 0) || !he_ul_nss) + return 0; + + rate_code = ATH12K_HW_RATE_CODE(he_ul_rate, he_ul_nss - 1, + WMI_RATE_PREAMBLE_HE); + + vdev_param = WMI_VDEV_PARAM_UL_FIXED_RATE; ret = ath12k_wmi_vdev_set_param_cmd(ar, arvif->vdev_id, - vdev_param, ldpc); + vdev_param, rate_code); + if (ret) { - ath12k_warn(ar->ab, "failed to set ldpc param %d: %d\n", - ldpc, ret); - return ret; + ath12k_warn(ar->ab, "failed to set HE UL Fixed Rate:%d, error:%d\n", + he_ul_rate, ret); } return 0; @@ -6207,67 +14460,371 @@ return true; } +static bool +ath12k_mac_he_mcs_range_present(struct ath12k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +{ + int i; + u16 he_mcs; + + for (i = 0; i < NL80211_HE_NSS_MAX; i++) { + he_mcs = mask->control[band].he_mcs[i]; + + switch (he_mcs) { + case 0: + case BIT(8) - 1: + case BIT(10) - 1: + case BIT(12) - 1: + break; + default: + return false; + } + } + + return true; +} + +static bool +ath12k_mac_he_ul_mcs_present(struct ath12k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +{ + int i; + + for (i = 0; i < NL80211_HE_NSS_MAX; i++) { + if (mask->control[band].he_ul_mcs[i]) + return true; + } + + return false; +} + +static bool +ath12k_mac_eht_mcs_range_present(struct ath12k *ar, + enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask) +{ + int i; + u16 eht_mcs; + + for (i = 0; i < NL80211_EHT_NSS_MAX; i++) { + eht_mcs = mask->control[band].eht_mcs[i]; + + switch (eht_mcs) { + case 0: + case BIT(8) - 1: + case BIT(10) - 1: + case BIT(12) - 1: + case BIT(14) - 1: + break; + case BIT(15) - 1: + case BIT(16) - 1: + case BIT(16) - BIT(14) - 1: + if (i != 0) + return false; + break; + default: + return false; + } + } + + return true; +} + static void ath12k_mac_set_bitrate_mask_iter(void *data, struct ieee80211_sta *sta) { - struct ath12k_vif *arvif = data; - struct ath12k_sta *arsta = (struct ath12k_sta *)sta->drv_priv; + struct ath12k_link_vif *arvif = data; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta; struct ath12k *ar = arvif->ar; + u8 link_id = arvif->link_id; + + if (ahsta->ahvif != arvif->ahvif) + return; + + /* Check if there is a link sta in the vif link */ + if (!(BIT(link_id) & ahsta->links_map)) + return; + + arsta = ahsta->link[link_id]; spin_lock_bh(&ar->data_lock); arsta->changed |= IEEE80211_RC_SUPP_RATES_CHANGED; spin_unlock_bh(&ar->data_lock); - ieee80211_queue_work(ar->hw, &arsta->update_wk); + ieee80211_queue_work(ar->ah->hw, &arsta->update_wk); } static void ath12k_mac_disable_peer_fixed_rate(void *data, struct ieee80211_sta *sta) { - struct ath12k_vif *arvif = data; + struct ath12k_link_sta *arsta; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_vif *arvif = data; + struct ath12k *ar; + u8 link_id = arvif->link_id; + + if (ahsta->ahvif != arvif->ahvif) + return; + + /* Check if there is a link sta in the vif link */ + if (!(BIT(link_id) & ahsta->links_map)) + return; + + arsta = ahsta->link[link_id]; + + ar = arvif->ar; + + spin_lock_bh(&ar->data_lock); + arsta->disable_fixed_rate = true; + spin_unlock_bh(&ar->data_lock); + + ieee80211_queue_work(ar->ah->hw, &arsta->update_wk); +} + +static bool +ath12k_mac_validate_fixed_rate_settings(struct ath12k *ar, enum nl80211_band band, + const struct cfg80211_bitrate_mask *mask, + unsigned int link_id) +{ + bool eht_fixed_rate = false, he_fixed_rate = false, vht_fixed_rate = false; + bool he_ul_fixed_rate = false; + struct ath12k_peer *peer, *tmp; + const u16 *vht_mcs_mask, *he_mcs_mask, *eht_mcs_mask, *he_ul_mcs_mask; + u8 vht_nss, he_nss, eht_nss, he_ul_nss; + bool ret = true; + struct ieee80211_link_sta *link_sta; + + vht_mcs_mask = mask->control[band].vht_mcs; + he_mcs_mask = mask->control[band].he_mcs; + eht_mcs_mask = mask->control[band].eht_mcs; + he_ul_mcs_mask = mask->control[band].he_ul_mcs; + + if (ath12k_mac_bitrate_mask_num_vht_rates(ar, band, mask) == 1) + vht_fixed_rate = true; + + if (ath12k_mac_bitrate_mask_num_he_rates(ar, band, mask) == 1) + he_fixed_rate = true; + + if (ath12k_mac_bitrate_mask_num_eht_rates(ar, band, mask) == 1) + eht_fixed_rate = true; + + if (ath12k_mac_bitrate_mask_num_he_ul_rates(ar, band, mask) == 1) + he_ul_fixed_rate = true; + + if (!vht_fixed_rate && !he_fixed_rate && !eht_fixed_rate && !he_ul_fixed_rate) + return true; + + vht_nss = ath12k_mac_max_vht_nss(vht_mcs_mask); + he_nss = ath12k_mac_max_he_nss(he_mcs_mask); + eht_nss = ath12k_mac_max_eht_nss(eht_mcs_mask); + he_ul_nss = ath12k_mac_max_he_nss(he_ul_mcs_mask); + + rcu_read_lock(); + spin_lock_bh(&ar->ab->base_lock); + list_for_each_entry_safe(peer, tmp, &ar->ab->peers, list) { + if (peer->sta) { + link_sta = rcu_dereference(peer->sta->link[link_id]); + + if (!link_sta) { + ret = false; + goto exit; + } + + if (vht_fixed_rate && (!link_sta->vht_cap.vht_supported || + link_sta->rx_nss < vht_nss)) { + ret = false; + goto exit; + } + if (he_fixed_rate && (!link_sta->he_cap.has_he || + link_sta->rx_nss < he_nss)) { + ret = false; + goto exit; + } + if (eht_fixed_rate && (!link_sta->eht_cap.has_eht || + link_sta->rx_nss < eht_nss)) { + ret = false; + goto exit; + } + /* TODO: + * check when UL is valid + */ + if (he_ul_fixed_rate && (!link_sta->he_cap.has_he || + link_sta->rx_nss < he_ul_nss)) { + ret = false; + goto exit; + } + } + } +exit: + spin_unlock_bh(&ar->ab->base_lock); + rcu_read_unlock(); + return ret; +} + +static bool +ath12k_mac_check_fixed_rate_settings_for_mumimo(struct ath12k_link_vif *arvif, + const u16 *vht_mcs_mask, + const u16 *he_mcs_mask) +{ struct ath12k *ar = arvif->ar; - int ret; + struct ieee80211_he_cap_elem he_cap_elem = {0}; + int nss_idx; + int he_nss; + int vht_nss; - ret = ath12k_wmi_set_peer_param(ar, sta->addr, - arvif->vdev_id, - WMI_PEER_PARAM_FIXED_RATE, - WMI_FIXED_RATE_NONE); - if (ret) - ath12k_warn(ar->ab, - "failed to disable peer fixed rate for STA %pM ret %d\n", - sta->addr, ret); + struct ieee80211_bss_conf *link_conf; + + rcu_read_lock(); + + link_conf = rcu_dereference(arvif->ahvif->vif->link_conf[arvif->link_id]); + + if (!link_conf) { + rcu_read_unlock(); + return -EINVAL; + } + + vht_nss = ath12k_mac_max_vht_nss(vht_mcs_mask); + + if (vht_nss != 1) { + for (nss_idx = vht_nss-1; nss_idx >= 0; nss_idx--) { + if (vht_mcs_mask[nss_idx]) + continue; + + if (arvif->vht_cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "vht fixed NSS rate is allowed only when MU MIMO is disabled\n"); + return false; + } + } + } + + if (!link_conf->he_support) { + rcu_read_unlock(); + return true; + } + + he_nss = ath12k_mac_max_he_nss(he_mcs_mask); + + + if (he_nss == 1) { + rcu_read_unlock(); + return true; + } + + for (nss_idx = he_nss-1; nss_idx >= 0; nss_idx--) { + if (he_mcs_mask[nss_idx]) + continue; + + if ((he_cap_elem.phy_cap_info[2] & IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO) || + (he_cap_elem.phy_cap_info[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { + rcu_read_unlock(); + ath12k_warn(ar->ab, "he fixed NSS rate is allowed only when MU MIMO is disabled\n"); + return false; + + } + } + rcu_read_unlock(); + return true; } static int ath12k_mac_op_set_bitrate_mask(struct ieee80211_hw *hw, - struct ieee80211_vif *vif, + struct ieee80211_vif *vif, /* unsigned int link_id, */ const struct cfg80211_bitrate_mask *mask) { - struct ath12k_vif *arvif = (void *)vif->drv_priv; + unsigned int link_id = 0; + struct ath12k_hw *ah = hw->priv; + struct ath12k_vif *ahvif = (void *)vif->drv_priv; struct cfg80211_chan_def def; - struct ath12k *ar = arvif->ar; + struct ath12k *ar; enum nl80211_band band; const u8 *ht_mcs_mask; const u16 *vht_mcs_mask; + const u16 *he_mcs_mask; + const u16 *eht_mcs_mask; + const u16 *he_ul_mcs_mask; + u8 he_ltf = 0; + u8 he_gi = 0; + u8 eht_ltf = 0; + u8 eht_gi = 0; u32 rate; - u8 nss; + u8 nss, he_ul_nss = 0; u8 sgi; u8 ldpc; int single_nss; - int ret; + int ret, i; int num_rates; + int he_ul_rate = -1; + bool he_fixed_rate = false; + bool eht_fixed_rate = false; + struct ath12k_link_vif *arvif; - if (ath12k_mac_vif_chan(vif, &def)) + if (ath12k_mac_vif_chan(vif, &def, link_id)) return -EPERM; + mutex_lock(&ah->conf_mutex); + + arvif = ahvif->link[link_id]; + + if (!arvif) { + ret = -EINVAL; + goto out; + } + + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + if (!ar) { + ath12k_err(NULL, + "unable to determine device to set bitrates, configs can be applied after device bringup\n"); + ret = -EPERM; + goto out; + } + band = def.chan->band; ht_mcs_mask = mask->control[band].ht_mcs; vht_mcs_mask = mask->control[band].vht_mcs; + he_mcs_mask = mask->control[band].he_mcs; + he_ul_mcs_mask = mask->control[band].he_ul_mcs; + eht_mcs_mask = mask->control[band].eht_mcs; ldpc = !!(ar->ht_cap_info & WMI_HT_CAP_LDPC); + if (vif->valid_links && ath12k_peer_assoc_h_eht_masked(eht_mcs_mask)) { + ath12k_warn(ar->ab, "cannot disable EHT rates on a ML bss\n"); + ret = -EINVAL; + goto out; + } + sgi = mask->control[band].gi; - if (sgi == NL80211_TXRATE_FORCE_LGI) - return -EINVAL; + if (sgi == NL80211_TXRATE_FORCE_LGI) { + ret = -EINVAL; + goto out; + } + + he_gi = mask->control[band].he_gi; + he_ltf = mask->control[band].he_ltf; + + eht_gi = 0xFF; + eht_ltf = 0xFF; + + for (i = 0; i < ARRAY_SIZE(mask->control[band].he_ul_mcs); i++) { + if (hweight16(mask->control[band].he_ul_mcs[i]) == 1) { + he_ul_nss = i + 1; + he_ul_rate = ffs((int) + mask->control[band].he_ul_mcs[i]) - 1; + break; + } + } + num_rates = ath12k_mac_bitrate_mask_num_he_ul_rates(ar, band, + mask); + if (ath12k_mac_he_ul_mcs_present(ar, band, mask) && + num_rates != 1) { + ath12k_warn(ar->ab, + "Setting HE UL MCS Fixed Rate range is not supported\n"); + ret = -EINVAL; + goto out; + } /* mac80211 doesn't support sending a fixed HT/VHT MCS alone, rather it * requires passing at least one of used basic rates along with them. @@ -6283,20 +14840,37 @@ if (ret) { ath12k_warn(ar->ab, "failed to get single legacy rate for vdev %i: %d\n", arvif->vdev_id, ret); - return ret; + goto out; } - ieee80211_iterate_stations_atomic(ar->hw, + ieee80211_iterate_stations_atomic(hw, ath12k_mac_disable_peer_fixed_rate, arvif); } else if (ath12k_mac_bitrate_mask_get_single_nss(ar, band, mask, &single_nss)) { rate = WMI_FIXED_RATE_NONE; nss = single_nss; + mutex_lock(&ar->conf_mutex); + arvif->bitrate_mask = *mask; + ieee80211_iterate_stations_atomic(hw, + ath12k_mac_set_bitrate_mask_iter, + arvif); + mutex_unlock(&ar->conf_mutex); } else { rate = WMI_FIXED_RATE_NONE; + + if (!ath12k_mac_check_fixed_rate_settings_for_mumimo(arvif, vht_mcs_mask, he_mcs_mask)) { + ret = -EINVAL; + goto out; + } + + if (!ath12k_mac_validate_fixed_rate_settings(ar, band, mask, link_id)) + ath12k_warn(ar->ab, + "could not update fixed rate settings to all peers due to mcs/nss incompaitiblity\n"); nss = min_t(u32, ar->num_tx_chains, - max(ath12k_mac_max_ht_nss(ht_mcs_mask), - ath12k_mac_max_vht_nss(vht_mcs_mask))); + max(max(max(ath12k_mac_max_ht_nss(ht_mcs_mask), + ath12k_mac_max_vht_nss(vht_mcs_mask)), + ath12k_mac_max_he_nss(he_mcs_mask)), + ath12k_mac_max_eht_nss(eht_mcs_mask))); /* If multiple rates across different preambles are given * we can reconfigure this info with all peers using PEER_ASSOC @@ -6328,17 +14902,43 @@ */ ath12k_warn(ar->ab, "Setting more than one MCS Value in bitrate mask not supported\n"); - return -EINVAL; + ret = -EINVAL; + goto out; } - ieee80211_iterate_stations_atomic(ar->hw, - ath12k_mac_disable_peer_fixed_rate, - arvif); + num_rates = ath12k_mac_bitrate_mask_num_he_rates(ar, band, + mask); + if (num_rates == 1) + he_fixed_rate = true; + + if (!ath12k_mac_he_mcs_range_present(ar, band, mask) && + num_rates > 1) { + ath12k_warn(ar->ab, + "Setting more than one HE MCS Value in bitrate mask not supported\n"); + ret = -EINVAL; + goto out; + } + + num_rates = ath12k_mac_bitrate_mask_num_eht_rates(ar, band, + mask); + if (num_rates == 1) + eht_fixed_rate = true; + + if (!ath12k_mac_eht_mcs_range_present(ar, band, mask) && + num_rates > 1) { + ath12k_warn(ar->ab, + "Setting more than one EHT MCS Value in bitrate mask not supported\n"); + ret =-EINVAL; + goto out; + } mutex_lock(&ar->conf_mutex); + ieee80211_iterate_stations_atomic(hw, + ath12k_mac_disable_peer_fixed_rate, + arvif); arvif->bitrate_mask = *mask; - ieee80211_iterate_stations_atomic(ar->hw, + ieee80211_iterate_stations_atomic(hw, ath12k_mac_set_bitrate_mask_iter, arvif); @@ -6347,56 +14947,119 @@ mutex_lock(&ar->conf_mutex); - ret = ath12k_mac_set_fixed_rate_params(arvif, rate, nss, sgi, ldpc); + ret = ath12k_mac_set_rate_params(arvif, rate, nss, sgi, ldpc, he_gi, + he_ltf, he_fixed_rate, eht_gi, eht_ltf, + eht_fixed_rate, he_ul_rate, he_ul_nss); if (ret) { ath12k_warn(ar->ab, "failed to set fixed rate params on vdev %i: %d\n", arvif->vdev_id, ret); } mutex_unlock(&ar->conf_mutex); - +out: + mutex_unlock(&ah->conf_mutex); return ret; } -static void -ath12k_mac_op_reconfig_complete(struct ieee80211_hw *hw, - enum ieee80211_reconfig_type reconfig_type) +static void ath12k_mac_sta_hw_restart_disconnect(struct ath12k *ar) { - struct ath12k *ar = hw->priv; - struct ath12k_base *ab = ar->ab; - int recovery_count; + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif; - if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART) - return; + list_for_each_entry(arvif, &ar->arvifs, list) { + ahvif = arvif->ahvif; + if (ahvif->vdev_type == WMI_VDEV_TYPE_STA) + ieee80211_hw_restart_disconnect(ahvif->vif); + } +} + +static void ath12k_mac_reconfig_completion(struct ath12k *ar, + u8 *restart_count) +{ + u8 recovery_count; mutex_lock(&ar->conf_mutex); if (ar->state == ATH12K_STATE_RESTARTED) { + if (ar->ab->ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE0) + ath12k_mac_sta_hw_restart_disconnect(ar); ath12k_warn(ar->ab, "pdev %d successfully recovered\n", ar->pdev->pdev_id); ar->state = ATH12K_STATE_ON; - ieee80211_wake_queues(ar->hw); + *restart_count += 1; + } - if (ab->is_reset) { - recovery_count = atomic_inc_return(&ab->recovery_count); - ath12k_dbg(ab, ATH12K_DBG_BOOT, "recovery count %d\n", - recovery_count); + if (ar->ab->is_reset) { + recovery_count = atomic_inc_return(&ar->ab->recovery_count); + ath12k_dbg(ar->ab, ATH12K_DBG_BOOT, + "recovery count %d\n", recovery_count); /* When there are multiple radios in an SOC, * the recovery has to be done for each radio */ - if (recovery_count == ab->num_radios) { - atomic_dec(&ab->reset_count); - complete(&ab->reset_complete); - ab->is_reset = false; - atomic_set(&ab->fail_cont_count, 0); - ath12k_dbg(ab, ATH12K_DBG_BOOT, "reset success\n"); - } + if (recovery_count == ar->ab->num_radios) { + atomic_dec(&ar->ab->reset_count); + complete(&ar->ab->reset_complete); + ar->ab->is_reset = false; + ar->ab->recovery_start = false; + atomic_set(&ar->ab->fail_cont_count, 0); + clear_bit(ATH12K_FLAG_RECOVERY, &ar->ab->dev_flags); + spin_lock_bh(&ar->ab->base_lock); + ar->ab->stats.last_recovery_time = + jiffies_to_msecs(jiffies - + ar->ab->recovery_start_time); + spin_unlock_bh(&ar->ab->base_lock); + ath12k_dbg(ar->ab, ATH12K_DBG_BOOT, "reset success\n"); } } mutex_unlock(&ar->conf_mutex); } +void +ath12k_mac_reconfig_complete(struct ieee80211_hw *hw, + enum ieee80211_reconfig_type reconfig_type, + struct ath12k *asserted_radio) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + u8 restart_count = 0; + int i; + + if (reconfig_type != IEEE80211_RECONFIG_TYPE_RESTART) + return; + + mutex_lock(&ah->conf_mutex); + + ar = ah->radio; + + if (asserted_radio) { + ath12k_mac_reconfig_completion(asserted_radio, &restart_count); + goto out; + } + + for (i = 0; i < ah->num_radio; i++) { + ath12k_mac_reconfig_completion(ar, &restart_count); + ar++; + } + +out: + /* If is_one_radio flag is set, then assume other radios + * are up and running and wake queues once the reconfig is + * done + */ + if (restart_count == ah->num_radio) + ieee80211_wake_queues(ah->hw); + + mutex_unlock(&ah->conf_mutex); + ah->ag->hw_queues_stopped = false; +} + +static void ath12k_mac_op_reconfig_complete(struct ieee80211_hw *hw, + enum ieee80211_reconfig_type reconfig_type) +{ + ath12k_mac_reconfig_complete(hw, reconfig_type, NULL); +} + static void ath12k_mac_update_bss_chan_survey(struct ath12k *ar, struct ieee80211_channel *channel) @@ -6432,32 +15095,59 @@ static int ath12k_mac_op_get_survey(struct ieee80211_hw *hw, int idx, struct survey_info *survey) { - struct ath12k *ar = hw->priv; + struct ath12k *ar; struct ieee80211_supported_band *sband; struct survey_info *ar_survey; int ret = 0; + enum nl80211_band band; if (idx >= ATH12K_NUM_CHANS) return -ENOENT; - ar_survey = &ar->survey[idx]; - - mutex_lock(&ar->conf_mutex); - + band = NL80211_BAND_2GHZ; sband = hw->wiphy->bands[NL80211_BAND_2GHZ]; if (sband && idx >= sband->n_channels) { idx -= sband->n_channels; sband = NULL; } - if (!sband) + if (!sband) { sband = hw->wiphy->bands[NL80211_BAND_5GHZ]; + band = NL80211_BAND_5GHZ; + } + + if (sband && idx >= sband->n_channels) { + idx -= sband->n_channels; + sband = NULL; + } + + if (!sband) { + sband = hw->wiphy->bands[NL80211_BAND_6GHZ]; + band = NL80211_BAND_6GHZ; + } if (!sband || idx >= sband->n_channels) { ret = -ENOENT; goto exit; } + ar = ath12k_mac_get_ar_by_chan(hw, &sband->channels[idx]); + if (!ar) { + if (sband->channels[idx].flags & IEEE80211_CHAN_DISABLED) { + ret = 0; + /* Flushing out the old survey results if any */ + memset(survey, 0, sizeof(*survey)); + goto exit; + } else { + ret = -ENOENT; + goto exit; + } + } + + ar_survey = &ar->survey[idx]; + + mutex_lock(&ar->conf_mutex); + ath12k_mac_update_bss_chan_survey(ar, &sband->channels[idx]); spin_lock_bh(&ar->data_lock); @@ -6469,27 +15159,68 @@ if (ar->rx_channel == survey->channel) survey->filled |= SURVEY_INFO_IN_USE; -exit: mutex_unlock(&ar->conf_mutex); + +exit: return ret; } +void ath12k_mac_ap_ps_recalc(struct ath12k *ar) { + struct ath12k_link_vif *arvif; + enum ath12k_ap_ps_state state = ATH12K_AP_PS_STATE_OFF; + int ret; + bool allow_ap_ps = true; + + lockdep_assert_held(&ar->conf_mutex); + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->ahvif->vdev_type != WMI_VDEV_TYPE_AP) { + allow_ap_ps = false; + break; + } + } + + if (!allow_ap_ps) + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "ap ps is not" + "allowed\n"); + + if (allow_ap_ps && !ar->num_stations && ar->ap_ps_enabled) + state = ATH12K_AP_PS_STATE_ON; + + if (ar->ap_ps_state == state) + return; + + ret = ath12k_wmi_pdev_ap_ps_cmd_send(ar, ar->pdev->pdev_id, state); + if (!ret) + ar->ap_ps_state = state; + else + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "failed to send ap ps command pdev_id %u state %u\n", + ar->pdev->pdev_id, state); +} + static void ath12k_mac_op_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta, struct station_info *sinfo) { - struct ath12k_sta *arsta = (struct ath12k_sta *)sta->drv_priv; - + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta = &ahsta->deflink; + struct ath12k *ar = arsta->arvif->ar; + + /* TODO accumulate link sta stats here? */ + + if (!ar) { + ath12k_err(NULL, + "unable to determine sta statistics \n"); + return; + } sinfo->rx_duration = arsta->rx_duration; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_DURATION); sinfo->tx_duration = arsta->tx_duration; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_DURATION); - if (!arsta->txrate.legacy && !arsta->txrate.nss) - return; - + if (arsta->txrate.legacy || arsta->txrate.nss) { if (arsta->txrate.legacy) { sinfo->txrate.legacy = arsta->txrate.legacy; } else { @@ -6502,10 +15233,686 @@ } sinfo->txrate.flags = arsta->txrate.flags; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); + } - /* TODO: Use real NF instead of default one. */ - sinfo->signal = arsta->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR; + sinfo->signal = arsta->rssi_comb + ar->rssi_offsets.rssi_offset; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL); + + sinfo->signal_avg = ewma_avg_rssi_read(&arsta->avg_rssi) + + ar->rssi_offsets.rssi_offset; + + sinfo->filled |= BIT_ULL(NL80211_STA_INFO_SIGNAL_AVG); +} + +int ath12k_mac_btcoex_config(struct ath12k *ar, struct ath12k_link_vif *arvif, + int coex, u32 wlan_prio_mask, u8 wlan_weight) +{ + struct coex_config_arg coex_config; + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + if (coex == BTCOEX_CONFIGURE_DEFAULT || (test_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags) ^ coex)) { + goto next; + } + + coex_config.vdev_id = arvif->vdev_id; + if (coex == BTCOEX_ENABLE) { + coex_config.config_type = WMI_COEX_CONFIG_PTA_INTERFACE; + coex_config.pta_num = ar->coex.pta_num; + coex_config.coex_mode = ar->coex.coex_mode; + coex_config.bt_txrx_time = ar->coex.bt_active_time_slot; + coex_config.bt_priority_time = ar->coex.bt_priority_time_slot; + coex_config.pta_algorithm = ar->coex.coex_algo_type; + coex_config.pta_priority = ar->coex.pta_priority; + ret = ath12k_send_coex_config_cmd(ar, &coex_config); + if (ret) { + ath12k_warn(ar->ab, + "failed to set coex config vdev_id %d ret %d\n", + coex_config.vdev_id, ret); + goto out; + } + } + + memset(&coex_config, 0, sizeof(struct coex_config_arg)); + coex_config.vdev_id = arvif->vdev_id; + coex_config.config_type = WMI_COEX_CONFIG_BTC_ENABLE; + coex_config.coex_enable = coex; + ret = ath12k_send_coex_config_cmd(ar, &coex_config); + if (ret) { + ath12k_warn(ar->ab, + "failed to set coex config vdev_id %d ret %d\n", + coex_config.vdev_id, ret); + goto out; + } + +next: + if (!coex) { + ret = 0; + goto out; + } + + memset(&coex_config, 0, sizeof(struct coex_config_arg)); + coex_config.vdev_id = arvif->vdev_id; + coex_config.config_type = WMI_COEX_CONFIG_WLAN_PKT_PRIORITY; + coex_config.wlan_pkt_type = wlan_prio_mask; + coex_config.wlan_pkt_weight = wlan_weight; + ret = ath12k_send_coex_config_cmd(ar, &coex_config); + if (ret) { + ath12k_warn(ar->ab, + "failed to set coex config vdev_id %d ret %d\n", + coex_config.vdev_id, ret); + } + +out: + return ret; +} + +static int ath12k_fw_stats_request(struct ath12k *ar, + struct stats_request_params *req_param) +{ + struct ath12k_base *ab = ar->ab; + unsigned long time_left; + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + spin_lock_bh(&ar->data_lock); + ar->fw_stats_done = false; + ath12k_fw_stats_pdevs_free(&ar->fw_stats.pdevs); + spin_unlock_bh(&ar->data_lock); + + reinit_completion(&ar->fw_stats_complete); + + ret = ath12k_wmi_send_stats_request_cmd(ar, req_param->stats_id, + req_param->vdev_id, req_param->pdev_id); + if (ret) { + ath12k_warn(ab, "could not request fw stats (%d)\n", + ret); + return ret; + } + + time_left = + wait_for_completion_timeout(&ar->fw_stats_complete, + 1 * HZ); + + if (!time_left) + return -ETIMEDOUT; + + return 0; +} + +static int ath12k_mac_op_get_txpower(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + /* unsigned int link_id, */int *dbm) +{ + unsigned int link_id = 0; + struct ath12k_hw *ah = hw->priv; + struct stats_request_params req_param; + struct ath12k_fw_stats_pdev *pdev; + struct ath12k *ar; + struct ath12k_base *ab; + int ret; + struct ieee80211_bss_conf *link_conf; + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif; + + /* Final Tx power is minimum of Target Power, CTL power, Regulatory + * Power, PSD EIRP Power. We just know the Regulatory power from the + * regulatory rules obtained. FW knows all these power and sets the min + * of these. Hence, we request the FW pdev stats in which FW reports + * the minimum of all vdev's channel Tx power. + */ + mutex_lock(&ah->conf_mutex); + + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + if (!ar) { + goto err_fallback; + } + + ab = ar->ab; + if (ar->state != ATH12K_STATE_ON) { + goto err_fallback; + } + + mutex_lock(&ar->conf_mutex); + if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + *dbm = 0; + return 0; + } + + /* Limit the requests to Firmware for fetching the tx power */ + if (ar->chan_tx_pwr != ATH12K_PDEV_TX_POWER_INVALID && + time_before(jiffies, msecs_to_jiffies(ATH12K_PDEV_TX_POWER_REFRESH_TIME_MSECS) + + ar->last_tx_power_update)) + goto get_tx_power; + + req_param.pdev_id = ar->pdev->pdev_id; + req_param.vdev_id = 0; + req_param.stats_id = WMI_REQUEST_PDEV_STAT; + + ret = ath12k_fw_stats_request(ar, &req_param); + if (ret) { + ath12k_warn(ab, "failed to request fw pdev stats: %d\n", ret); + mutex_unlock(&ar->conf_mutex); + goto err_fallback; + } + + spin_lock_bh(&ar->data_lock); + pdev = list_first_entry_or_null(&ar->fw_stats.pdevs, + struct ath12k_fw_stats_pdev, + list); + if (!pdev) { + spin_unlock_bh(&ar->data_lock); + mutex_unlock(&ar->conf_mutex); + goto err_fallback; + } + + /* tx power is set as 2 units per dBm in FW. */ + ar->chan_tx_pwr = pdev->chan_tx_power/2; + ar->last_tx_power_update = jiffies; + + spin_unlock_bh(&ar->data_lock); + +get_tx_power: + *dbm = ar->chan_tx_pwr; + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + + ath12k_dbg(ab, ATH12K_DBG_MAC, "txpower reported %d dBm\n", *dbm); + return 0; + +err_fallback: + ahvif = ath12k_vif_to_ahvif(vif); + arvif = ahvif->link[link_id]; + + if (!arvif) { + *dbm = 0; + mutex_unlock(&ah->conf_mutex); + return 0; + } + + rcu_read_lock(); + + /* We didn't get txpower from FW. Hence, relying on link_conf->txpower */ + link_conf = ath12k_get_link_bss_conf(arvif); + + if (!link_conf) { + *dbm = 0; + rcu_read_unlock(); + mutex_unlock(&ah->conf_mutex); + return 0; + } + + *dbm = link_conf->txpower; + rcu_read_unlock(); + mutex_unlock(&ah->conf_mutex); + ath12k_dbg(NULL, ATH12K_DBG_MAC, "txpower from firmware NaN, reported %d dBm\n", + *dbm); + return 0; +} + +/* + * Cancel remain on channel scan. This API will be called when remain on + * channel timer expires or when ROC scan required to be cancelled by + * mac layer even before ROC timer expires. + */ +static int ath12k_mac_op_cancel_remain_on_channel(struct ieee80211_hw *hw, + struct ieee80211_vif *vif) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_vif *ahvif = ath12k_vif_to_ahvif(vif); + u8 link_id = ahvif->last_scan_link; + struct ath12k_link_vif *arvif; + + mutex_lock(&ah->conf_mutex); + if (!(ahvif->links_map & BIT(link_id))) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(NULL, "unable to cancel scan. Link id %d not found\n", + link_id); + return -EINVAL; + } + + arvif = ahvif->link[link_id]; + + if (!arvif || !arvif->is_created) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(NULL, "unable to cancel scan. arvif interface is not created\n"); + return -EINVAL; + } + + ar = arvif->ar; + if (!ar) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(NULL, "unable to select device to cancel scan\n"); + return -EINVAL; + } + mutex_unlock(&ah->conf_mutex); + + mutex_lock(&ar->conf_mutex); + + spin_lock_bh(&ar->data_lock); + ar->scan.roc_notify = false; + spin_unlock_bh(&ar->data_lock); + + ath12k_scan_abort(ar); + + mutex_unlock(&ar->conf_mutex); + + cancel_delayed_work_sync(&ar->scan.timeout); + + return 0; +} + +/* + * Initiate remain on channel scan. When AP required to go to scan + * on off-channel, remain on channel will be called. This will + * start the scan in the requested channel + */ +static int ath12k_mac_op_remain_on_channel(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_channel *chan, + int duration, + enum ieee80211_roc_type type) +{ + struct ath12k_hw *ah = hw->priv; + struct ath12k_link_vif *arvif; + struct ath12k *ar; + struct ath12k_wmi_scan_req_arg arg = {0}; + struct cfg80211_chan_def chandef = {}; + struct ath12k_vif *ahvif; + int ret = 0, link_id; + u32 scan_time_msec; + bool create = true; + + mutex_lock(&ah->conf_mutex); + + ar = ath12k_mac_select_scan_device(hw, vif, chan->center_freq); + if (!ar) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(NULL, "unable to select device for scan\n"); + return -EINVAL; + } + if (unlikely(test_bit(ATH12K_FLAG_RECOVERY, &ar->ab->dev_flags))) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(ar->ab, "Recovery is in progress, cannot perform scan\n"); + return -ESHUTDOWN; + } + + link_id = ath12k_mac_find_link_id_by_freq(vif, ar, + chan->center_freq); + + arvif = ath12k_mac_assign_link_vif(ah, vif, link_id); + + if (!arvif) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(ar->ab, "arvif device is not found, link_id:%d, chan:%d, band:%d\n", + link_id, chan->center_freq, chan->band); + return -ENOMEM; + } + + if (arvif->is_created) { + if (ar != arvif->ar) { + if (arvif->is_started) { + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + if (!arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + mutex_lock(&arvif->ar->conf_mutex); + arvif->ar->scan.vdev_id = -1; + mutex_unlock(&arvif->ar->conf_mutex); + + ath12k_mac_remove_link_interface(hw, arvif); + ath12k_mac_unassign_link_vif(arvif); + } else { + create = false; + } + } + + if (create) { + mutex_lock(&ar->conf_mutex); + ret = ath12k_mac_vdev_create(ar, arvif); + mutex_unlock(&ar->conf_mutex); + if (ret) { + mutex_unlock(&ah->conf_mutex); + ath12k_warn(ar->ab, "unable to create scan vdev %d\n", ret); + return -EINVAL; + } + } + + ahvif = arvif->ahvif; + if (!arvif->is_started && ahvif->vdev_type == WMI_VDEV_TYPE_STA) { + chandef.chan = chan; + chandef.center_freq1 = chan->center_freq; + ret = ath12k_mac_vdev_start(arvif, &chandef, 0); + if (ret) { + mutex_unlock(&ah->conf_mutex); + ath12k_err(ar->ab, "vdev start failed sta roc\n"); + return -EINVAL; + } + arvif->is_started = true; + arvif->is_scan_vif = true; + } + + mutex_unlock(&ah->conf_mutex); + + mutex_lock(&ar->conf_mutex); + spin_lock_bh(&ar->data_lock); + switch (ar->scan.state) { + case ATH12K_SCAN_IDLE: + reinit_completion(&ar->scan.started); + reinit_completion(&ar->scan.completed); + reinit_completion(&ar->scan.on_channel); + ar->scan.state = ATH12K_SCAN_STARTING; + ar->scan.is_roc = true; + ar->scan.vdev_id = arvif->vdev_id; + ar->scan.roc_freq = chan->center_freq; + ar->scan.roc_notify = true; + ret = 0; + break; + case ATH12K_SCAN_STARTING: + case ATH12K_SCAN_RUNNING: + case ATH12K_SCAN_ABORTING: + ret = -EBUSY; + break; + } + spin_unlock_bh(&ar->data_lock); + + if (ret) { + mutex_unlock(&ar->conf_mutex); + ath12k_err(ar->ab, "Unable to start scan. scan_state:%d\n", ar->scan.state); + return ret; + } + + if (duration <= 0) + scan_time_msec = ah->hw->wiphy->max_remain_on_channel_duration * 2; + else + scan_time_msec = duration; + + ath12k_wmi_start_scan_init(ar, &arg); + + arg.num_chan = 1; + arg.chan_list = kcalloc(arg.num_chan, sizeof(*arg.chan_list), + GFP_KERNEL); + if (!arg.chan_list) { + mutex_unlock(&ar->conf_mutex); + ath12k_err(ar->ab, "chan list memory allocation failed\n"); + return -ENOMEM; + } + arg.chan_list[0] = chan->center_freq; + + arg.vdev_id = arvif->vdev_id; + arg.scan_id = ATH12K_SCAN_ID; + arg.dwell_time_active = scan_time_msec; + arg.dwell_time_passive = scan_time_msec; + arg.max_scan_time = scan_time_msec; + arg.dwell_time_active_6g = scan_time_msec; + arg.dwell_time_passive_6g = scan_time_msec; + + /* Set required scan flags*/ + arg.scan_f_passive = 1; + arg.scan_f_filter_prb_req = 1; + + /*these flags enables fw to tx offchan frame to unknown STA*/ + arg.scan_f_offchan_mgmt_tx = 1; + arg.scan_f_offchan_data_tx = 1; + arg.burst_duration = duration; + + ret = ath12k_start_scan(ar, &arg); + if (ret) { + ath12k_warn(ar->ab, "failed to start roc scan: %d\n", ret); + spin_lock_bh(&ar->data_lock); + ar->scan.state = ATH12K_SCAN_IDLE; + spin_unlock_bh(&ar->data_lock); + goto exit; + } + + ret = wait_for_completion_timeout(&ar->scan.on_channel, 3 * HZ); + if (ret == 0) { + ath12k_warn(ar->ab, "failed to switch to channel for roc scan\n"); + ret = ath12k_scan_stop(ar); + if (ret) + ath12k_warn(ar->ab, "failed to stop scan: %d\n", ret); + ret = -ETIMEDOUT; + goto exit; + } + + ieee80211_queue_delayed_work(ah->hw, &ar->scan.timeout, + msecs_to_jiffies(duration + + ATH12K_MAC_SCAN_TIMEOUT_MSECS)); + + ret = 0; + +exit: + kfree(arg.chan_list); + mutex_unlock(&ar->conf_mutex); + return ret; +} + +/* Note: only half bandwidth agile is supported */ +bool ath12k_is_supported_agile_bandwidth(enum nl80211_chan_width conf_bw, + enum nl80211_chan_width agile_bw) +{ + bool is_supported = false; + + switch (conf_bw) { + case NL80211_CHAN_WIDTH_20_NOHT: + case NL80211_CHAN_WIDTH_20: + case NL80211_CHAN_WIDTH_40: + if (agile_bw <= conf_bw) + is_supported = true; + break; + case NL80211_CHAN_WIDTH_80: + if (agile_bw == conf_bw || + agile_bw == NL80211_CHAN_WIDTH_40) + is_supported = true; + break; + case NL80211_CHAN_WIDTH_160: + if (agile_bw == conf_bw || + agile_bw == NL80211_CHAN_WIDTH_80) + is_supported = true; + break; + case NL80211_CHAN_WIDTH_320: + if (agile_bw == conf_bw || + agile_bw == NL80211_CHAN_WIDTH_160) + is_supported = true; + break; + default: + break; + } + + return is_supported; +} + +/* Note: caller should call rcu_read_lock before getting the peer mac. + */ +static u8 *ath12k_get_peer_mac(struct ieee80211_vif *vif, u8 *addr, u8 *link_id) +{ + struct ieee80211_sta *ap_sta; + struct ath12k_sta *ahsta; + struct ath12k_link_sta *arsta; + u8 link, *peer_addr = NULL; + + ap_sta = ieee80211_find_sta(vif, addr); + if (!ap_sta) + return NULL; + + ahsta = ath12k_sta_to_ahsta(ap_sta); + + for_each_set_bit(link, &ahsta->links_map, IEEE80211_MLD_MAX_NUM_LINKS) { + arsta = ahsta->link[link]; + if (!arsta) + continue; + + *link_id = link; + peer_addr = arsta->addr; + break; + } + return peer_addr; +} + +int ath12k_mac_op_set_scs(struct wireless_dev *wdev, + struct ath12k_latency_params *params) +{ + struct ieee80211_vif *vif; + struct ath12k *ar; + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif; + u8 *peer_mac; + int ret = 0; + u8 link_id; + + if (!wdev || !params) + return -EINVAL; + + vif = wdev_to_ieee80211_vif(wdev); + if (!vif) + return -EINVAL; + + ahvif = ath12k_vif_to_ahvif(vif); + if (!ahvif) + return -EINVAL; + + rcu_read_lock(); + peer_mac = ath12k_get_peer_mac(vif, params->peer_mac, &link_id); + if (!peer_mac) { + rcu_read_unlock(); + return -EINVAL; + } + memcpy(params->peer_mac, peer_mac, ETH_ALEN); + rcu_read_unlock(); + + arvif = ahvif->link[link_id]; + if (WARN_ON(!arvif)) + return -EINVAL; + + ar = arvif->ar; + if (!ar) + return -EINVAL; + + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "link id %d\n", link_id); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "service interval %d\n", params->service_interval); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "burst size %d\n", params->burst_size); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "delay bound %d\n", params->delay_bound); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "min data rate %d\n", params->min_data_rate); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "user priority %d\n", params->user_priority); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "req type %d\n", params->req_type); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "access category %d\n", params->ac); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "direction %d\n", params->direction); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "peer mac %pM\n", params->peer_mac); + + ret = ath12k_wmi_set_latency(ar, params); + return ret; +} + +static int ath12k_mac_op_set_radar_background(struct ieee80211_hw *hw, + struct cfg80211_chan_def *def) +{ + struct ath12k *ar; + struct ath12k_link_vif *arvif; + struct ath12k_vif *ahvif; + bool arvif_found = false; + int ret; + struct cfg80211_chan_def conf_def; + + if (def) + ar = ath12k_mac_get_ar_by_chan(hw, def->chan); + else + ar = ath12k_mac_get_ar_by_agile_chandef(hw, NL80211_BAND_5GHZ); + + if (!ar) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->ab->dfs_region == ATH12K_DFS_REG_UNSET) { + ret = -EINVAL; + goto exit; + } + + if (!test_bit(ar->cfg_rx_chainmask, &ar->pdev->cap.adfs_chain_mask) && + !test_bit(WMI_TLV_SERVICE_SW_PROG_DFS_SUPPORT, ar->ab->wmi_ab.svc_map)) { + ret = -EINVAL; + goto exit; + } + + list_for_each_entry(arvif, &ar->arvifs, list) { + ahvif = arvif->ahvif; + if (arvif->is_started && ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + arvif_found = true; + break; + } + } + + if (!arvif_found) { + ret = -EINVAL; + goto exit; + } + + if (!def) { + ret = ath12k_wmi_vdev_adfs_ocac_abort_cmd_send(ar,arvif->vdev_id); + if (!ret) { + memset(&ar->agile_chandef, 0, sizeof(struct cfg80211_chan_def)); + ar->agile_chandef.chan = NULL; + } + } else { + if (!cfg80211_chandef_valid(def)) { + ret = -EINVAL; + goto exit; + } + + if (WARN_ON(ath12k_mac_vif_chan(ahvif->vif, &conf_def, arvif->link_id))) { + ret = -EINVAL; + goto exit; + } + + if (cfg80211_chandef_identical(&conf_def, def) /* && + cfg80211_chandef_device_present(def) */) { + if (!test_bit(WMI_TLV_SERVICE_SW_PROG_DFS_SUPPORT, + ar->ab->wmi_ab.svc_map)) + ret = -EINVAL; + else + ret = 0; + goto exit; + } + + if (!(def->chan->flags & IEEE80211_CHAN_RADAR)) { + ret = -EINVAL; + goto exit; + } + + /* Note: Only Half width and full bandwidth is supported */ + if(!(ath12k_is_supported_agile_bandwidth(conf_def.width, + def->width))) { + ret = -EINVAL; + goto exit; + } + + if (conf_def.center_freq1 == def->center_freq1) { + ret = -EINVAL; + goto exit; + } + + ret = ath12k_wmi_vdev_adfs_ch_cfg_cmd_send(ar, arvif->vdev_id, def); + if (!ret) { + memcpy(&ar->agile_chandef, def, sizeof(struct cfg80211_chan_def)); + } else { + memset(&ar->agile_chandef, 0, sizeof(struct cfg80211_chan_def)); + ar->agile_chandef.chan = NULL; + } + } + +exit: + mutex_unlock(&ar->conf_mutex); + return ret; } static const struct ieee80211_ops ath12k_ops = { @@ -6518,12 +15925,15 @@ .remove_interface = ath12k_mac_op_remove_interface, .update_vif_offload = ath12k_mac_op_update_vif_offload, .config = ath12k_mac_op_config, - .bss_info_changed = ath12k_mac_op_bss_info_changed, + .link_info_changed = ath12k_mac_op_bss_info_changed, + .vif_cfg_changed = ath12k_mac_op_vif_cfg_changed, + .change_vif_links = ath12k_mac_op_change_vif_links, .configure_filter = ath12k_mac_op_configure_filter, .hw_scan = ath12k_mac_op_hw_scan, .cancel_hw_scan = ath12k_mac_op_cancel_hw_scan, .set_key = ath12k_mac_op_set_key, .sta_state = ath12k_mac_op_sta_state, + .sta_set_4addr = ath12k_mac_op_sta_set_4addr, .sta_set_txpwr = ath12k_mac_op_sta_set_txpwr, .sta_rc_update = ath12k_mac_op_sta_rc_update, .conf_tx = ath12k_mac_op_conf_tx, @@ -6541,7 +15951,21 @@ .set_bitrate_mask = ath12k_mac_op_set_bitrate_mask, .get_survey = ath12k_mac_op_get_survey, .flush = ath12k_mac_op_flush, + .flush_sta = ath12k_mac_op_flush_sta, .sta_statistics = ath12k_mac_op_sta_statistics, + .change_sta_links = ath12k_mac_op_change_sta_links, + CFG80211_TESTMODE_CMD(ath12k_tm_cmd) +#ifdef CONFIG_ATH12K_DEBUGFS + .sta_add_debugfs = ath12k_debugfs_sta_op_add, + .link_sta_add_debugfs = ath12k_debugfs_link_sta_op_add, +#endif + .remain_on_channel = ath12k_mac_op_remain_on_channel, + .cancel_remain_on_channel = ath12k_mac_op_cancel_remain_on_channel, + .get_txpower = ath12k_mac_op_get_txpower, + .set_radar_background = ath12k_mac_op_set_radar_background, +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + .set_multicast_to_unicast = ath12k_mac_op_set_multicast_to_unicast, +#endif }; static void ath12k_mac_update_ch_list(struct ath12k *ar, @@ -6560,6 +15984,65 @@ } } +/* During MLO split mac scenario, both the supporting channel list of same band + * should be updated in same wiphy->band[] place. We update the later incoming + * pdev supported channel list (new_band) into wiphy->band[] (orig_band) + */ +static int ath12k_mac_update_band(struct ath12k *ar, + struct ieee80211_supported_band *orig_band, + struct ieee80211_supported_band *new_band) +{ + struct ath12k_base *ab = ar->ab; + int i; + + if (!orig_band || !new_band) + return -EINVAL; + + if (orig_band->band != new_band->band) + return -EINVAL; + + if (WARN_ON(!ab->ag->mlo_capable)) + return -EOPNOTSUPP; + + for (i = 0; i < new_band->n_channels; i++) { + if (new_band->channels[i].flags & IEEE80211_CHAN_DISABLED) + continue; + + /* An enabled channel in new_band should not be already enabled + * in the orig_band + */ + if (WARN_ON(!(orig_band->channels[i].flags & + IEEE80211_CHAN_DISABLED))) + return -ENOTRECOVERABLE; + + orig_band->channels[i].flags &= ~IEEE80211_CHAN_DISABLED; + } + + return 0; +} + +#define ATH12K_5_9_MIN_FREQ 5845 +#define ATH12K_5_9_MAX_FREQ 5885 + +static void ath12k_mac_update_5_9_ch_list(struct ath12k *ar, + struct ieee80211_supported_band *band) +{ + int i; + + if (test_bit(WMI_TLV_SERVICE_5_9GHZ_SUPPORT, + ar->ab->wmi_ab.svc_map)) + return; + + if (ar->ab->dfs_region != ATH12K_DFS_REG_FCC) + return; + + for (i = 0; i < band->n_channels; i++) { + if (band->channels[i].center_freq >= ATH12K_5_9_MIN_FREQ && + band->channels[i].center_freq <= ATH12K_5_9_MAX_FREQ) + band->channels[i].flags |= IEEE80211_CHAN_DISABLED; + } +} + static u32 ath12k_get_phy_id(struct ath12k *ar, u32 band) { struct ath12k_pdev *pdev = ar->pdev; @@ -6579,17 +16062,21 @@ static int ath12k_mac_setup_channels_rates(struct ath12k *ar, u32 supported_bands) { + struct ath12k_base *ab = ar->ab; + struct ath12k_hw *ah = ar->ah; struct ieee80211_supported_band *band; - struct ath12k_wmi_hal_reg_capabilities_ext_arg *reg_cap; + struct ath12k_wmi_hal_reg_capabilities_ext_arg *reg_cap, *temp_reg_cap; void *channels; - u32 phy_id; + u32 phy_id, freq_low, freq_high; + int ret; BUILD_BUG_ON((ARRAY_SIZE(ath12k_2ghz_channels) + ARRAY_SIZE(ath12k_5ghz_channels) + ARRAY_SIZE(ath12k_6ghz_channels)) != ATH12K_NUM_CHANS); - reg_cap = &ar->ab->hal_reg_cap[ar->pdev_idx]; + reg_cap = &ab->hal_reg_cap[ar->pdev_idx]; + temp_reg_cap = reg_cap; if (supported_bands & WMI_HOST_WLAN_2G_CAP) { channels = kmemdup(ath12k_2ghz_channels, @@ -6604,46 +16091,55 @@ band->channels = channels; band->n_bitrates = ath12k_g_rates_size; band->bitrates = ath12k_g_rates; - ar->hw->wiphy->bands[NL80211_BAND_2GHZ] = band; - if (ar->ab->hw_params->single_pdev_only) { + if (ab->hw_params->single_pdev_only) { phy_id = ath12k_get_phy_id(ar, WMI_HOST_WLAN_2G_CAP); - reg_cap = &ar->ab->hal_reg_cap[phy_id]; + temp_reg_cap = &ab->hal_reg_cap[phy_id]; } ath12k_mac_update_ch_list(ar, band, - reg_cap->low_2ghz_chan, - reg_cap->high_2ghz_chan); - } + temp_reg_cap->low_2ghz_chan, + temp_reg_cap->high_2ghz_chan); - if (supported_bands & WMI_HOST_WLAN_5G_CAP) { - if (reg_cap->high_5ghz_chan >= ATH12K_MAX_6G_FREQ) { - channels = kmemdup(ath12k_6ghz_channels, - sizeof(ath12k_6ghz_channels), GFP_KERNEL); - if (!channels) { - kfree(ar->mac.sbands[NL80211_BAND_2GHZ].channels); - return -ENOMEM; - } + freq_low = max(temp_reg_cap->low_2ghz_chan, + ab->reg_freq_2g.start_freq); + freq_high = min(temp_reg_cap->high_2ghz_chan, + ab->reg_freq_2g.end_freq); + + ar->chan_info.low_freq = freq_low; + ar->chan_info.high_freq = freq_high; + ar->chan_info.num_channels = ath12k_reg_get_num_chans_in_band(ar, band, + freq_low, + freq_high); + + if (!ah->hw->wiphy->bands[NL80211_BAND_2GHZ]) { + ah->hw->wiphy->bands[NL80211_BAND_2GHZ] = band; + ah->supported_band_mask |= BIT(NL80211_BAND_2GHZ); + } else { + /* Split mac in same band under same wiphy during MLO */ + ret = ath12k_mac_update_band(ar, + ah->hw->wiphy->bands[NL80211_BAND_2GHZ], + band); + if (ret) + return ret; - ar->supports_6ghz = true; - band = &ar->mac.sbands[NL80211_BAND_6GHZ]; - band->band = NL80211_BAND_6GHZ; - band->n_channels = ARRAY_SIZE(ath12k_6ghz_channels); - band->channels = channels; - band->n_bitrates = ath12k_a_rates_size; - band->bitrates = ath12k_a_rates; - ar->hw->wiphy->bands[NL80211_BAND_6GHZ] = band; - ath12k_mac_update_ch_list(ar, band, - reg_cap->low_5ghz_chan, - reg_cap->high_5ghz_chan); + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac pdev %u identified as 2 GHz split mac during MLO\n", + ar->pdev->pdev_id); + } } - if (reg_cap->low_5ghz_chan < ATH12K_MIN_6G_FREQ) { + if (supported_bands & WMI_HOST_WLAN_5G_CAP) { + /* If 5g end and 6g start overlaps, decide band based on + * the difference between target limit and ATH12K_5G_MAX_CENTER. + */ + if ((reg_cap->low_5ghz_chan >= ATH12K_MIN_5G_FREQ) && + ((reg_cap->high_5ghz_chan < ATH12K_MAX_5G_FREQ) || + ((reg_cap->high_5ghz_chan - ATH12K_5G_MAX_CENTER) < (ATH12K_HALF_20MHZ_BW * 2)))) { channels = kmemdup(ath12k_5ghz_channels, sizeof(ath12k_5ghz_channels), GFP_KERNEL); if (!channels) { kfree(ar->mac.sbands[NL80211_BAND_2GHZ].channels); - kfree(ar->mac.sbands[NL80211_BAND_6GHZ].channels); + ar->mac.sbands[NL80211_BAND_2GHZ].channels = NULL; return -ENOMEM; } @@ -6653,34 +16149,120 @@ band->channels = channels; band->n_bitrates = ath12k_a_rates_size; band->bitrates = ath12k_a_rates; - ar->hw->wiphy->bands[NL80211_BAND_5GHZ] = band; if (ar->ab->hw_params->single_pdev_only) { phy_id = ath12k_get_phy_id(ar, WMI_HOST_WLAN_5G_CAP); - reg_cap = &ar->ab->hal_reg_cap[phy_id]; + temp_reg_cap = &ab->hal_reg_cap[phy_id]; } + ath12k_mac_update_ch_list(ar, band, + temp_reg_cap->low_5ghz_chan, + temp_reg_cap->high_5ghz_chan); + + ath12k_mac_update_5_9_ch_list(ar, band); + + freq_low = max(temp_reg_cap->low_5ghz_chan, + ab->reg_freq_5g.start_freq); + freq_high = min(temp_reg_cap->high_5ghz_chan, + ab->reg_freq_5g.end_freq); + + ar->chan_info.low_freq = freq_low; + ar->chan_info.high_freq = freq_high; + ar->chan_info.num_channels = + ath12k_reg_get_num_chans_in_band(ar, band, + freq_low, + freq_high); + + if (!ah->hw->wiphy->bands[NL80211_BAND_5GHZ]) { + ah->hw->wiphy->bands[NL80211_BAND_5GHZ] = band; + ah->supported_band_mask |= BIT(NL80211_BAND_5GHZ); + } else { + /* Split mac in same band under same wiphy during MLO */ + ret = ath12k_mac_update_band(ar, + ah->hw->wiphy->bands[NL80211_BAND_5GHZ], + band); + if (ret) + return ret; + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac pdev %u identified as 5 GHz split mac during MLO\n", + ar->pdev->pdev_id); + } + } else if (reg_cap->low_5ghz_chan >= ATH12K_MIN_6G_FREQ && + reg_cap->high_5ghz_chan <= ATH12K_MAX_6G_FREQ) { + band = &ar->mac.sbands[NL80211_BAND_6GHZ]; + band->band = NL80211_BAND_6GHZ; + channels = kmemdup(ath12k_6ghz_channels, + sizeof(ath12k_6ghz_channels), + GFP_KERNEL); + if (!channels) { + kfree(ar->mac.sbands[NL80211_BAND_2GHZ].channels); + ar->mac.sbands[NL80211_BAND_2GHZ].channels = NULL; + return -ENOMEM; + } + + band = &ar->mac.sbands[NL80211_BAND_6GHZ]; + band->band = NL80211_BAND_6GHZ; + band->n_channels = ARRAY_SIZE(ath12k_6ghz_channels); + band->channels = channels; + band->n_bitrates = ath12k_a_rates_size; + band->bitrates = ath12k_a_rates; + ar->supports_6ghz = true; ath12k_mac_update_ch_list(ar, band, - reg_cap->low_5ghz_chan, - reg_cap->high_5ghz_chan); + temp_reg_cap->low_5ghz_chan, + temp_reg_cap->high_5ghz_chan); + + freq_low = max(temp_reg_cap->low_5ghz_chan, + ab->reg_freq_6g.start_freq); + freq_high = min(temp_reg_cap->high_5ghz_chan, + ab->reg_freq_6g.end_freq); + + ar->chan_info.low_freq = freq_low; + ar->chan_info.high_freq = freq_high; + ar->chan_info.num_channels = + ath12k_reg_get_num_chans_in_band(ar, band, + freq_low, + freq_high); + + if (!ah->hw->wiphy->bands[NL80211_BAND_6GHZ]) { + ah->hw->wiphy->bands[NL80211_BAND_6GHZ] = band; + ah->supported_band_mask |= BIT(NL80211_BAND_6GHZ); + } else { + /* Split mac in same band under same wiphy during MLO */ + ret = ath12k_mac_update_band(ar, + ah->hw->wiphy->bands[NL80211_BAND_6GHZ], + band); + if (ret) + return ret; + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac pdev %u identified as 6 GHz split mac during MLO\n", + ar->pdev->pdev_id); + } } } + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "mac pdev %u freq limits %u->%u MHz no. of channels %u\n", + ar->pdev->pdev_id, ar->chan_info.low_freq, + ar->chan_info.high_freq, ar->chan_info.num_channels); return 0; } -static int ath12k_mac_setup_iface_combinations(struct ath12k *ar) +static int ath12k_mac_setup_iface_combinations(struct ath12k_hw *ah) { - struct ath12k_base *ab = ar->ab; + struct ieee80211_hw *hw = ah->hw; struct ieee80211_iface_combination *combinations; struct ieee80211_iface_limit *limits; + struct ath12k_base *ab_dflt; + struct ath12k *ar; int n_limits, max_interfaces; bool ap, mesh; - ap = ab->hw_params->interface_modes & BIT(NL80211_IFTYPE_AP); + ar = ah->radio; + ab_dflt = ar->ab; + + ap = ab_dflt->hw_params->interface_modes & BIT(NL80211_IFTYPE_AP); mesh = IS_ENABLED(CONFIG_MAC80211_MESH) && - ab->hw_params->interface_modes & BIT(NL80211_IFTYPE_MESH_POINT); + ab_dflt->hw_params->interface_modes & BIT(NL80211_IFTYPE_MESH_POINT); combinations = kzalloc(sizeof(*combinations), GFP_KERNEL); if (!combinations) @@ -6720,32 +16302,93 @@ combinations[0].radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT(NL80211_CHAN_WIDTH_20) | BIT(NL80211_CHAN_WIDTH_40) | - BIT(NL80211_CHAN_WIDTH_80); + BIT(NL80211_CHAN_WIDTH_80) | + BIT(NL80211_CHAN_WIDTH_80P80) | + BIT(NL80211_CHAN_WIDTH_160); - ar->hw->wiphy->iface_combinations = combinations; - ar->hw->wiphy->n_iface_combinations = 1; + hw->wiphy->iface_combinations = combinations; + hw->wiphy->n_iface_combinations = 1; return 0; } +static void ath12k_mac_fetch_coex_info(struct ath12k *ar) +{ + struct ath12k_pdev_cap *cap = &ar->pdev->cap; + struct ath12k_base *ab = ar->ab; + struct device *dev = ab->dev; + + ar->coex.coex_support = false; + + if (!(cap->supported_bands & WMI_HOST_WLAN_2G_CAP)) + return; + + if (of_property_read_u32(dev->of_node, "qcom,pta-num", + &ar->coex.pta_num)) { + /* ath12k_err(ab, "No qcom,pta_num entry in dev-tree.\n"); */ + } + + if (of_property_read_u32(dev->of_node, "qcom,coex-mode", + &ar->coex.coex_mode)) { + /* ath12k_err(ab, "No qcom,coex_mode entry in dev-tree.\n"); */ + } + + if (of_property_read_u32(dev->of_node, "qcom,bt-active-time", + &ar->coex.bt_active_time_slot)) { + /* ath12k_err(ab, "No qcom,bt-active-time entry in dev-tree.\n"); */ + } + + if (of_property_read_u32(dev->of_node, "qcom,bt-priority-time", + &ar->coex.bt_priority_time_slot)) { + /* ath12k_err(ab, "No qcom,bt-priority-time entry in dev-tree.\n"); */ + } + + if (of_property_read_u32(dev->of_node, "qcom,coex-algo", + &ar->coex.coex_algo_type)) { + /* ath12k_err(ab, "No qcom,coex-algo entry in dev-tree.\n"); */ + } + + if (of_property_read_u32(dev->of_node, "qcom,pta-priority", + &ar->coex.pta_priority)) { + /* ath12k_err(ab, "No qcom,pta-priority entry in dev-tree.\n"); */ + } + + if (ar->coex.coex_algo_type == COEX_ALGO_OCS) { + ar->coex.duty_cycle = 100000; + ar->coex.wlan_duration = 80000; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, "coex pta_num %u coex_mode %u" + " bt_active_time_slot %u bt_priority_time_slot %u" + " coex_algorithm %u pta_priority %u\n", ar->coex.pta_num, + ar->coex.coex_mode, ar->coex.bt_active_time_slot, + ar->coex.bt_priority_time_slot, ar->coex.coex_algo_type, + ar->coex.pta_priority); + ar->coex.coex_support = true; +} + static const u8 ath12k_if_types_ext_capa[] = { [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, + [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, }; static const u8 ath12k_if_types_ext_capa_sta[] = { [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, + [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, [9] = WLAN_EXT_CAPA10_TWT_REQUESTER_SUPPORT, }; static const u8 ath12k_if_types_ext_capa_ap[] = { [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, + [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, [9] = WLAN_EXT_CAPA10_TWT_RESPONDER_SUPPORT, + [10] = WLAN_EXT_CAPA11_EMA_SUPPORT, }; -static const struct wiphy_iftype_ext_capab ath12k_iftypes_ext_capa[] = { +static struct wiphy_iftype_ext_capab ath12k_iftypes_ext_capa[] = { { .extended_capabilities = ath12k_if_types_ext_capa, .extended_capabilities_mask = ath12k_if_types_ext_capa, @@ -6762,48 +16405,158 @@ .extended_capabilities_mask = ath12k_if_types_ext_capa_ap, .extended_capabilities_len = sizeof(ath12k_if_types_ext_capa_ap), + .eml_capabilities = 0, + .mld_capa_and_ops = 0, }, }; -static void __ath12k_mac_unregister(struct ath12k *ar) +static void __ath12k_mac_pre_unregister(struct ath12k *ar) { cancel_work_sync(&ar->regd_update_work); +} - ieee80211_unregister_hw(ar->hw); +static void __ath12k_mac_post_unregister(struct ath12k *ar) +{ + struct ath12k_mac_tx_mgmt_free_arg arg = { }; - idr_for_each(&ar->txmgmt_idr, ath12k_mac_tx_mgmt_pending_free, ar); + arg.ar = ar; + arg.type = u8_encode_bits(true, ATH12K_MAC_TX_MGMT_FREE_TYPE_PDEV); + idr_for_each(&ar->txmgmt_idr, ath12k_mac_tx_mgmt_pending_free, &arg); idr_destroy(&ar->txmgmt_idr); kfree(ar->mac.sbands[NL80211_BAND_2GHZ].channels); kfree(ar->mac.sbands[NL80211_BAND_5GHZ].channels); kfree(ar->mac.sbands[NL80211_BAND_6GHZ].channels); - kfree(ar->hw->wiphy->iface_combinations[0].limits); - kfree(ar->hw->wiphy->iface_combinations); - - SET_IEEE80211_DEV(ar->hw, NULL); + ar->mac.sbands[NL80211_BAND_2GHZ].channels = NULL; + ar->mac.sbands[NL80211_BAND_5GHZ].channels = NULL; + ar->mac.sbands[NL80211_BAND_6GHZ].channels = NULL; } -void ath12k_mac_unregister(struct ath12k_base *ab) +static void __ath12k_mac_unregister(struct ath12k *ar) + { + __ath12k_mac_pre_unregister(ar); + __ath12k_mac_post_unregister(ar); +} +static void ath12k_mac_hw_unregister(struct ath12k_hw *ah) { struct ath12k *ar; - struct ath12k_pdev *pdev; int i; - for (i = 0; i < ab->num_radios; i++) { - pdev = &ab->pdevs[i]; - ar = pdev->ar; - if (!ar) + ar = ah->radio; + + for (i = 0; i < ah->num_radio; i++) { + __ath12k_mac_pre_unregister(ar); + ar++; + } + + ieee80211_unregister_hw(ah->hw); + + ar = ah->radio; + for (i = 0; i < ah->num_radio; i++) { + __ath12k_mac_post_unregister(ar); + ar++; + } + + kfree(ah->hw->wiphy->iface_combinations[0].limits); + kfree(ah->hw->wiphy->iface_combinations); + + SET_IEEE80211_DEV(ah->hw, NULL); +} + +void ath12k_mac_unregister(struct ath12k_hw_group *ag) +{ + struct ath12k_hw *ah; + int i; + + for (i = ag->num_hw - 1; i >= 0; i--) { + ah = ag->ah[i]; + if (!ah) continue; - __ath12k_mac_unregister(ar); + ath12k_mac_hw_unregister(ah); } } static int __ath12k_mac_register(struct ath12k *ar) { - struct ath12k_base *ab = ar->ab; - struct ath12k_pdev_cap *cap = &ar->pdev->cap; + struct ieee80211_hw *hw; + struct ath12k_pdev_cap *cap; + int ret; + u32 ht_cap = 0; + + hw = ar->ah->hw; + init_waitqueue_head(&ar->tx_empty_waitq); + idr_init(&ar->txmgmt_idr); + spin_lock_init(&ar->txmgmt_idr_lock); + + cap = &ar->pdev->cap; + + ret = ath12k_mac_setup_channels_rates(ar, + cap->supported_bands); + if (ret) + return ret; + + ath12k_mac_setup_ht_vht_cap(ar, cap, &ht_cap); + ath12k_mac_setup_he_eht_cap(ar, cap); + + ar->rssi_offsets.rssi_offset = ATH12K_DEFAULT_NOISE_FLOOR; + + hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP_VLAN); + hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_AP_VLAN); + + ath12k_pdev_caps_update(ar); + + ar->max_num_stations = TARGET_NUM_STATIONS; + ar->max_num_peers = TARGET_NUM_PEERS_PDEV; + + if (cap->nss_ratio_enabled) + ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); + + ieee80211_hw_set(hw, AMPDU_AGGREGATION); + ieee80211_hw_set(hw, TX_AMPDU_SETUP_IN_HW); + ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER); + ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); + ieee80211_hw_set(hw, USES_RSS); + + /* TODO: Check if HT capability advertised from firmware is different + * for each band for a dual band capable radio. It will be tricky to + * handle it when the ht capability different for each band. + */ + if (ht_cap & WMI_HT_CAP_DYNAMIC_SMPS || ar->supports_6ghz) + hw->wiphy->features |= NL80211_FEATURE_DYNAMIC_SMPS; + + if (ar->supports_6ghz) { + wiphy_ext_feature_set(hw->wiphy, + NL80211_EXT_FEATURE_FILS_DISCOVERY); + wiphy_ext_feature_set(hw->wiphy, + NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); + } + + if (ar->pdev->cap.supported_bands & WMI_HOST_WLAN_5G_CAP) { + if (test_bit(ar->cfg_rx_chainmask, &cap->adfs_chain_mask)) { + wiphy_ext_feature_set(hw->wiphy, + NL80211_EXT_FEATURE_RADAR_BACKGROUND); + } else if (test_bit(WMI_TLV_SERVICE_SW_PROG_DFS_SUPPORT, + ar->ab->wmi_ab.svc_map)) { + wiphy_ext_feature_set(hw->wiphy, + NL80211_EXT_FEATURE_RADAR_BACKGROUND); + } + } + + return 0; +} +static int ath12k_mac_hw_register(struct ath12k_hw *ah) +{ + struct ieee80211_hw *hw; + struct ath12k_pdev_cap *cap; + struct ath12k_base *ab, *ab_dflt; + struct ath12k *ar; + struct ath12k_hw_group *ag; + struct ath12k_pdev *pdev; + int i, j, ret; + u32 antennas_rx, antennas_tx; + bool unregister = false; static const u32 cipher_suites[] = { WLAN_CIPHER_SUITE_TKIP, WLAN_CIPHER_SUITE_CCMP, @@ -6815,239 +16568,312 @@ WLAN_CIPHER_SUITE_GCMP_256, WLAN_CIPHER_SUITE_CCMP_256, }; - int ret; - u32 ht_cap = 0; - ath12k_pdev_caps_update(ar); + hw = ah->hw; - SET_IEEE80211_PERM_ADDR(ar->hw, ar->mac_addr); + hw->wiphy->max_ap_assoc_sta = 0; + antennas_rx = 0; + antennas_tx = 0; + + ar = ah->radio; + ab = ar->ab; + ag = ab->ag; + hw->wiphy->dev_port = ar->pdev_idx; - SET_IEEE80211_DEV(ar->hw, ab->dev); + /* Use the first chip in group to advertise some features/info + * these are expected to be similar for chips in group + */ + ab_dflt = ab; - ret = ath12k_mac_setup_channels_rates(ar, - cap->supported_bands); + for (i = 0; i < ah->num_radio; i++) { + ab = ar->ab; + pdev = ar->pdev; + cap = &ar->pdev->cap; + if (ab->pdevs_macaddr_valid) { + ether_addr_copy(ar->mac_addr, pdev->mac_addr); + } else { + ether_addr_copy(ar->mac_addr, ab->mac_addr); + ar->mac_addr[4] += i; + } + + ret = __ath12k_mac_register(ar); if (ret) - goto err; + goto err_cleanup; - ath12k_mac_setup_ht_vht_cap(ar, cap, &ht_cap); - ath12k_mac_setup_he_cap(ar, cap); + /* Advertise the max antenna support of all radios, driver can handle + * per pdev specific antenna setting based on pdev cap when antenna changes + * are made + */ + antennas_rx = max_t(u32, antennas_rx, cap->rx_chain_mask); + antennas_tx = max_t(u32, antennas_tx, cap->tx_chain_mask); - ret = ath12k_mac_setup_iface_combinations(ar); - if (ret) { - ath12k_err(ar->ab, "failed to setup interface combinations: %d\n", ret); - goto err_free_channels; - } + hw->wiphy->max_ap_assoc_sta += ar->max_num_stations; + SET_IEEE80211_PERM_ADDR(hw, ar->mac_addr); - ar->hw->wiphy->available_antennas_rx = cap->rx_chain_mask; - ar->hw->wiphy->available_antennas_tx = cap->tx_chain_mask; - - ar->hw->wiphy->interface_modes = ab->hw_params->interface_modes; - - ieee80211_hw_set(ar->hw, SIGNAL_DBM); - ieee80211_hw_set(ar->hw, SUPPORTS_PS); - ieee80211_hw_set(ar->hw, SUPPORTS_DYNAMIC_PS); - ieee80211_hw_set(ar->hw, MFP_CAPABLE); - ieee80211_hw_set(ar->hw, REPORTS_TX_ACK_STATUS); - ieee80211_hw_set(ar->hw, HAS_RATE_CONTROL); - ieee80211_hw_set(ar->hw, AP_LINK_PS); - ieee80211_hw_set(ar->hw, SPECTRUM_MGMT); - ieee80211_hw_set(ar->hw, CONNECTION_MONITOR); - ieee80211_hw_set(ar->hw, SUPPORTS_PER_STA_GTK); - ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); - ieee80211_hw_set(ar->hw, QUEUE_CONTROL); - ieee80211_hw_set(ar->hw, SUPPORTS_TX_FRAG); - ieee80211_hw_set(ar->hw, REPORTS_LOW_ACK); - - if (ht_cap & WMI_HT_CAP_ENABLED) { - ieee80211_hw_set(ar->hw, AMPDU_AGGREGATION); - ieee80211_hw_set(ar->hw, TX_AMPDU_SETUP_IN_HW); - ieee80211_hw_set(ar->hw, SUPPORTS_REORDERING_BUFFER); - ieee80211_hw_set(ar->hw, SUPPORTS_AMSDU_IN_AMPDU); - ieee80211_hw_set(ar->hw, USES_RSS); + ar++; } - ar->hw->wiphy->features |= NL80211_FEATURE_STATIC_SMPS; - ar->hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; + hw->wiphy->available_antennas_rx = antennas_rx; + hw->wiphy->available_antennas_tx = antennas_tx; - /* TODO: Check if HT capability advertised from firmware is different - * for each band for a dual band capable radio. It will be tricky to - * handle it when the ht capability different for each band. + /* TODO: Add link/ar specific iface combinations + * For now, setting up combination once for the wiphy (ah) */ - if (ht_cap & WMI_HT_CAP_DYNAMIC_SMPS) - ar->hw->wiphy->features |= NL80211_FEATURE_DYNAMIC_SMPS; + ret = ath12k_mac_setup_iface_combinations(ah); + if (ret) { + ath12k_err(NULL, "failed to setup interface combinations: %d\n", + ret); + goto err_cleanup; + } - ar->hw->wiphy->max_scan_ssids = WLAN_SCAN_PARAMS_MAX_SSID; - ar->hw->wiphy->max_scan_ie_len = WLAN_SCAN_PARAMS_MAX_IE_LEN; + SET_IEEE80211_DEV(hw, ab_dflt->dev); - ar->hw->max_listen_interval = ATH12K_MAX_HW_LISTEN_INTERVAL; + /* Iface modes are expected to be similar for partner chips */ + hw->wiphy->interface_modes = ab_dflt->hw_params->interface_modes; - ar->hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; - ar->hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; - ar->hw->wiphy->max_remain_on_channel_duration = 5000; + hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP_VLAN); + hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_AP_VLAN); - ar->hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; - ar->hw->wiphy->features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | + ieee80211_hw_set(hw, SIGNAL_DBM); + ieee80211_hw_set(hw, SUPPORTS_PS); + ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); + ieee80211_hw_set(hw, MFP_CAPABLE); + ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); + ieee80211_hw_set(hw, HAS_RATE_CONTROL); + ieee80211_hw_set(hw, AP_LINK_PS); + ieee80211_hw_set(hw, SPECTRUM_MGMT); + ieee80211_hw_set(hw, CONNECTION_MONITOR); + ieee80211_hw_set(hw, WANT_MONITOR_VIF); + ieee80211_hw_set(hw, SUPPORTS_PER_STA_GTK); + ieee80211_hw_set(hw, CHANCTX_STA_CSA); + ieee80211_hw_set(hw, QUEUE_CONTROL); + ieee80211_hw_set(hw, SUPPORTS_TX_FRAG); + ieee80211_hw_set(hw, REPORTS_LOW_ACK); + ieee80211_hw_set(hw, AMPDU_AGGREGATION); + ieee80211_hw_set(hw, TX_AMPDU_SETUP_IN_HW); + ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER); + ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); + ieee80211_hw_set(hw, USES_RSS); + ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); + + if (ath12k_frame_mode == ATH12K_HW_TXRX_ETHERNET) { + ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); + ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); + } + + hw->wiphy->features |= NL80211_FEATURE_STATIC_SMPS; + hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; + + hw->wiphy->max_scan_ssids = WLAN_SCAN_PARAMS_MAX_SSID; + hw->wiphy->max_scan_ie_len = WLAN_SCAN_PARAMS_MAX_IE_LEN; + + hw->max_listen_interval = ATH12K_MAX_HW_LISTEN_INTERVAL; + + hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; + hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; + hw->wiphy->max_remain_on_channel_duration = 5000; + + hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD; + hw->wiphy->features |= NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | NL80211_FEATURE_AP_SCAN; - ar->max_num_stations = TARGET_NUM_STATIONS; - ar->max_num_peers = TARGET_NUM_PEERS_PDEV; + hw->wiphy->features |= NL80211_FEATURE_TX_POWER_INSERTION; - ar->hw->wiphy->max_ap_assoc_sta = ar->max_num_stations; + if (ag->mlo_capable) + hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; - ar->hw->queues = ATH12K_HW_MAX_QUEUES; - ar->hw->wiphy->tx_queue_len = ATH12K_QUEUE_LEN; - ar->hw->offchannel_tx_hw_queue = ATH12K_HW_MAX_QUEUES - 1; - ar->hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_HE; + /* TODO Split queues per chip */ + hw->queues = ATH12K_HW_MAX_QUEUES; + hw->wiphy->tx_queue_len = ATH12K_QUEUE_LEN; + hw->offchannel_tx_hw_queue = ATH12K_HW_MAX_QUEUES - 1; + hw->max_rx_aggregation_subframes = IEEE80211_MAX_AMPDU_BUF_EHT; - ar->hw->vif_data_size = sizeof(struct ath12k_vif); - ar->hw->sta_data_size = sizeof(struct ath12k_sta); + hw->vif_data_size = sizeof(struct ath12k_vif); + hw->sta_data_size = sizeof(struct ath12k_sta); - wiphy_ext_feature_set(ar->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); - wiphy_ext_feature_set(ar->hw->wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); + wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); + wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_STA_TX_PWR); + wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); - ar->hw->wiphy->cipher_suites = cipher_suites; - ar->hw->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites); + if (test_bit(WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD, ab->wmi_ab.svc_map)) + wiphy_ext_feature_set(hw->wiphy, + NL80211_EXT_FEATURE_BSS_COLOR); - ar->hw->wiphy->iftype_ext_capab = ath12k_iftypes_ext_capa; - ar->hw->wiphy->num_iftype_ext_capab = - ARRAY_SIZE(ath12k_iftypes_ext_capa); + hw->wiphy->cipher_suites = cipher_suites; + hw->wiphy->n_cipher_suites = ARRAY_SIZE(cipher_suites); - if (ar->supports_6ghz) { - wiphy_ext_feature_set(ar->hw->wiphy, - NL80211_EXT_FEATURE_FILS_DISCOVERY); - wiphy_ext_feature_set(ar->hw->wiphy, - NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); + /* Copy over MLO related capabilities received from + * WMI_SERVICE_READY_EXT2_EVENT if mlo_capable is set + */ + if (ag->mlo_capable) { + ath12k_iftypes_ext_capa[2].eml_capabilities = cap->eml_cap; + ath12k_iftypes_ext_capa[2].mld_capa_and_ops = cap->mld_cap; + if (!test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) + ieee80211_hw_set(hw, MLO_MCAST_MULTI_LINK_TX); } + hw->wiphy->iftype_ext_capab = ath12k_iftypes_ext_capa; + hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(ath12k_iftypes_ext_capa); + + hw->wiphy->mbssid_max_interfaces = ah->num_radio * TARGET_NUM_VDEVS; + hw->wiphy->ema_max_profile_periodicity = TARGET_EMA_MAX_PROFILE_PERIOD; - ath12k_reg_init(ar); + ah->hw->wiphy->regulatory_flags = REGULATORY_WIPHY_SELF_MANAGED; + ah->hw->wiphy->reg_notifier = ath12k_reg_notifier; - if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { - ar->hw->netdev_features = NETIF_F_HW_CSUM; - ieee80211_hw_set(ar->hw, SW_CRYPTO_CONTROL); - ieee80211_hw_set(ar->hw, SUPPORT_FAST_XMIT); + ath12k_vendor_register(ah); + + if (!test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) { + ieee80211_hw_set(hw, SW_CRYPTO_CONTROL); + ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); } - ret = ieee80211_register_hw(ar->hw); + hw->netdev_features |= NETIF_F_LLTX; + + ret = ieee80211_register_hw(hw); if (ret) { - ath12k_err(ar->ab, "ieee80211 registration failed: %d\n", ret); - goto err_free_if_combs; + ath12k_err(NULL, "ieee80211 registration failed: %d\n", ret); + goto err_full_cleanup; } - if (!ab->hw_params->supports_monitor) + if (!ab_dflt->hw_params->supports_monitor) /* There's a race between calling ieee80211_register_hw() * and here where the monitor mode is enabled for a little * while. But that time is so short and in practise it make * a difference in real life. */ - ar->hw->wiphy->interface_modes &= ~BIT(NL80211_IFTYPE_MONITOR); + hw->wiphy->interface_modes &= ~BIT(NL80211_IFTYPE_MONITOR); - /* Apply the regd received during initialization */ + ar = ah->radio; + ab = ar->ab; + + for (i = 0; i < ah->num_radio; i++) { ret = ath12k_regd_update(ar, true); if (ret) { ath12k_err(ar->ab, "ath12k regd update failed: %d\n", ret); goto err_unregister_hw; } + /* fw stats init is separately required since fw pdev stats is also used + * in get_txpower mac ops hence it is handled separately from debugfs + */ + ath12k_fw_stats_init(ar); + + ret = ath12k_debugfs_register(ar); + if (ret) { + ath12k_err(ar->ab, "debugfs registration failed: %d\n", ret); + goto err_unregister_hw; + } + ar++; + } + return 0; err_unregister_hw: - ieee80211_unregister_hw(ar->hw); - -err_free_if_combs: - kfree(ar->hw->wiphy->iface_combinations[0].limits); - kfree(ar->hw->wiphy->iface_combinations); + ar = ah->radio; + for (j = 0; j < i; j++) { + ath12k_fw_stats_free(&ar->fw_stats); + ath12k_debugfs_unregister(ar); + ar++; + } + unregister = true; +err_full_cleanup: + kfree(hw->wiphy->iface_combinations[0].limits); + kfree(hw->wiphy->iface_combinations); + i = ah->num_radio; +err_cleanup: + ar = ah->radio; + for (j = 0; j < i; j++) { + __ath12k_mac_unregister(ar); + ar++; + } -err_free_channels: - kfree(ar->mac.sbands[NL80211_BAND_2GHZ].channels); - kfree(ar->mac.sbands[NL80211_BAND_5GHZ].channels); - kfree(ar->mac.sbands[NL80211_BAND_6GHZ].channels); + if (unregister) { + ieee80211_unregister_hw(hw); + SET_IEEE80211_DEV(hw, NULL); + } -err: - SET_IEEE80211_DEV(ar->hw, NULL); return ret; } -int ath12k_mac_register(struct ath12k_base *ab) +int ath12k_mac_register(struct ath12k_hw_group *ag) { - struct ath12k *ar; - struct ath12k_pdev *pdev; - int i; - int ret; - - if (test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags)) - return 0; + struct ath12k_hw *ah; + int ret, i; - for (i = 0; i < ab->num_radios; i++) { - pdev = &ab->pdevs[i]; - ar = pdev->ar; - if (ab->pdevs_macaddr_valid) { - ether_addr_copy(ar->mac_addr, pdev->mac_addr); - } else { - ether_addr_copy(ar->mac_addr, ab->mac_addr); - ar->mac_addr[4] += i; - } + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; - ret = __ath12k_mac_register(ar); + ret = ath12k_mac_hw_register(ah); if (ret) - goto err_cleanup; - - idr_init(&ar->txmgmt_idr); - spin_lock_init(&ar->txmgmt_idr_lock); + goto err_mac_unregister; } - /* Initialize channel counters frequency value in hertz */ - ab->cc_freq_hz = 320000; - ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS)) - 1; - return 0; -err_cleanup: +err_mac_unregister: for (i = i - 1; i >= 0; i--) { - pdev = &ab->pdevs[i]; - ar = pdev->ar; - __ath12k_mac_unregister(ar); + ah = ag->ah[i]; + if (!ah) + continue; + + ath12k_mac_hw_unregister(ah); } return ret; } -int ath12k_mac_allocate(struct ath12k_base *ab) +static inline struct ath12k *ath12k_mac_get_ar(struct ath12k_hw *ah, + u8 link_idx) +{ + struct ath12k *ar = ah->radio; + + if (link_idx >= ah->num_radio) + return NULL; + + return ar + link_idx; +} + +static int ath12k_mac_setup(struct ath12k_hw *ah, u8 link_id, + struct ath12k_base *ab, int mac_id) { - struct ieee80211_hw *hw; struct ath12k *ar; struct ath12k_pdev *pdev; - int ret; - int i; + struct ath12k_hw_group *ag = ab->ag; + u16 hw_link_id; - if (test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags)) - return 0; + pdev = &ab->pdevs[mac_id]; + hw_link_id = pdev->hw_link_id; - for (i = 0; i < ab->num_radios; i++) { - pdev = &ab->pdevs[i]; - hw = ieee80211_alloc_hw(sizeof(struct ath12k), &ath12k_ops); - if (!hw) { - ath12k_warn(ab, "failed to allocate mac80211 hw device\n"); - ret = -ENOMEM; - goto err_free_mac; + if (hw_link_id >= ATH12K_GROUP_MAX_RADIO) { + ath12k_err(ab, "HW link id %d is not supported\n", hw_link_id); + return -ENOENT; } - ar = hw->priv; - ar->hw = hw; + ar = ath12k_mac_get_ar(ah, link_id); + if (!ar) + return -EINVAL; + ar->ab = ab; + ar->ah = ah; ar->pdev = pdev; - ar->pdev_idx = i; - ar->lmac_id = ath12k_hw_get_mac_from_pdev_id(ab->hw_params, i); + ar->pdev_idx = mac_id; + ar->lmac_id = ath12k_hw_get_mac_from_pdev_id(ab->hw_params, mac_id); + ar->link_idx = link_id; - ar->wmi = &ab->wmi_ab.wmi[i]; - /* FIXME: wmi[0] is already initialized during attach, + ar->wmi = &ab->wmi_ab.wmi[mac_id]; + /* FIXME wmi[0] is already initialized during attach, * Should we do this again? */ - ath12k_wmi_pdev_attach(ab, i); + ath12k_wmi_pdev_attach(ab, mac_id); + + ath12k_mac_fetch_coex_info(ar); ar->cfg_tx_chainmask = pdev->cap.tx_chain_mask; ar->cfg_rx_chainmask = pdev->cap.rx_chain_mask; - ar->num_tx_chains = hweight32(pdev->cap.tx_chain_mask); - ar->num_rx_chains = hweight32(pdev->cap.rx_chain_mask); + ar->num_tx_chains = get_num_chains(pdev->cap.tx_chain_mask); + ar->num_rx_chains = get_num_chains(pdev->cap.rx_chain_mask); pdev->ar = ar; spin_lock_init(&ar->data_lock); @@ -7062,36 +16888,248 @@ init_completion(&ar->bss_survey_done); init_completion(&ar->scan.started); init_completion(&ar->scan.completed); + init_completion(&ar->thermal.wmi_sync); + init_completion(&ar->mlo_setup_done); + init_completion(&ar->mvr_complete); + init_completion(&ar->scan.on_channel); INIT_DELAYED_WORK(&ar->scan.timeout, ath12k_scan_timeout_work); + INIT_WORK(&ar->scan.vdev_del_wk, ath12k_scan_vdev_del_work); + ar->scan.vdev_id = -1; INIT_WORK(&ar->regd_update_work, ath12k_regd_update_work); INIT_WORK(&ar->wmi_mgmt_tx_work, ath12k_mgmt_over_wmi_tx_work); skb_queue_head_init(&ar->wmi_mgmt_tx_queue); - clear_bit(ATH12K_FLAG_MONITOR_ENABLED, &ar->monitor_flags); - } + clear_bit(MONITOR_VDEV_STARTED, &ar->monitor_flags); + ar->monitor_vdev_id = -1; + clear_bit(MONITOR_VDEV_CREATED, &ar->monitor_flags); + rcu_assign_pointer(ag->hw_links[hw_link_id], ar); return 0; +} + +int ath12k_mac_allocate(struct ath12k_hw_group *ag) +{ + struct ieee80211_hw *hw; + struct ath12k_base *ab; + struct ath12k_hw *ah; + struct ieee80211_ops *ops; + size_t len; + int i, j, total_radio, num_radios, ret; + int mac_id, chip_id; + u8 link_id, num_hw; + + total_radio = 0; + for (i = 0; i < ag->num_chip; i++) + total_radio += ag->ab[i]->num_radios; + + /* All pdev get combined and register as single wiphy if MLO capable + * is enabled. where as in other group, each pdev get register separately. + */ + if (ag->mlo_capable) + num_radios = total_radio; + else + num_radios = 1; + + num_hw = total_radio / num_radios; + + if (num_hw >= ATH12K_GROUP_MAX_RADIO) { + ath12k_err(NULL, "HW count %d is not supported\n", num_hw); + return -ENOSPC; + } + + ag->num_hw = 0; + mac_id = 0; + chip_id = 0; + for (i = 0; i < num_hw; i++) { + ops = kmemdup(&ath12k_ops, sizeof(ath12k_ops), GFP_KERNEL); + if (!ops) { + ret = -ENOMEM; + goto err_mac_destroy; + } + + len = sizeof(struct ath12k_hw) + (num_radios * sizeof(struct ath12k)); + hw = ieee80211_alloc_hw(len, ops); + if (!hw) { + kfree(ops); + ret = -ENOMEM; + goto err_mac_destroy; + } + +#ifdef CONFIG_MAC80211_BONDED_SUPPORT + ieee80211_enable_bond_dev(hw); +#endif + ah = hw->priv; + ah->hw = hw; + ah->ops = ops; + ah->num_radio = num_radios; + ag->ah[i] = ah; + ah->ag = ag; + + ath12k_info(NULL, + "ath12k hw device created with %d radios in group %d with %d chips\n", + ah->num_radio, ag->id, ag->num_chip); + + mutex_init(&ah->conf_mutex); + INIT_LIST_HEAD(&ah->ml_peers); + spin_lock_init(&ah->data_lock); + + link_id = 0; + for (j = 0; j < num_radios; j++) { + ab = ag->ab[chip_id]; + ret = ath12k_mac_setup(ah, link_id, ab, mac_id); + if (ret) { + ieee80211_free_hw(ah->hw); + kfree(ops); + ag->ah[i] = NULL; + + ath12k_err(ab, "failed to setup mac %d for chip %d group %d\n", + mac_id, chip_id, ag->id); + goto err_mac_destroy; + } + + link_id++; + mac_id++; + + /* If mac_id falls beyond the current chip MACs then + * move to next chip + */ + if (mac_id >= ab->num_radios) { + chip_id++; + mac_id = 0; -err_free_mac: - ath12k_mac_destroy(ab); + /* Initialize channel counters frequency value in hertz */ + ab->cc_freq_hz = 320000; + + spin_lock_bh(&ab->base_lock); + ab->free_vdev_map = (1LL << (ab->num_radios * TARGET_NUM_VDEVS)) - 1; + spin_unlock_bh(&ab->base_lock); + ret = ath12k_peer_rhash_tbl_init(ab); + if (ret) + goto err_mac_destroy; + ath12k_dp_pdev_pre_alloc(ab); + } + } + + ag->num_hw++; + } + + return 0; + +err_mac_destroy: + ath12k_mac_destroy(ag); return ret; } -void ath12k_mac_destroy(struct ath12k_base *ab) +void ath12k_mac_destroy(struct ath12k_hw_group *ag) { + struct ath12k_base *ab; + struct ath12k_hw *ah; struct ath12k *ar; struct ath12k_pdev *pdev; - int i; + const struct ieee80211_ops *ops; + int i, j; + u16 hw_link_id; + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + if (!ab) + continue; + + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + hw_link_id = pdev->hw_link_id; + + if (hw_link_id < ATH12K_GROUP_MAX_RADIO) { + rcu_assign_pointer(ag->hw_links[hw_link_id], NULL); + + if(!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->ag->dev_flags))) + synchronize_rcu(); + } - for (i = 0; i < ab->num_radios; i++) { - pdev = &ab->pdevs[i]; ar = pdev->ar; if (!ar) continue; - ieee80211_free_hw(ar->hw); pdev->ar = NULL; } + ath12k_peer_rhash_tbl_destroy(ab); + } + + for (i = 0; i < ag->num_hw; i++) { + ah = ag->ah[i]; + if (!ah) + continue; + + ops = ah->ops; + ieee80211_free_hw(ah->hw); + kfree(ops); + ag->ah[i] = NULL; + } +} + +u16 ath12k_calculate_subchannel_count(enum nl80211_chan_width width) { + u16 width_num = 0; + + switch (width) { + case NL80211_CHAN_WIDTH_20_NOHT: + case NL80211_CHAN_WIDTH_20: + width_num = 20; + break; + case NL80211_CHAN_WIDTH_40: + width_num = 40; + break; + case NL80211_CHAN_WIDTH_80: + case NL80211_CHAN_WIDTH_80P80: + width_num = 80; + break; + case NL80211_CHAN_WIDTH_160: + width_num = 160; + break; + case NL80211_CHAN_WIDTH_320: + width_num = 320; + break; + default: + break; + } + return width_num/20; +} + +void ath12k_mac_background_dfs_event(struct ath12k *ar, + enum ath12k_background_dfs_events ev) +{ + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif; + bool arvif_found = false; + int ret = 0; + + list_for_each_entry(arvif, &ar->arvifs, list) { + ahvif = arvif->ahvif; + if (arvif->is_started && + ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + arvif_found = true; + break; + } + } + + if (!arvif_found) + return; + + if (ev == ATH12K_BGDFS_RADAR) { + cfg80211_background_radar_event(ar->ah->hw->wiphy, &ar->agile_chandef, GFP_ATOMIC); + lockdep_assert_held(&ar->conf_mutex); + ret = ath12k_wmi_vdev_adfs_ocac_abort_cmd_send(ar, arvif->vdev_id); + } else if (ev == ATH12K_BGDFS_ABORT) { + cfg80211_background_cac_abort(ar->ah->hw->wiphy); + } + + if (!ret) { + memset(&ar->agile_chandef, 0, sizeof(struct cfg80211_chan_def)); + ar->agile_chandef.chan = NULL; + } else { + ath12k_dbg(ar->ab, ATH12K_DBG_MAC, + "ADFS state can't be reset (ret=%d)\n", + ret); + } } diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/mac.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mac.h --- linux-6.4/drivers/net/wireless/ath/ath12k/mac.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mac.h 2024-04-19 16:04:28.957735776 +0200 @@ -12,12 +12,56 @@ struct ath12k; struct ath12k_base; +struct ath12k_hw; +struct ath12k_hw_group; +struct ath12k_link_sta; struct ath12k_generic_iter { struct ath12k *ar; int ret; }; +struct ath12k_mac_any_chandef_arg { + struct ath12k *ar; + struct cfg80211_chan_def *def; +}; + +struct ath12k_mac_num_chanctxs_arg { + struct ath12k *ar; + int num; +}; + +#define ATH12K_MAC_TX_MGMT_FREE_TYPE_PDEV BIT(0) +#define ATH12K_MAC_TX_MGMT_FREE_TYPE_VIF BIT(1) +#define ATH12K_MAC_TX_MGMT_FREE_TYPE_LINK BIT(2) + +struct ath12k_mac_tx_mgmt_free_arg { + u8 type; + struct ath12k *ar; + struct ieee80211_vif *vif; + u8 link_id; +}; + +struct ath12k_latency_params { + u32 service_interval; + u32 burst_size; + u32 delay_bound; + u32 min_data_rate; + u8 user_priority; + u8 req_type; + u8 ac; + u8 direction; + u8 peer_mac[6]; +}; + +#define ATH12K_LATENCY_PARAM_SIZE sizeof(struct ath12k_latency_params) + +/* Default link after the IEEE802.11 defined Max link id limit + * for driver usage purpose + */ +#define ATH12K_DEFAULT_SCAN_LINK IEEE80211_MLD_MAX_NUM_LINKS +#define ATH12K_NUM_MAX_LINKS (IEEE80211_MLD_MAX_NUM_LINKS + 1) + /* number of failed packets (20 packets with 16 sw reties each) */ #define ATH12K_KICKOUT_THRESHOLD (20 * 16) @@ -33,7 +77,16 @@ #define IEEE80211_VHT_MCS_SUPPORT_0_11_MASK GENMASK(23, 16) #define IEEE80211_DISABLE_VHT_MCS_SUPPORT_0_11 BIT(24) -#define ATH12K_CHAN_WIDTH_NUM 8 +#define ATH12K_CHAN_WIDTH_NUM 14 +#define ATH12K_BW_NSS_MAP_ENABLE BIT(31) +#define ATH12K_PEER_RX_NSS_160MHZ GENMASK(2, 0) +#define ATH12K_PEER_RX_NSS_80_80MHZ GENMASK(5, 3) + +#define ATH12K_OBSS_PD_MAX_THRESHOLD -82 +#define ATH12K_OBSS_PD_THRESHOLD_DISABLED -128 +#define ATH12K_OBSS_PD_THRESHOLD_IN_DBM BIT(29) +#define ATH12K_OBSS_PD_SRG_EN BIT(30) +#define ATH12K_OBSS_PD_NON_SRG_EN BIT(31) #define ATH12K_TX_POWER_MAX_VAL 70 #define ATH12K_TX_POWER_MIN_VAL 0 @@ -43,14 +96,28 @@ ATH12K_BW_40 = 1, ATH12K_BW_80 = 2, ATH12K_BW_160 = 3, + ATH12K_BW_320 = 4, }; +#define ATH12K_PDEV_TX_POWER_INVALID (-1) +#define ATH12K_PDEV_TX_POWER_REFRESH_TIME_MSECS 5000 /* msecs */ + +enum ath12k_background_dfs_events { + ATH12K_BGDFS_SUCCESS, + ATH12K_BGDFS_ABORT, + ATH12K_BGDFS_RADAR, +}; + +#define ATH12K_WLAN_PRIO_MAX 0x63 +#define ATH12K_WLAN_PRIO_WEIGHT 0xff + extern const struct htt_rx_ring_tlv_filter ath12k_mac_mon_status_filter_default; -void ath12k_mac_destroy(struct ath12k_base *ab); -void ath12k_mac_unregister(struct ath12k_base *ab); -int ath12k_mac_register(struct ath12k_base *ab); -int ath12k_mac_allocate(struct ath12k_base *ab); +void ath12k_mac_ap_ps_recalc(struct ath12k *ar); +void ath12k_mac_destroy(struct ath12k_hw_group *ag); +void ath12k_mac_unregister(struct ath12k_hw_group *ag); +int ath12k_mac_register(struct ath12k_hw_group *ag); +int ath12k_mac_allocate(struct ath12k_hw_group *ag); int ath12k_mac_hw_ratecode_to_legacy_rate(u8 hw_rc, u8 preamble, u8 *rateidx, u16 *rate); u8 ath12k_mac_bitrate_to_idx(const struct ieee80211_supported_band *sband, @@ -61,16 +128,85 @@ void __ath12k_mac_scan_finish(struct ath12k *ar); void ath12k_mac_scan_finish(struct ath12k *ar); -struct ath12k_vif *ath12k_mac_get_arvif(struct ath12k *ar, u32 vdev_id); -struct ath12k_vif *ath12k_mac_get_arvif_by_vdev_id(struct ath12k_base *ab, +struct ath12k_link_vif *ath12k_mac_get_arvif(struct ath12k *ar, u32 vdev_id); +struct ath12k_link_vif *ath12k_mac_get_arvif_by_vdev_id(struct ath12k_base *ab, u32 vdev_id); +int ath12k_mac_btcoex_config(struct ath12k *ar, struct ath12k_link_vif *arvif, + int coex, u32 wlan_prio_mask, u8 wlan_weight); struct ath12k *ath12k_mac_get_ar_by_vdev_id(struct ath12k_base *ab, u32 vdev_id); struct ath12k *ath12k_mac_get_ar_by_pdev_id(struct ath12k_base *ab, u32 pdev_id); -void ath12k_mac_drain_tx(struct ath12k *ar); +void ath12k_mac_fill_reg_tpc_info(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ieee80211_chanctx_conf *ctx); +void ath12k_mac_radio_drain_tx(struct ath12k *ar); void ath12k_mac_peer_cleanup_all(struct ath12k *ar); int ath12k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx); enum rate_info_bw ath12k_mac_bw_to_mac80211_bw(enum ath12k_supported_bw bw); +u32 ath12k_mac_he_gi_to_nl80211_he_gi(u8 sgi); +enum nl80211_he_ru_alloc ath12k_mac_phy_he_ru_to_nl80211_he_ru_alloc(u16 ru_phy); +enum nl80211_he_ru_alloc ath12k_mac_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones); +enum nl80211_eht_ru_alloc ath12k_mac_eht_ru_tones_to_nl80211_eht_ru_alloc(u16 ru_tones); enum ath12k_supported_bw ath12k_mac_mac80211_bw_to_ath12k_bw(enum rate_info_bw bw); enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher); +void ath12k_mac_get_any_chandef_iter(struct ieee80211_hw *hw, + struct ieee80211_chanctx_conf *conf, + void *data); +struct ath12k *ath12k_get_ar_by_vif(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + u8 link_id); +int ath12k_mac_mlo_setup(struct ath12k_hw *ah); +int ath12k_mac_mlo_ready(struct ath12k_hw *ah); +int ath12k_mac_mlo_teardown(struct ath12k_hw *ah); +struct ieee80211_bss_conf *ath12k_get_link_bss_conf(struct ath12k_link_vif *arvif); +bool ath12k_mac_is_ml_arvif(struct ath12k_link_vif *arvif); +u16 ath12k_calculate_subchannel_count(enum nl80211_chan_width width); +void ath12k_mac_background_dfs_event(struct ath12k *ar, + enum ath12k_background_dfs_events ev); +bool ath12k_mac_tx_check_max_limit(struct ath12k *ar, struct sk_buff *skb); +int ath12k_mac_mlo_teardown_with_umac_reset(struct ath12k_base *ab); +void ath12k_mac_bss_info_changed(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ieee80211_bss_conf *info, + u64 changed); +int ath12k_mac_radio_start(struct ath12k *ar); +int ath12k_mac_conf_tx(struct ath12k *ar, + struct ath12k_link_vif *arvif, u16 ac, + const struct ieee80211_tx_queue_params *params); +int ath12k_mac_set_key(struct ath12k *ar, + enum set_key_cmd cmd, + struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta, + struct ieee80211_key_conf *key); + +int ath12k_mac_update_sta_state(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct ieee80211_sta *sta, + enum ieee80211_sta_state old_state, + enum ieee80211_sta_state new_state); +void ath12k_mgmt_rx_reo_init_timer(struct ath12k_hw_group *ag); +int ath12k_mac_vdev_create(struct ath12k *ar, struct ath12k_link_vif *arvif); +void ath12k_mac_vif_cache_flush(struct ath12k *ar, struct ieee80211_vif *vif, + u8 link_id); +void ath12k_mac_parse_tx_pwr_env(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ieee80211_chanctx_conf *ctx); +int ath12k_mac_monitor_start(struct ath12k *ar); +int ath12k_mac_mlo_vdev_start(struct ath12k_link_vif *arvif, bool flag); +int ath12k_mac_vdev_start(struct ath12k_link_vif *arvif, + const struct cfg80211_chan_def *chandef, + bool radar_enabled); +int ath12k_mac_monitor_vdev_create(struct ath12k *ar); +int ath12k_mac_monitor_vdev_delete(struct ath12k *ar); +int ath12k_mac_monitor_stop(struct ath12k *ar); +int ath12k_set_vdev_param_to_all_vifs(struct ath12k *ar, int param, u32 value); +void ath12k_mac_reconfig_complete(struct ieee80211_hw *hw, + enum ieee80211_reconfig_type reconfig_type, + struct ath12k *asserted_radio); +int ath12k_mac_partner_peer_cleanup(struct ath12k_base *ab); +void ath12k_bss_assoc(struct ath12k *ar, + struct ath12k_link_vif *arvif, + struct ieee80211_bss_conf *bss_conf); +void ath12k_bss_disassoc(struct ath12k *ar, struct ath12k_link_vif *arvif, + bool do_vdev_down); +int ath12k_mac_op_set_scs(struct wireless_dev *wdev, struct ath12k_latency_params *params); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/mhi.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mhi.c --- linux-6.4/drivers/net/wireless/ath/ath12k/mhi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mhi.c 2024-01-19 17:01:19.869847139 +0100 @@ -6,13 +6,20 @@ #include #include +#include +#include +#include #include "core.h" #include "debug.h" #include "mhi.h" #include "pci.h" +#include "pcic.h" +#include "hif.h" #define MHI_TIMEOUT_DEFAULT_MS 90000 +#define OTP_INVALID_BOARD_ID 0xFFFF +#define OTP_VALID_BOARD_ID_MASK 0x1000 static const struct mhi_channel_config ath12k_mhi_channels_qcn9274[] = { { @@ -252,7 +259,7 @@ int ret, num_vectors, i; int *irq; - ret = ath12k_pci_get_user_msi_assignment(ab, + ret = ath12k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors, &user_base_data, &base_vector); if (ret) @@ -266,7 +273,7 @@ return -ENOMEM; for (i = 0; i < num_vectors; i++) - irq[i] = ath12k_pci_get_msi_irq(ab->dev, + irq[i] = ath12k_hif_get_msi_irq(ab, base_vector + i); ab_pci->mhi_ctrl->irq = irq; @@ -310,21 +317,76 @@ } } +static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state) +{ + switch (mhi_state) { + case ATH12K_MHI_INIT: + return "INIT"; + case ATH12K_MHI_DEINIT: + return "DEINIT"; + case ATH12K_MHI_POWER_ON: + return "POWER_ON"; + case ATH12K_MHI_POWER_OFF: + return "POWER_OFF"; + case ATH12K_MHI_FORCE_POWER_OFF: + return "FORCE_POWER_OFF"; + case ATH12K_MHI_SUSPEND: + return "SUSPEND"; + case ATH12K_MHI_RESUME: + return "RESUME"; + case ATH12K_MHI_TRIGGER_RDDM: + return "TRIGGER_RDDM"; + case ATH12K_MHI_RDDM_DONE: + return "RDDM_DONE"; + case ATH12K_MHI_SOC_RESET: + return "SOC_RESET"; + default: + return "UNKNOWN"; + } +}; + static void ath12k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, enum mhi_callback cb) { struct ath12k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); + struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); - ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s\n", - ath12k_mhi_op_callback_to_str(cb)); + ath12k_dbg(ab, ATH12K_DBG_BOOT, "mhi notify status reason %s mhi_state:%s (0x%lx)\n", + ath12k_mhi_op_callback_to_str(cb), + ath12k_mhi_state_to_str(ab_pci->mhi_state), ab_pci->mhi_state); switch (cb) { case MHI_CB_SYS_ERROR: ath12k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); break; case MHI_CB_EE_RDDM: - if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) + /* check duplicate RDDM received from MHI */ + if (mhi_get_exec_env(ab_pci->mhi_ctrl) == mhi_cntrl->ee) { + ath12k_dbg(ab, ATH12K_DBG_BOOT, "Ignore duplicate status cb %s(%d) received from MHI\n", + ath12k_mhi_op_callback_to_str(cb), + cb); + return; + } + + /* In-case of rddm for mhi soc reset */ + if(test_bit(ATH12K_MHI_SOC_RESET, &ab_pci->mhi_state)) { + ath12k_dbg(ab, ATH12K_DBG_BOOT, "Triggering RDDM from mhi soc reset\n"); + clear_bit(ATH12K_MHI_SOC_RESET, &ab_pci->mhi_state); + complete(&ab->rddm_reset_done); + return; + } + + /* In-case of rddm for fatal error and ab is registered. */ + if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) { + set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); + set_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags); queue_work(ab->workqueue_aux, &ab->reset_work); + ath12k_dbg(ab, ATH12K_DBG_BOOT, "Schedule SSR Recovery reset work queue\n"); + ath12k_hal_dump_srng_stats(ab); + } else { + BUG_ON(1); + } + ath12k_hal_dump_srng_stats(ab); break; default: break; @@ -347,17 +409,77 @@ writel(val, addr); } +static int ath12k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) +{ + struct device_node *np; + struct resource res; + int ret; + + np = of_find_node_by_type(NULL, "memory"); + if (!np) + return -ENOENT; + + ret = of_address_to_resource(np, 0, &res); + if (ret) + return ret; + + mhi_ctrl->iova_start = res.start + 0x1000000; + mhi_ctrl->iova_stop = res.end; + + return 0; +} + int ath12k_mhi_register(struct ath12k_pci *ab_pci) { struct ath12k_base *ab = ab_pci->ab; + struct device *dev = ab->dev; struct mhi_controller *mhi_ctrl; + unsigned int board_id, otp_board_id; + const char *filename = ATH12K_AMSS_FILE; int ret; mhi_ctrl = mhi_alloc_controller(); if (!mhi_ctrl) return -ENOMEM; - ath12k_core_create_firmware_path(ab, ATH12K_AMSS_FILE, + otp_board_id = ath12k_pci_read32(ab, QCN9224_QFPROM_RAW_RFA_PDET_ROW13_LSB); + + board_id = FIELD_GET(OTP_BOARD_ID_MASK, otp_board_id); + if (!board_id || (board_id == OTP_INVALID_BOARD_ID)) { + if (of_property_read_u32(dev->of_node, "qcom,board_id", &board_id)) { + ath12k_warn(ab, "failed to read board id\n"); + } + } + + if (!board_id || (board_id == OTP_INVALID_BOARD_ID)) { + u16 ov_board_id; + + /* look for override */ + if (ath12k_pci_has_board_id_override(ab, &ov_board_id)) { + board_id = ov_board_id; + ath12k_info(ab, + "overriding board-id to 0x%x (%d)\n", + board_id, board_id); + } else { + ath12k_err(ab, + "device has invalid board-id (0x%04x), " + "to use this card you need to setup " + "%s/%s/%s file with " + "this line:\n pci:%s=\n", + board_id, + ATH12K_FW_DIR, ab->hw_params->fw.dir, + ATH12K_BOARD_OVERRIDE_FILE, + pci_name(ab_pci->pdev)); + return -EIO; + } + } + if (board_id & OTP_VALID_BOARD_ID_MASK) { + filename = ATH12K_AMSS_DUALMAC_FILE; + ath12k_dbg(ab, ATH12K_DBG_BOOT, + "dualmac fw selected for board id: %x\n", board_id); + } + + ath12k_core_create_firmware_path(ab, filename, ab_pci->amss_path, sizeof(ab_pci->amss_path)); @@ -367,6 +489,8 @@ mhi_ctrl->regs = ab->mem; mhi_ctrl->reg_len = ab->mem_len; + mhi_ctrl->rddm_size = ATH12K_PCI_FW_RDDM_SZ; + ret = ath12k_mhi_get_msi(ab_pci); if (ret) { ath12k_err(ab, "failed to get msi for mhi\n"); @@ -374,6 +498,15 @@ return ret; } + if (ab->bus_params.fixed_mem_region) { + ret = ath12k_mhi_read_addr_from_dt(mhi_ctrl); + if (ret < 0) + return ret; + } else { + mhi_ctrl->iova_start = 0; + mhi_ctrl->iova_stop = 0xFFFFFFFF; + } + mhi_ctrl->iova_start = 0; mhi_ctrl->iova_stop = 0xffffffff; mhi_ctrl->sbl_size = SZ_512K; @@ -405,32 +538,6 @@ ab_pci->mhi_ctrl = NULL; } -static char *ath12k_mhi_state_to_str(enum ath12k_mhi_state mhi_state) -{ - switch (mhi_state) { - case ATH12K_MHI_INIT: - return "INIT"; - case ATH12K_MHI_DEINIT: - return "DEINIT"; - case ATH12K_MHI_POWER_ON: - return "POWER_ON"; - case ATH12K_MHI_POWER_OFF: - return "POWER_OFF"; - case ATH12K_MHI_FORCE_POWER_OFF: - return "FORCE_POWER_OFF"; - case ATH12K_MHI_SUSPEND: - return "SUSPEND"; - case ATH12K_MHI_RESUME: - return "RESUME"; - case ATH12K_MHI_TRIGGER_RDDM: - return "TRIGGER_RDDM"; - case ATH12K_MHI_RDDM_DONE: - return "RDDM_DONE"; - default: - return "UNKNOWN"; - } -}; - static void ath12k_mhi_set_state_bit(struct ath12k_pci *ab_pci, enum ath12k_mhi_state mhi_state) { @@ -464,6 +571,9 @@ case ATH12K_MHI_RDDM_DONE: set_bit(ATH12K_MHI_RDDM_DONE, &ab_pci->mhi_state); break; + case ATH12K_MHI_SOC_RESET: + set_bit(ATH12K_MHI_SOC_RESET, &ab_pci->mhi_state); + break; default: ath12k_err(ab, "unhandled mhi state (%d)\n", mhi_state); } @@ -506,6 +616,8 @@ break; case ATH12K_MHI_RDDM_DONE: return 0; + case ATH12K_MHI_SOC_RESET: + return 0; default: ath12k_err(ab, "unhandled mhi state: %s(%d)\n", ath12k_mhi_state_to_str(mhi_state), mhi_state); @@ -518,7 +630,7 @@ return -EINVAL; } -static int ath12k_mhi_set_state(struct ath12k_pci *ab_pci, +int ath12k_mhi_set_state(struct ath12k_pci *ab_pci, enum ath12k_mhi_state mhi_state) { struct ath12k_base *ab = ab_pci->ab; @@ -561,6 +673,9 @@ break; case ATH12K_MHI_RDDM_DONE: break; + case ATH12K_MHI_SOC_RESET: + mhi_soc_reset(ab_pci->mhi_ctrl); + break; default: ath12k_err(ab, "unhandled MHI state (%d)\n", mhi_state); ret = -EINVAL; @@ -614,3 +729,8 @@ { ath12k_mhi_set_state(ab_pci, ATH12K_MHI_RESUME); } + +void ath12k_mhi_coredump(struct mhi_controller *mhi_ctrl, bool state) +{ + mhi_download_rddm_image(mhi_ctrl, state); +} diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/mhi.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mhi.h --- linux-6.4/drivers/net/wireless/ath/ath12k/mhi.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/mhi.h 2024-01-19 17:01:19.869847139 +0100 @@ -16,6 +16,7 @@ #define MHISTATUS 0x48 #define MHICTRL 0x38 #define MHICTRL_RESET_MASK 0x2 +#define ATH12K_PCI_FW_RDDM_SZ 0x600000 enum ath12k_mhi_state { ATH12K_MHI_INIT, @@ -28,6 +29,7 @@ ATH12K_MHI_TRIGGER_RDDM, ATH12K_MHI_RDDM, ATH12K_MHI_RDDM_DONE, + ATH12K_MHI_SOC_RESET, }; extern const struct mhi_controller_config ath12k_mhi_config_qcn9274; @@ -42,5 +44,7 @@ void ath12k_mhi_suspend(struct ath12k_pci *ar_pci); void ath12k_mhi_resume(struct ath12k_pci *ar_pci); - +void ath12k_mhi_coredump(struct mhi_controller *mhi_ctrl, bool state); +int ath12k_mhi_set_state(struct ath12k_pci *ab_pci, + enum ath12k_mhi_state mhi_state); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/pci.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/pci.c --- linux-6.4/drivers/net/wireless/ath/ath12k/pci.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/pci.c 2024-03-18 14:40:14.855741442 +0100 @@ -5,31 +5,23 @@ */ #include -#include -#include +#include #include "pci.h" -#include "core.h" -#include "hif.h" #include "mhi.h" #include "debug.h" +#include "ppe.h" +#include "bondif.h" +#include "pcic.h" #define ATH12K_PCI_BAR_NUM 0 #define ATH12K_PCI_DMA_MASK 32 -#define ATH12K_PCI_IRQ_CE0_OFFSET 3 - -#define WINDOW_ENABLE_BIT 0x40000000 -#define WINDOW_REG_ADDRESS 0x310c -#define WINDOW_VALUE_MASK GENMASK(24, 19) -#define WINDOW_START 0x80000 -#define WINDOW_RANGE_MASK GENMASK(18, 0) #define WINDOW_STATIC_MASK GENMASK(31, 6) #define TCSR_SOC_HW_VERSION 0x1B00000 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4) - /* BAR0 + 4k is always accessible, and no * need to force wakeup. * 4K - 32 = 0xFE0 @@ -39,6 +31,16 @@ #define QCN9274_DEVICE_ID 0x1109 #define WCN7850_DEVICE_ID 0x1107 +#define PCIE_PCIE_LOCAL_REG_PCIE_LOCAL_RSV0 0x1E03164 +#define QRTR_INSTANCE_MASK 0x000000FF +#define ATH12K_MAX_PCI_DOMAINS 0x5 + + +unsigned int ath12k_fw_mem_seg; +EXPORT_SYMBOL(ath12k_fw_mem_seg); +module_param_named(fw_mem_seg, ath12k_fw_mem_seg, uint, 0644); +MODULE_PARM_DESC(fw_mem_seg, "Enable/Disable FW segmentted memory"); + static const struct pci_device_id ath12k_pci_id_table[] = { { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) }, { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) }, @@ -47,76 +49,8 @@ MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table); -/* TODO: revisit IRQ mapping for new SRNG's */ -static const struct ath12k_msi_config ath12k_msi_config[] = { - { - .total_vectors = 16, - .total_users = 3, - .users = (struct ath12k_msi_user[]) { - { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, - { .name = "CE", .num_vectors = 5, .base_vector = 3 }, - { .name = "DP", .num_vectors = 8, .base_vector = 8 }, - }, - }, -}; - -static const char *irq_name[ATH12K_IRQ_NUM_MAX] = { - "bhi", - "mhi-er0", - "mhi-er1", - "ce0", - "ce1", - "ce2", - "ce3", - "ce4", - "ce5", - "ce6", - "ce7", - "ce8", - "ce9", - "ce10", - "ce11", - "ce12", - "ce13", - "ce14", - "ce15", - "host2wbm-desc-feed", - "host2reo-re-injection", - "host2reo-command", - "host2rxdma-monitor-ring3", - "host2rxdma-monitor-ring2", - "host2rxdma-monitor-ring1", - "reo2ost-exception", - "wbm2host-rx-release", - "reo2host-status", - "reo2host-destination-ring4", - "reo2host-destination-ring3", - "reo2host-destination-ring2", - "reo2host-destination-ring1", - "rxdma2host-monitor-destination-mac3", - "rxdma2host-monitor-destination-mac2", - "rxdma2host-monitor-destination-mac1", - "ppdu-end-interrupts-mac3", - "ppdu-end-interrupts-mac2", - "ppdu-end-interrupts-mac1", - "rxdma2host-monitor-status-ring-mac3", - "rxdma2host-monitor-status-ring-mac2", - "rxdma2host-monitor-status-ring-mac1", - "host2rxdma-host-buf-ring-mac3", - "host2rxdma-host-buf-ring-mac2", - "host2rxdma-host-buf-ring-mac1", - "rxdma2host-destination-ring-mac3", - "rxdma2host-destination-ring-mac2", - "rxdma2host-destination-ring-mac1", - "host2tcl-input-ring4", - "host2tcl-input-ring3", - "host2tcl-input-ring2", - "host2tcl-input-ring1", - "wbm2host-tx-completions-ring4", - "wbm2host-tx-completions-ring3", - "wbm2host-tx-completions-ring2", - "wbm2host-tx-completions-ring1", - "tcl2host-status-ring", +static const struct ath12k_bus_params ath12k_pci_bus_params = { + .fixed_bdf_addr = false, }; static int ath12k_pci_bus_wake_up(struct ath12k_base *ab) @@ -164,8 +98,9 @@ } } -static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci) +static void ath12k_pci_select_static_window(struct ath12k_base *ab) { + struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK); u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK); u32 window; @@ -176,30 +111,7 @@ ab_pci->register_window = window; spin_unlock_bh(&ab_pci->window_lock); - iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); -} - -static u32 ath12k_pci_get_window_start(struct ath12k_base *ab, - u32 offset) -{ - u32 window_start; - - /* If offset lies within DP register range, use 3rd window */ - if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) - window_start = 3 * WINDOW_START; - /* If offset lies within CE register range, use 2nd window */ - else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) - window_start = 2 * WINDOW_START; - /* If offset lies within PCI_BAR_WINDOW0_BASE and within PCI_SOC_PCI_REG_BASE - * use 0th window - */ - else if (((offset ^ PCI_BAR_WINDOW0_BASE) < WINDOW_RANGE_MASK) && - !((offset ^ PCI_SOC_PCI_REG_BASE) < PCI_SOC_RANGE_MASK)) - window_start = 0; - else - window_start = WINDOW_START; - - return window_start; + iowrite32(WINDOW_ENABLE_BIT | window, ab->mem + WINDOW_REG_ADDRESS); } static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) @@ -313,10 +225,15 @@ static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) { + mdelay(100); + if (power_on) { ath12k_pci_enable_ltssm(ab); ath12k_pci_clear_all_intrs(ab); ath12k_pci_set_wlaon_pwr_ctrl(ab); + + if (ab->hw_params->fix_l1ss) + ath12k_dbg(ab, ATH12K_DBG_PCI, "L1ss fix required\n"); } ath12k_mhi_clear_vector(ab); @@ -325,294 +242,160 @@ ath12k_mhi_set_mhictrl_reset(ab); } -static void ath12k_pci_free_ext_irq(struct ath12k_base *ab) -{ - int i, j; - - for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { - struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; - - for (j = 0; j < irq_grp->num_irq; j++) - free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); - - netif_napi_del(&irq_grp->napi); - } -} - -static void ath12k_pci_free_irq(struct ath12k_base *ab) -{ - int i, irq_idx; - - for (i = 0; i < ab->hw_params->ce_count; i++) { - if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) - continue; - irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; - free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); - } - - ath12k_pci_free_ext_irq(ab); -} - -static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id) -{ - u32 irq_idx; - - irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; - enable_irq(ab->irq_num[irq_idx]); -} - -static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id) -{ - u32 irq_idx; - - irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; - disable_irq_nosync(ab->irq_num[irq_idx]); -} - -static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab) -{ - int i; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +int ath12k_pci_ppeds_register_interrupts(struct ath12k_base *ab, int type, int vector, + int ring_num) +{ + struct ath12k_pci *ar_pci = (struct ath12k_pci *)ab->drv_priv; + int irq; + u8 bus_id = pci_domain_nr(ar_pci->pdev->bus); + int ret; - for (i = 0; i < ab->hw_params->ce_count; i++) { - if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) - continue; - ath12k_pci_ce_irq_disable(ab, i); - } + if (ab->ppeds_node_idx == -1) { + ath12k_err(ab, "invalid ppeds_node_idx in ppeds_register_interrupts\n"); + return -EINVAL; } -static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab) -{ - int i; - int irq_idx; - - for (i = 0; i < ab->hw_params->ce_count; i++) { - if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) - continue; + irq = ath12k_hif_get_msi_irq(ab, vector); - irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; - synchronize_irq(ab->irq_num[irq_idx]); - } + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + if (type == HAL_PPE2TCL) { + snprintf(&ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE2TCL], sizeof(ab->dp.ppeds_irq_name), + "pci%d_ppe2tcl_%d", bus_id, ab->ppeds_node_idx); + ret = request_irq(irq, ath12k_ds_ppe2tcl_irq_handler, + IRQF_SHARED, + ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE2TCL], (void *)ath12k_dp_get_ppe_ds_ctxt(ab)); + if (ret) + goto irq_fail; + ab->dp.ppeds_irq[PPEDS_IRQ_PPE2TCL] = irq; + } else if (type == HAL_REO2PPE) { + snprintf(&ab->dp.ppeds_irq_name[PPEDS_IRQ_REO2PPE], sizeof(ab->dp.ppeds_irq_name), + "pci%d_reo2ppe_%d", bus_id, ab->ppeds_node_idx); + ret = request_irq(irq, ath12k_ds_reo2ppe_irq_handler, + IRQF_SHARED, + ab->dp.ppeds_irq_name[PPEDS_IRQ_REO2PPE], (void *)ath12k_dp_get_ppe_ds_ctxt(ab)); + if (ret) + goto irq_fail; + ab->dp.ppeds_irq[PPEDS_IRQ_REO2PPE] = irq; + } else if (type == HAL_WBM2SW_RELEASE && ring_num == HAL_WBM2SW_PPEDS_TX_CMPLN_RING_NUM) { + snprintf(&ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE_WBM2SW_REL], sizeof(ab->dp.ppeds_irq_name), + "pci%d_ppe_wbm_rel_%d", bus_id, ab->ppeds_node_idx); + ret = request_irq(irq, ath12k_dp_ppeds_handle_tx_comp, + IRQF_SHARED, + ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE_WBM2SW_REL],(void *)ab); + if (ret) + goto irq_fail; + ab->dp.ppeds_irq[PPEDS_IRQ_PPE_WBM2SW_REL] = irq; + } else { + return 0; } + disable_irq_nosync(irq); -static void ath12k_pci_ce_tasklet(struct tasklet_struct *t) -{ - struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); - - ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); + return 0; - ath12k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); +irq_fail: + return ret; } -static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg) +void ath12k_pci_ppeds_irq_disable(struct ath12k_base *ab, enum ppeds_irq_type type) { - struct ath12k_ce_pipe *ce_pipe = arg; - - /* last interrupt received for this CE */ - ce_pipe->timestamp = jiffies; - - ath12k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); - tasklet_schedule(&ce_pipe->intr_tq); - - return IRQ_HANDLED; + disable_irq_nosync(ab->dp.ppeds_irq[type]); } -static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp) +void ath12k_pci_ppeds_irq_enable(struct ath12k_base *ab, enum ppeds_irq_type type) { - int i; - - for (i = 0; i < irq_grp->num_irq; i++) - disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); + enable_irq(ab->dp.ppeds_irq[type]); } -static void __ath12k_pci_ext_irq_disable(struct ath12k_base *sc) +void ath12k_pci_ppeds_free_interrupts(struct ath12k_base *ab) { - int i; - - for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { - struct ath12k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; + disable_irq_nosync(ab->dp.ppeds_irq[PPEDS_IRQ_PPE2TCL]); + free_irq(ab->dp.ppeds_irq[PPEDS_IRQ_PPE2TCL], ath12k_dp_get_ppe_ds_ctxt(ab)); - ath12k_pci_ext_grp_disable(irq_grp); + disable_irq_nosync(ab->dp.ppeds_irq[PPEDS_IRQ_REO2PPE]); + free_irq(ab->dp.ppeds_irq[PPEDS_IRQ_REO2PPE], ath12k_dp_get_ppe_ds_ctxt(ab)); - napi_synchronize(&irq_grp->napi); - napi_disable(&irq_grp->napi); + disable_irq_nosync(ab->dp.ppeds_irq[PPEDS_IRQ_PPE_WBM2SW_REL]); + free_irq(ab->dp.ppeds_irq[PPEDS_IRQ_PPE_WBM2SW_REL], ab); } -} - -static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp) -{ - int i; +#endif - for (i = 0; i < irq_grp->num_irq; i++) - enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); -} - -static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab) +int ath12k_pci_get_msi_irq(struct ath12k_base *ab, unsigned int vector) { - int i, j, irq_idx; - - for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { - struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + struct device *dev = ab->dev; + struct pci_dev *pci_dev = to_pci_dev(dev); - for (j = 0; j < irq_grp->num_irq; j++) { - irq_idx = irq_grp->irqs[j]; - synchronize_irq(ab->irq_num[irq_idx]); - } - } + return pci_irq_vector(pci_dev, vector); } -static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) +static void ath12k_umac_reset_tasklet_handler(struct tasklet_struct *t) { - struct ath12k_ext_irq_grp *irq_grp = container_of(napi, - struct ath12k_ext_irq_grp, - napi); - struct ath12k_base *ab = irq_grp->ab; - int work_done; + struct ath12k_dp_umac_reset *umac_reset = from_tasklet(umac_reset, t, intr_tq); + struct ath12k_base *ab = container_of(umac_reset, struct ath12k_base, dp_umac_reset); - work_done = ath12k_dp_service_srng(ab, irq_grp, budget); - if (work_done < budget) { - napi_complete_done(napi, work_done); - ath12k_pci_ext_grp_enable(irq_grp); + ath12k_dp_umac_reset_handle(ab); + enable_irq(umac_reset->irq_num); } - if (work_done > budget) - work_done = budget; - - return work_done; -} - -static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg) +static irqreturn_t ath12k_dp_umac_reset_interrupt_handler(int irq, void *arg) { - struct ath12k_ext_irq_grp *irq_grp = arg; - - ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); - - /* last interrupt received for this group */ - irq_grp->timestamp = jiffies; - - ath12k_pci_ext_grp_disable(irq_grp); - - napi_schedule(&irq_grp->napi); + struct ath12k_base *ab = arg; + struct ath12k_dp_umac_reset *umac_reset = &ab->dp_umac_reset; + disable_irq_nosync(umac_reset->irq_num); + tasklet_schedule(&umac_reset->intr_tq); return IRQ_HANDLED; } -static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) +static void ath12k_dp_umac_reset_enable_irq(struct ath12k_base *ab) { - int i, j, ret, num_vectors = 0; - u32 user_base_data = 0, base_vector = 0, base_idx; - - base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; - ret = ath12k_pci_get_user_msi_assignment(ab, "DP", - &num_vectors, - &user_base_data, - &base_vector); - if (ret < 0) - return ret; - - for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { - struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; - u32 num_irq = 0; - - irq_grp->ab = ab; - irq_grp->grp_id = i; - init_dummy_netdev(&irq_grp->napi_ndev); - netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, - ath12k_pci_ext_grp_napi_poll); - - if (ab->hw_params->ring_mask->tx[i] || - ab->hw_params->ring_mask->rx[i] || - ab->hw_params->ring_mask->rx_err[i] || - ab->hw_params->ring_mask->rx_wbm_rel[i] || - ab->hw_params->ring_mask->reo_status[i] || - ab->hw_params->ring_mask->host2rxdma[i] || - ab->hw_params->ring_mask->rx_mon_dest[i]) { - num_irq = 1; - } - - irq_grp->num_irq = num_irq; - irq_grp->irqs[0] = base_idx + i; - - for (j = 0; j < irq_grp->num_irq; j++) { - int irq_idx = irq_grp->irqs[j]; - int vector = (i % num_vectors) + base_vector; - int irq = ath12k_pci_get_msi_irq(ab->dev, vector); + struct ath12k_dp_umac_reset *umac_reset = &ab->dp_umac_reset; - ab->irq_num[irq_idx] = irq; - - ath12k_dbg(ab, ATH12K_DBG_PCI, - "irq:%d group:%d\n", irq, i); - - irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); - ret = request_irq(irq, ath12k_pci_ext_interrupt_handler, - IRQF_SHARED, - "DP_EXT_IRQ", irq_grp); - if (ret) { - ath12k_err(ab, "failed request irq %d: %d\n", - vector, ret); - return ret; - } - - disable_irq_nosync(ab->irq_num[irq_idx]); - } - } - - return 0; + enable_irq(umac_reset->irq_num); } -static int ath12k_pci_config_irq(struct ath12k_base *ab) +static int ath12k_dp_umac_pci_config_irq(struct ath12k_base *ab) { - struct ath12k_ce_pipe *ce_pipe; - u32 msi_data_start; - u32 msi_data_count, msi_data_idx; - u32 msi_irq_start; + u32 msi_data_start, msi_data_count, msi_irq_start; unsigned int msi_data; - int irq, i, ret, irq_idx; + int irq, ret; + struct ath12k_dp_umac_reset *umac_reset = &ab->dp_umac_reset; - ret = ath12k_pci_get_user_msi_assignment(ab, - "CE", &msi_data_count, + ret = ath12k_pcic_get_user_msi_assignment(ab, "DP", &msi_data_count, &msi_data_start, &msi_irq_start); if (ret) return ret; - /* Configure CE irqs */ + msi_data = (umac_reset->intr_offset % msi_data_count) + msi_irq_start; + irq = ath12k_pci_get_msi_irq(ab, msi_data); + umac_reset->irq_num = irq; + tasklet_setup(&umac_reset->intr_tq, ath12k_umac_reset_tasklet_handler); - for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { - if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) - continue; - - msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; - irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); - ce_pipe = &ab->ce.ce_pipe[i]; - - irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; - - tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet); - - ret = request_irq(irq, ath12k_pci_ce_interrupt_handler, - IRQF_SHARED, irq_name[irq_idx], - ce_pipe); + ret = request_irq(irq, ath12k_dp_umac_reset_interrupt_handler, + IRQF_NO_SUSPEND, "umac_dp_reset", ab); if (ret) { - ath12k_err(ab, "failed to request irq %d: %d\n", - irq_idx, ret); + ath12k_err(ab, "failed to request irq for umac dp reset %d\n", ret); return ret; } - ab->irq_num[irq_idx] = irq; - msi_data_idx++; + disable_irq_nosync(umac_reset->irq_num); - ath12k_pci_ce_irq_disable(ab, i); + return 0; } - ret = ath12k_pci_ext_irq_config(ab); - if (ret) - return ret; +static void ath12k_dp_umac_reset_free_irq(struct ath12k_base *ab) +{ + struct ath12k_dp_umac_reset *umac_reset = &ab->dp_umac_reset; - return 0; + disable_irq_nosync(umac_reset->irq_num); + free_irq(umac_reset->irq_num, ab); } static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab) { struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; + struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); + struct pci_bus *bus = ab_pci->pdev->bus; cfg->tgt_ce = ab->hw_params->target_ce_config; cfg->tgt_ce_len = ab->hw_params->target_ce_count; @@ -620,17 +403,10 @@ cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; -} - -static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab) -{ - int i; - for (i = 0; i < ab->hw_params->ce_count; i++) { - if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) - continue; - ath12k_pci_ce_irq_enable(ab, i); - } + ab_pci->instance = (((pci_domain_nr(bus) & 0xF) << 4) | + (bus->number & 0xF)) & QRTR_INSTANCE_MASK; + ab->qmi.service_ins_id += ab_pci->instance; } static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable) @@ -661,7 +437,7 @@ static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci) { struct ath12k_base *ab = ab_pci->ab; - const struct ath12k_msi_config *msi_config = ab_pci->msi_config; + const struct ath12k_msi_config *msi_config = ab->msi.config; struct msi_desc *msi_desc; int num_vectors; int ret; @@ -689,11 +465,11 @@ goto free_msi_vector; } - ab_pci->msi_ep_base_data = msi_desc->msg.data; + ab->msi.ep_base_data = msi_desc->msg.data; if (msi_desc->pci.msi_attrib.is_64) set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); - ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); + ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab->msi.ep_base_data); return 0; @@ -800,110 +576,32 @@ set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); } -static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) -{ - if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) - pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, - ab_pci->link_ctl); -} - -static void ath12k_pci_kill_tasklets(struct ath12k_base *ab) -{ - int i; - - for (i = 0; i < ab->hw_params->ce_count; i++) { - struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; - - if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) - continue; - - tasklet_kill(&ce_pipe->intr_tq); - } -} - -static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab) -{ - ath12k_pci_ce_irqs_disable(ab); - ath12k_pci_sync_ce_irqs(ab); - ath12k_pci_kill_tasklets(ab); -} - -int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, - u8 *ul_pipe, u8 *dl_pipe) -{ - const struct service_to_pipe *entry; - bool ul_set = false, dl_set = false; - int i; - - for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { - entry = &ab->hw_params->svc_to_ce_map[i]; - - if (__le32_to_cpu(entry->service_id) != service_id) - continue; - - switch (__le32_to_cpu(entry->pipedir)) { - case PIPEDIR_NONE: - break; - case PIPEDIR_IN: - WARN_ON(dl_set); - *dl_pipe = __le32_to_cpu(entry->pipenum); - dl_set = true; - break; - case PIPEDIR_OUT: - WARN_ON(ul_set); - *ul_pipe = __le32_to_cpu(entry->pipenum); - ul_set = true; - break; - case PIPEDIR_INOUT: - WARN_ON(dl_set); - WARN_ON(ul_set); - *dl_pipe = __le32_to_cpu(entry->pipenum); - *ul_pipe = __le32_to_cpu(entry->pipenum); - dl_set = true; - ul_set = true; - break; - } - } - - if (WARN_ON(!ul_set || !dl_set)) - return -ENOENT; - - return 0; -} - -int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector) -{ - struct pci_dev *pci_dev = to_pci_dev(dev); - - return pci_irq_vector(pci_dev, vector); -} - -int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, - int *num_vectors, u32 *user_base_data, - u32 *base_vector) +static void ath12k_pci_update_qrtr_node_id(struct ath12k_base *ab) { struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); - const struct ath12k_msi_config *msi_config = ab_pci->msi_config; - int idx; + u32 reg; - for (idx = 0; idx < msi_config->total_users; idx++) { - if (strcmp(user_name, msi_config->users[idx].name) == 0) { - *num_vectors = msi_config->users[idx].num_vectors; - *user_base_data = msi_config->users[idx].base_vector - + ab_pci->msi_ep_base_data; - *base_vector = msi_config->users[idx].base_vector; - - ath12k_dbg(ab, ATH12K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", - user_name, *num_vectors, *user_base_data, - *base_vector); + /* + * On platforms with two or more identical mhi devices, qmi service run + * with identical qrtr-node-id. Because of this identical ID qrtr-lookup + * cannot register more than one qmi service with identical node ID. + * + * This generates a unique instance ID from PCIe domain number and bus number, + * writes to the given register, it is available for firmware when the QMI service + * is spawned. + */ + reg = PCIE_PCIE_LOCAL_REG_PCIE_LOCAL_RSV0 & WINDOW_RANGE_MASK; + ath12k_pci_write32(ab, reg, ab_pci->instance); - return 0; - } + ath12k_dbg(ab, ATH12K_DBG_PCI, "pci reg 0x%x instance 0x%x read val 0x%x\n", + reg, ab_pci->instance, ath12k_pci_read32(ab, reg)); } - ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); - - return -EINVAL; +static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) +{ + if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) + pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, + ab_pci->link_ctl); } void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, @@ -942,30 +640,12 @@ void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab) { - ath12k_pci_ce_irqs_enable(ab); + ath12k_pcic_ce_irqs_enable(ab); } void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab) { - ath12k_pci_ce_irq_disable_sync(ab); -} - -void ath12k_pci_ext_irq_enable(struct ath12k_base *ab) -{ - int i; - - for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { - struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; - - napi_enable(&irq_grp->napi); - ath12k_pci_ext_grp_enable(irq_grp); - } -} - -void ath12k_pci_ext_irq_disable(struct ath12k_base *ab) -{ - __ath12k_pci_ext_irq_disable(ab); - ath12k_pci_sync_ext_irqs(ab); + ath12k_pcic_ce_irq_disable_sync(ab); } int ath12k_pci_hif_suspend(struct ath12k_base *ab) @@ -986,12 +666,6 @@ return 0; } -void ath12k_pci_stop(struct ath12k_base *ab) -{ - ath12k_pci_ce_irq_disable_sync(ab); - ath12k_ce_cleanup_pipes(ab); -} - int ath12k_pci_start(struct ath12k_base *ab) { struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); @@ -1000,17 +674,25 @@ ath12k_pci_aspm_restore(ab_pci); - ath12k_pci_ce_irqs_enable(ab); - ath12k_ce_rx_post_buf(ab); - + ath12k_pcic_start(ab); return 0; } +#define PCI_BAR_WINDOW0_BASE 0x1E00000 +#define PCI_BAR_WINDOW0_END 0x1E7FFFC +#define PCI_SOC_PCI_REG_BASE 0x1E04000 +#define PCI_SOC_PCI_REG_END 0x1E07FFC +#define PCI_PARF_BASE 0x1E08000 +#define PCI_PARF_END 0x1E0BFFC +#define PCI_MHIREGLEN_REG 0x1E0E100 +#define PCI_MHI_REGION_END 0x1E0EFFC + u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset) { struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); u32 val, window_start; int ret = 0; + bool is_window0; /* for offset beyond BAR + 4K - 32, may * need to wakeup MHI to access. @@ -1023,22 +705,30 @@ val = ioread32(ab->mem + offset); } else { if (ab->static_window_map) - window_start = ath12k_pci_get_window_start(ab, offset); + window_start = ath12k_pcic_get_window_start(ab, offset); else window_start = WINDOW_START; if (window_start == WINDOW_START) { spin_lock_bh(&ab_pci->window_lock); ath12k_pci_select_window(ab_pci, offset); + + is_window0 = ((offset >= PCI_BAR_WINDOW0_BASE && + offset <= PCI_BAR_WINDOW0_END) && + (offset >= PCI_MHIREGLEN_REG && + offset <= PCI_MHI_REGION_END)); + + if (is_window0) { + offset = offset - PCI_MHIREGLEN_REG; + + val = ioread32(ab->mem + (offset & WINDOW_RANGE_MASK)); + + } else { val = ioread32(ab->mem + window_start + (offset & WINDOW_RANGE_MASK)); + } spin_unlock_bh(&ab_pci->window_lock); } else { - if ((!window_start) && - (offset >= PCI_MHIREGLEN_REG && - offset <= PCI_MHI_REGION_END)) - offset = offset - PCI_MHIREGLEN_REG; - val = ioread32(ab->mem + window_start + (offset & WINDOW_RANGE_MASK)); } @@ -1056,6 +746,7 @@ struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); u32 window_start; int ret = 0; + bool is_window0; /* for offset beyond BAR + 4K - 32, may * need to wakeup MHI to access. @@ -1068,22 +759,30 @@ iowrite32(value, ab->mem + offset); } else { if (ab->static_window_map) - window_start = ath12k_pci_get_window_start(ab, offset); + window_start = ath12k_pcic_get_window_start(ab, offset); else window_start = WINDOW_START; if (window_start == WINDOW_START) { spin_lock_bh(&ab_pci->window_lock); ath12k_pci_select_window(ab_pci, offset); + + is_window0 = ((offset >= PCI_BAR_WINDOW0_BASE && + offset <= PCI_BAR_WINDOW0_END) && + (offset >= PCI_MHIREGLEN_REG && + offset <= PCI_MHI_REGION_END)); + + if (is_window0) { + offset = offset - PCI_MHIREGLEN_REG; + + iowrite32(value, ab->mem + + (offset & WINDOW_RANGE_MASK)); + } else { iowrite32(value, ab->mem + window_start + (offset & WINDOW_RANGE_MASK)); + } spin_unlock_bh(&ab_pci->window_lock); } else { - if ((!window_start) && - (offset >= PCI_MHIREGLEN_REG && - offset <= PCI_MHI_REGION_END)) - offset = offset - PCI_MHIREGLEN_REG; - iowrite32(value, ab->mem + window_start + (offset & WINDOW_RANGE_MASK)); } @@ -1111,6 +810,8 @@ ath12k_pci_msi_enable(ab_pci); + ath12k_pci_update_qrtr_node_id(ab); + ret = ath12k_mhi_start(ab_pci); if (ret) { ath12k_err(ab, "failed to start mhi: %d\n", ret); @@ -1118,7 +819,7 @@ } if (ab->static_window_map) - ath12k_pci_select_static_window(ab_pci); + ath12k_pci_select_static_window(ab); return 0; } @@ -1127,35 +828,81 @@ { struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); + + ath12k_mhi_set_state(ab_pci, ATH12K_MHI_SOC_RESET); + if (!wait_for_completion_timeout(&ab->rddm_reset_done, msecs_to_jiffies(200))) { + ath12k_warn(ab, "failed to set RDDM mode\n"); + if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags)) { + ath12k_warn(ab, "failed to clear MHI SOC RESET as mhi already in rddm state due to recovery in progress, clearing it here\n"); + clear_bit(ATH12K_MHI_SOC_RESET, &ab_pci->mhi_state); + reinit_completion(&ab->rddm_reset_done); + } + } + if (!(test_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags))) { + ath12k_qmi_free_target_mem_chunk(ab); + } /* restore aspm in case firmware bootup fails */ ath12k_pci_aspm_restore(ab_pci); + clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); ath12k_pci_force_wake(ab_pci->ab); ath12k_pci_msi_disable(ab_pci); ath12k_mhi_stop(ab_pci); - clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); ath12k_pci_sw_reset(ab_pci->ab, false); } static const struct ath12k_hif_ops ath12k_pci_hif_ops = { .start = ath12k_pci_start, - .stop = ath12k_pci_stop, + .stop = ath12k_pcic_stop, .read32 = ath12k_pci_read32, .write32 = ath12k_pci_write32, .power_down = ath12k_pci_power_down, .power_up = ath12k_pci_power_up, .suspend = ath12k_pci_hif_suspend, .resume = ath12k_pci_hif_resume, - .irq_enable = ath12k_pci_ext_irq_enable, - .irq_disable = ath12k_pci_ext_irq_disable, + .irq_enable = ath12k_pcic_ext_irq_enable, + .irq_disable = ath12k_pcic_ext_irq_disable, .get_msi_address = ath12k_pci_get_msi_address, - .get_user_msi_vector = ath12k_pci_get_user_msi_assignment, - .map_service_to_pipe = ath12k_pci_map_service_to_pipe, + .get_user_msi_vector = ath12k_pcic_get_user_msi_assignment, + .map_service_to_pipe = ath12k_pcic_map_service_to_pipe, .ce_irq_enable = ath12k_pci_hif_ce_irq_enable, .ce_irq_disable = ath12k_pci_hif_ce_irq_disable, .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx, +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + .ppeds_register_interrupts = ath12k_pci_ppeds_register_interrupts, + .ppeds_free_interrupts = ath12k_pci_ppeds_free_interrupts, + .ppeds_irq_enable = ath12k_pci_ppeds_irq_enable, + .ppeds_irq_disable = ath12k_pci_ppeds_irq_disable, +#endif + .dp_umac_reset_irq_config = ath12k_dp_umac_pci_config_irq, + .dp_umac_reset_enable_irq = ath12k_dp_umac_reset_enable_irq, + .dp_umac_reset_free_irq = ath12k_dp_umac_reset_free_irq, + .get_msi_irq = ath12k_pci_get_msi_irq, }; +bool ath12k_pci_has_board_id_override(struct ath12k_base *ab, + u16 *ov_board_id) +{ + struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); + struct pci_dev *pdev = ab_pci->pdev; + const struct ath12k_bid_override *ov; + + list_for_each_entry(ov, &ab->board_id_overrides, next) { + if (ov->domain != pci_domain_nr(pdev->bus)) + continue; + + if (ov->bus_nr != pdev->bus->number) + continue; + + if (pdev->devfn != PCI_DEVFN(ov->slot, ov->func)) + continue; + + *ov_board_id = ov->board_id; + return true; + } + return false; +} + static void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor) { @@ -1178,9 +925,13 @@ struct ath12k_base *ab; struct ath12k_pci *ab_pci; u32 soc_hw_version_major, soc_hw_version_minor; + u32 addr; int ret; - - ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + ath12k_bond_enable_ppe_ds(); +#endif + ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI, + &ath12k_pci_bus_params); if (!ab) { dev_err(&pdev->dev, "failed to allocate ath12k base\n"); return -ENOMEM; @@ -1193,9 +944,21 @@ ab_pci->ab = ab; ab_pci->pdev = pdev; ab->hif.ops = &ath12k_pci_hif_ops; + ab->fw_mode = ATH12K_FIRMWARE_MODE_NORMAL; pci_set_drvdata(pdev, ab); spin_lock_init(&ab_pci->window_lock); + /* Set fixed_mem_region to true for platforms support reserved memory + * from DT. If memory is reserved from DT for FW, ath11k driver need not + * allocate memory. + */ + if (!of_property_read_u32(ab->dev->of_node, "memory-region", &addr)) + ab->bus_params.fixed_mem_region = true; + + /* This is HACK to bring up the qcn9224 with segemnted memory */ + if (ath12k_fw_mem_seg) + ab->bus_params.fixed_mem_region = false; + ret = ath12k_pci_claim(ab_pci, pdev); if (ret) { ath12k_err(ab, "failed to claim device: %d\n", ret); @@ -1204,7 +967,7 @@ switch (pci_dev->device) { case QCN9274_DEVICE_ID: - ab_pci->msi_config = &ath12k_msi_config[0]; + ab->msi.config = &ath12k_msi_config[ATH12K_MSI_CONFIG_PCI]; ab->static_window_map = true; ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; ath12k_pci_read_hw_version(ab, &soc_hw_version_major, @@ -1225,10 +988,22 @@ } break; case WCN7850_DEVICE_ID: - ab_pci->msi_config = &ath12k_msi_config[0]; + ab->msi.config = &ath12k_msi_config[ATH12K_MSI_CONFIG_PCI]; ab->static_window_map = false; - ab->hw_rev = ATH12K_HW_WCN7850_HW20; ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; + ath12k_pci_read_hw_version(ab, &soc_hw_version_major, + &soc_hw_version_minor); + switch (soc_hw_version_major) { + case ATH12K_PCI_SOC_HW_VERSION_2: + ab->hw_rev = ATH12K_HW_WCN7850_HW20; + break; + default: + dev_err(&pdev->dev, + "Unknown hardware version found for WCN7850: 0x%x\n", + soc_hw_version_major); + ret = -EOPNOTSUPP; + goto err_pci_free_region; + } break; default: @@ -1266,7 +1041,7 @@ ath12k_pci_init_qmi_ce_config(ab); - ret = ath12k_pci_config_irq(ab); + ret = ath12k_pcic_config_irq(ab); if (ret) { ath12k_err(ab, "failed to config irq: %d\n", ret); goto err_ce_free; @@ -1277,10 +1052,11 @@ ath12k_err(ab, "failed to init core: %d\n", ret); goto err_free_irq; } + return 0; err_free_irq: - ath12k_pci_free_irq(ab); + ath12k_pcic_free_irq(ab); err_ce_free: ath12k_ce_free_pipes(ab); @@ -1310,11 +1086,13 @@ if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { ath12k_pci_power_down(ab); + ath12k_debugfs_soc_destroy(ab); ath12k_qmi_deinit_service(ab); + ath12k_core_put_hw_group(ab); goto qmi_fail; } - set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); + set_bit(ATH12K_FLAG_UNREGISTERING, &ab->ag->dev_flags); cancel_work_sync(&ab->reset_work); ath12k_core_deinit(ab); @@ -1322,7 +1100,7 @@ qmi_fail: ath12k_mhi_unregister(ab_pci); - ath12k_pci_free_irq(ab); + ath12k_pcic_free_irq(ab); ath12k_pci_msi_free(ab_pci); ath12k_pci_free_region(ab_pci); @@ -1335,7 +1113,16 @@ { struct ath12k_base *ab = pci_get_drvdata(pdev); - ath12k_pci_power_down(ab); + if (!ath12k_en_shutdown) + return + + set_bit(ATH12K_FLAG_UNREGISTERING, &ab->ag->dev_flags); + if (test_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags)) { + ath12k_warn(ab, "SSR recovery in progress, interrupting ssr recovery due to shutdown request\n"); + return; + } + cancel_work_sync(&ab->reset_work); + ath12k_core_deinit(ab); } static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev) @@ -1375,7 +1162,7 @@ .driver.pm = &ath12k_pci_pm_ops, }; -static int ath12k_pci_init(void) +int ath12k_pci_init(void) { int ret; @@ -1383,19 +1170,12 @@ if (ret) { pr_err("failed to register ath12k pci driver: %d\n", ret); - return ret; } - return 0; + return ret; } -module_init(ath12k_pci_init); -static void ath12k_pci_exit(void) +void ath12k_pci_exit(void) { pci_unregister_driver(&ath12k_pci_driver); } - -module_exit(ath12k_pci_exit); - -MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11be WLAN PCIe devices"); -MODULE_LICENSE("Dual BSD/GPL"); diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/pci.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/pci.h --- linux-6.4/drivers/net/wireless/ath/ath12k/pci.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/pci.h 2024-01-19 17:01:19.869847139 +0100 @@ -53,6 +53,9 @@ #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 +#define QCN9224_QFPROM_RAW_RFA_PDET_ROW13_LSB 0x1E20338 +#define OTP_BOARD_ID_MASK GENMASK(15,0) + #define PCI_BAR_WINDOW0_BASE 0x1E00000 #define PCI_BAR_WINDOW0_END 0x1E7FFFC #define PCI_SOC_RANGE_MASK 0x3FFF @@ -68,6 +71,12 @@ #define ATH12K_PCI_SOC_HW_VERSION_1 1 #define ATH12K_PCI_SOC_HW_VERSION_2 2 +enum ppeds_irq_type { + PPEDS_IRQ_PPE2TCL, + PPEDS_IRQ_REO2PPE, + PPEDS_IRQ_PPE_WBM2SW_REL, +}; + struct ath12k_msi_user { const char *name; int num_vectors; @@ -108,6 +117,7 @@ /* enum ath12k_pci_flags */ unsigned long flags; u16 link_ctl; + u32 instance; const struct ath12k_pci_ops *pci_ops; }; @@ -116,10 +126,12 @@ return (struct ath12k_pci *)ab->drv_priv; } +bool ath12k_pci_has_board_id_override(struct ath12k_base *ab, + u16 *ov_board_id); int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, int *num_vectors, u32 *user_base_data, u32 *base_vector); -int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector); +int ath12k_pci_get_msi_irq(struct ath12k_base *ab, unsigned int vector); void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value); u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset); int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, @@ -138,4 +150,11 @@ int ath12k_pci_start(struct ath12k_base *ab); int ath12k_pci_power_up(struct ath12k_base *ab); void ath12k_pci_power_down(struct ath12k_base *ab); +void ath12k_pci_ppeds_free_interrupts(struct ath12k_base *ab); +int ath12k_pci_ppeds_register_interrupts(struct ath12k_base *ab, int type, + int vector, int ring_num); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +void ath12k_pci_ppeds_irq_enable(struct ath12k_base *ab, enum ppeds_irq_type type); +void ath12k_pci_ppeds_irq_disable(struct ath12k_base *ab, enum ppeds_irq_type type); +#endif #endif /* ATH12K_PCI_H */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/peer.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/peer.c --- linux-6.4/drivers/net/wireless/ath/ath12k/peer.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/peer.c 2024-03-18 14:40:14.859741552 +0100 @@ -8,6 +8,23 @@ #include "peer.h" #include "debug.h" +static struct ath12k_ml_peer *ath12k_ml_peer_find(struct ath12k_hw *ah, + const u8 *addr) +{ + struct ath12k_ml_peer *ml_peer; + + lockdep_assert_held(&ah->data_lock); + + list_for_each_entry(ml_peer, &ah->ml_peers, list) { + if (!ether_addr_equal(ml_peer->addr, addr)) + continue; + + return ml_peer; + } + + return NULL; +} + struct ath12k_peer *ath12k_peer_find(struct ath12k_base *ab, int vdev_id, const u8 *addr) { @@ -49,33 +66,71 @@ struct ath12k_peer *ath12k_peer_find_by_addr(struct ath12k_base *ab, const u8 *addr) { - struct ath12k_peer *peer; lockdep_assert_held(&ab->base_lock); - list_for_each_entry(peer, &ab->peers, list) { - if (!ether_addr_equal(peer->addr, addr)) - continue; + if (!ab->rhead_peer_addr) + return NULL; + + return rhashtable_lookup_fast(ab->rhead_peer_addr, addr, + ab->rhash_peer_addr_param); - return peer; } +static struct ath12k_peer *ath12k_peer_find_by_ml_id(struct ath12k_base *ab, + int ml_peer_id) +{ + struct ath12k_peer *peer; + + lockdep_assert_held(&ab->base_lock); + + list_for_each_entry(peer, &ab->peers, list) + if (ml_peer_id == peer->ml_peer_id) + return peer; + return NULL; } -struct ath12k_peer *ath12k_peer_find_by_id(struct ath12k_base *ab, +struct ath12k_peer *ath12k_peer_find_list_by_id(struct ath12k_base *ab, int peer_id) { struct ath12k_peer *peer; lockdep_assert_held(&ab->base_lock); - list_for_each_entry(peer, &ab->peers, list) - if (peer_id == peer->peer_id) + if (peer_id == ATH12K_PEER_ID_INVALID) + return NULL; + + if (peer_id & ATH12K_ML_PEER_ID_VALID) { + return ath12k_peer_find_by_ml_id(ab, peer_id); + } else { + list_for_each_entry(peer, &ab->peers, list) { + if (peer->peer_id == peer_id) return peer; + } return NULL; } +} + +struct ath12k_peer *ath12k_peer_find_by_id(struct ath12k_base *ab, + int peer_id) +{ + lockdep_assert_held(&ab->base_lock); + + if (peer_id == ATH12K_PEER_ID_INVALID) + return NULL; + + if (peer_id & ATH12K_ML_PEER_ID_VALID) { + return ath12k_peer_find_by_ml_id(ab, peer_id); + } else { + if (!ab->rhead_peer_id) + return NULL; + + return rhashtable_lookup_fast(ab->rhead_peer_id, &peer_id, + ab->rhash_peer_id_param); + } +} bool ath12k_peer_exist_by_vdev_id(struct ath12k_base *ab, int vdev_id) { @@ -92,18 +147,20 @@ spin_unlock_bh(&ab->base_lock); return false; } - -struct ath12k_peer *ath12k_peer_find_by_ast(struct ath12k_base *ab, - int ast_hash) +struct ath12k_peer *ath12k_peer_find_by_vdev_id(struct ath12k_base *ab, + int vdev_id) { struct ath12k_peer *peer; - lockdep_assert_held(&ab->base_lock); + spin_lock_bh(&ab->base_lock); - list_for_each_entry(peer, &ab->peers, list) - if (ast_hash == peer->ast_hash) + list_for_each_entry(peer, &ab->peers, list) { + if (vdev_id == peer->vdev_id) { + spin_unlock_bh(&ab->base_lock); return peer; - + } + } + spin_unlock_bh(&ab->base_lock); return NULL; } @@ -113,17 +170,21 @@ spin_lock_bh(&ab->base_lock); - peer = ath12k_peer_find_by_id(ab, peer_id); + peer = ath12k_peer_find_list_by_id(ab, peer_id); if (!peer) { ath12k_warn(ab, "peer-unmap-event: unknown peer id %d\n", peer_id); goto exit; } - ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "htt peer unmap vdev %d peer %pM id %d\n", + ath12k_dbg(ab, ATH12K_DBG_PEER, "htt peer unmap vdev %d peer %pM id %d\n", peer->vdev_id, peer->addr, peer_id); list_del(&peer->list); +#ifdef CONFIG_ATH12K_SAWF + if (peer->sawf_ctx_peer.telemetry_peer_ctx) + ath12k_telemetry_peer_ctx_free(peer->sawf_ctx_peer.telemetry_peer_ctx); +#endif kfree(peer); wake_up(&ab->peer_mapping_wq); @@ -148,17 +209,75 @@ peer->ast_hash = ast_hash; peer->hw_peer_id = hw_peer_id; ether_addr_copy(peer->addr, mac_addr); +#ifdef CONFIG_ATH12K_SAWF + if (ath12k_sawf_enable) + ath12k_sdwf_fill_hbucket_type(peer); +#endif list_add(&peer->list, &ab->peers); wake_up(&ab->peer_mapping_wq); } - ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "htt peer map vdev %d peer %pM id %d\n", + ath12k_dbg(ab, ATH12K_DBG_PEER, "htt peer map vdev %d peer %pM id %d\n", vdev_id, mac_addr, peer_id); exit: spin_unlock_bh(&ab->base_lock); } +void ath12k_peer_mlo_map_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + struct ath11k_htt_mlo_peer_map_msg *msg; + u16 ml_peer_id; + struct ath12k_peer *peer; + u16 mld_mac_h16; + u8 mld_addr[ETH_ALEN]; + + msg = (struct ath11k_htt_mlo_peer_map_msg *)skb->data; + + ml_peer_id = FIELD_GET(ATH12K_HTT_MLO_PEER_MAP_INFO0_PEER_ID, msg->info0); + + ml_peer_id |= ATH12K_ML_PEER_ID_VALID; + + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_list_by_id(ab, ml_peer_id); + + /* TODO a sync wait to check ml peer map success or delete + * ml peer info in all link peers and make peer assoc failure + * TBA after testing basic changes + */ + if (!peer) { + ath12k_warn(ab, "peer corresponding to ml peer id %d not found", ml_peer_id); + spin_unlock_bh(&ab->base_lock); + return; + } + mld_mac_h16 = FIELD_GET(ATH12K_HTT_MLO_PEER_MAP_MAC_ADDR_H16, + msg->mac_addr.mac_addr_h16); + ath12k_dp_get_mac_addr(msg->mac_addr.mac_addr_l32, mld_mac_h16, mld_addr); + + WARN_ON(memcmp(mld_addr, peer->ml_addr, ETH_ALEN)); + + spin_unlock_bh(&ab->base_lock); + + ath12k_dbg(ab, ATH12K_DBG_PEER, "htt MLO peer map peer %pM id %d\n", + mld_addr, ml_peer_id); + + /* TODO rx queue setup for the ML peer */ +} + +void ath12k_peer_mlo_unmap_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + struct ath11k_htt_mlo_peer_unmap_msg *msg; + u16 ml_peer_id; + + msg = (struct ath11k_htt_mlo_peer_unmap_msg *)skb->data; + + ml_peer_id = FIELD_GET(ATH12K_HTT_MLO_PEER_UNMAP_PEER_ID, msg->info0); + + ml_peer_id |= ATH12K_ML_PEER_ID_VALID; + + ath12k_dbg(ab, ATH12K_DBG_PEER, "htt MLO peer unmap peer ml id %d\n", ml_peer_id); +} + static int ath12k_wait_for_peer_common(struct ath12k_base *ab, int vdev_id, const u8 *addr, bool expect_mapped) { @@ -181,6 +300,80 @@ return 0; } +static inline int ath12k_peer_rhash_insert(struct ath12k_base *ab, + struct rhashtable *rtbl, + struct rhash_head *rhead, + struct rhashtable_params *params, + void *key) +{ + struct ath12k_peer *tmp; + + lockdep_assert_held(&ab->tbl_mtx_lock); + + tmp = rhashtable_lookup_get_insert_fast(rtbl, rhead, *params); + + if (!tmp) + return 0; + else if (IS_ERR(tmp)) + return PTR_ERR(tmp); + else + return -EEXIST; +} +static inline int ath12k_peer_rhash_remove(struct ath12k_base *ab, + struct rhashtable *rtbl, + struct rhash_head *rhead, + struct rhashtable_params *params) +{ + int ret; + + lockdep_assert_held(&ab->tbl_mtx_lock); + + ret = rhashtable_remove_fast(rtbl, rhead, *params); + if (ret && ret != -ENOENT) + return ret; + + return 0; +} + +static int ath12k_peer_rhash_add(struct ath12k_base *ab, struct ath12k_peer *peer) +{ + int ret; + + lockdep_assert_held(&ab->base_lock); + lockdep_assert_held(&ab->tbl_mtx_lock); + + if (!ab->rhead_peer_id || !ab->rhead_peer_addr) + return -EPERM; + + if (peer->rhash_done) + return 0; + + ret = ath12k_peer_rhash_insert(ab, ab->rhead_peer_id, &peer->rhash_id, + &ab->rhash_peer_id_param, &peer->peer_id); + if (ret) { + ath12k_warn(ab, "failed to add peer %pM with id %d in rhash_id ret %d\n", + peer->addr, peer->peer_id, ret); + return ret; + } + + ret = ath12k_peer_rhash_insert(ab, ab->rhead_peer_addr, &peer->rhash_addr, + &ab->rhash_peer_addr_param, &peer->addr); + if (ret) { + ath12k_warn(ab, "failed to add peer %pM with id %d in rhash_addr ret %d\n", + peer->addr, peer->peer_id, ret); + goto err_clean; + } + + peer->rhash_done = true; + return 0; + +err_clean: + ath12k_peer_rhash_remove(ab, ab->rhead_peer_id, &peer->rhash_id, + &ab->rhash_peer_id_param); + return ret; +} + + void ath12k_peer_cleanup(struct ath12k *ar, u32 vdev_id) { struct ath12k_peer *peer, *tmp; @@ -188,6 +381,7 @@ lockdep_assert_held(&ar->conf_mutex); + mutex_lock(&ab->tbl_mtx_lock); spin_lock_bh(&ab->base_lock); list_for_each_entry_safe(peer, tmp, &ab->peers, list) { if (peer->vdev_id != vdev_id) @@ -195,13 +389,18 @@ ath12k_warn(ab, "removing stale peer %pM from vdev_id %d\n", peer->addr, vdev_id); - + ath12k_peer_rhash_delete(ab, peer); list_del(&peer->list); +#ifdef CONFIG_ATH12K_SAWF + if (peer->sawf_ctx_peer.telemetry_peer_ctx) + ath12k_telemetry_peer_ctx_free(peer->sawf_ctx_peer.telemetry_peer_ctx); +#endif kfree(peer); ar->num_peers--; } spin_unlock_bh(&ab->base_lock); + mutex_unlock(&ab->tbl_mtx_lock); } static int ath12k_wait_for_peer_deleted(struct ath12k *ar, int vdev_id, const u8 *addr) @@ -217,72 +416,251 @@ ret = ath12k_wait_for_peer_deleted(ar, vdev_id, addr); if (ret) { - ath12k_warn(ar->ab, "failed wait for peer deleted"); + ath12k_warn(ar->ab, "failed wait for peer deleted peer_addr : %pM\n", addr); return ret; } time_left = wait_for_completion_timeout(&ar->peer_delete_done, 3 * HZ); if (time_left == 0) { - ath12k_warn(ar->ab, "Timeout in receiving peer delete response\n"); + ath12k_warn(ar->ab, "Timeout in receiving peer delete response peer_addr : %pM\n", + addr); return -ETIMEDOUT; } return 0; } -int ath12k_peer_delete(struct ath12k *ar, u32 vdev_id, u8 *addr) +int ath12k_peer_delete_send(struct ath12k *ar, u32 vdev_id, const u8 *addr) { + struct ath12k_peer *peer; + struct ath12k_base *ab = ar->ab; int ret; lockdep_assert_held(&ar->conf_mutex); + mutex_lock(&ab->tbl_mtx_lock); + spin_lock_bh(&ab->base_lock); + + peer = ath12k_peer_find_by_addr(ab, addr); + if (peer && peer->vdev_id == vdev_id) + ath12k_peer_rhash_delete(ab, peer); + + if (!peer) + peer = ath12k_peer_find(ab, vdev_id, addr); + + if (!peer) { + spin_unlock_bh(&ab->base_lock); + mutex_unlock(&ab->tbl_mtx_lock); + + ath12k_warn(ab, + "failed to find peer vdev_id %d addr %pM in delete\n", + vdev_id, addr); + return -EINVAL; + } + + spin_unlock_bh(&ab->base_lock); + mutex_unlock(&ab->tbl_mtx_lock); + + reinit_completion(&ar->peer_delete_done); ret = ath12k_wmi_send_peer_delete_cmd(ar, addr, vdev_id); if (ret) { - ath12k_warn(ar->ab, + ath12k_warn(ab, "failed to delete peer vdev_id %d addr %pM ret %d\n", vdev_id, addr, ret); return ret; } + return 0; +} + +static int __ath12k_peer_delete(struct ath12k *ar, u32 vdev_id, const u8 *addr) +{ + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + ret = ath12k_peer_delete_send(ar, vdev_id, addr); + if (ret) + return ret; + ret = ath12k_wait_for_peer_delete_done(ar, vdev_id, addr); if (ret) return ret; + return 0; +} + +int ath12k_peer_delete(struct ath12k *ar, u32 vdev_id, const u8 *addr) +{ + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + ret = __ath12k_peer_delete(ar, vdev_id, addr); + if (ret) + return ret; + ar->num_peers--; return 0; } +int ath12k_ml_link_peers_delete(struct ath12k_vif *ahvif, struct ath12k_sta *ahsta) +{ + struct ath12k_link_vif *arvif; + struct ath12k_link_sta *arsta; + struct ieee80211_sta *sta; + struct ath12k *ar; + int ret, err_ret = 0; + u8 link_id = 0; + struct ath12k_hw *ah = ahvif->ah; + unsigned long links; + + lockdep_assert_held(&ah->conf_mutex); + + sta = container_of((void *)ahsta, struct ieee80211_sta, drv_priv); + + if (!sta->mlo) + return -EINVAL; + + /* FW expects delete of all link peers at once before waiting for reception + * of peer unmap or delete responses + */ + links = sta->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + + if (!arvif || !arsta) + continue; + + ar = arvif->ar; + + if (!ar) + continue; + cancel_work_sync(&arsta->update_wk); + + if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags) || + test_bit(ATH12K_FLAG_RECOVERY, &ar->ab->dev_flags) || + test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &ar->ab->dev_flags)) + continue; + + cancel_work_sync(&arsta->update_wk); + mutex_lock(&ar->conf_mutex); + ath12k_dp_peer_cleanup(ar, arvif->vdev_id, arsta->addr); + + ret = ath12k_peer_delete_send(ar, arvif->vdev_id, arsta->addr); + if (ret) { + mutex_unlock(&ar->conf_mutex); + ath12k_warn(ar->ab, + "failed to delete peer vdev_id %d addr %pM ret %d\n", + arvif->vdev_id, arsta->addr, ret); + err_ret = ret; + continue; + } + mutex_unlock(&ar->conf_mutex); + } + + /* Ensure all link peers are deleted and unmapped */ + links = sta->valid_links; + for_each_set_bit(link_id, &links, IEEE80211_MLD_MAX_NUM_LINKS) { + arvif = ahvif->link[link_id]; + arsta = ahsta->link[link_id]; + + if (!arvif || !arsta) + continue; + + ar = arvif->ar; + + if (!ar) + continue; + + if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags) || + test_bit(ATH12K_FLAG_RECOVERY, &ar->ab->dev_flags) || + test_bit(ATH12K_FLAG_UMAC_RECOVERY_START, &ar->ab->dev_flags)) + continue; + mutex_lock(&ar->conf_mutex); + ret = ath12k_wait_for_peer_delete_done(ar, arvif->vdev_id, arsta->addr); + if (ret) { + err_ret = ret; + mutex_unlock(&ar->conf_mutex); + continue; + } + ar->num_peers--; + mutex_unlock(&ar->conf_mutex); + } + + return err_ret; +} + static int ath12k_wait_for_peer_created(struct ath12k *ar, int vdev_id, const u8 *addr) { return ath12k_wait_for_peer_common(ar->ab, vdev_id, addr, true); } -int ath12k_peer_create(struct ath12k *ar, struct ath12k_vif *arvif, +int ath12k_peer_create(struct ath12k *ar, struct ath12k_link_vif *arvif, struct ieee80211_sta *sta, struct ath12k_wmi_peer_create_arg *arg) { struct ath12k_peer *peer; - int ret; + struct ath12k_sta *ahsta; + struct ath12k_link_sta *arsta; + u8 link_id = arvif->link_id; + struct ieee80211_vif *vif = arvif->ahvif->vif; + struct ath12k_ml_peer *ml_peer; + int ret, fbret; lockdep_assert_held(&ar->conf_mutex); - if (ar->num_peers > (ar->max_num_peers - 1)) { + if (ar->num_peers >= (ar->max_num_peers - 1)) { ath12k_warn(ar->ab, "failed to create peer due to insufficient peer entry resource in firmware\n"); return -ENOBUFS; } + /* Check if a ML peer with same address as this link peer already + * exists + */ + if (sta) { + ahsta = ath12k_sta_to_ahsta(sta); + spin_lock_bh(&ar->ah->data_lock); + ml_peer = ath12k_ml_peer_find(ar->ah, arg->peer_addr); + if (ml_peer && (!sta->mlo || ml_peer->id != ahsta->ml_peer_id)) { + spin_unlock_bh(&ar->ah->data_lock); + ath12k_warn(ar->ab, + "failed to create link peer %pM due to conflicting address with already associated ML peer %pM with ml peer id %d\n", + arg->peer_addr, ml_peer->addr, + ml_peer->id); + return -EINVAL; + } + spin_unlock_bh(&ar->ah->data_lock); + } + + mutex_lock(&ar->ab->tbl_mtx_lock); spin_lock_bh(&ar->ab->base_lock); peer = ath12k_peer_find_by_pdev_idx(ar->ab, ar->pdev_idx, arg->peer_addr); if (peer) { + ath12k_warn(ar->ab, "Peer %pM already found in pdev_idx %d vdev %d\n", + arg->peer_addr, ar->pdev_idx, peer->vdev_id); spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ar->ab->tbl_mtx_lock); return -EINVAL; } + + /* In case of Split PHY and roaming scenario, pdev idx + * might differ but both the pdev will share same rhash + * table. In that case update the rhash table if peer is + * already present + */ + peer = ath12k_peer_find_by_addr(ar->ab, arg->peer_addr); + if (peer) + ath12k_peer_rhash_delete(ar->ab, peer); + spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ar->ab->tbl_mtx_lock); ret = ath12k_wmi_send_peer_create_cmd(ar, arg); if (ret) { @@ -297,46 +675,385 @@ if (ret) return ret; + mutex_lock(&ar->ab->tbl_mtx_lock); spin_lock_bh(&ar->ab->base_lock); peer = ath12k_peer_find(ar->ab, arg->vdev_id, arg->peer_addr); if (!peer) { spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ar->ab->tbl_mtx_lock); ath12k_warn(ar->ab, "failed to find peer %pM on vdev %i after creation\n", arg->peer_addr, arg->vdev_id); - reinit_completion(&ar->peer_delete_done); - - ret = ath12k_wmi_send_peer_delete_cmd(ar, arg->peer_addr, - arg->vdev_id); - if (ret) { - ath12k_warn(ar->ab, "failed to delete peer vdev_id %d addr %pM\n", - arg->vdev_id, arg->peer_addr); - return ret; + goto cleanup; } - - ret = ath12k_wait_for_peer_delete_done(ar, arg->vdev_id, - arg->peer_addr); - if (ret) - return ret; - - return -ENOENT; + ret = ath12k_peer_rhash_add(ar->ab, peer); + if (ret) { + spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ar->ab->tbl_mtx_lock); + goto cleanup; } peer->pdev_idx = ar->pdev_idx; peer->sta = sta; - if (arvif->vif->type == NL80211_IFTYPE_STATION) { + if (vif->type == NL80211_IFTYPE_STATION) { arvif->ast_hash = peer->ast_hash; arvif->ast_idx = peer->hw_peer_id; + arvif->desc.info4 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX, arvif->ast_idx) | + FIELD_PREP(HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM, arvif->ast_hash); } peer->sec_type = HAL_ENCRYPT_TYPE_OPEN; peer->sec_type_grp = HAL_ENCRYPT_TYPE_OPEN; + peer->vif = vif; +#ifdef CONFIG_MAC80211_PPE_SUPPORT + peer->ppe_vp_num = peer->vif->ppe_vp_num; +#endif +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT + peer->ppe_vp_num = arvif->ppe_vp_num; +#endif + + if (sta) { + ahsta = ath12k_sta_to_ahsta(sta); + arsta = ahsta->link[link_id]; + arsta->tcl_metadata |= HTT_TCL_META_DATA_GET(0, + HTT_TCL_META_DATA_TYPE) | + HTT_TCL_META_DATA_GET(peer->peer_id, + HTT_TCL_META_DATA_PEER_ID); + peer->link_id = arsta->link_id; + + /* set HTT extension valid bit to 0 by default */ + arsta->tcl_metadata &= ~HTT_TCL_META_DATA_VALID_HTT; + + /* Fill ML info into created peer */ + if (sta->mlo) { + peer->ml_peer_id = ahsta->ml_peer_id | ATH12K_ML_PEER_ID_VALID; + ether_addr_copy(peer->ml_addr, sta->addr); + peer->mlo = true; + } else { + peer->ml_peer_id = ATH12K_MLO_PEER_ID_INVALID; + peer->mlo = false; + } + } ar->num_peers++; + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, "peer created %pM\n", arg->peer_addr); + spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ar->ab->tbl_mtx_lock); + + return 0; + +cleanup: + fbret = __ath12k_peer_delete(ar, arg->vdev_id, arg->peer_addr); + if (fbret) + ath12k_warn(ar->ab, "failed peer %pM delete vdev_id %d fallback ret %d\n", + arg->peer_addr, arg->vdev_id, fbret); + + return ret; + +} + +static u16 ath12k_mac_alloc_ml_peer_id(struct ath12k_hw *ah) +{ + + u16 ml_peer_id; + + lockdep_assert_held(&ah->conf_mutex); + + for (ml_peer_id = 0; ml_peer_id < ATH12K_MAX_MLO_PEERS; ml_peer_id++) { + if (test_bit(ml_peer_id, ah->free_ml_peer_id_map)) + continue; + + set_bit(ml_peer_id, ah->free_ml_peer_id_map); + break; + } + + if (ml_peer_id == ATH12K_MAX_MLO_PEERS) + ml_peer_id = ATH12K_MLO_PEER_ID_INVALID; + + ath12k_dbg(NULL, ATH12K_DBG_PEER, "Allocated ml_peer_id:%d", ml_peer_id); + + return ml_peer_id; +} + +int ath12k_ml_peer_create(struct ath12k_hw *ah, struct ieee80211_sta *sta) +{ + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_ml_peer *ml_peer; + + lockdep_assert_held(&ah->conf_mutex); + + if (!sta->mlo) + return -EINVAL; + + spin_lock_bh(&ah->data_lock); + ml_peer = ath12k_ml_peer_find(ah, sta->addr); + if (ml_peer) { + spin_unlock_bh(&ah->data_lock); + ath12k_err(NULL, "ML peer(id=%d) exists already, unable to add new entry for %pM", + ml_peer->id, sta->addr); + return -EEXIST; + } + + ml_peer = kzalloc(sizeof(*ml_peer), GFP_ATOMIC); + if (!ml_peer) { + spin_unlock_bh(&ah->data_lock); + ath12k_err(NULL, "unable to allocate new ML peer for %pM", + sta->addr); + return -ENOMEM; + } + + ahsta->ml_peer_id = ath12k_mac_alloc_ml_peer_id(ah); + + if (ahsta->ml_peer_id == ATH12K_MLO_PEER_ID_INVALID) { + kfree(ml_peer); + spin_unlock_bh(&ah->data_lock); + ath12k_err(NULL, "unable to allocate ml peer id for sta %pM", sta->addr); + return -ENOMEM; + } + + ether_addr_copy(ml_peer->addr, sta->addr); + ml_peer->id = ahsta->ml_peer_id; + list_add(&ml_peer->list, &ah->ml_peers); + spin_unlock_bh(&ah->data_lock); + + ath12k_dbg(NULL, ATH12K_DBG_PEER, "ML peer created for %pM id %d\n", + sta->addr, ahsta->ml_peer_id); + return 0; +} + +int ath12k_ml_peer_delete(struct ath12k_hw *ah, struct ieee80211_sta *sta) +{ + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_ml_peer *ml_peer; + + lockdep_assert_held(&ah->conf_mutex); + if (!sta->mlo) + return -EINVAL; + + clear_bit(ahsta->ml_peer_id, ah->free_ml_peer_id_map); + ahsta->ml_peer_id = ATH12K_MLO_PEER_ID_INVALID; + + spin_lock_bh(&ah->data_lock); + ml_peer = ath12k_ml_peer_find(ah, sta->addr); + if (!ml_peer) { + spin_unlock_bh(&ah->data_lock); + ath12k_err(NULL, "ML peer for %pM not found", sta->addr); + return -EINVAL; + } + + list_del(&ml_peer->list); + kfree(ml_peer); + spin_unlock_bh(&ah->data_lock); + + ath12k_dbg(NULL, ATH12K_DBG_PEER, "ML peer deleted for %pM\n", + sta->addr); + return 0; +} + +int ath12k_peer_rhash_delete(struct ath12k_base *ab, struct ath12k_peer *peer) +{ + int ret; + + lockdep_assert_held(&ab->base_lock); + lockdep_assert_held(&ab->tbl_mtx_lock); + + if (!ab->rhead_peer_id || !ab->rhead_peer_addr) + return -EPERM; + if (!peer->rhash_done) return 0; + + ret = ath12k_peer_rhash_remove(ab, ab->rhead_peer_addr, &peer->rhash_addr, + &ab->rhash_peer_addr_param); + if (ret) { + ath12k_warn(ab, "failed to remove peer %pM id %d in rhash_addr ret %d\n", + peer->addr, peer->peer_id, ret); + return ret; + } + + ret = ath12k_peer_rhash_remove(ab, ab->rhead_peer_id, &peer->rhash_id, + &ab->rhash_peer_id_param); + if (ret) { + ath12k_warn(ab, "failed to remove peer %pM id %d in rhash_id ret %d\n", + peer->addr, peer->peer_id, ret); + return ret; + } + + peer->rhash_done = false; + + return 0; +} + +static int ath12k_peer_rhash_id_tbl_init(struct ath12k_base *ab) +{ + struct rhashtable_params *param; + struct rhashtable *rhash_id_tbl; + int ret; + size_t size; + + lockdep_assert_held(&ab->tbl_mtx_lock); + + if (ab->rhead_peer_id) + return 0; + + size = sizeof(*ab->rhead_peer_id); + rhash_id_tbl = kzalloc(size, GFP_KERNEL); + if (!rhash_id_tbl) { + ath12k_warn(ab, "failed to init rhash id table due to no mem (size %zu)\n", + size); + return -ENOMEM; + } + + param = &ab->rhash_peer_id_param; + + param->key_offset = offsetof(struct ath12k_peer, peer_id); + param->head_offset = offsetof(struct ath12k_peer, rhash_id); + param->key_len = sizeof_field(struct ath12k_peer, peer_id); + param->automatic_shrinking = true; + param->nelem_hint = ab->num_radios * TARGET_NUM_PEERS_PDEV; + + ret = rhashtable_init(rhash_id_tbl, param); + if (ret) { + ath12k_warn(ab, "failed to init peer id rhash table %d\n", ret); + goto err_free; + } + + spin_lock_bh(&ab->base_lock); + + if (!ab->rhead_peer_id) { + ab->rhead_peer_id = rhash_id_tbl; + } else { + spin_unlock_bh(&ab->base_lock); + goto cleanup_tbl; + } + + spin_unlock_bh(&ab->base_lock); + + return 0; + +cleanup_tbl: + rhashtable_destroy(rhash_id_tbl); +err_free: + kfree(rhash_id_tbl); + + return ret; +} + +static int ath12k_peer_rhash_addr_tbl_init(struct ath12k_base *ab) +{ + struct rhashtable_params *param; + struct rhashtable *rhash_addr_tbl; + int ret; + size_t size; + + lockdep_assert_held(&ab->tbl_mtx_lock); + + if (ab->rhead_peer_addr) + return 0; + + size = sizeof(*ab->rhead_peer_addr); + rhash_addr_tbl = kzalloc(size, GFP_KERNEL); + if (!rhash_addr_tbl) { + ath12k_warn(ab, "failed to init rhash addr table due to no mem (size %zu)\n", + size); + return -ENOMEM; + } + + param = &ab->rhash_peer_addr_param; + + param->key_offset = offsetof(struct ath12k_peer, addr); + param->head_offset = offsetof(struct ath12k_peer, rhash_addr); + param->key_len = sizeof_field(struct ath12k_peer, addr); + param->automatic_shrinking = true; + param->nelem_hint = ab->num_radios * TARGET_NUM_PEERS_PDEV; + + ret = rhashtable_init(rhash_addr_tbl, param); + if (ret) { + ath12k_warn(ab, "failed to init peer addr rhash table %d\n", ret); + goto err_free; } + + spin_lock_bh(&ab->base_lock); + + if (!ab->rhead_peer_addr) { + ab->rhead_peer_addr = rhash_addr_tbl; + } else { + spin_unlock_bh(&ab->base_lock); + goto cleanup_tbl; + } + + spin_unlock_bh(&ab->base_lock); + + return 0; + +cleanup_tbl: + rhashtable_destroy(rhash_addr_tbl); +err_free: + kfree(rhash_addr_tbl); + + return ret; +} + +static inline void ath12k_peer_rhash_id_tbl_destroy(struct ath12k_base *ab) +{ + lockdep_assert_held(&ab->tbl_mtx_lock); + + if (!ab->rhead_peer_id) + return; + + rhashtable_destroy(ab->rhead_peer_id); + kfree(ab->rhead_peer_id); + ab->rhead_peer_id = NULL; +} + +static inline void ath12k_peer_rhash_addr_tbl_destroy(struct ath12k_base *ab) +{ + lockdep_assert_held(&ab->tbl_mtx_lock); + + if (!ab->rhead_peer_addr) + return; + + rhashtable_destroy(ab->rhead_peer_addr); + kfree(ab->rhead_peer_addr); + ab->rhead_peer_addr = NULL; +} + +int ath12k_peer_rhash_tbl_init(struct ath12k_base *ab) +{ + int ret; + + mutex_lock(&ab->tbl_mtx_lock); + + ret = ath12k_peer_rhash_id_tbl_init(ab); + if (ret) + goto out; + + ret = ath12k_peer_rhash_addr_tbl_init(ab); + if (ret) + goto cleanup_tbl; + + mutex_unlock(&ab->tbl_mtx_lock); + + return 0; + +cleanup_tbl: + ath12k_peer_rhash_id_tbl_destroy(ab); +out: + mutex_unlock(&ab->tbl_mtx_lock); + return ret; +} + +void ath12k_peer_rhash_tbl_destroy(struct ath12k_base *ab) +{ + mutex_lock(&ab->tbl_mtx_lock); + + ath12k_peer_rhash_addr_tbl_destroy(ab); + ath12k_peer_rhash_id_tbl_destroy(ab); + + mutex_unlock(&ab->tbl_mtx_lock); +} + diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/peer.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/peer.h --- linux-6.4/drivers/net/wireless/ath/ath12k/peer.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/peer.h 2024-03-18 14:40:14.859741552 +0100 @@ -8,6 +8,7 @@ #define ATH12K_PEER_H #include "dp_rx.h" +#include "sawf.h" struct ppdu_user_delayba { u16 sw_peer_id; @@ -22,6 +23,11 @@ struct ath12k_peer { struct list_head list; struct ieee80211_sta *sta; + struct ieee80211_vif *vif; +#ifdef CONFIG_ATH12K_SAWF + struct ath12k_sawf_peer_ctx sawf_ctx_peer; + struct ath12k_sawf_stats sawf_stats; +#endif /* CONFIG_ATH12K_SAWF */ int vdev_id; u8 addr[ETH_ALEN]; int peer_id; @@ -31,8 +37,19 @@ /* protected by ab->data_lock */ struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; + + /* rx tid queue is setup once for primary link peer + * in case of ML and cloned into partner peer data + * but would be accessed (only if required)and safely + * by ensuring primary parner is still valid + */ struct ath12k_dp_rx_tid rx_tid[IEEE80211_NUM_TIDS + 1]; + /* peer id based rhashtable list pointer */ + struct rhash_head rhash_id; + /* peer addr based rhashtable list pointer */ + struct rhash_head rhash_addr; + /* Info used in MMIC verification of * RX fragments */ @@ -44,6 +61,38 @@ struct ppdu_user_delayba ppdu_stats_delayba; bool delayba_flag; bool is_authorized; + + /* The below flag indicates whether + * a peer has setup its datapath or not + */ + bool dp_setup_done; + + bool mlo; + u16 ml_peer_id; + /* TODO remove or fill below these info if required/not required during dp change */ + /* for reference to ath12k_link_sta */ + u8 link_id; + + /* To ensure only certain work related to dp is done once */ + bool primary_link; + + /* To check if the peer entry is part of rhash table or not */ + bool rhash_done; + + /* any other ML info common for all partners can be added + * here and would be same for all partner peers + */ + u8 ml_addr[ETH_ALEN]; +#if defined(CONFIG_MAC80211_PPE_SUPPORT) || defined(CONFIG_ATH12K_BONDED_DS_SUPPORT) + /* Duplicate PPE port number to avoid link vif lookup in rx data path */ + int ppe_vp_num; +#endif +}; + +struct ath12k_ml_peer { + struct list_head list; + u8 addr[ETH_ALEN]; + u16 id; }; void ath12k_peer_unmap_event(struct ath12k_base *ab, u16 peer_id); @@ -51,17 +100,50 @@ u8 *mac_addr, u16 ast_hash, u16 hw_peer_id); struct ath12k_peer *ath12k_peer_find(struct ath12k_base *ab, int vdev_id, const u8 *addr); +struct ath12k_peer *ath12k_peer_find_list_by_id(struct ath12k_base *ab, + int peer_id); struct ath12k_peer *ath12k_peer_find_by_addr(struct ath12k_base *ab, const u8 *addr); struct ath12k_peer *ath12k_peer_find_by_id(struct ath12k_base *ab, int peer_id); void ath12k_peer_cleanup(struct ath12k *ar, u32 vdev_id); -int ath12k_peer_delete(struct ath12k *ar, u32 vdev_id, u8 *addr); -int ath12k_peer_create(struct ath12k *ar, struct ath12k_vif *arvif, +int ath12k_peer_delete(struct ath12k *ar, u32 vdev_id, const u8 *addr); +int ath12k_ml_link_peers_delete(struct ath12k_vif *ahvif, struct ath12k_sta *ahsta); +int ath12k_ml_peer_create(struct ath12k_hw *ah, struct ieee80211_sta *sta); +int ath12k_ml_peer_delete(struct ath12k_hw *ah, struct ieee80211_sta *sta); +int ath12k_peer_create(struct ath12k *ar, struct ath12k_link_vif *arvif, struct ieee80211_sta *sta, struct ath12k_wmi_peer_create_arg *arg); int ath12k_wait_for_peer_delete_done(struct ath12k *ar, u32 vdev_id, const u8 *addr); bool ath12k_peer_exist_by_vdev_id(struct ath12k_base *ab, int vdev_id); -struct ath12k_peer *ath12k_peer_find_by_ast(struct ath12k_base *ab, int ast_hash); - +int ath12k_peer_rhash_tbl_init(struct ath12k_base *ab); +void ath12k_peer_rhash_tbl_destroy(struct ath12k_base *ab); +int ath12k_peer_rhash_delete(struct ath12k_base *ab, struct ath12k_peer *peer); +void ath12k_peer_mlo_map_event(struct ath12k_base *ab, struct sk_buff *skb); +void ath12k_peer_mlo_unmap_event(struct ath12k_base *ab, struct sk_buff *skb); +int ath12k_peer_delete_send(struct ath12k *ar, u32 vdev_id, const u8 *addr); +struct ath12k_peer *ath12k_peer_find_by_vdev_id(struct ath12k_base *ab, + int vdev_id); +static inline +struct ath12k_link_sta *ath12k_peer_get_link_sta(struct ath12k_base *ab, + struct ath12k_peer *peer) +{ + struct ath12k_sta *ahsta; + + if (!peer->sta) + return NULL; + + ahsta = ath12k_sta_to_ahsta(peer->sta); + if (peer->ml_peer_id & ATH12K_ML_PEER_ID_VALID) { + if (!(ahsta->links_map & BIT(peer->link_id))) { + ath12k_warn(ab, "peer %pM id %d link_id %d can't found in STA link_map %lu\n", + peer->addr, peer->peer_id, peer->link_id, ahsta->links_map); + return NULL; + } + + return ahsta->link[peer->link_id]; + } else { + return &ahsta->deflink; + } +} #endif /* _PEER_H_ */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/qmi.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/qmi.c --- linux-6.4/drivers/net/wireless/ath/ath12k/qmi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/qmi.c 2024-04-11 13:36:13.766433759 +0200 @@ -8,15 +8,141 @@ #include "qmi.h" #include "core.h" +#include "hif.h" +#include "pci.h" #include "debug.h" +#include "coredump.h" #include +#include +#include +#include #include +#include +#include #define SLEEP_CLOCK_SELECT_INTERNAL_BIT 0x02 #define HOST_CSTATE_BIT 0x04 #define PLATFORM_CAP_PCIE_GLOBAL_RESET 0x08 #define ATH12K_QMI_MAX_CHUNK_SIZE 2097152 +bool ath12k_cold_boot_cal = 0; +module_param_named(cold_boot_cal, ath12k_cold_boot_cal, bool, 0644); +MODULE_PARM_DESC(cold_boot_cal, + "Decrease the channel switch time but increase the driver load time (Default: true)"); + +static struct qmi_elem_info qmi_wlfw_qdss_trace_config_download_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + seg_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + seg_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLANFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + end_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01, + end), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlanfw_qdss_trace_config_download_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_qdss_trace_config_download_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static bool ath12k_skip_caldata; +module_param_named(skip_caldata, ath12k_skip_caldata, bool, 0444); +MODULE_PARM_DESC(ath12k_skip_caldata, "Skip caldata download"); + static struct qmi_elem_info wlfw_host_mlo_chip_info_s_v01_ei[] = { { .data_type = QMI_UNSIGNED_1_BYTE, @@ -61,6 +187,73 @@ }, }; +static struct qmi_elem_info qmi_wlanfw_qdss_trace_mode_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_mode_req_msg_v01, + mode_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum qmi_wlanfw_qdss_trace_mode_enum_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_mode_req_msg_v01, + mode), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_mode_req_msg_v01, + option_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_mode_req_msg_v01, + option), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlanfw_qdss_trace_mode_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_mode_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + static struct qmi_elem_info qmi_wlanfw_host_cap_req_msg_v01_ei[] = { { .data_type = QMI_OPT_FLAG, @@ -387,7 +580,7 @@ mlo_capable_valid), }, { - .data_type = QMI_OPT_FLAG, + .data_type = QMI_UNSIGNED_1_BYTE, .elem_len = 1, .elem_size = sizeof(u8), .array_type = NO_ARRAY, @@ -505,6 +698,24 @@ feature_list), }, { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x2E, + .offset = offsetof(struct qmi_wlanfw_host_cap_req_msg_v01, + fw_cfg_support_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x2E, + .offset = offsetof(struct qmi_wlanfw_host_cap_req_msg_v01, + fw_cfg_support), + }, + { .data_type = QMI_EOTI, .array_type = NO_ARRAY, .tlv_type = QMI_COMMON_TLV_TYPE, @@ -528,6 +739,192 @@ }, }; +struct qmi_elem_info wlanfw_cfg_download_req_msg_v01_ei[] = { + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + file_type_valid), + }, + { + .data_type = QMI_SIGNED_4_BYTE_ENUM, + .elem_len = 1, + .elem_size = sizeof(enum wlanfw_cfg_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + file_type), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + total_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + seg_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x12, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + seg_id), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLANFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x13, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + data), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + end_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x14, + .offset = offsetof(struct wlanfw_cfg_download_req_msg_v01, + end), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlanfw_cfg_download_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlanfw_cfg_download_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlanfw_phy_cap_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlanfw_phy_cap_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_phy_cap_resp_msg_v01, resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_phy_cap_resp_msg_v01, + num_phy_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_phy_cap_resp_msg_v01, + num_phy), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_phy_cap_resp_msg_v01, + board_id_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_phy_cap_resp_msg_v01, + board_id), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + static struct qmi_elem_info qmi_wlanfw_ind_register_req_msg_v01_ei[] = { { .data_type = QMI_OPT_FLAG, @@ -747,6 +1144,60 @@ cal_done_enable), }, { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof(struct qmi_wlanfw_ind_register_req_msg_v01, + qdss_trace_req_mem_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1C, + .offset = offsetof(struct qmi_wlanfw_ind_register_req_msg_v01, + qdss_trace_req_mem_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof(struct qmi_wlanfw_ind_register_req_msg_v01, + qdss_trace_save_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x1D, + .offset = offsetof(struct qmi_wlanfw_ind_register_req_msg_v01, + qdss_trace_save_enable), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x20, + .offset = offsetof(struct qmi_wlanfw_ind_register_req_msg_v01, + m3_dump_upload_req_enable_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x20, + .offset = offsetof(struct qmi_wlanfw_ind_register_req_msg_v01, + m3_dump_upload_req_enable), + }, + { .data_type = QMI_EOTI, .array_type = NO_ARRAY, .tlv_type = QMI_COMMON_TLV_TYPE, @@ -983,6 +1434,68 @@ }, }; +static struct qmi_elem_info qmi_wlanfw_device_info_req_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_device_info_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_addr_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_addr), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_size_valid), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct qmi_wlanfw_device_info_resp_msg_v01, + bar_size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + static struct qmi_elem_info qmi_wlanfw_rf_chip_info_s_v01_ei[] = { { .data_type = QMI_UNSIGNED_4_BYTE, @@ -1342,6 +1855,24 @@ .ei_array = qmi_wlanfw_dev_mem_info_s_v01_ei, }, { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x25, + .offset = offsetof(struct qmi_wlanfw_cap_resp_msg_v01, + rxgainlut_support_valid), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x25, + .offset = offsetof(struct qmi_wlanfw_cap_resp_msg_v01, + rxgainlut_support), + }, + { .data_type = QMI_EOTI, .array_type = NO_ARRAY, .tlv_type = QMI_COMMON_TLV_TYPE, @@ -1879,6 +2410,85 @@ }, }; +struct qmi_elem_info qmi_wlanfw_qdss_trace_save_ind_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_save_ind_msg_v01, + source), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_save_ind_msg_v01, + total_size), + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_save_ind_msg_v01, + mem_seg_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_save_ind_msg_v01, + mem_seg_len), + }, + { + .data_type = QMI_STRUCT, + .elem_len = ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01, + .elem_size = sizeof(struct qmi_wlanfw_mem_seg_resp_s_v01), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_save_ind_msg_v01, + mem_seg), + .ei_array = qmi_wlanfw_mem_seg_resp_s_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_save_ind_msg_v01, + file_name_valid), + }, + { + .data_type = QMI_STRING, + .elem_len = QMI_WLANFW_MAX_STR_LEN_V01 + 1, + .elem_size = sizeof(char), + .array_type = NO_ARRAY, + .tlv_type = 0x11, + .offset = offsetof(struct + qmi_wlanfw_qdss_trace_save_ind_msg_v01, + file_name), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + static struct qmi_elem_info qmi_wlanfw_mem_ready_ind_msg_v01_ei[] = { { .data_type = QMI_EOTI, @@ -1893,34 +2503,649 @@ }, }; -static void ath12k_host_cap_parse_mlo(struct qmi_wlanfw_host_cap_req_msg_v01 *req) +struct qmi_elem_info wlfw_ini_req_msg_v01_ei[] = { { - req->mlo_capable_valid = 1; - req->mlo_capable = 1; - req->mlo_chip_id_valid = 1; - req->mlo_chip_id = 0; - req->mlo_group_id_valid = 1; + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_ini_req_msg_v01, + enablefwlog_valid), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct wlfw_ini_req_msg_v01, + enablefwlog), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info wlfw_ini_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct wlfw_ini_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlanfw_cold_boot_cal_done_ind_msg_v01_ei[] = { + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_read_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct qmi_wlanfw_mem_read_req_msg_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_mem_read_req_msg_v01, + mem_type), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct qmi_wlanfw_mem_read_req_msg_v01, + data_len), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_read_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_OPT_FLAG, + .elem_len = 1, + .elem_size = sizeof(u8), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + data_valid), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLANFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x10, + .offset = offsetof(struct + qmi_wlanfw_mem_read_resp_msg_v01, + data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_write_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + offset), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + mem_type), + }, + { + .data_type = QMI_DATA_LEN, + .elem_len = 1, + .elem_size = sizeof(u16), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + data_len), + }, + { + .data_type = QMI_UNSIGNED_1_BYTE, + .elem_len = QMI_WLANFW_MAX_DATA_SIZE_V01, + .elem_size = sizeof(u8), + .array_type = VAR_LEN_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct + qmi_wlanfw_mem_write_req_msg_v01, + data), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +struct qmi_elem_info qmi_wlanfw_mem_write_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_mem_write_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +int ath12k_qmi_mem_read(struct ath12k_base *ab, u32 mem_addr, void *mem_value,size_t count) +{ + struct qmi_wlanfw_mem_read_req_msg_v01 *req; + struct qmi_wlanfw_mem_read_resp_msg_v01 *resp; + struct qmi_txn txn = {}; + int ret; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->offset = mem_addr; + + /* Firmware uses mem type to map to various memory regions. + * If this is set to 0, firmware uses automatic mapping of regions. + * i.e, if mem address is given and mem_type is 0, firmware will + * find under which memory region that address belongs + */ + req->mem_type = QMI_MEM_REGION_TYPE; + req->data_len = count; + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_mem_read_resp_msg_v01_ei, resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_MEM_READ_REQ_V01, + QMI_WLANFW_MEM_READ_REQ_MSG_V01_MAX_MSG_LEN, + qmi_wlanfw_mem_read_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + ath12k_warn(ab, "Failed to send mem read request, err %d\n", + ret); + + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "qmi mem read req failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -EINVAL; + goto out; + } + + if (!resp->data_valid || resp->data_len != req->data_len) { + ath12k_warn(ab, "qmi mem read is invalid\n"); + ret = -EINVAL; + goto out; + } + memcpy(mem_value, resp->data, resp->data_len); + +out: + kfree(req); + kfree(resp); + return ret; +} + +int ath12k_qmi_mem_write(struct ath12k_base *ab, u32 mem_addr, void* mem_value, size_t count) +{ + struct qmi_wlanfw_mem_write_req_msg_v01 *req; + struct qmi_wlanfw_mem_write_resp_msg_v01 *resp; + struct qmi_txn txn = {}; + int ret; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->offset = mem_addr; + req->mem_type = QMI_MEM_REGION_TYPE; + req->data_len = count; + memcpy(req->data, mem_value, req->data_len); + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_mem_write_resp_msg_v01_ei, resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_MEM_WRITE_REQ_V01, + QMI_WLANFW_MEM_WRITE_REQ_MSG_V01_MAX_MSG_LEN, + qmi_wlanfw_mem_write_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + ath12k_warn(ab, "Failed to send mem write request, err %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "qmi mem write req failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -EINVAL; + goto out; + } + +out: + kfree(req); + kfree(resp); + return ret; +} + +static struct qmi_elem_info qmi_wlanfw_m3_dump_upload_req_ind_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct qmi_wlanfw_m3_dump_upload_req_ind_msg_v01, + pdev_id), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_m3_dump_upload_req_ind_msg_v01, + addr), + }, + { + .data_type = QMI_UNSIGNED_8_BYTE, + .elem_len = 1, + .elem_size = sizeof(u64), + .array_type = NO_ARRAY, + .tlv_type = 0x03, + .offset = offsetof(struct qmi_wlanfw_m3_dump_upload_req_ind_msg_v01, + size), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlanfw_m3_dump_upload_done_req_msg_v01_ei[] = { + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x01, + .offset = offsetof(struct + qmi_wlanfw_m3_dump_upload_done_req_msg_v01, + pdev_id), + }, + { + .data_type = QMI_UNSIGNED_4_BYTE, + .elem_len = 1, + .elem_size = sizeof(u32), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct + qmi_wlanfw_m3_dump_upload_done_req_msg_v01, + status), + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static struct qmi_elem_info qmi_wlanfw_m3_dump_upload_done_resp_msg_v01_ei[] = { + { + .data_type = QMI_STRUCT, + .elem_len = 1, + .elem_size = sizeof(struct qmi_response_type_v01), + .array_type = NO_ARRAY, + .tlv_type = 0x02, + .offset = offsetof(struct qmi_wlanfw_m3_dump_upload_done_resp_msg_v01, + resp), + .ei_array = qmi_response_type_v01_ei, + }, + { + .data_type = QMI_EOTI, + .array_type = NO_ARRAY, + .tlv_type = QMI_COMMON_TLV_TYPE, + }, +}; + +static int ath12k_qmi_send_qdss_trace_config_download_req(struct ath12k_base *ab, + const u8 *buffer, + unsigned int buffer_len) +{ + int ret = 0; + struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01 *req; + struct qmi_wlanfw_qdss_trace_config_download_resp_msg_v01 resp; + struct qmi_txn txn; + const u8 *temp = buffer; + int max_len = QMI_WLANFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_LEN; + unsigned int remaining; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + remaining = buffer_len; + while (remaining) { + memset(&resp, 0, sizeof(resp)); + req->total_size_valid = 1; + req->total_size = buffer_len; + req->seg_id_valid = 1; + req->data_valid = 1; + req->end_valid = 1; + + if (remaining > QMI_WLANFW_MAX_DATA_SIZE_V01) { + req->data_len = QMI_WLANFW_MAX_DATA_SIZE_V01; + } else { + req->data_len = remaining; + req->end = 1; + } + memcpy(req->data, temp, req->data_len); + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_qdss_trace_config_download_resp_msg_v01_ei, + &resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01, + max_len, + qmi_wlfw_qdss_trace_config_download_req_msg_v01_ei, + req); + if (ret < 0) { + ath12k_warn(ab, "Failed to send QDSS config download request = %d\n", + ret); + qmi_txn_cancel(&txn); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "QDSS config download request failed, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } + remaining -= req->data_len; + temp += req->data_len; + req->seg_id++; + } + +out: + kfree(req); + return ret; +} + +static int ath12k_qmi_send_qdss_config(struct ath12k_base *ab) +{ + struct device *dev = ab->dev; + const struct firmware *fw_entry; + char filename[ATH12K_QMI_MAX_QDSS_CONFIG_FILE_NAME_SIZE]; + int ret; + + snprintf(filename, sizeof(filename), + "%s/%s/%s", ATH12K_FW_DIR, ab->hw_params->fw.dir, + ATH12K_QMI_DEFAULT_QDSS_CONFIG_FILE_NAME); + ret = request_firmware(&fw_entry, filename, dev); + ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot firmware request %s size %zu\n", + filename, fw_entry->size); + if (ret) { + /* for backward compatibility */ + snprintf(filename, sizeof(filename), + "%s", ATH12K_QMI_DEFAULT_QDSS_CONFIG_FILE_NAME); + ret = request_firmware(&fw_entry, filename, dev); + ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot firmware request %s size %zu\n", + filename, fw_entry->size); + if (ret) { + ath12k_warn(ab, "qmi failed to load QDSS config: %s\n", filename); + return ret; + } + } + + ret = ath12k_qmi_send_qdss_trace_config_download_req(ab, fw_entry->data, + fw_entry->size); + if (ret < 0) { + ath12k_warn(ab, "qmi failed to load QDSS config to FW: %d\n", ret); + goto out; + } +out: + release_firmware(fw_entry); + return ret; +} + +static int ath12k_qmi_fill_mlo_host_caps(struct ath12k_base *ab, + struct qmi_wlanfw_host_cap_req_msg_v01 *req) +{ + struct wlfw_host_mlo_chip_info_s_v01 *info; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_base *partner_ab; + int ret, i, j, link_id; + + mutex_lock(&ag->mutex_lock); + + if (!ag->mlo_capable) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "Skip MLO cap send for chip id %d since it's not MLO capable\n", + ab->chip_id); + mutex_unlock(&ag->mutex_lock); + return 0; + } + + if (ath12k_cold_boot_cal && ab->qmi.cal_done == 0 && + ab->hw_params->cold_boot_calib && + ab->qmi.cal_timeout == 0) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "Skip MLO cap send for chip id %d since it's in cold_boot\n", + ab->chip_id); + mutex_unlock(&ag->mutex_lock); + return 0; + } + + if (ag->id == ATH12K_INVALID_GRP_ID || !ab->qmi.num_radios) { + ag->mlo_capable = false; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "Skip MLO cap send for chip id %d due to group_id %d qmi num_radio %d\n", + ab->chip_id, ag->id, ab->qmi.num_radios); + mutex_unlock(&ag->mutex_lock); + return 0; + } + + if (ab->chip_id == ATH12K_INVALID_CHIP_ID) { + ath12k_err(ab, "failed to send MLO cap send due to Invalid chip id\n"); + + ret = -EINVAL; + goto out; + } + + req->mlo_capable = true; + req->mlo_capable_valid = true; + + req->mlo_chip_id = ab->chip_id; + req->mlo_chip_id_valid = true; + + req->mlo_group_id = ag->id; + req->mlo_group_id_valid = true; + + req->max_mlo_peer = ab->hw_params->max_mlo_peer; + req->max_mlo_peer_valid = true; + + req->mlo_num_chips = ag->num_chip; + req->mlo_num_chips_valid = true; + + link_id = 0; + for (i = 0; i < ag->num_chip; i++) { + info = &req->mlo_chip_info[i]; + partner_ab = ag->ab[i]; + + if (partner_ab->chip_id == ATH12K_INVALID_CHIP_ID) { + ret = -EINVAL; + goto chip_cleanup; + } + + info->chip_id = partner_ab->chip_id; + + info->num_local_links = partner_ab->qmi.num_radios; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "MLO chip id %d num_link %d\n", + partner_ab->chip_id, info->num_local_links); + + for (j = 0; j < info->num_local_links; j++) { + info->hw_link_id[j] = link_id; + info->valid_mlo_link_id[j] = true; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "MLO link id %d\n", + info->hw_link_id[j]); + + link_id++; + } + } + + /* Disable MLO capable if there is no Multi-link in a group */ + if (link_id <= 1) + ag->mlo_capable = false; + + req->mlo_chip_info_valid = true; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "MLO host cap chosen\n"); + + mutex_unlock(&ag->mutex_lock); + return 0; + +chip_cleanup: + for (i = i - 1; i >= 0; i--) { + info = &req->mlo_chip_info[i]; + + memset(info, 0, sizeof(*info)); + } + + req->mlo_num_chips = 0; + req->mlo_num_chips_valid = 0; + + req->max_mlo_peer = 0; + req->max_mlo_peer_valid = 0; req->mlo_group_id = 0; - req->max_mlo_peer_valid = 1; - /* Max peer number generally won't change for the same device - * but needs to be synced with host driver. - */ - req->max_mlo_peer = 32; - req->mlo_num_chips_valid = 1; - req->mlo_num_chips = 1; - req->mlo_chip_info_valid = 1; - req->mlo_chip_info[0].chip_id = 0; - req->mlo_chip_info[0].num_local_links = 2; - req->mlo_chip_info[0].hw_link_id[0] = 0; - req->mlo_chip_info[0].hw_link_id[1] = 1; - req->mlo_chip_info[0].valid_mlo_link_id[0] = 1; - req->mlo_chip_info[0].valid_mlo_link_id[1] = 1; + req->mlo_group_id_valid = 0; + req->mlo_chip_id = 0; + req->mlo_chip_id_valid = 0; + req->mlo_capable = 0; + req->mlo_capable_valid = 0; + + ag->mlo_capable = false; +out: + mutex_unlock(&ag->mutex_lock); + + return ret; } static int ath12k_qmi_host_cap_send(struct ath12k_base *ab) { struct qmi_wlanfw_host_cap_req_msg_v01 req; struct qmi_wlanfw_host_cap_resp_msg_v01 resp; + struct ath12k_board_data bd; + struct device_node *root; + const char *model = NULL; struct qmi_txn txn = {}; int ret = 0; @@ -1934,16 +3159,39 @@ req.bdf_support_valid = 1; req.bdf_support = 1; + if (ab->hw_params->m3_fw_support) { req.m3_support_valid = 1; req.m3_support = 1; req.m3_cache_support_valid = 1; req.m3_cache_support = 1; + } else { + req.m3_support_valid = 0; + req.m3_support = 0; + req.m3_cache_support_valid = 0; + req.m3_cache_support = 0; + } req.cal_done_valid = 1; req.cal_done = ab->qmi.cal_done; + if (ab->hw_params->send_platform_model) { + root = of_find_node_by_path("/"); + if (root) { + model = of_get_property(root, "model", NULL); + if (model) { + req.platform_name_valid = 1; + strlcpy(req.platform_name, model, + QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01); + ath12k_info(ab, "Platform name: %s", req.platform_name); + } + of_node_put(root); + } + } + + if (ab->hw_params->qmi_cnss_feature_bitmap) { req.feature_list_valid = 1; - req.feature_list = BIT(CNSS_QDSS_CFG_MISS_V01); + req.feature_list = ab->hw_params->qmi_cnss_feature_bitmap; + } /* BRINGUP: here we are piggybacking a lot of stuff using * internal_sleep_clock, should it be split? @@ -1961,8 +3209,20 @@ */ req.nm_modem |= SLEEP_CLOCK_SELECT_INTERNAL_BIT; req.nm_modem |= PLATFORM_CAP_PCIE_GLOBAL_RESET; + } + + ret = ath12k_core_fetch_fw_cfg(ab, &bd); + if (!ret) { + req.fw_cfg_support_valid = 1; + req.fw_cfg_support = 1; + } + ab->fw_cfg_support = !!req.fw_cfg_support; + ath12k_core_free_bdf(ab, &bd); - ath12k_host_cap_parse_mlo(&req); + ret = ath12k_qmi_fill_mlo_host_caps(ab, &req); + if (ret < 0) { + ath12k_warn(ab, "Failed to get MLO capability,err = %d\n", ret); + goto out; } ret = qmi_txn_init(&ab->qmi.handle, &txn, @@ -1994,6 +3254,53 @@ return ret; } +static int ath12k_qmi_phy_cap_send(struct ath12k_base *ab) +{ + struct qmi_wlanfw_phy_cap_req_msg_v01 req = { }; + struct qmi_wlanfw_phy_cap_resp_msg_v01 resp = { }; + struct qmi_txn txn = { }; + int ret; + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_phy_cap_resp_msg_v01_ei, &resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_PHY_CAP_REQ_V01, + QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN, + qmi_wlanfw_phy_cap_req_msg_v01_ei, &req); + if (ret < 0) { + ath12k_warn(ab, "failed to send phy capability request, err = %d\n", ret); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ret = -EOPNOTSUPP; + goto out; + } + + if (!resp.num_phy_valid) { + ret = -ENODATA; + goto out; + } + + ab->qmi.num_radios = resp.num_phy; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "PHY capability resp valid %d num_phy %d valid %d board_id %d\n", + resp.num_phy_valid, resp.num_phy, + resp.board_id_valid, resp.board_id); + return 0; + +out: + ab->qmi.num_radios = ab->hw_params->num_local_link; + return ret; +} + static int ath12k_qmi_fw_ind_register_send(struct ath12k_base *ab) { struct qmi_wlanfw_ind_register_req_msg_v01 *req; @@ -2024,6 +3331,14 @@ req->cal_done_enable = 1; req->fw_init_done_enable_valid = 1; req->fw_init_done_enable = 1; + req->qdss_trace_req_mem_enable_valid = 1; + req->qdss_trace_req_mem_enable = 1; + req->qdss_trace_save_enable_valid = 1; + req->qdss_trace_save_enable = 1; + req->qdss_trace_free_enable_valid = 1; + req->qdss_trace_free_enable = 1; + req->m3_dump_upload_req_enable_valid = 1; + req->m3_dump_upload_req_enable = 1; req->pin_connect_result_enable_valid = 0; req->pin_connect_result_enable = 0; @@ -2082,7 +3397,7 @@ * failure to firmware and firmware then request multiple blocks of * small chunk size memory. */ - if (ab->qmi.target_mem_delayed) { + if (!ab->bus_params.fixed_mem_region && ab->qmi.target_mem_delayed) { delayed = true; ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi delays mem_request %d\n", ab->qmi.mem_seg_count); @@ -2094,8 +3409,7 @@ req->mem_seg[i].addr = ab->qmi.target_mem[i].paddr; req->mem_seg[i].size = ab->qmi.target_mem[i].size; req->mem_seg[i].type = ab->qmi.target_mem[i].type; - ath12k_dbg(ab, ATH12K_DBG_QMI, - "qmi req mem_seg[%d] %pad %u %u\n", i, + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi req mem_seg[%d] %pad %u %u\n", i, &ab->qmi.target_mem[i].paddr, ab->qmi.target_mem[i].size, ab->qmi.target_mem[i].type); @@ -2140,11 +3454,117 @@ return ret; } -static void ath12k_qmi_free_target_mem_chunk(struct ath12k_base *ab) +/** + * ath12k_free_mlo_glb_per_chip_crash_info() - Free MLO per_chip crash info + * @snapshot_info: Pointer to MLO Global crash info + * + * Return: None + */ +static void ath12k_free_mlo_glb_per_chip_crash_info( + struct ath12k_host_mlo_glb_chip_crash_info *global_chip_crash_info) { - int i; + if (global_chip_crash_info->per_chip_crash_info) { + kfree(global_chip_crash_info->per_chip_crash_info); + global_chip_crash_info->per_chip_crash_info = NULL; + } +} + +/** + * ath12k_free_mlo_mgmt_rx_reo_per_link_info() - Free Rx REO per-link info + * @snapshot_info: Pointer to MGMT Rx REO snapshot info + * + * Return: None + */ +void ath12k_free_mlo_mgmt_rx_reo_per_link_info + (struct ath12k_host_mlo_glb_rx_reo_snapshot_info *snapshot_info) +{ + if (snapshot_info && snapshot_info->link_info) { + kfree(snapshot_info->link_info); + snapshot_info->link_info = NULL; + } +} + +static void ath12k_qmi_free_mlo_mem_chunk(struct ath12k_base *ab, + struct target_mem_chunk *chunk, + int idx) +{ + struct ath12k_hw_group *ag = ab->ag; + struct target_mem_chunk *mlo_chunk; + bool fixed_mem = ab->bus_params.fixed_mem_region; + struct ath12k_host_mlo_mem_arena + *mlomem_arena_ctx = &ab->ag->mlomem_arena; + + lockdep_assert_held(&ag->mutex_lock); + + if (!ag->mlo_mem.init_done || ag->num_started) + return; + + if (idx >= ARRAY_SIZE(ag->mlo_mem.chunk)) { + ath12k_warn(ab, "invalid idx %d for MLO memory chunk free\n", idx); + return; + } + + mlo_chunk = &ag->mlo_mem.chunk[idx]; + + if (fixed_mem) { + if (mlo_chunk->v.ioaddr) { + iounmap(mlo_chunk->v.ioaddr); + mlo_chunk->v.ioaddr = NULL; + } + } else { + if (mlo_chunk->v.addr) { + dma_free_coherent(ab->dev, + mlo_chunk->size, + mlo_chunk->v.addr, + mlo_chunk->paddr); + mlo_chunk->v.addr = NULL; + } + } - for (i = 0; i < ab->qmi.mem_seg_count; i++) { + mlo_chunk->paddr = 0; + mlo_chunk->size = 0; + + if (fixed_mem) + chunk->v.ioaddr = NULL; + else + chunk->v.addr = NULL; + chunk->paddr = 0; + chunk->size = 0; + + ag->mlo_mem.is_mlo_mem_avail = false; + + /* We need to de-initialize when mlo memory is cleaned */ + mutex_lock(&mlomem_arena_ctx->mutex_lock); + if (mlomem_arena_ctx->init_done) { + mlomem_arena_ctx->init_done = false; + ath12k_free_mlo_mgmt_rx_reo_per_link_info + (&mlomem_arena_ctx->rx_reo_snapshot_info); + ath12k_free_mlo_glb_per_chip_crash_info + (&mlomem_arena_ctx->global_chip_crash_info); + } + mutex_unlock(&mlomem_arena_ctx->mutex_lock); + + return; +} + +void ath12k_qmi_free_target_mem_chunk(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + int i, mlo_idx; + + for (i = 0, mlo_idx = 0; i < ab->qmi.mem_seg_count; i++) { + if (ab->qmi.target_mem[i].type == MLO_GLOBAL_MEM_REGION_TYPE) { + ath12k_qmi_free_mlo_mem_chunk(ab, + &ab->qmi.target_mem[i], + mlo_idx); + } else { + if (ab->bus_params.fixed_mem_region) { + if (!ab->qmi.target_mem[i].v.ioaddr) + continue; + + iounmap(ab->qmi.target_mem[i].v.ioaddr); + ab->qmi.target_mem[i].v.ioaddr = NULL; + } else { if (!ab->qmi.target_mem[i].v.addr) continue; dma_free_coherent(ab->dev, @@ -2154,26 +3574,18 @@ ab->qmi.target_mem[i].v.addr = NULL; } } + } -static int ath12k_qmi_alloc_target_mem_chunk(struct ath12k_base *ab) -{ - int i; - struct target_mem_chunk *chunk; - - ab->qmi.target_mem_delayed = false; - - for (i = 0; i < ab->qmi.mem_seg_count; i++) { - chunk = &ab->qmi.target_mem[i]; + if (!ag->num_started && ag->mlo_mem.init_done) { + memset(ag->mlo_mem.chunk, 0, sizeof(ag->mlo_mem.chunk)); + ag->mlo_mem.rsv = NULL; + ag->mlo_mem.init_done = false; + } +} - /* Allocate memory for the region and the functionality supported - * on the host. For the non-supported memory region, host does not - * allocate memory, assigns NULL and FW will handle this without crashing. - */ - switch (chunk->type) { - case HOST_DDR_REGION_TYPE: - case M3_DUMP_REGION_TYPE: - case PAGEABLE_MEM_REGION_TYPE: - case CALDB_MEM_REGION_TYPE: +static int ath12k_qmi_alloc_chunk(struct ath12k_base *ab, + struct target_mem_chunk *chunk) +{ chunk->v.addr = dma_alloc_coherent(ab->dev, chunk->size, &chunk->paddr, @@ -2186,12 +3598,67 @@ chunk->size, chunk->type); ath12k_qmi_free_target_mem_chunk(ab); - return 0; + return -EAGAIN; } ath12k_warn(ab, "memory allocation failure for %u size: %d\n", chunk->type, chunk->size); return -ENOMEM; } + + return 0; +} + +static int ath12k_qmi_alloc_target_mem_chunk(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + int i, mlo_idx, ret; + struct target_mem_chunk *chunk, *mlo_chunk; + + mutex_lock(&ag->mutex_lock); + + if (!ag->mlo_mem.init_done) { + memset(ag->mlo_mem.chunk, 0, sizeof(ag->mlo_mem.chunk)); + ag->mlo_mem.init_done = true; + } + + ab->qmi.target_mem_delayed = false; + + for (i = 0, mlo_idx = 0; i < ab->qmi.mem_seg_count; i++) { + chunk = &ab->qmi.target_mem[i]; + + /* Allocate memory for the region and the functionality supported + * on the host. For the non-supported memory region, host does not + * allocate memory, assigns NULL and FW will handle this without crashing. + */ + switch (chunk->type) { + case MLO_GLOBAL_MEM_REGION_TYPE: + mlo_chunk = &ag->mlo_mem.chunk[mlo_idx]; + if (!mlo_chunk->paddr) { + mlo_chunk->size = chunk->size; + mlo_chunk->type = chunk->type; + + ret = ath12k_qmi_alloc_chunk(ab, mlo_chunk); + if (ret) { + ret = (ret == -EAGAIN) ? 0 : ret; + goto out; + } + + memset(mlo_chunk->v.addr, 0, mlo_chunk->size); + } + chunk->paddr = mlo_chunk->paddr; + chunk->v.addr = mlo_chunk->v.addr; + ag->mlo_mem.is_mlo_mem_avail = true; + mlo_idx++; + break; + case HOST_DDR_REGION_TYPE: + case M3_DUMP_REGION_TYPE: + case PAGEABLE_MEM_REGION_TYPE: + case CALDB_MEM_REGION_TYPE: + ret = ath12k_qmi_alloc_chunk(ab, chunk); + if (ret) { + ret = (ret == -EAGAIN) ? 0 : ret; + goto out; + } break; default: ath12k_warn(ab, "memory type %u not supported\n", @@ -2201,17 +3668,904 @@ break; } } + + mutex_unlock(&ag->mutex_lock); + return 0; + +out: + ath12k_qmi_free_target_mem_chunk(ab); + mutex_unlock(&ag->mutex_lock); + return ret; +} + +/** + * ath12k_mgmt_rx_reo_process_tlv_header() - Process a given TLV header + * @data: Pointer to start of the TLV + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @expected_tag: Expected TLV tag + * @tlv_len: Address of TLV length variable to be populated. This API populates + * the entire length(payload + header) of the TLV into @tlv_len + * @tlv_tag: Address of TLV Tag variable to be populated. + * + * Return: 0 on success, -1 on failure + */ +static int +ath12k_mgmt_rx_reo_process_tlv_header(struct ath12k_base *ab, + const u8 *data, size_t remaining_len, + u32 expected_tag, u32 *tlv_len, + u32 *tlv_tag) +{ + if (remaining_len < MLO_SHMEM_TLV_HDR_SIZE) { + ath12k_err(ab, "Not enough space(%zu) to read TLV header(%u)\n", + remaining_len, (u32)MLO_SHMEM_TLV_HDR_SIZE); + return -EINVAL; + } + *tlv_len = MLO_SHMEMTLV_GET_TLVLEN(MLO_SHMEMTLV_GET_HDR(data)); + *tlv_len += MLO_SHMEM_TLV_HDR_SIZE; + if (remaining_len < *tlv_len) { + ath12k_err(ab, "Not enough space(%zu) to read TLV payload(%u)\n", + remaining_len, *tlv_len); + return -EINVAL; + } + + *tlv_tag = MLO_SHMEMTLV_GET_TLVTAG(MLO_SHMEMTLV_GET_HDR(data)); + if (*tlv_tag != expected_tag) { + ath12k_err(ab, "Unexpected TLV tag: %u is seen. Expected: %u\n", + *tlv_tag, + expected_tag); + return -EINVAL; + } + return 0; } +/** + * ath12k_mgmt_rx_reo_extract_ath12k_mlo_glb_shmem_tlv() - extract ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM + * TLV + * @data: Pointer to start of the TLV + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @shmem_params: Pointer to MLO Global shared memory parameters. Extracted + * information will be populated in this data structure. + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_extract_ath12k_mlo_glb_shmem_tlv(struct ath12k_base *ab, + u8 *data, size_t remaining_len, + struct ath12k_host_ath12k_mlo_glb_shmem_params *shmem_params) +{ + struct ath12k_mlo_glb_shmem *ptlv; + u32 tlv_len, tlv_tag; + u32 major_minor_version; + + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM, + &tlv_len, &tlv_tag) < 0) { + ath12k_err(ab, "%s:process tlv hdr failed\n", __func__); + return -EINVAL; + } + + ptlv = (struct ath12k_mlo_glb_shmem *)data; + major_minor_version = get_field_value_in_tlv(ptlv, major_minor_version, + tlv_len); + shmem_params->major_version = + MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_GET( + major_minor_version); + shmem_params->minor_version = + MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_GET( + major_minor_version); + + return tlv_len; +} + +/** + * ath12k_mgmt_rx_reo_extract_mlo_glb_link_info_tlv() - extract lobal link info from shmem + * @data: Pointer to the first TLV in the arena + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @link_info: Pointer to which link info needs to be copied + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_extract_mlo_glb_link_info_tlv(struct ath12k_base *ab, + u8 *data, + size_t remaining_len, + u32 *link_info) +{ + struct mlo_glb_link_info *ptlv; + u32 tlv_len, tlv_tag; + + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO, + &tlv_len, &tlv_tag) < 0) { + ath12k_err(ab, "%s:process tlv hdr failed\n", __func__); + return -EPERM; + } + + ptlv = (struct mlo_glb_link_info *)data; + + *link_info = get_field_value_in_tlv(ptlv, link_info, tlv_len); + + return tlv_len; +} + +/** + * ath12k_mgmt_rx_reo_process_mlo_glb_per_link_status_tlv() - process per link info + * @data: Pointer to the first TLV in the arena + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_process_mlo_glb_per_link_status_tlv(struct ath12k_base *ab, + u8 *data, size_t remaining_len) +{ + u32 tlv_len, tlv_tag; + + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK, + &tlv_len, &tlv_tag) < 0) { + ath12k_err(ab, "%s:process tlv hdr failed\n", __func__); + return -EPERM; + } + + return tlv_len; +} + +/** + * ath12k_mgmt_rx_reo_parse_global_link_info() - parse lobal link info + * @data: Pointer to the first TLV in the arena + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_parse_global_link_info(struct ath12k_base *ab, u8 *data, size_t remaining_len) +{ + int parsed_bytes, len; + u8 link; + u32 link_info; + u8 num_links; + + /* Extract ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO_TLV */ + len = ath12k_mgmt_rx_reo_extract_mlo_glb_link_info_tlv(ab, data, remaining_len, &link_info); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes = len; + + num_links = MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_GET(link_info); + + for (link = 0; link < num_links; link++) { + len = ath12k_mgmt_rx_reo_process_mlo_glb_per_link_status_tlv(ab, data, remaining_len); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, + remaining_len); + parsed_bytes += len; + } + + return parsed_bytes; +} + +/** + * ath12k_mgmt_rx_reo_get_num_links_from_valid_link_bitmap() - Get the number of valid links + * @valid_link_bmap: Link bit map where the valid links are set to 1 + * + * Return: Number of valid links + */ +static u8 +ath12k_mgmt_rx_reo_get_num_links_from_valid_link_bitmap(u16 valid_link_bmap) +{ + u8 num_links = 0; + + /* Find the number of set bits */ + while (valid_link_bmap) { + num_links++; + valid_link_bmap &= (valid_link_bmap - 1); + } + + return num_links; +} + +static int +ath12k_mgmt_mlo_global_per_chip_crash_info_tlv(struct ath12k_base *ab, + u8 *data, + size_t remaining_len, u8 cur_chip_id, + struct ath12k_host_mlo_glb_per_chip_crash_info *per_chip_crash_info) +{ + struct mlo_glb_per_chip_crash_info *ptlv; + u32 tlv_len, tlv_tag; + u8 *crash_reason, *recovery_mode; + + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO, + &tlv_len, &tlv_tag) < 0) { + return -EPERM; + } + + ptlv = (struct mlo_glb_per_chip_crash_info *)data; + per_chip_crash_info->chip_id = cur_chip_id; + crash_reason = (u8 *)get_field_pointer_in_tlv(ptlv, crash_reason, tlv_len); + recovery_mode = (u8 *)get_field_pointer_in_tlv(ptlv, recovery_mode, tlv_len); + + per_chip_crash_info->crash_reason = (void *)crash_reason; + per_chip_crash_info->recovery_mode = (void *)recovery_mode; + + return tlv_len; +} + +static int +ath12k_mgmt_mlo_global_chip_crash_info_tlv(struct ath12k_base *ab, + u8 *data, + size_t remaining_len, + struct ath12k_host_mlo_glb_chip_crash_info *global_chip_crash_info) +{ + struct mlo_glb_chip_crash_info *ptlv; + u32 tlv_len, tlv_tag; + u32 chip_info; + u8 chip_map; + + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO, + &tlv_len, &tlv_tag) < 0) { + return -EPERM; + } + + ptlv = (struct mlo_glb_chip_crash_info *)data; + chip_info = get_field_value_in_tlv(ptlv, chip_info, tlv_len); + global_chip_crash_info->no_of_chips = + MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info); + chip_map = MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info); + + memcpy(&global_chip_crash_info->valid_chip_bmap, + &chip_map, + min(sizeof(global_chip_crash_info->valid_chip_bmap), + sizeof(chip_map))); + + /* Allocate memory to extrace per chip crash info */ + global_chip_crash_info->per_chip_crash_info = kmalloc_array( + global_chip_crash_info->no_of_chips, + sizeof(*global_chip_crash_info->per_chip_crash_info), + GFP_KERNEL); + + if (!global_chip_crash_info->per_chip_crash_info) + { + ath12k_warn(ab, "Couldn't allocate memory for per chip crash info!\n"); + return -ENOBUFS; + } + + return tlv_len; +} + +static int +ath12k_mgmt_mlo_global_chip_crash_info(struct ath12k_base *ab, + u8 *data, + size_t remaining_len, + struct ath12k_host_mlo_glb_chip_crash_info *global_chip_crash_info) +{ + u8 chip_id; + s32 len,parsed_bytes; + unsigned long valid_chip_bmap, cur_chip_id; + + len = ath12k_mgmt_mlo_global_chip_crash_info_tlv(ab, data, remaining_len, + global_chip_crash_info); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes = len; + + if (len < 0) + return len; + + memcpy(&valid_chip_bmap, + &global_chip_crash_info->valid_chip_bmap, + min(sizeof(valid_chip_bmap), + sizeof(global_chip_crash_info->valid_chip_bmap))); + + /* Extract per chip crash info */ + for (chip_id = 0; chip_id < global_chip_crash_info->no_of_chips; + chip_id++) { + cur_chip_id = find_first_bit(&valid_chip_bmap, 8); + __clear_bit(cur_chip_id, &valid_chip_bmap); + + if (WARN_ON(cur_chip_id < 0)) { + /* Exit gracefully */ + return 0; + } + + len = ath12k_mgmt_mlo_global_per_chip_crash_info_tlv(ab, data, + remaining_len, cur_chip_id, + &global_chip_crash_info->per_chip_crash_info[chip_id]); + if (len < 0) { + WARN_ON(1); + return len; + } + + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes += len; + } + + return parsed_bytes; +} + +/** + * ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_snapshot_info_tlv() - extract + * ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO TLV + * @data: Pointer to start of the TLV + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @snapshot_info: Pointer to MGMT Rx REO snapshot info. Extracted information + * will be populated in this data structure. + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_snapshot_info_tlv(struct ath12k_base *ab, + u8 *data, size_t remaining_len, + struct ath12k_host_mlo_glb_rx_reo_snapshot_info *snapshot_info) +{ + struct mlo_glb_rx_reo_snapshot_info *ptlv; + u32 tlv_len, tlv_tag; + u32 link_info; + u16 valid_link_bmap; + + /* process ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO TLV */ + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO, + &tlv_len, &tlv_tag) < 0) { + ath12k_err(ab, "%s:process tlv hdr failed\n", __func__); + return -EINVAL; + } + + ptlv = (struct mlo_glb_rx_reo_snapshot_info *)data; + link_info = get_field_value_in_tlv(ptlv, link_info, tlv_len); + valid_link_bmap = + MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_GET(link_info); + snapshot_info->valid_link_bmap = valid_link_bmap; + + if (is_field_present_in_tlv(ptlv, snapshot_ver_info, tlv_len)) { + u32 snapshot_ver_info; + + snapshot_ver_info = get_field_value_in_tlv + (ptlv, snapshot_ver_info, tlv_len); + snapshot_info->hw_forwarded_snapshot_ver = + MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_GET + (snapshot_ver_info); + snapshot_info->fw_forwarded_snapshot_ver = + MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_GET + (snapshot_ver_info); + snapshot_info->fw_consumed_snapshot_ver = + MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_GET + (snapshot_ver_info); + } + + snapshot_info->num_links = + ath12k_mgmt_rx_reo_get_num_links_from_valid_link_bitmap(valid_link_bmap); + snapshot_info->link_info = kmalloc_array(snapshot_info->num_links, + sizeof(*snapshot_info->link_info), + GFP_KERNEL); + if (!snapshot_info->link_info) { + ath12k_err(ab, "Couldn't allocate memory for rx_reo_per_link_info\n"); + return -EINVAL; + } + + return tlv_len; +} + +/** + * ath12k_mgmt_rx_reo_get_next_valid_link_id() - Get next valid link ID + * @valid_link_bmap: Link bit map where the valid links are set to 1 + * @prev_link_id: Previous link ID + * + * Return: Next valid link ID if there are valid links after @prev_link_id, + * else -1 + */ +static int +ath12k_mgmt_rx_reo_get_next_valid_link_id(u16 valid_link_bmap, int prev_link_id) +{ + int cur_link_id; + u16 mask; + u8 maxbits = sizeof(valid_link_bmap) * 8; + + cur_link_id = prev_link_id + 1; + mask = 1 << cur_link_id; + + while (!(valid_link_bmap & mask)) { + cur_link_id++; + if (cur_link_id == maxbits) + return -EINVAL; + mask = mask << 1; + } + + return cur_link_id; +} + +/** + * ath12k_mgmt_rx_reo_extract_mgmt_rx_reo_snapshot_tlv() - extract MGMT_RX_REO_SNAPSHOT TLV + * @data: Pointer to start of the TLV + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @address_ptr: Pointer to the snapshot address. This API will populate the + * snapshot address into the variable pointed by @address_ptr + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_extract_mgmt_rx_reo_snapshot_tlv(struct ath12k_base *ab, + u8 *data, size_t remaining_len, + void **address_ptr) +{ + struct mgmt_rx_reo_snapshot *ptlv; + u32 tlv_len, tlv_tag; + + /* process ATH12K_MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT TLV */ + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT, + &tlv_len, &tlv_tag) < 0) { + ath12k_err(ab, "%s:process tlv hdr failed\n", __func__); + return -EINVAL; + } + + ptlv = (struct mgmt_rx_reo_snapshot *)data; + *address_ptr = get_field_pointer_in_tlv(ptlv, mgmt_rx_reo_snapshot_low, + tlv_len); + + return tlv_len; +} + +/** + * ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_per_link_info_tlv() - extract + * RX_REO_PER_LINK_SNAPSHOT_INFO TLV + * @data: Pointer to start of the TLV + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @link_info: Pointer to MGMT Rx REO per link info. Extracted information + * will be populated in this data structure. + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_per_link_info_tlv(struct ath12k_base *ab, + u8 *data, size_t remaining_len, u8 link_id, + struct ath12k_host_mlo_glb_rx_reo_per_link_info *link_info) +{ + struct mlo_glb_rx_reo_per_link_snapshot_info *ptlv; + u32 tlv_len, tlv_tag; + int len; + u8 *fw_consumed; + int parsed_bytes; + + /* process ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO TLV */ + if (ath12k_mgmt_rx_reo_process_tlv_header(ab, data, remaining_len, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO, + &tlv_len, &tlv_tag) < 0) { + ath12k_err(ab, "%s:process tlv hdr failed\n", __func__); + return -EINVAL; + } + + ptlv = (struct mlo_glb_rx_reo_per_link_snapshot_info *)data; + + link_info->link_id = link_id; + + /** + * Get the pointer to the fw_consumed snapshot with in the TLV. + * Note that snapshots are nested TLVs within link_sanpshot_info TLV. + */ + data += offsetof(struct mlo_glb_rx_reo_per_link_snapshot_info, + fw_consumed); + fw_consumed = (u8 *)get_field_pointer_in_tlv(ptlv, fw_consumed, + tlv_len); + remaining_len -= offsetof(struct mlo_glb_rx_reo_per_link_snapshot_info, + fw_consumed); + parsed_bytes = offsetof(struct mlo_glb_rx_reo_per_link_snapshot_info, + fw_consumed); + + /* extract fw_consumed snapshot */ + len = ath12k_mgmt_rx_reo_extract_mgmt_rx_reo_snapshot_tlv(ab, data, remaining_len, + &link_info->fw_consumed); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes += len; + + /* extract fw_forwarded snapshot */ + len = ath12k_mgmt_rx_reo_extract_mgmt_rx_reo_snapshot_tlv(ab, data, remaining_len, + &link_info->fw_forwarded); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes += len; + + /* extract hw_forwarded snapshot */ + len = ath12k_mgmt_rx_reo_extract_mgmt_rx_reo_snapshot_tlv(ab, data, remaining_len, + &link_info->hw_forwarded); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes += len; + + /** + * Return the length of link_sanpshot_info TLV itself as the snapshots + * are nested inside link_sanpshot_info TLV and hence no need to add + * their lengths separately. + */ + return tlv_len; +} + +/** + * ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_snapshot_info() - extract MGMT Rx REO snapshot info + * @data: Pointer to start of ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO + * TLV + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @snapshot_info: Pointer to MGMT Rx REO snapshot info. Extracted information + * will be populated in this data structure. + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int +ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_snapshot_info(struct ath12k_base *ab, + u8 *data, size_t remaining_len, + struct ath12k_host_mlo_glb_rx_reo_snapshot_info *snapshot_info) +{ + int parsed_bytes, len; + u8 link; + int cur_link_id, prev_link_id = -1; + u16 valid_link_bmap; + + /* Extract ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO TLV */ + len = ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_snapshot_info_tlv(ab, data, remaining_len, + snapshot_info); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes = len; + + valid_link_bmap = snapshot_info->valid_link_bmap; + /* Foreach valid link */ + for (link = 0; link < snapshot_info->num_links; ++link) { + cur_link_id = ath12k_mgmt_rx_reo_get_next_valid_link_id(valid_link_bmap, + prev_link_id); + + BUG_ON(!(cur_link_id >= 0)); + + /* Extract per_link_info */ + len = ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_per_link_info_tlv(ab, + data, remaining_len, cur_link_id, + &snapshot_info->link_info[link]); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, + remaining_len); + parsed_bytes += len; + prev_link_id = cur_link_id; + } + + return parsed_bytes; +} + +/** + * ath12k_qmi_parse_mlo_mem_arena() - Parse MLO Global shared memory arena + * @data: Pointer to the first TLV in the arena + * @remaining_len: Length (in bytes) remaining in the arena from @data pointer + * @mlomem_arena_ctx: Pointer to MLO Global shared memory arena context. + * Extracted information will be populated in this data structure. + * + * Return: On success, the number of bytes parsed. On failure, errno is returned. + */ +static int ath12k_qmi_parse_mlo_mem_arena(struct ath12k_base *ab, + u8 *data, size_t remaining_len, + struct ath12k_host_mlo_mem_arena *mlomem_arena_ctx) +{ + int parsed_bytes; + int len; + + if (!data) + return -EINVAL; + + len = ath12k_mgmt_rx_reo_extract_ath12k_mlo_glb_shmem_tlv(ab, data, remaining_len, + &mlomem_arena_ctx->shmem_params); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes = len; + + len = ath12k_mgmt_rx_reo_extract_mlo_glb_rx_reo_snapshot_info(ab, + data, remaining_len, &mlomem_arena_ctx->rx_reo_snapshot_info); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes += len; + + len = ath12k_mgmt_rx_reo_parse_global_link_info(ab, data, remaining_len); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes += len; + + len = ath12k_mgmt_mlo_global_chip_crash_info(ab, data, remaining_len, + &mlomem_arena_ctx->global_chip_crash_info); + ATH12K_VALIDATE_PARSED_DATA_POINTER(len, data, remaining_len); + parsed_bytes += len; + + return parsed_bytes; +} + +int ath12k_qmi_mlo_global_snapshot_mem_init(struct ath12k_base *ab) +{ + struct ath12k_host_mlo_mem_arena *mlomem_arena_ctx = &ab->ag->mlomem_arena; + struct ath12k_hw_group *ag = ab->ag; + struct target_mem_chunk *mlo_chunk; + int ret = 0, mlo_idx = 0; + + if (!ag->mlo_mem.is_mlo_mem_avail) + return 0; + + mlo_chunk = &ab->ag->mlo_mem.chunk[mlo_idx]; + + /* We need to initialize only for the first invocation */ + mutex_lock(&mlomem_arena_ctx->mutex_lock); + if (mlomem_arena_ctx->init_done) { + mutex_unlock(&mlomem_arena_ctx->mutex_lock); + return 0; + } + + if (ab->bus_params.fixed_mem_region) + ret = ath12k_qmi_parse_mlo_mem_arena(ab, + mlo_chunk->v.ioaddr, + mlo_chunk->size, + mlomem_arena_ctx); + else + ret = ath12k_qmi_parse_mlo_mem_arena(ab, + mlo_chunk->v.addr, + mlo_chunk->size, + mlomem_arena_ctx); + + if (ret < 0) { + ath12k_err(ab, "parsing of mlo shared memory failed ret %d\n", ret); + ath12k_free_mlo_mgmt_rx_reo_per_link_info( + &mlomem_arena_ctx->rx_reo_snapshot_info); + ath12k_free_mlo_glb_per_chip_crash_info + (&mlomem_arena_ctx->global_chip_crash_info); + mutex_unlock(&mlomem_arena_ctx->mutex_lock); + return ret; + } + + mlomem_arena_ctx->init_done = true; + + mutex_unlock(&mlomem_arena_ctx->mutex_lock); + + return 0; +} + +#define MAX_TGT_MEM_MODES 5 +static int ath12k_qmi_assign_target_mem_chunk(struct ath12k_base *ab) +{ + struct device *dev = ab->dev; + struct ath12k_hw_group *ag = ab->ag; + struct device_node *hremote_node = NULL, *mem_node, *dev_node = NULL; + struct resource res, m3_dump; + int host_ddr_sz, mlo_ddr_sz, sz, mlo_sz = 0; + int i, idx, mlo_idx, ret; + unsigned int bdf_location[MAX_TGT_MEM_MODES], + caldb_location[MAX_TGT_MEM_MODES], + caldb_size[1]; + + sz = ab->host_ddr_fixed_mem_off; + hremote_node = of_parse_phandle(dev->of_node, "memory-region", 0); + if (!hremote_node) { + ath12k_warn(ab, "qmi fail to get hremote_node\n"); + return ret; + } + + ret = of_address_to_resource(hremote_node, 0, &res); + of_node_put(hremote_node); + if (ret) { + ath12k_warn(ab, "qmi fail to get reg from hremote\n"); + return ret; + } + + mutex_lock(&ag->mutex_lock); + + if (ag->mlo_mem.init_done) + goto skip_mlo_mem_init; + + mem_node = of_find_node_by_name(NULL, "mlo_global_mem_0"); + if (!mem_node) { + ath12k_warn(ab, "qmi fail to get MLO global memory node\n"); + ret = -EINVAL; + goto out; + } + + ag->mlo_mem.rsv = of_reserved_mem_lookup(mem_node); + of_node_put(mem_node); + if (!ag->mlo_mem.rsv) { + ath12k_warn(ab, "qmi fail to get MLO memory resource node %px\n", + ag->mlo_mem.rsv); + ret = -EINVAL; + goto out; + } + + memset(ag->mlo_mem.chunk, 0, sizeof(ag->mlo_mem.chunk)); + ag->mlo_mem.init_done = true; + +skip_mlo_mem_init: + mlo_ddr_sz = ag->mlo_mem.rsv->size; + host_ddr_sz = (res.end - res.start) + 1; + + for (i = 0, idx = 0, mlo_idx = 0; i < ab->qmi.mem_seg_count; i++) { + struct target_mem_chunk *mlo_chunk; + phys_addr_t paddr; + int remain_sz; + + if (ab->qmi.target_mem[i].type == MLO_GLOBAL_MEM_REGION_TYPE) { + paddr = ag->mlo_mem.rsv->base + mlo_sz; + remain_sz = mlo_ddr_sz - mlo_sz; + } else { + paddr = res.start + sz; + remain_sz = host_ddr_sz - sz; + } + + ab->qmi.target_mem[idx].paddr = paddr; + + if (ab->qmi.target_mem[i].size > remain_sz) { + ath12k_warn(ab, "No fixed mem to assign for type %d\n", + ab->qmi.target_mem[i].type); + ret = -EINVAL; + goto out; + } + + switch (ab->qmi.target_mem[i].type) { + case HOST_DDR_REGION_TYPE: + ab->qmi.target_mem[idx].v.ioaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); + ab->qmi.target_mem[idx].size = + ab->qmi.target_mem[i].size; + ab->qmi.target_mem[idx].type = + ab->qmi.target_mem[i].type; + sz += ab->qmi.target_mem[i].size; + idx++; + break; + case CALDB_MEM_REGION_TYPE: + if (ath12k_cold_boot_cal && + ab->hw_params->cold_boot_calib) { + if (ab->hif.bus == ATH12K_BUS_AHB || + ab->hif.bus == ATH12K_BUS_HYBRID) { + if (of_property_read_u32_array(dev->of_node, + "qcom,caldb-addr", caldb_location, + ARRAY_SIZE(caldb_location))) { + ath12k_err(ab, "CALDB_MEM_REGION Not defined in device_tree\n"); + ret = -EINVAL; + goto out; + } + + if (of_property_read_u32_array(dev->of_node, + "qcom,caldb-size", caldb_size, + ARRAY_SIZE(caldb_size))) { + ath12k_err(ab, "CALDB_SIZE Not defined in device_tree\n"); + ret = -EINVAL; + goto out; + } + + ab->qmi.target_mem[idx].paddr = caldb_location[ab->hw_params->fw_mem_mode]; + ab->qmi.target_mem[i].size = caldb_size[0]; + + ab->qmi.target_mem[idx].v.ioaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); + } else { + ab->qmi.target_mem[idx].v.ioaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); + sz += ab->qmi.target_mem[i].size; + } + } else { + ab->qmi.target_mem[idx].paddr = 0; + ab->qmi.target_mem[idx].v.ioaddr = NULL; + } + + ab->qmi.target_mem[idx].size = + ab->qmi.target_mem[i].size; + ab->qmi.target_mem[idx].type = + ab->qmi.target_mem[i].type; + idx++; + break; + case PAGEABLE_MEM_REGION_TYPE: + ab->qmi.target_mem[idx].v.ioaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); + ab->qmi.target_mem[idx].size = + ab->qmi.target_mem[i].size; + ab->qmi.target_mem[idx].type = + ab->qmi.target_mem[i].type; + sz += ab->qmi.target_mem[i].size; + if (ret < 0) + ath12k_warn(ab, + "qmi fail to update BHI table %d\n", ret); + idx++; + break; + case M3_DUMP_REGION_TYPE: + if (ab->hif.bus == ATH12K_BUS_AHB) { + dev_node = of_find_node_by_name(NULL, "m3_dump"); + if (of_address_to_resource(dev_node, 0, &m3_dump)) { + ath12k_err(ab, "M3_MEM_REGION Not defined in device_tree\n"); + ret = -EINVAL; + goto out; + } else { + ab->qmi.target_mem[idx].paddr = m3_dump.start; + } + } else if (ab->hif.bus == ATH12K_BUS_HYBRID) { + if (ab->userpd_id == USERPD_1) + dev_node = of_find_node_by_name(NULL, "m3_dump_qcn6432_1"); + else if (ab->userpd_id == USERPD_2) + dev_node = of_find_node_by_name(NULL, "m3_dump_qcn6432_2"); + + if (of_address_to_resource(dev_node, 0, &m3_dump)) { + ath12k_err(ab, "M3_MEM_REGION Not defined in device_tree\n"); + ret = -EINVAL; + goto out; + } else { + ab->qmi.target_mem[idx].paddr = m3_dump.start; + } + + } else { + sz += ab->qmi.target_mem[i].size; + } + ab->qmi.target_mem[idx].v.ioaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); + ab->qmi.target_mem[idx].size = + ab->qmi.target_mem[i].size; + ab->qmi.target_mem[idx].type = + ab->qmi.target_mem[i].type; + idx++; + break; + case MLO_GLOBAL_MEM_REGION_TYPE: + mlo_chunk = &ag->mlo_mem.chunk[mlo_idx]; + if (!mlo_chunk->paddr) { + mlo_chunk->size = ab->qmi.target_mem[i].size; + mlo_chunk->type = ab->qmi.target_mem[i].type; + mlo_chunk->paddr = paddr; + mlo_chunk->v.ioaddr = ioremap(mlo_chunk->paddr, + mlo_chunk->size); + memset_io(mlo_chunk->v.ioaddr, 0, mlo_chunk->size); + } + + ab->qmi.target_mem[idx].paddr = mlo_chunk->paddr; + ab->qmi.target_mem[idx].v.ioaddr = mlo_chunk->v.ioaddr; + ab->qmi.target_mem[idx].size = mlo_chunk->size; + ab->qmi.target_mem[idx].type = mlo_chunk->type; + mlo_sz += mlo_chunk->size; + ag->mlo_mem.is_mlo_mem_avail = true; + idx++; + mlo_idx++; + break; + case BDF_MEM_REGION_TYPE: + if (of_property_read_u32_array(dev->of_node, + "qcom,bdf-addr", bdf_location, + ARRAY_SIZE(bdf_location))) { + ath12k_err(ab, "BDF_MEM_REGION Not defined in device_tree\n"); + ret = -EINVAL; + goto out; + } + ab->qmi.target_mem[idx].paddr = bdf_location[ab->hw_params->fw_mem_mode]; + ab->qmi.target_mem[idx].v.ioaddr = + ioremap(ab->qmi.target_mem[idx].paddr, + ab->qmi.target_mem[i].size); + ab->qmi.target_mem[idx].size = + ab->qmi.target_mem[i].size; + ab->qmi.target_mem[idx].type = + ab->qmi.target_mem[i].type; + idx++; + break; + default: + ath12k_warn(ab, "qmi ignore invalid mem req type %d\n", + ab->qmi.target_mem[i].type); + break; + } + + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi target mem seg idx %d i %d type %d size %d\n", + idx, i, ab->qmi.target_mem[idx - 1].type, ab->qmi.target_mem[idx - 1].size); + } + + mutex_unlock(&ag->mutex_lock); + + ab->host_ddr_fixed_mem_off = sz; + ab->qmi.mem_seg_count = idx; + + return 0; + +out: + ath12k_qmi_free_target_mem_chunk(ab); + mutex_unlock(&ag->mutex_lock); + return ret; +} + static int ath12k_qmi_request_target_cap(struct ath12k_base *ab) { struct qmi_wlanfw_cap_req_msg_v01 req; struct qmi_wlanfw_cap_resp_msg_v01 resp; struct qmi_txn txn = {}; - unsigned int board_id = ATH12K_BOARD_ID_DEFAULT; + struct device *dev = ab->dev; + unsigned int board_id; int ret = 0; - int i; + int r, i; memset(&req, 0, sizeof(req)); memset(&resp, 0, sizeof(resp)); @@ -2249,10 +4603,19 @@ ab->qmi.target.chip_family = resp.chip_info.chip_family; } - if (resp.board_info_valid) + if (!of_property_read_u32(dev->of_node, "qcom,board_id", &board_id) && + board_id != 0xFF) + ab->qmi.target.board_id = board_id; + else if (resp.board_info_valid) ab->qmi.target.board_id = resp.board_info.board_id; - else + else { + u16 ov_board_id; + + if (ab->hif.bus == ATH12K_BUS_PCI && + ath12k_pci_has_board_id_override(ab, &ov_board_id)) + board_id = ov_board_id; ab->qmi.target.board_id = board_id; + } if (resp.soc_info_valid) ab->qmi.target.soc_id = resp.soc_info.soc_id; @@ -2281,6 +4644,11 @@ } } + if (resp.rxgainlut_support_valid) + ab->rxgainlut_support = !!resp.rxgainlut_support; + + ath12k_info(ab, "rxgainlut_support %u\n", ab->rxgainlut_support); + if (resp.eeprom_caldata_read_timeout_valid) { ab->qmi.target.eeprom_caldata = resp.eeprom_caldata_read_timeout; ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi cal data supported from eeprom\n"); @@ -2295,6 +4663,10 @@ ab->qmi.target.fw_build_timestamp, ab->qmi.target.fw_build_id); + r = ath12k_core_check_dt(ab); + if (r) + ath12k_dbg(ab, ATH12K_DBG_QMI, "DT bdf variant name not set.\n"); + out: return ret; } @@ -2306,6 +4678,7 @@ struct qmi_wlanfw_bdf_download_resp_msg_v01 resp; struct qmi_txn txn = {}; const u8 *temp = data; + void __iomem *bdf_addr = NULL; int ret; u32 remaining = len; @@ -2314,6 +4687,15 @@ return -ENOMEM; memset(&resp, 0, sizeof(resp)); + if (ab->bus_params.fixed_bdf_addr) { + bdf_addr = ioremap(ab->hw_params->bdf_addr, ab->hw_params->fw.board_size); + if (!bdf_addr) { + ath12k_warn(ab, "qmi ioremap error for BDF\n"); + ret = -EIO; + goto out; + } + } + while (remaining) { req->valid = 1; req->file_id_valid = 1; @@ -2334,7 +4716,8 @@ req->end = 1; } - if (type == ATH12K_QMI_FILE_TYPE_EEPROM) { + if ((ab->bus_params.fixed_bdf_addr) || + (type == ATH12K_QMI_FILE_TYPE_EEPROM)) { req->data_valid = 0; req->end = 1; req->data_len = ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE; @@ -2342,6 +4725,13 @@ memcpy(req->data, temp, req->data_len); } + if (ab->bus_params.fixed_bdf_addr) { + if (type == ATH12K_QMI_FILE_TYPE_CALDATA) + bdf_addr += ab->hw_params->fw.cal_offset; + + memcpy_toio(bdf_addr, temp, len); + } + ret = qmi_txn_init(&ab->qmi.handle, &txn, qmi_wlanfw_bdf_download_resp_msg_v01_ei, &resp); @@ -2371,7 +4761,8 @@ goto out; } - if (type == ATH12K_QMI_FILE_TYPE_EEPROM) { + if (type == ATH12K_QMI_FILE_TYPE_EEPROM || + ab->bus_params.fixed_bdf_addr) { remaining = 0; } else { remaining -= req->data_len; @@ -2384,10 +4775,97 @@ } out: + if (ab->bus_params.fixed_bdf_addr) + iounmap(bdf_addr); kfree(req); return ret; } +static int ath12k_qmi_fw_cfg_send_sync(struct ath12k_base *ab, + const u8 *data, u32 len, + enum wlanfw_cfg_type_v01 file_type) +{ + struct wlanfw_cfg_download_req_msg_v01 *req; + struct wlanfw_cfg_download_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret = 0; + const u8 *temp = data; + unsigned int remaining = len; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + while (remaining) { + req->file_type_valid = 1; + req->file_type = file_type; + req->total_size_valid = 1; + req->total_size = remaining; + req->seg_id_valid = 1; + req->data_valid = 1; + req->end_valid = 1; + + if (remaining > QMI_WLANFW_MAX_DATA_SIZE_V01) { + req->data_len = QMI_WLANFW_MAX_DATA_SIZE_V01; + } else { + req->data_len = remaining; + req->end = 1; + } + + memcpy(req->data, temp, req->data_len); + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + wlanfw_cfg_download_resp_msg_v01_ei, + resp); + if (ret < 0) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "Failed to initialize txn for FW file download request, err: %d\n", + ret); + goto err; + } + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_CFG_DOWNLOAD_REQ_V01, + WLANFW_CFG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN, + wlanfw_cfg_download_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + ath12k_dbg(ab, ATH12K_DBG_QMI, "Failed to send FW File download request, err: %d\n", + ret); + goto err; + } + + ret = qmi_txn_wait(&txn, ATH12K_QMI_WLANFW_TIMEOUT_MS); + if (ret < 0) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "Failed to wait for response of FW File download request, err: %d\n", + ret); + goto err; + } + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "FW file download request failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -resp->resp.result; + goto err; + } + + remaining -= req->data_len; + temp += req->data_len; + req->seg_id++; + } + +err: + kfree(req); + kfree(resp); + + return ret; +} + static int ath12k_qmi_load_bdf_qmi(struct ath12k_base *ab, enum ath12k_qmi_bdf_type type) { @@ -2416,14 +4894,32 @@ break; case ATH12K_QMI_BDF_TYPE_REGDB: - ret = ath12k_core_fetch_board_data_api_1(ab, &bd, - ATH12K_REGDB_FILE_NAME); + ret = ath12k_core_fetch_regdb(ab, &bd); if (ret) { - ath12k_warn(ab, "qmi failed to load regdb bin:\n"); + ath12k_warn(ab, "qmi failed to load regdb:\n"); + goto out; + } + type = ATH12K_QMI_BDF_TYPE_REGDB; + break; + case ATH12K_QMI_BDF_TYPE_RXGAINLUT: + ret = ath12k_core_fetch_rxgainlut(ab, &bd); + if (ret < 0) { + ath12k_warn(ab, "qmi failed to load rxgainlut\n"); goto out; } break; case ATH12K_QMI_BDF_TYPE_CALIBRATION: + if (ath12k_skip_caldata) { + if (ath12k_ftm_mode) { + ath12k_warn(ab, "Skipping caldata download " + "in FTM mode\n"); + goto out; + } + ath12k_err(ab, "skip_caldata=1 module param is " + "unsupported when FTM mode is disabled.\n"); + ret = -EOPNOTSUPP; + goto out; + } if (ab->qmi.target.eeprom_caldata) { file_type = ATH12K_QMI_FILE_TYPE_EEPROM; @@ -2436,11 +4932,21 @@ snprintf(filename, sizeof(filename), "cal-%s-%s.bin", ath12k_bus_str(ab->hif.bus), dev_name(dev)); fw_entry = ath12k_core_firmware_request(ab, filename); + if (!IS_ERR(fw_entry)) goto success; - fw_entry = ath12k_core_firmware_request(ab, - ATH12K_DEFAULT_CAL_FILE); + snprintf(filename, sizeof(filename), "%s", ATH12K_DEFAULT_CAL_FILE); + + if (ab->userpd_id) { + snprintf(filename, sizeof(filename), "%s%d%s", + ATH12K_QMI_DEF_CAL_FILE_PREFIX, + ab->userpd_id, + ATH12K_QMI_DEF_CAL_FILE_SUFFIX); + } + + fw_entry = ath12k_core_firmware_request(ab, filename); + if (IS_ERR(fw_entry)) { ret = PTR_ERR(fw_entry); ath12k_warn(ab, @@ -2527,7 +5033,7 @@ { struct m3_mem_region *m3_mem = &ab->qmi.m3_mem; - if (!m3_mem->vaddr) + if (!ab->hw_params->m3_fw_support || !m3_mem->vaddr) return; dma_free_coherent(ab->dev, m3_mem->size, @@ -2546,14 +5052,18 @@ memset(&req, 0, sizeof(req)); memset(&resp, 0, sizeof(resp)); + if (ab->hw_params->m3_fw_support) { ret = ath12k_qmi_m3_load(ab); if (ret) { ath12k_err(ab, "failed to load m3 firmware: %d", ret); return ret; } - req.addr = m3_mem->paddr; req.size = m3_mem->size; + } else { + req.addr = 0; + req.size = 0; + } ret = qmi_txn_init(&ab->qmi.handle, &txn, qmi_wlanfw_m3_info_resp_msg_v01_ei, &resp); @@ -2725,6 +5235,23 @@ return ret; } +int ath12k_config_qdss(struct ath12k_base *ab) +{ + int ret; + + /* Disabling qdss trace for FTM as it causes hig evt latency in FW +*/ + if (ab->fw_mode == ATH12K_FIRMWARE_MODE_FTM) + return 0; + + ret = ath12k_qmi_send_qdss_config(ab); + if (ret < 0) + ath12k_warn(ab, + "Failed to download QDSS config to FW: %d\n", + ret); + return ret; +} + void ath12k_qmi_firmware_stop(struct ath12k_base *ab) { int ret; @@ -2756,6 +5283,162 @@ return 0; } +static int ath12k_qmi_process_coldboot_calibration(struct ath12k_base *ab) +{ + int timeout; + int ret; + + ret = ath12k_qmi_wlanfw_mode_send(ab, ATH12K_FIRMWARE_MODE_COLD_BOOT); + if (ret < 0) { + ath12k_warn(ab, "qmi failed to send wlan fw mode:%d\n", ret); + return ret; + } + + ath12k_dbg(ab, ATH12K_DBG_QMI, "Coldboot calibration wait started\n"); + + timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, + (ab->qmi.cal_done == 1), + ATH12K_COLD_BOOT_FW_RESET_DELAY); + if (timeout <= 0) { + ath12k_warn(ab, "Coldboot Calibration failed - wait ended\n"); + return 0; + } + + ath12k_dbg(ab, ATH12K_DBG_QMI, "Coldboot calibration done\n"); + + return 0; +} + +int ath12k_qmi_fwreset_from_cold_boot(struct ath12k_base *ab) +{ + int timeout; + + if (ath12k_cold_boot_cal == 0 || + ab->hw_params->cold_boot_calib == 0){ + ath12k_info(ab, "Cold boot cal is not supported/enabled\n"); + return 0; + } + + ath12k_dbg(ab, ATH12K_DBG_QMI, "wait for cold boot done\n"); + + timeout = wait_event_timeout(ab->qmi.cold_boot_waitq, + (ab->qmi.cal_done == 1), + ATH12K_COLD_BOOT_FW_RESET_DELAY); + if (timeout <= 0) { + ath12k_warn(ab, "Coldboot Calibration timed out\n"); + /*set cal_timeout to switch to mission mode on firware reset*/ + ab->qmi.cal_timeout = 1; + } + + /* reset the firmware */ + ath12k_info(ab, "power down to restart firmware in mission mode\n"); + ath12k_qmi_firmware_stop(ab); + ath12k_hif_power_down(ab); + ath12k_info(ab, "power up to restart firmware in mission mode\n"); + /* reset host fixed mem off to zero */ + ab->host_ddr_fixed_mem_off = 0; + ath12k_hif_power_up(ab); + ath12k_dbg(ab, ATH12K_DBG_QMI, "exit wait for cold boot done\n"); + return 0; +} +EXPORT_SYMBOL(ath12k_qmi_fwreset_from_cold_boot); + +int ath12k_qmi_m3_dump_upload_done_ind_send(struct ath12k_base *ab, + u32 pdev_id, int status) +{ + struct qmi_wlanfw_m3_dump_upload_done_req_msg_v01 *req; + struct qmi_wlanfw_m3_dump_upload_done_resp_msg_v01 *resp; + struct qmi_txn txn; + int ret; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + resp = kzalloc(sizeof(*resp), GFP_KERNEL); + if (!resp) { + kfree(req); + return -ENOMEM; + } + + req->pdev_id = pdev_id; + req->status = status; + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_m3_dump_upload_done_resp_msg_v01_ei, resp); + if (ret < 0) + goto out; + + ret = + qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLFW_M3_DUMP_UPLOAD_DONE_REQ_V01, + QMI_WLANFW_M3_DUMP_UPLOAD_DONE_REQ_MSG_V01_MAX_MSG_LEN, + qmi_wlanfw_m3_dump_upload_done_req_msg_v01_ei, req); + if (ret < 0) { + qmi_txn_cancel(&txn); + ath12k_warn(ab, "Failed to send M3 dump upload done request, err %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + + if (resp->resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "qmi M3 upload done req failed, result: %d, err: %d\n", + resp->resp.result, resp->resp.error); + ret = -EINVAL; + goto out; + } + ath12k_info(ab, "qmi m3 dump uploaded\n"); + +out: + kfree(req); + kfree(resp); + return ret; +} + +static void ath12k_qmi_event_m3_dump_upload_req(struct ath12k_qmi *qmi, + void *data) +{ + struct ath12k_base *ab = qmi->ab; + struct ath12k_qmi_m3_dump_upload_req_data *event_data = data; + + ath12k_coredump_m3_dump(ab, event_data); +} + +static void ath12k_qmi_qdss_mem_free(struct ath12k_qmi *qmi) +{ + struct ath12k_base *ab = qmi->ab; + int i; + + for (i = 0; i < ab->qmi.qdss_mem_seg_len; i++) { + if (ab->qmi.qdss_mem[i].v.ioaddr) { + iounmap(ab->qmi.qdss_mem[i].v.ioaddr); + ab->qmi.qdss_mem[i].v.ioaddr = NULL; + } + } +} + +static void ath12k_qmi_event_qdss_trace_save_hdlr(struct ath12k_qmi *qmi, + void *data) +{ + struct ath12k_qmi_event_qdss_trace_save_data *event_data = data; + struct ath12k_base *ab = qmi->ab; + + if (!ab->qmi.qdss_mem_seg_len) { + ath12k_warn(ab, "Memory for QDSS trace is not available\n"); + return; + } + + ath12k_coredump_qdss_dump(ab, event_data); + + ath12k_qmi_qdss_mem_free(qmi); + ab->qmi.qdss_mem_seg_len = 0; + ab->is_qdss_tracing = false; +} + static int ath12k_qmi_driver_event_post(struct ath12k_qmi *qmi, enum ath12k_qmi_event_type type, @@ -2779,9 +5462,75 @@ return 0; } +void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab) +{ + struct ath12k_qmi *qmi = &ab->qmi; + bool block; + + spin_lock(&qmi->event_lock); + + block = ath12k_qmi_get_event_block(qmi); + if (block) + ath12k_qmi_set_event_block(qmi, false); + + spin_unlock(&qmi->event_lock); + + ath12k_dbg(ab, ATH12K_DBG_QMI, "Trigger host cap for chip id %d\n", + ab->chip_id); + + ath12k_qmi_driver_event_post(qmi, ATH12K_QMI_EVENT_HOST_CAP, NULL); +} + +static bool ath12k_qmi_hw_group_host_cap_ready(struct ath12k_hw_group *ag) +{ + struct ath12k_base *ab; + int i; + + lockdep_assert_held(&ag->mutex_lock); + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + if (!(ab && ab->qmi.num_radios != ATH12K_QMI_INVALID_RADIO)) + return false; + } + + return true; +} + +static struct ath12k_base * +ath12k_qmi_hw_group_find_blocked_chip(struct ath12k_hw_group *ag) +{ + struct ath12k_base *ab; + struct ath12k_qmi *qmi; + bool block; + int i; + + lockdep_assert_held(&ag->mutex_lock); + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + if (!ab) + continue; + + qmi = &ab->qmi; + + spin_lock(&qmi->event_lock); + block = ath12k_qmi_get_event_block(qmi); + spin_unlock(&qmi->event_lock); + + if (block) + return ab; + } + + return NULL; +} + static int ath12k_qmi_event_server_arrive(struct ath12k_qmi *qmi) { - struct ath12k_base *ab = qmi->ab; + struct ath12k_base *ab = qmi->ab, *block_ab; + struct ath12k_hw_group *ag = ab->ag; + bool host_cap_ready; int ret; ret = ath12k_qmi_fw_ind_register_send(ab); @@ -2790,11 +5539,72 @@ return ret; } + ath12k_qmi_phy_cap_send(ab); + if (ath12k_cold_boot_cal && ab->qmi.cal_done == 0 && + ab->hw_params->cold_boot_calib && + ab->qmi.cal_timeout == 0) { + /* Coldboot calibration mode */ + ath12k_qmi_trigger_host_cap(ab); + } else { + spin_lock(&qmi->event_lock); + ath12k_qmi_set_event_block(&ab->qmi, true); + spin_unlock(&qmi->event_lock); + + mutex_lock(&ag->mutex_lock); + host_cap_ready = ath12k_qmi_hw_group_host_cap_ready(ag); + if (host_cap_ready) { + block_ab = ath12k_qmi_hw_group_find_blocked_chip(ag); + if (block_ab) + ath12k_qmi_trigger_host_cap(block_ab); + } + mutex_unlock(&ag->mutex_lock); + } + + return ret; +} + +static int ath12k_qmi_fw_cfg(struct ath12k_base *ab) +{ + struct ath12k_board_data bd; + int ret; + + ret = ath12k_core_fetch_fw_cfg(ab, &bd); + if (ret < 0) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi failed to fetch FW CFG file:%d\n", ret); + goto out; + } + ret = ath12k_qmi_fw_cfg_send_sync(ab, bd.data, + bd.len, WLANFW_CFG_FILE_V01); + if (ret < 0) + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi failed to load FW CFG file\n"); + +out: + ath12k_core_free_bdf(ab, &bd); + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi FW CFG download sequence completed, ret: %d\n", + ret); + + return ret; +} + +static int ath12k_qmi_event_host_cap(struct ath12k_qmi *qmi) +{ + struct ath12k_base *ab = qmi->ab; + int ret; + ret = ath12k_qmi_host_cap_send(ab); if (ret < 0) { + clear_bit(ATH12K_FLAG_QMI_HOST_CAP_SENT, &ab->dev_flags); ath12k_warn(ab, "qmi failed to send host cap QMI:%d\n", ret); return ret; } + set_bit(ATH12K_FLAG_QMI_HOST_CAP_SENT, &ab->dev_flags); + + if (!ab->fw_cfg_support) { + ath12k_dbg(ab, ATH12K_DBG_QMI, "FW CFG file is not supported\n"); + return 0; + } + + ret = ath12k_qmi_fw_cfg(ab); return ret; } @@ -2813,6 +5623,345 @@ return ret; } +int ath12k_send_qdss_trace_mode_req(struct ath12k_base *ab, + enum qmi_wlanfw_qdss_trace_mode_enum_v01 mode) +{ + int ret; + struct qmi_txn txn; + struct qmi_wlanfw_qdss_trace_mode_req_msg_v01 req = {}; + struct qmi_wlanfw_qdss_trace_mode_resp_msg_v01 resp = {}; + + req.mode_valid = 1; + req.mode = mode; + req.option_valid = 1; + req.option = mode == QMI_WLANFW_QDSS_TRACE_OFF_V01 ? + QMI_WLANFW_QDSS_STOP_ALL_TRACE : 0; + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_qdss_trace_mode_resp_msg_v01_ei, &resp); + if (ret < 0) + return ret; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_QDSS_TRACE_MODE_REQ_V01, + QMI_WLANFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_LEN, + qmi_wlanfw_qdss_trace_mode_req_msg_v01_ei, &req); + if (ret < 0) { + ath12k_warn(ab, "Failed to send QDSS trace mode request,err = %d\n", ret); + qmi_txn_cancel(&txn); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) + goto out; + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "QDSS trace mode request failed, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } +out: + return ret; +} + +int ath12k_qmi_pci_alloc_qdss_mem(struct ath12k_qmi *qmi) +{ + struct ath12k_base *ab = qmi->ab; + struct device *dev = ab->dev; + struct resource res; + int ret; + + if (ab->qmi.qdss_mem_seg_len > 1) { + ath12k_warn(ab, "%s: FW requests %d segments, max allowed is 1\n", + __func__, ab->qmi.qdss_mem_seg_len); + return -EINVAL; + } + + switch (ab->qmi.qdss_mem[0].type) { + case QDSS_ETR_MEM_REGION_TYPE: + if (ab->qmi.qdss_mem[0].size > QMI_Q6_QDSS_ETR_SIZE_QCN9274) { + ath12k_warn(ab, "%s: FW requests more memory 0x%x\n", + __func__, ab->qmi.qdss_mem[0].size); + return -ENOMEM; + } + + ab->hremote_node = of_parse_phandle(dev->of_node, "memory-region", 0); + if (!ab->hremote_node) { + ath12k_warn(ab, "qmi fail to get hremote_node for pci device\n"); + return ret; + } + + ret = of_address_to_resource(ab->hremote_node, 0, &res); + of_node_put(ab->hremote_node); + if (ret) { + ath12k_warn(ab, "qmi fail to get reg from hremote\n"); + return ret; + } + + if ((ab->host_ddr_fixed_mem_off + ab->qmi.qdss_mem[0].size) > + ((res.end - res.start) + 1)) { + ath12k_warn(ab, + "No Fixed mem to allocate for QDSS_ETR_MEM_REGION_TYPE"); + return -EINVAL; + } + + ab->qmi.qdss_mem[0].paddr = (phys_addr_t)res.start + ab->host_ddr_fixed_mem_off; + ab->qmi.qdss_mem[0].v.ioaddr = + ioremap(ab->qmi.qdss_mem[0].paddr, + ab->qmi.qdss_mem[0].size); + if (!ab->qmi.qdss_mem[0].v.ioaddr) { + ath12k_warn(ab, "WARNING etr-addr remap failed\n"); + return -ENOMEM; + } + ab->host_ddr_fixed_mem_off += ab->qmi.qdss_mem[0].size; + break; + default: + ath12k_warn(ab, "qmi ignore invalid qdss mem req type %d\n", + ab->qmi.qdss_mem[0].type); + return -EINVAL; + } + + return 0; +} + +static +struct device_node *ath12k_get_etr_dev_node(struct ath12k_base *ab) +{ + struct device_node *dev_node = NULL; + + if (ab->userpd_id) { + if (ab->userpd_id == USERPD_1) + dev_node = of_find_node_by_name(NULL, + "q6_qcn6432_etr_1"); + else if (ab->userpd_id == USERPD_2) + dev_node = of_find_node_by_name(NULL, + "q6_qcn6432_etr_2"); + } else { + dev_node = of_find_node_by_name(NULL, "q6_etr_dump"); + } + + return dev_node; +} + +int ath12k_qmi_qdss_mem_alloc(struct ath12k_qmi *qmi) +{ + int ret, i; + struct ath12k_base *ab = qmi->ab; + struct device_node *dev_node = NULL; + struct resource q6_etr; + + switch (ab->hif.bus) { + case ATH12K_BUS_AHB: + case ATH12K_BUS_HYBRID: + dev_node = ath12k_get_etr_dev_node(ab); + if (!dev_node) { + ath12k_err(ab, "No q6_etr_dump available in dts\n"); + return -ENODEV; + } + ret = of_address_to_resource(dev_node, 0, &q6_etr); + of_node_put(dev_node); + if (ret) { + ath12k_err(ab, "Failed to get resource for q6_etr_dump\n"); + return ret; + } + for (i = 0; i < ab->qmi.qdss_mem_seg_len; i++) { + ab->qmi.qdss_mem[i].paddr = q6_etr.start; + ab->qmi.qdss_mem[i].size = resource_size(&q6_etr); + ab->qmi.qdss_mem[i].type = QDSS_ETR_MEM_REGION_TYPE; + ab->qmi.qdss_mem[i].v.ioaddr = + ioremap(ab->qmi.qdss_mem[i].paddr, + ab->qmi.qdss_mem[i].size); + if (!ab->qmi.qdss_mem[i].v.ioaddr) { + ath12k_err(ab, "Error: etr-addr remap failed\n"); + return -ENOMEM; + } + ath12k_dbg(ab, ATH12K_DBG_QMI, + "QDSS mem addr pa 0x%x va 0x%p, size 0x%x", + (unsigned int)ab->qmi.qdss_mem[i].paddr, + ab->qmi.qdss_mem[i].v.ioaddr, + (unsigned int)ab->qmi.qdss_mem[i].size); + } + break; + case ATH12K_BUS_PCI: + ret = ath12k_qmi_pci_alloc_qdss_mem(qmi); + break; + default: + ath12k_warn(ab, "invalid bus type: %d", ab->hif.bus); + ret = -EINVAL; + break; + } + return ret; +} + +int ath12k_qmi_qdss_trace_mem_info_send_sync(struct ath12k_base *ab) +{ + struct qmi_wlanfw_respond_mem_req_msg_v01 *req; + struct qmi_wlanfw_respond_mem_resp_msg_v01 resp = {}; + struct qmi_txn txn; + int ret, i; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + req->mem_seg_len = ab->qmi.qdss_mem_seg_len; + + for (i = 0; i < req->mem_seg_len ; i++) { + req->mem_seg[i].addr = ab->qmi.qdss_mem[i].paddr; + req->mem_seg[i].size = ab->qmi.qdss_mem[i].size; + req->mem_seg[i].type = ab->qmi.qdss_mem[i].type; + } + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_respond_mem_resp_msg_v01_ei, &resp); + + if (ret < 0) { + ath12k_warn(ab, "Fail to initialize txn for QDSS trace mem request: err %d\n", + ret); + goto out; + } + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01, + QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN, + qmi_wlanfw_respond_mem_req_msg_v01_ei, req); + + if (ret < 0) { + ath12k_warn(ab, "qmi failed to respond memory request, err = %d\n", + ret); + qmi_txn_cancel(&txn); + goto out; + } + + ret = qmi_txn_wait(&txn, + msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) { + ath12k_warn(ab, "qmi failed memory request, err = %d\n", ret); + goto out; + } + + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "Respond mem req failed, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } +out: + kfree(req); + return ret; +} + +static void ath12k_qmi_event_qdss_trace_req_mem_hdlr(struct ath12k_qmi *qmi) +{ + int ret; + struct ath12k_base *ab = qmi->ab; + + ret = ath12k_qmi_qdss_mem_alloc(qmi); + if (ret < 0) { + ath12k_err(ab, "failed to allocate memory for qdss:%d\n", ret); + return; + } + + ret = ath12k_qmi_qdss_trace_mem_info_send_sync(ab); + if (ret < 0) { + ath12k_warn(ab, + "qdss trace mem info send sync failed:%d\n", ret); + ath12k_qmi_qdss_mem_free(qmi); + return; + } + /* After qdss_trace_mem_info(QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01), + * the firmware will take one second at max + * for its configuration. We shouldn't send qdss_trace request + * before that. + */ + msleep(1000); + ret = ath12k_send_qdss_trace_mode_req(ab, QMI_WLANFW_QDSS_TRACE_ON_V01); + if (ret < 0) { + ath12k_warn(ab, "Failed to enable QDSS trace: %d\n", ret); + ath12k_qmi_qdss_mem_free(qmi); + return; + } + ab->is_qdss_tracing = true; + ath12k_dbg(ab, ATH12K_DBG_QMI, "QDSS configuration is completed and trace started\n"); +} + +static int ath12k_qmi_request_device_info(struct ath12k_base *ab) +{ + struct qmi_wlanfw_device_info_req_msg_v01 req; + struct qmi_wlanfw_device_info_resp_msg_v01 resp; + struct qmi_txn txn = {}; + void *bar_addr_va = NULL; + int ret = 0; + + /*device info message only supported for internal-PCI devices */ + if (ab->hw_rev != ATH12K_HW_QCN6432_HW10) + return 0; + + memset(&req, 0, sizeof(req)); + memset(&resp, 0, sizeof(resp)); + + ret = qmi_txn_init(&ab->qmi.handle, &txn, + qmi_wlanfw_device_info_resp_msg_v01_ei, &resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLANFW_DEVICE_INFO_REQ_V01, + QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01, + qmi_wlanfw_device_info_req_msg_v01_ei, &req); + if (ret < 0) { + ath12k_warn(ab, "qmi failed to send target device info request, err = %d\n", + ret); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) { + ath12k_warn(ab, "qmi failed target device info request %d\n", ret); + goto out; + } + + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "qmi device info req failed, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } + + if (!resp.bar_addr_valid || !resp.bar_size_valid) { + ath12k_warn(ab, "qmi device info response invalid, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } + if (!resp.bar_addr || + resp.bar_size != QCN6432_DEVICE_BAR_SIZE) { + ath12k_warn(ab, "qmi device info invalid addr and size, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + goto out; + } + + bar_addr_va = ioremap(resp.bar_addr, resp.bar_size); + if (!bar_addr_va) { + ath12k_warn(ab, "qmi device info ioremap failed\n"); + ab->mem_len = 0; + ret = -EIO; + goto out; + } + + ab->mem = bar_addr_va; + ab->mem_len = resp.bar_size; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "Device BAR Info pa: 0x%llx, va: 0x%p, size: 0x%lx\n", + resp.bar_addr, ab->mem, ab->mem_len); + + ath12k_hif_config_static_window(ab); + return 0; +out: + return ret; +} + static int ath12k_qmi_event_load_bdf(struct ath12k_qmi *qmi) { struct ath12k_base *ab = qmi->ab; @@ -2824,11 +5973,19 @@ return ret; } + ret = ath12k_qmi_request_device_info(ab); + if (ret < 0) { + ath12k_warn(ab, "qmi failed to req device info:%d\n", ret); + return ret; + } + + if (!ab->bus_params.fixed_bdf_addr) { ret = ath12k_qmi_load_bdf_qmi(ab, ATH12K_QMI_BDF_TYPE_REGDB); if (ret < 0) { ath12k_warn(ab, "qmi failed to load regdb file:%d\n", ret); return ret; } + } ret = ath12k_qmi_load_bdf_qmi(ab, ATH12K_QMI_BDF_TYPE_ELF); if (ret < 0) { @@ -2836,6 +5993,12 @@ return ret; } + if (ab->rxgainlut_support) { + ret = ath12k_qmi_load_bdf_qmi(ab, ATH12K_QMI_BDF_TYPE_RXGAINLUT); + if (ret < 0) + ath12k_warn(ab, "qmi failed to load rxgainlut: %d\n", ret); + } + if (ab->hw_params->download_calib) { ret = ath12k_qmi_load_bdf_qmi(ab, ATH12K_QMI_BDF_TYPE_CALIBRATION); if (ret < 0) @@ -2873,16 +6036,26 @@ for (i = 0; i < qmi->mem_seg_count ; i++) { ab->qmi.target_mem[i].type = msg->mem_seg[i].type; ab->qmi.target_mem[i].size = msg->mem_seg[i].size; + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi mem seg type %d size %d\n", msg->mem_seg[i].type, msg->mem_seg[i].size); } + if (ab->bus_params.fixed_mem_region) { + ret = ath12k_qmi_assign_target_mem_chunk(ab); + if (ret) { + ath12k_warn(ab, "qmi failed to assign target memory: %d\n", + ret); + return; + } + } else { ret = ath12k_qmi_alloc_target_mem_chunk(ab); if (ret) { ath12k_warn(ab, "qmi failed to alloc target memory: %d\n", ret); return; } + } ath12k_qmi_driver_event_post(qmi, ATH12K_QMI_EVENT_REQUEST_MEM, NULL); } @@ -2911,6 +6084,171 @@ ath12k_qmi_driver_event_post(qmi, ATH12K_QMI_EVENT_FW_READY, NULL); } +static void ath12k_qmi_msg_cold_boot_cal_done_cb(struct qmi_handle *qmi_hdl, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *decoded) +{ + struct ath12k_qmi *qmi = container_of(qmi_hdl, + struct ath12k_qmi, handle); + struct ath12k_base *ab = qmi->ab; + + ab->qmi.cal_done = 1; + wake_up(&ab->qmi.cold_boot_waitq); + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi cold boot calibration done\n"); +} + +static void ath12k_qmi_m3_dump_upload_req_ind_cb(struct qmi_handle *qmi_hdl, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct ath12k_qmi *qmi = container_of(qmi_hdl, struct ath12k_qmi, handle); + struct ath12k_base *ab = qmi->ab; + const struct qmi_wlanfw_m3_dump_upload_req_ind_msg_v01 *msg = data; + struct ath12k_qmi_m3_dump_upload_req_data *event_data; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi m3 dump memory request\n"); + + event_data = kzalloc(sizeof(*event_data), GFP_KERNEL); + if (!event_data) + return; + + event_data->pdev_id = msg->pdev_id; + event_data->addr = msg->addr; + event_data->size = msg->size; + + ath12k_qmi_driver_event_post(qmi, ATH12K_QMI_EVENT_M3_DUMP_UPLOAD_REQ, + event_data); +} + +static void ath12k_wlfw_qdss_trace_req_mem_ind_cb(struct qmi_handle *qmi_hdl, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct ath12k_qmi *qmi = container_of(qmi_hdl, + struct ath12k_qmi, + handle); + struct ath12k_base *ab = qmi->ab; + const struct qmi_wlanfw_request_mem_ind_msg_v01 *msg = data; + int i; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "qdss trace request memory from firmware\n"); + ab->qmi.qdss_mem_seg_len = msg->mem_seg_len; + + if (msg->mem_seg_len > 1) { + ath12k_warn(ab, "%s: FW requests %d segments, overwriting it with 1", + __func__, msg->mem_seg_len); + ab->qmi.qdss_mem_seg_len = 1; + } + + for (i = 0; i < ab->qmi.qdss_mem_seg_len; i++) { + ab->qmi.qdss_mem[i].type = msg->mem_seg[i].type; + ab->qmi.qdss_mem[i].size = msg->mem_seg[i].size; + ath12k_dbg(ab, ATH12K_DBG_QMI, "qmi mem seg type %d size %d\n", + msg->mem_seg[i].type, msg->mem_seg[i].size); + } + + ath12k_qmi_driver_event_post(qmi, + ATH12K_QMI_EVENT_QDSS_TRACE_REQ_MEM, + NULL); +} + +static void ath12k_wlfw_qdss_trace_save_ind_cb(struct qmi_handle *qmi_hdl, + struct sockaddr_qrtr *sq, + struct qmi_txn *txn, + const void *data) +{ + struct ath12k_qmi *qmi = container_of(qmi_hdl, + struct ath12k_qmi, + handle); + struct ath12k_base *ab = qmi->ab; + const struct qmi_wlanfw_qdss_trace_save_ind_msg_v01 *ind_msg = data; + struct ath12k_qmi_event_qdss_trace_save_data *event_data; + int i; + + if (ind_msg->source == 1) + return; + + ath12k_dbg(ab, ATH12K_DBG_QMI, "Received qdss trace save indication\n"); + event_data = kzalloc(sizeof(*event_data), GFP_KERNEL); + + if (!event_data) + return; + + if (ind_msg->mem_seg_valid) { + if (ind_msg->mem_seg_len > QDSS_TRACE_SEG_LEN_MAX) { + ath12k_err(ab, "Invalid seg len %u\n", + ind_msg->mem_seg_len); + goto free_event_data; + } + + event_data->mem_seg_len = ind_msg->mem_seg_len; + for (i = 0; i < ind_msg->mem_seg_len; i++) { + event_data->mem_seg[i].addr = ind_msg->mem_seg[i].addr; + event_data->mem_seg[i].size = ind_msg->mem_seg[i].size; + } + } + + event_data->total_size = ind_msg->total_size; + ath12k_qmi_driver_event_post(qmi, ATH12K_QMI_EVENT_QDSS_TRACE_SAVE, + event_data); + return; + +free_event_data: + kfree(event_data); +} + +int ath12k_enable_fwlog(struct ath12k_base *ab) +{ + struct wlfw_ini_req_msg_v01 *req; + struct wlfw_ini_resp_msg_v01 resp = {}; + struct qmi_txn txn = {}; + int ret = 0; + + if (!ab->hw_params->en_fwlog) + return 0; + + req = kzalloc(sizeof(*req), GFP_KERNEL); + if (!req) + return -ENOMEM; + + req->enablefwlog_valid = 1; + req->enablefwlog = 1; + + ret = qmi_txn_init(&ab->qmi.handle, &txn, wlfw_ini_resp_msg_v01_ei, &resp); + if (ret < 0) + goto out; + + ret = qmi_send_request(&ab->qmi.handle, NULL, &txn, + QMI_WLFW_INI_REQ_V01, + WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN, + wlfw_ini_req_msg_v01_ei, req); + + if (ret < 0) { + ath12k_warn(ab, "Failed to send init request for enabling fwlog = %d\n", + ret); + qmi_txn_cancel(&txn); + goto out; + } + + ret = qmi_txn_wait(&txn, msecs_to_jiffies(ATH12K_QMI_WLANFW_TIMEOUT_MS)); + if (ret < 0) { + ath12k_warn(ab, "fwlog enable wait for resp failed: %d\n", ret); + goto out; + } + + if (resp.resp.result != QMI_RESULT_SUCCESS_V01) { + ath12k_warn(ab, "fwlog enable request failed, result: %d, err: %d\n", + resp.resp.result, resp.resp.error); + ret = -EINVAL; + } +out: + kfree(req); + return ret; +} + static const struct qmi_msg_handler ath12k_qmi_msg_handlers[] = { { .type = QMI_INDICATION, @@ -2933,6 +6271,48 @@ .decoded_size = sizeof(struct qmi_wlanfw_fw_ready_ind_msg_v01), .fn = ath12k_qmi_msg_fw_ready_cb, }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01, + .ei = qmi_wlanfw_cold_boot_cal_done_ind_msg_v01_ei, + .decoded_size = + sizeof(struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01), + .fn = ath12k_qmi_msg_cold_boot_cal_done_cb, + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01, + .ei = qmi_wlanfw_cold_boot_cal_done_ind_msg_v01_ei, + .decoded_size = + sizeof(struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01), + .fn = ath12k_qmi_msg_cold_boot_cal_done_cb, + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_M3_DUMP_UPLOAD_REQ_IND_V01, + .ei = qmi_wlanfw_m3_dump_upload_req_ind_msg_v01_ei, + .decoded_size = + sizeof(struct qmi_wlanfw_m3_dump_upload_req_ind_msg_v01), + .fn = ath12k_qmi_m3_dump_upload_req_ind_cb, + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01, + .ei = qmi_wlanfw_request_mem_ind_msg_v01_ei, + .decoded_size = + sizeof(struct qmi_wlanfw_request_mem_ind_msg_v01), + .fn = ath12k_wlfw_qdss_trace_req_mem_ind_cb, + }, + { + .type = QMI_INDICATION, + .msg_id = QMI_WLFW_QDSS_TRACE_SAVE_IND_V01, + .ei = qmi_wlanfw_qdss_trace_save_ind_msg_v01_ei, + .decoded_size = + sizeof(struct qmi_wlanfw_qdss_trace_save_ind_msg_v01), + .fn = ath12k_wlfw_qdss_trace_save_ind_cb, + }, + /* (Additions here) */ + { /* terminator entry */ } }; static int ath12k_qmi_ops_new_server(struct qmi_handle *qmi_hdl, @@ -2975,6 +6355,23 @@ .del_server = ath12k_qmi_ops_del_server, }; +static int ath12k_wait_for_gic_msi(struct ath12k_base *ab) +{ + int timeout; + + if (ab->hw_rev != ATH12K_HW_QCN6432_HW10) + return 0; + + timeout = wait_event_timeout(ab->ipci.gic_msi_waitq, + (ab->ipci.gic_enabled == 1), + ATH12K_RCV_GIC_MSI_HDLR_DELAY); + if (timeout <= 0) { + ath12k_warn(ab, "Receive gic msi handler timed out\n"); + return -ETIMEDOUT; + } + return 0; +} + static void ath12k_qmi_driver_event_work(struct work_struct *work) { struct ath12k_qmi *qmi = container_of(work, struct ath12k_qmi, @@ -2984,6 +6381,7 @@ int ret; spin_lock(&qmi->event_lock); + while (!list_empty(&qmi->event_list)) { event = list_first_entry(&qmi->event_list, struct ath12k_qmi_driver_event, list); @@ -3001,7 +6399,7 @@ break; case ATH12K_QMI_EVENT_SERVER_EXIT: set_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); - set_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags); + clear_bit(ATH12K_FLAG_WMI_INIT_DONE, &ab->dev_flags); break; case ATH12K_QMI_EVENT_REQUEST_MEM: ret = ath12k_qmi_event_mem_request(qmi); @@ -3015,19 +6413,53 @@ break; case ATH12K_QMI_EVENT_FW_READY: clear_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags); - if (test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags)) { + if (test_bit(ATH12K_FLAG_QMI_FW_READY_COMPLETE, + &ab->dev_flags)) { ath12k_hal_dump_srng_stats(ab); queue_work(ab->workqueue, &ab->restart_work); break; } + if (ath12k_cold_boot_cal && ab->qmi.cal_done == 0 && + ab->hw_params->cold_boot_calib) { + ath12k_qmi_process_coldboot_calibration(ab); + } else { clear_bit(ATH12K_FLAG_CRASH_FLUSH, &ab->dev_flags); clear_bit(ATH12K_FLAG_RECOVERY, &ab->dev_flags); - ath12k_core_qmi_firmware_ready(ab); - set_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags); + ret = ath12k_wait_for_gic_msi(ab); + if (ret) { + ath12k_warn(ab, "failed to get qgic handler for dev %d ret: %d\n", + ab->hw_rev, ret); + break; + } + ret = ath12k_core_qmi_firmware_ready(ab); + if (ret) { + ath12k_warn(ab, "failed to init after firmware ready: %d\n", ret); + set_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags); + break; + } + set_bit(ATH12K_FLAG_QMI_FW_READY_COMPLETE, + &ab->dev_flags); + } break; + case ATH12K_QMI_EVENT_QDSS_TRACE_REQ_MEM: + ath12k_qmi_event_qdss_trace_req_mem_hdlr(qmi); + break; + case ATH12K_QMI_EVENT_QDSS_TRACE_SAVE: + ath12k_qmi_event_qdss_trace_save_hdlr(qmi, event->data); + break; + case ATH12K_QMI_EVENT_COLD_BOOT_CAL_DONE: + break; + case ATH12K_QMI_EVENT_M3_DUMP_UPLOAD_REQ: + ath12k_qmi_event_m3_dump_upload_req(qmi, event->data); + break; + case ATH12K_QMI_EVENT_HOST_CAP: + ret = ath12k_qmi_event_host_cap(qmi); + if (ret < 0) + set_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags); + break; default: ath12k_warn(ab, "invalid event type: %d", event->type); break; @@ -3048,7 +6480,7 @@ memset(&ab->qmi.target_mem, 0, sizeof(struct target_mem_chunk)); ab->qmi.ab = ab; - ab->qmi.target_mem_mode = ATH12K_QMI_TARGET_MEM_MODE_DEFAULT; + ab->qmi.target_mem_mode = ab->hw_params->fw_mem_mode; ret = qmi_handle_init(&ab->qmi.handle, ATH12K_QMI_RESP_LEN_MAX, &ath12k_qmi_ops, ath12k_qmi_msg_handlers); if (ret < 0) { @@ -3056,8 +6488,7 @@ return ret; } - ab->qmi.event_wq = alloc_workqueue("ath12k_qmi_driver_event", - WQ_UNBOUND, 1); + ab->qmi.event_wq = alloc_ordered_workqueue("ath12k_qmi_driver_event", 0); if (!ab->qmi.event_wq) { ath12k_err(ab, "failed to allocate workqueue\n"); return -EFAULT; diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/qmi.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/qmi.h --- linux-6.4/drivers/net/wireless/ath/ath12k/qmi.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/qmi.h 2024-03-18 14:40:14.859741552 +0100 @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH12K_QMI_H @@ -15,33 +15,61 @@ #define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE 64 #define ATH12K_QMI_CALDB_ADDRESS 0x4BA00000 #define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 -#define ATH12K_QMI_WLFW_NODE_ID_BASE 0x07 #define ATH12K_QMI_WLFW_SERVICE_ID_V01 0x45 #define ATH12K_QMI_WLFW_SERVICE_VERS_V01 0x01 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1 #define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274 0x07 +#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332 0x2 +#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN6432 0x60 #define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 #define ATH12K_QMI_RESP_LEN_MAX 8192 #define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 -#define ATH12K_QMI_CALDB_SIZE 0x480000 +#define ATH12K_QMI_CALDB_SIZE 0x800000 #define ATH12K_QMI_BDF_EXT_STR_LENGTH 0x20 #define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 #define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4 #define ATH12K_QMI_DEVMEM_CMEM_INDEX 0 +#define ATH12K_QMI_MAX_QDSS_CONFIG_FILE_NAME_SIZE 64 +#define ATH12K_QMI_DEFAULT_QDSS_CONFIG_FILE_NAME "qdss_trace_config.bin" +#define ATH12K_QMI_M3_DUMP_SIZE 0x100000 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 +#define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x0021 #define QMI_WLFW_FW_READY_IND_V01 0x0038 +#define QMI_WLFW_QDSS_TRACE_REQ_MEM_IND_V01 0x003F +#define QMI_Q6_QDSS_ETR_SIZE_QCN9274 0x100000 +#define QMI_WLFW_QDSS_TRACE_SAVE_IND_V01 0x0041 +#define QMI_Q6_QDSS_ETR_OFFSET_QCN9274 0x2500000 +#define QMI_WLFW_M3_DUMP_UPLOAD_REQ_IND_V01 0x004D +#define QMI_WLFW_M3_DUMP_UPLOAD_DONE_REQ_V01 0x004E #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 #define ATH12K_FIRMWARE_MODE_OFF 4 -#define ATH12K_QMI_TARGET_MEM_MODE_DEFAULT 0 +#define ATH12K_COLD_BOOT_FW_RESET_DELAY (60 * HZ) #define ATH12K_BOARD_ID_DEFAULT 0xFF +#define ATH12K_QMI_INVALID_RADIO 0xFF +#define QCN6432_DEVICE_BAR_SIZE 0x200000 +#define ATH12K_RCV_GIC_MSI_HDLR_DELAY (3 * HZ) + +enum ath12k_target_mem_mode { + ATH12K_QMI_TARGET_MEM_MODE_DEFAULT = 0, + ATH12K_QMI_TARGET_MEM_MODE_512M, +}; + +/* userpd_id in multi pd arch */ +enum userpd_id { + USERPD_0 = 0, + USERPD_1, + USERPD_2, +}; + struct ath12k_base; +struct ath12k_host_mlo_glb_rx_reo_snapshot_info; enum ath12k_qmi_file_type { ATH12K_QMI_FILE_TYPE_BDF_GOLDEN = 0, @@ -55,6 +83,7 @@ ATH12K_QMI_BDF_TYPE_ELF = 1, ATH12K_QMI_BDF_TYPE_REGDB = 4, ATH12K_QMI_BDF_TYPE_CALIBRATION = 5, + ATH12K_QMI_BDF_TYPE_RXGAINLUT = 7, }; enum ath12k_qmi_event_type { @@ -63,12 +92,18 @@ ATH12K_QMI_EVENT_REQUEST_MEM, ATH12K_QMI_EVENT_FW_MEM_READY, ATH12K_QMI_EVENT_FW_READY, + ATH12K_QMI_EVENT_COLD_BOOT_CAL_START, + ATH12K_QMI_EVENT_COLD_BOOT_CAL_DONE, ATH12K_QMI_EVENT_REGISTER_DRIVER, ATH12K_QMI_EVENT_UNREGISTER_DRIVER, ATH12K_QMI_EVENT_RECOVERY, ATH12K_QMI_EVENT_FORCE_FW_ASSERT, ATH12K_QMI_EVENT_POWER_UP, ATH12K_QMI_EVENT_POWER_DOWN, + ATH12K_QMI_EVENT_QDSS_TRACE_REQ_MEM = 15, + ATH12K_QMI_EVENT_QDSS_TRACE_SAVE, + ATH12K_QMI_EVENT_M3_DUMP_UPLOAD_REQ = 18, + ATH12K_QMI_EVENT_HOST_CAP, ATH12K_QMI_EVENT_MAX, }; @@ -78,6 +113,13 @@ void *data; }; +struct ath12k_qmi_m3_dump_data { + u32 pdev_id; + u32 size; + u64 timestamp; + char *addr; +}; + struct ath12k_qmi_ce_cfg { const struct ce_pipe_config *tgt_ce; int tgt_ce_len; @@ -138,22 +180,90 @@ struct ath12k_qmi_ce_cfg ce_cfg; struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; u32 mem_seg_count; + struct target_mem_chunk qdss_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; + u32 qdss_mem_seg_len; u32 target_mem_mode; bool target_mem_delayed; u8 cal_done; + u8 cal_timeout; + bool block_event; /* protect by event spinlock */ + u8 num_radios; struct target_info target; struct m3_mem_region m3_mem; unsigned int service_ins_id; + wait_queue_head_t cold_boot_waitq; struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; }; -#define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 +struct ath12k_qmi_m3_dump_upload_req_data { + u32 pdev_id; + u64 addr; + u64 size; +}; + +#define QMI_WLANFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6167 +#define QMI_WLANFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 +#define QMI_WLANFW_QDSS_TRACE_CONFIG_DOWNLOAD_REQ_V01 0x0044 +#define QMI_WLANFW_QDSS_TRACE_CONFIG_DOWNLOAD_RESP_V01 0x0044 + +struct qmi_wlanfw_qdss_trace_config_download_req_msg_v01 { + u8 total_size_valid; + u32 total_size; + u8 seg_id_valid; + u32 seg_id; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; + u8 end_valid; + u8 end; +}; + +struct qmi_wlanfw_qdss_trace_config_download_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define QMI_WLANFW_QDSS_TRACE_MODE_REQ_V01 0x0045 +#define QMI_WLANFW_QDSS_TRACE_MODE_REQ_MSG_V01_MAX_LEN 18 +#define QMI_WLANFW_QDSS_TRACE_MODE_RESP_MSG_V01_MAX_LEN 7 +#define QMI_WLANFW_QDSS_TRACE_MODE_RESP_V01 0x0045 +#define QMI_WLANFW_QDSS_STOP_ALL_TRACE 0x01 + +enum qmi_wlanfw_qdss_trace_mode_enum_v01 { + WLFW_QDSS_TRACE_MODE_ENUM_MIN_VAL_V01 = INT_MIN, + QMI_WLANFW_QDSS_TRACE_OFF_V01 = 0, + QMI_WLANFW_QDSS_TRACE_ON_V01 = 1, + WLFW_QDSS_TRACE_MODE_ENUM_MAX_VAL_V01 = INT_MAX, +}; + +struct qmi_wlanfw_qdss_trace_mode_req_msg_v01 { + u8 mode_valid; + enum qmi_wlanfw_qdss_trace_mode_enum_v01 mode; + u8 option_valid; + u64 option; +}; + +struct qmi_wlanfw_qdss_trace_mode_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +#define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 355 + +struct qmi_wlanfw_m3_dump_upload_done_req_msg_v01 { + u32 pdev_id; + u32 status; +}; + +struct qmi_wlanfw_m3_dump_upload_done_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 #define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 64 #define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01 3 +#define QDSS_ETR_MEM_REGION_TYPE 0x6 struct qmi_wlanfw_host_ddr_range { u64 start; @@ -165,6 +275,7 @@ BDF_MEM_REGION_TYPE = 0x2, M3_DUMP_REGION_TYPE = 0x3, CALDB_MEM_REGION_TYPE = 0x4, + MLO_GLOBAL_MEM_REGION_TYPE = 0x8, PAGEABLE_MEM_REGION_TYPE = 0x9, }; @@ -189,6 +300,7 @@ enum ath12k_qmi_cnss_feature { CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN, CNSS_QDSS_CFG_MISS_V01 = 3, + CNSS_PCIE_PERST_NO_PULL_V01 = 4, CNSS_MAX_FEATURE_V01 = 64, CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX, }; @@ -243,13 +355,31 @@ struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01]; u8 feature_list_valid; u64 feature_list; - + u8 fw_cfg_support_valid; + u8 fw_cfg_support; }; struct qmi_wlanfw_host_cap_resp_msg_v01 { struct qmi_response_type_v01 resp; }; +#define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN 0 +#define QMI_WLANFW_PHY_CAP_REQ_V01 0x0057 +#define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN 18 +#define QMI_WLANFW_PHY_CAP_RESP_V01 0x0057 + +struct qmi_wlanfw_phy_cap_req_msg_v01 { + char placeholder; +}; + +struct qmi_wlanfw_phy_cap_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 num_phy_valid; + u8 num_phy; + u8 board_id_valid; + u32 board_id; +}; + #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 @@ -281,6 +411,14 @@ u8 xo_cal_enable; u8 cal_done_enable_valid; u8 cal_done_enable; + u8 qdss_trace_req_mem_enable_valid; + u8 qdss_trace_req_mem_enable; + u8 qdss_trace_save_enable_valid; + u8 qdss_trace_save_enable; + u8 qdss_trace_free_enable_valid; + u8 qdss_trace_free_enable; + u8 m3_dump_upload_req_enable_valid; + u8 m3_dump_upload_req_enable; }; struct qmi_wlanfw_ind_register_resp_msg_v01 { @@ -296,6 +434,7 @@ #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 +#define QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01 0x0040 #define QMI_WLANFW_MAX_STR_LEN_V01 16 struct qmi_wlanfw_mem_cfg_s_v01 { @@ -312,6 +451,11 @@ QMI_WLANFW_MEM_M3_V01 = 3, QMI_WLANFW_MEM_CAL_V01 = 4, QMI_WLANFW_MEM_DPD_V01 = 5, + QMI_WLANFW_MEM_QDSS_V01 = 6, + QMI_WLANFW_MEM_HANG_DATA_V01 = 7, + QMI_WLANFW_MEM_MLO_GLOBAL_V01 = 8, + QMI_WLANFW_MEM_PAGEABLE_V01 = 9, + QMI_WLANFW_MEM_AFC_V01 = 10, WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, }; @@ -351,10 +495,16 @@ char placeholder; }; +struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { + char placeholder; +}; + #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 #define QMI_WLANFW_CAP_REQ_V01 0x0024 #define QMI_WLANFW_CAP_RESP_V01 0x0024 +#define QMI_WLANFW_DEVICE_INFO_REQ_V01 0x004C +#define QMI_WLANFW_DEVICE_INFO_REQ_MSG_V01 0 enum qmi_wlanfw_pipedir_enum_v01 { QMI_WLFW_PIPEDIR_NONE_V01 = 0, @@ -460,12 +610,26 @@ enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap; u8 dev_mem_info_valid; struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01]; + u8 rxgainlut_support_valid; + u8 rxgainlut_support; }; struct qmi_wlanfw_cap_req_msg_v01 { char placeholder; }; +struct qmi_wlanfw_device_info_req_msg_v01 { + char placeholder; +}; + +struct qmi_wlanfw_device_info_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u64 bar_addr; + u32 bar_size; + u8 bar_addr_valid; + u8 bar_size_valid; +}; + #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 @@ -500,6 +664,8 @@ #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C +#define QMI_WLANFW_M3_DUMP_UPLOAD_DONE_REQ_MSG_V01_MAX_MSG_LEN 14 + struct qmi_wlanfw_m3_info_req_msg_v01 { u64 addr; u32 size; @@ -558,6 +724,110 @@ struct qmi_response_type_v01 resp; }; +struct qmi_wlanfw_qdss_trace_save_ind_msg_v01 { + u32 source; + u32 total_size; + u8 mem_seg_valid; + u32 mem_seg_len; + struct qmi_wlanfw_mem_seg_resp_s_v01 + mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; + u8 file_name_valid; + char file_name[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; +}; + +#define QDSS_TRACE_SEG_LEN_MAX 32 + +struct qdss_trace_mem_seg { + u64 addr; + u32 size; +}; + +struct ath12k_qmi_event_qdss_trace_save_data { + u32 total_size; + u32 mem_seg_len; + struct qdss_trace_mem_seg mem_seg[QDSS_TRACE_SEG_LEN_MAX]; +}; + +#define QMI_MEM_REGION_TYPE 0 +#define QMI_WLANFW_MEM_WRITE_REQ_V01 0x0031 +#define QMI_WLANFW_MEM_WRITE_REQ_MSG_V01_MAX_MSG_LEN 6163 +#define QMI_WLANFW_MEM_READ_REQ_V01 0x0030 +#define QMI_WLANFW_MEM_READ_REQ_MSG_V01_MAX_MSG_LEN 21 + +struct qmi_wlanfw_mem_read_req_msg_v01 { + u32 offset; + u32 mem_type; + u32 data_len; +}; + +struct qmi_wlanfw_mem_read_resp_msg_v01 { + struct qmi_response_type_v01 resp; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; +}; + +struct qmi_wlanfw_mem_write_req_msg_v01 { + u32 offset; + u32 mem_type; + u32 data_len; + u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; +}; + +struct qmi_wlanfw_mem_write_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +int ath12k_qmi_mem_read(struct ath12k_base *ab, u32 mem_addr, void *mem_value,size_t count); + +int ath12k_qmi_mem_write(struct ath12k_base *ab, u32 mem_addr, void* mem_value, size_t count); + +#define QMI_WLFW_INI_REQ_V01 0x002F +#define WLFW_INI_REQ_MSG_V01_MAX_MSG_LEN 4 + +struct wlfw_ini_req_msg_v01 { + u8 enablefwlog_valid; + u8 enablefwlog; +}; + +struct wlfw_ini_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + +struct qmi_wlanfw_m3_dump_upload_req_ind_msg_v01 { + u32 pdev_id; + u64 addr; + u64 size; +}; + +#define QMI_WLANFW_CFG_DOWNLOAD_REQ_V01 0x0056 +#define QMI_WLANFW_CFG_DOWNLOAD_RESP_V01 0x0056 +enum wlanfw_cfg_type_v01 { + WLANFW_CFG_TYPE_MIN_VAL_V01 = INT_MIN, + WLANFW_CFG_FILE_V01 = 0, + WLANFW_CFG_TYPE_MAX_VAL_V01 = INT_MAX, +}; + +#define WLANFW_CFG_DOWNLOAD_REQ_MSG_V01_MAX_MSG_LEN 6174 +struct wlanfw_cfg_download_req_msg_v01 { + u8 file_type_valid; + enum wlanfw_cfg_type_v01 file_type; + u8 total_size_valid; + u32 total_size; + u8 seg_id_valid; + u32 seg_id; + u8 data_valid; + u32 data_len; + u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; + u8 end_valid; + u8 end; +}; + +#define WLANFW_CFG_DOWNLOAD_RESP_MSG_V01_MAX_MSG_LEN 7 +struct wlanfw_cfg_download_resp_msg_v01 { + struct qmi_response_type_v01 resp; +}; + int ath12k_qmi_firmware_start(struct ath12k_base *ab, u32 mode); void ath12k_qmi_firmware_stop(struct ath12k_base *ab); @@ -566,4 +836,29 @@ void ath12k_qmi_deinit_service(struct ath12k_base *ab); int ath12k_qmi_init_service(struct ath12k_base *ab); +int ath12k_send_qdss_trace_mode_req(struct ath12k_base *ab, + enum qmi_wlanfw_qdss_trace_mode_enum_v01 mode); +int ath12k_qmi_fwreset_from_cold_boot(struct ath12k_base *ab); +int ath12k_enable_fwlog(struct ath12k_base *ab); +int ath12k_qmi_m3_dump_upload_done_ind_send(struct ath12k_base *ab, + u32 pdev_id, int status); +void ath12k_qmi_free_target_mem_chunk(struct ath12k_base *ab); +void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab); +int ath12k_qmi_mlo_global_snapshot_mem_init(struct ath12k_base *ab); +void ath12k_free_mlo_mgmt_rx_reo_per_link_info( + struct ath12k_host_mlo_glb_rx_reo_snapshot_info *snapshot_info); + +static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block) +{ + lockdep_assert_held(&qmi->event_lock); + + qmi->block_event = block; +} + +static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi) +{ + lockdep_assert_held(&qmi->event_lock); + + return qmi->block_event; +} #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/reg.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/reg.c --- linux-6.4/drivers/net/wireless/ath/ath12k/reg.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/reg.c 2024-01-26 16:32:21.055710360 +0100 @@ -28,11 +28,37 @@ } }; -static bool ath12k_regdom_changes(struct ath12k *ar, char *alpha2) +enum wmi_reg_6g_ap_type +ath12k_ieee80211_ap_pwr_type_convert(enum ieee80211_ap_reg_power power_type) +{ + switch (power_type) { + case IEEE80211_REG_LPI_AP: + return WMI_REG_INDOOR_AP; + case IEEE80211_REG_SP_AP: + return WMI_REG_STD_POWER_AP; + case IEEE80211_REG_VLP_AP: + return WMI_REG_VLP_AP; + default: + return WMI_REG_MAX_AP_TYPE; + } +} + +static void ath12k_copy_reg_rule(struct ath12k_reg_freq *ath12k_reg_freq, + struct ath12k_reg_rule *reg_rule) +{ + if (!ath12k_reg_freq->start_freq) + ath12k_reg_freq->start_freq = reg_rule->start_freq; + + if ((!ath12k_reg_freq->end_freq) || + (ath12k_reg_freq->end_freq < reg_rule->end_freq)) + ath12k_reg_freq->end_freq = reg_rule->end_freq; +} + +static bool ath12k_regdom_changes(struct ath12k_hw *ah, char *alpha2) { const struct ieee80211_regdomain *regd; - regd = rcu_dereference_rtnl(ar->hw->wiphy->regd); + regd = rcu_dereference_rtnl(ah->hw->wiphy->regd); /* This can happen during wiphy registration where the previous * user request is received before we update the regd received * from firmware. @@ -44,38 +70,11 @@ } static void -ath12k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) +ath12k_reg_send_request(struct ath12k *ar, struct regulatory_request *request) { - struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); struct ath12k_wmi_init_country_arg arg; - struct ath12k *ar = hw->priv; int ret; - ath12k_dbg(ar->ab, ATH12K_DBG_REG, - "Regulatory Notification received for %s\n", wiphy_name(wiphy)); - - /* Currently supporting only General User Hints. Cell base user - * hints to be handled later. - * Hints from other sources like Core, Beacons are not expected for - * self managed wiphy's - */ - if (!(request->initiator == NL80211_REGDOM_SET_BY_USER && - request->user_reg_hint_type == NL80211_USER_REG_HINT_USER)) { - ath12k_warn(ar->ab, "Unexpected Regulatory event for this wiphy\n"); - return; - } - - if (!IS_ENABLED(CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS)) { - ath12k_dbg(ar->ab, ATH12K_DBG_REG, - "Country Setting is not allowed\n"); - return; - } - - if (!ath12k_regdom_changes(ar, request->alpha2)) { - ath12k_dbg(ar->ab, ATH12K_DBG_REG, "Country is already set\n"); - return; - } - /* Set the country code to the firmware and wait for * the WMI_REG_CHAN_LIST_CC EVENT for updating the * reg info @@ -84,18 +83,104 @@ memcpy(&arg.cc_info.alpha2, request->alpha2, 2); arg.cc_info.alpha2[2] = 0; + ar->ab->regd_change_user_request[ar->pdev_idx] = true; ret = ath12k_wmi_send_init_country_cmd(ar, &arg); if (ret) ath12k_warn(ar->ab, "INIT Country code set to fw failed : %d\n", ret); } +static bool ath12k_reg_validate_pdev_state(struct ath12k *ar) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_pdev *pdev; + struct ath12k *tmp_ar; + int i; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (!pdev) + continue; + + tmp_ar = pdev->ar; + if (tmp_ar) { + mutex_lock(&tmp_ar->conf_mutex); + if ((tmp_ar->state == ATH12K_STATE_ON || + tmp_ar->state == ATH12K_STATE_RESTARTED) && + tmp_ar->num_started_vdevs) { + if (tmp_ar == ar) + ath12k_warn(ab, "%s has active interface, please bring down to set country code", + wiphy_name(ar->ah->hw->wiphy)); + mutex_unlock(&tmp_ar->conf_mutex); + return false; + } + mutex_unlock(&tmp_ar->conf_mutex); + } + } + return true; +} + +static bool ath12k_reg_validate_ah_state(struct ath12k_hw *ah) +{ + struct ath12k *ar = ah->radio; + int i; + + lockdep_assert_held(&ah->conf_mutex); + + for (i = 0; i < ah->num_radio; i++, ar++) { + /* The SET_INIT_COUNTRY command should not be sent to firmware while any vdev is active + * Also it does not make sense to give the command for certain pdev's alone. + * Hence check all the pdev's if any have an active vdev before sending the command. + */ + if (!ath12k_reg_validate_pdev_state(ar)) + return false; + } + + return true; +} + +void ath12k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) +{ + struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + int i; + + /* Currently supporting only General User Hints. Cell base user + * hints to be handled later. + * Hints from other sources like Core, Beacons are not expected for + * self managed wiphy's + */ + if (!(request->initiator == NL80211_REGDOM_SET_BY_USER && + request->user_reg_hint_type == NL80211_USER_REG_HINT_USER)) + return; + + if (!IS_ENABLED(CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS)) + return; + + mutex_lock(&ah->conf_mutex); + if (!ath12k_regdom_changes(ah, request->alpha2)) + goto exit; + + if (!ath12k_reg_validate_ah_state(ah)) + goto exit; + + ah->regd_updated = false; + ar = ah->radio; + + /* Send the reg change request to all the radios */ + for (i = 0; i < ah->num_radio; i++, ar++) + ath12k_reg_send_request(ar, request); +exit: + mutex_unlock(&ah->conf_mutex); +} + int ath12k_reg_update_chan_list(struct ath12k *ar) { struct ieee80211_supported_band **bands; struct ath12k_wmi_scan_chan_list_arg *arg; struct ieee80211_channel *channel; - struct ieee80211_hw *hw = ar->hw; + struct ieee80211_hw *hw = ar->ah->hw; struct ath12k_wmi_channel_arg *ch; enum nl80211_band band; int num_channels = 0; @@ -103,7 +188,7 @@ bands = hw->wiphy->bands; for (band = 0; band < NUM_NL80211_BANDS; band++) { - if (!bands[band]) + if (!(ar->mac.sbands[band].channels && bands[band])) continue; for (i = 0; i < bands[band]->n_channels; i++) { @@ -111,12 +196,20 @@ IEEE80211_CHAN_DISABLED) continue; + if (band == NL80211_BAND_5GHZ) + if (bands[band]->channels[i].center_freq < + ar->chan_info.low_freq || + bands[band]->channels[i].center_freq > + ar->chan_info.high_freq) + continue; num_channels++; } } - if (WARN_ON(!num_channels)) - return -EINVAL; + if (!num_channels) { + ath12k_warn(ar->ab, "pdev is not supported for this country\n"); + return -ENOTSUPP; + } arg = kzalloc(struct_size(arg, channel, num_channels), GFP_KERNEL); @@ -129,7 +222,7 @@ ch = arg->channel; for (band = 0; band < NUM_NL80211_BANDS; band++) { - if (!bands[band]) + if (!(ar->mac.sbands[band].channels && bands[band])) continue; for (i = 0; i < bands[band]->n_channels; i++) { @@ -138,6 +231,13 @@ if (channel->flags & IEEE80211_CHAN_DISABLED) continue; + if (band == NL80211_BAND_5GHZ) + if (bands[band]->channels[i].center_freq < + ar->chan_info.low_freq || + bands[band]->channels[i].center_freq > + ar->chan_info.high_freq) + continue; + /* TODO: Set to true/false based on some condition? */ ch->allow_ht = true; ch->allow_vht = true; @@ -197,18 +297,97 @@ sizeof(struct ieee80211_reg_rule)); } +int ath12k_reg_get_num_chans_in_band(struct ath12k *ar, + struct ieee80211_supported_band *band, + u32 freq_low, u32 freq_high) +{ + int i, count = 0; + + if (!(freq_low && freq_high) || !band) + return 0; + + for (i = 0; i < band->n_channels; i++) { + if (band->channels[i].center_freq >= freq_low && + band->channels[i].center_freq <= freq_high) + count++; + } + + return count; +} + int ath12k_regd_update(struct ath12k *ar, bool init) { struct ieee80211_regdomain *regd, *regd_copy = NULL; int ret, regd_len, pdev_id; struct ath12k_base *ab; + struct ath12k_hw *ah; + struct ath12k_wmi_hal_reg_capabilities_ext_arg *reg_cap; + int i; + u32 phy_id, freq_low, freq_high, supported_bands, band; ab = ar->ab; + ah = ar->ah; + + mutex_lock(&ah->conf_mutex); + + supported_bands = ar->pdev->cap.supported_bands; + if (supported_bands & WMI_HOST_WLAN_2G_CAP) + band = NL80211_BAND_2GHZ; + else if(supported_bands & WMI_HOST_WLAN_5G_CAP && !ar->supports_6ghz) + band = NL80211_BAND_5GHZ; + else if(supported_bands & WMI_HOST_WLAN_5G_CAP && ar->supports_6ghz) + band = NL80211_BAND_6GHZ; + + reg_cap = &ab->hal_reg_cap[ar->pdev_idx]; + + if (ab->hw_params->single_pdev_only && !ar->supports_6ghz) { + phy_id = ar->pdev->cap.band[band].phy_id; + reg_cap = &ab->hal_reg_cap[phy_id]; + } + + /* Possible that due to reg change, current limits for supported + * frequency changed. Update that + */ + if (supported_bands & WMI_HOST_WLAN_2G_CAP) { + freq_low = max(reg_cap->low_2ghz_chan, ab->reg_freq_2g.start_freq); + freq_high = min(reg_cap->high_2ghz_chan, ab->reg_freq_2g.end_freq); + } else if(supported_bands & WMI_HOST_WLAN_5G_CAP && !ar->supports_6ghz) { + freq_low = max(reg_cap->low_5ghz_chan, ab->reg_freq_5g.start_freq); + freq_high = min(reg_cap->high_5ghz_chan, ab->reg_freq_5g.end_freq); + } else if(supported_bands & WMI_HOST_WLAN_5G_CAP && ar->supports_6ghz) { + freq_low = max(reg_cap->low_5ghz_chan, ab->reg_freq_6g.start_freq); + freq_high = min(reg_cap->high_5ghz_chan, ab->reg_freq_6g.end_freq); + } + + ar->chan_info.low_freq = freq_low; + ar->chan_info.high_freq = freq_high; + ar->chan_info.num_channels = ath12k_reg_get_num_chans_in_band(ar, + &ar->mac.sbands[band], + freq_low, + freq_high); + + ath12k_dbg(ab, ATH12K_DBG_REG, "pdev %u reg updated freq limits %u->%u MHz no of channel %u\n", + ar->pdev->pdev_id, ar->chan_info.low_freq, + ar->chan_info.high_freq, ar->chan_info.num_channels); + + /* Since FW provides reg rules which are similar for 2G/5G pdev + * but since 6G pdev has superset of all rules including rules for + * all bands, we prefer 6G pdev. If 6GHz pdev was part of the + * ath12k_hw, wait for the 6GHz pdev, else pick the first pdev + * which calls this function and use its regd to update global + * hw regd. The regd_updated flag set at the end will not allow + * any further updates. + */ + if ((ah->supported_band_mask & BIT(NL80211_BAND_6GHZ)) && !ar->supports_6ghz) { + mutex_unlock(&ah->conf_mutex); + return 0; + } + pdev_id = ar->pdev_idx; spin_lock_bh(&ab->base_lock); - if (init) { + if (init && !ab->new_regd[pdev_id]) { /* Apply the regd received during init through * WMI_REG_CHAN_LIST_CC event. In case of failure to * receive the regd, initialize with a default world @@ -245,25 +424,38 @@ goto err; } - rtnl_lock(); - wiphy_lock(ar->hw->wiphy); - ret = regulatory_set_wiphy_regd_sync(ar->hw->wiphy, regd_copy); - wiphy_unlock(ar->hw->wiphy); - rtnl_unlock(); + ret = regulatory_set_wiphy_regd(ah->hw->wiphy, regd_copy); kfree(regd_copy); if (ret) goto err; + ah->regd_updated = true; + + /* Apply the new regd to all the radios, this is expected to be received only once + * since we check for ah->regd_updated and allow here only once + */ + ar = ah->radio; + ab = ar->ab; + + for (i = 0; i < ah->num_radio; i++) { + ab = ar->ab; + if (ar->state == ATH12K_STATE_ON) { ret = ath12k_reg_update_chan_list(ar); - if (ret) + if (ret && ret == -ENOTSUPP) + continue; + else if (ret) goto err; } + ar++; + } + mutex_unlock(&ah->conf_mutex); return 0; err: + mutex_unlock(&ah->conf_mutex); ath12k_warn(ab, "failed to perform regd update : %d\n", ret); return ret; } @@ -276,16 +468,45 @@ case ATH12K_DFS_REG_CN: return NL80211_DFS_FCC; case ATH12K_DFS_REG_ETSI: - case ATH12K_DFS_REG_KR: return NL80211_DFS_ETSI; case ATH12K_DFS_REG_MKK: case ATH12K_DFS_REG_MKK_N: + case ATH12K_DFS_REG_KR: return NL80211_DFS_JP; default: return NL80211_DFS_UNSET; } } +static u32 ath12k_update_bw_reg_flags(u16 max_bw) +{ + u32 flags = 0; + switch (max_bw) { + case 20: + flags = (NL80211_RRF_NO_HT40 | + NL80211_RRF_NO_80MHZ | + NL80211_RRF_NO_160MHZ | + NL80211_RRF_NO_320MHZ); + break; + case 40: + flags = (NL80211_RRF_NO_80MHZ | + NL80211_RRF_NO_160MHZ | + NL80211_RRF_NO_320MHZ ); + break; + case 80: + flags = (NL80211_RRF_NO_160MHZ | + NL80211_RRF_NO_320MHZ); + break; + case 160: + flags = NL80211_RRF_NO_320MHZ; + break; + default: + break; + } + + return flags; +} + static u32 ath12k_map_fw_reg_flags(u16 reg_flags) { u32 flags = 0; @@ -314,128 +535,22 @@ return flags; } -static bool -ath12k_reg_can_intersect(struct ieee80211_reg_rule *rule1, - struct ieee80211_reg_rule *rule2) -{ - u32 start_freq1, end_freq1; - u32 start_freq2, end_freq2; - - start_freq1 = rule1->freq_range.start_freq_khz; - start_freq2 = rule2->freq_range.start_freq_khz; - - end_freq1 = rule1->freq_range.end_freq_khz; - end_freq2 = rule2->freq_range.end_freq_khz; - - if ((start_freq1 >= start_freq2 && - start_freq1 < end_freq2) || - (start_freq2 > start_freq1 && - start_freq2 < end_freq1)) - return true; - - /* TODO: Should we restrict intersection feasibility - * based on min bandwidth of the intersected region also, - * say the intersected rule should have a min bandwidth - * of 20MHz? - */ - - return false; -} - -static void ath12k_reg_intersect_rules(struct ieee80211_reg_rule *rule1, - struct ieee80211_reg_rule *rule2, - struct ieee80211_reg_rule *new_rule) -{ - u32 start_freq1, end_freq1; - u32 start_freq2, end_freq2; - u32 freq_diff, max_bw; - - start_freq1 = rule1->freq_range.start_freq_khz; - start_freq2 = rule2->freq_range.start_freq_khz; - - end_freq1 = rule1->freq_range.end_freq_khz; - end_freq2 = rule2->freq_range.end_freq_khz; - - new_rule->freq_range.start_freq_khz = max_t(u32, start_freq1, - start_freq2); - new_rule->freq_range.end_freq_khz = min_t(u32, end_freq1, end_freq2); - - freq_diff = new_rule->freq_range.end_freq_khz - - new_rule->freq_range.start_freq_khz; - max_bw = min_t(u32, rule1->freq_range.max_bandwidth_khz, - rule2->freq_range.max_bandwidth_khz); - new_rule->freq_range.max_bandwidth_khz = min_t(u32, max_bw, freq_diff); - - new_rule->power_rule.max_antenna_gain = - min_t(u32, rule1->power_rule.max_antenna_gain, - rule2->power_rule.max_antenna_gain); - - new_rule->power_rule.max_eirp = min_t(u32, rule1->power_rule.max_eirp, - rule2->power_rule.max_eirp); - - /* Use the flags of both the rules */ - new_rule->flags = rule1->flags | rule2->flags; - - /* To be safe, lts use the max cac timeout of both rules */ - new_rule->dfs_cac_ms = max_t(u32, rule1->dfs_cac_ms, - rule2->dfs_cac_ms); -} - -static struct ieee80211_regdomain * -ath12k_regd_intersect(struct ieee80211_regdomain *default_regd, - struct ieee80211_regdomain *curr_regd) +static u32 ath12k_map_fw_phy_flags(u32 phy_flags) { - u8 num_old_regd_rules, num_curr_regd_rules, num_new_regd_rules; - struct ieee80211_reg_rule *old_rule, *curr_rule, *new_rule; - struct ieee80211_regdomain *new_regd = NULL; - u8 i, j, k; + u32 flags = 0; - num_old_regd_rules = default_regd->n_reg_rules; - num_curr_regd_rules = curr_regd->n_reg_rules; - num_new_regd_rules = 0; + if (phy_flags & ATH12K_REG_PHY_BITMAP_NO11AX) + flags |= NL80211_RRF_NO_HE; - /* Find the number of intersecting rules to allocate new regd memory */ - for (i = 0; i < num_old_regd_rules; i++) { - old_rule = default_regd->reg_rules + i; - for (j = 0; j < num_curr_regd_rules; j++) { - curr_rule = curr_regd->reg_rules + j; + if (phy_flags & ATH12K_REG_PHY_BITMAP_NO11BE) + flags |= NL80211_RRF_NO_EHT; - if (ath12k_reg_can_intersect(old_rule, curr_rule)) - num_new_regd_rules++; - } + return flags; } - if (!num_new_regd_rules) - return NULL; - - new_regd = kzalloc(sizeof(*new_regd) + (num_new_regd_rules * - sizeof(struct ieee80211_reg_rule)), - GFP_ATOMIC); - - if (!new_regd) - return NULL; - - /* We set the new country and dfs region directly and only trim - * the freq, power, antenna gain by intersecting with the - * default regdomain. Also MAX of the dfs cac timeout is selected. - */ - new_regd->n_reg_rules = num_new_regd_rules; - memcpy(new_regd->alpha2, curr_regd->alpha2, sizeof(new_regd->alpha2)); - new_regd->dfs_region = curr_regd->dfs_region; - new_rule = new_regd->reg_rules; - - for (i = 0, k = 0; i < num_old_regd_rules; i++) { - old_rule = default_regd->reg_rules + i; - for (j = 0; j < num_curr_regd_rules; j++) { - curr_rule = curr_regd->reg_rules + j; - - if (ath12k_reg_can_intersect(old_rule, curr_rule)) - ath12k_reg_intersect_rules(old_rule, curr_rule, - (new_rule + k++)); - } - } - return new_regd; -} +/* TODO: API ath12k_reg_can_intersect() to handle whether two + * ieee80211_reg_rules can intersect or not based on their + * frequency range and power mode. */ static const char * ath12k_reg_get_regdom_str(enum nl80211_dfs_regions dfs_region) @@ -473,13 +588,15 @@ static void ath12k_reg_update_rule(struct ieee80211_reg_rule *reg_rule, u32 start_freq, u32 end_freq, u32 bw, u32 ant_gain, u32 reg_pwr, - u32 reg_flags) + s8 psd, u32 reg_flags, + int pwr_mode) { reg_rule->freq_range.start_freq_khz = MHZ_TO_KHZ(start_freq); reg_rule->freq_range.end_freq_khz = MHZ_TO_KHZ(end_freq); reg_rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw); reg_rule->power_rule.max_antenna_gain = DBI_TO_MBI(ant_gain); reg_rule->power_rule.max_eirp = DBM_TO_MBM(reg_pwr); + reg_rule->psd = psd; reg_rule->flags = reg_flags; } @@ -501,7 +618,7 @@ ath12k_reg_update_rule(regd->reg_rules + i, reg_rule->start_freq, ETSI_WEATHER_RADAR_BAND_LOW, bw, reg_rule->ant_gain, reg_rule->reg_power, - flags); + reg_rule->psd_eirp, flags, 0); ath12k_dbg(ab, ATH12K_DBG_REG, "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n", @@ -523,7 +640,7 @@ ath12k_reg_update_rule(regd->reg_rules + i, ETSI_WEATHER_RADAR_BAND_LOW, end_freq, bw, reg_rule->ant_gain, reg_rule->reg_power, - flags); + reg_rule->psd_eirp, flags, 0); regd->reg_rules[i].dfs_cac_ms = ETSI_WEATHER_RADAR_BAND_CAC_TIMEOUT; @@ -548,7 +665,7 @@ ath12k_reg_update_rule(regd->reg_rules + i, ETSI_WEATHER_RADAR_BAND_HIGH, reg_rule->end_freq, bw, reg_rule->ant_gain, reg_rule->reg_power, - flags); + reg_rule->psd_eirp, flags, 0); ath12k_dbg(ab, ATH12K_DBG_REG, "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n", @@ -562,15 +679,17 @@ struct ieee80211_regdomain * ath12k_reg_build_regd(struct ath12k_base *ab, - struct ath12k_reg_info *reg_info, bool intersect) + struct ath12k_reg_info *reg_info, + enum ieee80211_ap_reg_power power_type) { - struct ieee80211_regdomain *tmp_regd, *default_regd, *new_regd = NULL; + struct ieee80211_regdomain *new_regd = NULL; struct ath12k_reg_rule *reg_rule; u8 i = 0, j = 0, k = 0; u8 num_rules; u16 max_bw; - u32 flags; + u32 flags = 0; char alpha2[3]; + int pwr_mode; num_rules = reg_info->num_5g_reg_rules + reg_info->num_2g_reg_rules; @@ -582,50 +701,59 @@ num_rules += reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP]; if (!num_rules) - goto ret; + return new_regd; /* Add max additional rules to accommodate weather radar band */ if (reg_info->dfs_region == ATH12K_DFS_REG_ETSI) num_rules += 2; - tmp_regd = kzalloc(sizeof(*tmp_regd) + + new_regd = kzalloc(sizeof(*new_regd) + (num_rules * sizeof(struct ieee80211_reg_rule)), GFP_ATOMIC); - if (!tmp_regd) - goto ret; + if (!new_regd) + return new_regd; - memcpy(tmp_regd->alpha2, reg_info->alpha2, REG_ALPHA2_LEN + 1); + memcpy(new_regd->alpha2, reg_info->alpha2, REG_ALPHA2_LEN + 1); memcpy(alpha2, reg_info->alpha2, REG_ALPHA2_LEN + 1); alpha2[2] = '\0'; - tmp_regd->dfs_region = ath12k_map_fw_dfs_region(reg_info->dfs_region); + new_regd->dfs_region = ath12k_map_fw_dfs_region(reg_info->dfs_region); ath12k_dbg(ab, ATH12K_DBG_REG, "\r\nCountry %s, CFG Regdomain %s FW Regdomain %d, num_reg_rules %d\n", - alpha2, ath12k_reg_get_regdom_str(tmp_regd->dfs_region), + alpha2, ath12k_reg_get_regdom_str(new_regd->dfs_region), reg_info->dfs_region, num_rules); /* Update reg_rules[] below. Firmware is expected to * send these rules in order(2G rules first and then 5G) */ - for (; i < num_rules; i++) { + for (i = 0, j = 0; i < num_rules; i++) { if (reg_info->num_2g_reg_rules && (i < reg_info->num_2g_reg_rules)) { reg_rule = reg_info->reg_rules_2g_ptr + i; max_bw = min_t(u16, reg_rule->max_bw, reg_info->max_bw_2g); - flags = 0; + flags = ath12k_update_bw_reg_flags(reg_info->max_bw_2g); + pwr_mode = 0; + ath12k_copy_reg_rule(&ab->reg_freq_2g, reg_rule); } else if (reg_info->num_5g_reg_rules && (j < reg_info->num_5g_reg_rules)) { reg_rule = reg_info->reg_rules_5g_ptr + j++; max_bw = min_t(u16, reg_rule->max_bw, reg_info->max_bw_5g); - + flags = NL80211_RRF_AUTO_BW | ath12k_update_bw_reg_flags(reg_info->max_bw_5g); /* FW doesn't pass NL80211_RRF_AUTO_BW flag for * BW Auto correction, we can enable this by default * for all 5G rules here. The regulatory core performs * BW correction if required and applies flags as * per other BW rule flags we pass from here */ - flags = NL80211_RRF_AUTO_BW; + if ((reg_rule->start_freq == 5490) && (reg_rule->end_freq == 5730)) + flags &= ~NL80211_RRF_NO_320MHZ; + + pwr_mode = 0; + if (reg_rule->end_freq <= ATH12K_MAX_5G_FREQ) + ath12k_copy_reg_rule(&ab->reg_freq_5g, reg_rule); + else if (reg_rule->start_freq >= ATH12K_MIN_6G_FREQ) + ath12k_copy_reg_rule(&ab->reg_freq_6g, reg_rule); } else if (reg_info->is_ext_reg_event && reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP] && (k < reg_info->num_6g_reg_rules_ap[WMI_REG_INDOOR_AP])) { @@ -633,17 +761,25 @@ max_bw = min_t(u16, reg_rule->max_bw, reg_info->max_bw_6g_ap[WMI_REG_INDOOR_AP]); flags = NL80211_RRF_AUTO_BW; + if (reg_rule->psd_flag) + flags |= NL80211_RRF_PSD; + + if (reg_rule->end_freq <= ATH12K_MAX_6G_FREQ) + ath12k_copy_reg_rule(&ab->reg_freq_6g, reg_rule); + else if (reg_rule->start_freq >= ATH12K_MIN_6G_FREQ) + ath12k_copy_reg_rule(&ab->reg_freq_6g, reg_rule); } else { break; } flags |= ath12k_map_fw_reg_flags(reg_rule->flags); + flags |= ath12k_map_fw_phy_flags(reg_info->phybitmap); - ath12k_reg_update_rule(tmp_regd->reg_rules + i, + ath12k_reg_update_rule(new_regd->reg_rules + i, reg_rule->start_freq, reg_rule->end_freq, max_bw, reg_rule->ant_gain, reg_rule->reg_power, - flags); + reg_rule->psd_eirp, flags, pwr_mode); /* Update dfs cac timeout if the dfs domain is ETSI and the * new rule covers weather radar band. @@ -654,7 +790,7 @@ reg_info->dfs_region == ATH12K_DFS_REG_ETSI && (reg_rule->end_freq > ETSI_WEATHER_RADAR_BAND_LOW && reg_rule->start_freq < ETSI_WEATHER_RADAR_BAND_HIGH)){ - ath12k_reg_update_weather_radar_band(ab, tmp_regd, + ath12k_reg_update_weather_radar_band(ab, new_regd, reg_rule, &i, flags, max_bw); continue; @@ -664,37 +800,20 @@ ath12k_dbg(ab, ATH12K_DBG_REG, "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d) (%d, %d)\n", i + 1, reg_rule->start_freq, reg_rule->end_freq, max_bw, reg_rule->ant_gain, reg_rule->reg_power, - tmp_regd->reg_rules[i].dfs_cac_ms, + new_regd->reg_rules[i].dfs_cac_ms, flags, reg_rule->psd_flag, reg_rule->psd_eirp); } else { ath12k_dbg(ab, ATH12K_DBG_REG, "\t%d. (%d - %d @ %d) (%d, %d) (%d ms) (FLAGS %d)\n", i + 1, reg_rule->start_freq, reg_rule->end_freq, max_bw, reg_rule->ant_gain, reg_rule->reg_power, - tmp_regd->reg_rules[i].dfs_cac_ms, + new_regd->reg_rules[i].dfs_cac_ms, flags); } } - tmp_regd->n_reg_rules = i; + new_regd->n_reg_rules = i; - if (intersect) { - default_regd = ab->default_regd[reg_info->phy_id]; - - /* Get a new regd by intersecting the received regd with - * our default regd. - */ - new_regd = ath12k_regd_intersect(default_regd, tmp_regd); - kfree(tmp_regd); - if (!new_regd) { - ath12k_warn(ab, "Unable to create intersected regdomain\n"); - goto ret; - } - } else { - new_regd = tmp_regd; - } - -ret: return new_regd; } @@ -715,12 +834,6 @@ } } -void ath12k_reg_init(struct ath12k *ar) -{ - ar->hw->wiphy->regulatory_flags = REGULATORY_WIPHY_SELF_MANAGED; - ar->hw->wiphy->reg_notifier = ath12k_reg_notifier; -} - void ath12k_reg_free(struct ath12k_base *ab) { int i; diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/reg.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/reg.h --- linux-6.4/drivers/net/wireless/ath/ath12k/reg.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/reg.h 2024-01-19 17:01:19.873847249 +0100 @@ -25,6 +25,17 @@ ATH12K_DFS_REG_UNDEF, }; +/* Phybitmap supported in Firmware */ +enum ath12k_reg_phy_bitmap { + ATH12K_REG_PHY_BITMAP_NO11A = 0x0001, + ATH12K_REG_PHY_BITMAP_NO11B = 0x0002, + ATH12K_REG_PHY_BITMAP_NO11G = 0x0004, + ATH12K_REG_PHY_BITMAP_NO11N = 0x0008, + ATH12K_REG_PHY_BITMAP_NO11AC = 0x0010, + ATH12K_REG_PHY_BITMAP_NO11AX = 0x0020, + ATH12K_REG_PHY_BITMAP_NO11BE = 0x0040, +}; + enum ath12k_reg_cc_code { REG_SET_CC_STATUS_PASS = 0, REG_CURRENT_ALPHA2_NOT_FOUND = 1, @@ -42,7 +53,7 @@ u8 ant_gain; u16 flags; bool psd_flag; - u16 psd_eirp; + s8 psd_eirp; }; struct ath12k_reg_info { @@ -83,13 +94,19 @@ [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; }; -void ath12k_reg_init(struct ath12k *ar); +void ath12k_reg_notifier(struct wiphy *wiphy, + struct regulatory_request *request); void ath12k_reg_free(struct ath12k_base *ab); void ath12k_regd_update_work(struct work_struct *work); struct ieee80211_regdomain *ath12k_reg_build_regd(struct ath12k_base *ab, struct ath12k_reg_info *reg_info, - bool intersect); + enum ieee80211_ap_reg_power power_type); +enum wmi_reg_6g_ap_type +ath12k_ieee80211_ap_pwr_type_convert(enum ieee80211_ap_reg_power power_type); int ath12k_regd_update(struct ath12k *ar, bool init); int ath12k_reg_update_chan_list(struct ath12k *ar); +int ath12k_reg_get_num_chans_in_band(struct ath12k *ar, + struct ieee80211_supported_band *band, + u32 freq_low, u32 freq_high); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/rx_desc.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/rx_desc.h --- linux-6.4/drivers/net/wireless/ath/ath12k/rx_desc.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/rx_desc.h 2024-01-19 17:01:19.873847249 +0100 @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH12K_RX_DESC_H #define ATH12K_RX_DESC_H @@ -59,6 +59,8 @@ #define RX_MPDU_START_INFO3_AST_LOOKUP_VALID BIT(13) #define RX_MPDU_START_INFO3_RANGING BIT(14) +#define RX_MPDU_START_SW_PEER_ID_PEER GENMASK(13, 0) + #define RX_MPDU_START_INFO4_MPDU_FCTRL_VALID BIT(0) #define RX_MPDU_START_INFO4_MPDU_DUR_VALID BIT(1) #define RX_MPDU_START_INFO4_MAC_ADDR1_VALID BIT(2) @@ -117,6 +119,28 @@ #define RX_MPDU_START_INFO8_AUTH_TO_SEND_WDS BIT(0) struct rx_mpdu_start_qcn9274 { + __le32 info1; + __le32 pn[4]; + __le32 info2; + __le32 peer_meta_data; + __le16 info3; + __le16 phy_ppdu_id; + __le16 ast_index; + __le16 sw_peer_id; + __le32 info4; + __le32 info5; + __le32 info6; + __le16 frame_ctrl; + __le16 duration; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + __le16 seq_ctrl; + u8 addr4[ETH_ALEN]; + __le16 qos_ctrl; +} __packed; + +struct rx_mpdu_start_wcn7850 { __le32 info0; __le32 reo_queue_desc_lo; __le32 info1; @@ -582,6 +606,8 @@ RX_MSDU_START_PKT_TYPE_11N, RX_MSDU_START_PKT_TYPE_11AC, RX_MSDU_START_PKT_TYPE_11AX, + RX_MSDU_START_PKT_TYPE_11BA, + RX_MSDU_START_PKT_TYPE_11BE, }; enum rx_msdu_start_sgi { @@ -608,6 +634,10 @@ RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO, }; +#define RX_MSDU_END_64_TLV_TAG GENMASK(9, 1) +#define RX_MSDU_END_64_TLV_LEN GENMASK(21, 10) +#define RX_MSDU_END_64_TLV_SRC_LINK_ID GENMASK(24, 22) + #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER GENMASK(1, 0) #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID GENMASK(8, 2) @@ -661,7 +691,7 @@ #define RX_MSDU_END_INFO9_SERVICE_CODE GENMASK(14, 6) #define RX_MSDU_END_INFO9_PRIORITY_VALID BIT(15) -#define RX_MSDU_END_INFO9_INRA_BSS BIT(16) +#define RX_MSDU_END_INFO9_INTRA_BSS BIT(16) #define RX_MSDU_END_INFO9_DEST_CHIP_ID GENMASK(18, 17) #define RX_MSDU_END_INFO9_MCAST_ECHO BIT(19) #define RX_MSDU_END_INFO9_WDS_LEARN_EVENT BIT(20) @@ -737,6 +767,22 @@ #define RX_MSDU_END_INFO14_MSDU_DONE BIT(31) struct rx_msdu_end_qcn9274 { + __le64 msdu_end_tag; + __le16 sa_sw_peer_id; + __le16 info5; + __le16 sa_idx; + __le16 da_idx_or_sw_peer_id; + __le32 info10; + __le32 info11; + __le32 info12; + __le32 flow_id_toeplitz; + __le32 ppdu_start_timestamp_63_32; + __le32 phy_meta_data; + __le32 info13; + __le32 info14; +} __packed; + +struct rx_msdu_end_wcn7850 { __le16 info0; __le16 phy_ppdu_id; __le16 ip_hdr_cksum; @@ -1410,10 +1456,10 @@ struct hal_rx_desc_wcn7850 { __le64 msdu_end_tag; - struct rx_msdu_end_qcn9274 msdu_end; + struct rx_msdu_end_wcn7850 msdu_end; u8 rx_padding0[RX_BE_PADDING0_BYTES]; __le64 mpdu_start_tag; - struct rx_mpdu_start_qcn9274 mpdu_start; + struct rx_mpdu_start_wcn7850 mpdu_start; struct rx_pkt_hdr_tlv pkt_hdr_tlv; u8 msdu_payload[]; }; diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/wmi.c linux-6.4-fbx/drivers/net/wireless/ath/ath12k/wmi.c --- linux-6.4/drivers/net/wireless/ath/ath12k/wmi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/wmi.c 2024-04-19 16:04:28.961735885 +0200 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause-Clear /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -19,6 +19,7 @@ #include "mac.h" #include "hw.h" #include "peer.h" +#include "testmode.h" struct ath12k_wmi_svc_ready_parse { bool wmi_svc_bitmap_done; @@ -38,6 +39,9 @@ u32 max_bssid_rx_filters; u32 num_hw_modes; u32 num_phy; + u32 num_chainmask_tables; + struct ath12k_chainmask_table + chainmask_table[ATH12K_MAX_CHAINMASK_TABLES]; }; struct ath12k_wmi_svc_rdy_ext_parse { @@ -56,6 +60,7 @@ bool hw_mode_done; bool mac_phy_done; bool ext_hal_reg_done; + u32 n_mac_phy_chainmask_combo; bool mac_phy_chainmask_combo_done; bool mac_phy_chainmask_cap_done; bool oem_dma_ring_cap_done; @@ -63,8 +68,11 @@ }; struct ath12k_wmi_svc_rdy_ext2_parse { + struct ath12k_service_ext2_param param; struct ath12k_wmi_dma_ring_caps_parse dma_caps_parse; bool dma_ring_cap_done; + bool spectral_bin_scaling_done; + bool mac_phy_caps_ext_done; }; struct ath12k_wmi_rdy_parse { @@ -81,6 +89,25 @@ bool meta_data_done; }; +struct wmi_pdev_sscan_fw_param_parse { + struct ath12k_wmi_pdev_sscan_fw_cmd_fixed_param fixed; + struct ath12k_wmi_pdev_sscan_fft_bin_index *bin; + struct ath12k_wmi_pdev_sscan_chan_info ch_info; + struct ath12k_wmi_pdev_sscan_per_detector_info *det_info; + bool bin_entry_done; + bool det_info_entry_done; + +}; + +struct wmi_spectral_capabilities_parse { + struct ath12k_wmi_spectral_scan_bw_capabilities *sscan_bw_caps; + struct ath12k_wmi_spectral_fft_size_capabilities *fft_size_caps; + bool sscan_bw_caps_entry_done; + bool fft_size_caps_entry_done; + u32 num_bw_caps_entry; + u32 num_fft_size_caps_entry; +}; + struct ath12k_wmi_tlv_policy { size_t min_len; }; @@ -89,11 +116,18 @@ const struct ath12k_wmi_mgmt_rx_params *fixed; const u8 *frame_buf; bool frame_buf_done; + struct ath12k_wmi_mgmt_rx_reo_params *reo_params; + struct ath12k_wmi_mgmt_rx_fw_consumed_hdr *fw_consumed_reo_params; + struct ath12k_mgmt_rx_cu_arg cu_params; + bool mgmt_ml_info_done; + bool bpcc_buf_done; }; static const struct ath12k_wmi_tlv_policy ath12k_wmi_tlv_policies[] = { [WMI_TAG_ARRAY_BYTE] = { .min_len = 0 }, [WMI_TAG_ARRAY_UINT32] = { .min_len = 0 }, + [WMI_TAG_ARRAY_STRUCT] = { .min_len = 0 }, + [WMI_TAG_ARRAY_INT16] = { .min_len = 0 }, [WMI_TAG_SERVICE_READY_EVENT] = { .min_len = sizeof(struct wmi_service_ready_event) }, [WMI_TAG_SERVICE_READY_EXT_EVENT] = { @@ -134,6 +168,8 @@ .min_len = sizeof(struct wmi_service_available_event) }, [WMI_TAG_PEER_ASSOC_CONF_EVENT] = { .min_len = sizeof(struct wmi_peer_assoc_conf_event) }, + [WMI_TAG_STATS_EVENT] = { + .min_len = sizeof(struct wmi_stats_event) }, [WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT] = { .min_len = sizeof(struct wmi_pdev_ctl_failsafe_chk_event) }, [WMI_TAG_HOST_SWFDA_EVENT] = { @@ -142,8 +178,31 @@ .min_len = sizeof(struct wmi_probe_resp_tx_status_event) }, [WMI_TAG_VDEV_DELETE_RESP_EVENT] = { .min_len = sizeof(struct wmi_vdev_delete_resp_event) }, + [WMI_TAG_MUEDCA_PARAMS_CONFIG_EVENT] = { + .min_len = sizeof(struct wmi_pdev_update_muedca_event) }, + [WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT] = { + .min_len = sizeof(struct wmi_twt_add_dialog_event) }, + [WMI_TAG_OBSS_COLOR_COLLISION_EVT] = { + .min_len = sizeof(struct wmi_obss_color_collision_event) }, + [WMI_TAG_CTRL_PATH_EVENT_FIXED_PARAM] = { + .min_len = sizeof(struct wmi_cp_stats_event_fixed_param) }, + [WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT] = { + .min_len = sizeof(struct wmi_offchan_data_tx_compl_event) }, }; +static const u32 eml_trans_timeout[EMLCAP_TIMEOUT_MAX] = { + EMLCAP_TRANSTIMEOUT_0, + EMLCAP_TRANSTIMEOUT_1, + EMLCAP_TRANSTIMEOUT_2, + EMLCAP_TRANSTIMEOUT_3, + EMLCAP_TRANSTIMEOUT_4, + EMLCAP_TRANSTIMEOUT_5, + EMLCAP_TRANSTIMEOUT_6, + EMLCAP_TRANSTIMEOUT_7, + EMLCAP_TRANSTIMEOUT_8, + EMLCAP_TRANSTIMEOUT_9, + EMLCAP_TRANSTIMEOUT_10}; + static __le32 ath12k_wmi_tlv_hdr(u32 cmd, u32 len) { return le32_encode_bits(cmd, WMI_TLV_TAG) | @@ -155,9 +214,188 @@ return ath12k_wmi_tlv_hdr(cmd, len - TLV_HDR_SIZE); } +static int ath12k_pull_svc_ready_ext2(struct ath12k_wmi_pdev *wmi_handle, + const void *ptr, + struct ath12k_service_ext2_param *param) +{ + const struct wmi_service_ready_ext2_event *ev = ptr; + + if (!ev) + return -EINVAL; + + param->reg_db_version = ev->reg_db_version; + param->hw_min_max_tx_power_2g = ev->hw_min_max_tx_power_2g; + param->hw_min_max_tx_power_5g = ev->hw_min_max_tx_power_5g; + param->chwidth_num_peer_caps = ev->chwidth_num_peer_caps; + param->ru_punct_supp_bw = ev->ru_punct_supp_bw; + param->max_user_per_ppdu_ofdma = ev->max_user_per_ppdu_ofdma; + param->max_user_per_ppdu_mumimo = ev->max_user_per_ppdu_mumimo; + param->target_cap_flags = ev->target_cap_flags; + param->max_msduq_per_tid = ev->max_num_msduq_supported_per_tid; + param->default_msduq_per_tid = ev->default_num_msduq_supported_per_tid; + return 0; +} + +static int ath12k_wmi_tlv_mac_phy_caps_ext_parse(struct ath12k_base *ab, + struct wmi_mac_phy_caps_ext *caps, + struct ath12k_pdev *pdev, + struct ath12k_wmi_svc_rdy_ext2_parse *data) +{ + struct ath12k_band_cap *cap_band; + struct ath12k_pdev_cap *pdev_cap = &pdev->cap; + + if (pdev_cap->supported_bands & WMI_HOST_WLAN_2G_CAP) { + cap_band = &pdev_cap->band[NL80211_BAND_2GHZ]; + memcpy(cap_band->eht_cap_mac_info, &caps->eht_cap_mac_info_2G, + sizeof(u32) * PSOC_HOST_MAX_MAC_SIZE); + memcpy(cap_band->eht_cap_phy_info, &caps->eht_cap_phy_info_2G, + sizeof(u32) * PSOC_HOST_MAX_PHY_SIZE); + cap_band->eht_mcs_20_only = caps->eht_supp_mcs_ext_2G[0]; + cap_band->eht_mcs_80 = caps->eht_supp_mcs_ext_2G[1]; + cap_band->eht_mcs_160 = 0xFFFFFFFF; + cap_band->eht_mcs_320 = 0xFFFFFFFF; + memcpy(&cap_band->eht_ppet, &caps->eht_ppet2G, + sizeof(struct ath12k_ppe_threshold)); + cap_band->eht_cap_info_internal = caps->eht_cap_info_internal; + } + + if (pdev_cap->supported_bands & WMI_HOST_WLAN_5G_CAP) { + cap_band = &pdev_cap->band[NL80211_BAND_5GHZ]; + memcpy(cap_band->eht_cap_mac_info, &caps->eht_cap_mac_info_5G, + sizeof(u32) * PSOC_HOST_MAX_MAC_SIZE); + memcpy(cap_band->eht_cap_phy_info, &caps->eht_cap_phy_info_5G, + sizeof(u32) * PSOC_HOST_MAX_PHY_SIZE); + cap_band->eht_mcs_20_only = caps->eht_supp_mcs_ext_5G[0]; + cap_band->eht_mcs_80 = caps->eht_supp_mcs_ext_5G[1]; + cap_band->eht_mcs_160 = caps->eht_supp_mcs_ext_5G[2]; + cap_band->eht_mcs_320 = caps->eht_supp_mcs_ext_5G[3]; + memcpy(&cap_band->eht_ppet, &caps->eht_ppet5G, + sizeof(struct ath12k_ppe_threshold)); + cap_band->eht_cap_info_internal = caps->eht_cap_info_internal; + + cap_band = &pdev_cap->band[NL80211_BAND_6GHZ]; + memcpy(cap_band->eht_cap_mac_info, &caps->eht_cap_mac_info_5G, + sizeof(u32) * PSOC_HOST_MAX_MAC_SIZE); + memcpy(cap_band->eht_cap_phy_info, &caps->eht_cap_phy_info_5G, + sizeof(u32) * PSOC_HOST_MAX_PHY_SIZE); + cap_band->eht_mcs_20_only = caps->eht_supp_mcs_ext_5G[0]; + cap_band->eht_mcs_80 = caps->eht_supp_mcs_ext_5G[1]; + cap_band->eht_mcs_160 = caps->eht_supp_mcs_ext_5G[2]; + cap_band->eht_mcs_320 = caps->eht_supp_mcs_ext_5G[3]; + memcpy(&cap_band->eht_ppet, &caps->eht_ppet5G, + sizeof(struct ath12k_ppe_threshold)); + cap_band->eht_cap_info_internal = caps->eht_cap_info_internal; + } + + pdev_cap->eml_cap = caps->eml_cap_u.eml_capability; + pdev_cap->mld_cap = caps->mld_cap_u.mld_capability; + + if (data) + pdev_cap->ru_punct_supp_bw = data->param.ru_punct_supp_bw; + + return 0; +} + +static int ath12k_wmi_tlv_mac_phy_caps_ext(struct ath12k_base *ab, u16 tag, + u16 len, const void *ptr, void *data) +{ + struct wmi_mac_phy_caps_ext *caps = (struct wmi_mac_phy_caps_ext *)ptr; + int i, ret; + + if (tag != WMI_TAG_MAC_PHY_CAPABILITIES_EXT) + return -EPROTO; + + for (i = 0; i < ab->num_radios; i++) { + if (ab->pdevs[i].pdev_id == caps->u.wmi_pdev_to_link_map.pdev_id) + break; + } + + if (i == ab->num_radios) + return -EINVAL; + + ret = ath12k_wmi_tlv_mac_phy_caps_ext_parse(ab, caps, &ab->pdevs[i], + data); + if (ret) { + ath12k_warn(ab, + "failed to extract mac phy caps ext, pdev_id:%d\n", + ab->pdevs[i].pdev_id); + return ret; + } + + return 0; +} + void ath12k_wmi_init_qcn9274(struct ath12k_base *ab, struct ath12k_wmi_resource_config_arg *config) { + struct ath12k_hw_group *ag = ab->ag; + + config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; + + if (ab->num_radios == 2) { + config->num_peers = TARGET_NUM_PEERS(DBS); + config->num_tids = TARGET_NUM_TIDS(DBS); + } else if (ab->num_radios == 3) { + config->num_peers = TARGET_NUM_PEERS(DBS_SBS); + config->num_tids = TARGET_NUM_TIDS(DBS_SBS); + } else { + /* Control should not reach here */ + config->num_peers = TARGET_NUM_PEERS(SINGLE); + config->num_tids = TARGET_NUM_TIDS(SINGLE); + } + config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; + config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; + config->num_peer_keys = TARGET_NUM_PEER_KEYS; + config->ast_skid_limit = TARGET_AST_SKID_LIMIT; + config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; + config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; + config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; + config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; + config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; + config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; + + if (test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) + config->rx_decap_mode = TARGET_DECAP_MODE_RAW; + else + config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; + + config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; + config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; + config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; + config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; + config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; + config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; + config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; + config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; + config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; + config->dma_burst_size = TARGET_DMA_BURST_SIZE; + config->rx_skip_defrag_timeout_dup_detection_check = + TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; + config->vow_config = TARGET_VOW_CONFIG; + config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; + config->num_msdu_desc = TARGET_NUM_MSDU_DESC; + config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; + config->rx_batchmode = TARGET_RX_BATCHMODE; + /* Indicates host supports peer map v3 and unmap v2 support */ + config->peer_map_unmap_version = 0x32; + config->twt_ap_pdev_count = ab->num_radios; + config->twt_ap_sta_count = 1000; + config->ema_max_vap_cnt = ab->num_radios; + config->ema_max_profile_period = TARGET_EMA_MAX_PROFILE_PERIOD; + config->beacon_tx_offload_max_vdev += config->ema_max_vap_cnt; + + if (test_bit(WMI_TLV_SERVICE_SAWF_LEVEL0, ab->wmi_ab.svc_map)) + config->sawf = true; + if (test_bit(WMI_TLV_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT, ab->wmi_ab.svc_map)) + config->dp_peer_meta_data_ver = TARGET_RX_PEER_METADATA_VER_V1B; + +} + +void ath12k_wmi_init_ipq5332(struct ath12k_base *ab, + struct ath12k_wmi_resource_config_arg *config) +{ + struct ath12k_hw_group *ag = ab->ag; + config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; if (ab->num_radios == 2) { @@ -182,7 +420,7 @@ config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; - if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) + if (test_bit(ATH12K_FLAG_RAW_MODE, &ag->dev_flags)) config->rx_decap_mode = TARGET_DECAP_MODE_RAW; else config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; @@ -208,8 +446,18 @@ config->peer_map_unmap_version = 0x32; config->twt_ap_pdev_count = ab->num_radios; config->twt_ap_sta_count = 1000; + config->ema_max_vap_cnt = ab->num_radios; + config->ema_max_profile_period = TARGET_EMA_MAX_PROFILE_PERIOD; + config->beacon_tx_offload_max_vdev += config->ema_max_vap_cnt; + + if (test_bit(WMI_TLV_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT, ab->wmi_ab.svc_map)) + config->dp_peer_meta_data_ver = TARGET_RX_PEER_METADATA_VER_V1B; + + if (test_bit(WMI_TLV_SERVICE_SAWF_LEVEL0, ab->wmi_ab.svc_map)) + config->sawf = true; } + void ath12k_wmi_init_wcn7850(struct ath12k_base *ab, struct ath12k_wmi_resource_config_arg *config) { @@ -254,6 +502,10 @@ config->num_multicast_filter_entries = 0x20; config->num_wow_filters = 0x16; config->num_keep_alive_pattern = 0; + + if (test_bit(WMI_TLV_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT, ab->wmi_ab.svc_map)) + config->dp_peer_meta_data_ver = TARGET_RX_PEER_METADATA_VER_V1A; + } #define PRIMAP(_hw_mode_) \ @@ -270,6 +522,69 @@ PRIMAP(WMI_HOST_HW_MODE_MAX), }; + +enum wmi_host_channel_width +ath12k_wmi_get_host_chan_width(u32 width) +{ + enum wmi_host_channel_width host_width; + + switch (width) { + case NL80211_CHAN_WIDTH_20_NOHT: + case NL80211_CHAN_WIDTH_20: + host_width = WMI_HOST_CHAN_WIDTH_20; + break; + case NL80211_CHAN_WIDTH_40: + host_width = WMI_HOST_CHAN_WIDTH_40; + break; + case NL80211_CHAN_WIDTH_80: + host_width = WMI_HOST_CHAN_WIDTH_80; + break; + case NL80211_CHAN_WIDTH_160: + host_width = WMI_HOST_CHAN_WIDTH_160; + break; + case NL80211_CHAN_WIDTH_80P80: + host_width = WMI_HOST_CHAN_WIDTH_80P80; + break; + case NL80211_CHAN_WIDTH_320: + host_width = WMI_HOST_CHAN_WIDTH_320; + break; + default: + host_width = WMI_HOST_CHAN_WIDTH_MAX; + break; + } + + return host_width; +} + +enum wmi_host_channel_width ath12k_wmi_get_host_chan_switch_width(u32 width) +{ + enum wmi_host_channel_width host_width; + + switch (width) { + case IEEE80211_STA_RX_BW_20: + host_width = WMI_HOST_CHAN_WIDTH_20; + break; + case IEEE80211_STA_RX_BW_40: + host_width = WMI_HOST_CHAN_WIDTH_40; + break; + case IEEE80211_STA_RX_BW_80: + host_width = WMI_HOST_CHAN_WIDTH_80; + break; + case IEEE80211_STA_RX_BW_160: + host_width = WMI_HOST_CHAN_WIDTH_160; + break; + case IEEE80211_STA_RX_BW_320: + host_width = WMI_HOST_CHAN_WIDTH_320; + break; + default: + ath12k_warn(NULL, "invalid bandwidth %d switching back to 20 MHz\n", width); + host_width = WMI_HOST_CHAN_WIDTH_20; + break; + } + + return host_width; +} + static int ath12k_wmi_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, int (*iter)(struct ath12k_base *ab, u16 tag, u16 len, @@ -281,6 +596,7 @@ u16 tlv_tag, tlv_len; int ret; + while (len > 0) { if (len < sizeof(*tlv)) { ath12k_err(ab, "wmi tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", @@ -390,21 +706,41 @@ { struct ath12k_wmi_base *wmi_sc = wmi->wmi_ab; int ret = -EOPNOTSUPP; + struct ath12k_base *ab = wmi_sc->ab; + + if (!(test_bit(ATH12K_FLAG_WMI_INIT_DONE, &wmi_sc->ab->dev_flags)) && + cmd_id != WMI_INIT_CMDID) + return -ESHUTDOWN; might_sleep(); + if (ab->hw_params->credit_flow) { wait_event_timeout(wmi_sc->tx_credits_wq, ({ ret = ath12k_wmi_cmd_send_nowait(wmi, skb, cmd_id); - if (ret && test_bit(ATH12K_FLAG_CRASH_FLUSH, &wmi_sc->ab->dev_flags)) + if (ret && test_bit(ATH12K_FLAG_CRASH_FLUSH, + &wmi_sc->ab->dev_flags)) ret = -ESHUTDOWN; - (ret != -EAGAIN); }), WMI_SEND_TIMEOUT_HZ); + } else { + wait_event_timeout(wmi->tx_ce_desc_wq, ({ + ret = ath12k_wmi_cmd_send_nowait(wmi, skb, cmd_id); + if (ret && test_bit(ATH12K_FLAG_CRASH_FLUSH, + &wmi_sc->ab->dev_flags)) + ret = -ESHUTDOWN; + + (ret != -ENOBUFS); + }), WMI_SEND_TIMEOUT_HZ); + } if (ret == -EAGAIN) ath12k_warn(wmi_sc->ab, "wmi command %d timeout\n", cmd_id); + if (ret == -ENOBUFS) + ath12k_warn(wmi_sc->ab, "ce desc not available for wmi command %d\n", + cmd_id); + return ret; } @@ -472,14 +808,18 @@ mac_caps = wmi_mac_phy_caps + phy_idx; pdev->pdev_id = le32_to_cpu(mac_caps->pdev_id); + pdev->hw_link_id = mac_caps->hw_link_id; pdev_cap->supported_bands |= le32_to_cpu(mac_caps->supported_bands); pdev_cap->ampdu_density = le32_to_cpu(mac_caps->ampdu_density); + pdev_cap->chainmask_table_id = mac_caps->chainmask_table_id; /* Take non-zero tx/rx chainmask. If tx/rx chainmask differs from * band to band for a single radio, need to see how this should be * handled. */ if (le32_to_cpu(mac_caps->supported_bands) & WMI_HOST_WLAN_2G_CAP) { + pdev_cap->vht_cap = le32_to_cpu(mac_caps->vht_cap_info_2g); + pdev_cap->vht_mcs = le32_to_cpu(mac_caps->vht_supp_mcs_2g); pdev_cap->tx_chain_mask = le32_to_cpu(mac_caps->tx_chain_mask_2g); pdev_cap->rx_chain_mask = le32_to_cpu(mac_caps->rx_chain_mask_2g); } else if (le32_to_cpu(mac_caps->supported_bands) & WMI_HOST_WLAN_5G_CAP) { @@ -488,6 +828,10 @@ pdev_cap->he_mcs = le32_to_cpu(mac_caps->he_supp_mcs_5g); pdev_cap->tx_chain_mask = le32_to_cpu(mac_caps->tx_chain_mask_5g); pdev_cap->rx_chain_mask = le32_to_cpu(mac_caps->rx_chain_mask_5g); + pdev_cap->nss_ratio_enabled = + WMI_NSS_RATIO_ENABLE_DISABLE_GET(mac_caps->nss_ratio); + pdev_cap->nss_ratio_info = + WMI_NSS_RATIO_INFO_GET(mac_caps->nss_ratio); } else { return -EINVAL; } @@ -567,6 +911,225 @@ return 0; } +static void ath12k_wmi_event_mlo_setup_complete(struct ath12k_base *ab, + struct sk_buff *skb) +{ + const void **tb; + const struct wmi_mlo_setup_complete_event_fixed_param *ev; + struct ath12k *ar = NULL; + struct ath12k_pdev *pdev; + int ret, i; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, + "failed to parse mlo setup complete event tlv %d\n", + ret); + return; + } + + ev = tb[WMI_TAG_MLO_SETUP_COMPLETE_EVENT]; + if (!ev) { + ath12k_warn(ab, "failed to fetch mlo setup complete event\n"); + kfree(tb); + return; + } + + if (ev->status) + ath12k_warn(ab, "mlo setup, pdev id %u, status %u\n", + ev->pdev_id, ev->status); + + if (ev->pdev_id > ab->num_radios) + goto skip_lookup; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (pdev && pdev->pdev_id == ev->pdev_id) { + ar = pdev->ar; + break; + } + } + +skip_lookup: + if (!ar) { + ath12k_warn(ab, "invalid pdev_id %d status %u in setup complete event\n", + ev->pdev_id, ev->status); + goto out; + } + + ar->mlo_setup_status = ev->status; + if (ab->hw_params->hal_ops->hal_get_tqm_scratch_reg) + ab->hw_params->hal_ops->hal_get_tqm_scratch_reg(ab, &ar->delta_tqm); + complete(&ar->mlo_setup_done); + +out: + kfree(tb); +} + +static void ath12k_wmi_event_teardown_complete(struct ath12k_base *ab, + struct sk_buff *skb) +{ + const void **tb; + const struct wmi_mlo_teardown_complete_fixed_param *ev; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_pdev *pdev; + struct ath12k *ar; + int ret, i, j; + bool complete_flag = true; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, + "failed to parse teardown complete event tlv %d\n", + ret); + return; + } + + ev = tb[WMI_TAG_MLO_TEARDOWN_COMPLETE]; + if (!ev) { + ath12k_warn(ab, "failed to fetch teardown complete event\n"); + kfree(tb); + return; + } + + if (ev->status) + ath12k_warn(ab, "mlo teardown, pdev id %u, status %u\n", + ev->pdev_id, ev->status); + + kfree(tb); + + ar = ath12k_mac_get_ar_by_pdev_id(ab, ev->pdev_id); + if (!ar) { + ath12k_warn(ab, "invalid pdev id in teardown complete ev %d", + ev->pdev_id); + return; + } + ar->mlo_complete_event = true; + + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + + for (j = 0; j < ab->num_radios; j++) { + pdev = &ab->pdevs[j]; + ar = pdev->ar; + + if (!ar->mlo_complete_event) + complete_flag = false; + } + } + + if (complete_flag && ag->recovery_mode == ATH12K_MLO_RECOVERY_MODE1) + complete(&ag->umac_reset_complete); +} + +static void ath12k_wmi_process_mvr_event(struct ath12k_base *ab, u32 *vdev_id_bm, + u32 num_vdev_bm) +{ + struct ath12k *ar = NULL; + struct ath12k_link_vif *arvif = NULL; + u32 bit_pos; + unsigned long vdev_bitmap; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi mvr resp num_vdev_bm %d vdev_id_bm[0]=0x%x vdev_id_bm[1]=0x%x\n", + num_vdev_bm, vdev_id_bm[0], + (num_vdev_bm == WMI_MVR_RESP_VDEV_BM_MAX_LEN ? + vdev_id_bm[1] : 0x00)); + + /* 31-0 bits processing */ + vdev_bitmap = vdev_id_bm[0]; + + for (bit_pos = 0; bit_pos < 32; bit_pos++) { + + if (!(vdev_bitmap & BIT(bit_pos))) + continue; + + arvif = ath12k_mac_get_arvif_by_vdev_id(ab, bit_pos); + if (!arvif) { + ar = ath12k_mac_get_ar_by_vdev_id(ab, bit_pos); + if (!(ar && bit_pos == ar->monitor_vdev_id)) { + ath12k_warn(ab, "wmi mvr resp for unknown vdev %d", bit_pos); + continue; + } + } else { + arvif->mvr_processing = false; + } + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi mvr vdev %d restarted\n", bit_pos); + } + + /* TODO: 63-32 bits processing + * Add support to parse bitmap once support for + * TARGET_NUM_VDEVS > 32 is added + */ + + if (arvif) + ar = arvif->ar; + + if (ar) + complete(&ar->mvr_complete); +} + +static int ath12k_wmi_tlv_mvr_event_parse(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_pdev_mvr_resp_event_parse *parse = data; + struct wmi_pdev_mvr_resp_event_fixed_param *fixed_param; + + switch(tag) { + case WMI_TAG_MULTIPLE_VDEV_RESTART_RESPONSE_EVENT: + fixed_param = (struct wmi_pdev_mvr_resp_event_fixed_param *)ptr; + + if (fixed_param->status) { + ath12k_warn(ab, "wmi mvr resp event status %u\n", + fixed_param->status); + return -EINVAL; + } + + memcpy(&parse->fixed_param, fixed_param, + sizeof(struct wmi_pdev_mvr_resp_event_fixed_param)); + break; + case WMI_TAG_ARRAY_UINT32: + if ((len > WMI_MVR_RESP_VDEV_BM_MAX_LEN_BYTES) || (len == 0)) { + ath12k_warn(ab, "wmi invalid vdev id len in mvr resp %u\n", + len); + return -EINVAL; + } + + parse->num_vdevs_bm = len / sizeof(u32); + memcpy(parse->vdev_id_bm, ptr, len); + break; + default: + break; + } + + return 0; +} + +static void ath12k_wmi_event_mvr_response(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct wmi_pdev_mvr_resp_event_parse parse = {}; + int ret; + + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_tlv_mvr_event_parse, + &parse); + if (ret) { + ath12k_warn(ab, "wmi failed to parse mvr response tlv %d\n", + ret); + return; + } + + ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi mvr resp for pdev %d\n", + parse.fixed_param.pdev_id); + + ath12k_wmi_process_mvr_event(ab, parse.vdev_id_bm, parse.num_vdevs_bm); +} + static int ath12k_pull_reg_cap_svc_rdy_ext(struct ath12k_wmi_pdev *wmi_handle, const struct ath12k_wmi_soc_hal_reg_caps_params *reg_caps, @@ -720,18 +1283,25 @@ } int ath12k_wmi_mgmt_send(struct ath12k *ar, u32 vdev_id, u32 buf_id, - struct sk_buff *frame) + struct sk_buff *frame, bool link_agnostic) { struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_mgmt_send_cmd *cmd; + struct wmi_mlo_mgmt_send_params *ml_params; struct wmi_tlv *frame_tlv; struct sk_buff *skb; u32 buf_len; int ret, len; + void *ptr; + struct wmi_tlv *tlv; buf_len = min_t(int, frame->len, WMI_MGMT_SEND_DOWNLD_LEN); - len = sizeof(*cmd) + sizeof(*frame_tlv) + roundup(buf_len, 4); + len = sizeof(*cmd) + sizeof(*frame_tlv) + roundup(buf_len, sizeof(u32)); + + if (link_agnostic) + len += sizeof(struct wmi_mgmt_send_params) + + TLV_HDR_SIZE + sizeof(*ml_params); skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); if (!skb) @@ -750,10 +1320,34 @@ cmd->tx_params_valid = 0; frame_tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd)); - frame_tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, buf_len); + frame_tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, roundup(buf_len, sizeof(u32))); memcpy(frame_tlv->value, frame->data, buf_len); + if (!link_agnostic) + goto send; + + ptr = skb->data + sizeof(*cmd) + sizeof(*frame_tlv) + roundup(buf_len, sizeof(u32)); + + tlv = ptr; + + /* Tx params not used currently */ + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_TX_SEND_PARAMS) | + FIELD_PREP(WMI_TLV_LEN, sizeof(struct wmi_mgmt_send_params) - TLV_HDR_SIZE); + ptr += sizeof(struct wmi_mgmt_send_params); + + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_params)); + ptr += TLV_HDR_SIZE; + + ml_params = ptr; + ml_params->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_TX_SEND_PARAMS) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_params) - TLV_HDR_SIZE); + + ml_params->hw_link_id = WMI_MLO_MGMT_TID; + +send: ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MGMT_TX_SEND_CMDID); if (ret) { ath12k_warn(ar->ab, @@ -764,23 +1358,125 @@ return ret; } +static u32 ath12k_wmi_mgmt_get_freq(struct ath12k *ar, + struct ieee80211_tx_info *info) +{ + u32 freq = 0; + + if (ar->scan.is_roc && + (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)) + freq = ar->scan.roc_freq; + + return freq; +} + +/* For Big Endian Host, Copy Engine byte_swap is enabled + * When Copy Engine does byte_swap, need to byte swap again for the + * Host to get/put buffer content in the correct byte order + */ +void ath12k_ce_byte_swap(void *mem, u32 len) +{ + int i; + + if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { + if (!mem) + return; + + for (i = 0; i < (len / 4); i++) { + *(u32 *)mem = swab32(*(u32 *)mem); + mem += 4; + } + } +} + +/* Send off-channel managemnt frame to firmware. when driver receive a + * packet with off channel tx flag enabled. This API will send the + * packet to firmware with WMI command WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD + * for off-chan tx. + */ +int ath12k_wmi_offchan_mgmt_send(struct ath12k *ar, u32 vdev_id, u32 buf_id, + struct sk_buff *frame) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(frame); + struct wmi_mgmt_send_cmd *cmd; + struct wmi_tlv *frame_tlv; + struct sk_buff *skb; + u32 buf_len, buf_len_padded; + int ret, len; + void *ptr; + struct wmi_tlv *tlv; + + buf_len = min(frame->len, (unsigned int)WMI_MGMT_SEND_DOWNLD_LEN); + buf_len_padded = roundup(buf_len, sizeof(u32)); + + len = sizeof(*cmd) + sizeof(*frame_tlv) + buf_len_padded + + sizeof(struct wmi_mgmt_send_params); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + ptr = skb->data; + cmd = ptr; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, + sizeof(*cmd)); + cmd->vdev_id = cpu_to_le32(vdev_id); + cmd->desc_id = cpu_to_le32(buf_id); + cmd->chanfreq = cpu_to_le32(ath12k_wmi_mgmt_get_freq(ar, info)); + cmd->paddr_lo = cpu_to_le32(lower_32_bits(ATH12K_SKB_CB(frame)->paddr)); + cmd->paddr_hi = cpu_to_le32(upper_32_bits(ATH12K_SKB_CB(frame)->paddr)); + cmd->frame_len = cpu_to_le32(frame->len); + cmd->buf_len = cpu_to_le32(buf_len); + cmd->tx_params_valid = 1; + ptr += sizeof(*cmd); + + frame_tlv = ptr; + frame_tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, buf_len_padded); + ptr += sizeof(*frame_tlv); + + memcpy(ptr, frame->data, buf_len); + ath12k_ce_byte_swap(ptr, buf_len); + ptr += buf_len_padded; + + tlv = ptr; + /* Tx params not used currently */ + tlv->header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_TX_SEND_PARAMS, + sizeof(struct wmi_mgmt_send_params)); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_OFFCHAN_DATA_TX_SEND_CMDID); + + if (ret) { + ath12k_warn(ar->ab, + "failed to submit WMI_OFFCHAN_DATA_TX_SEND_CMDID cmd\n"); + dev_kfree_skb(skb); + } + + return ret; +} + int ath12k_wmi_vdev_create(struct ath12k *ar, u8 *macaddr, struct ath12k_wmi_vdev_create_arg *args) { struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_vdev_create_cmd *cmd; + struct wmi_vdev_create_mlo_params *ml_params; struct sk_buff *skb; struct ath12k_wmi_vdev_txrx_streams_params *txrx_streams; struct wmi_tlv *tlv; int ret, len; void *ptr; + bool is_ml_vdev; + + is_ml_vdev = is_valid_ether_addr(args->mld_addr); /* It can be optimized my sending tx/rx chain configuration * only for supported bands instead of always sending it for * both the bands. */ len = sizeof(*cmd) + TLV_HDR_SIZE + - (WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams)); + (WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams)) + + (is_ml_vdev ? TLV_HDR_SIZE + sizeof(*ml_params) : 0); skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); if (!skb) @@ -796,6 +1492,8 @@ cmd->num_cfg_txrx_streams = cpu_to_le32(WMI_NUM_SUPPORTED_BAND_MAX); cmd->pdev_id = cpu_to_le32(args->pdev_id); cmd->vdev_stats_id = cpu_to_le32(args->if_stats_id); + cmd->mbssid_flags = cpu_to_le32(args->mbssid_flags); + cmd->mbssid_tx_vdev_id = cpu_to_le32(args->mbssid_tx_vdev_id); ether_addr_copy(cmd->vdev_macaddr.addr, macaddr); ptr = skb->data + sizeof(*cmd); @@ -824,6 +1522,23 @@ txrx_streams->supported_rx_streams = args->chains[NL80211_BAND_5GHZ].rx; + if (is_ml_vdev) { + ptr = skb->data + sizeof(*cmd) + TLV_HDR_SIZE + + (WMI_NUM_SUPPORTED_BAND_MAX * sizeof(*txrx_streams)); + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_params)); + + ptr += TLV_HDR_SIZE; + ml_params = ptr; + + ml_params->tlv_header = + FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_VDEV_CREATE_PARAMS) | + FIELD_PREP(WMI_TLV_LEN, sizeof(ml_params->mld_macaddr.addr)); + + ether_addr_copy(ml_params->mld_macaddr.addr, args->mld_addr); + } + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev create: id %d type %d subtype %d macaddr %pM pdevid %d\n", args->if_id, args->type, args->subtype, @@ -855,7 +1570,8 @@ sizeof(*cmd)); cmd->vdev_id = cpu_to_le32(vdev_id); - ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev delete id %d\n", vdev_id); + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev delete id %d num_peers : %d\n", + vdev_id, ar->num_peers); ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_DELETE_CMDID); if (ret) { @@ -883,7 +1599,7 @@ sizeof(*cmd)); cmd->vdev_id = cpu_to_le32(vdev_id); - ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev stop id 0x%x\n", vdev_id); + ath12k_dbg(ar->ab, ATH12K_DBG_SET(WMI, L1), "WMI vdev stop id 0x%x\n", vdev_id); ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_STOP_CMDID); if (ret) { @@ -911,55 +1627,173 @@ sizeof(*cmd)); cmd->vdev_id = cpu_to_le32(vdev_id); - ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev down id 0x%x\n", vdev_id); + ath12k_dbg(ar->ab, ATH12K_DBG_SET(WMI, L1), "WMI vdev down id 0x%x\n", vdev_id); ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_DOWN_CMDID); if (ret) { - ath12k_warn(ar->ab, "failed to submit WMI_VDEV_DOWN cmd\n"); + ath12k_warn(ar->ab, "failed to submit WMI_VDEV_DOWN cmd vdev id : %d\n", + vdev_id); dev_kfree_skb(skb); } return ret; } +static inline bool +ath12k_wmi_check_device_present(u32 width_device, + u32 center_freq_device, + u32 center_freq_oper) +{ + return (center_freq_device && width_device && + center_freq_device != center_freq_oper); +} + +static u32 ath12k_wmi_set_ru_punc_bitmap_device(u32 oper_freq, + enum nl80211_chan_width width_device, + u32 device_freq, + u32 oper_ru_punct_bitmap) +{ + u32 device_bitmap = oper_ru_punct_bitmap; + + if (oper_freq == device_freq || oper_freq < device_freq) + return device_bitmap; + + switch (width_device) { + case NL80211_CHAN_WIDTH_160: + if (oper_freq > device_freq) + device_bitmap = (oper_ru_punct_bitmap << 4) | 0x0000FF0F; + break; + case NL80211_CHAN_WIDTH_320: + if (oper_freq > device_freq) + device_bitmap = (oper_ru_punct_bitmap << 8) | 0x000000FF; + break; + default: + return device_bitmap; + } + + return device_bitmap; +} + +static void ath12k_wmi_set_wmi_channel_device(struct ath12k_wmi_channel_params *chan_device, + struct wmi_channel_arg *channel, + u32 cf_device, u32 width_device) +{ + enum wmi_phy_mode mode_device; + + memset(chan_device, 0, sizeof(*chan_device)); + + chan_device->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHANNEL, + sizeof(*chan_device)); + chan_device->mhz = cpu_to_le32(channel->freq); + chan_device->band_center_freq1 = cpu_to_le32(cf_device); + + if (width_device == NL80211_CHAN_WIDTH_320) { + mode_device = MODE_11BE_EHT320; + if (channel->freq > chan_device->band_center_freq1) + chan_device->band_center_freq1 = cf_device + 80; + else + chan_device->band_center_freq1 = cf_device - 80; + chan_device->band_center_freq2 = cf_device; + } else if (width_device == NL80211_CHAN_WIDTH_160) { + mode_device = MODE_11BE_EHT160; + if (channel->freq > chan_device->band_center_freq1) + chan_device->band_center_freq1 = cf_device + 40; + else + chan_device->band_center_freq1 = cf_device - 40; + chan_device->band_center_freq2 = cf_device; + } else if (width_device == NL80211_CHAN_WIDTH_80) { + mode_device = MODE_11BE_EHT80; + } else if (width_device == NL80211_CHAN_WIDTH_40) { + mode_device = MODE_11BE_EHT40; + } else { + mode_device = MODE_UNKNOWN; + } + + chan_device->info |= le32_encode_bits(mode_device, WMI_CHAN_INFO_MODE); + if (channel->passive) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_PASSIVE); + if (channel->allow_ibss) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_ADHOC_ALLOWED); + if (channel->allow_ht) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HT); + if (channel->allow_vht) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_VHT); + if (channel->allow_he) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HE); + if (channel->ht40plus) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_HT40_PLUS); + if (channel->chan_radar) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_DFS); + if (channel->freq2_radar) + chan_device->info |= cpu_to_le32(WMI_CHAN_INFO_DFS_FREQ2); + + chan_device->reg_info_1 = le32_encode_bits(channel->max_power, + WMI_CHAN_REG_INFO1_MAX_PWR) | + le32_encode_bits(channel->max_reg_power, + WMI_CHAN_REG_INFO1_MAX_REG_PWR); + + chan_device->reg_info_2 = le32_encode_bits(channel->max_antenna_gain, + WMI_CHAN_REG_INFO2_ANT_MAX) | + le32_encode_bits(channel->max_power, + WMI_CHAN_REG_INFO2_MAX_TX_PWR); +} + static void ath12k_wmi_put_wmi_channel(struct ath12k_wmi_channel_params *chan, - struct wmi_vdev_start_req_arg *arg) + struct wmi_channel_arg chan_arg) { + u32 center_freq1 = chan_arg.band_center_freq1; memset(chan, 0, sizeof(*chan)); - chan->mhz = cpu_to_le32(arg->freq); - chan->band_center_freq1 = cpu_to_le32(arg->band_center_freq1); - if (arg->mode == MODE_11AC_VHT80_80) - chan->band_center_freq2 = cpu_to_le32(arg->band_center_freq2); + chan->mhz = chan_arg.freq; + chan->band_center_freq1 = chan_arg.band_center_freq1; + if (chan_arg.mode == MODE_11BE_EHT320) { + if (chan_arg.freq > chan_arg.band_center_freq1) + chan->band_center_freq1 = center_freq1 + 80; else + chan->band_center_freq1 = center_freq1 - 80; + + chan->band_center_freq2 = chan_arg.band_center_freq1; + + } else if (chan_arg.mode == MODE_11BE_EHT160) { + if (chan_arg.freq > chan_arg.band_center_freq1) + chan->band_center_freq1 = center_freq1 + 40; + else + chan->band_center_freq1 = center_freq1 - 40; + + chan->band_center_freq2 = chan_arg.band_center_freq1; + + } else if (chan_arg.mode == MODE_11BE_EHT80_80) { + chan->band_center_freq2 = chan_arg.band_center_freq2; + }else{ chan->band_center_freq2 = 0; + } - chan->info |= le32_encode_bits(arg->mode, WMI_CHAN_INFO_MODE); - if (arg->passive) + chan->info |= u32_encode_bits(chan_arg.mode, WMI_CHAN_INFO_MODE); + if (chan_arg.passive) chan->info |= cpu_to_le32(WMI_CHAN_INFO_PASSIVE); - if (arg->allow_ibss) + if (chan_arg.allow_ibss) chan->info |= cpu_to_le32(WMI_CHAN_INFO_ADHOC_ALLOWED); - if (arg->allow_ht) + if (chan_arg.allow_ht) chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HT); - if (arg->allow_vht) + if (chan_arg.allow_vht) chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_VHT); - if (arg->allow_he) + if (chan_arg.allow_he) chan->info |= cpu_to_le32(WMI_CHAN_INFO_ALLOW_HE); - if (arg->ht40plus) + if (chan_arg.ht40plus) chan->info |= cpu_to_le32(WMI_CHAN_INFO_HT40_PLUS); - if (arg->chan_radar) + if (chan_arg.chan_radar) chan->info |= cpu_to_le32(WMI_CHAN_INFO_DFS); - if (arg->freq2_radar) + if (chan_arg.freq2_radar) chan->info |= cpu_to_le32(WMI_CHAN_INFO_DFS_FREQ2); - chan->reg_info_1 = le32_encode_bits(arg->max_power, + chan->reg_info_1 = le32_encode_bits(chan_arg.max_power, WMI_CHAN_REG_INFO1_MAX_PWR) | - le32_encode_bits(arg->max_reg_power, + le32_encode_bits(chan_arg.max_reg_power, WMI_CHAN_REG_INFO1_MAX_REG_PWR); - chan->reg_info_2 = le32_encode_bits(arg->max_antenna_gain, + chan->reg_info_2 = le32_encode_bits(chan_arg.max_antenna_gain, WMI_CHAN_REG_INFO2_ANT_MAX) | - le32_encode_bits(arg->max_power, WMI_CHAN_REG_INFO2_MAX_TX_PWR); + le32_encode_bits(chan_arg.max_power, WMI_CHAN_REG_INFO2_MAX_TX_PWR); } int ath12k_wmi_vdev_start(struct ath12k *ar, struct wmi_vdev_start_req_arg *arg, @@ -967,16 +1801,32 @@ { struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_vdev_start_request_cmd *cmd; + struct wmi_vdev_start_mlo_params *ml_params; + struct wmi_partner_link_info *partner_info; struct sk_buff *skb; struct ath12k_wmi_channel_params *chan; struct wmi_tlv *tlv; + struct ath12k_wmi_channel_params *chan_device; void *ptr; - int ret, len; + int ret, len, ml_arg_size = 0; + u8 i; + struct ath12k_hw_group *ag = ar->ab->ag; + bool device_params_present = false; if (WARN_ON(arg->ssid_len > sizeof(cmd->ssid.ssid))) return -EINVAL; - len = sizeof(*cmd) + sizeof(*chan) + TLV_HDR_SIZE; + if (!restart && arg->ml.enabled) + ml_arg_size = TLV_HDR_SIZE + sizeof(*ml_params) + + TLV_HDR_SIZE + (arg->ml.num_partner_links * sizeof(*partner_info)); + + len = sizeof(*cmd) + sizeof(*chan) + TLV_HDR_SIZE + ml_arg_size; + + device_params_present = ath12k_wmi_check_device_present(arg->width_device, + arg->center_freq_device, + arg->channel.band_center_freq1); + if (device_params_present) + len += TLV_HDR_SIZE + sizeof(*chan_device); skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); if (!skb) @@ -995,6 +1845,16 @@ cmd->cac_duration_ms = cpu_to_le32(arg->cac_duration_ms); cmd->regdomain = cpu_to_le32(arg->regdomain); cmd->he_ops = cpu_to_le32(arg->he_ops); + cmd->mbssid_flags = cpu_to_le32(arg->mbssid_flags); + cmd->mbssid_tx_vdev_id = cpu_to_le32(arg->mbssid_tx_vdev_id); + + if (device_params_present) { + arg->ru_punct_bitmap = ath12k_wmi_set_ru_punc_bitmap_device(arg->channel.freq, + arg->width_device, + arg->center_freq_device, + arg->ru_punct_bitmap); + } + cmd->ru_punct_bitmap = cpu_to_le32(arg->ru_punct_bitmap); if (!restart) { if (arg->ssid) { @@ -1009,10 +1869,13 @@ cmd->flags |= cpu_to_le32(WMI_VDEV_START_LDPC_RX_ENABLED); + if (test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ag->dev_flags)) + cmd->flags |= cpu_to_le32(WMI_VDEV_START_HW_ENCRYPTION_DISABLED); + ptr = skb->data + sizeof(*cmd); chan = ptr; - ath12k_wmi_put_wmi_channel(chan, arg); + ath12k_wmi_put_wmi_channel(chan, arg->channel); chan->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHANNEL, sizeof(*chan)); @@ -1024,12 +1887,74 @@ /* Note: This is a nested TLV containing: * [wmi_tlv][wmi_p2p_noa_descriptor][wmi_tlv].. */ - ptr += sizeof(*tlv); + if (ml_arg_size) { + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_params)); + ptr += TLV_HDR_SIZE; + + ml_params = ptr; + + ml_params->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_VDEV_START_PARAMS) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_params) - TLV_HDR_SIZE); + + ml_params->flags = FIELD_PREP(ATH12K_WMI_FLAG_MLO_ENABLED, + arg->ml.enabled) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_ASSOC_LINK, + arg->ml.assoc_link) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_MCAST_VDEV, + arg->ml.mcast_link) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_LINK_ADD, + arg->ml.link_add); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "vdev %d start ml flags 0x%x\n", + arg->vdev_id, ml_params->flags); + + ptr += sizeof(*ml_params); + + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, arg->ml.num_partner_links * + sizeof(*partner_info)); + ptr += TLV_HDR_SIZE; + + partner_info = ptr; + + for (i = 0; i < arg->ml.num_partner_links; i++) { + partner_info->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_MLO_PARTNER_LINK_PARAMS) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*partner_info) - + TLV_HDR_SIZE); + + partner_info->vdev_id = arg->ml.partner_info[i].vdev_id; + partner_info->hw_link_id = arg->ml.partner_info[i].hw_link_id; + ether_addr_copy(partner_info->vdev_addr.addr, arg->ml.partner_info[i].addr); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "partner vdev %d hw_link_id %d macaddr%pM\n", + partner_info->vdev_id, partner_info->hw_link_id, + partner_info->vdev_addr.addr); + partner_info++; + } + } + + if (device_params_present) { + tlv = ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, + sizeof(*chan_device)); + ptr += TLV_HDR_SIZE; + + chan_device = ptr; + ath12k_wmi_set_wmi_channel_device(chan_device, &arg->channel, + arg->center_freq_device, + arg->width_device); + ptr += sizeof(*chan_device); + } + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "vdev %s id 0x%x freq 0x%x mode 0x%x\n", restart ? "restart" : "start", arg->vdev_id, - arg->freq, arg->mode); + arg->channel.freq, arg->channel.mode); if (restart) ret = ath12k_wmi_cmd_send(wmi, skb, @@ -1046,7 +1971,7 @@ return ret; } -int ath12k_wmi_vdev_up(struct ath12k *ar, u32 vdev_id, u32 aid, const u8 *bssid) +int ath12k_wmi_vdev_up(struct ath12k *ar, struct vdev_up_params *params) { struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_vdev_up_cmd *cmd; @@ -1061,14 +1986,17 @@ cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_UP_CMD, sizeof(*cmd)); - cmd->vdev_id = cpu_to_le32(vdev_id); - cmd->vdev_assoc_id = cpu_to_le32(aid); - - ether_addr_copy(cmd->vdev_bssid.addr, bssid); + cmd->vdev_id = cpu_to_le32(params->vdev_id); + cmd->vdev_assoc_id = cpu_to_le16(params->aid); + ether_addr_copy(cmd->vdev_bssid.addr, params->bssid); + cmd->profile_idx = cpu_to_le32(params->profile_idx); + cmd->profile_count = cpu_to_le32(params->profile_count); + if (params->tx_bssid) + ether_addr_copy(cmd->tx_vdev_bssid.addr, params->tx_bssid); ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI mgmt vdev up id 0x%x assoc id %d bssid %pM\n", - vdev_id, aid, bssid); + params->vdev_id, params->aid, params->bssid); ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_UP_CMDID); if (ret) { @@ -1085,9 +2013,14 @@ struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_peer_create_cmd *cmd; struct sk_buff *skb; - int ret; + int ret, len; + struct wmi_peer_create_mlo_params *ml_param; + void *ptr; + struct wmi_tlv *tlv; - skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + len = sizeof(*cmd) + TLV_HDR_SIZE + sizeof(*ml_param); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); if (!skb) return -ENOMEM; @@ -1099,9 +2032,22 @@ cmd->peer_type = cpu_to_le32(arg->peer_type); cmd->vdev_id = cpu_to_le32(arg->vdev_id); - ath12k_dbg(ar->ab, ATH12K_DBG_WMI, - "WMI peer create vdev_id %d peer_addr %pM\n", - arg->vdev_id, arg->peer_addr); + ptr = skb->data + sizeof(*cmd); + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_param)); + ptr += TLV_HDR_SIZE; + + ml_param = ptr; + ml_param->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_PEER_CREATE_PARAMS) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_param) - TLV_HDR_SIZE); + + ml_param->flags = FIELD_PREP(ATH12K_WMI_FLAG_MLO_ENABLED, arg->ml_enabled); + + + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, + "WMI peer create vdev_id %d peer_addr %pM ml_enabled %d\n", + arg->vdev_id, arg->peer_addr, arg->ml_enabled); ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_CREATE_CMDID); if (ret) { @@ -1131,13 +2077,162 @@ ether_addr_copy(cmd->peer_macaddr.addr, peer_addr); cmd->vdev_id = cpu_to_le32(vdev_id); - ath12k_dbg(ar->ab, ATH12K_DBG_WMI, - "WMI peer delete vdev_id %d peer_addr %pM\n", - vdev_id, peer_addr); + ath12k_dbg(ar->ab, ATH12K_DBG_PEER, + "WMI peer delete vdev_id %d peer_addr %pM num_peer : %d\n", + vdev_id, peer_addr, ar->num_peers); ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_DELETE_CMDID); if (ret) { - ath12k_warn(ar->ab, "failed to send WMI_PEER_DELETE cmd\n"); + ath12k_warn(ar->ab, "failed to send WMI_PEER_DELETE cmd" + " peer_addr %pM num_peer : %d\n", + peer_addr, ar->num_peers); + dev_kfree_skb(skb); + } + + return ret; +} + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +int ath12k_wmi_config_peer_ppeds_routing(struct ath12k *ar, + const u8 *peer_addr, u8 vdev_id, + u32 service_code, u32 priority_valid, + u32 src_info, bool ppe_routing_enable) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct sk_buff *skb; + struct wmi_peer_config_ppeds_cmd *cmd; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd =(struct wmi_peer_config_ppeds_cmd *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_CONFIG_PPEDS_ROUTING, + sizeof(*cmd)); + + ether_addr_copy(cmd->peer_macaddr.addr, peer_addr); + cmd->vdev_id = cpu_to_le32(vdev_id); + cmd->ppe_routing_enable = cpu_to_le32(ppe_routing_enable); + cmd->service_code = cpu_to_le32(service_code); + cmd->priority_valid = cpu_to_le32(priority_valid); + cmd->src_info = cpu_to_le32(src_info); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_CONFIG_PPE_DS_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_PEER_CONFIG_PPE_DS cmd" + " peer_addr %pM num_peer : %d\n", + peer_addr, ar->num_peers); + dev_kfree_skb(skb); + } + ath12k_dbg(ar->ab, ATH12K_DBG_PPE, + "ppe ds routing cmd peer_addr %pM vdev_id %d service_code %d " \ + "priority_valid %d src_info %d ppe_routing_enable %d \n", + peer_addr, vdev_id, service_code, priority_valid, + src_info, ppe_routing_enable); + + return ret; +} + +int +ath12k_wmi_send_vdev_set_intra_bss_cmd(struct ath12k *ar, + u32 vdev_id, u32 enable) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_vdev_set_intra_bss_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(struct ath12k_vdev_set_intra_bss_cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct ath12k_vdev_set_intra_bss_cmd *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_VDEV_SET_INTRA_BSS_PARAMS, + sizeof(*cmd)); + cmd->vdev_id = vdev_id; + cmd->enable = enable; + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_SET_INTRA_BSS_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to send WMI_VDEV_SET_INTRA_BSS_CMDID\n"); + dev_kfree_skb(skb); + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI vdev id 0x%x set inra bss %s\n", + vdev_id, enable?"enable":"disable"); + + return ret; +} + +int ath12k_wmi_set_peer_intra_bss_cmd(struct ath12k *ar, u32 vdev_id, const u8 *peer_addr, + u32 enable) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_peer_set_intra_bss_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_peer_set_intra_bss_param_cmd *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_SET_INTRA_BSS_PARAMS, + sizeof(*cmd)); + ether_addr_copy(cmd->peer_macaddr.addr, peer_addr); + cmd->vdev_id = cpu_to_le32(vdev_id); + cmd->enable = cpu_to_le32(enable); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_SET_INTRA_BSS_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_PEER_SET_INTRA_BSS_CMD\n"); + dev_kfree_skb(skb); + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI vdev %d peer 0x%pM set intra_bss %s\n", + vdev_id, peer_addr, enable ? "enable" : "disable"); + + return ret; +} +#endif /* CONFIG_ATH12K_PPE_DS_SUPPORT */ + +int ath12k_wmi_send_pdev_pkt_route(struct ath12k *ar, + struct ath12k_wmi_pkt_route_param *param) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_pdev_pkt_route_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_pkt_route_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + + cmd->pdev_id = ar->pdev->pdev_id; + cmd->opcode = param->opcode; + cmd->route_type_bmap = param->route_type_bmap; + cmd->dst_ring = param->dst_ring; + cmd->meta_data = param->meta_data; + cmd->dst_ring_handler = param->dst_ring_handler; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "CCE PPE WMI pdev pkt route opcode %d route_bmap %d dst_ring %d meta_data %d" \ + "dst_ring_handler %d\n", param->opcode, param->route_type_bmap, + param->dst_ring, param->meta_data, param->dst_ring_handler); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_UPDATE_PKT_ROUTING_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to send WMI_PDEV_UPDATE_PKT_ROUTING cmd\n"); dev_kfree_skb(skb); } @@ -1331,7 +2426,7 @@ } int ath12k_wmi_pdev_set_param(struct ath12k *ar, u32 param_id, - u32 param_value, u8 pdev_id) + s32 param_value, u8 pdev_id) { struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_pdev_set_param_cmd *cmd; @@ -1349,7 +2444,7 @@ cmd->param_id = cpu_to_le32(param_id); cmd->param_value = cpu_to_le32(param_value); - ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + ath12k_dbg(ar->ab, ATH12K_DBG_SET(WMI, L2), "WMI pdev set param %d pdev id %d value %d\n", param_id, pdev_id, param_value); @@ -1474,6 +2569,7 @@ cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, sizeof(*cmd)); cmd->req_type = cpu_to_le32(type); + cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI bss chan info req type %d\n", type); @@ -1557,12 +2653,12 @@ return ret; } -int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms) +int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms, bool nowait) { struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_force_fw_hang_cmd *cmd; struct sk_buff *skb; - int ret, len; + int ret = 0, len; len = sizeof(*cmd); @@ -1577,8 +2673,10 @@ cmd->type = cpu_to_le32(type); cmd->delay_time_ms = cpu_to_le32(delay_time_ms); + if (nowait) + ath12k_wmi_cmd_send_nowait(wmi, skb, WMI_FORCE_FW_HANG_CMDID); + else ret = ath12k_wmi_cmd_send(wmi, skb, WMI_FORCE_FW_HANG_CMDID); - if (ret) { ath12k_warn(ar->ab, "Failed to send WMI_FORCE_FW_HANG_CMDID"); dev_kfree_skb(skb); @@ -1620,6 +2718,142 @@ return ret; } +int ath12k_wmi_send_stats_request_cmd(struct ath12k *ar, u32 stats_id, + u32 vdev_id, u32 pdev_id) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_request_stats_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_request_stats_cmd *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_REQUEST_STATS_CMD, + sizeof(*cmd)); + + cmd->stats_id = cpu_to_le32(stats_id); + cmd->vdev_id = cpu_to_le32(vdev_id); + cmd->pdev_id = cpu_to_le32(pdev_id); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_REQUEST_STATS_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_REQUEST_STATS cmd\n"); + dev_kfree_skb(skb); + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI request stats 0x%x vdev id %d pdev id %d\n", + stats_id, vdev_id, pdev_id); + + return ret; +} + +static void ath12k_wmi_copy_coex_config(struct ath12k *ar, struct wmi_coex_config_cmd *cmd, + struct coex_config_arg *coex_config) +{ + switch (coex_config->config_type) { + case WMI_COEX_CONFIG_BTC_ENABLE: + cmd->coex_enable = coex_config->coex_enable; + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI coex config type %u vdev id %d" + " coex_enable %u\n", + coex_config->config_type, + coex_config->vdev_id, + coex_config->coex_enable); + break; + case WMI_COEX_CONFIG_WLAN_PKT_PRIORITY: + cmd->wlan_pkt_type = coex_config->wlan_pkt_type; + cmd->wlan_pkt_weight = coex_config->wlan_pkt_weight; + cmd->bt_pkt_weight = coex_config->bt_pkt_weight; + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI coex config type %u vdev id %d" + " wlan pkt type 0x%x wlan pkt weight %u" + " bt pkt weight %u\n", + coex_config->config_type, + coex_config->vdev_id, + coex_config->wlan_pkt_type, + coex_config->wlan_pkt_weight, + coex_config->bt_pkt_weight); + break; + case WMI_COEX_CONFIG_PTA_INTERFACE: + cmd->pta_num = coex_config->pta_num; + cmd->coex_mode = coex_config->coex_mode; + cmd->bt_txrx_time = coex_config->bt_txrx_time; + cmd->bt_priority_time = coex_config->bt_priority_time; + cmd->pta_algorithm = coex_config->pta_algorithm; + cmd->pta_priority = coex_config->pta_priority; + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI coex config type %u vdev id %d" + " pta num %u coex mode 0x%x" + " bt_txrx_time 0x%x" + " bt_priority_time 0x%x pta alogrithm 0x%x" + " pta priority 0x%x\n", + coex_config->config_type, + coex_config->vdev_id, + coex_config->pta_num, + coex_config->coex_mode, + coex_config->bt_txrx_time, + coex_config->bt_priority_time, + coex_config->pta_algorithm, + coex_config->pta_priority); + break; + case WMI_COEX_CONFIG_AP_TDM: + cmd->duty_cycle = coex_config->duty_cycle; + cmd->wlan_duration = coex_config->wlan_duration; + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI coex config type %u vdev id %d" + " duty_cycle %u wlan_duration %u\n", + coex_config->config_type, + coex_config->vdev_id, + coex_config->duty_cycle, + coex_config->wlan_duration); + break; + case WMI_COEX_CONFIG_FORCED_ALGO: + cmd->coex_algo = coex_config->coex_algo; + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI coex config type %u vdev id %d" + " coex_algorithm %u\n", + coex_config->config_type, + coex_config->vdev_id, + coex_config->coex_algo); + break; + default: + break; + } +} + +int ath12k_send_coex_config_cmd(struct ath12k *ar, + struct coex_config_arg *coex_config) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_coex_config_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_coex_config_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_COEX_CONFIG_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + + cmd->vdev_id = coex_config->vdev_id; + cmd->config_type = coex_config->config_type; + ath12k_wmi_copy_coex_config(ar, cmd, coex_config); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_COEX_CONFIG_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_COEX_CONFIG_CMD cmd\n"); + dev_kfree_skb(skb); + } + + return ret; +} + int ath12k_wmi_send_pdev_temperature_cmd(struct ath12k *ar) { struct ath12k_wmi_pdev *wmi = ar->wmi; @@ -1681,9 +2915,167 @@ return ret; } +static void ath12k_wmi_bcn_fill_ml_info(struct ath12k_link_vif *arvif, + struct wmi_bcn_tmpl_ml_info *ml_info, + u64 non_tx_ml_vdev_bmap) +{ + struct ath12k_base *ab = arvif->ar->ab; + struct ieee80211_bss_conf *link_conf; + /* u32 vdev_id = arvif->vdev_id; */ + unsigned long vdev_map_cat1 = 0; + unsigned long vdev_map_cat2 = 0; + + rcu_read_lock(); + + link_conf = ath12k_get_link_bss_conf(arvif); + if (!link_conf) { + rcu_read_unlock(); + goto err_fill_ml_info; + } + + rcu_read_unlock(); + + ml_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_TMPL_ML_INFO_CMD, + sizeof(*ml_info)); + ml_info->hw_link_id = cpu_to_le32(arvif->ar->pdev->hw_link_id); + + /* if this is cu cat 1 for tx vdev, then it applies to all + * non-tx vdevs as well set all non-tx mld's vdev id in bitmap + */ + + /* FIXME: disabled to make it compile without mlo */ + WARN(1, "mlo not supported"); + /* if (link_conf->elemid_added) { */ + /* set_bit(vdev_id, &vdev_map_cat1); */ + /* vdev_map_cat1 |= non_tx_ml_vdev_bmap; */ + /* } */ + + /* if (link_conf->elemid_modified) { */ + /* set_bit(vdev_id, &vdev_map_cat2); */ + /* vdev_map_cat2 |= non_tx_ml_vdev_bmap; */ + /* } */ + +err_fill_ml_info: + ml_info->cu_vdev_map_cat1_lo = + cpu_to_le32(ATH12K_GET_LOWER_32_BITS(vdev_map_cat1)); + ml_info->cu_vdev_map_cat1_hi = + cpu_to_le32(ATH12K_GET_UPPER_32_BITS(vdev_map_cat1)); + ml_info->cu_vdev_map_cat2_lo = + cpu_to_le32(ATH12K_GET_LOWER_32_BITS(vdev_map_cat2)); + ml_info->cu_vdev_map_cat2_hi = + cpu_to_le32(ATH12K_GET_UPPER_32_BITS(vdev_map_cat2)); + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi CU filled ml info cat1_lo=0x%x cat1_hi=0x%x cat2_lo=0x%x cat2_hi=0x%x non_tx_ml_bmap=%llu\n", + ml_info->cu_vdev_map_cat1_lo, ml_info->cu_vdev_map_cat1_hi, + ml_info->cu_vdev_map_cat2_lo, ml_info->cu_vdev_map_cat2_hi, + non_tx_ml_vdev_bmap); +} + +static void ath12k_wmi_fill_cu_arg(struct ath12k_link_vif *arvif, + struct wmi_critical_update_arg *cu_arg) +{ + struct ath12k_base *ab = arvif->ar->ab; + struct ath12k_link_vif *arvif_iter; + struct wmi_bcn_tmpl_ml_info *ml_info; + int i; + unsigned long non_tx_ml_vdev_bmap = 0; + struct ath12k *ar = arvif->ar; + struct ath12k_prb_resp_tmpl_ml_info *ar_ml_info; + + list_for_each_entry(arvif_iter, &arvif->ar->arvifs, list) { + if (arvif_iter != arvif && arvif_iter->tx_vdev_id == arvif->vdev_id && + ath12k_mac_is_ml_arvif(arvif_iter)) + set_bit(arvif_iter->vdev_id, &non_tx_ml_vdev_bmap); + } + if (!ath12k_mac_is_ml_arvif(arvif) && !non_tx_ml_vdev_bmap) + return; + + /* Fill ML params + * ML params should be filled for all partner links + */ + cu_arg->num_ml_params = 0; + /* TODO: Fill ML params. Will work without this info too */ + + /* Fill ML info + * ML info should be filled for impacted link only + */ + cu_arg->num_ml_info = 1; + cu_arg->ml_info = (struct wmi_bcn_tmpl_ml_info *) + kzalloc((cu_arg->num_ml_info * sizeof(*ml_info)), + GFP_KERNEL); + + if (!cu_arg->ml_info) { + ath12k_warn(ab, "wmi failed to get memory for ml info"); + cu_arg->num_ml_info = 0; + } else { + for (i = 0; i < cu_arg->num_ml_info; i++) { + ml_info = &cu_arg->ml_info[i]; + ath12k_wmi_bcn_fill_ml_info(arvif, ml_info, non_tx_ml_vdev_bmap); + /* Retain copy of CU vdev bitmap. Which are used to + * update cu_vdev_map in 20TU probe response template. + */ + if (ar->supports_6ghz) { + ar_ml_info = &arvif->ml_info; + ar_ml_info->hw_link_id = ml_info->hw_link_id; + ar_ml_info->cu_vdev_map_cat1_lo = ml_info->cu_vdev_map_cat1_lo; + ar_ml_info->cu_vdev_map_cat1_hi = ml_info->cu_vdev_map_cat1_hi; + ar_ml_info->cu_vdev_map_cat2_lo = ml_info->cu_vdev_map_cat2_lo; + ar_ml_info->cu_vdev_map_cat2_hi = ml_info->cu_vdev_map_cat2_hi; + } + } + } +} + +static void * +ath12k_wmi_append_critical_update_params(struct ath12k *ar, u32 vdev_id, + void *ptr, + struct wmi_critical_update_arg *cu_arg) +{ + struct wmi_bcn_tmpl_ml_params *ml_params; + struct wmi_bcn_tmpl_ml_info *ml_info; + void *start = ptr; + struct wmi_tlv *tlv; + size_t ml_params_len = cu_arg->num_ml_params * sizeof(*ml_params); + size_t ml_info_len = cu_arg->num_ml_info * sizeof(*ml_info); + int i; + + /* Add ML params */ + tlv = (struct wmi_tlv *)ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, ml_params_len); + ml_params = (struct wmi_bcn_tmpl_ml_params *)tlv->value; + + for (i = 0; i < cu_arg->num_ml_params; i++) + memcpy(&ml_params[i], &cu_arg->ml_params[i], + sizeof(*ml_params)); + + if (cu_arg->num_ml_params) + kfree(cu_arg->ml_params); + + ptr += TLV_HDR_SIZE + ml_params_len; + + /* Add ML info */ + tlv = (struct wmi_tlv *)ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, ml_info_len); + ml_info = (struct wmi_bcn_tmpl_ml_info *)tlv->value; + + for (i = 0; i < cu_arg->num_ml_info; i++) + memcpy(&ml_info[i], &cu_arg->ml_info[i], + sizeof(*ml_info)); + + if (cu_arg->num_ml_info) + kfree(cu_arg->ml_info); + + ptr += TLV_HDR_SIZE + ml_info_len; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi %ld bytes of additional data filled for CU\n", + (unsigned long)(ptr - start)); + return ptr; +} + int ath12k_wmi_bcn_tmpl(struct ath12k *ar, u32 vdev_id, struct ieee80211_mutable_offsets *offs, - struct sk_buff *bcn) + struct sk_buff *bcn, u32 ema_params) { struct ath12k_wmi_pdev *wmi = ar->wmi; struct wmi_bcn_tmpl_cmd *cmd; @@ -1693,12 +3085,32 @@ void *ptr; int ret, len; size_t aligned_len = roundup(bcn->len, 4); + struct ath12k_link_vif *arvif = ath12k_mac_get_arvif(ar, vdev_id); + struct wmi_critical_update_arg cu_arg = { + .num_ml_params = 0, + .ml_params = NULL, + .num_ml_info = 0, + .ml_info = NULL, + }; + + if (WARN_ON(!arvif)) + return -EINVAL; + + ath12k_wmi_fill_cu_arg(arvif, &cu_arg); - len = sizeof(*cmd) + sizeof(*bcn_prb_info) + TLV_HDR_SIZE + aligned_len; + len = sizeof(*cmd) + sizeof(*bcn_prb_info) + TLV_HDR_SIZE + aligned_len + + TLV_HDR_SIZE + (sizeof(struct wmi_bcn_tmpl_ml_params) * cu_arg.num_ml_params) + + TLV_HDR_SIZE + (sizeof(struct wmi_bcn_tmpl_ml_info) * cu_arg.num_ml_info); skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); - if (!skb) + if (!skb) { + if (cu_arg.num_ml_params) + kfree(cu_arg.ml_params); + if (cu_arg.num_ml_info) + kfree(cu_arg.ml_info); + return -ENOMEM; + } cmd = (struct wmi_bcn_tmpl_cmd *)skb->data; cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_BCN_TMPL_CMD, @@ -1707,7 +3119,12 @@ cmd->tim_ie_offset = cpu_to_le32(offs->tim_offset); cmd->csa_switch_count_offset = cpu_to_le32(offs->cntdwn_counter_offs[0]); cmd->ext_csa_switch_count_offset = cpu_to_le32(offs->cntdwn_counter_offs[1]); + cmd->csa_event_bitmap = cpu_to_le32(0xFFFFFFFF); cmd->buf_len = cpu_to_le32(bcn->len); + cmd->mbssid_ie_offset = cpu_to_le32(offs->mbssid_off); + cmd->ema_params = cpu_to_le32(ema_params); + cmd->feature_enable_bitmap = cpu_to_le32(u32_encode_bits(arvif->beacon_prot, + WMI_BEACON_PROTECTION_EN_BIT)); ptr = skb->data + sizeof(*cmd); @@ -1724,6 +3141,11 @@ tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len); memcpy(tlv->value, bcn->data, bcn->len); + ptr += (TLV_HDR_SIZE + aligned_len); + + ptr = ath12k_wmi_append_critical_update_params(ar, vdev_id, ptr, + &cu_arg); + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_BCN_TMPL_CMDID); if (ret) { ath12k_warn(ar->ab, "failed to send WMI_BCN_TMPL_CMDID\n"); @@ -1805,6 +3227,8 @@ cmd->peer_flags |= cpu_to_le32(WMI_PEER_80MHZ); if (arg->bw_160) cmd->peer_flags |= cpu_to_le32(WMI_PEER_160MHZ); + if (arg->bw_320) + cmd->peer_flags_ext |= cpu_to_le32(WMI_PEER_EXT_320MHZ); /* Typically if STBC is enabled for VHT it should be enabled * for HT as well @@ -1832,6 +3256,8 @@ cmd->peer_flags |= cpu_to_le32(WMI_PEER_TWT_REQ); if (arg->twt_responder) cmd->peer_flags |= cpu_to_le32(WMI_PEER_TWT_RESP); + if (arg->eht_flag) + cmd->peer_flags_ext |= cpu_to_le32(WMI_PEER_EXT_EHT); } /* Suppress authorization for all AUTH modes that need 4-way handshake @@ -1842,7 +3268,7 @@ cmd->peer_flags |= cpu_to_le32(WMI_PEER_AUTH); if (arg->need_ptk_4_way) { cmd->peer_flags |= cpu_to_le32(WMI_PEER_NEED_PTK_4_WAY); - if (!hw_crypto_disabled) + if (!hw_crypto_disabled && arg->is_assoc) cmd->peer_flags &= cpu_to_le32(~WMI_PEER_AUTH); } if (arg->need_gtk_2_way) @@ -1869,19 +3295,54 @@ cmd->peer_flags &= cpu_to_le32(~WMI_PEER_HT); } +static int ath12k_wmi_get_emlsr_pad_delay(u8 emlsr_pad_delay, + u32 *emlsr_pad_delay_us) +{ + u16 pad_delay_us[EMLSR_DELAY_MAX] = {0, 32, 64, 128, 256}; + + if (!emlsr_pad_delay_us) + return -EINVAL; + + if (emlsr_pad_delay >= EMLSR_DELAY_MAX) + return -EINVAL; + + *emlsr_pad_delay_us = pad_delay_us[emlsr_pad_delay]; + return 0; +} + +static int ath12k_get_emlsr_tran_delay(u8 emlsr_trans_delay, + u32 *emlsr_trans_delay_us) +{ + u16 delay_us[EMLSR_TRANS_DELAY_MAX] = {0, 16, 32, 64, 128, 256}; + + if (!emlsr_trans_delay_us) + return -EINVAL; + + if (emlsr_trans_delay >= EMLSR_TRANS_DELAY_MAX) + return -EINVAL; + + *emlsr_trans_delay_us = delay_us[emlsr_trans_delay]; + return 0; +} + int ath12k_wmi_send_peer_assoc_cmd(struct ath12k *ar, struct ath12k_wmi_peer_assoc_arg *arg) { struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_hw_group *ag = ar->ab->ag; struct wmi_peer_assoc_complete_cmd *cmd; struct ath12k_wmi_vht_rate_set_params *mcs; struct ath12k_wmi_he_rate_set_params *he_mcs; + struct wmi_eht_rate_set *eht_mcs; + struct wmi_peer_assoc_mlo_params *ml_params; + struct wmi_peer_assoc_mlo_partner_info *partner_info; struct sk_buff *skb; struct wmi_tlv *tlv; void *ptr; u32 peer_legacy_rates_align; u32 peer_ht_rates_align; int i, ret, len; + bool emlsr_support; peer_legacy_rates_align = roundup(arg->peer_legacy_rates.num_rates, sizeof(u32)); @@ -1892,7 +3353,11 @@ TLV_HDR_SIZE + (peer_legacy_rates_align * sizeof(u8)) + TLV_HDR_SIZE + (peer_ht_rates_align * sizeof(u8)) + sizeof(*mcs) + TLV_HDR_SIZE + - (sizeof(*he_mcs) * arg->peer_he_mcs_count); + (sizeof(*he_mcs) * arg->peer_he_mcs_count) + + TLV_HDR_SIZE + (sizeof(*eht_mcs) * arg->peer_eht_mcs_count) + + TLV_HDR_SIZE + sizeof(*ml_params) + + TLV_HDR_SIZE + (arg->ml.num_partner_links * sizeof(*partner_info)); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); if (!skb) @@ -1908,10 +3373,11 @@ cmd->peer_new_assoc = cpu_to_le32(arg->peer_new_assoc); cmd->peer_associd = cpu_to_le32(arg->peer_associd); + cmd->ru_punct_bitmap = cpu_to_le32(arg->ru_punct_bitmap); ath12k_wmi_copy_peer_flags(cmd, arg, test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, - &ar->ab->dev_flags)); + &ag->dev_flags)); ether_addr_copy(cmd->peer_macaddr.addr, arg->peer_mac); @@ -1939,6 +3405,17 @@ cmd->peer_ppet.ppet16_ppet8_ru3_ru0[i] = cpu_to_le32(arg->peer_ppet.ppet16_ppet8_ru3_ru0[i]); + /* Update 11be capabilities */ + memcpy_and_pad(cmd->peer_eht_cap_mac, sizeof(cmd->peer_eht_cap_mac), + arg->peer_eht_cap_mac, sizeof(arg->peer_eht_cap_mac), + 0); + memcpy_and_pad(cmd->peer_eht_cap_phy, sizeof(cmd->peer_eht_cap_phy), + arg->peer_eht_cap_phy, sizeof(arg->peer_eht_cap_phy), + 0); + memcpy_and_pad(&cmd->peer_eht_ppet, sizeof(cmd->peer_eht_ppet), + &arg->peer_eht_ppet, sizeof(arg->peer_eht_ppet), 0); + cmd->peer_eht_ops = arg->peer_eht_ops; + /* Update peer legacy rate information */ ptr += sizeof(*cmd); @@ -2000,13 +3477,118 @@ he_mcs->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_HE_RATE_SET, sizeof(*he_mcs)); - he_mcs->rx_mcs_set = cpu_to_le32(arg->peer_he_rx_mcs_set[i]); - he_mcs->tx_mcs_set = cpu_to_le32(arg->peer_he_tx_mcs_set[i]); + he_mcs->rx_mcs_set = cpu_to_le32(arg->peer_he_tx_mcs_set[i]); + he_mcs->tx_mcs_set = cpu_to_le32(arg->peer_he_rx_mcs_set[i]); ptr += sizeof(*he_mcs); } + /* MLO params */ + emlsr_support = FIELD_GET(IEEE80211_EML_CAP_EMLSR_SUPP, arg->ml.eml_caps); + + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_params)); + ptr += TLV_HDR_SIZE; + + ml_params = ptr; + ml_params->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_PEER_ASSOC_PARAMS) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*ml_params) - TLV_HDR_SIZE); + + ml_params->flags = FIELD_PREP(ATH12K_WMI_FLAG_MLO_ENABLED, + arg->ml.enabled) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_ASSOC_LINK, + arg->ml.assoc_link) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC, + arg->ml.primary_umac) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_LOGICAL_LINK_IDX_VALID, + arg->ml.logical_link_idx_valid) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_PEER_ID_VALID, + arg->ml.peer_id_valid) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_EMLSR_SUPPORT, + emlsr_support); + + ether_addr_copy(ml_params->mld_addr.addr, arg->ml.mld_addr); + ml_params->logical_link_idx = arg->ml.logical_link_idx; + ml_params->ml_peer_id = arg->ml.ml_peer_id; + ml_params->ieee_link_id = arg->ml.ieee_link_id; + + /* emlsr params */ + if (emlsr_support) { + u8 timeout; + /*get emlsr padding delay subfield, if invalid use 0us*/ + ath12k_wmi_get_emlsr_pad_delay( + FIELD_GET(IEEE80211_EML_CAP_EMLSR_PADDING_DELAY, + arg->ml.eml_caps), + &ml_params->emlsr_padding_delay_us); + /*get emlsr trans delay subfield value, if invalid use 0us*/ + ath12k_get_emlsr_tran_delay(FIELD_GET(IEEE80211_EML_CAP_EMLSR_TRANSITION_DELAY, + arg->ml.eml_caps), + &ml_params->emlsr_trans_delay_us); + + timeout = FIELD_GET(IEEE80211_EML_CAP_TRANSITION_TIMEOUT, + arg->ml.eml_caps); + if (timeout < EMLCAP_TIMEOUT_MAX) + ml_params->emlsr_trans_timeout_us = eml_trans_timeout[timeout]; + else + ath12k_warn(ar->ab, "Invalid emlsr trans timeout \n"); + } + ptr += sizeof(*ml_params); + + /* Loop through the EHT rate set. + */ + len = arg->peer_eht_mcs_count * sizeof(*eht_mcs); + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, len); + ptr += TLV_HDR_SIZE; + + for (i = 0; i < arg->peer_eht_mcs_count; i++) { + eht_mcs = ptr; + eht_mcs->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_EHT_RATE_SET) | + FIELD_PREP(WMI_TLV_LEN, + sizeof(*eht_mcs) - TLV_HDR_SIZE); + eht_mcs->rx_mcs_set = arg->peer_eht_rx_mcs_set[i]; + eht_mcs->tx_mcs_set = arg->peer_eht_tx_mcs_set[i]; + ptr += sizeof(*eht_mcs); + } + + /* fill ML Partner links */ + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, + arg->ml.num_partner_links * sizeof(*partner_info)); + ptr += TLV_HDR_SIZE; + + for (i = 0; i < arg->ml.num_partner_links; i++) { + partner_info = ptr; + partner_info->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_MLO_PARTNER_LINK_PARAMS_PEER_ASSOC) | + FIELD_PREP(WMI_TLV_LEN, + sizeof(*partner_info) - TLV_HDR_SIZE); + partner_info->vdev_id = arg->ml.partner_info[i].vdev_id; + partner_info->hw_link_id = arg->ml.partner_info[i].hw_link_id; + + partner_info->flags = FIELD_PREP(ATH12K_WMI_FLAG_MLO_ENABLED, 1) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_ASSOC_LINK, + arg->ml.partner_info[i].assoc_link) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC, + arg->ml.partner_info[i].primary_umac) | + FIELD_PREP(ATH12K_WMI_FLAG_MLO_LOGICAL_LINK_IDX_VALID, + arg->ml.partner_info[i].logical_link_idx_valid); + partner_info->logical_link_idx = arg->ml.partner_info[i].logical_link_idx; + ptr += sizeof(*partner_info); + } + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_ASSOC_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to send WMI_PEER_ASSOC_CMDID\n"); + dev_kfree_skb(skb); + } + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, - "wmi peer assoc vdev id %d assoc id %d peer mac %pM peer_flags %x rate_caps %x peer_caps %x listen_intval %d ht_caps %x max_mpdu %d nss %d phymode %d peer_mpdu_density %d vht_caps %x he cap_info %x he ops %x he cap_info_ext %x he phy %x %x %x peer_bw_rxnss_override %x\n", + "wmi peer assoc vdev id %d assoc id %d peer mac %pM peer_flags %x rate_caps %x peer_caps %x listen_intval %d ht_caps %x max_mpdu %d nss %d phymode %d peer_mpdu_density %d vht_caps %x he cap_info %x he ops %x he cap_info_ext %x he phy %x %x %x peer_bw_rxnss_override %x peer_flags_ext %x eht mac_cap %x %x eht phy_cap %x %x %x eht ops %x ml flags %x mld_addr %pM logical_link_idx %u ml peer id %d ieee_link_id %u num_partner_links %d\n", cmd->vdev_id, cmd->peer_associd, arg->peer_mac, cmd->peer_flags, cmd->peer_rate_caps, cmd->peer_caps, cmd->peer_listen_intval, cmd->peer_ht_caps, @@ -2016,14 +3598,14 @@ cmd->peer_he_ops, cmd->peer_he_cap_info_ext, cmd->peer_he_cap_phy[0], cmd->peer_he_cap_phy[1], cmd->peer_he_cap_phy[2], - cmd->peer_bw_rxnss_override); - - ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_ASSOC_CMDID); - if (ret) { - ath12k_warn(ar->ab, - "failed to send WMI_PEER_ASSOC_CMDID\n"); - dev_kfree_skb(skb); - } + cmd->peer_bw_rxnss_override, cmd->peer_flags_ext, + cmd->peer_eht_cap_mac[0], cmd->peer_eht_cap_mac[1], + cmd->peer_eht_cap_phy[0], cmd->peer_eht_cap_phy[1], + cmd->peer_eht_cap_phy[2], cmd->peer_eht_ops, + ml_params->flags, ml_params->mld_addr.addr, + ml_params->logical_link_idx, ml_params->ml_peer_id, + ml_params->ieee_link_id, + arg->ml.num_partner_links); return ret; } @@ -2033,16 +3615,16 @@ { /* setup commonly used values */ arg->scan_req_id = 1; - arg->scan_priority = WMI_SCAN_PRIORITY_LOW; - arg->dwell_time_active = 50; - arg->dwell_time_active_2g = 0; + arg->scan_priority = WMI_SCAN_PRIORITY_MEDIUM; + arg->dwell_time_active = 175; + arg->dwell_time_active_2g = 175; arg->dwell_time_passive = 150; - arg->dwell_time_active_6g = 40; - arg->dwell_time_passive_6g = 30; + arg->dwell_time_active_6g = 70; + arg->dwell_time_passive_6g = 70; arg->min_rest_time = 50; arg->max_rest_time = 500; arg->repeat_probe_time = 0; - arg->probe_spacing_time = 0; + arg->probe_spacing_time = 100; arg->idle_time = 0; arg->max_scan_time = 20000; arg->probe_delay = 5; @@ -2051,7 +3633,8 @@ WMI_SCAN_EVENT_BSS_CHANNEL | WMI_SCAN_EVENT_FOREIGN_CHAN | WMI_SCAN_EVENT_DEQUEUED; - arg->scan_flags |= WMI_SCAN_CHAN_STAT_EVENT; + arg->scan_flags |= WMI_SCAN_CHAN_STAT_EVENT | + WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS; arg->num_bssid = 1; /* fill bssid_list[0] with 0xff, otherwise bssid and RA will be @@ -2145,7 +3728,7 @@ void *ptr; int i, ret, len; u32 *tmp_ptr; - u8 extraie_len_with_pad = 0; + u16 extraie_len_with_pad = 0; struct ath12k_wmi_hint_short_ssid_arg *s_ssid = NULL; struct ath12k_wmi_hint_bssid_arg *hint_bssid = NULL; @@ -2164,7 +3747,7 @@ len += sizeof(*bssid) * arg->num_bssid; len += TLV_HDR_SIZE; - if (arg->extraie.len) + if (arg->extraie.len && arg->extraie.len <= 0xFFFF) extraie_len_with_pad = roundup(arg->extraie.len, sizeof(u32)); len += extraie_len_with_pad; @@ -2266,7 +3849,7 @@ tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, len); ptr += TLV_HDR_SIZE; - if (arg->extraie.len) + if (extraie_len_with_pad) memcpy(ptr, arg->extraie.ptr, arg->extraie.len); @@ -2311,6 +3894,69 @@ return ret; } +int ath12k_wmi_send_vdev_set_tpc_power(struct ath12k *ar, + u32 vdev_id, + struct ath12k_reg_tpc_power_info *param) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_vdev_set_tpc_power_cmd *cmd; + struct wmi_vdev_ch_power_info *ch; + struct sk_buff *skb; + struct wmi_tlv *tlv; + u8 *ptr; + int i, ret, len; + + len = sizeof(*cmd) + TLV_HDR_SIZE; + len += (sizeof(struct wmi_vdev_ch_power_info) * param->num_pwr_levels); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + ptr = skb->data; + + cmd = (struct wmi_vdev_set_tpc_power_cmd *)ptr; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_VDEV_SET_TPC_POWER_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + cmd->vdev_id = vdev_id; + cmd->psd_power = param->is_psd_power; + cmd->eirp_power = param->eirp_power; + cmd->power_type_6ghz = param->power_type_6g; + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi TPC vdev_id: %d is_psd_power: %d eirp_power: %d power_type_6g: %d\n", + vdev_id, param->is_psd_power, param->eirp_power, param->power_type_6g); + + ptr += sizeof(*cmd); + tlv = (struct wmi_tlv *)ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, param->num_pwr_levels * sizeof(*ch)); + + ptr += TLV_HDR_SIZE; + ch = (struct wmi_vdev_ch_power_info *)ptr; + + for (i = 0; i < param->num_pwr_levels; i++, ch++) { + ch->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_VDEV_CH_POWER_INFO) | + FIELD_PREP(WMI_TLV_LEN, + sizeof(*ch) - TLV_HDR_SIZE); + + ch->chan_cfreq = param->chan_power_info[i].chan_cfreq; + ch->tx_power = param->chan_power_info[i].tx_power; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi TPC chan_cfreq: %d , tx_power: %d\n", + ch->chan_cfreq, ch->tx_power); + } + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_VDEV_SET_TPC_POWER_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_VDEV_SET_TPC_POWER_CMDID\n"); + dev_kfree_skb(skb); + } + return ret; +} + int ath12k_wmi_send_scan_stop_cmd(struct ath12k *ar, struct ath12k_wmi_scan_cancel_arg *arg) { @@ -2453,6 +4099,8 @@ WMI_CHAN_REG_INFO1_REG_CLS); *reg2 |= le32_encode_bits(channel_arg->antennamax, WMI_CHAN_REG_INFO2_ANT_MAX); + *reg2 |= le32_encode_bits(channel_arg->maxregpower, + WMI_CHAN_REG_INFO2_MAX_TX_PWR); ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI chan scan list chan[%d] = %u, chan_info->info %8x\n", @@ -2525,7 +4173,7 @@ wmm_param->acm = cpu_to_le32(wmi_wmm_arg->acm); wmm_param->no_ack = cpu_to_le32(wmi_wmm_arg->no_ack); - ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + ath12k_dbg(ar->ab, ATH12K_DBG_SET(WMI, L3), "wmi wmm set ac %d aifs %d cwmin %d cwmax %d txop %d acm %d no_ack %d\n", ac, wmm_param->aifs, wmm_param->cwmin, wmm_param->cwmax, wmm_param->txoplimit, @@ -2715,6 +4363,52 @@ return ret; } +int ath12k_wmi_pdev_peer_pktlog_filter(struct ath12k *ar, u8 *addr, u8 enable) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_pdev_pktlog_filter_cmd *cmd; + struct wmi_pdev_pktlog_filter_info *info; + struct sk_buff *skb; + struct wmi_tlv *tlv; + void *ptr; + int ret, len; + + len = sizeof(*cmd) + sizeof(*info) + TLV_HDR_SIZE; + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_pktlog_filter_cmd *)skb->data; + + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD, + sizeof(*cmd)); + + cmd->pdev_id = cpu_to_le32(DP_HW2SW_MACID(ar->pdev->pdev_id)); + cmd->num_mac = cpu_to_le32(1); + cmd->enable = cpu_to_le32(enable); + + ptr = skb->data + sizeof(*cmd); + + tlv = ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, sizeof(*info)); + + ptr += TLV_HDR_SIZE; + info = ptr; + + ether_addr_copy(info->peer_macaddr.addr, addr); + info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, + sizeof(*info)); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_PKTLOG_FILTER_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_PDEV_PKTLOG_ENABLE_CMDID\n"); + dev_kfree_skb(skb); + } + + return ret; +} + int ath12k_wmi_send_init_country_cmd(struct ath12k *ar, struct ath12k_wmi_init_country_arg *arg) { @@ -2768,6 +4462,125 @@ } int +ath12k_wmi_send_thermal_mitigation_cmd(struct ath12k *ar, + struct ath12k_wmi_thermal_mitigation_arg *arg) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_therm_throt_config_request_cmd *cmd; + struct wmi_therm_throt_level_config_info *lvl_conf; + struct wmi_tlv *tlv; + struct sk_buff *skb; + int i, ret, len; + + len = sizeof(*cmd) + TLV_HDR_SIZE + THERMAL_LEVELS * sizeof(*lvl_conf); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_therm_throt_config_request_cmd *)skb->data; + + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_THERM_THROT_CONFIG_REQUEST, + sizeof(*cmd)); + + cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); + cmd->enable = cpu_to_le32(arg->enable); + cmd->dc = cpu_to_le32(arg->dc); + cmd->dc_per_event = cpu_to_le32(arg->dc_per_event); + cmd->therm_throt_levels = cpu_to_le32(THERMAL_LEVELS); + + tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd)); + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, + THERMAL_LEVELS * sizeof(*lvl_conf)); + + lvl_conf = (struct wmi_therm_throt_level_config_info *)(skb->data + + sizeof(*cmd) + + TLV_HDR_SIZE); + for (i = 0; i < THERMAL_LEVELS; i++) { + lvl_conf->tlv_header = + ath12k_wmi_tlv_cmd_hdr(WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, + sizeof(*lvl_conf)); + + lvl_conf->temp_lwm = arg->levelconf[i].tmplwm; + lvl_conf->temp_hwm = arg->levelconf[i].tmphwm; + lvl_conf->dc_off_percent = arg->levelconf[i].dcoffpercent; + lvl_conf->prio = arg->levelconf[i].priority; + lvl_conf++; + } + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_THERM_THROT_SET_CONF_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send THERM_THROT_SET_CONF cmd\n"); + dev_kfree_skb(skb); + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "WMI vdev set thermal throt pdev_id %d enable %d dc %d dc_per_event %x levels %d\n", + ar->pdev->pdev_id, arg->enable, arg->dc, + arg->dc_per_event, THERMAL_LEVELS); + + return ret; +} + +int ath12k_wmi_pdev_pktlog_enable(struct ath12k *ar, u32 pktlog_filter) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_pktlog_enable_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pktlog_enable_cmd *)skb->data; + + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, + sizeof(*cmd)); + + cmd->pdev_id = cpu_to_le32(DP_HW2SW_MACID(ar->pdev->pdev_id)); + cmd->evlist = cpu_to_le32(pktlog_filter); + cmd->enable = cpu_to_le32(ATH12K_WMI_PKTLOG_ENABLE_FORCE); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_PKTLOG_ENABLE_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_PDEV_PKTLOG_ENABLE_CMDID\n"); + dev_kfree_skb(skb); + } + + return ret; +} + +int ath12k_wmi_pdev_pktlog_disable(struct ath12k *ar) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_pktlog_disable_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pktlog_disable_cmd *)skb->data; + + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, + sizeof(*cmd)); + + cmd->pdev_id = cpu_to_le32(DP_HW2SW_MACID(ar->pdev->pdev_id)); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_PKTLOG_DISABLE_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_PDEV_PKTLOG_ENABLE_CMDID\n"); + dev_kfree_skb(skb); + } + + return ret; +} + +int ath12k_wmi_send_twt_enable_cmd(struct ath12k *ar, u32 pdev_id) { struct ath12k_wmi_pdev *wmi = ar->wmi; @@ -2811,11 +4624,12 @@ /* TODO add MBSSID support */ cmd->mbss_support = 0; - ret = ath12k_wmi_cmd_send(wmi, skb, - WMI_TWT_ENABLE_CMDID); + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_TWT_ENABLE_CMDID); if (ret) { ath12k_warn(ab, "Failed to send WMI_TWT_ENABLE_CMDID"); dev_kfree_skb(skb); + } else { + ar->twt_enabled = 1; } return ret; } @@ -2840,11 +4654,587 @@ len); cmd->pdev_id = cpu_to_le32(pdev_id); - ret = ath12k_wmi_cmd_send(wmi, skb, - WMI_TWT_DISABLE_CMDID); + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_TWT_DISABLE_CMDID); if (ret) { ath12k_warn(ab, "Failed to send WMI_TWT_DISABLE_CMDID"); dev_kfree_skb(skb); + } else { + ar->twt_enabled = 0; + } + return ret; +} + +int ath12k_wmi_send_twt_add_dialog_cmd(struct ath12k *ar, + struct wmi_twt_add_dialog_params *params) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_twt_add_dialog_params_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_twt_add_dialog_params_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_TWT_ADD_DIALOG_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + + cmd->vdev_id = params->vdev_id; + ether_addr_copy(cmd->peer_macaddr.addr, params->peer_macaddr); + cmd->dialog_id = params->dialog_id; + cmd->wake_intvl_us = params->wake_intvl_us; + cmd->wake_intvl_mantis = params->wake_intvl_mantis; + cmd->wake_dura_us = params->wake_dura_us; + cmd->sp_offset_us = params->sp_offset_us; + cmd->flags = params->twt_cmd; + if (params->flag_bcast) + cmd->flags |= WMI_TWT_ADD_DIALOG_FLAG_BCAST; + if (params->flag_trigger) + cmd->flags |= WMI_TWT_ADD_DIALOG_FLAG_TRIGGER; + if (params->flag_flow_type) + cmd->flags |= WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE; + if (params->flag_protection) + cmd->flags |= WMI_TWT_ADD_DIALOG_FLAG_PROTECTION; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi add twt dialog vdev %u dialog id %u wake interval %u mantissa %u wake duration %u service period offset %u flags 0x%x\n", + cmd->vdev_id, cmd->dialog_id, cmd->wake_intvl_us, + cmd->wake_intvl_mantis, cmd->wake_dura_us, cmd->sp_offset_us, + cmd->flags); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_TWT_ADD_DIALOG_CMDID); + + if (ret) { + ath12k_warn(ab, + "failed to send wmi command to add twt dialog: %d", + ret); + dev_kfree_skb(skb); + } + return ret; +} + +int +ath12k_wmi_send_wmi_ctrl_stats_cmd(struct ath12k *ar, + struct wmi_ctrl_path_stats_cmd_param *param) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + u32 pdev_id_array[2] = {0}; + int len, ret; + struct wmi_tlv *tlv; + struct sk_buff *skb; + struct wmi_ctrl_path_stats_cmd_param *cmd; + void *ptr; + u32 stats_id = 0; +#ifdef CONFIG_ATH12K_DEBUGFS + unsigned long time_left; +#endif + + switch (param->stats_id) { + case WMI_REQ_CTRL_PATH_PDEV_TX_STAT: + case WMI_REQ_CTRL_PATH_CAL_STAT: + case WMI_REQ_CTRL_PATH_BTCOEX_STAT: + pdev_id_array[0] = ar->pdev->pdev_id; + stats_id = (1 << param->stats_id); + break; + case WMI_REQ_CTRL_PATH_AWGN_STAT: + if (ar->supports_6ghz) { + pdev_id_array[0] = ar->pdev->pdev_id; + stats_id = (1 << param->stats_id); + } else { + ath12k_warn(ab, + "Stats id %d awgn stats are only supported for 6GHz", + param->stats_id); + return -EIO; + } + break; + /* Add case for newly wmi ctrl path stats here */ + default: + ath12k_warn(ab, "Unsupported stats id %d", param->stats_id); + return -EIO; + break; + } + + len = sizeof(*cmd) + + TLV_HDR_SIZE + sizeof(u32) + + TLV_HDR_SIZE + TLV_HDR_SIZE; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (void *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_CTRL_PATH_STATS_CMD_FIXED_PARAM) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + cmd->stats_id = stats_id; + cmd->req_id = param->req_id; + cmd->action = param->action; + + ptr = skb->data + sizeof(*cmd); + + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_UINT32) | + FIELD_PREP(WMI_TLV_LEN, sizeof(u32)); + ptr += TLV_HDR_SIZE; + memcpy(ptr, pdev_id_array, sizeof(pdev_id_array)); + ptr += sizeof(u32); + + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_UINT32) | + FIELD_PREP(WMI_TLV_LEN, 0); + ptr += TLV_HDR_SIZE; + + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_FIXED_STRUCT) | + FIELD_PREP(WMI_TLV_LEN, 0); + ptr += TLV_HDR_SIZE; + +#ifdef CONFIG_ATH12K_DEBUGFS + if (param->action == WMI_REQUEST_CTRL_PATH_STAT_GET) + reinit_completion(&ar->debug.wmi_ctrl_path_stats_rcvd); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_REQUEST_CTRL_PATH_STATS_CMDID); + if (ret) { + dev_kfree_skb(skb); + ath12k_warn(ab, "Failed to send WMI_REQUEST_CTRL_PATH_STATS_CMDID: %d", ret); + } else { + if (param->action == WMI_REQUEST_CTRL_PATH_STAT_GET) { + time_left = wait_for_completion_timeout( + &ar->debug.wmi_ctrl_path_stats_rcvd, + WMI_CTRL_STATS_READY_TIMEOUT_HZ * HZ); + if (time_left == 0) { + ath12k_warn(ab, "timeout in receiving wmi ctrl path stats\n"); + return -ETIMEDOUT; + } + } + } +#endif + + return ret; +} + +int ath12k_wmi_send_twt_del_dialog_cmd(struct ath12k *ar, + struct wmi_twt_del_dialog_params *params) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_twt_del_dialog_params_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_twt_del_dialog_params_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_TWT_DEL_DIALOG_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + + cmd->vdev_id = params->vdev_id; + ether_addr_copy(cmd->peer_macaddr.addr, params->peer_macaddr); + cmd->dialog_id = params->dialog_id; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi delete twt dialog vdev %u dialog id %u\n", + cmd->vdev_id, cmd->dialog_id); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_TWT_DEL_DIALOG_CMDID); + if (ret) { + ath12k_warn(ab, + "failed to send wmi command to delete twt dialog: %d", + ret); + dev_kfree_skb(skb); + } + return ret; +} + +#ifdef CONFIG_ATH12K_DEBUGFS +void ath12k_wmi_crl_path_stats_list_free(struct ath12k *ar, struct list_head *head) +{ + struct wmi_ctrl_path_stats_list *stats, *tmp; + + lockdep_assert_held(&ar->wmi_ctrl_path_stats_lock); + list_for_each_entry_safe(stats, tmp, head, list) { + kfree(stats->stats_ptr); + list_del(&stats->list); + kfree(stats); + } +} + +int wmi_print_ctrl_path_pdev_tx_stats_tlv(struct ath12k_base *ab, u16 len, const void *ptr, void *data) +{ + struct wmi_ctrl_path_stats_ev_parse_param *stats_buff = (struct wmi_ctrl_path_stats_ev_parse_param *)data; + struct wmi_ctrl_path_pdev_stats *pdev_stats_skb = (struct wmi_ctrl_path_pdev_stats *)ptr; + struct wmi_ctrl_path_pdev_stats *pdev_stats = NULL; + struct wmi_ctrl_path_stats_list *stats = kzalloc(sizeof(struct wmi_ctrl_path_stats_list), GFP_ATOMIC); + struct ath12k *ar = NULL; + + if (!stats) + return -ENOMEM; + + pdev_stats = kzalloc(sizeof(*pdev_stats), GFP_ATOMIC); + if (!pdev_stats) { + kfree(stats); + return -ENOMEM; + } + + memcpy(pdev_stats, pdev_stats_skb, sizeof(struct wmi_ctrl_path_pdev_stats)); + stats->stats_ptr = pdev_stats; + list_add_tail(&stats->list, &stats_buff->list); + + ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_stats_skb->pdev_id + 1); + if (!ar) { + ath12k_warn(ab, "Failed to get ar for wmi ctrl stats\n"); + kfree(pdev_stats); + kfree(stats); + return -EINVAL; + } + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ar->debug.wmi_ctrl_path_stats_tagid = WMI_CTRL_PATH_PDEV_STATS; + stats_buff->ar = ar; + return 0; +} + +int wmi_print_ctrl_path_cal_stats_tlv(struct ath12k_base *ab, u16 len, + const void *ptr, void *data) +{ + struct wmi_ctrl_path_stats_ev_parse_param *stats_buff = (struct wmi_ctrl_path_stats_ev_parse_param *)data; + struct wmi_ctrl_path_cal_stats *cal_stats_skb = (struct wmi_ctrl_path_cal_stats *)ptr; + struct wmi_ctrl_path_cal_stats *cal_stats = NULL; + struct wmi_ctrl_path_stats_list *stats = kzalloc(sizeof(struct wmi_ctrl_path_stats_list), GFP_ATOMIC); + struct ath12k *ar = NULL; + + if (!stats) + return -ENOMEM; + + cal_stats = kzalloc(sizeof(*cal_stats), GFP_ATOMIC); + if (!cal_stats) { + kfree(stats); + return -ENOMEM; + } + + memcpy(cal_stats, cal_stats_skb, sizeof(struct wmi_ctrl_path_cal_stats)); + stats->stats_ptr = cal_stats; + list_add_tail(&stats->list, &stats_buff->list); + + ar = ath12k_mac_get_ar_by_pdev_id(ab, cal_stats_skb->pdev_id + 1); + if (!ar) { + ath12k_warn(ab, "Failed to get ar for wmi ctrl cal stats\n"); + kfree(cal_stats); + kfree(stats); + return -EINVAL; + } + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ar->debug.wmi_ctrl_path_stats_tagid = WMI_CTRL_PATH_CAL_STATS; + stats_buff->ar = ar; + return 0; +} + +int wmi_print_ctrl_path_btcoex_stats_tlv(struct ath12k_base *ab, u16 len, + const void *ptr, void *data) +{ + struct wmi_ctrl_path_stats_ev_parse_param *stats_buff = + (struct wmi_ctrl_path_stats_ev_parse_param *)data; + struct wmi_ctrl_path_btcoex_stats *btcoex_stats_skb = + (struct wmi_ctrl_path_btcoex_stats *)ptr; + struct wmi_ctrl_path_btcoex_stats *btcoex_stats = NULL; + struct wmi_ctrl_path_stats_list *stats; + struct ath12k *ar = NULL; + + stats = kzalloc(sizeof(*stats), GFP_ATOMIC); + if (!stats) + return -ENOMEM; + + btcoex_stats = kzalloc(sizeof(*btcoex_stats), GFP_ATOMIC); + if (!btcoex_stats) { + kfree(stats); + return -ENOMEM; + } + + memcpy(btcoex_stats, btcoex_stats_skb, sizeof(*btcoex_stats)); + stats->stats_ptr = btcoex_stats; + list_add_tail(&stats->list, &stats_buff->list); + + ar = ath12k_mac_get_ar_by_pdev_id(ab, btcoex_stats_skb->pdev_id + 1); + if (!ar) { + ath12k_warn(ab, "Failed to get ar for wmi ctrl cal stats\n"); + kfree(btcoex_stats); + kfree(stats); + return -EINVAL; + } + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ar->debug.wmi_ctrl_path_stats_tagid = WMI_CTRL_PATH_BTCOEX_STATS; + stats_buff->ar = ar; + return 0; +} + +int wmi_print_ctrl_path_awgn_stats_tlv(struct ath12k_base *ab, u16 len, + const void *ptr, void *data) +{ + struct wmi_ctrl_path_stats_ev_parse_param *stats_buff = + (struct wmi_ctrl_path_stats_ev_parse_param *)data; + struct wmi_ctrl_path_awgn_stats *awgn_stats_skb, *awgn_stats = NULL; + struct wmi_ctrl_path_stats_list *stats; + struct ath12k *ar = NULL; + int i; + + awgn_stats_skb = (struct wmi_ctrl_path_awgn_stats *)ptr; + + for (i = 0; i < ATH12K_GROUP_MAX_RADIO; i++) { + ar = ab->ag->hw_links[i]; + if (!ar) { + ath12k_warn(ab, "Failed to get ar for wmi ctrl awgn stats\n"); + return -EINVAL; + } + + if (ar->supports_6ghz) + break; + } + + stats = kzalloc(sizeof(*stats), GFP_ATOMIC); + if (!stats) + return -ENOMEM; + + awgn_stats = kzalloc(sizeof(*awgn_stats), GFP_ATOMIC); + + if (!awgn_stats) { + kfree(stats); + return -ENOMEM; + } + + memcpy(awgn_stats, awgn_stats_skb, sizeof(*awgn_stats)); + stats->stats_ptr = awgn_stats; + list_add_tail(&stats->list, &stats_buff->list); + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ar->debug.wmi_ctrl_path_stats_tagid = WMI_CTRL_PATH_AWGN_STATS; + stats_buff->ar = ar; + + return 0; +} + +static int ath12k_wmi_ctrl_stats_subtlv_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + int ret = 0; + + switch (tag) { + case WMI_CTRL_PATH_STATS_EV_FIXED_PARAM: + break; + case WMI_CTRL_PATH_PDEV_STATS: + ret = wmi_print_ctrl_path_pdev_tx_stats_tlv(ab, len, ptr, data); + break; + case WMI_CTRL_PATH_CAL_STATS: + ret = wmi_print_ctrl_path_cal_stats_tlv(ab, len, ptr, data); + break; + case WMI_CTRL_PATH_BTCOEX_STATS: + ret = wmi_print_ctrl_path_btcoex_stats_tlv(ab, len, ptr, data); + break; + case WMI_CTRL_PATH_AWGN_STATS: + ret = wmi_print_ctrl_path_awgn_stats_tlv(ab, len, ptr, data); + break; + /* Add case for newly wmi ctrl path added stats here */ + default: + ath12k_warn(ab, + "Received invalid tag for wmi ctrl path stats in subtlvs, tag : 0x%x\n", + tag); + return -EINVAL; + break; + } + + return ret; +} + +static int ath12k_wmi_ctrl_stats_event_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + int ret = 0; + + ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi ctrl path stats tag 0x%x of len %d rcvd\n", + tag, len); + + switch (tag) { + case WMI_CTRL_PATH_STATS_EV_FIXED_PARAM: + /* Fixed param is already processed*/ + break; + case WMI_TAG_ARRAY_STRUCT: + /* len 0 is expected for array of struct when there + * is no content of that type to pack inside that tlv + */ + if (len == 0) + return 0; + + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_ctrl_stats_subtlv_parser, + data); + break; + default: + ath12k_warn(ab, "Received invalid tag for wmi ctrl path stats\n"); + ret = -EINVAL; + break; + } + + return ret; +} + +static void ath12k_wmi_ctrl_path_stats_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + int ret; + const struct wmi_tlv *tlv; + struct wmi_ctrl_path_stats_ev_param *fixed_param; + u16 tlv_tag; + u8 *ptr = skb->data; + struct ath12k *ar = NULL; + struct wmi_ctrl_path_stats_ev_parse_param param; + INIT_LIST_HEAD(¶m.list); + + if (!skb->data) { + ath12k_warn(ab, "No data present in wmi ctrl stats event\n"); + return; + } + + if (skb->len < (sizeof(*fixed_param) + TLV_HDR_SIZE)) { + ath12k_warn(ab, "wmi ctrl stats event size invalid\n"); + return; + } + + param.ar = NULL; + + tlv = (struct wmi_tlv *)ptr; + tlv_tag = FIELD_GET(WMI_TLV_TAG, tlv->header); + ptr += sizeof(*tlv); + + if (tlv_tag == WMI_CTRL_PATH_STATS_EV_FIXED_PARAM) + fixed_param = (struct wmi_ctrl_path_stats_ev_param *)ptr; + else + ath12k_warn(ab, "wmi ctrl Stats received without fixed param tlv at start\n"); + + if (!fixed_param) { + ath12k_warn(ab, "wmi ctrl Stats received fixed param is NULL\n"); + goto free; + } + + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_ctrl_stats_event_parser, + ¶m); + if (ret) { + ath12k_warn(ab, "failed to parse wmi_ctrl_path_stats tlv: %d\n", ret); + goto free; + } + + ar = param.ar; + if (!ar) + return; + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + list_splice_tail_init(¶m.list, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + + if (!fixed_param->more) { + complete(&ar->debug.wmi_ctrl_path_stats_rcvd); + ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi ctrl path stats completed"); + } +free: + ath12k_wmi_crl_path_stats_list_free(ar, ¶m.list); +} +#endif + +int ath12k_wmi_send_twt_pause_dialog_cmd(struct ath12k *ar, + struct wmi_twt_pause_dialog_params *params) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_twt_pause_dialog_params_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_twt_pause_dialog_params_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_TWT_PAUSE_DIALOG_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + + cmd->vdev_id = params->vdev_id; + ether_addr_copy(cmd->peer_macaddr.addr, params->peer_macaddr); + cmd->dialog_id = params->dialog_id; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi pause twt dialog vdev %u dialog id %u\n", + cmd->vdev_id, cmd->dialog_id); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_TWT_PAUSE_DIALOG_CMDID); + if (ret) { + ath12k_warn(ab, + "failed to send wmi command to pause twt dialog: %d", + ret); + dev_kfree_skb(skb); + } + return ret; +} + +int ath12k_wmi_send_twt_resume_dialog_cmd(struct ath12k *ar, + struct wmi_twt_resume_dialog_params *params) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_twt_resume_dialog_params_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_twt_resume_dialog_params_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_TWT_RESUME_DIALOG_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + + cmd->vdev_id = params->vdev_id; + ether_addr_copy(cmd->peer_macaddr.addr, params->peer_macaddr); + cmd->dialog_id = params->dialog_id; + cmd->sp_offset_us = params->sp_offset_us; + cmd->next_twt_size = params->next_twt_size; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi resume twt dialog vdev %u dialog id %u service period offset %u next twt subfield size %u\n", + cmd->vdev_id, cmd->dialog_id, cmd->sp_offset_us, + cmd->next_twt_size); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_TWT_RESUME_DIALOG_CMDID); + if (ret) { + ath12k_warn(ab, + "failed to send wmi command to resume twt dialog: %d", + ret); + dev_kfree_skb(skb); } return ret; } @@ -2925,6 +5315,232 @@ return ret; } +int ath12k_wmi_pdev_set_srg_bss_color_bitmap(struct ath12k *ar, u32 *bitmap) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_pdev_obss_pd_bitmap_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_obss_pd_bitmap_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap)); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "obss pd pdev_id %d bss color bitmap %08x %08x\n", + cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID); + if (ret) { + ath12k_warn(ab, + "Failed to send WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID"); + dev_kfree_skb(skb); + } + + return ret; +} + +int +ath12k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath12k *ar, u32 *bitmap) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_pdev_obss_pd_bitmap_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_obss_pd_bitmap_cmd *)skb->data; + cmd->tlv_header = + FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap)); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "obss pd pdev_id %d partial bssid bitmap %08x %08x\n", + cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID); + if (ret) { + ath12k_warn(ab, + "Failed to send WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID"); + dev_kfree_skb(skb); + } + + return ret; +} + +int +ath12k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath12k *ar, u32 *bitmap) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_pdev_obss_pd_bitmap_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_obss_pd_bitmap_cmd *)skb->data; + cmd->tlv_header = + FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap)); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "obss pd srg pdev_id %d bss color enable bitmap %08x %08x\n", + cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID); + if (ret) { + ath12k_warn(ab, + "Failed to send WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID"); + dev_kfree_skb(skb); + } + + return ret; +} + +int +ath12k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath12k *ar, u32 *bitmap) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_pdev_obss_pd_bitmap_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_obss_pd_bitmap_cmd *)skb->data; + cmd->tlv_header = + FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap)); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "obss pd srg pdev_id %d bssid enable bitmap %08x %08x\n", + cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID); + if (ret) { + ath12k_warn(ab, + "Failed to send WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID"); + dev_kfree_skb(skb); + } + + return ret; +} + +int +ath12k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath12k *ar, u32 *bitmap) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_pdev_obss_pd_bitmap_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_obss_pd_bitmap_cmd *)skb->data; + cmd->tlv_header = + FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap)); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "obss pd non_srg pdev_id %d bss color enable bitmap %08x %08x\n", + cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID); + if (ret) { + ath12k_warn(ab, + "Failed to send WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID"); + dev_kfree_skb(skb); + } + + return ret; +} + +int +ath12k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath12k *ar, u32 *bitmap) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct ath12k_base *ab = wmi->wmi_ab->ab; + struct wmi_pdev_obss_pd_bitmap_cmd *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_obss_pd_bitmap_cmd *)skb->data; + cmd->tlv_header = + FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD) | + FIELD_PREP(WMI_TLV_LEN, len - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + memcpy(cmd->bitmap, bitmap, sizeof(cmd->bitmap)); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "obss pd non_srg pdev_id %d bssid enable bitmap %08x %08x\n", + cmd->pdev_id, cmd->bitmap[0], cmd->bitmap[1]); + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID); + if (ret) { + ath12k_warn(ab, + "Failed to send WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID"); + dev_kfree_skb(skb); + } + + return ret; +} + int ath12k_wmi_send_bss_color_change_enable_cmd(struct ath12k *ar, u32 vdev_id, bool enable) { @@ -3000,6 +5616,41 @@ return ret; } +static void * +ath12k_wmi_append_prb_resp_cu_params(struct ath12k *ar, u32 vdev_id, void *ptr) +{ + struct wmi_prb_resp_tmpl_ml_info_params *ml_info; + struct ath12k_prb_resp_tmpl_ml_info *ar_ml_info; + void *start = ptr; + struct wmi_tlv *tlv; + struct ath12k_link_vif *arvif = ath12k_mac_get_arvif(ar, vdev_id); + size_t ml_info_len = sizeof(*ml_info); + + if (!arvif) + return ptr; + + /* Add ML info */ + tlv = ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, ml_info_len); + ml_info = (struct wmi_prb_resp_tmpl_ml_info_params *)tlv->value; + + ar_ml_info = &arvif->ml_info; + ml_info->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PRB_RESP_TMPL_ML_INFO_CMD, + sizeof(*ml_info)); + ml_info->hw_link_id = cpu_to_le32(ar_ml_info->hw_link_id); + ml_info->cu_vdev_map_cat1_lo = cpu_to_le32(ar_ml_info->cu_vdev_map_cat1_lo); + ml_info->cu_vdev_map_cat1_hi = cpu_to_le32(ar_ml_info->cu_vdev_map_cat1_hi); + ml_info->cu_vdev_map_cat2_lo = cpu_to_le32(ar_ml_info->cu_vdev_map_cat2_lo); + ml_info->cu_vdev_map_cat2_hi = cpu_to_le32(ar_ml_info->cu_vdev_map_cat2_hi); + + ptr += TLV_HDR_SIZE + sizeof(*ml_info); + /* Reset CU bitmap and bpcc values*/ + memset(&arvif->ml_info, 0, sizeof(arvif->ml_info)); + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "wmi %ld bytes of additional data filled for prb resp CU\n", + (unsigned long)(ptr - start)); + return ptr; +} + int ath12k_wmi_probe_resp_tmpl(struct ath12k *ar, u32 vdev_id, struct sk_buff *tmpl) { @@ -3008,18 +5659,23 @@ struct wmi_tlv *tlv; struct sk_buff *skb; void *ptr; - int ret, len; + int ret, len, mlinfo_tlv_len = 0; size_t aligned_len = roundup(tmpl->len, 4); + struct ath12k_link_vif *arvif = ath12k_mac_get_arvif(ar, vdev_id); ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI vdev %i set probe response template\n", vdev_id); - len = sizeof(*cmd) + sizeof(*probe_info) + TLV_HDR_SIZE + aligned_len; + if (ath12k_mac_is_ml_arvif(arvif)) + mlinfo_tlv_len = TLV_HDR_SIZE + sizeof(struct wmi_prb_resp_tmpl_ml_info_params); + + len = sizeof(*cmd) + sizeof(*probe_info) + TLV_HDR_SIZE + aligned_len + mlinfo_tlv_len; skb = ath12k_wmi_alloc_skb(ar->wmi->wmi_ab, len); - if (!skb) + if (!skb) { + memset(&arvif->ml_info, 0, sizeof(arvif->ml_info)); return -ENOMEM; - + } cmd = (struct wmi_probe_tmpl_cmd *)skb->data; cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PRB_TMPL_CMD, sizeof(*cmd)); @@ -3040,6 +5696,10 @@ tlv = ptr; tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_BYTE, aligned_len); memcpy(tlv->value, tmpl->data, tmpl->len); + ptr += (TLV_HDR_SIZE + aligned_len); + + if (ath12k_mac_is_ml_arvif(arvif)) + ptr = ath12k_wmi_append_prb_resp_cu_params(ar, vdev_id, ptr); ret = ath12k_wmi_cmd_send(ar->wmi, skb, WMI_PRB_TMPL_CMDID); if (ret) { @@ -3176,13 +5836,25 @@ wmi_cfg->bpf_instruction_size = cpu_to_le32(tg_cfg->bpf_instruction_size); wmi_cfg->max_bssid_rx_filters = cpu_to_le32(tg_cfg->max_bssid_rx_filters); wmi_cfg->use_pdev_id = cpu_to_le32(tg_cfg->use_pdev_id); - wmi_cfg->flag1 = cpu_to_le32(tg_cfg->atf_config); + wmi_cfg->flag1 = cpu_to_le32(tg_cfg->atf_config) | WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; wmi_cfg->peer_map_unmap_version = cpu_to_le32(tg_cfg->peer_map_unmap_version); wmi_cfg->sched_params = cpu_to_le32(tg_cfg->sched_params); wmi_cfg->twt_ap_pdev_count = cpu_to_le32(tg_cfg->twt_ap_pdev_count); wmi_cfg->twt_ap_sta_count = cpu_to_le32(tg_cfg->twt_ap_sta_count); - wmi_cfg->host_service_flags = - cpu_to_le32(1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT); + wmi_cfg->flags2 = WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET | + WMI_RSRC_CFG_FLAGS2_INTRABSS_MEC_WDS_LEARNING_DISABLE | + u32_encode_bits(tg_cfg->dp_peer_meta_data_ver, + WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_VERSION); +#ifdef CONFIG_ATH12K_SAWF + wmi_cfg->flags2 |= (tg_cfg->sawf & ath12k_sawf_enable) ? + (WMI_RSRC_CFG_FLAGS2_SAWF_CONFIG_ENABLE_SET) : (0); +#endif /* CONFIG_ATH12K_SAWF */ + wmi_cfg->host_service_flags &= ~(1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT); + wmi_cfg->host_service_flags |= 1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT; + wmi_cfg->host_service_flags |= 1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REO_QREF_SUPPORT_BIT; + wmi_cfg->host_service_flags |= 1 << WMI_RSRC_CFG_HOST_SVC_FLAG_FULL_BW_NOL_SUPPORT_BIT; + wmi_cfg->ema_max_vap_cnt = tg_cfg->ema_max_vap_cnt; + wmi_cfg->ema_max_profile_period = tg_cfg->ema_max_profile_period; } static int ath12k_init_cmd_send(struct ath12k_wmi_pdev *wmi, @@ -3196,6 +5868,8 @@ struct ath12k_wmi_pdev_band_to_mac_params *band_to_mac; struct ath12k_wmi_host_mem_chunk_params *host_mem_chunks; struct wmi_tlv *tlv; + struct device *dev = ab->dev; + bool three_way_coex_enabled = false; size_t ret, len; void *ptr; u32 hw_mode_len = 0; @@ -3220,6 +5894,10 @@ ptr = skb->data + sizeof(*cmd); cfg = ptr; + three_way_coex_enabled = of_property_read_bool(dev->of_node, "qcom,btcoex"); + if (three_way_coex_enabled) + cfg->flag1 |= WMI_RSRC_CFG_FLAG1_THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT; + ath12k_wmi_copy_resource_config(cfg, &arg->res_cfg); cfg->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_RESOURCE_CONFIG, @@ -3390,6 +6068,12 @@ struct ath12k_wmi_base *wmi_sc = &ab->wmi_ab; struct ath12k_wmi_init_cmd_arg arg = {}; + if (test_bit(WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT, + ab->wmi_ab.svc_map)) + arg.res_cfg.is_reg_cc_ext_event_supported = true; + if (test_bit(WMI_TLV_SERVICE_RADAR_FLAGS_SUPPORT, ab->wmi_ab.svc_map)) + arg.res_cfg.is_full_bw_nol_feature_supported = true; + ab->hw_params->wmi_init(ab, &arg.res_cfg); arg.num_mem_chunks = wmi_sc->num_mem_chunks; @@ -3509,7 +6193,7 @@ cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_DMA_RING_CFG_REQ, sizeof(*cmd)); - cmd->pdev_id = cpu_to_le32(DP_SW2HW_MACID(arg->pdev_id)); + cmd->pdev_id = cpu_to_le32(arg->pdev_id); cmd->module_id = cpu_to_le32(arg->module_id); cmd->base_paddr_lo = cpu_to_le32(arg->base_paddr_lo); cmd->base_paddr_hi = cpu_to_le32(arg->base_paddr_hi); @@ -3633,6 +6317,7 @@ struct ath12k_dbring_buf_release_event param; int ret; + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, ath12k_wmi_dma_buf_parse, &arg); @@ -3654,6 +6339,102 @@ } } + +static int ath12k_wmi_tlv_mac_phy_chainmask_caps(struct ath12k_base *soc, + u16 len, const void *ptr, void *data) +{ + struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; + struct wmi_mac_phy_chainmask_caps *cmask_caps = (struct wmi_mac_phy_chainmask_caps *)ptr; + struct ath12k_chainmask_table *cmask_table; + struct ath12k_pdev_cap *pdev_cap; + u32 tag; + int i, j; + + if (!svc_rdy_ext->hw_mode_caps) + return -EINVAL; + + if ((!svc_rdy_ext->arg.num_chainmask_tables) || + (svc_rdy_ext->arg.num_chainmask_tables > ATH12K_MAX_CHAINMASK_TABLES)) + return -EINVAL; + + for (i = 0; i < svc_rdy_ext->arg.num_chainmask_tables; i++) { + cmask_table = &svc_rdy_ext->arg.chainmask_table[i]; + + for (j = 0; j < cmask_table->num_valid_chainmasks; j++) { + tag = FIELD_GET(WMI_TLV_TAG, cmask_caps->tlv_header); + + if (tag != WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY) + return -EPROTO; + + cmask_table->cap_list[j].chainmask = cmask_caps->chainmask; + cmask_table->cap_list[j].supported_caps = cmask_caps->supported_flags; + cmask_caps++; + ath12k_dbg(soc, ATH12K_DBG_WMI,"[id %d] chainmask %x supported_caps %x", + cmask_table->table_id, cmask_table->cap_list[j].chainmask, + cmask_table->cap_list[j].supported_caps); + } + } + + for (i = 0; i < soc->num_radios; i++) { + pdev_cap = &soc->pdevs[i].cap; + for (j = 0; j < svc_rdy_ext->n_mac_phy_chainmask_combo; j++) { + cmask_table = &svc_rdy_ext->arg.chainmask_table[j]; + if (cmask_table->table_id == pdev_cap->chainmask_table_id) + break; + } + for (j = 0; j < cmask_table->num_valid_chainmasks; j++) { + if (cmask_table->cap_list[j].supported_caps & WMI_SUPPORT_CHAIN_MASK_ADFS) + pdev_cap->adfs_chain_mask |= (1 << cmask_table->cap_list[j].chainmask); + } + ath12k_dbg(soc, ATH12K_DBG_WMI, "updated adfs chain mask %lx for pdev %d", + pdev_cap->adfs_chain_mask, i); + } + return 0; +} + +static void ath12k_wmi_free_chainmask_caps(struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext) +{ + int i; + + if (!svc_rdy_ext->arg.num_chainmask_tables) + return; + + for (i = 0; i < svc_rdy_ext->arg.num_chainmask_tables; i++) { + if (!svc_rdy_ext->arg.chainmask_table[i].cap_list) + continue; + kfree(svc_rdy_ext->arg.chainmask_table[i].cap_list); + svc_rdy_ext->arg.chainmask_table[i].cap_list = NULL; + } +} + +static int ath12k_wmi_tlv_mac_phy_chainmask_combo_parse(struct ath12k_base *soc, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct ath12k_wmi_svc_rdy_ext_parse *svc_rdy_ext = data; + struct wmi_mac_phy_chainmask_combo *cmask_combo = (struct wmi_mac_phy_chainmask_combo *) ptr; + u32 i = svc_rdy_ext->n_mac_phy_chainmask_combo; + struct ath12k_chainmask_table *cmask_table; + + if (tag != WMI_TAG_MAC_PHY_CHAINMASK_COMBO) + return -EPROTO; + + if (svc_rdy_ext->n_mac_phy_chainmask_combo >= svc_rdy_ext->arg.num_chainmask_tables) + return -ENOBUFS; + + cmask_table = &svc_rdy_ext->arg.chainmask_table[i]; + cmask_table->table_id = cmask_combo->chainmask_table_id; + cmask_table->num_valid_chainmasks = cmask_combo->num_valid_chainmask; + cmask_table->cap_list = kcalloc(cmask_combo->num_valid_chainmask, + sizeof(struct ath12k_chainmask_caps), + GFP_ATOMIC); + if (!svc_rdy_ext->arg.chainmask_table[i].cap_list) + return -ENOMEM; + + svc_rdy_ext->n_mac_phy_chainmask_combo++; + return 0; +} + static int ath12k_wmi_hw_mode_caps_parse(struct ath12k_base *soc, u16 tag, u16 len, const void *ptr, void *data) @@ -3954,6 +6735,7 @@ svc_rdy_ext->hw_caps = ptr; svc_rdy_ext->arg.num_hw_modes = le32_to_cpu(svc_rdy_ext->hw_caps->num_hw_modes); + svc_rdy_ext->arg.num_chainmask_tables = le32_to_cpu(svc_rdy_ext->hw_caps->num_chainmask_tables); break; case WMI_TAG_SOC_HAL_REG_CAPABILITIES: @@ -3988,8 +6770,21 @@ svc_rdy_ext->ext_hal_reg_done = true; } else if (!svc_rdy_ext->mac_phy_chainmask_combo_done) { + svc_rdy_ext->n_mac_phy_chainmask_combo = 0; + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_tlv_mac_phy_chainmask_combo_parse, + svc_rdy_ext); + if (ret) { + ath12k_warn(ab, "failed to parse chainmask combo tlv %d\n", ret); + return ret; + } svc_rdy_ext->mac_phy_chainmask_combo_done = true; } else if (!svc_rdy_ext->mac_phy_chainmask_cap_done) { + ret = ath12k_wmi_tlv_mac_phy_chainmask_caps(ab, len, ptr, svc_rdy_ext); + if (ret) { + ath12k_warn(ab, "failed to parse chainmask caps tlv %d\n", ret); + return ret; + } svc_rdy_ext->mac_phy_chainmask_cap_done = true; } else if (!svc_rdy_ext->oem_dma_ring_cap_done) { svc_rdy_ext->oem_dma_ring_cap_done = true; @@ -4027,9 +6822,12 @@ complete(&ab->wmi_ab.service_ready); kfree(svc_rdy_ext.mac_phy_caps); + ath12k_wmi_free_chainmask_caps(&svc_rdy_ext); return 0; err: + kfree(svc_rdy_ext.mac_phy_caps); + ath12k_wmi_free_chainmask_caps(&svc_rdy_ext); ath12k_wmi_free_dbring_caps(ab); return ret; } @@ -4038,10 +6836,23 @@ u16 tag, u16 len, const void *ptr, void *data) { + struct ath12k_wmi_pdev *wmi_handle = &ab->wmi_ab.wmi[0]; struct ath12k_wmi_svc_rdy_ext2_parse *parse = data; int ret; switch (tag) { + case WMI_TAG_SERVICE_READY_EXT2_EVENT: + ret = ath12k_pull_svc_ready_ext2(wmi_handle, ptr, + &parse->param); + if (ret) { + ath12k_warn(ab, "unable to extract ext params\n"); + return ret; + } + ab->max_msduq_per_tid = parse->param.max_msduq_per_tid; + ab->default_msduq_per_tid = parse->param.default_msduq_per_tid; + ab->chwidth_num_peer_caps = parse->param.chwidth_num_peer_caps; + break; + case WMI_TAG_ARRAY_STRUCT: if (!parse->dma_ring_cap_done) { ret = ath12k_wmi_dma_ring_caps(ab, len, ptr, @@ -4050,6 +6861,22 @@ return ret; parse->dma_ring_cap_done = true; + } else if (!parse->spectral_bin_scaling_done) { + /* To-Do: This is a place-holder as WMI tag for + * spectral scaling is before + * WMI_TAG_MAC_PHY_CAPABILITIES_EXT + */ + parse->spectral_bin_scaling_done = true; + } else if (!parse->mac_phy_caps_ext_done) { + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_tlv_mac_phy_caps_ext, + parse); + if (ret) { + ath12k_warn(ab, "failed to parse tlv %d\n", ret); + return ret; + } + + parse->mac_phy_caps_ext_done = true; } break; default: @@ -4062,7 +6889,7 @@ static int ath12k_service_ready_ext2_event(struct ath12k_base *ab, struct sk_buff *skb) { - struct ath12k_wmi_svc_rdy_ext2_parse svc_rdy_ext2 = { }; + struct ath12k_wmi_svc_rdy_ext2_parse svc_rdy_ext2 = { 0 }; int ret; ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, @@ -4152,6 +6979,140 @@ return reg_rule_ptr; } +static const char *ath12k_cc_status_to_str(enum ath12k_reg_cc_code code) +{ + switch (code) { + case REG_SET_CC_STATUS_PASS: + return "REG_SET_CC_STATUS_PASS"; + case REG_CURRENT_ALPHA2_NOT_FOUND: + return "REG_CURRENT_ALPHA2_NOT_FOUND"; + case REG_INIT_ALPHA2_NOT_FOUND: + return "REG_INIT_ALPHA2_NOT_FOUND"; + case REG_SET_CC_CHANGE_NOT_ALLOWED: + return "REG_SET_CC_CHANGE_NOT_ALLOWED"; + case REG_SET_CC_STATUS_NO_MEMORY: + return "REG_SET_CC_STATUS_NO_MEMORY"; + case REG_SET_CC_STATUS_FAIL: + return "REG_SET_CC_STATUS_FAIL"; + default: + return "unknown cc status"; + } +}; + +static const char *ath12k_super_reg_6g_to_str(enum reg_super_domain_6g domain_id) +{ + switch (domain_id) { + case FCC1_6G: + return "FCC1_6G"; + case ETSI1_6G: + return "ETSI1_6G"; + case ETSI2_6G: + return "ETSI2_6G"; + case APL1_6G: + return "APL1_6G"; + case FCC1_6G_CL: + return "FCC1_6G_CL"; + default: + return "unknown domain id"; + } +} + +static const char *ath12k_6g_client_type_to_str(enum wmi_reg_6g_client_type type) +{ + switch (type) { + case WMI_REG_DEFAULT_CLIENT: + return "DEFAULT CLIENT"; + case WMI_REG_SUBORDINATE_CLIENT: + return "SUBORDINATE CLIENT"; + default: + return "unknown client type"; + } +} + +static const char *ath12k_6g_ap_type_to_str(enum wmi_reg_6g_ap_type type) +{ + switch (type) { + case WMI_REG_INDOOR_AP: + return "INDOOR AP"; + case WMI_REG_STD_POWER_AP: + return "STANDARD POWER AP"; + case WMI_REG_VLP_AP: + return "VERY LOW POWER AP"; + default: + return "unknown AP type"; + } +} + +static const char *ath12k_sub_reg_6g_to_str(enum reg_subdomains_6g sub_id) +{ + switch (sub_id) { + case FCC1_CLIENT_LPI_REGULAR_6G: + return "FCC1_CLIENT_LPI_REGULAR_6G"; + case FCC1_CLIENT_SP_6G: + return "FCC1_CLIENT_SP_6G"; + case FCC1_AP_LPI_6G: + return "FCC1_AP_LPI_6G/FCC1_CLIENT_LPI_SUBORDINATE"; + case FCC1_AP_SP_6G: + return "FCC1_AP_SP_6G"; + case ETSI1_LPI_6G: + return "ETSI1_LPI_6G"; + case ETSI1_VLP_6G: + return "ETSI1_VLP_6G"; + case ETSI2_LPI_6G: + return "ETSI2_LPI_6G"; + case ETSI2_VLP_6G: + return "ETSI2_VLP_6G"; + case APL1_LPI_6G: + return "APL1_LPI_6G"; + case APL1_VLP_6G: + return "APL1_VLP_6G"; + case EMPTY_6G: + return "N/A"; + default: + return "unknown sub reg id"; + } +} + +static void ath12k_print_reg_rule(struct ath12k_base *ab, const char *prev, + u32 num_reg_rules, + const struct ath12k_reg_rule *reg_rule_ptr) +{ + const struct ath12k_reg_rule *reg_rule = reg_rule_ptr; + u32 count; + + ath12k_dbg(ab, ATH12K_DBG_WMI, "%s reg rules number %d\n", prev, num_reg_rules); + + for (count = 0; count < num_reg_rules; count++) { + ath12k_dbg(ab, ATH12K_DBG_WMI, + "reg rule %d: (%d - %d @ %d) (%d, %d) (FLAGS %d) (psd flag %d EIRP %d dB/MHz)\n", + count + 1, reg_rule->start_freq, reg_rule->end_freq, + reg_rule->max_bw, reg_rule->ant_gain, reg_rule->reg_power, + reg_rule->flags, reg_rule->psd_flag, reg_rule->psd_eirp); + reg_rule++; + } +} + +static u8 +ath12k_invalid_5g_reg_ext_rules_from_wmi(u32 num_reg_rules, + struct ath12k_wmi_reg_rule_ext_params *wmi_reg_rule) +{ + u8 num_invalid_5g_rules = 0; + u32 count, start_freq, end_freq; + + for (count = 0; count < num_reg_rules; count++) { + start_freq = FIELD_GET(REG_RULE_START_FREQ, + wmi_reg_rule[count].freq_info); + end_freq = FIELD_GET(REG_RULE_END_FREQ, + wmi_reg_rule[count].freq_info); + + if (start_freq >= ATH12K_MIN_6G_FREQ && + end_freq <= ATH12K_MAX_6G_FREQ) + num_invalid_5g_rules++; + } + + return num_invalid_5g_rules; +} + static int ath12k_pull_reg_chan_list_ext_update_ev(struct ath12k_base *ab, struct sk_buff *skb, struct ath12k_reg_info *reg_info) @@ -4163,9 +7124,11 @@ u32 num_6g_reg_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; u32 num_6g_reg_rules_cl[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; u32 total_reg_rules = 0; - int ret, i, j; + int ret, i, j, skip_6g_rules_in_5g_rules = 0; - ath12k_dbg(ab, ATH12K_DBG_WMI, "processing regulatory ext channel list\n"); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "%s: status_code %s", __func__, + ath12k_cc_status_to_str(reg_info->status_code)); tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); if (IS_ERR(tb)) { @@ -4190,6 +7153,18 @@ reg_info->num_6g_reg_rules_ap[WMI_REG_VLP_AP] = le32_to_cpu(ev->num_6g_reg_rules_ap_vlp); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "6g reg info client type %s rnr_tpe_usable %d unspecified_ap_usable %d AP sub domain: lpi %s , sp %s , vlp %s\n", + ath12k_6g_client_type_to_str(reg_info->client_type), + reg_info->rnr_tpe_usable, + reg_info->unspecified_ap_usable, + ath12k_sub_reg_6g_to_str + (ev->domain_code_6g_ap_lpi), + ath12k_sub_reg_6g_to_str + (ev->domain_code_6g_ap_sp), + ath12k_sub_reg_6g_to_str + (ev->domain_code_6g_ap_vlp)); + for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { reg_info->num_6g_reg_rules_cl[WMI_REG_INDOOR_AP][i] = le32_to_cpu(ev->num_6g_reg_rules_cl_lpi[i]); @@ -4197,6 +7172,14 @@ le32_to_cpu(ev->num_6g_reg_rules_cl_sp[i]); reg_info->num_6g_reg_rules_cl[WMI_REG_VLP_AP][i] = le32_to_cpu(ev->num_6g_reg_rules_cl_vlp[i]); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "6g AP BW: lpi %d - %d sp %d - %d vlp %d - %d\n", + ev->min_bw_6g_ap_lpi, + ev->max_bw_6g_ap_lpi, + ev->min_bw_6g_ap_sp, + ev->max_bw_6g_ap_sp, + ev->min_bw_6g_ap_vlp, + ev->max_bw_6g_ap_vlp); } num_2g_reg_rules = reg_info->num_2g_reg_rules; @@ -4255,20 +7238,6 @@ memcpy(reg_info->alpha2, &ev->alpha2, REG_ALPHA2_LEN); - /* FIXME: Currently FW includes 6G reg rule also in 5G rule - * list for country US. - * Having same 6G reg rule in 5G and 6G rules list causes - * intersect check to be true, and same rules will be shown - * multiple times in iw cmd. So added hack below to avoid - * parsing 6G rule from 5G reg rule list, and this can be - * removed later, after FW updates to remove 6G reg rule - * from 5G rules list. - */ - if (memcmp(reg_info->alpha2, "US", 2) == 0) { - reg_info->num_5g_reg_rules = REG_US_5G_NUM_REG_RULES; - num_5g_reg_rules = reg_info->num_5g_reg_rules; - } - reg_info->dfs_region = le32_to_cpu(ev->dfs_region); reg_info->phybitmap = le32_to_cpu(ev->phybitmap); reg_info->num_phy = le32_to_cpu(ev->num_phy); @@ -4326,10 +7295,15 @@ } ath12k_dbg(ab, ATH12K_DBG_WMI, - "%s:cc_ext %s dsf %d BW: min_2g %d max_2g %d min_5g %d max_5g %d", + "%s: status_code %s", __func__, + ath12k_cc_status_to_str(reg_info->status_code)); + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "%s:cc_ext %s dsf %d BW: min_2g %d max_2g %d min_5g %d max_5g %d phy_bitmap: 0x%x", __func__, reg_info->alpha2, reg_info->dfs_region, reg_info->min_bw_2g, reg_info->max_bw_2g, - reg_info->min_bw_5g, reg_info->max_bw_5g); + reg_info->min_bw_5g, reg_info->max_bw_5g, + reg_info->phybitmap); ath12k_dbg(ab, ATH12K_DBG_WMI, "num_2g_reg_rules %d num_5g_reg_rules %d", @@ -4368,10 +7342,35 @@ ath12k_warn(ab, "Unable to Allocate memory for 2g rules\n"); return -ENOMEM; } + ath12k_print_reg_rule(ab, "2g", + num_2g_reg_rules, + reg_info->reg_rules_2g_ptr); + } + ext_wmi_reg_rule += num_2g_reg_rules; + + /* FIXME: Currently FW includes 6G reg rule also in 5G rule + * list for few countries. + * Having same 6G reg rule in 5G and 6G rules list causes + * intersect check to be true, and same rules will be shown + * multiple times in iw cmd. So added logic below to avoid + * parsing 6G rule from 5G reg rule list, and this can be + * removed later, after FW updates to remove 6G reg rule + * from 5G rules list. + */ + skip_6g_rules_in_5g_rules = ath12k_invalid_5g_reg_ext_rules_from_wmi(num_5g_reg_rules, + ext_wmi_reg_rule); + + if(skip_6g_rules_in_5g_rules) { + ath12k_dbg(ab, ATH12K_DBG_WMI, + "CC: %s 5g reg rules number %d from fw, %d number of invalid 5g rules", + reg_info->alpha2, reg_info->num_5g_reg_rules, + skip_6g_rules_in_5g_rules); + + num_5g_reg_rules = num_5g_reg_rules - skip_6g_rules_in_5g_rules; + reg_info->num_5g_reg_rules = num_5g_reg_rules; } if (num_5g_reg_rules) { - ext_wmi_reg_rule += num_2g_reg_rules; reg_info->reg_rules_5g_ptr = create_ext_reg_rules_from_wmi(num_5g_reg_rules, ext_wmi_reg_rule); @@ -4381,9 +7380,18 @@ ath12k_warn(ab, "Unable to Allocate memory for 5g rules\n"); return -ENOMEM; } + ath12k_print_reg_rule(ab, "5g", + num_5g_reg_rules, + reg_info->reg_rules_5g_ptr); } - ext_wmi_reg_rule += num_5g_reg_rules; + /* We have adjusted the number of 5g reg rules via the hack above. + * Here, we adjust that many extra rules which came with 5g reg rules + * (for cc: US) + * + * NOTE: skip_6g_rules_in_5g_rules will be 0 for rest other cases. + */ + ext_wmi_reg_rule += num_5g_reg_rules + skip_6g_rules_in_5g_rules; for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) { reg_info->reg_rules_6g_ap_ptr[i] = @@ -4396,10 +7404,17 @@ return -ENOMEM; } + ath12k_print_reg_rule(ab, ath12k_6g_ap_type_to_str(i), + num_6g_reg_rules_ap[i], + reg_info->reg_rules_6g_ap_ptr[i]); + ext_wmi_reg_rule += num_6g_reg_rules_ap[i]; } for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++) { + ath12k_dbg(ab, ATH12K_DBG_WMI, + "AP type %s", ath12k_6g_ap_type_to_str(j)); + for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) { reg_info->reg_rules_6g_client_ptr[j][i] = create_ext_reg_rules_from_wmi(num_6g_reg_rules_cl[j][i], @@ -4411,6 +7426,10 @@ return -ENOMEM; } + ath12k_print_reg_rule(ab, ath12k_6g_client_type_to_str(i), + num_6g_reg_rules_cl[j][i], + reg_info->reg_rules_6g_client_ptr[j][i]); + ext_wmi_reg_rule += num_6g_reg_rules_cl[j][i]; } } @@ -4436,8 +7455,9 @@ reg_info->domain_code_6g_super_id = le32_to_cpu(ev->domain_code_6g_super_id); - ath12k_dbg(ab, ATH12K_DBG_WMI, "6g client_type: %d domain_code_6g_super_id: %d", - reg_info->client_type, reg_info->domain_code_6g_super_id); + ath12k_dbg(ab, ATH12K_DBG_WMI, "6g client type %s 6g super domain %s", + ath12k_6g_client_type_to_str(reg_info->client_type), + ath12k_super_reg_6g_to_str(reg_info->domain_code_6g_super_id)); ath12k_dbg(ab, ATH12K_DBG_WMI, "processed regulatory ext channel list\n"); @@ -4560,11 +7580,46 @@ return 0; } +static int ath12k_wmi_mgmt_rx_sub_tlv_parse(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_tlv_mgmt_rx_parse *parse = data; + struct ath12k_mgmt_rx_cu_arg *rx_cu_params; + struct ath12k_wmi_mgmt_rx_cu_params *rx_cu_params_tlv; + + switch (tag) { + case WMI_TAG_MLO_MGMT_RX_CU_PARAMS: + rx_cu_params = &parse->cu_params; + rx_cu_params_tlv = (struct ath12k_wmi_mgmt_rx_cu_params *)ptr; + rx_cu_params->cu_vdev_map[0] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_1, CU_VDEV_MAP_LB); + rx_cu_params->cu_vdev_map[1] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_1, CU_VDEV_MAP_HB); + rx_cu_params->cu_vdev_map[2] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_2, CU_VDEV_MAP_LB); + rx_cu_params->cu_vdev_map[3] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_2, CU_VDEV_MAP_HB); + rx_cu_params->cu_vdev_map[4] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_3, CU_VDEV_MAP_LB); + rx_cu_params->cu_vdev_map[5] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_3, CU_VDEV_MAP_HB); + rx_cu_params->cu_vdev_map[6] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_4, CU_VDEV_MAP_LB); + rx_cu_params->cu_vdev_map[7] = + le32_get_bits(rx_cu_params_tlv->cu_vdev_map_4, CU_VDEV_MAP_HB); + parse->mgmt_ml_info_done = true; + break; + } + return 0; +} + static int ath12k_wmi_tlv_mgmt_rx_parse(struct ath12k_base *ab, u16 tag, u16 len, const void *ptr, void *data) { struct wmi_tlv_mgmt_rx_parse *parse = data; + int ret; switch (tag) { case WMI_TAG_MGMT_RX_HDR: @@ -4574,12 +7629,130 @@ if (!parse->frame_buf_done) { parse->frame_buf = ptr; parse->frame_buf_done = true; + } else if (!parse->bpcc_buf_done) { + if (len == 0) + break; + parse->cu_params.bpcc_bufp = (void *)ptr; + parse->bpcc_buf_done = true; } break; + case WMI_TAG_MLO_MGMT_RX_REO_PARAMS: + parse->reo_params = (struct ath12k_wmi_mgmt_rx_reo_params *)ptr; + break; + case WMI_TAG_MLO_MGMT_RX_FW_CONSUMED_HDR: + parse->fw_consumed_reo_params = (struct ath12k_wmi_mgmt_rx_fw_consumed_hdr *)ptr; + break; + case WMI_TAG_ARRAY_STRUCT: + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_mgmt_rx_sub_tlv_parse, parse); + if (ret) { + ath12k_warn(ab, "failed to parse mgmt rx sub tlv %d\n", ret); + return ret; + } + break; + } + return 0; +} + +static int ath12k_pull_fw_consumed_mgmt_rx_params_tlv(struct ath12k_base *ab, + struct sk_buff *skb, + struct ath12k_wmi_mgmt_rx_arg *hdr) +{ + struct wmi_tlv_mgmt_rx_parse parse = { }; + int ret; + struct ath12k_wmi_mgmt_rx_fw_consumed_hdr *fw_con_reo_params_tlv = NULL; + + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_tlv_mgmt_rx_parse, + &parse); + if (ret) { + ath12k_warn(ab, "failed to parse mgmt rx tlv %d\n", ret); + return ret; } + + + fw_con_reo_params_tlv = parse.fw_consumed_reo_params; + + if (!fw_con_reo_params_tlv) { + ret = -EINVAL; + ath12k_warn(ab, "no fw_consumed_reo_params\n"); + return ret; + } + + hdr->pdev_id = fw_con_reo_params_tlv->pdev_id; + hdr->reo_params.valid = FIELD_GET(WMI_MGMT_RX_FW_CONSUMED_PARAM_MGMT_PKT_CTR_VALID_GET, + fw_con_reo_params_tlv->mgmt_pkt_ctr_info); + hdr->reo_params.global_timestamp = fw_con_reo_params_tlv->global_timestamp; + hdr->reo_params.mgmt_pkt_ctr = FIELD_GET(WMI_MGMT_RX_FW_CONSUMED_PARAM_MGMT_PKT_CTR_GET, + fw_con_reo_params_tlv->mgmt_pkt_ctr_info); + hdr->reo_params.duration_us = fw_con_reo_params_tlv->rx_ppdu_duration_us; + hdr->reo_params.start_timestamp = hdr->reo_params.global_timestamp; + hdr->reo_params.end_timestamp = hdr->reo_params.start_timestamp + + hdr->reo_params.duration_us; + + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "FW Consumed : Mgmt Re-order ingress: valid %u global_ts %u pkt_ctr %u\n", + hdr->reo_params.valid, + hdr->reo_params.global_timestamp, + hdr->reo_params.mgmt_pkt_ctr); + return 0; } +static u32 ath12k_get_ar_next_vdev_pos(struct ath12k *ar, u32 pos) +{ + bool bit; + u32 i = 0; + + for (i = pos; i < MAX_AP_MLDS_PER_LINK; i++) { + bit = ar->allocated_vdev_map & (1LL << i); + if (bit) + break; + } + return i; +} + +static void ath12k_update_cu_params(struct ath12k_base *ab, + struct ath12k_mgmt_rx_cu_arg *cu_params) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k *ar; + struct ath12k_link_vif *arvif; + bool critical_flag; + u8 hw_link_id; + u8 *bpcc_ptr, *bpcc_bufp; + u32 vdev_id, pos = 0; + int i; + + if (!cu_params->bpcc_bufp) + return; + /* Iterate over all the valid hw links */ + for (hw_link_id = 0; hw_link_id < CU_MAX_MLO_LINKS; hw_link_id++) { + ar = rcu_dereference(ag->hw_links[hw_link_id]); + if (!ar) + continue; + pos = 0; + for (i = 0; i < ar->num_created_vdevs; i++) { + pos = ath12k_get_ar_next_vdev_pos(ar, pos); + vdev_id = pos; + pos++; + arvif = ath12k_mac_get_arvif(ar, vdev_id); + if (!arvif) + continue; + if (arvif->is_up && arvif->ahvif->vif->valid_links) { + critical_flag = cu_params->cu_vdev_map[hw_link_id] & (1 << i); + bpcc_bufp = cu_params->bpcc_bufp; + bpcc_ptr = bpcc_bufp + + ((hw_link_id * MAX_AP_MLDS_PER_LINK) + i); + WARN(1, "mlo not supported"); + /* ieee80211_critical_update(arvif->ahvif->vif, */ + /* arvif->link_id, */ + /* critical_flag, */ + /* *bpcc_ptr); */ + } + } + } +} + static int ath12k_pull_mgmt_rx_params_tlv(struct ath12k_base *ab, struct sk_buff *skb, struct ath12k_wmi_mgmt_rx_arg *hdr) @@ -4588,7 +7761,9 @@ const struct ath12k_wmi_mgmt_rx_params *ev; const u8 *frame; int i, ret; + struct ath12k_wmi_mgmt_rx_reo_params *reo_params_tlv = NULL; + memset(&parse, 0, sizeof(parse)); ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, ath12k_wmi_tlv_mgmt_rx_parse, &parse); @@ -4600,6 +7775,13 @@ ev = parse.fixed; frame = parse.frame_buf; + reo_params_tlv = parse.reo_params; + if (!reo_params_tlv) { + ret = -EINVAL; + ath12k_warn(ab, "no reo_params_tlv\n"); + return ret; + } + if (!ev || !frame) { ath12k_warn(ab, "failed to fetch mgmt rx hdr"); return -EPROTO; @@ -4620,6 +7802,29 @@ for (i = 0; i < ATH_MAX_ANTENNA; i++) hdr->rssi_ctl[i] = le32_to_cpu(ev->rssi_ctl[i]); + hdr->reo_params.pdev_id = ev->pdev_id; + + hdr->reo_params.valid = FIELD_GET(WMI_MGMT_RX_REO_PARAM_MGMT_PKT_CTR_VALID_GET, + reo_params_tlv->mgmt_pkt_ctr_link_info); + hdr->reo_params.global_timestamp = reo_params_tlv->global_timestamp; + hdr->reo_params.mgmt_pkt_ctr = FIELD_GET(WMI_MGMT_RX_REO_PARAM_MGMT_PKT_CTR_GET, + reo_params_tlv->mgmt_pkt_ctr_link_info); + hdr->reo_params.duration_us = reo_params_tlv->rx_ppdu_duration_us; + hdr->reo_params.start_timestamp = hdr->reo_params.global_timestamp; + hdr->reo_params.end_timestamp = hdr->reo_params.start_timestamp + + hdr->reo_params.duration_us; + + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Mgmt Re-order ingress: channel %d valid %u global_ts %u pkt_ctr %u\n", + hdr->channel, + hdr->reo_params.valid, + hdr->reo_params.global_timestamp, + hdr->reo_params.mgmt_pkt_ctr); + + if (parse.mgmt_ml_info_done) { + rcu_read_lock(); + ath12k_update_cu_params(ab, &parse.cu_params); + rcu_read_unlock(); + } if (skb->len < (frame - skb->data) + hdr->buf_len) { ath12k_warn(ab, "invalid length in mgmt rx hdr ev"); return -EPROTO; @@ -4635,12 +7840,20 @@ } static int wmi_process_mgmt_tx_comp(struct ath12k *ar, u32 desc_id, - u32 status) + u32 status, + u32 ack_rssi) { struct sk_buff *msdu; struct ieee80211_tx_info *info; struct ath12k_skb_cb *skb_cb; + struct ieee80211_hdr *hdr; + struct ieee80211_vif *vif; + struct ath12k_vif *ahvif; + struct ath12k_mgmt_frame_stats *mgmt_stats; + u16 frm_type; + int num_mgmt; + spin_lock_bh(&ar->data_lock); spin_lock_bh(&ar->txmgmt_idr_lock); msdu = idr_find(&ar->txmgmt_idr, desc_id); @@ -4648,6 +7861,7 @@ ath12k_warn(ar->ab, "received mgmt tx compl for invalid msdu_id: %d\n", desc_id); spin_unlock_bh(&ar->txmgmt_idr_lock); + spin_unlock_bh(&ar->data_lock); return -ENOENT; } @@ -4657,16 +7871,47 @@ skb_cb = ATH12K_SKB_CB(msdu); dma_unmap_single(ar->ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); + hdr = (struct ieee80211_hdr *)msdu->data; + + if (ieee80211_is_mgmt(hdr->frame_control)) { + frm_type = FIELD_GET(IEEE80211_FCTL_STYPE, hdr->frame_control); + vif = skb_cb->vif; + + if (!vif) { + ath12k_warn(ar->ab, "failed to find vif to update txcompl mgmt stats\n"); + goto skip_mgmt_stats; + } + + ahvif = ath12k_vif_to_ahvif(vif); + mgmt_stats = &ahvif->mgmt_stats; + + if (!status) + mgmt_stats->tx_compl_succ[frm_type]++; + else + mgmt_stats->tx_compl_fail[frm_type]++; + } + +skip_mgmt_stats: + spin_unlock_bh(&ar->data_lock); + info = IEEE80211_SKB_CB(msdu); - if ((!(info->flags & IEEE80211_TX_CTL_NO_ACK)) && !status) + if ((!(info->flags & IEEE80211_TX_CTL_NO_ACK)) && !status) { info->flags |= IEEE80211_TX_STAT_ACK; + info->status.ack_signal = ack_rssi; + info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; + } + + ieee80211_tx_status_irqsafe(ar->ah->hw, msdu); - ieee80211_tx_status_irqsafe(ar->hw, msdu); + num_mgmt = atomic_dec_if_positive(&ar->num_pending_mgmt_tx); /* WARN when we received this event without doing any mgmt tx */ - if (atomic_dec_if_positive(&ar->num_pending_mgmt_tx) < 0) + if (num_mgmt < 0) WARN_ON_ONCE(1); + if (atomic_read(&ar->flush_request) && !num_mgmt) + wake_up(&ar->tx_empty_waitq); + return 0; } @@ -4695,6 +7940,70 @@ param->pdev_id = ev->pdev_id; param->desc_id = ev->desc_id; param->status = ev->status; + param->ppdu_id = ev->ppdu_id; + param->ack_rssi = ev->ack_rssi; + + kfree(tb); + return 0; +} + +static void wmi_process_offchan_tx_comp(struct ath12k *ar, u32 desc_id, + u32 status) +{ + struct sk_buff *msdu; + struct ath12k_skb_cb *skb_cb; + struct ieee80211_tx_info *info; + + spin_lock_bh(&ar->data_lock); + spin_lock_bh(&ar->txmgmt_idr_lock); + msdu = idr_find(&ar->txmgmt_idr, desc_id); + + if (!msdu) { + spin_unlock_bh(&ar->txmgmt_idr_lock); + spin_unlock_bh(&ar->data_lock); + ath12k_warn(ar->ab, "received offchan tx compl for invalid msdu_id: %d\n", + desc_id); + return; + } + + idr_remove(&ar->txmgmt_idr, desc_id); + spin_unlock_bh(&ar->txmgmt_idr_lock); + + skb_cb = ATH12K_SKB_CB(msdu); + dma_unmap_single(ar->ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); + + spin_unlock_bh(&ar->data_lock); + + info = IEEE80211_SKB_CB(msdu); + if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) && !status) + info->flags |= IEEE80211_TX_STAT_ACK; + + ieee80211_tx_status_irqsafe(ar->ah->hw, msdu); +} + +static int ath12k_pull_offchan_tx_compl_param_tlv(struct ath12k_base *ab, + struct sk_buff *skb, + struct wmi_offchan_data_tx_compl_event *params) +{ + const void **tb; + const struct wmi_offchan_data_tx_compl_event *ev; + int ret; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, "failed to parse tlv: %d\n", ret); + return ret; + } + + ev = tb[WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT]; + if (!ev) { + ath12k_warn(ab, "failed to fetch offchan tx compl ev\n"); + kfree(tb); + return -EPROTO; + } + + *params = *ev; kfree(tb); return 0; @@ -4714,6 +8023,8 @@ break; case ATH12K_SCAN_STARTING: ar->scan.state = ATH12K_SCAN_RUNNING; + if (ar->scan.is_roc) + ieee80211_ready_on_channel(ar->ah->hw); complete(&ar->scan.started); break; } @@ -4795,7 +8106,10 @@ break; case ATH12K_SCAN_RUNNING: case ATH12K_SCAN_ABORTING: - ar->scan_channel = ieee80211_get_channel(ar->hw->wiphy, freq); + ar->scan_channel = ieee80211_get_channel(ar->ah->hw->wiphy, + freq); + if (ar->scan.is_roc && ar->scan.roc_freq == freq) + complete(&ar->scan.on_channel); break; } } @@ -4896,7 +8210,9 @@ return -EPROTO; } - arg->mac_addr = ev->peer_macaddr.addr; + ether_addr_copy(arg->mac_addr, ev->peer_macaddr.addr); + arg->reason = __le32_to_cpu(ev->reason); + arg->rssi = __le32_to_cpu(ev->rssi); kfree(tb); return 0; @@ -4934,13 +8250,14 @@ static int freq_to_idx(struct ath12k *ar, int freq) { struct ieee80211_supported_band *sband; + struct ieee80211_hw *hw = ar->ah->hw; int band, ch, idx = 0; for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { if (!ar->mac.sbands[band].channels) continue; - sband = ar->hw->wiphy->bands[band]; + sband = hw->wiphy->bands[band]; if (!sband) continue; @@ -5091,31 +8408,573 @@ return 0; } -static int -ath12k_pull_pdev_temp_ev(struct ath12k_base *ab, u8 *evt_buf, - u32 len, const struct wmi_pdev_temperature_event *ev) +static void ath12k_wmi_pull_pdev_stats_base(const struct wmi_pdev_stats_base *src, + struct ath12k_fw_stats_pdev *dst) +{ + dst->ch_noise_floor = src->chan_nf; + dst->tx_frame_count = src->tx_frame_count; + dst->rx_frame_count = src->rx_frame_count; + dst->rx_clear_count = src->rx_clear_count; + dst->cycle_count = src->cycle_count; + dst->phy_err_count = src->phy_err_count; + dst->chan_tx_power = src->chan_tx_pwr; +} + +static void +ath12k_wmi_pull_pdev_stats_tx(const struct wmi_pdev_stats_tx *src, + struct ath12k_fw_stats_pdev *dst) +{ + dst->comp_queued = src->comp_queued; + dst->comp_delivered = src->comp_delivered; + dst->msdu_enqued = src->msdu_enqued; + dst->mpdu_enqued = src->mpdu_enqued; + dst->wmm_drop = src->wmm_drop; + dst->local_enqued = src->local_enqued; + dst->local_freed = src->local_freed; + dst->hw_queued = src->hw_queued; + dst->hw_reaped = src->hw_reaped; + dst->underrun = src->underrun; + dst->tx_abort = src->tx_abort; + dst->mpdus_requed = src->mpdus_requed; + dst->tx_ko = src->tx_ko; + dst->data_rc = src->data_rc; + dst->self_triggers = src->self_triggers; + dst->sw_retry_failure = src->sw_retry_failure; + dst->illgl_rate_phy_err = src->illgl_rate_phy_err; + dst->pdev_cont_xretry = src->pdev_cont_xretry; + dst->pdev_tx_timeout = src->pdev_tx_timeout; + dst->pdev_resets = src->pdev_resets; + dst->stateless_tid_alloc_failure = src->stateless_tid_alloc_failure; + dst->phy_underrun = src->phy_underrun; + dst->txop_ovf = src->txop_ovf; +} + +static void ath12k_wmi_pull_pdev_stats_rx(const struct wmi_pdev_stats_rx *src, + struct ath12k_fw_stats_pdev *dst) +{ + dst->mid_ppdu_route_change = src->mid_ppdu_route_change; + dst->status_rcvd = src->status_rcvd; + dst->r0_frags = src->r0_frags; + dst->r1_frags = src->r1_frags; + dst->r2_frags = src->r2_frags; + dst->r3_frags = src->r3_frags; + dst->htt_msdus = src->htt_msdus; + dst->htt_mpdus = src->htt_mpdus; + dst->loc_msdus = src->loc_msdus; + dst->loc_mpdus = src->loc_mpdus; + dst->oversize_amsdu = src->oversize_amsdu; + dst->phy_errs = src->phy_errs; + dst->phy_err_drop = src->phy_err_drop; + dst->mpdu_errs = src->mpdu_errs; +} + +static void +ath12k_wmi_pull_vdev_stats(const struct wmi_vdev_stats *src, + struct ath12k_fw_stats_vdev *dst) +{ + int i; + + dst->vdev_id = src->vdev_id; + dst->beacon_snr = src->beacon_snr; + dst->data_snr = src->data_snr; + dst->num_rx_frames = src->num_rx_frames; + dst->num_rts_fail = src->num_rts_fail; + dst->num_rts_success = src->num_rts_success; + dst->num_rx_err = src->num_rx_err; + dst->num_rx_discard = src->num_rx_discard; + dst->num_tx_not_acked = src->num_tx_not_acked; + + for (i = 0; i < ARRAY_SIZE(src->num_tx_frames); i++) + dst->num_tx_frames[i] = src->num_tx_frames[i]; + + for (i = 0; i < ARRAY_SIZE(src->num_tx_frames_retries); i++) + dst->num_tx_frames_retries[i] = src->num_tx_frames_retries[i]; + + for (i = 0; i < ARRAY_SIZE(src->num_tx_frames_failures); i++) + dst->num_tx_frames_failures[i] = src->num_tx_frames_failures[i]; + + for (i = 0; i < ARRAY_SIZE(src->tx_rate_history); i++) + dst->tx_rate_history[i] = src->tx_rate_history[i]; + + for (i = 0; i < ARRAY_SIZE(src->beacon_rssi_history); i++) + dst->beacon_rssi_history[i] = src->beacon_rssi_history[i]; +} + +static void +ath12k_wmi_pull_bcn_stats(const struct wmi_bcn_stats *src, + struct ath12k_fw_stats_bcn *dst) +{ + dst->vdev_id = src->vdev_id; + dst->tx_bcn_succ_cnt = src->tx_bcn_succ_cnt; + dst->tx_bcn_outage_cnt = src->tx_bcn_outage_cnt; +} + +int ath12k_wmi_pull_fw_stats(struct ath12k_base *ab, struct sk_buff *skb, + struct ath12k_fw_stats *stats) { const void **tb; - int ret; + const struct wmi_stats_event *ev; + const void *data; + int i, ret; + struct ath12k *ar; + u32 len = skb->len; - tb = ath12k_wmi_tlv_parse_alloc(ab, evt_buf, len, GFP_ATOMIC); + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, len, GFP_ATOMIC); if (IS_ERR(tb)) { ret = PTR_ERR(tb); ath12k_warn(ab, "failed to parse tlv: %d\n", ret); return ret; } - ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT]; - if (!ev) { - ath12k_warn(ab, "failed to fetch pdev temp ev"); + ev = tb[WMI_TAG_STATS_EVENT]; + data = tb[WMI_TAG_ARRAY_BYTE]; + if (!ev || !data) { + ath12k_warn(ab, "failed to fetch update stats ev"); kfree(tb); return -EPROTO; } + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi stats update ev pdev_id %d pdev %i vdev %i bcn %i\n", + ev->pdev_id, + ev->num_pdev_stats, ev->num_vdev_stats, + ev->num_bcn_stats); + + stats->pdev_id = le32_to_cpu(ev->pdev_id); + stats->stats_id = 0; + + ar = ath12k_mac_get_ar_by_pdev_id(ab, ev->pdev_id); + + if (!ar) + return -EPROTO; + + for (i = 0; i < le32_to_cpu(ev->num_pdev_stats); i++) { + const struct wmi_pdev_stats *src; + struct ath12k_fw_stats_pdev *dst; + + src = data; + if (len < sizeof(*src)) { + kfree(tb); + return -EPROTO; + } + + stats->stats_id = WMI_REQUEST_PDEV_STAT; + + data += sizeof(*src); + len -= sizeof(*src); + + dst = kzalloc(sizeof(*dst), GFP_ATOMIC); + if (!dst) + continue; + + ath12k_wmi_pull_pdev_stats_base(&src->base, dst); + ath12k_wmi_pull_pdev_stats_tx(&src->tx, dst); + ath12k_wmi_pull_pdev_stats_rx(&src->rx, dst); + list_add_tail(&dst->list, &stats->pdevs); + } + + for (i = 0; i < le32_to_cpu(ev->num_vdev_stats); i++) { + const struct wmi_vdev_stats *src; + struct ath12k_fw_stats_vdev *dst; + + src = data; + if (len < sizeof(*src)) { + kfree(tb); + return -EPROTO; + } + + stats->stats_id = WMI_REQUEST_VDEV_STAT; + + data += sizeof(*src); + len -= sizeof(*src); + + dst = kzalloc(sizeof(*dst), GFP_ATOMIC); + if (!dst) + continue; + + ath12k_wmi_pull_vdev_stats(src, dst); + list_add_tail(&dst->list, &stats->vdevs); + } + + for (i = 0; i < le32_to_cpu(ev->num_bcn_stats); i++) { + const struct wmi_bcn_stats *src; + struct ath12k_fw_stats_bcn *dst; + + src = data; + if (len < sizeof(*src)) { + kfree(tb); + return -EPROTO; + } + + stats->stats_id = WMI_REQUEST_BCN_STAT; + + data += sizeof(*src); + len -= sizeof(*src); + + dst = kzalloc(sizeof(*dst), GFP_ATOMIC); + if (!dst) + continue; + + ath12k_wmi_pull_bcn_stats(src, dst); + list_add_tail(&dst->list, &stats->bcn); + } + kfree(tb); return 0; } +size_t ath12k_wmi_fw_stats_num_vdevs(struct list_head *head) +{ + struct ath12k_fw_stats_vdev *i; + size_t num = 0; + + list_for_each_entry(i, head, list) + ++num; + + return num; +} + +static size_t ath12k_wmi_fw_stats_num_bcn(struct list_head *head) +{ + struct ath12k_fw_stats_bcn *i; + size_t num = 0; + + list_for_each_entry(i, head, list) + ++num; + + return num; +} + +static void +ath12k_wmi_fw_pdev_base_stats_fill(const struct ath12k_fw_stats_pdev *pdev, + char *buf, u32 *length, u64 fw_soc_drop_cnt) +{ + u32 len = *length; + u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "\n"); + len += scnprintf(buf + len, buf_len - len, "%30s\n", + "ath12k PDEV stats"); + len += scnprintf(buf + len, buf_len - len, "%30s\n\n", + "================="); + + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Channel noise floor", pdev->ch_noise_floor); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "Channel TX power", pdev->chan_tx_power); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "TX frame count", pdev->tx_frame_count); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "RX frame count", pdev->rx_frame_count); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "RX clear count", pdev->rx_clear_count); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "Cycle count", pdev->cycle_count); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "PHY error count", pdev->phy_err_count); + len += scnprintf(buf + len, buf_len - len, "%30s %10llu\n", + "soc drop count", fw_soc_drop_cnt); + + *length = len; +} + +static void +ath12k_wmi_fw_pdev_tx_stats_fill(const struct ath12k_fw_stats_pdev *pdev, + char *buf, u32 *length) +{ + u32 len = *length; + u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "\n%30s\n", + "ath12k PDEV TX stats"); + len += scnprintf(buf + len, buf_len - len, "%30s\n\n", + "===================="); + + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "HTT cookies queued", pdev->comp_queued); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "HTT cookies disp.", pdev->comp_delivered); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MSDU queued", pdev->msdu_enqued); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MPDU queued", pdev->mpdu_enqued); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MSDUs dropped", pdev->wmm_drop); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Local enqued", pdev->local_enqued); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Local freed", pdev->local_freed); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "HW queued", pdev->hw_queued); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "PPDUs reaped", pdev->hw_reaped); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Num underruns", pdev->underrun); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "PPDUs cleaned", pdev->tx_abort); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MPDUs requeued", pdev->mpdus_requed); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "Excessive retries", pdev->tx_ko); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "HW rate", pdev->data_rc); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "Sched self triggers", pdev->self_triggers); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "Dropped due to SW retries", + pdev->sw_retry_failure); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "Illegal rate phy errors", + pdev->illgl_rate_phy_err); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "PDEV continuous xretry", pdev->pdev_cont_xretry); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "TX timeout", pdev->pdev_tx_timeout); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "PDEV resets", pdev->pdev_resets); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "Stateless TIDs alloc failures", + pdev->stateless_tid_alloc_failure); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "PHY underrun", pdev->phy_underrun); + len += scnprintf(buf + len, buf_len - len, "%30s %10u\n", + "MPDU is more than txop limit", pdev->txop_ovf); + *length = len; +} + +static void +ath12k_wmi_fw_pdev_rx_stats_fill(const struct ath12k_fw_stats_pdev *pdev, + char *buf, u32 *length) +{ + u32 len = *length; + u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "\n%30s\n", + "ath12k PDEV RX stats"); + len += scnprintf(buf + len, buf_len - len, "%30s\n\n", + "===================="); + + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Mid PPDU route change", + pdev->mid_ppdu_route_change); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Tot. number of statuses", pdev->status_rcvd); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Extra frags on rings 0", pdev->r0_frags); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Extra frags on rings 1", pdev->r1_frags); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Extra frags on rings 2", pdev->r2_frags); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Extra frags on rings 3", pdev->r3_frags); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MSDUs delivered to HTT", pdev->htt_msdus); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MPDUs delivered to HTT", pdev->htt_mpdus); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MSDUs delivered to stack", pdev->loc_msdus); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MPDUs delivered to stack", pdev->loc_mpdus); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "Oversized AMSUs", pdev->oversize_amsdu); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "PHY errors", pdev->phy_errs); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "PHY errors drops", pdev->phy_err_drop); + len += scnprintf(buf + len, buf_len - len, "%30s %10d\n", + "MPDU errors (FCS, MIC, ENC)", pdev->mpdu_errs); + *length = len; +} + +static void +ath12k_wmi_fw_vdev_stats_fill(struct ath12k *ar, + const struct ath12k_fw_stats_vdev *vdev, + char *buf, u32 *length) +{ + u32 len = *length; + u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; + struct ath12k_link_vif *arvif = ath12k_mac_get_arvif(ar, vdev->vdev_id); + u8 *vif_macaddr; + int i; + + /* VDEV stats has all the active VDEVs of other PDEVs as well, + * ignoring those not part of requested PDEV + */ + if (!arvif) + return; + + vif_macaddr = arvif->addr; + + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "VDEV ID", vdev->vdev_id); + len += scnprintf(buf + len, buf_len - len, "%30s %pM\n", + "VDEV MAC address", vif_macaddr); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "beacon snr", vdev->beacon_snr); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "data snr", vdev->data_snr); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "num rx frames", vdev->num_rx_frames); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "num rts fail", vdev->num_rts_fail); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "num rts success", vdev->num_rts_success); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "num rx err", vdev->num_rx_err); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "num rx discard", vdev->num_rx_discard); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "num tx not acked", vdev->num_tx_not_acked); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "rx msdu byte cnt", arvif->vdev_stats.rx_msdu_byte_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "rx msdu pkt cnt", arvif->vdev_stats.rx_msdu_pkt_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "ack msdu byte cnt", arvif->vdev_stats.tx_msdu_byte_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "ack msdu pkt cnt", arvif->vdev_stats.tx_msdu_pkt_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "retry byte cnt", arvif->vdev_stats.tx_retry_byte_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "retry pkt cnt", arvif->vdev_stats.tx_retry_pkt_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "drop byte cnt", arvif->vdev_stats.tx_drop_byte_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "drop pkt cnt", arvif->vdev_stats.tx_drop_pkt_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "age out drop byte cnt", + arvif->vdev_stats.tx_msdu_ttl_byte_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %llu\n", + "age out drop pkt cnt", + arvif->vdev_stats.tx_msdu_ttl_pkt_cnt); + + for (i = 0 ; i < ARRAY_SIZE(vdev->num_tx_frames); i++) + len += scnprintf(buf + len, buf_len - len, + "%25s [%02d] %u\n", + "num tx frames", i, + vdev->num_tx_frames[i]); + + for (i = 0 ; i < ARRAY_SIZE(vdev->num_tx_frames_retries); i++) + len += scnprintf(buf + len, buf_len - len, + "%25s [%02d] %u\n", + "num tx frames retries", i, + vdev->num_tx_frames_retries[i]); + + for (i = 0 ; i < ARRAY_SIZE(vdev->num_tx_frames_failures); i++) + len += scnprintf(buf + len, buf_len - len, + "%25s [%02d] %u\n", + "num tx frames failures", i, + vdev->num_tx_frames_failures[i]); + + for (i = 0 ; i < ARRAY_SIZE(vdev->tx_rate_history); i++) + len += scnprintf(buf + len, buf_len - len, + "%25s [%02d] 0x%08x\n", + "tx rate history", i, + vdev->tx_rate_history[i]); + + for (i = 0 ; i < ARRAY_SIZE(vdev->beacon_rssi_history); i++) + len += scnprintf(buf + len, buf_len - len, + "%25s [%02d] %u\n", + "beacon rssi history", i, + vdev->beacon_rssi_history[i]); + + len += scnprintf(buf + len, buf_len - len, "\n"); + *length = len; +} + +static void +ath12k_wmi_fw_bcn_stats_fill(struct ath12k *ar, + const struct ath12k_fw_stats_bcn *bcn, + char *buf, u32 *length) +{ + u32 len = *length; + u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; + struct ath12k_link_vif *arvif = ath12k_mac_get_arvif(ar, bcn->vdev_id); + u8 *vdev_macaddr; + + if (!arvif) { + ath12k_warn(ar->ab, "invalid vdev id %d in bcn stats", + bcn->vdev_id); + return; + } + + vdev_macaddr = arvif->addr; + + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "VDEV ID", bcn->vdev_id); + len += scnprintf(buf + len, buf_len - len, "%30s %pM\n", + "VDEV MAC address", vdev_macaddr); + len += scnprintf(buf + len, buf_len - len, "%30s\n\n", + "================"); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "Num of beacon tx success", bcn->tx_bcn_succ_cnt); + len += scnprintf(buf + len, buf_len - len, "%30s %u\n", + "Num of beacon tx failures", bcn->tx_bcn_outage_cnt); + + len += scnprintf(buf + len, buf_len - len, "\n"); + *length = len; +} + +void ath12k_wmi_fw_stats_fill(struct ath12k *ar, + struct ath12k_fw_stats *fw_stats, + u32 stats_id, char *buf) +{ + u32 len = 0; + u32 buf_len = ATH12K_FW_STATS_BUF_SIZE; + const struct ath12k_fw_stats_pdev *pdev; + const struct ath12k_fw_stats_vdev *vdev; + const struct ath12k_fw_stats_bcn *bcn; + size_t num_bcn; + + spin_lock_bh(&ar->data_lock); + + if (stats_id == WMI_REQUEST_PDEV_STAT) { + pdev = list_first_entry_or_null(&fw_stats->pdevs, + struct ath12k_fw_stats_pdev, list); + if (!pdev) { + ath12k_warn(ar->ab, "failed to get pdev stats\n"); + goto unlock; + } + + ath12k_wmi_fw_pdev_base_stats_fill(pdev, buf, &len, + ar->ab->fw_soc_drop_count); + ath12k_wmi_fw_pdev_tx_stats_fill(pdev, buf, &len); + ath12k_wmi_fw_pdev_rx_stats_fill(pdev, buf, &len); + } + + if (stats_id == WMI_REQUEST_VDEV_STAT) { + len += scnprintf(buf + len, buf_len - len, "\n"); + len += scnprintf(buf + len, buf_len - len, "%30s\n", + "ath12k VDEV stats"); + len += scnprintf(buf + len, buf_len - len, "%30s\n\n", + "================="); + + list_for_each_entry(vdev, &fw_stats->vdevs, list) + ath12k_wmi_fw_vdev_stats_fill(ar, vdev, buf, &len); + } + + if (stats_id == WMI_REQUEST_BCN_STAT) { + num_bcn = ath12k_wmi_fw_stats_num_bcn(&fw_stats->bcn); + + len += scnprintf(buf + len, buf_len - len, "\n"); + len += scnprintf(buf + len, buf_len - len, "%30s (%zu)\n", + "ath12k Beacon stats", num_bcn); + len += scnprintf(buf + len, buf_len - len, "%30s\n\n", + "==================="); + + list_for_each_entry(bcn, &fw_stats->bcn, list) + ath12k_wmi_fw_bcn_stats_fill(ar, bcn, buf, &len); + } + +unlock: + spin_unlock_bh(&ar->data_lock); + + if (len >= buf_len) + buf[len - 1] = 0; + else + buf[len] = 0; +} + static void ath12k_wmi_op_ep_tx_credits(struct ath12k_base *ab) { /* try to send pending beacons first. they take priority */ @@ -5125,42 +8984,47 @@ static void ath12k_wmi_htc_tx_complete(struct ath12k_base *ab, struct sk_buff *skb) { + struct ath12k_wmi_pdev *wmi = NULL; + u32 i; + u8 wmi_ep_count; + u8 eid; + + eid = ATH12K_SKB_CB(skb)->eid; dev_kfree_skb(skb); -} -static bool ath12k_reg_is_world_alpha(char *alpha) -{ - return alpha[0] == '0' && alpha[1] == '0'; -} + if (eid >= ATH12K_HTC_EP_COUNT) + return; -static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *skb) -{ - struct ath12k_reg_info *reg_info = NULL; - struct ieee80211_regdomain *regd = NULL; - bool intersect = false; - int ret = 0, pdev_idx, i, j; - struct ath12k *ar; + wmi_ep_count = ab->htc.wmi_ep_count; + if (wmi_ep_count > ab->hw_params->max_radios) + return; - reg_info = kzalloc(sizeof(*reg_info), GFP_ATOMIC); - if (!reg_info) { - ret = -ENOMEM; - goto fallback; + for (i = 0; i < ab->htc.wmi_ep_count; i++) { + if (ab->wmi_ab.wmi[i].eid == eid) { + wmi = &ab->wmi_ab.wmi[i]; + break; + } } - ret = ath12k_pull_reg_chan_list_ext_update_ev(ab, skb, reg_info); - - if (ret) { - ath12k_warn(ab, "failed to extract regulatory info from received event\n"); - goto fallback; + if (wmi) + wake_up(&wmi->tx_ce_desc_wq); } +static int ath12k_reg_handle_chan_list(struct ath12k_base *ab, + struct ath12k_reg_info *reg_info, + enum ieee80211_ap_reg_power power_type) +{ + struct ieee80211_regdomain *regd; + int pdev_idx; + struct ath12k *ar; + if (reg_info->status_code != REG_SET_CC_STATUS_PASS) { /* In case of failure to set the requested ctry, * fw retains the current regd. We print a failure info * and return from here. */ ath12k_warn(ab, "Failed to set the requested Country regulatory setting\n"); - goto mem_free; + return -EINVAL; } pdev_idx = reg_info->phy_id; @@ -5172,7 +9036,7 @@ */ if (ab->hw_params->single_pdev_only && pdev_idx < ab->hw_params->num_rxmda_per_pdev) - goto mem_free; + goto retfail; else goto fallback; } @@ -5183,26 +9047,20 @@ if (ab->default_regd[pdev_idx] && !ab->new_regd[pdev_idx] && !memcmp(ab->default_regd[pdev_idx]->alpha2, reg_info->alpha2, 2)) - goto mem_free; + goto retfail; - /* Intersect new rules with default regd if a new country setting was - * requested, i.e a default regd was already set during initialization - * and the regd coming from this event has a valid country info. - */ - if (ab->default_regd[pdev_idx] && - !ath12k_reg_is_world_alpha((char *) - ab->default_regd[pdev_idx]->alpha2) && - !ath12k_reg_is_world_alpha((char *)reg_info->alpha2)) - intersect = true; + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi handle chan list power type %d\n", power_type); - regd = ath12k_reg_build_regd(ab, reg_info, intersect); + regd = ath12k_reg_build_regd(ab, reg_info, power_type); if (!regd) { ath12k_warn(ab, "failed to build regd from reg_info\n"); goto fallback; } spin_lock(&ab->base_lock); - if (test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags)) { + if (ab->default_regd[pdev_idx] && + ab->regd_change_user_request[pdev_idx]) { /* Once mac is registered, ar is valid and all CC events from * fw is considered to be received due to user requests * currently. @@ -5213,7 +9071,8 @@ ar = ab->pdevs[pdev_idx].ar; kfree(ab->new_regd[pdev_idx]); ab->new_regd[pdev_idx] = regd; - ieee80211_queue_work(ar->hw, &ar->regd_update_work); + queue_work(ab->workqueue, &ar->regd_update_work); + } else { /* Multiple events for the same *ar is not expected. But we * can still clear any previously stored default_regd if we @@ -5227,7 +9086,7 @@ ab->dfs_region = reg_info->dfs_region; spin_unlock(&ab->base_lock); - goto mem_free; + return 0; fallback: /* Fallback to older reg (by sending previous country setting @@ -5239,17 +9098,42 @@ */ /* TODO: This is rare, but still should also be handled */ WARN_ON(1); +retfail: + return -EINVAL; +} + + +static int ath12k_reg_chan_list_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + struct ath12k_reg_info *reg_info; + int ret, i, j; + + reg_info = kzalloc(sizeof(*reg_info), GFP_ATOMIC); + if (!reg_info) + return -ENOMEM; + + ret = ath12k_pull_reg_chan_list_ext_update_ev(ab, skb, reg_info); + + if (ret) { + ath12k_warn(ab, "failed to extract regulatory info from received event\n"); + goto mem_free; + } + + ret = ath12k_reg_handle_chan_list(ab, reg_info, IEEE80211_REG_UNSET_AP); + if (ret) { + ath12k_warn(ab, "failed to process regulatory info from received event\n"); + goto mem_free; + } mem_free: if (reg_info) { kfree(reg_info->reg_rules_2g_ptr); kfree(reg_info->reg_rules_5g_ptr); if (reg_info->is_ext_reg_event) { - for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) + for (i = 0; i < WMI_REG_CURRENT_MAX_AP_TYPE; i++) { kfree(reg_info->reg_rules_6g_ap_ptr[i]); - - for (j = 0; j < WMI_REG_CURRENT_MAX_AP_TYPE; j++) - for (i = 0; i < WMI_REG_MAX_CLIENT_TYPE; i++) - kfree(reg_info->reg_rules_6g_client_ptr[j][i]); + for (j = 0; j < WMI_REG_MAX_CLIENT_TYPE; j++) + kfree(reg_info->reg_rules_6g_client_ptr[i][j]); + } } kfree(reg_info); } @@ -5277,7 +9161,7 @@ ether_addr_copy(ab->mac_addr, fixed_param.ready_event_min.mac_addr.addr); - ab->pktlog_defs_checksum = le32_to_cpu(fixed_param.pktlog_defs_checksum); + ab->pktlog_defs_checksum = fixed_param.pktlog_defs_checksum; ab->wmi_ready = true; break; case WMI_TAG_ARRAY_FIXED_STRUCT: @@ -5290,6 +9174,16 @@ for (i = 0; i < ab->num_radios; i++) { pdev = &ab->pdevs[i]; ether_addr_copy(pdev->mac_addr, addr_list[i].addr); + if (!memcmp(pdev->mac_addr, "\x00\x03\x7f", 3)) { + /* randomly assigned mac address + * chosen by firmware, but the problem + * is that it will chose the same one + * for all PCIe cards and we will get + * duplicate addresses, at least make + * sure to mark them locally assigned + * so userspace will override them */ + pdev->mac_addr[0] |= (1 << 1); + } } ab->pdevs_macaddr_valid = true; break; @@ -5327,7 +9221,7 @@ } rcu_read_lock(); - ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(peer_del_resp.vdev_id)); + ar = ath12k_mac_get_ar_by_vdev_id(ab, peer_del_resp.vdev_id); if (!ar) { ath12k_warn(ab, "invalid vdev id in peer delete resp ev %d", peer_del_resp.vdev_id); @@ -5337,7 +9231,7 @@ complete(&ar->peer_delete_done); rcu_read_unlock(); - ath12k_dbg(ab, ATH12K_DBG_WMI, "peer delete resp for vdev id %d addr %pM\n", + ath12k_dbg(ab, ATH12K_DBG_PEER, "peer delete resp for vdev id %d addr %pM\n", peer_del_resp.vdev_id, peer_del_resp.peer_macaddr.addr); } @@ -5380,6 +9274,14 @@ return "dfs violation"; case WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN: return "invalid regdomain"; + case WMI_VDEV_START_RESPONSE_INVALID_BAND: + return "invalid band"; + case WMI_VDEV_START_RESPONSE_INVALID_PREFERRED_TX_RX_STREAMS: + /** Invalid preferred tx/rx streams */ + return "invalid TX/RX streams"; + case WMI_VDEV_START_RESPONSE_INVALID_TX_VAP_CONFIG: + /** Invalid tx_vap config in VDEV start */ + return "invalid tx vap config"; default: return "unknown"; } @@ -5397,7 +9299,7 @@ } rcu_read_lock(); - ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(vdev_start_resp.vdev_id)); + ar = ath12k_mac_get_ar_by_vdev_id(ab, vdev_start_resp.vdev_id); if (!ar) { ath12k_warn(ab, "invalid vdev id in vdev start resp ev %d", vdev_start_resp.vdev_id); @@ -5406,8 +9308,9 @@ } ar->last_wmi_vdev_start_status = 0; + ar->max_allowed_tx_power = vdev_start_resp.max_allowed_tx_power; - status = le32_to_cpu(vdev_start_resp.status); + status = vdev_start_resp.status; if (WARN_ON_ONCE(status)) { ath12k_warn(ab, "vdev start resp error status %d (%s)\n", @@ -5425,6 +9328,7 @@ static void ath12k_bcn_tx_status_event(struct ath12k_base *ab, struct sk_buff *skb) { + struct ath12k_link_vif *arvif; u32 vdev_id, tx_status; if (ath12k_pull_bcn_tx_status_ev(ab, skb->data, skb->len, @@ -5432,6 +9336,16 @@ ath12k_warn(ab, "failed to extract bcn tx status"); return; } + + rcu_read_lock(); + arvif = ath12k_mac_get_arvif_by_vdev_id(ab, vdev_id); + if (!arvif) { + ath12k_warn(ab, "invalid vdev id %d in bcn_tx_status", + vdev_id); + rcu_read_unlock(); + return; + } + rcu_read_unlock(); } static void ath12k_vdev_stopped_event(struct ath12k_base *ab, struct sk_buff *skb) @@ -5460,52 +9374,2394 @@ ath12k_dbg(ab, ATH12K_DBG_WMI, "vdev stopped for vdev id %d", vdev_id); } +/** + * ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte() - Compare given mgmt packet counters + * @ctr1: Management packet counter1 + * @ctr2: Management packet counter2 + * + * We can't directly use the comparison operator here because the counters can + * overflow. But these counters have a property that the difference between + * them can never be greater than half the range of the data type. + * We can make use of this condition to detect which one is actually greater. + * + * Return: true if @ctr1 is greater than or equal to @ctr2, else false + */ +static inline bool +ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte(u16 ctr1, u16 ctr2) +{ + u16 delta = ctr1 - ctr2; + + return delta <= ATH12K_MGMT_RX_REO_PKT_CTR_HALF_RANGE; +} + +/** + * ath12k_mgmt_rx_reo_subtract_pkt_ctrs() - Subtract given mgmt packet counters + * @ctr1: Management packet counter1 + * @ctr2: Management packet counter2 + * + * We can't directly use the subtract operator here because the counters can + * overflow. But these counters have a property that the difference between + * them can never be greater than half the range of the data type. + * We can make use of this condition to detect whichone is actually greater and + * return the difference accordingly. + * + * Return: Difference between @ctr1 and @crt2 + */ +static inline int +ath12k_mgmt_rx_reo_subtract_pkt_ctrs(u16 ctr1, u16 ctr2) +{ + u16 delta = ctr1 - ctr2; + + /** + * if delta is greater than half the range (i.e, ctr1 is actually + * smaller than ctr2), then the result should be a negative number. + * subtracting the entire range should give the correct value. + */ + if (delta > ATH12K_MGMT_RX_REO_PKT_CTR_HALF_RANGE) + return delta - ATH12K_MGMT_RX_REO_PKT_CTR_FULL_RANGE; + + return delta; +} + +#define ATH12K_MGMT_RX_REO_GLOBAL_TS_HALF_RANGE (0x80000000) +/** + * ath12k_mgmt_rx_reo_compare_global_timestamps_gte()-Compare given global timestamps + * @ts1: Global timestamp1 + * @ts2: Global timestamp2 + * + * We can't directly use the comparison operator here because the timestamps can + * overflow. But these timestamps have a property that the difference between + * them can never be greater than half the range of the data type. + * We can make use of this condition to detect which one is actually greater. + * + * Return: true if @ts1 is greater than or equal to @ts2, else false + */ +static inline bool +ath12k_mgmt_rx_reo_compare_global_timestamps_gte(u32 ts1, u32 ts2) +{ + u32 delta = ts1 - ts2; + + return delta <= ATH12K_MGMT_RX_REO_GLOBAL_TS_HALF_RANGE; +} + +#define ATH12K_RX_REO_REORD_MAX_DELTA 0xFFFF +/** + * ath12k_wlan_mgmt_rx_reo_update_host_snapshot() - Update Host snapshot with the MGMT + * Rx REO parameters. + * @desc: pointer to frame descriptor + * + * Return: 0 on Success, Error value on failure of operation + */ +static int +ath12k_wlan_mgmt_rx_reo_update_host_snapshot(struct ath12k *ar, + struct ath12k_mgmt_rx_reo_frame_descriptor *desc) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_mgmt_rx_reo_pdev_info *rx_reo_pdev_ctx; + struct ath12k_mgmt_rx_reo_snapshot_params *host_ss; + struct ath12k_mgmt_rx_reo_params *reo_params; + int pkt_ctr_delta; + + if (!desc) { + ath12k_err(ab, "Mgmt Rx REO frame descriptor null\n"); + return -EINVAL; + } + + if (!desc->rx_params) { + ath12k_err(ab, "Mgmt Rx params NULL\n"); + return -EINVAL; + } + + reo_params = &desc->rx_params->reo_params; + + rx_reo_pdev_ctx = &ar->rx_reo_pdev_ctx; + if (!rx_reo_pdev_ctx) { + ath12k_err(ab, "Mgmt Rx REO context empty for pdev\n"); + return -EINVAL; + } + + /* FW should send valid REO parameters */ + if (!reo_params->valid) { + ath12k_err(ab, "Mgmt Rx REO params is invalid\n"); + return -EINVAL; + } + + host_ss = &rx_reo_pdev_ctx->host_snapshot; + + if (!host_ss->valid) { + desc->pkt_ctr_delta = 1; + goto update_host_ss; + } + + if (ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte(host_ss->mgmt_pkt_ctr, + reo_params->mgmt_pkt_ctr)) { + ath12k_err(ab, "Cur frame ctr < last frame ctr for link = %u", + reo_params->link_id); + goto failure_debug; + } + + pkt_ctr_delta = ath12k_mgmt_rx_reo_subtract_pkt_ctrs(reo_params->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr); + BUG_ON(!(pkt_ctr_delta > 0)); + desc->pkt_ctr_delta = pkt_ctr_delta; + + if (pkt_ctr_delta == 1) + goto update_host_ss; + + /* Under back pressure scenarios, FW may drop management Rx frame + * WMI events. So holes in the management packet counter is expected. + * Add a debug print and optional assert to track the holes. + */ + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "---- Rx reo reordering(this info is seen since pkt_ctr_delta > 0) ----\n"); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "pkt_ctr_delta = %u\n", pkt_ctr_delta); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Cur frame valid = %u, pkt_ctr = %u, ts =%u\n", + reo_params->valid, reo_params->mgmt_pkt_ctr, + reo_params->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Last frame valid = %u, pkt_ctr = %u, ts =%u\n", + host_ss->valid, host_ss->mgmt_pkt_ctr, + host_ss->global_timestamp); + + if (pkt_ctr_delta > ATH12K_RX_REO_REORD_MAX_DELTA) { + ath12k_err(ab, "pkt ctr delta %u > thresh %u for link %u", + pkt_ctr_delta, ATH12K_RX_REO_REORD_MAX_DELTA, + reo_params->link_id); + goto failure_debug; + } + +update_host_ss: + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Last frame valid = %u, pkt_ctr = %u, ts =%u\n", + host_ss->valid, host_ss->mgmt_pkt_ctr, + host_ss->global_timestamp); + + host_ss->valid = true; + host_ss->global_timestamp = reo_params->global_timestamp; + host_ss->mgmt_pkt_ctr = reo_params->mgmt_pkt_ctr; + + return 0; + +failure_debug: + ath12k_err(ab, "Cur frame valid = %u, pkt_ctr = %u, ts =%u\n", + reo_params->valid, reo_params->mgmt_pkt_ctr, + reo_params->global_timestamp); + ath12k_err(ab, "Last frame valid = %u, pkt_ctr = %u, ts =%u\n", + host_ss->valid, host_ss->mgmt_pkt_ctr, + host_ss->global_timestamp); + BUG_ON(1); + + return -EINVAL; +} + +/** + * ath12k_wmi_mgmt_rx_reo_read_snapshot_raw() - Read raw value of management + * rx-reorder snapshot + * @snapshot_address: snapshot address + * @ath12k_mgmt_rx_reo_snapshot_low: Pointer to lower 32 bits of snapshot value + * @ath12k_mgmt_rx_reo_snapshot_high: Pointer to higher 32 bits of snapshot value + * @snapshot_version: snapshot version + * + * Read raw value of management rx-reorder snapshots. + * + * Return: 0 on Success, Error value on failure + */ +static int +ath12k_wmi_mgmt_rx_reo_read_snapshot_raw + (struct ath12k_mgmt_rx_reo_shared_snapshot *snapshot_address, + u32 *ath12k_mgmt_rx_reo_snapshot_low, + u32 *ath12k_mgmt_rx_reo_snapshot_high, + u8 snapshot_version, + struct ath12k_mgmt_rx_reo_shared_snapshot *raw_snapshot) +{ + u32 prev_snapshot_low; + u32 prev_snapshot_high; + u32 cur_snapshot_low; + u32 cur_snapshot_high; + u8 retry_count = 0; + + if (snapshot_version == 1) { + *ath12k_mgmt_rx_reo_snapshot_low = + snapshot_address->u_low.ath12k_mgmt_rx_reo_snapshot_low; + *ath12k_mgmt_rx_reo_snapshot_high = + snapshot_address->u_high.ath12k_mgmt_rx_reo_snapshot_high; + raw_snapshot->u_low.ath12k_mgmt_rx_reo_snapshot_low = + *ath12k_mgmt_rx_reo_snapshot_low; + raw_snapshot->u_high.ath12k_mgmt_rx_reo_snapshot_high = + *ath12k_mgmt_rx_reo_snapshot_high; + return 0; + } + + prev_snapshot_low = snapshot_address->u_low.ath12k_mgmt_rx_reo_snapshot_low; + prev_snapshot_high = snapshot_address->u_high.ath12k_mgmt_rx_reo_snapshot_high; + raw_snapshot->u_low.ath12k_mgmt_rx_reo_snapshot_low = prev_snapshot_low; + raw_snapshot->u_high.ath12k_mgmt_rx_reo_snapshot_high = prev_snapshot_high; + + for (; retry_count < (ATH12K_MGMT_RX_REO_SNAPSHOT_B2B_READ_SWAR_RETRY_LIMIT - 1); + retry_count++) { + cur_snapshot_low = snapshot_address->u_low.ath12k_mgmt_rx_reo_snapshot_low; + cur_snapshot_high = snapshot_address->u_high.ath12k_mgmt_rx_reo_snapshot_high; + + raw_snapshot[retry_count + 1].u_low.ath12k_mgmt_rx_reo_snapshot_low = + cur_snapshot_low; + raw_snapshot[retry_count + 1].u_high.ath12k_mgmt_rx_reo_snapshot_high = + cur_snapshot_high; + + if (prev_snapshot_low == cur_snapshot_low && + prev_snapshot_high == cur_snapshot_high) + break; + + prev_snapshot_low = cur_snapshot_low; + prev_snapshot_high = cur_snapshot_high; + } + + BUG_ON(retry_count == + (ATH12K_MGMT_RX_REO_SNAPSHOT_B2B_READ_SWAR_RETRY_LIMIT - 1)); + + *ath12k_mgmt_rx_reo_snapshot_low = cur_snapshot_low; + *ath12k_mgmt_rx_reo_snapshot_high = cur_snapshot_high; + + return 0; +} + +/** + * Helper macros/functions for params GET/SET of different hw version + * of the mgmt_rx_reo_snapshot + */ + +static inline u8 +ath12k_mlo_shmem_mgmt_rx_reo_snapshot_valid_get(struct ath12k_base *ab, + u32 ath12k_mgmt_rx_reo_snapshot_low, + u8 snapshot_ver) +{ + if ((snapshot_ver != ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) && + (snapshot_ver != ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY)) { + ath12k_err(ab, "Check this error snapshot ver %d\n", snapshot_ver); + BUG_ON(1); + } + + return ATH12K_MLO_SHMEM_GET_BITS(ath12k_mgmt_rx_reo_snapshot_low, 31, 1); +} + +static inline u32 +ath12k_mlo_shmem_mgmt_rx_reo_snapshot_global_timestamp_get( + struct ath12k_base *ab, + u32 ath12k_mgmt_rx_reo_snapshot_low, + u32 ath12k_mgmt_rx_reo_snapshot_high, + u8 snapshot_ver) +{ + if (snapshot_ver == ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { + return ath12k_mgmt_rx_reo_snapshot_high; + } else if (snapshot_ver == ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY) { + return + ((ATH12K_MLO_SHMEM_GET_BITS(ath12k_mgmt_rx_reo_snapshot_high, 15, 17) << 15) | + ATH12K_MLO_SHMEM_GET_BITS(ath12k_mgmt_rx_reo_snapshot_low, 0, 15)); + } else { + ath12k_err(ab, "Check this error snapshot ver %d\n", snapshot_ver); + BUG_ON(1); + return 0; + } +} + +static inline u16 +mlo_shmem_mgmt_rx_reo_snapshot_mgmt_pkt_ctr_get( + struct ath12k_base *ab, + u32 ath12k_mgmt_rx_reo_snapshot_low, u8 snapshot_ver) +{ + if (snapshot_ver == ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { + return ATH12K_MLO_SHMEM_GET_BITS(ath12k_mgmt_rx_reo_snapshot_low, 0, 16); + } else if (snapshot_ver == ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY) { + return ATH12K_MLO_SHMEM_GET_BITS(ath12k_mgmt_rx_reo_snapshot_low, 15, 16); + } else { + ath12k_err(ab, "Check this error snapshot ver %d\n", snapshot_ver); + BUG_ON(1); + return 0; + } +} + +#define ATH12K_MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_GET( \ + ath12k_mgmt_rx_reo_snapshot_high) \ + ATH12K_MLO_SHMEM_GET_BITS(ath12k_mgmt_rx_reo_snapshot_high, 0, 15) + +#define ATH12K_MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_GET( \ + ath12k_mgmt_rx_reo_snapshot_low) \ + ATH12K_MLO_SHMEM_GET_BITS(ath12k_mgmt_rx_reo_snapshot_low, 16, 15) + +static inline bool +ath12k_mlo_shmem_mgmt_rx_reo_snapshot_check_consistency( + struct ath12k_base *ab, + u32 ath12k_mgmt_rx_reo_snapshot_low, + u32 ath12k_mgmt_rx_reo_snapshot_high, + u8 snapshot_ver) +{ + if (snapshot_ver == ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { + u32 global_timestamp; + u32 global_timestamp_redundant; + + global_timestamp = + ath12k_mlo_shmem_mgmt_rx_reo_snapshot_global_timestamp_get(ab, + ath12k_mgmt_rx_reo_snapshot_low, + ath12k_mgmt_rx_reo_snapshot_high, + snapshot_ver); + global_timestamp_redundant = + ATH12K_MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_GET( + ath12k_mgmt_rx_reo_snapshot_low); + + return + (ATH12K_MLO_SHMEM_GET_BITS(global_timestamp, 0, 15) == + ATH12K_MLO_SHMEM_GET_BITS(global_timestamp_redundant, 0, 15)); + } else if (snapshot_ver == ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY) { + u16 mgmt_pkt_ctr; + u16 mgmt_pkt_ctr_redundant; + + mgmt_pkt_ctr = mlo_shmem_mgmt_rx_reo_snapshot_mgmt_pkt_ctr_get(ab, + ath12k_mgmt_rx_reo_snapshot_low, snapshot_ver); + mgmt_pkt_ctr_redundant = + ATH12K_MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_GET( + ath12k_mgmt_rx_reo_snapshot_high); + + return + (ATH12K_MLO_SHMEM_GET_BITS(mgmt_pkt_ctr, 0, 15) == + ATH12K_MLO_SHMEM_GET_BITS(mgmt_pkt_ctr_redundant, 0, 15)); + } else { + ath12k_err(ab, "Check this error snapshot ver %d\n", snapshot_ver); + BUG_ON(1); + return 0; + } +} + +/** + * ath12k_mgmt_rx_reo_snapshot_get_mgmt_pkt_ctr() - Get the management packet counter + * from an MGMT Rx REO snapshot + * @snapshot_low: lower 32-bits of the snapshot + * @snapshot_version: snapshot version + * + * Return: Management packet counter of the snapshot + */ +static u16 ath12k_mgmt_rx_reo_snapshot_get_mgmt_pkt_ctr( + struct ath12k_base *ab, + u32 mgmt_rx_reo_snapshot_low, + u8 snapshot_version) +{ + if (snapshot_version == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { + return ATH12K_MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 16); + } else if (snapshot_version == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY) { + return ATH12K_MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 15, 16); + } else { + ath12k_err(ab, "Check this error snapshot ver %d\n", snapshot_version); + BUG_ON(1); + return 0; + } +} + +/** + * ath12k_wmi_mgmt_rx_reo_read_snapshot() - Read management rx-reorder snapshot + * @pdev: pdev pointer + * @snapshot_info: Snapshot info + * @id: Snapshot ID + * @snapshot_value: Pointer to snapshot value + * + * Read management rx-reorder snapshots from target. + * + * Return: 0 on Success, Error value on failure + */ +static int +ath12k_wmi_mgmt_rx_reo_read_snapshot( + struct ath12k *ar, + struct ath12k_mgmt_rx_reo_snapshot_info *snapshot_info, + enum ath12k_mgmt_rx_reo_shared_snapshot_id id, + struct ath12k_mgmt_rx_reo_snapshot_params *snapshot_value, + struct ath12k_mgmt_rx_reo_shared_snapshot (*raw_snapshot) + [ATH12K_MGMT_RX_REO_SNAPSHOT_B2B_READ_SWAR_RETRY_LIMIT]) +{ + struct ath12k_base *ab = ar->ab; + bool snapshot_valid; + u16 mgmt_pkt_ctr; + u32 global_timestamp; + u32 ath12k_mgmt_rx_reo_snapshot_low; + u32 ath12k_mgmt_rx_reo_snapshot_high; + u8 retry_count; + int status; + struct ath12k_mgmt_rx_reo_shared_snapshot *snapshot_address; + u8 snapshot_version; + + if (!snapshot_info) { + ath12k_err(ab, "Mgmt Rx REO snapshot info null\n"); + return -EINVAL; + } + + snapshot_address = snapshot_info->address; + if (!snapshot_address) { + ath12k_err(ab, "Mgmt Rx REO snapshot address null\n"); + return -EINVAL; + } + + snapshot_version = snapshot_info->version; + + if (!snapshot_value) { + ath12k_err(ab, "Mgmt Rx REO snapshot null\n"); + return -EINVAL; + } + + memset(snapshot_value, 0, sizeof(*snapshot_value)); + + switch (id) { + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAC_HW: + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_CONSUMED: + case ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_FORWARDED: + retry_count = 0; + for (; retry_count < ATH12K_MGMT_RX_REO_SNAPSHOT_READ_RETRY_LIMIT; + retry_count++) { + status = ath12k_wmi_mgmt_rx_reo_read_snapshot_raw + (snapshot_address, + &ath12k_mgmt_rx_reo_snapshot_low, + &ath12k_mgmt_rx_reo_snapshot_high, + snapshot_version, + raw_snapshot[retry_count]); + + if (status) { + ath12k_err(ab, "Failed to read snapshot %d status %d\n", + id, status); + return -EINVAL; + } + + snapshot_valid = ath12k_mlo_shmem_mgmt_rx_reo_snapshot_valid_get(ab, + ath12k_mgmt_rx_reo_snapshot_low, + snapshot_version); + + if (!snapshot_valid) { + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Invalid REO snapshot value"); + snapshot_value->valid = false; + snapshot_value->mgmt_pkt_ctr = + ath12k_mgmt_rx_reo_snapshot_get_mgmt_pkt_ctr + (ab, ath12k_mgmt_rx_reo_snapshot_low, + snapshot_version); + snapshot_value->global_timestamp = + ath12k_mlo_shmem_mgmt_rx_reo_snapshot_global_timestamp_get + (ab, ath12k_mgmt_rx_reo_snapshot_low, + ath12k_mgmt_rx_reo_snapshot_high, + snapshot_version); + snapshot_value->retry_count = retry_count + 1; + return 0; + } + + if (ath12k_mlo_shmem_mgmt_rx_reo_snapshot_check_consistency + (ar->ab, ath12k_mgmt_rx_reo_snapshot_low, + ath12k_mgmt_rx_reo_snapshot_high, + snapshot_version)) { + global_timestamp = + ath12k_mlo_shmem_mgmt_rx_reo_snapshot_global_timestamp_get + (ab, ath12k_mgmt_rx_reo_snapshot_low, + ath12k_mgmt_rx_reo_snapshot_high, + snapshot_version); + mgmt_pkt_ctr = + mlo_shmem_mgmt_rx_reo_snapshot_mgmt_pkt_ctr_get + (ab, ath12k_mgmt_rx_reo_snapshot_low, + snapshot_version); + break; + } + ath12k_info(ab, "Inconsistent snapshot %d, version=%u, low=0x%x, high=0x%x, retry=%u\n", + id, snapshot_version, + ath12k_mgmt_rx_reo_snapshot_low, + ath12k_mgmt_rx_reo_snapshot_high, + retry_count); + } + + if (retry_count == ATH12K_MGMT_RX_REO_SNAPSHOT_READ_RETRY_LIMIT) { + ath12k_err(ab, "Read retry limit, id = %d, ver = %u\n", + id, snapshot_version); + BUG_ON(1); + return -EINVAL; + } + + snapshot_value->valid = true; + snapshot_value->mgmt_pkt_ctr = mgmt_pkt_ctr; + snapshot_value->global_timestamp = global_timestamp; + snapshot_value->retry_count = retry_count + 1; + status = 0; + break; + + default: + ath12k_err(ab, "Invalid snapshot id %d\n", id); + status = -EINVAL; + break; + } + + return status; +} + +/** + * ath12k_mgmt_rx_reo_print_snapshots() - Print all snapshots related + * to management Rx reorder module + * @mac_hw_ss: MAC HW snapshot + * @fw_forwarded_ss: FW forwarded snapshot + * @fw_consumed_ss: FW consumed snapshot + * @host_ss: Host snapshot + * + * return: int + */ +static int +ath12k_mgmt_rx_reo_print_snapshots + (struct ath12k_base *ab, + struct ath12k_mgmt_rx_reo_snapshot_params *mac_hw_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *fw_forwarded_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *fw_consumed_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *host_ss) +{ + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "HW SS: valid = %u, ctr = %u, ts = %u\n", + mac_hw_ss->valid, mac_hw_ss->mgmt_pkt_ctr, + mac_hw_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "FW forwarded SS: valid = %u, ctr = %u, ts = %u\n", + fw_forwarded_ss->valid, + fw_forwarded_ss->mgmt_pkt_ctr, + fw_forwarded_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "FW consumed SS: valid = %u, ctr = %u, ts = %u\n", + fw_consumed_ss->valid, + fw_consumed_ss->mgmt_pkt_ctr, + fw_consumed_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "HOST SS: valid = %u, ctr = %u, ts = %u\n", + host_ss->valid, host_ss->mgmt_pkt_ctr, + host_ss->global_timestamp); + + return 0; +} + +/** + * ath12k_wmi_mgmt_rx_reo_invalidate_stale_snapshots() - Invalidate stale management + * Rx REO snapshots + * @mac_hw_ss: MAC HW snapshot + * @fw_forwarded_ss: FW forwarded snapshot + * @fw_consumed_ss: FW consumed snapshot + * @host_ss: Host snapshot + * @link: link ID + * + * return: int + */ +static int +ath12k_wmi_mgmt_rx_reo_invalidate_stale_snapshots + (struct ath12k *ar, + struct ath12k_mgmt_rx_reo_snapshot_params *mac_hw_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *fw_forwarded_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *fw_consumed_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *host_ss, + u8 link) +{ + struct ath12k_base *ab = ar->ab; + + if (!mac_hw_ss->valid) + return 0; + + if (host_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (mac_hw_ss->global_timestamp, + host_ss->global_timestamp) || + !ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (mac_hw_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr)) { + ath12k_mgmt_rx_reo_print_snapshots(ab, mac_hw_ss, fw_forwarded_ss, + fw_consumed_ss, host_ss); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Invalidate host snapshot, link %u", + link); + host_ss->valid = false; + } + } + + if (fw_forwarded_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (mac_hw_ss->global_timestamp, + fw_forwarded_ss->global_timestamp) || + !ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (mac_hw_ss->mgmt_pkt_ctr, + fw_forwarded_ss->mgmt_pkt_ctr)) { + ath12k_mgmt_rx_reo_print_snapshots(ab, mac_hw_ss, fw_forwarded_ss, + fw_consumed_ss, host_ss); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Invalidate FW forwarded SS, link %u\n", + link); + fw_forwarded_ss->valid = false; + } + } + + if (host_ss->valid && fw_forwarded_ss->valid && + (ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (host_ss->global_timestamp, + fw_forwarded_ss->global_timestamp) != + ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (host_ss->mgmt_pkt_ctr, + fw_forwarded_ss->mgmt_pkt_ctr))) { + ath12k_mgmt_rx_reo_print_snapshots(ab, mac_hw_ss, fw_forwarded_ss, + fw_consumed_ss, host_ss); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Invalidate FW forwarded SS, link %u", + link); + fw_forwarded_ss->valid = false; + } + + if (fw_consumed_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (mac_hw_ss->global_timestamp, + fw_consumed_ss->global_timestamp) || + !ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (mac_hw_ss->mgmt_pkt_ctr, + fw_consumed_ss->mgmt_pkt_ctr)) { + ath12k_mgmt_rx_reo_print_snapshots(ab, mac_hw_ss, fw_forwarded_ss, + fw_consumed_ss, host_ss); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Invalidate FW consumed SS, link %u\n", + link); + fw_consumed_ss->valid = false; + } + if (host_ss->valid && fw_consumed_ss->valid && + (ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (host_ss->global_timestamp, + fw_consumed_ss->global_timestamp) != + ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (host_ss->mgmt_pkt_ctr, + fw_consumed_ss->mgmt_pkt_ctr))) { + ath12k_mgmt_rx_reo_print_snapshots(ab, mac_hw_ss, fw_forwarded_ss, + fw_consumed_ss, host_ss); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "Invalidate FW consumed SS, link %u", + link); + fw_consumed_ss->valid = false; + } + } + + return 0; +} + +/** + * mgmt_rx_reo_snapshots_check_sanity() - Check the sanity of management + * Rx REO snapshots + * @mac_hw_ss: MAC HW snapshot + * @fw_forwarded_ss: FW forwarded snapshot + * @fw_consumed_ss: FW consumed snapshot + * @host_ss: Host snapshot + * + * return: int + */ +static int +mgmt_rx_reo_snapshots_check_sanity + (struct ath12k *ar, + struct ath12k_mgmt_rx_reo_snapshot_params *mac_hw_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *fw_forwarded_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *fw_consumed_ss, + struct ath12k_mgmt_rx_reo_snapshot_params *host_ss) +{ + int status; + struct ath12k_base *ab = ar->ab; + + if (!mac_hw_ss->valid) { + if (fw_forwarded_ss->valid || fw_consumed_ss->valid || + host_ss->valid) { + ath12k_err(ab, "MAC HW SS is invalid\n"); + status = -EINVAL; + goto fail; + } + + return 0; + } + + if (!fw_forwarded_ss->valid && !fw_consumed_ss->valid) { + if (host_ss->valid) { + ath12k_err(ab, "FW forwarded and consumed SS invalid\n"); + status = -EINVAL; + goto fail; + } + + return 0; + } + + if (fw_forwarded_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (mac_hw_ss->global_timestamp, + fw_forwarded_ss->global_timestamp)) { + ath12k_err(ab, "TS: MAC HW SS < FW forwarded SS\n"); + status = -EINVAL; + goto fail; + } + + if (!ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (mac_hw_ss->mgmt_pkt_ctr, + fw_forwarded_ss->mgmt_pkt_ctr)) { + ath12k_err(ab, "PKT CTR: MAC HW SS < FW forwarded SS\n"); + status = -EINVAL; + goto fail; + } + } + + if (fw_consumed_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (mac_hw_ss->global_timestamp, + fw_consumed_ss->global_timestamp)) { + ath12k_err(ab, "TS: MAC HW SS < FW consumed SS\n"); + status = -EINVAL; + goto fail; + } + + if (!ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (mac_hw_ss->mgmt_pkt_ctr, + fw_consumed_ss->mgmt_pkt_ctr)) { + ath12k_err(ab, "PKT CTR: MAC HW SS < FW consumed SS\n"); + status = -EINVAL; + goto fail; + } + } + + if (host_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (mac_hw_ss->global_timestamp, + host_ss->global_timestamp)) { + ath12k_err(ab, "TS: MAC HW SS < host SS\n"); + status = -EINVAL; + goto fail; + } + + if (!ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (mac_hw_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr)) { + ath12k_err(ab, "PKT CTR: MAC HW SS < host SS\n"); + status = -EINVAL; + goto fail; + } + + if (fw_forwarded_ss->valid && !fw_consumed_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (fw_forwarded_ss->global_timestamp, + host_ss->global_timestamp)) { + ath12k_err(ab, "TS: FW forwarded < host SS\n"); + status = -EINVAL; + goto fail; + } + + if (!ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (fw_forwarded_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr)) { + ath12k_err(ab, "CTR: FW forwarded < host SS\n"); + status = -EINVAL; + goto fail; + } + } + + if (fw_consumed_ss->valid && !fw_forwarded_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (fw_consumed_ss->global_timestamp, + host_ss->global_timestamp)) { + ath12k_err(ab, "TS: FW consumed < host SS\n"); + status = -EINVAL; + goto fail; + } + + if (!ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (fw_consumed_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr)) { + ath12k_err(ab, "CTR: FW consumed < host SS\n"); + status = -EINVAL; + goto fail; + } + } + + if (fw_forwarded_ss->valid && fw_consumed_ss->valid) { + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (fw_consumed_ss->global_timestamp, + host_ss->global_timestamp) && + !ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (fw_forwarded_ss->global_timestamp, + host_ss->global_timestamp)) { + ath12k_err(ab, "TS: FW consumed/forwarded < host\n"); + status = -EINVAL; + goto fail; + } + + if (!ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (fw_consumed_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr) && + !ath12k_mgmt_rx_reo_compare_pkt_ctrs_gte + (fw_forwarded_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr)) { + ath12k_err(ab, "CTR: FW consumed/forwarded < host\n"); + status = -EINVAL; + goto fail; + } + } + } + + return 0; + +fail: + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "HW SS: valid = %u, ctr = %u, ts = %u", + mac_hw_ss->valid, mac_hw_ss->mgmt_pkt_ctr, + mac_hw_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "FW forwarded SS: valid = %u, ctr = %u, ts = %u", + fw_forwarded_ss->valid, + fw_forwarded_ss->mgmt_pkt_ctr, + fw_forwarded_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "FW consumed SS: valid = %u, ctr = %u, ts = %u", + fw_consumed_ss->valid, + fw_consumed_ss->mgmt_pkt_ctr, + fw_consumed_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "HOST SS: valid = %u, ctr = %u, ts = %u", + host_ss->valid, host_ss->mgmt_pkt_ctr, + host_ss->global_timestamp); + + return status; +} + +/** + * ath12k_wmi_mgmt_rx_reorder_process_calculate_wait_count() - Calculates the number of + * frames an incoming frame should wait for before it gets delivered. + * @in_frame_pdev: pdev on which this frame is received + * @desc: frame Descriptor + * + * Each frame carrys a MGMT pkt number which is local to that link, and a + * timestamp which is global across all the links. MAC HW and FW also captures + * the same details of the last frame that they have seen. Host also maintains + * the details of the last frame it has seen. In total, there are 4 snapshots. + * 1. MAC HW snapshot - latest frame seen at MAC HW + * 2. FW forwarded snapshot- latest frame forwarded to the Host + * 3. FW consumed snapshot - latest frame consumed by the FW + * 4. Host/FW consumed snapshot - latest frame seen by the Host + * By using all these snapshots, this function tries to compute the wait count + * for a given incoming frame on all links. + * + * Return: 1 on success otherwise -1 on failure + */ +static int +ath12k_wmi_mgmt_rx_reorder_process_calculate_wait_count( + struct ath12k *ar, + struct ath12k_mgmt_rx_reo_frame_descriptor *desc) +{ + int status; + u8 hw_link_id; + s8 in_frame_link; + int frames_pending, delta_fwd_host; + u8 snapshot_id; + struct ath12k_base *ab = ar->ab; + struct ath12k *hw_link; + struct ath12k_mgmt_rx_reo_pdev_info *rx_reo_pdev_ctx; + struct ath12k_mgmt_rx_reo_pdev_info *in_frame_rx_reo_pdev_ctx; + struct ath12k_mgmt_rx_reo_snapshot_info *snapshot_info; + struct ath12k_mgmt_rx_reo_snapshot_params snapshot_params + [ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX]; + struct ath12k_mgmt_rx_reo_snapshot_params *mac_hw_ss, *fw_forwarded_ss, + *fw_consumed_ss, *host_ss; + struct ath12k_mgmt_rx_reo_params *in_frame_params; + struct ath12k_mgmt_rx_reo_wait_count *wait_count; + + in_frame_params = &desc->rx_params->reo_params; + + wait_count = &desc->wait_count; + + /* Get the hw link ID of incoming frame */ + in_frame_link = ar->pdev->hw_link_id; + in_frame_rx_reo_pdev_ctx = &ar->rx_reo_pdev_ctx; + + if (!in_frame_rx_reo_pdev_ctx) { + ath12k_err(ab, "Reo context null for incoming frame\n"); + return -EINVAL; + } + memset(in_frame_rx_reo_pdev_ctx->raw_snapshots, 0, + sizeof(in_frame_rx_reo_pdev_ctx->raw_snapshots)); + + /* Iterate over all the valid hw links */ + for (hw_link_id = 0; hw_link_id < ATH12K_WMI_MLO_MAX_LINKS; hw_link_id++) { + /* No need wait for any frames on an invalid hw_link_id */ + if (!ab->ag->hw_links[hw_link_id]) { + frames_pending = 0; + goto update_pending_frames; + } + + hw_link = ab->ag->hw_links[hw_link_id]; + + /* No need to wait for any frames if the pdev is not found */ + if (!hw_link) { + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "pdev is null for hw_link_id %d\n", hw_link_id); + frames_pending = 0; + goto update_pending_frames; + } + + rx_reo_pdev_ctx = &hw_link->rx_reo_pdev_ctx; + if (!rx_reo_pdev_ctx) { + ath12k_err(ab, "Mgmt reo context empty for hw_link %pK\n", + hw_link); + return -EINVAL; + } + + if (!rx_reo_pdev_ctx->init_complete) { + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "REO init in progress for hw_link_id %d", + hw_link_id); + frames_pending = 0; + goto update_pending_frames; + } + + host_ss = &rx_reo_pdev_ctx->host_snapshot; + + desc->host_snapshot[hw_link_id] = rx_reo_pdev_ctx->host_snapshot; + + ath12k_dbg(ab, ATH12K_DBG_RX_REO, + "hw_link_id = %u HOST SS: valid = %u, ctr = %u, ts = %u", + hw_link_id, host_ss->valid, host_ss->mgmt_pkt_ctr, + host_ss->global_timestamp); + + snapshot_id = 0; + /* Read all the shared snapshots */ + while (snapshot_id < + ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX) { + snapshot_info = &rx_reo_pdev_ctx-> + host_target_shared_snapshot_info[snapshot_id]; + + memset(&snapshot_params[snapshot_id], 0, + sizeof(snapshot_params[snapshot_id])); + + status = ath12k_wmi_mgmt_rx_reo_read_snapshot( + hw_link, snapshot_info, snapshot_id, + &snapshot_params[snapshot_id], + in_frame_rx_reo_pdev_ctx->raw_snapshots + [hw_link_id][snapshot_id]); + + /* Read operation shouldn't fail */ + if (status) { + ath12k_err(ab, "snapshot(%d) read failed on hw_link_id (%d) status %d\n", + snapshot_id, hw_link_id, status); + return status; + } + + /* If snapshot is valid, save it in the pdev context */ + if (snapshot_params[snapshot_id].valid) { + rx_reo_pdev_ctx-> + last_valid_shared_snapshot[snapshot_id] = + snapshot_params[snapshot_id]; + } + desc->shared_snapshots[hw_link_id][snapshot_id] = + snapshot_params[snapshot_id]; + + snapshot_id++; + } + + mac_hw_ss = &snapshot_params + [ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAC_HW]; + fw_forwarded_ss = &snapshot_params + [ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_FORWARDED]; + fw_consumed_ss = &snapshot_params + [ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_CONSUMED]; + + status = ath12k_wmi_mgmt_rx_reo_invalidate_stale_snapshots(ar, mac_hw_ss, + fw_forwarded_ss, + fw_consumed_ss, + host_ss, hw_link_id); + if (status) { + ath12k_err(ab, "Failed to invalidate SS for hw_link_id %u\n", + hw_link_id); + return status; + } + + desc->shared_snapshots[hw_link_id][ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAC_HW] = + *mac_hw_ss; + desc->shared_snapshots[hw_link_id][ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_FORWARDED] = + *fw_forwarded_ss; + desc->shared_snapshots[hw_link_id][ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_CONSUMED] = + *fw_consumed_ss; + desc->host_snapshot[hw_link_id] = *host_ss; + + status = mgmt_rx_reo_snapshots_check_sanity + (ar, mac_hw_ss, fw_forwarded_ss, fw_consumed_ss, host_ss); + if (status) { + ath12k_err(ab, "Snapshot sanity for hw_link_id %u failed\n", + hw_link_id); + return status; + } + + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "hw_link_id = %u HW SS: valid = %u, ctr = %u, ts = %u", + hw_link_id, mac_hw_ss->valid, + mac_hw_ss->mgmt_pkt_ctr, + mac_hw_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "hw_link_id = %u FW forwarded SS: valid = %u, ctr = %u, ts = %u", + hw_link_id, fw_forwarded_ss->valid, + fw_forwarded_ss->mgmt_pkt_ctr, + fw_forwarded_ss->global_timestamp); + ath12k_dbg(ab, ATH12K_DBG_RX_REO, "hw_link_id = %u FW consumed SS: valid = %u, ctr = %u, ts = %u", + hw_link_id, fw_consumed_ss->valid, + fw_consumed_ss->mgmt_pkt_ctr, + fw_consumed_ss->global_timestamp); + + /* No need wait for any frames on the same hw_link_id */ + if (hw_link_id == in_frame_link) { + frames_pending = 0; + goto update_pending_frames; + } + + /** + * If MAC HW snapshot is invalid, the hw_link_id has not started + * receiving management frames. Set wait count to zero. + */ + if (!mac_hw_ss->valid) { + frames_pending = 0; + goto update_pending_frames; + } + + /** + * If host snapshot is invalid, wait for MAX number of frames. + * When any frame in this hw_link_id arrives at host, actual wait + * counts will be updated. + */ + if (!host_ss->valid) { + wait_count->per_link_count[hw_link_id] = UINT_MAX; + wait_count->total_count += UINT_MAX; + goto print_wait_count; + } + + /** + * If MAC HW snapshot sequence number and host snapshot + * sequence number are same, all the frames received by + * this hw_link_id are processed by host. No need to wait for + * any frames from this hw_link_id. + */ + if (!ath12k_mgmt_rx_reo_subtract_pkt_ctrs(mac_hw_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr)) { + frames_pending = 0; + goto update_pending_frames; + } + + /** + * Ideally, the incoming frame has to wait for only those frames + * (on other links) which meet all the below criterion. + * 1. Frame's timestamp is less than incoming frame's + * 2. Frame is supposed to be consumed by the Host + * 3. Frame is not yet seen by the Host. + * We may not be able to compute the exact optimal wait count + * because HW/FW provides a limited assist. + * This reorder process tries to get the best estimate of wait + * count by not waiting for those frames where we have a conclusive + * evidence that we don't have to wait for those frames. + */ + + /** + * If this link has already seen a frame whose timestamp is + * greater than or equal to incoming frame's timestamp, + * then no need to wait for any frames on this link. + * If the total wait count becomes zero, then the policy on + * whether to deliver such a frame to upper layers is handled + * separately. + */ + if (ath12k_mgmt_rx_reo_compare_global_timestamps_gte( + host_ss->global_timestamp, + in_frame_params->global_timestamp)) { + frames_pending = 0; + goto update_pending_frames; + } + + /** + * For starters, we only have to wait for the frames that are + * seen by MAC HW but not yet seen by Host. The frames which + * reach MAC HW later are guaranteed to have a timestamp + * greater than incoming frame's timestamp. + */ + frames_pending = ath12k_mgmt_rx_reo_subtract_pkt_ctrs( + mac_hw_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr); + BUG_ON(!(frames_pending >= 0)); + + if (frames_pending && + ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (mac_hw_ss->global_timestamp, + in_frame_params->global_timestamp)) { + /** + * Last frame seen at MAC HW has timestamp greater than + * or equal to incoming frame's timestamp. So no need to + * wait for that last frame, but we can't conclusively + * say anything about timestamp of frames before the + * last frame, so try to wait for all of those frames. + */ + frames_pending--; + BUG_ON(!(frames_pending >= 0)); + + if (fw_consumed_ss->valid && + ath12k_mgmt_rx_reo_compare_global_timestamps_gte( + fw_consumed_ss->global_timestamp, + in_frame_params->global_timestamp)) { + /** + * Last frame consumed by the FW has timestamp + * greater than or equal to incoming frame's. + * That means all the frames from + * fw_consumed_ss->mgmt_pkt_ctr to + * mac_hw->mgmt_pkt_ctr will have timestamp + * greater than or equal to incoming frame's and + * hence, no need to wait for those frames. + * We just need to wait for frames from + * host_ss->mgmt_pkt_ctr to + * fw_consumed_ss->mgmt_pkt_ctr-1. This is a + * better estimate over the above estimate, + * so update frames_pending. + */ + frames_pending = + ath12k_mgmt_rx_reo_subtract_pkt_ctrs( + fw_consumed_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr) - 1; + + BUG_ON(!(frames_pending >= 0)); + + /** + * Last frame forwarded to Host has timestamp + * less than incoming frame's. That means all + * the frames starting from + * fw_forwarded_ss->mgmt_pkt_ctr+1 to + * fw_consumed_ss->mgmt_pkt_ctr are consumed by + * the FW and hence, no need to wait for those + * frames. We just need to wait for frames + * from host_ss->mgmt_pkt_ctr to + * fw_forwarded_ss->mgmt_pkt_ctr. This is a + * better estimate over the above estimate, + * so update frames_pending. + */ + if (fw_forwarded_ss->valid && + !ath12k_mgmt_rx_reo_compare_global_timestamps_gte( + fw_forwarded_ss->global_timestamp, + in_frame_params->global_timestamp)) { + frames_pending = + ath12k_mgmt_rx_reo_subtract_pkt_ctrs( + fw_forwarded_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr); + + /** + * frames_pending can be negative in + * cases whene there are no frames + * getting forwarded to the Host. No + * need to wait for any frames in that + * case. + */ + if (frames_pending < 0) + frames_pending = 0; + } + } + + /** + * Last frame forwarded to Host has timestamp greater + * than or equal to incoming frame's. That means all the + * frames from fw_forwarded->mgmt_pkt_ctr to + * mac_hw->mgmt_pkt_ctr will have timestamp greater than + * or equal to incoming frame's and hence, no need to + * wait for those frames. We may have to just wait for + * frames from host_ss->mgmt_pkt_ctr to + * fw_forwarded_ss->mgmt_pkt_ctr-1 + */ + if (fw_forwarded_ss->valid && + ath12k_mgmt_rx_reo_compare_global_timestamps_gte( + fw_forwarded_ss->global_timestamp, + in_frame_params->global_timestamp)) { + delta_fwd_host = + ath12k_mgmt_rx_reo_subtract_pkt_ctrs( + fw_forwarded_ss->mgmt_pkt_ctr, + host_ss->mgmt_pkt_ctr) - 1; + + BUG_ON(!(delta_fwd_host >= 0)); + + /** + * This will be a better estimate over the one + * we computed using mac_hw_ss but this may or + * may not be a better estimate over the + * one we computed using fw_consumed_ss. + * When timestamps of both fw_consumed_ss and + * fw_forwarded_ss are greater than incoming + * frame's but timestamp of fw_consumed_ss is + * smaller than fw_forwarded_ss, then + * frames_pending will be smaller than + * delta_fwd_host, the reverse will be true in + * other cases. Instead of checking for all + * those cases, just waiting for the minimum + * among these two should be sufficient. + */ + frames_pending = min(frames_pending, + delta_fwd_host); + BUG_ON(!(frames_pending >= 0)); + } + } + +update_pending_frames: + BUG_ON(!(frames_pending >= 0)); + + wait_count->per_link_count[hw_link_id] = frames_pending; + wait_count->total_count += frames_pending; + +print_wait_count: + ath12k_dbg(ab, ATH12K_DBG_RX_REO, + "hw_link_id = %u wait count: per link = 0x%x, total = 0x%llx", + hw_link_id, wait_count->per_link_count[hw_link_id], + wait_count->total_count); + } + return 0; +} + +/** + * mgmt_rx_reo_prepare_list_entry() - Prepare a list entry from the management + * frame received. + * @frame_desc: Pointer to the frame descriptor + * @entry: Pointer to the list entry + * + * This API prepares the reorder list entry corresponding to a management frame + * to be consumed by host. This entry would be inserted at the appropriate + * position in the reorder list. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_prepare_list_entry(struct ath12k_base *ab, + const struct ath12k_mgmt_rx_reo_frame_descriptor *frame_desc, + struct mgmt_rx_reo_list_entry **entry) +{ + struct mgmt_rx_reo_list_entry *list_entry; + struct ath12k_mgmt_rx_reo_params *reo_params = + &frame_desc->rx_params->reo_params; + struct ath12k *ar; + u8 link_id; + + link_id = reo_params->link_id; + + if (link_id >= ATH12K_GROUP_MAX_RADIO) { + ath12k_warn(ab, "%s:invalid hw link id %d\n", __func__, link_id); + return -EINVAL; + } + + ar = rcu_dereference(ab->ag->hw_links[link_id]); + if (!ar) { + ath12k_err(ab, "ar corresponding to link %u is null\n", + link_id); + return -EINVAL; + } + + list_entry = kmalloc(sizeof(*list_entry), GFP_ATOMIC); + if (!list_entry) + return -ENOMEM; + + list_entry->ar = ar; + list_entry->nbuf = frame_desc->nbuf; + list_entry->rx_params = frame_desc->rx_params; + list_entry->wait_count = frame_desc->wait_count; + list_entry->initial_wait_count = frame_desc->wait_count; + memcpy(list_entry->shared_snapshots, frame_desc->shared_snapshots, + min(sizeof(list_entry->shared_snapshots), + sizeof(frame_desc->shared_snapshots))); + memcpy(list_entry->host_snapshot, frame_desc->host_snapshot, + min(sizeof(list_entry->host_snapshot), + sizeof(frame_desc->host_snapshot))); + list_entry->status = 0; + if (list_entry->wait_count.total_count) + list_entry->status |= + ATH12K_MGMT_RX_REO_STATUS_WAIT_FOR_FRAME_ON_OTHER_LINKS; + + *entry = list_entry; + + return 0; +} + +/** + * ath12k_mgmt_rx_reo_is_stale_frame()- API to check whether the given management frame + * is stale + * @ts_last_released_frame: pointer to global time stamp of the last frame + * removed from the reorder list + * @frame_desc: pointer to frame descriptor + * + * This API checks whether the current management frame under processing is + * stale. Any frame older than the last frame delivered to upper layer is a + * stale frame. This could happen when we have to deliver frames out of order + * due to time out or list size limit. The frames which arrive late at host and + * with time stamp lesser than the last delivered frame are stale frames and + * they need to be handled differently. + * + * Return: 0 on success, non-zero on failure. On success "is_stale" and + * "is_parallel_rx" members of + * @frame_desc will be filled with proper values. + */ +static int +ath12k_mgmt_rx_reo_is_stale_frame(struct ath12k_base *ab, + struct ath12k_mgmt_rx_reo_global_ts_info *ts_last_released_frame, + struct ath12k_mgmt_rx_reo_frame_descriptor *frame_desc) +{ + struct ath12k_mgmt_rx_reo_params *reo_params + = &frame_desc->rx_params->reo_params; + u32 cur_frame_start_ts; + u32 cur_frame_end_ts; + + if (!ts_last_released_frame) { + ath12k_err(ab, "Last released frame time stamp info is null\n"); + return -EINVAL; + } + + if (!frame_desc) { + ath12k_err(ab, "Frame descriptor is null\n"); + return -EINVAL; + } + + frame_desc->is_stale = false; + frame_desc->is_parallel_rx = false; + + if (!ts_last_released_frame->valid) + return 0; + + cur_frame_start_ts = reo_params->start_timestamp; + cur_frame_end_ts = reo_params->end_timestamp; + + frame_desc->is_stale = + !ath12k_mgmt_rx_reo_compare_global_timestamps_gte(cur_frame_start_ts, + ts_last_released_frame->start_ts); + + if (ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (ts_last_released_frame->start_ts, cur_frame_start_ts) && + ath12k_mgmt_rx_reo_compare_global_timestamps_gte + (cur_frame_end_ts, ts_last_released_frame->end_ts)) { + frame_desc->is_parallel_rx = true; + frame_desc->is_stale = false; + } + + return 0; +} + +/** + * ath12k_mgmt_rx_reo_update_wait_count() - Update the wait count for a frame based + * on the wait count of a frame received after that on air. + * @wait_count_old_frame: Pointer to the wait count structure for the old frame. + * @wait_count_new_frame: Pointer to the wait count structure for the new frame. + * + * This API optimizes the wait count of a frame based on the wait count of + * a frame received after that on air. Old frame refers to the frame received + * first on the air and new frame refers to the frame received after that. + * We use the following fundamental idea. Wait counts for old frames can't be + * more than wait counts for the new frame. Use this to optimize the wait count + * for the old frames. Per link wait count of an old frame is minimum of the + * per link wait count of the old frame and new frame. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_update_wait_count( + struct ath12k_mgmt_rx_reo_wait_count *wait_count_old_frame, + const struct ath12k_mgmt_rx_reo_wait_count *wait_count_new_frame) +{ + u8 link_id; + + for (link_id = 0; link_id < ATH12K_WMI_MLO_MAX_LINKS; link_id++) { + if (wait_count_old_frame->per_link_count[link_id]) { + u32 temp_wait_count; + u32 wait_count_diff; + + temp_wait_count = + wait_count_old_frame->per_link_count[link_id]; + wait_count_old_frame->per_link_count[link_id] = + min(wait_count_old_frame-> + per_link_count[link_id], + wait_count_new_frame-> + per_link_count[link_id]); + wait_count_diff = temp_wait_count - + wait_count_old_frame->per_link_count[link_id]; + + wait_count_old_frame->total_count -= wait_count_diff; + } + } + + return 0; +} + +/** + * ath12k_mgmt_rx_reo_update_list() - Modify the reorder list when a frame is received + * @reo_list: Pointer to reorder list + * @frame_desc: Pointer to frame descriptor + * @is_queued: Whether this frame is queued in the REO list + * + * API to update the reorder list on every management frame reception. + * This API does the following things. + * a) Update the wait counts for all the frames in the reorder list with + * global time stamp <= current frame's global time stamp. We use the + * following principle for updating the wait count in this case. + * Let A and B be two management frames with global time stamp of A <= + * global time stamp of B. Let WAi and WBi be the wait count of A and B + * for link i, then WAi <= WBi. Hence we can optimize WAi as + * min(WAi, WBi). + * b) If the current frame is to be consumed by host, insert it in the + * reorder list such that the list is always sorted in the increasing order + * of global time stamp. Update the wait count of the current frame based + * on the frame next to it in the reorder list (if any). + * c) Update the wait count of the frames in the reorder list with global + * time stamp > current frame's global time stamp. Let the current frame + * belong to link "l". Then link "l"'s wait count can be reduced by one for + * all the frames in the reorder list with global time stamp > current + * frame's global time stamp. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_update_list( + struct ath12k_base *ab, + struct mgmt_rx_reo_list *reo_list, + struct ath12k_mgmt_rx_reo_frame_descriptor *frame_desc, + bool *is_queued) +{ + struct mgmt_rx_reo_list_entry *cur_entry; + struct mgmt_rx_reo_list_entry *least_greater_entry = NULL; + bool least_greater_entry_found = false; + int status; + u32 new_frame_global_ts; + struct mgmt_rx_reo_list_entry *new_entry = NULL; + u16 list_insertion_pos = 0; + struct ath12k_mgmt_rx_reo_params *reo_params; + + if (!is_queued) + return -EINVAL; + + *is_queued = false; + + if (!reo_list) { + ath12k_err(ab, "Mgmt Rx reo list is null\n"); + return -EINVAL; + } + + if (!frame_desc) { + ath12k_err(ab, "Mgmt frame descriptor is null\n"); + return -EINVAL; + } + + if (frame_desc->rx_params) { + reo_params = &frame_desc->rx_params->reo_params; + new_frame_global_ts = reo_params->global_timestamp; + } else { + ath12k_err(ab, "null rx_param %p\n", frame_desc->rx_params); + return -EINVAL; + } + + /* Prepare the list entry before acquiring lock */ + if (frame_desc->type == ATH12K_MGMT_RX_REO_FRAME_DESC_HOST_CONSUMED_FRAME && + frame_desc->reo_required) { + status = ath12k_mgmt_rx_reo_prepare_list_entry(ab, frame_desc, &new_entry); + if (status) { + ath12k_err(ab, "Failed to prepare list entry %d\n", status); + return -EINVAL; + } + } + + spin_lock_bh(&reo_list->list_lock); + + frame_desc->list_size_rx = reo_list->count; + + status = ath12k_mgmt_rx_reo_is_stale_frame(ab, &reo_list->ts_last_released_frame, + frame_desc); + if (status) + goto exit_free_entry; + + list_for_each_entry(cur_entry, &reo_list->list, node) { + u32 cur_entry_global_ts; + struct ath12k_mgmt_rx_reo_params *cur_reo_params = + &cur_entry->rx_params->reo_params; + + cur_entry_global_ts = cur_reo_params->global_timestamp; + + if (!ath12k_mgmt_rx_reo_compare_global_timestamps_gte( + new_frame_global_ts, cur_entry_global_ts)) { + least_greater_entry = cur_entry; + least_greater_entry_found = true; + break; + } + + /* if it is stale entry at this point and gts seems to be valid + * then the reordering didn't properly happened please check the + * reordering + */ + BUG_ON(!(!frame_desc->is_stale || cur_entry->is_parallel_rx)); + + list_insertion_pos++; + + status = ath12k_mgmt_rx_reo_update_wait_count( + &cur_entry->wait_count, + &frame_desc->wait_count); + if (status) + goto exit_free_entry; + + if (cur_entry->wait_count.total_count == 0) + cur_entry->status &= + ~ATH12K_MGMT_RX_REO_STATUS_WAIT_FOR_FRAME_ON_OTHER_LINKS; + } + + if (frame_desc->type == ATH12K_MGMT_RX_REO_FRAME_DESC_HOST_CONSUMED_FRAME && + !frame_desc->is_stale && frame_desc->reo_required) { + if (least_greater_entry_found) { + status = ath12k_mgmt_rx_reo_update_wait_count( + &new_entry->wait_count, + &least_greater_entry->wait_count); + + if (status) + goto exit_free_entry; + + frame_desc->wait_count = new_entry->wait_count; + + if (new_entry->wait_count.total_count == 0) + new_entry->status &= + ~ATH12K_MGMT_RX_REO_STATUS_WAIT_FOR_FRAME_ON_OTHER_LINKS; + } + + new_entry->insertion_ts = ktime_to_us(ktime_get()); + new_entry->ingress_timestamp = frame_desc->ingress_timestamp; + new_entry->is_parallel_rx = frame_desc->is_parallel_rx; + frame_desc->list_insertion_pos = list_insertion_pos; + + if (least_greater_entry_found) + list_add_tail(&new_entry->node, &least_greater_entry->node); + else + list_add_tail(&new_entry->node, &reo_list->list); + + reo_list->count++; + + *is_queued = true; + + if (new_entry->wait_count.total_count == 0) + frame_desc->zero_wait_count_rx = true; + + if (frame_desc->zero_wait_count_rx && + list_first_entry_or_null(&reo_list->list, + struct mgmt_rx_reo_list_entry, + node) == new_entry) + frame_desc->immediate_delivery = true; + } + + if (least_greater_entry_found) { + cur_entry = least_greater_entry; + + list_for_each_entry_from(cur_entry, &reo_list->list, node) { + u8 frame_link_id; + struct ath12k_mgmt_rx_reo_wait_count *wait_count; + + frame_link_id = reo_params->link_id; + wait_count = &cur_entry->wait_count; + if (wait_count->per_link_count[frame_link_id]) { + u32 old_wait_count; + u32 new_wait_count; + u32 wait_count_diff; + u16 pkt_ctr_delta; + + pkt_ctr_delta = frame_desc->pkt_ctr_delta; + old_wait_count = + wait_count->per_link_count[frame_link_id]; + + if (old_wait_count >= pkt_ctr_delta) + new_wait_count = old_wait_count - + pkt_ctr_delta; + else + new_wait_count = 0; + + wait_count_diff = old_wait_count - + new_wait_count; + + wait_count->per_link_count[frame_link_id] = + new_wait_count; + wait_count->total_count -= wait_count_diff; + + if (wait_count->total_count == 0) + cur_entry->status &= + ~ATH12K_MGMT_RX_REO_STATUS_WAIT_FOR_FRAME_ON_OTHER_LINKS; + } + } + } + + status = 0; + +exit_free_entry: + /* Cleanup the entry if it is not queued */ + if (new_entry && !*is_queued) { + /** + * New entry created is not inserted to reorder list, free + * the entry and release the reference + */ + kfree(new_entry); + } + + spin_unlock_bh(&reo_list->list_lock); + + return status; +} + +/** + * ath12k_mgmt_rx_reo_list_is_ready_to_send_up_entry() - API to check whether the + * list entry can be send to upper layers. + * @reo_list: Pointer to reorder list + * @entry: List entry + * + * Return: 0 on success, non-zero on failure + */ +static bool +ath12k_mgmt_rx_reo_list_is_ready_to_send_up_entry(struct mgmt_rx_reo_list *reo_list, + struct mgmt_rx_reo_list_entry *entry) +{ + if (!reo_list || !entry) + return false; + + return (reo_list->count > reo_list->max_list_size) || + !ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_WAITING_FOR_FRAME_ON_OTHER_LINK( + entry) || ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_AGED_OUT(entry) || + ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_OLDER_THAN_LATEST_AGED_OUT_FRAME + (entry); +} + +/** + * ath12k_mgmt_rx_reo_list_entry_get_release_reason() - Helper API to get the reason + * for releasing the reorder list entry to upper layer. + * reorder list. + * @entry: List entry + * + * This API expects the caller to acquire the spin lock protecting the reorder + * list. + * + * Return: Reason for releasing the frame. + */ +static u8 +ath12k_mgmt_rx_reo_list_entry_get_release_reason(struct mgmt_rx_reo_list_entry *entry) +{ + u8 release_reason = 0; + + if (!entry) + return 0; + + if (ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_MAX_SIZE_EXCEEDED(entry)) + release_reason |= + MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_LIST_MAX_SIZE_EXCEEDED; + + if (!ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_WAITING_FOR_FRAME_ON_OTHER_LINK(entry)) + release_reason |= + MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_ZERO_WAIT_COUNT; + + if (ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_AGED_OUT(entry)) + release_reason |= + MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_AGED_OUT; + + if (ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_OLDER_THAN_LATEST_AGED_OUT_FRAME(entry)) + release_reason |= + MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_OLDER_THAN_AGED_OUT_FRAME; + + return release_reason; +} + +/** + * mgmt_rx_reo_is_potential_premature_delivery() - Helper API to check + * whether the current frame getting delivered to upper layer is a premature + * delivery + * @release_reason: release reason + * + * Return: true for a premature delivery + */ +static bool +ath12k_mgmt_rx_reo_is_potential_premature_delivery(u8 release_reason) +{ + return !(release_reason & + MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_ZERO_WAIT_COUNT); +} + +/** + * ath12k_mgmt_rx_reo_list_entry_send_up() - API to send the frame to the upper layer. + * @reo_list: Pointer to reorder list + * @entry: List entry + * + * API to send the frame to the upper layer. This API has to be called only + * for entries which can be released to upper layer. It is the caller's + * responsibility to ensure that entry can be released (by using API + * mgmt_rx_reo_list_is_ready_to_send_up_entry). This API is called after + * acquiring the lock which serializes the frame delivery to the upper layers. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_list_entry_send_up(struct mgmt_rx_reo_list *reo_list, + struct mgmt_rx_reo_list_entry *entry) +{ + struct ath12k *ar = entry->ar; + u8 release_reason; + u8 link_id; + u32 entry_global_ts; + int status; + struct ath12k_mgmt_rx_reo_context *reo_context; + struct ath12k_mgmt_rx_reo_params *reo_params = + &entry->rx_params->reo_params; + + if (unlikely(!rcu_access_pointer(ar->ab->pdevs_active[ar->pdev_idx]))) { + dev_kfree_skb(entry->nbuf); + goto free; + } + + reo_context = container_of(reo_list, struct ath12k_mgmt_rx_reo_context, + reo_list); + + link_id = reo_params->link_id; + entry_global_ts = reo_params->global_timestamp; + + release_reason = ath12k_mgmt_rx_reo_list_entry_get_release_reason(entry); + + //TODO remove BUG_ON once the implementation is stablized + BUG_ON(!release_reason != 0); + + entry->is_delivered = false; + entry->is_premature_delivery = false; + entry->release_reason = release_reason; + + if (ath12k_mgmt_rx_reo_is_potential_premature_delivery(release_reason)) + entry->is_premature_delivery = true; + + ath12k_dbg(ar->ab, ATH12K_DBG_RX_REO, + "Mgmt Re-order egress: channel %d valid %u global_ts %u pkt_ctr %u is_parallel_rx %d\n", + entry->rx_params->channel, + entry->rx_params->reo_params.valid, + entry->rx_params->reo_params.global_timestamp, + entry->rx_params->reo_params.mgmt_pkt_ctr, + entry->is_parallel_rx); + + ieee80211_rx_ni(entry->ar->ah->hw, entry->nbuf); + /* believing rx stack takes care of skb */ + entry->is_delivered = true; + +free: + kfree(entry->rx_params); + /*Above ieee80211_rx_ni call frees nbuf and rx_params, make it null explicitly */ + entry->nbuf = NULL; + entry->rx_params = NULL; + status = 0; + + return status; +} + +/** + * ath12k_mgmt_rx_reo_list_release_entries() - Release entries from the reorder list + * @reo_context: Pointer to management Rx reorder context + * + * This API releases the entries from the reorder list based on the following + * conditions. + * a) Entries with total wait count equal to 0 + * b) Entries which are timed out or entries with global time stamp <= global + * time stamp of the latest frame which is timed out. We can only release + * the entries in the increasing order of the global time stamp. + * So all the entries with global time stamp <= global time stamp of the + * latest timed out frame has to be released. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_list_release_entries(struct ath12k_base *ab, + struct ath12k_mgmt_rx_reo_context *reo_context) +{ + struct mgmt_rx_reo_list *reo_list; + struct ath12k_mgmt_rx_reo_params *reo_params; + int status; + + if (!reo_context) { + ath12k_err(ab, "reo context is null\n"); + return -EINVAL; + } + + reo_list = &reo_context->reo_list; + + spin_lock(&reo_context->frame_release_lock); + + while (1) { + struct mgmt_rx_reo_list_entry *first_entry; + /* TODO yield if release_count > THRESHOLD */ + u16 release_count = 0; + struct ath12k_mgmt_rx_reo_global_ts_info *ts_last_released_frame = + &reo_list->ts_last_released_frame; + u32 entry_global_ts; + + spin_lock_bh(&reo_list->list_lock); + + first_entry = list_first_entry_or_null( + &reo_list->list, struct mgmt_rx_reo_list_entry, node); + + if (!first_entry) { + status = 0; + goto exit_unlock_list_lock; + } + + if (!ath12k_mgmt_rx_reo_list_is_ready_to_send_up_entry(reo_list, + first_entry)) { + status = 0; + goto exit_unlock_list_lock; + } + + if (reo_list->count > reo_list->max_list_size) + first_entry->status |= + ATH12K_MGMT_RX_REO_STATUS_LIST_MAX_SIZE_EXCEEDED; + + list_del_init(&first_entry->node); + reo_list->count--; + + if (status) { + status = -EINVAL; + goto exit_unlock_list_lock; + } + first_entry->removal_ts = ktime_to_us(ktime_get()); + + /** + * Last released frame global time stamp is invalid means that + * current frame is the first frame to be released to the + * upper layer from the reorder list. Blindly update the last + * released frame global time stamp to the current frame's + * global time stamp and set the valid to true. + * If the last released frame global time stamp is valid and + * current frame's global time stamp is >= last released frame + * global time stamp, deliver the current frame to upper layer + * and update the last released frame global time stamp. + */ + reo_params = &first_entry->rx_params->reo_params; + entry_global_ts = reo_params->global_timestamp; + + if (!ts_last_released_frame->valid || + ath12k_mgmt_rx_reo_compare_global_timestamps_gte( + entry_global_ts, ts_last_released_frame->global_ts)) { + ts_last_released_frame->global_ts = entry_global_ts; + ts_last_released_frame->start_ts = + reo_params->start_timestamp; + ts_last_released_frame->end_ts = + reo_params->end_timestamp; + ts_last_released_frame->valid = true; + ts_last_released_frame->expiry_time = jiffies + ATH12K_MGMT_RX_REO_GLOBAL_MGMT_RX_INACTIVITY_TIMEOUT; + + } else { + /** + * This should never happen. All the frames older than + * the last frame released from the reorder list will be + * discarded at the entry to reorder process itself. + */ + BUG_ON(!first_entry->is_parallel_rx); + } + + spin_unlock_bh(&reo_list->list_lock); + + status = ath12k_mgmt_rx_reo_list_entry_send_up(reo_list, + first_entry); + if (status) { + status = -EINVAL; + kfree(first_entry); + goto exit_unlock_frame_release_lock; + } + + kfree(first_entry); + release_count++; + } + + status = 0; + goto exit_unlock_frame_release_lock; + +exit_unlock_list_lock: + spin_unlock_bh(&reo_list->list_lock); +exit_unlock_frame_release_lock: + spin_unlock(&reo_context->frame_release_lock); + + return status; +} + +static int +ath12k_wmi_mgmt_rx_reorder_process_entry(struct ath12k *ar, + struct ath12k_mgmt_rx_reo_frame_descriptor *desc, + bool *is_queued) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_mgmt_rx_reo_context *reo_ctx; + int ret; + + if (!is_queued) + return -EINVAL; + + *is_queued = false; + + if (!desc || !desc->rx_params) { + ath12k_err(ab, "MGMT Rx REO descriptor or rx params are null\n"); + return -EINVAL; + } + + reo_ctx = &ab->ag->rx_reo; + if (!reo_ctx) { + ath12k_err(ab, "REO context is NULL\n"); + return -EINVAL; + } + + if (!reo_ctx->init_done || !reo_ctx->timer_init_done) { + ath12k_err(ab, "MGMT Rx REO timer is not initialised\n"); + return -EINVAL; + } + /** + * Critical Section = Host snapshot update + Calculation of wait + * counts + Update reorder list. Following section describes the + * motivation for making this a critical section. + * Lets take an example of 2 links (Link A & B) and each has received + * a management frame A1 and B1 such that MLO global time stamp of A1 < + * MLO global time stamp of B1. Host is concurrently executing + * "ath12k_wmi_mgmt_rx_reorder_process_entry" for A1 and B1 in 2 different CPUs. + * + * A lock less version of this API("ath12k_wmi_mgmt_rx_reorder_process_entry_v1") is + * as follows. + * + * ath12k_wmi_mgmt_rx_reorder_process_entry() + * { + * Host snapshot update + * Calculation of wait counts + * Update reorder list + * Release to upper layer + * } + * + * We may run into race conditions under the following sequence of + * operations. + * + * 1. Host snapshot update for link A in context of frame A1 + * 2. Host snapshot update for link B in context of frame B1 + * 3. Calculation of wait count for frame B1 + * link A wait count = 0 + * link B wait count = 0 + * 4. Update reorder list with frame B1 + * 5. Release B1 to upper layer + * 6. Calculation of wait count for frame A1 + * link A wait count = 0 + * link B wait count = 0 + * 7. Update reorder list with frame A1 + * 8. Release A1 to upper layer + * + * This leads to incorrect behaviour as B1 goes to upper layer before + * A1. + * + * To prevent this lets make Host snapshot update + Calculate wait count + * a critical section by adding locks. The updated version of the API + * ("ath12k_wmi_mgmt_rx_reorder_process_entry_v2") is as follows. + * + * ath12k_wmi_mgmt_rx_reorder_process_entry() + * { + * LOCK + * Host snapshot update + * Calculation of wait counts + * UNLOCK + * Update reorder list + * Release to upper layer + * } + * + * With this API also We may run into race conditions under the + * following sequence of operations. + * + * 1. Host snapshot update for link A in context of frame A1 + + * Calculation of wait count for frame A1 + * link A wait count = 0 + * link B wait count = 0 + * 2. Host snapshot update for link B in context of frame B1 + + * Calculation of wait count for frame B1 + * link A wait count = 0 + * link B wait count = 0 + * 4. Update reorder list with frame B1 + * 5. Release B1 to upper layer + * 7. Update reorder list with frame A1 + * 8. Release A1 to upper layer + * + * This also leads to incorrect behaviour as B1 goes to upper layer + * before A1. + * + * + * To prevent this, let's make Host snapshot update + Calculate wait + * count + Update reorder list a critical section by adding locks. + * The updated version of the API ("ath12k_wmi_mgmt_rx_reorder_process_entry_final") + * is as follows. + * + * ath12k_wmi_mgmt_rx_reorder_process_entry() + * { + * LOCK + * Host snapshot update + * Calculation of wait counts + * Update reorder list + * UNLOCK + * Release to upper layer + * } + */ + spin_lock_bh(&reo_ctx->rx_reorder_entry_lock); + + if (unlikely(!desc->rx_params->reo_params.valid)) { + ath12k_warn(ab, "Valid bit is not set for mgmt frame\n"); + goto failure; + } + + if ((desc->type == ATH12K_MGMT_RX_REO_FRAME_DESC_HOST_CONSUMED_FRAME || + desc->type == ATH12K_MGMT_RX_REO_FRAME_DESC_FW_CONSUMED_FRAME) && + !desc->rx_params->reo_params.duration_us) { + ath12k_warn(ab, "Rx reo duration of the frame is not valid %d\n", + desc->rx_params->reo_params.duration_us); + goto failure; + } + + /* Update the Host snapshot */ + ret = ath12k_wlan_mgmt_rx_reo_update_host_snapshot(ar, desc); + if (ret) + goto failure; + + /* Compute wait count for this frame/event */ + ret = ath12k_wmi_mgmt_rx_reorder_process_calculate_wait_count(ar, desc); + if (ret) + goto failure; + + /* Update the REO list */ + ret = ath12k_mgmt_rx_reo_update_list(ab, &reo_ctx->reo_list, desc, is_queued); + if (ret) + goto failure; + + spin_unlock_bh(&reo_ctx->rx_reorder_entry_lock); + /* Finally, release the entries for which pending frame is received */ + return ath12k_mgmt_rx_reo_list_release_entries(ab, reo_ctx); + +failure: + spin_unlock_bh(&reo_ctx->rx_reorder_entry_lock); + return ret; +} + +/** + * ath12k_mgmt_rx_reo_list_ageout_timer_handler() - Periodic ageout timer handler + * @arg: Argument to timer handler + * + * This is the handler for periodic ageout timer used to timeout entries in the + * reorder list. + * + * Return: void + */ +static void +ath12k_mgmt_rx_reo_list_ageout_timer_handler(struct timer_list *timer) + +{ + struct mgmt_rx_reo_list *reo_list = from_timer(reo_list, timer, ageout_timer); + struct ath12k_base *ab = reo_list->ab; + struct mgmt_rx_reo_list_entry *cur_entry; + u64 cur_ts; + int status; + struct ath12k_mgmt_rx_reo_context *reo_context = &ab->ag->rx_reo; + /** + * Stores the pointer to the entry in reorder list for the latest aged + * out frame. Latest aged out frame is the aged out frame in reorder + * list which has the largest global time stamp value. + */ + struct mgmt_rx_reo_list_entry *latest_aged_out_entry = NULL; + + spin_lock_bh(&reo_list->list_lock); + + cur_ts = ktime_to_us(ktime_get()); + + if (list_empty(&reo_list->list)) + goto out; + + list_for_each_entry(cur_entry, &reo_list->list, node) { + if (cur_ts - cur_entry->insertion_ts >= + reo_list->list_entry_timeout_us) { + latest_aged_out_entry = cur_entry; + cur_entry->status |= ATH12K_MGMT_RX_REO_STATUS_AGED_OUT; + } + } + + if (latest_aged_out_entry) { + list_for_each_entry(cur_entry, &reo_list->list, node) { + if (cur_entry == latest_aged_out_entry) + break; + cur_entry->status |= ATH12K_MGMT_RX_REO_STATUS_OLDER_THAN_LATEST_AGED_OUT_FRAME; + } + } + + +out: + spin_unlock_bh(&reo_list->list_lock); + + if (latest_aged_out_entry) { + status = ath12k_mgmt_rx_reo_list_release_entries(ab, reo_context); + if (status) { + ath12k_err(ab, "Failed to release entries, ret = %d\n", + status); + return; + } + } + + mod_timer(&reo_list->ageout_timer, jiffies + + msecs_to_jiffies(ATH12K_MGMT_RX_REO_AGEOUT_TIMER_PERIOD_MS)); +} + +/** + * ath12k_mgmt_rx_reo_global_mgmt_rx_inactivity_timer_handler() - Timer handler + * for global management Rx inactivity timer + * @arg: Argument to timer handler + * + * This is the timer handler for tracking management Rx inactivity across + * links. + * + * Return: void + */ +static void +ath12k_mgmt_rx_reo_global_mgmt_rx_inactivity_timer_handler(struct timer_list *timer) + +{ + struct mgmt_rx_reo_list *reo_list = from_timer(reo_list, timer, global_mgmt_rx_inactivity_timer); + struct ath12k_base *ab = reo_list->ab; + struct ath12k_mgmt_rx_reo_context *reo_context = &ab->ag->rx_reo; + struct ath12k_mgmt_rx_reo_global_ts_info *ts_last_released_frame; + + ts_last_released_frame = &reo_list->ts_last_released_frame; + + spin_lock(&reo_context->frame_release_lock); + spin_lock_bh(&reo_list->list_lock); + + if (time_after(jiffies, ts_last_released_frame->expiry_time)) + memset(ts_last_released_frame, 0, sizeof(*ts_last_released_frame)); + + spin_unlock_bh(&reo_list->list_lock); + spin_unlock(&reo_context->frame_release_lock); + + mod_timer(&reo_list->global_mgmt_rx_inactivity_timer, jiffies + + ATH12K_MGMT_RX_REO_GLOBAL_MGMT_RX_INACTIVITY_TIMEOUT); +} + +/** + * mgmt_rx_reo_list_init() - Initialize the management rx-reorder list + * @reo_list: Pointer to reorder list + * + * API to initialize the management rx-reorder list. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_list_init(struct ath12k_base *ab, struct mgmt_rx_reo_list *reo_list) +{ + reo_list->max_list_size = ATH12K_MGMT_RX_REO_LIST_MAX_SIZE; + reo_list->list_entry_timeout_us = ATH12K_MGMT_RX_REO_LIST_TIMEOUT_US; + reo_list->count = 0; + reo_list->ab = ab; + INIT_LIST_HEAD(&reo_list->list); + spin_lock_init(&reo_list->list_lock); + + timer_setup(&reo_list->ageout_timer, + ath12k_mgmt_rx_reo_list_ageout_timer_handler, 0); + + reo_list->ts_last_released_frame.valid = false; + + timer_setup(&reo_list->global_mgmt_rx_inactivity_timer, + ath12k_mgmt_rx_reo_global_mgmt_rx_inactivity_timer_handler, 0); + + return 0; +} + +/** + * ath12k_mgmt_rx_reo_flush_reorder_list() - Flush all entries in the reorder list + * @reo_list: Pointer to reorder list + * + * API to flush all the entries of the reorder list. This API would acquire + * the lock protecting the list. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_flush_reorder_list(struct ath12k_base *ab, struct mgmt_rx_reo_list *reo_list) +{ + struct mgmt_rx_reo_list_entry *cur_entry, *temp; + + if (!reo_list) { + ath12k_err(ab, "reorder list is null\n"); + return -EINVAL; + } + + spin_lock_bh(&reo_list->list_lock); + + list_for_each_entry_safe(cur_entry, temp, &reo_list->list, node) { + list_del(&cur_entry->node); + dev_kfree_skb(cur_entry->nbuf); + kfree(cur_entry->rx_params); + kfree(cur_entry); + } + + spin_unlock_bh(&reo_list->list_lock); + + return 0; +} + +/** + * mgmt_rx_reo_list_deinit() - De initialize the management rx-reorder list + * @reo_list: Pointer to reorder list + * + * API to de initialize the management rx-reorder list. + * + * Return: 0 on success, non-zero on failure + */ +static int +ath12k_mgmt_rx_reo_list_deinit(struct ath12k_base *ab, struct mgmt_rx_reo_list *reo_list) +{ + int status; + + status = ath12k_mgmt_rx_reo_flush_reorder_list(ab, reo_list); + if (status) { + ath12k_err(ab, "Failed to flush the reorder list\n"); + return status; + } + + return 0; +} + + +int ath12k_mgmt_rx_reo_init_context(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mgmt_rx_reo_context *reo_context = &ag->rx_reo; + + if (!(ag->mlo_mem.is_mlo_mem_avail && ag->mgmt_rx_reorder)) + return 0; + + if (reo_context->init_done) + return 0; + + spin_lock_init(&reo_context->rx_reorder_entry_lock); + spin_lock_init(&reo_context->frame_release_lock); + + ath12k_mgmt_rx_reo_list_init(ab, &reo_context->reo_list); + + reo_context->init_done = true; + + return 0; +} + +int +ath12k_mgmt_rx_reo_deinit_context(struct ath12k_base *ab) +{ + int status; + struct ath12k_mgmt_rx_reo_context *reo_context = &ab->ag->rx_reo; + struct ath12k_hw_group *ag = ab->ag; + + if (!(ag->mlo_mem.is_mlo_mem_avail && ag->mgmt_rx_reorder)) + return 0; + + if (!reo_context->init_done) + return 0; + + status = ath12k_mgmt_rx_reo_list_deinit(ab, &reo_context->reo_list); + if (status) { + ath12k_err(ab, "Failed to de-initialize mgmt Rx reo list\n"); + return status; + } + + reo_context->init_done = false; + + return status; +} + +static void ath12k_fw_consumed_mgmt_rx_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_wmi_mgmt_rx_arg *rx_ev; + struct ath12k *ar; + struct ath12k_mgmt_rx_reo_frame_descriptor desc = {0}; + bool is_queued = false; + int ret; + + if (!(ag->mlo_mem.is_mlo_mem_avail && ag->mgmt_rx_reorder)) + return; + + rx_ev = kmalloc(sizeof(*rx_ev), GFP_ATOMIC); + if (!rx_ev) { + ath12k_err(ab, "failed to allocate rx event\n"); + return; + } + + if (ath12k_pull_fw_consumed_mgmt_rx_params_tlv(ab, skb, rx_ev) != 0) { + ath12k_warn(ab, "failed to extract mgmt rx event"); + kfree(rx_ev); + return; + } + + rcu_read_lock(); + ar = ath12k_mac_get_ar_by_pdev_id(ab, rx_ev->pdev_id); + + if (!ar) { + ath12k_warn(ab, "invalid pdev_id %d in mgmt_rx_event\n", + rx_ev->pdev_id); + goto exit; + } + + rx_ev->reo_params.link_id = rx_ev->pdev_id; + + /* Populate frame descriptor */ + desc.type = ATH12K_MGMT_RX_REO_FRAME_DESC_HOST_CONSUMED_FRAME; + desc.nbuf = NULL; /* No frame buffer */ + desc.rx_params = rx_ev; + desc.ingress_timestamp = ktime_to_us(ktime_get()); + desc.list_size_rx = -1; + desc.list_insertion_pos = -1; + + desc.frame_type = IEEE80211_FTYPE_MGMT; + desc.frame_subtype = 0xFF; + + desc.reo_required = false; + + ret = ath12k_wmi_mgmt_rx_reorder_process_entry(ar, &desc, &is_queued); + if (ret) { + ath12k_warn(ab, "Failed to execute MGMT REO reorder process\n"); + goto exit; + } + + if (is_queued) + WARN_ON(1); + +exit: + /* if the frame is queued dont free it here + * it will be taken care by the mgmt rx reorder + * process + */ + if (!is_queued) + kfree(rx_ev); + + rcu_read_unlock(); +} + static void ath12k_mgmt_rx_event(struct ath12k_base *ab, struct sk_buff *skb) { - struct ath12k_wmi_mgmt_rx_arg rx_ev = {0}; + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_wmi_mgmt_rx_arg *rx_ev; struct ath12k *ar; struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); struct ieee80211_hdr *hdr; u16 fc; struct ieee80211_supported_band *sband; + struct ath12k_peer *peer; + struct ieee80211_vif *vif; + struct ath12k_vif *ahvif; + struct ath12k_mgmt_frame_stats *mgmt_stats; + u16 frm_type = 0; + struct ath12k_mgmt_rx_reo_frame_descriptor desc = {0}; + bool is_queued = false; + int ret; - if (ath12k_pull_mgmt_rx_params_tlv(ab, skb, &rx_ev) != 0) { + rx_ev = kmalloc(sizeof(*rx_ev), GFP_ATOMIC); + if (!rx_ev) { + dev_kfree_skb(skb); + ath12k_err(ab, "failed to allocate rx event\n"); + return; + } + + + if (ath12k_pull_mgmt_rx_params_tlv(ab, skb, rx_ev) != 0) { ath12k_warn(ab, "failed to extract mgmt rx event"); dev_kfree_skb(skb); + kfree(rx_ev); return; } memset(status, 0, sizeof(*status)); ath12k_dbg(ab, ATH12K_DBG_MGMT, "mgmt rx event status %08x\n", - rx_ev.status); + rx_ev->status); rcu_read_lock(); - ar = ath12k_mac_get_ar_by_pdev_id(ab, rx_ev.pdev_id); + ar = ath12k_mac_get_ar_by_pdev_id(ab, rx_ev->pdev_id); if (!ar) { ath12k_warn(ab, "invalid pdev_id %d in mgmt_rx_event\n", - rx_ev.pdev_id); + rx_ev->pdev_id); dev_kfree_skb(skb); goto exit; } if ((test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) || - (rx_ev.status & (WMI_RX_STATUS_ERR_DECRYPT | + (rx_ev->status & (WMI_RX_STATUS_ERR_DECRYPT | WMI_RX_STATUS_ERR_KEY_CACHE_MISS | WMI_RX_STATUS_ERR_CRC))) { dev_kfree_skb(skb); goto exit; } - if (rx_ev.status & WMI_RX_STATUS_ERR_MIC) + if (rx_ev->status & WMI_RX_STATUS_ERR_MIC) status->flag |= RX_FLAG_MMIC_ERROR; - if (rx_ev.chan_freq >= ATH12K_MIN_6G_FREQ) { + if (rx_ev->chan_freq >= ATH12K_MIN_6G_FREQ && + rx_ev->chan_freq <= ATH12K_MAX_6G_FREQ) { status->band = NL80211_BAND_6GHZ; - } else if (rx_ev.channel >= 1 && rx_ev.channel <= 14) { + status->freq = rx_ev->chan_freq; + } else if (rx_ev->channel >= 1 && rx_ev->channel <= 14) { status->band = NL80211_BAND_2GHZ; - } else if (rx_ev.channel >= 36 && rx_ev.channel <= ATH12K_MAX_5G_CHAN) { + } else if (rx_ev->channel >= 36 && rx_ev->channel <= ATH12K_MAX_5G_CHAN) { status->band = NL80211_BAND_5GHZ; } else { /* Shouldn't happen unless list of advertised channels to @@ -5516,20 +11772,50 @@ goto exit; } - if (rx_ev.phy_mode == MODE_11B && + if (rx_ev->phy_mode == MODE_11B && (status->band == NL80211_BAND_5GHZ || status->band == NL80211_BAND_6GHZ)) ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi mgmt rx 11b (CCK) on 5/6GHz, band = %d\n", status->band); sband = &ar->mac.sbands[status->band]; - status->freq = ieee80211_channel_to_frequency(rx_ev.channel, + if (status->band != NL80211_BAND_6GHZ) + status->freq = ieee80211_channel_to_frequency(rx_ev->channel, status->band); - status->signal = rx_ev.snr + ATH12K_DEFAULT_NOISE_FLOOR; - status->rate_idx = ath12k_mac_bitrate_to_idx(sband, rx_ev.rate / 100); + + status->signal = rx_ev->snr + ar->rssi_offsets.rssi_offset; + status->rate_idx = ath12k_mac_bitrate_to_idx(sband, rx_ev->rate / 100); hdr = (struct ieee80211_hdr *)skb->data; fc = le16_to_cpu(hdr->frame_control); + frm_type = FIELD_GET(IEEE80211_FCTL_STYPE, fc); + + spin_lock_bh(&ab->base_lock); + + peer = ath12k_peer_find_by_addr(ab, hdr->addr1); + if(!peer) + peer = ath12k_peer_find_by_addr(ab, hdr->addr3); + if (!peer) { + spin_unlock_bh(&ab->base_lock); + goto skip_mgmt_stats; + } + + vif = peer->vif; + + spin_unlock_bh(&ab->base_lock); + + if (!vif) + goto skip_mgmt_stats; + + spin_lock_bh(&ar->data_lock); + + ahvif = ath12k_vif_to_ahvif(vif); + mgmt_stats = &ahvif->mgmt_stats; + mgmt_stats->rx_cnt[frm_type]++; + + spin_unlock_bh(&ar->data_lock); + +skip_mgmt_stats: /* Firmware is guaranteed to report all essential management frames via * WMI while it can deliver some extra via HTT. Since there can be @@ -5556,6 +11842,43 @@ * ath12k_mac_handle_beacon(ar, skb); */ + if (!(ag->mlo_mem.is_mlo_mem_avail && ag->mgmt_rx_reorder)) + goto pass_up; + + if (!rx_ev->reo_params.valid) { + ath12k_warn(ab, "Invalid MGMT rx REO param for link %u\n", + ar->pdev->hw_link_id); + goto pass_up; + } + + rx_ev->reo_params.link_id = ar->pdev->hw_link_id; + + /* Populate frame descriptor */ + desc.type = ATH12K_MGMT_RX_REO_FRAME_DESC_HOST_CONSUMED_FRAME; + desc.nbuf = skb; + desc.rx_params = rx_ev; + desc.ingress_timestamp = ktime_to_us(ktime_get()); + desc.list_size_rx = -1; + desc.list_insertion_pos = -1; + + desc.frame_type = FIELD_GET(IEEE80211_FCTL_FTYPE, fc); + desc.frame_subtype = frm_type; + + desc.reo_required = true; + ret = ath12k_wmi_mgmt_rx_reorder_process_entry(ar, &desc, &is_queued); + if (ret) { + ath12k_warn(ab, "Failed to execute MGMT REO reorder process\n"); + dev_kfree_skb(skb); + goto exit; + } + + /** + * If frame is queued, we shouldn't free up rx params + */ + if (is_queued) + goto exit; + +pass_up: ath12k_dbg(ab, ATH12K_DBG_MGMT, "event mgmt rx skb %pK len %d ftype %02x stype %02x\n", skb, skb->len, @@ -5566,9 +11889,16 @@ status->freq, status->band, status->signal, status->rate_idx); - ieee80211_rx_ni(ar->hw, skb); + ieee80211_rx_ni(ar->ah->hw, skb); exit: + /* if the frame is queued dont free it here + * it will be taken care by the mgmt rx reorder + * process + */ + if (!is_queued) + kfree(rx_ev); + rcu_read_unlock(); } @@ -5591,7 +11921,8 @@ } wmi_process_mgmt_tx_comp(ar, le32_to_cpu(tx_compl_param.desc_id), - le32_to_cpu(tx_compl_param.status)); + le32_to_cpu(tx_compl_param.status), + le32_to_cpu(tx_compl_param.ack_rssi)); ath12k_dbg(ab, ATH12K_DBG_MGMT, "mgmt tx compl ev pdev_id %d, desc_id %d, status %d", @@ -5602,8 +11933,42 @@ rcu_read_unlock(); } -static struct ath12k *ath12k_get_ar_on_scan_abort(struct ath12k_base *ab, - u32 vdev_id) +static void ath12k_offchan_tx_completion_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + struct wmi_offchan_data_tx_compl_event offchan_tx_cmpl_params = {0}; + u32 desc_id; + u32 pdev_id; + u32 status; + struct ath12k *ar; + + if (ath12k_pull_offchan_tx_compl_param_tlv(ab, skb, &offchan_tx_cmpl_params) != 0) { + ath12k_warn(ab, "failed to extract mgmt tx compl event"); + return; + } + status = __le32_to_cpu(offchan_tx_cmpl_params.status); + pdev_id = __le32_to_cpu(offchan_tx_cmpl_params.pdev_id); + desc_id = __le32_to_cpu(offchan_tx_cmpl_params.desc_id); + + rcu_read_lock(); + ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); + if (!ar) { + ath12k_warn(ab, "invalid pdev id %d in offchan_tx_compl_event\n", + pdev_id); + goto exit; + } + + wmi_process_offchan_tx_comp(ar, desc_id, status); + + ath12k_dbg(ab, ATH12K_DBG_MGMT, + "off chan tx compl ev pdev_id %d, desc_id %d, status %d", + pdev_id, desc_id, status); +exit: + rcu_read_unlock(); +} + +static struct ath12k *ath12k_get_ar_on_scan_state(struct ath12k_base *ab, + u32 vdev_id, + enum ath12k_scan_state state) { int i; struct ath12k_pdev *pdev; @@ -5615,7 +11980,7 @@ ar = pdev->ar; spin_lock_bh(&ar->data_lock); - if (ar->scan.state == ATH12K_SCAN_ABORTING && + if (ar->scan.state == state && ar->scan.vdev_id == vdev_id) { spin_unlock_bh(&ar->data_lock); return ar; @@ -5645,9 +12010,13 @@ * aborting scan's vdev id matches this event info. */ if (le32_to_cpu(scan_ev.event_type) == WMI_SCAN_EVENT_COMPLETED && - le32_to_cpu(scan_ev.reason) == WMI_SCAN_REASON_CANCELLED) - ar = ath12k_get_ar_on_scan_abort(ab, le32_to_cpu(scan_ev.vdev_id)); - else + le32_to_cpu(scan_ev.reason) == WMI_SCAN_REASON_CANCELLED) { + ar = ath12k_get_ar_on_scan_state(ab, le32_to_cpu(scan_ev.vdev_id), + ATH12K_SCAN_ABORTING); + if(!ar) + ar = ath12k_get_ar_on_scan_state(ab, le32_to_cpu(scan_ev.vdev_id), + ATH12K_SCAN_RUNNING); + } else ar = ath12k_mac_get_ar_by_vdev_id(ab, le32_to_cpu(scan_ev.vdev_id)); if (!ar) { @@ -5688,6 +12057,8 @@ ath12k_wmi_event_scan_start_failed(ar); break; case WMI_SCAN_EVENT_DEQUEUED: + __ath12k_mac_scan_finish(ar); + break; case WMI_SCAN_EVENT_PREEMPTED: case WMI_SCAN_EVENT_RESTARTED: case WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT: @@ -5706,6 +12077,7 @@ struct ieee80211_sta *sta; struct ath12k_peer *peer; struct ath12k *ar; + unsigned int link_id; if (ath12k_pull_peer_sta_kickout_ev(ab, skb, &arg) != 0) { ath12k_warn(ab, "failed to extract peer sta kickout event"); @@ -5731,16 +12103,27 @@ goto exit; } - sta = ieee80211_find_sta_by_ifaddr(ar->hw, + if (peer->mlo) + sta = ieee80211_find_sta_by_link_addrs(ar->ah->hw, arg.mac_addr, + NULL, &link_id); + else + sta = ieee80211_find_sta_by_ifaddr(ar->ah->hw, arg.mac_addr, NULL); if (!sta) { - ath12k_warn(ab, "Spurious quick kickout for STA %pM\n", - arg.mac_addr); + ath12k_warn(ab, "Spurious quick kickout for %sSTA %pM\n", + peer->mlo ? "MLO " : "", arg.mac_addr); goto exit; } - ath12k_dbg(ab, ATH12K_DBG_WMI, "peer sta kickout event %pM", - arg.mac_addr); + if (peer->mlo && peer->link_id != link_id) { + ath12k_warn(ab, + "Spurious quick kickout for MLO STA %pM with invalid link_id, peer: %d, sta: %d\n", + arg.mac_addr, peer->link_id, link_id); + goto exit; + } + + ath12k_dbg(ab, ATH12K_DBG_PEER, "peer sta kickout event %pM reason:%d", + arg.mac_addr, arg.reason); ieee80211_report_low_ack(sta, 10); @@ -5928,12 +12311,14 @@ survey->noise = le32_to_cpu(bss_ch_info_ev.noise_floor); survey->time = div_u64(total, cc_freq_hz); survey->time_busy = div_u64(busy, cc_freq_hz); - survey->time_rx = div_u64(rx_bss, cc_freq_hz); + survey->time_rx = div_u64(rx, cc_freq_hz); survey->time_tx = div_u64(tx, cc_freq_hz); + survey->time_bss_rx = div_u64(rx_bss, cc_freq_hz); survey->filled |= (SURVEY_INFO_NOISE_DBM | SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY | SURVEY_INFO_TIME_RX | + SURVEY_INFO_TIME_BSS_RX | SURVEY_INFO_TIME_TX); exit: spin_unlock_bh(&ar->data_lock); @@ -5979,31 +12364,27 @@ rcu_read_unlock(); } -static void ath12k_service_available_event(struct ath12k_base *ab, struct sk_buff *skb) +static int ath12k_wmi_tlv_services_parser(struct ath12k_base *ab, + u16 tag, u16 tag_len, + const void *ptr, + void *data) { - const void **tb; const struct wmi_service_available_event *ev; - int ret; + u32 *wmi_ext2_service_bitmap; int i, j; + u16 expected_len; + u16 wmi_max_ext2_service_words; - tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); - if (IS_ERR(tb)) { - ret = PTR_ERR(tb); - ath12k_warn(ab, "failed to parse tlv: %d\n", ret); - return; - } - - ev = tb[WMI_TAG_SERVICE_AVAILABLE_EVENT]; - if (!ev) { - ath12k_warn(ab, "failed to fetch svc available ev"); - kfree(tb); - return; + expected_len = WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32); + if (tag_len < expected_len) { + ath12k_warn(ab, "invalid length %d for the WMI services available tag 0x%x\n", + tag_len, tag); + return -EINVAL; } - /* TODO: Use wmi_service_segment_offset information to get the service - * especially when more services are advertised in multiple service - * available events. - */ + switch (tag) { + case WMI_TAG_SERVICE_AVAILABLE_EVENT: + ev = (struct wmi_service_available_event *)ptr; for (i = 0, j = WMI_MAX_SERVICE; i < WMI_SERVICE_SEGMENT_BM_SIZE32 && j < WMI_MAX_EXT_SERVICE; i++) { @@ -6015,11 +12396,42 @@ } ath12k_dbg(ab, ATH12K_DBG_WMI, - "wmi_ext_service_bitmap 0:0x%x, 1:0x%x, 2:0x%x, 3:0x%x", - ev->wmi_service_segment_bitmap[0], ev->wmi_service_segment_bitmap[1], - ev->wmi_service_segment_bitmap[2], ev->wmi_service_segment_bitmap[3]); + "wmi_ext_service_bitmap 0x%x 0x%x 0x%x 0x%x", + ev->wmi_service_segment_bitmap[0], + ev->wmi_service_segment_bitmap[1], + ev->wmi_service_segment_bitmap[2], + ev->wmi_service_segment_bitmap[3]); + break; + case WMI_TAG_ARRAY_UINT32: + wmi_ext2_service_bitmap = (u32 *)ptr; + wmi_max_ext2_service_words = tag_len / sizeof(u32); + for (i = 0, j = WMI_MAX_EXT_SERVICE; + i < wmi_max_ext2_service_words && j < WMI_MAX_EXT2_SERVICE; + i++) { + do { + if (wmi_ext2_service_bitmap[i] & + BIT(j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32)) + set_bit(j, ab->wmi_ab.svc_map); + } while (++j % WMI_AVAIL_SERVICE_BITS_IN_SIZE32); + } - kfree(tb); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi_ext2_service_bitmap 0x%04x 0x%04x 0x%04x 0x%04x", + wmi_ext2_service_bitmap[0], wmi_ext2_service_bitmap[1], + wmi_ext2_service_bitmap[2], wmi_ext2_service_bitmap[3]); + break; + } + return 0; +} + +static int ath12k_service_available_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + int ret; + + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_tlv_services_parser, + NULL); + return ret; } static void ath12k_peer_assoc_conf_event(struct ath12k_base *ab, struct sk_buff *skb) @@ -6052,6 +12464,57 @@ static void ath12k_update_stats_event(struct ath12k_base *ab, struct sk_buff *skb) { + struct ath12k_fw_stats stats = {}; + struct ath12k *ar; + int ret; + + INIT_LIST_HEAD(&stats.pdevs); + INIT_LIST_HEAD(&stats.vdevs); + INIT_LIST_HEAD(&stats.bcn); + + ret = ath12k_wmi_pull_fw_stats(ab, skb, &stats); + if (ret) { + ath12k_warn(ab, "failed to pull fw stats: %d\n", ret); + goto free; + } + + rcu_read_lock(); + ar = ath12k_mac_get_ar_by_pdev_id(ab, stats.pdev_id); + if (!ar) { + rcu_read_unlock(); + ath12k_warn(ab, "failed to get ar for pdev_id %d: %d\n", + stats.pdev_id, ret); + goto free; + } + + spin_lock_bh(&ar->data_lock); + + /* WMI_REQUEST_PDEV_STAT can be requested via .get_txpower mac ops or via + * debugfs fw stats. Therfore, processing it separately. + */ + if (stats.stats_id == WMI_REQUEST_PDEV_STAT) { + list_splice_tail_init(&stats.pdevs, &ar->fw_stats.pdevs); + ar->fw_stats_done = true; + goto complete; + } + + /* WMI_REQUEST_VDEV_STAT and WMI_REQUEST_BCN_STAT are currently requested + * only via debugfs fw stats. Hence, processing these two in debugfs context + */ + ath12k_debugfs_fw_stats_process(ar, &stats); + +complete: + complete(&ar->fw_stats_complete); + rcu_read_unlock(); + spin_unlock_bh(&ar->data_lock); + + /* Since the stats's pdev, vdev and beacon list are spliced and reinitialised + * at this point, no need to free the individual list. + */ + return; + +free: + ath12k_fw_stats_free(&stats); } /* PDEV_CTL_FAILSAFE_CHECK_EVENT is received from FW when the frequency scanned @@ -6098,11 +12561,8 @@ const u32 *vdev_ids) { int i; - struct ath12k_vif *arvif; - - /* Finish CSA once the switch count becomes NULL */ - if (ev->current_switch_count) - return; + struct ath12k_link_vif *arvif; + struct ieee80211_bss_conf *link_conf; rcu_read_lock(); for (i = 0; i < le32_to_cpu(ev->num_vdevs); i++) { @@ -6113,9 +12573,24 @@ vdev_ids[i]); continue; } + link_conf = rcu_dereference(arvif->ahvif->vif->link_conf[arvif->link_id]); + + if (!link_conf) + continue; - if (arvif->is_up && arvif->vif->bss_conf.csa_active) - ieee80211_csa_finish(arvif->vif); + /* FIXME some changes are expected for ML vifs */ + if (arvif->is_up && (link_conf->csa_active || link_conf->color_change_active)) { + if (!ev->current_switch_count) { + if (link_conf->csa_active) + ieee80211_csa_finish_mlo(arvif->ahvif->vif, arvif->link_id); + } else if (ev->current_switch_count > 1) { + ieee80211_beacon_update_cntdwn_mlo(arvif->ahvif->vif, + arvif->link_id); + } else { + if (link_conf->color_change_active) + ieee80211_color_change_finish_mlo(arvif->ahvif->vif, arvif->link_id); + } + } } rcu_read_unlock(); } @@ -6198,32 +12673,530 @@ if (ar->dfs_block_radar_events) ath12k_info(ab, "DFS Radar detected, but ignored as requested\n"); else - ieee80211_radar_detected(ar->hw); + ieee80211_radar_detected(ar->ah->hw); exit: kfree(tb); } +static int ath12k_wmi_awgn_intf_subtlv_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + int ret = 0; + struct wmi_dcs_awgn_info *awgn_info; + + switch (tag) { + case WMI_TAG_DCS_AWGN_INT_TYPE: + awgn_info = (struct wmi_dcs_awgn_info *)ptr; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "AWGN Info: channel width: %d, chan freq: %d, center_freq0: %d, center_freq1: %d, bw_intf_bitmap: %d\n", + awgn_info->channel_width, awgn_info->chan_freq, awgn_info->center_freq0, awgn_info->center_freq1, + awgn_info->chan_bw_interference_bitmap); + memcpy(data, awgn_info, sizeof(*awgn_info)); + break; + default: + ath12k_warn(ab, + "Received invalid tag for wmi dcs interference in subtlvs\n"); + return -EINVAL; + break; + } + + return ret; +} + +static int ath12k_wmi_dcs_awgn_event_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + int ret = 0; + + ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi dcs awgn event tag 0x%x of len %d rcvd\n", + tag, len); + + switch (tag) { + case WMI_TAG_DCS_INTERFERENCE_EVENT: + /* Fixed param is already processed*/ + break; + case WMI_TAG_ARRAY_STRUCT: + /* len 0 is expected for array of struct when there + * is no content of that type to pack inside that tlv + */ + if (len == 0) + return 0; + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_awgn_intf_subtlv_parser, + data); + break; + default: + ath12k_warn(ab, "Received invalid tag for wmi dcs interference event\n"); + ret = -EINVAL; + break; + } + + return ret; +} + +bool ath12k_wmi_validate_dcs_awgn_info(struct ath12k *ar, struct wmi_dcs_awgn_info *awgn_info) +{ + spin_lock_bh(&ar->data_lock); + + if (!ar->rx_channel) { + spin_unlock_bh(&ar->data_lock); + return false; + } + + if (awgn_info->chan_freq != ar->rx_channel->center_freq) { + spin_unlock_bh(&ar->data_lock); + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "dcs interference event received with wrong channel %d",awgn_info->chan_freq); + return false; + } + spin_unlock_bh(&ar->data_lock); + + switch (awgn_info->channel_width) { + case WMI_HOST_CHAN_WIDTH_20: + if (awgn_info->chan_bw_interference_bitmap > WMI_DCS_SEG_PRI20) { + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "dcs interference event received with wrong chan width bmap %d for 20MHz", + awgn_info->chan_bw_interference_bitmap); + return false; + } + break; + case WMI_HOST_CHAN_WIDTH_40: + if (awgn_info->chan_bw_interference_bitmap > WMI_DCS_SEG_SEC20) { + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "dcs interference event received with wrong chan width bmap %d for 40MHz", + awgn_info->chan_bw_interference_bitmap); + return false; + } + break; + case WMI_HOST_CHAN_WIDTH_80: + if (awgn_info->chan_bw_interference_bitmap > WMI_DCS_SEG_SEC40) { + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "dcs interference event received with wrong chan width bmap %d for 80MHz", + awgn_info->chan_bw_interference_bitmap); + return false; + } + break; + case WMI_HOST_CHAN_WIDTH_160: + case WMI_HOST_CHAN_WIDTH_80P80: + if (awgn_info->chan_bw_interference_bitmap > WMI_DCS_SEG_SEC80) { + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "dcs interference event received with wrong chan width bmap %d for 80P80/160MHz", + awgn_info->chan_bw_interference_bitmap); + return false; + } + break; + case WMI_HOST_CHAN_WIDTH_320: + if (awgn_info->chan_bw_interference_bitmap > WMI_DCS_SEG_SEC160) { + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "dcs interference event received with wrong chan width bmap %d for 320MHz", + awgn_info->chan_bw_interference_bitmap); + return false; + } + break; + default: + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "dcs interference event received with unknown channel width %d", + awgn_info->channel_width); + return false; + } + return true; +} + +static void +ath12k_wmi_dcs_awgn_interference_event(struct ath12k_base *ab, + struct sk_buff *skb) +{ + const struct wmi_dcs_interference_ev *dcs_intf_ev; + struct wmi_dcs_awgn_info awgn_info = {}; + struct cfg80211_chan_def *chandef; + struct ath12k_mac_any_chandef_arg arg; + struct ath12k *ar; + const struct wmi_tlv *tlv; + struct ath12k_hw *ah; + u16 tlv_tag; + u8 *ptr; + int ret; + + if (!test_bit(WMI_TLV_SERVICE_DCS_AWGN_INT_SUPPORT, ab->wmi_ab.svc_map)) { + ath12k_warn(ab, "firmware doesn't support awgn interference, so dropping dcs interference ev\n"); + return; + } + + ptr = skb->data; + + if (skb->len < (sizeof(*dcs_intf_ev) + TLV_HDR_SIZE)) { + ath12k_warn(ab, "dcs interference event size invalid\n"); + return; + } + + tlv = (struct wmi_tlv *)ptr; + tlv_tag = FIELD_GET(WMI_TLV_TAG, tlv->header); + ptr += sizeof(*tlv); + + if (tlv_tag == WMI_TAG_DCS_INTERFERENCE_EVENT) { + dcs_intf_ev = (struct wmi_dcs_interference_ev*)ptr; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "pdev awgn detected on pdev %d, interference type %d\n", + dcs_intf_ev->pdev_id, dcs_intf_ev->interference_type); + + if (dcs_intf_ev->interference_type != WMI_DCS_AWGN_INTF) { + ath12k_warn(ab, "interference type is not awgn\n"); + return; + } + } else { + ath12k_warn(ab, "dcs interference event received with wrong tag\n"); + return; + } + + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_dcs_awgn_event_parser, + &awgn_info); + if (ret) { + ath12k_warn(ab, "failed to parse awgn tlv %d\n", ret); + return; + } + + rcu_read_lock(); + ar = ath12k_mac_get_ar_by_pdev_id(ab, dcs_intf_ev->pdev_id); + if (!ar) { + ath12k_warn(ab, "awgn detected in invalid pdev id(%d)\n", + dcs_intf_ev->pdev_id); + goto exit; + } + if (!ar->supports_6ghz) { + ath12k_warn(ab, "pdev does not supports 6G, so dropping dcs interference event\n"); + goto exit; + } + + spin_lock_bh(&ar->data_lock); + if (ar->awgn_intf_handling_in_prog) { + spin_unlock_bh(&ar->data_lock); + rcu_read_unlock(); + return; + } + spin_unlock_bh(&ar->data_lock); + + if (!ath12k_wmi_validate_dcs_awgn_info(ar, &awgn_info)) { + ath12k_warn(ab, "Invalid DCS AWGN TLV - Skipping event"); + goto exit; + } + + ah = ar->ah; + + ath12k_info(ab, "Interface(pdev %d) : AWGN interference detected\n", + dcs_intf_ev->pdev_id); + + arg.ar = ar; + arg.def = NULL; + + ieee80211_iter_chan_contexts_atomic(ah->hw, ath12k_mac_get_any_chandef_iter, + &arg); + chandef = arg.def; + if (!chandef) { + ath12k_warn(ab, "chandef is not available\n"); + goto exit; + } + ar->awgn_chandef = *chandef; + + /* ieee80211_awgn_detected(ah->hw, awgn_info.chan_bw_interference_bitmap, */ + /* chandef->chan); */ + + spin_lock_bh(&ar->data_lock); + ar->awgn_intf_handling_in_prog = true; + ar->chan_bw_interference_bitmap = awgn_info.chan_bw_interference_bitmap; + spin_unlock_bh(&ar->data_lock); + + ath12k_dbg(ab, ATH12K_DBG_WMI, "AWGN : Interference handling started\n"); +exit: + rcu_read_unlock(); +} + +#ifdef CONFIG_ATH12K_PKTLOG +static void +ath12k_wmi_pktlog_decode_info(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct ath12k *ar; + const void **tb; + int ret; + struct ath_pktlog *pktlog; + struct ath_pl_fw_info *pktlog_info; + + if (!test_bit(WMI_TLV_SERVICE_PKTLOG_DECODE_INFO_SUPPORT, ab->wmi_ab.svc_map)) { + ath12k_warn(ab, "firmware doesn't support pktlog decode info support\n"); + return; + } + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, "failed to parse tlv: %d\n", ret); + return; + } + pktlog_info = tb[WMI_TAG_PDEV_PKTLOG_DECODE_INFO]; + if (!pktlog_info) { + ath12k_warn(ab, "failed to fetch pktlog debug info"); + kfree(tb); + return; + } + + pktlog_info->pdev_id = DP_SW2HW_MACID(pktlog_info->pdev_id); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "pktlog pktlog_defs_json_version: %d", pktlog_info->pktlog_defs_json_version); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "pktlog software_image: %s", pktlog_info->software_image); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "pktlog chip_info: %s", pktlog_info->chip_info); + ath12k_dbg(ab, ATH12K_DBG_WMI, + "pktlog pdev_id: %d", pktlog_info->pdev_id); + + ar = ath12k_mac_get_ar_by_pdev_id(ab, pktlog_info->pdev_id); + if (!ar) { + ath12k_warn(ab, "invalid pdev id in pktlog decode info %d", pktlog_info->pdev_id); + kfree(tb); + return; + } + pktlog = &ar->debug.pktlog; + pktlog->fw_version_record = 1; + if (pktlog->buf == NULL) { + ath12k_warn(ab, "failed to initialize, start pktlog\n"); + kfree(tb); + return; + } + pktlog->buf->bufhdr.magic_num = PKTLOG_MAGIC_NUM_FW_VERSION_SUPPORT; + memcpy(pktlog->buf->bufhdr.software_image, pktlog_info->software_image, sizeof(pktlog_info->software_image)); + memcpy(pktlog->buf->bufhdr.chip_info, pktlog_info->chip_info, sizeof(pktlog_info->chip_info)); + pktlog->buf->bufhdr.pktlog_defs_json_version = pktlog_info->pktlog_defs_json_version; + ath12k_dbg(ab, ATH12K_DBG_WMI, + "pktlog new magic_num: 0x%x\n", pktlog->buf->bufhdr.magic_num); + kfree(tb); +} +#endif + +static int +ath12k_wmi_rssi_dbm_conv_subtlv_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_rssi_dbm_conv_offsets *rssi_offsets = + (struct wmi_rssi_dbm_conv_offsets *) data; + struct wmi_rssi_dbm_conv_param_info *param_info; + struct wmi_rssi_dbm_conv_temp_offset *temp_offset_info; + int i, ret = 0; + s8 min_nf = 0; + + switch (tag) { + case WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO: + if (len != sizeof(*param_info)) { + ath12k_warn(ab, "wmi rssi dbm conv subtlv 0x%x invalid len rcvd", + tag); + return -EINVAL; + } + param_info = (struct wmi_rssi_dbm_conv_param_info *)ptr; + + /* Using minimum pri20 Noise Floor across active chains instead + * of all sub-bands*/ + for (i = 0; i < MAX_NUM_ANTENNA; i++) { + if (param_info->curr_rx_chainmask & (0x01 << i)) + min_nf = min(param_info->nf_hw_dbm[i][0], min_nf); + } + rssi_offsets->min_nf_dbm = min_nf; + break; + case WMI_TAG_RSSI_DBM_CONVERSION_TEMP_OFFSET_INFO: + if (len != sizeof(*temp_offset_info)) { + ath12k_warn(ab, "wmi rssi dbm conv subtlv 0x%x invalid len rcvd", + tag); + return -EINVAL; + } + temp_offset_info = (struct wmi_rssi_dbm_conv_temp_offset *)ptr; + rssi_offsets->rssi_temp_offset = temp_offset_info->rssi_temp_offset; + break; + default: + ath12k_warn(ab, "Received invalid sub-tag for wmi rssi dbm conversion\n"); + ret = -EINVAL; + } + return ret; +} + +static int +ath12k_wmi_rssi_dbm_conv_event_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + int ret = 0; + + ath12k_dbg(ab, ATH12K_DBG_WMI, "wmi rssi dbm conv tag 0x%x of len %d rcvd", + tag, len); + switch (tag) { + case WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO_FIXED_PARAM: + /* Fixed param is already processed*/ + break; + case WMI_TAG_ARRAY_STRUCT: + /* len 0 is expected for array of struct when there + * is no content of that type inside that tlv + */ + if (len == 0) + return ret; + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_rssi_dbm_conv_subtlv_parser, + data); + break; + default: + ath12k_warn(ab, "Received invalid tag for wmi rssi dbm conv interference event\n"); + ret = -EINVAL; + break; + + } + + return ret; +} + +static struct +ath12k *ath12k_wmi_rssi_dbm_process_fixed_param( struct ath12k_base *ab, + u8 *ptr, size_t len) +{ + struct ath12k *ar; + const struct wmi_tlv *tlv; + struct wmi_rssi_dbm_conv_event_fixed_param *fixed_param; + u16 tlv_tag; + + if(!ptr) { + ath12k_warn(ab, "No data present in rssi dbm conv event\n"); + return NULL; + } + + if (len < (sizeof(*fixed_param) + TLV_HDR_SIZE)) { + ath12k_warn(ab, "rssi dbm conv event size invalid\n"); + return NULL; + } + + tlv = (struct wmi_tlv *)ptr; + tlv_tag = FIELD_GET(WMI_TLV_TAG, tlv->header); + ptr += sizeof(*tlv); + + if (tlv_tag == WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO_FIXED_PARAM) { + fixed_param = (struct wmi_rssi_dbm_conv_event_fixed_param *)ptr; + + ar = ath12k_mac_get_ar_by_pdev_id(ab, fixed_param->pdev_id); + if (!ar) { + ath12k_warn(ab, "Failed to get ar for rssi dbm conv event\n"); + return NULL; + } + } else { + ath12k_warn(ab, "rssi dbm conv event received without fixed param tlv at start\n"); + return NULL; + } + + return ar; +} + +static void ath12k_wmi_rssi_dbm_conversion_param_info(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct ath12k *ar; + struct wmi_rssi_dbm_conv_offsets *rssi_offsets; + int ret, i; + + /* if pdevs are not active ignore the event */ + for (i = 0; i < ab->num_radios; i++) { + if (!ab->pdevs_active[i]) + return; + } + + ar = ath12k_wmi_rssi_dbm_process_fixed_param(ab, skb->data, + skb->len); + if(!ar) { + ath12k_warn(ab, "failed to get ar from rssi dbm conversion event\n"); + return; + } + + rssi_offsets = &ar->rssi_offsets; + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_rssi_dbm_conv_event_parser, + rssi_offsets); + if (ret) { + ath12k_warn(ab, "Unable to parse rssi dbm conversion event\n"); + return; + } + + rssi_offsets->rssi_offset = rssi_offsets->min_nf_dbm + + rssi_offsets->rssi_temp_offset; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "RSSI offset updated, current offset is %d\n", + rssi_offsets->rssi_offset); +} + +static void ath12k_wmi_tm_event_segmented(struct ath12k_base *ab, u32 cmd_id, + struct sk_buff *skb) +{ + const void **tb; + const struct wmi_ftm_event_msg *ev; + u16 length; + int ret; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, "failed to parse ftm event tlv: %d\n", ret); + return; + } + + ev = tb[WMI_TAG_ARRAY_BYTE]; + if (!ev) { + ath12k_warn(ab, "failed to fetch ftm msg\n"); + kfree(tb); + return; + } + + length = skb->len - TLV_HDR_SIZE; + ret = ath12k_tm_process_event(ab, cmd_id, ev, length); + if (ret) + ath12k_warn(ab, "Failed to process ftm event\n"); + kfree(tb); +} static void ath12k_wmi_pdev_temperature_event(struct ath12k_base *ab, struct sk_buff *skb) { struct ath12k *ar; - struct wmi_pdev_temperature_event ev = {0}; + const void **tb; + int ret; + const struct wmi_pdev_temperature_event *ev; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, "failed to parse tlv: %d\n", ret); + return; + } - if (ath12k_pull_pdev_temp_ev(ab, skb->data, skb->len, &ev) != 0) { - ath12k_warn(ab, "failed to extract pdev temperature event"); + ev = tb[WMI_TAG_PDEV_TEMPERATURE_EVENT]; + if (!ev) { + ath12k_warn(ab, "failed to fetch pdev temp ev"); + kfree(tb); return; } ath12k_dbg(ab, ATH12K_DBG_WMI, - "pdev temperature ev temp %d pdev_id %d\n", ev.temp, ev.pdev_id); + "pdev temperature ev temp %d pdev_id %d\n", ev->temp, + ev->pdev_id); - ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(ev.pdev_id)); + ar = ath12k_mac_get_ar_by_pdev_id(ab, le32_to_cpu(ev->pdev_id)); if (!ar) { - ath12k_warn(ab, "invalid pdev id in pdev temperature ev %d", ev.pdev_id); + ath12k_warn(ab, "invalid pdev id in pdev temperature ev %d", + ev->pdev_id); return; } + + ath12k_thermal_event_temperature(ar, ev->temp); + + kfree(tb); } static void ath12k_fils_discovery_event(struct ath12k_base *ab, @@ -6288,6 +13261,1056 @@ kfree(tb); } +static int ath12k_tpc_get_reg_pwr(struct ath12k_base *ab, + struct wmi_tpc_stats_event *tpc_stats, + struct wmi_max_reg_power_fixed_param *ev) +{ + int total_size; + struct wmi_max_reg_power_allowed *reg_pwr; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "Received reg power array type %d length %d for tpc stats\n", + ev->reg_power_type, ev->reg_array_len); + + switch (ev->reg_power_type) { + case TPC_STATS_REG_PWR_ALLOWED_TYPE: + reg_pwr = &tpc_stats->max_reg_allowed_power; + break; + default: + goto out; + } + + /* Each entry is 2 byte hence multiplying the indices with 2 */ + total_size = (ev->d1 * ev->d2 * ev->d3 * ev->d4 * 2); + if (ev->reg_array_len != total_size) { + ath12k_warn(ab, + "Total size and reg_array_len doesn't match for tpc stats\n"); + return -EINVAL; + } + + memcpy(®_pwr->tpc_reg_pwr, ev, sizeof(struct wmi_max_reg_power_fixed_param)); + + reg_pwr->reg_pwr_array = kzalloc(reg_pwr->tpc_reg_pwr.reg_array_len, + GFP_ATOMIC); + if (!reg_pwr->reg_pwr_array) + return -ENOMEM; + + tpc_stats->tlvs_rcvd |= WMI_TPC_REG_PWR_ALLOWED; +out: + return 0; +} + +static int ath12k_tpc_get_rate_array(struct ath12k_base *ab, + struct wmi_tpc_stats_event *tpc_stats, + struct wmi_tpc_rates_array_fixed_param *ev) +{ + u32 flag = 0; + struct wmi_tpc_rates_array *rates_array; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "Received rates array type %d length %d for tpc stats\n", + ev->rate_array_type, ev->rate_array_len); + + switch (ev->rate_array_type) { + case ATH12K_TPC_STATS_RATES_ARRAY1: + rates_array = &tpc_stats->rates_array1; + flag = WMI_TPC_RATES_ARRAY1; + break; + case ATH12K_TPC_STATS_RATES_ARRAY2: + rates_array = &tpc_stats->rates_array2; + flag = WMI_TPC_RATES_ARRAY2; + break; + default: + ath12k_warn(ab, + "Received invalid type of rates array for tpc stats\n"); + return -EINVAL; + } + memcpy(&rates_array->tpc_rates_array, ev, sizeof(struct wmi_tpc_rates_array_fixed_param)); + rates_array->rate_array = kzalloc(rates_array->tpc_rates_array.rate_array_len, + GFP_ATOMIC); + if (!rates_array->rate_array) + return -ENOMEM; + + tpc_stats->tlvs_rcvd |= flag; + return 0; +} + +static int ath12k_tpc_get_ctl_pwr_tbl(struct ath12k_base *ab, + struct wmi_tpc_stats_event *tpc_stats, + struct wmi_tpc_ctl_pwr_fixed_param *ev) +{ + int total_size, ret = 0; + u32 flag = 0; + struct wmi_tpc_ctl_pwr_table *ctl_array; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "Received ctl array type %d length %d for tpc stats\n", + ev->ctl_array_type, ev->ctl_array_len); + + switch (ev->ctl_array_type) { + case ATH12K_TPC_STATS_CTL_ARRAY: + ctl_array = &tpc_stats->ctl_array; + flag = WMI_TPC_CTL_PWR_ARRAY; + break; + default: + ath12k_warn(ab, + "Received invalid type of ctl pwr table for tpc stats\n"); + return -EINVAL; + } + + total_size = (ev->d1 * ev->d2 * ev->d3 * ev->d4); + if (ev->ctl_array_len != total_size) { + ath12k_warn(ab, + "Total size and ctl_array_len doesn't match for tpc stats\n"); + return -EINVAL; + } + + memcpy(&ctl_array->tpc_ctl_pwr, ev, sizeof(struct wmi_tpc_ctl_pwr_fixed_param)); + + ctl_array->ctl_pwr_table = kzalloc(ctl_array->tpc_ctl_pwr.ctl_array_len, + GFP_ATOMIC); + if (!ctl_array->ctl_pwr_table) + return -ENOMEM; + + tpc_stats->tlvs_rcvd |= flag; + return ret; +} + +static int ath12k_wmi_tpc_stats_subtlv_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + int ret = 0; + struct wmi_tpc_stats_event *tpc_stats = (struct wmi_tpc_stats_event *)data; + struct wmi_tpc_configs *tpc_config; + struct wmi_max_reg_power_fixed_param *tpc_reg_pwr; + struct wmi_tpc_rates_array_fixed_param *tpc_rates_array; + struct wmi_tpc_ctl_pwr_fixed_param *tpc_ctl_pwr; + + if (!tpc_stats) { + ath12k_warn(ab, "tpc stats memory unavailable\n"); + return -EINVAL; + } + + switch (tag) { + case WMI_TAG_TPC_STATS_CONFIG_EVENT: + tpc_config = (struct wmi_tpc_configs *)ptr; + memcpy(&tpc_stats->tpc_config, tpc_config, + sizeof(struct wmi_tpc_configs)); + break; + + case WMI_TAG_TPC_STATS_REG_PWR_ALLOWED: + tpc_reg_pwr = (struct wmi_max_reg_power_fixed_param *)ptr; + ret = ath12k_tpc_get_reg_pwr(ab, tpc_stats, tpc_reg_pwr); + break; + + case WMI_TAG_TPC_STATS_RATES_ARRAY: + tpc_rates_array = (struct wmi_tpc_rates_array_fixed_param *)ptr; + ret = ath12k_tpc_get_rate_array(ab, tpc_stats, tpc_rates_array); + break; + + case WMI_TAG_TPC_STATS_CTL_PWR_TABLE_EVENT: + tpc_ctl_pwr = (struct wmi_tpc_ctl_pwr_fixed_param *)ptr; + ret = ath12k_tpc_get_ctl_pwr_tbl(ab, tpc_stats, tpc_ctl_pwr); + break; + + default: + ath12k_warn(ab, + "Received invalid tag for tpc stats in subtlvs\n"); + return -EINVAL; + } + return ret; +} + +static int ath12k_wmi_tpc_stats_copy_buffer(struct ath12k_base *ab, + const void *ptr, u16 tag, u16 len, + struct wmi_tpc_stats_event *tpc_stats) +{ + s16 *reg_rates_src; + s8 *ctl_src; + s16 *dst_ptr; + s8 *dst_ptr_ctl; + int ret = 0; + + if (tag == WMI_TAG_ARRAY_INT16) + reg_rates_src = (s16 *)ptr; + else + ctl_src = (s8 *)ptr; + + switch (tpc_stats->event_count) { + case ATH12K_TPC_STATS_CONFIG_REG_PWR_EVENT: + if (tpc_stats->tlvs_rcvd & WMI_TPC_REG_PWR_ALLOWED) { + dst_ptr = tpc_stats->max_reg_allowed_power.reg_pwr_array; + memcpy(dst_ptr, reg_rates_src, + tpc_stats->max_reg_allowed_power.tpc_reg_pwr.reg_array_len); + reg_rates_src += tpc_stats->max_reg_allowed_power.tpc_reg_pwr.reg_array_len; + } + break; + case ATH12K_TPC_STATS_RATES_EVENT1: + if (tpc_stats->tlvs_rcvd & WMI_TPC_RATES_ARRAY1) { + dst_ptr = tpc_stats->rates_array1.rate_array; + memcpy(dst_ptr, reg_rates_src, + tpc_stats->rates_array1.tpc_rates_array.rate_array_len); + reg_rates_src += tpc_stats->rates_array1.tpc_rates_array.rate_array_len; + } + break; + case ATH12K_TPC_STATS_RATES_EVENT2: + if (tpc_stats->tlvs_rcvd & WMI_TPC_RATES_ARRAY2) { + dst_ptr = tpc_stats->rates_array2.rate_array; + memcpy(dst_ptr, reg_rates_src, + tpc_stats->rates_array2.tpc_rates_array.rate_array_len); + reg_rates_src += tpc_stats->rates_array2.tpc_rates_array.rate_array_len; + } + break; + case ATH12K_TPC_STATS_CTL_TABLE_EVENT: + if (tpc_stats->tlvs_rcvd & WMI_TPC_CTL_PWR_ARRAY) { + dst_ptr_ctl = tpc_stats->ctl_array.ctl_pwr_table; + memcpy(dst_ptr_ctl, ctl_src, + tpc_stats->ctl_array.tpc_ctl_pwr.ctl_array_len); + ctl_src += tpc_stats->ctl_array.tpc_ctl_pwr.ctl_array_len; + } + break; + } + return ret; +} + +static int ath12k_wmi_tpc_stats_event_parser(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_tpc_stats_event *tpc_stats = (struct wmi_tpc_stats_event *)data; + int ret = 0; + + ath12k_dbg(ab, ATH12K_DBG_WMI, "tpc stats tag 0x%x of len %d rcvd\n", + tag, len); + switch (tag) { + case WMI_TAG_CTRL_PATH_EVENT_FIXED_PARAM: + /* Fixed param is already processed*/ + break; + + case WMI_TAG_ARRAY_STRUCT: + /* len 0 is expected for array of struct when there + * is no content of that type to pack inside that tlv + */ + if (len == 0) + return 0; + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_tpc_stats_subtlv_parser, + tpc_stats); + break; + + case WMI_TAG_ARRAY_INT16: + if (len == 0) + return 0; + ret = ath12k_wmi_tpc_stats_copy_buffer(ab, ptr, + WMI_TAG_ARRAY_INT16, + len, tpc_stats); + break; + + case WMI_TAG_ARRAY_BYTE: + if (len == 0) + return 0; + ret = ath12k_wmi_tpc_stats_copy_buffer(ab, ptr, + WMI_TAG_ARRAY_BYTE, + len, tpc_stats); + break; + + default: + ath12k_warn(ab, "Received invalid tag for tpc stats\n"); + ret = -EINVAL; + break; + } + return ret; +} + +void ath12k_wmi_free_tpc_stats_mem(struct ath12k *ar) +{ + struct wmi_tpc_stats_event *tpc_stats = ar->tpc_stats; + + lockdep_assert_held(&ar->data_lock); + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "tpc stats mem free\n"); + if (tpc_stats) { + kfree(tpc_stats->max_reg_allowed_power.reg_pwr_array); + kfree(tpc_stats->rates_array1.rate_array); + kfree(tpc_stats->rates_array2.rate_array); + kfree(tpc_stats->ctl_array.ctl_pwr_table); + kfree(tpc_stats); + ar->tpc_stats = NULL; + } +} + +static struct ath12k *ath12k_wmi_tpc_process_fixed_param(struct ath12k_base *ab, + u8 *ptr, size_t len) +{ + struct ath12k *ar; + const struct wmi_tlv *tlv; + struct wmi_cp_stats_event_fixed_param *fixed_param; + struct wmi_tpc_stats_event *tpc_stats; + u16 tlv_tag; + + if (!ptr) { + ath12k_warn(ab, "No data present in tpc stats event\n"); + return NULL; + } + + if (len < (sizeof(*fixed_param) + TLV_HDR_SIZE)) { + ath12k_warn(ab, "tpc stats event size invalid\n"); + return NULL; + } + + tlv = (struct wmi_tlv *)ptr; + tlv_tag = FIELD_GET(WMI_TLV_TAG, tlv->header); + ptr += sizeof(*tlv); + + if (tlv_tag == WMI_TAG_CTRL_PATH_EVENT_FIXED_PARAM) { + fixed_param = (struct wmi_cp_stats_event_fixed_param *)ptr; + + ar = ath12k_mac_get_ar_by_pdev_id(ab, fixed_param->pdev_id); + if (!ar) { + ath12k_warn(ab, "Failed to get ar for tpc stats\n"); + return NULL; + } + } else { + ath12k_warn(ab, "TPC Stats received without fixed param tlv at start\n"); + return NULL; + } + + spin_lock_bh(&ar->data_lock); + if (!ar->tpc_request) { + /* Event is received either without request or the + * timeout, if memory is already allocated free it + */ + if (ar->tpc_stats) { + ath12k_warn(ab, "Freeing memory for tpc_stats\n"); + ath12k_wmi_free_tpc_stats_mem(ar); + } + spin_unlock_bh(&ar->data_lock); + return NULL; + } + + if (fixed_param->event_count == 0) { + if (ar->tpc_stats) { + ath12k_warn(ab, + "Invalid tpc memory present\n"); + spin_unlock_bh(&ar->data_lock); + return NULL; + } + ar->tpc_stats = + kzalloc(sizeof(struct wmi_tpc_stats_event), + GFP_ATOMIC); + } + + if (!ar->tpc_stats) { + ath12k_warn(ab, + "Failed to allocate memory for tpc stats\n"); + spin_unlock_bh(&ar->data_lock); + return NULL; + } + + tpc_stats = ar->tpc_stats; + + if (!(fixed_param->event_count == 0)) { + if (fixed_param->event_count != tpc_stats->event_count + 1) { + ath12k_warn(ab, + "Invalid tpc event received\n"); + spin_unlock_bh(&ar->data_lock); + return NULL; + } + } + tpc_stats->pdev_id = fixed_param->pdev_id; + tpc_stats->event_count = fixed_param->event_count; + tpc_stats->end_of_event = fixed_param->end_of_event; + ath12k_dbg(ab, ATH12K_DBG_WMI, + "tpc stats event_count %d\n", + tpc_stats->event_count); + + spin_unlock_bh(&ar->data_lock); + + return ar; +} + +static void ath12k_process_tpc_stats(struct ath12k_base *ab, + struct sk_buff *skb) +{ + int ret; + struct ath12k *ar; + struct wmi_tpc_stats_event *tpc_stats = NULL; + + rcu_read_lock(); + ar = ath12k_wmi_tpc_process_fixed_param(ab, skb->data, skb->len); + if (!ar) { + ath12k_warn(ab, "Failed to get ar for tpc event\n"); + goto exit; + } + + spin_lock_bh(&ar->data_lock); + tpc_stats = ar->tpc_stats; + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_tpc_stats_event_parser, + tpc_stats); + if (ret) { + if (tpc_stats) { + ath12k_warn(ab, "Freeing memory for tpc_stats\n"); + ath12k_wmi_free_tpc_stats_mem(ar); + } + spin_unlock_bh(&ar->data_lock); + ath12k_warn(ab, "failed to parse tpc_stats tlv: %d\n", ret); + goto exit; + } + + if (tpc_stats && tpc_stats->end_of_event) + complete(&ar->tpc_complete); + + spin_unlock_bh(&ar->data_lock); + +exit: + rcu_read_unlock(); +} + +int ath12k_wmi_pdev_get_tpc_table_cmdid(struct ath12k *ar) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_request_ctrl_path_stats_cmd_fixed_param *cmd; + struct sk_buff *skb; + struct wmi_tlv *tlv; + void *ptr; + u32 *pdev_ids, buf_len; + int ret; + + buf_len = sizeof(*cmd) + sizeof(u32) + TLV_HDR_SIZE; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, buf_len); + if (!skb) + return -ENOMEM; + cmd = (struct wmi_request_ctrl_path_stats_cmd_fixed_param *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_CTRL_PATH_CMD_FIXED_PARAM) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + + cmd->stats_id_mask = WMI_REQ_CTRL_PATH_PDEV_TX_STAT; + cmd->action = WMI_REQUEST_CTRL_PATH_STAT_GET; + cmd->subid = ar->tpc_stats_type; + + ptr = skb->data + sizeof(*cmd); + + tlv = ptr; + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_UINT32) | + FIELD_PREP(WMI_TLV_LEN, sizeof(u32)); + + ptr += TLV_HDR_SIZE; + + pdev_ids = ptr; + pdev_ids[0] = ar->pdev->pdev_id; + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_REQUEST_STATS_CTRL_PATH_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to submit WMI_REQUEST_STATS_CTRL_PATH_CMDID\n"); + dev_kfree_skb(skb); + return ret; + } + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI get TPC STATS sent on pdev %d\n", + ar->pdev->pdev_id); + + return ret; +} + +static void ath12k_wmi_diag_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + const struct wmi_tlv *tlv; + u16 tlv_tag, tlv_len; + u32 *dev_id; + u8 *data; + + tlv = (struct wmi_tlv *)skb->data; + tlv_tag = FIELD_GET(WMI_TLV_TAG, tlv->header); + tlv_len = FIELD_GET(WMI_TLV_LEN, tlv->header); + + if (tlv_tag == WMI_TAG_ARRAY_BYTE) { + data = skb->data + sizeof(struct wmi_tlv); + dev_id = (uint32_t *)data; + *dev_id = ab->hw_params->hw_rev + ATH12K_DIAG_HW_ID_OFFSET; + } else { + ath12k_warn(ab, "WMI Diag Event missing required tlv\n"); + return; + } + + ath12k_fwlog_write(ab, data, tlv_len); +} + +#define make_min_max(max,min) (u32_encode_bits(max, 0xf0) | u32_encode_bits(min, 0xf)) + +static void +ath12k_wmi_pdev_update_muedca_params_status_event(struct ath12k_base *ab, + struct sk_buff *skb) +{ + const void **tb; + const struct wmi_pdev_update_muedca_event *ev; + struct ieee80211_mu_edca_param_set *params; + struct ath12k *ar; + int ret; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, "failed to parse tlv: %d\n", ret); + return; + } + + ev = tb[WMI_TAG_MUEDCA_PARAMS_CONFIG_EVENT]; + if (!ev) { + ath12k_warn(ab, "failed to fetch pdev update muedca params ev"); + goto mem_free; + } + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "Update MU-EDCA parameters for pdev:%d\n", ev->pdev_id); + + rcu_read_lock(); + ar = ath12k_mac_get_ar_by_pdev_id(ab, ev->pdev_id); + if (!ar) { + ath12k_warn(ab, "MU-EDCA parameter change in invalid pdev %d\n", + ev->pdev_id); + goto unlock; + } + + params = kzalloc(sizeof(*params), GFP_ATOMIC); + if (!params) { + ath12k_warn(ab, + "Failed to allocate memory for updated MU-EDCA Parameters"); + goto unlock; + } + + params->ac_be.aifsn = ev->aifsn[WMI_AC_BE]; + params->ac_be.ecw_min_max = make_min_max(ev->ecwmax[WMI_AC_BE], + ev->ecwmin[WMI_AC_BE]); + params->ac_be.mu_edca_timer = ev->muedca_expiration_time[WMI_AC_BE]; + + params->ac_bk.aifsn = ev->aifsn[WMI_AC_BK]; + params->ac_bk.ecw_min_max = make_min_max(ev->ecwmax[WMI_AC_BK], + ev->ecwmin[WMI_AC_BK]); + params->ac_bk.mu_edca_timer = ev->muedca_expiration_time[WMI_AC_BK]; + + params->ac_vi.aifsn = ev->aifsn[WMI_AC_VI]; + params->ac_vi.ecw_min_max = make_min_max(ev->ecwmax[WMI_AC_VI], + ev->ecwmin[WMI_AC_VI]); + params->ac_vi.mu_edca_timer = ev->muedca_expiration_time[WMI_AC_VI]; + + params->ac_vo.aifsn = ev->aifsn[WMI_AC_VO]; + params->ac_vo.ecw_min_max = make_min_max(ev->ecwmax[WMI_AC_VO], + ev->ecwmin[WMI_AC_VO]); + params->ac_vo.mu_edca_timer = ev->muedca_expiration_time[WMI_AC_VO]; + + /* cfg80211_update_muedca_params_event(ar->ah->hw->wiphy, params, GFP_ATOMIC); */ + + kfree(params); + +unlock: + rcu_read_unlock(); +mem_free: + kfree(tb); +} + +static const char *ath12k_wmi_twt_add_dialog_event_status(u32 status) +{ + switch (status) { + case WMI_ADD_TWT_STATUS_OK: + return "ok"; + case WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED: + return "twt disabled"; + case WMI_ADD_TWT_STATUS_USED_DIALOG_ID: + return "dialog id in use"; + case WMI_ADD_TWT_STATUS_INVALID_PARAM: + return "invalid parameters"; + case WMI_ADD_TWT_STATUS_NOT_READY: + return "not ready"; + case WMI_ADD_TWT_STATUS_NO_RESOURCE: + return "resource unavailable"; + case WMI_ADD_TWT_STATUS_NO_ACK: + return "no ack"; + case WMI_ADD_TWT_STATUS_NO_RESPONSE: + return "no response"; + case WMI_ADD_TWT_STATUS_DENIED: + return "denied"; + case WMI_ADD_TWT_STATUS_UNKNOWN_ERROR: + fallthrough; + default: + return "unknown error"; + } +} + +int ath12k_wmi_dbglog_cfg(struct ath12k *ar, u32 param, u64 value) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_dbglog_config_cmd_fixed_param *cmd; + struct sk_buff *skb; + struct wmi_tlv *tlv; + u32 module_id_bitmap; + int ret, len; + + len = sizeof(*cmd) + TLV_HDR_SIZE + sizeof(module_id_bitmap); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + cmd = (struct wmi_dbglog_config_cmd_fixed_param *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_DEBUG_LOG_CONFIG_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + cmd->dbg_log_param = param; + + tlv = (struct wmi_tlv *)((u8 *) cmd + sizeof(*cmd)); + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_UINT32) | + FIELD_PREP(WMI_TLV_LEN, sizeof(u32)); + + switch (param) { + case WMI_DEBUG_LOG_PARAM_LOG_LEVEL: + case WMI_DEBUG_LOG_PARAM_VDEV_ENABLE: + case WMI_DEBUG_LOG_PARAM_VDEV_DISABLE: + case WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP: + cmd->value = value; + break; + case WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP: + case WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP: + cmd->value = value; + module_id_bitmap = value >> 32; + memcpy(tlv->value, &module_id_bitmap, sizeof(module_id_bitmap)); + break; + default: + dev_kfree_skb(skb); + return -EINVAL; + } + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_DBGLOG_CFG_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to send WMI_DBGLOG_CFG_CMDID\n"); + dev_kfree_skb(skb); + } + return ret; +} + +static void ath12k_wmi_twt_add_dialog_event(struct ath12k_base *ab, + struct sk_buff *skb) +{ + const void **tb; + const struct wmi_twt_add_dialog_event *ev; + int ret; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, + "failed to parse wmi twt add dialog status event tlv: %d\n", + ret); + return; + } + + ev = tb[WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT]; + if (!ev) { + ath12k_warn(ab, "failed to fetch twt add dialog wmi event\n"); + goto exit; + } + + if (ev->status) + ath12k_warn(ab, + "wmi add twt dialog event vdev %d dialog id %d status %s\n", + ev->vdev_id, ev->dialog_id, + ath12k_wmi_twt_add_dialog_event_status(ev->status)); + +exit: + kfree(tb); +} + +static void +ath12k_wmi_obss_color_collision_event(struct ath12k_base *ab, struct sk_buff *skb) +{ + const void **tb; + const struct wmi_obss_color_collision_event *ev; + struct ath12k_link_vif *arvif; + struct ath12k *ar; + int ret; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, "failed to parse tlv: %d\n", ret); + return; + } + + rcu_read_lock(); + ev = tb[WMI_TAG_OBSS_COLOR_COLLISION_EVT]; + if (!ev) { + ath12k_warn(ab, "failed to fetch obss color collision ev"); + goto unlock; + } + + arvif = ath12k_mac_get_arvif_by_vdev_id(ab, ev->vdev_id); + if (!arvif) + { + ath12k_warn(ab, "failed to find arvif with vedv id %d in obss_color_collision_event\n", + ev->vdev_id); + goto unlock; + } + + switch (ev->evt_type) { + case WMI_BSS_COLOR_COLLISION_DETECTION: + ar = arvif->ar; + arvif->obss_color_bitmap = ev->obss_color_bitmap; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "OBSS color collision detected vdev:%d, event:%d, bitmap:%08llx\n", + ev->vdev_id, ev->evt_type, ev->obss_color_bitmap); + rcu_read_unlock(); + ieee80211_queue_work(ar->ah->hw, &arvif->update_obss_color_notify_work); + goto exit; + case WMI_BSS_COLOR_COLLISION_DISABLE: + case WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY: + case WMI_BSS_COLOR_FREE_SLOT_AVAILABLE: + goto exit; + default: + ath12k_warn(ab, "received unknown obss color collision detetction event\n"); + goto exit; + } + +unlock: + rcu_read_unlock(); +exit: + kfree(tb); +} + +static void ath12k_process_ocac_complete_event(struct ath12k_base *ab, + struct sk_buff *skb) +{ + const void **tb; + const struct wmi_vdev_adfs_ocac_complete_event_fixed_param *ev; + struct ath12k *ar; + int ret; + + tb = ath12k_wmi_tlv_parse_alloc(ab, skb->data, skb->len, GFP_ATOMIC); + if (IS_ERR(tb)) { + ret = PTR_ERR(tb); + ath12k_warn(ab, "failed to parse tlv: %d\n", ret); + return; + } + + ev = tb[WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT]; + + if (!ev) { + ath12k_warn(ab, "failed to fetch ocac completed ev"); + kfree(tb); + return; + } + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "pdev dfs ocac complete event on pdev %d, chan freq %d," + "chan_width %d, status %d freq %d, freq1 %d, freq2 %d", + ev->vdev_id, ev->chan_freq, ev->chan_width, + ev->status, ev->center_freq, ev->center_freq1, + ev->center_freq2); + + ar = ath12k_mac_get_ar_by_vdev_id(ab, ev->vdev_id); + + if (!ar) { + ath12k_warn(ab, "OCAC complete event in invalid vdev %d\n", + ev->vdev_id); + goto exit; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI,"aDFS ocac complete event in vdev %d\n", + ev->vdev_id); + + if (ev->status) { + ath12k_mac_background_dfs_event(ar, ATH12K_BGDFS_ABORT); + } else { + memset(&ar->agile_chandef, 0, sizeof(struct cfg80211_chan_def)); + ar->agile_chandef.chan = NULL; + } +exit: + kfree(tb); +} + +static int ath12k_wmi_pdev_sscan_fft_bin_index_parse(struct ath12k_base *soc, + u16 tag, u16 len, + const void *ptr, void *data) +{ + if (tag != WMI_TAG_PDEV_SSCAN_FFT_BIN_INDEX) + return -EPROTO; + return 0; +} + +static int ath12k_wmi_pdev_sscan_per_detector_info_parse(struct ath12k_base *soc, + u16 tag, u16 len, + const void *ptr, void *data) +{ + if (tag != WMI_TAG_PDEV_SSCAN_PER_DETECTOR_INFO) + return -EPROTO; + + return 0; +} + +static int ath12k_wmi_tlv_sscan_fw_parse(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_pdev_sscan_fw_param_parse *parse = data; + int ret; + + switch (tag) { + + case WMI_TAG_PDEV_SSCAN_FW_CMD_FIXED_PARAM: + memcpy(&parse->fixed, ptr, + sizeof(struct ath12k_wmi_pdev_sscan_fw_cmd_fixed_param)); + parse->fixed.pdev_id = DP_HW2SW_MACID(parse->fixed.pdev_id); + break; + case WMI_TAG_ARRAY_STRUCT: + if (!parse->bin_entry_done) { + parse->bin = (struct ath12k_wmi_pdev_sscan_fft_bin_index *)ptr; + + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_pdev_sscan_fft_bin_index_parse, + parse); + + if (ret) { + ath12k_warn(ab, "failed to parse fft bin index %d\n", + ret); + return ret; + } + + parse->bin_entry_done = true; + } else if (!parse->det_info_entry_done) { + parse->det_info = (struct ath12k_wmi_pdev_sscan_per_detector_info *)ptr; + + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_pdev_sscan_per_detector_info_parse, + parse); + + if (ret) { + ath12k_warn(ab, "failed to parse detector info %d\n", + ret); + return ret; + } + parse->det_info_entry_done = true; + } + break; + case WMI_TAG_PDEV_SSCAN_CHAN_INFO: + memcpy(&parse->ch_info, ptr, + sizeof(struct ath12k_wmi_pdev_sscan_chan_info)); + parse->bin_entry_done = true; + break; + default: + break; + } + return 0; + +} + +static void +ath12k_wmi_pdev_sscan_fw_param_event(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct ath12k *ar; + struct wmi_pdev_sscan_fw_param_parse parse = { }; + struct wmi_pdev_sscan_fw_param_event param; + int ret; + u8 pdev_idx; + + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_tlv_sscan_fw_parse, + &parse); + + if (ret) { + ath12k_warn(ab, "failed to parse padev sscan fw tlv %d\n", ret); + return; + } + + param.fixed = parse.fixed; + param.bin = parse.bin; + param.ch_info = parse.ch_info; + param.det_info = parse.det_info; + + pdev_idx = param.fixed.pdev_id; + ar = ab->pdevs[pdev_idx].ar; + +#ifdef CONFIG_ATH12K_SPECTRAL + ar->spectral.ch_width = param.ch_info.operating_bw; +#endif + +} + +static int +ath12k_wmi_spectral_scan_bw_cap_parse(struct ath12k_base *soc, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_spectral_capabilities_parse *parse = data; + if (tag != WMI_TAG_SPECTRAL_SCAN_BW_CAPABILITIES) + return -EPROTO; + parse->num_bw_caps_entry++; + return 0; +} + +static int +ath12k_wmi_spectral_fft_size_cap_parse(struct ath12k_base *soc, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_spectral_capabilities_parse *parse = data; + if (tag != WMI_TAG_SPECTRAL_FFT_SIZE_CAPABILITIES) + return -EPROTO; + + parse->num_fft_size_caps_entry++; + return 0; +} + +static int +ath12k_wmi_tlv_spectral_cap_parse(struct ath12k_base *ab, + u16 tag, u16 len, + const void *ptr, void *data) +{ + struct wmi_spectral_capabilities_parse *parse = data; + int ret; + + if (tag == WMI_TAG_ARRAY_STRUCT) { + if (!parse->sscan_bw_caps_entry_done) { + parse->num_bw_caps_entry = 0; + parse->sscan_bw_caps = (struct ath12k_wmi_spectral_scan_bw_capabilities *)ptr; + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_spectral_scan_bw_cap_parse, + parse); + if (ret) { + ath12k_warn(ab, "failed to parse scan bw cap %d\n", + ret); + return ret; + } + parse->sscan_bw_caps_entry_done = true; + } else if (!parse->fft_size_caps_entry_done) { + parse->num_fft_size_caps_entry = 0; + parse->fft_size_caps = (struct ath12k_wmi_spectral_fft_size_capabilities *)ptr; + ret = ath12k_wmi_tlv_iter(ab, ptr, len, + ath12k_wmi_spectral_fft_size_cap_parse, + parse); + if (ret) { + ath12k_warn(ab, "failed to parse fft size cap %d\n", + ret); + return ret; + } + parse->fft_size_caps_entry_done = true; + } + } + return 0; +} + +static void +ath12k_wmi_spectral_capabilities_event(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct wmi_spectral_capabilities_parse parse = { }; + struct wmi_spectral_capabilities_event param; + struct ath12k *ar = NULL; + int ret, size; + u8 pdev_id, i; + struct ath12k_pdev *pdev; + + ret = ath12k_wmi_tlv_iter(ab, skb->data, skb->len, + ath12k_wmi_tlv_spectral_cap_parse, + &parse); + if (ret) { + ath12k_warn(ab, "failed to parse spectral capabilities tlv %d\n", ret); + return; + } + + param.sscan_bw_caps = parse.sscan_bw_caps; + param.fft_size_caps = parse.fft_size_caps; + param.num_bw_caps_entry = parse.num_bw_caps_entry; + param.num_fft_size_caps_entry = parse.num_fft_size_caps_entry; + + pdev_id = param.sscan_bw_caps->pdev_id; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (pdev && pdev->pdev_id == pdev_id) { + ar = pdev->ar; + break; + } + } + + if (!ar) { + ath12k_dbg(ab, ATH12K_DBG_WMI, + "ar is NULL for pdev_id %d use default spectral fft size 7", + pdev_id); + return; + } + size = sizeof(struct ath12k_wmi_spectral_fft_size_capabilities)* + param.num_fft_size_caps_entry; + +#ifdef CONFIG_ATH12K_SPECTRAL + ar->spectral.spectral_cap.fft_size_caps = kzalloc(size, GFP_ATOMIC); + if (!ar->spectral.spectral_cap.fft_size_caps) { + ath12k_warn(ab, "Failed to allocate memory"); + return; + } + memcpy(ar->spectral.spectral_cap.fft_size_caps, + param.fft_size_caps, size); + ar->spectral.spectral_cap.num_bw_caps_entry = param.num_bw_caps_entry; + ar->spectral.spectral_cap.num_fft_size_caps_entry = param.num_fft_size_caps_entry; +#endif + +} + +int ath12k_wmi_pdev_get_ani_level(struct ath12k *ar, u32 cmd_id, u8 pdev_id) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_pdev_get_ani_level_cmd *cmd; + struct sk_buff *skb; + int ret; + enum wmi_tlv_tag tlv_tag; + + tlv_tag = WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_get_ani_level_cmd *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(tlv_tag, sizeof(*cmd)); + cmd->pdev_id = cpu_to_le32(pdev_id); + + ret = ath12k_wmi_cmd_send(wmi, skb, cmd_id); + if (ret) { + ath12k_warn(ar->ab, "failed to send WMI_PDEV_GET_ANI_CONFIG cmd\n"); + dev_kfree_skb(skb); + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "WMI_PDEV_GET_ANI_CONFIG cmdid %d for pdev_id: %d\n", + cmd_id, pdev_id); + return ret; +} + +static void ath12k_wmi_event_ani_ofdm_level(struct ath12k_base *ab, + struct sk_buff *skb) +{ + const struct wmi_pdev_ani_event *ev; + struct ath12k *ar; + u8 pdev_id; + bool pdev_id_valid; + + ev = (struct wmi_pdev_ani_event *)skb->data; + + pdev_id_valid = WMI_ANI_EVENT_PDEV_ID_VALID & le32_to_cpu(ev->pdev_id_bitmap); + if (!pdev_id_valid) { + ath12k_warn(ab, "WMI_PDEV_ANI_OFDM_LEVEL_EVENT is not supported\n"); + return; + } + + pdev_id = le32_get_bits(ev->pdev_id_bitmap, WMI_ANI_EVENT_PDEV_ID); + ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); + if (!ar) { + ath12k_warn(ab, "Invalid pdev_id received for ANI OFDM level\n"); + return; + } + + ar->ani_ofdm_level = le32_to_cpu(ev->ani_level); + complete(&ar->ani_ofdm_event); +} + static void ath12k_wmi_op_rx(struct ath12k_base *ab, struct sk_buff *skb) { struct wmi_cmd_hdr *cmd_hdr; @@ -6380,11 +14403,26 @@ case WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID: ath12k_probe_resp_tx_status_event(ab, skb); break; + case WMI_TWT_ADD_DIALOG_EVENTID: + ath12k_wmi_twt_add_dialog_event(ab, skb); + break; + case WMI_PDEV_SSCAN_FW_PARAM_EVENTID: + ath12k_wmi_pdev_sscan_fw_param_event(ab, skb); + break; + case WMI_SPECTRAL_CAPABILITIES_EVENTID: + ath12k_wmi_spectral_capabilities_event(ab, skb); + break; + case WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID: + ath12k_offchan_tx_completion_event(ab, skb); + break; /* add Unsupported events here */ case WMI_TBTTOFFSET_EXT_UPDATE_EVENTID: case WMI_PEER_OPER_MODE_CHANGE_EVENTID: case WMI_TWT_ENABLE_EVENTID: case WMI_TWT_DISABLE_EVENTID: + case WMI_TWT_DEL_DIALOG_EVENTID: + case WMI_TWT_PAUSE_DIALOG_EVENTID: + case WMI_TWT_RESUME_DIALOG_EVENTID: case WMI_PDEV_DMA_RING_CFG_RSP_EVENTID: ath12k_dbg(ab, ATH12K_DBG_WMI, "ignoring unsupported event 0x%x\n", id); @@ -6395,6 +14433,58 @@ case WMI_VDEV_DELETE_RESP_EVENTID: ath12k_vdev_delete_resp_event(ab, skb); break; + case WMI_DIAG_EVENTID: + ath12k_wmi_diag_event(ab, skb); + break; + case WMI_DCS_INTERFERENCE_EVENTID: + ath12k_wmi_dcs_awgn_interference_event(ab, skb); + break; + case WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID: +#ifdef CONFIG_ATH12K_PKTLOG + ath12k_wmi_pktlog_decode_info(ab, skb); +#endif + break; + case WMI_CTRL_PATH_STATS_EVENTID: +#ifdef CONFIG_ATH12K_DEBUGFS + ath12k_wmi_ctrl_path_stats_event(ab, skb); +#endif + break; + case WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID: + ath12k_wmi_rssi_dbm_conversion_param_info(ab, skb); + break; + case WMI_MUEDCA_PARAMS_CONFIG_EVENTID: + ath12k_wmi_pdev_update_muedca_params_status_event(ab, skb); + break; + case WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID: + ath12k_wmi_obss_color_collision_event(ab, skb); + break; + case WMI_PDEV_UTF_EVENTID: + if (test_bit(ATH12K_FLAG_FTM_SEGMENTED, &ab->dev_flags)) + ath12k_wmi_tm_event_segmented(ab, id, skb); + else + ath12k_tm_wmi_event_unsegmented(ab, id, skb); + break; + case WMI_STATS_CTRL_PATH_EVENTID: + ath12k_process_tpc_stats(ab, skb); + break; + case WMI_MLO_SETUP_COMPLETE_EVENTID: + ath12k_wmi_event_mlo_setup_complete(ab, skb); + break; + case WMI_MLO_TEARDOWN_COMPLETE_EVENTID: + ath12k_wmi_event_teardown_complete(ab, skb); + break; + case WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID: + ath12k_wmi_event_mvr_response(ab, skb); + break; + case WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID: + ath12k_process_ocac_complete_event(ab, skb); + break; + case WMI_MGMT_RX_FW_CONSUMED_EVENTID: + ath12k_fw_consumed_mgmt_rx_event(ab, skb); + break; + case WMI_PDEV_ANI_OFDM_LEVEL_EVENTID: + ath12k_wmi_event_ani_ofdm_level(ab, skb); + break; /* TODO: Add remaining events */ default: ath12k_dbg(ab, ATH12K_DBG_WMI, "Unknown eventid: 0x%x\n", id); @@ -6433,6 +14523,7 @@ ab->wmi_ab.wmi_endpoint_id[pdev_idx] = conn_resp.eid; ab->wmi_ab.wmi[pdev_idx].eid = conn_resp.eid; ab->wmi_ab.max_msg_len[pdev_idx] = conn_resp.max_msg_len; + init_waitqueue_head(&ab->wmi_ab.wmi[pdev_idx].tx_ce_desc_wq); return 0; } @@ -6495,15 +14586,17 @@ return ret; } -int ath12k_wmi_simulate_radar(struct ath12k *ar) +int ath12k_wmi_simulate_radar(struct ath12k *ar, u32 radar_params) { - struct ath12k_vif *arvif; + struct ath12k_link_vif *arvif; + struct ath12k_vif *ahvif; u32 dfs_args[DFS_MAX_TEST_ARGS]; struct wmi_unit_test_cmd wmi_ut; bool arvif_found = false; list_for_each_entry(arvif, &ar->arvifs, list) { - if (arvif->is_started && arvif->vdev_type == WMI_VDEV_TYPE_AP) { + ahvif = arvif->ahvif; + if (arvif->is_started && ahvif->vdev_type == WMI_VDEV_TYPE_AP) { arvif_found = true; break; } @@ -6514,11 +14607,10 @@ dfs_args[DFS_TEST_CMDID] = 0; dfs_args[DFS_TEST_PDEV_ID] = ar->pdev->pdev_id; - /* Currently we could pass segment_id(b0 - b1), chirp(b2) - * freq offset (b3 - b10) to unit test. For simulation - * purpose this can be set to 0 which is valid. + /* Currently we pass segment_id(b0 - b1), chirp(b2) + * freq offset (b3 - b10), detector_id(b11 - b12) to unit test. */ - dfs_args[DFS_TEST_RADAR_PARAM] = 0; + dfs_args[DFS_TEST_RADAR_PARAM] = radar_params; wmi_ut.vdev_id = cpu_to_le32(arvif->vdev_id); wmi_ut.module_id = cpu_to_le32(DFS_UNIT_TEST_MODULE); @@ -6530,6 +14622,76 @@ return ath12k_wmi_send_unit_test_cmd(ar, wmi_ut, dfs_args); } +int ath12k_wmi_simulate_awgn(struct ath12k *ar, u32 chan_bw_interference_bitmap) +{ + struct ath12k_link_vif *arvif; + struct ath12k_vif *ahvif; + u32 awgn_args[WMI_AWGN_MAX_TEST_ARGS]; + struct wmi_unit_test_cmd wmi_ut; + bool arvif_found = false; + + if (!test_bit(WMI_TLV_SERVICE_DCS_AWGN_INT_SUPPORT, ar->ab->wmi_ab.svc_map)) { + ath12k_warn(ar->ab, "firmware doesn't support awgn interference, so can't simulate it\n"); + return -EOPNOTSUPP; + } + + list_for_each_entry(arvif, &ar->arvifs, list) { + ahvif = arvif->ahvif; + if (arvif->is_started && ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + arvif_found = true; + break; + } + } + + if (!arvif_found) + return -EINVAL; + + awgn_args[WMI_AWGN_TEST_AWGN_INT] = WMI_UNIT_TEST_AWGN_INTF_TYPE; + awgn_args[WMI_AWGN_TEST_BITMAP] = chan_bw_interference_bitmap; + + wmi_ut.vdev_id = arvif->vdev_id; + wmi_ut.module_id = WMI_AWGN_UNIT_TEST_MODULE; + wmi_ut.num_args = WMI_AWGN_MAX_TEST_ARGS; + wmi_ut.diag_token = WMI_AWGN_UNIT_TEST_TOKEN; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "Triggering AWGN Simulation, interference bitmap : 0x%x\n", + chan_bw_interference_bitmap); + + return ath12k_wmi_send_unit_test_cmd(ar, wmi_ut, awgn_args); +} + +int ath12k_wmi_pdev_m3_dump_enable(struct ath12k *ar, u32 enable) +{ + struct ath12k_link_vif *arvif; + u32 m3_args[WMI_M3_MAX_TEST_ARGS]; + struct wmi_unit_test_cmd wmi_ut; + bool arvif_found = false; + + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->is_started) { + arvif_found = true; + break; + } + } + + if (!arvif_found) + return -EINVAL; + + m3_args[WMI_M3_TEST_CMDID] = WMI_DBG_ENABLE_M3_SSR; + m3_args[WMI_M3_TEST_ENABLE] = enable; + + wmi_ut.vdev_id = arvif->vdev_id; + wmi_ut.module_id = WMI_M3_UNIT_TEST_MODULE; + wmi_ut.num_args = WMI_M3_MAX_TEST_ARGS; + wmi_ut.diag_token = WMI_M3_UNIT_TEST_TOKEN; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "%s M3 SSR dump\n", + enable ? "Enabling" : "Disabling"); + + return ath12k_wmi_send_unit_test_cmd(ar, wmi_ut, m3_args); +} + int ath12k_wmi_connect(struct ath12k_base *ab) { u32 i; @@ -6554,14 +14716,14 @@ } int ath12k_wmi_pdev_attach(struct ath12k_base *ab, - u8 pdev_id) + u8 pdev_idx) { struct ath12k_wmi_pdev *wmi_handle; - if (pdev_id >= ab->hw_params->max_radios) + if (pdev_idx >= ab->hw_params->max_radios) return -EINVAL; - wmi_handle = &ab->wmi_ab.wmi[pdev_id]; + wmi_handle = &ab->wmi_ab.wmi[pdev_idx]; wmi_handle->wmi_ab = &ab->wmi_ab; @@ -6602,5 +14764,732 @@ for (i = 0; i < ab->htc.wmi_ep_count; i++) ath12k_wmi_pdev_detach(ab, i); + clear_bit(ATH12K_FLAG_WMI_INIT_DONE, &ab->dev_flags); ath12k_wmi_free_dbring_caps(ab); } + +int ath12k_wmi_pdev_ap_ps_cmd_send(struct ath12k *ar, u8 pdev_id, + u32 param_value) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_pdev_ap_ps_cmd *cmd; + struct sk_buff *skb; + int ret; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_ap_ps_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, + WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + cmd->pdev_id = pdev_id; + cmd->param_value = param_value; + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to send ap ps enable/disable cmd %d\n",ret); + dev_kfree_skb(skb); + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi pdev ap ps set pdev id %d value %d\n", + pdev_id, param_value); + + return ret; +} + +int ath12k_wmi_mlo_setup(struct ath12k *ar, + struct wmi_mlo_setup_params *mlo_params) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_mlo_setup_cmd_fixed_param *cmd; + struct sk_buff *skb; + struct wmi_tlv *tlv; + u32 *plinks; + u32 num_links; + int i, ret, len; + + num_links = mlo_params->num_partner_links; + + len = sizeof(*cmd) + TLV_HDR_SIZE + (num_links * sizeof(u32)); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_mlo_setup_cmd_fixed_param *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_SETUP_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + cmd->mld_group_id = mlo_params->group_id; + cmd->pdev_id = ar->pdev->pdev_id; + + tlv = (struct wmi_tlv *)(skb->data + sizeof(*cmd)); + tlv->header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_UINT32) | + FIELD_PREP(WMI_TLV_LEN, num_links); + + plinks = (u32 *)tlv->value; + for (i = 0; i < num_links; i++) + plinks[i] = mlo_params->partner_link_id[i]; + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MLO_SETUP_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to submit WMI_MLO_SETUP_CMDID cmd\n"); + dev_kfree_skb(skb); + } + + return ret; +} + +int ath12k_wmi_mlo_ready(struct ath12k *ar) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_mlo_ready_cmd_fixed_param *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_mlo_ready_cmd_fixed_param *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_READY_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MLO_READY_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to submit WMI_MLO_READY_CMDID cmd\n"); + dev_kfree_skb(skb); + } + + return ret; +} + +int ath12k_wmi_mlo_teardown(struct ath12k *ar, bool umac_reset) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_mlo_teardown_fixed_param *cmd; + struct sk_buff *skb; + int ret, len; + + len = sizeof(*cmd); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_mlo_teardown_fixed_param *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_MLO_TEARDOWN_CMD) | + FIELD_PREP(WMI_TLV_LEN, sizeof(*cmd) - TLV_HDR_SIZE); + cmd->pdev_id = ar->pdev->pdev_id; + cmd->reason_code = WMI_MLO_TEARDOWN_SSR_REASON; + cmd->umac_reset = umac_reset; + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_MLO_TEARDOWN_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to submit WMI MLO teardown cmd\n"); + dev_kfree_skb(skb); + } + + ar->mlo_complete_event = false; + return ret; +} + +bool ath12k_wmi_is_mvr_supported(struct ath12k_base *ab) +{ + struct ath12k_wmi_base *wmi_ab = &ab->wmi_ab; + + return test_bit(WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART, + wmi_ab->svc_map) && + test_bit(WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART_RESPONSE_SUPPORT, + wmi_ab->svc_map); +} + +int ath12k_wmi_pdev_multiple_vdev_restart(struct ath12k *ar, + struct wmi_pdev_multiple_vdev_restart_req_arg *arg) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_pdev_multiple_vdev_restart_request_cmd *cmd; + struct ath12k_wmi_channel_params *chan; + struct wmi_tlv *tlv; + struct ath12k_wmi_channel_params *chan_device; + u32 num_vdev_ids; + __le32 *vdev_ids; + size_t vdev_ids_len; + struct sk_buff *skb; + void *ptr; + int ret, len, i; + bool device_params_present = false; + + if (WARN_ON(arg->vdev_ids.id_len > TARGET_NUM_VDEVS)) + return -EINVAL; + + num_vdev_ids = arg->vdev_ids.id_len; + vdev_ids_len = num_vdev_ids * sizeof(__le32); + + len = sizeof(*cmd) + TLV_HDR_SIZE + vdev_ids_len + + sizeof(*chan) + TLV_HDR_SIZE + TLV_HDR_SIZE + + TLV_HDR_SIZE; + + device_params_present = ath12k_wmi_check_device_present(arg->width_device, + arg->center_freq_device, + arg->channel.band_center_freq1); + + if (device_params_present) + len += TLV_HDR_SIZE + sizeof(*chan_device); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_pdev_multiple_vdev_restart_request_cmd *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, + sizeof(*cmd)); + cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); + cmd->num_vdevs = cpu_to_le32(arg->vdev_ids.id_len); + + if (device_params_present) { + arg->ru_punct_bitmap = + ath12k_wmi_set_ru_punc_bitmap_device(arg->channel.freq, arg->width_device, + arg->center_freq_device, + arg->ru_punct_bitmap); + } + cmd->puncture_20mhz_bitmap = cpu_to_le32(arg->ru_punct_bitmap); + + cmd->flags = cpu_to_le32(WMI_MVR_RESPONSE_SUPPORT_EXPECTED); + + ptr = skb->data + sizeof(*cmd); + tlv = (struct wmi_tlv *)ptr; + + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, vdev_ids_len); + vdev_ids = (__le32 *)tlv->value; + + for (i = 0; i < num_vdev_ids; i++) + vdev_ids[i] = cpu_to_le32(arg->vdev_ids.id[i]); + + ptr += TLV_HDR_SIZE + vdev_ids_len; + chan = (struct ath12k_wmi_channel_params *)ptr; + + ath12k_wmi_put_wmi_channel(chan, arg->channel); + + chan->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHANNEL, sizeof(*chan)); + ptr += sizeof(*chan); + + /* Zero length TLVs for phymode_list, preferred_tx_stream_list + * and preferred_rx_stream_list which are mandatory if any of + * the following TLVs are to be sent to target. + */ + tlv = ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); + ptr += sizeof(*tlv); + tlv = ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); + ptr += sizeof(*tlv); + tlv = ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_UINT32, 0); + ptr += sizeof(*tlv); + + if (device_params_present) { + tlv = ptr; + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, + sizeof(*chan_device)); + ptr += TLV_HDR_SIZE; + chan_device = ptr; + ath12k_wmi_set_wmi_channel_device(chan_device, &arg->channel, + arg->center_freq_device, + arg->width_device); + ptr += sizeof(*chan_device); + } + + ret = ath12k_wmi_cmd_send(wmi, skb, + WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID); + if (ret) { + ath12k_warn(ar->ab, "wmi failed to send mvr command (%d)\n", + ret); + dev_kfree_skb(skb); + return ret; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi mvr cmd sent num_vdevs %d freq %d\n", + num_vdev_ids, arg->channel.freq); + + return ret; +} + +int ath12k_wmi_vdev_adfs_ch_cfg_cmd_send(struct ath12k *ar, + u32 vdev_id, + struct cfg80211_chan_def *def) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_vdev_adfs_ch_cfg_cmd *cmd; + struct sk_buff *skb; + int ret = 0; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_vdev_adfs_ch_cfg_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_VDEV_ADFS_CH_CFG_CMD) | + FIELD_PREP(WMI_TLV_LEN, + sizeof(struct wmi_vdev_adfs_ch_cfg_cmd) - TLV_HDR_SIZE); + cmd->vdev_id = vdev_id; + + if (ar->ab->dfs_region == ATH12K_DFS_REG_ETSI) { + cmd->ocac_mode = WMI_ADFS_MODE_QUICK_OCAC; + cmd->min_duration_ms = cfg80211_chandef_dfs_cac_time(ar->ah->hw->wiphy, + def /*, + true, false */); + + + if (cmd->min_duration_ms == MIN_WEATHER_RADAR_CHAN_PRECAC_TIMEOUT) + cmd->max_duration_ms = MAX_WEATHER_RADAR_CHAN_PRECAC_TIMEOUT; + else + cmd->max_duration_ms = MAX_PRECAC_TIMEOUT; + } else if (ar->ab->dfs_region == ATH12K_DFS_REG_FCC) { + cmd->ocac_mode = WMI_ADFS_MODE_QUICK_RCAC; + cmd->min_duration_ms = MIN_RCAC_TIMEOUT; + cmd->max_duration_ms = MAX_RCAC_TIMEOUT; + } + + cmd->chan_freq = def->chan->center_freq; + cmd->chan_width = ath12k_wmi_get_host_chan_width(def->width); + cmd->center_freq1 = def->center_freq1; + cmd->center_freq2 = def->center_freq2; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "Send adfs channel cfg command for vdev id %d " + "mode as %d min duration %d chan_freq %d chan_width %d\n" + "center_freq1 %d center_freq2 %d", cmd->vdev_id, + cmd->ocac_mode, cmd->min_duration_ms, cmd->chan_freq, + cmd->chan_width, cmd->center_freq1, cmd->center_freq2); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_ADFS_CH_CFG_CMDID); + if (ret) { + ath12k_warn(ar->ab, + "failed to send WMI_VDEV_ADFS_CH_CFG_CMDID\n"); + dev_kfree_skb(skb); + } + + return ret; +} + +int ath12k_wmi_vdev_adfs_ocac_abort_cmd_send(struct ath12k *ar, u32 vdev_id) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_vdev_adfs_ocac_abort_cmd *cmd; + struct sk_buff *skb; + int ret = 0; + + if (!ar->agile_chandef.chan) { + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "Currently, agile CAC is not active on any channel." + "Ignore abort"); + return ret; + } + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, sizeof(*cmd)); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_vdev_adfs_ocac_abort_cmd *)skb->data; + cmd->tlv_header = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD) | + FIELD_PREP(WMI_TLV_LEN, + sizeof(struct wmi_vdev_adfs_ocac_abort_cmd) - TLV_HDR_SIZE); + + cmd->vdev_id = vdev_id; + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_VDEV_ADFS_OCAC_ABORT_CMDID); + + if (ret) { + ath12k_warn(ar->ab, + "failed to send WMI_VDEV_ADFS_ABORT_CMD\n"); + dev_kfree_skb(skb); + return ret; + } + return ret; +} + +#ifdef CONFIG_ATH12K_SAWF + +int ath12k_wmi_svc_config_send(struct ath12k *ar, struct ath12k_sawf_svc_params *param) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_sawf_svc_cfg_cmd_fixed_param *cmd; + struct sk_buff *skb; + int len, ret; + + len = sizeof(*cmd); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_sawf_svc_cfg_cmd_fixed_param *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SAWF_SERVICE_CLASS_CFG_CMD_FIXED_PARAM, + sizeof(*cmd)); + + /* Valid svc_id advertized to user is in the range of 1 to 128. + * However, firmware is maintaining svc_id range from 0 to 127. + * So sending svc_id - 1, to address this firmware limitation. + */ + cmd->svc_class_id = cpu_to_le32(param->svc_id - 1); + cmd->min_thruput_kbps = cpu_to_le32(param->min_throughput_rate); + cmd->max_thruput_kbps = cpu_to_le32(param->max_throughput_rate); + cmd->burst_size_bytes = cpu_to_le32(param->burst_size); + cmd->svc_interval_ms = cpu_to_le32(param->service_interval); + cmd->delay_bound_ms = cpu_to_le32(param->delay_bound); + cmd->time_to_live_ms = cpu_to_le32(param->msdu_ttl); + cmd->priority = cpu_to_le32(param->priority); + cmd->tid = cpu_to_le32(param->tid); + cmd->msdu_loss_rate_ppm = cpu_to_le32(param->msdu_rate_loss); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "Service class configure: svc_id: %u, min_throughput: %u, " + "max_throughput: %u, burst_size: %u, svc_interval: %u, " + "delay_bound: %u, TTL: %u, priority: %u, tid: %u, msdu_loss_rate: %u", + cmd->svc_class_id, cmd->min_thruput_kbps, cmd->max_thruput_kbps, + cmd->burst_size_bytes, cmd->svc_interval_ms, cmd->delay_bound_ms, + cmd->time_to_live_ms, cmd->priority, cmd->tid, + cmd->msdu_loss_rate_ppm); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_SAWF_SERVICE_CLASS_CFG_CMDID); + if (ret) { + ath12k_err(ar->ab, + "failed to config/reconfig the service class param\n"); + dev_kfree_skb(skb); + } + + return ret; +} + +int ath12k_wmi_svc_send_disable(struct ath12k *ar, u32 svc_id) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_sawf_svc_disable_cmd_fixed_param *cmd; + struct sk_buff *skb; + int len, ret; + + len = sizeof(*cmd); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_sawf_svc_disable_cmd_fixed_param *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_SAWF_SERVICE_CLASS_DISABLE_CMD_FIXED_PARAM, + sizeof(*cmd)); + + /* Valid svc_id advertized to user is in the range of 1 to 128. + * However, firmware is maintaining svc_id range from 0 to 127. + * So sending svc_id - 1, to address this firmware limitation. + */ + cmd->svc_class_id = cpu_to_le32(svc_id - 1); + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "Service class disable: svc_id: %u", + cmd->svc_class_id); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_SAWF_SERVICE_CLASS_DISABLE_CMDID); + if (ret) { + ath12k_err(ar->ab, + "failed to disable service class: %u\n", svc_id); + dev_kfree_skb(skb); + } + + return ret; +} + +#endif /* CONFIG_ATH12K_SAWF */ + +static void ath12k_wmi_put_peer_list(struct ath12k_base *ab, + struct wmi_chan_width_peer_list *peer_list, + struct wmi_chan_width_peer_arg *peer_arg, + u32 num_peers, int start_idx) +{ + struct wmi_chan_width_peer_list *itr; + struct wmi_chan_width_peer_arg *arg_itr; + int i; + u32 host_chan_width; + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi peer channel width switch command peer list\n"); + + for (i = 0; i < num_peers; i++) { + itr = &peer_list[i]; + arg_itr = &peer_arg[start_idx + i]; + + itr->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_CHAN_WIDTH_PEER_LIST, + sizeof(*itr)); + ether_addr_copy(itr->mac_addr.addr, arg_itr->mac_addr.addr); + host_chan_width = ath12k_wmi_get_host_chan_switch_width(arg_itr->chan_width); + itr->chan_width = cpu_to_le32(host_chan_width); + itr->puncture_20mhz_bitmap = cpu_to_le32(arg_itr->puncture_20mhz_bitmap); + + ath12k_dbg(ab, ATH12K_DBG_WMI, + " (%u) width %u addr %pM punct_bitmap 0x%x host chan_width: %d\n", + i + 1, arg_itr->chan_width, arg_itr->mac_addr.addr, + arg_itr->puncture_20mhz_bitmap, host_chan_width); + } +} + +static int ath12k_wmi_peer_chan_width_switch(struct ath12k *ar, + struct wmi_peer_chan_width_switch_arg *arg) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct wmi_peer_chan_width_switch_req_cmd *cmd; + struct wmi_chan_width_peer_list *peer_list; + struct wmi_tlv *tlv; + u32 num_peers; + size_t peer_list_len; + struct sk_buff *skb; + void *ptr; + int ret, len; + + num_peers = arg->num_peers; + + if (WARN_ON(num_peers > ab->chwidth_num_peer_caps)) + return -EINVAL; + + peer_list_len = num_peers * sizeof(*peer_list); + + len = sizeof(*cmd) + TLV_HDR_SIZE + peer_list_len; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) + return -ENOMEM; + + cmd = (struct wmi_peer_chan_width_switch_req_cmd *)skb->data; + cmd->tlv_header = ath12k_wmi_tlv_cmd_hdr(WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, + sizeof(*cmd)); + cmd->num_peers = cpu_to_le32(num_peers); + cmd->vdev_var = cpu_to_le32(arg->vdev_var); + + ptr = skb->data + sizeof(*cmd); + tlv = (struct wmi_tlv *)ptr; + + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, peer_list_len); + peer_list = (struct wmi_chan_width_peer_list *)tlv->value; + + ath12k_wmi_put_peer_list(ab, peer_list, arg->peer_arg, num_peers, + arg->start_idx); + + ptr += peer_list_len; + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_CHAN_WIDTH_SWITCH_CMDID); + if (ret) { + ath12k_warn(ab, "wmi failed to send peer chan width switch command (%d)\n", + ret); + dev_kfree_skb(skb); + return ret; + } + + ath12k_dbg(ab, ATH12K_DBG_WMI, + "wmi peer chan width switch cmd sent num_peers %d \n", + num_peers); + + return ret; +} + +void ath12k_wmi_set_peers_chan_width(struct ath12k_link_vif *arvif, + struct wmi_chan_width_peer_arg *peer_arg, + int num, u8 start_idx) +{ + struct ath12k *ar = arvif->ar; + struct wmi_chan_width_peer_arg *arg; + int i, err; + + for (i = 0; i < num; i++) { + arg = &peer_arg[start_idx + i]; + + /* for bandwidth upgrade phymode should be set already. Safe to + * to directly set channel width + */ + err = ath12k_wmi_set_peer_param(ar, arg->mac_addr.addr, + arvif->vdev_id, WMI_PEER_CHWIDTH, + arg->chan_width); + if (err) { + ath12k_warn(ar->ab, "failed to update STA %pM peer bw %d: %d\n", + arg->mac_addr.addr, arg->chan_width, err); + continue; + } + + /* for bandwidth downgrade, phymode should be set after setting + * channel width + */ + if (!arg->is_upgrade) { + err = ath12k_wmi_set_peer_param(ar, arg->mac_addr.addr, + arvif->vdev_id, WMI_PEER_PHYMODE, + arg->peer_phymode); + if (err) + ath12k_warn(ar->ab, "failed to update STA %pM peer phymode %d: %d\n", + arg->mac_addr.addr, arg->peer_phymode, err); + } + } +} + +void ath12k_wmi_peer_chan_width_switch_work(struct work_struct *work) +{ + struct ath12k_link_vif *arvif = container_of(work, struct ath12k_link_vif, + peer_ch_width_switch_work); + struct ath12k *ar = arvif->ar; + struct ath12k_peer_ch_width_switch_data *data; + struct wmi_peer_chan_width_switch_arg arg; + struct wmi_chan_width_peer_arg *peer_arg; + unsigned long time_left = 0; + int count_left, curr_count, max_count_per_cmd = ar->ab->chwidth_num_peer_caps; + int cmd_num = 0, ret, i; + + mutex_lock(&ar->conf_mutex); + + /* possible that the worker got scheduled after complete was triggered. In + * this case we don't wait for timeout */ + if (arvif->peer_ch_width_switch_data->count == arvif->num_stations) + goto send_cmd; + + mutex_unlock(&ar->conf_mutex); + + time_left = wait_for_completion_timeout(&arvif->peer_ch_width_switch_send, + ATH12K_PEER_CH_WIDTH_SWITCH_TIMEOUT_HZ); + if (time_left == 0) { + /* Even though timeout occured, we would send the command for the peers + * for which we received sta rc update event, hence not returning */ + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "timed out waiting for all peers in peer channel width switch\n"); + } + + mutex_lock(&ar->conf_mutex); + +send_cmd: + + data = arvif->peer_ch_width_switch_data; + + spin_lock_bh(&ar->data_lock); + arg.vdev_var = arvif->vdev_id; + spin_unlock_bh(&ar->data_lock); + + arg.vdev_var |= ATH12K_PEER_VALID_VDEV_ID | ATH12K_PEER_PUNCT_BITMAP_VALID; + arg.peer_arg = data->peer_arg; + + count_left = data->count; + + while (count_left > 0) { + if (count_left <= max_count_per_cmd) + curr_count = count_left; + else + curr_count = max_count_per_cmd; + + count_left -= curr_count; + + cmd_num++; + + arg.num_peers = curr_count; + arg.start_idx = (cmd_num - 1) * max_count_per_cmd; + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, + "wmi peer channel width switch command num %u\n", + cmd_num); + + ret = ath12k_wmi_peer_chan_width_switch(ar, &arg); + if (ret) { + /* fallback */ + ath12k_wmi_set_peers_chan_width(arvif, arg.peer_arg, arg.num_peers, + arg.start_idx); + } + } + + for (i = 0; i < data->count; i++) { + peer_arg = &data->peer_arg[i]; + + /* for bandwidth upgrade phymode is set from worker scheduler */ + if (peer_arg->is_upgrade) + continue; + + /* for bandwidth downgrade phymode needs to be set */ + ret = ath12k_wmi_set_peer_param(ar, peer_arg->mac_addr.addr, + arvif->vdev_id, WMI_PEER_PHYMODE, + peer_arg->peer_phymode); + if (ret) + ath12k_warn(ar->ab, "failed to update STA %pM peer phymode %d: %d\n", + peer_arg->mac_addr.addr, peer_arg->peer_phymode, ret); + } + + kfree(arvif->peer_ch_width_switch_data); + arvif->peer_ch_width_switch_data = NULL; + mutex_unlock(&ar->conf_mutex); +} + +int ath12k_wmi_set_latency(struct ath12k *ar, struct ath12k_latency_params *params) +{ + struct sk_buff *skb; + struct wmi_tlv *tlv; + struct ath12k_wmi_pdev *wmi; + struct wmi_peer_tid_latency_cmd *cmd; + struct wmi_tid_latency_params *tid_lat; + void *data; + int len, ret, num_peer = 1, sawf_ul_param = 1; + u8 dl_enable, ul_enable; + + wmi = ar->wmi; + len = sizeof(*cmd) + TLV_HDR_SIZE + (num_peer * sizeof(*tid_lat)); + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, len); + if (!skb) { + ath12k_warn(ar->ab, "Memory is not available\n"); + return -ENOMEM; + } + + if (params->direction == WMI_LATENCY_DIR_UL) { + ul_enable = 1; + dl_enable = 0; + } else if (params->direction == WMI_LATENCY_DIR_DL) { + ul_enable = 0; + dl_enable = 1; + } else { + ath12k_warn(ar->ab, "Direct link is not supported\n"); + dev_kfree_skb(skb); + return -EINVAL; + } + + data = skb->data; + cmd = data; + cmd->tlv_header = ath12k_wmi_tlv_hdr(WMI_TAG_PEER_TID_LATENCY_CONFIG_FIXED_PARAM, + (sizeof(*cmd) - TLV_HDR_SIZE)); + cmd->pdev_id = cpu_to_le32(ar->pdev->pdev_id); + + data += sizeof(*cmd); + tlv = data; + len = sizeof(*tid_lat) * num_peer; + + tlv->header = ath12k_wmi_tlv_hdr(WMI_TAG_ARRAY_STRUCT, len); + + data += TLV_HDR_SIZE; + tid_lat = data; + + tid_lat->tlv_header = ath12k_wmi_tlv_hdr(WMI_TAG_TID_LATENCY_INFO, + (sizeof(*tid_lat) - TLV_HDR_SIZE)); + + tid_lat->service_interval = cpu_to_le32(params->service_interval); + tid_lat->burst_size_diff = cpu_to_le32(params->burst_size); + tid_lat->max_latency = cpu_to_le32(params->delay_bound); + tid_lat->min_tput = cpu_to_le32(params->min_data_rate); + + ether_addr_copy(tid_lat->destmac.addr, params->peer_mac); + + tid_lat->latency_tid_info = + le32_encode_bits(params->user_priority, WMI_LATENCY_TID_INFO_SCS_TID_NUM) | + le32_encode_bits(params->ac, WMI_LATENCY_TID_INFO_SCS_AC) | + le32_encode_bits(dl_enable, WMI_LATENCY_TID_INFO_SCS_DL_EN) | + le32_encode_bits(ul_enable, WMI_LATENCY_TID_INFO_SCS_UL_EN) | + le32_encode_bits(params->req_type, WMI_LATENCY_TID_INFO_SCS_BURST_SZ_SUM) | + le32_encode_bits(sawf_ul_param, WMI_LATENCY_TID_INFO_SCS_SAWF_UL_PARAM); + + ret = ath12k_wmi_cmd_send(wmi, skb, WMI_PEER_TID_LATENCY_CONFIG_CMDID); + if (ret) { + ath12k_warn(ar->ab, "failed to submit WMI_PEER_TID_LATENCY_CONFIG_CMDID cmd %d\n", + ret); + dev_kfree_skb(skb); + } + return ret; +} diff -ruw linux-6.4/drivers/net/wireless/ath/ath12k/wmi.h linux-6.4-fbx/drivers/net/wireless/ath/ath12k/wmi.h --- linux-6.4/drivers/net/wireless/ath/ath12k/wmi.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/wmi.h 2024-03-18 14:40:14.867741770 +0100 @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: BSD-3-Clause-Clear */ /* * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef ATH12K_WMI_H @@ -24,6 +24,12 @@ struct ath12k_base; struct ath12k; +struct ath12k_fw_stats; +struct ath12k_reg_tpc_power_info; +struct ath12k_sawf_svc_params; +struct ath12k_latency_params; + +#define PSOC_HOST_MAX_NUM_SS (8) /* There is no signed version of __le32, so for a temporary solution come * up with our own version. The idea is from fs/ntfs/endian.h. @@ -72,6 +78,31 @@ u8 value[]; } __packed; +struct wmi_vdev_ch_power_info { + u32 tlv_header; + u32 chan_cfreq; /* Channel center frequency (MHz) */ + /* Unit: dBm, either PSD/EIRP power for this frequency or + * incremental for non-PSD BW + */ + u32 tx_power; +} __packed; + +struct wmi_vdev_set_tpc_power_cmd { + u32 tlv_header; + u32 vdev_id; + u32 psd_power; /* Value: 0 or 1, is PSD power or not */ + u32 eirp_power; /* Maximum EIRP power (dBm units), valid only if power is PSD */ + u32 power_type_6ghz; /* Type: WMI_6GHZ_REG_TYPE, used for halphy CTL lookup */ + /* This fixed_param TLV is followed by the below TLVs: + * num_pwr_levels of wmi_vdev_ch_power_info + * For non-psd power, the power values are for 20, 40, and till + * BSS BW power levels. + * The num_pwr_levels will be checked by sw how many elements present + * in the variable-length array. + */ +} __packed; + + #define WMI_TLV_LEN GENMASK(15, 0) #define WMI_TLV_TAG GENMASK(31, 16) #define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header) @@ -175,6 +206,58 @@ #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 #define WMI_BA_MODE_BUFFER_SIZE_256 3 +#define WMI_BA_MODE_BUFFER_SIZE_1024 6 + +#define ATH12K_VALIDATE_PARSED_DATA_POINTER(parsed_bytes, data, \ + remaining_len) \ +do { \ + if ((parsed_bytes) < 0 || (parsed_bytes > remaining_len)) { \ + ath12k_err(ab, "TLV extraction failed\n"); \ + return -EINVAL; \ + } \ + (data) += (parsed_bytes); \ + (remaining_len) -= (parsed_bytes); \ +} while (0) + +/** + * is_field_present_in_tlv() - Check whether a given field is present + * in a given TLV + * @ptlv: Pointer to start of the TLV + * @field_name: name of the field in the TLV structure + * @tlv_len: Length of the TLV + * + * Return: true if the field is present within the TLV, + * else false + */ +#define is_field_present_in_tlv(ptlv, field_name, tlv_len) \ + (offsetof(typeof(*(ptlv)), field_name) < (tlv_len) ? \ + true : false) + +/** + * get_field_value_in_tlv() - Get the value of a given field in a given TLV + * @ptlv: Pointer to start of the TLV + * @field_name: name of the field in the TLV structure + * @tlv_len: Length of the TLV + * + * Return: Value of the given field if the offset of the field with in the TLV + * structure is less than the TLV length, else 0. + */ +#define get_field_value_in_tlv(ptlv, field_name, tlv_len) \ + (offsetof(typeof(*(ptlv)), field_name) < (tlv_len) ? \ + (ptlv)->field_name : 0) + +/** + * get_field_pointer_in_tlv() - Get the address of a given field in a given TLV + * @ptlv: Pointer to start of the TLV + * @field_name: name of the field in the TLV structure + * @tlv_len: Length of the TLV + * + * Return: Address of the given field if the offset of the field with in the + * TLV structure is less than the TLV length, else NULL. + */ +#define get_field_pointer_in_tlv(ptlv, field_name, tlv_len) \ + (offsetof(typeof(*(ptlv)), field_name) < (tlv_len) ? \ + &(ptlv)->field_name : NULL) /* HW mode config type replicated from FW header * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. @@ -227,6 +310,22 @@ WMI_HOST_WLAN_2G_5G_CAP = 3, }; +/* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. + * Used only for HE auto rate mode. + */ +enum { + /* HE LTF related configuration */ + WMI_HE_AUTORATE_LTF_1X = BIT(0), + WMI_HE_AUTORATE_LTF_2X = BIT(1), + WMI_HE_AUTORATE_LTF_4X = BIT(2), + + /* HE GI related configuration */ + WMI_AUTORATE_400NS_GI = BIT(8), + WMI_AUTORATE_800NS_GI = BIT(9), + WMI_AUTORATE_1600NS_GI = BIT(10), + WMI_AUTORATE_3200NS_GI = BIT(11), +}; + enum wmi_cmd_group { /* 0 to 2 are reserved */ WMI_GRP_START = 0x3, @@ -292,6 +391,9 @@ WMI_GRP_TWT = 0x3e, WMI_GRP_MOTION_DET = 0x3f, WMI_GRP_SPATIAL_REUSE = 0x40, + WMI_GRP_LATENCY = 0x47, + WMI_GRP_MLO = 0x48, + WMI_GRP_SAWF = 0x49, }; #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) @@ -361,6 +463,17 @@ WMI_PDEV_DMA_RING_CFG_REQ_CMDID, WMI_PDEV_HE_TB_ACTION_FRM_CMDID, WMI_PDEV_PKTLOG_FILTER_CMDID, + WMI_PDEV_SET_RAP_CONFIG_CMDID, + WMI_PDEV_DSM_FILTER_CMDID, + WMI_PDEV_FRAME_INJECT_CMDID, + WMI_PDEV_TBTT_OFFSET_SYNC_CMDID, + WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, + WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, + WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, + WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, + WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, + WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, + WMI_PDEV_GET_TPC_STATS_CMDID, WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), WMI_VDEV_DELETE_CMDID, WMI_VDEV_START_REQUEST_CMDID, @@ -388,6 +501,38 @@ WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, + /** WMI commands related to dbg arp stats */ + WMI_VDEV_SET_ARP_STAT_CMDID, + WMI_VDEV_GET_ARP_STAT_CMDID, + /** get tx power for the current vdev */ + WMI_VDEV_GET_TX_POWER_CMDID, + /* limit STA offchannel activity */ + WMI_VDEV_LIMIT_OFFCHAN_CMDID, + /** To set custom software retries per-AC for vdev */ + WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID, + /** To set chainmask configuration for vdev */ + WMI_VDEV_CHAINMASK_CONFIG_CMDID, + WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID, + /* request LTE-Coex info */ + WMI_VDEV_GET_MWS_COEX_INFO_CMDID, + /** delete all peer (excluding bss peer) */ + WMI_VDEV_DELETE_ALL_PEER_CMDID, + /* To set bss max idle time related parameters */ + WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID, + /** Indicates FW to trigger Audio sync */ + WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID, + /** Gives Qtimer value to FW */ + WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID, + /** Preferred channel list for each vdev */ + WMI_VDEV_SET_PCL_CMDID, + /** VDEV_GET_BIG_DATA_CMD IS DEPRECATED - DO NOT USE */ + WMI_VDEV_GET_BIG_DATA_CMDID, + /** Get per vdev BIG DATA stats phase 2 */ + WMI_VDEV_GET_BIG_DATA_P2_CMDID, + /** set TPC PSD/non-PSD power */ + WMI_VDEV_SET_TPC_POWER_CMDID, + WMI_VDEV_IGMP_OFFLOAD_CMDID, + WMI_VDEV_SET_INTRA_BSS_CMDID, WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), WMI_PEER_DELETE_CMDID, WMI_PEER_FLUSH_TIDS_CMDID, @@ -410,6 +555,16 @@ WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, WMI_PEER_SET_RX_BLOCKSIZE_CMDID, WMI_PEER_ANTDIV_INFO_REQ_CMDID, + WMI_PEER_RESERVED0_CMDID, + WMI_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMDID, + WMI_PEER_TID_CONFIGURATIONS_CMDID, + WMI_PEER_CFR_CAPTURE_CMDID, + WMI_PEER_CHAN_WIDTH_SWITCH_CMDID, + WMI_PEER_TX_PN_REQUEST_CMDID, + WMI_PEER_UNMAP_RESPONSE_CMDID, + WMI_PEER_CONFIG_VLAN_CMDID, + WMI_PEER_CONFIG_PPE_DS_CMDID, + WMI_PEER_SET_INTRA_BSS_CMDID, WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), WMI_PDEV_SEND_BCN_CMDID, WMI_BCN_TMPL_CMDID, @@ -424,6 +579,9 @@ WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, WMI_FILS_DISCOVERY_TMPL_CMDID, + WMI_QOS_NULL_FRAME_TX_SEND_CMDID, + /** WMI CMD to receive the management filter criteria from the host for RX REO */ + WMI_MGMT_RX_REO_FILTER_CONFIGURATION_CMDID, WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), WMI_ADDBA_SEND_CMDID, WMI_ADDBA_STATUS_CMDID, @@ -519,6 +677,11 @@ WMI_REQUEST_RCPI_CMDID, WMI_REQUEST_PEER_STATS_INFO_CMDID, WMI_REQUEST_RADIO_CHAN_STATS_CMDID, + WMI_REQUEST_WLM_STATS_CMDID, + WMI_REQUEST_CTRL_PATH_STATS_CMDID, + WMI_REQUEST_UNIFIED_LL_GET_STA_CMDID, + WMI_REQUEST_THERMAL_STATS_CMDID, + WMI_REQUEST_STATS_CTRL_PATH_CMDID, WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, @@ -669,6 +832,22 @@ WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, + /** WMI commands specific to Tid level Latency config **/ + /** VDEV Latency Config command */ + WMI_VDEV_TID_LATENCY_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LATENCY), + /** TID Latency Request command */ + WMI_PEER_TID_LATENCY_CONFIG_CMDID, + WMI_MLO_LINK_SET_ACTIVE_CMDID = WMI_TLV_CMD(WMI_GRP_MLO), + WMI_MLO_SETUP_CMDID, + WMI_MLO_READY_CMDID, + WMI_MLO_TEARDOWN_CMDID, + WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID, + /** Service Aware WiFi (SAWF) **/ + /** configure or reconfigure the parameters for a service class **/ + WMI_SAWF_SERVICE_CLASS_CFG_CMDID = WMI_TLV_CMD(WMI_GRP_SAWF), + /** disable a service class **/ + WMI_SAWF_SERVICE_CLASS_DISABLE_CMDID, + }; enum wmi_tlv_event_id { @@ -676,6 +855,9 @@ WMI_READY_EVENTID, WMI_SERVICE_AVAILABLE_EVENTID, WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), + WMI_PDEV_SSCAN_FW_PARAM_EVENTID, + WMI_SSCAN_EVT_MESSAGE_EVENTID, + WMI_SPECTRAL_CAPABILITIES_EVENTID, WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), WMI_CHAN_INFO_EVENTID, WMI_PHYERR_EVENTID, @@ -710,6 +892,15 @@ WMI_PDEV_RAP_INFO_EVENTID, WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, WMI_SERVICE_READY_EXT2_EVENTID, + WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID, + WMI_PDEV_GET_TPC_STATS_EVENTID, + WMI_PDEV_GET_DPD_STATUS_EVENTID, + WMI_PDEV_GET_HALPHY_CAL_STATUS_EVENTID, + WMI_PDEV_SET_HALPHY_CAL_BMAP_EVENTID, + WMI_PDEV_AOA_PHASEDELTA_EVENTID, + WMI_PDEV_FIPS_EXTEND_EVENTID, + WMI_PDEV_PKTLOG_DECODE_INFO_EVENTID, + WMI_PDEV_RSSI_DBM_CONVERSION_PARAMS_INFO_EVENTID, WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), WMI_VDEV_STOPPED_EVENTID, WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, @@ -751,6 +942,9 @@ WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, WMI_HOST_FILS_DISCOVERY_EVENTID, + WMI_HOST_FILS_V2_DISCOVERY_EVENTID, + WMI_QOS_NULL_FRAME_TX_COMPLETION_EVENTID, + WMI_MGMT_RX_FW_CONSUMED_EVENTID, WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), WMI_TX_ADDBA_COMPLETE_EVENTID, WMI_BA_RSP_SSN_EVENTID, @@ -781,6 +975,9 @@ WMI_UPDATE_RCPI_EVENTID, WMI_PEER_STATS_INFO_EVENTID, WMI_RADIO_CHAN_STATS_EVENTID, + WMI_WLM_STATS_EVENTID, + WMI_CTRL_PATH_STATS_EVENTID, + WMI_STATS_CTRL_PATH_EVENTID, WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), WMI_NLO_SCAN_COMPLETE_EVENTID, WMI_APFIND_EVENTID, @@ -817,6 +1014,7 @@ WMI_READ_DATA_FROM_FLASH_EVENTID, WMI_REPORT_RX_AGGR_FAILURE_EVENTID, WMI_PKGID_EVENTID, + WMI_MUEDCA_PARAMS_CONFIG_EVENTID = 0x1d01e, WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), WMI_UPLOADH_EVENTID, WMI_CAPTUREH_EVENTID, @@ -849,6 +1047,8 @@ WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), WMI_SAP_OFL_DEL_STA_EVENTID, + WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = + WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, WMI_DCC_GET_STATS_RESP_EVENTID, @@ -878,6 +1078,9 @@ WMI_TWT_DEL_DIALOG_EVENTID, WMI_TWT_PAUSE_DIALOG_EVENTID, WMI_TWT_RESUME_DIALOG_EVENTID, + WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MLO), + WMI_MLO_SETUP_COMPLETE_EVENTID, + WMI_MLO_TEARDOWN_COMPLETE_EVENTID, }; enum wmi_tlv_pdev_param { @@ -1024,6 +1227,12 @@ WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, WMI_PDEV_PARAM_MESH_MCAST_ENABLE, + WMI_PDEV_PARAM_SET_CONG_CTRL_MAX_MSDUS = 0xa6, + WMI_PDEV_PARAM_SUB_CHANNEL_MARKING = 0xb0, + WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, + WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, + WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, + WMI_PDEV_PARAM_MPD_USERPD_SSR = 0xce, }; enum wmi_tlv_vdev_param { @@ -1136,13 +1345,25 @@ WMI_VDEV_PARAM_HE_RANGE_EXT, WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, + WMI_VDEV_PARAM_HE_LTF = 0x74, WMI_VDEV_PARAM_BA_MODE = 0x7e, + WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, + WMI_VDEV_PARAM_UL_FIXED_RATE, WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, WMI_VDEV_PARAM_PROTOTYPE = 0x8000, WMI_VDEV_PARAM_BSS_COLOR, WMI_VDEV_PARAM_SET_HEMU_MODE, WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, + WMI_VDEV_PARAM_OBSSPD, + WMI_VDEV_PARAM_SET_EHT_MU_MODE, + WMI_VDEV_PARAM_EHT_LTF, + WMI_VDEV_PARAM_UL_EHT_LTF, + WMI_VDEV_PARAM_EHT_DCM, + WMI_VDEV_PARAM_EHT_RANGE_EXT, + WMI_VDEV_PARAM_NON_DATA_EHT_RANGE_EXT, + WMI_VDEV_PARAM_FIXED_PUNCTURE_PATTERN, + WMI_VDEV_PARAM_EHTOPS_0_31, }; enum wmi_tlv_peer_flags { @@ -1175,6 +1396,7 @@ WMI_TAG_ARRAY_BYTE, WMI_TAG_ARRAY_STRUCT, WMI_TAG_ARRAY_FIXED_STRUCT, + WMI_TAG_ARRAY_INT16, WMI_TAG_LAST_ARRAY_ENUM = 31, WMI_TAG_SERVICE_READY_EVENT, WMI_TAG_HAL_REG_CAPABILITIES, @@ -1920,10 +2142,76 @@ /* TODO add all the missing cmds */ WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, + WMI_TAG_MUEDCA_PARAMS_CONFIG_EVENT = 0x32a, + WMI_TAG_SERVICE_READY_EXT2_EVENT = 0x334, WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, + WMI_TAG_MULTIPLE_VDEV_RESTART_RESPONSE_EVENT = 0x365, WMI_TAG_MAC_PHY_CAPABILITIES_EXT = 0x36F, + WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, + WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, + WMI_TAG_PDEV_SSCAN_FW_CMD_FIXED_PARAM = 0x37f, + WMI_TAG_PDEV_SSCAN_FFT_BIN_INDEX, + WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, + WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, + WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, + WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, + /* TODO add all the missing cmds */ + WMI_CTRL_PATH_STATS_CMD_FIXED_PARAM = + WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD + 4, + WMI_CTRL_PATH_STATS_EV_FIXED_PARAM, + WMI_CTRL_PATH_PDEV_STATS, WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, + WMI_TAG_VDEV_SET_TPC_POWER_CMD = 0x3B5, + WMI_TAG_VDEV_CH_POWER_INFO, + WMI_TAG_PEER_TID_LATENCY_CONFIG_FIXED_PARAM = 0x3B9, + WMI_TAG_TID_LATENCY_INFO, + WMI_CTRL_PATH_CAL_STATS = 0x3BC, + WMI_CTRL_PATH_BTCOEX_STATS = 0x3FD, + WMI_CTRL_PATH_AWGN_STATS = 0x3F9, + WMI_TAG_EHT_RATE_SET = 0x3C4, + WMI_TAG_DCS_AWGN_INT_TYPE = 0x3C5, + WMI_TAG_MLO_TX_SEND_PARAMS, + WMI_TAG_MLO_PARTNER_LINK_PARAMS, + WMI_TAG_MLO_PARTNER_LINK_PARAMS_PEER_ASSOC, + WMI_TAG_MLO_SETUP_CMD, + WMI_TAG_MLO_SETUP_COMPLETE_EVENT, + WMI_TAG_MLO_READY_CMD, + WMI_TAG_MLO_TEARDOWN_CMD, + WMI_TAG_MLO_TEARDOWN_COMPLETE, + WMI_TAG_MLO_PEER_ASSOC_PARAMS = 0x3D0, + WMI_TAG_MLO_MGMT_RX_REO_PARAMS = 0x3D2, + WMI_TAG_MLO_MGMT_RX_FW_CONSUMED_HDR = 0x3D3, + WMI_TAG_MLO_MGMT_RX_REO_FILTER_CFG_CMD = 0x3D4, + WMI_TAG_MLO_PEER_CREATE_PARAMS = 0x3D5, + WMI_TAG_MLO_VDEV_START_PARAMS = 0x3D6, + WMI_TAG_MLO_VDEV_CREATE_PARAMS = 0x3D7, + WMI_TAG_VDEV_SET_INTRA_BSS_PARAMS = 0x3EE, + WMI_TAG_PEER_SET_INTRA_BSS_PARAMS, + WMI_TAG_PDEV_PKTLOG_DECODE_INFO = 0x414, + WMI_TAG_TPC_STATS_GET_CMD = 0x38B, + WMI_TAG_TPC_STATS_EVENT_FIXED_PARAM, + WMI_TAG_TPC_STATS_CONFIG_EVENT, + WMI_TAG_TPC_STATS_REG_PWR_ALLOWED, + WMI_TAG_TPC_STATS_RATES_ARRAY, + WMI_TAG_TPC_STATS_CTL_PWR_TABLE_EVENT, + WMI_TAG_BCN_TMPL_ML_PARAMS_CMD = 0x3E6, + WMI_TAG_PEER_CONFIG_PPEDS_ROUTING = 0x3EA, + WMI_TAG_SAWF_SERVICE_CLASS_CFG_CMD_FIXED_PARAM = 0x40A, + WMI_TAG_SAWF_SERVICE_CLASS_DISABLE_CMD_FIXED_PARAM = 0x40B, + WMI_TAG_SPECTRAL_SCAN_BW_CAPABILITIES = 0x415, + WMI_TAG_SPECTRAL_FFT_SIZE_CAPABILITIES, + WMI_TAG_PDEV_SSCAN_CHAN_INFO = 0X417, + WMI_TAG_PDEV_SSCAN_PER_DETECTOR_INFO, + WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO_FIXED_PARAM = 0x427, + WMI_TAG_RSSI_DBM_CONVERSION_PARAMS_INFO, + WMI_TAG_RSSI_DBM_CONVERSION_TEMP_OFFSET_INFO, + WMI_TAG_BCN_TMPL_ML_INFO_CMD = 0x436, + WMI_TAG_MLO_MGMT_RX_CU_PARAMS = 0x439, + WMI_TAG_CTRL_PATH_CMD_FIXED_PARAM = 0x442, + WMI_TAG_CTRL_PATH_EVENT_FIXED_PARAM, + WMI_TAG_PDEV_DFS_RADAR_FLAGS = 0x4b4, + WMI_TAG_PRB_RESP_TMPL_ML_INFO_CMD = 0x460, WMI_TAG_MAX }; @@ -2147,8 +2435,28 @@ WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, WMI_TLV_SERVICE_EXT2_MSG = 220, - - WMI_MAX_EXT_SERVICE + WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART_RESPONSE_SUPPORT = 235, + WMI_TLV_SERVICE_5_9GHZ_SUPPORT = 247, + WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, + + WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, + WMI_MAX_EXT_SERVICE = 256, + + WMI_TLV_SERVICE_EXT_TPC_REG_SUPPORT = 280, + WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, + WMI_TLV_SERVICE_DCS_AWGN_INT_SUPPORT = 286, + WMI_TLV_SERVICE_BE = 289, + WMI_TLV_SERVICE_SAWF_LEVEL0 = 311, + WMI_TLV_SERVICE_PKTLOG_DECODE_INFO_SUPPORT = 320, + WMI_TLV_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, + WMI_TLV_SERVICE_RADAR_FLAGS_SUPPORT = 390, + WMI_TLV_SERVICE_SW_PROG_DFS_SUPPORT = 395, + WMI_MAX_EXT2_SERVICE, +}; + +enum wmi_unit_test_cmdid { + /* TODO: Add the remaining cmd ids if needed */ + WMI_DBG_ENABLE_M3_SSR = 36, }; enum { @@ -2196,6 +2504,14 @@ WMI_VDEV_PREAMBLE_SHORT = 2, }; +/** 6GHZ params **/ +/* Control to enable/disable beacon tx in non-HT duplicate */ +#define WMI_VDEV_6GHZ_BITMAP_NON_HT_DUPLICATE_BEACON BIT(0) +/* Control to enable/disable broadcast probe response tx in non-HT duplicate */ +#define WMI_VDEV_6GHZ_BITMAP_NON_HT_DUPLICATE_BCAST_PROBE_RSP BIT(1) +/* Control to enable/disable FILS discovery frame tx in non-HT duplicate */ +#define WMI_VDEV_6GHZ_BITMAP_NON_HT_DUPLICATE_FD_FRAME BIT(2) + enum wmi_peer_smps_state { WMI_PEER_SMPS_PS_NONE = 0, WMI_PEER_SMPS_STATIC = 1, @@ -2207,6 +2523,8 @@ WMI_PEER_CHWIDTH_40MHZ = 1, WMI_PEER_CHWIDTH_80MHZ = 2, WMI_PEER_CHWIDTH_160MHZ = 3, + WMI_PEER_CHWIDTH_320MHZ = 4, + WMI_PEER_CHWIDTH_MAX = 9, }; enum wmi_beacon_gen_mode { @@ -2217,11 +2535,31 @@ enum wmi_direct_buffer_module { WMI_DIRECT_BUF_SPECTRAL = 0, WMI_DIRECT_BUF_CFR = 1, + WMI_CONFIG_MODULE_CV_UPLOAD = 2, /* keep it last */ WMI_DIRECT_BUF_MAX }; +/* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext + * event + * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss + * of 80MHz + * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss + * of 80MHz + * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz + * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max + * nss of 80MHz + */ + +enum wmi_nss_ratio { + WMI_NSS_RATIO_1BY2_NSS = 0x0, + WMI_NSS_RATIO_3BY4_NSS = 0x1, + WMI_NSS_RATIO_1_NSS = 0x2, + WMI_NSS_RATIO_2_NSS = 0x3, +}; + + struct ath12k_wmi_pdev_band_arg { u32 pdev_id; u32 start_freq; @@ -2234,6 +2572,7 @@ u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; }; +#define PSOC_HOST_MAX_MAC_SIZE (2) #define PSOC_HOST_MAX_PHY_SIZE (3) #define ATH12K_11B_SUPPORT BIT(0) #define ATH12K_11G_SUPPORT BIT(1) @@ -2255,6 +2594,77 @@ u32 high_5ghz_chan; }; +#define WMI_MAX_EHTCAP_MAC_SIZE 2 +#define WMI_MAX_EHTCAP_PHY_SIZE 3 +#define WMI_MAX_EHTCAP_RATE_SET 3 + +enum { + WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001, + WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002, + WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004, + WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008, + WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010, +}; + +/* HW mode MLO capability flags + * WMI_HOST_MLO_CAP_FLAG_NONE: Do not support MLO for the specific HW mode + * WMI_HOST_MLO_CAP_FLAG_NON_STR_IN_DBS: Support STR MLO when DBS for the specific HW mode + * WMI_HOST_MLO_CAP_FLAG_STR_IN_DBS: Support Non-STR MLO when DBS for the specific HW mode + * WMI_HOST_MLO_CAP_FLAG_NON_STR_IN_SBS: Support STR MLO when SBS for the specific HW mode + * WMI_HOST_MLO_CAP_FLAG_STR_IN_SBS: Support Non-STR MLO when SBS for the specific HW mode + * WMI_HOST_MLO_CAP_FLAG_STR: Support STR for the specific HW mode + * WMI_HOST_MLO_CAP_FLAG_EMLSR: Support eMLSR mode + */ +#define WMI_HOST_MLO_CAP_FLAG_NONE 0x0 +#define WMI_HOST_MLO_CAP_FLAG_NON_STR_IN_DBS 0x1 +#define WMI_HOST_MLO_CAP_FLAG_STR_IN_DBS 0x2 +#define WMI_HOST_MLO_CAP_FLAG_NON_STR_IN_SBS 0x4 +#define WMI_HOST_MLO_CAP_FLAG_STR_IN_SBS 0x8 +#define WMI_HOST_MLO_CAP_FLAG_STR 0x10 +#define WMI_HOST_MLO_CAP_FLAG_EMLSR 0x20 + +/* + * 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid) + * 1 – index for <= 80MHz bw (only 3 bytes are valid and other is reserved) + * 2 – index for == 160Mhz bw (only 3 bytes are valid and other is reserved) + * 3 – index for == 320Mhz bw (only 3 bytes are valid and other is reserved) + */ +#define WMI_MAX_EHT_SUPP_MCS_2G_SIZE 2 +#define WMI_MAX_EHT_SUPP_MCS_5G_SIZE 4 + +#define WMI_EHTCAP_TXRX_MCS_NSS_IDX_80 0 +#define WMI_EHTCAP_TXRX_MCS_NSS_IDX_160 1 +#define WMI_EHTCAP_TXRX_MCS_NSS_IDX_320 2 + +#define WMI_MCS_NSS_MAP_0_7 GENMASK(3, 0) +#define WMI_MCS_NSS_MAP_8_9 GENMASK(7, 4) +#define WMI_MCS_NSS_MAP_10_11 GENMASK(11, 8) +#define WMI_MCS_NSS_MAP_12_13 GENMASK(15, 12) + +/* + * 0 – index indicated EHT-MCS map for 20Mhz only sta (4 bytes valid) + * 1 – index for <= 80MHz bw (only 3 bytes are valid and other is reserved) + * 2 – index for == 160Mhz bw (only 3 bytes are valid and other is reserved) + * 3 – index for == 320Mhz bw (only 3 bytes are valid and other is reserved) + */ +#define WMI_MAX_EHT_SUPP_MCS_2G_SIZE 2 +#define WMI_MAX_EHT_SUPP_MCS_5G_SIZE 4 + +struct ath12k_service_ext2_param { + u32 reg_db_version; + u32 hw_min_max_tx_power_2g; + u32 hw_min_max_tx_power_5g; + u32 chwidth_num_peer_caps; + u32 ru_punct_supp_bw; + u32 max_user_per_ppdu_ofdma; + u32 max_user_per_ppdu_mumimo; + u32 target_cap_flags; + u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; + u32 max_num_linkview_peers; + u32 max_msduq_per_tid; + u32 default_msduq_per_tid; +}; + #define WMI_HOST_MAX_PDEV 3 struct ath12k_wmi_host_mem_chunk_params { @@ -2333,6 +2743,12 @@ u32 sched_params; u32 twt_ap_pdev_count; u32 twt_ap_sta_count; + bool is_reg_cc_ext_event_supported; + u32 ema_max_vap_cnt; + u32 ema_max_profile_period; + u8 dp_peer_meta_data_ver; + bool sawf; + bool is_full_bw_nol_feature_supported; }; struct ath12k_wmi_init_cmd_arg { @@ -2367,6 +2783,34 @@ __le32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; } __packed; +struct ath12k_ppe_threshold { + u32 numss_m1; + u32 ru_bit_mask; + u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS]; +}; + +struct ath12k_chainmask_caps { + u32 supported_caps; + u32 chainmask; +}; + +struct ath12k_chainmask_table { + u32 table_id; + u32 num_valid_chainmasks; + struct ath12k_chainmask_caps *cap_list; +}; + +#define ATH12K_MAX_CHAINMASK_TABLES 5 + +struct wmi_ppe_threshold { + u32 numss_m1; /** NSS - 1*/ + union { + u32 ru_count; + u32 ru_mask; + } __packed; + u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; +} __packed; + #define HW_BD_INFO_SIZE 5 struct ath12k_wmi_abi_version_params { @@ -2385,6 +2829,14 @@ } __packed; #define WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT 4 +#define WMI_RSRC_CFG_HOST_SVC_FLAG_REO_QREF_SUPPORT_BIT 12 +#define WMI_RSRC_CFG_HOST_SVC_FLAG_FULL_BW_NOL_SUPPORT_BIT 14 +#define WMI_RSRC_CFG_FLAGS2_RX_PEER_METADATA_VERSION GENMASK(5,4) +#define WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET BIT(9) +#define WMI_RSRC_CFG_FLAGS2_INTRABSS_MEC_WDS_LEARNING_DISABLE BIT(15) +#define WMI_RSRC_CFG_FLAG1_THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT BIT(25) +#define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) +#define WMI_RSRC_CFG_FLAGS2_SAWF_CONFIG_ENABLE_SET BIT(13) struct ath12k_wmi_resource_config_params { __le32 tlv_header; @@ -2516,6 +2968,9 @@ __le32 num_chainmask_tables; } __packed; +#define WMI_HW_MODE_INFO0_CONFIG_TYPE GENMASK(26, 0) +#define WMI_HW_MODE_INFO0_MLO_CAP_FLAG GENMASK(31, 27) + struct ath12k_wmi_hw_mode_cap_params { __le32 tlv_header; __le32 hw_mode_id; @@ -2523,11 +2978,30 @@ __le32 hw_mode_config_type; } __packed; +struct wmi_mac_phy_chainmask_combo { + u32 chainmask_table_id; + u32 num_valid_chainmask; +} __packed; + +struct wmi_mac_phy_chainmask_caps { + u32 tlv_header; + u32 supported_flags; + u32 chainmask; +} __packed; + + #define WMI_MAX_HECAP_PHY_SIZE (3) +#define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0) +#define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \ + FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val) +#define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) +#define WMI_NSS_RATIO_INFO_GET(_val) \ + FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val) struct ath12k_wmi_mac_phy_caps_params { __le32 hw_mode_id; - __le32 pdev_id; + __le16 pdev_id; + __le16 hw_link_id; __le32 phy_id; __le32 supported_flags; __le32 supported_bands; @@ -2557,6 +3031,12 @@ __le32 he_cap_info_2g_ext; __le32 he_cap_info_5g_ext; __le32 he_cap_info_internal; + __le32 wireless_modes; + __le32 low_2ghz_chan_freq; + __le32 high_2ghz_chan_freq; + __le32 low_5ghz_chan_freq; + __le32 high_5ghz_chan_freq; + __le32 nss_ratio; } __packed; struct ath12k_wmi_hal_reg_caps_ext_params { @@ -2577,6 +3057,108 @@ __le32 num_phy; } __packed; +struct wmi_service_ready_ext2_event { + u32 reg_db_version; + u32 hw_min_max_tx_power_2g; + u32 hw_min_max_tx_power_5g; + u32 chwidth_num_peer_caps; + u32 ru_punct_supp_bw; + u32 max_user_per_ppdu_ofdma; + u32 max_user_per_ppdu_mumimo; + u32 target_cap_flags; + u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; + u32 max_num_linkview_peers; + u32 max_num_msduq_supported_per_tid; + u32 default_num_msduq_supported_per_tid; +} __packed; + +enum wmi_spectral_scaling_formula_id { + NO_SCALING = 0, + AGC_GAIN_RSSI_CORR_BASED = 1, +}; + +struct wmi_spectral_bin_scaling { + u32 pdev_id; + enum wmi_spectral_scaling_formula_id formula_id; + u32 low_level_offset; + u32 high_level_offset; + u32 rssi_thr; + u32 default_agc_max_gain; +} __packed; + +enum wmi_eht_mcs_support { + WMI_EHT_MCS_SUPPORT_0_9 = 0, + WMI_EHT_MCS_SUPPORT_0_11 = 1, + WMI_EHT_MCS_SUPPORT_0_13 = 2, + WMI_EHT_MCS_NOT_SUPPORTED = 3, +}; + +#define EML_INFO_EMLSR_SUPPORT BIT(0) +#define EML_INFO_EMLSR_PADDING_DELAY GENMASK(3, 1) +#define EML_INFO_EMLSR_TRANSITION_DELAY GENMASK(6, 4) +#define EML_INFO_EMLMR_SUPPORT BIT(7) +#define EML_INFO_EMLMR_PADDING_DELAY GENMASK(10, 8) +#define EML_INFO_TRANSITION_TIMEOUT GENMASK(14, 11) + +enum wmi_mld_cap_tid_to_link_map { + WMI_MLD_MAP_TID_TO_LINK_NONE, + WMI_MLD_MAP_EACH_TID_TO_SAME_OR_DIFF_LINK_SET, + WMI_MLD_MAP_ALL_TID_TO_SAME_LINK_SET, +}; + +#define MLD_INFO_MAX_SIMULTANEOUS_LINK GENMASK(3, 0) +#define MLD_INFO_SRS_SUPPORT BIT(4) +#define MLD_INFO_TID_TO_LINK_MAP_SUPPORT GENMASK(6, 5) +#define MLD_INFO_FREQ_SEPARATION_STR GENMASK(11, 7) +#define MLD_INFO_AAR_SUPPORT BIT(12) + +struct wmi_mac_phy_caps_ext { + u32 hw_mode_id; + union { + struct { + u32 pdev_id:16, + hw_link_id:16; + } wmi_pdev_to_link_map; + u32 pdev_id; + } u; + u32 phy_id; + u32 wireless_modes_ext; + u32 eht_cap_mac_info_2G[WMI_MAX_EHTCAP_MAC_SIZE]; + u32 eht_cap_mac_info_5G[WMI_MAX_EHTCAP_MAC_SIZE]; + u32 rsvd0[2]; + u32 eht_cap_phy_info_2G[WMI_MAX_EHTCAP_PHY_SIZE]; + u32 eht_cap_phy_info_5G[WMI_MAX_EHTCAP_PHY_SIZE]; + struct wmi_ppe_threshold eht_ppet2G; + struct wmi_ppe_threshold eht_ppet5G; + u32 eht_cap_info_internal; + u32 eht_supp_mcs_ext_2G[WMI_MAX_EHT_SUPP_MCS_2G_SIZE]; + u32 eht_supp_mcs_ext_5G[WMI_MAX_EHT_SUPP_MCS_5G_SIZE]; + union { + struct { + u32 emlsr_support:1, + emlsr_padding_delay:3, + emlsr_transition_delay:3, + emlmr_support:1, + emlmr_delay:3, + transition_timeout:4, + reserved: 17; + }; + u32 eml_capability; + } eml_cap_u; + union { + struct { + u32 max_num_simultaneous_links:4, + srs_support:1, + tid_to_link_negotiation_support:2, + freq_separation_str:5, + aar_support:1, + reserved2: 19; + }; + u32 mld_capability; + } mld_cap_u; +} __packed; + + /* 2 word representation of MAC addr */ struct ath12k_wmi_mac_addr_params { u8 addr[ETH_ALEN]; @@ -2622,7 +3204,10 @@ u8 rx; } chains[NUM_NL80211_BANDS]; u32 pdev_id; + u32 mbssid_flags; + u32 mbssid_tx_vdev_id; u8 if_stats_id; + u8 mld_addr[ETH_ALEN]; }; #define ATH12K_MAX_VDEV_STATS_ID 0x30 @@ -2636,6 +3221,9 @@ struct ath12k_wmi_mac_addr_params vdev_macaddr; __le32 num_cfg_txrx_streams; __le32 pdev_id; + __le32 mbssid_flags; + __le32 mbssid_tx_vdev_id; + __le32 vdev_stats_id_valid; __le32 vdev_stats_id; } __packed; @@ -2646,19 +3234,66 @@ u32 supported_rx_streams; } __packed; +/* 2 word representation of MAC addr */ +struct wmi_mac_addr { + union { + u8 addr[6]; + struct { + u32 word0; + u32 word1; + } __packed; + } __packed; +} __packed; + +struct wmi_vdev_create_mlo_params { + u32 tlv_header; + struct wmi_mac_addr mld_macaddr; +} __packed; + +#define ATH12K_WMI_FLAG_MLO_ENABLED BIT(0) +#define ATH12K_WMI_FLAG_MLO_ASSOC_LINK BIT(1) +#define ATH12K_WMI_FLAG_MLO_PRIMARY_UMAC BIT(2) +#define ATH12K_WMI_FLAG_MLO_LOGICAL_LINK_IDX_VALID BIT(3) +#define ATH12K_WMI_FLAG_MLO_PEER_ID_VALID BIT(4) +#define ATH12K_WMI_FLAG_MLO_MCAST_VDEV BIT(5) +#define ATH12K_WMI_FLAG_MLO_EMLSR_SUPPORT BIT(6) +#define ATH12K_WMI_FLAG_MLO_FORCED_INACTIVE BIT(7) +#define ATH12K_WMI_FLAG_MLO_LINK_ADD BIT(8) + +struct wmi_vdev_start_mlo_params { + u32 tlv_header; + u32 flags; +} __packed; + +struct wmi_partner_link_info { + u32 tlv_header; + u32 vdev_id; + u32 hw_link_id; + struct wmi_mac_addr vdev_addr; +} __packed; + struct wmi_vdev_delete_cmd { __le32 tlv_header; __le32 vdev_id; } __packed; +struct vdev_up_params { + __le32 vdev_id; + __le16 aid; + const u8 *bssid; + __le32 profile_idx; + __le32 profile_count; + u8 *tx_bssid; +} __packed; + struct wmi_vdev_up_cmd { __le32 tlv_header; __le32 vdev_id; __le32 vdev_assoc_id; struct ath12k_wmi_mac_addr_params vdev_bssid; - struct ath12k_wmi_mac_addr_params trans_bssid; + struct ath12k_wmi_mac_addr_params tx_vdev_bssid; __le32 profile_idx; - __le32 profile_num; + __le32 profile_count; } __packed; struct wmi_vdev_stop_cmd { @@ -2674,6 +3309,7 @@ #define WMI_VDEV_START_HIDDEN_SSID BIT(0) #define WMI_VDEV_START_PMF_ENABLED BIT(1) #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) +#define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4) #define ATH12K_WMI_SSID_LEN 32 @@ -2682,7 +3318,7 @@ u8 ssid[ATH12K_WMI_SSID_LEN]; } __packed; -#define ATH12K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ) +#define ATH12K_VDEV_SETUP_TIMEOUT_HZ (10 * HZ) struct wmi_vdev_start_request_cmd { __le32 tlv_header; @@ -2701,6 +3337,11 @@ __le32 he_ops; __le32 cac_duration_ms; __le32 regdomain; + __le32 min_data_rate; + __le32 mbssid_flags; + __le32 mbssid_tx_vdev_id; + __le32 eht_ops; + __le32 ru_punct_bitmap; } __packed; #define MGMT_TX_DL_FRM_LEN 64 @@ -2729,6 +3370,25 @@ u8 reg_class_id; }; +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +struct wmi_peer_config_ppeds_cmd { + __le32 tlv_header; + struct wmi_mac_addr peer_macaddr; + __le32 ppe_routing_enable; + __le32 service_code; + __le32 priority_valid; + __le32 src_info; + __le32 vdev_id; +}; + +enum wmi_ppeds_routing_type { + WMI_PPE_ROUTING_DISABLED = 0, + WMI_AST_USE_PPE_ENABLED = 1, + WMI_AST_USE_PPE_DISABLED = 2, + WMI_PPE_ROUTING_TYPE_MAX, +}; +#endif + enum wmi_phy_mode { MODE_11A = 0, MODE_11G = 1, /* 11b/g Mode */ @@ -2754,12 +3414,20 @@ MODE_11AX_HE20_2G = 21, MODE_11AX_HE40_2G = 22, MODE_11AX_HE80_2G = 23, - MODE_UNKNOWN = 24, - MODE_MAX = 24 + MODE_11BE_EHT20 = 24, + MODE_11BE_EHT40 = 25, + MODE_11BE_EHT80 = 26, + MODE_11BE_EHT80_80 = 27, + MODE_11BE_EHT160 = 28, + MODE_11BE_EHT160_160 = 29, + MODE_11BE_EHT320 = 30, + MODE_11BE_EHT20_2G = 31, + MODE_11BE_EHT40_2G = 32, + MODE_UNKNOWN = 33, + MODE_MAX = 33 }; -struct wmi_vdev_start_req_arg { - u32 vdev_id; +struct wmi_channel_arg { u32 freq; u32 band_center_freq1; u32 band_center_freq2; @@ -2776,6 +3444,113 @@ u32 max_reg_power; u32 max_antenna_gain; enum wmi_phy_mode mode; +}; + +static inline const char *ath12k_wmi_phymode_str(enum wmi_phy_mode mode) +{ + switch (mode) { + case MODE_11A: + return "11a"; + case MODE_11G: + return "11g"; + case MODE_11B: + return "11b"; + case MODE_11GONLY: + return "11gonly"; + case MODE_11NA_HT20: + return "11na-ht20"; + case MODE_11NG_HT20: + return "11ng-ht20"; + case MODE_11NA_HT40: + return "11na-ht40"; + case MODE_11NG_HT40: + return "11ng-ht40"; + case MODE_11AC_VHT20: + return "11ac-vht20"; + case MODE_11AC_VHT40: + return "11ac-vht40"; + case MODE_11AC_VHT80: + return "11ac-vht80"; + case MODE_11AC_VHT160: + return "11ac-vht160"; + case MODE_11AC_VHT80_80: + return "11ac-vht80+80"; + case MODE_11AC_VHT20_2G: + return "11ac-vht20-2g"; + case MODE_11AC_VHT40_2G: + return "11ac-vht40-2g"; + case MODE_11AC_VHT80_2G: + return "11ac-vht80-2g"; + case MODE_11AX_HE20: + return "11ax-he20"; + case MODE_11AX_HE40: + return "11ax-he40"; + case MODE_11AX_HE80: + return "11ax-he80"; + case MODE_11AX_HE80_80: + return "11ax-he80+80"; + case MODE_11AX_HE160: + return "11ax-he160"; + case MODE_11AX_HE20_2G: + return "11ax-he20-2g"; + case MODE_11AX_HE40_2G: + return "11ax-he40-2g"; + case MODE_11AX_HE80_2G: + return "11ax-he80-2g"; + case MODE_11BE_EHT20: + return "11be-eht20"; + case MODE_11BE_EHT40: + return "11be-eht40"; + case MODE_11BE_EHT80: + return "11be-eht80"; + case MODE_11BE_EHT80_80: + return "11be-eht80+80"; + case MODE_11BE_EHT160: + return "11be-eht160"; + case MODE_11BE_EHT160_160: + return "11be-eht160+160"; + case MODE_11BE_EHT320: + return "11be-eht320"; + case MODE_11BE_EHT20_2G: + return "11be-eht20-2g"; + case MODE_11BE_EHT40_2G: + return "11be-eht40-2g"; + case MODE_UNKNOWN: + /* skip */ + break; + + /* no default handler to allow compiler to check that the + * * enum is fully handled + * */ + } + + return ""; +} + +#define ATH12K_WMI_MLO_MAX_LINKS 3 + +struct wmi_ml_partner_info { + u32 vdev_id; + u32 hw_link_id; + u8 addr[ETH_ALEN]; + bool assoc_link; + bool primary_umac; + bool logical_link_idx_valid; + u32 logical_link_idx; +}; + +struct wmi_ml_arg { + bool enabled; + bool assoc_link; + bool mcast_link; + bool link_add; + u8 num_partner_links; + struct wmi_ml_partner_info partner_info[ATH12K_WMI_MLO_MAX_LINKS]; +}; + +struct wmi_vdev_start_req_arg { + u32 vdev_id; + struct wmi_channel_arg channel; u32 bcn_intval; u32 dtim_period; u8 *ssid; @@ -2791,12 +3566,20 @@ u32 pref_rx_streams; u32 pref_tx_streams; u32 num_noa_descriptors; + u32 min_data_rate; + u32 mbssid_flags; + u32 mbssid_tx_vdev_id; + u32 ru_punct_bitmap; + struct wmi_ml_arg ml; + u32 width_device; + u32 center_freq_device; }; struct ath12k_wmi_peer_create_arg { const u8 *peer_addr; u32 peer_type; u32 vdev_id; + bool ml_enabled; }; struct ath12k_wmi_pdev_set_regdomain_arg { @@ -2809,6 +3592,27 @@ u32 pdev_id; }; +/* Defines various options for routing policy */ +enum wmi_pdev_dest_ring_handler_type { + ATH12K_WMI_PKTROUTE_USE_CCE = 0, + ATH12K_WMI_PKTROUTE_USE_ASPT = 1, + ATH12K_WMI_PKTROUTE_USE_FSE = 2, + ATH12K_WMI_PKTROUTE_USE_CCE2 = 3, +}; + +enum ath12k_wmi_pkt_route_opcode { + ATH12K_WMI_PKTROUTE_ADD, + ATH12K_WMI_PKTROUTE_DEL, +}; + +struct ath12k_wmi_pkt_route_param { + enum ath12k_wmi_pkt_route_opcode opcode; + u32 route_type_bmap; + u32 dst_ring_handler; + u32 dst_ring; + u32 meta_data; +}; + struct ath12k_wmi_rx_reorder_queue_remove_arg { u8 *peer_macaddr; u16 vdev_id; @@ -2832,17 +3636,19 @@ #define REG_RULE_MAX_BW 0x0000ffff #define REG_RULE_REG_PWR 0x00ff0000 #define REG_RULE_ANT_GAIN 0xff000000 -#define REG_RULE_PSD_INFO BIT(2) -#define REG_RULE_PSD_EIRP 0xffff0000 +#define REG_RULE_PSD_INFO BIT(0) +#define REG_RULE_PSD_EIRP 0xff0000 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) -#define HECAP_PHYDWORD_0 0 -#define HECAP_PHYDWORD_1 1 -#define HECAP_PHYDWORD_2 2 +#define HE_PHYCAP_BYTE_0 0 +#define HE_PHYCAP_BYTE_1 1 +#define HE_PHYCAP_BYTE_2 2 +#define HE_PHYCAP_BYTE_3 3 +#define HE_PHYCAP_BYTE_4 4 #define HECAP_PHY_SU_BFER BIT(31) #define HECAP_PHY_SU_BFEE BIT(0) @@ -2876,8 +3682,31 @@ #define HE_DL_MUOFDMA_ENABLE 1 #define HE_UL_MUOFDMA_ENABLE 1 #define HE_DL_MUMIMO_ENABLE 1 +#define HE_UL_MUMIMO_ENABLE 1 #define HE_MU_BFEE_ENABLE 1 #define HE_SU_BFEE_ENABLE 1 +#define HE_MU_BFER_ENABLE 1 +#define HE_SU_BFER_ENABLE 1 + +#define EHT_MODE_SU_TX_BFEE BIT(0) +#define EHT_MODE_SU_TX_BFER BIT(1) +#define EHT_MODE_MU_TX_BFEE BIT(2) +#define EHT_MODE_MU_TX_BFER BIT(3) +#define EHT_MODE_DL_OFDMA BIT(4) +#define EHT_MODE_UL_OFDMA BIT(5) +#define EHT_MODE_MUMIMO BIT(6) +#define EHT_MODE_DL_OFDMA_TXBF BIT(7) +#define EHT_MODE_DL_OFDMA_MUMIMO BIT(8) +#define EHT_MODE_UL_OFDMA_MUMIMO BIT(9) + +#define EHT_DL_MUOFDMA_ENABLE 1 +#define EHT_UL_MUOFDMA_ENABLE 1 +#define EHT_DL_MUMIMO_ENABLE 1 +#define EHT_UL_MUMIMO_ENABLE 1 +#define EHT_MU_BFEE_ENABLE 1 +#define EHT_SU_BFEE_ENABLE 1 +#define EHT_MU_BFER_ENABLE 1 +#define EHT_SU_BFER_ENABLE 1 #define HE_VHT_SOUNDING_MODE_ENABLE 1 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 @@ -2901,6 +3730,11 @@ WMI_PEER_TYPE_TDLS = 2, }; +struct wmi_peer_create_mlo_params { + u32 tlv_header; + u32 flags; +} __packed; + struct wmi_peer_create_cmd { __le32 tlv_header; __le32 vdev_id; @@ -2938,6 +3772,18 @@ WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, }; +struct wmi_pdev_ap_ps_cmd { + u32 tlv_header; + u32 pdev_id; + u32 param_value; +}; + +struct wmi_pdev_get_ani_level_cmd { + __le32 tlv_header; + __le32 pdev_id; + __le32 param_id; +} __packed; + struct wmi_pdev_set_param_cmd { __le32 tlv_header; __le32 pdev_id; @@ -2966,6 +3812,7 @@ __le32 tlv_header; /* ref wmi_bss_chan_info_req_type */ __le32 req_type; + __le32 pdev_id; } __packed; struct wmi_ap_ps_peer_cmd { @@ -2994,6 +3841,16 @@ __le32 dfs_domain; } __packed; +struct wmi_pdev_pkt_route_cmd { + u32 tlv_header; + u32 pdev_id; + u32 opcode; + u32 route_type_bmap; + u32 dst_ring; + u32 meta_data; + u32 dst_ring_handler; +} __packed; + struct wmi_peer_set_param_cmd { __le32 tlv_header; __le32 vdev_id; @@ -3002,6 +3859,21 @@ __le32 param_value; } __packed; +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT +struct wmi_peer_set_intra_bss_cmd { + __le32 tlv_header; + struct wmi_mac_addr peer_macaddr; + __le32 vdev_id; + __le32 enable; +} __packed; + +struct ath12k_vdev_set_intra_bss_cmd { + u32 tlv_header; + u32 vdev_id; + u32 enable; +} __packed; +#endif + struct wmi_peer_flush_tids_cmd { __le32 tlv_header; __le32 vdev_id; @@ -3030,7 +3902,6 @@ #define WLAN_SCAN_MAX_NUM_SSID 10 #define WLAN_SCAN_MAX_NUM_BSSID 10 -#define WLAN_SCAN_MAX_NUM_CHANNELS 40 struct ath12k_wmi_element_info_arg { u32 len; @@ -3213,17 +4084,17 @@ scan_f_filter_prb_req:1, scan_f_bypass_dfs_chn:1, scan_f_continue_on_err:1, + scan_f_promisc_mode:1, + scan_f_force_active_dfs_chn:1, + scan_f_add_tpc_ie_in_probe:1, + scan_f_add_ds_ie_in_probe:1, + scan_f_add_spoofed_mac_in_probe:1, scan_f_offchan_mgmt_tx:1, scan_f_offchan_data_tx:1, - scan_f_promisc_mode:1, scan_f_capture_phy_err:1, scan_f_strict_passive_pch:1, scan_f_half_rate:1, scan_f_quarter_rate:1, - scan_f_force_active_dfs_chn:1, - scan_f_add_tpc_ie_in_probe:1, - scan_f_add_ds_ie_in_probe:1, - scan_f_add_spoofed_mac_in_probe:1, scan_f_add_rand_seq_in_probe:1, scan_f_en_ie_whitelist_in_probe:1, scan_f_forced:1, @@ -3239,7 +4110,7 @@ u32 num_bssid; u32 num_ssids; u32 n_probes; - u32 chan_list[WLAN_SCAN_MAX_NUM_CHANNELS]; + u32 *chan_list; u32 notify_scan_events; struct cfg80211_ssid ssid[WLAN_SCAN_MAX_NUM_SSID]; struct ath12k_wmi_mac_addr_params bssid_list[WLAN_SCAN_MAX_NUM_BSSID]; @@ -3347,6 +4218,29 @@ #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) +enum reg_subdomains_6g { + EMPTY_6G = 0x0, + FCC1_CLIENT_LPI_REGULAR_6G = 0x01, + FCC1_CLIENT_SP_6G = 0x02, + FCC1_AP_LPI_6G = 0x03, + FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6G, + FCC1_AP_SP_6G = 0x04, + ETSI1_LPI_6G = 0x10, + ETSI1_VLP_6G = 0x11, + ETSI2_LPI_6G = 0x12, + ETSI2_VLP_6G = 0x13, + APL1_LPI_6G = 0x20, + APL1_VLP_6G = 0x21, +}; + +enum reg_super_domain_6g { + FCC1_6G = 0x01, + ETSI1_6G = 0x02, + ETSI2_6G = 0x03, + APL1_6G = 0x04, + FCC1_6G_CL = 0x05, + }; + struct ath12k_wmi_channel_params { __le32 tlv_header; __le32 mhz; @@ -3369,6 +4263,12 @@ #define ATH12K_WMI_FW_HANG_ASSERT_TYPE 1 #define ATH12K_WMI_FW_HANG_DELAY 0 +enum wmi_fw_hang_recovery_mode_type { + ATH12K_WMI_DISABLE_FW_RECOVERY = 200, + ATH12K_WMI_FW_HANG_RECOVERY_MODE0, + ATH12K_WMI_FW_HANG_RECOVERY_MODE1, +}; + /* type, 0:unused 1: ASSERT 2: not respond detect command * delay_time_ms, the simulate will delay time */ @@ -3386,14 +4286,66 @@ __le32 param_value; } __packed; +enum wmi_stats_id { + WMI_REQUEST_PEER_STAT = BIT(0), + WMI_REQUEST_AP_STAT = BIT(1), + WMI_REQUEST_PDEV_STAT = BIT(2), + WMI_REQUEST_VDEV_STAT = BIT(3), + WMI_REQUEST_BCNFLT_STAT = BIT(4), + WMI_REQUEST_VDEV_RATE_STAT = BIT(5), + WMI_REQUEST_INST_STAT = BIT(6), + WMI_REQUEST_MIB_STAT = BIT(7), + WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), + WMI_REQUEST_CONGESTION_STAT = BIT(9), + WMI_REQUEST_PEER_EXTD_STAT = BIT(10), + WMI_REQUEST_BCN_STAT = BIT(11), + WMI_REQUEST_BCN_STAT_RESET = BIT(12), + WMI_REQUEST_PEER_EXTD2_STAT = BIT(13), +}; + +struct wmi_request_stats_cmd { + __le32 tlv_header; + /* enum wmi_stats_id */ + __le32 stats_id; + __le32 vdev_id; + struct ath12k_wmi_mac_addr_params peer_macaddr; + __le32 pdev_id; +} __packed; + struct wmi_get_pdev_temperature_cmd { __le32 tlv_header; __le32 param; __le32 pdev_id; } __packed; +#define MAX_WMI_UTF_LEN 252 + +struct wmi_ftm_seg_hdr { + u32 len; + u32 msgref; + u32 segmentinfo; + u32 pdev_id; +} __packed; + +struct wmi_ftm_cmd { + u32 tlv_header; + struct wmi_ftm_seg_hdr seg_hdr; + u8 data[]; +} __packed; + +struct wmi_ftm_event_msg { + struct wmi_ftm_seg_hdr seg_hdr; + u8 data[]; +} __packed; #define WMI_BEACON_TX_BUFFER_SIZE 512 +#define WMI_BEACON_EMA_PARAM_PERIODICITY_SHIFT 0 +#define WMI_BEACON_EMA_PARAM_TMPL_IDX_SHIFT 8 +#define WMI_BEACON_EMA_PARAM_FIRST_TMPL_SHIFT 16 +#define WMI_BEACON_EMA_PARAM_LAST_TMPL_SHIFT 24 + +#define WMI_BEACON_PROTECTION_EN_BIT BIT(0) + struct wmi_bcn_tmpl_cmd { __le32 tlv_header; __le32 vdev_id; @@ -3404,6 +4356,11 @@ __le32 csa_event_bitmap; __le32 mbssid_ie_offset; __le32 esp_ie_offset; + __le32 csc_switch_count_offset; + __le32 csc_event_bitmap; + __le32 mu_edca_ie_offset; + __le32 feature_enable_bitmap; + __le32 ema_params; } __packed; struct wmi_vdev_install_key_cmd { @@ -3454,7 +4411,39 @@ u8 rates[WMI_MAX_SUPPORTED_RATES]; }; +#define EMLSR_DELAY_MAX 5 +#define EMLSR_TRANS_DELAY_MAX 6 +#define EMLCAP_TIMEOUT_MAX 11 +#define IEEE80211_TU_TO_USEC(x) ((x) << 10) /* (x)X1024 */ +#define EMLCAP_TRANSTIMEOUT_0 0 +#define EMLCAP_TRANSTIMEOUT_1 (1U << 7) +#define EMLCAP_TRANSTIMEOUT_2 (1U << 8) +#define EMLCAP_TRANSTIMEOUT_3 (1U << 9) +#define EMLCAP_TRANSTIMEOUT_4 IEEE80211_TU_TO_USEC(1) +#define EMLCAP_TRANSTIMEOUT_5 IEEE80211_TU_TO_USEC((1U << 1)) +#define EMLCAP_TRANSTIMEOUT_6 IEEE80211_TU_TO_USEC((1U << 2)) +#define EMLCAP_TRANSTIMEOUT_7 IEEE80211_TU_TO_USEC((1U << 3)) +#define EMLCAP_TRANSTIMEOUT_8 IEEE80211_TU_TO_USEC((1U << 4)) +#define EMLCAP_TRANSTIMEOUT_9 IEEE80211_TU_TO_USEC((1U << 5)) +#define EMLCAP_TRANSTIMEOUT_10 IEEE80211_TU_TO_USEC((1U << 6)) + +struct peer_assoc_mlo_params { + bool enabled; + bool assoc_link; + bool primary_umac; + bool peer_id_valid; + bool logical_link_idx_valid; + u8 mld_addr[ETH_ALEN]; + u32 logical_link_idx; + u32 ml_peer_id; + u32 ieee_link_id; + u8 num_partner_links; + struct wmi_ml_partner_info partner_info[ATH12K_WMI_MLO_MAX_LINKS]; + u32 eml_caps; +}; + struct ath12k_wmi_peer_assoc_arg { + struct wmi_mac_addr peer_macaddr; u32 vdev_id; u32 peer_new_assoc; u32 peer_associd; @@ -3487,6 +4476,7 @@ bool bw_40; bool bw_80; bool bw_160; + bool bw_320; bool stbc_flag; bool ldpc_flag; bool static_mimops_flag; @@ -3514,8 +4504,39 @@ bool twt_responder; bool twt_requester; struct ath12k_wmi_ppe_threshold_arg peer_ppet; + bool eht_flag; + u32 peer_eht_cap_mac[WMI_MAX_EHTCAP_MAC_SIZE]; + u32 peer_eht_cap_phy[WMI_MAX_EHTCAP_PHY_SIZE]; + u32 peer_eht_mcs_count; + u32 peer_eht_rx_mcs_set[WMI_MAX_EHTCAP_RATE_SET]; + u32 peer_eht_tx_mcs_set[WMI_MAX_EHTCAP_RATE_SET]; + u32 peer_eht_ops; + struct ath12k_ppe_threshold peer_eht_ppet; + u32 ru_punct_bitmap; + bool is_assoc; + struct peer_assoc_mlo_params ml; }; +struct wmi_peer_assoc_mlo_partner_info { + u32 tlv_header; + u32 vdev_id; + u32 hw_link_id; + u32 flags; + u32 logical_link_idx; +} __packed; + +struct wmi_peer_assoc_mlo_params { + u32 tlv_header; + u32 flags; + struct wmi_mac_addr mld_addr; + u32 logical_link_idx; + u32 ml_peer_id; + u32 ieee_link_id; + u32 emlsr_trans_timeout_us; + u32 emlsr_trans_delay_us; + u32 emlsr_padding_delay_us; +} __packed; + struct wmi_peer_assoc_complete_cmd { __le32 tlv_header; struct ath12k_wmi_mac_addr_params peer_macaddr; @@ -3545,8 +4566,23 @@ __le32 peer_he_cap_info_internal; __le32 min_data_rate; __le32 peer_he_caps_6ghz; + __le32 sta_type; + __le32 bss_max_idle_option; + __le32 auth_mode; + __le32 peer_flags_ext; + __le32 ru_punct_bitmap; + __le32 peer_eht_cap_mac[WMI_MAX_EHTCAP_MAC_SIZE]; + __le32 peer_eht_cap_phy[WMI_MAX_EHTCAP_PHY_SIZE]; + __le32 peer_eht_ops; + struct wmi_ppe_threshold peer_eht_ppet; } __packed; +struct stats_request_params { + u32 stats_id; + u32 vdev_id; + u32 pdev_id; +}; + struct wmi_stop_scan_cmd { __le32 tlv_header; __le32 requestor; @@ -3569,6 +4605,7 @@ __le32 pdev_id; } __packed; +#define WMI_MLO_MGMT_TID 0xFFFFFFFF #define WMI_MGMT_SEND_DOWNLD_LEN 64 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) @@ -3596,6 +4633,18 @@ /* This TLV is followed by struct wmi_mgmt_frame */ /* Followed by struct wmi_mgmt_send_params */ + /* Followed by struct wmi_mlo_mgmt_send_params */ +} __packed; + +struct wmi_mlo_mgmt_send_params { + u32 tlv_header; + u32 hw_link_id; +} __packed; + +struct wmi_mgmt_send_params { + u32 tlv_header; + u32 tx_param_dword0; + u32 tx_param_dword1; } __packed; struct wmi_sta_powersave_mode_cmd { @@ -3673,6 +4722,39 @@ } cc_info; } __packed; +#define THERMAL_LEVELS 1 +struct tt_level_config { + u32 tmplwm; + u32 tmphwm; + u32 dcoffpercent; + u32 priority; +}; + +struct ath12k_wmi_thermal_mitigation_arg { + u32 pdev_id; + u32 enable; + u32 dc; + u32 dc_per_event; + struct tt_level_config levelconf[THERMAL_LEVELS]; +}; + +struct wmi_therm_throt_config_request_cmd { + __le32 tlv_header; + __le32 pdev_id; + __le32 enable; + __le32 dc; + __le32 dc_per_event; + __le32 therm_throt_levels; +} __packed; + +struct wmi_therm_throt_level_config_info { + __le32 tlv_header; + u32 temp_lwm; + u32 temp_hwm; + u32 dc_off_percent; + u32 prio; +} __packed; + struct wmi_delba_send_cmd { __le32 tlv_header; __le32 vdev_id; @@ -3704,6 +4786,36 @@ struct ath12k_wmi_mac_addr_params peer_macaddr; } __packed; +struct wmi_pdev_pktlog_filter_info { + __le32 tlv_header; + struct ath12k_wmi_mac_addr_params peer_macaddr; +} __packed; + +struct wmi_pdev_pktlog_filter_cmd { + __le32 tlv_header; + __le32 pdev_id; + __le32 enable; + __le32 filter_type; + __le32 num_mac; +} __packed; + +enum ath12k_wmi_pktlog_enable { + ATH12K_WMI_PKTLOG_ENABLE_AUTO = 0, + ATH12K_WMI_PKTLOG_ENABLE_FORCE = 1, +}; + +struct wmi_pktlog_enable_cmd { + __le32 tlv_header; + __le32 pdev_id; + __le32 evlist; /* WMI_PKTLOG_EVENT */ + __le32 enable; +} __packed; + +struct wmi_pktlog_disable_cmd { + __le32 tlv_header; + __le32 pdev_id; +} __packed; + #define DFS_PHYERR_UNIT_TEST_CMD 0 #define DFS_UNIT_TEST_MODULE 0x2b #define DFS_UNIT_TEST_TOKEN 0xAA @@ -3721,6 +4833,26 @@ u32 radar_param; }; +#define WMI_AWGN_UNIT_TEST_MODULE 0x18 +#define WMI_AWGN_UNIT_TEST_TOKEN 0 +#define WMI_UNIT_TEST_AWGN_INTF_TYPE 1 +#define WMI_UNIT_TEST_AWGN_PRIMARY_20 0x01 + +enum wmi_awgn_test_args_idx { + WMI_AWGN_TEST_AWGN_INT, + WMI_AWGN_TEST_BITMAP, + WMI_AWGN_MAX_TEST_ARGS, +}; + +#define WMI_M3_UNIT_TEST_MODULE 0x22 +#define WMI_M3_UNIT_TEST_TOKEN 0 + +enum wmi_m3_test_args_idx { + WMI_M3_TEST_CMDID, + WMI_M3_TEST_ENABLE, + WMI_M3_MAX_TEST_ARGS, +}; + struct wmi_unit_test_cmd { __le32 tlv_header; __le32 vdev_id; @@ -3757,6 +4889,9 @@ #define WMI_PEER_160MHZ 0x40000000 #define WMI_PEER_SAFEMODE_EN 0x80000000 +#define WMI_PEER_EXT_EHT 0x00000001 +#define WMI_PEER_EXT_320MHZ 0x00000002 + struct ath12k_wmi_vht_rate_set_params { __le32 tlv_header; __le32 rx_max_rate; @@ -3768,6 +4903,14 @@ struct ath12k_wmi_he_rate_set_params { __le32 tlv_header; + /* MCS at which the peer can receive */ + __le32 rx_mcs_set; + /* MCS at which the peer can transmit */ + __le32 tx_mcs_set; +} __packed; + +struct wmi_eht_rate_set { + __le32 tlv_header; __le32 rx_mcs_set; __le32 tx_mcs_set; } __packed; @@ -3775,7 +4918,6 @@ #define MAX_REG_RULES 10 #define REG_ALPHA2_LEN 2 #define MAX_6G_REG_RULES 5 -#define REG_US_5G_NUM_REG_RULES 4 enum wmi_start_event_param { WMI_VDEV_START_RESP_EVENT = 0, @@ -3796,6 +4938,7 @@ }; __le32 cfgd_tx_streams; __le32 cfgd_rx_streams; + s32 max_allowed_tx_power; } __packed; /* VDEV start response status codes */ @@ -3805,6 +4948,10 @@ WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, + /** Band unsupported by current hw mode in VDEV start */ + WMI_VDEV_START_RESPONSE_INVALID_BAND = 5, + WMI_VDEV_START_RESPONSE_INVALID_PREFERRED_TX_RX_STREAMS = 6, /** Invalid preferred tx/rx streams */ + WMI_VDEV_START_RESPONSE_INVALID_TX_VAP_CONFIG = 7, /** Invalid tx_vap config in VDEV start */ }; enum wmi_reg_6g_ap_type { @@ -3846,6 +4993,11 @@ #define WMI_REG_CLIENT_MAX 4 +enum wmi_reg_chan_list_cmd_type { + WMI_REG_CHAN_LIST_CC_ID = 0, + WMI_REG_CHAN_LIST_CC_EXT_ID = 1, +}; + struct wmi_reg_chan_list_cc_ext_event { __le32 status_code; __le32 phy_id; @@ -3918,7 +5070,6 @@ } __packed; struct wmi_pdev_bss_chan_info_event { - __le32 pdev_id; __le32 freq; /* Units in MHz */ __le32 noise_floor; /* units are dBm */ /* rx clear - how often the channel was unused */ @@ -3936,6 +5087,7 @@ /*rx_cycle cnt for my bss in 64bits format */ __le32 rx_bss_cycle_count_low; __le32 rx_bss_cycle_count_high; + __le32 pdev_id; } __packed; #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 @@ -3977,6 +5129,177 @@ __le32 tx_status; } __packed; +struct wmi_pdev_stats_base { + s32 chan_nf; + u32 tx_frame_count; /* Cycles spent transmitting frames */ + u32 rx_frame_count; /* Cycles spent receiving frames */ + u32 rx_clear_count; /* Total channel busy time, evidently */ + u32 cycle_count; /* Total on-channel time */ + u32 phy_err_count; + u32 chan_tx_pwr; +} __packed; + +struct wmi_pdev_stats_extra { + u32 ack_rx_bad; + u32 rts_bad; + u32 rts_good; + u32 fcs_bad; + u32 no_beacons; + u32 mib_int_count; +} __packed; + +struct wmi_pdev_stats_tx { + /* Num HTT cookies queued to dispatch list */ + s32 comp_queued; + + /* Num HTT cookies dispatched */ + s32 comp_delivered; + + /* Num MSDU queued to WAL */ + s32 msdu_enqued; + + /* Num MPDU queue to WAL */ + s32 mpdu_enqued; + + /* Num MSDUs dropped by WMM limit */ + s32 wmm_drop; + + /* Num Local frames queued */ + s32 local_enqued; + + /* Num Local frames done */ + s32 local_freed; + + /* Num queued to HW */ + s32 hw_queued; + + /* Num PPDU reaped from HW */ + s32 hw_reaped; + + /* Num underruns */ + s32 underrun; + + /* Num PPDUs cleaned up in TX abort */ + s32 tx_abort; + + /* Num MPDUs requeued by SW */ + s32 mpdus_requed; + + /* excessive retries */ + u32 tx_ko; + + /* data hw rate code */ + u32 data_rc; + + /* Scheduler self triggers */ + u32 self_triggers; + + /* frames dropped due to excessive sw retries */ + u32 sw_retry_failure; + + /* illegal rate phy errors */ + u32 illgl_rate_phy_err; + + /* wal pdev continuous xretry */ + u32 pdev_cont_xretry; + + /* wal pdev tx timeouts */ + u32 pdev_tx_timeout; + + /* wal pdev resets */ + u32 pdev_resets; + + /* frames dropped due to non-availability of stateless TIDs */ + u32 stateless_tid_alloc_failure; + + /* PhY/BB underrun */ + u32 phy_underrun; + + /* MPDU is more than txop limit */ + u32 txop_ovf; +} __packed; + +struct wmi_pdev_stats_rx { + /* Cnts any change in ring routing mid-ppdu */ + s32 mid_ppdu_route_change; + + /* Total number of statuses processed */ + s32 status_rcvd; + + /* Extra frags on rings 0-3 */ + s32 r0_frags; + s32 r1_frags; + s32 r2_frags; + s32 r3_frags; + + /* MSDUs / MPDUs delivered to HTT */ + s32 htt_msdus; + s32 htt_mpdus; + + /* MSDUs / MPDUs delivered to local stack */ + s32 loc_msdus; + s32 loc_mpdus; + + /* AMSDUs that have more MSDUs than the status ring size */ + s32 oversize_amsdu; + + /* Number of PHY errors */ + s32 phy_errs; + + /* Number of PHY errors drops */ + s32 phy_err_drop; + + /* Number of mpdu errors - FCS, MIC, ENC etc. */ + s32 mpdu_errs; +} __packed; + +struct wmi_pdev_stats { + struct wmi_pdev_stats_base base; + struct wmi_pdev_stats_tx tx; + struct wmi_pdev_stats_rx rx; +} __packed; + +#define WLAN_MAX_AC 4 +#define MAX_TX_RATE_VALUES 10 +#define MAX_TX_RATE_VALUES 10 + +struct wmi_vdev_stats { + u32 vdev_id; + u32 beacon_snr; + u32 data_snr; + u32 num_tx_frames[WLAN_MAX_AC]; + u32 num_rx_frames; + u32 num_tx_frames_retries[WLAN_MAX_AC]; + u32 num_tx_frames_failures[WLAN_MAX_AC]; + u32 num_rts_fail; + u32 num_rts_success; + u32 num_rx_err; + u32 num_rx_discard; + u32 num_tx_not_acked; + u32 tx_rate_history[MAX_TX_RATE_VALUES]; + u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; +} __packed; + +struct wmi_bcn_stats { + u32 vdev_id; + u32 tx_bcn_succ_cnt; + u32 tx_bcn_outage_cnt; +} __packed; + +struct wmi_stats_event { + __le32 stats_id; + __le32 num_pdev_stats; + __le32 num_vdev_stats; + __le32 num_peer_stats; + __le32 num_bcnflt_stats; + __le32 num_chan_stats; + __le32 num_mib_stats; + __le32 pdev_id; + __le32 num_bcn_stats; + __le32 num_peer_extd_stats; + __le32 num_peer_extd2_stats; +} __packed; + struct wmi_pdev_ctl_failsafe_chk_event { __le32 pdev_id; __le32 ctl_failsafe_status; @@ -4001,10 +5324,83 @@ a_sle32 sidx; } __packed; +struct wmi_pdev_radar_flags_param { + __le32 radar_flags; +} __packed; +#define WMI_PDEV_RADAR_FLAGS_FULL_BW_NOL_MARK_BIT 0 + +#define WMI_DCS_AWGN_INTF 0x04 + +struct wmi_dcs_awgn_info { + u32 channel_width; + u32 chan_freq; + u32 center_freq0; + u32 center_freq1; + u32 chan_bw_interference_bitmap; +} __packed; + +struct wmi_dcs_interference_ev { + u32 interference_type; + u32 pdev_id; +} __packed; + +enum wmi_host_channel_width { + WMI_HOST_CHAN_WIDTH_20 = 0, + WMI_HOST_CHAN_WIDTH_40 = 1, + WMI_HOST_CHAN_WIDTH_80 = 2, + WMI_HOST_CHAN_WIDTH_160 = 3, + WMI_HOST_CHAN_WIDTH_80P80 = 4, + WMI_HOST_CHAN_WIDTH_5 = 5, + WMI_HOST_CHAN_WIDTH_10 = 6, + WMI_HOST_CHAN_WIDTH_165 = 7, + WMI_HOST_CHAN_WIDTH_160P160 = 8, + WMI_HOST_CHAN_WIDTH_320 = 9, + /*keep last */ + WMI_HOST_CHAN_WIDTH_MAX = 0xF, +}; + +enum wmi_dcs_interference_chan_segment { + WMI_DCS_SEG_PRI20 = 0x1, + WMI_DCS_SEG_SEC20 = 0x2, + WMI_DCS_SEG_SEC40_LOW = 0x4, + WMI_DCS_SEG_SEC40_UP = 0x8, + WMI_DCS_SEG_SEC40 = 0xC, + WMI_DCS_SEG_SEC80_LOW = 0x10, + WMI_DCS_SEG_SEC80_LOW_UP = 0x20, + WMI_DCS_SEG_SEC80_UP_LOW = 0x40, + WMI_DCS_SEG_SEC80_UP = 0x80, + WMI_DCS_SEG_SEC80 = 0xF0, + WMI_DCS_SEG_SEC160_LOW = 0x0100, + WMI_DCS_SEG_SEC160_LOW_UP = 0x0200, + WMI_DCS_SEG_SEC160_LOW_UP_UP = 0x0400, + WMI_DCS_SEG_SEC160_LOW_UP_UP_UP = 0x0800, + WMI_DCS_SEG_SEC160_UP_LOW_LOW_LOW = 0x1000, + WMI_DCS_SEG_SEC160_UP_LOW_LOW = 0x2000, + WMI_DCS_SEG_SEC160_UP_LOW = 0x4000, + WMI_DCS_SEG_SEC160_UP = 0x8000, + WMI_DCS_SEG_SEC160 = 0xFF00, +}; + struct wmi_pdev_temperature_event { /* temperature value in Celsius degree */ a_sle32 temp; __le32 pdev_id; + __le32 mbssid_flags; + __le32 mbssid_tx_vdev_id; +} __packed; + +#define WMI_AC_BE 0 +#define WMI_AC_BK 1 +#define WMI_AC_VI 2 +#define WMI_AC_VO 3 +#define WMI_AC_MAX 4 + +struct wmi_pdev_update_muedca_event { + u32 pdev_id; + u32 aifsn[WMI_AC_MAX]; + u32 ecwmin[WMI_AC_MAX]; + u32 ecwmax[WMI_AC_MAX]; + u32 muedca_expiration_time[WMI_AC_MAX]; } __packed; #define WMI_RX_STATUS_OK 0x00 @@ -4015,6 +5411,1000 @@ #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 +/** + * ath12k_host_mlo_glb_per_chip_crash_info - per chip crash + * information in MLO global shared memory + * @chip_id: MLO chip id + * @crash_reason: Address of the crash_reason corresponding to chip_id + * recovery_mode: Address of recovery mode corressponding to chip_id + */ +struct ath12k_host_mlo_glb_per_chip_crash_info { + u8 chip_id; + void *crash_reason; + void *recovery_mode; +}; + +/** + * ath12k_host_mlo_glb_chip_crash_info - chip crash information in MLO + * global shared memory + * @no_of_chips: No of partner chip to which crash information is shared + * @valid_chip_bmap: Valid chip bitmap + * @per_chip_crash_info: pointer to per chip crash information. + */ +struct ath12k_host_mlo_glb_chip_crash_info { + u8 no_of_chips; + u8 valid_chip_bmap; + struct ath12k_host_mlo_glb_per_chip_crash_info *per_chip_crash_info; +}; + +/** + * ath12k_host_mlo_glb_rx_reo_snapshot_info - MGMT Rx REO information in MLO + * global shared memory + * @num_links: Number of valid links + * @valid_link_bmap: Valid link bitmap + * @link_info: pointer to an array of Rx REO per-link information + * @hw_forwarded_snapshot_ver: HW forwarded snapshot version + * @fw_forwarded_snapshot_ver: FW forwarded snapshot version + * @fw_consumed_snapshot_ver: FW consumed snapshot version + */ +struct ath12k_host_mlo_glb_rx_reo_snapshot_info { + u8 num_links; + u16 valid_link_bmap; + struct ath12k_host_mlo_glb_rx_reo_per_link_info *link_info; + u8 hw_forwarded_snapshot_ver; + u8 fw_forwarded_snapshot_ver; + u8 fw_consumed_snapshot_ver; +}; + +/** + * ath12k_host_ath12k_mlo_glb_shmem_params - MLO global shared memory parameters + * @major_version: Major version + * @minor_version: Minor version + */ +struct ath12k_host_ath12k_mlo_glb_shmem_params { + u16 major_version; + u16 minor_version; +}; + +/** + * ath12k_host_mlo_mem_arena - MLO Global shared memory arena context + * @shmem_params: shared memory parameters + * @rx_reo_snapshot_info: MGMT Rx REO snapshot information + * @init_done: Initialized snapshot info + */ +struct ath12k_host_mlo_mem_arena { + struct ath12k_host_ath12k_mlo_glb_shmem_params shmem_params; + struct ath12k_host_mlo_glb_rx_reo_snapshot_info rx_reo_snapshot_info; + struct ath12k_host_mlo_glb_chip_crash_info global_chip_crash_info; + bool init_done; + /* Protect the parallel initialization */ + struct mutex mutex_lock; +}; + +/** Helper Macros for tlv header of the given tlv buffer */ +/* Size of the TLV Header which is the Tag and Length fields */ +#define MLO_SHMEM_TLV_HDR_SIZE (1 * sizeof(u32)) + +/* TLV Helper macro to get the TLV Header given the pointer to the TLV buffer. */ +#define MLO_SHMEMTLV_GET_HDR(tlv_buf) (((u32 *)(tlv_buf))[0]) + +/* TLV Helper macro to set the TLV Header given the pointer to the TLV buffer. */ +#define MLO_SHMEMTLV_SET_HDR(tlv_buf, tag, len) \ + ((((u32 *)(tlv_buf))[0]) = ((tag << 16) | (len & 0x0000FFFF))) + +/* TLV Helper macro to get the TLV Tag given the TLV header. */ +#define MLO_SHMEMTLV_GET_TLVTAG(tlv_header) ((u32)((tlv_header) >> 16)) + +/* TLV Helper macro to get the TLV Buffer Length (minus TLV header size) + * given the TLV header. + */ +#define MLO_SHMEMTLV_GET_TLVLEN(tlv_header) \ + ((u32)((tlv_header) & 0x0000FFFF)) +/* TLV Helper macro to get the TLV length from TLV structure size + * by removing TLV header size. + */ +#define MLO_SHMEMTLV_GET_STRUCT_TLVLEN(tlv_struct) \ + ((u32)(sizeof(tlv_struct) - MLO_SHMEM_TLV_HDR_SIZE)) + +/* Definition of Global H SHMEM Arena */ +struct ath12k_mlo_glb_shmem { + /* TLV tag and len; tag equals ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM */ + u32 tlv_header; + /** + * major_minor_version + * + * [15:0]: minor version + * [31:16]: major version + */ + u32 major_minor_version; + /* This TLV is followed by TLVs + * mlo_glb_rx_reo_snapshot_info reo_snapshot; + * struct mlo_glb_link_info glb_info; + */ +}; + +#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_MASK GENMASK(31, 16) +#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_MASK GENMASK(15, 0) +#define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_MASK GENMASK(19, 4) +#define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_MASK GENMASK(3, 0) +#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_MASK GENMASK(2, 0) +#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_MASK GENMASK(5, 3) +#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_MASK GENMASK(8, 6) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_MASK GENMASK(1, 0) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_MASK GENMASK(4, 2) + +#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_GET(major_minor_version) \ + FIELD_GET(MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_MASK, major_minor_version) +#define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_GET(major_minor_version) \ + FIELD_GET(MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_MASK, major_minor_version) + +#define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_GET(link_info) \ + FIELD_GET(MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_MASK, link_info) +#define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_GET(link_info) \ + FIELD_GET(MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_MASK, link_info) +#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_GET(snapshot_ver_info) \ + FIELD_GET(MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_MASK, snapshot_ver_info) +#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_GET(snapshot_ver_info) \ + FIELD_GET(MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_MASK, snapshot_ver_info) +#define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_GET(snapshot_ver_info) \ + FIELD_GET(MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_MASK, snapshot_ver_info) + +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) \ + FIELD_GET(MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_MASK, chip_info) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) \ + FIELD_GET(MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_MASK, chip_info) + +/** Definition of the GLB_H_SHMEM arena tlv structures */ +enum { + ATH12K_MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO, + ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO, +}; + +struct mlo_glb_link_info { + /* TLV tag and len; tag equals ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO */ + u32 tlv_header; + + /** + * link_info + * + * [3:0]: no_of_links + * [19:4]: valid_link_bmap + * [31:20]: reserved + */ + u32 link_info; + /* This TLV is followed by array of mlo_glb_link: + * mlo_glb_link will have multiple instances equal to num of hw links + * received by no_of_link + * mlo_glb_link glb_link_info[]; + */ +}; + +enum ath12k_mlo_chip_crash_reason { + ATH12K_MLO_SHMEM_CRASH_PARTNER_CHIPS = 1, +}; + +struct mlo_glb_chip_crash_info { + /* TLV tag and len; tag equals + * MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */ + u32 tlv_header; + + /** + * [1:0]: no_of_chips + * [4:2]: valid_chip_bmap + * For number of chips beyond 3, extension fields are added. + * [9:5]: valid_chip_bmap_ext + * [15:12]: no_of_chips_ext + * [31:16]: reserved + */ + u32 chip_info; + /* + * This TLV is followed by array of mlo_glb_per_chip_crash_info: + * mlo_glb_per_chip_crash_info will have multiple instances equal to + * num of partner chips received by no_of_chips + * mlo_glb_per_chip_crash_info per_chip_crash_info[]; + */ +}; + +struct mlo_glb_per_chip_crash_info { + /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO */ + u32 tlv_header; + + /* + * crash reason, takes value in enum ath12k_mlo_chip_crash_reason + */ + u32 crash_reason; + + /* + * recovery mode, takes value in enum ath12k_mlo_recovery_mode + */ + u32 recovery_mode; +}; + + +/* Definition of the complete REO snapshot info */ +struct mlo_glb_rx_reo_snapshot_info { + /* TLV tag and len; tag equals ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO */ + u32 tlv_header; + + /** + * link_info + * + * [3:0]: no_of_links + * [19:4]: valid_link_bmap + * [31:20]: reserved + */ + u32 link_info; + + /** + * snapshot_ver_info + * + * [2:0]: hw_forwarded snapshot version + * [5:3]: fw_forwarded snapshot version + * [8:6]: fw_consumed snapshot version + * [31:9]: reserved + */ + u32 snapshot_ver_info; + u32 reserved_alignment_padding; + + /* This TLV is followed by array of mlo_glb_rx_reo_per_link_snapshot_info: + * mlo_glb_rx_reo_per_link_snapshot_info will have multiple instances + * equal to num of hw links received by no_of_link + * mlo_glb_rx_reo_per_link_snapshot_info per_link_info[]; + */ +}; + +struct ath12k_host_mlo_glb_rx_reo_per_link_info { + u8 link_id; + void *fw_consumed; + void *fw_forwarded; + void *hw_forwarded; +}; + +/* REO snapshot structure */ +struct mgmt_rx_reo_snapshot { + /* TLV tag and len; tag equals ATH12K_MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT */ + u32 tlv_header; + u32 reserved_alignment_padding; + /** + * mgmt_rx_reo_snapshot_low + * + * [0]: valid + * [16:1]: mgmt_pkt_ctr + * [31:17]: global_timestamp_low + */ + u32 mgmt_rx_reo_snapshot_low; + + /** + * mgmt_rx_reo_snapshot_high + * + * [16:0]: global_timestamp_high + * [31:17]: mgmt_pkt_ctr_redundant + */ + u32 mgmt_rx_reo_snapshot_high; + +}; + +struct mlo_glb_rx_reo_per_link_snapshot_info { + /* TLV tag and len; tag equals ATH12K_MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO */ + u32 tlv_header; + u32 reserved_alignment_padding; + struct mgmt_rx_reo_snapshot fw_consumed; + struct mgmt_rx_reo_snapshot fw_forwarded; + struct mgmt_rx_reo_snapshot hw_forwarded; +}; + +/** + * Enum which defines different versions of management Rx reorder snapshots. + */ +enum { + /** + * DWORD Lower: + * [15:0] : Management packet counter + * [30:16] : Redundant global time stamp = Global time stamp[14:0] + * [31] : Valid + * + * DWORD Upper: + * [31:0] : Global time stamp + * + */ + ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY = 0, + + /** + * DWORD Lower: + * [14:0] : Global time stamp[14:0] + * [30:15] : Management packet counter + * [31] : Valid + * + * DWORD Upper: + * [14:0] : Redundant management packet counter = Management packet + * counter[14:0] + * [31:15] : Global time stamp[31:15] + */ + ATH12K_MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY = 1, +}; + +/** + * Macros for getting and setting the required number of bits + * from the TLV params. + */ +#define ATH12K_MLO_SHMEM_GET_BITS(_val, _index, _num_bits) \ + (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) + +/* WMI CMD to receive the management filter criteria from the host */ +struct ath12k_wmi_mgmt_rx_reo_filter_config_cmd_fixed_param { + u32 tlv_header; + u32 pdev_id; /* pdev_id for identifying the MAC */ + /* filter: + * Each bit represents the possible combination of frame type (2 bits) + * and subtype (4 bits) + * There would be 64 such combinations as per the 802.11 standard + * For Exp : We have beacon frame, we will take the type and subtype + * of this frame and concatenate the bits, it will give 6 bits + * number. We need to go to that bit position in the below + * 2 filter_low and filter_high bitmap and set the bit. + */ + u32 filter_low; + u32 filter_high; +}; + +#define WMI_MGMT_RX_FW_CONSUMED_PARAM_MGMT_PKT_CTR_VALID_GET GENMASK(15, 15) +#define WMI_MGMT_RX_FW_CONSUMED_PARAM_MGMT_PKT_CTR_GET GENMASK(31, 16) + +struct ath12k_wmi_mgmt_rx_fw_consumed_hdr { + u32 rx_tsf_l32; /* h/w assigned timestamp of the rx frame in micro sec */ + u32 rx_tsf_u32 ;/* h/w assigned timestamp of the rx frame in micro sec */ + u32 pdev_id; /* pdev_id for identifying the MAC the rx mgmt frame was received by */ + /** + * peer_info_subtype + * + * [15:0]: ml_peer_id, ML peer_id unique across chips + * [18:16]: ieee_link_id, protocol link id on which the rx frame is received + * [27:19]: reserved + * [31:28]: subtype, subtype of the received MGMT frame + */ + u32 peer_info_subtype; + u32 chan_freq; /* frequency in MHz of the channel on which this frame was received */ + /* Timestamp (in micro sec) of the last fw consumed/dropped mgmt. frame, same across chips */ + u32 global_timestamp; + /** + * mgmt_pkt_ctr_info + * + * [14:0]: reserved + * [15]: mgmt_pkt_ctr_valid + * [31:16]: mgmt_pkt_ctr, Sequence number of the last fw consumed mgmt frame + */ + u32 mgmt_pkt_ctr_info; + u32 rx_ppdu_duration_us; /* receive duration in us */ + u32 mpdu_end_timestamp; /* mpdu end timestamp in us (based on HWMLO timer) */ +}; + +#define WMI_MGMT_RX_REO_PARAM_IEEE_LINK_ID_GET GENMASK(14, 12) +#define WMI_MGMT_RX_REO_PARAM_MGMT_PKT_CTR_VALID_GET GENMASK(15, 15) +#define WMI_MGMT_RX_REO_PARAM_MGMT_PKT_CTR_GET GENMASK(31, 16) + +/** Data structure of the TLV to add in RX EVENTID for providing REO params + * like global_timestamp and mgmt_pkt_ctr + */ +struct ath12k_wmi_mgmt_rx_reo_params { + /* Timestamp (in micro sec) of the last fw forwarded mgmt. frame, same across chips */ + u32 global_timestamp; + /** + * mgmt_pkt_ctr_link_info + * + * [11:0]: reserved + * [14:12]: ieee_link_id, protocol link id on which the rx frame is received + * [15]: mgmt_pkt_ctr_valid + * [31:16]: mgmt_pkt_ctr, Sequence number of the last fw forwarded mgmt frame + */ + + u32 mgmt_pkt_ctr_link_info; + u32 rx_ppdu_duration_us; /* receive duration in us */ + u32 mpdu_end_timestamp; /* mpdu end timestamp in us (based on HWMLO timer) */ +}; + +/* struct ath12k_mgmt_rx_reo_params - MGMT Rx REO parameters + * @valid: Whether these params are valid + * @pdev_id: pdev ID for which FW consumed event is received + * @link_id: link ID for which FW consumed event is received + * @mgmt_pkt_ctr: MGMT packet counter of the frame that is consumed + * @global_timestamp: Global timestamp of the frame that is consumed + * @duration_us: duration in us + * @start_timestamp: start time stamp + * @end_timestamp: end time stamp + */ +struct ath12k_mgmt_rx_reo_params { + bool valid; + u8 pdev_id; + u8 link_id; + u8 mlo_grp_id; + u16 mgmt_pkt_ctr; + u32 global_timestamp; + u16 duration_us; + u32 start_timestamp; + u32 end_timestamp; +}; + +/* struct ath12k_mgmt_rx_reo_filter - MGMT Rx REO filter + * @filter_low: Least significant 32-bits of the filter + * @filter_high: Most significant 32-bits of the filter + */ +struct ath12k_mgmt_rx_reo_filter { + u32 low; + u32 high; +}; + +/* struct ath12k_mgmt_rx_reo_wait_count - Wait count for a mgmt frame + * @per_link_count: Array of wait counts for all MLO links. Each array entry + * holds the number of frames this mgmt frame should wait for on that + * particular link. + * @total_count: Sum of entries in @per_link_count + */ +struct ath12k_mgmt_rx_reo_wait_count { + unsigned int per_link_count[ATH12K_WMI_MLO_MAX_LINKS]; + unsigned long long total_count; +}; + +/* struct ath12k_mgmt_rx_reo_snapshot_params - Represents the simplified version of + * Management Rx Frame snapshot for Host use. Note that this is different from + * the structure shared between the Host and FW/HW + * @valid: Whether this snapshot is valid + * @retry_count: snapshot read retry count + * @mgmt_pkt_ctr: MGMT packet counter. This will be local to a particular + * HW link + * @global_timestamp: Global timestamp.This is taken from a clock which is + * common across all the HW links + */ +struct ath12k_mgmt_rx_reo_snapshot_params { + bool valid; + u8 retry_count; + u16 mgmt_pkt_ctr; + u32 global_timestamp; +}; + +/* struct ath12k_mgmt_rx_reo_shared_snapshot - Represents the management rx-reorder + * shared snapshots + * @ath12k_mgmt_rx_reo_snapshot_low: Lower 32 bits of the reo snapshot + * @ath12k_mgmt_rx_reo_snapshot_high: Higher 32 bits of the reo snapshot + */ +struct ath12k_mgmt_rx_reo_shared_snapshot { + union { + u32 ath12k_mgmt_rx_reo_snapshot_low; + u32 mgmt_pkt_ctr_ver_a:16, + global_timestamp_redundant_ver_a:15, + valid_ver_a:1; + u32 global_timestamp_low_ver_b:15, + mgmt_pkt_ctr_ver_b:16, + valid_ver_b:1; + } u_low; + + union { + u32 ath12k_mgmt_rx_reo_snapshot_high; + u32 global_timestamp_ver_a; + u32 mgmt_pkt_ctr_redundant_ver_b:15, + global_timestamp_high_ver_b:17; + } u_high; +}; + +/* struct ath12k_mgmt_rx_reo_snapshot_info - Information related to management Rx + * reorder snapshot + * @address: Snapshot address + * @version: Snapshot version + */ +struct ath12k_mgmt_rx_reo_snapshot_info { + struct ath12k_mgmt_rx_reo_shared_snapshot *address; + u8 version; +}; + +#define ATH12K_MGMT_RX_REO_SNAPSHOT_B2B_READ_SWAR_RETRY_LIMIT (11) +#define ATH12K_MGMT_RX_REO_SNAPSHOT_READ_RETRY_LIMIT (25) + +/* enum ath12k_mgmt_rx_reo_shared_snapshot_id - Represents the management + * rx-reorder snapshots shared between host and target in the host DDR. + * These snapshots are written by FW/HW and read by Host. + * @ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_CONSUMED: FW consumed snapshot + * @ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_FORWARDED: FW forwarded snapshot + * @ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAC_HW: MAC HW snapshot + * @ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX: Max number of snapshots + * @ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_INVALID: Invalid snapshot + */ +enum ath12k_mgmt_rx_reo_shared_snapshot_id { + ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_CONSUMED = 0, + ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_FW_FORWARDED = 1, + ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAC_HW = 2, + ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX = 3, + ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_INVALID, +}; + +/* struct ath12k_mgmt_rx_reo_pdev_info - Pdev information required by the Management + * Rx REO module + * @host_snapshot: Latest snapshot seen at the Host. + * It considers both MGMT Rx and MGMT FW consumed. + * @last_valid_shared_snapshot: Array of last valid snapshots(for snapshots + * shared between host and target) + * @host_target_shared_snapshot_info: Array of meta information related to + * snapshots(for snapshots shared between host and target) + * @filter: MGMT Rx REO filter + * @init_complete: Flag to indicate initialization completion of the + * ath12k_mgmt_rx_reo_pdev_info object + */ +struct ath12k_mgmt_rx_reo_pdev_info { + struct ath12k_mgmt_rx_reo_snapshot_params host_snapshot; + struct ath12k_mgmt_rx_reo_snapshot_params last_valid_shared_snapshot + [ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX]; + struct ath12k_mgmt_rx_reo_snapshot_info host_target_shared_snapshot_info + [ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX]; + struct ath12k_mgmt_rx_reo_filter filter; + struct ath12k_mgmt_rx_reo_shared_snapshot raw_snapshots[ATH12K_WMI_MLO_MAX_LINKS] + [ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX] + [ATH12K_MGMT_RX_REO_SNAPSHOT_READ_RETRY_LIMIT] + [ATH12K_MGMT_RX_REO_SNAPSHOT_B2B_READ_SWAR_RETRY_LIMIT]; + bool init_complete; +}; + +/* enum ath12k_mgmt_rx_reo_frame_descriptor_type - Enumeration for management frame + * descriptor type. + * @ATH12K_MGMT_RX_REO_FRAME_DESC_HOST_CONSUMED_FRAME: Management frame to be consumed + * by host. + * @ATH12K_MGMT_RX_REO_FRAME_DESC_FW_CONSUMED_FRAME: Management frame consumed by FW + * @ATH12K_MGMT_RX_REO_FRAME_DESC_ERROR_FRAME: Management frame which got dropped + * at host due to any error + * @ATH12K_MGMT_RX_REO_FRAME_DESC_TYPE_MAX: Maximum number of frame types + */ +enum ath12k_mgmt_rx_reo_frame_descriptor_type { + ATH12K_MGMT_RX_REO_FRAME_DESC_HOST_CONSUMED_FRAME = 0, + ATH12K_MGMT_RX_REO_FRAME_DESC_FW_CONSUMED_FRAME, + ATH12K_MGMT_RX_REO_FRAME_DESC_ERROR_FRAME, + ATH12K_MGMT_RX_REO_FRAME_DESC_TYPE_MAX, +}; + +/* struct ath12k_mgmt_rx_reo_global_ts_info - This structure holds the global time + * stamp information of a frame. + * @valid: Indicates whether global time stamp is valid + * @global_ts: Global time stamp value + * @start_ts: Start time stamp value + * @end_ts: End time stamp value + * @expiry_time: information in the structure is valid until expiry_time + */ +struct ath12k_mgmt_rx_reo_global_ts_info { + bool valid; + u32 global_ts; + u32 start_ts; + u32 end_ts; + unsigned long expiry_time; +}; + +/* struct ath12k_reo_ingress_debug_frame_info - Debug information about a frame + * entering reorder process + * @link_id: link id + * @mgmt_pkt_ctr: management packet counter + * @global_timestamp: MLO global time stamp + * @start_timestamp: start time stamp of the frame + * @end_timestamp: end time stamp of the frame + * @duration_us: duration of the frame in us + * @desc_type: Type of the frame descriptor + * @frame_type: frame type + * @frame_subtype: frame sub type + * @ingress_timestamp: Host time stamp when the frames enters the reorder + * process + * @ingress_duration: Duration in us for processing the incoming frame. + * ingress_duration = Time stamp at which reorder list update is done - + * Time stamp at which frame has entered the reorder module + * @wait_count: Wait count calculated for the current frame + * @is_queued: Indicates whether this frame is queued to reorder list + * @is_stale: Indicates whether this frame is stale. + * @is_parallel_rx: Indicates that this frame is received in parallel to the + * last frame which is delivered to the upper layer. + * @zero_wait_count_rx: Indicates whether this frame's wait count was + * zero when received by host + * @immediate_delivery: Indicates whether this frame can be delivered + * immediately to the upper layers + * @is_error: Indicates whether any error occurred during processing this frame + * @ts_last_released_frame: Stores the global time stamp for the last frame + * removed from the reorder list + * @list_size_rx: Size of the reorder list when this frame is received (before + * updating the list based on this frame). + * @list_insertion_pos: Position in the reorder list where this frame is going + * to get inserted (Applicable for only host consumed frames) + * @shared_snapshots: snapshots shared b/w host and target + * @host_snapshot: host snapshot + * @cpu_id: CPU index + * @reo_required: Indicates whether reorder is required for the current frame. + * If reorder is not required, current frame will just be used for updating the + * wait count of frames already part of the reorder list. + */ +struct ath12k_reo_ingress_debug_frame_info { + u8 link_id; + u16 mgmt_pkt_ctr; + u32 global_timestamp; + u32 start_timestamp; + u32 end_timestamp; + u32 duration_us; + enum ath12k_mgmt_rx_reo_frame_descriptor_type desc_type; + u8 frame_type; + u8 frame_subtype; + u64 ingress_timestamp; + u64 ingress_duration; + struct ath12k_mgmt_rx_reo_wait_count wait_count; + bool is_queued; + bool is_stale; + bool is_parallel_rx; + bool zero_wait_count_rx; + bool immediate_delivery; + bool is_error; + struct ath12k_mgmt_rx_reo_global_ts_info ts_last_released_frame; + s16 list_size_rx; + s16 list_insertion_pos; + struct ath12k_mgmt_rx_reo_snapshot_params shared_snapshots + [ATH12K_WMI_MLO_MAX_LINKS][ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX]; + struct ath12k_mgmt_rx_reo_snapshot_params host_snapshot[ATH12K_WMI_MLO_MAX_LINKS]; + int cpu_id; + bool reo_required; +}; + +/* struct ath12k_reo_ingress_frame_stats - Structure to store statistics related to + * incoming frames + * @ingress_count: Number of frames entering reo module + * @queued_count: Number of frames queued to reorder list + * @zero_wait_count_rx_count: Number of frames for which wait count is + * zero when received at host + * @immediate_delivery_count: Number of frames which can be delivered + * immediately to the upper layers without reordering. A frame can be + * immediately delivered if it has wait count of zero on reception at host + * and the global time stamp is less than or equal to the global time + * stamp of all the frames in the reorder list. Such frames would get + * inserted to the head of the reorder list and gets delivered immediately + * to the upper layers. + * @stale_count: Number of stale frames. Any frame older than the + * last frame delivered to upper layer is a stale frame. + * @error_count: Number of frames dropped due to error occurred + * within the reorder module + */ +struct ath12k_reo_ingress_frame_stats { + u64 ingress_count + [ATH12K_WMI_MLO_MAX_LINKS][ATH12K_MGMT_RX_REO_FRAME_DESC_TYPE_MAX]; + u64 queued_count[ATH12K_WMI_MLO_MAX_LINKS]; + u64 zero_wait_count_rx_count[ATH12K_WMI_MLO_MAX_LINKS]; + u64 immediate_delivery_count[ATH12K_WMI_MLO_MAX_LINKS]; + u64 stale_count[ATH12K_WMI_MLO_MAX_LINKS] + [ATH12K_MGMT_RX_REO_FRAME_DESC_TYPE_MAX]; + u64 error_count[ATH12K_WMI_MLO_MAX_LINKS] + [ATH12K_MGMT_RX_REO_FRAME_DESC_TYPE_MAX]; +}; + +#define ATH12K_MGMT_RX_REO_INGRESS_FRAME_DEBUG_INFO_BOARDER_MAX_SIZE (785) + +/* struct reo_ingress_debug_info - Circular array to store the + * debug information about the frames entering the reorder process. + * @frame_list: Circular array to store the debug info about frames + * @frame_list_size: Size of circular array @frame_list + * @next_index: The index at which information about next frame will be logged + * @wrap_aroud: Flag to indicate whether wrap around occurred when logging + * debug information to @frame_list + * @stats: Stats related to incoming frames + * @boarder: boarder string + */ +struct reo_ingress_debug_info { + struct ath12k_reo_ingress_debug_frame_info *frame_list; + u16 frame_list_size; + int next_index; + bool wrap_aroud; + struct ath12k_reo_ingress_frame_stats stats; + char boarder[ATH12K_MGMT_RX_REO_INGRESS_FRAME_DEBUG_INFO_BOARDER_MAX_SIZE + 1]; +}; + +/* struct ath12k_reo_egress_debug_frame_info - Debug information about a frame + * leaving the reorder module + * @is_delivered: Indicates whether the frame is delivered to upper layers + * @is_premature_delivery: Indicates whether the frame is delivered + * prematurely + * @link_id: link id + * @mgmt_pkt_ctr: management packet counter + * @global_timestamp: MLO global time stamp + * @ingress_timestamp: Host time stamp when the frame enters the reorder module + * @insertion_ts: Host time stamp when the frame is inserted into the reorder + * list + * @egress_timestamp: Host time stamp just before delivery of the frame to upper + * layer + * @egress_duration: Duration in us taken by the upper layer to process + * the frame. + * @removal_ts: Host time stamp when this entry is removed from the list + * @initial_wait_count: Wait count when the frame is queued + * @final_wait_count: Wait count when frame is released to upper layer + * @release_reason: Reason for delivering the frame to upper layers + * @shared_snapshots: snapshots shared b/w host and target + * @host_snapshot: host snapshot + * @cpu_id: CPU index + */ +struct ath12k_reo_egress_debug_frame_info { + bool is_delivered; + bool is_premature_delivery; + u8 link_id; + u16 mgmt_pkt_ctr; + u32 global_timestamp; + u64 ingress_timestamp; + u64 insertion_ts; + u64 egress_timestamp; + u64 egress_duration; + u64 removal_ts; + struct ath12k_mgmt_rx_reo_wait_count initial_wait_count; + struct ath12k_mgmt_rx_reo_wait_count final_wait_count; + u8 release_reason; + struct ath12k_mgmt_rx_reo_snapshot_params shared_snapshots + [ATH12K_WMI_MLO_MAX_LINKS][ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX]; + struct ath12k_mgmt_rx_reo_snapshot_params host_snapshot[ATH12K_WMI_MLO_MAX_LINKS]; + int cpu_id; +}; + +/* Reason to release an entry from the reorder list */ +#define MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_ZERO_WAIT_COUNT (BIT(0)) +#define MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_AGED_OUT (BIT(1)) +#define MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_OLDER_THAN_AGED_OUT_FRAME (BIT(2)) +#define MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_LIST_MAX_SIZE_EXCEEDED (BIT(3)) +#define MGMT_RX_REO_RELEASE_REASON_MAX \ + (MGMT_RX_REO_LIST_ENTRY_RELEASE_REASON_LIST_MAX_SIZE_EXCEEDED << 1) + +/** + * struct reo_egress_frame_stats - Structure to store statistics related to + * outgoing frames + * @delivery_attempts_count: Number of attempts to deliver management + * frames to upper layers + * @delivery_success_count: Number of successful management frame + * deliveries to upper layer + * @premature_delivery_count: Number of frames delivered + * prematurely. Premature delivery is the delivery of a management frame + * to the upper layers even before its wait count is reaching zero. + * @delivery_count: Number frames delivered successfully for + * each link and release reason. + */ +struct reo_egress_frame_stats { + u64 delivery_attempts_count[ATH12K_WMI_MLO_MAX_LINKS]; + u64 delivery_success_count[ATH12K_WMI_MLO_MAX_LINKS]; + u64 premature_delivery_count[ATH12K_WMI_MLO_MAX_LINKS]; + u64 delivery_count[ATH12K_WMI_MLO_MAX_LINKS] + [MGMT_RX_REO_RELEASE_REASON_MAX]; +}; + +#define ATH12K_MGMT_RX_REO_EGRESS_FRAME_DEBUG_INFO_BOARDER_MAX_SIZE (816) + +/** + * struct ath12k_reo_egress_debug_info - Circular array to store the + * debug information about the frames leaving the reorder module. + * @frame_list: Circular array to store the debug info + * @frame_list_size: Size of circular array @frame_list + * @next_index: The index at which information about next frame will be logged + * @wrap_aroud: Flag to indicate whether wrap around occurred when logging + * debug information to @frame_list + * @stats: Stats related to outgoing frames + * @boarder: boarder string + */ +struct ath12k_reo_egress_debug_info { + struct ath12k_reo_egress_debug_frame_info *frame_list; + u16 frame_list_size; + int next_index; + bool wrap_aroud; + struct reo_egress_frame_stats stats; + char boarder[ATH12K_MGMT_RX_REO_EGRESS_FRAME_DEBUG_INFO_BOARDER_MAX_SIZE + 1]; +}; + +/** + * struct mgmt_rx_reo_list – Linked list used to reorder the management frames + * received. Each list entry would correspond to a management frame. List + * entries would be sorted in the same order in which they are received by MAC + * HW. + * @list: List used for reordering + * @list_lock: Lock to protect the list + * @max_list_size: Maximum size of the reorder list + * @list_entry_timeout_us: Time out value(microsecond) for the reorder list + * entries + * @ageout_timer: Periodic timer to age-out the list entries + * @global_mgmt_rx_inactivity_timer: Global management Rx inactivity timer + * @ts_last_released_frame: Stores the global time stamp for the last frame + * removed from the reorder list + */ +struct mgmt_rx_reo_list { + struct ath12k_base *ab; + struct list_head list; + int count; + /* protects the list used for reordering */ + spinlock_t list_lock; + u32 max_list_size; + u32 list_entry_timeout_us; + struct timer_list ageout_timer; + struct timer_list global_mgmt_rx_inactivity_timer; + struct ath12k_mgmt_rx_reo_global_ts_info ts_last_released_frame; +}; + +/** + * struct ath12k_mgmt_rx_reo_context - This structure holds the info required for + * management rx-reordering. Reordering is done across all the psocs. + * So there should be only one instance of this structure defined. + * @reo_list: Linked list used for reordering + * @rx_reorder_entry_lock: Spin lock to protect rx reorder process entry critical + * section execution + * @frame_release_lock: Spin lock to serialize the frame delivery to the + * upper layers. This could prevent race conditions like the one given in + * the following example. + * Lets take an example of 2 links (Link A & B) and each has received + * a management frame A1(deauth) and B1(auth) such that MLO global time + * stamp of A1 < MLO global time stamp of B1. Host is concurrently + * executing "mgmt_rx_reo_list_release_entries" for A1 and B1 in + * 2 different CPUs. It is possible that frame B1 gets processed by + * upper layers before frame A1 and this could result in unwanted + * disconnection. Hence it is required to serialize the delivery + * of management frames to upper layers in the strict order of MLO + * global time stamp. + * @sim_context: Management rx-reorder simulation context + * @ingress_debug_info_init_count: Initialization count of + * object @ingress_frame_debug_info + * @ingress_frame_debug_info: Debug object to log incoming frames + * @egress_frame_debug_info: Debug object to log outgoing frames + * @egress_debug_info_init_count: Initialization count of + * object @egress_frame_debug_info + * @simulation_in_progress: Flag to indicate whether simulation is + * in progress + * @init_done: This will indicate intialization of management rx-reorder list. + * @timer_init_done: This will indicate firing of management rx-reorder timer. + */ +struct ath12k_mgmt_rx_reo_context { + struct mgmt_rx_reo_list reo_list; + /* Protects the rx reorder process entry critical section exec */ + spinlock_t rx_reorder_entry_lock; + /* Lock to Serialize the frame delivery */ + spinlock_t frame_release_lock; + atomic_t ingress_debug_info_init_count; + struct reo_ingress_debug_info ingress_frame_debug_info; + atomic_t egress_debug_info_init_count; + struct ath12k_reo_egress_debug_info egress_frame_debug_info; + bool init_done; + bool timer_init_done; +}; + +/** MGMT RX REO Changes */ +/* Macros for having versioning info for compatibility check between host and firmware */ +#define MLO_SHMEM_MAJOR_VERSION 2 +#define MLO_SHMEM_MINOR_VERSION 1 + +/** + * Enum which defines different versions of management Rx reorder snapshots. + */ +enum { + /** + * DWORD Lower: + * [15:0] : Management packet counter + * [30:16] : Redundant global time stamp = Global time stamp[14:0] + * [31] : Valid + * + * DWORD Upper: + * [31:0] : Global time stamp + * + */ + MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY = 0, + + /** + * DWORD Lower: + * [14:0] : Global time stamp[14:0] + * [30:15] : Management packet counter + * [31] : Valid + * + * DWORD Upper: + * [14:0] : Redundant management packet counter = Management packet + * counter[14:0] + * [31:15] : Global time stamp[31:15] + */ + MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY = 1, +}; + +#define ATH12K_MGMT_RX_REO_INVALID_SNAPSHOT_VERSION (-1) + +/** + * struct mgmt_rx_reo_list_entry - Entry in the Management reorder list + * @node: List node + * @nbuf: nbuf corresponding to this frame + * @rx_params: Management rx event parameters + * @wait_count: Wait counts for the frame + * @initial_wait_count: Wait count when the frame is queued + * @insertion_ts: Host time stamp when this entry is inserted to the list. + * @removal_ts: Host time stamp when this entry is removed from the list + * @ingress_timestamp: Host time stamp when this frame has arrived reorder + * module + * @egress_timestamp: Host time stamp when this frame has exited reorder + * module + * @status: Status for this entry + * @pdev: Pointer to pdev object corresponding to this frame + * @release_reason: Release reason + * @is_delivered: Indicates whether the frame is delivered successfully + * @is_premature_delivery: Indicates whether the frame is delivered + * prematurely + * @is_parallel_rx: Indicates that this frame is received in parallel to the + * last frame which is delivered to the upper layer. + * @shared_snapshots: snapshots shared b/w host and target + * @host_snapshot: host snapshot + */ +struct mgmt_rx_reo_list_entry { + struct list_head node; + struct sk_buff *nbuf; + struct ath12k_wmi_mgmt_rx_arg *rx_params; + struct ath12k_mgmt_rx_reo_wait_count wait_count; + struct ath12k_mgmt_rx_reo_wait_count initial_wait_count; + u64 insertion_ts; + u64 removal_ts; + u64 ingress_timestamp; + u64 egress_timestamp; + u32 status; + struct ath12k *ar; + u8 release_reason; + bool is_delivered; + bool is_premature_delivery; + bool is_parallel_rx; + struct ath12k_mgmt_rx_reo_snapshot_params shared_snapshots + [ATH12K_WMI_MLO_MAX_LINKS][ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX]; + struct ath12k_mgmt_rx_reo_snapshot_params host_snapshot[ATH12K_WMI_MLO_MAX_LINKS]; +}; + +#define ATH12K_MGMT_RX_REO_STATUS_WAIT_FOR_FRAME_ON_OTHER_LINKS (BIT(0)) +#define ATH12K_MGMT_RX_REO_STATUS_AGED_OUT (BIT(1)) +#define ATH12K_MGMT_RX_REO_STATUS_OLDER_THAN_LATEST_AGED_OUT_FRAME (BIT(2)) +#define ATH12K_MGMT_RX_REO_STATUS_LIST_MAX_SIZE_EXCEEDED (BIT(3)) + +#define ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_WAITING_FOR_FRAME_ON_OTHER_LINK(entry) \ + ((entry)->status & ATH12K_MGMT_RX_REO_STATUS_WAIT_FOR_FRAME_ON_OTHER_LINKS) +#define ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_AGED_OUT(entry) \ + ((entry)->status & ATH12K_MGMT_RX_REO_STATUS_AGED_OUT) +#define ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_OLDER_THAN_LATEST_AGED_OUT_FRAME(entry) \ + ((entry)->status & ATH12K_MGMT_RX_REO_STATUS_OLDER_THAN_LATEST_AGED_OUT_FRAME) +#define ATH12K_MGMT_RX_REO_LIST_ENTRY_IS_MAX_SIZE_EXCEEDED(entry) \ + ((entry)->status & ATH12K_MGMT_RX_REO_STATUS_LIST_MAX_SIZE_EXCEEDED) + +#define ATH12K_MGMT_RX_REO_GLOBAL_MGMT_RX_INACTIVITY_TIMEOUT (600 * HZ) +#define ATH12K_MGMT_RX_REO_LIST_MAX_SIZE (100) +#define ATH12K_MGMT_RX_REO_LIST_TIMEOUT_US (500000) +#define ATH12K_MGMT_RX_REO_AGEOUT_TIMER_PERIOD_MS (250) + +#define ATH12K_MGMT_RX_REO_PKT_CTR_HALF_RANGE (0x8000) +#define ATH12K_MGMT_RX_REO_PKT_CTR_FULL_RANGE (ATH12K_MGMT_RX_REO_PKT_CTR_HALF_RANGE << 1) + +#define CU_VDEV_MAP_LB GENMASK(15, 0) +#define CU_VDEV_MAP_HB GENMASK(31, 16) +/* Maximum number of CU LINKS across the system. + * this is not the CU links within an AP MLD. + */ +#define CU_MAX_MLO_LINKS 8 +#define MAX_AP_MLDS_PER_LINK 16 + +struct ath12k_wmi_mgmt_rx_cu_params { + /* CU vdev map to intimate about the on-going Critical update + * per-link contains 16 VAPs at max. + */ + + /* bits : 0-15 | 16-31 + * link-id : 0 | 1 + */ + __le32 cu_vdev_map_1; + /* bits : 0-15 | 16-31 + * link-id : 2 | 3 + */ + __le32 cu_vdev_map_2; + /* bits : 0-15 | 16-31 + * link-id : 4 | 5 + */ + __le32 cu_vdev_map_3; + /* bits : 0-15 | 16-31 + * link-id : 6 | 7 + */ + __le32 cu_vdev_map_4; /* bits 63:32 */ +}; + +struct ath12k_mgmt_rx_cu_arg { + u16 cu_vdev_map[CU_MAX_MLO_LINKS]; + u8 *bpcc_bufp; +}; + struct ath12k_wmi_mgmt_rx_arg { u32 chan_freq; u32 channel; @@ -4028,6 +6418,61 @@ int rssi; u32 tsf_delta; u8 pdev_id; + struct ath12k_mgmt_rx_reo_params reo_params; +}; + +/** + * struct ath12k_mgmt_rx_reo_frame_descriptor - Frame Descriptor used to describe + * a management frame in mgmt rx reo module. + * @type: Frame descriptor type + * @frame_type: frame type + * @frame_subtype: frame subtype + * @nbuf: nbuf corresponding to this frame + * @rx_params: Management rx event parameters + * @wait_count: Wait counts for the frame + * @ingress_timestamp: Host time stamp when the frames enters the reorder + * process + * @is_stale: Indicates whether this frame is stale. Any frame older than the + * last frame delivered to upper layer is a stale frame. Stale frames should not + * be delivered to the upper layers. These frames can be discarded after + * updating the host snapshot and wait counts of entries currently residing in + * the reorder list. + * @zero_wait_count_rx: Indicates whether this frame's wait count was + * zero when received by host + * @immediate_delivery: Indicates whether this frame can be delivered + * immediately to the upper layers + * @list_size_rx: Size of the reorder list when this frame is received (before + * updating the list based on this frame). + * @list_insertion_pos: Position in the reorder list where this frame is going + * to get inserted (Applicable for only host consumed frames) + * @shared_snapshots: snapshots shared b/w host and target + * @host_snapshot: host snapshot + * @is_parallel_rx: Indicates that this frame is received in parallel to the + * last frame which is delivered to the upper layer. + * @pkt_ctr_delta: Packet counter delta of the current and last frame + * @reo_required: Indicates whether reorder is required for the current frame. + * If reorder is not required, current frame will just be used for updating the + * wait count of frames already part of the reorder list. + */ +struct ath12k_mgmt_rx_reo_frame_descriptor { + enum ath12k_mgmt_rx_reo_frame_descriptor_type type; + u8 frame_type; + u8 frame_subtype; + struct sk_buff *nbuf; + struct ath12k_wmi_mgmt_rx_arg *rx_params; + struct ath12k_mgmt_rx_reo_wait_count wait_count; + u64 ingress_timestamp; + bool is_stale; + bool zero_wait_count_rx; + bool immediate_delivery; + s16 list_size_rx; + s16 list_insertion_pos; + struct ath12k_mgmt_rx_reo_snapshot_params shared_snapshots + [ATH12K_WMI_MLO_MAX_LINKS][ATH12K_MGMT_RX_REO_SHARED_SNAPSHOT_MAX]; + struct ath12k_mgmt_rx_reo_snapshot_params host_snapshot[ATH12K_WMI_MLO_MAX_LINKS]; + bool is_parallel_rx; + int pkt_ctr_delta; + bool reo_required; }; #define ATH_MAX_ANTENNA 4 @@ -4055,6 +6500,8 @@ __le32 desc_id; __le32 status; __le32 pdev_id; + __le32 ppdu_id; + __le32 ack_rssi; } __packed; struct wmi_scan_event { @@ -4072,12 +6519,33 @@ __le32 tsf_timestamp; } __packed; +struct wmi_offchan_data_tx_compl_event { + __le32 desc_id; + __le32 status; + __le32 pdev_id; + __le32 ppdu_id; +} __packed; + +enum wmi_peer_sta_kickout_reason { + WMI_PEER_STA_KICKOUT_REASON_UNSPECIFIED = 0, + WMI_PEER_STA_KICKOUT_REASON_XRETRY = 1, + WMI_PEER_STA_KICKOUT_REASON_INACTIVITY = 2, + WMI_PEER_STA_KICKOUT_REASON_IBSS_DISCONNECT = 3, + WMI_PEER_STA_KICKOUT_REASON_TDLS_DISCONNECT = 4, + WMI_PEER_STA_KICKOUT_REASON_SA_QUERY_TIMEOUT = 5, + WMI_PEER_STA_KICKOUT_REASON_ROAMING_EVENT = 6, +}; + struct wmi_peer_sta_kickout_arg { - const u8 *mac_addr; + u8 mac_addr[ETH_ALEN]; + __le32 reason; + __le32 rssi; }; struct wmi_peer_sta_kickout_event { struct ath12k_wmi_mac_addr_params peer_macaddr; + __le32 reason; + __le32 rssi; } __packed; enum wmi_roam_reason { @@ -4138,6 +6606,7 @@ }; enum wmi_vdev_type { + WMI_VDEV_TYPE_UNSPEC = 0, WMI_VDEV_TYPE_AP = 1, WMI_VDEV_TYPE_STA = 2, WMI_VDEV_TYPE_IBSS = 3, @@ -4262,7 +6731,7 @@ #define DISABLE_SIFS_RESPONSE_TRIGGER 0 -#define WMI_MAX_KEY_INDEX 3 +#define WMI_MAX_KEY_INDEX 7 #define WMI_MAX_KEY_LEN 32 enum wmi_key_type { @@ -4304,6 +6773,7 @@ WMI_RATE_PREAMBLE_HT, WMI_RATE_PREAMBLE_VHT, WMI_RATE_PREAMBLE_HE, + WMI_RATE_PREAMBLE_EHT, }; /** @@ -4353,6 +6823,119 @@ ATH12K_HW_TXRX_ETHERNET = 2, }; +enum wmi_coex_config_type { + WMI_COEX_CONFIG_PAGE_P2P_TDM = 1, + WMI_COEX_CONFIG_PAGE_STA_TDM = 2, + WMI_COEX_CONFIG_PAGE_SAP_TDM = 3, + WMI_COEX_CONFIG_DURING_WLAN_CONN = 4, + WMI_COEX_CONFIG_BTC_ENABLE = 5, + WMI_COEX_CONFIG_COEX_DBG = 6, + WMI_COEX_CONFIG_PAGE_P2P_STA_TDM = 7, + WMI_COEX_CONFIG_INQUIRY_P2P_TDM = 8, + WMI_COEX_CONFIG_INQUIRY_STA_TDM = 9, + WMI_COEX_CONFIG_INQUIRY_SAP_TDM = 10, + WMI_COEX_CONFIG_INQUIRY_P2P_STA_TDM = 11, + WMI_COEX_CONFIG_TX_POWER = 12, + WMI_COEX_CONFIG_PTA_CONFIG = 13, + WMI_COEX_CONFIG_AP_TDM = 14, + WMI_COEX_CONFIG_WLAN_SCAN_PRIORITY = 15, + WMI_COEX_CONFIG_WLAN_PKT_PRIORITY = 16, + WMI_COEX_CONFIG_PTA_INTERFACE = 17, + WMI_COEX_CONFIG_THREE_WAY_COEX_RESET = 32, + WMI_COEX_CONFIG_THREE_WAY_COEX_START = 34, + /* WMI_COEX_CONFIG_FORCED_ALGO + * config to select coex algorithm + * coex_algo: select fixed coex algorithm + */ + WMI_COEX_CONFIG_FORCED_ALGO = 47, +}; + +struct coex_config_arg { + u32 vdev_id; + u32 config_type; + union { + struct { + u32 coex_enable; + }; + + struct { + u32 pta_num; + u32 coex_mode; + u32 bt_txrx_time; + u32 bt_priority_time; + u32 pta_algorithm; + u32 pta_priority; + }; + + struct { + u32 wlan_pkt_type; + u32 wlan_pkt_type_continued; + u32 wlan_pkt_weight; + u32 bt_pkt_weight; + }; + struct { + u32 duty_cycle; + u32 wlan_duration; + }; + struct { + u32 coex_algo; + }; + struct { + u32 priority0; + u32 priority1; + u32 priority2; + u32 config_arg4; + u32 config_arg5; + u32 config_arg6; + }; + }; +}; + +struct wmi_coex_config_cmd { + u32 tlv_header; + u32 vdev_id; + u32 config_type; + union { + struct { + u32 coex_enable; + } __packed; + + struct { + u32 pta_num; + u32 coex_mode; + u32 bt_txrx_time; + u32 bt_priority_time; + u32 pta_algorithm; + u32 pta_priority; + } __packed; + + struct { + u32 wlan_pkt_type; + u32 wlan_pkt_type_continued; + u32 wlan_pkt_weight; + u32 bt_pkt_weight; + } __packed; + + struct { + u32 duty_cycle; + u32 wlan_duration; + } __packed; + + struct { + u32 coex_algo; + } __packed; + + struct { + u32 priority0; + u32 priority1; + u32 priority2; + u32 config_arg4; + u32 config_arg5; + u32 config_arg6; + } __packed; + } __packed; +} __packed; + struct wmi_wmm_params { __le32 tlv_header; __le32 cwmin; @@ -4428,6 +7011,465 @@ __le32 pdev_id; } __packed; +enum WMI_HOST_TWT_COMMAND { + WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0, + WMI_HOST_TWT_COMMAND_SUGGEST_TWT, + WMI_HOST_TWT_COMMAND_DEMAND_TWT, + WMI_HOST_TWT_COMMAND_TWT_GROUPING, + WMI_HOST_TWT_COMMAND_ACCEPT_TWT, + WMI_HOST_TWT_COMMAND_ALTERNATE_TWT, + WMI_HOST_TWT_COMMAND_DICTATE_TWT, + WMI_HOST_TWT_COMMAND_REJECT_TWT, +}; + +#define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8) +#define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9) +#define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10) +#define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11) + +struct wmi_twt_add_dialog_params_cmd { + u32 tlv_header; + u32 vdev_id; + struct ath12k_wmi_mac_addr_params peer_macaddr; + u32 dialog_id; + u32 wake_intvl_us; + u32 wake_intvl_mantis; + u32 wake_dura_us; + u32 sp_offset_us; + u32 flags; +} __packed; + +struct wmi_twt_add_dialog_params { + u32 vdev_id; + u8 peer_macaddr[ETH_ALEN]; + u32 dialog_id; + u32 wake_intvl_us; + u32 wake_intvl_mantis; + u32 wake_dura_us; + u32 sp_offset_us; + u8 twt_cmd; + u8 flag_bcast; + u8 flag_trigger; + u8 flag_flow_type; + u8 flag_protection; +} __packed; + +enum wmi_twt_add_dialog_status { + WMI_ADD_TWT_STATUS_OK, + WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED, + WMI_ADD_TWT_STATUS_USED_DIALOG_ID, + WMI_ADD_TWT_STATUS_INVALID_PARAM, + WMI_ADD_TWT_STATUS_NOT_READY, + WMI_ADD_TWT_STATUS_NO_RESOURCE, + WMI_ADD_TWT_STATUS_NO_ACK, + WMI_ADD_TWT_STATUS_NO_RESPONSE, + WMI_ADD_TWT_STATUS_DENIED, + WMI_ADD_TWT_STATUS_UNKNOWN_ERROR, +}; + +struct wmi_twt_add_dialog_event { + u32 vdev_id; + struct ath12k_wmi_mac_addr_params peer_macaddr; + u32 dialog_id; + u32 status; +} __packed; + +struct wmi_twt_del_dialog_params { + u32 vdev_id; + u8 peer_macaddr[ETH_ALEN]; + u32 dialog_id; +} __packed; + +struct wmi_twt_del_dialog_params_cmd { + u32 tlv_header; + u32 vdev_id; + struct ath12k_wmi_mac_addr_params peer_macaddr; + u32 dialog_id; +} __packed; + +struct wmi_twt_pause_dialog_params { + u32 vdev_id; + u8 peer_macaddr[ETH_ALEN]; + u32 dialog_id; +} __packed; + +struct wmi_twt_pause_dialog_params_cmd { + u32 tlv_header; + u32 vdev_id; + struct ath12k_wmi_mac_addr_params peer_macaddr; + u32 dialog_id; +} __packed; + +struct wmi_twt_resume_dialog_params { + u32 vdev_id; + u8 peer_macaddr[ETH_ALEN]; + u32 dialog_id; + u32 sp_offset_us; + u32 next_twt_size; +} __packed; + +struct wmi_twt_resume_dialog_params_cmd { + u32 tlv_header; + u32 vdev_id; + struct ath12k_wmi_mac_addr_params peer_macaddr; + u32 dialog_id; + u32 sp_offset_us; + u32 next_twt_size; +} __packed; + +struct wmi_sawf_svc_cfg_cmd_fixed_param { + u32 tlv_header; /* TLV tag and len */ + /* Tag equals WMI_TAG_SAWF_SERVICE_CLASS_CFG_CMD_FIXED_PARAM */ + u32 svc_class_id; /* which service class is being configured */ + /*----- + * The below fields specify the values for the parameters of the + * service class being configured. + * Each such service class parameter has a default value specified in the + * above WMI_SAWF_SVC_CLASS_PARAM_DEFAULTS enum. + * This default value shall be specified for service classes where + * the parameter in question is not applicable. + * For example, for service classes that have no minimum throughput + * requirement, the min_thruput_kbps field should be set to + * WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MIN_THRUPUT, i.e. 0. + *----- + */ + /* min_thruput_kbps: + * How much throughput should be "guaranteed" for each MSDU queue + * belonging to this service class. + * Units are kilobits per second. + */ + u32 min_thruput_kbps; + /* max_thruput_kbps: + * What upper limit on throughput shall be applied to MSDU queues beloning + * to this service class, if other peer-TIDs are not meeting their QoS + * service goals. + * Units are kilobits per second. + */ + u32 max_thruput_kbps; + /* burst_size_bytes: + * How much data (i.e. how many MSDUs) should be pulled from a + * MSDU queue belonging to this service class to be formed into MPDUs + * and enqueued for transmission. + * Similarly, how long should a tx op be for MPDUs containing MSDUs from + * this service class, to ensure that the necessary amount of data gets + * delivered to the peer. + * Units are bytes. + */ + u32 burst_size_bytes; + /* svc_interval_ms: + * How frequently MSDUs belonging to this service class should be + * formed into MPDUs and enqueued for transmission. + * The svc_interval_ms parameter is expected to be <= the delay_bound_ms + * parameter. + * Units are milliseconds. + */ + u32 svc_interval_ms; + /* delay_bound_ms: + * How promptly the MSDUs belonging to this service class need to be + * delivered to the recipient peer. + * Units are milliseconds. + */ + u32 delay_bound_ms; + /* time_to_live_ms: + * How long MSDUs belonging to this service class remain valid. + * If the MSDU has not been successfully transmitted before this + * time-to-live time has elapsed, the MSDU should be discarded. + * The time_to_live_ms parameter is expected to be >= the delay_bound_ms + * parameter. + * Units are milliseconds. + */ + u32 time_to_live_ms; + /* priority: + * What degree of precedence shall the WLAN FW's tx scheduler use + * when considering whether to transmit MPDUs generated from MSDUs + * belonging to this service class. + */ + u32 priority; + /* tid: + * Which WLAN TID shall be used for delivering traffic of this + * service class. + */ + u32 tid; + /* msdu_loss_rate_ppm: + * This parameter indicates the acceptable rate of MSDU loss. + * Units are parts per million. + * E.g. if it is acceptable for 1 MSDU of every 10000 to be lost, + * the msdu_loss_rate_ppm value would be 100, + * since 100 / 1000000 = 1 / 10000. + */ + u32 msdu_loss_rate_ppm; +} __packed; + +struct wmi_sawf_svc_disable_cmd_fixed_param { + u32 tlv_header; /* TLV tag and len*/ + /* Tag equals WMI_TAG_SAWF_SERVICE_CLASS_DISABLE_CMD_FIXED_PARAM*/ + u32 svc_class_id; /* which service class is being disabled */ +} __packed; + +/** + * WMI arrays of length WMI_MGMT_FRAME_SUBTYPE_MAX use the + * IEEE802.11 standard's enumeration of mgmt frame subtypes: + * 0 -> IEEE80211_STYPE_FC0_SUBTYPE_ASSOC_REQ + * 1 -> IEEE80211_STYPE_FC0_SUBTYPE_ASSOC_RESP + * 2 -> IEEE80211_STYPE_FC0_SUBTYPE_REASSOC_REQ + * 3 -> IEEE80211_STYPE_FC0_SUBTYPE_REASSOC_RESP + * 4 -> IEEE80211_STYPE_FC0_SUBTYPE_PROBE_REQ + * 5 -> IEEE80211_STYPE_FC0_SUBTYPE_PROBE_RESP + * 6 -> Reserved + * 7 -> Reserved + * 8 -> IEEE80211_STYPE_FC0_SUBTYPE_BEACON + * 9 -> IEEE80211_STYPE_FC0_SUBTYPE_ATIM + * 10 -> IEEE80211_STYPE_FC0_SUBTYPE_DISASSOC + * 11 -> IEEE80211_STYPE_FC0_SUBTYPE_AUTH + * 12 -> IEEE80211_STYPE_FC0_SUBTYPE_DEAUTH + * 13 -> IEEE80211_STYPE_FCO_SUBTYPE_ACTION + * 14 -> IEEE80211_STYPE_FC0_SUBTYPE_ACTION_NOACK + * 15 -> IEEE80211_STYPE_FC0_SUBTYPE_RESERVED + */ +#define WMI_MGMT_FRAME_SUBTYPE_MAX 16 +#define WMI_MAX_STRING_LEN 256 + +enum wmi_ctrl_path_cal_prof_id { + WMI_CTRL_PATH_STATS_CAL_PROF_COLD_BOOT_CAL = 0, + WMI_CTRL_PATH_STATS_CAL_PROF_FULL_CHAN_SWITCH, + WMI_CTRL_PATH_STATS_CAL_PROF_SCAN_CHAN_SWITCH, + WMI_CTRL_PATH_STATS_CAL_PROF_DPD_SPLIT_CAL, + WMI_CTRL_PATH_STATS_CAL_PROF_TEMP_TRIGEER_CAL, + WMI_CTRL_PATH_STATS_CAL_PROF_POWER_SAVE_WAKE_UP, + WMI_CTRL_PATH_STATS_CAL_PROF_TIMER_TRIGGER_CAL, + WMI_CTRL_PATH_STATS_CAL_PROF_FTM_TRIGGER_CAL, + WMI_CTRL_PATH_STATS_CAL_PROF_AGILE_OR_POWER_DOWN_DTIM, + WMI_CTRL_PATH_STATS_CAL_PROF_NOISY_ENV_RXDO, + /* IDs from 10 to 30 for future use*/ + WMI_CTRL_PATH_STATS_CAL_PROFILE_INVALID = 0x1F, +}; + +static inline const char * +wmi_ctrl_path_cal_prof_id_to_name(u8 prof_id) { + switch (prof_id) { + case WMI_CTRL_PATH_STATS_CAL_PROF_COLD_BOOT_CAL: + return "COLD_BOOT_CAL"; + case WMI_CTRL_PATH_STATS_CAL_PROF_FULL_CHAN_SWITCH: + return "FULL_CHAN_SWITCH"; + case WMI_CTRL_PATH_STATS_CAL_PROF_SCAN_CHAN_SWITCH: + return "SCAN_CHAN_SWITCH"; + case WMI_CTRL_PATH_STATS_CAL_PROF_DPD_SPLIT_CAL: + return "DPD_SPLIT_CAL"; + case WMI_CTRL_PATH_STATS_CAL_PROF_TEMP_TRIGEER_CAL: + return "TEMP_TRIGEER_CAL"; + case WMI_CTRL_PATH_STATS_CAL_PROF_POWER_SAVE_WAKE_UP: + return "POWER_SAVE_WAKE_UP"; + case WMI_CTRL_PATH_STATS_CAL_PROF_TIMER_TRIGGER_CAL: + return "TIMER_TRIGGER_CAL"; + case WMI_CTRL_PATH_STATS_CAL_PROF_FTM_TRIGGER_CAL: + return "FTM_TRIGGER_CAL"; + case WMI_CTRL_PATH_STATS_CAL_PROF_AGILE_OR_POWER_DOWN_DTIM: + return "AGILE_OR_POWER_DOWN_DTIM"; + case WMI_CTRL_PATH_STATS_CAL_PROF_NOISY_ENV_RXDO: + return "NOISY_ENV_RXDO"; + case WMI_CTRL_PATH_STATS_CAL_PROFILE_INVALID: + break; + } + return "UNKOWN_CAL_PROFILE"; +} + +enum wmi_ctrl_path_cal_type_id { + WMI_CTRL_PATH_STATS_CAL_TYPE_ADC = 0, + WMI_CTRL_PATH_STATS_CAL_TYPE_DAC, + WMI_CTRL_PATH_STATS_CAL_TYPE_PROCESS, + WMI_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR, + WMI_CTRL_PATH_STATS_CAL_TYPE_RXDCO, + WMI_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ, + WMI_CTRL_PATH_STATS_CAL_TYPE_TXLO, + WMI_CTRL_PATH_STATS_CAL_TYPE_TXIQ, + WMI_CTRL_PATH_STATS_CAL_TYPE_RXIQ, + WMI_CTRL_PATH_STATS_CAL_TYPE_IM2, + WMI_CTRL_PATH_STATS_CAL_TYPE_LNA, + WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO, + WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ, + WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS, + WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY, + WMI_CTRL_PATH_STATS_CAL_TYPE_IBF, + WMI_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL, + WMI_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ, + WMI_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM, + WMI_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL, + WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ, + WMI_CTRL_PATH_STATS_CAL_TYPE_BWFILTER, + WMI_CTRL_PATH_STATS_CAL_TYPE_PEF, + WMI_CTRL_PATH_STATS_CAL_TYPE_PADROOP, + WMI_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC, + /* IDs 25 to 254 for future use*/ + WMI_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xff, +}; + +static inline const char * +wmi_ctrl_path_cal_type_id_to_name(u8 type_id) { + switch (type_id) { + case WMI_CTRL_PATH_STATS_CAL_TYPE_ADC: + return "ADC"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_DAC: + return "DAC"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_PROCESS: + return "PROCESS"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR: + return "NOISE_FLOOR"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_RXDCO: + return "RXDCO"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ: + return "COMB_TXLO_TXIQ_RXIQ"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_TXLO: + return "TXLO"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_TXIQ: + return "TXIQ"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_RXIQ: + return "RXIQ"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_IM2: + return "IM2"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_LNA: + return "LNA"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO: + return "DPD_LP_RXDCO"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ: + return "DPD_LP_RXIQ"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS: + return "DPD_MEMORYLESS"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY: + return "DPD_MEMORY"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_IBF: + return "IBF"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL: + return "PDET_AND_PAL"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ: + return "RXDCO_IQ"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM: + return "RXDCO_DTIM"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL: + return "TPC_CAL"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ: + return "DPD_TIMEREQ"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_BWFILTER: + return "BWFILTER"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_PEF: + return "PEF"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_PADROOP: + return "PADROOP"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC: + return "SELFCALTPC"; + case WMI_CTRL_PATH_STATS_CAL_TYPE_INVALID: + break; + } + return "UNKNOWN_CAL_TYPE"; +} + +enum wmi_ctrl_path_periodic_cal_type_id { + WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_NOISE_FLOOR, + WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_DPD_MEMORYLESS, + WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_DPD_MEMORY, + /* IDs 3 to 254 for future use*/ + WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_INVALID = 0xFF, +}; + +static inline const char * +wmi_ctrl_path_periodic_cal_type_id_to_name(u8 type_id) { + switch (type_id) { + case WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_NOISE_FLOOR: + return "NOISE_FLOOR"; + case WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_DPD_MEMORYLESS: + return "DPD_MEMORYLESS"; + case WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_DPD_MEMORY: + return "DPD_MEMORY"; + case WMI_CTRL_PATH_STATS_PERIODIC_CAL_TYPE_INVALID: + break; + } + return "UNKNOWN_PERIODIC_CAL_TYPE"; +} + +#define WMI_CTRL_PATH_CAL_PROF_MASK GENMASK(12, 8) +#define WMI_CTRL_PATH_CAL_TYPE_MASK GENMASK(7, 0) +#define WMI_CTRL_PATH_IS_PERIODIC_CAL GENMASK(13, 13) +#define WMI_AWGN_MAX_BW 6 + +struct wmi_ctrl_path_pdev_stats { + u32 pdev_id; + u32 tx_mgmt_subtype[WMI_MGMT_FRAME_SUBTYPE_MAX]; + u32 rx_mgmt_subtype[WMI_MGMT_FRAME_SUBTYPE_MAX]; + u32 scan_fail_dfs_violation_time_ms; + u32 nol_chk_fail_last_chan_freq; + u32 nol_chk_fail_time_stamp_ms; + u32 tot_peer_create_cnt; + u32 tot_peer_del_cnt; + u32 tot_peer_del_resp_cnt; + u32 vdev_pause_fail_rt_to_sched_algo_fifo_full_cnt; +} __packed; + +struct wmi_ctrl_path_cal_stats { + u32 pdev_id; + u32 cal_info; + u32 cal_triggered_cnt; + u32 cal_fail_cnt; + u32 cal_fcs_cnt; + u32 cal_fcs_fail_cnt; +} __packed; + +struct wmi_ctrl_path_stats_cmd_param { + u32 tlv_header; + u32 stats_id; + u32 req_id; + /* get/reset/start/stop based on stats id is defined as + * a part of wmi_ctrl_path_stats_action + */ + u32 action; +} __packed; + +struct wmi_ctrl_path_stats_ev_param { + u32 req_id; + /* more flag + * 1 - More events sent after this event. + * 0 - no more events after this event. + */ + u32 more; +} __packed; + +struct wmi_ctrl_path_stats_list { + struct list_head list; + void *stats_ptr; +} __packed; + +struct wmi_ctrl_path_btcoex_stats { + u32 pdev_id; + u32 bt_tx_req_cntr; + u32 bt_rx_req_cntr; + u32 bt_req_nack_cntr; + u32 wl_tx_req_nack_schd_bt_reason_cntr; + u32 wl_tx_req_nack_current_bt_reason_cntr; + u32 wl_tx_req_nack_other_wlan_tx_reason_cntr; + u32 wl_in_tx_abort_cntr; + u32 wl_tx_auto_resp_req_cntr; + u32 wl_tx_req_ack_cntr; + u32 wl_tx_req_cntr; +} __packed; + +struct wmi_ctrl_path_awgn_stats { + u32 awgn_send_evt_cnt; + u32 awgn_pri_int_cnt; + u32 awgn_sec_int_cnt; + u32 awgn_pkt_drop_trigger_cnt; + u32 awgn_pkt_drop_trigger_reset_cnt; + u32 awgn_bw_drop_cnt; + u32 awgn_bw_drop_reset_cnt; + u32 awgn_cca_int_cnt; + u32 awgn_cca_int_reset_cnt; + u32 awgn_cca_ack_blk_cnt; + u32 awgn_cca_ack_reset_cnt; + u32 awgn_int_bw_cnt[WMI_AWGN_MAX_BW]; +} __packed; + +struct wmi_ctrl_path_stats_ev_parse_param { + struct list_head list; + struct ath12k *ar; +} __packed; + struct wmi_obss_spatial_reuse_params_cmd { __le32 tlv_header; __le32 pdev_id; @@ -4437,6 +7479,12 @@ __le32 vdev_id; } __packed; +struct wmi_pdev_obss_pd_bitmap_cmd { + u32 tlv_header; + u32 pdev_id; + u32 bitmap[2]; +} __packed; + #define ATH12K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 #define ATH12K_OBSS_COLOR_COLLISION_DETECTION 1 @@ -4444,6 +7492,13 @@ #define ATH12K_BSS_COLOR_STA_PERIODS 10000 #define ATH12K_BSS_COLOR_AP_PERIODS 5000 +enum wmi_bss_color_collision { + WMI_BSS_COLOR_COLLISION_DISABLE = 0, + WMI_BSS_COLOR_COLLISION_DETECTION, + WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, + WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, +}; + struct wmi_obss_color_collision_cfg_params_cmd { __le32 tlv_header; __le32 vdev_id; @@ -4461,6 +7516,12 @@ __le32 enable; } __packed; +struct wmi_obss_color_collision_event { + u32 vdev_id; + u32 evt_type; + u64 obss_color_bitmap; +} __packed; + #define ATH12K_IPV4_TH_SEED_SIZE 5 #define ATH12K_IPV6_TH_SEED_SIZE 11 @@ -4604,6 +7665,78 @@ __le32 paddr_hi; } __packed; +struct ath12k_wmi_pdev_sscan_fw_cmd_fixed_param { + u32 pdev_id; + u32 spectral_scan_mode; +} __packed; + + +struct ath12k_wmi_pdev_sscan_fft_bin_index { + u32 pri80_bins; + u32 sec80_bins; + u32 mid_5mhz_bins; +} __packed; + +struct ath12k_wmi_pdev_sscan_chan_info { + u32 operating_pri20_freq; + u32 operating_cfreq1; + u32 operating_cfreq2; + u32 operating_bw; + u32 operating_puncture_20mhz_bitmap; + u32 sscan_cfreq1; + u32 sscan_cfreq2; + u32 sscan_bw; + u32 sscan_puncture_20mhz_bitmap; +} __packed; + +struct ath12k_wmi_pdev_sscan_per_detector_info { + __le32 tlv_header; + u32 detector_id; + u32 start_freq; + u32 end_freq; +} __packed; + +struct ath12k_wmi_spectral_scan_bw_capabilities { + __le32 tlv_header; + u32 pdev_id; + u32 sscan_mode; + u32 operating_bw; + union { + struct { + u32 supports_sscan_bw_20:1, + supports_sscan_bw_40:1, + supports_sscan_bw_80:1, + supports_sscan_bw_160:1, + supports_sscan_bw_80p80:1, + supports_sscan_bw_320:1, + reserved:21; + }; + u32 supported_flags; + }; +} __packed; + +struct ath12k_wmi_spectral_fft_size_capabilities { + __le32 tlv_header; + u32 pdev_id; + u32 sscan_bw; + union { + struct { + u32 supports_fft_size_1:1, + supports_fft_size_2:1, + supports_fft_size_3:1, + supports_fft_size_4:1, + supports_fft_size_5:1, + supports_fft_size_6:1, + supports_fft_size_7:1, + supports_fft_size_8:1, + supports_fft_size_9:1, + supports_fft_size_10:1, + supports_fft_size_11:1, + reserved:21; + }; + u32 supported_flags; + }; +} __packed; #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) @@ -4642,18 +7775,265 @@ __le32 buf_len; } __packed; +enum wmi_tpc_pream_bw { + WMI_TPC_PREAM_CCK, + WMI_TPC_PREAM_OFDM, + WMI_TPC_PREAM_HT20, + WMI_TPC_PREAM_HT40, + WMI_TPC_PREAM_VHT20, + WMI_TPC_PREAM_VHT40, + WMI_TPC_PREAM_VHT80, + WMI_TPC_PREAM_VHT160, + WMI_TPC_PREAM_HE20, + WMI_TPC_PREAM_HE40, + WMI_TPC_PREAM_HE80, + WMI_TPC_PREAM_HE160, + WMI_TPC_PREAM_EHT20, + WMI_TPC_PREAM_EHT40, + WMI_TPC_PREAM_EHT60, + WMI_TPC_PREAM_EHT80, + WMI_TPC_PREAM_EHT120, + WMI_TPC_PREAM_EHT140, + WMI_TPC_PREAM_EHT160, + WMI_TPC_PREAM_EHT200, + WMI_TPC_PREAM_EHT240, + WMI_TPC_PREAM_EHT280, + WMI_TPC_PREAM_EHT320, + WMI_TPC_PREAM_MAX +}; + +#define ATH12K_2G_MAX_FREQUENCY 2495 +#define ATH12K_5G_MAX_FREQUENCY 5920 +#define WMI_TPC_CONFIG BIT(1) +#define WMI_TPC_REG_PWR_ALLOWED BIT(2) +#define WMI_TPC_RATES_ARRAY1 BIT(3) +#define WMI_TPC_RATES_ARRAY2 BIT(4) +#define WMI_TPC_RATES_DL_OFDMA_ARRAY BIT(5) +#define WMI_TPC_CTL_PWR_ARRAY BIT(6) +#define WMI_TPC_CONFIG_PARAM 0x1 +#define ATH12K_TPC_RATE_ARRAY_MU GENMASK(15, 8) +#define ATH12K_TPC_RATE_ARRAY_SU GENMASK(7, 0) +#define ATH12K_HW_PREAMBLE(_rcode) (((_rcode) >> 8) & 0x7) +#define ATH12K_HW_NSS(_rcode) (((_rcode) >> 5) & 0x7) +#define MODULATION_LIMIT 126 +#define TPC_STATS_REG_PWR_ALLOWED_TYPE 0 +#define HE_EXTRA_MCS_SUPPORT GENMASK(31, 16) + +enum wmi_ctrl_path_stats_action { + WMI_REQUEST_CTRL_PATH_STAT_GET = 1, + WMI_REQUEST_CTRL_PATH_STAT_RESET = 2, + WMI_REQUEST_CTRL_PATH_STAT_START = 3, + WMI_REQUEST_CTRL_PATH_STAT_STOP = 4, +}; + +struct wmi_request_ctrl_path_stats_cmd_fixed_param { + u32 tlv_header; + /** Bitmask showing which of stats IDs 0-31 have been requested + * These stats ids are defined in enum wmi_ctrl_path_stats_id. + */ + u32 stats_id_mask; + /** request ID to store the cookies in wifistats */ + u32 request_id; + /** action + * get/reset/start/stop based on stats id + * defined as a part of wmi_ctrl_path_stats_action + */ + u32 action; + /** Request Halphy subid stats + * According to the requested stats_id this halphy_subid varies + * For stats_id = 1, the possible values could be enum wmi_halphy_ctrl_path_statsid + */ + u32 subid; +} __packed; + +struct wmi_cp_stats_event_fixed_param { + /** Request ID */ + u32 request_id; + /*end_of_event - single event or Multiple Event */ + u32 end_of_event; + /*event_count - If Multiple Events are send, this is to identify particular + * event out of Multiple Events that are send to host + */ + u32 event_count; + u32 pdev_id; +} __packed; + +struct wmi_tpc_configs { + u32 reg_domain; + /* current channel in MHz */ + u32 chan_freq; + /* current phy mode */ + u32 phy_mode; + /* Max antenna gain for current regulatory in 0.25 dBm steps */ + u32 twice_antenna_reduction; + /* Max transmit power allowed in regulatory domain in 0.25 dBm steps */ + u32 twice_max_reg_power; + /* User specified antenna gain in 0.25 dBm steps */ + s32 twice_antenna_gain; + /* The overall power limit in 0.25 dBm steps */ + u32 power_limit; + /* The total number of rates supported */ + u32 rate_max; + /* The total number of active chains */ + u32 num_tx_chain; + /* not used for now */ + u32 ctl; + u32 flags; + /* tells info abt BE, HE, HE_EXTRA_MCS, 160, 320, 11BE PUNC*/ + u32 caps; +} __packed; + +struct wmi_max_reg_power_fixed_param { + /* 0: maxRegAllowedPower[TX_NUM_CHAIN]; + * 1:maxRegPowerAGCDD[TX_NUM_CHAIN - 1][TX_NUM_CHAIN - 1], + * 2:maxRegPowerAGSTBC[TX_NUM_CHAIN - 1][TX_NUM_CHAIN - 1], + * 3:maxRegPowerAGTXBF([TX_NUM_CHAIN - 1][TX_NUM_CHAIN - 1] + * type 1-3 no used, for future use + */ + u32 reg_power_type; + /* Length of the regulatory power array being sent in bytes */ + u32 reg_array_len; + /* dimensions below + * d1 - [TX_NUM_CHAIN - 1] + * d2- [TX_NUM_CHAIN - 1] for cdd, stbc, txbf + * d2 = 1 for maxRegAllowedPower + * d3 = 1 d4 = 1 + */ + u32 d1; + u32 d2; + u32 d3; + u32 d4; +} __packed; + +struct wmi_max_reg_power_allowed { + struct wmi_max_reg_power_fixed_param tpc_reg_pwr; + s16 *reg_pwr_array; +}; + +struct wmi_tpc_rates_array_fixed_param { + /* 0: ratesArray[TPC_RATE_MAX], (for CCK, OFDM, HT, VHT and HE Rates info) + * 1: ratesArray2[TPC_RATE_MAX] (for EHT Rates info), + * 2: dl_ofdma rate array. Type 2 unsed, for future use + */ + u32 rate_array_type; + u32 rate_array_len; +} __packed; + +struct wmi_tpc_rates_array { + struct wmi_tpc_rates_array_fixed_param tpc_rates_array; + s16 *rate_array; +}; + +struct wmi_tpc_ctl_pwr_fixed_param { + /* 0: ctl_array; 1: ctl_160 array; 2: ctl_dlOfdma array + * Type 2 unsed, for future use + */ + u32 ctl_array_type; + /* Length of the CTL array being sent in bytes */ + u32 ctl_array_len; + /* Message MAY be split into smaller chunks to fit in the WMI svc msg + * not used for now + */ + u32 end_of_ctl_pwr; + /* Incremented for every event chunk for Host to know the sequence + * not used for now + */ + u32 ctl_pwr_count; + /* Dimensions below + * For ctl_array + * d4 = No of chains + * d3 = BF on/off = 2 + * d2 = 28 which the number of different tx modes-legacy, HT20, HT40 etc + * d1 = NSS number of spatial streams + * s8 ctl_160array[WHAL_MAX_NUM_CHAINS][pri_or_sec][bf][nss]. + * For ctl_160 array + * d4 = No of chains d3 = primary/secondary channel + * d2 = BF on/off d1 = NSS + */ + u32 d1; + u32 d2; + u32 d3; + u32 d4; +} __packed; + +struct wmi_tpc_ctl_pwr_table { + struct wmi_tpc_ctl_pwr_fixed_param tpc_ctl_pwr; + s8 *ctl_pwr_table; +}; + +struct wmi_tpc_stats_event { + u32 pdev_id; + u32 event_count; + u32 end_of_event; + /* Bitmap to set and use the received tlvs alone. Not all tlvs are + * supported for all chipset. For eg ctl_160 is not present for chipset + * which does not have 160Mhz support + */ + u32 tlvs_rcvd; + struct wmi_max_reg_power_allowed max_reg_allowed_power; + struct wmi_tpc_rates_array rates_array1; + struct wmi_tpc_rates_array rates_array2; + struct wmi_tpc_configs tpc_config; + struct wmi_tpc_ctl_pwr_table ctl_array; +}; + +enum ath12k_wmi_tpc_stats_events { + ATH12K_TPC_STATS_CONFIG_REG_PWR_EVENT, + ATH12K_TPC_STATS_RATES_EVENT1, + ATH12K_TPC_STATS_RATES_EVENT2, + ATH12K_TPC_STATS_CTL_TABLE_EVENT +}; + +enum ath12k_wmi_tpc_stats_rates_array { + ATH12K_TPC_STATS_RATES_ARRAY1, + ATH12K_TPC_STATS_RATES_ARRAY2, +}; + +enum ath12k_wmi_tpc_stats_ctl_array { + ATH12K_TPC_STATS_CTL_ARRAY, + ATH12K_TPC_STATS_CTL_160ARRAY, +}; + +enum wmi_ctrl_path_stats_id { + /* bit 0 is currently unused / reserved */ + WMI_REQ_CTRL_PATH_PDEV_TX_STAT = 1, + WMI_REQ_CTRL_PATH_VDEV_EXTD_STAT = 2, + WMI_REQ_CTRL_PATH_MEM_STAT = 3, + WMI_REQ_CTRL_PATH_CAL_STAT = 5, + WMI_REQ_CTRL_PATH_AWGN_STAT = 7, + WMI_REQ_CTRL_PATH_BTCOEX_STAT = 8, +}; + +enum wmi_dblog_param { + WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1, + WMI_DEBUG_LOG_PARAM_VDEV_ENABLE, + WMI_DEBUG_LOG_PARAM_VDEV_DISABLE, + WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP, + WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP, + WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP, +}; + +struct wmi_dbglog_config_cmd_fixed_param { + u32 tlv_header; + u32 dbg_log_param; + u32 value; +} __packed; + #define WMI_MAX_MEM_REQS 32 #define MAX_RADIOS 3 +#define WMI_MLO_CMD_TIMEOUT_HZ (5 * HZ) #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) #define WMI_SEND_TIMEOUT_HZ (3 * HZ) +#define WMI_CTRL_STATS_READY_TIMEOUT_HZ (1 * HZ) struct ath12k_wmi_pdev { struct ath12k_wmi_base *wmi_ab; enum ath12k_htc_ep_id eid; const struct wmi_peer_flags_map *peer_flags; u32 rx_decap_mode; + wait_queue_head_t tx_ce_desc_wq; }; struct ath12k_wmi_base { @@ -4664,7 +8044,7 @@ struct completion service_ready; struct completion unified_ready; - DECLARE_BITMAP(svc_map, WMI_MAX_EXT_SERVICE); + DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE); wait_queue_head_t tx_credits_wq; const struct wmi_peer_flags_map *peer_flags; u32 num_mem_chunks; @@ -4676,30 +8056,312 @@ struct ath12k_wmi_target_cap_arg *targ_cap; }; +struct wmi_mlo_setup_cmd_fixed_param { + u32 tlv_header; + u32 mld_group_id; + u32 pdev_id; +} __packed; + +struct wmi_mlo_setup_params { + u32 group_id; + u8 num_partner_links; + u8 *partner_link_id; +}; + +struct wmi_mlo_ready_cmd_fixed_param { + u32 tlv_header; + u32 pdev_id; +} __packed; + +enum wmi_mlo_tear_down_reason_code_type { + WMI_MLO_TEARDOWN_SSR_REASON, +}; + +struct wmi_mlo_teardown_fixed_param { + u32 tlv_header; + u32 pdev_id; + u32 reason_code; + u32 umac_reset; +} __packed; + +struct wmi_mlo_setup_complete_event_fixed_param { + u32 pdev_id; + u32 status; +} __packed; + +struct wmi_mlo_teardown_complete_fixed_param { + u32 pdev_id; + u32 status; +} __packed; + +/* Inform FW that host expects response for multi-vdev + * restart command */ +#define WMI_MVR_RESPONSE_SUPPORT_EXPECTED 0x1 +#define WMI_MVR_CMD_TIMEOUT_HZ (2 * HZ) +#define WMI_MVR_RESP_VDEV_BM_MAX_LEN 2 +#define WMI_MVR_RESP_VDEV_BM_MAX_LEN_BYTES (WMI_MVR_RESP_VDEV_BM_MAX_LEN * 4) + +struct wmi_vdev_ids_arg { + u32 id_len; + u32 id[17]; /* TARGET_NUM_VDEVS */ +}; + +struct wmi_pdev_multiple_vdev_restart_req_arg { + struct wmi_vdev_ids_arg vdev_ids; + struct wmi_channel_arg channel; + u16 ru_punct_bitmap; + u32 width_device; + u32 center_freq_device; +}; + +struct wmi_pdev_multiple_vdev_restart_request_cmd { + __le32 tlv_header; + __le32 pdev_id; + __le32 requestor_id; + __le32 disable_hw_ack; + __le32 cac_duration_ms; + __le32 num_vdevs; + __le32 flags; + __le32 puncture_20mhz_bitmap; +} __packed; + +struct wmi_pdev_mvr_resp_event_fixed_param { + u32 pdev_id; + u32 requestor_id; + u32 status; +} __packed; + +struct wmi_pdev_mvr_resp_event_parse { + struct wmi_pdev_mvr_resp_event_fixed_param fixed_param; + u32 num_vdevs_bm; + u32 vdev_id_bm[WMI_MVR_RESP_VDEV_BM_MAX_LEN]; +} __packed; + +struct wmi_bcn_tmpl_ml_params { + __le32 tlv_header; + __le32 vdev_id; + __le32 hw_link_id; + __le32 beacon_interval; + __le32 csa_switch_count_offset; + __le32 ext_csa_switch_count_offset; + __le32 per_sta_profile_offset; + __le32 quiet_ie_offset; + __le32 is_other_ie_present; +} __packed; + +struct wmi_bcn_tmpl_ml_info { + __le32 tlv_header; + __le32 hw_link_id; + __le32 cu_vdev_map_cat1_lo; + __le32 cu_vdev_map_cat1_hi; + __le32 cu_vdev_map_cat2_lo; + __le32 cu_vdev_map_cat2_hi; +} __packed; + +struct wmi_critical_update_arg { + u16 num_ml_params; + struct wmi_bcn_tmpl_ml_params *ml_params; + u16 num_ml_info; + struct wmi_bcn_tmpl_ml_info *ml_info; +}; + +struct wmi_prb_resp_tmpl_ml_info_params { + __le32 tlv_header; + __le32 hw_link_id; + __le32 cu_vdev_map_cat1_lo; + __le32 cu_vdev_map_cat1_hi; + __le32 cu_vdev_map_cat2_lo; + __le32 cu_vdev_map_cat2_hi; +} __packed; + +#define ATH12K_LOWER_32_MASK GENMASK_ULL(31, 0) +#define ATH12K_UPPER_32_MASK GENMASK_ULL(63, 32) +#define ATH12K_GET_LOWER_32_BITS(val) (val & ATH12K_LOWER_32_MASK) +#define ATH12K_GET_UPPER_32_BITS(val) ((val & ATH12K_UPPER_32_MASK) >> 32) + + +#define WMI_ADFS_MODE_QUICK_OCAC 0 /* Agile preCAC */ +#define WMI_ADFS_MODE_QUICK_RCAC 2 /* Agile Rolling CAC */ +#define WMI_SUPPORT_CHAIN_MASK_ADFS BIT(31) + +#define MIN_PRECAC_TIMEOUT (6 * 60 * 1000) /* 6 minutes */ +#define MIN_WEATHER_RADAR_CHAN_PRECAC_TIMEOUT (6 * 10 * 60 * 1000) /* 1 hour */ +#define MAX_PRECAC_TIMEOUT (4 * 60 * 60 * 1000) /* 4 hours */ +#define MAX_WEATHER_RADAR_CHAN_PRECAC_TIMEOUT (24 * 60 * 60 * 1000) /* 24 hours */ +#define MIN_RCAC_TIMEOUT (62 * 1000) /* 62 seconds */ +#define MAX_RCAC_TIMEOUT 0xffffffff + +struct wmi_vdev_adfs_ch_cfg_cmd { + u32 tlv_header; + u32 vdev_id; + u32 ocac_mode; + u32 min_duration_ms; + u32 max_duration_ms; + u32 chan_freq; + u32 chan_width; + /* + * Two center frequencies are required since agile channel switch + * has to support 160/165 MHz for products like Pine. + * For agile which supports only up to 80MHz (HK), + * freq2 will be 0 and ignored. + */ + union { + u32 center_freq; + u32 center_freq1; + }; + u32 center_freq2; +} __packed; + +struct wmi_vdev_adfs_ocac_abort_cmd { + u32 tlv_header; + u32 vdev_id; +} __packed; + +#define WMI_DFS_RADAR_DETECTED_IN_SERVICE_CHAN 0 +#define WMI_DFS_RADAR_DETECTED_IN_OCAC_CHAN 1 + +struct wmi_vdev_adfs_ocac_complete_event_fixed_param { + u32 vdev_id; + u32 chan_freq; + u32 chan_width; + union { + u32 center_freq; + u32 center_freq1; + }; + u32 status; + u32 center_freq2; +} __packed; + +#define ATH12K_PEER_VALID_VDEV_ID (1 << 31) +#define ATH12K_PEER_PUNCT_BITMAP_VALID (1 << 30) +#define ATH12K_PEER_CH_WIDTH_SWITCH_TIMEOUT_HZ (5 * HZ) + +struct wmi_chan_width_peer_arg { + struct ath12k_wmi_mac_addr_params mac_addr; + u32 chan_width; + u32 puncture_20mhz_bitmap; + enum wmi_phy_mode peer_phymode; + bool is_upgrade; +}; + +struct wmi_peer_chan_width_switch_arg { + u32 num_peers; + u32 vdev_var; + u32 start_idx; + struct wmi_chan_width_peer_arg *peer_arg; +}; + +struct wmi_peer_chan_width_switch_req_cmd { + __le32 tlv_header; + __le32 num_peers; + __le32 vdev_var; +} __packed; + +struct wmi_chan_width_peer_list { + __le32 tlv_header; + struct ath12k_wmi_mac_addr_params mac_addr; + __le32 chan_width; + __le32 puncture_20mhz_bitmap; +} __packed; + + +#define MAX_20MHZ_SEGS 16 +#define MAX_NUM_ANTENNA 8 + +struct wmi_rssi_dbm_conv_event_fixed_param { + u32 pdev_id; +} __packed; + +struct wmi_rssi_dbm_conv_param_info { + u32 curr_bw; + u32 curr_rx_chainmask; + u32 xbar_config; + u32 xlna_bypass_offset; + u32 xlna_bypass_threshold; + s8 nf_hw_dbm[MAX_NUM_ANTENNA][MAX_20MHZ_SEGS]; +} __packed; + +struct wmi_rssi_dbm_conv_temp_offset { + s32 rssi_temp_offset; +} __packed; + +struct wmi_rssi_dbm_conv_offsets { + s32 rssi_temp_offset; + s8 min_nf_dbm; + /* rssi_offset is the sum of min_nf_dbm & rssi_temp_offset*/ + s32 rssi_offset; +}; + +#define WMI_LATENCY_TID_INFO_SCS_TID_NUM GENMASK(7, 0) +#define WMI_LATENCY_TID_INFO_SCS_AC GENMASK(9, 8) +#define WMI_LATENCY_TID_INFO_SCS_DL_EN BIT(10) +#define WMI_LATENCY_TID_INFO_SCS_UL_EN BIT(11) +#define WMI_LATENCY_TID_INFO_SCS_BURST_SZ_SUM GENMASK(13, 12) +#define WMI_LATENCY_TID_INFO_SCS_MSDUQ_ID GENMASK(17, 14) +#define WMI_LATENCY_TID_INFO_SCS_UL_OFDMA_DISABLE BIT(18) +#define WMI_LATENCY_TID_INFO_SCS_UL_MU_MIMO_DISABLE BIT(19) +#define WMI_LATENCY_TID_INFO_SCS_SAWF_UL_PARAM BIT(20) + +#define WMI_LATENCY_DIR_UL 0 +#define WMI_LATENCY_DIR_DL 1 +#define WMI_LATENCY_DIR_DIRECT 2 + +struct wmi_tid_latency_params { + __le32 tlv_header; + struct wmi_mac_addr destmac; + __le32 service_interval; + __le32 burst_size_diff; + __le32 max_latency; + __le32 max_per; + __le32 min_tput; + __le32 latency_tid_info; +} __packed; + +struct wmi_peer_tid_latency_cmd { + __le32 tlv_header; + __le32 pdev_id; +} __packed; + +#define WMI_ANI_EVENT_PDEV_ID_VALID BIT(31) +#define WMI_ANI_EVENT_PDEV_ID GENMASK(7, 0) + +struct wmi_pdev_ani_event { + __le32 tlv_header; + __s32 ani_level; + /* Bits 7:0 - pdev_id + * Bits 30:8 - reserved + * Bits 31 - pdev_id_valid - Flag to check pdev_id is valid or not + */ + __le32 pdev_id_bitmap; +} __packed; + #define ATH12K_FW_STATS_BUF_SIZE (1024 * 1024) void ath12k_wmi_init_qcn9274(struct ath12k_base *ab, struct ath12k_wmi_resource_config_arg *config); void ath12k_wmi_init_wcn7850(struct ath12k_base *ab, struct ath12k_wmi_resource_config_arg *config); +void ath12k_wmi_init_ipq5332(struct ath12k_base *ab, + struct ath12k_wmi_resource_config_arg *config); int ath12k_wmi_cmd_send(struct ath12k_wmi_pdev *wmi, struct sk_buff *skb, u32 cmd_id); struct sk_buff *ath12k_wmi_alloc_skb(struct ath12k_wmi_base *wmi_sc, u32 len); int ath12k_wmi_mgmt_send(struct ath12k *ar, u32 vdev_id, u32 buf_id, + struct sk_buff *frame, bool link_agnostic); +int ath12k_wmi_offchan_mgmt_send(struct ath12k *ar, u32 vdev_id, u32 buf_id, struct sk_buff *frame); int ath12k_wmi_bcn_tmpl(struct ath12k *ar, u32 vdev_id, struct ieee80211_mutable_offsets *offs, - struct sk_buff *bcn); + struct sk_buff *bcn, u32 ema_param); int ath12k_wmi_vdev_down(struct ath12k *ar, u8 vdev_id); -int ath12k_wmi_vdev_up(struct ath12k *ar, u32 vdev_id, u32 aid, - const u8 *bssid); +int ath12k_wmi_vdev_up(struct ath12k *ar, struct vdev_up_params *params); int ath12k_wmi_vdev_stop(struct ath12k *ar, u8 vdev_id); int ath12k_wmi_vdev_start(struct ath12k *ar, struct wmi_vdev_start_req_arg *arg, bool restart); int ath12k_wmi_set_peer_param(struct ath12k *ar, const u8 *peer_addr, u32 vdev_id, u32 param_id, u32 param_val); int ath12k_wmi_pdev_set_param(struct ath12k *ar, u32 param_id, - u32 param_value, u8 pdev_id); + s32 param_value, u8 pdev_id); int ath12k_wmi_pdev_set_ps_mode(struct ath12k *ar, int vdev_id, u32 enable); int ath12k_wmi_wait_for_unified_ready(struct ath12k_base *ab); int ath12k_wmi_cmd_init(struct ath12k_base *ab); @@ -4718,7 +8380,8 @@ int ath12k_wmi_set_sta_ps_param(struct ath12k *ar, u32 vdev_id, u32 param, u32 param_value); -int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms); +int ath12k_wmi_force_fw_hang_cmd(struct ath12k *ar, u32 type, u32 delay_time_ms, + bool nowait); int ath12k_wmi_send_peer_delete_cmd(struct ath12k *ar, const u8 *peer_addr, u8 vdev_id); int ath12k_wmi_vdev_delete(struct ath12k *ar, u8 vdev_id); @@ -4764,6 +8427,12 @@ u32 vdev_id, u32 bcn_ctrl_op); int ath12k_wmi_send_init_country_cmd(struct ath12k *ar, struct ath12k_wmi_init_country_arg *arg); +int +ath12k_wmi_send_thermal_mitigation_cmd(struct ath12k *ar, + struct ath12k_wmi_thermal_mitigation_arg *arg); +int ath12k_wmi_pdev_pktlog_enable(struct ath12k *ar, u32 pktlog_filter); +int ath12k_wmi_pdev_pktlog_disable(struct ath12k *ar); +int ath12k_wmi_pdev_peer_pktlog_filter(struct ath12k *ar, u8 *addr, u8 enable); int ath12k_wmi_peer_rx_reorder_queue_setup(struct ath12k *ar, int vdev_id, const u8 *addr, dma_addr_t paddr, u8 tid, @@ -4772,13 +8441,47 @@ int ath12k_wmi_rx_reord_queue_remove(struct ath12k *ar, struct ath12k_wmi_rx_reorder_queue_remove_arg *arg); +int ath12k_wmi_send_pdev_pkt_route(struct ath12k *ar, + struct ath12k_wmi_pkt_route_param *param); int ath12k_wmi_send_pdev_set_regdomain(struct ath12k *ar, struct ath12k_wmi_pdev_set_regdomain_arg *arg); -int ath12k_wmi_simulate_radar(struct ath12k *ar); +int ath12k_wmi_pull_fw_stats(struct ath12k_base *ab, struct sk_buff *skb, + struct ath12k_fw_stats *stats); +size_t ath12k_wmi_fw_stats_num_peers(struct list_head *head); +size_t ath12k_wmi_fw_stats_num_peers_extd(struct list_head *head); +size_t ath12k_wmi_fw_stats_num_vdevs(struct list_head *head); +void ath12k_wmi_fw_stats_fill(struct ath12k *ar, + struct ath12k_fw_stats *fw_stats, u32 stats_id, + char *buf); +int ath12k_wmi_simulate_radar(struct ath12k *ar, u32 radar_params); +int ath12k_wmi_simulate_awgn(struct ath12k *ar, u32 chan_bw_interference_bitmap); int ath12k_wmi_send_twt_enable_cmd(struct ath12k *ar, u32 pdev_id); int ath12k_wmi_send_twt_disable_cmd(struct ath12k *ar, u32 pdev_id); +int ath12k_wmi_send_twt_add_dialog_cmd(struct ath12k *ar, + struct wmi_twt_add_dialog_params *params); +int ath12k_wmi_send_twt_del_dialog_cmd(struct ath12k *ar, + struct wmi_twt_del_dialog_params *params); +int ath12k_wmi_send_twt_pause_dialog_cmd(struct ath12k *ar, + struct wmi_twt_pause_dialog_params *params); +int ath12k_wmi_send_twt_resume_dialog_cmd(struct ath12k *ar, + struct wmi_twt_resume_dialog_params *params); int ath12k_wmi_send_obss_spr_cmd(struct ath12k *ar, u32 vdev_id, struct ieee80211_he_obss_pd *he_obss_pd); +int ath12k_wmi_pdev_set_srg_bss_color_bitmap(struct ath12k *ar, u32 *bitmap); +int ath12k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath12k *ar, u32 *bitmap); +int ath12k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath12k *ar, + u32 *bitmap); +int ath12k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath12k *ar, + u32 *bitmap); +int ath12k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath12k *ar, + u32 *bitmap); +int ath12k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath12k *ar, + u32 *bitmap); +int ath12k_send_coex_config_cmd(struct ath12k *ar, + struct coex_config_arg *coex_config); +int ath12k_wmi_obss_color_cfg_cmd(struct ath12k *ar, u32 vdev_id, + u8 bss_color, u32 period, + bool enable); int ath12k_wmi_obss_color_cfg_cmd(struct ath12k *ar, u32 vdev_id, u8 bss_color, u32 period, bool enable); @@ -4799,5 +8502,49 @@ struct sk_buff *tmpl); int ath12k_wmi_set_hw_mode(struct ath12k_base *ab, enum wmi_host_hw_mode_config_type mode); - +int ath12k_wmi_send_vdev_set_tpc_power(struct ath12k *ar, + u32 vdev_id, + struct ath12k_reg_tpc_power_info *param); +int ath12k_wmi_dbglog_cfg(struct ath12k *ar, u32 param, u64 value); +int ath12k_wmi_pdev_ap_ps_cmd_send(struct ath12k *ar, u8 pdev_id, u32 value); +int ath12k_wmi_pdev_m3_dump_enable(struct ath12k *ar, u32 enable); +int ath12k_wmi_pdev_get_tpc_table_cmdid(struct ath12k *ar); +void ath12k_wmi_free_tpc_stats_mem(struct ath12k *ar); +int ath12k_wmi_send_wmi_ctrl_stats_cmd(struct ath12k *ar, + struct wmi_ctrl_path_stats_cmd_param *param); +int ath12k_wmi_mlo_setup(struct ath12k *ar, + struct wmi_mlo_setup_params *mlo_params); +int ath12k_wmi_mlo_ready(struct ath12k *ar); +int ath12k_wmi_mlo_teardown(struct ath12k *ar, bool umac_reset); +bool ath12k_wmi_is_mvr_supported(struct ath12k_base *ab); +int ath12k_wmi_pdev_multiple_vdev_restart(struct ath12k *ar, + struct wmi_pdev_multiple_vdev_restart_req_arg *arg); +int ath12k_wmi_vdev_adfs_ch_cfg_cmd_send(struct ath12k *ar,u32 vdev_id, + struct cfg80211_chan_def *chandef); +int ath12k_wmi_vdev_adfs_ocac_abort_cmd_send(struct ath12k *ar,u32 vdev_id); +int ath12k_wmi_svc_config_send(struct ath12k *ar, + struct ath12k_sawf_svc_params *param); +int ath12k_wmi_svc_send_disable(struct ath12k *ar, u32 svc_id); +int ath12k_wmi_mgmt_rx_reo_filter_config(struct ath12k *ar, + struct ath12k_mgmt_rx_reo_filter *filter); +int +ath12k_mgmt_rx_reo_init_context(struct ath12k_base *ab); +int +ath12k_mgmt_rx_reo_deinit_context(struct ath12k_base *ab); +#ifdef CONFIG_ATH12K_BONDED_DS_SUPPORT +int +ath12k_wmi_send_vdev_set_intra_bss_cmd(struct ath12k *ar, + u32 vdev_id, u32 enable); +int ath12k_wmi_set_peer_intra_bss_cmd(struct ath12k *ar, u32 vdev_id, const u8 *peer_addr, + u32 enable); +#endif +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +int ath12k_wmi_config_peer_ppeds_routing(struct ath12k *ar, + const u8 *peer_addr, u8 vdev_id, + u32 service_code, u32 priority_valid, + u32 src_info, bool ppe_routing_enable); +#endif +void ath12k_wmi_peer_chan_width_switch_work(struct work_struct *work); +int ath12k_wmi_set_latency(struct ath12k *ar, struct ath12k_latency_params *params); +int ath12k_wmi_pdev_get_ani_level(struct ath12k *ar, u32 param_id, u8 pdev_id); #endif diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/ar9003_calib.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ar9003_calib.c --- linux-6.4/drivers/net/wireless/ath/ath9k/ar9003_calib.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ar9003_calib.c 2023-05-22 20:06:42.251800816 +0200 @@ -165,6 +165,8 @@ if (ret < 0) return ret; + ath9k_hw_update_cca_threshold(ah); + /* start NF calibration, without updating BB NF register */ ath9k_hw_start_nfcal(ah, false); } diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/ar9003_phy.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.c --- linux-6.4/drivers/net/wireless/ath/ath9k/ar9003_phy.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.c 2023-05-22 20:06:42.251800816 +0200 @@ -1918,6 +1918,116 @@ } } +/* + * Adaptive CCA threshold - Calculate and update CCA threshold periodically + * after NF calibration and at the end of initialization sequence during every + * chip reset. + * + * Step 1: Compute NF_max_primary and NF_max_extension + * If noise floor completes, + * NF_max_primary = max of noise floor read across all chains in primary channel + * NF_max_extension = max of noise floor read across all chains in extension channel + * else + * NF_max_primary = NF_max_extension = the value that is forced into HW as noise floor + * + * Step 2: Compute CCA_threshold_primary and CCA_threshold_extension + * CCA_threshold_primary = CCA_detection_level – CCA_detection_margin – NF_max_primary + * CCA_threshold_extension = CCA_detection_level – CCA_detection_margin – NF_max_extension + * + * Step 3: Program CCA thresholds + * + */ +void ar9003_update_cca_threshold(struct ath_hw *ah) +{ + struct ath9k_hw_cal_data *cal = ah->caldata; + struct ath9k_nfcal_hist *h; + u_int16_t cca_detection_margin_pri, cca_detection_margin_ext; + int16_t nf, nf_max_primary, nf_max_extension, nf_nominal, + derived_max_cca, max_cca_cap, cca_threshold_primary, + cca_threshold_extension; + u_int8_t chainmask; + int chan, chain, i, init_nf = 0; + + if (!ah->adaptive_cca_threshold_enabled) + return; + + if (!cal) + return; + + h = cal->nfCalHist; + + if (IS_CHAN_2GHZ(ah->curchan)) + nf = ah->nf_2g.max; + else + nf = ah->nf_5g.max; + + nf_max_primary = nf_max_extension = nf; + + chainmask = ah->rxchainmask & ah->caps.rx_chainmask; + + /* Compute max of noise floor read across all chains in primary channel */ + for (chan = 0; chan < 2 /*ctl,ext*/; chan++) { + ath_dbg(ath9k_hw_common(ah), CALIBRATE, "chan: %s\n", + !chan ? "ctrl" : "extn"); + + for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { + if (!((chainmask >> chain) & 0x1)) + continue; + + i = chan * AR9300_MAX_CHAINS + chain; + if (!init_nf) { + nf = h[i].privNF; + init_nf = 1; + } + + ath_dbg(ath9k_hw_common(ah), CALIBRATE, "privNF[%d]: %d\n", + i, h[i].privNF); + nf = (nf > h[i].privNF) ? nf : h[i].privNF; + } + + if (!chan) + nf_max_primary = nf; + else + nf_max_extension = nf; + } + + if (IS_CHAN_HT40(ah->curchan)) + nf_nominal = NF_NOM_40MHZ; + else + nf_nominal = NF_NOM_20MHZ; + + cca_detection_margin_pri = ah->cca_detection_margin; + if (nf_max_primary < nf_nominal) + cca_detection_margin_pri += (nf_nominal - nf_max_primary); + + cca_detection_margin_ext = ah->cca_detection_margin; + if (nf_max_extension < nf_nominal) + cca_detection_margin_ext += (nf_nominal - nf_max_extension); + + derived_max_cca = ah->cca_detection_level - ah->cca_detection_margin - BEST_CASE_NOISE_FLOOR; + max_cca_cap = derived_max_cca < MAX_CCA_THRESHOLD ? derived_max_cca : MAX_CCA_THRESHOLD; + + ath_dbg(ath9k_hw_common(ah), CALIBRATE, "derived_max_cca: %d, max_cca_cap: %d\n", + derived_max_cca, max_cca_cap); + + cca_threshold_primary = ah->cca_detection_level - cca_detection_margin_pri - nf_max_primary; + cca_threshold_primary = cca_threshold_primary < max_cca_cap ? + (cca_threshold_primary > MIN_CCA_THRESHOLD ? + cca_threshold_primary : MIN_CCA_THRESHOLD) : max_cca_cap; + cca_threshold_extension = ah->cca_detection_level - cca_detection_margin_ext - nf_max_extension; + cca_threshold_extension = cca_threshold_extension < max_cca_cap ? + (cca_threshold_extension > MIN_CCA_THRESHOLD ? + cca_threshold_extension : MIN_CCA_THRESHOLD) : max_cca_cap; + + ath_dbg(ath9k_hw_common(ah), CALIBRATE, + "nf_max_primary: %d, nf_max_extension: %d, cca_pri: %d, cca_ext: %d\n", + nf_max_primary, nf_max_extension, cca_threshold_primary, cca_threshold_extension); + + REG_RMW_FIELD(ah, AR_PHY_CCA_0, AR_PHY_CCA_THRESH62, cca_threshold_primary); + REG_RMW_FIELD(ah, AR_PHY_EXTCHN_PWRTHR1, AR_PHY_EXT_CCA0_THRESH62, cca_threshold_extension); + REG_RMW_FIELD(ah, AR_PHY_CCA_CTRL_0, AR_PHY_EXT_CCA0_THRESH62_MODE, 0x0); +} + void ar9003_hw_attach_phy_ops(struct ath_hw *ah) { struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); @@ -1953,6 +2063,7 @@ priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; priv_ops->set_radar_params = ar9003_hw_set_radar_params; priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; + priv_ops->update_cca_threshold = ar9003_update_cca_threshold; ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/ar9003_phy.h linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.h --- linux-6.4/drivers/net/wireless/ath/ath9k/ar9003_phy.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.h 2023-05-22 20:06:42.251800816 +0200 @@ -399,6 +399,8 @@ #define AR_PHY_EXT_CCA0_THRESH62_S 0 #define AR_PHY_EXT_CCA0_THRESH62_1 0x000001FF #define AR_PHY_EXT_CCA0_THRESH62_1_S 0 +#define AR_PHY_EXT_CCA0_THRESH62_MODE 0x00040000 +#define AR_PHY_EXT_CCA0_THRESH62_MODE_S 18 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 @@ -1326,4 +1328,10 @@ #define AR9300_DFS_FIRPWR -28 +#define BEST_CASE_NOISE_FLOOR -130 +#define MAX_CCA_THRESHOLD 90 +#define MIN_CCA_THRESHOLD 0 +#define NF_NOM_20MHZ -101 +#define NF_NOM_40MHZ -98 + #endif /* AR9003_PHY_H */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/ath9k.h linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ath9k.h --- linux-6.4/drivers/net/wireless/ath/ath9k/ath9k.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/ath9k.h 2023-05-22 20:06:42.255800922 +0200 @@ -1152,4 +1152,18 @@ static inline void ath_ahb_exit(void) {}; #endif +#ifdef CONFIG_ATH9K_TX99 +extern int ath9k_enable_tx99; + +static inline bool ath9k_tx99_enabled(void) +{ + return ath9k_enable_tx99 > 0; +} +#else +static inline bool ath9k_tx99_enabled(void) +{ + return false; +} +#endif + #endif /* ATH9K_H */ diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/calib.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/calib.c --- linux-6.4/drivers/net/wireless/ath/ath9k/calib.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/calib.c 2023-05-22 20:06:42.255800922 +0200 @@ -234,12 +234,17 @@ REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_ENABLE_NF); + if (ah->adaptive_cca_threshold_enabled) { + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), + AR_PHY_AGC_CONTROL_NO_UPDATE_NF); + } else { if (update) REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NO_UPDATE_NF); else REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NO_UPDATE_NF); + } REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF); } @@ -476,9 +481,13 @@ * the baseband update the internal NF value itself, similar to * what is being done after a full reset. */ - if (!test_bit(NFCAL_PENDING, &caldata->cal_flags)) - ath9k_hw_start_nfcal(ah, true); - else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF)) + if (!test_bit(NFCAL_PENDING, &caldata->cal_flags)) { + bool do_fast_recalib; + + ath9k_hw_update_cca_threshold(ah); + do_fast_recalib = !ah->adaptive_cca_threshold_enabled; + ath9k_hw_start_nfcal(ah, do_fast_recalib); + } else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL(ah)) & AR_PHY_AGC_CONTROL_NF)) ath9k_hw_getnf(ah, ah->curchan); set_bit(NFCAL_INTF, &caldata->cal_flags); diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/debug.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/debug.c --- linux-6.4/drivers/net/wireless/ath/ath9k/debug.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/debug.c 2023-05-22 20:06:42.255800922 +0200 @@ -1289,6 +1289,101 @@ .llseek = default_llseek, }; +static ssize_t read_file_cca_detection_level(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + char buf[32]; + unsigned int len; + + len = sprintf(buf, "%d\n", ah->cca_detection_level); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t write_file_cca_detection_level(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + long val; + char buf[32]; + ssize_t len; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + + if (kstrtol(buf, 0, &val)) + return -EINVAL; + + if (val > 0) + return -EINVAL; + + ah->cca_detection_level = val; + + return count; +} + +static const struct file_operations fops_cca_detection_level = { + .read = read_file_cca_detection_level, + .write = write_file_cca_detection_level, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t read_file_cca_detection_margin(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + char buf[32]; + unsigned int len; + + len = sprintf(buf, "%d\n", ah->cca_detection_margin); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t write_file_cca_detection_margin(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + unsigned long val; + char buf[32]; + ssize_t len; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + ah->cca_detection_margin = val; + + return count; +} + +static const struct file_operations fops_cca_detection_margin = { + .read = read_file_cca_detection_margin, + .write = write_file_cca_detection_margin, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + /* Ethtool support for get-stats */ #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO" @@ -1497,6 +1592,11 @@ debugfs_create_file("nf_override", 0600, sc->debug.debugfs_phy, sc, &fops_nf_override); - + debugfs_create_file("cca_detection_level", 0600, + sc->debug.debugfs_phy, sc, &fops_cca_detection_level); + debugfs_create_file("cca_detection_margin", 0600, + sc->debug.debugfs_phy, sc, &fops_cca_detection_margin); + debugfs_create_bool("adaptive_cca_threshold_enabled", 0600, sc->debug.debugfs_phy, + &sc->sc_ah->adaptive_cca_threshold_enabled); return 0; } diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/hw-ops.h linux-6.4-fbx/drivers/net/wireless/ath/ath9k/hw-ops.h --- linux-6.4/drivers/net/wireless/ath/ath9k/hw-ops.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/hw-ops.h 2023-03-10 13:04:57.476924804 +0100 @@ -260,6 +260,14 @@ ath9k_hw_private_ops(ah)->set_radar_params(ah, &ah->radar_conf); } +static inline void ath9k_hw_update_cca_threshold(struct ath_hw *ah) +{ + if (!ath9k_hw_private_ops(ah)->update_cca_threshold) + return; + + ath9k_hw_private_ops(ah)->update_cca_threshold(ah); +} + static inline void ath9k_hw_init_cal_settings(struct ath_hw *ah) { ath9k_hw_private_ops(ah)->init_cal_settings(ah); diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/hw.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/hw.c --- linux-6.4/drivers/net/wireless/ath/ath9k/hw.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/hw.c 2023-05-22 20:06:42.259801029 +0200 @@ -395,6 +395,7 @@ { struct ath_common *common = ath9k_hw_common(ah); + ah->config.dma_beacon_response_time = 1; ah->config.sw_beacon_response_time = 6; ah->config.cwm_ignore_extcca = false; @@ -1837,6 +1838,7 @@ ar9003_mci_2g5g_switch(ah, false); ath9k_hw_loadnf(ah, ah->curchan); + ath9k_hw_update_cca_threshold(ah); ath9k_hw_start_nfcal(ah, true); if (AR_SREV_9271(ah)) @@ -2062,6 +2064,7 @@ if (AR_SREV_9300_20_OR_LATER(ah)) { ath9k_hw_loadnf(ah, chan); + ath9k_hw_update_cca_threshold(ah); ath9k_hw_start_nfcal(ah, true); } diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/hw.h linux-6.4-fbx/drivers/net/wireless/ath/ath9k/hw.h --- linux-6.4/drivers/net/wireless/ath/ath9k/hw.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/hw.h 2023-05-22 20:06:42.259801029 +0200 @@ -667,7 +667,7 @@ struct ath_hw_radar_conf *conf); int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, u8 *ini_reloaded); - + void (*update_cca_threshold)(struct ath_hw *ah); /* ANI */ void (*ani_cache_ini_regs)(struct ath_hw *ah); @@ -988,6 +988,10 @@ bool msi_enabled; u32 msi_mask; u32 msi_reg; + + bool adaptive_cca_threshold_enabled; + s16 cca_detection_level; + u16 cca_detection_margin; }; struct ath_bus_ops { diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/init.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/init.c --- linux-6.4/drivers/net/wireless/ath/ath9k/init.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/init.c 2023-05-22 20:06:42.259801029 +0200 @@ -80,6 +80,16 @@ module_param_named(use_msi, ath9k_use_msi, int, 0444); MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible"); +int ath9k_use_adaptive_cca; +module_param_named(use_adaptive_cca, ath9k_use_adaptive_cca, int, 0444); +MODULE_PARM_DESC(use_adaptive_cca, "enable adaptive cca by default"); + +#ifdef CONFIG_ATH9K_TX99 +int ath9k_enable_tx99; +module_param_named(enable_tx99, ath9k_enable_tx99, int, 0444); +MODULE_PARM_DESC(enable_tx99, "Enable TX99, which will disable STA/AP mode support"); +#endif + bool is_ath9k_unloaded; #ifdef CONFIG_MAC80211_LEDS @@ -714,6 +724,9 @@ ah->hw_version.devid = devid; ah->ah_flags |= AH_USE_EEPROM; ah->led_pin = -1; + ah->cca_detection_level = -70; + ah->cca_detection_margin = 3; + ah->adaptive_cca_threshold_enabled = ath9k_use_adaptive_cca; ah->reg_ops.read = ath9k_ioread32; ah->reg_ops.multi_read = ath9k_multi_ioread32; ah->reg_ops.write = ath9k_iowrite32; @@ -742,6 +755,7 @@ common->debug_mask = ath9k_debug; common->btcoex_enabled = ath9k_btcoex_enable == 1; common->disable_ani = false; + common->dfs_pulse_valid_diff_ts = 0; /* * Platform quirks. @@ -981,7 +995,7 @@ NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | NL80211_FEATURE_P2P_GO_CTWIN; - if (!IS_ENABLED(CONFIG_ATH9K_TX99)) { + if (!ath9k_tx99_enabled()) { hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT) | diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/link.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/link.c --- linux-6.4/drivers/net/wireless/ath/ath9k/link.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/link.c 2023-03-15 13:36:54.470058565 +0100 @@ -523,11 +523,14 @@ survey->filled |= SURVEY_INFO_TIME | SURVEY_INFO_TIME_BUSY | SURVEY_INFO_TIME_RX | + SURVEY_INFO_TIME_BSS_RX | SURVEY_INFO_TIME_TX; survey->time += cc->cycles / div; survey->time_busy += cc->rx_busy / div; survey->time_rx += cc->rx_frame / div; survey->time_tx += cc->tx_frame / div; + /* convert rx airtime from usec to msec */ + survey->time_bss_rx += cc->rx_bss_frame / 1000; } if (cc->cycles < div) diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/main.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/main.c --- linux-6.4/drivers/net/wireless/ath/ath9k/main.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/main.c 2024-01-19 17:01:19.881847467 +0100 @@ -850,7 +850,7 @@ static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix) { struct ath_hw *ah = sc->sc_ah; - int i; + int i, j; struct ath_txq *txq; bool key_in_use = false; @@ -868,8 +868,9 @@ if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { int idx = txq->txq_tailidx; - while (!key_in_use && - !list_empty(&txq->txq_fifo[idx])) { + for (j = 0; !key_in_use && + !list_empty(&txq->txq_fifo[idx]) && + j < ATH_TXFIFO_DEPTH; j++) { key_in_use = ath9k_txq_list_has_key( &txq->txq_fifo[idx], keyix); INCR(idx, ATH_TXFIFO_DEPTH); @@ -1336,7 +1337,7 @@ struct ath_node *an = &avp->mcast_node; mutex_lock(&sc->mutex); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) { + if (ath9k_tx99_enabled()) { if (sc->cur_chan->nvifs >= 1) { mutex_unlock(&sc->mutex); return -EOPNOTSUPP; @@ -1386,7 +1387,7 @@ mutex_lock(&sc->mutex); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) { + if (ath9k_tx99_enabled()) { mutex_unlock(&sc->mutex); return -EOPNOTSUPP; } @@ -1446,7 +1447,7 @@ struct ath_hw *ah = sc->sc_ah; struct ath_common *common = ath9k_hw_common(ah); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return; sc->ps_enabled = true; @@ -1465,7 +1466,7 @@ struct ath_hw *ah = sc->sc_ah; struct ath_common *common = ath9k_hw_common(ah); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return; sc->ps_enabled = false; @@ -1541,7 +1542,7 @@ ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef); } - if (changed & IEEE80211_CONF_CHANGE_POWER) + if ((changed & IEEE80211_CONF_CHANGE_POWER) && !(ah->tpc_enabled)) ath9k_set_txpower(sc, NULL); mutex_unlock(&sc->mutex); @@ -2070,7 +2071,7 @@ unsigned long flags; int pos; - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return -EOPNOTSUPP; spin_lock_irqsave(&common->cc_lock, flags); @@ -2120,7 +2121,7 @@ struct ath_softc *sc = hw->priv; struct ath_hw *ah = sc->sc_ah; - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return; mutex_lock(&sc->mutex); @@ -2383,7 +2384,22 @@ { struct ath_softc *sc = hw->priv; struct ath_common *common = ath9k_hw_common(sc->sc_ah); + struct cfg80211_chan_def *chandef = &sc->cur_chan->chandef; + struct ieee80211_channel *chan = chandef->chan; + int pos = chan->hw_value; set_bit(ATH_OP_SCANNING, &common->op_flags); + + /* Reset current survey */ + if (!sc->cur_chan->offchannel) { + if (sc->cur_survey != &sc->survey[pos]) { + if (sc->cur_survey) + sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE; + sc->cur_survey = &sc->survey[pos]; + } + + memset(sc->cur_survey, 0, sizeof(struct survey_info)); + sc->cur_survey->filled |= SURVEY_INFO_IN_USE; + } } static void ath9k_sw_scan_complete(struct ieee80211_hw *hw, diff -ruw linux-6.4/drivers/net/wireless/ath/ath9k/recv.c linux-6.4-fbx/drivers/net/wireless/ath/ath9k/recv.c --- linux-6.4/drivers/net/wireless/ath/ath9k/recv.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath9k/recv.c 2023-03-15 13:36:54.470058565 +0100 @@ -377,7 +377,7 @@ struct ath_common *common = ath9k_hw_common(sc->sc_ah); u32 rfilt; - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return 0; rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST @@ -1018,6 +1018,7 @@ struct ieee80211_rx_status *rxs; const struct ieee80211_rate *rate; bool is_sgi, is_40, is_sp; + unsigned long flags; int phy; u16 len = rs->rs_datalen; u32 airtime = 0; @@ -1052,6 +1053,10 @@ len, rxs->rate_idx, is_sp); } + spin_lock_irqsave(&common->cc_lock, flags); + common->cc_survey.rx_bss_frame += airtime; + spin_unlock_irqrestore(&common->cc_lock, flags); + ieee80211_sta_register_airtime(sta, tidno, 0, airtime); exit: rcu_read_unlock(); diff -ruw linux-6.4/drivers/net/wireless/ath/dfs_pattern_detector.c linux-6.4-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c --- linux-6.4/drivers/net/wireless/ath/dfs_pattern_detector.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c 2024-01-25 13:40:06.020812288 +0100 @@ -275,6 +275,7 @@ { u32 i; struct channel_detector *cd; + int diff_ts; /* * pulses received for a non-supported or un-initialized @@ -287,8 +288,9 @@ if (cd == NULL) return false; + diff_ts = event->ts - dpd->last_pulse_ts; /* reset detector on time stamp wraparound, caused by TSF reset */ - if (event->ts < dpd->last_pulse_ts) + if (diff_ts < dpd->common->dfs_pulse_valid_diff_ts) dpd_reset(dpd); dpd->last_pulse_ts = event->ts; diff -ruw linux-6.4/drivers/net/wireless/ath/dfs_pattern_detector.h linux-6.4-fbx/drivers/net/wireless/ath/dfs_pattern_detector.h --- linux-6.4/drivers/net/wireless/ath/dfs_pattern_detector.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/dfs_pattern_detector.h 2023-02-27 20:51:59.590934925 +0100 @@ -24,7 +24,7 @@ /* tolerated deviation of radar time stamp in usecs on both sides * TODO: this might need to be HW-dependent */ -#define PRI_TOLERANCE 16 +#define PRI_TOLERANCE 6 /** * struct ath_dfs_pool_stats - DFS Statistics for global pools diff -ruw linux-6.4/drivers/net/wireless/ath/key.c linux-6.4-fbx/drivers/net/wireless/ath/key.c --- linux-6.4/drivers/net/wireless/ath/key.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/key.c 2023-05-22 20:06:42.267801242 +0200 @@ -524,7 +524,7 @@ idx = ath_reserve_key_cache_slot(common, key->cipher); break; default: - idx = key->keyidx; + idx = ath_reserve_key_cache_slot(common, key->cipher); break; } } else if (key->keyidx) { diff -ruw linux-6.4/drivers/net/wireless/ath/regd.c linux-6.4-fbx/drivers/net/wireless/ath/regd.c --- linux-6.4/drivers/net/wireless/ath/regd.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/ath/regd.c 2023-02-27 20:46:50.166676215 +0100 @@ -345,6 +345,10 @@ struct ieee80211_channel *ch; unsigned int i; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif + for (band = 0; band < NUM_NL80211_BANDS; band++) { if (!wiphy->bands[band]) continue; @@ -379,6 +383,10 @@ { struct ieee80211_supported_band *sband; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif + sband = wiphy->bands[NL80211_BAND_2GHZ]; if (!sband) return; @@ -408,6 +416,9 @@ struct ieee80211_channel *ch; unsigned int i; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif if (!wiphy->bands[NL80211_BAND_5GHZ]) return; @@ -640,6 +651,11 @@ const struct ieee80211_regdomain *regd; wiphy->reg_notifier = reg_notifier; + +#ifdef CONFIG_ATH_REG_IGNORE + return 0; +#endif + wiphy->regulatory_flags |= REGULATORY_STRICT_REG | REGULATORY_CUSTOM_REG; @@ -704,7 +720,7 @@ regdmn == CTRY_DEFAULT) { printk(KERN_DEBUG "ath: EEPROM indicates default " "country code should be used\n"); - reg->country_code = CTRY_UNITED_STATES; + reg->country_code = CTRY_FRANCE; } if (reg->country_code == CTRY_DEFAULT) { diff -ruw linux-6.4/drivers/net/wireless/marvell/Kconfig linux-6.4-fbx/drivers/net/wireless/marvell/Kconfig --- linux-6.4/drivers/net/wireless/marvell/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/marvell/Kconfig 2023-03-10 17:18:24.474042758 +0100 @@ -25,4 +25,8 @@ To compile this driver as a module, choose M here: the module will be called mwl8k. If unsure, say N. +config MWL8K_NEW + tristate "Marvell 88W8xxx PCI/PCIe NEW" + depends on MAC80211 && PCI + endif # WLAN_VENDOR_MARVELL diff -ruw linux-6.4/drivers/net/wireless/marvell/Makefile linux-6.4-fbx/drivers/net/wireless/marvell/Makefile --- linux-6.4/drivers/net/wireless/marvell/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/net/wireless/marvell/Makefile 2023-03-10 17:18:24.474042758 +0100 @@ -5,3 +5,4 @@ obj-$(CONFIG_MWIFIEX) += mwifiex/ obj-$(CONFIG_MWL8K) += mwl8k.o +obj-$(CONFIG_MWL8K_NEW) += mwl8k_new/ diff -ruw linux-6.4/drivers/nvmem/Kconfig linux-6.4-fbx/drivers/nvmem/Kconfig --- linux-6.4/drivers/nvmem/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/nvmem/Kconfig 2023-05-22 20:06:42.603810179 +0200 @@ -59,6 +59,9 @@ This driver provides support for Broadcom's NVRAM that can be accessed using I/O mapping. +config NVMEM_IGNORE_RO + bool "ignore read-only flags" + config NVMEM_IMX_IIM tristate "i.MX IC Identification Module support" depends on ARCH_MXC || COMPILE_TEST diff -ruw linux-6.4/drivers/nvmem/core.c linux-6.4-fbx/drivers/nvmem/core.c --- linux-6.4/drivers/nvmem/core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/nvmem/core.c 2023-05-22 20:06:42.607810285 +0200 @@ -930,8 +930,10 @@ if (rval) goto err_put_device; +#ifndef CONFIG_NVMEM_IGNORE_RO nvmem->read_only = device_property_present(config->dev, "read-only") || config->read_only || !nvmem->reg_write; +#endif #ifdef CONFIG_NVMEM_SYSFS nvmem->dev.groups = nvmem_dev_groups; diff -ruw linux-6.4/drivers/of/Kconfig linux-6.4-fbx/drivers/of/Kconfig --- linux-6.4/drivers/of/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/of/Kconfig 2023-05-22 20:06:42.607810285 +0200 @@ -47,6 +47,11 @@ If unsure, say N here, but this option is safe to enable. +config OF_DTB_BUILTIN_LIST + string "Link given list of DTB files into kernel" + help + Specify filename without .dtb extension + config OF_FLATTREE bool select DTC @@ -102,4 +107,11 @@ config OF_NUMA bool +config OF_CONFIGFS + bool "Device Tree Overlay ConfigFS interface" + select CONFIGFS_FS + select OF_OVERLAY + help + Enable a simple user-space driven DT overlay interface. + endif # OF diff -ruw linux-6.4/drivers/of/Makefile linux-6.4-fbx/drivers/of/Makefile --- linux-6.4/drivers/of/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/of/Makefile 2023-05-22 20:06:42.607810285 +0200 @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y = base.o cpu.o device.o module.o platform.o property.o obj-$(CONFIG_OF_KOBJ) += kobj.o +obj-$(CONFIG_OF_CONFIGFS) += configfs.o obj-$(CONFIG_OF_DYNAMIC) += dynamic.o obj-$(CONFIG_OF_FLATTREE) += fdt.o obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o diff -ruw linux-6.4/drivers/of/fdt.c linux-6.4-fbx/drivers/of/fdt.c --- linux-6.4/drivers/of/fdt.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/of/fdt.c 2023-05-22 20:06:42.611810392 +0200 @@ -29,6 +29,7 @@ #include /* for COMMAND_LINE_SIZE */ #include +#include #include "of_private.h" @@ -787,6 +788,39 @@ return 0; } +/* + * iterate list of built-in dtb to find a compatible match + */ +const void __init *of_fdt_find_compatible_dtb(const char *name) +{ + struct fdt_header { + __be32 magic; + __be32 totalsize; + }; + const struct fdt_header *blob, *best; + unsigned int best_score = ~0; + + best = NULL; + blob = (const struct fdt_header *)__dtb_start; + while ((void *)blob < (void *)__dtb_end && + (be32_to_cpu(blob->magic) == OF_DT_HEADER)) { + unsigned int score; + u32 size; + + score = of_fdt_is_compatible(blob, 0, name); + if (score > 0 && score < best_score) { + best = blob; + best_score = score; + } + + size = be32_to_cpu(blob->totalsize); + blob = (const struct fdt_header *) + PTR_ALIGN((void *)blob + size, STRUCT_ALIGNMENT); + } + + return best; +} + /** * of_flat_dt_is_compatible - Return true if given node has compat in compatible list * @node: node to test diff -ruw linux-6.4/drivers/of/overlay.c linux-6.4-fbx/drivers/of/overlay.c --- linux-6.4/drivers/of/overlay.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/of/overlay.c 2023-06-27 11:47:15.875861725 +0200 @@ -358,7 +358,7 @@ } if (!of_node_check_flag(target->np, OF_OVERLAY)) - pr_err("WARNING: memory leak will occur if overlay removed, property: %pOF/%s\n", + pr_debug("WARNING: memory leak will occur if overlay removed, property: %pOF/%s\n", target->np, new_prop->name); if (ret) { diff -ruw linux-6.4/drivers/pci/controller/Kconfig linux-6.4-fbx/drivers/pci/controller/Kconfig --- linux-6.4/drivers/pci/controller/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pci/controller/Kconfig 2023-05-22 20:06:42.623810711 +0200 @@ -179,7 +179,6 @@ depends on MVEBU_MBUS depends on ARM depends on OF - depends on BROKEN select PCI_BRIDGE_EMUL help Add support for Marvell EBU PCIe controller. This PCIe controller @@ -208,6 +207,12 @@ Say Y here if you want to enable Gen3 PCIe controller support on MediaTek SoCs. +config PCIE_BCM63XX + tristate "BCM63XX SoCs PCIe endpoint driver." + depends on ARCH_BCMBCA || COMPILE_TEST + depends on OF + depends on PCI_MSI + config PCIE_MT7621 tristate "MediaTek MT7621 PCIe controller" depends on SOC_MT7621 || COMPILE_TEST diff -ruw linux-6.4/drivers/pci/controller/Makefile linux-6.4-fbx/drivers/pci/controller/Makefile --- linux-6.4/drivers/pci/controller/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pci/controller/Makefile 2023-05-22 20:06:42.623810711 +0200 @@ -33,6 +33,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o +obj-$(CONFIG_PCIE_BCM63XX) += pcie-bcm63xx.o obj-$(CONFIG_VMD) += vmd.o obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o diff -ruw linux-6.4/drivers/pci/pci-sysfs.c linux-6.4-fbx/drivers/pci/pci-sysfs.c --- linux-6.4/drivers/pci/pci-sysfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pci/pci-sysfs.c 2024-01-26 20:19:34.752196606 +0100 @@ -1149,6 +1149,7 @@ { int i; + mutex_lock(&pdev->sysfs_init_lock); for (i = 0; i < PCI_STD_NUM_BARS; i++) { struct bin_attribute *res_attr; @@ -1164,6 +1165,9 @@ kfree(res_attr); } } + + pdev->sysfs_init_done = 0; + mutex_unlock(&pdev->sysfs_init_lock); } static int pci_create_attr(struct pci_dev *pdev, int num, int write_combine) @@ -1226,6 +1230,12 @@ int i; int retval; + mutex_lock(&pdev->sysfs_init_lock); + if (pdev->sysfs_init_done) { + mutex_unlock(&pdev->sysfs_init_lock); + return 0; + } + /* Expose the PCI resources from this device as files */ for (i = 0; i < PCI_STD_NUM_BARS; i++) { @@ -1239,10 +1249,14 @@ pdev->resource[i].flags & IORESOURCE_PREFETCH) retval = pci_create_attr(pdev, i, 1); if (retval) { + mutex_unlock(&pdev->sysfs_init_lock); pci_remove_resource_files(pdev); return retval; } } + + pdev->sysfs_init_done = 1; + mutex_unlock(&pdev->sysfs_init_lock); return 0; } #else /* !(defined(HAVE_PCI_MMAP) || defined(ARCH_GENERIC_PCI_MMAP_RESOURCE)) */ diff -ruw linux-6.4/drivers/pci/pcie/portdrv.c linux-6.4-fbx/drivers/pci/pcie/portdrv.c --- linux-6.4/drivers/pci/pcie/portdrv.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pci/pcie/portdrv.c 2023-11-22 18:41:18.370269029 +0100 @@ -21,6 +21,8 @@ #include "../pci.h" #include "portdrv.h" +static DEFINE_MUTEX(irq_alloc_mutex); + /* * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must * be one of the first 32 MSI-X entries. Per PCI r3.0, sec 6.8.3.1, MSI @@ -114,16 +116,21 @@ int nr_entries, nvec, pcie_irq; u32 pme = 0, aer = 0, dpc = 0; + mutex_lock(&irq_alloc_mutex); + /* Allocate the maximum possible number of MSI/MSI-X vectors */ nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSI_ENTRIES, PCI_IRQ_MSIX | PCI_IRQ_MSI); - if (nr_entries < 0) + if (nr_entries < 0) { + mutex_unlock(&irq_alloc_mutex); return nr_entries; + } /* See how many and which Interrupt Message Numbers we actually use */ nvec = pcie_message_numbers(dev, mask, &pme, &aer, &dpc); if (nvec > nr_entries) { pci_free_irq_vectors(dev); + mutex_unlock(&irq_alloc_mutex); return -EIO; } @@ -143,9 +150,13 @@ nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec, PCI_IRQ_MSIX | PCI_IRQ_MSI); - if (nr_entries < 0) + if (nr_entries < 0) { + mutex_unlock(&irq_alloc_mutex); return nr_entries; } + } + + mutex_unlock(&irq_alloc_mutex); /* PME, hotplug and bandwidth notification share an MSI/MSI-X vector */ if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | diff -ruw linux-6.4/drivers/pci/probe.c linux-6.4-fbx/drivers/pci/probe.c --- linux-6.4/drivers/pci/probe.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pci/probe.c 2024-01-29 18:35:21.690960369 +0100 @@ -2310,6 +2310,7 @@ return NULL; INIT_LIST_HEAD(&dev->bus_list); + mutex_init(&dev->sysfs_init_lock); dev->dev.type = &pci_dev_type; dev->bus = pci_bus_get(bus); dev->driver_exclusive_resource = (struct resource) { @@ -3270,6 +3271,34 @@ return max; } +/* + * Walks the PCI/PCIe tree to find the first instance of a PCIe device and + * hands off the PCIe bus to pcie_bus_configure_settings to walk the rest. + */ +static int pcie_rescan_bus_configure_settings(struct pci_dev *dev, void *data) +{ + if (pci_is_pcie(dev)) { + struct pci_bus *child, *bus = dev->bus; + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + return 1; + } + return 0; +} + +/** + * pci_bus_configure_settings - Configure bus settings + * @bus: PCI/PCIE bus to configure + * + * Currently only configures PCIe bus settings related to MPS and MRRS. + */ +static void pci_bus_configure_settings(struct pci_bus *bus) +{ + pci_walk_bus(bus, pcie_rescan_bus_configure_settings, NULL); +} + /** * pci_rescan_bus - Scan a PCI bus for devices * @bus: PCI bus to scan @@ -3285,6 +3314,7 @@ max = pci_scan_child_bus(bus); pci_assign_unassigned_bus_resources(bus); + pci_bus_configure_settings(bus); pci_bus_add_devices(bus); return max; diff -ruw linux-6.4/drivers/pci/quirks.c linux-6.4-fbx/drivers/pci/quirks.c --- linux-6.4/drivers/pci/quirks.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pci/quirks.c 2023-06-27 11:47:15.875861725 +0200 @@ -3150,6 +3150,8 @@ dev->is_hotplug_bridge = 1; } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PI7C9X20303SL, + quirk_hotplug_bridge); /* * This is a quirk for the Ricoh MMC controller found as a part of some diff -ruw linux-6.4/drivers/phy/Kconfig linux-6.4-fbx/drivers/phy/Kconfig --- linux-6.4/drivers/phy/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/phy/Kconfig 2023-05-22 20:06:42.691812520 +0200 @@ -71,6 +71,10 @@ functional modes using gpios and sets the attribute max link rate, for CAN drivers. +config XDSL_PHY_API + tristate "xDSL PHY API" + select GENERIC_PHY + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff -ruw linux-6.4/drivers/phy/Makefile linux-6.4-fbx/drivers/phy/Makefile --- linux-6.4/drivers/phy/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/phy/Makefile 2023-05-22 20:06:42.691812520 +0200 @@ -10,6 +10,8 @@ obj-$(CONFIG_PHY_XGENE) += phy-xgene.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o +obj-$(CONFIG_XDSL_PHY_API) += xdsl_phy_api.o + obj-y += allwinner/ \ amlogic/ \ broadcom/ \ diff -ruw linux-6.4/drivers/phy/broadcom/Kconfig linux-6.4-fbx/drivers/phy/broadcom/Kconfig --- linux-6.4/drivers/phy/broadcom/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/phy/broadcom/Kconfig 2023-05-22 20:06:42.691812520 +0200 @@ -39,6 +39,11 @@ help Enable this to support the Broadcom Kona USB 2.0 PHY. +config PHY_BRCM_USB_63138 + tristate "Broadcom 63138 USB 2.0/3.0 PHY Driver" + depends on ARCH_BCMBCA || COMPILE_TEST + select GENERIC_PHY + config PHY_BCM_NS_USB2 tristate "Broadcom Northstar USB 2.0 PHY Driver" depends on ARCH_BCM_IPROC || COMPILE_TEST diff -ruw linux-6.4/drivers/phy/broadcom/Makefile linux-6.4-fbx/drivers/phy/broadcom/Makefile --- linux-6.4/drivers/phy/broadcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/phy/broadcom/Makefile 2023-03-09 15:06:11.376234546 +0100 @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_BCM63XX_USBH) += phy-bcm63xx-usbh.o obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o +obj-$(CONFIG_PHY_BRCM_USB_63138) += phy-brcm-usb-63138.o obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o obj-$(CONFIG_PHY_BCM_NS_USB3) += phy-bcm-ns-usb3.o diff -ruw linux-6.4/drivers/phy/marvell/Kconfig linux-6.4-fbx/drivers/phy/marvell/Kconfig --- linux-6.4/drivers/phy/marvell/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/phy/marvell/Kconfig 2023-03-09 15:22:14.035699334 +0100 @@ -136,3 +136,11 @@ components on MMP3-based boards. To compile this driver as a module, choose M here. + +config PHY_UTMI_CP110 + bool "Marvell CP110 UTMI PHY Driver" + depends on ARCH_MVEBU + depends on OF + help + Enable this to support Marvell USB2.0 PHY driver for Marvell + CP110-based SoCs (A7K and A8K). diff -ruw linux-6.4/drivers/phy/marvell/Makefile linux-6.4-fbx/drivers/phy/marvell/Makefile --- linux-6.4/drivers/phy/marvell/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/phy/marvell/Makefile 2023-03-09 15:22:14.035699334 +0100 @@ -13,3 +13,4 @@ obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o obj-$(CONFIG_PHY_PXA_USB) += phy-pxa-usb.o +obj-$(CONFIG_PHY_UTMI_CP110) += phy-utmi-cp110.o diff -ruw linux-6.4/drivers/pinctrl/bcm/Kconfig linux-6.4-fbx/drivers/pinctrl/bcm/Kconfig --- linux-6.4/drivers/pinctrl/bcm/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pinctrl/bcm/Kconfig 2023-09-01 15:04:29.529632893 +0200 @@ -52,6 +52,16 @@ select REGMAP select GPIO_REGMAP +config PINCTRL_BCM63138 + bool "Broadcom 63138 pinmux driver" + depends on OF && (ARCH_BCMBCA || COMPILE_TEST) + default ARCH_BCMBCA + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + select GPIOLIB_IRQCHIP + config PINCTRL_BCM6318 bool "Broadcom BCM6318 GPIO driver" depends on (BMIPS_GENERIC || COMPILE_TEST) diff -ruw linux-6.4/drivers/pinctrl/bcm/Makefile linux-6.4-fbx/drivers/pinctrl/bcm/Makefile --- linux-6.4/drivers/pinctrl/bcm/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/pinctrl/bcm/Makefile 2023-05-22 20:06:42.723813371 +0200 @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o obj-$(CONFIG_PINCTRL_BCM63268) += pinctrl-bcm63268.o +obj-$(CONFIG_PINCTRL_BCM63138) += pinctrl-bcm63138.o obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o diff -ruw linux-6.4/drivers/platform/Kconfig linux-6.4-fbx/drivers/platform/Kconfig --- linux-6.4/drivers/platform/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/platform/Kconfig 2023-07-20 17:19:14.610365797 +0200 @@ -14,3 +14,11 @@ source "drivers/platform/surface/Kconfig" source "drivers/platform/x86/Kconfig" + +if X86_INTEL_CE +source "drivers/platform/intelce/Kconfig" +endif + +source "drivers/platform/fbxgw7r/Kconfig" + +source "drivers/platform/ipq/Kconfig" diff -ruw linux-6.4/drivers/platform/Makefile linux-6.4-fbx/drivers/platform/Makefile --- linux-6.4/drivers/platform/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/platform/Makefile 2023-07-20 17:19:14.610365797 +0200 @@ -11,3 +11,6 @@ obj-$(CONFIG_GOLDFISH) += goldfish/ obj-$(CONFIG_CHROME_PLATFORMS) += chrome/ obj-$(CONFIG_SURFACE_PLATFORMS) += surface/ +obj-$(CONFIG_X86_INTEL_CE) += intelce/ +obj-$(CONFIG_FBXGW7R_PLATFORM) += fbxgw7r/ +obj-$(CONFIG_QCOM_IPQ_PLATFORM) += ipq/ diff -ruw linux-6.4/drivers/regulator/Kconfig linux-6.4-fbx/drivers/regulator/Kconfig --- linux-6.4/drivers/regulator/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/regulator/Kconfig 2024-04-19 15:59:31.193600561 +0200 @@ -30,6 +30,12 @@ help Say yes here to enable debugging support. +config REGULATOR_FAULT_SENSING + bool "Regulator fault-sensing detection" + help + Add support for fault-sensing gpio which will cause + regulator to be forced-disabled. + config REGULATOR_FIXED_VOLTAGE tristate "Fixed voltage regulator support" help diff -ruw linux-6.4/drivers/rtc/Kconfig linux-6.4-fbx/drivers/rtc/Kconfig --- linux-6.4/drivers/rtc/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/rtc/Kconfig 2024-01-08 17:49:53.079558710 +0100 @@ -1391,6 +1391,15 @@ This driver can also be built as a module. If so, the module will be called rtc-meson-vrtc. +config RTC_DRV_MESON_AXG + tristate "Amlogic Meson AXG RTC + wakeup" + depends on RTC_HCTOSYS + depends on ARCH_MESON || COMPILE_TEST + default m if ARCH_MESON + help + If you say yes here you will get support for the RTC of Amlogic SoCs + as implemented in M3's firmware for AXG platform by Freebox. + config RTC_DRV_OMAP tristate "TI OMAP Real Time Clock" depends on ARCH_OMAP || ARCH_DAVINCI || COMPILE_TEST diff -ruw linux-6.4/drivers/rtc/Makefile linux-6.4-fbx/drivers/rtc/Makefile --- linux-6.4/drivers/rtc/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/rtc/Makefile 2024-01-08 17:49:53.079558710 +0100 @@ -97,6 +97,7 @@ obj-$(CONFIG_RTC_DRV_MAX8997) += rtc-max8997.o obj-$(CONFIG_RTC_DRV_MAX8998) += rtc-max8998.o obj-$(CONFIG_RTC_DRV_MESON_VRTC)+= rtc-meson-vrtc.o +obj-$(CONFIG_RTC_DRV_MESON_AXG) += rtc-meson-axg.o obj-$(CONFIG_RTC_DRV_MC13XXX) += rtc-mc13xxx.o obj-$(CONFIG_RTC_DRV_MCP795) += rtc-mcp795.o obj-$(CONFIG_RTC_DRV_MESON) += rtc-meson.o diff -ruw linux-6.4/drivers/soc/bcm/Kconfig linux-6.4-fbx/drivers/soc/bcm/Kconfig --- linux-6.4/drivers/soc/bcm/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/soc/bcm/Kconfig 2023-05-22 20:06:43.275828054 +0200 @@ -24,7 +24,8 @@ config SOC_BCM63XX bool "Broadcom 63xx SoC drivers" - depends on BMIPS_GENERIC || COMPILE_TEST + depends on BMIPS_GENERIC || ARCH_BCMBCA || COMPILE_TEST + select RESET_CONTROLLER help Enables drivers for the Broadcom 63xx series of chips. Drivers can be enabled individually within this menu. diff -ruw linux-6.4/drivers/soc/bcm/Makefile linux-6.4-fbx/drivers/soc/bcm/Makefile --- linux-6.4/drivers/soc/bcm/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/soc/bcm/Makefile 2023-05-22 20:06:43.275828054 +0200 @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_BCM2835_POWER) += bcm2835-power.o obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o -obj-y += bcm63xx/ obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/ +obj-$(CONFIG_SOC_BCM63XX) += bcm63xx/ diff -ruw linux-6.4/drivers/soc/bcm/bcm63xx/Kconfig linux-6.4-fbx/drivers/soc/bcm/bcm63xx/Kconfig --- linux-6.4/drivers/soc/bcm/bcm63xx/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/Kconfig 2023-05-22 20:06:43.275828054 +0200 @@ -9,6 +9,31 @@ This enables support for the BCM63xx power domains controller on BCM6318, BCM6328, BCM6362 and BCM63268 SoCs. +config SOC_BCM63XX_RDP + bool "rdp subsystem" + depends on ARCH_BCMBCA || COMPILE_TEST + +config SOC_BCM63XX_XRDP + tristate "xrdp subsystem" + depends on ARCH_BCMBCA || COMPILE_TEST + select UBUS4_BCM63158 + +config SOC_BCM63XX_XRDP_IOCTL + bool "ioctl interface" + depends on SOC_BCM63XX_XRDP + +config UBUS4_BCM63158 + bool "Broadcom 63158 UBUS4 driver" + depends on ARCH_BCMBCA || COMPILE_TEST + +config SOC_MEMC_BCM63158 + tristate "Broadcom 63158 MEMC driver" + depends on ARCH_BCMBCA || COMPILE_TEST + +config PROCMON_BCM63158 + bool "Broadcom 63158 PROCMON driver" + depends on ARCH_BCMBCA || COMPILE_TEST + endif # SOC_BCM63XX config BCM_PMB @@ -19,3 +44,4 @@ help This enables support for the Broadcom's PMB (Power Management Bus) that is used for disabling and enabling SoC devices. + diff -ruw linux-6.4/drivers/soc/bcm/bcm63xx/Makefile linux-6.4-fbx/drivers/soc/bcm/bcm63xx/Makefile --- linux-6.4/drivers/soc/bcm/bcm63xx/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/Makefile 2023-05-22 20:06:43.275828054 +0200 @@ -1,3 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_BCM63XX_POWER) += bcm63xx-power.o obj-$(CONFIG_BCM_PMB) += bcm-pmb.o + +obj-$(CONFIG_ARCH_BCMBCA) += pmc.o +obj-$(CONFIG_SOC_BCM63XX_RDP) += rdp/ +obj-$(CONFIG_SOC_BCM63XX_XRDP) += xrdp/ +obj-$(CONFIG_UBUS4_BCM63158) += ubus4-bcm63158.o +obj-$(CONFIG_PROCMON_BCM63158) += procmon-bcm63158.o +obj-$(CONFIG_SOC_MEMC_BCM63158) += memc-bcm63158.o diff -ruw linux-6.4/drivers/soc/qcom/Kconfig linux-6.4-fbx/drivers/soc/qcom/Kconfig --- linux-6.4/drivers/soc/qcom/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/soc/qcom/Kconfig 2024-04-19 15:59:31.193600561 +0200 @@ -279,4 +279,8 @@ tristate select QCOM_SCM +config QCOM_IMEM_RESET_REASON + tristate "QCOM IMEM based reset reason" + depends on ARCH_QCOM || COMPILE_TEST + endmenu diff -ruw linux-6.4/drivers/soc/qcom/Makefile linux-6.4-fbx/drivers/soc/qcom/Makefile --- linux-6.4/drivers/soc/qcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/soc/qcom/Makefile 2024-04-19 15:59:31.193600561 +0200 @@ -34,3 +34,5 @@ obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o qcom_ice-objs += ice.o obj-$(CONFIG_QCOM_INLINE_CRYPTO_ENGINE) += qcom_ice.o + +obj-$(CONFIG_QCOM_IMEM_RESET_REASON) += qcom-imem-reset-reason.o diff -ruw linux-6.4/drivers/spi/Kconfig linux-6.4-fbx/drivers/spi/Kconfig --- linux-6.4/drivers/spi/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/spi/Kconfig 2023-05-22 20:06:43.315829118 +0200 @@ -771,6 +771,12 @@ help This selects a driver for the PPC4xx SPI Controller. +config SPI_TDM_ORION + tristate "Orion TDM SPI master" + depends on PLAT_ORION + help + This enables using the TDM SPI master controller on the Orion chips. + config SPI_PXA2XX tristate "PXA2xx SSP SPI master" depends on ARCH_PXA || ARCH_MMP || PCI || ACPI || COMPILE_TEST diff -ruw linux-6.4/drivers/spi/Makefile linux-6.4-fbx/drivers/spi/Makefile --- linux-6.4/drivers/spi/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/spi/Makefile 2023-05-22 20:06:43.315829118 +0200 @@ -99,6 +99,7 @@ obj-$(CONFIG_SPI_PCI1XXXX) += spi-pci1xxxx.o obj-$(CONFIG_SPI_PIC32) += spi-pic32.o obj-$(CONFIG_SPI_PIC32_SQI) += spi-pic32-sqi.o +obj-$(CONFIG_SPI_TDM_ORION) += orion_tdm_spi.o obj-$(CONFIG_SPI_PL022) += spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff -ruw linux-6.4/drivers/spi/spi-bcm63xx-hsspi.c linux-6.4-fbx/drivers/spi/spi-bcm63xx-hsspi.c --- linux-6.4/drivers/spi/spi-bcm63xx-hsspi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/spi/spi-bcm63xx-hsspi.c 2023-05-22 20:06:43.319829224 +0200 @@ -62,7 +62,7 @@ #define HSSPI_PINGPONG_STATUS_SRC_BUSY BIT(1) #define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) -#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff +#define CLK_CTRL_FREQ_CTRL_MASK 0x000007ff #define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) #define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) @@ -143,6 +143,8 @@ u32 xfer_mode; u32 prepend_cnt; u8 *prepend_buf; + + int dummy_cs; }; static ssize_t wait_mode_show(struct device *dev, struct device_attribute *attr, @@ -445,6 +447,8 @@ u32 reg; reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); + if (reg > CLK_CTRL_FREQ_CTRL_MASK) + reg = CLK_CTRL_FREQ_CTRL_MASK; __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile)); @@ -465,6 +469,17 @@ mutex_unlock(&bs->bus_mutex); } +/* + * use the DT-specified dummy chip select or fallback to the previous + * behaviour (dummy_cs = !cs). + */ +static inline int bcm63xx_hsspi_get_dummy_cs(struct bcm63xx_hsspi *bs, int cs) +{ + if (bs->dummy_cs >= 0) + return bs->dummy_cs; + return !cs; +} + static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) { struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); @@ -475,6 +490,7 @@ const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; u32 reg = 0; + int dummy_cs = bcm63xx_hsspi_get_dummy_cs(bs, chip_select); bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); if (!t->cs_off) @@ -520,7 +536,7 @@ __raw_writel(HSSPI_PINGx_CMD_DONE(0), bs->regs + HSSPI_INT_MASK_REG); - reg = !chip_select << PINGPONG_CMD_SS_SHIFT | + reg = dummy_cs << PINGPONG_CMD_SS_SHIFT | chip_select << PINGPONG_CMD_PROFILE_SHIFT | PINGPONG_COMMAND_START_NOW; __raw_writel(reg, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); @@ -600,7 +616,7 @@ * e. At the end restore the polarities again to their default values. */ - dummy_cs = !spi_get_chipselect(spi, 0); + dummy_cs = bcm63xx_hsspi_get_dummy_cs(bs, spi_get_chipselect(spi, 0)); bcm63xx_hsspi_set_cs(bs, dummy_cs, true); list_for_each_entry(t, &msg->transfers, transfer_list) { @@ -731,6 +747,7 @@ int irq, ret; u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; struct reset_control *reset; + u32 dummy_cs; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -799,6 +816,13 @@ goto out_put_master; } + if (of_property_read_u32(dev->of_node, "broadcom,dummy-cs", + &dummy_cs) < 0 || dummy_cs >= 8) + bs->dummy_cs = -1; + else + bs->dummy_cs = dummy_cs; + dev_info(&pdev->dev, "using dummy chip select %d\n", bs->dummy_cs); + mutex_init(&bs->bus_mutex); mutex_init(&bs->msg_mutex); init_completion(&bs->done); diff -ruw linux-6.4/drivers/tee/optee/smc_abi.c linux-6.4-fbx/drivers/tee/optee/smc_abi.c --- linux-6.4/drivers/tee/optee/smc_abi.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/tee/optee/smc_abi.c 2023-06-27 11:47:15.907862595 +0200 @@ -1782,9 +1782,14 @@ if (optee->smc.sec_caps & OPTEE_SMC_SEC_CAP_DYNAMIC_SHM) pr_info("dynamic shared memory is enabled\n"); + if (device_property_present(&pdev->dev, "skip-enumeration")) + optee->scan_bus_done = true; + + if (!optee->scan_bus_done) { rc = optee_enumerate_devices(PTA_CMD_GET_DEVICES); if (rc) goto err_disable_shm_cache; + } pr_info("initialized driver\n"); return 0; diff -ruw linux-6.4/drivers/thermal/thermal_core.c linux-6.4-fbx/drivers/thermal/thermal_core.c --- linux-6.4/drivers/thermal/thermal_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/thermal/thermal_core.c 2023-05-22 20:06:43.535834969 +0200 @@ -810,6 +810,7 @@ /** * __thermal_cooling_device_register() - register a new thermal cooling device + * @dev: parent device * @np: a pointer to a device tree node. * @type: the thermal cooling device type. * @devdata: device private data. @@ -825,7 +826,7 @@ * ERR_PTR. Caller must check return value with IS_ERR*() helpers. */ static struct thermal_cooling_device * -__thermal_cooling_device_register(struct device_node *np, +__thermal_cooling_device_register(struct device *pdev, struct device_node *np, const char *type, void *devdata, const struct thermal_cooling_device_ops *ops) { @@ -873,6 +874,7 @@ ret = dev_set_name(&cdev->device, "cooling_device%d", cdev->id); if (ret) goto out_cooling_dev; + cdev->device.parent = pdev; ret = device_register(&cdev->device); if (ret) { @@ -926,11 +928,30 @@ thermal_cooling_device_register(const char *type, void *devdata, const struct thermal_cooling_device_ops *ops) { - return __thermal_cooling_device_register(NULL, type, devdata, ops); + return __thermal_cooling_device_register(NULL, NULL, type, devdata, ops); } EXPORT_SYMBOL_GPL(thermal_cooling_device_register); /** + * thermal_cooling_device_register_with_parent() - register a new thermal cooling device + * @pdev: parent device + * @type: the thermal cooling device type. + * @devdata: device private data. + * @ops: standard thermal cooling devices callbacks. + * + * Same as thermal_cooling_device_register but take also the parent device. + * Then, hwpath will include the parent device to uniquely identify this device + */ +struct thermal_cooling_device * +thermal_cooling_device_register_with_parent(struct device *pdev, + const char *type, void *devdata, + const struct thermal_cooling_device_ops *ops) +{ + return __thermal_cooling_device_register(pdev, NULL, type, devdata, ops); +} +EXPORT_SYMBOL_GPL(thermal_cooling_device_register_with_parent); + +/** * thermal_of_cooling_device_register() - register an OF thermal cooling device * @np: a pointer to a device tree node. * @type: the thermal cooling device type. @@ -950,7 +971,7 @@ const char *type, void *devdata, const struct thermal_cooling_device_ops *ops) { - return __thermal_cooling_device_register(np, type, devdata, ops); + return __thermal_cooling_device_register(NULL, np, type, devdata, ops); } EXPORT_SYMBOL_GPL(thermal_of_cooling_device_register); @@ -990,7 +1011,7 @@ if (!ptr) return ERR_PTR(-ENOMEM); - tcd = __thermal_cooling_device_register(np, type, devdata, ops); + tcd = __thermal_cooling_device_register(NULL, np, type, devdata, ops); if (IS_ERR(tcd)) { devres_free(ptr); return tcd; diff -ruw linux-6.4/drivers/tty/serial/Kconfig linux-6.4-fbx/drivers/tty/serial/Kconfig --- linux-6.4/drivers/tty/serial/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/tty/serial/Kconfig 2023-06-27 11:47:15.911862703 +0200 @@ -1075,6 +1075,11 @@ BCM68xx (PON) BCM7xxx (STB) - DOCSIS console +config SERIAL_BCM63XX_HS + tristate "Broadcom BCM63xx HS UART support" + select SERIAL_CORE + depends on ARCH_BCMBCA || COMPILE_TEST + config SERIAL_BCM63XX_CONSOLE bool "Console on BCM63xx serial port" depends on SERIAL_BCM63XX=y diff -ruw linux-6.4/drivers/tty/serial/Makefile linux-6.4-fbx/drivers/tty/serial/Makefile --- linux-6.4/drivers/tty/serial/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/tty/serial/Makefile 2023-05-22 20:06:43.571835927 +0200 @@ -30,6 +30,7 @@ obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o +obj-$(CONFIG_SERIAL_BCM63XX_HS) += bcm63xx-hs-uart.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_MAX310X) += max310x.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o diff -ruw linux-6.4/drivers/usb/host/Kconfig linux-6.4-fbx/drivers/usb/host/Kconfig --- linux-6.4/drivers/usb/host/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/usb/host/Kconfig 2023-05-22 20:06:43.695839225 +0200 @@ -78,13 +78,13 @@ If unsure, say N. config USB_XHCI_MVEBU - tristate "xHCI support for Marvell Armada 375/38x/37xx" + tristate "xHCI support for Marvell Armada 375/38x/37xx/70x0/80x0" select USB_XHCI_PLATFORM depends on HAS_IOMEM depends on ARCH_MVEBU || COMPILE_TEST help Say 'Y' to enable the support for the xHCI host controller - found in Marvell Armada 375/38x/37xx ARM SOCs. + found in Marvell Armada 375/38x/37xx/70x0/80x0 ARM SOCs. config USB_XHCI_RCAR tristate "xHCI support for Renesas R-Car SoCs" @@ -690,6 +690,10 @@ If unsure, say N. +config USB_BCM63158 + tristate "Broadcom BCM63158 SoC USB host driver" + depends on ARCH_BCMBCA || COMPILE_TEST + config USB_HCD_SSB tristate "SSB usb host driver" depends on SSB diff -ruw linux-6.4/drivers/usb/host/Makefile linux-6.4-fbx/drivers/usb/host/Makefile --- linux-6.4/drivers/usb/host/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/usb/host/Makefile 2023-05-22 20:06:43.695839225 +0200 @@ -85,3 +85,4 @@ obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o obj-$(CONFIG_USB_MAX3421_HCD) += max3421-hcd.o obj-$(CONFIG_USB_XEN_HCD) += xen-hcd.o +obj-$(CONFIG_USB_BCM63158) += usb-bcm63158.o diff -ruw linux-6.4/drivers/usb/host/xhci-plat.c linux-6.4-fbx/drivers/usb/host/xhci-plat.c --- linux-6.4/drivers/usb/host/xhci-plat.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/usb/host/xhci-plat.c 2023-11-16 16:11:31.633535041 +0100 @@ -133,6 +133,8 @@ .compatible = "marvell,armada3700-xhci", .data = &xhci_plat_marvell_armada3700, }, { + .compatible = "marvell,armada-8k-xhci", + }, { .compatible = "brcm,xhci-brcm-v2", .data = &xhci_plat_brcm, }, { @@ -294,10 +296,6 @@ xhci->shared_hcd->usb_phy = devm_usb_get_phy_by_phandle(sysdev, "usb-phy", 1); if (IS_ERR(xhci->shared_hcd->usb_phy)) { - if (PTR_ERR(xhci->shared_hcd->usb_phy) != -ENODEV) - dev_err(sysdev, "%s get usb3phy fail (ret=%d)\n", - __func__, - (int)PTR_ERR(xhci->shared_hcd->usb_phy)); xhci->shared_hcd->usb_phy = NULL; } else { ret = usb_phy_init(xhci->shared_hcd->usb_phy); diff -ruw linux-6.4/drivers/usb/host/xhci-ring.c linux-6.4-fbx/drivers/usb/host/xhci-ring.c --- linux-6.4/drivers/usb/host/xhci-ring.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/usb/host/xhci-ring.c 2023-09-01 15:04:29.533633001 +0200 @@ -1890,7 +1890,8 @@ } /* We might get interrupts after shared_hcd is removed */ - if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL) { + if (port->rhub == &xhci->usb3_rhub && xhci->shared_hcd == NULL && + !xhci_has_one_roothub(xhci)) { xhci_dbg(xhci, "ignore port event for removed USB3 hcd\n"); bogus_port_status = true; goto cleanup; diff -ruw linux-6.4/drivers/usb/storage/usb.c linux-6.4-fbx/drivers/usb/storage/usb.c --- linux-6.4/drivers/usb/storage/usb.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/usb/storage/usb.c 2024-02-13 16:56:46.401367196 +0100 @@ -67,7 +67,7 @@ MODULE_DESCRIPTION("USB Mass Storage driver for Linux"); MODULE_LICENSE("GPL"); -static unsigned int delay_use = 1; +static unsigned int delay_use = 5; module_param(delay_use, uint, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(delay_use, "seconds to delay before using a new device"); diff -ruw linux-6.4/drivers/video/Kconfig linux-6.4-fbx/drivers/video/Kconfig --- linux-6.4/drivers/video/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/video/Kconfig 2023-05-22 20:06:43.791841779 +0200 @@ -59,5 +59,4 @@ endif - endmenu diff -ruw linux-6.4/drivers/video/fbdev/Kconfig linux-6.4-fbx/drivers/video/fbdev/Kconfig --- linux-6.4/drivers/video/fbdev/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/video/fbdev/Kconfig 2023-05-22 20:06:43.799841992 +0200 @@ -2208,6 +2208,24 @@ called sm712fb. If you want to compile it as a module, say M here and read . +config FB_SSD1320 + tristate "SSD1320 OLED driver" + depends on FB && SPI + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + select FB_BACKLIGHT + +config FB_SSD1327 + tristate "SSD1327 OLED driver" + depends on FB && SPI + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + select FB_BACKLIGHT + source "drivers/video/fbdev/omap/Kconfig" source "drivers/video/fbdev/omap2/Kconfig" source "drivers/video/fbdev/mmp/Kconfig" diff -ruw linux-6.4/drivers/video/fbdev/Makefile linux-6.4-fbx/drivers/video/fbdev/Makefile --- linux-6.4/drivers/video/fbdev/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/drivers/video/fbdev/Makefile 2023-05-22 20:06:43.799841992 +0200 @@ -126,6 +126,8 @@ obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o obj-$(CONFIG_FB_SIMPLE) += simplefb.o +obj-$(CONFIG_FB_SSD1327) += ssd1327.o +obj-$(CONFIG_FB_SSD1320) += ssd1320.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff -ruw linux-6.4/fs/Kconfig linux-6.4-fbx/fs/Kconfig --- linux-6.4/fs/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/Kconfig 2023-06-27 11:47:15.923863029 +0200 @@ -156,6 +156,7 @@ source "fs/exfat/Kconfig" source "fs/ntfs/Kconfig" source "fs/ntfs3/Kconfig" +source "fs/exfat-fbx/Kconfig" endmenu endif # BLOCK diff -ruw linux-6.4/fs/Makefile linux-6.4-fbx/fs/Makefile --- linux-6.4/fs/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/Makefile 2023-06-27 11:47:15.923863029 +0200 @@ -135,3 +135,4 @@ obj-$(CONFIG_EROFS_FS) += erofs/ obj-$(CONFIG_VBOXSF_FS) += vboxsf/ obj-$(CONFIG_ZONEFS_FS) += zonefs/ +obj-$(CONFIG_EXFAT_FS_FBX) += exfat-fbx/ diff -ruw linux-6.4/fs/exec.c linux-6.4-fbx/fs/exec.c --- linux-6.4/fs/exec.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/exec.c 2023-05-22 20:06:44.067849120 +0200 @@ -1895,6 +1895,23 @@ return PTR_ERR(filename); /* + * handle current->exec_mode: + * - if unlimited, then nothing to do. + * - if once, then set it to denied and continue (next execve + * after this one will fail). + * - if denied, then effectively fail the execve call with EPERM. + */ + switch (current->exec_mode) { + case EXEC_MODE_UNLIMITED: + break; + case EXEC_MODE_ONCE: + current->exec_mode = EXEC_MODE_DENIED; + break; + case EXEC_MODE_DENIED: + return -EPERM; + } + + /* * We move the actual failure in case of RLIMIT_NPROC excess from * set*uid() to execve() because too many poorly written programs * don't check setuid() return code. Here we additionally recheck diff -ruw linux-6.4/fs/proc/array.c linux-6.4-fbx/fs/proc/array.c --- linux-6.4/fs/proc/array.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/proc/array.c 2023-05-22 20:06:44.315855717 +0200 @@ -145,6 +145,21 @@ return task_state_array[task_state_index(tsk)]; } +static const char *const task_exec_mode_array[] = { + "0 (Denied)", + "1 (Once)", + "2 (Unlimited)", +}; + +static inline const char *get_task_exec_mode(struct task_struct *tsk) +{ + unsigned int exec_mode = tsk->exec_mode; + + if (exec_mode > EXEC_MODE_UNLIMITED) + return "? (Invalid)"; + return task_exec_mode_array[exec_mode]; +} + static inline void task_state(struct seq_file *m, struct pid_namespace *ns, struct pid *pid, struct task_struct *p) { @@ -403,6 +418,12 @@ seq_putc(m, '\n'); } +static inline void task_exec_mode(struct seq_file *m, + struct task_struct *p) +{ + seq_printf(m, "Exec mode: %s\n", get_task_exec_mode(p)); +} + static void task_cpus_allowed(struct seq_file *m, struct task_struct *task) { seq_printf(m, "Cpus_allowed:\t%*pb\n", @@ -455,6 +476,7 @@ task_cpus_allowed(m, task); cpuset_task_status_allowed(m, task); task_context_switch_counts(m, task); + task_exec_mode(m, task); return 0; } diff -ruw linux-6.4/fs/pstore/inode.c linux-6.4-fbx/fs/pstore/inode.c --- linux-6.4/fs/pstore/inode.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/pstore/inode.c 2023-05-22 20:06:44.323855930 +0200 @@ -371,9 +371,10 @@ goto fail; inode->i_mode = S_IFREG | 0444; inode->i_fop = &pstore_file_operations; - scnprintf(name, sizeof(name), "%s-%s-%llu%s", + scnprintf(name, sizeof(name), "%s-%s-%s%llu%s", pstore_type_to_name(record->type), - record->psi->name, record->id, + record->psi->name, record->old ? "old-" : "", + record->id, record->compressed ? ".enc.z" : ""); private = kzalloc(sizeof(*private), GFP_KERNEL); diff -ruw linux-6.4/fs/pstore/ram.c linux-6.4-fbx/fs/pstore/ram.c --- linux-6.4/fs/pstore/ram.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/pstore/ram.c 2023-05-22 20:06:44.323855930 +0200 @@ -137,6 +137,7 @@ record->type = prz->type; record->id = id; + record->old = prz->old_zone; return prz; } @@ -481,7 +482,7 @@ static int ramoops_init_przs(const char *name, struct device *dev, struct ramoops_context *cxt, struct persistent_ram_zone ***przs, - phys_addr_t *paddr, size_t mem_sz, + phys_addr_t *paddr, void *vaddr, size_t mem_sz, ssize_t record_size, unsigned int *cnt, u32 sig, u32 flags) { @@ -545,7 +546,7 @@ else label = kasprintf(GFP_KERNEL, "ramoops:%s(%d/%d)", name, i, *cnt - 1); - prz_ar[i] = persistent_ram_new(*paddr, zone_sz, sig, + prz_ar[i] = persistent_ram_new(*paddr, vaddr, zone_sz, sig, &cxt->ecc_info, cxt->memtype, flags, label); kfree(label); @@ -578,7 +579,7 @@ static int ramoops_init_prz(const char *name, struct device *dev, struct ramoops_context *cxt, struct persistent_ram_zone **prz, - phys_addr_t *paddr, size_t sz, u32 sig) + phys_addr_t *paddr, void *vaddr, size_t sz, u32 sig) { char *label; @@ -593,7 +594,7 @@ } label = kasprintf(GFP_KERNEL, "ramoops:%s", name); - *prz = persistent_ram_new(*paddr, sz, sig, &cxt->ecc_info, + *prz = persistent_ram_new(*paddr, vaddr, sz, sig, &cxt->ecc_info, cxt->memtype, PRZ_FLAG_ZAP_OLD, label); kfree(label); if (IS_ERR(*prz)) { @@ -781,17 +782,20 @@ dump_mem_sz = cxt->size - cxt->console_size - cxt->ftrace_size - cxt->pmsg_size; err = ramoops_init_przs("dmesg", dev, cxt, &cxt->dprzs, &paddr, + pdata->mem_ptr, dump_mem_sz, cxt->record_size, &cxt->max_dump_cnt, 0, 0); if (err) goto fail_init; err = ramoops_init_prz("console", dev, cxt, &cxt->cprz, &paddr, + pdata->mem_ptr, cxt->console_size, 0); if (err) goto fail_init; err = ramoops_init_prz("pmsg", dev, cxt, &cxt->mprz, &paddr, + pdata->mem_ptr, cxt->pmsg_size, 0); if (err) goto fail_init; @@ -800,6 +804,7 @@ ? nr_cpu_ids : 1; err = ramoops_init_przs("ftrace", dev, cxt, &cxt->fprzs, &paddr, + pdata->mem_ptr, cxt->ftrace_size, -1, &cxt->max_ftrace_cnt, LINUX_VERSION_CODE, (cxt->flags & RAMOOPS_FLAG_FTRACE_PER_CPU) diff -ruw linux-6.4/fs/pstore/ram_core.c linux-6.4-fbx/fs/pstore/ram_core.c --- linux-6.4/fs/pstore/ram_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/pstore/ram_core.c 2023-05-22 20:06:44.323855930 +0200 @@ -35,6 +35,7 @@ uint32_t sig; atomic_t start; atomic_t size; + atomic_t flags; uint8_t data[]; }; @@ -394,6 +395,7 @@ { atomic_set(&prz->buffer->start, 0); atomic_set(&prz->buffer->size, 0); + atomic_set(&prz->buffer->flags, 0); persistent_ram_update_header_ecc(prz); } @@ -480,13 +482,16 @@ return va; } -static int persistent_ram_buffer_map(phys_addr_t start, phys_addr_t size, +static int persistent_ram_buffer_map(phys_addr_t start, void *vaddr, + phys_addr_t size, struct persistent_ram_zone *prz, int memtype) { prz->paddr = start; prz->size = size; - if (pfn_valid(start >> PAGE_SHIFT)) + if (vaddr) + prz->vaddr = vaddr; + else if (pfn_valid(start >> PAGE_SHIFT)) prz->vaddr = persistent_ram_vmap(start, size, memtype); else prz->vaddr = persistent_ram_iomap(start, size, memtype, @@ -533,6 +538,15 @@ pr_debug("found existing buffer, size %zu, start %zu\n", buffer_size(prz), buffer_start(prz)); persistent_ram_save_old(prz); + + if (atomic_read(&prz->buffer->flags) > 0) { + pr_info("old ramoops!\n"); + prz->old_zone = true; + } else { + pr_info("fresh ramoops!\n"); + atomic_set(&prz->buffer->flags, 1); + } + persistent_ram_update_header_ecc(prz); } } else { pr_debug("no valid data in buffer (sig = 0x%08x)\n", @@ -582,7 +596,8 @@ *_prz = NULL; } -struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, size_t size, +struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, + void *vaddr, size_t size, u32 sig, struct persistent_ram_ecc_info *ecc_info, unsigned int memtype, u32 flags, char *label) { @@ -600,7 +615,7 @@ prz->flags = flags; prz->label = kstrdup(label, GFP_KERNEL); - ret = persistent_ram_buffer_map(start, size, prz, memtype); + ret = persistent_ram_buffer_map(start, vaddr, size, prz, memtype); if (ret) goto err; diff -ruw linux-6.4/fs/pstore/ram_internal.h linux-6.4-fbx/fs/pstore/ram_internal.h --- linux-6.4/fs/pstore/ram_internal.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/pstore/ram_internal.h 2023-05-22 20:06:44.323855930 +0200 @@ -55,6 +55,10 @@ * @old_log_size: * bytes contained in @old_log * + * @old_zone: + * tells whether the zone has just been freshly created, and has + * been read for the first time, this boot, or if it is old, and + * has been created many boots ago. */ struct persistent_ram_zone { phys_addr_t paddr; @@ -77,9 +81,12 @@ char *old_log; size_t old_log_size; + + bool old_zone; }; -struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, size_t size, +struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, + void *addr, size_t size, u32 sig, struct persistent_ram_ecc_info *ecc_info, unsigned int memtype, u32 flags, char *label); void persistent_ram_free(struct persistent_ram_zone **_prz); diff -ruw linux-6.4/fs/smb/common/smb2pdu.h linux-6.4-fbx/fs/smb/common/smb2pdu.h --- linux-6.4/fs/smb/common/smb2pdu.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/common/smb2pdu.h 2024-01-25 13:36:32.714984559 +0100 @@ -1206,6 +1206,7 @@ #define SMB2_LEASE_WRITE_CACHING_LE cpu_to_le32(0x04) #define SMB2_LEASE_FLAG_BREAK_IN_PROGRESS_LE cpu_to_le32(0x02) +#define SMB2_LEASE_FLAG_PARENT_LEASE_KEY_SET_LE cpu_to_le32(0x04) #define SMB2_LEASE_KEY_SIZE 16 diff -ruw linux-6.4/fs/smb/server/Kconfig linux-6.4-fbx/fs/smb/server/Kconfig --- linux-6.4/fs/smb/server/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/Kconfig 2023-11-07 13:38:44.038256036 +0100 @@ -56,6 +56,16 @@ SMB Direct allows transferring SMB packets over RDMA. If unsure, say N. +config SMB_INSECURE_SERVER + bool "Support for insecure SMB1/CIFS and SMB2.0 protocols" + depends on SMB_SERVER + select CRYPTO_MD4 + default n + + help + This enables deprecated insecure protocols dialects: SMB1/CIFS + and SMB2.0 + endif config SMB_SERVER_CHECK_CAP_NET_ADMIN diff -ruw linux-6.4/fs/smb/server/Makefile linux-6.4-fbx/fs/smb/server/Makefile --- linux-6.4/fs/smb/server/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/Makefile 2023-11-07 13:38:44.038256036 +0100 @@ -18,3 +18,4 @@ $(obj)/ksmbd_spnego_negtokentarg.asn1.o: $(obj)/ksmbd_spnego_negtokentarg.asn1.c $(obj)/ksmbd_spnego_negtokentarg.asn1.h ksmbd-$(CONFIG_SMB_SERVER_SMBDIRECT) += transport_rdma.o +ksmbd-$(CONFIG_SMB_INSECURE_SERVER) += smb1pdu.o smb1ops.o smb1misc.o netmisc.o diff -ruw linux-6.4/fs/smb/server/asn1.c linux-6.4-fbx/fs/smb/server/asn1.c --- linux-6.4/fs/smb/server/asn1.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/asn1.c 2024-01-25 13:36:32.714984559 +0100 @@ -214,12 +214,15 @@ { struct ksmbd_conn *conn = context; - conn->mechToken = kmalloc(vlen + 1, GFP_KERNEL); + if (!vlen) + return -EINVAL; + + conn->mechToken = kmemdup_nul(value, vlen, GFP_KERNEL); if (!conn->mechToken) return -ENOMEM; - memcpy(conn->mechToken, value, vlen); - conn->mechToken[vlen] = '\0'; + conn->mechTokenLen = (unsigned int)vlen; + return 0; } diff -ruw linux-6.4/fs/smb/server/auth.c linux-6.4-fbx/fs/smb/server/auth.c --- linux-6.4/fs/smb/server/auth.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/auth.c 2023-11-07 13:38:44.038256036 +0100 @@ -68,6 +68,126 @@ { memcpy(buf, NEGOTIATE_GSS_HEADER, AUTH_GSS_LENGTH); } +#ifdef CONFIG_SMB_INSECURE_SERVER +static void +str_to_key(unsigned char *str, unsigned char *key) +{ + int i; + + key[0] = str[0] >> 1; + key[1] = ((str[0] & 0x01) << 6) | (str[1] >> 2); + key[2] = ((str[1] & 0x03) << 5) | (str[2] >> 3); + key[3] = ((str[2] & 0x07) << 4) | (str[3] >> 4); + key[4] = ((str[3] & 0x0F) << 3) | (str[4] >> 5); + key[5] = ((str[4] & 0x1F) << 2) | (str[5] >> 6); + key[6] = ((str[5] & 0x3F) << 1) | (str[6] >> 7); + key[7] = str[6] & 0x7F; + for (i = 0; i < 8; i++) + key[i] = (key[i] << 1); +} + +static int +smbhash(unsigned char *out, const unsigned char *in, unsigned char *key) +{ + unsigned char key2[8]; + struct des_ctx ctx; + + if (fips_enabled) { + ksmbd_debug(AUTH, "FIPS compliance enabled: DES not permitted\n"); + return -ENOENT; + } + + str_to_key(key, key2); + des_expand_key(&ctx, key2, DES_KEY_SIZE); + des_encrypt(&ctx, out, in); + memzero_explicit(&ctx, sizeof(ctx)); + return 0; +} + +static int ksmbd_enc_p24(unsigned char *p21, const unsigned char *c8, unsigned char *p24) +{ + int rc; + + rc = smbhash(p24, c8, p21); + if (rc) + return rc; + rc = smbhash(p24 + 8, c8, p21 + 7); + if (rc) + return rc; + return smbhash(p24 + 16, c8, p21 + 14); +} + +/* produce a md4 message digest from data of length n bytes */ +static int ksmbd_enc_md4(unsigned char *md4_hash, unsigned char *link_str, + int link_len) +{ + int rc; + struct ksmbd_crypto_ctx *ctx; + + ctx = ksmbd_crypto_ctx_find_md4(); + if (!ctx) { + ksmbd_debug(AUTH, "Crypto md4 allocation error\n"); + return -ENOMEM; + } + + rc = crypto_shash_init(CRYPTO_MD4(ctx)); + if (rc) { + ksmbd_debug(AUTH, "Could not init md4 shash\n"); + goto out; + } + + rc = crypto_shash_update(CRYPTO_MD4(ctx), link_str, link_len); + if (rc) { + ksmbd_debug(AUTH, "Could not update with link_str\n"); + goto out; + } + + rc = crypto_shash_final(CRYPTO_MD4(ctx), md4_hash); + if (rc) + ksmbd_debug(AUTH, "Could not generate md4 hash\n"); +out: + ksmbd_release_crypto_ctx(ctx); + return rc; +} + +static int ksmbd_enc_update_sess_key(unsigned char *md5_hash, char *nonce, + char *server_challenge, int len) +{ + int rc; + struct ksmbd_crypto_ctx *ctx; + + ctx = ksmbd_crypto_ctx_find_md5(); + if (!ctx) { + ksmbd_debug(AUTH, "Crypto md5 allocation error\n"); + return -ENOMEM; + } + + rc = crypto_shash_init(CRYPTO_MD5(ctx)); + if (rc) { + ksmbd_debug(AUTH, "Could not init md5 shash\n"); + goto out; + } + + rc = crypto_shash_update(CRYPTO_MD5(ctx), server_challenge, len); + if (rc) { + ksmbd_debug(AUTH, "Could not update with challenge\n"); + goto out; + } + + rc = crypto_shash_update(CRYPTO_MD5(ctx), nonce, len); + if (rc) { + ksmbd_debug(AUTH, "Could not update with nonce\n"); + goto out; + } + + rc = crypto_shash_final(CRYPTO_MD5(ctx), md5_hash); + if (rc) + ksmbd_debug(AUTH, "Could not generate md5 hash\n"); +out: + ksmbd_release_crypto_ctx(ctx); + return rc; +} +#endif /** * ksmbd_gen_sess_key() - function to generate session key @@ -206,6 +326,46 @@ return ret; } +// XXX missing config_smb_insecure_server ? +/** + * ksmbd_auth_ntlm() - NTLM authentication handler + * @sess: session of connection + * @pw_buf: NTLM challenge response + * @passkey: user password + * + * Return: 0 on success, error number on error + */ +#ifdef CONFIG_SMB_INSECURE_SERVER +int ksmbd_auth_ntlm(struct ksmbd_session *sess, char *pw_buf, char *cryptkey) +{ + int rc; + unsigned char p21[21]; + char key[CIFS_AUTH_RESP_SIZE]; + + memset(p21, '\0', 21); + memcpy(p21, user_passkey(sess->user), CIFS_NTHASH_SIZE); + rc = ksmbd_enc_p24(p21, cryptkey, key); + if (rc) { + pr_err("password processing failed\n"); + return rc; + } + + ksmbd_enc_md4(sess->sess_key, user_passkey(sess->user), + CIFS_SMB1_SESSKEY_SIZE); + memcpy(sess->sess_key + CIFS_SMB1_SESSKEY_SIZE, key, + CIFS_AUTH_RESP_SIZE); + sess->sequence_number = 1; + + if (strncmp(pw_buf, key, CIFS_AUTH_RESP_SIZE) != 0) { + ksmbd_debug(AUTH, "ntlmv1 authentication failed\n"); + return -EINVAL; + } + + ksmbd_debug(AUTH, "ntlmv1 authentication pass\n"); + return 0; +} +#endif + /** * ksmbd_auth_ntlmv2() - NTLMv2 authentication handler * @sess: session of connection @@ -290,6 +450,46 @@ return rc; } +#ifdef CONFIG_SMB_INSECURE_SERVER +/** + * __ksmbd_auth_ntlmv2() - NTLM2(extended security) authentication handler + * @sess: session of connection + * @client_nonce: client nonce from LM response. + * @ntlm_resp: ntlm response data from client. + * + * Return: 0 on success, error number on error + */ +static int __ksmbd_auth_ntlmv2(struct ksmbd_session *sess, + char *client_nonce, + char *ntlm_resp, + char *cryptkey) +{ + char sess_key[CIFS_SMB1_SESSKEY_SIZE] = {0}; + int rc; + unsigned char p21[21]; + char key[CIFS_AUTH_RESP_SIZE]; + + rc = ksmbd_enc_update_sess_key(sess_key, client_nonce, cryptkey, 8); + if (rc) { + pr_err("password processing failed\n"); + goto out; + } + + memset(p21, '\0', 21); + memcpy(p21, user_passkey(sess->user), CIFS_NTHASH_SIZE); + rc = ksmbd_enc_p24(p21, sess_key, key); + if (rc) { + pr_err("password processing failed\n"); + goto out; + } + + if (memcmp(ntlm_resp, key, CIFS_AUTH_RESP_SIZE) != 0) + rc = -EINVAL; +out: + return rc; +} +#endif + /** * ksmbd_decode_ntlmssp_auth_blob() - helper function to construct * authenticate blob @@ -306,6 +506,10 @@ char *domain_name; unsigned int nt_off, dn_off; unsigned short nt_len, dn_len; +#ifdef CONFIG_SMB_INSECURE_SERVER + unsigned int lm_off; + unsigned short lm_len; +#endif int ret; if (blob_len < sizeof(struct authenticate_message)) { @@ -329,6 +533,26 @@ nt_len < CIFS_ENCPWD_SIZE) return -EINVAL; +#ifdef CONFIG_SMB_INSECURE_SERVER + lm_off = le32_to_cpu(authblob->LmChallengeResponse.BufferOffset); + lm_len = le16_to_cpu(authblob->LmChallengeResponse.Length); + if (blob_len < (u64)lm_off + lm_len) + return -EINVAL; + + /* process NTLM authentication */ + if (nt_len == CIFS_AUTH_RESP_SIZE) { + if (le32_to_cpu(authblob->NegotiateFlags) & + NTLMSSP_NEGOTIATE_EXTENDED_SEC) + return __ksmbd_auth_ntlmv2(sess, + (char *)authblob + lm_off, + (char *)authblob + nt_off, + conn->ntlmssp.cryptkey); + else + return ksmbd_auth_ntlm(sess, (char *)authblob + + nt_off, conn->ntlmssp.cryptkey); + } +#endif + /* TODO : use domain name that imported from configuration file */ domain_name = smb_strndup_from_utf16((const char *)authblob + dn_off, dn_len, true, conn->local_nls); @@ -355,6 +579,9 @@ if (blob_len < (u64)sess_key_off + sess_key_len) return -EINVAL; + if (sess_key_len > CIFS_KEY_SIZE) + return -EINVAL; + ctx_arc4 = kmalloc(sizeof(*ctx_arc4), GFP_KERNEL); if (!ctx_arc4) return -ENOMEM; @@ -560,6 +787,60 @@ } #endif +#ifdef CONFIG_SMB_INSECURE_SERVER +/** + * ksmbd_sign_smb1_pdu() - function to generate SMB1 packet signing + * @sess: session of connection + * @iov: buffer iov array + * @n_vec: number of iovecs + * @sig: signature value generated for client request packet + * + */ +int ksmbd_sign_smb1_pdu(struct ksmbd_session *sess, struct kvec *iov, int n_vec, + char *sig) +{ + struct ksmbd_crypto_ctx *ctx; + int rc, i; + + ctx = ksmbd_crypto_ctx_find_md5(); + if (!ctx) { + ksmbd_debug(AUTH, "could not crypto alloc md5\n"); + return -ENOMEM; + } + + rc = crypto_shash_init(CRYPTO_MD5(ctx)); + if (rc) { + ksmbd_debug(AUTH, "md5 init error %d\n", rc); + goto out; + } + + rc = crypto_shash_update(CRYPTO_MD5(ctx), sess->sess_key, 40); + if (rc) { + ksmbd_debug(AUTH, "md5 update error %d\n", rc); + goto out; + } + + for (i = 0; i < n_vec; i++) { + rc = crypto_shash_update(CRYPTO_MD5(ctx), + iov[i].iov_base, + iov[i].iov_len); + if (rc) { + ksmbd_debug(AUTH, "md5 update error %d\n", rc); + goto out; + } + } + + rc = crypto_shash_final(CRYPTO_MD5(ctx), sig); + if (rc) + ksmbd_debug(AUTH, "md5 generation error %d\n", rc); + +out: + ksmbd_release_crypto_ctx(ctx); + return rc; +} +#endif + + /** * ksmbd_sign_smb2_pdu() - function to generate packet signing * @conn: connection @@ -1029,11 +1310,15 @@ { struct scatterlist *sg; unsigned int assoc_data_len = sizeof(struct smb2_transform_hdr) - 20; - int i, nr_entries[3] = {0}, total_entries = 0, sg_idx = 0; + int i, *nr_entries, total_entries = 0, sg_idx = 0; if (!nvec) return NULL; + nr_entries = kcalloc(nvec, sizeof(int), GFP_KERNEL); + if (!nr_entries) + return NULL; + for (i = 0; i < nvec - 1; i++) { unsigned long kaddr = (unsigned long)iov[i + 1].iov_base; @@ -1051,8 +1336,10 @@ total_entries += 2; sg = kmalloc_array(total_entries, sizeof(struct scatterlist), GFP_KERNEL); - if (!sg) + if (!sg) { + kfree(nr_entries); return NULL; + } sg_init_table(sg, total_entries); smb2_sg_set_buf(&sg[sg_idx++], iov[0].iov_base + 24, assoc_data_len); @@ -1086,6 +1373,7 @@ } } smb2_sg_set_buf(&sg[sg_idx], sign, SMB2_SIGNATURE_SIZE); + kfree(nr_entries); return sg; } diff -ruw linux-6.4/fs/smb/server/auth.h linux-6.4-fbx/fs/smb/server/auth.h --- linux-6.4/fs/smb/server/auth.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/auth.h 2023-11-07 13:38:44.038256036 +0100 @@ -52,6 +52,11 @@ struct ksmbd_conn *conn); int ksmbd_krb5_authenticate(struct ksmbd_session *sess, char *in_blob, int in_len, char *out_blob, int *out_len); +#ifdef CONFIG_SMB_INSECURE_SERVER +int ksmbd_auth_ntlm(struct ksmbd_session *sess, char *pw_buf, char *cryptkey); +int ksmbd_sign_smb1_pdu(struct ksmbd_session *sess, struct kvec *iov, int n_vec, + char *sig); +#endif int ksmbd_sign_smb2_pdu(struct ksmbd_conn *conn, char *key, struct kvec *iov, int n_vec, char *sig); int ksmbd_sign_smb3_pdu(struct ksmbd_conn *conn, char *key, struct kvec *iov, diff -ruw linux-6.4/fs/smb/server/connection.c linux-6.4-fbx/fs/smb/server/connection.c --- linux-6.4/fs/smb/server/connection.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/connection.c 2024-01-25 13:36:32.714984559 +0100 @@ -10,6 +10,9 @@ #include "server.h" #include "smb_common.h" +#ifdef CONFIG_SMB_INSECURE_SERVER +#include "smb1pdu.h" +#endif #include "mgmt/ksmbd_ida.h" #include "connection.h" #include "transport_tcp.h" @@ -84,6 +87,8 @@ spin_lock_init(&conn->llist_lock); INIT_LIST_HEAD(&conn->lock_list); + init_rwsem(&conn->session_lock); + down_write(&conn_list_lock); list_add(&conn->conns_list, &conn_list); up_write(&conn_list_lock); @@ -111,9 +116,20 @@ { struct ksmbd_conn *conn = work->conn; struct list_head *requests_queue = NULL; +#ifdef CONFIG_SMB_INSECURE_SERVER + struct smb2_hdr *hdr = work->request_buf; + if (hdr->ProtocolId == SMB2_PROTO_NUMBER) { if (conn->ops->get_cmd_val(work) != SMB2_CANCEL_HE) requests_queue = &conn->requests; + } else { + if (conn->ops->get_cmd_val(work) != SMB_COM_NT_CANCEL) + requests_queue = &conn->requests; + } +#else + if (conn->ops->get_cmd_val(work) != SMB2_CANCEL_HE) + requests_queue = &conn->requests; +#endif if (requests_queue) { atomic_inc(&conn->req_running); @@ -123,28 +139,22 @@ } } -int ksmbd_conn_try_dequeue_request(struct ksmbd_work *work) +void ksmbd_conn_try_dequeue_request(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; - int ret = 1; if (list_empty(&work->request_entry) && list_empty(&work->async_request_entry)) - return 0; + return; - if (!work->multiRsp) atomic_dec(&conn->req_running); - if (!work->multiRsp) { spin_lock(&conn->request_lock); list_del_init(&work->request_entry); spin_unlock(&conn->request_lock); if (work->asynchronous) release_async_work(work); - ret = 0; - } wake_up_all(&conn->req_running_q); - return ret; } void ksmbd_conn_lock(struct ksmbd_conn *conn) @@ -171,61 +181,35 @@ void ksmbd_conn_wait_idle(struct ksmbd_conn *conn, u64 sess_id) { - struct ksmbd_conn *bind_conn; - wait_event(conn->req_running_q, atomic_read(&conn->req_running) < 2); - - down_read(&conn_list_lock); - list_for_each_entry(bind_conn, &conn_list, conns_list) { - if (bind_conn == conn) - continue; - - if ((bind_conn->binding || xa_load(&bind_conn->sessions, sess_id)) && - !ksmbd_conn_releasing(bind_conn) && - atomic_read(&bind_conn->req_running)) { - wait_event(bind_conn->req_running_q, - atomic_read(&bind_conn->req_running) == 0); - } - } - up_read(&conn_list_lock); } int ksmbd_conn_write(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; - size_t len = 0; int sent; - struct kvec iov[3]; - int iov_idx = 0; if (!work->response_buf) { pr_err("NULL response header\n"); return -EINVAL; } - if (work->tr_buf) { - iov[iov_idx] = (struct kvec) { work->tr_buf, - sizeof(struct smb2_transform_hdr) + 4 }; - len += iov[iov_idx++].iov_len; - } + if (work->send_no_response) + return 0; - if (work->aux_payload_sz) { - iov[iov_idx] = (struct kvec) { work->response_buf, work->resp_hdr_sz }; - len += iov[iov_idx++].iov_len; - iov[iov_idx] = (struct kvec) { work->aux_payload_buf, work->aux_payload_sz }; - len += iov[iov_idx++].iov_len; - } else { - if (work->tr_buf) - iov[iov_idx].iov_len = work->resp_hdr_sz; - else - iov[iov_idx].iov_len = get_rfc1002_len(work->response_buf) + 4; - iov[iov_idx].iov_base = work->response_buf; - len += iov[iov_idx++].iov_len; - } +#ifdef CONFIG_SMB_INSECURE_SERVER + if (!work->iov_idx) + ksmbd_iov_pin_rsp(work, (char *)work->response_buf + 4, + work->response_offset); +#endif + + if (!work->iov_idx) + return -EINVAL; ksmbd_conn_lock(conn); - sent = conn->transport->ops->writev(conn->transport, &iov[0], - iov_idx, len, + sent = conn->transport->ops->writev(conn->transport, work->iov, + work->iov_cnt, + get_rfc1002_len(work->iov[0].iov_base) + 4, work->need_invalidate_rkey, work->remote_key); ksmbd_conn_unlock(conn); @@ -294,7 +278,11 @@ return true; } +#ifdef CONFIG_SMB_INSECURE_SERVER +#define SMB1_MIN_SUPPORTED_HEADER_SIZE SMB_HEADER_SIZE +#else #define SMB1_MIN_SUPPORTED_HEADER_SIZE (sizeof(struct smb_hdr)) +#endif #define SMB2_MIN_SUPPORTED_HEADER_SIZE (sizeof(struct smb2_hdr) + 4) /** @@ -320,6 +308,7 @@ goto out; conn->last_active = jiffies; + set_freezable(); while (ksmbd_conn_alive(conn)) { if (try_to_freeze()) continue; @@ -341,8 +330,9 @@ max_allowed_pdu_size = SMB3_MAX_MSGSIZE; if (pdu_size > max_allowed_pdu_size) { - pr_err_ratelimited("PDU length(%u) exceeded maximum allowed pdu size(%u) on connection(%d)\n", + pr_err_ratelimited("PDU length(%u) exceeded maximum allowed pdu size(%u) from %pISc (status=%d\n", pdu_size, max_allowed_pdu_size, + KSMBD_TCP_PEER_SOCKADDR(conn), READ_ONCE(conn->status)); break; } @@ -451,13 +441,7 @@ again: down_read(&conn_list_lock); list_for_each_entry(conn, &conn_list, conns_list) { - struct task_struct *task; - t = conn->transport; - task = t->handler; - if (task) - ksmbd_debug(CONN, "Stop session handler %s/%d\n", - task->comm, task_pid_nr(task)); ksmbd_conn_set_exiting(conn); if (t->ops->shutdown) { up_read(&conn_list_lock); diff -ruw linux-6.4/fs/smb/server/connection.h linux-6.4-fbx/fs/smb/server/connection.h --- linux-6.4/fs/smb/server/connection.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/connection.h 2024-01-25 13:36:32.714984559 +0100 @@ -50,6 +50,7 @@ struct nls_table *local_nls; struct unicode_map *um; struct list_head conns_list; + struct rw_semaphore session_lock; /* smb session 1 per user */ struct xarray sessions; unsigned long last_active; @@ -87,6 +88,7 @@ __u16 dialect; char *mechToken; + unsigned int mechTokenLen; struct ksmbd_conn_ops *conn_ops; @@ -133,7 +135,6 @@ struct ksmbd_transport { struct ksmbd_conn *conn; struct ksmbd_transport_ops *ops; - struct task_struct *handler; }; #define KSMBD_TCP_RECV_TIMEOUT (7 * HZ) @@ -158,7 +159,7 @@ struct smb2_buffer_desc_v1 *desc, unsigned int desc_len); void ksmbd_conn_enqueue_request(struct ksmbd_work *work); -int ksmbd_conn_try_dequeue_request(struct ksmbd_work *work); +void ksmbd_conn_try_dequeue_request(struct ksmbd_work *work); void ksmbd_conn_init_server_callbacks(struct ksmbd_conn_ops *ops); int ksmbd_conn_handler_loop(void *p); int ksmbd_conn_transport_init(void); diff -ruw linux-6.4/fs/smb/server/crypto_ctx.c linux-6.4-fbx/fs/smb/server/crypto_ctx.c --- linux-6.4/fs/smb/server/crypto_ctx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/crypto_ctx.c 2023-11-07 13:38:44.038256036 +0100 @@ -81,6 +81,14 @@ case CRYPTO_SHASH_SHA512: tfm = crypto_alloc_shash("sha512", 0, 0); break; +#ifdef CONFIG_SMB_INSECURE_SERVER + case CRYPTO_SHASH_MD4: + tfm = crypto_alloc_shash("md4", 0, 0); + break; + case CRYPTO_SHASH_MD5: + tfm = crypto_alloc_shash("md5", 0, 0); + break; +#endif default: return NULL; } @@ -207,6 +215,17 @@ { return ____crypto_shash_ctx_find(CRYPTO_SHASH_SHA512); } +#ifdef CONFIG_SMB_INSECURE_SERVER +struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_md4(void) +{ + return ____crypto_shash_ctx_find(CRYPTO_SHASH_MD4); +} + +struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_md5(void) +{ + return ____crypto_shash_ctx_find(CRYPTO_SHASH_MD5); +} +#endif static struct ksmbd_crypto_ctx *____crypto_aead_ctx_find(int id) { diff -ruw linux-6.4/fs/smb/server/crypto_ctx.h linux-6.4-fbx/fs/smb/server/crypto_ctx.h --- linux-6.4/fs/smb/server/crypto_ctx.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/crypto_ctx.h 2023-11-07 13:38:44.038256036 +0100 @@ -15,6 +15,10 @@ CRYPTO_SHASH_CMACAES, CRYPTO_SHASH_SHA256, CRYPTO_SHASH_SHA512, +#ifdef CONFIG_SMB_INSECURE_SERVER + CRYPTO_SHASH_MD4, + CRYPTO_SHASH_MD5, +#endif CRYPTO_SHASH_MAX, }; @@ -41,6 +45,10 @@ #define CRYPTO_CMACAES(c) ((c)->desc[CRYPTO_SHASH_CMACAES]) #define CRYPTO_SHA256(c) ((c)->desc[CRYPTO_SHASH_SHA256]) #define CRYPTO_SHA512(c) ((c)->desc[CRYPTO_SHASH_SHA512]) +#ifdef CONFIG_SMB_INSECURE_SERVER +#define CRYPTO_MD4(c) ((c)->desc[CRYPTO_SHASH_MD4]) +#define CRYPTO_MD5(c) ((c)->desc[CRYPTO_SHASH_MD5]) +#endif #define CRYPTO_HMACMD5_TFM(c) ((c)->desc[CRYPTO_SHASH_HMACMD5]->tfm) #define CRYPTO_HMACSHA256_TFM(c)\ @@ -48,6 +56,10 @@ #define CRYPTO_CMACAES_TFM(c) ((c)->desc[CRYPTO_SHASH_CMACAES]->tfm) #define CRYPTO_SHA256_TFM(c) ((c)->desc[CRYPTO_SHASH_SHA256]->tfm) #define CRYPTO_SHA512_TFM(c) ((c)->desc[CRYPTO_SHASH_SHA512]->tfm) +#ifdef CONFIG_SMB_INSECURE_SERVER +#define CRYPTO_MD4_TFM(c) ((c)->desc[CRYPTO_SHASH_MD4]->tfm) +#define CRYPTO_MD5_TFM(c) ((c)->desc[CRYPTO_SHASH_MD5]->tfm) +#endif #define CRYPTO_GCM(c) ((c)->ccmaes[CRYPTO_AEAD_AES_GCM]) #define CRYPTO_CCM(c) ((c)->ccmaes[CRYPTO_AEAD_AES_CCM]) @@ -58,6 +70,10 @@ struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_cmacaes(void); struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_sha512(void); struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_sha256(void); +#ifdef CONFIG_SMB_INSECURE_SERVER +struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_md4(void); +struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_md5(void); +#endif struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_gcm(void); struct ksmbd_crypto_ctx *ksmbd_crypto_ctx_find_ccm(void); void ksmbd_crypto_destroy(void); diff -ruw linux-6.4/fs/smb/server/glob.h linux-6.4-fbx/fs/smb/server/glob.h --- linux-6.4/fs/smb/server/glob.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/glob.h 2023-11-07 13:38:44.038256036 +0100 @@ -46,4 +46,8 @@ #define UNICODE_LEN(x) ((x) * 2) +#ifdef CONFIG_SMB_INSECURE_SERVER +extern void ntstatus_to_dos(__le32 ntstatus, __u8 *eclass, __le16 *ecode); +#endif + #endif /* __KSMBD_GLOB_H */ diff -ruw linux-6.4/fs/smb/server/ksmbd_netlink.h linux-6.4-fbx/fs/smb/server/ksmbd_netlink.h --- linux-6.4/fs/smb/server/ksmbd_netlink.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/ksmbd_netlink.h 2024-04-19 15:59:31.193600561 +0200 @@ -166,7 +166,8 @@ __u16 force_uid; __u16 force_gid; __s8 share_name[KSMBD_REQ_MAX_SHARE_NAME]; - __u32 reserved[112]; /* Reserved room */ + __u32 reserved[111]; /* Reserved room */ + __u32 payload_sz; __u32 veto_list_sz; __s8 ____payload[]; }; @@ -304,7 +305,8 @@ KSMBD_EVENT_SPNEGO_AUTHEN_REQUEST, KSMBD_EVENT_SPNEGO_AUTHEN_RESPONSE = 15, - KSMBD_EVENT_MAX + __KSMBD_EVENT_MAX, + KSMBD_EVENT_MAX = __KSMBD_EVENT_MAX - 1 }; /* @@ -353,6 +355,7 @@ #define KSMBD_SHARE_FLAG_FOLLOW_SYMLINKS BIT(12) #define KSMBD_SHARE_FLAG_ACL_XATTR BIT(13) #define KSMBD_SHARE_FLAG_UPDATE BIT(14) +#define KSMBD_SHARE_FLAG_CROSSMNT BIT(15) /* * Tree connect request flags. diff -ruw linux-6.4/fs/smb/server/ksmbd_work.c linux-6.4-fbx/fs/smb/server/ksmbd_work.c --- linux-6.4/fs/smb/server/ksmbd_work.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/ksmbd_work.c 2024-01-25 13:36:32.714984559 +0100 @@ -27,18 +27,38 @@ INIT_LIST_HEAD(&work->async_request_entry); INIT_LIST_HEAD(&work->fp_entry); INIT_LIST_HEAD(&work->interim_entry); + INIT_LIST_HEAD(&work->aux_read_list); + work->iov_alloc_cnt = 4; + work->iov = kcalloc(work->iov_alloc_cnt, sizeof(struct kvec), + GFP_KERNEL); + if (!work->iov) { + kmem_cache_free(work_cache, work); + work = NULL; + } } return work; } void ksmbd_free_work_struct(struct ksmbd_work *work) { + struct aux_read *ar, *tmp; + WARN_ON(work->saved_cred != NULL); kvfree(work->response_buf); - kvfree(work->aux_payload_buf); + + list_for_each_entry_safe(ar, tmp, &work->aux_read_list, entry) { + kvfree(ar->buf); + list_del(&ar->entry); + kfree(ar); + } + kfree(work->tr_buf); kvfree(work->request_buf); + kfree(work->iov); + if (!list_empty(&work->interim_entry)) + list_del(&work->interim_entry); + if (work->async_id) ksmbd_release_id(&work->conn->async_ida, work->async_id); kmem_cache_free(work_cache, work); @@ -77,3 +97,81 @@ { return queue_work(ksmbd_wq, &work->work); } + +static inline void __ksmbd_iov_pin(struct ksmbd_work *work, void *ib, + unsigned int ib_len) +{ + work->iov[++work->iov_idx].iov_base = ib; + work->iov[work->iov_idx].iov_len = ib_len; + work->iov_cnt++; +} + +static int __ksmbd_iov_pin_rsp(struct ksmbd_work *work, void *ib, int len, + void *aux_buf, unsigned int aux_size) +{ + struct aux_read *ar = NULL; + int need_iov_cnt = 1; + + if (aux_size) { + need_iov_cnt++; + ar = kmalloc(sizeof(struct aux_read), GFP_KERNEL); + if (!ar) + return -ENOMEM; + } + + if (work->iov_alloc_cnt < work->iov_cnt + need_iov_cnt) { + struct kvec *new; + + work->iov_alloc_cnt += 4; + new = krealloc(work->iov, + sizeof(struct kvec) * work->iov_alloc_cnt, + GFP_KERNEL | __GFP_ZERO); + if (!new) { + kfree(ar); + work->iov_alloc_cnt -= 4; + return -ENOMEM; + } + work->iov = new; + } + + /* Plus rfc_length size on first iov */ + if (!work->iov_idx) { + work->iov[work->iov_idx].iov_base = work->response_buf; + *(__be32 *)work->iov[0].iov_base = 0; + work->iov[work->iov_idx].iov_len = 4; + work->iov_cnt++; + } + + __ksmbd_iov_pin(work, ib, len); + inc_rfc1001_len(work->iov[0].iov_base, len); + + if (aux_size) { + __ksmbd_iov_pin(work, aux_buf, aux_size); + inc_rfc1001_len(work->iov[0].iov_base, aux_size); + + ar->buf = aux_buf; + list_add(&ar->entry, &work->aux_read_list); + } + + return 0; +} + +int ksmbd_iov_pin_rsp(struct ksmbd_work *work, void *ib, int len) +{ + return __ksmbd_iov_pin_rsp(work, ib, len, NULL, 0); +} + +int ksmbd_iov_pin_rsp_read(struct ksmbd_work *work, void *ib, int len, + void *aux_buf, unsigned int aux_size) +{ + return __ksmbd_iov_pin_rsp(work, ib, len, aux_buf, aux_size); +} + +int allocate_interim_rsp_buf(struct ksmbd_work *work) +{ + work->response_buf = kzalloc(MAX_CIFS_SMALL_BUFFER_SIZE, GFP_KERNEL); + if (!work->response_buf) + return -ENOMEM; + work->response_sz = MAX_CIFS_SMALL_BUFFER_SIZE; + return 0; +} diff -ruw linux-6.4/fs/smb/server/ksmbd_work.h linux-6.4-fbx/fs/smb/server/ksmbd_work.h --- linux-6.4/fs/smb/server/ksmbd_work.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/ksmbd_work.h 2023-11-07 13:38:44.038256036 +0100 @@ -19,6 +19,11 @@ KSMBD_WORK_CLOSED, }; +struct aux_read { + void *buf; + struct list_head entry; +}; + /* one of these for every pending CIFS request at the connection */ struct ksmbd_work { /* Server corresponding to this mid */ @@ -30,14 +35,23 @@ void *request_buf; /* Response buffer */ void *response_buf; - - /* Read data buffer */ - void *aux_payload_buf; +#ifdef CONFIG_SMB_INSECURE_SERVER + size_t response_offset; +#endif + + struct list_head aux_read_list; + + struct kvec *iov; + int iov_alloc_cnt; + int iov_cnt; + int iov_idx; /* Next cmd hdr in compound req buf*/ int next_smb2_rcv_hdr_off; /* Next cmd hdr in compound rsp buf*/ int next_smb2_rsp_hdr_off; + /* Current cmd hdr in compound rsp buf*/ + int curr_smb2_rsp_hdr_off; /* * Current Local FID assigned compound response if SMB2 CREATE @@ -53,16 +67,11 @@ unsigned int credits_granted; /* response smb header size */ - unsigned int resp_hdr_sz; unsigned int response_sz; - /* Read data count */ - unsigned int aux_payload_sz; void *tr_buf; unsigned char state; - /* Multiple responses for one request e.g. SMB ECHO */ - bool multiRsp:1; /* No response for cancelled request */ bool send_no_response:1; /* Request is encrypted */ @@ -96,6 +105,15 @@ } /** + * ksmbd_resp_buf_curr - Get current buffer on compound response. + * @work: smb work containing response buffer + */ +static inline void *ksmbd_resp_buf_curr(struct ksmbd_work *work) +{ + return work->response_buf + work->curr_smb2_rsp_hdr_off + 4; +} + +/** * ksmbd_req_buf_next - Get next buffer on compound request. * @work: smb work containing response buffer */ @@ -113,5 +131,8 @@ int ksmbd_workqueue_init(void); void ksmbd_workqueue_destroy(void); bool ksmbd_queue_work(struct ksmbd_work *work); - +int ksmbd_iov_pin_rsp_read(struct ksmbd_work *work, void *ib, int len, + void *aux_buf, unsigned int aux_size); +int ksmbd_iov_pin_rsp(struct ksmbd_work *work, void *ib, int len); +int allocate_interim_rsp_buf(struct ksmbd_work *work); #endif /* __KSMBD_WORK_H__ */ diff -ruw linux-6.4/fs/smb/server/mgmt/ksmbd_ida.c linux-6.4-fbx/fs/smb/server/mgmt/ksmbd_ida.c --- linux-6.4/fs/smb/server/mgmt/ksmbd_ida.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/ksmbd_ida.c 2023-11-07 13:38:44.038256036 +0100 @@ -10,6 +10,13 @@ return ida_simple_get(ida, from, to, GFP_KERNEL); } +#ifdef CONFIG_SMB_INSECURE_SERVER +int ksmbd_acquire_smb1_tid(struct ida *ida) +{ + return __acquire_id(ida, 1, 0xFFFF); +} +#endif + int ksmbd_acquire_smb2_tid(struct ida *ida) { int id; @@ -19,6 +26,13 @@ return id; } +#ifdef CONFIG_SMB_INSECURE_SERVER +int ksmbd_acquire_smb1_uid(struct ida *ida) +{ + return __acquire_id(ida, 1, 0xFFFE); +} +#endif + int ksmbd_acquire_smb2_uid(struct ida *ida) { int id; diff -ruw linux-6.4/fs/smb/server/mgmt/ksmbd_ida.h linux-6.4-fbx/fs/smb/server/mgmt/ksmbd_ida.h --- linux-6.4/fs/smb/server/mgmt/ksmbd_ida.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/ksmbd_ida.h 2023-11-07 13:38:44.038256036 +0100 @@ -16,6 +16,9 @@ * The value 0xFFFF is used to specify all TIDs or no TID, * depending upon the context in which it is used. */ +#ifdef CONFIG_SMB_INSECURE_SERVER +int ksmbd_acquire_smb1_tid(struct ida *ida); +#endif int ksmbd_acquire_smb2_tid(struct ida *ida); /* @@ -25,6 +28,9 @@ * valid UID.<21> All other possible values for a UID, excluding * zero (0x0000), are valid. */ +#ifdef CONFIG_SMB_INSECURE_SERVER +int ksmbd_acquire_smb1_uid(struct ida *ida); +#endif int ksmbd_acquire_smb2_uid(struct ida *ida); int ksmbd_acquire_async_msg_id(struct ida *ida); diff -ruw linux-6.4/fs/smb/server/mgmt/share_config.c linux-6.4-fbx/fs/smb/server/mgmt/share_config.c --- linux-6.4/fs/smb/server/mgmt/share_config.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/share_config.c 2024-04-19 15:59:31.193600561 +0200 @@ -158,7 +158,12 @@ share->name = kstrdup(name, GFP_KERNEL); if (!test_share_config_flag(share, KSMBD_SHARE_FLAG_PIPE)) { - share->path = kstrdup(ksmbd_share_config_path(resp), + int path_len = PATH_MAX; + + if (resp->payload_sz) + path_len = resp->payload_sz - resp->veto_list_sz; + + share->path = kstrndup(ksmbd_share_config_path(resp), path_len, GFP_KERNEL); if (share->path) share->path_sz = strlen(share->path); diff -ruw linux-6.4/fs/smb/server/mgmt/share_config.h linux-6.4-fbx/fs/smb/server/mgmt/share_config.h --- linux-6.4/fs/smb/server/mgmt/share_config.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/share_config.h 2023-11-07 13:38:44.038256036 +0100 @@ -34,29 +34,22 @@ #define KSMBD_SHARE_INVALID_UID ((__u16)-1) #define KSMBD_SHARE_INVALID_GID ((__u16)-1) -static inline int share_config_create_mode(struct ksmbd_share_config *share, +static inline umode_t +share_config_create_mode(struct ksmbd_share_config *share, umode_t posix_mode) { - if (!share->force_create_mode) { - if (!posix_mode) - return share->create_mask; - else - return posix_mode & share->create_mask; - } - return share->force_create_mode & share->create_mask; + umode_t mode = (posix_mode ?: (umode_t)-1) & share->create_mask; + + return mode | share->force_create_mode; } -static inline int share_config_directory_mode(struct ksmbd_share_config *share, +static inline umode_t +share_config_directory_mode(struct ksmbd_share_config *share, umode_t posix_mode) { - if (!share->force_directory_mode) { - if (!posix_mode) - return share->directory_mask; - else - return posix_mode & share->directory_mask; - } + umode_t mode = (posix_mode ?: (umode_t)-1) & share->directory_mask; - return share->force_directory_mode & share->directory_mask; + return mode | share->force_directory_mode; } static inline int test_share_config_flag(struct ksmbd_share_config *share, diff -ruw linux-6.4/fs/smb/server/mgmt/tree_connect.c linux-6.4-fbx/fs/smb/server/mgmt/tree_connect.c --- linux-6.4/fs/smb/server/mgmt/tree_connect.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/tree_connect.c 2023-11-07 13:38:44.038256036 +0100 @@ -73,7 +73,10 @@ tree_conn->user = sess->user; tree_conn->share_conf = sc; + tree_conn->t_state = TREE_NEW; status.tree_conn = tree_conn; + atomic_set(&tree_conn->refcount, 1); + init_waitqueue_head(&tree_conn->refcount_q); ret = xa_err(xa_store(&sess->tree_conns, tree_conn->id, tree_conn, GFP_KERNEL)); @@ -93,14 +96,33 @@ return status; } +void ksmbd_tree_connect_put(struct ksmbd_tree_connect *tcon) +{ + /* + * Checking waitqueue to releasing tree connect on + * tree disconnect. waitqueue_active is safe because it + * uses atomic operation for condition. + */ + if (!atomic_dec_return(&tcon->refcount) && + waitqueue_active(&tcon->refcount_q)) + wake_up(&tcon->refcount_q); +} + int ksmbd_tree_conn_disconnect(struct ksmbd_session *sess, struct ksmbd_tree_connect *tree_conn) { int ret; + write_lock(&sess->tree_conns_lock); + xa_erase(&sess->tree_conns, tree_conn->id); + write_unlock(&sess->tree_conns_lock); + + if (!atomic_dec_and_test(&tree_conn->refcount)) + wait_event(tree_conn->refcount_q, + atomic_read(&tree_conn->refcount) == 0); + ret = ksmbd_ipc_tree_disconnect_request(sess->id, tree_conn->id); ksmbd_release_tree_conn_id(sess, tree_conn->id); - xa_erase(&sess->tree_conns, tree_conn->id); ksmbd_share_config_put(tree_conn->share_conf); kfree(tree_conn); return ret; @@ -111,26 +133,19 @@ { struct ksmbd_tree_connect *tcon; + read_lock(&sess->tree_conns_lock); tcon = xa_load(&sess->tree_conns, id); if (tcon) { - if (test_bit(TREE_CONN_EXPIRE, &tcon->status)) + if (tcon->t_state != TREE_CONNECTED) + tcon = NULL; + else if (!atomic_inc_not_zero(&tcon->refcount)) tcon = NULL; } + read_unlock(&sess->tree_conns_lock); return tcon; } -struct ksmbd_share_config *ksmbd_tree_conn_share(struct ksmbd_session *sess, - unsigned int id) -{ - struct ksmbd_tree_connect *tc; - - tc = ksmbd_tree_conn_lookup(sess, id); - if (tc) - return tc->share_conf; - return NULL; -} - int ksmbd_tree_conn_session_logoff(struct ksmbd_session *sess) { int ret = 0; @@ -140,8 +155,18 @@ if (!sess) return -EINVAL; - xa_for_each(&sess->tree_conns, id, tc) + xa_for_each(&sess->tree_conns, id, tc) { + write_lock(&sess->tree_conns_lock); + if (tc->t_state == TREE_DISCONNECTED) { + write_unlock(&sess->tree_conns_lock); + ret = -ENOENT; + continue; + } + tc->t_state = TREE_DISCONNECTED; + write_unlock(&sess->tree_conns_lock); + ret |= ksmbd_tree_conn_disconnect(sess, tc); + } xa_destroy(&sess->tree_conns); return ret; } diff -ruw linux-6.4/fs/smb/server/mgmt/tree_connect.h linux-6.4-fbx/fs/smb/server/mgmt/tree_connect.h --- linux-6.4/fs/smb/server/mgmt/tree_connect.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/tree_connect.h 2023-11-07 13:38:44.038256036 +0100 @@ -14,7 +14,11 @@ struct ksmbd_user; struct ksmbd_conn; -#define TREE_CONN_EXPIRE 1 +enum { + TREE_NEW = 0, + TREE_CONNECTED, + TREE_DISCONNECTED +}; struct ksmbd_tree_connect { int id; @@ -27,7 +31,9 @@ int maximal_access; bool posix_extensions; - unsigned long status; + atomic_t refcount; + wait_queue_head_t refcount_q; + unsigned int t_state; }; struct ksmbd_tree_conn_status { @@ -46,6 +52,7 @@ struct ksmbd_tree_conn_status ksmbd_tree_conn_connect(struct ksmbd_conn *conn, struct ksmbd_session *sess, const char *share_name); +void ksmbd_tree_connect_put(struct ksmbd_tree_connect *tcon); int ksmbd_tree_conn_disconnect(struct ksmbd_session *sess, struct ksmbd_tree_connect *tree_conn); @@ -53,9 +60,6 @@ struct ksmbd_tree_connect *ksmbd_tree_conn_lookup(struct ksmbd_session *sess, unsigned int id); -struct ksmbd_share_config *ksmbd_tree_conn_share(struct ksmbd_session *sess, - unsigned int id); - int ksmbd_tree_conn_session_logoff(struct ksmbd_session *sess); #endif /* __TREE_CONNECT_MANAGEMENT_H__ */ diff -ruw linux-6.4/fs/smb/server/mgmt/user_session.c linux-6.4-fbx/fs/smb/server/mgmt/user_session.c --- linux-6.4/fs/smb/server/mgmt/user_session.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/user_session.c 2023-11-07 13:38:44.038256036 +0100 @@ -174,18 +174,23 @@ unsigned long id; struct ksmbd_session *sess; - down_write(&sessions_table_lock); + down_write(&conn->session_lock); xa_for_each(&conn->sessions, id, sess) { if (sess->state != SMB2_SESSION_VALID || time_after(jiffies, sess->last_active + SMB2_SESSION_TIMEOUT)) { xa_erase(&conn->sessions, sess->id); +#ifdef CONFIG_SMB_INSECURE_SERVER + if (hash_hashed(&sess->hlist)) + hash_del(&sess->hlist); +#else hash_del(&sess->hlist); +#endif ksmbd_session_destroy(sess); continue; } } - up_write(&sessions_table_lock); + up_write(&conn->session_lock); } int ksmbd_session_register(struct ksmbd_conn *conn, @@ -222,12 +227,19 @@ hash_for_each_safe(sessions_table, bkt, tmp, sess, hlist) { if (!ksmbd_chann_del(conn, sess) && xa_empty(&sess->ksmbd_chann_list)) { +#ifdef CONFIG_SMB_INSECURE_SERVER + if (hash_hashed(&sess->hlist)) hash_del(&sess->hlist); +#else + hash_del(&sess->hlist); +#endif ksmbd_session_destroy(sess); } } } + up_write(&sessions_table_lock); + down_write(&conn->session_lock); xa_for_each(&conn->sessions, id, sess) { unsigned long chann_id; struct channel *chann; @@ -240,11 +252,16 @@ ksmbd_chann_del(conn, sess); if (xa_empty(&sess->ksmbd_chann_list)) { xa_erase(&conn->sessions, sess->id); +#ifdef CONFIG_SMB_INSECURE_SERVER + if (hash_hashed(&sess->hlist)) hash_del(&sess->hlist); +#else + hash_del(&sess->hlist); +#endif ksmbd_session_destroy(sess); } } - up_write(&sessions_table_lock); + up_write(&conn->session_lock); } struct ksmbd_session *ksmbd_session_lookup(struct ksmbd_conn *conn, @@ -252,9 +269,11 @@ { struct ksmbd_session *sess; + down_read(&conn->session_lock); sess = xa_load(&conn->sessions, id); if (sess) sess->last_active = jiffies; + up_read(&conn->session_lock); return sess; } @@ -319,6 +338,18 @@ return NULL; } +#ifdef CONFIG_SMB_INSECURE_SERVER +static int __init_smb1_session(struct ksmbd_session *sess) +{ + int id = ksmbd_acquire_smb1_uid(&session_ida); + + if (id < 0) + return -EINVAL; + sess->id = id; + return 0; +} +#endif + static int __init_smb2_session(struct ksmbd_session *sess) { int id = ksmbd_acquire_smb2_uid(&session_ida); @@ -334,8 +365,10 @@ struct ksmbd_session *sess; int ret; +#ifndef CONFIG_SMB_INSECURE_SERVER if (protocol != CIFDS_SESSION_FLAG_SMB2) return NULL; +#endif sess = kzalloc(sizeof(struct ksmbd_session), GFP_KERNEL); if (!sess) @@ -351,8 +384,22 @@ xa_init(&sess->ksmbd_chann_list); xa_init(&sess->rpc_handle_list); sess->sequence_number = 1; + rwlock_init(&sess->tree_conns_lock); + switch (protocol) { +#ifdef CONFIG_SMB_INSECURE_SERVER + case CIFDS_SESSION_FLAG_SMB1: + ret = __init_smb1_session(sess); + break; +#endif + case CIFDS_SESSION_FLAG_SMB2: ret = __init_smb2_session(sess); + break; + default: + ret = -EINVAL; + break; + } + if (ret) goto error; @@ -369,6 +416,13 @@ return NULL; } +#ifdef CONFIG_SMB_INSECURE_SERVER +struct ksmbd_session *ksmbd_smb1_session_create(void) +{ + return __session_create(CIFDS_SESSION_FLAG_SMB1); +} +#endif + struct ksmbd_session *ksmbd_smb2_session_create(void) { return __session_create(CIFDS_SESSION_FLAG_SMB2); @@ -378,6 +432,10 @@ { int id = -EINVAL; +#ifdef CONFIG_SMB_INSECURE_SERVER + if (test_session_flag(sess, CIFDS_SESSION_FLAG_SMB1)) + id = ksmbd_acquire_smb1_tid(&sess->tree_conn_ida); +#endif if (test_session_flag(sess, CIFDS_SESSION_FLAG_SMB2)) id = ksmbd_acquire_smb2_tid(&sess->tree_conn_ida); diff -ruw linux-6.4/fs/smb/server/mgmt/user_session.h linux-6.4-fbx/fs/smb/server/mgmt/user_session.h --- linux-6.4/fs/smb/server/mgmt/user_session.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/mgmt/user_session.h 2023-11-07 13:38:44.042256145 +0100 @@ -12,6 +12,9 @@ #include "../smb_common.h" #include "../ntlmssp.h" +#ifdef CONFIG_SMB_INSECURE_SERVER +#define CIFDS_SESSION_FLAG_SMB1 BIT(0) +#endif #define CIFDS_SESSION_FLAG_SMB2 BIT(1) #define PREAUTH_HASHVALUE_SIZE 64 @@ -60,6 +63,7 @@ struct ksmbd_file_table file_table; unsigned long last_active; + rwlock_t tree_conns_lock; }; static inline int test_session_flag(struct ksmbd_session *sess, int bit) @@ -77,6 +81,9 @@ sess->flags &= ~bit; } +#ifdef CONFIG_SMB_INSECURE_SERVER +struct ksmbd_session *ksmbd_smb1_session_create(void); +#endif struct ksmbd_session *ksmbd_smb2_session_create(void); void ksmbd_session_destroy(struct ksmbd_session *sess); diff -ruw linux-6.4/fs/smb/server/oplock.c linux-6.4-fbx/fs/smb/server/oplock.c --- linux-6.4/fs/smb/server/oplock.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/oplock.c 2024-03-18 14:40:14.867741770 +0100 @@ -10,6 +10,9 @@ #include "oplock.h" #include "smb_common.h" +#ifdef CONFIG_SMB_INSECURE_SERVER +#include "smb1pdu.h" +#endif #include "smbstatus.h" #include "connection.h" #include "mgmt/user_session.h" @@ -45,6 +48,9 @@ opinfo->pending_break = 0; opinfo->fid = id; opinfo->Tid = Tid; +#ifdef CONFIG_SMB_INSECURE_SERVER + opinfo->is_smb2 = IS_SMB2(conn); +#endif INIT_LIST_HEAD(&opinfo->op_entry); INIT_LIST_HEAD(&opinfo->interim_list); init_waitqueue_head(&opinfo->oplock_q); @@ -102,9 +108,10 @@ lease->new_state = 0; lease->flags = lctx->flags; lease->duration = lctx->duration; + lease->is_dir = lctx->is_dir; memcpy(lease->parent_lease_key, lctx->parent_lease_key, SMB2_LEASE_KEY_SIZE); lease->version = lctx->version; - lease->epoch = 0; + lease->epoch = le16_to_cpu(lctx->epoch) + 1; INIT_LIST_HEAD(&opinfo->lease_entry); opinfo->o_lease = lease; @@ -258,6 +265,8 @@ { struct lease *lease = opinfo->o_lease; +#ifdef CONFIG_SMB_INSECURE_SERVER + if (opinfo->is_smb2) { if (!(opinfo->level == SMB2_OPLOCK_LEVEL_BATCH || opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE)) { pr_err("bad oplock(0x%x)\n", opinfo->level); @@ -269,6 +278,27 @@ if (opinfo->is_lease) lease->state = lease->new_state; + } else { + if (!(opinfo->level == OPLOCK_EXCLUSIVE || + opinfo->level == OPLOCK_BATCH)) { + pr_err("bad oplock(0x%x)\n", opinfo->level); + return -EINVAL; + } + opinfo->level = OPLOCK_READ; + } +#else + if (!(opinfo->level == SMB2_OPLOCK_LEVEL_BATCH || + opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE)) { + pr_err("bad oplock(0x%x)\n", opinfo->level); + if (opinfo->is_lease) + pr_err("lease state(0x%x)\n", lease->state); + return -EINVAL; + } + opinfo->level = SMB2_OPLOCK_LEVEL_II; + + if (opinfo->is_lease) + lease->state = lease->new_state; +#endif return 0; } @@ -297,6 +327,27 @@ { struct lease *lease = opinfo->o_lease; +#ifdef CONFIG_SMB_INSECURE_SERVER + if (opinfo->is_smb2) { + if (!(opinfo->level == SMB2_OPLOCK_LEVEL_BATCH || + opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE)) { + pr_err("bad oplock(0x%x)\n", opinfo->level); + if (opinfo->is_lease) + pr_err("lease state(0x%x)\n", lease->state); + return -EINVAL; + } + opinfo->level = SMB2_OPLOCK_LEVEL_NONE; + if (opinfo->is_lease) + lease->state = lease->new_state; + } else { + if (!(opinfo->level == OPLOCK_EXCLUSIVE || + opinfo->level == OPLOCK_BATCH)) { + pr_err("bad oplock(0x%x)\n", opinfo->level); + return -EINVAL; + } + opinfo->level = OPLOCK_NONE; + } +#else if (!(opinfo->level == SMB2_OPLOCK_LEVEL_BATCH || opinfo->level == SMB2_OPLOCK_LEVEL_EXCLUSIVE)) { pr_err("bad oplock(0x%x)\n", opinfo->level); @@ -307,6 +358,7 @@ opinfo->level = SMB2_OPLOCK_LEVEL_NONE; if (opinfo->is_lease) lease->state = lease->new_state; +#endif return 0; } @@ -320,6 +372,8 @@ { struct lease *lease = opinfo->o_lease; +#ifdef CONFIG_SMB_INSECURE_SERVER + if (opinfo->is_smb2) { if (opinfo->level != SMB2_OPLOCK_LEVEL_II) { pr_err("bad oplock(0x%x)\n", opinfo->level); if (opinfo->is_lease) @@ -329,6 +383,24 @@ opinfo->level = SMB2_OPLOCK_LEVEL_NONE; if (opinfo->is_lease) lease->state = lease->new_state; + } else { + if (opinfo->level != OPLOCK_READ) { + pr_err("bad oplock(0x%x)\n", opinfo->level); + return -EINVAL; + } + opinfo->level = OPLOCK_NONE; + } +#else + if (opinfo->level != SMB2_OPLOCK_LEVEL_II) { + pr_err("bad oplock(0x%x)\n", opinfo->level); + if (opinfo->is_lease) + pr_err("lease state(0x%x)\n", lease->state); + return -EINVAL; + } + opinfo->level = SMB2_OPLOCK_LEVEL_NONE; + if (opinfo->is_lease) + lease->state = lease->new_state; +#endif return 0; } @@ -395,8 +467,8 @@ { struct oplock_info *opinfo; - if (S_ISDIR(file_inode(fp->filp)->i_mode)) - return; + if (fp->reserve_lease_break) + smb_lazy_parent_lease_break_close(fp); opinfo = opinfo_get(fp); if (!opinfo) @@ -432,10 +504,24 @@ { struct lease *lease = opinfo_new->o_lease; +#ifdef CONFIG_SMB_INSECURE_SERVER + if (opinfo_new->is_smb2) { + if (req_oplock == SMB2_OPLOCK_LEVEL_BATCH) + opinfo_new->level = SMB2_OPLOCK_LEVEL_BATCH; + else + opinfo_new->level = SMB2_OPLOCK_LEVEL_EXCLUSIVE; + } else { + if (req_oplock == REQ_BATCHOPLOCK) + opinfo_new->level = OPLOCK_BATCH; + else + opinfo_new->level = OPLOCK_EXCLUSIVE; + } +#else if (req_oplock == SMB2_OPLOCK_LEVEL_BATCH) opinfo_new->level = SMB2_OPLOCK_LEVEL_BATCH; else opinfo_new->level = SMB2_OPLOCK_LEVEL_EXCLUSIVE; +#endif if (lctx) { lease->state = lctx->req_state; @@ -455,7 +541,14 @@ { struct lease *lease = opinfo_new->o_lease; +#ifdef CONFIG_SMB_INSECURE_SERVER + if (opinfo_new->is_smb2) opinfo_new->level = SMB2_OPLOCK_LEVEL_II; + else + opinfo_new->level = OPLOCK_READ; +#else + opinfo_new->level = SMB2_OPLOCK_LEVEL_II; +#endif if (lctx) { lease->state = SMB2_LEASE_READ_CACHING_LE; @@ -477,7 +570,14 @@ { struct lease *lease = opinfo_new->o_lease; +#ifdef CONFIG_SMB_INSECURE_SERVER + if (opinfo_new->is_smb2) + opinfo_new->level = SMB2_OPLOCK_LEVEL_NONE; + else + opinfo_new->level = OPLOCK_NONE; +#else opinfo_new->level = SMB2_OPLOCK_LEVEL_NONE; +#endif if (lctx) { lease->state = 0; @@ -543,25 +643,31 @@ /* upgrading lease */ if ((atomic_read(&ci->op_count) + atomic_read(&ci->sop_count)) == 1) { - if (lease->state == - (lctx->req_state & lease->state)) { + if (lease->state != SMB2_LEASE_NONE_LE && + lease->state == (lctx->req_state & lease->state)) { + lease->epoch++; lease->state |= lctx->req_state; if (lctx->req_state & SMB2_LEASE_WRITE_CACHING_LE) lease_read_to_write(opinfo); + } } else if ((atomic_read(&ci->op_count) + atomic_read(&ci->sop_count)) > 1) { if (lctx->req_state == (SMB2_LEASE_READ_CACHING_LE | - SMB2_LEASE_HANDLE_CACHING_LE)) + SMB2_LEASE_HANDLE_CACHING_LE)) { + lease->epoch++; lease->state = lctx->req_state; } + } if (lctx->req_state && lease->state == - SMB2_LEASE_NONE_LE) + SMB2_LEASE_NONE_LE) { + lease->epoch++; lease_none_upgrade(opinfo, lctx->req_state); } + } read_lock(&ci->m_lock); } read_unlock(&ci->m_lock); @@ -616,6 +722,7 @@ return 0; } +#ifdef CONFIG_SMB_INSECURE_SERVER static inline int allocate_oplock_break_buf(struct ksmbd_work *work) { work->response_buf = kzalloc(MAX_CIFS_SMALL_BUFFER_SIZE, GFP_KERNEL); @@ -626,6 +733,108 @@ } /** + * smb1_oplock_break_noti() - send smb1 oplock break cmd from conn + * to client + * @work: smb work object + * + * There are two ways this function can be called. 1- while file open we break + * from exclusive/batch lock to levelII oplock and 2- while file write/truncate + * we break from levelII oplock no oplock. + * work->request_buf contains oplock_info. + */ +static void __smb1_oplock_break_noti(struct work_struct *wk) +{ + struct ksmbd_work *work = container_of(wk, struct ksmbd_work, work); + struct ksmbd_conn *conn = work->conn; + struct smb_hdr *rsp_hdr; + struct smb_com_lock_req *req; + struct oplock_info *opinfo = work->request_buf; + + if (allocate_oplock_break_buf(work)) { + pr_err("smb_allocate_rsp_buf failed! "); + ksmbd_free_work_struct(work); + return; + } + + /* Init response header */ + rsp_hdr = work->response_buf; + /* wct is 8 for locking andx(18) */ + memset(rsp_hdr, 0, sizeof(struct smb_hdr) + 18); + rsp_hdr->smb_buf_length = + cpu_to_be32(conn->vals->header_size - 4 + 18); + rsp_hdr->Protocol[0] = 0xFF; + rsp_hdr->Protocol[1] = 'S'; + rsp_hdr->Protocol[2] = 'M'; + rsp_hdr->Protocol[3] = 'B'; + + rsp_hdr->Command = SMB_COM_LOCKING_ANDX; + /* we know unicode, long file name and use nt error codes */ + rsp_hdr->Flags2 = SMBFLG2_UNICODE | SMBFLG2_KNOWS_LONG_NAMES | + SMBFLG2_ERR_STATUS; + rsp_hdr->Uid = cpu_to_le16(work->sess->id); + rsp_hdr->Pid = cpu_to_le16(0xFFFF); + rsp_hdr->Mid = cpu_to_le16(0xFFFF); + rsp_hdr->Tid = cpu_to_le16(opinfo->Tid); + rsp_hdr->WordCount = 8; + + /* Init locking request */ + req = work->response_buf; + + req->AndXCommand = 0xFF; + req->AndXReserved = 0; + req->AndXOffset = 0; + req->Fid = opinfo->fid; + req->LockType = LOCKING_ANDX_OPLOCK_RELEASE; + if (!opinfo->open_trunc && + (opinfo->level == OPLOCK_BATCH || + opinfo->level == OPLOCK_EXCLUSIVE)) + req->OplockLevel = 1; + else + req->OplockLevel = 0; + req->Timeout = 0; + req->NumberOfUnlocks = 0; + req->ByteCount = 0; + ksmbd_debug(OPLOCK, "sending oplock break for fid %d lock level = %d\n", + req->Fid, req->OplockLevel); + + ksmbd_conn_write(work); + ksmbd_free_work_struct(work); +} + +/** + * smb1_oplock_break() - send smb1 exclusive/batch to level2 oplock + * break command from server to client + * @opinfo: oplock info object + * @ack_required if requiring ack + * + * Return: 0 on success, otherwise error + */ +static int smb1_oplock_break_noti(struct oplock_info *opinfo) +{ + struct ksmbd_conn *conn = opinfo->conn; + struct ksmbd_work *work = ksmbd_alloc_work_struct(); + + if (!work) + return -ENOMEM; + + work->request_buf = (char *)opinfo; + work->conn = conn; + + if (opinfo->op_state == OPLOCK_ACK_WAIT) { + INIT_WORK(&work->work, __smb1_oplock_break_noti); + ksmbd_queue_work(work); + + wait_for_break_ack(opinfo); + } else { + __smb1_oplock_break_noti(&work->work); + if (opinfo->level == OPLOCK_READ) + opinfo->level = OPLOCK_NONE; + } + return 0; +} +#endif + +/** * __smb2_oplock_break_noti() - send smb2 oplock break cmd from conn * to client * @wk: smb work object @@ -639,7 +848,6 @@ { struct smb2_oplock_break *rsp = NULL; struct ksmbd_work *work = container_of(wk, struct ksmbd_work, work); - struct ksmbd_conn *conn = work->conn; struct oplock_break_info *br_info = work->request_buf; struct smb2_hdr *rsp_hdr; struct ksmbd_file *fp; @@ -648,7 +856,7 @@ if (!fp) goto out; - if (allocate_oplock_break_buf(work)) { + if (allocate_interim_rsp_buf(work)) { pr_err("smb2_allocate_rsp_buf failed! "); ksmbd_fd_put(work, fp); goto out; @@ -656,8 +864,6 @@ rsp_hdr = smb2_get_msg(work->response_buf); memset(rsp_hdr, 0, sizeof(struct smb2_hdr) + 2); - *(__be32 *)work->response_buf = - cpu_to_be32(conn->vals->header_size); rsp_hdr->ProtocolId = SMB2_PROTO_NUMBER; rsp_hdr->StructureSize = SMB2_HEADER_STRUCTURE_SIZE; rsp_hdr->CreditRequest = cpu_to_le16(0); @@ -684,13 +890,15 @@ rsp->PersistentFid = fp->persistent_id; rsp->VolatileFid = fp->volatile_id; - inc_rfc1001_len(work->response_buf, 24); + ksmbd_fd_put(work, fp); + if (ksmbd_iov_pin_rsp(work, (void *)rsp, + sizeof(struct smb2_oplock_break))) + goto out; ksmbd_debug(OPLOCK, "sending oplock break v_id %llu p_id = %llu lock level = %d\n", rsp->VolatileFid, rsp->PersistentFid, rsp->OplockLevel); - ksmbd_fd_put(work, fp); ksmbd_conn_write(work); out: @@ -751,18 +959,15 @@ struct smb2_lease_break *rsp = NULL; struct ksmbd_work *work = container_of(wk, struct ksmbd_work, work); struct lease_break_info *br_info = work->request_buf; - struct ksmbd_conn *conn = work->conn; struct smb2_hdr *rsp_hdr; - if (allocate_oplock_break_buf(work)) { + if (allocate_interim_rsp_buf(work)) { ksmbd_debug(OPLOCK, "smb2_allocate_rsp_buf failed! "); goto out; } rsp_hdr = smb2_get_msg(work->response_buf); memset(rsp_hdr, 0, sizeof(struct smb2_hdr) + 2); - *(__be32 *)work->response_buf = - cpu_to_be32(conn->vals->header_size); rsp_hdr->ProtocolId = SMB2_PROTO_NUMBER; rsp_hdr->StructureSize = SMB2_HEADER_STRUCTURE_SIZE; rsp_hdr->CreditRequest = cpu_to_le16(0); @@ -791,7 +996,9 @@ rsp->AccessMaskHint = 0; rsp->ShareMaskHint = 0; - inc_rfc1001_len(work->response_buf, 44); + if (ksmbd_iov_pin_rsp(work, (void *)rsp, + sizeof(struct smb2_lease_break))) + goto out; ksmbd_conn_write(work); @@ -844,7 +1051,8 @@ interim_entry); setup_async_work(in_work, NULL, NULL); smb2_send_interim_resp(in_work, STATUS_PENDING); - list_del(&in_work->interim_entry); + list_del_init(&in_work->interim_entry); + release_async_work(in_work); } INIT_WORK(&work->work, __smb2_lease_break_noti); ksmbd_queue_work(work); @@ -910,7 +1118,8 @@ lease->new_state = SMB2_LEASE_READ_CACHING_LE; } else { - if (lease->state & SMB2_LEASE_HANDLE_CACHING_LE) + if (lease->state & SMB2_LEASE_HANDLE_CACHING_LE && + !lease->is_dir) lease->new_state = SMB2_LEASE_READ_CACHING_LE; else @@ -933,10 +1142,20 @@ brk_opinfo->op_state = OPLOCK_ACK_WAIT; } +#ifdef CONFIG_SMB_INSECURE_SERVER + if (brk_opinfo->is_smb2) + if (brk_opinfo->is_lease) + err = smb2_lease_break_noti(brk_opinfo); + else + err = smb2_oplock_break_noti(brk_opinfo); + else + err = smb1_oplock_break_noti(brk_opinfo); +#else if (brk_opinfo->is_lease) err = smb2_lease_break_noti(brk_opinfo); else err = smb2_oplock_break_noti(brk_opinfo); +#endif ksmbd_debug(OPLOCK, "oplock granted = %d\n", brk_opinfo->level); if (brk_opinfo->op_state == OPLOCK_CLOSING) @@ -1042,6 +1261,8 @@ SMB2_LEASE_KEY_SIZE); lease2->duration = lease1->duration; lease2->flags = lease1->flags; + lease2->epoch = lease1->epoch; + lease2->version = lease1->version; } static int add_lease_global_list(struct oplock_info *opinfo) @@ -1078,6 +1299,10 @@ struct lease_ctx_info *lctx) { switch (level) { +#ifdef CONFIG_SMB_INSECURE_SERVER + case REQ_OPLOCK: + case REQ_BATCHOPLOCK: +#endif case SMB2_OPLOCK_LEVEL_BATCH: case SMB2_OPLOCK_LEVEL_EXCLUSIVE: grant_write_oplock(opinfo, level, lctx); @@ -1091,6 +1316,89 @@ } } +void smb_send_parent_lease_break_noti(struct ksmbd_file *fp, + struct lease_ctx_info *lctx) +{ + struct oplock_info *opinfo; + struct ksmbd_inode *p_ci = NULL; + + if (lctx->version != 2) + return; + + p_ci = ksmbd_inode_lookup_lock(fp->filp->f_path.dentry->d_parent); + if (!p_ci) + return; + + read_lock(&p_ci->m_lock); + list_for_each_entry(opinfo, &p_ci->m_op_list, op_entry) { + if (!opinfo->is_lease) + continue; + + if (opinfo->o_lease->state != SMB2_OPLOCK_LEVEL_NONE && + (!(lctx->flags & SMB2_LEASE_FLAG_PARENT_LEASE_KEY_SET_LE) || + !compare_guid_key(opinfo, fp->conn->ClientGUID, + lctx->parent_lease_key))) { + if (!atomic_inc_not_zero(&opinfo->refcount)) + continue; + + atomic_inc(&opinfo->conn->r_count); + if (ksmbd_conn_releasing(opinfo->conn)) { + atomic_dec(&opinfo->conn->r_count); + continue; + } + + read_unlock(&p_ci->m_lock); + oplock_break(opinfo, SMB2_OPLOCK_LEVEL_NONE); + opinfo_conn_put(opinfo); + read_lock(&p_ci->m_lock); + } + } + read_unlock(&p_ci->m_lock); + + ksmbd_inode_put(p_ci); +} + +void smb_lazy_parent_lease_break_close(struct ksmbd_file *fp) +{ + struct oplock_info *opinfo; + struct ksmbd_inode *p_ci = NULL; + + rcu_read_lock(); + opinfo = rcu_dereference(fp->f_opinfo); + rcu_read_unlock(); + + if (!opinfo || !opinfo->is_lease || opinfo->o_lease->version != 2) + return; + + p_ci = ksmbd_inode_lookup_lock(fp->filp->f_path.dentry->d_parent); + if (!p_ci) + return; + + read_lock(&p_ci->m_lock); + list_for_each_entry(opinfo, &p_ci->m_op_list, op_entry) { + if (!opinfo->is_lease) + continue; + + if (opinfo->o_lease->state != SMB2_OPLOCK_LEVEL_NONE) { + if (!atomic_inc_not_zero(&opinfo->refcount)) + continue; + + atomic_inc(&opinfo->conn->r_count); + if (ksmbd_conn_releasing(opinfo->conn)) { + atomic_dec(&opinfo->conn->r_count); + continue; + } + read_unlock(&p_ci->m_lock); + oplock_break(opinfo, SMB2_OPLOCK_LEVEL_NONE); + opinfo_conn_put(opinfo); + read_lock(&p_ci->m_lock); + } + } + read_unlock(&p_ci->m_lock); + + ksmbd_inode_put(p_ci); +} + /** * smb_grant_oplock() - handle oplock/lease request on file open * @work: smb work @@ -1114,9 +1422,11 @@ bool prev_op_has_lease; __le32 prev_op_state = 0; - /* not support directory lease */ - if (S_ISDIR(file_inode(fp->filp)->i_mode)) + /* Only v2 leases handle the directory */ + if (S_ISDIR(file_inode(fp->filp)->i_mode)) { + if (!lctx || lctx->version != 2) return 0; + } opinfo = alloc_opinfo(work, pid, tid); if (!opinfo) @@ -1286,6 +1596,36 @@ } rcu_read_unlock(); + +#ifdef CONFIG_SMB_INSECURE_SERVER + if (brk_op->is_smb2) { + if (brk_op->is_lease && (brk_op->o_lease->state & + (~(SMB2_LEASE_READ_CACHING_LE | + SMB2_LEASE_HANDLE_CACHING_LE)))) { + ksmbd_debug(OPLOCK, + "unexpected lease state(0x%x)\n", + brk_op->o_lease->state); + goto next; + } else if (brk_op->level != + SMB2_OPLOCK_LEVEL_II) { + ksmbd_debug(OPLOCK, "unexpected oplock(0x%x)\n", + brk_op->level); + goto next; + } + + /* Skip oplock being break to none */ + if (brk_op->is_lease && + brk_op->o_lease->new_state == SMB2_LEASE_NONE_LE && + atomic_read(&brk_op->breaking_cnt)) + goto next; + } else { + if (brk_op->level != OPLOCK_READ) { + ksmbd_debug(OPLOCK, "unexpected oplock(0x%x)\n", + brk_op->level); + goto next; + } + } +#else if (brk_op->is_lease && (brk_op->o_lease->state & (~(SMB2_LEASE_READ_CACHING_LE | SMB2_LEASE_HANDLE_CACHING_LE)))) { @@ -1304,6 +1644,7 @@ brk_op->o_lease->new_state == SMB2_LEASE_NONE_LE && atomic_read(&brk_op->breaking_cnt)) goto next; +#endif if (op && op->is_lease && brk_op->is_lease && !memcmp(conn->ClientGUID, brk_op->conn->ClientGUID, @@ -1374,6 +1715,7 @@ memcpy(buf->lcontext.LeaseKey, lease->lease_key, SMB2_LEASE_KEY_SIZE); buf->lcontext.LeaseFlags = lease->flags; + buf->lcontext.Epoch = cpu_to_le16(lease->epoch); buf->lcontext.LeaseState = lease->state; memcpy(buf->lcontext.ParentLeaseKey, lease->parent_lease_key, SMB2_LEASE_KEY_SIZE); @@ -1410,10 +1752,11 @@ /** * parse_lease_state() - parse lease context containted in file open request * @open_req: buffer containing smb2 file open(create) request + * @is_dir: whether leasing file is directory * * Return: oplock state, -ENOENT if create lease context not found */ -struct lease_ctx_info *parse_lease_state(void *open_req) +struct lease_ctx_info *parse_lease_state(void *open_req, bool is_dir) { struct create_context *cc; struct smb2_create_req *req = (struct smb2_create_req *)open_req; @@ -1431,8 +1774,14 @@ struct create_lease_v2 *lc = (struct create_lease_v2 *)cc; memcpy(lreq->lease_key, lc->lcontext.LeaseKey, SMB2_LEASE_KEY_SIZE); + if (is_dir) { + lreq->req_state = lc->lcontext.LeaseState & + ~SMB2_LEASE_WRITE_CACHING_LE; + lreq->is_dir = true; + } else lreq->req_state = lc->lcontext.LeaseState; lreq->flags = lc->lcontext.LeaseFlags; + lreq->epoch = lc->lcontext.Epoch; lreq->duration = lc->lcontext.LeaseDuration; memcpy(lreq->parent_lease_key, lc->lcontext.ParentLeaseKey, SMB2_LEASE_KEY_SIZE); @@ -1492,7 +1841,7 @@ name_len < 4 || name_off + name_len > cc_len || (value_off & 0x7) != 0 || - (value_off && (value_off < name_off + name_len)) || + (value_len && value_off < name_off + (name_len < 8 ? 8 : name_len)) || ((u64)value_off + value_len > cc_len)) return ERR_PTR(-EINVAL); diff -ruw linux-6.4/fs/smb/server/oplock.h linux-6.4-fbx/fs/smb/server/oplock.h --- linux-6.4/fs/smb/server/oplock.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/oplock.h 2024-01-25 13:36:32.714984559 +0100 @@ -11,6 +11,14 @@ #define OPLOCK_WAIT_TIME (35 * HZ) +#ifdef CONFIG_SMB_INSECURE_SERVER +/* SMB Oplock levels */ +#define OPLOCK_NONE 0 +#define OPLOCK_EXCLUSIVE 1 +#define OPLOCK_BATCH 2 +#define OPLOCK_READ 3 /* level 2 oplock */ +#endif + /* SMB2 Oplock levels */ #define SMB2_OPLOCK_LEVEL_NONE 0x00 #define SMB2_OPLOCK_LEVEL_II 0x01 @@ -34,7 +42,9 @@ __le32 flags; __le64 duration; __u8 parent_lease_key[SMB2_LEASE_KEY_SIZE]; + __le16 epoch; int version; + bool is_dir; }; struct lease_table { @@ -53,6 +63,7 @@ __u8 parent_lease_key[SMB2_LEASE_KEY_SIZE]; int version; unsigned short epoch; + bool is_dir; struct lease_table *l_lb; }; @@ -69,6 +80,9 @@ atomic_t refcount; __u16 Tid; bool is_lease; +#ifdef CONFIG_SMB_INSECURE_SERVER + bool is_smb2; +#endif bool open_trunc; /* truncate on open */ struct lease *o_lease; struct list_head interim_list; @@ -108,7 +122,7 @@ /* Lease related functions */ void create_lease_buf(u8 *rbuf, struct lease *lease); -struct lease_ctx_info *parse_lease_state(void *open_req); +struct lease_ctx_info *parse_lease_state(void *open_req, bool is_dir); __u8 smb2_map_lease_to_oplock(__le32 lease_state); int lease_read_to_write(struct oplock_info *opinfo); @@ -124,4 +138,7 @@ int find_same_lease_key(struct ksmbd_session *sess, struct ksmbd_inode *ci, struct lease_ctx_info *lctx); void destroy_lease_table(struct ksmbd_conn *conn); +void smb_send_parent_lease_break_noti(struct ksmbd_file *fp, + struct lease_ctx_info *lctx); +void smb_lazy_parent_lease_break_close(struct ksmbd_file *fp); #endif /* __KSMBD_OPLOCK_H */ diff -ruw linux-6.4/fs/smb/server/server.c linux-6.4-fbx/fs/smb/server/server.c --- linux-6.4/fs/smb/server/server.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/server.c 2023-11-07 13:38:44.042256145 +0100 @@ -115,8 +115,10 @@ if (check_conn_state(work)) return SERVER_HANDLER_CONTINUE; - if (ksmbd_verify_smb_message(work)) + if (ksmbd_verify_smb_message(work)) { + conn->ops->set_rsp_status(work, STATUS_INVALID_PARAMETER); return SERVER_HANDLER_ABORT; + } command = conn->ops->get_cmd_val(work); *cmd = command; @@ -163,6 +165,7 @@ { u16 command = 0; int rc; + bool is_chained = false; if (conn->ops->allocate_rsp_buf(work)) return; @@ -229,16 +232,17 @@ } } + is_chained = is_chained_smb2_message(work); + if (work->sess && (work->sess->sign || smb3_11_final_sess_setup_resp(work) || conn->ops->is_sign_req(work, command))) conn->ops->set_sign_rsp(work); - } while (is_chained_smb2_message(work)); - - if (work->send_no_response) - return; + } while (is_chained == true); send: + if (work->tcon) + ksmbd_tree_connect_put(work->tcon); smb3_preauth_hash_rsp(work); if (work->sess && work->sess->enc && work->encrypted && conn->ops->encrypt_resp) { @@ -286,6 +290,7 @@ static int queue_ksmbd_work(struct ksmbd_conn *conn) { struct ksmbd_work *work; + int err; work = ksmbd_alloc_work_struct(); if (!work) { @@ -297,7 +302,11 @@ work->request_buf = conn->request_buf; conn->request_buf = NULL; - ksmbd_init_smb_server(work); + err = ksmbd_init_smb_server(work); + if (err) { + ksmbd_free_work_struct(work); + return 0; + } ksmbd_conn_enqueue_request(work); atomic_inc(&conn->r_count); diff -ruw linux-6.4/fs/smb/server/smb2misc.c linux-6.4-fbx/fs/smb/server/smb2misc.c --- linux-6.4/fs/smb/server/smb2misc.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smb2misc.c 2024-03-22 17:24:19.542846394 +0100 @@ -101,29 +101,46 @@ *len = le16_to_cpu(((struct smb2_sess_setup_req *)hdr)->SecurityBufferLength); break; case SMB2_TREE_CONNECT: - *off = le16_to_cpu(((struct smb2_tree_connect_req *)hdr)->PathOffset); + *off = max_t(unsigned short int, + le16_to_cpu(((struct smb2_tree_connect_req *)hdr)->PathOffset), + offsetof(struct smb2_tree_connect_req, Buffer)); *len = le16_to_cpu(((struct smb2_tree_connect_req *)hdr)->PathLength); break; case SMB2_CREATE: { + unsigned short int name_off = + max_t(unsigned short int, + le16_to_cpu(((struct smb2_create_req *)hdr)->NameOffset), + offsetof(struct smb2_create_req, Buffer)); + unsigned short int name_len = + le16_to_cpu(((struct smb2_create_req *)hdr)->NameLength); + if (((struct smb2_create_req *)hdr)->CreateContextsLength) { *off = le32_to_cpu(((struct smb2_create_req *) hdr)->CreateContextsOffset); *len = le32_to_cpu(((struct smb2_create_req *) hdr)->CreateContextsLength); + if (!name_len) + break; + + if (name_off + name_len < (u64)*off + *len) break; } - *off = le16_to_cpu(((struct smb2_create_req *)hdr)->NameOffset); - *len = le16_to_cpu(((struct smb2_create_req *)hdr)->NameLength); + *off = name_off; + *len = name_len; break; } case SMB2_QUERY_INFO: - *off = le16_to_cpu(((struct smb2_query_info_req *)hdr)->InputBufferOffset); + *off = max_t(unsigned int, + le16_to_cpu(((struct smb2_query_info_req *)hdr)->InputBufferOffset), + offsetof(struct smb2_query_info_req, Buffer)); *len = le32_to_cpu(((struct smb2_query_info_req *)hdr)->InputBufferLength); break; case SMB2_SET_INFO: - *off = le16_to_cpu(((struct smb2_set_info_req *)hdr)->BufferOffset); + *off = max_t(unsigned int, + le16_to_cpu(((struct smb2_set_info_req *)hdr)->BufferOffset), + offsetof(struct smb2_set_info_req, Buffer)); *len = le32_to_cpu(((struct smb2_set_info_req *)hdr)->BufferLength); break; case SMB2_READ: @@ -133,7 +150,7 @@ case SMB2_WRITE: if (((struct smb2_write_req *)hdr)->DataOffset || ((struct smb2_write_req *)hdr)->Length) { - *off = max_t(unsigned int, + *off = max_t(unsigned short int, le16_to_cpu(((struct smb2_write_req *)hdr)->DataOffset), offsetof(struct smb2_write_req, Buffer)); *len = le32_to_cpu(((struct smb2_write_req *)hdr)->Length); @@ -144,7 +161,9 @@ *len = le16_to_cpu(((struct smb2_write_req *)hdr)->WriteChannelInfoLength); break; case SMB2_QUERY_DIRECTORY: - *off = le16_to_cpu(((struct smb2_query_directory_req *)hdr)->FileNameOffset); + *off = max_t(unsigned short int, + le16_to_cpu(((struct smb2_query_directory_req *)hdr)->FileNameOffset), + offsetof(struct smb2_query_directory_req, Buffer)); *len = le16_to_cpu(((struct smb2_query_directory_req *)hdr)->FileNameLength); break; case SMB2_LOCK: @@ -159,7 +178,9 @@ break; } case SMB2_IOCTL: - *off = le32_to_cpu(((struct smb2_ioctl_req *)hdr)->InputOffset); + *off = max_t(unsigned int, + le32_to_cpu(((struct smb2_ioctl_req *)hdr)->InputOffset), + offsetof(struct smb2_ioctl_req, Buffer)); *len = le32_to_cpu(((struct smb2_ioctl_req *)hdr)->InputCount); break; default: @@ -380,13 +401,13 @@ } if (smb2_req_struct_sizes[command] != pdu->StructureSize2) { - if (command == SMB2_OPLOCK_BREAK_HE && - le16_to_cpu(pdu->StructureSize2) != OP_BREAK_STRUCT_SIZE_20 && - le16_to_cpu(pdu->StructureSize2) != OP_BREAK_STRUCT_SIZE_21) { + if (!(command == SMB2_OPLOCK_BREAK_HE && + (le16_to_cpu(pdu->StructureSize2) == OP_BREAK_STRUCT_SIZE_20 || + le16_to_cpu(pdu->StructureSize2) == OP_BREAK_STRUCT_SIZE_21))) { /* special case for SMB2.1 lease break message */ ksmbd_debug(SMB, - "Illegal request size %d for oplock break\n", - le16_to_cpu(pdu->StructureSize2)); + "Illegal request size %u for command %d\n", + le16_to_cpu(pdu->StructureSize2), command); return 1; } } @@ -440,10 +461,8 @@ validate_credit: if ((work->conn->vals->capabilities & SMB2_GLOBAL_CAP_LARGE_MTU) && - smb2_validate_credit_charge(work->conn, hdr)) { - work->conn->ops->set_rsp_status(work, STATUS_INVALID_PARAMETER); + smb2_validate_credit_charge(work->conn, hdr)) return 1; - } return 0; } diff -ruw linux-6.4/fs/smb/server/smb2ops.c linux-6.4-fbx/fs/smb/server/smb2ops.c --- linux-6.4/fs/smb/server/smb2ops.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smb2ops.c 2024-04-19 15:59:31.193600561 +0200 @@ -12,6 +12,34 @@ #include "smb_common.h" #include "server.h" +#ifdef CONFIG_SMB_INSECURE_SERVER +static struct smb_version_values smb20_server_values = { + .version_string = SMB20_VERSION_STRING, + .protocol_id = SMB20_PROT_ID, + .capabilities = 0, + .max_read_size = CIFS_DEFAULT_IOSIZE, + .max_write_size = CIFS_DEFAULT_IOSIZE, + .max_trans_size = CIFS_DEFAULT_IOSIZE, + .max_credits = SMB2_MAX_CREDITS, + .large_lock_type = 0, + .exclusive_lock_type = SMB2_LOCKFLAG_EXCLUSIVE, + .shared_lock_type = SMB2_LOCKFLAG_SHARED, + .unlock_lock_type = SMB2_LOCKFLAG_UNLOCK, + .header_size = sizeof(struct smb2_hdr), + .max_header_size = MAX_SMB2_HDR_SIZE, + .read_rsp_size = sizeof(struct smb2_read_rsp) - 1, + .lock_cmd = SMB2_LOCK, + .cap_unix = 0, + .cap_nt_find = SMB2_NT_FIND, + .cap_large_files = SMB2_LARGE_FILES, + .create_lease_size = sizeof(struct create_lease), + .create_durable_size = sizeof(struct create_durable_rsp), + .create_mxac_size = sizeof(struct create_mxac_rsp), + .create_disk_id_size = sizeof(struct create_disk_id_rsp), + .create_posix_size = sizeof(struct create_posix_rsp), +}; +#endif + static struct smb_version_values smb21_server_values = { .version_string = SMB21_VERSION_STRING, .protocol_id = SMB21_PROT_ID, @@ -190,6 +218,22 @@ [SMB2_CHANGE_NOTIFY_HE] = { .proc = smb2_notify}, }; +#ifdef CONFIG_SMB_INSECURE_SERVER +/** + * init_smb2_0_server() - initialize a smb server connection with smb2.0 + * command dispatcher + * @conn: connection instance + */ +void init_smb2_0_server(struct ksmbd_conn *conn) +{ + conn->vals = &smb20_server_values; + conn->ops = &smb2_0_server_ops; + conn->cmds = smb2_0_server_cmds; + conn->max_cmds = ARRAY_SIZE(smb2_0_server_cmds); + conn->signing_algorithm = SIGNING_ALG_HMAC_SHA256; +} +#endif + /** * init_smb2_1_server() - initialize a smb server connection with smb2.1 * command dispatcher @@ -221,12 +265,18 @@ conn->signing_algorithm = SIGNING_ALG_AES_CMAC_LE; if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_LEASES) - conn->vals->capabilities |= SMB2_GLOBAL_CAP_LEASING; + conn->vals->capabilities |= SMB2_GLOBAL_CAP_LEASING | + SMB2_GLOBAL_CAP_DIRECTORY_LEASING; if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_ENCRYPTION && conn->cli_cap & SMB2_GLOBAL_CAP_ENCRYPTION) conn->vals->capabilities |= SMB2_GLOBAL_CAP_ENCRYPTION; + if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_ENCRYPTION || + (!(server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_ENCRYPTION_OFF) && + conn->cli_cap & SMB2_GLOBAL_CAP_ENCRYPTION)) + conn->vals->capabilities |= SMB2_GLOBAL_CAP_ENCRYPTION; + if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB3_MULTICHANNEL) conn->vals->capabilities |= SMB2_GLOBAL_CAP_MULTI_CHANNEL; } @@ -245,7 +295,8 @@ conn->signing_algorithm = SIGNING_ALG_AES_CMAC_LE; if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_LEASES) - conn->vals->capabilities |= SMB2_GLOBAL_CAP_LEASING; + conn->vals->capabilities |= SMB2_GLOBAL_CAP_LEASING | + SMB2_GLOBAL_CAP_DIRECTORY_LEASING; if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_ENCRYPTION || (!(server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_ENCRYPTION_OFF) && @@ -270,12 +321,8 @@ conn->signing_algorithm = SIGNING_ALG_AES_CMAC_LE; if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_LEASES) - conn->vals->capabilities |= SMB2_GLOBAL_CAP_LEASING; - - if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_ENCRYPTION || - (!(server_conf.flags & KSMBD_GLOBAL_FLAG_SMB2_ENCRYPTION_OFF) && - conn->cli_cap & SMB2_GLOBAL_CAP_ENCRYPTION)) - conn->vals->capabilities |= SMB2_GLOBAL_CAP_ENCRYPTION; + conn->vals->capabilities |= SMB2_GLOBAL_CAP_LEASING | + SMB2_GLOBAL_CAP_DIRECTORY_LEASING; if (server_conf.flags & KSMBD_GLOBAL_FLAG_SMB3_MULTICHANNEL) conn->vals->capabilities |= SMB2_GLOBAL_CAP_MULTI_CHANNEL; diff -ruw linux-6.4/fs/smb/server/smb2pdu.c linux-6.4-fbx/fs/smb/server/smb2pdu.c --- linux-6.4/fs/smb/server/smb2pdu.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smb2pdu.c 2024-04-19 15:59:31.197600671 +0200 @@ -87,9 +87,9 @@ */ int smb2_get_ksmbd_tcon(struct ksmbd_work *work) { - struct smb2_hdr *req_hdr = smb2_get_msg(work->request_buf); + struct smb2_hdr *req_hdr = ksmbd_req_buf_next(work); unsigned int cmd = le16_to_cpu(req_hdr->Command); - int tree_id; + unsigned int tree_id; if (cmd == SMB2_TREE_CONNECT_HE || cmd == SMB2_CANCEL_HE || @@ -114,7 +114,7 @@ pr_err("The first operation in the compound does not have tcon\n"); return -EINVAL; } - if (work->tcon->id != tree_id) { + if (tree_id != UINT_MAX && work->tcon->id != tree_id) { pr_err("tree id(%u) is different with id(%u) in first operation\n", tree_id, work->tcon->id); return -EINVAL; @@ -145,12 +145,18 @@ err_rsp = smb2_get_msg(work->response_buf); if (err_rsp->hdr.Status != STATUS_STOPPED_ON_SYMLINK) { + int err; + err_rsp->StructureSize = SMB2_ERROR_STRUCTURE_SIZE2_LE; err_rsp->ErrorContextCount = 0; err_rsp->Reserved = 0; err_rsp->ByteCount = 0; err_rsp->ErrorData[0] = 0; - inc_rfc1001_len(work->response_buf, SMB2_ERROR_STRUCTURE_SIZE2); + err = ksmbd_iov_pin_rsp(work, (void *)err_rsp, + __SMB2_HEADER_STRUCTURE_SIZE + + SMB2_ERROR_STRUCTURE_SIZE2); + if (err) + work->send_no_response = 1; } } @@ -225,11 +231,12 @@ { struct smb2_hdr *rsp_hdr; - if (work->next_smb2_rcv_hdr_off) - rsp_hdr = ksmbd_resp_buf_next(work); - else rsp_hdr = smb2_get_msg(work->response_buf); rsp_hdr->Status = err; + + work->iov_idx = 0; + work->iov_cnt = 0; + work->next_smb2_rcv_hdr_off = 0; smb2_set_err_rsp(work); } @@ -245,9 +252,7 @@ struct smb2_hdr *rsp_hdr; struct smb2_negotiate_rsp *rsp; struct ksmbd_conn *conn = work->conn; - - *(__be32 *)work->response_buf = - cpu_to_be32(conn->vals->header_size); + int err; rsp_hdr = smb2_get_msg(work->response_buf); memset(rsp_hdr, 0, sizeof(struct smb2_hdr) + 2); @@ -286,12 +291,13 @@ rsp->SecurityBufferLength = cpu_to_le16(AUTH_GSS_LENGTH); ksmbd_copy_gss_neg_header((char *)(&rsp->hdr) + le16_to_cpu(rsp->SecurityBufferOffset)); - inc_rfc1001_len(work->response_buf, - sizeof(struct smb2_negotiate_rsp) - - sizeof(struct smb2_hdr) + AUTH_GSS_LENGTH); rsp->SecurityMode = SMB2_NEGOTIATE_SIGNING_ENABLED_LE; if (server_conf.signing == KSMBD_CONFIG_OPT_MANDATORY) rsp->SecurityMode |= SMB2_NEGOTIATE_SIGNING_REQUIRED_LE; + err = ksmbd_iov_pin_rsp(work, rsp, + sizeof(struct smb2_negotiate_rsp) + AUTH_GSS_LENGTH); + if (err) + return err; conn->use_spnego = true; ksmbd_conn_set_need_negotiate(conn); @@ -390,11 +396,12 @@ next_hdr_offset = le32_to_cpu(req->NextCommand); new_len = ALIGN(len, 8); - inc_rfc1001_len(work->response_buf, - sizeof(struct smb2_hdr) + new_len - len); + work->iov[work->iov_idx].iov_len += (new_len - len); + inc_rfc1001_len(work->response_buf, new_len - len); rsp->NextCommand = cpu_to_le32(new_len); work->next_smb2_rcv_hdr_off += next_hdr_offset; + work->curr_smb2_rsp_hdr_off = work->next_smb2_rsp_hdr_off; work->next_smb2_rsp_hdr_off += new_len; ksmbd_debug(SMB, "Compound req new_len = %d rcv off = %d rsp off = %d\n", @@ -470,10 +477,10 @@ len = len - get_rfc1002_len(work->response_buf); if (len) { ksmbd_debug(SMB, "padding len %u\n", len); + work->iov[work->iov_idx].iov_len += len; inc_rfc1001_len(work->response_buf, len); - if (work->aux_payload_sz) - work->aux_payload_sz += len; } + work->curr_smb2_rsp_hdr_off = work->next_smb2_rsp_hdr_off; } return false; } @@ -488,11 +495,8 @@ { struct smb2_hdr *rsp_hdr = smb2_get_msg(work->response_buf); struct smb2_hdr *rcv_hdr = smb2_get_msg(work->request_buf); - struct ksmbd_conn *conn = work->conn; memset(rsp_hdr, 0, sizeof(struct smb2_hdr) + 2); - *(__be32 *)work->response_buf = - cpu_to_be32(conn->vals->header_size); rsp_hdr->ProtocolId = rcv_hdr->ProtocolId; rsp_hdr->StructureSize = SMB2_HEADER_STRUCTURE_SIZE; rsp_hdr->Command = rcv_hdr->Command; @@ -543,7 +547,7 @@ if (le32_to_cpu(hdr->NextCommand) > 0) sz = large_sz; - work->response_buf = kvmalloc(sz, GFP_KERNEL | __GFP_ZERO); + work->response_buf = kvzalloc(sz, GFP_KERNEL); if (!work->response_buf) return -ENOMEM; @@ -559,9 +563,9 @@ */ int smb2_check_user_session(struct ksmbd_work *work) { - struct smb2_hdr *req_hdr = smb2_get_msg(work->request_buf); + struct smb2_hdr *req_hdr = ksmbd_req_buf_next(work); struct ksmbd_conn *conn = work->conn; - unsigned int cmd = conn->ops->get_cmd_val(work); + unsigned int cmd = le16_to_cpu(req_hdr->Command); unsigned long long sess_id; /* @@ -587,7 +591,7 @@ pr_err("The first operation in the compound does not have sess\n"); return -EINVAL; } - if (work->sess->id != sess_id) { + if (sess_id != ULLONG_MAX && work->sess->id != sess_id) { pr_err("session id(%llu) is different with the first operation(%lld)\n", sess_id, work->sess->id); return -EINVAL; @@ -653,13 +657,9 @@ int setup_async_work(struct ksmbd_work *work, void (*fn)(void **), void **arg) { - struct smb2_hdr *rsp_hdr; struct ksmbd_conn *conn = work->conn; int id; - rsp_hdr = smb2_get_msg(work->response_buf); - rsp_hdr->Flags |= SMB2_FLAGS_ASYNC_COMMAND; - id = ksmbd_acquire_async_msg_id(&conn->async_ida); if (id < 0) { pr_err("Failed to alloc async message id\n"); @@ -667,7 +667,6 @@ } work->asynchronous = true; work->async_id = id; - rsp_hdr->Id.AsyncId = cpu_to_le64(id); ksmbd_debug(SMB, "Send interim Response to inform async request id : %d\n", @@ -706,15 +705,26 @@ void smb2_send_interim_resp(struct ksmbd_work *work, __le32 status) { struct smb2_hdr *rsp_hdr; + struct ksmbd_work *in_work = ksmbd_alloc_work_struct(); - rsp_hdr = smb2_get_msg(work->response_buf); - smb2_set_err_rsp(work); + if (allocate_interim_rsp_buf(in_work)) { + pr_err("smb_allocate_rsp_buf failed!\n"); + ksmbd_free_work_struct(in_work); + return; + } + + in_work->conn = work->conn; + memcpy(smb2_get_msg(in_work->response_buf), ksmbd_resp_buf_next(work), + __SMB2_HEADER_STRUCTURE_SIZE); + + rsp_hdr = smb2_get_msg(in_work->response_buf); + rsp_hdr->Flags |= SMB2_FLAGS_ASYNC_COMMAND; + rsp_hdr->Id.AsyncId = cpu_to_le64(work->async_id); + smb2_set_err_rsp(in_work); rsp_hdr->Status = status; - work->multiRsp = 1; - ksmbd_conn_write(work); - rsp_hdr->Status = 0; - work->multiRsp = 0; + ksmbd_conn_write(in_work); + ksmbd_free_work_struct(in_work); } static __le32 smb2_get_reparse_tag_special_file(umode_t mode) @@ -821,9 +831,8 @@ pneg_ctxt->Name[15] = 0x7C; } -static void assemble_neg_contexts(struct ksmbd_conn *conn, - struct smb2_negotiate_rsp *rsp, - void *smb2_buf_len) +static unsigned int assemble_neg_contexts(struct ksmbd_conn *conn, + struct smb2_negotiate_rsp *rsp) { char * const pneg_ctxt = (char *)rsp + le32_to_cpu(rsp->NegotiateContextOffset); @@ -834,7 +843,6 @@ "assemble SMB2_PREAUTH_INTEGRITY_CAPABILITIES context\n"); build_preauth_ctxt((struct smb2_preauth_neg_context *)pneg_ctxt, conn->preauth_info->Preauth_HashId); - inc_rfc1001_len(smb2_buf_len, AUTH_GSS_PADDING); ctxt_size = sizeof(struct smb2_preauth_neg_context); if (conn->cipher_type) { @@ -874,7 +882,7 @@ } rsp->NegotiateContextCount = cpu_to_le16(neg_ctxt_cnt); - inc_rfc1001_len(smb2_buf_len, ctxt_size); + return ctxt_size + AUTH_GSS_PADDING; } static __le32 decode_preauth_ctxt(struct ksmbd_conn *conn, @@ -1090,7 +1098,7 @@ struct smb2_negotiate_req *req = smb2_get_msg(work->request_buf); struct smb2_negotiate_rsp *rsp = smb2_get_msg(work->response_buf); int rc = 0; - unsigned int smb2_buf_len, smb2_neg_size; + unsigned int smb2_buf_len, smb2_neg_size, neg_ctxt_len = 0; __le32 status; ksmbd_debug(SMB, "Received negotiate request\n"); @@ -1183,7 +1191,7 @@ conn->preauth_info->Preauth_HashValue); rsp->NegotiateContextOffset = cpu_to_le32(OFFSET_OF_NEG_CONTEXT); - assemble_neg_contexts(conn, rsp, work->response_buf); + neg_ctxt_len = assemble_neg_contexts(conn, rsp); break; case SMB302_PROT_ID: init_smb3_02_server(conn); @@ -1194,6 +1202,11 @@ case SMB21_PROT_ID: init_smb2_1_server(conn); break; +#ifdef CONFIG_SMB_INSECURE_SERVER + case SMB20_PROT_ID: + init_smb2_0_server(conn); + break; +#endif case SMB2X_PROT_ID: case BAD_PROT_ID: default: @@ -1233,8 +1246,7 @@ rsp->SecurityBufferLength = cpu_to_le16(AUTH_GSS_LENGTH); ksmbd_copy_gss_neg_header((char *)(&rsp->hdr) + le16_to_cpu(rsp->SecurityBufferOffset)); - inc_rfc1001_len(work->response_buf, sizeof(struct smb2_negotiate_rsp) - - sizeof(struct smb2_hdr) + AUTH_GSS_LENGTH); + rsp->SecurityMode = SMB2_NEGOTIATE_SIGNING_ENABLED_LE; conn->use_spnego = true; @@ -1252,9 +1264,15 @@ ksmbd_conn_set_need_negotiate(conn); err_out: + if (rc) + rsp->hdr.Status = STATUS_INSUFFICIENT_RESOURCES; + + if (!rc) + rc = ksmbd_iov_pin_rsp(work, rsp, + sizeof(struct smb2_negotiate_rsp) + + AUTH_GSS_LENGTH + neg_ctxt_len); if (rc < 0) smb2_set_err_rsp(work); - return rc; } @@ -1322,9 +1340,8 @@ static int ntlm_negotiate(struct ksmbd_work *work, struct negotiate_message *negblob, - size_t negblob_len) + size_t negblob_len, struct smb2_sess_setup_rsp *rsp) { - struct smb2_sess_setup_rsp *rsp = smb2_get_msg(work->response_buf); struct challenge_message *chgblob; unsigned char *spnego_blob = NULL; u16 spnego_blob_len; @@ -1402,6 +1419,9 @@ char *name; unsigned int name_off, name_len, secbuf_len; + if (conn->use_spnego && conn->mechToken) + secbuf_len = conn->mechTokenLen; + else secbuf_len = le16_to_cpu(req->SecurityBufferLength); if (secbuf_len < sizeof(struct authenticate_message)) { ksmbd_debug(SMB, "blob len %d too small\n", secbuf_len); @@ -1429,10 +1449,10 @@ return user; } -static int ntlm_authenticate(struct ksmbd_work *work) +static int ntlm_authenticate(struct ksmbd_work *work, + struct smb2_sess_setup_req *req, + struct smb2_sess_setup_rsp *rsp) { - struct smb2_sess_setup_req *req = smb2_get_msg(work->request_buf); - struct smb2_sess_setup_rsp *rsp = smb2_get_msg(work->response_buf); struct ksmbd_conn *conn = work->conn; struct ksmbd_session *sess = work->sess; struct channel *chann = NULL; @@ -1455,7 +1475,6 @@ memcpy((char *)&rsp->hdr.ProtocolId + sz, spnego_blob, spnego_blob_len); rsp->SecurityBufferLength = cpu_to_le16(spnego_blob_len); kfree(spnego_blob); - inc_rfc1001_len(work->response_buf, spnego_blob_len - 1); } user = session_user(conn, req); @@ -1494,6 +1513,9 @@ struct authenticate_message *authblob; authblob = user_authblob(conn, req); + if (conn->use_spnego && conn->mechToken) + sz = conn->mechTokenLen; + else sz = le16_to_cpu(req->SecurityBufferLength); rc = ksmbd_decode_ntlmssp_auth_blob(authblob, sz, conn, sess); if (rc) { @@ -1566,10 +1588,10 @@ } #ifdef CONFIG_SMB_SERVER_KERBEROS5 -static int krb5_authenticate(struct ksmbd_work *work) +static int krb5_authenticate(struct ksmbd_work *work, + struct smb2_sess_setup_req *req, + struct smb2_sess_setup_rsp *rsp) { - struct smb2_sess_setup_req *req = smb2_get_msg(work->request_buf); - struct smb2_sess_setup_rsp *rsp = smb2_get_msg(work->response_buf); struct ksmbd_conn *conn = work->conn; struct ksmbd_session *sess = work->sess; char *in_blob, *out_blob; @@ -1601,7 +1623,6 @@ return -EINVAL; } rsp->SecurityBufferLength = cpu_to_le16(out_len); - inc_rfc1001_len(work->response_buf, out_len - 1); if ((conn->sign || server_conf.enforced_signing) || (req->SecurityMode & SMB2_NEGOTIATE_SIGNING_REQUIRED)) @@ -1647,7 +1668,9 @@ return 0; } #else -static int krb5_authenticate(struct ksmbd_work *work) +static int krb5_authenticate(struct ksmbd_work *work, + struct smb2_sess_setup_req *req, + struct smb2_sess_setup_rsp *rsp) { return -EOPNOTSUPP; } @@ -1656,8 +1679,8 @@ int smb2_sess_setup(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; - struct smb2_sess_setup_req *req = smb2_get_msg(work->request_buf); - struct smb2_sess_setup_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_sess_setup_req *req; + struct smb2_sess_setup_rsp *rsp; struct ksmbd_session *sess; struct negotiate_message *negblob; unsigned int negblob_len, negblob_off; @@ -1665,11 +1688,12 @@ ksmbd_debug(SMB, "Received request for session setup\n"); + WORK_BUFFERS(work, req, rsp); + rsp->StructureSize = cpu_to_le16(9); rsp->SessionFlags = 0; rsp->SecurityBufferOffset = cpu_to_le16(72); rsp->SecurityBufferLength = 0; - inc_rfc1001_len(work->response_buf, 9); ksmbd_conn_lock(conn); if (!req->hdr.SessionId) { @@ -1765,8 +1789,7 @@ negblob_off = le16_to_cpu(req->SecurityBufferOffset); negblob_len = le16_to_cpu(req->SecurityBufferLength); - if (negblob_off < offsetof(struct smb2_sess_setup_req, Buffer) || - negblob_len < offsetof(struct negotiate_message, NegotiateFlags)) { + if (negblob_off < offsetof(struct smb2_sess_setup_req, Buffer)) { rc = -EINVAL; goto out_err; } @@ -1775,8 +1798,15 @@ negblob_off); if (decode_negotiation_token(conn, negblob, negblob_len) == 0) { - if (conn->mechToken) + if (conn->mechToken) { negblob = (struct negotiate_message *)conn->mechToken; + negblob_len = conn->mechTokenLen; + } + } + + if (negblob_len < offsetof(struct negotiate_message, NegotiateFlags)) { + rc = -EINVAL; + goto out_err; } if (server_conf.auth_mechs & conn->auth_mechs) { @@ -1786,7 +1816,7 @@ if (conn->preferred_auth_mech & (KSMBD_AUTH_KRB5 | KSMBD_AUTH_MSKRB5)) { - rc = krb5_authenticate(work); + rc = krb5_authenticate(work, req, rsp); if (rc) { rc = -EINVAL; goto out_err; @@ -1800,20 +1830,13 @@ sess->Preauth_HashValue = NULL; } else if (conn->preferred_auth_mech == KSMBD_AUTH_NTLMSSP) { if (negblob->MessageType == NtLmNegotiate) { - rc = ntlm_negotiate(work, negblob, negblob_len); + rc = ntlm_negotiate(work, negblob, negblob_len, rsp); if (rc) goto out_err; rsp->hdr.Status = STATUS_MORE_PROCESSING_REQUIRED; - /* - * Note: here total size -1 is done as an - * adjustment for 0 size blob - */ - inc_rfc1001_len(work->response_buf, - le16_to_cpu(rsp->SecurityBufferLength) - 1); - } else if (negblob->MessageType == NtLmAuthenticate) { - rc = ntlm_authenticate(work); + rc = ntlm_authenticate(work, req, rsp); if (rc) goto out_err; @@ -1896,6 +1919,18 @@ ksmbd_conn_set_need_negotiate(conn); } } + smb2_set_err_rsp(work); + } else { + unsigned int iov_len; + + if (rsp->SecurityBufferLength) + iov_len = offsetof(struct smb2_sess_setup_rsp, Buffer) + + le16_to_cpu(rsp->SecurityBufferLength); + else + iov_len = sizeof(struct smb2_sess_setup_rsp); + rc = ksmbd_iov_pin_rsp(work, rsp, iov_len); + if (rc) + rsp->hdr.Status = STATUS_INSUFFICIENT_RESOURCES; } ksmbd_conn_unlock(conn); @@ -1911,15 +1946,17 @@ int smb2_tree_connect(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; - struct smb2_tree_connect_req *req = smb2_get_msg(work->request_buf); - struct smb2_tree_connect_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_tree_connect_req *req; + struct smb2_tree_connect_rsp *rsp; struct ksmbd_session *sess = work->sess; char *treename = NULL, *name = NULL; struct ksmbd_tree_conn_status status; struct ksmbd_share_config *share; int rc = -EINVAL; - treename = smb_strndup_from_utf16(req->Buffer, + WORK_BUFFERS(work, req, rsp); + + treename = smb_strndup_from_utf16((char *)req + le16_to_cpu(req->PathOffset), le16_to_cpu(req->PathLength), true, conn->local_nls); if (IS_ERR(treename)) { @@ -1971,14 +2008,20 @@ if (conn->posix_ext_supported) status.tree_conn->posix_extensions = true; + write_lock(&sess->tree_conns_lock); + status.tree_conn->t_state = TREE_CONNECTED; + write_unlock(&sess->tree_conns_lock); rsp->StructureSize = cpu_to_le16(16); - inc_rfc1001_len(work->response_buf, 16); out_err1: rsp->Capabilities = 0; rsp->Reserved = 0; /* default manual caching */ rsp->ShareFlags = SMB2_SHAREFLAG_MANUAL_CACHING; + rc = ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_tree_connect_rsp)); + if (rc) + status.ret = KSMBD_TREE_CONN_STATUS_NOMEM; + if (!IS_ERR(treename)) kfree(treename); if (!IS_ERR(name)) @@ -2087,30 +2130,60 @@ */ int smb2_tree_disconnect(struct ksmbd_work *work) { - struct smb2_tree_disconnect_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_tree_disconnect_rsp *rsp; + struct smb2_tree_disconnect_req *req; struct ksmbd_session *sess = work->sess; struct ksmbd_tree_connect *tcon = work->tcon; + int err; - rsp->StructureSize = cpu_to_le16(4); - inc_rfc1001_len(work->response_buf, 4); + WORK_BUFFERS(work, req, rsp); ksmbd_debug(SMB, "request\n"); - if (!tcon || test_and_set_bit(TREE_CONN_EXPIRE, &tcon->status)) { - struct smb2_tree_disconnect_req *req = - smb2_get_msg(work->request_buf); - + if (!tcon) { ksmbd_debug(SMB, "Invalid tid %d\n", req->hdr.Id.SyncId.TreeId); rsp->hdr.Status = STATUS_NETWORK_NAME_DELETED; - smb2_set_err_rsp(work); - return 0; + err = -ENOENT; + goto err_out; } ksmbd_close_tree_conn_fds(work); - ksmbd_tree_conn_disconnect(sess, tcon); + + write_lock(&sess->tree_conns_lock); + if (tcon->t_state == TREE_DISCONNECTED) { + write_unlock(&sess->tree_conns_lock); + rsp->hdr.Status = STATUS_NETWORK_NAME_DELETED; + err = -ENOENT; + goto err_out; + } + + WARN_ON_ONCE(atomic_dec_and_test(&tcon->refcount)); + tcon->t_state = TREE_DISCONNECTED; + write_unlock(&sess->tree_conns_lock); + + err = ksmbd_tree_conn_disconnect(sess, tcon); + if (err) { + rsp->hdr.Status = STATUS_NETWORK_NAME_DELETED; + goto err_out; + } + work->tcon = NULL; + + rsp->StructureSize = cpu_to_le16(4); + err = ksmbd_iov_pin_rsp(work, rsp, + sizeof(struct smb2_tree_disconnect_rsp)); + if (err) { + rsp->hdr.Status = STATUS_INSUFFICIENT_RESOURCES; + goto err_out; + } + return 0; + +err_out: + smb2_set_err_rsp(work); + return err; + } /** @@ -2122,17 +2195,27 @@ int smb2_session_logoff(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; - struct smb2_logoff_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_logoff_req *req; + struct smb2_logoff_rsp *rsp; struct ksmbd_session *sess; - struct smb2_logoff_req *req = smb2_get_msg(work->request_buf); - u64 sess_id = le64_to_cpu(req->hdr.SessionId); + u64 sess_id; + int err; - rsp->StructureSize = cpu_to_le16(4); - inc_rfc1001_len(work->response_buf, 4); + WORK_BUFFERS(work, req, rsp); ksmbd_debug(SMB, "request\n"); + ksmbd_conn_lock(conn); + if (!ksmbd_conn_good(conn)) { + ksmbd_conn_unlock(conn); + rsp->hdr.Status = STATUS_NETWORK_NAME_DELETED; + smb2_set_err_rsp(work); + return -ENOENT; + } + sess_id = le64_to_cpu(req->hdr.SessionId); ksmbd_all_conn_set_status(sess_id, KSMBD_SESS_NEED_RECONNECT); + ksmbd_conn_unlock(conn); + ksmbd_close_session_fds(work); ksmbd_conn_wait_idle(conn, sess_id); @@ -2145,7 +2228,7 @@ ksmbd_debug(SMB, "Invalid tid %d\n", req->hdr.Id.SyncId.TreeId); rsp->hdr.Status = STATUS_NETWORK_NAME_DELETED; smb2_set_err_rsp(work); - return 0; + return -ENOENT; } ksmbd_destroy_file_table(&sess->file_table); @@ -2154,6 +2237,14 @@ ksmbd_free_user(sess->user); sess->user = NULL; ksmbd_all_conn_set_status(sess_id, KSMBD_SESS_NEED_NEGOTIATE); + + rsp->StructureSize = cpu_to_le16(4); + err = ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_logoff_rsp)); + if (err) { + rsp->hdr.Status = STATUS_INSUFFICIENT_RESOURCES; + smb2_set_err_rsp(work); + return err; + } return 0; } @@ -2165,12 +2256,14 @@ */ static noinline int create_smb2_pipe(struct ksmbd_work *work) { - struct smb2_create_rsp *rsp = smb2_get_msg(work->response_buf); - struct smb2_create_req *req = smb2_get_msg(work->request_buf); + struct smb2_create_rsp *rsp; + struct smb2_create_req *req; int id; int err; char *name; + WORK_BUFFERS(work, req, rsp); + name = smb_strndup_from_utf16(req->Buffer, le16_to_cpu(req->NameLength), 1, work->conn->local_nls); if (IS_ERR(name)) { @@ -2204,7 +2297,10 @@ rsp->CreateContextsOffset = 0; rsp->CreateContextsLength = 0; - inc_rfc1001_len(work->response_buf, 88); /* StructureSize - 1*/ + err = ksmbd_iov_pin_rsp(work, rsp, offsetof(struct smb2_create_rsp, Buffer)); + if (err) + goto out; + kfree(name); return 0; @@ -2232,11 +2328,12 @@ * @eabuf: set info command buffer * @buf_len: set info command buffer length * @path: dentry path for get ea + * @get_write: get write access to a mount * * Return: 0 on success, otherwise error */ static int smb2_set_ea(struct smb2_ea_info *eabuf, unsigned int buf_len, - const struct path *path) + const struct path *path, bool get_write) { struct mnt_idmap *idmap = mnt_idmap(path->mnt); char *attr_name = NULL, *value; @@ -2298,7 +2395,8 @@ rc = 0; } else { rc = ksmbd_vfs_setxattr(idmap, path, attr_name, value, - le16_to_cpu(eabuf->EaValueLength), 0); + le16_to_cpu(eabuf->EaValueLength), + 0, true); if (rc < 0) { ksmbd_debug(SMB, "ksmbd_vfs_setxattr is failed(%d)\n", @@ -2313,9 +2411,16 @@ break; buf_len -= next; eabuf = (struct smb2_ea_info *)((char *)eabuf + next); - if (next < (u32)eabuf->EaNameLength + le16_to_cpu(eabuf->EaValueLength)) + if (buf_len < sizeof(struct smb2_ea_info)) { + rc = -EINVAL; break; + } + if (buf_len < sizeof(struct smb2_ea_info) + eabuf->EaNameLength + + le16_to_cpu(eabuf->EaValueLength)) { + rc = -EINVAL; + break; + } } while (next != 0); kfree(attr_name); @@ -2354,7 +2459,7 @@ return -EBADF; } - rc = ksmbd_vfs_setxattr(idmap, path, xattr_stream_name, NULL, 0, 0); + rc = ksmbd_vfs_setxattr(idmap, path, xattr_stream_name, NULL, 0, 0, false); if (rc < 0) pr_err("Failed to store XATTR stream name :%d\n", rc); return 0; @@ -2429,7 +2534,7 @@ da.flags = XATTR_DOSINFO_ATTRIB | XATTR_DOSINFO_CREATE_TIME | XATTR_DOSINFO_ITIME; - rc = ksmbd_vfs_set_dos_attrib_xattr(mnt_idmap(path->mnt), path, &da); + rc = ksmbd_vfs_set_dos_attrib_xattr(mnt_idmap(path->mnt), path, &da, true); if (rc) ksmbd_debug(SMB, "failed to store file attribute into xattr\n"); } @@ -2456,8 +2561,9 @@ } } -static int smb2_creat(struct ksmbd_work *work, struct path *path, char *name, - int open_flags, umode_t posix_mode, bool is_dir) +static int smb2_creat(struct ksmbd_work *work, struct path *parent_path, + struct path *path, char *name, int open_flags, + umode_t posix_mode, bool is_dir) { struct ksmbd_tree_connect *tcon = work->tcon; struct ksmbd_share_config *share = tcon->share_conf; @@ -2484,7 +2590,7 @@ return rc; } - rc = ksmbd_vfs_kern_path_locked(work, name, 0, path, 0); + rc = ksmbd_vfs_kern_path_locked(work, name, 0, parent_path, path, 0); if (rc) { pr_err("cannot get linux path (%s), err = %d\n", name, rc); @@ -2518,7 +2624,7 @@ sizeof(struct create_sd_buf_req)) return -EINVAL; return set_info_sec(work->conn, work->tcon, path, &sd_buf->ntsd, - le32_to_cpu(sd_buf->ccontext.DataLength), true); + le32_to_cpu(sd_buf->ccontext.DataLength), true, false); } static void ksmbd_acls_fattr(struct smb_fattr *fattr, @@ -2554,7 +2660,7 @@ struct ksmbd_tree_connect *tcon = work->tcon; struct smb2_create_req *req; struct smb2_create_rsp *rsp; - struct path path; + struct path path, parent_path; struct ksmbd_share_config *share = tcon->share_conf; struct ksmbd_file *fp = NULL; struct file *filp = NULL; @@ -2578,6 +2684,7 @@ u64 time; umode_t posix_mode = 0; __le32 daccess, maximal_access = 0; + int iov_len = 0; WORK_BUFFERS(work, req, rsp); @@ -2599,10 +2706,10 @@ *(char *)req->Buffer == '\\') { pr_err("not allow directory name included leading slash\n"); rc = -EINVAL; - goto err_out1; + goto err_out2; } - name = smb2_get_name(req->Buffer, + name = smb2_get_name((char *)req + le16_to_cpu(req->NameOffset), le16_to_cpu(req->NameLength), work->conn->local_nls); if (IS_ERR(name)) { @@ -2610,7 +2717,7 @@ if (rc != -ENOMEM) rc = -ENOENT; name = NULL; - goto err_out1; + goto err_out2; } ksmbd_debug(SMB, "converted name = %s\n", name); @@ -2618,48 +2725,44 @@ if (!test_share_config_flag(work->tcon->share_conf, KSMBD_SHARE_FLAG_STREAMS)) { rc = -EBADF; - goto err_out1; + goto err_out2; } rc = parse_stream_name(name, &stream_name, &s_type); if (rc < 0) - goto err_out1; + goto err_out2; } rc = ksmbd_validate_filename(name); if (rc < 0) - goto err_out1; + goto err_out2; if (ksmbd_share_veto_filename(share, name)) { rc = -ENOENT; ksmbd_debug(SMB, "Reject open(), vetoed file: %s\n", name); - goto err_out1; + goto err_out2; } } else { name = kstrdup("", GFP_KERNEL); if (!name) { rc = -ENOMEM; - goto err_out1; + goto err_out2; } } - req_op_level = req->RequestedOplockLevel; - if (req_op_level == SMB2_OPLOCK_LEVEL_LEASE) - lc = parse_lease_state(req); - if (le32_to_cpu(req->ImpersonationLevel) > le32_to_cpu(IL_DELEGATE)) { pr_err("Invalid impersonationlevel : 0x%x\n", le32_to_cpu(req->ImpersonationLevel)); rc = -EIO; rsp->hdr.Status = STATUS_BAD_IMPERSONATION_LEVEL; - goto err_out1; + goto err_out2; } if (req->CreateOptions && !(req->CreateOptions & CREATE_OPTIONS_MASK_LE)) { pr_err("Invalid create options : 0x%x\n", le32_to_cpu(req->CreateOptions)); rc = -EINVAL; - goto err_out1; + goto err_out2; } else { if (req->CreateOptions & FILE_SEQUENTIAL_ONLY_LE && req->CreateOptions & FILE_RANDOM_ACCESS_LE) @@ -2669,13 +2772,13 @@ (FILE_OPEN_BY_FILE_ID_LE | CREATE_TREE_CONNECTION | FILE_RESERVE_OPFILTER_LE)) { rc = -EOPNOTSUPP; - goto err_out1; + goto err_out2; } if (req->CreateOptions & FILE_DIRECTORY_FILE_LE) { if (req->CreateOptions & FILE_NON_DIRECTORY_FILE_LE) { rc = -EINVAL; - goto err_out1; + goto err_out2; } else if (req->CreateOptions & FILE_NO_COMPRESSION_LE) { req->CreateOptions = ~(FILE_NO_COMPRESSION_LE); } @@ -2687,21 +2790,21 @@ pr_err("Invalid create disposition : 0x%x\n", le32_to_cpu(req->CreateDisposition)); rc = -EINVAL; - goto err_out1; + goto err_out2; } if (!(req->DesiredAccess & DESIRED_ACCESS_MASK)) { pr_err("Invalid desired access : 0x%x\n", le32_to_cpu(req->DesiredAccess)); rc = -EACCES; - goto err_out1; + goto err_out2; } if (req->FileAttributes && !(req->FileAttributes & FILE_ATTRIBUTE_MASK_LE)) { pr_err("Invalid file attribute : 0x%x\n", le32_to_cpu(req->FileAttributes)); rc = -EINVAL; - goto err_out1; + goto err_out2; } if (req->CreateContextsOffset) { @@ -2709,19 +2812,19 @@ context = smb2_find_context_vals(req, SMB2_CREATE_EA_BUFFER, 4); if (IS_ERR(context)) { rc = PTR_ERR(context); - goto err_out1; + goto err_out2; } else if (context) { ea_buf = (struct create_ea_buf_req *)context; if (le16_to_cpu(context->DataOffset) + le32_to_cpu(context->DataLength) < sizeof(struct create_ea_buf_req)) { rc = -EINVAL; - goto err_out1; + goto err_out2; } if (req->CreateOptions & FILE_NO_EA_KNOWLEDGE_LE) { rsp->hdr.Status = STATUS_ACCESS_DENIED; rc = -EACCES; - goto err_out1; + goto err_out2; } } @@ -2729,7 +2832,7 @@ SMB2_CREATE_QUERY_MAXIMAL_ACCESS_REQUEST, 4); if (IS_ERR(context)) { rc = PTR_ERR(context); - goto err_out1; + goto err_out2; } else if (context) { ksmbd_debug(SMB, "get query maximal access context\n"); @@ -2740,11 +2843,11 @@ SMB2_CREATE_TIMEWARP_REQUEST, 4); if (IS_ERR(context)) { rc = PTR_ERR(context); - goto err_out1; + goto err_out2; } else if (context) { ksmbd_debug(SMB, "get timewarp context\n"); rc = -EBADF; - goto err_out1; + goto err_out2; } if (tcon->posix_extensions) { @@ -2752,7 +2855,7 @@ SMB2_CREATE_TAG_POSIX, 16); if (IS_ERR(context)) { rc = PTR_ERR(context); - goto err_out1; + goto err_out2; } else if (context) { struct create_posix *posix = (struct create_posix *)context; @@ -2760,7 +2863,7 @@ le32_to_cpu(context->DataLength) < sizeof(struct create_posix) - 4) { rc = -EINVAL; - goto err_out1; + goto err_out2; } ksmbd_debug(SMB, "get posix context\n"); @@ -2772,10 +2875,11 @@ if (ksmbd_override_fsids(work)) { rc = -ENOMEM; - goto err_out1; + goto err_out2; } - rc = ksmbd_vfs_kern_path_locked(work, name, LOOKUP_NO_SYMLINKS, &path, 1); + rc = ksmbd_vfs_kern_path_locked(work, name, LOOKUP_NO_SYMLINKS, + &parent_path, &path, 1); if (!rc) { file_present = true; @@ -2872,11 +2976,9 @@ if (!file_present) { daccess = cpu_to_le32(GENERIC_ALL_FLAGS); } else { - rc = ksmbd_vfs_query_maximal_access(idmap, + ksmbd_vfs_query_maximal_access(idmap, path.dentry, &daccess); - if (rc) - goto err_out; already_permitted = true; } maximal_access = daccess; @@ -2887,7 +2989,7 @@ &may_flags); if (!test_tree_conn_flag(tcon, KSMBD_TREE_CONN_FLAG_WRITABLE)) { - if (open_flags & O_CREAT) { + if (open_flags & (O_CREAT | O_TRUNC)) { ksmbd_debug(SMB, "User does not have write permission\n"); rc = -EACCES; @@ -2897,7 +2999,8 @@ /*create file if not present */ if (!file_present) { - rc = smb2_creat(work, &path, name, open_flags, posix_mode, + rc = smb2_creat(work, &parent_path, &path, name, open_flags, + posix_mode, req->CreateOptions & FILE_DIRECTORY_FILE_LE); if (rc) { if (rc == -ENOENT) { @@ -2918,7 +3021,7 @@ rc = smb2_set_ea(&ea_buf->ea, le32_to_cpu(ea_buf->ccontext.DataLength), - &path); + &path, false); if (rc == -EOPNOTSUPP) rc = 0; else if (rc) @@ -2947,7 +3050,7 @@ } } - rc = ksmbd_query_inode_status(d_inode(path.dentry->d_parent)); + rc = ksmbd_query_inode_status(path.dentry->d_parent); if (rc == KSMBD_INODE_STATUS_PENDING_DELETE) { rc = -EBUSY; goto err_out; @@ -3061,7 +3164,8 @@ idmap, &path, pntsd, - pntsd_size); + pntsd_size, + false); kfree(pntsd); if (rc) pr_err("failed to store ntacl in xattr : %d\n", @@ -3084,11 +3188,6 @@ fp->attrib_only = !(req->DesiredAccess & ~(FILE_READ_ATTRIBUTES_LE | FILE_WRITE_ATTRIBUTES_LE | FILE_SYNCHRONIZE_LE)); - if (!S_ISDIR(file_inode(filp)->i_mode) && open_flags & O_TRUNC && - !fp->attrib_only && !stream_name) { - smb_break_all_oplock(work, fp); - need_truncate = 1; - } /* fp should be searchable through ksmbd_inode.m_fp_list * after daccess, saccess, attrib_only, and stream are @@ -3104,23 +3203,43 @@ goto err_out; } + if (file_present || created) + ksmbd_vfs_kern_path_unlock(&parent_path, &path); + + if (!S_ISDIR(file_inode(filp)->i_mode) && open_flags & O_TRUNC && + !fp->attrib_only && !stream_name) { + smb_break_all_oplock(work, fp); + need_truncate = 1; + } + + req_op_level = req->RequestedOplockLevel; + if (req_op_level == SMB2_OPLOCK_LEVEL_LEASE) + lc = parse_lease_state(req, S_ISDIR(file_inode(filp)->i_mode)); + share_ret = ksmbd_smb_check_shared_mode(fp->filp, fp); if (!test_share_config_flag(work->tcon->share_conf, KSMBD_SHARE_FLAG_OPLOCKS) || (req_op_level == SMB2_OPLOCK_LEVEL_LEASE && !(conn->vals->capabilities & SMB2_GLOBAL_CAP_LEASING))) { if (share_ret < 0 && !S_ISDIR(file_inode(fp->filp)->i_mode)) { rc = share_ret; - goto err_out; + goto err_out1; } } else { if (req_op_level == SMB2_OPLOCK_LEVEL_LEASE) { + /* + * Compare parent lease using parent key. If there is no + * a lease that has same parent key, Send lease break + * notification. + */ + smb_send_parent_lease_break_noti(fp, lc); + req_op_level = smb2_map_lease_to_oplock(lc->req_state); ksmbd_debug(SMB, "lease req for(%s) req oplock state 0x%x, lease state 0x%x\n", name, req_op_level, lc->req_state); rc = find_same_lease_key(sess, fp->f_ci, lc); if (rc) - goto err_out; + goto err_out1; } else if (open_flags == O_RDONLY && (req_op_level == SMB2_OPLOCK_LEVEL_BATCH || req_op_level == SMB2_OPLOCK_LEVEL_EXCLUSIVE)) @@ -3131,16 +3250,16 @@ le32_to_cpu(req->hdr.Id.SyncId.TreeId), lc, share_ret); if (rc < 0) - goto err_out; + goto err_out1; } if (req->CreateOptions & FILE_DELETE_ON_CLOSE_LE) ksmbd_fd_set_delete_on_close(fp, file_info); if (need_truncate) { - rc = smb2_create_truncate(&path); + rc = smb2_create_truncate(&fp->filp->f_path); if (rc) - goto err_out; + goto err_out1; } if (req->CreateContextsOffset) { @@ -3150,7 +3269,7 @@ SMB2_CREATE_ALLOCATION_SIZE, 4); if (IS_ERR(az_req)) { rc = PTR_ERR(az_req); - goto err_out; + goto err_out1; } else if (az_req) { loff_t alloc_size; int err; @@ -3159,7 +3278,7 @@ le32_to_cpu(az_req->ccontext.DataLength) < sizeof(struct create_alloc_size_req)) { rc = -EINVAL; - goto err_out; + goto err_out1; } alloc_size = le64_to_cpu(az_req->AllocationSize); ksmbd_debug(SMB, @@ -3177,7 +3296,7 @@ context = smb2_find_context_vals(req, SMB2_CREATE_QUERY_ON_DISK_ID, 4); if (IS_ERR(context)) { rc = PTR_ERR(context); - goto err_out; + goto err_out1; } else if (context) { ksmbd_debug(SMB, "get query on disk id context\n"); query_disk_id = 1; @@ -3186,7 +3305,7 @@ rc = ksmbd_vfs_getattr(&path, &stat); if (rc) - goto err_out; + goto err_out1; if (stat.result_mask & STATX_BTIME) fp->create_time = ksmbd_UnixTimeToNT(stat.btime); @@ -3229,7 +3348,7 @@ rsp->CreateContextsOffset = 0; rsp->CreateContextsLength = 0; - inc_rfc1001_len(work->response_buf, 88); /* StructureSize - 1*/ + iov_len = offsetof(struct smb2_create_rsp, Buffer); /* If lease is request send lease context response */ if (opinfo && opinfo->is_lease) { @@ -3244,8 +3363,7 @@ create_lease_buf(rsp->Buffer, opinfo->o_lease); le32_add_cpu(&rsp->CreateContextsLength, conn->vals->create_lease_size); - inc_rfc1001_len(work->response_buf, - conn->vals->create_lease_size); + iov_len += conn->vals->create_lease_size; next_ptr = &lease_ccontext->Next; next_off = conn->vals->create_lease_size; } @@ -3265,8 +3383,7 @@ le32_to_cpu(maximal_access)); le32_add_cpu(&rsp->CreateContextsLength, conn->vals->create_mxac_size); - inc_rfc1001_len(work->response_buf, - conn->vals->create_mxac_size); + iov_len += conn->vals->create_mxac_size; if (next_ptr) *next_ptr = cpu_to_le32(next_off); next_ptr = &mxac_ccontext->Next; @@ -3284,8 +3401,7 @@ stat.ino, tcon->id); le32_add_cpu(&rsp->CreateContextsLength, conn->vals->create_disk_id_size); - inc_rfc1001_len(work->response_buf, - conn->vals->create_disk_id_size); + iov_len += conn->vals->create_disk_id_size; if (next_ptr) *next_ptr = cpu_to_le32(next_off); next_ptr = &disk_id_ccontext->Next; @@ -3299,8 +3415,7 @@ fp); le32_add_cpu(&rsp->CreateContextsLength, conn->vals->create_posix_size); - inc_rfc1001_len(work->response_buf, - conn->vals->create_posix_size); + iov_len += conn->vals->create_posix_size; if (next_ptr) *next_ptr = cpu_to_le32(next_off); } @@ -3311,13 +3426,17 @@ } err_out: - if (file_present || created) { - inode_unlock(d_inode(path.dentry->d_parent)); - dput(path.dentry); - } - ksmbd_revert_fsids(work); + if (rc && (file_present || created)) + ksmbd_vfs_kern_path_unlock(&parent_path, &path); + err_out1: + ksmbd_revert_fsids(work); +err_out2: + if (!rc) { + ksmbd_update_fstate(&work->sess->file_table, fp, FP_INITED); + rc = ksmbd_iov_pin_rsp(work, (void *)rsp, iov_len); + } if (rc) { if (rc == -EINVAL) rsp->hdr.Status = STATUS_INVALID_PARAMETER; @@ -3714,11 +3833,16 @@ } ksmbd_kstat.kstat = &kstat; - if (priv->info_level != FILE_NAMES_INFORMATION) - ksmbd_vfs_fill_dentry_attrs(priv->work, + if (priv->info_level != FILE_NAMES_INFORMATION) { + rc = ksmbd_vfs_fill_dentry_attrs(priv->work, idmap, dent, &ksmbd_kstat); + if (rc) { + dput(dent); + continue; + } + } rc = smb2_populate_readdir_entry(priv->work->conn, priv->info_level, @@ -3961,7 +4085,7 @@ } srch_flag = req->Flags; - srch_ptr = smb_strndup_from_utf16(req->Buffer, + srch_ptr = smb_strndup_from_utf16((char *)req + le16_to_cpu(req->FileNameOffset), le16_to_cpu(req->FileNameLength), 1, conn->local_nls); if (IS_ERR(srch_ptr)) { @@ -4043,7 +4167,10 @@ rsp->OutputBufferOffset = cpu_to_le16(0); rsp->OutputBufferLength = cpu_to_le32(0); rsp->Buffer[0] = 0; - inc_rfc1001_len(work->response_buf, 9); + rc = ksmbd_iov_pin_rsp(work, (void *)rsp, + sizeof(struct smb2_query_directory_rsp)); + if (rc) + goto err_out; } else { no_buf_len: ((struct file_directory_info *) @@ -4055,7 +4182,11 @@ rsp->StructureSize = cpu_to_le16(9); rsp->OutputBufferOffset = cpu_to_le16(72); rsp->OutputBufferLength = cpu_to_le32(d_info.data_count); - inc_rfc1001_len(work->response_buf, 8 + d_info.data_count); + rc = ksmbd_iov_pin_rsp(work, (void *)rsp, + offsetof(struct smb2_query_directory_rsp, Buffer) + + d_info.data_count); + if (rc) + goto err_out; } kfree(srch_ptr); @@ -4102,22 +4233,14 @@ */ static int buffer_check_err(int reqOutputBufferLength, struct smb2_query_info_rsp *rsp, - void *rsp_org, int infoclass_size) + void *rsp_org) { if (reqOutputBufferLength < le32_to_cpu(rsp->OutputBufferLength)) { - if (reqOutputBufferLength < infoclass_size) { pr_err("Invalid Buffer Size Requested\n"); rsp->hdr.Status = STATUS_INFO_LENGTH_MISMATCH; *(__be32 *)rsp_org = cpu_to_be32(sizeof(struct smb2_hdr)); return -EINVAL; } - - ksmbd_debug(SMB, "Buffer Overflow\n"); - rsp->hdr.Status = STATUS_BUFFER_OVERFLOW; - *(__be32 *)rsp_org = cpu_to_be32(sizeof(struct smb2_hdr) + - reqOutputBufferLength); - rsp->OutputBufferLength = cpu_to_le32(reqOutputBufferLength); - } return 0; } @@ -4135,7 +4258,6 @@ sinfo->Directory = 0; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_standard_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_standard_info)); } static void get_internal_info_pipe(struct smb2_query_info_rsp *rsp, u64 num, @@ -4149,7 +4271,6 @@ file_info->IndexNumber = cpu_to_le64(num | (1ULL << 63)); rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_internal_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_internal_info)); } static int smb2_get_info_file_pipe(struct ksmbd_session *sess, @@ -4175,14 +4296,12 @@ case FILE_STANDARD_INFORMATION: get_standard_info_pipe(rsp, rsp_org); rc = buffer_check_err(le32_to_cpu(req->OutputBufferLength), - rsp, rsp_org, - FILE_STANDARD_INFORMATION_SIZE); + rsp, rsp_org); break; case FILE_INTERNAL_INFORMATION: get_internal_info_pipe(rsp, id, rsp_org); rc = buffer_check_err(le32_to_cpu(req->OutputBufferLength), - rsp, rsp_org, - FILE_INTERNAL_INFORMATION_SIZE); + rsp, rsp_org); break; default: ksmbd_debug(SMB, "smb2_info_file_pipe for %u not supported\n", @@ -4227,7 +4346,8 @@ sizeof(struct smb2_ea_info_req)) return -EINVAL; - ea_req = (struct smb2_ea_info_req *)req->Buffer; + ea_req = (struct smb2_ea_info_req *)((char *)req + + le16_to_cpu(req->InputBufferOffset)); } else { /* need to send all EAs, if no specific EA is requested*/ if (le32_to_cpu(req->Flags) & SL_RETURN_SINGLE_ENTRY) @@ -4288,7 +4408,7 @@ if (!strncmp(name, XATTR_USER_PREFIX, XATTR_USER_PREFIX_LEN)) name_len -= XATTR_USER_PREFIX_LEN; - ptr = (char *)(&eainfo->name + name_len + 1); + ptr = eainfo->name + name_len + 1; buf_free_len -= (offsetof(struct smb2_ea_info, name) + name_len + 1); /* bailout if xattr can't fit in buf_free_len */ @@ -4350,7 +4470,6 @@ if (rsp_data_cnt == 0) rsp->hdr.Status = STATUS_NO_EAS_ON_FILE; rsp->OutputBufferLength = cpu_to_le32(rsp_data_cnt); - inc_rfc1001_len(rsp_org, rsp_data_cnt); out: kvfree(xattr_list); return rc; @@ -4365,7 +4484,6 @@ file_info->AccessFlags = fp->daccess; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_access_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_access_info)); } static int get_file_basic_info(struct smb2_query_info_rsp *rsp, @@ -4374,6 +4492,7 @@ struct smb2_file_basic_info *basic_info; struct kstat stat; u64 time; + int ret; if (!(fp->daccess & FILE_READ_ATTRIBUTES_LE)) { pr_err("no right to read the attributes : 0x%x\n", @@ -4381,9 +4500,12 @@ return -EACCES; } + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; + basic_info = (struct smb2_file_basic_info *)rsp->Buffer; - generic_fillattr(file_mnt_idmap(fp->filp), file_inode(fp->filp), - &stat); basic_info->CreationTime = cpu_to_le64(fp->create_time); time = ksmbd_UnixTimeToNT(stat.atime); basic_info->LastAccessTime = cpu_to_le64(time); @@ -4395,33 +4517,34 @@ basic_info->Pad1 = 0; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_basic_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_basic_info)); return 0; } -static void get_file_standard_info(struct smb2_query_info_rsp *rsp, +static int get_file_standard_info(struct smb2_query_info_rsp *rsp, struct ksmbd_file *fp, void *rsp_org) { struct smb2_file_standard_info *sinfo; unsigned int delete_pending; - struct inode *inode; struct kstat stat; + int ret; - inode = file_inode(fp->filp); - generic_fillattr(file_mnt_idmap(fp->filp), inode, &stat); + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; sinfo = (struct smb2_file_standard_info *)rsp->Buffer; delete_pending = ksmbd_inode_pending_delete(fp); - sinfo->AllocationSize = cpu_to_le64(inode->i_blocks << 9); + sinfo->AllocationSize = cpu_to_le64(stat.blocks << 9); sinfo->EndOfFile = S_ISDIR(stat.mode) ? 0 : cpu_to_le64(stat.size); sinfo->NumberOfLinks = cpu_to_le32(get_nlink(&stat) - delete_pending); sinfo->DeletePending = delete_pending; sinfo->Directory = S_ISDIR(stat.mode) ? 1 : 0; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_standard_info)); - inc_rfc1001_len(rsp_org, - sizeof(struct smb2_file_standard_info)); + + return 0; } static void get_file_alignment_info(struct smb2_query_info_rsp *rsp, @@ -4433,8 +4556,6 @@ file_info->AlignmentRequirement = 0; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_alignment_info)); - inc_rfc1001_len(rsp_org, - sizeof(struct smb2_file_alignment_info)); } static int get_file_all_info(struct ksmbd_work *work, @@ -4445,11 +4566,11 @@ struct ksmbd_conn *conn = work->conn; struct smb2_file_all_info *file_info; unsigned int delete_pending; - struct inode *inode; struct kstat stat; int conv_len; char *filename; u64 time; + int ret; if (!(fp->daccess & FILE_READ_ATTRIBUTES_LE)) { ksmbd_debug(SMB, "no right to read the attributes : 0x%x\n", @@ -4461,8 +4582,10 @@ if (IS_ERR(filename)) return PTR_ERR(filename); - inode = file_inode(fp->filp); - generic_fillattr(file_mnt_idmap(fp->filp), inode, &stat); + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; ksmbd_debug(SMB, "filename = %s\n", filename); delete_pending = ksmbd_inode_pending_delete(fp); @@ -4477,8 +4600,7 @@ file_info->ChangeTime = cpu_to_le64(time); file_info->Attributes = fp->f_ci->m_fattr; file_info->Pad1 = 0; - file_info->AllocationSize = - cpu_to_le64(inode->i_blocks << 9); + file_info->AllocationSize = cpu_to_le64(stat.blocks << 9); file_info->EndOfFile = S_ISDIR(stat.mode) ? 0 : cpu_to_le64(stat.size); file_info->NumberOfLinks = cpu_to_le32(get_nlink(&stat) - delete_pending); @@ -4498,7 +4620,6 @@ rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_all_info) + conv_len - 1); kfree(filename); - inc_rfc1001_len(rsp_org, le32_to_cpu(rsp->OutputBufferLength)); return 0; } @@ -4521,10 +4642,9 @@ file_info->FileNameLength = cpu_to_le32(conv_len); rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_alt_name_info) + conv_len); - inc_rfc1001_len(rsp_org, le32_to_cpu(rsp->OutputBufferLength)); } -static void get_file_stream_info(struct ksmbd_work *work, +static int get_file_stream_info(struct ksmbd_work *work, struct smb2_query_info_rsp *rsp, struct ksmbd_file *fp, void *rsp_org) @@ -4538,9 +4658,13 @@ int nbytes = 0, streamlen, stream_name_len, next, idx = 0; int buf_free_len; struct smb2_query_info_req *req = ksmbd_req_buf_next(work); + int ret; + + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; - generic_fillattr(file_mnt_idmap(fp->filp), file_inode(fp->filp), - &stat); file_info = (struct smb2_file_stream_info *)rsp->Buffer; buf_free_len = @@ -4621,31 +4745,37 @@ kvfree(xattr_list); rsp->OutputBufferLength = cpu_to_le32(nbytes); - inc_rfc1001_len(rsp_org, nbytes); + + return 0; } -static void get_file_internal_info(struct smb2_query_info_rsp *rsp, +static int get_file_internal_info(struct smb2_query_info_rsp *rsp, struct ksmbd_file *fp, void *rsp_org) { struct smb2_file_internal_info *file_info; struct kstat stat; + int ret; + + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; - generic_fillattr(file_mnt_idmap(fp->filp), file_inode(fp->filp), - &stat); file_info = (struct smb2_file_internal_info *)rsp->Buffer; file_info->IndexNumber = cpu_to_le64(stat.ino); rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_internal_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_internal_info)); + + return 0; } static int get_file_network_open_info(struct smb2_query_info_rsp *rsp, struct ksmbd_file *fp, void *rsp_org) { struct smb2_file_ntwrk_info *file_info; - struct inode *inode; struct kstat stat; u64 time; + int ret; if (!(fp->daccess & FILE_READ_ATTRIBUTES_LE)) { pr_err("no right to read the attributes : 0x%x\n", @@ -4653,10 +4783,12 @@ return -EACCES; } - file_info = (struct smb2_file_ntwrk_info *)rsp->Buffer; + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; - inode = file_inode(fp->filp); - generic_fillattr(file_mnt_idmap(fp->filp), inode, &stat); + file_info = (struct smb2_file_ntwrk_info *)rsp->Buffer; file_info->CreationTime = cpu_to_le64(fp->create_time); time = ksmbd_UnixTimeToNT(stat.atime); @@ -4666,13 +4798,11 @@ time = ksmbd_UnixTimeToNT(stat.ctime); file_info->ChangeTime = cpu_to_le64(time); file_info->Attributes = fp->f_ci->m_fattr; - file_info->AllocationSize = - cpu_to_le64(inode->i_blocks << 9); + file_info->AllocationSize = cpu_to_le64(stat.blocks << 9); file_info->EndOfFile = S_ISDIR(stat.mode) ? 0 : cpu_to_le64(stat.size); file_info->Reserved = cpu_to_le32(0); rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_ntwrk_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_ntwrk_info)); return 0; } @@ -4684,7 +4814,6 @@ file_info->EASize = 0; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_ea_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_ea_info)); } static void get_file_position_info(struct smb2_query_info_rsp *rsp, @@ -4696,7 +4825,6 @@ file_info->CurrentByteOffset = cpu_to_le64(fp->filp->f_pos); rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_pos_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_pos_info)); } static void get_file_mode_info(struct smb2_query_info_rsp *rsp, @@ -4708,17 +4836,19 @@ file_info->Mode = fp->coption & FILE_MODE_INFO_MASK; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_mode_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_mode_info)); } -static void get_file_compression_info(struct smb2_query_info_rsp *rsp, +static int get_file_compression_info(struct smb2_query_info_rsp *rsp, struct ksmbd_file *fp, void *rsp_org) { struct smb2_file_comp_info *file_info; struct kstat stat; + int ret; - generic_fillattr(file_mnt_idmap(fp->filp), file_inode(fp->filp), - &stat); + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; file_info = (struct smb2_file_comp_info *)rsp->Buffer; file_info->CompressedFileSize = cpu_to_le64(stat.blocks << 9); @@ -4730,7 +4860,8 @@ rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_comp_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_comp_info)); + + return 0; } static int get_file_attribute_tag_info(struct smb2_query_info_rsp *rsp, @@ -4749,7 +4880,6 @@ file_info->ReparseTag = 0; rsp->OutputBufferLength = cpu_to_le32(sizeof(struct smb2_file_attr_tag_info)); - inc_rfc1001_len(rsp_org, sizeof(struct smb2_file_attr_tag_info)); return 0; } @@ -4761,24 +4891,31 @@ struct mnt_idmap *idmap = file_mnt_idmap(fp->filp); vfsuid_t vfsuid = i_uid_into_vfsuid(idmap, inode); vfsgid_t vfsgid = i_gid_into_vfsgid(idmap, inode); + struct kstat stat; u64 time; int out_buf_len = sizeof(struct smb311_posix_qinfo) + 32; + int ret; + + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) + return ret; file_info = (struct smb311_posix_qinfo *)rsp->Buffer; file_info->CreationTime = cpu_to_le64(fp->create_time); - time = ksmbd_UnixTimeToNT(inode->i_atime); + time = ksmbd_UnixTimeToNT(stat.atime); file_info->LastAccessTime = cpu_to_le64(time); - time = ksmbd_UnixTimeToNT(inode->i_mtime); + time = ksmbd_UnixTimeToNT(stat.mtime); file_info->LastWriteTime = cpu_to_le64(time); - time = ksmbd_UnixTimeToNT(inode->i_ctime); + time = ksmbd_UnixTimeToNT(stat.ctime); file_info->ChangeTime = cpu_to_le64(time); file_info->DosAttributes = fp->f_ci->m_fattr; - file_info->Inode = cpu_to_le64(inode->i_ino); - file_info->EndOfFile = cpu_to_le64(inode->i_size); - file_info->AllocationSize = cpu_to_le64(inode->i_blocks << 9); - file_info->HardLinks = cpu_to_le32(inode->i_nlink); - file_info->Mode = cpu_to_le32(inode->i_mode & 0777); - file_info->DeviceId = cpu_to_le32(inode->i_rdev); + file_info->Inode = cpu_to_le64(stat.ino); + file_info->EndOfFile = cpu_to_le64(stat.size); + file_info->AllocationSize = cpu_to_le64(stat.blocks << 9); + file_info->HardLinks = cpu_to_le32(stat.nlink); + file_info->Mode = cpu_to_le32(stat.mode & 0777); + file_info->DeviceId = cpu_to_le32(stat.rdev); /* * Sids(32) contain two sids(Domain sid(16), UNIX group sid(16)). @@ -4791,8 +4928,8 @@ SIDUNIX_GROUP, (struct smb_sid *)&file_info->Sids[16]); rsp->OutputBufferLength = cpu_to_le32(out_buf_len); - inc_rfc1001_len(rsp_org, out_buf_len); - return out_buf_len; + + return 0; } static int smb2_get_info_file(struct ksmbd_work *work, @@ -4802,7 +4939,6 @@ struct ksmbd_file *fp; int fileinfoclass = 0; int rc = 0; - int file_infoclass_size; unsigned int id = KSMBD_NO_FID, pid = KSMBD_NO_FID; if (test_share_config_flag(work->tcon->share_conf, @@ -4835,85 +4971,69 @@ switch (fileinfoclass) { case FILE_ACCESS_INFORMATION: get_file_access_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_ACCESS_INFORMATION_SIZE; break; case FILE_BASIC_INFORMATION: rc = get_file_basic_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_BASIC_INFORMATION_SIZE; break; case FILE_STANDARD_INFORMATION: - get_file_standard_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_STANDARD_INFORMATION_SIZE; + rc = get_file_standard_info(rsp, fp, work->response_buf); break; case FILE_ALIGNMENT_INFORMATION: get_file_alignment_info(rsp, work->response_buf); - file_infoclass_size = FILE_ALIGNMENT_INFORMATION_SIZE; break; case FILE_ALL_INFORMATION: rc = get_file_all_info(work, rsp, fp, work->response_buf); - file_infoclass_size = FILE_ALL_INFORMATION_SIZE; break; case FILE_ALTERNATE_NAME_INFORMATION: get_file_alternate_info(work, rsp, fp, work->response_buf); - file_infoclass_size = FILE_ALTERNATE_NAME_INFORMATION_SIZE; break; case FILE_STREAM_INFORMATION: - get_file_stream_info(work, rsp, fp, work->response_buf); - file_infoclass_size = FILE_STREAM_INFORMATION_SIZE; + rc = get_file_stream_info(work, rsp, fp, work->response_buf); break; case FILE_INTERNAL_INFORMATION: - get_file_internal_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_INTERNAL_INFORMATION_SIZE; + rc = get_file_internal_info(rsp, fp, work->response_buf); break; case FILE_NETWORK_OPEN_INFORMATION: rc = get_file_network_open_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_NETWORK_OPEN_INFORMATION_SIZE; break; case FILE_EA_INFORMATION: get_file_ea_info(rsp, work->response_buf); - file_infoclass_size = FILE_EA_INFORMATION_SIZE; break; case FILE_FULL_EA_INFORMATION: rc = smb2_get_ea(work, fp, req, rsp, work->response_buf); - file_infoclass_size = FILE_FULL_EA_INFORMATION_SIZE; break; case FILE_POSITION_INFORMATION: get_file_position_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_POSITION_INFORMATION_SIZE; break; case FILE_MODE_INFORMATION: get_file_mode_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_MODE_INFORMATION_SIZE; break; case FILE_COMPRESSION_INFORMATION: - get_file_compression_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_COMPRESSION_INFORMATION_SIZE; + rc = get_file_compression_info(rsp, fp, work->response_buf); break; case FILE_ATTRIBUTE_TAG_INFORMATION: rc = get_file_attribute_tag_info(rsp, fp, work->response_buf); - file_infoclass_size = FILE_ATTRIBUTE_TAG_INFORMATION_SIZE; break; case SMB_FIND_FILE_POSIX_INFO: if (!work->tcon->posix_extensions) { pr_err("client doesn't negotiate with SMB3.1.1 POSIX Extensions\n"); rc = -EOPNOTSUPP; } else { - file_infoclass_size = find_file_posix_info(rsp, fp, - work->response_buf); + rc = find_file_posix_info(rsp, fp, work->response_buf); } break; default: @@ -4923,8 +5043,7 @@ } if (!rc) rc = buffer_check_err(le32_to_cpu(req->OutputBufferLength), - rsp, work->response_buf, - file_infoclass_size); + rsp, work->response_buf); ksmbd_fd_put(work, fp); return rc; } @@ -4940,7 +5059,6 @@ struct kstatfs stfs; struct path path; int rc = 0, len; - int fs_infoclass_size = 0; if (!share->path) return -EIO; @@ -4970,8 +5088,6 @@ info->DeviceType = cpu_to_le32(stfs.f_type); info->DeviceCharacteristics = cpu_to_le32(0x00000020); rsp->OutputBufferLength = cpu_to_le32(8); - inc_rfc1001_len(work->response_buf, 8); - fs_infoclass_size = FS_DEVICE_INFORMATION_SIZE; break; } case FS_ATTRIBUTE_INFORMATION: @@ -5000,8 +5116,6 @@ info->FileSystemNameLen = cpu_to_le32(len); sz = sizeof(struct filesystem_attribute_info) - 2 + len; rsp->OutputBufferLength = cpu_to_le32(sz); - inc_rfc1001_len(work->response_buf, sz); - fs_infoclass_size = FS_ATTRIBUTE_INFORMATION_SIZE; break; } case FS_VOLUME_INFORMATION: @@ -5028,8 +5142,6 @@ info->Reserved = 0; sz = sizeof(struct filesystem_vol_info) - 2 + len; rsp->OutputBufferLength = cpu_to_le32(sz); - inc_rfc1001_len(work->response_buf, sz); - fs_infoclass_size = FS_VOLUME_INFORMATION_SIZE; break; } case FS_SIZE_INFORMATION: @@ -5042,8 +5154,6 @@ info->SectorsPerAllocationUnit = cpu_to_le32(1); info->BytesPerSector = cpu_to_le32(stfs.f_bsize); rsp->OutputBufferLength = cpu_to_le32(24); - inc_rfc1001_len(work->response_buf, 24); - fs_infoclass_size = FS_SIZE_INFORMATION_SIZE; break; } case FS_FULL_SIZE_INFORMATION: @@ -5059,8 +5169,6 @@ info->SectorsPerAllocationUnit = cpu_to_le32(1); info->BytesPerSector = cpu_to_le32(stfs.f_bsize); rsp->OutputBufferLength = cpu_to_le32(32); - inc_rfc1001_len(work->response_buf, 32); - fs_infoclass_size = FS_FULL_SIZE_INFORMATION_SIZE; break; } case FS_OBJECT_ID_INFORMATION: @@ -5080,8 +5188,6 @@ info->extended_info.rel_date = 0; memcpy(info->extended_info.version_string, "1.1.0", strlen("1.1.0")); rsp->OutputBufferLength = cpu_to_le32(64); - inc_rfc1001_len(work->response_buf, 64); - fs_infoclass_size = FS_OBJECT_ID_INFORMATION_SIZE; break; } case FS_SECTOR_SIZE_INFORMATION: @@ -5103,8 +5209,6 @@ info->ByteOffsetForSectorAlignment = 0; info->ByteOffsetForPartitionAlignment = 0; rsp->OutputBufferLength = cpu_to_le32(28); - inc_rfc1001_len(work->response_buf, 28); - fs_infoclass_size = FS_SECTOR_SIZE_INFORMATION_SIZE; break; } case FS_CONTROL_INFORMATION: @@ -5125,8 +5229,6 @@ info->DefaultQuotaLimit = cpu_to_le64(SMB2_NO_FID); info->Padding = 0; rsp->OutputBufferLength = cpu_to_le32(48); - inc_rfc1001_len(work->response_buf, 48); - fs_infoclass_size = FS_CONTROL_INFORMATION_SIZE; break; } case FS_POSIX_INFORMATION: @@ -5146,8 +5248,6 @@ info->TotalFileNodes = cpu_to_le64(stfs.f_files); info->FreeFileNodes = cpu_to_le64(stfs.f_ffree); rsp->OutputBufferLength = cpu_to_le32(56); - inc_rfc1001_len(work->response_buf, 56); - fs_infoclass_size = FS_POSIX_INFORMATION_SIZE; } break; } @@ -5156,8 +5256,7 @@ return -EOPNOTSUPP; } rc = buffer_check_err(le32_to_cpu(req->OutputBufferLength), - rsp, work->response_buf, - fs_infoclass_size); + rsp, work->response_buf); path_put(&path); return rc; } @@ -5191,7 +5290,6 @@ secdesclen = sizeof(struct smb_ntsd); rsp->OutputBufferLength = cpu_to_le32(secdesclen); - inc_rfc1001_len(work->response_buf, secdesclen); return 0; } @@ -5236,7 +5334,6 @@ return rc; rsp->OutputBufferLength = cpu_to_le32(secdesclen); - inc_rfc1001_len(work->response_buf, secdesclen); return 0; } @@ -5275,6 +5372,14 @@ rc = -EOPNOTSUPP; } + if (!rc) { + rsp->StructureSize = cpu_to_le16(9); + rsp->OutputBufferOffset = cpu_to_le16(72); + rc = ksmbd_iov_pin_rsp(work, (void *)rsp, + offsetof(struct smb2_query_info_rsp, Buffer) + + le32_to_cpu(rsp->OutputBufferLength)); + } + if (rc < 0) { if (rc == -EACCES) rsp->hdr.Status = STATUS_ACCESS_DENIED; @@ -5282,6 +5387,8 @@ rsp->hdr.Status = STATUS_FILE_CLOSED; else if (rc == -EIO) rsp->hdr.Status = STATUS_UNEXPECTED_IO_ERROR; + else if (rc == -ENOMEM) + rsp->hdr.Status = STATUS_INSUFFICIENT_RESOURCES; else if (rc == -EOPNOTSUPP || rsp->hdr.Status == 0) rsp->hdr.Status = STATUS_INVALID_INFO_CLASS; smb2_set_err_rsp(work); @@ -5290,9 +5397,6 @@ rc); return rc; } - rsp->StructureSize = cpu_to_le16(9); - rsp->OutputBufferOffset = cpu_to_le16(72); - inc_rfc1001_len(work->response_buf, 8); return 0; } @@ -5305,8 +5409,10 @@ static noinline int smb2_close_pipe(struct ksmbd_work *work) { u64 id; - struct smb2_close_req *req = smb2_get_msg(work->request_buf); - struct smb2_close_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_close_req *req; + struct smb2_close_rsp *rsp; + + WORK_BUFFERS(work, req, rsp); id = req->VolatileFileId; ksmbd_session_rpc_close(work->sess, id); @@ -5321,8 +5427,9 @@ rsp->AllocationSize = 0; rsp->EndOfFile = 0; rsp->Attributes = 0; - inc_rfc1001_len(work->response_buf, 60); - return 0; + + return ksmbd_iov_pin_rsp(work, (void *)rsp, + sizeof(struct smb2_close_rsp)); } /** @@ -5339,7 +5446,6 @@ struct smb2_close_rsp *rsp; struct ksmbd_conn *conn = work->conn; struct ksmbd_file *fp; - struct inode *inode; u64 time; int err = 0; @@ -5394,24 +5500,33 @@ rsp->Reserved = 0; if (req->Flags == SMB2_CLOSE_FLAG_POSTQUERY_ATTRIB) { + struct kstat stat; + int ret; + fp = ksmbd_lookup_fd_fast(work, volatile_id); if (!fp) { err = -ENOENT; goto out; } - inode = file_inode(fp->filp); + ret = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (ret) { + ksmbd_fd_put(work, fp); + goto out; + } + rsp->Flags = SMB2_CLOSE_FLAG_POSTQUERY_ATTRIB; - rsp->AllocationSize = S_ISDIR(inode->i_mode) ? 0 : - cpu_to_le64(inode->i_blocks << 9); - rsp->EndOfFile = cpu_to_le64(inode->i_size); + rsp->AllocationSize = S_ISDIR(stat.mode) ? 0 : + cpu_to_le64(stat.blocks << 9); + rsp->EndOfFile = cpu_to_le64(stat.size); rsp->Attributes = fp->f_ci->m_fattr; rsp->CreationTime = cpu_to_le64(fp->create_time); - time = ksmbd_UnixTimeToNT(inode->i_atime); + time = ksmbd_UnixTimeToNT(stat.atime); rsp->LastAccessTime = cpu_to_le64(time); - time = ksmbd_UnixTimeToNT(inode->i_mtime); + time = ksmbd_UnixTimeToNT(stat.mtime); rsp->LastWriteTime = cpu_to_le64(time); - time = ksmbd_UnixTimeToNT(inode->i_ctime); + time = ksmbd_UnixTimeToNT(stat.ctime); rsp->ChangeTime = cpu_to_le64(time); ksmbd_fd_put(work, fp); } else { @@ -5427,15 +5542,17 @@ err = ksmbd_close_fd(work, volatile_id); out: + if (!err) + err = ksmbd_iov_pin_rsp(work, (void *)rsp, + sizeof(struct smb2_close_rsp)); + if (err) { if (rsp->hdr.Status == 0) rsp->hdr.Status = STATUS_FILE_CLOSED; smb2_set_err_rsp(work); - } else { - inc_rfc1001_len(work->response_buf, 60); } - return 0; + return err; } /** @@ -5448,10 +5565,12 @@ { struct smb2_echo_rsp *rsp = smb2_get_msg(work->response_buf); + if (work->next_smb2_rcv_hdr_off) + rsp = ksmbd_resp_buf_next(work); + rsp->StructureSize = cpu_to_le16(4); rsp->Reserved = 0; - inc_rfc1001_len(work->response_buf, 4); - return 0; + return ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_echo_rsp)); } static int smb2_rename(struct ksmbd_work *work, @@ -5497,7 +5616,7 @@ rc = ksmbd_vfs_setxattr(file_mnt_idmap(fp->filp), &fp->filp->f_path, xattr_stream_name, - NULL, 0, 0); + NULL, 0, 0, true); if (rc < 0) { pr_err("failed to store stream name in xattr: %d\n", rc); @@ -5519,6 +5638,8 @@ flags = RENAME_NOREPLACE; rc = ksmbd_vfs_rename(work, &fp->filp->f_path, new_name, flags); + if (!rc) + smb_break_all_levII_oplock(work, fp, 0); out: kfree(new_name); return rc; @@ -5531,7 +5652,7 @@ struct nls_table *local_nls) { char *link_name = NULL, *target_name = NULL, *pathname = NULL; - struct path path; + struct path path, parent_path; bool file_present = false; int rc; @@ -5561,7 +5682,7 @@ ksmbd_debug(SMB, "target name is %s\n", target_name); rc = ksmbd_vfs_kern_path_locked(work, link_name, LOOKUP_NO_SYMLINKS, - &path, 0); + &parent_path, &path, 0); if (rc) { if (rc != -ENOENT) goto out; @@ -5590,10 +5711,9 @@ if (rc) rc = -EINVAL; out: - if (file_present) { - inode_unlock(d_inode(path.dentry->d_parent)); - path_put(&path); - } + if (file_present) + ksmbd_vfs_kern_path_unlock(&parent_path, &path); + if (!IS_ERR(link_name)) kfree(link_name); kfree(pathname); @@ -5660,7 +5780,8 @@ da.flags = XATTR_DOSINFO_ATTRIB | XATTR_DOSINFO_CREATE_TIME | XATTR_DOSINFO_ITIME; - rc = ksmbd_vfs_set_dos_attrib_xattr(idmap, &filp->f_path, &da); + rc = ksmbd_vfs_set_dos_attrib_xattr(idmap, &filp->f_path, &da, + true); if (rc) ksmbd_debug(SMB, "failed to restore file attribute in EA\n"); @@ -5695,15 +5816,21 @@ loff_t alloc_blks; struct inode *inode; + struct kstat stat; int rc; if (!(fp->daccess & FILE_WRITE_DATA_LE)) return -EACCES; + rc = vfs_getattr(&fp->filp->f_path, &stat, STATX_BASIC_STATS, + AT_STATX_SYNC_AS_STAT); + if (rc) + return rc; + alloc_blks = (le64_to_cpu(file_alloc_info->AllocationSize) + 511) >> 9; inode = file_inode(fp->filp); - if (alloc_blks > inode->i_blocks) { + if (alloc_blks > stat.blocks) { smb_break_all_levII_oplock(work, fp, 1); rc = vfs_fallocate(fp->filp, FALLOC_FL_KEEP_SIZE, 0, alloc_blks * 512); @@ -5711,7 +5838,7 @@ pr_err("vfs_fallocate is failed : %d\n", rc); return rc; } - } else if (alloc_blks < inode->i_blocks) { + } else if (alloc_blks < stat.blocks) { loff_t size; /* @@ -5866,6 +5993,7 @@ struct ksmbd_share_config *share) { unsigned int buf_len = le32_to_cpu(req->BufferLength); + char *buffer = (char *)req + le16_to_cpu(req->BufferOffset); switch (req->FileInfoClass) { case FILE_BASIC_INFORMATION: @@ -5873,7 +6001,7 @@ if (buf_len < sizeof(struct smb2_file_basic_info)) return -EINVAL; - return set_file_basic_info(fp, (struct smb2_file_basic_info *)req->Buffer, share); + return set_file_basic_info(fp, (struct smb2_file_basic_info *)buffer, share); } case FILE_ALLOCATION_INFORMATION: { @@ -5881,7 +6009,7 @@ return -EINVAL; return set_file_allocation_info(work, fp, - (struct smb2_file_alloc_info *)req->Buffer); + (struct smb2_file_alloc_info *)buffer); } case FILE_END_OF_FILE_INFORMATION: { @@ -5889,21 +6017,15 @@ return -EINVAL; return set_end_of_file_info(work, fp, - (struct smb2_file_eof_info *)req->Buffer); + (struct smb2_file_eof_info *)buffer); } case FILE_RENAME_INFORMATION: { - if (!test_tree_conn_flag(work->tcon, KSMBD_TREE_CONN_FLAG_WRITABLE)) { - ksmbd_debug(SMB, - "User does not have write permission\n"); - return -EACCES; - } - if (buf_len < sizeof(struct smb2_file_rename_info)) return -EINVAL; return set_rename_info(work, fp, - (struct smb2_file_rename_info *)req->Buffer, + (struct smb2_file_rename_info *)buffer, buf_len); } case FILE_LINK_INFORMATION: @@ -5912,23 +6034,17 @@ return -EINVAL; return smb2_create_link(work, work->tcon->share_conf, - (struct smb2_file_link_info *)req->Buffer, + (struct smb2_file_link_info *)buffer, buf_len, fp->filp, work->conn->local_nls); } case FILE_DISPOSITION_INFORMATION: { - if (!test_tree_conn_flag(work->tcon, KSMBD_TREE_CONN_FLAG_WRITABLE)) { - ksmbd_debug(SMB, - "User does not have write permission\n"); - return -EACCES; - } - if (buf_len < sizeof(struct smb2_file_disposition_info)) return -EINVAL; return set_file_disposition_info(fp, - (struct smb2_file_disposition_info *)req->Buffer); + (struct smb2_file_disposition_info *)buffer); } case FILE_FULL_EA_INFORMATION: { @@ -5941,22 +6057,22 @@ if (buf_len < sizeof(struct smb2_ea_info)) return -EINVAL; - return smb2_set_ea((struct smb2_ea_info *)req->Buffer, - buf_len, &fp->filp->f_path); + return smb2_set_ea((struct smb2_ea_info *)buffer, + buf_len, &fp->filp->f_path, true); } case FILE_POSITION_INFORMATION: { if (buf_len < sizeof(struct smb2_file_pos_info)) return -EINVAL; - return set_file_position_info(fp, (struct smb2_file_pos_info *)req->Buffer); + return set_file_position_info(fp, (struct smb2_file_pos_info *)buffer); } case FILE_MODE_INFORMATION: { if (buf_len < sizeof(struct smb2_file_mode_info)) return -EINVAL; - return set_file_mode_info(fp, (struct smb2_file_mode_info *)req->Buffer); + return set_file_mode_info(fp, (struct smb2_file_mode_info *)buffer); } } @@ -5972,7 +6088,7 @@ fp->saccess |= FILE_SHARE_DELETE_LE; return set_info_sec(fp->conn, fp->tcon, &fp->filp->f_path, pntsd, - buf_len, false); + buf_len, false, true); } /** @@ -5985,7 +6101,7 @@ { struct smb2_set_info_req *req; struct smb2_set_info_rsp *rsp; - struct ksmbd_file *fp; + struct ksmbd_file *fp = NULL; int rc = 0; unsigned int id = KSMBD_NO_FID, pid = KSMBD_NO_FID; @@ -6005,6 +6121,13 @@ rsp = smb2_get_msg(work->response_buf); } + if (!test_tree_conn_flag(work->tcon, KSMBD_TREE_CONN_FLAG_WRITABLE)) { + ksmbd_debug(SMB, "User does not have write permission\n"); + pr_err("User does not have write permission\n"); + rc = -EACCES; + goto err_out; + } + if (!has_file_id(id)) { id = req->VolatileFileId; pid = req->PersistentFileId; @@ -6030,7 +6153,7 @@ } rc = smb2_set_info_sec(fp, le32_to_cpu(req->AdditionalInformation), - req->Buffer, + (char *)req + le16_to_cpu(req->BufferOffset), le32_to_cpu(req->BufferLength)); ksmbd_revert_fsids(work); break; @@ -6042,7 +6165,10 @@ goto err_out; rsp->StructureSize = cpu_to_le16(2); - inc_rfc1001_len(work->response_buf, 2); + rc = ksmbd_iov_pin_rsp(work, (void *)rsp, + sizeof(struct smb2_set_info_rsp)); + if (rc) + goto err_out; ksmbd_fd_put(work, fp); return 0; @@ -6082,33 +6208,45 @@ int nbytes = 0, err; u64 id; struct ksmbd_rpc_command *rpc_resp; - struct smb2_read_req *req = smb2_get_msg(work->request_buf); - struct smb2_read_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_read_req *req; + struct smb2_read_rsp *rsp; + + WORK_BUFFERS(work, req, rsp); id = req->VolatileFileId; - inc_rfc1001_len(work->response_buf, 16); rpc_resp = ksmbd_rpc_read(work->sess, id); if (rpc_resp) { + void *aux_payload_buf; + if (rpc_resp->flags != KSMBD_RPC_OK) { err = -EINVAL; goto out; } - work->aux_payload_buf = - kvmalloc(rpc_resp->payload_sz, GFP_KERNEL | __GFP_ZERO); - if (!work->aux_payload_buf) { + aux_payload_buf = + kvmalloc(rpc_resp->payload_sz, GFP_KERNEL); + if (!aux_payload_buf) { err = -ENOMEM; goto out; } - memcpy(work->aux_payload_buf, rpc_resp->payload, - rpc_resp->payload_sz); + memcpy(aux_payload_buf, rpc_resp->payload, rpc_resp->payload_sz); nbytes = rpc_resp->payload_sz; - work->resp_hdr_sz = get_rfc1002_len(work->response_buf) + 4; - work->aux_payload_sz = nbytes; + err = ksmbd_iov_pin_rsp_read(work, (void *)rsp, + offsetof(struct smb2_read_rsp, Buffer), + aux_payload_buf, nbytes); + if (err) { + kvfree(aux_payload_buf); + goto out; + } kvfree(rpc_resp); + } else { + err = ksmbd_iov_pin_rsp(work, (void *)rsp, + offsetof(struct smb2_read_rsp, Buffer)); + if (err) + goto out; } rsp->StructureSize = cpu_to_le16(17); @@ -6117,7 +6255,6 @@ rsp->DataLength = cpu_to_le32(nbytes); rsp->DataRemaining = 0; rsp->Flags = 0; - inc_rfc1001_len(work->response_buf, nbytes); return 0; out: @@ -6191,8 +6328,8 @@ int err = 0; bool is_rdma_channel = false; unsigned int max_read_size = conn->vals->max_read_size; - - WORK_BUFFERS(work, req, rsp); + unsigned int id = KSMBD_NO_FID, pid = KSMBD_NO_FID; + void *aux_payload_buf; if (test_share_config_flag(work->tcon->share_conf, KSMBD_SHARE_FLAG_PIPE)) { @@ -6200,6 +6337,25 @@ return smb2_read_pipe(work); } + if (work->next_smb2_rcv_hdr_off) { + req = ksmbd_req_buf_next(work); + rsp = ksmbd_resp_buf_next(work); + if (!has_file_id(req->VolatileFileId)) { + ksmbd_debug(SMB, "Compound request set FID = %llu\n", + work->compound_fid); + id = work->compound_fid; + pid = work->compound_pfid; + } + } else { + req = smb2_get_msg(work->request_buf); + rsp = smb2_get_msg(work->response_buf); + } + + if (!has_file_id(id)) { + id = req->VolatileFileId; + pid = req->PersistentFileId; + } + if (req->Channel == SMB2_CHANNEL_RDMA_V1_INVALIDATE || req->Channel == SMB2_CHANNEL_RDMA_V1) { is_rdma_channel = true; @@ -6222,7 +6378,7 @@ goto out; } - fp = ksmbd_lookup_fd_slow(work, req->VolatileFileId, req->PersistentFileId); + fp = ksmbd_lookup_fd_slow(work, id, pid); if (!fp) { err = -ENOENT; goto out; @@ -6248,21 +6404,20 @@ ksmbd_debug(SMB, "filename %pD, offset %lld, len %zu\n", fp->filp, offset, length); - work->aux_payload_buf = kvmalloc(length, GFP_KERNEL | __GFP_ZERO); - if (!work->aux_payload_buf) { + aux_payload_buf = kvzalloc(length, GFP_KERNEL); + if (!aux_payload_buf) { err = -ENOMEM; goto out; } - nbytes = ksmbd_vfs_read(work, fp, length, &offset); + nbytes = ksmbd_vfs_read(work, fp, length, &offset, aux_payload_buf); if (nbytes < 0) { err = nbytes; goto out; } if ((nbytes == 0 && length != 0) || nbytes < mincount) { - kvfree(work->aux_payload_buf); - work->aux_payload_buf = NULL; + kvfree(aux_payload_buf); rsp->hdr.Status = STATUS_END_OF_FILE; smb2_set_err_rsp(work); ksmbd_fd_put(work, fp); @@ -6275,11 +6430,10 @@ if (is_rdma_channel == true) { /* write data to the client using rdma channel */ remain_bytes = smb2_read_rdma_channel(work, req, - work->aux_payload_buf, + aux_payload_buf, nbytes); - kvfree(work->aux_payload_buf); - work->aux_payload_buf = NULL; - + kvfree(aux_payload_buf); + aux_payload_buf = NULL; nbytes = 0; if (remain_bytes < 0) { err = (int)remain_bytes; @@ -6293,10 +6447,13 @@ rsp->DataLength = cpu_to_le32(nbytes); rsp->DataRemaining = cpu_to_le32(remain_bytes); rsp->Flags = 0; - inc_rfc1001_len(work->response_buf, 16); - work->resp_hdr_sz = get_rfc1002_len(work->response_buf) + 4; - work->aux_payload_sz = nbytes; - inc_rfc1001_len(work->response_buf, nbytes); + err = ksmbd_iov_pin_rsp_read(work, (void *)rsp, + offsetof(struct smb2_read_rsp, Buffer), + aux_payload_buf, nbytes); + if (err) { + kvfree(aux_payload_buf); + goto out; + } ksmbd_fd_put(work, fp); return 0; @@ -6331,14 +6488,16 @@ */ static noinline int smb2_write_pipe(struct ksmbd_work *work) { - struct smb2_write_req *req = smb2_get_msg(work->request_buf); - struct smb2_write_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_write_req *req; + struct smb2_write_rsp *rsp; struct ksmbd_rpc_command *rpc_resp; u64 id = 0; int err = 0, ret = 0; char *data_buf; size_t length; + WORK_BUFFERS(work, req, rsp); + length = le32_to_cpu(req->Length); id = req->VolatileFileId; @@ -6377,8 +6536,8 @@ rsp->DataLength = cpu_to_le32(length); rsp->DataRemaining = 0; rsp->Reserved2 = 0; - inc_rfc1001_len(work->response_buf, 16); - return 0; + err = ksmbd_iov_pin_rsp(work, (void *)rsp, + offsetof(struct smb2_write_rsp, Buffer)); out: if (err) { rsp->hdr.Status = STATUS_INVALID_HANDLE; @@ -6397,7 +6556,7 @@ int ret; ssize_t nbytes; - data_buf = kvmalloc(length, GFP_KERNEL | __GFP_ZERO); + data_buf = kvzalloc(length, GFP_KERNEL); if (!data_buf) return -ENOMEM; @@ -6534,7 +6693,9 @@ rsp->DataLength = cpu_to_le32(nbytes); rsp->DataRemaining = 0; rsp->Reserved2 = 0; - inc_rfc1001_len(work->response_buf, 16); + err = ksmbd_iov_pin_rsp(work, rsp, offsetof(struct smb2_write_rsp, Buffer)); + if (err) + goto out; ksmbd_fd_put(work, fp); return 0; @@ -6581,15 +6742,11 @@ rsp->StructureSize = cpu_to_le16(4); rsp->Reserved = 0; - inc_rfc1001_len(work->response_buf, 4); - return 0; + return ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_flush_rsp)); out: - if (err) { rsp->hdr.Status = STATUS_INVALID_HANDLE; smb2_set_err_rsp(work); - } - return err; } @@ -6607,6 +6764,9 @@ struct ksmbd_work *iter; struct list_head *command_list; + if (work->next_smb2_rcv_hdr_off) + hdr = ksmbd_resp_buf_next(work); + ksmbd_debug(SMB, "smb2 cancel called on mid %llu, async flags 0x%x\n", hdr->MessageId, hdr->Flags); @@ -6766,8 +6926,8 @@ */ int smb2_lock(struct ksmbd_work *work) { - struct smb2_lock_req *req = smb2_get_msg(work->request_buf); - struct smb2_lock_rsp *rsp = smb2_get_msg(work->response_buf); + struct smb2_lock_req *req; + struct smb2_lock_rsp *rsp; struct smb2_lock_element *lock_ele; struct ksmbd_file *fp = NULL; struct file_lock *flock = NULL; @@ -6784,6 +6944,8 @@ LIST_HEAD(rollback_list); int prior_lock = 0; + WORK_BUFFERS(work, req, rsp); + ksmbd_debug(SMB, "Received lock request\n"); fp = ksmbd_lookup_fd_slow(work, req->VolatileFileId, req->PersistentFileId); if (!fp) { @@ -6989,10 +7151,6 @@ ksmbd_debug(SMB, "would have to wait for getting lock\n"); - spin_lock(&work->conn->llist_lock); - list_add_tail(&smb_lock->clist, - &work->conn->lock_list); - spin_unlock(&work->conn->llist_lock); list_add(&smb_lock->llist, &rollback_list); argv = kmalloc(sizeof(void *), GFP_KERNEL); @@ -7006,6 +7164,7 @@ smb2_remove_blocked_lock, argv); if (rc) { + kfree(argv); err = -ENOMEM; goto out; } @@ -7023,9 +7182,6 @@ if (work->state != KSMBD_WORK_ACTIVE) { list_del(&smb_lock->llist); - spin_lock(&work->conn->llist_lock); - list_del(&smb_lock->clist); - spin_unlock(&work->conn->llist_lock); locks_free_lock(flock); if (work->state == KSMBD_WORK_CANCELLED) { @@ -7038,8 +7194,6 @@ goto out; } - init_smb2_rsp_hdr(work); - smb2_set_err_rsp(work); rsp->hdr.Status = STATUS_RANGE_NOT_LOCKED; kfree(smb_lock); @@ -7047,19 +7201,16 @@ } list_del(&smb_lock->llist); - spin_lock(&work->conn->llist_lock); - list_del(&smb_lock->clist); - spin_unlock(&work->conn->llist_lock); release_async_work(work); goto retry; } else if (!rc) { + list_add(&smb_lock->llist, &rollback_list); spin_lock(&work->conn->llist_lock); list_add_tail(&smb_lock->clist, &work->conn->lock_list); list_add_tail(&smb_lock->flist, &fp->lock_list); spin_unlock(&work->conn->llist_lock); - list_add(&smb_lock->llist, &rollback_list); ksmbd_debug(SMB, "successful in taking lock\n"); } else { goto out; @@ -7074,7 +7225,10 @@ ksmbd_debug(SMB, "successful in taking lock\n"); rsp->hdr.Status = STATUS_SUCCESS; rsp->Reserved = 0; - inc_rfc1001_len(work->response_buf, 4); + err = ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_lock_rsp)); + if (err) + goto out; + ksmbd_fd_put(work, fp); return 0; @@ -7445,7 +7599,7 @@ struct smb2_ioctl_rsp *rsp) { struct ksmbd_rpc_command *rpc_resp; - char *data_buf = (char *)&req->Buffer[0]; + char *data_buf = (char *)req + le32_to_cpu(req->InputOffset); int nbytes = 0; rpc_resp = ksmbd_rpc_ioctl(work->sess, id, data_buf, @@ -7515,7 +7669,8 @@ da.attr = le32_to_cpu(fp->f_ci->m_fattr); ret = ksmbd_vfs_set_dos_attrib_xattr(idmap, - &fp->filp->f_path, &da); + &fp->filp->f_path, + &da, true); if (ret) fp->f_ci->m_fattr = old_fattr; } @@ -7557,6 +7712,7 @@ u64 id = KSMBD_NO_FID; struct ksmbd_conn *conn = work->conn; int ret = 0; + char *buffer; if (work->next_smb2_rcv_hdr_off) { req = ksmbd_req_buf_next(work); @@ -7579,6 +7735,8 @@ goto out; } + buffer = (char *)req + le32_to_cpu(req->InputOffset); + cnt_code = le32_to_cpu(req->CtlCode); ret = smb2_calc_max_out_buf_len(work, 48, le32_to_cpu(req->MaxOutputResponse)); @@ -7636,7 +7794,7 @@ } ret = fsctl_validate_negotiate_info(conn, - (struct validate_negotiate_info_req *)&req->Buffer[0], + (struct validate_negotiate_info_req *)buffer, (struct validate_negotiate_info_rsp *)&rsp->Buffer[0], in_buf_len); if (ret < 0) @@ -7689,7 +7847,7 @@ rsp->VolatileFileId = req->VolatileFileId; rsp->PersistentFileId = req->PersistentFileId; fsctl_copychunk(work, - (struct copychunk_ioctl_req *)&req->Buffer[0], + (struct copychunk_ioctl_req *)buffer, le32_to_cpu(req->CtlCode), le32_to_cpu(req->InputCount), req->VolatileFileId, @@ -7702,8 +7860,7 @@ goto out; } - ret = fsctl_set_sparse(work, id, - (struct file_sparse *)&req->Buffer[0]); + ret = fsctl_set_sparse(work, id, (struct file_sparse *)buffer); if (ret < 0) goto out; break; @@ -7726,7 +7883,7 @@ } zero_data = - (struct file_zero_data_information *)&req->Buffer[0]; + (struct file_zero_data_information *)buffer; off = le64_to_cpu(zero_data->FileOffset); bfz = le64_to_cpu(zero_data->BeyondFinalZero); @@ -7757,7 +7914,7 @@ } ret = fsctl_query_allocated_ranges(work, id, - (struct file_allocated_range_buffer *)&req->Buffer[0], + (struct file_allocated_range_buffer *)buffer, (struct file_allocated_range_buffer *)&rsp->Buffer[0], out_buf_len / sizeof(struct file_allocated_range_buffer), &nbytes); @@ -7801,7 +7958,7 @@ goto out; } - dup_ext = (struct duplicate_extents_to_file *)&req->Buffer[0]; + dup_ext = (struct duplicate_extents_to_file *)buffer; fp_in = ksmbd_lookup_fd_slow(work, dup_ext->VolatileFileHandle, dup_ext->PersistentFileHandle); @@ -7870,9 +8027,9 @@ rsp->Reserved = cpu_to_le16(0); rsp->Flags = cpu_to_le32(0); rsp->Reserved2 = cpu_to_le32(0); - inc_rfc1001_len(work->response_buf, 48 + nbytes); - - return 0; + ret = ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_ioctl_rsp) + nbytes); + if (!ret) + return ret; out: if (ret == -EACCES) @@ -7897,8 +8054,8 @@ */ static void smb20_oplock_break_ack(struct ksmbd_work *work) { - struct smb2_oplock_break *req = smb2_get_msg(work->request_buf); - struct smb2_oplock_break *rsp = smb2_get_msg(work->response_buf); + struct smb2_oplock_break *req; + struct smb2_oplock_break *rsp; struct ksmbd_file *fp; struct oplock_info *opinfo = NULL; __le32 err = 0; @@ -7907,6 +8064,8 @@ char req_oplevel = 0, rsp_oplevel = 0; unsigned int oplock_change_type; + WORK_BUFFERS(work, req, rsp); + volatile_id = req->VolatileFid; persistent_id = req->PersistentFid; req_oplevel = req->OplockLevel; @@ -7994,10 +8153,10 @@ goto err_out; } - opinfo_put(opinfo); - ksmbd_fd_put(work, fp); opinfo->op_state = OPLOCK_STATE_NONE; wake_up_interruptible_all(&opinfo->oplock_q); + opinfo_put(opinfo); + ksmbd_fd_put(work, fp); rsp->StructureSize = cpu_to_le16(24); rsp->OplockLevel = rsp_oplevel; @@ -8005,7 +8164,8 @@ rsp->Reserved2 = 0; rsp->VolatileFid = volatile_id; rsp->PersistentFid = persistent_id; - inc_rfc1001_len(work->response_buf, 24); + ret = ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_oplock_break)); + if (!ret) return; err_out: @@ -8041,8 +8201,8 @@ static void smb21_lease_break_ack(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; - struct smb2_lease_ack *req = smb2_get_msg(work->request_buf); - struct smb2_lease_ack *rsp = smb2_get_msg(work->response_buf); + struct smb2_lease_ack *req; + struct smb2_lease_ack *rsp; struct oplock_info *opinfo; __le32 err = 0; int ret = 0; @@ -8050,6 +8210,8 @@ __le32 lease_state; struct lease *lease; + WORK_BUFFERS(work, req, rsp); + ksmbd_debug(OPLOCK, "smb21 lease break, lease state(0x%x)\n", le32_to_cpu(req->LeaseState)); opinfo = lookup_lease_in_table(conn, req->LeaseKey); @@ -8136,6 +8298,11 @@ le32_to_cpu(req->LeaseState)); } + if (ret < 0) { + rsp->hdr.Status = err; + goto err_out; + } + lease_state = lease->state; opinfo->op_state = OPLOCK_STATE_NONE; wake_up_interruptible_all(&opinfo->oplock_q); @@ -8143,22 +8310,17 @@ wake_up_interruptible_all(&opinfo->oplock_brk); opinfo_put(opinfo); - if (ret < 0) { - rsp->hdr.Status = err; - goto err_out; - } - rsp->StructureSize = cpu_to_le16(36); rsp->Reserved = 0; rsp->Flags = 0; memcpy(rsp->LeaseKey, req->LeaseKey, 16); rsp->LeaseState = lease_state; rsp->LeaseDuration = 0; - inc_rfc1001_len(work->response_buf, 36); + ret = ksmbd_iov_pin_rsp(work, rsp, sizeof(struct smb2_lease_ack)); + if (!ret) return; err_out: - opinfo->op_state = OPLOCK_STATE_NONE; wake_up_interruptible_all(&opinfo->oplock_q); atomic_dec(&opinfo->breaking_cnt); wake_up_interruptible_all(&opinfo->oplock_brk); @@ -8175,8 +8337,10 @@ */ int smb2_oplock_break(struct ksmbd_work *work) { - struct smb2_oplock_break *req = smb2_get_msg(work->request_buf); - struct smb2_oplock_break *rsp = smb2_get_msg(work->response_buf); + struct smb2_oplock_break *req; + struct smb2_oplock_break *rsp; + + WORK_BUFFERS(work, req, rsp); switch (le16_to_cpu(req->StructureSize)) { case OP_BREAK_STRUCT_SIZE_20: @@ -8291,43 +8455,19 @@ void smb2_set_sign_rsp(struct ksmbd_work *work) { struct smb2_hdr *hdr; - struct smb2_hdr *req_hdr; char signature[SMB2_HMACSHA256_SIZE]; - struct kvec iov[2]; - size_t len; + struct kvec *iov; int n_vec = 1; - hdr = smb2_get_msg(work->response_buf); - if (work->next_smb2_rsp_hdr_off) - hdr = ksmbd_resp_buf_next(work); - - req_hdr = ksmbd_req_buf_next(work); - - if (!work->next_smb2_rsp_hdr_off) { - len = get_rfc1002_len(work->response_buf); - if (req_hdr->NextCommand) - len = ALIGN(len, 8); - } else { - len = get_rfc1002_len(work->response_buf) - - work->next_smb2_rsp_hdr_off; - len = ALIGN(len, 8); - } - - if (req_hdr->NextCommand) - hdr->NextCommand = cpu_to_le32(len); - + hdr = ksmbd_resp_buf_curr(work); hdr->Flags |= SMB2_FLAGS_SIGNED; memset(hdr->Signature, 0, SMB2_SIGNATURE_SIZE); - iov[0].iov_base = (char *)&hdr->ProtocolId; - iov[0].iov_len = len; - - if (work->aux_payload_sz) { - iov[0].iov_len -= work->aux_payload_sz; - - iov[1].iov_base = work->aux_payload_buf; - iov[1].iov_len = work->aux_payload_sz; + if (hdr->Command == SMB2_READ) { + iov = &work->iov[work->iov_idx - 1]; n_vec++; + } else { + iov = &work->iov[work->iov_idx]; } if (!ksmbd_sign_smb2_pdu(work->conn, work->sess->sess_key, iov, n_vec, @@ -8403,29 +8543,14 @@ void smb3_set_sign_rsp(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; - struct smb2_hdr *req_hdr, *hdr; + struct smb2_hdr *hdr; struct channel *chann; char signature[SMB2_CMACAES_SIZE]; - struct kvec iov[2]; + struct kvec *iov; int n_vec = 1; - size_t len; char *signing_key; - hdr = smb2_get_msg(work->response_buf); - if (work->next_smb2_rsp_hdr_off) - hdr = ksmbd_resp_buf_next(work); - - req_hdr = ksmbd_req_buf_next(work); - - if (!work->next_smb2_rsp_hdr_off) { - len = get_rfc1002_len(work->response_buf); - if (req_hdr->NextCommand) - len = ALIGN(len, 8); - } else { - len = get_rfc1002_len(work->response_buf) - - work->next_smb2_rsp_hdr_off; - len = ALIGN(len, 8); - } + hdr = ksmbd_resp_buf_curr(work); if (conn->binding == false && le16_to_cpu(hdr->Command) == SMB2_SESSION_SETUP_HE) { @@ -8441,21 +8566,18 @@ if (!signing_key) return; - if (req_hdr->NextCommand) - hdr->NextCommand = cpu_to_le32(len); - hdr->Flags |= SMB2_FLAGS_SIGNED; memset(hdr->Signature, 0, SMB2_SIGNATURE_SIZE); - iov[0].iov_base = (char *)&hdr->ProtocolId; - iov[0].iov_len = len; - if (work->aux_payload_sz) { - iov[0].iov_len -= work->aux_payload_sz; - iov[1].iov_base = work->aux_payload_buf; - iov[1].iov_len = work->aux_payload_sz; + + if (hdr->Command == SMB2_READ) { + iov = &work->iov[work->iov_idx - 1]; n_vec++; + } else { + iov = &work->iov[work->iov_idx]; } - if (!ksmbd_sign_smb3_pdu(conn, signing_key, iov, n_vec, signature)) + if (!ksmbd_sign_smb3_pdu(conn, signing_key, iov, n_vec, + signature)) memcpy(hdr->Signature, signature, SMB2_SIGNATURE_SIZE); } @@ -8522,45 +8644,22 @@ int smb3_encrypt_resp(struct ksmbd_work *work) { - char *buf = work->response_buf; - struct kvec iov[3]; + struct kvec *iov = work->iov; int rc = -ENOMEM; - int buf_size = 0, rq_nvec = 2 + (work->aux_payload_sz ? 1 : 0); - - if (ARRAY_SIZE(iov) < rq_nvec) - return -ENOMEM; + void *tr_buf; - work->tr_buf = kzalloc(sizeof(struct smb2_transform_hdr) + 4, GFP_KERNEL); - if (!work->tr_buf) + tr_buf = kzalloc(sizeof(struct smb2_transform_hdr) + 4, GFP_KERNEL); + if (!tr_buf) return rc; /* fill transform header */ - fill_transform_hdr(work->tr_buf, buf, work->conn->cipher_type); + fill_transform_hdr(tr_buf, work->response_buf, work->conn->cipher_type); - iov[0].iov_base = work->tr_buf; + iov[0].iov_base = tr_buf; iov[0].iov_len = sizeof(struct smb2_transform_hdr) + 4; - buf_size += iov[0].iov_len - 4; - - iov[1].iov_base = buf + 4; - iov[1].iov_len = get_rfc1002_len(buf); - if (work->aux_payload_sz) { - iov[1].iov_len = work->resp_hdr_sz - 4; + work->tr_buf = tr_buf; - iov[2].iov_base = work->aux_payload_buf; - iov[2].iov_len = work->aux_payload_sz; - buf_size += iov[2].iov_len; - } - buf_size += iov[1].iov_len; - work->resp_hdr_sz = iov[1].iov_len; - - rc = ksmbd_crypt_message(work, iov, rq_nvec, 1); - if (rc) - return rc; - - memmove(buf, iov[1].iov_base, iov[1].iov_len); - *(__be32 *)work->tr_buf = cpu_to_be32(buf_size); - - return rc; + return ksmbd_crypt_message(work, iov, work->iov_idx + 1, 1); } bool smb3_is_transform_hdr(void *buf) @@ -8580,7 +8679,8 @@ struct smb2_transform_hdr *tr_hdr = smb2_get_msg(buf); int rc = 0; - if (buf_data_size < sizeof(struct smb2_hdr)) { + if (pdu_length < sizeof(struct smb2_transform_hdr) || + buf_data_size < sizeof(struct smb2_hdr)) { pr_err("Transform message is too small (%u)\n", pdu_length); return -ECONNABORTED; diff -ruw linux-6.4/fs/smb/server/smb2pdu.h linux-6.4-fbx/fs/smb/server/smb2pdu.h --- linux-6.4/fs/smb/server/smb2pdu.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smb2pdu.h 2023-11-07 13:38:44.046256254 +0100 @@ -361,7 +361,7 @@ __u8 Flags; __u8 EaNameLength; __le16 EaValueLength; - char name[1]; + char name[]; /* optionally followed by value */ } __packed; /* level 15 Query */ @@ -407,6 +407,9 @@ } __packed; /* functions */ +#ifdef CONFIG_SMB_INSECURE_SERVER +void init_smb2_0_server(struct ksmbd_conn *conn); +#endif void init_smb2_1_server(struct ksmbd_conn *conn); void init_smb3_0_server(struct ksmbd_conn *conn); void init_smb3_02_server(struct ksmbd_conn *conn); diff -ruw linux-6.4/fs/smb/server/smb_common.c linux-6.4-fbx/fs/smb/server/smb_common.c --- linux-6.4/fs/smb/server/smb_common.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smb_common.c 2024-01-25 13:36:32.718984668 +0100 @@ -17,6 +17,10 @@ #include "mgmt/tree_connect.h" #include "mgmt/share_config.h" +#ifdef CONFIG_SMB_INSECURE_SERVER +#include "smb1pdu.h" +#endif + /*for shortname implementation */ static const char basechars[43] = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ_-!@#$%"; #define MANGLE_BASE (sizeof(basechars) / sizeof(char) - 1) @@ -32,6 +36,20 @@ }; static struct smb_protocol smb1_protos[] = { +#ifdef CONFIG_SMB_INSECURE_SERVER + { + SMB1_PROT, + "\2NT LM 0.12", + "NT1", + SMB10_PROT_ID + }, + { + SMB2_PROT, + "\2SMB 2.002", + "SMB2_02", + SMB20_PROT_ID + }, +#endif { SMB21_PROT, "\2SMB 2.1", @@ -90,7 +108,11 @@ inline int ksmbd_min_protocol(void) { +#ifdef CONFIG_SMB_INSECURE_SERVER + return SMB1_PROT; +#else return SMB21_PROT; +#endif } inline int ksmbd_max_protocol(void) @@ -135,6 +157,16 @@ int ksmbd_verify_smb_message(struct ksmbd_work *work) { struct smb2_hdr *smb2_hdr = ksmbd_req_buf_next(work); + +#ifdef CONFIG_SMB_INSECURE_SERVER + if (smb2_hdr->ProtocolId == SMB2_PROTO_NUMBER) { + ksmbd_debug(SMB, "got SMB2 command\n"); + return ksmbd_smb2_check_message(work); + } + + work->conn->outstanding_credits++; + return ksmbd_smb1_check_message(work); +#else struct smb_hdr *hdr; if (smb2_hdr->ProtocolId == SMB2_PROTO_NUMBER) @@ -148,6 +180,7 @@ } return -EINVAL; +#endif } /** @@ -158,8 +191,12 @@ */ bool ksmbd_smb_request(struct ksmbd_conn *conn) { - __le32 *proto = (__le32 *)smb2_get_msg(conn->request_buf); + __le32 *proto; + if (conn->request_buf[0] != 0) + return false; + + proto = (__le32 *)smb2_get_msg(conn->request_buf); if (*proto == SMB2_COMPRESSION_TRANSFORM_ID) { pr_err_ratelimited("smb2 compression not support yet"); return false; @@ -295,6 +332,7 @@ return BAD_PROT_ID; } +#ifndef CONFIG_SMB_INSECURE_SERVER #define SMB_COM_NEGOTIATE_EX 0x0 /** @@ -319,12 +357,6 @@ struct smb_hdr *rsp_hdr = (struct smb_hdr *)work->response_buf; struct smb_hdr *rcv_hdr = (struct smb_hdr *)work->request_buf; - /* - * Remove 4 byte direct TCP header. - */ - *(__be32 *)work->response_buf = - cpu_to_be32(sizeof(struct smb_hdr) - 4); - rsp_hdr->Command = SMB_COM_NEGOTIATE; *(__le32 *)rsp_hdr->Protocol = SMB1_PROTO_NUMBER; rsp_hdr->Flags = SMBFLG_RESPONSE; @@ -359,8 +391,8 @@ */ static int smb1_allocate_rsp_buf(struct ksmbd_work *work) { - work->response_buf = kmalloc(MAX_CIFS_SMALL_BUFFER_SIZE, - GFP_KERNEL | __GFP_ZERO); + work->response_buf = kzalloc(MAX_CIFS_SMALL_BUFFER_SIZE, + GFP_KERNEL); work->response_sz = MAX_CIFS_SMALL_BUFFER_SIZE; if (!work->response_buf) { @@ -388,26 +420,30 @@ [SMB_COM_NEGOTIATE_EX] = { .proc = smb1_negotiate, }, }; -static void init_smb1_server(struct ksmbd_conn *conn) +static int init_smb1_server(struct ksmbd_conn *conn) { conn->ops = &smb1_server_ops; conn->cmds = smb1_server_cmds; conn->max_cmds = ARRAY_SIZE(smb1_server_cmds); + return 0; } +#endif -void ksmbd_init_smb_server(struct ksmbd_work *work) +int ksmbd_init_smb_server(struct ksmbd_work *work) { struct ksmbd_conn *conn = work->conn; __le32 proto; - if (conn->need_neg == false) - return; - proto = *(__le32 *)((struct smb_hdr *)work->request_buf)->Protocol; + if (conn->need_neg == false) { if (proto == SMB1_PROTO_NUMBER) - init_smb1_server(conn); - else - init_smb3_11_server(conn); + return -EINVAL; + return 0; + } + + if (proto == SMB1_PROTO_NUMBER) + return init_smb1_server(conn); + return init_smb3_11_server(conn); } int ksmbd_populate_dot_dotdot_entries(struct ksmbd_work *work, int info_level, @@ -551,21 +587,24 @@ conn->dialect <= SMB311_PROT_ID); } +#ifndef CONFIG_SMB_INSECURE_SERVER static int smb_handle_negotiate(struct ksmbd_work *work) { struct smb_negotiate_rsp *neg_rsp = work->response_buf; ksmbd_debug(SMB, "Unsupported SMB1 protocol\n"); - /* Add 2 byte bcc and 2 byte DialectIndex. */ - inc_rfc1001_len(work->response_buf, 4); - neg_rsp->hdr.Status.CifsError = STATUS_SUCCESS; + if (ksmbd_iov_pin_rsp(work, (void *)neg_rsp, + sizeof(struct smb_negotiate_rsp) - 4)) + return -ENOMEM; + neg_rsp->hdr.Status.CifsError = STATUS_SUCCESS; neg_rsp->hdr.WordCount = 1; neg_rsp->DialectIndex = cpu_to_le16(work->conn->dialect); neg_rsp->ByteCount = 0; return 0; } +#endif int ksmbd_smb_negotiate_common(struct ksmbd_work *work, unsigned int command) { diff -ruw linux-6.4/fs/smb/server/smb_common.h linux-6.4-fbx/fs/smb/server/smb_common.h --- linux-6.4/fs/smb/server/smb_common.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smb_common.h 2023-11-07 13:38:44.046256254 +0100 @@ -49,6 +49,42 @@ /* * File Attribute flags */ +#ifdef CONFIG_SMB_INSECURE_SERVER +#define ATTR_READONLY 0x0001 +#define ATTR_HIDDEN 0x0002 +#define ATTR_SYSTEM 0x0004 +#define ATTR_VOLUME 0x0008 +#define ATTR_DIRECTORY 0x0010 +#define ATTR_ARCHIVE 0x0020 +#define ATTR_DEVICE 0x0040 +#define ATTR_NORMAL 0x0080 +#define ATTR_TEMPORARY 0x0100 +#define ATTR_SPARSE 0x0200 +#define ATTR_REPARSE 0x0400 +#define ATTR_COMPRESSED 0x0800 +#define ATTR_OFFLINE 0x1000 +#define ATTR_NOT_CONTENT_INDEXED 0x2000 +#define ATTR_ENCRYPTED 0x4000 + +#define ATTR_READONLY_LE cpu_to_le32(ATTR_READONLY) +#define ATTR_HIDDEN_LE cpu_to_le32(ATTR_HIDDEN) +#define ATTR_SYSTEM_LE cpu_to_le32(ATTR_SYSTEM) +#define ATTR_DIRECTORY_LE cpu_to_le32(ATTR_DIRECTORY) +#define ATTR_ARCHIVE_LE cpu_to_le32(ATTR_ARCHIVE) +#define ATTR_NORMAL_LE cpu_to_le32(ATTR_NORMAL) +#define ATTR_TEMPORARY_LE cpu_to_le32(ATTR_TEMPORARY) +#define ATTR_SPARSE_FILE_LE cpu_to_le32(ATTR_SPARSE) +#define ATTR_REPARSE_POINT_LE cpu_to_le32(ATTR_REPARSE) +#define ATTR_COMPRESSED_LE cpu_to_le32(ATTR_COMPRESSED) +#define ATTR_OFFLINE_LE cpu_to_le32(ATTR_OFFLINE) +#define ATTR_NOT_CONTENT_INDEXED_LE cpu_to_le32(ATTR_NOT_CONTENT_INDEXED) +#define ATTR_ENCRYPTED_LE cpu_to_le32(ATTR_ENCRYPTED) +#define ATTR_INTEGRITY_STREAML_LE cpu_to_le32(0x00008000) +#define ATTR_NO_SCRUB_DATA_LE cpu_to_le32(0x00020000) +#define ATTR_MASK_LE cpu_to_le32(0x00007FB7) + +#define IS_SMB2(x) ((x)->vals->protocol_id != SMB10_PROT_ID) +#endif #define ATTR_POSIX_SEMANTICS 0x01000000 #define ATTR_BACKUP_SEMANTICS 0x02000000 #define ATTR_DELETE_ON_CLOSE 0x04000000 @@ -203,11 +239,13 @@ unsigned char DialectsArray[1]; } __packed; +#ifndef CONFIG_SMB_INSECURE_SERVER struct smb_negotiate_rsp { struct smb_hdr hdr; /* wct = 17 */ __le16 DialectIndex; /* 0xFFFF = no dialect acceptable */ __le16 ByteCount; } __packed; +#endif struct filesystem_attribute_info { __le32 Attributes; @@ -236,6 +274,14 @@ __le32 BytesPerSector; } __packed; /* size info, level 0x103 */ +struct filesystem_full_info { + __le64 TotalAllocationUnits; + __le64 FreeAllocationUnits; + __le64 ActualAvailableUnits; + __le32 SectorsPerAllocationUnit; + __le32 BytesPerSector; +} __packed; /* size info, level 0x3ef */ + #define EXTENDED_INFO_MAGIC 0x43667364 /* Cfsd */ #define STRING_LENGTH 28 @@ -427,7 +473,7 @@ int ksmbd_lookup_dialect_by_id(__le16 *cli_dialects, __le16 dialects_count); -void ksmbd_init_smb_server(struct ksmbd_work *work); +int ksmbd_init_smb_server(struct ksmbd_work *work); struct ksmbd_kstat; int ksmbd_populate_dot_dotdot_entries(struct ksmbd_work *work, diff -ruw linux-6.4/fs/smb/server/smbacl.c linux-6.4-fbx/fs/smb/server/smbacl.c --- linux-6.4/fs/smb/server/smbacl.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smbacl.c 2024-01-25 13:36:32.718984668 +0100 @@ -401,10 +401,6 @@ if (num_aces > ULONG_MAX / sizeof(struct smb_ace *)) return; - ppace = kmalloc_array(num_aces, sizeof(struct smb_ace *), GFP_KERNEL); - if (!ppace) - return; - ret = init_acl_state(&acl_state, num_aces); if (ret) return; @@ -414,6 +410,13 @@ return; } + ppace = kmalloc_array(num_aces, sizeof(struct smb_ace *), GFP_KERNEL); + if (!ppace) { + free_acl_state(&default_acl_state); + free_acl_state(&acl_state); + return; + } + /* * reset rwx permissions for user/group/other. * Also, if num_aces is 0 i.e. DACL has no ACEs, @@ -1107,6 +1110,7 @@ struct smb_acl *pdacl; struct smb_sid *powner_sid = NULL, *pgroup_sid = NULL; int powner_sid_size = 0, pgroup_sid_size = 0, pntsd_size; + int pntsd_alloc_size; if (parent_pntsd->osidoffset) { powner_sid = (struct smb_sid *)((char *)parent_pntsd + @@ -1119,9 +1123,10 @@ pgroup_sid_size = 1 + 1 + 6 + (pgroup_sid->num_subauth * 4); } - pntsd = kzalloc(sizeof(struct smb_ntsd) + powner_sid_size + - pgroup_sid_size + sizeof(struct smb_acl) + - nt_size, GFP_KERNEL); + pntsd_alloc_size = sizeof(struct smb_ntsd) + powner_sid_size + + pgroup_sid_size + sizeof(struct smb_acl) + nt_size; + + pntsd = kzalloc(pntsd_alloc_size, GFP_KERNEL); if (!pntsd) { rc = -ENOMEM; goto free_aces_base; @@ -1136,6 +1141,27 @@ pntsd->gsidoffset = parent_pntsd->gsidoffset; pntsd->dacloffset = parent_pntsd->dacloffset; + if ((u64)le32_to_cpu(pntsd->osidoffset) + powner_sid_size > + pntsd_alloc_size) { + rc = -EINVAL; + kfree(pntsd); + goto free_aces_base; + } + + if ((u64)le32_to_cpu(pntsd->gsidoffset) + pgroup_sid_size > + pntsd_alloc_size) { + rc = -EINVAL; + kfree(pntsd); + goto free_aces_base; + } + + if ((u64)le32_to_cpu(pntsd->dacloffset) + sizeof(struct smb_acl) + nt_size > + pntsd_alloc_size) { + rc = -EINVAL; + kfree(pntsd); + goto free_aces_base; + } + if (pntsd->osidoffset) { struct smb_sid *owner_sid = (struct smb_sid *)((char *)pntsd + le32_to_cpu(pntsd->osidoffset)); @@ -1162,7 +1188,7 @@ pntsd_size += sizeof(struct smb_acl) + nt_size; } - ksmbd_vfs_set_sd_xattr(conn, idmap, path, pntsd, pntsd_size); + ksmbd_vfs_set_sd_xattr(conn, idmap, path, pntsd, pntsd_size, false); kfree(pntsd); } @@ -1354,7 +1380,7 @@ int set_info_sec(struct ksmbd_conn *conn, struct ksmbd_tree_connect *tcon, const struct path *path, struct smb_ntsd *pntsd, int ntsd_len, - bool type_check) + bool type_check, bool get_write) { int rc; struct smb_fattr fattr = {{0}}; @@ -1414,13 +1440,13 @@ if (test_share_config_flag(tcon->share_conf, KSMBD_SHARE_FLAG_ACL_XATTR)) { /* Update WinACL in xattr */ ksmbd_vfs_remove_sd_xattrs(idmap, path); - ksmbd_vfs_set_sd_xattr(conn, idmap, path, pntsd, ntsd_len); + ksmbd_vfs_set_sd_xattr(conn, idmap, path, pntsd, ntsd_len, + get_write); } out: posix_acl_release(fattr.cf_acls); posix_acl_release(fattr.cf_dacls); - mark_inode_dirty(inode); return rc; } diff -ruw linux-6.4/fs/smb/server/smbacl.h linux-6.4-fbx/fs/smb/server/smbacl.h --- linux-6.4/fs/smb/server/smbacl.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/smbacl.h 2024-01-25 13:36:32.722984777 +0100 @@ -207,7 +207,7 @@ __le32 *pdaccess, int uid); int set_info_sec(struct ksmbd_conn *conn, struct ksmbd_tree_connect *tcon, const struct path *path, struct smb_ntsd *pntsd, int ntsd_len, - bool type_check); + bool type_check, bool get_write); void id_to_sid(unsigned int cid, uint sidtype, struct smb_sid *ssid); void ksmbd_init_domain(u32 *sub_auth); diff -ruw linux-6.4/fs/smb/server/transport_ipc.c linux-6.4-fbx/fs/smb/server/transport_ipc.c --- linux-6.4/fs/smb/server/transport_ipc.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/transport_ipc.c 2024-04-19 15:59:31.197600671 +0200 @@ -65,6 +65,7 @@ struct hlist_node ipc_table_hlist; void *response; + unsigned int msg_sz; }; static struct delayed_work ipc_timer_work; @@ -74,7 +75,7 @@ static int handle_generic_event(struct sk_buff *skb, struct genl_info *info); static int ksmbd_ipc_heartbeat_request(void); -static const struct nla_policy ksmbd_nl_policy[KSMBD_EVENT_MAX] = { +static const struct nla_policy ksmbd_nl_policy[KSMBD_EVENT_MAX + 1] = { [KSMBD_EVENT_UNSPEC] = { .len = 0, }, @@ -229,7 +230,7 @@ struct ksmbd_ipc_msg *msg; size_t msg_sz = sz + sizeof(struct ksmbd_ipc_msg); - msg = kvmalloc(msg_sz, GFP_KERNEL | __GFP_ZERO); + msg = kvzalloc(msg_sz, GFP_KERNEL); if (msg) msg->sz = sz; return msg; @@ -268,13 +269,14 @@ entry->type + 1, type); } - entry->response = kvmalloc(sz, GFP_KERNEL | __GFP_ZERO); + entry->response = kvzalloc(sz, GFP_KERNEL); if (!entry->response) { ret = -ENOMEM; break; } memcpy(entry->response, payload, sz); + entry->msg_sz = sz; wake_up_interruptible(&entry->wait); ret = 0; break; @@ -403,7 +405,7 @@ return -EPERM; #endif - if (type >= KSMBD_EVENT_MAX) { + if (type > KSMBD_EVENT_MAX) { WARN_ON(1); return -EINVAL; } @@ -453,6 +455,34 @@ return ret; } +static int ipc_validate_msg(struct ipc_msg_table_entry *entry) +{ + unsigned int msg_sz = entry->msg_sz; + + if (entry->type == KSMBD_EVENT_RPC_REQUEST) { + struct ksmbd_rpc_command *resp = entry->response; + + msg_sz = sizeof(struct ksmbd_rpc_command) + resp->payload_sz; + } else if (entry->type == KSMBD_EVENT_SPNEGO_AUTHEN_REQUEST) { + struct ksmbd_spnego_authen_response *resp = entry->response; + + msg_sz = sizeof(struct ksmbd_spnego_authen_response) + + resp->session_key_len + resp->spnego_blob_len; + } else if (entry->type == KSMBD_EVENT_SHARE_CONFIG_REQUEST) { + struct ksmbd_share_config_response *resp = entry->response; + + if (resp->payload_sz) { + if (resp->payload_sz < resp->veto_list_sz) + return -EINVAL; + + msg_sz = sizeof(struct ksmbd_share_config_response) + + resp->payload_sz; + } + } + + return entry->msg_sz != msg_sz ? -EINVAL : 0; +} + static void *ipc_msg_send_request(struct ksmbd_ipc_msg *msg, unsigned int handle) { struct ipc_msg_table_entry entry; @@ -477,6 +507,13 @@ ret = wait_event_interruptible_timeout(entry.wait, entry.response != NULL, IPC_WAIT_TIMEOUT); + if (entry.response) { + ret = ipc_validate_msg(&entry); + if (ret) { + kvfree(entry.response); + entry.response = NULL; + } + } out: down_write(&ipc_msg_table_lock); hash_del(&entry.ipc_table_hlist); diff -ruw linux-6.4/fs/smb/server/transport_tcp.c linux-6.4-fbx/fs/smb/server/transport_tcp.c --- linux-6.4/fs/smb/server/transport_tcp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/transport_tcp.c 2024-01-25 13:36:32.722984777 +0100 @@ -185,6 +185,7 @@ struct sockaddr *csin; int rc = 0; struct tcp_transport *t; + struct task_struct *handler; t = alloc_transport(client_sk); if (!t) { @@ -199,13 +200,13 @@ goto out_error; } - KSMBD_TRANS(t)->handler = kthread_run(ksmbd_conn_handler_loop, + handler = kthread_run(ksmbd_conn_handler_loop, KSMBD_TRANS(t)->conn, "ksmbd:%u", ksmbd_tcp_get_port(csin)); - if (IS_ERR(KSMBD_TRANS(t)->handler)) { + if (IS_ERR(handler)) { pr_err("cannot start conn thread\n"); - rc = PTR_ERR(KSMBD_TRANS(t)->handler); + rc = PTR_ERR(handler); free_transport(t); } return rc; diff -ruw linux-6.4/fs/smb/server/unicode.c linux-6.4-fbx/fs/smb/server/unicode.c --- linux-6.4/fs/smb/server/unicode.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/unicode.c 2023-11-07 13:38:44.046256254 +0100 @@ -14,46 +14,28 @@ #include "uniupr.h" #include "smb_common.h" -/* - * smb_utf16_bytes() - how long will a string be after conversion? - * @from: pointer to input string - * @maxbytes: don't go past this many bytes of input string - * @codepage: destination codepage - * - * Walk a utf16le string and return the number of bytes that the string will - * be after being converted to the given charset, not including any null - * termination required. Don't walk past maxbytes in the source buffer. - * - * Return: string length after conversion - */ -static int smb_utf16_bytes(const __le16 *from, int maxbytes, - const struct nls_table *codepage) +#ifdef CONFIG_SMB_INSECURE_SERVER +int smb1_utf16_name_length(const __le16 *from, int maxbytes) { - int i; - int charlen, outlen = 0; + int i, len = 0; int maxwords = maxbytes / 2; - char tmp[NLS_MAX_CHARSET_SIZE]; __u16 ftmp; for (i = 0; i < maxwords; i++) { ftmp = get_unaligned_le16(&from[i]); + len += 2; if (ftmp == 0) break; - - charlen = codepage->uni2char(ftmp, tmp, NLS_MAX_CHARSET_SIZE); - if (charlen > 0) - outlen += charlen; - else - outlen++; } - return outlen; + return len; } +#endif /* * cifs_mapchar() - convert a host-endian char to proper char in codepage * @target: where converted character should be copied - * @src_char: 2 byte host-endian source character + * @from: host-endian source string * @cp: codepage to which character should be converted * @mapchar: should character be mapped according to mapchars mount option? * @@ -64,10 +46,13 @@ * Return: string length after conversion */ static int -cifs_mapchar(char *target, const __u16 src_char, const struct nls_table *cp, +cifs_mapchar(char *target, const __u16 *from, const struct nls_table *cp, bool mapchar) { int len = 1; + __u16 src_char; + + src_char = *from; if (!mapchar) goto cp_convert; @@ -105,12 +90,66 @@ cp_convert: len = cp->uni2char(src_char, target, NLS_MAX_CHARSET_SIZE); - if (len <= 0) { + if (len <= 0) + goto surrogate_pair; + + goto out; + +surrogate_pair: + /* convert SURROGATE_PAIR and IVS */ + if (strcmp(cp->charset, "utf8")) + goto unknown; + len = utf16s_to_utf8s(from, 3, UTF16_LITTLE_ENDIAN, target, 6); + if (len <= 0) + goto unknown; + return len; + +unknown: *target = '?'; len = 1; + goto out; } - goto out; +/* + * smb_utf16_bytes() - how long will a string be after conversion? + * @from: pointer to input string + * @maxbytes: don't go past this many bytes of input string + * @codepage: destination codepage + * + * Walk a utf16le string and return the number of bytes that the string will + * be after being converted to the given charset, not including any null + * termination required. Don't walk past maxbytes in the source buffer. + * + * Return: string length after conversion + */ +static int smb_utf16_bytes(const __le16 *from, int maxbytes, + const struct nls_table *codepage) +{ + int i, j; + int charlen, outlen = 0; + int maxwords = maxbytes / 2; + char tmp[NLS_MAX_CHARSET_SIZE]; + __u16 ftmp[3]; + + for (i = 0; i < maxwords; i++) { + ftmp[0] = get_unaligned_le16(&from[i]); + if (ftmp[0] == 0) + break; + for (j = 1; j <= 2; j++) { + if (i + j < maxwords) + ftmp[j] = get_unaligned_le16(&from[i + j]); + else + ftmp[j] = 0; + } + + charlen = cifs_mapchar(tmp, ftmp, codepage, 0); + if (charlen > 0) + outlen += charlen; + else + outlen++; + } + + return outlen; } /* @@ -140,12 +179,12 @@ static int smb_from_utf16(char *to, const __le16 *from, int tolen, int fromlen, const struct nls_table *codepage, bool mapchar) { - int i, charlen, safelen; + int i, j, charlen, safelen; int outlen = 0; int nullsize = nls_nullsize(codepage); int fromwords = fromlen / 2; char tmp[NLS_MAX_CHARSET_SIZE]; - __u16 ftmp; + __u16 ftmp[3]; /* ftmp[3] = 3array x 2bytes = 6bytes UTF-16 */ /* * because the chars can be of varying widths, we need to take care @@ -156,9 +195,15 @@ safelen = tolen - (NLS_MAX_CHARSET_SIZE + nullsize); for (i = 0; i < fromwords; i++) { - ftmp = get_unaligned_le16(&from[i]); - if (ftmp == 0) + ftmp[0] = get_unaligned_le16(&from[i]); + if (ftmp[0] == 0) break; + for (j = 1; j <= 2; j++) { + if (i + j < fromwords) + ftmp[j] = get_unaligned_le16(&from[i + j]); + else + ftmp[j] = 0; + } /* * check to see if converting this character might make the @@ -173,6 +218,19 @@ /* put converted char into 'to' buffer */ charlen = cifs_mapchar(&to[outlen], ftmp, codepage, mapchar); outlen += charlen; + + /* + * charlen (=bytes of UTF-8 for 1 character) + * 4bytes UTF-8(surrogate pair) is charlen=4 + * (4bytes UTF-16 code) + * 7-8bytes UTF-8(IVS) is charlen=3+4 or 4+4 + * (2 UTF-8 pairs divided to 2 UTF-16 pairs) + */ + if (charlen == 4) + i++; + else if (charlen >= 5) + /* 5-6bytes UTF-8 */ + i += 2; } /* properly null-terminate string */ @@ -307,10 +365,15 @@ char src_char; __le16 dst_char; wchar_t tmp; + wchar_t *wchar_to; /* UTF-16 */ + int ret; + unicode_t u; if (!mapchars) return smb_strtoUTF16(target, source, srclen, cp); + wchar_to = kzalloc(6, GFP_KERNEL); + for (i = 0, j = 0; i < srclen; j++) { src_char = source[i]; charlen = 1; @@ -349,11 +412,55 @@ * if no match, use question mark, which at least in * some cases serves as wild card */ - if (charlen < 1) { + if (charlen > 0) + goto ctoUTF16; + + /* convert SURROGATE_PAIR */ + if (strcmp(cp->charset, "utf8") || !wchar_to) + goto unknown; + if (*(source + i) & 0x80) { + charlen = utf8_to_utf32(source + i, 6, &u); + if (charlen < 0) + goto unknown; + } else + goto unknown; + ret = utf8s_to_utf16s(source + i, charlen, + UTF16_LITTLE_ENDIAN, + wchar_to, 6); + if (ret < 0) + goto unknown; + + i += charlen; + dst_char = cpu_to_le16(*wchar_to); + if (charlen <= 3) + /* 1-3bytes UTF-8 to 2bytes UTF-16 */ + put_unaligned(dst_char, &target[j]); + else if (charlen == 4) { + /* 4bytes UTF-8(surrogate pair) to 4bytes UTF-16 + * 7-8bytes UTF-8(IVS) divided to 2 UTF-16 + * (charlen=3+4 or 4+4) */ + put_unaligned(dst_char, &target[j]); + dst_char = cpu_to_le16(*(wchar_to + 1)); + j++; + put_unaligned(dst_char, &target[j]); + } else if (charlen >= 5) { + /* 5-6bytes UTF-8 to 6bytes UTF-16 */ + put_unaligned(dst_char, &target[j]); + dst_char = cpu_to_le16(*(wchar_to + 1)); + j++; + put_unaligned(dst_char, &target[j]); + dst_char = cpu_to_le16(*(wchar_to + 2)); + j++; + put_unaligned(dst_char, &target[j]); + } + continue; + +unknown: dst_char = cpu_to_le16(0x003f); charlen = 1; } - } + +ctoUTF16: /* * character may take more than one byte in the source string, * but will take exactly two bytes in the target string diff -ruw linux-6.4/fs/smb/server/unicode.h linux-6.4-fbx/fs/smb/server/unicode.h --- linux-6.4/fs/smb/server/unicode.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/unicode.h 2023-11-07 13:38:44.046256254 +0100 @@ -63,6 +63,9 @@ #endif /* UNIUPR_NOLOWER */ #ifdef __KERNEL__ +#ifdef CONFIG_SMB_INSECURE_SERVER +int smb1_utf16_name_length(const __le16 *from, int maxbytes); +#endif int smb_strtoUTF16(__le16 *to, const char *from, int len, const struct nls_table *codepage); char *smb_strndup_from_utf16(const char *src, const int maxlen, diff -ruw linux-6.4/fs/smb/server/vfs.c linux-6.4-fbx/fs/smb/server/vfs.c --- linux-6.4/fs/smb/server/vfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/vfs.c 2024-03-18 14:40:14.867741770 +0100 @@ -63,13 +63,13 @@ static int ksmbd_vfs_path_lookup_locked(struct ksmbd_share_config *share_conf, char *pathname, unsigned int flags, + struct path *parent_path, struct path *path) { struct qstr last; struct filename *filename; struct path *root_share_path = &share_conf->vfs_path; int err, type; - struct path parent_path; struct dentry *d; if (pathname[0] == '\0') { @@ -84,7 +84,7 @@ return PTR_ERR(filename); err = vfs_path_parent_lookup(filename, flags, - &parent_path, &last, &type, + parent_path, &last, &type, root_share_path); if (err) { putname(filename); @@ -92,13 +92,20 @@ } if (unlikely(type != LAST_NORM)) { - path_put(&parent_path); + path_put(parent_path); + putname(filename); + return -ENOENT; + } + + err = mnt_want_write(parent_path->mnt); + if (err) { + path_put(parent_path); putname(filename); return -ENOENT; } - inode_lock_nested(parent_path.dentry->d_inode, I_MUTEX_PARENT); - d = lookup_one_qstr_excl(&last, parent_path.dentry, 0); + inode_lock_nested(parent_path->dentry->d_inode, I_MUTEX_PARENT); + d = lookup_one_qstr_excl(&last, parent_path->dentry, 0); if (IS_ERR(d)) goto err_out; @@ -108,24 +115,30 @@ } path->dentry = d; - path->mnt = share_conf->vfs_path.mnt; - path_put(&parent_path); - putname(filename); + path->mnt = mntget(parent_path->mnt); + if (test_share_config_flag(share_conf, KSMBD_SHARE_FLAG_CROSSMNT)) { + err = follow_down(path, 0); + if (err < 0) { + path_put(path); + goto err_out; + } + } + + putname(filename); return 0; err_out: - inode_unlock(parent_path.dentry->d_inode); - path_put(&parent_path); + inode_unlock(d_inode(parent_path->dentry)); + mnt_drop_write(parent_path->mnt); + path_put(parent_path); putname(filename); return -ENOENT; } -int ksmbd_vfs_query_maximal_access(struct mnt_idmap *idmap, +void ksmbd_vfs_query_maximal_access(struct mnt_idmap *idmap, struct dentry *dentry, __le32 *daccess) { - int ret = 0; - *daccess = cpu_to_le32(FILE_READ_ATTRIBUTES | READ_CONTROL); if (!inode_permission(idmap, d_inode(dentry), MAY_OPEN | MAY_WRITE)) @@ -142,8 +155,6 @@ if (!inode_permission(idmap, d_inode(dentry->d_parent), MAY_EXEC | MAY_WRITE)) *daccess |= FILE_DELETE_LE; - - return ret; } /** @@ -170,10 +181,6 @@ return err; } - err = mnt_want_write(path.mnt); - if (err) - goto out_err; - mode |= S_IFREG; err = vfs_create(mnt_idmap(path.mnt), d_inode(path.dentry), dentry, mode, true); @@ -183,9 +190,7 @@ } else { pr_err("File(%s): creation failed (err:%d)\n", name, err); } - mnt_drop_write(path.mnt); -out_err: done_path_create(&path, dentry); return err; } @@ -216,10 +221,6 @@ return err; } - err = mnt_want_write(path.mnt); - if (err) - goto out_err2; - idmap = mnt_idmap(path.mnt); mode |= S_IFDIR; err = vfs_mkdir(idmap, d_inode(path.dentry), dentry, mode); @@ -230,21 +231,19 @@ dentry->d_name.len); if (IS_ERR(d)) { err = PTR_ERR(d); - goto out_err1; + goto out_err; } if (unlikely(d_is_negative(d))) { dput(d); err = -ENOENT; - goto out_err1; + goto out_err; } ksmbd_vfs_inherit_owner(work, d_inode(path.dentry), d_inode(d)); dput(d); } -out_err1: - mnt_drop_write(path.mnt); -out_err2: +out_err: done_path_create(&path, dentry); if (err) pr_err("mkdir(%s): creation failed (err:%d)\n", name, err); @@ -364,15 +363,15 @@ * @fid: file id of open file * @count: read byte count * @pos: file pos + * @rbuf: read data buffer * * Return: number of read bytes on success, otherwise error */ int ksmbd_vfs_read(struct ksmbd_work *work, struct ksmbd_file *fp, size_t count, - loff_t *pos) + loff_t *pos, char *rbuf) { struct file *filp = fp->filp; ssize_t nbytes = 0; - char *rbuf = work->aux_payload_buf; struct inode *inode = file_inode(filp); if (S_ISDIR(inode->i_mode)) @@ -416,7 +415,8 @@ { char *stream_buf = NULL, *wbuf; struct mnt_idmap *idmap = file_mnt_idmap(fp->filp); - size_t size, v_len; + size_t size; + ssize_t v_len; int err = 0; ksmbd_debug(VFS, "write stream data pos : %llu, count : %zd\n", @@ -433,14 +433,14 @@ fp->stream.name, fp->stream.size, &stream_buf); - if ((int)v_len < 0) { + if (v_len < 0) { pr_err("not found stream in xattr : %zd\n", v_len); - err = (int)v_len; + err = v_len; goto out; } if (v_len < size) { - wbuf = kvmalloc(size, GFP_KERNEL | __GFP_ZERO); + wbuf = kvzalloc(size, GFP_KERNEL); if (!wbuf) { err = -ENOMEM; goto out; @@ -459,7 +459,8 @@ fp->stream.name, (void *)stream_buf, size, - 0); + 0, + true); if (err < 0) goto out; @@ -516,6 +517,9 @@ } } + /* Reserve lease break for parent dir at closing time */ + fp->reserve_lease_break = true; + /* Do we need to break any of a levelII oplock? */ smb_break_all_levII_oplock(work, fp, 1); @@ -557,6 +561,245 @@ return err; } +#ifdef CONFIG_SMB_INSECURE_SERVER +/** + * smb_check_attrs() - sanitize inode attributes + * @inode: inode + * @attrs: inode attributes + */ +static void smb_check_attrs(struct inode *inode, struct iattr *attrs) +{ + /* sanitize the mode change */ + if (attrs->ia_valid & ATTR_MODE) { + attrs->ia_mode &= S_IALLUGO; + attrs->ia_mode |= (inode->i_mode & ~S_IALLUGO); + } + + /* Revoke setuid/setgid on chown */ + if (!S_ISDIR(inode->i_mode) && + (((attrs->ia_valid & ATTR_UID) && + !uid_eq(attrs->ia_uid, inode->i_uid)) || + ((attrs->ia_valid & ATTR_GID) && + !gid_eq(attrs->ia_gid, inode->i_gid)))) { + attrs->ia_valid |= ATTR_KILL_PRIV; + if (attrs->ia_valid & ATTR_MODE) { + /* we're setting mode too, just clear the s*id bits */ + attrs->ia_mode &= ~S_ISUID; + if (attrs->ia_mode & 0010) + attrs->ia_mode &= ~S_ISGID; + } else { + /* set ATTR_KILL_* bits and let VFS handle it */ + attrs->ia_valid |= (ATTR_KILL_SUID | ATTR_KILL_SGID); + } + } +} + +/** + * ksmbd_vfs_setattr() - vfs helper for smb setattr + * @work: work + * @name: file name + * @fid: file id of open file + * @attrs: inode attributes + * + * Return: 0 on success, otherwise error + */ +int ksmbd_vfs_setattr(struct ksmbd_work *work, const char *name, u64 fid, + struct iattr *attrs) +{ + struct file *filp; + struct dentry *dentry; + struct inode *inode; + struct path path; + bool update_size = false; + int err = 0; + struct ksmbd_file *fp = NULL; + struct mnt_idmap *idmap; + + if (ksmbd_override_fsids(work)) + return -ENOMEM; + + if (name) { + err = kern_path(name, 0, &path); + if (err) { + ksmbd_revert_fsids(work); + ksmbd_debug(VFS, "lookup failed for %s, err = %d\n", + name, err); + return -ENOENT; + } + dentry = path.dentry; + inode = d_inode(dentry); + idmap = mnt_idmap(path.mnt); + } else { + fp = ksmbd_lookup_fd_fast(work, fid); + if (!fp) { + ksmbd_revert_fsids(work); + pr_err("failed to get filp for fid %llu\n", fid); + return -ENOENT; + } + + filp = fp->filp; + dentry = filp->f_path.dentry; + inode = d_inode(dentry); + idmap = file_mnt_idmap(filp); + } + + err = inode_permission(idmap, d_inode(dentry), MAY_WRITE); + if (err) + goto out; + + /* no need to update mode of symlink */ + if (S_ISLNK(inode->i_mode)) + attrs->ia_valid &= ~ATTR_MODE; + + /* skip setattr, if nothing to update */ + if (!attrs->ia_valid) { + err = 0; + goto out; + } + + smb_check_attrs(inode, attrs); + if (attrs->ia_valid & ATTR_SIZE) { + err = get_write_access(inode); + if (err) + goto out; + update_size = true; + } + + attrs->ia_valid |= ATTR_CTIME; + + inode_lock(inode); + err = notify_change(idmap, dentry, attrs, NULL); + inode_unlock(inode); + + if (update_size) + put_write_access(inode); + + if (!err) { + sync_inode_metadata(inode, 1); + ksmbd_debug(VFS, "fid %llu, setattr done\n", fid); + } + +out: + if (name) + path_put(&path); + ksmbd_fd_put(work, fp); + ksmbd_revert_fsids(work); + return err; +} + +/** + * ksmbd_vfs_symlink() - vfs helper for creating smb symlink + * @name: source file name + * @symname: symlink name + * + * Return: 0 on success, otherwise error + */ +int ksmbd_vfs_symlink(struct ksmbd_work *work, const char *name, + const char *symname) +{ + struct path path; + struct dentry *dentry; + int err; + + if (ksmbd_override_fsids(work)) + return -ENOMEM; + + dentry = kern_path_create(AT_FDCWD, symname, &path, 0); + if (IS_ERR(dentry)) { + ksmbd_revert_fsids(work); + err = PTR_ERR(dentry); + pr_err("path create failed for %s, err %d\n", name, err); + return err; + } + + err = vfs_symlink(mnt_idmap(path.mnt), d_inode(dentry->d_parent), dentry, name); + if (err && (err != -EEXIST || err != -ENOSPC)) + ksmbd_debug(VFS, "failed to create symlink, err %d\n", err); + + done_path_create(&path, dentry); + ksmbd_revert_fsids(work); + return err; +} + +/** + * ksmbd_vfs_readlink() - vfs helper for reading value of symlink + * @path: path of symlink + * @buf: destination buffer for symlink value + * @lenp: destination buffer length + * + * Return: symlink value length on success, otherwise error + */ +int ksmbd_vfs_readlink(struct path *path, char *buf, int lenp) +{ + struct inode *inode; + int err; + const char *link; + DEFINE_DELAYED_CALL(done); + int len; + + if (!path) + return -ENOENT; + + inode = d_inode(path->dentry); + if (!S_ISLNK(inode->i_mode)) + return -EINVAL; + + link = vfs_get_link(path->dentry, &done); + if (IS_ERR(link)) { + err = PTR_ERR(link); + pr_err("readlink failed, err = %d\n", err); + return err; + } + + len = strlen(link); + if (len > lenp) + len = lenp; + + memcpy(buf, link, len); + do_delayed_call(&done); + + return len; +} + +int ksmbd_vfs_readdir_name(struct ksmbd_work *work, + struct mnt_idmap *idmap, + struct ksmbd_kstat *ksmbd_kstat, + const char *de_name, int de_name_len, + const char *dir_path) +{ + struct path parent_path, path; + int rc, file_pathlen, dir_pathlen; + char *name; + + dir_pathlen = strlen(dir_path); + /* 1 for '/'*/ + file_pathlen = dir_pathlen + de_name_len + 1; + name = kmalloc(file_pathlen + 1, GFP_KERNEL); + if (!name) + return -ENOMEM; + + memcpy(name, dir_path, dir_pathlen); + memset(name + dir_pathlen, '/', 1); + memcpy(name + dir_pathlen + 1, de_name, de_name_len); + name[file_pathlen] = '\0'; + + rc = ksmbd_vfs_kern_path_locked(work, name, LOOKUP_NO_SYMLINKS, + &parent_path, &path, true); + if (rc) { + pr_err("lookup failed: %s [%d]\n", name, rc); + kfree(name); + return -ENOMEM; + } + + ksmbd_vfs_fill_dentry_attrs(work, idmap, path.dentry, ksmbd_kstat); + inode_unlock(d_inode(parent_path.dentry)); + path_put(&path); + path_put(&parent_path); + kfree(name); + return 0; +} +#endif + /** * ksmbd_vfs_fsync() - vfs helper for smb fsync * @work: work @@ -601,10 +844,6 @@ goto out_err; } - err = mnt_want_write(path->mnt); - if (err) - goto out_err; - idmap = mnt_idmap(path->mnt); if (S_ISDIR(d_inode(path->dentry)->i_mode)) { err = vfs_rmdir(idmap, d_inode(parent), path->dentry); @@ -615,7 +854,6 @@ if (err) ksmbd_debug(VFS, "unlink failed, err %d\n", err); } - mnt_drop_write(path->mnt); out_err: ksmbd_revert_fsids(work); @@ -661,16 +899,11 @@ goto out3; } - err = mnt_want_write(newpath.mnt); - if (err) - goto out3; - err = vfs_link(oldpath.dentry, mnt_idmap(newpath.mnt), d_inode(newpath.dentry), dentry, NULL); if (err) ksmbd_debug(VFS, "vfs_link failed err %d\n", err); - mnt_drop_write(newpath.mnt); out3: done_path_create(&newpath, dentry); @@ -728,7 +961,7 @@ goto out3; } - parent_fp = ksmbd_lookup_fd_inode(d_inode(old_child->d_parent)); + parent_fp = ksmbd_lookup_fd_inode(old_child->d_parent); if (parent_fp) { if (parent_fp->daccess & FILE_DELETE_LE) { pr_err("parent dir is opened with delete access\n"); @@ -751,10 +984,13 @@ goto out4; } + /* explicitly handle file overwrite case, for compatibility with + * filesystems that may not support rename flags (e.g: fuse) */ if ((flags & RENAME_NOREPLACE) && d_is_positive(new_dentry)) { err = -EEXIST; goto out4; } + flags &= ~(RENAME_NOREPLACE); if (old_child == trap) { err = -EINVAL; @@ -857,7 +1093,7 @@ if (size <= 0) return size; - vlist = kvmalloc(size, GFP_KERNEL | __GFP_ZERO); + vlist = kvzalloc(size, GFP_KERNEL); if (!vlist) return -ENOMEM; @@ -920,18 +1156,22 @@ * @attr_value: xattr value to set * @attr_size: size of xattr value * @flags: destination buffer length + * @get_write: get write access to a mount * * Return: 0 on success, otherwise error */ int ksmbd_vfs_setxattr(struct mnt_idmap *idmap, const struct path *path, const char *attr_name, - void *attr_value, size_t attr_size, int flags) + void *attr_value, size_t attr_size, int flags, + bool get_write) { int err; + if (get_write == true) { err = mnt_want_write(path->mnt); if (err) return err; + } err = vfs_setxattr(idmap, path->dentry, @@ -941,10 +1181,43 @@ flags); if (err) ksmbd_debug(VFS, "setxattr failed, err %d\n", err); + if (get_write == true) mnt_drop_write(path->mnt); return err; } +#ifdef CONFIG_SMB_INSECURE_SERVER +int ksmbd_vfs_fsetxattr(struct ksmbd_work *work, const char *filename, + const char *attr_name, const void *attr_value, + size_t attr_size, int flags) +{ + struct path path; + int err; + + if (ksmbd_override_fsids(work)) + return -ENOMEM; + + err = kern_path(filename, 0, &path); + if (err) { + ksmbd_revert_fsids(work); + ksmbd_debug(VFS, "cannot get linux path %s, err %d\n", + filename, err); + return err; + } + + err = vfs_setxattr(mnt_idmap(path.mnt), path.dentry, + attr_name, + attr_value, + attr_size, + flags); + if (err) + ksmbd_debug(VFS, "setxattr failed, err %d\n", err); + path_put(&path); + ksmbd_revert_fsids(work); + return err; +} +#endif + /** * ksmbd_vfs_set_fadvise() - convert smb IO caching options to linux options * @filp: file pointer for IO @@ -1091,6 +1364,63 @@ return err; } +#ifdef CONFIG_SMB_INSECURE_SERVER +/** + * ksmbd_vfs_dentry_open() - open a dentry and provide fid for it + * @work: smb work ptr + * @path: path of dentry to be opened + * @flags: open flags + * @ret_id: fid returned on this + * @option: file access pattern options for fadvise + * @fexist: file already present or not + * + * Return: allocated struct ksmbd_file on success, otherwise error pointer + */ +struct ksmbd_file *ksmbd_vfs_dentry_open(struct ksmbd_work *work, + const struct path *path, int flags, + __le32 option, int fexist) +{ + struct file *filp; + int err = 0; + struct ksmbd_file *fp = NULL; + + filp = dentry_open(path, flags | O_LARGEFILE, current_cred()); + if (IS_ERR(filp)) { + err = PTR_ERR(filp); + pr_err("dentry open failed, err %d\n", err); + return ERR_PTR(err); + } + + ksmbd_vfs_set_fadvise(filp, option); + + fp = ksmbd_open_fd(work, filp); + if (IS_ERR(fp)) { + fput(filp); + err = PTR_ERR(fp); + pr_err("id insert failed\n"); + goto err_out; + } + + if (flags & O_TRUNC) { + if (fexist) + smb_break_all_oplock(work, fp); + err = vfs_truncate((struct path *)path, 0); + if (err) + goto err_out; + } + return fp; + +err_out: + if (!IS_ERR(fp)) + ksmbd_close_fd(work, fp->volatile_id); + if (err) { + fp = ERR_PTR(err); + pr_err("err : %d\n", err); + } + return fp; +} +#endif + static bool __dir_empty(struct dir_context *ctx, const char *name, int namlen, loff_t offset, u64 ino, unsigned int d_type) { @@ -1198,16 +1528,16 @@ * Return: 0 on success, otherwise error */ int ksmbd_vfs_kern_path_locked(struct ksmbd_work *work, char *name, - unsigned int flags, struct path *path, - bool caseless) + unsigned int flags, struct path *parent_path, + struct path *path, bool caseless) { struct ksmbd_share_config *share_conf = work->tcon->share_conf; int err; - struct path parent_path; - err = ksmbd_vfs_path_lookup_locked(share_conf, name, flags, path); + err = ksmbd_vfs_path_lookup_locked(share_conf, name, flags, parent_path, + path); if (!err) - return err; + return 0; if (caseless) { char *filepath; @@ -1220,10 +1550,10 @@ path_len = strlen(filepath); remain_len = path_len; - parent_path = share_conf->vfs_path; - path_get(&parent_path); + *parent_path = share_conf->vfs_path; + path_get(parent_path); - while (d_can_lookup(parent_path.dentry)) { + while (d_can_lookup(parent_path->dentry)) { char *filename = filepath + path_len - remain_len; char *next = strchrnul(filename, '/'); size_t filename_len = next - filename; @@ -1232,7 +1562,7 @@ if (filename_len == 0) break; - err = ksmbd_vfs_lookup_in_dir(&parent_path, filename, + err = ksmbd_vfs_lookup_in_dir(parent_path, filename, filename_len, work->conn->um); if (err) @@ -1249,8 +1579,8 @@ goto out2; else if (is_last) goto out1; - path_put(&parent_path); - parent_path = *path; + path_put(parent_path); + *parent_path = *path; next[0] = '/'; remain_len -= filename_len + 1; @@ -1258,20 +1588,36 @@ err = -EINVAL; out2: - path_put(&parent_path); + path_put(parent_path); out1: kfree(filepath); } if (!err) { - err = ksmbd_vfs_lock_parent(parent_path.dentry, path->dentry); - if (err) - dput(path->dentry); - path_put(&parent_path); + err = mnt_want_write(parent_path->mnt); + if (err) { + path_put(path); + path_put(parent_path); + return err; + } + + err = ksmbd_vfs_lock_parent(parent_path->dentry, path->dentry); + if (err) { + path_put(path); + path_put(parent_path); + } } return err; } +void ksmbd_vfs_kern_path_unlock(struct path *parent_path, struct path *path) +{ + inode_unlock(d_inode(parent_path->dentry)); + mnt_drop_write(parent_path->mnt); + path_put(path); + path_put(parent_path); +} + struct dentry *ksmbd_vfs_kern_path_create(struct ksmbd_work *work, const char *name, unsigned int flags, @@ -1426,7 +1772,8 @@ int ksmbd_vfs_set_sd_xattr(struct ksmbd_conn *conn, struct mnt_idmap *idmap, const struct path *path, - struct smb_ntsd *pntsd, int len) + struct smb_ntsd *pntsd, int len, + bool get_write) { int rc; struct ndr sd_ndr = {0}, acl_ndr = {0}; @@ -1486,7 +1833,7 @@ rc = ksmbd_vfs_setxattr(idmap, path, XATTR_NAME_SD, sd_ndr.data, - sd_ndr.offset, 0); + sd_ndr.offset, 0, get_write); if (rc < 0) pr_err("Failed to store XATTR ntacl :%d\n", rc); @@ -1575,7 +1922,8 @@ int ksmbd_vfs_set_dos_attrib_xattr(struct mnt_idmap *idmap, const struct path *path, - struct xattr_dos_attrib *da) + struct xattr_dos_attrib *da, + bool get_write) { struct ndr n; int err; @@ -1585,7 +1933,7 @@ return err; err = ksmbd_vfs_setxattr(idmap, path, XATTR_NAME_DOS_ATTRIBUTE, - (void *)n.data, n.offset, 0); + (void *)n.data, n.offset, 0, get_write); if (err) ksmbd_debug(SMB, "failed to store dos attribute in xattr\n"); kfree(n.data); @@ -1651,10 +1999,19 @@ struct dentry *dentry, struct ksmbd_kstat *ksmbd_kstat) { + struct ksmbd_share_config *share_conf = work->tcon->share_conf; u64 time; int rc; + struct path path = { + .mnt = share_conf->vfs_path.mnt, + .dentry = dentry, + }; - generic_fillattr(idmap, d_inode(dentry), ksmbd_kstat->kstat); + rc = vfs_getattr(&path, ksmbd_kstat->kstat, + STATX_BASIC_STATS | STATX_BTIME, + AT_STATX_SYNC_AS_STAT); + if (rc) + return rc; time = ksmbd_UnixTimeToNT(ksmbd_kstat->kstat->ctime); ksmbd_kstat->create_time = time; @@ -1856,10 +2213,6 @@ } posix_state_to_acl(&acl_state, acls->a_entries); - rc = mnt_want_write(path->mnt); - if (rc) - goto out_err; - rc = set_posix_acl(idmap, dentry, ACL_TYPE_ACCESS, acls); if (rc < 0) ksmbd_debug(SMB, "Set posix acl(ACL_TYPE_ACCESS) failed, rc : %d\n", @@ -1871,9 +2224,7 @@ ksmbd_debug(SMB, "Set posix acl(ACL_TYPE_DEFAULT) failed, rc : %d\n", rc); } - mnt_drop_write(path->mnt); -out_err: free_acl_state(&acl_state); posix_acl_release(acls); return rc; @@ -1903,10 +2254,6 @@ } } - rc = mnt_want_write(path->mnt); - if (rc) - goto out_err; - rc = set_posix_acl(idmap, dentry, ACL_TYPE_ACCESS, acls); if (rc < 0) ksmbd_debug(SMB, "Set posix acl(ACL_TYPE_ACCESS) failed, rc : %d\n", @@ -1918,9 +2265,7 @@ ksmbd_debug(SMB, "Set posix acl(ACL_TYPE_DEFAULT) failed, rc : %d\n", rc); } - mnt_drop_write(path->mnt); -out_err: posix_acl_release(acls); return rc; } diff -ruw linux-6.4/fs/smb/server/vfs.h linux-6.4-fbx/fs/smb/server/vfs.h --- linux-6.4/fs/smb/server/vfs.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/vfs.h 2024-01-25 13:36:32.722984777 +0100 @@ -39,6 +39,9 @@ struct ksmbd_dir_info { const char *name; +#ifdef CONFIG_SMB_INSECURE_SERVER + char *smb1_name; +#endif char *wptr; char *rptr; int name_len; @@ -72,12 +75,12 @@ }; int ksmbd_vfs_lock_parent(struct dentry *parent, struct dentry *child); -int ksmbd_vfs_query_maximal_access(struct mnt_idmap *idmap, +void ksmbd_vfs_query_maximal_access(struct mnt_idmap *idmap, struct dentry *dentry, __le32 *daccess); int ksmbd_vfs_create(struct ksmbd_work *work, const char *name, umode_t mode); int ksmbd_vfs_mkdir(struct ksmbd_work *work, const char *name, umode_t mode); -int ksmbd_vfs_read(struct ksmbd_work *work, struct ksmbd_file *fp, - size_t count, loff_t *pos); +int ksmbd_vfs_read(struct ksmbd_work *work, struct ksmbd_file *fp, size_t count, + loff_t *pos, char *rbuf); int ksmbd_vfs_write(struct ksmbd_work *work, struct ksmbd_file *fp, char *buf, size_t count, loff_t *pos, bool sync, ssize_t *written); @@ -86,6 +89,24 @@ int ksmbd_vfs_link(struct ksmbd_work *work, const char *oldname, const char *newname); int ksmbd_vfs_getattr(const struct path *path, struct kstat *stat); +#ifdef CONFIG_SMB_INSECURE_SERVER +struct ksmbd_file *ksmbd_vfs_dentry_open(struct ksmbd_work *work, + const struct path *path, int flags, + __le32 option, int fexist); +int ksmbd_vfs_setattr(struct ksmbd_work *work, const char *name, + u64 fid, struct iattr *attrs); +int ksmbd_vfs_fsetxattr(struct ksmbd_work *work, const char *filename, + const char *attr_name, const void *attr_value, + size_t attr_size, int flags); +int ksmbd_vfs_symlink(struct ksmbd_work *work, + const char *name, const char *symname); +int ksmbd_vfs_readlink(struct path *path, char *buf, int lenp); +int ksmbd_vfs_readdir_name(struct ksmbd_work *work, + struct mnt_idmap *idmap, + struct ksmbd_kstat *ksmbd_kstat, + const char *de_name, int de_name_len, + const char *dir_path); +#endif int ksmbd_vfs_rename(struct ksmbd_work *work, const struct path *old_path, char *newname, int flags); int ksmbd_vfs_truncate(struct ksmbd_work *work, @@ -109,14 +130,16 @@ int attr_name_len); int ksmbd_vfs_setxattr(struct mnt_idmap *idmap, const struct path *path, const char *attr_name, - void *attr_value, size_t attr_size, int flags); + void *attr_value, size_t attr_size, int flags, + bool get_write); int ksmbd_vfs_xattr_stream_name(char *stream_name, char **xattr_stream_name, size_t *xattr_stream_name_size, int s_type); int ksmbd_vfs_remove_xattr(struct mnt_idmap *idmap, const struct path *path, char *attr_name); int ksmbd_vfs_kern_path_locked(struct ksmbd_work *work, char *name, - unsigned int flags, struct path *path, - bool caseless); + unsigned int flags, struct path *parent_path, + struct path *path, bool caseless); +void ksmbd_vfs_kern_path_unlock(struct path *parent_path, struct path *path); struct dentry *ksmbd_vfs_kern_path_create(struct ksmbd_work *work, const char *name, unsigned int flags, @@ -144,14 +167,16 @@ int ksmbd_vfs_set_sd_xattr(struct ksmbd_conn *conn, struct mnt_idmap *idmap, const struct path *path, - struct smb_ntsd *pntsd, int len); + struct smb_ntsd *pntsd, int len, + bool get_write); int ksmbd_vfs_get_sd_xattr(struct ksmbd_conn *conn, struct mnt_idmap *idmap, struct dentry *dentry, struct smb_ntsd **pntsd); int ksmbd_vfs_set_dos_attrib_xattr(struct mnt_idmap *idmap, const struct path *path, - struct xattr_dos_attrib *da); + struct xattr_dos_attrib *da, + bool get_write); int ksmbd_vfs_get_dos_attrib_xattr(struct mnt_idmap *idmap, struct dentry *dentry, struct xattr_dos_attrib *da); diff -ruw linux-6.4/fs/smb/server/vfs_cache.c linux-6.4-fbx/fs/smb/server/vfs_cache.c --- linux-6.4/fs/smb/server/vfs_cache.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/vfs_cache.c 2024-01-25 13:36:32.722984777 +0100 @@ -66,14 +66,14 @@ return tmp & inode_hash_mask; } -static struct ksmbd_inode *__ksmbd_inode_lookup(struct inode *inode) +static struct ksmbd_inode *__ksmbd_inode_lookup(struct dentry *de) { struct hlist_head *head = inode_hashtable + - inode_hash(inode->i_sb, inode->i_ino); + inode_hash(d_inode(de)->i_sb, (unsigned long)de); struct ksmbd_inode *ci = NULL, *ret_ci = NULL; hlist_for_each_entry(ci, head, m_hash) { - if (ci->m_inode == inode) { + if (ci->m_de == de) { if (atomic_inc_not_zero(&ci->m_count)) ret_ci = ci; break; @@ -84,29 +84,30 @@ static struct ksmbd_inode *ksmbd_inode_lookup(struct ksmbd_file *fp) { - return __ksmbd_inode_lookup(file_inode(fp->filp)); + return __ksmbd_inode_lookup(fp->filp->f_path.dentry); } -static struct ksmbd_inode *ksmbd_inode_lookup_by_vfsinode(struct inode *inode) +struct ksmbd_inode *ksmbd_inode_lookup_lock(struct dentry *d) { struct ksmbd_inode *ci; read_lock(&inode_hash_lock); - ci = __ksmbd_inode_lookup(inode); + ci = __ksmbd_inode_lookup(d); read_unlock(&inode_hash_lock); + return ci; } -int ksmbd_query_inode_status(struct inode *inode) +int ksmbd_query_inode_status(struct dentry *dentry) { struct ksmbd_inode *ci; int ret = KSMBD_INODE_STATUS_UNKNOWN; read_lock(&inode_hash_lock); - ci = __ksmbd_inode_lookup(inode); + ci = __ksmbd_inode_lookup(dentry); if (ci) { ret = KSMBD_INODE_STATUS_OK; - if (ci->m_flags & S_DEL_PENDING) + if (ci->m_flags & (S_DEL_PENDING | S_DEL_ON_CLS)) ret = KSMBD_INODE_STATUS_PENDING_DELETE; atomic_dec(&ci->m_count); } @@ -116,7 +117,7 @@ bool ksmbd_inode_pending_delete(struct ksmbd_file *fp) { - return (fp->f_ci->m_flags & S_DEL_PENDING); + return (fp->f_ci->m_flags & (S_DEL_PENDING | S_DEL_ON_CLS)); } void ksmbd_set_inode_pending_delete(struct ksmbd_file *fp) @@ -143,7 +144,7 @@ static void ksmbd_inode_hash(struct ksmbd_inode *ci) { struct hlist_head *b = inode_hashtable + - inode_hash(ci->m_inode->i_sb, ci->m_inode->i_ino); + inode_hash(d_inode(ci->m_de)->i_sb, (unsigned long)ci->m_de); hlist_add_head(&ci->m_hash, b); } @@ -157,7 +158,6 @@ static int ksmbd_inode_init(struct ksmbd_inode *ci, struct ksmbd_file *fp) { - ci->m_inode = file_inode(fp->filp); atomic_set(&ci->m_count, 1); atomic_set(&ci->op_count, 0); atomic_set(&ci->sop_count, 0); @@ -166,6 +166,7 @@ INIT_LIST_HEAD(&ci->m_fp_list); INIT_LIST_HEAD(&ci->m_op_list); rwlock_init(&ci->m_lock); + ci->m_de = fp->filp->f_path.dentry; return 0; } @@ -209,7 +210,7 @@ kfree(ci); } -static void ksmbd_inode_put(struct ksmbd_inode *ci) +void ksmbd_inode_put(struct ksmbd_inode *ci) { if (atomic_dec_and_test(&ci->m_count)) ksmbd_inode_free(ci); @@ -325,6 +326,9 @@ locks_free_lock(smb_lock->fl); kfree(smb_lock); } +#ifdef CONFIG_SMB_INSECURE_SERVER + kfree(fp->filename); +#endif if (ksmbd_stream_fd(fp)) kfree(fp->stream.name); @@ -333,6 +337,9 @@ static struct ksmbd_file *ksmbd_fp_get(struct ksmbd_file *fp) { + if (fp->f_state != FP_INITED) + return NULL; + if (!atomic_inc_not_zero(&fp->refcount)) return NULL; return fp; @@ -382,15 +389,20 @@ return 0; ft = &work->sess->file_table; - read_lock(&ft->lock); + write_lock(&ft->lock); fp = idr_find(ft->idr, id); if (fp) { set_close_state_blocked_works(fp); + if (fp->f_state != FP_INITED) + fp = NULL; + else { + fp->f_state = FP_CLOSED; if (!atomic_dec_and_test(&fp->refcount)) fp = NULL; } - read_unlock(&ft->lock); + } + write_unlock(&ft->lock); if (!fp) return -EINVAL; @@ -480,12 +492,61 @@ return fp; } -struct ksmbd_file *ksmbd_lookup_fd_inode(struct inode *inode) +#ifdef CONFIG_SMB_INSECURE_SERVER +struct ksmbd_file *ksmbd_lookup_fd_filename(struct ksmbd_work *work, char *filename) +{ + struct ksmbd_file *fp = NULL; + unsigned int id; + char *pathname; + + pathname = kmalloc(PATH_MAX, GFP_KERNEL); + if (!pathname) + return NULL; + + read_lock(&work->sess->file_table.lock); + idr_for_each_entry(work->sess->file_table.idr, fp, id) { + char *path = d_path(&fp->filp->f_path, pathname, PATH_MAX); + + if (IS_ERR(path)) + break; + + if (!strcmp(path, filename)) { + fp = ksmbd_fp_get(fp); + break; + } + } + read_unlock(&work->sess->file_table.lock); + + kfree(pathname); + return fp; +} + +int ksmbd_file_table_flush(struct ksmbd_work *work) +{ + struct ksmbd_file *fp = NULL; + unsigned int id; + int ret; + + read_lock(&work->sess->file_table.lock); + idr_for_each_entry(work->sess->file_table.idr, fp,id) { + ret = ksmbd_vfs_fsync(work, fp->volatile_id, KSMBD_NO_FID); + if (ret) + break; + } + read_unlock(&work->sess->file_table.lock); + return ret; +} +#endif + +struct ksmbd_file *ksmbd_lookup_fd_inode(struct dentry *dentry) { struct ksmbd_file *lfp; struct ksmbd_inode *ci; + struct inode *inode = d_inode(dentry); - ci = ksmbd_inode_lookup_by_vfsinode(inode); + read_lock(&inode_hash_lock); + ci = __ksmbd_inode_lookup(dentry); + read_unlock(&inode_hash_lock); if (!ci) return NULL; @@ -527,7 +588,13 @@ idr_preload(GFP_KERNEL); write_lock(&ft->lock); +#ifdef CONFIG_SMB_INSECURE_SERVER + ret = idr_alloc_cyclic(ft->idr, fp, 0, + IS_SMB2(fp->conn) ? INT_MAX - 1 : 0xFFFF, + GFP_NOWAIT); +#else ret = idr_alloc_cyclic(ft->idr, fp, 0, INT_MAX - 1, GFP_NOWAIT); +#endif if (ret >= 0) { id = ret; ret = 0; @@ -570,6 +637,7 @@ fp->tcon = work->tcon; fp->volatile_id = KSMBD_NO_FID; fp->persistent_id = KSMBD_NO_FID; + fp->f_state = FP_NEW; fp->f_ci = ksmbd_inode_get(fp); if (!fp->f_ci) { @@ -591,6 +659,17 @@ return ERR_PTR(ret); } +void ksmbd_update_fstate(struct ksmbd_file_table *ft, struct ksmbd_file *fp, + unsigned int state) +{ + if (!fp) + return; + + write_lock(&ft->lock); + fp->f_state = state; + write_unlock(&ft->lock); +} + static int __close_file_table_ids(struct ksmbd_file_table *ft, struct ksmbd_tree_connect *tcon, diff -ruw linux-6.4/fs/smb/server/vfs_cache.h linux-6.4-fbx/fs/smb/server/vfs_cache.h --- linux-6.4/fs/smb/server/vfs_cache.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/fs/smb/server/vfs_cache.h 2024-01-25 13:36:32.722984777 +0100 @@ -51,7 +51,7 @@ atomic_t op_count; /* opinfo count for streams */ atomic_t sop_count; - struct inode *m_inode; + struct dentry *m_de; unsigned int m_flags; struct hlist_node m_hash; struct list_head m_fp_list; @@ -60,6 +60,12 @@ __le32 m_fattr; }; +enum { + FP_NEW = 0, + FP_INITED, + FP_CLOSED +}; + struct ksmbd_file { struct file *filp; u64 persistent_id; @@ -95,9 +101,25 @@ int durable_timeout; +#ifdef CONFIG_SMB_INSECURE_SERVER + /* for SMB1 */ + int pid; + + /* conflict lock fail count for SMB1 */ + unsigned int cflock_cnt; + /* last lock failure start offset for SMB1 */ + unsigned long long llock_fstart; + + int dirent_offset; + + /* for find_first/find_next */ + char *filename; +#endif /* if ls is happening on directory, below is valid*/ struct ksmbd_readdir_data readdir_data; int dot_dotdot[2]; + unsigned int f_state; + bool reserve_lease_break; }; static inline void set_ctx_actor(struct dir_context *ctx, @@ -131,9 +153,15 @@ struct ksmbd_file *ksmbd_lookup_fd_slow(struct ksmbd_work *work, u64 id, u64 pid); void ksmbd_fd_put(struct ksmbd_work *work, struct ksmbd_file *fp); +struct ksmbd_inode *ksmbd_inode_lookup_lock(struct dentry *d); +void ksmbd_inode_put(struct ksmbd_inode *ci); struct ksmbd_file *ksmbd_lookup_durable_fd(unsigned long long id); struct ksmbd_file *ksmbd_lookup_fd_cguid(char *cguid); -struct ksmbd_file *ksmbd_lookup_fd_inode(struct inode *inode); +#ifdef CONFIG_SMB_INSECURE_SERVER +struct ksmbd_file *ksmbd_lookup_fd_filename(struct ksmbd_work *work, char *filename); +int ksmbd_file_table_flush(struct ksmbd_work *work); +#endif +struct ksmbd_file *ksmbd_lookup_fd_inode(struct dentry *dentry); unsigned int ksmbd_open_durable_fd(struct ksmbd_file *fp); struct ksmbd_file *ksmbd_open_fd(struct ksmbd_work *work, struct file *filp); void ksmbd_close_tree_conn_fds(struct ksmbd_work *work); @@ -142,6 +170,8 @@ int ksmbd_init_global_file_table(void); void ksmbd_free_global_file_table(void); void ksmbd_set_fd_limit(unsigned long limit); +void ksmbd_update_fstate(struct ksmbd_file_table *ft, struct ksmbd_file *fp, + unsigned int state); /* * INODE hash @@ -155,7 +185,7 @@ KSMBD_INODE_STATUS_PENDING_DELETE, }; -int ksmbd_query_inode_status(struct inode *inode); +int ksmbd_query_inode_status(struct dentry *dentry); bool ksmbd_inode_pending_delete(struct ksmbd_file *fp); void ksmbd_set_inode_pending_delete(struct ksmbd_file *fp); void ksmbd_clear_inode_pending_delete(struct ksmbd_file *fp); diff -ruw linux-6.4/include/asm-generic/vmlinux.lds.h linux-6.4-fbx/include/asm-generic/vmlinux.lds.h --- linux-6.4/include/asm-generic/vmlinux.lds.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/asm-generic/vmlinux.lds.h 2023-06-27 11:47:16.059866727 +0200 @@ -350,7 +350,7 @@ #define KERNEL_DTB() \ STRUCT_ALIGN(); \ __dtb_start = .; \ - KEEP(*(.dtb.init.rodata)) \ + KEEP(*(.dtb.rodata)) \ __dtb_end = .; /* @@ -462,6 +462,7 @@ . = ALIGN((align)); \ .rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \ __start_rodata = .; \ + KERNEL_DTB() \ *(.rodata) *(.rodata.*) \ SCHED_DATA \ RO_AFTER_INIT_DATA /* Read only after init */ \ @@ -703,7 +704,6 @@ TIMER_OF_TABLES() \ CPU_METHOD_OF_TABLES() \ CPUIDLE_METHOD_OF_TABLES() \ - KERNEL_DTB() \ IRQCHIP_OF_MATCH_TABLE() \ ACPI_PROBE_TABLE(irqchip) \ ACPI_PROBE_TABLE(timer) \ diff -ruw linux-6.4/include/dt-bindings/input/linux-event-codes.h linux-6.4-fbx/include/dt-bindings/input/linux-event-codes.h --- linux-6.4/include/dt-bindings/input/linux-event-codes.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/dt-bindings/input/linux-event-codes.h 2023-05-22 20:06:44.879870719 +0200 @@ -803,6 +803,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff diff -ruw linux-6.4/include/linux/brcmphy.h linux-6.4-fbx/include/linux/brcmphy.h --- linux-6.4/include/linux/brcmphy.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/brcmphy.h 2023-05-22 20:06:44.511860930 +0200 @@ -34,6 +34,10 @@ #define PHY_ID_BCM72113 0x35905310 #define PHY_ID_BCM72116 0x35905350 #define PHY_ID_BCM72165 0x35905340 + +#define PHY_ID_BCM63138 0x600d85c0 +#define PHY_ID_BCM63138S 0x0143bff0 + #define PHY_ID_BCM7250 0xae025280 #define PHY_ID_BCM7255 0xae025120 #define PHY_ID_BCM7260 0xae025190 @@ -56,6 +60,8 @@ #define PHY_ID_BCM_CYGNUS 0xae025200 #define PHY_ID_BCM_OMEGA 0xae025100 +#define PHY_ID_BCM63158 0xae0251c1 + #define PHY_BCM_OUI_MASK 0xfffffc00 #define PHY_BCM_OUI_1 0x00206000 #define PHY_BCM_OUI_2 0x0143bc00 diff -ruw linux-6.4/include/linux/compiler_attributes.h linux-6.4-fbx/include/linux/compiler_attributes.h --- linux-6.4/include/linux/compiler_attributes.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/compiler_attributes.h 2023-11-07 13:38:44.050256364 +0100 @@ -89,6 +89,19 @@ #endif /* + * Optional: only supported since gcc >= 14 + * Optional: only supported since clang >= 18 + * + * gcc: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108896 + * clang: https://reviews.llvm.org/D148381 + */ +#if __has_attribute(__counted_by__) +# define __counted_by(member) __attribute__((__counted_by__(member))) +#else +# define __counted_by(member) +#endif + +/* * Optional: not supported by gcc * Optional: only supported since clang >= 14.0 * diff -ruw linux-6.4/include/linux/ethtool.h linux-6.4-fbx/include/linux/ethtool.h --- linux-6.4/include/linux/ethtool.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/ethtool.h 2023-05-31 17:11:03.421680714 +0200 @@ -912,6 +912,15 @@ int (*set_mm)(struct net_device *dev, struct ethtool_mm_cfg *cfg, struct netlink_ext_ack *extack); void (*get_mm_stats)(struct net_device *dev, struct ethtool_mm_stats *stats); + int (*set_shaper_param)(struct net_device *, + const struct ethtool_shaper_params *); + int (*get_shaper_param)(struct net_device *, + struct ethtool_shaper_params *); + int (*get_epon_param)(struct net_device *, + struct ethtool_epon_param *); + int (*set_epon_param)(struct net_device *, + const struct ethtool_epon_param *); + struct phylink *(*get_phylink)(struct net_device *); }; int ethtool_check_ops(const struct ethtool_ops *ops); diff -ruw linux-6.4/include/linux/ieee80211.h linux-6.4-fbx/include/linux/ieee80211.h --- linux-6.4/include/linux/ieee80211.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/ieee80211.h 2024-03-18 14:40:14.867741770 +0100 @@ -307,6 +307,13 @@ #define IEEE80211_TRIGGER_TYPE_BQRP 0x6 #define IEEE80211_TRIGGER_TYPE_NFRP 0x7 +/* UL-bandwidth within common_info of trigger frame */ +#define IEEE80211_TRIGGER_ULBW_MASK 0xc0000 +#define IEEE80211_TRIGGER_ULBW_20MHZ 0x0 +#define IEEE80211_TRIGGER_ULBW_40MHZ 0x1 +#define IEEE80211_TRIGGER_ULBW_80MHZ 0x2 +#define IEEE80211_TRIGGER_ULBW_160_80P80MHZ 0x3 + struct ieee80211_hdr { __le16 frame_control; __le16 duration_id; @@ -836,9 +843,14 @@ }; /** - * struct ieee80211_quiet_ie + * struct ieee80211_quiet_ie - Quiet element + * @count: Quiet Count + * @period: Quiet Period + * @duration: Quiet Duration + * @offset: Quiet Offset * - * This structure refers to "Quiet information element" + * This structure represents the payload of the "Quiet element" as + * described in IEEE Std 802.11-2020 section 9.4.2.22. */ struct ieee80211_quiet_ie { u8 count; @@ -848,9 +860,15 @@ } __packed; /** - * struct ieee80211_msrment_ie - * - * This structure refers to "Measurement Request/Report information element" + * struct ieee80211_msrment_ie - Measurement element + * @token: Measurement Token + * @mode: Measurement Report Mode + * @type: Measurement Type + * @request: Measurement Request or Measurement Report + * + * This structure represents the payload of both the "Measurement + * Request element" and the "Measurement Report element" as described + * in IEEE Std 802.11-2020 sections 9.4.2.20 and 9.4.2.21. */ struct ieee80211_msrment_ie { u8 token; @@ -860,9 +878,14 @@ } __packed; /** - * struct ieee80211_channel_sw_ie - * - * This structure refers to "Channel Switch Announcement information element" + * struct ieee80211_channel_sw_ie - Channel Switch Announcement element + * @mode: Channel Switch Mode + * @new_ch_num: New Channel Number + * @count: Channel Switch Count + * + * This structure represents the payload of the "Channel Switch + * Announcement element" as described in IEEE Std 802.11-2020 section + * 9.4.2.18. */ struct ieee80211_channel_sw_ie { u8 mode; @@ -871,9 +894,14 @@ } __packed; /** - * struct ieee80211_ext_chansw_ie + * struct ieee80211_ext_chansw_ie - Extended Channel Switch Announcement element + * @mode: Channel Switch Mode + * @new_operating_class: New Operating Class + * @new_ch_num: New Channel Number + * @count: Channel Switch Count * - * This structure represents the "Extended Channel Switch Announcement element" + * This structure represents the "Extended Channel Switch Announcement + * element" as described in IEEE Std 802.11-2020 section 9.4.2.52. */ struct ieee80211_ext_chansw_ie { u8 mode; @@ -894,8 +922,14 @@ /** * struct ieee80211_mesh_chansw_params_ie - mesh channel switch parameters IE - * - * This structure represents the "Mesh Channel Switch Paramters element" + * @mesh_ttl: Time To Live + * @mesh_flags: Flags + * @mesh_reason: Reason Code + * @mesh_pre_value: Precedence Value + * + * This structure represents the payload of the "Mesh Channel Switch + * Parameters element" as described in IEEE Std 802.11-2020 section + * 9.4.2.102. */ struct ieee80211_mesh_chansw_params_ie { u8 mesh_ttl; @@ -906,6 +940,13 @@ /** * struct ieee80211_wide_bw_chansw_ie - wide bandwidth channel switch IE + * @new_channel_width: New Channel Width + * @new_center_freq_seg0: New Channel Center Frequency Segment 0 + * @new_center_freq_seg1: New Channel Center Frequency Segment 1 + * + * This structure represents the payload of the "Wide Bandwidth + * Channel Switch element" as described in IEEE Std 802.11-2020 + * section 9.4.2.160. */ struct ieee80211_wide_bw_chansw_ie { u8 new_channel_width; @@ -913,22 +954,42 @@ } __packed; /** - * struct ieee80211_tim - * - * This structure refers to "Traffic Indication Map information element" + * struct ieee80211_tim_ie - Traffic Indication Map information element + * @dtim_count: DTIM Count + * @dtim_period: DTIM Period + * @bitmap_ctrl: Bitmap Control + * @required_octet: "Syntatic sugar" to force the struct size to the + * minimum valid size when carried in a non-S1G PPDU + * @virtual_map: Partial Virtual Bitmap + * + * This structure represents the payload of the "TIM element" as + * described in IEEE Std 802.11-2020 section 9.4.2.5. Note that this + * definition is only applicable when the element is carried in a + * non-S1G PPDU. When the TIM is carried in an S1G PPDU, the Bitmap + * Control and Partial Virtual Bitmap may not be present. */ struct ieee80211_tim_ie { u8 dtim_count; u8 dtim_period; u8 bitmap_ctrl; - /* variable size: 1 - 251 bytes */ - u8 virtual_map[1]; + union { + u8 required_octet; + DECLARE_FLEX_ARRAY(u8, virtual_map); + }; } __packed; /** - * struct ieee80211_meshconf_ie + * struct ieee80211_meshconf_ie - Mesh Configuration element + * @meshconf_psel: Active Path Selection Protocol Identifier + * @meshconf_pmetric: Active Path Selection Metric Identifier + * @meshconf_congest: Congestion Control Mode Identifier + * @meshconf_synch: Synchronization Method Identifier + * @meshconf_auth: Authentication Protocol Identifier + * @meshconf_form: Mesh Formation Info + * @meshconf_cap: Mesh Capability (see &enum mesh_config_capab_flags) * - * This structure refers to "Mesh Configuration information element" + * This structure represents the payload of the "Mesh Configuration + * element" as described in IEEE Std 802.11-2020 section 9.4.2.97. */ struct ieee80211_meshconf_ie { u8 meshconf_psel; @@ -950,6 +1011,9 @@ * is ongoing * @IEEE80211_MESHCONF_CAPAB_POWER_SAVE_LEVEL: STA is in deep sleep mode or has * neighbors in deep sleep mode + * + * Enumerates the "Mesh Capability" as described in IEEE Std + * 802.11-2020 section 9.4.2.97.7. */ enum mesh_config_capab_flags { IEEE80211_MESHCONF_CAPAB_ACCEPT_PLINKS = 0x01, @@ -960,7 +1024,7 @@ #define IEEE80211_MESHCONF_FORM_CONNECTED_TO_GATE 0x1 -/** +/* * mesh channel switch parameters element's flag indicator * */ @@ -969,9 +1033,17 @@ #define WLAN_EID_CHAN_SWITCH_PARAM_REASON BIT(2) /** - * struct ieee80211_rann_ie + * struct ieee80211_rann_ie - RANN (root announcement) element + * @rann_flags: Flags + * @rann_hopcount: Hop Count + * @rann_ttl: Element TTL + * @rann_addr: Root Mesh STA Address + * @rann_seq: HWMP Sequence Number + * @rann_interval: Interval + * @rann_metric: Metric * - * This structure refers to "Root Announcement information element" + * This structure represents the payload of the "RANN element" as + * described in IEEE Std 802.11-2020 section 9.4.2.111. */ struct ieee80211_rann_ie { u8 rann_flags; @@ -993,7 +1065,7 @@ }; /** - * enum ieee80211_opmode_bits - VHT operating mode field bits + * enum ieee80211_vht_opmode_bits - VHT operating mode field bits * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_MASK: channel width mask * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_20MHZ: 20 MHz channel width * @IEEE80211_OPMODE_NOTIF_CHANWIDTH_40MHZ: 40 MHz channel width @@ -1042,9 +1114,12 @@ #define WLAN_USER_POSITION_LEN 16 /** - * struct ieee80211_tpc_report_ie + * struct ieee80211_tpc_report_ie - TPC Report element + * @tx_power: Transmit Power + * @link_margin: Link Margin * - * This structure refers to "TPC Report element" + * This structure represents the payload of the "TPC Report element" as + * described in IEEE Std 802.11-2020 section 9.4.2.16. */ struct ieee80211_tpc_report_ie { u8 tx_power; @@ -1062,9 +1137,14 @@ } __packed; /** - * struct ieee80211_s1g_bcn_compat_ie - * - * S1G Beacon Compatibility element + * struct ieee80211_s1g_bcn_compat_ie - S1G Beacon Compatibility element + * @compat_info: Compatibility Information + * @beacon_int: Beacon Interval + * @tsf_completion: TSF Completion + * + * This structure represents the payload of the "S1G Beacon + * Compatibility element" as described in IEEE Std 802.11-2020 section + * 9.4.2.196. */ struct ieee80211_s1g_bcn_compat_ie { __le16 compat_info; @@ -1073,9 +1153,15 @@ } __packed; /** - * struct ieee80211_s1g_oper_ie + * struct ieee80211_s1g_oper_ie - S1G Operation element + * @ch_width: S1G Operation Information Channel Width + * @oper_class: S1G Operation Information Operating Class + * @primary_ch: S1G Operation Information Primary Channel Number + * @oper_ch: S1G Operation Information Channel Center Frequency + * @basic_mcs_nss: Basic S1G-MCS and NSS Set * - * S1G Operation element + * This structure represents the payload of the "S1G Operation + * element" as described in IEEE Std 802.11-2020 section 9.4.2.212. */ struct ieee80211_s1g_oper_ie { u8 ch_width; @@ -1086,9 +1172,13 @@ } __packed; /** - * struct ieee80211_aid_response_ie + * struct ieee80211_aid_response_ie - AID Response element + * @aid: AID/Group AID + * @switch_count: AID Switch Count + * @response_int: AID Response Interval * - * AID Response element + * This structure represents the payload of the "AID Response element" + * as described in IEEE Std 802.11-2020 section 9.4.2.194. */ struct ieee80211_aid_response_ie { __le16 aid; @@ -1163,6 +1253,30 @@ u8 params[]; } __packed; +#define IEEE80211_TTLM_MAX_CNT 2 +#define IEEE80211_TTLM_CONTROL_DIRECTION 0x03 +#define IEEE80211_TTLM_CONTROL_DEF_LINK_MAP 0x04 +#define IEEE80211_TTLM_CONTROL_SWITCH_TIME_PRESENT 0x08 +#define IEEE80211_TTLM_CONTROL_EXPECTED_DUR_PRESENT 0x10 +#define IEEE80211_TTLM_CONTROL_LINK_MAP_SIZE 0x20 + +#define IEEE80211_TTLM_DIRECTION_DOWN 0 +#define IEEE80211_TTLM_DIRECTION_UP 1 +#define IEEE80211_TTLM_DIRECTION_BOTH 2 + +/** + * struct ieee80211_ttlm_elem - TID-To-Link Mapping element + * + * Defined in section 9.4.2.314 in P802.11be_D4 + * + * @control: the first part of control field + * @optional: the second part of control field + */ +struct ieee80211_ttlm_elem { + u8 control; + u8 optional[]; +} __packed; + struct ieee80211_mgmt { __le16 frame_control; __le16 duration; @@ -1349,8 +1463,11 @@ /* Supported rates membership selectors */ #define BSS_MEMBERSHIP_SELECTOR_HT_PHY 127 #define BSS_MEMBERSHIP_SELECTOR_VHT_PHY 126 -#define BSS_MEMBERSHIP_SELECTOR_HE_PHY 122 +#define BSS_MEMBERSHIP_SELECTOR_GLK 125 +#define BSS_MEMBERSHIP_SELECTOR_EPS 124 #define BSS_MEMBERSHIP_SELECTOR_SAE_H2E 123 +#define BSS_MEMBERSHIP_SELECTOR_HE_PHY 122 +#define BSS_MEMBERSHIP_SELECTOR_EHT_PHY 121 /* mgmt header + 1 byte category code */ #define IEEE80211_MIN_ACTION_SIZE offsetof(struct ieee80211_mgmt, u.action.u) @@ -1486,7 +1603,7 @@ /* * Peer-to-Peer IE attribute related definitions. */ -/** +/* * enum ieee80211_p2p_attr_id - identifies type of peer-to-peer attribute. */ enum ieee80211_p2p_attr_id { @@ -1536,10 +1653,16 @@ #define IEEE80211_P2P_OPPPS_CTWINDOW_MASK 0x7F /** - * struct ieee80211_bar - HT Block Ack Request + * struct ieee80211_bar - Block Ack Request frame format + * @frame_control: Frame Control + * @duration: Duration + * @ra: RA + * @ta: TA + * @control: BAR Control + * @start_seq_num: Starting Sequence Number (see Figure 9-37) * - * This structure refers to "HT BlockAckReq" as - * described in 802.11n draft section 7.2.1.7.1 + * This structure represents the "BlockAckReq frame format" + * as described in IEEE Std 802.11-2020 section 9.3.1.7. */ struct ieee80211_bar { __le16 frame_control; @@ -1560,13 +1683,17 @@ #define IEEE80211_HT_MCS_MASK_LEN 10 /** - * struct ieee80211_mcs_info - MCS information + * struct ieee80211_mcs_info - Supported MCS Set field * @rx_mask: RX mask * @rx_highest: highest supported RX rate. If set represents * the highest supported RX data rate in units of 1 Mbps. * If this field is 0 this value should not be used to * consider the highest RX data rate supported. * @tx_params: TX parameters + * @reserved: Reserved bits + * + * This structure represents the "Supported MCS Set field" as + * described in IEEE Std 802.11-2020 section 9.4.2.55.4. */ struct ieee80211_mcs_info { u8 rx_mask[IEEE80211_HT_MCS_MASK_LEN]; @@ -1585,6 +1712,8 @@ #define IEEE80211_HT_MCS_TX_MAX_STREAMS 4 #define IEEE80211_HT_MCS_TX_UNEQUAL_MODULATION 0x10 +#define IEEE80211_HT_MCS_CHAINS(mcs) ((mcs) == 32 ? 1 : (1 + ((mcs) >> 3))) + /* * 802.11n D5.0 20.3.5 / 20.6 says: * - indices 0 to 7 and 32 are single spatial stream @@ -1597,10 +1726,16 @@ (IEEE80211_HT_MCS_UNEQUAL_MODULATION_START / 8) /** - * struct ieee80211_ht_cap - HT capabilities + * struct ieee80211_ht_cap - HT capabilities element + * @cap_info: HT Capability Information + * @ampdu_params_info: A-MPDU Parameters + * @mcs: Supported MCS Set + * @extended_ht_cap_info: HT Extended Capabilities + * @tx_BF_cap_info: Transmit Beamforming Capabilities + * @antenna_selection_info: ASEL Capability * - * This structure is the "HT capabilities element" as - * described in 802.11n D5.0 7.3.2.57 + * This structure represents the payload of the "HT Capabilities + * element" as described in IEEE Std 802.11-2020 section 9.4.2.55. */ struct ieee80211_ht_cap { __le16 cap_info; @@ -1688,9 +1823,14 @@ /** * struct ieee80211_ht_operation - HT operation IE + * @primary_chan: Primary Channel + * @ht_param: HT Operation Information parameters + * @operation_mode: HT Operation Information operation mode + * @stbc_param: HT Operation Information STBC params + * @basic_set: Basic HT-MCS Set * - * This structure is the "HT operation element" as - * described in 802.11n-2009 7.3.2.57 + * This structure represents the payload of the "HT Operation + * element" as described in IEEE Std 802.11-2020 section 9.4.2.56. */ struct ieee80211_ht_operation { u8 primary_chan; @@ -1859,9 +1999,12 @@ /** * struct ieee80211_he_cap_elem - HE capabilities element + * @mac_cap_info: HE MAC Capabilities Information + * @phy_cap_info: HE PHY Capabilities Information * - * This structure is the "HE capabilities element" fixed fields as - * described in P802.11ax_D4.0 section 9.4.2.242.2 and 9.4.2.242.3 + * This structure represents the fixed fields of the payload of the + * "HE capabilities element" as described in IEEE Std 802.11ax-2021 + * sections 9.4.2.248.2 and 9.4.2.248.3. */ struct ieee80211_he_cap_elem { u8 mac_cap_info[6]; @@ -1920,35 +2063,45 @@ } __packed; /** - * struct ieee80211_he_operation - HE capabilities element + * struct ieee80211_he_operation - HE Operation element + * @he_oper_params: HE Operation Parameters + BSS Color Information + * @he_mcs_nss_set: Basic HE-MCS And NSS Set + * @optional: Optional fields VHT Operation Information, Max Co-Hosted + * BSSID Indicator, and 6 GHz Operation Information * - * This structure is the "HE operation element" fields as - * described in P802.11ax_D4.0 section 9.4.2.243 + * This structure represents the payload of the "HE Operation + * element" as described in IEEE Std 802.11ax-2021 section 9.4.2.249. */ struct ieee80211_he_operation { __le32 he_oper_params; __le16 he_mcs_nss_set; - /* Optional 0,1,3,4,5,7 or 8 bytes: depends on @he_oper_params */ u8 optional[]; } __packed; /** - * struct ieee80211_he_spr - HE spatial reuse element - * - * This structure is the "HE spatial reuse element" element as - * described in P802.11ax_D4.0 section 9.4.2.241 + * struct ieee80211_he_spr - Spatial Reuse Parameter Set element + * @he_sr_control: SR Control + * @optional: Optional fields Non-SRG OBSS PD Max Offset, SRG OBSS PD + * Min Offset, SRG OBSS PD Max Offset, SRG BSS Color + * Bitmap, and SRG Partial BSSID Bitmap + * + * This structure represents the payload of the "Spatial Reuse + * Parameter Set element" as described in IEEE Std 802.11ax-2021 + * section 9.4.2.252. */ struct ieee80211_he_spr { u8 he_sr_control; - /* Optional 0 to 19 bytes: depends on @he_sr_control */ u8 optional[]; } __packed; /** * struct ieee80211_he_mu_edca_param_ac_rec - MU AC Parameter Record field + * @aifsn: ACI/AIFSN + * @ecw_min_max: ECWmin/ECWmax + * @mu_edca_timer: MU EDCA Timer * - * This structure is the "MU AC Parameter Record" fields as - * described in P802.11ax_D4.0 section 9.4.2.245 + * This structure represents the "MU AC Parameter Record" as described + * in IEEE Std 802.11ax-2021 section 9.4.2.251, Figure 9-788p. */ struct ieee80211_he_mu_edca_param_ac_rec { u8 aifsn; @@ -1958,9 +2111,14 @@ /** * struct ieee80211_mu_edca_param_set - MU EDCA Parameter Set element + * @mu_qos_info: QoS Info + * @ac_be: MU AC_BE Parameter Record + * @ac_bk: MU AC_BK Parameter Record + * @ac_vi: MU AC_VI Parameter Record + * @ac_vo: MU AC_VO Parameter Record * - * This structure is the "MU EDCA Parameter Set element" fields as - * described in P802.11ax_D4.0 section 9.4.2.245 + * This structure represents the payload of the "MU EDCA Parameter Set + * element" as described in IEEE Std 802.11ax-2021 section 9.4.2.251. */ struct ieee80211_mu_edca_param_set { u8 mu_qos_info; @@ -1993,13 +2151,19 @@ * @rx_tx_mcs13_max_nss: indicates the maximum number of spatial streams * supported for reception and the maximum number of spatial streams * supported for transmission for MCS 12 - 13. + * @rx_tx_max_nss: array of the previous fields for easier loop access */ struct ieee80211_eht_mcs_nss_supp_20mhz_only { + union { + struct { u8 rx_tx_mcs7_max_nss; u8 rx_tx_mcs9_max_nss; u8 rx_tx_mcs11_max_nss; u8 rx_tx_mcs13_max_nss; }; + u8 rx_tx_max_nss[4]; + }; +}; /** * struct ieee80211_eht_mcs_nss_supp_bw - EHT max supported NSS per MCS (except @@ -2018,12 +2182,18 @@ * @rx_tx_mcs13_max_nss: indicates the maximum number of spatial streams * supported for reception and the maximum number of spatial streams * supported for transmission for MCS 12 - 13. + * @rx_tx_max_nss: array of the previous fields for easier loop access */ struct ieee80211_eht_mcs_nss_supp_bw { + union { + struct { u8 rx_tx_mcs9_max_nss; u8 rx_tx_mcs11_max_nss; u8 rx_tx_mcs13_max_nss; }; + u8 rx_tx_max_nss[3]; + }; +}; /** * struct ieee80211_eht_cap_elem_fixed - EHT capabilities fixed data @@ -2075,7 +2245,7 @@ */ struct ieee80211_eht_operation { u8 params; - __le32 basic_mcs_nss; + struct ieee80211_eht_mcs_nss_supp_20mhz_only basic_mcs_nss; u8 optional[]; } __packed; @@ -2162,9 +2332,9 @@ * enum ieee80211_ap_reg_power - regulatory power for a Access Point * * @IEEE80211_REG_UNSET_AP: Access Point has no regulatory power mode - * @IEEE80211_REG_LPI: Indoor Access Point - * @IEEE80211_REG_SP: Standard power Access Point - * @IEEE80211_REG_VLP: Very low power Access Point + * @IEEE80211_REG_LPI_AP: Indoor Access Point + * @IEEE80211_REG_SP_AP: Standard power Access Point + * @IEEE80211_REG_VLP_AP: Very low power Access Point * @IEEE80211_REG_AP_POWER_AFTER_LAST: internal * @IEEE80211_REG_AP_POWER_MAX: maximum value */ @@ -2552,7 +2722,7 @@ #define IEEE80211_6GHZ_CTRL_REG_SP_AP 1 /** - * ieee80211_he_6ghz_oper - HE 6 GHz operation Information field + * struct ieee80211_he_6ghz_oper - HE 6 GHz operation Information field * @primary: primary channel * @control: control flags * @ccfs0: channel center frequency segment 0 @@ -2599,9 +2769,13 @@ }; /** - * struct ieee80211_tx_pwr_env - * - * This structure represents the "Transmit Power Envelope element" + * struct ieee80211_tx_pwr_env - Transmit Power Envelope + * @tx_power_info: Transmit Power Information field + * @tx_power: Maximum Transmit Power field + * + * This structure represents the payload of the "Transmit Power + * Envelope element" as described in IEEE Std 802.11ax-2021 section + * 9.4.2.161 */ struct ieee80211_tx_pwr_env { u8 tx_power_info; @@ -2808,6 +2982,10 @@ #define IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454 2 #define IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK 0x01 +#define IEEE80211_EHT_MAC_CAP1_EHT_TRS 0x02 +#define IEEE80211_EHT_MAC_CAP1_TXOP_SHARE_MODE2 0x04 +#define IEEE80211_EHT_MAC_CAP1_TWO_BQRS_SUPP 0x08 +#define IEEE80211_EHT_MAC_CAP1_EHT_LINK_ADAPTATION_SUPP 0x30 /* EHT PHY capabilities as defined in P802.11be_D2.0 section 9.4.2.313.3 */ #define IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ 0x02 @@ -2856,6 +3034,7 @@ /* Maximum number of supported EHT LTF is split */ #define IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK 0xc0 +#define IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF 0x40 #define IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK 0x07 #define IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK 0x78 @@ -2872,6 +3051,9 @@ #define IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA 0x01 #define IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA 0x02 +#define IEEE80211_EHT_PHY_CAP8_20MHZ_ONLY_CAPS 0x04 +#define IEEE80211_EHT_PHY_CAP8_20MHZ_ONLY_TRIGGER_MUBF_FL_BW_FB_DLMUMIMO 0x08 +#define IEEE80211_EHT_PHY_CAP8_20MHZ_ONLY_MRU_SUPP 0x10 /* * EHT operation channel width as defined in P802.11be_D2.0 section 9.4.2.311 @@ -2918,6 +3100,7 @@ #define IEEE80211_EHT_PPE_THRES_NSS_POS 0 #define IEEE80211_EHT_PPE_THRES_NSS_MASK 0xf #define IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_MASK 0x1f0 +#define IEEE80211_EHT_PPE_THRES_RU_INDEX_BITMASK_POS 4 #define IEEE80211_EHT_PPE_THRES_INFO_PPET_SIZE 3 #define IEEE80211_EHT_PPE_THRES_INFO_HEADER_SIZE 9 @@ -2997,6 +3180,28 @@ return len >= needed; } +#define IEEE80211_BW_IND_DIS_SUBCH_PRESENT BIT(1) + +struct ieee80211_bandwidth_indication { + u8 params; + struct ieee80211_eht_operation_info info; +} __packed; + +static inline bool +ieee80211_bandwidth_indication_size_ok(const u8 *data, u8 len) +{ + const struct ieee80211_bandwidth_indication *bwi = (const void *)data; + + if (len < sizeof(*bwi)) + return false; + + if (bwi->params & IEEE80211_BW_IND_DIS_SUBCH_PRESENT && + len < sizeof(*bwi) + 2) + return false; + + return true; +} + #define LISTEN_INT_USF GENMASK(15, 14) #define LISTEN_INT_UI GENMASK(13, 0) @@ -3454,6 +3659,8 @@ WLAN_EID_EXT_EHT_OPERATION = 106, WLAN_EID_EXT_EHT_MULTI_LINK = 107, WLAN_EID_EXT_EHT_CAPABILITY = 108, + WLAN_EID_EXT_TID_TO_LINK_MAPPING = 109, + WLAN_EID_EXT_BANDWIDTH_INDICATION = 135, }; /* Action category code */ @@ -3493,6 +3700,16 @@ WLAN_ACTION_SPCT_CHL_SWITCH = 4, }; +/* RADIO_MEASUREMENT action code */ +enum ieee80211_radio_measurement_actioncode { + WLAN_ACTION_RADIO_MSR_RM_REQ = 0, + WLAN_ACTION_RADIO_MSR_RM_REP = 1, + WLAN_ACTION_RADIO_MSR_LINK_MSR_REQ = 2, + WLAN_ACTION_RADIO_MSR_LINK_MSR_REP = 3, + WLAN_ACTION_RADIO_MSR_NBOR_REP_REQ = 4, + WLAN_ACTION_RADIO_MSR_NBOR_REP_REP = 5, +}; + /* HT action codes */ enum ieee80211_ht_actioncode { WLAN_HT_ACTION_NOTIFY_CHANWIDTH = 0, @@ -4221,6 +4438,35 @@ } /** + * ieee80211_is_protected_dual_of_public_action - check if skb contains a + * protected dual of public action management frame + * @skb: the skb containing the frame, length will be checked + * + * Return: true if the skb contains a protected dual of public action + * management frame, false otherwise. + */ +static inline bool +ieee80211_is_protected_dual_of_public_action(struct sk_buff *skb) +{ + u8 action; + + if (!ieee80211_is_public_action((void *)skb->data, skb->len) || + skb->len < IEEE80211_MIN_ACTION_SIZE + 1) + return false; + + action = *(u8 *)(skb->data + IEEE80211_MIN_ACTION_SIZE); + + return action != WLAN_PUB_ACTION_20_40_BSS_COEX && + action != WLAN_PUB_ACTION_DSE_REG_LOC_ANN && + action != WLAN_PUB_ACTION_MSMT_PILOT && + action != WLAN_PUB_ACTION_TDLS_DISCOVER_RES && + action != WLAN_PUB_ACTION_LOC_TRACK_NOTI && + action != WLAN_PUB_ACTION_FTM_REQUEST && + action != WLAN_PUB_ACTION_FTM_RESPONSE && + action != WLAN_PUB_ACTION_FILS_DISCOVERY; +} + +/** * _ieee80211_is_group_privacy_action - check if frame is a group addressed * privacy action frame * @hdr: the frame @@ -4291,12 +4537,11 @@ /** * ieee80211_get_tdls_action - get tdls packet action (or -1, if not tdls packet) * @skb: the skb containing the frame, length will not be checked - * @hdr_size: the size of the ieee80211_hdr that starts at skb->data * * This function assumes the frame is a data frame, and that the network header * is in the correct place. */ -static inline int ieee80211_get_tdls_action(struct sk_buff *skb, u32 hdr_size) +static inline int ieee80211_get_tdls_action(struct sk_buff *skb) { if (!skb_is_nonlinear(skb) && skb->len > (skb_network_offset(skb) + 2)) { @@ -4462,7 +4707,7 @@ return (const u8 *)element == (const u8 *)data + datalen; } -/** +/* * RSNX Capabilities: * bits 0-3: Field length (n-1) */ @@ -4477,8 +4722,8 @@ #define IEEE80211_AP_INFO_TBTT_HDR_FILTERED 0x04 #define IEEE80211_AP_INFO_TBTT_HDR_COLOC 0x08 #define IEEE80211_AP_INFO_TBTT_HDR_COUNT 0xF0 -#define IEEE80211_TBTT_INFO_OFFSET_BSSID_BSS_PARAM 9 -#define IEEE80211_TBTT_INFO_OFFSET_BSSID_SSSID_BSS_PARAM 13 +#define IEEE80211_TBTT_INFO_TYPE_TBTT 0 +#define IEEE80211_TBTT_INFO_TYPE_MLD 1 #define IEEE80211_RNR_TBTT_PARAMS_OCT_RECOMMENDED 0x01 #define IEEE80211_RNR_TBTT_PARAMS_SAME_SSID 0x02 @@ -4488,6 +4733,9 @@ #define IEEE80211_RNR_TBTT_PARAMS_PROBE_ACTIVE 0x20 #define IEEE80211_RNR_TBTT_PARAMS_COLOC_AP 0x40 +#define IEEE80211_RNR_TBTT_PARAMS_PSD_NO_LIMIT 127 +#define IEEE80211_RNR_TBTT_PARAMS_PSD_RESERVED -128 + struct ieee80211_neighbor_ap_info { u8 tbtt_info_hdr; u8 tbtt_info_len; @@ -4502,6 +4750,42 @@ IEEE80211_RANGE_PARAMS_MAX_TOTAL_LTF_UNSPECIFIED, }; +/* + * reduced neighbor report, based on Draft P802.11be_D3.0, + * section 9.4.2.170.2. + */ +struct ieee80211_rnr_mld_params { + u8 mld_id; + __le16 params; +} __packed; + +#define IEEE80211_RNR_MLD_PARAMS_LINK_ID 0x000F +#define IEEE80211_RNR_MLD_PARAMS_BSS_CHANGE_COUNT 0x0FF0 +#define IEEE80211_RNR_MLD_PARAMS_UPDATES_INCLUDED 0x1000 +#define IEEE80211_RNR_MLD_PARAMS_DISABLED_LINK 0x2000 + +/* Format of the TBTT information element if it has 7, 8 or 9 bytes */ +struct ieee80211_tbtt_info_7_8_9 { + u8 tbtt_offset; + u8 bssid[ETH_ALEN]; + + /* The following element is optional, structure may not grow */ + u8 bss_params; + s8 psd_20; +} __packed; + +/* Format of the TBTT information element if it has >= 11 bytes */ +struct ieee80211_tbtt_info_ge_11 { + u8 tbtt_offset; + u8 bssid[ETH_ALEN]; + __le32 short_ssid; + + /* The following elements are optional, structure may grow */ + u8 bss_params; + s8 psd_20; + struct ieee80211_rnr_mld_params mld_params; +} __packed; + /* multi-link device */ #define IEEE80211_MLD_MAX_NUM_LINKS 15 @@ -4529,6 +4813,14 @@ #define IEEE80211_MED_SYNC_DELAY_SYNC_OFDM_ED_THRESH 0x0f00 #define IEEE80211_MED_SYNC_DELAY_SYNC_MAX_NUM_TXOPS 0xf000 +/* + * Described in P802.11be_D3.0 + * dot11MSDTimerDuration should default to 5484 (i.e. 171.375) + * dot11MSDOFDMEDthreshold defaults to -72 (i.e. 0) + * dot11MSDTXOPMAX defaults to 1 + */ +#define IEEE80211_MED_SYNC_DELAY_DEFAULT 0x10ac + #define IEEE80211_EML_CAP_EMLSR_SUPP 0x0001 #define IEEE80211_EML_CAP_EMLSR_PADDING_DELAY 0x000e #define IEEE80211_EML_CAP_EMLSR_PADDING_DELAY_0US 0 @@ -4611,15 +4903,12 @@ case IEEE80211_ML_CONTROL_TYPE_BASIC: case IEEE80211_ML_CONTROL_TYPE_PREQ: case IEEE80211_ML_CONTROL_TYPE_TDLS: + case IEEE80211_ML_CONTROL_TYPE_RECONF: /* * The length is the first octet pointed by mle->variable so no * need to add anything */ break; - case IEEE80211_ML_CONTROL_TYPE_RECONF: - if (control & IEEE80211_MLC_RECONF_PRES_MLD_MAC_ADDR) - common += ETH_ALEN; - return common; case IEEE80211_ML_CONTROL_TYPE_PRIO_ACCESS: if (control & IEEE80211_MLC_PRIO_ACCESS_PRES_AP_MLD_MAC_ADDR) common += ETH_ALEN; @@ -4633,6 +4922,95 @@ } /** + * ieee80211_mle_get_bss_param_ch_cnt - returns the BSS parameter change count + * @mle: the basic multi link element + * + * The element is assumed to be of the correct type (BASIC) and big enough, + * this must be checked using ieee80211_mle_type_ok(). + * + * If the BSS parameter change count value can't be found (the presence bit + * for it is clear), 0 will be returned. + */ +static inline u8 +ieee80211_mle_get_bss_param_ch_cnt(const struct ieee80211_multi_link_elem *mle) +{ + u16 control = le16_to_cpu(mle->control); + const u8 *common = mle->variable; + + /* common points now at the beginning of ieee80211_mle_basic_common_info */ + common += sizeof(struct ieee80211_mle_basic_common_info); + + if (!(control & IEEE80211_MLC_BASIC_PRES_BSS_PARAM_CH_CNT)) + return 0; + + if (control & IEEE80211_MLC_BASIC_PRES_LINK_ID) + common += 1; + + return *common; +} + +/** + * ieee80211_mle_get_eml_med_sync_delay - returns the medium sync delay + * @data: pointer to the multi link EHT IE + * + * The element is assumed to be of the correct type (BASIC) and big enough, + * this must be checked using ieee80211_mle_type_ok(). + * + * If the medium synchronization is not present, then the default value is + * returned. + */ +static inline u16 ieee80211_mle_get_eml_med_sync_delay(const u8 *data) +{ + const struct ieee80211_multi_link_elem *mle = (const void *)data; + u16 control = le16_to_cpu(mle->control); + const u8 *common = mle->variable; + + /* common points now at the beginning of ieee80211_mle_basic_common_info */ + common += sizeof(struct ieee80211_mle_basic_common_info); + + if (!(control & IEEE80211_MLC_BASIC_PRES_MED_SYNC_DELAY)) + return IEEE80211_MED_SYNC_DELAY_DEFAULT; + + if (control & IEEE80211_MLC_BASIC_PRES_LINK_ID) + common += 1; + if (control & IEEE80211_MLC_BASIC_PRES_BSS_PARAM_CH_CNT) + common += 1; + + return get_unaligned_le16(common); +} + +/** + * ieee80211_mle_get_eml_cap - returns the EML capability + * @data: pointer to the multi link EHT IE + * + * The element is assumed to be of the correct type (BASIC) and big enough, + * this must be checked using ieee80211_mle_type_ok(). + * + * If the EML capability is not present, 0 will be returned. + */ +static inline u16 ieee80211_mle_get_eml_cap(const u8 *data) +{ + const struct ieee80211_multi_link_elem *mle = (const void *)data; + u16 control = le16_to_cpu(mle->control); + const u8 *common = mle->variable; + + /* common points now at the beginning of ieee80211_mle_basic_common_info */ + common += sizeof(struct ieee80211_mle_basic_common_info); + + if (!(control & IEEE80211_MLC_BASIC_PRES_EML_CAPA)) + return 0; + + if (control & IEEE80211_MLC_BASIC_PRES_LINK_ID) + common += 1; + if (control & IEEE80211_MLC_BASIC_PRES_BSS_PARAM_CH_CNT) + common += 1; + if (control & IEEE80211_MLC_BASIC_PRES_MED_SYNC_DELAY) + common += 2; + + return get_unaligned_le16(common); +} + +/** * ieee80211_mle_size_ok - validate multi-link element size * @data: pointer to the element data * @len: length of the containing element @@ -4700,6 +5078,28 @@ return mle->variable[0] >= common; } +/** + * ieee80211_mle_type_ok - validate multi-link element type and size + * @data: pointer to the element data + * @type: expected type of the element + * @len: length of the containing element + */ +static inline bool ieee80211_mle_type_ok(const u8 *data, u8 type, size_t len) +{ + const struct ieee80211_multi_link_elem *mle = (const void *)data; + u16 control; + + if (!ieee80211_mle_size_ok(data, len)) + return false; + + control = le16_to_cpu(mle->control); + + if (u16_get_bits(control, IEEE80211_ML_CONTROL_TYPE) == type) + return true; + + return false; +} + enum ieee80211_mle_subelems { IEEE80211_MLE_SUBELEM_PER_STA_PROFILE = 0, IEEE80211_MLE_SUBELEM_FRAGMENT = 254, @@ -4722,11 +5122,13 @@ } __packed; /** - * ieee80211_mle_sta_prof_size_ok - validate multi-link element sta profile size + * ieee80211_mle_basic_sta_prof_size_ok - validate basic multi-link element sta + * profile size * @data: pointer to the sub element data * @len: length of the containing sub element */ -static inline bool ieee80211_mle_sta_prof_size_ok(const u8 *data, size_t len) +static inline bool ieee80211_mle_basic_sta_prof_size_ok(const u8 *data, + size_t len) { const struct ieee80211_mle_per_sta_profile *prof = (const void *)data; u16 control; @@ -4746,25 +5148,196 @@ info_len += 8; if (control & IEEE80211_MLE_STA_CONTROL_DTIM_INFO_PRESENT) info_len += 2; - if (control & IEEE80211_MLE_STA_CONTROL_BSS_PARAM_CHANGE_CNT_PRESENT) - info_len += 1; - if (control & IEEE80211_MLE_STA_CONTROL_COMPLETE_PROFILE && - control & IEEE80211_MLE_STA_CONTROL_NSTR_BITMAP_SIZE) { + control & IEEE80211_MLE_STA_CONTROL_NSTR_LINK_PAIR_PRESENT) { if (control & IEEE80211_MLE_STA_CONTROL_NSTR_BITMAP_SIZE) info_len += 2; else info_len += 1; } + if (control & IEEE80211_MLE_STA_CONTROL_BSS_PARAM_CHANGE_CNT_PRESENT) + info_len += 1; return prof->sta_info_len >= info_len && fixed + prof->sta_info_len <= len; } +/** + * ieee80211_mle_basic_sta_prof_bss_param_ch_cnt - get per-STA profile BSS + * parameter change count + * @prof: the per-STA profile, having been checked with + * ieee80211_mle_basic_sta_prof_size_ok() for the correct length + * + * Return: The BSS parameter change count value if present, 0 otherwise. + */ +static inline u8 +ieee80211_mle_basic_sta_prof_bss_param_ch_cnt(const struct ieee80211_mle_per_sta_profile *prof) +{ + u16 control = le16_to_cpu(prof->control); + const u8 *pos = prof->variable; + + if (!(control & IEEE80211_MLE_STA_CONTROL_BSS_PARAM_CHANGE_CNT_PRESENT)) + return 0; + + if (control & IEEE80211_MLE_STA_CONTROL_STA_MAC_ADDR_PRESENT) + pos += 6; + if (control & IEEE80211_MLE_STA_CONTROL_BEACON_INT_PRESENT) + pos += 2; + if (control & IEEE80211_MLE_STA_CONTROL_TSF_OFFS_PRESENT) + pos += 8; + if (control & IEEE80211_MLE_STA_CONTROL_DTIM_INFO_PRESENT) + pos += 2; + if (control & IEEE80211_MLE_STA_CONTROL_COMPLETE_PROFILE && + control & IEEE80211_MLE_STA_CONTROL_NSTR_LINK_PAIR_PRESENT) { + if (control & IEEE80211_MLE_STA_CONTROL_NSTR_BITMAP_SIZE) + pos += 2; + else + pos += 1; + } + + return *pos; +} + +#define IEEE80211_MLE_STA_RECONF_CONTROL_LINK_ID 0x000f +#define IEEE80211_MLE_STA_RECONF_CONTROL_COMPLETE_PROFILE 0x0010 +#define IEEE80211_MLE_STA_RECONF_CONTROL_STA_MAC_ADDR_PRESENT 0x0020 +#define IEEE80211_MLE_STA_RECONF_CONTROL_AP_REM_TIMER_PRESENT 0x0040 +#define IEEE80211_MLE_STA_RECONF_CONTROL_OPERATION_UPDATE_TYPE 0x0780 +#define IEEE80211_MLE_STA_RECONF_CONTROL_OPERATION_PARAMS_PRESENT 0x0800 + +/** + * ieee80211_mle_reconf_sta_prof_size_ok - validate reconfiguration multi-link + * element sta profile size. + * @data: pointer to the sub element data + * @len: length of the containing sub element + */ +static inline bool ieee80211_mle_reconf_sta_prof_size_ok(const u8 *data, + size_t len) +{ + const struct ieee80211_mle_per_sta_profile *prof = (const void *)data; + u16 control; + u8 fixed = sizeof(*prof); + u8 info_len = 1; + + if (len < fixed) + return false; + + control = le16_to_cpu(prof->control); + + if (control & IEEE80211_MLE_STA_RECONF_CONTROL_STA_MAC_ADDR_PRESENT) + info_len += ETH_ALEN; + if (control & IEEE80211_MLE_STA_RECONF_CONTROL_AP_REM_TIMER_PRESENT) + info_len += 2; + if (control & IEEE80211_MLE_STA_RECONF_CONTROL_OPERATION_PARAMS_PRESENT) + info_len += 2; + + return prof->sta_info_len >= info_len && + fixed + prof->sta_info_len - 1 <= len; +} + +static inline bool ieee80211_tid_to_link_map_size_ok(const u8 *data, size_t len) +{ + const struct ieee80211_ttlm_elem *t2l = (const void *)data; + u8 control, fixed = sizeof(*t2l), elem_len = 0; + + if (len < fixed) + return false; + + control = t2l->control; + + if (control & IEEE80211_TTLM_CONTROL_SWITCH_TIME_PRESENT) + elem_len += 2; + if (control & IEEE80211_TTLM_CONTROL_EXPECTED_DUR_PRESENT) + elem_len += 3; + + if (!(control & IEEE80211_TTLM_CONTROL_DEF_LINK_MAP)) { + u8 bm_size; + + elem_len += 1; + if (len < fixed + elem_len) + return false; + + if (control & IEEE80211_TTLM_CONTROL_LINK_MAP_SIZE) + bm_size = 1; + else + bm_size = 2; + + elem_len += hweight8(t2l->optional[0]) * bm_size; + } + + return len >= fixed + elem_len; +} + #define for_each_mle_subelement(_elem, _data, _len) \ if (ieee80211_mle_size_ok(_data, _len)) \ for_each_element(_elem, \ _data + ieee80211_mle_common_size(_data),\ _len - ieee80211_mle_common_size(_data)) +/** + * enum ieee80211_critical_updates - Critical Update (CU) flags + * + * These flags are used to indicate the type of critical update happening + * on a link in an interface. + * + * @IEEE80211_CU_INCLUDE_CSA_ELEM: critical update due to inclusion of a Channel + * Switch Announcement element. + * @IEEE80211_CU_INCLUDE_ECSA_ELEM: critical update due to inclusion of an + * Extended Channel Switch Announcement element. + * @IEEE80211_CU_MODIFY_EDCA_PARAM_ELEM: critical update due to modification of + * the EDCA parameters element. + * @IEEE80211_CU_INCLUDE_QUIET_ELEM: critical update due to inclusion of a Quiet + * element. + * @IEEE80211_CU_MODIFY_DSSS_PARAM_ELEM: critical update due to modification of + * the DSSS Parameter Set. + * @IEEE80211_CU_MODIFY_HT_OPER_ELEM: critical update due to modification of the + * HT Operation element + * @IEEE80211_CU_INCLUDE_WBCS_ELEM: critical update due to inclusion of a Wide + * Bandwidth Channel Switch element. + * @IEEE80211_CU_INCLUDE_CSW_ELEM: critical update due to inclusion of a Channel + * Switch Wrapper element. + * @IEEE80211_CU_INCLUDE_OMN_ELEM: critical update due to inclusion of an + * Operating Mode Notification element. + * @IEEE80211_CU_INCLUDE_Q_CHAN_ELEM: critical update due to inclusion of a + * Quiet Channel element. + * @IEEE80211_CU_MODIFY_VHT_OPER_ELEM: critical update due to modification of the + * VHT Operation element. + * @IEEE80211_CU_MODIFY_HE_OPER_ELEM: critical update due to modification of the + * HE Operation element. + * @IEEE80211_CU_INCLUDE_B_TWT_ELEM: critical update due to inclusion a + * Broadcast TWT element. + * @IEEE80211_CU_INCLUDE_B_TWT_EXIST_ELEM: critical update due to inclusion of a + * Broadcast TWT Parameter Set field in an existing Broadcast TWT element. + * @IEEE80211_CU_INCLUDE_BCCA_ELEM: critical update due to inclusion of the BSS + * Color Change Announcement element. + * @IEEE80211_CU_MODIFY_MU_EDCA_PARAM_ELEM: critical update due to modification + * of the MU EDCA Parameter Set element. + * @IEEE80211_CU_MODIFY_SR_PARAM_ELEM: critical update due to modification of the + * Spatial Reuse Parameter Set element. + * @IEEE80211_CU_MODIFY_UORA_PARAM_ELEM: critical update due to modification of + * the UORA Parameter Set element. + * @IEEE80211_CU_MODIFY_EHT_OPER_ELEM: critical update due to modification of the + * EHT Operation element. + */ +enum ieee80211_critical_updates { + IEEE80211_CU_INCLUDE_CSA_ELEM = 1 << 0, + IEEE80211_CU_INCLUDE_ECSA_ELEM = 1 << 1, + IEEE80211_CU_MODIFY_EDCA_PARAM_ELEM = 1 << 2, + IEEE80211_CU_INCLUDE_QUIET_ELEM = 1 << 3, + IEEE80211_CU_MODIFY_DSSS_PARAM_ELEM = 1 << 4, + IEEE80211_CU_MODIFY_HT_OPER_ELEM = 1 << 5, + IEEE80211_CU_INCLUDE_WBCS_ELEM = 1 << 6, + IEEE80211_CU_INCLUDE_CSW_ELEM = 1 << 7, + IEEE80211_CU_INCLUDE_OMN_ELEM = 1 << 8, + IEEE80211_CU_INCLUDE_Q_CHAN_ELEM = 1 << 9, + IEEE80211_CU_MODIFY_VHT_OPER_ELEM = 1 << 10, + IEEE80211_CU_MODIFY_HE_OPER_ELEM = 1 << 11, + IEEE80211_CU_INCLUDE_B_TWT_ELEM = 1 << 12, + IEEE80211_CU_INCLUDE_B_TWT_EXIST_ELEM = 1 << 13, + IEEE80211_CU_INCLUDE_BCCA_ELEM = 1 << 14, + IEEE80211_CU_MODIFY_MU_EDCA_PARAM_ELEM = 1 << 15, + IEEE80211_CU_MODIFY_SR_PARAM_ELEM = 1 << 16, + IEEE80211_CU_MODIFY_UORA_PARAM_ELEM = 1 << 17, + IEEE80211_CU_MODIFY_EHT_OPER_ELEM = 1 << 18, +}; #endif /* LINUX_IEEE80211_H */ diff -ruw linux-6.4/include/linux/if_vlan.h linux-6.4-fbx/include/linux/if_vlan.h --- linux-6.4/include/linux/if_vlan.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/if_vlan.h 2024-02-08 19:19:27.692597465 +0100 @@ -12,6 +12,7 @@ #include #include #include +#include #define VLAN_HLEN 4 /* The additional bytes required by VLAN * (in addition to the Ethernet header) @@ -144,6 +145,7 @@ int (*action)(struct net_device *dev, int vid, void *arg), void *arg); extern struct net_device *vlan_dev_real_dev(const struct net_device *dev); +extern struct net_device *vlan_dev_upper_dev(const struct net_device *dev); extern u16 vlan_dev_vlan_id(const struct net_device *dev); extern __be16 vlan_dev_vlan_proto(const struct net_device *dev); @@ -213,7 +215,7 @@ mp = vlan_dev_priv(dev)->egress_priority_map[(skprio & 0xF)]; while (mp) { - if (mp->priority == skprio) { + if (mp->priority == (skprio & TC_H_MIN_MASK)) { return mp->vlan_qos; /* This should already be shifted * to mask correctly with the * VLAN's TCI */ @@ -257,6 +259,12 @@ return NULL; } +static inline struct net_device *vlan_dev_upper_dev(const struct net_device *dev) +{ + BUG(); + return NULL; +} + static inline u16 vlan_dev_vlan_id(const struct net_device *dev) { BUG(); @@ -317,6 +325,9 @@ switch (ethertype) { case htons(ETH_P_8021Q): case htons(ETH_P_8021AD): +#ifdef CONFIG_VLAN_FBX + case htons(ETH_P_FBXVLAN): +#endif return true; default: return false; diff -ruw linux-6.4/include/linux/in.h linux-6.4-fbx/include/linux/in.h --- linux-6.4/include/linux/in.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/in.h 2023-02-27 13:36:18.996765333 +0100 @@ -30,6 +30,9 @@ return 0; case IPPROTO_AH: /* SPI */ return 4; + case IPPROTO_IPV6: + /* third byte of ipv6 destination address */ + return 36; default: return -EINVAL; } diff -ruw linux-6.4/include/linux/miscdevice.h linux-6.4-fbx/include/linux/miscdevice.h --- linux-6.4/include/linux/miscdevice.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/miscdevice.h 2023-05-22 20:06:44.603863377 +0200 @@ -21,6 +21,7 @@ #define APOLLO_MOUSE_MINOR 7 /* unused */ #define PC110PAD_MINOR 9 /* unused */ /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ +#define TALDEV_MINOR 74 /* Marvell TAL device */ #define WATCHDOG_MINOR 130 /* Watchdog timer */ #define TEMP_MINOR 131 /* Temperature Sensor */ #define APM_MINOR_DEV 134 diff -ruw linux-6.4/include/linux/mm_types.h linux-6.4-fbx/include/linux/mm_types.h --- linux-6.4/include/linux/mm_types.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/mm_types.h 2024-01-19 17:01:19.897847904 +0100 @@ -123,7 +123,7 @@ */ unsigned long pp_magic; struct page_pool *pp; - unsigned long _pp_mapping_pad; + unsigned long pp_recycle_flag; unsigned long dma_addr; union { /** @@ -398,8 +398,8 @@ */ #define STRUCT_PAGE_MAX_SHIFT (order_base_2(sizeof(struct page))) -#define PAGE_FRAG_CACHE_MAX_SIZE __ALIGN_MASK(32768, ~PAGE_MASK) -#define PAGE_FRAG_CACHE_MAX_ORDER get_order(PAGE_FRAG_CACHE_MAX_SIZE) +#define PAGE_FRAG_CACHE_MAX_ORDER CONFIG_PAGE_FRAG_CACHE_ORDER +#define PAGE_FRAG_CACHE_MAX_SIZE (4096 << PAGE_FRAG_CACHE_MAX_ORDER) /* * page_private can be used on tail pages. However, PagePrivate is only @@ -432,6 +432,7 @@ */ unsigned int pagecnt_bias; bool pfmemalloc; + atomic_t pages_allocated; }; typedef unsigned long vm_flags_t; diff -ruw linux-6.4/include/linux/mtd/mtd.h linux-6.4-fbx/include/linux/mtd/mtd.h --- linux-6.4/include/linux/mtd/mtd.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/mtd/mtd.h 2023-05-22 20:06:44.623863909 +0200 @@ -287,6 +287,13 @@ */ unsigned int bitflip_threshold; + /* NAND related attributes */ + const char *nand_type; + const char *nand_manufacturer; + const char *onfi_model; + uint8_t onfi_ecc_bits; + uint8_t nand_ids[8]; + /* Kernel-only stuff starts here. */ const char *name; int index; diff -ruw linux-6.4/include/linux/mtd/spi-nor.h linux-6.4-fbx/include/linux/mtd/spi-nor.h --- linux-6.4/include/linux/mtd/spi-nor.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/mtd/spi-nor.h 2023-05-22 20:06:44.623863909 +0200 @@ -40,9 +40,11 @@ #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define SPINOR_OP_EWRSR 0x50 /* SST: Enable write to status reg */ #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_RDID_ALT 0x90 /* Read ID (alt) */ #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ @@ -313,6 +315,9 @@ ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len, const u8 *buf); int (*erase)(struct spi_nor *nor, loff_t offs); + + int (*read_alt_id)(struct spi_nor *nor, u8 cmd, u8 *val, int len); + int (*read_atmel_id)(struct spi_nor *nor, u8 cmd, u8 *val, int len); }; /** diff -ruw linux-6.4/include/linux/netdevice.h linux-6.4-fbx/include/linux/netdevice.h --- linux-6.4/include/linux/netdevice.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/netdevice.h 2023-11-07 13:38:44.050256364 +0100 @@ -78,6 +78,20 @@ struct xdp_buff; struct xdp_md; +#ifdef CONFIG_NETRXTHREAD + +#define RXTHREAD_MAX_PKTS 512 +struct krxd { + struct sk_buff_head pkt_queue; + unsigned int stats_pkts; + unsigned int stats_dropped; + wait_queue_head_t wq; + struct task_struct *task; +}; + +extern struct krxd gkrxd[CONFIG_NETRXTHREAD_RX_QUEUE]; +#endif + void synchronize_net(void); void netdev_set_default_ethtool_ops(struct net_device *dev, const struct ethtool_ops *ops); @@ -1743,6 +1757,8 @@ IFF_NO_ADDRCONF = BIT_ULL(30), IFF_TX_SKB_NO_LINEAR = BIT_ULL(31), IFF_CHANGE_PROTO_DOWN = BIT_ULL(32), + IFF_FBXBRIDGE = BIT_ULL(33), + IFF_FBXBRIDGE_PORT = BIT_ULL(34), }; #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN @@ -1776,6 +1792,8 @@ #define IFF_FAILOVER_SLAVE IFF_FAILOVER_SLAVE #define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER #define IFF_TX_SKB_NO_LINEAR IFF_TX_SKB_NO_LINEAR +#define IFF_FBXBRIDGE IFF_FBXBRIDGE +#define IFF_FBXBRIDGE_PORT IFF_FBXBRIDGE_PORT /* Specifies the type of the struct net_device::ml_priv pointer */ enum netdev_ml_priv_type { @@ -4827,13 +4845,6 @@ int skb_csum_hwoffload_help(struct sk_buff *skb, const netdev_features_t features); -struct sk_buff *__skb_gso_segment(struct sk_buff *skb, - netdev_features_t features, bool tx_path); -struct sk_buff *skb_eth_gso_segment(struct sk_buff *skb, - netdev_features_t features, __be16 type); -struct sk_buff *skb_mac_gso_segment(struct sk_buff *skb, - netdev_features_t features); - struct netdev_bonding_info { ifslave slave; ifbond master; @@ -4856,11 +4867,6 @@ } #endif -static inline -struct sk_buff *skb_gso_segment(struct sk_buff *skb, netdev_features_t features) -{ - return __skb_gso_segment(skb, features, true); -} __be16 skb_network_protocol(struct sk_buff *skb, int *depth); static inline bool can_checksum_protocol(netdev_features_t features, @@ -4987,6 +4993,7 @@ struct net_device *dev, netdev_features_t features); netdev_features_t netif_skb_features(struct sk_buff *skb); +void skb_warn_bad_offload(const struct sk_buff *skb); static inline bool net_gso_ok(netdev_features_t features, int gso_type) { @@ -5035,19 +5042,6 @@ void netif_inherit_tso_max(struct net_device *to, const struct net_device *from); -static inline void skb_gso_error_unwind(struct sk_buff *skb, __be16 protocol, - int pulled_hlen, u16 mac_offset, - int mac_len) -{ - skb->protocol = protocol; - skb->encapsulation = 1; - skb_push(skb, pulled_hlen); - skb_reset_transport_header(skb); - skb->mac_header = mac_offset; - skb->network_header = skb->mac_header + mac_len; - skb->mac_len = mac_len; -} - static inline bool netif_is_macsec(const struct net_device *dev) { return dev->priv_flags & IFF_MACSEC; @@ -5103,6 +5097,16 @@ return dev->priv_flags & IFF_BRIDGE_PORT; } +static inline bool netif_is_fbxbridge_master(const struct net_device *dev) +{ + return dev->priv_flags & IFF_FBXBRIDGE; +} + +static inline bool netif_is_fbxbridge_port(const struct net_device *dev) +{ + return dev->priv_flags & IFF_FBXBRIDGE_PORT; +} + static inline bool netif_is_ovs_master(const struct net_device *dev) { return dev->priv_flags & IFF_OPENVSWITCH; diff -ruw linux-6.4/include/linux/netfilter/nf_conntrack_ftp.h linux-6.4-fbx/include/linux/netfilter/nf_conntrack_ftp.h --- linux-6.4/include/linux/netfilter/nf_conntrack_ftp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/netfilter/nf_conntrack_ftp.h 2023-02-27 19:50:22.648261408 +0100 @@ -22,6 +22,11 @@ u_int16_t seq_aft_nl_num[IP_CT_DIR_MAX]; /* pickup sequence tracking, useful for conntrackd */ u_int16_t flags[IP_CT_DIR_MAX]; +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + unsigned int is_fbxbridge; + unsigned long fbxbridge_remote; + unsigned long fbxbridge_wan; +#endif }; /* For NAT to hook in when we find a packet which describes what other diff -ruw linux-6.4/include/linux/netfilter/nf_conntrack_sip.h linux-6.4-fbx/include/linux/netfilter/nf_conntrack_sip.h --- linux-6.4/include/linux/netfilter/nf_conntrack_sip.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/netfilter/nf_conntrack_sip.h 2023-05-22 20:06:44.631864122 +0200 @@ -5,6 +5,7 @@ #include #include #include +#include #define SIP_PORT 5060 #define SIP_TIMEOUT 3600 @@ -12,7 +13,7 @@ struct nf_ct_sip_master { unsigned int register_cseq; unsigned int invite_cseq; - __be16 forced_dport; + __be16 forced_dport[IP_CT_DIR_ORIGINAL]; }; enum sip_expectation_classes { @@ -30,6 +31,10 @@ enum sip_expectation_classes class; }; +struct nf_ct_sip_expect { + u8 cid_hash[SHA256_DIGEST_SIZE]; +}; + #define SDP_MEDIA_TYPE(__name, __class) \ { \ .name = (__name), \ diff -ruw linux-6.4/include/linux/netfilter/nf_conntrack_tcp.h linux-6.4-fbx/include/linux/netfilter/nf_conntrack_tcp.h --- linux-6.4/include/linux/netfilter/nf_conntrack_tcp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/netfilter/nf_conntrack_tcp.h 2023-02-27 12:58:11.897584734 +0100 @@ -28,6 +28,7 @@ /* For SYN packets while we may be out-of-sync */ u_int8_t last_wscale; /* Last window scaling factor seen */ u_int8_t last_flags; /* Last flags set */ + u_int32_t no_window_track; }; #endif /* _NF_CONNTRACK_TCP_H */ diff -ruw linux-6.4/include/linux/of_fdt.h linux-6.4-fbx/include/linux/of_fdt.h --- linux-6.4/include/linux/of_fdt.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/of_fdt.h 2023-05-22 20:06:44.643864441 +0200 @@ -83,6 +83,7 @@ extern void unflatten_and_copy_device_tree(void); extern void early_init_devtree(void *); extern void early_get_first_memblock_info(void *, phys_addr_t *); +const void *of_fdt_find_compatible_dtb(const char *name); #else /* CONFIG_OF_EARLY_FLATTREE */ static inline void early_init_dt_check_for_usable_mem_range(void) {} static inline int early_init_dt_scan_chosen_stdout(void) { return -ENODEV; } diff -ruw linux-6.4/include/linux/page_owner.h linux-6.4-fbx/include/linux/page_owner.h --- linux-6.4/include/linux/page_owner.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/page_owner.h 2023-05-22 20:06:44.643864441 +0200 @@ -12,6 +12,9 @@ extern void __set_page_owner(struct page *page, unsigned short order, gfp_t gfp_mask); extern void __split_page_owner(struct page *page, unsigned int nr); +extern void __set_page_owner_frag_cache(struct page *page, + unsigned int order, + struct page_frag_cache *nc); extern void __folio_copy_owner(struct folio *newfolio, struct folio *old); extern void __set_page_owner_migrate_reason(struct page *page, int reason); extern void __dump_page_owner(const struct page *page); @@ -36,6 +39,13 @@ if (static_branch_unlikely(&page_owner_inited)) __split_page_owner(page, nr); } +static inline void set_page_owner_frag_cache(struct page *page, + unsigned int order, + struct page_frag_cache *nc) +{ + if (static_branch_unlikely(&page_owner_inited)) + __set_page_owner_frag_cache(page, order, nc); +} static inline void folio_copy_owner(struct folio *newfolio, struct folio *old) { if (static_branch_unlikely(&page_owner_inited)) @@ -59,6 +69,11 @@ unsigned int order, gfp_t gfp_mask) { } +static inline void set_page_owner_frag_cache(struct page *page, + unsigned int order, + struct page_frag_cache *nc) +{ +} static inline void split_page_owner(struct page *page, unsigned short order) { diff -ruw linux-6.4/include/linux/part_stat.h linux-6.4-fbx/include/linux/part_stat.h --- linux-6.4/include/linux/part_stat.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/part_stat.h 2023-05-22 20:06:44.647864548 +0200 @@ -12,6 +12,7 @@ unsigned long merges[NR_STAT_GROUPS]; unsigned long io_ticks; local_t in_flight[2]; + unsigned long io_errors[2]; }; /* diff -ruw linux-6.4/include/linux/pci.h linux-6.4-fbx/include/linux/pci.h --- linux-6.4/include/linux/pci.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/pci.h 2023-06-01 18:16:20.069748352 +0200 @@ -464,12 +464,14 @@ unsigned int no_vf_scan:1; /* Don't scan for VFs after IOV enablement */ unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ + unsigned int sysfs_init_done:1; /* res_attr has been created */ pci_dev_flags_t dev_flags; atomic_t enable_cnt; /* pci_enable_device has been called */ u32 saved_config_space[16]; /* Config space saved at suspend time */ struct hlist_head saved_cap_space; int rom_attr_enabled; /* Display of ROM attribute enabled? */ + struct mutex sysfs_init_lock; /* res_attr has been created */ struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ diff -ruw linux-6.4/include/linux/pci_ids.h linux-6.4-fbx/include/linux/pci_ids.h --- linux-6.4/include/linux/pci_ids.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/pci_ids.h 2023-05-22 20:06:44.651864654 +0200 @@ -1828,6 +1828,7 @@ #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 +#define PCI_DEVICE_ID_PI7C9X20303SL 0xa303 #define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 #define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 diff -ruw linux-6.4/include/linux/phy.h linux-6.4-fbx/include/linux/phy.h --- linux-6.4/include/linux/phy.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/phy.h 2023-05-22 20:30:14.549854255 +0200 @@ -110,6 +110,7 @@ * @PHY_INTERFACE_MODE_XLGMII:40 gigabit media-independent interface * @PHY_INTERFACE_MODE_MOCA: Multimedia over Coax * @PHY_INTERFACE_MODE_QSGMII: Quad SGMII + * @PHY_INTERFACE_MODE_PSGMII: Penta SGMII * @PHY_INTERFACE_MODE_TRGMII: Turbo RGMII * @PHY_INTERFACE_MODE_100BASEX: 100 BaseX * @PHY_INTERFACE_MODE_1000BASEX: 1000 BaseX @@ -123,6 +124,7 @@ * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN + * @PHY_INTERFACE_MODE_10G_QXGMII: USXGMII-M 10G / 4 ports * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -147,6 +149,7 @@ PHY_INTERFACE_MODE_XLGMII, PHY_INTERFACE_MODE_MOCA, PHY_INTERFACE_MODE_QSGMII, + PHY_INTERFACE_MODE_PSGMII, PHY_INTERFACE_MODE_TRGMII, PHY_INTERFACE_MODE_100BASEX, PHY_INTERFACE_MODE_1000BASEX, @@ -162,6 +165,15 @@ PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, + PHY_INTERFACE_MODE_10G_QXGMII, + + PHY_INTERFACE_MODE_1000BASEPX_D, + PHY_INTERFACE_MODE_1000BASEPX_U, + PHY_INTERFACE_MODE_10000BASEPR_D, + PHY_INTERFACE_MODE_10000BASEPR_U, + PHY_INTERFACE_MODE_10000_1000_BASEPRX_D, + PHY_INTERFACE_MODE_10000_1000_BASEPRX_U, + PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -255,6 +267,8 @@ return "moca"; case PHY_INTERFACE_MODE_QSGMII: return "qsgmii"; + case PHY_INTERFACE_MODE_PSGMII: + return "psgmii"; case PHY_INTERFACE_MODE_TRGMII: return "trgmii"; case PHY_INTERFACE_MODE_1000BASEX: @@ -281,6 +295,20 @@ return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; + case PHY_INTERFACE_MODE_10G_QXGMII: + return "10g-qxgmii"; + case PHY_INTERFACE_MODE_1000BASEPX_D: + return "1000base-px-d"; + case PHY_INTERFACE_MODE_1000BASEPX_U: + return "1000base-px-u"; + case PHY_INTERFACE_MODE_10000BASEPR_D: + return "10000base-pr-d"; + case PHY_INTERFACE_MODE_10000BASEPR_U: + return "10000base-pr-u"; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_D: + return "10000_1000base-prx-d"; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + return "10000_1000base-prx-u"; default: return "unknown"; } @@ -420,7 +448,11 @@ /** @reset_post_delay_us: GPIO reset deassert delay in microseconds */ int reset_post_delay_us; /** @reset_gpiod: Reset GPIO descriptor pointer */ - struct gpio_desc *reset_gpiod; + struct gpio_descs *reset_gpiod; + + /* mark non-present phy as present but broken during + * probing */ + bool keep_broken_phy; /** @shared_lock: protect access to the shared element */ struct mutex shared_lock; @@ -1814,6 +1846,7 @@ /* Generic C45 PHY driver */ extern struct phy_driver genphy_c45_driver; +extern struct phy_driver genphy_broken_c45_driver; /* The gen10g_* functions are the old Clause 45 stub */ int gen10g_config_aneg(struct phy_device *phydev); diff -ruw linux-6.4/include/linux/phylink.h linux-6.4-fbx/include/linux/phylink.h --- linux-6.4/include/linux/phylink.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/phylink.h 2023-05-31 17:11:03.421680714 +0200 @@ -584,6 +584,7 @@ void phylink_mac_change(struct phylink *, bool up); void phylink_start(struct phylink *); +void phylink_start_silent(struct phylink *); void phylink_stop(struct phylink *); void phylink_suspend(struct phylink *pl, bool mac_wol); @@ -660,4 +661,12 @@ void phylink_decode_usxgmii_word(struct phylink_link_state *state, uint16_t lpa); +int phylink_set_interface(struct phylink *pl, + phy_interface_t interface, + bool an_enabled); +void phylink_get_interface(struct phylink *pl, + phy_interface_t *interface, + int *an_en, + int *mode); + #endif diff -ruw linux-6.4/include/linux/ppp_channel.h linux-6.4-fbx/include/linux/ppp_channel.h --- linux-6.4/include/linux/ppp_channel.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/ppp_channel.h 2023-05-22 20:06:44.671865186 +0200 @@ -50,6 +50,9 @@ /* Called by the channel when it can send some more data. */ extern void ppp_output_wakeup(struct ppp_channel *); +/* Called by the channel when it want to prevent further transmit on it */ +extern void ppp_output_stop(struct ppp_channel *); + /* Called by the channel to process a received PPP packet. The packet should have just the 2-byte PPP protocol header. */ extern void ppp_input(struct ppp_channel *, struct sk_buff *); diff -ruw linux-6.4/include/linux/pstore.h linux-6.4-fbx/include/linux/pstore.h --- linux-6.4/include/linux/pstore.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/pstore.h 2023-05-22 20:06:44.671865186 +0200 @@ -67,6 +67,7 @@ * @reason: kdump reason for notification * @part: position in a multipart record * @compressed: whether the buffer is compressed + * @old: reflects underlying prz old_zone. * */ struct pstore_record { @@ -83,6 +84,7 @@ enum kmsg_dump_reason reason; unsigned int part; bool compressed; + bool old; }; /** diff -ruw linux-6.4/include/linux/pstore_ram.h linux-6.4-fbx/include/linux/pstore_ram.h --- linux-6.4/include/linux/pstore_ram.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/pstore_ram.h 2023-05-22 20:06:44.671865186 +0200 @@ -29,6 +29,7 @@ struct ramoops_platform_data { unsigned long mem_size; phys_addr_t mem_address; + void *mem_ptr; unsigned int mem_type; unsigned long record_size; unsigned long console_size; diff -ruw linux-6.4/include/linux/regmap.h linux-6.4-fbx/include/linux/regmap.h --- linux-6.4/include/linux/regmap.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/regmap.h 2023-05-22 20:06:44.679865399 +0200 @@ -1704,6 +1704,7 @@ int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq); struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data); +void __iomem *regmap_get_mmio_base_address(struct regmap *map); #else /* diff -ruw linux-6.4/include/linux/sched.h linux-6.4-fbx/include/linux/sched.h --- linux-6.4/include/linux/sched.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/sched.h 2023-05-22 20:06:44.687865612 +0200 @@ -736,6 +736,12 @@ #endif }; +enum task_exec_mode { + EXEC_MODE_DENIED, + EXEC_MODE_ONCE, + EXEC_MODE_UNLIMITED, +}; + struct task_struct { #ifdef CONFIG_THREAD_INFO_IN_TASK /* @@ -762,6 +768,7 @@ /* Per task flags (PF_*), defined further below: */ unsigned int flags; unsigned int ptrace; + enum task_exec_mode exec_mode; #ifdef CONFIG_SMP int on_cpu; diff -ruw linux-6.4/include/linux/sfp.h linux-6.4-fbx/include/linux/sfp.h --- linux-6.4/include/linux/sfp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/sfp.h 2023-05-22 20:06:44.695865825 +0200 @@ -554,6 +554,7 @@ int sfp_get_module_eeprom_by_page(struct sfp_bus *bus, const struct ethtool_module_eeprom *page, struct netlink_ext_ack *extack); +int sfp_get_sfp_state(struct sfp_bus *bus, struct ethtool_sfp_state *st); void sfp_upstream_start(struct sfp_bus *bus); void sfp_upstream_stop(struct sfp_bus *bus); void sfp_bus_put(struct sfp_bus *bus); @@ -606,6 +607,12 @@ { return -EOPNOTSUPP; } + +static inline int sfp_get_sfp_state(struct sfp_bus *the_bus, + struct ethtool_sfp_state *st) +{ + return -EOPNOTSUPP; +} static inline void sfp_upstream_start(struct sfp_bus *bus) { diff -ruw linux-6.4/include/linux/skbuff.h linux-6.4-fbx/include/linux/skbuff.h --- linux-6.4/include/linux/skbuff.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/skbuff.h 2024-01-19 17:01:19.897847904 +0100 @@ -687,6 +687,13 @@ typedef unsigned char *sk_buff_data_t; #endif +enum { + FFN_STATE_INIT = 0, + FFN_STATE_FORWARDABLE, + FFN_STATE_FAST_FORWARDED, + FFN_STATE_INCOMPATIBLE, +}; + /** * DOC: Basic sk_buff geometry * @@ -893,11 +900,22 @@ #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) unsigned long _nfct; #endif + +#if defined(CONFIG_IP_FFN) || defined(CONFIG_IPV6_FFN) + int ffn_state; + int ffn_orig_tos; + __u16 ffn_ff_done, + ffn_ff_dirty_len; +#endif unsigned int len, data_len; __u16 mac_len, hdr_len; +#ifdef CONFIG_NETRXTHREAD + int rxthread_prio; +#endif + /* Following fields are _not_ copied in __copy_skb_header() * Note that queue_mapping is here mostly to fill a hole. */ @@ -3035,6 +3053,10 @@ * get_rps_cpu() for example only access one 64 bytes aligned block : * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) */ +#ifdef CONFIG_NETSKBPAD +#define NET_SKB_PAD CONFIG_NETSKBPAD +#endif + #ifndef NET_SKB_PAD #define NET_SKB_PAD max(32, L1_CACHE_BYTES) #endif @@ -3163,6 +3185,10 @@ void *__netdev_alloc_frag_align(unsigned int fragsz, unsigned int align_mask); +struct page_frag_cache *netdev_frag_cache_get(unsigned int cpu_id); +struct page_frag_cache *napi_frag_cache_get(unsigned int cpu_id); + + /** * netdev_alloc_frag - allocate a page fragment * @fragsz: fragment size @@ -3992,8 +4018,6 @@ void skb_split(struct sk_buff *skb, struct sk_buff *skb1, const u32 len); int skb_shift(struct sk_buff *tgt, struct sk_buff *skb, int shiftlen); void skb_scrub_packet(struct sk_buff *skb, bool xnet); -bool skb_gso_validate_network_len(const struct sk_buff *skb, unsigned int mtu); -bool skb_gso_validate_mac_len(const struct sk_buff *skb, unsigned int len); struct sk_buff *skb_segment(struct sk_buff *skb, netdev_features_t features); struct sk_buff *skb_segment_list(struct sk_buff *skb, netdev_features_t features, unsigned int offset); @@ -4859,75 +4883,6 @@ #endif } -/* Keeps track of mac header offset relative to skb->head. - * It is useful for TSO of Tunneling protocol. e.g. GRE. - * For non-tunnel skb it points to skb_mac_header() and for - * tunnel skb it points to outer mac header. - * Keeps track of level of encapsulation of network headers. - */ -struct skb_gso_cb { - union { - int mac_offset; - int data_offset; - }; - int encap_level; - __wsum csum; - __u16 csum_start; -}; -#define SKB_GSO_CB_OFFSET 32 -#define SKB_GSO_CB(skb) ((struct skb_gso_cb *)((skb)->cb + SKB_GSO_CB_OFFSET)) - -static inline int skb_tnl_header_len(const struct sk_buff *inner_skb) -{ - return (skb_mac_header(inner_skb) - inner_skb->head) - - SKB_GSO_CB(inner_skb)->mac_offset; -} - -static inline int gso_pskb_expand_head(struct sk_buff *skb, int extra) -{ - int new_headroom, headroom; - int ret; - - headroom = skb_headroom(skb); - ret = pskb_expand_head(skb, extra, 0, GFP_ATOMIC); - if (ret) - return ret; - - new_headroom = skb_headroom(skb); - SKB_GSO_CB(skb)->mac_offset += (new_headroom - headroom); - return 0; -} - -static inline void gso_reset_checksum(struct sk_buff *skb, __wsum res) -{ - /* Do not update partial checksums if remote checksum is enabled. */ - if (skb->remcsum_offload) - return; - - SKB_GSO_CB(skb)->csum = res; - SKB_GSO_CB(skb)->csum_start = skb_checksum_start(skb) - skb->head; -} - -/* Compute the checksum for a gso segment. First compute the checksum value - * from the start of transport header to SKB_GSO_CB(skb)->csum_start, and - * then add in skb->csum (checksum from csum_start to end of packet). - * skb->csum and csum_start are then updated to reflect the checksum of the - * resultant packet starting from the transport header-- the resultant checksum - * is in the res argument (i.e. normally zero or ~ of checksum of a pseudo - * header. - */ -static inline __sum16 gso_make_checksum(struct sk_buff *skb, __wsum res) -{ - unsigned char *csum_start = skb_transport_header(skb); - int plen = (skb->head + SKB_GSO_CB(skb)->csum_start) - csum_start; - __wsum partial = SKB_GSO_CB(skb)->csum; - - SKB_GSO_CB(skb)->csum = res; - SKB_GSO_CB(skb)->csum_start = csum_start - skb->head; - - return csum_fold(csum_partial(csum_start, plen, partial)); -} - static inline bool skb_is_gso(const struct sk_buff *skb) { return skb_shinfo(skb)->gso_size; diff -ruw linux-6.4/include/linux/tcp.h linux-6.4-fbx/include/linux/tcp.h --- linux-6.4/include/linux/tcp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/tcp.h 2023-05-22 20:06:44.719866463 +0200 @@ -255,7 +255,8 @@ u8 compressed_ack; u8 dup_ack_counter:2, tlp_retrans:1, /* TLP is a retransmission */ - unused:5; + linear_rto:1, + unused:4; u32 chrono_start; /* Start time in jiffies of a TCP chrono */ u32 chrono_stat[3]; /* Time in jiffies for chrono_stat stats */ u8 chrono_type:2, /* current chronograph type */ diff -ruw linux-6.4/include/linux/thermal.h linux-6.4-fbx/include/linux/thermal.h --- linux-6.4/include/linux/thermal.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/thermal.h 2023-05-22 20:06:44.719866463 +0200 @@ -326,6 +326,9 @@ struct thermal_cooling_device *thermal_cooling_device_register(const char *, void *, const struct thermal_cooling_device_ops *); +struct thermal_cooling_device *thermal_cooling_device_register_with_parent( + struct device *pdev, const char *, void *, + const struct thermal_cooling_device_ops *); struct thermal_cooling_device * thermal_of_cooling_device_register(struct device_node *np, const char *, void *, const struct thermal_cooling_device_ops *); diff -ruw linux-6.4/include/linux/vmalloc.h linux-6.4-fbx/include/linux/vmalloc.h --- linux-6.4/include/linux/vmalloc.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/linux/vmalloc.h 2023-05-22 20:06:44.739866995 +0200 @@ -145,6 +145,8 @@ extern void *vmalloc_32(unsigned long size) __alloc_size(1); extern void *vmalloc_32_user(unsigned long size) __alloc_size(1); extern void *__vmalloc(unsigned long size, gfp_t gfp_mask) __alloc_size(1); +extern void *__vmalloc_pgprot(unsigned long size, gfp_t gfp_mask, + pgprot_t prot) __alloc_size(1); extern void *__vmalloc_node_range(unsigned long size, unsigned long align, unsigned long start, unsigned long end, gfp_t gfp_mask, pgprot_t prot, unsigned long vm_flags, int node, diff -ruw linux-6.4/include/media/dvb-usb-ids.h linux-6.4-fbx/include/media/dvb-usb-ids.h --- linux-6.4/include/media/dvb-usb-ids.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/media/dvb-usb-ids.h 2023-05-22 20:06:44.743867101 +0200 @@ -167,6 +167,7 @@ #define USB_PID_DIBCOM_ANCHOR_2135_COLD 0x2131 #define USB_PID_DIBCOM_HOOK_DEFAULT 0x0064 #define USB_PID_DIBCOM_HOOK_DEFAULT_REENUM 0x0065 +#define USB_PID_DIBCOM_HOOK_DEFAULT_STK7770P 0x0066 #define USB_PID_DIBCOM_MOD3000_COLD 0x0bb8 #define USB_PID_DIBCOM_MOD3000_WARM 0x0bb9 #define USB_PID_DIBCOM_MOD3001_COLD 0x0bc6 diff -ruw linux-6.4/include/net/cfg80211.h linux-6.4-fbx/include/net/cfg80211.h --- linux-6.4/include/net/cfg80211.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/cfg80211.h 2024-04-19 16:04:28.965735994 +0200 @@ -7,7 +7,7 @@ * Copyright 2006-2010 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright 2015-2017 Intel Deutschland GmbH - * Copyright (C) 2018-2021 Intel Corporation + * Copyright (C) 2018-2021, 2023 Intel Corporation */ #include @@ -76,6 +76,8 @@ * @IEEE80211_CHAN_DISABLED: This channel is disabled. * @IEEE80211_CHAN_NO_IR: do not initiate radiation, this includes * sending probe requests or beaconing. + * @IEEE80211_CHAN_PSD: Power spectral density (in dBm) is set for this + * channel. * @IEEE80211_CHAN_RADAR: Radar detection is required on this channel. * @IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel * is not permitted. @@ -119,7 +121,7 @@ enum ieee80211_channel_flags { IEEE80211_CHAN_DISABLED = 1<<0, IEEE80211_CHAN_NO_IR = 1<<1, - /* hole at 1<<2 */ + IEEE80211_CHAN_PSD = 1<<2, IEEE80211_CHAN_RADAR = 1<<3, IEEE80211_CHAN_NO_HT40PLUS = 1<<4, IEEE80211_CHAN_NO_HT40MINUS = 1<<5, @@ -144,6 +146,7 @@ (IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS) #define IEEE80211_DFS_MIN_CAC_TIME_MS 60000 +#define IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS 600000 #define IEEE80211_DFS_MIN_NOP_TIME_MS (30 * 60 * 1000) /** @@ -171,6 +174,7 @@ * on this channel. * @dfs_state_entered: timestamp (jiffies) when the dfs state was entered. * @dfs_cac_ms: DFS CAC time in milliseconds, this is valid for DFS channels. + * @psd: power spectral density (in dBm) */ struct ieee80211_channel { enum nl80211_band band; @@ -187,6 +191,7 @@ enum nl80211_dfs_state dfs_state; unsigned long dfs_state_entered; unsigned int dfs_cac_ms; + s8 psd; }; /** @@ -263,7 +268,7 @@ * are only for driver use when pointers to this structure are * passed around. * - * @flags: rate-specific flags + * @flags: rate-specific flags from &enum ieee80211_rate_flags * @bitrate: bitrate in units of 100 Kbps * @hw_value: driver/hardware value for this rate * @hw_value_short: driver/hardware value for this rate when @@ -309,6 +314,9 @@ u8 color; bool enabled; bool partial; + + /* help compiling QCA code, no API to set it, value is always true */ + bool collision_detection_enabled; }; /** @@ -562,6 +570,9 @@ if (WARN_ON(iftype >= NL80211_IFTYPE_MAX)) return NULL; + if (iftype == NL80211_IFTYPE_AP_VLAN) + iftype = NL80211_IFTYPE_AP; + for (i = 0; i < sband->n_iftype_data; i++) { const struct ieee80211_sband_iftype_data *data = &sband->iftype_data[i]; @@ -752,6 +763,10 @@ u32 center_freq2; struct ieee80211_edmg edmg; u16 freq1_offset; + + /* help compiling QCA code, no API to set it, initialized to 0 */ + u16 ru_punct_bitmap; + bool ru_punct_bitmap_supp_he; }; /* @@ -766,6 +781,13 @@ enum nl80211_txrate_gi gi; enum nl80211_he_gi he_gi; enum nl80211_he_ltf he_ltf; + /* help compiling QCA code, no API to set it, value is + * always 0 */ + u16 he_ul_mcs[NL80211_HE_NSS_MAX]; + + /* help compiling QCA code, no API to set it, initialized + * according to station capabilities */ + u16 eht_mcs[NL80211_EHT_NSS_MAX]; } control[NUM_NL80211_BANDS]; }; @@ -808,7 +830,7 @@ struct cfg80211_tid_config { const u8 *peer; u32 n_tid_conf; - struct cfg80211_tid_cfg tid_conf[]; + struct cfg80211_tid_cfg tid_conf[] __counted_by(n_tid_conf); }; /** @@ -951,6 +973,30 @@ enum nl80211_iftype iftype); /** + * cfg80211_chandef_dfs_usable - checks if chandef is DFS usable and we + * can/need start CAC on such channel + * @wiphy: the wiphy to validate against + * @chandef: the channel definition to check + * + * Return: true if all channels available and at least + * one channel requires CAC (NL80211_DFS_USABLE) + */ +bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy, + const struct cfg80211_chan_def *chandef); + +/** + * cfg80211_chandef_dfs_cac_time - get the DFS CAC time (in ms) for given + * channel definition + * @wiphy: the wiphy to validate against + * @chandef: the channel definition to check + * + * Returns: DFS CAC time (in ms) which applies for this channel definition + */ +unsigned int +cfg80211_chandef_dfs_cac_time(struct wiphy *wiphy, + const struct cfg80211_chan_def *chandef); + +/** * nl80211_send_chandef - sends the channel definition. * @msg: the msg to send channel definition * @chandef: the channel definition to check @@ -1184,7 +1230,7 @@ struct { const u8 *data; size_t len; - } elem[]; + } elem[] __counted_by(cnt); }; /** @@ -1201,7 +1247,7 @@ struct { const u8 *data; size_t len; - } elem[]; + } elem[] __counted_by(cnt); }; /** @@ -1279,13 +1325,14 @@ int n_acl_entries; /* Keep it last */ - struct mac_address mac_addrs[]; + struct mac_address mac_addrs[] __counted_by(n_acl_entries); }; /** * struct cfg80211_fils_discovery - FILS discovery parameters from * IEEE Std 802.11ai-2016, Annex C.3 MIB detail. * + * @update: Set to true if the feature configuration should be updated. * @min_interval: Minimum packet interval in TUs (0 - 10000) * @max_interval: Maximum packet interval in TUs (0 - 10000) * @tmpl_len: Template length @@ -1293,6 +1340,7 @@ * frame headers. */ struct cfg80211_fils_discovery { + bool update; u32 min_interval; u32 max_interval; size_t tmpl_len; @@ -1303,6 +1351,7 @@ * struct cfg80211_unsol_bcast_probe_resp - Unsolicited broadcast probe * response parameters in 6GHz. * + * @update: Set to true if the feature configuration should be updated. * @interval: Packet interval in TUs. Maximum allowed is 20 TU, as mentioned * in IEEE P802.11ax/D6.0 26.17.2.3.2 - AP behavior for fast passive * scanning @@ -1310,6 +1359,7 @@ * @tmpl: Template data for probe response */ struct cfg80211_unsol_bcast_probe_resp { + bool update; u32 interval; size_t tmpl_len; const u8 *tmpl; @@ -1350,7 +1400,7 @@ * @twt_responder: Enable Target Wait Time * @he_required: stations must support HE * @sae_h2e_required: stations must support direct H2E technique in SAE - * @flags: flags, as defined in enum cfg80211_ap_settings_flags + * @flags: flags, as defined in &enum nl80211_ap_settings_flags * @he_obss_pd: OBSS Packet Detection settings * @he_oper: HE operation IE (or %NULL if HE isn't enabled) * @fils_discovery: FILS discovery transmission parameters @@ -1396,6 +1446,22 @@ u16 punct_bitmap; }; + +/** + * struct cfg80211_ap_update - AP configuration update + * + * Subset of &struct cfg80211_ap_settings, for updating a running AP. + * + * @beacon: beacon data + * @fils_discovery: FILS discovery transmission parameters + * @unsol_bcast_probe_resp: Unsolicited broadcast probe response parameters + */ +struct cfg80211_ap_update { + struct cfg80211_beacon_data beacon; + struct cfg80211_fils_discovery fils_discovery; + struct cfg80211_unsol_bcast_probe_resp unsol_bcast_probe_resp; +}; + /** * struct cfg80211_csa_settings - channel switch settings * @@ -1479,7 +1545,6 @@ * @STATION_PARAM_APPLY_UAPSD: apply new uAPSD parameters (uapsd_queues, max_sp) * @STATION_PARAM_APPLY_CAPABILITY: apply new capability * @STATION_PARAM_APPLY_PLINK_STATE: apply new plink state - * @STATION_PARAM_APPLY_STA_TXPOWER: apply tx power for STA * * Not all station parameters have in-band "no change" signalling, * for those that don't these flags will are used. @@ -1532,6 +1597,8 @@ * @he_6ghz_capa: HE 6 GHz Band capabilities of station * @eht_capa: EHT capabilities of station * @eht_capa_len: the length of the EHT capabilities + * @tp_override: Throughput overide value + * @tp_overridden: Throughput has been overridden */ struct link_station_parameters { const u8 *mld_mac; @@ -1550,6 +1617,8 @@ const struct ieee80211_he_6ghz_capa *he_6ghz_capa; const struct ieee80211_eht_cap_elem *eht_capa; u8 eht_capa_len; + u32 tp_override; + bool tp_overridden; }; /** @@ -1702,6 +1771,7 @@ * @RATE_INFO_FLAGS_EDMG: 60GHz MCS in EDMG mode * @RATE_INFO_FLAGS_EXTENDED_SC_DMG: 60GHz extended SC MCS * @RATE_INFO_FLAGS_EHT_MCS: EHT MCS information + * @RATE_INFO_FLAGS_S1G_MCS: MCS field filled with S1G MCS */ enum rate_info_flags { RATE_INFO_FLAGS_MCS = BIT(0), @@ -1712,6 +1782,7 @@ RATE_INFO_FLAGS_EDMG = BIT(5), RATE_INFO_FLAGS_EXTENDED_SC_DMG = BIT(6), RATE_INFO_FLAGS_EHT_MCS = BIT(7), + RATE_INFO_FLAGS_S1G_MCS = BIT(8), }; /** @@ -1728,6 +1799,11 @@ * @RATE_INFO_BW_HE_RU: bandwidth determined by HE RU allocation * @RATE_INFO_BW_320: 320 MHz bandwidth * @RATE_INFO_BW_EHT_RU: bandwidth determined by EHT RU allocation + * @RATE_INFO_BW_1: 1 MHz bandwidth + * @RATE_INFO_BW_2: 2 MHz bandwidth + * @RATE_INFO_BW_4: 4 MHz bandwidth + * @RATE_INFO_BW_8: 8 MHz bandwidth + * @RATE_INFO_BW_16: 16 MHz bandwidth */ enum rate_info_bw { RATE_INFO_BW_20 = 0, @@ -1739,6 +1815,11 @@ RATE_INFO_BW_HE_RU, RATE_INFO_BW_320, RATE_INFO_BW_EHT_RU, + RATE_INFO_BW_1, + RATE_INFO_BW_2, + RATE_INFO_BW_4, + RATE_INFO_BW_8, + RATE_INFO_BW_16, }; /** @@ -1747,8 +1828,8 @@ * Information about a receiving or transmitting bitrate * * @flags: bitflag of flags from &enum rate_info_flags - * @mcs: mcs index if struct describes an HT/VHT/HE rate * @legacy: bitrate in 100kbit/s for 802.11abg + * @mcs: mcs index if struct describes an HT/VHT/HE/EHT/S1G rate * @nss: number of streams (VHT & HE only) * @bw: bandwidth (from &enum rate_info_bw) * @he_gi: HE guard interval (from &enum nl80211_he_gi) @@ -1761,9 +1842,9 @@ * only valid if bw is %RATE_INFO_BW_EHT_RU) */ struct rate_info { - u8 flags; - u8 mcs; + u16 flags; u16 legacy; + u8 mcs; u8 nss; u8 bw; u8 he_gi; @@ -2141,7 +2222,7 @@ * @sn: target sequence number * @metric: metric (cost) of this mesh path * @exptime: expiration time for the mesh path from now, in msecs - * @flags: mesh path flags + * @flags: mesh path flags from &enum mesh_path_flags * @discovery_timeout: total mesh path discovery timeout, in msecs * @discovery_retries: mesh path discovery retries * @generation: generation number for nl80211 dumps. @@ -2166,6 +2247,15 @@ int generation; }; +#define MPLINK_DUMP_MAX_BLOCKED_ENTRIES 216 /* 216/6 = 36 entries */ +/** + * struct mplink_blocked_info - mesh peer link blocked info + */ +struct mplink_blocked_info { + u8 count; + u8 info[MPLINK_DUMP_MAX_BLOCKED_ENTRIES]; +}; + /** * struct bss_parameters - BSS parameters * @@ -2332,7 +2422,7 @@ * @user_mpm: userspace handles all MPM functions * @dtim_period: DTIM period to use * @beacon_interval: beacon interval to use - * @mcast_rate: multicat rate for Mesh Node [6Mbps is the default for 802.11a] + * @mcast_rate: multicast rate for Mesh Node [6Mbps is the default for 802.11a] * @basic_rates: basic rates to use when creating the mesh * @beacon_rate: bitrate to be used for beacons * @userspace_handles_dfs: whether user space controls DFS operation, i.e. @@ -2366,6 +2456,17 @@ }; /** + * struct mesh_setup - 802.11s mesh setup configuration + * @ie: vendor information elements + * @ie_len: length of vendor information elements + * These parameters are updated peroidically after mesh creation. + */ +struct mesh_vendor_ie { + const u8 *ie; + u8 ie_len; +}; + +/** * struct ocb_setup - 802.11p OCB mode setup configuration * @chandef: defines the channel to use * @@ -2454,6 +2555,7 @@ * @short_ssid_valid: @short_ssid is valid and can be used * @psc_no_listen: when set, and the channel is a PSC channel, no need to wait * 20 TUs before starting to send probe requests. + * @psd_20: The AP's 20 MHz PSD value. */ struct cfg80211_scan_6ghz_params { u32 short_ssid; @@ -2462,6 +2564,7 @@ bool unsolicited_probe; bool short_ssid_valid; bool psc_no_listen; + s8 psd_20; }; /** @@ -2471,7 +2574,6 @@ * @n_ssids: number of SSIDs * @channels: channels to scan on. * @n_channels: total number of channels to scan - * @scan_width: channel width for scanning * @ie: optional information element(s) to add into Probe Request or %NULL * @ie_len: length of ie in octets * @duration: how long to listen on each channel, in TUs. If @@ -2479,7 +2581,7 @@ * the actual dwell time may be shorter. * @duration_mandatory: if set, the scan duration must be as specified by the * %duration field. - * @flags: bit field of flags controlling operation + * @flags: control flags from &enum nl80211_scan_flags * @rates: bitmap of rates to advertise for each band * @wiphy: the wiphy this was for * @scan_start: time (in jiffies) when the scan started @@ -2501,7 +2603,6 @@ struct cfg80211_ssid *ssids; int n_ssids; u32 n_channels; - enum nl80211_bss_scan_width scan_width; const u8 *ie; size_t ie_len; u16 duration; @@ -2527,7 +2628,7 @@ struct cfg80211_scan_6ghz_params *scan_6ghz_params; /* keep last */ - struct ieee80211_channel *channels[]; + struct ieee80211_channel *channels[] __counted_by(n_channels); }; static inline void get_random_mask_addr(u8 *buf, const u8 *addr, const u8 *mask) @@ -2550,7 +2651,7 @@ * or no match (RSSI only) * @rssi_thold: don't report scan results below this threshold (in s32 dBm) * @per_band_rssi_thold: Minimum rssi threshold for each band to be applied - * for filtering out scan results received. Drivers advertize this support + * for filtering out scan results received. Drivers advertise this support * of band specific rssi based filtering through the feature capability * %NL80211_EXT_FEATURE_SCHED_SCAN_BAND_SPECIFIC_RSSI_THOLD. These band * specific rssi thresholds take precedence over rssi_thold, if specified. @@ -2596,14 +2697,13 @@ * @ssids: SSIDs to scan for (passed in the probe_reqs in active scans) * @n_ssids: number of SSIDs * @n_channels: total number of channels to scan - * @scan_width: channel width for scanning * @ie: optional information element(s) to add into Probe Request or %NULL * @ie_len: length of ie in octets - * @flags: bit field of flags controlling operation + * @flags: control flags from &enum nl80211_scan_flags * @match_sets: sets of parameters to be matched for a scan result * entry to be considered valid and to be passed to the host * (others are filtered out). - * If ommited, all results are passed. + * If omitted, all results are passed. * @n_match_sets: number of match sets * @report_results: indicates that results were reported for this request * @wiphy: the wiphy this was for @@ -2637,14 +2737,13 @@ * to the specified band while deciding whether a better BSS is reported * using @relative_rssi. If delta is a negative number, the BSSs that * belong to the specified band will be penalized by delta dB in relative - * comparisions. + * comparisons. */ struct cfg80211_sched_scan_request { u64 reqid; struct cfg80211_ssid *ssids; int n_ssids; u32 n_channels; - enum nl80211_bss_scan_width scan_width; const u8 *ie; size_t ie_len; u32 flags; @@ -2692,7 +2791,6 @@ /** * struct cfg80211_inform_bss - BSS inform data * @chan: channel the frame was received on - * @scan_width: scan width that was used * @signal: signal strength value, according to the wiphy's * signal type * @boottime_ns: timestamp (CLOCK_BOOTTIME) when the information was @@ -2708,16 +2806,18 @@ * the BSS that requested the scan in which the beacon/probe was received. * @chains: bitmask for filled values in @chain_signal. * @chain_signal: per-chain signal strength of last received BSS in dBm. + * @drv_data: Data to be passed through to @inform_bss */ struct cfg80211_inform_bss { struct ieee80211_channel *chan; - enum nl80211_bss_scan_width scan_width; s32 signal; u64 boottime_ns; u64 parent_tsf; u8 parent_bssid[ETH_ALEN] __aligned(2); u8 chains; s8 chain_signal[IEEE80211_MAX_CHAINS]; + + void *drv_data; }; /** @@ -2743,7 +2843,6 @@ * for use in scan results and similar. * * @channel: channel this BSS is on - * @scan_width: width of the control channel * @bssid: BSSID of the BSS * @beacon_interval: the beacon interval as from the frame * @capability: the capability field in host byte order @@ -2773,7 +2872,6 @@ */ struct cfg80211_bss { struct ieee80211_channel *channel; - enum nl80211_bss_scan_width scan_width; const struct cfg80211_bss_ies __rcu *ies; const struct cfg80211_bss_ies __rcu *beacon_ies; @@ -2870,11 +2968,17 @@ * if this is %NULL for a link, that link is not requested * @elems: extra elements for the per-STA profile for this link * @elems_len: length of the elements + * @disabled: If set this link should be included during association etc. but it + * should not be used until enabled by the AP MLD. + * @error: per-link error code, must be <= 0. If there is an error, then the + * operation as a whole must fail. */ struct cfg80211_assoc_link { struct cfg80211_bss *bss; const u8 *elems; size_t elems_len; + bool disabled; + int error; }; /** @@ -3473,7 +3577,7 @@ * This structure provides information needed to transmit a mgmt frame * * @chan: channel to use - * @offchan: indicates wether off channel operation is required + * @offchan: indicates whether off channel operation is required * @wait: duration for ROC * @buf: buffer to transmit * @len: buffer length @@ -3591,7 +3695,7 @@ * @publish_bcast: if true, the solicited publish should be broadcasted * @subscribe_active: if true, the subscribe is active * @followup_id: the instance ID for follow up - * @followup_reqid: the requestor instance ID for follow up + * @followup_reqid: the requester instance ID for follow up * @followup_dest: MAC address of the recipient of the follow up * @ttl: time to live counter in DW. * @serv_spec_info: Service Specific Info @@ -3925,7 +4029,7 @@ struct list_head list; - struct cfg80211_pmsr_request_peer peers[]; + struct cfg80211_pmsr_request_peer peers[] __counted_by(n_peers); }; /** @@ -4086,6 +4190,13 @@ * * @change_bss: Modify parameters for a given BSS. * + * @inform_bss: Called by cfg80211 while being informed about new BSS data + * for every BSS found within the reported data or frame. This is called + * from within the cfg8011 inform_bss handlers while holding the bss_lock. + * The data parameter is passed through from drv_data inside + * struct cfg80211_inform_bss. + * The new IE data for the BSS is explicitly passed. + * * @set_txq_params: Set TX queue parameters * * @libertas_set_mesh_channel: Only for backward compatibility for libertas, @@ -4421,7 +4532,7 @@ int (*start_ap)(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_ap_settings *settings); int (*change_beacon)(struct wiphy *wiphy, struct net_device *dev, - struct cfg80211_beacon_data *info); + struct cfg80211_ap_update *info); int (*stop_ap)(struct wiphy *wiphy, struct net_device *dev, unsigned int link_id); @@ -4473,6 +4584,9 @@ int (*change_bss)(struct wiphy *wiphy, struct net_device *dev, struct bss_parameters *params); + void (*inform_bss)(struct wiphy *wiphy, struct cfg80211_bss *bss, + const struct cfg80211_bss_ies *ies, void *data); + int (*set_txq_params)(struct wiphy *wiphy, struct net_device *dev, struct ieee80211_txq_params *params); @@ -4592,9 +4706,10 @@ struct cfg80211_gtk_rekey_data *data); int (*tdls_mgmt)(struct wiphy *wiphy, struct net_device *dev, - const u8 *peer, u8 action_code, u8 dialog_token, - u16 status_code, u32 peer_capability, - bool initiator, const u8 *buf, size_t len); + const u8 *peer, int link_id, + u8 action_code, u8 dialog_token, u16 status_code, + u32 peer_capability, bool initiator, + const u8 *buf, size_t len); int (*tdls_oper)(struct wiphy *wiphy, struct net_device *dev, const u8 *peer, enum nl80211_tdls_operation oper); @@ -4783,6 +4898,8 @@ * @WIPHY_FLAG_SUPPORTS_EXT_KCK_32: The device supports 32-byte KCK keys. * @WIPHY_FLAG_NOTIFY_REGDOM_BY_DRIVER: The device could handle reg notify for * NL80211_REGDOM_SET_BY_DRIVER. + * @WIPHY_FLAG_CHANNEL_CHANGE_ON_BEACON: reg_call_notifier() is called if driver + * set this flag to update channels on beacon hints. */ enum wiphy_flags { WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK = BIT(0), @@ -4809,6 +4926,7 @@ WIPHY_FLAG_SUPPORTS_5_10_MHZ = BIT(22), WIPHY_FLAG_HAS_CHANNEL_SWITCH = BIT(23), WIPHY_FLAG_NOTIFY_REGDOM_BY_DRIVER = BIT(24), + WIPHY_FLAG_CHANNEL_CHANGE_ON_BEACON = BIT(25), }; /** @@ -5410,6 +5528,8 @@ u8 perm_addr[ETH_ALEN]; u8 addr_mask[ETH_ALEN]; + int dev_port; + struct mac_address *addresses; const struct ieee80211_txrx_stypes *mgmt_stypes; @@ -5724,12 +5844,17 @@ * wiphy_lock - lock the wiphy * @wiphy: the wiphy to lock * - * This is mostly exposed so it can be done around registering and - * unregistering netdevs that aren't created through cfg80211 calls, - * since that requires locking in cfg80211 when the notifiers is - * called, but that cannot differentiate which way it's called. + * This is needed around registering and unregistering netdevs that + * aren't created through cfg80211 calls, since that requires locking + * in cfg80211 when the notifiers is called, but that cannot + * differentiate which way it's called. + * + * It can also be used by drivers for their own purposes. * * When cfg80211 ops are called, the wiphy is already locked. + * + * Note that this makes sure that no workers that have been queued + * with wiphy_queue_work() are running. */ static inline void wiphy_lock(struct wiphy *wiphy) __acquires(&wiphy->mtx) @@ -5749,6 +5874,109 @@ mutex_unlock(&wiphy->mtx); } +struct wiphy_work; +typedef void (*wiphy_work_func_t)(struct wiphy *, struct wiphy_work *); + +struct wiphy_work { + struct list_head entry; + wiphy_work_func_t func; +}; + +static inline void wiphy_work_init(struct wiphy_work *work, + wiphy_work_func_t func) +{ + INIT_LIST_HEAD(&work->entry); + work->func = func; +} + +/** + * wiphy_work_queue - queue work for the wiphy + * @wiphy: the wiphy to queue for + * @work: the work item + * + * This is useful for work that must be done asynchronously, and work + * queued here has the special property that the wiphy mutex will be + * held as if wiphy_lock() was called, and that it cannot be running + * after wiphy_lock() was called. Therefore, wiphy_cancel_work() can + * use just cancel_work() instead of cancel_work_sync(), it requires + * being in a section protected by wiphy_lock(). + */ +void wiphy_work_queue(struct wiphy *wiphy, struct wiphy_work *work); + +/** + * wiphy_work_cancel - cancel previously queued work + * @wiphy: the wiphy, for debug purposes + * @work: the work to cancel + * + * Cancel the work *without* waiting for it, this assumes being + * called under the wiphy mutex acquired by wiphy_lock(). + */ +void wiphy_work_cancel(struct wiphy *wiphy, struct wiphy_work *work); + +/** + * wiphy_work_flush - flush previously queued work + * @wiphy: the wiphy, for debug purposes + * @work: the work to flush, this can be %NULL to flush all work + * + * Flush the work (i.e. run it if pending). This must be called + * under the wiphy mutex acquired by wiphy_lock(). + */ +void wiphy_work_flush(struct wiphy *wiphy, struct wiphy_work *work); + +struct wiphy_delayed_work { + struct wiphy_work work; + struct wiphy *wiphy; + struct timer_list timer; +}; + +void wiphy_delayed_work_timer(struct timer_list *t); + +static inline void wiphy_delayed_work_init(struct wiphy_delayed_work *dwork, + wiphy_work_func_t func) +{ + timer_setup(&dwork->timer, wiphy_delayed_work_timer, 0); + wiphy_work_init(&dwork->work, func); +} + +/** + * wiphy_delayed_work_queue - queue delayed work for the wiphy + * @wiphy: the wiphy to queue for + * @dwork: the delayable worker + * @delay: number of jiffies to wait before queueing + * + * This is useful for work that must be done asynchronously, and work + * queued here has the special property that the wiphy mutex will be + * held as if wiphy_lock() was called, and that it cannot be running + * after wiphy_lock() was called. Therefore, wiphy_cancel_work() can + * use just cancel_work() instead of cancel_work_sync(), it requires + * being in a section protected by wiphy_lock(). + */ +void wiphy_delayed_work_queue(struct wiphy *wiphy, + struct wiphy_delayed_work *dwork, + unsigned long delay); + +/** + * wiphy_delayed_work_cancel - cancel previously queued delayed work + * @wiphy: the wiphy, for debug purposes + * @dwork: the delayed work to cancel + * + * Cancel the work *without* waiting for it, this assumes being + * called under the wiphy mutex acquired by wiphy_lock(). + */ +void wiphy_delayed_work_cancel(struct wiphy *wiphy, + struct wiphy_delayed_work *dwork); + +/** + * wiphy_delayed_work_flush - flush previously queued delayed work + * @wiphy: the wiphy, for debug purposes + * @dwork: the delayed work to flush + * + * Flush the work (i.e. run it if pending). This must be called + * under the wiphy mutex acquired by wiphy_lock(). + */ +void wiphy_delayed_work_flush(struct wiphy *wiphy, + struct wiphy_delayed_work *dwork); + /** * struct wireless_dev - wireless device state * @@ -5797,8 +6025,6 @@ * @mgmt_registrations: list of registrations for management frames * @mgmt_registrations_need_update: mgmt registrations were updated, * need to propagate the update to the driver - * @mtx: mutex used to lock data in this struct, may be used by drivers - * and some API functions require it held * @beacon_interval: beacon interval used on this device for transmitting * beacons, 0 when not valid * @address: The address for this device, valid only if @netdev is %NULL @@ -5821,6 +6047,7 @@ * @event_lock: (private) lock for event list * @owner_nlportid: (private) owner socket port ID * @nl_owner_dead: (private) owner socket went away + * @cqm_rssi_work: (private) CQM RSSI reporting work * @cqm_config: (private) nl80211 RSSI monitor state * @pmsr_list: (private) peer measurement requests * @pmsr_lock: (private) peer measurements requests/results lock @@ -5844,8 +6071,6 @@ struct list_head mgmt_registrations; u8 mgmt_registrations_need_update:1; - struct mutex mtx; - bool use_4addr, is_running, registered, registering; u8 address[ETH_ALEN] __aligned(sizeof(u16)); @@ -5893,7 +6118,8 @@ } wext; #endif - struct cfg80211_cqm_config *cqm_config; + struct wiphy_work cqm_rssi_work; + struct cfg80211_cqm_config __rcu *cqm_config; struct list_head pmsr_list; spinlock_t pmsr_lock; @@ -6135,13 +6361,11 @@ /** * ieee80211_mandatory_rates - get mandatory rates for a given band * @sband: the band to look for rates in - * @scan_width: width of the control channel * * This function returns a bitmap of the mandatory rates for the given * band, bits are set according to the rate position in the bitrates array. */ -u32 ieee80211_mandatory_rates(struct ieee80211_supported_band *sband, - enum nl80211_bss_scan_width scan_width); +u32 ieee80211_mandatory_rates(struct ieee80211_supported_band *sband); /* * Radiotap parsing functions -- for controlled injection support @@ -6482,7 +6706,7 @@ * @ies: data consisting of IEs * @len: length of data * - * Return: %NULL if the etended element could not be found or if + * Return: %NULL if the extended element could not be found or if * the element is invalid (claims to be longer than the given * data) or if the byte array doesn't match; otherwise return the * requested element struct. @@ -6561,6 +6785,28 @@ } /** + * cfg80211_defragment_element - Defrag the given element data into a buffer + * + * @elem: the element to defragment + * @ies: elements where @elem is contained + * @ieslen: length of @ies + * @data: buffer to store element data + * @data_len: length of @data + * @frag_id: the element ID of fragments + * + * Return: length of @data, or -EINVAL on error + * + * Copy out all data from an element that may be fragmented into @data, while + * skipping all headers. + * + * The function uses memmove() internally. It is acceptable to defragment an + * element in-place. + */ +ssize_t cfg80211_defragment_element(const struct element *elem, const u8 *ies, + size_t ieslen, u8 *data, size_t data_len, + u8 frag_id); + +/** * cfg80211_send_layer2_update - send layer 2 update frame * * @dev: network device @@ -6607,7 +6853,7 @@ /** * regulatory_set_wiphy_regd - set regdom info for self managed drivers * @wiphy: the wireless device we want to process the regulatory domain on - * @rd: the regulatory domain informatoin to use for this wiphy + * @rd: the regulatory domain information to use for this wiphy * * Set the regulatory domain information for self-managed wiphys, only they * may use this function. See %REGULATORY_WIPHY_SELF_MANAGED for more @@ -6698,7 +6944,7 @@ * Regulatory self-managed driver can use it to proactively * * @alpha2: the ISO/IEC 3166 alpha2 wmm rule to be queried. - * @freq: the freqency(in MHz) to be queried. + * @freq: the frequency (in MHz) to be queried. * @rule: pointer to store the wmm rule from the regulatory db. * * Self-managed wireless drivers can use this function to query @@ -6781,22 +7027,6 @@ gfp_t gfp); static inline struct cfg80211_bss * __must_check -cfg80211_inform_bss_width_frame(struct wiphy *wiphy, - struct ieee80211_channel *rx_channel, - enum nl80211_bss_scan_width scan_width, - struct ieee80211_mgmt *mgmt, size_t len, - s32 signal, gfp_t gfp) -{ - struct cfg80211_inform_bss data = { - .chan = rx_channel, - .scan_width = scan_width, - .signal = signal, - }; - - return cfg80211_inform_bss_frame_data(wiphy, &data, mgmt, len, gfp); -} - -static inline struct cfg80211_bss * __must_check cfg80211_inform_bss_frame(struct wiphy *wiphy, struct ieee80211_channel *rx_channel, struct ieee80211_mgmt *mgmt, size_t len, @@ -6804,7 +7034,6 @@ { struct cfg80211_inform_bss data = { .chan = rx_channel, - .scan_width = NL80211_BSS_CHAN_WIDTH_20, .signal = signal, }; @@ -6907,26 +7136,6 @@ gfp_t gfp); static inline struct cfg80211_bss * __must_check -cfg80211_inform_bss_width(struct wiphy *wiphy, - struct ieee80211_channel *rx_channel, - enum nl80211_bss_scan_width scan_width, - enum cfg80211_bss_frame_type ftype, - const u8 *bssid, u64 tsf, u16 capability, - u16 beacon_interval, const u8 *ie, size_t ielen, - s32 signal, gfp_t gfp) -{ - struct cfg80211_inform_bss data = { - .chan = rx_channel, - .scan_width = scan_width, - .signal = signal, - }; - - return cfg80211_inform_bss_data(wiphy, &data, ftype, bssid, tsf, - capability, beacon_interval, ie, ielen, - gfp); -} - -static inline struct cfg80211_bss * __must_check cfg80211_inform_bss(struct wiphy *wiphy, struct ieee80211_channel *rx_channel, enum cfg80211_bss_frame_type ftype, @@ -6936,7 +7145,6 @@ { struct cfg80211_inform_bss data = { .chan = rx_channel, - .scan_width = NL80211_BSS_CHAN_WIDTH_20, .signal = signal, }; @@ -7021,19 +7229,6 @@ void *data), void *iter_data); -static inline enum nl80211_bss_scan_width -cfg80211_chandef_to_scan_width(const struct cfg80211_chan_def *chandef) -{ - switch (chandef->width) { - case NL80211_CHAN_WIDTH_5: - return NL80211_BSS_CHAN_WIDTH_5; - case NL80211_CHAN_WIDTH_10: - return NL80211_BSS_CHAN_WIDTH_10; - default: - return NL80211_BSS_CHAN_WIDTH_20; - } -} - /** * cfg80211_rx_mlme_mgmt - notification of processed MLME management frame * @dev: network device @@ -7066,7 +7261,7 @@ void cfg80211_auth_timeout(struct net_device *dev, const u8 *addr); /** - * struct cfg80211_rx_assoc_resp - association response data + * struct cfg80211_rx_assoc_resp_data - association response data * @bss: the BSS that association was requested with, ownership of the pointer * moves to cfg80211 in the call to cfg80211_rx_assoc_resp() * @buf: (Re)Association Response frame (header + body) @@ -7081,7 +7276,7 @@ * @links.status: Set this (along with a BSS pointer) for links that * were rejected by the AP. */ -struct cfg80211_rx_assoc_resp { +struct cfg80211_rx_assoc_resp_data { const u8 *buf; size_t len; const u8 *req_ies; @@ -7089,7 +7284,7 @@ int uapsd_queues; const u8 *ap_mld_addr; struct { - const u8 *addr; + u8 addr[ETH_ALEN] __aligned(2); struct cfg80211_bss *bss; u16 status; } links[IEEE80211_MLD_MAX_NUM_LINKS]; @@ -7098,7 +7293,7 @@ /** * cfg80211_rx_assoc_resp - notification of processed association response * @dev: network device - * @data: association response data, &struct cfg80211_rx_assoc_resp + * @data: association response data, &struct cfg80211_rx_assoc_resp_data * * After being asked to associate via cfg80211_ops::assoc() the driver must * call either this function or cfg80211_auth_timeout(). @@ -7106,7 +7301,7 @@ * This function may sleep. The caller must hold the corresponding wdev's mutex. */ void cfg80211_rx_assoc_resp(struct net_device *dev, - struct cfg80211_rx_assoc_resp *data); + struct cfg80211_rx_assoc_resp_data *data); /** * struct cfg80211_assoc_failure - association failure data @@ -7825,7 +8020,8 @@ * cfg80211_port_authorized - notify cfg80211 of successful security association * * @dev: network device - * @bssid: the BSSID of the AP + * @peer_addr: BSSID of the AP/P2P GO in case of STA/GC or STA/GC MAC address + * in case of AP/P2P GO * @td_bitmap: transition disable policy * @td_bitmap_len: Length of transition disable policy * @gfp: allocation flags @@ -7836,8 +8032,11 @@ * should be preceded with a call to cfg80211_connect_result(), * cfg80211_connect_done(), cfg80211_connect_bss() or cfg80211_roamed() to * indicate the 802.11 association. + * This function can also be called by AP/P2P GO driver that supports + * authentication offload. In this case the peer_mac passed is that of + * associated STA/GC. */ -void cfg80211_port_authorized(struct net_device *dev, const u8 *bssid, +void cfg80211_port_authorized(struct net_device *dev, const u8 *peer_addr, const u8* td_bitmap, u8 td_bitmap_len, gfp_t gfp); /** @@ -7975,7 +8174,7 @@ * @link_id: the ID of the link the frame was received on * @buf: Management frame (header + body) * @len: length of the frame data - * @flags: flags, as defined in enum nl80211_rxmgmt_flags + * @flags: flags, as defined in &enum nl80211_rxmgmt_flags * @rx_tstamp: Hardware timestamp of frame RX in nanoseconds * @ack_tstamp: Hardware timestamp of ack TX in nanoseconds */ @@ -8426,7 +8625,7 @@ * @link_id: the link ID for MLO, must be 0 for non-MLO * @punct_bitmap: the new puncturing bitmap * - * Caller must acquire wdev_lock, therefore must only be called from sleepable + * Caller must hold wiphy mutex, therefore must only be called from sleepable * driver context! */ void cfg80211_ch_switch_notify(struct net_device *dev, @@ -8666,6 +8865,18 @@ } /** + * ieee80211_fragment_element - fragment the last element in skb + * @skb: The skbuf that the element was added to + * @len_pos: Pointer to length of the element to fragment + * @frag_id: The element ID to use for fragments + * + * This function fragments all data after @len_pos, adding fragmentation + * elements with the given ID as appropriate. The SKB will grow in size + * accordingly. + */ +void ieee80211_fragment_element(struct sk_buff *skb, u8 *len_pos, u8 frag_id); + +/** * cfg80211_report_wowlan_wakeup - report wakeup from WoWLAN * @wdev: the wireless device reporting the wakeup * @wakeup: the wakeup report @@ -8914,9 +9125,9 @@ /** * cfg80211_assoc_comeback - notification of association that was - * temporarly rejected with a comeback + * temporarily rejected with a comeback * @netdev: network device - * @ap_addr: AP (MLD) address that rejected the assocation + * @ap_addr: AP (MLD) address that rejected the association * @timeout: timeout interval value TUs. * * this function may sleep. the caller must hold the corresponding wdev's mutex. @@ -9067,4 +9278,17 @@ bool cfg80211_valid_disable_subchannel_bitmap(u16 *bitmap, const struct cfg80211_chan_def *chandef); +/** + * cfg80211_links_removed - Notify about removed STA MLD setup links. + * @dev: network device. + * @link_mask: BIT mask of removed STA MLD setup link IDs. + * + * Inform cfg80211 and the userspace about removed STA MLD setup links due to + * AP MLD removing the corresponding affiliated APs with Multi-Link + * reconfiguration. Note that it's not valid to remove all links, in this + * case disconnect instead. + * Also note that the wdev mutex must be held. + */ +void cfg80211_links_removed(struct net_device *dev, u16 link_mask); + #endif /* __NET_CFG80211_H */ diff -ruw linux-6.4/include/net/dsa.h linux-6.4-fbx/include/net/dsa.h --- linux-6.4/include/net/dsa.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/dsa.h 2023-06-27 11:47:16.079867270 +0200 @@ -56,6 +56,7 @@ #define DSA_TAG_PROTO_RTL8_4T_VALUE 25 #define DSA_TAG_PROTO_RZN1_A5PSW_VALUE 26 #define DSA_TAG_PROTO_LAN937X_VALUE 27 +#define DSA_TAG_PROTO_BRCM_FBX_VALUE 28 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, @@ -86,6 +87,7 @@ DSA_TAG_PROTO_RTL8_4T = DSA_TAG_PROTO_RTL8_4T_VALUE, DSA_TAG_PROTO_RZN1_A5PSW = DSA_TAG_PROTO_RZN1_A5PSW_VALUE, DSA_TAG_PROTO_LAN937X = DSA_TAG_PROTO_LAN937X_VALUE, + DSA_TAG_PROTO_BRCM_FBX = DSA_TAG_PROTO_BRCM_FBX_VALUE, }; struct dsa_switch; @@ -263,6 +265,8 @@ DSA_PORT_TYPE_DSA, DSA_PORT_TYPE_USER, } type; + bool is_def_cpu_port; + struct device_node *force_cpu_dn; const char *name; struct dsa_port *cpu_dp; diff -ruw linux-6.4/include/net/gro.h linux-6.4-fbx/include/net/gro.h --- linux-6.4/include/net/gro.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/gro.h 2023-11-07 13:38:44.058256582 +0100 @@ -446,5 +446,6 @@ gro_normal_list(napi); } +extern struct list_head offload_base; #endif /* _NET_IPV6_GRO_H */ diff -ruw linux-6.4/include/net/ieee80211_radiotap.h linux-6.4-fbx/include/net/ieee80211_radiotap.h --- linux-6.4/include/net/ieee80211_radiotap.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/ieee80211_radiotap.h 2023-11-13 17:17:11.639576253 +0100 @@ -21,7 +21,7 @@ #include /** - * struct ieee82011_radiotap_header - base radiotap header + * struct ieee80211_radiotap_header - base radiotap header */ struct ieee80211_radiotap_header { /** @@ -535,8 +535,16 @@ IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR_KNOWN = 0x00000008, IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP_KNOWN = 0x00000010, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BAD_USIG_CRC = 0x00000020, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_VALIDATE_BITS_CHECKED = 0x00000040, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_VALIDATE_BITS_OK = 0x00000080, IEEE80211_RADIOTAP_EHT_USIG_COMMON_PHY_VER = 0x00007000, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW = 0x00038000, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ = 0, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ = 1, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ = 2, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ = 3, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1 = 4, + IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_2 = 5, IEEE80211_RADIOTAP_EHT_USIG_COMMON_UL_DL = 0x00040000, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BSS_COLOR = 0x01f80000, IEEE80211_RADIOTAP_EHT_USIG_COMMON_TXOP = 0xfe000000, @@ -573,6 +581,7 @@ /** * ieee80211_get_radiotap_len - get radiotap header length + * @data: pointer to the header */ static inline u16 ieee80211_get_radiotap_len(const char *data) { diff -ruw linux-6.4/include/net/ip.h linux-6.4-fbx/include/net/ip.h --- linux-6.4/include/net/ip.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/ip.h 2023-06-27 11:47:16.079867270 +0200 @@ -705,6 +705,20 @@ #endif /* + * Functions provided by ip_ffn.c + */ + +enum { + IP_FFN_FINISH_OUT, + IP_FFN_LOCAL_IN, +}; + +extern void ip_ffn_init(void); +extern int ip_ffn_process(struct sk_buff *skb); +extern void ip_ffn_add(struct sk_buff *skb, int when); +extern void ip_ffn_flush_all(void); + +/* * Functions provided by ip_forward.c */ diff -ruw linux-6.4/include/net/ip6_tunnel.h linux-6.4-fbx/include/net/ip6_tunnel.h --- linux-6.4/include/net/ip6_tunnel.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/ip6_tunnel.h 2023-05-22 20:06:44.779868059 +0200 @@ -18,6 +18,18 @@ /* determine capability on a per-packet basis */ #define IP6_TNL_F_CAP_PER_PACKET 0x40000 +/* IPv6 tunnel FMR */ +struct __ip6_tnl_fmr { + struct __ip6_tnl_fmr *next; /* next fmr in list */ + struct in6_addr ip6_prefix; + struct in_addr ip4_prefix; + + __u8 ip6_prefix_len; + __u8 ip4_prefix_len; + __u8 ea_len; + __u8 offset; +}; + struct __ip6_tnl_parm { char name[IFNAMSIZ]; /* name of tunnel device */ int link; /* ifindex of underlying L2 interface */ @@ -29,6 +41,7 @@ __u32 flags; /* tunnel flags */ struct in6_addr laddr; /* local tunnel end-point address */ struct in6_addr raddr; /* remote tunnel end-point address */ + struct __ip6_tnl_fmr *fmrs; /* FMRs */ __be16 i_flags; __be16 o_flags; diff -ruw linux-6.4/include/net/ipv6.h linux-6.4-fbx/include/net/ipv6.h --- linux-6.4/include/net/ipv6.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/ipv6.h 2023-05-22 20:06:44.779868059 +0200 @@ -1147,6 +1147,7 @@ int ip6_output(struct net *net, struct sock *sk, struct sk_buff *skb); int ip6_forward(struct sk_buff *skb); int ip6_input(struct sk_buff *skb); +int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb); int ip6_mc_input(struct sk_buff *skb); void ip6_protocol_deliver_rcu(struct net *net, struct sk_buff *skb, int nexthdr, bool have_final); @@ -1377,4 +1378,18 @@ release_sock(sk); } +/* + * Functions provided by ipv6_ffn.c + */ + +enum { + IPV6_FFN_FINISH_OUT, + IPV6_FFN_LOCAL_IN, +}; + +extern void ipv6_ffn_init(void); +extern int ipv6_ffn_process(struct sk_buff *skb); +extern void ipv6_ffn_add(struct sk_buff *skb, int when); +extern void ipv6_ffn_flush_all(void); + #endif /* _NET_IPV6_H */ diff -ruw linux-6.4/include/net/mac80211.h linux-6.4-fbx/include/net/mac80211.h --- linux-6.4/include/net/mac80211.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/mac80211.h 2024-01-19 17:01:19.905848123 +0100 @@ -7,7 +7,7 @@ * Copyright 2007-2010 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright (C) 2015 - 2017 Intel Deutschland GmbH - * Copyright (C) 2018 - 2022 Intel Corporation + * Copyright (C) 2018 - 2023 Intel Corporation */ #ifndef MAC80211_H @@ -341,6 +341,7 @@ * @BSS_CHANGED_UNSOL_BCAST_PROBE_RESP: Unsolicited broadcast probe response * status changed. * @BSS_CHANGED_EHT_PUNCTURING: The channel puncturing bitmap changed. + * @BSS_CHANGED_MLD_VALID_LINKS: MLD valid links status changed. */ enum ieee80211_bss_change { BSS_CHANGED_ASSOC = 1<<0, @@ -376,6 +377,7 @@ BSS_CHANGED_FILS_DISCOVERY = 1<<30, BSS_CHANGED_UNSOL_BCAST_PROBE_RESP = 1<<31, BSS_CHANGED_EHT_PUNCTURING = BIT_ULL(32), + BSS_CHANGED_MLD_VALID_LINKS = BIT_ULL(33), /* when adding here, make sure to change ieee80211_reconfig */ }; @@ -643,9 +645,7 @@ * @pwr_reduction: power constraint of BSS. * @eht_support: does this BSS support EHT * @eht_puncturing: bitmap to indicate which channels are punctured in this BSS - * @csa_active: marks whether a channel switch is going on. Internally it is - * write-protected by sdata_lock and local->mtx so holding either is fine - * for read access. + * @csa_active: marks whether a channel switch is going on. * @csa_punct_bitmap: new puncturing bitmap for channel switch * @mu_mimo_owner: indicates interface owns MU-MIMO capability * @chanctx_conf: The channel context this interface is assigned to, or %NULL @@ -653,9 +653,7 @@ * path needing to access it; even though the netdev carrier will always * be off when it is %NULL there can still be races and packets could be * processed after it switches back to %NULL. - * @color_change_active: marks whether a color change is ongoing. Internally it is - * write-protected by sdata_lock and local->mtx so holding either is fine - * for read access. + * @color_change_active: marks whether a color change is ongoing. * @color_change_color: the bss color that will be used after the change. * @ht_ldpc: in AP mode, indicates interface has HT LDPC capability. * @vht_ldpc: in AP mode, indicates interface has VHT LDPC capability. @@ -776,6 +774,21 @@ bool eht_su_beamformer; bool eht_su_beamformee; bool eht_mu_beamformer; + bool eht_80mhz_full_bw_ul_mumimo; + + + /* next two fields are only present to make QCA ath12k + * compile, they are never set to useful value */ + struct ieee80211_vif *mbssid_tx_vif; + int mbssid_tx_vif_linkid; + + /* help compiling QCA code, no API to set it, value is always + * false */ + bool ap_ps_enable; + + /* help compiling QCA code, no API to set it, value is always + * 0 */ + u32 critical_update_flag; }; /** @@ -1082,6 +1095,11 @@ #define IEEE80211_MAX_TX_RETRY 31 +static inline bool ieee80211_rate_valid(struct ieee80211_tx_rate *rate) +{ + return rate->idx >= 0 && rate->count > 0; +} + static inline void ieee80211_rate_set_vht(struct ieee80211_tx_rate *rate, u8 mcs, u8 nss) { @@ -1115,7 +1133,9 @@ * not valid if the interface is an MLD since we won't know which * link the frame will be transmitted on * @hw_queue: HW queue to put the frame on, skb_get_queue_mapping() gives the AC - * @ack_frame_id: internal frame ID for TX status, used internally + * @status_data: internal data for TX status handling, assigned privately, + * see also &enum ieee80211_status_data for the internal documentation + * @status_data_idr: indicates status data is IDR allocated ID for ack frame * @tx_time_est: TX time estimate in units of 4us, used internally * @control: union part for control data * @control.rates: TX rates array to try @@ -1155,10 +1175,11 @@ /* common information */ u32 flags; u32 band:3, - ack_frame_id:13, + status_data_idr:1, + status_data:13, hw_queue:4, tx_time_est:10; - /* 2 free bits */ + /* 1 free bit */ union { struct { @@ -1172,7 +1193,11 @@ u8 use_cts_prot:1; u8 short_preamble:1; u8 skip_table:1; - /* 2 bytes free */ + + /* for injection only (bitmap) */ + u8 antennas:2; + + /* 14 bits free */ }; /* only needed before rate control */ unsigned long jiffies; @@ -1755,12 +1780,15 @@ * @IEEE80211_VIF_GET_NOA_UPDATE: request to handle NOA attributes * and send P2P_PS notification to the driver if NOA changed, even * this is not pure P2P vif. + * @IEEE80211_VIF_EML_ACTIVE: The driver indicates that EML operation is + * enabled for the interface. */ enum ieee80211_vif_flags { IEEE80211_VIF_BEACON_FILTER = BIT(0), IEEE80211_VIF_SUPPORTS_CQM_RSSI = BIT(1), IEEE80211_VIF_SUPPORTS_UAPSD = BIT(2), IEEE80211_VIF_GET_NOA_UPDATE = BIT(3), + IEEE80211_VIF_EML_ACTIVE = BIT(4), }; @@ -1790,6 +1818,9 @@ * @ps: power-save mode (STA only). This flag is NOT affected by * offchannel/dynamic_ps operations. * @aid: association ID number, valid only when @assoc is true + * @eml_cap: EML capabilities as described in P802.11be_D2.2 Figure 9-1002k. + * @eml_med_sync_delay: Medium Synchronization delay as described in + * P802.11be_D2.2 Figure 9-1002j. * @arp_addr_list: List of IPv4 addresses for hardware ARP filtering. The * may filter ARP queries targeted for other addresses than listed here. * The driver must allow ARP queries targeted for all address listed here @@ -1812,6 +1843,8 @@ bool ibss_creator; bool ps; u16 aid; + u16 eml_cap; + u16 eml_med_sync_delay; __be32 arp_addr_list[IEEE80211_BSS_ARP_ADDR_LIST_LEN]; int arp_addr_cnt; @@ -1838,6 +1871,8 @@ * @active_links: The bitmap of active links, or 0 for non-MLO. * The driver shouldn't change this directly, but use the * API calls meant for that purpose. + * @dormant_links: bitmap of valid but disabled links, or 0 for non-MLO. + * Must be a subset of valid_links. * @addr: address of this interface * @p2p: indicates whether this AP or STA interface is a p2p * interface, i.e. a GO or p2p-sta respectively @@ -1875,7 +1910,7 @@ struct ieee80211_vif_cfg cfg; struct ieee80211_bss_conf bss_conf; struct ieee80211_bss_conf __rcu *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; - u16 valid_links, active_links; + u16 valid_links, active_links, dormant_links; u8 addr[ETH_ALEN] __aligned(2); bool p2p; @@ -1901,6 +1936,27 @@ u8 drv_priv[] __aligned(sizeof(void *)); }; +/** + * ieee80211_vif_usable_links - Return the usable links for the vif + * @vif: the vif for which the usable links are requested + * Return: the usable link bitmap + */ +static inline u16 ieee80211_vif_usable_links(const struct ieee80211_vif *vif) +{ + return vif->valid_links & ~vif->dormant_links; +} + +/** + * ieee80211_vif_is_mld - Returns true iff the vif is an MLD one + * @vif: the vif + * Return: %true if the vif is an MLD, %false otherwise. + */ +static inline bool ieee80211_vif_is_mld(const struct ieee80211_vif *vif) +{ + /* valid_links != 0 indicates this vif is an MLD */ + return vif->valid_links != 0; +} + #define for_each_vif_active_link(vif, link, link_id) \ for (link_id = 0; link_id < ARRAY_SIZE((vif)->link_conf); link_id++) \ if ((!(vif)->active_links || \ @@ -1938,22 +1994,18 @@ */ struct wireless_dev *ieee80211_vif_to_wdev(struct ieee80211_vif *vif); -/** - * lockdep_vif_mutex_held - for lockdep checks on link poiners - * @vif: the interface to check - */ -static inline bool lockdep_vif_mutex_held(struct ieee80211_vif *vif) +static inline bool lockdep_vif_wiphy_mutex_held(struct ieee80211_vif *vif) { - return lockdep_is_held(&ieee80211_vif_to_wdev(vif)->mtx); + return lockdep_is_held(&ieee80211_vif_to_wdev(vif)->wiphy->mtx); } #define link_conf_dereference_protected(vif, link_id) \ rcu_dereference_protected((vif)->link_conf[link_id], \ - lockdep_vif_mutex_held(vif)) + lockdep_vif_wiphy_mutex_held(vif)) #define link_conf_dereference_check(vif, link_id) \ rcu_dereference_check((vif)->link_conf[link_id], \ - lockdep_vif_mutex_held(vif)) + lockdep_vif_wiphy_mutex_held(vif)) /** * enum ieee80211_key_flags - key flags @@ -2250,11 +2302,16 @@ struct ieee80211_he_6ghz_capa he_6ghz_capa; struct ieee80211_sta_eht_cap eht_cap; + /* help compiling QCA code, no API to set it, value is always 0 */ + u16 ru_punct_bitmap; + struct ieee80211_sta_aggregates agg; u8 rx_nss; enum ieee80211_sta_rx_bandwidth bandwidth; + enum ieee80211_sta_rx_bandwidth sta_max_bandwidth; struct ieee80211_sta_txpwr txpwr; + u32 tp_override; }; /** @@ -2704,6 +2761,8 @@ IEEE80211_HW_DETECTS_COLOR_COLLISION, IEEE80211_HW_MLO_MCAST_MULTI_LINK_TX, + IEEE80211_HW_APVLAN_NEED_MCAST_TO_UCAST, + /* keep last, obviously */ NUM_IEEE80211_HW_FLAGS }; @@ -3601,11 +3660,14 @@ * @success: whether the frame exchange was successful, only * used with the mgd_complete_tx() method, and then only * valid for auth and (re)assoc. + * @link_id: the link id on which the frame will be TX'ed. + * Only used with the mgd_prepare_tx() method. */ struct ieee80211_prep_tx_info { u16 duration; u16 subtype; u8 success:1; + int link_id; }; /** @@ -3829,6 +3891,10 @@ * the station. See @sta_pre_rcu_remove if needed. * This callback can sleep. * + * @vif_add_debugfs: Drivers can use this callback to add a debugfs vif + * directory with its files. This callback should be within a + * CONFIG_MAC80211_DEBUGFS conditional. This callback can sleep. + * * @link_add_debugfs: Drivers can use this callback to add debugfs files * when a link is added to a mac80211 vif. This callback should be within * a CONFIG_MAC80211_DEBUGFS conditional. This callback can sleep. @@ -4033,11 +4099,15 @@ * This callback must be atomic. * * @get_et_sset_count: Ethtool API to get string-set count. + * Note that the wiphy mutex is not held for this callback since it's + * expected to return a static value. * * @get_et_stats: Ethtool API to get a set of u64 stats. * * @get_et_strings: Ethtool API to get a set of strings to describe stats * and perhaps other supported types of ethtool data-sets. + * Note that the wiphy mutex is not held for this callback since it's + * expected to return a static value. * * @mgd_prepare_tx: Prepare for transmitting a management frame for association * before associated. In multi-channel scenarios, a virtual interface is @@ -4242,6 +4312,8 @@ struct sk_buff *skb); int (*start)(struct ieee80211_hw *hw); void (*stop)(struct ieee80211_hw *hw); + int (*set_powered)(struct ieee80211_hw *hw); + int (*get_powered)(struct ieee80211_hw *hw, bool *up, bool *busy); #ifdef CONFIG_PM int (*suspend)(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan); int (*resume)(struct ieee80211_hw *hw); @@ -4324,6 +4396,8 @@ int (*sta_remove)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_sta *sta); #ifdef CONFIG_MAC80211_DEBUGFS + void (*vif_add_debugfs)(struct ieee80211_hw *hw, + struct ieee80211_vif *vif); void (*link_add_debugfs)(struct ieee80211_hw *hw, struct ieee80211_vif *vif, struct ieee80211_bss_conf *link_conf, @@ -4472,7 +4546,8 @@ struct ieee80211_prep_tx_info *info); void (*mgd_protect_tdls_discover)(struct ieee80211_hw *hw, - struct ieee80211_vif *vif); + struct ieee80211_vif *vif, + unsigned int link_id); int (*add_chanctx)(struct ieee80211_hw *hw, struct ieee80211_chanctx_conf *ctx); @@ -4510,7 +4585,8 @@ struct ieee80211_channel_switch *ch_switch); int (*post_channel_switch)(struct ieee80211_hw *hw, - struct ieee80211_vif *vif); + struct ieee80211_vif *vif, + struct ieee80211_bss_conf *link_conf); void (*abort_channel_switch)(struct ieee80211_hw *hw, struct ieee80211_vif *vif); void (*channel_switch_rx_beacon)(struct ieee80211_hw *hw, @@ -5135,6 +5211,10 @@ void ieee80211_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); +void ieee80211_tx_status_8023(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct sk_buff *skb); + /** * ieee80211_tx_status_ext - extended transmit status callback * @@ -6505,11 +6585,14 @@ * ieee80211_chswitch_done - Complete channel switch process * @vif: &struct ieee80211_vif pointer from the add_interface callback. * @success: make the channel switch successful or not + * @link_id: the link_id on which the switch was done. Ignored if success is + * false. * * Complete the channel switch post-process: set the new operational channel * and wake up the suspended queues. */ -void ieee80211_chswitch_done(struct ieee80211_vif *vif, bool success); +void ieee80211_chswitch_done(struct ieee80211_vif *vif, bool success, + unsigned int link_id); /** * ieee80211_channel_switch_disconnect - disconnect due to channel switch error @@ -6578,6 +6661,7 @@ * marks frames marked in the bitmap as having been filtered. Afterwards, it * checks if any frames in the window starting from @ssn can now be released * (in case they were only waiting for frames that were filtered.) + * (Only work correctly if @max_rx_aggregation_subframes <= 64 frames) */ void ieee80211_mark_rx_ba_filtered_frames(struct ieee80211_sta *pubsta, u8 tid, u16 ssn, u64 filtered, @@ -6597,6 +6681,13 @@ void ieee80211_send_bar(struct ieee80211_vif *vif, u8 *ra, u16 tid, u16 ssn); /** + * same as ieee80211_send_bar but for given STA, allow sending to a + * STA on AP_VLAN and get a valid control->sta in the driver + */ +void ieee80211_send_bar_sta(struct ieee80211_sta *pubsta, + u16 tid, u16 ssn); + +/** * ieee80211_manage_rx_ba_offl - helper to queue an RX BA work * @vif: &struct ieee80211_vif pointer from the add_interface callback * @addr: station mac address @@ -6862,6 +6953,48 @@ } /** + * ieee80211_get_he_iftype_cap_vif - return HE capabilities for sband/vif + * @sband: the sband to search for the iftype on + * @vif: the vif to get the iftype from + * + * Return: pointer to the struct ieee80211_sta_he_cap, or %NULL is none found + */ +static inline const struct ieee80211_sta_he_cap * +ieee80211_get_he_iftype_cap_vif(const struct ieee80211_supported_band *sband, + struct ieee80211_vif *vif) +{ + return ieee80211_get_he_iftype_cap(sband, ieee80211_vif_type_p2p(vif)); +} + +/** + * ieee80211_get_he_6ghz_capa_vif - return HE 6 GHz capabilities + * @sband: the sband to search for the STA on + * @vif: the vif to get the iftype from + * + * Return: the 6GHz capabilities + */ +static inline __le16 +ieee80211_get_he_6ghz_capa_vif(const struct ieee80211_supported_band *sband, + struct ieee80211_vif *vif) +{ + return ieee80211_get_he_6ghz_capa(sband, ieee80211_vif_type_p2p(vif)); +} + +/** + * ieee80211_get_eht_iftype_cap_vif - return ETH capabilities for sband/vif + * @sband: the sband to search for the iftype on + * @vif: the vif to get the iftype from + * + * Return: pointer to the struct ieee80211_sta_eht_cap, or %NULL is none found + */ +static inline const struct ieee80211_sta_eht_cap * +ieee80211_get_eht_iftype_cap_vif(const struct ieee80211_supported_band *sband, + struct ieee80211_vif *vif) +{ + return ieee80211_get_eht_iftype_cap(sband, ieee80211_vif_type_p2p(vif)); +} + +/** * ieee80211_update_mu_groups - set the VHT MU-MIMO groud data * * @vif: the specified virtual interface @@ -7367,4 +7500,74 @@ void ieee80211_set_active_links_async(struct ieee80211_vif *vif, u16 active_links); +/* + * force dtim count value on given VIF + */ +void ieee80211_force_dtim(struct ieee80211_vif *vif, + unsigned int dtim_count); + +/* + * special helpers for QCA ath12 non upstream code + */ +static inline +void ieee80211_csa_finish_mlo(struct ieee80211_vif *vif, + unsigned int link_id) +{ + /* FIXME: implement correctly */ + ieee80211_csa_finish(vif); +} + +static inline +bool ieee80211_beacon_cntdwn_is_complete_mlo(struct ieee80211_vif *vif, + unsigned int link_id) +{ + /* FIXME: implement correctly */ + return ieee80211_beacon_cntdwn_is_complete(vif); +} + +static inline +void ieee80211_color_change_finish_mlo(struct ieee80211_vif *vif, + unsigned int link_id) +{ + /* FIXME: implement correctly */ + return ieee80211_color_change_finish(vif); +} + +static inline +u8 ieee80211_beacon_update_cntdwn_mlo(struct ieee80211_vif *vif, + unsigned int link_id) +{ + /* FIXME: implement correctly */ + return ieee80211_beacon_update_cntdwn(vif); +} + +static inline +struct sk_buff *ieee80211_get_fils_discovery_tmpl_mlo(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + unsigned int link_id) +{ + /* FIXME: implement correctly */ + return ieee80211_get_fils_discovery_tmpl(hw, vif); +} + +static inline +struct sk_buff * +ieee80211_get_unsol_bcast_probe_resp_tmpl_mlo(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + unsigned int link_id) +{ + /* FIXME: implement correctly */ + return ieee80211_get_unsol_bcast_probe_resp_tmpl(hw, vif); +} + +static inline +void +ieee80211_obss_color_collision_notify_mlo(struct ieee80211_vif *vif, + u64 color_bitmap, gfp_t gfp, + unsigned int link_id) +{ + /* FIXME: implement correctly */ + return ieee80211_obss_color_collision_notify(vif, color_bitmap, gfp); +} + #endif /* MAC80211_H */ diff -ruw linux-6.4/include/net/netfilter/nf_conntrack.h linux-6.4-fbx/include/net/netfilter/nf_conntrack.h --- linux-6.4/include/net/netfilter/nf_conntrack.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/netfilter/nf_conntrack.h 2023-05-22 20:06:44.787868272 +0200 @@ -53,6 +53,8 @@ /* only used when new connection is allocated: */ atomic_t count; unsigned int expect_count; + u8 sysctl_auto_assign_helper; + bool auto_assign_helper_warned; /* only used from work queues, configuration plane, and so on: */ unsigned int users4; @@ -118,6 +120,9 @@ u_int32_t secmark; #endif + union nf_conntrack_man_proto nat_src_proto_min; + union nf_conntrack_man_proto nat_src_proto_max; + /* Extensions */ struct nf_ct_ext *ext; diff -ruw linux-6.4/include/net/netfilter/nf_conntrack_expect.h linux-6.4-fbx/include/net/netfilter/nf_conntrack_expect.h --- linux-6.4/include/net/netfilter/nf_conntrack_expect.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/netfilter/nf_conntrack_expect.h 2023-03-13 14:08:39.114429164 +0100 @@ -58,13 +58,24 @@ #endif struct rcu_head rcu; + + /* private expect information. */ + char data[32] __aligned(8); }; +#define NF_CT_EXPECT_BUILD_BUG_ON(structsize) \ + BUILD_BUG_ON((structsize) > sizeof_field(struct nf_conntrack_expect, data)) + static inline struct net *nf_ct_exp_net(struct nf_conntrack_expect *exp) { return nf_ct_net(exp->master); } +static inline void *nf_ct_exp_data(struct nf_conntrack_expect *exp) +{ + return (void *)exp->data; +} + #define NF_CT_EXP_POLICY_NAME_LEN 16 struct nf_conntrack_expect_policy { diff -ruw linux-6.4/include/net/netns/conntrack.h linux-6.4-fbx/include/net/netns/conntrack.h --- linux-6.4/include/net/netns/conntrack.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/netns/conntrack.h 2023-05-22 20:06:44.791868378 +0200 @@ -100,6 +100,7 @@ u8 sysctl_log_invalid; /* Log invalid packets */ u8 sysctl_events; u8 sysctl_acct; + u8 sysctl_auto_assign_helper; u8 sysctl_tstamp; u8 sysctl_checksum; diff -ruw linux-6.4/include/net/page_pool.h linux-6.4-fbx/include/net/page_pool.h --- linux-6.4/include/net/page_pool.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/page_pool.h 2024-01-19 17:01:19.905848123 +0100 @@ -377,6 +377,21 @@ page->dma_addr_upper = upper_32_bits(addr); } +static inline void page_pool_clear_recycle_flag(struct page *page) +{ + page->pp_recycle_flag= 0; +} + +static inline void page_pool_set_recycled_flag(struct page *page) +{ + page->pp_recycle_flag = 1; +} + +static inline bool page_pool_is_recycled(struct page *page) +{ + return page->pp_recycle_flag & 1; +} + static inline bool is_page_pool_compiled_in(void) { #ifdef CONFIG_PAGE_POOL diff -ruw linux-6.4/include/net/regulatory.h linux-6.4-fbx/include/net/regulatory.h --- linux-6.4/include/net/regulatory.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/regulatory.h 2023-11-07 13:38:44.058256582 +0100 @@ -140,17 +140,6 @@ * otherwise initiating radiation is not allowed. This will enable the * relaxations enabled under the CFG80211_REG_RELAX_NO_IR configuration * option - * @REGULATORY_IGNORE_STALE_KICKOFF: the regulatory core will _not_ make sure - * all interfaces on this wiphy reside on allowed channels. If this flag - * is not set, upon a regdomain change, the interfaces are given a grace - * period (currently 60 seconds) to disconnect or move to an allowed - * channel. Interfaces on forbidden channels are forcibly disconnected. - * Currently these types of interfaces are supported for enforcement: - * NL80211_IFTYPE_ADHOC, NL80211_IFTYPE_STATION, NL80211_IFTYPE_AP, - * NL80211_IFTYPE_AP_VLAN, NL80211_IFTYPE_MONITOR, - * NL80211_IFTYPE_P2P_CLIENT, NL80211_IFTYPE_P2P_GO, - * NL80211_IFTYPE_P2P_DEVICE. The flag will be set by default if a device - * includes any modes unsupported for enforcement checking. * @REGULATORY_WIPHY_SELF_MANAGED: for devices that employ wiphy-specific * regdom management. These devices will ignore all regdom changes not * originating from their own wiphy. @@ -177,7 +166,7 @@ REGULATORY_COUNTRY_IE_FOLLOW_POWER = BIT(3), REGULATORY_COUNTRY_IE_IGNORE = BIT(4), REGULATORY_ENABLE_RELAX_NO_IR = BIT(5), - REGULATORY_IGNORE_STALE_KICKOFF = BIT(6), + /* reuse bit 6 next time */ REGULATORY_WIPHY_SELF_MANAGED = BIT(7), }; @@ -224,6 +213,7 @@ u32 flags; u32 dfs_cac_ms; bool has_wmm; + s8 psd; }; struct ieee80211_regdomain { diff -ruw linux-6.4/include/net/sock.h linux-6.4-fbx/include/net/sock.h --- linux-6.4/include/net/sock.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/sock.h 2023-06-27 11:47:16.083867379 +0200 @@ -187,6 +187,7 @@ unsigned char skc_reuseport:1; unsigned char skc_ipv6only:1; unsigned char skc_net_refcnt:1; + unsigned char skc_reuse_conflict; int skc_bound_dev_if; union { struct hlist_node skc_bind_node; @@ -383,6 +384,7 @@ #define sk_reuseport __sk_common.skc_reuseport #define sk_ipv6only __sk_common.skc_ipv6only #define sk_net_refcnt __sk_common.skc_net_refcnt +#define sk_reuse_conflict __sk_common.skc_reuse_conflict #define sk_bound_dev_if __sk_common.skc_bound_dev_if #define sk_bind_node __sk_common.skc_bind_node #define sk_prot __sk_common.skc_prot @@ -959,6 +961,7 @@ SOCK_XDP, /* XDP is attached */ SOCK_TSTAMP_NEW, /* Indicates 64 bit timestamps always */ SOCK_RCVMARK, /* Receive SO_MARK ancillary data with packet */ + SOCK_UDP_DUP_UNICAST, }; #define SK_FLAGS_TIMESTAMP ((1UL << SOCK_TIMESTAMP) | (1UL << SOCK_TIMESTAMPING_RX_SOFTWARE)) diff -ruw linux-6.4/include/net/udp.h linux-6.4-fbx/include/net/udp.h --- linux-6.4/include/net/udp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/net/udp.h 2023-11-07 13:38:44.058256582 +0100 @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include diff -ruw linux-6.4/include/uapi/asm-generic/socket.h linux-6.4-fbx/include/uapi/asm-generic/socket.h --- linux-6.4/include/uapi/asm-generic/socket.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/asm-generic/socket.h 2023-05-22 20:06:44.851869974 +0200 @@ -30,9 +30,10 @@ #define SO_PEERCRED 17 #define SO_RCVLOWAT 18 #define SO_SNDLOWAT 19 +#endif + #define SO_RCVTIMEO_OLD 20 #define SO_SNDTIMEO_OLD 21 -#endif /* Security levels - as per NRL IPv6 - don't actually do anything */ #define SO_SECURITY_AUTHENTICATION 22 @@ -132,6 +133,8 @@ #define SO_RCVMARK 75 +#define SO_UDP_DUP_UNICAST 100 + #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 || (defined(__x86_64__) && defined(__ILP32__)) diff -ruw linux-6.4/include/uapi/linux/batadv_packet.h linux-6.4-fbx/include/uapi/linux/batadv_packet.h --- linux-6.4/include/uapi/linux/batadv_packet.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/batadv_packet.h 2023-12-12 17:24:34.163627207 +0100 @@ -44,6 +44,7 @@ BATADV_ELP = 0x03, BATADV_OGM2 = 0x04, BATADV_MCAST = 0x05, + BATADV_FBX = 0x3f, /* 0x40 - 0x7f: unicast */ #define BATADV_UNICAST_MIN 0x40 BATADV_UNICAST = 0x40, @@ -87,6 +88,14 @@ }; /** + * enum batadv_v_flags - flags used in B.A.T.M.A.N. V OGM2 packets + * @BATADV_V_HALF_DUPLEX: Halfduplex penalty should be applied to throughput + */ +enum batadv_v_flags { + BATADV_V_HALF_DUPLEX = 1UL << 7, +}; + +/** * enum batadv_icmp_packettype - ICMP message types * @BATADV_ECHO_REPLY: success reply to BATADV_ECHO_REQUEST * @BATADV_DESTINATION_UNREACHABLE: failure when route to destination not found @@ -174,6 +183,7 @@ * @BATADV_TVLV_TT: translation table tvlv * @BATADV_TVLV_ROAM: roaming advertisement tvlv * @BATADV_TVLV_MCAST: multicast capability tvlv + * @BATADV_TVLV_FBX: fbx specific tvlv */ enum batadv_tvlv_type { BATADV_TVLV_GW = 0x01, @@ -182,6 +192,7 @@ BATADV_TVLV_TT = 0x04, BATADV_TVLV_ROAM = 0x05, BATADV_TVLV_MCAST = 0x06, + BATADV_TVLV_FBX = 0xff, }; #pragma pack(2) @@ -628,6 +639,61 @@ __u8 reserved[3]; }; +/** + * struct batadv_fbx_packet - FBX specific packets + * @packet_type: batman-adv packet type, part of the general header + * @version: batman-adv protocol version, part of the general header + * @subtype: FBX packet subtype (see batadv_fbx_subtype) + * @rev: FBX specific version for compatibility + * @seqno: an alway increasing sequence number, not checked for now + */ +struct batadv_fbx_packet { + __u8 packet_type; + __u8 version; + __u8 subtype; /* see batadv_fbx_subtype detection message types */ + __u8 rev; + __be32 seqno; +}; +#define BATADV_FBX_HLEN sizeof(struct batadv_fbx_packet) + +/** + * enum batadv_fbx_subtype - FBX packet subtypes + * @BATADV_FBX_MTU_PROBE: Big message sent to a neigh to probe link MTU + * @BATADV_FBX_MTU_RESP: MTU acknowledgment from receiver to sender + */ +enum batadv_fbx_subtype { + BATADV_FBX_SUB_UNUSED = 0, + BATADV_FBX_SUB_MTU_PROBE, + BATADV_FBX_SUB_MTU_RESP, + BATADV_FBX_SUB_SLAP, + /* keep last */ + BATADV_FBX_SUB_LAST, +}; + +/** + * struct batadv_fbx_mtu_packet - FBX MTU probing packet + * @hdr: Common FBX header + * @mtu: The mtu this probe / resp packet relates to + */ +struct batadv_fbx_mtu_packet { + struct batadv_fbx_packet hdr; + __be16 mtu; +}; + +#define BATADV_FBX_MTU_HLEN sizeof(struct batadv_fbx_mtu_packet) + +/** + * struct batadv_fbx_slap_packet - FBX SLAP ID packet + * @hdr: Common FBX header + * @prio: SLAP Prio of the originator node + */ +struct batadv_fbx_slap_packet { + struct batadv_fbx_packet hdr; + __be32 prio; +}; + +#define BATADV_FBX_SLAP_HLEN sizeof(struct batadv_fbx_slap_packet) + #pragma pack() #endif /* _UAPI_LINUX_BATADV_PACKET_H_ */ diff -ruw linux-6.4/include/uapi/linux/batman_adv.h linux-6.4-fbx/include/uapi/linux/batman_adv.h --- linux-6.4/include/uapi/linux/batman_adv.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/batman_adv.h 2023-12-12 17:24:34.163627207 +0100 @@ -11,6 +11,7 @@ #define BATADV_NL_MCAST_GROUP_CONFIG "config" #define BATADV_NL_MCAST_GROUP_TPMETER "tpmeter" +#define BATADV_NL_MCAST_GROUP_ROUTE "route" /** * enum batadv_tt_client_flags - TT client specific flags @@ -49,6 +50,12 @@ BATADV_TT_CLIENT_ISOLA = (1 << 5), /** + * @BATADV_TT_CLIENT_SEEN: this global client has been actually + * detected to be part of the originator and has not yet expired + */ + BATADV_TT_CLIENT_SEEN = (1 << 6), + + /** * @BATADV_TT_CLIENT_NOPURGE: this client should never be removed from * the table */ @@ -481,6 +488,11 @@ */ BATADV_ATTR_MULTICAST_FANOUT, + /** + * @BATADV_ATTF_FBX: defines FBX specific NL attributes + */ + BATADV_ATTR_FBX, + /* add attributes above here, update the policy in netlink.c */ /** @@ -500,6 +512,52 @@ }; /** + * enum batadv_nl_fbx_attrs - batman-adv netlink attributes + */ +enum batadv_nl_fbx_attr { + /** + * @BATADV_ATTR_FBX_MTU: defines the MTU this neighbor can safely use. + */ + BATADV_ATTR_FBX_MTU, + + /** + * @BATADV_ATTR_FBX_SLAP_MASTER_MAC: Show current SLAP master address + */ + BATADV_ATTR_FBX_SLAP_MASTER_ADDRESS, + + /** + * @BATADV_ATTR_FBX_SLAP_MASTER_PRIO: Show current SLAP master priority + */ + BATADV_ATTR_FBX_SLAP_MASTER_PRIO, + + /** + * @BATADV_ATTR_FBX_SLAP_IFINDEX: defines the currently selected SLAP + * interface + */ + BATADV_ATTR_FBX_SLAP_IFINDEX, + + /** + * @BATADV_ATTR_FBX_SLAP_PRIO: defines the current SLAP priority + */ + BATADV_ATTR_FBX_SLAP_PRIO, + + /** + * @__BATADV_ATTR_FBX_AFTER_LAST: internal use + */ + __BATADV_ATTR_FBX_AFTER_LAST, + + /** + * @NUM_BATADV_FBX_ATTR: total number of batadv_nl_fbx_attrs available + */ + NUM_BATADV_ATTR_FBX = __BATADV_ATTR_FBX_AFTER_LAST, + + /** + * @BATADV_ATTR_FBX_MAX: highest attribute number currently defined + */ + BATADV_ATTR_FBX_MAX = __BATADV_ATTR_FBX_AFTER_LAST - 1 +}; + +/** * enum batadv_nl_commands - supported batman-adv netlink commands */ enum batadv_nl_commands { @@ -613,6 +671,21 @@ */ BATADV_CMD_SET_VLAN, + /** + * @BATADV_CMD_ADD_ROUTE: Add new route to reach originator + */ + BATADV_CMD_ADD_ROUTE, + + /** + * @BATADV_CMD_DEL_ROUTE: Del route to originator + */ + BATADV_CMD_DEL_ROUTE, + + /** + * @BATADV_CMD_CHANGE_ROUTE: Modify an existing route to originator + */ + BATADV_CMD_CHANGE_ROUTE, + /* add new commands above here */ /** diff -ruw linux-6.4/include/uapi/linux/ethtool.h linux-6.4-fbx/include/uapi/linux/ethtool.h --- linux-6.4/include/uapi/linux/ethtool.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/ethtool.h 2023-05-31 17:11:03.421680714 +0200 @@ -294,6 +294,8 @@ ETHTOOL_PHY_DOWNSHIFT, ETHTOOL_PHY_FAST_LINK_DOWN, ETHTOOL_PHY_EDPD, + ETHTOOL_PHY_BROKEN, + /* * Add your fresh new phy tunable attribute above and remember to update * phy_tunable_strings[] in net/ethtool/common.c @@ -681,6 +683,7 @@ * @ETH_SS_STATS_ETH_MAC: names of IEEE 802.3 MAC statistics * @ETH_SS_STATS_ETH_CTRL: names of IEEE 802.3 MAC Control statistics * @ETH_SS_STATS_RMON: names of RMON statistics + * @ETH_SS_PHYLINK_IFTYPES: names of phylink interface types * * @ETH_SS_COUNT: number of defined string sets */ @@ -706,6 +709,7 @@ ETH_SS_STATS_ETH_MAC, ETH_SS_STATS_ETH_CTRL, ETH_SS_STATS_RMON, + ETH_SS_PHYLINK_IFTYPES, /* add new constants above here */ ETH_SS_COUNT @@ -1576,6 +1580,91 @@ #define ETHTOOL_FEC_BASER (1 << ETHTOOL_FEC_BASER_BIT) #define ETHTOOL_FEC_LLRS (1 << ETHTOOL_FEC_LLRS_BIT) +/** + * struct ethtool_shaper_params + * @cmd: %ETHTOOL_GSHAPER_PARAMS / %ETHTOOL_SSHAPER_PARAMS + */ +struct ethtool_shaper_params { + __u32 cmd; + + __u64 rate; + __u32 burst; + __u32 mtu; +}; + +/** + * struct ethtool_epon_param + * @cmd: Command number = %ETHTOOL_GEPON_PARAM or %ETHTOOL_SEPON_* + */ +struct ethtool_epon_param { + __u32 cmd; + __u8 discovery_rx; + __u8 registered; + __u16 llid; + __u32 burst_cap; + __u32 lasermon_event_count; + __u32 change_count; + __u32 keys_update_id; + __u8 key_sci[8]; + __u8 down_key0[16]; + __u8 down_key1[16]; + __u32 down_encrypt; + __u32 down_last_rx_encrypted; + __u32 down_last_rx_key_id; + __u16 mcast_llid; + __u16 pad; +}; + +/* + * currently a 1:1 mapping for SFP SM in drivers/net/phy/sfp.c + */ +enum { + ETHTOOL_SFP_S_DOWN = 0, + ETHTOOL_SFP_S_FAIL, + ETHTOOL_SFP_S_WAIT, + ETHTOOL_SFP_S_INIT, + ETHTOOL_SFP_S_INIT_PHY, + ETHTOOL_SFP_S_INIT_TX_FAULT, + ETHTOOL_SFP_S_WAIT_LOS, + ETHTOOL_SFP_S_LINK_UP, + ETHTOOL_SFP_S_TX_FAULT, + ETHTOOL_SFP_S_REINIT, + ETHTOOL_SFP_S_TX_DISABLE, +}; + +/** + * struct ethtool_sfp_state + * @cmd: Command number = %ETHTOOL_GSFP_STATE + */ +struct ethtool_sfp_state { + __u32 cmd; + + __u32 fsm_state; + + __u8 o_pwren; + __u8 o_txdis; + __u8 i_presence; + __u8 i_rxlos; + __u8 i_txfault; +}; + +/** + * struct ethtool_phylink_if_mode + * @cmd: %ETHTOOL_GPHYLINK_IFTYPE / %ETHTOOL_SPHYLINK_IFTYPE + */ +struct ethtool_phylink_iftype { + __u32 cmd; + + /* stringified phy_interface_t (enum is not part of UAPI and + * is not stable), uses string from phy_modes() */ + char iftype[ETH_GSTRING_LEN]; + + __u32 autoneg_en; + + /* enum MLO_AN_xxx, read-only */ + __u32 mode; +}; + /* CMDs currently supported */ #define ETHTOOL_GSET 0x00000001 /* DEPRECATED, Get settings. * Please use ETHTOOL_GLINKSETTINGS @@ -1671,6 +1760,23 @@ #define ETHTOOL_GFECPARAM 0x00000050 /* Get FEC settings */ #define ETHTOOL_SFECPARAM 0x00000051 /* Set FEC settings */ +#define ETHTOOL_GEPON_PARAM 0x00000052 /* Get EPON params */ +#define ETHTOOL_SEPON_KEYS 0x00000053 /* Set EPON encryption keys */ +#define ETHTOOL_SEPON_ENCRYPT 0x00000054 /* Set EPON encryption keys */ +#define ETHTOOL_SEPON_RESTART 0x00000055 /* restart epon link */ +#define ETHTOOL_SEPON_BURST 0x00000056 /* update burst value */ +#define ETHTOOL_SEPON_ADD_MCLLID 0x00000057 /* add epon llid */ +#define ETHTOOL_SEPON_DEL_MCLLID 0x00000058 /* remove epon llid */ +#define ETHTOOL_SEPON_CLR_MCLLID 0x00000059 /* remove all epon llid */ + +#define ETHTOOL_GSFP_STATE 0x00000060 /* get SFP state (IOs/FSM) */ + +#define ETHTOOL_SSHAPER_PARAMS 0x00000061 /* set HW TX shaper params */ +#define ETHTOOL_GSHAPER_PARAMS 0x00000062 /* get HW TX shaper params */ + +#define ETHTOOL_GPHYLINK_IFTYPE 0x00000063 /* get phylink interface type */ +#define ETHTOOL_SPHYLINK_IFTYPE 0x00000064 /* set phylink interface type */ + /* compatibility with older code */ #define SPARC_ETH_GSET ETHTOOL_GSET #define SPARC_ETH_SSET ETHTOOL_SSET @@ -1787,6 +1893,12 @@ ETHTOOL_LINK_MODE_10baseT1S_Full_BIT = 99, ETHTOOL_LINK_MODE_10baseT1S_Half_BIT = 100, ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT = 101, + ETHTOOL_LINK_MODE_1000basePX_D_Full_BIT = 102, + ETHTOOL_LINK_MODE_1000basePX_U_Full_BIT = 103, + ETHTOOL_LINK_MODE_10000basePR_D_Full_BIT = 104, + ETHTOOL_LINK_MODE_10000basePR_U_Full_BIT = 105, + ETHTOOL_LINK_MODE_10000_1000basePRX_D_Full_BIT = 106, + ETHTOOL_LINK_MODE_10000_1000basePRX_U_Full_BIT = 107, /* must be last entry */ __ETHTOOL_LINK_MODE_MASK_NBITS diff -ruw linux-6.4/include/uapi/linux/if_ether.h linux-6.4-fbx/include/uapi/linux/if_ether.h --- linux-6.4/include/uapi/linux/if_ether.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/if_ether.h 2024-02-08 19:19:27.692597465 +0100 @@ -55,6 +55,7 @@ #define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ #define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ #define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ +#define ETH_P_FBXVLAN 0x1337 /* Freebox specific VLAN type [ NOT AN OFFICIALLY REGISTERED ID ] */ #define ETH_P_BATMAN 0x4305 /* B.A.T.M.A.N.-Advanced packet [ NOT AN OFFICIALLY REGISTERED ID ] */ #define ETH_P_DEC 0x6000 /* DEC Assigned proto */ #define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ diff -ruw linux-6.4/include/uapi/linux/if_tun.h linux-6.4-fbx/include/uapi/linux/if_tun.h --- linux-6.4/include/uapi/linux/if_tun.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/if_tun.h 2023-05-22 20:06:44.879870719 +0200 @@ -62,6 +62,32 @@ #define TUNSETCARRIER _IOW('T', 226, int) #define TUNGETDEVNETNS _IO('T', 227) + +struct smalltun_rule { + __u8 proto; + __be16 src_port_start; + __be16 src_port_end; + __be16 dst_port_start; + __be16 dst_port_end; +}; + +struct smalltun_fp { + __be32 inner_src; + __be32 inner_dst; + + __u32 af; + __u8 outer_src[16]; + __u8 outer_dst[16]; + __be16 outer_src_port; + __be16 outer_dst_port; + + struct smalltun_rule rules[8]; + __u32 rule_count; +}; + +#define TUNSMALLTUNSETFP _IOW('T', 228, struct smalltun_fp) +#define TUNSMALLTUNDELFP _IOW('T', 229, struct smalltun_fp) + /* TUNSETIFF ifr flags */ #define IFF_TUN 0x0001 #define IFF_TAP 0x0002 diff -ruw linux-6.4/include/uapi/linux/if_tunnel.h linux-6.4-fbx/include/uapi/linux/if_tunnel.h --- linux-6.4/include/uapi/linux/if_tunnel.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/if_tunnel.h 2023-05-22 20:06:44.879870719 +0200 @@ -77,10 +77,23 @@ IFLA_IPTUN_ENCAP_DPORT, IFLA_IPTUN_COLLECT_METADATA, IFLA_IPTUN_FWMARK, + IFLA_IPTUN_FMRS, __IFLA_IPTUN_MAX, }; #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) +enum { + IFLA_IPTUN_FMR_UNSPEC, + IFLA_IPTUN_FMR_IP6_PREFIX, + IFLA_IPTUN_FMR_IP4_PREFIX, + IFLA_IPTUN_FMR_IP6_PREFIX_LEN, + IFLA_IPTUN_FMR_IP4_PREFIX_LEN, + IFLA_IPTUN_FMR_EA_LEN, + IFLA_IPTUN_FMR_OFFSET, + __IFLA_IPTUN_FMR_MAX, +}; +#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) + enum tunnel_encap_types { TUNNEL_ENCAP_NONE, TUNNEL_ENCAP_FOU, diff -ruw linux-6.4/include/uapi/linux/input-event-codes.h linux-6.4-fbx/include/uapi/linux/input-event-codes.h --- linux-6.4/include/uapi/linux/input-event-codes.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/input-event-codes.h 2023-05-22 20:06:44.879870719 +0200 @@ -803,6 +803,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff diff -ruw linux-6.4/include/uapi/linux/libc-compat.h linux-6.4-fbx/include/uapi/linux/libc-compat.h --- linux-6.4/include/uapi/linux/libc-compat.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/libc-compat.h 2023-02-27 14:15:14.847571831 +0100 @@ -49,11 +49,11 @@ #ifndef _UAPI_LIBC_COMPAT_H #define _UAPI_LIBC_COMPAT_H -/* We have included glibc headers... */ -#if defined(__GLIBC__) +/* We have included libc headers... */ +#if !defined(__KERNEL__) -/* Coordinate with glibc net/if.h header. */ -#if defined(_NET_IF_H) && defined(__USE_MISC) +/* Coordinate with libc net/if.h header. */ +#if defined(_NET_IF_H) && (!defined(__GLIBC__) || defined(__USE_MISC)) /* GLIBC headers included first so don't define anything * that would already be defined. */ @@ -65,9 +65,11 @@ /* Everything up to IFF_DYNAMIC, matches net/if.h until glibc 2.23 */ #define __UAPI_DEF_IF_NET_DEVICE_FLAGS 0 /* For the future if glibc adds IFF_LOWER_UP, IFF_DORMANT and IFF_ECHO */ +#ifndef IFF_ECHO #ifndef __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO #define __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO 1 #endif /* __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO */ +#endif /* IFF_ECHO */ #else /* _NET_IF_H */ @@ -170,7 +172,7 @@ * or we are being included in the kernel, then define everything * that we need. Check for previous __UAPI_* definitions to give * unsupported C libraries a way to opt out of any kernel definition. */ -#else /* !defined(__GLIBC__) */ +#else /* !defined(__KERNEL__) */ /* Definitions for if.h */ #ifndef __UAPI_DEF_IF_IFCONF @@ -262,6 +264,6 @@ #define __UAPI_DEF_XATTR 1 #endif -#endif /* __GLIBC__ */ +#endif /* __KERNEL__ */ #endif /* _UAPI_LIBC_COMPAT_H */ diff -ruw linux-6.4/include/uapi/linux/nl80211.h linux-6.4-fbx/include/uapi/linux/nl80211.h --- linux-6.4/include/uapi/linux/nl80211.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/nl80211.h 2024-04-19 16:04:28.965735994 +0200 @@ -11,7 +11,7 @@ * Copyright 2008 Jouni Malinen * Copyright 2008 Colin McCabe * Copyright 2015-2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -167,7 +167,7 @@ * following events occur. * a) Expiration of hardware timer whose expiration time is set to maximum * coalescing delay of matching coalesce rule. - * b) Coalescing buffer in hardware reaches it's limit. + * b) Coalescing buffer in hardware reaches its limit. * c) Packet doesn't match any of the configured coalesce rules. * * User needs to configure following parameters for creating a coalesce @@ -326,7 +326,7 @@ /** * DOC: Multi-Link Operation * - * In Multi-Link Operation, a connection between to MLDs utilizes multiple + * In Multi-Link Operation, a connection between two MLDs utilizes multiple * links. To use this in nl80211, various commands and responses now need * to or will include the new %NL80211_ATTR_MLO_LINKS attribute. * Additionally, various commands that need to operate on a specific link @@ -335,6 +335,15 @@ */ /** + * DOC: OWE DH IE handling offload + * + * By setting @NL80211_EXT_FEATURE_OWE_OFFLOAD flag, drivers can indicate + * kernel/application space to avoid DH IE handling. When this flag is + * advertised, the driver/device will take care of DH IE inclusion and + * processing of peer DH IE to generate PMK. + */ + +/** * enum nl80211_commands - supported nl80211 commands * * @NL80211_CMD_UNSPEC: unspecified command to catch errors @@ -1309,6 +1318,11 @@ * The number of peers that HW timestamping can be enabled for concurrently * is indicated by %NL80211_ATTR_MAX_HW_TIMESTAMP_PEERS. * + * @NL80211_CMD_LINKS_REMOVED: Notify userspace about the removal of STA MLD + * setup links due to AP MLD removing the corresponding affiliated APs with + * Multi-Link reconfiguration. %NL80211_ATTR_MLO_LINKS is used to provide + * information about the removed STA MLD setup links. + * * @NL80211_CMD_MAX: highest used command number * @__NL80211_CMD_AFTER_LAST: internal use */ @@ -1562,6 +1576,8 @@ NL80211_CMD_SET_HW_TIMESTAMP, + NL80211_CMD_LINKS_REMOVED, + /* add new commands above here */ /* used to define NL80211_CMD_MAX below */ @@ -2683,11 +2699,13 @@ * * @NL80211_ATTR_FILS_DISCOVERY: Optional parameter to configure FILS * discovery. It is a nested attribute, see - * &enum nl80211_fils_discovery_attributes. + * &enum nl80211_fils_discovery_attributes. Userspace should pass an empty + * nested attribute to disable this feature and delete the templates. * * @NL80211_ATTR_UNSOL_BCAST_PROBE_RESP: Optional parameter to configure * unsolicited broadcast probe response. It is a nested attribute, see - * &enum nl80211_unsol_bcast_probe_resp_attributes. + * &enum nl80211_unsol_bcast_probe_resp_attributes. Userspace should pass an empty + * nested attribute to disable this feature and delete the templates. * * @NL80211_ATTR_S1G_CAPABILITY: S1G Capability information element (from * association request when used with NL80211_CMD_NEW_STATION) @@ -2805,6 +2823,9 @@ * index. If the userspace includes more RNR elements than number of * MBSSID elements then these will be added in every EMA beacon. * + * @NL80211_ATTR_MLO_LINK_DISABLED: Flag attribute indicating that the link is + * disabled. + * * @NUM_NL80211_ATTR: total number of nl80211_attrs available * @NL80211_ATTR_MAX: highest attribute number currently defined * @__NL80211_ATTR_AFTER_LAST: internal use @@ -3341,6 +3362,8 @@ NL80211_ATTR_EMA_RNR_ELEMS, + NL80211_ATTR_MLO_LINK_DISABLED, + /* add attributes here, update the policy in nl80211.c */ __NL80211_ATTR_AFTER_LAST, @@ -3348,6 +3371,9 @@ NL80211_ATTR_MAX = __NL80211_ATTR_AFTER_LAST - 1 }; +#define NL80211_QBC_UPDATE_NODE_METRICS_IE 1 +#define NL80211_QBC_UPDATE_PATH_METRICS_IE 2 + /* source-level API compatibility */ #define NL80211_ATTR_SCAN_GENERATION NL80211_ATTR_GENERATION #define NL80211_ATTR_MESH_PARAMS NL80211_ATTR_MESH_CONFIG @@ -3667,6 +3693,13 @@ * (u8, see &enum nl80211_eht_gi) * @NL80211_RATE_INFO_EHT_RU_ALLOC: EHT RU allocation, if not present then * non-OFDMA was used (u8, see &enum nl80211_eht_ru_alloc) + * @NL80211_RATE_INFO_S1G_MCS: S1G MCS index (u8, 0-10) + * @NL80211_RATE_INFO_S1G_NSS: S1G NSS value (u8, 1-4) + * @NL80211_RATE_INFO_1_MHZ_WIDTH: 1 MHz S1G rate + * @NL80211_RATE_INFO_2_MHZ_WIDTH: 2 MHz S1G rate + * @NL80211_RATE_INFO_4_MHZ_WIDTH: 4 MHz S1G rate + * @NL80211_RATE_INFO_8_MHZ_WIDTH: 8 MHz S1G rate + * @NL80211_RATE_INFO_16_MHZ_WIDTH: 16 MHz S1G rate * @__NL80211_RATE_INFO_AFTER_LAST: internal use */ enum nl80211_rate_info { @@ -3693,6 +3726,13 @@ NL80211_RATE_INFO_EHT_NSS, NL80211_RATE_INFO_EHT_GI, NL80211_RATE_INFO_EHT_RU_ALLOC, + NL80211_RATE_INFO_S1G_MCS, + NL80211_RATE_INFO_S1G_NSS, + NL80211_RATE_INFO_1_MHZ_WIDTH, + NL80211_RATE_INFO_2_MHZ_WIDTH, + NL80211_RATE_INFO_4_MHZ_WIDTH, + NL80211_RATE_INFO_8_MHZ_WIDTH, + NL80211_RATE_INFO_16_MHZ_WIDTH, /* keep last */ __NL80211_RATE_INFO_AFTER_LAST, @@ -4187,6 +4227,8 @@ * as the primary or any of the secondary channels isn't possible * @NL80211_FREQUENCY_ATTR_NO_EHT: EHT operation is not allowed on this channel * in current regulatory domain. + * @NL80211_FREQUENCY_ATTR_PSD: Power spectral density (in dBm) that + * is allowed on this channel in current regulatory domain. * @NL80211_FREQUENCY_ATTR_MAX: highest frequency attribute number * currently defined * @__NL80211_FREQUENCY_ATTR_AFTER_LAST: internal use @@ -4225,6 +4267,7 @@ NL80211_FREQUENCY_ATTR_16MHZ, NL80211_FREQUENCY_ATTR_NO_320MHZ, NL80211_FREQUENCY_ATTR_NO_EHT, + NL80211_FREQUENCY_ATTR_PSD, /* keep last */ __NL80211_FREQUENCY_ATTR_AFTER_LAST, @@ -4325,6 +4368,8 @@ * a given frequency range. The value is in mBm (100 * dBm). * @NL80211_ATTR_DFS_CAC_TIME: DFS CAC time in milliseconds. * If not present or 0 default CAC time will be used. + * @NL80211_ATTR_POWER_RULE_PSD: power spectral density (in dBm). + * This could be negative. * @NL80211_REG_RULE_ATTR_MAX: highest regulatory rule attribute number * currently defined * @__NL80211_REG_RULE_ATTR_AFTER_LAST: internal use @@ -4342,6 +4387,8 @@ NL80211_ATTR_DFS_CAC_TIME, + NL80211_ATTR_POWER_RULE_PSD, + /* keep last */ __NL80211_REG_RULE_ATTR_AFTER_LAST, NL80211_REG_RULE_ATTR_MAX = __NL80211_REG_RULE_ATTR_AFTER_LAST - 1 @@ -4424,6 +4471,8 @@ * @NL80211_RRF_NO_160MHZ: 160MHz operation not allowed * @NL80211_RRF_NO_HE: HE operation not allowed * @NL80211_RRF_NO_320MHZ: 320MHz operation not allowed + * @NL80211_RRF_NO_EHT: EHT operation not allowed + * @NL80211_RRF_PSD: Ruleset has power spectral density value */ enum nl80211_reg_rule_flags { NL80211_RRF_NO_OFDM = 1<<0, @@ -4443,6 +4492,8 @@ NL80211_RRF_NO_160MHZ = 1<<16, NL80211_RRF_NO_HE = 1<<17, NL80211_RRF_NO_320MHZ = 1<<18, + NL80211_RRF_NO_EHT = 1<<19, + NL80211_RRF_PSD = 1<<20, }; #define NL80211_RRF_PASSIVE_SCAN NL80211_RRF_NO_IR @@ -5010,7 +5061,7 @@ * elements from a Beacon frame (bin); not present if no Beacon frame has * yet been received * @NL80211_BSS_CHAN_WIDTH: channel width of the control channel - * (u32, enum nl80211_bss_scan_width) + * (u32, enum nl80211_bss_scan_width) - No longer used! * @NL80211_BSS_BEACON_TSF: TSF of the last received beacon (u64) * (not present if no beacon frame has been received yet) * @NL80211_BSS_PRESP_DATA: the data in @NL80211_BSS_INFORMATION_ELEMENTS and @@ -5255,6 +5306,7 @@ }; #define NL80211_HE_NSS_MAX 8 +#define NL80211_EHT_NSS_MAX 16 /** * struct nl80211_txrate_he - HE MCS/NSS txrate bitmap * @mcs: MCS bitmap table for each NSS (array index 0 for 1 stream, etc.) @@ -6372,6 +6424,12 @@ * in authentication and deauthentication frames sent to unassociated peer * using @NL80211_CMD_FRAME. * + * @NL80211_EXT_FEATURE_OWE_OFFLOAD: Driver/Device wants to do OWE DH IE + * handling in station mode. + * + * @NL80211_EXT_FEATURE_OWE_OFFLOAD_AP: Driver/Device wants to do OWE DH IE + * handling in AP mode. + * * @NUM_NL80211_EXT_FEATURES: number of extended features. * @MAX_NL80211_EXT_FEATURES: highest extended feature index. */ @@ -6443,6 +6501,8 @@ NL80211_EXT_FEATURE_PUNCT, NL80211_EXT_FEATURE_SECURE_NAN, NL80211_EXT_FEATURE_AUTH_AND_DEAUTH_RANDOM_TA, + NL80211_EXT_FEATURE_OWE_OFFLOAD, + NL80211_EXT_FEATURE_OWE_OFFLOAD_AP, /* add new features before the definition below */ NUM_NL80211_EXT_FEATURES, @@ -6567,6 +6627,7 @@ * these channels would passively be scanned. Also note that when the flag * is set, in addition to the colocated APs, PSC channels would also be * scanned if the user space has asked for it. + * @NL80211_SCAN_FLAG_UPDATE_DFS: scan results will update DFS state */ enum nl80211_scan_flags { NL80211_SCAN_FLAG_LOW_PRIORITY = 1<<0, @@ -6584,6 +6645,7 @@ NL80211_SCAN_FLAG_MIN_PREQ_CONTENT = 1<<12, NL80211_SCAN_FLAG_FREQ_KHZ = 1<<13, NL80211_SCAN_FLAG_COLOCATED_6GHZ = 1<<14, + NL80211_SCAN_FLAG_UPDATE_DFS = 1<<15, }; /** @@ -7578,7 +7640,7 @@ * @NL80211_FILS_DISCOVERY_ATTR_INT_MIN: Minimum packet interval (u32, TU). * Allowed range: 0..10000 (TU = Time Unit) * @NL80211_FILS_DISCOVERY_ATTR_INT_MAX: Maximum packet interval (u32, TU). - * Allowed range: 0..10000 (TU = Time Unit) + * Allowed range: 0..10000 (TU = Time Unit). If set to 0, the feature is disabled. * @NL80211_FILS_DISCOVERY_ATTR_TMPL: Template data for FILS discovery action * frame including the headers. * @@ -7611,7 +7673,8 @@ * * @NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INT: Maximum packet interval (u32, TU). * Allowed range: 0..20 (TU = Time Unit). IEEE P802.11ax/D6.0 - * 26.17.2.3.2 (AP behavior for fast passive scanning). + * 26.17.2.3.2 (AP behavior for fast passive scanning). If set to 0, the feature is + * disabled. * @NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_TMPL: Unsolicited broadcast probe response * frame template (binary). * diff -ruw linux-6.4/include/uapi/linux/serial_core.h linux-6.4-fbx/include/uapi/linux/serial_core.h --- linux-6.4/include/uapi/linux/serial_core.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/serial_core.h 2023-05-22 20:06:44.903871357 +0200 @@ -279,4 +279,7 @@ /* Sunplus UART */ #define PORT_SUNPLUS 123 +/* BCM63xx HS */ +#define PORT_BCM63XX_HS 123 + #endif /* _UAPILINUX_SERIAL_CORE_H */ diff -ruw linux-6.4/include/uapi/linux/sockios.h linux-6.4-fbx/include/uapi/linux/sockios.h --- linux-6.4/include/uapi/linux/sockios.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/sockios.h 2023-02-27 20:40:38.056744387 +0100 @@ -153,6 +153,14 @@ #define SIOCSHWTSTAMP 0x89b0 /* set and get config */ #define SIOCGHWTSTAMP 0x89b1 /* get config */ +/* fbxbridge call */ +#define SIOCGFBXBRIDGE 0x89c0 /* fbxbridge support */ +#define SIOCSFBXBRIDGE 0x89c1 /* Set fbxbridge options */ + +/* fbxdiverter call */ +#define SIOCGFBXDIVERT 0x89d0 /* fbxdiverter support */ +#define SIOCSFBXDIVERT 0x89d1 /* Set fbxdiverter options */ + /* Device private ioctl calls */ /* diff -ruw linux-6.4/include/uapi/linux/stddef.h linux-6.4-fbx/include/uapi/linux/stddef.h --- linux-6.4/include/uapi/linux/stddef.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/stddef.h 2023-11-07 13:38:44.062256691 +0100 @@ -45,3 +45,7 @@ TYPE NAME[]; \ } #endif + +#ifndef __counted_by +#define __counted_by(m) +#endif diff -ruw linux-6.4/include/uapi/linux/tcp.h linux-6.4-fbx/include/uapi/linux/tcp.h --- linux-6.4/include/uapi/linux/tcp.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/tcp.h 2023-05-22 20:06:44.911871570 +0200 @@ -134,6 +134,8 @@ #define TCP_REPAIR_OFF 0 #define TCP_REPAIR_OFF_NO_WP -1 /* Turn off without window probes */ +#define TCP_LINEAR_RTO 128 /* force use of linear timeouts */ + struct tcp_repair_opt { __u32 opt_code; __u32 opt_val; diff -ruw linux-6.4/include/uapi/linux/tty.h linux-6.4-fbx/include/uapi/linux/tty.h --- linux-6.4/include/uapi/linux/tty.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/include/uapi/linux/tty.h 2023-05-22 20:06:44.911871570 +0200 @@ -39,8 +39,9 @@ #define N_MCTP 28 /* MCTP-over-serial */ #define N_DEVELOPMENT 29 /* Manual out-of-tree testing */ #define N_CAN327 30 /* ELM327 based OBD-II interfaces */ +#define N_REMOTI 31 /* RemoTI over UART */ /* Always the newest line discipline + 1 */ -#define NR_LDISCS 31 +#define NR_LDISCS 32 #endif /* _UAPI_LINUX_TTY_H */ diff -ruw linux-6.4/init/Kconfig linux-6.4-fbx/init/Kconfig --- linux-6.4/init/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/init/Kconfig 2023-05-22 20:06:44.935872208 +0200 @@ -139,6 +139,15 @@ Maximum of each of the number of arguments and environment variables passed to init from the kernel command line. + +config CROSS_COMPILE + string "Cross-compiler tool prefix" + help + Same as running 'make CROSS_COMPILE=prefix-' but stored for + default make runs in this kernel build directory. You don't + need to set this unless you want the configured kernel build + directory to select the cross-compiler automatically. + config COMPILE_TEST bool "Compile also drivers which will not load" depends on HAS_IOMEM @@ -779,6 +788,44 @@ There is no additional runtime cost to printk with this enabled. +config FBX_DECRYPT_INITRD + bool "Decrypt initrd at boot" + depends on BLK_DEV_RAM + default n + +choice + prompt "initrd decryption encryption flavor" + default FBX_DECRYPT_INITRD_RC4 + +config FBX_DECRYPT_INITRD_RC4 + depends on FBX_DECRYPT_INITRD + bool "RC4" + +config FBX_DECRYPT_INITRD_CHACHA20 + depends on FBX_DECRYPT_INITRD + bool "CHACHA20" + select CRYPTO_CHACHA20 + +endchoice + +config FBX_DECRYPT_INITRD_KEY + string "Decryption key" + depends on FBX_DECRYPT_INITRD + +config FBX_DECRYPT_INITRD_NONCE + string "Decryption nonce/IV" + depends on FBX_DECRYPT_INITRD_CHACHA20 + +config FBX_VERIFY_INITRD + bool "Verify initrd at boot" + depends on FBX_DECRYPT_INITRD + select CRYPTO_RSA + select CRYPTO_SHA256 + +config FBX_VERIFY_INITRD_PUBKEY + string "Public key path for initrd verify" + depends on FBX_VERIFY_INITRD + # # Architectures with an unreliable sched_clock() should select this: # diff -ruw linux-6.4/init/Makefile linux-6.4-fbx/init/Makefile --- linux-6.4/init/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/init/Makefile 2023-05-22 20:06:44.935872208 +0200 @@ -15,6 +15,14 @@ obj-y += init_task.o +obj-$(CONFIG_FBX_DECRYPT_INITRD)+= fbx_decrypt_initrd.o +obj-$(CONFIG_FBX_DECRYPT_INITRD_RC4) += rc4.o +obj-$(CONFIG_FBX_VERIFY_INITRD) += fbx_initrd_pub_key.o + +PUB_KEY_PATH_UNQUOTED = $(patsubst "%",%,$(CONFIG_FBX_VERIFY_INITRD_PUBKEY)) + +init/fbx_initrd_pub_key.o: $(PUB_KEY_PATH_UNQUOTED) + mounts-y := do_mounts.o mounts-$(CONFIG_BLK_DEV_RAM) += do_mounts_rd.o mounts-$(CONFIG_BLK_DEV_INITRD) += do_mounts_initrd.o diff -ruw linux-6.4/init/init_task.c linux-6.4-fbx/init/init_task.c --- linux-6.4/init/init_task.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/init/init_task.c 2023-05-22 20:06:44.939872315 +0200 @@ -75,6 +75,7 @@ .stack = init_stack, .usage = REFCOUNT_INIT(2), .flags = PF_KTHREAD, + .exec_mode = EXEC_MODE_UNLIMITED, .prio = MAX_PRIO - 20, .static_prio = MAX_PRIO - 20, .normal_prio = MAX_PRIO - 20, diff -ruw linux-6.4/init/initramfs.c linux-6.4-fbx/init/initramfs.c --- linux-6.4/init/initramfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/init/initramfs.c 2023-05-22 20:06:44.939872315 +0200 @@ -18,6 +18,7 @@ #include #include #include +#include static __initdata bool csum_present; static __initdata u32 io_csum; @@ -668,6 +669,10 @@ ssize_t written; struct file *file; loff_t pos = 0; +#ifdef CONFIG_FBX_DECRYPT_INITRD + int ret; + extern int fbx_decrypt_initrd(char *start, u32 size); +#endif unpack_to_rootfs(__initramfs_start, __initramfs_size); @@ -677,6 +682,15 @@ if (IS_ERR(file)) return; +#ifdef CONFIG_FBX_DECRYPT_INITRD + ret = fbx_decrypt_initrd((char*)initrd_start, + initrd_end - initrd_start); + if (ret) { + printk(KERN_ERR "Decrypt failed: %i\n", ret); + return; + } +#endif + written = xwrite(file, (char *)initrd_start, initrd_end - initrd_start, &pos); if (written != initrd_end - initrd_start) diff -ruw linux-6.4/kernel/fork.c linux-6.4-fbx/kernel/fork.c --- linux-6.4/kernel/fork.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/kernel/fork.c 2023-06-27 11:47:16.103867923 +0200 @@ -1195,6 +1195,11 @@ tsk->mm_cid_active = 0; tsk->migrate_from_cpu = -1; #endif + /* + * inherit parent exec_mode. + */ + tsk->exec_mode = orig->exec_mode; + return tsk; free_stack: diff -ruw linux-6.4/kernel/module/Kconfig linux-6.4-fbx/kernel/module/Kconfig --- linux-6.4/kernel/module/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/kernel/module/Kconfig 2023-05-22 20:06:45.039874975 +0200 @@ -385,6 +385,10 @@ one per line. The path can be absolute, or relative to the kernel source tree. +config UNUSED_KSYMS_WHITELIST_SYMS + string "Whitelist of symbols name to keep in ksymtab" + depends on TRIM_UNUSED_KSYMS + config MODULES_TREE_LOOKUP def_bool y depends on PERF_EVENTS || TRACING || CFI_CLANG diff -ruw linux-6.4/kernel/sys.c linux-6.4-fbx/kernel/sys.c --- linux-6.4/kernel/sys.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/kernel/sys.c 2023-05-22 20:06:45.091876358 +0200 @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -2708,6 +2709,18 @@ error = !!test_bit(MMF_VM_MERGE_ANY, &me->mm->flags); break; #endif + case PR_SET_EXEC_MODE: + if (arg2 != EXEC_MODE_UNLIMITED && + arg2 != EXEC_MODE_ONCE && + arg2 != EXEC_MODE_DENIED) + return -EINVAL; + + if (arg2 > current->exec_mode) + return -EPERM; + current->exec_mode = arg2; + return 0; + case PR_GET_EXEC_MODE: + return current->exec_mode; default: error = -EINVAL; break; diff -ruw linux-6.4/lib/Kconfig linux-6.4-fbx/lib/Kconfig --- linux-6.4/lib/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/lib/Kconfig 2023-05-22 20:06:45.147877847 +0200 @@ -728,6 +728,13 @@ config OBJAGG tristate "objagg" if COMPILE_TEST +config ARCH_HAS_FBXSERIAL + bool + +config FBXSERIAL + bool "fbxserial" + select CRC32 + endmenu config GENERIC_IOREMAP diff -ruw linux-6.4/lib/Makefile linux-6.4-fbx/lib/Makefile --- linux-6.4/lib/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/lib/Makefile 2023-05-22 20:06:45.151877954 +0200 @@ -430,3 +430,4 @@ ifeq ($(CONFIG_FORTIFY_SOURCE),y) $(obj)/string.o: $(obj)/$(TEST_FORTIFY_LOG) endif +obj-$(CONFIG_FBXSERIAL) += fbxserial.o diff -ruw linux-6.4/mm/Kconfig linux-6.4-fbx/mm/Kconfig --- linux-6.4/mm/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/mm/Kconfig 2023-05-22 20:06:45.207879443 +0200 @@ -709,6 +709,13 @@ config ARCH_SUPPORTS_MEMORY_FAILURE bool +config PAGE_FRAG_CACHE_ORDER + int "page order size of page fragment allocator" + default 3 + help + This allocator is used by networking only for skb->head allocation. + A large value speeds up allocation but causes memory fragmentation. + config MEMORY_FAILURE depends on MMU depends on ARCH_SUPPORTS_MEMORY_FAILURE diff -ruw linux-6.4/mm/memtest.c linux-6.4-fbx/mm/memtest.c --- linux-6.4/mm/memtest.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/mm/memtest.c 2023-12-05 17:14:42.315715453 +0100 @@ -28,6 +28,7 @@ 0x7a6c7258554e494cULL, /* yeah ;-) */ }; +#ifndef CONFIG_X86 // original code static void __init reserve_bad_mem(u64 pattern, phys_addr_t start_bad, phys_addr_t end_bad) { pr_info(" %016llx bad mem addr %pa - %pa reserved\n", @@ -68,19 +69,83 @@ early_memtest_done = true; } +#else // fbx6hd +/* + * Count memory errors in segment [a,b] + * If an error is detected, remove segment from memory pool. + */ +static void __init test_segment(unsigned long a, unsigned long b, u64 pat) +{ + int err_count = 0; + u64 *p; + + /* + * If an exception, such as page fault, is required to prefetch the data, + * then the software prefetch instruction retires without prefetching data. + */ + for (p = __va(a); p != __va(b); p += 4) { + __builtin_prefetch(p+64); + if (p[0] != pat || p[1] != pat || p[2] != pat || p[3] != pat) + ++err_count; + } + + if (err_count) { + pr_warn("BAD+RAM: %lx-%lx: N=%d", a, b, err_count); + memblock_reserve(a, b-a); + } +} + +typedef u64 u128 __attribute__ ((__vector_size__ (16))); + +static void __init write_pattern(unsigned long a, unsigned long b, u64 pat) +{ + u128 val = (u128){ pat, pat }; + u128 *p = __va(a), *q = __va(b); + kernel_fpu_begin(); + asm("movdqa %0, %%xmm0" : : "m" (val)); + for (/**/; p != q; ++p) + asm("movntdq %%xmm0, %0" : "=m" (*p)); + kernel_fpu_end(); +} + +#define SEGMENT_SIZE (1 << 16) // 64K + +static void __init memtest(u64 pattern, phys_addr_t start_phys, phys_addr_t size) +{ + /* On fbx6hd, ulong is wide enough to store physical addresses */ + unsigned long curr = start_phys; + unsigned long next = ALIGN(curr + 1, SEGMENT_SIZE); + unsigned long end = start_phys + size; + + // Check alignment for correct loop unrolling + if (curr & 0x1f || end & 0x1f) { + pr_warn("BAD+RAM: %lx-%lx: misaligned", curr, end); + return; + } + + write_pattern(curr, end, pattern); + + while (curr < end) { + if (next > end) + next = end; + test_segment(curr, next, pattern); + curr = next; + next += SEGMENT_SIZE; + } +} +#endif static void __init do_one_pass(u64 pattern, phys_addr_t start, phys_addr_t end) { u64 i; phys_addr_t this_start, this_end; + pr_info("pattern %016llx\n", cpu_to_be64(pattern)); for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &this_start, &this_end, NULL) { this_start = clamp(this_start, start, end); this_end = clamp(this_end, start, end); if (this_start < this_end) { - pr_info(" %pa - %pa pattern %016llx\n", - &this_start, &this_end, cpu_to_be64(pattern)); memtest(pattern, this_start, this_end - this_start); } } diff -ruw linux-6.4/mm/page_alloc.c linux-6.4-fbx/mm/page_alloc.c --- linux-6.4/mm/page_alloc.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/mm/page_alloc.c 2023-05-22 20:06:45.263880933 +0200 @@ -4887,18 +4887,24 @@ { struct page *page = NULL; gfp_t gfp = gfp_mask; + unsigned int order; #if (PAGE_SIZE < PAGE_FRAG_CACHE_MAX_SIZE) gfp_mask |= __GFP_COMP | __GFP_NOWARN | __GFP_NORETRY | __GFP_NOMEMALLOC; page = alloc_pages_node(NUMA_NO_NODE, gfp_mask, PAGE_FRAG_CACHE_MAX_ORDER); + order = PAGE_FRAG_CACHE_MAX_ORDER; nc->size = page ? PAGE_FRAG_CACHE_MAX_SIZE : PAGE_SIZE; #endif - if (unlikely(!page)) + if (unlikely(!page)) { page = alloc_pages_node(NUMA_NO_NODE, gfp, 0); + order = 0; + } nc->va = page ? page_address(page) : NULL; + if (page) + set_page_owner_frag_cache(page, order, nc); return page; } diff -ruw linux-6.4/mm/vmalloc.c linux-6.4-fbx/mm/vmalloc.c --- linux-6.4/mm/vmalloc.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/mm/vmalloc.c 2023-06-27 11:47:16.127868575 +0200 @@ -3340,6 +3340,19 @@ EXPORT_SYMBOL_GPL(__vmalloc_node); #endif +/* + * __vmalloc_pgprot(): same as __vmalloc, but with a pgprot_t parameter. + * + * required for IntelCE drivers. + */ +void *__vmalloc_pgprot(unsigned long size, gfp_t gfp_mask, pgprot_t prot) +{ + return __vmalloc_node_range(size, 1, VMALLOC_START, VMALLOC_END, + gfp_mask, prot, 0, NUMA_NO_NODE, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(__vmalloc_pgprot); + void *__vmalloc(unsigned long size, gfp_t gfp_mask) { return __vmalloc_node(size, 1, gfp_mask, NUMA_NO_NODE, diff -ruw linux-6.4/net/8021q/Kconfig linux-6.4-fbx/net/8021q/Kconfig --- linux-6.4/net/8021q/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/8021q/Kconfig 2024-02-08 19:19:27.692597465 +0100 @@ -39,3 +39,12 @@ supersedes GVRP and is not backwards-compatible. If unsure, say N. + +config VLAN_FBX + bool "Freebox specific VLAN ethertype to bypass dump switches" + depends on VLAN_8021Q + help + Select this to enable FBX VLAN specific ethertype to bypass + switches that drops 802.1q packets + + If unsure, say N. diff -ruw linux-6.4/net/8021q/vlan.c linux-6.4-fbx/net/8021q/vlan.c --- linux-6.4/net/8021q/vlan.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/8021q/vlan.c 2023-05-22 20:06:45.287881571 +0200 @@ -211,7 +211,7 @@ /* Attach a VLAN device to a mac address (ie Ethernet Card). * Returns 0 if the device was created or a negative error code otherwise. */ -static int register_vlan_device(struct net_device *real_dev, u16 vlan_id) +int register_vlan_device(struct net_device *real_dev, u16 vlan_id) { struct net_device *new_dev; struct vlan_dev_priv *vlan; diff -ruw linux-6.4/net/8021q/vlan.h linux-6.4-fbx/net/8021q/vlan.h --- linux-6.4/net/8021q/vlan.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/8021q/vlan.h 2024-02-08 19:19:27.692597465 +0100 @@ -16,6 +16,9 @@ enum vlan_protos { VLAN_PROTO_8021Q = 0, VLAN_PROTO_8021AD, +#ifdef CONFIG_VLAN_FBX + VLAN_PROTO_FBX, +#endif VLAN_PROTO_NUM, }; @@ -43,6 +46,10 @@ return VLAN_PROTO_8021Q; case htons(ETH_P_8021AD): return VLAN_PROTO_8021AD; +#ifdef CONFIG_VLAN_FBX + case htons(ETH_P_FBXVLAN): + return VLAN_PROTO_FBX; +#endif default: WARN(1, "invalid VLAN protocol: 0x%04x\n", ntohs(proto)); return -EINVAL; diff -ruw linux-6.4/net/8021q/vlan_core.c linux-6.4-fbx/net/8021q/vlan_core.c --- linux-6.4/net/8021q/vlan_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/8021q/vlan_core.c 2023-05-22 20:06:45.287881571 +0200 @@ -99,6 +99,12 @@ } EXPORT_SYMBOL(__vlan_find_dev_deep_rcu); +struct net_device *vlan_dev_upper_dev(const struct net_device *dev) +{ + return vlan_dev_priv(dev)->real_dev; +} +EXPORT_SYMBOL(vlan_dev_upper_dev); + struct net_device *vlan_dev_real_dev(const struct net_device *dev) { struct net_device *ret = vlan_dev_priv(dev)->real_dev; diff -ruw linux-6.4/net/8021q/vlan_netlink.c linux-6.4-fbx/net/8021q/vlan_netlink.c --- linux-6.4/net/8021q/vlan_netlink.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/8021q/vlan_netlink.c 2024-02-08 19:19:27.692597465 +0100 @@ -63,6 +63,9 @@ switch (nla_get_be16(data[IFLA_VLAN_PROTOCOL])) { case htons(ETH_P_8021Q): case htons(ETH_P_8021AD): +#ifdef CONFIG_VLAN_FBX + case htons(ETH_P_FBXVLAN): +#endif break; default: NL_SET_ERR_MSG_MOD(extack, "Invalid VLAN protocol"); diff -ruw linux-6.4/net/Kconfig linux-6.4-fbx/net/Kconfig --- linux-6.4/net/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/Kconfig 2023-12-12 17:24:34.163627207 +0100 @@ -32,6 +32,10 @@ This option can be selected by other options that need compat netlink messages. +config NET_PROMISC_MESSAGES + bool "show promisc/allmulti status change in kernel log" + default y + config COMPAT_NETLINK_MESSAGES def_bool y depends on COMPAT @@ -60,6 +64,19 @@ menu "Networking options" +config NETSKBPAD + int "Size reserved by dev_alloc_skb" + default 32 + +config NETRXTHREAD + bool "Do rx network processing in kernel thread" + depends on BROKEN_ON_SMP + +config NETRXTHREAD_RX_QUEUE + int "Number of rx queues" + default 1 + depends on NETRXTHREAD + source "net/packet/Kconfig" source "net/unix/Kconfig" source "net/tls/Kconfig" @@ -236,6 +253,8 @@ source "net/tipc/Kconfig" source "net/atm/Kconfig" source "net/l2tp/Kconfig" +source "net/fbxatm/Kconfig" +source "net/fbxbridge/Kconfig" source "net/802/Kconfig" source "net/bridge/Kconfig" source "net/dsa/Kconfig" diff -ruw linux-6.4/net/Makefile linux-6.4-fbx/net/Makefile --- linux-6.4/net/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/Makefile 2023-12-12 17:24:34.163627207 +0100 @@ -39,6 +39,12 @@ obj-$(CONFIG_STREAM_PARSER) += strparser/ obj-$(CONFIG_ATM) += atm/ obj-$(CONFIG_L2TP) += l2tp/ +ifneq ($(CONFIG_FBXATM),) +obj-y += fbxatm/ +endif +ifneq ($(CONFIG_FBXBRIDGE),) +obj-y += fbxbridge/ +endif obj-$(CONFIG_PHONET) += phonet/ ifneq ($(CONFIG_VLAN_8021Q),) obj-y += 8021q/ diff -ruw linux-6.4/net/batman-adv/Kconfig linux-6.4-fbx/net/batman-adv/Kconfig --- linux-6.4/net/batman-adv/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/Kconfig 2023-12-21 17:30:06.449516617 +0100 @@ -94,3 +94,31 @@ messages using the generic tracing infrastructure of the kernel. BATMAN_ADV_DEBUG must also be selected to get trace events for batadv_dbg. + +config BATMAN_ADV_FBX + bool "B.A.T.M.A.N. FBX specific features" + depends on BATMAN_ADV + help + This enables FBX specific options to be selected (e.g. MTU + discovery, SLAP protocol). + +config BATMAN_ADV_FBX_MTU + bool "B.A.T.M.A.N. FBX path max MTU discovery feature" + depends on BATMAN_ADV_FBX + help + This enables FBX path max MTU discovery protocol. + +config BATMAN_ADV_FBX_SLAP + bool "B.A.T.M.A.N. FBX SLAP" + depends on BATMAN_ADV_FBX + help + This enables FBX SLAP (simple loop avoidance protocol) to handle + blend of LAN and B.A.T.M.A.N traffic on ethernet port correctly + in Freebox configuration + +config BATMAN_ADV_FBX_PERIF_ROUTER + bool "B.A.T.M.A.N. FBX perif router" + depends on BATMAN_ADV_FBX && BATMAN_ADV_BATMAN_V + help + Keep track of per interface best router to reach a specific + originator. diff -ruw linux-6.4/net/batman-adv/Makefile linux-6.4-fbx/net/batman-adv/Makefile --- linux-6.4/net/batman-adv/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/Makefile 2023-12-21 17:30:06.449516617 +0100 @@ -4,6 +4,7 @@ # Marek Lindner, Simon Wunderlich obj-$(CONFIG_BATMAN_ADV) += batman-adv.o + batman-adv-y += bat_algo.o batman-adv-y += bat_iv_ogm.o batman-adv-$(CONFIG_BATMAN_ADV_BATMAN_V) += bat_v.o @@ -30,5 +31,9 @@ batman-adv-y += tp_meter.o batman-adv-y += translation-table.o batman-adv-y += tvlv.o +batman-adv-$(CONFIG_BATMAN_ADV_FBX) += fbx/fbx.o +batman-adv-$(CONFIG_BATMAN_ADV_FBX_MTU) += fbx/mtu.o +batman-adv-$(CONFIG_BATMAN_ADV_FBX_SLAP) += fbx/slap.o +batman-adv-$(CONFIG_BATMAN_ADV_FBX_PERIF_ROUTER) += fbx/router.o CFLAGS_trace.o := -I$(src) diff -ruw linux-6.4/net/batman-adv/bat_v.c linux-6.4-fbx/net/batman-adv/bat_v.c --- linux-6.4/net/batman-adv/bat_v.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/bat_v.c 2023-12-12 17:24:34.163627207 +0100 @@ -38,6 +38,8 @@ #include "hard-interface.h" #include "hash.h" #include "log.h" +#include "fbx/fbx.h" +#include "fbx/mtu.h" #include "netlink.h" #include "originator.h" @@ -130,6 +132,7 @@ batadv_v_neigh_dump_neigh(struct sk_buff *msg, u32 portid, u32 seq, struct batadv_hardif_neigh_node *hardif_neigh) { + struct batadv_priv *bat_priv; void *hdr; unsigned int last_seen_msecs; u32 throughput; @@ -154,6 +157,9 @@ nla_put_u32(msg, BATADV_ATTR_THROUGHPUT, throughput)) goto nla_put_failure; + bat_priv = netdev_priv(hardif_neigh->if_incoming->soft_iface); + batadv_fbx_nl(bat_priv, BATADV_CMD_GET_NEIGHBORS, NULL, msg, + hardif_neigh); genlmsg_end(msg, hdr); return 0; @@ -311,6 +317,9 @@ if (best && nla_put_flag(msg, BATADV_ATTR_FLAG_BEST)) goto nla_put_failure; + batadv_fbx_nl(bat_priv, BATADV_CMD_GET_ORIGINATORS, NULL, msg, + orig_node); + genlmsg_end(msg, hdr); return 0; diff -ruw linux-6.4/net/batman-adv/bat_v_elp.c linux-6.4-fbx/net/batman-adv/bat_v_elp.c --- linux-6.4/net/batman-adv/bat_v_elp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/bat_v_elp.c 2023-12-12 17:24:34.163627207 +0100 @@ -140,7 +140,8 @@ } default_throughput: - if (!(hard_iface->bat_v.flags & BATADV_WARNING_DEFAULT)) { + if (hard_iface->soft_iface && + !(hard_iface->bat_v.flags & BATADV_WARNING_DEFAULT)) { batadv_info(hard_iface->soft_iface, "WiFi driver or ethtool info does not provide information about link speeds on interface %s, therefore defaulting to hardcoded throughput values of %u.%1u Mbps. Consider overriding the throughput manually or checking your driver.\n", hard_iface->net_dev->name, @@ -505,7 +506,7 @@ struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface); struct batadv_elp_packet *elp_packet; struct batadv_hard_iface *primary_if; - struct ethhdr *ethhdr = (struct ethhdr *)skb_mac_header(skb); + struct ethhdr *ethhdr; bool res; int ret = NET_RX_DROP; @@ -513,6 +514,7 @@ if (!res) goto free_skb; + ethhdr = eth_hdr(skb); if (batadv_is_my_mac(bat_priv, ethhdr->h_source)) goto free_skb; diff -ruw linux-6.4/net/batman-adv/bat_v_ogm.c linux-6.4-fbx/net/batman-adv/bat_v_ogm.c --- linux-6.4/net/batman-adv/bat_v_ogm.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/bat_v_ogm.c 2023-12-21 17:30:06.449516617 +0100 @@ -42,6 +42,7 @@ #include "send.h" #include "translation-table.h" #include "tvlv.h" +#include "fbx/fbx.h" /** * batadv_v_ogm_orig_get() - retrieve and possibly create an originator node @@ -123,8 +124,10 @@ { struct batadv_priv *bat_priv = netdev_priv(hard_iface->soft_iface); - if (hard_iface->if_status != BATADV_IF_ACTIVE) + if (hard_iface->if_status != BATADV_IF_ACTIVE) { + kfree_skb(skb); return; + } batadv_inc_counter(bat_priv, BATADV_CNT_MGMT_TX); batadv_add_counter(bat_priv, BATADV_CNT_MGMT_TX_BYTES, @@ -473,12 +476,14 @@ static u32 batadv_v_forward_penalty(struct batadv_priv *bat_priv, struct batadv_hard_iface *if_incoming, struct batadv_hard_iface *if_outgoing, - u32 throughput) + u32 throughput, bool *half_duplex) { int if_hop_penalty = atomic_read(&if_incoming->hop_penalty); int hop_penalty = atomic_read(&bat_priv->hop_penalty); int hop_penalty_max = BATADV_TQ_MAX_VALUE; + *half_duplex = false; + /* Apply per hardif hop penalty */ throughput = throughput * (hop_penalty_max - if_hop_penalty) / hop_penalty_max; @@ -493,8 +498,10 @@ */ if (throughput > 10 && if_incoming == if_outgoing && - !(if_incoming->bat_v.flags & BATADV_FULL_DUPLEX)) + !(if_incoming->bat_v.flags & BATADV_FULL_DUPLEX)) { + *half_duplex = true; return throughput / 2; + } /* hop penalty of 255 equals 100% */ return throughput * (hop_penalty_max - hop_penalty) / hop_penalty_max; @@ -572,6 +579,9 @@ /* apply forward penalty */ ogm_forward = (struct batadv_ogm2_packet *)skb_buff; + ogm_forward->flags &= ~BATADV_V_HALF_DUPLEX; + if (neigh_ifinfo->bat_v.half_duplex) + ogm_forward->flags |= BATADV_V_HALF_DUPLEX; ogm_forward->throughput = htonl(neigh_ifinfo->bat_v.throughput); ogm_forward->ttl--; @@ -614,6 +624,7 @@ bool protection_started = false; int ret = -EINVAL; u32 path_throughput; + bool half_duplex; s32 seq_diff; orig_ifinfo = batadv_orig_ifinfo_new(orig_node, if_outgoing); @@ -655,10 +666,12 @@ path_throughput = batadv_v_forward_penalty(bat_priv, if_incoming, if_outgoing, - ntohl(ogm2->throughput)); + ntohl(ogm2->throughput), + &half_duplex); neigh_ifinfo->bat_v.throughput = path_throughput; neigh_ifinfo->bat_v.last_seqno = ntohl(ogm2->seqno); neigh_ifinfo->last_ttl = ogm2->ttl; + neigh_ifinfo->bat_v.half_duplex = half_duplex; if (seq_diff > 0 || protection_started) ret = 1; @@ -842,6 +855,28 @@ } /** + * batadv_v_get_throughput() - Compute path throughput from ogm + * @ogm: OGM2 packet received + * @neigh: Neighbour OGM packet has been received from + * @return: Estimated path throughput + */ +static u32 batadv_v_get_throughput(struct batadv_ogm2_packet *ogm, + struct batadv_hardif_neigh_node *neigh) +{ + u32 oth, lth; + + oth = ntohl(ogm->throughput); + lth = ewma_throughput_read(&neigh->bat_v.throughput); + + if (!(ogm->flags & BATADV_V_HALF_DUPLEX)) + return min_t(u32, lth, oth); + + /* OGM throughput was divided by two for retrocompatibility sake */ + oth *= 2; + return oth * lth / (oth + lth); +} + +/** * batadv_v_ogm_process() - process an incoming batman v OGM * @skb: the skb containing the OGM * @ogm_offset: offset to the OGM which should be processed (for aggregates) @@ -857,7 +892,7 @@ struct batadv_neigh_node *neigh_node = NULL; struct batadv_hard_iface *hard_iface; struct batadv_ogm2_packet *ogm_packet; - u32 ogm_throughput, link_throughput, path_throughput; + u32 ogm_throughput; int ret; ethhdr = eth_hdr(skb); @@ -911,9 +946,8 @@ * - For OGMs traversing more than hop the path throughput metric is * the smaller of the path throughput and the link throughput. */ - link_throughput = ewma_throughput_read(&hardif_neigh->bat_v.throughput); - path_throughput = min_t(u32, link_throughput, ogm_throughput); - ogm_packet->throughput = htonl(path_throughput); + ogm_packet->throughput = htonl(batadv_v_get_throughput(ogm_packet, + hardif_neigh)); batadv_v_ogm_process_per_outif(bat_priv, ethhdr, ogm_packet, orig_node, neigh_node, if_incoming, @@ -967,6 +1001,7 @@ } rcu_read_unlock(); out: + batadv_fbx_ogm_process(bat_priv, orig_node, neigh_node, ogm_packet); batadv_orig_node_put(orig_node); batadv_neigh_node_put(neigh_node); batadv_hardif_neigh_put(hardif_neigh); @@ -985,7 +1020,7 @@ { struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface); struct batadv_ogm2_packet *ogm_packet; - struct ethhdr *ethhdr = eth_hdr(skb); + struct ethhdr *ethhdr; int ogm_offset; u8 *packet_pos; int ret = NET_RX_DROP; @@ -999,6 +1034,7 @@ if (!batadv_check_management_packet(skb, if_incoming, BATADV_OGM2_HLEN)) goto free_skb; + ethhdr = eth_hdr(skb); if (batadv_is_my_mac(bat_priv, ethhdr->h_source)) goto free_skb; diff -ruw linux-6.4/net/batman-adv/fragmentation.c linux-6.4-fbx/net/batman-adv/fragmentation.c --- linux-6.4/net/batman-adv/fragmentation.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/fragmentation.c 2023-12-12 17:24:34.163627207 +0100 @@ -28,6 +28,8 @@ #include "routing.h" #include "send.h" +#include "fbx/mtu.h" + /** * batadv_frag_clear_chain() - delete entries in the fragment buffer chain * @head: head of chain with entries. @@ -445,7 +447,7 @@ struct batadv_hard_iface *primary_if = NULL; struct batadv_frag_packet frag_header; struct sk_buff *skb_fragment; - unsigned int mtu = net_dev->mtu; + unsigned int mtu = batadv_mtu_get_for_neigh(neigh_node->hardif_neigh); unsigned int header_size = sizeof(frag_header); unsigned int max_fragment_size, num_fragments; int ret; diff -ruw linux-6.4/net/batman-adv/hard-interface.c linux-6.4-fbx/net/batman-adv/hard-interface.c --- linux-6.4/net/batman-adv/hard-interface.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/hard-interface.c 2023-12-12 17:24:34.167627317 +0100 @@ -36,6 +36,7 @@ #include "gateway_client.h" #include "log.h" #include "originator.h" +#include "fbx/fbx.h" #include "send.h" #include "soft-interface.h" #include "translation-table.h" @@ -469,6 +470,7 @@ batadv_dat_init_own_addr(bat_priv, primary_if); batadv_bla_update_orig_address(bat_priv, primary_if, oldif); + batadv_fbx_primary_update(bat_priv, primary_if); out: batadv_hardif_put(primary_if); } @@ -970,8 +972,10 @@ batadv_hardif_remove_interface(hard_iface); break; case NETDEV_CHANGEMTU: - if (hard_iface->soft_iface) + if (hard_iface->soft_iface) { batadv_update_min_mtu(hard_iface->soft_iface); + batadv_fbx_hardif_update(hard_iface); + } break; case NETDEV_CHANGEADDR: if (hard_iface->if_status == BATADV_IF_NOT_IN_USE) diff -ruw linux-6.4/net/batman-adv/main.c linux-6.4-fbx/net/batman-adv/main.c --- linux-6.4/net/batman-adv/main.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/main.c 2023-12-12 17:24:34.167627317 +0100 @@ -59,6 +59,7 @@ #include "soft-interface.h" #include "tp_meter.h" #include "translation-table.h" +#include "fbx/fbx.h" /* List manipulations on hardif_list have to be rtnl_lock()'ed, * list traversals just rcu-locked @@ -115,6 +116,7 @@ register_netdevice_notifier(&batadv_hard_if_notifier); rtnl_link_register(&batadv_link_ops); batadv_netlink_register(); + batadv_fbx_init(); pr_info("B.A.T.M.A.N. advanced %s (compatibility version %i) loaded\n", BATADV_SOURCE_VERSION, BATADV_COMPAT_VERSION); @@ -129,6 +131,7 @@ static void __exit batadv_exit(void) { + batadv_fbx_exit(); batadv_netlink_unregister(); rtnl_link_unregister(&batadv_link_ops); unregister_netdevice_notifier(&batadv_hard_if_notifier); @@ -228,6 +231,7 @@ batadv_gw_init(bat_priv); batadv_mcast_init(bat_priv); + batadv_fbx_new_priv(bat_priv); atomic_set(&bat_priv->gw.reselect, 0); atomic_set(&bat_priv->mesh_state, BATADV_MESH_ACTIVE); @@ -270,6 +274,7 @@ batadv_dat_free(bat_priv); batadv_bla_free(bat_priv); + batadv_fbx_free_priv(bat_priv); batadv_mcast_free(bat_priv); /* Free the TT and the originator tables only after having terminated @@ -481,6 +486,7 @@ memset(skb->cb, 0, sizeof(struct batadv_skb_cb)); idx = batadv_ogm_packet->packet_type; + (*batadv_rx_handler[idx])(skb, hard_iface); batadv_hardif_put(hard_iface); @@ -526,6 +532,7 @@ BUILD_BUG_ON(sizeof(struct batadv_tvlv_tt_vlan_data) != 8); BUILD_BUG_ON(sizeof(struct batadv_tvlv_tt_change) != 12); BUILD_BUG_ON(sizeof(struct batadv_tvlv_roam_adv) != 8); + BUILD_BUG_ON(sizeof(struct batadv_fbx_packet) != 8); i = sizeof_field(struct sk_buff, cb); BUILD_BUG_ON(sizeof(struct batadv_skb_cb) > i); diff -ruw linux-6.4/net/batman-adv/netlink.c linux-6.4-fbx/net/batman-adv/netlink.c --- linux-6.4/net/batman-adv/netlink.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/netlink.c 2023-12-21 17:30:06.449516617 +0100 @@ -51,6 +51,7 @@ #include "soft-interface.h" #include "tp_meter.h" #include "translation-table.h" +#include "fbx/fbx.h" struct genl_family batadv_netlink_family; @@ -58,6 +59,7 @@ enum batadv_netlink_multicast_groups { BATADV_NL_MCGRP_CONFIG, BATADV_NL_MCGRP_TPMETER, + BATADV_NL_MCGRP_ROUTE, }; /** @@ -89,6 +91,7 @@ static const struct genl_multicast_group batadv_netlink_mcgrps[] = { [BATADV_NL_MCGRP_CONFIG] = { .name = BATADV_NL_MCAST_GROUP_CONFIG }, [BATADV_NL_MCGRP_TPMETER] = { .name = BATADV_NL_MCAST_GROUP_TPMETER }, + [BATADV_NL_MCGRP_ROUTE] = { .name = BATADV_NL_MCAST_GROUP_ROUTE }, }; static const struct nla_policy batadv_netlink_policy[NUM_BATADV_ATTR] = { @@ -151,6 +154,7 @@ [BATADV_ATTR_ORIG_INTERVAL] = { .type = NLA_U32 }, [BATADV_ATTR_ELP_INTERVAL] = { .type = NLA_U32 }, [BATADV_ATTR_THROUGHPUT_OVERRIDE] = { .type = NLA_U32 }, + [BATADV_ATTR_FBX] = { .type = NLA_NESTED }, }; /** @@ -361,6 +365,7 @@ batadv_hardif_put(primary_if); + batadv_fbx_nl(bat_priv, cmd, NULL, msg, NULL); genlmsg_end(msg, hdr); return 0; @@ -613,6 +618,7 @@ atomic_set(&bat_priv->orig_interval, orig_interval); } + batadv_fbx_nl(bat_priv, BATADV_CMD_SET_MESH, info, NULL, NULL); batadv_netlink_notify_mesh(bat_priv); return 0; @@ -1151,6 +1157,100 @@ return 0; } +/** + * batadv_netlink_mesh_fill: Fill message with route attributes + * @msg: Nelink message to dump route info into + * @bat_priv: the bat priv with all the soft interface information + * @cmd: type of netlink message + * @orig: Current route destination originator + * @neigh: Current best neighbour for this originator + * @best: Globally best route + * @portid: Port making netlink request + * @seq: sequence number for message + * @flags: Additionnal netlink flag message + */ +static int batadv_netlink_route_fill(struct sk_buff *msg, + struct batadv_priv *bat_priv, + enum batadv_nl_commands cmd, + struct batadv_orig_node *orig_node, + struct batadv_neigh_node *neigh_node, + bool best, + u32 portid, u32 seq, int flags) +{ + struct net_device *soft_iface = bat_priv->soft_iface; + void *hdr; + + hdr = genlmsg_put(msg, portid, seq, &batadv_netlink_family, flags, cmd); + if (!hdr) + return -ENOBUFS; + + if (nla_put_u32(msg, BATADV_ATTR_MESH_IFINDEX, soft_iface->ifindex)) + goto nla_put_failure; + + if (nla_put(msg, BATADV_ATTR_MESH_ADDRESS, ETH_ALEN, + soft_iface->dev_addr)) + goto nla_put_failure; + + if (nla_put(msg, BATADV_ATTR_ORIG_ADDRESS, ETH_ALEN, + orig_node->orig)) + goto nla_put_failure; + + if (best && nla_put_flag(msg, BATADV_ATTR_FLAG_BEST)) + goto nla_put_failure; + + if (neigh_node && nla_put(msg, BATADV_ATTR_NEIGH_ADDRESS, ETH_ALEN, + neigh_node->addr)) + goto nla_put_failure; + + if (neigh_node && + nla_put_u32(msg, BATADV_ATTR_HARD_IFINDEX, + neigh_node->if_incoming->net_dev->ifindex)) + goto nla_put_failure; + + genlmsg_end(msg, hdr); + return 0; + +nla_put_failure: + genlmsg_cancel(msg, hdr); + return -EMSGSIZE; +} + +/** + * batadv_netlink_notify_route() - send route events to listener + * @bat_priv: the bat priv with all the soft interface information + * @ev: Route event type (add, del or change) + * @orig: The route destination node + * @neigh: Best neighbour for this route + * @best: This is a globaly best route + * + * Return: 0 on success, < 0 on error + */ +int batadv_netlink_notify_route(struct batadv_priv *bat_priv, + enum batadv_nl_commands ev, + struct batadv_orig_node *orig_node, + struct batadv_neigh_node *neigh_node, + bool best) +{ + struct sk_buff *msg; + int ret; + + msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_ATOMIC); + if (!msg) + return -ENOMEM; + + ret = batadv_netlink_route_fill(msg, bat_priv, ev, orig_node, + neigh_node, best, 0, 0, 0); + if (ret < 0) { + nlmsg_free(msg); + return ret; + } + + genlmsg_multicast_netns(&batadv_netlink_family, + dev_net(bat_priv->soft_iface), msg, 0, + BATADV_NL_MCGRP_ROUTE, GFP_KERNEL); + return 0; +} + /** * batadv_get_softif_from_info() - Retrieve soft interface from genl attributes * @net: the applicable net namespace diff -ruw linux-6.4/net/batman-adv/netlink.h linux-6.4-fbx/net/batman-adv/netlink.h --- linux-6.4/net/batman-adv/netlink.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/netlink.h 2023-12-21 17:30:06.449516617 +0100 @@ -27,6 +27,12 @@ int batadv_netlink_notify_vlan(struct batadv_priv *bat_priv, struct batadv_softif_vlan *vlan); +int batadv_netlink_notify_route(struct batadv_priv *bat_priv, + enum batadv_nl_commands ev, + struct batadv_orig_node *orig_node, + struct batadv_neigh_node *neigh_node, + bool best); + extern struct genl_family batadv_netlink_family; #endif /* _NET_BATMAN_ADV_NETLINK_H_ */ diff -ruw linux-6.4/net/batman-adv/originator.c linux-6.4-fbx/net/batman-adv/originator.c --- linux-6.4/net/batman-adv/originator.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/originator.c 2023-12-21 17:30:06.453516726 +0100 @@ -42,6 +42,7 @@ #include "routing.h" #include "soft-interface.h" #include "translation-table.h" +#include "fbx/fbx.h" /* hash class keys */ static struct lock_class_key batadv_orig_hash_lock_class_key; @@ -249,6 +250,7 @@ hlist_del_init_rcu(&hardif_neigh->list); spin_unlock_bh(&hardif_neigh->if_incoming->neigh_list_lock); + batadv_fbx_neigh_release(hardif_neigh); batadv_hardif_put(hardif_neigh->if_incoming); kfree_rcu(hardif_neigh, rcu); } @@ -381,6 +383,8 @@ INIT_HLIST_NODE(&orig_ifinfo->list); kref_init(&orig_ifinfo->refcount); + batadv_fbx_orig_ifinfo_init(orig_ifinfo); + kref_get(&orig_ifinfo->refcount); hlist_add_head_rcu(&orig_ifinfo->list, &orig_node->ifinfo_list); @@ -517,6 +521,7 @@ { struct batadv_priv *bat_priv = netdev_priv(hard_iface->soft_iface); struct batadv_hardif_neigh_node *hardif_neigh; + int ret; spin_lock_bh(&hard_iface->neigh_list_lock); @@ -537,6 +542,13 @@ hardif_neigh->last_seen = jiffies; kref_init(&hardif_neigh->refcount); + ret = batadv_fbx_neigh_init(hardif_neigh); + if (ret) { + batadv_hardif_put(hard_iface); + kfree(hardif_neigh); + hardif_neigh = NULL; + goto out; + } if (bat_priv->algo_ops->neigh.hardif_init) bat_priv->algo_ops->neigh.hardif_init(hardif_neigh); @@ -776,6 +788,8 @@ orig_ifinfo = container_of(ref, struct batadv_orig_ifinfo, refcount); + batadv_fbx_orig_ifinfo_release(orig_ifinfo); + if (orig_ifinfo->if_outgoing != BATADV_IF_DEFAULT) batadv_hardif_put(orig_ifinfo->if_outgoing); @@ -796,6 +810,8 @@ orig_node = container_of(rcu, struct batadv_orig_node, rcu); + batadv_fbx_orig_release(orig_node); + batadv_mcast_purge_orig(orig_node); batadv_frag_purge_orig(orig_node, NULL); @@ -906,7 +922,7 @@ struct batadv_orig_node *orig_node; struct batadv_orig_node_vlan *vlan; unsigned long reset_time; - int i; + int ret, i; batadv_dbg(BATADV_DBG_BATMAN, bat_priv, "Creating new originator: %pM\n", addr); @@ -964,6 +980,10 @@ orig_node->fragments[i].size = 0; } + ret = batadv_fbx_orig_init(orig_node); + if (ret) + goto free_orig_node; + return orig_node; free_orig_node: kfree(orig_node); diff -ruw linux-6.4/net/batman-adv/routing.c linux-6.4-fbx/net/batman-adv/routing.c --- linux-6.4/net/batman-adv/routing.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/routing.c 2023-12-21 17:30:06.453516726 +0100 @@ -37,6 +37,8 @@ #include "tp_meter.h" #include "translation-table.h" #include "tvlv.h" +#include "netlink.h" +#include "fbx/fbx.h" static int batadv_route_unicast_packet(struct sk_buff *skb, struct batadv_hard_iface *recv_if); @@ -57,6 +59,7 @@ { struct batadv_orig_ifinfo *orig_ifinfo; struct batadv_neigh_node *curr_router; + enum batadv_nl_commands cmd; orig_ifinfo = batadv_orig_ifinfo_get(orig_node, recv_if); if (!orig_ifinfo) @@ -82,6 +85,7 @@ /* route deleted */ if (curr_router && !neigh_node) { + cmd = BATADV_CMD_DEL_ROUTE; batadv_dbg(BATADV_DBG_ROUTES, bat_priv, "Deleting route towards: %pM\n", orig_node->orig); batadv_tt_global_del_orig(bat_priv, orig_node, -1, @@ -89,11 +93,13 @@ /* route added */ } else if (!curr_router && neigh_node) { + cmd = BATADV_CMD_ADD_ROUTE; batadv_dbg(BATADV_DBG_ROUTES, bat_priv, "Adding route towards: %pM (via %pM)\n", orig_node->orig, neigh_node->addr); /* route changed */ } else if (neigh_node && curr_router) { + cmd = BATADV_CMD_CHANGE_ROUTE; batadv_dbg(BATADV_DBG_ROUTES, bat_priv, "Changing route towards: %pM (now via %pM - was via %pM)\n", orig_node->orig, neigh_node->addr, @@ -102,6 +108,10 @@ /* decrease refcount of previous best neighbor */ batadv_neigh_node_put(curr_router); + + if (recv_if == BATADV_IF_DEFAULT) + batadv_netlink_notify_route(bat_priv, cmd, orig_node, + neigh_node, true); } /** @@ -946,7 +956,7 @@ int check, hdr_size = sizeof(*unicast_packet); enum batadv_subtype subtype; int ret = NET_RX_DROP; - bool is4addr, is_gw; + bool is4addr, is_gw, shortcut; unicast_packet = (struct batadv_unicast_packet *)skb->data; is4addr = unicast_packet->packet_type == BATADV_UNICAST_4ADDR; @@ -970,8 +980,10 @@ unicast_packet = (struct batadv_unicast_packet *)skb->data; + shortcut = batadv_fbx_shortcut(bat_priv, unicast_packet->dest); + /* packet for me */ - if (batadv_is_my_mac(bat_priv, unicast_packet->dest)) { + if (shortcut || batadv_is_my_mac(bat_priv, unicast_packet->dest)) { /* If this is a unicast packet from another backgone gw, * drop it. */ diff -ruw linux-6.4/net/batman-adv/send.c linux-6.4-fbx/net/batman-adv/send.c --- linux-6.4/net/batman-adv/send.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/send.c 2023-12-12 17:24:34.167627317 +0100 @@ -34,6 +34,8 @@ #include "gateway_client.h" #include "hard-interface.h" #include "log.h" +#include "fbx/fbx.h" +#include "fbx/mtu.h" #include "network-coding.h" #include "originator.h" #include "routing.h" @@ -192,7 +194,7 @@ * it if needed. */ if (atomic_read(&bat_priv->fragmentation) && - skb->len > neigh_node->if_incoming->net_dev->mtu) { + skb->len > batadv_mtu_get_for_neigh(neigh_node->hardif_neigh)) { /* Fragment and send packet. */ ret = batadv_frag_send_packet(skb, orig_node, neigh_node); /* skb was consumed */ @@ -408,7 +410,7 @@ struct ethhdr *ethhdr = (struct ethhdr *)skb->data; struct batadv_orig_node *orig_node; u8 *src, *dst; - int ret; + int ret = NET_XMIT_DROP; src = ethhdr->h_source; dst = ethhdr->h_dest; @@ -420,6 +422,10 @@ } orig_node = batadv_transtable_search(bat_priv, src, dst, vid); + /* unknown unicast (no tt entry for dest), handle same as broadcast */ + if (!orig_node) + return batadv_send_bcast_packet(bat_priv, skb, 0, true); + ret = batadv_send_skb_unicast(bat_priv, skb, packet_type, packet_subtype, orig_node, vid); @@ -990,13 +996,48 @@ * * Consumes the provided skb. */ -void batadv_send_bcast_packet(struct batadv_priv *bat_priv, +int batadv_send_bcast_packet(struct batadv_priv *bat_priv, struct sk_buff *skb, unsigned long delay, bool own_packet) { + struct batadv_bcast_packet *bcast_packet; + struct batadv_hard_iface *primary_if = NULL; + u32 seqno; + + primary_if = batadv_primary_if_get_selected(bat_priv); + if (!primary_if) + goto drop; + + if (batadv_skb_head_push(skb, sizeof(*bcast_packet)) < 0) + goto drop; + + bcast_packet = (struct batadv_bcast_packet *)skb->data; + bcast_packet->version = BATADV_COMPAT_VERSION; + bcast_packet->ttl = BATADV_TTL - 1; + + /* batman packet type: broadcast */ + bcast_packet->packet_type = BATADV_BCAST; + bcast_packet->reserved = 0; + + /* hw address of first interface is the orig mac because only + * this mac is known throughout the mesh + */ + ether_addr_copy(bcast_packet->orig, + primary_if->net_dev->dev_addr); + + /* set broadcast sequence number */ + seqno = atomic_inc_return(&bat_priv->bcast_seqno); + bcast_packet->seqno = htonl(seqno); + __batadv_forw_bcast_packet(bat_priv, skb, delay, own_packet); + consume_skb(skb); + batadv_hardif_put(primary_if); + return NET_XMIT_SUCCESS; +drop: + kfree_skb(skb); + return NET_XMIT_DROP; } /** diff -ruw linux-6.4/net/batman-adv/send.h linux-6.4-fbx/net/batman-adv/send.h --- linux-6.4/net/batman-adv/send.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/send.h 2023-12-12 17:24:34.167627317 +0100 @@ -43,7 +43,7 @@ struct sk_buff *skb, unsigned long delay, bool own_packet); -void batadv_send_bcast_packet(struct batadv_priv *bat_priv, +int batadv_send_bcast_packet(struct batadv_priv *bat_priv, struct sk_buff *skb, unsigned long delay, bool own_packet); diff -ruw linux-6.4/net/batman-adv/soft-interface.c linux-6.4-fbx/net/batman-adv/soft-interface.c --- linux-6.4/net/batman-adv/soft-interface.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/soft-interface.c 2024-03-22 17:24:19.542846394 +0100 @@ -50,6 +50,7 @@ #include "network-coding.h" #include "send.h" #include "translation-table.h" +#include "fbx/fbx.h" /** * batadv_skb_head_push() - Increase header size and move (push) head pointer @@ -174,13 +175,27 @@ { } +#ifndef ETH_P_BCOM_DSA +#define ETH_P_BCOM_DSA 0x8874 +#endif + +#ifndef ETH_P_REALTEK_RRCP +#define ETH_P_REALTEK_RRCP 0x8899 +#endif + +#ifndef RRCP_PROTO_RLDP +#define RRCP_PROTO_RLDP 0x03 +#endif + +#ifndef RRCP_PROTO_RLDP2 +#define RRCP_PROTO_RLDP2 0x23 +#endif + static netdev_tx_t batadv_interface_tx(struct sk_buff *skb, struct net_device *soft_iface) { struct ethhdr *ethhdr; struct batadv_priv *bat_priv = netdev_priv(soft_iface); - struct batadv_hard_iface *primary_if = NULL; - struct batadv_bcast_packet *bcast_packet; static const u8 stp_addr[ETH_ALEN] = {0x01, 0x80, 0xC2, 0x00, 0x00, 0x00}; static const u8 ectp_addr[ETH_ALEN] = {0xCF, 0x00, 0x00, 0x00, @@ -193,12 +208,12 @@ unsigned long brd_delay = 0; bool do_bcast = false, client_added; unsigned short vid; - u32 seqno; int gw_mode; enum batadv_forw_mode forw_mode = BATADV_FORW_BCAST; int mcast_is_routable = 0; int network_offset = ETH_HLEN; __be16 proto; + u8 rrcp_proto = 0; if (atomic_read(&bat_priv->mesh_state) != BATADV_MESH_ACTIVE) goto dropped; @@ -237,6 +252,9 @@ if (batadv_bla_tx(bat_priv, skb, vid)) goto dropped; + if (!batadv_fbx_check_skb_tx(bat_priv, skb, vid)) + goto dropped; + /* skb->data might have been reallocated by batadv_bla_tx() */ ethhdr = eth_hdr(skb); @@ -253,18 +271,42 @@ /* Snoop address candidates from DHCPACKs for early DAT filling */ batadv_dat_snoop_outgoing_dhcp_ack(bat_priv, skb, proto, vid); - /* don't accept stp packets. STP does not help in meshes. - * better use the bridge loop avoidance ... + /* don't accept stp packets with BLA. STP does not help in meshes. + * better use the bridge loop avoidance .... But as some devices uses + * that, such as SONOS ones, if BLA is not enabled let those packets + * going and print debug once. * * The same goes for ECTP sent at least by some Cisco Switches, * it might confuse the mesh when used with bridge loop avoidance. + * Those seems safe to drop with or without BLA. */ - if (batadv_compare_eth(ethhdr->h_dest, stp_addr)) +#ifdef CONFIG_BATMAN_ADV_BLA + if (atomic_read(&bat_priv->bridge_loop_avoidance) && + batadv_compare_eth(ethhdr->h_dest, stp_addr)) goto dropped; +#else + WARN_ONCE(batadv_compare_eth(ethhdr->h_dest, stp_addr), + "Some STP packets stroll around this network"); +#endif if (batadv_compare_eth(ethhdr->h_dest, ectp_addr)) goto dropped; + /* Also don't accept Broadcom and Realtek loop detection packets as + * they do not play well on mesh. + */ + if (unlikely(is_multicast_ether_addr(ethhdr->h_dest))) { + if (unlikely(proto == htons(ETH_P_BCOM_DSA))) + goto dropped; + if (unlikely(proto == htons(ETH_P_REALTEK_RRCP))) { + skb_copy_bits(skb, sizeof(*ethhdr), &rrcp_proto, 1); + if (rrcp_proto == RRCP_PROTO_RLDP) + goto dropped; + if (rrcp_proto == RRCP_PROTO_RLDP2) + goto dropped; + } + } + gw_mode = atomic_read(&bat_priv->gw.mode); if (is_multicast_ether_addr(ethhdr->h_dest)) { /* if gw mode is off, broadcast every packet */ @@ -318,10 +360,6 @@ /* ethernet packet should be broadcasted */ if (do_bcast) { - primary_if = batadv_primary_if_get_selected(bat_priv); - if (!primary_if) - goto dropped; - /* in case of ARP request, we do not immediately broadcasti the * packet, instead we first wait for DAT to try to retrieve the * correct ARP entry @@ -329,28 +367,9 @@ if (batadv_dat_snoop_outgoing_arp_request(bat_priv, skb)) brd_delay = msecs_to_jiffies(ARP_REQ_DELAY); - if (batadv_skb_head_push(skb, sizeof(*bcast_packet)) < 0) - goto dropped; - - bcast_packet = (struct batadv_bcast_packet *)skb->data; - bcast_packet->version = BATADV_COMPAT_VERSION; - bcast_packet->ttl = BATADV_TTL - 1; - - /* batman packet type: broadcast */ - bcast_packet->packet_type = BATADV_BCAST; - bcast_packet->reserved = 0; - - /* hw address of first interface is the orig mac because only - * this mac is known throughout the mesh - */ - ether_addr_copy(bcast_packet->orig, - primary_if->net_dev->dev_addr); - - /* set broadcast sequence number */ - seqno = atomic_inc_return(&bat_priv->bcast_seqno); - bcast_packet->seqno = htonl(seqno); - - batadv_send_bcast_packet(bat_priv, skb, brd_delay, true); + ret = batadv_send_bcast_packet(bat_priv, skb, brd_delay, true); + if (ret != NET_XMIT_SUCCESS) + goto dropped_freed; /* unicast packet */ } else { /* DHCP packets going to a server will use the GW feature */ @@ -385,7 +404,6 @@ dropped_freed: batadv_inc_counter(bat_priv, BATADV_CNT_TX_DROPPED); end: - batadv_hardif_put(primary_if); return NETDEV_TX_OK; } @@ -431,6 +449,9 @@ if (unlikely(!pskb_may_pull(skb, ETH_HLEN))) goto dropped; + if (!batadv_fbx_check_skb_rx(bat_priv, packet_type, skb)) + goto dropped; + vid = batadv_get_vid(skb, 0); ethhdr = eth_hdr(skb); @@ -774,7 +795,8 @@ atomic_set(&bat_priv->batman_queue_left, BATADV_BATMAN_QUEUE_LEN); atomic_set(&bat_priv->mesh_state, BATADV_MESH_INACTIVE); - atomic_set(&bat_priv->bcast_seqno, 1); + get_random_bytes(&random_seqno, sizeof(random_seqno)); + atomic_set(&bat_priv->bcast_seqno, random_seqno); atomic_set(&bat_priv->tt.vn, 0); atomic_set(&bat_priv->tt.local_changes, 0); atomic_set(&bat_priv->tt.ogm_append_cnt, 0); diff -ruw linux-6.4/net/batman-adv/translation-table.c linux-6.4-fbx/net/batman-adv/translation-table.c --- linux-6.4/net/batman-adv/translation-table.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/translation-table.c 2023-12-12 17:24:34.167627317 +0100 @@ -50,6 +50,7 @@ #include "originator.h" #include "soft-interface.h" #include "tvlv.h" +#include "fbx/fbx.h" static struct kmem_cache *batadv_tl_cache __read_mostly; static struct kmem_cache *batadv_tg_cache __read_mostly; @@ -167,7 +168,7 @@ * Return: a pointer to the corresponding tt_local_entry struct if the client is * found, NULL otherwise. */ -static struct batadv_tt_local_entry * +struct batadv_tt_local_entry * batadv_tt_local_hash_find(struct batadv_priv *bat_priv, const u8 *addr, unsigned short vid) { @@ -244,8 +245,7 @@ * possibly release it * @tt_local_entry: tt_local_entry to be free'd */ -static void -batadv_tt_local_entry_put(struct batadv_tt_local_entry *tt_local_entry) +void batadv_tt_local_entry_put(struct batadv_tt_local_entry *tt_local_entry) { if (!tt_local_entry) return; @@ -456,7 +456,7 @@ * @tt_local_entry: the TT entry involved in the event * @event_flags: flags to store in the event structure */ -static void batadv_tt_local_event(struct batadv_priv *bat_priv, +void batadv_tt_local_event(struct batadv_priv *bat_priv, struct batadv_tt_local_entry *tt_local_entry, u8 event_flags) { @@ -645,8 +645,9 @@ struct hlist_head *head; struct batadv_tt_orig_list_entry *orig_entry; int hash_added, table_size, packet_size_max; - bool ret = false; + bool roam = true, ret = false; bool roamed_back = false; + u16 save_flags; u8 remote_flags; u32 match_mark; @@ -708,6 +709,8 @@ /* increase the refcounter of the related vlan */ vlan = batadv_softif_vlan_get(bat_priv, vid); + if (!vlan) + vlan = batadv_softif_vlan_get(bat_priv, 0); if (!vlan) { net_ratelimited_function(batadv_info, soft_iface, "adding TT local entry %pM to non-existent VLAN %d\n", @@ -758,10 +761,17 @@ batadv_tt_local_event(bat_priv, tt_local, BATADV_NO_FLAGS); check_roaming: + + save_flags = tt_local->common.flags; + roam = batadv_fbx_tt_local_add(bat_priv, tt_local, tt_global, ifindex); + if (save_flags != tt_local->common.flags) + batadv_tt_local_event(bat_priv, tt_local, BATADV_NO_FLAGS); + /* Check whether it is a roaming, but don't do anything if the roaming * process has already been handled */ - if (tt_global && !(tt_global->common.flags & BATADV_TT_CLIENT_ROAM)) { + if (roam && tt_global && + !(tt_global->common.flags & BATADV_TT_CLIENT_ROAM)) { /* These node are probably going to update their tt table */ head = &tt_global->orig_list; rcu_read_lock(); @@ -774,7 +784,6 @@ if (roamed_back) { batadv_tt_global_free(bat_priv, tt_global, "Roaming canceled"); - tt_global = NULL; } else { /* The global entry has to be marked as ROAMING and * has to be kept for consistency purpose @@ -1081,6 +1090,8 @@ vlan = batadv_softif_vlan_get(bat_priv, common->vid); if (!vlan) + vlan = batadv_softif_vlan_get(bat_priv, 0); + if (!vlan) return 0; crc = vlan->tt.crc; @@ -1252,6 +1263,7 @@ struct batadv_tt_local_entry *tt_local_entry; u16 flags, curr_flags = BATADV_NO_FLAGS; struct hlist_node *tt_removed_node; + bool remove; tt_local_entry = batadv_tt_local_hash_find(bat_priv, addr, vid); if (!tt_local_entry) @@ -1259,6 +1271,16 @@ curr_flags = tt_local_entry->common.flags; + remove = batadv_fbx_tt_local_del(bat_priv, tt_local_entry); + if (!remove) { + /* Do not delete local entry if other SLAP node has still + * references on it, just mark it shallow + */ + batadv_tt_local_event(bat_priv, tt_local_entry, + BATADV_NO_FLAGS); + goto out; + } + flags = BATADV_TT_CLIENT_DEL; /* if this global entry addition is due to a roaming, the node has to * mark the local entry as "roamed" in order to correctly reroute @@ -1329,6 +1351,13 @@ if (!batadv_has_timed_out(tt_local_entry->last_seen, timeout)) continue; + if (!batadv_fbx_tt_local_del(bat_priv, tt_local_entry)) { + /* Send only flag changes */ + batadv_tt_local_event(bat_priv, tt_local_entry, + BATADV_NO_FLAGS); + continue; + } + batadv_tt_local_set_pending(bat_priv, tt_local_entry, BATADV_TT_CLIENT_DEL, "timed out"); } @@ -1595,7 +1624,7 @@ { struct batadv_tt_global_entry *tt_global_entry; struct batadv_tt_local_entry *tt_local_entry; - bool ret = false; + bool remove = true, ret = false; int hash_added; struct batadv_tt_common_entry *common; u16 local_flags; @@ -1711,6 +1740,8 @@ batadv_tt_global_orig_entry_add(tt_global_entry, orig_node, ttvn, flags & BATADV_TT_SYNC_MASK); + remove = batadv_fbx_tt_global_add(bat_priv, tt_global_entry, orig_node); + batadv_dbg(BATADV_DBG_TT, bat_priv, "Creating new global tt entry: %pM (vid: %d, via %pM)\n", common->addr, batadv_print_vid(common->vid), @@ -1721,7 +1752,7 @@ /* Do not remove multicast addresses from the local hash on * global additions */ - if (is_multicast_ether_addr(tt_addr)) + if (!remove || is_multicast_ether_addr(tt_addr)) goto out; /* remove address from local hash if present */ @@ -1730,13 +1761,13 @@ flags & BATADV_TT_CLIENT_ROAM); tt_global_entry->common.flags |= local_flags & BATADV_TT_CLIENT_WIFI; - if (!(flags & BATADV_TT_CLIENT_ROAM)) +out: + if (tt_global_entry && !(flags & BATADV_TT_CLIENT_ROAM)) /* this is a normal global add. Therefore the client is not in a * roaming state anymore. */ tt_global_entry->common.flags &= ~BATADV_TT_CLIENT_ROAM; -out: batadv_tt_global_entry_put(tt_global_entry); batadv_tt_local_entry_put(tt_local_entry); return ret; @@ -2166,7 +2197,7 @@ local_entry = batadv_tt_local_hash_find(bat_priv, tt_global_entry->common.addr, vid); - if (local_entry) { + if (local_entry && local_entry->common.flags & BATADV_TT_CLIENT_SEEN) { /* local entry exists, case 2: client roamed to us. */ batadv_tt_global_del_orig_list(tt_global_entry); batadv_tt_global_free(bat_priv, tt_global_entry, message); @@ -2177,6 +2208,8 @@ } out: + /* TODO check roaming */ + batadv_fbx_tt_global_del(bat_priv, tt_global_entry, orig_node); batadv_tt_global_entry_put(tt_global_entry); batadv_tt_local_entry_put(local_entry); } diff -ruw linux-6.4/net/batman-adv/translation-table.h linux-6.4-fbx/net/batman-adv/translation-table.h --- linux-6.4/net/batman-adv/translation-table.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/translation-table.h 2023-12-12 17:24:34.167627317 +0100 @@ -21,6 +21,10 @@ u16 batadv_tt_local_remove(struct batadv_priv *bat_priv, const u8 *addr, unsigned short vid, const char *message, bool roaming); +struct batadv_tt_local_entry * +batadv_tt_local_hash_find(struct batadv_priv *bat_priv, const u8 *addr, + unsigned short vid); +void batadv_tt_local_entry_put(struct batadv_tt_local_entry *tt_local_entry); int batadv_tt_local_dump(struct sk_buff *msg, struct netlink_callback *cb); int batadv_tt_global_dump(struct sk_buff *msg, struct netlink_callback *cb); void batadv_tt_global_del_orig(struct batadv_priv *bat_priv, diff -ruw linux-6.4/net/batman-adv/types.h linux-6.4-fbx/net/batman-adv/types.h --- linux-6.4/net/batman-adv/types.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/batman-adv/types.h 2023-12-21 17:30:06.453516726 +0100 @@ -275,6 +275,19 @@ /** @rcu: struct used for freeing in an RCU-safe manner */ struct rcu_head rcu; +#ifdef CONFIG_BATMAN_ADV_FBX_PERIF_ROUTER + /** + * @fbx_ifrouter: best router that should be used to reach this + * originator from this interface. Due to internal BATMAN_V router + * management algorithm, orig_ifinfo->router is the best router to + * reach originator from any interface not only this one, + * orig_ifinfo->fbx_ifrouter is used to get best router for this + * interface. + */ + struct batadv_neigh_node __rcu *fbx_ifrouter; + /** @ fbx_ifrouter_lock: lock to protect fbx_ifrouter rcu update */ + spinlock_t fbx_ifrouter_lock; +#endif }; /** @@ -527,6 +540,10 @@ /** @bat_iv: B.A.T.M.A.N. IV private structure */ struct batadv_orig_bat_iv bat_iv; +#ifdef CONFIG_BATMAN_ADV_FBX_SLAP + struct batadv_slap_segid *slap_segid; + spinlock_t slap_lock; +#endif }; /** @@ -601,6 +618,74 @@ struct work_struct metric_work; }; +#ifdef CONFIG_BATMAN_ADV_FBX_MTU +/** + * MTU discovery bookkeeping data + */ +struct batadv_mtu { + /** @neigh: Neighbour hardif */ + struct batadv_hardif_neigh_node __rcu *neigh; + /** periodic work */ + struct delayed_work periodic_work; + /** timeout work */ + struct delayed_work recv_work; + /** release work */ + struct delayed_work release_work; + /** the final MTU to use for this link */ + atomic_t mtu; + /** current delay, not critical, use (READ/WRITE)_ONCE */ + unsigned long delay; +}; +#endif + +#ifdef CONFIG_BATMAN_ADV_FBX_SLAP +/** + * batadv_slap_segid - SLAP segment address used to uniquely identify a SLAP + * segment + */ +struct batadv_slap_segid { + /* @rcu: struct used for freeing in a RCU-safe manner */ + struct rcu_head rcu; + /* @addr: The SLAP master MAC address is used as unique segment ID */ + u8 addr[ETH_ALEN]; +}; + +/** + * batadv_slap_id - SLAP ID management structure, a SLAP ID is composed of the + * MAC address of the originator along with a priority + */ +struct batadv_slap_id { + /** @bat_priv: pointer to the mesh object */ + struct batadv_priv *bat_priv; + /* @dw: delayed work used to schedule SLAP ID expiration */ + struct delayed_work expire; + /** @refcount: Number of contexts using this slap id */ + struct kref refcount; + /* @rcu: struct used for freeing in a RCU-safe manner */ + struct rcu_head rcu; + /* @exp_time: Expiration time of this SLAP ID, in jiffies */ + unsigned long exp_time; + /* @prio: SLAP ID priority part */ + u32 prio; + /* @addr: SLAP ID addr part */ + u8 addr[ETH_ALEN]; +}; + +struct batadv_hardif_neigh_node; + +/** + * struct batadv_hardif_neigh_slap - SLAP specific neighbor information + */ +struct batadv_hardif_neigh_slap { + /** @neigh: Neighbour hardif */ + struct batadv_hardif_neigh_node __rcu *neigh; + /** @announce: Work to announce our SLAP ID to this neighbor */ + struct delayed_work announce; + /** @release: Work to announce our SLAP ID to this neighbor */ + struct delayed_work release; +}; +#endif + /** * struct batadv_hardif_neigh_node - unique neighbor per hard-interface */ @@ -632,6 +717,15 @@ /** @rcu: struct used for freeing in a RCU-safe manner */ struct rcu_head rcu; + + /** @mtud: struct used for mtu discovery related stuff */ +#ifdef CONFIG_BATMAN_ADV_FBX_MTU + struct batadv_mtu *mtud; +#endif +#ifdef CONFIG_BATMAN_ADV_FBX_SLAP + /** @slap: SLAP specific neighbour information */ + struct batadv_hardif_neigh_slap *slap; +#endif }; /** @@ -708,6 +802,9 @@ /** @last_seqno: last sequence number known for this neighbor */ u32 last_seqno; + + /** @half_duplex: throughput should suffer half duplex penalty */ + bool half_duplex; }; /** @@ -1738,6 +1835,40 @@ /** @bat_v: B.A.T.M.A.N. V per soft-interface private data */ struct batadv_priv_bat_v bat_v; #endif + +#ifdef CONFIG_BATMAN_ADV_FBX + /** @fbx_nl_cmd_handlers: List of NL command handler */ + struct hlist_head fbx_nl_handlers; + /** @fbx_tvlv_handlers: List of FBX specific TVLV handler */ + struct hlist_head fbx_tvlv_handlers; + /** @fbx_tvlv_containers: List of FBX specific TVLV container */ + struct hlist_head fbx_tvlv_containers; + /** @fbx_nl_lock: FBX specific NL handler list lock */ + spinlock_t fbx_nl_lock; + /** @fbx_tvlv_lock: FBX specific TVLV handler list lock */ + spinlock_t fbx_tvlv_lock; +#ifdef CONFIG_BATMAN_ADV_FBX_MTU + /** MTU delayed work */ + atomic_t mtu_seqno; +#endif +#ifdef CONFIG_BATMAN_ADV_FBX_SLAP + /** + * @slap_lock: Common SLAP lock used to serialize rcu write side on + * both bat_priv and neighbor + */ + spinlock_t slap_lock; + /** @slap_master: Current SLAP master */ + struct batadv_slap_id __rcu *slap_master; + /** @slap_iface: Current SLAP hard interface */ + struct batadv_hard_iface __rcu *slap_iface; + /** @slap_id: Current SLAP ID */ + struct batadv_slap_id __rcu *slap_id; + /** @slap_skb: SLAP ID SKB model to use */ + struct sk_buff __rcu *slap_skb; + /* @slap_wq: Common worqueue for delayed SLAP work */ + struct workqueue_struct *slap_wq; +#endif +#endif }; #ifdef CONFIG_BATMAN_ADV_BLA diff -ruw linux-6.4/net/bridge/Kconfig linux-6.4-fbx/net/bridge/Kconfig --- linux-6.4/net/bridge/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/bridge/Kconfig 2023-11-07 16:12:24.794176326 +0100 @@ -34,6 +34,11 @@ If unsure, say N. +config BRIDGE_STATE_MESSAGES + bool "show port status change in kernel log" + depends on BRIDGE + default y + config BRIDGE_IGMP_SNOOPING bool "IGMP/MLD snooping" depends on BRIDGE diff -ruw linux-6.4/net/bridge/br_device.c linux-6.4-fbx/net/bridge/br_device.c --- linux-6.4/net/bridge/br_device.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/bridge/br_device.c 2023-05-22 20:06:45.323882529 +0200 @@ -213,6 +213,7 @@ struct net_bridge *br = netdev_priv(dev); dev->mtu = new_mtu; + br->forced_mtu = new_mtu; /* this flag will be cleared if the MTU was automatically adjusted */ br_opt_toggle(br, BROPT_MTU_SET_BY_USER, true); diff -ruw linux-6.4/net/bridge/br_fdb.c linux-6.4-fbx/net/bridge/br_fdb.c --- linux-6.4/net/bridge/br_fdb.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/bridge/br_fdb.c 2023-12-21 17:30:06.453516726 +0100 @@ -850,6 +850,21 @@ test_and_clear_bit(BR_FDB_NOTIFY_INACTIVE, &fdb->flags)); } +bool br_fdb_update_only(struct net_bridge *br, + struct net_bridge_port *source, + const unsigned char *addr) +{ + struct net_bridge_fdb_entry *fdb; + + fdb = br_fdb_find_rcu(br, addr, 0); + if (!fdb) + return false; + + fdb->updated = jiffies; + return true; +} +EXPORT_SYMBOL(br_fdb_update_only); + void br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid, unsigned long flags) { @@ -992,6 +1007,7 @@ rcu_read_unlock(); return err; } +EXPORT_SYMBOL(br_fdb_find_rcu); /* returns true if the fdb is modified */ static bool fdb_handle_notify(struct net_bridge_fdb_entry *fdb, u8 notify) diff -ruw linux-6.4/net/bridge/br_if.c linux-6.4-fbx/net/bridge/br_if.c --- linux-6.4/net/bridge/br_if.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/bridge/br_if.c 2023-05-22 20:06:45.323882529 +0200 @@ -500,13 +500,13 @@ static int br_mtu_min(const struct net_bridge *br) { const struct net_bridge_port *p; - int ret_mtu = 0; + int ret_mtu = min_t(unsigned int, br->forced_mtu, ETH_DATA_LEN); list_for_each_entry(p, &br->port_list, list) if (!ret_mtu || ret_mtu > p->dev->mtu) ret_mtu = p->dev->mtu; - return ret_mtu ? ret_mtu : ETH_DATA_LEN; + return ret_mtu; } void br_mtu_auto_adjust(struct net_bridge *br) diff -ruw linux-6.4/net/bridge/br_private.h linux-6.4-fbx/net/bridge/br_private.h --- linux-6.4/net/bridge/br_private.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/bridge/br_private.h 2023-12-12 17:24:34.171627426 +0100 @@ -569,6 +569,7 @@ #if IS_ENABLED(CONFIG_BRIDGE_CFM) struct hlist_head mep_list; #endif + unsigned int forced_mtu; }; struct br_input_skb_cb { @@ -623,8 +624,14 @@ br_printk(KERN_WARNING, __br, format, ##args) #define br_notice(__br, format, args...) \ br_printk(KERN_NOTICE, __br, format, ##args) + +#ifdef CONFIG_BRIDGE_STATE_MESSAGES #define br_info(__br, format, args...) \ br_printk(KERN_INFO, __br, format, ##args) +#else +#define br_info(__br, format, args...) \ + pr_debug("%s: " format, (__br)->dev->name, ##args) +#endif #define br_debug(br, format, args...) \ pr_debug("%s: " format, (br)->dev->name, ##args) @@ -811,6 +818,9 @@ unsigned long off); int br_fdb_add_local(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid); +bool br_fdb_update_only(struct net_bridge *br, + struct net_bridge_port *source, + const unsigned char *addr); void br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid, unsigned long flags); diff -ruw linux-6.4/net/core/Makefile linux-6.4-fbx/net/core/Makefile --- linux-6.4/net/core/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/Makefile 2023-11-07 13:38:44.062256691 +0100 @@ -13,7 +13,7 @@ neighbour.o rtnetlink.o utils.o link_watch.o filter.o \ sock_diag.o dev_ioctl.o tso.o sock_reuseport.o \ fib_notifier.o xdp.o flow_offload.o gro.o \ - netdev-genl.o netdev-genl-gen.o + netdev-genl.o netdev-genl-gen.o gso.o obj-$(CONFIG_NETDEV_ADDR_LIST_TEST) += dev_addr_lists_test.o diff -ruw linux-6.4/net/core/dev.c linux-6.4-fbx/net/core/dev.c --- linux-6.4/net/core/dev.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/dev.c 2023-12-12 17:24:34.171627426 +0100 @@ -150,6 +150,7 @@ #include #include #include +#include #include "dev.h" #include "net-sysfs.h" @@ -165,6 +166,10 @@ struct netlink_ext_ack *extack); static struct napi_struct *napi_by_id(unsigned int napi_id); +#ifdef CONFIG_NETRXTHREAD +struct krxd gkrxd[CONFIG_NETRXTHREAD_RX_QUEUE]; +#endif + /* * The @dev_base_head list is protected by @dev_base_lock and the rtnl * semaphore. @@ -3209,7 +3214,7 @@ return (u16) reciprocal_scale(skb_get_hash(skb), qcount) + qoffset; } -static void skb_warn_bad_offload(const struct sk_buff *skb) +void skb_warn_bad_offload(const struct sk_buff *skb) { static const netdev_features_t null_features; struct net_device *dev = skb->dev; @@ -3338,74 +3343,6 @@ return vlan_get_protocol_and_depth(skb, type, depth); } -/* openvswitch calls this on rx path, so we need a different check. - */ -static inline bool skb_needs_check(struct sk_buff *skb, bool tx_path) -{ - if (tx_path) - return skb->ip_summed != CHECKSUM_PARTIAL && - skb->ip_summed != CHECKSUM_UNNECESSARY; - - return skb->ip_summed == CHECKSUM_NONE; -} - -/** - * __skb_gso_segment - Perform segmentation on skb. - * @skb: buffer to segment - * @features: features for the output path (see dev->features) - * @tx_path: whether it is called in TX path - * - * This function segments the given skb and returns a list of segments. - * - * It may return NULL if the skb requires no segmentation. This is - * only possible when GSO is used for verifying header integrity. - * - * Segmentation preserves SKB_GSO_CB_OFFSET bytes of previous skb cb. - */ -struct sk_buff *__skb_gso_segment(struct sk_buff *skb, - netdev_features_t features, bool tx_path) -{ - struct sk_buff *segs; - - if (unlikely(skb_needs_check(skb, tx_path))) { - int err; - - /* We're going to init ->check field in TCP or UDP header */ - err = skb_cow_head(skb, 0); - if (err < 0) - return ERR_PTR(err); - } - - /* Only report GSO partial support if it will enable us to - * support segmentation on this frame without needing additional - * work. - */ - if (features & NETIF_F_GSO_PARTIAL) { - netdev_features_t partial_features = NETIF_F_GSO_ROBUST; - struct net_device *dev = skb->dev; - - partial_features |= dev->features & dev->gso_partial_features; - if (!skb_gso_ok(skb, features | partial_features)) - features &= ~NETIF_F_GSO_PARTIAL; - } - - BUILD_BUG_ON(SKB_GSO_CB_OFFSET + - sizeof(*SKB_GSO_CB(skb)) > sizeof(skb->cb)); - - SKB_GSO_CB(skb)->mac_offset = skb_headroom(skb); - SKB_GSO_CB(skb)->encap_level = 0; - - skb_reset_mac_header(skb); - skb_reset_mac_len(skb); - - segs = skb_mac_gso_segment(skb, features); - - if (segs != skb && unlikely(skb_needs_check(skb, tx_path) && !IS_ERR(segs))) - skb_warn_bad_offload(skb); - - return segs; -} -EXPORT_SYMBOL(__skb_gso_segment); /* Take action when hardware reception checksum errors are detected. */ #ifdef CONFIG_BUG @@ -4959,6 +4896,23 @@ return ret; } +/* Start Freebox added code */ +#if defined(CONFIG_FREEBOX_DIVERTER) || defined(CONFIG_FREEBOX_DIVERTER_MODULE) +int (*fbxdiverter_hook)(struct sk_buff *); + +static int handle_fbxdiverter(struct sk_buff *skb) +{ + /* try_module_get is missing here, so there is a race on + * fbxdiverter module deletion */ + if (!fbxdiverter_hook) + return 0; + return fbxdiverter_hook(skb); +} + +EXPORT_SYMBOL(fbxdiverter_hook); +#endif + + /** * __netif_rx - Slightly optimized version of netif_rx * @skb: buffer to post @@ -5278,28 +5232,116 @@ return 0; } +static int __netif_receive_skb_core_end(struct sk_buff **pskb, bool pfmemalloc, + struct packet_type **ppt_prev); + static int __netif_receive_skb_core(struct sk_buff **pskb, bool pfmemalloc, struct packet_type **ppt_prev) { - struct packet_type *ptype, *pt_prev; - rx_handler_func_t *rx_handler; struct sk_buff *skb = *pskb; - struct net_device *orig_dev; - bool deliver_exact = false; - int ret = NET_RX_DROP; - __be16 type; +#ifdef CONFIG_NETRXTHREAD + unsigned int len; + struct krxd *krxd; +#endif net_timestamp_check(!READ_ONCE(netdev_tstamp_prequeue), skb); trace_netif_receive_skb(skb); - orig_dev = skb->dev; - skb_reset_network_header(skb); if (!skb_transport_header_was_set(skb)) skb_reset_transport_header(skb); skb_reset_mac_len(skb); +#if defined(CONFIG_FREEBOX_DIVERTER) || defined(CONFIG_FREEBOX_DIVERTER_MODULE) + if (handle_fbxdiverter(skb)) + return NET_RX_SUCCESS; +#endif + +#ifndef CONFIG_NETRXTHREAD + return __netif_receive_skb_core_end(pskb, pfmemalloc, ppt_prev); +#else + if (pfmemalloc) + return __netif_receive_skb_core_end(pskb, pfmemalloc, ppt_prev); + + BUILD_BUG_ON(ARRAY_SIZE(gkrxd) < 2); + krxd = &gkrxd[skb->rxthread_prio & 1]; + + /* queue the packet to the rx thread */ + local_bh_disable(); + len = skb_queue_len(&krxd->pkt_queue); + if (len < RXTHREAD_MAX_PKTS) { + __skb_queue_tail(&krxd->pkt_queue, skb); + krxd->stats_pkts++; + if (!len) + wake_up(&krxd->wq); + } else { + krxd->stats_dropped++; + dev_kfree_skb(skb); + } + local_bh_enable(); + return NET_RX_SUCCESS; +#endif +} + +#ifdef CONFIG_NETRXTHREAD +static int krxd_action(void *data) +{ + struct krxd *krxd = (struct krxd *)data; + unsigned int queue = krxd - gkrxd; + struct sk_buff *skb; + + set_user_nice(current, queue > 0 ? -10 : -5); + current->flags |= PF_NOFREEZE; + __set_current_state(TASK_RUNNING); + + local_bh_disable(); + while (1) { + struct packet_type *pt_prev = NULL; + struct net_device *orig_dev; + + skb = skb_dequeue(&krxd->pkt_queue); + if (!skb) { + local_bh_enable(); + wait_event_interruptible(krxd->wq, + skb_queue_len(&krxd->pkt_queue)); + set_current_state(TASK_RUNNING); + local_bh_disable(); + continue; + } + + rcu_read_lock(); + orig_dev = skb->dev; + __netif_receive_skb_core_end(&skb, false, &pt_prev); + if (pt_prev) + INDIRECT_CALL_INET(pt_prev->func, + ipv6_rcv, ip_rcv, skb, + skb->dev, pt_prev, orig_dev); + rcu_read_unlock(); + + /* only schedule when working on lowest prio queue */ + if (queue == 0 && need_resched()) { + local_bh_enable(); + schedule(); + local_bh_disable(); + } + } + return 0; +} +#endif + +static int __netif_receive_skb_core_end(struct sk_buff **pskb, bool pfmemalloc, + struct packet_type **ppt_prev) +{ + struct sk_buff *skb = *pskb; + struct packet_type *ptype, *pt_prev; + rx_handler_func_t *rx_handler; + struct net_device *orig_dev; + bool deliver_exact = false; + int ret = NET_RX_DROP; + __be16 type; + + orig_dev = skb->dev; pt_prev = NULL; another_round: @@ -5457,7 +5499,9 @@ if (pt_prev) { if (unlikely(skb_orphan_frags_rx(skb, GFP_ATOMIC))) goto drop; - *ppt_prev = pt_prev; + else + ret = INDIRECT_CALL_INET(pt_prev->func, ipv6_rcv, ip_rcv, skb, + skb->dev, pt_prev, orig_dev); } else { drop: if (!deliver_exact) @@ -5488,10 +5532,16 @@ struct packet_type *pt_prev = NULL; int ret; +#ifdef CONFIG_NETRXTHREAD + (void)orig_dev; + ret = __netif_receive_skb_core(&skb, pfmemalloc, &pt_prev); +#else ret = __netif_receive_skb_core(&skb, pfmemalloc, &pt_prev); if (pt_prev) ret = INDIRECT_CALL_INET(pt_prev->func, ipv6_rcv, ip_rcv, skb, skb->dev, pt_prev, orig_dev); +#endif + return ret; } @@ -8356,8 +8406,10 @@ } } if (dev->flags != old_flags) { +#ifdef CONFIG_NET_PROMISC_MESSAGES netdev_info(dev, "%s promiscuous mode\n", dev->flags & IFF_PROMISC ? "entered" : "left"); +#endif if (audit_enabled) { current_uid_gid(&uid, &gid); audit_log(audit_context(), GFP_ATOMIC, @@ -8425,8 +8477,10 @@ } } if (dev->flags ^ old_flags) { +#ifdef CONFIG_NET_PROMISC_MESSAGES netdev_info(dev, "%s allmulticast mode\n", dev->flags & IFF_ALLMULTI ? "entered" : "left"); +#endif dev_change_rx_flags(dev, IFF_ALLMULTI); dev_set_rx_mode(dev); if (notify) @@ -11477,6 +11531,24 @@ open_softirq(NET_TX_SOFTIRQ, net_tx_action); open_softirq(NET_RX_SOFTIRQ, net_rx_action); +#ifdef CONFIG_NETRXTHREAD + for (i = 0; i < CONFIG_NETRXTHREAD_RX_QUEUE; i++) { + struct krxd *krxd = &gkrxd[i]; + struct task_struct *task; + + skb_queue_head_init(&krxd->pkt_queue); + init_waitqueue_head(&krxd->wq); + task = kthread_create(krxd_action, krxd, "krxthread_%u", i); + if (IS_ERR(task)) { + printk(KERN_ERR "unable to create krxd\n"); + return -ENOMEM; + } + krxd->task = task; + wake_up_process(task); + } +#endif + + rc = cpuhp_setup_state_nocalls(CPUHP_NET_DEV_DEAD, "net/dev:dead", NULL, dev_cpu_dead); WARN_ON(rc < 0); diff -ruw linux-6.4/net/core/gro.c linux-6.4-fbx/net/core/gro.c --- linux-6.4/net/core/gro.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/gro.c 2023-11-07 13:38:44.066256801 +0100 @@ -10,7 +10,7 @@ #define GRO_MAX_HEAD (MAX_HEADER + 128) static DEFINE_SPINLOCK(offload_lock); -static struct list_head offload_base __read_mostly = LIST_HEAD_INIT(offload_base); +struct list_head offload_base __read_mostly = LIST_HEAD_INIT(offload_base); /* Maximum number of GRO_NORMAL skbs to batch up for list-RX */ int gro_normal_batch __read_mostly = 8; @@ -92,63 +92,6 @@ } EXPORT_SYMBOL(dev_remove_offload); -/** - * skb_eth_gso_segment - segmentation handler for ethernet protocols. - * @skb: buffer to segment - * @features: features for the output path (see dev->features) - * @type: Ethernet Protocol ID - */ -struct sk_buff *skb_eth_gso_segment(struct sk_buff *skb, - netdev_features_t features, __be16 type) -{ - struct sk_buff *segs = ERR_PTR(-EPROTONOSUPPORT); - struct packet_offload *ptype; - - rcu_read_lock(); - list_for_each_entry_rcu(ptype, &offload_base, list) { - if (ptype->type == type && ptype->callbacks.gso_segment) { - segs = ptype->callbacks.gso_segment(skb, features); - break; - } - } - rcu_read_unlock(); - - return segs; -} -EXPORT_SYMBOL(skb_eth_gso_segment); - -/** - * skb_mac_gso_segment - mac layer segmentation handler. - * @skb: buffer to segment - * @features: features for the output path (see dev->features) - */ -struct sk_buff *skb_mac_gso_segment(struct sk_buff *skb, - netdev_features_t features) -{ - struct sk_buff *segs = ERR_PTR(-EPROTONOSUPPORT); - struct packet_offload *ptype; - int vlan_depth = skb->mac_len; - __be16 type = skb_network_protocol(skb, &vlan_depth); - - if (unlikely(!type)) - return ERR_PTR(-EINVAL); - - __skb_pull(skb, vlan_depth); - - rcu_read_lock(); - list_for_each_entry_rcu(ptype, &offload_base, list) { - if (ptype->type == type && ptype->callbacks.gso_segment) { - segs = ptype->callbacks.gso_segment(skb, features); - break; - } - } - rcu_read_unlock(); - - __skb_push(skb, skb->data - skb_mac_header(skb)); - - return segs; -} -EXPORT_SYMBOL(skb_mac_gso_segment); int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb) { diff -ruw linux-6.4/net/core/net-procfs.c linux-6.4-fbx/net/core/net-procfs.c --- linux-6.4/net/core/net-procfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/net-procfs.c 2023-05-22 20:06:45.363883593 +0200 @@ -200,6 +200,89 @@ .show = softnet_seq_show, }; +static struct page_frag_cache *frag_alloc_netdev_get_online(loff_t *pos) +{ + struct page_frag_cache *nc = NULL; + + while (*pos < nr_cpu_ids) + if (cpu_online(*pos)) { + nc = netdev_frag_cache_get(*pos); + break; + } else + ++*pos; + return nc; +} + +static struct page_frag_cache *frag_alloc_napi_get_online(loff_t *pos) +{ + struct page_frag_cache *nc = NULL; + + while (*pos < nr_cpu_ids) + if (cpu_online(*pos)) { + nc = napi_frag_cache_get(*pos); + break; + } else + ++*pos; + return nc; +} + +static void *frag_alloc_netdev_seq_start(struct seq_file *seq, loff_t *pos) +{ + return frag_alloc_netdev_get_online(pos); +} + +static void *frag_alloc_netdev_seq_next(struct seq_file *seq, void *v, loff_t *pos) +{ + ++*pos; + return frag_alloc_netdev_get_online(pos); +} + +static void *frag_alloc_napi_seq_start(struct seq_file *seq, loff_t *pos) +{ + return frag_alloc_napi_get_online(pos); +} + +static void *frag_alloc_napi_seq_next(struct seq_file *seq, void *v, loff_t *pos) +{ + ++*pos; + return frag_alloc_napi_get_online(pos); +} + +static void frag_alloc_seq_stop(struct seq_file *seq, void *v) +{ +} + +static int frag_alloc_seq_show(struct seq_file *seq, void *v) +{ +#ifdef CONFIG_PAGE_OWNER + struct page_frag_cache *nc = v; + unsigned int pages = atomic_read(&nc->pages_allocated); + + seq_printf(seq, + "cpu[%d]: pages:%u (%lu kB)\n", + (int)seq->index, pages, (pages * PAGE_SIZE) / 1024); +#else + seq_printf(seq, + "cpu[%d]: CONFIG_PAGE_OWNER missing\n", + (int)seq->index); +#endif + return 0; +} + +static const struct seq_operations frag_alloc_netdev_seq_ops = { + .start = frag_alloc_netdev_seq_start, + .next = frag_alloc_netdev_seq_next, + .stop = frag_alloc_seq_stop, + .show = frag_alloc_seq_show, +}; + +static const struct seq_operations frag_alloc_napi_seq_ops = { + .start = frag_alloc_napi_seq_start, + .next = frag_alloc_napi_seq_next, + .stop = frag_alloc_seq_stop, + .show = frag_alloc_seq_show, +}; + static void *ptype_get_idx(struct seq_file *seq, loff_t pos) { struct list_head *ptype_list = NULL; @@ -320,6 +403,85 @@ .show = ptype_seq_show, }; +#ifdef CONFIG_NETRXTHREAD +/* + * This is invoked by the /proc filesystem handler to display a device + * in detail. + */ +static void *krxthread_seq_start(struct seq_file *seq, loff_t *pos) +{ + int *queue; + + if (*pos > CONFIG_NETRXTHREAD_RX_QUEUE) + return NULL; + + queue = kmalloc(sizeof(*queue), GFP_KERNEL); + if (!queue) + return NULL; + *queue = ((int)*pos - 1); + + return queue; +} + +static void *krxthread_seq_next(struct seq_file *seq, void *v, loff_t *pos) +{ + int *queue = v; + + if (*pos == CONFIG_NETRXTHREAD_RX_QUEUE) { + ++*pos; + return NULL; + } + + ++*queue; + *pos = *queue + 1; + return queue; +} + +static void krxthread_seq_stop(struct seq_file *seq, void *v) +{ + kfree(v); +} + +static void krxthread_seq_printf_stats(struct seq_file *seq, int queue) +{ + seq_printf(seq, "%8u %12u %12u\n", + queue, + gkrxd[queue].stats_pkts, + gkrxd[queue].stats_dropped); +} + +static int krxthread_seq_show(struct seq_file *seq, void *v) +{ + int *queue = v; + + if (*queue == -1) + seq_printf(seq, "%8s %12s %12s\n", + "queue", "packets", "drops"); + else + krxthread_seq_printf_stats(seq, *queue); + return 0; +} + +static const struct seq_operations krxthread_seq_ops = { + .start = krxthread_seq_start, + .next = krxthread_seq_next, + .stop = krxthread_seq_stop, + .show = krxthread_seq_show, +}; + +static int krxthread_seq_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &krxthread_seq_ops); +} + +static const struct proc_ops krxthread_seq_fops = { + .proc_open = krxthread_seq_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, +}; +#endif /* KRXTHREAD */ + static int __net_init dev_proc_net_init(struct net *net) { int rc = -ENOMEM; @@ -333,9 +495,20 @@ if (!proc_create_net("ptype", 0444, net->proc_net, &ptype_seq_ops, sizeof(struct seq_net_private))) goto out_softnet; + if (!proc_create_seq("frag_alloc_netdev", 0444, net->proc_net, + &frag_alloc_netdev_seq_ops)) + goto out_softnet; + if (!proc_create_seq("frag_alloc_napi", 0444, net->proc_net, + &frag_alloc_napi_seq_ops)) + goto out_softnet; if (wext_proc_init(net)) goto out_ptype; +#ifdef CONFIG_NETRXTHREAD + if (!proc_create("krxthread", S_IRUGO, net->proc_net, + &krxthread_seq_fops)) + goto out_ptype; +#endif rc = 0; out: return rc; diff -ruw linux-6.4/net/core/net-sysfs.c linux-6.4-fbx/net/core/net-sysfs.c --- linux-6.4/net/core/net-sysfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/net-sysfs.c 2023-05-22 20:06:45.363883593 +0200 @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -747,7 +748,28 @@ .attrs = netstat_attrs, }; +#if IS_ENABLED(CONFIG_CFG80211) +static ssize_t show_nl80211_iftype(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct net_device *netdev = to_net_dev(dev); + ssize_t ret = 0; + + if (!rtnl_trylock()) + return restart_syscall(); + if (netdev->ieee80211_ptr) + ret = sprintf(buf, "%d\n", netdev->ieee80211_ptr->iftype); + rtnl_unlock(); + + return ret; +} +static DEVICE_ATTR(nl80211_iftype, S_IRUGO, show_nl80211_iftype, NULL); +#endif + static struct attribute *wireless_attrs[] = { +#if IS_ENABLED(CONFIG_CFG80211) + &dev_attr_nl80211_iftype.attr, +#endif NULL }; diff -ruw linux-6.4/net/core/of_net.c linux-6.4-fbx/net/core/of_net.c --- linux-6.4/net/core/of_net.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/of_net.c 2023-05-22 20:06:45.367883699 +0200 @@ -12,6 +12,7 @@ #include #include #include +#include /** * of_get_phy_mode - Get phy mode for given device_node @@ -96,6 +97,23 @@ } EXPORT_SYMBOL(of_get_mac_address_nvmem); +static int of_get_mac_addr_from_fbxserial(struct device_node *np, u8 *addr) +{ +#ifdef CONFIG_FBXSERIAL + struct property *pp; + + pp = of_find_property(np, "fbxserial-mac-address", NULL); + if (!pp || pp->length != 4) + return -ENODEV; + + memcpy(addr, fbxserialinfo_get_mac_addr(be32_to_cpu(*(u32*)pp->value)), + ETH_ALEN); + return 0; +#else + return -ENOSYS; +#endif +} + /** * of_get_mac_address() * @np: Caller's Device Node @@ -129,6 +147,10 @@ if (!np) return -ENODEV; + ret = of_get_mac_addr_from_fbxserial(np, addr); + if (!ret) + return 0; + ret = of_get_mac_addr(np, "mac-address", addr); if (!ret) return 0; diff -ruw linux-6.4/net/core/page_pool.c linux-6.4-fbx/net/core/page_pool.c --- linux-6.4/net/core/page_pool.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/page_pool.c 2024-01-19 17:01:19.905848123 +0100 @@ -357,6 +357,7 @@ { page->pp = pool; page->pp_magic |= PP_SIGNATURE; + page_pool_clear_recycle_flag(page); if (pool->p.init_callback) pool->p.init_callback(page, pool->p.init_arg); } diff -ruw linux-6.4/net/core/skbuff.c linux-6.4-fbx/net/core/skbuff.c --- linux-6.4/net/core/skbuff.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/skbuff.c 2024-01-19 17:01:19.905848123 +0100 @@ -67,6 +67,7 @@ #include #include #include +#include #include #include #include @@ -281,6 +282,17 @@ static DEFINE_PER_CPU(struct page_frag_cache, netdev_alloc_cache); static DEFINE_PER_CPU(struct napi_alloc_cache, napi_alloc_cache); +struct page_frag_cache *netdev_frag_cache_get(unsigned int cpu_id) +{ + return per_cpu_ptr(&netdev_alloc_cache, cpu_id); +} + +struct page_frag_cache *napi_frag_cache_get(unsigned int cpu_id) +{ + struct napi_alloc_cache *nc = per_cpu_ptr(&napi_alloc_cache, cpu_id); + return &nc->page; +} + /* Double check that napi_get_frags() allocates skbs with * skb->head being backed by slab, not a page fragment. * This is to make sure bug fixed in 3226b158e67c @@ -893,6 +905,11 @@ { if (!IS_ENABLED(CONFIG_PAGE_POOL) || !skb->pp_recycle) return false; + +#ifdef CONFIG_IP_FFN + if (skb->ffn_ff_done & BIT(1)) + page_pool_set_recycled_flag(virt_to_page(data)); +#endif return page_pool_return_skb_page(virt_to_page(data), napi_safe); } @@ -1345,6 +1362,11 @@ new->queue_mapping = old->queue_mapping; memcpy(&new->headers, &old->headers, sizeof(new->headers)); + +#ifdef CONFIG_IP_FFN + new->ffn_state = FFN_STATE_INIT; + new->ffn_ff_done = 0; +#endif CHECK_SKB_FIELD(protocol); CHECK_SKB_FIELD(csum); CHECK_SKB_FIELD(hash); @@ -5774,157 +5796,20 @@ skb->offload_fwd_mark = 0; skb->offload_l3_fwd_mark = 0; #endif + skb->mark = 0; +#ifdef CONFIG_IP_FFN + skb->ffn_state = FFN_STATE_INIT; + skb->ffn_ff_done = 0; +#endif if (!xnet) return; ipvs_reset(skb); - skb->mark = 0; skb_clear_tstamp(skb); } EXPORT_SYMBOL_GPL(skb_scrub_packet); -/** - * skb_gso_transport_seglen - Return length of individual segments of a gso packet - * - * @skb: GSO skb - * - * skb_gso_transport_seglen is used to determine the real size of the - * individual segments, including Layer4 headers (TCP/UDP). - * - * The MAC/L2 or network (IP, IPv6) headers are not accounted for. - */ -static unsigned int skb_gso_transport_seglen(const struct sk_buff *skb) -{ - const struct skb_shared_info *shinfo = skb_shinfo(skb); - unsigned int thlen = 0; - - if (skb->encapsulation) { - thlen = skb_inner_transport_header(skb) - - skb_transport_header(skb); - - if (likely(shinfo->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))) - thlen += inner_tcp_hdrlen(skb); - } else if (likely(shinfo->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))) { - thlen = tcp_hdrlen(skb); - } else if (unlikely(skb_is_gso_sctp(skb))) { - thlen = sizeof(struct sctphdr); - } else if (shinfo->gso_type & SKB_GSO_UDP_L4) { - thlen = sizeof(struct udphdr); - } - /* UFO sets gso_size to the size of the fragmentation - * payload, i.e. the size of the L4 (UDP) header is already - * accounted for. - */ - return thlen + shinfo->gso_size; -} - -/** - * skb_gso_network_seglen - Return length of individual segments of a gso packet - * - * @skb: GSO skb - * - * skb_gso_network_seglen is used to determine the real size of the - * individual segments, including Layer3 (IP, IPv6) and L4 headers (TCP/UDP). - * - * The MAC/L2 header is not accounted for. - */ -static unsigned int skb_gso_network_seglen(const struct sk_buff *skb) -{ - unsigned int hdr_len = skb_transport_header(skb) - - skb_network_header(skb); - - return hdr_len + skb_gso_transport_seglen(skb); -} - -/** - * skb_gso_mac_seglen - Return length of individual segments of a gso packet - * - * @skb: GSO skb - * - * skb_gso_mac_seglen is used to determine the real size of the - * individual segments, including MAC/L2, Layer3 (IP, IPv6) and L4 - * headers (TCP/UDP). - */ -static unsigned int skb_gso_mac_seglen(const struct sk_buff *skb) -{ - unsigned int hdr_len = skb_transport_header(skb) - skb_mac_header(skb); - - return hdr_len + skb_gso_transport_seglen(skb); -} - -/** - * skb_gso_size_check - check the skb size, considering GSO_BY_FRAGS - * - * There are a couple of instances where we have a GSO skb, and we - * want to determine what size it would be after it is segmented. - * - * We might want to check: - * - L3+L4+payload size (e.g. IP forwarding) - * - L2+L3+L4+payload size (e.g. sanity check before passing to driver) - * - * This is a helper to do that correctly considering GSO_BY_FRAGS. - * - * @skb: GSO skb - * - * @seg_len: The segmented length (from skb_gso_*_seglen). In the - * GSO_BY_FRAGS case this will be [header sizes + GSO_BY_FRAGS]. - * - * @max_len: The maximum permissible length. - * - * Returns true if the segmented length <= max length. - */ -static inline bool skb_gso_size_check(const struct sk_buff *skb, - unsigned int seg_len, - unsigned int max_len) { - const struct skb_shared_info *shinfo = skb_shinfo(skb); - const struct sk_buff *iter; - - if (shinfo->gso_size != GSO_BY_FRAGS) - return seg_len <= max_len; - - /* Undo this so we can re-use header sizes */ - seg_len -= GSO_BY_FRAGS; - - skb_walk_frags(skb, iter) { - if (seg_len + skb_headlen(iter) > max_len) - return false; - } - - return true; -} - -/** - * skb_gso_validate_network_len - Will a split GSO skb fit into a given MTU? - * - * @skb: GSO skb - * @mtu: MTU to validate against - * - * skb_gso_validate_network_len validates if a given skb will fit a - * wanted MTU once split. It considers L3 headers, L4 headers, and the - * payload. - */ -bool skb_gso_validate_network_len(const struct sk_buff *skb, unsigned int mtu) -{ - return skb_gso_size_check(skb, skb_gso_network_seglen(skb), mtu); -} -EXPORT_SYMBOL_GPL(skb_gso_validate_network_len); - -/** - * skb_gso_validate_mac_len - Will a split GSO skb fit in a given length? - * - * @skb: GSO skb - * @len: length to validate against - * - * skb_gso_validate_mac_len validates if a given skb will fit a wanted - * length once split, including L2, L3 and L4 headers and the payload. - */ -bool skb_gso_validate_mac_len(const struct sk_buff *skb, unsigned int len) -{ - return skb_gso_size_check(skb, skb_gso_mac_seglen(skb), len); -} -EXPORT_SYMBOL_GPL(skb_gso_validate_mac_len); - static struct sk_buff *skb_reorder_vlan_header(struct sk_buff *skb) { int mac_len, meta_len; diff -ruw linux-6.4/net/core/sock.c linux-6.4-fbx/net/core/sock.c --- linux-6.4/net/core/sock.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/core/sock.c 2023-06-27 11:47:16.143869010 +0200 @@ -1526,6 +1526,10 @@ WRITE_ONCE(sk->sk_txrehash, (u8)val); break; + case SO_UDP_DUP_UNICAST: + sock_valbool_flag(sk, SOCK_UDP_DUP_UNICAST, valbool); + break; + default: ret = -ENOPROTOOPT; break; @@ -1896,6 +1900,10 @@ v.val64 = sock_gen_cookie(sk); break; + case SO_UDP_DUP_UNICAST: + v.val = sock_flag(sk, SOCK_UDP_DUP_UNICAST); + break; + case SO_ZEROCOPY: v.val = sock_flag(sk, SOCK_ZEROCOPY); break; diff -ruw linux-6.4/net/dsa/Kconfig linux-6.4-fbx/net/dsa/Kconfig --- linux-6.4/net/dsa/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/dsa/Kconfig 2023-05-22 20:06:45.383884125 +0200 @@ -63,6 +63,10 @@ Say Y or M if you want to enable support for tagging frames for the Hirschmann Hellcreek TSN switches. +config NET_DSA_TAG_BRCM_FBX + tristate "Tag driver for Broadcom switches using in-frame headers" + select NET_DSA_TAG_BRCM_COMMON + config NET_DSA_TAG_GSWIP tristate "Tag driver for Lantiq / Intel GSWIP switches" help diff -ruw linux-6.4/net/dsa/dsa.c linux-6.4-fbx/net/dsa/dsa.c --- linux-6.4/net/dsa/dsa.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/dsa/dsa.c 2023-08-16 14:13:31.823188647 +0200 @@ -421,6 +421,32 @@ return cpu_dp; } +/* + * find cpu port forcibly assigned to this port via device tree + */ +static struct dsa_port * +dsa_port_get_forced_cpu_port(struct dsa_switch_tree *dst, + struct dsa_port *dp) +{ + struct device_node *cpu_dn; + struct dsa_switch *ds = dp->ds; + + cpu_dn = of_parse_phandle(dp->dn, "dsa,cpu-port", 0); + if (!cpu_dn) + return ERR_PTR(-ENOENT); + + list_for_each_entry (dp, &dst->ports, list) { + if (!dsa_port_is_cpu(dp)) + continue; + + if (dp->dn == cpu_dn) + return dp; + } + + dev_err(ds->dev, "failed to find cpu port referenced by phandle"); + return ERR_PTR(-EINVAL); +} + /* Perform initial assignment of CPU ports to user ports and DSA links in the * fabric, giving preference to CPU ports local to each switch. Default to * using the first CPU port in the switch tree if the port does not have a CPU @@ -429,17 +455,49 @@ static int dsa_tree_setup_cpu_ports(struct dsa_switch_tree *dst) { struct dsa_port *preferred_cpu_dp, *cpu_dp, *dp; + size_t loop; + + /* + * first pass to assign explicit cpu port assigned through DT + * to user ports + */ + list_for_each_entry(dp, &dst->ports, list) { + if (!dsa_port_is_user(dp) && !dsa_port_is_dsa(dp)) + continue; + + preferred_cpu_dp = dsa_switch_preferred_default_local_cpu_port(dp->ds); + if (preferred_cpu_dp && preferred_cpu_dp != dp) + continue; + + cpu_dp = dsa_port_get_forced_cpu_port(dst, dp); + + if (IS_ERR(cpu_dp)) { + if (PTR_ERR(cpu_dp) == -EINVAL) + return -EINVAL; + continue; + } + dp->cpu_dp = cpu_dp; + } + + /* + * for user ports without explicit cpu port, we will assigned + * one CPU port from the same switch, first lookup default CPU + * port if it's declared in DT, or fallback to first cpu port + */ + for (loop = 0; loop < 2; loop++) { list_for_each_entry(cpu_dp, &dst->ports, list) { if (!dsa_port_is_cpu(cpu_dp)) continue; - preferred_cpu_dp = dsa_switch_preferred_default_local_cpu_port(cpu_dp->ds); - if (preferred_cpu_dp && preferred_cpu_dp != cpu_dp) + if (loop == 0 && !cpu_dp->is_def_cpu_port) continue; + list_for_each_entry(dp, &dst->ports, list) { /* Prefer a local CPU port */ - dsa_switch_for_each_port(dp, cpu_dp->ds) { + if (dp->ds != cpu_dp->ds) + continue; + /* Prefer the first local CPU port found */ if (dp->cpu_dp) continue; @@ -448,7 +506,10 @@ dp->cpu_dp = cpu_dp; } } + } + /* finally handle all remaining user ports, which don't have a + * CPU port on the same switch */ return dsa_tree_setup_default_cpu(dst); } @@ -1222,6 +1283,7 @@ dp->type = DSA_PORT_TYPE_CPU; dsa_port_set_tag_protocol(dp, dst->tag_ops); dp->dst = dst; + dp->is_def_cpu_port = of_property_read_bool(dp->dn, "dsa,def-cpu-port"); /* At this point, the tree may be configured to use a different * tagger than the one chosen by the switch driver during diff -ruw linux-6.4/net/dsa/slave.c linux-6.4-fbx/net/dsa/slave.c --- linux-6.4/net/dsa/slave.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/dsa/slave.c 2023-05-22 20:06:45.383884125 +0200 @@ -515,7 +515,7 @@ ndm->ndm_family = AF_BRIDGE; ndm->ndm_pad1 = 0; ndm->ndm_pad2 = 0; - ndm->ndm_flags = NTF_SELF; + ndm->ndm_flags = NTF_SELF | NTF_OFFLOADED; ndm->ndm_type = 0; ndm->ndm_ifindex = dump->dev->ifindex; ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; @@ -2389,7 +2389,7 @@ return 0; } -static const struct net_device_ops dsa_slave_netdev_ops = { +const struct net_device_ops dsa_slave_netdev_ops = { .ndo_open = dsa_slave_open, .ndo_stop = dsa_slave_close, .ndo_start_xmit = dsa_slave_xmit, diff -ruw linux-6.4/net/dsa/slave.h linux-6.4-fbx/net/dsa/slave.h --- linux-6.4/net/dsa/slave.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/dsa/slave.h 2023-05-22 20:06:45.383884125 +0200 @@ -51,6 +51,13 @@ int dsa_slave_manage_vlan_filtering(struct net_device *dev, bool vlan_filtering); +extern const struct net_device_ops dsa_slave_netdev_ops; + +static inline bool dsa_is_slave(const struct net_device *dev) +{ + return (dev->netdev_ops == &dsa_slave_netdev_ops); +} + static inline struct dsa_port *dsa_slave_to_port(const struct net_device *dev) { struct dsa_slave_priv *p = netdev_priv(dev); diff -ruw linux-6.4/net/dsa/tag_brcm.c linux-6.4-fbx/net/dsa/tag_brcm.c --- linux-6.4/net/dsa/tag_brcm.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/dsa/tag_brcm.c 2023-05-22 20:06:45.387884231 +0200 @@ -79,7 +79,8 @@ #define BRCM_EG_PID_MASK 0x1f #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) || \ - IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) + IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) || \ + IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_FBX) static struct sk_buff *brcm_tag_xmit_ll(struct sk_buff *skb, struct net_device *dev, @@ -177,7 +178,8 @@ } #endif -#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) || \ + IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_FBX) static struct sk_buff *brcm_tag_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -199,7 +201,9 @@ return nskb; } +#endif +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) static const struct dsa_device_ops brcm_netdev_ops = { .name = BRCM_NAME, .proto = DSA_TAG_PROTO_BRCM, @@ -321,6 +325,37 @@ MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM_PREPEND, BRCM_PREPEND_NAME); #endif +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_FBX) +static struct sk_buff * +brcm_tag_rcv_fbx(struct sk_buff *skb, struct net_device *dev) +{ + struct sk_buff *nskb = brcm_tag_rcv(skb, dev); + + if (!nskb) + return nskb; + + /* if the packet was broadcast, the switch already did the + * flood to the other ports */ + if (nskb->pkt_type == PACKET_BROADCAST) + nskb->offload_fwd_mark = 1; + else + nskb->offload_fwd_mark = 0; + + return nskb; +} + +static const struct dsa_device_ops brcm_fbx_netdev_ops = { + .name = "brcm-fbx", + .proto = DSA_TAG_PROTO_BRCM_FBX, + .xmit = brcm_tag_xmit, + .rcv = brcm_tag_rcv_fbx, + .needed_headroom = BRCM_TAG_LEN, +}; + +DSA_TAG_DRIVER(brcm_fbx_netdev_ops); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM_FBX, "brcm-fbx"); +#endif + static struct dsa_tag_driver *dsa_tag_driver_array[] = { #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) &DSA_TAG_DRIVER_NAME(brcm_netdev_ops), @@ -331,6 +366,9 @@ #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) &DSA_TAG_DRIVER_NAME(brcm_prepend_netdev_ops), #endif +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_FBX) + &DSA_TAG_DRIVER_NAME(brcm_fbx_netdev_ops), +#endif }; module_dsa_tag_drivers(dsa_tag_driver_array); diff -ruw linux-6.4/net/ethernet/eth.c linux-6.4-fbx/net/ethernet/eth.c --- linux-6.4/net/ethernet/eth.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ethernet/eth.c 2023-05-22 20:06:45.387884231 +0200 @@ -62,6 +62,7 @@ #include #include #include +#include /** * eth_header - create the Ethernet header @@ -609,6 +610,21 @@ */ int fwnode_get_mac_address(struct fwnode_handle *fwnode, char *addr) { +#ifdef CONFIG_FBXSERIAL + u32 index; + int ret; + + ret = fwnode_property_read_u32(fwnode, "fbxserial-mac-address", + &index); + if (ret == 0) { + const void *res = fbxserialinfo_get_mac_addr(index); + if (res) { + memcpy(addr, res, ETH_ALEN); + return 0; + } + } +#endif + if (!fwnode_get_mac_addr(fwnode, "mac-address", addr) || !fwnode_get_mac_addr(fwnode, "local-mac-address", addr) || !fwnode_get_mac_addr(fwnode, "address", addr)) diff -ruw linux-6.4/net/ethtool/common.c linux-6.4-fbx/net/ethtool/common.c --- linux-6.4/net/ethtool/common.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ethtool/common.c 2023-05-31 17:11:03.421680714 +0200 @@ -211,6 +211,12 @@ __DEFINE_LINK_MODE_NAME(10, T1S, Full), __DEFINE_LINK_MODE_NAME(10, T1S, Half), __DEFINE_LINK_MODE_NAME(10, T1S_P2MP, Half), + __DEFINE_LINK_MODE_NAME(1000, PX_D, Full), + __DEFINE_LINK_MODE_NAME(1000, PX_U, Full), + __DEFINE_LINK_MODE_NAME(10000, PR_D, Full), + __DEFINE_LINK_MODE_NAME(10000, PR_U, Full), + __DEFINE_LINK_MODE_NAME(10000_1000, PRX_D, Full), + __DEFINE_LINK_MODE_NAME(10000_1000, PRX_U, Full), }; static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); @@ -251,6 +257,10 @@ #define __LINK_MODE_LANES_T1S_P2MP 1 #define __LINK_MODE_LANES_VR8 8 #define __LINK_MODE_LANES_DR8_2 8 +#define __LINK_MODE_LANES_PX_D 1 +#define __LINK_MODE_LANES_PX_U 1 +#define __LINK_MODE_LANES_PR_U 1 +#define __LINK_MODE_LANES_PR_D 1 #define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \ [ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \ @@ -374,6 +384,18 @@ __DEFINE_LINK_MODE_PARAMS(10, T1S, Full), __DEFINE_LINK_MODE_PARAMS(10, T1S, Half), __DEFINE_LINK_MODE_PARAMS(10, T1S_P2MP, Half), + __DEFINE_LINK_MODE_PARAMS(1000, PX_D, Full), + __DEFINE_LINK_MODE_PARAMS(1000, PX_U, Full), + __DEFINE_LINK_MODE_PARAMS(10000, PR_D, Full), + __DEFINE_LINK_MODE_PARAMS(10000, PR_U, Full), + [ETHTOOL_LINK_MODE_10000_1000basePRX_D_Full_BIT] = { + .speed = SPEED_10000, + .duplex = DUPLEX_FULL, + }, + [ETHTOOL_LINK_MODE_10000_1000basePRX_U_Full_BIT] = { + .speed = SPEED_10000, + .duplex = DUPLEX_FULL, + }, }; static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS); diff -ruw linux-6.4/net/ethtool/ioctl.c linux-6.4-fbx/net/ethtool/ioctl.c --- linux-6.4/net/ethtool/ioctl.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ethtool/ioctl.c 2023-05-31 17:11:03.425680822 +0200 @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -179,6 +180,9 @@ if (sset == ETH_SS_LINK_MODES) return __ETHTOOL_LINK_MODE_MASK_NBITS; + if (sset == ETH_SS_PHYLINK_IFTYPES) + return PHY_INTERFACE_MODE_MAX - 1; + if (ops->get_sset_count && ops->get_strings) return ops->get_sset_count(dev, sset); else @@ -208,7 +212,16 @@ else if (stringset == ETH_SS_LINK_MODES) memcpy(data, link_mode_names, __ETHTOOL_LINK_MODE_MASK_NBITS * ETH_GSTRING_LEN); - else + else if (stringset == ETH_SS_PHYLINK_IFTYPES) { + int i; + + for (i = PHY_INTERFACE_MODE_NA + 1; + i < PHY_INTERFACE_MODE_MAX; i++) { + strlcpy(data + (i - 1) * ETH_GSTRING_LEN, + phy_modes(i), + ETH_GSTRING_LEN); + } + } else /* ops->get_strings is valid because checked earlier */ ops->get_strings(dev, stringset, data); } @@ -2624,6 +2637,7 @@ switch (tuna->id) { case ETHTOOL_PHY_DOWNSHIFT: case ETHTOOL_PHY_FAST_LINK_DOWN: + case ETHTOOL_PHY_BROKEN: if (tuna->len != sizeof(u8) || tuna->type_id != ETHTOOL_TUNABLE_U8) return -EINVAL; @@ -2750,6 +2764,156 @@ return dev->ethtool_ops->set_fecparam(dev, &fecparam); } +static int ethtool_get_sfp_state(struct net_device *dev, void __user *useraddr) +{ + struct ethtool_sfp_state sfp_state; + int rc; + + if (!dev->sfp_bus) { + printk("no SFP bus ya twat.\n"); + return -ENODEV; + } + + rc = sfp_get_sfp_state(dev->sfp_bus, &sfp_state); + if (rc) + return rc; + + if (copy_to_user(useraddr, &sfp_state, sizeof (sfp_state))) + return -EFAULT; + return 0; +} + +static int ethtool_get_shaper_params(struct net_device *dev, void __user *uaddr) +{ + struct ethtool_shaper_params sp; + int rc; + + if (!dev->ethtool_ops->get_shaper_param) + return -EOPNOTSUPP; + + memset(&sp, 0, sizeof (sp)); + rc = dev->ethtool_ops->get_shaper_param(dev, &sp); + if (rc) + return rc; + + if (copy_to_user(uaddr, &sp, sizeof (sp))) + return -EFAULT; + + return 0; +} + +static int ethtool_set_shaper_params(struct net_device *dev, void __user *uaddr) +{ + struct ethtool_shaper_params sp; + + if (!dev->ethtool_ops->set_shaper_param) + return -EOPNOTSUPP; + + if (copy_from_user(&sp, uaddr, sizeof (sp))) + return -EFAULT; + + return dev->ethtool_ops->set_shaper_param(dev, &sp); +} + +static int ethtool_get_eponparam(struct net_device *dev, void __user *useraddr) +{ + struct ethtool_epon_param eponparam = { .cmd = ETHTOOL_GEPON_PARAM }; + int rc; + + if (!dev->ethtool_ops->get_epon_param) + return -EOPNOTSUPP; + + rc = dev->ethtool_ops->get_epon_param(dev, &eponparam); + if (rc) + return rc; + + if (copy_to_user(useraddr, &eponparam, sizeof(eponparam))) + return -EFAULT; + return 0; +} + +static int ethtool_set_eponparam(struct net_device *dev, void __user *useraddr) +{ + struct ethtool_epon_param eponparam; + + if (!dev->ethtool_ops->set_epon_param) + return -EOPNOTSUPP; + + if (copy_from_user(&eponparam, useraddr, sizeof(eponparam))) + return -EFAULT; + + return dev->ethtool_ops->set_epon_param(dev, &eponparam); +} + +#ifdef CONFIG_PHYLINK +static int ethtool_get_phylink_iftype(struct net_device *dev, void __user *uaddr) +{ + struct ethtool_phylink_iftype sp; + phy_interface_t interface; + struct phylink *pl; + int mode, an_enable; + + if (!dev->ethtool_ops->get_phylink) + return -EOPNOTSUPP; + + pl = dev->ethtool_ops->get_phylink(dev); + if (!pl) + return -EIO; + + memset(&sp, 0, sizeof (sp)); + phylink_get_interface(pl, &interface, &an_enable, &mode); + strlcpy(sp.iftype, phy_modes(interface), sizeof (sp.iftype)); + sp.autoneg_en = an_enable; + sp.mode = mode; + + if (copy_to_user(uaddr, &sp, sizeof (sp))) + return -EFAULT; + + return 0; +} +#else +static inline int ethtool_get_phylink_iftype(struct net_device *dev, void __user *uaddr) +{ + return -ENOTSUPP; +} +#endif + +#ifdef CONFIG_PHYLINK +static int ethtool_set_phylink_iftype(struct net_device *dev, void __user *uaddr) +{ + struct ethtool_phylink_iftype sp; + phy_interface_t i; + struct phylink *pl; + + if (copy_from_user(&sp, uaddr, sizeof (sp))) + return -EFAULT; + + if (!dev->ethtool_ops->get_phylink) + return -EOPNOTSUPP; + + pl = dev->ethtool_ops->get_phylink(dev); + if (!pl) + return -EIO; + + sp.iftype[sizeof (sp.iftype) - 1] = 0; + + for (i = PHY_INTERFACE_MODE_NA; i < PHY_INTERFACE_MODE_MAX; i++) { + if (!strcmp(phy_modes(i), sp.iftype)) + break; + } + + if (i == PHY_INTERFACE_MODE_MAX) + return -EINVAL; + + return phylink_set_interface(pl, i, sp.autoneg_en ? 1 : 0); +} +#else +static inline int ethtool_set_phylink_iftype(struct net_device *dev, void __user *uaddr) +{ + return -ENOTSUPP; +} +#endif + /* The main entry point in this file. Called from net/core/dev_ioctl.c */ static int @@ -3036,6 +3200,33 @@ case ETHTOOL_SFECPARAM: rc = ethtool_set_fecparam(dev, useraddr); break; + case ETHTOOL_SSHAPER_PARAMS: + rc = ethtool_set_shaper_params(dev, useraddr); + break; + case ETHTOOL_GSHAPER_PARAMS: + rc = ethtool_get_shaper_params(dev, useraddr); + break; + case ETHTOOL_GEPON_PARAM: + rc = ethtool_get_eponparam(dev, useraddr); + break; + case ETHTOOL_SEPON_KEYS: + case ETHTOOL_SEPON_ENCRYPT: + case ETHTOOL_SEPON_RESTART: + case ETHTOOL_SEPON_BURST: + case ETHTOOL_SEPON_ADD_MCLLID: + case ETHTOOL_SEPON_DEL_MCLLID: + case ETHTOOL_SEPON_CLR_MCLLID: + rc = ethtool_set_eponparam(dev, useraddr); + break; + case ETHTOOL_GSFP_STATE: + rc = ethtool_get_sfp_state(dev, useraddr); + break; + case ETHTOOL_GPHYLINK_IFTYPE: + rc = ethtool_get_phylink_iftype(dev, useraddr); + break; + case ETHTOOL_SPHYLINK_IFTYPE: + rc = ethtool_set_phylink_iftype(dev, useraddr); + break; default: rc = -EOPNOTSUPP; } diff -ruw linux-6.4/net/ipv4/Makefile linux-6.4-fbx/net/ipv4/Makefile --- linux-6.4/net/ipv4/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/Makefile 2023-05-22 20:06:45.399884550 +0200 @@ -20,6 +20,8 @@ obj-$(CONFIG_NET_IP_TUNNEL) += ip_tunnel.o obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o + +obj-$(CONFIG_IP_FFN) += ip_ffn.o obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o obj-$(CONFIG_IP_MROUTE) += ipmr.o diff -ruw linux-6.4/net/ipv4/af_inet.c linux-6.4-fbx/net/ipv4/af_inet.c --- linux-6.4/net/ipv4/af_inet.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/af_inet.c 2023-11-07 13:38:44.066256801 +0100 @@ -100,6 +100,7 @@ #include #include #include +#include #include #include #include diff -ruw linux-6.4/net/ipv4/gre_offload.c linux-6.4-fbx/net/ipv4/gre_offload.c --- linux-6.4/net/ipv4/gre_offload.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/gre_offload.c 2023-11-07 13:38:44.066256801 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include static struct sk_buff *gre_gso_segment(struct sk_buff *skb, netdev_features_t features) diff -ruw linux-6.4/net/ipv4/ip_input.c linux-6.4-fbx/net/ipv4/ip_input.c --- linux-6.4/net/ipv4/ip_input.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/ip_input.c 2023-05-22 20:06:45.415884976 +0200 @@ -224,8 +224,12 @@ } } -static int ip_local_deliver_finish(struct net *net, struct sock *sk, struct sk_buff *skb) +int ip_local_deliver_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ip_ffn_add(skb, IP_FFN_LOCAL_IN); +#endif skb_clear_delivery_time(skb); __skb_pull(skb, skb_network_header_len(skb)); @@ -566,6 +570,11 @@ if (skb == NULL) return NET_RX_DROP; +#ifdef CONFIG_IP_FFN + if (!ip_ffn_process(skb)) + return NET_RX_SUCCESS; +#endif + return NF_HOOK(NFPROTO_IPV4, NF_INET_PRE_ROUTING, net, NULL, skb, dev, NULL, ip_rcv_finish); diff -ruw linux-6.4/net/ipv4/ip_output.c linux-6.4-fbx/net/ipv4/ip_output.c --- linux-6.4/net/ipv4/ip_output.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/ip_output.c 2023-11-07 13:38:44.066256801 +0100 @@ -73,6 +73,7 @@ #include #include #include +#include #include #include #include @@ -219,6 +220,11 @@ return res; } +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ip_ffn_add(skb, IP_FFN_FINISH_OUT); +#endif + rcu_read_lock(); neigh = ip_neigh_for_gw(rt, skb, &is_v6gw); if (!IS_ERR(neigh)) { @@ -428,6 +434,11 @@ skb->dev = dev; skb->protocol = htons(ETH_P_IP); +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FAST_FORWARDED) + return ip_finish_output(net, sk, skb); +#endif + return NF_HOOK_COND(NFPROTO_IPV4, NF_INET_POST_ROUTING, net, sk, skb, indev, dev, ip_finish_output, @@ -1769,4 +1780,7 @@ #if defined(CONFIG_IP_MULTICAST) igmp_mc_init(); #endif +#ifdef CONFIG_IP_FFN + ip_ffn_init(); +#endif } diff -ruw linux-6.4/net/ipv4/ip_tunnel_core.c linux-6.4-fbx/net/ipv4/ip_tunnel_core.c --- linux-6.4/net/ipv4/ip_tunnel_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/ip_tunnel_core.c 2023-05-22 20:06:45.419885082 +0200 @@ -38,6 +38,9 @@ #include #include #include +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) +#include +#endif const struct ip_tunnel_encap_ops __rcu * iptun_encaps[MAX_IPTUN_ENCAP_OPS] __read_mostly; @@ -60,6 +63,11 @@ skb_scrub_packet(skb, xnet); skb_clear_hash_if_not_l4(skb); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + if (proto == IPPROTO_IPV6) + nf_ct_set(skb, NULL, IP_CT_UNTRACKED); +#endif + skb_dst_set(skb, &rt->dst); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); diff -ruw linux-6.4/net/ipv4/ipconfig.c linux-6.4-fbx/net/ipv4/ipconfig.c --- linux-6.4/net/ipv4/ipconfig.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/ipconfig.c 2023-05-22 20:06:45.419885082 +0200 @@ -197,16 +197,62 @@ static struct ic_device *ic_first_dev __initdata; /* List of open device */ static struct ic_device *ic_dev __initdata; /* Selected device */ -static bool __init ic_is_init_dev(struct net_device *dev) +static bool __init ic_is_init_dev(struct net_device *dev, bool partial) { + char *p = NULL; + bool ret; + if (dev->flags & IFF_LOOPBACK) return false; - return user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : + + if (partial) { + p = strchr(user_dev_name, '.'); + if (p) + *p = 0; + } + + ret = false; + if (user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : (!(dev->flags & IFF_LOOPBACK) && (dev->flags & (IFF_POINTOPOINT|IFF_BROADCAST)) && - strncmp(dev->name, "dummy", 5)); + strncmp(dev->name, "dummy", 5))) + ret = true; + if (p) + *p = '.'; + return ret; } +#ifdef CONFIG_VLAN_8021Q +int register_vlan_device(struct net_device *real_dev, u16 vlan_id); + +static void __init prepare_vlan(void) +{ + unsigned short oflags; + struct net_device *dev; + char *p; + u16 vid; + + if (!strchr(user_dev_name, '.')) + return; + + p = strchr(user_dev_name, '.'); + *p = 0; + vid = simple_strtoul(p + 1, NULL, 10); + dev = __dev_get_by_name(&init_net, user_dev_name); + if (!dev) + goto fail; + + oflags = dev->flags; + if (dev_change_flags(dev, oflags | IFF_UP, NULL) < 0) + goto fail; + + register_vlan_device(dev, vid); + +fail: + *p = '.'; +} +#endif + static int __init ic_open_devs(void) { struct ic_device *d, **last; @@ -225,8 +271,13 @@ pr_err("IP-Config: Failed to open %s\n", dev->name); } +#ifdef CONFIG_VLAN_8021Q + /* register vlan device if needed */ + prepare_vlan(); +#endif + for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, false)) { int able = 0; if (dev->mtu >= 364) able |= IC_BOOTP; @@ -281,7 +332,7 @@ rtnl_lock(); for_each_netdev(&init_net, dev) - if (ic_is_init_dev(dev) && netif_carrier_ok(dev)) { + if (ic_is_init_dev(dev, false) && netif_carrier_ok(dev)) { rtnl_unlock(); goto have_carrier; } @@ -729,8 +780,10 @@ e += len; } if (*vendor_class_identifier) { +#ifdef IPCONFIG_DEBUG pr_info("DHCP: sending class identifier \"%s\"\n", vendor_class_identifier); +#endif *e++ = 60; /* Class-identifier */ len = strlen(vendor_class_identifier); *e++ = len; @@ -1445,7 +1498,7 @@ rtnl_lock(); for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, true)) { found = 1; break; } diff -ruw linux-6.4/net/ipv4/netfilter/Kconfig linux-6.4-fbx/net/ipv4/netfilter/Kconfig --- linux-6.4/net/ipv4/netfilter/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/netfilter/Kconfig 2023-05-22 20:06:45.427885295 +0200 @@ -6,6 +6,13 @@ menu "IP: Netfilter Configuration" depends on INET && NETFILTER +config IP_FFN + bool "IP: Fast forwarding and NAT" + +config IP_FFN_PROCFS + bool "IP: Fast forwarding and NAT /proc/net entries" + depends on IP_FFN + config NF_DEFRAG_IPV4 tristate default n diff -ruw linux-6.4/net/ipv4/netfilter/ip_tables.c linux-6.4-fbx/net/ipv4/netfilter/ip_tables.c --- linux-6.4/net/ipv4/netfilter/ip_tables.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/netfilter/ip_tables.c 2023-05-22 20:06:45.427885295 +0200 @@ -1099,6 +1099,8 @@ return ret; } +extern void fbxbr_flush_cache(void); + static int do_replace(struct net *net, sockptr_t arg, unsigned int len) { @@ -1138,6 +1140,14 @@ tmp.num_counters, tmp.counters); if (ret) goto free_newinfo_untrans; + +#ifdef CONFIG_FBXBRIDGE + fbxbr_flush_cache(); +#endif + +#ifdef CONFIG_IP_FFN + ip_ffn_flush_all(); +#endif return 0; free_newinfo_untrans: diff -ruw linux-6.4/net/ipv4/tcp.c linux-6.4-fbx/net/ipv4/tcp.c --- linux-6.4/net/ipv4/tcp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/tcp.c 2023-06-27 11:47:16.151869227 +0200 @@ -3599,6 +3599,13 @@ err = -EINVAL; break; + case TCP_LINEAR_RTO: + if (val < 0 || val > 1) + err = -EINVAL; + else + tp->linear_rto = val; + break; + case TCP_REPAIR: if (!tcp_can_repair_sock(sk)) err = -EPERM; @@ -4203,6 +4210,9 @@ case TCP_THIN_DUPACK: val = 0; break; + case TCP_LINEAR_RTO: + val = tp->linear_rto; + break; case TCP_REPAIR: val = tp->repair; diff -ruw linux-6.4/net/ipv4/tcp_offload.c linux-6.4-fbx/net/ipv4/tcp_offload.c --- linux-6.4/net/ipv4/tcp_offload.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/tcp_offload.c 2023-11-07 13:38:44.066256801 +0100 @@ -9,6 +9,7 @@ #include #include #include +#include #include #include diff -ruw linux-6.4/net/ipv4/tcp_timer.c linux-6.4-fbx/net/ipv4/tcp_timer.c --- linux-6.4/net/ipv4/tcp_timer.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/tcp_timer.c 2023-06-27 11:47:16.151869227 +0200 @@ -587,6 +587,10 @@ icsk->icsk_retransmits <= TCP_THIN_LINEAR_RETRIES) { icsk->icsk_backoff = 0; icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); + + } else if (sk->sk_state == TCP_ESTABLISHED && tp->linear_rto) { + icsk->icsk_backoff = 0; + icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); } else { /* Use normal (exponential) backoff */ icsk->icsk_rto = min(icsk->icsk_rto << 1, TCP_RTO_MAX); diff -ruw linux-6.4/net/ipv4/udp.c linux-6.4-fbx/net/ipv4/udp.c --- linux-6.4/net/ipv4/udp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/udp.c 2023-11-07 13:38:44.066256801 +0100 @@ -103,6 +103,7 @@ #include #include #include +#include #include #include #include @@ -315,6 +316,49 @@ inet_sk(sk)->inet_num = snum; udp_sk(sk)->udp_port_hash = snum; udp_sk(sk)->udp_portaddr_hash ^= snum; + + /* resolve udp reuse conflict */ + if (sk->sk_reuse) { + struct sock *sk2; + bool found; + + found = false; + sk_for_each(sk2, &hslot->head) { + if (!net_eq(sock_net(sk2), net) || + sk2 == sk || + (udp_sk(sk2)->udp_port_hash != snum)) + continue; + + if (sk2->sk_bound_dev_if && + sk->sk_bound_dev_if && + sk2->sk_bound_dev_if != sk->sk_bound_dev_if) + continue; + + if (!inet_rcv_saddr_equal(sk, sk2, true)) + continue; + + found = true; + break; + } + + sk_for_each(sk2, &hslot->head) { + if (!net_eq(sock_net(sk2), net) || + sk2 == sk || + (udp_sk(sk2)->udp_port_hash != snum)) + continue; + + if (sk2->sk_bound_dev_if && + sk->sk_bound_dev_if && + sk2->sk_bound_dev_if != sk->sk_bound_dev_if) + continue; + + if (!inet_rcv_saddr_equal(sk, sk2, true)) + continue; + + sk->sk_reuse_conflict = found; + } + } + if (sk_unhashed(sk)) { if (sk->sk_reuseport && udp_reuseport_add_sock(sk, hslot)) { @@ -2342,6 +2386,90 @@ return 0; } +/* + * Unicast goes to one listener and all sockets with dup flag + * + * Note: called only from the BH handler context. + * + * Note2: it is okay to use the udp_table.hash table only here + * and not udp_table.hash2 table as the sock is always hashed in + * both udp_table.hash and udp_table.hash2. This might impact + * performance if the sock hash bucket hosts more than 10 socks + * but has the benefit of keeping the code simplier. + * + * Note3: __udp_is_mcast_sock() does not have really anything to + * do with multicast, it used there to deliver the packet only to + * the sockets that are bound to the ip:port/interface the skbuff + * is targeted to. + */ +static int __udp4_lib_uc_conflict_deliver(struct net *net, struct sk_buff *skb, + struct udphdr *uh, + __be32 saddr, __be32 daddr, + struct udp_table *udptable, + int proto) +{ + struct sock *sk, *first = NULL; + unsigned short hnum = ntohs(uh->dest); + struct udp_hslot *hslot = udp_hashslot(udptable, net, hnum); + int dif = skb->dev->ifindex; + unsigned int offset = offsetof(typeof(*sk), sk_node); + struct hlist_node *node; + struct sk_buff *nskb; + int sdif = inet_sdif(skb); + bool found_non_dup; + + found_non_dup = false; + sk_for_each_entry_offset_rcu(sk, node, &hslot->head, offset) { + bool need_deliver; + + if (!__udp_is_mcast_sock(net, sk, uh->dest, daddr, + uh->source, saddr, dif, sdif, hnum)) + continue; + + if (sock_flag(sk, SOCK_UDP_DUP_UNICAST)) + need_deliver = true; + else { + if (!found_non_dup) + need_deliver = true; + else + need_deliver = false; + found_non_dup = true; + } + + if (!need_deliver) + continue; + + if (!first) { + first = sk; + continue; + } + nskb = skb_clone(skb, GFP_ATOMIC); + + if (unlikely(!nskb)) { + atomic_inc(&sk->sk_drops); + __UDP_INC_STATS(net, UDP_MIB_RCVBUFERRORS, + IS_UDPLITE(sk)); + __UDP_INC_STATS(net, UDP_MIB_INERRORS, + IS_UDPLITE(sk)); + continue; + } + + if (udp_queue_rcv_skb(sk, nskb) > 0) + consume_skb(nskb); + } + + if (first) { + if (udp_queue_rcv_skb(first, skb) > 0) + consume_skb(skb); + } else { + kfree_skb(skb); + __UDP_INC_STATS(net, UDP_MIB_IGNOREDMULTI, + proto == IPPROTO_UDPLITE); + } + + return 0; +} + /* Initialize UDP checksum. If exited with zero value (success), * CHECKSUM_UNNECESSARY means, that no more checks are required. * Otherwise, csum completion requires checksumming packet body, @@ -2471,9 +2599,15 @@ saddr, daddr, udptable, proto); sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable); - if (sk) - return udp_unicast_rcv_skb(sk, skb, uh); + if (sk) { + if (sk->sk_reuse_conflict) + return __udp4_lib_uc_conflict_deliver(net, + skb, uh, + saddr, daddr, + udptable, proto); + return udp_unicast_rcv_skb(sk, skb, uh); + } if (!xfrm4_policy_check(NULL, XFRM_POLICY_IN, skb)) goto drop; nf_reset_ct(skb); diff -ruw linux-6.4/net/ipv4/udp_offload.c linux-6.4-fbx/net/ipv4/udp_offload.c --- linux-6.4/net/ipv4/udp_offload.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv4/udp_offload.c 2023-11-07 13:38:44.066256801 +0100 @@ -8,6 +8,7 @@ #include #include +#include #include #include #include diff -ruw linux-6.4/net/ipv6/Makefile linux-6.4-fbx/net/ipv6/Makefile --- linux-6.4/net/ipv6/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/Makefile 2023-05-22 20:06:45.487886891 +0200 @@ -13,6 +13,7 @@ udp_offload.o seg6.o fib6_notifier.o rpl.o ioam6.o ipv6-$(CONFIG_SYSCTL) += sysctl_net_ipv6.o +ipv6-$(CONFIG_IPV6_FFN) += ip6_ffn.o ipv6-$(CONFIG_IPV6_MROUTE) += ip6mr.o ipv6-$(CONFIG_XFRM) += xfrm6_policy.o xfrm6_state.o xfrm6_input.o \ diff -ruw linux-6.4/net/ipv6/addrconf.c linux-6.4-fbx/net/ipv6/addrconf.c --- linux-6.4/net/ipv6/addrconf.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/addrconf.c 2023-05-22 20:06:45.495887104 +0200 @@ -2310,12 +2310,27 @@ return 0; } +static int addrconf_ifid_ppp(u8 *eui, struct net_device *dev) +{ + if (is_zero_ether_addr(dev->perm_addr)) + return -1; + + memcpy(eui, dev->perm_addr, 3); + memcpy(eui + 5, dev->perm_addr + 3, 3); + eui[3] = 0xFF; + eui[4] = 0xFE; + eui[0] ^= 2; + return 0; +} + static int ipv6_generate_eui64(u8 *eui, struct net_device *dev) { switch (dev->type) { case ARPHRD_ETHER: case ARPHRD_FDDI: return addrconf_ifid_eui48(eui, dev); + case ARPHRD_PPP: + return addrconf_ifid_ppp(eui, dev); case ARPHRD_ARCNET: return addrconf_ifid_arcnet(eui, dev); case ARPHRD_INFINIBAND: @@ -3363,6 +3378,7 @@ if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_FDDI) && + (dev->type != ARPHRD_PPP) && (dev->type != ARPHRD_ARCNET) && (dev->type != ARPHRD_INFINIBAND) && (dev->type != ARPHRD_IEEE1394) && diff -ruw linux-6.4/net/ipv6/af_inet6.c linux-6.4-fbx/net/ipv6/af_inet6.c --- linux-6.4/net/ipv6/af_inet6.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/af_inet6.c 2023-05-22 20:06:45.499887210 +0200 @@ -1180,6 +1180,10 @@ if (err) goto udpv6_fail; +#ifdef CONFIG_IPV6_FFN + ipv6_ffn_init(); +#endif + err = udplitev6_init(); if (err) goto udplitev6_fail; diff -ruw linux-6.4/net/ipv6/esp6_offload.c linux-6.4-fbx/net/ipv6/esp6_offload.c --- linux-6.4/net/ipv6/esp6_offload.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/esp6_offload.c 2023-11-07 13:38:44.070256910 +0100 @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff -ruw linux-6.4/net/ipv6/ip6_input.c linux-6.4-fbx/net/ipv6/ip6_input.c --- linux-6.4/net/ipv6/ip6_input.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/ip6_input.c 2023-05-22 20:06:45.511887529 +0200 @@ -306,6 +306,12 @@ skb = ip6_rcv_core(skb, dev, net); if (skb == NULL) return NET_RX_DROP; + +#ifdef CONFIG_IPV6_FFN + if (!ipv6_ffn_process(skb)) + return NET_RX_SUCCESS; +#endif + return NF_HOOK(NFPROTO_IPV6, NF_INET_PRE_ROUTING, net, NULL, skb, dev, NULL, ip6_rcv_finish); @@ -475,8 +481,13 @@ kfree_skb_reason(skb, reason); } -static int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb) +int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { +#ifdef CONFIG_IPV6_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ipv6_ffn_add(skb, IPV6_FFN_LOCAL_IN); +#endif + skb_clear_delivery_time(skb); rcu_read_lock(); ip6_protocol_deliver_rcu(net, skb, 0, false); diff -ruw linux-6.4/net/ipv6/ip6_offload.c linux-6.4-fbx/net/ipv6/ip6_offload.c --- linux-6.4/net/ipv6/ip6_offload.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/ip6_offload.c 2023-11-07 13:38:44.070256910 +0100 @@ -16,6 +16,7 @@ #include #include #include +#include #include "ip6_offload.h" diff -ruw linux-6.4/net/ipv6/ip6_output.c linux-6.4-fbx/net/ipv6/ip6_output.c --- linux-6.4/net/ipv6/ip6_output.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/ip6_output.c 2023-11-07 13:38:44.070256910 +0100 @@ -42,6 +42,7 @@ #include #include +#include #include #include #include @@ -51,6 +52,7 @@ #include #include #include +#include #include #include #include @@ -116,6 +118,11 @@ return res; } +#ifdef CONFIG_IPV6_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ipv6_ffn_add(skb, IPV6_FFN_FINISH_OUT); +#endif + rcu_read_lock(); nexthop = rt6_nexthop((struct rt6_info *)dst, daddr); neigh = __ipv6_neigh_lookup_noref(dev, nexthop); @@ -224,6 +231,11 @@ return 0; } +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FAST_FORWARDED) + return ip6_finish_output(net, sk, skb); +#endif + return NF_HOOK_COND(NFPROTO_IPV6, NF_INET_POST_ROUTING, net, sk, skb, indev, dev, ip6_finish_output, @@ -646,6 +658,8 @@ hdr->hop_limit--; + skb->priority = rt_tos2priority(ipv6_get_dsfield(hdr)); + return NF_HOOK(NFPROTO_IPV6, NF_INET_FORWARD, net, NULL, skb, skb->dev, dst->dev, ip6_forward_finish); diff -ruw linux-6.4/net/ipv6/ip6_tunnel.c linux-6.4-fbx/net/ipv6/ip6_tunnel.c --- linux-6.4/net/ipv6/ip6_tunnel.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/ip6_tunnel.c 2023-05-22 20:06:45.515887636 +0200 @@ -67,9 +67,9 @@ module_param(log_ecn_error, bool, 0644); MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); -static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) +static u32 HASH(const struct in6_addr *addr) { - u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); + u32 hash = ipv6_addr_hash(addr); return hash_32(hash, IP6_TUNNEL_HASH_SIZE_SHIFT); } @@ -114,17 +114,26 @@ ip6_tnl_lookup(struct net *net, int link, const struct in6_addr *remote, const struct in6_addr *local) { - unsigned int hash = HASH(remote, local); + unsigned int hash = HASH(local); struct ip6_tnl *t, *cand = NULL; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); struct in6_addr any; + struct __ip6_tnl_fmr *fmr; for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { if (!ipv6_addr_equal(local, &t->parms.laddr) || - !ipv6_addr_equal(remote, &t->parms.raddr) || !(t->dev->flags & IFF_UP)) continue; + if (!ipv6_addr_equal(remote, &t->parms.raddr)) { + for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { + if (ipv6_prefix_equal(remote, &fmr->ip6_prefix, + fmr->ip6_prefix_len)) + return t; + } + continue ; + } + if (link == t->parms.link) return t; else @@ -132,7 +141,7 @@ } memset(&any, 0, sizeof(any)); - hash = HASH(&any, local); + hash = HASH(local); for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { if (!ipv6_addr_equal(local, &t->parms.laddr) || !ipv6_addr_any(&t->parms.raddr) || @@ -145,7 +154,7 @@ cand = t; } - hash = HASH(remote, &any); + hash = HASH(&any); for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { if (!ipv6_addr_equal(remote, &t->parms.raddr) || !ipv6_addr_any(&t->parms.laddr) || @@ -194,7 +203,7 @@ if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { prio = 1; - h = HASH(remote, local); + h = HASH(local); } return &ip6n->tnls[prio][h]; } @@ -376,6 +385,12 @@ struct net *net = t->net; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + while (t->parms.fmrs) { + struct __ip6_tnl_fmr *next = t->parms.fmrs->next; + kfree(t->parms.fmrs); + t->parms.fmrs = next; + } + if (dev == ip6n->fb_tnl_dev) RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); else @@ -788,6 +803,107 @@ } EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); +/** + * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR + * @dest: destination IPv6 address buffer + * @skb: received socket buffer + * @fmr: MAP FMR + * @xmit: Calculate for xmit or rcv + **/ +static void ip4ip6_fmr_calc(struct in6_addr *dest, + const struct iphdr *iph, const uint8_t *end, + const struct __ip6_tnl_fmr *fmr, bool xmit) +{ + int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); + u8 *portp = NULL; + bool use_dest_addr; + const struct iphdr *dsth = iph; + + if ((u8*)dsth >= end) + return; + + /* find significant IP header */ + if (iph->protocol == IPPROTO_ICMP) { + struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); + if (ih && ((u8*)&ih[1]) <= end && ( + ih->type == ICMP_DEST_UNREACH || + ih->type == ICMP_SOURCE_QUENCH || + ih->type == ICMP_TIME_EXCEEDED || + ih->type == ICMP_PARAMETERPROB || + ih->type == ICMP_REDIRECT)) + dsth = (const struct iphdr*)&ih[1]; + } + + /* in xmit-path use dest port by default and source port only if + this is an ICMP reply to something else; vice versa in rcv-path */ + use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); + + /* get dst port */ + if (((u8*)&dsth[1]) <= end && ( + dsth->protocol == IPPROTO_UDP || + dsth->protocol == IPPROTO_TCP || + dsth->protocol == IPPROTO_SCTP || + dsth->protocol == IPPROTO_DCCP)) { + /* for UDP, TCP, SCTP and DCCP source and dest port + follow IPv4 header directly */ + portp = ((u8*)dsth) + dsth->ihl * 4; + + if (use_dest_addr) + portp += sizeof(u16); + } else if (iph->protocol == IPPROTO_ICMP) { + struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); + + /* use icmp identifier as port */ + if (((u8*)&ih) <= end && ( + (use_dest_addr && ( + ih->type == ICMP_ECHOREPLY || + ih->type == ICMP_TIMESTAMPREPLY || + ih->type == ICMP_INFO_REPLY || + ih->type == ICMP_ADDRESSREPLY)) || + (!use_dest_addr && ( + ih->type == ICMP_ECHO || + ih->type == ICMP_TIMESTAMP || + ih->type == ICMP_INFO_REQUEST || + ih->type == ICMP_ADDRESS) + ))) + portp = (u8*)&ih->un.echo.id; + } + + if ((portp && &portp[2] <= end) || psidlen == 0) { + int frombyte = fmr->ip6_prefix_len / 8; + int fromrem = fmr->ip6_prefix_len % 8; + int bytes = sizeof(struct in6_addr) - frombyte; + const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; + u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); + u64 t = 0; + + /* extract PSID from port and add it to eabits */ + u16 psidbits = 0; + if (psidlen > 0) { + psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); + psidbits >>= 16 - psidlen - fmr->offset; + psidbits = (u16)(psidbits << (16 - psidlen)); + eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); + } + + /* rewrite destination address */ + *dest = fmr->ip6_prefix; + memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); + dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); + + if (bytes > sizeof(u64)) + bytes = sizeof(u64); + + /* insert eabits */ + memcpy(&t, &dest->s6_addr[frombyte], bytes); + t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) + << (64 - fmr->ea_len - fromrem)); + t = cpu_to_be64(t | (eabits >> fromrem)); + memcpy(&dest->s6_addr[frombyte], &t, bytes); + } +} + + static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb, const struct tnl_ptk_info *tpi, struct metadata_dst *tun_dst, @@ -840,6 +956,27 @@ skb_reset_network_header(skb); memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); + if (tpi->proto == htons(ETH_P_IP) && + !ipv6_addr_equal(&ipv6h->saddr, &tunnel->parms.raddr)) { + /* Packet didn't come from BR, so lookup FMR */ + struct __ip6_tnl_fmr *fmr; + struct in6_addr expected = tunnel->parms.raddr; + for (fmr = tunnel->parms.fmrs; fmr; fmr = fmr->next) + if (ipv6_prefix_equal(&ipv6h->saddr, + &fmr->ip6_prefix, fmr->ip6_prefix_len)) + break; + + /* Check that IPv6 matches IPv4 source to prevent spoofing */ + if (fmr) + ip4ip6_fmr_calc(&expected, ip_hdr(skb), + skb_tail_pointer(skb), fmr, false); + + if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { + rcu_read_unlock(); + goto drop; + } + } + __skb_tunnel_rx(skb, tunnel->dev, tunnel->net); err = dscp_ecn_decapsulate(tunnel, ipv6h, skb); @@ -987,6 +1124,7 @@ opt->ops.opt_nflen = 8; } + /** * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own * @t: the outgoing tunnel device @@ -1281,6 +1419,7 @@ const struct iphdr *iph; int encap_limit = -1; __u16 offset; + struct __ip6_tnl_fmr *fmr; struct flowi6 fl6; __u8 dsfield, orig_dsfield; __u32 mtu; @@ -1376,6 +1515,18 @@ fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL); dsfield = INET_ECN_encapsulate(dsfield, orig_dsfield); + /* try to find matching FMR */ + for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { + unsigned mshift = 32 - fmr->ip4_prefix_len; + if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == + ntohl(ip_hdr(skb)->daddr) >> mshift) + break; + } + + /* change dstaddr according to FMR */ + if (fmr) + ip4ip6_fmr_calc(&fl6.daddr, ip_hdr(skb), skb_tail_pointer(skb), fmr, true); + if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6)) return -1; @@ -1528,6 +1679,14 @@ t->parms.link = p->link; t->parms.proto = p->proto; t->parms.fwmark = p->fwmark; + + while (t->parms.fmrs) { + struct __ip6_tnl_fmr *next = t->parms.fmrs->next; + kfree(t->parms.fmrs); + t->parms.fmrs = next; + } + t->parms.fmrs = p->fmrs; + dst_cache_reset(&t->dst_cache); ip6_tnl_link_config(t); } @@ -1562,6 +1721,7 @@ p->flowinfo = u->flowinfo; p->link = u->link; p->proto = u->proto; + p->fmrs = NULL; memcpy(p->name, u->name, sizeof(u->name)); } @@ -1948,13 +2108,22 @@ return 0; } -static void ip6_tnl_netlink_parms(struct nlattr *data[], +static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { + [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, + [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, + [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } +}; + +static int ip6_tnl_netlink_parms(struct nlattr *data[], struct __ip6_tnl_parm *parms) { memset(parms, 0, sizeof(*parms)); if (!data) - return; + return 0; if (data[IFLA_IPTUN_LINK]) parms->link = nla_get_u32(data[IFLA_IPTUN_LINK]); @@ -1985,6 +2154,52 @@ if (data[IFLA_IPTUN_FWMARK]) parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]); + + if (data[IFLA_IPTUN_FMRS]) { + unsigned rem; + struct nlattr *fmr; + + nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { + struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; + struct __ip6_tnl_fmr *nfmr; + int err; + + err = nla_parse_nested_deprecated(fmrd, IFLA_IPTUN_FMR_MAX, + fmr, ip6_tnl_fmr_policy, NULL); + if (err) + return err; + + if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) + return -ENOMEM; + + nfmr->offset = 6; + + if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) + nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], + sizeof(nfmr->ip6_prefix)); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) + nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], + sizeof(nfmr->ip4_prefix)); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) + nfmr->ip6_prefix_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) + nfmr->ip4_prefix_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) + nfmr->ea_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) + nfmr->offset = nla_get_u8(c); + + nfmr->next = parms->fmrs; + parms->fmrs = nfmr; + } + } + + return 0; } static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev, @@ -2005,7 +2220,9 @@ return err; } - ip6_tnl_netlink_parms(data, &nt->parms); + err = ip6_tnl_netlink_parms(data, &nt->parms); + if (err) + return err; if (nt->parms.collect_md) { if (rtnl_dereference(ip6n->collect_md_tun)) @@ -2032,6 +2249,7 @@ struct net *net = t->net; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); struct ip_tunnel_encap ipencap; + int err; if (dev == ip6n->fb_tnl_dev) return -EINVAL; @@ -2042,7 +2260,10 @@ if (err < 0) return err; } - ip6_tnl_netlink_parms(data, &p); + err = ip6_tnl_netlink_parms(data, &p); + if (err) + return err; + if (p.collect_md) return -EINVAL; @@ -2068,6 +2289,12 @@ static size_t ip6_tnl_get_size(const struct net_device *dev) { + const struct ip6_tnl *t = netdev_priv(dev); + struct __ip6_tnl_fmr *c; + int fmrs = 0; + for (c = t->parms.fmrs; c; c = c->next) + ++fmrs; + return /* IFLA_IPTUN_LINK */ nla_total_size(4) + @@ -2097,6 +2324,24 @@ nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + + /* IFLA_IPTUN_FMRS */ + nla_total_size(0) + + ( + /* nest */ + nla_total_size(0) + + /* IFLA_IPTUN_FMR_IP6_PREFIX */ + nla_total_size(sizeof(struct in6_addr)) + + /* IFLA_IPTUN_FMR_IP4_PREFIX */ + nla_total_size(sizeof(struct in_addr)) + + /* IFLA_IPTUN_FMR_EA_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_OFFSET */ + nla_total_size(1) + ) * fmrs + 0; } @@ -2104,6 +2349,9 @@ { struct ip6_tnl *tunnel = netdev_priv(dev); struct __ip6_tnl_parm *parm = &tunnel->parms; + struct __ip6_tnl_fmr *c; + int fmrcnt = 0; + struct nlattr *fmrs; if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || @@ -2113,9 +2361,27 @@ nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || - nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark)) + nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark) || + !(fmrs = nla_nest_start_noflag(skb, IFLA_IPTUN_FMRS))) goto nla_put_failure; + for (c = parm->fmrs; c; c = c->next) { + struct nlattr *fmr = nla_nest_start_noflag(skb, ++fmrcnt); + if (!fmr || + nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, + sizeof(c->ip6_prefix), &c->ip6_prefix) || + nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, + sizeof(c->ip4_prefix), &c->ip4_prefix) || + nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) + goto nla_put_failure; + + nla_nest_end(skb, fmr); + } + nla_nest_end(skb, fmrs); + if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || @@ -2155,6 +2421,7 @@ [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, + [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, }; static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff -ruw linux-6.4/net/ipv6/netfilter/Kconfig linux-6.4-fbx/net/ipv6/netfilter/Kconfig --- linux-6.4/net/ipv6/netfilter/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/netfilter/Kconfig 2023-05-22 20:06:45.515887636 +0200 @@ -6,6 +6,13 @@ menu "IPv6: Netfilter Configuration" depends on INET && IPV6 && NETFILTER +config IPV6_FFN + bool "IPv6: Fast forwarding and NAT" + +config IPV6_FFN_PROCFS + bool "IPv6: Fast forwarding and NAT /proc/net entries" + depends on IPV6_FFN + config NF_SOCKET_IPV6 tristate "IPv6 socket lookup support" help diff -ruw linux-6.4/net/ipv6/netfilter/ip6_tables.c linux-6.4-fbx/net/ipv6/netfilter/ip6_tables.c --- linux-6.4/net/ipv6/netfilter/ip6_tables.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/netfilter/ip6_tables.c 2023-05-22 20:06:45.519887742 +0200 @@ -1155,6 +1155,10 @@ tmp.num_counters, tmp.counters); if (ret) goto free_newinfo_untrans; + +#ifdef CONFIG_IPV6_FFN + ipv6_ffn_flush_all(); +#endif return 0; free_newinfo_untrans: diff -ruw linux-6.4/net/ipv6/udp.c linux-6.4-fbx/net/ipv6/udp.c --- linux-6.4/net/ipv6/udp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/udp.c 2023-05-22 20:06:45.527887955 +0200 @@ -844,6 +844,82 @@ * Note: called only from the BH handler context, * so we don't need to lock the hashes. */ +static int __udp6_lib_uc_conflict_deliver(struct net *net, struct sk_buff *skb, + const struct in6_addr *saddr, const struct in6_addr *daddr, + struct udp_table *udptable, int proto) +{ + struct sock *sk, *first = NULL; + const struct udphdr *uh = udp_hdr(skb); + unsigned short hnum = ntohs(uh->dest); + struct udp_hslot *hslot = udp_hashslot(udptable, net, hnum); + unsigned int offset = offsetof(typeof(*sk), sk_node); + int dif = inet6_iif(skb); + int sdif = inet6_sdif(skb); + struct hlist_node *node; + struct sk_buff *nskb; + bool found_non_dup; + + found_non_dup = false; + sk_for_each_entry_offset_rcu(sk, node, &hslot->head, offset) { + bool need_deliver; + + if (!__udp_v6_is_mcast_sock(net, sk, uh->dest, daddr, + uh->source, saddr, dif, sdif, hnum)) + + continue; + + /* If zero checksum and no_check is not on for + * the socket then skip it. + */ + if (!uh->check && !udp_sk(sk)->no_check6_rx) + continue; + + if (sock_flag(sk, SOCK_UDP_DUP_UNICAST)) + need_deliver = true; + else { + if (!found_non_dup) + need_deliver = true; + else + need_deliver = false; + found_non_dup = true; + } + + if (!need_deliver) + continue; + + if (!first) { + first = sk; + continue; + } + nskb = skb_clone(skb, GFP_ATOMIC); + if (unlikely(!nskb)) { + atomic_inc(&sk->sk_drops); + __UDP6_INC_STATS(net, UDP_MIB_RCVBUFERRORS, + IS_UDPLITE(sk)); + __UDP6_INC_STATS(net, UDP_MIB_INERRORS, + IS_UDPLITE(sk)); + continue; + } + + if (udpv6_queue_rcv_skb(sk, nskb) > 0) + consume_skb(nskb); + } + + if (first) { + if (udpv6_queue_rcv_skb(first, skb) > 0) + consume_skb(skb); + } else { + kfree_skb(skb); + __UDP6_INC_STATS(net, UDP_MIB_IGNOREDMULTI, + proto == IPPROTO_UDPLITE); + } + return 0; +} + +/* + * Note: called only from the BH handler context, + * so we don't need to lock the hashes. + */ static int __udp6_lib_mcast_deliver(struct net *net, struct sk_buff *skb, const struct in6_addr *saddr, const struct in6_addr *daddr, struct udp_table *udptable, int proto) @@ -1018,6 +1094,12 @@ if (sk) { if (!uh->check && !udp_sk(sk)->no_check6_rx) goto report_csum_error; + + if (sk->sk_reuse_conflict) + return __udp6_lib_uc_conflict_deliver(net, skb, + saddr, daddr, + udptable, proto); + return udp6_unicast_rcv_skb(sk, skb, uh); } diff -ruw linux-6.4/net/ipv6/udp_offload.c linux-6.4-fbx/net/ipv6/udp_offload.c --- linux-6.4/net/ipv6/udp_offload.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/ipv6/udp_offload.c 2023-11-07 13:38:44.070256910 +0100 @@ -14,6 +14,7 @@ #include #include "ip6_offload.h" #include +#include static struct sk_buff *udp6_ufo_fragment(struct sk_buff *skb, netdev_features_t features) diff -ruw linux-6.4/net/mac80211/Kconfig linux-6.4-fbx/net/mac80211/Kconfig --- linux-6.4/net/mac80211/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/Kconfig 2023-12-12 17:24:34.171627426 +0100 @@ -57,6 +57,17 @@ comment "Some wireless drivers require a rate control algorithm" depends on MAC80211 && MAC80211_HAS_RC=n +config MAC80211_KUNIT_TEST + tristate "KUnit tests for mac80211" if !KUNIT_ALL_TESTS + depends on KUNIT + depends on MAC80211 + default KUNIT_ALL_TESTS + depends on !KERNEL_6_2 + help + Enable this option to test mac80211 internals with kunit. + + If unsure, say N. + config MAC80211_MESH bool "Enable mac80211 mesh networking support" depends on MAC80211 @@ -304,3 +315,9 @@ connect more stations than the number selected here.) If unsure, leave the default of 0. + +config FBX80211_SCUM + bool "Same channel unassociated metrics" + depends on FBX80211 + help + Support for unassociated STA metrics diff -ruw linux-6.4/net/mac80211/Makefile linux-6.4-fbx/net/mac80211/Makefile --- linux-6.4/net/mac80211/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/Makefile 2024-04-19 16:04:28.969736104 +0200 @@ -36,7 +36,8 @@ tdls.o \ ocb.o \ airtime.o \ - eht.o + eht.o \ + nmeshd_nl.o mac80211-$(CONFIG_MAC80211_LEDS) += led.o mac80211-$(CONFIG_MAC80211_DEBUGFS) += \ @@ -54,6 +55,7 @@ mesh_ps.o mac80211-$(CONFIG_PM) += pm.o +mac80211-$(CONFIG_FBX80211_SCUM) += fbx_scum.o CFLAGS_trace.o := -I$(src) @@ -65,4 +67,6 @@ mac80211-$(CONFIG_MAC80211_RC_MINSTREL) += $(rc80211_minstrel-y) +obj-y += tests/ + ccflags-y += -DDEBUG diff -ruw linux-6.4/net/mac80211/agg-rx.c linux-6.4-fbx/net/mac80211/agg-rx.c --- linux-6.4/net/mac80211/agg-rx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/agg-rx.c 2023-11-07 13:38:44.070256910 +0100 @@ -9,7 +9,7 @@ * Copyright 2007, Michael Wu * Copyright 2007-2010, Intel Corporation * Copyright(c) 2015-2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation */ /** @@ -55,7 +55,7 @@ kfree(tid_rx); } -void ___ieee80211_stop_rx_ba_session(struct sta_info *sta, u16 tid, +void __ieee80211_stop_rx_ba_session(struct sta_info *sta, u16 tid, u16 initiator, u16 reason, bool tx) { struct ieee80211_local *local = sta->local; @@ -69,10 +69,10 @@ .ssn = 0, }; - lockdep_assert_held(&sta->ampdu_mlme.mtx); + lockdep_assert_wiphy(sta->local->hw.wiphy); tid_rx = rcu_dereference_protected(sta->ampdu_mlme.tid_rx[tid], - lockdep_is_held(&sta->ampdu_mlme.mtx)); + lockdep_is_held(&sta->local->hw.wiphy->mtx)); if (!test_bit(tid, sta->ampdu_mlme.agg_session_valid)) return; @@ -114,14 +114,6 @@ call_rcu(&tid_rx->rcu_head, ieee80211_free_tid_rx); } -void __ieee80211_stop_rx_ba_session(struct sta_info *sta, u16 tid, - u16 initiator, u16 reason, bool tx) -{ - mutex_lock(&sta->ampdu_mlme.mtx); - ___ieee80211_stop_rx_ba_session(sta, tid, initiator, reason, tx); - mutex_unlock(&sta->ampdu_mlme.mtx); -} - void ieee80211_stop_rx_ba_session(struct ieee80211_vif *vif, u16 ba_rx_bitmap, const u8 *addr) { @@ -140,7 +132,7 @@ if (ba_rx_bitmap & BIT(i)) set_bit(i, sta->ampdu_mlme.tid_rx_stop_requested); - ieee80211_queue_work(&sta->local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(sta->local->hw.wiphy, &sta->ampdu_mlme.work); rcu_read_unlock(); } EXPORT_SYMBOL(ieee80211_stop_rx_ba_session); @@ -166,7 +158,7 @@ sta->sta.addr, tid); set_bit(tid, sta->ampdu_mlme.tid_rx_timer_expired); - ieee80211_queue_work(&sta->local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(sta->local->hw.wiphy, &sta->ampdu_mlme.work); } static void sta_rx_agg_reorder_timer_expired(struct timer_list *t) @@ -250,7 +242,7 @@ ieee80211_tx_skb(sdata, skb); } -void ___ieee80211_start_rx_ba_session(struct sta_info *sta, +void __ieee80211_start_rx_ba_session(struct sta_info *sta, u8 dialog_token, u16 timeout, u16 start_seq_num, u16 ba_policy, u16 tid, u16 buf_size, bool tx, bool auto_seq, @@ -270,6 +262,8 @@ u16 status = WLAN_STATUS_REQUEST_DECLINED; u16 max_buf_size; + lockdep_assert_wiphy(sta->local->hw.wiphy); + if (tid >= IEEE80211_FIRST_TSPEC_TSID) { ht_dbg(sta->sdata, "STA %pM requests BA session on unsupported tid %d\n", @@ -325,9 +319,6 @@ ht_dbg(sta->sdata, "AddBA Req buf_size=%d for %pM\n", buf_size, sta->sta.addr); - /* examine state machine */ - lockdep_assert_held(&sta->ampdu_mlme.mtx); - if (test_bit(tid, sta->ampdu_mlme.agg_session_valid)) { if (sta->ampdu_mlme.tid_rx_token[tid] == dialog_token) { struct tid_ampdu_rx *tid_rx; @@ -355,7 +346,7 @@ sta->sta.addr, tid); /* delete existing Rx BA session on the same tid */ - ___ieee80211_stop_rx_ba_session(sta, tid, WLAN_BACK_RECIPIENT, + __ieee80211_stop_rx_ba_session(sta, tid, WLAN_BACK_RECIPIENT, WLAN_STATUS_UNSPECIFIED_QOS, false); } @@ -444,20 +435,6 @@ timeout, addbaext); } -static void __ieee80211_start_rx_ba_session(struct sta_info *sta, - u8 dialog_token, u16 timeout, - u16 start_seq_num, u16 ba_policy, - u16 tid, u16 buf_size, bool tx, - bool auto_seq, - const struct ieee80211_addba_ext_ie *addbaext) -{ - mutex_lock(&sta->ampdu_mlme.mtx); - ___ieee80211_start_rx_ba_session(sta, dialog_token, timeout, - start_seq_num, ba_policy, tid, - buf_size, tx, auto_seq, addbaext); - mutex_unlock(&sta->ampdu_mlme.mtx); -} - void ieee80211_process_addba_request(struct ieee80211_local *local, struct sta_info *sta, struct ieee80211_mgmt *mgmt, @@ -507,7 +484,6 @@ const u8 *addr, unsigned int tid) { struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); - struct ieee80211_local *local = sdata->local; struct sta_info *sta; rcu_read_lock(); @@ -516,7 +492,7 @@ goto unlock; set_bit(tid, sta->ampdu_mlme.tid_rx_manage_offl); - ieee80211_queue_work(&local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(sta->local->hw.wiphy, &sta->ampdu_mlme.work); unlock: rcu_read_unlock(); } @@ -526,7 +502,6 @@ const u8 *addr, unsigned int tid) { struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); - struct ieee80211_local *local = sdata->local; struct sta_info *sta; rcu_read_lock(); @@ -535,7 +510,7 @@ goto unlock; set_bit(tid, sta->ampdu_mlme.tid_rx_timer_expired); - ieee80211_queue_work(&local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(sta->local->hw.wiphy, &sta->ampdu_mlme.work); unlock: rcu_read_unlock(); diff -ruw linux-6.4/net/mac80211/agg-tx.c linux-6.4-fbx/net/mac80211/agg-tx.c --- linux-6.4/net/mac80211/agg-tx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/agg-tx.c 2023-11-07 13:38:44.070256910 +0100 @@ -9,7 +9,7 @@ * Copyright 2007, Michael Wu * Copyright 2007-2010, Intel Corporation * Copyright(c) 2015-2017 Intel Deutschland GmbH - * Copyright (C) 2018 - 2022 Intel Corporation + * Copyright (C) 2018 - 2023 Intel Corporation */ #include @@ -139,10 +139,18 @@ } EXPORT_SYMBOL(ieee80211_send_bar); +void ieee80211_send_bar_sta(struct ieee80211_sta *pubsta, + u16 tid, u16 ssn) +{ + struct sta_info *sta = container_of(pubsta, struct sta_info, sta); + ieee80211_send_bar(&sta->sdata->vif, pubsta->addr, tid, ssn); +} +EXPORT_SYMBOL(ieee80211_send_bar_sta); + void ieee80211_assign_tid_tx(struct sta_info *sta, int tid, struct tid_ampdu_tx *tid_tx) { - lockdep_assert_held(&sta->ampdu_mlme.mtx); + lockdep_assert_wiphy(sta->local->hw.wiphy); lockdep_assert_held(&sta->lock); rcu_assign_pointer(sta->ampdu_mlme.tid_tx[tid], tid_tx); } @@ -213,7 +221,7 @@ struct ieee80211_txq *txq = sta->sta.txq[tid]; struct txq_info *txqi; - lockdep_assert_held(&sta->ampdu_mlme.mtx); + lockdep_assert_wiphy(sta->local->hw.wiphy); if (!txq) return; @@ -271,7 +279,7 @@ { struct tid_ampdu_tx *tid_tx; - lockdep_assert_held(&sta->ampdu_mlme.mtx); + lockdep_assert_wiphy(sta->local->hw.wiphy); lockdep_assert_held(&sta->lock); tid_tx = rcu_dereference_protected_tid_tx(sta, tid); @@ -296,7 +304,7 @@ kfree_rcu(tid_tx, rcu_head); } -int ___ieee80211_stop_tx_ba_session(struct sta_info *sta, u16 tid, +int __ieee80211_stop_tx_ba_session(struct sta_info *sta, u16 tid, enum ieee80211_agg_stop_reason reason) { struct ieee80211_local *local = sta->local; @@ -311,7 +319,7 @@ }; int ret; - lockdep_assert_held(&sta->ampdu_mlme.mtx); + lockdep_assert_wiphy(sta->local->hw.wiphy); switch (reason) { case AGG_STOP_DECLINED: @@ -457,6 +465,12 @@ u8 tid = tid_tx->tid; u16 buf_size; + if (WARN_ON_ONCE(test_bit(HT_AGG_STATE_STOPPING, &tid_tx->state) || + test_bit(HT_AGG_STATE_WANT_STOP, &tid_tx->state))) + return; + + lockdep_assert_wiphy(sta->local->hw.wiphy); + /* activate the timer for the recipient's addBA response */ mod_timer(&tid_tx->addba_resp_timer, jiffies + ADDBA_RESP_INTERVAL); ht_dbg(sdata, "activated addBA response timer on %pM tid %d\n", @@ -491,7 +505,7 @@ { struct tid_ampdu_tx *tid_tx; struct ieee80211_local *local = sta->local; - struct ieee80211_sub_if_data *sdata; + struct ieee80211_sub_if_data *sdata = sta->sdata; struct ieee80211_ampdu_params params = { .sta = &sta->sta, .action = IEEE80211_AMPDU_TX_START, @@ -519,7 +533,6 @@ */ synchronize_net(); - sdata = sta->sdata; params.ssn = sta->tid_seq[tid] >> 4; ret = drv_ampdu_action(local, sdata, ¶ms); tid_tx->ssn = params.ssn; @@ -533,9 +546,6 @@ */ set_bit(HT_AGG_STATE_DRV_READY, &tid_tx->state); } else if (ret) { - if (!sdata) - return; - ht_dbg(sdata, "BA request denied - HW unavailable for %pM tid %d\n", sta->sta.addr, tid); @@ -737,7 +747,7 @@ */ sta->ampdu_mlme.tid_start_tx[tid] = tid_tx; - ieee80211_queue_work(&local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(local->hw.wiphy, &sta->ampdu_mlme.work); /* this flow continues off the work */ err_unlock_sta: @@ -758,7 +768,7 @@ .ssn = 0, }; - lockdep_assert_held(&sta->ampdu_mlme.mtx); + lockdep_assert_wiphy(sta->local->hw.wiphy); tid_tx = rcu_dereference_protected_tid_tx(sta, tid); params.buf_size = tid_tx->buf_size; @@ -795,9 +805,15 @@ struct ieee80211_sub_if_data *sdata = sta->sdata; struct ieee80211_local *local = sdata->local; + lockdep_assert_wiphy(sta->local->hw.wiphy); + if (WARN_ON(test_and_set_bit(HT_AGG_STATE_DRV_READY, &tid_tx->state))) return; + if (test_bit(HT_AGG_STATE_STOPPING, &tid_tx->state) || + test_bit(HT_AGG_STATE_WANT_STOP, &tid_tx->state)) + return; + if (!test_bit(HT_AGG_STATE_SENT_ADDBA, &tid_tx->state)) { ieee80211_send_addba_with_timeout(sta, tid_tx); /* RESPONSE_RECEIVED state whould trigger the flow again */ @@ -850,26 +866,12 @@ goto out; set_bit(HT_AGG_STATE_START_CB, &tid_tx->state); - ieee80211_queue_work(&local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(local->hw.wiphy, &sta->ampdu_mlme.work); out: rcu_read_unlock(); } EXPORT_SYMBOL(ieee80211_start_tx_ba_cb_irqsafe); -int __ieee80211_stop_tx_ba_session(struct sta_info *sta, u16 tid, - enum ieee80211_agg_stop_reason reason) -{ - int ret; - - mutex_lock(&sta->ampdu_mlme.mtx); - - ret = ___ieee80211_stop_tx_ba_session(sta, tid, reason); - - mutex_unlock(&sta->ampdu_mlme.mtx); - - return ret; -} - int ieee80211_stop_tx_ba_session(struct ieee80211_sta *pubsta, u16 tid) { struct sta_info *sta = container_of(pubsta, struct sta_info, sta); @@ -904,7 +906,7 @@ } set_bit(HT_AGG_STATE_WANT_STOP, &tid_tx->state); - ieee80211_queue_work(&local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(local->hw.wiphy, &sta->ampdu_mlme.work); unlock: spin_unlock_bh(&sta->lock); @@ -964,7 +966,7 @@ goto out; set_bit(HT_AGG_STATE_STOP_CB, &tid_tx->state); - ieee80211_queue_work(&local->hw, &sta->ampdu_mlme.work); + wiphy_work_queue(local->hw.wiphy, &sta->ampdu_mlme.work); out: rcu_read_unlock(); } @@ -981,6 +983,8 @@ u16 capab, tid, buf_size; bool amsdu; + lockdep_assert_wiphy(sta->local->hw.wiphy); + capab = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); amsdu = capab & IEEE80211_ADDBA_PARAM_AMSDU_MASK; tid = u16_get_bits(capab, IEEE80211_ADDBA_PARAM_TID_MASK); @@ -991,16 +995,14 @@ if (!amsdu && txq) set_bit(IEEE80211_TXQ_NO_AMSDU, &to_txq_info(txq)->flags); - mutex_lock(&sta->ampdu_mlme.mtx); - tid_tx = rcu_dereference_protected_tid_tx(sta, tid); if (!tid_tx) - goto out; + return; if (mgmt->u.action.u.addba_resp.dialog_token != tid_tx->dialog_token) { ht_dbg(sta->sdata, "wrong addBA response token, %pM tid %d\n", sta->sta.addr, tid); - goto out; + return; } del_timer_sync(&tid_tx->addba_resp_timer); @@ -1018,7 +1020,7 @@ ht_dbg(sta->sdata, "got addBA resp for %pM tid %d but we already gave up\n", sta->sta.addr, tid); - goto out; + return; } /* @@ -1032,7 +1034,7 @@ if (test_and_set_bit(HT_AGG_STATE_RESPONSE_RECEIVED, &tid_tx->state)) { /* ignore duplicate response */ - goto out; + return; } tid_tx->buf_size = buf_size; @@ -1053,9 +1055,6 @@ } } else { - ___ieee80211_stop_tx_ba_session(sta, tid, AGG_STOP_DECLINED); + __ieee80211_stop_tx_ba_session(sta, tid, AGG_STOP_DECLINED); } - - out: - mutex_unlock(&sta->ampdu_mlme.mtx); } diff -ruw linux-6.4/net/mac80211/airtime.c linux-6.4-fbx/net/mac80211/airtime.c --- linux-6.4/net/mac80211/airtime.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/airtime.c 2023-11-07 13:38:44.070256910 +0100 @@ -557,7 +557,7 @@ if (ieee80211_fill_rate_info(hw, stat, band, ri)) return 0; - if (rate->idx < 0 || !rate->count) + if (!ieee80211_rate_valid(rate)) return -1; if (rate->flags & IEEE80211_TX_RC_160_MHZ_WIDTH) @@ -632,7 +632,7 @@ { struct ieee80211_supported_band *sband; struct ieee80211_chanctx_conf *conf; - int rateidx, shift = 0; + int rateidx; bool cck, short_pream; u32 basic_rates; u8 band = 0; @@ -641,10 +641,8 @@ len += 38; /* Ethernet header length */ conf = rcu_dereference(vif->bss_conf.chanctx_conf); - if (conf) { + if (conf) band = conf->def.chan->band; - shift = ieee80211_chandef_get_shift(&conf->def); - } if (pubsta) { struct sta_info *sta = container_of(pubsta, struct sta_info, @@ -704,7 +702,7 @@ short_pream = vif->bss_conf.use_short_preamble; rateidx = basic_rates ? ffs(basic_rates) - 1 : 0; - rate = sband->bitrates[rateidx].bitrate << shift; + rate = sband->bitrates[rateidx].bitrate; cck = sband->bitrates[rateidx].flags & IEEE80211_RATE_MANDATORY_B; return ieee80211_calc_legacy_rate_duration(rate, short_pream, cck, len); diff -ruw linux-6.4/net/mac80211/cfg.c linux-6.4-fbx/net/mac80211/cfg.c --- linux-6.4/net/mac80211/cfg.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/cfg.c 2024-04-19 16:04:28.969736104 +0200 @@ -35,7 +35,7 @@ * the return value at all (if it's not a pairwise key), * so in that case (require_valid==false) don't error. */ - if (require_valid && sdata->vif.valid_links) + if (require_valid && ieee80211_vif_is_mld(&sdata->vif)) return ERR_PTR(-EINVAL); return &sdata->deflink; @@ -214,6 +214,8 @@ struct sta_info *sta; int ret; + lockdep_assert_wiphy(local->hw.wiphy); + ret = ieee80211_if_change_type(sdata, type); if (ret) return ret; @@ -228,19 +230,17 @@ return 0; /* FIXME: no support for 4-addr MLO yet */ - if (sdata->vif.valid_links) + if (ieee80211_vif_is_mld(&sdata->vif)) return -EOPNOTSUPP; sdata->u.mgd.use_4addr = params->use_4addr; if (!ifmgd->associated) return 0; - mutex_lock(&local->sta_mtx); sta = sta_info_get(sdata, sdata->deflink.u.mgd.bssid); if (sta) drv_sta_set_4addr(local, sdata, &sta->sta, params->use_4addr); - mutex_unlock(&local->sta_mtx); if (params->use_4addr) ieee80211_send_4addr_nullfunc(local, sdata); @@ -261,9 +261,9 @@ struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); int ret; - mutex_lock(&sdata->local->chanctx_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + ret = ieee80211_check_combinations(sdata, NULL, 0, 0); - mutex_unlock(&sdata->local->chanctx_mtx); if (ret < 0) return ret; @@ -283,9 +283,9 @@ struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); int ret; - mutex_lock(&sdata->local->chanctx_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + ret = ieee80211_check_combinations(sdata, NULL, 0, 0); - mutex_unlock(&sdata->local->chanctx_mtx); if (ret < 0) return ret; @@ -452,13 +452,11 @@ if (sta->ptk_idx == key_idx) return 0; - mutex_lock(&local->key_mtx); - key = key_mtx_dereference(local, sta->ptk[key_idx]); + key = wiphy_dereference(local->hw.wiphy, sta->ptk[key_idx]); if (key && key->conf.flags & IEEE80211_KEY_FLAG_NO_AUTO_TX) ret = ieee80211_set_tx_key(key); - mutex_unlock(&local->key_mtx); return ret; } @@ -474,6 +472,8 @@ struct ieee80211_key *key; int err; + lockdep_assert_wiphy(local->hw.wiphy); + if (!ieee80211_sdata_running(sdata)) return -ENETDOWN; @@ -510,8 +510,6 @@ if (params->mode == NL80211_KEY_NO_TX) key->conf.flags |= IEEE80211_KEY_FLAG_NO_AUTO_TX; - mutex_lock(&local->sta_mtx); - if (mac_addr) { sta = sta_info_get_bss(sdata, mac_addr); /* @@ -526,8 +524,7 @@ */ if (!sta || !test_sta_flag(sta, WLAN_STA_ASSOC)) { ieee80211_key_free_unused(key); - err = -ENOENT; - goto out_unlock; + return -ENOENT; } } @@ -566,10 +563,9 @@ } err = ieee80211_key_link(key, link, sta); - - out_unlock: - mutex_unlock(&local->sta_mtx); - + /* KRACK protection, shouldn't happen but just silently accept key */ + if (err == -EALREADY) + err = 0; return err; } @@ -582,8 +578,7 @@ struct ieee80211_key *key; if (link_id >= 0) { - link = rcu_dereference_check(sdata->link[link_id], - lockdep_is_held(&sdata->wdev.mtx)); + link = sdata_dereference(sdata->link[link_id], sdata); if (!link) return NULL; } @@ -598,7 +593,7 @@ if (link_id >= 0) { link_sta = rcu_dereference_check(sta->link[link_id], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (!link_sta) return NULL; } else { @@ -606,30 +601,29 @@ } if (pairwise && key_idx < NUM_DEFAULT_KEYS) - return rcu_dereference_check_key_mtx(local, + return wiphy_dereference(local->hw.wiphy, sta->ptk[key_idx]); if (!pairwise && key_idx < NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS + NUM_DEFAULT_BEACON_KEYS) - return rcu_dereference_check_key_mtx(local, + return wiphy_dereference(local->hw.wiphy, link_sta->gtk[key_idx]); return NULL; } if (pairwise && key_idx < NUM_DEFAULT_KEYS) - return rcu_dereference_check_key_mtx(local, - sdata->keys[key_idx]); + return wiphy_dereference(local->hw.wiphy, sdata->keys[key_idx]); - key = rcu_dereference_check_key_mtx(local, link->gtk[key_idx]); + key = wiphy_dereference(local->hw.wiphy, link->gtk[key_idx]); if (key) return key; /* or maybe it was a WEP key */ if (key_idx < NUM_DEFAULT_KEYS) - return rcu_dereference_check_key_mtx(local, sdata->keys[key_idx]); + return wiphy_dereference(local->hw.wiphy, sdata->keys[key_idx]); return NULL; } @@ -641,25 +635,16 @@ struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_local *local = sdata->local; struct ieee80211_key *key; - int ret; - mutex_lock(&local->sta_mtx); - mutex_lock(&local->key_mtx); + lockdep_assert_wiphy(local->hw.wiphy); key = ieee80211_lookup_key(sdata, link_id, key_idx, pairwise, mac_addr); - if (!key) { - ret = -ENOENT; - goto out_unlock; - } + if (!key) + return -ENOENT; ieee80211_key_free(key, sdata->vif.type == NL80211_IFTYPE_STATION); - ret = 0; - out_unlock: - mutex_unlock(&local->key_mtx); - mutex_unlock(&local->sta_mtx); - - return ret; + return 0; } static int ieee80211_get_key(struct wiphy *wiphy, struct net_device *dev, @@ -830,15 +815,11 @@ rinfo->nss = ieee80211_rate_get_vht_nss(rate); } else { struct ieee80211_supported_band *sband; - int shift = ieee80211_vif_get_shift(&sta->sdata->vif); - u16 brate; sband = ieee80211_get_sband(sta->sdata); WARN_ON_ONCE(sband && !sband->bitrates); - if (sband && sband->bitrates) { - brate = sband->bitrates[rate->idx].bitrate; - rinfo->legacy = DIV_ROUND_UP(brate, 1 << shift); - } + if (sband && sband->bitrates) + rinfo->legacy = sband->bitrates[rate->idx].bitrate; } if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) rinfo->bw = RATE_INFO_BW_40; @@ -860,7 +841,7 @@ struct sta_info *sta; int ret = -ENOENT; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); sta = sta_info_get_by_idx(sdata, idx); if (sta) { @@ -869,8 +850,6 @@ sta_set_sinfo(sta, sinfo, true); } - mutex_unlock(&local->sta_mtx); - return ret; } @@ -890,7 +869,7 @@ struct sta_info *sta; int ret = -ENOENT; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); sta = sta_info_get_bss(sdata, mac); if (sta) { @@ -898,8 +877,6 @@ sta_set_sinfo(sta, sinfo, true); } - mutex_unlock(&local->sta_mtx); - return ret; } @@ -910,10 +887,11 @@ struct ieee80211_sub_if_data *sdata; int ret = 0; + lockdep_assert_wiphy(local->hw.wiphy); + if (cfg80211_chandef_identical(&local->monitor_chandef, chandef)) return 0; - mutex_lock(&local->mtx); if (local->use_chanctx) { sdata = wiphy_dereference(local->hw.wiphy, local->monitor_sdata); @@ -923,14 +901,15 @@ chandef, IEEE80211_CHANCTX_EXCLUSIVE); } - } else if (local->open_count == local->monitors) { + } else { + if (local->open_count == local->monitors) { local->_oper_chandef = *chandef; ieee80211_hw_config(local, 0); } + } if (ret == 0) local->monitor_chandef = *chandef; - mutex_unlock(&local->mtx); return ret; } @@ -978,25 +957,29 @@ struct fils_discovery_data *new, *old = NULL; struct ieee80211_fils_discovery *fd; - if (!params->tmpl || !params->tmpl_len) - return -EINVAL; + if (!params->update) + return 0; fd = &link_conf->fils_discovery; fd->min_interval = params->min_interval; fd->max_interval = params->max_interval; old = sdata_dereference(link->u.ap.fils_discovery, sdata); + if (old) + kfree_rcu(old, rcu_head); + + if (params->tmpl && params->tmpl_len) { new = kzalloc(sizeof(*new) + params->tmpl_len, GFP_KERNEL); if (!new) return -ENOMEM; new->len = params->tmpl_len; memcpy(new->data, params->tmpl, params->tmpl_len); rcu_assign_pointer(link->u.ap.fils_discovery, new); + } else { + RCU_INIT_POINTER(link->u.ap.fils_discovery, NULL); + } - if (old) - kfree_rcu(old, rcu_head); - - return 0; + return BSS_CHANGED_FILS_DISCOVERY; } static int @@ -1007,23 +990,27 @@ { struct unsol_bcast_probe_resp_data *new, *old = NULL; - if (!params->tmpl || !params->tmpl_len) - return -EINVAL; + if (!params->update) + return 0; + + link_conf->unsol_bcast_probe_resp_interval = params->interval; old = sdata_dereference(link->u.ap.unsol_bcast_probe_resp, sdata); + if (old) + kfree_rcu(old, rcu_head); + + if (params->tmpl && params->tmpl_len) { new = kzalloc(sizeof(*new) + params->tmpl_len, GFP_KERNEL); if (!new) return -ENOMEM; new->len = params->tmpl_len; memcpy(new->data, params->tmpl, params->tmpl_len); rcu_assign_pointer(link->u.ap.unsol_bcast_probe_resp, new); + } else { + RCU_INIT_POINTER(link->u.ap.unsol_bcast_probe_resp, NULL); + } - if (old) - kfree_rcu(old, rcu_head); - - link_conf->unsol_bcast_probe_resp_interval = params->interval; - - return 0; + return BSS_CHANGED_UNSOL_BCAST_PROBE_RESP; } static int ieee80211_set_ftm_responder_params( @@ -1101,18 +1088,20 @@ return offset; } -static int ieee80211_assign_beacon(struct ieee80211_sub_if_data *sdata, +static int +ieee80211_assign_beacon(struct ieee80211_sub_if_data *sdata, struct ieee80211_link_data *link, struct cfg80211_beacon_data *params, const struct ieee80211_csa_settings *csa, - const struct ieee80211_color_change_settings *cca) + const struct ieee80211_color_change_settings *cca, + u64 *changed) { struct cfg80211_mbssid_elems *mbssid = NULL; struct cfg80211_rnr_elems *rnr = NULL; struct beacon_data *new, *old; int new_head_len, new_tail_len; int size, err; - u32 changed = BSS_CHANGED_BEACON; + u64 _changed = BSS_CHANGED_BEACON; struct ieee80211_bss_conf *link_conf = link->conf; old = sdata_dereference(link->u.ap.beacon, sdata); @@ -1219,7 +1208,7 @@ return err; } if (err == 0) - changed |= BSS_CHANGED_AP_PROBE_RESP; + _changed |= BSS_CHANGED_AP_PROBE_RESP; if (params->ftm_responder != -1) { link_conf->ftm_responder = params->ftm_responder; @@ -1235,7 +1224,7 @@ return err; } - changed |= BSS_CHANGED_FTM_RESPONDER; + _changed |= BSS_CHANGED_FTM_RESPONDER; } rcu_assign_pointer(link->u.ap.beacon, new); @@ -1244,7 +1233,8 @@ if (old) kfree_rcu(old, rcu_head); - return changed; + *changed |= _changed; + return 0; } static int ieee80211_start_ap(struct wiphy *wiphy, struct net_device *dev, @@ -1266,6 +1256,8 @@ struct ieee80211_link_data *link; struct ieee80211_bss_conf *link_conf; + lockdep_assert_wiphy(local->hw.wiphy); + link = sdata_dereference(sdata->link[link_id], sdata); if (!link) return -ENOLINK; @@ -1360,10 +1352,14 @@ (IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ | IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ | IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ); + link_conf->eht_80mhz_full_bw_ul_mumimo = + params->eht_cap->fixed.phy_cap_info[7] & + IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ; } else { link_conf->eht_su_beamformer = false; link_conf->eht_su_beamformee = false; link_conf->eht_mu_beamformer = false; + link_conf->eht_80mhz_full_bw_ul_mumimo = false; } if (sdata->vif.type == NL80211_IFTYPE_AP && @@ -1375,12 +1371,10 @@ return err; } - mutex_lock(&local->mtx); err = ieee80211_link_use_channel(link, ¶ms->chandef, IEEE80211_CHANCTX_SHARED); if (!err) ieee80211_link_copy_chanctx_to_vlans(link, false); - mutex_unlock(&local->mtx); if (err) { link_conf->beacon_int = prev_beacon_int; return err; @@ -1446,28 +1440,23 @@ if (ieee80211_hw_check(&local->hw, HAS_RATE_CONTROL)) link_conf->beacon_tx_rate = params->beacon_rate; - err = ieee80211_assign_beacon(sdata, link, ¶ms->beacon, NULL, NULL); + err = ieee80211_assign_beacon(sdata, link, ¶ms->beacon, NULL, NULL, + &changed); if (err < 0) goto error; - changed |= err; - if (params->fils_discovery.max_interval) { - err = ieee80211_set_fils_discovery(sdata, - ¶ms->fils_discovery, + err = ieee80211_set_fils_discovery(sdata, ¶ms->fils_discovery, link, link_conf); if (err < 0) goto error; - changed |= BSS_CHANGED_FILS_DISCOVERY; - } + changed |= err; - if (params->unsol_bcast_probe_resp.interval) { err = ieee80211_set_unsol_bcast_probe_resp(sdata, ¶ms->unsol_bcast_probe_resp, link, link_conf); if (err < 0) goto error; - changed |= BSS_CHANGED_UNSOL_BCAST_PROBE_RESP; - } + changed |= err; err = drv_start_ap(sdata->local, sdata, link_conf); if (err) { @@ -1491,25 +1480,26 @@ return 0; error: - mutex_lock(&local->mtx); ieee80211_link_release_channel(link); - mutex_unlock(&local->mtx); return err; } static int ieee80211_change_beacon(struct wiphy *wiphy, struct net_device *dev, - struct cfg80211_beacon_data *params) + struct cfg80211_ap_update *params) + { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_link_data *link; + struct cfg80211_beacon_data *beacon = ¶ms->beacon; struct beacon_data *old; int err; struct ieee80211_bss_conf *link_conf; + u64 changed = 0; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(wiphy); - link = sdata_dereference(sdata->link[params->link_id], sdata); + link = sdata_dereference(sdata->link[beacon->link_id], sdata); if (!link) return -ENOLINK; @@ -1525,17 +1515,31 @@ if (!old) return -ENOENT; - err = ieee80211_assign_beacon(sdata, link, params, NULL, NULL); + err = ieee80211_assign_beacon(sdata, link, beacon, NULL, NULL, + &changed); + if (err < 0) + return err; + + err = ieee80211_set_fils_discovery(sdata, ¶ms->fils_discovery, + link, link_conf); + if (err < 0) + return err; + changed |= err; + + err = ieee80211_set_unsol_bcast_probe_resp(sdata, + ¶ms->unsol_bcast_probe_resp, + link, link_conf); if (err < 0) return err; + changed |= err; - if (params->he_bss_color_valid && - params->he_bss_color.enabled != link_conf->he_bss_color.enabled) { - link_conf->he_bss_color.enabled = params->he_bss_color.enabled; - err |= BSS_CHANGED_HE_BSS_COLOR; + if (beacon->he_bss_color_valid && + beacon->he_bss_color.enabled != link_conf->he_bss_color.enabled) { + link_conf->he_bss_color.enabled = beacon->he_bss_color.enabled; + changed |= BSS_CHANGED_HE_BSS_COLOR; } - ieee80211_link_info_change_notify(sdata, link, err); + ieee80211_link_info_change_notify(sdata, link, changed); return 0; } @@ -1565,7 +1569,7 @@ sdata_dereference(sdata->link[link_id], sdata); struct ieee80211_bss_conf *link_conf = link->conf; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(local->hw.wiphy); old_beacon = sdata_dereference(link->u.ap.beacon, sdata); if (!old_beacon) @@ -1579,7 +1583,6 @@ sdata); /* abort any running channel switch or color change */ - mutex_lock(&local->mtx); link_conf->csa_active = false; link_conf->color_change_active = false; if (link->csa_block_tx) { @@ -1588,8 +1591,6 @@ link->csa_block_tx = false; } - mutex_unlock(&local->mtx); - ieee80211_free_next_beacon(link); /* turn off carrier for this interface and dependent VLANs */ @@ -1632,7 +1633,7 @@ if (sdata->wdev.cac_started) { chandef = link_conf->chandef; - cancel_delayed_work_sync(&link->dfs_cac_timer_work); + wiphy_delayed_work_cancel(wiphy, &link->dfs_cac_timer_work); cfg80211_cac_event(sdata->dev, &chandef, NL80211_RADAR_CAC_ABORTED, GFP_KERNEL); @@ -1644,10 +1645,8 @@ local->total_ps_buffered -= skb_queue_len(&sdata->u.ap.ps.bc_buf); ieee80211_purge_tx_queue(&local->hw, &sdata->u.ap.ps.bc_buf); - mutex_lock(&local->mtx); ieee80211_link_copy_chanctx_to_vlans(link, true); ieee80211_link_release_channel(link); - mutex_unlock(&local->mtx); return 0; } @@ -1718,7 +1717,7 @@ { #ifdef CONFIG_MAC80211_MESH struct ieee80211_sub_if_data *sdata = sta->sdata; - u32 changed = 0; + u64 changed = 0; if (params->sta_modify_mask & STATION_PARAM_APPLY_PLINK_STATE) { switch (params->plink_state) { @@ -1789,7 +1788,7 @@ sdata_dereference(sdata->link[link_id], sdata); struct link_sta_info *link_sta = rcu_dereference_protected(sta->link[link_id], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); /* * If there are no changes, then accept a link that doesn't exist, @@ -1800,7 +1799,8 @@ !params->supported_rates_len && !params->ht_capa && !params->vht_capa && !params->he_capa && !params->eht_capa && - !params->opmode_notif_used) + !params->opmode_notif_used && + !params->tp_overridden) return 0; if (!link || !link_sta) @@ -1846,7 +1846,8 @@ /* VHT can override some HT caps such as the A-MSDU max length */ if (params->vht_capa) ieee80211_vht_cap_ie_to_sta_vht_cap(sdata, sband, - params->vht_capa, link_sta); + params->vht_capa, NULL, + link_sta); if (params->he_capa) ieee80211_he_cap_ie_to_sta_he_cap(sdata, sband, @@ -1872,6 +1873,10 @@ sband->band); } + if (params->tp_overridden) + link_sta->pub->tp_override = params->tp_override; + + return ret; } @@ -2023,6 +2028,8 @@ struct ieee80211_sub_if_data *sdata; int err; + lockdep_assert_wiphy(local->hw.wiphy); + if (params->vlan) { sdata = IEEE80211_DEV_TO_SUB_IF(params->vlan); @@ -2066,9 +2073,7 @@ * visible yet), sta_apply_parameters (and inner functions) require * the mutex due to other paths. */ - mutex_lock(&local->sta_mtx); err = sta_apply_parameters(local, sta, params); - mutex_unlock(&local->sta_mtx); if (err) { sta_info_free(local, sta); return err; @@ -2111,13 +2116,11 @@ enum cfg80211_station_type statype; int err; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); sta = sta_info_get_bss(sdata, mac); - if (!sta) { - err = -ENOENT; - goto out_err; - } + if (!sta) + return -ENOENT; switch (sdata->vif.type) { case NL80211_IFTYPE_MESH_POINT: @@ -2147,22 +2150,19 @@ statype = CFG80211_STA_AP_CLIENT_UNASSOC; break; default: - err = -EOPNOTSUPP; - goto out_err; + return -EOPNOTSUPP; } err = cfg80211_check_station_change(wiphy, params, statype); if (err) - goto out_err; + return err; if (params->vlan && params->vlan != sta->sdata->dev) { vlansdata = IEEE80211_DEV_TO_SUB_IF(params->vlan); if (params->vlan->ieee80211_ptr->use_4addr) { - if (vlansdata->u.vlan.sta) { - err = -EBUSY; - goto out_err; - } + if (vlansdata->u.vlan.sta) + return -EBUSY; rcu_assign_pointer(vlansdata->u.vlan.sta, sta); __ieee80211_check_fast_rx_iface(vlansdata); @@ -2188,18 +2188,9 @@ } } - /* we use sta_info_get_bss() so this might be different */ - if (sdata != sta->sdata) { - mutex_lock_nested(&sta->sdata->wdev.mtx, 1); err = sta_apply_parameters(local, sta, params); - mutex_unlock(&sta->sdata->wdev.mtx); - } else { - err = sta_apply_parameters(local, sta, params); - } if (err) - goto out_err; - - mutex_unlock(&local->sta_mtx); + return err; if (sdata->vif.type == NL80211_IFTYPE_STATION && params->sta_flags_mask & BIT(NL80211_STA_FLAG_AUTHORIZED)) { @@ -2208,9 +2199,6 @@ } return 0; -out_err: - mutex_unlock(&local->sta_mtx); - return err; } #ifdef CONFIG_MAC80211_MESH @@ -2422,6 +2410,163 @@ return 0; } +int ieee80211_update_mpp(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst, const u8 *next_hop) +{ + struct ieee80211_sub_if_data *sdata; + int ret = 0; + struct mesh_path *mppath; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + + rcu_read_lock(); + + mppath = mpp_path_lookup(sdata, dst); + if (!mppath) { + ret = mpp_path_add(sdata, dst, next_hop); + if (!ret) { + mppath = mpp_path_lookup(sdata, dst); + spin_lock_bh(&mppath->state_lock); + mppath->flags |= MESH_PATH_FIXED; + spin_unlock_bh(&mppath->state_lock); + } + } else { + spin_lock_bh(&mppath->state_lock); + if (!ether_addr_equal(mppath->mpp, next_hop)) + memcpy(mppath->mpp, next_hop, ETH_ALEN); + mppath->exp_time = jiffies; + mppath->flags |= MESH_PATH_FIXED; + spin_unlock_bh(&mppath->state_lock); + } + rcu_read_unlock(); + return ret; +} + +int ieee80211_delete_mpp(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst) +{ + struct ieee80211_sub_if_data *sdata; + int ret = 0; + struct mesh_path *mppath; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + rcu_read_lock(); + mppath = mpp_path_lookup(sdata, dst); + if (mppath) { + spin_lock_bh(&mppath->state_lock); + mppath->flags &= ~MESH_PATH_FIXED; + spin_unlock_bh(&mppath->state_lock); + } else { + ret = -ENOENT; + } + rcu_read_unlock(); + return ret; +} + +static struct mplink_block_list_info * +ieee80211_find_mp_blink_info(struct ieee80211_if_mesh *ifmsh, const u8 *dst) +{ + struct mplink_block_list_info *mp_blink; + + list_for_each_entry(mp_blink, &ifmsh->mplink_blocking_list, list) { + if (ether_addr_equal(dst, mp_blink->dst)) + return mp_blink; + } + + return NULL; +} + +int ieee80211_mplink_block(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_if_mesh *ifmsh; + struct mplink_block_list_info *mp_blink; + int ret = 0; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + ifmsh = &sdata->u.mesh; + + spin_lock_bh(&ifmsh->mplink_blocking_list_lock); + + if (ieee80211_find_mp_blink_info(ifmsh, dst)) + goto out; + + mp_blink = kzalloc(sizeof(*mp_blink), GFP_ATOMIC); + if (!mp_blink) { + ret = -ENOMEM; + goto out; + } + + memcpy(mp_blink->dst, dst, ETH_ALEN); + list_add_tail(&mp_blink->list, &ifmsh->mplink_blocking_list); + +out: + spin_unlock_bh(&ifmsh->mplink_blocking_list_lock); + return ret; +} + +int ieee80211_mplink_unblock(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_if_mesh *ifmsh; + struct mplink_block_list_info *mp_blink; + int ret = 0; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + ifmsh = &sdata->u.mesh; + + spin_lock_bh(&ifmsh->mplink_blocking_list_lock); + + mp_blink = ieee80211_find_mp_blink_info(ifmsh, dst); + if (!mp_blink) { + ret = -ENOENT; + goto out; + } + + list_del(&mp_blink->list); + kfree(mp_blink); + +out: + spin_unlock_bh(&ifmsh->mplink_blocking_list_lock); + + return ret; +} + +int ieee80211_dump_blocked_mplink_info(struct wiphy *wiphy, struct net_device *dev, + struct mplink_blocked_info *minfo) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_if_mesh *ifmsh; + struct mplink_block_list_info *mp_blink; + u32 len = 0; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + ifmsh = &sdata->u.mesh; + + spin_lock_bh(&ifmsh->mplink_blocking_list_lock); + list_for_each_entry(mp_blink, &ifmsh->mplink_blocking_list, list) { + if (minfo->count > (sizeof(struct mplink_blocked_info) / ETH_ALEN)) + break; + memcpy(minfo->info + len, mp_blink->dst, ETH_ALEN); + len += ETH_ALEN; + minfo->count++; + } + spin_unlock_bh(&ifmsh->mplink_blocking_list_lock); + + return 0; +} + +int ieee80211_mplink_flush(struct wiphy *wiphy, struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + + ieee80211_mesh_free_blocked_mplink_entries(sdata); + + return 0; +} + static int ieee80211_get_mesh_config(struct wiphy *wiphy, struct net_device *dev, struct mesh_config *conf) @@ -2615,6 +2760,36 @@ return 0; } +int ieee80211_update_mesh_vendor_node_metrics_ie(struct wiphy *wiphy, + struct net_device *dev, + const struct mesh_vendor_ie *vendor_ie) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_if_mesh *ifmsh; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + ifmsh = &sdata->u.mesh; + memcpy(ifmsh->node_vendor_ie, vendor_ie->ie, vendor_ie->ie_len); + ifmsh->node_vendor_ie_len = vendor_ie->ie_len; + ieee80211_mbss_info_change_notify(sdata, BSS_CHANGED_BEACON); + return 0; +} + +int ieee80211_update_mesh_vendor_path_metrics_ie(struct wiphy *wiphy, + struct net_device *dev, + const struct mesh_vendor_ie *vendor_ie) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_if_mesh *ifmsh; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + ifmsh = &sdata->u.mesh; + memcpy(ifmsh->mpm_vendor_ie, vendor_ie->ie, vendor_ie->ie_len); + ifmsh->mpm_vendor_ie_len = vendor_ie->ie_len; + ieee80211_mbss_info_change_notify(sdata, BSS_CHANGED_BEACON); + return 0; +} + static int ieee80211_join_mesh(struct wiphy *wiphy, struct net_device *dev, const struct mesh_config *conf, const struct mesh_setup *setup) @@ -2623,6 +2798,8 @@ struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; int err; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + memcpy(&ifmsh->mshcfg, conf, sizeof(struct mesh_config)); err = copy_mesh_setup(ifmsh, setup); if (err) @@ -2634,12 +2811,12 @@ sdata->deflink.smps_mode = IEEE80211_SMPS_OFF; sdata->deflink.needed_rx_chains = sdata->local->rx_chains; - mutex_lock(&sdata->local->mtx); err = ieee80211_link_use_channel(&sdata->deflink, &setup->chandef, IEEE80211_CHANCTX_SHARED); - mutex_unlock(&sdata->local->mtx); - if (err) + if (err) { + kfree(ifmsh->ie); return err; + } return ieee80211_start_mesh(sdata); } @@ -2648,11 +2825,11 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + ieee80211_stop_mesh(sdata); - mutex_lock(&sdata->local->mtx); ieee80211_link_release_channel(&sdata->deflink); kfree(sdata->u.mesh.ie); - mutex_unlock(&sdata->local->mtx); return 0; } @@ -2665,7 +2842,7 @@ struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_link_data *link; struct ieee80211_supported_band *sband; - u32 changed = 0; + u64 changed = 0; link = ieee80211_link_or_deflink(sdata, params->link_id, true); if (IS_ERR(link)) @@ -3010,6 +3187,8 @@ bool update_txp_type = false; bool has_monitor = false; + lockdep_assert_wiphy(local->hw.wiphy); + if (wdev) { sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); @@ -3057,7 +3236,6 @@ break; } - mutex_lock(&local->iflist_mtx); list_for_each_entry(sdata, &local->interfaces, list) { if (sdata->vif.type == NL80211_IFTYPE_MONITOR) { has_monitor = true; @@ -3073,7 +3251,6 @@ continue; ieee80211_recalc_txpower(sdata, update_txp_type); } - mutex_unlock(&local->iflist_mtx); if (has_monitor) { sdata = wiphy_dereference(local->hw.wiphy, @@ -3106,6 +3283,10 @@ else *dbm = sdata->vif.bss_conf.txpower; + /* INT_MIN indicates no power level was set yet */ + if (*dbm == INT_MIN) + return -EINVAL; + return 0; } @@ -3162,14 +3343,24 @@ struct sta_info *sta; bool tdls_peer_found = false; - lockdep_assert_held(&sdata->wdev.mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (WARN_ON_ONCE(sdata->vif.type != NL80211_IFTYPE_STATION)) return -EINVAL; + if (ieee80211_vif_is_mld(&sdata->vif) && + !(sdata->vif.active_links & BIT(link->link_id))) + return 0; + old_req = link->u.mgd.req_smps; link->u.mgd.req_smps = smps_mode; + /* The driver indicated that EML is enabled for the interface, which + * implies that SMPS flows towards the AP should be stopped. + */ + if (sdata->vif.driver_flags & IEEE80211_VIF_EML_ACTIVE) + return 0; + if (old_req == smps_mode && smps_mode != IEEE80211_SMPS_AUTOMATIC) return 0; @@ -3183,7 +3374,7 @@ link->conf->chandef.width == NL80211_CHAN_WIDTH_20_NOHT) return 0; - ap = link->u.mgd.bssid; + ap = sdata->vif.cfg.ap_addr; rcu_read_lock(); list_for_each_entry_rcu(sta, &sdata->local->sta_list, list) { @@ -3205,7 +3396,9 @@ /* send SM PS frame to AP */ err = ieee80211_send_smps_action(sdata, smps_mode, - ap, ap); + ap, ap, + ieee80211_vif_is_mld(&sdata->vif) ? + link->link_id : -1); if (err) link->u.mgd.req_smps = old_req; else if (smps_mode != IEEE80211_SMPS_OFF && tdls_peer_found) @@ -3235,7 +3428,6 @@ local->dynamic_ps_forced_timeout = timeout; /* no change, but if automatic follow powersave */ - sdata_lock(sdata); for (link_id = 0; link_id < ARRAY_SIZE(sdata->link); link_id++) { struct ieee80211_link_data *link; @@ -3246,7 +3438,6 @@ __ieee80211_request_smps_mgd(sdata, link, link->u.mgd.req_smps); } - sdata_unlock(sdata); if (ieee80211_hw_check(&local->hw, SUPPORTS_DYNAMIC_PS)) ieee80211_hw_config(local, IEEE80211_CONF_CHANGE_PS); @@ -3392,7 +3583,8 @@ struct ieee80211_local *local = sdata->local; int err; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); + if (!list_empty(&local->roc_list) || local->scanning) { err = -EBUSY; goto out_unlock; @@ -3407,12 +3599,10 @@ if (err) goto out_unlock; - ieee80211_queue_delayed_work(&sdata->local->hw, - &sdata->deflink.dfs_cac_timer_work, + wiphy_delayed_work_queue(wiphy, &sdata->deflink.dfs_cac_timer_work, msecs_to_jiffies(cac_time_ms)); out_unlock: - mutex_unlock(&local->mtx); return err; } @@ -3422,20 +3612,21 @@ struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_local *local = sdata->local; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); + list_for_each_entry(sdata, &local->interfaces, list) { /* it might be waiting for the local->mtx, but then * by the time it gets it, sdata->wdev.cac_started * will no longer be true */ - cancel_delayed_work(&sdata->deflink.dfs_cac_timer_work); + wiphy_delayed_work_cancel(wiphy, + &sdata->deflink.dfs_cac_timer_work); if (sdata->wdev.cac_started) { ieee80211_link_release_channel(&sdata->deflink); sdata->wdev.cac_started = false; } } - mutex_unlock(&local->mtx); } static struct cfg80211_beacon_data * @@ -3567,11 +3758,11 @@ if (iter == sdata || iter->vif.mbssid_tx_vif != vif) continue; - ieee80211_queue_work(&iter->local->hw, + wiphy_work_queue(iter->local->hw.wiphy, &iter->deflink.csa_finalize_work); } } - ieee80211_queue_work(&local->hw, &sdata->deflink.csa_finalize_work); + wiphy_work_queue(local->hw.wiphy, &sdata->deflink.csa_finalize_work); rcu_read_unlock(); } @@ -3585,7 +3776,7 @@ sdata->deflink.csa_block_tx = block_tx; sdata_info(sdata, "channel switch failed, disconnecting\n"); - ieee80211_queue_work(&local->hw, &ifmgd->csa_connection_drop_work); + wiphy_work_queue(local->hw.wiphy, &ifmgd->csa_connection_drop_work); } EXPORT_SYMBOL(ieee80211_channel_switch_disconnect); @@ -3601,25 +3792,22 @@ err = ieee80211_assign_beacon(sdata, &sdata->deflink, sdata->deflink.u.ap.next_beacon, - NULL, NULL); + NULL, NULL, changed); ieee80211_free_next_beacon(&sdata->deflink); if (err < 0) return err; - *changed |= err; break; case NL80211_IFTYPE_ADHOC: - err = ieee80211_ibss_finish_csa(sdata); + err = ieee80211_ibss_finish_csa(sdata, changed); if (err < 0) return err; - *changed |= err; break; #ifdef CONFIG_MAC80211_MESH case NL80211_IFTYPE_MESH_POINT: - err = ieee80211_mesh_finish_csa(sdata); + err = ieee80211_mesh_finish_csa(sdata, changed); if (err < 0) return err; - *changed |= err; break; #endif default: @@ -3630,21 +3818,14 @@ return 0; } -static int __ieee80211_csa_finalize(struct ieee80211_sub_if_data *sdata) +static int __ieee80211_csa_finalize(struct ieee80211_link_data *link_data) { + struct ieee80211_sub_if_data *sdata = link_data->sdata; struct ieee80211_local *local = sdata->local; u64 changed = 0; int err; - sdata_assert_lock(sdata); - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); - - if (sdata->vif.bss_conf.eht_puncturing != sdata->vif.bss_conf.csa_punct_bitmap) { - sdata->vif.bss_conf.eht_puncturing = - sdata->vif.bss_conf.csa_punct_bitmap; - changed |= BSS_CHANGED_EHT_PUNCTURING; - } + lockdep_assert_wiphy(local->hw.wiphy); /* * using reservation isn't immediate as it may be deferred until later @@ -3653,20 +3834,20 @@ * completed successfully */ - if (sdata->deflink.reserved_chanctx) { + if (link_data->reserved_chanctx) { /* * with multi-vif csa driver may call ieee80211_csa_finish() * many times while waiting for other interfaces to use their * reservations */ - if (sdata->deflink.reserved_ready) + if (link_data->reserved_ready) return 0; return ieee80211_link_use_reserved_context(&sdata->deflink); } - if (!cfg80211_chandef_identical(&sdata->vif.bss_conf.chandef, - &sdata->deflink.csa_chandef)) + if (!cfg80211_chandef_identical(&link_data->conf->chandef, + &link_data->csa_chandef)) return -EINVAL; sdata->vif.bss_conf.csa_active = false; @@ -3675,62 +3856,64 @@ if (err) return err; - ieee80211_link_info_change_notify(sdata, &sdata->deflink, changed); + if (sdata->vif.bss_conf.eht_puncturing != sdata->vif.bss_conf.csa_punct_bitmap) { + sdata->vif.bss_conf.eht_puncturing = + sdata->vif.bss_conf.csa_punct_bitmap; + changed |= BSS_CHANGED_EHT_PUNCTURING; + } + + ieee80211_link_info_change_notify(sdata, link_data, changed); - if (sdata->deflink.csa_block_tx) { + if (link_data->csa_block_tx) { ieee80211_wake_vif_queues(local, sdata, IEEE80211_QUEUE_STOP_REASON_CSA); - sdata->deflink.csa_block_tx = false; + link_data->csa_block_tx = false; } - err = drv_post_channel_switch(sdata); + err = drv_post_channel_switch(link_data); if (err) return err; - cfg80211_ch_switch_notify(sdata->dev, &sdata->deflink.csa_chandef, 0, - sdata->vif.bss_conf.eht_puncturing); + cfg80211_ch_switch_notify(sdata->dev, &link_data->csa_chandef, + link_data->link_id, + link_data->conf->eht_puncturing); return 0; } -static void ieee80211_csa_finalize(struct ieee80211_sub_if_data *sdata) +static void ieee80211_csa_finalize(struct ieee80211_link_data *link_data) { - if (__ieee80211_csa_finalize(sdata)) { + struct ieee80211_sub_if_data *sdata = link_data->sdata; + + if (__ieee80211_csa_finalize(link_data)) { sdata_info(sdata, "failed to finalize CSA, disconnecting\n"); cfg80211_stop_iface(sdata->local->hw.wiphy, &sdata->wdev, GFP_KERNEL); } } -void ieee80211_csa_finalize_work(struct work_struct *work) +void ieee80211_csa_finalize_work(struct wiphy *wiphy, struct wiphy_work *work) { - struct ieee80211_sub_if_data *sdata = - container_of(work, struct ieee80211_sub_if_data, - deflink.csa_finalize_work); + struct ieee80211_link_data *link = + container_of(work, struct ieee80211_link_data, csa_finalize_work); + struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_local *local = sdata->local; - sdata_lock(sdata); - mutex_lock(&local->mtx); - mutex_lock(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* AP might have been stopped while waiting for the lock. */ - if (!sdata->vif.bss_conf.csa_active) - goto unlock; + if (!link->conf->csa_active) + return; if (!ieee80211_sdata_running(sdata)) - goto unlock; - - ieee80211_csa_finalize(sdata); + return; -unlock: - mutex_unlock(&local->chanctx_mtx); - mutex_unlock(&local->mtx); - sdata_unlock(sdata); + ieee80211_csa_finalize(link); } static int ieee80211_set_csa_beacon(struct ieee80211_sub_if_data *sdata, struct cfg80211_csa_settings *params, - u32 *changed) + u64 *changed) { struct ieee80211_csa_settings csa = {}; int err; @@ -3777,12 +3960,11 @@ err = ieee80211_assign_beacon(sdata, &sdata->deflink, ¶ms->beacon_csa, &csa, - NULL); + NULL, changed); if (err < 0) { ieee80211_free_next_beacon(&sdata->deflink); return err; } - *changed |= err; break; case NL80211_IFTYPE_ADHOC: @@ -3814,10 +3996,9 @@ /* see comments in the NL80211_IFTYPE_AP block */ if (params->count > 1) { - err = ieee80211_ibss_csa_beacon(sdata, params); + err = ieee80211_ibss_csa_beacon(sdata, params, changed); if (err < 0) return err; - *changed |= err; } ieee80211_send_action_csa(sdata, params); @@ -3842,12 +4023,11 @@ /* see comments in the NL80211_IFTYPE_AP block */ if (params->count > 1) { - err = ieee80211_mesh_csa_beacon(sdata, params); + err = ieee80211_mesh_csa_beacon(sdata, params, changed); if (err < 0) { ifmsh->csa_role = IEEE80211_MESH_CSA_ROLE_NONE; return err; } - *changed |= err; } if (ifmsh->csa_role == IEEE80211_MESH_CSA_ROLE_INIT) @@ -3881,11 +4061,10 @@ struct ieee80211_channel_switch ch_switch; struct ieee80211_chanctx_conf *conf; struct ieee80211_chanctx *chanctx; - u32 changed = 0; + u64 changed = 0; int err; - sdata_assert_lock(sdata); - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (!list_empty(&local->roc_list) || local->scanning) return -EBUSY; @@ -3901,9 +4080,8 @@ if (sdata->vif.bss_conf.csa_active) return -EBUSY; - mutex_lock(&local->chanctx_mtx); conf = rcu_dereference_protected(sdata->vif.bss_conf.chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (!conf) { err = -EBUSY; goto out; @@ -3973,11 +4151,10 @@ drv_channel_switch_beacon(sdata, ¶ms->chandef); } else { /* if the beacon didn't change, we can finalize immediately */ - ieee80211_csa_finalize(sdata); + ieee80211_csa_finalize(&sdata->deflink); } out: - mutex_unlock(&local->chanctx_mtx); return err; } @@ -3986,18 +4163,15 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_local *local = sdata->local; - int err; - mutex_lock(&local->mtx); - err = __ieee80211_channel_switch(wiphy, dev, params); - mutex_unlock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); - return err; + return __ieee80211_channel_switch(wiphy, dev, params); } u64 ieee80211_mgmt_tx_cookie(struct ieee80211_local *local) { - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); local->roc_cookie_counter++; @@ -4029,7 +4203,8 @@ return -ENOMEM; } - IEEE80211_SKB_CB(skb)->ack_frame_id = id; + IEEE80211_SKB_CB(skb)->status_data_idr = 1; + IEEE80211_SKB_CB(skb)->status_data = id; *cookie = ieee80211_mgmt_tx_cookie(local); IEEE80211_SKB_CB(ack_skb)->ack.cookie = *cookie; @@ -4079,11 +4254,17 @@ static int ieee80211_set_antenna(struct wiphy *wiphy, u32 tx_ant, u32 rx_ant) { struct ieee80211_local *local = wiphy_priv(wiphy); + int ret; if (local->started) return -EOPNOTSUPP; - return drv_set_antenna(local, tx_ant, rx_ant); + ret = drv_set_antenna(local, tx_ant, rx_ant); + if (ret) + return ret; + + local->rx_chains = hweight8(rx_ant); + return 0; } static int ieee80211_get_antenna(struct wiphy *wiphy, u32 *tx_ant, u32 *rx_ant) @@ -4125,22 +4306,23 @@ int ret; /* the lock is needed to assign the cookie later */ - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); rcu_read_lock(); + sta = sta_info_get_bss(sdata, peer); + if (!sta) { + ret = -ENOLINK; + goto unlock; + } + + qos = sta->sta.wme; + chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf); if (WARN_ON(!chanctx_conf)) { ret = -EINVAL; goto unlock; } band = chanctx_conf->def.chan->band; - sta = sta_info_get_bss(sdata, peer); - if (sta) { - qos = sta->sta.wme; - } else { - ret = -ENOLINK; - goto unlock; - } if (qos) { fc = cpu_to_le16(IEEE80211_FTYPE_DATA | @@ -4195,7 +4377,6 @@ ret = 0; unlock: rcu_read_unlock(); - mutex_unlock(&local->mtx); return ret; } @@ -4553,7 +4734,8 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct sta_info *sta; - int ret; + + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (!sdata->local->ops->set_tid_config) return -EOPNOTSUPP; @@ -4561,17 +4743,11 @@ if (!tid_conf->peer) return drv_set_tid_config(sdata->local, sdata, NULL, tid_conf); - mutex_lock(&sdata->local->sta_mtx); sta = sta_info_get_bss(sdata, tid_conf->peer); - if (!sta) { - mutex_unlock(&sdata->local->sta_mtx); + if (!sta) return -ENOENT; - } - ret = drv_set_tid_config(sdata->local, sdata, &sta->sta, tid_conf); - mutex_unlock(&sdata->local->sta_mtx); - - return ret; + return drv_set_tid_config(sdata->local, sdata, &sta->sta, tid_conf); } static int ieee80211_reset_tid_config(struct wiphy *wiphy, @@ -4580,7 +4756,8 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct sta_info *sta; - int ret; + + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (!sdata->local->ops->reset_tid_config) return -EOPNOTSUPP; @@ -4588,17 +4765,11 @@ if (!peer) return drv_reset_tid_config(sdata->local, sdata, NULL, tids); - mutex_lock(&sdata->local->sta_mtx); sta = sta_info_get_bss(sdata, peer); - if (!sta) { - mutex_unlock(&sdata->local->sta_mtx); + if (!sta) return -ENOENT; - } - - ret = drv_reset_tid_config(sdata->local, sdata, &sta->sta, tids); - mutex_unlock(&sdata->local->sta_mtx); - return ret; + return drv_reset_tid_config(sdata->local, sdata, &sta->sta, tids); } static int ieee80211_set_sar_specs(struct wiphy *wiphy, @@ -4614,7 +4785,7 @@ static int ieee80211_set_after_color_change_beacon(struct ieee80211_sub_if_data *sdata, - u32 *changed) + u64 *changed) { switch (sdata->vif.type) { case NL80211_IFTYPE_AP: { @@ -4625,13 +4796,12 @@ ret = ieee80211_assign_beacon(sdata, &sdata->deflink, sdata->deflink.u.ap.next_beacon, - NULL, NULL); + NULL, NULL, changed); ieee80211_free_next_beacon(&sdata->deflink); if (ret < 0) return ret; - *changed |= ret; break; } default: @@ -4645,7 +4815,7 @@ static int ieee80211_set_color_change_beacon(struct ieee80211_sub_if_data *sdata, struct cfg80211_color_change_settings *params, - u32 *changed) + u64 *changed) { struct ieee80211_color_change_settings color_change = {}; int err; @@ -4668,12 +4838,11 @@ err = ieee80211_assign_beacon(sdata, &sdata->deflink, ¶ms->beacon_color_change, - NULL, &color_change); + NULL, &color_change, changed); if (err < 0) { ieee80211_free_next_beacon(&sdata->deflink); return err; } - *changed |= err; break; default: return -EOPNOTSUPP; @@ -4684,8 +4853,10 @@ static void ieee80211_color_change_bss_config_notify(struct ieee80211_sub_if_data *sdata, - u8 color, int enable, u32 changed) + u8 color, int enable, u64 changed) { + lockdep_assert_wiphy(sdata->local->hw.wiphy); + sdata->vif.bss_conf.he_bss_color.color = color; sdata->vif.bss_conf.he_bss_color.enabled = enable; changed |= BSS_CHANGED_HE_BSS_COLOR; @@ -4695,7 +4866,6 @@ if (!sdata->vif.bss_conf.nontransmitted && sdata->vif.mbssid_tx_vif) { struct ieee80211_sub_if_data *child; - mutex_lock(&sdata->local->iflist_mtx); list_for_each_entry(child, &sdata->local->interfaces, list) { if (child != sdata && child->vif.mbssid_tx_vif == &sdata->vif) { child->vif.bss_conf.he_bss_color.color = color; @@ -4705,18 +4875,16 @@ BSS_CHANGED_HE_BSS_COLOR); } } - mutex_unlock(&sdata->local->iflist_mtx); } } static int ieee80211_color_change_finalize(struct ieee80211_sub_if_data *sdata) { struct ieee80211_local *local = sdata->local; - u32 changed = 0; + u64 changed = 0; int err; - sdata_assert_lock(sdata); - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); sdata->vif.bss_conf.color_change_active = false; @@ -4734,28 +4902,24 @@ return 0; } -void ieee80211_color_change_finalize_work(struct work_struct *work) +void ieee80211_color_change_finalize_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata = container_of(work, struct ieee80211_sub_if_data, deflink.color_change_finalize_work); struct ieee80211_local *local = sdata->local; - sdata_lock(sdata); - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* AP might have been stopped while waiting for the lock. */ if (!sdata->vif.bss_conf.color_change_active) - goto unlock; + return; if (!ieee80211_sdata_running(sdata)) - goto unlock; + return; ieee80211_color_change_finalize(sdata); - -unlock: - mutex_unlock(&local->mtx); - sdata_unlock(sdata); } void ieee80211_color_collision_detection_work(struct work_struct *work) @@ -4766,16 +4930,14 @@ color_collision_detect_work); struct ieee80211_sub_if_data *sdata = link->sdata; - sdata_lock(sdata); cfg80211_obss_color_collision_notify(sdata->dev, link->color_bitmap); - sdata_unlock(sdata); } void ieee80211_color_change_finish(struct ieee80211_vif *vif) { struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->deflink.color_change_finalize_work); } EXPORT_SYMBOL_GPL(ieee80211_color_change_finish); @@ -4809,16 +4971,14 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_local *local = sdata->local; - u32 changed = 0; + u64 changed = 0; int err; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(local->hw.wiphy); if (sdata->vif.bss_conf.nontransmitted) return -EINVAL; - mutex_lock(&local->mtx); - /* don't allow another color change if one is already active or if csa * is active */ @@ -4843,7 +5003,6 @@ ieee80211_color_change_finalize(sdata); out: - mutex_unlock(&local->mtx); return err; } @@ -4865,16 +5024,13 @@ unsigned int link_id) { struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); - int res; + + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (wdev->use_4addr) return -EOPNOTSUPP; - mutex_lock(&sdata->local->mtx); - res = ieee80211_vif_set_links(sdata, wdev->valid_links); - mutex_unlock(&sdata->local->mtx); - - return res; + return ieee80211_vif_set_links(sdata, wdev->valid_links, 0); } static void ieee80211_del_intf_link(struct wiphy *wiphy, @@ -4883,9 +5039,9 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); - mutex_lock(&sdata->local->mtx); - ieee80211_vif_set_links(sdata, wdev->valid_links); - mutex_unlock(&sdata->local->mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + + ieee80211_vif_set_links(sdata, wdev->valid_links, 0); } static int sta_add_link_station(struct ieee80211_local *local, @@ -4925,13 +5081,10 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_local *local = wiphy_priv(wiphy); - int ret; - mutex_lock(&sdata->local->sta_mtx); - ret = sta_add_link_station(local, sdata, params); - mutex_unlock(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); - return ret; + return sta_add_link_station(local, sdata, params); } static int sta_mod_link_station(struct ieee80211_local *local, @@ -4956,13 +5109,10 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_local *local = wiphy_priv(wiphy); - int ret; - mutex_lock(&sdata->local->sta_mtx); - ret = sta_mod_link_station(local, sdata, params); - mutex_unlock(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); - return ret; + return sta_mod_link_station(local, sdata, params); } static int sta_del_link_station(struct ieee80211_sub_if_data *sdata, @@ -4991,13 +5141,10 @@ struct link_station_del_parameters *params) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); - int ret; - mutex_lock(&sdata->local->sta_mtx); - ret = sta_del_link_station(sdata, params); - mutex_unlock(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); - return ret; + return sta_del_link_station(sdata, params); } static int ieee80211_set_hw_timestamp(struct wiphy *wiphy, @@ -5053,6 +5200,7 @@ .join_ocb = ieee80211_join_ocb, .leave_ocb = ieee80211_leave_ocb, .change_bss = ieee80211_change_bss, + .inform_bss = ieee80211_inform_bss, .set_txq_params = ieee80211_set_txq_params, .set_monitor_channel = ieee80211_set_monitor_channel, .suspend = ieee80211_suspend, diff -ruw linux-6.4/net/mac80211/chan.c linux-6.4-fbx/net/mac80211/chan.c --- linux-6.4/net/mac80211/chan.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/chan.c 2023-11-07 13:38:44.074257019 +0100 @@ -18,7 +18,7 @@ struct ieee80211_link_data *link; int num = 0; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(link, &ctx->assigned_links, assigned_chanctx_list) num++; @@ -32,7 +32,7 @@ struct ieee80211_link_data *link; int num = 0; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(link, &ctx->reserved_links, reserved_chanctx_list) num++; @@ -52,7 +52,7 @@ struct ieee80211_chanctx *ctx; int num = 0; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(ctx, &local->chanctx_list, list) num++; @@ -62,7 +62,8 @@ static bool ieee80211_can_create_new_chanctx(struct ieee80211_local *local) { - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + return ieee80211_num_chanctx(local) < ieee80211_max_num_channels(local); } @@ -73,7 +74,7 @@ struct ieee80211_chanctx_conf *conf; conf = rcu_dereference_protected(link->conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (!conf) return NULL; @@ -87,7 +88,7 @@ { struct ieee80211_link_data *link; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(link, &ctx->reserved_links, reserved_chanctx_list) { @@ -110,7 +111,7 @@ { struct ieee80211_link_data *link; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(link, &ctx->assigned_links, assigned_chanctx_list) { @@ -136,7 +137,7 @@ struct ieee80211_chanctx *ctx, const struct cfg80211_chan_def *compat) { - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); compat = ieee80211_chanctx_reserved_chandef(local, ctx, compat); if (!compat) @@ -154,7 +155,7 @@ struct ieee80211_chanctx *ctx, const struct cfg80211_chan_def *def) { - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (ieee80211_chanctx_combined_chandef(local, ctx, def)) return true; @@ -173,7 +174,7 @@ { struct ieee80211_chanctx *ctx; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (mode == IEEE80211_CHANCTX_EXCLUSIVE) return NULL; @@ -361,7 +362,7 @@ enum nl80211_chan_width max_bw; struct cfg80211_chan_def min_def; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* don't optimize non-20MHz based and radar_enabled confs */ if (ctx->conf.def.width == NL80211_CHAN_WIDTH_5 || @@ -537,7 +538,7 @@ { struct ieee80211_chanctx *ctx; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (mode == IEEE80211_CHANCTX_EXCLUSIVE) return NULL; @@ -572,7 +573,7 @@ { struct ieee80211_sub_if_data *sdata; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); rcu_read_lock(); list_for_each_entry_rcu(sdata, &local->interfaces, list) { @@ -602,8 +603,7 @@ struct ieee80211_sub_if_data *sdata; bool required = false; - lockdep_assert_held(&local->chanctx_mtx); - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); rcu_read_lock(); list_for_each_entry_rcu(sdata, &local->interfaces, list) { @@ -641,7 +641,7 @@ { struct ieee80211_chanctx *ctx; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); ctx = kzalloc(sizeof(*ctx) + local->hw.chanctx_data_size, GFP_KERNEL); if (!ctx) @@ -665,8 +665,7 @@ u32 changed; int err; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (!local->use_chanctx) local->hw.conf.radar_enabled = ctx->conf.radar_enabled; @@ -698,8 +697,7 @@ struct ieee80211_chanctx *ctx; int err; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); ctx = ieee80211_alloc_chanctx(local, chandef, mode); if (!ctx) @@ -718,7 +716,7 @@ static void ieee80211_del_chanctx(struct ieee80211_local *local, struct ieee80211_chanctx *ctx) { - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (!local->use_chanctx) { struct cfg80211_chan_def *chandef = &local->_oper_chandef; @@ -753,7 +751,7 @@ static void ieee80211_free_chanctx(struct ieee80211_local *local, struct ieee80211_chanctx *ctx) { - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); WARN_ON_ONCE(ieee80211_chanctx_refcount(local, ctx) != 0); @@ -770,7 +768,7 @@ const struct cfg80211_chan_def *compat = NULL; struct sta_info *sta; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); rcu_read_lock(); list_for_each_entry_rcu(sdata, &local->interfaces, list) { @@ -802,6 +800,11 @@ } } + if (WARN_ON_ONCE(!compat)) { + rcu_read_unlock(); + return; + } + /* TDLS peers can sometimes affect the chandef width */ list_for_each_entry_rcu(sta, &local->sta_list, list) { if (!sta->uploaded || @@ -828,9 +831,7 @@ { bool radar_enabled; - lockdep_assert_held(&local->chanctx_mtx); - /* for ieee80211_is_radar_required */ - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); radar_enabled = ieee80211_chanctx_radar_required(local, chanctx); @@ -860,7 +861,7 @@ return -ENOTSUPP; conf = rcu_dereference_protected(link->conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (conf) { curr_ctx = container_of(conf, struct ieee80211_chanctx, conf); @@ -915,7 +916,7 @@ struct ieee80211_sub_if_data *sdata; u8 rx_chains_static, rx_chains_dynamic; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); rx_chains_static = 1; rx_chains_dynamic = 1; @@ -1018,7 +1019,7 @@ if (WARN_ON(sdata->vif.type != NL80211_IFTYPE_AP)) return; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* Check that conf exists, even when clearing this function * must be called with the AP's channel context still there @@ -1027,7 +1028,7 @@ * to a channel context that has already been freed. */ conf = rcu_dereference_protected(link_conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); WARN_ON(!conf); if (clear) @@ -1051,11 +1052,9 @@ { struct ieee80211_local *local = link->sdata->local; - mutex_lock(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); __ieee80211_link_copy_chanctx_to_vlans(link, clear); - - mutex_unlock(&local->chanctx_mtx); } int ieee80211_link_unreserve_chanctx(struct ieee80211_link_data *link) @@ -1063,7 +1062,7 @@ struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_chanctx *ctx = link->reserved_chanctx; - lockdep_assert_held(&sdata->local->chanctx_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (WARN_ON(!ctx)) return -EINVAL; @@ -1103,7 +1102,7 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_chanctx *new_ctx, *curr_ctx, *ctx; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); curr_ctx = ieee80211_link_get_chanctx(link); if (curr_ctx && local->use_chanctx && !local->ops->switch_vif_chanctx) @@ -1201,12 +1200,12 @@ case NL80211_IFTYPE_AP: case NL80211_IFTYPE_MESH_POINT: case NL80211_IFTYPE_OCB: - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &link->csa_finalize_work); break; case NL80211_IFTYPE_STATION: - ieee80211_queue_work(&sdata->local->hw, - &link->u.mgd.chswitch_work); + wiphy_delayed_work_queue(sdata->local->hw.wiphy, + &link->u.mgd.chswitch_work, 0); break; case NL80211_IFTYPE_UNSPECIFIED: case NL80211_IFTYPE_AP_VLAN: @@ -1257,11 +1256,10 @@ struct ieee80211_vif_chanctx_switch vif_chsw[1] = {}; struct ieee80211_chanctx *old_ctx, *new_ctx; const struct cfg80211_chan_def *chandef; - u32 changed = 0; + u64 changed = 0; int err; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); new_ctx = link->reserved_chanctx; old_ctx = ieee80211_link_get_chanctx(link); @@ -1385,7 +1383,7 @@ struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_chanctx *old_ctx, *new_ctx; - lockdep_assert_held(&sdata->local->chanctx_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); new_ctx = link->reserved_chanctx; old_ctx = ieee80211_link_get_chanctx(link); @@ -1410,8 +1408,7 @@ { const struct cfg80211_chan_def *chandef; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); chandef = ieee80211_chanctx_reserved_chandef(local, new_ctx, NULL); if (WARN_ON(!chandef)) @@ -1432,8 +1429,7 @@ struct ieee80211_chanctx *ctx, *old_ctx; int i, err; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); vif_chsw = kcalloc(n_vifs, sizeof(vif_chsw[0]), GFP_KERNEL); if (!vif_chsw) @@ -1477,8 +1473,7 @@ struct ieee80211_chanctx *ctx; int err; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(ctx, &local->chanctx_list, list) { if (ctx->replace_state != IEEE80211_CHANCTX_REPLACES_OTHER) @@ -1518,8 +1513,7 @@ int err, n_assigned, n_reserved, n_ready; int n_ctx = 0, n_vifs_switch = 0, n_vifs_assign = 0, n_vifs_ctxless = 0; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* * If there are 2 independent pairs of channel contexts performing @@ -1653,7 +1647,7 @@ reserved_chanctx_list) { struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_bss_conf *link_conf = link->conf; - u32 changed = 0; + u64 changed = 0; if (!ieee80211_link_has_in_place_reservation(link)) continue; @@ -1778,10 +1772,10 @@ struct ieee80211_chanctx *ctx; bool use_reserved_switch = false; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); conf = rcu_dereference_protected(link_conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (!conf) return; @@ -1816,7 +1810,7 @@ u8 radar_detect_width = 0; int ret; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (sdata->vif.active_links && !(sdata->vif.active_links & BIT(link->link_id))) { @@ -1824,8 +1818,6 @@ return 0; } - mutex_lock(&local->chanctx_mtx); - ret = cfg80211_chandef_dfs_required(local->hw.wiphy, chandef, sdata->wdev.iftype); @@ -1867,7 +1859,6 @@ if (ret) link->radar_required = false; - mutex_unlock(&local->chanctx_mtx); return ret; } @@ -1879,8 +1870,7 @@ struct ieee80211_chanctx *old_ctx; int err; - lockdep_assert_held(&local->mtx); - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); new_ctx = link->reserved_chanctx; old_ctx = ieee80211_link_get_chanctx(link); @@ -1943,51 +1933,40 @@ struct ieee80211_chanctx_conf *conf; struct ieee80211_chanctx *ctx; const struct cfg80211_chan_def *compat; - int ret; + + lockdep_assert_wiphy(local->hw.wiphy); if (!cfg80211_chandef_usable(sdata->local->hw.wiphy, chandef, IEEE80211_CHAN_DISABLED)) return -EINVAL; - mutex_lock(&local->chanctx_mtx); - if (cfg80211_chandef_identical(chandef, &link_conf->chandef)) { - ret = 0; - goto out; - } + if (cfg80211_chandef_identical(chandef, &link_conf->chandef)) + return 0; if (chandef->width == NL80211_CHAN_WIDTH_20_NOHT || - link_conf->chandef.width == NL80211_CHAN_WIDTH_20_NOHT) { - ret = -EINVAL; - goto out; - } + link_conf->chandef.width == NL80211_CHAN_WIDTH_20_NOHT) + return -EINVAL; conf = rcu_dereference_protected(link_conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); - if (!conf) { - ret = -EINVAL; - goto out; - } + lockdep_is_held(&local->hw.wiphy->mtx)); + if (!conf) + return -EINVAL; ctx = container_of(conf, struct ieee80211_chanctx, conf); compat = cfg80211_chandef_compatible(&conf->def, chandef); - if (!compat) { - ret = -EINVAL; - goto out; - } + if (!compat) + return -EINVAL; switch (ctx->replace_state) { case IEEE80211_CHANCTX_REPLACE_NONE: - if (!ieee80211_chanctx_reserved_chandef(local, ctx, compat)) { - ret = -EBUSY; - goto out; - } + if (!ieee80211_chanctx_reserved_chandef(local, ctx, compat)) + return -EBUSY; break; case IEEE80211_CHANCTX_WILL_BE_REPLACED: /* TODO: Perhaps the bandwidth change could be treated as a * reservation itself? */ - ret = -EBUSY; - goto out; + return -EBUSY; case IEEE80211_CHANCTX_REPLACES_OTHER: /* channel context that is going to replace another channel * context doesn't really exist and shouldn't be assigned @@ -2001,23 +1980,18 @@ ieee80211_recalc_chanctx_chantype(local, ctx); *changed |= BSS_CHANGED_BANDWIDTH; - ret = 0; - out: - mutex_unlock(&local->chanctx_mtx); - return ret; + return 0; } void ieee80211_link_release_channel(struct ieee80211_link_data *link) { struct ieee80211_sub_if_data *sdata = link->sdata; - mutex_lock(&sdata->local->chanctx_mtx); - if (rcu_access_pointer(link->conf->chanctx_conf)) { - lockdep_assert_held(&sdata->local->mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + + if (rcu_access_pointer(link->conf->chanctx_conf)) __ieee80211_link_release_channel(link); } - mutex_unlock(&sdata->local->chanctx_mtx); -} void ieee80211_link_vlan_copy_chanctx(struct ieee80211_link_data *link) { @@ -2029,20 +2003,19 @@ struct ieee80211_sub_if_data *ap; struct ieee80211_chanctx_conf *conf; + lockdep_assert_wiphy(local->hw.wiphy); + if (WARN_ON(sdata->vif.type != NL80211_IFTYPE_AP_VLAN || !sdata->bss)) return; ap = container_of(sdata->bss, struct ieee80211_sub_if_data, u.ap); - mutex_lock(&local->chanctx_mtx); - rcu_read_lock(); ap_conf = rcu_dereference(ap->vif.link_conf[link_id]); conf = rcu_dereference_protected(ap_conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); rcu_assign_pointer(link_conf->chanctx_conf, conf); rcu_read_unlock(); - mutex_unlock(&local->chanctx_mtx); } void ieee80211_iter_chan_contexts_atomic( diff -ruw linux-6.4/net/mac80211/debug.h linux-6.4-fbx/net/mac80211/debug.h --- linux-6.4/net/mac80211/debug.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/debug.h 2023-11-07 13:38:44.074257019 +0100 @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Portions - * Copyright (C) 2022 Intel Corporation + * Copyright (C) 2022 - 2023 Intel Corporation */ #ifndef __MAC80211_DEBUG_H #define __MAC80211_DEBUG_H @@ -136,7 +136,7 @@ #define link_info(link, fmt, ...) \ do { \ - if ((link)->sdata->vif.valid_links) \ + if (ieee80211_vif_is_mld(&(link)->sdata->vif)) \ _sdata_info((link)->sdata, "[link %d] " fmt, \ (link)->link_id, \ ##__VA_ARGS__); \ @@ -145,7 +145,7 @@ } while (0) #define link_err(link, fmt, ...) \ do { \ - if ((link)->sdata->vif.valid_links) \ + if (ieee80211_vif_is_mld(&(link)->sdata->vif)) \ _sdata_err((link)->sdata, "[link %d] " fmt, \ (link)->link_id, \ ##__VA_ARGS__); \ @@ -154,7 +154,7 @@ } while (0) #define link_dbg(link, fmt, ...) \ do { \ - if ((link)->sdata->vif.valid_links) \ + if (ieee80211_vif_is_mld(&(link)->sdata->vif)) \ _sdata_dbg(1, (link)->sdata, "[link %d] " fmt, \ (link)->link_id, \ ##__VA_ARGS__); \ diff -ruw linux-6.4/net/mac80211/debugfs.c linux-6.4-fbx/net/mac80211/debugfs.c --- linux-6.4/net/mac80211/debugfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/debugfs.c 2023-11-07 13:38:44.074257019 +0100 @@ -4,7 +4,7 @@ * * Copyright 2007 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH - * Copyright (C) 2018 - 2019, 2021-2022 Intel Corporation + * Copyright (C) 2018 - 2019, 2021-2023 Intel Corporation */ #include @@ -288,10 +288,10 @@ q_limit_low_old = local->aql_txq_limit_low[ac]; q_limit_high_old = local->aql_txq_limit_high[ac]; + wiphy_lock(local->hw.wiphy); local->aql_txq_limit_low[ac] = q_limit_low; local->aql_txq_limit_high[ac] = q_limit_high; - mutex_lock(&local->sta_mtx); list_for_each_entry(sta, &local->sta_list, list) { /* If a sta has customized queue limits, keep it */ if (sta->airtime[ac].aql_limit_low == q_limit_low_old && @@ -300,7 +300,8 @@ sta->airtime[ac].aql_limit_high = q_limit_high; } } - mutex_unlock(&local->sta_mtx); + wiphy_unlock(local->hw.wiphy); + return count; } @@ -496,6 +497,7 @@ FLAG(SUPPORTS_CONC_MON_RX_DECAP), FLAG(DETECTS_COLOR_COLLISION), FLAG(MLO_MCAST_MULTI_LINK_TX), + FLAG(APVLAN_NEED_MCAST_TO_UCAST), #undef FLAG }; @@ -594,9 +596,9 @@ char buf[20]; int res; - rtnl_lock(); + wiphy_lock(local->hw.wiphy); res = drv_get_stats(local, &stats); - rtnl_unlock(); + wiphy_unlock(local->hw.wiphy); if (res) return res; res = printvalue(&stats, buf, sizeof(buf)); diff -ruw linux-6.4/net/mac80211/debugfs_key.c linux-6.4-fbx/net/mac80211/debugfs_key.c --- linux-6.4/net/mac80211/debugfs_key.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/debugfs_key.c 2023-11-07 13:38:44.074257019 +0100 @@ -4,7 +4,7 @@ * Copyright (c) 2006 Jiri Benc * Copyright 2007 Johannes Berg * Copyright (C) 2015 Intel Deutschland GmbH - * Copyright (C) 2021-2022 Intel Corporation + * Copyright (C) 2021-2023 Intel Corporation */ #include @@ -378,13 +378,13 @@ if (!sdata->vif.debugfs_dir) return; - lockdep_assert_held(&sdata->local->key_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); debugfs_remove(sdata->debugfs.default_unicast_key); sdata->debugfs.default_unicast_key = NULL; if (sdata->default_unicast_key) { - key = key_mtx_dereference(sdata->local, + key = wiphy_dereference(sdata->local->hw.wiphy, sdata->default_unicast_key); sprintf(buf, "../keys/%d", key->debugfs.cnt); sdata->debugfs.default_unicast_key = @@ -396,7 +396,7 @@ sdata->debugfs.default_multicast_key = NULL; if (sdata->deflink.default_multicast_key) { - key = key_mtx_dereference(sdata->local, + key = wiphy_dereference(sdata->local->hw.wiphy, sdata->deflink.default_multicast_key); sprintf(buf, "../keys/%d", key->debugfs.cnt); sdata->debugfs.default_multicast_key = @@ -413,7 +413,7 @@ if (!sdata->vif.debugfs_dir) return; - key = key_mtx_dereference(sdata->local, + key = wiphy_dereference(sdata->local->hw.wiphy, sdata->deflink.default_mgmt_key); if (key) { sprintf(buf, "../keys/%d", key->debugfs.cnt); @@ -442,7 +442,7 @@ if (!sdata->vif.debugfs_dir) return; - key = key_mtx_dereference(sdata->local, + key = wiphy_dereference(sdata->local->hw.wiphy, sdata->deflink.default_beacon_key); if (key) { sprintf(buf, "../keys/%d", key->debugfs.cnt); diff -ruw linux-6.4/net/mac80211/debugfs_netdev.c linux-6.4-fbx/net/mac80211/debugfs_netdev.c --- linux-6.4/net/mac80211/debugfs_netdev.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/debugfs_netdev.c 2023-11-07 13:38:44.074257019 +0100 @@ -2,7 +2,7 @@ /* * Copyright (c) 2006 Jiri Benc * Copyright 2007 Johannes Berg - * Copyright (C) 2020-2022 Intel Corporation + * Copyright (C) 2020-2023 Intel Corporation */ #include @@ -22,18 +22,18 @@ #include "debugfs_netdev.h" #include "driver-ops.h" -static ssize_t ieee80211_if_read( - void *data, +static ssize_t ieee80211_if_read_sdata( + struct ieee80211_sub_if_data *sdata, char __user *userbuf, size_t count, loff_t *ppos, - ssize_t (*format)(const void *, char *, int)) + ssize_t (*format)(const struct ieee80211_sub_if_data *sdata, char *, int)) { char buf[200]; ssize_t ret = -EINVAL; - read_lock(&dev_base_lock); - ret = (*format)(data, buf, sizeof(buf)); - read_unlock(&dev_base_lock); + wiphy_lock(sdata->local->hw.wiphy); + ret = (*format)(sdata, buf, sizeof(buf)); + wiphy_unlock(sdata->local->hw.wiphy); if (ret >= 0) ret = simple_read_from_buffer(userbuf, count, ppos, buf, ret); @@ -41,11 +41,11 @@ return ret; } -static ssize_t ieee80211_if_write( - void *data, +static ssize_t ieee80211_if_write_sdata( + struct ieee80211_sub_if_data *sdata, const char __user *userbuf, size_t count, loff_t *ppos, - ssize_t (*write)(void *, const char *, int)) + ssize_t (*write)(struct ieee80211_sub_if_data *sdata, const char *, int)) { char buf[64]; ssize_t ret; @@ -57,9 +57,51 @@ return -EFAULT; buf[count] = '\0'; - rtnl_lock(); - ret = (*write)(data, buf, count); - rtnl_unlock(); + wiphy_lock(sdata->local->hw.wiphy); + ret = (*write)(sdata, buf, count); + wiphy_unlock(sdata->local->hw.wiphy); + + return ret; +} + +static ssize_t ieee80211_if_read_link( + struct ieee80211_link_data *link, + char __user *userbuf, + size_t count, loff_t *ppos, + ssize_t (*format)(const struct ieee80211_link_data *link, char *, int)) +{ + char buf[200]; + ssize_t ret = -EINVAL; + + wiphy_lock(link->sdata->local->hw.wiphy); + ret = (*format)(link, buf, sizeof(buf)); + wiphy_unlock(link->sdata->local->hw.wiphy); + + if (ret >= 0) + ret = simple_read_from_buffer(userbuf, count, ppos, buf, ret); + + return ret; +} + +static ssize_t ieee80211_if_write_link( + struct ieee80211_link_data *link, + const char __user *userbuf, + size_t count, loff_t *ppos, + ssize_t (*write)(struct ieee80211_link_data *link, const char *, int)) +{ + char buf[64]; + ssize_t ret; + + if (count >= sizeof(buf)) + return -E2BIG; + + if (copy_from_user(buf, userbuf, count)) + return -EFAULT; + buf[count] = '\0'; + + wiphy_lock(link->sdata->local->hw.wiphy); + ret = (*write)(link, buf, count); + wiphy_unlock(link->sdata->local->hw.wiphy); return ret; } @@ -126,41 +168,37 @@ .llseek = generic_file_llseek, \ } -#define _IEEE80211_IF_FILE_R_FN(name, type) \ +#define _IEEE80211_IF_FILE_R_FN(name) \ static ssize_t ieee80211_if_read_##name(struct file *file, \ char __user *userbuf, \ size_t count, loff_t *ppos) \ { \ - ssize_t (*fn)(const void *, char *, int) = (void *) \ - ((ssize_t (*)(const type, char *, int)) \ + return ieee80211_if_read_sdata(file->private_data, \ + userbuf, count, ppos, \ ieee80211_if_fmt_##name); \ - return ieee80211_if_read(file->private_data, \ - userbuf, count, ppos, fn); \ } -#define _IEEE80211_IF_FILE_W_FN(name, type) \ +#define _IEEE80211_IF_FILE_W_FN(name) \ static ssize_t ieee80211_if_write_##name(struct file *file, \ const char __user *userbuf, \ size_t count, loff_t *ppos) \ { \ - ssize_t (*fn)(void *, const char *, int) = (void *) \ - ((ssize_t (*)(type, const char *, int)) \ + return ieee80211_if_write_sdata(file->private_data, userbuf, \ + count, ppos, \ ieee80211_if_parse_##name); \ - return ieee80211_if_write(file->private_data, userbuf, count, \ - ppos, fn); \ } #define IEEE80211_IF_FILE_R(name) \ - _IEEE80211_IF_FILE_R_FN(name, struct ieee80211_sub_if_data *) \ + _IEEE80211_IF_FILE_R_FN(name) \ _IEEE80211_IF_FILE_OPS(name, ieee80211_if_read_##name, NULL) #define IEEE80211_IF_FILE_W(name) \ - _IEEE80211_IF_FILE_W_FN(name, struct ieee80211_sub_if_data *) \ + _IEEE80211_IF_FILE_W_FN(name) \ _IEEE80211_IF_FILE_OPS(name, NULL, ieee80211_if_write_##name) #define IEEE80211_IF_FILE_RW(name) \ - _IEEE80211_IF_FILE_R_FN(name, struct ieee80211_sub_if_data *) \ - _IEEE80211_IF_FILE_W_FN(name, struct ieee80211_sub_if_data *) \ + _IEEE80211_IF_FILE_R_FN(name) \ + _IEEE80211_IF_FILE_W_FN(name) \ _IEEE80211_IF_FILE_OPS(name, ieee80211_if_read_##name, \ ieee80211_if_write_##name) @@ -168,18 +206,37 @@ IEEE80211_IF_FMT_##format(name, struct ieee80211_sub_if_data, field) \ IEEE80211_IF_FILE_R(name) -/* Same but with a link_ prefix in the ops variable name and different type */ +#define _IEEE80211_IF_LINK_R_FN(name) \ +static ssize_t ieee80211_if_read_##name(struct file *file, \ + char __user *userbuf, \ + size_t count, loff_t *ppos) \ +{ \ + return ieee80211_if_read_link(file->private_data, \ + userbuf, count, ppos, \ + ieee80211_if_fmt_##name); \ +} + +#define _IEEE80211_IF_LINK_W_FN(name) \ +static ssize_t ieee80211_if_write_##name(struct file *file, \ + const char __user *userbuf, \ + size_t count, loff_t *ppos) \ +{ \ + return ieee80211_if_write_link(file->private_data, userbuf, \ + count, ppos, \ + ieee80211_if_parse_##name); \ +} + #define IEEE80211_IF_LINK_FILE_R(name) \ - _IEEE80211_IF_FILE_R_FN(name, struct ieee80211_link_data *) \ + _IEEE80211_IF_LINK_R_FN(name) \ _IEEE80211_IF_FILE_OPS(link_##name, ieee80211_if_read_##name, NULL) #define IEEE80211_IF_LINK_FILE_W(name) \ - _IEEE80211_IF_FILE_W_FN(name) \ + _IEEE80211_IF_LINK_W_FN(name) \ _IEEE80211_IF_FILE_OPS(link_##name, NULL, ieee80211_if_write_##name) #define IEEE80211_IF_LINK_FILE_RW(name) \ - _IEEE80211_IF_FILE_R_FN(name, struct ieee80211_link_data *) \ - _IEEE80211_IF_FILE_W_FN(name, struct ieee80211_link_data *) \ + _IEEE80211_IF_LINK_R_FN(name) \ + _IEEE80211_IF_LINK_W_FN(name) \ _IEEE80211_IF_FILE_OPS(link_##name, ieee80211_if_read_##name, \ ieee80211_if_write_##name) @@ -265,7 +322,12 @@ { struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_local *local = sdata->local; - int err; + + /* The driver indicated that EML is enabled for the interface, thus do + * not allow to override the SMPS state. + */ + if (sdata->vif.driver_flags & IEEE80211_VIF_EML_ACTIVE) + return -EOPNOTSUPP; if (!(local->hw.wiphy->features & NL80211_FEATURE_STATIC_SMPS) && smps_mode == IEEE80211_SMPS_STATIC) @@ -280,11 +342,7 @@ if (sdata->vif.type != NL80211_IFTYPE_STATION) return -EOPNOTSUPP; - sdata_lock(sdata); - err = __ieee80211_request_smps_mgd(link->sdata, link, smps_mode); - sdata_unlock(sdata); - - return err; + return __ieee80211_request_smps_mgd(link->sdata, link, smps_mode); } static const char *smps_modes[IEEE80211_SMPS_NUM_MODES] = { @@ -356,16 +414,13 @@ case NL80211_IFTYPE_STATION: fc |= cpu_to_le16(IEEE80211_FCTL_TODS); /* BSSID SA DA */ - sdata_lock(sdata); if (!sdata->u.mgd.associated) { - sdata_unlock(sdata); dev_kfree_skb(skb); return -ENOTCONN; } memcpy(hdr->addr1, sdata->deflink.u.mgd.bssid, ETH_ALEN); memcpy(hdr->addr2, sdata->vif.addr, ETH_ALEN); memcpy(hdr->addr3, addr, ETH_ALEN); - sdata_unlock(sdata); break; default: dev_kfree_skb(skb); @@ -690,6 +745,19 @@ debugfs_create_file(#name, mode, sdata->vif.debugfs_dir, \ sdata, &name##_ops) +#define DEBUGFS_ADD_X(_bits, _name, _mode) \ + debugfs_create_x##_bits(#_name, _mode, sdata->vif.debugfs_dir, \ + &sdata->vif._name) + +#define DEBUGFS_ADD_X8(_name, _mode) \ + DEBUGFS_ADD_X(8, _name, _mode) + +#define DEBUGFS_ADD_X16(_name, _mode) \ + DEBUGFS_ADD_X(16, _name, _mode) + +#define DEBUGFS_ADD_X32(_name, _mode) \ + DEBUGFS_ADD_X(32, _name, _mode) + #define DEBUGFS_ADD(name) DEBUGFS_ADD_MODE(name, 0400) static void add_common_files(struct ieee80211_sub_if_data *sdata) @@ -717,8 +785,9 @@ DEBUGFS_ADD_MODE(uapsd_queues, 0600); DEBUGFS_ADD_MODE(uapsd_max_sp_len, 0600); DEBUGFS_ADD_MODE(tdls_wider_bw, 0600); - DEBUGFS_ADD_MODE(valid_links, 0200); + DEBUGFS_ADD_MODE(valid_links, 0400); DEBUGFS_ADD_MODE(active_links, 0600); + DEBUGFS_ADD_X16(dormant_links, 0400); } static void add_ap_files(struct ieee80211_sub_if_data *sdata) @@ -868,18 +937,20 @@ } } -void ieee80211_debugfs_add_netdev(struct ieee80211_sub_if_data *sdata) +void ieee80211_debugfs_add_netdev(struct ieee80211_sub_if_data *sdata, + bool mld_vif) { char buf[10+IFNAMSIZ]; sprintf(buf, "netdev:%s", sdata->name); sdata->vif.debugfs_dir = debugfs_create_dir(buf, sdata->local->hw.wiphy->debugfsdir); + /* deflink also has this */ + sdata->deflink.debugfs_dir = sdata->vif.debugfs_dir; sdata->debugfs.subdir_stations = debugfs_create_dir("stations", sdata->vif.debugfs_dir); add_files(sdata); - - if (!(sdata->local->hw.wiphy->flags & WIPHY_FLAG_SUPPORTS_MLO)) + if (!mld_vif) add_link_files(&sdata->deflink, sdata->vif.debugfs_dir); } @@ -907,11 +978,21 @@ debugfs_rename(dir->d_parent, dir, dir->d_parent, buf); } +void ieee80211_debugfs_recreate_netdev(struct ieee80211_sub_if_data *sdata, + bool mld_vif) +{ + ieee80211_debugfs_remove_netdev(sdata); + ieee80211_debugfs_add_netdev(sdata, mld_vif); + drv_vif_add_debugfs(sdata->local, sdata); + if (!mld_vif) + ieee80211_link_debugfs_drv_add(&sdata->deflink); +} + void ieee80211_link_debugfs_add(struct ieee80211_link_data *link) { char link_dir_name[10]; - if (WARN_ON(!link->sdata->vif.debugfs_dir)) + if (WARN_ON(!link->sdata->vif.debugfs_dir || link->debugfs_dir)) return; /* For now, this should not be called for non-MLO capable drivers */ @@ -948,7 +1029,8 @@ void ieee80211_link_debugfs_drv_add(struct ieee80211_link_data *link) { - if (WARN_ON(!link->debugfs_dir)) + if (link->sdata->vif.type == NL80211_IFTYPE_MONITOR || + WARN_ON(!link->debugfs_dir)) return; drv_link_add_debugfs(link->sdata->local, link->sdata, diff -ruw linux-6.4/net/mac80211/debugfs_netdev.h linux-6.4-fbx/net/mac80211/debugfs_netdev.h --- linux-6.4/net/mac80211/debugfs_netdev.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/debugfs_netdev.h 2023-11-07 13:38:44.074257019 +0100 @@ -1,4 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ +/* + * Portions: + * Copyright (C) 2023 Intel Corporation + */ /* routines exported for debugfs handling */ #ifndef __IEEE80211_DEBUGFS_NETDEV_H @@ -7,9 +11,12 @@ #include "ieee80211_i.h" #ifdef CONFIG_MAC80211_DEBUGFS -void ieee80211_debugfs_add_netdev(struct ieee80211_sub_if_data *sdata); +void ieee80211_debugfs_add_netdev(struct ieee80211_sub_if_data *sdata, + bool mld_vif); void ieee80211_debugfs_remove_netdev(struct ieee80211_sub_if_data *sdata); void ieee80211_debugfs_rename_netdev(struct ieee80211_sub_if_data *sdata); +void ieee80211_debugfs_recreate_netdev(struct ieee80211_sub_if_data *sdata, + bool mld_vif); void ieee80211_link_debugfs_add(struct ieee80211_link_data *link); void ieee80211_link_debugfs_remove(struct ieee80211_link_data *link); @@ -18,7 +25,7 @@ void ieee80211_link_debugfs_drv_remove(struct ieee80211_link_data *link); #else static inline void ieee80211_debugfs_add_netdev( - struct ieee80211_sub_if_data *sdata) + struct ieee80211_sub_if_data *sdata, bool mld_vif) {} static inline void ieee80211_debugfs_remove_netdev( struct ieee80211_sub_if_data *sdata) @@ -26,7 +33,9 @@ static inline void ieee80211_debugfs_rename_netdev( struct ieee80211_sub_if_data *sdata) {} - +static inline void ieee80211_debugfs_recreate_netdev( + struct ieee80211_sub_if_data *sdata, bool mld_vif) +{} static inline void ieee80211_link_debugfs_add(struct ieee80211_link_data *link) {} static inline void ieee80211_link_debugfs_remove(struct ieee80211_link_data *link) diff -ruw linux-6.4/net/mac80211/debugfs_sta.c linux-6.4-fbx/net/mac80211/debugfs_sta.c --- linux-6.4/net/mac80211/debugfs_sta.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/debugfs_sta.c 2023-11-07 13:38:44.074257019 +0100 @@ -5,7 +5,7 @@ * Copyright 2007 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright(c) 2016 Intel Deutschland GmbH - * Copyright (C) 2018 - 2022 Intel Corporation + * Copyright (C) 2018 - 2023 Intel Corporation */ #include @@ -420,6 +420,7 @@ if (ret || tid >= IEEE80211_NUM_TIDS) return -EINVAL; + wiphy_lock(sta->local->hw.wiphy); if (tx) { if (start) ret = ieee80211_start_tx_ba_session(&sta->sta, tid, @@ -431,6 +432,7 @@ 3, true); ret = 0; } + wiphy_unlock(sta->local->hw.wiphy); return ret ?: count; } @@ -1035,6 +1037,190 @@ } LINK_STA_OPS(he_capa); +static ssize_t link_sta_eht_capa_read(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + char *buf, *p; + size_t buf_sz = PAGE_SIZE; + struct link_sta_info *link_sta = file->private_data; + struct ieee80211_sta_eht_cap *bec = &link_sta->pub->eht_cap; + struct ieee80211_eht_cap_elem_fixed *fixed = &bec->eht_cap_elem; + struct ieee80211_eht_mcs_nss_supp *nss = &bec->eht_mcs_nss_supp; + u8 *cap; + int i; + ssize_t ret; + static const char *mcs_desc[] = { "0-7", "8-9", "10-11", "12-13"}; + + buf = kmalloc(buf_sz, GFP_KERNEL); + if (!buf) + return -ENOMEM; + p = buf; + + p += scnprintf(p, buf_sz + buf - p, "EHT %ssupported\n", + bec->has_eht ? "" : "not "); + if (!bec->has_eht) + goto out; + + p += scnprintf(p, buf_sz + buf - p, + "MAC-CAP: %#.2x %#.2x\n", + fixed->mac_cap_info[0], fixed->mac_cap_info[1]); + p += scnprintf(p, buf_sz + buf - p, + "PHY-CAP: %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x %#.2x\n", + fixed->phy_cap_info[0], fixed->phy_cap_info[1], + fixed->phy_cap_info[2], fixed->phy_cap_info[3], + fixed->phy_cap_info[4], fixed->phy_cap_info[5], + fixed->phy_cap_info[6], fixed->phy_cap_info[7], + fixed->phy_cap_info[8]); + +#define PRINT(fmt, ...) \ + p += scnprintf(p, buf_sz + buf - p, "\t\t" fmt "\n", \ + ##__VA_ARGS__) + +#define PFLAG(t, n, a, b) \ + do { \ + if (cap[n] & IEEE80211_EHT_##t##_CAP##n##_##a) \ + PRINT("%s", b); \ + } while (0) + + cap = fixed->mac_cap_info; + PFLAG(MAC, 0, EPCS_PRIO_ACCESS, "EPCS-PRIO-ACCESS"); + PFLAG(MAC, 0, OM_CONTROL, "OM-CONTROL"); + PFLAG(MAC, 0, TRIG_TXOP_SHARING_MODE1, "TRIG-TXOP-SHARING-MODE1"); + PFLAG(MAC, 0, TRIG_TXOP_SHARING_MODE2, "TRIG-TXOP-SHARING-MODE2"); + PFLAG(MAC, 0, RESTRICTED_TWT, "RESTRICTED-TWT"); + PFLAG(MAC, 0, SCS_TRAFFIC_DESC, "SCS-TRAFFIC-DESC"); + switch ((cap[0] & 0xc0) >> 6) { + case IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_3895: + PRINT("MAX-MPDU-LEN: 3985"); + break; + case IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991: + PRINT("MAX-MPDU-LEN: 7991"); + break; + case IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454: + PRINT("MAX-MPDU-LEN: 11454"); + break; + } + + cap = fixed->phy_cap_info; + PFLAG(PHY, 0, 320MHZ_IN_6GHZ, "320MHZ-IN-6GHZ"); + PFLAG(PHY, 0, 242_TONE_RU_GT20MHZ, "242-TONE-RU-GT20MHZ"); + PFLAG(PHY, 0, NDP_4_EHT_LFT_32_GI, "NDP-4-EHT-LFT-32-GI"); + PFLAG(PHY, 0, PARTIAL_BW_UL_MU_MIMO, "PARTIAL-BW-UL-MU-MIMO"); + PFLAG(PHY, 0, SU_BEAMFORMER, "SU-BEAMFORMER"); + PFLAG(PHY, 0, SU_BEAMFORMEE, "SU-BEAMFORMEE"); + i = cap[0] >> 7; + i |= (cap[1] & 0x3) << 1; + PRINT("BEAMFORMEE-80-NSS: %i", i); + PRINT("BEAMFORMEE-160-NSS: %i", (cap[1] >> 2) & 0x7); + PRINT("BEAMFORMEE-320-NSS: %i", (cap[1] >> 5) & 0x7); + PRINT("SOUNDING-DIM-80-NSS: %i", (cap[2] & 0x7)); + PRINT("SOUNDING-DIM-160-NSS: %i", (cap[2] >> 3) & 0x7); + i = cap[2] >> 6; + i |= (cap[3] & 0x1) << 3; + PRINT("SOUNDING-DIM-320-NSS: %i", i); + + PFLAG(PHY, 3, NG_16_SU_FEEDBACK, "NG-16-SU-FEEDBACK"); + PFLAG(PHY, 3, NG_16_MU_FEEDBACK, "NG-16-MU-FEEDBACK"); + PFLAG(PHY, 3, CODEBOOK_4_2_SU_FDBK, "CODEBOOK-4-2-SU-FDBK"); + PFLAG(PHY, 3, CODEBOOK_7_5_MU_FDBK, "CODEBOOK-7-5-MU-FDBK"); + PFLAG(PHY, 3, TRIG_SU_BF_FDBK, "TRIG-SU-BF-FDBK"); + PFLAG(PHY, 3, TRIG_MU_BF_PART_BW_FDBK, "TRIG-MU-BF-PART-BW-FDBK"); + PFLAG(PHY, 3, TRIG_CQI_FDBK, "TRIG-CQI-FDBK"); + + PFLAG(PHY, 4, PART_BW_DL_MU_MIMO, "PART-BW-DL-MU-MIMO"); + PFLAG(PHY, 4, PSR_SR_SUPP, "PSR-SR-SUPP"); + PFLAG(PHY, 4, POWER_BOOST_FACT_SUPP, "POWER-BOOST-FACT-SUPP"); + PFLAG(PHY, 4, EHT_MU_PPDU_4_EHT_LTF_08_GI, "EHT-MU-PPDU-4-EHT-LTF-08-GI"); + PRINT("MAX_NC: %i", cap[4] >> 4); + + PFLAG(PHY, 5, NON_TRIG_CQI_FEEDBACK, "NON-TRIG-CQI-FEEDBACK"); + PFLAG(PHY, 5, TX_LESS_242_TONE_RU_SUPP, "TX-LESS-242-TONE-RU-SUPP"); + PFLAG(PHY, 5, RX_LESS_242_TONE_RU_SUPP, "RX-LESS-242-TONE-RU-SUPP"); + PFLAG(PHY, 5, PPE_THRESHOLD_PRESENT, "PPE_THRESHOLD_PRESENT"); + switch (cap[5] >> 4 & 0x3) { + case IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_0US: + PRINT("NOMINAL_PKT_PAD: 0us"); + break; + case IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_8US: + PRINT("NOMINAL_PKT_PAD: 8us"); + break; + case IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US: + PRINT("NOMINAL_PKT_PAD: 16us"); + break; + case IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US: + PRINT("NOMINAL_PKT_PAD: 20us"); + break; + } + i = cap[5] >> 6; + i |= cap[6] & 0x7; + PRINT("MAX-NUM-SUPP-EHT-LTF: %i", i); + PFLAG(PHY, 5, SUPP_EXTRA_EHT_LTF, "SUPP-EXTRA-EHT-LTF"); + + i = (cap[6] >> 3) & 0xf; + PRINT("MCS15-SUPP-MASK: %i", i); + PFLAG(PHY, 6, EHT_DUP_6GHZ_SUPP, "EHT-DUP-6GHZ-SUPP"); + + PFLAG(PHY, 7, 20MHZ_STA_RX_NDP_WIDER_BW, "20MHZ-STA-RX-NDP-WIDER-BW"); + PFLAG(PHY, 7, NON_OFDMA_UL_MU_MIMO_80MHZ, "NON-OFDMA-UL-MU-MIMO-80MHZ"); + PFLAG(PHY, 7, NON_OFDMA_UL_MU_MIMO_160MHZ, "NON-OFDMA-UL-MU-MIMO-160MHZ"); + PFLAG(PHY, 7, NON_OFDMA_UL_MU_MIMO_320MHZ, "NON-OFDMA-UL-MU-MIMO-320MHZ"); + PFLAG(PHY, 7, MU_BEAMFORMER_80MHZ, "MU-BEAMFORMER-80MHZ"); + PFLAG(PHY, 7, MU_BEAMFORMER_160MHZ, "MU-BEAMFORMER-160MHZ"); + PFLAG(PHY, 7, MU_BEAMFORMER_320MHZ, "MU-BEAMFORMER-320MHZ"); + PFLAG(PHY, 7, TB_SOUNDING_FDBK_RATE_LIMIT, "TB-SOUNDING-FDBK-RATE-LIMIT"); + + PFLAG(PHY, 8, RX_1024QAM_WIDER_BW_DL_OFDMA, "RX-1024QAM-WIDER-BW-DL-OFDMA"); + PFLAG(PHY, 8, RX_4096QAM_WIDER_BW_DL_OFDMA, "RX-4096QAM-WIDER-BW-DL-OFDMA"); + +#undef PFLAG + + PRINT(""); /* newline */ + if (!(link_sta->pub->he_cap.he_cap_elem.phy_cap_info[0] & + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) { + u8 *mcs_vals = (u8 *)(&nss->only_20mhz); + + for (i = 0; i < 4; i++) + PRINT("EHT bw=20 MHz, max NSS for MCS %s: Rx=%u, Tx=%u", + mcs_desc[i], + mcs_vals[i] & 0xf, mcs_vals[i] >> 4); + } else { + u8 *mcs_vals = (u8 *)(&nss->bw._80); + + for (i = 0; i < 3; i++) + PRINT("EHT bw <= 80 MHz, max NSS for MCS %s: Rx=%u, Tx=%u", + mcs_desc[i + 1], + mcs_vals[i] & 0xf, mcs_vals[i] >> 4); + + mcs_vals = (u8 *)(&nss->bw._160); + for (i = 0; i < 3; i++) + PRINT("EHT bw <= 160 MHz, max NSS for MCS %s: Rx=%u, Tx=%u", + mcs_desc[i + 1], + mcs_vals[i] & 0xf, mcs_vals[i] >> 4); + + mcs_vals = (u8 *)(&nss->bw._320); + for (i = 0; i < 3; i++) + PRINT("EHT bw <= 320 MHz, max NSS for MCS %s: Rx=%u, Tx=%u", + mcs_desc[i + 1], + mcs_vals[i] & 0xf, mcs_vals[i] >> 4); + } + + if (cap[5] & IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT) { + u8 ppe_size = ieee80211_eht_ppe_size(bec->eht_ppe_thres[0], cap); + + p += scnprintf(p, buf_sz + buf - p, "EHT PPE Thresholds: "); + for (i = 0; i < ppe_size; i++) + p += scnprintf(p, buf_sz + buf - p, "0x%02x ", + bec->eht_ppe_thres[i]); + PRINT(""); /* newline */ + } + +out: + ret = simple_read_from_buffer(userbuf, count, ppos, buf, p - buf); + kfree(buf); + return ret; +} +LINK_STA_OPS(eht_capa); + #define DEBUGFS_ADD(name) \ debugfs_create_file(#name, 0400, \ sta->debugfs_dir, sta, &sta_ ##name## _ops) @@ -1128,6 +1314,7 @@ DEBUGFS_ADD(ht_capa); DEBUGFS_ADD(vht_capa); DEBUGFS_ADD(he_capa); + DEBUGFS_ADD(eht_capa); DEBUGFS_ADD_COUNTER(rx_duplicates, rx_stats.num_duplicates); DEBUGFS_ADD_COUNTER(rx_fragments, rx_stats.fragments); diff -ruw linux-6.4/net/mac80211/driver-ops.c linux-6.4-fbx/net/mac80211/driver-ops.c --- linux-6.4/net/mac80211/driver-ops.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/driver-ops.c 2023-11-07 13:38:44.074257019 +0100 @@ -15,6 +15,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(local->started)) return -EALREADY; @@ -35,6 +36,7 @@ void drv_stop(struct ieee80211_local *local) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(!local->started)) return; @@ -52,12 +54,37 @@ local->started = false; } +int drv_get_powered(struct ieee80211_local *local, bool *up, bool *busy) +{ + int ret = -EOPNOTSUPP; + + might_sleep(); + + if (local->ops->get_powered) + ret = local->ops->get_powered(&local->hw, up, busy); + + return ret; +} + +int drv_set_powered(struct ieee80211_local *local) +{ + int ret = -EOPNOTSUPP; + + might_sleep(); + + if (local->ops->set_powered) + ret = local->ops->set_powered(&local->hw); + + return ret; +} + int drv_add_interface(struct ieee80211_local *local, struct ieee80211_sub_if_data *sdata) { int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(sdata->vif.type == NL80211_IFTYPE_AP_VLAN || (sdata->vif.type == NL80211_IFTYPE_MONITOR && @@ -69,10 +96,18 @@ ret = local->ops->add_interface(&local->hw, &sdata->vif); trace_drv_return_int(local, ret); - if (ret == 0) + if (ret) + return ret; + sdata->flags |= IEEE80211_SDATA_IN_DRIVER; - return ret; + if (!local->in_reconfig) { + drv_vif_add_debugfs(local, sdata); + /* initially vif is not MLD */ + ieee80211_link_debugfs_drv_add(&sdata->deflink); + } + + return 0; } int drv_change_interface(struct ieee80211_local *local, @@ -82,6 +117,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -96,6 +132,7 @@ struct ieee80211_sub_if_data *sdata) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -116,6 +153,7 @@ int ret = 0; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -149,6 +187,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -190,6 +229,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -223,6 +263,7 @@ u64 ret = -1ULL; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return ret; @@ -239,6 +280,7 @@ u64 tsf) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -254,6 +296,7 @@ s64 offset) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -268,6 +311,7 @@ struct ieee80211_sub_if_data *sdata) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -285,7 +329,9 @@ { int ret = 0; - drv_verify_link_exists(sdata, link_conf); + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) return -EIO; @@ -312,8 +358,8 @@ struct ieee80211_chanctx *ctx) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); - drv_verify_link_exists(sdata, link_conf); if (!check_sdata_in_driver(sdata)) return; @@ -340,6 +386,7 @@ int i; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!local->ops->switch_vif_chanctx) return -EOPNOTSUPP; @@ -392,9 +439,7 @@ int ret = -EOPNOTSUPP; might_sleep(); - - if (!sdata) - return -EIO; + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -416,6 +461,7 @@ int link_id, u64 changed) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON_ONCE(changed & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED) && @@ -429,7 +475,8 @@ sdata->vif.type == NL80211_IFTYPE_NAN || (sdata->vif.type == NL80211_IFTYPE_MONITOR && !sdata->vif.bss_conf.mu_mimo_owner && - !(changed & BSS_CHANGED_TXPOWER)))) + !(changed & (BSS_CHANGED_TXPOWER | + BSS_CHANGED_QOS))))) return; if (!check_sdata_in_driver(sdata)) @@ -458,6 +505,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -485,6 +533,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -510,11 +559,14 @@ if (ret) return ret; - for_each_set_bit(link_id, &links_to_add, IEEE80211_MLD_MAX_NUM_LINKS) { + if (!local->in_reconfig) { + for_each_set_bit(link_id, &links_to_add, + IEEE80211_MLD_MAX_NUM_LINKS) { link = rcu_access_pointer(sdata->link[link_id]); ieee80211_link_debugfs_drv_add(link); } + } return 0; } @@ -532,6 +584,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -547,7 +600,7 @@ for_each_set_bit(link_id, &links_to_rem, IEEE80211_MLD_MAX_NUM_LINKS) { link_sta = rcu_dereference_protected(info->link[link_id], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); ieee80211_link_sta_debugfs_drv_remove(link_sta); } @@ -563,7 +616,7 @@ for_each_set_bit(link_id, &links_to_add, IEEE80211_MLD_MAX_NUM_LINKS) { link_sta = rcu_dereference_protected(info->link[link_id], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); ieee80211_link_sta_debugfs_drv_add(link_sta); } diff -ruw linux-6.4/net/mac80211/driver-ops.h linux-6.4-fbx/net/mac80211/driver-ops.h --- linux-6.4/net/mac80211/driver-ops.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/driver-ops.h 2024-01-11 15:42:54.309009962 +0100 @@ -2,7 +2,7 @@ /* * Portions of this file * Copyright(c) 2016 Intel Deutschland GmbH -* Copyright (C) 2018 - 2019, 2021 Intel Corporation +* Copyright (C) 2018 - 2019, 2021 - 2023 Intel Corporation */ #ifndef __MAC80211_DRIVER_OPS @@ -13,15 +13,17 @@ #include "trace.h" #define check_sdata_in_driver(sdata) ({ \ - !WARN_ONCE(!(sdata->flags & IEEE80211_SDATA_IN_DRIVER), \ + WARN_ONCE(!sdata->local->reconfig_failure && \ + !(sdata->flags & IEEE80211_SDATA_IN_DRIVER), \ "%s: Failed check-sdata-in-driver check, flags: 0x%x\n", \ sdata->dev ? sdata->dev->name : sdata->name, sdata->flags); \ + !!(sdata->flags & IEEE80211_SDATA_IN_DRIVER); \ }) static inline struct ieee80211_sub_if_data * get_bss_sdata(struct ieee80211_sub_if_data *sdata) { - if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) + if (sdata && sdata->vif.type == NL80211_IFTYPE_AP_VLAN) sdata = container_of(sdata->bss, struct ieee80211_sub_if_data, u.ap); @@ -38,6 +40,9 @@ static inline void drv_sync_rx_queues(struct ieee80211_local *local, struct sta_info *sta) { + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (local->ops->sync_rx_queues) { trace_drv_sync_rx_queues(local, sta->sdata, &sta->sta); local->ops->sync_rx_queues(&local->hw); @@ -84,6 +89,8 @@ int drv_start(struct ieee80211_local *local); void drv_stop(struct ieee80211_local *local); +int drv_get_powered(struct ieee80211_local *local, bool *up, bool *busy); +int drv_set_powered(struct ieee80211_local *local); #ifdef CONFIG_PM static inline int drv_suspend(struct ieee80211_local *local, @@ -92,6 +99,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_suspend(local); ret = local->ops->suspend(&local->hw, wowlan); @@ -104,6 +112,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_resume(local); ret = local->ops->resume(&local->hw); @@ -115,6 +124,7 @@ bool enabled) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!local->ops->set_wakeup) return; @@ -140,6 +150,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_config(local, changed); ret = local->ops->config(&local->hw, changed); @@ -152,6 +163,7 @@ u64 changed) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -191,6 +203,7 @@ u64 multicast) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_configure_filter(local, changed_flags, total_flags, multicast); @@ -205,6 +218,7 @@ unsigned int changed_flags) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_config_iface_filter(local, sdata, filter_flags, changed_flags); @@ -261,6 +275,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -275,6 +290,7 @@ struct ieee80211_sub_if_data *sdata) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -293,6 +309,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -310,6 +327,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -326,6 +344,7 @@ const u8 *mac_addr) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_sw_scan_start(local, sdata, mac_addr); if (local->ops->sw_scan_start) @@ -337,6 +356,7 @@ struct ieee80211_sub_if_data *sdata) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_sw_scan_complete(local, sdata); if (local->ops->sw_scan_complete) @@ -350,6 +370,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (local->ops->get_stats) ret = local->ops->get_stats(&local->hw, stats); @@ -373,6 +394,7 @@ int ret = 0; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_set_frag_threshold(local, value); if (local->ops->set_frag_threshold) @@ -387,6 +409,7 @@ int ret = 0; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_set_rts_threshold(local, value); if (local->ops->set_rts_threshold) @@ -400,6 +423,7 @@ { int ret = 0; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_set_coverage_class(local, value); if (local->ops->set_coverage_class) @@ -433,6 +457,7 @@ int ret = 0; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -452,6 +477,7 @@ struct ieee80211_sta *sta) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -465,12 +491,30 @@ } #ifdef CONFIG_MAC80211_DEBUGFS +static inline void drv_vif_add_debugfs(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata) +{ + might_sleep(); + + if (sdata->vif.type == NL80211_IFTYPE_MONITOR || + WARN_ON(!sdata->vif.debugfs_dir)) + return; + + sdata = get_bss_sdata(sdata); + if (!check_sdata_in_driver(sdata)) + return; + + if (local->ops->vif_add_debugfs) + local->ops->vif_add_debugfs(&local->hw, &sdata->vif); +} + static inline void drv_link_add_debugfs(struct ieee80211_local *local, struct ieee80211_sub_if_data *sdata, struct ieee80211_bss_conf *link_conf, struct dentry *dir) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -487,6 +531,7 @@ struct dentry *dir) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -503,6 +548,7 @@ struct dentry *dir) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -512,6 +558,12 @@ local->ops->link_sta_add_debugfs(&local->hw, &sdata->vif, link_sta, dir); } +#else +static inline void drv_vif_add_debugfs(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata) +{ + might_sleep(); +} #endif static inline void drv_sta_pre_rcu_remove(struct ieee80211_local *local, @@ -519,6 +571,7 @@ struct sta_info *sta) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) @@ -567,6 +620,9 @@ struct ieee80211_sta *sta, struct station_info *sinfo) { + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + sdata = get_bss_sdata(sdata); if (!check_sdata_in_driver(sdata)) return; @@ -597,6 +653,7 @@ int ret = 0; /* default unsupported op for less congestion */ might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_tx_last_beacon(local); if (local->ops->tx_last_beacon) @@ -614,6 +671,9 @@ { int ret = -EOPNOTSUPP; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + trace_drv_get_survey(local, idx, survey); if (local->ops->get_survey) @@ -627,6 +687,7 @@ static inline void drv_rfkill_poll(struct ieee80211_local *local) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (local->ops->rfkill_poll) local->ops->rfkill_poll(&local->hw); @@ -636,9 +697,13 @@ struct ieee80211_sub_if_data *sdata, u32 queues, bool drop) { - struct ieee80211_vif *vif = sdata ? &sdata->vif : NULL; + struct ieee80211_vif *vif; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + + sdata = get_bss_sdata(sdata); + vif = sdata ? &sdata->vif : NULL; if (sdata && !check_sdata_in_driver(sdata)) return; @@ -654,6 +719,9 @@ struct sta_info *sta) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + + sdata = get_bss_sdata(sdata); if (sdata && !check_sdata_in_driver(sdata)) return; @@ -669,6 +737,7 @@ struct ieee80211_channel_switch *ch_switch) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_channel_switch(local, sdata, ch_switch); local->ops->channel_switch(&local->hw, &sdata->vif, ch_switch); @@ -681,6 +750,7 @@ { int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (local->ops->set_antenna) ret = local->ops->set_antenna(&local->hw, tx_ant, rx_ant); trace_drv_set_antenna(local, tx_ant, rx_ant, ret); @@ -692,6 +762,7 @@ { int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (local->ops->get_antenna) ret = local->ops->get_antenna(&local->hw, tx_ant, rx_ant); trace_drv_get_antenna(local, *tx_ant, *rx_ant, ret); @@ -707,6 +778,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_remain_on_channel(local, sdata, chan, duration, type); ret = local->ops->remain_on_channel(&local->hw, &sdata->vif, @@ -723,6 +795,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_cancel_remain_on_channel(local, sdata); ret = local->ops->cancel_remain_on_channel(&local->hw, &sdata->vif); @@ -737,6 +810,7 @@ int ret = -ENOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_set_ringparam(local, tx, rx); if (local->ops->set_ringparam) @@ -750,6 +824,7 @@ u32 *tx, u32 *tx_max, u32 *rx, u32 *rx_max) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_get_ringparam(local, tx, tx_max, rx, rx_max); if (local->ops->get_ringparam) @@ -762,6 +837,7 @@ bool ret = false; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_tx_frames_pending(local); if (local->ops->tx_frames_pending) @@ -778,6 +854,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -795,6 +872,9 @@ struct ieee80211_sub_if_data *sdata, struct cfg80211_gtk_rekey_data *data) { + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) return; @@ -849,11 +929,13 @@ struct ieee80211_prep_tx_info *info) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; WARN_ON_ONCE(sdata->vif.type != NL80211_IFTYPE_STATION); + info->link_id = info->link_id < 0 ? 0 : info->link_id; trace_drv_mgd_prepare_tx(local, sdata, info->duration, info->subtype, info->success); if (local->ops->mgd_prepare_tx) @@ -866,6 +948,7 @@ struct ieee80211_prep_tx_info *info) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -880,17 +963,22 @@ static inline void drv_mgd_protect_tdls_discover(struct ieee80211_local *local, - struct ieee80211_sub_if_data *sdata) + struct ieee80211_sub_if_data *sdata, + int link_id) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; WARN_ON_ONCE(sdata->vif.type != NL80211_IFTYPE_STATION); + link_id = link_id > 0 ? link_id : 0; + trace_drv_mgd_protect_tdls_discover(local, sdata); if (local->ops->mgd_protect_tdls_discover) - local->ops->mgd_protect_tdls_discover(&local->hw, &sdata->vif); + local->ops->mgd_protect_tdls_discover(&local->hw, &sdata->vif, + link_id); trace_drv_return_void(local); } @@ -900,6 +988,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_add_chanctx(local, ctx); if (local->ops->add_chanctx) @@ -915,6 +1004,7 @@ struct ieee80211_chanctx *ctx) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(!ctx->driver_present)) return; @@ -931,6 +1021,7 @@ u32 changed) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_change_chanctx(local, ctx, changed); if (local->ops->change_chanctx) { @@ -940,14 +1031,6 @@ trace_drv_return_void(local); } -static inline void drv_verify_link_exists(struct ieee80211_sub_if_data *sdata, - struct ieee80211_bss_conf *link_conf) -{ - /* deflink always exists, so need to check only for other links */ - if (sdata->deflink.conf != link_conf) - sdata_assert_lock(sdata); -} - int drv_assign_vif_chanctx(struct ieee80211_local *local, struct ieee80211_sub_if_data *sdata, struct ieee80211_bss_conf *link_conf, @@ -966,10 +1049,8 @@ { int ret = 0; - /* make sure link_conf is protected */ - drv_verify_link_exists(sdata, link_conf); - might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -985,8 +1066,8 @@ struct ieee80211_sub_if_data *sdata, struct ieee80211_bss_conf *link_conf) { - /* make sure link_conf is protected */ - drv_verify_link_exists(sdata, link_conf); + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1002,6 +1083,7 @@ enum ieee80211_reconfig_type reconfig_type) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); trace_drv_reconfig_complete(local, reconfig_type); if (local->ops->reconfig_complete) @@ -1014,6 +1096,9 @@ struct ieee80211_sub_if_data *sdata, int key_idx) { + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) return; @@ -1044,6 +1129,9 @@ { struct ieee80211_local *local = sdata->local; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (local->ops->channel_switch_beacon) { trace_drv_channel_switch_beacon(local, sdata, chandef); local->ops->channel_switch_beacon(&local->hw, &sdata->vif, @@ -1058,6 +1146,9 @@ struct ieee80211_local *local = sdata->local; int ret = 0; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) return -EIO; @@ -1070,17 +1161,22 @@ } static inline int -drv_post_channel_switch(struct ieee80211_sub_if_data *sdata) +drv_post_channel_switch(struct ieee80211_link_data *link) { + struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_local *local = sdata->local; int ret = 0; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) return -EIO; trace_drv_post_channel_switch(local, sdata); if (local->ops->post_channel_switch) - ret = local->ops->post_channel_switch(&local->hw, &sdata->vif); + ret = local->ops->post_channel_switch(&local->hw, &sdata->vif, + link->conf); trace_drv_return_int(local, ret); return ret; } @@ -1090,6 +1186,9 @@ { struct ieee80211_local *local = sdata->local; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) return; @@ -1105,6 +1204,9 @@ { struct ieee80211_local *local = sdata->local; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) return; @@ -1120,6 +1222,7 @@ int ret = 0; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -1134,6 +1237,7 @@ struct ieee80211_sub_if_data *sdata) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1161,6 +1265,9 @@ { int ret; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!local->ops->get_txpower) return -EOPNOTSUPP; @@ -1180,6 +1287,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -1200,6 +1308,7 @@ struct ieee80211_sta *sta) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1265,6 +1374,11 @@ { u32 ret = -EOPNOTSUPP; + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); + if (!check_sdata_in_driver(sdata)) + return -EIO; + if (local->ops->get_ftm_responder_stats) ret = local->ops->get_ftm_responder_stats(&local->hw, &sdata->vif, @@ -1281,6 +1395,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return -EIO; @@ -1300,6 +1415,7 @@ trace_drv_abort_pmsr(local, sdata); might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1315,6 +1431,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); check_sdata_in_driver(sdata); trace_drv_start_nan(local, sdata, conf); @@ -1327,6 +1444,7 @@ struct ieee80211_sub_if_data *sdata) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); check_sdata_in_driver(sdata); trace_drv_stop_nan(local, sdata); @@ -1342,6 +1460,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); check_sdata_in_driver(sdata); if (!local->ops->nan_change_conf) @@ -1362,6 +1481,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); check_sdata_in_driver(sdata); if (!local->ops->add_nan_func) @@ -1379,6 +1499,7 @@ u8 instance_id) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); check_sdata_in_driver(sdata); trace_drv_del_nan_func(local, sdata, instance_id); @@ -1395,6 +1516,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); ret = local->ops->set_tid_config(&local->hw, &sdata->vif, sta, tid_conf); trace_drv_return_int(local, ret); @@ -1409,6 +1531,7 @@ int ret; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); ret = local->ops->reset_tid_config(&local->hw, &sdata->vif, sta, tids); trace_drv_return_int(local, ret); @@ -1419,6 +1542,7 @@ struct ieee80211_sub_if_data *sdata) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); check_sdata_in_driver(sdata); if (!local->ops->update_vif_offload) @@ -1434,6 +1558,9 @@ struct ieee80211_sta *sta, bool enabled) { sdata = get_bss_sdata(sdata); + + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1449,6 +1576,9 @@ bool enabled) { sdata = get_bss_sdata(sdata); + + might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1467,6 +1597,7 @@ struct ieee80211_twt_params *twt_agrt; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1484,6 +1615,7 @@ u8 flowid) { might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); if (!check_sdata_in_driver(sdata)) return; @@ -1524,6 +1656,8 @@ { int ret = -EOPNOTSUPP; + might_sleep(); + sdata = get_bss_sdata(sdata); trace_drv_net_setup_tc(local, sdata, type); if (local->ops->net_setup_tc) diff -ruw linux-6.4/net/mac80211/drop.h linux-6.4-fbx/net/mac80211/drop.h --- linux-6.4/net/mac80211/drop.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/drop.h 2023-11-07 13:38:44.074257019 +0100 @@ -18,9 +18,54 @@ /* this line for the trailing \ - add before this */ #define MAC80211_DROP_REASONS_UNUSABLE(R) \ + /* 0x00 == ___RX_DROP_UNUSABLE */ \ R(RX_DROP_U_MIC_FAIL) \ R(RX_DROP_U_REPLAY) \ R(RX_DROP_U_BAD_MMIE) \ + R(RX_DROP_U_DUP) \ + R(RX_DROP_U_SPURIOUS) \ + R(RX_DROP_U_DECRYPT_FAIL) \ + R(RX_DROP_U_NO_KEY_ID) \ + R(RX_DROP_U_BAD_CIPHER) \ + R(RX_DROP_U_OOM) \ + R(RX_DROP_U_NONSEQ_PN) \ + R(RX_DROP_U_BAD_KEY_COLOR) \ + R(RX_DROP_U_BAD_4ADDR) \ + R(RX_DROP_U_BAD_AMSDU) \ + R(RX_DROP_U_BAD_AMSDU_CIPHER) \ + R(RX_DROP_U_INVALID_8023) \ + /* 0x10 */ \ + R(RX_DROP_U_RUNT_ACTION) \ + R(RX_DROP_U_UNPROT_ACTION) \ + R(RX_DROP_U_UNPROT_DUAL) \ + R(RX_DROP_U_UNPROT_UCAST_MGMT) \ + R(RX_DROP_U_UNPROT_MCAST_MGMT) \ + R(RX_DROP_U_UNPROT_BEACON) \ + R(RX_DROP_U_UNPROT_UNICAST_PUB_ACTION) \ + R(RX_DROP_U_UNPROT_ROBUST_ACTION) \ + R(RX_DROP_U_ACTION_UNKNOWN_SRC) \ + R(RX_DROP_U_REJECTED_ACTION_RESPONSE) \ + R(RX_DROP_U_EXPECT_DEFRAG_PROT) \ + R(RX_DROP_U_WEP_DEC_FAIL) \ + R(RX_DROP_U_NO_IV) \ + R(RX_DROP_U_NO_ICV) \ + R(RX_DROP_U_AP_RX_GROUPCAST) \ + R(RX_DROP_U_SHORT_MMIC) \ + /* 0x20 */ \ + R(RX_DROP_U_MMIC_FAIL) \ + R(RX_DROP_U_SHORT_TKIP) \ + R(RX_DROP_U_TKIP_FAIL) \ + R(RX_DROP_U_SHORT_CCMP) \ + R(RX_DROP_U_SHORT_CCMP_MIC) \ + R(RX_DROP_U_SHORT_GCMP) \ + R(RX_DROP_U_SHORT_GCMP_MIC) \ + R(RX_DROP_U_SHORT_CMAC) \ + R(RX_DROP_U_SHORT_CMAC256) \ + R(RX_DROP_U_SHORT_GMAC) \ + R(RX_DROP_U_UNEXPECTED_VLAN_4ADDR) \ + R(RX_DROP_U_UNEXPECTED_STA_4ADDR) \ + R(RX_DROP_U_UNEXPECTED_VLAN_MCAST) \ + R(RX_DROP_U_NOT_PORT_CONTROL) \ /* this line for the trailing \ - add before this */ /* having two enums allows for checking ieee80211_rx_result use with sparse */ @@ -46,11 +91,13 @@ RX_CONTINUE = (__force ieee80211_rx_result)___RX_CONTINUE, RX_QUEUED = (__force ieee80211_rx_result)___RX_QUEUED, RX_DROP_MONITOR = (__force ieee80211_rx_result)___RX_DROP_MONITOR, - RX_DROP_UNUSABLE = (__force ieee80211_rx_result)___RX_DROP_UNUSABLE, #define DEF(x) x = (__force ieee80211_rx_result)___ ## x, MAC80211_DROP_REASONS_MONITOR(DEF) MAC80211_DROP_REASONS_UNUSABLE(DEF) #undef DEF }; +#define RX_RES_IS_UNUSABLE(result) \ + (((__force u32)(result) & SKB_DROP_REASON_SUBSYS_MASK) == ___RX_DROP_UNUSABLE) + #endif /* MAC80211_DROP_H */ diff -ruw linux-6.4/net/mac80211/eht.c linux-6.4-fbx/net/mac80211/eht.c --- linux-6.4/net/mac80211/eht.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/eht.c 2024-01-19 17:01:19.905848123 +0100 @@ -2,7 +2,7 @@ /* * EHT handling * - * Copyright(c) 2021-2022 Intel Corporation + * Copyright(c) 2021-2023 Intel Corporation */ #include "ieee80211_i.h" @@ -25,8 +25,7 @@ memset(eht_cap, 0, sizeof(*eht_cap)); if (!eht_cap_ie_elem || - !ieee80211_get_eht_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif))) + !ieee80211_get_eht_iftype_cap_vif(sband, &sdata->vif)) return; mcs_nss_size = ieee80211_eht_mcs_nss_size(he_cap_ie_elem, @@ -76,4 +75,5 @@ link_sta->cur_max_bandwidth = ieee80211_sta_cap_rx_bw(link_sta); link_sta->pub->bandwidth = ieee80211_sta_cur_vht_bw(link_sta); + link_sta->pub->sta_max_bandwidth = link_sta->cur_max_bandwidth; } diff -ruw linux-6.4/net/mac80211/ethtool.c linux-6.4-fbx/net/mac80211/ethtool.c --- linux-6.4/net/mac80211/ethtool.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/ethtool.c 2023-11-07 13:38:44.074257019 +0100 @@ -5,7 +5,7 @@ * Copied from cfg.c - originally * Copyright 2006-2010 Johannes Berg * Copyright 2014 Intel Corporation (Author: Johannes Berg) - * Copyright (C) 2018, 2022 Intel Corporation + * Copyright (C) 2018, 2022-2023 Intel Corporation */ #include #include @@ -19,11 +19,16 @@ struct netlink_ext_ack *extack) { struct ieee80211_local *local = wiphy_priv(dev->ieee80211_ptr->wiphy); + int ret; if (rp->rx_mini_pending != 0 || rp->rx_jumbo_pending != 0) return -EINVAL; - return drv_set_ringparam(local, rp->tx_pending, rp->rx_pending); + wiphy_lock(local->hw.wiphy); + ret = drv_set_ringparam(local, rp->tx_pending, rp->rx_pending); + wiphy_unlock(local->hw.wiphy); + + return ret; } static void ieee80211_get_ringparam(struct net_device *dev, @@ -35,8 +40,10 @@ memset(rp, 0, sizeof(*rp)); + wiphy_lock(local->hw.wiphy); drv_get_ringparam(local, &rp->tx_pending, &rp->tx_max_pending, &rp->rx_pending, &rp->rx_max_pending); + wiphy_unlock(local->hw.wiphy); } static const char ieee80211_gstrings_sta_stats[][ETH_GSTRING_LEN] = { @@ -50,6 +57,22 @@ }; #define STA_STATS_LEN ARRAY_SIZE(ieee80211_gstrings_sta_stats) +struct ethtool_priv_flags_strings { + const char string[ETH_GSTRING_LEN]; +}; + +enum { + POWERED_SUPPORTED = (1 << 0), + POWERED_STATUS = (1 << 1), + POWERED_CHANGE_BUSY = (1 << 2), +}; + +static const struct ethtool_priv_flags_strings ieee80211_pflags_strings[] = { + { .string = "powered-supported" }, + { .string = "powered-status" }, + { .string = "powered-change-busy", }, +}; + static int ieee80211_get_sset_count(struct net_device *dev, int sset) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); @@ -60,6 +83,9 @@ rv += drv_get_et_sset_count(sdata, sset); + if (sset == ETH_SS_PRIV_FLAGS) + rv += ARRAY_SIZE(ieee80211_pflags_strings); + if (rv == 0) return -EOPNOTSUPP; return rv; @@ -102,7 +128,7 @@ * network device. */ - mutex_lock(&local->sta_mtx); + wiphy_lock(local->hw.wiphy); if (sdata->vif.type == NL80211_IFTYPE_STATION) { sta = sta_info_get_bss(sdata, sdata->deflink.u.mgd.bssid); @@ -198,12 +224,13 @@ else data[i++] = -1LL; - mutex_unlock(&local->sta_mtx); - - if (WARN_ON(i != STA_STATS_LEN)) + if (WARN_ON(i != STA_STATS_LEN)) { + wiphy_unlock(local->hw.wiphy); return; + } drv_get_et_stats(sdata, stats, &(data[STA_STATS_LEN])); + wiphy_unlock(local->hw.wiphy); } static void ieee80211_get_strings(struct net_device *dev, u32 sset, u8 *data) @@ -216,6 +243,9 @@ memcpy(data, ieee80211_gstrings_sta_stats, sz_sta_stats); } drv_get_et_strings(sdata, sset, &(data[sz_sta_stats])); + if (sset == ETH_SS_PRIV_FLAGS) + memcpy(data, ieee80211_pflags_strings, + sizeof (ieee80211_pflags_strings)); } static int ieee80211_get_regs_len(struct net_device *dev) @@ -233,6 +263,35 @@ regs->len = 0; } +static u32 ieee80211_get_priv_flags(struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; + bool powered, powered_busy; + u32 ret; + + ret = 0; + if (!drv_get_powered(local, &powered, &powered_busy)) { + ret |= POWERED_SUPPORTED; + if (powered) + ret |= POWERED_STATUS; + if (powered_busy) + ret |= POWERED_CHANGE_BUSY; + } + return ret; +} + +static int ieee80211_set_priv_flags(struct net_device *dev, u32 flags) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; + + if (flags & (POWERED_STATUS)) + return drv_set_powered(local); + + return 0; +} + const struct ethtool_ops ieee80211_ethtool_ops = { .get_drvinfo = cfg80211_get_drvinfo, .get_regs_len = ieee80211_get_regs_len, @@ -243,4 +302,6 @@ .get_strings = ieee80211_get_strings, .get_ethtool_stats = ieee80211_get_stats, .get_sset_count = ieee80211_get_sset_count, + .set_priv_flags = ieee80211_set_priv_flags, + .get_priv_flags = ieee80211_get_priv_flags, }; diff -ruw linux-6.4/net/mac80211/fils_aead.c linux-6.4-fbx/net/mac80211/fils_aead.c --- linux-6.4/net/mac80211/fils_aead.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/fils_aead.c 2023-11-07 13:38:44.074257019 +0100 @@ -5,9 +5,9 @@ */ #include -#include #include #include +#include #include "ieee80211_i.h" #include "aes_cmac.h" diff -ruw linux-6.4/net/mac80211/he.c linux-6.4-fbx/net/mac80211/he.c --- linux-6.4/net/mac80211/he.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/he.c 2024-01-19 17:01:19.905848123 +0100 @@ -128,8 +128,7 @@ return; own_he_cap_ptr = - ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); if (!own_he_cap_ptr) return; @@ -163,6 +162,7 @@ link_sta->cur_max_bandwidth = ieee80211_sta_cap_rx_bw(link_sta); link_sta->pub->bandwidth = ieee80211_sta_cur_vht_bw(link_sta); + link_sta->pub->sta_max_bandwidth = link_sta->cur_max_bandwidth; if (sband->band == NL80211_BAND_6GHZ && he_6ghz_capa) ieee80211_update_from_he_6ghz_capa(he_6ghz_capa, link_sta); diff -ruw linux-6.4/net/mac80211/ht.c linux-6.4-fbx/net/mac80211/ht.c --- linux-6.4/net/mac80211/ht.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/ht.c 2024-01-19 17:01:19.905848123 +0100 @@ -9,7 +9,7 @@ * Copyright 2007, Michael Wu * Copyright 2007-2010, Intel Corporation * Copyright 2017 Intel Deutschland GmbH - * Copyright(c) 2020-2022 Intel Corporation + * Copyright(c) 2020-2023 Intel Corporation */ #include @@ -282,6 +282,7 @@ link_sta->cur_max_bandwidth = ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40 ? IEEE80211_STA_RX_BW_40 : IEEE80211_STA_RX_BW_20; + link_sta->pub->sta_max_bandwidth = link_sta->cur_max_bandwidth; if (sta->sdata->vif.type == NL80211_IFTYPE_AP || sta->sdata->vif.type == NL80211_IFTYPE_AP_VLAN) { @@ -316,16 +317,16 @@ { int i; - mutex_lock(&sta->ampdu_mlme.mtx); + lockdep_assert_wiphy(sta->local->hw.wiphy); + for (i = 0; i < IEEE80211_NUM_TIDS; i++) - ___ieee80211_stop_rx_ba_session(sta, i, WLAN_BACK_RECIPIENT, + __ieee80211_stop_rx_ba_session(sta, i, WLAN_BACK_RECIPIENT, WLAN_REASON_QSTA_LEAVE_QBSS, reason != AGG_STOP_DESTROY_STA && reason != AGG_STOP_PEER_REQUEST); for (i = 0; i < IEEE80211_NUM_TIDS; i++) - ___ieee80211_stop_tx_ba_session(sta, i, reason); - mutex_unlock(&sta->ampdu_mlme.mtx); + __ieee80211_stop_tx_ba_session(sta, i, reason); /* * In case the tear down is part of a reconfigure due to HW restart @@ -333,9 +334,8 @@ * the BA session, so handle it to properly clean tid_tx data. */ if(reason == AGG_STOP_DESTROY_STA) { - cancel_work_sync(&sta->ampdu_mlme.work); + wiphy_work_cancel(sta->local->hw.wiphy, &sta->ampdu_mlme.work); - mutex_lock(&sta->ampdu_mlme.mtx); for (i = 0; i < IEEE80211_NUM_TIDS; i++) { struct tid_ampdu_tx *tid_tx = rcu_dereference_protected_tid_tx(sta, i); @@ -346,11 +346,10 @@ if (test_and_clear_bit(HT_AGG_STATE_STOP_CB, &tid_tx->state)) ieee80211_stop_tx_ba_cb(sta, i, tid_tx); } - mutex_unlock(&sta->ampdu_mlme.mtx); } } -void ieee80211_ba_session_work(struct work_struct *work) +void ieee80211_ba_session_work(struct wiphy *wiphy, struct wiphy_work *work) { struct sta_info *sta = container_of(work, struct sta_info, ampdu_mlme.work); @@ -358,32 +357,33 @@ bool blocked; int tid; + lockdep_assert_wiphy(sta->local->hw.wiphy); + /* When this flag is set, new sessions should be blocked. */ blocked = test_sta_flag(sta, WLAN_STA_BLOCK_BA); - mutex_lock(&sta->ampdu_mlme.mtx); for (tid = 0; tid < IEEE80211_NUM_TIDS; tid++) { if (test_and_clear_bit(tid, sta->ampdu_mlme.tid_rx_timer_expired)) - ___ieee80211_stop_rx_ba_session( + __ieee80211_stop_rx_ba_session( sta, tid, WLAN_BACK_RECIPIENT, WLAN_REASON_QSTA_TIMEOUT, true); if (test_and_clear_bit(tid, sta->ampdu_mlme.tid_rx_stop_requested)) - ___ieee80211_stop_rx_ba_session( + __ieee80211_stop_rx_ba_session( sta, tid, WLAN_BACK_RECIPIENT, WLAN_REASON_UNSPECIFIED, true); if (!blocked && test_and_clear_bit(tid, sta->ampdu_mlme.tid_rx_manage_offl)) - ___ieee80211_start_rx_ba_session(sta, 0, 0, 0, 1, tid, + __ieee80211_start_rx_ba_session(sta, 0, 0, 0, 1, tid, IEEE80211_MAX_AMPDU_BUF_HT, false, true, NULL); if (test_and_clear_bit(tid + IEEE80211_NUM_TIDS, sta->ampdu_mlme.tid_rx_manage_offl)) - ___ieee80211_stop_rx_ba_session( + __ieee80211_stop_rx_ba_session( sta, tid, WLAN_BACK_RECIPIENT, 0, false); @@ -414,9 +414,7 @@ */ synchronize_net(); - mutex_unlock(&sta->ampdu_mlme.mtx); - - ieee80211_queue_work(&sdata->local->hw, work); + wiphy_work_queue(sdata->local->hw.wiphy, work); return; } @@ -448,12 +446,11 @@ test_and_clear_bit(HT_AGG_STATE_START_CB, &tid_tx->state)) ieee80211_start_tx_ba_cb(sta, tid, tid_tx); if (test_and_clear_bit(HT_AGG_STATE_WANT_STOP, &tid_tx->state)) - ___ieee80211_stop_tx_ba_session(sta, tid, + __ieee80211_stop_tx_ba_session(sta, tid, AGG_STOP_LOCAL_REQUEST); if (test_and_clear_bit(HT_AGG_STATE_STOP_CB, &tid_tx->state)) ieee80211_stop_tx_ba_cb(sta, tid, tid_tx); } - mutex_unlock(&sta->ampdu_mlme.mtx); } void ieee80211_send_delba(struct ieee80211_sub_if_data *sdata, @@ -538,11 +535,13 @@ int ieee80211_send_smps_action(struct ieee80211_sub_if_data *sdata, enum ieee80211_smps_mode smps, const u8 *da, - const u8 *bssid) + const u8 *bssid, int link_id) { struct ieee80211_local *local = sdata->local; struct sk_buff *skb; struct ieee80211_mgmt *action_frame; + struct ieee80211_tx_info *info; + u8 status_link_id = link_id < 0 ? 0 : link_id; /* 27 = header + category + action + smps mode */ skb = dev_alloc_skb(27 + local->hw.extra_tx_headroom); @@ -562,6 +561,7 @@ case IEEE80211_SMPS_AUTOMATIC: case IEEE80211_SMPS_NUM_MODES: WARN_ON(1); + smps = IEEE80211_SMPS_OFF; fallthrough; case IEEE80211_SMPS_OFF: action_frame->u.action.u.ht_smps.smps_control = @@ -578,8 +578,13 @@ } /* we'll do more on status of this frame */ - IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; - ieee80211_tx_skb(sdata, skb); + info = IEEE80211_SKB_CB(skb); + info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; + /* we have 12 bits, and need 6: link_id 4, smps 2 */ + info->status_data = IEEE80211_STATUS_TYPE_SMPS | + u16_encode_bits(status_link_id << 2 | smps, + IEEE80211_STATUS_SUBDATA_MASK); + ieee80211_tx_skb_tid(sdata, skb, 7, link_id); return 0; } @@ -602,7 +607,8 @@ goto out; link->u.mgd.driver_smps_mode = smps_mode; - ieee80211_queue_work(&sdata->local->hw, &link->u.mgd.request_smps_work); + wiphy_work_queue(sdata->local->hw.wiphy, + &link->u.mgd.request_smps_work); out: rcu_read_unlock(); } diff -ruw linux-6.4/net/mac80211/ibss.c linux-6.4-fbx/net/mac80211/ibss.c --- linux-6.4/net/mac80211/ibss.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/ibss.c 2023-11-07 13:38:44.074257019 +0100 @@ -9,7 +9,7 @@ * Copyright 2009, Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright(c) 2016 Intel Deutschland GmbH - * Copyright(c) 2018-2022 Intel Corporation + * Copyright(c) 2018-2023 Intel Corporation */ #include @@ -51,7 +51,6 @@ u32 rate_flags, rates = 0, rates_added = 0; struct beacon_data *presp; int frame_len; - int shift; /* Build IBSS probe response */ frame_len = sizeof(struct ieee80211_hdr_3addr) + @@ -92,7 +91,6 @@ sband = local->hw.wiphy->bands[chandef->chan->band]; rate_flags = ieee80211_chandef_rate_flags(chandef); - shift = ieee80211_chandef_get_shift(chandef); rates_n = 0; if (have_higher_than_11mbit) *have_higher_than_11mbit = false; @@ -111,8 +109,7 @@ *pos++ = WLAN_EID_SUPP_RATES; *pos++ = min_t(int, 8, rates_n); for (ri = 0; ri < sband->n_bitrates; ri++) { - int rate = DIV_ROUND_UP(sband->bitrates[ri].bitrate, - 5 * (1 << shift)); + int rate = DIV_ROUND_UP(sband->bitrates[ri].bitrate, 5); u8 basic = 0; if (!(rates & BIT(ri))) continue; @@ -155,8 +152,7 @@ *pos++ = WLAN_EID_EXT_SUPP_RATES; *pos++ = rates_n - 8; for (; ri < sband->n_bitrates; ri++) { - int rate = DIV_ROUND_UP(sband->bitrates[ri].bitrate, - 5 * (1 << shift)); + int rate = DIV_ROUND_UP(sband->bitrates[ri].bitrate, 5); u8 basic = 0; if (!(rates & BIT(ri))) continue; @@ -226,7 +222,7 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_mgmt *mgmt; struct cfg80211_bss *bss; - u32 bss_change; + u64 bss_change; struct cfg80211_chan_def chandef; struct ieee80211_channel *chan; struct beacon_data *presp; @@ -235,7 +231,7 @@ bool radar_required; int err; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(local->hw.wiphy); /* Reset own TSF to allow time synchronization work. */ drv_reset_tsf(local, sdata); @@ -299,17 +295,14 @@ radar_required = err; - mutex_lock(&local->mtx); if (ieee80211_link_use_channel(&sdata->deflink, &chandef, ifibss->fixed_channel ? IEEE80211_CHANCTX_SHARED : IEEE80211_CHANCTX_EXCLUSIVE)) { sdata_info(sdata, "Failed to join IBSS, no channel context\n"); - mutex_unlock(&local->mtx); return; } sdata->deflink.radar_required = radar_required; - mutex_unlock(&local->mtx); memcpy(ifibss->bssid, bssid, ETH_ALEN); @@ -367,9 +360,7 @@ sdata->vif.cfg.ssid_len = 0; RCU_INIT_POINTER(ifibss->presp, NULL); kfree_rcu(presp, rcu_head); - mutex_lock(&local->mtx); ieee80211_link_release_channel(&sdata->deflink); - mutex_unlock(&local->mtx); sdata_info(sdata, "Failed to join IBSS, driver failure: %d\n", err); return; @@ -382,7 +373,6 @@ round_jiffies(jiffies + IEEE80211_IBSS_MERGE_INTERVAL)); bss_meta.chan = chan; - bss_meta.scan_width = cfg80211_chandef_to_scan_width(&chandef); bss = cfg80211_inform_bss_frame_data(local->hw.wiphy, &bss_meta, mgmt, presp->head_len, GFP_KERNEL); @@ -405,9 +395,8 @@ enum nl80211_channel_type chan_type; u64 tsf; u32 rate_flags; - int shift; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (beacon_int < 10) beacon_int = 10; @@ -440,7 +429,6 @@ sband = sdata->local->hw.wiphy->bands[cbss->channel->band]; rate_flags = ieee80211_chandef_rate_flags(&sdata->u.ibss.chandef); - shift = ieee80211_vif_get_shift(&sdata->vif); basic_rates = 0; @@ -454,8 +442,7 @@ != rate_flags) continue; - brate = DIV_ROUND_UP(sband->bitrates[j].bitrate, - 5 * (1 << shift)); + brate = DIV_ROUND_UP(sband->bitrates[j].bitrate, 5); if (brate == rate) { if (is_basic) basic_rates |= BIT(j); @@ -478,7 +465,8 @@ } int ieee80211_ibss_csa_beacon(struct ieee80211_sub_if_data *sdata, - struct cfg80211_csa_settings *csa_settings) + struct cfg80211_csa_settings *csa_settings, + u64 *changed) { struct ieee80211_if_ibss *ifibss = &sdata->u.ibss; struct beacon_data *presp, *old_presp; @@ -487,7 +475,7 @@ u16 capability = WLAN_CAPABILITY_IBSS; u64 tsf; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (ifibss->privacy) capability |= WLAN_CAPABILITY_PRIVACY; @@ -520,15 +508,16 @@ if (old_presp) kfree_rcu(old_presp, rcu_head); - return BSS_CHANGED_BEACON; + *changed |= BSS_CHANGED_BEACON; + return 0; } -int ieee80211_ibss_finish_csa(struct ieee80211_sub_if_data *sdata) +int ieee80211_ibss_finish_csa(struct ieee80211_sub_if_data *sdata, u64 *changed) { struct ieee80211_if_ibss *ifibss = &sdata->u.ibss; struct cfg80211_bss *cbss; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); /* When not connected/joined, sending CSA doesn't make sense. */ if (ifibss->state != IEEE80211_IBSS_MLME_JOINED) @@ -552,14 +541,15 @@ ifibss->chandef = sdata->deflink.csa_chandef; /* generate the beacon */ - return ieee80211_ibss_csa_beacon(sdata, NULL); + return ieee80211_ibss_csa_beacon(sdata, NULL, changed); } void ieee80211_ibss_stop(struct ieee80211_sub_if_data *sdata) { struct ieee80211_if_ibss *ifibss = &sdata->u.ibss; - cancel_work_sync(&ifibss->csa_connection_drop_work); + wiphy_work_cancel(sdata->local->hw.wiphy, + &ifibss->csa_connection_drop_work); } static struct sta_info *ieee80211_ibss_finish_sta(struct sta_info *sta) @@ -597,7 +587,6 @@ struct sta_info *sta; struct ieee80211_chanctx_conf *chanctx_conf; struct ieee80211_supported_band *sband; - enum nl80211_bss_scan_width scan_width; int band; /* @@ -626,7 +615,6 @@ if (WARN_ON_ONCE(!chanctx_conf)) return NULL; band = chanctx_conf->def.chan->band; - scan_width = cfg80211_chandef_to_scan_width(&chanctx_conf->def); rcu_read_unlock(); sta = sta_info_alloc(sdata, addr, GFP_KERNEL); @@ -638,7 +626,7 @@ /* make sure mandatory rates are always added */ sband = local->hw.wiphy->bands[band]; sta->sta.deflink.supp_rates[band] = supp_rates | - ieee80211_mandatory_rates(sband, scan_width); + ieee80211_mandatory_rates(sband); return ieee80211_ibss_finish_sta(sta); } @@ -649,7 +637,7 @@ int active = 0; struct sta_info *sta; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); rcu_read_lock(); @@ -677,6 +665,8 @@ struct beacon_data *presp; struct sta_info *sta; + lockdep_assert_wiphy(local->hw.wiphy); + if (!is_zero_ether_addr(ifibss->bssid)) { cbss = cfg80211_get_bss(local->hw.wiphy, ifibss->chandef.chan, ifibss->bssid, ifibss->ssid, @@ -723,27 +713,22 @@ ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_IBSS); drv_leave_ibss(local, sdata); - mutex_lock(&local->mtx); ieee80211_link_release_channel(&sdata->deflink); - mutex_unlock(&local->mtx); } -static void ieee80211_csa_connection_drop_work(struct work_struct *work) +static void ieee80211_csa_connection_drop_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata = container_of(work, struct ieee80211_sub_if_data, u.ibss.csa_connection_drop_work); - sdata_lock(sdata); - ieee80211_ibss_disconnect(sdata); synchronize_rcu(); skb_queue_purge(&sdata->skb_queue); /* trigger a scan to find another IBSS network to join */ - ieee80211_queue_work(&sdata->local->hw, &sdata->work); - - sdata_unlock(sdata); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } static void ieee80211_ibss_csa_mark_radar(struct ieee80211_sub_if_data *sdata) @@ -775,7 +760,7 @@ ieee80211_conn_flags_t conn_flags; u32 vht_cap_info = 0; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); conn_flags = IEEE80211_CONN_DISABLE_VHT; @@ -894,7 +879,7 @@ return true; disconnect: ibss_dbg(sdata, "Can't handle channel switch, disconnect\n"); - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &ifibss->csa_connection_drop_work); ieee80211_ibss_csa_mark_radar(sdata); @@ -947,7 +932,7 @@ { u16 auth_alg, auth_transaction; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (len < 24 + 6) return; @@ -980,7 +965,6 @@ { struct sta_info *sta; enum nl80211_band band = rx_status->band; - enum nl80211_bss_scan_width scan_width; struct ieee80211_local *local = sdata->local; struct ieee80211_supported_band *sband; bool rates_updated = false; @@ -1006,15 +990,9 @@ u32 prev_rates; prev_rates = sta->sta.deflink.supp_rates[band]; - /* make sure mandatory rates are always added */ - scan_width = NL80211_BSS_CHAN_WIDTH_20; - if (rx_status->bw == RATE_INFO_BW_5) - scan_width = NL80211_BSS_CHAN_WIDTH_5; - else if (rx_status->bw == RATE_INFO_BW_10) - scan_width = NL80211_BSS_CHAN_WIDTH_10; sta->sta.deflink.supp_rates[band] = supp_rates | - ieee80211_mandatory_rates(sband, scan_width); + ieee80211_mandatory_rates(sband); if (sta->sta.deflink.supp_rates[band] != prev_rates) { ibss_dbg(sdata, "updated supp_rates set for %pM based on beacon/probe_resp (0x%x -> 0x%x)\n", @@ -1068,7 +1046,7 @@ &chandef); memcpy(&cap_ie, elems->vht_cap_elem, sizeof(cap_ie)); ieee80211_vht_cap_ie_to_sta_vht_cap(sdata, sband, - &cap_ie, + &cap_ie, NULL, &sta->deflink); if (memcmp(&cap, &sta->sta.deflink.vht_cap, sizeof(cap))) rates_updated |= true; @@ -1201,7 +1179,6 @@ struct sta_info *sta; struct ieee80211_chanctx_conf *chanctx_conf; struct ieee80211_supported_band *sband; - enum nl80211_bss_scan_width scan_width; int band; /* @@ -1227,7 +1204,6 @@ return; } band = chanctx_conf->def.chan->band; - scan_width = cfg80211_chandef_to_scan_width(&chanctx_conf->def); rcu_read_unlock(); sta = sta_info_alloc(sdata, addr, GFP_ATOMIC); @@ -1237,12 +1213,12 @@ /* make sure mandatory rates are always added */ sband = local->hw.wiphy->bands[band]; sta->sta.deflink.supp_rates[band] = supp_rates | - ieee80211_mandatory_rates(sband, scan_width); + ieee80211_mandatory_rates(sband); spin_lock(&ifibss->incomplete_lock); list_add(&sta->list, &ifibss->incomplete_stations); spin_unlock(&ifibss->incomplete_lock); - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); } static void ieee80211_ibss_sta_expire(struct ieee80211_sub_if_data *sdata) @@ -1253,7 +1229,7 @@ unsigned long exp_time = IEEE80211_IBSS_INACTIVITY_LIMIT; unsigned long exp_rsn = IEEE80211_IBSS_RSN_INACTIVITY_LIMIT; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry_safe(sta, tmp, &local->sta_list, list) { unsigned long last_active = ieee80211_sta_last_active(sta); @@ -1278,8 +1254,6 @@ WARN_ON(__sta_info_destroy(sta)); } } - - mutex_unlock(&local->sta_mtx); } /* @@ -1289,9 +1263,8 @@ static void ieee80211_sta_merge_ibss(struct ieee80211_sub_if_data *sdata) { struct ieee80211_if_ibss *ifibss = &sdata->u.ibss; - enum nl80211_bss_scan_width scan_width; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); mod_timer(&ifibss->timer, round_jiffies(jiffies + IEEE80211_IBSS_MERGE_INTERVAL)); @@ -1311,9 +1284,8 @@ sdata_info(sdata, "No active IBSS STAs - trying to scan for other IBSS networks with same SSID (merge)\n"); - scan_width = cfg80211_chandef_to_scan_width(&ifibss->chandef); ieee80211_request_ibss_scan(sdata, ifibss->ssid, ifibss->ssid_len, - NULL, 0, scan_width); + NULL, 0); } static void ieee80211_sta_create_ibss(struct ieee80211_sub_if_data *sdata) @@ -1323,7 +1295,7 @@ u16 capability; int i; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (ifibss->fixed_bssid) { memcpy(bssid, ifibss->bssid, ETH_ALEN); @@ -1403,6 +1375,9 @@ case NL80211_CHAN_WIDTH_160: width = 160; break; + case NL80211_CHAN_WIDTH_320: + width = 320; + break; default: width = 20; break; @@ -1431,10 +1406,9 @@ struct cfg80211_bss *cbss; struct ieee80211_channel *chan = NULL; const u8 *bssid = NULL; - enum nl80211_bss_scan_width scan_width; int active_ibss; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); active_ibss = ieee80211_sta_active_ibss(sdata); ibss_dbg(sdata, "sta_find_ibss (active_ibss=%d)\n", active_ibss); @@ -1490,8 +1464,6 @@ sdata_info(sdata, "Trigger new scan to find an IBSS to join\n"); - scan_width = cfg80211_chandef_to_scan_width(&ifibss->chandef); - if (ifibss->fixed_channel) { num = ieee80211_ibss_setup_scan_channels(local->hw.wiphy, &ifibss->chandef, @@ -1499,11 +1471,10 @@ ARRAY_SIZE(channels)); ieee80211_request_ibss_scan(sdata, ifibss->ssid, ifibss->ssid_len, channels, - num, scan_width); + num); } else { ieee80211_request_ibss_scan(sdata, ifibss->ssid, - ifibss->ssid_len, NULL, - 0, scan_width); + ifibss->ssid_len, NULL, 0); } } else { int interval = IEEE80211_SCAN_INTERVAL; @@ -1528,7 +1499,7 @@ struct beacon_data *presp; u8 *pos, *end; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); presp = sdata_dereference(ifibss->presp, sdata); @@ -1624,10 +1595,8 @@ mgmt = (struct ieee80211_mgmt *) skb->data; fc = le16_to_cpu(mgmt->frame_control); - sdata_lock(sdata); - if (!sdata->u.ibss.ssid_len) - goto mgmt_out; /* not ready to merge yet */ + return; /* not ready to merge yet */ switch (fc & IEEE80211_FCTL_STYPE) { case IEEE80211_STYPE_PROBE_REQ: @@ -1667,9 +1636,6 @@ break; } } - - mgmt_out: - sdata_unlock(sdata); } void ieee80211_ibss_work(struct ieee80211_sub_if_data *sdata) @@ -1677,15 +1643,13 @@ struct ieee80211_if_ibss *ifibss = &sdata->u.ibss; struct sta_info *sta; - sdata_lock(sdata); - /* * Work could be scheduled after scan or similar * when we aren't even joined (or trying) with a * network. */ if (!ifibss->ssid_len) - goto out; + return; spin_lock_bh(&ifibss->incomplete_lock); while (!list_empty(&ifibss->incomplete_stations)) { @@ -1711,9 +1675,6 @@ WARN_ON(1); break; } - - out: - sdata_unlock(sdata); } static void ieee80211_ibss_timer(struct timer_list *t) @@ -1721,7 +1682,7 @@ struct ieee80211_sub_if_data *sdata = from_timer(sdata, t, u.ibss.timer); - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } void ieee80211_ibss_setup_sdata(struct ieee80211_sub_if_data *sdata) @@ -1731,7 +1692,7 @@ timer_setup(&ifibss->timer, ieee80211_ibss_timer, 0); INIT_LIST_HEAD(&ifibss->incomplete_stations); spin_lock_init(&ifibss->incomplete_lock); - INIT_WORK(&ifibss->csa_connection_drop_work, + wiphy_work_init(&ifibss->csa_connection_drop_work, ieee80211_csa_connection_drop_work); } @@ -1740,7 +1701,8 @@ { struct ieee80211_sub_if_data *sdata; - mutex_lock(&local->iflist_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + list_for_each_entry(sdata, &local->interfaces, list) { if (!ieee80211_sdata_running(sdata)) continue; @@ -1748,13 +1710,12 @@ continue; sdata->u.ibss.last_scan_completed = jiffies; } - mutex_unlock(&local->iflist_mtx); } int ieee80211_ibss_join(struct ieee80211_sub_if_data *sdata, struct cfg80211_ibss_params *params) { - u32 changed = 0; + u64 changed = 0; u32 rate_flags; struct ieee80211_supported_band *sband; enum ieee80211_chanctx_mode chanmode; @@ -1763,6 +1724,8 @@ int i; int ret; + lockdep_assert_wiphy(local->hw.wiphy); + if (params->chandef.chan->freq_offset) { /* this may work, but is untested */ return -EOPNOTSUPP; @@ -1783,10 +1746,8 @@ chanmode = (params->channel_fixed && !ret) ? IEEE80211_CHANCTX_SHARED : IEEE80211_CHANCTX_EXCLUSIVE; - mutex_lock(&local->chanctx_mtx); ret = ieee80211_check_combinations(sdata, ¶ms->chandef, chanmode, radar_detect_width); - mutex_unlock(&local->chanctx_mtx); if (ret < 0) return ret; @@ -1856,7 +1817,7 @@ sdata->deflink.needed_rx_chains = local->rx_chains; sdata->control_port_over_nl80211 = params->control_port_over_nl80211; - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); return 0; } diff -ruw linux-6.4/net/mac80211/ieee80211_i.h linux-6.4-fbx/net/mac80211/ieee80211_i.h --- linux-6.4/net/mac80211/ieee80211_i.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/ieee80211_i.h 2024-04-19 16:04:28.969736104 +0200 @@ -85,6 +85,12 @@ #define IEEE80211_MAX_NAN_INSTANCE_ID 255 +enum ieee80211_status_data { + IEEE80211_STATUS_TYPE_MASK = 0x00f, + IEEE80211_STATUS_TYPE_INVALID = 0, + IEEE80211_STATUS_TYPE_SMPS = 1, + IEEE80211_STATUS_SUBDATA_MASK = 0xff0, +}; /* * Keep a station's queues on the active list for deficit accounting purposes @@ -410,6 +416,8 @@ ieee80211_conn_flags_t conn_flags; u16 status; + + bool disabled; } link[IEEE80211_MLD_MAX_NUM_LINKS]; u8 ap_addr[ETH_ALEN] __aligned(2); @@ -459,15 +467,26 @@ bool downgraded; }; +/* Advertised TID-to-link mapping info */ +struct ieee80211_adv_ttlm_info { + /* time in TUs at which the new mapping is established, or 0 if there is + * no planned advertised TID-to-link mapping + */ + u16 switch_time; + u32 duration; /* duration of the planned T2L map in TUs */ + u16 map; /* map of usable links for all TIDs */ + bool active; /* whether the advertised mapping is active or not */ +}; + DECLARE_EWMA(beacon_signal, 4, 4) struct ieee80211_if_managed { struct timer_list timer; struct timer_list conn_mon_timer; struct timer_list bcn_mon_timer; - struct work_struct monitor_work; - struct work_struct beacon_connection_loss_work; - struct work_struct csa_connection_drop_work; + struct wiphy_work monitor_work; + struct wiphy_work beacon_connection_loss_work; + struct wiphy_work csa_connection_drop_work; unsigned long beacon_timeout; unsigned long probe_timeout; @@ -528,7 +547,7 @@ /* TDLS support */ u8 tdls_peer[ETH_ALEN] __aligned(2); - struct delayed_work tdls_peer_del_work; + struct wiphy_delayed_work tdls_peer_del_work; struct sk_buff *orig_teardown_skb; /* The original teardown skb */ struct sk_buff *teardown_skb; /* A copy to send through the AP */ spinlock_t teardown_lock; /* To lock changing teardown_skb */ @@ -542,18 +561,25 @@ * on the BE queue, but there's a lot of VO traffic, we might * get stuck in a downgraded situation and flush takes forever. */ - struct delayed_work tx_tspec_wk; + struct wiphy_delayed_work tx_tspec_wk; /* Information elements from the last transmitted (Re)Association * Request frame. */ u8 *assoc_req_ies; size_t assoc_req_ies_len; + + struct wiphy_delayed_work ml_reconf_work; + u16 removed_links; + + /* TID-to-link mapping support */ + struct wiphy_delayed_work ttlm_work; + struct ieee80211_adv_ttlm_info ttlm_info; }; struct ieee80211_if_ibss { struct timer_list timer; - struct work_struct csa_connection_drop_work; + struct wiphy_work csa_connection_drop_work; unsigned long last_scan_completed; @@ -613,8 +639,9 @@ * these declarations define the interface, which enables * vendor-specific mesh synchronization * + * @rx_bcn_presp: beacon/probe response was received + * @adjust_tsf: TSF adjustment method */ -struct ieee802_11_elems; struct ieee80211_mesh_sync_ops { void (*rx_bcn_presp)(struct ieee80211_sub_if_data *sdata, u16 stype, struct ieee80211_mgmt *mgmt, unsigned int len, @@ -671,7 +698,7 @@ struct timer_list mesh_path_root_timer; unsigned long wrkq_flags; - unsigned long mbss_changed; + unsigned long mbss_changed[64 / BITS_PER_LONG]; bool userspace_handles_dfs; @@ -744,6 +771,18 @@ int mesh_paths_generation; int mpp_paths_generation; struct mesh_tx_cache tx_cache; + + /* Store Vendor specific node metrics IE */ + u8 node_vendor_ie[260]; + u8 node_vendor_ie_len; + /* Store Vendor specific mesh path metrics IE */ + u8 mpm_vendor_ie[260]; + u8 mpm_vendor_ie_len; + + /* list to hold blocked mesh peer link entries */ + struct list_head mplink_blocking_list; + /* lock for mplink_blocking_list list */ + spinlock_t mplink_blocking_list_lock; }; #ifdef CONFIG_MAC80211_MESH @@ -854,12 +893,13 @@ * struct txq_info - per tid queue * * @tin: contains packets split into multiple flows - * @def_flow: used as a fallback flow when a packet destined to @tin hashes to - * a fq_flow which is already owned by a different tin - * @def_cvars: codel vars for @def_flow + * @def_cvars: codel vars for the @tin's default_flow + * @cstats: code statistics for this queue * @frags: used to keep fragments created after dequeue * @schedule_order: used with ieee80211_local->active_txqs * @schedule_round: counter to prevent infinite loops on TXQ scheduling + * @flags: TXQ flags from &enum txq_info_flags + * @txq: the driver visible part */ struct txq_info { struct fq_tin tin; @@ -877,18 +917,30 @@ struct ieee80211_txq txq; }; +#ifdef CONFIG_FBX80211_SCUM +struct ieee80211_if_scum { + struct list_head client_list; + struct list_head next; + bool skip_mon; +}; +#endif + struct ieee80211_if_mntr { u32 flags; u8 mu_follow_addr[ETH_ALEN] __aligned(2); struct list_head list; +#ifdef CONFIG_FBX80211_SCUM + struct ieee80211_if_scum scum; +#endif }; /** * struct ieee80211_if_nan - NAN state * * @conf: current NAN configuration - * @func_ids: a bitmap of available instance_id's + * @func_lock: lock for @func_inst_ids + * @function_inst_ids: a bitmap of available instance_id's */ struct ieee80211_if_nan { struct cfg80211_nan_conf conf; @@ -918,10 +970,12 @@ bool csa_waiting_bcn; bool csa_ignored_same_chan; - struct timer_list chswitch_timer; - struct work_struct chswitch_work; + struct wiphy_delayed_work chswitch_work; + + struct wiphy_work request_smps_work; + /* used to reconfigure hardware SM PS */ + struct wiphy_work recalc_smps; - struct work_struct request_smps_work; bool beacon_crc_valid; u32 beacon_crc; struct ewma_beacon_signal ave_beacon_signal; @@ -947,6 +1001,8 @@ int wmm_last_param_set; int mu_edca_last_param_set; + u8 bss_param_ch_cnt; + struct cfg80211_bss *bss; }; @@ -964,8 +1020,8 @@ struct ieee80211_sub_if_data *sdata; unsigned int link_id; - struct list_head assigned_chanctx_list; /* protected by chanctx_mtx */ - struct list_head reserved_chanctx_list; /* protected by chanctx_mtx */ + struct list_head assigned_chanctx_list; /* protected by wiphy mutex */ + struct list_head reserved_chanctx_list; /* protected by wiphy mutex */ /* multicast keys only */ struct ieee80211_key __rcu *gtk[NUM_DEFAULT_KEYS + @@ -975,18 +1031,18 @@ struct ieee80211_key __rcu *default_mgmt_key; struct ieee80211_key __rcu *default_beacon_key; - struct work_struct csa_finalize_work; - bool csa_block_tx; /* write-protected by sdata_lock and local->mtx */ + struct wiphy_work csa_finalize_work; + bool csa_block_tx; bool operating_11g_mode; struct cfg80211_chan_def csa_chandef; - struct work_struct color_change_finalize_work; + struct wiphy_work color_change_finalize_work; struct delayed_work color_collision_detect_work; u64 color_bitmap; - /* context reservation -- protected with chanctx_mtx */ + /* context reservation -- protected with wiphy mutex */ struct ieee80211_chanctx *reserved_chanctx; struct cfg80211_chan_def reserved_chandef; bool reserved_radar_required; @@ -999,7 +1055,7 @@ int ap_power_level; /* in dBm */ bool radar_required; - struct delayed_work dfs_cac_timer_work; + struct wiphy_delayed_work dfs_cac_timer_work; union { struct ieee80211_link_data_managed mgd; @@ -1026,7 +1082,7 @@ /* count for keys needing tailroom space allocation */ int crypto_tx_tailroom_needed_cnt; int crypto_tx_tailroom_pending_dec; - struct delayed_work dec_tailroom_needed_wk; + struct wiphy_delayed_work dec_tailroom_needed_wk; struct net_device *dev; struct ieee80211_local *local; @@ -1058,10 +1114,7 @@ atomic_t num_tx_queued; struct mac80211_qos_map __rcu *qos_map; - /* used to reconfigure hardware SM PS */ - struct work_struct recalc_smps; - - struct work_struct work; + struct wiphy_work work; struct sk_buff_head skb_queue; struct sk_buff_head status_queue; @@ -1100,7 +1153,7 @@ struct ieee80211_link_data __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; /* for ieee80211_set_active_links_async() */ - struct work_struct activate_links_work; + struct wiphy_work activate_links_work; u16 desired_active_links; #ifdef CONFIG_MAC80211_DEBUGFS @@ -1123,62 +1176,8 @@ return container_of(p, struct ieee80211_sub_if_data, vif); } -static inline void sdata_lock(struct ieee80211_sub_if_data *sdata) - __acquires(&sdata->wdev.mtx) -{ - mutex_lock(&sdata->wdev.mtx); - __acquire(&sdata->wdev.mtx); -} - -static inline void sdata_unlock(struct ieee80211_sub_if_data *sdata) - __releases(&sdata->wdev.mtx) -{ - mutex_unlock(&sdata->wdev.mtx); - __release(&sdata->wdev.mtx); -} - #define sdata_dereference(p, sdata) \ - rcu_dereference_protected(p, lockdep_is_held(&sdata->wdev.mtx)) - -static inline void -sdata_assert_lock(struct ieee80211_sub_if_data *sdata) -{ - lockdep_assert_held(&sdata->wdev.mtx); -} - -static inline int -ieee80211_chanwidth_get_shift(enum nl80211_chan_width width) -{ - switch (width) { - case NL80211_CHAN_WIDTH_5: - return 2; - case NL80211_CHAN_WIDTH_10: - return 1; - default: - return 0; - } -} - -static inline int -ieee80211_chandef_get_shift(struct cfg80211_chan_def *chandef) -{ - return ieee80211_chanwidth_get_shift(chandef->width); -} - -static inline int -ieee80211_vif_get_shift(struct ieee80211_vif *vif) -{ - struct ieee80211_chanctx_conf *chanctx_conf; - int shift = 0; - - rcu_read_lock(); - chanctx_conf = rcu_dereference(vif->bss_conf.chanctx_conf); - if (chanctx_conf) - shift = ieee80211_chandef_get_shift(&chanctx_conf->def); - rcu_read_unlock(); - - return shift; -} + wiphy_dereference(sdata->local->hw.wiphy, p) static inline int ieee80211_get_mbssid_beacon_len(struct cfg80211_mbssid_elems *elems, @@ -1248,7 +1247,7 @@ #endif /** - * mac80211 scan flags - currently active scan mode + * enum mac80211_scan_flags - currently active scan mode * * @SCAN_SW_SCANNING: We're currently in the process of scanning but may as * well be on the operating channel @@ -1266,7 +1265,7 @@ * and could send a probe request after receiving a beacon. * @SCAN_BEACON_DONE: Beacon received, we can now send a probe request */ -enum { +enum mac80211_scan_flags { SCAN_SW_SCANNING, SCAN_HW_SCANNING, SCAN_ONCHANNEL_SCANNING, @@ -1356,7 +1355,7 @@ spinlock_t filter_lock; /* used for uploading changed mc list */ - struct work_struct reconfig_filter; + struct wiphy_work reconfig_filter; /* aggregated multicast list */ struct netdev_hw_addr_list mc_list; @@ -1394,10 +1393,13 @@ /* device is during a HW reconfig */ bool in_reconfig; + /* reconfiguration failed ... suppress some warnings etc. */ + bool reconfig_failure; + /* wowlan is enabled -- don't reconfig on resume */ bool wowlan; - struct work_struct radar_detected_work; + struct wiphy_work radar_detected_work; /* number of RX chains the hardware has */ u8 rx_chains; @@ -1420,10 +1422,9 @@ /* Station data */ /* - * The mutex only protects the list, hash table and - * counter, reads are done with RCU. + * The list, hash table and counter are protected + * by the wiphy mutex, reads are done with RCU. */ - struct mutex sta_mtx; spinlock_t tim_lock; unsigned long num_sta; struct list_head sta_list; @@ -1452,15 +1453,6 @@ struct list_head mon_list; /* only that are IFF_UP && !cooked */ struct mutex iflist_mtx; - /* - * Key mutex, protects sdata's key_list and sta_info's - * key pointers and ptk_idx (write access, they're RCU.) - */ - struct mutex key_mtx; - - /* mutex for scan and work locking */ - struct mutex mtx; - /* Scanning and BSS list */ unsigned long scanning; struct cfg80211_ssid scan_ssid; @@ -1474,14 +1466,14 @@ int hw_scan_ies_bufsize; struct cfg80211_scan_info scan_info; - struct work_struct sched_scan_stopped_work; + struct wiphy_work sched_scan_stopped_work; struct ieee80211_sub_if_data __rcu *sched_scan_sdata; struct cfg80211_sched_scan_request __rcu *sched_scan_req; u8 scan_addr[ETH_ALEN]; unsigned long leave_oper_channel_time; enum mac80211_scan_state next_scan_state; - struct delayed_work scan_work; + struct wiphy_delayed_work scan_work; struct ieee80211_sub_if_data __rcu *scan_sdata; /* For backward compatibility only -- do not use */ struct cfg80211_chan_def _oper_chandef; @@ -1491,7 +1483,6 @@ /* channel contexts */ struct list_head chanctx_list; - struct mutex chanctx_mtx; #ifdef CONFIG_MAC80211_LEDS struct led_trigger tx_led, rx_led, assoc_led, radio_led; @@ -1545,8 +1536,8 @@ * interface (and monitors) in PS, this then points there. */ struct ieee80211_sub_if_data *ps_sdata; - struct work_struct dynamic_ps_enable_work; - struct work_struct dynamic_ps_disable_work; + struct wiphy_work dynamic_ps_enable_work; + struct wiphy_work dynamic_ps_disable_work; struct timer_list dynamic_ps_timer; struct notifier_block ifa_notifier; struct notifier_block ifa6_notifier; @@ -1574,9 +1565,9 @@ /* * Remain-on-channel support */ - struct delayed_work roc_work; + struct wiphy_delayed_work roc_work; struct list_head roc_list; - struct work_struct hw_roc_start, hw_roc_done; + struct wiphy_work hw_roc_start, hw_roc_done; unsigned long hw_roc_start_time; u64 roc_cookie_counter; @@ -1591,6 +1582,9 @@ /* extended capabilities provided by mac80211 */ u8 ext_capa[8]; +#ifdef CONFIG_FBX80211_SCUM + struct list_head scum_list; +#endif }; static inline struct ieee80211_sub_if_data * @@ -1612,7 +1606,7 @@ struct ieee80211_chanctx_conf *chanctx_conf; enum nl80211_band band; - WARN_ON(sdata->vif.valid_links); + WARN_ON(ieee80211_vif_is_mld(&sdata->vif)); rcu_read_lock(); chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf); @@ -1722,7 +1716,10 @@ const struct ieee80211_aid_response_ie *aid_resp; const struct ieee80211_eht_cap_elem *eht_cap; const struct ieee80211_eht_operation *eht_operation; - const struct ieee80211_multi_link_elem *multi_link; + const struct ieee80211_multi_link_elem *ml_basic; + const struct ieee80211_multi_link_elem *ml_reconf; + const struct ieee80211_bandwidth_indication *bandwidth_indication; + const struct ieee80211_ttlm_elem *ttlm[IEEE80211_TTLM_MAX_CNT]; /* length of them, respectively */ u8 ext_capab_len; @@ -1747,7 +1744,16 @@ u8 eht_cap_len; /* mult-link element can be de-fragmented and thus u8 is not sufficient */ - size_t multi_link_len; + size_t ml_basic_len; + size_t ml_reconf_len; + + /* The basic Multi-Link element in the original IEs */ + const struct element *ml_basic_elem; + + /* The reconfiguration Multi-Link element in the original IEs */ + const struct element *ml_reconf_elem; + + u8 ttlm_num; /* * store the per station profile pointer and length in case that the @@ -1766,7 +1772,14 @@ */ size_t scratch_len; u8 *scratch_pos; - u8 scratch[]; + u8 scratch[] __counted_by(scratch_len); +}; + +struct ieee802_11_mesh_vendor_specific_elems { + const u8 *ie_start; + u8 ie_len; + /* whether a parse error occurred while retrieving these elements */ + bool parse_error; }; static inline struct ieee80211_local *hw_to_local( @@ -1827,7 +1840,7 @@ struct ieee80211_link_data *link, u64 changed); void ieee80211_configure_filter(struct ieee80211_local *local); -u32 ieee80211_reset_erp_info(struct ieee80211_sub_if_data *sdata); +u64 ieee80211_reset_erp_info(struct ieee80211_sub_if_data *sdata); u64 ieee80211_mgmt_tx_cookie(struct ieee80211_local *local); int ieee80211_attach_ack_skb(struct ieee80211_local *local, struct sk_buff *skb, @@ -1855,7 +1868,6 @@ struct ieee80211_sub_if_data *sdata); void ieee80211_recalc_ps(struct ieee80211_local *local); void ieee80211_recalc_ps_vif(struct ieee80211_sub_if_data *sdata); -int ieee80211_set_arp_filter(struct ieee80211_sub_if_data *sdata); void ieee80211_sta_work(struct ieee80211_sub_if_data *sdata); void ieee80211_sta_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata, struct sk_buff *skb); @@ -1887,8 +1899,10 @@ void ieee80211_ibss_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata, struct sk_buff *skb); int ieee80211_ibss_csa_beacon(struct ieee80211_sub_if_data *sdata, - struct cfg80211_csa_settings *csa_settings); -int ieee80211_ibss_finish_csa(struct ieee80211_sub_if_data *sdata); + struct cfg80211_csa_settings *csa_settings, + u64 *changed); +int ieee80211_ibss_finish_csa(struct ieee80211_sub_if_data *sdata, + u64 *changed); void ieee80211_ibss_stop(struct ieee80211_sub_if_data *sdata); /* OCB code */ @@ -1905,22 +1919,26 @@ void ieee80211_mesh_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata, struct sk_buff *skb); int ieee80211_mesh_csa_beacon(struct ieee80211_sub_if_data *sdata, - struct cfg80211_csa_settings *csa_settings); -int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata); + struct cfg80211_csa_settings *csa_settings, + u64 *changed); +int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata, + u64 *changed); /* scan/BSS handling */ -void ieee80211_scan_work(struct work_struct *work); +void ieee80211_scan_work(struct wiphy *wiphy, struct wiphy_work *work); int ieee80211_request_ibss_scan(struct ieee80211_sub_if_data *sdata, const u8 *ssid, u8 ssid_len, struct ieee80211_channel **channels, - unsigned int n_channels, - enum nl80211_bss_scan_width scan_width); + unsigned int n_channels); int ieee80211_request_scan(struct ieee80211_sub_if_data *sdata, struct cfg80211_scan_request *req); void ieee80211_scan_cancel(struct ieee80211_local *local); void ieee80211_run_deferred_scan(struct ieee80211_local *local); void ieee80211_scan_rx(struct ieee80211_local *local, struct sk_buff *skb); +void ieee80211_inform_bss(struct wiphy *wiphy, struct cfg80211_bss *bss, + const struct cfg80211_bss_ies *ies, void *data); + void ieee80211_mlme_notify_scan_completed(struct ieee80211_local *local); struct ieee80211_bss * ieee80211_bss_info_update(struct ieee80211_local *local, @@ -1939,7 +1957,8 @@ struct cfg80211_sched_scan_request *req); int ieee80211_request_sched_scan_stop(struct ieee80211_local *local); void ieee80211_sched_scan_end(struct ieee80211_local *local); -void ieee80211_sched_scan_stopped_work(struct work_struct *work); +void ieee80211_sched_scan_stopped_work(struct wiphy *wiphy, + struct wiphy_work *work); /* off-channel/mgmt-tx */ void ieee80211_offchannel_stop_vifs(struct ieee80211_local *local); @@ -1959,19 +1978,20 @@ struct wireless_dev *wdev, u64 cookie); /* channel switch handling */ -void ieee80211_csa_finalize_work(struct work_struct *work); +void ieee80211_csa_finalize_work(struct wiphy *wiphy, struct wiphy_work *work); int ieee80211_channel_switch(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_csa_settings *params); /* color change handling */ -void ieee80211_color_change_finalize_work(struct work_struct *work); +void ieee80211_color_change_finalize_work(struct wiphy *wiphy, + struct wiphy_work *work); void ieee80211_color_collision_detection_work(struct work_struct *work); /* interface handling */ #define MAC80211_SUPPORTED_FEATURES_TX (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | \ NETIF_F_HW_CSUM | NETIF_F_SG | \ NETIF_F_HIGHDMA | NETIF_F_GSO_SOFTWARE | \ - NETIF_F_HW_TC) + NETIF_F_LLTX) #define MAC80211_SUPPORTED_FEATURES_RX (NETIF_F_RXCSUM) #define MAC80211_SUPPORTED_FEATURES (MAC80211_SUPPORTED_FEATURES_TX | \ MAC80211_SUPPORTED_FEATURES_RX) @@ -2013,8 +2033,11 @@ struct ieee80211_bss_conf *link_conf); void ieee80211_link_stop(struct ieee80211_link_data *link); int ieee80211_vif_set_links(struct ieee80211_sub_if_data *sdata, - u16 new_links); -void ieee80211_vif_clear_links(struct ieee80211_sub_if_data *sdata); + u16 new_links, u16 dormant_links); +static inline void ieee80211_vif_clear_links(struct ieee80211_sub_if_data *sdata) +{ + ieee80211_vif_set_links(sdata, 0, 0); +} /* tx handling */ void ieee80211_clear_tx_pending(struct ieee80211_local *local); @@ -2036,7 +2059,7 @@ ieee80211_build_data_template(struct ieee80211_sub_if_data *sdata, struct sk_buff *skb, u32 info_flags); void ieee80211_tx_monitor(struct ieee80211_local *local, struct sk_buff *skb, - int retry_count, int shift, bool send_to_cooked, + int retry_count, bool send_to_cooked, struct ieee80211_tx_status *status); void ieee80211_check_fast_xmit(struct sta_info *sta); @@ -2069,15 +2092,13 @@ u16 initiator, u16 reason_code); int ieee80211_send_smps_action(struct ieee80211_sub_if_data *sdata, enum ieee80211_smps_mode smps, const u8 *da, - const u8 *bssid); + const u8 *bssid, int link_id); bool ieee80211_smps_is_restrictive(enum ieee80211_smps_mode smps_mode_old, enum ieee80211_smps_mode smps_mode_new); -void ___ieee80211_stop_rx_ba_session(struct sta_info *sta, u16 tid, - u16 initiator, u16 reason, bool stop); void __ieee80211_stop_rx_ba_session(struct sta_info *sta, u16 tid, u16 initiator, u16 reason, bool stop); -void ___ieee80211_start_rx_ba_session(struct sta_info *sta, +void __ieee80211_start_rx_ba_session(struct sta_info *sta, u8 dialog_token, u16 timeout, u16 start_seq_num, u16 ba_policy, u16 tid, u16 buf_size, bool tx, bool auto_seq, @@ -2098,13 +2119,11 @@ int __ieee80211_stop_tx_ba_session(struct sta_info *sta, u16 tid, enum ieee80211_agg_stop_reason reason); -int ___ieee80211_stop_tx_ba_session(struct sta_info *sta, u16 tid, - enum ieee80211_agg_stop_reason reason); void ieee80211_start_tx_ba_cb(struct sta_info *sta, int tid, struct tid_ampdu_tx *tid_tx); void ieee80211_stop_tx_ba_cb(struct sta_info *sta, int tid, struct tid_ampdu_tx *tid_tx); -void ieee80211_ba_session_work(struct work_struct *work); +void ieee80211_ba_session_work(struct wiphy *wiphy, struct wiphy_work *work); void ieee80211_tx_ba_session_handle_start(struct sta_info *sta, int tid); void ieee80211_release_reorder_timeout(struct sta_info *sta, int tid); @@ -2117,6 +2136,7 @@ ieee80211_vht_cap_ie_to_sta_vht_cap(struct ieee80211_sub_if_data *sdata, struct ieee80211_supported_band *sband, const struct ieee80211_vht_cap *vht_cap_ie, + const struct ieee80211_vht_cap *vht_cap_ie2, struct link_sta_info *link_sta); enum ieee80211_sta_rx_bandwidth ieee80211_sta_cap_rx_bw(struct link_sta_info *link_sta); @@ -2181,7 +2201,7 @@ * flags from &enum ieee80211_conn_flags. * @bssid: the currently connected bssid (for reporting) * @csa_ie: parsed 802.11 csa elements on count, mode, chandef and mesh ttl. - All of them will be filled with if success only. + * All of them will be filled with if success only. * Return: 0 on success, <0 on error and >0 if there is nothing to parse. */ int ieee80211_parse_ch_switch_ie(struct ieee80211_sub_if_data *sdata, @@ -2213,8 +2233,7 @@ /* utility functions/constants */ extern const void *const mac80211_wiphy_privid; /* for wiphy privid */ int ieee80211_frame_duration(enum nl80211_band band, size_t len, - int rate, int erp, int short_preamble, - int shift); + int rate, int erp, int short_preamble); void ieee80211_regulatory_limit_wmm_params(struct ieee80211_sub_if_data *sdata, struct ieee80211_tx_queue_params *qparam, int ac); @@ -2269,8 +2288,6 @@ * (or re-association) response frame if this is given * @from_ap: frame is received from an AP (currently used only * for EHT capabilities parsing) - * @scratch_len: if non zero, specifies the requested length of the scratch - * buffer; otherwise, 'len' is used. */ struct ieee80211_elems_parse_params { const u8 *start; @@ -2281,7 +2298,6 @@ struct cfg80211_bss *bss; int link_id; bool from_ap; - size_t scratch_len; }; struct ieee802_11_elems * @@ -2305,6 +2321,10 @@ return ieee802_11_parse_elems_full(¶ms); } +u32 ieee802_11_parse_mesh_vendor_elems(const u8 *start, size_t len, bool action, + struct ieee802_11_mesh_vendor_specific_elems *elems, + u64 filter, u32 crc, u8 type); + static inline struct ieee802_11_elems * ieee802_11_parse_elems(const u8 *start, size_t len, bool action, struct cfg80211_bss *bss) @@ -2312,8 +2332,6 @@ return ieee802_11_parse_elems_crc(start, len, action, 0, 0, bss); } -void ieee80211_fragment_element(struct sk_buff *skb, u8 *len_pos, u8 frag_id); - extern const int ieee802_1d_to_ac[8]; static inline int ieee80211_ac_from_tid(int tid) @@ -2321,8 +2339,10 @@ return ieee802_1d_to_ac[tid & 7]; } -void ieee80211_dynamic_ps_enable_work(struct work_struct *work); -void ieee80211_dynamic_ps_disable_work(struct work_struct *work); +void ieee80211_dynamic_ps_enable_work(struct wiphy *wiphy, + struct wiphy_work *work); +void ieee80211_dynamic_ps_disable_work(struct wiphy *wiphy, + struct wiphy_work *work); void ieee80211_dynamic_ps_timer(struct timer_list *t); void ieee80211_send_nullfunc(struct ieee80211_local *local, struct ieee80211_sub_if_data *sdata, @@ -2407,6 +2427,7 @@ struct txq_info *txq, int tid); void ieee80211_txq_purge(struct ieee80211_local *local, struct txq_info *txqi); +void ieee80211_purge_sta_txqs(struct sta_info *sta); void ieee80211_txq_remove_vlan(struct ieee80211_local *local, struct ieee80211_sub_if_data *sdata); void ieee80211_fill_txq_stats(struct cfg80211_txq_stats *txqstats, @@ -2421,6 +2442,7 @@ const u8 *da, const u8 *bssid, u16 stype, u16 reason, bool send_frame, u8 *frame_buf); +u8 *ieee80211_write_he_6ghz_cap(u8 *pos, __le16 cap, u8 *end); enum { IEEE80211_PROBE_FLAG_DIRECTED = BIT(0), @@ -2499,7 +2521,7 @@ const struct ieee80211_vht_operation *oper, const struct ieee80211_ht_operation *htop, struct cfg80211_chan_def *chandef); -void ieee80211_chandef_eht_oper(const struct ieee80211_eht_operation *eht_oper, +void ieee80211_chandef_eht_oper(const struct ieee80211_eht_operation_info *info, bool support_160, bool support_320, struct cfg80211_chan_def *chandef); bool ieee80211_chandef_he_6ghz_oper(struct ieee80211_sub_if_data *sdata, @@ -2541,10 +2563,10 @@ struct ieee80211_link_data *rsvd_for); bool ieee80211_is_radar_required(struct ieee80211_local *local); -void ieee80211_dfs_cac_timer(unsigned long data); -void ieee80211_dfs_cac_timer_work(struct work_struct *work); +void ieee80211_dfs_cac_timer_work(struct wiphy *wiphy, struct wiphy_work *work); void ieee80211_dfs_cac_cancel(struct ieee80211_local *local); -void ieee80211_dfs_radar_detected_work(struct work_struct *work); +void ieee80211_dfs_radar_detected_work(struct wiphy *wiphy, + struct wiphy_work *work); int ieee80211_send_action_csa(struct ieee80211_sub_if_data *sdata, struct cfg80211_csa_settings *csa_settings); @@ -2560,13 +2582,13 @@ /* TDLS */ int ieee80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev, - const u8 *peer, u8 action_code, u8 dialog_token, - u16 status_code, u32 peer_capability, - bool initiator, const u8 *extra_ies, - size_t extra_ies_len); + const u8 *peer, int link_id, + u8 action_code, u8 dialog_token, u16 status_code, + u32 peer_capability, bool initiator, + const u8 *extra_ies, size_t extra_ies_len); int ieee80211_tdls_oper(struct wiphy *wiphy, struct net_device *dev, const u8 *peer, enum nl80211_tdls_operation oper); -void ieee80211_tdls_peer_del_work(struct work_struct *wk); +void ieee80211_tdls_peer_del_work(struct wiphy *wiphy, struct wiphy_work *wk); int ieee80211_tdls_channel_switch(struct wiphy *wiphy, struct net_device *dev, const u8 *addr, u8 oper_class, struct cfg80211_chan_def *chandef); diff -ruw linux-6.4/net/mac80211/iface.c linux-6.4-fbx/net/mac80211/iface.c --- linux-6.4/net/mac80211/iface.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/iface.c 2023-12-12 17:24:34.175627535 +0100 @@ -8,7 +8,7 @@ * Copyright 2008, Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright (c) 2016 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation */ #include #include @@ -26,6 +26,7 @@ #include "driver-ops.h" #include "wme.h" #include "rate.h" +#include "fbx_scum.h" /** * DOC: Interface list locking @@ -33,17 +34,16 @@ * The interface list in each struct ieee80211_local is protected * three-fold: * - * (1) modifications may only be done under the RTNL - * (2) modifications and readers are protected against each other by - * the iflist_mtx. - * (3) modifications are done in an RCU manner so atomic readers + * (1) modifications may only be done under the RTNL *and* wiphy mutex + * *and* iflist_mtx + * (2) modifications are done in an RCU manner so atomic readers * can traverse the list in RCU-safe blocks. * * As a consequence, reads (traversals) of the list can be protected - * by either the RTNL, the iflist_mtx or RCU. + * by either the RTNL, the wiphy mutex, the iflist_mtx or RCU. */ -static void ieee80211_iface_work(struct work_struct *work); +static void ieee80211_iface_work(struct wiphy *wiphy, struct wiphy_work *work); bool __ieee80211_recalc_txpower(struct ieee80211_sub_if_data *sdata) { @@ -110,7 +110,7 @@ bool working, scanning, active; unsigned int led_trig_start = 0, led_trig_stop = 0; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); active = force_active || !list_empty(&local->chanctx_list) || @@ -160,6 +160,8 @@ u8 *m; int ret = 0; + lockdep_assert_wiphy(local->hw.wiphy); + if (is_zero_ether_addr(local->hw.wiphy->addr_mask)) return 0; @@ -176,7 +178,6 @@ if (!check_dup) return ret; - mutex_lock(&local->iflist_mtx); list_for_each_entry(iter, &local->interfaces, list) { if (iter == sdata) continue; @@ -195,7 +196,6 @@ break; } } - mutex_unlock(&local->iflist_mtx); return ret; } @@ -207,6 +207,8 @@ struct ieee80211_sub_if_data *scan_sdata; int ret = 0; + lockdep_assert_wiphy(local->hw.wiphy); + /* To be the most flexible here we want to only limit changing the * address if the specific interface is doing offchannel work or * scanning. @@ -214,8 +216,6 @@ if (netif_carrier_ok(sdata->dev)) return -EBUSY; - mutex_lock(&local->mtx); - /* First check no ROC work is happening on this iface */ list_for_each_entry(roc, &local->roc_list, list) { if (roc->sdata != sdata) @@ -230,7 +230,7 @@ /* And if this iface is scanning */ if (local->scanning) { scan_sdata = rcu_dereference_protected(local->scan_sdata, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (sdata == scan_sdata) ret = -EBUSY; } @@ -247,13 +247,12 @@ } unlock: - mutex_unlock(&local->mtx); return ret; } -static int ieee80211_change_mac(struct net_device *dev, void *addr) +static int _ieee80211_change_mac(struct ieee80211_sub_if_data *sdata, + void *addr) { - struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ieee80211_local *local = sdata->local; struct sockaddr *sa = addr; bool check_dup = true; @@ -278,7 +277,7 @@ if (live) drv_remove_interface(local, sdata); - ret = eth_mac_addr(dev, sa); + ret = eth_mac_addr(sdata->dev, sa); if (ret == 0) { memcpy(sdata->vif.addr, sa->sa_data, ETH_ALEN); @@ -294,6 +293,27 @@ return ret; } +static int ieee80211_change_mac(struct net_device *dev, void *addr) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; + int ret; + + /* + * This happens during unregistration if there's a bond device + * active (maybe other cases?) and we must get removed from it. + * But we really don't care anymore if it's not registered now. + */ + if (!dev->ieee80211_ptr->registered) + return 0; + + wiphy_lock(local->hw.wiphy); + ret = _ieee80211_change_mac(sdata, addr); + wiphy_unlock(local->hw.wiphy); + + return ret; +} + static inline int identical_mac_addr_allowed(int type1, int type2) { return type1 == NL80211_IFTYPE_MONITOR || @@ -311,9 +331,9 @@ { struct ieee80211_local *local = sdata->local; struct ieee80211_sub_if_data *nsdata; - int ret; ASSERT_RTNL(); + lockdep_assert_wiphy(local->hw.wiphy); /* we hold the RTNL here so can safely walk the list */ list_for_each_entry(nsdata, &local->interfaces, list) { @@ -378,10 +398,7 @@ } } - mutex_lock(&local->chanctx_mtx); - ret = ieee80211_check_combinations(sdata, NULL, 0, 0); - mutex_unlock(&local->chanctx_mtx); - return ret; + return ieee80211_check_combinations(sdata, NULL, 0, 0); } static int ieee80211_check_queues(struct ieee80211_sub_if_data *sdata, @@ -430,12 +447,13 @@ if (!is_valid_ether_addr(dev->dev_addr)) return -EADDRNOTAVAIL; + wiphy_lock(sdata->local->hw.wiphy); err = ieee80211_check_concurrent_iface(sdata, sdata->vif.type); if (err) - return err; + goto out; - wiphy_lock(sdata->local->hw.wiphy); err = ieee80211_do_open(&sdata->wdev, true); +out: wiphy_unlock(sdata->local->hw.wiphy); return err; @@ -453,6 +471,8 @@ bool cancel_scan; struct cfg80211_nan_func *func; + lockdep_assert_wiphy(local->hw.wiphy); + clear_bit(SDATA_STATE_RUNNING, &sdata->state); synchronize_rcu(); /* flush _ieee80211_wake_txqs() */ @@ -472,6 +492,8 @@ case NL80211_IFTYPE_MONITOR: if (sdata->u.mntr.flags & MONITOR_FLAG_COOK_FRAMES) break; + if (fbx80211_skip_mon(sdata)) + break; list_del_rcu(&sdata->u.mntr.list); break; default: @@ -516,16 +538,12 @@ } del_timer_sync(&local->dynamic_ps_timer); - cancel_work_sync(&local->dynamic_ps_enable_work); - - cancel_work_sync(&sdata->recalc_smps); + wiphy_work_cancel(local->hw.wiphy, &local->dynamic_ps_enable_work); - sdata_lock(sdata); - WARN(sdata->vif.valid_links, + WARN(ieee80211_vif_is_mld(&sdata->vif), "destroying interface with valid links 0x%04x\n", sdata->vif.valid_links); - mutex_lock(&local->mtx); sdata->vif.bss_conf.csa_active = false; if (sdata->vif.type == NL80211_IFTYPE_STATION) sdata->deflink.u.mgd.csa_waiting_bcn = false; @@ -534,20 +552,17 @@ IEEE80211_QUEUE_STOP_REASON_CSA); sdata->deflink.csa_block_tx = false; } - mutex_unlock(&local->mtx); - sdata_unlock(sdata); - - cancel_work_sync(&sdata->deflink.csa_finalize_work); - cancel_work_sync(&sdata->deflink.color_change_finalize_work); - cancel_delayed_work_sync(&sdata->deflink.dfs_cac_timer_work); + wiphy_work_cancel(local->hw.wiphy, &sdata->deflink.csa_finalize_work); + wiphy_work_cancel(local->hw.wiphy, + &sdata->deflink.color_change_finalize_work); + wiphy_delayed_work_cancel(local->hw.wiphy, + &sdata->deflink.dfs_cac_timer_work); if (sdata->wdev.cac_started) { chandef = sdata->vif.bss_conf.chandef; WARN_ON(local->suspended); - mutex_lock(&local->mtx); ieee80211_link_release_channel(&sdata->deflink); - mutex_unlock(&local->mtx); cfg80211_cac_event(sdata->dev, &chandef, NL80211_RADAR_CAC_ABORTED, GFP_KERNEL); @@ -575,9 +590,7 @@ switch (sdata->vif.type) { case NL80211_IFTYPE_AP_VLAN: - mutex_lock(&local->mtx); list_del(&sdata->u.vlan.list); - mutex_unlock(&local->mtx); RCU_INIT_POINTER(sdata->vif.bss_conf.chanctx_conf, NULL); /* see comment in the default case below */ ieee80211_free_keys(sdata, true); @@ -614,7 +627,7 @@ RCU_INIT_POINTER(local->p2p_sdata, NULL); fallthrough; default: - cancel_work_sync(&sdata->work); + wiphy_work_cancel(sdata->local->hw.wiphy, &sdata->work); /* * When we get here, the interface is marked down. * Free the remaining keys, if there are any @@ -675,9 +688,7 @@ if (local->monitors == 0) ieee80211_del_virtual_monitor(local); - mutex_lock(&local->mtx); ieee80211_recalc_idle(local); - mutex_unlock(&local->mtx); if (!(sdata->u.mntr.flags & MONITOR_FLAG_ACTIVE)) break; @@ -691,7 +702,7 @@ ieee80211_recalc_ps(local); if (cancel_scan) - flush_delayed_work(&local->scan_work); + wiphy_delayed_work_flush(local->hw.wiphy, &local->scan_work); if (local->open_count == 0) { ieee80211_stop_device(local); @@ -750,9 +761,9 @@ ieee80211_stop_mbssid(sdata); } - cancel_work_sync(&sdata->activate_links_work); - wiphy_lock(sdata->local->hw.wiphy); + wiphy_work_cancel(sdata->local->hw.wiphy, &sdata->activate_links_work); + ieee80211_do_stop(sdata, true); wiphy_unlock(sdata->local->hw.wiphy); @@ -779,7 +790,7 @@ spin_lock_bh(&local->filter_lock); __hw_addr_sync(&local->mc_list, &dev->mc, dev->addr_len); spin_unlock_bh(&local->filter_lock); - ieee80211_queue_work(&local->hw, &local->reconfig_filter); + wiphy_work_queue(local->hw.wiphy, &local->reconfig_filter); } /* @@ -788,6 +799,9 @@ */ static void ieee80211_teardown_sdata(struct ieee80211_sub_if_data *sdata) { + if (sdata->vif.type == NL80211_IFTYPE_MONITOR) + fbx80211_scum_teardown(sdata); + /* free extra data */ ieee80211_free_keys(sdata, false); @@ -1046,7 +1060,7 @@ if (!ieee80211_hw_check(&local->hw, SUPPORTS_TX_ENCAP_OFFLOAD)) return; - mutex_lock(&local->iflist_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(sdata, &local->interfaces, list) { if (!ieee80211_sdata_running(sdata)) @@ -1054,8 +1068,6 @@ ieee80211_recalc_sdata_offload(sdata); } - - mutex_unlock(&local->iflist_mtx); } void ieee80211_adjust_monitor_flags(struct ieee80211_sub_if_data *sdata, @@ -1133,6 +1145,7 @@ snprintf(sdata->name, IFNAMSIZ, "%s-monitor", wiphy_name(local->hw.wiphy)); sdata->wdev.iftype = NL80211_IFTYPE_MONITOR; + sdata->wdev.wiphy = local->hw.wiphy; ieee80211_sdata_init(local, sdata); @@ -1157,10 +1170,8 @@ rcu_assign_pointer(local->monitor_sdata, sdata); mutex_unlock(&local->iflist_mtx); - mutex_lock(&local->mtx); ret = ieee80211_link_use_channel(&sdata->deflink, &local->monitor_chandef, IEEE80211_CHANCTX_EXCLUSIVE); - mutex_unlock(&local->mtx); if (ret) { mutex_lock(&local->iflist_mtx); RCU_INIT_POINTER(local->monitor_sdata, NULL); @@ -1173,7 +1184,7 @@ skb_queue_head_init(&sdata->skb_queue); skb_queue_head_init(&sdata->status_queue); - INIT_WORK(&sdata->work, ieee80211_iface_work); + wiphy_work_init(&sdata->work, ieee80211_iface_work); return 0; } @@ -1202,9 +1213,7 @@ synchronize_net(); - mutex_lock(&local->mtx); ieee80211_link_release_channel(&sdata->deflink); - mutex_unlock(&local->mtx); drv_remove_interface(local, sdata); @@ -1221,10 +1230,12 @@ struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); struct net_device *dev = wdev->netdev; struct ieee80211_local *local = sdata->local; - u32 changed = 0; + u64 changed = 0; int res; u32 hw_reconf_flags = 0; + lockdep_assert_wiphy(local->hw.wiphy); + switch (sdata->vif.type) { case NL80211_IFTYPE_AP_VLAN: { struct ieee80211_sub_if_data *master; @@ -1232,9 +1243,7 @@ if (!sdata->bss) return -ENOLINK; - mutex_lock(&local->mtx); list_add(&sdata->u.vlan.list, &sdata->bss->vlans); - mutex_unlock(&local->mtx); master = container_of(sdata->bss, struct ieee80211_sub_if_data, u.ap); @@ -1251,10 +1260,8 @@ sizeof(sdata->vif.hw_queue)); sdata->vif.bss_conf.chandef = master->vif.bss_conf.chandef; - mutex_lock(&local->key_mtx); sdata->crypto_tx_tailroom_needed_cnt += master->crypto_tx_tailroom_needed_cnt; - mutex_unlock(&local->key_mtx); break; } @@ -1281,6 +1288,9 @@ } if (local->open_count == 0) { + /* here we can consider everything in good order (again) */ + local->reconfig_failure = false; + res = drv_start(local); if (res) goto err_del_bss; @@ -1342,9 +1352,7 @@ ieee80211_adjust_monitor_flags(sdata, 1); ieee80211_configure_filter(local); ieee80211_recalc_offload(local); - mutex_lock(&local->mtx); ieee80211_recalc_idle(local); - mutex_unlock(&local->mtx); netif_carrier_on(dev); break; @@ -1417,6 +1425,8 @@ case NL80211_IFTYPE_MONITOR: if (sdata->u.mntr.flags & MONITOR_FLAG_COOK_FRAMES) break; + if (fbx80211_skip_mon(sdata)) + break; list_add_tail_rcu(&sdata->u.mntr.list, &local->mon_list); break; default: @@ -1449,11 +1459,8 @@ drv_stop(local); err_del_bss: sdata->bss = NULL; - if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) { - mutex_lock(&local->mtx); + if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) list_del(&sdata->u.vlan.list); - mutex_unlock(&local->mtx); - } /* might already be clear but that doesn't matter */ clear_bit(SDATA_STATE_RUNNING, &sdata->state); return res; @@ -1480,12 +1487,13 @@ { struct ieee80211_mgmt *mgmt = (void *)skb->data; + lockdep_assert_wiphy(local->hw.wiphy); + if (ieee80211_is_action(mgmt->frame_control) && mgmt->u.action.category == WLAN_CATEGORY_BACK) { struct sta_info *sta; int len = skb->len; - mutex_lock(&local->sta_mtx); sta = sta_info_get_bss(sdata, mgmt->sa); if (sta) { switch (mgmt->u.action.u.addba_req.action_code) { @@ -1506,7 +1514,6 @@ break; } } - mutex_unlock(&local->sta_mtx); } else if (ieee80211_is_action(mgmt->frame_control) && mgmt->u.action.category == WLAN_CATEGORY_VHT) { switch (mgmt->u.action.u.vht_group_notif.action_code) { @@ -1520,7 +1527,6 @@ band = status->band; opmode = mgmt->u.action.u.vht_opmode_notif.operating_mode; - mutex_lock(&local->sta_mtx); sta = sta_info_get_bss(sdata, mgmt->sa); if (sta) @@ -1528,7 +1534,6 @@ &sta->deflink, opmode, band); - mutex_unlock(&local->sta_mtx); break; } case WLAN_VHT_ACTION_GROUPID_MGMT: @@ -1575,7 +1580,6 @@ * a block-ack session was active. That cannot be * right, so terminate the session. */ - mutex_lock(&local->sta_mtx); sta = sta_info_get_bss(sdata, mgmt->sa); if (sta) { u16 tid = ieee80211_get_tid(hdr); @@ -1585,7 +1589,6 @@ WLAN_REASON_QSTA_REQUIRE_SETUP, true); } - mutex_unlock(&local->sta_mtx); } else switch (sdata->vif.type) { case NL80211_IFTYPE_STATION: ieee80211_sta_rx_queued_mgmt(sdata, skb); @@ -1622,7 +1625,7 @@ } } -static void ieee80211_iface_work(struct work_struct *work) +static void ieee80211_iface_work(struct wiphy *wiphy, struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata = container_of(work, struct ieee80211_sub_if_data, work); @@ -1682,15 +1685,8 @@ } } -static void ieee80211_recalc_smps_work(struct work_struct *work) -{ - struct ieee80211_sub_if_data *sdata = - container_of(work, struct ieee80211_sub_if_data, recalc_smps); - - ieee80211_recalc_smps(sdata, &sdata->deflink); -} - -static void ieee80211_activate_links_work(struct work_struct *work) +static void ieee80211_activate_links_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata = container_of(work, struct ieee80211_sub_if_data, @@ -1734,9 +1730,9 @@ skb_queue_head_init(&sdata->skb_queue); skb_queue_head_init(&sdata->status_queue); - INIT_WORK(&sdata->work, ieee80211_iface_work); - INIT_WORK(&sdata->recalc_smps, ieee80211_recalc_smps_work); - INIT_WORK(&sdata->activate_links_work, ieee80211_activate_links_work); + wiphy_work_init(&sdata->work, ieee80211_iface_work); + wiphy_work_init(&sdata->activate_links_work, + ieee80211_activate_links_work); switch (type) { case NL80211_IFTYPE_P2P_GO: @@ -1775,6 +1771,7 @@ sdata->dev->netdev_ops = &ieee80211_monitorif_ops; sdata->u.mntr.flags = MONITOR_FLAG_CONTROL | MONITOR_FLAG_OTHER_BSS; + fbx80211_scum_setup(sdata); break; case NL80211_IFTYPE_NAN: idr_init(&sdata->u.nan.function_inst_ids); @@ -1795,7 +1792,7 @@ /* need to do this after the switch so vif.type is correct */ ieee80211_link_setup(&sdata->deflink); - ieee80211_debugfs_add_netdev(sdata); + ieee80211_debugfs_add_netdev(sdata, false); } static int ieee80211_runtime_change_iftype(struct ieee80211_sub_if_data *sdata, @@ -1812,7 +1809,7 @@ return -EBUSY; /* for now, don't support changing while links exist */ - if (sdata->vif.valid_links) + if (ieee80211_vif_is_mld(&sdata->vif)) return -EBUSY; switch (sdata->vif.type) { @@ -1926,6 +1923,8 @@ u8 tmp_addr[ETH_ALEN]; int i; + lockdep_assert_wiphy(local->hw.wiphy); + /* default ... something at least */ memcpy(perm_addr, local->hw.wiphy->perm_addr, ETH_ALEN); @@ -1933,8 +1932,6 @@ local->hw.wiphy->n_addresses <= 1) return; - mutex_lock(&local->iflist_mtx); - switch (type) { case NL80211_IFTYPE_MONITOR: /* doesn't matter */ @@ -1958,7 +1955,7 @@ if (!ieee80211_sdata_running(sdata)) continue; memcpy(perm_addr, sdata->vif.addr, ETH_ALEN); - goto out_unlock; + return; } } fallthrough; @@ -2044,9 +2041,6 @@ break; } - - out_unlock: - mutex_unlock(&local->iflist_mtx); } int ieee80211_if_add(struct ieee80211_local *local, const char *name, @@ -2060,6 +2054,7 @@ int ret, i; ASSERT_RTNL(); + lockdep_assert_wiphy(local->hw.wiphy); if (type == NL80211_IFTYPE_P2P_DEVICE || type == NL80211_IFTYPE_NAN) { struct wireless_dev *wdev; @@ -2147,7 +2142,7 @@ INIT_LIST_HEAD(&sdata->key_list); - INIT_DELAYED_WORK(&sdata->dec_tailroom_needed_wk, + wiphy_delayed_work_init(&sdata->dec_tailroom_needed_wk, ieee80211_delayed_tailroom_dec); for (i = 0; i < NUM_NL80211_BANDS; i++) { @@ -2226,6 +2221,7 @@ void ieee80211_if_remove(struct ieee80211_sub_if_data *sdata) { ASSERT_RTNL(); + lockdep_assert_wiphy(sdata->local->hw.wiphy); mutex_lock(&sdata->local->iflist_mtx); list_del_rcu(&sdata->list); @@ -2255,7 +2251,6 @@ { struct ieee80211_sub_if_data *sdata, *tmp; LIST_HEAD(unreg_list); - LIST_HEAD(wdev_list); ASSERT_RTNL(); @@ -2272,28 +2267,34 @@ */ cfg80211_shutdown_all_interfaces(local->hw.wiphy); + wiphy_lock(local->hw.wiphy); + WARN(local->open_count, "%s: open count remains %d\n", wiphy_name(local->hw.wiphy), local->open_count); - ieee80211_txq_teardown_flows(local); - mutex_lock(&local->iflist_mtx); - list_for_each_entry_safe(sdata, tmp, &local->interfaces, list) { - list_del(&sdata->list); - - if (sdata->dev) - unregister_netdevice_queue(sdata->dev, &unreg_list); - else - list_add(&sdata->list, &wdev_list); - } + list_splice_init(&local->interfaces, &unreg_list); mutex_unlock(&local->iflist_mtx); - unregister_netdevice_many(&unreg_list); + list_for_each_entry_safe(sdata, tmp, &unreg_list, list) { + bool netdev = sdata->dev; + + /* + * Remove IP addresses explicitly, since the notifier will + * skip the callbacks if wdev->registered is false, since + * we can't acquire the wiphy_lock() again there if already + * inside this locked section. + */ + sdata->vif.cfg.arp_addr_cnt = 0; + if (sdata->vif.type == NL80211_IFTYPE_STATION && + sdata->u.mgd.associated) + ieee80211_vif_cfg_change_notify(sdata, + BSS_CHANGED_ARP_FILTER); - wiphy_lock(local->hw.wiphy); - list_for_each_entry_safe(sdata, tmp, &wdev_list, list) { list_del(&sdata->list); cfg80211_unregister_wdev(&sdata->wdev); + + if (!netdev) kfree(sdata); } wiphy_unlock(local->hw.wiphy); diff -ruw linux-6.4/net/mac80211/key.c linux-6.4-fbx/net/mac80211/key.c --- linux-6.4/net/mac80211/key.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/key.c 2023-11-07 13:38:44.078257129 +0100 @@ -6,9 +6,10 @@ * Copyright 2007-2008 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright 2015-2017 Intel Deutschland GmbH - * Copyright 2018-2020, 2022 Intel Corporation + * Copyright 2018-2020, 2022-2023 Intel Corporation */ +#include #include #include #include @@ -17,7 +18,6 @@ #include #include #include -#include #include #include "ieee80211_i.h" #include "driver-ops.h" @@ -53,11 +53,6 @@ static const u8 bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; -static void assert_key_lock(struct ieee80211_local *local) -{ - lockdep_assert_held(&local->key_mtx); -} - static void update_vlan_tailroom_need_count(struct ieee80211_sub_if_data *sdata, int delta) { @@ -67,7 +62,7 @@ return; /* crypto_tx_tailroom_needed_cnt is protected by this */ - assert_key_lock(sdata->local); + lockdep_assert_wiphy(sdata->local->hw.wiphy); rcu_read_lock(); @@ -98,7 +93,7 @@ * http://mid.gmane.org/1308590980.4322.19.camel@jlt3.sipsolutions.net */ - assert_key_lock(sdata->local); + lockdep_assert_wiphy(sdata->local->hw.wiphy); update_vlan_tailroom_need_count(sdata, 1); @@ -114,7 +109,7 @@ static void decrease_tailroom_need_count(struct ieee80211_sub_if_data *sdata, int delta) { - assert_key_lock(sdata->local); + lockdep_assert_wiphy(sdata->local->hw.wiphy); WARN_ON_ONCE(sdata->crypto_tx_tailroom_needed_cnt < delta); @@ -129,6 +124,7 @@ int ret = -EOPNOTSUPP; might_sleep(); + lockdep_assert_wiphy(key->local->hw.wiphy); if (key->flags & KEY_FLAG_TAINTED) { /* If we get here, it's during resume and the key is @@ -151,8 +147,6 @@ if (!key->local->ops->set_key) goto out_unsupported; - assert_key_lock(key->local); - sta = key->sta; /* @@ -172,6 +166,12 @@ * Hence, don't send GTKs for VLAN interfaces to the driver. */ if (!(key->conf.flags & IEEE80211_KEY_FLAG_PAIRWISE)) { + if (ieee80211_hw_check(&key->local->hw, + APVLAN_NEED_MCAST_TO_UCAST)) { + /* no need to fail, this key will + * never be used */ + return 0; + } ret = 1; goto out_unsupported; } @@ -242,14 +242,14 @@ if (!key || !key->local->ops->set_key) return; - assert_key_lock(key->local); - if (!(key->flags & KEY_FLAG_UPLOADED_TO_HARDWARE)) return; sta = key->sta; sdata = key->sdata; + lockdep_assert_wiphy(key->local->hw.wiphy); + if (key->conf.link_id >= 0 && sdata->vif.active_links && !(sdata->vif.active_links & BIT(key->conf.link_id))) return; @@ -275,7 +275,7 @@ struct sta_info *sta = key->sta; struct ieee80211_local *local = key->local; - assert_key_lock(local); + lockdep_assert_wiphy(local->hw.wiphy); set_sta_flag(sta, WLAN_STA_USES_ENCRYPTION); @@ -300,7 +300,7 @@ struct sta_info *sta = new->sta; int i; - assert_key_lock(local); + lockdep_assert_wiphy(local->hw.wiphy); if (new->conf.flags & IEEE80211_KEY_FLAG_NO_AUTO_TX) { /* Extended Key ID key install, initial one or rekey */ @@ -317,11 +317,9 @@ * job done for the few ms we need it.) */ set_sta_flag(sta, WLAN_STA_BLOCK_BA); - mutex_lock(&sta->ampdu_mlme.mtx); for (i = 0; i < IEEE80211_NUM_TIDS; i++) - ___ieee80211_stop_tx_ba_session(sta, i, + __ieee80211_stop_tx_ba_session(sta, i, AGG_STOP_LOCAL_REQUEST); - mutex_unlock(&sta->ampdu_mlme.mtx); } } else if (old) { /* Rekey without Extended Key ID. @@ -358,12 +356,14 @@ struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_key *key = NULL; - assert_key_lock(sdata->local); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (idx >= 0 && idx < NUM_DEFAULT_KEYS) { - key = key_mtx_dereference(sdata->local, sdata->keys[idx]); + key = wiphy_dereference(sdata->local->hw.wiphy, + sdata->keys[idx]); if (!key) - key = key_mtx_dereference(sdata->local, link->gtk[idx]); + key = wiphy_dereference(sdata->local->hw.wiphy, + link->gtk[idx]); } if (uni) { @@ -382,9 +382,9 @@ void ieee80211_set_default_key(struct ieee80211_link_data *link, int idx, bool uni, bool multi) { - mutex_lock(&link->sdata->local->key_mtx); + lockdep_assert_wiphy(link->sdata->local->hw.wiphy); + __ieee80211_set_default_key(link, idx, uni, multi); - mutex_unlock(&link->sdata->local->key_mtx); } static void @@ -393,11 +393,12 @@ struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_key *key = NULL; - assert_key_lock(sdata->local); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (idx >= NUM_DEFAULT_KEYS && idx < NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS) - key = key_mtx_dereference(sdata->local, link->gtk[idx]); + key = wiphy_dereference(sdata->local->hw.wiphy, + link->gtk[idx]); rcu_assign_pointer(link->default_mgmt_key, key); @@ -407,9 +408,9 @@ void ieee80211_set_default_mgmt_key(struct ieee80211_link_data *link, int idx) { - mutex_lock(&link->sdata->local->key_mtx); + lockdep_assert_wiphy(link->sdata->local->hw.wiphy); + __ieee80211_set_default_mgmt_key(link, idx); - mutex_unlock(&link->sdata->local->key_mtx); } static void @@ -418,12 +419,13 @@ struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_key *key = NULL; - assert_key_lock(sdata->local); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (idx >= NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS && idx < NUM_DEFAULT_KEYS + NUM_DEFAULT_MGMT_KEYS + NUM_DEFAULT_BEACON_KEYS) - key = key_mtx_dereference(sdata->local, link->gtk[idx]); + key = wiphy_dereference(sdata->local->hw.wiphy, + link->gtk[idx]); rcu_assign_pointer(link->default_beacon_key, key); @@ -433,9 +435,9 @@ void ieee80211_set_default_beacon_key(struct ieee80211_link_data *link, int idx) { - mutex_lock(&link->sdata->local->key_mtx); + lockdep_assert_wiphy(link->sdata->local->hw.wiphy); + __ieee80211_set_default_beacon_key(link, idx); - mutex_unlock(&link->sdata->local->key_mtx); } static int ieee80211_key_replace(struct ieee80211_sub_if_data *sdata, @@ -452,6 +454,8 @@ bool defunikey, defmultikey, defmgmtkey, defbeaconkey; bool is_wep; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + /* caller must provide at least one old/new */ if (WARN_ON(!new && !old)) return 0; @@ -482,7 +486,7 @@ if (sta) { link_sta = rcu_dereference_protected(sta->link[link_id], - lockdep_is_held(&sta->local->sta_mtx)); + lockdep_is_held(&sta->local->hw.wiphy->mtx)); if (!link_sta) return -ENOLINK; } @@ -512,6 +516,8 @@ } else { if (!new->local->wowlan) ret = ieee80211_key_enable_hw_accel(new); + else + new->flags |= KEY_FLAG_UPLOADED_TO_HARDWARE; } if (ret) @@ -537,16 +543,16 @@ ieee80211_check_fast_rx(sta); } else { defunikey = old && - old == key_mtx_dereference(sdata->local, + old == wiphy_dereference(sdata->local->hw.wiphy, sdata->default_unicast_key); defmultikey = old && - old == key_mtx_dereference(sdata->local, + old == wiphy_dereference(sdata->local->hw.wiphy, link->default_multicast_key); defmgmtkey = old && - old == key_mtx_dereference(sdata->local, + old == wiphy_dereference(sdata->local->hw.wiphy, link->default_mgmt_key); defbeaconkey = old && - old == key_mtx_dereference(sdata->local, + old == wiphy_dereference(sdata->local->hw.wiphy, link->default_beacon_key); if (defunikey && !new) @@ -771,7 +777,8 @@ if (delay_tailroom) { /* see ieee80211_delayed_tailroom_dec */ sdata->crypto_tx_tailroom_pending_dec++; - schedule_delayed_work(&sdata->dec_tailroom_needed_wk, + wiphy_delayed_work_queue(sdata->local->hw.wiphy, + &sdata->dec_tailroom_needed_wk, HZ/2); } else { decrease_tailroom_need_count(sdata, 1); @@ -798,6 +805,9 @@ void ieee80211_key_free_unused(struct ieee80211_key *key) { + if (!key) + return; + WARN_ON(key->sdata || key->local); ieee80211_key_free_common(key); } @@ -850,58 +860,64 @@ * can cause warnings to appear. */ bool delay_tailroom = sdata->vif.type == NL80211_IFTYPE_STATION; - int ret = -EOPNOTSUPP; + int ret; - mutex_lock(&sdata->local->key_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (sta && pairwise) { struct ieee80211_key *alt_key; - old_key = key_mtx_dereference(sdata->local, sta->ptk[idx]); - alt_key = key_mtx_dereference(sdata->local, sta->ptk[idx ^ 1]); + old_key = wiphy_dereference(sdata->local->hw.wiphy, + sta->ptk[idx]); + alt_key = wiphy_dereference(sdata->local->hw.wiphy, + sta->ptk[idx ^ 1]); /* The rekey code assumes that the old and new key are using * the same cipher. Enforce the assumption for pairwise keys. */ if ((alt_key && alt_key->conf.cipher != key->conf.cipher) || - (old_key && old_key->conf.cipher != key->conf.cipher)) + (old_key && old_key->conf.cipher != key->conf.cipher)) { + ret = -EOPNOTSUPP; goto out; + } } else if (sta) { struct link_sta_info *link_sta = &sta->deflink; int link_id = key->conf.link_id; if (link_id >= 0) { link_sta = rcu_dereference_protected(sta->link[link_id], - lockdep_is_held(&sta->local->sta_mtx)); + lockdep_is_held(&sta->local->hw.wiphy->mtx)); if (!link_sta) { ret = -ENOLINK; goto out; } } - old_key = key_mtx_dereference(sdata->local, link_sta->gtk[idx]); + old_key = wiphy_dereference(sdata->local->hw.wiphy, + link_sta->gtk[idx]); } else { if (idx < NUM_DEFAULT_KEYS) - old_key = key_mtx_dereference(sdata->local, + old_key = wiphy_dereference(sdata->local->hw.wiphy, sdata->keys[idx]); if (!old_key) - old_key = key_mtx_dereference(sdata->local, + old_key = wiphy_dereference(sdata->local->hw.wiphy, link->gtk[idx]); } /* Non-pairwise keys must also not switch the cipher on rekey */ if (!pairwise) { - if (old_key && old_key->conf.cipher != key->conf.cipher) + if (old_key && old_key->conf.cipher != key->conf.cipher) { + ret = -EOPNOTSUPP; goto out; } + } /* * Silently accept key re-installation without really installing the * new version of the key to avoid nonce reuse or replay issues. */ if (ieee80211_key_identical(sdata, old_key, key)) { - ieee80211_key_free_unused(key); - ret = 0; + ret = -EALREADY; goto out; } @@ -926,9 +942,10 @@ ieee80211_key_free(key, delay_tailroom); } - out: - mutex_unlock(&sdata->local->key_mtx); + key = NULL; + out: + ieee80211_key_free_unused(key); return ret; } @@ -954,8 +971,6 @@ lockdep_assert_wiphy(sdata->local->hw.wiphy); - mutex_lock(&sdata->local->key_mtx); - sdata->crypto_tx_tailroom_needed_cnt = 0; sdata->crypto_tx_tailroom_pending_dec = 0; @@ -972,8 +987,6 @@ ieee80211_key_enable_hw_accel(key); } } - - mutex_unlock(&sdata->local->key_mtx); } void ieee80211_iter_keys(struct ieee80211_hw *hw, @@ -991,7 +1004,6 @@ lockdep_assert_wiphy(hw->wiphy); - mutex_lock(&local->key_mtx); if (vif) { sdata = vif_to_sdata(vif); list_for_each_entry_safe(key, tmp, &sdata->key_list, list) @@ -1006,7 +1018,6 @@ key->sta ? &key->sta->sta : NULL, &key->conf, iter_data); } - mutex_unlock(&local->key_mtx); } EXPORT_SYMBOL(ieee80211_iter_keys); @@ -1086,7 +1097,8 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_key *key, *tmp; - mutex_lock(&local->key_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + list_for_each_entry_safe(key, tmp, &sdata->key_list, list) { if (key->conf.link_id != link->link_id) continue; @@ -1095,7 +1107,6 @@ key, NULL); list_add_tail(&key->list, keys); } - mutex_unlock(&local->key_mtx); } void ieee80211_free_key_list(struct ieee80211_local *local, @@ -1103,10 +1114,10 @@ { struct ieee80211_key *key, *tmp; - mutex_lock(&local->key_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + list_for_each_entry_safe(key, tmp, keys, list) __ieee80211_key_destroy(key, false); - mutex_unlock(&local->key_mtx); } void ieee80211_free_keys(struct ieee80211_sub_if_data *sdata, @@ -1118,9 +1129,10 @@ struct ieee80211_key *key, *tmp; LIST_HEAD(keys); - cancel_delayed_work_sync(&sdata->dec_tailroom_needed_wk); + wiphy_delayed_work_cancel(local->hw.wiphy, + &sdata->dec_tailroom_needed_wk); - mutex_lock(&local->key_mtx); + lockdep_assert_wiphy(local->hw.wiphy); ieee80211_free_keys_iface(sdata, &keys); @@ -1153,8 +1165,6 @@ WARN_ON_ONCE(vlan->crypto_tx_tailroom_needed_cnt || vlan->crypto_tx_tailroom_pending_dec); } - - mutex_unlock(&local->key_mtx); } void ieee80211_free_sta_keys(struct ieee80211_local *local, @@ -1163,9 +1173,10 @@ struct ieee80211_key *key; int i; - mutex_lock(&local->key_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + for (i = 0; i < ARRAY_SIZE(sta->deflink.gtk); i++) { - key = key_mtx_dereference(local, sta->deflink.gtk[i]); + key = wiphy_dereference(local->hw.wiphy, sta->deflink.gtk[i]); if (!key) continue; ieee80211_key_replace(key->sdata, NULL, key->sta, @@ -1176,7 +1187,7 @@ } for (i = 0; i < NUM_DEFAULT_KEYS; i++) { - key = key_mtx_dereference(local, sta->ptk[i]); + key = wiphy_dereference(local->hw.wiphy, sta->ptk[i]); if (!key) continue; ieee80211_key_replace(key->sdata, NULL, key->sta, @@ -1185,11 +1196,10 @@ __ieee80211_key_destroy(key, key->sdata->vif.type == NL80211_IFTYPE_STATION); } - - mutex_unlock(&local->key_mtx); } -void ieee80211_delayed_tailroom_dec(struct work_struct *wk) +void ieee80211_delayed_tailroom_dec(struct wiphy *wiphy, + struct wiphy_work *wk) { struct ieee80211_sub_if_data *sdata; @@ -1212,11 +1222,9 @@ * within an ESS this usually won't happen. */ - mutex_lock(&sdata->local->key_mtx); decrease_tailroom_need_count(sdata, sdata->crypto_tx_tailroom_pending_dec); sdata->crypto_tx_tailroom_pending_dec = 0; - mutex_unlock(&sdata->local->key_mtx); } void ieee80211_gtk_rekey_notify(struct ieee80211_vif *vif, const u8 *bssid, @@ -1345,7 +1353,7 @@ key = container_of(keyconf, struct ieee80211_key, conf); - assert_key_lock(key->local); + lockdep_assert_wiphy(key->local->hw.wiphy); /* * if key was uploaded, we assume the driver will/has remove(d) diff -ruw linux-6.4/net/mac80211/key.h linux-6.4-fbx/net/mac80211/key.h --- linux-6.4/net/mac80211/key.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/key.h 2023-11-07 13:38:44.078257129 +0100 @@ -2,7 +2,7 @@ /* * Copyright 2002-2004, Instant802 Networks, Inc. * Copyright 2005, Devicescape Software, Inc. - * Copyright (C) 2019, 2022 Intel Corporation + * Copyright (C) 2019, 2022-2023 Intel Corporation */ #ifndef IEEE80211_KEY_H @@ -168,12 +168,7 @@ int ieee80211_key_switch_links(struct ieee80211_sub_if_data *sdata, unsigned long del_links_mask, unsigned long add_links_mask); - -#define key_mtx_dereference(local, ref) \ - rcu_dereference_protected(ref, lockdep_is_held(&((local)->key_mtx))) -#define rcu_dereference_check_key_mtx(local, ref) \ - rcu_dereference_check(ref, lockdep_is_held(&((local)->key_mtx))) - -void ieee80211_delayed_tailroom_dec(struct work_struct *wk); +void ieee80211_delayed_tailroom_dec(struct wiphy *wiphy, + struct wiphy_work *wk); #endif /* IEEE80211_KEY_H */ diff -ruw linux-6.4/net/mac80211/link.c linux-6.4-fbx/net/mac80211/link.c --- linux-6.4/net/mac80211/link.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/link.c 2023-11-07 13:38:44.078257129 +0100 @@ -37,15 +37,15 @@ link_conf->link_id = link_id; link_conf->vif = &sdata->vif; - INIT_WORK(&link->csa_finalize_work, + wiphy_work_init(&link->csa_finalize_work, ieee80211_csa_finalize_work); - INIT_WORK(&link->color_change_finalize_work, + wiphy_work_init(&link->color_change_finalize_work, ieee80211_color_change_finalize_work); INIT_DELAYED_WORK(&link->color_collision_detect_work, ieee80211_color_collision_detection_work); INIT_LIST_HEAD(&link->assigned_chanctx_list); INIT_LIST_HEAD(&link->reserved_chanctx_list); - INIT_DELAYED_WORK(&link->dfs_cac_timer_work, + wiphy_delayed_work_init(&link->dfs_cac_timer_work, ieee80211_dfs_cac_timer_work); if (!deflink) { @@ -142,25 +142,34 @@ } static void ieee80211_set_vif_links_bitmaps(struct ieee80211_sub_if_data *sdata, - u16 links) + u16 valid_links, u16 dormant_links) { - sdata->vif.valid_links = links; + sdata->vif.valid_links = valid_links; + sdata->vif.dormant_links = dormant_links; - if (!links) { + if (!valid_links || + WARN((~valid_links & dormant_links) || + !(valid_links & ~dormant_links), + "Invalid links: valid=0x%x, dormant=0x%x", + valid_links, dormant_links)) { sdata->vif.active_links = 0; + sdata->vif.dormant_links = 0; return; } switch (sdata->vif.type) { case NL80211_IFTYPE_AP: /* in an AP all links are always active */ - sdata->vif.active_links = links; + sdata->vif.active_links = valid_links; + + /* AP links are not expected to be disabled */ + WARN_ON(dormant_links); break; case NL80211_IFTYPE_STATION: if (sdata->vif.active_links) break; - WARN_ON(hweight16(links) > 1); - sdata->vif.active_links = links; + sdata->vif.active_links = valid_links & ~dormant_links; + WARN_ON(hweight16(sdata->vif.active_links) > 1); break; default: WARN_ON(1); @@ -169,7 +178,7 @@ static int ieee80211_vif_update_links(struct ieee80211_sub_if_data *sdata, struct link_container **to_free, - u16 new_links) + u16 new_links, u16 dormant_links) { u16 old_links = sdata->vif.valid_links; u16 old_active = sdata->vif.active_links; @@ -182,11 +191,11 @@ struct ieee80211_link_data *old_data[IEEE80211_MLD_MAX_NUM_LINKS]; bool use_deflink = old_links == 0; /* set for error case */ - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); memset(to_free, 0, sizeof(links)); - if (old_links == new_links) + if (old_links == new_links && dormant_links == sdata->vif.dormant_links) return 0; /* if there were no old links, need to clear the pointers to deflink */ @@ -226,6 +235,9 @@ RCU_INIT_POINTER(sdata->vif.link_conf[link_id], NULL); } + if (!old_links) + ieee80211_debugfs_recreate_netdev(sdata, true); + /* link them into data structures */ for_each_set_bit(link_id, &add, IEEE80211_MLD_MAX_NUM_LINKS) { WARN_ON(!use_deflink && @@ -245,20 +257,22 @@ /* for keys we will not be able to undo this */ ieee80211_tear_down_links(sdata, to_free, rem); - ieee80211_set_vif_links_bitmaps(sdata, new_links); + ieee80211_set_vif_links_bitmaps(sdata, new_links, dormant_links); /* tell the driver */ ret = drv_change_vif_links(sdata->local, sdata, old_links & old_active, new_links & sdata->vif.active_links, old); + if (!new_links) + ieee80211_debugfs_recreate_netdev(sdata, false); } if (ret) { /* restore config */ memcpy(sdata->link, old_data, sizeof(old_data)); memcpy(sdata->vif.link_conf, old, sizeof(old)); - ieee80211_set_vif_links_bitmaps(sdata, old_links); + ieee80211_set_vif_links_bitmaps(sdata, old_links, dormant_links); /* and free (only) the newly allocated links */ memset(to_free, 0, sizeof(links)); goto free; @@ -282,34 +296,18 @@ } int ieee80211_vif_set_links(struct ieee80211_sub_if_data *sdata, - u16 new_links) + u16 new_links, u16 dormant_links) { struct link_container *links[IEEE80211_MLD_MAX_NUM_LINKS]; int ret; - ret = ieee80211_vif_update_links(sdata, links, new_links); + ret = ieee80211_vif_update_links(sdata, links, new_links, + dormant_links); ieee80211_free_links(sdata, links); return ret; } -void ieee80211_vif_clear_links(struct ieee80211_sub_if_data *sdata) -{ - struct link_container *links[IEEE80211_MLD_MAX_NUM_LINKS]; - - /* - * The locking here is different because when we free links - * in the station case we need to be able to cancel_work_sync() - * something that also takes the lock. - */ - - sdata_lock(sdata); - ieee80211_vif_update_links(sdata, links, 0); - sdata_unlock(sdata); - - ieee80211_free_links(sdata, links); -} - static int _ieee80211_set_active_links(struct ieee80211_sub_if_data *sdata, u16 active_links) { @@ -328,8 +326,7 @@ if (sdata->vif.type != NL80211_IFTYPE_STATION) return -EINVAL; - /* cannot activate links that don't exist */ - if (active_links & ~sdata->vif.valid_links) + if (active_links & ~ieee80211_vif_usable_links(&sdata->vif)) return -EINVAL; /* nothing to do */ @@ -445,10 +442,8 @@ u16 old_active; int ret; - sdata_lock(sdata); - mutex_lock(&local->sta_mtx); - mutex_lock(&local->mtx); - mutex_lock(&local->key_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + old_active = sdata->vif.active_links; if (old_active & active_links) { /* @@ -464,10 +459,6 @@ /* otherwise switch directly */ ret = _ieee80211_set_active_links(sdata, active_links); } - mutex_unlock(&local->key_mtx); - mutex_unlock(&local->mtx); - mutex_unlock(&local->sta_mtx); - sdata_unlock(sdata); return ret; } @@ -484,8 +475,7 @@ if (sdata->vif.type != NL80211_IFTYPE_STATION) return; - /* cannot activate links that don't exist */ - if (active_links & ~sdata->vif.valid_links) + if (active_links & ~ieee80211_vif_usable_links(&sdata->vif)) return; /* nothing to do */ @@ -493,6 +483,6 @@ return; sdata->desired_active_links = active_links; - schedule_work(&sdata->activate_links_work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->activate_links_work); } EXPORT_SYMBOL_GPL(ieee80211_set_active_links_async); diff -ruw linux-6.4/net/mac80211/main.c linux-6.4-fbx/net/mac80211/main.c --- linux-6.4/net/mac80211/main.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/main.c 2024-04-19 16:04:28.969736104 +0200 @@ -5,7 +5,7 @@ * Copyright 2006-2007 Jiri Benc * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright (C) 2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation */ #include @@ -33,6 +33,8 @@ #include "wep.h" #include "led.h" #include "debugfs.h" +#include "nmeshd_nl.h" +#include "fbx_scum.h" void ieee80211_configure_filter(struct ieee80211_local *local) { @@ -84,7 +86,8 @@ local->filter_flags = new_flags & ~(1<<31); } -static void ieee80211_reconfig_filter(struct work_struct *work) +static void ieee80211_reconfig_filter(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, reconfig_filter); @@ -206,7 +209,8 @@ BSS_CHANGED_PS |\ BSS_CHANGED_IBSS |\ BSS_CHANGED_ARP_FILTER |\ - BSS_CHANGED_SSID) + BSS_CHANGED_SSID |\ + BSS_CHANGED_MLD_VALID_LINKS) void ieee80211_bss_info_change_notify(struct ieee80211_sub_if_data *sdata, u64 changed) @@ -291,7 +295,7 @@ drv_link_info_changed(local, sdata, link->conf, link->link_id, changed); } -u32 ieee80211_reset_erp_info(struct ieee80211_sub_if_data *sdata) +u64 ieee80211_reset_erp_info(struct ieee80211_sub_if_data *sdata) { sdata->vif.bss_conf.use_cts_prot = false; sdata->vif.bss_conf.use_short_preamble = false; @@ -335,14 +339,12 @@ struct ieee80211_sub_if_data *sdata; int ret; - /* wait for scan work complete */ flush_workqueue(local->workqueue); - flush_work(&local->sched_scan_stopped_work); - flush_work(&local->radar_detected_work); rtnl_lock(); /* we might do interface manipulations, so need both */ wiphy_lock(local->hw.wiphy); + wiphy_work_flush(local->hw.wiphy, NULL); WARN(test_bit(SCAN_HW_SCANNING, &local->scanning), "%s called with hardware scan in progress\n", __func__); @@ -364,22 +366,21 @@ * The exception is ieee80211_chswitch_done. * Then we can have a race... */ - cancel_work_sync(&sdata->u.mgd.csa_connection_drop_work); - if (sdata->vif.bss_conf.csa_active) { - sdata_lock(sdata); + wiphy_work_cancel(local->hw.wiphy, + &sdata->u.mgd.csa_connection_drop_work); + if (sdata->vif.bss_conf.csa_active) ieee80211_sta_connection_lost(sdata, WLAN_REASON_UNSPECIFIED, false); - sdata_unlock(sdata); } - } - flush_delayed_work(&sdata->dec_tailroom_needed_wk); + wiphy_delayed_work_flush(local->hw.wiphy, + &sdata->dec_tailroom_needed_wk); } ieee80211_scan_cancel(local); /* make sure any new ROC will consider local->in_reconfig */ - flush_delayed_work(&local->roc_work); - flush_work(&local->hw_roc_done); + wiphy_delayed_work_flush(local->hw.wiphy, &local->roc_work); + wiphy_work_flush(local->hw.wiphy, &local->hw_roc_done); /* wait for all packet processing to be done */ synchronize_net(); @@ -438,7 +439,7 @@ if (!wdev) return NOTIFY_DONE; - if (wdev->wiphy != local->hw.wiphy) + if (wdev->wiphy != local->hw.wiphy || !wdev->registered) return NOTIFY_DONE; sdata = IEEE80211_DEV_TO_SUB_IF(ndev); @@ -453,7 +454,25 @@ return NOTIFY_DONE; ifmgd = &sdata->u.mgd; - sdata_lock(sdata); + + /* + * The nested here is needed to convince lockdep that this is + * all OK. Yes, we lock the wiphy mutex here while we already + * hold the notifier rwsem, that's the normal case. And yes, + * we also acquire the notifier rwsem again when unregistering + * a netdev while we already hold the wiphy mutex, so it does + * look like a typical ABBA deadlock. + * + * However, both of these things happen with the RTNL held + * already. Therefore, they can't actually happen, since the + * lock orders really are ABC and ACB, which is fine due to + * the RTNL (A). + * + * We still need to prevent recursion, which is accomplished + * by the !wdev->registered check above. + */ + mutex_lock_nested(&local->hw.wiphy->mtx, 1); + __acquire(&local->hw.wiphy->mtx); /* Copy the addresses to the vif config list */ ifa = rtnl_dereference(idev->ifa_list); @@ -470,7 +489,7 @@ if (ifmgd->associated) ieee80211_vif_cfg_change_notify(sdata, BSS_CHANGED_ARP_FILTER); - sdata_unlock(sdata); + wiphy_unlock(local->hw.wiphy); return NOTIFY_OK; } @@ -783,9 +802,6 @@ __hw_addr_init(&local->mc_list); mutex_init(&local->iflist_mtx); - mutex_init(&local->mtx); - - mutex_init(&local->key_mtx); spin_lock_init(&local->filter_lock); spin_lock_init(&local->rx_path_lock); spin_lock_init(&local->queue_stop_reason_lock); @@ -806,25 +822,24 @@ spin_lock_init(&local->handle_wake_tx_queue_lock); INIT_LIST_HEAD(&local->chanctx_list); - mutex_init(&local->chanctx_mtx); - INIT_DELAYED_WORK(&local->scan_work, ieee80211_scan_work); + wiphy_delayed_work_init(&local->scan_work, ieee80211_scan_work); INIT_WORK(&local->restart_work, ieee80211_restart_work); - INIT_WORK(&local->radar_detected_work, + wiphy_work_init(&local->radar_detected_work, ieee80211_dfs_radar_detected_work); - INIT_WORK(&local->reconfig_filter, ieee80211_reconfig_filter); + wiphy_work_init(&local->reconfig_filter, ieee80211_reconfig_filter); local->smps_mode = IEEE80211_SMPS_OFF; - INIT_WORK(&local->dynamic_ps_enable_work, + wiphy_work_init(&local->dynamic_ps_enable_work, ieee80211_dynamic_ps_enable_work); - INIT_WORK(&local->dynamic_ps_disable_work, + wiphy_work_init(&local->dynamic_ps_disable_work, ieee80211_dynamic_ps_disable_work); timer_setup(&local->dynamic_ps_timer, ieee80211_dynamic_ps_timer, 0); - INIT_WORK(&local->sched_scan_stopped_work, + wiphy_work_init(&local->sched_scan_stopped_work, ieee80211_sched_scan_stopped_work); spin_lock_init(&local->ack_status_lock); @@ -847,6 +862,7 @@ local->hw.radiotap_timestamp.units_pos = -1; local->hw.radiotap_timestamp.accuracy = -1; + fbx80211_scum_local_init(local); return &local->hw; err_free: @@ -1445,6 +1461,7 @@ ieee80211_remove_interfaces(local); rtnl_unlock(); fail_rate: + ieee80211_txq_teardown_flows(local); fail_flows: ieee80211_led_exit(local); destroy_workqueue(local->workqueue); @@ -1481,13 +1498,17 @@ */ ieee80211_remove_interfaces(local); + ieee80211_txq_teardown_flows(local); + + wiphy_lock(local->hw.wiphy); + wiphy_delayed_work_cancel(local->hw.wiphy, &local->roc_work); + wiphy_work_cancel(local->hw.wiphy, &local->reconfig_filter); + wiphy_work_cancel(local->hw.wiphy, &local->sched_scan_stopped_work); + wiphy_work_cancel(local->hw.wiphy, &local->radar_detected_work); + wiphy_unlock(local->hw.wiphy); rtnl_unlock(); - cancel_delayed_work_sync(&local->roc_work); cancel_work_sync(&local->restart_work); - cancel_work_sync(&local->reconfig_filter); - flush_work(&local->sched_scan_stopped_work); - flush_work(&local->radar_detected_work); ieee80211_clear_tx_pending(local); rate_control_deinitialize(local); @@ -1517,8 +1538,9 @@ struct ieee80211_local *local = hw_to_local(hw); enum nl80211_band band; + fbx80211_scum_local_cleanup(local); + mutex_destroy(&local->iflist_mtx); - mutex_destroy(&local->mtx); if (local->wiphy_ciphers_allocated) { kfree(local->hw.wiphy->cipher_suites); @@ -1587,6 +1609,7 @@ drop_reasons_register_subsys(SKB_DROP_REASON_SUBSYS_MAC80211_UNUSABLE, &drop_reason_list_unusable); + nmeshd_nl_init(); return 0; err_netdev: rc80211_minstrel_exit(); @@ -1596,6 +1619,8 @@ static void __exit ieee80211_exit(void) { + nmeshd_nl_deinit(); + rc80211_minstrel_exit(); ieee80211s_stop(); diff -ruw linux-6.4/net/mac80211/mesh.c linux-6.4-fbx/net/mac80211/mesh.c --- linux-6.4/net/mac80211/mesh.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mesh.c 2024-04-19 16:04:28.973736213 +0200 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008, 2009 open80211s Ltd. - * Copyright (C) 2018 - 2022 Intel Corporation + * Copyright (C) 2018 - 2023 Intel Corporation * Authors: Luis Carlos Cobo * Javier Cardona */ @@ -45,7 +45,7 @@ set_bit(MESH_WORK_HOUSEKEEPING, &ifmsh->wrkq_flags); - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); } /** @@ -56,6 +56,8 @@ * * This function checks if the mesh configuration of a mesh point matches the * local mesh configuration, i.e. if both nodes belong to the same mesh network. + * + * Returns: %true if both nodes belong to the same mesh */ bool mesh_matches_local(struct ieee80211_sub_if_data *sdata, struct ieee802_11_elems *ie) @@ -119,6 +121,8 @@ * mesh_peer_accepts_plinks - check if an mp is willing to establish peer links * * @ie: information elements of a management frame from the mesh peer + * + * Returns: %true if the mesh peer is willing to establish peer links */ bool mesh_peer_accepts_plinks(struct ieee802_11_elems *ie) { @@ -133,10 +137,10 @@ * * Returns: beacon changed flag if the beacon content changed. */ -u32 mesh_accept_plinks_update(struct ieee80211_sub_if_data *sdata) +u64 mesh_accept_plinks_update(struct ieee80211_sub_if_data *sdata) { bool free_plinks; - u32 changed = 0; + u64 changed = 0; /* In case mesh_plink_free_count > 0 and mesh_plinktbl_capacity == 0, * the mesh interface might be able to establish plinks with peers that @@ -162,7 +166,7 @@ void mesh_sta_cleanup(struct sta_info *sta) { struct ieee80211_sub_if_data *sdata = sta->sdata; - u32 changed = mesh_plink_deactivate(sta); + u64 changed = mesh_plink_deactivate(sta); if (changed) ieee80211_mbss_info_change_notify(sdata, changed); @@ -349,19 +353,32 @@ u8 offset, len; const u8 *data; - if (!ifmsh->ie || !ifmsh->ie_len) - return 0; - /* fast-forward to vendor IEs */ - offset = ieee80211_ie_split_vendor(ifmsh->ie, ifmsh->ie_len, 0); + if (ifmsh->node_vendor_ie_len) { + offset = ieee80211_ie_split_vendor(ifmsh->node_vendor_ie, + ifmsh->node_vendor_ie_len, 0); + + if (offset < ifmsh->node_vendor_ie_len) { + len = ifmsh->node_vendor_ie_len - offset; + data = ifmsh->node_vendor_ie + offset; + if (skb_tailroom(skb) < len) + return -ENOMEM; + skb_put_data(skb, data, len); + } + } - if (offset < ifmsh->ie_len) { - len = ifmsh->ie_len - offset; - data = ifmsh->ie + offset; + if (ifmsh->mpm_vendor_ie_len) { + offset = ieee80211_ie_split_vendor(ifmsh->mpm_vendor_ie, + ifmsh->mpm_vendor_ie_len, 0); + + if (offset < ifmsh->mpm_vendor_ie_len) { + len = ifmsh->mpm_vendor_ie_len - offset; + data = ifmsh->mpm_vendor_ie + offset; if (skb_tailroom(skb) < len) return -ENOMEM; skb_put_data(skb, data, len); } + } return 0; } @@ -703,7 +720,7 @@ struct ieee80211_sub_if_data *sdata = from_timer(sdata, t, u.mesh.mesh_path_timer); - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } static void ieee80211_mesh_path_root_timer(struct timer_list *t) @@ -714,7 +731,7 @@ set_bit(MESH_WORK_ROOT, &ifmsh->wrkq_flags); - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } void ieee80211_mesh_root_setup(struct ieee80211_if_mesh *ifmsh) @@ -858,7 +875,7 @@ * @meshsa: source address in the mesh. Same as TA, as frame is * locally originated. * - * Return the length of the 802.11 (does not include a mesh control header) + * Returns: the length of the 802.11 frame header (excludes mesh control header) */ int ieee80211_fill_mesh_addresses(struct ieee80211_hdr *hdr, __le16 *fc, const u8 *meshda, const u8 *meshsa) @@ -891,7 +908,7 @@ * @addr6: 2nd address in the ae header, which corresponds to addr6 of the * mesh frame * - * Return the header length. + * Returns: the header length */ unsigned int ieee80211_new_mesh_header(struct ieee80211_sub_if_data *sdata, struct ieee80211s_hdr *meshhdr, @@ -923,7 +940,7 @@ static void ieee80211_mesh_housekeeping(struct ieee80211_sub_if_data *sdata) { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; - u32 changed; + u64 changed; if (ifmsh->mshcfg.plink_timeout > 0) ieee80211_sta_expire(sdata, ifmsh->mshcfg.plink_timeout * HZ); @@ -1006,7 +1023,9 @@ ie_len_eht_cap + 2 + 1 + offsetof(struct ieee80211_eht_operation, optional) + offsetof(struct ieee80211_eht_operation_info, optional) + - ifmsh->ie_len; + ifmsh->ie_len + + ifmsh->node_vendor_ie_len + + ifmsh->mpm_vendor_ie_len; bcn = kzalloc(sizeof(*bcn) + head_len + tail_len, GFP_KERNEL); /* need an skb for IE builders to operate on */ @@ -1164,7 +1183,7 @@ } void ieee80211_mbss_info_change_notify(struct ieee80211_sub_if_data *sdata, - u32 changed) + u64 changed) { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; unsigned long bits = changed; @@ -1175,16 +1194,16 @@ /* if we race with running work, worst case this work becomes a noop */ for_each_set_bit(bit, &bits, sizeof(changed) * BITS_PER_BYTE) - set_bit(bit, &ifmsh->mbss_changed); + set_bit(bit, ifmsh->mbss_changed); set_bit(MESH_WORK_MBSS_CHANGED, &ifmsh->wrkq_flags); - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } int ieee80211_start_mesh(struct ieee80211_sub_if_data *sdata) { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; struct ieee80211_local *local = sdata->local; - u32 changed = BSS_CHANGED_BEACON | + u64 changed = BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_HT | BSS_CHANGED_BASIC_RATES | @@ -1202,7 +1221,7 @@ ifmsh->sync_offset_clockdrift_max = 0; set_bit(MESH_WORK_HOUSEKEEPING, &ifmsh->wrkq_flags); ieee80211_mesh_root_setup(ifmsh); - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); sdata->vif.bss_conf.ht_operation_mode = ifmsh->mshcfg.ht_opmode; sdata->vif.bss_conf.enable_beacon = true; @@ -1257,7 +1276,7 @@ /* clear any mesh work (for next join) we may have accrued */ ifmsh->wrkq_flags = 0; - ifmsh->mbss_changed = 0; + memset(ifmsh->mbss_changed, 0, sizeof(ifmsh->mbss_changed)); local->fif_other_bss--; atomic_dec(&local->iff_allmultis); @@ -1291,7 +1310,7 @@ ieee80211_conn_flags_t conn_flags = 0; u32 vht_cap_info = 0; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); sband = ieee80211_get_sband(sdata); if (!sband) @@ -1472,12 +1491,18 @@ size_t baselen; int freq; enum nl80211_band band = rx_status->band; + struct ieee802_11_mesh_vendor_specific_elems nm, pm; + u32 beacon_int; + bool is_neigh_conn_estab; /* ignore ProbeResp to foreign address */ if (stype == IEEE80211_STYPE_PROBE_RESP && !ether_addr_equal(mgmt->da, sdata->vif.addr)) return; + if (stype == IEEE80211_STYPE_BEACON) + beacon_int = mgmt->u.beacon.beacon_int; + baselen = (u8 *) mgmt->u.probe_resp.variable - (u8 *) mgmt; if (baselen > len) return; @@ -1507,6 +1532,22 @@ if (mesh_matches_local(sdata, elems)) { mpl_dbg(sdata, "rssi_threshold=%d,rx_status->signal=%d\n", sdata->u.mesh.mshcfg.rssi_threshold, rx_status->signal); + + is_neigh_conn_estab = mesh_neighbour_connection_established(sdata, mgmt->sa); + ieee802_11_parse_mesh_vendor_elems(mgmt->u.probe_resp.variable, len - baselen, false, + &nm, 0, 0, NL80211_QBC_UPDATE_NODE_METRICS_IE); + if (nm.parse_error == false) + elems->total_len -= (nm.ie_len + 2); + + ieee802_11_parse_mesh_vendor_elems(mgmt->u.probe_resp.variable, len - baselen, false, + &pm, 0, 0, NL80211_QBC_UPDATE_PATH_METRICS_IE); + if (pm.parse_error == false) + elems->total_len -= (pm.ie_len + 2); + + if (is_neigh_conn_estab) + nmeshd_nl_send_vendor_ies(sdata->dev, mgmt->sa, stype, rx_status->signal, + beacon_int, &pm, &nm, GFP_KERNEL); + if (!sdata->u.mesh.user_mpm || sdata->u.mesh.mshcfg.rssi_threshold == 0 || sdata->u.mesh.mshcfg.rssi_threshold < rx_status->signal) @@ -1525,12 +1566,11 @@ kfree(elems); } -int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata) +int ieee80211_mesh_finish_csa(struct ieee80211_sub_if_data *sdata, u64 *changed) { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; struct mesh_csa_settings *tmp_csa_settings; int ret = 0; - int changed = 0; /* Reset the TTL value and Initiator flag */ ifmsh->csa_role = IEEE80211_MESH_CSA_ROLE_NONE; @@ -1545,21 +1585,22 @@ if (ret) return -EINVAL; - changed |= BSS_CHANGED_BEACON; + *changed |= BSS_CHANGED_BEACON; mcsa_dbg(sdata, "complete switching to center freq %d MHz", sdata->vif.bss_conf.chandef.chan->center_freq); - return changed; + return 0; } int ieee80211_mesh_csa_beacon(struct ieee80211_sub_if_data *sdata, - struct cfg80211_csa_settings *csa_settings) + struct cfg80211_csa_settings *csa_settings, + u64 *changed) { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; struct mesh_csa_settings *tmp_csa_settings; int ret = 0; - lockdep_assert_held(&sdata->wdev.mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); tmp_csa_settings = kmalloc(sizeof(*tmp_csa_settings), GFP_ATOMIC); @@ -1579,7 +1620,8 @@ return ret; } - return BSS_CHANGED_BEACON; + *changed |= BSS_CHANGED_BEACON; + return 0; } static int mesh_fwd_csa_frame(struct ieee80211_sub_if_data *sdata, @@ -1618,11 +1660,21 @@ bool fwd_csa = true; size_t baselen; u8 *pos; + struct sta_info *sta = NULL; if (mgmt->u.action.u.measurement.action_code != WLAN_ACTION_SPCT_CHL_SWITCH) return; + /* Process action frames received from connected mesh nodes */ + rcu_read_lock(); + sta = sta_info_get(sdata, mgmt->bssid); + if (!sta) { + rcu_read_unlock(); + return; + } + rcu_read_unlock(); + pos = mgmt->u.action.u.chan_switch.variable; baselen = offsetof(struct ieee80211_mgmt, u.action.u.chan_switch.variable); @@ -1690,11 +1742,11 @@ struct ieee80211_mgmt *mgmt; u16 stype; - sdata_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); /* mesh already went down */ if (!sdata->u.mesh.mesh_id_len) - goto out; + return; rx_status = IEEE80211_SKB_RXCB(skb); mgmt = (struct ieee80211_mgmt *) skb->data; @@ -1713,18 +1765,17 @@ ieee80211_mesh_rx_mgmt_action(sdata, mgmt, skb->len, rx_status); break; } -out: - sdata_unlock(sdata); } static void mesh_bss_info_changed(struct ieee80211_sub_if_data *sdata) { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; - u32 bit, changed = 0; + u32 bit; + u64 changed = 0; - for_each_set_bit(bit, &ifmsh->mbss_changed, + for_each_set_bit(bit, ifmsh->mbss_changed, sizeof(changed) * BITS_PER_BYTE) { - clear_bit(bit, &ifmsh->mbss_changed); + clear_bit(bit, ifmsh->mbss_changed); changed |= BIT(bit); } @@ -1743,11 +1794,11 @@ { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; - sdata_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); /* mesh already went down */ if (!sdata->u.mesh.mesh_id_len) - goto out; + return; if (ifmsh->preq_queue_len && time_after(jiffies, @@ -1765,8 +1816,6 @@ if (test_and_clear_bit(MESH_WORK_MBSS_CHANGED, &ifmsh->wrkq_flags)) mesh_bss_info_changed(sdata); -out: - sdata_unlock(sdata); } @@ -1797,13 +1846,29 @@ skb_queue_head_init(&ifmsh->ps.bc_buf); spin_lock_init(&ifmsh->mesh_preq_queue_lock); spin_lock_init(&ifmsh->sync_offset_lock); + INIT_LIST_HEAD(&ifmsh->mplink_blocking_list); + spin_lock_init(&ifmsh->mplink_blocking_list_lock); RCU_INIT_POINTER(ifmsh->beacon, NULL); sdata->vif.bss_conf.bssid = zero_addr; } +void ieee80211_mesh_free_blocked_mplink_entries(struct ieee80211_sub_if_data *sdata) +{ + struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; + struct mplink_block_list_info *mp_blink, *mp_blink_nxt; + + spin_lock_bh(&ifmsh->mplink_blocking_list_lock); + list_for_each_entry_safe(mp_blink, mp_blink_nxt, &ifmsh->mplink_blocking_list, list) { + list_del(&mp_blink->list); + kfree(mp_blink); + } + spin_unlock_bh(&ifmsh->mplink_blocking_list_lock); +} + void ieee80211_mesh_teardown_sdata(struct ieee80211_sub_if_data *sdata) { mesh_rmc_free(sdata); mesh_pathtbl_unregister(sdata); + ieee80211_mesh_free_blocked_mplink_entries(sdata); } diff -ruw linux-6.4/net/mac80211/mesh.h linux-6.4-fbx/net/mac80211/mesh.h --- linux-6.4/net/mac80211/mesh.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mesh.h 2024-04-19 16:04:28.973736213 +0200 @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008, 2009 open80211s Ltd. + * Copyright (C) 2023 Intel Corporation * Authors: Luis Carlos Cobo * Javier Cardona */ @@ -157,6 +158,11 @@ unsigned long timestamp; }; +struct mplink_block_list_info { + struct list_head list; + u8 dst[ETH_ALEN]; +}; + /* Recent multicast cache */ /* RMC_BUCKETS must be a power of 2, maximum 256 */ #define RMC_BUCKETS 256 @@ -211,7 +217,6 @@ const u8 *addr, struct ieee80211s_hdr *mesh_hdr); bool mesh_matches_local(struct ieee80211_sub_if_data *sdata, struct ieee802_11_elems *ie); -void mesh_ids_set_default(struct ieee80211_if_mesh *mesh); int mesh_add_meshconf_ie(struct ieee80211_sub_if_data *sdata, struct sk_buff *skb); int mesh_add_meshid_ie(struct ieee80211_sub_if_data *sdata, @@ -252,11 +257,12 @@ const struct ieee80211_mesh_sync_ops *ieee80211_mesh_sync_ops_get(u8 method); /* wrapper for ieee80211_bss_info_change_notify() */ void ieee80211_mbss_info_change_notify(struct ieee80211_sub_if_data *sdata, - u32 changed); + u64 changed); +void ieee80211_mesh_free_blocked_mplink_entries(struct ieee80211_sub_if_data *sdata); /* mesh power save */ -u32 ieee80211_mps_local_status_update(struct ieee80211_sub_if_data *sdata); -u32 ieee80211_mps_set_sta_local_pm(struct sta_info *sta, +u64 ieee80211_mps_local_status_update(struct ieee80211_sub_if_data *sdata); +u64 ieee80211_mps_set_sta_local_pm(struct sta_info *sta, enum nl80211_mesh_power_mode pm); void ieee80211_mps_set_frame_flags(struct ieee80211_sub_if_data *sdata, struct sta_info *sta, @@ -303,17 +309,18 @@ u8 *hw_addr, struct ieee802_11_elems *ie, struct ieee80211_rx_status *rx_status); bool mesh_peer_accepts_plinks(struct ieee802_11_elems *ie); -u32 mesh_accept_plinks_update(struct ieee80211_sub_if_data *sdata); +u64 mesh_accept_plinks_update(struct ieee80211_sub_if_data *sdata); void mesh_plink_timer(struct timer_list *t); void mesh_plink_broken(struct sta_info *sta); -u32 mesh_plink_deactivate(struct sta_info *sta); -u32 mesh_plink_open(struct sta_info *sta); -u32 mesh_plink_block(struct sta_info *sta); +u64 mesh_plink_deactivate(struct sta_info *sta); +u64 mesh_plink_open(struct sta_info *sta); +u64 mesh_plink_block(struct sta_info *sta); void mesh_rx_plink_frame(struct ieee80211_sub_if_data *sdata, struct ieee80211_mgmt *mgmt, size_t len, struct ieee80211_rx_status *rx_status); void mesh_sta_cleanup(struct sta_info *sta); - +bool mesh_neighbour_connection_established(struct ieee80211_sub_if_data *sdata, + u8 *hw_addr); /* Private interfaces */ /* Mesh paths */ int mesh_path_error_tx(struct ieee80211_sub_if_data *sdata, @@ -349,14 +356,14 @@ #ifdef CONFIG_MAC80211_MESH static inline -u32 mesh_plink_inc_estab_count(struct ieee80211_sub_if_data *sdata) +u64 mesh_plink_inc_estab_count(struct ieee80211_sub_if_data *sdata) { atomic_inc(&sdata->u.mesh.estab_plinks); return mesh_accept_plinks_update(sdata) | BSS_CHANGED_BEACON; } static inline -u32 mesh_plink_dec_estab_count(struct ieee80211_sub_if_data *sdata) +u64 mesh_plink_dec_estab_count(struct ieee80211_sub_if_data *sdata) { atomic_dec(&sdata->u.mesh.estab_plinks); return mesh_accept_plinks_update(sdata) | BSS_CHANGED_BEACON; @@ -387,12 +394,20 @@ void mesh_path_flush_by_iface(struct ieee80211_sub_if_data *sdata); void mesh_sync_adjust_tsf(struct ieee80211_sub_if_data *sdata); void ieee80211s_stop(void); +void nmeshd_nl_send_vendor_ies(struct net_device *dev, const u8 *macaddr, u16 stype, s8 signal, + u32 beacon_int, struct ieee802_11_mesh_vendor_specific_elems *pm, + struct ieee802_11_mesh_vendor_specific_elems *nm, gfp_t gfp); + #else static inline bool mesh_path_sel_is_hwmp(struct ieee80211_sub_if_data *sdata) { return false; } static inline void mesh_path_flush_by_iface(struct ieee80211_sub_if_data *sdata) {} static inline void ieee80211s_stop(void) {} +static inline void nmeshd_nl_send_vendor_ies(struct net_device *dev, const u8 *macaddr, u16 stype, s8 signal, + u32 beacon_int, struct ieee802_11_mesh_vendor_specific_elems *pm, + struct ieee802_11_mesh_vendor_specific_elems *nm, gfp_t gfp) +{} #endif #endif /* IEEE80211S_H */ diff -ruw linux-6.4/net/mac80211/mesh_hwmp.c linux-6.4-fbx/net/mac80211/mesh_hwmp.c --- linux-6.4/net/mac80211/mesh_hwmp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mesh_hwmp.c 2023-11-07 13:38:44.078257129 +0100 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008, 2009 open80211s Ltd. - * Copyright (C) 2019, 2021-2022 Intel Corporation + * Copyright (C) 2019, 2021-2023 Intel Corporation * Author: Luis Carlos Cobo */ @@ -230,6 +230,8 @@ * Note: This function may be called with driver locks taken that the driver * also acquires in the TX path. To avoid a deadlock we don't transmit the * frame directly but add it to the pending queue instead. + * + * Returns: 0 on success */ int mesh_path_error_tx(struct ieee80211_sub_if_data *sdata, u8 ttl, const u8 *target, u32 target_sn, @@ -1026,14 +1028,14 @@ spin_unlock_bh(&ifmsh->mesh_preq_queue_lock); if (time_after(jiffies, ifmsh->last_preq + min_preq_int_jiff(sdata))) - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); else if (time_before(jiffies, ifmsh->last_preq)) { /* avoid long wait if did not send preqs for a long time * and jiffies wrapped around */ ifmsh->last_preq = jiffies - min_preq_int_jiff(sdata) - 1; - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } else mod_timer(&ifmsh->mesh_path_timer, ifmsh->last_preq + min_preq_int_jiff(sdata)); diff -ruw linux-6.4/net/mac80211/mesh_pathtbl.c linux-6.4-fbx/net/mac80211/mesh_pathtbl.c --- linux-6.4/net/mac80211/mesh_pathtbl.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mesh_pathtbl.c 2023-11-07 13:38:44.082257238 +0100 @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008, 2009 open80211s Ltd. + * Copyright (C) 2023 Intel Corporation * Author: Luis Carlos Cobo */ @@ -173,6 +174,11 @@ /** * mesh_path_move_to_queue - Move or copy frames from one mpath queue to another * + * @gate_mpath: An active mpath the frames will be sent to (i.e. the gate) + * @from_mpath: The failed mpath + * @copy: When true, copy all the frames to the new mpath queue. When false, + * move them. + * * This function is used to transfer or copy frames from an unresolved mpath to * a gate mpath. The function also adds the Address Extension field and * updates the next hop. @@ -181,11 +187,6 @@ * destination addresses are updated. * * The gate mpath must be an active mpath with a valid mpath->next_hop. - * - * @gate_mpath: An active mpath the frames will be sent to (i.e. the gate) - * @from_mpath: The failed mpath - * @copy: When true, copy all the frames to the new mpath queue. When false, - * move them. */ static void mesh_path_move_to_queue(struct mesh_path *gate_mpath, struct mesh_path *from_mpath, @@ -330,6 +331,8 @@ /** * mesh_path_add_gate - add the given mpath to a mesh gate to our path table * @mpath: gate path to add to table + * + * Returns: 0 on success, -EEXIST */ int mesh_path_add_gate(struct mesh_path *mpath) { @@ -388,6 +391,8 @@ /** * mesh_gate_num - number of gates known to this interface * @sdata: subif data + * + * Returns: The number of gates */ int mesh_gate_num(struct ieee80211_sub_if_data *sdata) { @@ -648,7 +653,7 @@ cache = &sdata->u.mesh.tx_cache; spin_lock_bh(&cache->walk_lock); - entry = rhashtable_lookup(&cache->rht, addr, fast_tx_rht_params); + entry = rhashtable_lookup_fast(&cache->rht, addr, fast_tx_rht_params); if (entry) mesh_fast_tx_entry_free(cache, entry); spin_unlock_bh(&cache->walk_lock); @@ -861,10 +866,9 @@ /** * mesh_path_flush_by_iface - Deletes all mesh paths associated with a given iface * - * This function deletes both mesh paths as well as mesh portal paths. - * * @sdata: interface data to match * + * This function deletes both mesh paths as well as mesh portal paths. */ void mesh_path_flush_by_iface(struct ieee80211_sub_if_data *sdata) { @@ -944,6 +948,8 @@ * queue to that gate's queue. If there are more than one gates, the frames * are copied from each gate to the next. After frames are copied, the * mpath queues are emptied onto the transmission queue. + * + * Returns: 0 on success, -EHOSTUNREACH */ int mesh_path_send_to_gates(struct mesh_path *mpath) { diff -ruw linux-6.4/net/mac80211/mesh_plink.c linux-6.4-fbx/net/mac80211/mesh_plink.c --- linux-6.4/net/mac80211/mesh_plink.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mesh_plink.c 2024-04-19 16:04:28.973736213 +0200 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008, 2009 open80211s Ltd. - * Copyright (C) 2019, 2021-2022 Intel Corporation + * Copyright (C) 2019, 2021-2023 Intel Corporation * Author: Luis Carlos Cobo */ #include @@ -90,12 +90,13 @@ * * Returns BSS_CHANGED_ERP_SLOT or 0 for no change. */ -static u32 mesh_set_short_slot_time(struct ieee80211_sub_if_data *sdata) +static u64 mesh_set_short_slot_time(struct ieee80211_sub_if_data *sdata) { struct ieee80211_local *local = sdata->local; struct ieee80211_supported_band *sband; struct sta_info *sta; - u32 erp_rates = 0, changed = 0; + u32 erp_rates = 0; + u64 changed = 0; int i; bool short_slot = false; @@ -152,8 +153,10 @@ * selected if any non-HT peers are present in our MBSS. 20MHz-protection mode * is selected if all peers in our 20/40MHz MBSS support HT and at least one * HT20 peer is present. Otherwise no-protection mode is selected. + * + * Returns: BSS_CHANGED_HT or 0 for no change */ -static u32 mesh_set_ht_prot_mode(struct ieee80211_sub_if_data *sdata) +static u64 mesh_set_ht_prot_mode(struct ieee80211_sub_if_data *sdata) { struct ieee80211_local *local = sdata->local; struct sta_info *sta; @@ -361,14 +364,14 @@ * Mesh paths with this peer as next hop should be flushed * by the caller outside of plink_lock. * - * Returns beacon changed flag if the beacon content changed. + * Returns: beacon changed flag if the beacon content changed. * * Locking: the caller must hold sta->mesh->plink_lock */ -static u32 __mesh_plink_deactivate(struct sta_info *sta) +static u64 __mesh_plink_deactivate(struct sta_info *sta) { struct ieee80211_sub_if_data *sdata = sta->sdata; - u32 changed = 0; + u64 changed = 0; lockdep_assert_held(&sta->mesh->plink_lock); @@ -389,11 +392,13 @@ * @sta: mesh peer link to deactivate * * All mesh paths with this peer as next hop will be flushed + * + * Returns: beacon changed flag if the beacon content changed. */ -u32 mesh_plink_deactivate(struct sta_info *sta) +u64 mesh_plink_deactivate(struct sta_info *sta) { struct ieee80211_sub_if_data *sdata = sta->sdata; - u32 changed; + u64 changed; spin_lock_bh(&sta->mesh->plink_lock); changed = __mesh_plink_deactivate(sta); @@ -450,7 +455,7 @@ changed |= IEEE80211_RC_BW_CHANGED; ieee80211_vht_cap_ie_to_sta_vht_cap(sdata, sband, - elems->vht_cap_elem, + elems->vht_cap_elem, NULL, &sta->deflink); ieee80211_he_cap_ie_to_sta_he_cap(sdata, sband, elems->he_cap, @@ -622,7 +627,7 @@ struct ieee80211_rx_status *rx_status) { struct sta_info *sta; - u32 changed = 0; + u64 changed = 0; sta = mesh_sta_info_get(sdata, hw_addr, elems, rx_status); if (!sta) @@ -775,10 +780,10 @@ return llid; } -u32 mesh_plink_open(struct sta_info *sta) +u64 mesh_plink_open(struct sta_info *sta) { struct ieee80211_sub_if_data *sdata = sta->sdata; - u32 changed; + u64 changed; if (!test_sta_flag(sta, WLAN_STA_AUTH)) return 0; @@ -805,9 +810,9 @@ return changed; } -u32 mesh_plink_block(struct sta_info *sta) +u64 mesh_plink_block(struct sta_info *sta) { - u32 changed; + u64 changed; spin_lock_bh(&sta->mesh->plink_lock); changed = __mesh_plink_deactivate(sta); @@ -831,11 +836,11 @@ mod_plink_timer(sta, mshcfg->dot11MeshHoldingTimeout); } -static u32 mesh_plink_establish(struct ieee80211_sub_if_data *sdata, +static u64 mesh_plink_establish(struct ieee80211_sub_if_data *sdata, struct sta_info *sta) { struct mesh_config *mshcfg = &sdata->u.mesh.mshcfg; - u32 changed = 0; + u64 changed = 0; del_timer(&sta->mesh->plink_timer); sta->mesh->plink_state = NL80211_PLINK_ESTAB; @@ -857,12 +862,12 @@ * * Return: changed MBSS flags */ -static u32 mesh_plink_fsm(struct ieee80211_sub_if_data *sdata, +static u64 mesh_plink_fsm(struct ieee80211_sub_if_data *sdata, struct sta_info *sta, enum plink_event event) { struct mesh_config *mshcfg = &sdata->u.mesh.mshcfg; enum ieee80211_self_protected_actioncode action = 0; - u32 changed = 0; + u64 changed = 0; bool flush = false; mpl_dbg(sdata, "peer %pM in state %s got event %s\n", sta->sta.addr, @@ -1117,7 +1122,7 @@ struct sta_info *sta; enum plink_event event; enum ieee80211_self_protected_actioncode ftype; - u32 changed = 0; + u64 changed = 0; u8 ie_len = elems->peering_len; u16 plid, llid = 0; @@ -1245,3 +1250,31 @@ mesh_process_plink_frame(sdata, mgmt, elems, rx_status); kfree(elems); } + +/* + * mesh_neighbour_connection_established - return if connection has been established with neighbor. + * + * @sdata: local meshif + * @addr: peer's address + * @elems: IEs from beacon or mesh peering frame + * + * + */ +bool mesh_neighbour_connection_established(struct ieee80211_sub_if_data *sdata, + u8 *hw_addr) +{ + struct sta_info *sta; + bool ret = false; + + rcu_read_lock(); + sta = sta_info_get(sdata, hw_addr); + if (!sta) + goto out; + + if (sta->mesh->plink_state == NL80211_PLINK_ESTAB) + ret = true; + +out: + rcu_read_unlock(); + return ret; +} diff -ruw linux-6.4/net/mac80211/mesh_ps.c linux-6.4-fbx/net/mac80211/mesh_ps.c --- linux-6.4/net/mac80211/mesh_ps.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mesh_ps.c 2023-11-07 13:38:44.082257238 +0100 @@ -3,6 +3,7 @@ * Copyright 2012-2013, Marco Porsch * Copyright 2012-2013, cozybit Inc. * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2023 Intel Corporation */ #include "mesh.h" @@ -14,6 +15,8 @@ /** * mps_qos_null_get - create pre-addressed QoS Null frame for mesh powersave * @sta: the station to get the frame for + * + * Returns: A newly allocated SKB */ static struct sk_buff *mps_qos_null_get(struct sta_info *sta) { @@ -76,15 +79,17 @@ * * sets the non-peer power mode and triggers the driver PS (re-)configuration * Return BSS_CHANGED_BEACON if a beacon update is necessary. + * + * Returns: BSS_CHANGED_BEACON if a beacon update is in order. */ -u32 ieee80211_mps_local_status_update(struct ieee80211_sub_if_data *sdata) +u64 ieee80211_mps_local_status_update(struct ieee80211_sub_if_data *sdata) { struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; struct sta_info *sta; bool peering = false; int light_sleep_cnt = 0; int deep_sleep_cnt = 0; - u32 changed = 0; + u64 changed = 0; enum nl80211_mesh_power_mode nonpeer_pm; rcu_read_lock(); @@ -146,9 +151,9 @@ * * @sta: mesh STA * @pm: the power mode to set - * Return BSS_CHANGED_BEACON if a beacon update is in order. + * Returns: BSS_CHANGED_BEACON if a beacon update is in order. */ -u32 ieee80211_mps_set_sta_local_pm(struct sta_info *sta, +u64 ieee80211_mps_set_sta_local_pm(struct sta_info *sta, enum nl80211_mesh_power_mode pm) { struct ieee80211_sub_if_data *sdata = sta->sdata; diff -ruw linux-6.4/net/mac80211/mesh_sync.c linux-6.4-fbx/net/mac80211/mesh_sync.c --- linux-6.4/net/mac80211/mesh_sync.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mesh_sync.c 2023-11-07 13:38:44.082257238 +0100 @@ -3,7 +3,7 @@ * Copyright 2011-2012, Pavel Zubarev * Copyright 2011-2012, Marco Porsch * Copyright 2011-2012, cozybit Inc. - * Copyright (C) 2021 Intel Corporation + * Copyright (C) 2021,2023 Intel Corporation */ #include "ieee80211_i.h" @@ -37,6 +37,8 @@ * mesh_peer_tbtt_adjusting - check if an mp is currently adjusting its TBTT * * @cfg: mesh config element from the mesh peer (or %NULL) + * + * Returns: If the mesh peer is currently adjusting its TBTT */ static bool mesh_peer_tbtt_adjusting(const struct ieee80211_meshconf_ie *cfg) { diff -ruw linux-6.4/net/mac80211/mlme.c linux-6.4-fbx/net/mac80211/mlme.c --- linux-6.4/net/mac80211/mlme.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/mlme.c 2023-11-07 13:38:44.082257238 +0100 @@ -110,7 +110,8 @@ return 0; /* set 160/320 supported to get the full AP definition */ - ieee80211_chandef_eht_oper(eht_oper, true, true, &ap_chandef); + ieee80211_chandef_eht_oper((const void *)eht_oper->optional, + true, true, &ap_chandef); ap_center_freq = ap_chandef.center_freq1; ap_bw = 20 * BIT(u8_get_bits(info->control, IEEE80211_EHT_OPER_CHAN_WIDTH)); @@ -175,7 +176,7 @@ static void run_again(struct ieee80211_sub_if_data *sdata, unsigned long timeout) { - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (!timer_pending(&sdata->u.mgd.timer) || time_before(timeout, sdata->u.mgd.timer.expires)) @@ -388,7 +389,7 @@ if (eht_oper && (eht_oper->params & IEEE80211_EHT_OPER_INFO_PRESENT)) { struct cfg80211_chan_def eht_chandef = *chandef; - ieee80211_chandef_eht_oper(eht_oper, + ieee80211_chandef_eht_oper((const void *)eht_oper->optional, eht_chandef.width == NL80211_CHAN_WIDTH_160, false, &eht_chandef); @@ -511,16 +512,14 @@ /* don't check HE if we associated as non-HE station */ if (link->u.mgd.conn_flags & IEEE80211_CONN_DISABLE_HE || - !ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif))) { + !ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif)) { he_oper = NULL; eht_oper = NULL; } /* don't check EHT if we associated as non-EHT station */ if (link->u.mgd.conn_flags & IEEE80211_CONN_DISABLE_EHT || - !ieee80211_get_eht_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif))) + !ieee80211_get_eht_iftype_cap_vif(sband, &sdata->vif)) eht_oper = NULL; /* @@ -776,8 +775,7 @@ const struct ieee80211_sta_he_cap *he_cap; u8 he_cap_size; - he_cap = ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + he_cap = ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); if (WARN_ON(!he_cap)) return; @@ -806,10 +804,8 @@ const struct ieee80211_sta_eht_cap *eht_cap; u8 eht_cap_size; - he_cap = ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); - eht_cap = ieee80211_get_eht_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + he_cap = ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); + eht_cap = ieee80211_get_eht_iftype_cap_vif(sband, &sdata->vif); /* * EHT capabilities element is only added if the HE capabilities element @@ -835,7 +831,6 @@ struct ieee80211_supported_band *sband, struct ieee80211_mgd_assoc_data *assoc_data) { - unsigned int shift = ieee80211_chanwidth_get_shift(width); unsigned int rates_len, supp_rates_len; u32 rates = 0; int i, count; @@ -874,8 +869,7 @@ count = 0; for (i = 0; i < sband->n_bitrates; i++) { if (BIT(i) & rates) { - int rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, - 5 * (1 << shift)); + int rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, 5); *pos++ = (u8)rate; if (++count == 8) break; @@ -891,8 +885,7 @@ if (BIT(i) & rates) { int rate; - rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, - 5 * (1 << shift)); + rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, 5); *pos++ = (u8)rate; } } @@ -1287,7 +1280,7 @@ u8 *ml_elem_len; void *capab_pos; - if (!sdata->vif.valid_links) + if (!ieee80211_vif_is_mld(&sdata->vif)) return; ift_ext_capa = cfg80211_get_iftype_ext_capa(local->hw.wiphy, @@ -1406,7 +1399,7 @@ assoc_data->ie, assoc_data->ie_len); - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); size = local->hw.extra_tx_headroom + sizeof(*mgmt) + /* bit too much but doesn't matter */ @@ -1462,7 +1455,7 @@ capab |= WLAN_CAPABILITY_PRIVACY; } - if (sdata->vif.valid_links) { + if (ieee80211_vif_is_mld(&sdata->vif)) { /* consider the multi-link element with STA profile */ size += sizeof(struct ieee80211_multi_link_elem); /* max common info field in basic multi-link element */ @@ -1591,6 +1584,7 @@ ifmgd->assoc_req_ies_len = pos - ie_start; + info.link_id = assoc_data->assoc_link_id; drv_mgd_prepare_tx(local, sdata, &info); IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_INTFL_DONT_ENCRYPT; @@ -1680,10 +1674,12 @@ } /* spectrum management related things */ -static void ieee80211_chswitch_work(struct work_struct *work) +static void ieee80211_chswitch_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_link_data *link = - container_of(work, struct ieee80211_link_data, u.mgd.chswitch_work); + container_of(work, struct ieee80211_link_data, + u.mgd.chswitch_work.work); struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_local *local = sdata->local; struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; @@ -1692,15 +1688,13 @@ if (!ieee80211_sdata_running(sdata)) return; - sdata_lock(sdata); - mutex_lock(&local->mtx); - mutex_lock(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (!ifmgd->associated) - goto out; + return; if (!link->conf->csa_active) - goto out; + return; /* * using reservation isn't immediate as it may be deferred until later @@ -1716,39 +1710,32 @@ * reservations */ if (link->reserved_ready) - goto out; + return; ret = ieee80211_link_use_reserved_context(link); if (ret) { sdata_info(sdata, "failed to use reserved channel context, disconnecting (err=%d)\n", ret); - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &ifmgd->csa_connection_drop_work); - goto out; } - - goto out; + return; } if (!cfg80211_chandef_identical(&link->conf->chandef, &link->csa_chandef)) { sdata_info(sdata, "failed to finalize channel switch, disconnecting\n"); - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &ifmgd->csa_connection_drop_work); - goto out; + return; } link->u.mgd.csa_waiting_bcn = true; ieee80211_sta_reset_beacon_monitor(sdata); ieee80211_sta_reset_conn_monitor(sdata); - -out: - mutex_unlock(&local->chanctx_mtx); - mutex_unlock(&local->mtx); - sdata_unlock(sdata); } static void ieee80211_chswitch_post_beacon(struct ieee80211_link_data *link) @@ -1758,7 +1745,7 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; int ret; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); WARN_ON(!link->conf->csa_active); @@ -1776,47 +1763,49 @@ */ link->u.mgd.beacon_crc_valid = false; - ret = drv_post_channel_switch(sdata); + ret = drv_post_channel_switch(link); if (ret) { sdata_info(sdata, "driver post channel switch failed, disconnecting\n"); - ieee80211_queue_work(&local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &ifmgd->csa_connection_drop_work); return; } - cfg80211_ch_switch_notify(sdata->dev, &link->reserved_chandef, 0, 0); + cfg80211_ch_switch_notify(sdata->dev, &link->reserved_chandef, + link->link_id, 0); } -void ieee80211_chswitch_done(struct ieee80211_vif *vif, bool success) +void ieee80211_chswitch_done(struct ieee80211_vif *vif, bool success, + unsigned int link_id) { struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); - struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - if (WARN_ON(sdata->vif.valid_links)) - success = false; + trace_api_chswitch_done(sdata, success, link_id); + + rcu_read_lock(); - trace_api_chswitch_done(sdata, success); if (!success) { sdata_info(sdata, "driver channel switch failed, disconnecting\n"); - ieee80211_queue_work(&sdata->local->hw, - &ifmgd->csa_connection_drop_work); + wiphy_work_queue(sdata->local->hw.wiphy, + &sdata->u.mgd.csa_connection_drop_work); } else { - ieee80211_queue_work(&sdata->local->hw, - &sdata->deflink.u.mgd.chswitch_work); - } + struct ieee80211_link_data *link = + rcu_dereference(sdata->link[link_id]); + + if (WARN_ON(!link)) { + rcu_read_unlock(); + return; } -EXPORT_SYMBOL(ieee80211_chswitch_done); -static void ieee80211_chswitch_timer(struct timer_list *t) -{ - struct ieee80211_link_data *link = - from_timer(link, t, u.mgd.chswitch_timer); + wiphy_delayed_work_queue(sdata->local->hw.wiphy, + &link->u.mgd.chswitch_work, 0); + } - ieee80211_queue_work(&link->sdata->local->hw, - &link->u.mgd.chswitch_work); + rcu_read_unlock(); } +EXPORT_SYMBOL(ieee80211_chswitch_done); static void ieee80211_sta_abort_chanswitch(struct ieee80211_link_data *link) @@ -1824,14 +1813,12 @@ struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_local *local = sdata->local; + lockdep_assert_wiphy(local->hw.wiphy); + if (!local->ops->abort_channel_switch) return; - mutex_lock(&local->mtx); - - mutex_lock(&local->chanctx_mtx); ieee80211_link_unreserve_chanctx(link); - mutex_unlock(&local->chanctx_mtx); if (link->csa_block_tx) ieee80211_wake_vif_queues(local, sdata, @@ -1840,8 +1827,6 @@ link->csa_block_tx = false; link->conf->csa_active = false; - mutex_unlock(&local->mtx); - drv_abort_channel_switch(sdata); } @@ -1861,16 +1846,14 @@ struct ieee80211_csa_ie csa_ie; struct ieee80211_channel_switch ch_switch; struct ieee80211_bss *bss; + unsigned long timeout; int res; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(local->hw.wiphy); if (!cbss) return; - if (local->scanning) - return; - current_band = cbss->channel->band; bss = (void *)cbss->priv; res = ieee80211_parse_ch_switch_ie(sdata, elems, current_band, @@ -1888,7 +1871,7 @@ } if (res < 0) - goto lock_and_drop_connection; + goto drop_connection; if (beacon && link->conf->csa_active && !link->u.mgd.csa_waiting_bcn) { @@ -1910,7 +1893,7 @@ csa_ie.chandef.chan->center_freq, csa_ie.chandef.width, csa_ie.chandef.center_freq1, csa_ie.chandef.center_freq2); - goto lock_and_drop_connection; + goto drop_connection; } if (!cfg80211_chandef_usable(local->hw.wiphy, &csa_ie.chandef, @@ -1925,7 +1908,7 @@ csa_ie.chandef.width, csa_ie.chandef.center_freq1, csa_ie.chandef.freq1_offset, csa_ie.chandef.center_freq2); - goto lock_and_drop_connection; + goto drop_connection; } if (cfg80211_chandef_identical(&csa_ie.chandef, @@ -1948,10 +1931,8 @@ */ ieee80211_teardown_tdls_peers(sdata); - mutex_lock(&local->mtx); - mutex_lock(&local->chanctx_mtx); conf = rcu_dereference_protected(link->conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (!conf) { sdata_info(sdata, "no channel context assigned to vif?, disconnecting\n"); @@ -1981,7 +1962,6 @@ res); goto drop_connection; } - mutex_unlock(&local->chanctx_mtx); link->conf->csa_active = true; link->csa_chandef = csa_ie.chandef; @@ -1992,10 +1972,10 @@ if (link->csa_block_tx) ieee80211_stop_vif_queues(local, sdata, IEEE80211_QUEUE_STOP_REASON_CSA); - mutex_unlock(&local->mtx); - cfg80211_ch_switch_started_notify(sdata->dev, &csa_ie.chandef, 0, - csa_ie.count, csa_ie.mode, 0); + cfg80211_ch_switch_started_notify(sdata->dev, &csa_ie.chandef, + link->link_id, csa_ie.count, + csa_ie.mode, 0); if (local->ops->channel_switch) { /* use driver's channel switch callback */ @@ -2004,16 +1984,12 @@ } /* channel switch handled in software */ - if (csa_ie.count <= 1) - ieee80211_queue_work(&local->hw, &link->u.mgd.chswitch_work); - else - mod_timer(&link->u.mgd.chswitch_timer, - TU_TO_EXP_TIME((csa_ie.count - 1) * - cbss->beacon_interval)); - return; - lock_and_drop_connection: - mutex_lock(&local->mtx); - mutex_lock(&local->chanctx_mtx); + timeout = TU_TO_JIFFIES((max_t(int, csa_ie.count, 1) - 1) * + cbss->beacon_interval); + wiphy_delayed_work_queue(local->hw.wiphy, + &link->u.mgd.chswitch_work, + timeout); + return; drop_connection: /* * This is just so that the disconnect flow will know that @@ -2025,9 +2001,8 @@ link->conf->csa_active = true; link->csa_block_tx = csa_ie.mode; - ieee80211_queue_work(&local->hw, &ifmgd->csa_connection_drop_work); - mutex_unlock(&local->chanctx_mtx); - mutex_unlock(&local->mtx); + wiphy_work_queue(sdata->local->hw.wiphy, + &ifmgd->csa_connection_drop_work); } static bool @@ -2116,7 +2091,7 @@ *pwr_level = (__s8)cisco_dtpc_ie[4]; } -static u32 ieee80211_handle_pwr_constr(struct ieee80211_link_data *link, +static u64 ieee80211_handle_pwr_constr(struct ieee80211_link_data *link, struct ieee80211_channel *channel, struct ieee80211_mgmt *mgmt, const u8 *country_ie, u8 country_ie_len, @@ -2223,7 +2198,8 @@ conf->flags &= ~IEEE80211_CONF_PS; ieee80211_hw_config(local, IEEE80211_CONF_CHANGE_PS); del_timer_sync(&local->dynamic_ps_timer); - cancel_work_sync(&local->dynamic_ps_enable_work); + wiphy_work_cancel(local->hw.wiphy, + &local->dynamic_ps_enable_work); } } @@ -2320,7 +2296,8 @@ } } -void ieee80211_dynamic_ps_disable_work(struct work_struct *work) +void ieee80211_dynamic_ps_disable_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, @@ -2337,7 +2314,8 @@ false); } -void ieee80211_dynamic_ps_enable_work(struct work_struct *work) +void ieee80211_dynamic_ps_enable_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, @@ -2410,26 +2388,25 @@ { struct ieee80211_local *local = from_timer(local, t, dynamic_ps_timer); - ieee80211_queue_work(&local->hw, &local->dynamic_ps_enable_work); + wiphy_work_queue(local->hw.wiphy, &local->dynamic_ps_enable_work); } -void ieee80211_dfs_cac_timer_work(struct work_struct *work) +void ieee80211_dfs_cac_timer_work(struct wiphy *wiphy, struct wiphy_work *work) { - struct delayed_work *delayed_work = to_delayed_work(work); struct ieee80211_link_data *link = - container_of(delayed_work, struct ieee80211_link_data, - dfs_cac_timer_work); + container_of(work, struct ieee80211_link_data, + dfs_cac_timer_work.work); struct cfg80211_chan_def chandef = link->conf->chandef; struct ieee80211_sub_if_data *sdata = link->sdata; - mutex_lock(&sdata->local->mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + if (sdata->wdev.cac_started) { ieee80211_link_release_channel(link); cfg80211_cac_event(sdata->dev, &chandef, NL80211_RADAR_CAC_FINISHED, GFP_KERNEL); } - mutex_unlock(&sdata->local->mtx); } static bool @@ -2499,8 +2476,10 @@ ac); tx_tspec->action = TX_TSPEC_ACTION_NONE; ret = true; - schedule_delayed_work(&ifmgd->tx_tspec_wk, - tx_tspec->time_slice_start + HZ - now + 1); + wiphy_delayed_work_queue(local->hw.wiphy, + &ifmgd->tx_tspec_wk, + tx_tspec->time_slice_start + + HZ - now + 1); break; case TX_TSPEC_ACTION_NONE: /* nothing now */ @@ -2518,7 +2497,8 @@ BSS_CHANGED_QOS); } -static void ieee80211_sta_handle_tspec_ac_params_wk(struct work_struct *work) +static void ieee80211_sta_handle_tspec_ac_params_wk(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata; @@ -2650,7 +2630,7 @@ params[ac].aifs = pos[0] & 0x0f; if (params[ac].aifs < 2) { - sdata_info(sdata, + link_info(link, "AP has invalid WMM params (AIFSN=%d for ACI %d), will use 2\n", params[ac].aifs, aci); params[ac].aifs = 2; @@ -2663,7 +2643,7 @@ if (params[ac].cw_min == 0 || params[ac].cw_min > params[ac].cw_max) { - sdata_info(sdata, + link_info(link, "AP has invalid WMM params (CWmin/max=%d/%d for ACI %d), using defaults\n", params[ac].cw_min, params[ac].cw_max, aci); return false; @@ -2674,7 +2654,7 @@ /* WMM specification requires all 4 ACIs. */ for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) { if (params[ac].cw_min == 0) { - sdata_info(sdata, + link_info(link, "AP has invalid WMM params (missing AC %d), using defaults\n", ac); return false; @@ -2693,7 +2673,7 @@ static void __ieee80211_stop_poll(struct ieee80211_sub_if_data *sdata) { - lockdep_assert_held(&sdata->local->mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); sdata->u.mgd.flags &= ~IEEE80211_STA_CONNECTION_POLL; ieee80211_run_deferred_scan(sdata->local); @@ -2701,17 +2681,17 @@ static void ieee80211_stop_poll(struct ieee80211_sub_if_data *sdata) { - mutex_lock(&sdata->local->mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + __ieee80211_stop_poll(sdata); - mutex_unlock(&sdata->local->mtx); } -static u32 ieee80211_handle_bss_capability(struct ieee80211_link_data *link, +static u64 ieee80211_handle_bss_capability(struct ieee80211_link_data *link, u16 capab, bool erp_valid, u8 erp) { struct ieee80211_bss_conf *bss_conf = link->conf; struct ieee80211_supported_band *sband; - u32 changed = 0; + u64 changed = 0; bool use_protection; bool use_short_preamble; bool use_short_slot; @@ -2757,7 +2737,7 @@ struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_bss_conf *bss_conf = link->conf; struct ieee80211_bss *bss = (void *)cbss->priv; - u32 changed = BSS_CHANGED_QOS; + u64 changed = BSS_CHANGED_QOS; /* not really used in MLO */ sdata->u.mgd.beacon_timeout = @@ -2821,6 +2801,8 @@ u64 vif_changed = BSS_CHANGED_ASSOC; unsigned int link_id; + lockdep_assert_wiphy(local->hw.wiphy); + sdata->u.mgd.associated = true; for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) { @@ -2831,6 +2813,10 @@ assoc_data->link[link_id].status != WLAN_STATUS_SUCCESS) continue; + if (ieee80211_vif_is_mld(&sdata->vif) && + !(ieee80211_vif_usable_links(&sdata->vif) & BIT(link_id))) + continue; + link = sdata_dereference(sdata->link[link_id], sdata); if (WARN_ON(!link)) return; @@ -2849,7 +2835,7 @@ if (vif_cfg->arp_addr_cnt) vif_changed |= BSS_CHANGED_ARP_FILTER; - if (sdata->vif.valid_links) { + if (ieee80211_vif_is_mld(&sdata->vif)) { for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) { @@ -2857,6 +2843,8 @@ struct cfg80211_bss *cbss = assoc_data->link[link_id].bss; if (!cbss || + !(BIT(link_id) & + ieee80211_vif_usable_links(&sdata->vif)) || assoc_data->link[link_id].status != WLAN_STATUS_SUCCESS) continue; @@ -2876,12 +2864,10 @@ vif_changed | changed[0]); } - mutex_lock(&local->iflist_mtx); ieee80211_recalc_ps(local); - mutex_unlock(&local->iflist_mtx); /* leave this here to not change ordering in non-MLO cases */ - if (!sdata->vif.valid_links) + if (!ieee80211_vif_is_mld(&sdata->vif)) ieee80211_recalc_smps(sdata, &sdata->deflink); ieee80211_recalc_ps_vif(sdata); @@ -2895,12 +2881,12 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; struct ieee80211_local *local = sdata->local; unsigned int link_id; - u32 changed = 0; + u64 changed = 0; struct ieee80211_prep_tx_info info = { .subtype = stype, }; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON_ONCE(tx && !frame_buf)) return; @@ -2951,10 +2937,23 @@ * deauthentication frame by calling mgd_prepare_tx, if the * driver requested so. */ - if (ieee80211_hw_check(&local->hw, DEAUTH_NEED_MGD_TX_PREP) && - !sdata->deflink.u.mgd.have_beacon) { + if (ieee80211_hw_check(&local->hw, DEAUTH_NEED_MGD_TX_PREP)) { + for (link_id = 0; link_id < ARRAY_SIZE(sdata->link); + link_id++) { + struct ieee80211_link_data *link; + + link = sdata_dereference(sdata->link[link_id], + sdata); + if (!link) + continue; + if (link->u.mgd.have_beacon) + break; + } + if (link_id == IEEE80211_MLD_MAX_NUM_LINKS) { + info.link_id = ffs(sdata->vif.active_links) - 1; drv_mgd_prepare_tx(sdata->local, sdata, &info); } + } ieee80211_send_deauth_disassoc(sdata, sdata->vif.cfg.ap_addr, sdata->vif.cfg.ap_addr, stype, @@ -2977,7 +2976,7 @@ sta_info_flush(sdata); /* finally reset all BSS / config parameters */ - if (!sdata->vif.valid_links) + if (!ieee80211_vif_is_mld(&sdata->vif)) changed |= ieee80211_reset_erp_info(sdata); ieee80211_led_assoc(local, 0); @@ -3002,21 +3001,21 @@ sizeof(sdata->vif.bss_conf.mu_group.membership)); memset(sdata->vif.bss_conf.mu_group.position, 0, sizeof(sdata->vif.bss_conf.mu_group.position)); - if (!sdata->vif.valid_links) + if (!ieee80211_vif_is_mld(&sdata->vif)) changed |= BSS_CHANGED_MU_GROUPS; sdata->vif.bss_conf.mu_mimo_owner = false; sdata->deflink.ap_power_level = IEEE80211_UNSET_POWER_LEVEL; del_timer_sync(&local->dynamic_ps_timer); - cancel_work_sync(&local->dynamic_ps_enable_work); + wiphy_work_cancel(local->hw.wiphy, &local->dynamic_ps_enable_work); /* Disable ARP filtering */ if (sdata->vif.cfg.arp_addr_cnt) changed |= BSS_CHANGED_ARP_FILTER; sdata->vif.bss_conf.qos = false; - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { changed |= BSS_CHANGED_QOS; /* The BSSID (not really interesting) and HT changed */ changed |= BSS_CHANGED_BSSID | BSS_CHANGED_HT; @@ -3031,7 +3030,6 @@ del_timer_sync(&sdata->u.mgd.conn_mon_timer); del_timer_sync(&sdata->u.mgd.bcn_mon_timer); del_timer_sync(&sdata->u.mgd.timer); - del_timer_sync(&sdata->deflink.u.mgd.chswitch_timer); sdata->vif.bss_conf.dtim_period = 0; sdata->vif.bss_conf.beacon_rate = NULL; @@ -3042,7 +3040,6 @@ ifmgd->flags = 0; sdata->deflink.u.mgd.conn_flags = 0; - mutex_lock(&local->mtx); for (link_id = 0; link_id < ARRAY_SIZE(sdata->link); link_id++) { struct ieee80211_link_data *link; @@ -3061,18 +3058,20 @@ IEEE80211_QUEUE_STOP_REASON_CSA); sdata->deflink.csa_block_tx = false; } - mutex_unlock(&local->mtx); /* existing TX TSPEC sessions no longer exist */ memset(ifmgd->tx_tspec, 0, sizeof(ifmgd->tx_tspec)); - cancel_delayed_work_sync(&ifmgd->tx_tspec_wk); + wiphy_delayed_work_cancel(local->hw.wiphy, &ifmgd->tx_tspec_wk); sdata->vif.bss_conf.pwr_reduction = 0; sdata->vif.bss_conf.tx_pwr_env_num = 0; memset(sdata->vif.bss_conf.tx_pwr_env, 0, sizeof(sdata->vif.bss_conf.tx_pwr_env)); - ieee80211_vif_set_links(sdata, 0); + memset(&sdata->u.mgd.ttlm_info, 0, + sizeof(sdata->u.mgd.ttlm_info)); + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, &ifmgd->ttlm_work); + ieee80211_vif_set_links(sdata, 0, 0); } static void ieee80211_reset_ap_probe(struct ieee80211_sub_if_data *sdata) @@ -3080,18 +3079,17 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; struct ieee80211_local *local = sdata->local; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); + if (!(ifmgd->flags & IEEE80211_STA_CONNECTION_POLL)) - goto out; + return; __ieee80211_stop_poll(sdata); - mutex_lock(&local->iflist_mtx); ieee80211_recalc_ps(local); - mutex_unlock(&local->iflist_mtx); if (ieee80211_hw_check(&sdata->local->hw, CONNECTION_MONITOR)) - goto out; + return; /* * We've received a probe response, but are not sure whether @@ -3103,8 +3101,6 @@ mod_timer(&ifmgd->conn_mon_timer, round_jiffies_up(jiffies + IEEE80211_CONNECTION_IDLE_TIME)); -out: - mutex_unlock(&local->mtx); } static void ieee80211_sta_tx_wmm_ac_notify(struct ieee80211_sub_if_data *sdata, @@ -3133,7 +3129,8 @@ if (tx_tspec->downgraded) { tx_tspec->action = TX_TSPEC_ACTION_STOP_DOWNGRADE; - schedule_delayed_work(&ifmgd->tx_tspec_wk, 0); + wiphy_delayed_work_queue(sdata->local->hw.wiphy, + &ifmgd->tx_tspec_wk, 0); } } @@ -3145,7 +3142,8 @@ if (tx_tspec->consumed_tx_time >= tx_tspec->admitted_time) { tx_tspec->downgraded = true; tx_tspec->action = TX_TSPEC_ACTION_DOWNGRADE; - schedule_delayed_work(&ifmgd->tx_tspec_wk, 0); + wiphy_delayed_work_queue(sdata->local->hw.wiphy, + &ifmgd->tx_tspec_wk, 0); } } @@ -3162,7 +3160,7 @@ sdata->u.mgd.probe_send_count = 0; else sdata->u.mgd.nullfunc_failed = true; - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } static void ieee80211_mlme_send_probe_req(struct ieee80211_sub_if_data *sdata, @@ -3186,7 +3184,9 @@ u8 unicast_limit = max(1, max_probe_tries - 3); struct sta_info *sta; - if (WARN_ON(sdata->vif.valid_links)) + lockdep_assert_wiphy(sdata->local->hw.wiphy); + + if (WARN_ON(ieee80211_vif_is_mld(&sdata->vif))) return; /* @@ -3207,11 +3207,9 @@ ifmgd->probe_send_count++; if (dst) { - mutex_lock(&sdata->local->sta_mtx); sta = sta_info_get(sdata, dst); if (!WARN_ON(!sta)) ieee80211_check_fast_rx(sta); - mutex_unlock(&sdata->local->sta_mtx); } if (ieee80211_hw_check(&sdata->local->hw, REPORTS_TX_ACK_STATUS)) { @@ -3234,29 +3232,24 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; bool already = false; - if (WARN_ON_ONCE(sdata->vif.valid_links)) + lockdep_assert_wiphy(sdata->local->hw.wiphy); + + if (WARN_ON_ONCE(ieee80211_vif_is_mld(&sdata->vif))) return; if (!ieee80211_sdata_running(sdata)) return; - sdata_lock(sdata); - if (!ifmgd->associated) - goto out; - - mutex_lock(&sdata->local->mtx); + return; - if (sdata->local->tmp_channel || sdata->local->scanning) { - mutex_unlock(&sdata->local->mtx); - goto out; - } + if (sdata->local->tmp_channel || sdata->local->scanning) + return; if (sdata->local->suspending) { /* reschedule after resume */ - mutex_unlock(&sdata->local->mtx); ieee80211_reset_ap_probe(sdata); - goto out; + return; } if (beacon) { @@ -3283,19 +3276,13 @@ ifmgd->flags |= IEEE80211_STA_CONNECTION_POLL; - mutex_unlock(&sdata->local->mtx); - if (already) - goto out; + return; - mutex_lock(&sdata->local->iflist_mtx); ieee80211_recalc_ps(sdata->local); - mutex_unlock(&sdata->local->iflist_mtx); ifmgd->probe_send_count = 0; ieee80211_mgd_probe_ap_send(sdata); - out: - sdata_unlock(sdata); } struct sk_buff *ieee80211_ap_probereq_get(struct ieee80211_hw *hw, @@ -3308,12 +3295,12 @@ const struct element *ssid; int ssid_len; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + if (WARN_ON(sdata->vif.type != NL80211_IFTYPE_STATION || - sdata->vif.valid_links)) + ieee80211_vif_is_mld(&sdata->vif))) return NULL; - sdata_assert_lock(sdata); - if (ifmgd->associated) cbss = sdata->deflink.u.mgd.bss; else if (ifmgd->auth_data) @@ -3367,14 +3354,14 @@ u8 frame_buf[IEEE80211_DEAUTH_FRAME_LEN]; bool tx; - sdata_lock(sdata); - if (!ifmgd->associated) { - sdata_unlock(sdata); + lockdep_assert_wiphy(local->hw.wiphy); + + if (!ifmgd->associated) return; - } /* in MLO assume we have a link where we can TX the frame */ - tx = sdata->vif.valid_links || !sdata->deflink.csa_block_tx; + tx = ieee80211_vif_is_mld(&sdata->vif) || + !sdata->deflink.csa_block_tx; if (!ifmgd->driver_disconnect) { unsigned int link_id; @@ -3404,7 +3391,6 @@ WLAN_REASON_DEAUTH_LEAVING : WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY, tx, frame_buf); - mutex_lock(&local->mtx); /* the other links will be destroyed */ sdata->vif.bss_conf.csa_active = false; sdata->deflink.u.mgd.csa_waiting_bcn = false; @@ -3413,17 +3399,15 @@ IEEE80211_QUEUE_STOP_REASON_CSA); sdata->deflink.csa_block_tx = false; } - mutex_unlock(&local->mtx); ieee80211_report_disconnect(sdata, frame_buf, sizeof(frame_buf), tx, WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY, ifmgd->reconnect); ifmgd->reconnect = false; - - sdata_unlock(sdata); } -static void ieee80211_beacon_connection_loss_work(struct work_struct *work) +static void ieee80211_beacon_connection_loss_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata = container_of(work, struct ieee80211_sub_if_data, @@ -3448,7 +3432,8 @@ } } -static void ieee80211_csa_connection_drop_work(struct work_struct *work) +static void ieee80211_csa_connection_drop_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata = container_of(work, struct ieee80211_sub_if_data, @@ -3465,7 +3450,7 @@ trace_api_beacon_loss(sdata); sdata->u.mgd.connection_loss = false; - ieee80211_queue_work(hw, &sdata->u.mgd.beacon_connection_loss_work); + wiphy_work_queue(hw->wiphy, &sdata->u.mgd.beacon_connection_loss_work); } EXPORT_SYMBOL(ieee80211_beacon_loss); @@ -3477,7 +3462,7 @@ trace_api_connection_loss(sdata); sdata->u.mgd.connection_loss = true; - ieee80211_queue_work(hw, &sdata->u.mgd.beacon_connection_loss_work); + wiphy_work_queue(hw->wiphy, &sdata->u.mgd.beacon_connection_loss_work); } EXPORT_SYMBOL(ieee80211_connection_loss); @@ -3493,7 +3478,7 @@ sdata->u.mgd.driver_disconnect = true; sdata->u.mgd.reconnect = reconnect; - ieee80211_queue_work(hw, &sdata->u.mgd.beacon_connection_loss_work); + wiphy_work_queue(hw->wiphy, &sdata->u.mgd.beacon_connection_loss_work); } EXPORT_SYMBOL(ieee80211_disconnect); @@ -3502,7 +3487,7 @@ { struct ieee80211_mgd_auth_data *auth_data = sdata->u.mgd.auth_data; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (!assoc) { /* @@ -3520,10 +3505,8 @@ BSS_CHANGED_BSSID); sdata->u.mgd.flags = 0; - mutex_lock(&sdata->local->mtx); ieee80211_link_release_channel(&sdata->deflink); - ieee80211_vif_set_links(sdata, 0); - mutex_unlock(&sdata->local->mtx); + ieee80211_vif_set_links(sdata, 0, 0); } cfg80211_put_bss(sdata->local->hw.wiphy, auth_data->bss); @@ -3543,7 +3526,7 @@ { struct ieee80211_mgd_assoc_data *assoc_data = sdata->u.mgd.assoc_data; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (status != ASSOC_SUCCESS) { /* @@ -3573,16 +3556,14 @@ for (i = 0; i < ARRAY_SIZE(data.bss); i++) data.bss[i] = assoc_data->link[i].bss; - if (sdata->vif.valid_links) + if (ieee80211_vif_is_mld(&sdata->vif)) data.ap_mld_addr = assoc_data->ap_addr; cfg80211_assoc_failure(sdata->dev, &data); } - mutex_lock(&sdata->local->mtx); ieee80211_link_release_channel(&sdata->deflink); - ieee80211_vif_set_links(sdata, 0); - mutex_unlock(&sdata->local->mtx); + ieee80211_vif_set_links(sdata, 0, 0); } kfree(assoc_data); @@ -3599,6 +3580,7 @@ u32 tx_flags = 0; struct ieee80211_prep_tx_info info = { .subtype = IEEE80211_STYPE_AUTH, + .link_id = auth_data->link_id, }; pos = mgmt->u.auth.variable; @@ -3624,7 +3606,8 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; const u8 *ap_addr = ifmgd->auth_data->ap_addr; struct sta_info *sta; - bool result = true; + + lockdep_assert_wiphy(sdata->local->hw.wiphy); sdata_info(sdata, "authenticated\n"); ifmgd->auth_data->done = true; @@ -3633,22 +3616,17 @@ run_again(sdata, ifmgd->auth_data->timeout); /* move station state to auth */ - mutex_lock(&sdata->local->sta_mtx); sta = sta_info_get(sdata, ap_addr); if (!sta) { WARN_ONCE(1, "%s: STA %pM not found", sdata->name, ap_addr); - result = false; - goto out; + return false; } if (sta_info_move_state(sta, IEEE80211_STA_AUTH)) { sdata_info(sdata, "failed moving %pM to auth\n", ap_addr); - result = false; - goto out; + return false; } -out: - mutex_unlock(&sdata->local->sta_mtx); - return result; + return true; } static void ieee80211_rx_mgmt_auth(struct ieee80211_sub_if_data *sdata, @@ -3664,7 +3642,7 @@ .subtype = IEEE80211_STYPE_AUTH, }; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (len < 24 + 6) return; @@ -3822,7 +3800,7 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; u16 reason_code = le16_to_cpu(mgmt->u.deauth.reason_code); - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (len < 24 + 2) return; @@ -3866,7 +3844,7 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; u16 reason_code; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (len < 24 + 2) return; @@ -3896,8 +3874,7 @@ u8 *supp_rates, unsigned int supp_rates_len, u32 *rates, u32 *basic_rates, bool *have_higher_than_11mbit, - int *min_rate, int *min_rate_index, - int shift) + int *min_rate, int *min_rate_index) { int i, j; @@ -3905,12 +3882,12 @@ int rate = supp_rates[i] & 0x7f; bool is_basic = !!(supp_rates[i] & 0x80); - if ((rate * 5 * (1 << shift)) > 110) + if ((rate * 5) > 110) *have_higher_than_11mbit = true; /* - * Skip HT, VHT, HE and SAE H2E only BSS membership selectors - * since they're not rates. + * Skip HT, VHT, HE, EHT and SAE H2E only BSS membership + * selectors since they're not rates. * * Note: Even though the membership selector and the basic * rate flag share the same bit, they are not exactly @@ -3919,6 +3896,7 @@ if (supp_rates[i] == (0x80 | BSS_MEMBERSHIP_SELECTOR_HT_PHY) || supp_rates[i] == (0x80 | BSS_MEMBERSHIP_SELECTOR_VHT_PHY) || supp_rates[i] == (0x80 | BSS_MEMBERSHIP_SELECTOR_HE_PHY) || + supp_rates[i] == (0x80 | BSS_MEMBERSHIP_SELECTOR_EHT_PHY) || supp_rates[i] == (0x80 | BSS_MEMBERSHIP_SELECTOR_SAE_H2E)) continue; @@ -3928,7 +3906,7 @@ br = &sband->bitrates[j]; - brate = DIV_ROUND_UP(br->bitrate, (1 << shift) * 5); + brate = DIV_ROUND_UP(br->bitrate, 5); if (brate == rate) { *rates |= BIT(j); if (is_basic) @@ -3949,8 +3927,7 @@ const struct ieee802_11_elems *elems) { const struct ieee80211_sta_he_cap *own_he_cap = - ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); if (elems->ext_capab_len < 10) return false; @@ -3965,7 +3942,7 @@ IEEE80211_HE_MAC_CAP0_TWT_REQ); } -static int ieee80211_recalc_twt_req(struct ieee80211_sub_if_data *sdata, +static u64 ieee80211_recalc_twt_req(struct ieee80211_sub_if_data *sdata, struct ieee80211_supported_band *sband, struct ieee80211_link_data *link, struct link_sta_info *link_sta, @@ -3986,8 +3963,7 @@ struct link_sta_info *link_sta) { const struct ieee80211_sta_he_cap *own_he_cap = - ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); return bss_conf->he_support && (link_sta->pub->he_cap.he_cap_elem.mac_cap_info[2] & @@ -4021,6 +3997,8 @@ const struct cfg80211_bss_ies *bss_ies = NULL; struct ieee80211_supported_band *sband; struct ieee802_11_elems *elems; + const __le16 prof_bss_param_ch_present = + cpu_to_le16(IEEE80211_MLE_STA_CONTROL_BSS_PARAM_CHANGE_CNT_PRESENT); u16 capab_info; bool ret; @@ -4036,7 +4014,17 @@ * successful, so set the status directly to success */ assoc_data->link[link_id].status = WLAN_STATUS_SUCCESS; - } else if (!elems->prof) { + if (elems->ml_basic) { + if (!(elems->ml_basic->control & + cpu_to_le16(IEEE80211_MLC_BASIC_PRES_BSS_PARAM_CH_CNT))) { + ret = false; + goto out; + } + link->u.mgd.bss_param_ch_cnt = + ieee80211_mle_get_bss_param_ch_cnt(elems->ml_basic); + } + } else if (!elems->prof || + !(elems->prof->control & prof_bss_param_ch_present)) { ret = false; goto out; } else { @@ -4049,6 +4037,8 @@ */ capab_info = get_unaligned_le16(ptr); assoc_data->link[link_id].status = get_unaligned_le16(ptr + 2); + link->u.mgd.bss_param_ch_cnt = + ieee80211_mle_basic_sta_prof_bss_param_ch_cnt(elems->prof); if (assoc_data->link[link_id].status != WLAN_STATUS_SUCCESS) { link_info(link, "association response status code=%u\n", @@ -4191,10 +4181,33 @@ elems->ht_cap_elem, link_sta); - if (elems->vht_cap_elem && !(link->u.mgd.conn_flags & IEEE80211_CONN_DISABLE_VHT)) + if (elems->vht_cap_elem && + !(link->u.mgd.conn_flags & IEEE80211_CONN_DISABLE_VHT)) { + const struct ieee80211_vht_cap *bss_vht_cap = NULL; + const struct cfg80211_bss_ies *ies; + + /* + * Cisco AP module 9115 with FW 17.3 has a bug and sends a + * too large maximum MPDU length in the association response + * (indicating 12k) that it cannot actually process ... + * Work around that. + */ + rcu_read_lock(); + ies = rcu_dereference(cbss->ies); + if (ies) { + const struct element *elem; + + elem = cfg80211_find_elem(WLAN_EID_VHT_CAPABILITY, + ies->data, ies->len); + if (elem && elem->datalen >= sizeof(*bss_vht_cap)) + bss_vht_cap = (const void *)elem->data; + } + ieee80211_vht_cap_ie_to_sta_vht_cap(sdata, sband, elems->vht_cap_elem, - link_sta); + bss_vht_cap, link_sta); + rcu_read_unlock(); + } if (elems->he_operation && !(link->u.mgd.conn_flags & IEEE80211_CONN_DISABLE_HE) && elems->he_cap) { @@ -4360,8 +4373,6 @@ u32 rates = 0, basic_rates = 0; bool have_higher_than_11mbit = false; int min_rate = INT_MAX, min_rate_index = -1; - /* this is clearly wrong for MLO but we'll just remove it later */ - int shift = ieee80211_vif_get_shift(&sdata->vif); struct ieee80211_supported_band *sband; memcpy(link_sta->addr, cbss->bssid, ETH_ALEN); @@ -4377,7 +4388,7 @@ ieee80211_get_rates(sband, bss->supp_rates, bss->supp_rates_len, &rates, &basic_rates, &have_higher_than_11mbit, - &min_rate, &min_rate_index, shift); + &min_rate, &min_rate_index); /* * This used to be a workaround for basic rates missing @@ -4624,8 +4635,7 @@ const struct ieee80211_he_operation *he_op) { const struct ieee80211_sta_he_cap *sta_he_cap = - ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); u16 ap_min_req_set; int i; @@ -4698,9 +4708,93 @@ return false; } +static u8 +ieee80211_get_eht_cap_mcs_nss(const struct ieee80211_sta_he_cap *sta_he_cap, + const struct ieee80211_sta_eht_cap *sta_eht_cap, + unsigned int idx, int bw) +{ + u8 he_phy_cap0 = sta_he_cap->he_cap_elem.phy_cap_info[0]; + u8 eht_phy_cap0 = sta_eht_cap->eht_cap_elem.phy_cap_info[0]; + + /* handle us being a 20 MHz-only EHT STA - with four values + * for MCS 0-7, 8-9, 10-11, 12-13. + */ + if (!(he_phy_cap0 & IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) + return sta_eht_cap->eht_mcs_nss_supp.only_20mhz.rx_tx_max_nss[idx]; + + /* the others have MCS 0-9 together, rather than separately from 0-7 */ + if (idx > 0) + idx--; + + switch (bw) { + case 0: + return sta_eht_cap->eht_mcs_nss_supp.bw._80.rx_tx_max_nss[idx]; + case 1: + if (!(he_phy_cap0 & + (IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G | + IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G))) + return 0xff; /* pass check */ + return sta_eht_cap->eht_mcs_nss_supp.bw._160.rx_tx_max_nss[idx]; + case 2: + if (!(eht_phy_cap0 & IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ)) + return 0xff; /* pass check */ + return sta_eht_cap->eht_mcs_nss_supp.bw._320.rx_tx_max_nss[idx]; + } + + WARN_ON(1); + return 0; +} + +static bool +ieee80211_verify_sta_eht_mcs_support(struct ieee80211_sub_if_data *sdata, + struct ieee80211_supported_band *sband, + const struct ieee80211_eht_operation *eht_op) +{ + const struct ieee80211_sta_he_cap *sta_he_cap = + ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); + const struct ieee80211_sta_eht_cap *sta_eht_cap = + ieee80211_get_eht_iftype_cap_vif(sband, &sdata->vif); + const struct ieee80211_eht_mcs_nss_supp_20mhz_only *req; + unsigned int i; + + if (!sta_he_cap || !sta_eht_cap || !eht_op) + return false; + + req = &eht_op->basic_mcs_nss; + + for (i = 0; i < ARRAY_SIZE(req->rx_tx_max_nss); i++) { + u8 req_rx_nss, req_tx_nss; + unsigned int bw; + + req_rx_nss = u8_get_bits(req->rx_tx_max_nss[i], + IEEE80211_EHT_MCS_NSS_RX); + req_tx_nss = u8_get_bits(req->rx_tx_max_nss[i], + IEEE80211_EHT_MCS_NSS_TX); + + for (bw = 0; bw < 3; bw++) { + u8 have, have_rx_nss, have_tx_nss; + + have = ieee80211_get_eht_cap_mcs_nss(sta_he_cap, + sta_eht_cap, + i, bw); + have_rx_nss = u8_get_bits(have, + IEEE80211_EHT_MCS_NSS_RX); + have_tx_nss = u8_get_bits(have, + IEEE80211_EHT_MCS_NSS_TX); + + if (req_rx_nss > have_rx_nss || + req_tx_nss > have_tx_nss) + return false; + } + } + + return true; +} + static int ieee80211_prep_channel(struct ieee80211_sub_if_data *sdata, struct ieee80211_link_data *link, struct cfg80211_bss *cbss, + bool mlo, ieee80211_conn_flags_t *conn_flags) { struct ieee80211_local *local = sdata->local; @@ -4714,9 +4808,9 @@ struct cfg80211_chan_def chandef; bool is_6ghz = cbss->channel->band == NL80211_BAND_6GHZ; bool is_5ghz = cbss->channel->band == NL80211_BAND_5GHZ; + bool supports_mlo = false; struct ieee80211_bss *bss = (void *)cbss->priv; struct ieee80211_elems_parse_params parse_params = { - .bss = cbss, .link_id = -1, .from_ap = true, }; @@ -4726,6 +4820,8 @@ u32 i; bool have_80mhz; + lockdep_assert_wiphy(local->hw.wiphy); + rcu_read_lock(); ies = rcu_dereference(cbss->ies); @@ -4759,15 +4855,13 @@ *conn_flags |= IEEE80211_CONN_DISABLE_EHT; } - if (!ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif))) { + if (!ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif)) { mlme_dbg(sdata, "HE not supported, disabling HE and EHT\n"); *conn_flags |= IEEE80211_CONN_DISABLE_HE; *conn_flags |= IEEE80211_CONN_DISABLE_EHT; } - if (!ieee80211_get_eht_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif))) { + if (!ieee80211_get_eht_iftype_cap_vif(sband, &sdata->vif)) { mlme_dbg(sdata, "EHT not supported, disabling EHT\n"); *conn_flags |= IEEE80211_CONN_DISABLE_EHT; } @@ -4844,6 +4938,7 @@ IEEE80211_CONN_DISABLE_EHT)) && he_oper) { const struct cfg80211_bss_ies *cbss_ies; + const struct element *eht_ml_elem; const u8 *eht_oper_ie; cbss_ies = rcu_dereference(cbss->ies); @@ -4854,6 +4949,26 @@ eht_oper = (void *)(eht_oper_ie + 3); else eht_oper = NULL; + + if (!ieee80211_verify_sta_eht_mcs_support(sdata, sband, eht_oper)) + *conn_flags |= IEEE80211_CONN_DISABLE_EHT; + + eht_ml_elem = cfg80211_find_ext_elem(WLAN_EID_EXT_EHT_MULTI_LINK, + cbss_ies->data, cbss_ies->len); + + /* data + 1 / datalen - 1 since it's an extended element */ + if (!(*conn_flags & IEEE80211_CONN_DISABLE_EHT) && + eht_ml_elem && + ieee80211_mle_type_ok(eht_ml_elem->data + 1, + IEEE80211_ML_CONTROL_TYPE_BASIC, + eht_ml_elem->datalen - 1)) { + supports_mlo = true; + + sdata->vif.cfg.eml_cap = + ieee80211_mle_get_eml_cap(eht_ml_elem->data + 1); + sdata->vif.cfg.eml_med_sync_delay = + ieee80211_mle_get_eml_med_sync_delay(eht_ml_elem->data + 1); + } } /* Allow VHT if at least one channel on the sband supports 80 MHz */ @@ -4904,13 +5019,17 @@ return -EINVAL; } + if (mlo && !supports_mlo) { + sdata_info(sdata, "Rejecting MLO as it is not supported by AP\n"); + return -EINVAL; + } + if (!link) return 0; /* will change later if needed */ link->smps_mode = IEEE80211_SMPS_OFF; - mutex_lock(&local->mtx); /* * If this fails (possibly due to channel context sharing * on incompatible channels, e.g. 80+80 and 160 sharing the @@ -4931,7 +5050,6 @@ IEEE80211_CHANCTX_SHARED); } out: - mutex_unlock(&local->mtx); return ret; } @@ -4980,10 +5098,10 @@ unsigned int link_id; struct sta_info *sta; u64 changed[IEEE80211_MLD_MAX_NUM_LINKS] = {}; - u16 valid_links = 0; + u16 valid_links = 0, dormant_links = 0; int err; - mutex_lock(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); /* * station info was already allocated and inserted before * the association and should be available to us @@ -4992,11 +5110,14 @@ if (WARN_ON(!sta)) goto out_err; - if (sdata->vif.valid_links) { + if (ieee80211_vif_is_mld(&sdata->vif)) { for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) { if (!assoc_data->link[link_id].bss) continue; + valid_links |= BIT(link_id); + if (assoc_data->link[link_id].disabled) + dormant_links |= BIT(link_id); if (link_id != assoc_data->assoc_link_id) { err = ieee80211_sta_allocate_link(sta, link_id); @@ -5005,7 +5126,7 @@ } } - ieee80211_vif_set_links(sdata, valid_links); + ieee80211_vif_set_links(sdata, valid_links, dormant_links); } for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) { @@ -5020,7 +5141,7 @@ if (WARN_ON(!link)) goto out_err; - if (sdata->vif.valid_links) + if (ieee80211_vif_is_mld(&sdata->vif)) link_info(link, "local address %pM, AP link address %pM%s\n", link->conf->addr, @@ -5029,7 +5150,7 @@ " (assoc)" : ""); link_sta = rcu_dereference_protected(sta->link[link_id], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (WARN_ON(!link_sta)) goto out_err; @@ -5052,7 +5173,7 @@ link->conf->dtim_period = link->u.mgd.dtim_period ?: 1; if (link_id != assoc_data->assoc_link_id) { - err = ieee80211_prep_channel(sdata, link, cbss, + err = ieee80211_prep_channel(sdata, link, cbss, true, &link->u.mgd.conn_flags); if (err) { link_info(link, "prep_channel failed\n"); @@ -5085,7 +5206,7 @@ } /* links might have changed due to rejected ones, set them again */ - ieee80211_vif_set_links(sdata, valid_links); + ieee80211_vif_set_links(sdata, valid_links, dormant_links); rate_control_rate_init(sta); @@ -5116,8 +5237,6 @@ if (sdata->wdev.use_4addr) drv_sta_set_4addr(local, sdata, &sta->sta, true); - mutex_unlock(&sdata->local->sta_mtx); - ieee80211_set_associated(sdata, assoc_data, changed); /* @@ -5137,7 +5256,6 @@ return true; out_err: eth_zero_addr(sdata->vif.cfg.ap_addr); - mutex_unlock(&sdata->local->sta_mtx); return false; } @@ -5163,13 +5281,13 @@ .u.mlme.data = ASSOC_EVENT, }; struct ieee80211_prep_tx_info info = {}; - struct cfg80211_rx_assoc_resp resp = { + struct cfg80211_rx_assoc_resp_data resp = { .uapsd_queues = -1, }; u8 ap_mld_addr[ETH_ALEN] __aligned(2); unsigned int link_id; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (!assoc_data) return; @@ -5269,25 +5387,25 @@ ifmgd->broken_ap = true; } - if (sdata->vif.valid_links) { - if (!elems->multi_link) { + if (ieee80211_vif_is_mld(&sdata->vif)) { + if (!elems->ml_basic) { sdata_info(sdata, "MLO association with %pM but no multi-link element in response!\n", assoc_data->ap_addr); goto abandon_assoc; } - if (le16_get_bits(elems->multi_link->control, + if (le16_get_bits(elems->ml_basic->control, IEEE80211_ML_CONTROL_TYPE) != IEEE80211_ML_CONTROL_TYPE_BASIC) { sdata_info(sdata, "bad multi-link element (control=0x%x)\n", - le16_to_cpu(elems->multi_link->control)); + le16_to_cpu(elems->ml_basic->control)); goto abandon_assoc; } else { struct ieee80211_mle_basic_common_info *common; - common = (void *)elems->multi_link->variable; + common = (void *)elems->ml_basic->variable; if (memcmp(assoc_data->ap_addr, common->mld_mac_addr, ETH_ALEN)) { @@ -5318,17 +5436,18 @@ for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) { struct ieee80211_link_data *link; - link = sdata_dereference(sdata->link[link_id], sdata); - if (!link) - continue; - if (!assoc_data->link[link_id].bss) continue; resp.links[link_id].bss = assoc_data->link[link_id].bss; - resp.links[link_id].addr = link->conf->addr; + ether_addr_copy(resp.links[link_id].addr, + assoc_data->link[link_id].addr); resp.links[link_id].status = assoc_data->link[link_id].status; + link = sdata_dereference(sdata->link[link_id], sdata); + if (!link) + continue; + /* get uapsd queues configuration - same for all links */ resp.uapsd_queues = 0; for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) @@ -5336,7 +5455,7 @@ resp.uapsd_queues |= ieee80211_ac_to_qos_mask[ac]; } - if (sdata->vif.valid_links) { + if (ieee80211_vif_is_mld(&sdata->vif)) { ether_addr_copy(ap_mld_addr, sdata->vif.cfg.ap_addr); resp.ap_mld_addr = ap_mld_addr; } @@ -5369,7 +5488,7 @@ struct ieee80211_bss *bss; struct ieee80211_channel *channel; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); channel = ieee80211_get_channel_khz(local->hw.wiphy, ieee80211_rx_status_to_khz(rx_status)); @@ -5396,7 +5515,7 @@ ifmgd = &sdata->u.mgd; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); /* * According to Draft P802.11ax D6.0 clause 26.17.2.3.2: @@ -5598,6 +5717,351 @@ return true; } +static void ieee80211_ml_reconf_work(struct wiphy *wiphy, + struct wiphy_work *work) +{ + struct ieee80211_sub_if_data *sdata = + container_of(work, struct ieee80211_sub_if_data, + u.mgd.ml_reconf_work.work); + u16 new_valid_links, new_active_links, new_dormant_links; + int ret; + + if (!sdata->u.mgd.removed_links) + return; + + sdata_info(sdata, + "MLO Reconfiguration: work: valid=0x%x, removed=0x%x\n", + sdata->vif.valid_links, sdata->u.mgd.removed_links); + + new_valid_links = sdata->vif.valid_links & ~sdata->u.mgd.removed_links; + if (new_valid_links == sdata->vif.valid_links) + return; + + if (!new_valid_links || + !(new_valid_links & ~sdata->vif.dormant_links)) { + sdata_info(sdata, "No valid links after reconfiguration\n"); + ret = -EINVAL; + goto out; + } + + new_active_links = sdata->vif.active_links & ~sdata->u.mgd.removed_links; + if (new_active_links != sdata->vif.active_links) { + if (!new_active_links) + new_active_links = + BIT(ffs(new_valid_links & + ~sdata->vif.dormant_links) - 1); + + ret = ieee80211_set_active_links(&sdata->vif, new_active_links); + if (ret) { + sdata_info(sdata, + "Failed setting active links\n"); + goto out; + } + } + + new_dormant_links = sdata->vif.dormant_links & ~sdata->u.mgd.removed_links; + + ret = ieee80211_vif_set_links(sdata, new_valid_links, + new_dormant_links); + if (ret) + sdata_info(sdata, "Failed setting valid links\n"); + + ieee80211_vif_cfg_change_notify(sdata, BSS_CHANGED_MLD_VALID_LINKS); + +out: + if (!ret) + cfg80211_links_removed(sdata->dev, sdata->u.mgd.removed_links); + else + __ieee80211_disconnect(sdata); + + sdata->u.mgd.removed_links = 0; +} + +static void ieee80211_ml_reconfiguration(struct ieee80211_sub_if_data *sdata, + struct ieee802_11_elems *elems) +{ + const struct ieee80211_multi_link_elem *ml; + const struct element *sub; + size_t ml_len; + unsigned long removed_links = 0; + u16 link_removal_timeout[IEEE80211_MLD_MAX_NUM_LINKS] = {}; + u8 link_id; + u32 delay; + + if (!ieee80211_vif_is_mld(&sdata->vif) || !elems->ml_reconf) + return; + + ml_len = cfg80211_defragment_element(elems->ml_reconf_elem, + elems->ie_start, + elems->total_len, + elems->scratch_pos, + elems->scratch + elems->scratch_len - + elems->scratch_pos, + WLAN_EID_FRAGMENT); + + elems->ml_reconf = (const void *)elems->scratch_pos; + elems->ml_reconf_len = ml_len; + ml = elems->ml_reconf; + + /* Directly parse the sub elements as the common information doesn't + * hold any useful information. + */ + for_each_mle_subelement(sub, (u8 *)ml, ml_len) { + struct ieee80211_mle_per_sta_profile *prof = (void *)sub->data; + u8 *pos = prof->variable; + u16 control; + + if (sub->id != IEEE80211_MLE_SUBELEM_PER_STA_PROFILE) + continue; + + if (!ieee80211_mle_reconf_sta_prof_size_ok(sub->data, + sub->datalen)) + return; + + control = le16_to_cpu(prof->control); + link_id = control & IEEE80211_MLE_STA_RECONF_CONTROL_LINK_ID; + + removed_links |= BIT(link_id); + + /* the MAC address should not be included, but handle it */ + if (control & + IEEE80211_MLE_STA_RECONF_CONTROL_STA_MAC_ADDR_PRESENT) + pos += 6; + + /* According to Draft P802.11be_D3.0, the control should + * include the AP Removal Timer present. If the AP Removal Timer + * is not present assume immediate removal. + */ + if (control & + IEEE80211_MLE_STA_RECONF_CONTROL_AP_REM_TIMER_PRESENT) + link_removal_timeout[link_id] = le16_to_cpu(*(__le16 *)pos); + } + + removed_links &= sdata->vif.valid_links; + if (!removed_links) { + /* In case the removal was cancelled, abort it */ + if (sdata->u.mgd.removed_links) { + sdata->u.mgd.removed_links = 0; + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, + &sdata->u.mgd.ml_reconf_work); + } + return; + } + + delay = 0; + for_each_set_bit(link_id, &removed_links, IEEE80211_MLD_MAX_NUM_LINKS) { + struct ieee80211_bss_conf *link_conf = + sdata_dereference(sdata->vif.link_conf[link_id], sdata); + u32 link_delay; + + if (!link_conf) { + removed_links &= ~BIT(link_id); + continue; + } + + link_delay = link_conf->beacon_int * + link_removal_timeout[link_id]; + + if (!delay) + delay = link_delay; + else + delay = min(delay, link_delay); + } + + sdata->u.mgd.removed_links = removed_links; + wiphy_delayed_work_queue(sdata->local->hw.wiphy, + &sdata->u.mgd.ml_reconf_work, + TU_TO_JIFFIES(delay)); +} + +static void ieee80211_tid_to_link_map_work(struct wiphy *wiphy, + struct wiphy_work *work) +{ + u16 new_active_links, new_dormant_links; + struct ieee80211_sub_if_data *sdata = + container_of(work, struct ieee80211_sub_if_data, + u.mgd.ttlm_work.work); + int ret; + + new_active_links = sdata->u.mgd.ttlm_info.map & + sdata->vif.valid_links; + new_dormant_links = ~sdata->u.mgd.ttlm_info.map & + sdata->vif.valid_links; + if (!new_active_links) { + ieee80211_disconnect(&sdata->vif, false); + return; + } + + ieee80211_vif_set_links(sdata, sdata->vif.valid_links, 0); + new_active_links = BIT(ffs(new_active_links) - 1); + ieee80211_set_active_links(&sdata->vif, new_active_links); + + ret = ieee80211_vif_set_links(sdata, sdata->vif.valid_links, + new_dormant_links); + + sdata->u.mgd.ttlm_info.active = true; + sdata->u.mgd.ttlm_info.switch_time = 0; + + if (!ret) + ieee80211_vif_cfg_change_notify(sdata, + BSS_CHANGED_MLD_VALID_LINKS); +} + +static u16 ieee80211_get_ttlm(u8 bm_size, u8 *data) +{ + if (bm_size == 1) + return *data; + else + return get_unaligned_le16(data); +} + +static int +ieee80211_parse_adv_t2l(struct ieee80211_sub_if_data *sdata, + const struct ieee80211_ttlm_elem *ttlm, + struct ieee80211_adv_ttlm_info *ttlm_info) +{ + /* The element size was already validated in + * ieee80211_tid_to_link_map_size_ok() + */ + u8 control, link_map_presence, map_size, tid; + u8 *pos; + + memset(ttlm_info, 0, sizeof(*ttlm_info)); + pos = (void *)ttlm->optional; + control = ttlm->control; + + if ((control & IEEE80211_TTLM_CONTROL_DEF_LINK_MAP) || + !(control & IEEE80211_TTLM_CONTROL_SWITCH_TIME_PRESENT)) + return 0; + + if ((control & IEEE80211_TTLM_CONTROL_DIRECTION) != + IEEE80211_TTLM_DIRECTION_BOTH) { + sdata_info(sdata, "Invalid advertised T2L map direction\n"); + return -EINVAL; + } + + link_map_presence = *pos; + pos++; + + ttlm_info->switch_time = get_unaligned_le16(pos); + pos += 2; + + if (control & IEEE80211_TTLM_CONTROL_EXPECTED_DUR_PRESENT) { + ttlm_info->duration = pos[0] | pos[1] << 8 | pos[2] << 16; + pos += 3; + } + + if (control & IEEE80211_TTLM_CONTROL_LINK_MAP_SIZE) + map_size = 1; + else + map_size = 2; + + /* According to Draft P802.11be_D3.0 clause 35.3.7.1.7, an AP MLD shall + * not advertise a TID-to-link mapping that does not map all TIDs to the + * same link set, reject frame if not all links have mapping + */ + if (link_map_presence != 0xff) { + sdata_info(sdata, + "Invalid advertised T2L mapping presence indicator\n"); + return -EINVAL; + } + + ttlm_info->map = ieee80211_get_ttlm(map_size, pos); + if (!ttlm_info->map) { + sdata_info(sdata, + "Invalid advertised T2L map for TID 0\n"); + return -EINVAL; + } + + pos += map_size; + + for (tid = 1; tid < 8; tid++) { + u16 map = ieee80211_get_ttlm(map_size, pos); + + if (map != ttlm_info->map) { + sdata_info(sdata, "Invalid advertised T2L map for tid %d\n", + tid); + return -EINVAL; + } + + pos += map_size; + } + return 0; +} + +static void ieee80211_process_adv_ttlm(struct ieee80211_sub_if_data *sdata, + struct ieee802_11_elems *elems, + u64 beacon_ts) +{ + u8 i; + int ret; + + if (!ieee80211_vif_is_mld(&sdata->vif)) + return; + + if (!elems->ttlm_num) { + if (sdata->u.mgd.ttlm_info.switch_time) { + /* if a planned TID-to-link mapping was cancelled - + * abort it + */ + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, + &sdata->u.mgd.ttlm_work); + } else if (sdata->u.mgd.ttlm_info.active) { + /* if no TID-to-link element, set to default mapping in + * which all TIDs are mapped to all setup links + */ + ret = ieee80211_vif_set_links(sdata, + sdata->vif.valid_links, + 0); + if (ret) { + sdata_info(sdata, "Failed setting valid/dormant links\n"); + return; + } + ieee80211_vif_cfg_change_notify(sdata, + BSS_CHANGED_MLD_VALID_LINKS); + } + memset(&sdata->u.mgd.ttlm_info, 0, + sizeof(sdata->u.mgd.ttlm_info)); + return; + } + + for (i = 0; i < elems->ttlm_num; i++) { + struct ieee80211_adv_ttlm_info ttlm_info; + u32 res; + + res = ieee80211_parse_adv_t2l(sdata, elems->ttlm[i], + &ttlm_info); + + if (res) { + __ieee80211_disconnect(sdata); + return; + } + + if (ttlm_info.switch_time) { + u32 st_us, delay = 0; + u32 ts_l26 = beacon_ts & GENMASK(25, 0); + + /* The t2l map switch time is indicated with a partial + * TSF value, convert it to TSF and calc the delay + * to the start time. + */ + st_us = ieee80211_tu_to_usec(ttlm_info.switch_time); + if (st_us > ts_l26) + delay = st_us - ts_l26; + else + continue; + + sdata->u.mgd.ttlm_info = ttlm_info; + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, + &sdata->u.mgd.ttlm_work); + wiphy_delayed_work_queue(sdata->local->hw.wiphy, + &sdata->u.mgd.ttlm_work, + usecs_to_jiffies(delay)); + return; + } + } +} + static void ieee80211_rx_mgmt_beacon(struct ieee80211_link_data *link, struct ieee80211_hdr *hdr, size_t len, struct ieee80211_rx_status *rx_status) @@ -5626,7 +6090,7 @@ .from_ap = true, }; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(local->hw.wiphy); /* Process beacon from the current BSS */ bssid = ieee80211_get_bssid(hdr, len, sdata->vif.type); @@ -5662,7 +6126,7 @@ rcu_read_unlock(); if (ifmgd->assoc_data && ifmgd->assoc_data->need_beacon && - !WARN_ON(sdata->vif.valid_links) && + !WARN_ON(ieee80211_vif_is_mld(&sdata->vif)) && ieee80211_rx_our_beacon(bssid, ifmgd->assoc_data->link[0].bss)) { parse_params.bss = ifmgd->assoc_data->link[0].bss; elems = ieee802_11_parse_elems_full(&parse_params); @@ -5842,9 +6306,7 @@ changed |= BSS_CHANGED_BEACON_INFO; link->u.mgd.have_beacon = true; - mutex_lock(&local->iflist_mtx); ieee80211_recalc_ps(local); - mutex_unlock(&local->iflist_mtx); ieee80211_recalc_ps_vif(sdata); } @@ -5861,16 +6323,13 @@ le16_to_cpu(mgmt->u.beacon.capab_info), erp_valid, erp_value); - mutex_lock(&local->sta_mtx); sta = sta_info_get(sdata, sdata->vif.cfg.ap_addr); if (WARN_ON(!sta)) { - mutex_unlock(&local->sta_mtx); goto free; } link_sta = rcu_dereference_protected(sta->link[link->link_id], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (WARN_ON(!link_sta)) { - mutex_unlock(&local->sta_mtx); goto free; } @@ -5886,7 +6345,6 @@ elems->vht_operation, elems->he_operation, elems->eht_operation, elems->s1g_oper, bssid, &changed)) { - mutex_unlock(&local->sta_mtx); sdata_info(sdata, "failed to follow AP %pM bandwidth change, disconnect\n", bssid); @@ -5904,7 +6362,6 @@ ieee80211_vht_handle_opmode(sdata, link_sta, *elems->opmode_notif, rx_status->band); - mutex_unlock(&local->sta_mtx); changed |= ieee80211_handle_pwr_constr(link, chan, mgmt, elems->country_elem, @@ -5927,6 +6384,10 @@ } } + ieee80211_ml_reconfiguration(sdata, elems); + ieee80211_process_adv_ttlm(sdata, elems, + le64_to_cpu(mgmt->u.beacon.timestamp)); + ieee80211_link_info_change_notify(sdata, link, changed); free: kfree(elems); @@ -5940,17 +6401,17 @@ struct ieee80211_hdr *hdr; u16 fc; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + rx_status = (struct ieee80211_rx_status *) skb->cb; hdr = (struct ieee80211_hdr *) skb->data; fc = le16_to_cpu(hdr->frame_control); - sdata_lock(sdata); switch (fc & IEEE80211_FCTL_STYPE) { case IEEE80211_STYPE_S1G_BEACON: ieee80211_rx_mgmt_beacon(link, hdr, skb->len, rx_status); break; } - sdata_unlock(sdata); } void ieee80211_sta_rx_queued_mgmt(struct ieee80211_sub_if_data *sdata, @@ -5962,17 +6423,17 @@ u16 fc; int ies_len; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + rx_status = (struct ieee80211_rx_status *) skb->cb; mgmt = (struct ieee80211_mgmt *) skb->data; fc = le16_to_cpu(mgmt->frame_control); - sdata_lock(sdata); - if (rx_status->link_valid) { link = sdata_dereference(sdata->link[rx_status->link_id], sdata); if (!link) - goto out; + return; } switch (fc & IEEE80211_FCTL_STYPE) { @@ -5997,6 +6458,10 @@ ieee80211_rx_mgmt_assoc_resp(sdata, mgmt, skb->len); break; case IEEE80211_STYPE_ACTION: + if (!sdata->u.mgd.associated || + !ether_addr_equal(mgmt->bssid, sdata->vif.cfg.ap_addr)) + break; + if (mgmt->u.action.category == WLAN_CATEGORY_SPECTRUM_MGMT) { struct ieee802_11_elems *elems; @@ -6051,8 +6516,6 @@ } break; } -out: - sdata_unlock(sdata); } static void ieee80211_sta_timer(struct timer_list *t) @@ -6060,7 +6523,7 @@ struct ieee80211_sub_if_data *sdata = from_timer(sdata, t, u.mgd.timer); - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } void ieee80211_sta_connection_lost(struct ieee80211_sub_if_data *sdata, @@ -6087,7 +6550,7 @@ .subtype = IEEE80211_STYPE_AUTH, }; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (WARN_ON_ONCE(!auth_data)) return -EINVAL; @@ -6110,6 +6573,7 @@ if (auth_data->algorithm == WLAN_AUTH_SAE) info.duration = jiffies_to_msecs(IEEE80211_AUTH_TIMEOUT_SAE); + info.link_id = auth_data->link_id; drv_mgd_prepare_tx(local, sdata, &info); sdata_info(sdata, "send auth to %pM (try %d/%d)\n", @@ -6156,7 +6620,7 @@ struct ieee80211_local *local = sdata->local; int ret; - sdata_assert_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); assoc_data->tries++; if (assoc_data->tries > IEEE80211_ASSOC_MAX_TRIES) { @@ -6204,7 +6668,7 @@ sdata->u.mgd.status_acked = acked; sdata->u.mgd.status_received = true; - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); } void ieee80211_sta_work(struct ieee80211_sub_if_data *sdata) @@ -6212,7 +6676,7 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - sdata_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (ifmgd->status_received) { __le16 fc = ifmgd->status_fc; @@ -6347,8 +6811,6 @@ WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY, false); } } - - sdata_unlock(sdata); } static void ieee80211_sta_bcn_mon_timer(struct timer_list *t) @@ -6356,7 +6818,7 @@ struct ieee80211_sub_if_data *sdata = from_timer(sdata, t, u.mgd.bcn_mon_timer); - if (WARN_ON(sdata->vif.valid_links)) + if (WARN_ON(ieee80211_vif_is_mld(&sdata->vif))) return; if (sdata->vif.bss_conf.csa_active && @@ -6367,7 +6829,7 @@ return; sdata->u.mgd.connection_loss = false; - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->u.mgd.beacon_connection_loss_work); } @@ -6380,7 +6842,7 @@ struct sta_info *sta; unsigned long timeout; - if (WARN_ON(sdata->vif.valid_links)) + if (WARN_ON(ieee80211_vif_is_mld(&sdata->vif))) return; if (sdata->vif.bss_conf.csa_active && @@ -6404,10 +6866,11 @@ return; } - ieee80211_queue_work(&local->hw, &ifmgd->monitor_work); + wiphy_work_queue(local->hw.wiphy, &sdata->u.mgd.monitor_work); } -static void ieee80211_sta_monitor_work(struct work_struct *work) +static void ieee80211_sta_monitor_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_sub_if_data *sdata = container_of(work, struct ieee80211_sub_if_data, @@ -6423,7 +6886,7 @@ /* let's probe the connection once */ if (!ieee80211_hw_check(&sdata->local->hw, CONNECTION_MONITOR)) - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->u.mgd.monitor_work); } } @@ -6434,7 +6897,7 @@ struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; u8 frame_buf[IEEE80211_DEAUTH_FRAME_LEN]; - sdata_lock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); if (ifmgd->auth_data || ifmgd->assoc_data) { const u8 *ap_addr = ifmgd->auth_data ? @@ -6486,8 +6949,6 @@ memcpy(bssid, sdata->vif.cfg.ap_addr, ETH_ALEN); ieee80211_mgd_deauth(sdata, &req); } - - sdata_unlock(sdata); } #endif @@ -6495,11 +6956,10 @@ { struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - sdata_lock(sdata); - if (!ifmgd->associated) { - sdata_unlock(sdata); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + + if (!ifmgd->associated) return; - } if (sdata->flags & IEEE80211_SDATA_DISCONNECT_RESUME) { sdata->flags &= ~IEEE80211_SDATA_DISCONNECT_RESUME; @@ -6507,7 +6967,6 @@ ieee80211_sta_connection_lost(sdata, WLAN_REASON_UNSPECIFIED, true); - sdata_unlock(sdata); return; } @@ -6517,23 +6976,19 @@ ieee80211_sta_connection_lost(sdata, WLAN_REASON_UNSPECIFIED, true); - sdata_unlock(sdata); return; } - - sdata_unlock(sdata); } -static void ieee80211_request_smps_mgd_work(struct work_struct *work) +static void ieee80211_request_smps_mgd_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_link_data *link = container_of(work, struct ieee80211_link_data, u.mgd.request_smps_work); - sdata_lock(link->sdata); __ieee80211_request_smps_mgd(link->sdata, link, link->u.mgd.driver_smps_mode); - sdata_unlock(link->sdata); } /* interface setup */ @@ -6541,18 +6996,22 @@ { struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; - INIT_WORK(&ifmgd->monitor_work, ieee80211_sta_monitor_work); - INIT_WORK(&ifmgd->beacon_connection_loss_work, + wiphy_work_init(&ifmgd->monitor_work, ieee80211_sta_monitor_work); + wiphy_work_init(&ifmgd->beacon_connection_loss_work, ieee80211_beacon_connection_loss_work); - INIT_WORK(&ifmgd->csa_connection_drop_work, + wiphy_work_init(&ifmgd->csa_connection_drop_work, ieee80211_csa_connection_drop_work); - INIT_DELAYED_WORK(&ifmgd->tdls_peer_del_work, + wiphy_delayed_work_init(&ifmgd->tdls_peer_del_work, ieee80211_tdls_peer_del_work); + wiphy_delayed_work_init(&ifmgd->ml_reconf_work, + ieee80211_ml_reconf_work); timer_setup(&ifmgd->timer, ieee80211_sta_timer, 0); timer_setup(&ifmgd->bcn_mon_timer, ieee80211_sta_bcn_mon_timer, 0); timer_setup(&ifmgd->conn_mon_timer, ieee80211_sta_conn_mon_timer, 0); - INIT_DELAYED_WORK(&ifmgd->tx_tspec_wk, + wiphy_delayed_work_init(&ifmgd->tx_tspec_wk, ieee80211_sta_handle_tspec_ac_params_wk); + wiphy_delayed_work_init(&ifmgd->ttlm_work, + ieee80211_tid_to_link_map_work); ifmgd->flags = 0; ifmgd->powersave = sdata->wdev.ps; @@ -6564,6 +7023,16 @@ ifmgd->orig_teardown_skb = NULL; } +static void ieee80211_recalc_smps_work(struct wiphy *wiphy, + struct wiphy_work *work) +{ + struct ieee80211_link_data *link = + container_of(work, struct ieee80211_link_data, + u.mgd.recalc_smps); + + ieee80211_recalc_smps(link->sdata, link); +} + void ieee80211_mgd_setup_link(struct ieee80211_link_data *link) { struct ieee80211_sub_if_data *sdata = link->sdata; @@ -6574,15 +7043,17 @@ link->u.mgd.conn_flags = 0; link->conf->bssid = link->u.mgd.bssid; - INIT_WORK(&link->u.mgd.request_smps_work, + wiphy_work_init(&link->u.mgd.request_smps_work, ieee80211_request_smps_mgd_work); + wiphy_work_init(&link->u.mgd.recalc_smps, + ieee80211_recalc_smps_work); if (local->hw.wiphy->features & NL80211_FEATURE_DYNAMIC_SMPS) link->u.mgd.req_smps = IEEE80211_SMPS_AUTOMATIC; else link->u.mgd.req_smps = IEEE80211_SMPS_OFF; - INIT_WORK(&link->u.mgd.chswitch_work, ieee80211_chswitch_work); - timer_setup(&link->u.mgd.chswitch_timer, ieee80211_chswitch_timer, 0); + wiphy_delayed_work_init(&link->u.mgd.chswitch_work, + ieee80211_chswitch_work); if (sdata->u.mgd.assoc_data) ether_addr_copy(link->conf->addr, @@ -6623,12 +7094,12 @@ mlo = true; if (WARN_ON(!ap_mld_addr)) return -EINVAL; - err = ieee80211_vif_set_links(sdata, BIT(link_id)); + err = ieee80211_vif_set_links(sdata, BIT(link_id), 0); } else { if (WARN_ON(ap_mld_addr)) return -EINVAL; ap_mld_addr = cbss->bssid; - err = ieee80211_vif_set_links(sdata, 0); + err = ieee80211_vif_set_links(sdata, 0, 0); link_id = 0; mlo = false; } @@ -6739,7 +7210,7 @@ } if (new_sta || override) { - err = ieee80211_prep_channel(sdata, link, cbss, + err = ieee80211_prep_channel(sdata, link, cbss, mlo, &link->u.mgd.conn_flags); if (err) { if (new_sta) @@ -6780,7 +7251,7 @@ out_err: ieee80211_link_release_channel(&sdata->deflink); - ieee80211_vif_set_links(sdata, 0); + ieee80211_vif_set_links(sdata, 0, 0); return err; } @@ -6791,10 +7262,14 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; struct ieee80211_mgd_auth_data *auth_data; + struct ieee80211_link_data *link; + const struct element *csa_elem, *ecsa_elem; u16 auth_alg; int err; bool cont_auth; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + /* prepare auth data structure */ switch (req->auth_type) { @@ -6831,6 +7306,22 @@ if (ifmgd->assoc_data) return -EBUSY; + rcu_read_lock(); + csa_elem = ieee80211_bss_get_elem(req->bss, WLAN_EID_CHANNEL_SWITCH); + ecsa_elem = ieee80211_bss_get_elem(req->bss, + WLAN_EID_EXT_CHANSWITCH_ANN); + if ((csa_elem && + csa_elem->datalen == sizeof(struct ieee80211_channel_sw_ie) && + ((struct ieee80211_channel_sw_ie *)csa_elem->data)->count != 0) || + (ecsa_elem && + ecsa_elem->datalen == sizeof(struct ieee80211_ext_chansw_ie) && + ((struct ieee80211_ext_chansw_ie *)ecsa_elem->data)->count != 0)) { + rcu_read_unlock(); + sdata_info(sdata, "AP is in CSA process, reject auth\n"); + return -EINVAL; + } + rcu_read_unlock(); + auth_data = kzalloc(sizeof(*auth_data) + req->auth_data_len + req->ie_len, GFP_KERNEL); if (!auth_data) @@ -6914,8 +7405,6 @@ false); } - sdata_info(sdata, "authenticate with %pM\n", auth_data->ap_addr); - /* needed for transmitting the auth frame(s) properly */ memcpy(sdata->vif.cfg.ap_addr, auth_data->ap_addr, ETH_ALEN); @@ -6924,6 +7413,19 @@ if (err) goto err_clear; + if (req->link_id > 0) + link = sdata_dereference(sdata->link[req->link_id], sdata); + else + link = sdata_dereference(sdata->link[0], sdata); + + if (WARN_ON(!link)) { + err = -ENOLINK; + goto err_clear; + } + + sdata_info(sdata, "authenticate with %pM (local address=%pM)\n", + auth_data->ap_addr, link->conf->addr); + err = ieee80211_auth(sdata); if (err) { sta_info_destroy_addr(sdata, auth_data->ap_addr); @@ -6935,13 +7437,11 @@ return 0; err_clear: - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { eth_zero_addr(sdata->deflink.u.mgd.bssid); ieee80211_link_info_change_notify(sdata, &sdata->deflink, BSS_CHANGED_BSSID); - mutex_lock(&sdata->local->mtx); ieee80211_link_release_channel(&sdata->deflink); - mutex_unlock(&sdata->local->mtx); } ifmgd->auth_data = NULL; kfree(auth_data); @@ -6956,7 +7456,7 @@ unsigned int link_id) { struct ieee80211_local *local = sdata->local; - const struct cfg80211_bss_ies *beacon_ies; + const struct cfg80211_bss_ies *bss_ies; struct ieee80211_supported_band *sband; const struct element *ht_elem, *vht_elem; struct ieee80211_link_data *link; @@ -7031,32 +7531,37 @@ link->conf->eht_puncturing = 0; rcu_read_lock(); - beacon_ies = rcu_dereference(cbss->beacon_ies); - if (beacon_ies) { - const struct ieee80211_eht_operation *eht_oper; - const struct element *elem; + bss_ies = rcu_dereference(cbss->beacon_ies); + if (bss_ies) { u8 dtim_count = 0; - ieee80211_get_dtim(beacon_ies, &dtim_count, + ieee80211_get_dtim(bss_ies, &dtim_count, &link->u.mgd.dtim_period); sdata->deflink.u.mgd.have_beacon = true; if (ieee80211_hw_check(&local->hw, TIMING_BEACON_ONLY)) { - link->conf->sync_tsf = beacon_ies->tsf; + link->conf->sync_tsf = bss_ies->tsf; link->conf->sync_device_ts = bss->device_ts_beacon; link->conf->sync_dtim_count = dtim_count; } + } else { + bss_ies = rcu_dereference(cbss->ies); + } + + if (bss_ies) { + const struct ieee80211_eht_operation *eht_oper; + const struct element *elem; elem = cfg80211_find_ext_elem(WLAN_EID_EXT_MULTIPLE_BSSID_CONFIGURATION, - beacon_ies->data, beacon_ies->len); + bss_ies->data, bss_ies->len); if (elem && elem->datalen >= 3) link->conf->profile_periodicity = elem->data[2]; else link->conf->profile_periodicity = 0; elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, - beacon_ies->data, beacon_ies->len); + bss_ies->data, bss_ies->len); if (elem && elem->datalen >= 11 && (elem->data[10] & WLAN_EXT_CAPA11_EMA_SUPPORT)) link->conf->ema_ap = true; @@ -7064,7 +7569,7 @@ link->conf->ema_ap = false; elem = cfg80211_find_ext_elem(WLAN_EID_EXT_EHT_OPERATION, - beacon_ies->data, beacon_ies->len); + bss_ies->data, bss_ies->len); eht_oper = (const void *)(elem->data + 1); if (elem && @@ -7124,7 +7629,7 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; struct ieee80211_mgd_assoc_data *assoc_data; - const struct element *ssid_elem; + const struct element *ssid_elem, *csa_elem, *ecsa_elem; struct ieee80211_vif_cfg *vif_cfg = &sdata->vif.cfg; ieee80211_conn_flags_t conn_flags = 0; struct ieee80211_link_data *link; @@ -7154,6 +7659,21 @@ kfree(assoc_data); return -EINVAL; } + + csa_elem = ieee80211_bss_get_elem(cbss, WLAN_EID_CHANNEL_SWITCH); + ecsa_elem = ieee80211_bss_get_elem(cbss, WLAN_EID_EXT_CHANSWITCH_ANN); + if ((csa_elem && + csa_elem->datalen == sizeof(struct ieee80211_channel_sw_ie) && + ((struct ieee80211_channel_sw_ie *)csa_elem->data)->count != 0) || + (ecsa_elem && + ecsa_elem->datalen == sizeof(struct ieee80211_ext_chansw_ie) && + ((struct ieee80211_ext_chansw_ie *)ecsa_elem->data)->count != 0)) { + sdata_info(sdata, "AP is in CSA process, reject assoc\n"); + rcu_read_unlock(); + kfree(assoc_data); + return -EINVAL; + } + memcpy(assoc_data->ssid, ssid_elem->data, ssid_elem->datalen); assoc_data->ssid_len = ssid_elem->datalen; memcpy(vif_cfg->ssid, assoc_data->ssid, assoc_data->ssid_len); @@ -7214,7 +7734,10 @@ match = ether_addr_equal(ifmgd->auth_data->ap_addr, assoc_data->ap_addr) && ifmgd->auth_data->link_id == req->link_id; - ieee80211_destroy_auth_data(sdata, match); + + /* Cleanup is delayed if auth_data matches */ + if (!match) + ieee80211_destroy_auth_data(sdata, false); } /* prepare assoc data */ @@ -7320,10 +7843,11 @@ for (i = 0; i < ARRAY_SIZE(assoc_data->link); i++) { assoc_data->link[i].conn_flags = conn_flags; assoc_data->link[i].bss = req->links[i].bss; + assoc_data->link[i].disabled = req->links[i].disabled; } /* if there was no authentication, set up the link */ - err = ieee80211_vif_set_links(sdata, BIT(assoc_link_id)); + err = ieee80211_vif_set_links(sdata, BIT(assoc_link_id), 0); if (err) goto err_clear; } else { @@ -7394,11 +7918,14 @@ if (i == assoc_data->assoc_link_id) continue; /* only calculate the flags, hence link == NULL */ - err = ieee80211_prep_channel(sdata, NULL, assoc_data->link[i].bss, + err = ieee80211_prep_channel(sdata, NULL, + assoc_data->link[i].bss, true, &assoc_data->link[i].conn_flags); - if (err) + if (err) { + req->links[i].error = err; goto err_clear; } + } /* needed for transmitting the assoc frames properly */ memcpy(sdata->vif.cfg.ap_addr, assoc_data->ap_addr, ETH_ALEN); @@ -7433,11 +7960,17 @@ run_again(sdata, assoc_data->timeout); + /* We are associating, clean up auth_data */ + if (ifmgd->auth_data) + ieee80211_destroy_auth_data(sdata, true); + return 0; err_clear: + if (!ifmgd->auth_data) { eth_zero_addr(sdata->deflink.u.mgd.bssid); ieee80211_link_info_change_notify(sdata, &sdata->deflink, BSS_CHANGED_BSSID); + } ifmgd->assoc_data = NULL; err_free: kfree(assoc_data); @@ -7461,6 +7994,7 @@ req->bssid, req->reason_code, ieee80211_get_reason_code_string(req->reason_code)); + info.link_id = ifmgd->auth_data->link_id; drv_mgd_prepare_tx(sdata->local, sdata, &info); ieee80211_send_deauth_disassoc(sdata, req->bssid, req->bssid, IEEE80211_STYPE_DEAUTH, @@ -7481,6 +8015,7 @@ req->bssid, req->reason_code, ieee80211_get_reason_code_string(req->reason_code)); + info.link_id = ifmgd->assoc_data->assoc_link_id; drv_mgd_prepare_tx(sdata->local, sdata, &info); ieee80211_send_deauth_disassoc(sdata, req->bssid, req->bssid, IEEE80211_STYPE_DEAUTH, @@ -7538,8 +8073,12 @@ void ieee80211_mgd_stop_link(struct ieee80211_link_data *link) { - cancel_work_sync(&link->u.mgd.request_smps_work); - cancel_work_sync(&link->u.mgd.chswitch_work); + wiphy_work_cancel(link->sdata->local->hw.wiphy, + &link->u.mgd.request_smps_work); + wiphy_work_cancel(link->sdata->local->hw.wiphy, + &link->u.mgd.recalc_smps); + wiphy_delayed_work_cancel(link->sdata->local->hw.wiphy, + &link->u.mgd.chswitch_work); } void ieee80211_mgd_stop(struct ieee80211_sub_if_data *sdata) @@ -7551,12 +8090,18 @@ * they will not do anything but might not have been * cancelled when disconnecting. */ - cancel_work_sync(&ifmgd->monitor_work); - cancel_work_sync(&ifmgd->beacon_connection_loss_work); - cancel_work_sync(&ifmgd->csa_connection_drop_work); - cancel_delayed_work_sync(&ifmgd->tdls_peer_del_work); + wiphy_work_cancel(sdata->local->hw.wiphy, + &ifmgd->monitor_work); + wiphy_work_cancel(sdata->local->hw.wiphy, + &ifmgd->beacon_connection_loss_work); + wiphy_work_cancel(sdata->local->hw.wiphy, + &ifmgd->csa_connection_drop_work); + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, + &ifmgd->tdls_peer_del_work); + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, + &ifmgd->ml_reconf_work); + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, &ifmgd->ttlm_work); - sdata_lock(sdata); if (ifmgd->assoc_data) ieee80211_destroy_assoc_data(sdata, ASSOC_TIMEOUT); if (ifmgd->auth_data) @@ -7572,7 +8117,6 @@ ifmgd->assoc_req_ies_len = 0; spin_unlock_bh(&ifmgd->teardown_lock); del_timer_sync(&ifmgd->timer); - sdata_unlock(sdata); } void ieee80211_cqm_rssi_notify(struct ieee80211_vif *vif, diff -ruw linux-6.4/net/mac80211/ocb.c linux-6.4-fbx/net/mac80211/ocb.c --- linux-6.4/net/mac80211/ocb.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/ocb.c 2023-11-07 13:38:44.086257347 +0100 @@ -4,7 +4,7 @@ * * Copyright: (c) 2014 Czech Technical University in Prague * (c) 2014 Volkswagen Group Research - * Copyright (C) 2022 Intel Corporation + * Copyright (C) 2022 - 2023 Intel Corporation * Author: Rostislav Lisovy * Funded by: Volkswagen Group Research */ @@ -44,7 +44,6 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_chanctx_conf *chanctx_conf; struct ieee80211_supported_band *sband; - enum nl80211_bss_scan_width scan_width; struct sta_info *sta; int band; @@ -66,7 +65,6 @@ return; } band = chanctx_conf->def.chan->band; - scan_width = cfg80211_chandef_to_scan_width(&chanctx_conf->def); rcu_read_unlock(); sta = sta_info_alloc(sdata, addr, GFP_ATOMIC); @@ -75,13 +73,12 @@ /* Add only mandatory rates for now */ sband = local->hw.wiphy->bands[band]; - sta->sta.deflink.supp_rates[band] = - ieee80211_mandatory_rates(sband, scan_width); + sta->sta.deflink.supp_rates[band] = ieee80211_mandatory_rates(sband); spin_lock(&ifocb->incomplete_lock); list_add(&sta->list, &ifocb->incomplete_stations); spin_unlock(&ifocb->incomplete_lock); - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); } static struct sta_info *ieee80211_ocb_finish_sta(struct sta_info *sta) @@ -124,11 +121,11 @@ struct ieee80211_if_ocb *ifocb = &sdata->u.ocb; struct sta_info *sta; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + if (ifocb->joined != true) return; - sdata_lock(sdata); - spin_lock_bh(&ifocb->incomplete_lock); while (!list_empty(&ifocb->incomplete_stations)) { sta = list_first_entry(&ifocb->incomplete_stations, @@ -144,8 +141,6 @@ if (test_and_clear_bit(OCB_WORK_HOUSEKEEPING, &ifocb->wrkq_flags)) ieee80211_ocb_housekeeping(sdata); - - sdata_unlock(sdata); } static void ieee80211_ocb_housekeeping_timer(struct timer_list *t) @@ -157,7 +152,7 @@ set_bit(OCB_WORK_HOUSEKEEPING, &ifocb->wrkq_flags); - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); } void ieee80211_ocb_setup_sdata(struct ieee80211_sub_if_data *sdata) @@ -175,9 +170,11 @@ { struct ieee80211_local *local = sdata->local; struct ieee80211_if_ocb *ifocb = &sdata->u.ocb; - u32 changed = BSS_CHANGED_OCB | BSS_CHANGED_BSSID; + u64 changed = BSS_CHANGED_OCB | BSS_CHANGED_BSSID; int err; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + if (ifocb->joined == true) return -EINVAL; @@ -185,10 +182,8 @@ sdata->deflink.smps_mode = IEEE80211_SMPS_OFF; sdata->deflink.needed_rx_chains = sdata->local->rx_chains; - mutex_lock(&sdata->local->mtx); err = ieee80211_link_use_channel(&sdata->deflink, &setup->chandef, IEEE80211_CHANCTX_SHARED); - mutex_unlock(&sdata->local->mtx); if (err) return err; @@ -197,7 +192,7 @@ ifocb->joined = true; set_bit(OCB_WORK_HOUSEKEEPING, &ifocb->wrkq_flags); - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); netif_carrier_on(sdata->dev); return 0; @@ -209,6 +204,8 @@ struct ieee80211_local *local = sdata->local; struct sta_info *sta; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + ifocb->joined = false; sta_info_flush(sdata); @@ -228,9 +225,7 @@ clear_bit(SDATA_STATE_OFFCHANNEL, &sdata->state); ieee80211_bss_info_change_notify(sdata, BSS_CHANGED_OCB); - mutex_lock(&sdata->local->mtx); ieee80211_link_release_channel(&sdata->deflink); - mutex_unlock(&sdata->local->mtx); skb_queue_purge(&sdata->skb_queue); diff -ruw linux-6.4/net/mac80211/offchannel.c linux-6.4-fbx/net/mac80211/offchannel.c --- linux-6.4/net/mac80211/offchannel.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/offchannel.c 2023-11-07 13:38:44.086257347 +0100 @@ -8,7 +8,7 @@ * Copyright 2006-2007 Jiri Benc * Copyright 2007, Michael Wu * Copyright 2009 Johannes Berg - * Copyright (C) 2019, 2022 Intel Corporation + * Copyright (C) 2019, 2022-2023 Intel Corporation */ #include #include @@ -34,7 +34,7 @@ del_timer_sync(&ifmgd->bcn_mon_timer); del_timer_sync(&ifmgd->conn_mon_timer); - cancel_work_sync(&local->dynamic_ps_enable_work); + wiphy_work_cancel(local->hw.wiphy, &local->dynamic_ps_enable_work); if (local->hw.conf.flags & IEEE80211_CONF_PS) { offchannel_ps_enabled = true; @@ -84,6 +84,8 @@ { struct ieee80211_sub_if_data *sdata; + lockdep_assert_wiphy(local->hw.wiphy); + if (WARN_ON(local->use_chanctx)) return; @@ -101,7 +103,6 @@ false); ieee80211_flush_queues(local, NULL, false); - mutex_lock(&local->iflist_mtx); list_for_each_entry(sdata, &local->interfaces, list) { if (!ieee80211_sdata_running(sdata)) continue; @@ -127,17 +128,17 @@ sdata->u.mgd.associated) ieee80211_offchannel_ps_enable(sdata); } - mutex_unlock(&local->iflist_mtx); } void ieee80211_offchannel_return(struct ieee80211_local *local) { struct ieee80211_sub_if_data *sdata; + lockdep_assert_wiphy(local->hw.wiphy); + if (WARN_ON(local->use_chanctx)) return; - mutex_lock(&local->iflist_mtx); list_for_each_entry(sdata, &local->interfaces, list) { if (sdata->vif.type == NL80211_IFTYPE_P2P_DEVICE) continue; @@ -161,7 +162,6 @@ BSS_CHANGED_BEACON_ENABLED); } } - mutex_unlock(&local->iflist_mtx); ieee80211_wake_queues_by_reason(&local->hw, IEEE80211_MAX_QUEUE_MAP, IEEE80211_QUEUE_STOP_REASON_OFFCHANNEL, @@ -197,7 +197,7 @@ struct ieee80211_roc_work *roc, *tmp; long remaining_dur_min = LONG_MAX; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry_safe(roc, tmp, &local->roc_list, list) { long remaining; @@ -230,7 +230,7 @@ if (dur == LONG_MAX) return false; - mod_delayed_work(local->workqueue, &local->roc_work, dur); + wiphy_delayed_work_queue(local->hw.wiphy, &local->roc_work, dur); return true; } @@ -258,13 +258,13 @@ roc->notified = true; } -static void ieee80211_hw_roc_start(struct work_struct *work) +static void ieee80211_hw_roc_start(struct wiphy *wiphy, struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, hw_roc_start); struct ieee80211_roc_work *roc; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(roc, &local->roc_list, list) { if (!roc->started) @@ -273,8 +273,6 @@ roc->hw_begun = true; ieee80211_handle_roc_started(roc, local->hw_roc_start_time); } - - mutex_unlock(&local->mtx); } void ieee80211_ready_on_channel(struct ieee80211_hw *hw) @@ -285,7 +283,7 @@ trace_api_ready_on_channel(local); - ieee80211_queue_work(hw, &local->hw_roc_start); + wiphy_work_queue(hw->wiphy, &local->hw_roc_start); } EXPORT_SYMBOL_GPL(ieee80211_ready_on_channel); @@ -295,7 +293,7 @@ enum ieee80211_roc_type type; u32 min_dur, max_dur; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(list_empty(&local->roc_list))) return; @@ -338,7 +336,7 @@ tmp->started = true; tmp->abort = true; } - ieee80211_queue_work(&local->hw, &local->hw_roc_done); + wiphy_work_queue(local->hw.wiphy, &local->hw_roc_done); return; } @@ -368,7 +366,7 @@ ieee80211_hw_config(local, 0); } - ieee80211_queue_delayed_work(&local->hw, &local->roc_work, + wiphy_delayed_work_queue(local->hw.wiphy, &local->roc_work, msecs_to_jiffies(min_dur)); /* tell userspace or send frame(s) */ @@ -386,7 +384,7 @@ { struct ieee80211_roc_work *roc; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (list_empty(&local->roc_list)) { ieee80211_run_deferred_scan(local); @@ -407,7 +405,7 @@ _ieee80211_start_next_roc(local); } else { /* delay it a bit */ - ieee80211_queue_delayed_work(&local->hw, &local->roc_work, + wiphy_delayed_work_queue(local->hw.wiphy, &local->roc_work, round_jiffies_relative(HZ/2)); } } @@ -417,7 +415,7 @@ struct ieee80211_roc_work *roc; bool on_channel; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(local->ops->remain_on_channel)) return; @@ -451,29 +449,27 @@ } } -static void ieee80211_roc_work(struct work_struct *work) +static void ieee80211_roc_work(struct wiphy *wiphy, struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, roc_work.work); - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); + __ieee80211_roc_work(local); - mutex_unlock(&local->mtx); } -static void ieee80211_hw_roc_done(struct work_struct *work) +static void ieee80211_hw_roc_done(struct wiphy *wiphy, struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, hw_roc_done); - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); ieee80211_end_finished_rocs(local, jiffies); /* if there's another roc, start it now */ ieee80211_start_next_roc(local); - - mutex_unlock(&local->mtx); } void ieee80211_remain_on_channel_expired(struct ieee80211_hw *hw) @@ -482,7 +478,7 @@ trace_api_remain_on_channel_expired(local); - ieee80211_queue_work(hw, &local->hw_roc_done); + wiphy_work_queue(hw->wiphy, &local->hw_roc_done); } EXPORT_SYMBOL_GPL(ieee80211_remain_on_channel_expired); @@ -537,7 +533,7 @@ bool queued = false, combine_started = true; int ret; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (channel->freq_offset) /* this may work, but is untested */ @@ -586,7 +582,7 @@ /* if not HW assist, just queue & schedule work */ if (!local->ops->remain_on_channel) { list_add_tail(&roc->list, &local->roc_list); - ieee80211_queue_delayed_work(&local->hw, + wiphy_delayed_work_queue(local->hw.wiphy, &local->roc_work, 0); } else { /* otherwise actually kick it off here @@ -675,15 +671,12 @@ { struct ieee80211_sub_if_data *sdata = IEEE80211_WDEV_TO_SUB_IF(wdev); struct ieee80211_local *local = sdata->local; - int ret; - mutex_lock(&local->mtx); - ret = ieee80211_start_roc_work(local, sdata, chan, + lockdep_assert_wiphy(local->hw.wiphy); + + return ieee80211_start_roc_work(local, sdata, chan, duration, cookie, NULL, IEEE80211_ROC_TYPE_NORMAL); - mutex_unlock(&local->mtx); - - return ret; } static int ieee80211_cancel_roc(struct ieee80211_local *local, @@ -692,12 +685,13 @@ struct ieee80211_roc_work *roc, *tmp, *found = NULL; int ret; + lockdep_assert_wiphy(local->hw.wiphy); + if (!cookie) return -ENOENT; - flush_work(&local->hw_roc_start); + wiphy_work_flush(local->hw.wiphy, &local->hw_roc_start); - mutex_lock(&local->mtx); list_for_each_entry_safe(roc, tmp, &local->roc_list, list) { if (!mgmt_tx && roc->cookie != cookie) continue; @@ -709,7 +703,6 @@ } if (!found) { - mutex_unlock(&local->mtx); return -ENOENT; } @@ -721,10 +714,26 @@ if (local->ops->remain_on_channel) { ret = drv_cancel_remain_on_channel(local, roc->sdata); if (WARN_ON_ONCE(ret)) { - mutex_unlock(&local->mtx); return ret; } + /* + * We could be racing against the notification from the driver: + * + driver is handling the notification on CPU0 + * + user space is cancelling the remain on channel and + * schedules the hw_roc_done worker. + * + * Now hw_roc_done might start to run after the next roc will + * start and mac80211 will think that this second roc has + * ended prematurely. + * Cancel the work to make sure that all the pending workers + * have completed execution. + * Note that this assumes that by the time the driver returns + * from drv_cancel_remain_on_channel, it has completed all + * the processing of related notifications. + */ + wiphy_work_cancel(local->hw.wiphy, &local->hw_roc_done); + /* TODO: * if multiple items were combined here then we really shouldn't * cancel them all - we should wait for as much time as needed @@ -745,11 +754,10 @@ } else { /* go through work struct to return to the operating channel */ found->abort = true; - mod_delayed_work(local->workqueue, &local->roc_work, 0); + wiphy_delayed_work_queue(local->hw.wiphy, &local->roc_work, 0); } out_unlock: - mutex_unlock(&local->mtx); return 0; } @@ -778,6 +786,8 @@ int ret; u8 *data; + lockdep_assert_wiphy(local->hw.wiphy); + if (params->dont_wait_for_ack) flags = IEEE80211_TX_CTL_NO_ACK; else @@ -833,13 +843,16 @@ break; case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: - sdata_lock(sdata); if (!sdata->u.mgd.associated || (params->offchan && params->wait && local->ops->remain_on_channel && - memcmp(sdata->vif.cfg.ap_addr, mgmt->bssid, ETH_ALEN))) + memcmp(sdata->vif.cfg.ap_addr, mgmt->bssid, ETH_ALEN))) { need_offchan = true; - sdata_unlock(sdata); + } else if (sdata->u.mgd.associated && + ether_addr_equal(sdata->vif.cfg.ap_addr, mgmt->da)) { + sta = sta_info_get_bss(sdata, mgmt->da); + mlo_sta = sta && sta->sta.mlo; + } break; case NL80211_IFTYPE_P2P_DEVICE: need_offchan = true; @@ -855,8 +868,6 @@ if (need_offchan && !params->chan) return -EINVAL; - mutex_lock(&local->mtx); - /* Check if the operating channel is the requested channel */ if (!params->chan && mlo_sta) { need_offchan = false; @@ -980,7 +991,6 @@ if (ret) ieee80211_free_txskb(&local->hw, skb); out_unlock: - mutex_unlock(&local->mtx); return ret; } @@ -994,9 +1004,9 @@ void ieee80211_roc_setup(struct ieee80211_local *local) { - INIT_WORK(&local->hw_roc_start, ieee80211_hw_roc_start); - INIT_WORK(&local->hw_roc_done, ieee80211_hw_roc_done); - INIT_DELAYED_WORK(&local->roc_work, ieee80211_roc_work); + wiphy_work_init(&local->hw_roc_start, ieee80211_hw_roc_start); + wiphy_work_init(&local->hw_roc_done, ieee80211_hw_roc_done); + wiphy_delayed_work_init(&local->roc_work, ieee80211_roc_work); INIT_LIST_HEAD(&local->roc_list); } @@ -1006,7 +1016,8 @@ struct ieee80211_roc_work *roc, *tmp; bool work_to_do = false; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); + list_for_each_entry_safe(roc, tmp, &local->roc_list, list) { if (sdata && roc->sdata != sdata) continue; @@ -1014,7 +1025,7 @@ if (roc->started) { if (local->ops->remain_on_channel) { /* can race, so ignore return value */ - drv_cancel_remain_on_channel(local, sdata); + drv_cancel_remain_on_channel(local, roc->sdata); ieee80211_roc_notify_destroy(roc); } else { roc->abort = true; @@ -1026,5 +1037,4 @@ } if (work_to_do) __ieee80211_roc_work(local); - mutex_unlock(&local->mtx); } diff -ruw linux-6.4/net/mac80211/rc80211_minstrel_ht.c linux-6.4-fbx/net/mac80211/rc80211_minstrel_ht.c --- linux-6.4/net/mac80211/rc80211_minstrel_ht.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/rc80211_minstrel_ht.c 2023-11-07 13:38:44.086257347 +0100 @@ -1725,16 +1725,15 @@ mi->band = sband->band; mi->last_stats_update = jiffies; - ack_dur = ieee80211_frame_duration(sband->band, 10, 60, 1, 1, 0); - mi->overhead = ieee80211_frame_duration(sband->band, 0, 60, 1, 1, 0); + ack_dur = ieee80211_frame_duration(sband->band, 10, 60, 1, 1); + mi->overhead = ieee80211_frame_duration(sband->band, 0, 60, 1, 1); mi->overhead += ack_dur; mi->overhead_rtscts = mi->overhead + 2 * ack_dur; ctl_rate = &sband->bitrates[rate_lowest_index(sband, sta)]; erp = ctl_rate->flags & IEEE80211_RATE_ERP_G; ack_dur = ieee80211_frame_duration(sband->band, 10, - ctl_rate->bitrate, erp, 1, - ieee80211_chandef_get_shift(chandef)); + ctl_rate->bitrate, erp, 1); mi->overhead_legacy = ack_dur; mi->overhead_legacy_rtscts = mi->overhead_legacy + 2 * ack_dur; diff -ruw linux-6.4/net/mac80211/rx.c linux-6.4-fbx/net/mac80211/rx.c --- linux-6.4/net/mac80211/rx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/rx.c 2024-04-19 16:04:28.973736213 +0200 @@ -6,7 +6,7 @@ * Copyright 2007-2010 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright(c) 2015 - 2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation */ #include @@ -32,6 +32,7 @@ #include "tkip.h" #include "wme.h" #include "rate.h" +#include "fbx_scum.h" /* * monitor mode reception @@ -229,7 +230,7 @@ } skb_queue_tail(&sdata->skb_queue, skb); - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); if (sta) sta->deflink.rx_stats.packets++; } @@ -817,17 +818,11 @@ return NULL; } + fbx80211_rx_monitor(local, origskb, rate, rtap_space); only_monitor = should_drop_frame(origskb, present_fcs_len, rtap_space); - if (!local->monitors || (status->flag & RX_FLAG_SKIP_MONITOR)) { - if (only_monitor) { - dev_kfree_skb(origskb); - return NULL; - } - - return ieee80211_clean_skb(origskb, present_fcs_len, - rtap_space); - } + if (!local->monitors || (status->flag & RX_FLAG_SKIP_MONITOR)) + goto out; ieee80211_handle_mu_mimo_mon(monitor_sdata, origskb, rtap_space); @@ -868,6 +863,11 @@ /* ditto */ if (!origskb) return NULL; +out: + if (only_monitor) { + dev_kfree_skb(origskb); + return NULL; + } return ieee80211_clean_skb(origskb, present_fcs_len, rtap_space); } @@ -1083,7 +1083,8 @@ struct sk_buff *tail = skb_peek_tail(frames); struct ieee80211_rx_status *status; - if (tid_agg_rx->reorder_buf_filtered & BIT_ULL(index)) + if (tid_agg_rx->reorder_buf_filtered && + tid_agg_rx->reorder_buf_filtered & BIT_ULL(index)) return true; if (!tail) @@ -1124,6 +1125,7 @@ } no_frame: + if (tid_agg_rx->reorder_buf_filtered) tid_agg_rx->reorder_buf_filtered &= ~BIT_ULL(index); tid_agg_rx->head_seq_num = ieee80211_sn_inc(tid_agg_rx->head_seq_num); } @@ -1434,7 +1436,7 @@ rx->sta->last_seq_ctrl[rx->seqno_idx] == hdr->seq_ctrl)) { I802_DEBUG_INC(rx->local->dot11FrameDuplicateCount); rx->link_sta->rx_stats.num_duplicates++; - return RX_DROP_UNUSABLE; + return RX_DROP_U_DUP; } else if (!(status->flag & RX_FLAG_AMSDU_MORE)) { rx->sta->last_seq_ctrl[rx->seqno_idx] = hdr->seq_ctrl; } @@ -1488,7 +1490,7 @@ cfg80211_rx_spurious_frame(rx->sdata->dev, hdr->addr2, GFP_ATOMIC)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SPURIOUS; return RX_DROP_MONITOR; } @@ -1732,7 +1734,7 @@ if (ether_addr_equal(bssid, rx->sdata->u.ibss.bssid) && test_sta_flag(sta, WLAN_STA_AUTHORIZED)) { link_sta->rx_stats.last_rx = jiffies; - if (ieee80211_is_data(hdr->frame_control) && + if (ieee80211_is_data_present(hdr->frame_control) && !is_multicast_ether_addr(hdr->addr1)) link_sta->rx_stats.last_rate = sta_stats_encode_rate(status); @@ -1746,7 +1748,7 @@ * match the current local configuration when processed. */ link_sta->rx_stats.last_rx = jiffies; - if (ieee80211_is_data(hdr->frame_control)) + if (ieee80211_is_data_present(hdr->frame_control)) link_sta->rx_stats.last_rate = sta_stats_encode_rate(status); } @@ -1881,7 +1883,7 @@ struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; int keyidx; - ieee80211_rx_result result = RX_DROP_UNUSABLE; + ieee80211_rx_result result = RX_DROP_U_DECRYPT_FAIL; struct ieee80211_key *sta_ptk = NULL; struct ieee80211_key *ptk_idx = NULL; int mmie_keyidx = -1; @@ -1931,7 +1933,7 @@ keyid = ieee80211_get_keyid(rx->skb); if (unlikely(keyid < 0)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_NO_KEY_ID; ptk_idx = rcu_dereference(rx->sta->ptk[keyid]); } @@ -2036,7 +2038,7 @@ keyidx = ieee80211_get_keyid(rx->skb); if (unlikely(keyidx < 0)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_NO_KEY_ID; /* check per-station GTK first, if multicast packet */ if (is_multicast_ether_addr(hdr->addr1) && rx->link_sta) @@ -2102,7 +2104,7 @@ result = ieee80211_crypto_gcmp_decrypt(rx); break; default: - result = RX_DROP_UNUSABLE; + result = RX_DROP_U_BAD_CIPHER; } /* the hdr variable is invalid after the decrypt handlers */ @@ -2110,7 +2112,7 @@ /* either the frame has been decrypted or will be dropped */ status->flag |= RX_FLAG_DECRYPTED; - if (unlikely(ieee80211_is_beacon(fc) && (result & RX_DROP_UNUSABLE) && + if (unlikely(ieee80211_is_beacon(fc) && RX_RES_IS_UNUSABLE(result) && rx->sdata->dev)) cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, skb->data, skb->len); @@ -2247,7 +2249,7 @@ I802_DEBUG_INC(rx->local->rx_handlers_fragments); if (skb_linearize(rx->skb)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; /* * skb_linearize() might change the skb->data and @@ -2310,11 +2312,11 @@ u8 pn[IEEE80211_CCMP_PN_LEN], *rpn; if (!requires_sequential_pn(rx, fc)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_NONSEQ_PN; /* Prevent mixed key and fragment cache attacks */ if (entry->key_color != rx->key->color) - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_KEY_COLOR; memcpy(pn, entry->last_pn, IEEE80211_CCMP_PN_LEN); for (i = IEEE80211_CCMP_PN_LEN - 1; i >= 0; i--) { @@ -2325,7 +2327,7 @@ rpn = rx->ccm_gcm.pn; if (memcmp(pn, rpn, IEEE80211_CCMP_PN_LEN)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_REPLAY; memcpy(entry->last_pn, pn, IEEE80211_CCMP_PN_LEN); } else if (entry->is_protected && (!rx->key || @@ -2336,11 +2338,11 @@ * if for TKIP Michael MIC should protect us, and WEP is a * lost cause anyway. */ - return RX_DROP_UNUSABLE; + return RX_DROP_U_EXPECT_DEFRAG_PROT; } else if (entry->is_protected && rx->key && entry->key_color != rx->key->color && (status->flag & RX_FLAG_DECRYPTED)) { - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_KEY_COLOR; } skb_pull(rx->skb, ieee80211_hdrlen(fc)); @@ -2359,7 +2361,7 @@ GFP_ATOMIC))) { I802_DEBUG_INC(rx->local->rx_handlers_drop_defrag); __skb_queue_purge(&entry->skb_list); - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; } } while ((skb = __skb_dequeue(&entry->skb_list))) { @@ -2403,29 +2405,42 @@ return 0; } -static int ieee80211_drop_unencrypted_mgmt(struct ieee80211_rx_data *rx) +static ieee80211_rx_result +ieee80211_drop_unencrypted_mgmt(struct ieee80211_rx_data *rx) { - struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)rx->skb->data; struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(rx->skb); - __le16 fc = hdr->frame_control; + struct ieee80211_mgmt *mgmt = (void *)rx->skb->data; + __le16 fc = mgmt->frame_control; /* * Pass through unencrypted frames if the hardware has * decrypted them already. */ if (status->flag & RX_FLAG_DECRYPTED) - return 0; + return RX_CONTINUE; + + /* drop unicast protected dual (that wasn't protected) */ + if (ieee80211_is_action(fc) && + mgmt->u.action.category == WLAN_CATEGORY_PROTECTED_DUAL_OF_ACTION) + return RX_DROP_U_UNPROT_DUAL; if (rx->sta && test_sta_flag(rx->sta, WLAN_STA_MFP)) { if (unlikely(!ieee80211_has_protected(fc) && - ieee80211_is_unicast_robust_mgmt_frame(rx->skb) && - rx->key)) { + ieee80211_is_unicast_robust_mgmt_frame(rx->skb))) { if (ieee80211_is_deauth(fc) || - ieee80211_is_disassoc(fc)) + ieee80211_is_disassoc(fc)) { + /* + * Permit unprotected deauth/disassoc frames + * during 4-way-HS (key is installed after HS). + */ + if (!rx->key) + return RX_CONTINUE; + cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, rx->skb->data, rx->skb->len); - return -EACCES; + } + return RX_DROP_U_UNPROT_UCAST_MGMT; } /* BIP does not use Protected field, so need to check MMIE */ if (unlikely(ieee80211_is_multicast_robust_mgmt_frame(rx->skb) && @@ -2435,14 +2450,14 @@ cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, rx->skb->data, rx->skb->len); - return -EACCES; + return RX_DROP_U_UNPROT_MCAST_MGMT; } if (unlikely(ieee80211_is_beacon(fc) && rx->key && ieee80211_get_mmie_keyidx(rx->skb) < 0)) { cfg80211_rx_unprot_mlme_mgmt(rx->sdata->dev, rx->skb->data, rx->skb->len); - return -EACCES; + return RX_DROP_U_UNPROT_BEACON; } /* * When using MFP, Action frames are not allowed prior to @@ -2450,13 +2465,27 @@ */ if (unlikely(ieee80211_is_action(fc) && !rx->key && ieee80211_is_robust_mgmt_frame(rx->skb))) - return -EACCES; + return RX_DROP_U_UNPROT_ACTION; + + /* drop unicast public action frames when using MPF */ + if (is_unicast_ether_addr(mgmt->da) && + ieee80211_is_protected_dual_of_public_action(rx->skb)) + return RX_DROP_U_UNPROT_UNICAST_PUB_ACTION; } - return 0; + /* + * Drop robust action frames before assoc regardless of MFP state, + * after assoc we also have decided on MFP or not. + */ + if (ieee80211_is_action(fc) && + ieee80211_is_robust_mgmt_frame(rx->skb) && + (!rx->sta || !test_sta_flag(rx->sta, WLAN_STA_ASSOC))) + return RX_DROP_U_UNPROT_ROBUST_ACTION; + + return RX_CONTINUE; } -static int +static ieee80211_rx_result __ieee80211_data_to_8023(struct ieee80211_rx_data *rx, bool *port_control) { struct ieee80211_sub_if_data *sdata = rx->sdata; @@ -2468,32 +2497,31 @@ *port_control = false; if (ieee80211_has_a4(hdr->frame_control) && sdata->vif.type == NL80211_IFTYPE_AP_VLAN && !sdata->u.vlan.sta) - return -1; + return RX_DROP_U_UNEXPECTED_VLAN_4ADDR; if (sdata->vif.type == NL80211_IFTYPE_STATION && !!sdata->u.mgd.use_4addr != !!ieee80211_has_a4(hdr->frame_control)) { - if (!sdata->u.mgd.use_4addr) - return -1; + return RX_DROP_U_UNEXPECTED_STA_4ADDR; else if (!ether_addr_equal(hdr->addr1, sdata->vif.addr)) check_port_control = true; } if (is_multicast_ether_addr(hdr->addr1) && sdata->vif.type == NL80211_IFTYPE_AP_VLAN && sdata->u.vlan.sta) - return -1; + return RX_DROP_U_UNEXPECTED_VLAN_MCAST; ret = ieee80211_data_to_8023(rx->skb, sdata->vif.addr, sdata->vif.type); if (ret < 0) - return ret; + return RX_DROP_U_INVALID_8023; ehdr = (struct ethhdr *) rx->skb->data; if (ehdr->h_proto == rx->sdata->control_port_protocol) *port_control = true; else if (check_port_control) - return -1; + return RX_DROP_U_NOT_PORT_CONTROL; - return 0; + return RX_CONTINUE; } bool ieee80211_is_our_addr(struct ieee80211_sub_if_data *sdata, @@ -2505,7 +2533,7 @@ if (ether_addr_equal(sdata->vif.addr, addr)) return true; - if (!sdata->vif.valid_links) + if (!ieee80211_vif_is_mld(&sdata->vif)) return false; for (link_id = 0; link_id < ARRAY_SIZE(sdata->vif.link_conf); link_id++) { @@ -2884,10 +2912,10 @@ skb = NULL; if (skb_cow_head(fwd_skb, hdrlen - sizeof(struct ethhdr))) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; if (skb_linearize(fwd_skb)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; } fwd_hdr = skb_push(fwd_skb, hdrlen - sizeof(struct ethhdr)); @@ -2983,7 +3011,7 @@ rx->sdata->vif.addr, rx->sdata->vif.type, data_offset, true)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_AMSDU; if (rx->sta->amsdu_mesh_control < 0) { s8 valid = -1; @@ -3058,21 +3086,21 @@ switch (rx->sdata->vif.type) { case NL80211_IFTYPE_AP_VLAN: if (!rx->sdata->u.vlan.sta) - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_4ADDR; break; case NL80211_IFTYPE_STATION: if (!rx->sdata->u.mgd.use_4addr) - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_4ADDR; break; case NL80211_IFTYPE_MESH_POINT: break; default: - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_4ADDR; } } if (is_multicast_ether_addr(hdr->addr1) || !rx->sta) - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_AMSDU; if (rx->key) { /* @@ -3085,7 +3113,7 @@ case WLAN_CIPHER_SUITE_WEP40: case WLAN_CIPHER_SUITE_WEP104: case WLAN_CIPHER_SUITE_TKIP: - return RX_DROP_UNUSABLE; + return RX_DROP_U_BAD_AMSDU_CIPHER; default: break; } @@ -3104,7 +3132,6 @@ __le16 fc = hdr->frame_control; ieee80211_rx_result res; bool port_control; - int err; if (unlikely(!ieee80211_is_data(hdr->frame_control))) return RX_CONTINUE; @@ -3125,9 +3152,9 @@ return RX_DROP_MONITOR; } - err = __ieee80211_data_to_8023(rx, &port_control); - if (unlikely(err)) - return RX_DROP_UNUSABLE; + res = __ieee80211_data_to_8023(rx, &port_control); + if (unlikely(res != RX_CONTINUE)) + return res; res = ieee80211_rx_mesh_data(rx->sdata, rx->sta, rx->skb); if (res != RX_CONTINUE) @@ -3356,6 +3383,11 @@ if (!ieee80211_is_mgmt(mgmt->frame_control)) return RX_DROP_MONITOR; + /* drop too small action frames */ + if (ieee80211_is_action(mgmt->frame_control) && + rx->skb->len < IEEE80211_MIN_ACTION_SIZE) + return RX_DROP_U_RUNT_ACTION; + if (rx->sdata->vif.type == NL80211_IFTYPE_AP && ieee80211_is_beacon(mgmt->frame_control) && !(rx->flags & IEEE80211_RX_BEACON_REPORTED)) { @@ -3375,10 +3407,7 @@ rx->flags |= IEEE80211_RX_BEACON_REPORTED; } - if (ieee80211_drop_unencrypted_mgmt(rx)) - return RX_DROP_UNUSABLE; - - return RX_CONTINUE; + return ieee80211_drop_unencrypted_mgmt(rx); } static bool @@ -3445,14 +3474,10 @@ if (!ieee80211_is_action(mgmt->frame_control)) return RX_CONTINUE; - /* drop too small frames */ - if (len < IEEE80211_MIN_ACTION_SIZE) - return RX_DROP_UNUSABLE; - if (!rx->sta && mgmt->u.action.category != WLAN_CATEGORY_PUBLIC && mgmt->u.action.category != WLAN_CATEGORY_SELF_PROTECTED && mgmt->u.action.category != WLAN_CATEGORY_SPECTRUM_MGMT) - return RX_DROP_UNUSABLE; + return RX_DROP_U_ACTION_UNKNOWN_SRC; switch (mgmt->u.action.category) { case WLAN_CATEGORY_HT: @@ -3532,6 +3557,7 @@ /* set cur_max_bandwidth and recalc sta bw */ rx->link_sta->cur_max_bandwidth = max_bw; + rx->link_sta->pub->sta_max_bandwidth = rx->link_sta->cur_max_bandwidth; new_bw = ieee80211_sta_cur_vht_bw(rx->link_sta); if (rx->link_sta->pub->bandwidth == new_bw) @@ -3713,6 +3739,10 @@ break; goto queue; case WLAN_CATEGORY_S1G: + if (len < offsetofend(typeof(*mgmt), + u.action.u.s1g.action_code)) + break; + switch (mgmt->u.action.u.s1g.action_code) { case WLAN_S1G_TWT_SETUP: case WLAN_S1G_TWT_TEARDOWN: @@ -3853,7 +3883,7 @@ /* do not return rejected action frames */ if (mgmt->u.action.category & 0x80) - return RX_DROP_UNUSABLE; + return RX_DROP_U_REJECTED_ACTION_RESPONSE; nskb = skb_copy_expand(rx->skb, local->hw.extra_tx_headroom, 0, GFP_ATOMIC); @@ -4245,6 +4275,7 @@ u16 ssn, u64 filtered, u16 received_mpdus) { + struct ieee80211_local *local; struct sta_info *sta; struct tid_ampdu_rx *tid_agg_rx; struct sk_buff_head frames; @@ -4262,6 +4293,11 @@ sta = container_of(pubsta, struct sta_info, sta); + local = sta->sdata->local; + WARN_ONCE(local->hw.max_rx_aggregation_subframes > 64, + "RX BA marker can't support max_rx_aggregation_subframes %u > 64\n", + local->hw.max_rx_aggregation_subframes); + if (!ieee80211_rx_data_set_sta(&rx, sta, -1)) return; @@ -4638,7 +4674,7 @@ struct ieee80211_local *local = sdata->local; struct sta_info *sta; - lockdep_assert_held(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(sta, &local->sta_list, list) { if (sdata != sta->sdata && @@ -4652,9 +4688,9 @@ { struct ieee80211_local *local = sdata->local; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + __ieee80211_check_fast_rx_iface(sdata); - mutex_unlock(&local->sta_mtx); } static void ieee80211_rx_8023(struct ieee80211_rx_data *rx, @@ -4907,6 +4943,37 @@ return true; } +static bool ieee80211_check_frame_is_valid_to_process(struct ieee80211_rx_data *rx, + struct sk_buff *skb) +{ + struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; + struct ieee80211_sub_if_data *sdata = rx->sdata; + struct ieee80211_if_mesh *ifmsh = &sdata->u.mesh; + struct mplink_block_list_info *mp_blink; + __le16 fc; + + fc = ((struct ieee80211_hdr *)skb->data)->frame_control; + + if ((rx->sdata->vif.type == NL80211_IFTYPE_MESH_POINT) && + ieee80211_is_data(fc) && is_multicast_ether_addr(hdr->addr1)) { + spin_lock_bh(&ifmsh->mplink_blocking_list_lock); + list_for_each_entry(mp_blink, &ifmsh->mplink_blocking_list, list) { + if (ether_addr_equal(hdr->addr2, mp_blink->dst)) { + spin_unlock_bh(&ifmsh->mplink_blocking_list_lock); +/* Commented this temporarily, need to give the option to enable/disable at run time */ +#if 0 + print_hex_dump_bytes("skb_dump:", DUMP_PREFIX_NONE, + skb->data, skb->len); +#endif + return false; + } + } + spin_unlock_bh(&ifmsh->mplink_blocking_list_lock); + } + + return true; +} + /* * This function returns whether or not the SKB * was destined for RX processing or not, which, @@ -4922,6 +4989,9 @@ struct link_sta_info *link_sta = rx->link_sta; struct ieee80211_link_data *link = rx->link; + if (!ieee80211_check_frame_is_valid_to_process(rx, skb)) + return false; + rx->skb = skb; /* See if we can do fast-rx; if we have to copy we already lost, @@ -5274,7 +5344,7 @@ * The same happens when we're not even started, * but that's worth a warning. */ - if (WARN_ON(!local->started)) + if (!local->started) goto drop; if (likely(!(status->flag & RX_FLAG_FAILED_PLCP_CRC))) { diff -ruw linux-6.4/net/mac80211/s1g.c linux-6.4-fbx/net/mac80211/s1g.c --- linux-6.4/net/mac80211/s1g.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/s1g.c 2023-11-07 13:38:44.086257347 +0100 @@ -2,6 +2,7 @@ /* * S1G handling * Copyright(c) 2020 Adapt-IP + * Copyright (C) 2023 Intel Corporation */ #include #include @@ -153,11 +154,11 @@ struct ieee80211_local *local = sdata->local; struct sta_info *sta; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); sta = sta_info_get_bss(sdata, mgmt->sa); if (!sta) - goto out; + return; switch (mgmt->u.action.u.s1g.action_code) { case WLAN_S1G_TWT_SETUP: @@ -169,9 +170,6 @@ default: break; } - -out: - mutex_unlock(&local->sta_mtx); } void ieee80211_s1g_status_twt_action(struct ieee80211_sub_if_data *sdata, @@ -181,11 +179,11 @@ struct ieee80211_local *local = sdata->local; struct sta_info *sta; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); sta = sta_info_get_bss(sdata, mgmt->da); if (!sta) - goto out; + return; switch (mgmt->u.action.u.s1g.action_code) { case WLAN_S1G_TWT_SETUP: @@ -195,7 +193,4 @@ default: break; } - -out: - mutex_unlock(&local->sta_mtx); } diff -ruw linux-6.4/net/mac80211/scan.c linux-6.4-fbx/net/mac80211/scan.c --- linux-6.4/net/mac80211/scan.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/scan.c 2023-11-07 13:38:44.086257347 +0100 @@ -9,7 +9,7 @@ * Copyright 2007, Michael Wu * Copyright 2013-2015 Intel Mobile Communications GmbH * Copyright 2016-2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation */ #include @@ -55,27 +55,45 @@ return qos_info & IEEE80211_WMM_IE_AP_QOSINFO_UAPSD; } -static void -ieee80211_update_bss_from_elems(struct ieee80211_local *local, - struct ieee80211_bss *bss, - struct ieee802_11_elems *elems, - struct ieee80211_rx_status *rx_status, - bool beacon) -{ +struct inform_bss_update_data { + struct ieee80211_rx_status *rx_status; + bool beacon; +}; + +void ieee80211_inform_bss(struct wiphy *wiphy, + struct cfg80211_bss *cbss, + const struct cfg80211_bss_ies *ies, + void *data) +{ + struct ieee80211_local *local = wiphy_priv(wiphy); + struct inform_bss_update_data *update_data = data; + struct ieee80211_bss *bss = (void *)cbss->priv; + struct ieee80211_rx_status *rx_status; + struct ieee802_11_elems *elems; int clen, srlen; - if (beacon) + /* This happens while joining an IBSS */ + if (!update_data) + return; + + elems = ieee802_11_parse_elems(ies->data, ies->len, false, NULL); + if (!elems) + return; + + rx_status = update_data->rx_status; + + if (update_data->beacon) bss->device_ts_beacon = rx_status->device_timestamp; else bss->device_ts_presp = rx_status->device_timestamp; if (elems->parse_error) { - if (beacon) + if (update_data->beacon) bss->corrupt_data |= IEEE80211_BSS_CORRUPT_BEACON; else bss->corrupt_data |= IEEE80211_BSS_CORRUPT_PROBE_RESP; } else { - if (beacon) + if (update_data->beacon) bss->corrupt_data &= ~IEEE80211_BSS_CORRUPT_BEACON; else bss->corrupt_data &= ~IEEE80211_BSS_CORRUPT_PROBE_RESP; @@ -124,7 +142,7 @@ bss->valid_data |= IEEE80211_BSS_VALID_WMM; } - if (beacon) { + if (update_data->beacon) { struct ieee80211_supported_band *sband = local->hw.wiphy->bands[rx_status->band]; if (!(rx_status->encoding == RX_ENC_HT) && @@ -138,6 +156,8 @@ le32_to_cpu(elems->vht_cap_elem->vht_cap_info); else bss->vht_cap_info = 0; + + kfree(elems); } struct ieee80211_bss * @@ -148,16 +168,17 @@ { bool beacon = ieee80211_is_beacon(mgmt->frame_control) || ieee80211_is_s1g_beacon(mgmt->frame_control); - struct cfg80211_bss *cbss, *non_tx_cbss; - struct ieee80211_bss *bss, *non_tx_bss; + struct cfg80211_bss *cbss; + struct inform_bss_update_data update_data = { + .rx_status = rx_status, + .beacon = beacon, + }; struct cfg80211_inform_bss bss_meta = { .boottime_ns = rx_status->boottime_ns, + .drv_data = (void *)&update_data, }; bool signal_valid; struct ieee80211_sub_if_data *scan_sdata; - struct ieee802_11_elems *elems; - size_t baselen; - u8 *elements; if (rx_status->flag & RX_FLAG_NO_SIGNAL_VAL) bss_meta.signal = 0; /* invalid signal indication */ @@ -166,12 +187,6 @@ else if (ieee80211_hw_check(&local->hw, SIGNAL_UNSPEC)) bss_meta.signal = (rx_status->signal * 100) / local->hw.max_signal; - bss_meta.scan_width = NL80211_BSS_CHAN_WIDTH_20; - if (rx_status->bw == RATE_INFO_BW_5) - bss_meta.scan_width = NL80211_BSS_CHAN_WIDTH_5; - else if (rx_status->bw == RATE_INFO_BW_10) - bss_meta.scan_width = NL80211_BSS_CHAN_WIDTH_10; - bss_meta.chan = channel; rcu_read_lock(); @@ -192,50 +207,12 @@ if (!cbss) return NULL; - if (ieee80211_is_probe_resp(mgmt->frame_control)) { - elements = mgmt->u.probe_resp.variable; - baselen = offsetof(struct ieee80211_mgmt, - u.probe_resp.variable); - } else if (ieee80211_is_s1g_beacon(mgmt->frame_control)) { - struct ieee80211_ext *ext = (void *) mgmt; - - baselen = offsetof(struct ieee80211_ext, u.s1g_beacon.variable); - elements = ext->u.s1g_beacon.variable; - } else { - baselen = offsetof(struct ieee80211_mgmt, u.beacon.variable); - elements = mgmt->u.beacon.variable; - } - - if (baselen > len) - return NULL; - - elems = ieee802_11_parse_elems(elements, len - baselen, false, cbss); - if (!elems) - return NULL; - /* In case the signal is invalid update the status */ signal_valid = channel == cbss->channel; if (!signal_valid) rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; - bss = (void *)cbss->priv; - ieee80211_update_bss_from_elems(local, bss, elems, rx_status, beacon); - kfree(elems); - - list_for_each_entry(non_tx_cbss, &cbss->nontrans_list, nontrans_list) { - non_tx_bss = (void *)non_tx_cbss->priv; - - elems = ieee802_11_parse_elems(elements, len - baselen, false, - non_tx_cbss); - if (!elems) - continue; - - ieee80211_update_bss_from_elems(local, non_tx_bss, elems, - rx_status, beacon); - kfree(elems); - } - - return bss; + return (void *)cbss->priv; } static bool ieee80211_scan_accept_presp(struct ieee80211_sub_if_data *sdata, @@ -292,7 +269,7 @@ * to active scan */ set_bit(SCAN_BEACON_DONE, &local->scanning); - ieee80211_queue_delayed_work(&local->hw, &local->scan_work, 0); + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, 0); } if (ieee80211_is_probe_resp(mgmt->frame_control)) { @@ -332,22 +309,11 @@ ieee80211_rx_bss_put(local, bss); } -static void -ieee80211_prepare_scan_chandef(struct cfg80211_chan_def *chandef, - enum nl80211_bss_scan_width scan_width) +static void ieee80211_prepare_scan_chandef(struct cfg80211_chan_def *chandef) { memset(chandef, 0, sizeof(*chandef)); - switch (scan_width) { - case NL80211_BSS_CHAN_WIDTH_5: - chandef->width = NL80211_CHAN_WIDTH_5; - break; - case NL80211_BSS_CHAN_WIDTH_10: - chandef->width = NL80211_CHAN_WIDTH_10; - break; - default: + chandef->width = NL80211_CHAN_WIDTH_20_NOHT; - break; - } } /* return false if no more work */ @@ -361,7 +327,7 @@ u32 flags = 0; req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (test_bit(SCAN_HW_CANCELLED, &local->scanning)) return false; @@ -395,7 +361,7 @@ } local->hw_scan_req->req.n_channels = n_chans; - ieee80211_prepare_scan_chandef(&chandef, req->scan_width); + ieee80211_prepare_scan_chandef(&chandef); if (req->flags & NL80211_SCAN_FLAG_MIN_PREQ_CONTENT) flags |= IEEE80211_PROBE_FLAG_MIN_CONTENT; @@ -426,7 +392,7 @@ struct ieee80211_sub_if_data *scan_sdata; struct ieee80211_sub_if_data *sdata; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* * It's ok to abort a not-yet-running scan (that @@ -441,7 +407,7 @@ return; scan_sdata = rcu_dereference_protected(local->scan_sdata, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (hw_scan && !aborted && !ieee80211_hw_check(&local->hw, SINGLE_SCAN_ON_ALL_BANDS) && @@ -450,7 +416,7 @@ rc = drv_hw_scan(local, rcu_dereference_protected(local->scan_sdata, - lockdep_is_held(&local->mtx)), + lockdep_is_held(&local->hw.wiphy->mtx)), local->hw_scan_req); if (rc == 0) @@ -467,7 +433,7 @@ local->hw_scan_req = NULL; scan_req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); RCU_INIT_POINTER(local->scan_req, NULL); RCU_INIT_POINTER(local->scan_sdata, NULL); @@ -502,7 +468,7 @@ */ list_for_each_entry_rcu(sdata, &local->interfaces, list) { if (ieee80211_sdata_running(sdata)) - ieee80211_queue_work(&sdata->local->hw, &sdata->work); + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->work); } if (was_scanning) @@ -522,7 +488,7 @@ memcpy(&local->scan_info, info, sizeof(*info)); - ieee80211_queue_delayed_work(&local->hw, &local->scan_work, 0); + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, 0); } EXPORT_SYMBOL(ieee80211_scan_completed); @@ -562,8 +528,7 @@ /* We need to set power level at maximum rate for scanning. */ ieee80211_hw_config(local, 0); - ieee80211_queue_delayed_work(&local->hw, - &local->scan_work, 0); + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, 0); return 0; } @@ -573,20 +538,18 @@ struct ieee80211_local *local = sdata->local; struct ieee80211_sub_if_data *sdata_iter; + lockdep_assert_wiphy(local->hw.wiphy); + if (!ieee80211_is_radar_required(local)) return true; if (!regulatory_pre_cac_allowed(local->hw.wiphy)) return false; - mutex_lock(&local->iflist_mtx); list_for_each_entry(sdata_iter, &local->interfaces, list) { - if (sdata_iter->wdev.cac_started) { - mutex_unlock(&local->iflist_mtx); + if (sdata_iter->wdev.cac_started) return false; } - } - mutex_unlock(&local->iflist_mtx); return true; } @@ -609,7 +572,7 @@ void ieee80211_run_deferred_scan(struct ieee80211_local *local) { - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (!local->scan_req || local->scanning) return; @@ -617,10 +580,10 @@ if (!ieee80211_can_scan(local, rcu_dereference_protected( local->scan_sdata, - lockdep_is_held(&local->mtx)))) + lockdep_is_held(&local->hw.wiphy->mtx)))) return; - ieee80211_queue_delayed_work(&local->hw, &local->scan_work, + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, round_jiffies_relative(0)); } @@ -662,7 +625,7 @@ u32 flags = 0, tx_flags; scan_req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); tx_flags = IEEE80211_TX_INTFL_OFFCHAN_TX_OK; if (scan_req->no_cck) @@ -673,7 +636,7 @@ flags |= IEEE80211_PROBE_FLAG_RANDOM_SN; sdata = rcu_dereference_protected(local->scan_sdata, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); for (i = 0; i < scan_req->n_ssids; i++) ieee80211_send_scan_probe_req( @@ -698,7 +661,7 @@ bool hw_scan = local->ops->hw_scan; int rc; - lockdep_assert_held(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (local->scan_req) return -EBUSY; @@ -812,7 +775,7 @@ } /* Now, just wait a bit and we are all done! */ - ieee80211_queue_delayed_work(&local->hw, &local->scan_work, + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, next_delay); return 0; } else { @@ -878,12 +841,13 @@ enum mac80211_scan_state next_scan_state; struct cfg80211_scan_request *scan_req; + lockdep_assert_wiphy(local->hw.wiphy); + /* * check if at least one STA interface is associated, * check if at least one STA interface has pending tx frames * and grab the lowest used beacon interval */ - mutex_lock(&local->iflist_mtx); list_for_each_entry(sdata, &local->interfaces, list) { if (!ieee80211_sdata_running(sdata)) continue; @@ -899,10 +863,9 @@ } } } - mutex_unlock(&local->iflist_mtx); scan_req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); next_chan = scan_req->channels[local->scan_channel_idx]; @@ -939,11 +902,10 @@ { int skip; struct ieee80211_channel *chan; - enum nl80211_bss_scan_width oper_scan_width; struct cfg80211_scan_request *scan_req; scan_req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); skip = 0; chan = scan_req->channels[local->scan_channel_idx]; @@ -953,42 +915,21 @@ local->scan_chandef.freq1_offset = chan->freq_offset; local->scan_chandef.center_freq2 = 0; - /* For scanning on the S1G band, ignore scan_width (which is constant - * across all channels) for now since channel width is specific to each - * channel. Detect the required channel width here and likely revisit - * later. Maybe scan_width could be used to build the channel scan list? + /* For scanning on the S1G band, detect the channel width according to + * the channel being scanned. */ if (chan->band == NL80211_BAND_S1GHZ) { local->scan_chandef.width = ieee80211_s1g_channel_width(chan); goto set_channel; } - switch (scan_req->scan_width) { - case NL80211_BSS_CHAN_WIDTH_5: - local->scan_chandef.width = NL80211_CHAN_WIDTH_5; - break; - case NL80211_BSS_CHAN_WIDTH_10: - local->scan_chandef.width = NL80211_CHAN_WIDTH_10; - break; - default: - case NL80211_BSS_CHAN_WIDTH_20: /* If scanning on oper channel, use whatever channel-type * is currently in use. */ - oper_scan_width = cfg80211_chandef_to_scan_width( - &local->_oper_chandef); - if (chan == local->_oper_chandef.chan && - oper_scan_width == scan_req->scan_width) + if (chan == local->_oper_chandef.chan) local->scan_chandef = local->_oper_chandef; else local->scan_chandef.width = NL80211_CHAN_WIDTH_20_NOHT; - break; - case NL80211_BSS_CHAN_WIDTH_1: - case NL80211_BSS_CHAN_WIDTH_2: - /* shouldn't get here, S1G handled above */ - WARN_ON(1); - break; - } set_channel: if (ieee80211_hw_config(local, IEEE80211_CONF_CHANGE_CHANNEL)) @@ -1060,7 +1001,7 @@ local->next_scan_state = SCAN_SET_CHANNEL; } -void ieee80211_scan_work(struct work_struct *work) +void ieee80211_scan_work(struct wiphy *wiphy, struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, scan_work.work); @@ -1069,7 +1010,7 @@ unsigned long next_delay = 0; bool aborted; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (!ieee80211_can_run_worker(local)) { aborted = true; @@ -1077,9 +1018,9 @@ } sdata = rcu_dereference_protected(local->scan_sdata, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); scan_req = rcu_dereference_protected(local->scan_req, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); /* When scanning on-channel, the first-callback means completed. */ if (test_bit(SCAN_ONCHANNEL_SCANNING, &local->scanning)) { @@ -1093,7 +1034,7 @@ } if (!sdata || !scan_req) - goto out; + return; if (!local->scanning) { int rc; @@ -1102,13 +1043,12 @@ RCU_INIT_POINTER(local->scan_sdata, NULL); rc = __ieee80211_start_scan(sdata, scan_req); - if (rc) { + if (!rc) + return; /* need to complete scan in cfg80211 */ rcu_assign_pointer(local->scan_req, scan_req); aborted = true; goto out_complete; - } else - goto out; } clear_bit(SCAN_BEACON_WAIT, &local->scanning); @@ -1154,38 +1094,32 @@ } } while (next_delay == 0); - ieee80211_queue_delayed_work(&local->hw, &local->scan_work, next_delay); - goto out; + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, + next_delay); + return; out_complete: __ieee80211_scan_completed(&local->hw, aborted); -out: - mutex_unlock(&local->mtx); } int ieee80211_request_scan(struct ieee80211_sub_if_data *sdata, struct cfg80211_scan_request *req) { - int res; - - mutex_lock(&sdata->local->mtx); - res = __ieee80211_start_scan(sdata, req); - mutex_unlock(&sdata->local->mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); - return res; + return __ieee80211_start_scan(sdata, req); } int ieee80211_request_ibss_scan(struct ieee80211_sub_if_data *sdata, const u8 *ssid, u8 ssid_len, struct ieee80211_channel **channels, - unsigned int n_channels, - enum nl80211_bss_scan_width scan_width) + unsigned int n_channels) { struct ieee80211_local *local = sdata->local; int ret = -EBUSY, i, n_ch = 0; enum nl80211_band band; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* busy scanning */ if (local->scan_req) @@ -1236,13 +1170,11 @@ local->int_scan_req->ssids = &local->scan_ssid; local->int_scan_req->n_ssids = 1; - local->int_scan_req->scan_width = scan_width; memcpy(local->int_scan_req->ssids[0].ssid, ssid, IEEE80211_MAX_SSID_LEN); local->int_scan_req->ssids[0].ssid_len = ssid_len; ret = __ieee80211_start_scan(sdata, sdata->local->int_scan_req); unlock: - mutex_unlock(&local->mtx); return ret; } @@ -1269,9 +1201,8 @@ * after the scan was completed/aborted. */ - mutex_lock(&local->mtx); if (!local->scan_req) - goto out; + return; /* * We have a scan running and the driver already reported completion, @@ -1281,7 +1212,7 @@ if (test_bit(SCAN_HW_SCANNING, &local->scanning) && test_bit(SCAN_COMPLETED, &local->scanning)) { set_bit(SCAN_HW_CANCELLED, &local->scanning); - goto out; + return; } if (test_bit(SCAN_HW_SCANNING, &local->scanning)) { @@ -1293,21 +1224,14 @@ if (local->ops->cancel_hw_scan) drv_cancel_hw_scan(local, rcu_dereference_protected(local->scan_sdata, - lockdep_is_held(&local->mtx))); - goto out; + lockdep_is_held(&local->hw.wiphy->mtx))); + return; } - /* - * If the work is currently running, it must be blocked on - * the mutex, but we'll set scan_sdata = NULL and it'll - * simply exit once it acquires the mutex. - */ - cancel_delayed_work(&local->scan_work); + wiphy_delayed_work_cancel(local->hw.wiphy, &local->scan_work); /* and clean up */ memset(&local->scan_info, 0, sizeof(local->scan_info)); __ieee80211_scan_completed(&local->hw, true); -out: - mutex_unlock(&local->mtx); } int __ieee80211_request_sched_scan_start(struct ieee80211_sub_if_data *sdata, @@ -1322,9 +1246,9 @@ u8 *ie; u32 flags = 0; - iebufsz = local->scan_ies_len + req->ie_len; + lockdep_assert_wiphy(local->hw.wiphy); - lockdep_assert_held(&local->mtx); + iebufsz = local->scan_ies_len + req->ie_len; if (!local->ops->sched_scan_start) return -ENOTSUPP; @@ -1346,7 +1270,7 @@ goto out; } - ieee80211_prepare_scan_chandef(&chandef, req->scan_width); + ieee80211_prepare_scan_chandef(&chandef); ieee80211_build_preq_ies(sdata, ie, num_bands * iebufsz, &sched_scan_ies, req->ie, @@ -1375,19 +1299,13 @@ struct cfg80211_sched_scan_request *req) { struct ieee80211_local *local = sdata->local; - int ret; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); - if (rcu_access_pointer(local->sched_scan_sdata)) { - mutex_unlock(&local->mtx); + if (rcu_access_pointer(local->sched_scan_sdata)) return -EBUSY; - } - - ret = __ieee80211_request_sched_scan_start(sdata, req); - mutex_unlock(&local->mtx); - return ret; + return __ieee80211_request_sched_scan_start(sdata, req); } int ieee80211_request_sched_scan_stop(struct ieee80211_local *local) @@ -1395,25 +1313,21 @@ struct ieee80211_sub_if_data *sched_scan_sdata; int ret = -ENOENT; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); - if (!local->ops->sched_scan_stop) { - ret = -ENOTSUPP; - goto out; - } + if (!local->ops->sched_scan_stop) + return -ENOTSUPP; /* We don't want to restart sched scan anymore. */ RCU_INIT_POINTER(local->sched_scan_req, NULL); sched_scan_sdata = rcu_dereference_protected(local->sched_scan_sdata, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (sched_scan_sdata) { ret = drv_sched_scan_stop(local, sched_scan_sdata); if (!ret) RCU_INIT_POINTER(local->sched_scan_sdata, NULL); } -out: - mutex_unlock(&local->mtx); return ret; } @@ -1430,24 +1344,21 @@ void ieee80211_sched_scan_end(struct ieee80211_local *local) { - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); - if (!rcu_access_pointer(local->sched_scan_sdata)) { - mutex_unlock(&local->mtx); + if (!rcu_access_pointer(local->sched_scan_sdata)) return; - } RCU_INIT_POINTER(local->sched_scan_sdata, NULL); /* If sched scan was aborted by the driver. */ RCU_INIT_POINTER(local->sched_scan_req, NULL); - mutex_unlock(&local->mtx); - - cfg80211_sched_scan_stopped(local->hw.wiphy, 0); + cfg80211_sched_scan_stopped_locked(local->hw.wiphy, 0); } -void ieee80211_sched_scan_stopped_work(struct work_struct *work) +void ieee80211_sched_scan_stopped_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, @@ -1470,6 +1381,6 @@ if (local->in_reconfig) return; - schedule_work(&local->sched_scan_stopped_work); + wiphy_work_queue(hw->wiphy, &local->sched_scan_stopped_work); } EXPORT_SYMBOL(ieee80211_sched_scan_stopped); diff -ruw linux-6.4/net/mac80211/spectmgmt.c linux-6.4-fbx/net/mac80211/spectmgmt.c --- linux-6.4/net/mac80211/spectmgmt.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/spectmgmt.c 2023-11-07 13:38:44.086257347 +0100 @@ -9,7 +9,7 @@ * Copyright 2007, Michael Wu * Copyright 2007-2008, Intel Corporation * Copyright 2008, Johannes Berg - * Copyright (C) 2018, 2020, 2022 Intel Corporation + * Copyright (C) 2018, 2020, 2022-2023 Intel Corporation */ #include @@ -33,12 +33,14 @@ struct cfg80211_chan_def new_vht_chandef = {}; const struct ieee80211_sec_chan_offs_ie *sec_chan_offs; const struct ieee80211_wide_bw_chansw_ie *wide_bw_chansw_ie; + const struct ieee80211_bandwidth_indication *bwi; int secondary_channel_offset = -1; memset(csa_ie, 0, sizeof(*csa_ie)); sec_chan_offs = elems->sec_chan_offs; wide_bw_chansw_ie = elems->wide_bw_chansw_ie; + bwi = elems->bandwidth_indication; if (conn_flags & (IEEE80211_CONN_DISABLE_HT | IEEE80211_CONN_DISABLE_40MHZ)) { @@ -132,7 +134,14 @@ break; } - if (wide_bw_chansw_ie) { + if (bwi) { + /* start with the CSA one */ + new_vht_chandef = csa_ie->chandef; + /* and update the width accordingly */ + /* FIXME: support 160/320 */ + ieee80211_chandef_eht_oper(&bwi->info, true, true, + &new_vht_chandef); + } else if (wide_bw_chansw_ie) { u8 new_seg1 = wide_bw_chansw_ie->new_center_freq_seg1; struct ieee80211_vht_operation vht_oper = { .chan_width = diff -ruw linux-6.4/net/mac80211/sta_info.c linux-6.4-fbx/net/mac80211/sta_info.c --- linux-6.4/net/mac80211/sta_info.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/sta_info.c 2023-12-12 17:24:34.179627645 +0100 @@ -4,7 +4,7 @@ * Copyright 2006-2007 Jiri Benc * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright (C) 2015 - 2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation */ #include @@ -88,7 +88,6 @@ .max_size = CONFIG_MAC80211_STA_HASH_MAX_SIZE, }; -/* Caller must hold local->sta_mtx */ static int sta_info_hash_del(struct ieee80211_local *local, struct sta_info *sta) { @@ -99,19 +98,36 @@ static int link_sta_info_hash_add(struct ieee80211_local *local, struct link_sta_info *link_sta) { - lockdep_assert_held(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + return rhltable_insert(&local->link_sta_hash, - &link_sta->link_hash_node, - link_sta_rht_params); + &link_sta->link_hash_node, link_sta_rht_params); } static int link_sta_info_hash_del(struct ieee80211_local *local, struct link_sta_info *link_sta) { - lockdep_assert_held(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + return rhltable_remove(&local->link_sta_hash, - &link_sta->link_hash_node, - link_sta_rht_params); + &link_sta->link_hash_node, link_sta_rht_params); +} + +void ieee80211_purge_sta_txqs(struct sta_info *sta) +{ + struct ieee80211_local *local = sta->sdata->local; + int i; + + for (i = 0; i < ARRAY_SIZE(sta->sta.txq); i++) { + struct txq_info *txqi; + + if (!sta->sta.txq[i]) + continue; + + txqi = to_txq_info(sta->sta.txq[i]); + + ieee80211_txq_purge(local, txqi); + } } static void __cleanup_single_sta(struct sta_info *sta) @@ -140,16 +156,7 @@ atomic_dec(&ps->num_sta_ps); } - for (i = 0; i < ARRAY_SIZE(sta->sta.txq); i++) { - struct txq_info *txqi; - - if (!sta->sta.txq[i]) - continue; - - txqi = to_txq_info(sta->sta.txq[i]); - - ieee80211_txq_purge(local, txqi); - } + ieee80211_purge_sta_txqs(sta); for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) { local->total_ps_buffered -= skb_queue_len(&sta->ps_tx_buf[ac]); @@ -331,7 +338,7 @@ int i = 0; list_for_each_entry_rcu(sta, &local->sta_list, list, - lockdep_is_held(&local->sta_mtx)) { + lockdep_is_held(&local->hw.wiphy->mtx)) { if (sdata != sta->sdata) continue; if (i < idx) { @@ -355,9 +362,9 @@ struct sta_link_alloc *alloc = NULL; struct link_sta_info *link_sta; - link_sta = rcu_dereference_protected(sta->link[link_id], - lockdep_is_held(&sta->local->sta_mtx)); + lockdep_assert_wiphy(sta->local->hw.wiphy); + link_sta = rcu_access_pointer(sta->link[link_id]); if (WARN_ON(!link_sta)) return; @@ -436,7 +443,6 @@ kfree(sta); } -/* Caller must hold local->sta_mtx */ static int sta_info_hash_add(struct ieee80211_local *local, struct sta_info *sta) { @@ -454,9 +460,10 @@ return; local_bh_disable(); - if (!test_sta_flag(sta, WLAN_STA_PS_STA)) + if (!test_sta_flag(sta, WLAN_STA_PS_STA)) { + if (test_sta_flag(sta, WLAN_STA_PS_DELIVER)) ieee80211_sta_ps_deliver_wakeup(sta); - else if (test_and_clear_sta_flag(sta, WLAN_STA_PSPOLL)) + } else if (test_and_clear_sta_flag(sta, WLAN_STA_PSPOLL)) ieee80211_sta_ps_deliver_poll_response(sta); else if (test_and_clear_sta_flag(sta, WLAN_STA_UAPSD)) ieee80211_sta_ps_deliver_uapsd(sta); @@ -555,8 +562,7 @@ spin_lock_init(&sta->lock); spin_lock_init(&sta->ps_lock); INIT_WORK(&sta->drv_deliver_wk, sta_deliver_ps_frames); - INIT_WORK(&sta->ampdu_mlme.work, ieee80211_ba_session_work); - mutex_init(&sta->ampdu_mlme.mtx); + wiphy_work_init(&sta->ampdu_mlme.work, ieee80211_ba_session_work); #ifdef CONFIG_MAC80211_MESH if (ieee80211_vif_is_mesh(&sdata->vif)) { sta->mesh = kzalloc(sizeof(*sta->mesh), gfp); @@ -716,6 +722,8 @@ { struct ieee80211_sub_if_data *sdata = sta->sdata; + lockdep_assert_wiphy(sdata->local->hw.wiphy); + /* * Can't be a WARN_ON because it can be triggered through a race: * something inserts a STA (on one CPU) without holding the RTNL @@ -733,7 +741,6 @@ * for correctness. */ rcu_read_lock(); - lockdep_assert_held(&sdata->local->sta_mtx); if (ieee80211_hw_check(&sdata->local->hw, NEEDS_UNIQUE_STA_ADDR) && ieee80211_find_sta_by_ifaddr(&sdata->local->hw, sta->addr, NULL)) { rcu_read_unlock(); @@ -807,11 +814,6 @@ } } -/* - * should be called with sta_mtx locked - * this function replaces the mutex lock - * with a RCU lock - */ static int sta_info_insert_finish(struct sta_info *sta) __acquires(RCU) { struct ieee80211_local *local = sta->local; @@ -819,7 +821,7 @@ struct station_info *sinfo = NULL; int err = 0; - lockdep_assert_held(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* check if STA exists already */ if (sta_info_get_bss(sdata, sta->sta.addr)) { @@ -883,7 +885,7 @@ struct link_sta_info *link_sta; link_sta = rcu_dereference_protected(sta->link[i], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (!link_sta) continue; @@ -905,7 +907,6 @@ /* move reference to rcu-protected */ rcu_read_lock(); - mutex_unlock(&local->sta_mtx); if (ieee80211_vif_is_mesh(&sdata->vif)) mesh_accept_plinks_update(sdata); @@ -921,7 +922,6 @@ synchronize_net(); out_cleanup: cleanup_single_sta(sta); - mutex_unlock(&local->sta_mtx); kfree(sinfo); rcu_read_lock(); return err; @@ -933,13 +933,11 @@ int err; might_sleep(); - - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); err = sta_info_insert_check(sta); if (err) { sta_info_free(local, sta); - mutex_unlock(&local->sta_mtx); rcu_read_lock(); return err; } @@ -1218,7 +1216,7 @@ local = sta->local; sdata = sta->sdata; - lockdep_assert_held(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* * Before removing the station from the driver and @@ -1243,7 +1241,7 @@ continue; link_sta = rcu_dereference_protected(sta->link[i], - lockdep_is_held(&local->sta_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); link_sta_info_hash_del(local, link_sta); } @@ -1274,7 +1272,137 @@ return 0; } -static void __sta_info_destroy_part2(struct sta_info *sta) +static int _sta_info_move_state(struct sta_info *sta, + enum ieee80211_sta_state new_state, + bool recalc) +{ + struct ieee80211_local *local = sta->local; + + might_sleep(); + + if (sta->sta_state == new_state) + return 0; + + /* check allowed transitions first */ + + switch (new_state) { + case IEEE80211_STA_NONE: + if (sta->sta_state != IEEE80211_STA_AUTH) + return -EINVAL; + break; + case IEEE80211_STA_AUTH: + if (sta->sta_state != IEEE80211_STA_NONE && + sta->sta_state != IEEE80211_STA_ASSOC) + return -EINVAL; + break; + case IEEE80211_STA_ASSOC: + if (sta->sta_state != IEEE80211_STA_AUTH && + sta->sta_state != IEEE80211_STA_AUTHORIZED) + return -EINVAL; + break; + case IEEE80211_STA_AUTHORIZED: + if (sta->sta_state != IEEE80211_STA_ASSOC) + return -EINVAL; + break; + default: + WARN(1, "invalid state %d", new_state); + return -EINVAL; + } + + sta_dbg(sta->sdata, "moving STA %pM to state %d\n", + sta->sta.addr, new_state); + + /* notify the driver before the actual changes so it can + * fail the transition + */ + if (test_sta_flag(sta, WLAN_STA_INSERTED)) { + int err = drv_sta_state(sta->local, sta->sdata, sta, + sta->sta_state, new_state); + if (err) + return err; + } + + /* reflect the change in all state variables */ + + switch (new_state) { + case IEEE80211_STA_NONE: + if (sta->sta_state == IEEE80211_STA_AUTH) + clear_bit(WLAN_STA_AUTH, &sta->_flags); + break; + case IEEE80211_STA_AUTH: + if (sta->sta_state == IEEE80211_STA_NONE) { + set_bit(WLAN_STA_AUTH, &sta->_flags); + } else if (sta->sta_state == IEEE80211_STA_ASSOC) { + clear_bit(WLAN_STA_ASSOC, &sta->_flags); + if (recalc) { + ieee80211_recalc_min_chandef(sta->sdata, -1); + if (!sta->sta.support_p2p_ps) + ieee80211_recalc_p2p_go_ps_allowed(sta->sdata); + } + } + break; + case IEEE80211_STA_ASSOC: + if (sta->sta_state == IEEE80211_STA_AUTH) { + set_bit(WLAN_STA_ASSOC, &sta->_flags); + sta->assoc_at = ktime_get_boottime_ns(); + if (recalc) { + ieee80211_recalc_min_chandef(sta->sdata, -1); + if (!sta->sta.support_p2p_ps) + ieee80211_recalc_p2p_go_ps_allowed(sta->sdata); + } + } else if (sta->sta_state == IEEE80211_STA_AUTHORIZED) { + ieee80211_vif_dec_num_mcast(sta->sdata); + clear_bit(WLAN_STA_AUTHORIZED, &sta->_flags); + + /* + * If we have encryption offload, flush (station) queues + * (after ensuring concurrent TX completed) so we won't + * transmit anything later unencrypted if/when keys are + * also removed, which might otherwise happen depending + * on how the hardware offload works. + */ + if (local->ops->set_key) { + synchronize_net(); + if (local->ops->flush_sta) + drv_flush_sta(local, sta->sdata, sta); + else + ieee80211_flush_queues(local, + sta->sdata, + false); + } + + ieee80211_clear_fast_xmit(sta); + ieee80211_clear_fast_rx(sta); + } + break; + case IEEE80211_STA_AUTHORIZED: + if (sta->sta_state == IEEE80211_STA_ASSOC) { + ieee80211_vif_inc_num_mcast(sta->sdata); + set_bit(WLAN_STA_AUTHORIZED, &sta->_flags); + ieee80211_check_fast_xmit(sta); + ieee80211_check_fast_rx(sta); + } + if (sta->sdata->vif.type == NL80211_IFTYPE_AP_VLAN || + sta->sdata->vif.type == NL80211_IFTYPE_AP) + cfg80211_send_layer2_update(sta->sdata->dev, + sta->sta.addr); + break; + default: + break; + } + + sta->sta_state = new_state; + + return 0; +} + +int sta_info_move_state(struct sta_info *sta, + enum ieee80211_sta_state new_state) +{ + return _sta_info_move_state(sta, new_state, true); +} + +static void __sta_info_destroy_part2(struct sta_info *sta, bool recalc) { struct ieee80211_local *local = sta->local; struct ieee80211_sub_if_data *sdata = sta->sdata; @@ -1286,26 +1414,28 @@ * after _part1 and before _part2! */ + /* + * There's a potential race in _part1 where we set WLAN_STA_BLOCK_BA + * but someone might have just gotten past a check, and not yet into + * queuing the work/creating the data/etc. + * + * Do another round of destruction so that the worker is certainly + * canceled before we later free the station. + * + * Since this is after synchronize_rcu()/synchronize_net() we're now + * certain that nobody can actually hold a reference to the STA and + * be calling e.g. ieee80211_start_tx_ba_session(). + */ + ieee80211_sta_tear_down_BA_sessions(sta, AGG_STOP_DESTROY_STA); + might_sleep(); - lockdep_assert_held(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (sta->sta_state == IEEE80211_STA_AUTHORIZED) { - ret = sta_info_move_state(sta, IEEE80211_STA_ASSOC); + ret = _sta_info_move_state(sta, IEEE80211_STA_ASSOC, recalc); WARN_ON_ONCE(ret); } - /* Flush queues before removing keys, as that might remove them - * from hardware, and then depending on the offload method, any - * frames sitting on hardware queues might be sent out without - * any encryption at all. - */ - if (local->ops->set_key) { - if (local->ops->flush_sta) - drv_flush_sta(local, sta->sdata, sta); - else - ieee80211_flush_queues(local, sta->sdata, false); - } - /* now keys can no longer be reached */ ieee80211_free_sta_keys(local, sta); @@ -1318,7 +1448,7 @@ local->sta_generation++; while (sta->sta_state > IEEE80211_STA_NONE) { - ret = sta_info_move_state(sta, sta->sta_state - 1); + ret = _sta_info_move_state(sta, sta->sta_state - 1, recalc); if (ret) { WARN_ON_ONCE(1); break; @@ -1355,7 +1485,7 @@ synchronize_net(); - __sta_info_destroy_part2(sta); + __sta_info_destroy_part2(sta, true); return 0; } @@ -1363,28 +1493,22 @@ int sta_info_destroy_addr(struct ieee80211_sub_if_data *sdata, const u8 *addr) { struct sta_info *sta; - int ret; - mutex_lock(&sdata->local->sta_mtx); - sta = sta_info_get(sdata, addr); - ret = __sta_info_destroy(sta); - mutex_unlock(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); - return ret; + sta = sta_info_get(sdata, addr); + return __sta_info_destroy(sta); } int sta_info_destroy_addr_bss(struct ieee80211_sub_if_data *sdata, const u8 *addr) { struct sta_info *sta; - int ret; - mutex_lock(&sdata->local->sta_mtx); - sta = sta_info_get_bss(sdata, addr); - ret = __sta_info_destroy(sta); - mutex_unlock(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); - return ret; + sta = sta_info_get_bss(sdata, addr); + return __sta_info_destroy(sta); } static void sta_info_cleanup(struct timer_list *t) @@ -1424,7 +1548,6 @@ } spin_lock_init(&local->tim_lock); - mutex_init(&local->sta_mtx); INIT_LIST_HEAD(&local->sta_list); timer_setup(&local->sta_cleanup, sta_info_cleanup, 0); @@ -1447,11 +1570,11 @@ int ret = 0; might_sleep(); + lockdep_assert_wiphy(local->hw.wiphy); WARN_ON(vlans && sdata->vif.type != NL80211_IFTYPE_AP); WARN_ON(vlans && !sdata->bss); - mutex_lock(&local->sta_mtx); list_for_each_entry_safe(sta, tmp, &local->sta_list, list) { if (sdata == sta->sdata || (vlans && sdata->bss == sta->sdata->bss)) { @@ -1462,11 +1585,19 @@ } if (!list_empty(&free_list)) { + bool support_p2p_ps = true; + synchronize_net(); - list_for_each_entry_safe(sta, tmp, &free_list, free_list) - __sta_info_destroy_part2(sta); + list_for_each_entry_safe(sta, tmp, &free_list, free_list) { + if (!sta->sta.support_p2p_ps) + support_p2p_ps = false; + __sta_info_destroy_part2(sta, false); + } + + ieee80211_recalc_min_chandef(sdata, -1); + if (!support_p2p_ps) + ieee80211_recalc_p2p_go_ps_allowed(sdata); } - mutex_unlock(&local->sta_mtx); return ret; } @@ -1477,7 +1608,7 @@ struct ieee80211_local *local = sdata->local; struct sta_info *sta, *tmp; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry_safe(sta, tmp, &local->sta_list, list) { unsigned long last_active = ieee80211_sta_last_active(sta); @@ -1496,8 +1627,6 @@ WARN_ON(__sta_info_destroy(sta)); } } - - mutex_unlock(&local->sta_mtx); } struct ieee80211_sta *ieee80211_find_sta_by_ifaddr(struct ieee80211_hw *hw, @@ -2252,106 +2381,6 @@ } } -int sta_info_move_state(struct sta_info *sta, - enum ieee80211_sta_state new_state) -{ - might_sleep(); - - if (sta->sta_state == new_state) - return 0; - - /* check allowed transitions first */ - - switch (new_state) { - case IEEE80211_STA_NONE: - if (sta->sta_state != IEEE80211_STA_AUTH) - return -EINVAL; - break; - case IEEE80211_STA_AUTH: - if (sta->sta_state != IEEE80211_STA_NONE && - sta->sta_state != IEEE80211_STA_ASSOC) - return -EINVAL; - break; - case IEEE80211_STA_ASSOC: - if (sta->sta_state != IEEE80211_STA_AUTH && - sta->sta_state != IEEE80211_STA_AUTHORIZED) - return -EINVAL; - break; - case IEEE80211_STA_AUTHORIZED: - if (sta->sta_state != IEEE80211_STA_ASSOC) - return -EINVAL; - break; - default: - WARN(1, "invalid state %d", new_state); - return -EINVAL; - } - - sta_dbg(sta->sdata, "moving STA %pM to state %d\n", - sta->sta.addr, new_state); - - /* - * notify the driver before the actual changes so it can - * fail the transition - */ - if (test_sta_flag(sta, WLAN_STA_INSERTED)) { - int err = drv_sta_state(sta->local, sta->sdata, sta, - sta->sta_state, new_state); - if (err) - return err; - } - - /* reflect the change in all state variables */ - - switch (new_state) { - case IEEE80211_STA_NONE: - if (sta->sta_state == IEEE80211_STA_AUTH) - clear_bit(WLAN_STA_AUTH, &sta->_flags); - break; - case IEEE80211_STA_AUTH: - if (sta->sta_state == IEEE80211_STA_NONE) { - set_bit(WLAN_STA_AUTH, &sta->_flags); - } else if (sta->sta_state == IEEE80211_STA_ASSOC) { - clear_bit(WLAN_STA_ASSOC, &sta->_flags); - ieee80211_recalc_min_chandef(sta->sdata, -1); - if (!sta->sta.support_p2p_ps) - ieee80211_recalc_p2p_go_ps_allowed(sta->sdata); - } - break; - case IEEE80211_STA_ASSOC: - if (sta->sta_state == IEEE80211_STA_AUTH) { - set_bit(WLAN_STA_ASSOC, &sta->_flags); - sta->assoc_at = ktime_get_boottime_ns(); - ieee80211_recalc_min_chandef(sta->sdata, -1); - if (!sta->sta.support_p2p_ps) - ieee80211_recalc_p2p_go_ps_allowed(sta->sdata); - } else if (sta->sta_state == IEEE80211_STA_AUTHORIZED) { - ieee80211_vif_dec_num_mcast(sta->sdata); - clear_bit(WLAN_STA_AUTHORIZED, &sta->_flags); - ieee80211_clear_fast_xmit(sta); - ieee80211_clear_fast_rx(sta); - } - break; - case IEEE80211_STA_AUTHORIZED: - if (sta->sta_state == IEEE80211_STA_ASSOC) { - ieee80211_vif_inc_num_mcast(sta->sdata); - set_bit(WLAN_STA_AUTHORIZED, &sta->_flags); - ieee80211_check_fast_xmit(sta); - ieee80211_check_fast_rx(sta); - } - if (sta->sdata->vif.type == NL80211_IFTYPE_AP_VLAN || - sta->sdata->vif.type == NL80211_IFTYPE_AP) - cfg80211_send_layer2_update(sta->sdata->dev, - sta->sta.addr); - break; - default: - break; - } - - sta->sta_state = new_state; - - return 0; -} - static struct ieee80211_sta_rx_stats * sta_get_last_rx_stats(struct sta_info *sta) { @@ -2691,7 +2720,8 @@ } if (!(sinfo->filled & BIT_ULL(NL80211_STA_INFO_TX_BITRATE)) && - !sta->sta.valid_links) { + !sta->sta.valid_links && + ieee80211_rate_valid(&sta->deflink.tx_stats.last_rate)) { sta_set_rate_info_tx(sta, &sta->deflink.tx_stats.last_rate, &sinfo->txrate); sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE); @@ -2803,6 +2833,10 @@ struct rate_control_ref *ref = NULL; u32 thr = 0; + /* first check for overrride */ + if (sta->deflink.pub->tp_override) + return sta->deflink.pub->tp_override; + if (test_sta_flag(sta, WLAN_STA_RATE_CONTROL)) ref = local->rate_ctrl; @@ -2852,7 +2886,9 @@ struct sta_link_alloc *alloc; int ret; - lockdep_assert_held(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); + + WARN_ON(!test_sta_flag(sta, WLAN_STA_INSERTED)); /* must represent an MLD from the start */ if (WARN_ON(!sta->sta.valid_links)) @@ -2881,7 +2917,9 @@ void ieee80211_sta_free_link(struct sta_info *sta, unsigned int link_id) { - lockdep_assert_held(&sta->sdata->local->sta_mtx); + lockdep_assert_wiphy(sta->sdata->local->hw.wiphy); + + WARN_ON(!test_sta_flag(sta, WLAN_STA_INSERTED)); sta_remove_link(sta, link_id, false); } @@ -2895,7 +2933,7 @@ int ret; link_sta = rcu_dereference_protected(sta->link[link_id], - lockdep_is_held(&sdata->local->sta_mtx)); + lockdep_is_held(&sdata->local->hw.wiphy->mtx)); if (WARN_ON(old_links == new_links || !link_sta)) return -EINVAL; @@ -2910,9 +2948,11 @@ sta->sta.valid_links = new_links; - if (!test_sta_flag(sta, WLAN_STA_INSERTED)) + if (WARN_ON(!test_sta_flag(sta, WLAN_STA_INSERTED))) goto hash; + ieee80211_recalc_min_chandef(sdata, link_id); + /* Ensure the values are updated for the driver, * redone by sta_remove_link on failure. */ @@ -2937,11 +2977,11 @@ struct ieee80211_sub_if_data *sdata = sta->sdata; u16 old_links = sta->sta.valid_links; - lockdep_assert_held(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); sta->sta.valid_links &= ~BIT(link_id); - if (test_sta_flag(sta, WLAN_STA_INSERTED)) + if (!WARN_ON(!test_sta_flag(sta, WLAN_STA_INSERTED))) drv_change_sta_links(sdata->local, sdata, &sta->sta, old_links, sta->sta.valid_links); @@ -2968,7 +3008,7 @@ WLAN_EXT_CAPA9_MAX_MSDU_IN_AMSDU_MSB) << 1; if (val) - sta->sta.max_amsdu_subframes = 4 << val; + sta->sta.max_amsdu_subframes = 4 << (4 - val); } #ifdef CONFIG_LOCKDEP @@ -2976,7 +3016,7 @@ { struct sta_info *sta = container_of(pubsta, struct sta_info, sta); - return lockdep_is_held(&sta->local->sta_mtx); + return lockdep_is_held(&sta->local->hw.wiphy->mtx); } EXPORT_SYMBOL(lockdep_sta_mutex_held); #endif diff -ruw linux-6.4/net/mac80211/sta_info.h linux-6.4-fbx/net/mac80211/sta_info.h --- linux-6.4/net/mac80211/sta_info.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/sta_info.h 2023-12-12 17:24:34.179627645 +0100 @@ -3,7 +3,7 @@ * Copyright 2002-2005, Devicescape Software, Inc. * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright(c) 2015-2017 Intel Deutschland GmbH - * Copyright(c) 2020-2022 Intel Corporation + * Copyright(c) 2020-2023 Intel Corporation */ #ifndef STA_INFO_H @@ -259,9 +259,6 @@ /** * struct sta_ampdu_mlme - STA aggregation information. * - * @mtx: mutex to protect all TX data (except non-NULL assignments - * to tid_tx[idx], which are protected by the sta spinlock) - * tid_start_tx is also protected by sta->lock. * @tid_rx: aggregation info for Rx per TID -- RCU protected * @tid_rx_token: dialog tokens for valid aggregation sessions * @tid_rx_timer_expired: bitmap indicating on which TIDs the @@ -275,13 +272,13 @@ * unexpected aggregation related frames outside a session * @work: work struct for starting/stopping aggregation * @tid_tx: aggregation info for Tx per TID - * @tid_start_tx: sessions where start was requested + * @tid_start_tx: sessions where start was requested, not just protected + * by wiphy mutex but also sta->lock * @last_addba_req_time: timestamp of the last addBA request. * @addba_req_num: number of times addBA request has been sent. * @dialog_token_allocator: dialog token enumerator for each new session; */ struct sta_ampdu_mlme { - struct mutex mtx; /* rx */ struct tid_ampdu_rx __rcu *tid_rx[IEEE80211_NUM_TIDS]; u8 tid_rx_token[IEEE80211_NUM_TIDS]; @@ -291,7 +288,7 @@ unsigned long agg_session_valid[BITS_TO_LONGS(IEEE80211_NUM_TIDS)]; unsigned long unexpected_agg[BITS_TO_LONGS(IEEE80211_NUM_TIDS)]; /* tx */ - struct work_struct work; + struct wiphy_work work; struct tid_ampdu_tx __rcu *tid_tx[IEEE80211_NUM_TIDS]; struct tid_ampdu_tx *tid_start_tx[IEEE80211_NUM_TIDS]; unsigned long last_addba_req_time[IEEE80211_NUM_TIDS]; @@ -618,8 +615,6 @@ * @sta: station information we share with the driver * @sta_state: duplicates information about station state (for debug) * @rcu_head: RCU head used for freeing this station struct - * @cur_max_bandwidth: maximum bandwidth to use for TX to the station, - * taken from HT/VHT capabilities or VHT operating mode notification * @cparams: CoDel parameters for this station. * @reserved_tid: reserved TID (if any, otherwise IEEE80211_TID_UNRESERVED) * @amsdu_mesh_control: track the mesh A-MSDU format used by the peer: @@ -702,6 +697,8 @@ struct airtime_info airtime[IEEE80211_NUM_ACS]; u16 airtime_weight; + u32 tp_override; + /* * Aggregation information, locked with lock. */ @@ -796,13 +793,10 @@ void ieee80211_assign_tid_tx(struct sta_info *sta, int tid, struct tid_ampdu_tx *tid_tx); -static inline struct tid_ampdu_tx * -rcu_dereference_protected_tid_tx(struct sta_info *sta, int tid) -{ - return rcu_dereference_protected(sta->ampdu_mlme.tid_tx[tid], - lockdep_is_held(&sta->lock) || - lockdep_is_held(&sta->ampdu_mlme.mtx)); -} +#define rcu_dereference_protected_tid_tx(sta, tid) \ + rcu_dereference_protected((sta)->ampdu_mlme.tid_tx[tid], \ + lockdep_is_held(&(sta)->lock) || \ + lockdep_is_held(&(sta)->local->hw.wiphy->mtx)); /* Maximum number of frames to buffer per power saving station per AC */ #define STA_MAX_TX_BUFFER 64 @@ -827,7 +821,7 @@ struct sta_info *sta_info_get_bss(struct ieee80211_sub_if_data *sdata, const u8 *addr); -/* user must hold sta_mtx or be in RCU critical section */ +/* user must hold wiphy mutex or be in RCU critical section */ struct sta_info *sta_info_get_by_addrs(struct ieee80211_local *local, const u8 *sta_addr, const u8 *vif_addr); diff -ruw linux-6.4/net/mac80211/status.c linux-6.4-fbx/net/mac80211/status.c --- linux-6.4/net/mac80211/status.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/status.c 2024-01-19 17:01:19.909848232 +0100 @@ -5,7 +5,7 @@ * Copyright 2006-2007 Jiri Benc * Copyright 2008-2010 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH - * Copyright 2021-2022 Intel Corporation + * Copyright 2021-2023 Intel Corporation */ #include @@ -17,6 +17,7 @@ #include "mesh.h" #include "led.h" #include "wme.h" +#include "fbx_scum.h" void ieee80211_tx_status_irqsafe(struct ieee80211_hw *hw, @@ -184,8 +185,6 @@ static void ieee80211_frame_acked(struct sta_info *sta, struct sk_buff *skb) { struct ieee80211_mgmt *mgmt = (void *) skb->data; - struct ieee80211_local *local = sta->local; - struct ieee80211_sub_if_data *sdata = sta->sdata; if (ieee80211_is_data_qos(mgmt->frame_control)) { struct ieee80211_hdr *hdr = (void *) skb->data; @@ -194,39 +193,6 @@ ieee80211_check_pending_bar(sta, hdr->addr1, tid); } - - if (ieee80211_is_action(mgmt->frame_control) && - !ieee80211_has_protected(mgmt->frame_control) && - mgmt->u.action.category == WLAN_CATEGORY_HT && - mgmt->u.action.u.ht_smps.action == WLAN_HT_ACTION_SMPS && - ieee80211_sdata_running(sdata)) { - enum ieee80211_smps_mode smps_mode; - - switch (mgmt->u.action.u.ht_smps.smps_control) { - case WLAN_HT_SMPS_CONTROL_DYNAMIC: - smps_mode = IEEE80211_SMPS_DYNAMIC; - break; - case WLAN_HT_SMPS_CONTROL_STATIC: - smps_mode = IEEE80211_SMPS_STATIC; - break; - case WLAN_HT_SMPS_CONTROL_DISABLED: - default: /* shouldn't happen since we don't send that */ - smps_mode = IEEE80211_SMPS_OFF; - break; - } - - if (sdata->vif.type == NL80211_IFTYPE_STATION) { - /* - * This update looks racy, but isn't -- if we come - * here we've definitely got a station that we're - * talking to, and on a managed interface that can - * only be the AP. And the only other place updating - * this variable in managed mode is before association. - */ - sdata->deflink.smps_mode = smps_mode; - ieee80211_queue_work(&local->hw, &sdata->recalc_smps); - } - } } static void ieee80211_set_bar_pending(struct sta_info *sta, u8 tid, u16 ssn) @@ -291,7 +257,7 @@ static void ieee80211_add_tx_radiotap_header(struct ieee80211_local *local, struct sk_buff *skb, int retry_count, - int rtap_len, int shift, + int rtap_len, struct ieee80211_tx_status *status) { struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); @@ -342,7 +308,7 @@ if (legacy_rate) { rthdr->it_present |= cpu_to_le32(BIT(IEEE80211_RADIOTAP_RATE)); - *pos = DIV_ROUND_UP(legacy_rate, 5 * (1 << shift)); + *pos = DIV_ROUND_UP(legacy_rate, 5); /* padding for tx flags */ pos += 2; } @@ -633,7 +599,7 @@ unsigned long flags; spin_lock_irqsave(&local->ack_status_lock, flags); - skb = idr_remove(&local->ack_status_frames, info->ack_frame_id); + skb = idr_remove(&local->ack_status_frames, info->status_data); spin_unlock_irqrestore(&local->ack_status_lock, flags); if (!skb) @@ -695,6 +661,42 @@ } } +static void ieee80211_handle_smps_status(struct ieee80211_sub_if_data *sdata, + bool acked, u16 status_data) +{ + u16 sub_data = u16_get_bits(status_data, IEEE80211_STATUS_SUBDATA_MASK); + enum ieee80211_smps_mode smps_mode = sub_data & 3; + int link_id = (sub_data >> 2); + struct ieee80211_link_data *link; + + if (!sdata || !ieee80211_sdata_running(sdata)) + return; + + if (!acked) + return; + + if (sdata->vif.type != NL80211_IFTYPE_STATION) + return; + + if (WARN(link_id >= ARRAY_SIZE(sdata->link), + "bad SMPS status link: %d\n", link_id)) + return; + + link = rcu_dereference(sdata->link[link_id]); + if (!link) + return; + + /* + * This update looks racy, but isn't, the only other place + * updating this variable is in managed mode before assoc, + * and we have to be associated to have a status from the + * action frame TX, since we cannot send it while we're not + * associated yet. + */ + link->smps_mode = smps_mode; + wiphy_work_queue(sdata->local->hw.wiphy, &link->u.mgd.recalc_smps); +} + static void ieee80211_report_used_skb(struct ieee80211_local *local, struct sk_buff *skb, bool dropped, ktime_t ack_hwtstamp) @@ -730,12 +732,9 @@ if (!sdata) { skb->dev = NULL; } else if (!dropped) { - unsigned int hdr_size = - ieee80211_hdrlen(hdr->frame_control); - /* Check to see if packet is a TDLS teardown packet */ if (ieee80211_is_data(hdr->frame_control) && - (ieee80211_get_tdls_action(skb, hdr_size) == + (ieee80211_get_tdls_action(skb) == WLAN_TDLS_TEARDOWN)) { ieee80211_tdls_td_tx_handle(local, sdata, skb, info->flags); @@ -747,7 +746,7 @@ if (qskb) { skb_queue_tail(&sdata->status_queue, qskb); - ieee80211_queue_work(&local->hw, + wiphy_work_queue(local->hw.wiphy, &sdata->work); } } @@ -759,9 +758,24 @@ } rcu_read_unlock(); - } else if (info->ack_frame_id) { + } else if (info->status_data_idr) { ieee80211_report_ack_skb(local, skb, acked, dropped, ack_hwtstamp); + } else if (info->status_data) { + struct ieee80211_sub_if_data *sdata; + + rcu_read_lock(); + + sdata = ieee80211_sdata_from_skb(local, skb); + + switch (u16_get_bits(info->status_data, + IEEE80211_STATUS_TYPE_MASK)) { + case IEEE80211_STATUS_TYPE_SMPS: + ieee80211_handle_smps_status(sdata, acked, + info->status_data); + break; + } + rcu_read_unlock(); } if (!dropped && skb->destructor) { @@ -862,7 +876,7 @@ } void ieee80211_tx_monitor(struct ieee80211_local *local, struct sk_buff *skb, - int retry_count, int shift, bool send_to_cooked, + int retry_count, bool send_to_cooked, struct ieee80211_tx_status *status) { struct sk_buff *skb2; @@ -879,7 +893,7 @@ return; } ieee80211_add_tx_radiotap_header(local, skb, retry_count, - rtap_len, shift, status); + rtap_len, status); /* XXX: is this sufficient for BPF? */ skb_reset_mac_header(skb); @@ -894,6 +908,9 @@ if (!ieee80211_sdata_running(sdata)) continue; + if (fbx80211_skip_mon(sdata)) + continue; + if ((sdata->u.mntr.flags & MONITOR_FLAG_COOK_FRAMES) && !send_to_cooked) continue; @@ -932,14 +949,14 @@ bool acked; bool noack_success; struct ieee80211_bar *bar; - int shift = 0; int tid = IEEE80211_NUM_TIDS; + bool ack_requested; + ack_requested = !(info->flags & IEEE80211_TX_CTL_NO_ACK); fc = hdr->frame_control; - if (status->sta) { + if (status->sta && ack_requested) { sta = container_of(status->sta, struct sta_info, sta); - shift = ieee80211_vif_get_shift(&sta->sdata->vif); if (info->flags & IEEE80211_TX_STATUS_EOSP) clear_sta_flag(sta, WLAN_STA_SP); @@ -1077,7 +1094,7 @@ } /* send to monitor interfaces */ - ieee80211_tx_monitor(local, skb, retry_count, shift, + ieee80211_tx_monitor(local, skb, retry_count, send_to_cooked, status); } @@ -1102,6 +1119,30 @@ } EXPORT_SYMBOL(ieee80211_tx_status); +void ieee80211_tx_status_8023(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + struct sk_buff *skb) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_tx_status status = { + .skb = skb, + .info = IEEE80211_SKB_CB(skb), + }; + struct sta_info *sta; + + sdata = vif_to_sdata(vif); + + rcu_read_lock(); + + if (!ieee80211_lookup_ra_sta(sdata, skb, &sta) && !IS_ERR(sta)) + status.sta = &sta->sta; + + ieee80211_tx_status_ext(hw, &status); + + rcu_read_unlock(); +} +EXPORT_SYMBOL(ieee80211_tx_status_8023); + void ieee80211_tx_status_ext(struct ieee80211_hw *hw, struct ieee80211_tx_status *status) { @@ -1113,6 +1154,7 @@ int rates_idx, retry_count; bool acked, noack_success, ack_signal_valid; u16 tx_time_est; + bool ack_requested; if (pubsta) { sta = container_of(pubsta, struct sta_info, sta); @@ -1139,12 +1181,13 @@ rates_idx = ieee80211_tx_get_rates(hw, info, &retry_count); + ack_requested = !(info->flags & IEEE80211_TX_CTL_NO_ACK); acked = !!(info->flags & IEEE80211_TX_STAT_ACK); noack_success = !!(info->flags & IEEE80211_TX_STAT_NOACK_TRANSMITTED); ack_signal_valid = !!(info->status.flags & IEEE80211_TX_STATUS_ACK_SIGNAL_VALID); - if (pubsta) { + if (pubsta && ack_requested) { struct ieee80211_sub_if_data *sdata = sta->sdata; if (!acked && !noack_success) diff -ruw linux-6.4/net/mac80211/tdls.c linux-6.4-fbx/net/mac80211/tdls.c --- linux-6.4/net/mac80211/tdls.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/tdls.c 2023-11-07 13:38:44.090257456 +0100 @@ -6,7 +6,7 @@ * Copyright 2014, Intel Corporation * Copyright 2014 Intel Mobile Communications GmbH * Copyright 2015 - 2016 Intel Deutschland GmbH - * Copyright (C) 2019, 2021-2022 Intel Corporation + * Copyright (C) 2019, 2021-2023 Intel Corporation */ #include @@ -21,7 +21,7 @@ /* give usermode some time for retries in setting up the TDLS session */ #define TDLS_PEER_SETUP_TIMEOUT (15 * HZ) -void ieee80211_tdls_peer_del_work(struct work_struct *wk) +void ieee80211_tdls_peer_del_work(struct wiphy *wiphy, struct wiphy_work *wk) { struct ieee80211_sub_if_data *sdata; struct ieee80211_local *local; @@ -30,18 +30,19 @@ u.mgd.tdls_peer_del_work.work); local = sdata->local; - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); + if (!is_zero_ether_addr(sdata->u.mgd.tdls_peer)) { tdls_dbg(sdata, "TDLS del peer %pM\n", sdata->u.mgd.tdls_peer); sta_info_destroy_addr(sdata, sdata->u.mgd.tdls_peer); eth_zero_addr(sdata->u.mgd.tdls_peer); } - mutex_unlock(&local->mtx); } -static void ieee80211_tdls_add_ext_capab(struct ieee80211_sub_if_data *sdata, +static void ieee80211_tdls_add_ext_capab(struct ieee80211_link_data *link, struct sk_buff *skb) { + struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_local *local = sdata->local; struct ieee80211_if_managed *ifmgd = &sdata->u.mgd; bool chan_switch = local->hw.wiphy->features & @@ -50,7 +51,7 @@ !ifmgd->tdls_wider_bw_prohibited; bool buffer_sta = ieee80211_hw_check(&local->hw, SUPPORTS_TDLS_BUFFER_STA); - struct ieee80211_supported_band *sband = ieee80211_get_sband(sdata); + struct ieee80211_supported_band *sband = ieee80211_get_link_sband(link); bool vht = sband && sband->vht_cap.vht_supported; u8 *pos = skb_put(skb, 10); @@ -152,13 +153,13 @@ *pos = 2 * subband_cnt; } -static void ieee80211_tdls_add_oper_classes(struct ieee80211_sub_if_data *sdata, +static void ieee80211_tdls_add_oper_classes(struct ieee80211_link_data *link, struct sk_buff *skb) { u8 *pos; u8 op_class; - if (!ieee80211_chandef_to_operating_class(&sdata->vif.bss_conf.chandef, + if (!ieee80211_chandef_to_operating_class(&link->conf->chandef, &op_class)) return; @@ -180,7 +181,7 @@ *pos++ = WLAN_BSS_COEX_INFORMATION_REQUEST; } -static u16 ieee80211_get_tdls_sta_capab(struct ieee80211_sub_if_data *sdata, +static u16 ieee80211_get_tdls_sta_capab(struct ieee80211_link_data *link, u16 status_code) { struct ieee80211_supported_band *sband; @@ -189,7 +190,8 @@ if (status_code != 0) return 0; - sband = ieee80211_get_sband(sdata); + sband = ieee80211_get_link_sband(link); + if (sband && sband->band == NL80211_BAND_2GHZ) { return WLAN_CAPABILITY_SHORT_SLOT_TIME | WLAN_CAPABILITY_SHORT_PREAMBLE; @@ -198,10 +200,11 @@ return 0; } -static void ieee80211_tdls_add_link_ie(struct ieee80211_sub_if_data *sdata, +static void ieee80211_tdls_add_link_ie(struct ieee80211_link_data *link, struct sk_buff *skb, const u8 *peer, bool initiator) { + struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_tdls_lnkie *lnkid; const u8 *init_addr, *rsp_addr; @@ -218,7 +221,7 @@ lnkid->ie_type = WLAN_EID_LINK_ID; lnkid->ie_len = sizeof(struct ieee80211_tdls_lnkie) - 2; - memcpy(lnkid->bssid, sdata->deflink.u.mgd.bssid, ETH_ALEN); + memcpy(lnkid->bssid, link->u.mgd.bssid, ETH_ALEN); memcpy(lnkid->init_sta, init_addr, ETH_ALEN); memcpy(lnkid->resp_sta, rsp_addr, ETH_ALEN); } @@ -306,7 +309,7 @@ struct sta_info *sta) { /* IEEE802.11ac-2013 Table E-4 */ - u16 centers_80mhz[] = { 5210, 5290, 5530, 5610, 5690, 5775 }; + static const u16 centers_80mhz[] = { 5210, 5290, 5530, 5610, 5690, 5775 }; struct cfg80211_chan_def uc = sta->tdls_chandef; enum nl80211_chan_width max_width = ieee80211_sta_cap_chan_bw(&sta->deflink); @@ -359,21 +362,24 @@ } static void -ieee80211_tdls_add_setup_start_ies(struct ieee80211_sub_if_data *sdata, +ieee80211_tdls_add_setup_start_ies(struct ieee80211_link_data *link, struct sk_buff *skb, const u8 *peer, u8 action_code, bool initiator, const u8 *extra_ies, size_t extra_ies_len) { + struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_supported_band *sband; struct ieee80211_local *local = sdata->local; struct ieee80211_sta_ht_cap ht_cap; struct ieee80211_sta_vht_cap vht_cap; + const struct ieee80211_sta_he_cap *he_cap; + const struct ieee80211_sta_eht_cap *eht_cap; struct sta_info *sta = NULL; size_t offset = 0, noffset; u8 *pos; - sband = ieee80211_get_sband(sdata); - if (!sband) + sband = ieee80211_get_link_sband(link); + if (WARN_ON_ONCE(!sband)) return; ieee80211_add_srates_ie(sdata, skb, false, sband->band); @@ -397,7 +403,7 @@ offset = noffset; } - ieee80211_tdls_add_ext_capab(sdata, skb); + ieee80211_tdls_add_ext_capab(link, skb); /* add the QoS element if we support it */ if (local->hw.queues >= IEEE80211_NUM_ACS && @@ -426,20 +432,16 @@ offset = noffset; } - mutex_lock(&local->sta_mtx); - /* we should have the peer STA if we're already responding */ if (action_code == WLAN_TDLS_SETUP_RESPONSE) { sta = sta_info_get(sdata, peer); - if (WARN_ON_ONCE(!sta)) { - mutex_unlock(&local->sta_mtx); + if (WARN_ON_ONCE(!sta)) return; - } - sta->tdls_chandef = sdata->vif.bss_conf.chandef; + sta->tdls_chandef = link->conf->chandef; } - ieee80211_tdls_add_oper_classes(sdata, skb); + ieee80211_tdls_add_oper_classes(link, skb); /* * with TDLS we can switch channels, and HT-caps are not necessarily @@ -472,7 +474,7 @@ (ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) ieee80211_tdls_add_bss_coex_ie(skb); - ieee80211_tdls_add_link_ie(sdata, skb, peer, initiator); + ieee80211_tdls_add_link_ie(link, skb, peer, initiator); /* add any custom IEs that go before VHT capabilities */ if (extra_ies_len) { @@ -497,17 +499,21 @@ offset = noffset; } - /* build the VHT-cap similarly to the HT-cap */ + /* add AID if VHT, HE or EHT capabilities supported */ memcpy(&vht_cap, &sband->vht_cap, sizeof(vht_cap)); + he_cap = ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); + eht_cap = ieee80211_get_eht_iftype_cap_vif(sband, &sdata->vif); + if ((vht_cap.vht_supported || he_cap || eht_cap) && + (action_code == WLAN_TDLS_SETUP_REQUEST || + action_code == WLAN_TDLS_SETUP_RESPONSE)) + ieee80211_tdls_add_aid(sdata, skb); + + /* build the VHT-cap similarly to the HT-cap */ if ((action_code == WLAN_TDLS_SETUP_REQUEST || action_code == WLAN_PUB_ACTION_TDLS_DISCOVER_RES) && vht_cap.vht_supported) { ieee80211_apply_vhtcap_overrides(sdata, &vht_cap); - /* the AID is present only when VHT is implemented */ - if (action_code == WLAN_TDLS_SETUP_REQUEST) - ieee80211_tdls_add_aid(sdata, skb); - pos = skb_put(skb, sizeof(struct ieee80211_vht_cap) + 2); ieee80211_ie_build_vht_cap(pos, &vht_cap, vht_cap.cap); } else if (action_code == WLAN_TDLS_SETUP_RESPONSE && @@ -515,9 +521,6 @@ /* the peer caps are already intersected with our own */ memcpy(&vht_cap, &sta->sta.deflink.vht_cap, sizeof(vht_cap)); - /* the AID is present only when VHT is implemented */ - ieee80211_tdls_add_aid(sdata, skb); - pos = skb_put(skb, sizeof(struct ieee80211_vht_cap) + 2); ieee80211_ie_build_vht_cap(pos, &vht_cap, vht_cap.cap); @@ -529,7 +532,80 @@ ieee80211_tdls_chandef_vht_upgrade(sdata, sta); } - mutex_unlock(&local->sta_mtx); + /* add any custom IEs that go before HE capabilities */ + if (extra_ies_len) { + static const u8 before_he_cap[] = { + WLAN_EID_EXTENSION, + WLAN_EID_EXT_FILS_REQ_PARAMS, + WLAN_EID_AP_CSN, + }; + noffset = ieee80211_ie_split(extra_ies, extra_ies_len, + before_he_cap, + ARRAY_SIZE(before_he_cap), + offset); + skb_put_data(skb, extra_ies + offset, noffset - offset); + offset = noffset; + } + + /* build the HE-cap from sband */ + if (he_cap && + (action_code == WLAN_TDLS_SETUP_REQUEST || + action_code == WLAN_TDLS_SETUP_RESPONSE || + action_code == WLAN_PUB_ACTION_TDLS_DISCOVER_RES)) { + __le16 he_6ghz_capa; + u8 cap_size; + + cap_size = + 2 + 1 + sizeof(he_cap->he_cap_elem) + + ieee80211_he_mcs_nss_size(&he_cap->he_cap_elem) + + ieee80211_he_ppe_size(he_cap->ppe_thres[0], + he_cap->he_cap_elem.phy_cap_info); + pos = skb_put(skb, cap_size); + pos = ieee80211_ie_build_he_cap(0, pos, he_cap, pos + cap_size); + + /* Build HE 6Ghz capa IE from sband */ + if (sband->band == NL80211_BAND_6GHZ) { + cap_size = 2 + 1 + sizeof(struct ieee80211_he_6ghz_capa); + pos = skb_put(skb, cap_size); + he_6ghz_capa = + ieee80211_get_he_6ghz_capa_vif(sband, &sdata->vif); + pos = ieee80211_write_he_6ghz_cap(pos, he_6ghz_capa, + pos + cap_size); + } + } + + /* add any custom IEs that go before EHT capabilities */ + if (extra_ies_len) { + static const u8 before_he_cap[] = { + WLAN_EID_EXTENSION, + WLAN_EID_EXT_FILS_REQ_PARAMS, + WLAN_EID_AP_CSN, + }; + + noffset = ieee80211_ie_split(extra_ies, extra_ies_len, + before_he_cap, + ARRAY_SIZE(before_he_cap), + offset); + skb_put_data(skb, extra_ies + offset, noffset - offset); + offset = noffset; + } + + /* build the EHT-cap from sband */ + if (he_cap && eht_cap && + (action_code == WLAN_TDLS_SETUP_REQUEST || + action_code == WLAN_TDLS_SETUP_RESPONSE || + action_code == WLAN_PUB_ACTION_TDLS_DISCOVER_RES)) { + u8 cap_size; + + cap_size = + 2 + 1 + sizeof(eht_cap->eht_cap_elem) + + ieee80211_eht_mcs_nss_size(&he_cap->he_cap_elem, + &eht_cap->eht_cap_elem, false) + + ieee80211_eht_ppe_size(eht_cap->eht_ppe_thres[0], + eht_cap->eht_cap_elem.phy_cap_info); + pos = skb_put(skb, cap_size); + ieee80211_ie_build_eht_cap(pos, he_cap, eht_cap, pos + cap_size, false); + } /* add any remaining IEs */ if (extra_ies_len) { @@ -540,31 +616,29 @@ } static void -ieee80211_tdls_add_setup_cfm_ies(struct ieee80211_sub_if_data *sdata, +ieee80211_tdls_add_setup_cfm_ies(struct ieee80211_link_data *link, struct sk_buff *skb, const u8 *peer, bool initiator, const u8 *extra_ies, size_t extra_ies_len) { + struct ieee80211_sub_if_data *sdata = link->sdata; struct ieee80211_local *local = sdata->local; size_t offset = 0, noffset; struct sta_info *sta, *ap_sta; struct ieee80211_supported_band *sband; u8 *pos; - sband = ieee80211_get_sband(sdata); - if (!sband) + sband = ieee80211_get_link_sband(link); + if (WARN_ON_ONCE(!sband)) return; - mutex_lock(&local->sta_mtx); - sta = sta_info_get(sdata, peer); - ap_sta = sta_info_get(sdata, sdata->deflink.u.mgd.bssid); - if (WARN_ON_ONCE(!sta || !ap_sta)) { - mutex_unlock(&local->sta_mtx); + ap_sta = sta_info_get(sdata, sdata->vif.cfg.ap_addr); + + if (WARN_ON_ONCE(!sta || !ap_sta)) return; - } - sta->tdls_chandef = sdata->vif.bss_conf.chandef; + sta->tdls_chandef = link->conf->chandef; /* add any custom IEs that go before the QoS IE */ if (extra_ies_len) { @@ -610,11 +684,11 @@ pos = skb_put(skb, 2 + sizeof(struct ieee80211_ht_operation)); ieee80211_ie_build_ht_oper(pos, &sta->sta.deflink.ht_cap, - &sdata->vif.bss_conf.chandef, prot, + &link->conf->chandef, prot, true); } - ieee80211_tdls_add_link_ie(sdata, skb, peer, initiator); + ieee80211_tdls_add_link_ie(link, skb, peer, initiator); /* only include VHT-operation if not on the 2.4GHz band */ if (sband->band != NL80211_BAND_2GHZ && @@ -631,8 +705,6 @@ &sta->tdls_chandef); } - mutex_unlock(&local->sta_mtx); - /* add any remaining IEs */ if (extra_ies_len) { noffset = extra_ies_len; @@ -641,7 +713,7 @@ } static void -ieee80211_tdls_add_chan_switch_req_ies(struct ieee80211_sub_if_data *sdata, +ieee80211_tdls_add_chan_switch_req_ies(struct ieee80211_link_data *link, struct sk_buff *skb, const u8 *peer, bool initiator, const u8 *extra_ies, size_t extra_ies_len, u8 oper_class, @@ -670,7 +742,7 @@ offset = noffset; } - ieee80211_tdls_add_link_ie(sdata, skb, peer, initiator); + ieee80211_tdls_add_link_ie(link, skb, peer, initiator); /* add any remaining IEs */ if (extra_ies_len) { @@ -680,20 +752,20 @@ } static void -ieee80211_tdls_add_chan_switch_resp_ies(struct ieee80211_sub_if_data *sdata, +ieee80211_tdls_add_chan_switch_resp_ies(struct ieee80211_link_data *link, struct sk_buff *skb, const u8 *peer, u16 status_code, bool initiator, const u8 *extra_ies, size_t extra_ies_len) { if (status_code == 0) - ieee80211_tdls_add_link_ie(sdata, skb, peer, initiator); + ieee80211_tdls_add_link_ie(link, skb, peer, initiator); if (extra_ies_len) skb_put_data(skb, extra_ies, extra_ies_len); } -static void ieee80211_tdls_add_ies(struct ieee80211_sub_if_data *sdata, +static void ieee80211_tdls_add_ies(struct ieee80211_link_data *link, struct sk_buff *skb, const u8 *peer, u8 action_code, u16 status_code, bool initiator, const u8 *extra_ies, @@ -705,7 +777,8 @@ case WLAN_TDLS_SETUP_RESPONSE: case WLAN_PUB_ACTION_TDLS_DISCOVER_RES: if (status_code == 0) - ieee80211_tdls_add_setup_start_ies(sdata, skb, peer, + ieee80211_tdls_add_setup_start_ies(link, + skb, peer, action_code, initiator, extra_ies, @@ -713,7 +786,7 @@ break; case WLAN_TDLS_SETUP_CONFIRM: if (status_code == 0) - ieee80211_tdls_add_setup_cfm_ies(sdata, skb, peer, + ieee80211_tdls_add_setup_cfm_ies(link, skb, peer, initiator, extra_ies, extra_ies_len); break; @@ -722,16 +795,17 @@ if (extra_ies_len) skb_put_data(skb, extra_ies, extra_ies_len); if (status_code == 0 || action_code == WLAN_TDLS_TEARDOWN) - ieee80211_tdls_add_link_ie(sdata, skb, peer, initiator); + ieee80211_tdls_add_link_ie(link, skb, + peer, initiator); break; case WLAN_TDLS_CHANNEL_SWITCH_REQUEST: - ieee80211_tdls_add_chan_switch_req_ies(sdata, skb, peer, + ieee80211_tdls_add_chan_switch_req_ies(link, skb, peer, initiator, extra_ies, extra_ies_len, oper_class, chandef); break; case WLAN_TDLS_CHANNEL_SWITCH_RESPONSE: - ieee80211_tdls_add_chan_switch_resp_ies(sdata, skb, peer, + ieee80211_tdls_add_chan_switch_resp_ies(link, skb, peer, status_code, initiator, extra_ies, extra_ies_len); @@ -742,6 +816,7 @@ static int ieee80211_prep_tdls_encap_data(struct wiphy *wiphy, struct net_device *dev, + struct ieee80211_link_data *link, const u8 *peer, u8 action_code, u8 dialog_token, u16 status_code, struct sk_buff *skb) { @@ -766,7 +841,7 @@ skb_put(skb, sizeof(tf->u.setup_req)); tf->u.setup_req.dialog_token = dialog_token; tf->u.setup_req.capability = - cpu_to_le16(ieee80211_get_tdls_sta_capab(sdata, + cpu_to_le16(ieee80211_get_tdls_sta_capab(link, status_code)); break; case WLAN_TDLS_SETUP_RESPONSE: @@ -777,7 +852,7 @@ tf->u.setup_resp.status_code = cpu_to_le16(status_code); tf->u.setup_resp.dialog_token = dialog_token; tf->u.setup_resp.capability = - cpu_to_le16(ieee80211_get_tdls_sta_capab(sdata, + cpu_to_le16(ieee80211_get_tdls_sta_capab(link, status_code)); break; case WLAN_TDLS_SETUP_CONFIRM: @@ -824,7 +899,8 @@ static int ieee80211_prep_tdls_direct(struct wiphy *wiphy, struct net_device *dev, - const u8 *peer, u8 action_code, u8 dialog_token, + const u8 *peer, struct ieee80211_link_data *link, + u8 action_code, u8 dialog_token, u16 status_code, struct sk_buff *skb) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); @@ -833,8 +909,7 @@ mgmt = skb_put_zero(skb, 24); memcpy(mgmt->da, peer, ETH_ALEN); memcpy(mgmt->sa, sdata->vif.addr, ETH_ALEN); - memcpy(mgmt->bssid, sdata->deflink.u.mgd.bssid, ETH_ALEN); - + memcpy(mgmt->bssid, link->u.mgd.bssid, ETH_ALEN); mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_ACTION); @@ -847,7 +922,7 @@ mgmt->u.action.u.tdls_discover_resp.dialog_token = dialog_token; mgmt->u.action.u.tdls_discover_resp.capability = - cpu_to_le16(ieee80211_get_tdls_sta_capab(sdata, + cpu_to_le16(ieee80211_get_tdls_sta_capab(link, status_code)); break; default: @@ -859,15 +934,23 @@ static struct sk_buff * ieee80211_tdls_build_mgmt_packet_data(struct ieee80211_sub_if_data *sdata, - const u8 *peer, u8 action_code, - u8 dialog_token, u16 status_code, - bool initiator, const u8 *extra_ies, - size_t extra_ies_len, u8 oper_class, + const u8 *peer, int link_id, + u8 action_code, u8 dialog_token, + u16 status_code, bool initiator, + const u8 *extra_ies, size_t extra_ies_len, + u8 oper_class, struct cfg80211_chan_def *chandef) { struct ieee80211_local *local = sdata->local; struct sk_buff *skb; int ret; + struct ieee80211_link_data *link; + + link_id = link_id >= 0 ? link_id : 0; + rcu_read_lock(); + link = rcu_dereference(sdata->link[link_id]); + if (WARN_ON(!link)) + goto unlock; skb = netdev_alloc_skb(sdata->dev, local->hw.extra_tx_headroom + @@ -880,6 +963,13 @@ sizeof(struct ieee80211_ht_operation)) + 2 + max(sizeof(struct ieee80211_vht_cap), sizeof(struct ieee80211_vht_operation)) + + 2 + 1 + sizeof(struct ieee80211_he_cap_elem) + + sizeof(struct ieee80211_he_mcs_nss_supp) + + IEEE80211_HE_PPE_THRES_MAX_LEN + + 2 + 1 + sizeof(struct ieee80211_he_6ghz_capa) + + 2 + 1 + sizeof(struct ieee80211_eht_cap_elem) + + sizeof(struct ieee80211_eht_mcs_nss_supp) + + IEEE80211_EHT_PPE_THRES_MAX_LEN + 50 + /* supported channels */ 3 + /* 40/20 BSS coex */ 4 + /* AID */ @@ -887,7 +977,7 @@ extra_ies_len + sizeof(struct ieee80211_tdls_lnkie)); if (!skb) - return NULL; + goto unlock; skb_reserve(skb, local->hw.extra_tx_headroom); @@ -900,13 +990,13 @@ case WLAN_TDLS_CHANNEL_SWITCH_REQUEST: case WLAN_TDLS_CHANNEL_SWITCH_RESPONSE: ret = ieee80211_prep_tdls_encap_data(local->hw.wiphy, - sdata->dev, peer, + sdata->dev, link, peer, action_code, dialog_token, status_code, skb); break; case WLAN_PUB_ACTION_TDLS_DISCOVER_RES: ret = ieee80211_prep_tdls_direct(local->hw.wiphy, sdata->dev, - peer, action_code, + peer, link, action_code, dialog_token, status_code, skb); break; @@ -918,19 +1008,23 @@ if (ret < 0) goto fail; - ieee80211_tdls_add_ies(sdata, skb, peer, action_code, status_code, + ieee80211_tdls_add_ies(link, skb, peer, action_code, status_code, initiator, extra_ies, extra_ies_len, oper_class, chandef); + rcu_read_unlock(); return skb; fail: dev_kfree_skb(skb); +unlock: + rcu_read_unlock(); return NULL; } static int ieee80211_tdls_prep_mgmt_packet(struct wiphy *wiphy, struct net_device *dev, - const u8 *peer, u8 action_code, u8 dialog_token, + const u8 *peer, int link_id, + u8 action_code, u8 dialog_token, u16 status_code, u32 peer_capability, bool initiator, const u8 *extra_ies, size_t extra_ies_len, u8 oper_class, @@ -988,7 +1082,8 @@ if (ret < 0) goto fail; - skb = ieee80211_tdls_build_mgmt_packet_data(sdata, peer, action_code, + skb = ieee80211_tdls_build_mgmt_packet_data(sdata, peer, + link_id, action_code, dialog_token, status_code, initiator, extra_ies, extra_ies_len, oper_class, @@ -999,7 +1094,7 @@ } if (action_code == WLAN_PUB_ACTION_TDLS_DISCOVER_RES) { - ieee80211_tx_skb(sdata, skb); + ieee80211_tx_skb_tid(sdata, skb, 7, link_id); return 0; } @@ -1066,7 +1161,8 @@ static int ieee80211_tdls_mgmt_setup(struct wiphy *wiphy, struct net_device *dev, - const u8 *peer, u8 action_code, u8 dialog_token, + const u8 *peer, int link_id, + u8 action_code, u8 dialog_token, u16 status_code, u32 peer_capability, bool initiator, const u8 *extra_ies, size_t extra_ies_len) { @@ -1084,7 +1180,7 @@ return -ENOTSUPP; } - mutex_lock(&local->mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* we don't support concurrent TDLS peer setups */ if (!is_zero_ether_addr(sdata->u.mgd.tdls_peer) && @@ -1112,34 +1208,32 @@ ieee80211_flush_queues(local, sdata, false); memcpy(sdata->u.mgd.tdls_peer, peer, ETH_ALEN); - mutex_unlock(&local->mtx); /* we cannot take the mutex while preparing the setup packet */ - ret = ieee80211_tdls_prep_mgmt_packet(wiphy, dev, peer, action_code, + ret = ieee80211_tdls_prep_mgmt_packet(wiphy, dev, peer, + link_id, action_code, dialog_token, status_code, peer_capability, initiator, extra_ies, extra_ies_len, 0, NULL); if (ret < 0) { - mutex_lock(&local->mtx); eth_zero_addr(sdata->u.mgd.tdls_peer); - mutex_unlock(&local->mtx); return ret; } - ieee80211_queue_delayed_work(&sdata->local->hw, + wiphy_delayed_work_queue(sdata->local->hw.wiphy, &sdata->u.mgd.tdls_peer_del_work, TDLS_PEER_SETUP_TIMEOUT); return 0; out_unlock: - mutex_unlock(&local->mtx); return ret; } static int ieee80211_tdls_mgmt_teardown(struct wiphy *wiphy, struct net_device *dev, - const u8 *peer, u8 action_code, u8 dialog_token, + const u8 *peer, int link_id, + u8 action_code, u8 dialog_token, u16 status_code, u32 peer_capability, bool initiator, const u8 *extra_ies, size_t extra_ies_len) @@ -1159,7 +1253,8 @@ IEEE80211_QUEUE_STOP_REASON_TDLS_TEARDOWN); ieee80211_flush_queues(local, sdata, false); - ret = ieee80211_tdls_prep_mgmt_packet(wiphy, dev, peer, action_code, + ret = ieee80211_tdls_prep_mgmt_packet(wiphy, dev, peer, + link_id, action_code, dialog_token, status_code, peer_capability, initiator, extra_ies, extra_ies_len, 0, @@ -1185,10 +1280,10 @@ } int ieee80211_tdls_mgmt(struct wiphy *wiphy, struct net_device *dev, - const u8 *peer, u8 action_code, u8 dialog_token, - u16 status_code, u32 peer_capability, - bool initiator, const u8 *extra_ies, - size_t extra_ies_len) + const u8 *peer, int link_id, + u8 action_code, u8 dialog_token, u16 status_code, + u32 peer_capability, bool initiator, + const u8 *extra_ies, size_t extra_ies_len) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); int ret; @@ -1204,13 +1299,14 @@ switch (action_code) { case WLAN_TDLS_SETUP_REQUEST: case WLAN_TDLS_SETUP_RESPONSE: - ret = ieee80211_tdls_mgmt_setup(wiphy, dev, peer, action_code, + ret = ieee80211_tdls_mgmt_setup(wiphy, dev, peer, + link_id, action_code, dialog_token, status_code, peer_capability, initiator, extra_ies, extra_ies_len); break; case WLAN_TDLS_TEARDOWN: - ret = ieee80211_tdls_mgmt_teardown(wiphy, dev, peer, + ret = ieee80211_tdls_mgmt_teardown(wiphy, dev, peer, link_id, action_code, dialog_token, status_code, peer_capability, initiator, @@ -1222,13 +1318,13 @@ * response frame. It is transmitted directly and not buffered * by the AP. */ - drv_mgd_protect_tdls_discover(sdata->local, sdata); + drv_mgd_protect_tdls_discover(sdata->local, sdata, link_id); fallthrough; case WLAN_TDLS_SETUP_CONFIRM: case WLAN_PUB_ACTION_TDLS_DISCOVER_RES: /* no special handling */ ret = ieee80211_tdls_prep_mgmt_packet(wiphy, dev, peer, - action_code, + link_id, action_code, dialog_token, status_code, peer_capability, @@ -1240,8 +1336,8 @@ break; } - tdls_dbg(sdata, "TDLS mgmt action %d peer %pM status %d\n", - action_code, peer, ret); + tdls_dbg(sdata, "TDLS mgmt action %d peer %pM link_id %d status %d\n", + action_code, peer, link_id, ret); return ret; } @@ -1254,9 +1350,10 @@ enum nl80211_chan_width width; struct ieee80211_supported_band *sband; - mutex_lock(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + conf = rcu_dereference_protected(sdata->vif.bss_conf.chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (conf) { width = conf->def.width; sband = local->hw.wiphy->bands[conf->def.chan->band]; @@ -1284,7 +1381,6 @@ } } - mutex_unlock(&local->chanctx_mtx); } static int iee80211_tdls_have_ht_peers(struct ieee80211_sub_if_data *sdata) @@ -1347,6 +1443,8 @@ struct ieee80211_local *local = sdata->local; int ret; + lockdep_assert_wiphy(local->hw.wiphy); + if (!(wiphy->flags & WIPHY_FLAG_SUPPORTS_TDLS)) return -ENOTSUPP; @@ -1367,35 +1465,26 @@ /* protect possible bss_conf changes and avoid concurrency in * ieee80211_bss_info_change_notify() */ - sdata_lock(sdata); - mutex_lock(&local->mtx); tdls_dbg(sdata, "TDLS oper %d peer %pM\n", oper, peer); switch (oper) { case NL80211_TDLS_ENABLE_LINK: if (sdata->vif.bss_conf.csa_active) { tdls_dbg(sdata, "TDLS: disallow link during CSA\n"); - ret = -EBUSY; - break; + return -EBUSY; } - mutex_lock(&local->sta_mtx); sta = sta_info_get(sdata, peer); - if (!sta) { - mutex_unlock(&local->sta_mtx); - ret = -ENOLINK; - break; - } + if (!sta) + return -ENOLINK; iee80211_tdls_recalc_chanctx(sdata, sta); iee80211_tdls_recalc_ht_protection(sdata, sta); set_sta_flag(sta, WLAN_STA_TDLS_PEER_AUTH); - mutex_unlock(&local->sta_mtx); WARN_ON_ONCE(is_zero_ether_addr(sdata->u.mgd.tdls_peer) || !ether_addr_equal(sdata->u.mgd.tdls_peer, peer)); - ret = 0; break; case NL80211_TDLS_DISABLE_LINK: /* @@ -1414,29 +1503,26 @@ ret = sta_info_destroy_addr(sdata, peer); - mutex_lock(&local->sta_mtx); iee80211_tdls_recalc_ht_protection(sdata, NULL); - mutex_unlock(&local->sta_mtx); iee80211_tdls_recalc_chanctx(sdata, NULL); + if (ret) + return ret; break; default: - ret = -ENOTSUPP; - break; + return -ENOTSUPP; } - if (ret == 0 && ether_addr_equal(sdata->u.mgd.tdls_peer, peer)) { - cancel_delayed_work(&sdata->u.mgd.tdls_peer_del_work); + if (ether_addr_equal(sdata->u.mgd.tdls_peer, peer)) { + wiphy_delayed_work_cancel(sdata->local->hw.wiphy, + &sdata->u.mgd.tdls_peer_del_work); eth_zero_addr(sdata->u.mgd.tdls_peer); } - if (ret == 0) - ieee80211_queue_work(&sdata->local->hw, + wiphy_work_queue(sdata->local->hw.wiphy, &sdata->deflink.u.mgd.request_smps_work); - mutex_unlock(&local->mtx); - sdata_unlock(sdata); - return ret; + return 0; } void ieee80211_tdls_oper_request(struct ieee80211_vif *vif, const u8 *peer, @@ -1497,6 +1583,7 @@ int extra_ies_len = 2 + sizeof(struct ieee80211_ch_switch_timing); u8 *pos = extra_ies; struct sk_buff *skb; + int link_id = sta->sta.valid_links ? ffs(sta->sta.valid_links) - 1 : 0; /* * if chandef points to a wide channel add a Secondary-Channel @@ -1524,6 +1611,7 @@ iee80211_tdls_add_ch_switch_timing(pos, 0, 0); skb = ieee80211_tdls_build_mgmt_packet_data(sdata, sta->sta.addr, + link_id, WLAN_TDLS_CHANNEL_SWITCH_REQUEST, 0, 0, !sta->sta.tdls_initiator, extra_ies, extra_ies_len, @@ -1567,11 +1655,12 @@ u32 ch_sw_tm_ie; int ret; + lockdep_assert_wiphy(local->hw.wiphy); + if (chandef->chan->freq_offset) /* this may work, but is untested */ return -EOPNOTSUPP; - mutex_lock(&local->sta_mtx); sta = sta_info_get(sdata, addr); if (!sta) { tdls_dbg(sdata, @@ -1601,7 +1690,6 @@ set_sta_flag(sta, WLAN_STA_TDLS_OFF_CHANNEL); out: - mutex_unlock(&local->sta_mtx); dev_kfree_skb_any(skb); return ret; } @@ -1615,26 +1703,24 @@ struct ieee80211_local *local = sdata->local; struct sta_info *sta; - mutex_lock(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + sta = sta_info_get(sdata, addr); if (!sta) { tdls_dbg(sdata, "Invalid TDLS peer %pM for channel switch cancel\n", addr); - goto out; + return; } if (!test_sta_flag(sta, WLAN_STA_TDLS_OFF_CHANNEL)) { tdls_dbg(sdata, "TDLS channel switch not initiated by %pM\n", addr); - goto out; + return; } drv_tdls_cancel_channel_switch(local, sdata, &sta->sta); clear_sta_flag(sta, WLAN_STA_TDLS_OFF_CHANNEL); - -out: - mutex_unlock(&local->sta_mtx); } static struct sk_buff * @@ -1644,11 +1730,13 @@ struct ieee80211_sub_if_data *sdata = sta->sdata; struct sk_buff *skb; u8 extra_ies[2 + sizeof(struct ieee80211_ch_switch_timing)]; + int link_id = sta->sta.valid_links ? ffs(sta->sta.valid_links) - 1 : 0; /* initial timing are always zero in the template */ iee80211_tdls_add_ch_switch_timing(extra_ies, 0, 0); skb = ieee80211_tdls_build_mgmt_packet_data(sdata, sta->sta.addr, + link_id, WLAN_TDLS_CHANNEL_SWITCH_RESPONSE, 0, 0, !sta->sta.tdls_initiator, extra_ies, sizeof(extra_ies), 0, NULL); @@ -1694,6 +1782,8 @@ struct ieee80211_tdls_ch_sw_params params = {}; int ret; + lockdep_assert_wiphy(local->hw.wiphy); + params.action_code = WLAN_TDLS_CHANNEL_SWITCH_RESPONSE; params.timestamp = rx_status->device_timestamp; @@ -1703,7 +1793,6 @@ return -EINVAL; } - mutex_lock(&local->sta_mtx); sta = sta_info_get(sdata, tf->sa); if (!sta || !test_sta_flag(sta, WLAN_STA_TDLS_PEER_AUTH)) { tdls_dbg(sdata, "TDLS chan switch from non-peer sta %pM\n", @@ -1766,7 +1855,6 @@ tf->sa, params.status); out: - mutex_unlock(&local->sta_mtx); dev_kfree_skb_any(params.tmpl_skb); kfree(elems); return ret; @@ -1792,6 +1880,8 @@ struct ieee80211_tdls_ch_sw_params params = {}; int ret = 0; + lockdep_assert_wiphy(local->hw.wiphy); + params.action_code = WLAN_TDLS_CHANNEL_SWITCH_REQUEST; params.timestamp = rx_status->device_timestamp; @@ -1880,7 +1970,6 @@ goto free; } - mutex_lock(&local->sta_mtx); sta = sta_info_get(sdata, tf->sa); if (!sta || !test_sta_flag(sta, WLAN_STA_TDLS_PEER_AUTH)) { tdls_dbg(sdata, "TDLS chan switch from non-peer sta %pM\n", @@ -1927,7 +2016,6 @@ tf->sa, params.chandef->chan->center_freq, params.chandef->width); out: - mutex_unlock(&local->sta_mtx); dev_kfree_skb_any(params.tmpl_skb); free: kfree(elems); diff -ruw linux-6.4/net/mac80211/trace.h linux-6.4-fbx/net/mac80211/trace.h --- linux-6.4/net/mac80211/trace.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/trace.h 2023-11-07 13:38:44.090257456 +0100 @@ -2,7 +2,7 @@ /* * Portions of this file * Copyright(c) 2016-2017 Intel Deutschland GmbH - * Copyright (C) 2018 - 2022 Intel Corporation + * Copyright (C) 2018 - 2023 Intel Corporation */ #if !defined(__MAC80211_DRIVER_TRACE) || defined(TRACE_HEADER_MULTI_READ) @@ -17,7 +17,7 @@ #define MAXNAME 32 #define LOCAL_ENTRY __array(char, wiphy_name, 32) -#define LOCAL_ASSIGN strlcpy(__entry->wiphy_name, wiphy_name(local->hw.wiphy), MAXNAME) +#define LOCAL_ASSIGN strscpy(__entry->wiphy_name, wiphy_name(local->hw.wiphy), MAXNAME) #define LOCAL_PR_FMT "%s" #define LOCAL_PR_ARG __entry->wiphy_name @@ -634,6 +634,7 @@ LOCAL_ENTRY VIF_ENTRY STA_ENTRY + __field(u32, cmd) KEY_ENTRY ), @@ -641,12 +642,13 @@ LOCAL_ASSIGN; VIF_ASSIGN; STA_ASSIGN; + __entry->cmd = cmd; KEY_ASSIGN(key); ), TP_printk( - LOCAL_PR_FMT VIF_PR_FMT STA_PR_FMT KEY_PR_FMT, - LOCAL_PR_ARG, VIF_PR_ARG, STA_PR_ARG, KEY_PR_ARG + LOCAL_PR_FMT VIF_PR_FMT STA_PR_FMT " cmd: %d" KEY_PR_FMT, + LOCAL_PR_ARG, VIF_PR_ARG, STA_PR_ARG, __entry->cmd, KEY_PR_ARG ) ); @@ -2837,23 +2839,26 @@ ); TRACE_EVENT(api_chswitch_done, - TP_PROTO(struct ieee80211_sub_if_data *sdata, bool success), + TP_PROTO(struct ieee80211_sub_if_data *sdata, bool success, + unsigned int link_id), - TP_ARGS(sdata, success), + TP_ARGS(sdata, success, link_id), TP_STRUCT__entry( VIF_ENTRY __field(bool, success) + __field(unsigned int, link_id) ), TP_fast_assign( VIF_ASSIGN; __entry->success = success; + __entry->link_id = link_id; ), TP_printk( - VIF_PR_FMT " success=%d", - VIF_PR_ARG, __entry->success + VIF_PR_FMT " success=%d link_id=%d", + VIF_PR_ARG, __entry->success, __entry->link_id ) ); diff -ruw linux-6.4/net/mac80211/tx.c linux-6.4-fbx/net/mac80211/tx.c --- linux-6.4/net/mac80211/tx.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/tx.c 2024-03-18 14:40:14.879742098 +0100 @@ -26,6 +26,7 @@ #include #include #include +#include #include "ieee80211_i.h" #include "driver-ops.h" @@ -42,7 +43,7 @@ struct sk_buff *skb, int group_addr, int next_frag_len) { - int rate, mrate, erp, dur, i, shift = 0; + int rate, mrate, erp, dur, i; struct ieee80211_rate *txrate; struct ieee80211_local *local = tx->local; struct ieee80211_supported_band *sband; @@ -57,10 +58,8 @@ rcu_read_lock(); chanctx_conf = rcu_dereference(tx->sdata->vif.bss_conf.chanctx_conf); - if (chanctx_conf) { - shift = ieee80211_chandef_get_shift(&chanctx_conf->def); + if (chanctx_conf) rate_flags = ieee80211_chandef_rate_flags(&chanctx_conf->def); - } rcu_read_unlock(); /* uh huh? */ @@ -142,7 +141,7 @@ continue; if (tx->sdata->vif.bss_conf.basic_rates & BIT(i)) - rate = DIV_ROUND_UP(r->bitrate, 1 << shift); + rate = r->bitrate; switch (sband->band) { case NL80211_BAND_2GHZ: @@ -172,7 +171,7 @@ if (rate == -1) { /* No matching basic rate found; use highest suitable mandatory * PHY rate */ - rate = DIV_ROUND_UP(mrate, 1 << shift); + rate = mrate; } /* Don't calculate ACKs for QoS Frames with NoAck Policy set */ @@ -184,8 +183,7 @@ * (10 bytes + 4-byte FCS = 112 bits) plus SIFS; rounded up * to closest integer */ dur = ieee80211_frame_duration(sband->band, 10, rate, erp, - tx->sdata->vif.bss_conf.use_short_preamble, - shift); + tx->sdata->vif.bss_conf.use_short_preamble); if (next_frag_len) { /* Frame is fragmented: duration increases with time needed to @@ -194,8 +192,7 @@ /* next fragment */ dur += ieee80211_frame_duration(sband->band, next_frag_len, txrate->bitrate, erp, - tx->sdata->vif.bss_conf.use_short_preamble, - shift); + tx->sdata->vif.bss_conf.use_short_preamble); } return cpu_to_le16(dur); @@ -265,7 +262,7 @@ IEEE80211_QUEUE_STOP_REASON_PS, false); ifmgd->flags &= ~IEEE80211_STA_NULLFUNC_ACKED; - ieee80211_queue_work(&local->hw, + wiphy_work_queue(local->hw.wiphy, &local->dynamic_ps_disable_work); } @@ -581,25 +578,9 @@ { struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx->skb->data; struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx->skb); - enum { - USE_NONE, - USE_MGMT_KEY, - USE_MCAST_KEY, - } which_key = USE_NONE; struct ieee80211_link_data *link; unsigned int link_id; - if (ieee80211_is_group_privacy_action(tx->skb)) - which_key = USE_MCAST_KEY; - else if (ieee80211_is_mgmt(hdr->frame_control) && - is_multicast_ether_addr(hdr->addr1) && - ieee80211_is_robust_mgmt_frame(tx->skb)) - which_key = USE_MGMT_KEY; - else if (is_multicast_ether_addr(hdr->addr1)) - which_key = USE_MCAST_KEY; - else - return NULL; - link_id = u32_get_bits(info->control.flags, IEEE80211_TX_CTRL_MLO_LINK); if (link_id == IEEE80211_LINK_UNSPECIFIED) { link = &tx->sdata->deflink; @@ -609,14 +590,14 @@ return NULL; } - switch (which_key) { - case USE_NONE: - break; - case USE_MGMT_KEY: + if (ieee80211_is_group_privacy_action(tx->skb)) + return rcu_dereference(link->default_multicast_key); + else if (ieee80211_is_mgmt(hdr->frame_control) && + is_multicast_ether_addr(hdr->addr1) && + ieee80211_is_robust_mgmt_frame(tx->skb)) return rcu_dereference(link->default_mgmt_key); - case USE_MCAST_KEY: + else if (is_multicast_ether_addr(hdr->addr1)) return rcu_dereference(link->default_multicast_key); - } return NULL; } @@ -680,7 +661,8 @@ } if (unlikely(tx->key && tx->key->flags & KEY_FLAG_TAINTED && - !ieee80211_is_deauth(hdr->frame_control))) + !ieee80211_is_deauth(hdr->frame_control)) && + tx->skb->protocol != tx->sdata->control_port_protocol) return TX_DROP; if (!skip_hw && tx->key && @@ -860,7 +842,7 @@ /* SNS11 from 802.11be 10.3.2.14 */ if (unlikely(is_multicast_ether_addr(hdr->addr1) && - info->control.vif->valid_links && + ieee80211_vif_is_mld(info->control.vif) && info->control.vif->type == NL80211_IFTYPE_AP)) { if (info->control.flags & IEEE80211_TX_CTRL_MCAST_MLO_FIRST_TX) tx->sdata->mld_mcast_seq += 0x10; @@ -1320,6 +1302,9 @@ (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) return NULL; + if (unlikely(ieee80211_is_ctl(hdr->frame_control))) + return NULL; + if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && unlikely(!ieee80211_is_data_present(hdr->frame_control))) { if ((!ieee80211_is_mgmt(hdr->frame_control) || @@ -2181,6 +2166,11 @@ rate_found = true; break; + case IEEE80211_RADIOTAP_ANTENNA: + /* this can appear multiple times, keep a bitmap */ + info->control.antennas |= BIT(*iterator.this_arg); + break; + case IEEE80211_RADIOTAP_DATA_RETRIES: rate_retries = *iterator.this_arg; break; @@ -2275,8 +2265,17 @@ } if (rate_flags & IEEE80211_TX_RC_MCS) { + /* reset antennas if not enough */ + if (IEEE80211_HT_MCS_CHAINS(rate) > + hweight8(info->control.antennas)) + info->control.antennas = 0; + info->control.rates[0].idx = rate; } else if (rate_flags & IEEE80211_TX_RC_VHT_MCS) { + /* reset antennas if not enough */ + if (vht_nss > hweight8(info->control.antennas)) + info->control.antennas = 0; + ieee80211_rate_set_vht(info->control.rates, vht_mcs, vht_nss); } else if (sband) { @@ -2626,7 +2625,7 @@ ethertype = (skb->data[12] << 8) | skb->data[13]; fc = cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_DATA); - if (!sdata->vif.valid_links) + if (!ieee80211_vif_is_mld(&sdata->vif)) chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf); @@ -2643,7 +2642,7 @@ authorized = test_sta_flag(sta, WLAN_STA_AUTHORIZED); wme_sta = sta->sta.wme; } - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { struct ieee80211_sub_if_data *ap_sdata; /* override chanctx_conf from AP (we don't have one) */ @@ -2661,7 +2660,7 @@ /* DA BSSID SA */ memcpy(hdr.addr1, skb->data, ETH_ALEN); - if (sdata->vif.valid_links && sta && !sta->sta.mlo) { + if (ieee80211_vif_is_mld(&sdata->vif) && sta && !sta->sta.mlo) { struct ieee80211_link_data *link; link_id = sta->deflink.link_id; @@ -2769,10 +2768,20 @@ tdls_peer = test_sta_flag(sta, WLAN_STA_TDLS_PEER); if (tdls_peer) { + /* For TDLS only one link can be valid with peer STA */ + int tdls_link_id = sta->sta.valid_links ? + __ffs(sta->sta.valid_links) : 0; + struct ieee80211_link_data *link; + /* DA SA BSSID */ memcpy(hdr.addr1, skb->data, ETH_ALEN); memcpy(hdr.addr2, skb->data + ETH_ALEN, ETH_ALEN); - memcpy(hdr.addr3, sdata->deflink.u.mgd.bssid, ETH_ALEN); + link = rcu_dereference(sdata->link[tdls_link_id]); + if (WARN_ON_ONCE(!link)) { + ret = -EINVAL; + goto free; + } + memcpy(hdr.addr3, link->u.mgd.bssid, ETH_ALEN); hdrlen = 24; } else if (sdata->u.mgd.use_4addr && cpu_to_be16(ethertype) != sdata->control_port_protocol) { @@ -2813,7 +2822,7 @@ } if (!chanctx_conf) { - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { ret = -ENOTCONN; goto free; } @@ -2860,7 +2869,8 @@ goto free; } - if (unlikely(!multicast && ((skb->sk && + if (unlikely(!multicast && + ((skb->sk && skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS) || ctrl_flags & IEEE80211_TX_CTL_REQ_TX_STATUS))) info_id = ieee80211_store_ack_skb(local, skb, &info_flags, @@ -2946,7 +2956,10 @@ memset(info, 0, sizeof(*info)); info->flags = info_flags; - info->ack_frame_id = info_id; + if (info_id) { + info->status_data = info_id; + info->status_data_idr = 1; + } info->band = band; if (likely(!cookie)) { @@ -3055,7 +3068,7 @@ !ieee80211_hw_check(&local->hw, SUPPORTS_TX_FRAG)) goto out; - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { rcu_read_lock(); chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf); @@ -3082,10 +3095,18 @@ break; case NL80211_IFTYPE_STATION: if (test_sta_flag(sta, WLAN_STA_TDLS_PEER)) { + /* For TDLS only one link can be valid with peer STA */ + int tdls_link_id = sta->sta.valid_links ? + __ffs(sta->sta.valid_links) : 0; + struct ieee80211_link_data *link; + /* DA SA BSSID */ build.da_offs = offsetof(struct ieee80211_hdr, addr1); build.sa_offs = offsetof(struct ieee80211_hdr, addr2); - memcpy(hdr->addr3, sdata->deflink.u.mgd.bssid, ETH_ALEN); + link = rcu_dereference(sdata->link[tdls_link_id]); + if (WARN_ON_ONCE(!link)) + break; + memcpy(hdr->addr3, link->u.mgd.bssid, ETH_ALEN); build.hdr_len = 24; break; } @@ -3126,7 +3147,7 @@ fc |= cpu_to_le16(IEEE80211_FCTL_FROMDS); /* DA BSSID SA */ build.da_offs = offsetof(struct ieee80211_hdr, addr1); - if (sta->sta.mlo || !sdata->vif.valid_links) { + if (sta->sta.mlo || !ieee80211_vif_is_mld(&sdata->vif)) { memcpy(hdr->addr2, sdata->vif.addr, ETH_ALEN); } else { unsigned int link_id = sta->deflink.link_id; @@ -4350,6 +4371,9 @@ return false; if (sdata->wdev.use_4addr) return false; + if (ieee80211_hw_check(&sdata->local->hw, + APVLAN_NEED_MCAST_TO_UCAST)) + break; fallthrough; case NL80211_IFTYPE_AP: /* check runtime toggle for this bss */ @@ -4471,6 +4495,8 @@ * @dev: incoming interface * * On failure skb will be freed. + * + * Returns: the netdev TX status (but really only %NETDEV_TX_OK) */ netdev_tx_t ieee80211_subif_start_xmit(struct sk_buff *skb, struct net_device *dev) @@ -4495,7 +4521,7 @@ __ieee80211_subif_start_xmit(skb, dev, 0, IEEE80211_TX_CTRL_MLO_LINK_UNSPEC, NULL); - } else if (sdata->vif.valid_links && + } else if (ieee80211_vif_is_mld(&sdata->vif) && sdata->vif.type == NL80211_IFTYPE_AP && !ieee80211_hw_check(&sdata->local->hw, MLO_MCAST_MULTI_LINK_TX)) { ieee80211_mlo_multicast_tx(dev, skb); @@ -4570,19 +4596,25 @@ static void ieee80211_8023_xmit(struct ieee80211_sub_if_data *sdata, struct net_device *dev, struct sta_info *sta, - struct ieee80211_key *key, struct sk_buff *skb) + struct ieee80211_key *key, struct sk_buff *skb, + u32 info_flags, u32 ctrl_flags, u64 *cookie) { struct ieee80211_tx_info *info; struct ieee80211_local *local = sdata->local; struct tid_ampdu_tx *tid_tx; struct sk_buff *seg, *next; + struct ethhdr *ehdr = (struct ethhdr *)skb->data; + unsigned char *ra = ehdr->h_dest; unsigned int skbs = 0, len = 0; u16 queue; + bool multicast; u8 tid; queue = ieee80211_select_queue(sdata, sta, skb); skb_set_queue_mapping(skb, queue); + multicast = is_multicast_ether_addr(ra); + if (unlikely(test_bit(SCAN_SW_SCANNING, &local->scanning)) && test_bit(SDATA_STATE_OFFCHANNEL, &sdata->state)) goto out_free; @@ -4615,6 +4647,7 @@ info = IEEE80211_SKB_CB(skb); memset(info, 0, sizeof(*info)); + info->flags |= info_flags; info->hw_queue = sdata->vif.hw_queue[queue]; if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN) @@ -4634,10 +4667,14 @@ memcpy(IEEE80211_SKB_CB(seg), info, sizeof(*info)); } - if (unlikely(skb->sk && - skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS)) - info->ack_frame_id = ieee80211_store_ack_skb(local, skb, - &info->flags, NULL); + if (unlikely((skb->sk && + skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS) || + ((ctrl_flags & IEEE80211_TX_CTL_REQ_TX_STATUS) && !multicast))) { + info->status_data = ieee80211_store_ack_skb(local, skb, + &info->flags, cookie); + if (info->status_data) + info->status_data_idr = 1; + } dev_sw_netstats_tx_add(dev, skbs, len); sta->deflink.tx_stats.packets[queue] += skbs; @@ -4653,13 +4690,87 @@ kfree_skb(skb); } -netdev_tx_t ieee80211_subif_start_xmit_8023(struct sk_buff *skb, - struct net_device *dev) +static +void ieee80211_8023_xmit_ap(struct ieee80211_sub_if_data *sdata, + struct net_device *dev, struct sta_info *sta, + struct ieee80211_key *key, struct sk_buff *skb, + u32 info_flags, u32 ctrl_flags, u64 *cookie) +{ + struct ieee80211_tx_info *info; + struct ieee80211_local *local = sdata->local; + struct ieee80211_sta *pubsta = NULL; + struct ieee80211_tx_control control = {}; + struct ethhdr *ehdr = (struct ethhdr *)skb->data; + unsigned char *ra = ehdr->h_dest; + bool multicast = is_multicast_ether_addr(ra); + unsigned long flags; + int q; + u16 q_map; + + /* + * If the skb is shared we need to obtain our own copy. + */ + skb = skb_share_check(skb, GFP_ATOMIC); + + if (unlikely(!skb)) + return; + + info = IEEE80211_SKB_CB(skb); + memset(info, 0, sizeof(*info)); + info->flags |= info_flags; + + if (unlikely((skb->sk && + skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS) || + ((ctrl_flags & IEEE80211_TX_CTL_REQ_TX_STATUS) && !multicast))) { + info->status_data = ieee80211_store_ack_skb(local, skb, + &info->flags, cookie); + if (info->status_data) + info->status_data_idr = 1; + } + + info->flags |= IEEE80211_TX_CTL_HW_80211_ENCAP; + info->control.vif = &sdata->vif; + + if (key) + info->control.hw_key = &key->conf; + + q_map = skb_get_queue_mapping(skb); + q = sdata->vif.hw_queue[q_map]; + + if (sta) { + sta->deflink.tx_stats.bytes[q_map] += skb->len; + sta->deflink.tx_stats.packets[q_map]++; + } + + spin_lock_irqsave(&local->queue_stop_reason_lock, flags); + + if (local->queue_stop_reasons[q] || !skb_queue_empty(&local->pending[q])) { + skb_queue_tail(&local->pending[q], skb); + spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); + return; + } + + spin_unlock_irqrestore(&local->queue_stop_reason_lock, flags); + + if (sta && sta->uploaded) + pubsta = &sta->sta; + + control.sta = pubsta; + + drv_tx(local, &control, skb); +} + +static netdev_tx_t __ieee80211_subif_start_xmit_8023(struct sk_buff *skb, + struct net_device *dev, + u32 info_flags, + u32 ctrl_flags, + u64 *cookie) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); struct ethhdr *ehdr = (struct ethhdr *)skb->data; struct ieee80211_key *key; struct sta_info *sta; + bool is_eapol; if (unlikely(!ieee80211_sdata_running(sdata) || skb->len < ETH_HLEN)) { kfree_skb(skb); @@ -4672,10 +4783,11 @@ kfree_skb(skb); goto out; } + is_eapol = (sdata->control_port_protocol == ehdr->h_proto); if (unlikely(IS_ERR_OR_NULL(sta) || !sta->uploaded || - !test_sta_flag(sta, WLAN_STA_AUTHORIZED) || - sdata->control_port_protocol == ehdr->h_proto)) + (!test_sta_flag(sta, WLAN_STA_AUTHORIZED) && !is_eapol) || + (is_eapol && !(sdata->vif.offload_flags & IEEE80211_OFFLOAD_ENCAP_ENABLED)))) goto skip_offload; key = rcu_dereference(sta->ptk[sta->ptk_idx]); @@ -4687,7 +4799,14 @@ goto skip_offload; sk_pacing_shift_update(skb->sk, sdata->local->hw.tx_sk_pacing_shift); - ieee80211_8023_xmit(sdata, dev, sta, key, skb); + + if (sdata->vif.type == NL80211_IFTYPE_AP) { + ieee80211_8023_xmit_ap(sdata, dev, sta, key, skb, info_flags, ctrl_flags, cookie); + goto out; + } + + ieee80211_8023_xmit(sdata, dev, sta, key, skb, info_flags, + ctrl_flags, cookie); goto out; skip_offload: @@ -4698,6 +4817,60 @@ return NETDEV_TX_OK; } +netdev_tx_t ieee80211_subif_start_xmit_8023(struct sk_buff *skb, + struct net_device *dev) +{ +#if defined(CONFIG_IP_FFN) || defined(CONFIG_IPV6_FFN) + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); + struct ieee80211_tx_control control = {}; + struct sta_info *sta; + struct ieee80211_sta *pubsta = NULL; + + info->control.vif = &sdata->vif; + + if (skb->ffn_ff_done) { + info->control.flags = u32_encode_bits(IEEE80211_LINK_UNSPECIFIED, + IEEE80211_TX_CTRL_MLO_LINK); + info->flags = IEEE80211_TX_CTL_HW_80211_ENCAP; + + if (hweight16(sdata->vif.valid_links) > 1) { + rcu_read_lock(); + + if (ieee80211_lookup_ra_sta(sdata, skb, &sta)) { + kfree_skb(skb); + goto out; + } + + if (!IS_ERR_OR_NULL(sta) && sta->uploaded) + pubsta = &sta->sta; + + control.sta = pubsta; + drv_tx(sdata->local, &control, skb); +out: + rcu_read_unlock(); + } else { + control.sta = NULL; + + rcu_read_lock(); + if (!ieee80211_lookup_ra_sta(sdata, skb, &sta) && + !IS_ERR_OR_NULL(sta)) { + sta->deflink.tx_stats.packets[0]++; + sta->deflink.tx_stats.bytes[0] += skb->len; + } + rcu_read_unlock(); + dev_sw_netstats_tx_add(dev, 1, skb->len); + + drv_tx(sdata->local, &control, skb); + } + + return NETDEV_TX_OK; + } +#endif + + return __ieee80211_subif_start_xmit_8023(skb, dev, 0, 0, NULL); +} + struct sk_buff * ieee80211_build_data_template(struct ieee80211_sub_if_data *sdata, struct sk_buff *skb, u32 info_flags) @@ -4771,7 +4944,7 @@ if (info->control.flags & IEEE80211_TX_INTCFL_NEED_TXPROCESSING) { /* update band only for non-MLD */ - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf); if (unlikely(!chanctx_conf)) { @@ -5546,7 +5719,6 @@ IEEE80211_INCLUDE_ALL_MBSSID_ELEMS, NULL); struct sk_buff *copy; - int shift; if (!bcn) return bcn; @@ -5566,8 +5738,7 @@ if (!copy) return bcn; - shift = ieee80211_vif_get_shift(vif); - ieee80211_tx_monitor(hw_to_local(hw), copy, 1, shift, false, NULL); + ieee80211_tx_monitor(hw_to_local(hw), copy, 1, false, NULL); return bcn; } @@ -5917,7 +6088,7 @@ int ret; u32 queues; - lockdep_assert_held(&local->sta_mtx); + lockdep_assert_wiphy(local->hw.wiphy); /* only some cases are supported right now */ switch (sdata->vif.type) { @@ -5978,7 +6149,7 @@ struct sta_info *sta = container_of(pubsta, struct sta_info, sta); struct ieee80211_sub_if_data *sdata = sta->sdata; - lockdep_assert_held(&sdata->local->sta_mtx); + lockdep_assert_wiphy(sdata->local->hw.wiphy); /* only some cases are supported right now */ switch (sdata->vif.type) { @@ -6018,7 +6189,7 @@ BUILD_BUG_ON(!FIELD_FIT(IEEE80211_TX_CTRL_MLO_LINK, IEEE80211_LINK_UNSPECIFIED)); - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { link = 0; } else if (link_id >= 0) { link = link_id; @@ -6064,7 +6235,7 @@ enum nl80211_band band; rcu_read_lock(); - if (!sdata->vif.valid_links) { + if (!ieee80211_vif_is_mld(&sdata->vif)) { WARN_ON(link_id >= 0); chanctx_conf = rcu_dereference(sdata->vif.bss_conf.chanctx_conf); @@ -6099,6 +6270,9 @@ u32 flags = 0; int err; + /* mutex lock is only needed for incrementing the cookie counter */ + lockdep_assert_wiphy(local->hw.wiphy); + /* Only accept CONTROL_PORT_PROTOCOL configured in CONNECT/ASSOCIATE * or Pre-Authentication */ @@ -6189,15 +6363,15 @@ rcu_read_unlock(); start_xmit: - /* mutex lock is only needed for incrementing the cookie counter */ - mutex_lock(&local->mtx); - local_bh_disable(); - __ieee80211_subif_start_xmit(skb, skb->dev, flags, ctrl_flags, cookie); + if (sdata->vif.offload_flags & IEEE80211_OFFLOAD_ENCAP_ENABLED) + __ieee80211_subif_start_xmit_8023(skb, skb->dev, flags, + ctrl_flags, cookie); + else + __ieee80211_subif_start_xmit(skb, skb->dev, flags, ctrl_flags, + cookie); local_bh_enable(); - mutex_unlock(&local->mtx); - return 0; } diff -ruw linux-6.4/net/mac80211/util.c linux-6.4-fbx/net/mac80211/util.c --- linux-6.4/net/mac80211/util.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/util.c 2024-04-19 16:04:28.973736213 +0200 @@ -6,7 +6,7 @@ * Copyright 2007 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright (C) 2015-2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation * * utilities for mac80211 */ @@ -24,6 +24,7 @@ #include #include #include +#include #include "ieee80211_i.h" #include "driver-ops.h" @@ -109,8 +110,7 @@ } int ieee80211_frame_duration(enum nl80211_band band, size_t len, - int rate, int erp, int short_preamble, - int shift) + int rate, int erp, int short_preamble) { int dur; @@ -121,9 +121,6 @@ * * rate is in 100 kbps, so divident is multiplied by 10 in the * DIV_ROUND_UP() operations. - * - * shift may be 2 for 5 MHz channels or 1 for 10 MHz channels, and - * is assumed to be 0 otherwise. */ if (band == NL80211_BAND_5GHZ || erp) { @@ -144,12 +141,6 @@ dur += 16; /* IEEE 802.11-2012 18.3.2.4: T_PREAMBLE = 16 usec */ dur += 4; /* IEEE 802.11-2012 18.3.2.4: T_SIGNAL = 4 usec */ - /* IEEE 802.11-2012 18.3.2.4: all values above are: - * * times 4 for 5 MHz - * * times 2 for 10 MHz - */ - dur *= 1 << shift; - /* rates should already consider the channel bandwidth, * don't apply divisor again. */ @@ -184,7 +175,7 @@ { struct ieee80211_sub_if_data *sdata; u16 dur; - int erp, shift = 0; + int erp; bool short_preamble = false; erp = 0; @@ -193,11 +184,10 @@ short_preamble = sdata->vif.bss_conf.use_short_preamble; if (sdata->deflink.operating_11g_mode) erp = rate->flags & IEEE80211_RATE_ERP_G; - shift = ieee80211_vif_get_shift(vif); } dur = ieee80211_frame_duration(band, frame_len, rate->bitrate, erp, - short_preamble, shift); + short_preamble); return cpu_to_le16(dur); } @@ -211,7 +201,7 @@ struct ieee80211_rate *rate; struct ieee80211_sub_if_data *sdata; bool short_preamble; - int erp, shift = 0, bitrate; + int erp, bitrate; u16 dur; struct ieee80211_supported_band *sband; @@ -227,20 +217,19 @@ short_preamble = sdata->vif.bss_conf.use_short_preamble; if (sdata->deflink.operating_11g_mode) erp = rate->flags & IEEE80211_RATE_ERP_G; - shift = ieee80211_vif_get_shift(vif); } - bitrate = DIV_ROUND_UP(rate->bitrate, 1 << shift); + bitrate = rate->bitrate; /* CTS duration */ dur = ieee80211_frame_duration(sband->band, 10, bitrate, - erp, short_preamble, shift); + erp, short_preamble); /* Data frame duration */ dur += ieee80211_frame_duration(sband->band, frame_len, bitrate, - erp, short_preamble, shift); + erp, short_preamble); /* ACK duration */ dur += ieee80211_frame_duration(sband->band, 10, bitrate, - erp, short_preamble, shift); + erp, short_preamble); return cpu_to_le16(dur); } @@ -255,7 +244,7 @@ struct ieee80211_rate *rate; struct ieee80211_sub_if_data *sdata; bool short_preamble; - int erp, shift = 0, bitrate; + int erp, bitrate; u16 dur; struct ieee80211_supported_band *sband; @@ -270,18 +259,17 @@ short_preamble = sdata->vif.bss_conf.use_short_preamble; if (sdata->deflink.operating_11g_mode) erp = rate->flags & IEEE80211_RATE_ERP_G; - shift = ieee80211_vif_get_shift(vif); } - bitrate = DIV_ROUND_UP(rate->bitrate, 1 << shift); + bitrate = rate->bitrate; /* Data frame duration */ dur = ieee80211_frame_duration(sband->band, frame_len, bitrate, - erp, short_preamble, shift); + erp, short_preamble); if (!(frame_txctl->flags & IEEE80211_TX_CTL_NO_ACK)) { /* ACK duration */ dur += ieee80211_frame_duration(sband->band, 10, bitrate, - erp, short_preamble, shift); + erp, short_preamble); } return cpu_to_le16(dur); @@ -705,6 +693,19 @@ IEEE80211_QUEUE_STOP_REASON_FLUSH, false); + if (drop) { + struct sta_info *sta; + + /* Purge the queues, so the frames on them won't be + * sent during __ieee80211_wake_queue() + */ + list_for_each_entry(sta, &local->sta_list, list) { + if (sdata != sta->sdata) + continue; + ieee80211_purge_sta_txqs(sta); + } + } + drv_flush(local, sdata, queues, drop); ieee80211_wake_queues_by_reason(&local->hw, queues, @@ -918,6 +919,7 @@ struct ieee80211_elems_parse_params *params) { const void *data = elem->data + 1; + bool calc_crc = false; u8 len; if (!elem->datalen) @@ -927,12 +929,9 @@ switch (elem->data[0]) { case WLAN_EID_EXT_HE_MU_EDCA: - if (len >= sizeof(*elems->mu_edca_param_set)) { + calc_crc = true; + if (len >= sizeof(*elems->mu_edca_param_set)) elems->mu_edca_param_set = data; - if (crc) - *crc = crc32_be(*crc, (void *)elem, - elem->datalen + 2); - } break; case WLAN_EID_EXT_HE_CAPABILITY: if (ieee80211_he_capa_size_ok(data, len)) { @@ -941,13 +940,10 @@ } break; case WLAN_EID_EXT_HE_OPERATION: + calc_crc = true; if (len >= sizeof(*elems->he_operation) && - len >= ieee80211_he_oper_size(data) - 1) { - if (crc) - *crc = crc32_be(*crc, (void *)elem, - elem->datalen + 2); + len >= ieee80211_he_oper_size(data) - 1) elems->he_operation = data; - } break; case WLAN_EID_EXT_UORA: if (len >= 1) @@ -981,14 +977,49 @@ case WLAN_EID_EXT_EHT_OPERATION: if (ieee80211_eht_oper_size_ok(data, len)) elems->eht_operation = data; + calc_crc = true; break; case WLAN_EID_EXT_EHT_MULTI_LINK: + calc_crc = true; + if (ieee80211_mle_size_ok(data, len)) { - elems->multi_link = (void *)data; - elems->multi_link_len = len; + const struct ieee80211_multi_link_elem *mle = + (void *)data; + + switch (le16_get_bits(mle->control, + IEEE80211_ML_CONTROL_TYPE)) { + case IEEE80211_ML_CONTROL_TYPE_BASIC: + elems->ml_basic_elem = (void *)elem; + elems->ml_basic = data; + elems->ml_basic_len = len; + break; + case IEEE80211_ML_CONTROL_TYPE_RECONF: + elems->ml_reconf_elem = (void *)elem; + elems->ml_reconf = data; + elems->ml_reconf_len = len; + break; + default: + break; + } } break; + case WLAN_EID_EXT_BANDWIDTH_INDICATION: + if (ieee80211_bandwidth_indication_size_ok(data, len)) + elems->bandwidth_indication = data; + calc_crc = true; + break; + case WLAN_EID_EXT_TID_TO_LINK_MAPPING: + calc_crc = true; + if (ieee80211_tid_to_link_map_size_ok(data, len) && + elems->ttlm_num < ARRAY_SIZE(elems->ttlm)) { + elems->ttlm[elems->ttlm_num] = (void *)data; + elems->ttlm_num++; } + break; + } + + if (crc && calc_crc) + *crc = crc32_be(*crc, (void *)elem, elem->datalen + 2); } static u32 @@ -1000,11 +1031,11 @@ bool calc_crc = params->filter != 0; DECLARE_BITMAP(seen_elems, 256); u32 crc = params->crc; - const u8 *ie; bitmap_zero(seen_elems, 256); for_each_element(elem, params->start, params->len) { + const struct element *subelem; bool elem_parse_failed; u8 id = elem->id; u8 elen = elem->datalen; @@ -1262,15 +1293,27 @@ } /* * This is a bit tricky, but as we only care about - * the wide bandwidth channel switch element, so - * just parse it out manually. + * a few elements, parse them out manually. */ - ie = cfg80211_find_ie(WLAN_EID_WIDE_BW_CHANNEL_SWITCH, + subelem = cfg80211_find_elem(WLAN_EID_WIDE_BW_CHANNEL_SWITCH, pos, elen); - if (ie) { - if (ie[1] >= sizeof(*elems->wide_bw_chansw_ie)) + if (subelem) { + if (subelem->datalen >= sizeof(*elems->wide_bw_chansw_ie)) elems->wide_bw_chansw_ie = - (void *)(ie + 2); + (void *)subelem->data; + else + elem_parse_failed = true; + } + + subelem = cfg80211_find_ext_elem(WLAN_EID_EXT_BANDWIDTH_INDICATION, + pos, elen); + if (subelem) { + const void *edata = subelem->data + 1; + u8 edatalen = subelem->datalen - 1; + + if (ieee80211_bandwidth_indication_size_ok(edata, + edatalen)) + elems->bandwidth_indication = edata; else elem_parse_failed = true; } @@ -1458,56 +1501,11 @@ return found ? profile_len : 0; } -static void ieee80211_defragment_element(struct ieee802_11_elems *elems, - void **elem_ptr, size_t *len, - size_t total_len, u8 frag_id) -{ - u8 *data = *elem_ptr, *pos, *start; - const struct element *elem; - - /* - * Since 'data' points to the data of the element, not the element - * itself, allow 254 in case it was an extended element where the - * extended ID isn't part of the data we see here and thus not part of - * 'len' either. - */ - if (!data || (*len != 254 && *len != 255)) - return; - - start = elems->scratch_pos; - - if (WARN_ON(*len > (elems->scratch + elems->scratch_len - - elems->scratch_pos))) - return; - - memcpy(elems->scratch_pos, data, *len); - elems->scratch_pos += *len; - - pos = data + *len; - total_len -= *len; - for_each_element(elem, pos, total_len) { - if (elem->id != frag_id) - break; - - if (WARN_ON(elem->datalen > - (elems->scratch + elems->scratch_len - - elems->scratch_pos))) - return; - - memcpy(elems->scratch_pos, elem->data, elem->datalen); - elems->scratch_pos += elem->datalen; - - *len += elem->datalen; - } - - *elem_ptr = start; -} - static void ieee80211_mle_get_sta_prof(struct ieee802_11_elems *elems, u8 link_id) { - const struct ieee80211_multi_link_elem *ml = elems->multi_link; - size_t ml_len = elems->multi_link_len; + const struct ieee80211_multi_link_elem *ml = elems->ml_basic; + ssize_t ml_len = elems->ml_basic_len; const struct element *sub; if (!ml || !ml_len) @@ -1519,12 +1517,14 @@ for_each_mle_subelement(sub, (u8 *)ml, ml_len) { struct ieee80211_mle_per_sta_profile *prof = (void *)sub->data; + ssize_t sta_prof_len; u16 control; if (sub->id != IEEE80211_MLE_SUBELEM_PER_STA_PROFILE) continue; - if (!ieee80211_mle_sta_prof_size_ok(sub->data, sub->datalen)) + if (!ieee80211_mle_basic_sta_prof_size_ok(sub->data, + sub->datalen)) return; control = le16_to_cpu(prof->control); @@ -1536,14 +1536,23 @@ if (!(control & IEEE80211_MLE_STA_CONTROL_COMPLETE_PROFILE)) return; - elems->prof = prof; - elems->sta_prof_len = sub->datalen; - /* the sub element can be fragmented */ - ieee80211_defragment_element(elems, (void **)&elems->prof, - &elems->sta_prof_len, - ml_len - (sub->data - (u8 *)ml), + sta_prof_len = + cfg80211_defragment_element(sub, + (u8 *)ml, ml_len, + elems->scratch_pos, + elems->scratch + + elems->scratch_len - + elems->scratch_pos, IEEE80211_MLE_SUBELEM_FRAGMENT); + + if (sta_prof_len < 0) + return; + + elems->prof = (void *)elems->scratch_pos; + elems->sta_prof_len = sta_prof_len; + elems->scratch_pos += sta_prof_len; + return; } } @@ -1557,18 +1566,28 @@ .from_ap = params->from_ap, .link_id = -1, }; + ssize_t ml_len = elems->ml_basic_len; const struct element *non_inherit = NULL; const u8 *end; if (params->link_id == -1) return; - ieee80211_defragment_element(elems, (void **)&elems->multi_link, - &elems->multi_link_len, - elems->total_len - ((u8 *)elems->multi_link - - elems->ie_start), + ml_len = cfg80211_defragment_element(elems->ml_basic_elem, + elems->ie_start, + elems->total_len, + elems->scratch_pos, + elems->scratch + + elems->scratch_len - + elems->scratch_pos, WLAN_EID_FRAGMENT); + if (ml_len < 0) + return; + + elems->ml_basic = (const void *)elems->scratch_pos; + elems->ml_basic_len = ml_len; + ieee80211_mle_get_sta_prof(elems, params->link_id); prof = elems->prof; @@ -1597,6 +1616,59 @@ _ieee802_11_parse_elems_full(&sub, elems, non_inherit); } +u32 ieee802_11_parse_mesh_vendor_elems(const u8 *start, size_t len, bool action, + struct ieee802_11_mesh_vendor_specific_elems *elems, + u64 filter, u32 crc, u8 type) +{ + size_t left = len; + const u8 *pos = start; + bool calc_crc = filter != 0; + + memset(elems, 0, sizeof(*elems)); + elems->parse_error = true; + + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) + break; + + if (calc_crc && id < 64 && (filter & (1ULL << id))) + crc = crc32_be(crc, pos - 2, elen + 2); + + switch (id) { + case WLAN_EID_VENDOR_SPECIFIC: + if (elen >= 4 && pos[0] == 0xC0 && pos[1] == 0xFF && + pos[2] == 0xEE && pos[3] == type) { + /* Qubercomm OUI (C0:FF:EE) */ + + if (calc_crc) + crc = crc32_be(crc, pos - 2, elen + 2); + + elems->ie_start = pos; + elems->ie_len = elen; + elems->parse_error = false; + } + break; + default: + break; + } + + if (elems->parse_error == false) + break; + + left -= elen; + pos += elen; + } + + return crc; +} +EXPORT_SYMBOL(ieee802_11_parse_mesh_vendor_elems); + struct ieee802_11_elems * ieee802_11_parse_elems_full(struct ieee80211_elems_parse_params *params) { @@ -1604,9 +1676,9 @@ const struct element *non_inherit = NULL; u8 *nontransmitted_profile; int nontransmitted_profile_len = 0; - size_t scratch_len = params->scratch_len ?: 3 * params->len; + size_t scratch_len = 3 * params->len; - elems = kzalloc(sizeof(*elems) + scratch_len, GFP_ATOMIC); + elems = kzalloc(struct_size(elems, scratch, scratch_len), GFP_ATOMIC); if (!elems) return NULL; elems->ie_start = params->start; @@ -1661,6 +1733,7 @@ return elems; } +EXPORT_SYMBOL_IF_KUNIT(ieee802_11_parse_elems_full); void ieee80211_regulatory_limit_wmm_params(struct ieee80211_sub_if_data *sdata, struct ieee80211_tx_queue_params @@ -1824,7 +1897,7 @@ struct ieee80211_local *local = sdata->local; struct sk_buff *skb; struct ieee80211_mgmt *mgmt; - bool multi_link = sdata->vif.valid_links; + bool multi_link = ieee80211_vif_is_mld(&sdata->vif); struct { u8 id; u8 len; @@ -1918,7 +1991,7 @@ } } -static u8 *ieee80211_write_he_6ghz_cap(u8 *pos, __le16 cap, u8 *end) +u8 *ieee80211_write_he_6ghz_cap(u8 *pos, __le16 cap, u8 *end) { if ((end - pos) < 5) return pos; @@ -1949,7 +2022,6 @@ u8 rates[32]; int num_rates; int ext_rates_len; - int shift; u32 rate_flags; bool have_80mhz = false; @@ -1960,7 +2032,6 @@ return 0; rate_flags = ieee80211_chandef_rate_flags(chandef); - shift = ieee80211_chandef_get_shift(chandef); /* For direct scan add S1G IE and consider its override bits */ if (band == NL80211_BAND_S1GHZ) { @@ -1978,8 +2049,7 @@ continue; rates[num_rates++] = - (u8) DIV_ROUND_UP(sband->bitrates[i].bitrate, - (1 << shift) * 5); + (u8) DIV_ROUND_UP(sband->bitrates[i].bitrate, 5); } supp_rates_len = min_t(int, num_rates, 8); @@ -2121,8 +2191,7 @@ *offset = noffset; } - he_cap = ieee80211_get_he_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + he_cap = ieee80211_get_he_iftype_cap_vif(sband, &sdata->vif); if (he_cap && cfg80211_any_usable_channels(local->hw.wiphy, BIT(sband->band), IEEE80211_CHAN_NO_HE)) { @@ -2131,8 +2200,7 @@ goto out_err; } - eht_cap = ieee80211_get_eht_iftype_cap(sband, - ieee80211_vif_type_p2p(&sdata->vif)); + eht_cap = ieee80211_get_eht_iftype_cap_vif(sband, &sdata->vif); if (eht_cap && cfg80211_any_usable_channels(local->hw.wiphy, BIT(sband->band), @@ -2150,8 +2218,7 @@ struct ieee80211_supported_band *sband6; sband6 = local->hw.wiphy->bands[NL80211_BAND_6GHZ]; - he_cap = ieee80211_get_he_iftype_cap(sband6, - ieee80211_vif_type_p2p(&sdata->vif)); + he_cap = ieee80211_get_he_iftype_cap_vif(sband6, &sdata->vif); if (he_cap) { enum nl80211_iftype iftype = @@ -2275,14 +2342,13 @@ struct ieee80211_supported_band *sband; size_t num_rates; u32 supp_rates, rate_flags; - int i, j, shift; + int i, j; sband = sdata->local->hw.wiphy->bands[band]; if (WARN_ON(!sband)) return 1; rate_flags = ieee80211_chandef_rate_flags(&sdata->vif.bss_conf.chandef); - shift = ieee80211_vif_get_shift(&sdata->vif); num_rates = sband->n_bitrates; supp_rates = 0; @@ -2308,8 +2374,7 @@ != rate_flags) continue; - brate = DIV_ROUND_UP(sband->bitrates[j].bitrate, - 1 << shift); + brate = sband->bitrates[j].bitrate; if (brate == own_rate) { supp_rates |= BIT(j); @@ -2326,9 +2391,10 @@ ieee80211_led_radio(local, false); ieee80211_mod_tpt_led_trig(local, 0, IEEE80211_TPT_LEDTRIG_FL_RADIO); - cancel_work_sync(&local->reconfig_filter); + wiphy_work_cancel(local->hw.wiphy, &local->reconfig_filter); flush_workqueue(local->workqueue); + wiphy_work_flush(local->hw.wiphy, NULL); drv_stop(local); } @@ -2350,8 +2416,8 @@ */ if (aborted) set_bit(SCAN_ABORTED, &local->scanning); - ieee80211_queue_delayed_work(&local->hw, &local->scan_work, 0); - flush_delayed_work(&local->scan_work); + wiphy_delayed_work_queue(local->hw.wiphy, &local->scan_work, 0); + wiphy_delayed_work_flush(local->hw.wiphy, &local->scan_work); } } @@ -2360,6 +2426,8 @@ struct ieee80211_sub_if_data *sdata; struct ieee80211_chanctx *ctx; + lockdep_assert_wiphy(local->hw.wiphy); + /* * We get here if during resume the device can't be restarted properly. * We might also get here if this happens during HW reset, which is a @@ -2373,6 +2441,7 @@ local->resuming = false; local->suspended = false; local->in_reconfig = false; + local->reconfig_failure = true; ieee80211_flush_completed_scan(local, true); @@ -2387,10 +2456,8 @@ /* Mark channel contexts as not being in the driver any more to avoid * removing them from the driver during the shutdown process... */ - mutex_lock(&local->chanctx_mtx); list_for_each_entry(ctx, &local->chanctx_list, list) ctx->driver_present = false; - mutex_unlock(&local->chanctx_mtx); } static void ieee80211_assign_chanctx(struct ieee80211_local *local, @@ -2400,17 +2467,17 @@ struct ieee80211_chanctx_conf *conf; struct ieee80211_chanctx *ctx; + lockdep_assert_wiphy(local->hw.wiphy); + if (!local->use_chanctx) return; - mutex_lock(&local->chanctx_mtx); conf = rcu_dereference_protected(link->conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (conf) { ctx = container_of(conf, struct ieee80211_chanctx, conf); drv_assign_vif_chanctx(local, sdata, link->conf, ctx); } - mutex_unlock(&local->chanctx_mtx); } static void ieee80211_reconfig_stations(struct ieee80211_sub_if_data *sdata) @@ -2418,8 +2485,9 @@ struct ieee80211_local *local = sdata->local; struct sta_info *sta; + lockdep_assert_wiphy(local->hw.wiphy); + /* add STAs back */ - mutex_lock(&local->sta_mtx); list_for_each_entry(sta, &local->sta_list, list) { enum ieee80211_sta_state state; @@ -2431,7 +2499,6 @@ WARN_ON(drv_sta_state(local, sta->sdata, sta, state, state + 1)); } - mutex_unlock(&local->sta_mtx); } static int ieee80211_reconfig_nan(struct ieee80211_sub_if_data *sdata) @@ -2475,6 +2542,35 @@ return 0; } +static void ieee80211_reconfig_ap_links(struct ieee80211_local *local, + struct ieee80211_sub_if_data *sdata, + u64 changed) +{ + int link_id; + + for (link_id = 0; link_id < ARRAY_SIZE(sdata->link); link_id++) { + struct ieee80211_link_data *link; + + if (!(sdata->vif.active_links & BIT(link_id))) + continue; + + link = sdata_dereference(sdata->link[link_id], sdata); + if (!link) + continue; + + if (rcu_access_pointer(link->u.ap.beacon)) + drv_start_ap(local, sdata, link->conf); + + if (!link->conf->enable_beacon) + continue; + + changed |= BSS_CHANGED_BEACON | + BSS_CHANGED_BEACON_ENABLED; + + ieee80211_link_info_change_notify(sdata, link, changed); + } +} + int ieee80211_reconfig(struct ieee80211_local *local) { struct ieee80211_hw *hw = &local->hw; @@ -2489,6 +2585,8 @@ bool suspended = local->suspended; bool in_reconfig = false; + lockdep_assert_wiphy(local->hw.wiphy); + /* nothing to do if HW shouldn't run */ if (!local->open_count) goto wake_up; @@ -2604,12 +2702,10 @@ /* add channel contexts */ if (local->use_chanctx) { - mutex_lock(&local->chanctx_mtx); list_for_each_entry(ctx, &local->chanctx_list, list) if (ctx->replace_state != IEEE80211_CHANCTX_REPLACES_OTHER) WARN_ON(drv_add_chanctx(local, ctx)); - mutex_unlock(&local->chanctx_mtx); sdata = wiphy_dereference(local->hw.wiphy, local->monitor_sdata); @@ -2624,20 +2720,53 @@ /* Finally also reconfigure all the BSS information */ list_for_each_entry(sdata, &local->interfaces, list) { + /* common change flags for all interface types - link only */ + u64 changed = BSS_CHANGED_ERP_CTS_PROT | + BSS_CHANGED_ERP_PREAMBLE | + BSS_CHANGED_ERP_SLOT | + BSS_CHANGED_HT | + BSS_CHANGED_BASIC_RATES | + BSS_CHANGED_BEACON_INT | + BSS_CHANGED_BSSID | + BSS_CHANGED_CQM | + BSS_CHANGED_QOS | + BSS_CHANGED_TXPOWER | + BSS_CHANGED_MCAST_RATE; + struct ieee80211_link_data *link = NULL; unsigned int link_id; - u32 changed; + u32 active_links = 0; if (!ieee80211_sdata_running(sdata)) continue; - sdata_lock(sdata); + if (ieee80211_vif_is_mld(&sdata->vif)) { + struct ieee80211_bss_conf *old[IEEE80211_MLD_MAX_NUM_LINKS] = { + [0] = &sdata->vif.bss_conf, + }; + + if (sdata->vif.type == NL80211_IFTYPE_STATION) { + /* start with a single active link */ + active_links = sdata->vif.active_links; + link_id = ffs(active_links) - 1; + sdata->vif.active_links = BIT(link_id); + } + + drv_change_vif_links(local, sdata, 0, + sdata->vif.active_links, + old); + } + for (link_id = 0; link_id < ARRAY_SIZE(sdata->vif.link_conf); link_id++) { - struct ieee80211_link_data *link; + if (ieee80211_vif_is_mld(&sdata->vif) && + !(sdata->vif.active_links & BIT(link_id))) + continue; link = sdata_dereference(sdata->link[link_id], sdata); - if (link) + if (!link) + continue; + ieee80211_assign_chanctx(local, sdata, link); } @@ -2658,27 +2787,16 @@ &sdata->deflink.tx_conf[i]); break; } - sdata_unlock(sdata); - - /* common change flags for all interface types */ - changed = BSS_CHANGED_ERP_CTS_PROT | - BSS_CHANGED_ERP_PREAMBLE | - BSS_CHANGED_ERP_SLOT | - BSS_CHANGED_HT | - BSS_CHANGED_BASIC_RATES | - BSS_CHANGED_BEACON_INT | - BSS_CHANGED_BSSID | - BSS_CHANGED_CQM | - BSS_CHANGED_QOS | - BSS_CHANGED_IDLE | - BSS_CHANGED_TXPOWER | - BSS_CHANGED_MCAST_RATE; if (sdata->vif.bss_conf.mu_mimo_owner) changed |= BSS_CHANGED_MU_GROUPS; + if (!ieee80211_vif_is_mld(&sdata->vif)) + changed |= BSS_CHANGED_IDLE; + switch (sdata->vif.type) { case NL80211_IFTYPE_STATION: + if (!ieee80211_vif_is_mld(&sdata->vif)) { changed |= BSS_CHANGED_ASSOC | BSS_CHANGED_ARP_FILTER | BSS_CHANGED_PS; @@ -2691,9 +2809,20 @@ sdata->vif.bss_conf.protected_keep_alive) changed |= BSS_CHANGED_KEEP_ALIVE; - sdata_lock(sdata); - ieee80211_bss_info_change_notify(sdata, changed); - sdata_unlock(sdata); + if (sdata->vif.bss_conf.eht_puncturing) + changed |= BSS_CHANGED_EHT_PUNCTURING; + + ieee80211_bss_info_change_notify(sdata, + changed); + } else if (!WARN_ON(!link)) { + ieee80211_link_info_change_notify(sdata, link, + changed); + changed = BSS_CHANGED_ASSOC | + BSS_CHANGED_IDLE | + BSS_CHANGED_PS | + BSS_CHANGED_ARP_FILTER; + ieee80211_vif_cfg_change_notify(sdata, changed); + } break; case NL80211_IFTYPE_OCB: changed |= BSS_CHANGED_OCB; @@ -2703,7 +2832,13 @@ changed |= BSS_CHANGED_IBSS; fallthrough; case NL80211_IFTYPE_AP: - changed |= BSS_CHANGED_SSID | BSS_CHANGED_P2P_PS; + changed |= BSS_CHANGED_P2P_PS; + + if (ieee80211_vif_is_mld(&sdata->vif)) + ieee80211_vif_cfg_change_notify(sdata, + BSS_CHANGED_SSID); + else + changed |= BSS_CHANGED_SSID; if (sdata->vif.bss_conf.ftm_responder == 1 && wiphy_ext_feature_isset(sdata->local->hw.wiphy, @@ -2713,6 +2848,13 @@ if (sdata->vif.type == NL80211_IFTYPE_AP) { changed |= BSS_CHANGED_AP_PROBE_RESP; + if (ieee80211_vif_is_mld(&sdata->vif)) { + ieee80211_reconfig_ap_links(local, + sdata, + changed); + break; + } + if (rcu_access_pointer(sdata->deflink.u.ap.beacon)) drv_start_ap(local, sdata, sdata->deflink.conf); @@ -2745,6 +2887,9 @@ WARN_ON(1); break; } + + if (active_links) + ieee80211_set_active_links(&sdata->vif, active_links); } ieee80211_recalc_ps(local); @@ -2771,7 +2916,6 @@ if (!ieee80211_sdata_running(sdata)) continue; - sdata_lock(sdata); switch (sdata->vif.type) { case NL80211_IFTYPE_AP_VLAN: case NL80211_IFTYPE_AP: @@ -2780,7 +2924,6 @@ default: break; } - sdata_unlock(sdata); } /* add back keys */ @@ -2788,11 +2931,10 @@ ieee80211_reenable_keys(sdata); /* Reconfigure sched scan if it was interrupted by FW restart */ - mutex_lock(&local->mtx); sched_scan_sdata = rcu_dereference_protected(local->sched_scan_sdata, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); sched_scan_req = rcu_dereference_protected(local->sched_scan_req, - lockdep_is_held(&local->mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); if (sched_scan_sdata && sched_scan_req) /* * Sched scan stopped, but we don't want to report it. Instead, @@ -2808,7 +2950,6 @@ RCU_INIT_POINTER(local->sched_scan_req, NULL); sched_scan_stopped = true; } - mutex_unlock(&local->mtx); if (sched_scan_stopped) cfg80211_sched_scan_stopped_locked(local->hw.wiphy, 0); @@ -2829,16 +2970,12 @@ * are active. This is really a workaround though. */ if (ieee80211_hw_check(hw, AMPDU_AGGREGATION)) { - mutex_lock(&local->sta_mtx); - list_for_each_entry(sta, &local->sta_list, list) { if (!local->resuming) ieee80211_sta_tear_down_BA_sessions( sta, AGG_STOP_LOCAL_REQUEST); clear_sta_flag(sta, WLAN_STA_BLOCK_BA); } - - mutex_unlock(&local->sta_mtx); } /* @@ -2854,13 +2991,11 @@ barrier(); /* Restart deferred ROCs */ - mutex_lock(&local->mtx); ieee80211_start_next_roc(local); - mutex_unlock(&local->mtx); /* Requeue all works */ list_for_each_entry(sdata, &local->interfaces, list) - ieee80211_queue_work(&local->hw, &sdata->work); + wiphy_work_queue(local->hw.wiphy, &sdata->work); } ieee80211_wake_queues_by_reason(hw, IEEE80211_MAX_QUEUE_MAP, @@ -2917,6 +3052,8 @@ sdata = vif_to_sdata(vif); local = sdata->local; + lockdep_assert_wiphy(local->hw.wiphy); + if (WARN_ON(flag & IEEE80211_SDATA_DISCONNECT_RESUME && !local->resuming)) return; @@ -2930,10 +3067,8 @@ sdata->flags |= flag; - mutex_lock(&local->key_mtx); list_for_each_entry(key, &sdata->key_list, list) key->flags |= KEY_FLAG_TAINTED; - mutex_unlock(&local->key_mtx); } void ieee80211_hw_restart_disconnect(struct ieee80211_vif *vif) @@ -2955,10 +3090,10 @@ struct ieee80211_chanctx_conf *chanctx_conf; struct ieee80211_chanctx *chanctx; - mutex_lock(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); chanctx_conf = rcu_dereference_protected(link->conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); /* * This function can be called from a work, thus it may be possible @@ -2967,12 +3102,10 @@ * So nothing should be done in such case. */ if (!chanctx_conf) - goto unlock; + return; chanctx = container_of(chanctx_conf, struct ieee80211_chanctx, conf); ieee80211_recalc_smps_chanctx(local, chanctx); - unlock: - mutex_unlock(&local->chanctx_mtx); } void ieee80211_recalc_min_chandef(struct ieee80211_sub_if_data *sdata, @@ -2983,7 +3116,7 @@ struct ieee80211_chanctx *chanctx; int i; - mutex_lock(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); for (i = 0; i < ARRAY_SIZE(sdata->vif.link_conf); i++) { struct ieee80211_bss_conf *bss_conf; @@ -2999,9 +3132,9 @@ } chanctx_conf = rcu_dereference_protected(bss_conf->chanctx_conf, - lockdep_is_held(&local->chanctx_mtx)); + lockdep_is_held(&local->hw.wiphy->mtx)); /* - * Since we hold the chanctx_mtx (checked above) + * Since we hold the wiphy mutex (checked above) * we can take the chanctx_conf pointer out of the * RCU critical section, it cannot go away without * the mutex. Just the way we reached it could - in @@ -3011,14 +3144,12 @@ rcu_read_unlock(); if (!chanctx_conf) - goto unlock; + return; chanctx = container_of(chanctx_conf, struct ieee80211_chanctx, conf); ieee80211_recalc_chanctx_min_def(local, chanctx, NULL); } - unlock: - mutex_unlock(&local->chanctx_mtx); } size_t ieee80211_ie_split_vendor(const u8 *ies, size_t ielen, size_t offset) @@ -3706,12 +3837,10 @@ return true; } -void ieee80211_chandef_eht_oper(const struct ieee80211_eht_operation *eht_oper, +void ieee80211_chandef_eht_oper(const struct ieee80211_eht_operation_info *info, bool support_160, bool support_320, struct cfg80211_chan_def *chandef) { - struct ieee80211_eht_operation_info *info = (void *)eht_oper->optional; - chandef->center_freq1 = ieee80211_channel_to_frequency(info->ccfs0, chandef->chan->band); @@ -3801,10 +3930,8 @@ } eht_cap = ieee80211_get_eht_iftype_cap(sband, iftype); - if (!eht_cap) { - sdata_info(sdata, "Missing iftype sband data/EHT cap"); + if (!eht_cap) eht_oper = NULL; - } he_6ghz_oper = ieee80211_he_6ghz_oper(he_oper); @@ -3882,8 +4009,9 @@ support_320 = eht_phy_cap & IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; - ieee80211_chandef_eht_oper(eht_oper, support_160, - support_320, &he_chandef); + ieee80211_chandef_eht_oper((const void *)eht_oper->optional, + support_160, support_320, + &he_chandef); } if (!cfg80211_chandef_valid(&he_chandef)) { @@ -3942,7 +4070,6 @@ const u8 *srates, int srates_len, u32 *rates) { u32 rate_flags = ieee80211_chanwidth_rate_flags(width); - int shift = ieee80211_chanwidth_get_shift(width); struct ieee80211_rate *br; int brate, rate, i, j, count = 0; @@ -3956,7 +4083,7 @@ if ((rate_flags & br->flags) != rate_flags) continue; - brate = DIV_ROUND_UP(br->bitrate, (1 << shift) * 5); + brate = DIV_ROUND_UP(br->bitrate, 5); if (brate == rate) { *rates |= BIT(j); count++; @@ -3973,12 +4100,11 @@ { struct ieee80211_local *local = sdata->local; struct ieee80211_supported_band *sband; - int rate, shift; + int rate; u8 i, rates, *pos; u32 basic_rates = sdata->vif.bss_conf.basic_rates; u32 rate_flags; - shift = ieee80211_vif_get_shift(&sdata->vif); rate_flags = ieee80211_chandef_rate_flags(&sdata->vif.bss_conf.chandef); sband = local->hw.wiphy->bands[band]; rates = 0; @@ -4003,8 +4129,7 @@ if (need_basic && basic_rates & BIT(i)) basic = 0x80; - rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, - 5 * (1 << shift)); + rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, 5); *pos++ = basic | (u8) rate; } @@ -4017,13 +4142,12 @@ { struct ieee80211_local *local = sdata->local; struct ieee80211_supported_band *sband; - int rate, shift; + int rate; u8 i, exrates, *pos; u32 basic_rates = sdata->vif.bss_conf.basic_rates; u32 rate_flags; rate_flags = ieee80211_chandef_rate_flags(&sdata->vif.bss_conf.chandef); - shift = ieee80211_vif_get_shift(&sdata->vif); sband = local->hw.wiphy->bands[band]; exrates = 0; @@ -4052,8 +4176,7 @@ continue; if (need_basic && basic_rates & BIT(i)) basic = 0x80; - rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, - 5 * (1 << shift)); + rate = DIV_ROUND_UP(sband->bitrates[i].bitrate, 5); *pos++ = basic | (u8) rate; } } @@ -4097,6 +4220,8 @@ * This function calculates the RX timestamp at the given MPDU offset, taking * into account what the RX timestamp was. An offset of 0 will just normalize * the timestamp to TSF at beginning of MPDU reception. + * + * Returns: the calculated timestamp */ u64 ieee80211_calculate_rx_timestamp(struct ieee80211_local *local, struct ieee80211_rx_status *status, @@ -4212,25 +4337,13 @@ fallthrough; case RX_ENC_LEGACY: { struct ieee80211_supported_band *sband; - int shift = 0; - int bitrate; - - switch (status->bw) { - case RATE_INFO_BW_10: - shift = 1; - break; - case RATE_INFO_BW_5: - shift = 2; - break; - } sband = local->hw.wiphy->bands[status->band]; - bitrate = sband->bitrates[status->rate_idx].bitrate; - ri.legacy = DIV_ROUND_UP(bitrate, (1 << shift)); + ri.legacy = sband->bitrates[status->rate_idx].bitrate; if (status->flag & RX_FLAG_MACTIME_PLCP_START) { if (status->band == NL80211_BAND_5GHZ) { - ts += 20 << shift; + ts += 20; mpdu_offset += 2; } else if (status->enc_flags & RX_ENC_FLAG_SHORTPRE) { ts += 96; @@ -4263,16 +4376,15 @@ struct ieee80211_sub_if_data *sdata; struct cfg80211_chan_def chandef; - /* for interface list, to avoid linking iflist_mtx and chanctx_mtx */ lockdep_assert_wiphy(local->hw.wiphy); - mutex_lock(&local->mtx); list_for_each_entry(sdata, &local->interfaces, list) { /* it might be waiting for the local->mtx, but then * by the time it gets it, sdata->wdev.cac_started * will no longer be true */ - cancel_delayed_work(&sdata->deflink.dfs_cac_timer_work); + wiphy_delayed_work_cancel(local->hw.wiphy, + &sdata->deflink.dfs_cac_timer_work); if (sdata->wdev.cac_started) { chandef = sdata->vif.bss_conf.chandef; @@ -4283,10 +4395,10 @@ GFP_KERNEL); } } - mutex_unlock(&local->mtx); } -void ieee80211_dfs_radar_detected_work(struct work_struct *work) +void ieee80211_dfs_radar_detected_work(struct wiphy *wiphy, + struct wiphy_work *work) { struct ieee80211_local *local = container_of(work, struct ieee80211_local, radar_detected_work); @@ -4294,7 +4406,8 @@ struct ieee80211_chanctx *ctx; int num_chanctx = 0; - mutex_lock(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); + list_for_each_entry(ctx, &local->chanctx_list, list) { if (ctx->replace_state == IEEE80211_CHANCTX_REPLACES_OTHER) continue; @@ -4302,11 +4415,8 @@ num_chanctx++; chandef = ctx->conf.def; } - mutex_unlock(&local->chanctx_mtx); - wiphy_lock(local->hw.wiphy); ieee80211_dfs_cac_cancel(local); - wiphy_unlock(local->hw.wiphy); if (num_chanctx > 1) /* XXX: multi-channel is not supported yet */ @@ -4321,7 +4431,7 @@ trace_api_radar_detected(local); - schedule_work(&local->radar_detected_work); + wiphy_work_queue(hw->wiphy, &local->radar_detected_work); } EXPORT_SYMBOL(ieee80211_radar_detected); @@ -4699,13 +4809,39 @@ ps->dtim_count = dtim_count; } +void ieee80211_force_dtim(struct ieee80211_vif *vif, + unsigned int dtim_count) +{ + struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); + u8 dtim_period = sdata->vif.bss_conf.dtim_period; + struct ps_data *ps; + + if (sdata->vif.type == NL80211_IFTYPE_AP || + sdata->vif.type == NL80211_IFTYPE_AP_VLAN) { + if (!sdata->bss) + return; + + ps = &sdata->bss->ps; + } else if (ieee80211_vif_is_mesh(&sdata->vif)) { + ps = &sdata->u.mesh.ps; + } else { + return; + } + + if (WARN_ON_ONCE(dtim_count >= dtim_period)) + return; + + ps->dtim_count = dtim_count; +} +EXPORT_SYMBOL(ieee80211_force_dtim); + static u8 ieee80211_chanctx_radar_detect(struct ieee80211_local *local, struct ieee80211_chanctx *ctx) { struct ieee80211_link_data *link; u8 radar_detect = 0; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(ctx->replace_state == IEEE80211_CHANCTX_WILL_BE_REPLACED)) return 0; @@ -4746,7 +4882,7 @@ .radar_detect = radar_detect, }; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); if (WARN_ON(hweight32(radar_detect) > 1)) return -EINVAL; @@ -4836,7 +4972,7 @@ int err; struct iface_combination_params params = {0}; - lockdep_assert_held(&local->chanctx_mtx); + lockdep_assert_wiphy(local->hw.wiphy); list_for_each_entry(ctx, &local->chanctx_list, list) { if (ctx->replace_state == IEEE80211_CHANCTX_WILL_BE_REPLACED) @@ -5048,31 +5184,3 @@ return pos; } - -void ieee80211_fragment_element(struct sk_buff *skb, u8 *len_pos, u8 frag_id) -{ - unsigned int elem_len; - - if (!len_pos) - return; - - elem_len = skb->data + skb->len - len_pos - 1; - - while (elem_len > 255) { - /* this one is 255 */ - *len_pos = 255; - /* remaining data gets smaller */ - elem_len -= 255; - /* make space for the fragment ID/len in SKB */ - skb_put(skb, 2); - /* shift back the remaining data to place fragment ID/len */ - memmove(len_pos + 255 + 3, len_pos + 255 + 1, elem_len); - /* place the fragment ID */ - len_pos += 255 + 1; - *len_pos = frag_id; - /* and point to fragment length to update later */ - len_pos++; - } - - *len_pos = elem_len; -} diff -ruw linux-6.4/net/mac80211/vht.c linux-6.4-fbx/net/mac80211/vht.c --- linux-6.4/net/mac80211/vht.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/vht.c 2024-01-19 17:01:19.913848341 +0100 @@ -4,7 +4,7 @@ * * Portions of this file * Copyright(c) 2015 - 2016 Intel Deutschland GmbH - * Copyright (C) 2018 - 2022 Intel Corporation + * Copyright (C) 2018 - 2023 Intel Corporation */ #include @@ -116,12 +116,14 @@ ieee80211_vht_cap_ie_to_sta_vht_cap(struct ieee80211_sub_if_data *sdata, struct ieee80211_supported_band *sband, const struct ieee80211_vht_cap *vht_cap_ie, + const struct ieee80211_vht_cap *vht_cap_ie2, struct link_sta_info *link_sta) { struct ieee80211_sta_vht_cap *vht_cap = &link_sta->pub->vht_cap; struct ieee80211_sta_vht_cap own_cap; u32 cap_info, i; bool have_80mhz; + u32 mpdu_len; memset(vht_cap, 0, sizeof(*vht_cap)); @@ -230,9 +232,11 @@ sizeof(struct ieee80211_vht_mcs_info)); /* copy EXT_NSS_BW Support value or remove the capability */ - if (ieee80211_hw_check(&sdata->local->hw, SUPPORTS_VHT_EXT_NSS_BW)) + if (ieee80211_hw_check(&sdata->local->hw, SUPPORTS_VHT_EXT_NSS_BW)) { + vht_cap->cap |= cap_info & + IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK; vht_cap->cap |= (cap_info & IEEE80211_VHT_CAP_EXT_NSS_BW_MASK); - else + } else vht_cap->vht_mcs.tx_highest &= ~cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); @@ -316,12 +320,23 @@ } link_sta->pub->bandwidth = ieee80211_sta_cur_vht_bw(link_sta); + link_sta->pub->sta_max_bandwidth = link_sta->cur_max_bandwidth; + + /* + * Work around the Cisco 9115 FW 17.3 bug by taking the min of + * both reported MPDU lengths. + */ + mpdu_len = vht_cap->cap & IEEE80211_VHT_CAP_MAX_MPDU_MASK; + if (vht_cap_ie2) + mpdu_len = min_t(u32, mpdu_len, + le32_get_bits(vht_cap_ie2->vht_cap_info, + IEEE80211_VHT_CAP_MAX_MPDU_MASK)); /* * FIXME - should the amsdu len be per link? store per link * and maintain a minimum? */ - switch (vht_cap->cap & IEEE80211_VHT_CAP_MAX_MPDU_MASK) { + switch (mpdu_len) { case IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454: link_sta->pub->agg.max_amsdu_len = IEEE80211_MAX_MPDU_LEN_VHT_11454; break; @@ -678,6 +693,7 @@ break; } + link_sta->pub->sta_max_bandwidth = link_sta->cur_max_bandwidth; new_bw = ieee80211_sta_cur_vht_bw(link_sta); if (new_bw != link_sta->pub->bandwidth) { link_sta->pub->bandwidth = new_bw; diff -ruw linux-6.4/net/mac80211/wep.c linux-6.4-fbx/net/mac80211/wep.c --- linux-6.4/net/mac80211/wep.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/wep.c 2023-11-07 13:38:44.094257566 +0100 @@ -3,6 +3,7 @@ * Software WEP encryption implementation * Copyright 2002, Jouni Malinen * Copyright 2003, Instant802 Networks, Inc. + * Copyright (C) 2023 Intel Corporation */ #include @@ -250,18 +251,18 @@ if (!(status->flag & RX_FLAG_DECRYPTED)) { if (skb_linearize(rx->skb)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; if (ieee80211_wep_decrypt(rx->local, rx->skb, rx->key)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_WEP_DEC_FAIL; } else if (!(status->flag & RX_FLAG_IV_STRIPPED)) { if (!pskb_may_pull(rx->skb, ieee80211_hdrlen(fc) + IEEE80211_WEP_IV_LEN)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_NO_IV; ieee80211_wep_remove_iv(rx->local, rx->skb, rx->key); /* remove ICV */ if (!(status->flag & RX_FLAG_ICV_STRIPPED) && pskb_trim(rx->skb, rx->skb->len - IEEE80211_WEP_ICV_LEN)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_NO_ICV; } return RX_CONTINUE; diff -ruw linux-6.4/net/mac80211/wpa.c linux-6.4-fbx/net/mac80211/wpa.c --- linux-6.4/net/mac80211/wpa.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/mac80211/wpa.c 2023-11-07 13:38:44.094257566 +0100 @@ -3,7 +3,7 @@ * Copyright 2002-2004, Instant802 Networks, Inc. * Copyright 2008, Jouni Malinen * Copyright (C) 2016-2017 Intel Deutschland GmbH - * Copyright (C) 2020-2022 Intel Corporation + * Copyright (C) 2020-2023 Intel Corporation */ #include @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include "ieee80211_i.h" #include "michael.h" @@ -142,7 +142,7 @@ * group keys and only the AP is sending real multicast * frames in the BSS. */ - return RX_DROP_UNUSABLE; + return RX_DROP_U_AP_RX_GROUPCAST; } if (status->flag & RX_FLAG_MMIC_ERROR) @@ -150,10 +150,10 @@ hdrlen = ieee80211_hdrlen(hdr->frame_control); if (skb->len < hdrlen + MICHAEL_MIC_LEN) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_MMIC; if (skb_linearize(rx->skb)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; hdr = (void *)skb->data; data = skb->data + hdrlen; @@ -188,7 +188,7 @@ NL80211_KEYTYPE_PAIRWISE, rx->key ? rx->key->conf.keyidx : -1, NULL, GFP_ATOMIC); - return RX_DROP_UNUSABLE; + return RX_DROP_U_MMIC_FAIL; } static int tkip_encrypt_skb(struct ieee80211_tx_data *tx, struct sk_buff *skb) @@ -276,11 +276,11 @@ return RX_CONTINUE; if (!rx->sta || skb->len - hdrlen < 12) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_TKIP; /* it may be possible to optimize this a bit more */ if (skb_linearize(rx->skb)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; hdr = (void *)skb->data; /* @@ -298,7 +298,7 @@ &rx->tkip.iv32, &rx->tkip.iv16); if (res != TKIP_DECRYPT_OK) - return RX_DROP_UNUSABLE; + return RX_DROP_U_TKIP_FAIL; /* Trim ICV */ if (!(status->flag & RX_FLAG_ICV_STRIPPED)) @@ -523,12 +523,12 @@ if (status->flag & RX_FLAG_DECRYPTED) { if (!pskb_may_pull(rx->skb, hdrlen + IEEE80211_CCMP_HDR_LEN)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_CCMP; if (status->flag & RX_FLAG_MIC_STRIPPED) mic_len = 0; } else { if (skb_linearize(rx->skb)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; } /* reload hdr - skb might have been reallocated */ @@ -536,7 +536,7 @@ data_len = skb->len - hdrlen - IEEE80211_CCMP_HDR_LEN - mic_len; if (!rx->sta || data_len < 0) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_CCMP; if (!(status->flag & RX_FLAG_PN_VALIDATED)) { int res; @@ -574,7 +574,7 @@ /* Remove CCMP header and MIC */ if (pskb_trim(skb, skb->len - mic_len)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_CCMP_MIC; memmove(skb->data + IEEE80211_CCMP_HDR_LEN, skb->data, hdrlen); skb_pull(skb, IEEE80211_CCMP_HDR_LEN); @@ -719,12 +719,12 @@ if (status->flag & RX_FLAG_DECRYPTED) { if (!pskb_may_pull(rx->skb, hdrlen + IEEE80211_GCMP_HDR_LEN)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_GCMP; if (status->flag & RX_FLAG_MIC_STRIPPED) mic_len = 0; } else { if (skb_linearize(rx->skb)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; } /* reload hdr - skb might have been reallocated */ @@ -732,7 +732,7 @@ data_len = skb->len - hdrlen - IEEE80211_GCMP_HDR_LEN - mic_len; if (!rx->sta || data_len < 0) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_GCMP; if (!(status->flag & RX_FLAG_PN_VALIDATED)) { int res; @@ -771,7 +771,7 @@ /* Remove GCMP header and MIC */ if (pskb_trim(skb, skb->len - mic_len)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_GCMP_MIC; memmove(skb->data + IEEE80211_GCMP_HDR_LEN, skb->data, hdrlen); skb_pull(skb, IEEE80211_GCMP_HDR_LEN); @@ -924,7 +924,7 @@ /* management frames are already linear */ if (skb->len < 24 + sizeof(*mmie)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_CMAC; mmie = (struct ieee80211_mmie *) (skb->data + skb->len - sizeof(*mmie)); @@ -974,13 +974,13 @@ /* management frames are already linear */ if (skb->len < 24 + sizeof(*mmie)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_CMAC256; mmie = (struct ieee80211_mmie_16 *) (skb->data + skb->len - sizeof(*mmie)); if (mmie->element_id != WLAN_EID_MMIE || mmie->length != sizeof(*mmie) - 2) - return RX_DROP_UNUSABLE; /* Invalid MMIE */ + return RX_DROP_U_BAD_MMIE; /* Invalid MMIE */ bip_ipn_swap(ipn, mmie->sequence_number); @@ -1073,7 +1073,7 @@ /* management frames are already linear */ if (skb->len < 24 + sizeof(*mmie)) - return RX_DROP_UNUSABLE; + return RX_DROP_U_SHORT_GMAC; mmie = (struct ieee80211_mmie_16 *) (skb->data + skb->len - sizeof(*mmie)); @@ -1097,7 +1097,7 @@ mic = kmalloc(GMAC_MIC_LEN, GFP_ATOMIC); if (!mic) - return RX_DROP_UNUSABLE; + return RX_DROP_U_OOM; if (ieee80211_aes_gmac(key->u.aes_gmac.tfm, aad, nonce, skb->data + 24, skb->len - 24, mic) < 0 || diff -ruw linux-6.4/net/netfilter/Kconfig linux-6.4-fbx/net/netfilter/Kconfig --- linux-6.4/net/netfilter/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/Kconfig 2023-05-22 20:06:45.643891041 +0200 @@ -364,6 +364,7 @@ config NF_CONNTRACK_SIP tristate "SIP protocol support" default m if NETFILTER_ADVANCED=n + select CRYPTO_LIB_SHA256 help SIP is an application-layer control protocol that can establish, modify, and terminate multimedia sessions (conferences) such as diff -ruw linux-6.4/net/netfilter/nf_conntrack_core.c linux-6.4-fbx/net/netfilter/nf_conntrack_core.c --- linux-6.4/net/netfilter/nf_conntrack_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_core.c 2023-06-27 11:47:16.167869662 +0200 @@ -577,12 +577,29 @@ #endif } +#ifdef CONFIG_IP_FFN +extern void ip_ffn_ct_destroy(struct nf_conn *ct); +#endif + +#ifdef CONFIG_IPV6_FFN +extern void ipv6_ffn_ct_destroy(struct nf_conn *ct); +#endif + void nf_ct_destroy(struct nf_conntrack *nfct) { struct nf_conn *ct = (struct nf_conn *)nfct; WARN_ON(refcount_read(&nfct->use) != 0); +#ifdef CONFIG_IP_FFN + if (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num == AF_INET) + ip_ffn_ct_destroy(ct); +#endif +#ifdef CONFIG_IPV6_FFN + if (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num == AF_INET6) + ipv6_ffn_ct_destroy(ct); +#endif + if (unlikely(nf_ct_is_template(ct))) { nf_ct_tmpl_free(ct); return; @@ -1784,7 +1801,7 @@ } spin_unlock_bh(&nf_conntrack_expect_lock); } - if (!exp && tmpl) + if (!exp) __nf_ct_try_assign_helper(ct, tmpl, GFP_ATOMIC); /* Other CPU might have obtained a pointer to this object before it was @@ -2063,6 +2080,10 @@ ct->tuplehash[IP_CT_DIR_REPLY].tuple = *newreply; if (ct->master || (help && !hlist_empty(&help->expectations))) return; + + rcu_read_lock(); + __nf_ct_try_assign_helper(ct, NULL, GFP_ATOMIC); + rcu_read_unlock(); } EXPORT_SYMBOL_GPL(nf_conntrack_alter_reply); @@ -2804,6 +2825,7 @@ nf_conntrack_acct_pernet_init(net); nf_conntrack_tstamp_pernet_init(net); nf_conntrack_ecache_pernet_init(net); + nf_conntrack_helper_pernet_init(net); nf_conntrack_proto_pernet_init(net); return 0; diff -ruw linux-6.4/net/netfilter/nf_conntrack_ftp.c linux-6.4-fbx/net/netfilter/nf_conntrack_ftp.c --- linux-6.4/net/netfilter/nf_conntrack_ftp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_ftp.c 2023-05-22 20:06:45.671891785 +0200 @@ -27,6 +27,10 @@ #include #define HELPER_NAME "ftp" +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) +#include +#include +#endif MODULE_LICENSE("GPL"); MODULE_AUTHOR("Rusty Russell "); @@ -397,6 +401,17 @@ if (unlikely(skb_linearize(skb))) return NF_DROP; +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + if (!ct_ftp_info->is_fbxbridge && skb->dev->fbx_bridge) { + struct fbxbridge *fbxbr; + + fbxbr = skb->dev->fbx_bridge; + ct_ftp_info->is_fbxbridge = 1; + ct_ftp_info->fbxbridge_remote = ntohl(fbxbr->br_remote_ipaddr); + ct_ftp_info->fbxbridge_wan = fbxbr->wan_ipaddr; + } +#endif + th = skb_header_pointer(skb, protoff, sizeof(_tcph), &_tcph); if (th == NULL) return NF_ACCEPT; @@ -483,6 +498,50 @@ * Doesn't matter unless NAT is happening. */ daddr = &ct->tuplehash[!dir].tuple.dst.u3; +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + if (ct_ftp_info->is_fbxbridge && + search[dir][i].ftptype == NF_CT_FTP_PORT) { + unsigned long orig_ip_addr; + unsigned short orig_port; + char buffer[sizeof("nnn,nnn,nnn,nnn,nnn,nnn")]; + unsigned int len; + __be32 addr; + + /* kludge: if we are here, then this is a local pkt + * that has gone through internal fbxbridge snat. + * + * If we see a port command, then we mangle packet to + * change ip address given to the remote bridge + * address */ + + /* check address is packet is the one fbxbridge + * changed */ + orig_ip_addr = cmd.u3.ip; + if (orig_ip_addr != ct_ftp_info->fbxbridge_wan) + goto donttouch; + + /* now mangle the remote address */ + orig_port = cmd.u.tcp.port; + addr = ct_ftp_info->fbxbridge_remote; + len = sprintf(buffer, "%u,%u,%u,%u,%u,%u", + ((unsigned char *)&addr)[0], + ((unsigned char *)&addr)[1], + ((unsigned char *)&addr)[2], + ((unsigned char *)&addr)[3], + orig_port >> 8 , orig_port & 0xFF); + + nf_nat_mangle_tcp_packet(skb, ct, ctinfo, matchoff, + matchlen, buffer, len); + + /* then adjust as if nothing happened */ + matchlen = len; + cmd.u3.ip = ct_ftp_info->fbxbridge_remote; + } +donttouch: + +#endif + + /* Update the ftp info */ if ((cmd.l3num == nf_ct_l3num(ct)) && memcmp(&cmd.u3.all, &ct->tuplehash[dir].tuple.src.u3.all, diff -ruw linux-6.4/net/netfilter/nf_conntrack_helper.c linux-6.4-fbx/net/netfilter/nf_conntrack_helper.c --- linux-6.4/net/netfilter/nf_conntrack_helper.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_helper.c 2023-05-22 20:06:45.671891785 +0200 @@ -37,6 +37,11 @@ EXPORT_SYMBOL_GPL(nf_ct_helper_hsize); static unsigned int nf_ct_helper_count __read_mostly; +static bool nf_ct_auto_assign_helper __read_mostly = true; +module_param_named(nf_conntrack_helper, nf_ct_auto_assign_helper, bool, 0644); +MODULE_PARM_DESC(nf_conntrack_helper, + "Enable automatic conntrack helper assignment (default 0)"); + static DEFINE_MUTEX(nf_ct_nat_helpers_mutex); static struct list_head nf_ct_nat_helpers __read_mostly; @@ -48,6 +53,24 @@ (__force __u16)tuple->src.u.all) % nf_ct_helper_hsize; } +static struct nf_conntrack_helper * +__nf_ct_helper_find(const struct nf_conntrack_tuple *tuple) +{ + struct nf_conntrack_helper *helper; + struct nf_conntrack_tuple_mask mask = { .src.u.all = htons(0xFFFF) }; + unsigned int h; + + if (!nf_ct_helper_count) + return NULL; + + h = helper_hash(tuple); + hlist_for_each_entry_rcu(helper, &nf_ct_helper_hash[h], hnode) { + if (nf_ct_tuple_src_mask_cmp(tuple, &helper->tuple, &mask)) + return helper; + } + return NULL; +} + struct nf_conntrack_helper * __nf_conntrack_helper_find(const char *name, u16 l3num, u8 protonum) { @@ -188,11 +211,33 @@ } EXPORT_SYMBOL_GPL(nf_ct_helper_ext_add); +static struct nf_conntrack_helper * +nf_ct_lookup_helper(struct nf_conn *ct, struct net *net) +{ + struct nf_conntrack_net *cnet = nf_ct_pernet(net); + + if (!cnet->sysctl_auto_assign_helper) { + if (cnet->auto_assign_helper_warned) + return NULL; + if (!__nf_ct_helper_find(&ct->tuplehash[IP_CT_DIR_REPLY].tuple)) + return NULL; + pr_info("nf_conntrack: default automatic helper assignment " + "has been turned off for security reasons and CT-based " + "firewall rule not found. Use the iptables CT target " + "to attach helpers instead.\n"); + cnet->auto_assign_helper_warned = true; + return NULL; + } + + return __nf_ct_helper_find(&ct->tuplehash[IP_CT_DIR_REPLY].tuple); +} + int __nf_ct_try_assign_helper(struct nf_conn *ct, struct nf_conn *tmpl, gfp_t flags) { struct nf_conntrack_helper *helper = NULL; struct nf_conn_help *help; + struct net *net = nf_ct_net(ct); /* We already got a helper explicitly attached. The function * nf_conntrack_alter_reply - in case NAT is in use - asks for looking @@ -203,22 +248,24 @@ if (test_bit(IPS_HELPER_BIT, &ct->status)) return 0; - if (WARN_ON_ONCE(!tmpl)) - return 0; - + if (tmpl != NULL) { help = nfct_help(tmpl); if (help != NULL) { helper = rcu_dereference(help->helper); set_bit(IPS_HELPER_BIT, &ct->status); } + } help = nfct_help(ct); if (helper == NULL) { + helper = nf_ct_lookup_helper(ct, net); + if (helper == NULL) { if (help) RCU_INIT_POINTER(help->helper, NULL); return 0; } + } if (help == NULL) { help = nf_ct_helper_ext_add(ct, flags); @@ -500,6 +547,19 @@ } EXPORT_SYMBOL_GPL(nf_nat_helper_unregister); +void nf_ct_set_auto_assign_helper_warned(struct net *net) +{ + nf_ct_pernet(net)->auto_assign_helper_warned = true; +} +EXPORT_SYMBOL_GPL(nf_ct_set_auto_assign_helper_warned); + +void nf_conntrack_helper_pernet_init(struct net *net) +{ + struct nf_conntrack_net *cnet = nf_ct_pernet(net); + + cnet->sysctl_auto_assign_helper = nf_ct_auto_assign_helper; +} + int nf_conntrack_helper_init(void) { nf_ct_helper_hsize = 1; /* gets rounded up to use one page */ diff -ruw linux-6.4/net/netfilter/nf_conntrack_netlink.c linux-6.4-fbx/net/netfilter/nf_conntrack_netlink.c --- linux-6.4/net/netfilter/nf_conntrack_netlink.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_netlink.c 2023-05-22 20:06:45.675891892 +0200 @@ -2297,6 +2297,11 @@ ct->status |= IPS_HELPER; RCU_INIT_POINTER(help->helper, helper); } + } else { + /* try an implicit helper assignation */ + err = __nf_ct_try_assign_helper(ct, NULL, GFP_ATOMIC); + if (err < 0) + goto err2; } err = ctnetlink_setup_nat(ct, cda); diff -ruw linux-6.4/net/netfilter/nf_conntrack_proto_tcp.c linux-6.4-fbx/net/netfilter/nf_conntrack_proto_tcp.c --- linux-6.4/net/netfilter/nf_conntrack_proto_tcp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_proto_tcp.c 2023-05-22 20:06:45.675891892 +0200 @@ -1247,6 +1247,7 @@ break; } + if (!ct->proto.tcp.no_window_track) { res = tcp_in_window(ct, dir, index, skb, dataoff, th, state); switch (res) { @@ -1260,6 +1261,7 @@ case NFCT_TCP_ACCEPT: break; } + } in_window: /* From now on we have got in-window packets */ ct->proto.tcp.last_index = index; @@ -1333,6 +1335,38 @@ return NF_ACCEPT; } +#ifdef CONFIG_IP_FFN +int external_tcpv4_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET, + .net = nf_ct_net(ct), + }; + return nf_conntrack_tcp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + +#ifdef CONFIG_IPV6_FFN +int external_tcpv6_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET6, + .net = nf_ct_net(ct), + }; + return nf_conntrack_tcp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + #if IS_ENABLED(CONFIG_NF_CT_NETLINK) #include diff -ruw linux-6.4/net/netfilter/nf_conntrack_proto_udp.c linux-6.4-fbx/net/netfilter/nf_conntrack_proto_udp.c --- linux-6.4/net/netfilter/nf_conntrack_proto_udp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_proto_udp.c 2023-05-22 20:06:45.675891892 +0200 @@ -129,6 +129,38 @@ return NF_ACCEPT; } +#ifdef CONFIG_IP_FFN +int external_udpv4_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET, + .net = nf_ct_net(ct), + }; + return nf_conntrack_udp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + +#ifdef CONFIG_IPV6_FFN +int external_udpv6_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET6, + .net = nf_ct_net(ct), + }; + return nf_conntrack_udp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + #ifdef CONFIG_NF_CT_PROTO_UDPLITE static void udplite_error_log(const struct sk_buff *skb, const struct nf_hook_state *state, diff -ruw linux-6.4/net/netfilter/nf_conntrack_sip.c linux-6.4-fbx/net/netfilter/nf_conntrack_sip.c --- linux-6.4/net/netfilter/nf_conntrack_sip.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_sip.c 2023-05-22 20:06:45.675891892 +0200 @@ -35,6 +35,8 @@ MODULE_ALIAS("ip_conntrack_sip"); MODULE_ALIAS_NFCT_HELPER(HELPER_NAME); +#define MAX_CALLS 8 + #define MAX_PORTS 8 static unsigned short ports[MAX_PORTS]; static unsigned int ports_c; @@ -825,7 +827,8 @@ return found; } -static void flush_expectations(struct nf_conn *ct, bool media) +static void __flush_expectations(struct nf_conn *ct, bool media, + const u8 *cid_hash) { struct nf_conn_help *help = nfct_help(ct); struct nf_conntrack_expect *exp; @@ -835,6 +838,15 @@ hlist_for_each_entry_safe(exp, next, &help->expectations, lnode) { if ((exp->class != SIP_EXPECT_SIGNALLING) ^ media) continue; + if (media && cid_hash) { + const struct nf_ct_sip_expect *exp_sip_info; + exp_sip_info = nf_ct_exp_data(exp); + + if (memcmp(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash))) + continue; + } + if (!nf_ct_remove_expect(exp)) continue; if (!media) @@ -843,12 +855,36 @@ spin_unlock_bh(&nf_conntrack_expect_lock); } +static void flush_sig_expectations(struct nf_conn *ct) +{ + return __flush_expectations(ct, false, NULL); +} + +static void flush_media_expectations(struct nf_conn *ct, + const char *msg_data, + unsigned int msg_len) +{ + unsigned int matchoff, matchlen; + u8 cid_hash[SHA256_DIGEST_SIZE]; + struct sha256_state s; + + sha256_init(&s); + if (ct_sip_get_header(ct, msg_data, 0, msg_len, + SIP_HDR_CALL_ID, + &matchoff, &matchlen) > 0) + sha256_update(&s, msg_data + matchoff, matchlen); + sha256_final(&s, cid_hash); + + __flush_expectations(ct, true, cid_hash); +} + static int set_expected_rtp_rtcp(struct sk_buff *skb, unsigned int protoff, unsigned int dataoff, const char **dptr, unsigned int *datalen, union nf_inet_addr *daddr, __be16 port, enum sip_expectation_classes class, - unsigned int mediaoff, unsigned int medialen) + unsigned int mediaoff, unsigned int medialen, + const u8 *cid_hash) { struct nf_conntrack_expect *exp, *rtp_exp, *rtcp_exp; enum ip_conntrack_info ctinfo; @@ -861,6 +897,7 @@ u_int16_t base_port; __be16 rtp_port, rtcp_port; const struct nf_nat_sip_hooks *hooks; + struct nf_ct_sip_expect *exp_sip_info; saddr = NULL; if (sip_direct_media) { @@ -953,18 +990,29 @@ goto err1; } - if (skip_expect) + if (skip_expect) { + exp_sip_info = nf_ct_exp_data(exp); + memcpy(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash)); return NF_ACCEPT; + } rtp_exp = nf_ct_expect_alloc(ct); if (rtp_exp == NULL) goto err1; + exp_sip_info = nf_ct_exp_data(rtp_exp); + memcpy(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash)); nf_ct_expect_init(rtp_exp, class, nf_ct_l3num(ct), saddr, daddr, IPPROTO_UDP, NULL, &rtp_port); + rtcp_exp = nf_ct_expect_alloc(ct); if (rtcp_exp == NULL) goto err2; + exp_sip_info = nf_ct_exp_data(rtcp_exp); + memcpy(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash)); nf_ct_expect_init(rtcp_exp, class, nf_ct_l3num(ct), saddr, daddr, IPPROTO_UDP, NULL, &rtcp_port); @@ -1039,10 +1087,20 @@ const struct nf_nat_sip_hooks *hooks; unsigned int port; const struct sdp_media_type *t; + struct sha256_state s; + u8 cid_hash[SHA256_DIGEST_SIZE]; int ret = NF_ACCEPT; hooks = rcu_dereference(nf_nat_sip_hooks); + /* extract caller id if any */ + sha256_init(&s); + if (ct_sip_get_header(ct, *dptr, 0, *datalen, + SIP_HDR_CALL_ID, + &matchoff, &matchlen) > 0) + sha256_update(&s, *dptr + matchoff, matchlen); + sha256_final(&s, cid_hash); + /* Find beginning of session description */ if (ct_sip_get_sdp_header(ct, *dptr, 0, *datalen, SDP_HDR_VERSION, SDP_HDR_UNSPEC, @@ -1101,7 +1159,7 @@ ret = set_expected_rtp_rtcp(skb, protoff, dataoff, dptr, datalen, &rtp_addr, htons(port), t->class, - mediaoff, medialen); + mediaoff, medialen, cid_hash); if (ret != NF_ACCEPT) { nf_ct_helper_log(skb, ct, "cannot add expectation for voice"); @@ -1145,7 +1203,7 @@ (code >= 200 && code <= 299)) return process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); else if (ct_sip_info->invite_cseq == cseq) - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1162,7 +1220,7 @@ (code >= 200 && code <= 299)) return process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); else if (ct_sip_info->invite_cseq == cseq) - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1179,7 +1237,7 @@ (code >= 200 && code <= 299)) return process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); else if (ct_sip_info->invite_cseq == cseq) - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1193,7 +1251,7 @@ struct nf_ct_sip_master *ct_sip_info = nfct_help_data(ct); unsigned int ret; - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); ret = process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); if (ret == NF_ACCEPT) ct_sip_info->invite_cseq = cseq; @@ -1208,7 +1266,7 @@ enum ip_conntrack_info ctinfo; struct nf_conn *ct = nf_ct_get(skb, &ctinfo); - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1392,7 +1450,7 @@ } flush: - flush_expectations(ct, false); + flush_sig_expectations(ct); return NF_ACCEPT; } @@ -1468,12 +1526,13 @@ * Via: header so that nf_nat_sip can redirect the responses to * the correct port. */ - if (ct_sip_parse_header_uri(ct, *dptr, NULL, *datalen, + if (nf_ct_protonum(ct) == IPPROTO_UDP && + ct_sip_parse_header_uri(ct, *dptr, NULL, *datalen, SIP_HDR_VIA_UDP, NULL, &matchoff, &matchlen, &addr, &port) > 0 && port != ct->tuplehash[dir].tuple.src.u.udp.port && nf_inet_addr_cmp(&addr, &ct->tuplehash[dir].tuple.src.u3)) - ct_sip_info->forced_dport = port; + ct_sip_info->forced_dport[!dir] = port; for (i = 0; i < ARRAY_SIZE(sip_handlers); i++) { const struct sip_handler *handler; @@ -1647,17 +1706,17 @@ }, [SIP_EXPECT_AUDIO] = { .name = "audio", - .max_expected = 2 * IP_CT_DIR_MAX, + .max_expected = MAX_CALLS * 2 * IP_CT_DIR_MAX, .timeout = 3 * 60, }, [SIP_EXPECT_VIDEO] = { .name = "video", - .max_expected = 2 * IP_CT_DIR_MAX, + .max_expected = MAX_CALLS * 2 * IP_CT_DIR_MAX, .timeout = 3 * 60, }, [SIP_EXPECT_IMAGE] = { .name = "image", - .max_expected = IP_CT_DIR_MAX, + .max_expected = MAX_CALLS * IP_CT_DIR_MAX, .timeout = 3 * 60, }, }; @@ -1672,6 +1731,7 @@ int i, ret; NF_CT_HELPER_BUILD_BUG_ON(sizeof(struct nf_ct_sip_master)); + NF_CT_EXPECT_BUILD_BUG_ON(sizeof(struct nf_ct_sip_expect)); if (ports_c == 0) ports[ports_c++] = SIP_PORT; diff -ruw linux-6.4/net/netfilter/nf_conntrack_standalone.c linux-6.4-fbx/net/netfilter/nf_conntrack_standalone.c --- linux-6.4/net/netfilter/nf_conntrack_standalone.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_conntrack_standalone.c 2023-05-22 20:06:45.675891892 +0200 @@ -557,6 +557,7 @@ NF_SYSCTL_CT_LOG_INVALID, NF_SYSCTL_CT_EXPECT_MAX, NF_SYSCTL_CT_ACCT, + NF_SYSCTL_CT_HELPER, #ifdef CONFIG_NF_CONNTRACK_EVENTS NF_SYSCTL_CT_EVENTS, #endif @@ -674,6 +675,14 @@ .extra1 = SYSCTL_ZERO, .extra2 = SYSCTL_ONE, }, + [NF_SYSCTL_CT_HELPER] = { + .procname = "nf_conntrack_helper", + .maxlen = sizeof(u8), + .mode = 0644, + .proc_handler = proc_dou8vec_minmax, + .extra1 = SYSCTL_ZERO, + .extra2 = SYSCTL_ONE, + }, #ifdef CONFIG_NF_CONNTRACK_EVENTS [NF_SYSCTL_CT_EVENTS] = { .procname = "nf_conntrack_events", @@ -1079,6 +1088,7 @@ table[NF_SYSCTL_CT_CHECKSUM].data = &net->ct.sysctl_checksum; table[NF_SYSCTL_CT_LOG_INVALID].data = &net->ct.sysctl_log_invalid; table[NF_SYSCTL_CT_ACCT].data = &net->ct.sysctl_acct; + table[NF_SYSCTL_CT_HELPER].data = &cnet->sysctl_auto_assign_helper; #ifdef CONFIG_NF_CONNTRACK_EVENTS table[NF_SYSCTL_CT_EVENTS].data = &net->ct.sysctl_events; #endif diff -ruw linux-6.4/net/netfilter/nf_nat_core.c linux-6.4-fbx/net/netfilter/nf_nat_core.c --- linux-6.4/net/netfilter/nf_nat_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_nat_core.c 2023-05-22 20:06:45.679891998 +0200 @@ -641,6 +641,11 @@ else ct->status |= IPS_SRC_NAT_DONE; + if (maniptype == NF_NAT_MANIP_SRC) { + ct->nat_src_proto_min = range->min_proto; + ct->nat_src_proto_max = range->max_proto; + } + return NF_ACCEPT; } EXPORT_SYMBOL(nf_nat_setup_info); diff -ruw linux-6.4/net/netfilter/nf_nat_ftp.c linux-6.4-fbx/net/netfilter/nf_nat_ftp.c --- linux-6.4/net/netfilter/nf_nat_ftp.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_nat_ftp.c 2023-05-22 20:06:45.679891998 +0200 @@ -69,7 +69,8 @@ struct nf_conntrack_expect *exp) { union nf_inet_addr newaddr; - u_int16_t port; + u_int16_t port, sport, eport; + unsigned int i; int dir = CTINFO2DIR(ctinfo); struct nf_conn *ct = exp->master; char buffer[sizeof("|1||65535|") + INET6_ADDRSTRLEN]; @@ -86,7 +87,42 @@ * this one. */ exp->expectfn = nf_nat_follow_master; - port = nf_nat_exp_find_port(exp, ntohs(exp->saved_proto.tcp.port)); + if (dir == IP_CT_DIR_ORIGINAL && + (ct->status & IPS_SRC_NAT) && + ct->nat_src_proto_min.all && + ct->nat_src_proto_max.all) { + sport = ntohs(ct->nat_src_proto_min.all); + eport = ntohs(ct->nat_src_proto_max.all); + } else { + sport = 1024; + eport = 65535; + } + + port = ntohs(exp->saved_proto.tcp.port); + if (port < sport || port > eport) { + get_random_bytes(&port, sizeof (port)); + port %= eport - sport; + port += sport; + } + + /* Try to get same port: if not, try to change it. */ + for (i = 0; i < eport - sport + 1; i++) { + int ret; + + exp->tuple.dst.u.tcp.port = htons(port); + ret = nf_ct_expect_related(exp, 0); + if (ret == 0) + break; + else if (ret != -EBUSY) { + port = 0; + break; + } + + port++; + if (port > eport) + port = sport; + } + if (port == 0) { nf_ct_helper_log(skb, exp->master, "all ports in use"); return NF_DROP; diff -ruw linux-6.4/net/netfilter/nf_nat_helper.c linux-6.4-fbx/net/netfilter/nf_nat_helper.c --- linux-6.4/net/netfilter/nf_nat_helper.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_nat_helper.c 2023-05-22 20:06:45.679891998 +0200 @@ -188,6 +188,14 @@ range.flags = NF_NAT_RANGE_MAP_IPS; range.min_addr = range.max_addr = ct->master->tuplehash[!exp->dir].tuple.dst.u3; + + if (ct->master->nat_src_proto_min.all && + ct->master->nat_src_proto_max.all) { + range.flags |= NF_NAT_RANGE_PROTO_SPECIFIED; + range.min_proto = ct->master->nat_src_proto_min; + range.max_proto = ct->master->nat_src_proto_max; + } + nf_nat_setup_info(ct, &range, NF_NAT_MANIP_SRC); /* For DST manip, map port here to where it's expected. */ diff -ruw linux-6.4/net/netfilter/nf_nat_proto.c linux-6.4-fbx/net/netfilter/nf_nat_proto.c --- linux-6.4/net/netfilter/nf_nat_proto.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_nat_proto.c 2023-02-27 13:42:32.630771810 +0100 @@ -385,6 +385,8 @@ { #if IS_ENABLED(CONFIG_IPV6) struct ipv6hdr *ipv6h; + const __be32 *to; + __be32 *from; __be16 frag_off; int hdroff; u8 nexthdr; @@ -407,10 +409,24 @@ ipv6h = (void *)skb->data + iphdroff; manip_addr: - if (maniptype == NF_NAT_MANIP_SRC) - ipv6h->saddr = target->src.u3.in6; - else - ipv6h->daddr = target->dst.u3.in6; + if (maniptype == NF_NAT_MANIP_SRC) { + from = ipv6h->saddr.s6_addr32; + to = target->src.u3.in6.s6_addr32; + } else { + from = ipv6h->daddr.s6_addr32; + to = target->dst.u3.in6.s6_addr32; + } + + if (skb->ip_summed == CHECKSUM_COMPLETE) { + __be32 diff[] = { + ~from[0], ~from[1], ~from[2], ~from[3], + to[0], to[1], to[2], to[3], + }; + + skb->csum = ~csum_partial(diff, sizeof(diff), ~skb->csum); + } + + memcpy(from, to, sizeof (struct in6_addr)); #endif return true; diff -ruw linux-6.4/net/netfilter/nf_nat_sip.c linux-6.4-fbx/net/netfilter/nf_nat_sip.c --- linux-6.4/net/netfilter/nf_nat_sip.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nf_nat_sip.c 2023-05-22 20:06:45.679891998 +0200 @@ -111,8 +111,11 @@ } else if (nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.dst.u3, addr) && ct->tuplehash[dir].tuple.dst.u.udp.port == port) { newaddr = ct->tuplehash[!dir].tuple.src.u3; - newport = ct_sip_info->forced_dport ? : + if (nf_ct_protonum(ct) == IPPROTO_UDP) + newport = ct_sip_info->forced_dport[dir] ? : ct->tuplehash[!dir].tuple.src.u.udp.port; + else + newport = ct->tuplehash[!dir].tuple.src.u.udp.port; } else return 1; @@ -279,7 +282,8 @@ } /* Mangle destination port for Cisco phones, then fix up checksums */ - if (dir == IP_CT_DIR_REPLY && ct_sip_info->forced_dport) { + if (nf_ct_protonum(ct) == IPPROTO_UDP && + dir == IP_CT_DIR_REPLY && ct_sip_info->forced_dport[dir]) { struct udphdr *uh; if (skb_ensure_writable(skb, skb->len)) { @@ -288,7 +292,7 @@ } uh = (void *)skb->data + protoff; - uh->dest = ct_sip_info->forced_dport; + uh->dest = ct_sip_info->forced_dport[dir]; if (!nf_nat_mangle_udp_packet(skb, ct, ctinfo, protoff, 0, 0, NULL, 0)) { @@ -397,7 +401,7 @@ /* If the signalling port matches the connection's source port in the * original direction, try to use the destination port in the opposite * direction. */ - srcport = ct_sip_info->forced_dport ? : + srcport = ct_sip_info->forced_dport[dir] ? : ct->tuplehash[dir].tuple.src.u.udp.port; if (exp->tuple.dst.u.udp.port == srcport) port = ntohs(ct->tuplehash[!dir].tuple.dst.u.udp.port); diff -ruw linux-6.4/net/netfilter/nfnetlink.c linux-6.4-fbx/net/netfilter/nfnetlink.c --- linux-6.4/net/netfilter/nfnetlink.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/netfilter/nfnetlink.c 2023-06-27 11:47:16.171869771 +0200 @@ -648,7 +648,10 @@ skb->len < nlh->nlmsg_len) return; - if (!netlink_net_capable(skb, CAP_NET_ADMIN)) { + if (NFNL_SUBSYS_ID(nlh->nlmsg_type) == NFNL_SUBSYS_CTNETLINK && + NFNL_MSG_TYPE(nlh->nlmsg_type) == 1 /* IPCTNL_MSG_CT_GET */) { + pr_debug("Carving out access exception for conntrack get; does not work for batch queries\n"); + } else if (!netlink_net_capable(skb, CAP_NET_ADMIN)) { netlink_ack(skb, nlh, -EPERM, NULL); return; } diff -ruw linux-6.4/net/sched/act_police.c linux-6.4-fbx/net/sched/act_police.c --- linux-6.4/net/sched/act_police.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/sched/act_police.c 2023-11-07 13:38:44.098257675 +0100 @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff -ruw linux-6.4/net/sched/sch_drr.c linux-6.4-fbx/net/sched/sch_drr.c --- linux-6.4/net/sched/sch_drr.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/sched/sch_drr.c 2023-05-22 20:06:45.951899233 +0200 @@ -325,7 +325,9 @@ cl = drr_find_class(sch, res.classid); return cl; } - return NULL; + + /* default to first minor if it exists, or drop */ + return drr_find_class(sch, TC_H_MAKE(TC_H_MAJ(sch->handle), 1)); } static int drr_enqueue(struct sk_buff *skb, struct Qdisc *sch, diff -ruw linux-6.4/net/socket.c linux-6.4-fbx/net/socket.c --- linux-6.4/net/socket.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/socket.c 2023-05-22 20:06:46.211906149 +0200 @@ -1220,6 +1220,29 @@ return err; } +static DEFINE_MUTEX(fbxbridge_ioctl_mutex); +static int (*fbxbridge_ioctl_hook)(struct net *, unsigned int cmd, void __user *arg) = NULL; + +void fbxbridge_set(int (*hook)(struct net *, unsigned int, void __user *)) +{ + mutex_lock(&fbxbridge_ioctl_mutex); + fbxbridge_ioctl_hook = hook; + mutex_unlock(&fbxbridge_ioctl_mutex); +} + +static DEFINE_MUTEX(fbxdiverter_ioctl_mutex); +static int (*fbxdiverter_ioctl_hook) (struct net *, unsigned int cmd, void __user *arg) = NULL; + +void fbxdiverter_ioctl_set(int (*hook) (struct net *, unsigned int, + void __user *)) +{ + mutex_lock(&fbxdiverter_ioctl_mutex); + fbxdiverter_ioctl_hook = hook; + mutex_unlock(&fbxdiverter_ioctl_mutex); +} + +EXPORT_SYMBOL(fbxdiverter_ioctl_set); + /* * With an ioctl, arg may well be a user mode pointer, but we don't know * what to do with it - that's up to the protocol still. @@ -1289,6 +1312,17 @@ err = open_related_ns(&net->ns, get_net_ns); break; + case SIOCGFBXDIVERT: + case SIOCSFBXDIVERT: + err = -ENOPKG; + if (!fbxdiverter_ioctl_hook) + request_module("fbxdiverter"); + + mutex_lock(&fbxdiverter_ioctl_mutex); + if (fbxdiverter_ioctl_hook) + err = fbxdiverter_ioctl_hook(net, cmd, argp); + mutex_unlock(&fbxdiverter_ioctl_mutex); + break; case SIOCGSTAMP_OLD: case SIOCGSTAMPNS_OLD: if (!sock->ops->gettstamp) { @@ -1314,6 +1348,17 @@ err = dev_ifconf(net, argp); break; + case SIOCGFBXBRIDGE: + case SIOCSFBXBRIDGE: + err = -ENOPKG; + if (!fbxbridge_ioctl_hook) + request_module("fbxbridge"); + + mutex_lock(&fbxbridge_ioctl_mutex); + if (fbxbridge_ioctl_hook) + err = fbxbridge_ioctl_hook(net, cmd, argp); + mutex_unlock(&fbxbridge_ioctl_mutex); + break; default: err = sock_do_ioctl(net, sock, cmd, arg); break; diff -ruw linux-6.4/net/unix/Kconfig linux-6.4-fbx/net/unix/Kconfig --- linux-6.4/net/unix/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/unix/Kconfig 2023-04-05 14:58:59.067863051 +0200 @@ -30,6 +30,9 @@ depends on UNIX default y +config UNIX_ABSTRACT_IGNORE_NETNS + bool "make abstract namespace global to all network namespaces" + config UNIX_DIAG tristate "UNIX: socket monitoring interface" depends on UNIX diff -ruw linux-6.4/net/unix/af_unix.c linux-6.4-fbx/net/unix/af_unix.c --- linux-6.4/net/unix/af_unix.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/unix/af_unix.c 2023-06-27 11:47:16.191870315 +0200 @@ -1116,8 +1116,19 @@ if (sunaddr->sun_path[0]) sk = unix_find_bsd(sunaddr, addr_len, type); - else + else { +#ifdef CONFIG_UNIX_ABSTRACT_IGNORE_NETNS + down_read(&net_rwsem); + for_each_net(net) { +#endif sk = unix_find_abstract(net, sunaddr, addr_len, type); +#ifdef CONFIG_UNIX_ABSTRACT_IGNORE_NETNS + if (!IS_ERR(sk)) + break; + } + up_read(&net_rwsem); +#endif + } return sk; } diff -ruw linux-6.4/net/wireless/Kconfig linux-6.4-fbx/net/wireless/Kconfig --- linux-6.4/net/wireless/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/Kconfig 2024-02-14 17:43:53.023127909 +0100 @@ -177,6 +177,9 @@ If unsure, say N. +config CFG80211_DFS_CACHE + bool "keep each channel dfs state in global cache" + config CFG80211_CRDA_SUPPORT bool "support CRDA" if EXPERT default y @@ -201,6 +204,22 @@ Drivers should select this option if they require cfg80211's wext compatibility symbols to be exported. +config CFG80211_KUNIT_TEST + tristate "KUnit tests for cfg80211" if !KUNIT_ALL_TESTS + depends on KUNIT + depends on CFG80211 + default KUNIT_ALL_TESTS + depends on !KERNEL_6_2 + help + Enable this option to test cfg80211 functions with kunit. + + If unsure, say N. + +config FBX80211 + bool "fbx genl family" + help + Support for freebox specific genl family + endif # CFG80211 config LIB80211 diff -ruw linux-6.4/net/wireless/Makefile linux-6.4-fbx/net/wireless/Makefile --- linux-6.4/net/wireless/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/Makefile 2023-12-12 17:24:34.179627645 +0100 @@ -4,6 +4,7 @@ obj-$(CONFIG_LIB80211_CRYPT_WEP) += lib80211_crypt_wep.o obj-$(CONFIG_LIB80211_CRYPT_CCMP) += lib80211_crypt_ccmp.o obj-$(CONFIG_LIB80211_CRYPT_TKIP) += lib80211_crypt_tkip.o +obj-y += tests/ obj-$(CONFIG_WEXT_CORE) += wext-core.o obj-$(CONFIG_WEXT_PROC) += wext-proc.o @@ -24,6 +25,8 @@ cfg80211-y += extra-certs.o endif +cfg80211-$(CONFIG_FBX80211) += nlfbx.o + $(obj)/shipped-certs.c: $(wildcard $(srctree)/$(src)/certs/*.hex) @$(kecho) " GEN $@" $(Q)(echo '#include "reg.h"'; \ diff -ruw linux-6.4/net/wireless/ap.c linux-6.4-fbx/net/wireless/ap.c --- linux-6.4/net/wireless/ap.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/ap.c 2023-11-07 13:38:44.098257675 +0100 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Parts of this file are - * Copyright (C) 2022 Intel Corporation + * Copyright (C) 2022-2023 Intel Corporation */ #include #include @@ -18,7 +18,7 @@ struct wireless_dev *wdev = dev->ieee80211_ptr; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!rdev->ops->stop_ap) return -EOPNOTSUPP; @@ -52,7 +52,7 @@ return err; } -int __cfg80211_stop_ap(struct cfg80211_registered_device *rdev, +int cfg80211_stop_ap(struct cfg80211_registered_device *rdev, struct net_device *dev, int link_id, bool notify) { @@ -72,17 +72,3 @@ return ret; } - -int cfg80211_stop_ap(struct cfg80211_registered_device *rdev, - struct net_device *dev, int link_id, - bool notify) -{ - struct wireless_dev *wdev = dev->ieee80211_ptr; - int err; - - wdev_lock(wdev); - err = __cfg80211_stop_ap(rdev, dev, link_id, notify); - wdev_unlock(wdev); - - return err; -} diff -ruw linux-6.4/net/wireless/chan.c linux-6.4-fbx/net/wireless/chan.c --- linux-6.4/net/wireless/chan.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/chan.c 2024-02-14 17:43:53.027128018 +0100 @@ -32,6 +32,8 @@ chandef->center_freq2 = 0; chandef->edmg.bw_config = 0; chandef->edmg.channels = 0; + chandef->ru_punct_bitmap = 0; + chandef->ru_punct_bitmap_supp_he = 0; switch (chan_type) { case NL80211_CHAN_NO_HT: @@ -445,6 +447,77 @@ } EXPORT_SYMBOL(cfg80211_chandef_compatible); +static inline u32 +dfs_cache_channel_to_khz(const struct cfg80211_chan_dfs_cache *cd) +{ + return MHZ_TO_KHZ(cd->center_freq) + cd->freq_offset; +} + +static struct cfg80211_chan_dfs_cache * +__get_dfs_chan_cache(struct ieee80211_channel *c) +{ + struct cfg80211_chan_dfs_cache *cd; + u32 freq; + + freq = ieee80211_channel_to_khz(c); + list_for_each_entry(cd, &cfg80211_dfs_cache.bands[c->band], next) { + if (dfs_cache_channel_to_khz(cd) == freq) + return cd; + } + return NULL; +} + +struct cfg80211_chan_dfs_cache * +cfg80211_get_dfs_chan_cache(struct ieee80211_channel *c) +{ + struct cfg80211_chan_dfs_cache *cd; + u32 freq; + + freq = ieee80211_channel_to_khz(c); + list_for_each_entry(cd, &cfg80211_dfs_cache.bands[c->band], next) { + if (dfs_cache_channel_to_khz(cd) == freq) + return cd; + } + return NULL; +} + +void cfg80211_flush_dfs_cache(void) +{ + struct cfg80211_chan_dfs_cache *cd, *tmp; + size_t i; + + for (i = 0; i < ARRAY_SIZE(cfg80211_dfs_cache.bands); i++) { + list_for_each_entry_safe(cd, tmp, + &cfg80211_dfs_cache.bands[i], next) { + list_del(&cd->next); + kfree(cd); + } + } +} + +static void set_dfs_cache_state(struct ieee80211_channel *c, + enum nl80211_dfs_state dfs_state) +{ + struct cfg80211_chan_dfs_cache *cd; + + mutex_lock(&cfg80211_dfs_cache.mtx); + + cd = __get_dfs_chan_cache(c); + if (!cd) { + cd = kzalloc(sizeof (*cd), GFP_KERNEL); + if (!cd) + return; + cd->center_freq = c->center_freq; + cd->freq_offset = c->freq_offset; + list_add(&cd->next, &cfg80211_dfs_cache.bands[c->band]); + } + + cd->dfs_state = dfs_state; + cd->dfs_state_entered = jiffies; + + mutex_unlock(&cfg80211_dfs_cache.mtx); +} + static void cfg80211_set_chans_dfs_state(struct wiphy *wiphy, u32 center_freq, u32 bandwidth, enum nl80211_dfs_state dfs_state) @@ -459,6 +532,8 @@ if (!c || !(c->flags & IEEE80211_CHAN_RADAR)) continue; + if (IS_ENABLED(CONFIG_CFG80211_DFS_CACHE)) + set_dfs_cache_state(c, dfs_state); c->dfs_state = dfs_state; c->dfs_state_entered = jiffies; } @@ -666,6 +741,7 @@ return (r1 + r2 > 0); } +EXPORT_SYMBOL(cfg80211_chandef_dfs_usable); /* * Checks if center frequency of chan falls with in the bandwidth @@ -713,7 +789,7 @@ { unsigned int link; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); switch (wdev->iftype) { case NL80211_IFTYPE_AP: @@ -782,19 +858,15 @@ { struct wireless_dev *wdev; + lockdep_assert_wiphy(wiphy); + list_for_each_entry(wdev, &wiphy->wdev_list, list) { - wdev_lock(wdev); - if (!cfg80211_beaconing_iface_active(wdev)) { - wdev_unlock(wdev); + if (!cfg80211_beaconing_iface_active(wdev)) continue; - } - if (cfg80211_wdev_on_sub_chan(wdev, chan, false)) { - wdev_unlock(wdev); + if (cfg80211_wdev_on_sub_chan(wdev, chan, false)) return true; } - wdev_unlock(wdev); - } return false; } @@ -823,14 +895,18 @@ if (!(chan->flags & IEEE80211_CHAN_RADAR)) return false; - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { + bool found; + if (!reg_dfs_domain_same(wiphy, &rdev->wiphy)) continue; - if (cfg80211_is_wiphy_oper_chan(&rdev->wiphy, chan)) - return true; + wiphy_lock(&rdev->wiphy); + found = cfg80211_is_wiphy_oper_chan(&rdev->wiphy, chan) || + cfg80211_offchan_chain_is_active(rdev, chan); + wiphy_unlock(&rdev->wiphy); - if (cfg80211_offchan_chain_is_active(rdev, chan)) + if (found) return true; } @@ -965,6 +1041,7 @@ return max(t1, t2); } +EXPORT_SYMBOL(cfg80211_chandef_dfs_cac_time); static bool cfg80211_secondary_chans_ok(struct wiphy *wiphy, u32 center_freq, u32 bandwidth, @@ -1321,10 +1398,7 @@ list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { bool ret; - wdev_lock(wdev); ret = cfg80211_ir_permissive_check_wdev(iftype, wdev, chan); - wdev_unlock(wdev); - if (ret) return ret; } @@ -1433,17 +1507,10 @@ struct cfg80211_chan_def *wdev_chandef(struct wireless_dev *wdev, unsigned int link_id) { - /* - * We need to sort out the locking here - in some cases - * where we get here we really just don't care (yet) - * about the valid links, but in others we do. But we - * get here with various driver cases, so we cannot - * easily require the wdev mutex. - */ - if (link_id || wdev->valid_links & BIT(0)) { - ASSERT_WDEV_LOCK(wdev); - WARN_ON(!(wdev->valid_links & BIT(link_id))); - } + lockdep_assert_wiphy(wdev->wiphy); + + WARN_ON(wdev->valid_links && !(wdev->valid_links & BIT(link_id))); + WARN_ON(!wdev->valid_links && link_id > 0); switch (wdev->iftype) { case NL80211_IFTYPE_MESH_POINT: diff -ruw linux-6.4/net/wireless/core.c linux-6.4-fbx/net/wireless/core.c --- linux-6.4/net/wireless/core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/core.c 2024-02-14 17:43:53.027128018 +0100 @@ -25,6 +25,7 @@ #include #include #include "nl80211.h" +#include "nlfbx.h" #include "core.h" #include "sysfs.h" #include "debugfs.h" @@ -54,13 +55,17 @@ MODULE_PARM_DESC(cfg80211_disable_40mhz_24ghz, "Disable 40MHz support in the 2.4GHz band"); +/* global dfs cache */ +struct cfg80211_dfs_cache cfg80211_dfs_cache; +static struct dentry *cfg80211_dfs_cache_debugfs; + struct cfg80211_registered_device *cfg80211_rdev_by_wiphy_idx(int wiphy_idx) { struct cfg80211_registered_device *result = NULL, *rdev; ASSERT_RTNL(); - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { if (rdev->wiphy_idx == wiphy_idx) { result = rdev; break; @@ -116,7 +121,7 @@ } /* Ensure another device does not already have this name. */ - list_for_each_entry(rdev2, &cfg80211_rdev_list, list) + for_each_rdev(rdev2) if (strcmp(newname, wiphy_name(&rdev2->wiphy)) == 0) return -EINVAL; @@ -129,6 +134,7 @@ int result; ASSERT_RTNL(); + lockdep_assert_wiphy(&rdev->wiphy); /* Ignore nop renames */ if (strcmp(newname, wiphy_name(&rdev->wiphy)) == 0) @@ -195,6 +201,8 @@ continue; nl80211_notify_iface(rdev, wdev, NL80211_CMD_DEL_INTERFACE); } + + wiphy_lock(&rdev->wiphy); nl80211_notify_wiphy(rdev, NL80211_CMD_DEL_WIPHY); wiphy_net_set(&rdev->wiphy, net); @@ -203,6 +211,8 @@ WARN_ON(err); nl80211_notify_wiphy(rdev, NL80211_CMD_NEW_WIPHY); + wiphy_unlock(&rdev->wiphy); + list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { if (!wdev->netdev) continue; @@ -360,7 +370,8 @@ rtnl_unlock(); } -static void cfg80211_sched_scan_stop_wk(struct work_struct *work) +static void cfg80211_sched_scan_stop_wk(struct wiphy *wiphy, + struct wiphy_work *work) { struct cfg80211_registered_device *rdev; struct cfg80211_sched_scan_request *req, *tmp; @@ -368,12 +379,10 @@ rdev = container_of(work, struct cfg80211_registered_device, sched_scan_stop_wk); - wiphy_lock(&rdev->wiphy); list_for_each_entry_safe(req, tmp, &rdev->sched_scan_req_list, list) { if (req->nl_owner_dead) cfg80211_stop_sched_scan_req(rdev, req, false); } - wiphy_unlock(&rdev->wiphy); } static void cfg80211_propagate_radar_detect_wk(struct work_struct *work) @@ -408,6 +417,34 @@ rtnl_unlock(); } +static void cfg80211_wiphy_work(struct work_struct *work) +{ + struct cfg80211_registered_device *rdev; + struct wiphy_work *wk; + + rdev = container_of(work, struct cfg80211_registered_device, wiphy_work); + + wiphy_lock(&rdev->wiphy); + if (rdev->suspended) + goto out; + + spin_lock_irq(&rdev->wiphy_work_lock); + wk = list_first_entry_or_null(&rdev->wiphy_work_list, + struct wiphy_work, entry); + if (wk) { + list_del_init(&wk->entry); + if (!list_empty(&rdev->wiphy_work_list)) + schedule_work(work); + spin_unlock_irq(&rdev->wiphy_work_lock); + + wk->func(&rdev->wiphy, wk); + } else { + spin_unlock_irq(&rdev->wiphy_work_lock); + } +out: + wiphy_unlock(&rdev->wiphy); +} + /* exported functions */ struct wiphy *wiphy_new_nm(const struct cfg80211_ops *ops, int sizeof_priv, @@ -495,7 +532,7 @@ spin_lock_init(&rdev->bss_lock); INIT_LIST_HEAD(&rdev->bss_list); INIT_LIST_HEAD(&rdev->sched_scan_req_list); - INIT_WORK(&rdev->scan_done_wk, __cfg80211_scan_done); + wiphy_work_init(&rdev->scan_done_wk, __cfg80211_scan_done); INIT_DELAYED_WORK(&rdev->dfs_update_channels_wk, cfg80211_dfs_channels_update_work); #ifdef CONFIG_CFG80211_WEXT @@ -508,7 +545,7 @@ device_enable_async_suspend(&rdev->wiphy.dev); INIT_WORK(&rdev->destroy_work, cfg80211_destroy_iface_wk); - INIT_WORK(&rdev->sched_scan_stop_wk, cfg80211_sched_scan_stop_wk); + wiphy_work_init(&rdev->sched_scan_stop_wk, cfg80211_sched_scan_stop_wk); INIT_WORK(&rdev->sched_scan_res_wk, cfg80211_sched_scan_results_wk); INIT_WORK(&rdev->propagate_radar_detect_wk, cfg80211_propagate_radar_detect_wk); @@ -533,6 +570,9 @@ return NULL; } + INIT_WORK(&rdev->wiphy_work, cfg80211_wiphy_work); + INIT_LIST_HEAD(&rdev->wiphy_work_list); + spin_lock_init(&rdev->wiphy_work_lock); INIT_WORK(&rdev->rfkill_block, cfg80211_rfkill_block_work); INIT_WORK(&rdev->conn_work, cfg80211_conn_work); INIT_WORK(&rdev->event_work, cfg80211_event_work); @@ -558,6 +598,7 @@ rdev->wiphy.max_sched_scan_plans = 1; rdev->wiphy.max_sched_scan_plan_interval = U32_MAX; + rdev->wiphy.dev_port = -1; return &rdev->wiphy; } @@ -721,22 +762,6 @@ return -EINVAL; } - /* - * if a wiphy has unsupported modes for regulatory channel enforcement, - * opt-out of enforcement checking - */ - if (wiphy->interface_modes & ~(BIT(NL80211_IFTYPE_STATION) | - BIT(NL80211_IFTYPE_P2P_CLIENT) | - BIT(NL80211_IFTYPE_AP) | - BIT(NL80211_IFTYPE_MESH_POINT) | - BIT(NL80211_IFTYPE_P2P_GO) | - BIT(NL80211_IFTYPE_ADHOC) | - BIT(NL80211_IFTYPE_P2P_DEVICE) | - BIT(NL80211_IFTYPE_NAN) | - BIT(NL80211_IFTYPE_AP_VLAN) | - BIT(NL80211_IFTYPE_MONITOR))) - wiphy->regulatory_flags |= REGULATORY_IGNORE_STALE_KICKOFF; - if (WARN_ON((wiphy->regulatory_flags & REGULATORY_WIPHY_SELF_MANAGED) && (wiphy->regulatory_flags & (REGULATORY_CUSTOM_REG | @@ -941,8 +966,10 @@ rdev->wiphy.features |= NL80211_FEATURE_SCAN_FLUSH; rtnl_lock(); + wiphy_lock(&rdev->wiphy); res = device_add(&rdev->wiphy.dev); if (res) { + wiphy_unlock(&rdev->wiphy); rtnl_unlock(); return res; } @@ -956,6 +983,7 @@ cfg80211_debugfs_rdev_add(rdev); nl80211_notify_wiphy(rdev, NL80211_CMD_NEW_WIPHY); + wiphy_unlock(&rdev->wiphy); /* set up regulatory info */ wiphy_regulatory_register(wiphy); @@ -1027,6 +1055,36 @@ } EXPORT_SYMBOL(wiphy_rfkill_start_polling); +void cfg80211_process_wiphy_works(struct cfg80211_registered_device *rdev, + struct wiphy_work *end) +{ + unsigned int runaway_limit = 100; + unsigned long flags; + + lockdep_assert_held(&rdev->wiphy.mtx); + + spin_lock_irqsave(&rdev->wiphy_work_lock, flags); + while (!list_empty(&rdev->wiphy_work_list)) { + struct wiphy_work *wk; + + wk = list_first_entry(&rdev->wiphy_work_list, + struct wiphy_work, entry); + list_del_init(&wk->entry); + spin_unlock_irqrestore(&rdev->wiphy_work_lock, flags); + + wk->func(&rdev->wiphy, wk); + + spin_lock_irqsave(&rdev->wiphy_work_lock, flags); + + if (wk == end) + break; + + if (WARN_ON(--runaway_limit == 0)) + INIT_LIST_HEAD(&rdev->wiphy_work_list); + } + spin_unlock_irqrestore(&rdev->wiphy_work_lock, flags); +} + void wiphy_unregister(struct wiphy *wiphy) { struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); @@ -1065,25 +1123,29 @@ cfg80211_rdev_list_generation++; device_del(&rdev->wiphy.dev); +#ifdef CONFIG_PM + if (rdev->wiphy.wowlan_config && rdev->ops->set_wakeup) + rdev_set_wakeup(rdev, false); +#endif + + /* surely nothing is reachable now, clean up work */ + cfg80211_process_wiphy_works(rdev, NULL); wiphy_unlock(&rdev->wiphy); rtnl_unlock(); - flush_work(&rdev->scan_done_wk); + /* this has nothing to do now but make sure it's gone */ + cancel_work_sync(&rdev->wiphy_work); + cancel_work_sync(&rdev->conn_work); flush_work(&rdev->event_work); cancel_delayed_work_sync(&rdev->dfs_update_channels_wk); cancel_delayed_work_sync(&rdev->background_cac_done_wk); flush_work(&rdev->destroy_work); - flush_work(&rdev->sched_scan_stop_wk); flush_work(&rdev->propagate_radar_detect_wk); flush_work(&rdev->propagate_cac_done_wk); flush_work(&rdev->mgmt_registrations_update_wk); flush_work(&rdev->background_cac_abort_wk); -#ifdef CONFIG_PM - if (rdev->wiphy.wowlan_config && rdev->ops->set_wakeup) - rdev_set_wakeup(rdev, false); -#endif cfg80211_rdev_free_wowlan(rdev); cfg80211_rdev_free_coalesce(rdev); } @@ -1130,23 +1192,16 @@ } EXPORT_SYMBOL(wiphy_rfkill_set_hw_state_reason); -void cfg80211_cqm_config_free(struct wireless_dev *wdev) -{ - kfree(wdev->cqm_config); - wdev->cqm_config = NULL; -} - static void _cfg80211_unregister_wdev(struct wireless_dev *wdev, bool unregister_netdev) { struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); + struct cfg80211_cqm_config *cqm_config; unsigned int link_id; ASSERT_RTNL(); lockdep_assert_held(&rdev->wiphy.mtx); - flush_work(&wdev->pmsr_free_wk); - nl80211_notify_iface(rdev, wdev, NL80211_CMD_DEL_INTERFACE); wdev->registered = false; @@ -1178,11 +1233,10 @@ kfree_sensitive(wdev->wext.keys); wdev->wext.keys = NULL; #endif - /* only initialized if we have a netdev */ - if (wdev->netdev) - flush_work(&wdev->disconnect_wk); - - cfg80211_cqm_config_free(wdev); + wiphy_work_cancel(wdev->wiphy, &wdev->cqm_rssi_work); + /* deleted from the list, so can't be found from nl80211 any more */ + cqm_config = rcu_access_pointer(wdev->cqm_config); + kfree_rcu(cqm_config, rcu_head); /* * Ensure that all events have been processed and @@ -1228,14 +1282,13 @@ rdev->num_running_monitor_ifaces += num; } -void __cfg80211_leave(struct cfg80211_registered_device *rdev, +void cfg80211_leave(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev) { struct net_device *dev = wdev->netdev; struct cfg80211_sched_scan_request *pos, *tmp; lockdep_assert_held(&rdev->wiphy.mtx); - ASSERT_WDEV_LOCK(wdev); cfg80211_pmsr_wdev_down(wdev); @@ -1243,7 +1296,7 @@ switch (wdev->iftype) { case NL80211_IFTYPE_ADHOC: - __cfg80211_leave_ibss(rdev, dev, true); + cfg80211_leave_ibss(rdev, dev, true); break; case NL80211_IFTYPE_P2P_CLIENT: case NL80211_IFTYPE_STATION: @@ -1263,14 +1316,14 @@ WLAN_REASON_DEAUTH_LEAVING, true); break; case NL80211_IFTYPE_MESH_POINT: - __cfg80211_leave_mesh(rdev, dev); + cfg80211_leave_mesh(rdev, dev); break; case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: - __cfg80211_stop_ap(rdev, dev, -1, true); + cfg80211_stop_ap(rdev, dev, -1, true); break; case NL80211_IFTYPE_OCB: - __cfg80211_leave_ocb(rdev, dev); + cfg80211_leave_ocb(rdev, dev); break; case NL80211_IFTYPE_P2P_DEVICE: case NL80211_IFTYPE_NAN: @@ -1288,14 +1341,6 @@ } } -void cfg80211_leave(struct cfg80211_registered_device *rdev, - struct wireless_dev *wdev) -{ - wdev_lock(wdev); - __cfg80211_leave(rdev, wdev); - wdev_unlock(wdev); -} - void cfg80211_stop_iface(struct wiphy *wiphy, struct wireless_dev *wdev, gfp_t gfp) { @@ -1320,7 +1365,6 @@ void cfg80211_init_wdev(struct wireless_dev *wdev) { - mutex_init(&wdev->mtx); INIT_LIST_HEAD(&wdev->event_list); spin_lock_init(&wdev->event_lock); INIT_LIST_HEAD(&wdev->mgmt_registrations); @@ -1334,6 +1378,8 @@ wdev->wext.connect.auth_type = NL80211_AUTHTYPE_AUTOMATIC; #endif + wiphy_work_init(&wdev->cqm_rssi_work, cfg80211_cqm_rssi_notify_work); + if (wdev->wiphy->flags & WIPHY_FLAG_PS_ON_BY_DEFAULT) wdev->ps = true; else @@ -1392,6 +1438,7 @@ lockdep_assert_held(&rdev->wiphy.mtx); /* we'll take care of this */ + dev->dev_port = rdev->wiphy.dev_port + 1; wdev->registered = true; wdev->registering = true; ret = register_netdevice(dev); @@ -1455,6 +1502,9 @@ cfg80211_leave(rdev, wdev); cfg80211_remove_links(wdev); wiphy_unlock(&rdev->wiphy); + /* since we just did cfg80211_leave() nothing to do there */ + cancel_work_sync(&wdev->disconnect_wk); + cancel_work_sync(&wdev->pmsr_free_wk); break; case NETDEV_DOWN: wiphy_lock(&rdev->wiphy); @@ -1480,7 +1530,6 @@ case NETDEV_UP: wiphy_lock(&rdev->wiphy); cfg80211_update_iface_num(rdev, wdev->iftype, 1); - wdev_lock(wdev); switch (wdev->iftype) { #ifdef CONFIG_CFG80211_WEXT case NL80211_IFTYPE_ADHOC: @@ -1510,7 +1559,6 @@ default: break; } - wdev_unlock(wdev); rdev->opencount++; /* @@ -1553,7 +1601,7 @@ struct cfg80211_registered_device *rdev; rtnl_lock(); - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { if (net_eq(wiphy_net(&rdev->wiphy), net)) WARN_ON(cfg80211_switch_netns(rdev, &init_net)); } @@ -1564,6 +1612,125 @@ .exit = cfg80211_pernet_exit, }; +void wiphy_work_queue(struct wiphy *wiphy, struct wiphy_work *work) +{ + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + unsigned long flags; + + spin_lock_irqsave(&rdev->wiphy_work_lock, flags); + if (list_empty(&work->entry)) + list_add_tail(&work->entry, &rdev->wiphy_work_list); + spin_unlock_irqrestore(&rdev->wiphy_work_lock, flags); + + queue_work(system_unbound_wq, &rdev->wiphy_work); +} +EXPORT_SYMBOL_GPL(wiphy_work_queue); + +void wiphy_work_cancel(struct wiphy *wiphy, struct wiphy_work *work) +{ + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + unsigned long flags; + + lockdep_assert_held(&wiphy->mtx); + + spin_lock_irqsave(&rdev->wiphy_work_lock, flags); + if (!list_empty(&work->entry)) + list_del_init(&work->entry); + spin_unlock_irqrestore(&rdev->wiphy_work_lock, flags); +} +EXPORT_SYMBOL_GPL(wiphy_work_cancel); + +void wiphy_work_flush(struct wiphy *wiphy, struct wiphy_work *work) +{ + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + unsigned long flags; + bool run; + + spin_lock_irqsave(&rdev->wiphy_work_lock, flags); + run = !work || !list_empty(&work->entry); + spin_unlock_irqrestore(&rdev->wiphy_work_lock, flags); + + if (run) + cfg80211_process_wiphy_works(rdev, work); +} +EXPORT_SYMBOL_GPL(wiphy_work_flush); + +void wiphy_delayed_work_timer(struct timer_list *t) +{ + struct wiphy_delayed_work *dwork = from_timer(dwork, t, timer); + + wiphy_work_queue(dwork->wiphy, &dwork->work); +} +EXPORT_SYMBOL(wiphy_delayed_work_timer); + +void wiphy_delayed_work_queue(struct wiphy *wiphy, + struct wiphy_delayed_work *dwork, + unsigned long delay) +{ + if (!delay) { + wiphy_work_queue(wiphy, &dwork->work); + return; + } + + dwork->wiphy = wiphy; + mod_timer(&dwork->timer, jiffies + delay); +} +EXPORT_SYMBOL_GPL(wiphy_delayed_work_queue); + +void wiphy_delayed_work_cancel(struct wiphy *wiphy, + struct wiphy_delayed_work *dwork) +{ + lockdep_assert_held(&wiphy->mtx); + + del_timer_sync(&dwork->timer); + wiphy_work_cancel(wiphy, &dwork->work); +} +EXPORT_SYMBOL_GPL(wiphy_delayed_work_cancel); + +void wiphy_delayed_work_flush(struct wiphy *wiphy, + struct wiphy_delayed_work *dwork) +{ + lockdep_assert_held(&wiphy->mtx); + + del_timer_sync(&dwork->timer); + wiphy_work_flush(wiphy, &dwork->work); +} +EXPORT_SYMBOL_GPL(wiphy_delayed_work_flush); + +/* + * + */ +static int dfs_cache_flush_set(void *data, u64 val) +{ + cfg80211_flush_dfs_cache(); + printk("DFS cache flushed\n"); + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(fops_dfs_cache_flush, NULL, + dfs_cache_flush_set, "%llu\n"); + +static void __init dfs_cache_init(void) +{ + size_t i; + + mutex_init(&cfg80211_dfs_cache.mtx); + + for (i = 0; i < ARRAY_SIZE(cfg80211_dfs_cache.bands); i++) + INIT_LIST_HEAD(&cfg80211_dfs_cache.bands[i]); + + cfg80211_dfs_cache_debugfs = + debugfs_create_file_unsafe("dfs_cache_flush", 0200, + ieee80211_debugfs_dir, NULL, + &fops_dfs_cache_flush); +} + +static void __exit dfs_cache_exit(void) +{ + cfg80211_flush_dfs_cache(); + debugfs_remove(cfg80211_dfs_cache_debugfs); +} + static int __init cfg80211_init(void) { int err; @@ -1584,8 +1751,14 @@ if (err) goto out_fail_nl80211; + err = nlfbx_init(); + if (err) + goto out_fail_nlfbx; + ieee80211_debugfs_dir = debugfs_create_dir("ieee80211", NULL); + dfs_cache_init(); + err = regulatory_init(); if (err) goto out_fail_reg; @@ -1601,6 +1774,8 @@ out_fail_wq: regulatory_exit(); out_fail_reg: + nlfbx_exit(); +out_fail_nlfbx: debugfs_remove(ieee80211_debugfs_dir); nl80211_exit(); out_fail_nl80211: @@ -1616,6 +1791,7 @@ static void __exit cfg80211_exit(void) { + dfs_cache_exit(); debugfs_remove(ieee80211_debugfs_dir); nl80211_exit(); unregister_netdevice_notifier(&cfg80211_netdev_notifier); diff -ruw linux-6.4/net/wireless/core.h linux-6.4-fbx/net/wireless/core.h --- linux-6.4/net/wireless/core.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/core.h 2024-02-14 17:43:53.027128018 +0100 @@ -75,7 +75,7 @@ struct sk_buff *scan_msg; struct list_head sched_scan_req_list; time64_t suspend_at; - struct work_struct scan_done_wk; + struct wiphy_work scan_done_wk; struct genl_info *cur_cmd_info; @@ -95,7 +95,7 @@ struct cfg80211_coalesce *coalesce; struct work_struct destroy_work; - struct work_struct sched_scan_stop_wk; + struct wiphy_work sched_scan_stop_wk; struct work_struct sched_scan_res_wk; struct cfg80211_chan_def radar_chandef; @@ -108,6 +108,12 @@ /* lock for all wdev lists */ spinlock_t mgmt_registrations_lock; + struct work_struct wiphy_work; + struct list_head wiphy_work_list; + /* protects the list above */ + spinlock_t wiphy_work_lock; + bool suspended; + /* must be last because of the way we do wiphy_priv(), * and it should at least be aligned to NETDEV_ALIGN */ struct wiphy wiphy __aligned(NETDEV_ALIGN); @@ -154,6 +160,40 @@ extern struct list_head cfg80211_rdev_list; extern int cfg80211_rdev_list_generation; + +/* + * DFS cache + */ +struct cfg80211_chan_dfs_cache { + u32 center_freq; + u16 freq_offset; + + enum nl80211_dfs_state dfs_state; + unsigned long dfs_state_entered; + struct list_head next; +}; + +struct cfg80211_dfs_cache { + struct list_head bands[NUM_NL80211_BANDS]; + struct mutex mtx; +}; + +extern struct cfg80211_dfs_cache cfg80211_dfs_cache; + +struct cfg80211_chan_dfs_cache * +cfg80211_get_dfs_chan_cache(struct ieee80211_channel *c); +void cfg80211_flush_dfs_cache(void); + +/* This is constructed like this so it can be used in if/else */ +static inline int for_each_rdev_check_rtnl(void) +{ + ASSERT_RTNL(); + return 0; +} +#define for_each_rdev(rdev) \ + if (for_each_rdev_check_rtnl()) {} else \ + list_for_each_entry(rdev, &cfg80211_rdev_list, list) + struct cfg80211_internal_bss { struct list_head list; struct list_head hidden_list; @@ -219,22 +259,6 @@ void cfg80211_register_wdev(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev); -static inline void wdev_lock(struct wireless_dev *wdev) - __acquires(wdev) -{ - mutex_lock(&wdev->mtx); - __acquire(wdev->mtx); -} - -static inline void wdev_unlock(struct wireless_dev *wdev) - __releases(wdev) -{ - __release(wdev->mtx); - mutex_unlock(&wdev->mtx); -} - -#define ASSERT_WDEV_LOCK(wdev) lockdep_assert_held(&(wdev)->mtx) - static inline bool cfg80211_has_monitors_only(struct cfg80211_registered_device *rdev) { lockdep_assert_held(&rdev->wiphy.mtx); @@ -270,7 +294,7 @@ struct ieee80211_channel *channel; } ij; struct { - u8 bssid[ETH_ALEN]; + u8 peer_addr[ETH_ALEN]; const u8 *td_bitmap; u8 td_bitmap_len; } pa; @@ -289,12 +313,17 @@ }; struct cfg80211_cqm_config { + struct rcu_head rcu_head; u32 rssi_hyst; s32 last_rssi_event_value; + enum nl80211_cqm_rssi_threshold_event last_rssi_event_type; int n_rssi_thresholds; - s32 rssi_thresholds[]; + s32 rssi_thresholds[] __counted_by(n_rssi_thresholds); }; +void cfg80211_cqm_rssi_notify_work(struct wiphy *wiphy, + struct wiphy_work *work); + void cfg80211_destroy_ifaces(struct cfg80211_registered_device *rdev); /* free object */ @@ -318,8 +347,6 @@ struct cfg80211_ibss_params *params, struct cfg80211_cached_keys *connkeys); void cfg80211_clear_ibss(struct net_device *dev, bool nowext); -int __cfg80211_leave_ibss(struct cfg80211_registered_device *rdev, - struct net_device *dev, bool nowext); int cfg80211_leave_ibss(struct cfg80211_registered_device *rdev, struct net_device *dev, bool nowext); void __cfg80211_ibss_joined(struct net_device *dev, const u8 *bssid, @@ -334,8 +361,6 @@ struct net_device *dev, struct mesh_setup *setup, const struct mesh_config *conf); -int __cfg80211_leave_mesh(struct cfg80211_registered_device *rdev, - struct net_device *dev); int cfg80211_leave_mesh(struct cfg80211_registered_device *rdev, struct net_device *dev); int cfg80211_set_mesh_channel(struct cfg80211_registered_device *rdev, @@ -343,21 +368,13 @@ struct cfg80211_chan_def *chandef); /* OCB */ -int __cfg80211_join_ocb(struct cfg80211_registered_device *rdev, - struct net_device *dev, - struct ocb_setup *setup); int cfg80211_join_ocb(struct cfg80211_registered_device *rdev, struct net_device *dev, struct ocb_setup *setup); -int __cfg80211_leave_ocb(struct cfg80211_registered_device *rdev, - struct net_device *dev); int cfg80211_leave_ocb(struct cfg80211_registered_device *rdev, struct net_device *dev); /* AP */ -int __cfg80211_stop_ap(struct cfg80211_registered_device *rdev, - struct net_device *dev, int link, - bool notify); int cfg80211_stop_ap(struct cfg80211_registered_device *rdev, struct net_device *dev, int link, bool notify); @@ -411,7 +428,7 @@ bool wextev); void __cfg80211_roamed(struct wireless_dev *wdev, struct cfg80211_roam_info *info); -void __cfg80211_port_authorized(struct wireless_dev *wdev, const u8 *bssid, +void __cfg80211_port_authorized(struct wireless_dev *wdev, const u8 *peer_addr, const u8 *td_bitmap, u8 td_bitmap_len); int cfg80211_mgd_wext_connect(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev); @@ -435,7 +452,7 @@ int cfg80211_validate_key_settings(struct cfg80211_registered_device *rdev, struct key_params *params, int key_idx, bool pairwise, const u8 *mac_addr); -void __cfg80211_scan_done(struct work_struct *wk); +void __cfg80211_scan_done(struct wiphy *wiphy, struct wiphy_work *wk); void ___cfg80211_scan_done(struct cfg80211_registered_device *rdev, bool send_message); void cfg80211_add_sched_scan_req(struct cfg80211_registered_device *rdev, @@ -453,6 +470,8 @@ struct net_device *dev, enum nl80211_iftype ntype, struct vif_params *params); void cfg80211_process_rdev_events(struct cfg80211_registered_device *rdev); +void cfg80211_process_wiphy_works(struct cfg80211_registered_device *rdev, + struct wiphy_work *end); void cfg80211_process_wdev_events(struct wireless_dev *wdev); bool cfg80211_does_bw_fit_range(const struct ieee80211_freq_range *freq_range, @@ -462,29 +481,12 @@ extern struct work_struct cfg80211_disconnect_work; -/** - * cfg80211_chandef_dfs_usable - checks if chandef is DFS usable - * @wiphy: the wiphy to validate against - * @chandef: the channel definition to check - * - * Checks if chandef is usable and we can/need start CAC on such channel. - * - * Return: true if all channels available and at least - * one channel requires CAC (NL80211_DFS_USABLE) - */ -bool cfg80211_chandef_dfs_usable(struct wiphy *wiphy, - const struct cfg80211_chan_def *chandef); - void cfg80211_set_dfs_state(struct wiphy *wiphy, const struct cfg80211_chan_def *chandef, enum nl80211_dfs_state dfs_state); void cfg80211_dfs_channels_update_work(struct work_struct *work); -unsigned int -cfg80211_chandef_dfs_cac_time(struct wiphy *wiphy, - const struct cfg80211_chan_def *chandef); - void cfg80211_sched_dfs_chan_update(struct cfg80211_registered_device *rdev); int @@ -533,8 +535,6 @@ void cfg80211_update_iface_num(struct cfg80211_registered_device *rdev, enum nl80211_iftype iftype, int num); -void __cfg80211_leave(struct cfg80211_registered_device *rdev, - struct wireless_dev *wdev); void cfg80211_leave(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev); @@ -559,8 +559,6 @@ #define CFG80211_DEV_WARN_ON(cond) ({bool __r = (cond); __r; }) #endif -void cfg80211_cqm_config_free(struct wireless_dev *wdev); - void cfg80211_release_pmsr(struct wireless_dev *wdev, u32 portid); void cfg80211_pmsr_wdev_down(struct wireless_dev *wdev); void cfg80211_pmsr_free_wk(struct work_struct *work); @@ -569,5 +567,6 @@ void cfg80211_remove_links(struct wireless_dev *wdev); int cfg80211_remove_virtual_intf(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev); +void cfg80211_wdev_release_link_bsses(struct wireless_dev *wdev, u16 link_mask); #endif /* __NET_WIRELESS_CORE_H */ diff -ruw linux-6.4/net/wireless/ibss.c linux-6.4-fbx/net/wireless/ibss.c --- linux-6.4/net/wireless/ibss.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/ibss.c 2023-11-07 13:38:44.102257784 +0100 @@ -3,7 +3,7 @@ * Some IBSS support code for cfg80211. * * Copyright 2009 Johannes Berg - * Copyright (C) 2020-2022 Intel Corporation + * Copyright (C) 2020-2023 Intel Corporation */ #include @@ -93,7 +93,6 @@ int err; lockdep_assert_held(&rdev->wiphy.mtx); - ASSERT_WDEV_LOCK(wdev); if (wdev->u.ibss.ssid_len) return -EALREADY; @@ -151,13 +150,13 @@ return 0; } -static void __cfg80211_clear_ibss(struct net_device *dev, bool nowext) +void cfg80211_clear_ibss(struct net_device *dev, bool nowext) { struct wireless_dev *wdev = dev->ieee80211_ptr; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); int i; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); kfree_sensitive(wdev->connect_keys); wdev->connect_keys = NULL; @@ -187,22 +186,13 @@ cfg80211_sched_dfs_chan_update(rdev); } -void cfg80211_clear_ibss(struct net_device *dev, bool nowext) -{ - struct wireless_dev *wdev = dev->ieee80211_ptr; - - wdev_lock(wdev); - __cfg80211_clear_ibss(dev, nowext); - wdev_unlock(wdev); -} - -int __cfg80211_leave_ibss(struct cfg80211_registered_device *rdev, +int cfg80211_leave_ibss(struct cfg80211_registered_device *rdev, struct net_device *dev, bool nowext) { struct wireless_dev *wdev = dev->ieee80211_ptr; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!wdev->u.ibss.ssid_len) return -ENOLINK; @@ -213,24 +203,11 @@ return err; wdev->conn_owner_nlportid = 0; - __cfg80211_clear_ibss(dev, nowext); + cfg80211_clear_ibss(dev, nowext); return 0; } -int cfg80211_leave_ibss(struct cfg80211_registered_device *rdev, - struct net_device *dev, bool nowext) -{ - struct wireless_dev *wdev = dev->ieee80211_ptr; - int err; - - wdev_lock(wdev); - err = __cfg80211_leave_ibss(rdev, dev, nowext); - wdev_unlock(wdev); - - return err; -} - #ifdef CONFIG_CFG80211_WEXT int cfg80211_ibss_wext_join(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev) @@ -239,7 +216,7 @@ enum nl80211_band band; int i, err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!wdev->wext.ibss.beacon_interval) wdev->wext.ibss.beacon_interval = 100; @@ -336,11 +313,9 @@ if (wdev->wext.ibss.chandef.chan == chan) return 0; - wdev_lock(wdev); err = 0; if (wdev->u.ibss.ssid_len) - err = __cfg80211_leave_ibss(rdev, dev, true); - wdev_unlock(wdev); + err = cfg80211_leave_ibss(rdev, dev, true); if (err) return err; @@ -354,11 +329,7 @@ wdev->wext.ibss.channel_fixed = false; } - wdev_lock(wdev); - err = cfg80211_ibss_wext_join(rdev, wdev); - wdev_unlock(wdev); - - return err; + return cfg80211_ibss_wext_join(rdev, wdev); } int cfg80211_ibss_wext_giwfreq(struct net_device *dev, @@ -372,12 +343,10 @@ if (WARN_ON(wdev->iftype != NL80211_IFTYPE_ADHOC)) return -EINVAL; - wdev_lock(wdev); if (wdev->u.ibss.current_bss) chan = wdev->u.ibss.current_bss->pub.channel; else if (wdev->wext.ibss.chandef.chan) chan = wdev->wext.ibss.chandef.chan; - wdev_unlock(wdev); if (chan) { freq->m = chan->center_freq; @@ -405,11 +374,9 @@ if (!rdev->ops->join_ibss) return -EOPNOTSUPP; - wdev_lock(wdev); err = 0; if (wdev->u.ibss.ssid_len) - err = __cfg80211_leave_ibss(rdev, dev, true); - wdev_unlock(wdev); + err = cfg80211_leave_ibss(rdev, dev, true); if (err) return err; @@ -422,11 +389,7 @@ wdev->wext.ibss.ssid = wdev->u.ibss.ssid; wdev->wext.ibss.ssid_len = len; - wdev_lock(wdev); - err = cfg80211_ibss_wext_join(rdev, wdev); - wdev_unlock(wdev); - - return err; + return cfg80211_ibss_wext_join(rdev, wdev); } int cfg80211_ibss_wext_giwessid(struct net_device *dev, @@ -441,7 +404,6 @@ data->flags = 0; - wdev_lock(wdev); if (wdev->u.ibss.ssid_len) { data->flags = 1; data->length = wdev->u.ibss.ssid_len; @@ -451,7 +413,6 @@ data->length = wdev->wext.ibss.ssid_len; memcpy(ssid, wdev->wext.ibss.ssid, data->length); } - wdev_unlock(wdev); return 0; } @@ -491,11 +452,9 @@ ether_addr_equal(bssid, wdev->wext.ibss.bssid)) return 0; - wdev_lock(wdev); err = 0; if (wdev->u.ibss.ssid_len) - err = __cfg80211_leave_ibss(rdev, dev, true); - wdev_unlock(wdev); + err = cfg80211_leave_ibss(rdev, dev, true); if (err) return err; @@ -506,11 +465,7 @@ } else wdev->wext.ibss.bssid = NULL; - wdev_lock(wdev); - err = cfg80211_ibss_wext_join(rdev, wdev); - wdev_unlock(wdev); - - return err; + return cfg80211_ibss_wext_join(rdev, wdev); } int cfg80211_ibss_wext_giwap(struct net_device *dev, @@ -525,7 +480,6 @@ ap_addr->sa_family = ARPHRD_ETHER; - wdev_lock(wdev); if (wdev->u.ibss.current_bss) memcpy(ap_addr->sa_data, wdev->u.ibss.current_bss->pub.bssid, ETH_ALEN); @@ -534,8 +488,6 @@ else eth_zero_addr(ap_addr->sa_data); - wdev_unlock(wdev); - return 0; } #endif diff -ruw linux-6.4/net/wireless/mesh.c linux-6.4-fbx/net/wireless/mesh.c --- linux-6.4/net/wireless/mesh.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/mesh.c 2023-11-07 13:38:44.102257784 +0100 @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Portions - * Copyright (C) 2022 Intel Corporation + * Copyright (C) 2022-2023 Intel Corporation */ #include #include @@ -109,7 +109,7 @@ BUILD_BUG_ON(IEEE80211_MAX_SSID_LEN != IEEE80211_MAX_MESH_ID_LEN); - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_MESH_POINT) return -EOPNOTSUPP; @@ -172,7 +172,6 @@ * basic rates */ if (!setup->basic_rates) { - enum nl80211_bss_scan_width scan_width; struct ieee80211_supported_band *sband = rdev->wiphy.bands[setup->chandef.chan->band]; @@ -193,9 +192,7 @@ } } } else { - scan_width = cfg80211_chandef_to_scan_width(&setup->chandef); - setup->basic_rates = ieee80211_mandatory_rates(sband, - scan_width); + setup->basic_rates = ieee80211_mandatory_rates(sband); } } @@ -257,13 +254,13 @@ return 0; } -int __cfg80211_leave_mesh(struct cfg80211_registered_device *rdev, +int cfg80211_leave_mesh(struct cfg80211_registered_device *rdev, struct net_device *dev) { struct wireless_dev *wdev = dev->ieee80211_ptr; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_MESH_POINT) return -EOPNOTSUPP; @@ -287,16 +284,3 @@ return err; } - -int cfg80211_leave_mesh(struct cfg80211_registered_device *rdev, - struct net_device *dev) -{ - struct wireless_dev *wdev = dev->ieee80211_ptr; - int err; - - wdev_lock(wdev); - err = __cfg80211_leave_mesh(rdev, dev); - wdev_unlock(wdev); - - return err; -} diff -ruw linux-6.4/net/wireless/mlme.c linux-6.4-fbx/net/wireless/mlme.c --- linux-6.4/net/wireless/mlme.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/mlme.c 2023-11-07 13:38:44.102257784 +0100 @@ -4,7 +4,7 @@ * * Copyright (c) 2009, Jouni Malinen * Copyright (c) 2015 Intel Deutschland GmbH - * Copyright (C) 2019-2020, 2022 Intel Corporation + * Copyright (C) 2019-2020, 2022-2023 Intel Corporation */ #include @@ -22,7 +22,7 @@ void cfg80211_rx_assoc_resp(struct net_device *dev, - struct cfg80211_rx_assoc_resp *data) + struct cfg80211_rx_assoc_resp_data *data) { struct wireless_dev *wdev = dev->ieee80211_ptr; struct wiphy *wiphy = wdev->wiphy; @@ -43,16 +43,18 @@ for (link_id = 0; link_id < ARRAY_SIZE(data->links); link_id++) { cr.links[link_id].status = data->links[link_id].status; + cr.links[link_id].bss = data->links[link_id].bss; + WARN_ON_ONCE(cr.links[link_id].status != WLAN_STATUS_SUCCESS && (!cr.ap_mld_addr || !cr.links[link_id].bss)); - cr.links[link_id].bss = data->links[link_id].bss; if (!cr.links[link_id].bss) continue; cr.links[link_id].bssid = data->links[link_id].bss->bssid; cr.links[link_id].addr = data->links[link_id].addr; /* need to have local link addresses for MLO connections */ - WARN_ON(cr.ap_mld_addr && !cr.links[link_id].addr); + WARN_ON(cr.ap_mld_addr && + !is_valid_ether_addr(cr.links[link_id].addr)); BUG_ON(!cr.links[link_id].bss->channel); @@ -149,7 +151,7 @@ struct wireless_dev *wdev = dev->ieee80211_ptr; struct ieee80211_mgmt *mgmt = (void *)buf; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); trace_cfg80211_rx_mlme_mgmt(dev, buf, len); @@ -214,7 +216,7 @@ struct wireless_dev *wdev = dev->ieee80211_ptr; struct ieee80211_mgmt *mgmt = (void *)buf; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); trace_cfg80211_tx_mlme_mgmt(dev, buf, len, reconnect); @@ -262,7 +264,7 @@ { struct wireless_dev *wdev = dev->ieee80211_ptr; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!req->bss) return -ENOENT; @@ -281,6 +283,11 @@ ether_addr_equal(req->bss->bssid, wdev->u.client.connected_addr)) return -EALREADY; + if (ether_addr_equal(req->bss->bssid, dev->dev_addr) || + (req->link_id >= 0 && + ether_addr_equal(req->ap_mld_addr, dev->dev_addr))) + return -EINVAL; + return rdev_auth(rdev, dev, req); } @@ -326,7 +333,7 @@ struct wireless_dev *wdev = dev->ieee80211_ptr; int err, i, j; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); for (i = 1; i < ARRAY_SIZE(req->links); i++) { if (!req->links[i].bss) @@ -335,6 +342,9 @@ if (req->links[i].bss == req->links[j].bss) return -EINVAL; } + + if (ether_addr_equal(req->links[i].bss->bssid, dev->dev_addr)) + return -EINVAL; } if (wdev->connected && @@ -342,6 +352,11 @@ !ether_addr_equal(wdev->u.client.connected_addr, req->prev_bssid))) return -EALREADY; + if ((req->bss && ether_addr_equal(req->bss->bssid, dev->dev_addr)) || + (req->link_id >= 0 && + ether_addr_equal(req->ap_mld_addr, dev->dev_addr))) + return -EINVAL; + cfg80211_oper_and_ht_capa(&req->ht_capa_mask, rdev->wiphy.ht_capa_mod_mask); cfg80211_oper_and_vht_capa(&req->vht_capa_mask, @@ -380,7 +395,7 @@ .local_state_change = local_state_change, }; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (local_state_change && (!wdev->connected || @@ -410,7 +425,7 @@ }; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!wdev->connected) return -ENOTCONN; @@ -433,7 +448,7 @@ struct wireless_dev *wdev = dev->ieee80211_ptr; u8 bssid[ETH_ALEN]; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!rdev->ops->deauth) return; @@ -713,6 +728,8 @@ const struct ieee80211_mgmt *mgmt; u16 stype; + lockdep_assert_wiphy(&rdev->wiphy); + if (!wdev->wiphy->mgmt_stypes) return -EOPNOTSUPP; @@ -735,8 +752,6 @@ mgmt->u.action.category != WLAN_CATEGORY_PUBLIC) { int err = 0; - wdev_lock(wdev); - switch (wdev->iftype) { case NL80211_IFTYPE_ADHOC: /* @@ -801,7 +816,6 @@ err = -EOPNOTSUPP; break; } - wdev_unlock(wdev); if (err) return err; diff -ruw linux-6.4/net/wireless/nl80211.c linux-6.4-fbx/net/wireless/nl80211.c --- linux-6.4/net/wireless/nl80211.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/nl80211.c 2024-01-19 17:01:19.917848451 +0100 @@ -5,7 +5,7 @@ * Copyright 2006-2010 Johannes Berg * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright 2015-2017 Intel Deutschland GmbH - * Copyright (C) 2018-2022 Intel Corporation + * Copyright (C) 2018-2023 Intel Corporation */ #include @@ -106,7 +106,7 @@ ASSERT_RTNL(); - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { struct wireless_dev *wdev; if (wiphy_net(&rdev->wiphy) != netns) @@ -323,6 +323,7 @@ [NL80211_PMSR_FTM_REQ_ATTR_TRIGGER_BASED] = { .type = NLA_FLAG }, [NL80211_PMSR_FTM_REQ_ATTR_NON_TRIGGER_BASED] = { .type = NLA_FLAG }, [NL80211_PMSR_FTM_REQ_ATTR_LMR_FEEDBACK] = { .type = NLA_FLAG }, + [NL80211_PMSR_FTM_REQ_ATTR_BSS_COLOR] = { .type = NLA_U8 }, }; static const struct nla_policy @@ -816,6 +817,7 @@ [NL80211_ATTR_MAX_HW_TIMESTAMP_PEERS] = { .type = NLA_U16 }, [NL80211_ATTR_HW_TIMESTAMP_ENABLED] = { .type = NLA_FLAG }, [NL80211_ATTR_EMA_RNR_ELEMS] = { .type = NLA_NESTED }, + [NL80211_ATTR_MLO_LINK_DISABLED] = { .type = NLA_FLAG }, }; /* policy for the key attributes */ @@ -1113,6 +1115,10 @@ if (nla_put_u32(msg, NL80211_FREQUENCY_ATTR_OFFSET, chan->freq_offset)) goto nla_put_failure; + if ((chan->flags & IEEE80211_CHAN_PSD) && + nla_put_s8(msg, NL80211_FREQUENCY_ATTR_PSD, chan->psd)) + goto nla_put_failure; + if ((chan->flags & IEEE80211_CHAN_DISABLED) && nla_put_flag(msg, NL80211_FREQUENCY_ATTR_DISABLED)) goto nla_put_failure; @@ -1542,7 +1548,7 @@ static int nl80211_key_allowed(struct wireless_dev *wdev) { - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); switch (wdev->iftype) { case NL80211_IFTYPE_AP: @@ -3073,7 +3079,7 @@ cb->args[0] = (long)state; } - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { if (!net_eq(wiphy_net(&rdev->wiphy), sock_net(skb->sk))) continue; if (++idx <= state->start) @@ -3081,6 +3087,7 @@ if (state->filter_wiphy != -1 && state->filter_wiphy != rdev->wiphy_idx) continue; + wiphy_lock(&rdev->wiphy); /* attempt to fit multiple wiphy data chunks into the skb */ do { ret = nl80211_send_wiphy(rdev, NL80211_CMD_NEW_WIPHY, @@ -3107,6 +3114,7 @@ cb->min_dump_alloc < 4096) { cb->min_dump_alloc = 4096; state->split_start = 0; + wiphy_unlock(&rdev->wiphy); rtnl_unlock(); return 1; } @@ -3114,6 +3122,7 @@ break; } } while (state->split_start > 0); + wiphy_unlock(&rdev->wiphy); break; } rtnl_unlock(); @@ -3418,13 +3427,8 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; int link_id = nl80211_link_id_or_invalid(info->attrs); struct net_device *netdev = info->user_ptr[1]; - int ret; - - wdev_lock(netdev->ieee80211_ptr); - ret = __nl80211_set_channel(rdev, netdev, info, link_id); - wdev_unlock(netdev->ieee80211_ptr); - return ret; + return __nl80211_set_channel(rdev, netdev, info, link_id); } static int nl80211_set_wiphy(struct sk_buff *skb, struct genl_info *info) @@ -3504,6 +3508,7 @@ } if (netdev->ieee80211_ptr->iftype != NL80211_IFTYPE_AP && + netdev->ieee80211_ptr->iftype != NL80211_IFTYPE_MONITOR && netdev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO) { result = -EINVAL; goto out; @@ -3531,7 +3536,6 @@ txq_params.link_id = nl80211_link_id_or_invalid(info->attrs); - wdev_lock(netdev->ieee80211_ptr); if (txq_params.link_id >= 0 && !(netdev->ieee80211_ptr->valid_links & BIT(txq_params.link_id))) @@ -3542,7 +3546,6 @@ else result = rdev_set_txq_params(rdev, netdev, &txq_params); - wdev_unlock(netdev->ieee80211_ptr); if (result) goto out; } @@ -3552,12 +3555,10 @@ int link_id = nl80211_link_id_or_invalid(info->attrs); if (wdev) { - wdev_lock(wdev); result = __nl80211_set_channel( rdev, nl80211_can_set_dev_channel(wdev) ? netdev : NULL, info, link_id); - wdev_unlock(wdev); } else { result = __nl80211_set_channel(rdev, netdev, info, link_id); } @@ -3865,33 +3866,31 @@ goto nla_put_failure; } - wdev_lock(wdev); switch (wdev->iftype) { case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: if (wdev->u.ap.ssid_len && nla_put(msg, NL80211_ATTR_SSID, wdev->u.ap.ssid_len, wdev->u.ap.ssid)) - goto nla_put_failure_locked; + goto nla_put_failure; break; case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: if (wdev->u.client.ssid_len && nla_put(msg, NL80211_ATTR_SSID, wdev->u.client.ssid_len, wdev->u.client.ssid)) - goto nla_put_failure_locked; + goto nla_put_failure; break; case NL80211_IFTYPE_ADHOC: if (wdev->u.ibss.ssid_len && nla_put(msg, NL80211_ATTR_SSID, wdev->u.ibss.ssid_len, wdev->u.ibss.ssid)) - goto nla_put_failure_locked; + goto nla_put_failure; break; default: /* nothing */ break; } - wdev_unlock(wdev); if (rdev->ops->get_txq_stats) { struct cfg80211_txq_stats txqstats = {}; @@ -3938,8 +3937,6 @@ genlmsg_end(msg, hdr); return 0; - nla_put_failure_locked: - wdev_unlock(wdev); nla_put_failure: genlmsg_cancel(msg, hdr); return -EMSGSIZE; @@ -3980,7 +3977,7 @@ filter_wiphy = cb->args[2] - 1; } - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { if (!net_eq(wiphy_net(&rdev->wiphy), sock_net(skb->sk))) continue; if (wp_idx < wp_start) { @@ -4186,7 +4183,6 @@ if (netif_running(dev)) return -EBUSY; - wdev_lock(wdev); BUILD_BUG_ON(IEEE80211_MAX_SSID_LEN != IEEE80211_MAX_MESH_ID_LEN); wdev->u.mesh.id_up_len = @@ -4194,7 +4190,6 @@ memcpy(wdev->u.mesh.id, nla_data(info->attrs[NL80211_ATTR_MESH_ID]), wdev->u.mesh.id_up_len); - wdev_unlock(wdev); } if (info->attrs[NL80211_ATTR_4ADDR]) { @@ -4295,7 +4290,6 @@ case NL80211_IFTYPE_MESH_POINT: if (!info->attrs[NL80211_ATTR_MESH_ID]) break; - wdev_lock(wdev); BUILD_BUG_ON(IEEE80211_MAX_SSID_LEN != IEEE80211_MAX_MESH_ID_LEN); wdev->u.mesh.id_up_len = @@ -4303,7 +4297,6 @@ memcpy(wdev->u.mesh.id, nla_data(info->attrs[NL80211_ATTR_MESH_ID]), wdev->u.mesh.id_up_len); - wdev_unlock(wdev); break; case NL80211_IFTYPE_NAN: case NL80211_IFTYPE_P2P_DEVICE: @@ -4594,79 +4587,67 @@ !(key.p.mode == NL80211_KEY_SET_TX)) return -EINVAL; - wdev_lock(wdev); - if (key.def) { - if (!rdev->ops->set_default_key) { - err = -EOPNOTSUPP; - goto out; - } + if (!rdev->ops->set_default_key) + return -EOPNOTSUPP; err = nl80211_key_allowed(wdev); if (err) - goto out; + return err; err = nl80211_validate_key_link_id(info, wdev, link_id, false); if (err) - goto out; + return err; err = rdev_set_default_key(rdev, dev, link_id, key.idx, key.def_uni, key.def_multi); if (err) - goto out; + return err; #ifdef CONFIG_CFG80211_WEXT wdev->wext.default_key = key.idx; #endif + return 0; } else if (key.defmgmt) { - if (key.def_uni || !key.def_multi) { - err = -EINVAL; - goto out; - } + if (key.def_uni || !key.def_multi) + return -EINVAL; - if (!rdev->ops->set_default_mgmt_key) { - err = -EOPNOTSUPP; - goto out; - } + if (!rdev->ops->set_default_mgmt_key) + return -EOPNOTSUPP; err = nl80211_key_allowed(wdev); if (err) - goto out; + return err; err = nl80211_validate_key_link_id(info, wdev, link_id, false); if (err) - goto out; + return err; err = rdev_set_default_mgmt_key(rdev, dev, link_id, key.idx); if (err) - goto out; + return err; #ifdef CONFIG_CFG80211_WEXT wdev->wext.default_mgmt_key = key.idx; #endif + return 0; } else if (key.defbeacon) { - if (key.def_uni || !key.def_multi) { - err = -EINVAL; - goto out; - } + if (key.def_uni || !key.def_multi) + return -EINVAL; - if (!rdev->ops->set_default_beacon_key) { - err = -EOPNOTSUPP; - goto out; - } + if (!rdev->ops->set_default_beacon_key) + return -EOPNOTSUPP; err = nl80211_key_allowed(wdev); if (err) - goto out; + return err; err = nl80211_validate_key_link_id(info, wdev, link_id, false); if (err) - goto out; + return err; - err = rdev_set_default_beacon_key(rdev, dev, link_id, key.idx); - if (err) - goto out; + return rdev_set_default_beacon_key(rdev, dev, link_id, key.idx); } else if (key.p.mode == NL80211_KEY_SET_TX && wiphy_ext_feature_isset(&rdev->wiphy, NL80211_EXT_FEATURE_EXT_KEY_ID)) { @@ -4675,25 +4656,19 @@ if (info->attrs[NL80211_ATTR_MAC]) mac_addr = nla_data(info->attrs[NL80211_ATTR_MAC]); - if (!mac_addr || key.idx < 0 || key.idx > 1) { - err = -EINVAL; - goto out; - } + if (!mac_addr || key.idx < 0 || key.idx > 1) + return -EINVAL; err = nl80211_validate_key_link_id(info, wdev, link_id, true); if (err) - goto out; + return err; - err = rdev_add_key(rdev, dev, link_id, key.idx, + return rdev_add_key(rdev, dev, link_id, key.idx, NL80211_KEYTYPE_PAIRWISE, mac_addr, &key.p); - } else { - err = -EINVAL; } - out: - wdev_unlock(wdev); - return err; + return -EINVAL; } static int nl80211_new_key(struct sk_buff *skb, struct genl_info *info) @@ -4746,7 +4721,6 @@ return -EINVAL; } - wdev_lock(wdev); err = nl80211_key_allowed(wdev); if (err) GENL_SET_ERR_MSG(info, "key not allowed"); @@ -4762,7 +4736,6 @@ if (err) GENL_SET_ERR_MSG(info, "key addition failed"); } - wdev_unlock(wdev); return err; } @@ -4803,7 +4776,6 @@ if (!rdev->ops->del_key) return -EOPNOTSUPP; - wdev_lock(wdev); err = nl80211_key_allowed(wdev); if (key.type == NL80211_KEYTYPE_GROUP && mac_addr && @@ -4827,7 +4799,6 @@ wdev->wext.default_mgmt_key = -1; } #endif - wdev_unlock(wdev); return err; } @@ -4885,13 +4856,12 @@ acl = kzalloc(struct_size(acl, mac_addrs, n_entries), GFP_KERNEL); if (!acl) return ERR_PTR(-ENOMEM); + acl->n_acl_entries = n_entries; nla_for_each_nested(attr, info->attrs[NL80211_ATTR_MAC_ADDRS], tmp) { memcpy(acl->mac_addrs[i].addr, nla_data(attr), ETH_ALEN); i++; } - - acl->n_acl_entries = n_entries; acl->acl_policy = acl_policy; return acl; @@ -5129,6 +5099,106 @@ return true; } +static int eht_build_mcs_mask(struct genl_info *info, + const struct ieee80211_sta_he_cap *he_cap, + const struct ieee80211_sta_eht_cap *eht_cap, + u16 *mcs_mask) +{ + struct net_device *dev = info->user_ptr[1]; + struct wireless_dev *wdev = dev->ieee80211_ptr; + u8 mcs_nss_len, nss, mcs_7 = 0, mcs_9 = 0, mcs_11 = 0, mcs_13 = 0; + bool mcs_14 = false, mcs_15 = false; + + mcs_nss_len = ieee80211_eht_mcs_nss_size(&he_cap->he_cap_elem, + &eht_cap->eht_cap_elem, + wdev->iftype == + NL80211_IFTYPE_STATION); + + if (eht_cap->eht_cap_elem.phy_cap_info[6] & + IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP) + mcs_14 = true; + + if (eht_cap->eht_cap_elem.phy_cap_info[6] & + IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK) + mcs_15 = true; + + if (mcs_nss_len == 4) { + const struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs = + &eht_cap->eht_mcs_nss_supp.only_20mhz; + + mcs_7 = mcs->rx_tx_mcs7_max_nss; + mcs_9 = mcs->rx_tx_mcs9_max_nss; + mcs_11 = mcs->rx_tx_mcs11_max_nss; + mcs_13 = mcs->rx_tx_mcs13_max_nss; + } else { + const struct ieee80211_eht_mcs_nss_supp_bw *mcs; + enum nl80211_chan_width width; + + switch (wdev->iftype) { + case NL80211_IFTYPE_AP: + width = wdev->u.ap.preset_chandef.width; + break; + case NL80211_IFTYPE_MESH_POINT: + width = wdev->u.mesh.chandef.width; + break; + default: + return -EINVAL; + } + + switch (width) { + case NL80211_CHAN_WIDTH_320: + mcs = &eht_cap->eht_mcs_nss_supp.bw._320; + break; + case NL80211_CHAN_WIDTH_160: + mcs = &eht_cap->eht_mcs_nss_supp.bw._160; + break; + case NL80211_CHAN_WIDTH_80: + case NL80211_CHAN_WIDTH_40: + case NL80211_CHAN_WIDTH_20: + mcs = &eht_cap->eht_mcs_nss_supp.bw._80; + break; + default: + return -EINVAL; + } + + mcs_7 = mcs->rx_tx_mcs9_max_nss; + mcs_9 = mcs->rx_tx_mcs9_max_nss; + mcs_11 = mcs->rx_tx_mcs11_max_nss; + mcs_13 = mcs->rx_tx_mcs13_max_nss; + } + + for (nss = 0; nss < NL80211_EHT_NSS_MAX; nss++) { + if (nss == 0) { + if (mcs_14) + mcs_mask[nss] |= 0x4000; + if (mcs_15) + mcs_mask[nss] |= 0x8000; + } + + if (!mcs_7) + continue; + mcs_mask[nss] |= 0x00FF; + mcs_7--; + + if (!mcs_9) + continue; + mcs_mask[nss] |= 0x0300; + mcs_9--; + + if (!mcs_11) + continue; + mcs_mask[nss] |= 0x0C00; + mcs_11--; + + if (!mcs_13) + continue; + mcs_mask[nss] |= 0x3000; + mcs_13--; + } + + return 0; +} + static int nl80211_parse_tx_bitrate_mask(struct genl_info *info, struct nlattr *attrs[], enum nl80211_attrs attr, @@ -5149,6 +5219,7 @@ /* Default to all rates enabled */ for (i = 0; i < NUM_NL80211_BANDS; i++) { const struct ieee80211_sta_he_cap *he_cap; + const struct ieee80211_sta_eht_cap *eht_cap; if (!default_all_enabled) break; @@ -5175,6 +5246,13 @@ he_tx_mcs_map = he_get_txmcsmap(info, link_id, he_cap); he_build_mcs_mask(he_tx_mcs_map, mask->control[i].he_mcs); + eht_cap = ieee80211_get_eht_iftype_cap(sband, wdev->iftype); + if (!eht_cap) + continue; + + eht_build_mcs_mask(info, he_cap, eht_cap, + mask->control[i].eht_mcs); + mask->control[i].he_gi = 0xFF; mask->control[i].he_ltf = 0xFF; } @@ -5254,7 +5332,8 @@ */ if (!(rdev->wiphy.bands[band]->ht_cap.ht_supported || rdev->wiphy.bands[band]->vht_cap.vht_supported || - ieee80211_get_he_iftype_cap(sband, wdev->iftype))) + ieee80211_get_he_iftype_cap(sband, wdev->iftype) || + ieee80211_get_eht_iftype_cap(sband, wdev->iftype))) return -EINVAL; for (i = 0; i < IEEE80211_HT_MCS_MASK_LEN; i++) @@ -5269,6 +5348,10 @@ if (mask->control[band].he_mcs[i]) goto out; + for (i = 0; i < NL80211_EHT_NSS_MAX; i++) + if (mask->control[band].eht_mcs[i]) + goto out; + /* legacy and mcs rates may not be both empty */ return -EINVAL; } @@ -5426,19 +5509,22 @@ if (!wiphy->mbssid_max_interfaces) return ERR_PTR(-EINVAL); - nla_for_each_nested(nl_elems, attrs, rem_elems) + nla_for_each_nested(nl_elems, attrs, rem_elems) { + if (num_elems >= 255) + return ERR_PTR(-EINVAL); num_elems++; + } elems = kzalloc(struct_size(elems, elem, num_elems), GFP_KERNEL); if (!elems) return ERR_PTR(-ENOMEM); + elems->cnt = num_elems; nla_for_each_nested(nl_elems, attrs, rem_elems) { elems->elem[i].data = nla_data(nl_elems); elems->elem[i].len = nla_len(nl_elems); i++; } - elems->cnt = num_elems; return elems; } @@ -5464,13 +5550,13 @@ elems = kzalloc(struct_size(elems, elem, num_elems), GFP_KERNEL); if (!elems) return ERR_PTR(-ENOMEM); + elems->cnt = num_elems; nla_for_each_nested(nl_elems, attrs, rem_elems) { elems->elem[i].data = nla_data(nl_elems); elems->elem[i].len = nla_len(nl_elems); i++; } - elems->cnt = num_elems; return elems; } @@ -5494,6 +5580,7 @@ !nla_get_flag(tb[NL80211_HE_BSS_COLOR_ATTR_DISABLED]); he_bss_color->partial = nla_get_flag(tb[NL80211_HE_BSS_COLOR_ATTR_PARTIAL]); + he_bss_color->collision_detection_enabled = true; return 0; } @@ -5664,11 +5751,10 @@ static int nl80211_parse_fils_discovery(struct cfg80211_registered_device *rdev, struct nlattr *attrs, - struct cfg80211_ap_settings *params) + struct cfg80211_fils_discovery *fd) { struct nlattr *tb[NL80211_FILS_DISCOVERY_ATTR_MAX + 1]; int ret; - struct cfg80211_fils_discovery *fd = ¶ms->fils_discovery; if (!wiphy_ext_feature_isset(&rdev->wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY)) @@ -5679,6 +5765,13 @@ if (ret) return ret; + if (!tb[NL80211_FILS_DISCOVERY_ATTR_INT_MIN] && + !tb[NL80211_FILS_DISCOVERY_ATTR_INT_MAX] && + !tb[NL80211_FILS_DISCOVERY_ATTR_TMPL]) { + fd->update = true; + return 0; + } + if (!tb[NL80211_FILS_DISCOVERY_ATTR_INT_MIN] || !tb[NL80211_FILS_DISCOVERY_ATTR_INT_MAX] || !tb[NL80211_FILS_DISCOVERY_ATTR_TMPL]) @@ -5688,19 +5781,17 @@ fd->tmpl = nla_data(tb[NL80211_FILS_DISCOVERY_ATTR_TMPL]); fd->min_interval = nla_get_u32(tb[NL80211_FILS_DISCOVERY_ATTR_INT_MIN]); fd->max_interval = nla_get_u32(tb[NL80211_FILS_DISCOVERY_ATTR_INT_MAX]); - + fd->update = true; return 0; } static int nl80211_parse_unsol_bcast_probe_resp(struct cfg80211_registered_device *rdev, struct nlattr *attrs, - struct cfg80211_ap_settings *params) + struct cfg80211_unsol_bcast_probe_resp *presp) { struct nlattr *tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_MAX + 1]; int ret; - struct cfg80211_unsol_bcast_probe_resp *presp = - ¶ms->unsol_bcast_probe_resp; if (!wiphy_ext_feature_isset(&rdev->wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP)) @@ -5711,6 +5802,12 @@ if (ret) return ret; + if (!tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INT] && + !tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_TMPL]) { + presp->update = true; + return 0; + } + if (!tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INT] || !tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_TMPL]) return -EINVAL; @@ -5718,6 +5815,7 @@ presp->tmpl = nla_data(tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_TMPL]); presp->tmpl_len = nla_len(tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_TMPL]); presp->interval = nla_get_u32(tb[NL80211_UNSOL_BCAST_PROBE_RESP_ATTR_INT]); + presp->update = true; return 0; } @@ -5902,6 +6000,21 @@ nlmsg_free(msg); } +static int nl80211_validate_ap_phy_operation(struct cfg80211_ap_settings *params) +{ + struct ieee80211_channel *channel = params->chandef.chan; + + if ((params->he_cap || params->he_oper) && + (channel->flags & IEEE80211_CHAN_NO_HE)) + return -EOPNOTSUPP; + + if ((params->eht_cap || params->eht_oper) && + (channel->flags & IEEE80211_CHAN_NO_EHT)) + return -EOPNOTSUPP; + + return 0; +} + static int nl80211_start_ap(struct sk_buff *skb, struct genl_info *info) { struct cfg80211_registered_device *rdev = info->user_ptr[0]; @@ -6065,20 +6178,18 @@ goto out; } - wdev_lock(wdev); - if (info->attrs[NL80211_ATTR_TX_RATES]) { err = nl80211_parse_tx_bitrate_mask(info, info->attrs, NL80211_ATTR_TX_RATES, ¶ms->beacon_rate, dev, false, link_id); if (err) - goto out_unlock; + goto out; err = validate_beacon_tx_rate(rdev, params->chandef.chan->band, ¶ms->beacon_rate); if (err) - goto out_unlock; + goto out; } if (info->attrs[NL80211_ATTR_SMPS_MODE]) { @@ -6091,19 +6202,19 @@ if (!(rdev->wiphy.features & NL80211_FEATURE_STATIC_SMPS)) { err = -EINVAL; - goto out_unlock; + goto out; } break; case NL80211_SMPS_DYNAMIC: if (!(rdev->wiphy.features & NL80211_FEATURE_DYNAMIC_SMPS)) { err = -EINVAL; - goto out_unlock; + goto out; } break; default: err = -EINVAL; - goto out_unlock; + goto out; } } else { params->smps_mode = NL80211_SMPS_OFF; @@ -6112,7 +6223,7 @@ params->pbss = nla_get_flag(info->attrs[NL80211_ATTR_PBSS]); if (params->pbss && !rdev->wiphy.bands[NL80211_BAND_60GHZ]) { err = -EOPNOTSUPP; - goto out_unlock; + goto out; } if (info->attrs[NL80211_ATTR_ACL_POLICY]) { @@ -6120,7 +6231,7 @@ if (IS_ERR(params->acl)) { err = PTR_ERR(params->acl); params->acl = NULL; - goto out_unlock; + goto out; } } @@ -6132,23 +6243,23 @@ info->attrs[NL80211_ATTR_HE_OBSS_PD], ¶ms->he_obss_pd); if (err) - goto out_unlock; + goto out; } if (info->attrs[NL80211_ATTR_FILS_DISCOVERY]) { err = nl80211_parse_fils_discovery(rdev, info->attrs[NL80211_ATTR_FILS_DISCOVERY], - params); + ¶ms->fils_discovery); if (err) - goto out_unlock; + goto out; } if (info->attrs[NL80211_ATTR_UNSOL_BCAST_PROBE_RESP]) { err = nl80211_parse_unsol_bcast_probe_resp( rdev, info->attrs[NL80211_ATTR_UNSOL_BCAST_PROBE_RESP], - params); + ¶ms->unsol_bcast_probe_resp); if (err) - goto out_unlock; + goto out; } if (info->attrs[NL80211_ATTR_MBSSID_CONFIG]) { @@ -6159,17 +6270,21 @@ params->beacon.mbssid_ies->cnt : 0); if (err) - goto out_unlock; + goto out; } if (!params->mbssid_config.ema && params->beacon.rnr_ies) { err = -EINVAL; - goto out_unlock; + goto out; } err = nl80211_calculate_ap_params(params); if (err) - goto out_unlock; + goto out; + + err = nl80211_validate_ap_phy_operation(params); + if (err) + goto out; if (info->attrs[NL80211_ATTR_AP_SETTINGS_FLAGS]) params->flags = nla_get_u32( @@ -6181,7 +6296,7 @@ info->attrs[NL80211_ATTR_SOCKET_OWNER] && wdev->conn_owner_nlportid != info->snd_portid) { err = -EINVAL; - goto out_unlock; + goto out; } /* FIXME: validate MLO/link-id against driver capabilities */ @@ -6199,8 +6314,6 @@ nl80211_send_ap_started(wdev, link_id); } -out_unlock: - wdev_unlock(wdev); out: kfree(params->acl); kfree(params->beacon.mbssid_ies); @@ -6220,7 +6333,8 @@ unsigned int link_id = nl80211_link_id(info->attrs); struct net_device *dev = info->user_ptr[1]; struct wireless_dev *wdev = dev->ieee80211_ptr; - struct cfg80211_beacon_data params; + struct cfg80211_ap_update *params; + struct nlattr *attr; int err; if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_AP && @@ -6233,17 +6347,37 @@ if (!wdev->links[link_id].ap.beacon_interval) return -EINVAL; - err = nl80211_parse_beacon(rdev, info->attrs, ¶ms, info->extack); + params = kzalloc(sizeof(*params), GFP_KERNEL); + if (!params) + return -ENOMEM; + + err = nl80211_parse_beacon(rdev, info->attrs, ¶ms->beacon, + info->extack); if (err) goto out; - wdev_lock(wdev); - err = rdev_change_beacon(rdev, dev, ¶ms); - wdev_unlock(wdev); + attr = info->attrs[NL80211_ATTR_FILS_DISCOVERY]; + if (attr) { + err = nl80211_parse_fils_discovery(rdev, attr, + ¶ms->fils_discovery); + if (err) + goto out; + } + + attr = info->attrs[NL80211_ATTR_UNSOL_BCAST_PROBE_RESP]; + if (attr) { + err = nl80211_parse_unsol_bcast_probe_resp(rdev, attr, + ¶ms->unsol_bcast_probe_resp); + if (err) + goto out; + } + + err = rdev_change_beacon(rdev, dev, params); out: - kfree(params.mbssid_ies); - kfree(params.rnr_ies); + kfree(params->beacon.mbssid_ies); + kfree(params->beacon.rnr_ies); + kfree(params); return err; } @@ -6365,12 +6499,27 @@ return false; switch (info->bw) { + case RATE_INFO_BW_1: + rate_flg = NL80211_RATE_INFO_1_MHZ_WIDTH; + break; + case RATE_INFO_BW_2: + rate_flg = NL80211_RATE_INFO_2_MHZ_WIDTH; + break; + case RATE_INFO_BW_4: + rate_flg = NL80211_RATE_INFO_4_MHZ_WIDTH; + break; case RATE_INFO_BW_5: rate_flg = NL80211_RATE_INFO_5_MHZ_WIDTH; break; + case RATE_INFO_BW_8: + rate_flg = NL80211_RATE_INFO_8_MHZ_WIDTH; + break; case RATE_INFO_BW_10: rate_flg = NL80211_RATE_INFO_10_MHZ_WIDTH; break; + case RATE_INFO_BW_16: + rate_flg = NL80211_RATE_INFO_16_MHZ_WIDTH; + break; default: WARN_ON(1); fallthrough; @@ -6429,6 +6578,14 @@ nla_put_u8(msg, NL80211_RATE_INFO_HE_RU_ALLOC, info->he_ru_alloc)) return false; + } else if (info->flags & RATE_INFO_FLAGS_S1G_MCS) { + if (nla_put_u8(msg, NL80211_RATE_INFO_S1G_MCS, info->mcs)) + return false; + if (nla_put_u8(msg, NL80211_RATE_INFO_S1G_NSS, info->nss)) + return false; + if (info->flags & RATE_INFO_FLAGS_SHORT_GI && + nla_put_flag(msg, NL80211_RATE_INFO_SHORT_GI)) + return false; } else if (info->flags & RATE_INFO_FLAGS_EHT_MCS) { if (nla_put_u8(msg, NL80211_RATE_INFO_EHT_MCS, info->mcs)) return false; @@ -7124,6 +7281,34 @@ return 0; } +static const +struct nla_policy nl80211_sta_info_policy[NL80211_STA_INFO_MAX+1] = { + [NL80211_STA_INFO_EXPECTED_THROUGHPUT] = { .type = NLA_U32 }, +}; + +static int nl80211_parse_sta_info(struct genl_info *info, + struct station_parameters *params) +{ + struct nlattr *tb[NL80211_STA_INFO_MAX + 1]; + + if (!info->attrs[NL80211_ATTR_STA_INFO]) + return 0; + if (nla_parse_nested_deprecated(tb, + NL80211_STA_INFO_MAX, + info->attrs[NL80211_ATTR_STA_INFO], + nl80211_sta_info_policy, + info->extack)) + return -EINVAL; + + if (tb[NL80211_STA_INFO_EXPECTED_THROUGHPUT]) { + params->link_sta_params.tp_overridden = true; + params->link_sta_params.tp_override = + nla_get_u32(tb[NL80211_STA_INFO_EXPECTED_THROUGHPUT]); + } + + return 0; +} + static int nl80211_set_station(struct sk_buff *skb, struct genl_info *info) { struct cfg80211_registered_device *rdev = info->user_ptr[0]; @@ -7256,6 +7441,10 @@ if (err) return err; + err = nl80211_parse_sta_info(info, ¶ms); + if (err) + return err; + params.vlan = get_vlan(info, rdev); if (IS_ERR(params.vlan)) return PTR_ERR(params.vlan); @@ -7275,9 +7464,7 @@ } /* driver will call cfg80211_check_station_change() */ - wdev_lock(dev->ieee80211_ptr); err = rdev_change_station(rdev, dev, mac_addr, ¶ms); - wdev_unlock(dev->ieee80211_ptr); out_put_vlan: dev_put(params.vlan); @@ -7457,6 +7644,10 @@ (params.link_sta_params.ht_capa || params.link_sta_params.vht_capa)) return -EINVAL; + /* Ensure that HE capabilities are set along with EHT */ + if (params.link_sta_params.eht_capa && !params.link_sta_params.he_capa) + return -EINVAL; + /* When you run into this, adjust the code below for the new flag */ BUILD_BUG_ON(NL80211_STA_FLAG_MAX != 7); @@ -7545,7 +7736,6 @@ /* be aware of params.vlan when changing code here */ - wdev_lock(dev->ieee80211_ptr); if (wdev->valid_links) { if (params.link_sta_params.link_id < 0) { err = -EINVAL; @@ -7563,7 +7753,6 @@ } err = rdev_add_station(rdev, dev, mac_addr, ¶ms); out: - wdev_unlock(dev->ieee80211_ptr); dev_put(params.vlan); return err; } @@ -7573,7 +7762,6 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; struct station_del_parameters params; - int ret; memset(¶ms, 0, sizeof(params)); @@ -7621,11 +7809,7 @@ params.reason_code = WLAN_REASON_PREV_AUTH_NOT_VALID; } - wdev_lock(dev->ieee80211_ptr); - ret = rdev_del_station(rdev, dev, ¶ms); - wdev_unlock(dev->ieee80211_ptr); - - return ret; + return rdev_del_station(rdev, dev, ¶ms); } static int nl80211_send_mpath(struct sk_buff *msg, u32 portid, u32 seq, @@ -7944,9 +8128,7 @@ { struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; - struct wireless_dev *wdev = dev->ieee80211_ptr; struct bss_parameters params; - int err; memset(¶ms, 0, sizeof(params)); params.link_id = nl80211_link_id_or_invalid(info->attrs); @@ -8009,11 +8191,7 @@ dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_GO) return -EOPNOTSUPP; - wdev_lock(wdev); - err = rdev_change_bss(rdev, dev, ¶ms); - wdev_unlock(wdev); - - return err; + return rdev_change_bss(rdev, dev, ¶ms); } static int nl80211_req_set_reg(struct sk_buff *skb, struct genl_info *info) @@ -8084,13 +8262,11 @@ if (!rdev->ops->get_mesh_config) return -EOPNOTSUPP; - wdev_lock(wdev); /* If not connected, get default parameters */ if (!wdev->u.mesh.id_len) memcpy(&cur_params, &default_mesh_config, sizeof(cur_params)); else err = rdev_get_mesh_config(rdev, dev, &cur_params); - wdev_unlock(wdev); if (err) return err; @@ -8452,7 +8628,7 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; struct wireless_dev *wdev = dev->ieee80211_ptr; - struct mesh_config cfg; + struct mesh_config cfg = {}; u32 mask; int err; @@ -8466,15 +8642,12 @@ if (err) return err; - wdev_lock(wdev); if (!wdev->u.mesh.id_len) err = -ENOLINK; if (!err) err = rdev_update_mesh_config(rdev, dev, mask, &cfg); - wdev_unlock(wdev); - return err; } @@ -8529,6 +8702,11 @@ reg_rule->dfs_cac_ms)) goto nla_put_failure; + if ((reg_rule->flags & NL80211_RRF_PSD) && + nla_put_s8(msg, NL80211_ATTR_POWER_RULE_PSD, + reg_rule->psd)) + goto nla_put_failure; + nla_nest_end(msg, nl_reg_rule); } @@ -8965,7 +9143,7 @@ unsigned int link_id; bool all_ok = true; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!cfg80211_beaconing_iface_active(wdev)) return true; @@ -9215,7 +9393,6 @@ request->n_channels = i; - wdev_lock(wdev); for (i = 0; i < request->n_channels; i++) { struct ieee80211_channel *chan = request->channels[i]; @@ -9224,12 +9401,10 @@ continue; if (!cfg80211_wdev_on_sub_chan(wdev, chan, true)) { - wdev_unlock(wdev); err = -EBUSY; goto out_free; } } - wdev_unlock(wdev); i = 0; if (n_ssids) { @@ -10235,9 +10410,7 @@ goto free; } - wdev_lock(wdev); err = rdev_channel_switch(rdev, dev, ¶ms); - wdev_unlock(wdev); free: kfree(params.beacon_after.mbssid_ies); @@ -10260,7 +10433,7 @@ void *hdr; struct nlattr *bss; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); hdr = nl80211hdr_put(msg, NETLINK_CB(cb->skb).portid, seq, flags, NL80211_CMD_NEW_SCAN_RESULTS); @@ -10323,7 +10496,6 @@ nla_put_u32(msg, NL80211_BSS_FREQUENCY, res->channel->center_freq) || nla_put_u32(msg, NL80211_BSS_FREQUENCY_OFFSET, res->channel->freq_offset) || - nla_put_u32(msg, NL80211_BSS_CHAN_WIDTH, res->scan_width) || nla_put_u32(msg, NL80211_BSS_SEEN_MS_AGO, jiffies_to_msecs(jiffies - intbss->ts))) goto nla_put_failure; @@ -10409,7 +10581,6 @@ /* nl80211_prepare_wdev_dump acquired it in the successful case */ __acquire(&rdev->wiphy.mtx); - wdev_lock(wdev); spin_lock_bh(&rdev->bss_lock); /* @@ -10435,7 +10606,6 @@ } spin_unlock_bh(&rdev->bss_lock); - wdev_unlock(wdev); cb->args[2] = idx; wiphy_unlock(&rdev->wiphy); @@ -10558,9 +10728,7 @@ } while (1) { - wdev_lock(wdev); res = rdev_dump_survey(rdev, wdev->netdev, survey_idx, &survey); - wdev_unlock(wdev); if (res == -ENOENT) break; if (res) @@ -10733,9 +10901,7 @@ if (!req.bss) return -ENOENT; - wdev_lock(dev->ieee80211_ptr); err = cfg80211_mlme_auth(rdev, dev, &req); - wdev_unlock(dev->ieee80211_ptr); cfg80211_put_bss(&rdev->wiphy, req.bss); @@ -10945,7 +11111,8 @@ if (cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, req.ie, req.ie_len)) { - GENL_SET_ERR_MSG(info, + NL_SET_ERR_MSG_ATTR(info->extack, + info->attrs[NL80211_ATTR_IE], "non-inheritance makes no sense"); return -EINVAL; } @@ -11071,6 +11238,7 @@ if (!attrs[NL80211_ATTR_MLO_LINK_ID]) { err = -EINVAL; + NL_SET_BAD_ATTR(info->extack, link); goto free; } @@ -11078,6 +11246,7 @@ /* cannot use the same link ID again */ if (req.links[link_id].bss) { err = -EINVAL; + NL_SET_BAD_ATTR(info->extack, link); goto free; } req.links[link_id].bss = @@ -11085,6 +11254,8 @@ if (IS_ERR(req.links[link_id].bss)) { err = PTR_ERR(req.links[link_id].bss); req.links[link_id].bss = NULL; + NL_SET_ERR_MSG_ATTR(info->extack, + link, "Error fetching BSS for link"); goto free; } @@ -11097,7 +11268,8 @@ if (cfg80211_find_elem(WLAN_EID_FRAGMENT, req.links[link_id].elems, req.links[link_id].elems_len)) { - GENL_SET_ERR_MSG(info, + NL_SET_ERR_MSG_ATTR(info->extack, + attrs[NL80211_ATTR_IE], "cannot deal with fragmentation"); err = -EINVAL; goto free; @@ -11106,12 +11278,16 @@ if (cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, req.links[link_id].elems, req.links[link_id].elems_len)) { - GENL_SET_ERR_MSG(info, + NL_SET_ERR_MSG_ATTR(info->extack, + attrs[NL80211_ATTR_IE], "cannot deal with non-inheritance"); err = -EINVAL; goto free; } } + + req.links[link_id].disabled = + nla_get_flag(attrs[NL80211_ATTR_MLO_LINK_DISABLED]); } if (!req.links[req.link_id].bss) { @@ -11126,6 +11302,13 @@ goto free; } + if (req.links[req.link_id].disabled) { + GENL_SET_ERR_MSG(info, + "cannot have assoc link disabled"); + err = -EINVAL; + goto free; + } + kfree(attrs); attrs = NULL; } else { @@ -11140,7 +11323,8 @@ err = nl80211_crypto_settings(rdev, info, &req.crypto, 1); if (!err) { - wdev_lock(dev->ieee80211_ptr); + struct nlattr *link; + int rem = 0; err = cfg80211_mlme_assoc(rdev, dev, &req); @@ -11151,7 +11335,33 @@ ap_addr, ETH_ALEN); } - wdev_unlock(dev->ieee80211_ptr); + /* Report error from first problematic link */ + if (info->attrs[NL80211_ATTR_MLO_LINKS]) { + nla_for_each_nested(link, + info->attrs[NL80211_ATTR_MLO_LINKS], + rem) { + struct nlattr *link_id_attr = + nla_find_nested(link, NL80211_ATTR_MLO_LINK_ID); + + if (!link_id_attr) + continue; + + link_id = nla_get_u8(link_id_attr); + + if (link_id == req.link_id) + continue; + + if (!req.links[link_id].error || + WARN_ON(req.links[link_id].error > 0)) + continue; + + WARN_ON(err >= 0); + + NL_SET_BAD_ATTR(info->extack, link); + err = req.links[link_id].error; + break; + } + } } free: @@ -11168,7 +11378,7 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; const u8 *ie = NULL, *bssid; - int ie_len = 0, err; + int ie_len = 0; u16 reason_code; bool local_state_change; @@ -11204,11 +11414,8 @@ local_state_change = !!info->attrs[NL80211_ATTR_LOCAL_STATE_CHANGE]; - wdev_lock(dev->ieee80211_ptr); - err = cfg80211_mlme_deauth(rdev, dev, bssid, ie, ie_len, reason_code, + return cfg80211_mlme_deauth(rdev, dev, bssid, ie, ie_len, reason_code, local_state_change); - wdev_unlock(dev->ieee80211_ptr); - return err; } static int nl80211_disassociate(struct sk_buff *skb, struct genl_info *info) @@ -11216,7 +11423,7 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; const u8 *ie = NULL, *bssid; - int ie_len = 0, err; + int ie_len = 0; u16 reason_code; bool local_state_change; @@ -11252,11 +11459,8 @@ local_state_change = !!info->attrs[NL80211_ATTR_LOCAL_STATE_CHANGE]; - wdev_lock(dev->ieee80211_ptr); - err = cfg80211_mlme_disassoc(rdev, dev, bssid, ie, ie_len, reason_code, + return cfg80211_mlme_disassoc(rdev, dev, bssid, ie, ie_len, reason_code, local_state_change); - wdev_unlock(dev->ieee80211_ptr); - return err; } static bool @@ -11434,13 +11638,11 @@ ibss.userspace_handles_dfs = nla_get_flag(info->attrs[NL80211_ATTR_HANDLE_DFS]); - wdev_lock(dev->ieee80211_ptr); err = __cfg80211_join_ibss(rdev, dev, &ibss, connkeys); if (err) kfree_sensitive(connkeys); else if (info->attrs[NL80211_ATTR_SOCKET_OWNER]) dev->ieee80211_ptr->conn_owner_nlportid = info->snd_portid; - wdev_unlock(dev->ieee80211_ptr); return err; } @@ -11973,8 +12175,6 @@ if (nla_get_flag(info->attrs[NL80211_ATTR_MLO_SUPPORT])) connect.flags |= CONNECT_REQ_MLO_SUPPORT; - wdev_lock(dev->ieee80211_ptr); - err = cfg80211_connect(rdev, dev, &connect, connkeys, connect.prev_bssid); if (err) @@ -11989,8 +12189,6 @@ eth_zero_addr(dev->ieee80211_ptr->disconnect_bssid); } - wdev_unlock(dev->ieee80211_ptr); - return err; } @@ -12004,7 +12202,6 @@ bool fils_sk_offload; u32 auth_type; u32 changed = 0; - int ret; if (!rdev->ops->update_connect_params) return -EOPNOTSUPP; @@ -12065,14 +12262,10 @@ changed |= UPDATE_AUTH_TYPE; } - wdev_lock(dev->ieee80211_ptr); if (!wdev->connected) - ret = -ENOLINK; - else - ret = rdev_update_connect_params(rdev, dev, &connect, changed); - wdev_unlock(dev->ieee80211_ptr); + return -ENOLINK; - return ret; + return rdev_update_connect_params(rdev, dev, &connect, changed); } static int nl80211_disconnect(struct sk_buff *skb, struct genl_info *info) @@ -12080,7 +12273,6 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; u16 reason; - int ret; if (dev->ieee80211_ptr->conn_owner_nlportid && dev->ieee80211_ptr->conn_owner_nlportid != info->snd_portid) @@ -12098,10 +12290,7 @@ dev->ieee80211_ptr->iftype != NL80211_IFTYPE_P2P_CLIENT) return -EOPNOTSUPP; - wdev_lock(dev->ieee80211_ptr); - ret = cfg80211_disconnect(rdev, dev, reason, true); - wdev_unlock(dev->ieee80211_ptr); - return ret; + return cfg80211_disconnect(rdev, dev, reason, true); } static int nl80211_wiphy_netns(struct sk_buff *skb, struct genl_info *info) @@ -12225,6 +12414,7 @@ u32 peer_capability = 0; u16 status_code; u8 *peer; + int link_id; bool initiator; if (!(rdev->wiphy.flags & WIPHY_FLAG_SUPPORTS_TDLS) || @@ -12246,8 +12436,9 @@ if (info->attrs[NL80211_ATTR_TDLS_PEER_CAPABILITY]) peer_capability = nla_get_u32(info->attrs[NL80211_ATTR_TDLS_PEER_CAPABILITY]); + link_id = nl80211_link_id_or_invalid(info->attrs); - return rdev_tdls_mgmt(rdev, dev, peer, action_code, + return rdev_tdls_mgmt(rdev, dev, peer, link_id, action_code, dialog_token, status_code, peer_capability, initiator, nla_data(info->attrs[NL80211_ATTR_IE]), @@ -12310,7 +12501,6 @@ if (err) return err; - wdev_lock(wdev); if (!cfg80211_off_channel_oper_allowed(wdev, chandef.chan)) { const struct cfg80211_chan_def *oper_chandef, *compat_chandef; @@ -12319,7 +12509,6 @@ if (WARN_ON(!oper_chandef)) { /* cannot happen since we must beacon to get here */ WARN_ON(1); - wdev_unlock(wdev); return -EBUSY; } @@ -12327,12 +12516,9 @@ compat_chandef = cfg80211_chandef_compatible(&chandef, oper_chandef); - if (compat_chandef != &chandef) { - wdev_unlock(wdev); + if (compat_chandef != &chandef) return -EBUSY; } - } - wdev_unlock(wdev); msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); if (!msg) @@ -12391,23 +12577,18 @@ unsigned int link_id = nl80211_link_id(info->attrs); struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; - struct wireless_dev *wdev = dev->ieee80211_ptr; int err; if (!rdev->ops->set_bitrate_mask) return -EOPNOTSUPP; - wdev_lock(wdev); err = nl80211_parse_tx_bitrate_mask(info, info->attrs, NL80211_ATTR_TX_RATES, &mask, dev, true, link_id); if (err) - goto out; - - err = rdev_set_bitrate_mask(rdev, dev, link_id, NULL, &mask); -out: - wdev_unlock(wdev); return err; + + return rdev_set_bitrate_mask(rdev, dev, link_id, NULL, &mask); } static int nl80211_register_mgmt(struct sk_buff *skb, struct genl_info *info) @@ -12536,12 +12717,9 @@ if (!chandef.chan && params.offchan) return -EINVAL; - wdev_lock(wdev); if (params.offchan && - !cfg80211_off_channel_oper_allowed(wdev, chandef.chan)) { - wdev_unlock(wdev); + !cfg80211_off_channel_oper_allowed(wdev, chandef.chan)) return -EBUSY; - } params.link_id = nl80211_link_id_or_invalid(info->attrs); /* @@ -12550,11 +12728,8 @@ * to the driver. */ if (params.link_id >= 0 && - !(wdev->valid_links & BIT(params.link_id))) { - wdev_unlock(wdev); + !(wdev->valid_links & BIT(params.link_id))) return -EINVAL; - } - wdev_unlock(wdev); params.buf = nla_data(info->attrs[NL80211_ATTR_FRAME]); params.len = nla_len(info->attrs[NL80211_ATTR_FRAME]); @@ -12754,7 +12929,8 @@ } static int cfg80211_cqm_rssi_update(struct cfg80211_registered_device *rdev, - struct net_device *dev) + struct net_device *dev, + struct cfg80211_cqm_config *cqm_config) { struct wireless_dev *wdev = dev->ieee80211_ptr; s32 last, low, high; @@ -12763,7 +12939,7 @@ int err; /* RSSI reporting disabled? */ - if (!wdev->cqm_config) + if (!cqm_config) return rdev_set_cqm_rssi_range_config(rdev, dev, 0, 0); /* @@ -12772,7 +12948,7 @@ * connection is established and enough beacons received to calculate * the average. */ - if (!wdev->cqm_config->last_rssi_event_value && + if (!cqm_config->last_rssi_event_value && wdev->links[0].client.current_bss && rdev->ops->get_station) { struct station_info sinfo = {}; @@ -12786,30 +12962,30 @@ cfg80211_sinfo_release_content(&sinfo); if (sinfo.filled & BIT_ULL(NL80211_STA_INFO_BEACON_SIGNAL_AVG)) - wdev->cqm_config->last_rssi_event_value = + cqm_config->last_rssi_event_value = (s8) sinfo.rx_beacon_signal_avg; } - last = wdev->cqm_config->last_rssi_event_value; - hyst = wdev->cqm_config->rssi_hyst; - n = wdev->cqm_config->n_rssi_thresholds; + last = cqm_config->last_rssi_event_value; + hyst = cqm_config->rssi_hyst; + n = cqm_config->n_rssi_thresholds; for (i = 0; i < n; i++) { i = array_index_nospec(i, n); - if (last < wdev->cqm_config->rssi_thresholds[i]) + if (last < cqm_config->rssi_thresholds[i]) break; } low_index = i - 1; if (low_index >= 0) { low_index = array_index_nospec(low_index, n); - low = wdev->cqm_config->rssi_thresholds[low_index] - hyst; + low = cqm_config->rssi_thresholds[low_index] - hyst; } else { low = S32_MIN; } if (i < n) { i = array_index_nospec(i, n); - high = wdev->cqm_config->rssi_thresholds[i] + hyst - 1; + high = cqm_config->rssi_thresholds[i] + hyst - 1; } else { high = S32_MAX; } @@ -12822,10 +12998,11 @@ u32 hysteresis) { struct cfg80211_registered_device *rdev = info->user_ptr[0]; + struct cfg80211_cqm_config *cqm_config = NULL, *old; struct net_device *dev = info->user_ptr[1]; struct wireless_dev *wdev = dev->ieee80211_ptr; - int i, err; s32 prev = S32_MIN; + int i, err; /* Check all values negative and sorted */ for (i = 0; i < n_thresholds; i++) { @@ -12839,10 +13016,6 @@ wdev->iftype != NL80211_IFTYPE_P2P_CLIENT) return -EOPNOTSUPP; - wdev_lock(wdev); - cfg80211_cqm_config_free(wdev); - wdev_unlock(wdev); - if (n_thresholds <= 1 && rdev->ops->set_cqm_rssi_config) { if (n_thresholds == 0 || thresholds[0] == 0) /* Disabling */ return rdev_set_cqm_rssi_config(rdev, dev, 0, 0); @@ -12858,17 +13031,14 @@ if (n_thresholds == 1 && thresholds[0] == 0) /* Disabling */ n_thresholds = 0; - wdev_lock(wdev); - if (n_thresholds) { - struct cfg80211_cqm_config *cqm_config; + old = wiphy_dereference(wdev->wiphy, wdev->cqm_config); + if (n_thresholds) { cqm_config = kzalloc(struct_size(cqm_config, rssi_thresholds, n_thresholds), GFP_KERNEL); - if (!cqm_config) { - err = -ENOMEM; - goto unlock; - } + if (!cqm_config) + return -ENOMEM; cqm_config->rssi_hyst = hysteresis; cqm_config->n_rssi_thresholds = n_thresholds; @@ -12876,13 +13046,18 @@ flex_array_size(cqm_config, rssi_thresholds, n_thresholds)); - wdev->cqm_config = cqm_config; + rcu_assign_pointer(wdev->cqm_config, cqm_config); + } else { + RCU_INIT_POINTER(wdev->cqm_config, NULL); } - err = cfg80211_cqm_rssi_update(rdev, dev); - -unlock: - wdev_unlock(wdev); + err = cfg80211_cqm_rssi_update(rdev, dev, cqm_config); + if (err) { + rcu_assign_pointer(wdev->cqm_config, old); + kfree_rcu(cqm_config, rcu_head); + } else { + kfree_rcu(old, rcu_head); + } return err; } @@ -13066,11 +13241,9 @@ setup.control_port_over_nl80211 = true; } - wdev_lock(dev->ieee80211_ptr); err = __cfg80211_join_mesh(rdev, dev, &setup, &cfg); if (!err && info->attrs[NL80211_ATTR_SOCKET_OWNER]) dev->ieee80211_ptr->conn_owner_nlportid = info->snd_portid; - wdev_unlock(dev->ieee80211_ptr); return err; } @@ -14014,21 +14187,13 @@ if (tb[NL80211_REKEY_DATA_AKM]) rekey_data.akm = nla_get_u32(tb[NL80211_REKEY_DATA_AKM]); - wdev_lock(wdev); - if (!wdev->connected) { - err = -ENOTCONN; - goto out; - } + if (!wdev->connected) + return -ENOTCONN; - if (!rdev->ops->set_rekey_data) { - err = -EOPNOTSUPP; - goto out; - } + if (!rdev->ops->set_rekey_data) + return -EOPNOTSUPP; - err = rdev_set_rekey_data(rdev, dev, &rekey_data); - out: - wdev_unlock(wdev); - return err; + return rdev_set_rekey_data(rdev, dev, &rekey_data); } static int nl80211_register_unexpected_frame(struct sk_buff *skb, @@ -15232,11 +15397,9 @@ memcpy(qos_map->up, pos, IEEE80211_QOS_MAP_LEN_MIN); } - wdev_lock(dev->ieee80211_ptr); ret = nl80211_key_allowed(dev->ieee80211_ptr); if (!ret) ret = rdev_set_qos_map(rdev, dev, qos_map); - wdev_unlock(dev->ieee80211_ptr); kfree(qos_map); return ret; @@ -15250,7 +15413,6 @@ const u8 *peer; u8 tsid, up; u16 admitted_time = 0; - int err; if (!(rdev->wiphy.features & NL80211_FEATURE_SUPPORTS_WMM_ADMISSION)) return -EOPNOTSUPP; @@ -15280,34 +15442,25 @@ return -EINVAL; } - wdev_lock(wdev); switch (wdev->iftype) { case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: if (wdev->connected) break; - err = -ENOTCONN; - goto out; + return -ENOTCONN; default: - err = -EOPNOTSUPP; - goto out; + return -EOPNOTSUPP; } - err = rdev_add_tx_ts(rdev, dev, tsid, peer, up, admitted_time); - - out: - wdev_unlock(wdev); - return err; + return rdev_add_tx_ts(rdev, dev, tsid, peer, up, admitted_time); } static int nl80211_del_tx_ts(struct sk_buff *skb, struct genl_info *info) { struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; - struct wireless_dev *wdev = dev->ieee80211_ptr; const u8 *peer; u8 tsid; - int err; if (!info->attrs[NL80211_ATTR_TSID] || !info->attrs[NL80211_ATTR_MAC]) return -EINVAL; @@ -15315,11 +15468,7 @@ tsid = nla_get_u8(info->attrs[NL80211_ATTR_TSID]); peer = nla_data(info->attrs[NL80211_ATTR_MAC]); - wdev_lock(wdev); - err = rdev_del_tx_ts(rdev, dev, tsid, peer); - wdev_unlock(wdev); - - return err; + return rdev_del_tx_ts(rdev, dev, tsid, peer); } static int nl80211_tdls_channel_switch(struct sk_buff *skb, @@ -15375,11 +15524,7 @@ addr = nla_data(info->attrs[NL80211_ATTR_MAC]); oper_class = nla_get_u8(info->attrs[NL80211_ATTR_OPER_CLASS]); - wdev_lock(wdev); - err = rdev_tdls_channel_switch(rdev, dev, addr, oper_class, &chandef); - wdev_unlock(wdev); - - return err; + return rdev_tdls_channel_switch(rdev, dev, addr, oper_class, &chandef); } static int nl80211_tdls_cancel_channel_switch(struct sk_buff *skb, @@ -15387,7 +15532,6 @@ { struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; - struct wireless_dev *wdev = dev->ieee80211_ptr; const u8 *addr; if (!rdev->ops->tdls_channel_switch || @@ -15408,9 +15552,7 @@ addr = nla_data(info->attrs[NL80211_ATTR_MAC]); - wdev_lock(wdev); rdev_tdls_cancel_channel_switch(rdev, dev, addr); - wdev_unlock(wdev); return 0; } @@ -15443,7 +15585,6 @@ struct net_device *dev = info->user_ptr[1]; struct wireless_dev *wdev = dev->ieee80211_ptr; struct cfg80211_pmk_conf pmk_conf = {}; - int ret; if (wdev->iftype != NL80211_IFTYPE_STATION && wdev->iftype != NL80211_IFTYPE_P2P_CLIENT) @@ -15456,34 +15597,24 @@ if (!info->attrs[NL80211_ATTR_MAC] || !info->attrs[NL80211_ATTR_PMK]) return -EINVAL; - wdev_lock(wdev); - if (!wdev->connected) { - ret = -ENOTCONN; - goto out; - } + if (!wdev->connected) + return -ENOTCONN; pmk_conf.aa = nla_data(info->attrs[NL80211_ATTR_MAC]); - if (memcmp(pmk_conf.aa, wdev->u.client.connected_addr, ETH_ALEN)) { - ret = -EINVAL; - goto out; - } + if (memcmp(pmk_conf.aa, wdev->u.client.connected_addr, ETH_ALEN)) + return -EINVAL; pmk_conf.pmk = nla_data(info->attrs[NL80211_ATTR_PMK]); pmk_conf.pmk_len = nla_len(info->attrs[NL80211_ATTR_PMK]); if (pmk_conf.pmk_len != WLAN_PMK_LEN && - pmk_conf.pmk_len != WLAN_PMK_LEN_SUITE_B_192) { - ret = -EINVAL; - goto out; - } + pmk_conf.pmk_len != WLAN_PMK_LEN_SUITE_B_192) + return -EINVAL; if (info->attrs[NL80211_ATTR_PMKR0_NAME]) pmk_conf.pmk_r0_name = nla_data(info->attrs[NL80211_ATTR_PMKR0_NAME]); - ret = rdev_set_pmk(rdev, dev, &pmk_conf); -out: - wdev_unlock(wdev); - return ret; + return rdev_set_pmk(rdev, dev, &pmk_conf); } static int nl80211_del_pmk(struct sk_buff *skb, struct genl_info *info) @@ -15492,7 +15623,6 @@ struct net_device *dev = info->user_ptr[1]; struct wireless_dev *wdev = dev->ieee80211_ptr; const u8 *aa; - int ret; if (wdev->iftype != NL80211_IFTYPE_STATION && wdev->iftype != NL80211_IFTYPE_P2P_CLIENT) @@ -15505,12 +15635,8 @@ if (!info->attrs[NL80211_ATTR_MAC]) return -EINVAL; - wdev_lock(wdev); aa = nla_data(info->attrs[NL80211_ATTR_MAC]); - ret = rdev_del_pmk(rdev, dev, aa); - wdev_unlock(wdev); - - return ret; + return rdev_del_pmk(rdev, dev, aa); } static int nl80211_external_auth(struct sk_buff *skb, struct genl_info *info) @@ -15584,8 +15710,6 @@ return -EINVAL; } - wdev_lock(wdev); - switch (wdev->iftype) { case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: @@ -15594,21 +15718,16 @@ case NL80211_IFTYPE_ADHOC: if (wdev->u.ibss.current_bss) break; - err = -ENOTCONN; - goto out; + return -ENOTCONN; case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: if (wdev->connected) break; - err = -ENOTCONN; - goto out; + return -ENOTCONN; default: - err = -EOPNOTSUPP; - goto out; + return -EOPNOTSUPP; } - wdev_unlock(wdev); - buf = nla_data(info->attrs[NL80211_ATTR_FRAME]); len = nla_len(info->attrs[NL80211_ATTR_FRAME]); dest = nla_data(info->attrs[NL80211_ATTR_MAC]); @@ -15624,9 +15743,6 @@ if (!err && !dont_wait_for_ack) nl_set_extack_cookie_u64(info->extack, cookie); return err; - out: - wdev_unlock(wdev); - return err; } static int nl80211_get_ftm_responder_stats(struct sk_buff *skb, @@ -15904,8 +16020,6 @@ if (info->attrs[NL80211_ATTR_MAC]) tid_config->peer = nla_data(info->attrs[NL80211_ATTR_MAC]); - wdev_lock(dev->ieee80211_ptr); - nla_for_each_nested(tid, info->attrs[NL80211_ATTR_TID_CONFIG], rem_conf) { ret = nla_parse_nested(attrs, NL80211_TID_CONFIG_ATTR_MAX, @@ -15927,7 +16041,6 @@ bad_tid_conf: kfree(tid_config); - wdev_unlock(dev->ieee80211_ptr); return ret; } @@ -16024,9 +16137,7 @@ params.counter_offset_presp = offset; } - wdev_lock(wdev); err = rdev_color_change(rdev, dev, ¶ms); - wdev_unlock(wdev); out: kfree(params.beacon_next.mbssid_ies); @@ -16082,7 +16193,6 @@ !is_valid_ether_addr(nla_data(info->attrs[NL80211_ATTR_MAC]))) return -EINVAL; - wdev_lock(wdev); wdev->valid_links |= BIT(link_id); ether_addr_copy(wdev->links[link_id].addr, nla_data(info->attrs[NL80211_ATTR_MAC])); @@ -16092,7 +16202,6 @@ wdev->valid_links &= ~BIT(link_id); eth_zero_addr(wdev->links[link_id].addr); } - wdev_unlock(wdev); return ret; } @@ -16114,9 +16223,7 @@ return -EINVAL; } - wdev_lock(wdev); cfg80211_remove_link(wdev, link_id); - wdev_unlock(wdev); return 0; } @@ -16206,14 +16313,10 @@ if (err) return err; - wdev_lock(dev->ieee80211_ptr); if (add) - err = rdev_add_link_station(rdev, dev, ¶ms); - else - err = rdev_mod_link_station(rdev, dev, ¶ms); - wdev_unlock(dev->ieee80211_ptr); + return rdev_add_link_station(rdev, dev, ¶ms); - return err; + return rdev_mod_link_station(rdev, dev, ¶ms); } static int @@ -16234,7 +16337,6 @@ struct link_station_del_parameters params = {}; struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; - int ret; if (!rdev->ops->del_link_station) return -EOPNOTSUPP; @@ -16246,11 +16348,7 @@ params.mld_mac = nla_data(info->attrs[NL80211_ATTR_MLD_ADDR]); params.link_id = nla_get_u8(info->attrs[NL80211_ATTR_MLO_LINK_ID]); - wdev_lock(dev->ieee80211_ptr); - ret = rdev_del_link_station(rdev, dev, ¶ms); - wdev_unlock(dev->ieee80211_ptr); - - return ret; + return rdev_del_link_station(rdev, dev, ¶ms); } static int nl80211_set_hw_timestamp(struct sk_buff *skb, @@ -17114,7 +17212,8 @@ .validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP, .doit = nl80211_tdls_mgmt, .flags = GENL_UNS_ADMIN_PERM, - .internal_flags = IFLAGS(NL80211_FLAG_NEED_NETDEV_UP), + .internal_flags = IFLAGS(NL80211_FLAG_NEED_NETDEV_UP | + NL80211_FLAG_MLO_VALID_LINK_ID), }, { .cmd = NL80211_CMD_TDLS_OPER, @@ -17851,7 +17950,7 @@ void nl80211_send_rx_assoc(struct cfg80211_registered_device *rdev, struct net_device *netdev, - struct cfg80211_rx_assoc_resp *data) + struct cfg80211_rx_assoc_resp_data *data) { nl80211_send_mlme_event(rdev, netdev, data->buf, data->len, NL80211_CMD_ASSOCIATE, GFP_KERNEL, @@ -18176,7 +18275,7 @@ } void nl80211_send_port_authorized(struct cfg80211_registered_device *rdev, - struct net_device *netdev, const u8 *bssid, + struct net_device *netdev, const u8 *peer_addr, const u8 *td_bitmap, u8 td_bitmap_len) { struct sk_buff *msg; @@ -18194,7 +18293,7 @@ if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) || nla_put_u32(msg, NL80211_ATTR_IFINDEX, netdev->ifindex) || - nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, bssid)) + nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, peer_addr)) goto nla_put_failure; if ((td_bitmap_len > 0) && td_bitmap) @@ -18248,6 +18347,76 @@ nlmsg_free(msg); } +void cfg80211_links_removed(struct net_device *dev, u16 link_mask) +{ + struct wireless_dev *wdev = dev->ieee80211_ptr; + struct wiphy *wiphy = wdev->wiphy; + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + struct sk_buff *msg; + struct nlattr *links; + void *hdr; + + lockdep_assert_wiphy(wdev->wiphy); + trace_cfg80211_links_removed(dev, link_mask); + + if (WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION && + wdev->iftype != NL80211_IFTYPE_P2P_CLIENT)) + return; + + if (WARN_ON(!wdev->valid_links || !link_mask || + (wdev->valid_links & link_mask) != link_mask || + wdev->valid_links == link_mask)) + return; + + cfg80211_wdev_release_link_bsses(wdev, link_mask); + wdev->valid_links &= ~link_mask; + + msg = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); + if (!msg) + return; + + hdr = nl80211hdr_put(msg, 0, 0, 0, NL80211_CMD_LINKS_REMOVED); + if (!hdr) { + nlmsg_free(msg); + return; + } + + if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) || + nla_put_u32(msg, NL80211_ATTR_IFINDEX, dev->ifindex)) + goto nla_put_failure; + + links = nla_nest_start(msg, NL80211_ATTR_MLO_LINKS); + if (!links) + goto nla_put_failure; + + while (link_mask) { + struct nlattr *link; + int link_id = __ffs(link_mask); + + link = nla_nest_start(msg, link_id + 1); + if (!link) + goto nla_put_failure; + + if (nla_put_u8(msg, NL80211_ATTR_MLO_LINK_ID, link_id)) + goto nla_put_failure; + + nla_nest_end(msg, link); + link_mask &= ~(1 << link_id); + } + + nla_nest_end(msg, links); + + genlmsg_end(msg, hdr); + + genlmsg_multicast_netns(&nl80211_fam, wiphy_net(&rdev->wiphy), msg, 0, + NL80211_MCGRP_MLME, GFP_KERNEL); + return; + + nla_put_failure: + nlmsg_free(msg); +} +EXPORT_SYMBOL(cfg80211_links_removed); + void nl80211_send_ibss_bssid(struct cfg80211_registered_device *rdev, struct net_device *netdev, const u8 *bssid, gfp_t gfp) @@ -18960,9 +19129,8 @@ enum nl80211_cqm_rssi_threshold_event rssi_event, s32 rssi_level, gfp_t gfp) { - struct sk_buff *msg; struct wireless_dev *wdev = dev->ieee80211_ptr; - struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); + struct cfg80211_cqm_config *cqm_config; trace_cfg80211_cqm_rssi_notify(dev, rssi_event, rssi_level); @@ -18970,16 +19138,37 @@ rssi_event != NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH)) return; - if (wdev->cqm_config) { - wdev->cqm_config->last_rssi_event_value = rssi_level; + rcu_read_lock(); + cqm_config = rcu_dereference(wdev->cqm_config); + if (cqm_config) { + cqm_config->last_rssi_event_value = rssi_level; + cqm_config->last_rssi_event_type = rssi_event; + wiphy_work_queue(wdev->wiphy, &wdev->cqm_rssi_work); + } + rcu_read_unlock(); +} +EXPORT_SYMBOL(cfg80211_cqm_rssi_notify); - cfg80211_cqm_rssi_update(rdev, dev); +void cfg80211_cqm_rssi_notify_work(struct wiphy *wiphy, struct wiphy_work *work) +{ + struct wireless_dev *wdev = container_of(work, struct wireless_dev, + cqm_rssi_work); + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + enum nl80211_cqm_rssi_threshold_event rssi_event; + struct cfg80211_cqm_config *cqm_config; + struct sk_buff *msg; + s32 rssi_level; - if (rssi_level == 0) - rssi_level = wdev->cqm_config->last_rssi_event_value; - } + cqm_config = wiphy_dereference(wdev->wiphy, wdev->cqm_config); + if (!wdev->cqm_config) + return; - msg = cfg80211_prepare_cqm(dev, NULL, gfp); + cfg80211_cqm_rssi_update(rdev, wdev->netdev, cqm_config); + + rssi_level = cqm_config->last_rssi_event_value; + rssi_event = cqm_config->last_rssi_event_type; + + msg = cfg80211_prepare_cqm(wdev->netdev, NULL, GFP_KERNEL); if (!msg) return; @@ -18991,14 +19180,13 @@ rssi_level)) goto nla_put_failure; - cfg80211_send_cqm(msg, gfp); + cfg80211_send_cqm(msg, GFP_KERNEL); return; nla_put_failure: nlmsg_free(msg); } -EXPORT_SYMBOL(cfg80211_cqm_rssi_notify); void cfg80211_cqm_txe_notify(struct net_device *dev, const u8 *peer, u32 num_packets, @@ -19241,7 +19429,7 @@ struct wiphy *wiphy = wdev->wiphy; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); WARN_INVALID_LINK_ID(wdev, link_id); trace_cfg80211_ch_switch_notify(dev, chandef, link_id, punct_bitmap); @@ -19286,7 +19474,7 @@ struct wiphy *wiphy = wdev->wiphy; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); WARN_INVALID_LINK_ID(wdev, link_id); trace_cfg80211_ch_switch_started_notify(dev, chandef, link_id, @@ -19309,7 +19497,7 @@ struct sk_buff *msg; void *hdr; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); trace_cfg80211_bss_color_notify(dev, cmd, count, color_bitmap); @@ -19774,7 +19962,8 @@ list) { if (sched_scan_req->owner_nlportid == notify->portid) { sched_scan_req->nl_owner_dead = true; - schedule_work(&rdev->sched_scan_stop_wk); + wiphy_work_queue(&rdev->wiphy, + &rdev->sched_scan_stop_wk); } } diff -ruw linux-6.4/net/wireless/nl80211.h linux-6.4-fbx/net/wireless/nl80211.h --- linux-6.4/net/wireless/nl80211.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/nl80211.h 2023-11-07 13:38:44.110258003 +0100 @@ -60,7 +60,7 @@ const u8 *buf, size_t len, gfp_t gfp); void nl80211_send_rx_assoc(struct cfg80211_registered_device *rdev, struct net_device *netdev, - struct cfg80211_rx_assoc_resp *data); + struct cfg80211_rx_assoc_resp_data *data); void nl80211_send_deauth(struct cfg80211_registered_device *rdev, struct net_device *netdev, const u8 *buf, size_t len, @@ -82,8 +82,11 @@ void nl80211_send_roamed(struct cfg80211_registered_device *rdev, struct net_device *netdev, struct cfg80211_roam_info *info, gfp_t gfp); +/* For STA/GC, indicate port authorized with AP/GO bssid. + * For GO/AP, use peer GC/STA mac_addr. + */ void nl80211_send_port_authorized(struct cfg80211_registered_device *rdev, - struct net_device *netdev, const u8 *bssid, + struct net_device *netdev, const u8 *peer_addr, const u8 *td_bitmap, u8 td_bitmap_len); void nl80211_send_disconnected(struct cfg80211_registered_device *rdev, struct net_device *netdev, u16 reason, @@ -120,6 +123,5 @@ /* peer measurement */ int nl80211_pmsr_start(struct sk_buff *skb, struct genl_info *info); -int nl80211_pmsr_dump_results(struct sk_buff *skb, struct netlink_callback *cb); #endif /* __NET_WIRELESS_NL80211_H */ diff -ruw linux-6.4/net/wireless/ocb.c linux-6.4-fbx/net/wireless/ocb.c --- linux-6.4/net/wireless/ocb.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/ocb.c 2023-11-07 13:38:44.110258003 +0100 @@ -4,7 +4,7 @@ * * Copyright: (c) 2014 Czech Technical University in Prague * (c) 2014 Volkswagen Group Research - * Copyright (C) 2022 Intel Corporation + * Copyright (C) 2022-2023 Intel Corporation * Author: Rostislav Lisovy * Funded by: Volkswagen Group Research */ @@ -15,14 +15,14 @@ #include "core.h" #include "rdev-ops.h" -int __cfg80211_join_ocb(struct cfg80211_registered_device *rdev, +int cfg80211_join_ocb(struct cfg80211_registered_device *rdev, struct net_device *dev, struct ocb_setup *setup) { struct wireless_dev *wdev = dev->ieee80211_ptr; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_OCB) return -EOPNOTSUPP; @@ -40,27 +40,13 @@ return err; } -int cfg80211_join_ocb(struct cfg80211_registered_device *rdev, - struct net_device *dev, - struct ocb_setup *setup) -{ - struct wireless_dev *wdev = dev->ieee80211_ptr; - int err; - - wdev_lock(wdev); - err = __cfg80211_join_ocb(rdev, dev, setup); - wdev_unlock(wdev); - - return err; -} - -int __cfg80211_leave_ocb(struct cfg80211_registered_device *rdev, +int cfg80211_leave_ocb(struct cfg80211_registered_device *rdev, struct net_device *dev) { struct wireless_dev *wdev = dev->ieee80211_ptr; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_OCB) return -EOPNOTSUPP; @@ -68,22 +54,12 @@ if (!rdev->ops->leave_ocb) return -EOPNOTSUPP; + if (!wdev->u.ocb.chandef.chan) + return -ENOTCONN; + err = rdev_leave_ocb(rdev, dev); if (!err) memset(&wdev->u.ocb.chandef, 0, sizeof(wdev->u.ocb.chandef)); return err; } - -int cfg80211_leave_ocb(struct cfg80211_registered_device *rdev, - struct net_device *dev) -{ - struct wireless_dev *wdev = dev->ieee80211_ptr; - int err; - - wdev_lock(wdev); - err = __cfg80211_leave_ocb(rdev, dev); - wdev_unlock(wdev); - - return err; -} diff -ruw linux-6.4/net/wireless/pmsr.c linux-6.4-fbx/net/wireless/pmsr.c --- linux-6.4/net/wireless/pmsr.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/pmsr.c 2023-11-07 13:38:44.110258003 +0100 @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2018 - 2021 Intel Corporation + * Copyright (C) 2018 - 2021, 2023 Intel Corporation */ #include #include "core.h" @@ -291,6 +291,7 @@ req = kzalloc(struct_size(req, peers, count), GFP_KERNEL); if (!req) return -ENOMEM; + req->n_peers = count; if (info->attrs[NL80211_ATTR_TIMEOUT]) req->timeout = nla_get_u32(info->attrs[NL80211_ATTR_TIMEOUT]); @@ -321,8 +322,6 @@ goto out_err; idx++; } - - req->n_peers = count; req->cookie = cfg80211_assign_cookie(rdev); req->nl_portid = info->snd_portid; @@ -601,7 +600,7 @@ struct cfg80211_pmsr_request *req, *tmp; LIST_HEAD(free_list); - lockdep_assert_held(&wdev->mtx); + lockdep_assert_wiphy(wdev->wiphy); spin_lock_bh(&wdev->pmsr_lock); list_for_each_entry_safe(req, tmp, &wdev->pmsr_list, list) { @@ -623,9 +622,9 @@ struct wireless_dev *wdev = container_of(work, struct wireless_dev, pmsr_free_wk); - wdev_lock(wdev); + wiphy_lock(wdev->wiphy); cfg80211_pmsr_process_abort(wdev); - wdev_unlock(wdev); + wiphy_unlock(wdev->wiphy); } void cfg80211_pmsr_wdev_down(struct wireless_dev *wdev) diff -ruw linux-6.4/net/wireless/rdev-ops.h linux-6.4-fbx/net/wireless/rdev-ops.h --- linux-6.4/net/wireless/rdev-ops.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/rdev-ops.h 2023-11-07 13:38:44.110258003 +0100 @@ -173,7 +173,7 @@ static inline int rdev_change_beacon(struct cfg80211_registered_device *rdev, struct net_device *dev, - struct cfg80211_beacon_data *info) + struct cfg80211_ap_update *info) { int ret; trace_rdev_change_beacon(&rdev->wiphy, dev, info); @@ -407,6 +407,18 @@ return ret; } +static inline void rdev_inform_bss(struct cfg80211_registered_device *rdev, + struct cfg80211_bss *bss, + const struct cfg80211_bss_ies *ies, + void *drv_data) + +{ + trace_rdev_inform_bss(&rdev->wiphy, bss); + if (rdev->ops->inform_bss) + rdev->ops->inform_bss(&rdev->wiphy, bss, ies, drv_data); + trace_rdev_return_void(&rdev->wiphy); +} + static inline int rdev_set_txq_params(struct cfg80211_registered_device *rdev, struct net_device *dev, struct ieee80211_txq_params *params) @@ -899,17 +911,18 @@ static inline int rdev_tdls_mgmt(struct cfg80211_registered_device *rdev, struct net_device *dev, u8 *peer, - u8 action_code, u8 dialog_token, - u16 status_code, u32 peer_capability, - bool initiator, const u8 *buf, size_t len) + int link_id, u8 action_code, + u8 dialog_token, u16 status_code, + u32 peer_capability, bool initiator, + const u8 *buf, size_t len) { int ret; - trace_rdev_tdls_mgmt(&rdev->wiphy, dev, peer, action_code, - dialog_token, status_code, peer_capability, - initiator, buf, len); - ret = rdev->ops->tdls_mgmt(&rdev->wiphy, dev, peer, action_code, + trace_rdev_tdls_mgmt(&rdev->wiphy, dev, peer, link_id, action_code, dialog_token, status_code, peer_capability, initiator, buf, len); + ret = rdev->ops->tdls_mgmt(&rdev->wiphy, dev, peer, link_id, + action_code, dialog_token, status_code, + peer_capability, initiator, buf, len); trace_rdev_return_int(&rdev->wiphy, ret); return ret; } diff -ruw linux-6.4/net/wireless/reg.c linux-6.4-fbx/net/wireless/reg.c --- linux-6.4/net/wireless/reg.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/reg.c 2024-02-14 17:43:53.027128018 +0100 @@ -5,7 +5,7 @@ * Copyright 2008-2011 Luis R. Rodriguez * Copyright 2013-2014 Intel Mobile Communications GmbH * Copyright 2017 Intel Deutschland GmbH - * Copyright (C) 2018 - 2022 Intel Corporation + * Copyright (C) 2018 - 2023 Intel Corporation * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -1283,7 +1283,9 @@ * 60 GHz band. * This resolution can be lowered and should be considered as we add * regulatory rule support for other "bands". - **/ + * + * Returns: whether or not the frequency is in the range + */ static bool freq_in_rule_band(const struct ieee80211_freq_range *freq_range, u32 freq_khz) { @@ -1492,6 +1494,8 @@ * Returns a pointer to the regulatory domain structure which will hold the * resulting intersection of rules between rd1 and rd2. We will * kzalloc() this structure for you. + * + * Returns: the intersected regdomain */ static struct ieee80211_regdomain * regdom_intersect(const struct ieee80211_regdomain *rd1, @@ -1587,6 +1591,10 @@ channel_flags |= IEEE80211_CHAN_NO_HE; if (rd_flags & NL80211_RRF_NO_320MHZ) channel_flags |= IEEE80211_CHAN_NO_320MHZ; + if (rd_flags & NL80211_RRF_NO_EHT) + channel_flags |= IEEE80211_CHAN_NO_EHT; + if (rd_flags & NL80211_RRF_PSD) + channel_flags |= IEEE80211_CHAN_PSD; return channel_flags; } @@ -1755,6 +1763,40 @@ return bw_flags; } +static void restore_channel_dfs_cached_state(struct wiphy *wiphy, + struct ieee80211_channel *c) +{ + struct cfg80211_chan_dfs_cache *cd; + unsigned long timeout; + + if (!IS_ENABLED(CONFIG_CFG80211_DFS_CACHE)) + return; + + cd = cfg80211_get_dfs_chan_cache(c); + if (!cd) + return; + + if (cd->dfs_state == NL80211_DFS_USABLE) + return; + + if (cd->dfs_state == NL80211_DFS_UNAVAILABLE) { + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + + timeout = cd->dfs_state_entered + + msecs_to_jiffies(IEEE80211_DFS_MIN_NOP_TIME_MS); + + if (time_after_eq(jiffies, timeout)) + return; + + cfg80211_sched_dfs_chan_update(rdev); + } + + wiphy_info(wiphy, "restoring channel %u DFS state from cache\n", + cd->center_freq); + c->dfs_state = cd->dfs_state; + c->dfs_state_entered = cd->dfs_state_entered; +} + static void handle_channel_single_rule(struct wiphy *wiphy, enum nl80211_reg_initiator initiator, struct ieee80211_channel *chan, @@ -1789,15 +1831,22 @@ if (chan->flags & IEEE80211_CHAN_RADAR) { chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS; + if (chan->center_freq >= 5600 && + chan->center_freq <= 5650) + chan->dfs_cac_ms = IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS; if (reg_rule->dfs_cac_ms) chan->dfs_cac_ms = reg_rule->dfs_cac_ms; } + if (chan->flags & IEEE80211_CHAN_PSD) + chan->psd = reg_rule->psd; + return; } chan->dfs_state = NL80211_DFS_USABLE; chan->dfs_state_entered = jiffies; + restore_channel_dfs_cached_state(wiphy, chan); chan->beacon_found = false; chan->flags = flags | bw_flags | map_regdom_flags(reg_rule->flags); @@ -1809,9 +1858,17 @@ if (chan->flags & IEEE80211_CHAN_RADAR) { if (reg_rule->dfs_cac_ms) chan->dfs_cac_ms = reg_rule->dfs_cac_ms; + else { + if (chan->center_freq >= 5600 && + chan->center_freq <= 5650) + chan->dfs_cac_ms = IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS; else chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS; } + } + + if (chan->flags & IEEE80211_CHAN_PSD) + chan->psd = reg_rule->psd; if (chan->orig_mpwr) { /* @@ -1882,11 +1939,18 @@ rrule2->dfs_cac_ms); } + if ((rrule1->flags & NL80211_RRF_PSD) && + (rrule2->flags & NL80211_RRF_PSD)) + chan->psd = min_t(s8, rrule1->psd, rrule2->psd); + else + chan->flags &= ~NL80211_RRF_PSD; + return; } chan->dfs_state = NL80211_DFS_USABLE; chan->dfs_state_entered = jiffies; + restore_channel_dfs_cached_state(wiphy, chan); chan->beacon_found = false; chan->flags = flags | bw_flags1 | bw_flags2 | @@ -2149,6 +2213,13 @@ return false; } +static void reg_call_notifier(struct wiphy *wiphy, + struct regulatory_request *request) +{ + if (wiphy->reg_notifier) + wiphy->reg_notifier(wiphy, request); +} + static void handle_reg_beacon(struct wiphy *wiphy, unsigned int chan_idx, struct reg_beacon *reg_beacon) { @@ -2156,6 +2227,7 @@ struct ieee80211_channel *chan; bool channel_changed = false; struct ieee80211_channel chan_before; + struct regulatory_request *lr = get_last_request(); sband = wiphy->bands[reg_beacon->chan.band]; chan = &sband->channels[chan_idx]; @@ -2181,8 +2253,11 @@ channel_changed = true; } - if (channel_changed) + if (channel_changed) { nl80211_send_beacon_hint_event(wiphy, &chan_before, chan); + if (wiphy->flags & WIPHY_FLAG_CHANNEL_CHANGE_ON_BEACON) + reg_call_notifier(wiphy, lr); + } } /* @@ -2325,13 +2400,6 @@ reg_process_ht_flags_band(wiphy, wiphy->bands[band]); } -static void reg_call_notifier(struct wiphy *wiphy, - struct regulatory_request *request) -{ - if (wiphy->reg_notifier) - wiphy->reg_notifier(wiphy, request); -} - static bool reg_wdev_chan_valid(struct wiphy *wiphy, struct wireless_dev *wdev) { struct cfg80211_chan_def chandef = {}; @@ -2340,19 +2408,18 @@ bool ret; int link; - wdev_lock(wdev); iftype = wdev->iftype; /* make sure the interface is active */ if (!wdev->netdev || !netif_running(wdev->netdev)) - goto wdev_inactive_unlock; + return true; for (link = 0; link < ARRAY_SIZE(wdev->links); link++) { struct ieee80211_channel *chan; if (!wdev->valid_links && link > 0) break; - if (!(wdev->valid_links & BIT(link))) + if (wdev->valid_links && !(wdev->valid_links & BIT(link))) continue; switch (iftype) { case NL80211_IFTYPE_AP: @@ -2391,14 +2458,20 @@ case NL80211_IFTYPE_P2P_DEVICE: /* no enforcement required */ break; + case NL80211_IFTYPE_OCB: + if (!wdev->u.ocb.chandef.chan) + continue; + chandef = wdev->u.ocb.chandef; + break; + case NL80211_IFTYPE_NAN: + /* we have no info, but NAN is also pretty universal */ + continue; default: /* others not implemented for now */ - WARN_ON(1); + WARN_ON_ONCE(1); break; } - wdev_unlock(wdev); - switch (iftype) { case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: @@ -2419,16 +2492,8 @@ default: break; } - - wdev_lock(wdev); } - wdev_unlock(wdev); - - return true; - -wdev_inactive_unlock: - wdev_unlock(wdev); return true; } @@ -2451,9 +2516,7 @@ pr_debug("Verifying active interfaces after reg change\n"); rtnl_lock(); - list_for_each_entry(rdev, &cfg80211_rdev_list, list) - if (!(rdev->wiphy.regulatory_flags & - REGULATORY_IGNORE_STALE_KICKOFF)) + for_each_rdev(rdev) reg_leave_invalid_chans(&rdev->wiphy); rtnl_unlock(); @@ -2507,7 +2570,7 @@ ASSERT_RTNL(); - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { wiphy = &rdev->wiphy; wiphy_update_regulatory(wiphy, initiator); } @@ -2549,6 +2612,7 @@ chan->dfs_state_entered = jiffies; chan->dfs_state = NL80211_DFS_USABLE; + restore_channel_dfs_cached_state(wiphy, chan); chan->beacon_found = false; @@ -2569,6 +2633,9 @@ chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS; } + if (chan->flags & IEEE80211_CHAN_PSD) + chan->psd = reg_rule->psd; + chan->max_power = chan->max_reg_power; } @@ -2655,6 +2722,9 @@ * * The wireless subsystem can use this function to process * a regulatory request issued by the regulatory core. + * + * Returns: %REG_REQ_OK or %REG_REQ_IGNORE, indicating if the + * hint was processed or ignored */ static enum reg_request_treatment reg_process_hint_core(struct regulatory_request *core_request) @@ -2711,6 +2781,9 @@ * * The wireless subsystem can use this function to process * a regulatory request initiated by userspace. + * + * Returns: %REG_REQ_OK or %REG_REQ_IGNORE, indicating if the + * hint was processed or ignored */ static enum reg_request_treatment reg_process_hint_user(struct regulatory_request *user_request) @@ -2766,7 +2839,7 @@ * The wireless subsystem can use this function to process * a regulatory request issued by an 802.11 driver. * - * Returns one of the different reg request treatment values. + * Returns: one of the different reg request treatment values. */ static enum reg_request_treatment reg_process_hint_driver(struct wiphy *wiphy, @@ -2870,7 +2943,7 @@ * The wireless subsystem can use this function to process * a regulatory request issued by a country Information Element. * - * Returns one of the different reg request treatment values. + * Returns: one of the different reg request treatment values. */ static enum reg_request_treatment reg_process_hint_country_ie(struct wiphy *wiphy, @@ -2983,7 +3056,7 @@ ASSERT_RTNL(); - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { if (wiphy == &rdev->wiphy) continue; wiphy_share_dfs_chan_state(wiphy, &rdev->wiphy); @@ -3049,7 +3122,7 @@ struct cfg80211_registered_device *rdev; struct wiphy *wiphy; - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { wiphy = &rdev->wiphy; if (wiphy->regulatory_flags & REGULATORY_WIPHY_SELF_MANAGED && request->initiator == NL80211_REGDOM_SET_BY_USER) @@ -3114,7 +3187,7 @@ list_del_init(&pending_beacon->list); /* Applies the beacon hint to current wiphys */ - list_for_each_entry(rdev, &cfg80211_rdev_list, list) + for_each_rdev(rdev) wiphy_update_new_beacon(&rdev->wiphy, pending_beacon); /* Remembers the beacon hint for new wiphys or reg changes */ @@ -3169,7 +3242,7 @@ ASSERT_RTNL(); - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { wiphy_lock(&rdev->wiphy); reg_process_self_managed_hint(&rdev->wiphy); wiphy_unlock(&rdev->wiphy); @@ -3509,7 +3582,7 @@ world_alpha2[0] = cfg80211_world_regdom->alpha2[0]; world_alpha2[1] = cfg80211_world_regdom->alpha2[1]; - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { if (rdev->wiphy.regulatory_flags & REGULATORY_WIPHY_SELF_MANAGED) continue; if (rdev->wiphy.regulatory_flags & REGULATORY_CUSTOM_REG) @@ -3566,15 +3639,15 @@ struct cfg80211_registered_device *rdev; struct wireless_dev *wdev; - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { + wiphy_lock(&rdev->wiphy); list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { - wdev_lock(wdev); if (!(wdev->wiphy->regulatory_flags & flag)) { - wdev_unlock(wdev); + wiphy_unlock(&rdev->wiphy); return false; } - wdev_unlock(wdev); } + wiphy_unlock(&rdev->wiphy); } return true; @@ -3830,7 +3903,7 @@ { const struct ieee80211_regdomain *regd; const struct ieee80211_regdomain *intersected_rd = NULL; - const struct ieee80211_regdomain *tmp; + const struct ieee80211_regdomain *tmp = NULL; struct wiphy *request_wiphy; if (is_world_regdom(rd->alpha2)) @@ -3853,10 +3926,8 @@ if (!driver_request->intersect) { ASSERT_RTNL(); wiphy_lock(request_wiphy); - if (request_wiphy->regd) { - wiphy_unlock(request_wiphy); - return -EALREADY; - } + if (request_wiphy->regd) + tmp = get_wiphy_regdom(request_wiphy); regd = reg_copy_regd(rd); if (IS_ERR(regd)) { @@ -3865,6 +3936,7 @@ } rcu_assign_pointer(request_wiphy->regd, regd); + rcu_free_regdom(tmp); wiphy_unlock(request_wiphy); reset_regdomains(false, rd); return 0; @@ -4236,7 +4308,7 @@ if (WARN_ON(!cfg80211_chandef_valid(chandef))) return; - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { if (wiphy == &rdev->wiphy) continue; diff -ruw linux-6.4/net/wireless/reg.h linux-6.4-fbx/net/wireless/reg.h --- linux-6.4/net/wireless/reg.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/reg.h 2023-11-07 13:38:44.110258003 +0100 @@ -5,7 +5,7 @@ /* * Copyright 2008-2011 Luis R. Rodriguez - * Copyright (C) 2019 Intel Corporation + * Copyright (C) 2019, 2023 Intel Corporation * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -133,7 +133,7 @@ /** * cfg80211_get_unii - get the U-NII band for the frequency * @freq: the frequency for which we want to get the UNII band. - + * * Get a value specifying the U-NII band frequency belongs to. * U-NII bands are defined by the FCC in C.F.R 47 part 15. * @@ -156,11 +156,11 @@ /** * regulatory_propagate_dfs_state - Propagate DFS channel state to other wiphys - * @wiphy - wiphy on which radar is detected and the event will be propagated + * @wiphy: wiphy on which radar is detected and the event will be propagated * to other available wiphys having the same DFS domain - * @chandef - Channel definition of radar detected channel - * @dfs_state - DFS channel state to be set - * @event - Type of radar event which triggered this DFS state change + * @chandef: Channel definition of radar detected channel + * @dfs_state: DFS channel state to be set + * @event: Type of radar event which triggered this DFS state change * * This function should be called with rtnl lock held. */ @@ -171,8 +171,8 @@ /** * reg_dfs_domain_same - Checks if both wiphy have same DFS domain configured - * @wiphy1 - wiphy it's dfs_region to be checked against that of wiphy2 - * @wiphy2 - wiphy it's dfs_region to be checked against that of wiphy1 + * @wiphy1: wiphy it's dfs_region to be checked against that of wiphy2 + * @wiphy2: wiphy it's dfs_region to be checked against that of wiphy1 */ bool reg_dfs_domain_same(struct wiphy *wiphy1, struct wiphy *wiphy2); diff -ruw linux-6.4/net/wireless/scan.c linux-6.4-fbx/net/wireless/scan.c --- linux-6.4/net/wireless/scan.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/scan.c 2024-02-14 17:43:53.027128018 +0100 @@ -96,6 +96,7 @@ * colocated and can be discovered via legacy bands. * @short_ssid_valid: short_ssid is valid and can be used * @short_ssid: the short SSID for this SSID + * @psd_20: The 20MHz PSD EIRP of the primary 20MHz channel for the reported AP */ struct cfg80211_colocated_ap { struct list_head list; @@ -111,6 +112,7 @@ transmitted_bssid:1, colocated_ess:1, short_ssid_valid:1; + s8 psd_20; }; static void bss_free(struct cfg80211_internal_bss *bss) @@ -218,6 +220,10 @@ if (elem->id == WLAN_EID_MULTIPLE_BSSID) return false; + if (elem->id == WLAN_EID_EXTENSION && elem->datalen > 1 && + elem->data[0] == WLAN_EID_EXT_EHT_MULTI_LINK) + return false; + if (!non_inherit_elem || non_inherit_elem->datalen < 2) return true; @@ -259,117 +265,152 @@ } EXPORT_SYMBOL(cfg80211_is_element_inherited); -static size_t cfg80211_gen_new_ie(const u8 *ie, size_t ielen, - const u8 *subelement, size_t subie_len, - u8 *new_ie, gfp_t gfp) +static size_t cfg80211_copy_elem_with_frags(const struct element *elem, + const u8 *ie, size_t ie_len, + u8 **pos, u8 *buf, size_t buf_len) { - u8 *pos, *tmp; - const u8 *tmp_old, *tmp_new; - const struct element *non_inherit_elem; - u8 *sub_copy; - - /* copy subelement as we need to change its content to - * mark an ie after it is processed. - */ - sub_copy = kmemdup(subelement, subie_len, gfp); - if (!sub_copy) + if (WARN_ON((u8 *)elem < ie || elem->data > ie + ie_len || + elem->data + elem->datalen > ie + ie_len)) return 0; - pos = &new_ie[0]; + if (elem->datalen + 2 > buf + buf_len - *pos) + return 0; - /* set new ssid */ - tmp_new = cfg80211_find_ie(WLAN_EID_SSID, sub_copy, subie_len); - if (tmp_new) { - memcpy(pos, tmp_new, tmp_new[1] + 2); - pos += (tmp_new[1] + 2); - } + memcpy(*pos, elem, elem->datalen + 2); + *pos += elem->datalen + 2; - /* get non inheritance list if exists */ - non_inherit_elem = - cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, - sub_copy, subie_len); + /* Finish if it is not fragmented */ + if (elem->datalen != 255) + return *pos - buf; - /* go through IEs in ie (skip SSID) and subelement, - * merge them into new_ie - */ - tmp_old = cfg80211_find_ie(WLAN_EID_SSID, ie, ielen); - tmp_old = (tmp_old) ? tmp_old + tmp_old[1] + 2 : ie; + ie_len = ie + ie_len - elem->data - elem->datalen; + ie = (const u8 *)elem->data + elem->datalen; - while (tmp_old + 2 - ie <= ielen && - tmp_old + tmp_old[1] + 2 - ie <= ielen) { - if (tmp_old[0] == 0) { - tmp_old++; - continue; - } + for_each_element(elem, ie, ie_len) { + if (elem->id != WLAN_EID_FRAGMENT) + break; - if (tmp_old[0] == WLAN_EID_EXTENSION) - tmp = (u8 *)cfg80211_find_ext_ie(tmp_old[2], sub_copy, - subie_len); - else - tmp = (u8 *)cfg80211_find_ie(tmp_old[0], sub_copy, - subie_len); + if (elem->datalen + 2 > buf + buf_len - *pos) + return 0; - if (!tmp) { - const struct element *old_elem = (void *)tmp_old; + memcpy(*pos, elem, elem->datalen + 2); + *pos += elem->datalen + 2; - /* ie in old ie but not in subelement */ - if (cfg80211_is_element_inherited(old_elem, - non_inherit_elem)) { - memcpy(pos, tmp_old, tmp_old[1] + 2); - pos += tmp_old[1] + 2; + if (elem->datalen != 255) + break; } - } else { - /* ie in transmitting ie also in subelement, - * copy from subelement and flag the ie in subelement - * as copied (by setting eid field to WLAN_EID_SSID, - * which is skipped anyway). - * For vendor ie, compare OUI + type + subType to - * determine if they are the same ie. - */ - if (tmp_old[0] == WLAN_EID_VENDOR_SPECIFIC) { - if (tmp_old[1] >= 5 && tmp[1] >= 5 && - !memcmp(tmp_old + 2, tmp + 2, 5)) { - /* same vendor ie, copy from - * subelement - */ - memcpy(pos, tmp, tmp[1] + 2); - pos += tmp[1] + 2; - tmp[0] = WLAN_EID_SSID; - } else { - memcpy(pos, tmp_old, tmp_old[1] + 2); - pos += tmp_old[1] + 2; + + return *pos - buf; } + +static size_t cfg80211_gen_new_ie(const u8 *ie, size_t ielen, + const u8 *subie, size_t subie_len, + u8 *new_ie, size_t new_ie_len) +{ + const struct element *non_inherit_elem, *parent, *sub; + u8 *pos = new_ie; + u8 id, ext_id; + unsigned int match_len; + + non_inherit_elem = cfg80211_find_ext_elem(WLAN_EID_EXT_NON_INHERITANCE, + subie, subie_len); + + /* We copy the elements one by one from the parent to the generated + * elements. + * If they are not inherited (included in subie or in the non + * inheritance element), then we copy all occurrences the first time + * we see this element type. + */ + for_each_element(parent, ie, ielen) { + if (parent->id == WLAN_EID_FRAGMENT) + continue; + + if (parent->id == WLAN_EID_EXTENSION) { + if (parent->datalen < 1) + continue; + + id = WLAN_EID_EXTENSION; + ext_id = parent->data[0]; + match_len = 1; } else { - /* copy ie from subelement into new ie */ - memcpy(pos, tmp, tmp[1] + 2); - pos += tmp[1] + 2; - tmp[0] = WLAN_EID_SSID; + id = parent->id; + match_len = 0; } + + /* Find first occurrence in subie */ + sub = cfg80211_find_elem_match(id, subie, subie_len, + &ext_id, match_len, 0); + + /* Copy from parent if not in subie and inherited */ + if (!sub && + cfg80211_is_element_inherited(parent, non_inherit_elem)) { + if (!cfg80211_copy_elem_with_frags(parent, + ie, ielen, + &pos, new_ie, + new_ie_len)) + return 0; + + continue; } - if (tmp_old + tmp_old[1] + 2 - ie == ielen) - break; + /* Already copied if an earlier element had the same type */ + if (cfg80211_find_elem_match(id, ie, (u8 *)parent - ie, + &ext_id, match_len, 0)) + continue; + + /* Not inheriting, copy all similar elements from subie */ + while (sub) { + if (!cfg80211_copy_elem_with_frags(sub, + subie, subie_len, + &pos, new_ie, + new_ie_len)) + return 0; - tmp_old += tmp_old[1] + 2; + sub = cfg80211_find_elem_match(id, + sub->data + sub->datalen, + subie_len + subie - + (sub->data + + sub->datalen), + &ext_id, match_len, 0); + } } - /* go through subelement again to check if there is any ie not - * copied to new ie, skip ssid, capability, bssid-index ie + /* The above misses elements that are included in subie but not in the + * parent, so do a pass over subie and append those. + * Skip the non-tx BSSID caps and non-inheritance element. */ - tmp_new = sub_copy; - while (tmp_new + 2 - sub_copy <= subie_len && - tmp_new + tmp_new[1] + 2 - sub_copy <= subie_len) { - if (!(tmp_new[0] == WLAN_EID_NON_TX_BSSID_CAP || - tmp_new[0] == WLAN_EID_SSID)) { - memcpy(pos, tmp_new, tmp_new[1] + 2); - pos += tmp_new[1] + 2; + for_each_element(sub, subie, subie_len) { + if (sub->id == WLAN_EID_NON_TX_BSSID_CAP) + continue; + + if (sub->id == WLAN_EID_FRAGMENT) + continue; + + if (sub->id == WLAN_EID_EXTENSION) { + if (sub->datalen < 1) + continue; + + id = WLAN_EID_EXTENSION; + ext_id = sub->data[0]; + match_len = 1; + + if (ext_id == WLAN_EID_EXT_NON_INHERITANCE) + continue; + } else { + id = sub->id; + match_len = 0; } - if (tmp_new + tmp_new[1] + 2 - sub_copy == subie_len) - break; - tmp_new += tmp_new[1] + 2; + + /* Processed if one was included in the parent */ + if (cfg80211_find_elem_match(id, ie, ielen, + &ext_id, match_len, 0)) + continue; + + if (!cfg80211_copy_elem_with_frags(sub, subie, subie_len, + &pos, new_ie, new_ie_len)) + return 0; } - kfree(sub_copy); return pos - new_ie; } @@ -535,39 +576,58 @@ static int cfg80211_parse_ap_info(struct cfg80211_colocated_ap *entry, const u8 *pos, u8 length, const struct element *ssid_elem, - int s_ssid_tmp) + u32 s_ssid_tmp) { - /* skip the TBTT offset */ - pos++; + u8 bss_params; - /* ignore entries with invalid BSSID */ - if (!is_valid_ether_addr(pos)) - return -EINVAL; + entry->psd_20 = IEEE80211_RNR_TBTT_PARAMS_PSD_RESERVED; - memcpy(entry->bssid, pos, ETH_ALEN); - pos += ETH_ALEN; + /* The length is already verified by the caller to contain bss_params */ + if (length > sizeof(struct ieee80211_tbtt_info_7_8_9)) { + struct ieee80211_tbtt_info_ge_11 *tbtt_info = (void *)pos; - if (length >= IEEE80211_TBTT_INFO_OFFSET_BSSID_SSSID_BSS_PARAM) { - memcpy(&entry->short_ssid, pos, - sizeof(entry->short_ssid)); + memcpy(entry->bssid, tbtt_info->bssid, ETH_ALEN); + entry->short_ssid = le32_to_cpu(tbtt_info->short_ssid); entry->short_ssid_valid = true; - pos += 4; + + bss_params = tbtt_info->bss_params; + + /* Ignore disabled links */ + if (length >= offsetofend(typeof(*tbtt_info), mld_params)) { + if (le16_get_bits(tbtt_info->mld_params.params, + IEEE80211_RNR_MLD_PARAMS_DISABLED_LINK)) + return -EINVAL; + } + + if (length >= offsetofend(struct ieee80211_tbtt_info_ge_11, + psd_20)) + entry->psd_20 = tbtt_info->psd_20; + } else { + struct ieee80211_tbtt_info_7_8_9 *tbtt_info = (void *)pos; + + memcpy(entry->bssid, tbtt_info->bssid, ETH_ALEN); + + bss_params = tbtt_info->bss_params; + + if (length == offsetofend(struct ieee80211_tbtt_info_7_8_9, + psd_20)) + entry->psd_20 = tbtt_info->psd_20; } + /* ignore entries with invalid BSSID */ + if (!is_valid_ether_addr(entry->bssid)) + return -EINVAL; + /* skip non colocated APs */ - if (!cfg80211_parse_bss_param(*pos, entry)) + if (!cfg80211_parse_bss_param(bss_params, entry)) return -EINVAL; - pos++; - if (length == IEEE80211_TBTT_INFO_OFFSET_BSSID_BSS_PARAM) { - /* - * no information about the short ssid. Consider the entry valid + /* no information about the short ssid. Consider the entry valid * for now. It would later be dropped in case there are explicit * SSIDs that need to be matched */ - if (!entry->same_ssid) + if (!entry->same_ssid && !entry->short_ssid_valid) return 0; - } if (entry->same_ssid) { entry->short_ssid = s_ssid_tmp; @@ -578,10 +638,10 @@ * cfg80211_parse_colocated_ap(), before calling this * function. */ - memcpy(&entry->ssid, &ssid_elem->data, - ssid_elem->datalen); + memcpy(&entry->ssid, &ssid_elem->data, ssid_elem->datalen); entry->ssid_len = ssid_elem->datalen; } + return 0; } @@ -595,17 +655,14 @@ int n_coloc = 0, ret; LIST_HEAD(ap_list); - elem = cfg80211_find_elem(WLAN_EID_REDUCED_NEIGHBOR_REPORT, ies->data, - ies->len); - if (!elem) + ret = cfg80211_calc_short_ssid(ies, &ssid_elem, &s_ssid_tmp); + if (ret) return 0; + for_each_element_id(elem, WLAN_EID_REDUCED_NEIGHBOR_REPORT, + ies->data, ies->len) { pos = elem->data; - end = pos + elem->datalen; - - ret = cfg80211_calc_short_ssid(ies, &ssid_elem, &s_ssid_tmp); - if (ret) - return ret; + end = elem->data + elem->datalen; /* RNR IE may contain more than one NEIGHBOR_AP_INFO */ while (pos + sizeof(*ap_info) <= end) { @@ -624,20 +681,30 @@ &band)) break; - freq = ieee80211_channel_to_frequency(ap_info->channel, band); + freq = ieee80211_channel_to_frequency(ap_info->channel, + band); if (end - pos < count * length) break; - /* - * TBTT info must include bss param + BSSID + + if (u8_get_bits(ap_info->tbtt_info_hdr, + IEEE80211_AP_INFO_TBTT_HDR_TYPE) != + IEEE80211_TBTT_INFO_TYPE_TBTT) { + pos += count * length; + continue; + } + + /* TBTT info must include bss param + BSSID + * (short SSID or same_ssid bit to be set). * ignore other options, and move to the * next AP info */ if (band != NL80211_BAND_6GHZ || - (length != IEEE80211_TBTT_INFO_OFFSET_BSSID_BSS_PARAM && - length < IEEE80211_TBTT_INFO_OFFSET_BSSID_SSSID_BSS_PARAM)) { + !(length == offsetofend(struct ieee80211_tbtt_info_7_8_9, + bss_params) || + length == sizeof(struct ieee80211_tbtt_info_7_8_9) || + length >= offsetofend(struct ieee80211_tbtt_info_ge_11, + bss_params))) { pos += count * length; continue; } @@ -649,12 +716,13 @@ GFP_ATOMIC); if (!entry) - break; + goto error; entry->center_freq = freq; if (!cfg80211_parse_ap_info(entry, pos, length, - ssid_elem, s_ssid_tmp)) { + ssid_elem, + s_ssid_tmp)) { n_coloc++; list_add_tail(&entry->list, &ap_list); } else { @@ -665,10 +733,12 @@ } } +error: if (pos != end) { cfg80211_free_coloc_ap_list(&ap_list); return 0; } + } list_splice_tail(&ap_list, list); return n_coloc; @@ -760,10 +830,47 @@ list_for_each_entry(intbss, &rdev->bss_list, list) { struct cfg80211_bss *res = &intbss->pub; const struct cfg80211_bss_ies *ies; + const struct element *ssid_elem; + struct cfg80211_colocated_ap *entry; + u32 s_ssid_tmp; + int ret; ies = rcu_access_pointer(res->ies); count += cfg80211_parse_colocated_ap(ies, &coloc_ap_list); + + /* In case the scan request specified a specific BSSID + * and the BSS is found and operating on 6GHz band then + * add this AP to the collocated APs list. + * This is relevant for ML probe requests when the lower + * band APs have not been discovered. + */ + if (is_broadcast_ether_addr(rdev_req->bssid) || + !ether_addr_equal(rdev_req->bssid, res->bssid) || + res->channel->band != NL80211_BAND_6GHZ) + continue; + + ret = cfg80211_calc_short_ssid(ies, &ssid_elem, + &s_ssid_tmp); + if (ret) + continue; + + entry = kzalloc(sizeof(*entry) + IEEE80211_MAX_SSID_LEN, + GFP_ATOMIC); + + if (!entry) + continue; + + memcpy(entry->bssid, res->bssid, ETH_ALEN); + entry->short_ssid = s_ssid_tmp; + memcpy(entry->ssid, ssid_elem->data, + ssid_elem->datalen); + entry->ssid_len = ssid_elem->datalen; + entry->short_ssid_valid = true; + entry->center_freq = res->channel->center_freq; + + list_add_tail(&entry->list, &coloc_ap_list); + count++; } spin_unlock_bh(&rdev->bss_lock); } @@ -838,6 +945,10 @@ !cfg80211_find_ssid_match(ap, request)) continue; + if (!is_broadcast_ether_addr(request->bssid) && + !ether_addr_equal(request->bssid, ap->bssid)) + continue; + if (!request->n_ssids && ap->multi_bss && !ap->transmitted_bssid) continue; @@ -846,6 +957,7 @@ scan_6ghz_params->short_ssid = ap->short_ssid; scan_6ghz_params->short_ssid_valid = ap->short_ssid_valid; scan_6ghz_params->unsolicited_probe = ap->unsolicited_probe; + scan_6ghz_params->psd_20 = ap->psd_20; /* * If a PSC channel is added to the scan and 'need_scan_psc' is @@ -1004,16 +1116,9 @@ nl80211_send_scan_msg(rdev, msg); } -void __cfg80211_scan_done(struct work_struct *wk) +void __cfg80211_scan_done(struct wiphy *wiphy, struct wiphy_work *wk) { - struct cfg80211_registered_device *rdev; - - rdev = container_of(wk, struct cfg80211_registered_device, - scan_done_wk); - - wiphy_lock(&rdev->wiphy); - ___cfg80211_scan_done(rdev, true); - wiphy_unlock(&rdev->wiphy); + ___cfg80211_scan_done(wiphy_to_rdev(wiphy), true); } void cfg80211_scan_done(struct cfg80211_scan_request *request, @@ -1039,7 +1144,8 @@ } request->notified = true; - queue_work(cfg80211_wq, &wiphy_to_rdev(request->wiphy)->scan_done_wk); + wiphy_work_queue(request->wiphy, + &wiphy_to_rdev(request->wiphy)->scan_done_wk); } EXPORT_SYMBOL(cfg80211_scan_done); @@ -1573,8 +1679,6 @@ continue; if (bss->pub.channel != new->pub.channel) continue; - if (bss->pub.scan_width != new->pub.scan_width) - continue; if (rcu_access_pointer(bss->pub.beacon_ies)) continue; ies = rcu_access_pointer(bss->pub.ies); @@ -1604,12 +1708,6 @@ return true; } -struct cfg80211_non_tx_bss { - struct cfg80211_bss *tx_bss; - u8 max_bssid_indicator; - u8 bssid_index; -}; - static void cfg80211_update_hidden_bsses(struct cfg80211_internal_bss *known, const struct cfg80211_bss_ies *new_ies, const struct cfg80211_bss_ies *old_ies) @@ -1706,9 +1804,168 @@ return true; } +static const struct channel_5ghz_desc { + unsigned int freq; + unsigned int aligned_start_freq_40; + unsigned int aligned_start_freq_80; + unsigned int aligned_start_freq_160; +} channel_5ghz_descs[] = { + { 5180, 5170, 5170, 5170 }, /* 36 */ + { 5200, 5170, 5170, 5170 }, /* 40 */ + { 5220, 5210, 5170, 5170 }, /* 44 */ + { 5240, 5210, 5170, 5170 }, /* 48 */ + { 5260, 5250, 5250, 5170 }, /* 52 */ + { 5280, 5250, 5250, 5170 }, /* 56 */ + { 5300, 5290, 5250, 5170 }, /* 60 */ + { 5320, 5290, 5250, 5170 }, /* 64 */ + { 5340, 5330, 5330, 5330 }, /* 68 */ + { 5360, 5330, 5330, 5330 }, /* 72 */ + { 5380, 5370, 5330, 5330 }, /* 76 */ + { 5400, 5370, 5330, 5330 }, /* 80 */ + { 5420, 5410, 5410, 5330 }, /* 84 */ + { 5440, 5410, 5410, 5330 }, /* 88 */ + { 5460, 5450, 5410, 5330 }, /* 92 */ + { 5480, 5450, 5410, 5330 }, /* 96 */ + { 5500, 5490, 5490, 5490 }, /* 100 */ + { 5520, 5490, 5490, 5490 }, /* 104 */ + { 5540, 5530, 5490, 5490 }, /* 108 */ + { 5560, 5530, 5490, 5490 }, /* 112 */ + { 5580, 5570, 5570, 5490 }, /* 116 */ + { 5600, 5570, 5570, 5490 }, /* 120 */ + { 5620, 5610, 5570, 5490 }, /* 124 */ + { 5640, 5610, 5570, 5490 }, /* 128 */ + { 5660, 5650, 5650, 5650 }, /* 132 */ + { 5680, 5650, 5650, 5650 }, /* 136 */ + { 5700, 5690, 5650, 5650 }, /* 140 */ + { 5720, 5690, 5650, 5650 }, /* 144 */ + { 5745, 5735, 5735, 5735 }, /* 148 */ + { 5765, 5735, 5735, 5735 }, /* 152 */ + { 5785, 5775, 5735, 5735 }, /* 156 */ + { 5805, 5775, 5735, 5735 }, /* 160 */ + { 5825, 5815, 5815, 5735 }, /* 164 */ + { 5845, 5815, 5815, 5735 }, /* 168 */ + { 5865, 5855, 5815, 5735 }, /* 172 */ + { 5885, 5855, 5815, 5735 }, /* 176 */ + { 5905, 5895, 5895, 5895 }, /* 180 */ +}; + +static void bss_update_rdev_dfs_state(struct cfg80211_registered_device *rdev, + struct cfg80211_internal_bss *bss) +{ + struct ieee80211_channel *chan = bss->pub.channel; + const struct cfg80211_bss_ies *ies = bss->pub.ies; + const struct channel_5ghz_desc *cdesc; + const struct element *elem; + enum nl80211_band band; + unsigned int width, start_freq, freq; + u8 oper_class; + size_t i; + + /* extract some IE to check if AP seems to be indeed doing + * DFS, expect country code & power constraint to be present */ + if (!cfg80211_find_elem(WLAN_EID_PWR_CONSTRAINT, ies->data, + ies->len) || + !cfg80211_find_elem(WLAN_EID_COUNTRY, ies->data, + ies->len)) + return; + + /* guess operating bandwidth, use only operating class for + * now */ + elem = cfg80211_find_elem(WLAN_EID_SUPPORTED_REGULATORY_CLASSES, + ies->data, ies->len); + if (!elem || elem->datalen < 1) + return; + + oper_class = elem->data[0]; + if (!ieee80211_operating_class_to_band(oper_class, &band) || + band != NL80211_BAND_5GHZ) + return; + + switch (oper_class) { + case 115: + case 118: + case 121: + case 124: + case 125: + width = 20; + break; + case 116: + case 117: + case 119: + case 120: + case 122: + case 123: + case 126: + case 127: + width = 40; + break; + case 128: + width = 80; + break; + case 129: + width = 160; + break; + case 130: + /* ignore 80+80 */ + return; + default: + return; + } + + /* compute spanned channels according to primary channel & + * width */ + cdesc = NULL; + for (i = 0; i < ARRAY_SIZE(channel_5ghz_descs); i++) { + if (channel_5ghz_descs[i].freq == chan->center_freq) { + cdesc = &channel_5ghz_descs[i]; + break; + } + } + + if (!cdesc) + return; + + switch (width) { + case 20: + start_freq = cdesc->freq - 10; + break; + case 40: + start_freq = cdesc->aligned_start_freq_40; + break; + case 80: + start_freq = cdesc->aligned_start_freq_80; + break; + case 160: + start_freq = cdesc->aligned_start_freq_160; + break; + } + + for (freq = start_freq + 10; + freq <= start_freq + width - 10; + freq += 20) { + struct ieee80211_channel *c; + + c = ieee80211_get_channel(&rdev->wiphy, freq); + if (!c || + (c->flags & IEEE80211_CHAN_DISABLED) || + !(c->flags & IEEE80211_CHAN_RADAR)) + continue; + + if (c->dfs_state != NL80211_DFS_USABLE) + continue; + + wiphy_info(&rdev->wiphy, + "setting channel %u DFS state from scan result\n", + freq); + + c->dfs_state = NL80211_DFS_AVAILABLE; + c->dfs_state_entered = jiffies; + } +} + /* Returned bss is reference counted and must be cleaned up appropriately. */ -struct cfg80211_internal_bss * -cfg80211_bss_update(struct cfg80211_registered_device *rdev, +static struct cfg80211_internal_bss * +__cfg80211_bss_update(struct cfg80211_registered_device *rdev, struct cfg80211_internal_bss *tmp, bool signal_valid, unsigned long ts) { @@ -1719,10 +1976,7 @@ tmp->ts = ts; - spin_lock_bh(&rdev->bss_lock); - if (WARN_ON(!rcu_access_pointer(tmp->pub.ies))) { - spin_unlock_bh(&rdev->bss_lock); return NULL; } @@ -1730,7 +1984,11 @@ if (found) { if (!cfg80211_update_known_bss(rdev, found, tmp, signal_valid)) - goto drop; + return NULL; + + if (rdev->scan_req && + rdev->scan_req->flags & NL80211_SCAN_FLAG_UPDATE_DFS) + bss_update_rdev_dfs_state(rdev, found); } else { struct cfg80211_internal_bss *new; struct cfg80211_internal_bss *hidden; @@ -1750,7 +2008,7 @@ ies = (void *)rcu_dereference(tmp->pub.proberesp_ies); if (ies) kfree_rcu(ies, rcu_head); - goto drop; + return NULL; } memcpy(new, tmp, sizeof(*new)); new->refcount = 1; @@ -1781,14 +2039,14 @@ */ if (!cfg80211_combine_bsses(rdev, new)) { bss_ref_put(rdev, new); - goto drop; + return NULL; } } if (rdev->bss_entries >= bss_entries_limit && !cfg80211_bss_expire_oldest(rdev)) { bss_ref_put(rdev, new); - goto drop; + return NULL; } /* This must be before the call to bss_ref_get */ @@ -1797,6 +2055,10 @@ bss_ref_get(rdev, bss_from_pub(tmp->pub.transmitted_bss)); } + if (rdev->scan_req && + rdev->scan_req->flags & NL80211_SCAN_FLAG_UPDATE_DFS) + bss_update_rdev_dfs_state(rdev, new); + list_add_tail(&new->list, &rdev->bss_list); rdev->bss_entries++; rb_insert_bss(rdev, new); @@ -1805,12 +2067,22 @@ rdev->bss_generation++; bss_ref_get(rdev, found); - spin_unlock_bh(&rdev->bss_lock); return found; - drop: +} + +struct cfg80211_internal_bss * +cfg80211_bss_update(struct cfg80211_registered_device *rdev, + struct cfg80211_internal_bss *tmp, + bool signal_valid, unsigned long ts) +{ + struct cfg80211_internal_bss *res; + + spin_lock_bh(&rdev->bss_lock); + res = __cfg80211_bss_update(rdev, tmp, signal_valid, ts); spin_unlock_bh(&rdev->bss_lock); - return NULL; + + return res; } int cfg80211_get_ies_channel_number(const u8 *ie, size_t ielen, @@ -1870,8 +2142,7 @@ */ static struct ieee80211_channel * cfg80211_get_bss_channel(struct wiphy *wiphy, const u8 *ie, size_t ielen, - struct ieee80211_channel *channel, - enum nl80211_bss_scan_width scan_width) + struct ieee80211_channel *channel) { u32 freq; int channel_number; @@ -1911,16 +2182,6 @@ return channel; } - if (scan_width == NL80211_BSS_CHAN_WIDTH_10 || - scan_width == NL80211_BSS_CHAN_WIDTH_5) { - /* - * Ignore channel number in 5 and 10 MHz channels where there - * may not be an n:1 or 1:n mapping between frequencies and - * channel numbers. - */ - return channel; - } - /* * Use the channel determined through the payload channel number * instead of the RX channel reported by the driver. @@ -1930,17 +2191,36 @@ return alt_channel; } +struct cfg80211_inform_single_bss_data { + struct cfg80211_inform_bss *drv_data; + enum cfg80211_bss_frame_type ftype; + struct ieee80211_channel *channel; + u8 bssid[ETH_ALEN]; + u64 tsf; + u16 capability; + u16 beacon_interval; + const u8 *ie; + size_t ielen; + + enum { + BSS_SOURCE_DIRECT = 0, + BSS_SOURCE_MBSSID, + BSS_SOURCE_STA_PROFILE, + } bss_source; + /* Set if reporting bss_source != BSS_SOURCE_DIRECT */ + struct cfg80211_bss *source_bss; + u8 max_bssid_indicator; + u8 bssid_index; +}; + /* Returned bss is reference counted and must be cleaned up appropriately. */ static struct cfg80211_bss * cfg80211_inform_single_bss_data(struct wiphy *wiphy, - struct cfg80211_inform_bss *data, - enum cfg80211_bss_frame_type ftype, - const u8 *bssid, u64 tsf, u16 capability, - u16 beacon_interval, const u8 *ie, size_t ielen, - struct cfg80211_non_tx_bss *non_tx_data, + struct cfg80211_inform_single_bss_data *data, gfp_t gfp) { struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); + struct cfg80211_inform_bss *drv_data = data->drv_data; struct cfg80211_bss_ies *ies; struct ieee80211_channel *channel; struct cfg80211_internal_bss tmp = {}, *res; @@ -1952,31 +2232,51 @@ return NULL; if (WARN_ON(wiphy->signal_type == CFG80211_SIGNAL_TYPE_UNSPEC && - (data->signal < 0 || data->signal > 100))) + (drv_data->signal < 0 || drv_data->signal > 100))) return NULL; - channel = cfg80211_get_bss_channel(wiphy, ie, ielen, data->chan, - data->scan_width); + if (WARN_ON(data->bss_source != BSS_SOURCE_DIRECT && !data->source_bss)) + return NULL; + + channel = data->channel; + if (!channel) + channel = cfg80211_get_bss_channel(wiphy, data->ie, data->ielen, + drv_data->chan); if (!channel) return NULL; - memcpy(tmp.pub.bssid, bssid, ETH_ALEN); + memcpy(tmp.pub.bssid, data->bssid, ETH_ALEN); tmp.pub.channel = channel; - tmp.pub.scan_width = data->scan_width; - tmp.pub.signal = data->signal; - tmp.pub.beacon_interval = beacon_interval; - tmp.pub.capability = capability; - tmp.ts_boottime = data->boottime_ns; - tmp.parent_tsf = data->parent_tsf; - ether_addr_copy(tmp.parent_bssid, data->parent_bssid); - - if (non_tx_data) { - tmp.pub.transmitted_bss = non_tx_data->tx_bss; - ts = bss_from_pub(non_tx_data->tx_bss)->ts; - tmp.pub.bssid_index = non_tx_data->bssid_index; - tmp.pub.max_bssid_indicator = non_tx_data->max_bssid_indicator; + if (data->bss_source != BSS_SOURCE_STA_PROFILE) + tmp.pub.signal = drv_data->signal; + else + tmp.pub.signal = 0; + tmp.pub.beacon_interval = data->beacon_interval; + tmp.pub.capability = data->capability; + tmp.ts_boottime = drv_data->boottime_ns; + tmp.parent_tsf = drv_data->parent_tsf; + ether_addr_copy(tmp.parent_bssid, drv_data->parent_bssid); + + if (data->bss_source != BSS_SOURCE_DIRECT) { + tmp.pub.transmitted_bss = data->source_bss; + ts = bss_from_pub(data->source_bss)->ts; + tmp.pub.bssid_index = data->bssid_index; + tmp.pub.max_bssid_indicator = data->max_bssid_indicator; } else { ts = jiffies; + + if (channel->band == NL80211_BAND_60GHZ) { + bss_type = data->capability & + WLAN_CAPABILITY_DMG_TYPE_MASK; + if (bss_type == WLAN_CAPABILITY_DMG_TYPE_AP || + bss_type == WLAN_CAPABILITY_DMG_TYPE_PBSS) + regulatory_hint_found_beacon(wiphy, channel, + gfp); + } else { + if (data->capability & WLAN_CAPABILITY_ESS) + regulatory_hint_found_beacon(wiphy, channel, + gfp); + } } /* @@ -1987,15 +2287,15 @@ * override the IEs pointer should we have received an earlier * indication of Probe Response data. */ - ies = kzalloc(sizeof(*ies) + ielen, gfp); + ies = kzalloc(sizeof(*ies) + data->ielen, gfp); if (!ies) return NULL; - ies->len = ielen; - ies->tsf = tsf; + ies->len = data->ielen; + ies->tsf = data->tsf; ies->from_beacon = false; - memcpy(ies->data, ie, ielen); + memcpy(ies->data, data->ie, data->ielen); - switch (ftype) { + switch (data->ftype) { case CFG80211_BSS_FTYPE_BEACON: ies->from_beacon = true; fallthrough; @@ -2008,42 +2308,37 @@ } rcu_assign_pointer(tmp.pub.ies, ies); - signal_valid = data->chan == channel; - res = cfg80211_bss_update(wiphy_to_rdev(wiphy), &tmp, signal_valid, ts); + signal_valid = drv_data->chan == channel; + spin_lock_bh(&rdev->bss_lock); + res = __cfg80211_bss_update(rdev, &tmp, signal_valid, ts); if (!res) - return NULL; + goto drop; - if (channel->band == NL80211_BAND_60GHZ) { - bss_type = res->pub.capability & WLAN_CAPABILITY_DMG_TYPE_MASK; - if (bss_type == WLAN_CAPABILITY_DMG_TYPE_AP || - bss_type == WLAN_CAPABILITY_DMG_TYPE_PBSS) - regulatory_hint_found_beacon(wiphy, channel, gfp); - } else { - if (res->pub.capability & WLAN_CAPABILITY_ESS) - regulatory_hint_found_beacon(wiphy, channel, gfp); - } + rdev_inform_bss(rdev, &res->pub, ies, drv_data->drv_data); - if (non_tx_data) { + if (data->bss_source == BSS_SOURCE_MBSSID) { /* this is a nontransmitting bss, we need to add it to * transmitting bss' list if it is not there */ - spin_lock_bh(&rdev->bss_lock); - if (cfg80211_add_nontrans_list(non_tx_data->tx_bss, - &res->pub)) { + if (cfg80211_add_nontrans_list(data->source_bss, &res->pub)) { if (__cfg80211_unlink_bss(rdev, res)) { rdev->bss_generation++; res = NULL; } } - spin_unlock_bh(&rdev->bss_lock); if (!res) - return NULL; + goto drop; } + spin_unlock_bh(&rdev->bss_lock); trace_cfg80211_return_bss(&res->pub); - /* cfg80211_bss_update gives us a referenced result */ + /* __cfg80211_bss_update gives us a referenced result */ return &res->pub; + +drop: + spin_unlock_bh(&rdev->bss_lock); + return NULL; } static const struct element @@ -2118,43 +2413,48 @@ } EXPORT_SYMBOL(cfg80211_merge_profile); -static void cfg80211_parse_mbssid_data(struct wiphy *wiphy, - struct cfg80211_inform_bss *data, - enum cfg80211_bss_frame_type ftype, - const u8 *bssid, u64 tsf, - u16 beacon_interval, const u8 *ie, - size_t ielen, - struct cfg80211_non_tx_bss *non_tx_data, +static void +cfg80211_parse_mbssid_data(struct wiphy *wiphy, + struct cfg80211_inform_single_bss_data *tx_data, + struct cfg80211_bss *source_bss, gfp_t gfp) { + struct cfg80211_inform_single_bss_data data = { + .drv_data = tx_data->drv_data, + .ftype = tx_data->ftype, + .tsf = tx_data->tsf, + .beacon_interval = tx_data->beacon_interval, + .source_bss = source_bss, + .bss_source = BSS_SOURCE_MBSSID, + }; const u8 *mbssid_index_ie; const struct element *elem, *sub; - size_t new_ie_len; - u8 new_bssid[ETH_ALEN]; u8 *new_ie, *profile; u64 seen_indices = 0; - u16 capability; struct cfg80211_bss *bss; - if (!non_tx_data) + if (!source_bss) return; - if (!cfg80211_find_elem(WLAN_EID_MULTIPLE_BSSID, ie, ielen)) + if (!cfg80211_find_elem(WLAN_EID_MULTIPLE_BSSID, + tx_data->ie, tx_data->ielen)) return; if (!wiphy->support_mbssid) return; if (wiphy->support_only_he_mbssid && - !cfg80211_find_ext_elem(WLAN_EID_EXT_HE_CAPABILITY, ie, ielen)) + !cfg80211_find_ext_elem(WLAN_EID_EXT_HE_CAPABILITY, + tx_data->ie, tx_data->ielen)) return; new_ie = kmalloc(IEEE80211_MAX_DATA_LEN, gfp); if (!new_ie) return; - profile = kmalloc(ielen, gfp); + profile = kmalloc(tx_data->ielen, gfp); if (!profile) goto out; - for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, ie, ielen) { + for_each_element_id(elem, WLAN_EID_MULTIPLE_BSSID, + tx_data->ie, tx_data->ielen) { if (elem->datalen < 4) continue; if (elem->data[0] < 1 || (int)elem->data[0] > 8) @@ -2176,12 +2476,13 @@ continue; } - memset(profile, 0, ielen); - profile_len = cfg80211_merge_profile(ie, ielen, + memset(profile, 0, tx_data->ielen); + profile_len = cfg80211_merge_profile(tx_data->ie, + tx_data->ielen, elem, sub, profile, - ielen); + tx_data->ielen); /* found a Nontransmitted BSSID Profile */ mbssid_index_ie = cfg80211_find_ie @@ -2201,31 +2502,27 @@ seen_indices |= BIT_ULL(mbssid_index_ie[2]); - non_tx_data->bssid_index = mbssid_index_ie[2]; - non_tx_data->max_bssid_indicator = elem->data[0]; + data.bssid_index = mbssid_index_ie[2]; + data.max_bssid_indicator = elem->data[0]; + + cfg80211_gen_new_bssid(tx_data->bssid, + data.max_bssid_indicator, + data.bssid_index, + data.bssid); - cfg80211_gen_new_bssid(bssid, - non_tx_data->max_bssid_indicator, - non_tx_data->bssid_index, - new_bssid); memset(new_ie, 0, IEEE80211_MAX_DATA_LEN); - new_ie_len = cfg80211_gen_new_ie(ie, ielen, + data.ie = new_ie; + data.ielen = cfg80211_gen_new_ie(tx_data->ie, + tx_data->ielen, profile, - profile_len, new_ie, - gfp); - if (!new_ie_len) + profile_len, + new_ie, + IEEE80211_MAX_DATA_LEN); + if (!data.ielen) continue; - capability = get_unaligned_le16(profile + 2); - bss = cfg80211_inform_single_bss_data(wiphy, data, - ftype, - new_bssid, tsf, - capability, - beacon_interval, - new_ie, - new_ie_len, - non_tx_data, - gfp); + data.capability = get_unaligned_le16(profile + 2); + bss = cfg80211_inform_single_bss_data(wiphy, &data, gfp); if (!bss) break; cfg80211_put_bss(wiphy, bss); @@ -2237,142 +2534,425 @@ kfree(profile); } -struct cfg80211_bss * -cfg80211_inform_bss_data(struct wiphy *wiphy, - struct cfg80211_inform_bss *data, - enum cfg80211_bss_frame_type ftype, - const u8 *bssid, u64 tsf, u16 capability, - u16 beacon_interval, const u8 *ie, size_t ielen, +ssize_t cfg80211_defragment_element(const struct element *elem, const u8 *ies, + size_t ieslen, u8 *data, size_t data_len, + u8 frag_id) +{ + const struct element *next; + ssize_t copied; + u8 elem_datalen; + + if (!elem) + return -EINVAL; + + /* elem might be invalid after the memmove */ + next = (void *)(elem->data + elem->datalen); + elem_datalen = elem->datalen; + + if (elem->id == WLAN_EID_EXTENSION) { + copied = elem->datalen - 1; + if (copied > data_len) + return -ENOSPC; + + memmove(data, elem->data + 1, copied); + } else { + copied = elem->datalen; + if (copied > data_len) + return -ENOSPC; + + memmove(data, elem->data, copied); + } + + /* Fragmented elements must have 255 bytes */ + if (elem_datalen < 255) + return copied; + + for (elem = next; + elem->data < ies + ieslen && + elem->data + elem->datalen <= ies + ieslen; + elem = next) { + /* elem might be invalid after the memmove */ + next = (void *)(elem->data + elem->datalen); + + if (elem->id != frag_id) + break; + + elem_datalen = elem->datalen; + + if (copied + elem_datalen > data_len) + return -ENOSPC; + + memmove(data + copied, elem->data, elem_datalen); + copied += elem_datalen; + + /* Only the last fragment may be short */ + if (elem_datalen != 255) + break; + } + + return copied; +} +EXPORT_SYMBOL(cfg80211_defragment_element); + +struct cfg80211_mle { + struct ieee80211_multi_link_elem *mle; + struct ieee80211_mle_per_sta_profile + *sta_prof[IEEE80211_MLD_MAX_NUM_LINKS]; + ssize_t sta_prof_len[IEEE80211_MLD_MAX_NUM_LINKS]; + + u8 data[]; +}; + +static struct cfg80211_mle * +cfg80211_defrag_mle(const struct element *mle, const u8 *ie, size_t ielen, gfp_t gfp) { - struct cfg80211_bss *res; - struct cfg80211_non_tx_bss non_tx_data; + const struct element *elem; + struct cfg80211_mle *res; + size_t buf_len; + ssize_t mle_len; + u8 common_size, idx; + + if (!mle || !ieee80211_mle_size_ok(mle->data + 1, mle->datalen - 1)) + return NULL; + + /* Required length for first defragmentation */ + buf_len = mle->datalen - 1; + for_each_element(elem, mle->data + mle->datalen, + ielen - sizeof(*mle) + mle->datalen) { + if (elem->id != WLAN_EID_FRAGMENT) + break; - res = cfg80211_inform_single_bss_data(wiphy, data, ftype, bssid, tsf, - capability, beacon_interval, ie, - ielen, NULL, gfp); + buf_len += elem->datalen; + } + + res = kzalloc(struct_size(res, data, buf_len), gfp); if (!res) return NULL; - non_tx_data.tx_bss = res; - cfg80211_parse_mbssid_data(wiphy, data, ftype, bssid, tsf, - beacon_interval, ie, ielen, &non_tx_data, - gfp); + + mle_len = cfg80211_defragment_element(mle, ie, ielen, + res->data, buf_len, + WLAN_EID_FRAGMENT); + if (mle_len < 0) + goto error; + + res->mle = (void *)res->data; + + /* Find the sub-element area in the buffer */ + common_size = ieee80211_mle_common_size((u8 *)res->mle); + ie = res->data + common_size; + ielen = mle_len - common_size; + + idx = 0; + for_each_element_id(elem, IEEE80211_MLE_SUBELEM_PER_STA_PROFILE, + ie, ielen) { + res->sta_prof[idx] = (void *)elem->data; + res->sta_prof_len[idx] = elem->datalen; + + idx++; + if (idx >= IEEE80211_MLD_MAX_NUM_LINKS) + break; + } + if (!for_each_element_completed(elem, ie, ielen)) + goto error; + + /* Defragment sta_info in-place */ + for (idx = 0; idx < IEEE80211_MLD_MAX_NUM_LINKS && res->sta_prof[idx]; + idx++) { + if (res->sta_prof_len[idx] < 255) + continue; + + elem = (void *)res->sta_prof[idx] - 2; + + if (idx + 1 < ARRAY_SIZE(res->sta_prof) && + res->sta_prof[idx + 1]) + buf_len = (u8 *)res->sta_prof[idx + 1] - + (u8 *)res->sta_prof[idx]; + else + buf_len = ielen + ie - (u8 *)elem; + + res->sta_prof_len[idx] = + cfg80211_defragment_element(elem, + (u8 *)elem, buf_len, + (u8 *)res->sta_prof[idx], + buf_len, + IEEE80211_MLE_SUBELEM_FRAGMENT); + if (res->sta_prof_len[idx] < 0) + goto error; + } + return res; + +error: + kfree(res); + return NULL; } -EXPORT_SYMBOL(cfg80211_inform_bss_data); -static void -cfg80211_parse_mbssid_frame_data(struct wiphy *wiphy, - struct cfg80211_inform_bss *data, - struct ieee80211_mgmt *mgmt, size_t len, - struct cfg80211_non_tx_bss *non_tx_data, - gfp_t gfp) +static bool +cfg80211_tbtt_info_for_mld_ap(const u8 *ie, size_t ielen, u8 mld_id, u8 link_id, + const struct ieee80211_neighbor_ap_info **ap_info, + const u8 **tbtt_info) { - enum cfg80211_bss_frame_type ftype; - const u8 *ie = mgmt->u.probe_resp.variable; - size_t ielen = len - offsetof(struct ieee80211_mgmt, - u.probe_resp.variable); + const struct ieee80211_neighbor_ap_info *info; + const struct element *rnr; + const u8 *pos, *end; - ftype = ieee80211_is_beacon(mgmt->frame_control) ? - CFG80211_BSS_FTYPE_BEACON : CFG80211_BSS_FTYPE_PRESP; + for_each_element_id(rnr, WLAN_EID_REDUCED_NEIGHBOR_REPORT, ie, ielen) { + pos = rnr->data; + end = rnr->data + rnr->datalen; - cfg80211_parse_mbssid_data(wiphy, data, ftype, mgmt->bssid, - le64_to_cpu(mgmt->u.probe_resp.timestamp), - le16_to_cpu(mgmt->u.probe_resp.beacon_int), - ie, ielen, non_tx_data, gfp); + /* RNR IE may contain more than one NEIGHBOR_AP_INFO */ + while (sizeof(*info) <= end - pos) { + const struct ieee80211_rnr_mld_params *mld_params; + u16 params; + u8 length, i, count, mld_params_offset; + u8 type, lid; + + info = (void *)pos; + count = u8_get_bits(info->tbtt_info_hdr, + IEEE80211_AP_INFO_TBTT_HDR_COUNT) + 1; + length = info->tbtt_info_len; + + pos += sizeof(*info); + + if (count * length > end - pos) + return false; + + type = u8_get_bits(info->tbtt_info_hdr, + IEEE80211_AP_INFO_TBTT_HDR_TYPE); + + /* Only accept full TBTT information. NSTR mobile APs + * use the shortened version, but we ignore them here. + */ + if (type == IEEE80211_TBTT_INFO_TYPE_TBTT && + length >= + offsetofend(struct ieee80211_tbtt_info_ge_11, + mld_params)) { + mld_params_offset = + offsetof(struct ieee80211_tbtt_info_ge_11, mld_params); + } else { + pos += count * length; + continue; } -static void -cfg80211_update_notlisted_nontrans(struct wiphy *wiphy, - struct cfg80211_bss *nontrans_bss, - struct ieee80211_mgmt *mgmt, size_t len) -{ - u8 *ie, *new_ie, *pos; - const struct element *nontrans_ssid; - const u8 *trans_ssid, *mbssid; - size_t ielen = len - offsetof(struct ieee80211_mgmt, - u.probe_resp.variable); - size_t new_ie_len; - struct cfg80211_bss_ies *new_ies; - const struct cfg80211_bss_ies *old; - size_t cpy_len; + for (i = 0; i < count; i++) { + mld_params = (void *)pos + mld_params_offset; + params = le16_to_cpu(mld_params->params); + + lid = u16_get_bits(params, + IEEE80211_RNR_MLD_PARAMS_LINK_ID); + + if (mld_id == mld_params->mld_id && + link_id == lid) { + *ap_info = info; + *tbtt_info = pos; + + return true; + } + + pos += length; + } + } + } - lockdep_assert_held(&wiphy_to_rdev(wiphy)->bss_lock); + return false; +} - ie = mgmt->u.probe_resp.variable; +static void cfg80211_parse_ml_sta_data(struct wiphy *wiphy, + struct cfg80211_inform_single_bss_data *tx_data, + struct cfg80211_bss *source_bss, + gfp_t gfp) +{ + struct cfg80211_inform_single_bss_data data = { + .drv_data = tx_data->drv_data, + .ftype = tx_data->ftype, + .source_bss = source_bss, + .bss_source = BSS_SOURCE_STA_PROFILE, + }; + struct ieee80211_multi_link_elem *ml_elem; + const struct element *elem; + struct cfg80211_mle *mle; + u16 control; + u8 *new_ie; + struct cfg80211_bss *bss; + int mld_id; + u16 seen_links = 0; + const u8 *pos; + u8 i; - new_ie_len = ielen; - trans_ssid = cfg80211_find_ie(WLAN_EID_SSID, ie, ielen); - if (!trans_ssid) + if (!source_bss) return; - new_ie_len -= trans_ssid[1]; - mbssid = cfg80211_find_ie(WLAN_EID_MULTIPLE_BSSID, ie, ielen); - /* - * It's not valid to have the MBSSID element before SSID - * ignore if that happens - the code below assumes it is - * after (while copying things inbetween). - */ - if (!mbssid || mbssid < trans_ssid) + + if (tx_data->ftype != CFG80211_BSS_FTYPE_PRESP) return; - new_ie_len -= mbssid[1]; - nontrans_ssid = ieee80211_bss_get_elem(nontrans_bss, WLAN_EID_SSID); - if (!nontrans_ssid) + elem = cfg80211_find_ext_elem(WLAN_EID_EXT_EHT_MULTI_LINK, + tx_data->ie, tx_data->ielen); + if (!elem || !ieee80211_mle_size_ok(elem->data + 1, elem->datalen - 1)) return; - new_ie_len += nontrans_ssid->datalen; + ml_elem = (void *)elem->data + 1; + control = le16_to_cpu(ml_elem->control); + if (u16_get_bits(control, IEEE80211_ML_CONTROL_TYPE) != + IEEE80211_ML_CONTROL_TYPE_BASIC) + return; - /* generate new ie for nontrans BSS - * 1. replace SSID with nontrans BSS' SSID - * 2. skip MBSSID IE - */ - new_ie = kzalloc(new_ie_len, GFP_ATOMIC); - if (!new_ie) + /* Must be present when transmitted by an AP (in a probe response) */ + if (!(control & IEEE80211_MLC_BASIC_PRES_BSS_PARAM_CH_CNT) || + !(control & IEEE80211_MLC_BASIC_PRES_LINK_ID) || + !(control & IEEE80211_MLC_BASIC_PRES_MLD_CAPA_OP)) return; - new_ies = kzalloc(sizeof(*new_ies) + new_ie_len, GFP_ATOMIC); - if (!new_ies) - goto out_free; - - pos = new_ie; - - /* copy the nontransmitted SSID */ - cpy_len = nontrans_ssid->datalen + 2; - memcpy(pos, nontrans_ssid, cpy_len); - pos += cpy_len; - /* copy the IEs between SSID and MBSSID */ - cpy_len = trans_ssid[1] + 2; - memcpy(pos, (trans_ssid + cpy_len), (mbssid - (trans_ssid + cpy_len))); - pos += (mbssid - (trans_ssid + cpy_len)); - /* copy the IEs after MBSSID */ - cpy_len = mbssid[1] + 2; - memcpy(pos, mbssid + cpy_len, ((ie + ielen) - (mbssid + cpy_len))); - - /* update ie */ - new_ies->len = new_ie_len; - new_ies->tsf = le64_to_cpu(mgmt->u.probe_resp.timestamp); - new_ies->from_beacon = ieee80211_is_beacon(mgmt->frame_control); - memcpy(new_ies->data, new_ie, new_ie_len); - if (ieee80211_is_probe_resp(mgmt->frame_control)) { - old = rcu_access_pointer(nontrans_bss->proberesp_ies); - rcu_assign_pointer(nontrans_bss->proberesp_ies, new_ies); - rcu_assign_pointer(nontrans_bss->ies, new_ies); - if (old) - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); + /* length + MLD MAC address + link ID info + BSS Params Change Count */ + pos = ml_elem->variable + 1 + 6 + 1 + 1; + + if (u16_get_bits(control, IEEE80211_MLC_BASIC_PRES_MED_SYNC_DELAY)) + pos += 2; + if (u16_get_bits(control, IEEE80211_MLC_BASIC_PRES_EML_CAPA)) + pos += 2; + + /* MLD capabilities and operations */ + pos += 2; + + /* Not included when the (nontransmitted) AP is responding itself, + * but defined to zero then (Draft P802.11be_D3.0, 9.4.2.170.2) + */ + if (u16_get_bits(control, IEEE80211_MLC_BASIC_PRES_MLD_ID)) { + mld_id = *pos; + pos += 1; } else { - old = rcu_access_pointer(nontrans_bss->beacon_ies); - rcu_assign_pointer(nontrans_bss->beacon_ies, new_ies); - cfg80211_update_hidden_bsses(bss_from_pub(nontrans_bss), - new_ies, old); - rcu_assign_pointer(nontrans_bss->ies, new_ies); - if (old) - kfree_rcu((struct cfg80211_bss_ies *)old, rcu_head); + mld_id = 0; + } + + /* Extended MLD capabilities and operations */ + pos += 2; + + /* Fully defrag the ML element for sta information/profile iteration */ + mle = cfg80211_defrag_mle(elem, tx_data->ie, tx_data->ielen, gfp); + if (!mle) + return; + + new_ie = kmalloc(IEEE80211_MAX_DATA_LEN, gfp); + if (!new_ie) + goto out; + + for (i = 0; i < ARRAY_SIZE(mle->sta_prof) && mle->sta_prof[i]; i++) { + const struct ieee80211_neighbor_ap_info *ap_info; + enum nl80211_band band; + u32 freq; + const u8 *profile; + const u8 *tbtt_info; + ssize_t profile_len; + u8 link_id; + + if (!ieee80211_mle_basic_sta_prof_size_ok((u8 *)mle->sta_prof[i], + mle->sta_prof_len[i])) + continue; + + control = le16_to_cpu(mle->sta_prof[i]->control); + + if (!(control & IEEE80211_MLE_STA_CONTROL_COMPLETE_PROFILE)) + continue; + + link_id = u16_get_bits(control, + IEEE80211_MLE_STA_CONTROL_LINK_ID); + if (seen_links & BIT(link_id)) + break; + seen_links |= BIT(link_id); + + if (!(control & IEEE80211_MLE_STA_CONTROL_BEACON_INT_PRESENT) || + !(control & IEEE80211_MLE_STA_CONTROL_TSF_OFFS_PRESENT) || + !(control & IEEE80211_MLE_STA_CONTROL_STA_MAC_ADDR_PRESENT)) + continue; + + memcpy(data.bssid, mle->sta_prof[i]->variable, ETH_ALEN); + data.beacon_interval = + get_unaligned_le16(mle->sta_prof[i]->variable + 6); + data.tsf = tx_data->tsf + + get_unaligned_le64(mle->sta_prof[i]->variable + 8); + + /* sta_info_len counts itself */ + profile = mle->sta_prof[i]->variable + + mle->sta_prof[i]->sta_info_len - 1; + profile_len = (u8 *)mle->sta_prof[i] + mle->sta_prof_len[i] - + profile; + + if (profile_len < 2) + continue; + + data.capability = get_unaligned_le16(profile); + profile += 2; + profile_len -= 2; + + /* Find in RNR to look up channel information */ + if (!cfg80211_tbtt_info_for_mld_ap(tx_data->ie, tx_data->ielen, + mld_id, link_id, + &ap_info, &tbtt_info)) + continue; + + /* We could sanity check the BSSID is included */ + + if (!ieee80211_operating_class_to_band(ap_info->op_class, + &band)) + continue; + + freq = ieee80211_channel_to_freq_khz(ap_info->channel, band); + data.channel = ieee80211_get_channel_khz(wiphy, freq); + + /* Generate new elements */ + memset(new_ie, 0, IEEE80211_MAX_DATA_LEN); + data.ie = new_ie; + data.ielen = cfg80211_gen_new_ie(tx_data->ie, tx_data->ielen, + profile, profile_len, + new_ie, + IEEE80211_MAX_DATA_LEN); + if (!data.ielen) + continue; + + bss = cfg80211_inform_single_bss_data(wiphy, &data, gfp); + if (!bss) + break; + cfg80211_put_bss(wiphy, bss); } -out_free: +out: kfree(new_ie); + kfree(mle); } +struct cfg80211_bss * +cfg80211_inform_bss_data(struct wiphy *wiphy, + struct cfg80211_inform_bss *data, + enum cfg80211_bss_frame_type ftype, + const u8 *bssid, u64 tsf, u16 capability, + u16 beacon_interval, const u8 *ie, size_t ielen, + gfp_t gfp) +{ + struct cfg80211_inform_single_bss_data inform_data = { + .drv_data = data, + .ftype = ftype, + .tsf = tsf, + .capability = capability, + .beacon_interval = beacon_interval, + .ie = ie, + .ielen = ielen, + }; + struct cfg80211_bss *res; + + memcpy(inform_data.bssid, bssid, ETH_ALEN); + + res = cfg80211_inform_single_bss_data(wiphy, &inform_data, gfp); + if (!res) + return NULL; + + cfg80211_parse_mbssid_data(wiphy, &inform_data, res, gfp); + + cfg80211_parse_ml_sta_data(wiphy, &inform_data, res, gfp); + + return res; +} +EXPORT_SYMBOL(cfg80211_inform_bss_data); + /* cfg80211_inform_bss_width_frame helper */ static struct cfg80211_bss * cfg80211_inform_single_bss_frame_data(struct wiphy *wiphy, @@ -2380,6 +2960,7 @@ struct ieee80211_mgmt *mgmt, size_t len, gfp_t gfp) { + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wiphy); struct cfg80211_internal_bss tmp = {}, *res; struct cfg80211_bss_ies *ies; struct ieee80211_channel *channel; @@ -2426,8 +3007,7 @@ variable = ext->u.s1g_beacon.variable; } - channel = cfg80211_get_bss_channel(wiphy, variable, - ielen, data->chan, data->scan_width); + channel = cfg80211_get_bss_channel(wiphy, variable, ielen, data->chan); if (!channel) return NULL; @@ -2451,6 +3031,16 @@ capability = le16_to_cpu(mgmt->u.probe_resp.capab_info); } + if (channel->band == NL80211_BAND_60GHZ) { + bss_type = capability & WLAN_CAPABILITY_DMG_TYPE_MASK; + if (bss_type == WLAN_CAPABILITY_DMG_TYPE_AP || + bss_type == WLAN_CAPABILITY_DMG_TYPE_PBSS) + regulatory_hint_found_beacon(wiphy, channel, gfp); + } else { + if (capability & WLAN_CAPABILITY_ESS) + regulatory_hint_found_beacon(wiphy, channel, gfp); + } + ies = kzalloc(sizeof(*ies) + ielen, gfp); if (!ies) return NULL; @@ -2470,7 +3060,6 @@ tmp.pub.beacon_interval = beacon_int; tmp.pub.capability = capability; tmp.pub.channel = channel; - tmp.pub.scan_width = data->scan_width; tmp.pub.signal = data->signal; tmp.ts_boottime = data->boottime_ns; tmp.parent_tsf = data->parent_tsf; @@ -2479,24 +3068,22 @@ ether_addr_copy(tmp.parent_bssid, data->parent_bssid); signal_valid = data->chan == channel; - res = cfg80211_bss_update(wiphy_to_rdev(wiphy), &tmp, signal_valid, - jiffies); + spin_lock_bh(&rdev->bss_lock); + res = __cfg80211_bss_update(rdev, &tmp, signal_valid, jiffies); if (!res) - return NULL; + goto drop; - if (channel->band == NL80211_BAND_60GHZ) { - bss_type = res->pub.capability & WLAN_CAPABILITY_DMG_TYPE_MASK; - if (bss_type == WLAN_CAPABILITY_DMG_TYPE_AP || - bss_type == WLAN_CAPABILITY_DMG_TYPE_PBSS) - regulatory_hint_found_beacon(wiphy, channel, gfp); - } else { - if (res->pub.capability & WLAN_CAPABILITY_ESS) - regulatory_hint_found_beacon(wiphy, channel, gfp); - } + rdev_inform_bss(rdev, &res->pub, ies, data->drv_data); + + spin_unlock_bh(&rdev->bss_lock); trace_cfg80211_return_bss(&res->pub); - /* cfg80211_bss_update gives us a referenced result */ + /* __cfg80211_bss_update gives us a referenced result */ return &res->pub; + +drop: + spin_unlock_bh(&rdev->bss_lock); + return NULL; } struct cfg80211_bss * @@ -2505,51 +3092,34 @@ struct ieee80211_mgmt *mgmt, size_t len, gfp_t gfp) { - struct cfg80211_bss *res, *tmp_bss; - const u8 *ie = mgmt->u.probe_resp.variable; - const struct cfg80211_bss_ies *ies1, *ies2; - size_t ielen = len - offsetof(struct ieee80211_mgmt, - u.probe_resp.variable); - struct cfg80211_non_tx_bss non_tx_data = {}; + struct cfg80211_inform_single_bss_data inform_data = { + .drv_data = data, + .ie = mgmt->u.probe_resp.variable, + .ielen = len - offsetof(struct ieee80211_mgmt, + u.probe_resp.variable), + }; + struct cfg80211_bss *res; res = cfg80211_inform_single_bss_frame_data(wiphy, data, mgmt, len, gfp); + if (!res) + return NULL; - /* don't do any further MBSSID handling for S1G */ + /* don't do any further MBSSID/ML handling for S1G */ if (ieee80211_is_s1g_beacon(mgmt->frame_control)) return res; - if (!res || !wiphy->support_mbssid || - !cfg80211_find_elem(WLAN_EID_MULTIPLE_BSSID, ie, ielen)) - return res; - if (wiphy->support_only_he_mbssid && - !cfg80211_find_ext_elem(WLAN_EID_EXT_HE_CAPABILITY, ie, ielen)) - return res; + inform_data.ftype = ieee80211_is_beacon(mgmt->frame_control) ? + CFG80211_BSS_FTYPE_BEACON : CFG80211_BSS_FTYPE_PRESP; + memcpy(inform_data.bssid, mgmt->bssid, ETH_ALEN); + inform_data.tsf = le64_to_cpu(mgmt->u.probe_resp.timestamp); + inform_data.beacon_interval = + le16_to_cpu(mgmt->u.probe_resp.beacon_int); - non_tx_data.tx_bss = res; /* process each non-transmitting bss */ - cfg80211_parse_mbssid_frame_data(wiphy, data, mgmt, len, - &non_tx_data, gfp); - - spin_lock_bh(&wiphy_to_rdev(wiphy)->bss_lock); - - /* check if the res has other nontransmitting bss which is not - * in MBSSID IE - */ - ies1 = rcu_access_pointer(res->ies); + cfg80211_parse_mbssid_data(wiphy, &inform_data, res, gfp); - /* go through nontrans_list, if the timestamp of the BSS is - * earlier than the timestamp of the transmitting BSS then - * update it - */ - list_for_each_entry(tmp_bss, &res->nontrans_list, - nontrans_list) { - ies2 = rcu_access_pointer(tmp_bss->ies); - if (ies2->tsf < ies1->tsf) - cfg80211_update_notlisted_nontrans(wiphy, tmp_bss, - mgmt, len); - } - spin_unlock_bh(&wiphy_to_rdev(wiphy)->bss_lock); + cfg80211_parse_ml_sta_data(wiphy, &inform_data, res, gfp); return res; } @@ -3043,59 +3613,63 @@ cfg = (u8 *)ie + 2; memset(&iwe, 0, sizeof(iwe)); iwe.cmd = IWEVCUSTOM; - sprintf(buf, "Mesh Network Path Selection Protocol ID: " - "0x%02X", cfg[0]); - iwe.u.data.length = strlen(buf); + iwe.u.data.length = sprintf(buf, + "Mesh Network Path Selection Protocol ID: 0x%02X", + cfg[0]); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) goto unlock; - sprintf(buf, "Path Selection Metric ID: 0x%02X", + iwe.u.data.length = sprintf(buf, + "Path Selection Metric ID: 0x%02X", cfg[1]); - iwe.u.data.length = strlen(buf); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) goto unlock; - sprintf(buf, "Congestion Control Mode ID: 0x%02X", + iwe.u.data.length = sprintf(buf, + "Congestion Control Mode ID: 0x%02X", cfg[2]); - iwe.u.data.length = strlen(buf); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) goto unlock; - sprintf(buf, "Synchronization ID: 0x%02X", cfg[3]); - iwe.u.data.length = strlen(buf); + iwe.u.data.length = sprintf(buf, + "Synchronization ID: 0x%02X", + cfg[3]); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) goto unlock; - sprintf(buf, "Authentication ID: 0x%02X", cfg[4]); - iwe.u.data.length = strlen(buf); + iwe.u.data.length = sprintf(buf, + "Authentication ID: 0x%02X", + cfg[4]); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) goto unlock; - sprintf(buf, "Formation Info: 0x%02X", cfg[5]); - iwe.u.data.length = strlen(buf); + iwe.u.data.length = sprintf(buf, + "Formation Info: 0x%02X", + cfg[5]); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) goto unlock; - sprintf(buf, "Capabilities: 0x%02X", cfg[6]); - iwe.u.data.length = strlen(buf); + iwe.u.data.length = sprintf(buf, + "Capabilities: 0x%02X", + cfg[6]); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, @@ -3151,17 +3725,16 @@ memset(&iwe, 0, sizeof(iwe)); iwe.cmd = IWEVCUSTOM; - sprintf(buf, "tsf=%016llx", (unsigned long long)(ies->tsf)); - iwe.u.data.length = strlen(buf); + iwe.u.data.length = sprintf(buf, "tsf=%016llx", + (unsigned long long)(ies->tsf)); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) goto unlock; memset(&iwe, 0, sizeof(iwe)); iwe.cmd = IWEVCUSTOM; - sprintf(buf, " Last beacon: %ums ago", + iwe.u.data.length = sprintf(buf, " Last beacon: %ums ago", elapsed_jiffies_msecs(bss->ts)); - iwe.u.data.length = strlen(buf); current_ev = iwe_stream_add_point_check(info, current_ev, end_buf, &iwe, buf); if (IS_ERR(current_ev)) diff -ruw linux-6.4/net/wireless/sme.c linux-6.4-fbx/net/wireless/sme.c --- linux-6.4/net/wireless/sme.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/sme.c 2023-11-07 13:38:44.114258112 +0100 @@ -5,7 +5,7 @@ * (for nl80211's connect() and wext) * * Copyright 2009 Johannes Berg - * Copyright (C) 2009, 2020, 2022 Intel Corporation. All rights reserved. + * Copyright (C) 2009, 2020, 2022-2023 Intel Corporation. All rights reserved. * Copyright 2017 Intel Deutschland GmbH */ @@ -67,7 +67,7 @@ struct cfg80211_scan_request *request; int n_channels, err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (rdev->scan_req || rdev->scan_msg) return -EBUSY; @@ -151,7 +151,7 @@ struct cfg80211_assoc_request req = {}; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!wdev->conn) return 0; @@ -255,16 +255,13 @@ if (!wdev->netdev) continue; - wdev_lock(wdev); - if (!netif_running(wdev->netdev)) { - wdev_unlock(wdev); + if (!netif_running(wdev->netdev)) continue; - } + if (!wdev->conn || - wdev->conn->state == CFG80211_CONN_CONNECTED) { - wdev_unlock(wdev); + wdev->conn->state == CFG80211_CONN_CONNECTED) continue; - } + if (wdev->conn->params.bssid) { memcpy(bssid_buf, wdev->conn->params.bssid, ETH_ALEN); bssid = bssid_buf; @@ -279,7 +276,6 @@ cr.timeout_reason = treason; __cfg80211_connect_result(wdev->netdev, &cr, false); } - wdev_unlock(wdev); } wiphy_unlock(&rdev->wiphy); @@ -300,7 +296,7 @@ struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); struct cfg80211_bss *bss; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); bss = cfg80211_get_bss(wdev->wiphy, wdev->conn->params.channel, wdev->conn->params.bssid, @@ -317,13 +313,13 @@ return bss; } -static void __cfg80211_sme_scan_done(struct net_device *dev) +void cfg80211_sme_scan_done(struct net_device *dev) { struct wireless_dev *wdev = dev->ieee80211_ptr; struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); struct cfg80211_bss *bss; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!wdev->conn) return; @@ -339,15 +335,6 @@ schedule_work(&rdev->conn_work); } -void cfg80211_sme_scan_done(struct net_device *dev) -{ - struct wireless_dev *wdev = dev->ieee80211_ptr; - - wdev_lock(wdev); - __cfg80211_sme_scan_done(dev); - wdev_unlock(wdev); -} - void cfg80211_sme_rx_auth(struct wireless_dev *wdev, const u8 *buf, size_t len) { struct wiphy *wiphy = wdev->wiphy; @@ -355,7 +342,7 @@ struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)buf; u16 status_code = le16_to_cpu(mgmt->u.auth.status_code); - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (!wdev->conn || wdev->conn->state == CFG80211_CONN_CONNECTED) return; @@ -491,6 +478,21 @@ } } +void cfg80211_wdev_release_link_bsses(struct wireless_dev *wdev, u16 link_mask) +{ + unsigned int link; + + for_each_valid_link(wdev, link) { + if (!wdev->links[link].client.current_bss || + !(link_mask & BIT(link))) + continue; + cfg80211_unhold_bss(wdev->links[link].client.current_bss); + cfg80211_put_bss(wdev->wiphy, + &wdev->links[link].client.current_bss->pub); + wdev->links[link].client.current_bss = NULL; + } +} + static int cfg80211_sme_get_conn_ies(struct wireless_dev *wdev, const u8 *ies, size_t ies_len, const u8 **out_ies, size_t *out_ies_len) @@ -687,14 +689,14 @@ * need not issue a disconnect hint and reset any info such * as chan dfs state, etc. */ - list_for_each_entry(rdev, &cfg80211_rdev_list, list) { + for_each_rdev(rdev) { + wiphy_lock(&rdev->wiphy); list_for_each_entry(wdev, &rdev->wiphy.wdev_list, list) { - wdev_lock(wdev); if (wdev->conn || wdev->connected || cfg80211_beaconing_iface_active(wdev)) is_all_idle = false; - wdev_unlock(wdev); } + wiphy_unlock(&rdev->wiphy); } return is_all_idle; @@ -746,7 +748,7 @@ const u8 *connected_addr; bool bss_not_found = false; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION && wdev->iftype != NL80211_IFTYPE_P2P_CLIENT)) @@ -1078,7 +1080,7 @@ unsigned int link; const u8 *connected_addr; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION && wdev->iftype != NL80211_IFTYPE_P2P_CLIENT)) @@ -1279,24 +1281,29 @@ } EXPORT_SYMBOL(cfg80211_roamed); -void __cfg80211_port_authorized(struct wireless_dev *wdev, const u8 *bssid, +void __cfg80211_port_authorized(struct wireless_dev *wdev, const u8 *peer_addr, const u8 *td_bitmap, u8 td_bitmap_len) { - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION && - wdev->iftype != NL80211_IFTYPE_P2P_CLIENT)) + wdev->iftype != NL80211_IFTYPE_P2P_CLIENT && + wdev->iftype != NL80211_IFTYPE_AP && + wdev->iftype != NL80211_IFTYPE_P2P_GO)) return; + if (wdev->iftype == NL80211_IFTYPE_STATION || + wdev->iftype == NL80211_IFTYPE_P2P_CLIENT) { if (WARN_ON(!wdev->connected) || - WARN_ON(!ether_addr_equal(wdev->u.client.connected_addr, bssid))) + WARN_ON(!ether_addr_equal(wdev->u.client.connected_addr, peer_addr))) return; + } nl80211_send_port_authorized(wiphy_to_rdev(wdev->wiphy), wdev->netdev, - bssid, td_bitmap, td_bitmap_len); + peer_addr, td_bitmap, td_bitmap_len); } -void cfg80211_port_authorized(struct net_device *dev, const u8 *bssid, +void cfg80211_port_authorized(struct net_device *dev, const u8 *peer_addr, const u8 *td_bitmap, u8 td_bitmap_len, gfp_t gfp) { struct wireless_dev *wdev = dev->ieee80211_ptr; @@ -1304,7 +1311,7 @@ struct cfg80211_event *ev; unsigned long flags; - if (WARN_ON(!bssid)) + if (WARN_ON(!peer_addr)) return; ev = kzalloc(sizeof(*ev) + td_bitmap_len, gfp); @@ -1312,7 +1319,7 @@ return; ev->type = EVENT_PORT_AUTHORIZED; - memcpy(ev->pa.bssid, bssid, ETH_ALEN); + memcpy(ev->pa.peer_addr, peer_addr, ETH_ALEN); ev->pa.td_bitmap = ((u8 *)ev) + sizeof(*ev); ev->pa.td_bitmap_len = td_bitmap_len; memcpy((void *)ev->pa.td_bitmap, td_bitmap, td_bitmap_len); @@ -1338,7 +1345,7 @@ union iwreq_data wrqu; #endif - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); if (WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION && wdev->iftype != NL80211_IFTYPE_P2P_CLIENT)) @@ -1428,7 +1435,7 @@ struct wireless_dev *wdev = dev->ieee80211_ptr; int err; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); /* * If we have an ssid_len, we're trying to connect or are @@ -1534,7 +1541,7 @@ struct wireless_dev *wdev = dev->ieee80211_ptr; int err = 0; - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); kfree_sensitive(wdev->connect_keys); wdev->connect_keys = NULL; @@ -1569,19 +1576,19 @@ container_of(work, struct wireless_dev, disconnect_wk); struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); - wdev_lock(wdev); + wiphy_lock(wdev->wiphy); if (wdev->conn_owner_nlportid) { switch (wdev->iftype) { case NL80211_IFTYPE_ADHOC: - __cfg80211_leave_ibss(rdev, wdev->netdev, false); + cfg80211_leave_ibss(rdev, wdev->netdev, false); break; case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: - __cfg80211_stop_ap(rdev, wdev->netdev, -1, false); + cfg80211_stop_ap(rdev, wdev->netdev, -1, false); break; case NL80211_IFTYPE_MESH_POINT: - __cfg80211_leave_mesh(rdev, wdev->netdev); + cfg80211_leave_mesh(rdev, wdev->netdev); break; case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: @@ -1606,5 +1613,5 @@ } } - wdev_unlock(wdev); + wiphy_unlock(wdev->wiphy); } diff -ruw linux-6.4/net/wireless/sysfs.c linux-6.4-fbx/net/wireless/sysfs.c --- linux-6.4/net/wireless/sysfs.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/sysfs.c 2023-11-07 13:38:44.114258112 +0100 @@ -5,7 +5,7 @@ * * Copyright 2005-2006 Jiri Benc * Copyright 2006 Johannes Berg - * Copyright (C) 2020-2021 Intel Corporation + * Copyright (C) 2020-2021, 2023 Intel Corporation */ #include @@ -36,6 +36,7 @@ SHOW_FMT(index, "%d", wiphy_idx); SHOW_FMT(macaddress, "%pM", wiphy.perm_addr); SHOW_FMT(address_mask, "%pM", wiphy.addr_mask); +SHOW_FMT(dev_port, "%d", wiphy.dev_port); static ssize_t name_show(struct device *dev, struct device_attribute *attr, @@ -70,6 +71,7 @@ &dev_attr_macaddress.attr, &dev_attr_address_mask.attr, &dev_attr_addresses.attr, + &dev_attr_dev_port.attr, &dev_attr_name.attr, NULL, }; @@ -105,14 +107,18 @@ cfg80211_leave_all(rdev); cfg80211_process_rdev_events(rdev); } + cfg80211_process_wiphy_works(rdev, NULL); if (rdev->ops->suspend) ret = rdev_suspend(rdev, rdev->wiphy.wowlan_config); if (ret == 1) { /* Driver refuse to configure wowlan */ cfg80211_leave_all(rdev); cfg80211_process_rdev_events(rdev); + cfg80211_process_wiphy_works(rdev, NULL); ret = rdev_suspend(rdev, NULL); } + if (ret == 0) + rdev->suspended = true; } wiphy_unlock(&rdev->wiphy); rtnl_unlock(); @@ -132,6 +138,8 @@ wiphy_lock(&rdev->wiphy); if (rdev->wiphy.registered && rdev->ops->resume) ret = rdev_resume(rdev); + rdev->suspended = false; + schedule_work(&rdev->wiphy_work); wiphy_unlock(&rdev->wiphy); if (ret) diff -ruw linux-6.4/net/wireless/trace.h linux-6.4-fbx/net/wireless/trace.h --- linux-6.4/net/wireless/trace.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/trace.h 2023-11-07 13:38:44.114258112 +0100 @@ -22,7 +22,7 @@ #define MAXNAME 32 #define WIPHY_ENTRY __array(char, wiphy_name, 32) -#define WIPHY_ASSIGN strlcpy(__entry->wiphy_name, wiphy_name(wiphy), MAXNAME) +#define WIPHY_ASSIGN strscpy(__entry->wiphy_name, wiphy_name(wiphy), MAXNAME) #define WIPHY_PR_FMT "%s" #define WIPHY_PR_ARG __entry->wiphy_name @@ -615,49 +615,47 @@ TRACE_EVENT(rdev_change_beacon, TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, - struct cfg80211_beacon_data *info), + struct cfg80211_ap_update *info), TP_ARGS(wiphy, netdev, info), TP_STRUCT__entry( WIPHY_ENTRY NETDEV_ENTRY __field(int, link_id) - __dynamic_array(u8, head, info ? info->head_len : 0) - __dynamic_array(u8, tail, info ? info->tail_len : 0) - __dynamic_array(u8, beacon_ies, info ? info->beacon_ies_len : 0) - __dynamic_array(u8, proberesp_ies, - info ? info->proberesp_ies_len : 0) - __dynamic_array(u8, assocresp_ies, - info ? info->assocresp_ies_len : 0) - __dynamic_array(u8, probe_resp, info ? info->probe_resp_len : 0) + __dynamic_array(u8, head, info->beacon.head_len) + __dynamic_array(u8, tail, info->beacon.tail_len) + __dynamic_array(u8, beacon_ies, info->beacon.beacon_ies_len) + __dynamic_array(u8, proberesp_ies, info->beacon.proberesp_ies_len) + __dynamic_array(u8, assocresp_ies, info->beacon.assocresp_ies_len) + __dynamic_array(u8, probe_resp, info->beacon.probe_resp_len) ), TP_fast_assign( WIPHY_ASSIGN; NETDEV_ASSIGN; - if (info) { - __entry->link_id = info->link_id; - if (info->head) - memcpy(__get_dynamic_array(head), info->head, - info->head_len); - if (info->tail) - memcpy(__get_dynamic_array(tail), info->tail, - info->tail_len); - if (info->beacon_ies) + __entry->link_id = info->beacon.link_id; + if (info->beacon.head) + memcpy(__get_dynamic_array(head), + info->beacon.head, + info->beacon.head_len); + if (info->beacon.tail) + memcpy(__get_dynamic_array(tail), + info->beacon.tail, + info->beacon.tail_len); + if (info->beacon.beacon_ies) memcpy(__get_dynamic_array(beacon_ies), - info->beacon_ies, info->beacon_ies_len); - if (info->proberesp_ies) + info->beacon.beacon_ies, + info->beacon.beacon_ies_len); + if (info->beacon.proberesp_ies) memcpy(__get_dynamic_array(proberesp_ies), - info->proberesp_ies, - info->proberesp_ies_len); - if (info->assocresp_ies) + info->beacon.proberesp_ies, + info->beacon.proberesp_ies_len); + if (info->beacon.assocresp_ies) memcpy(__get_dynamic_array(assocresp_ies), - info->assocresp_ies, - info->assocresp_ies_len); - if (info->probe_resp) + info->beacon.assocresp_ies, + info->beacon.assocresp_ies_len); + if (info->beacon.probe_resp) memcpy(__get_dynamic_array(probe_resp), - info->probe_resp, info->probe_resp_len); - } else { - __entry->link_id = -1; - } + info->beacon.probe_resp, + info->beacon.probe_resp_len); ), TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", link_id:%d", WIPHY_PR_ARG, NETDEV_PR_ARG, __entry->link_id) @@ -1159,6 +1157,23 @@ __entry->ap_isolate, __entry->ht_opmode) ); +TRACE_EVENT(rdev_inform_bss, + TP_PROTO(struct wiphy *wiphy, struct cfg80211_bss *bss), + TP_ARGS(wiphy, bss), + TP_STRUCT__entry( + WIPHY_ENTRY + MAC_ENTRY(bssid) + CHAN_ENTRY + ), + TP_fast_assign( + WIPHY_ASSIGN; + MAC_ASSIGN(bssid, bss->bssid); + CHAN_ASSIGN(bss->channel); + ), + TP_printk(WIPHY_PR_FMT ", %pM, " CHAN_PR_FMT, + WIPHY_PR_ARG, __entry->bssid, CHAN_PR_ARG) +); + TRACE_EVENT(rdev_set_txq_params, TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, struct ieee80211_txq_params *params), @@ -1306,16 +1321,18 @@ NETDEV_ENTRY MAC_ENTRY(bssid) __field(u16, reason_code) + __field(bool, local_state_change) ), TP_fast_assign( WIPHY_ASSIGN; NETDEV_ASSIGN; MAC_ASSIGN(bssid, req->bssid); __entry->reason_code = req->reason_code; + __entry->local_state_change = req->local_state_change; ), - TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", bssid: %pM, reason: %u", + TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", bssid: %pM, reason: %u, local_state_change:%d", WIPHY_PR_ARG, NETDEV_PR_ARG, __entry->bssid, - __entry->reason_code) + __entry->reason_code, __entry->local_state_change) ); TRACE_EVENT(rdev_disassoc, @@ -1779,15 +1796,16 @@ TRACE_EVENT(rdev_tdls_mgmt, TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, - u8 *peer, u8 action_code, u8 dialog_token, + u8 *peer, int link_id, u8 action_code, u8 dialog_token, u16 status_code, u32 peer_capability, bool initiator, const u8 *buf, size_t len), - TP_ARGS(wiphy, netdev, peer, action_code, dialog_token, status_code, - peer_capability, initiator, buf, len), + TP_ARGS(wiphy, netdev, peer, link_id, action_code, dialog_token, + status_code, peer_capability, initiator, buf, len), TP_STRUCT__entry( WIPHY_ENTRY NETDEV_ENTRY MAC_ENTRY(peer) + __field(int, link_id) __field(u8, action_code) __field(u8, dialog_token) __field(u16, status_code) @@ -1799,6 +1817,7 @@ WIPHY_ASSIGN; NETDEV_ASSIGN; MAC_ASSIGN(peer, peer); + __entry->link_id = link_id; __entry->action_code = action_code; __entry->dialog_token = dialog_token; __entry->status_code = status_code; @@ -1806,11 +1825,12 @@ __entry->initiator = initiator; memcpy(__get_dynamic_array(buf), buf, len); ), - TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", %pM, action_code: %u, " + TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", %pM" + ", link_id: %d, action_code: %u " "dialog_token: %u, status_code: %u, peer_capability: %u " "initiator: %s buf: %#.2x ", WIPHY_PR_ARG, NETDEV_PR_ARG, __entry->peer, - __entry->action_code, __entry->dialog_token, + __entry->link_id, __entry->action_code, __entry->dialog_token, __entry->status_code, __entry->peer_capability, BOOL_TO_STR(__entry->initiator), ((u8 *)__get_dynamic_array(buf))[0]) @@ -2908,7 +2928,7 @@ TRACE_EVENT(cfg80211_send_rx_assoc, TP_PROTO(struct net_device *netdev, - struct cfg80211_rx_assoc_resp *data), + struct cfg80211_rx_assoc_resp_data *data), TP_ARGS(netdev, data), TP_STRUCT__entry( NETDEV_ENTRY @@ -3570,7 +3590,6 @@ TP_STRUCT__entry( WIPHY_ENTRY CHAN_ENTRY - __field(enum nl80211_bss_scan_width, scan_width) __dynamic_array(u8, mgmt, len) __field(s32, signal) __field(u64, ts_boottime) @@ -3580,7 +3599,6 @@ TP_fast_assign( WIPHY_ASSIGN; CHAN_ASSIGN(data->chan); - __entry->scan_width = data->scan_width; if (mgmt) memcpy(__get_dynamic_array(mgmt), mgmt, len); __entry->signal = data->signal; @@ -3589,8 +3607,8 @@ MAC_ASSIGN(parent_bssid, data->parent_bssid); ), TP_printk(WIPHY_PR_FMT ", " CHAN_PR_FMT - "(scan_width: %d) signal: %d, tsb:%llu, detect_tsf:%llu, tsf_bssid: %pM", - WIPHY_PR_ARG, CHAN_PR_ARG, __entry->scan_width, + "signal: %d, tsb:%llu, detect_tsf:%llu, tsf_bssid: %pM", + WIPHY_PR_ARG, CHAN_PR_ARG, __entry->signal, (unsigned long long)__entry->ts_boottime, (unsigned long long)__entry->parent_tsf, __entry->parent_bssid) @@ -3946,6 +3964,21 @@ __entry->enable) ); +TRACE_EVENT(cfg80211_links_removed, + TP_PROTO(struct net_device *netdev, u16 link_mask), + TP_ARGS(netdev, link_mask), + TP_STRUCT__entry( + NETDEV_ENTRY + __field(u16, link_mask) + ), + TP_fast_assign( + NETDEV_ASSIGN; + __entry->link_mask = link_mask; + ), + TP_printk(NETDEV_PR_FMT ", link_mask:%u", NETDEV_PR_ARG, + __entry->link_mask) +); + #endif /* !__RDEV_OPS_TRACE || TRACE_HEADER_MULTI_READ */ #undef TRACE_INCLUDE_PATH diff -ruw linux-6.4/net/wireless/util.c linux-6.4-fbx/net/wireless/util.c --- linux-6.4/net/wireless/util.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/wireless/util.c 2023-11-07 13:38:44.114258112 +0100 @@ -43,8 +43,7 @@ } EXPORT_SYMBOL(ieee80211_get_response_rate); -u32 ieee80211_mandatory_rates(struct ieee80211_supported_band *sband, - enum nl80211_bss_scan_width scan_width) +u32 ieee80211_mandatory_rates(struct ieee80211_supported_band *sband) { struct ieee80211_rate *bitrates; u32 mandatory_rates = 0; @@ -54,15 +53,10 @@ if (WARN_ON(!sband)) return 1; - if (sband->band == NL80211_BAND_2GHZ) { - if (scan_width == NL80211_BSS_CHAN_WIDTH_5 || - scan_width == NL80211_BSS_CHAN_WIDTH_10) - mandatory_flag = IEEE80211_RATE_MANDATORY_G; - else + if (sband->band == NL80211_BAND_2GHZ) mandatory_flag = IEEE80211_RATE_MANDATORY_B; - } else { + else mandatory_flag = IEEE80211_RATE_MANDATORY_A; - } bitrates = sband->bitrates; for (i = 0; i < sband->n_bitrates; i++) @@ -580,6 +574,8 @@ hdrlen += ETH_ALEN + 2; else if (!pskb_may_pull(skb, hdrlen)) return -EINVAL; + else + payload.eth.h_proto = htons(skb->len - hdrlen); mesh_addr = skb->data + sizeof(payload.eth) + ETH_ALEN; switch (payload.flags & MESH_FLAGS_AE) { @@ -1042,7 +1038,6 @@ list_del(&ev->list); spin_unlock_irqrestore(&wdev->event_lock, flags); - wdev_lock(wdev); switch (ev->type) { case EVENT_CONNECT_RESULT: __cfg80211_connect_result( @@ -1064,15 +1059,14 @@ ev->ij.channel); break; case EVENT_STOPPED: - __cfg80211_leave(wiphy_to_rdev(wdev->wiphy), wdev); + cfg80211_leave(wiphy_to_rdev(wdev->wiphy), wdev); break; case EVENT_PORT_AUTHORIZED: - __cfg80211_port_authorized(wdev, ev->pa.bssid, + __cfg80211_port_authorized(wdev, ev->pa.peer_addr, ev->pa.td_bitmap, ev->pa.td_bitmap_len); break; } - wdev_unlock(wdev); kfree(ev); @@ -1122,9 +1116,7 @@ return -EBUSY; dev->ieee80211_ptr->use_4addr = false; - wdev_lock(dev->ieee80211_ptr); rdev_set_qos_map(rdev, dev, NULL); - wdev_unlock(dev->ieee80211_ptr); switch (otype) { case NL80211_IFTYPE_AP: @@ -1136,10 +1128,8 @@ break; case NL80211_IFTYPE_STATION: case NL80211_IFTYPE_P2P_CLIENT: - wdev_lock(dev->ieee80211_ptr); cfg80211_disconnect(rdev, dev, WLAN_REASON_DEAUTH_LEAVING, true); - wdev_unlock(dev->ieee80211_ptr); break; case NL80211_IFTYPE_MESH_POINT: /* mesh should be handled? */ @@ -1646,6 +1636,114 @@ return result / 10000; } +static u32 cfg80211_calculate_bitrate_s1g(struct rate_info *rate) +{ + /* For 1, 2, 4, 8 and 16 MHz channels */ + static const u32 base[5][11] = { + { 300000, + 600000, + 900000, + 1200000, + 1800000, + 2400000, + 2700000, + 3000000, + 3600000, + 4000000, + /* MCS 10 supported in 1 MHz only */ + 150000, + }, + { 650000, + 1300000, + 1950000, + 2600000, + 3900000, + 5200000, + 5850000, + 6500000, + 7800000, + /* MCS 9 not valid */ + }, + { 1350000, + 2700000, + 4050000, + 5400000, + 8100000, + 10800000, + 12150000, + 13500000, + 16200000, + 18000000, + }, + { 2925000, + 5850000, + 8775000, + 11700000, + 17550000, + 23400000, + 26325000, + 29250000, + 35100000, + 39000000, + }, + { 8580000, + 11700000, + 17550000, + 23400000, + 35100000, + 46800000, + 52650000, + 58500000, + 70200000, + 78000000, + }, + }; + u32 bitrate; + /* default is 1 MHz index */ + int idx = 0; + + if (rate->mcs >= 11) + goto warn; + + switch (rate->bw) { + case RATE_INFO_BW_16: + idx = 4; + break; + case RATE_INFO_BW_8: + idx = 3; + break; + case RATE_INFO_BW_4: + idx = 2; + break; + case RATE_INFO_BW_2: + idx = 1; + break; + case RATE_INFO_BW_1: + idx = 0; + break; + case RATE_INFO_BW_5: + case RATE_INFO_BW_10: + case RATE_INFO_BW_20: + case RATE_INFO_BW_40: + case RATE_INFO_BW_80: + case RATE_INFO_BW_160: + default: + goto warn; + } + + bitrate = base[idx][rate->mcs]; + bitrate *= rate->nss; + + if (rate->flags & RATE_INFO_FLAGS_SHORT_GI) + bitrate = (bitrate / 9) * 10; + /* do NOT round down here */ + return (bitrate + 50000) / 100000; +warn: + WARN_ONCE(1, "invalid rate bw=%d, mcs=%d, nss=%d\n", + rate->bw, rate->mcs, rate->nss); + return 0; +} + u32 cfg80211_calculate_bitrate(struct rate_info *rate) { if (rate->flags & RATE_INFO_FLAGS_MCS) @@ -1662,6 +1760,8 @@ return cfg80211_calculate_bitrate_he(rate); if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) return cfg80211_calculate_bitrate_eht(rate); + if (rate->flags & RATE_INFO_FLAGS_S1G_MCS) + return cfg80211_calculate_bitrate_s1g(rate); return rate->legacy; } @@ -1860,6 +1960,35 @@ } EXPORT_SYMBOL(ieee80211_ie_split_ric); +void ieee80211_fragment_element(struct sk_buff *skb, u8 *len_pos, u8 frag_id) +{ + unsigned int elem_len; + + if (!len_pos) + return; + + elem_len = skb->data + skb->len - len_pos - 1; + + while (elem_len > 255) { + /* this one is 255 */ + *len_pos = 255; + /* remaining data gets smaller */ + elem_len -= 255; + /* make space for the fragment ID/len in SKB */ + skb_put(skb, 2); + /* shift back the remaining data to place fragment ID/len */ + memmove(len_pos + 255 + 3, len_pos + 255 + 1, elem_len); + /* place the fragment ID */ + len_pos += 255 + 1; + *len_pos = frag_id; + /* and point to fragment length to update later */ + len_pos++; + } + + *len_pos = elem_len; +} +EXPORT_SYMBOL(ieee80211_fragment_element); + bool ieee80211_operating_class_to_band(u8 operating_class, enum nl80211_band *band) { @@ -1870,6 +1999,7 @@ *band = NL80211_BAND_5GHZ; return true; case 131 ... 135: + case 137: *band = NL80211_BAND_6GHZ; return true; case 81: @@ -2535,12 +2665,12 @@ { struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); - ASSERT_WDEV_LOCK(wdev); + lockdep_assert_wiphy(wdev->wiphy); switch (wdev->iftype) { case NL80211_IFTYPE_AP: case NL80211_IFTYPE_P2P_GO: - __cfg80211_stop_ap(rdev, wdev->netdev, link_id, true); + cfg80211_stop_ap(rdev, wdev->netdev, link_id, true); break; default: /* per-link not relevant */ @@ -2565,12 +2695,10 @@ if (wdev->iftype != NL80211_IFTYPE_AP) return; - wdev_lock(wdev); if (wdev->valid_links) { for_each_valid_link(wdev, link_id) cfg80211_remove_link(wdev, link_id); } - wdev_unlock(wdev); } int cfg80211_remove_virtual_intf(struct cfg80211_registered_device *rdev, diff -ruw linux-6.4/net/xfrm/xfrm_device.c linux-6.4-fbx/net/xfrm/xfrm_device.c --- linux-6.4/net/xfrm/xfrm_device.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/xfrm/xfrm_device.c 2023-11-07 13:38:44.114258112 +0100 @@ -15,6 +15,7 @@ #include #include #include +#include #include #include diff -ruw linux-6.4/net/xfrm/xfrm_interface_core.c linux-6.4-fbx/net/xfrm/xfrm_interface_core.c --- linux-6.4/net/xfrm/xfrm_interface_core.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/xfrm/xfrm_interface_core.c 2023-11-07 13:38:44.114258112 +0100 @@ -33,6 +33,7 @@ #include #include +#include #include #include #include diff -ruw linux-6.4/net/xfrm/xfrm_output.c linux-6.4-fbx/net/xfrm/xfrm_output.c --- linux-6.4/net/xfrm/xfrm_output.c 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/net/xfrm/xfrm_output.c 2023-11-07 13:38:44.114258112 +0100 @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff -ruw linux-6.4/scripts/Makefile.lib linux-6.4-fbx/scripts/Makefile.lib --- linux-6.4/scripts/Makefile.lib 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/scripts/Makefile.lib 2023-05-22 20:06:46.611916789 +0200 @@ -372,7 +372,7 @@ cmd_wrap_S_dtb = { \ symbase=__$(patsubst .%,%,$(suffix $<))_$(subst -,_,$(notdir $*)); \ echo '\#include '; \ - echo '.section .dtb.init.rodata,"a"'; \ + echo '.section .dtb.rodata,"a"'; \ echo '.balign STRUCT_ALIGNMENT'; \ echo ".global $${symbase}_begin"; \ echo "$${symbase}_begin:"; \ diff -ruw linux-6.4/scripts/dtc/include-prefixes/arm64/amlogic/Makefile linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/amlogic/Makefile --- linux-6.4/scripts/dtc/include-prefixes/arm64/amlogic/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/amlogic/Makefile 2023-11-27 19:13:52.958343154 +0100 @@ -1,8 +1,15 @@ # SPDX-License-Identifier: GPL-2.0 +fbx-boards += \ + fbxwmr.dtb \ + fbxwmr-r1.dtb fbxwmr-r2.dtb \ + fbxwmr-r3.dtb fbxwmr-r4.dtb + dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-3.dtb +DTC_FLAGS += -@ +dtb-$(CONFIG_ARCH_MESON) += $(fbx-boards) dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb diff -ruw linux-6.4/scripts/dtc/include-prefixes/arm64/broadcom/Makefile linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/broadcom/Makefile --- linux-6.4/scripts/dtc/include-prefixes/arm64/broadcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/broadcom/Makefile 2023-05-22 20:06:36.535648775 +0200 @@ -11,3 +11,4 @@ subdir-y += bcmbca subdir-y += northstar2 subdir-y += stingray +subdir-y += bcm63xx diff -ruw linux-6.4/scripts/dtc/include-prefixes/arm64/marvell/Makefile linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/marvell/Makefile --- linux-6.4/scripts/dtc/include-prefixes/arm64/marvell/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/marvell/Makefile 2023-05-22 20:06:36.575649839 +0200 @@ -27,3 +27,19 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_dsl_lte.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_pon.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_pcie_pine_pericom.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_pcie_pine_asmedia.dtb + +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp2_ftth_p2p.dtb + +# export symbols in DTBs file to allow overlay usage +DTC_FLAGS += -@ diff -ruw linux-6.4/scripts/dtc/include-prefixes/arm64/qcom/Makefile linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/qcom/Makefile --- linux-6.4/scripts/dtc/include-prefixes/arm64/qcom/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/scripts/dtc/include-prefixes/arm64/qcom/Makefile 2023-11-24 18:39:54.353042707 +0100 @@ -1,204 +1,208 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb -dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb -dtb-$(CONFIG_ARCH_QCOM) += ipq9574-al02-c7.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-acer-a1-724.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-gplus-fl8005a.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e5.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-e7.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-grandmax.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt510.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-gt58.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5x.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-tissot.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-vince.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-kugo.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8956-sony-xperia-loire-suzu.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-huawei-angler-rev-101.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-satsuki.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-sumire.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-suzuran.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-oneplus3t.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-natrium.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8996pro-xiaomi-scorpio.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-cheeseburger.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb -dtb-$(CONFIG_ARCH_QCOM) += msm8998-xiaomi-sagit.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb -dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb4210-rb2.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb -dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb -dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-kb.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r9-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-ti.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel360-wifi.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd-pro.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-evoker-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r1-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-zombie-nvme-lte.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc8280xp-lenovo-thinkpad-x13s.dtb -dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm450-motorola-ali.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c-navigation-mezzanine.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyln.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-lg-judyp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-enchilada.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-samsung-starqltechn.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-ebbg.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium-tianma.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-polaris.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb -dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-bahamut.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8150-sony-xperia-kumano-griffin.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx203.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-sony-xperia-edo-pdx206.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-boe.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8250-xiaomi-elish-csot.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb -dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8094-sony-xperia-kitakami-karin_windy.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8096-db820c.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq5332-mi01.2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq5332-rdp468.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq6018-cp01-c1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq8074-hk01.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq8074-hk10-c1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq8074-hk10-c2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp418.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp433.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp449.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM_FBX_DTB) += fbxgw9r.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-acer-a1-724.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-alcatel-idol347.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-asus-z00l.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-gplus-fl8005a.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-huawei-g7.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-longcheer-l8150.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-longcheer-l8910.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-a3u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-a5u-eur.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-e5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-e7.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-grandmax.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-gt510.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-gt58.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-j5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-j5x.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-samsung-serranove.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-thwc-uf896.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-thwc-ufi001c.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-wingtech-wt88047.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-motorola-potter.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-daisy.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-mido.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-tissot.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8953-xiaomi-vince.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8956-sony-xperia-loire-kugo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8956-sony-xperia-loire-suzu.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-lg-bullhead-rev-10.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-lg-bullhead-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-msft-lumia-octagon-talkman.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8992-xiaomi-libra.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-huawei-angler-rev-101.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-msft-lumia-octagon-cityman.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-ivy.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-karin.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-satsuki.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-sumire.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8994-sony-xperia-kitakami-suzuran.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-oneplus3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-oneplus3t.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-sony-xperia-tone-dora.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-sony-xperia-tone-kagura.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-sony-xperia-tone-keyaki.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996-xiaomi-gemini.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996pro-xiaomi-natrium.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8996pro-xiaomi-scorpio.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-asus-novago-tp370ql.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-fxtec-pro1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-hp-envy-x2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-lenovo-miix-630.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-oneplus-cheeseburger.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-oneplus-dumpling.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-sony-xperia-yoshino-lilac.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-sony-xperia-yoshino-maple.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-sony-xperia-yoshino-poplar.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += msm8998-xiaomi-sagit.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qcs404-evb-1000.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qcs404-evb-4000.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qdu1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb2210-rb1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb4210-rb2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb5165-rb5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qrb5165-rb5-vision-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += qru1000-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8295p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8540p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sa8775p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-coachz-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-homestar-r2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-homestar-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-homestar-r4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-kingoftown.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r1-kb.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r3-kb.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r9.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r9-kb.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-r9-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-r4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-r9.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-lte-parade.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-lte-ti.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-parade.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel-ti.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel360-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pazquel360-wifi.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r2-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-pompom-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-quackingstick-r0.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-quackingstick-r0-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-boe.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-inx.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-wormdingler-rev1-boe-rt5682s.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7180-trogdor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-crd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-crd-pro.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-evoker.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-evoker-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-herobrine-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-villager-r0.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-villager-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-villager-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie-nvme.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-herobrine-zombie-nvme-lte.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-idp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-idp2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc7280-crd-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc8280xp-crd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sc8280xp-lenovo-thinkpad-x13s.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sda660-inforce-ifc6560.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm450-motorola-ali.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-ganges-kirin.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-nile-discovery.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-nile-pioneer.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm630-sony-xperia-nile-voyager.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm632-fairphone-fp3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm632-motorola-ocean.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm636-sony-xperia-ganges-mermaid.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm660-xiaomi-lavender.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm670-google-sargo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-cheza-r1.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-cheza-r2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-cheza-r3.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-db845c.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-db845c-navigation-mezzanine.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-lg-judyln.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-lg-judyp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-oneplus-enchilada.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-oneplus-fajita.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-samsung-starqltechn.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-sony-xperia-tama-akari.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-sony-xperia-tama-akatsuki.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-sony-xperia-tama-apollo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-xiaomi-beryllium-ebbg.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-xiaomi-beryllium-tianma.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-xiaomi-polaris.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm845-shift-axolotl.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm850-lenovo-yoga-c630.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sdm850-samsung-w737.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6115p-lenovo-j606f.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6125-sony-xperia-seine-pdx201.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6125-xiaomi-laurel-sprout.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6350-sony-xperia-lena-pdx213.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm6375-sony-xperia-murray-pdx225.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm7225-fairphone-fp4.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-microsoft-surface-duo.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-sony-xperia-kumano-bahamut.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8150-sony-xperia-kumano-griffin.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-sony-xperia-edo-pdx203.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-sony-xperia-edo-pdx206.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-xiaomi-elish-boe.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8250-xiaomi-elish-csot.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-microsoft-surface-duo2.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-sony-xperia-sagami-pdx214.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8350-sony-xperia-sagami-pdx215.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-hdk.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-sony-xperia-nagara-pdx223.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8450-sony-xperia-nagara-pdx224.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8550-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM_DTB) += sm8550-qrd.dtb diff -ruw linux-6.4/scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h linux-6.4-fbx/scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h --- linux-6.4/scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h 2023-05-22 20:06:44.879870719 +0200 @@ -803,6 +803,18 @@ #define BTN_TRIGGER_HAPPY39 0x2e6 #define BTN_TRIGGER_HAPPY40 0x2e7 +#define KEY_APP_TV 0x2f1 +#define KEY_APP_REPLAY 0x2f2 +#define KEY_APP_VIDEOCLUB 0x2f3 +#define KEY_APP_WHATSON 0x2f4 +#define KEY_APP_RECORDS 0x2f5 +#define KEY_APP_MEDIA 0x2f6 +#define KEY_APP_YOUTUBE 0x2f7 +#define KEY_APP_RADIOS 0x2f8 +#define KEY_APP_CANALVOD 0x2f9 +#define KEY_APP_PIP 0x2fa +#define KEY_APP_NETFLIX 0x2fb + /* We avoid low common keys in module aliases so they don't get huge. */ #define KEY_MIN_INTERESTING KEY_MUTE #define KEY_MAX 0x2ff diff -ruw linux-6.4/scripts/gen_autoksyms.sh linux-6.4-fbx/scripts/gen_autoksyms.sh --- linux-6.4/scripts/gen_autoksyms.sh 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/scripts/gen_autoksyms.sh 2023-05-22 20:06:46.643917640 +0200 @@ -22,7 +22,7 @@ output_file="$1" -needed_symbols= +needed_symbols=$(sed -n 's/^CONFIG_UNUSED_KSYMS_WHITELIST_SYMS=\(.*\)$/\1/p' include/config/auto.conf) # Special case for modversions (see modpost.c) if grep -q "^CONFIG_MODVERSIONS=y$" include/config/auto.conf; then diff -ruw linux-6.4/sound/soc/kirkwood/Kconfig linux-6.4-fbx/sound/soc/kirkwood/Kconfig --- linux-6.4/sound/soc/kirkwood/Kconfig 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/sound/soc/kirkwood/Kconfig 2023-02-27 19:50:24.596313402 +0100 @@ -16,3 +16,8 @@ Say Y if you want to add support for SoC audio on the Armada 370 Development Board. +config SND_KIRKWOOD_SOC_FBXGW2R + tristate "Soc Audio support for fbxgw2r" + depends on SND_KIRKWOOD_SOC && MACH_FBXGW2R && I2C + select SND_KIRKWOOD_SOC_I2S + select SND_SOC_CS42L52 diff -ruw linux-6.4/sound/soc/kirkwood/Makefile linux-6.4-fbx/sound/soc/kirkwood/Makefile --- linux-6.4/sound/soc/kirkwood/Makefile 2023-06-26 01:29:58.000000000 +0200 +++ linux-6.4-fbx/sound/soc/kirkwood/Makefile 2023-02-27 19:50:24.596313402 +0100 @@ -6,3 +6,6 @@ snd-soc-armada-370-db-objs := armada-370-db.o obj-$(CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB) += snd-soc-armada-370-db.o + +snd-soc-fbxgw2r-objs := kirkwood-fbxgw2r.o +obj-$(CONFIG_SND_KIRKWOOD_SOC_FBXGW2R) += snd-soc-fbxgw2r.o diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./Makefile linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/Makefile --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/Makefile 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,26 @@ +board-dtbs = \ + fbxgw8r-board-00.dtb \ + fbxgw8r-board-01.dtb \ + fbxgw8r-board-02.dtb \ + fbxgw8r-board-03.dtb \ + fbxgw8r-board-04.dtb + +dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158ref1d.dtb fbxgw8r.dtb $(board-dtbs) + +always-y := $(dtb-y) +always-$(CONFIG_ARCH_BCMBCA) += fbxgw8r_dtbs + +subdir-y := $(dts-dirs) +clean-files := *.dtb fbxgw8r_dtbs + +cmd_dtbs = ./scripts/dtbs.sh $@ $^ +quiet_cmd_dtbs = DTBS $@ + +$(obj)/fbxgw8r_dtbs: $(addprefix $(obj)/,$(board-dtbs)) + $(call cmd,dtbs) + +# export symbols in DTBs file to allow overlay usage +DTC_FLAGS += -@ + +dtb-$(CONFIG_ARCH_BCMBCA) += fbxgw8r_pcie_pine_asmedia.dtb +dtb-$(CONFIG_ARCH_BCMBCA) += fbxgw8r_pcie_pine_dualband_noswitch.dtb diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm63158.dtsi linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm63158.dtsi --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm63158.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm63158.dtsi 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,1126 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define USE_PSCI // comment when booting on broadcom CFE. + +/* + * uncomment when xrdp reserved memory is needed for debugging. + */ +// #define USE_RDP_RESERVED_TM + +#define SDIO_EMMC_SPI 95 +#define SPU_GMAC_SPI 75 +#define HS_SPI_SPI 37 +#define BSC_I2C0_SPI 82 +#define BSC_I2C1_SPI 83 +#define PCIE0_SPI 60 +#define PCIE1_SPI 61 +#define PCIE2_SPI 62 +#define PCIE3_SPI 63 +#define HS_UART_SPI 34 +#define XHCI_SPI 123 +#define OHCI0_SPI 124 +#define EHCI0_SPI 125 +#define OHCI1_SPI 121 +#define EHCI1_SPI 122 + +#define DRAM_BASE 0x0 +#define DRAM_DEF_SIZE 0x08000000 + +/memreserve/ 0x00000000 0x00020000; + +/ { + model = "Broadcom-v8A"; + compatible = "brcm,brcm-v8A"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + +#ifdef USE_PSCI + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +#define CPU_ENABLE_METHOD "psci" +#else +#define CPU_ENABLE_METHOD "spin-table" +#endif + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + skip-enumeration; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + }; + B53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = CPU_ENABLE_METHOD; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&L2_0>; + }; + B53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = CPU_ENABLE_METHOD; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&L2_0>; + }; + B53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = CPU_ENABLE_METHOD; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&B53_0>, + <&B53_1>, + <&B53_2>, + <&B53_3>; + }; + + soc_dram: memory@00000000 { + device_type = "memory"; + reg = <0x00000000 DRAM_BASE 0x0 DRAM_DEF_SIZE>; + + // this is overwritten by bootloader with correct value + brcm,ddr-mcb = <0x4142b>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf@0x10000000 { + no-map; + reg = <0x0 0x10000000 0x0 0x00100000>; + }; + optee@0x10800000 { + no-map; + reg = <0x0 0x10800000 0x0 0x00400000>; + }; + + optee-shared-area@0x11000000 { + no-map; + reg = <0x0 0x11000000 0x0 0x00100000>; + }; + dsl_reserved: dsl_reserved { + compatible = "shared-dma-pool"; + /* + * only 3MB are actually used, but because of pointer alignment + * arithmetics done by the driver, they need to be at the end of an + * 8MB aligned region, must be at an address lower than 256M too + */ + size = <0x0 0x00800000>; + alignment = <0x0 0x00800000>; + alloc-ranges = <0x0 0x0 0x0 0x10000000>; + no-map; + no-cache; + }; +#ifdef USE_RDP_RESERVED_TM + rdp_reserved_tm: rdp_reserved_tm { + compatible = "shared-dma-pool"; + size = <0x0 0x00800000>; + alloc-ranges = <0x0 0x0 0x0 0x10000000>; + no-map; + no-cache; + }; +#endif + }; + + uartclk: uartclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + spiclk: spiclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <(200 * 1000 * 1000)>; + }; + + pcie01: pcidual@80040000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80040000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xC0000000 0 0xC0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE01>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE0>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE0_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <2>; + brcm,dram = <&soc_dram>; + }; + + pcie0: pci@80040000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80040000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xC0000000 0 0xC0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE0>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE0>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE0_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + brcm,dram = <&soc_dram>; + }; + + pcie1: pci@80050000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80050000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xD0000000 0 0xD0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE1>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE0>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE1_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + brcm,dram = <&soc_dram>; + }; + + pcie2: pci@80060000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80060000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xE0000000 0 0xE0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE2>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE2>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE2_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + brcm,dram = <&soc_dram>; + }; + + pcie3: pci@80070000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80070000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xB0000000 0 0xB0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE3>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE3>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE3_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x80000000 0x0 0x04000000>; + + xtm: xtm@80130000 { + compatible = "brcm,bcm63158-xtm"; + status = "disabled"; + + interrupts = ; + reg = <0x0 0x130000 0x0 0x4000>; + + xdsl-phy = <&xdsl_phy>; + xtm-runner,xrdp = <&xrdp>; + }; + + memc: memc@0x80180000 { + compatible = "brcm,bcm63158-memc"; + reg = <0x0 0x180000 0x0 0x40000>; + }; + + pmc: pmc@80200000 { + compatible = "brcm,bcm63158-pmc"; + reg = <0x0 0x200000 0x0 0x10000>; + #reset-cells = <1>; + }; + + procmon: procmon@80280000 { + compatible = "brcm,bcm63158-procmon"; + reg = <0x0 0x280000 0x0 0x100>; + #procmon-cells = <1>; + }; + + ubus4: ubus4@80300000 { + compatible = "brcm,bcm63158-ubus4"; + reg = <0x0 0x03000000 0x0 0x00500000>, + <0x0 0x10a0400 0x0 0x400>; + reg-names = "master-config", "coherency-config"; + #ubus-cells = <1>; + brcm,dram = <&soc_dram>; + }; + + sf2: sf2@80400000 { + compatible = "brcm,bcm63158-sf2"; + reg = <0x0 0x400000 0x0 0x80000>, + <0x0 0x480000 0x0 0x500>, + <0x0 0x4805c0 0x0 0x10>, + <0x0 0x480600 0x0 0x200>, + <0x0 0x480800 0x0 0x500>; + reg-names = "core", "reg", "mdio", "fcb", "acb"; + resets = <&pmc PMC_R_SF2>; + reset-names = "sf2"; + status = "disabled"; + + sf2,qphy-base-id = <1>; + sf2,sphy-phy-id = <5>; + sf2,serdes-phy-id = <6>; + + leds-top = <&leds_top_syscon>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sf2_port0: port@0 { + // this is a normal port + reg = <0>; + status = "disabled"; + phy-handle = <&sf2_qphy0>; + phy-connection-type = "gmii"; + }; + + sf2_port1: port@1 { + // this is a normal port + reg = <1>; + status = "disabled"; + phy-handle = <&sf2_qphy1>; + phy-connection-type = "gmii"; + }; + + sf2_port2: port@2 { + // this is a normal port + reg = <2>; + status = "disabled"; + phy-handle = <&sf2_qphy2>; + phy-connection-type = "gmii"; + }; + + sf2_port3: port@3 { + // this is a normal port + reg = <3>; + status = "disabled"; + /* 0: quad phy3, 1: rgmii2 */ + mux1-in-port = <0>; + phy-handle = <&sf2_qphy3>; + phy-connection-type = "gmii"; + }; + + sf2_port4: port@4 { + // this is a normal port + reg = <4>; + status = "disabled"; + /* default config is xbar to sphy */ + xbar-in-port = <2>; + phy-handle = <&sf2_sphy>; + phy-connection-type = "gmii"; + }; + + sf2_port5: port@5 { + // this is a CPU port + reg = <5>; + status = "disabled"; + phy-connection-type = "internal"; + ethernet = <&runner_unimac1>; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + sf2_port6: port@6 { + // this is a normal port + reg = <6>; + status = "disabled"; + xbar-in-port = <1>; + /* default config is xbar to serdes */ + phy-connection-type = "sgmii"; + }; + + sf2_port7: port@7 { + // this is a CPU port + reg = <7>; + status = "disabled"; + ethernet = <&runner_unimac2>; + phy-connection-type = "internal"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + sf2_port8: port@8 { + // this is a CPU port + reg = <8>; + status = "disabled"; + /* 0: system port, 1: unimac bbh */ + mux2-in-port = <1>; + + dsa,def-cpu-port; + //ethernet = <&systemport>; + ethernet = <&runner_unimac0>; + + phy-connection-type = "internal"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + }; + + sf2,wan-port-config { + status = "disabled"; + xbar-in-port = <0>; + }; + + sf2,mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* XXX: depends on sf2,qphy-base-id */ + sf2_qphy0: ethernetphy@1 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <1>; + }; + sf2_qphy1: ethernet-phy@2 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <2>; + }; + sf2_qphy2: ethernet-phy@3 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <3>; + }; + sf2_qphy3: ethernet-phy@4 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <4>; + }; + /* XXX: depends on sf2,sphy-base-id */ + sf2_sphy: ethernet-phy@5 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <5>; + }; + }; + }; + + systemport: systemport@80490000 { + compatible = "brcm,systemport-63158"; + reg = <0x0 0x490000 0x0 0x4650>; + local-mac-address = [ 00 07 CB 00 00 FE ]; + interrupts = , + ; + status = "disabled"; + dma-coherent; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + xdsl_phy: xdsl-phy@80650000 { + compatible = "brcm,bcm63158-xdsl-phy"; + status = "disabled"; + + memory-region = <&dsl_reserved>; + interrupts = ; + reg = <0x0 0x650000 0x0 0x20000>, + <0x0 0x800000 0x0 0xe0000>, + <0x0 0x9A0000 0x0 0x660000>; + reg-names = "phy", "lmem", "xmem"; + + pinctrl-0 = <&ld0_pins>; + pinctrl-names = "default"; + + ubus = <&ubus4 UBUS_PORT_ID_DSLCPU>, + <&ubus4 UBUS_PORT_ID_DSL>; + + /* + * this is used by dsldiags, but unfortunately + * lying outside the axi space, in the ubus + * space. + */ + perf-base = <0xff800000>; + perf-size = <0x10>; + }; + + gic: interrupt-controller@81000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x1001000 0 0x1000>, + <0x0 0x1002000 0 0x2000>; + }; + + usb: usb@8000d000 { + status = "disabled"; + compatible = "brcm,bcm63158-usb"; + + reg = <0x0 0xd000 0x0 0x1000>, + <0x0 0xc200 0x0 0x100>, + <0x0 0xc300 0x0 0x100>, + <0x0 0xc400 0x0 0x100>, + <0x0 0xc500 0x0 0x100>, + <0x0 0xc600 0x0 0x100>; + reg-names = "xhci", "usb-control", "ehci0", + "ohci0", "ehci1", "ohci1"; + dma-coherent; + + interrupts = , + , + , + , + ; + interrupt-names = "xhci", "ehci0", "ohci0", + "ehci1", "ohci1"; + + resets = <&pmc PMC_R_USBH>; + reset-names = "xhci-pmc-reset"; + + ubus = <&ubus4 UBUS_PORT_ID_USB>; + }; + + xrdp: xrdp@82000000 { + compatible = "brcm,bcm63158-xrdp"; + reg = <0x0 0x2000000 0x0 0x1000000>, + <0x0 0x0170000 0x0 0x10000>; + reg-names = "core", "wan_top"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "fpm", + "hash", + "qm", + "dsptchr", + "sbpm", + "runner0", + "runner1", + "runner2", + "runner3", + "runner4", + "runner5", + "queue0", + "queue1", + "queue2", + "queue3", + "queue4", + "queue5", + "queue6", + "queue7", + "queue8", + "queue9", + "queue10", + "queue11", + "queue12", + "queue13", + "queue14", + "queue15", + "queue16", + "queue17", + "queue18", + "queue19", + "queue20", + "queue21", + "queue22", + "queue23", + "queue24", + "queue25", + "queue26", + "queue27", + "queue28", + "queue29", + "queue30", + "queue31"; + +#ifdef USE_RDP_RESERVED_TM + memory-region = <&rdp_reserved_tm>; +#endif + resets = <&pmc PMC_R_XRDP>; + reset-names = "rdp"; + ubus = <&ubus4 UBUS_PORT_ID_QM>, + <&ubus4 UBUS_PORT_ID_DQM>, + <&ubus4 UBUS_PORT_ID_NATC>, + <&ubus4 UBUS_PORT_ID_DMA0>, + <&ubus4 UBUS_PORT_ID_RQ0>, + <&ubus4 UBUS_PORT_ID_SWH>; + }; + + runner_unimac0: runner-unimac0 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-unimac"; + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,bbh = <0>; + dma-coherent; + + phy-mode = "gmii"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + runner_unimac1: runner-unimac1 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-unimac"; + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,bbh = <1>; + dma-coherent; + + phy-mode = "gmii"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + runner_unimac2: runner-unimac2 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-unimac"; + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,bbh = <2>; + dma-coherent; + + phy-mode = "gmii"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + runner_xport0: runner-xport0 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-xport"; + reg = <0x0 0x00144000 0x0 0x100>, + <0x0 0x00138000 0x0 0x6fff>, + <0x0 0x00147800 0x0 0xe80>, + <0x0 0x00140000 0x0 0x3fff>; + reg-names = "wan_top", "xport", "xlif", "epon"; + dma-coherent; + + resets = <&pmc PMC_R_WAN_AE>; + reset-names = "wan_ae"; + + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,xport-pon-bbh = <3>; + enet-runner,xport-ae-bbh = <4>; + + //phy-mode = "1000base-x"; + phy-mode = "10gbase-r"; + managed = "in-band-status"; + }; + }; + + ubus@ff800000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x62000>; + + leds_top_syscon: system-controller@ff800800 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x800 0x0 0x100>; + }; + + sdhci: sdhci@ff810000 { + status = "disabled"; + compatible = "brcm,bcm63xx-sdhci"; + reg = <0x0 0x00010000 0x0 0x100>; + interrupts = ; + no-1-8v; + bus-width = <8>; + }; + + arm_serial0: serial@ff812000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x12000 0x0 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + arm_serial2: serial@ff814000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x14000 0x0 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + timer: timer@400 { + compatible = "syscon", "brcm,bcm63158-timer"; + reg = <0x0 0x400 0x0 0x94>, + <0x0 0x5a03c 0x0 0x4>; + reg-names = "timer", "top-reset-status"; + interrupts = ; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x8c>; + mask = <1>; + }; + + pinctrl: pinctrl@500 { + compatible = "brcm,bcm63158-pinctrl"; + reg = <0x0 0x500 0x0 0x60>, + <0x0 0x20 0x0 0x2c>; + reg-names = "gpio", "irq"; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + /* just for ref, they are hardcoded in driver too */ + interrupts = , + , + , + , + , + , + , + ; + + emmc_pins: emmc-pins-0 { + emmc-d0 { + pinmux = ; + }; + emmc-d1 { + pinmux = ; + }; + emmc-d2 { + pinmux = ; + }; + emmc-d3 { + pinmux = ; + }; + emmc-d4 { + pinmux = ; + }; + emmc-d5 { + pinmux = ; + }; + emmc-d6 { + pinmux = ; + }; + emmc-d7 { + pinmux = ; + }; + emmc-clk { + pinmux = ; + }; + emmc-cmd { + pinmux = ; + }; + }; + + spi_pins: spi-pins { + spi-clk { + pinmux = ; + }; + spi-mosi { + pinmux = ; + }; + spi-miso { + pinmux = ; + }; + + /* + * board DTS will have to specify SPI + * SS pins as required. + */ + }; + + i2c0_pins: i2c0-pins { + i2c-sda { + pinmux = ; + }; + i2c-scl { + pinmux = ; + }; + }; + + i2c1_pins: i2c1-pins { + i2c-sda { + pinmux = ; + }; + i2c-scl { + pinmux = ; + }; + }; + + pcie0_pins: pcie0-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcie1_pins: pcie1-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcie2_pins: pcie2-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcie3_pins: pcie3-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcm_pins: pcm-pins { + pcm-clk { + pinmux = ; + }; + pcm-fsync { + pinmux = ; + }; + pcm-sdin { + pinmux = ; + }; + pcm-sdout { + pinmux = ; + }; + }; + + hs_uart_pins: hs-uart-pins { + hs-uart-sout { + pinmux = ; + }; + hs-uart-sin { + pinmux = ; + }; + hs-uart-cts { + pinmux = ; + }; + hs-uart-rts { + pinmux = ; + }; + }; + + usb01_pins: usb01-pins { + pwr0-en { + pinmux = ; + }; + pwr0-fault { + pinmux = ; + }; + pwr1-en { + pinmux = ; + }; + pwr1-fault { + pinmux = ; + }; + }; + + usb0_pins: usb0-pins { + pwr0-en { + pinmux = ; + }; + pwr0-fault { + pinmux = ; + }; + }; + + usb1_pins: usb1-pins { + pwr0-en { + pinmux = ; + }; + pwr0-fault { + pinmux = ; + }; + }; + + ld0_pins: ld0-pins { + ld0_pwr_up { + pinmux = ; + }; + + ld0_din { + pinmux = ; + }; + + ld0_dclk { + pinmux = ; + }; + }; + + ld1_pins: ld1-pins-0 { + ld1_pwr_up { + pinmux = ; + }; + + ld1_din { + pinmux = ; + }; + + ld1_dclk { + pinmux = ; + }; + }; + + gphy01_link_act_leds: gphy01-link-act-leds { + gphy0_link_act_led { + pinmux = ; + }; + gphy1_link_act_led { + pinmux = ; + }; + }; + + sfp_rogue0_pins: sfp-rogue0-pins { + sfp_rogue0_in { + pinmux = ; + }; + }; + + sfp_rogue1_pins: sfp-rogue1-pins { + sfp_rogue1_in { + pinmux = ; + }; + }; + sfp_rs0_gpio_pins: sfp-rs0-gpio { + sfp_rogue1_rs0 { + pinmux = ; + }; + }; + }; + + hs_spim: spi@1000 { + status = "disabled"; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x0 0x1000 0x0 0x600>; + interrupts = ; + clocks = <&spiclk>; + clock-names = "hsspi"; + #address-cells = <1>; + #size-cells = <0>; + }; + + hs_uart: hs-uart@10400 { + status = "disabled"; + compatible = "brcm,bcm63xx-hs-uart"; + reg = <0x0 0x00010400 0x0 0x1e0>; + interrupts = ; + clocks = <&uartclk>; + }; + + i2c_bsc0: i2c@2100 { + status = "disabled"; + compatible = "brcm,brcmper-i2c"; + reg = <0x0 0x2100 0x0 0x60>; + interrupts = ; + }; + + i2c_bsc1: i2c@5a800 { + status = "disabled"; + compatible = "brcm,brcmper-i2c"; + reg = <0x0 0x5a800 0x0 0x60>; + interrupts = ; + }; + + bcm_pcm: bcm_pcm@60000 { + status = "disabled"; + compatible = "brcm,bcm63158-pcm"; + reg = <0x0 0x60000 0x0 0x2000>; + interrupts = , + , + ; + interrupt-names = "pcm", "dma0", "dma1"; + }; + + bcm63158_cpufreq { + compatible = "brcm,bcm63158-cpufreq"; + pmc = <&pmc>; + }; + }; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm963158ref1d.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm963158ref1d.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm963158ref1d.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm963158ref1d.dts 2023-03-09 15:06:11.332233370 +0100 @@ -0,0 +1,331 @@ +/* + * Broadcom BCM63158 Reference Board REF1 DTS + */ + +/dts-v1/; + +#include "bcm63158.dtsi" + +/ { + compatible = "brcm,BCM963158REF1", "brcm,bcm63158"; + model = "Broadcom BCM963158REF1"; + + chosen { + bootargs = "console=ttyAMA0,115200"; + stdout-path = &arm_serial0; + }; + + reserved-memory { + ramoops@3fff0000 { + compatible = "ramoops"; + /* RAM top - 64k */ + reg = <0x0 0x3fff0000 0x0 (64 * 1024)>; + record-size = <(64 * 1024)>; + ecc-size = <16>; + no-dump-oops; + }; + }; + + bcm963158ref1d-fbxgpio { + compatible = "fbx,fbxgpio"; + + wps-button { + gpio = <&pinctrl 41 0>; + input; + }; + dsl0-link-led { + gpio = <&pinctrl 18 0>; + output-low; + }; + + sfp-ae-pwren { + gpio = <&pinctrl 3 0>; + output-low; + }; + sfp-ae-rs0 { + gpio = <&pinctrl 40 0>; + input; + }; + sfp-ae-rs1 { + gpio = <&pinctrl 12 0>; + output-low; + }; + + sfp-ae-presence { + gpio = <&pinctrl 9 0>; + input; + }; + sfp-ae-rxlos { + gpio = <&pinctrl 8 0>; + input; + }; + + sfp-sgmii-presence { + gpio = <&pinctrl 20 0>; + input; + }; + sfp-sgmii-rxlos { + gpio = <&pinctrl 21 0>; + input; + }; + }; + + i2c0_gpio: i2c0-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 24 0 /* sda */ + &pinctrl 25 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1_gpio: i2c1-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 15 0 /* sda */ + &pinctrl 16 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&arm_serial0 { + status = "okay"; +}; + +&sf2 { + status = "okay"; +}; + +&sf2_port0 { + status = "okay"; + label = "swp1"; +}; + +&sf2_port1 { + status = "okay"; + label = "swp2"; +}; + +&sf2_port2 { + status = "okay"; + label = "swp3"; +}; + +&sf2_port3 { + status = "okay"; + label = "swp4"; +}; + +&sf2_port4 { + status = "okay"; + label = "swp5"; +}; + +&sf2_port8 { + status = "okay"; +}; + +&sf2_qphy0 { + status = "okay"; +}; + +&sf2_qphy1 { + status = "okay"; +}; + +&sf2_qphy2 { + status = "okay"; +}; + +&sf2_qphy3 { + status = "okay"; +}; + +&sf2_sphy { + status = "okay"; +}; + +&systemport { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&sdhci { + status = "okay"; + + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + partitions-main { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%d"; + + bank0@0 { + label = "bank0"; + reg = /bits/64 <0 (32 * 1024 * 1024)>; + read-only; + }; + + bank1@0 { + label = "bank1"; + reg = /bits/64 <(-1) (256 * 1024 * 1024)>; + }; + + nvram@0 { + label = "nvram"; + reg = /bits/64 <(-1) (4 * 1024 * 1024)>; + }; + + config@0 { + label = "config"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + new-bank0@0 { + label = "new_bank0"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + userdata@0 { + label = "userdata"; + reg = /bits/64 <(-1) (-1)>; + }; + }; + + + partitions-boot { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%dboot0"; + + cfe@0 { + label = "cfe"; + reg = /bits/64 <0 (1 * 1024 * 1024)>; + read-only; + }; + + serial@0 { + label = "fbxserial"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + + fbxboot@0 { + label = "fbxboot"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + }; +}; + +&spi_pins { + spi-ss0 { + pinmux = ; + }; + spi-ss1 { + pinmux = ; + }; +}; + +&hs_spim { + status = "okay"; + num-cs = <2>; + broadcom,dummy-cs = <2>; + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + serial-flash@0 { + compatible = "m25p80"; + reg = <0>; + spi-max-frequency = <(50 * 1000 * 1000)>; + label = "serial-flash"; + }; + + /* TO TEST SLAC */ + /* + spi-slac@1 { + compatible = "microsemi,le9641"; + reg = <1>; + spi-max-frequency = <(1 * 1000 * 1000)>; + }; + */ + + /* TO TEST LCD */ + /* + ssd1320@1 { + compatible = "solomon,ssd1320"; + reg = <1>; + spi-max-frequency = <(9 * 1000 * 1000)>; + ssd1320,width = <160>; + ssd1320,height = <100>; + ssd1320,segs-hw-skip = <0>; + ssd1320,coms-hw-skip = <30>; + ssd1320,rotate = <180>; + ssd1320,watchdog = <300>; + ssd1320,data-select-gpio = <&pinctrl 14 GPIO_ACTIVE_HIGH>; + ssd1320,reset-gpio = <&pinctrl 4 GPIO_ACTIVE_HIGH>; + }; + */ +}; + +&pcie01 { + status = "okay"; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie2 { + status = "okay"; + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; +}; + + +&pcie3 { + status = "okay"; + pinctrl-0 = <&pcie3_pins>; + pinctrl-names = "default"; +}; + +&xdsl_phy { + status = "okay"; + + pinctrl-0 = <&ld0_pins>, <&ld1_pins>; + pinctrl-names = "default"; + + afe-id-0 = <(BCM63XX_XDSLPHY_AFE_CHIP_CH0 | + BCM63XX_XDSLPHY_AFE_LD_6304 | + BCM63XX_XDSLPHY_AFE_FE_ANNEXA | + BCM63XX_XDSLPHY_AFE_FE_REV_6304_REV_12_4_60 | + BCM63XX_XDSLPHY_AFE_FE_RNC)>; + + afe-id-1 = <(BCM63XX_XDSLPHY_AFE_CHIP_CH1 | + BCM63XX_XDSLPHY_AFE_LD_6304 | + BCM63XX_XDSLPHY_AFE_FE_ANNEXA | + BCM63XX_XDSLPHY_AFE_FE_REV_6304_REV_12_4_60 | + BCM63XX_XDSLPHY_AFE_FE_RNC)>; +}; + +/* TO TEST TELEPHONY */ +/* +&bcm_pcm { + status = "okay"; + pinctrl-0 = <&pcm_pins>; + pinctrl-names = "default"; +}; +*/ + +&usb { + status = "okay"; + + pinctrl-0 = <&usb01_pins>; + pinctrl-names = "default"; + + brcm,pwren-low; + brcm,pwrflt-low; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-00.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-00.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-00.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-00.dts 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,14 @@ +/* + * Freebox FBXGW8R Board DTS, board ID 0x00 + */ +/dts-v1/; + +#include "fbxgw8r-common.dtsi" +#include "fbxgw8r-common-nopmu.dtsi" +#include "fbxgw8r-phy-aquantia.dtsi" + +/ { + compatible = "freebox,fbxgw8r-board-00", "freebox,fbxgw8r", + "brcm,bcm63158"; + cfe-v2.4-work-around-padding; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-01.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-01.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-01.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-01.dts 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,17 @@ +/* + * Freebox FBXGW8R Board DTS, board ID 0x01 + * + * With Realtek PHY 2.5G phy replacing the Aquantia 2.5G PHY, at + * address 0x6 (protos) or 0x7 (final version). + */ +/dts-v1/; + +#include "fbxgw8r-common.dtsi" +#include "fbxgw8r-common-nopmu.dtsi" +#include "fbxgw8r-phy-realtek.dtsi" + +/ { + compatible = "freebox,fbxgw8r-board-01", "freebox,fbxgw8r", + "brcm,bcm63158"; + cfe-v2.4-work-around-padding; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-02.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-02.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-02.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-02.dts 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,14 @@ +/* + * Freebox FBXGW8R Board DTS, board ID 0x02, same as 0x00 but with external + * PMU (only for power-btn/rtc & leds) and wifi 7 + */ +/dts-v1/; + +#include "fbxgw8r-common.dtsi" +#include "fbxgw8r-common-external-pmu.dtsi" +#include "fbxgw8r-phy-aquantia.dtsi" + +/ { + compatible = "freebox,fbxgw8r-board-02", "freebox,fbxgw8r", + "brcm,bcm63158"; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-03.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-03.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-03.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-03.dts 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,14 @@ +/* + * Freebox FBXGW8R Board DTS, board ID 0x02, same as 0x01 but with external + * PMU (only for power-btn/rtc & leds) and wifi 7 + */ +/dts-v1/; + +#include "fbxgw8r-common.dtsi" +#include "fbxgw8r-common-external-pmu.dtsi" +#include "fbxgw8r-phy-realtek.dtsi" + +/ { + compatible = "freebox,fbxgw8r-board-03", "freebox,fbxgw8r", + "brcm,bcm63158"; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-04.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-04.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-board-04.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-board-04.dts 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,16 @@ +/* + * Freebox FBXGW8R Board DTS, board ID 0x04 + * + * With Realtek PHY 2.5G phy, DDR4 & fbxpmu, dual pci express, fbxpmu + * based keypad. + */ +/dts-v1/; + +#include "fbxgw8r-common.dtsi" +#include "fbxgw8r-common-onboard-pmu.dtsi" +#include "fbxgw8r-phy-realtek.dtsi" + +/ { + compatible = "freebox,fbxgw8r-board-04", "freebox,fbxgw8r", + "brcm,bcm63158"; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common-external-pmu.dtsi linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common-external-pmu.dtsi --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common-external-pmu.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common-external-pmu.dtsi 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,271 @@ +/* + * common dtsi file for fbxgw8r for boards with on-board PMU, wifi 7 + */ +/ { + powerbtn { + compatible = "gpio-keys"; + autorepeat = <0>; + + powerbtn { + label = "power"; + linux,code = ; + gpios = <&fbxpmu_gpio_expander 4 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + }; + + dgasp { + compatible = "misc,dgasp"; + interrupt-parent = <&pinctrl>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + + toreset-gpios = <&pinctrl 99 GPIO_ACTIVE_HIGH>; /* w-enable-2 */ + }; +}; + +&i2c1_gpio { + adt7475@2e { + compatible = "adi,adt7475"; + reg = <0x2e>; + }; +}; + +&pinctrl { + gpio-line-names = "", /* 0 */ + "", /* 1 */ + "", /* 2 */ + "bt-rst", /* 3 */ + "", /* 4 */ + "", /* 5 */ + "", /* 6 */ + "", /* 7 */ + "", /* 8 */ + "wan-sfp-presence", /* 9 */ + "wan-sfp-rxlos", /* 10 */ + "wan-sfp-txfault", /* 11 */ + "wan-sfp-rs1", /* 12 */ + "", /* 13 */ + "wan-sfp-pwren", /* 14 */ + "", /* 15 */ + "", /* 16 */ + "", /* 17 */ + "", /* 18 */ + "i2c-int", /* 19 */ + "pmu-dyinggasp-int", /* 20 */ + "fan-int", /* 21 */ + "", /* 22 */ + "fxs-int", /* 23 */ + "", /* 24 */ + "", /* 25 */ + "phy25-int", /* 26 */ + "phy25-reset", /* 27 */ + "", /* 28 */ + "", /* 29 */ + "", /* 30 */ + "", /* 31 */ + "", /* 32 */ + "", /* 33 */ + "", /* 34 */ + "", /* 35 */ + "oled-rst", /* 36 */ + "pmu-int", /* 37 */ + "", /* 38 */ + "", /* 39 */ + "wan-sfp-rs0", /* 40 */ + "wan-sfp-pwrgood", /* 41 */ + "", /* 42 */ + "", /* 43 */ + "", /* 44 */ + "", /* 45 */ + "", /* 46 */ + "", /* 47 */ + "", /* 48 */ + "", /* 49 */ + "", /* 50 */ + "", /* 51 */ + "", /* 52 */ + "", /* 53 */ + "", /* 54 */ + "", /* 55 */ + "", /* 56 */ + "", /* 57 */ + "", /* 58 */ + "", /* 59 */ + "", /* 60 */ + "", /* 61 */ + "", /* 62 */ + "", /* 63 */ + "", /* 64 */ + "", /* 65 */ + "", /* 66 */ + "", /* 67 */ + "", /* 68 */ + "", /* 69 */ + "", /* 70 */ + "", /* 71 */ + "", /* 72 */ + "", /* 73 */ + "", /* 74 */ + "", /* 75 */ + "", /* 76 */ + "", /* 77 */ + "", /* 78 */ + "", /* 79 */ + "oled-data-select", /* 80 */ + "backlight-en", /* 81 */ + "led-white", /* 82 */ + "led-red", /* 83 */ + "", /* 84 */ + "", /* 85 */ + "keypad-left", /* 86 */ + "oled-vcc", /* 87 */ + "bt-rst", /* 88 */ + "ha-swd-clk", /* 89 */ + "ha-swd-io", /* 90 */ + "ha-rst", /* 91 */ + "", /* 92 */ + "", /* 93 */ + "", /* 94 */ + "", /* 95 */ + "keypad-up", /* 96 */ + "keypad-down", /* 97 */ + "w-enable-1", /* 98 */ + "w-enable-2", /* 99 */ + "", /* 100 */ + "", /* 101 */ + "keypad-right", /* 102 */ + "", /* 103 */ + "", /* 104 */ + "", /* 105 */ + "", /* 106 */ + "", /* 107 */ + "", /* 108 */ + "", /* 109 */ + "", /* 110 */ + "", /* 111 */ + "", /* 112 */ + "", /* 113 */ + "", /* 114 */ + "", /* 115 */ + "", /* 116 */ + "", /* 117 */ + "", /* 118 */ + "", /* 119 */ + "", /* 120 */ + "", /* 121 */ + "", /* 122 */ + "", /* 123 */ + "", /* 124 */ + "", /* 125 */ + "", /* 126 */ + "", /* 127 */ + "", /* 128 */ + "", /* 129 */ + ""; /* 130 */ + + w-enable-hog { + gpio-hog; + gpios = <99 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&keypad { + keyup { + label = "key up"; + linux,code = ; + gpios = <&pinctrl 97 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + keydown { + label = "key down"; + linux,code = ; + gpios = <&pinctrl 96 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + keyright { + label = "key right"; + linux,code = ; + gpios = <&pinctrl 102 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + keyleft { + label = "key left"; + linux,code = ; + gpios = <&pinctrl 86 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; +}; + +&i2c1_gpio { + fbxpmu@3c { + compatible = "freebox,fbxgwr-pmu"; + reg = <0x3c>; + + fbxpmu_gpio_expander: fbxpmu@3c { + compatible = "freebox,fbxgwr-pmu-gpio"; + interrupt-parent = <&pinctrl>; + interrupts = <37 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + ngpios = <24>; + #gpio-cells = <2>; + gpio-line-names = "", /* 0 */ + "", /* 1 */ + "", /* 2 */ + "", /* 3 */ + "power-button", /* 4 */ + "test-mode"; /* 5 */ + }; + + led-controller { + compatible = "freebox,fbxgwr-pmu-led"; + #address-cells = <1>; + #size-cells = <0>; + + nleds = <3>; + + led0@0 { + label = "green"; + reg = <0x00>; + }; + + led1@1 { + label = "red"; + reg = <0x01>; + }; + + led2@2 { + label = "blue"; + reg = <0x02>; + }; + }; + }; +}; + +&pcie01 { + status = "okay"; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&xdsl_phy { + status = "okay"; + + pinctrl-0 = <&ld0_pins>; + pinctrl-names = "default"; + + afe-id-0 = <(BCM63XX_XDSLPHY_AFE_CHIP_GFAST_CH0 | + BCM63XX_XDSLPHY_AFE_LD_6303 | + BCM63XX_XDSLPHY_AFE_FE_ANNEXA | + BCM63XX_XDSLPHY_AFE_FE_REV_6303_REV_12_3_60 | + BCM63XX_XDSLPHY_AFE_FE_RNC)>; +}; + +&xtm { + status = "okay"; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common-nopmu.dtsi linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common-nopmu.dtsi --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common-nopmu.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common-nopmu.dtsi 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,231 @@ +/* + * common dtsi file for fbxgw8r for boards without PMU + */ +/ { + leds { + compatible = "gpio-leds"; + led0 { + gpios = <&pinctrl 82 GPIO_ACTIVE_HIGH>; + default-state = "on"; + label = "white"; + }; + led1 { + gpios = <&pinctrl 83 GPIO_ACTIVE_HIGH>; + default-state = "off"; + label = "red"; + }; + }; +}; + +&i2c1_gpio { + adt7475@2e { + compatible = "adi,adt7475"; + reg = <0x2e>; + }; + + ld6710-fbx@68 { + compatible = "leadtrend,ld6710-fbx"; + reg = <0x68>; + }; +}; + +&pinctrl { + gpio-line-names = "", /* 0 */ + "", /* 1 */ + "", /* 2 */ + "bt-rst", /* 3 */ + "", /* 4 */ + "", /* 5 */ + "", /* 6 */ + "", /* 7 */ + "", /* 8 */ + "wan-sfp-presence", /* 9 */ + "wan-sfp-rxlos", /* 10 */ + "wan-sfp-txfault", /* 11 */ + "wan-sfp-rs1", /* 12 */ + "", /* 13 */ + "wan-sfp-pwren", /* 14 */ + "", /* 15 */ + "", /* 16 */ + "", /* 17 */ + "", /* 18 */ + "i2c-int", /* 19 */ + "poe-on", /* 20 */ + "fan-int", /* 21 */ + "", /* 22 */ + "fxs-int", /* 23 */ + "", /* 24 */ + "", /* 25 */ + "phy25-int", /* 26 */ + "phy25-reset", /* 27 */ + "", /* 28 */ + "", /* 29 */ + "", /* 30 */ + "", /* 31 */ + "", /* 32 */ + "", /* 33 */ + "", /* 34 */ + "", /* 35 */ + "oled-rst", /* 36 */ + "boot-eth", /* 37 */ + "", /* 38 */ + "", /* 39 */ + "wan-sfp-rs0", /* 40 */ + "wan-sfp-pwrgood", /* 41 */ + "", /* 42 */ + "", /* 43 */ + "", /* 44 */ + "", /* 45 */ + "", /* 46 */ + "", /* 47 */ + "", /* 48 */ + "", /* 49 */ + "", /* 50 */ + "", /* 51 */ + "", /* 52 */ + "", /* 53 */ + "", /* 54 */ + "", /* 55 */ + "", /* 56 */ + "", /* 57 */ + "", /* 58 */ + "", /* 59 */ + "", /* 60 */ + "", /* 61 */ + "", /* 62 */ + "", /* 63 */ + "", /* 64 */ + "", /* 65 */ + "", /* 66 */ + "", /* 67 */ + "", /* 68 */ + "", /* 69 */ + "", /* 70 */ + "", /* 71 */ + "", /* 72 */ + "", /* 73 */ + "", /* 74 */ + "", /* 75 */ + "", /* 76 */ + "", /* 77 */ + "", /* 78 */ + "", /* 79 */ + "oled-data-select", /* 80 */ + "backlight-en", /* 81 */ + "led-white", /* 82 */ + "led-red", /* 83 */ + "", /* 84 */ + "", /* 85 */ + "keypad-left", /* 86 */ + "oled-vcc", /* 87 */ + "bt-rst", /* 88 */ + "ha-swd-clk", /* 89 */ + "ha-swd-io", /* 90 */ + "ha-rst", /* 91 */ + "", /* 92 */ + "", /* 93 */ + "", /* 94 */ + "", /* 95 */ + "keypad-up", /* 96 */ + "keypad-down", /* 97 */ + "w-enable-1", /* 98 */ + "w-enable-2", /* 99 */ + "", /* 100 */ + "", /* 101 */ + "keypad-right", /* 102 */ + "", /* 103 */ + "", /* 104 */ + "", /* 105 */ + "", /* 106 */ + "", /* 107 */ + "", /* 108 */ + "", /* 109 */ + "", /* 110 */ + "", /* 111 */ + "", /* 112 */ + "", /* 113 */ + "", /* 114 */ + "", /* 115 */ + "", /* 116 */ + "", /* 117 */ + "", /* 118 */ + "", /* 119 */ + "", /* 120 */ + "", /* 121 */ + "", /* 122 */ + "", /* 123 */ + "", /* 124 */ + "", /* 125 */ + "", /* 126 */ + "", /* 127 */ + "", /* 128 */ + "", /* 129 */ + ""; /* 130 */ +}; + +&fbxgw8r_gpio { + poe-on { + gpio = <&pinctrl 20 0>; + output-low; + }; +}; + +&keypad { + keyup { + label = "key up"; + linux,code = ; + gpios = <&pinctrl 97 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + keydown { + label = "key down"; + linux,code = ; + gpios = <&pinctrl 96 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + keyright { + label = "key right"; + linux,code = ; + gpios = <&pinctrl 102 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + keyleft { + label = "key left"; + linux,code = ; + gpios = <&pinctrl 86 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; +}; + +&pcie0 { + status = "okay"; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie1 { + status = "okay"; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; +}; + +&xdsl_phy { + status = "okay"; + + pinctrl-0 = <&ld0_pins>; + pinctrl-names = "default"; + + afe-id-0 = <(BCM63XX_XDSLPHY_AFE_CHIP_GFAST_CH0 | + BCM63XX_XDSLPHY_AFE_LD_6303 | + BCM63XX_XDSLPHY_AFE_FE_ANNEXA | + BCM63XX_XDSLPHY_AFE_FE_REV_6303_REV_12_3_60 | + BCM63XX_XDSLPHY_AFE_FE_RNC)>; +}; + +&xtm { + status = "okay"; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common-onboard-pmu.dtsi linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common-onboard-pmu.dtsi --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common-onboard-pmu.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common-onboard-pmu.dtsi 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,255 @@ +/* + * common dtsi file for fbxgw8r for boards with on-board PMU + */ +/ { + powerbtn { + compatible = "gpio-keys"; + autorepeat = <0>; + + powerbtn { + label = "power"; + linux,code = ; + gpios = <&fbxpmu_gpio_expander 4 GPIO_ACTIVE_HIGH>; + debounce-interval = <50>; + linux,can-disable; + }; + }; + + dgasp { + compatible = "misc,dgasp"; + interrupt-parent = <&pinctrl>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + toreset-gpios = <&pinctrl 99 GPIO_ACTIVE_HIGH>; /* w-enable-2 */ + }; +}; + +&ramoops { + reg = <0x0 0x3fff0000 0x0 (64 * 1024)>; +}; + +&pinctrl { + gpio-line-names = "", /* 0 */ + "", /* 1 */ + "", /* 2 */ + "pmu-dyinggasp-int", /* 3 */ + "", /* 4 */ + "", /* 5 */ + "", /* 6 */ + "", /* 7 */ + "", /* 8 */ + "wan-sfp-presence", /* 9 */ + "wan-sfp-rxlos", /* 10 */ + "wan-sfp-txfault", /* 11 */ + "wan-sfp-rs1", /* 12 */ + "", /* 13 */ + "wan-sfp-pwren", /* 14 */ + "", /* 15 */ + "", /* 16 */ + "", /* 17 */ + "", /* 18 */ + "", /* 19 */ + "", /* 20 */ + "pmu-int", /* 21 */ + "", /* 22 */ + "fxs-int", /* 23 */ + "", /* 24 */ + "", /* 25 */ + "phy25-int", /* 26 */ + "phy25-reset", /* 27 */ + "", /* 28 */ + "", /* 29 */ + "", /* 30 */ + "", /* 31 */ + "", /* 32 */ + "", /* 33 */ + "", /* 34 */ + "", /* 35 */ + "oled-rst", /* 36 */ + "boot-eth", /* 37 */ + "", /* 38 */ + "", /* 39 */ + "wan-sfp-rs0", /* 40 */ + "wan-sfp-pwrgood", /* 41 */ + "", /* 42 */ + "", /* 43 */ + "", /* 44 */ + "", /* 45 */ + "", /* 46 */ + "", /* 47 */ + "", /* 48 */ + "", /* 49 */ + "", /* 50 */ + "", /* 51 */ + "", /* 52 */ + "", /* 53 */ + "", /* 54 */ + "", /* 55 */ + "", /* 56 */ + "", /* 57 */ + "", /* 58 */ + "", /* 59 */ + "", /* 60 */ + "", /* 61 */ + "", /* 62 */ + "", /* 63 */ + "", /* 64 */ + "", /* 65 */ + "", /* 66 */ + "", /* 67 */ + "", /* 68 */ + "", /* 69 */ + "", /* 70 */ + "", /* 71 */ + "", /* 72 */ + "", /* 73 */ + "", /* 74 */ + "", /* 75 */ + "", /* 76 */ + "", /* 77 */ + "", /* 78 */ + "", /* 79 */ + "oled-data-select", /* 80 */ + "", /* 81 */ + "", /* 82 */ + "", /* 83 */ + "", /* 84 */ + "", /* 85 */ + "", /* 86 */ + "oled-vcc", /* 87 */ + "", /* 88 */ + "", /* 89 */ + "", /* 90 */ + "", /* 91 */ + "", /* 92 */ + "", /* 93 */ + "", /* 94 */ + "", /* 95 */ + "", /* 96 */ + "", /* 97 */ + "", /* 98 */ + "w-enable-2", /* 99 */ + "", /* 100 */ + "", /* 101 */ + "", /* 102 */ + "", /* 103 */ + "", /* 104 */ + "", /* 105 */ + "", /* 106 */ + "", /* 107 */ + "", /* 108 */ + "", /* 109 */ + "", /* 110 */ + "", /* 111 */ + "", /* 112 */ + "", /* 113 */ + "", /* 114 */ + "", /* 115 */ + "", /* 116 */ + "", /* 117 */ + "", /* 118 */ + "", /* 119 */ + "", /* 120 */ + "", /* 121 */ + "", /* 122 */ + "", /* 123 */ + "", /* 124 */ + "", /* 125 */ + "", /* 126 */ + "", /* 127 */ + "", /* 128 */ + "", /* 129 */ + ""; /* 130 */ + + w-enable-hog { + gpio-hog; + gpios = <99 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&dsl_reserved { + status = "disabled"; +}; + +&i2c1_gpio { + fbxpmu@3c { + compatible = "freebox,fbxgwr-pmu"; + reg = <0x3c>; + + fbxpmu_gpio_expander: fbxpmu@3c { + compatible = "freebox,fbxgwr-pmu-gpio"; + interrupt-parent = <&pinctrl>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + ngpios = <24>; + #gpio-cells = <2>; + gpio-line-names = "keypad-down", /* 0 */ + "keypad-up", /* 1 */ + "keypad-cancel", /* 2 */ + "keypad-ok", /* 3 */ + "power-button", /* 4 */ + "test-mode"; /* 5 */ + }; + + led-controller { + compatible = "freebox,fbxgwr-pmu-led"; + #address-cells = <1>; + #size-cells = <0>; + + nleds = <3>; + + led0@0 { + label = "green"; + reg = <0x00>; + }; + + led1@1 { + label = "red"; + reg = <0x01>; + }; + + led2@2 { + label = "blue"; + reg = <0x02>; + }; + }; + }; +}; + +&keypad { + keyup { + label = "key up"; + linux,code = ; + gpios = <&fbxpmu_gpio_expander 1 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + linux,can-disable; + }; + keydown { + label = "key down"; + linux,code = ; + gpios = <&fbxpmu_gpio_expander 0 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + linux,can-disable; + }; + keyright { + label = "key right"; + linux,code = ; + gpios = <&fbxpmu_gpio_expander 3 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + linux,can-disable; + }; + keyleft { + label = "key left"; + linux,code = ; + gpios = <&fbxpmu_gpio_expander 2 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + linux,can-disable; + }; +}; + +&pcie01 { + status = "okay"; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common.dtsi linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common.dtsi --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-common.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-common.dtsi 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,449 @@ +/* + * common dtsi file for fbxgw8r. + */ +#include +#include "bcm63158.dtsi" + +#include <../../../include/generated/autoconf.h> + +/ { + model = "Freebox FBXGW8R"; + + chosen { + bootargs = "console=ttyAMA0,115200"; + stdout-path = &arm_serial0; + }; + + reserved-memory { + ramoops: ramoops@1fff0000 { + compatible = "ramoops"; + /* RAM top - 64k */ + reg = <0x0 0x1fff0000 0x0 (64 * 1024)>; + record-size = <(64 * 1024)>; + ecc-size = <16>; + no-dump-oops; + }; + +#ifdef CONFIG_ATH11K_QCN9074_FIXED_MEM_REGION + qca_pine_2G4: qca-pine-2G4 { + reg = <0x0 0x14000000 0x0 0x01A00000>; + no-map; + }; + qca_pine_5G: qca-pine-5G { + reg = <0x0 0x15a00000 0x0 0x01A00000>; + no-map; + }; +#endif + }; + fbxgw8r_gpio: fbxgw8r-gpio { + compatible = "fbx,fbxgpio"; + + wan-sfp-txfault { + gpio = <&pinctrl 11 0>; + input; + }; + wan-sfp-pwren { + gpio = <&pinctrl 14 0>; + output-low; + }; + wan-sfp-presence { + gpio = <&pinctrl 9 0>; + input; + }; + wan-sfp-pwrgood { + gpio = <&pinctrl 41 0>; + input; + }; + wan-sfp-rxlos { + gpio = <&pinctrl 10 0>; + input; + }; + wan-sfp-rs1 { + gpio = <&pinctrl 12 0>; + output-high; + }; + wan-sfp-rogue-in { + gpio = <&pinctrl 40 0>; + input; + no-claim; + }; + + boot-eth { + gpio = <&pinctrl 37 0>; + input; + }; + + ha-rst { + gpio = <&pinctrl 91 0>; + output-low; + }; + backlight-en { + gpio = <&pinctrl 81 0>; + output-low; + }; + + board-id-0 { + gpio = <&pinctrl 35 0>; + input; + }; + board-id-1 { + gpio = <&pinctrl 28 0>; + input; + }; + board-id-2 { + gpio = <&pinctrl 29 0>; + input; + }; + board-id-3 { + gpio = <&pinctrl 30 0>; + input; + }; + board-id-4 { + gpio = <&pinctrl 31 0>; + input; + }; + board-id-5 { + gpio = <&pinctrl 13 0>; + input; + }; + }; + + keypad: keypad { + compatible = "gpio-keys"; + autorepeat = <1>; + }; + + i2c0_gpio: i2c0-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 24 0 /* sda */ + &pinctrl 25 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1_gpio: i2c1-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 15 0 /* sda */ + &pinctrl 16 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + aliases { + i2c0 = &i2c0_gpio; + i2c1 = &i2c1_gpio; + }; + + qcom,diag@0 { + compatible = "qcom,diag"; + status = "ok"; + }; +}; + +&pinctrl { + arm_serial2_pins: arm-serial2-pins-0 { + arm_serial2_sout { + pinmux = ; + }; + arm_serial2_sin { + pinmux = ; + }; + }; +}; + +&arm_serial0 { + status = "okay"; +}; + + +&arm_serial2 { + /* home automation */ + status = "okay"; + pinctrl-0 = <&arm_serial2_pins>; + pinctrl-names = "default"; +}; + +&sf2 { + status = "okay"; + + pinctrl-0 = <&gphy01_link_act_leds>; + pinctrl-names = "default"; + + sf2,mdio { + reset-gpio = <&pinctrl 27 GPIO_ACTIVE_LOW>; + reset-delay-us = <100000>; + reset-post-delay-us = <100000>; + keep-broken-phy; + }; +}; + +&sf2_port0 { + status = "okay"; + label = "swp1"; + sf2,led-link-act = <20>; +}; + +&sf2_port1 { + status = "okay"; + label = "swp2"; + sf2,led-link-act = <21>; + dsa,cpu-port = <&sf2_port7>; +}; + +&sf2_port5 { + status = "okay"; +}; + +&sf2_port6 { + status = "okay"; + xbar-in-port = <0>; + phy-handle = <&port6_phy>; + label = "swp3"; + dsa,cpu-port = <&sf2_port5>; +}; + +&sf2_port7 { + status = "okay"; +}; + +&sf2_port8 { + status = "okay"; +}; + +&sf2_qphy0 { + status = "okay"; +}; + +&sf2_qphy1 { + status = "okay"; +}; + +&runner_unimac0 { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&runner_unimac1 { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&runner_unimac2 { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&runner_xport0 { + status = "okay"; + fbxserial-mac-address = <0>; + pinctrl-0 = <&sfp_rogue1_pins>; + pinctrl-1 = <&sfp_rs0_gpio_pins>; + pinctrl-names = "rogue1", "rs0"; + +}; + +&sdhci { + status = "okay"; + + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + partitions-main { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%d"; + + bank0@0 { + label = "bank0"; + reg = /bits/64 <0 (32 * 1024 * 1024)>; + read-only; + }; + + bank1@0 { + label = "bank1"; + reg = /bits/64 <(-1) (256 * 1024 * 1024)>; + }; + + nvram@0 { + label = "nvram"; + reg = /bits/64 <(-1) (4 * 1024 * 1024)>; + }; + + config@0 { + label = "config"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + new-bank0@0 { + label = "new_bank0"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + fbxmbr@0 { + label = "fbxmbr"; + reg = /bits/64 <(-1) (4096)>; + }; + + fortknox@0 { + label = "fortknox"; + reg = /bits/64 <(-1) (128 * 1024 * 1024)>; + }; + + userdata@0 { + label = "userdata"; + reg = /bits/64 <(-1) (-1)>; + }; + + }; + + + partitions-boot { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%dboot0"; + + cfe@0 { + label = "cfe0"; + reg = /bits/64 <0 (256 * 1024)>; + read-only; + }; + cfe@1 { + label = "cfe1"; + reg = /bits/64 <(-1) (256 * 1024)>; + read-only; + }; + cfe@2 { + label = "cfe2"; + reg = /bits/64 <(-1) (256 * 1024)>; + read-only; + }; + + serial@0 { + label = "fbxserial"; + reg = /bits/64 <(1024 * 1024) (8 * 1024)>; + read-only; + }; + + fbxboot@0 { + label = "fbxboot"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + + calibration@0 { + label = "calibration"; + reg = /bits/64 <(-1) (64 * 1024)>; + read-only; + }; + }; +}; + +&spi_pins { + spi-ss0 { + pinmux = ; + }; + spi-ss1 { + pinmux = ; + }; +}; + +&hs_spim { + status = "okay"; + num-cs = <2>; + broadcom,dummy-cs = <2>; + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + ssd1320@0 { + compatible = "solomon,ssd1320"; + reg = <0>; + + spi-max-frequency = <(14 * 1000 * 1000)>; + + /* + * display mapping info (when looking at it such as keypad + * is on the right): + * + * SEG used on x-axis + * COM used on y-axis + * + * top-left: COM159/SEG0 + * bottom-right: COM0/SEG159 + * + * visible area (160x80) + * top-left: COM119/SEG0 + * bottom-right: COM40/SEG159 + * + * SEG are mapped in alternate: SEG0, SEG80, SEG1, ... + */ + ssd1320,com-range = <40 119>; + ssd1320,seg-range = <0 159>; + ssd1320,com-reverse-dir; + ssd1320,seg-first-odd; + + ssd1320,clk-divide-ratio = <0xb1>; + ssd1320,precharge-period = <0x42>; + ssd1320,vcom-deselect-level = <0x30>; + ssd1320,precharge-voltage = <0x10>; + ssd1320,iref = <0x10>; + + ssd1320,display-enh-a = <0xd5>; + ssd1320,display-enh-b = <0x21>; + + ssd1320,grayscale-table = <0x01 0x02 0x03 0x05 0x08 0x0b + 0xe 0x12 0x17 0x1c 0x22 0x29 0x2f 0x36 0x3f>; + + ssd1320,default-brightness = <0x9f>; + ssd1320,max-brightness = <0xff>; + + ssd1320,watchdog = <300>; + ssd1320,vcc-gpio = <&pinctrl 87 GPIO_ACTIVE_HIGH>; + ssd1320,data-select-gpio = <&pinctrl 80 GPIO_ACTIVE_HIGH>; + ssd1320,reset-gpio = <&pinctrl 36 GPIO_ACTIVE_LOW>; + }; + + spi-slac@1 { + compatible = "microsemi,le9641"; + reg = <1>; + spi-max-frequency = <(1 * 1000 * 1000)>; + }; +}; + +&bcm_pcm { + status = "okay"; + pinctrl-0 = <&pcm_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + brcm,pwren-high; + brcm,pwrflt-low; +}; + +&hs_uart { + status = "okay"; + pinctrl-0 = <&hs_uart_pins>; + pinctrl-names = "default"; + bluetooth { + compatible = "realtek,rtl8761btv-bt"; + firmware-postfix = "1M5"; + reset-gpio = <&pinctrl 88 GPIO_ACTIVE_LOW>; + }; +}; + +&memc { + // status = "disabled"; + brcm,auto-sr-en; + brcm,auto-sr-thresh = <20>; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-phy-aquantia.dtsi linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-phy-aquantia.dtsi --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-phy-aquantia.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-phy-aquantia.dtsi 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,10 @@ +&sf2 { + sf2,mdio { + /* aquantia PHY */ + port6_phy: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + status = "okay"; + reg = <8>; + }; + }; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-phy-realtek.dtsi linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-phy-realtek.dtsi --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r-phy-realtek.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r-phy-realtek.dtsi 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,10 @@ +&sf2 { + sf2,mdio { + /* realtek PHY */ + port6_phy: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + status = "okay"; + reg = <7>; + }; + }; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r.dts 2024-03-18 14:40:14.835740896 +0100 @@ -0,0 +1,13 @@ +/* + * Freebox FBXGW8R Board DTS + */ +/dts-v1/; + +#include "fbxgw8r-common.dtsi" +#include "fbxgw8r-common-nopmu.dtsi" +#include "fbxgw8r-phy-aquantia.dtsi" + +/ { + compatible = "freebox,fbxgw8r-board-00", "freebox,fbxgw8r", + "brcm,bcm63158"; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r_pcie_pine_asmedia.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r_pcie_pine_asmedia.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r_pcie_pine_asmedia.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r_pcie_pine_asmedia.dts 2023-03-15 19:52:23.509978971 +0100 @@ -0,0 +1,60 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "freebox,fbxgw8r"; + + fragment@1 { + target = <&pcie0>; + __overlay__ { + #address-cells = <3>; + #size-cells = <2>; + rc@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0000 0x0 0x0 0x0 0x0>; + ep_pine6G { + reg = <0x0000 0x0 0x0 0x0 0x0>; + qcom,board_id = <0xa9>; + }; + }; + }; + }; + + + fragment@2 { + target = <&pcie1>; + __overlay__ { + #address-cells = <3>; + #size-cells = <2>; + rc@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0000 0x0 0x0 0x0 0x0>; + us { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0000 0x0 0x0 0x0 0x0>; + ds1 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x1800 0x0 0x0 0x0 0x0>; + ep_pine2G4 { + reg = <0x0000 0x0 0x0 0x0 0x0>; + qcom,board_id = <0xa6>; + }; + }; + ds2 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x3800 0x0 0x0 0x0 0x0>; + ep_pine5G { + reg = <0x0000 0x0 0x0 0x0 0x0>; + qcom,board_id = <0xa3>; + }; + }; + }; + }; + }; + }; +}; diff -Nruw linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r_pcie_pine_dualband_noswitch.dts linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r_pcie_pine_dualband_noswitch.dts --- linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r_pcie_pine_dualband_noswitch.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r_pcie_pine_dualband_noswitch.dts 2023-11-07 13:38:43.982254506 +0100 @@ -0,0 +1,49 @@ +/dts-v1/; +/plugin/; + +#include <../../../include/generated/autoconf.h> + +/ { + compatible = "freebox,fbxgw8r"; + + fragment@1 { + target = <&pcie0>; + __overlay__ { + #address-cells = <3>; + #size-cells = <2>; + rc@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0000 0x0 0x0 0x0 0x0>; + ep_pine5G { + reg = <0x0000 0x0 0x0 0x0 0x0>; + qcom,board_id = <0xa3>; +#ifdef CONFIG_ATH11K_QCN9074_FIXED_MEM_REGION + memory-region = <&qca_pine_5G>; +#endif + }; + }; + }; + }; + + + fragment@2 { + target = <&pcie1>; + __overlay__ { + #address-cells = <3>; + #size-cells = <2>; + rc@0,0 { + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0000 0x0 0x0 0x0 0x0>; + ep_pine2G4 { + reg = <0x0000 0x0 0x0 0x0 0x0>; + qcom,board_id = <0xa6>; +#ifdef CONFIG_ATH11K_QCN9074_FIXED_MEM_REGION + memory-region = <&qca_pine_2G4>; +#endif + }; + }; + }; + }; +}; --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/block/partitions/dt.c 2023-02-24 19:10:44.415570202 +0100 @@ -0,0 +1,204 @@ +#define PREFIX "dtparts" + +#include +#include +#include +#include "check.h" + +/** + * match_one: - Determines if a string matches a simple pattern + * @s: the string to examine for presence of the pattern + * @p: the string containing the pattern + */ +static int match_one(char *s, const char *p) +{ + char *meta, *from, *to; + + while (1) { + int len = -1; + + meta = strchr(p, '%'); + if (!meta) + return strcmp(p, s) == 0; + + if (strncmp(p, s, meta-p)) + return 0; + + s += meta - p; + p = meta + 1; + + if (isdigit(*p)) + len = simple_strtoul(p, (char **) &p, 10); + else if (*p == '%') { + if (*s++ != '%') + return 0; + p++; + continue; + } + + from = s; + switch (*p++) { + case 's': { + size_t str_len = strlen(s); + + if (str_len == 0) + return 0; + if (len == -1 || len > str_len) + len = str_len; + to = s + len; + break; + } + case 'd': + simple_strtol(s, &to, 0); + goto num; + case 'u': + simple_strtoul(s, &to, 0); + goto num; + case 'o': + simple_strtoul(s, &to, 8); + goto num; + case 'x': + simple_strtoul(s, &to, 16); + + num: + if (to == from) + return 0; + break; + default: + return 0; + } + s = to; + } +} + +/* + * + */ +static struct device_node *find_first_parent_node(const struct device *ddev) +{ + while (ddev && !ddev->of_node) + ddev = ddev->parent; + + if (!ddev) + return NULL; + return ddev->of_node; +} + +/* + * + */ +int dt_partition(struct parsed_partitions *state) +{ + struct device *ddev = disk_to_dev(state->disk); + struct device_node *np, *part_node, *pp; + u64 disk_size, last_end; + int nr_parts, i; + + /* find first parent device with a non null device tree + * node */ + np = find_first_parent_node(ddev); + if (!np) + return -1; + + part_node = NULL; + for_each_child_of_node(np, pp) { + char diskname[BDEVNAME_SIZE]; + const char *pattern; + + if (!of_device_is_compatible(pp, "fixed-partitions")) + continue; + + /* check device name match pattern */ + strlcpy(diskname, state->disk->disk_name, sizeof (diskname)); + + if (of_property_read_string(pp, "disk-name", &pattern)) { + part_node = pp; + break; + } + + if (match_one(diskname, pattern)) { + part_node = pp; + break; + } + } + + if (!part_node) + return -1; + + /* First count the subnodes */ + nr_parts = 0; + for_each_child_of_node(part_node, pp) + nr_parts++; + + if (nr_parts == 0) + return 0; + + disk_size = get_capacity(state->disk) << 9; + + last_end = 0; + i = 1; + for_each_child_of_node(part_node, pp) { + struct partition_meta_info *info; + char tmp[sizeof (info->volname) + 4]; + const __be32 *reg; + const char *partname; + int a_cells, s_cells; + u64 size, offset; + int len; + + reg = of_get_property(pp, "reg", &len); + if (!reg) { + pr_err("part %pOF (%pOF) missing reg property.\n", + pp, np); + return -1; + } + + a_cells = of_n_addr_cells(pp); + s_cells = of_n_size_cells(pp); + if (len / 4 != a_cells + s_cells) { + pr_err("ofpart partition %pOF (%pOF) " + "error parsing reg property.\n", + pp, np); + return -1; + } + + partname = of_get_property(pp, "label", &len); + if (!partname) + partname = of_get_property(pp, "name", &len); + + if (i >= state->limit) { + pr_err("too many partitions\n"); + return -1; + } + + offset = of_read_number(reg, a_cells); + if (offset == (u64)-1) { + offset = last_end; + } + + size = of_read_number(reg + a_cells, s_cells); + if (size == (u64)-1) + size = disk_size - offset; + + last_end = offset + size; + put_partition(state, i, offset >> 9, size >> 9); + + info = &state->parts[i].info; + strlcpy(info->volname, partname, sizeof (info->volname)); + state->parts[i].has_info = true; + + if (!IS_ENABLED(CONFIG_OF_PARTITION_IGNORE_RO) && + of_get_property(pp, "read-only", &len)) + state->parts[i].flags |= ADDPART_FLAG_RO; + + snprintf(tmp, sizeof(tmp), "(%s/%s)", + info->volname, + state->parts[i].flags ? "ro" : "rw"); + strlcat(state->pp_buf, tmp, PAGE_SIZE); + + i++; + } + + strlcat(state->pp_buf, "\n", PAGE_SIZE); + return 1; +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/config 2024-04-19 18:23:15.413222881 +0200 @@ -0,0 +1,4940 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 6.4.0 Kernel Configuration +# +CONFIG_CC_VERSION_TEXT="aarch64-linux-musl-gcc (freebox) 10.4.0" +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100400 +CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23800 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23800 +CONFIG_LLD_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y +CONFIG_PAHOLE_VERSION=0 +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_TABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="/opt/toolchains/aarch64-musl-1.2.2-gcc-10.4.0-binutils-2.38-gdb-11.2-1/bin/aarch64-linux-musl-" +# CONFIG_COMPILE_TEST is not set +# CONFIG_WERROR is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_WATCH_QUEUE is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_IRQ_IPI=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +# CONFIG_BPF_SYSCALL is not set +CONFIG_BPF_JIT=y +CONFIG_BPF_JIT_DEFAULT_ON=y +# end of BPF subsystem + +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_DYNAMIC is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# CONFIG_CPU_ISOLATION is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +# CONFIG_PRINTK_INDEX is not set +# CONFIG_FBX_DECRYPT_INITRD is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_CC_HAS_INT128=y +CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +CONFIG_GCC11_NO_ARRAY_BOUNDS=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_MISC is not set +# CONFIG_CGROUP_DEBUG is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +# CONFIG_TIME_NS is not set +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INITRAMFS_FORCE is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +# CONFIG_RD_ZSTD is not set +# CONFIG_BOOT_CONFIG is not set +# CONFIG_INITRAMFS_PRESERVE_MTIME is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y +CONFIG_LD_ORPHAN_WARN_LEVEL="warn" +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +# CONFIG_FHANDLE is not set +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_IO_URING is not set +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_SELFTEST is not set +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +# CONFIG_KCMP is not set +# CONFIG_RSEQ is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +# CONFIG_PROFILING is not set +# end of General setup + +CONFIG_ARM64=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_PTE_SHIFT=4 +CONFIG_ARM64_CONT_PMD_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_APPLE is not set +CONFIG_ARCH_BCM=y +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +CONFIG_ARCH_BCMBCA=y +# CONFIG_ARCH_BRCMSTB is not set +CONFIG_ARCH_BCM63XX_SHARED_OSH=y +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SPARX5 is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEEMBAY is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_NXP is not set +# CONFIG_ARCH_NPCM is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_INTEL_SOCFPGA is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VISCONTI is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set +# end of Platform selection + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +# CONFIG_ARM64_ERRATUM_832075 is not set +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +# CONFIG_ARM64_ERRATUM_1024718 is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1319367 is not set +# CONFIG_ARM64_ERRATUM_1530923 is not set +# CONFIG_ARM64_ERRATUM_2441007 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_ERRATUM_1508412 is not set +# CONFIG_ARM64_ERRATUM_2051678 is not set +# CONFIG_ARM64_ERRATUM_2077057 is not set +# CONFIG_ARM64_ERRATUM_2658417 is not set +# CONFIG_ARM64_ERRATUM_2054223 is not set +# CONFIG_ARM64_ERRATUM_2067961 is not set +# CONFIG_ARM64_ERRATUM_2441009 is not set +# CONFIG_ARM64_ERRATUM_2645198 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set +# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set +# end of ARM errata workarounds via the alternatives framework + +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_CLUSTER is not set +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=4 +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NUMA is not set +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_HW_PERF_EVENTS=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_XEN is not set +CONFIG_ARCH_FORCE_MAX_ORDER=10 +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set +# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +# CONFIG_COMPAT is not set + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +CONFIG_AS_HAS_LDAPR=y +CONFIG_AS_HAS_LSE_ATOMICS=y +# CONFIG_ARM64_USE_LSE_ATOMICS is not set +# end of ARMv8.1 architectural features + +# +# ARMv8.2 architectural features +# +CONFIG_AS_HAS_ARMV8_2=y +CONFIG_AS_HAS_SHA3=y +# CONFIG_ARM64_PMEM is not set +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set +# end of ARMv8.2 architectural features + +# +# ARMv8.3 architectural features +# +# CONFIG_ARM64_PTR_AUTH is not set +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y +CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y +CONFIG_AS_HAS_ARMV8_3=y +CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y +# end of ARMv8.3 architectural features + +# +# ARMv8.4 architectural features +# +# CONFIG_ARM64_AMU_EXTN is not set +CONFIG_AS_HAS_ARMV8_4=y +# CONFIG_ARM64_TLB_RANGE is not set +# end of ARMv8.4 architectural features + +# +# ARMv8.5 architectural features +# +CONFIG_AS_HAS_ARMV8_5=y +# CONFIG_ARM64_BTI is not set +CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y +# CONFIG_ARM64_E0PD is not set +CONFIG_ARM64_AS_HAS_MTE=y +# CONFIG_ARM64_MTE is not set +# end of ARMv8.5 architectural features + +# +# ARMv8.7 architectural features +# +# CONFIG_ARM64_EPAN is not set +# end of ARMv8.7 architectural features + +# CONFIG_ARM64_SVE is not set +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +# CONFIG_RELOCATABLE is not set +# CONFIG_RANDOMIZE_BASE is not set +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +# end of Kernel Features + +# +# Boot options +# +CONFIG_CMDLINE="console=ttyAMA0,115200 earlycon=pl011,mmio32,0xff812000 debug ip=:::::swp1:dhcp root=/dev/nfs" +# CONFIG_CMDLINE_FROM_BOOTLOADER is not set +CONFIG_CMDLINE_FORCE=y +# CONFIG_EFI is not set +# end of Boot options + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_BCM63158_CPUFREQ=y +# end of CPU Frequency scaling +# end of CPU Power Management + +CONFIG_HAVE_KVM=y +# CONFIG_VIRTUALIZATION is not set + +# +# General architecture-dependent options +# +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HAS_NMI_SAFE_THIS_CPU_OPS=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_ARCH_SECCOMP=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y +CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +# CONFIG_STACKPROTECTOR is not set +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y +CONFIG_ARCH_SUPPORTS_CFI_CLANG=y +CONFIG_HAVE_CONTEXT_TRACKING_USER=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_ARCH_HUGE_VMALLOC=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET is not set +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_HAVE_ARCH_COMPILER_H=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_HAVE_PREEMPT_DYNAMIC=y +CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y +CONFIG_ARCH_HAVE_TRACE_MMIO_ACCESS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_HAVE_GCC_PLUGINS=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FUNCTION_ALIGNMENT=4 +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_DEBUG is not set +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODULE_UNLOAD_TAINT_TRACKING is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" +CONFIG_TRIM_UNUSED_KSYMS=y +CONFIG_UNUSED_KSYMS_WHITELIST="" +CONFIG_UNUSED_KSYMS_WHITELIST_SYMS="dib7000p_attach" +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set +CONFIG_BLK_DEV_BSG_COMMON=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_OF_PARTITION=y +# CONFIG_OF_PARTITION_IGNORE_RO is not set +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y +CONFIG_BLOCK_HOLDER_DEPRECATED=y +CONFIG_BLK_MQ_STACKING=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_STATE=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_HAVE_ELF_PROT=y +CONFIG_ARCH_USE_GNU_PROPERTY=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +# CONFIG_SWAP is not set + +# +# SLAB allocator options +# +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLUB_TINY is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SLUB_STATS is not set +CONFIG_SLUB_CPU_PARTIAL=y +# end of SLAB allocator options + +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_COMPAT_BRK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +# CONFIG_COMPACTION is not set +# CONFIG_PAGE_REPORTING is not set +# CONFIG_MIGRATION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_PAGE_FRAG_CACHE_ORDER=1 +# CONFIG_MEMORY_FAILURE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_CMA is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y +# CONFIG_ZONE_DMA is not set +# CONFIG_ZONE_DMA32 is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_TEST is not set +# CONFIG_DMAPOOL_TEST is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# CONFIG_SECRETMEM is not set +# CONFIG_ANON_VMA_NAME is not set +# CONFIG_USERFAULTFD is not set +# CONFIG_LRU_GEN is not set +CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y +CONFIG_PER_VMA_LOCK=y + +# +# Data Access Monitoring +# +# CONFIG_DAMON is not set +# end of Data Access Monitoring +# end of Memory Management options + +CONFIG_NET=y +# CONFIG_NET_PROMISC_MESSAGES is not set +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_NETSKBPAD=64 +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_AF_UNIX_OOB=y +CONFIG_UNIX_ABSTRACT_IGNORE_NETNS=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=y +CONFIG_XFRM_ESP=y +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_NET_HANDSHAKE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +CONFIG_NET_UDP_TUNNEL=y +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_ESPINTCP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_ESP_OFFLOAD=y +# CONFIG_INET6_ESPINTCP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +CONFIG_INET6_TUNNEL=y +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_GRE is not set +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set +# CONFIG_IPV6_IOAM6_LWTUNNEL is not set +# CONFIG_MPTCP is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_INGRESS is not set +# CONFIG_NETFILTER_EGRESS is not set +CONFIG_NETFILTER_NETLINK=y +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_OSF is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_LOG_SYSLOG is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_LABELS is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=m +# CONFIG_NF_CONNTRACK_SANE is not set +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_NAT=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +# CONFIG_NF_TABLES is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=y +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_NAT=y +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=y +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +CONFIG_NETFILTER_XT_MATCH_DSCP=y +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +CONFIG_NETFILTER_XT_MATCH_OWNER=y +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=y +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +CONFIG_NETFILTER_XT_MATCH_STATE=y +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_FFN=y +CONFIG_IP_FFN_PROCFS=y +CONFIG_NF_DEFRAG_IPV4=y +# CONFIG_NF_SOCKET_IPV4 is not set +CONFIG_NF_TPROXY_IPV4=y +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_REJECT_IPV4=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_IPV6_FFN=y +CONFIG_IPV6_FFN_PROCFS=y +# CONFIG_NF_SOCKET_IPV6 is not set +CONFIG_NF_TPROXY_IPV6=y +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=y +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=y +# CONFIG_IP6_NF_RAW is not set +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +# CONFIG_IP6_NF_TARGET_NPT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=y +# CONFIG_NF_CONNTRACK_BRIDGE is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_FBXATM=y +CONFIG_FBXATM_STACK=y +# CONFIG_FBXATM_REMOTE_STUB is not set +# CONFIG_FBXATM_REMOTE_DRIVER is not set +CONFIG_FBXBRIDGE=y +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_STATE_MESSAGES is not set +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_TAG_NONE is not set +# CONFIG_NET_DSA_TAG_AR9331 is not set +CONFIG_NET_DSA_TAG_BRCM_COMMON=y +CONFIG_NET_DSA_TAG_BRCM=y +# CONFIG_NET_DSA_TAG_BRCM_LEGACY is not set +# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set +# CONFIG_NET_DSA_TAG_HELLCREEK is not set +CONFIG_NET_DSA_TAG_BRCM_FBX=y +# CONFIG_NET_DSA_TAG_GSWIP is not set +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_DSA_TAG_MTK is not set +# CONFIG_NET_DSA_TAG_KSZ is not set +# CONFIG_NET_DSA_TAG_OCELOT is not set +# CONFIG_NET_DSA_TAG_OCELOT_8021Q is not set +# CONFIG_NET_DSA_TAG_QCA is not set +# CONFIG_NET_DSA_TAG_RTL4_A is not set +# CONFIG_NET_DSA_TAG_RTL8_4 is not set +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set +# CONFIG_NET_DSA_TAG_LAN9303 is not set +# CONFIG_NET_DSA_TAG_SJA1105 is not set +# CONFIG_NET_DSA_TAG_TRAILER is not set +# CONFIG_NET_DSA_TAG_XRS700X is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +CONFIG_VLAN_FBX=y +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=y +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_NETEM is not set +CONFIG_NET_SCH_DRR=y +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +CONFIG_NET_SCH_INGRESS=y +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_SAMPLE is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +CONFIG_NET_ACT_SKBEDIT=y +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_MPLS is not set +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_SKBMOD is not set +# CONFIG_NET_ACT_IFE is not set +# CONFIG_NET_ACT_TUNNEL_KEY is not set +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_DNS_RESOLVER is not set +CONFIG_BATMAN_ADV=y +CONFIG_BATMAN_ADV_BATMAN_V=y +# CONFIG_BATMAN_ADV_BLA is not set +# CONFIG_BATMAN_ADV_DAT is not set +# CONFIG_BATMAN_ADV_NC is not set +# CONFIG_BATMAN_ADV_MCAST is not set +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_BATMAN_ADV_FBX=y +CONFIG_BATMAN_ADV_FBX_MTU=y +CONFIG_BATMAN_ADV_FBX_SLAP=y +# CONFIG_BATMAN_ADV_FBX_PERIF_ROUTER is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_L3_MASTER_DEV is not set +CONFIG_QRTR=y +# CONFIG_QRTR_TUN is not set +CONFIG_QRTR_MHI=y +# CONFIG_NET_NCSI is not set +# CONFIG_PCPU_DEV_REFCNT is not set +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=y +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_BT=y +CONFIG_BT_BREDR=y +# CONFIG_BT_RFCOMM is not set +# CONFIG_BT_BNEP is not set +CONFIG_BT_HIDP=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y +# CONFIG_BT_LE_L2CAP_ECRED is not set +# CONFIG_BT_LEDS is not set +# CONFIG_BT_MSFTEXT is not set +# CONFIG_BT_AOSPEXT is not set +CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set +# CONFIG_BT_FEATURE_DEBUG is not set + +# +# Bluetooth device drivers +# +CONFIG_BT_RTL=y +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIUART_3WIRE=y +# CONFIG_BT_HCIUART_INTEL is not set +# CONFIG_BT_HCIUART_BCM is not set +CONFIG_BT_HCIUART_RTL=y +# CONFIG_BT_HCIUART_QCA is not set +# CONFIG_BT_HCIUART_AG6XX is not set +# CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBCM4377 is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_MTKSDIO is not set +# CONFIG_BT_MTKUART is not set +# CONFIG_BT_NXPUART is not set +# end of Bluetooth device drivers + +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +# CONFIG_MCTP is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_CERTIFICATION_ONUS=y +# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set +# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set +# CONFIG_CFG80211_REG_RELAX_NO_IR is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_DFS_CACHE is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_WEXT is not set +# CONFIG_FBX80211 is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_DEVLINK=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +# CONFIG_FAILOVER is not set +# CONFIG_ETHTOOL_NETLINK is not set + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIEASPM is not set +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_VGA_ARB is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCIE_BRCMSTB is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HOST_GENERIC is not set +CONFIG_PCIE_BCM63XX=y +# CONFIG_PCIE_MICROCHIP_HOST is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCIE_XILINX is not set + +# +# Cadence-based PCIe controllers +# +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +# CONFIG_PCI_J721E_HOST is not set +# end of Cadence-based PCIe controllers + +# +# DesignWare-based PCIe controllers +# +# CONFIG_PCIE_AL is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCIE_DW_PLAT_HOST is not set +# end of DesignWare-based PCIe controllers + +# +# Mobiveil-based PCIe controllers +# +# end of Mobiveil-based PCIe controllers +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_CXL_BUS is not set +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_DEVTMPFS_SAFE is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_EXTRA_FIRMWARE="aquantia_phy/aqr112.uc xrdp/dsl_firmware/bcm63xx_dsl_runner.rpgm xrdp/enet_firmware/bcm63xx_enet_runner.rpgm" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +# CONFIG_FW_LOADER_COMPRESS is not set +# CONFIG_FW_UPLOAD is not set +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set +# CONFIG_VEXPRESS_CONFIG is not set +CONFIG_MHI_BUS=y +# CONFIG_MHI_BUS_DEBUG is not set +# CONFIG_MHI_BUS_PCI_GENERIC is not set +# CONFIG_MHI_BUS_EP is not set +# end of Bus devices + +# CONFIG_CONNECTOR is not set + +# +# Firmware Drivers +# + +# +# ARM System Control and Management Interface Protocol +# +# CONFIG_ARM_SCMI_PROTOCOL is not set +# end of ARM System Control and Management Interface Protocol + +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_ARM_FFA_TRANSPORT is not set +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_ARM_PSCI_FW=y +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y +# CONFIG_ARM_SMCCC_SOC_ID is not set + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# CONFIG_GNSS is not set +CONFIG_FREEBOX_PROCFS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_ERASE_PRINTK=y + +# +# Partition parsers +# +# CONFIG_MTD_AR7_PARTS is not set +# CONFIG_MTD_BRCM_U_BOOT is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_OF_PARTS_BCM4908 is not set +# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set +# CONFIG_MTD_OF_PARTS_IGNORE_RO is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_FBX6HD_PARTS is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y + +# +# Note that in some cases UBI block is preferred. See MTD_UBI_BLOCK. +# +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_MCHP48L640 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# +# NAND +# +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# ECC engine support +# +# CONFIG_MTD_NAND_ECC_SW_HAMMING is not set +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_MXIC is not set +# end of ECC engine support +# end of NAND + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +# CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_DTB_BUILTIN_LIST="" +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_ZRAM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_UBLK is not set + +# +# NVME Support +# +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_WINTEGRA_MMAP is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_INTELCE_PIC16PMU is not set +CONFIG_FBXSERIAL_OF=y +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_OPEN_DICE is not set +# CONFIG_VCPU_STALL_DETECTOR is not set +CONFIG_DGASP=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# CONFIG_EEPROM_EE1004_RAW is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_VMWARE_VMCI is not set +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_PVPANIC is not set +# CONFIG_GP_PCI1XXXX is not set + +# +# RemoTI support +# +# end of RemoTI support + +# +# HDMI CEC support +# +# CONFIG_HDMI_CEC is not set +# end of HDMI CEC support +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI_COMMON=y +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_DM_AUDIT is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +CONFIG_DUMMY=y +CONFIG_WIREGUARD=y +# CONFIG_WIREGUARD_DEBUG is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set +# CONFIG_GTP is not set +# CONFIG_AMT is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +# CONFIG_NLMON is not set +# CONFIG_MHI_NET is not set +# CONFIG_ARCNET is not set + +# +# Distributed Switch Architecture drivers +# +# CONFIG_B53 is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_NET_DSA_LOOP is not set +# CONFIG_NET_DSA_LANTIQ_GSWIP is not set +# CONFIG_NET_DSA_MT7530 is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_AR9331 is not set +# CONFIG_NET_DSA_QCA8K is not set +# CONFIG_NET_DSA_SJA1105 is not set +# CONFIG_NET_DSA_XRS700X_I2C is not set +# CONFIG_NET_DSA_XRS700X_MDIO is not set +# CONFIG_NET_DSA_REALTEK is not set +# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set +# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCM4908_ENET is not set +# CONFIG_BCM63XX_ENET_RUNNER is not set +CONFIG_BCM63158_SF2=y +CONFIG_BCM63158_ENET_RUNNER=y +CONFIG_BCM63158_ENET_RUNNER_FF=y +# CONFIG_BCMGENET is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2X is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_BNXT is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=m +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLINK=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set +CONFIG_PHYLIB_LEDS=y +CONFIG_FIXED_PHY=y +# CONFIG_SFP is not set + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_ADIN1100_PHY is not set +CONFIG_AQUANTIA_PHY=y +# CONFIG_AX88796B_PHY is not set +CONFIG_BROADCOM_PHY=y +# CONFIG_BCM54140_PHY is not set +CONFIG_BCM7XXX_PHY=y +# CONFIG_BCM84881_PHY is not set +# CONFIG_BCM87XX_PHY is not set +CONFIG_BCM_NET_PHYLIB=y +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MAXLINEAR_GPHY is not set +# CONFIG_MEDIATEK_GE_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_T1S_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_MOTORCOMM_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_CBTX_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_NCN26000_PHY is not set +# CONFIG_QCA807X_PHY is not set +# CONFIG_QCA8084_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set +# CONFIG_DP83TD510_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PSE_CONTROLLER is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_FWNODE_MDIO=y +CONFIG_OF_MDIO=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set + +# +# PCS device drivers +# +# end of PCS device drivers + +CONFIG_PPP=y +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=y +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPPOE=y +CONFIG_PPTP=y +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_WLAN=y +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH_COMMON=y +CONFIG_WLAN_VENDOR_ATH=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH_REG_IGNORE=y +CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS=y +CONFIG_ATH_REG_DYNAMIC_USER_CERT_TESTING=y +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_COMMON_DEBUG=y +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +CONFIG_ATH9K_DEBUGFS=y +CONFIG_ATH9K_STATION_STATISTICS=y +CONFIG_ATH9K_TX99=y +# CONFIG_ATH9K_DFS_CERTIFIED is not set +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +# CONFIG_ATH9K_PCOEM is not set +# CONFIG_ATH9K_PCI_NO_EEPROM is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_ATH9K_HWRNG is not set +# CONFIG_ATH9K_COMMON_SPECTRAL is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +# CONFIG_WIL6210 is not set +CONFIG_ATH10K=y +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_AHB is not set +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +CONFIG_ATH10K_DEBUG=y +CONFIG_ATH10K_DEBUGFS=y +# CONFIG_ATH10K_SPECTRAL is not set +CONFIG_ATH10K_DFS_CERTIFIED=y +# CONFIG_WCN36XX is not set +CONFIG_ATH11K=y +CONFIG_ATH11K_PCI=m +CONFIG_ATH11K_DEBUG=y +CONFIG_ATH11K_DEBUGFS=y +CONFIG_ATH11K_SMALL_DP_RINGS=y +# CONFIG_ATH11K_QCN9074_FIXED_MEM_REGION is not set +CONFIG_ATH12K=m +CONFIG_ATH12K_DEBUG=y +CONFIG_ATH12K_DEBUGFS=y +CONFIG_ATH12K_MEM_PROFILE_512M=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_PURELIFI is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_SILABS is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_VIRT_WIFI is not set +# CONFIG_WAN is not set + +# +# Wireless WAN +# +# CONFIG_WWAN is not set +# end of Wireless WAN + +# CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CYPRESS_SF is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_DA7280_HAPTICS is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_IQS269A is not set +# CONFIG_INPUT_IQS626A is not set +# CONFIG_INPUT_IQS7222 is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_SMSC_CAP1066 is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_LEGACY_TIOCSTI is not set +# CONFIG_LDISC_AUTOLOAD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set +CONFIG_SERIAL_BCM63XX_HS=m +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_SPRD is not set +# end of Serial drivers + +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_HVC_DCC is not set +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_BCM2835 is not set +# CONFIG_HW_RANDOM_BCM63XX is not set +# CONFIG_HW_RANDOM_OPTEE is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +# CONFIG_HW_RANDOM_XIPHERA is not set +# CONFIG_HW_RANDOM_ARM_SMCCC_TRNG is not set +# CONFIG_HW_RANDOM_CN10K is not set +# CONFIG_APPLICOM is not set +# CONFIG_DEVMEM is not set +# CONFIG_DEVPHYSMEM is not set +# CONFIG_DEVPORT is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set +# CONFIG_XILLYUSB is not set +# end of Character devices + +# +# Diag Support +# +# CONFIG_DIAG_CHAR is not set +# end of Diag Support + +# +# DIAG traffic over USB +# +# end of DIAG traffic over USB + +# +# DIAG traffic over QRTR +# +# end of DIAG traffic over QRTR + +# +# HSIC/SMUX support for DIAG +# +# end of HSIC/SMUX support for DIAG + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_BRCMSTB=y +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +# CONFIG_I2C_HISI is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_THUNDERX is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set +# CONFIG_I2C_PCI1XXXX is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_VIRTIO is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BCM63XX_HSSPI=y +# CONFIG_SPI_BCM_QSPI is not set +# CONFIG_SPI_BCMBCA_HSSPI is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_MICROCHIP_CORE is not set +# CONFIG_SPI_MICROCHIP_CORE_QSPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PCI1XXXX is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_SN_F_OSPI is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_THUNDERX is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPI_AMD is not set + +# +# SPI Multiplexer support +# +# CONFIG_SPI_MUX is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_DYNAMIC=y +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PTP_1588_CLOCK_OPTIONAL=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_CY8C95X0 is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_BCM4908 is not set +CONFIG_PINCTRL_BCM63138=y + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_CDEV=y +# CONFIG_GPIO_CDEV_V1 is not set + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HISI is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SIFIVE is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADNP is not set +CONFIG_GPIO_FBXGWR_PMU=y +# CONFIG_GPIO_FXL6408 is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# +# Virtual GPIO drivers +# +# CONFIG_GPIO_AGGREGATOR is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_MOCKUP is not set +# CONFIG_GPIO_SIM is not set +# end of Virtual GPIO drivers + +CONFIG_FREEBOX_GPIO=y +CONFIG_FREEBOX_GPIO_DT=y +# CONFIG_FREEBOX_JTAG is not set +# CONFIG_W1 is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_XGENE is not set +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +# CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_POWER_SUPPLY_HWMON is not set +# CONFIG_IP5XXX_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SAMSUNG_SDI is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_LTC4162L is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_MAX77976 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ2515X is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +# CONFIG_CHARGER_BQ256XX is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_RT5033 is not set +# CONFIG_CHARGER_RT9455 is not set +# CONFIG_CHARGER_BD99954 is not set +# CONFIG_BATTERY_UG3105 is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +CONFIG_SENSORS_ADT7475=y +# CONFIG_SENSORS_AHT10 is not set +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set +CONFIG_SENSORS_FBXGWR_PMU=y +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set +# CONFIG_SENSORS_LTC2947_SPI is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC2992 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX31730 is not set +# CONFIG_SENSORS_MAX31760 is not set +# CONFIG_SENSORS_MAX6620 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MC34VR500 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set +# CONFIG_SENSORS_MR75203 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT6775_I2C is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SBTSI is not set +# CONFIG_SENSORS_SBRMI is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHT4x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC2305 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA238 is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP464 is not set +# CONFIG_SENSORS_TMP513 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_LD6710_FBX=m +# CONFIG_SENSORS_AP806 is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +# CONFIG_THERMAL_HWMON is not set +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +# CONFIG_CPU_THERMAL is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_MMIO is not set + +# +# Broadcom thermal drivers +# +# end of Broadcom thermal drivers + +CONFIG_FREEBOX_WATCHDOG=y +# CONFIG_FREEBOX_WATCHDOG_CHAR is not set +CONFIG_FREEBOX_WATCHDOG_BCM63XX_OF=y +# CONFIG_FREEBOX_WATCHDOG_FBXGWR_PMU is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_SMPRO is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX597X is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77714 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_SY7636A is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT4831 is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RT5120 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_FBXGW7R_PANEL is not set +CONFIG_MFD_FBXGWR_PMU=y +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_RAVE_SP_CORE is not set +# CONFIG_MFD_INTEL_M10_BMC_SPI is not set +# CONFIG_MFD_RSMU_I2C is not set +# CONFIG_MFD_RSMU_SPI is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +CONFIG_RC_CORE=y +# CONFIG_LIRC is not set +# CONFIG_RC_MAP is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_DEVICES is not set + +# +# CEC support +# +# CONFIG_MEDIA_CEC_SUPPORT is not set +# end of CEC support + +CONFIG_MEDIA_SUPPORT=y +# CONFIG_MEDIA_SUPPORT_FILTER is not set +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set + +# +# Media device types +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_SDR_SUPPORT=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_TEST_SUPPORT=y +# end of Media device types + +# +# Media core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_MEDIA_CONTROLLER is not set +CONFIG_DVB_CORE=y +# end of Media core support + +# +# Digital TV options +# +# CONFIG_DVB_NET is not set +CONFIG_DVB_MAX_ADAPTERS=8 +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set +# end of Digital TV options + +# +# Media drivers +# + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# + +# +# Analog TV USB devices +# + +# +# Analog/digital TV USB devices +# + +# +# Digital TV USB devices +# +# CONFIG_DVB_AS102 is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +CONFIG_DVB_USB_V2=y +# CONFIG_DVB_USB_AF9015 is not set +CONFIG_DVB_USB_AF9035=m +# CONFIG_DVB_USB_ANYSEE is not set +# CONFIG_DVB_USB_AU6610 is not set +# CONFIG_DVB_USB_AZ6007 is not set +# CONFIG_DVB_USB_CE6230 is not set +# CONFIG_DVB_USB_DVBSKY is not set +# CONFIG_DVB_USB_EC168 is not set +# CONFIG_DVB_USB_GL861 is not set +# CONFIG_DVB_USB_LME2510 is not set +# CONFIG_DVB_USB_MXL111SF is not set +# CONFIG_DVB_USB_RTL28XXU is not set +# CONFIG_DVB_USB_ZD1301 is not set +CONFIG_DVB_USB=y +# CONFIG_DVB_USB_DEBUG is not set +# CONFIG_DVB_USB_A800 is not set +# CONFIG_DVB_USB_AF9005 is not set +# CONFIG_DVB_USB_AZ6027 is not set +# CONFIG_DVB_USB_CINERGY_T2 is not set +# CONFIG_DVB_USB_CXUSB is not set +CONFIG_DVB_USB_DIB0700=m +# CONFIG_DVB_USB_DIBUSB_MB is not set +# CONFIG_DVB_USB_DIBUSB_MC is not set +# CONFIG_DVB_USB_DIGITV is not set +# CONFIG_DVB_USB_DTT200U is not set +# CONFIG_DVB_USB_DTV5100 is not set +# CONFIG_DVB_USB_DW2102 is not set +# CONFIG_DVB_USB_GP8PSK is not set +# CONFIG_DVB_USB_M920X is not set +# CONFIG_DVB_USB_NOVA_T_USB2 is not set +# CONFIG_DVB_USB_OPERA1 is not set +# CONFIG_DVB_USB_PCTV452E is not set +# CONFIG_DVB_USB_TECHNISAT_USB2 is not set +# CONFIG_DVB_USB_TTUSB2 is not set +# CONFIG_DVB_USB_UMT_010 is not set +# CONFIG_DVB_USB_VP702X is not set +# CONFIG_DVB_USB_VP7045 is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set + +# +# Webcam, TV (analog/digital) USB devices +# + +# +# Software defined radio USB devices +# +# CONFIG_MEDIA_PCI_SUPPORT is not set +# CONFIG_MEDIA_PLATFORM_DRIVERS is not set + +# +# MMC/SDIO DVB adapters +# +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_CYPRESS_FIRMWARE=y +# end of Media drivers + +# +# Media ancillary drivers +# +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +CONFIG_MEDIA_TUNER_IT913X=m +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_TDA18250 is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC4000 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_M88DS3103=m +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set + +# +# Multistandard (cable + terrestrial) frontends +# +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_TDA18271C2DD is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_TDA10071 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_AF9013=m +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_NXT6000 is not set +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +# CONFIG_DVB_S5H1432 is not set +CONFIG_DVB_SI2168=m +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_CXD2880 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_STV0297 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_VES1820 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_LGDT3305 is not set +CONFIG_DVB_LGDT3306A=m +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_MXL692 is not set +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_S5H1411 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set +# CONFIG_DVB_S921 is not set + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_MN88443X is not set +# CONFIG_DVB_TC90522 is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +CONFIG_DVB_TUNER_DIB0070=m +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_A8293 is not set +CONFIG_DVB_AF9033=m +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_DRX39XYJ is not set + +# +# Common Interface (EN50221) controller drivers +# +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set +# end of Customise DVB Frontends + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# end of Media ancillary drivers + +# +# Graphics support +# +CONFIG_VIDEO_CMDLINE=y +# CONFIG_DRM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set + +# +# ARM devices +# +# end of ARM devices + +# +# Frame buffer Devices +# +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_BACKLIGHT=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +CONFIG_FB_SSD1320=y +# CONFIG_FB_SSD1327 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTZ8866 is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# CONFIG_BACKLIGHT_LED is not set +# end of Backlight & LCD device support + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +# CONFIG_HID_GENERIC is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_EVISION is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set +# CONFIG_HID_VIVALDI is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_VRC2 is not set +# CONFIG_HID_XIAOMI is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NINTENDO is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PXRC is not set +# CONFIG_HID_RAZER is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SEMITEK is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_TOPRE is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# HID-BPF support +# +# end of HID-BPF support + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +# CONFIG_I2C_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_PCI is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +# CONFIG_USB_XHCI_PCI_RENESAS is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_BCM63158=m +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set + +# +# USB dual-mode controller drivers +# +# CONFIG_USB_CDNS_SUPPORT is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set +# CONFIG_USB_ONBOARD_HUB is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_HSQ is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +CONFIG_MMC_SDHCI_BRCMSTB=y +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_FBXGWR_PMU=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP50XX is not set +# CONFIG_LEDS_LP55XX_COMMON is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set +# CONFIG_LEDS_IS31FL3299 is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_LED1202 is not set + +# +# Flash and Torch LED drivers +# + +# +# RGB LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set + +# +# Simple LED drivers +# +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VDPA is not set +# CONFIG_VHOST_MENU is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +# CONFIG_SURFACE_PLATFORMS is not set +# CONFIG_FBXGW7R_PLATFORM is not set +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Clock driver for ARM Reference designs +# +# CONFIG_CLK_ICST is not set +# CONFIG_CLK_SP810 is not set +# end of Clock driver for ARM Reference designs + +# CONFIG_LMK04832 is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_AXI_CLKGEN is not set +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_RS9_PCIE is not set +# CONFIG_COMMON_CLK_SI521XX is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_VC7 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_CLK_BCM_63XX is not set +# CONFIG_XILINX_VCU is not set +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_ARM64_ERRATUM_858921=y +# end of Clock Source drivers + +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Broadcom SoC drivers +# +CONFIG_SOC_BCM63XX=y +# CONFIG_SOC_BRCMSTB is not set +# CONFIG_SOC_BCM63XX_RDP is not set +CONFIG_SOC_BCM63XX_XRDP=y +# CONFIG_SOC_BCM63XX_XRDP_IOCTL is not set +CONFIG_UBUS4_BCM63158=y +CONFIG_SOC_MEMC_BCM63158=m +CONFIG_PROCMON_BCM63158=y +# CONFIG_BCM_PMB is not set +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# CONFIG_QUICC_ENGINE is not set +# end of NXP/Freescale QorIQ SoC drivers + +# +# fujitsu SoC drivers +# +# end of fujitsu SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Enable LiteX SoC Builder specific drivers +# +# CONFIG_LITEX_SOC_CONTROLLER is not set +# end of Enable LiteX SoC Builder specific drivers + +# CONFIG_WPCM450_SOC is not set + +# +# Qualcomm SoC drivers +# +CONFIG_QCOM_QMI_HELPERS=y +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set +# CONFIG_XILINX_INTC is not set +CONFIG_PARTITION_PERCPU=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_SIMPLE is not set +# CONFIG_RESET_TI_SYSCON is not set +# CONFIG_RESET_TI_TPS380X is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_PHY_CAN_TRANSCEIVER is not set +CONFIG_XDSL_PHY_API=m + +# +# PHY drivers for Broadcom platforms +# +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_BRCM_USB_63138 is not set +# CONFIG_PHY_BRCM_SATA is not set +# CONFIG_PHY_BRCM_USB is not set +# end of PHY drivers for Broadcom platforms + +# CONFIG_PHY_CADENCE_TORRENT is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_DPHY_RX is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_CADENCE_SALVO is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_LAN966X_SERDES is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +# CONFIG_ARM_CMN is not set +CONFIG_ARM_PMU=y +CONFIG_ARM_PMUV3=y +# CONFIG_ARM_DSU_PMU is not set +# CONFIG_ARM_SPE_PMU is not set +# CONFIG_HISI_PCIE_PMU is not set +# CONFIG_HNS3_PMU is not set +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_USB4 is not set + +# +# Android +# +# CONFIG_ANDROID_BINDER_IPC is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# Layout Types +# +# CONFIG_NVMEM_LAYOUT_SL28_VPD is not set +# CONFIG_NVMEM_LAYOUT_ONIE_TLV is not set +# end of Layout Types + +# CONFIG_NVMEM_IGNORE_RO is not set +# CONFIG_NVMEM_RMEM is not set +# CONFIG_NVMEM_U_BOOT_ENV is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# CONFIG_HISI_PTT is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +CONFIG_TEE=y +CONFIG_OPTEE=y +# CONFIG_OPTEE_INSECURE_LOAD_IMAGE is not set +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# CONFIG_MOST is not set +# CONFIG_PECI is not set +# CONFIG_HTE is not set +# CONFIG_CDX_BUS is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +CONFIG_LEGACY_DIRECT_IO=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_SUPPORT_V4 is not set +CONFIG_XFS_SUPPORT_ASCII_CI=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/EXFAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=850 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +# CONFIG_NTFS3_FS is not set +CONFIG_EXFAT_FS_FBX=y +# end of DOS/FAT/EXFAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_TMPFS_INODE64 is not set +CONFIG_ARCH_SUPPORTS_HUGETLBFS=y +# CONFIG_HUGETLBFS is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +CONFIG_HFS_FS=y +CONFIG_HFSPLUS_FS=y +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +CONFIG_CRAMFS_BLOCKDEV=y +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU is not set +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZSTD is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +# CONFIG_PSTORE_DEFLATE_COMPRESS is not set +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=y +# CONFIG_PSTORE_BLK is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set +CONFIG_NFSD=y +# CONFIG_NFSD_V2 is not set +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +# CONFIG_NFSD_BLOCKLAYOUT is not set +# CONFIG_NFSD_SCSILAYOUT is not set +# CONFIG_NFSD_FLEXFILELAYOUT is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +CONFIG_SMB_SERVER=y +CONFIG_SMB_INSECURE_SERVER=y +CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y +# CONFIG_SMB_SERVER_KERBEROS5 is not set +CONFIG_SMBFS=y +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_TRUSTED_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization + +CONFIG_RANDSTRUCT_NONE=y +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set +# end of Crypto core or helper + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECDSA=y +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# end of Public-key cryptography + +# +# Block ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ARIA is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_TWOFISH is not set +# end of Block ciphers + +# +# Length-preserving ciphers and modes +# +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_CHACHA20=y +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_HCTR2 is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# end of Length-preserving ciphers and modes + +# +# AEAD (authenticated encryption with associated data) ciphers +# +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_CHACHA20POLY1305=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y +CONFIG_CRYPTO_ESSIV=y +# end of AEAD (authenticated encryption with associated data) ciphers + +# +# Hashes, digests, and MACs +# +# CONFIG_CRYPTO_BLAKE2B is not set +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_POLY1305=y +# CONFIG_CRYPTO_RMD160 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=y +# CONFIG_CRYPTO_SM3_GENERIC is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_VMAC is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_XXHASH is not set +# end of Hashes, digests, and MACs + +# +# CRCs (cyclic redundancy checks) +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# end of CRCs (cyclic redundancy checks) + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set +# end of Compression + +# +# Random number generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# end of Random number generation + +# +# Userspace interface +# +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# end of Userspace interface + +CONFIG_CRYPTO_HASH_INFO=y +# CONFIG_CRYPTO_NHPOLY1305_NEON is not set +CONFIG_CRYPTO_CHACHA20_NEON=y + +# +# Accelerated Cryptographic Algorithms for CPU (arm64) +# +# CONFIG_CRYPTO_GHASH_ARM64_CE is not set +CONFIG_CRYPTO_POLY1305_NEON=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA256_ARM64=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64=y +CONFIG_CRYPTO_SHA512_ARM64_CE=y +# CONFIG_CRYPTO_SHA3_ARM64 is not set +# CONFIG_CRYPTO_SM3_NEON is not set +# CONFIG_CRYPTO_SM3_ARM64_CE is not set +# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y +# CONFIG_CRYPTO_AES_ARM64_BS is not set +# CONFIG_CRYPTO_SM4_ARM64_CE is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set +# end of Accelerated Cryptographic Algorithms for CPU (arm64) + +# CONFIG_CRYPTO_HW is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y +# CONFIG_INDIRECT_PIO is not set + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y +CONFIG_CRYPTO_LIB_CURVE25519=y +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 +CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_POLY1305_GENERIC=y +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +# end of Crypto library routines + +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC64_ROCKSOFT is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +# CONFIG_XZ_DEC_SPARC is not set +# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_RESTRICTED_POOL is not set +CONFIG_DMA_NONCOHERENT_MMAP=y +CONFIG_DMA_COHERENT_POOL=y +CONFIG_DMA_DIRECT_REMAP=y +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +CONFIG_SGL_ALLOC=y +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y +CONFIG_SG_POOL=y +CONFIG_ARCH_STACKWALK=y +CONFIG_STACKDEPOT=y +CONFIG_STACKDEPOT_ALWAYS_INIT=y +CONFIG_SBITMAP=y +CONFIG_ARCH_HAS_FBXSERIAL=y +CONFIG_FBXSERIAL=y +# end of Library routines + +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DYNAMIC_DEBUG_CORE is not set +# CONFIG_SYMBOLIC_ERRNAME is not set +CONFIG_DEBUG_BUGVERBOSE=y +# end of printk and dmesg options + +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_MISC is not set + +# +# Compile-time checks and compiler options +# +CONFIG_AS_HAS_NON_CONST_LEB128=y +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +# +# Generic Kernel Debugging Instruments +# +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y +# end of Generic Kernel Debugging Instruments + +# +# Networking Debugging +# +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set +# end of Networking Debugging + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_TABLE_CHECK is not set +CONFIG_PAGE_POISONING=y +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 +# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set +# CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN is not set +# CONFIG_PER_VMA_LOCK_STATS is not set +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_SELFTEST=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y +CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 +# CONFIG_SHRINKER_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +CONFIG_DEBUG_VM_IRQSOFF=y +CONFIG_DEBUG_VM=y +# CONFIG_DEBUG_VM_MAPLE_TREE is not set +CONFIG_DEBUG_VM_RB=y +CONFIG_DEBUG_VM_PGFLAGS=y +# CONFIG_DEBUG_VM_PGTABLE is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_DEBUG_VIRTUAL=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y +# CONFIG_KASAN is not set +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set +# end of Memory Debugging + +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Oops, Lockups and Hangs +# +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SOFTLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs + +# +# Scheduler Debugging +# +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# end of Scheduler Debugging + +CONFIG_DEBUG_TIMEKEEPING=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +# CONFIG_DEBUG_IRQFLAGS is not set +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set + +# +# Debug kernel data structures +# +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_PLIST is not set +CONFIG_DEBUG_SG=y +CONFIG_DEBUG_NOTIFIERS=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +# end of Debug kernel data structures + +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set + +# +# arm64 Debugging +# +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of arm64 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage + +# +# Rust hacking +# +# end of Rust hacking +# end of Kernel hacking diff -Nruw linux-6.4-fbx/drivers/char/diag./Kconfig linux-6.4-fbx/drivers/char/diag/Kconfig --- linux-6.4-fbx/drivers/char/diag./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/char/diag/Kconfig 2023-03-15 19:52:23.513979080 +0100 @@ -0,0 +1,38 @@ +menu "Diag Support" + +config DIAG_CHAR + tristate "char driver interface and diag forwarding to/from modem" + select CRC_CCITT + help + Char driver interface for diag user space and diag-forwarding to modem ARM and back. + This enables diagchar for maemo usb gadget or android usb gadget based on config selected. +endmenu + +menu "DIAG traffic over USB" + +config DIAG_OVER_USB + bool "Enable DIAG traffic to go over USB" + depends on DIAG_CHAR + help + This feature helps segregate code required for DIAG traffic to go over USB. +endmenu + +menu "DIAG traffic over QRTR" + +config DIAG_OVER_QRTR + bool "Enable DIAG traffic to go over QRTR" + depends on QRTR && DIAG_CHAR + default n + help + This feature helps segregate code required for DIAG traffic to go over QRTR. +endmenu + +menu "HSIC/SMUX support for DIAG" + +config DIAGFWD_BRIDGE_CODE + bool "Enable QSC/9K DIAG traffic over SMUX/HSIC" + depends on DIAG_CHAR + depends on USB_QCOM_DIAG_BRIDGE || MHI_BUS + help + SMUX/HSIC Transport Layer for DIAG Router +endmenu diff -Nruw linux-6.4-fbx/drivers/char/diag./Makefile linux-6.4-fbx/drivers/char/diag/Makefile --- linux-6.4-fbx/drivers/char/diag./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/char/diag/Makefile 2023-03-15 19:52:23.513979080 +0100 @@ -0,0 +1,19 @@ +obj-$(CONFIG_DIAG_CHAR) := diagchar.o +obj-$(CONFIG_USB_QCOM_DIAG_BRIDGE) += diagfwd_hsic.o +obj-$(CONFIG_USB_QCOM_DIAG_BRIDGE) += diagfwd_smux.o +diagchar-objs := diagchar_core.o diagchar_hdlc.o diagfwd.o diagfwd_peripheral.o diag_mux.o diag_memorydevice.o diag_usb.o diagmem.o diagfwd_cntl.o diag_dci.o diag_masks.o diag_debugfs.o + +ifdef CONFIG_DIAG_OVER_QRTR +diagchar-objs += qcom_diagfwd_socket.o +else +diagchar-objs += diagfwd_socket.o +endif + +ifdef CONFIG_DIAGFWD_BRIDGE_CODE +diagchar-objs += diagfwd_bridge.o + +ifdef CONFIG_MHI_BUS +diagchar-objs += diagfwd_mhi.o +endif + +endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/cpufreq/bcm63158-cpufreq.c 2023-03-13 12:20:28.102325213 +0100 @@ -0,0 +1,431 @@ +/* + * bcm63158-cpufreq.c for bcm63158-cpufreq + * Created by on Fri Jun 26 16:07:36 2020 + */ + +#include +#include +#include +#include +#include +#include + +#include + +struct bcm63158_cpufreq { + struct bcm63xx_pmc *pmc; + struct device *dev; + struct cpufreq_driver drv; + struct cpufreq_frequency_table *freq_table; +}; + +/* + * CPU frequency change on 63158 + */ +#define BIU_PLL_RESET_REG (0x4 << 2) +#define BIU_PLL_RESET_BYP_EN (1 << 20) +#define BIU_PLL_RESET_PLL_RST (1 << 3) + +#define BIU_PLL_PDIV_REG (0x8 << 2) +#define BIU_PLL_PDIV_NDIV_OVERRIDE (1 << 31) + +#define BIU_PLL_NDIV_REG (0x7 << 2) +#define BIU_PLL_NDIV_NDIV_MASK (0x3ff) + +#define BIU_PLL_POSTDIV_REG (0xb << 2) +#define BIU_PLL_POSTDIV_DIV0_MASK (0xff) +#define BIU_PLL_POSTDIV_DIV0_OVERRIDE (1 << 15) + +#define BIU_PLL_STAT_REG (0xf << 2) +#define BIU_PLL_STAT_PLL_LOCK (1 << 31) + +static void biu_pll_bypass_enable(struct bcm63xx_pmc *pmc, bool en) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, ®); + + if (en) + reg |= BIU_PLL_RESET_BYP_EN; + else + reg &= ~BIU_PLL_RESET_BYP_EN; + + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, reg); +} + +static bool biu_pll_get_bypass_enable(struct bcm63xx_pmc *pmc) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, ®); + return !!(reg & BIU_PLL_RESET_BYP_EN); +} + +static void biu_pll_reset_assert(struct bcm63xx_pmc *pmc, bool en) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, ®); + if (en) + reg |= BIU_PLL_RESET_PLL_RST; + else + reg &= ~BIU_PLL_RESET_PLL_RST; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, reg); +} + +static void biu_pll_set_ndiv_override(struct bcm63xx_pmc *pmc, bool en) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_PDIV_REG, ®); + if (en) + reg |= BIU_PLL_PDIV_NDIV_OVERRIDE; + else + reg &= ~BIU_PLL_PDIV_NDIV_OVERRIDE; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_PDIV_REG, reg); +} + +static u32 biu_pll_get_ndiv(struct bcm63xx_pmc *pmc) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_NDIV_REG, ®); + return reg & BIU_PLL_NDIV_NDIV_MASK; +} + +static void biu_pll_set_ndiv(struct bcm63xx_pmc *pmc, u32 ndiv) +{ + u32 reg; + + ndiv &= BIU_PLL_NDIV_NDIV_MASK; + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_NDIV_REG, ®); + reg &= ~BIU_PLL_NDIV_NDIV_MASK; + reg |= ndiv; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_NDIV_REG, reg); +} + +static u32 biu_pll_get_mdiv(struct bcm63xx_pmc *pmc) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + ®); + + return reg & BIU_PLL_POSTDIV_DIV0_MASK; +} + +static void biu_pll_set_mdiv(struct bcm63xx_pmc *pmc, u8 mdiv) +{ + u32 reg; + + if (mdiv == biu_pll_get_mdiv(pmc)) + return ; + + mdiv &= BIU_PLL_POSTDIV_DIV0_MASK; + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + ®); + reg &= ~BIU_PLL_POSTDIV_DIV0_OVERRIDE; + reg &= ~BIU_PLL_POSTDIV_DIV0_MASK; + reg |= mdiv; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + reg); + usleep_range(1000, 1200); + + reg |= BIU_PLL_POSTDIV_DIV0_OVERRIDE; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + reg); + usleep_range(10000, 12000); +} + +static int biu_pll_wait_lock(struct bcm63xx_pmc *pmc) +{ + int tries = 1000; + + do { + u32 reg; + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_STAT_REG, + ®); + + if (reg & BIU_PLL_STAT_PLL_LOCK) + break; + usleep_range(1000, 2000); + --tries; + } while (tries > 0); + + return tries > 0 ? 0 : -ETIMEDOUT; +} + +/* + * unless bypass clock is enabled, cpu frequency in mhz is: + * + * 50 * ndiv / mdiv + * + * mdiv is usually 2, unless for CPU speeds higher than 1675 mhz, in + * which case it is 1. + */ +static int pmc_cpufreq_get(struct bcm63158_cpufreq *priv) +{ + struct bcm63xx_pmc *pmc = priv->pmc; + u32 ndiv; + u32 mdiv; + + if (biu_pll_get_bypass_enable(pmc)) { + /* + * 400 mhz slow clock cpu clocking is active. + */ + return 400; + } + + ndiv = biu_pll_get_ndiv(pmc); + mdiv = biu_pll_get_mdiv(pmc); + return 50 * ndiv / mdiv; +} + +/* + * this will change the CPU speed to the requested frequency. + * + * valid frequencies are: 400, then 550 to 1675 mhz, frequency is + * rounted down to the nearest 25mhz. Frequencies from 1700 to 2200 + * mhz are possible, rounded down to the nearest 50 mhz. + * + * Frequencies from 1700 to 2200 Mhz are in the overclocking range and + * the CPU may not work reliably in that case. + */ +static int pmc_cpufreq_set(struct bcm63158_cpufreq *priv, unsigned int val) +{ + struct bcm63xx_pmc *pmc = priv->pmc; + u32 mdiv, ndiv; + int error; + u32 ndiv_lo, ndiv_hi; + + val /= 1000; + + if (val > 2200) + return -EINVAL; + + if (val > 1675) { + mdiv = 1; + ndiv_lo = 34; + ndiv_hi = 44; + } else { + mdiv = 2; + ndiv_lo = 22; + ndiv_hi = 67; + } + + ndiv = mdiv * val / 50; + + if ((ndiv < ndiv_lo || ndiv > ndiv_hi) && val != 400) { + dev_warn(priv->dev, "%u: unsupported frequency.\n", val); + return -EINVAL; + } + + /* + * enabling bypass clock will clock the CPU at 400 mhz from a + * clock that will remain stable while we configure the + * divisors. + */ + biu_pll_bypass_enable(pmc, true); + biu_pll_reset_assert(pmc, true); + + if (val == 400) + /* + * just leave the system with the slow clock strap + * frequency. + */ + return 0; + + /* + * set ndiv + */ + biu_pll_set_ndiv_override(pmc, true); + biu_pll_set_ndiv(pmc, ndiv); + + /* + * deassert PLL and wait for it to lock. + */ + biu_pll_reset_assert(pmc, false); + error = biu_pll_wait_lock(pmc); + if (error) { + /* + * if the pll fails to lock it looks like the system + * will be left in a usable state as long as we keep + * the bypass enabled. cpu freq will be 400 Mhz, the + * slow clock strap freq. + */ + dev_crit(priv->dev, "BIU pll failed to lock. " + "leaving PLL bypass enabled (%u Mhz was wanted).\n", + val); + return error; + } + + /* + * set post divider (mdiv) + */ + biu_pll_set_mdiv(pmc, mdiv); + + /* + * disable clock bypass, the cpu will after be clocked at the + * requested frequency. + */ + biu_pll_bypass_enable(pmc, false); + return 0; +} + +static int bcm63158_cpufreq_init(struct cpufreq_policy *policy) +{ + struct bcm63158_cpufreq *priv = cpufreq_get_driver_data(); + + policy->cpuinfo.max_freq = 1675000; + policy->cpuinfo.min_freq = 400000; + policy->cur = pmc_cpufreq_get(priv) * 1000; + policy->cpuinfo.transition_latency = 20 * 1000 * 1000; /* 20 msec */ + policy->freq_table = priv->freq_table; + policy->driver_data = cpufreq_get_driver_data(); + + /* + * All cores share the same clock and thus the same policy. + */ + cpumask_setall(policy->cpus); + + return 0; +} + +static int bcm63158_cpufreq_target_index(struct cpufreq_policy *policy, + unsigned int index) +{ + struct bcm63158_cpufreq *priv = policy->driver_data; + + pmc_cpufreq_set(priv, policy->freq_table[index].frequency); + return 0; +} + +static int add_freq_entry(struct cpufreq_frequency_table *tbl, + unsigned int freq_mhz, size_t *cur, size_t size) +{ + if (*cur >= size) { + pr_err("unable to add frequency %u to table: no room left.\n", + freq_mhz); + return -ENOSPC; + } + + tbl = &tbl[*cur]; + tbl->frequency = freq_mhz ? (freq_mhz * 1000) : CPUFREQ_TABLE_END; + ++(*cur); + return 0; +} + +/* + * NOTE: the hardware could do 550 Mhz, but in some case the BIU PLL + * won't lock at that frequency. just don't advertise 550 Mhz in the + * frequency table. + */ +#define FREQ_LOW 575 +#define FREQ_HI 1575 + +/* + * the hardware can work in 25 mhz frequency increments, but it's + * probably not needed that much to have this kind of granularity. + * + * Also the 45 possible frequencies make it that the stats/trans_table + * sysfs attribute cannot work due to its content being larger than 4k + * (the max for sysfs attributes). + * + * allow all frequencies between FREQ_LO and FREQ_HI in 100 mhz + * increment as a result. + */ +#define FREQ_INC 100 + +static int bcm63158_cpufreq_build_table(struct bcm63158_cpufreq *priv) +{ + size_t nr_freqs; + size_t cur_freq; + unsigned int freq; + struct cpufreq_frequency_table *table; + int error; + + nr_freqs = (FREQ_HI - FREQ_LOW) / FREQ_INC + 1; + nr_freqs += 2; /* account for 400 mhz entry and end element */ + + table = devm_kzalloc(priv->dev, sizeof (*table) * nr_freqs, + GFP_KERNEL); + if (!table) + return -ENOMEM; + + cur_freq = 0; + error = add_freq_entry(table, 400, &cur_freq, nr_freqs); + if (error) + return error; + + for (freq = FREQ_LOW; freq <= FREQ_HI; freq += FREQ_INC) { + error = add_freq_entry(table, freq, &cur_freq, nr_freqs); + if (error) + return error; + } + + error = add_freq_entry(table, 0, &cur_freq, nr_freqs); + if (error) + return error; + + priv->freq_table = table; + return 0; +} + +static int bcm63158_cpufreq_probe(struct platform_device *pdev) +{ + struct bcm63158_cpufreq *priv; + int err; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pmc = pmc_of_get(pdev->dev.of_node); + if (IS_ERR(priv)) + return PTR_ERR(priv); + + + dev_set_drvdata(&pdev->dev, priv); + + strlcpy(priv->drv.name, "bcm63158-cpufreq", sizeof (priv->drv.name)); + priv->drv.init = bcm63158_cpufreq_init; + priv->drv.verify = cpufreq_generic_frequency_table_verify; + priv->drv.target_index = bcm63158_cpufreq_target_index; + priv->drv.driver_data = priv; + priv->drv.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; + priv->dev = &pdev->dev; + + err = bcm63158_cpufreq_build_table(priv); + if (err) + return err; + + return cpufreq_register_driver(&priv->drv); +} + +static int __exit bcm63158_cpufreq_remove(struct platform_device *pdev) +{ + struct bcm63158_cpufreq *priv = dev_get_drvdata(&pdev->dev); + + cpufreq_unregister_driver(&priv->drv); + return 0; +} + +static const struct of_device_id bcm63158_cpufreq_of_match[] = { + { .compatible = "brcm,bcm63158-cpufreq" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63158_cpufreq_of_match); + +static struct platform_driver bcm63158_cpufreq_pdriver = { + .driver = { + .name = "bcm63158-cpufreq", + .of_match_table = bcm63158_cpufreq_of_match, + }, + .probe = bcm63158_cpufreq_probe, + .remove = bcm63158_cpufreq_remove, +}; +module_platform_driver(bcm63158_cpufreq_pdriver); + +MODULE_AUTHOR("Nicolas Schichan +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "fbxgpio_core: " + +/* #define DEBUG */ +#ifdef DEBUG +#define dprint(Fmt, Arg...) printk(PFX Fmt, Arg) +#else +#define dprint(Fmt, Arg...) do { } while (0) +#endif + +static struct class *fbxgpio_class; + +/* + * retrieval of a struct fbxgpio_pin from a phandle in the device + * tree. + * + * can be removed when fbxjtag uses standard gpio library instead of + * fbxgpio + */ +struct fbxgpio_of_mach_data { + struct fbxgpio_pin *match; + struct device_node *np; +}; + +static int match_fbxgpio_of_node(struct device *dev, void *data) +{ + struct fbxgpio_of_mach_data *md = data; + struct fbxgpio_pin *pin = dev_get_drvdata(dev); + + if (pin->of_node == md->np) { + md->match = pin; + return 1; + } + return 0; +} + +struct fbxgpio_pin *fbxgpio_of_get(struct device_node *np, const char *propname, + int index) +{ + struct fbxgpio_of_mach_data md; + + /* + * get the pin device_node. + */ + md.match = NULL; + md.np = of_parse_phandle(np, propname, index); + if (!md.np) + return ERR_PTR(-ENOENT); + + /* + * find the struct fbxgpio_pin behind that device_node. + */ + class_for_each_device(fbxgpio_class, NULL, &md, + match_fbxgpio_of_node); + + return md.match ? md.match : ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(fbxgpio_of_get); + +/* + * can be removed when fbxjtag uses standard gpio library instead of + * fbxgpio + */ +int fbxgpio_set_data_out(struct fbxgpio_pin *p, int val) +{ + struct gpio_desc *desc; + + p->cur_dataout = val; + + if (p->use_desc) { + desc = p->request_desc(p); + if (IS_ERR(desc)) + return PTR_ERR(desc); + gpiod_set_value_cansleep(desc, val); + p->release_desc(p); + } else { + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + gpio_set_value_cansleep(p->pin_num, val); + } + return 0; +} + +EXPORT_SYMBOL(fbxgpio_set_data_out); + +/* + * can be removed when fbxjtag uses standard gpio library instead of + * fbxgpio + */ +int fbxgpio_get_data_in(struct fbxgpio_pin *p) +{ + const struct gpio_desc *desc; + int val; + + if (p->use_desc) { + desc = p->request_desc(p); + if (IS_ERR(desc)) + return PTR_ERR(desc); + + val = gpiod_get_value_cansleep(desc); + p->release_desc(p); + } else { + val = gpio_get_value_cansleep(p->pin_num); + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + } + + return val; +} + +EXPORT_SYMBOL(fbxgpio_get_data_in); + +/* + * show direction in for gpio associated with class_device dev. + */ +static ssize_t show_direction(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + int dir, ret = 0; + + p = dev_get_drvdata(dev); + + dir = p->direction; + + switch (dir) { + case GPIO_DIR_IN: + ret += sprintf(buf, "input\n"); + break; + case GPIO_DIR_OUT: + ret += sprintf(buf, "output\n"); + break; + default: + ret += sprintf(buf, "unknown\n"); + break; + } + return ret; +} + +/* + * show input data for input gpio pins. + */ +static ssize_t show_datain(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + int val; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_OUT) + return -EINVAL; + + val = fbxgpio_get_data_in(p); + return sprintf(buf, "%i\n", val); +} + +/* + * show output data for output gpio pins. + */ +static ssize_t show_dataout(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_IN) + return -EINVAL; + + val = p->cur_dataout; + return sprintf(buf, "%i\n", val); +} + +/* + * store new dataout value for output gpio pins. + */ +static ssize_t store_dataout(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct fbxgpio_pin *p; + int val; + + if (*buf == ' ' || *buf == '\t' || *buf == '\r' || *buf == '\n') + /* silently eat any spaces/tab/linefeed/carriagereturn */ + return 1; + + p = dev_get_drvdata(dev); + + if (p->direction != GPIO_DIR_OUT) + return -EINVAL; + + switch (*buf) { + case '0': + val = 0; + break ; + case '1': + val = 1; + break ; + default: + return -EINVAL; + } + + fbxgpio_set_data_out(p, val); + return 1; +} + +/* + * attribute list associated with each class device. + */ +static struct device_attribute gpio_attributes[] = { + __ATTR(direction, 0400, show_direction, NULL), + __ATTR(data_in, 0400, show_datain, NULL), + __ATTR(data_out, 0600, show_dataout, store_dataout), +}; + +static int fbxgpio_register_pin(struct platform_device *ppdev, + struct fbxgpio_pin *pin) +{ + struct device *dev; + int i, ret; + + if (pin->use_desc && (!pin->request_desc || !pin->release_desc)) + return -EINVAL; + + dprint("registering pin %s\n", pin->pin_name); + + dev = device_create(fbxgpio_class, &ppdev->dev, 0, pin, + "%s", pin->pin_name); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) { + ret = device_create_file(dev, &gpio_attributes[i]); + if (ret) + goto err_out; + } + + pin->dev = dev; + return 0; + +err_out: + for (; i >= 0; i--) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); + return ret; +} + +static void fbxgpio_unregister_pin(struct fbxgpio_pin *pin) +{ + struct device *dev; + int i; + + dprint("unregistering pin %s\n", pin->pin_name); + dev = pin->dev; + pin->dev = NULL; + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); +} + +static int fbxgpio_platform_probe(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + int err = 0; + + p = pdev->dev.platform_data; + while (p->pin_name) { + err = fbxgpio_register_pin(pdev, p); + if (err) + return err; + ++p; + } + return 0; +} + +static int fbxgpio_platform_remove(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + + p = pdev->dev.platform_data; + while (p->pin_name) { + fbxgpio_unregister_pin(p); + ++p; + } + return 0; +} + +static struct platform_driver fbxgpio_platform_driver = +{ + .probe = fbxgpio_platform_probe, + .remove = fbxgpio_platform_remove, + .driver = { + .name = "fbxgpio", + } +}; + +static int __init fbxgpio_init(void) +{ + int ret; + + fbxgpio_class = class_create("fbxgpio"); + if (IS_ERR(fbxgpio_class)) + return PTR_ERR(fbxgpio_class); + + ret = platform_driver_register(&fbxgpio_platform_driver); + if (ret) { + printk(KERN_ERR PFX "unable to register fbxgpio driver.\n"); + class_destroy(fbxgpio_class); + return ret; + } + return 0; +} + +static void __exit fbxgpio_exit(void) +{ + platform_driver_unregister(&fbxgpio_platform_driver); + class_destroy(fbxgpio_class); +} + +subsys_initcall(fbxgpio_init); +module_exit(fbxgpio_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); diff -Nruw linux-6.4-fbx/drivers/fbxgpio./fbxgpio_dt.c linux-6.4-fbx/drivers/fbxgpio/fbxgpio_dt.c --- linux-6.4-fbx/drivers/fbxgpio./fbxgpio_dt.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxgpio/fbxgpio_dt.c 2023-05-22 20:06:38.183692610 +0200 @@ -0,0 +1,256 @@ +/* + * fbxgpio_dt.c for fbxgpio + * Created by on Tue Aug 1 14:01:01 2017 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static atomic_t last_id = ATOMIC_INIT(0); + +/* + * fbxgpio driver fetching gpios names and configuration from + * device-tree. + */ + +struct fbxgpio_dt_priv { + struct fbxgpio_pin *pins; + unsigned int npins; + + /* dynamically created platform_device for fbxgpio_core */ + struct platform_device *top_pdev; +}; + +/* + * + */ +static struct gpio_desc *request_desc_cb(struct fbxgpio_pin *pin) +{ + struct gpio_desc *desc; + int ret; + + if (!pin->dt.no_claim) { + /* was requested earlier */ + return pin->dt.desc; + } + + /* try to request it for real first */ + desc = fwnode_gpiod_get_index(of_fwnode_handle(pin->of_node), + NULL, 0, pin->dt.flags, + pin->dt.pin_name); + if (!IS_ERR(desc)) { + /* we want to release it later */ + pin->dt.desc = desc; + return desc; + } + + ret = PTR_ERR(desc); + if (ret != -EBUSY) + return desc; + + /* device is busy, which is expected for no-claim, just fetch + * a "light" reference, which we won't need to put */ + return fwnode_gpiod_get_index(of_fwnode_handle(pin->of_node), + NULL, 0, GPIOD_ASIS | + GPIOD_FLAGS_BIT_NONEXCLUSIVE, + pin->dt.pin_name); +} + +/* + * + */ +static void release_desc_cb(struct fbxgpio_pin *pin) +{ + if (pin->dt.no_claim && pin->dt.desc) { + gpiod_put(pin->dt.desc); + pin->dt.desc = NULL; + } +} + +/* + * fill an fbxgpio_pin with the configuration found in a device tree + * node. + * + * required properties are: + * - gpio: a phandle to a standard linux gpio. + * + * - the name of the node: the name of the gpio as it will appear under + * /sys/class/fbxgpio/ + * + * - //: how to declare gpio and + * actually setup it unless no-claim is given + * + * - : just declare gpio, but don't request & setup it + */ +static int fbxgpio_dt_fill_gpio(struct platform_device *pdev, + struct device_node *np, + struct fbxgpio_pin *pin) +{ + enum gpiod_flags flags; + int error; + + error = of_property_read_string(np, "name", &pin->pin_name); + if (error) { + dev_err(&pdev->dev, "gpio has no name.\n"); + return error; + } + + if (of_property_read_bool(np, "input")) { + pin->direction = GPIO_DIR_IN; + flags = GPIOD_IN; + } else if (of_property_read_bool(np, "output-low")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 0; + flags = GPIOD_OUT_LOW; + } else if (of_property_read_bool(np, "output-high")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 1; + flags = GPIOD_OUT_HIGH; + } else { + dev_err(&pdev->dev, + "no state specified for %s\n", + pin->pin_name); + return -EINVAL; + } + + pin->use_desc = true; + pin->of_node = np; + pin->dt.flags = flags; + pin->request_desc = request_desc_cb; + pin->release_desc = release_desc_cb; + scnprintf(pin->dt.pin_name, sizeof (pin->dt.pin_name), + "fbxgpio-dt/%s", pin->pin_name); + + if (of_property_read_bool(np, "no-claim")) { + /* will be requested on demain */ + pin->dt.no_claim = true; + return 0; + } + + pin->dt.desc = devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(np), + NULL, flags, pin->dt.pin_name); + if (IS_ERR(pin->dt.desc)) { + int ret = PTR_ERR(pin->dt.desc); + + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, + "unable to get gpio desc for %s: %d.\n", + pin->pin_name, ret); + return ret; + } + + return 0; +} + +static int fbxgpio_dt_probe(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv; + struct device_node *fbxgpio_node; + u32 cur_gpio; + int error = 0; + size_t priv_alloc_size; + int i; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, priv); + + /* + * first pass to get the number of struct fbxgpio_pin to + * allocate. + */ + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + ++priv->npins; + } + + /* + * allocate pins: use npins + 1 for zeroed end sentinel. + */ + priv_alloc_size = (priv->npins + 1) * sizeof (struct fbxgpio_pin); + priv->pins = devm_kzalloc(&pdev->dev, priv_alloc_size, GFP_KERNEL); + if (!priv->pins) + return -ENOMEM; + + /* + * second pass to fill the priv->pins array. + */ + cur_gpio = 0; + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + error = fbxgpio_dt_fill_gpio(pdev, fbxgpio_node, + &priv->pins[cur_gpio]); + if (error) + return error; + ++cur_gpio; + } + + dev_info(&pdev->dev, "%u gpios.\n", priv->npins); + + /* + * create and register a platform device for fbxgpio_core. + */ + priv->top_pdev = platform_device_register_data(&pdev->dev, + "fbxgpio", + atomic_inc_return(&last_id), + priv->pins, + priv_alloc_size); + + if (IS_ERR(priv->top_pdev)) { + dev_err(&pdev->dev, "unable to register fbxgpio platform " + "device: %ld\n", PTR_ERR(priv->top_pdev)); + return PTR_ERR(priv->top_pdev); + } + + for (i = 0; i < priv->npins; i++) { + struct fbxgpio_pin *pin = &priv->pins[i]; + + if (pin->direction == GPIO_DIR_OUT) + dev_dbg(&pdev->dev, + "%sgpio %s is output, default %d\n", + pin->dt.no_claim ? "unclaimed " : "", + pin->pin_name, pin->cur_dataout); + else + dev_dbg(&pdev->dev, + "%sgpio %s is input\n", + pin->dt.no_claim ? "unclaimed " : "", + pin->pin_name); + } + + return 0; +} + +static int fbxgpio_dt_remove(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv = dev_get_drvdata(&pdev->dev); + platform_device_unregister(priv->top_pdev); + return 0; +} + +static const struct of_device_id fbxgpio_dt_of_match_table[] = { + { .compatible = "fbx,fbxgpio" }, + { }, +}; +MODULE_DEVICE_TABLE(of, fbxgpio_dt_of_match_table); + +static struct platform_driver fbxgpio_dt_platform_driver = { + .probe = fbxgpio_dt_probe, + .remove = fbxgpio_dt_remove, + .driver = { + .name = "fbxgpio-dt", + .of_match_table = fbxgpio_dt_of_match_table, + }, +}; + +module_platform_driver(fbxgpio_dt_platform_driver); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("DT Freebox GPIO Driver"); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-6.4-fbx/drivers/fbxjtag./Kconfig linux-6.4-fbx/drivers/fbxjtag/Kconfig --- linux-6.4-fbx/drivers/fbxjtag./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxjtag/Kconfig 2023-03-09 15:06:11.348233797 +0100 @@ -0,0 +1,3 @@ +config FREEBOX_JTAG + tristate "Freebox JTAG control interface" + default n diff -Nruw linux-6.4-fbx/drivers/fbxjtag./Makefile linux-6.4-fbx/drivers/fbxjtag/Makefile --- linux-6.4-fbx/drivers/fbxjtag./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxjtag/Makefile 2023-03-09 15:06:11.348233797 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FREEBOX_JTAG) += fbxjtag.o diff -Nruw linux-6.4-fbx/drivers/fbxprocfs./Kconfig linux-6.4-fbx/drivers/fbxprocfs/Kconfig --- linux-6.4-fbx/drivers/fbxprocfs./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxprocfs/Kconfig 2023-02-27 19:50:21.524231407 +0100 @@ -0,0 +1,2 @@ +config FREEBOX_PROCFS + tristate "Freebox procfs interface" diff -Nruw linux-6.4-fbx/drivers/fbxprocfs./Makefile linux-6.4-fbx/drivers/fbxprocfs/Makefile --- linux-6.4-fbx/drivers/fbxprocfs./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxprocfs/Makefile 2023-02-27 19:50:21.524231407 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FREEBOX_PROCFS) += fbxprocfs.o diff -Nruw linux-6.4-fbx/drivers/fbxprocfs./fbxprocfs.c linux-6.4-fbx/drivers/fbxprocfs/fbxprocfs.c --- linux-6.4-fbx/drivers/fbxprocfs./fbxprocfs.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxprocfs/fbxprocfs.c 2023-05-22 20:06:38.183692610 +0200 @@ -0,0 +1,299 @@ +/* + * Freebox ProcFs interface + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PFX "fbxprocfs: " + + +static struct list_head clients; +static struct mutex clients_mutex; + +static struct proc_dir_entry *root; + +/* + * register a fbxprocfs client with given dirname, caller should + * consider returned struct opaque + */ +struct fbxprocfs_client *fbxprocfs_add_client(const char *dirname, + struct module *owner) +{ + struct fbxprocfs_client *ret, *p; + + ret = NULL; + mutex_lock(&clients_mutex); + + /* check for duplicate */ + list_for_each_entry(p, &clients, list) { + if (!strcmp(dirname, p->dirname)) + goto out; + } + + if (!(ret = kmalloc(sizeof (*ret), GFP_KERNEL))) { + printk(KERN_ERR PFX "kmalloc failed\n"); + goto out; + } + + /* try to create client directory */ + if (!(ret->dir = proc_mkdir(dirname, root))) { + printk(KERN_ERR PFX "can't create %s dir\n", dirname); + kfree(ret); + ret = NULL; + goto out; + } + + atomic_set(&ret->refcount, 1); + ret->dirname = dirname; + list_add(&ret->list, &clients); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * unregister a fbxprocfs client, make sure usage count is zero + */ +int fbxprocfs_remove_client(struct fbxprocfs_client *client) +{ + int ret; + + mutex_lock(&clients_mutex); + + ret = 0; + if (atomic_read(&client->refcount) > 1) { + ret = -EBUSY; + goto out; + } + + remove_proc_entry(client->dirname, root); + list_del(&client->list); + kfree(client); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * remove given entries from client directory + */ +static int +__remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + remove_proc_entry(ro_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + remove_proc_entry(rw_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + return 0; +} + +/* + * replacement for NULL rfunc. + */ +static int bad_rfunc(struct seq_file *m, void *ptr) +{ + return -EACCES; +} + +/* + * fbxprocfs write path is now handled by seq_file code. this + * simplifies client code greatly. + */ +static int fbxprocfs_open(struct inode *inode, struct file *file) +{ + const struct fbxprocfs_desc *desc = pde_data(inode); + + return single_open(file, desc->rfunc ? desc->rfunc : bad_rfunc, + (void*)desc->id); +} + +/* + * no particular help from kernel in the write path, fetch user buffer + * in a kernel buffer and call write func. + */ +static ssize_t fbxprocfs_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *off) +{ + /* + * get fbxprocfs desc via the proc_dir_entry in file inode + */ + struct fbxprocfs_desc *d = pde_data(file_inode(file)); + char *kbuf; + int ret; + + /* + * must have a wfunc callback. + */ + if (!d->wfunc) + return -EACCES; + + /* + * allow up to SZ_4K bytes to be written. + */ + if (len > SZ_4K) + return -EOVERFLOW; + + /* + * alloc and fetch kernel buffer containing user data. + */ + kbuf = kmalloc(SZ_4K, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + ret = -EFAULT; + if (copy_from_user(kbuf, ubuf, len)) + goto kfree; + + ret = d->wfunc(file, kbuf, len, (void*)d->id); + +kfree: + kfree(kbuf); + return ret; +} + +/* + * fbxprocfs file operations, read stuff is handled by seq_file code. + */ +static const struct proc_ops fbxprocfs_fops = { + .proc_open = fbxprocfs_open, + .proc_lseek = seq_lseek, + .proc_read = seq_read, + .proc_release = single_release, + .proc_write = fbxprocfs_write, +}; + +/* + * replaces create_proc_read_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_read_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, 0, base, &fbxprocfs_fops, + (void*)desc); +} + +/* + * replaces create_proc_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, S_IFREG | S_IWUSR | S_IRUGO, + base, &fbxprocfs_fops, (void*)desc); +} + +/* + * create given entries in client directory + */ +static int +__create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + struct proc_dir_entry *proc; + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + if (!(proc = __create_proc_read_entry(&ro_desc[i], + client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + if (!(proc = __create_proc_entry(&rw_desc[i], client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + return 0; + +err: + __remove_entries(client, ro_desc, rw_desc); + return -1; +} + +int +fbxprocfs_create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __create_entries(client, ro_desc, rw_desc); + return ret; +} + +int +fbxprocfs_remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __remove_entries(client, ro_desc, rw_desc); + return ret; +} + + +static int __init +fbxprocfs_init(void) +{ + INIT_LIST_HEAD(&clients); + mutex_init(&clients_mutex); + + /* create freebox directory */ + if (!(root = proc_mkdir("freebox", NULL))) { + printk(KERN_ERR PFX "can't create freebox/ dir\n"); + return -EIO; + } + return 0; +} + +static void __exit +fbxprocfs_exit(void) +{ + remove_proc_entry("freebox", NULL); +} + +module_init(fbxprocfs_init); +module_exit(fbxprocfs_exit); + +EXPORT_SYMBOL(fbxprocfs_create_entries); +EXPORT_SYMBOL(fbxprocfs_remove_entries); +EXPORT_SYMBOL(fbxprocfs_add_client); +EXPORT_SYMBOL(fbxprocfs_remove_client); + +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Maxime Bizon "); + diff -Nruw linux-6.4-fbx/drivers/fbxwatchdog./Kconfig linux-6.4-fbx/drivers/fbxwatchdog/Kconfig --- linux-6.4-fbx/drivers/fbxwatchdog./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxwatchdog/Kconfig 2024-03-18 14:40:14.839741005 +0100 @@ -0,0 +1,28 @@ +menuconfig FREEBOX_WATCHDOG + tristate "Freebox Watchdog" + default n + +if FREEBOX_WATCHDOG + +config FREEBOX_WATCHDOG_CHAR + bool "Freebox Watchdog char device interface." + default n + +config FREEBOX_WATCHDOG_ORION + tristate "Marvell Orion support" + depends on PLAT_ORION + +config FREEBOX_WATCHDOG_BCM63XX + tristate "Broadcom 63xx Freebox Watchdog support" + depends on BCM63XX + default n + +config FREEBOX_WATCHDOG_BCM63XX_OF + tristate "Broadcom 63xx Freebox Watchdog support (generic)" + depends on OF && !FREEBOX_WATCHDOG_BCM63XX + +config FREEBOX_WATCHDOG_FBXGWR_PMU + tristate "Freebox PMU Watchdog support" + depends on MFD_FBXGWR_PMU + +endif diff -Nruw linux-6.4-fbx/drivers/fbxwatchdog./Makefile linux-6.4-fbx/drivers/fbxwatchdog/Makefile --- linux-6.4-fbx/drivers/fbxwatchdog./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxwatchdog/Makefile 2024-03-18 14:40:14.839741005 +0100 @@ -0,0 +1,11 @@ +obj-$(CONFIG_FREEBOX_WATCHDOG) += fbxwatchdog.o + +fbxwatchdog-objs = fbxwatchdog_core.o +ifeq ($(CONFIG_FREEBOX_WATCHDOG_CHAR),y) +fbxwatchdog-objs += fbxwatchdog_char.o +endif + +obj-$(CONFIG_FREEBOX_WATCHDOG_ORION) += fbxwatchdog_orion.o +obj-$(CONFIG_FREEBOX_WATCHDOG_BCM63XX) += fbxwatchdog_bcm63xx.o +obj-$(CONFIG_FREEBOX_WATCHDOG_BCM63XX_OF) += fbxwatchdog_bcm63xx_of.o +obj-$(CONFIG_FREEBOX_WATCHDOG_FBXGWR_PMU) += fbxwatchdog_gwr_pmu.o diff -Nruw linux-6.4-fbx/drivers/fbxwatchdog./fbxwatchdog.h linux-6.4-fbx/drivers/fbxwatchdog/fbxwatchdog.h --- linux-6.4-fbx/drivers/fbxwatchdog./fbxwatchdog.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxwatchdog/fbxwatchdog.h 2024-03-18 14:40:14.839741005 +0100 @@ -0,0 +1,49 @@ +#ifndef FBXWATCHDOG_H +# define FBXWATCHDOG_H + +struct fbxwatchdog { + const char *name; + void *priv; + + int enabled; + int countdown; + int countdown_min; + + int (*wdt_init)(struct fbxwatchdog *wdt); + int (*wdt_cleanup)(struct fbxwatchdog *wdt); + + /* + * wdt_start and wdt_stop are called with wdt->lock held and irq + * disabled. + */ + int (*wdt_start)(struct fbxwatchdog *wdt); + int (*wdt_stop)(struct fbxwatchdog *wdt); + + /* + * cb is called from interrupt/softirq context (depends on the + * underlying driver/hardware). + */ + void (*cb)(struct fbxwatchdog *wdt); + + struct timer_list timer; + + struct device *dev; + + /* + * protect interrupt handlers & start/stop methods running in + * thread context. + */ + spinlock_t lock; + struct mutex mutex; + bool use_mutex; +}; + +int fbxwatchdog_register(struct fbxwatchdog *wdt); +int fbxwatchdog_unregister(struct fbxwatchdog *wdt); + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR +int fbxwatchdog_char_add(struct fbxwatchdog *wdt); +void fbxwatchdog_char_remove(struct fbxwatchdog *wdt); +#endif + +#endif /* !FBXWATCHDOG_H */ diff -Nruw linux-6.4-fbx/drivers/fbxwatchdog./fbxwatchdog_bcm63xx_of.c linux-6.4-fbx/drivers/fbxwatchdog/fbxwatchdog_bcm63xx_of.c --- linux-6.4-fbx/drivers/fbxwatchdog./fbxwatchdog_bcm63xx_of.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxwatchdog/fbxwatchdog_bcm63xx_of.c 2024-02-16 18:22:40.343781783 +0100 @@ -0,0 +1,501 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fbxwatchdog.h" + +enum bcm63xx_wdt_reg { + /* Watchdog default count register */ + WDT_DEFVAL_REG, + /* Watchdog control register */ + WDT_CTL_REG, + /* Watchdog reset length register */ + WDT_RSTLEN_REG, +}; + +enum bcmtimer_chip_id { + WDT_6328, + WDT_63158, +}; + +static const u32 regs_offsets_6328[] = { + [WDT_DEFVAL_REG] = 0x28, + [WDT_CTL_REG] = 0x2c, + [WDT_RSTLEN_REG] = 0x30, +}; + +static const u32 regs_offsets_63158[] = { + [WDT_DEFVAL_REG] = 0xc0, + [WDT_CTL_REG] = 0xc4, + [WDT_RSTLEN_REG] = 0xc8, +}; + +#define PERF_TIMER64_RESET_REASON 0x48 +#define PERF_TIMER64_RESET_REASON_WD0 (1 << 31) +#define PERF_TIMER64_RESET_REASON_WD1 (1 << 30) +#define PERF_TIMER64_RESET_REASON_USR_MASK 0xff +#define PERF_TIMER64_RESET_REASON_USR_PANPAN 'P' + +/* Watchdog control register constants */ +#define WDT_START_1 (0xff00) +#define WDT_START_2 (0x00ff) +#define WDT_STOP_1 (0xee00) +#define WDT_STOP_2 (0x00ee) + +#define PFX "fbxwatchdog_bcm63xx: " + +struct bcm_priv { + void __iomem *regs; + void __iomem *reg_top_reset_status; + const u32 *regs_offsets; + int irq; + enum bcmtimer_chip_id chip_id; + struct platform_device *pdev; + + struct notifier_block panic_notifier; + u32 timer64_reset_reason; + u32 top_reset_status; +}; + +#define nb_to_bcm_priv(nb) container_of(nb, struct bcm_priv, \ + panic_notifier) + +/* + * io helpers to access mac registers + */ +static inline u32 wdt_readl(struct bcm_priv *priv, enum bcm63xx_wdt_reg reg) +{ + return readl(priv->regs + priv->regs_offsets[reg]); +} + +static inline void wdt_writel(struct bcm_priv *priv, u32 val, + enum bcm63xx_wdt_reg reg) +{ + writel(val, priv->regs + priv->regs_offsets[reg]); +} + +/* + * IRQ handler, called when half the hw countdown is reached + */ +static irqreturn_t bcm63xx_wdt_irq(int irq, void *dev_id) +{ + struct fbxwatchdog *wdt = dev_id; + struct bcm_priv *priv; + + priv = wdt->priv; + spin_lock(&wdt->lock); + + if (!wdt->enabled) { + printk(KERN_CRIT "watchdog is still enabled, stopping !\n"); + wdt_writel(priv, WDT_STOP_1, WDT_CTL_REG); + wdt_writel(priv, WDT_STOP_2, WDT_CTL_REG); + goto out; + } + + /* clear interrupt and reload */ + wdt_writel(priv, WDT_START_1, WDT_CTL_REG); + wdt_writel(priv, WDT_START_2, WDT_CTL_REG); + + if (wdt->cb) + wdt->cb(wdt); + +out: + spin_unlock(&wdt->lock); + return IRQ_HANDLED; +} + +static int bcm63xx_wdt_init(struct fbxwatchdog *wdt) +{ + struct bcm_priv *priv = wdt->priv; + int ret; + u32 countdown; + + ret = request_irq(priv->irq, bcm63xx_wdt_irq, 0, + "fbxwatchdog_bcm63xx", wdt); + if (ret) { + printk(KERN_ERR PFX "request_irq failed: %d\n", ret); + return ret; + } + + /* irq is triggerd at half time, install a 1 sec watchdog, + * that gives 2 irq/s (freq is 50Mhz) */ + countdown = (50 * 1000 * 1000); + wdt_writel(wdt->priv, countdown, WDT_DEFVAL_REG); + + return 0; +} + +static int bcm63xx_wdt_cleanup(struct fbxwatchdog *wdt) +{ + struct bcm_priv *priv = wdt->priv; + + free_irq(priv->irq, wdt); + return 0; +} + +static int bcm63xx_wdt_start(struct fbxwatchdog *wdt) +{ + printk(KERN_INFO PFX "watchdog enabled\n"); + wdt_writel(wdt->priv, WDT_START_1, WDT_CTL_REG); + wdt_writel(wdt->priv, WDT_START_2, WDT_CTL_REG); + return 0; +} + +static int bcm63xx_wdt_stop(struct fbxwatchdog *wdt) +{ + wdt_writel(wdt->priv, WDT_STOP_1, WDT_CTL_REG); + wdt_writel(wdt->priv, WDT_STOP_2, WDT_CTL_REG); + printk(KERN_INFO PFX "watchdog disabled\n"); + return 0; +} + +struct reset_reason { + int bit; + char *reason; +}; + +struct reset_reason bcm63158_reasons[] = { + { .bit = 31, .reason = "por-reset", }, + { .bit = 30, .reason = "hw-reset", }, + { .bit = 29, .reason = "sw-reset", }, + { .bit = 28, .reason = "pcie-reset", }, +}; + +/* + * all potentially self clearing data in the registers is stored in + * the priv structure for further reuse in + * bcm63xx_wdt_show_reset_reason. + */ +static void bcm63xx_wdt_report_reset_status(struct fbxwatchdog *wdt) +{ + struct bcm_priv *priv = wdt->priv; + + if (priv->chip_id != WDT_63158) + return ; + + if (priv->reg_top_reset_status) { + size_t i; + u32 reg = readl(priv->reg_top_reset_status); + + dev_info(&priv->pdev->dev, "%08x (TOP reset status)\n", reg); + + for (i = 0; i < ARRAY_SIZE(bcm63158_reasons); ++i) { + struct reset_reason *r = &bcm63158_reasons[i]; + + dev_info(&priv->pdev->dev, " %s: %u\n", + r->reason, !!(reg & (1 << r->bit))); + } + priv->top_reset_status = reg; + } + + /* + * NOTE: WD0 & WD1 fields in the PERF_TIMER64_RESET_REASON + * register will self clear on first register read. + */ + priv->timer64_reset_reason = readl(priv->regs + + PERF_TIMER64_RESET_REASON); + + dev_info(&priv->pdev->dev, "%08x (PERF timer64 reset reason)", + priv->timer64_reset_reason); + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD0) + dev_info(&priv->pdev->dev, " wd0 (nominal reboot)\n"); + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD1) + dev_info(&priv->pdev->dev, " wd1 (abnormal reboot)\n"); + + if ((priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_USR_MASK) == + PERF_TIMER64_RESET_REASON_USR_PANPAN) + dev_info(&priv->pdev->dev, " a panic was in progress.\n"); + + /* + * explicitely clear user defined bits in reset reason register. + */ + writel(0x0, priv->regs + PERF_TIMER64_RESET_REASON); +} + +extern int panic_timeout; + +/* + * watchdog panic notifier. in the unlikely case of a panic, the + * watchdog refreshing via the interrupt will be out of order. + * + * This will result in the board resetting before panic_timeout can + * elapse. + * + * In that case rearm the watchdog so that it fires at panic_timeout + + * 1 second. + */ +static int bcm63xx_wdt_on_panic(struct notifier_block *nb, + unsigned long code, void *unused) +{ + struct bcm_priv *priv = nb_to_bcm_priv(nb); + static int in_panic; + u32 new_wdt_countdown = (panic_timeout + 1) * (50 * 1000 * 1000); + + /* + * avoid recursive calls. + */ + if (in_panic) + return NOTIFY_DONE; + in_panic = 1; + + + dev_info(&priv->pdev->dev, "rearming watchdog to expire in %u " + "seconds.\n", panic_timeout + 1); + + wdt_writel(priv, new_wdt_countdown, WDT_DEFVAL_REG); + + wdt_writel(priv, WDT_START_1, WDT_CTL_REG); + wdt_writel(priv, WDT_START_2, WDT_CTL_REG); + + if (priv->chip_id == WDT_63158) + /* + * write PANPAN as user defined reason to the reset + * reason register. In the unlikely event a crashzone + * log cannot be read back, it will preserve the knowledge + * that the board crashed due to a panic. + */ + writel(PERF_TIMER64_RESET_REASON_USR_PANPAN, + priv->regs + PERF_TIMER64_RESET_REASON); + + return NOTIFY_DONE; +} + +ssize_t bcm63xx_wdt_show_reset_reason(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + size_t i; + struct fbxwatchdog *wdt = dev_get_drvdata(dev); + struct bcm_priv *priv = wdt->priv; + size_t retsize; + + if (priv->chip_id != WDT_63158) + return -ENOTSUPP; + + /* + * no register access here, bcm63xx_wdt_report_reset_status() + * will store them in priv, as most of them are self clear on + * first read. + */ + *buf = '\0'; + + /* + * first iterate on the top reset status reset reasons. + */ + for (i = 0; i < ARRAY_SIZE(bcm63158_reasons); ++i) { + const struct reset_reason *r = &bcm63158_reasons[i]; + + if (priv->top_reset_status & (1 << r->bit)) { + strcat(buf, r->reason); + strcat(buf, ","); + } + } + + /* + * watchdog status in PERF_TIMER64_RESET_REASON register. in + * our context, wd0 is used to reboot the box normally. wd1 + * (managed by this driver) will reboot the board if something + * goes wrong and the hardware watchdog isn't refreshed. + * + * in a nutshell: + * wd0 -> normal boot, used by ATF via the PSCI reset call + * wd1 -> boot due to a hardware watchdog trigger. + */ + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD0) + strcat(buf, "wd0,"); + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD1) + strcat(buf, "wd1,watchdog,"); + + /* + * user defined reboot bits in PERF_TIMER64_RESET_REASON_REG. + */ + if ((priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_USR_MASK) == + PERF_TIMER64_RESET_REASON_USR_PANPAN) + strcat(buf, "panic,"); + + /* + * '\n'-terminate the string. + */ + retsize = strlen(buf); + if (retsize) + buf[retsize - 1] = '\n'; + + return strlen(buf); +} + +static DEVICE_ATTR(reset_reason, 0444, bcm63xx_wdt_show_reset_reason, NULL); + +static struct attribute *bcm63xx_wdt_attrs[] = { + &dev_attr_reset_reason.attr, + NULL +}; + +static const struct attribute_group bcm63xx_wdt_attrs_group = { + .attrs = bcm63xx_wdt_attrs, +}; + +/* + * + */ +static int fbxwatchdog_bcm63xx_probe(struct platform_device *pdev) +{ + struct fbxwatchdog *wdt; + struct bcm_priv *priv; + struct resource *res; + int ret, irq_number; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pdev = pdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to get register core resource\n"); + return -ENODEV; + } + + priv->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->regs)) { + dev_err(&pdev->dev, "unable to ioremap regs\n"); + return PTR_ERR(priv->regs); + } + + /* + * ioremap optional reset cause register. + */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + priv->reg_top_reset_status = devm_ioremap_resource(&pdev->dev, + res); + if (IS_ERR(priv->reg_top_reset_status)) { + dev_err(&pdev->dev, "unable to ioremap TOP reset " + "status register.\n"); + return PTR_ERR(priv->reg_top_reset_status); + } + dev_info(&pdev->dev, "TOP reset status regiser: %pR", res); + } + + priv->chip_id = (unsigned long)of_device_get_match_data(&pdev->dev); + switch (priv->chip_id) { + case WDT_6328: + irq_number = 4; + priv->regs_offsets = regs_offsets_6328; + break; + case WDT_63158: + irq_number = 0; + priv->regs_offsets = regs_offsets_63158; + break; + default: + return -ENODEV; + } + + priv->irq = platform_get_irq(pdev, irq_number); + if (priv->irq < 0) { + dev_err(&pdev->dev, "cannot get watchdog irq\n"); + return priv->irq; + } + + wdt = devm_kzalloc(&pdev->dev, sizeof (*wdt), GFP_KERNEL); + if (!wdt) { + printk(KERN_WARNING PFX "unable to allocate memory for " + "watchdog.\n"); + return -ENOMEM; + } + + wdt->name = pdev->name; + wdt->priv = priv; + wdt->wdt_init = bcm63xx_wdt_init; + wdt->wdt_cleanup = bcm63xx_wdt_cleanup; + wdt->wdt_start = bcm63xx_wdt_start; + wdt->wdt_stop = bcm63xx_wdt_stop; + + ret = fbxwatchdog_register(wdt); + if (ret) { + printk(KERN_WARNING PFX "unable to register watchdog %s.\n", + wdt->name); + return ret; + } + bcm63xx_wdt_report_reset_status(wdt); + + priv->panic_notifier.notifier_call = bcm63xx_wdt_on_panic, + atomic_notifier_chain_register(&panic_notifier_list, + &priv->panic_notifier); + + ret = sysfs_create_group(&wdt->dev->kobj, &bcm63xx_wdt_attrs_group); + if (ret) { + dev_info(&pdev->dev, "sysfs_create_group failed: %pe\n", + ERR_PTR(ret)); + goto err_unregister_notifier; + } + + platform_set_drvdata(pdev, wdt); + return 0; + +err_unregister_notifier: + atomic_notifier_chain_unregister(&panic_notifier_list, + &priv->panic_notifier); + fbxwatchdog_unregister(wdt); + return ret; +} + +/* + * + */ +static int fbxwatchdog_bcm63xx_remove(struct platform_device *pdev) +{ + struct fbxwatchdog *wdt; + struct bcm_priv *priv; + + wdt = platform_get_drvdata(pdev); + if (!wdt) + return -ENODEV; + priv = wdt->priv; + + sysfs_remove_group(&wdt->dev->kobj, &bcm63xx_wdt_attrs_group); + atomic_notifier_chain_unregister(&panic_notifier_list, + &priv->panic_notifier); + fbxwatchdog_unregister(wdt); + + return 0; +} + +static const struct of_device_id bcmtimer_of_table[] = { + { .compatible = "brcm,bcm6328-timer", .data = (void *)WDT_6328}, + { .compatible = "brcm,bcm63158-timer", .data = (void *)WDT_63158 }, + { } +}; +MODULE_DEVICE_TABLE(of, bcmtimer_of_table); + +struct platform_driver fbxwatchdog_bcm63xx_driver = { + .probe = fbxwatchdog_bcm63xx_probe, + .remove = fbxwatchdog_bcm63xx_remove, + .driver = { + .name = "bcm63xx_wdt", + .of_match_table = of_match_ptr(bcmtimer_of_table), + }, +}; + +static int __init fbxwatchdog_bcm63xx_of_init(void) +{ + platform_driver_register(&fbxwatchdog_bcm63xx_driver); + return 0; +} + +static void __exit fbxwatchdog_bcm63xx_of_exit(void) +{ + platform_driver_unregister(&fbxwatchdog_bcm63xx_driver); +} + +module_init(fbxwatchdog_bcm63xx_of_init); +module_exit(fbxwatchdog_bcm63xx_of_exit); + +MODULE_AUTHOR("Maxime Bizon"); +MODULE_LICENSE("GPL"); diff -Nruw linux-6.4-fbx/drivers/fbxwatchdog./fbxwatchdog_core.c linux-6.4-fbx/drivers/fbxwatchdog/fbxwatchdog_core.c --- linux-6.4-fbx/drivers/fbxwatchdog./fbxwatchdog_core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/fbxwatchdog/fbxwatchdog_core.c 2024-03-18 14:40:14.839741005 +0100 @@ -0,0 +1,317 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fbxwatchdog.h" + +#define SOFTTIMER_FREQ (HZ / 10) + +#define PFX "fbxwatchdog: " + +static struct class *fbxwatchdog_class; + +static void wdt_lock(struct fbxwatchdog *wdt, unsigned long *flags) +{ + if (wdt->use_mutex) + mutex_lock(&wdt->mutex); + else + spin_lock_irqsave(&wdt->lock, *flags); +} + +static void wdt_unlock(struct fbxwatchdog *wdt, unsigned long *flags) +{ + if (wdt->use_mutex) + mutex_unlock(&wdt->mutex); + else + spin_unlock_irqrestore(&wdt->lock, *flags); +} + +static ssize_t +show_enabled(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxwatchdog *wdt; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + return snprintf(buf, PAGE_SIZE, "%i\n", wdt->enabled); +} + +/* + * start/stop watchdog depending on the value of the first character + * of buf. set countdown_min to a sane value. + */ +static ssize_t +store_enabled(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct fbxwatchdog *wdt; + unsigned long flags; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + if (size == 0) + return 0; + + + wdt_lock(wdt, &flags); + switch (*buf) { + case '0': + if (wdt->enabled) { + wdt->enabled = 0; + wdt->wdt_stop(wdt); + } + break; + + case '1': + if (!wdt->enabled) { + wdt->enabled = 1; + wdt->wdt_start(wdt); + wdt->countdown_min = INT_MAX; + } + break; + + default: + break; + } + wdt_unlock(wdt, &flags); + + return size; +} + +static ssize_t +show_countdown(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxwatchdog *wdt; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + return snprintf(buf, PAGE_SIZE, "%i\n", wdt->countdown); +} + +/* + * update watchdog countdown with the userland value given in buf. + */ +static ssize_t +store_countdown(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct fbxwatchdog *wdt; + int countdown; + char *ptr; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + if (size == 0) + return 0; + + ptr = kzalloc(size + 1, GFP_KERNEL); + if (!ptr) + return -ENOMEM; + strlcpy(ptr, buf, size + 1); + + countdown = simple_strtoul(ptr, NULL, 10); + wdt->countdown = countdown; + kfree(ptr); + + return size; +} + +static ssize_t +show_countdown_min(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxwatchdog *wdt; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + return snprintf(buf, PAGE_SIZE, "%i\n", wdt->countdown_min); +} + +static struct device_attribute wdt_attributes[] = { + __ATTR(enabled, 0600, show_enabled, store_enabled), + __ATTR(countdown, 0600, show_countdown, store_countdown), + __ATTR(countdown_min, 0400, show_countdown_min, NULL), +}; + +/* + * software timer callback: decrement countdown and update + * countdown_min if needed. this is called 10 times per second. + */ +static void fbxwatchdog_timer_cb(struct timer_list *t) +{ + struct fbxwatchdog *wdt = from_timer(wdt, t, timer); + + if (wdt->enabled) { + wdt->countdown -= jiffies_to_msecs(SOFTTIMER_FREQ); + if (wdt->countdown < wdt->countdown_min) + wdt->countdown_min = wdt->countdown; + } + + wdt->timer.expires = jiffies + SOFTTIMER_FREQ; + add_timer(&wdt->timer); +} + +/* + * called from half life interrupt handler, panic if countdown is too + * low (ie if userland has not reset countdown to before it reached + * 0). + */ +static void fbxwatchdog_halflife_cb(struct fbxwatchdog *wdt) +{ + if (wdt->countdown <= 0) { + wdt->wdt_stop(wdt); + panic("software fbxwatchdog triggered"); + } +} + +/* + * register a new watchdog device. + */ +int fbxwatchdog_register(struct fbxwatchdog *wdt) +{ + struct device *dev; + int i = 0, err = 0; + + if (wdt == NULL) + return -EFAULT; + + printk(KERN_INFO PFX "registering watchdog %s\n", wdt->name); + + dev = device_create(fbxwatchdog_class, NULL, 0, wdt, "%s", wdt->name); + if (IS_ERR(dev)) { + printk(KERN_ERR PFX "unable to allocate device.\n"); + err = PTR_ERR(dev); + goto out_error; + } + wdt->dev = dev; + + for (i = 0; i < ARRAY_SIZE(wdt_attributes); i++) { + err = device_create_file(dev, &wdt_attributes[i]); + if (err) + goto out_error; + } + + /* start countdown soft timer */ + timer_setup(&wdt->timer, fbxwatchdog_timer_cb, 0); + wdt->timer.expires = jiffies + SOFTTIMER_FREQ; + add_timer(&wdt->timer); + + if (wdt->use_mutex) + mutex_init(&wdt->mutex); + else + spin_lock_init(&wdt->lock); + + wdt->cb = fbxwatchdog_halflife_cb; + err = wdt->wdt_init(wdt); + if (err) { + printk(KERN_ERR PFX "unable to do low level init of " + "watchdog %s.\n", wdt->name); + goto out_del_timer; + } + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR + err = fbxwatchdog_char_add(wdt); + if (err) { + printk(KERN_ERR PFX "unable to add %s to the fbxwatchdog char " + "device interface.\n", wdt->name); + goto out_wdt_cleanup; + } +#endif + + return 0; + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR +out_wdt_cleanup: + wdt->wdt_cleanup(wdt); +#endif + +out_del_timer: + del_timer_sync(&wdt->timer); +out_error: + if (wdt->dev) { + for (; i >= 0; i--) + device_remove_file(dev, &wdt_attributes[i]); + device_unregister(dev); + } + return err; +} + +int fbxwatchdog_unregister(struct fbxwatchdog *wdt) +{ + int i; + + printk(KERN_INFO PFX "unregistering watchdog %s\n", wdt->name); + + if (wdt->enabled) { + unsigned long flags; + + printk(KERN_WARNING "removing enabled watchdog.\n"); + wdt_lock(wdt, &flags); + wdt->wdt_stop(wdt); + wdt_unlock(wdt, &flags); + } + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR + fbxwatchdog_char_remove(wdt); +#endif + wdt->wdt_cleanup(wdt); + del_timer_sync(&wdt->timer); + for (i = 0; i < ARRAY_SIZE(wdt_attributes); i++) + device_remove_file(wdt->dev, &wdt_attributes[i]); + device_unregister(wdt->dev); + wdt->dev = NULL; + return 0; +} + +static int __init fbxwatchdog_init(void) +{ + printk(KERN_INFO PFX "2007, Freebox SA.\n"); + fbxwatchdog_class = class_create("fbxwatchdog"); + if (IS_ERR(fbxwatchdog_class)) + return PTR_ERR(fbxwatchdog_class); + return 0; +} + +static void __exit fbxwatchdog_exit(void) +{ + class_destroy(fbxwatchdog_class); +} + + +EXPORT_SYMBOL_GPL(fbxwatchdog_register); +EXPORT_SYMBOL_GPL(fbxwatchdog_unregister); + +module_init(fbxwatchdog_init); +module_exit(fbxwatchdog_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Freebox Watchdog Core - www.freebox.fr"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/gpio/gpio-fbxgwr-pmu.c 2024-03-18 14:40:14.839741005 +0100 @@ -0,0 +1,453 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define PMU_MAX_GPIOS 32 +#define PMU_BANK_SZ 8 + +/* + * private context + */ +struct fbxgwr_pmu_gpio { + struct regmap *regmap; + struct gpio_chip chip; + + int irq; + struct mutex irq_lock; + + DECLARE_BITMAP(irq_enabled, PMU_MAX_GPIOS); + DECLARE_BITMAP(irq_enabled_new, PMU_MAX_GPIOS); +}; + +/* + * local functions + */ +static int fbxgwr_pmu_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset); +static int fbxgwr_pmu_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset); +static int fbxgwr_pmu_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value); +static int fbxgwr_pmu_gpio_get(struct gpio_chip *chip, unsigned int offset); +static void fbxgwr_pmu_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value); + +static const struct gpio_chip fbxgwr_pmu_gpio_chip = { + .label = "fbxgwr_pmu_gpio", + .owner = THIS_MODULE, + .get_direction = fbxgwr_pmu_gpio_get_direction, + .direction_input = fbxgwr_pmu_gpio_direction_input, + .direction_output = fbxgwr_pmu_gpio_direction_output, + .get = fbxgwr_pmu_gpio_get, + .set = fbxgwr_pmu_gpio_set, + .base = -1, + .can_sleep = 1, +}; + +static int fbxgwr_pmu_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(chip); + u8 dirreg, bit; + u32 reg_val; + int ret; + + dirreg = PMU_REG_GPIO_DIR_GET_0 + offset / PMU_BANK_SZ; + bit = BIT(offset % PMU_BANK_SZ); + + ret = regmap_read(priv->regmap, dirreg, ®_val); + if (ret) + return ret; + + if (!(reg_val & bit)) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int fbxgwr_pmu_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(chip); + u8 dirreg, bit; + + dirreg = PMU_REG_GPIO_DIR_CLR_0 + offset / PMU_BANK_SZ; + bit = BIT(offset % PMU_BANK_SZ); + + return regmap_write(priv->regmap, dirreg, bit); +} + +static int fbxgwr_pmu_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(chip); + u8 dirreg, outreg, bit; + int ret; + + bit = BIT(offset % PMU_BANK_SZ); + + if (value) + outreg = PMU_REG_GPIO_OUT_SET_0 + offset / PMU_BANK_SZ; + else + outreg = PMU_REG_GPIO_OUT_CLR_0 + offset / PMU_BANK_SZ; + + ret = regmap_write(priv->regmap, outreg, bit); + if (ret) + return ret; + + dirreg = PMU_REG_GPIO_DIR_SET_0 + offset / PMU_BANK_SZ; + + return regmap_write(priv->regmap, dirreg, bit); +} + +static int fbxgwr_pmu_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(chip); + u8 inreg, bit; + u32 reg_val; + int ret; + + inreg = PMU_REG_GPIO_IN_0 + offset / PMU_BANK_SZ; + bit = BIT(offset % PMU_BANK_SZ); + + ret = regmap_read(priv->regmap, inreg, ®_val); + if (ret) + return ret; + + return !!(reg_val & bit); +} + +static void fbxgwr_pmu_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(chip); + u8 outreg, bit; + + bit = BIT(offset % PMU_BANK_SZ); + + if (value) + outreg = PMU_REG_GPIO_OUT_SET_0 + offset / PMU_BANK_SZ; + else + outreg = PMU_REG_GPIO_OUT_CLR_0 + offset / PMU_BANK_SZ; + + regmap_write(priv->regmap, outreg, bit); +} + +static void fbxgwr_pmu_irq_enable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(gc); + + /* delay manipulation of registers to bus_sync_unlock() + * callback */ + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + set_bit(d->hwirq, priv->irq_enabled_new); +} + +static void fbxgwr_pmu_irq_disable(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(gc); + + /* delay manipulation of registers to bus_sync_unlock() + * callback */ + clear_bit(d->hwirq, priv->irq_enabled_new); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +static void fbxgwr_pmu_irq_bus_lock(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(gc); + + mutex_lock(&priv->irq_lock); + bitmap_copy(priv->irq_enabled_new, priv->irq_enabled, PMU_MAX_GPIOS); +} + +static int do_irqcmd(struct fbxgwr_pmu_gpio *priv, + u32 cmd, u32 nr) +{ + int ret, i; + u32 val; + + regmap_write(priv->regmap, PMU_REG_GPIO_IRQ_CMD_NR, nr); + regmap_write(priv->regmap, PMU_REG_GPIO_IRQ_CMD, cmd); + + for (i = 0; i < 100; i++) { + ret = regmap_read(priv->regmap, PMU_REG_GPIO_IRQ_CMD_STAT, + &val); + if (ret) { + dev_err(priv->chip.parent, "regmap read: %d\n", ret); + return ret; + } + + if (val & PMU_GPIOIRQCMD_RES_BUSY) { + msleep(1); + continue; + } + + if ((val & PMU_GPIOIRQCMD_RES_SUCCESS)) + return 0; + + dev_err(priv->chip.parent, "failed to start/stop interrupt\n"); + return -EIO; + } + + return 0; +} + +static void fbxgwr_pmu_irq_bus_sync_unlock(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(gc); + size_t i; + + /* update enabled mask */ + if (!bitmap_equal(priv->irq_enabled, priv->irq_enabled_new, + PMU_MAX_GPIOS)) { + unsigned int p; + DECLARE_BITMAP(irq_changed, PMU_MAX_GPIOS); + + bitmap_xor(irq_changed, + priv->irq_enabled, priv->irq_enabled_new, + PMU_MAX_GPIOS); + + for_each_set_bit(p, irq_changed, PMU_MAX_GPIOS) { + unsigned int cmd; + + if (test_bit(p, priv->irq_enabled_new)) + cmd = PMU_GPIOIRQCMD_ENABLE; + else + cmd = PMU_GPIOIRQCMD_DISABLE; + do_irqcmd(priv, cmd, p); + } + + /* update changed mask */ + for (i = 0; i < PMU_MAX_GPIOS / PMU_BANK_SZ; i++) { + u8 mask; + + mask = bitmap_get_value8(priv->irq_enabled_new, i * 8); + regmap_write(priv->regmap, + PMU_REG_GPIO_IRQ_MASK_BASE + i, + mask); + } + + bitmap_copy(priv->irq_enabled, + priv->irq_enabled_new, PMU_MAX_GPIOS); + } + + mutex_unlock(&priv->irq_lock); +} + +static irqreturn_t fbxgwr_pmu_irq_handler(int irq, void *devid) +{ + struct fbxgwr_pmu_gpio *priv = devid; + DECLARE_BITMAP(pending, PMU_MAX_GPIOS); + irqreturn_t irqret = IRQ_NONE; + unsigned int p; + size_t i; + + bitmap_zero(pending, PMU_MAX_GPIOS); + + for (i = 0; i < PMU_MAX_GPIOS / PMU_BANK_SZ; i++) { + u32 bank_pending; + u8 mask; + int ret; + + mask = bitmap_get_value8(priv->irq_enabled, i * 8); + if (!mask) + continue; + + ret = regmap_read(priv->regmap, PMU_REG_GPIO_IRQ_STAT_BASE + i, + &bank_pending); + if (ret) + break; + + if (!bank_pending) + continue; + + irqret = IRQ_HANDLED; + + /* clear interrupt status */ + ret = regmap_write(priv->regmap, + PMU_REG_GPIO_IRQ_STAT_BASE + i, + bank_pending); + if (ret) + break; + + bitmap_set_value8(pending, bank_pending, i * 8); + } + + for_each_set_bit(p, pending, PMU_MAX_GPIOS) { + int child_irq; + child_irq = irq_find_mapping(priv->chip.irq.domain, p); + handle_nested_irq(child_irq); + } + + return irqret; +} + +static int fbxgwr_pmu_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + + /* we only support both edges */ + if ((type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH) { + dev_err(gc->parent, "irq %d: unsupported type %d\n", + d->irq, type); + return -EINVAL; + } + + return 0; +} + +static void fbxgwr_pmu_init_irq_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct fbxgwr_pmu_gpio *priv = gpiochip_get_data(gc); + DECLARE_BITMAP(irq_valid, PMU_MAX_GPIOS); + unsigned int i; + + for (i = 0; i < PMU_MAX_GPIOS / PMU_BANK_SZ; i++) { + u32 val; + int ret; + + ret = regmap_read(priv->regmap, PMU_REG_GPIO_IRQ_CAP_BASE + i, + &val); + if (ret) { + dev_err(gc->parent, "regmap read failed: %d\n", ret); + return; + } + + bitmap_set_value8(irq_valid, val, i * 8); + } + + bitmap_copy(valid_mask, irq_valid, ngpios); +} + +static const struct irq_chip fbxgwr_pmu_irq_chip = { + .name = "fbxgwr_pmu_gpio", + .irq_bus_lock = fbxgwr_pmu_irq_bus_lock, + .irq_bus_sync_unlock = fbxgwr_pmu_irq_bus_sync_unlock, + .irq_set_type = fbxgwr_pmu_irq_set_type, + .irq_enable = fbxgwr_pmu_irq_enable, + .irq_disable = fbxgwr_pmu_irq_disable, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +static int fbxgwr_pmu_gpio_irq_setup(struct platform_device *pdev, + struct fbxgwr_pmu_gpio *priv) +{ + struct gpio_irq_chip *girq; + u32 val; + int ret; + + if (!priv->irq) + return 0; + + ret = regmap_read(priv->regmap, PMU_REG_FW_CAPABILITIES, &val); + if (ret) + return -EIO; + + if (!(val & PMU_FW_CAP_GPIO_IRQ)) + return 0; + + mutex_init(&priv->irq_lock); + + ret = devm_request_threaded_irq(&pdev->dev, priv->irq, + NULL, fbxgwr_pmu_irq_handler, + IRQF_ONESHOT | + IRQF_SHARED | + IRQF_TRIGGER_LOW, + dev_name(&pdev->dev), priv); + if (ret) { + dev_err(&pdev->dev, "failed to request irq %d\n", ret); + return ret; + } + + girq = &priv->chip.irq; + + gpio_irq_chip_set_chip(girq, &fbxgwr_pmu_irq_chip); + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->init_valid_mask = fbxgwr_pmu_init_irq_valid_mask; + girq->threaded = true; + + return 0; +} + +static int fbxgwr_pmu_gpio_probe(struct platform_device *pdev) +{ + struct fbxgwr_pmu_gpio *priv; + u32 ngpios; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(struct fbxgwr_pmu_gpio), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!priv->regmap) + return -ENODEV; + + priv->irq = platform_get_irq_optional(pdev, 0); + if (priv->irq < 0) + return priv->irq; + + priv->chip = fbxgwr_pmu_gpio_chip; + priv->chip.parent = &pdev->dev; + + ret = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios); + if (ret) { + dev_err(&pdev->dev, "missing ngpios property in DT\n"); + return ret; + } + + /* reset io expander internal state, in case something else + * enabled any irq before */ + ret = regmap_write(priv->regmap, PMU_REG_GPIO_REINIT, 1); + if (ret) + return -EIO; + + priv->chip.ngpio = ngpios; + + ret = fbxgwr_pmu_gpio_irq_setup(pdev, priv); + if (ret) + return ret; + + ret = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id fbxgwr_pmu_gpio_of_id[] = { + { .compatible = "freebox,fbxgwr-pmu-gpio", }, + {} +}; +MODULE_DEVICE_TABLE(of, fbxgwr_pmu_gpio_of_id); + +static struct platform_driver fbxgwr_pmu_gpio_driver = { + .probe = fbxgwr_pmu_gpio_probe, + .driver = { + .name = "fbxgwr-pmu-gpio", + .of_match_table = fbxgwr_pmu_gpio_of_id, + }, +}; + +module_platform_driver(fbxgwr_pmu_gpio_driver); + +MODULE_AUTHOR("Marios Makassikis"); +MODULE_LICENSE("GPL"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/hwmon/fbxgwr_pmu_hwmon.c 2023-08-10 16:54:11.558117447 +0200 @@ -0,0 +1,281 @@ +#include +#include +#include +#include +#include +#include +#include + +struct fbxgwr_pmu_hwmon { + struct regmap *regmap; + u8 *in_map[hwmon_max]; +}; + +static inline int __pow10(u8 x) +{ + int r = 1; + + while (x--) + r *= 10; + + return r; +} + +static int fbxgwr_pmu_hwmon_read(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct fbxgwr_pmu_hwmon *priv = dev_get_drvdata(dev); + u32 reg_val; + int ret; + + switch (type) { + case hwmon_in: + case hwmon_curr: + case hwmon_fan: + case hwmon_temp: + case hwmon_power: + { + int in_off = priv->in_map[type][channel] * 3; + u32 high, low; + u16 val16; + int div; + + ret = regmap_read(priv->regmap, + PMU_REG_IN_BASE + in_off + 0, + ®_val); + if (ret) + return ret; + + ret = regmap_read(priv->regmap, + PMU_REG_IN_BASE + in_off + 1, + &low); + if (ret) + return ret; + + ret = regmap_read(priv->regmap, + PMU_REG_IN_BASE + in_off + 2, + &high); + if (ret) + return ret; + + val16 = (high << 8) | low; + if (reg_val & PMU_IN_SIGNED_MASK) + *val = sign_extend32(val16, 15); + else + *val = val16; + + div = (reg_val & PMU_IN_DIVIDER_MASK) >> PMU_IN_DIVIDER_SHIFT; + if (div) + *val *= __pow10(div); + + break; + } + + case hwmon_pwm: + ret = regmap_read(priv->regmap, PMU_REG_FAN_PWM_BASE + channel, + ®_val); + if (ret) + return ret; + *val = reg_val; + break; + + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static int fbxgwr_pmu_hwmon_write(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct fbxgwr_pmu_hwmon *priv = dev_get_drvdata(dev); + int ret; + + switch (type) { + case hwmon_pwm: + val = clamp_val(val, 0, 255); + ret = regmap_write(priv->regmap, + PMU_REG_FAN_PWM_BASE + channel, val); + if (ret) + return ret; + break; + default: + ret = -EOPNOTSUPP; + } + + return ret; +} + +static umode_t fbxgwr_pmu_hwmon_is_visible(const void *_data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_in: + case hwmon_curr: + case hwmon_fan: + case hwmon_temp: + case hwmon_power: + return 0444; + case hwmon_pwm: + return 0644; + default: + return 0; + } +} + +static const struct hwmon_ops fbxgwr_pmu_hwmon_ops = { + .is_visible = fbxgwr_pmu_hwmon_is_visible, + .read = fbxgwr_pmu_hwmon_read, + .write = fbxgwr_pmu_hwmon_write, +}; + +static u32 hwmon_attributes[hwmon_max] = { + [hwmon_temp] = HWMON_T_INPUT, + [hwmon_in] = HWMON_I_INPUT, + [hwmon_curr] = HWMON_C_INPUT, + [hwmon_power] = HWMON_P_INPUT, + [hwmon_pwm] = HWMON_PWM_INPUT, + [hwmon_fan] = HWMON_F_INPUT, +}; + +static int fbxgwr_pmu_hwmon_probe(struct platform_device *pdev) +{ + struct fbxgwr_pmu_hwmon *hwmon; + struct device *hwmon_dev; + enum hwmon_sensor_types type; + u32 fan_count, in_reg_count, in_count, cinfo_count, i; + int ret, nr_count[hwmon_max] = {0}; + const struct hwmon_channel_info **ptr_cinfos; + struct hwmon_channel_info *cinfos; + struct hwmon_chip_info pmu_hwmon_chip_info = { + .ops = &fbxgwr_pmu_hwmon_ops, + }; + + hwmon = devm_kzalloc(&pdev->dev, sizeof(struct fbxgwr_pmu_hwmon), + GFP_KERNEL); + if (!hwmon) + return -ENOMEM; + + hwmon->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!hwmon->regmap) + return -ENODEV; + + /* enumerate hardware channels and build channel infos + * dynamically */ + ret = regmap_read(hwmon->regmap, PMU_REG_IN_COUNT, &in_reg_count); + if (ret) + return ret; + + /* get actual sensor type from hardware */ + in_count = 0; + for (i = 0; i < in_reg_count; i++) { + u32 in_type; + + ret = regmap_read(hwmon->regmap, PMU_REG_IN_BASE + i * 3, + &in_type); + if (ret) + return ret; + + in_type &= PMU_IN_TYPE_MASK; + switch (in_type) { + case PMU_IN_TYPE_UNUSED: + continue; + case PMU_IN_TYPE_CURRENT: + type = hwmon_curr; + break; + case PMU_IN_TYPE_VOLTAGE: + type = hwmon_in; + break; + case PMU_IN_TYPE_POWER: + type = hwmon_power; + break; + case PMU_IN_TYPE_TEMPERATURE: + type = hwmon_temp; + break; + case PMU_IN_TYPE_FAN_INPUT: + type = hwmon_fan; + break; + default: + dev_warn(&pdev->dev, "unknown in-type, " + "assume voltage\n"); + type = hwmon_in; + break; + } + + if (!hwmon->in_map[type]) { + hwmon->in_map[type] = devm_kcalloc(&pdev->dev, + in_reg_count, + sizeof (u8), + GFP_KERNEL); + if (!hwmon->in_map[type]) + return -ENOMEM; + } + + hwmon->in_map[type][nr_count[type]] = i; + nr_count[type]++; + in_count++; + } + + ret = regmap_read(hwmon->regmap, PMU_REG_FAN_PWM_COUNT, &fan_count); + if (ret) + return ret; + nr_count[hwmon_pwm] = fan_count; + + /* finally allocate channel info */ + cinfo_count = fan_count + in_count; + + cinfos = devm_kcalloc(&pdev->dev, cinfo_count, + sizeof (*cinfos), GFP_KERNEL); + if (!cinfos) + return -ENOMEM; + + ptr_cinfos = devm_kcalloc(&pdev->dev, cinfo_count + 1, + sizeof (*ptr_cinfos), GFP_KERNEL); + if (!ptr_cinfos) + return -ENOMEM; + + pmu_hwmon_chip_info.info = ptr_cinfos; + + for (type = 0; type < hwmon_max; type++) { + u32 *cfg; + + if (!nr_count[type]) + continue; + + cfg = devm_kcalloc(&pdev->dev, nr_count[type] + 1, + sizeof (*cfg), GFP_KERNEL); + if (!cfg) + return -ENOMEM; + + for (i = 0; i < nr_count[type]; i++) + cfg[i] = hwmon_attributes[type]; + + cinfos->type = type; + cinfos->config = cfg; + *ptr_cinfos++ = cinfos++; + } + + hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, + "fbxgwr_pmu_hwmon", + hwmon, + &pmu_hwmon_chip_info, + NULL); + return PTR_ERR_OR_ZERO(hwmon_dev); +} + +static struct platform_driver fbxgwr_pmu_hwmon_driver = { + .probe = fbxgwr_pmu_hwmon_probe, + .driver = { + .name = "fbxgwr-pmu-hwmon", + }, +}; + +module_platform_driver(fbxgwr_pmu_hwmon_driver); + +MODULE_AUTHOR("Marios Makassikis"); +MODULE_LICENSE("GPL"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/hwmon/ld6710-fbx.c 2023-05-22 20:06:40.267748043 +0200 @@ -0,0 +1,340 @@ +/* + * ld6710-fbx.c for ld6710-fbx + * Created by on Wed Sep 25 15:01:56 2019 + */ + +/* + * Driver for LD6710 power deliverance with freebox specific + * firmware. The power supply temperature report on the I2C register + * space is a feature of the ROMed firmware on the chip, which depends + * on the OEM. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LD6710_CHIPVER 0x00 +#define LD6710_FWVER 0x01 + +#define LD6710_SINK_CURRENT 0x10 +#define LD6710_SINK_CURRENT_MAX 0x11 + +#define LD6710_SINK_TEMP 0x20 +#define LD6710_SINK_TEMP_TURNOFF 0x21 +#define LD6710_SINK_TEMP_TURNON 0x22 + +#define LD6710_SINK_STATUS 0x30 +#define SINK_STATUS_OTP (1 << 0) +#define SINK_STATUS_OCP (1 << 1) +#define SINK_STATUS_OVP (1 << 2) + +struct ld6710_priv { + struct device *hwmon_dev; + struct i2c_client *client; + struct mutex mutex; +}; + +static int ld6710_read(struct ld6710_priv *priv, u8 addr) +{ + int ret; + + ret = i2c_smbus_read_byte_data(priv->client, addr); + if (ret < 0) { + dev_err(&priv->client->dev, "i2c read error at address %02x\n", + addr); + return 0xff; + } + return ret; +} + +static void ld6710_write(struct ld6710_priv *priv, u8 addr, u8 value) +{ + i2c_smbus_write_byte_data(priv->client, addr, value); +} + +static struct ld6710_priv *to_ld6710_priv(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + return i2c_get_clientdata(client); +} + +/* + * chip / fw + */ +static ssize_t version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + u32 v; + + mutex_lock(&priv->mutex); + v = ld6710_read(priv, sattr->nr); + mutex_unlock(&priv->mutex); + + return sprintf(buf, "0x%02x\n", v); +} + +static SENSOR_DEVICE_ATTR_2_RO(chipver, version, LD6710_CHIPVER, 0); +static SENSOR_DEVICE_ATTR_2_RO(fwver, version, LD6710_FWVER, 0); + +static struct attribute *ld6710_ver_attrs[] = { + &sensor_dev_attr_chipver.dev_attr.attr, + &sensor_dev_attr_fwver.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_ver_group = { + .attrs = ld6710_ver_attrs, +}; + +/* + * sink current (mA) + */ +static ssize_t current_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + u32 v; + + mutex_lock(&priv->mutex); + v = ld6710_read(priv, sattr->nr) * 100; + mutex_unlock(&priv->mutex); + + return sprintf(buf, "%d\n", v); +} + +static ssize_t current_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + val /= 100; + if (val > 255) + return -EINVAL; + + mutex_lock(&priv->mutex); + ld6710_write(priv, sattr->nr, val); + mutex_unlock(&priv->mutex); + + return count; +} + +static SENSOR_DEVICE_ATTR_2_RO(sink_current, current, LD6710_SINK_CURRENT, 0); +static SENSOR_DEVICE_ATTR_2_RO(in1_input, current, LD6710_SINK_CURRENT, 0); +static SENSOR_DEVICE_ATTR_2_RW(sink_current_max, current, + LD6710_SINK_CURRENT_MAX, 0); + +static struct attribute *ld6710_sink_current_attrs[] = { + &sensor_dev_attr_in1_input.dev_attr.attr, + &sensor_dev_attr_sink_current.dev_attr.attr, + &sensor_dev_attr_sink_current_max.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_sink_current_group = { + .attrs = ld6710_sink_current_attrs, +}; + +/* + * sink temperature (1/1000th degree) + */ +static ssize_t temperature_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + u32 v; + + mutex_lock(&priv->mutex); + v = ld6710_read(priv, sattr->nr) * 1000; + mutex_unlock(&priv->mutex); + + return sprintf(buf, "%d\n", v); +} + +static ssize_t temperature_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + val /= 1000; + if (val > 255) + return -EINVAL; + + mutex_lock(&priv->mutex); + ld6710_write(priv, sattr->nr, val); + mutex_unlock(&priv->mutex); + + return count; +} + +static SENSOR_DEVICE_ATTR_2_RO(temp1_input, temperature, LD6710_SINK_TEMP, 0); +static SENSOR_DEVICE_ATTR_2_RW(temp1_turnoff, temperature, + LD6710_SINK_TEMP_TURNOFF, 0); +static SENSOR_DEVICE_ATTR_2_RW(temp1_turnon, temperature, + LD6710_SINK_TEMP_TURNON, 0); + + +static struct attribute *ld6710_sink_temp_attrs[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_turnoff.dev_attr.attr, + &sensor_dev_attr_temp1_turnon.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_sink_temp_group = { + .attrs = ld6710_sink_temp_attrs, +}; + +/* + * status + */ +static ssize_t status_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return version_show(dev, attr, buf); +} + +static SENSOR_DEVICE_ATTR_2_RO(status, status, LD6710_SINK_STATUS, 0); + +static struct attribute *ld6710_status_attrs[] = { + &sensor_dev_attr_status.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_status_group = { + .attrs = ld6710_status_attrs, +}; + + +static void ld6710_fbx_remove_files(struct i2c_client *client) +{ + sysfs_remove_group(&client->dev.kobj, &ld6710_ver_group); + sysfs_remove_group(&client->dev.kobj, &ld6710_sink_current_group); + sysfs_remove_group(&client->dev.kobj, &ld6710_sink_temp_group); + sysfs_remove_group(&client->dev.kobj, &ld6710_status_group); +} + +static int ld6710_fbx_probe(struct i2c_client *client) +{ + struct ld6710_priv *priv; + u8 chipver, fwver; + int error; + + dev_info(&client->dev, "probe\n"); + + priv = devm_kzalloc(&client->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->client = client; + mutex_init(&priv->mutex); + i2c_set_clientdata(client, priv); + + /* + * read chipver and fwver and check that they look sane. + */ + chipver = ld6710_read(priv, LD6710_CHIPVER); + fwver = ld6710_read(priv, LD6710_FWVER); + if (chipver == 0xff || fwver == 0xff) { + dev_err(&client->dev, "invalid chip version of firmware " + "version.\n"); + return -ENXIO; + } + + dev_info(&client->dev, "LD6710 chip %02x, fw %02x\n", + chipver, fwver); + + /* + * create attributes + */ + error = sysfs_create_group(&client->dev.kobj, &ld6710_ver_group); + if (error) + goto remove_files; + + error = sysfs_create_group(&client->dev.kobj, + &ld6710_sink_current_group); + if (error) + goto remove_files; + + error = sysfs_create_group(&client->dev.kobj, &ld6710_sink_temp_group); + if (error) + goto remove_files; + + error = sysfs_create_group(&client->dev.kobj, &ld6710_status_group); + if (error) + goto remove_files; + + /* + * register hwmon device. + */ + priv->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(priv->hwmon_dev)) { + dev_err(&client->dev, "unable to register hwmon device.\n"); + error = PTR_ERR(priv->hwmon_dev); + goto remove_files; + } + + return 0; + +remove_files: + ld6710_fbx_remove_files(client); + return error; +} + +static void ld6710_fbx_remove(struct i2c_client *client) +{ + struct ld6710_priv *priv = i2c_get_clientdata(client); + + dev_info(&client->dev, "remove\n"); + + hwmon_device_unregister(priv->hwmon_dev); + ld6710_fbx_remove_files(priv->client); +} + +static const struct of_device_id ld6710_fbx_of_match[] = { + { .compatible = "leadtrend,ld6710-fbx" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ld6710_fbx_of_match); + + +static const unsigned short ld6710_addrs[] = { 0x68, /* maybe some others ? */ + I2C_CLIENT_END }; + +static struct i2c_driver ld6710_fbx_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "ld6710_fbx", + .of_match_table = of_match_ptr(ld6710_fbx_of_match), + }, + .probe = ld6710_fbx_probe, + .remove = ld6710_fbx_remove, + .address_list = ld6710_addrs, +}; + +module_i2c_driver(ld6710_fbx_driver); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/leds/leds-fbxgwr-pmu.c 2023-06-22 21:43:23.074921233 +0200 @@ -0,0 +1,117 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +struct fbxgwr_pmu_led; + +struct pmu_led { + struct led_classdev ldev; + u32 reg; + struct fbxgwr_pmu_led *priv; +}; + +struct fbxgwr_pmu_led { + struct regmap *regmap; + struct pmu_led *leds; + size_t nleds; +}; + +static int fbxgwr_pmu_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) +{ + struct pmu_led *led = container_of(led_cdev, struct pmu_led, ldev); + + return regmap_write(led->priv->regmap, led->reg, brightness); +} + +static int fbxgwr_pmu_led_probe(struct platform_device *pdev) +{ + struct device_node *node, *child; + struct fbxgwr_pmu_led *priv; + struct pmu_led *led; + u32 nleds; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(struct fbxgwr_pmu_led), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!priv->regmap) + return -ENODEV; + + ret = of_property_read_u32(pdev->dev.of_node, "nleds", &nleds); + if (ret) { + dev_err(&pdev->dev, "missing nleds property in DT\n"); + return ret; + } + + led = devm_kcalloc(&pdev->dev, nleds, sizeof(struct pmu_led), + GFP_KERNEL); + if (!led) + return -ENOMEM; + + priv->nleds = nleds; + priv->leds = led; + + node = pdev->dev.of_node; + + for_each_child_of_node(node, child) { + u32 reg; + + led->ldev.name = + of_get_property(child, "label", NULL) ?: child->name; + led->ldev.flags = 0; + led->ldev.brightness_set_blocking = + fbxgwr_pmu_led_brightness_set; + led->ldev.max_brightness = LED_FULL; + + ret = of_property_read_u32(child, "reg", ®); + if (ret || reg >= nleds) { + of_node_put(child); + return -EINVAL; + } + + led->reg = PMU_REG_LED0_PWM + reg; + + ret = regmap_read(priv->regmap, led->reg, + &led->ldev.brightness); + if (ret) + return ret; + + ret = devm_led_classdev_register(&pdev->dev, &led->ldev); + if (ret) + return ret; + + led->priv = priv; + + led++; + } + + return 0; +} + +static const struct of_device_id fbxgwr_pmu_led_of_id[] = { + { .compatible = "freebox,fbxgwr-pmu-led", }, + {} +}; +MODULE_DEVICE_TABLE(of, fbxgwr_pmu_led_of_id); + +static struct platform_driver fbxgwr_pmu_led_driver = { + .probe = fbxgwr_pmu_led_probe, + .driver = { + .name = "fbxgwr-pmu-led", + .of_match_table = fbxgwr_pmu_led_of_id, + }, +}; + +module_platform_driver(fbxgwr_pmu_led_driver); + +MODULE_AUTHOR("Marios Makassikis"); +MODULE_LICENSE("GPL"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/mfd/fbxgwr-pmu.c 2024-03-18 14:40:14.839741005 +0100 @@ -0,0 +1,671 @@ +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * private context + */ +struct fbxgwr_pmu { + struct i2c_client *i2c_client; + struct regmap *regmap; + u32 board_id; + u32 app_ver_rev; + u32 api_major; + u32 api_minor; +}; + +/* XXX dummy func to disable regmap caching */ +static bool volatile_reg(struct device *dev, unsigned int reg) +{ + return true; +} + +static const struct regmap_config fbxgwr_pmu_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, + + .volatile_reg = volatile_reg, +}; + +static const struct mfd_cell fbxgwr_pmu_devs[] = { + MFD_CELL_OF("fbxgwr-pmu-gpio", NULL, + NULL, 0, 0, "freebox,fbxgwr-pmu-gpio"), + MFD_CELL_OF("fbxgwr-pmu-led", NULL, + NULL, 0, 0, "freebox,fbxgwr-pmu-led"), + MFD_CELL_NAME("fbxgwr-pmu-hwmon"), + MFD_CELL_OF("fbxgwr-pmu-watchdog", NULL, + NULL, 0, 0, "freebox,fbxgwr-pmu-watchdog"), +}; + +static ssize_t pmu_board_id_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", priv->board_id); +} + +static ssize_t pmu_app_version_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + + return sprintf(buf, "%u.%u\n", + priv->app_ver_rev >> 16, + priv->app_ver_rev & 0xffff); +} + +static ssize_t pmu_app_iversion_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", priv->app_ver_rev); +} + +static ssize_t pmu_api_major_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", priv->api_major); +} + +static ssize_t pmu_api_minor_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", priv->api_minor); +} + +static ssize_t pmu_test_mode_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int ret; + u32 val; + + ret = regmap_read(priv->regmap, PMU_REG_TEST_MODE, &val); + if (ret) + return -EIO; + + return sprintf(buf, "0x%x\n", val); +} + +static ssize_t pmu_cur_app_bank_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int ret; + u32 val; + + ret = regmap_read(priv->regmap, PMU_REG_CUR_APP_BANK, &val); + if (ret) + return -EIO; + + return sprintf(buf, "%u\n", val); +} + +static ssize_t pmu_fw_capabilities_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + size_t len; + u32 val; + int ret; + + ret = regmap_read(priv->regmap, PMU_REG_FW_CAPABILITIES, &val); + if (ret) + return -EIO; + + buf[0] = 0; + len = 0; + if (val & PMU_FW_CAP_FWUPGRADE) + len += scnprintf(buf + len, PAGE_SIZE - len, "fw_upgrade "); + if (val & PMU_FW_CAP_BANK_SWITCH) + len += scnprintf(buf + len, PAGE_SIZE - len, "bank_switch "); + if (val & PMU_FW_CAP_RTC) + len += scnprintf(buf + len, PAGE_SIZE - len, "rtc "); + if (val & PMU_FW_CAP_STANDBY) + len += scnprintf(buf + len, PAGE_SIZE - len, "standby "); + if (val & PMU_FW_CAP_WDT) + len += scnprintf(buf + len, PAGE_SIZE - len, "watchdog "); + if (val & PMU_FW_CAP_GPIO_IRQ) + len += scnprintf(buf + len, PAGE_SIZE - len, "gpio-irq"); + + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); + return len; +} + +static ssize_t pmu_rtc_reg_show(struct device *dev, + struct device_attribute *attr, + char *buf, + int base) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + u32 val[4], rtc; + int ret, i; + + for (i = 0; i < 4; i++) { + ret = regmap_read(priv->regmap, base + i, val + i); + if (ret) + return -EIO; + } + + rtc = (val[3] << 24) | (val[2] << 16) | (val[1] << 8) | val[0]; + return sprintf(buf, "%u\n", rtc); +} + +static ssize_t pmu_rtc_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return pmu_rtc_reg_show(dev, attr, buf, PMU_REG_RTC_VALUE_0); +} + +static ssize_t pmu_rtc_cmp_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return pmu_rtc_reg_show(dev, attr, buf, PMU_REG_RTC_CMP_VALUE_0); +} + +static ssize_t pmu_rtc_cmp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int rtc; + int ret, i; + + rtc = simple_strtoul(buf, NULL, 10); + if (rtc < 0) + return ret; + + for (i = 0; i < 4; i++) { + ret = regmap_write(priv->regmap, PMU_REG_RTC_CMP_VALUE_0 + i, + (rtc >> (i * 8)) & 0xff); + if (ret) + return -EIO; + } + return len; +} + +static ssize_t pmu_board_reset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int val, ret; + + val = simple_strtoul(buf, NULL, 10); + if (val < 0) + return val; + if (val > 0) { + ret = regmap_write(priv->regmap, PMU_REG_BOARD_RESET, + PMU_RESET_MAGIC); + if (ret) + return -EIO; + } + return len; +} + +static ssize_t pmu_fake_dgasp_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int val, ret; + + val = simple_strtoul(buf, NULL, 10); + if (val < 0) + return val; + if (val > 0) { + ret = regmap_write(priv->regmap, PMU_REG_FAKE_DGASP, + PMU_FAKE_DGASP_MAGIC); + if (ret) + return -EIO; + } + return len; +} + +static ssize_t pmu_enter_standby_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int val, ret; + + val = simple_strtoul(buf, NULL, 10); + if (val < 0) + return val; + if (val > 0) { + /* clear wake reason */ + ret = regmap_write(priv->regmap, PMU_REG_WAKE_REASON_MASK, + 0xff); + if (ret) + return -EIO; + ret = regmap_write(priv->regmap, PMU_REG_ENTER_STANDBY, + PMU_STANDBY_MAGIC); + if (ret) + return -EIO; + } + return len; +} + +static ssize_t pmu_wake_pon_interval_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int ret; + u32 val; + + ret = regmap_read(priv->regmap, PMU_REG_WAKE_PON_INTERVAL, &val); + if (ret) + return -EIO; + + return sprintf(buf, "%u\n", val); +} + +static ssize_t pmu_wake_pon_interval_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int val, ret; + + val = simple_strtoul(buf, NULL, 10); + if (val < 0) + return val; + if (val >= 0) { + ret = regmap_write(priv->regmap, PMU_REG_WAKE_PON_INTERVAL, + val); + if (ret) + return -EIO; + } + return len; +} + +static ssize_t pmu_wake_src_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + size_t len; + u32 val; + int ret; + + ret = regmap_read(priv->regmap, PMU_REG_WAKE_SRC_MASK, &val); + if (ret) + return -EIO; + + buf[0] = 0; + len = 0; + if (val & PMU_WAKE_R_RTC_MASK) + len += scnprintf(buf + len, PAGE_SIZE - len, "rtc "); + if (val & PMU_WAKE_R_PWRBTN_MASK) + len += scnprintf(buf + len, PAGE_SIZE - len, "button "); + if (val & PMU_WAKE_R_WAKEPON_MASK) + len += scnprintf(buf + len, PAGE_SIZE - len, "pon "); + + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); + return len; +} + +static ssize_t pmu_wake_src_enabled_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + int ret, i, argc; + char **args; + u32 val; + + args = argv_split(GFP_KERNEL, buf, &argc); + if (args == NULL) + return -ENOMEM; + + val = 0; + for (i = 0; i < argc; i++) { + if (!strcmp(args[i], "rtc")) + val |= PMU_WAKE_R_RTC_MASK; + else if (!strcmp(args[i], "button")) + val |= PMU_WAKE_R_PWRBTN_MASK; + else if (!strcmp(args[i], "pon")) + val |= PMU_WAKE_R_WAKEPON_MASK; + else { + argv_free(args); + return -EINVAL; + } + } + + argv_free(args); + ret = regmap_write(priv->regmap, PMU_REG_WAKE_SRC_MASK, val); + if (ret) + return -EIO; + + return len; +} + +static ssize_t pmu_wake_src_available_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "rtc button pon\n"); +} + + +static ssize_t pmu_last_wake_reason_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + const char *reason; + u32 val; + int ret; + + ret = regmap_read(priv->regmap, PMU_REG_WAKE_REASON_MASK, &val); + if (ret) + return -EIO; + + reason = "unknown"; + if (!val) + reason = "power-on-reset"; + else if (val & PMU_WAKE_R_RTC_MASK) + reason = "rtc"; + else if (val & PMU_WAKE_R_PWRBTN_MASK) + reason = "button"; + else if (val & PMU_WAKE_R_WAKEPON_MASK) + reason = "pon"; + else if (val & PMU_WAKE_R_WDT_RST_MASK) + reason = "wdt-reset"; + else if (val & PMU_WAKE_R_SOC_RST_MASK) + reason = "soc-reset"; + + return sprintf(buf, "%s\n", reason); +} + +static ssize_t pmu_last_wake_reason_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + int ret; + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + + ret = regmap_write(priv->regmap, PMU_REG_WAKE_REASON_MASK, ~0); + if (ret) + return -EIO; + + return len; +} + +static ssize_t pmu_mcu_reboot_reason_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + const char *reason; + u32 val; + int ret; + + ret = regmap_read(priv->regmap, PMU_REG_PMU_RESET_REASON, &val); + if (ret) + return -EIO; + + switch (val) { + case PMU_RESET_R_POR: + reason = "power-on-reset"; + break; + case PMU_RESET_R_SWRESET: + reason = "swreset"; + break; + case PMU_RESET_R_VDROP: + reason = "vdrop"; + break; + case PMU_RESET_R_HWRESET: + reason = "hwreset"; + break; + case PMU_RESET_R_WATCHDOG: + reason = "watchdog"; + break; + case PMU_RESET_R_BUS_ERROR: + reason = "bus_error"; + break; + case PMU_RESET_R_SRAM_PARITY: + reason = "sram_parity"; + break; + case PMU_RESET_R_BOOTSTRAP: + reason = "bootstrap"; + break; + default: + reason = "unknown"; + break; + } + + return sprintf(buf, "%s\n", reason); +} + +static ssize_t pmu_cc_polarity_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct fbxgwr_pmu *priv = dev_get_drvdata(dev); + const char *reason; + u32 val; + int ret; + + ret = regmap_read(priv->regmap, PMU_REG_CC_POLARITY, &val); + if (ret) + return -EIO; + + switch (val) { + case PMU_CC_POLARITY_CC1: + reason = "cc1"; + break; + case PMU_CC_POLARITY_CC2: + reason = "cc2"; + break; + case PMU_CC_POLARITY_UNKNOWN: + default: + reason = "unknown"; + break; + } + + return sprintf(buf, "%s\n", reason); +} + +static DEVICE_ATTR_RO(pmu_board_id); +static DEVICE_ATTR_RO(pmu_app_iversion); +static DEVICE_ATTR_RO(pmu_app_version); +static DEVICE_ATTR_RO(pmu_api_major); +static DEVICE_ATTR_RO(pmu_api_minor); +static DEVICE_ATTR_RO(pmu_test_mode); +static DEVICE_ATTR_RO(pmu_cur_app_bank); +static DEVICE_ATTR_RO(pmu_fw_capabilities); +static DEVICE_ATTR_RO(pmu_rtc); +static DEVICE_ATTR_RW(pmu_rtc_cmp); +static DEVICE_ATTR_WO(pmu_board_reset); +static DEVICE_ATTR_WO(pmu_enter_standby); +static DEVICE_ATTR_WO(pmu_fake_dgasp); +static DEVICE_ATTR_RO(pmu_wake_src_available); +static DEVICE_ATTR_RW(pmu_wake_src_enabled); +static DEVICE_ATTR_RW(pmu_wake_pon_interval); +static DEVICE_ATTR_RW(pmu_last_wake_reason); +static DEVICE_ATTR_RO(pmu_mcu_reboot_reason); +static DEVICE_ATTR_RO(pmu_cc_polarity); + +static struct attribute *sysfs_attrs_ctrl[] = { + &dev_attr_pmu_board_id.attr, + &dev_attr_pmu_app_iversion.attr, + &dev_attr_pmu_app_version.attr, + &dev_attr_pmu_api_major.attr, + &dev_attr_pmu_api_minor.attr, + &dev_attr_pmu_test_mode.attr, + &dev_attr_pmu_cur_app_bank.attr, + &dev_attr_pmu_fw_capabilities.attr, + &dev_attr_pmu_rtc.attr, + &dev_attr_pmu_rtc_cmp.attr, + &dev_attr_pmu_board_reset.attr, + &dev_attr_pmu_enter_standby.attr, + &dev_attr_pmu_fake_dgasp.attr, + &dev_attr_pmu_wake_src_available.attr, + &dev_attr_pmu_wake_src_enabled.attr, + &dev_attr_pmu_wake_pon_interval.attr, + &dev_attr_pmu_last_wake_reason.attr, + &dev_attr_pmu_mcu_reboot_reason.attr, + &dev_attr_pmu_cc_polarity.attr, + NULL, +}; + +static const struct attribute_group pmu_attribute_group[] = { + { .attrs = sysfs_attrs_ctrl }, +}; + +static int fbxgwr_pmu_i2c_probe(struct i2c_client *i2c) +{ + struct fbxgwr_pmu *priv; + u32 magic0, magic1, val; + int ret; + + priv = devm_kzalloc(&i2c->dev, sizeof(struct fbxgwr_pmu), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + i2c_set_clientdata(i2c, priv); + priv->i2c_client = i2c; + priv->regmap = devm_regmap_init_i2c(i2c, &fbxgwr_pmu_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + /* read magic */ + ret = regmap_read(priv->regmap, PMU_REG_MAGIC0, &magic0); + if (ret) + return ret; + + ret = regmap_read(priv->regmap, PMU_REG_MAGIC1, &magic1); + if (ret) + return ret; + + if (magic0 != PMU_MAGIC0_VAL || magic1 != PMU_MAGIC1_VAL) { + dev_err(&i2c->dev, "invalid magic\n"); + return -EINVAL; + } + + ret = regmap_read(priv->regmap, PMU_REG_APP_REVISION_LO, &val); + if (ret) + return -EIO; + priv->app_ver_rev = (val << 0); + + ret = regmap_read(priv->regmap, PMU_REG_APP_REVISION_HI, &val); + if (ret) + return -EIO; + priv->app_ver_rev |= (val << 8); + + ret = regmap_read(priv->regmap, PMU_REG_APP_VERSION_LO, &val); + if (ret) + return -EIO; + priv->app_ver_rev |= (val << 16); + + ret = regmap_read(priv->regmap, PMU_REG_APP_VERSION_HI, &val); + if (ret) + return -EIO; + priv->app_ver_rev |= (val << 24); + + ret = regmap_read(priv->regmap, PMU_REG_API_MAJOR, &priv->api_major); + if (ret) + return -EIO; + + ret = regmap_read(priv->regmap, PMU_REG_API_MINOR, &priv->api_minor); + if (ret) + return -EIO; + + ret = regmap_read(priv->regmap, PMU_REG_BOARD_ID, &priv->board_id); + if (ret) + return -EIO; + + ret = sysfs_create_group(&i2c->dev.kobj, pmu_attribute_group); + if (ret < 0) { + dev_err(&i2c->dev, "Sysfs registration failed\n"); + return ret; + } + + ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_NONE, + fbxgwr_pmu_devs, + ARRAY_SIZE(fbxgwr_pmu_devs), NULL, 0, 0); + if (ret) { + dev_err(&i2c->dev, "failed to register subdevices\n"); + return ret; + } + + dev_info(&i2c->dev, "Freebox PMU driver (fwver:%d.%d api:%d.%d)\n", + priv->app_ver_rev >> 16, priv->app_ver_rev & 0xffff, + priv->api_major, priv->api_minor); + + return 0; +} + +static void fbxgwr_pmu_i2c_remove(struct i2c_client *i2c) +{ + sysfs_remove_group(&i2c->dev.kobj, pmu_attribute_group); +} +const struct of_device_id fbxgwr_pmu_match[] = { + { .compatible = "freebox,fbxgwr-pmu" }, + { /* sentinel */ }, +}; + +static struct i2c_driver fbxgwr_pmu_driver = { + .driver = { + .name = "fbxgwr_pmu", + .of_match_table = of_match_ptr(fbxgwr_pmu_match), + }, + .probe_new = fbxgwr_pmu_i2c_probe, + .remove = fbxgwr_pmu_i2c_remove, +}; + +static int __init fbxgwr_pmu_i2c_init(void) +{ + int ret; + + ret = i2c_add_driver(&fbxgwr_pmu_driver); + if (ret != 0) + pr_err("Failed to register Freebox PMU driver: %d\n", ret); + + return 0; +} + +static void __exit fbxgwr_pmu_i2c_exit(void) +{ + i2c_del_driver(&fbxgwr_pmu_driver); +} + +module_init(fbxgwr_pmu_i2c_init); +module_exit(fbxgwr_pmu_i2c_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Marios Makassikis"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/misc/dgasp.c 2023-09-01 15:04:29.529632893 +0200 @@ -0,0 +1,207 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct { + struct kthread_worker *worker; + struct kthread_work dgasp_work; + struct device *dev; +} g; + +ATOMIC_NOTIFIER_HEAD(dgasp_notifier_list); + +static DEFINE_PER_CPU(spinlock_t, dgasp_cpu_lock); + +static void other_cpu_dgasp_func(void *info) +{ + spinlock_t *lock = &per_cpu(dgasp_cpu_lock, smp_processor_id()); + + local_irq_disable(); + spin_lock(lock); + while (1) + cpu_relax(); +} + +static DEFINE_PER_CPU(call_single_data_t, dgasp_csd) = + CSD_INIT(other_cpu_dgasp_func, NULL); + +/* + * + */ +static void dgasp_work_func(struct kthread_work *work) +{ + struct gpio_descs *toset_gpiod; + struct gpio_descs *toreset_gpiod; + unsigned int i; + int old_level; + + /* request all GPIOs now */ + old_level = console_loglevel; + console_loglevel = CONSOLE_LOGLEVEL_SILENT; + toset_gpiod = gpiod_get_array_optional(g.dev, "toset", + GPIOD_ASIS | + GPIOD_FLAGS_BIT_NONEXCLUSIVE); + console_loglevel = old_level; + if (IS_ERR(toset_gpiod)) { + printk(KERN_CRIT "dgasp: failed to get toset gpios\n"); + toset_gpiod = NULL; + } + + console_loglevel = CONSOLE_LOGLEVEL_SILENT; + toreset_gpiod = gpiod_get_array_optional(g.dev, "toreset", + GPIOD_ASIS | + GPIOD_FLAGS_BIT_NONEXCLUSIVE); + if (IS_ERR(toreset_gpiod)) { + printk(KERN_CRIT "dgasp: failed to get toreset gpios\n"); + toreset_gpiod = NULL; + } + console_loglevel = old_level; + + /* neutralize other CPUs ASAP */ + for_each_online_cpu(i) { + spinlock_t *lock = &per_cpu(dgasp_cpu_lock, i); + spin_lock_init(lock); + } + + for_each_online_cpu(i) { + call_single_data_t *csd = &per_cpu(dgasp_csd, i); + if (i != smp_processor_id()) + smp_call_function_single_async(i, csd); + } + + /* wait for other CPUs to be dead */ + for_each_online_cpu(i) { + spinlock_t *lock = &per_cpu(dgasp_cpu_lock, i); + + if (i == smp_processor_id()) + continue; + while (!spin_is_locked(lock)) + ; + } + + /* disable interrupts on this CPU */ + local_irq_disable(); + + /* now that other CPUs cannot trigger any panic/error, toggle + * all GPIOs (toggling PCI reset could have caused unexpected + * exceptions otherwise) */ + if (toset_gpiod) { + for (i = 0; i < toset_gpiod->ndescs; i++) + gpiod_direction_output(toset_gpiod->desc[i], 1); + } + if (toreset_gpiod) { + for (i = 0; i < toreset_gpiod->ndescs; i++) + gpiod_direction_output(toreset_gpiod->desc[i], 0); + } + + /* call notifiers */ + atomic_notifier_call_chain(&dgasp_notifier_list, 0, NULL); + + /* wait to die */ + printk("dying gasp sent\n"); + while (1) + cpu_relax(); +} + +/* + * + */ +static irqreturn_t dgasp_irq(int irq, void *data) +{ + kthread_queue_work(g.worker, &g.dgasp_work); + disable_irq_nosync(irq); + return IRQ_HANDLED; +} + +/* + * + */ +static int dgasp_probe(struct platform_device *pdev) +{ + struct kthread_worker *worker; + struct gpio_descs *gpiod; + int ret, irq; + + printk("dgasp probe\n"); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return dev_err_probe(&pdev->dev, irq, + "failed to get dgasp interrupt\n"); + + /* sanity check on all gpios so we detect any error now */ + gpiod = gpiod_get_array_optional(&pdev->dev, "toset", + GPIOD_ASIS | + GPIOD_FLAGS_BIT_NONEXCLUSIVE); + if (IS_ERR(gpiod)) + return dev_err_probe(&pdev->dev, PTR_ERR(gpiod), + "failed to get dgasp toset gpios"); + if (gpiod) + gpiod_put_array(gpiod); + + gpiod = gpiod_get_array_optional(&pdev->dev, "toreset", + GPIOD_ASIS | + GPIOD_FLAGS_BIT_NONEXCLUSIVE); + if (IS_ERR(gpiod)) + return dev_err_probe(&pdev->dev, PTR_ERR(gpiod), + "failed to get dgasp toreset gpios"); + if (gpiod) + gpiod_put_array(gpiod); + + worker = kthread_create_worker(0, "dgasp-worker"); + if (IS_ERR(worker)) + return dev_err_probe(&pdev->dev, PTR_ERR(worker), + "failed to create worker\n"); + sched_set_fifo_low(worker->task); + + g.worker = worker; + kthread_init_work(&g.dgasp_work, dgasp_work_func); + g.dev = &pdev->dev; + + ret = devm_request_irq(&pdev->dev, irq, dgasp_irq, + IRQF_ONESHOT | IRQF_NO_THREAD, + "dgasp", NULL); + if (ret < 0) { + kthread_destroy_worker(worker); + return dev_err_probe(&pdev->dev, ret, "request irq failed\n"); + } + + return 0; +} + +/* + * + */ +static int dgasp_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct of_device_id id_table_dgasp[] = { + { .compatible = "misc,dgasp" }, + {} +}; + +MODULE_DEVICE_TABLE(of, id_table_dgasp); + +static struct platform_driver dgasp_driver = { + .probe = dgasp_probe, + .remove = dgasp_remove, + .driver = { + .name = "dgasp", + .of_match_table = id_table_dgasp, + }, +}; + +module_platform_driver(dgasp_driver); + +MODULE_AUTHOR("Maxime Bizon "); +MODULE_DESCRIPTION("Driver for dying gasp"); +MODULE_LICENSE("GPL v2"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/misc/fbxserial_of.c 2023-02-27 19:50:19.752184110 +0100 @@ -0,0 +1,38 @@ +#include +#include +#include +#include + +static struct fbx_serial serial_info; + +const struct fbx_serial *arch_get_fbxserial(void) +{ + return &serial_info; +} + +EXPORT_SYMBOL(arch_get_fbxserial); + +/* + * + */ +static __init int fbxserial_of_read(void) +{ + struct device_node *np; + const void *fbxserial_data; + int len; + + np = of_find_node_by_path("/chosen"); + if (!np) + return 0; + + fbxserial_data = of_get_property(np, "fbx,serialinfo", &len); + if (!fbxserial_data) + return 0; + + fbxserialinfo_read(fbxserial_data, &serial_info); + add_device_randomness(&serial_info, sizeof (serial_info)); + + return 0; +} + +arch_initcall(fbxserial_of_read); diff -Nruw linux-6.4-fbx/drivers/misc/hdmi-cec./Kconfig linux-6.4-fbx/drivers/misc/hdmi-cec/Kconfig --- linux-6.4-fbx/drivers/misc/hdmi-cec./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/misc/hdmi-cec/Kconfig 2023-03-09 15:06:11.352233904 +0100 @@ -0,0 +1,15 @@ +menu "HDMI CEC support" + +config HDMI_CEC + tristate "HDMI CEC (Consumer Electronics Control) support" + help + HDMI Consumer Electronics Control support. + +config HDMI_CEC_REMOTI + tristate "RemoTI CEC driver" + depends on HDMI_CEC + select REMOTI + help + HDMI CEC driver using RemoTI IPCs. + +endmenu diff -Nruw linux-6.4-fbx/drivers/misc/hdmi-cec./Makefile linux-6.4-fbx/drivers/misc/hdmi-cec/Makefile --- linux-6.4-fbx/drivers/misc/hdmi-cec./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/misc/hdmi-cec/Makefile 2023-03-09 15:06:11.352233904 +0100 @@ -0,0 +1,6 @@ +obj-$(CONFIG_HDMI_CEC) += hdmi-cec.o +hdmi-cec-objs += core.o dev.o + +# drivers +obj-$(CONFIG_HDMI_CEC_REMOTI) += remoti-cec.o +remoti-cec-objs := remoti.o diff -Nruw linux-6.4-fbx/drivers/misc/remoti./Kconfig linux-6.4-fbx/drivers/misc/remoti/Kconfig --- linux-6.4-fbx/drivers/misc/remoti./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/misc/remoti/Kconfig 2023-03-09 15:06:11.352233904 +0100 @@ -0,0 +1,26 @@ +menu "RemoTI support" + +config REMOTI + tristate "RemoTI support" + depends on FBX6HD + help + Texas Instruments RemoTI stack. + +config REMOTI_LEDS + tristate "RemoTI LEDS support" + depends on REMOTI + depends on LEDS_CLASS + help + RemoTI LEDS class driver support. + +config REMOTI_GPIO + tristate "RemoTI gpio support" + depends on REMOTI + help + gpiochip driver for the RemoTI RNP + +config REMOTI_USER + tristate "RemoTI userspace access" + depends on REMOTI + +endmenu diff -Nruw linux-6.4-fbx/drivers/misc/remoti./Makefile linux-6.4-fbx/drivers/misc/remoti/Makefile --- linux-6.4-fbx/drivers/misc/remoti./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/misc/remoti/Makefile 2023-03-09 15:06:11.352233904 +0100 @@ -0,0 +1,9 @@ +obj-$(CONFIG_REMOTI) += remoti.o +obj-$(CONFIG_REMOTI_GPIO) += remoti-gpio.o +obj-$(CONFIG_REMOTI_LEDS) += remoti-leds.o +obj-$(CONFIG_REMOTI_USER) += remoti-user.o + +remoti-objs := core.o core-sysfs.o +remoti-gpio-objs := gpio.o +remoti-leds-objs := leds.o +remoti-user-objs := user.o diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./Makefile linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/Makefile --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/Makefile 2023-05-22 20:06:41.435779111 +0200 @@ -0,0 +1,2 @@ +obj-$(CONFIG_BCM63158_SF2) += sf2/ +obj-$(CONFIG_BCM63158_ENET_RUNNER) += enet/ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/Makefile linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/Makefile --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/Makefile 2023-03-09 15:06:11.356234011 +0100 @@ -0,0 +1,11 @@ +obj-$(CONFIG_BCM63158_ENET_RUNNER) += bcm63158_enet_runner.o + +bcm63158_enet_runner-y := \ + ethtool.o \ + main.o \ + port_unimac.o \ + port_xport.o \ + port_xport_serdes.o \ + port_xport_epon.o \ + port_xport_epon_dbg.o \ + port_xport_xlmac.o diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/bcm63158_enet_runner.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/bcm63158_enet_runner.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/bcm63158_enet_runner.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/bcm63158_enet_runner.h 2023-09-01 15:04:29.529632893 +0200 @@ -0,0 +1,292 @@ +#ifndef BCM63158_ENET_RUNNER_H_ +#define BCM63158_ENET_RUNNER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "enet_fw_defs.h" + +#define BCM_ENET_RUNNER_MAX_RXQ 1 +#define BCM_ENET_RUNNER_MAX_TXQ 2 + +enum bcm_runner_port_type { + BCM_RUNNER_PORT_UNIMAC, + BCM_RUNNER_PORT_XPORT, +}; + +/* + * note: RDP has a maximum MTU hardcoded, prevent setting mac do a + * value higher than it has + */ +#define BCM_RUNNER_MAC_MAX_MTU 2048 + +/* + * ethtool private flags + */ +#define PRIV_FLAGS_FORCE_LBE_OE_BIT 0 +#define PRIV_FLAGS_FORCE_LBE_OE_VAL_BIT 1 +#define PRIV_FLAGS_ST_SYNC_OK_BIT 2 + +struct bcm_runner_ethtool_stat { + char stat_string[ETH_GSTRING_LEN]; + unsigned int size; + unsigned int offset; + unsigned int reg; + unsigned int type; +}; + +struct rx_queue { + int index; + unsigned int ring_size; + unsigned int rx_curr_desc; + unsigned int rx_desc_area_size; + + struct rx_desc *rx_desc_area; + dma_addr_t rx_desc_dma; + void **frags; +}; + +struct tx_queue_pdata { + /* keep SKB & len separated because if we + * transmit a clone, then len may change and + * during reclaim we must unmap using same len + * that was mapped */ + void *data; + unsigned int len; +}; + +struct tx_queue { + /* + * "hot" fields first + */ + spinlock_t tx_lock; + unsigned int ring_size; + unsigned int tx_cur_desc; + unsigned int tx_dirty_desc; + struct tx_desc *tx_desc_area; + struct tx_queue_pdata *tx_desc_pdata; + + int index; + unsigned int tx_desc_area_size; + dma_addr_t tx_desc_dma; + + uint8_t use_dsa:1; + uint8_t dsa_port:4; + uint8_t dsa_queue:3; + uint8_t dsa_imp_port:4; +}; + +/* + * per port/mode operations + */ +struct bcm_enet_runner_priv; + +struct bcm_enet_mode_ops { + const char *name; + + /* called *before* init */ + u32 (*get_bbh_id)(void *port_priv); + + /* called only before netdevice is registred or when netdevice + * is down */ + void *(*init)(void *port_priv, + const struct bcm_xrdp_enet_params *); + void (*release)(void *mode_priv); + + /* called on netdevice stop, after runner & netdev queue are + * stopped, no start() operation, first phylink_mac_config() + * calls act the start() operation */ + void (*stop)(void *mode_priv); + + /* set interface mtu */ + void (*mtu_set)(void *mode_priv, unsigned int size); + + /* check if sending this packet type is allowed */ + bool (*can_send)(void *mode_priv, unsigned int protocol); + + /* stats update */ + void (*stats_update)(void *mode_priv, + struct net_device_stats *); + + /* mib operation */ + const struct bcm_runner_ethtool_stat *mib_estat; + size_t mib_estat_count; + void (*mib_update)(void *mode_priv); + void *(*mib_get_data)(void *mode_priv); + + /* get/set private on netdevice */ + u32 (*get_priv_flags)(void *mode_priv); + int (*set_priv_flags)(void *mode_priv, u32 flags); + + /* ethtool epon params callback */ + int (*get_epon_param)(void *mode_priv, + struct ethtool_epon_param *); + int (*set_epon_param)(void *mode_priv, + const struct ethtool_epon_param *); + + /* dgasp operation */ + bool dgasp_supported; + int (*dgasp_gen_data)(void *mode_priv, + u8 *buf, size_t buf_len); + + /* + * phylink callback + */ + void (*phylink_mac_config)(void *mode_priv, + unsigned int pl_mode, + const struct phylink_link_state *); + + int (*phylink_pcs_config)(void *mode_priv, + unsigned int mode, + phy_interface_t interface, + const unsigned long *advertising); + void (*phylink_link_down)(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface); + + void (*phylink_link_up)(void *mode_priv, + unsigned int plmode, + phy_interface_t interface, + int speed, int duplex, + struct phy_device *phy); + int (*phylink_pcs_get_state)(void *mode_priv, + struct phylink_link_state *); + void (*phylink_pcs_an_restart)(void *mode_priv); +}; + +struct bcm_enet_port_ops { + const struct bcm_enet_mode_ops *modes[4]; + size_t mode_count; + + /* phylink validate for this port */ + void (*phylink_validate)(unsigned long *supported, + struct phylink_link_state *state); + int pcs_poll; + + /* select correct mode for given interface */ + int (*mode_select)(phy_interface_t interface); + + /* return list of supported interfaces */ + void (*get_supported_interfaces)(unsigned long *); + + /* return mac capabilities */ + void (*get_mac_capabilities)(unsigned long *); + + /* called once at modprobe/rmmod */ + void *(*init)(struct bcm_enet_runner_priv *); + void (*release)(void *port_priv); + + void (*pcs_shutdown)(void *port_priv); +}; + +struct bcm_dsa_port { + struct net_device *slave_netdev; + unsigned int imp_port; + unsigned int port; + struct list_head next; +}; + +struct queue_info { + char irq_name[32]; + cpumask_t irq_affinity_mask; + struct irq_affinity_notify affinity_notifier; +}; + +struct bcm_enet_runner_priv { + /* + * valid after probe + */ + struct net_device *netdev; + struct bcm_xrdp_priv *xrdp; + struct phylink *phylink; + struct phylink_config phylink_config; + struct phylink_pcs phylink_pcs; + struct platform_device *pdev; + + const struct bcm_enet_port_ops *port_ops; + void *port_priv; + enum bcm_runner_port_type port_type; + + bool reset_scheduled; + struct delayed_work reset_link_work; + + struct queue_info rxq_info[BCM_ENET_RUNNER_MAX_RXQ]; + struct queue_info txq_info[BCM_ENET_RUNNER_MAX_TXQ]; + + struct notifier_block netdev_notifier; + bool netdev_notifier_registered; + struct list_head dsa_ports; + struct notifier_block dgasp_nb; + + /* + * valid after netdevice is opened + */ + unsigned int pkt_size; + unsigned int frag_size; + + /* + * valid when valid mode is selected + */ + const struct bcm_enet_mode_ops *mode_ops; + void *mode_priv; + struct bcm_xrdp_enet_params xrdp_params; + + struct napi_struct napi; + u32 irq_mask; + u32 work_todo; + u32 work_batch; + + struct rx_queue rxq[BCM_ENET_RUNNER_MAX_RXQ]; + unsigned int rxq_size; + + struct tx_queue txq[BCM_ENET_RUNNER_MAX_TXQ]; + u8 txq_port_map[DSA_MAX_PORTS]; + unsigned int txq_count; + unsigned int txq_size; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + unsigned int ff_hw_id; + struct tx_queue *ff_txq; + struct task_struct *ff_reclaim_thread; +#endif +}; + +extern struct dentry *bcm63158_dbg_root; + +extern const size_t bcm_runner_fw_estat_count; +extern const struct bcm_runner_ethtool_stat bcm_runner_fw_estat[]; +u64 bcm_runner_fw_read_estat(struct bcm_enet_runner_priv *priv, int idx); +void bcm_runner_fw_stop_tx(struct bcm_enet_runner_priv *priv); +bool bcm_runner_fw_tx_is_stopped(struct bcm_enet_runner_priv *priv); +void bcm_runner_fw_tx_stop_wait(struct bcm_enet_runner_priv *priv); +bool bcm_runner_fw_bbh_is_empty(struct bcm_enet_runner_priv *priv); + +int bcm_enet_runner_toggle_mode(struct bcm_enet_runner_priv *priv, + unsigned int new_mode_idx); + +void bcm_enet_runner_schedule_reset(struct bcm_enet_runner_priv *priv, + unsigned int delay_ms); +void bcm_enet_runner_unschedule_reset(struct bcm_enet_runner_priv *priv); + + +extern const struct ethtool_ops bcm_runner_ethtool_ops; +extern const struct bcm_enet_port_ops port_unimac_ops; +extern const struct bcm_enet_port_ops port_xport_ops; + +#endif /* BCM63158_ENET_RUNNER_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/enet_fw_defs.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/enet_fw_defs.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/enet_fw_defs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/enet_fw_defs.h 2023-03-09 15:06:11.356234011 +0100 @@ -0,0 +1,220 @@ +#ifndef ENET_FW_DEFS_H_ +#define ENET_FW_DEFS_H_ + +#define RX_FQM_BURST 8 +#define RX_FQM_SIZE (RX_FQM_BURST * 3) + +// +// RX global "registers" area, 16 bytes needed +// +#define RX_CONTROL_REG 0x0 +#define RX_CONTROL_RX_EN_SHIFT 0 +#define RX_CONTROL_RX_EN_MASK (1 << RX_CONTROL_RX_EN_SHIFT) +#define RX_CONTROL_RX_EN_F_OFFSET RX_CONTROL_RX_EN_SHIFT +#define RX_CONTROL_RX_EN_F_WIDTH 1 +#define RX_DESC_ADDRESS_REG 0x4 +#define RX_DESC_COUNT_REG 0x8 +#define RX_IRQ_MASK_REG 0xc + +// +// RX Free Queue Manager "registers" area, follows global, 32 + RX_FQM_SCRATCH_AREA size needed +// +#define RX_FQM_STATUS_REG 0x10 +#define RX_FQM_STATUS_RX_EN_SHIFT 0 +#define RX_FQM_STATUS_RX_EN_MASK (1 << RX_FQM_STATUS_RX_EN_SHIFT) +#define RX_FQM_STATUS_RX_EN_F_OFFSET RX_FQM_STATUS_RX_EN_SHIFT +#define RX_FQM_STATUS_RX_EN_F_WIDTH 1 + +#define RX_FQM_STAT_DBG_TASK_CALL_REG 0x14 +#define RX_FQM_STAT_DBG_CPU_RING_IDX_REG 0x18 +#define RX_FQM_STAT_DBG_FULL_REG 0x1c +#define RX_FQM_STAT_DBG_HOST_NOBUF_REG 0x20 + +#define RX_FQM_HEAD_IDX_REG 0x24 /* 8 bits */ +#define RX_FQM_TAIL_IDX_REG 0x25 /* 8 bits */ + +#define RX_FQM_SCRATCH_AREA 0x30 /* RX_FQM_SIZE * CPU_RX_DESC_LEN */ + +// +// RX xfer "registers" area, starts after global regs +// +#define RX_IF_REGS_BASE_OFF 0x100 +#define RX_IF_REGS_PERIF_SIZE 0x50 + +#define RX_XF_STATUS_REG 0x0 +#define RX_XF_STATUS_RX_EN_SHIFT 0 +#define RX_XF_STATUS_RX_EN_MASK (1 << RX_XF_STATUS_RX_EN_SHIFT) +#define RX_XF_STATUS_RX_EN_F_OFFSET RX_XF_STATUS_RX_EN_SHIFT +#define RX_XF_STATUS_RX_EN_F_WIDTH 1 + +#define RX_XF_STAT_RX_CNT_PKT_REG 0x04 +#define RX_XF_STAT_RX_CNT_DROP_NOBUF_REG 0x08 +#define RX_XF_STAT_RX_CNT_DROP_RXDIS_REG 0x0c +#define RX_XF_STAT_RX_CNT_DROP_RXERR_REG 0x10 + +#define RX_XF_STAT_DBG_TASK_CALL_REG 0x14 +#define RX_XF_STAT_DBG_LAST_PD0_REG 0x18 +#define RX_XF_STAT_DBG_LAST_PD1_REG 0x1c +#define RX_XF_STAT_DBG_LAST_PD2_REG 0x20 +#define RX_XF_STAT_DBG_LAST_PD3_REG 0x24 +#define RX_XF_STAT_DBG_LAST_SN_REG 0x28 +#define RX_XF_STAT_DBG_LAST_BN_REG 0x2c +#define RX_XF_STAT_DBG_LAST_PLEN_REG 0x30 +#define RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG 0x34 +#define RX_XF_STAT_DBG_INVALID_PD_CNT_REG 0x38 +#define RX_XF_SCRATCH_CPU_WBACK_DESC 0x3c /* 4 bytes needed */ +#define RX_XF_SCRATCH_CPU_DESC 0x40 /* CPU_RX_DESC_LEN space needed */ +#define RX_XF_SCRATCH_SBPM_REPLY 0x48 /* 8 bytes needed */ + +// +// CPU RX descriptor +// +#define CPU_RX_DESC_LEN 8 +#define CPU_RX_DESC_LEN_LOG2 3 + +#define CPU_RX_DESC0_LEN_SHIFT 0 +#define CPU_RX_DESC0_LEN_MASK (0xffff << CPU_RX_DESC0_LEN_SHIFT) +#define CPU_RX_DESC0_LEN_F_OFFSET CPU_RX_DESC0_LEN_SHIFT +#define CPU_RX_DESC0_LEN_F_WIDTH 16 + +// internal field +#define CPU_RX_DESC0_ABS_IDX_SHIFT 16 +#define CPU_RX_DESC0_ABS_IDX_MASK (0x3fff << CPU_RX_DESC0_ABS_IDX_SHIFT) +#define CPU_RX_DESC0_ABS_IDX_F_OFFSET CPU_RX_DESC0_ABS_IDX_SHIFT +#define CPU_RX_DESC0_ABS_IDX_F_WIDTH 14 + +#define CPU_RX_DESC0_HW_OWNED_SHIFT 31 +#define CPU_RX_DESC0_HW_OWNED_MASK (1 << CPU_RX_DESC0_HW_OWNED_SHIFT) +#define CPU_RX_DESC0_HW_OWNED_F_OFFSET CPU_RX_DESC0_HW_OWNED_SHIFT +#define CPU_RX_DESC0_HW_OWNED_F_WIDTH 1 + +#define CPU_RX_DESC1_OFFSET 4 + +#ifdef __KERNEL__ +struct rx_desc { + __be32 flags_len; + __be32 address; +}; +#endif + + +// +// TX "registers" area, 512 bytes needed +// + +/* fix TX_SCRATCH_SENT_DESC_QIDX if you change this */ +#define TXQ_MAX_COUNT 2 +#define TX_DESC_READ_BURST 8 +#define TX_PD_SEND_BURST 4 + +/* global scoped */ +#define TX_CONTROL_REG 0x0 /* 32 bits */ +#define TX_CONTROL_TX_EN_SHIFT 0 +#define TX_CONTROL_TX_EN_MASK (1 << TX_CONTROL_TX_EN_SHIFT) +#define TX_CONTROL_TX_EN_F_OFFSET TX_CONTROL_TX_EN_SHIFT +#define TX_CONTROL_TX_EN_F_WIDTH 1 + +#define TX_STATUS_REG 0x4 /* 32 bits */ +#define TX_STATUS_TX_EN_SHIFT 0 +#define TX_STATUS_TX_EN_MASK (1 << TX_STATUS_TX_EN_SHIFT) +#define TX_STATUS_TX_EN_F_OFFSET TX_STATUS_TX_EN_SHIFT +#define TX_STATUS_TX_EN_F_WIDTH 1 + +#define TX_BBH_PD_QUEUE_SIZE_REG 0x8 /* 16 bits, must be power of 2 - 1, min value is 3 */ +#define TX_BBH_MDU_QUEUE_ADDR_REG 0xa /* 16 bits */ +#define TX_BBH_BB_ID_REG 0xc /* 8 bits */ +#define TX_EPON_REPORTING_REG 0xd /* 8 bits */ + +#define TX_STAT_CNT_TX_DISABLED_REG 0x10 /* 32 bits */ + +#define TX_STAT_DBG_TASK_CALL_REG 0x14 /* 32 bits */ +#define TX_STAT_DBG_FIFO_FULL_REG 0x18 /* 32 bits */ +#define TX_STAT_DBG_MDU_FW_RECLAIM_IDX_REG 0x1c /* 32 bits */ +#define TX_STAT_DBG_MDU_FW_PUSH_IDX_REG 0x20 /* 32 bits */ + +#define TX_SCRATCH_MAX1 0x24 +#define TX_SCRATCH_MAX2 0x28 +#define TX_SCRATCH_MAX3 0x2c + +/* used for dma & temp */ +#define TX_SCRATCH_SENT_DESC_QIDX 0x30 /* 256 bits: 1 bit for each desc, XXX: works for 2 TX queues only */ +#define TX_SCRATCH_ZERO 0x50 /* 4 bytes needed */ +#define TX_SCRATCH_ACB_STAT_BUF 0x60 /* 8 bytes needed */ + +/* per-queue scoped */ +#define TXQ_REGS_BASE_OFF 0x80 +#define TXQ_REGS_PERQ_SIZE 0x80 +#define TXQ_REGS_PERQ_SIZE_LOG2 7 /* == 128 (0x80) */ + +#define TXQ_OFF_DESC_ADDRESS_REG 0x0 /* 32 bits, DDR queue base address */ +#define TXQ_OFF_DESC_COUNT_REG 0x4 /* 32 bits, must be power of 2, max 2^15 */ +#define TXQ_OFF_IRQ_MASK_REG 0x8 /* 32 bits */ +#define TXQ_OFF_ACB_ENABLED_REG 0xc /* 8 bits */ +#define TXQ_OFF_ACB_QIDX_REG 0xd /* 8 bits */ +#define TXQ_OFF_ACB_CONTROL_REG 0xe /* 16 bits */ +#define TXQ_OFF_TX_DESC_IDX 0x10 /* 8 bits */ +#define TXQ_OFF_TX_DESC_CNT 0x11 /* 8 bits */ +#define TXQ_OFF_RING_PUSH_IDX_REG 0x12 /* 16 bits */ +#define TXQ_OFF_RING_RECLAIM_IDX_REG 0x14 /* 16 bits */ +#define TXQ_OFF_STAT_CNT_PKT_SENT_REG 0x18 /* 32 bits */ +#define TXQ_OFF_STAT_CNT_PKT_RECLAIMED_REG 0x1c /* 32 bits */ +#define TXQ_OFF_STAT_CNT_ACB_QFULL 0x20 /* 32 bits */ +#define TXQ_OFF_ACB_TX_BUF 0x30 /* 16 bytes needed */ +#define TXQ_OFF_TX_DESCS_BUF 0x40 /* CPU_TX_DESC_LEN * TX_DESC_READ_BURST size needed */ + + +/* + * ACB control field format + */ +#define TXQ_ACBCTRL_EGRESS_QUEUE_SHIFT 0 +#define TXQ_ACBCTRL_EGRESS_PORT_SHIFT 3 +#define TXQ_ACBCTRL_IMP_PORT_SHIFT 6 + +#ifdef __KERNEL__ +static inline unsigned int enet_fw_imp_port_map(unsigned int p) +{ + switch (p) { + case 5: + return 1; + case 7: + return 2; + case 8: + return 0; + } + WARN(1, "unknown imp port %d", p); + return 0; +} +#endif + +/* + * runner enet tx descriptor + */ +#define CPU_TX_DESC_LEN 8 +#define CPU_TX_DESC_LEN_LOG2 3 + +#define CPU_TX_DESC0_LEN_SHIFT 0 +#define CPU_TX_DESC0_LEN_MASK (0xffff << CPU_TX_DESC0_LEN_SHIFT) +#define CPU_TX_DESC0_LEN_F_OFFSET CPU_TX_DESC0_LEN_SHIFT +#define CPU_TX_DESC0_LEN_F_WIDTH 16 + +#define CPU_TX_DESC0_HW_OWNED_SHIFT 31 +#define CPU_TX_DESC0_HW_OWNED_MASK (1 << CPU_TX_DESC0_HW_OWNED_SHIFT) +#define CPU_TX_DESC0_HW_OWNED_F_OFFSET CPU_TX_DESC0_HW_OWNED_SHIFT +#define CPU_TX_DESC0_HW_OWNED_F_WIDTH 1 + +/* internal fw use */ +#define CPU_TX_DESC0_ACB_DONE_SHIFT 30 +#define CPU_TX_DESC0_ACB_DONE_MASK (1 << CPU_TX_DESC0_ACB_DONE_SHIFT) +#define CPU_TX_DESC0_ACB_DONE_F_OFFSET CPU_TX_DESC0_ACB_DONE_SHIFT +#define CPU_TX_DESC0_ACB_DONE_F_WIDTH 1 + +#define CPU_TX_DESC1_OFFSET 4 + +#ifdef __KERNEL__ +struct tx_desc { + __be32 flags_len; + __be32 address; +}; +#endif + +#endif /* !ENET_FW_DEFS_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/ethtool.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/ethtool.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/ethtool.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/ethtool.c 2023-05-31 17:11:03.409680387 +0200 @@ -0,0 +1,269 @@ +#include "bcm63158_enet_runner.h" + +static char bcm_enet_runner_driver_name[] = "bcm63158_enet_runner"; +static char bcm_enet_runner_driver_version[] = "1.0"; + +/* + * ethtool callbacks + */ +static void bcm_runner_get_drvinfo(struct net_device *netdev, + struct ethtool_drvinfo *drvinfo) +{ + strlcpy(drvinfo->driver, bcm_enet_runner_driver_name, sizeof(drvinfo->driver)); + strlcpy(drvinfo->version, bcm_enet_runner_driver_version, + sizeof(drvinfo->version)); + strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); + strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info)); +} + +struct ethtool_priv_flags_strings { + const char string[ETH_GSTRING_LEN]; +}; + +static const struct ethtool_priv_flags_strings bcm_runner_priv_flags_strings[] = { + { .string = "force-lbe-output" }, + { .string = "force-lbe-output-value" }, + { .string = "st-sync-ok" }, +}; + +static int bcm_runner_get_sset_count(struct net_device *netdev, + int string_set) +{ + struct bcm_enet_runner_priv *priv; + + priv = netdev_priv(netdev); + + switch (string_set) { + case ETH_SS_STATS: + if (!priv->mode_ops) + return 0; + + return priv->mode_ops->mib_estat_count + bcm_runner_fw_estat_count; + + case ETH_SS_PRIV_FLAGS: + return ARRAY_SIZE(bcm_runner_priv_flags_strings); + + default: + return -EINVAL; + } +} + +static void bcm_runner_get_strings(struct net_device *netdev, + u32 stringset, u8 *data) +{ + struct bcm_enet_runner_priv *priv; + int i, offset; + + priv = netdev_priv(netdev); + switch (stringset) { + case ETH_SS_STATS: + { + const struct bcm_runner_ethtool_stat *estat; + size_t estat_count; + + if (!priv->mode_ops) + return; + + estat = priv->mode_ops->mib_estat; + estat_count = priv->mode_ops->mib_estat_count; + + offset = 0; + for (i = 0; i < estat_count; i++) { + memcpy(data + (i + offset) * ETH_GSTRING_LEN, + estat[i].stat_string, + ETH_GSTRING_LEN); + } + offset += estat_count; + for (i = 0; i < bcm_runner_fw_estat_count; i++) { + memcpy(data + (i + offset) * ETH_GSTRING_LEN, + bcm_runner_fw_estat[i].stat_string, + ETH_GSTRING_LEN); + } + break; + } + + case ETH_SS_PRIV_FLAGS: + memcpy(data, bcm_runner_priv_flags_strings, + sizeof (bcm_runner_priv_flags_strings)); + break; + } +} + + +static void bcm_runner_get_ethtool_stats(struct net_device *netdev, + struct ethtool_stats *stats, + u64 *data) +{ + struct bcm_enet_runner_priv *priv; + size_t i, offset; + + priv = netdev_priv(netdev); + + offset = 0; + if (priv->mode_ops) { + const struct bcm_runner_ethtool_stat *estat; + size_t estat_count; + void *mib_data; + + estat = priv->mode_ops->mib_estat; + estat_count = priv->mode_ops->mib_estat_count; + + priv->mode_ops->mib_update(priv->mode_priv); + mib_data = priv->mode_ops->mib_get_data(priv->mode_priv); + + for (i = 0; i < estat_count; i++) { + const struct bcm_runner_ethtool_stat *s; + char *p; + + s = &estat[i]; + p = (char *)mib_data + s->offset; + data[offset + i] = (s->size == sizeof(u64)) ? + *(u64 *)p : *(u32 *)p; + } + offset += estat_count; + } + + for (i = 0; i < bcm_runner_fw_estat_count; i++) + data[offset + i] = bcm_runner_fw_read_estat(priv, i); +} + +static int bcm_runner_nway_reset(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + return phylink_ethtool_nway_reset(priv->phylink); +} + +static int +bcm_runner_get_link_ksettings(struct net_device *dev, + struct ethtool_link_ksettings *cmd) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + return phylink_ethtool_ksettings_get(priv->phylink, cmd); +} + +static int +bcm_runner_set_link_ksettings(struct net_device *dev, + const struct ethtool_link_ksettings *cmd) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + return phylink_ethtool_ksettings_set(priv->phylink, cmd); +} + +static int +bcm_runner_set_priv_flags(struct net_device *dev, u32 flags) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops) + return -ENETDOWN; + + if (!priv->mode_ops->set_priv_flags) + return -EOPNOTSUPP; + + return priv->mode_ops->set_priv_flags(priv->mode_priv, flags); +} + +static u32 +bcm_runner_get_priv_flags(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops || !priv->mode_ops->get_priv_flags) + return 0; + + return priv->mode_ops->get_priv_flags(priv->mode_priv); +} + +static int +bcm_runner_get_epon_param(struct net_device *dev, + struct ethtool_epon_param *param) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops) + return -ENETDOWN; + + if (!priv->mode_ops->get_epon_param) + return -EOPNOTSUPP; + + return priv->mode_ops->get_epon_param(priv->mode_priv, param); +} + +static int +bcm_runner_set_epon_param(struct net_device *dev, + const struct ethtool_epon_param *param) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops) + return -ENETDOWN; + + if (!priv->mode_ops->set_epon_param) + return -EOPNOTSUPP; + + return priv->mode_ops->set_epon_param(priv->mode_priv, param); +} + +static void +bcm_runner_get_ringparam(struct net_device *dev, + struct ethtool_ringparam *er, + struct kernel_ethtool_ringparam *ker, + struct netlink_ext_ack *extack) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + er->rx_max_pending = 4096; + er->tx_max_pending = 4096; + + er->rx_pending = priv->rxq_size; + er->tx_pending = priv->txq_size; +} + +static int +bcm_runner_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *er, + struct kernel_ethtool_ringparam *ker, + struct netlink_ext_ack *extack) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (er->rx_mini_pending || er->rx_jumbo_pending) + return -EINVAL; + + if (netif_running(dev)) + return -EBUSY; + + priv->rxq_size = er->rx_pending; + priv->txq_size = er->tx_pending; + + return 0; +} + +static struct phylink * +bcm_runner_get_phylink(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + return priv->phylink; +} + +const struct ethtool_ops bcm_runner_ethtool_ops = { + .get_drvinfo = bcm_runner_get_drvinfo, + .get_ethtool_stats = bcm_runner_get_ethtool_stats, + .get_link = ethtool_op_get_link, + .get_sset_count = bcm_runner_get_sset_count, + .get_strings = bcm_runner_get_strings, + .get_priv_flags = bcm_runner_get_priv_flags, + .set_priv_flags = bcm_runner_set_priv_flags, + + .get_epon_param = bcm_runner_get_epon_param, + .set_epon_param = bcm_runner_set_epon_param, + + .nway_reset = bcm_runner_nway_reset, + .get_link_ksettings = bcm_runner_get_link_ksettings, + .set_link_ksettings = bcm_runner_set_link_ksettings, + + .get_ringparam = bcm_runner_get_ringparam, + .set_ringparam = bcm_runner_set_ringparam, + + .get_phylink = bcm_runner_get_phylink, +}; diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/main.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/main.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/main.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/main.c 2024-03-08 17:37:03.600237154 +0100 @@ -0,0 +1,4743 @@ +#include +#include +#include +#include +#include +#include "bcm63158_enet_runner.h" +#include "enet_fw_defs.h" + +struct dentry *bcm63158_dbg_root; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../../net/bridge/br_private.h" +#include "../../../net/fbxbridge/fbxbr_private.h" +#include "../../../net/dsa/slave.h" +#endif + +#define RX_OFFSET (ALIGN(NET_SKB_PAD, SMP_CACHE_BYTES) + 2) + + +/* Ingress and egress opcodes */ +#define BRCM_OPCODE_SHIFT 5 +#define BRCM_OPCODE_MASK 0x7 + +/* Ingress fields */ +/* 1st byte in the tag */ +#define BRCM_IG_TC_SHIFT 2 +#define BRCM_IG_TC_MASK 0x7 +/* 2nd byte in the tag */ +#define BRCM_IG_TE_MASK 0x3 +#define BRCM_IG_TS_SHIFT 7 +/* 3rd byte in the tag */ +#define BRCM_IG_DSTMAP2_MASK 1 +#define BRCM_IG_DSTMAP1_MASK 0xff + +/* + * for FW dev (driver won't write to fw area) + */ +#undef NO_FW_IO + +/* + * discard all rx traffic and re-arm descriptor (for benchmark) + */ +#undef DBG_RX_DISCARD_ALL + +/* + * for dev (debug print on rx/tx) + */ +#undef RX_DBG_PRINT +#undef TX_DBG_PRINT +#undef FFTX_DBG_PRINT + +#ifdef RX_DBG_PRINT +#define rxdbg(...) printk(__VA_ARGS__) +#else +#define rxdbg(...) +#endif + +#ifdef TX_DBG_PRINT +#define txdbg(...) printk(__VA_ARGS__) +#else +#define txdbg(...) +#endif + +#ifdef FFTX_DBG_PRINT +#define fftxdbg(...) printk(__VA_ARGS__) +#else +#define fftxdbg(...) +#endif + +/* + * io accessors, RX global regs + */ +static inline u8 fw_rx_reg_readb(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread8(priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline u16 fw_rx_reg_readh(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread16be(priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline u32 fw_rx_reg_readl(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread32be(priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline void fw_rx_reg_writel(struct bcm_enet_runner_priv *priv, u32 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite32be(val, priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline u32 fw_rx_xf_off(u32 xf_id, u32 reg) +{ + return RX_IF_REGS_BASE_OFF + xf_id * RX_IF_REGS_PERIF_SIZE + reg; +} + +/* + * io accessors, TX global regs + */ +static inline u8 fw_tx_reg_readb(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread8(priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline u16 fw_tx_reg_readh(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread16be(priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline u32 fw_tx_reg_readl(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread32be(priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline u32 fw_txqoff(u32 qidx, u32 reg) +{ + return TXQ_REGS_BASE_OFF + qidx * TXQ_REGS_PERQ_SIZE + reg; +} + +static inline void fw_tx_reg_writel(struct bcm_enet_runner_priv *priv, u32 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite32be(val, priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline void fw_tx_reg_writeh(struct bcm_enet_runner_priv *priv, u16 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite16be(val, priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline void fw_tx_reg_writeb(struct bcm_enet_runner_priv *priv, u8 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite8(val, priv->xrdp_params.tx_regs + offset); +#endif +} + +/* + * FF declarations + */ +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +struct ff_dev_desc { + bool is_hardware; + const char *netdev_name; + const char *bridge_name; +}; + +struct ff_dev_ctx { + __be16 vlan_id; + uint8_t is_hardware:1; + uint8_t hw_id:2; + uint8_t active:1; + uint8_t use_dsa:1; + uint8_t dsa_port:3; + u8 hwaddr[6]; + + struct net_device *netdev; + struct net_device *br_netdev; + struct net_bridge_port *br_port; + struct fbxbr_port *fbxbr_port; + struct net_device *real_netdev; +}; + +struct ff_tun_ctx { + struct net_device *netdev; + u16 mtu; + u8 active:1; + + /* sit parameters */ + union ff_tun_params { + struct { + u32 src; + u32 s6rd_prefix; + u32 s6rd_pmask; + u8 s6rd_plen; + } sit; + + struct { + /* map parameters */ + u32 ipv4_prefix; + u32 ipv4_pmask; + u8 ipv4_plen; + u8 ipv6_plen; + struct in6_addr src; + struct in6_addr br; + + u64 ipv6_prefix; + u32 ea_addr_mask; + u16 ea_port_mask; + u8 psid_len; + u8 ea_lshift; + } map; + } u; +}; + +enum { + FF_HWDEV_ID_UNIMAC0, + FF_HWDEV_ID_UNIMAC1, + FF_HWDEV_ID_UNIMAC2, + FF_HWDEV_ID_FTTH, + + FF_HWDEV_ID_LAST = FF_HWDEV_ID_FTTH, +}; + +enum { + FF_DEV_WLAN1, + FF_DEV_SWP1, + FF_DEV_SWP2, + FF_DEV_SWP3, + FF_DEV_WAN, + FF_DEV_LANWAN0, + FF_DEV_LANWAN1, + + FF_DEV_LAST = FF_DEV_LANWAN1, + FF_DEV_LAN_LAST = FF_DEV_SWP3, +}; + +struct ff_ctx { + struct ff_dev_ctx devs[FF_DEV_LAST + 1]; + struct ff_tun_ctx tun; + u32 jiffies; + struct bcm_enet_runner_priv *ports_by_hw_id[FF_HWDEV_ID_LAST + 1]; + + struct ff_dev_desc devs_desc[FF_DEV_LAST + 1]; + int wan_active_dev; + char tun_netdev_name[IFNAMSIZ]; + char wan_netdev_name[IFNAMSIZ]; +}; + +static struct notifier_block ff_notifier; +static DEFINE_MUTEX(ff_notifier_mutex); +static bool ff_enabled; + +static struct ff_ctx ff = { + .devs_desc = { + [FF_DEV_WLAN1] = { + .is_hardware = false, + .netdev_name = "wlan1", + .bridge_name = "br0", + }, + + [FF_DEV_SWP1] = { + .is_hardware = true, + .netdev_name = "swp1", + .bridge_name = "br0", + }, + + [FF_DEV_SWP2] = { + .is_hardware = true, + .netdev_name = "swp2", + .bridge_name = "br0", + }, + + [FF_DEV_SWP3] = { + .is_hardware = true, + .netdev_name = "swp3", + .bridge_name = "br0", + }, + + [FF_DEV_WAN] = { + .is_hardware = true, + .netdev_name = "ftthpub0", + }, + + [FF_DEV_LANWAN0] = { + .is_hardware = true, + .netdev_name = "lanwanpub0", + }, + + [FF_DEV_LANWAN1] = { + .is_hardware = true, + .netdev_name = "lanwanpub1", + }, + }, +}; + +static bool ff_idx_is_wan(size_t idx) +{ + return (idx == FF_DEV_WAN || + idx == FF_DEV_LANWAN0 || + idx == FF_DEV_LANWAN1); + +} + +static DEFINE_PER_CPU(spinlock_t, ff_plock); + +/* + * ff lock + */ +static void ff_lock_this_cpu(void) +{ + spinlock_t *lock = &per_cpu(ff_plock, raw_smp_processor_id()); + spin_lock(lock); +} + +static void ff_unlock_this_cpu(void) +{ + spinlock_t *lock = &per_cpu(ff_plock, raw_smp_processor_id()); + spin_unlock(lock); +} + +static void ff_lock_cpu_bh(int cpu) +{ + spinlock_t *lock = &per_cpu(ff_plock, cpu); + spin_lock_bh(lock); +} + +static void ff_unlock_cpu_bh(int cpu) +{ + spinlock_t *lock = &per_cpu(ff_plock, cpu); + spin_unlock_bh(lock); +} + +static void ff_lock_all_cpu_bh(void) +{ + int cpu; + + for_each_online_cpu(cpu) + ff_lock_cpu_bh(cpu); +} + +static void ff_unlock_all_cpu_bh(void) +{ + int cpu; + + for_each_online_cpu(cpu) + ff_unlock_cpu_bh(cpu); +} + + +/* + * + */ +static bool __ff_tx_queue_full(struct tx_queue *txq) +{ + unsigned int cur_desc, next_desc; + + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + if (unlikely(next_desc == txq->tx_dirty_desc)) + return true; + + return false; +} + +/* + * + */ +static bool __ff_tx_queue_can_reclaim(struct tx_queue *txq) +{ + struct tx_desc *desc; + unsigned int dirty_desc; + u32 flags_len; + + dirty_desc = txq->tx_dirty_desc; + if (dirty_desc == txq->tx_cur_desc) + return false; + + desc = &txq->tx_desc_area[dirty_desc]; + flags_len = be32_to_cpu(desc->flags_len); + + if ((flags_len & CPU_TX_DESC0_HW_OWNED_MASK)) + return false; + + return true; +} + +static void *ff_tx_queue_frag_reclaim(struct bcm_enet_runner_priv *priv, + unsigned int needed_frag_size) +{ + struct tx_desc *desc; + struct tx_queue *txq = priv->ff_txq; + unsigned int dirty_desc, next_desc; + void *frag; + unsigned int frag_size; + + spin_lock(&txq->tx_lock); + if (!__ff_tx_queue_can_reclaim(txq)) { + spin_unlock(&txq->tx_lock); + return NULL; + } + + dirty_desc = txq->tx_dirty_desc; + desc = &txq->tx_desc_area[dirty_desc]; + frag = txq->tx_desc_pdata[dirty_desc].data; + frag_size = txq->tx_desc_pdata[dirty_desc].len; + txq->tx_desc_pdata[dirty_desc].data = NULL; + + next_desc = dirty_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + txq->tx_dirty_desc = next_desc; + spin_unlock(&txq->tx_lock); + + if (needed_frag_size != frag_size) { + fftxdbg("ffrecl[%s/q%u]: desc_idx:%u, bad size:%u != %u\n", + priv->netdev->name, + txq->index, + dirty_desc, + frag_size, + needed_frag_size); + skb_free_frag(frag); + return NULL; + } + + fftxdbg("ffrecl[%s/q%u]: desc_idx:%u frag:%pS size:%u\n", + priv->netdev->name, + txq->index, + dirty_desc, + frag, + frag_size); + + return frag; +} + +static void *ff_reclaim_any_sent_frag(unsigned int pkt_size, + unsigned int rx_ff_dev_idx, + int ff_peek_first_dev_idx) +{ + struct bcm_enet_runner_priv *oport; + unsigned int hw_id, idx_todo, hwid_done; + void *frag; + size_t i; + + BUG_ON(!ff.devs[ff_peek_first_dev_idx].is_hardware); + hw_id = ff.devs[ff_peek_first_dev_idx].hw_id; + oport = ff.ports_by_hw_id[hw_id]; + if (likely(oport)) { + frag = ff_tx_queue_frag_reclaim(oport, pkt_size); + if (frag) + return frag; + } + + /* + * failed, try other tx queues this port can ff packets to + */ + if (ff_idx_is_wan(rx_ff_dev_idx)) { + idx_todo = ((1 << FF_DEV_SWP1) | + (1 << FF_DEV_SWP2) | + (1 << FF_DEV_SWP3)); + } else if (ff.wan_active_dev != -1) + idx_todo = (1 << ff.wan_active_dev); + else + idx_todo = 0; + + idx_todo &= ~(1 << ff_peek_first_dev_idx); + hwid_done = (1 << hw_id); + + for (i = 0; idx_todo && i < FF_DEV_LAST + 1; i++) { + if (!(idx_todo & (1 << i))) + continue; + + BUG_ON(!ff.devs[i].is_hardware); + hw_id = ff.devs[i].hw_id; + if (hwid_done & (1 << hw_id)) + continue; + + oport = ff.ports_by_hw_id[hw_id]; + if (unlikely(!oport)) + continue; + + frag = ff_tx_queue_frag_reclaim(oport, pkt_size); + if (frag) + return frag; + + hwid_done |= (1 << hw_id); + } + return NULL; +} + +#endif + +static int rxq_refill_desc(struct bcm_enet_runner_priv *priv, + struct rx_queue *rxq, + int desc_idx, + bool unmap, + void *forced_frag) +{ + struct rx_desc *desc; + void *frag; + bool frag_allocated = true; + dma_addr_t addr; + u32 val; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (forced_frag) { + frag = forced_frag; + frag_allocated = false; + } + else +#endif + frag = napi_alloc_frag_align(priv->frag_size, 16); + + if (!frag) + return -ENOMEM; + + desc = &rxq->rx_desc_area[desc_idx]; + if (unmap) { + addr = be32_to_cpu(desc->address); + dma_unmap_single(priv->netdev->dev.parent, + addr, + priv->pkt_size, + DMA_FROM_DEVICE); + } + + addr = dma_map_single(priv->netdev->dev.parent, + frag + RX_OFFSET, + priv->pkt_size, + DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(priv->netdev->dev.parent, addr))) { + printk("dma_map_single failed\n"); + if (frag_allocated) { + rxq->frags[desc_idx] = NULL; + skb_free_frag(frag); + } + return -ENOMEM; + } + + rxdbg("rxq_refill_desc: idx:%u addr:0x%08x\n", + desc_idx, addr); + + rxq->frags[desc_idx] = frag; + desc->address = cpu_to_be32(addr); + wmb(); + val = CPU_RX_DESC0_HW_OWNED_MASK | + (priv->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + desc->flags_len = cpu_to_be32(val); + return 0; +} + +/* + * FF stuff + */ +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +static inline u32 ff_gen_netmask(u8 len) +{ + return htonl(~((1 << (32 - len)) - 1)); +} + +static void __ff_tun_set_params(bool active, + unsigned int mtu, + const union ff_tun_params *tp) +{ + if (!active) { + if (!ff.tun.active) + return; + + printk(KERN_DEBUG "ff: tunnel now NOT active\n"); + ff.tun.active = 0; + return; + } + + if (ff.tun.active) { + if (ff.tun.mtu == mtu && !memcmp(tp, &ff.tun.u, sizeof (*tp))) + return; + } + + ff.tun.mtu = mtu; + memcpy(&ff.tun.u, tp, sizeof (*tp)); + + if (!ff.tun.active) + printk(KERN_DEBUG "ff: tunnel now active\n"); + else + printk(KERN_DEBUG "ff: tunnel params updated\n"); + + ff.tun.active = true; +} + +static void __ff_tun_read_params(void) +{ + union ff_tun_params tp; + const struct ff_dev_ctx *wan_ff_dev; + + if (!ff.tun.netdev) + return; + + if (ff.wan_active_dev == -1) { + __ff_tun_set_params(false, 0, NULL); + return; + } + + wan_ff_dev = &ff.devs[ff.wan_active_dev]; + + memset(&tp, 0, sizeof (tp)); + + if (ff.tun.netdev->type == ARPHRD_SIT) { + const struct ip_tunnel *tun = netdev_priv(ff.tun.netdev); + const struct ip_tunnel_6rd_parm *ip6rd = &tun->ip6rd; + + if (!ip6rd->prefixlen || ip6rd->prefixlen > 32) { + printk(KERN_DEBUG "ff: unsupported 6rd plen\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + if (ff.tun.netdev->mtu + sizeof (struct iphdr) > wan_ff_dev->netdev->mtu) { + printk(KERN_DEBUG "ff: WAN mtu too " + "small for tunnel (%u => %u)\n", + ff.tun.netdev->mtu, wan_ff_dev->netdev->mtu); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.sit.src = tun->parms.iph.saddr; + tp.sit.s6rd_prefix = ip6rd->prefix.s6_addr32[0]; + tp.sit.s6rd_pmask = ff_gen_netmask(ip6rd->prefixlen); + tp.sit.s6rd_plen = ip6rd->prefixlen; + __ff_tun_set_params(true, ff.tun.netdev->mtu, &tp); + return; + } + + if (ff.tun.netdev->type == ARPHRD_TUNNEL6) { + const struct ip6_tnl *t = netdev_priv(ff.tun.netdev); + const struct __ip6_tnl_parm *prm = &t->parms; + const struct __ip6_tnl_fmr *fmr; + + if (ff.tun.netdev->mtu + sizeof (struct ipv6hdr) > + wan_ff_dev->netdev->mtu) { + printk(KERN_DEBUG "ff: WAN mtu too " + "small for tunnel (%u => %u)\n", + ff.tun.netdev->mtu, wan_ff_dev->netdev->mtu); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.map.src = prm->laddr; + tp.map.br = prm->raddr; + + fmr = prm->fmrs; + if (!fmr) { + tp.map.ipv4_prefix = 0; + __ff_tun_set_params(true, ff.tun.netdev->mtu, &tp); + return; + } + + if (fmr->ip6_prefix_len < 32 || + (fmr->ip6_prefix_len + 32 - fmr->ip4_prefix_len > 64)) { + printk(KERN_DEBUG "ff: unsupp MAP-E: eabits " + "span 32 bits\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + if (fmr->offset) { + printk(KERN_DEBUG "ff: unsupp MAP-E: non zero " + "PSID offset\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.map.ipv4_prefix = fmr->ip4_prefix.s_addr; + tp.map.ipv4_pmask = ff_gen_netmask(fmr->ip4_prefix_len); + tp.map.ipv4_plen = fmr->ip4_prefix_len; + tp.map.ipv6_plen = fmr->ip6_prefix_len; + memcpy(&tp.map.ipv6_prefix, &fmr->ip6_prefix, 8); + + tp.map.ea_addr_mask = ~ff_gen_netmask(fmr->ip4_prefix_len); + if (fmr->ea_len <= 32 - fmr->ip4_prefix_len) { + /* v4 prefix or full IP */ + u32 addr_bits; + + addr_bits = fmr->ip4_prefix_len + fmr->ea_len; + if (addr_bits != 32) + tp.map.ea_addr_mask &= ff_gen_netmask(addr_bits); + tp.map.psid_len = 0; + } else { + u8 psid_len; + + psid_len = fmr->ea_len - (32 - fmr->ip4_prefix_len); + tp.map.psid_len = psid_len; + tp.map.ea_port_mask = ff_gen_netmask(psid_len); + } + + tp.map.ea_lshift = 32 - (fmr->ip6_prefix_len - 32) - + fmr->ea_len; + + __ff_tun_set_params(true, ff.tun.netdev->mtu, &tp); + return; + } +} + +static void __ff_tun_capture(void) +{ + struct net_device *dev; + + if (ff.tun.netdev) { + printk(KERN_ERR "ff: error: tun already registered\n"); + return; + } + + dev = dev_get_by_name(&init_net, ff.tun_netdev_name); + if (!dev) { + return; + } + + if (dev->type != ARPHRD_SIT && dev->type != ARPHRD_TUNNEL6) { + return; + } + + if (!(dev->flags & IFF_UP)) { + dev_put(ff.tun.netdev); + return; + } + + ff.tun.netdev = dev; + __ff_tun_read_params(); + printk(KERN_INFO "ff: tun dev grabbed\n"); +} + +static void __ff_tun_release(void) +{ + int was_on = 0; + + if (ff.tun.netdev) { + dev_put(ff.tun.netdev); + ff.tun.netdev = NULL; + was_on = 1; + } + if (was_on) + printk(KERN_INFO "ff: tun dev released\n"); +} + +static void ff_notifier_event_tunnel(struct net_device *dev, + unsigned long event) +{ + ff_lock_all_cpu_bh(); + + switch (event) { + case NETDEV_UP: + if (!ff.tun.netdev) + __ff_tun_capture(); + break; + + case NETDEV_CHANGE: + case NETDEV_CHANGEMTU: + if (ff.tun.netdev == dev) + __ff_tun_read_params(); + break; + + case NETDEV_GOING_DOWN: + case NETDEV_DOWN: + case NETDEV_UNREGISTER: + if (ff.tun.netdev == dev) + __ff_tun_release(); + break; + } + + ff_unlock_all_cpu_bh(); +} + +static int ff_dev_resolve_bridge(struct ff_dev_ctx *ff_dev, + const char *bridge_name) +{ + bool ok = false; + + rcu_read_lock(); + + if (netif_is_bridge_port(ff_dev->netdev)) { + struct net_bridge_port *br_port; + struct net_bridge *br; + + ff_dev->fbxbr_port = NULL; + br_port = br_port_get_rcu(ff_dev->netdev); + if (!br_port) { + ff_dev->br_port = NULL; + goto done; + } + + br = br_port->br; + if (!br) { + ff_dev->br_port = NULL; + goto done; + } + + if (strcmp(br->dev->name, bridge_name)) { + ff_dev->br_port = NULL; + goto done; + } + + ff_dev->br_port = br_port; + if (br->dev->flags & IFF_UP) { + memcpy(ff_dev->hwaddr, br->dev->dev_addr, 6); + ff_dev->br_netdev = br->dev; + ok = true; + } + } + + if (netif_is_fbxbridge_port(ff_dev->netdev)) { + struct fbxbr_port *fbxbr_port; + struct fbxbr *fbxbr; + + ff_dev->br_port = NULL; + fbxbr_port = fbxbr_port_get_rcu(ff_dev->netdev); + if (!fbxbr_port) { + ff_dev->fbxbr_port = NULL; + goto done; + } + + fbxbr = fbxbr_port->br; + if (strcmp(fbxbr->dev->name, bridge_name)) { + ff_dev->fbxbr_port = NULL; + goto done; + } + + ff_dev->fbxbr_port = fbxbr_port_get_rcu(ff_dev->netdev); + if (fbxbr->dev->flags & IFF_UP) + ok = true; + } + +done: + rcu_read_unlock(); + return ok ? 0 : 1; +} + +static bool ff_dev_bridge_is_up(struct ff_dev_ctx *ff_dev) +{ + if (ff_dev->br_port) { + struct net_bridge *br = ff_dev->br_port->br; + if (!br) + return false; + return br->dev->flags & IFF_UP; + } + if (ff_dev->fbxbr_port) + return ff_dev->fbxbr_port->br->dev->flags & IFF_UP; + return false; +} + +static void __ff_select_active_wan(void) +{ + size_t idx; + int matching; + + matching = -1; + for (idx = 0; idx < FF_DEV_LAST + 1; idx++) { + if (!ff_idx_is_wan(idx)) + continue; + if (!ff.devs[idx].active) + continue; + if (strcmp(ff.devs[idx].netdev->name, ff.wan_netdev_name)) + continue; + matching = (int)idx; + break; + } + + if (ff.wan_active_dev != -1) { + if (matching == -1) { + printk(KERN_INFO "ff: no more selected wan\n"); + ff.wan_active_dev = -1; + } else if (matching != ff.wan_active_dev) { + printk(KERN_INFO "ff: selected wan changed\n"); + ff.wan_active_dev = matching; + } + + } else if (matching != -1) { + printk(KERN_INFO "ff: selected wan now %s\n", + ff.wan_netdev_name); + ff.wan_active_dev = matching; + } + __ff_tun_read_params(); +} + +static void ff_dev_mark_active(struct ff_dev_ctx *ff_dev, size_t dev_idx) +{ + ff_lock_all_cpu_bh(); + ff_dev->active = true; + + if (ff_idx_is_wan(dev_idx)) + __ff_select_active_wan(); + + ff_unlock_all_cpu_bh(); + printk(KERN_INFO "ff: ff_dev %s: now active\n", ff_dev->netdev->name); +} + +static void ff_dev_mark_inactive(struct ff_dev_ctx *ff_dev, size_t dev_idx) +{ + bool was_active; + + ff_lock_all_cpu_bh(); + was_active = ff_dev->active; + ff_dev->active = false; + + if (ff_idx_is_wan(dev_idx)) + __ff_select_active_wan(); + + ff_unlock_all_cpu_bh(); + + if (was_active) + printk(KERN_INFO "ff: ff_dev %s: now inactive\n", ff_dev->netdev->name); +} + +static void ff_notifier_event_dev(struct net_device *netdev, + unsigned long event, + unsigned int dev_idx) +{ + const struct ff_dev_desc *desc = &ff.devs_desc[dev_idx]; + struct ff_dev_ctx *ff_dev = &ff.devs[dev_idx]; + struct net_device *real_netdev = netdev; + size_t i; + + switch (event) { + case NETDEV_UP: + case NETDEV_CHANGE: + { + struct dsa_port *dsap = NULL; + bool found; + + if (ff_dev->active) { + /* ignore up event while already active */ + return; + } + + if (is_vlan_dev(netdev)) { + ff_dev->vlan_id = ntohs(vlan_dev_vlan_id(netdev)); + real_netdev = vlan_dev_upper_dev(netdev); + } else + ff_dev->vlan_id = 0; + + if (dsa_is_slave(real_netdev)) { + dsap = dsa_slave_to_port(real_netdev); + real_netdev = dsa_slave_to_master(real_netdev); + } + + if (!(netdev->flags & IFF_UP)) + return; + + if (real_netdev != netdev && !(real_netdev->flags & IFF_UP)) + return; + + /* does this device matches one hardware port */ + if (!desc->is_hardware) + ff_dev->is_hardware = 0; + else { + found = false; + for (i = 0; i < ARRAY_SIZE(ff.ports_by_hw_id); i++) { + struct bcm_enet_runner_priv *port; + + port = ff.ports_by_hw_id[i]; + + if (!port) + continue; + if (port->netdev != real_netdev) + continue; + + found = true; + break; + } + + if (!found) + return; + + if (dsap) { + ff_dev->use_dsa = 1; + ff_dev->dsa_port = dsap->index; + } + ff_dev->hw_id = i; + ff_dev->is_hardware = 1; + } + + if (ff_dev->netdev) + dev_put(ff_dev->netdev); + + ff_dev->netdev = netdev; + dev_hold(netdev); + ff_dev->real_netdev = real_netdev; + memcpy(ff_dev->hwaddr, netdev->dev_addr, 6); + + /* resolve bridge */ + if (desc->bridge_name) { + if (ff_dev_resolve_bridge(ff_dev, desc->bridge_name)) + return; + } + + ff_dev_mark_active(ff_dev, dev_idx); + break; + } + + case NETDEV_CHANGEUPPER: + if (!desc->bridge_name || !ff_dev->netdev) + return; + + if (!ff_dev->active) { + if (!ff_dev_resolve_bridge(ff_dev, desc->bridge_name)) + ff_dev_mark_active(ff_dev, dev_idx); + } else { + if (!ff_dev_bridge_is_up(ff_dev)) + ff_dev_mark_inactive(ff_dev, dev_idx); + } + break; + + case NETDEV_GOING_DOWN: + case NETDEV_DOWN: + case NETDEV_UNREGISTER: + if (!ff_dev->netdev) + return; + + ff_dev_mark_inactive(ff_dev, dev_idx); + + /* remove all references */ + dev_put(netdev); + ff_dev->netdev = NULL; + ff_dev->real_netdev = NULL; + ff_dev->br_port = NULL; + ff_dev->fbxbr_port = NULL; + ff_dev->br_netdev = NULL; + break; + } +} + +static int ff_notifier_event(struct net_device *dev, unsigned long event) +{ + size_t i; + + mutex_lock(&ff_notifier_mutex); + + /* + * check for tun match + */ + if (!strcmp(dev->name, ff.tun_netdev_name)) { + ff_notifier_event_tunnel(dev, event); + mutex_unlock(&ff_notifier_mutex); + return 0; + } + + /* + * check for dev match + */ + for (i = 0; i < ARRAY_SIZE(ff.devs_desc); i++) { + if (!strcmp(dev->name, ff.devs_desc[i].netdev_name)) { + ff_notifier_event_dev(dev, event, i); + mutex_unlock(&ff_notifier_mutex); + return 0; + } + } + + /* + * check for bridge/fbxbridge match + * + * bridge can change up/down status, but lower netdev will not get + * CHANGE_UPPER + */ + if (netif_is_bridge_master(dev) || netif_is_fbxbridge_master(dev)) { + size_t i; + + for (i = 0; i < ARRAY_SIZE(ff.devs_desc); i++) { + struct ff_dev_ctx *ff_dev = &ff.devs[i]; + const char *bridge_name = ff.devs_desc[i].bridge_name; + + if (!bridge_name) + continue; + + if (!ff_dev->netdev) + continue; + + if (!ff_dev->active) { + if (!ff_dev_resolve_bridge(ff_dev, + bridge_name)) + ff_dev_mark_active(ff_dev, i); + } else { + if (!ff_dev_bridge_is_up(ff_dev)) + ff_dev_mark_inactive(ff_dev, i); + } + } + } + + /* + * check for real_dev match + */ + for (i = 0; i < ARRAY_SIZE(ff.devs); i++) { + if (dev == ff.devs[i].real_netdev) + ff_notifier_event_dev(ff.devs[i].netdev, event, i); + } + + mutex_unlock(&ff_notifier_mutex); + return 0; +} + +static int ff_notifier_event_cb(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct net_device *dev = netdev_notifier_info_to_dev(ptr); + + if (!net_eq(dev_net(dev), &init_net)) + return 0; + + ff_notifier_event(dev, event); + return 0; +} + +/* + * ipv4 forward cache private data + */ +struct ff_priv { + struct in6_addr tun_dest_ip6; + struct dst_entry *tun_dst; +}; + +static void ff_priv_release(const struct ff_priv *priv) +{ + dst_release(priv->tun_dst); +} + +static void ff_priv_destructor_cb(void *data) +{ + const struct ff_priv *priv = (const struct ff_priv *)data; + ff_priv_release(priv); +} + +static const struct ff_priv *ffn_get_ro_priv(const struct ffn_lookup_entry *e) +{ + if (e->manip.priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (const struct ff_priv *)e->manip.ffn_priv_area; +} + +static struct ff_priv *ffn_get_rw_priv(struct ffn_lookup_entry *e) +{ + BUILD_BUG_ON(sizeof (e->manip.ffn_priv_area) < + sizeof (struct ff_priv)); + + if (e->manip.priv_destructor && + e->manip.priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (struct ff_priv *)e->manip.ffn_priv_area; +} + +static const struct ff_priv *fwc_get_ro_priv(const struct fbxbr_fwcache *fwc) +{ + if (fwc->priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (const struct ff_priv *)fwc->priv_area; +} + +static struct ff_priv *fwc_get_rw_priv(const struct fbxbr_fwcache *fwc) +{ + BUILD_BUG_ON(sizeof (fwc->priv_area) < sizeof (struct ff_priv)); + + if (fwc->priv_destructor && + fwc->priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (struct ff_priv *)fwc->priv_area; +} + +/* + * ipv6 forward cache private data + */ +struct ff6_priv { + u32 tun_dest_ip; + struct dst_entry *tun_dst; +}; + +static void ff6_priv_release(const struct ff6_priv *priv) +{ + dst_release(priv->tun_dst); +} + +static void ff6_priv_destructor_cb(void *data) +{ + const struct ff6_priv *priv = (const struct ff6_priv *)data; + ff6_priv_release(priv); +} + +static const struct ff6_priv *ffn6_get_ro_priv(const struct ffn6_lookup_entry *e6) +{ + if (e6->manip.priv_destructor != ff6_priv_destructor_cb) + return NULL; + + return (const struct ff6_priv *)e6->manip.ffn_priv_area; +} + +static struct ff6_priv *ffn6_get_rw_priv(struct ffn6_lookup_entry *e6) +{ + BUILD_BUG_ON(sizeof (e6->manip.ffn_priv_area) < + sizeof (struct ff6_priv)); + + if (e6->manip.priv_destructor && + e6->manip.priv_destructor != ff6_priv_destructor_cb) + return NULL; + + return (struct ff6_priv *)e6->manip.ffn_priv_area; +} + + +/* + * + */ +static u32 ff_tun_extract_6rd_addr(const struct in6_addr *d) +{ + u32 a1, a2; + + a1 = ntohl(d->s6_addr32[0] & ~ff.tun.u.sit.s6rd_pmask); + a1 <<= ff.tun.u.sit.s6rd_plen; + + a2 = ntohl(d->s6_addr32[1] & ff.tun.u.sit.s6rd_pmask); + a2 >>= (32 - ff.tun.u.sit.s6rd_plen); + return htonl(a1 | a2); +} + +/* + * + */ +static void ff_tun_gen_mape_addr(u32 addr, u16 port, struct in6_addr *dest) +{ + u32 eabits; + u16 psid; + + eabits = ntohl(addr & ff.tun.u.map.ea_addr_mask) << ff.tun.u.map.psid_len; + psid = 0; + if (ff.tun.u.map.psid_len) { + psid = ntohs(port & ff.tun.u.map.ea_port_mask) >> + (16 - ff.tun.u.map.psid_len); + eabits |= psid; + } + + memcpy(dest, &ff.tun.u.map.ipv6_prefix, 8); + dest->s6_addr32[1] |= htonl(eabits << ff.tun.u.map.ea_lshift); + + dest->s6_addr32[2] = htonl(ntohl(addr) >> 16); + dest->s6_addr32[3] = htonl((ntohl(addr) << 16) | psid); +} + +/* + * broadcom DSA + */ +#define BRCM_TAG_LEN 4 + +#define BRCM_OPCODE_SHIFT 5 +#define BRCM_OPCODE_MASK 0x7 + +struct ff_pkt_info { + __be16 vlan_id; + u8 is_dsa:1; + u8 dsa_port:3; + u8 is_ipv4:1; + u8 l3_hdr_offset; + u16 l3_plen; +}; + +/* 2nd byte in the tag */ +#define BRCM_EG_CID_MASK 0xff + +/* 3rd byte in the tag */ +#define BRCM_EG_RC_MASK 0xff +#define BRCM_EG_RC_RSVD (3 << 6) +#define BRCM_EG_RC_EXCEPTION (1 << 5) +#define BRCM_EG_RC_PROT_SNOOP (1 << 4) +#define BRCM_EG_RC_PROT_TERM (1 << 3) +#define BRCM_EG_RC_SWITCH (1 << 2) +#define BRCM_EG_RC_MAC_LEARN (1 << 1) +#define BRCM_EG_RC_MIRROR (1 << 0) +#define BRCM_EG_TC_SHIFT 5 +#define BRCM_EG_TC_MASK 0x7 +#define BRCM_EG_PID_MASK 0x1f + +/* + * + */ +static bool ff_send(struct bcm_enet_runner_priv *priv, + struct tx_queue *txq, + u32 dma_buf_addr, + void *frag, + u32 frag_size, + unsigned int send_len, + int extra_pad_len) +{ + const struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + struct tx_desc *tx_desc; + unsigned int cur_desc, next_desc; + u32 flags_len; + + /* pad small packets (add more for DSA packets) */ + if (send_len < 60 + extra_pad_len) + send_len = 60 + extra_pad_len; + + dma_sync_single_for_device(priv->netdev->dev.parent, + dma_buf_addr, + send_len, + DMA_TO_DEVICE); + + spin_lock(&txq->tx_lock); + + /* make sure we have room */ + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + if (WARN_ON(unlikely(next_desc == txq->tx_dirty_desc))) { + spin_unlock(&txq->tx_lock); + return 1; + } + + txq->tx_desc_pdata[cur_desc].data = frag; + txq->tx_desc_pdata[cur_desc].len = frag_size; + + /* point to the next available desc */ + txq->tx_cur_desc = next_desc; + + /* update descriptor index */ + flags_len = CPU_TX_DESC0_HW_OWNED_MASK | + (send_len << CPU_TX_DESC0_LEN_SHIFT); + + fftxdbg("ffxmit[%s/q%u]: desc_idx:%u frag:%pS len:%u size:%u\n", + priv->netdev->name, + txq->index, + cur_desc, frag, send_len, frag_size); + + tx_desc = &txq->tx_desc_area[cur_desc]; + tx_desc->address = cpu_to_be32(dma_buf_addr); + wmb(); + tx_desc->flags_len = cpu_to_be32(flags_len); + spin_unlock(&txq->tx_lock); + + bcm_xrdp_api_wakeup(priv->xrdp, + params->tx_core_id, + params->txq_wakeup_thread[0]); + + return 0; +} + +/* + * + */ +static int ff_parse_packet(struct bcm_enet_runner_priv *port, + struct ff_pkt_info *info, + const void *frag, + size_t offset, + size_t eth_len) +{ + const struct ethhdr *eth; + const uint16_t *proto; + + eth = (const struct ethhdr *)((uint8_t *)frag + offset); + + /* extract DSA info */ + if (netdev_uses_dsa(port->netdev)) { + const u8 *brcm_tag; + + brcm_tag = (const u8 *)ð->h_proto; + + if (unlikely((brcm_tag[0] >> BRCM_OPCODE_SHIFT) & BRCM_OPCODE_MASK)) + return 1; + + if (unlikely(brcm_tag[2] & BRCM_EG_RC_RSVD)) + return 1; + + info->is_dsa = 1; + info->dsa_port = brcm_tag[3] & BRCM_EG_PID_MASK; + proto = (const uint16_t *)(brcm_tag + BRCM_TAG_LEN); + eth_len -= BRCM_TAG_LEN; + } else + proto = (const uint16_t *)ð->h_proto; + + if (*proto == htons(ETH_P_8021Q)) { + const struct vlan_hdr *vhdr; + + vhdr = (const struct vlan_hdr *)(proto + 1); + info->vlan_id = vhdr->h_vlan_TCI; + + proto = (const uint16_t *)&vhdr->h_vlan_encapsulated_proto; + info->l3_hdr_offset = (const void *)(vhdr + 1) - (const void *)eth; + info->l3_plen = eth_len - VLAN_ETH_HLEN; + } else { + info->vlan_id = 0; + info->l3_hdr_offset = (const void *)(proto + 1) - (const void *)eth; + info->l3_plen = eth_len - ETH_HLEN; + } + + if (*proto == htons(ETH_P_IP)) { + if (info->l3_plen < sizeof (struct iphdr)) + return 1; + info->is_ipv4 = 1; + return 0; + } + + info->is_ipv4 = 0; + if (*proto == htons(ETH_P_IPV6)) { + if (info->l3_plen < sizeof (struct ipv6hdr)) + return 1; + return 0; + } + + return 1; +} + +enum ff_xmit_mode { + FF_XMIT_IPV4, + FF_XMIT_IPV6, + FF_XMIT_IPV6_IN_IPV4, + FF_XMIT_IPV4_IN_IPV6, +}; + +/* + * + */ +static bool ff_receive(struct bcm_enet_runner_priv *rx_port, + struct rx_queue *rxq, + unsigned int rx_desc_idx, + void *frag, + size_t frag_size, + size_t offset, size_t eth_len) +{ + struct rx_desc *rx_desc; + struct ff_pkt_info pinfo; + struct ethhdr *eth; + struct bcm_enet_runner_priv *tx_port; + struct net_device_stats *tx_hw_stats; + struct net_device *last_rx_dev, *next_tx_dev; + struct ffn_lookup_entry *e = NULL; + struct ffn6_lookup_entry *e6 = NULL; + struct nf_conn *ct = NULL; + enum ff_xmit_mode xmit_mode; + const struct in6_addr *tun_v6_pdest = NULL; + struct net_device *tx_dev; + struct ff_dev_ctx *tx_ff_dev, *rx_ff_dev; + u32 tun_v4_dest = 0; + u8 dest_hw[6]; + u32 buf_addr; + unsigned int timeout; + void *l2_hdr, *l3_hdr, *l4_hdr; + bool l3_is_ipv4, l4_is_tcp; + u16 proto; + u16 *pproto; + size_t i, rx_ff_dev_idx, tx_ff_dev_idx; + bool parsed; + void *new_frag; + + /* make sure we have headroom for the worst case scenario */ + BUILD_BUG_ON(NET_SKB_PAD < + (sizeof (struct ipv6hdr) + VLAN_HLEN + BRCM_TAG_LEN)); + + if (!ff_enabled) + return false; + + if (eth_len < ETH_HLEN) + return false; + + /* locate rx ff device */ + parsed = false; + for (i = 0; i < ARRAY_SIZE(ff.devs); i++) { + if (!ff.devs[i].active) + continue; + + if (ff.devs[i].hw_id != rx_port->ff_hw_id) + continue; + + /* candidate, fully parse packet */ + if (!parsed && + ff_parse_packet(rx_port, &pinfo, frag, offset, eth_len)) + return false; + + parsed = true; + + /* make sure this is the right device */ + if (ff.devs[i].use_dsa) { + if (!pinfo.is_dsa) + continue; + + if (ff.devs[i].dsa_port != pinfo.dsa_port) + continue; + } + + if (ff.devs[i].vlan_id != pinfo.vlan_id) + continue; + + /* device match! */ + break; + } + + if (i == ARRAY_SIZE(ff.devs)) + return false; + + rx_ff_dev_idx = i; + rx_ff_dev = &ff.devs[rx_ff_dev_idx]; + last_rx_dev = rx_ff_dev->netdev; + + /* find opposing device */ + if (ff_idx_is_wan(rx_ff_dev_idx)) { + if (!ff.devs[FF_DEV_LAN_LAST].active) + return false; + + /* XXX: to get bridge/fbxbridge device, assume to be + * the same on all devices, real tx dev not yet + * known */ + if (!ff.devs[FF_DEV_LAN_LAST].fbxbr_port) + tx_dev = ff.devs[FF_DEV_LAN_LAST].br_netdev; + else + tx_dev = ff.devs[FF_DEV_LAN_LAST].netdev; + } else { + if (ff.wan_active_dev != -1) + tx_dev = ff.devs[ff.wan_active_dev].netdev; + else + return false; + } + + if (WARN_ON(!tx_dev)) + return false; + + /* make sure packet is for our mac address */ + eth = (struct ethhdr *)((uint8_t *)frag + offset); + if (memcmp(eth->h_dest, ff.devs[i].hwaddr, 6)) + return false; + + l3_is_ipv4 = pinfo.is_ipv4; + l3_hdr = (u8 *)eth + pinfo.l3_hdr_offset; + + if (l3_is_ipv4) { + struct iphdr *iph; + struct fbxbr_fwcache *fwc; + struct fbxbr *fbxbr = NULL; + struct fbxbr_port *fbxbr_fwd_port = NULL; + u16 sport, dport; + u8 ip_proto; + +handle_ipv4: + iph = (struct iphdr *)l3_hdr; + + /* lookup IP ffn entry */ + if (iph->ihl > 5 || (iph->frag_off & htons(IP_MF | IP_OFFSET))) + return false; + + if (iph->ttl <= 1) + return false; + + ip_proto = iph->protocol; + if (ip_proto == IPPROTO_TCP) { + struct tcphdr *tcph; + + if (pinfo.l3_plen < sizeof (*iph) + sizeof (*tcph)) + return false; + + tcph = (struct tcphdr *)((u8 *)iph + 20); + if (tcph->fin || + tcph->syn || + tcph->rst || + !tcph->ack) { + return false; + } + + sport = tcph->source; + dport = tcph->dest; + l4_hdr = tcph; + l4_is_tcp = true; + + } else if (ip_proto == IPPROTO_UDP) { + struct udphdr *udph; + + if (pinfo.l3_plen < sizeof (*iph) + sizeof (*udph)) + return false; + + udph = (struct udphdr *)((u8 *)iph + 20); + sport = udph->source; + dport = udph->dest; + l4_hdr = udph; + l4_is_tcp = false; + + } else if (ip_proto == IPPROTO_IPV6) { + struct ipv6hdr *ip6hdr; + u32 ip6rd_daddr; + + if (!ff.tun.active) + return false; + + /* must be for us */ + if (iph->daddr != ff.tun.u.sit.src) + return false; + + /* check len */ + if (pinfo.l3_plen < sizeof (struct iphdr) + + sizeof (struct ipv6hdr)) + return false; + + ip6hdr = (struct ipv6hdr *)(iph + 1); + + /* must belong to 6rd prefix */ + if ((ip6hdr->daddr.s6_addr32[0] & + ff.tun.u.sit.s6rd_pmask) != ff.tun.u.sit.s6rd_prefix) + return false; + + /* 6rd address */ + ip6rd_daddr = ff_tun_extract_6rd_addr(&ip6hdr->daddr); + if (ip6rd_daddr != ff.tun.u.sit.src) + return false; + + /* TODO: should check for spoofing here */ + l3_hdr = ip6hdr; + pinfo.l3_plen -= 20; + l3_is_ipv4 = false; + goto handle_ipv6; + + } else + return false; + + if (netif_is_fbxbridge_port(last_rx_dev)) { + struct fbxbr_fwcache_key k; + struct fbxbr_port *p; + u32 hash; + + p = fbxbr_port_get_rcu(last_rx_dev); + fbxbr = p->br; + + if (p->is_wan) { + k.wan_ip = iph->saddr; + k.lan_ip = iph->daddr; + k.wan_port = sport; + k.lan_port = dport; + fbxbr_fwd_port = fbxbr->lan_port; + } else { + k.lan_ip = iph->saddr; + k.wan_ip = iph->daddr; + k.lan_port = sport; + k.wan_port = dport; + fbxbr_fwd_port = fbxbr->wan_port; + } + k.is_tcp = l4_is_tcp; + + if (!unlikely(fbxbr_fwd_port)) + return false; + + hash = fbxbr_fwcache_hash(&k); + fwc = __fbxbr_fwcache_lookup_rcu(p->br, hash, &k); + if (!fwc) + return false; + + next_tx_dev = fbxbr_fwd_port->dev; + e = NULL; + } else { + struct ffn_lookup_key k; + + k.sip = iph->saddr; + k.dip = iph->daddr; + k.sport = sport; + k.dport = dport; + k.is_tcp = l4_is_tcp; + e = __ffn_get_rcu(&k); + if (!e) + return false; + + if (e->manip.dst->obsolete > 0) + return false; + + ct = e->manip.ct; + + /* only fast forward TCP connections in established state */ + if (l4_is_tcp && + ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) + return false; + + next_tx_dev = e->manip.dst->dev; + fwc = NULL; + } + + /* find out if the packet is to be sent as-is or + * tunneled */ + if (ff.tun.netdev && next_tx_dev == ff.tun.netdev) { + const struct ff_priv *ff_priv; + struct ff_priv *ff_wpriv; + struct dst_entry *v6_dst; + const struct in6_addr *pdest, *nexthop; + struct in6_addr dest; + struct rt6_info *rt6; + struct neighbour *neigh; + + /* IPv4 tunneled into MAP-E device */ + if (!ff.tun.active) { + return false; + } + + if (pinfo.l3_plen > ff.tun.mtu) + return false; + + /* lookup ipv6 route cache */ + if (e) + ff_priv = ffn_get_ro_priv(e); + else + ff_priv = fwc_get_ro_priv(fwc); + + if (ff_priv) { + if (ff_priv->tun_dst->obsolete < 0) { + /* valid route found */ + v6_dst = ff_priv->tun_dst; + pdest = &ff_priv->tun_dest_ip6; + goto cached_ipv6_route; + } + + ff_priv_release(ff_priv); + if (e) + e->manip.priv_destructor = NULL; + else + fwc->priv_destructor = NULL; + } + + /* cache miss, compute IPv6 destination */ + if (ff.tun.u.map.ipv4_prefix && + (iph->daddr & ff.tun.u.map.ipv4_pmask) == + ff.tun.u.map.ipv4_prefix) { + /* compute dest using FMR */ + ff_tun_gen_mape_addr(iph->daddr, dport, &dest); + pdest = &dest; + } else { + /* next hop is BR */ + pdest = &ff.tun.u.map.br; + } + + /* v6 route lookup */ + rt6 = rt6_lookup(&init_net, pdest, NULL, 0, NULL, 0); + if (!rt6) + return false; + + if (e) + ff_wpriv = ffn_get_rw_priv(e); + else + ff_wpriv = fwc_get_rw_priv(fwc); + if (!ff_wpriv) + return false; + + /* cache this inside FFN private area */ + ff_wpriv->tun_dst = (struct dst_entry *)rt6; + memcpy(&ff_wpriv->tun_dest_ip6, pdest, 16); + if (e) + e->manip.priv_destructor = ff_priv_destructor_cb; + else + fwc->priv_destructor = ff_priv_destructor_cb; + ff_priv = ff_wpriv; + + v6_dst = (struct dst_entry *)rt6; + +cached_ipv6_route: + if (v6_dst->dev != tx_dev) { + return false; + } + + /* is the neighboor ready ? */ + rt6 = (struct rt6_info *)v6_dst; + nexthop = rt6_nexthop(rt6, (struct in6_addr *)pdest); + if (!nexthop) { + return false; + } + + neigh = __ipv6_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + xmit_mode = FF_XMIT_IPV4_IN_IPV6; + tun_v6_pdest = &ff_priv->tun_dest_ip6; + + } else if (next_tx_dev == tx_dev) { + struct neighbour *neigh; + const struct rtable *rt; + + /* is the neighboor ready ? */ + if (e) { + u32 nexthop; + + rt = (const struct rtable *)e->manip.dst; + nexthop = (__force u32)rt_nexthop(rt, + e->manip.new_dip); + neigh = __ipv4_neigh_lookup_noref(tx_dev, + nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + + memcpy(dest_hw, neigh->ha, 6); + } else { + if (!fbxbr_fwd_port->is_wan) { + if (!fbxbr->have_hw_addr) + return false; + memcpy(dest_hw, fbxbr->lan_hwaddr, 6); + } else { + __be32 nh; + + nh = iph->daddr; + if ((nh & fbxbr->wan_netmask) != + (fbxbr->wan_ipaddr & + fbxbr->wan_netmask)) { + rt = fbxbr_fwd_port->rt; + if (!rt || + rt->dst.obsolete > 0) + return false; + + nh = rt_nexthop(rt, nh); + } + + neigh = __ipv4_neigh_lookup_noref( + tx_dev, nh); + if (!neigh || + !(neigh->nud_state & NUD_VALID)) + return false; + + memcpy(dest_hw, neigh->ha, 6); + } + } + + xmit_mode = FF_XMIT_IPV4; + } else + return false; + + } else { + struct ipv6hdr *ip6hdr; + struct ffn6_lookup_key k; + u16 sport, dport; + u8 ip_proto; + +handle_ipv6: + ip6hdr = (struct ipv6hdr *)l3_hdr; + + if (ip6hdr->hop_limit <= 1 || !ip6hdr->payload_len) + return false; + + if (ntohs(ip6hdr->payload_len) > pinfo.l3_plen) + return false; + + ip_proto = ip6hdr->nexthdr; + + if (ip_proto == IPPROTO_TCP) { + struct tcphdr *tcph; + + if (pinfo.l3_plen < sizeof (*ip6hdr) + sizeof (*tcph)) + return false; + + tcph = (struct tcphdr *)((u8 *)ip6hdr + + sizeof (*ip6hdr)); + + if (tcph->fin || + tcph->syn || + tcph->rst || + !tcph->ack) { + return false; + } + + sport = tcph->source; + dport = tcph->dest; + l4_hdr = tcph; + l4_is_tcp = true; + + } else if (ip_proto == IPPROTO_UDP) { + struct udphdr *udph; + + if (pinfo.l3_plen < sizeof (*ip6hdr) + sizeof (*udph)) + return false; + + udph = (struct udphdr *)((u8 *)ip6hdr + + sizeof (*ip6hdr)); + sport = udph->source; + dport = udph->dest; + l4_hdr = udph; + l4_is_tcp = false; + + } else if (ip_proto == IPPROTO_IPIP) { + struct iphdr *iph; + + if (!ff.tun.active) + return false; + + /* must be for us */ + if (memcmp(&ip6hdr->daddr, &ff.tun.u.map.src, 16)) + return false; + + /* check len */ + if (pinfo.l3_plen < sizeof (struct iphdr) + + sizeof (struct ipv6hdr)) + return false; + + iph = (struct iphdr *)(ip6hdr + 1); + + /* does it come from BR ? */ + if (memcmp(&ip6hdr->saddr, &ff.tun.u.map.br, 16)) { + struct in6_addr exp_src_addr; + + /* no, check FMR for spoofing */ + if (!ff.tun.u.map.ipv4_prefix) + return false; + + /* check up to PSID to reduce lookup + * depth */ + ff_tun_gen_mape_addr(iph->saddr, 0, + &exp_src_addr); + if (!ipv6_prefix_equal(&ip6hdr->saddr, + &exp_src_addr, + ff.tun.u.map.ipv6_plen + + ff.tun.u.map.ipv4_plen)) + return false; + } + + last_rx_dev = ff.tun.netdev; + if (!last_rx_dev) + return false; + + l3_hdr = iph; + pinfo.l3_plen -= sizeof (*ip6hdr); + l3_is_ipv4 = true; + goto handle_ipv4; + + } else + return false; + + k.sip = ip6hdr->saddr.s6_addr32; + k.dip = ip6hdr->daddr.s6_addr32; + k.sport = sport; + k.dport = dport; + k.is_tcp = l4_is_tcp; + e6 = __ffn6_get_rcu(&k); + if (!e6) { + return false; + } + + if (e6->manip.dst->obsolete > 0) { + return false; + } + + ct = e6->manip.ct; + + /* only fast forward TCP connections in established state */ + if (l4_is_tcp && + ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) { + return false; + } + + /* find out if the packet is to be sent as-is or + * tunneled */ + if (ff.tun.netdev && e6->manip.dst->dev == ff.tun.netdev) { + const struct ff6_priv *ff6_priv; + struct ff6_priv *ff6_wpriv; + struct dst_entry *v4_dst; + struct flowi4 fl4; + struct rtable *rt; + struct neighbour *neigh; + u32 dest, nexthop; + + /* IPv6 tunneled into SIT device using 6rd */ + if (!ff.tun.active) { + return false; + } + + if (pinfo.l3_plen > ff.tun.mtu) + return false; + + /* lookup ipv4 route cache */ + ff6_priv = ffn6_get_ro_priv(e6); + if (ff6_priv) { + if (!ff6_priv->tun_dst->obsolete) { + /* valid route found */ + v4_dst = ff6_priv->tun_dst; + dest = ff6_priv->tun_dest_ip; + goto cached_ipv4_route; + } + + ff6_priv_release(ff6_priv); + e6->manip.priv_destructor = NULL; + } + + /* cache miss, compute IPv4 destination */ + if ((ip6hdr->daddr.s6_addr32[0] & + ff.tun.u.sit.s6rd_pmask) == ff.tun.u.sit.s6rd_prefix) { + /* next hop via prefix */ + dest = ff_tun_extract_6rd_addr(&ip6hdr->daddr); + } else { + const struct in6_addr *nh6; + struct rt6_info *rt6; + + /* next hop via route */ + rt6 = (struct rt6_info *)e6->manip.dst; + nh6 = rt6_nexthop(rt6, + (struct in6_addr *)e6->manip.new_dip); + if (!nh6) { + return false; + } + + /* should be a v4 mapped */ + if (nh6->s6_addr32[0] != 0 || + nh6->s6_addr32[1] != 0 || + nh6->s6_addr32[2] != 0) { + return false; + } + + dest = nh6->s6_addr32[3]; + } + + /* v4 route lookup */ + rt = ip_route_output_ports(&init_net, &fl4, NULL, + dest, ff.tun.u.sit.src, + 0, 0, + IPPROTO_IPV6, 0, + 0); + if (IS_ERR(rt) || + rt->rt_type != RTN_UNICAST) + return false; + + ff6_wpriv = ffn6_get_rw_priv(e6); + if (!ff6_wpriv) + return false; + + /* cache this inside FFN private area */ + ff6_wpriv->tun_dst = (struct dst_entry *)rt; + ff6_wpriv->tun_dest_ip = dest; + e6->manip.priv_destructor = ff6_priv_destructor_cb; + + v4_dst = (struct dst_entry *)rt; + ff6_priv = ff6_wpriv; + +cached_ipv4_route: + if (v4_dst->dev != tx_dev) { + return false; + } + + /* is the neighboor ready ? */ + rt = (struct rtable *)v4_dst; + nexthop = (__force u32)rt_nexthop(rt, dest); + neigh = __ipv4_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + tun_v4_dest = dest; + xmit_mode = FF_XMIT_IPV6_IN_IPV4; + + } else if (e6->manip.dst->dev == tx_dev) { + const struct in6_addr *nexthop; + struct rt6_info *rt6; + struct neighbour *neigh; + + /* is the neighboor ready ? */ + rt6 = (struct rt6_info *)e6->manip.dst; + + nexthop = rt6_nexthop(rt6, + (struct in6_addr *)e6->manip.new_dip); + if (!nexthop) + return false; + + neigh = __ipv6_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + xmit_mode = FF_XMIT_IPV6; + } else + return false; + } + + /* compute outgoing device */ + if (!ff_idx_is_wan(rx_ff_dev_idx)) { + tx_ff_dev = &ff.devs[ff.wan_active_dev]; + tx_ff_dev_idx = ff.wan_active_dev; + + } else if (ff.devs[FF_DEV_LAN_LAST].br_port) { + struct net_bridge_port *br_port; + struct net_bridge_fdb_entry *fdb; + + /* XXX get reference to bridge using last lan port */ + br_port = ff.devs[FF_DEV_LAN_LAST].br_port; + fdb = br_fdb_find_rcu(br_port->br, dest_hw, 0); + if (!fdb) + return false; + + tx_ff_dev = NULL; + for (i = 0; i < ARRAY_SIZE(ff.devs); i++) { + if (!ff.devs[i].active) + continue; + if (ff.devs[i].br_port == fdb->dst) { + tx_ff_dev = &ff.devs[i]; + break; + } + } + + if (!tx_ff_dev) { + return false; + } + + tx_ff_dev_idx = i; + + } else if (ff.devs[FF_DEV_LAN_LAST].fbxbr_port) { + tx_ff_dev = &ff.devs[FF_DEV_LAN_LAST]; + tx_ff_dev_idx = FF_DEV_LAN_LAST; + } else + return false; + + /* update rx statistics */ + if (!ff_idx_is_wan(rx_ff_dev_idx) && rx_ff_dev->br_port) { + struct net_bridge *br; + struct net_bridge_port *p; + + /* packet comes from a bridge, make sure we are + * allowed to ingress it */ + p = rx_ff_dev->br_port; + if (p->state != BR_STATE_FORWARDING) + return false; + + /* refresh FDB entry for this source */ + br = netdev_priv(rx_ff_dev->br_netdev); + if (!br_fdb_update_only(br, p, eth->h_source)) + return false; + + dev_sw_netstats_rx_add(br->dev, eth_len); + } + + if (rx_ff_dev->vlan_id) { + struct vlan_dev_priv *vlan = vlan_dev_priv(rx_ff_dev->netdev); + struct vlan_pcpu_stats *stats; + stats = this_cpu_ptr(vlan->vlan_pcpu_stats); + u64_stats_inc(&stats->rx_packets); + u64_stats_add(&stats->rx_bytes, eth_len); + } else { + rx_ff_dev->netdev->stats.rx_packets++; + rx_ff_dev->netdev->stats.rx_bytes += eth_len; + } + + rx_desc = &rxq->rx_desc_area[rx_desc_idx]; + + /* do we have room in the tx queue ? */ + if (tx_ff_dev->is_hardware) { + tx_port = ff.ports_by_hw_id[tx_ff_dev->hw_id]; + + /* XXX: no lock, so this might return wrong result, or + * the queue might become full after (if another cpu + * is pushing to the same tx queue. We take the lock + * later to ensure it won't happen */ + if (__ff_tx_queue_full(tx_port->ff_txq) && + !__ff_tx_queue_can_reclaim(tx_port->ff_txq)) { + /* just rearm descriptor and fake success */ + u32 flags; + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (rx_port->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + return true; + } + } else + tx_port = NULL; + + /* can we allocate a new fragment to replace the descriptor we + * are about to use ? */ + if (tx_ff_dev->is_hardware) { + /* remember RX desc hw address before we reload it and + * point if back to frag hw address */ + buf_addr = be32_to_cpu(rx_desc->address); + buf_addr -= offset; + new_frag = ff_reclaim_any_sent_frag(rx_port->pkt_size, + rx_ff_dev_idx, + tx_ff_dev_idx); + } else { + buf_addr = 0; + new_frag = NULL; + } + + if (rxq_refill_desc(rx_port, rxq, rx_desc_idx, true, new_frag)) { + /* just rearm descriptor and fake success */ + u32 flags; + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (rx_port->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + return true; + } + + if (ct && l4_is_tcp) { + /* don't try to track window anymore on this + * connection */ + ct->proto.tcp.no_window_track = 1; + } + + /* alter l3 & l4 content if needed (routing only) */ + if (l3_is_ipv4 && e) { + struct iphdr *iph = (struct iphdr *)l3_hdr; + + if (e->manip.alter) { + if (l4_is_tcp) { + struct tcphdr *tcph = (struct tcphdr *)l4_hdr; + tcph->source = e->manip.new_sport; + tcph->dest = e->manip.new_dport; + tcph->check = csum16_sub(tcph->check, + e->manip.l4_adjustment); + } else { + struct udphdr *udph = (struct udphdr *)l4_hdr; + udph->source = e->manip.new_sport; + udph->dest = e->manip.new_dport; + if (udph->check) { + u16 tcheck; + + tcheck = csum16_sub(udph->check, + e->manip.l4_adjustment); + udph->check = tcheck ? tcheck : 0xffff; + } + } + + iph->saddr = e->manip.new_sip; + iph->daddr = e->manip.new_dip; + } + + iph->ttl--; + iph->check = csum16_sub(iph->check, + e->manip.ip_adjustment); + + } else if (!l3_is_ipv4 && e6) { + struct ipv6hdr *ip6hdr = (struct ipv6hdr *)l3_hdr; + + if (e6->manip.alter) { + if (l4_is_tcp) { + struct tcphdr *tcph = (struct tcphdr *)l4_hdr; + tcph->source = e6->manip.new_sport; + tcph->dest = e6->manip.new_dport; + tcph->check = csum16_sub(tcph->check, + e6->manip.adjustment); + } else { + struct udphdr *udph = (struct udphdr *)l4_hdr; + udph->source = e6->manip.new_sport; + udph->dest = e6->manip.new_dport; + + if (udph->check) { + u16 tcheck; + + tcheck = csum16_sub(udph->check, + e6->manip.adjustment); + udph->check = tcheck ? tcheck : 0xffff; + } + } + + memcpy(ip6hdr->saddr.s6_addr32, e6->manip.new_sip, 16); + memcpy(ip6hdr->daddr.s6_addr32, e6->manip.new_dip, 16); + } + + ip6hdr->hop_limit--; + } + + /* packet is ready to xmit */ + switch (xmit_mode) { + case FF_XMIT_IPV4: + proto = ETH_P_IP; + break; + + case FF_XMIT_IPV6: + proto = ETH_P_IPV6; + break; + + case FF_XMIT_IPV6_IN_IPV4: + { + struct iphdr *tun_hdr; + /* prepend IPv4 */ + tun_hdr = (struct iphdr *)((u8 *)l3_hdr - sizeof (*tun_hdr)); + tun_hdr->ihl = 5; + tun_hdr->version = 4; + tun_hdr->tos = 0; + tun_hdr->tot_len = htons(pinfo.l3_plen + sizeof (*tun_hdr)); + tun_hdr->id = 0; + tun_hdr->frag_off = 0; + tun_hdr->check = 0; + tun_hdr->ttl = 64; + tun_hdr->protocol = IPPROTO_IPV6; + tun_hdr->saddr = ff.tun.u.sit.src; + tun_hdr->daddr = tun_v4_dest; + tun_hdr->check = ip_fast_csum((u8 *)tun_hdr, 5); + + l3_hdr = (u8 *)tun_hdr; + pinfo.l3_plen += sizeof (*tun_hdr); + + proto = ETH_P_IP; + break; + } + + case FF_XMIT_IPV4_IN_IPV6: + { + struct ipv6hdr *tun_6hdr; + + /* prepend IPv6 */ + tun_6hdr = (struct ipv6hdr *)((u8 *)l3_hdr - sizeof (*tun_6hdr)); + tun_6hdr->version = 6; + tun_6hdr->priority = 0; + memset(tun_6hdr->flow_lbl, 0, sizeof (tun_6hdr->flow_lbl)); + tun_6hdr->payload_len = htons(pinfo.l3_plen); + tun_6hdr->nexthdr = IPPROTO_IPIP; + tun_6hdr->hop_limit = 64; + tun_6hdr->saddr = ff.tun.u.map.src; + tun_6hdr->daddr = *tun_v6_pdest; + + l3_hdr = (u8 *)tun_6hdr; + pinfo.l3_plen += sizeof (*tun_6hdr); + + proto = ETH_P_IPV6; + break; + } + } + + /* add vlan header if any */ + l2_hdr = l3_hdr; + if (tx_ff_dev->vlan_id) { + struct vlan_hdr *vhdr; + + l2_hdr -= VLAN_HLEN; + vhdr = (struct vlan_hdr *)l2_hdr; + vhdr->h_vlan_TCI = tx_ff_dev->vlan_id; + vhdr->h_vlan_encapsulated_proto = htons(proto); + proto = ETH_P_8021Q; + } + + /* add protocol */ + l2_hdr -= sizeof (*pproto); + pproto = (u16 *)l2_hdr; + *pproto = htons(proto); + + /* add DSA header if any */ + if (tx_ff_dev->use_dsa) { + u8 *brcm_tag; + + l2_hdr -= BRCM_TAG_LEN; + brcm_tag = (u8 *)l2_hdr; + brcm_tag[0] = (1 << BRCM_OPCODE_SHIFT); + brcm_tag[1] = 0; + brcm_tag[2] = 0; + if (tx_ff_dev->dsa_port == 8) + brcm_tag[2] = (1 << 0); + brcm_tag[3] = (1 << tx_ff_dev->dsa_port); + } + + /* finally add eth dst/src */ + l2_hdr -= ETH_ALEN * 2; + eth = (struct ethhdr *)l2_hdr; + memcpy(eth->h_dest, dest_hw, 6); + memcpy(eth->h_source, tx_ff_dev->hwaddr, 6); + + /* compute final len */ + eth_len = pinfo.l3_plen + (l3_hdr - l2_hdr); + + /* refresh conntrack */ + if (ct) { + if (l4_is_tcp) + timeout = HZ * 3600 * 24 * 5; + else + timeout = HZ * 180; + + if (ct->timeout - ff.jiffies < timeout - 10 * HZ) { + unsigned long newtime = ff.jiffies + timeout; + ct->timeout = newtime; + } + } + + if (tx_ff_dev->is_hardware) { + if (ff_send(tx_port, + tx_port->ff_txq, + buf_addr + (void *)eth - frag, + frag, + rx_port->pkt_size, + eth_len, + tx_ff_dev->use_dsa ? BRCM_TAG_LEN : 0)) { + skb_free_frag(frag); + return true; + } + + if (tx_ff_dev->vlan_id) { + struct vlan_dev_priv *vlan = vlan_dev_priv(tx_ff_dev->netdev); + struct vlan_pcpu_stats *stats; + stats = this_cpu_ptr(vlan->vlan_pcpu_stats); + u64_stats_inc(&stats->tx_packets); + u64_stats_add(&stats->tx_bytes, eth_len); + } else { + tx_ff_dev->netdev->stats.tx_packets++; + tx_ff_dev->netdev->stats.tx_bytes += eth_len; + } + + if (tx_port->netdev != tx_ff_dev->netdev) { + tx_hw_stats = &tx_port->netdev->stats; + tx_hw_stats->tx_bytes += eth_len; + tx_hw_stats->tx_packets++; + } + } else { + struct sk_buff *skb; + + skb = build_skb(frag, frag_size > PAGE_SIZE ? 0 : frag_size); + if (!skb) { + skb_free_frag(frag); + return true; + } + + skb_reserve(skb, (void *)eth - frag); + skb_put(skb, eth_len); + skb->protocol = eth->h_proto; + skb_set_network_header(skb, l3_hdr - l2_hdr); + skb->dev = tx_ff_dev->netdev; + dev_queue_xmit(skb); + } + + if (!ff_idx_is_wan(tx_ff_dev_idx) && tx_ff_dev->br_port) { + struct net_bridge *br; + br = netdev_priv(tx_ff_dev->br_netdev); + + dev_sw_netstats_tx_add(br->dev, 1, eth_len); + } + + return true; +} + +/* + * + */ +static ssize_t ff_show_enabled(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", ff_enabled); +} + +static ssize_t ff_store_enabled(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + if (ff_enabled == val) + return len; + + printk(KERN_NOTICE "ff: fastpath now %s\n", + val ? "enabled" : "disabled"); + ff_enabled = val; + return len; +} + +static struct device_attribute dev_attr_ff = { + .attr = { .name = "ff_enabled", .mode = (S_IRUGO | S_IWUSR) }, + .show = ff_show_enabled, + .store = ff_store_enabled, +}; + +/* + * + */ +static ssize_t ff_show_tun_dev(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%s\n", ff.tun_netdev_name); +} + +static ssize_t ff_store_tun_dev(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + if (!len || buf[0] == '\n') { + ff.tun_netdev_name[0] = 0; + ff_lock_all_cpu_bh(); + __ff_tun_release(); + ff_unlock_all_cpu_bh(); + printk(KERN_NOTICE "ff: tun dev unset\n"); + return len; + } + + ff_lock_all_cpu_bh(); + __ff_tun_release(); + strncpy(ff.tun_netdev_name, buf, len); + strim(ff.tun_netdev_name); + printk(KERN_NOTICE "ff: tun dev set to %s\n", ff.tun_netdev_name); + __ff_tun_capture(); + ff_unlock_all_cpu_bh(); + return len; +} + +static struct device_attribute dev_attr_tun = { + .attr = { .name = "ff_tun_dev", .mode = (S_IRUGO | S_IWUSR) }, + .show = ff_show_tun_dev, + .store = ff_store_tun_dev, +}; + +/* + * + */ +static ssize_t ff_show_wan_dev(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%s\n", ff.wan_netdev_name); +} + +static ssize_t ff_store_wan_dev(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + if (!len || buf[0] == '\n') { + ff.wan_netdev_name[0] = 0; + ff_lock_all_cpu_bh(); + __ff_select_active_wan(); + ff_unlock_all_cpu_bh(); + printk(KERN_NOTICE "ff: requested wan dev unset\n"); + return len; + } + + ff_lock_all_cpu_bh(); + ff.wan_netdev_name[0] = 0; + __ff_select_active_wan(); + strncpy(ff.wan_netdev_name, buf, len); + strim(ff.wan_netdev_name); + printk(KERN_NOTICE "ff: requested wan dev set to %s\n", + ff.wan_netdev_name); + __ff_select_active_wan(); + ff_unlock_all_cpu_bh(); + return len; +} + +static struct device_attribute dev_attr_wan = { + .attr = { .name = "ff_wan_dev", .mode = (S_IRUGO | S_IWUSR) }, + .show = ff_show_wan_dev, + .store = ff_store_wan_dev, +}; + +static void ff_init(struct device *dev) +{ + static bool done; + int i; + + if (done) + return; + + for_each_possible_cpu(i) { + spinlock_t *lock = &per_cpu(ff_plock, i); + spin_lock_init(lock); + } + + ff.wan_active_dev = -1; + device_create_file(dev, &dev_attr_ff); + device_create_file(dev, &dev_attr_wan); + device_create_file(dev, &dev_attr_tun); + printk(KERN_DEBUG "ff_init\n"); + done = true; +} +#endif + + +/* + * + */ +static void rxq_deinit(struct bcm_enet_runner_priv *priv, struct rx_queue *rxq) +{ + int i; + + for (i = 0; i < rxq->ring_size; i++) { + struct rx_desc *desc; + dma_addr_t addr; + + if (!rxq->frags || !rxq->frags[i]) + continue; + + desc = &rxq->rx_desc_area[i]; + addr = be32_to_cpu(desc->address); + dma_unmap_single(priv->netdev->dev.parent, + addr, + priv->pkt_size, + DMA_FROM_DEVICE); + skb_free_frag(rxq->frags[i]); + } + + if (rxq->rx_desc_area) + dma_free_coherent(priv->netdev->dev.parent, + rxq->rx_desc_area_size, + rxq->rx_desc_area, + rxq->rx_desc_dma); + if (rxq->frags) + kfree(rxq->frags); +} + +/* + * + */ +static int rxq_init(struct bcm_enet_runner_priv *priv, int index) +{ + struct rx_queue *rxq = priv->rxq + index; + int size; + int i; + + memset(rxq, 0, sizeof (*rxq)); + rxq->index = index; + rxq->ring_size = priv->rxq_size; + + size = rxq->ring_size * sizeof (struct rx_desc); + rxq->rx_desc_area_size = size; + rxq->rx_desc_area = dma_alloc_coherent(priv->netdev->dev.parent, + size, &rxq->rx_desc_dma, + GFP_KERNEL); + + if (rxq->rx_desc_area == NULL) { + netdev_err(priv->netdev, + "can't allocate rx ring (%d bytes)\n", size); + goto out; + } + + memset(rxq->rx_desc_area, 0, size); + + rxq->frags = kzalloc(sizeof (*rxq->frags) * rxq->ring_size, GFP_KERNEL); + if (!rxq->frags) { + netdev_err(priv->netdev, "can't allocate rx frags\n"); + goto out; + } + + for (i = 0; i < rxq->ring_size; i++) { + int ret; + + local_bh_disable(); + ret = rxq_refill_desc(priv, rxq, i, false, NULL); + local_bh_enable(); + if (ret) + goto out; + } + + return 0; + +out: + rxq_deinit(priv, rxq); + return -ENOMEM; +} + +/* + * + */ +static int bcm_runner_do_rx(struct bcm_enet_runner_priv *priv, + struct rx_queue *rxq, int budget) +{ + struct net_device_stats *stats = &priv->netdev->stats; + int rx_done; + u32 rcvd_pkts = 0; + u32 rcvd_bytes = 0; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_lock_this_cpu(); +#endif + + rx_done = 0; + while (rx_done < budget) { + struct rx_desc *rx_desc; + struct sk_buff *skb; + void *frag; + u32 flags; + unsigned int idx, pkt_len; + int ret; + + idx = rxq->rx_curr_desc; + rx_desc = &rxq->rx_desc_area[idx]; + + rmb(); + + flags = be32_to_cpu(rx_desc->flags_len); + + rxdbg("bcm_runner_do_rx: idx:%u flags:0x%08x\n", + idx, flags); + + if ((flags & CPU_RX_DESC0_HW_OWNED_MASK)) + break; + + pkt_len = (flags & CPU_RX_DESC0_LEN_MASK) >> + CPU_RX_DESC0_LEN_SHIFT; + pkt_len -= ETH_FCS_LEN; + frag = rxq->frags[idx]; + + rxq->rx_curr_desc++; + rx_done++; + if (rxq->rx_curr_desc == rxq->ring_size) + rxq->rx_curr_desc = 0; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + rcu_read_lock(); + ret = ff_receive(priv, + rxq, + idx, + frag, + priv->frag_size, + RX_OFFSET, + pkt_len); + rcu_read_unlock(); + if (ret) { + rcvd_pkts++; + rcvd_bytes += pkt_len; + continue; + } +#endif + +#ifdef DBG_RX_DISCARD_ALL + /* re-arm with old buffer */ + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (priv->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + rcvd_pkts++; + rcvd_bytes += pkt_len; + continue; +#endif + + ret = rxq_refill_desc(priv, rxq, idx, true, NULL); + if (ret) { + netdev_err(priv->netdev, "oom while refill\n"); + stats->rx_packets++; + stats->rx_dropped++; + + /* re-arm with old buffer */ + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (priv->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + continue; + } + + /* descriptor is re-armed now */ + skb = build_skb(frag, + priv->frag_size > PAGE_SIZE ? + 0 : priv->frag_size); + if (!skb) { + skb_free_frag(frag); + stats->rx_dropped++; + continue; + } + + skb_reserve(skb, RX_OFFSET); + skb_put(skb, pkt_len); + + rcvd_pkts++; + rcvd_bytes += pkt_len; + skb->protocol = eth_type_trans(skb, priv->netdev); + netif_receive_skb(skb); + } + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_unlock_this_cpu(); +#endif + + if (rcvd_pkts) { + stats->rx_packets += rcvd_pkts; + stats->rx_bytes += rcvd_bytes; + } + + return rx_done; +} + +/* + * try to or force reclaim of transmitted buffers + */ +static int __bcm_runner_tx_reclaim_one(struct bcm_enet_runner_priv *priv, + struct net_device *dev, + struct tx_queue *txq, + int force) +{ + struct tx_desc *desc; + void *pdata_ptr; + dma_addr_t address; + u32 flags_len; + unsigned int dirty_desc; + unsigned int pdata_len; + + if (txq->tx_dirty_desc == txq->tx_cur_desc) { + txdbg("bcm_runner_tx_reclaim[q%d]: reach end of desc to reclaim\n", + txq->index); + return 0; + } + + dirty_desc = txq->tx_dirty_desc; + desc = &txq->tx_desc_area[dirty_desc]; + flags_len = be32_to_cpu(desc->flags_len); + + if (!force && (flags_len & CPU_TX_DESC0_HW_OWNED_MASK)) { + txdbg("bcm_runner_tx_reclaim[q%d]: tx desc %u owned by hw\n", + txq->index, dirty_desc); + return 0; + } + + /* ensure other field of the descriptor were not read before + * we checked ownership */ + rmb(); + + pdata_ptr = txq->tx_desc_pdata[dirty_desc].data; + pdata_len = txq->tx_desc_pdata[dirty_desc].len; + txq->tx_desc_pdata[dirty_desc].data = NULL; + + txdbg("tx_reclaim[q%u]: dirty_desc:%u skb:%pS => free\n", + txq->index, dirty_desc, pdata_ptr); + + address = be32_to_cpu(desc->address); + + dirty_desc++; + if (unlikely(dirty_desc >= txq->ring_size)) + dirty_desc = 0; + + txq->tx_dirty_desc = dirty_desc; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (txq == priv->ff_txq) + skb_free_frag(pdata_ptr); + else +#endif + { + dma_unmap_single(dev->dev.parent, + address, pdata_len, + DMA_TO_DEVICE); + dev_kfree_skb((struct sk_buff *)pdata_ptr); + } + return 1; +} + +/* + * try to or force reclaim of transmitted buffers + */ +static int bcm_runner_tx_reclaim(struct bcm_enet_runner_priv *priv, + struct net_device *dev, + struct tx_queue *txq, + int budget, + int force) +{ + struct netdev_queue *netdev_txq; + unsigned int cur_desc, next_desc; + int released; + + txdbg("bcm_runner_tx_reclaim[q%d]: budget:%u\n", txq->index, budget); + + released = 0; + while (released < budget) { + int done; + + /* We run in a bh and fight against start_xmit, which + * is called with bh disabled */ + spin_lock(&txq->tx_lock); + done = __bcm_runner_tx_reclaim_one(priv, dev, txq, force); + spin_unlock(&txq->tx_lock); + if (!done) + break; + + released++; + } + + if (force || !released) + goto end; + + netdev_txq = netdev_get_tx_queue(dev, txq->index); + if (!netif_tx_queue_stopped(netdev_txq)) + goto end; + + /* recheck in case xmit already filled all available space */ + spin_lock(&txq->tx_lock); + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + if (next_desc != txq->tx_dirty_desc) + netif_tx_wake_queue(netdev_txq); + spin_unlock(&txq->tx_lock); + +end: + return released; +} + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +static int ff_reclaim_threadfn(void *data) +{ + struct bcm_enet_runner_priv *priv = data; + + set_user_nice(current, MAX_NICE); + + while (!kthread_should_stop()) { + while (!kthread_should_stop()) { + int done = 0; + + if (spin_trylock_bh(&priv->ff_txq->tx_lock)) { + done = __bcm_runner_tx_reclaim_one( + priv, + priv->netdev, + priv->ff_txq, + 0); + spin_unlock_bh(&priv->ff_txq->tx_lock); + } + + if (!done) + break; + schedule(); + } + msleep(10); + } + + return 0; +} +#endif + +/* + * this is called with interrupts disabled, and all CPUs beside the + * current one are also blocked in a loop with interrupt disable + */ +static int bcm_enet_runner_dgasp_handler(struct notifier_block *nb, + unsigned long action, void *data) +{ + const struct bcm_xrdp_enet_params *params; + struct bcm_enet_runner_priv *priv; + struct tx_queue *txq; + struct ethhdr *eth; + unsigned int cur_desc, next_desc; + struct tx_desc *tx_desc; + dma_addr_t address; + u32 flags_len; + u8 *buf; + int dlen; + + priv = container_of(nb, struct bcm_enet_runner_priv, dgasp_nb); + if (!netif_carrier_ok(priv->netdev)) + return 0; + + buf = kmalloc(priv->pkt_size, GFP_ATOMIC); + if (!buf) { + printk("failed to alloc dgasp data\n"); + return 0; + } + + dlen = priv->mode_ops->dgasp_gen_data(priv->mode_priv, + buf, priv->pkt_size); + if (dlen < 0) { + printk("failed to gen dgasp data\n"); + kfree(buf); + return 0; + } + + eth = (struct ethhdr *)buf; + + if (unlikely((priv->mode_ops->can_send && + !priv->mode_ops->can_send(priv->mode_priv, + ntohs(eth->h_proto))))) { + kfree(buf); + return 0; + } + + params = &priv->xrdp_params; + txq = &priv->txq[0]; + + /* pad small packets */ + if (dlen < 60) { + memset(buf + dlen, 0, 60 - dlen); + dlen = 60; + } + + /* map buffer */ + address = dma_map_single(priv->netdev->dev.parent, + buf, + dlen, + DMA_TO_DEVICE); + + if (unlikely(dma_mapping_error(priv->netdev->dev.parent, address))) { + printk("dma_map_single failed\n"); + kfree(buf); + return 0; + } + + /* make sure we have room */ + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (next_desc >= txq->ring_size) + next_desc = 0; + + if (next_desc == txq->tx_dirty_desc) { + /* queue is full, poll until the dirty desc is sent */ + tx_desc = &txq->tx_desc_area[txq->tx_dirty_desc]; + while (1) { + flags_len = be32_to_cpu(tx_desc->flags_len); + if (!(flags_len & CPU_TX_DESC0_HW_OWNED_MASK)) + break; + } + } + + /* update descriptor index */ + flags_len = CPU_TX_DESC0_HW_OWNED_MASK | + (dlen << CPU_TX_DESC0_LEN_SHIFT); + + tx_desc = &txq->tx_desc_area[cur_desc]; + tx_desc->address = cpu_to_be32(address); + wmb(); + tx_desc->flags_len = cpu_to_be32(flags_len); + + /* kick tx dma */ + bcm_xrdp_api_wakeup(priv->xrdp, + params->tx_core_id, + params->txq_wakeup_thread[0]); + + return 0; +} + +/* + * + */ +static u32 collect_work(struct bcm_enet_runner_priv *priv) +{ + const struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 val; + + val = bcm_xrdp_api_irq_read_status(priv->xrdp, params->rx_core_id); + val &= priv->irq_mask; + if (val) { + /* ack */ + bcm_xrdp_api_irq_write_status(priv->xrdp, params->rx_core_id, + val); + (void)bcm_xrdp_api_irq_read_status(priv->xrdp, + params->rx_core_id); + } + return val; +} + +/* + * + */ +int bcm_runner_poll(struct napi_struct *napi, int budget) +{ + struct bcm_enet_runner_priv *priv; + struct net_device *dev; + struct bcm_xrdp_enet_params *params; + int work_done; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff.jiffies = nfct_time_stamp; +#endif + + priv = container_of(napi, struct bcm_enet_runner_priv, napi); + params = &priv->xrdp_params; + dev = priv->netdev; + + work_done = 0; + + txdbg("bcm_runner_poll: enter budget:%d work_todo:%08x work_batch:%08x\n", + budget, priv->work_todo, priv->work_batch); + + while (work_done < budget) { + int small_budget, done, i; + + /* collect work todo */ + if (!priv->work_batch) { + if (!priv->work_todo) { + priv->work_todo = collect_work(priv); + txdbg("bcm_runner_poll: colloect work_todo:%08x\n", + priv->work_todo); + if (!priv->work_todo) + break; + } + + priv->work_batch = priv->work_todo; + } + + txdbg("bcm_runner_poll: loop work_todo:%08x work_batch:%08x\n", + priv->work_todo, priv->work_batch); + + small_budget = budget - work_done; + if (small_budget > 16) + small_budget = 16; + + for (i = 0; i < dev->real_num_tx_queues; i++) { + if (!(priv->work_batch & params->tx_done_irq_mask[i])) + continue; + + txdbg("bcm_runner_poll: tx done work for queue %u\n", i); + priv->work_batch &= ~params->tx_done_irq_mask[i]; + + /* reclaim sent skb */ + done = bcm_runner_tx_reclaim(priv, dev, + &priv->txq[i], + small_budget, 0); + + txdbg("bcm_runner_poll: tx reclaim done => %u\n", done); + /* if we reclaimed everything, clear the work bit */ + if (done < small_budget) + priv->work_todo &= ~params->tx_done_irq_mask[i]; + small_budget -= done; + work_done += done; + } + + if (!small_budget) + continue; + + for (i = 0; i < dev->real_num_rx_queues; i++) { + if (!(priv->work_batch & params->rx_irq_mask[i])) + continue; + + txdbg("bcm_runner_poll: rx done work for queue %u\n", i); + priv->work_batch &= ~params->rx_irq_mask[i]; + + /* do rx */ + done = bcm_runner_do_rx(priv, &priv->rxq[i], + small_budget); + + /* if we reclaimed everything, clear the work bit */ + if (done < small_budget) + priv->work_todo &= ~params->rx_irq_mask[i]; + + small_budget -= done; + work_done += done; + } + } + + if (work_done < budget && !priv->work_todo) { + txdbg("bcm_runner_poll: all work done\n"); + + /* no more packet in rx/tx queue, remove device from + * poll queue */ + napi_complete_done(napi, work_done); + + /* restore rx/tx interrupt */ + bcm_xrdp_api_irq_mask_set(priv->xrdp, + params->rx_core_id, priv->irq_mask); + } + + return work_done; +} + +/* + * + */ +static void txq_deinit(struct bcm_enet_runner_priv *priv, struct tx_queue *txq) +{ + unsigned int i; + + for (i = 0; i < txq->ring_size; i++) { + struct tx_desc *desc; + dma_addr_t addr; + void *pdata_ptr; + unsigned int pdata_len; + + if (!txq->tx_desc_pdata) + continue; + + pdata_ptr = txq->tx_desc_pdata[i].data; + if (!pdata_ptr) + continue; + + pdata_len = txq->tx_desc_pdata[i].len; + desc = &txq->tx_desc_area[i]; + addr = be32_to_cpu(desc->address); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (txq == priv->ff_txq) + skb_free_frag(pdata_ptr); + else +#endif + { + dma_unmap_single(priv->netdev->dev.parent, + addr, pdata_len, + DMA_TO_DEVICE); + dev_kfree_skb((struct sk_buff *)pdata_ptr); + } + + } + + if (txq->tx_desc_area) + dma_free_coherent(priv->netdev->dev.parent, + txq->tx_desc_area_size, + txq->tx_desc_area, + txq->tx_desc_dma); + if (txq->tx_desc_pdata) + kfree(txq->tx_desc_pdata); +} + +/* + * + */ +static int txq_init(struct bcm_enet_runner_priv *priv, int index) +{ + struct tx_queue *txq = priv->txq + index; + int size; + + memset(txq, 0, sizeof (*txq)); + spin_lock_init(&txq->tx_lock); + txq->index = index; + txq->ring_size = priv->txq_size; + + size = txq->ring_size * sizeof (struct tx_desc); + txq->tx_desc_area_size = size; + txq->tx_desc_area = dma_alloc_coherent(priv->netdev->dev.parent, + size, &txq->tx_desc_dma, + GFP_KERNEL); + + if (txq->tx_desc_area == NULL) { + netdev_err(priv->netdev, + "can't allocate tx ring (%d bytes)\n", size); + goto out; + } + + memset(txq->tx_desc_area, 0, size); + + txq->tx_desc_pdata = kzalloc(sizeof (*txq->tx_desc_pdata) * + txq->ring_size, GFP_KERNEL); + if (!txq->tx_desc_pdata) { + netdev_err(priv->netdev, "can't allocate tx skbs ring\n"); + goto out; + } + + return 0; + +out: + txq_deinit(priv, txq); + return -ENOMEM; +} + +/* + * + */ +static u16 bcm_runner_select_queue(struct net_device *dev, struct sk_buff *skb, + struct net_device *sb_dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + u16 queue = skb_get_queue_mapping(skb); + u8 index; + + if (!netdev_uses_dsa(dev)) + return netdev_pick_tx(dev, skb, NULL); + + /* DSA tagging layer will have configured the correct queue */ + index = priv->txq_port_map[BRCM_TAG_GET_PORT(queue)]; + + if (unlikely(index >= priv->txq_count)) + return netdev_pick_tx(dev, skb, NULL); + + return index; +} + +/* + * + */ +static int bcm_runner_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + struct tx_queue *txq; + struct netdev_queue *netdev_txq; + struct tx_desc *desc; + unsigned int cur_desc, next_desc; + dma_addr_t address; + u32 flags_len; + u16 queue; + + if (unlikely((priv->mode_ops->can_send && + !priv->mode_ops->can_send(priv->mode_priv, + ntohs(skb->protocol))))) { + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } + + queue = skb_get_queue_mapping(skb); + netdev_txq = netdev_get_tx_queue(dev, queue); + txq = &priv->txq[queue]; + + if (params->tx_need_batch) + sk_pacing_shift_update(skb->sk, 6); + + /* pad small packets */ + if (skb->len < 60) { + int needed = 60 - skb->len; + char *data; + + if (unlikely(skb_tailroom(skb) < needed)) { + struct sk_buff *nskb; + + nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC); + if (!nskb) + return NETDEV_TX_BUSY; + + dev_kfree_skb(skb); + skb = nskb; + } + data = skb_put_zero(skb, needed); + } + + /* map buffer */ + address = dma_map_single(dev->dev.parent, + skb->data, + skb->len, + DMA_TO_DEVICE); + + if (unlikely(dma_mapping_error(dev->dev.parent, address))) { + netdev_err(dev, "dma_map_single failed\n"); + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } + + /* lock against tx reclaim */ + spin_lock(&txq->tx_lock); + + /* make sure we have room */ + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + txdbg("runnerxmit[q%u]: cur_desc:%u skb:%pS len:%u\n", + txq->index, + cur_desc, skb, skb->len); + + if (unlikely(next_desc == txq->tx_dirty_desc)) { + /* queue was full */ + netif_tx_stop_queue(netdev_txq); + spin_unlock(&txq->tx_lock); + + netdev_err(dev, "tx queue full unexpected\n"); + dma_unmap_single(dev->dev.parent, + address, + skb->len, + DMA_TO_DEVICE); + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } + + /* point to the next available desc */ + desc = &txq->tx_desc_area[cur_desc]; + txq->tx_desc_pdata[cur_desc].data = skb; + txq->tx_desc_pdata[cur_desc].len = skb->len; + + /* update descriptor index */ + cur_desc = next_desc; + txq->tx_cur_desc = cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + /* check if queue is now full */ + if (unlikely(next_desc == txq->tx_dirty_desc)) { + txdbg("runnerxmit[q%u]: queue now full (dirty_desc %u)\n", + txq->index, + txq->tx_dirty_desc); + netif_tx_stop_queue(netdev_txq); + } + + /* fill current descriptor */ + flags_len = CPU_TX_DESC0_HW_OWNED_MASK | + (skb->len << CPU_TX_DESC0_LEN_SHIFT); + + desc->address = cpu_to_be32(address); + wmb(); + desc->flags_len = cpu_to_be32(flags_len); + wmb(); + + spin_unlock(&txq->tx_lock); + + /* kick tx dma */ + bcm_xrdp_api_wakeup(priv->xrdp, + params->tx_core_id, + params->txq_wakeup_thread[0]); + + dev->stats.tx_bytes += skb->len; + dev->stats.tx_packets++; + return NETDEV_TX_OK; +} + +/* + * + */ +static irqreturn_t bcm_enet_runner_isr(int irq, void *dev_id) +{ + struct bcm_enet_runner_priv *priv = (struct bcm_enet_runner_priv *)dev_id; + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 val; + + /* check if interrupt is for us */ + val = bcm_xrdp_api_irq_read_status(priv->xrdp, + params->rx_core_id); + txdbg("bcm_enet_runner_isr: val:%08x\n", val); + val &= priv->irq_mask; + if (!val) + return IRQ_NONE; + + /* mask irq */ + bcm_xrdp_api_irq_mask_clear(priv->xrdp, + params->rx_core_id, priv->irq_mask); + napi_schedule(&priv->napi); + return IRQ_HANDLED; +} + +/* + * called when irq affinity is changed from userspace, so we can save + * it and reapply later + */ +static void +bcm_enet_runner_irq_affinity_notify(struct irq_affinity_notify *notify, + const cpumask_t *mask) +{ + struct queue_info *txq_info = + container_of(notify, struct queue_info, affinity_notifier); + cpumask_copy(&txq_info->irq_affinity_mask, mask); +} + +/* + * release callback for irq affinity notifier + */ +static void +bcm_enet_runner_irq_affinity_release(struct kref *ref) +{ +} + +/* + * + */ +static int bcm_runner_mode_start(struct bcm_enet_runner_priv *priv, + phy_interface_t interface) +{ + struct net_device *dev = priv->netdev; + const struct bcm_enet_mode_ops *mode_ops; + struct bcm_xrdp_enet_params params; + unsigned int txq_with_irq_count; + struct bcm_dsa_port *dp; + void *mode_priv; + int rxq_ready = 0, txq_ready = 0; + int rxq_irq_ready = 0, txq_irq_ready = 0; + int ret, i, first_queue, mode_idx; + u32 bbh_id, val; + + /* + * select the correct mode for the given interface + */ + mode_idx = priv->port_ops->mode_select(interface); + if (WARN_ON(mode_idx < 0)) { + /* should not happen since the interface was + * validated in phylink_validate() */ + return -ENOTSUPP; + } + + if (WARN_ON((unsigned)mode_idx >= priv->port_ops->mode_count)) + return -EINVAL; + + mode_ops = priv->port_ops->modes[mode_idx]; + if (priv->port_ops->mode_count > 1) + netdev_info(dev, "switching to mode %s\n", + mode_ops->name); + + bbh_id = mode_ops->get_bbh_id(priv->port_priv); + ret = bcm_xrdp_api_get_enet_params(priv->xrdp, bbh_id, ¶ms); + if (ret < 0) { + netdev_err(dev, + "failed to get rdp params for bbh %u\n", bbh_id); + return ret; + } + + /* sanity check on parameters */ + if (WARN_ON(params.rx_queue_count > ARRAY_SIZE(priv->rxq))) + return -EINVAL; + + if (WARN_ON(params.tx_queue_count > ARRAY_SIZE(priv->txq))) + return -EINVAL; + + /* do actual mode init */ + mode_priv = mode_ops->init(priv->port_priv, ¶ms); + if (IS_ERR(mode_priv)) { + netdev_err(dev, "failed to switch mode: %ld\n", + PTR_ERR(mode_priv)); + return PTR_ERR(mode_priv); + } + + mode_ops->mtu_set(mode_priv, priv->pkt_size); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + switch (priv->port_type) { + case BCM_RUNNER_PORT_UNIMAC: + priv->ff_hw_id = FF_HWDEV_ID_UNIMAC0 + bbh_id; + break; + case BCM_RUNNER_PORT_XPORT: + priv->ff_hw_id = FF_HWDEV_ID_FTTH; + break; + default: + WARN(1, "unknown port type"); + return -EINVAL; + } +#endif + + /* cap rxq & txq count to the hardware capabilities */ + ret = netif_set_real_num_rx_queues(dev, params.rx_queue_count); + if (ret) + goto out; + + priv->txq_count = params.tx_queue_count; + txq_with_irq_count = priv->txq_count; +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + txq_with_irq_count--; + if (WARN_ON(!txq_with_irq_count)) + goto out; +#endif + + ret = netif_set_real_num_tx_queues(dev, txq_with_irq_count); + if (ret) + goto out; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + priv->ff_reclaim_thread = kthread_create(ff_reclaim_threadfn, + priv, "ff_reclaim_%s", + dev->name); + if (IS_ERR(priv->ff_reclaim_thread)) { + ret = PTR_ERR(priv->ff_reclaim_thread); + priv->ff_reclaim_thread = NULL; + goto out; + } +#endif + + /* allocate rx rings */ + for (i = 0; i < dev->real_num_rx_queues; i++) { + ret = rxq_init(priv, i); + if (ret) + goto out; + rxq_ready++; + } + + /* allocate tx rings */ + for (i = 0; i < priv->txq_count; i++) { + ret = txq_init(priv, i); + if (ret) + goto out; + txq_ready++; + } + + /* + * configure txq DSA port queue mapping + * + * for now, use 1 queue per port + */ + i = 0; + list_for_each_entry(dp, &priv->dsa_ports, next) { + struct tx_queue *txq; + + if (i == dev->real_num_tx_queues) { + netdev_warn(dev, "too many DSA ports " + "vs tx queue, ACB flow control " + "will not work correctly\n"); + break; + } + + txq = &priv->txq[i]; + txq->use_dsa = true; + txq->dsa_port = dp->port; + txq->dsa_imp_port = dp->imp_port; + txq->dsa_queue = 0; + netif_set_real_num_tx_queues(dp->slave_netdev, 1); + priv->txq_port_map[dp->port] = i; + i++; + } + + /* assign same dsa data to remaining queues, but the kernel + * should not use them */ + first_queue = i; + if (first_queue) { + struct tx_queue *prev_txq = &priv->txq[first_queue - 1]; + + for (i = first_queue; i < priv->txq_count; i++) { + struct tx_queue *txq = &priv->txq[i]; + txq->use_dsa = prev_txq->use_dsa; + txq->dsa_port = prev_txq->dsa_port; + txq->dsa_imp_port = prev_txq->dsa_imp_port; + txq->dsa_queue = prev_txq->dsa_queue; + } + } + + /* interrupt clear */ + priv->irq_mask = 0; + for (i = 0; i < dev->real_num_rx_queues; i++) + priv->irq_mask |= params.rx_irq_mask[i]; + for (i = 0; i < dev->real_num_tx_queues; i++) + priv->irq_mask |= params.tx_done_irq_mask[i]; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + priv->ff_txq = &priv->txq[priv->txq_count - 1]; +#endif + + bcm_xrdp_api_irq_write_status(priv->xrdp, + params.rx_core_id, priv->irq_mask); + + for (i = 0; i < dev->real_num_rx_queues; i++) { + struct queue_info *rxq_info = &priv->rxq_info[i]; + + scnprintf(rxq_info->irq_name, + sizeof (rxq_info->irq_name), + "%s-rx%u", + dev->name, i); + + ret = request_irq(params.rx_irq[i], + bcm_enet_runner_isr, + 0, rxq_info->irq_name, priv); + if (ret) { + netdev_err(dev, "request_irq failed\n"); + goto out; + } + + rxq_info->affinity_notifier.notify = + bcm_enet_runner_irq_affinity_notify; + rxq_info->affinity_notifier.release = + bcm_enet_runner_irq_affinity_release; + irq_set_affinity_notifier(params.rx_irq[i], + &rxq_info->affinity_notifier); + irq_set_affinity_hint(params.rx_irq[i], + &rxq_info->irq_affinity_mask); + rxq_irq_ready++; + } + + for (i = 0; i < dev->real_num_tx_queues; i++) { + struct queue_info *txq_info = &priv->txq_info[i]; + + scnprintf(txq_info->irq_name, + sizeof (txq_info->irq_name), + "%s-tx%u", + dev->name, i); + + ret = request_irq(params.tx_irq[i], + bcm_enet_runner_isr, + 0, txq_info->irq_name, priv); + if (ret) { + netdev_err(dev, "request_irq failed\n"); + goto out; + } + + txq_info->affinity_notifier.notify = + bcm_enet_runner_irq_affinity_notify; + txq_info->affinity_notifier.release = + bcm_enet_runner_irq_affinity_release; + irq_set_affinity_notifier(params.tx_irq[i], + &txq_info->affinity_notifier); + irq_set_affinity_hint(params.tx_irq[i], + &txq_info->irq_affinity_mask); + txq_irq_ready++; + } + + /* all set, start rx/tx */ + memcpy(&priv->xrdp_params, ¶ms, sizeof (priv->xrdp_params)); + priv->mode_ops = mode_ops; + priv->mode_priv = mode_priv; + + /* setup firmware */ + for (i = 0; i < dev->real_num_rx_queues; i++) { + struct rx_queue *rxq = &priv->rxq[i]; + + /* assign rx queue pointers & size */ + fw_rx_reg_writel(priv, rxq->rx_desc_dma, RX_DESC_ADDRESS_REG); + fw_rx_reg_writel(priv, rxq->ring_size, RX_DESC_COUNT_REG); + fw_rx_reg_writel(priv, params.rx_irq_mask[i], + RX_IRQ_MASK_REG); + } + + /* setup TX */ + fw_tx_reg_writeb(priv, params.tx_bbh_bbid, + TX_BBH_BB_ID_REG); + fw_tx_reg_writeb(priv, params.tx_need_reporting, + TX_EPON_REPORTING_REG); + fw_tx_reg_writeh(priv, params.tx_bbh_pd_queue_size, + TX_BBH_PD_QUEUE_SIZE_REG); + fw_tx_reg_writeh(priv, params.tx_bbh_mdu_addr, + TX_BBH_MDU_QUEUE_ADDR_REG); + + for (i = 0; i < priv->txq_count; i++) { + struct tx_queue *txq = &priv->txq[i]; + u16 acb_control; + unsigned int imp_port_mapped; + + /* assign tx queue pointers & size */ + fw_tx_reg_writel(priv, txq->tx_desc_dma, + fw_txqoff(i, TXQ_OFF_DESC_ADDRESS_REG)); + fw_tx_reg_writel(priv, txq->ring_size, + fw_txqoff(i, TXQ_OFF_DESC_COUNT_REG)); + fw_tx_reg_writel(priv, params.tx_done_irq_mask[i], + fw_txqoff(i, TXQ_OFF_IRQ_MASK_REG)); + + + if (!txq->use_dsa) + continue; + + fw_tx_reg_writeb(priv, txq->use_dsa ? 1 : 0, + fw_txqoff(i, TXQ_OFF_ACB_ENABLED_REG)); + fw_tx_reg_writeb(priv, txq->dsa_port * 8 + txq->dsa_queue, + fw_txqoff(i, TXQ_OFF_ACB_QIDX_REG)); + + imp_port_mapped = enet_fw_imp_port_map(txq->dsa_imp_port); + acb_control = + (imp_port_mapped << TXQ_ACBCTRL_IMP_PORT_SHIFT) | + (txq->dsa_port << TXQ_ACBCTRL_EGRESS_PORT_SHIFT) | + (txq->dsa_queue << TXQ_ACBCTRL_EGRESS_QUEUE_SHIFT); + fw_tx_reg_writeh(priv, acb_control, + fw_txqoff(i, TXQ_OFF_ACB_CONTROL_REG)); + } + + /* unmask interrupt */ + bcm_xrdp_api_irq_mask_set(priv->xrdp, + params.rx_core_id, priv->irq_mask); + napi_enable(&priv->napi); + + /* start firmware RX operation */ + val = fw_rx_reg_readl(priv, RX_CONTROL_REG); + val |= RX_CONTROL_RX_EN_MASK; + fw_rx_reg_writel(priv, val, RX_CONTROL_REG); + + /* kick FQM */ + bcm_xrdp_api_wakeup(priv->xrdp, + params.rx_core_id, + params.rxq_fqm_wakeup_thread); + + /* start firmware TX operation */ + val = fw_tx_reg_readl(priv, TX_CONTROL_REG); + val |= TX_CONTROL_TX_EN_MASK; + fw_tx_reg_writel(priv, val, TX_CONTROL_REG); + + netif_tx_start_all_queues(dev); + + /* register dgasp notifier */ + if (priv->mode_ops->dgasp_supported) + dgasp_notifier_chain_register(&priv->dgasp_nb); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + /* ff can reference this while looking for opposite device */ + ff_lock_all_cpu_bh(); + WARN_ON(ff.ports_by_hw_id[priv->ff_hw_id] != NULL); + ff.ports_by_hw_id[priv->ff_hw_id] = priv; + ff_unlock_all_cpu_bh(); + + wake_up_process(priv->ff_reclaim_thread); + + /* + * this can be called from: + * 1) phylink major reconfig + * 2) netdevice ifup path + * 3) reset_link_path + * + * the netdevice may either be up or not at this point + */ + ff_notifier_event(priv->netdev, NETDEV_CHANGE); +#endif + return 0; + +out: +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (priv->ff_reclaim_thread) { + kthread_stop(priv->ff_reclaim_thread); + priv->ff_reclaim_thread = NULL; + } +#endif + for (i = 0; i < rxq_irq_ready; i++) { + irq_set_affinity_notifier(params.rx_irq[i], NULL); + irq_set_affinity_hint(params.rx_irq[i], NULL); + free_irq(params.rx_irq[i], priv); + } + for (i = 0; i < txq_irq_ready; i++) { + irq_set_affinity_notifier(params.tx_irq[i], NULL); + irq_set_affinity_hint(params.tx_irq[i], NULL); + free_irq(params.tx_irq[i], priv); + } + + for (i = 0; i < rxq_ready; i++) + rxq_deinit(priv, priv->rxq + i); + for (i = 0; i < txq_ready; i++) + txq_deinit(priv, priv->txq + i); + + mode_ops->release(mode_priv); + return ret; +} + +/* + * + */ +bool bcm_runner_fw_bbh_is_empty(struct bcm_enet_runner_priv *priv) +{ + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 bbh_id; + + bbh_id = priv->mode_ops->get_bbh_id(priv->port_priv); + return bcm_xrdp_api_bbh_txq_is_empty(priv->xrdp, + bbh_id, + params->tx_bbh_queue_id); +} + +/* + * + */ +void bcm_runner_fw_stop_tx(struct bcm_enet_runner_priv *priv) +{ + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 val; + + val = fw_tx_reg_readl(priv, TX_CONTROL_REG); + val &= ~TX_CONTROL_TX_EN_MASK; + fw_tx_reg_writel(priv, val, TX_CONTROL_REG); + + bcm_xrdp_api_wakeup(priv->xrdp, + params->tx_core_id, + params->txq_wakeup_thread[0]); +} + +/* + * + */ +bool bcm_runner_fw_tx_is_stopped(struct bcm_enet_runner_priv *priv) +{ + u32 val; + + val = fw_tx_reg_readl(priv, TX_STATUS_REG); + if ((val & TX_STATUS_TX_EN_MASK)) + return false; + return true; +} + +/* + * + */ +void bcm_runner_fw_tx_stop_wait(struct bcm_enet_runner_priv *priv) +{ + unsigned int i; + bool stopped; + + bcm_runner_fw_stop_tx(priv); + for (i = 0; i < 1000; i++) { + stopped = bcm_runner_fw_tx_is_stopped(priv); + if (stopped) + break; + usleep_range(1000, 2000); + } + + if (!stopped) + netdev_err(priv->netdev, "failed to stop TX DMA"); +} + +/* + * + */ +static void bcm_runner_mode_uninit(struct bcm_enet_runner_priv *priv) +{ + struct net_device *dev = priv->netdev; + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + unsigned int i, xfid; + u32 val; + + /* unregister from dgasp notifier */ + if (priv->mode_ops->dgasp_supported) + dgasp_notifier_chain_unregister(&priv->dgasp_nb); + + /* mask all interrupts */ + bcm_xrdp_api_irq_mask_clear(priv->xrdp, + params->rx_core_id, priv->irq_mask); + + /* prevent hardxmit from being called */ + netif_tx_disable(dev); + + /* prevent poll() from being called */ + napi_disable(&priv->napi); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (priv->ff_reclaim_thread) { + kthread_stop(priv->ff_reclaim_thread); + priv->ff_reclaim_thread = NULL; + } + + ff_lock_all_cpu_bh(); + ff.ports_by_hw_id[priv->ff_hw_id] = NULL; + ff_unlock_all_cpu_bh(); + + /* + * this can be called from: + * 1) phylink major reconfig + * 2) netdevice ifdown path + * 3) reset_link_path + * + * it may have already been sent when coming from 2), but + * there is no harm in doing it again + */ + ff_notifier_event(priv->netdev, NETDEV_GOING_DOWN); +#endif + + /* stop firmware RX operation & wait for RX enable status to + * clear */ + val = fw_rx_reg_readl(priv, RX_CONTROL_REG); + val &= ~RX_CONTROL_RX_EN_MASK; + fw_rx_reg_writel(priv, val, RX_CONTROL_REG); + + /* wait for all XF first */ + for (xfid = 0; xfid < ARRAY_SIZE(params->rxq_xf_wakeup_thread); + xfid++) { + bcm_xrdp_api_wakeup(priv->xrdp, + params->rx_core_id, + params->rxq_xf_wakeup_thread[xfid]); + + for (i = 0; i < 1000; i++) { + val = fw_rx_reg_readl(priv, + fw_rx_xf_off(xfid, RX_XF_STATUS_REG)); + if (!(val & RX_XF_STATUS_RX_EN_MASK)) + break; + + usleep_range(1000, 2000); + } + + if ((val & RX_XF_STATUS_RX_EN_MASK)) + netdev_err(dev, "failed to stop RX for xf %u", xfid); + } + + /* wait for FQM */ + bcm_xrdp_api_wakeup(priv->xrdp, + params->rx_core_id, + params->rxq_fqm_wakeup_thread); + + for (i = 0; i < 1000; i++) { + val = fw_rx_reg_readl(priv, RX_FQM_STATUS_REG); + if (!(val & RX_FQM_STATUS_RX_EN_MASK)) + break; + + usleep_range(1000, 2000); + } + + if ((val & RX_FQM_STATUS_RX_EN_MASK)) + netdev_err(dev, "failed to stop RX for FQM"); + + priv->mode_ops->stop(priv->mode_priv); + priv->mode_ops->release(priv->mode_priv); + priv->mode_ops = NULL; + priv->mode_priv = NULL; + + /* force reclaim of all tx buffers now that firmware does not + * use them */ + local_bh_disable(); + for (i = 0; i < priv->txq_count; i++) + bcm_runner_tx_reclaim(priv, dev, &priv->txq[i], INT_MAX, 1); + local_bh_enable(); + + for (i = 0; i < dev->real_num_rx_queues; i++) { + irq_set_affinity_notifier(params->rx_irq[i], NULL); + irq_set_affinity_hint(params->rx_irq[i], NULL); + free_irq(params->rx_irq[i], priv); + } + for (i = 0; i < dev->real_num_tx_queues; i++) { + irq_set_affinity_notifier(params->tx_irq[i], NULL); + irq_set_affinity_hint(params->tx_irq[i], NULL); + free_irq(params->tx_irq[i], priv); + } + + for (i = 0; i < dev->real_num_rx_queues; i++) + rxq_deinit(priv, priv->rxq + i); + for (i = 0; i < priv->txq_count; i++) + txq_deinit(priv, priv->txq + i); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + priv->ff_txq = NULL; +#endif + priv->reset_scheduled = false; +} + +/* + * Change the interface's mac address. + */ +static int bcm_runner_set_mac_address(struct net_device *dev, void *p) +{ + struct sockaddr *addr = p; + + if (netif_running(dev)) + return -EBUSY; + + dev_addr_mod(dev, 0, addr->sa_data, ETH_ALEN); + return 0; +} + +/* + * return device statistics + */ +static struct net_device_stats * +bcm_runner_get_stats(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv; + + if (!netif_running(dev)) + return &dev->stats; + + priv = netdev_priv(dev); + + /* update some error counters that are only visible in MIB */ + if (priv->mode_ops && priv->mode_ops->stats_update) + priv->mode_ops->stats_update(priv->mode_priv, &dev->stats); + + return &dev->stats; +} + +/* + * called by phylink before a major config, give us a chance to return + * an error if some initialization fails + */ +static int phylink_mac_prepare(struct phylink_config *config, + unsigned int pl_mode, + phy_interface_t interface) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + int ret; + + if (priv->mode_ops) + bcm_runner_mode_uninit(priv); + + ret = bcm_runner_mode_start(priv, interface); + if (ret) + return ret; + + return 0; +} + +/* + * + */ +static struct phylink_pcs *phylink_select_pcs(struct phylink_config *config, + phy_interface_t interface) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + return &priv->phylink_pcs; +} + +/* + * called by phylink to apply new pcs config, with rtnl held + * + * only called when netdevice is up + */ +static int phylink_pcs_config(struct phylink_pcs *pcs, + unsigned int mode, + phy_interface_t interface, + const unsigned long *advertising, + bool permit_pause_to_mac) +{ + struct bcm_enet_runner_priv *priv; + + priv = container_of(pcs, struct bcm_enet_runner_priv, phylink_pcs); + if (!priv->mode_ops || !priv->mode_ops->phylink_pcs_config) + return 0; + + return priv->mode_ops->phylink_pcs_config(priv->mode_priv, + mode, + interface, + advertising); +} + + +/* + * called by phylink to apply new pcs config, with rtnl held + * + * only called when netdevice is up + */ +static void phylink_mac_config(struct phylink_config *config, + unsigned int pl_mode, + const struct phylink_link_state *state) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + + if (!priv->mode_ops || !priv->mode_ops->phylink_mac_config) + return; + + priv->mode_ops->phylink_mac_config(priv->mode_priv, pl_mode, state); +} + +/* + * + */ +static void phylink_mac_link_up(struct phylink_config *config, + struct phy_device *phy, + unsigned int mode, + phy_interface_t interface, + int speed, int duplex, + bool tx_fc, bool rx_fc) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + + if (!priv->mode_ops) + return; + + priv->mode_ops->phylink_link_up(priv->mode_priv, mode, interface, + speed, duplex, phy); +} + +/* + * + */ +static void phylink_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + + if (!priv->mode_ops) + return; + + priv->mode_ops->phylink_link_down(priv->mode_priv, mode, interface); +} + +/* + * phylink callback, only for inband autoneg + */ +static void phylink_pcs_an_restart(struct phylink_pcs *pcs) +{ + struct bcm_enet_runner_priv *priv; + + priv = container_of(pcs, struct bcm_enet_runner_priv, phylink_pcs); + if (!priv->mode_ops) + return; + + if (priv->mode_ops->phylink_pcs_an_restart) + priv->mode_ops->phylink_pcs_an_restart(priv->mode_priv); +} + +/* + * phylink callback, only for inband autoneg + */ +static void phylink_pcs_get_state(struct phylink_pcs *pcs, + struct phylink_link_state *state) +{ + struct bcm_enet_runner_priv *priv; + + priv = container_of(pcs, struct bcm_enet_runner_priv, phylink_pcs); + if (!priv->mode_ops) + return; + + if (priv->mode_ops->phylink_pcs_get_state) + priv->mode_ops->phylink_pcs_get_state(priv->mode_priv, state); +} + +/* + * + */ +static void recalc_frag_size(struct bcm_enet_runner_priv *priv) +{ + /* + * Reserve 14 bytes for an ethernet header + 8 bytes for up + * to two VLAN tags + */ + priv->pkt_size = priv->netdev->mtu + ETH_HLEN + 4 * 2; + + /* + * add NET_SKB_PAD per build_skb() requirement, make sure we + * have room to align data to cache size after reserving + */ + priv->frag_size = priv->pkt_size + RX_OFFSET; + + /* + * per build_skb() requirement + */ + priv->frag_size = (SKB_DATA_ALIGN(priv->frag_size) + + SKB_DATA_ALIGN(sizeof (struct skb_shared_info))); +} + +/* + * netdevice open callback + */ +static int bcm_runner_open(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + /* not much to do here, we have to wait for phylink to device + * the interface type to decide which mode to use, only then + * we can initialize everything */ + recalc_frag_size(priv); + phylink_start(priv->phylink); + return 0; +} + +/* + * netdevice stop callback + */ +static int bcm_runner_stop(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + phylink_stop(priv->phylink); + + if (priv->mode_ops) + bcm_runner_mode_uninit(priv); + + if (priv->port_ops->pcs_shutdown) + priv->port_ops->pcs_shutdown(priv->port_priv); + + return 0; +} + +/* + * Change the interface's MTU + */ +static int bcm_runner_change_mtu(struct net_device *dev, + int new_mtu) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + bool running = netif_running(dev); + int ret = 0; + + if (running) { + ret = bcm_runner_stop(dev); + if (ret < 0) + return ret; + } + + dev->mtu = new_mtu; + + if (running) + ret = bcm_runner_open(priv->netdev); + + return ret; +} + +const struct phylink_mac_ops bcm_enet_runner_phylink_ops = { + .mac_prepare = phylink_mac_prepare, + .mac_config = phylink_mac_config, + .mac_link_up = phylink_mac_link_up, + .mac_link_down = phylink_mac_link_down, + .mac_select_pcs = phylink_select_pcs, +}; + +const struct phylink_pcs_ops bcm_enet_runner_phylink_pcs_ops = { + .pcs_get_state = phylink_pcs_get_state, + .pcs_an_restart = phylink_pcs_an_restart, + .pcs_config = phylink_pcs_config, +}; + +const struct net_device_ops bcm_runner_ops = { + .ndo_open = bcm_runner_open, + .ndo_stop = bcm_runner_stop, + .ndo_start_xmit = bcm_runner_start_xmit, + .ndo_set_mac_address = bcm_runner_set_mac_address, + .ndo_get_stats = bcm_runner_get_stats, + .ndo_change_mtu = bcm_runner_change_mtu, + .ndo_select_queue = bcm_runner_select_queue, +}; + +/* + * + */ +static void reset_link_work(struct work_struct *w) +{ + struct delayed_work *dwork = to_delayed_work(w); + struct bcm_enet_runner_priv *priv; + + priv = container_of(dwork, struct bcm_enet_runner_priv, + reset_link_work); + + rtnl_lock(); + if (!priv->reset_scheduled || !netif_running(priv->netdev)) { + rtnl_unlock(); + return; + } + + priv->reset_scheduled = false; + netdev_info(priv->netdev, "resetting link\n"); + bcm_runner_stop(priv->netdev); + if (bcm_runner_open(priv->netdev)) + netdev_err(priv->netdev, "failed to reset link\n"); + rtnl_unlock(); +} + +/* + * + */ +void bcm_enet_runner_schedule_reset(struct bcm_enet_runner_priv *priv, + unsigned int delay_ms) +{ + priv->reset_scheduled = true; + schedule_delayed_work(&priv->reset_link_work, + msecs_to_jiffies(delay_ms)); +} + +/* + * + */ +void bcm_enet_runner_unschedule_reset(struct bcm_enet_runner_priv *priv) +{ + priv->reset_scheduled = false; +} + +/* + * runner mib + */ +#define GEN_RUNNER_RX_STAT(reg) 4, 0, reg, 1 +#define GEN_RUNNER_RX_XF_STAT(xfid, reg) \ + GEN_RUNNER_RX_STAT(RX_IF_REGS_BASE_OFF + xfid * RX_IF_REGS_PERIF_SIZE + reg) + +#define GEN_RUNNER_TX_STAT(reg) 4, 0, reg, 2 +#define GEN_RUNNER_TXQ_STAT(q, reg) \ + GEN_RUNNER_TX_STAT(TXQ_REGS_BASE_OFF + (q) * TXQ_REGS_PERQ_SIZE + reg) + +#define GEN_RUNNER_RX_STAT16(reg) 2, 0, reg, 1 +#define GEN_RUNNER_RX_XF_STAT16(xfid, reg) \ + GEN_RUNNER_RX_STAT16(RX_IF_REGS_BASE_OFF + xfid * RX_IF_REGS_PERIF_SIZE + reg) + +#define GEN_RUNNER_TX_STAT16(reg) 2, 0, reg, 2 +#define GEN_RUNNER_TXQ_STAT16(q, reg) \ + GEN_RUNNER_TX_STAT16(TXQ_REGS_BASE_OFF + (q) * TXQ_REGS_PERQ_SIZE + reg) + +#define GEN_RUNNER_RX_STAT8(reg) 1, 0, reg, 1 +#define GEN_RUNNER_RX_XF_STAT8(xfid, reg) \ + GEN_RUNNER_RX_STAT8(RX_IF_REGS_BASE_OFF + xfid * RX_IF_REGS_PERIF_SIZE + reg) + +#define GEN_RUNNER_TX_STAT8(reg) 1, 0, reg, 2 +#define GEN_RUNNER_TXQ_STAT8(q, reg) \ + GEN_RUNNER_TX_STAT8(TXQ_REGS_BASE_OFF + (q) * TXQ_REGS_PERQ_SIZE + reg) + +const struct bcm_runner_ethtool_stat bcm_runner_fw_estat[] = { + { "rnr_rx_control", GEN_RUNNER_RX_STAT(RX_CONTROL_REG) }, + { "rnr_rx_desc_addr", GEN_RUNNER_RX_STAT(RX_DESC_ADDRESS_REG) }, + { "rnr_rx_desc_size", GEN_RUNNER_RX_STAT(RX_DESC_COUNT_REG) }, + { "rnr_rx_irq_mask", GEN_RUNNER_RX_STAT(RX_IRQ_MASK_REG) }, + + { "rnr_rx_fqm_status", GEN_RUNNER_RX_STAT(RX_FQM_STATUS_REG) }, + { "rnr_rx_fqm_dbg_task_call", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_fqm_dbg_cpu_ring_idx", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_CPU_RING_IDX_REG) }, + { "rnr_rx_fqm_dbg_full", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_FULL_REG) }, + { "rnr_rx_fqm_dbg_host_nobuf", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_HOST_NOBUF_REG) }, + { "rnr_rx_fqm_head_idx", GEN_RUNNER_RX_STAT8(RX_FQM_HEAD_IDX_REG) }, + { "rnr_rx_fqm_tail_idx", GEN_RUNNER_RX_STAT8(RX_FQM_TAIL_IDX_REG) }, + + { "rnr_rx_xf0_status", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STATUS_REG) }, + { "rnr_rx_xf0_cnt_pkt_count", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_PKT_REG) }, + { "rnr_rx_xf0_cnt_drop_nobuf", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_DROP_NOBUF_REG) }, + { "rnr_rx_xf0_cnt_drop_rxdis", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_DROP_RXDIS_REG) }, + { "rnr_rx_xf0_cnt_drop_rxerr", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_DROP_RXERR_REG) }, + { "rnr_rx_xf0_dbg_task_call", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_xf0_dbg_last_pd0", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD0_REG) }, + { "rnr_rx_xf0_dbg_last_pd1", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD1_REG) }, + { "rnr_rx_xf0_dbg_last_pd2", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD2_REG) }, + { "rnr_rx_xf0_dbg_last_pd3", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD3_REG) }, + { "rnr_rx_xf0_dbg_last_sn", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_SN_REG) }, + { "rnr_rx_xf0_dbg_last_bn", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_BN_REG) }, + { "rnr_rx_xf0_dbg_last_plen", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PLEN_REG) }, + { "rnr_rx_xf0_dbg_last_cpudesc_idx", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG) }, + { "rnr_rx_xf0_dbg_cnt_invalid_pd", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_INVALID_PD_CNT_REG) }, + + { "rnr_rx_xf1_status", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STATUS_REG) }, + { "rnr_rx_xf1_cnt_pkt_count", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_PKT_REG) }, + { "rnr_rx_xf1_cnt_drop_nobuf", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_DROP_NOBUF_REG) }, + { "rnr_rx_xf1_cnt_drop_rxdis", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_DROP_RXDIS_REG) }, + { "rnr_rx_xf1_cnt_drop_rxerr", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_DROP_RXERR_REG) }, + { "rnr_rx_xf1_dbg_task_call", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_xf1_dbg_last_pd0", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD0_REG) }, + { "rnr_rx_xf1_dbg_last_pd1", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD1_REG) }, + { "rnr_rx_xf1_dbg_last_pd2", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD2_REG) }, + { "rnr_rx_xf1_dbg_last_pd3", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD3_REG) }, + { "rnr_rx_xf1_dbg_last_sn", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_SN_REG) }, + { "rnr_rx_xf1_dbg_last_bn", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_BN_REG) }, + { "rnr_rx_xf1_dbg_last_plen", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PLEN_REG) }, + { "rnr_rx_xf1_dbg_last_cpudesc_idx", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG) }, + { "rnr_rx_xf1_dbg_cnt_invalid_pd", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_INVALID_PD_CNT_REG) }, + + { "rnr_rx_xf2_status", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STATUS_REG) }, + { "rnr_rx_xf2_cnt_pkt_count", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_PKT_REG) }, + { "rnr_rx_xf2_cnt_drop_nobuf", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_DROP_NOBUF_REG) }, + { "rnr_rx_xf2_cnt_drop_rxdis", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_DROP_RXDIS_REG) }, + { "rnr_rx_xf2_cnt_drop_rxerr", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_DROP_RXERR_REG) }, + { "rnr_rx_xf2_dbg_task_call", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_xf2_dbg_last_pd0", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD0_REG) }, + { "rnr_rx_xf2_dbg_last_pd1", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD1_REG) }, + { "rnr_rx_xf2_dbg_last_pd2", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD2_REG) }, + { "rnr_rx_xf2_dbg_last_pd3", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD3_REG) }, + { "rnr_rx_xf2_dbg_last_sn", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_SN_REG) }, + { "rnr_rx_xf2_dbg_last_bn", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_BN_REG) }, + { "rnr_rx_xf2_dbg_last_plen", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PLEN_REG) }, + { "rnr_rx_xf2_dbg_last_cpudesc_idx", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG) }, + { "rnr_rx_xf2_dbg_cnt_invalid_pd", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_INVALID_PD_CNT_REG) }, + + { "rnr_tx_status", GEN_RUNNER_TX_STAT(TX_STATUS_REG) }, + { "rnr_tx_control", GEN_RUNNER_TX_STAT(TX_CONTROL_REG) }, + { "rnr_tx_bbh_id", GEN_RUNNER_TX_STAT(TX_BBH_BB_ID_REG) }, + { "rnr_tx_pd_queue_size", GEN_RUNNER_TX_STAT(TX_BBH_PD_QUEUE_SIZE_REG) }, + { "rnr_tx_cnt_drop_txdis", GEN_RUNNER_TX_STAT(TX_STAT_CNT_TX_DISABLED_REG) }, + { "rnr_tx_dbg_task_call", GEN_RUNNER_TX_STAT(TX_STAT_DBG_TASK_CALL_REG) }, + { "rnr_tx_dbg_hw_fifo_full", GEN_RUNNER_TX_STAT(TX_STAT_DBG_FIFO_FULL_REG) }, + { "rnr_tx_dbg_mdu_reclaim_idx", GEN_RUNNER_TX_STAT(TX_STAT_DBG_MDU_FW_RECLAIM_IDX_REG) }, + { "rnr_tx_dbg_mdu_push_idx", GEN_RUNNER_TX_STAT(TX_STAT_DBG_MDU_FW_PUSH_IDX_REG) }, + + { "rnr_txq0_desc_addr", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_DESC_ADDRESS_REG) }, + { "rnr_txq0_desc_count", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_DESC_COUNT_REG) }, + { "rnr_txq0_irq_mask", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_IRQ_MASK_REG) }, + { "rnr_txq0_tx_idx", GEN_RUNNER_TXQ_STAT8(0, TXQ_OFF_TX_DESC_IDX) }, + { "rnr_txq0_tx_cnt", GEN_RUNNER_TXQ_STAT8(0, TXQ_OFF_TX_DESC_CNT) }, + { "rnr_txq0_cnt_pkt", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_STAT_CNT_PKT_SENT_REG) }, + { "rnr_txq0_cnt_reclaimed", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_STAT_CNT_PKT_RECLAIMED_REG) }, + { "rnr_txq0_ring_push_idx", GEN_RUNNER_TXQ_STAT16(0, TXQ_OFF_RING_PUSH_IDX_REG) }, + { "rnr_txq0_ring_reclaim_idx", GEN_RUNNER_TXQ_STAT16(0, TXQ_OFF_RING_RECLAIM_IDX_REG) }, + { "rnr_txq0_acb_qfull", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_STAT_CNT_ACB_QFULL) }, + + { "rnr_txq1_desc_addr", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_DESC_ADDRESS_REG) }, + { "rnr_txq1_desc_count", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_DESC_COUNT_REG) }, + { "rnr_txq1_irq_mask", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_IRQ_MASK_REG) }, + { "rnr_txq1_tx_idx", GEN_RUNNER_TXQ_STAT8(1, TXQ_OFF_TX_DESC_IDX) }, + { "rnr_txq1_tx_cnt", GEN_RUNNER_TXQ_STAT8(1, TXQ_OFF_TX_DESC_CNT) }, + { "rnr_txq1_cnt_pkt", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_STAT_CNT_PKT_SENT_REG) }, + { "rnr_txq1_cnt_reclaimed", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_STAT_CNT_PKT_RECLAIMED_REG) }, + { "rnr_txq1_ring_push_idx", GEN_RUNNER_TXQ_STAT16(1, TXQ_OFF_RING_PUSH_IDX_REG) }, + { "rnr_txq1_ring_reclaim_idx", GEN_RUNNER_TXQ_STAT16(1, TXQ_OFF_RING_RECLAIM_IDX_REG) }, + { "rnr_txq1_acb_qfull", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_STAT_CNT_ACB_QFULL) }, +}; + +const size_t bcm_runner_fw_estat_count = ARRAY_SIZE(bcm_runner_fw_estat); + +u64 bcm_runner_fw_read_estat(struct bcm_enet_runner_priv *priv, int idx) +{ + const struct bcm_runner_ethtool_stat *s; + + BUG_ON(idx >=bcm_runner_fw_estat_count); + s = &bcm_runner_fw_estat[idx]; + + switch (s->type) { + case 1: + switch (s->size) { + case 1: + return fw_rx_reg_readb(priv, s->reg); + case 2: + return fw_rx_reg_readh(priv, s->reg); + case 4: + default: + return fw_rx_reg_readl(priv, s->reg); + } + case 2: + switch (s->size) { + case 1: + return fw_tx_reg_readb(priv, s->reg); + case 2: + return fw_tx_reg_readh(priv, s->reg); + case 4: + default: + return fw_tx_reg_readl(priv, s->reg); + } + } + return 0; +} + +/* + * callback when a new DSA slave device is using this dev as master + */ +static int +bcm_enet_runner_dsa_port_reg(struct bcm_enet_runner_priv *priv, + struct net_device *slave_dev) +{ + struct dsa_port *dp = dsa_port_from_netdev(slave_dev); + struct bcm_dsa_port *bdp; + + if (dp->ds->index) + return 0; + + bdp = kmalloc(sizeof (*dp), GFP_ATOMIC); + if (!bdp) + return 0; + + printk("dsa_port_ret: %s -> %s, imp_port %d\n", + netdev_name(priv->netdev), netdev_name(slave_dev), dp->cpu_dp->index); + + bdp->port = dp->index; + bdp->imp_port = dp->cpu_dp ? dp->cpu_dp->index : 0; + bdp->slave_netdev = slave_dev; + list_add(&bdp->next, &priv->dsa_ports); + /* resolve queue mapping at device open time, when actual + * number of queue is known */ + return 0; +} + +/* + * callback when a new DSA slave device is detached from this master + */ +static int +bcm_enet_runner_dsa_port_remove(struct bcm_enet_runner_priv *priv, + struct net_device *slave_dev) +{ + struct bcm_dsa_port *dp; + + list_for_each_entry(dp, &priv->dsa_ports, next) { + if (dp->slave_netdev == slave_dev) { + list_del(&dp->next); + kfree(dp); + break; + } + } + + return 0; +} + +/* + * DSA slave device change notifier + */ +static int bcm_enet_runner_netdev_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + int ret = NOTIFY_DONE; + struct netdev_notifier_changeupper_info *info = ptr; + struct net_device *dev = netdev_notifier_info_to_dev(ptr); + struct bcm_enet_runner_priv *priv; + + priv = container_of(nb, struct bcm_enet_runner_priv, netdev_notifier); + if (priv->netdev != dev) + return NOTIFY_DONE; + + switch (event) { + case NETDEV_CHANGEUPPER: + if (dev->netdev_ops != &bcm_runner_ops) + return NOTIFY_DONE; + + if (!dsa_slave_dev_check(info->upper_dev)) + return NOTIFY_DONE; + + if (info->linking) + ret = bcm_enet_runner_dsa_port_reg(priv, + info->upper_dev); + else + ret = bcm_enet_runner_dsa_port_remove(priv, + info->upper_dev); + break; + } + + return notifier_from_errno(ret); +} + +/* + * + */ +static int bcm_enet_runner_probe(struct platform_device *pdev) +{ + struct bcm_enet_runner_priv *priv; + struct device_node *xrdp_node; + struct platform_device *xrdp_pdev; + struct bcm_xrdp_priv *xrdp_priv; + struct net_device *netdev; + enum bcm_runner_port_type port_type; + u8 macaddr[ETH_ALEN]; + phy_interface_t phy_mode; + int ret, err; + size_t i; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_init(&pdev->dev); +#endif + + ret = of_get_phy_mode(pdev->dev.of_node, &phy_mode); + if (ret < 0) { + dev_err(&pdev->dev, "incorrect phy-mode\n"); + return -ENODEV; + } + + xrdp_node = of_parse_phandle(pdev->dev.of_node, "enet-runner,xrdp", 0); + if (!xrdp_node) { + dev_err(&pdev->dev, "failed to find XRDP node\n"); + return -ENODEV; + } + + xrdp_pdev = of_find_device_by_node(xrdp_node); + of_node_put(xrdp_node); + if (!xrdp_pdev) { + dev_err(&pdev->dev, "failed to find XRDP device\n"); + return -ENODEV; + } + + xrdp_priv = platform_get_drvdata(xrdp_pdev); + if (!xrdp_priv) { + dev_dbg(&pdev->dev, "XRDP not yet initialized\n"); + return -EPROBE_DEFER; + } + + err = of_get_mac_address(pdev->dev.of_node, macaddr); + if (err) { + dev_err(&pdev->dev, + "failed to find address node\n"); + return err; + } + + netdev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof (*priv), + BCM_ENET_RUNNER_MAX_TXQ, + BCM_ENET_RUNNER_MAX_RXQ); + if (!netdev) + return -ENOMEM; + + priv = netdev_priv(netdev); + priv->netdev = netdev; + priv->pdev = pdev; + priv->xrdp = xrdp_priv; + priv->rxq_size = 512; + priv->txq_size = 512; + INIT_DELAYED_WORK(&priv->reset_link_work, reset_link_work); + INIT_LIST_HEAD(&priv->dsa_ports); + for (i = 0; i < ARRAY_SIZE(priv->rxq_info); i++) + cpumask_copy(&priv->rxq_info[i].irq_affinity_mask, + cpu_all_mask); + for (i = 0; i < ARRAY_SIZE(priv->txq_info); i++) + cpumask_copy(&priv->txq_info[i].irq_affinity_mask, + cpu_all_mask); + + port_type = (uintptr_t)of_device_get_match_data(&pdev->dev); + switch (port_type) { + case BCM_RUNNER_PORT_UNIMAC: + priv->port_ops = &port_unimac_ops; + break; + case BCM_RUNNER_PORT_XPORT: + priv->port_ops = &port_xport_ops; + break; + default: + return -EINVAL; + } + priv->port_type = port_type; + + priv->port_priv = priv->port_ops->init(priv); + if (IS_ERR(priv->port_priv)) + return PTR_ERR(priv->port_priv); + + /* register netdevice */ + netdev->min_mtu = ETH_ZLEN - ETH_HLEN; + netdev->max_mtu = BCM_RUNNER_MAC_MAX_MTU; + netdev->netdev_ops = &bcm_runner_ops; + netdev->ethtool_ops = &bcm_runner_ethtool_ops; + dev_addr_mod(netdev, 0, macaddr, ETH_ALEN); + SET_NETDEV_DEV(netdev, &pdev->dev); + netif_napi_add_weight(netdev, &priv->napi, bcm_runner_poll, 16); + + priv->phylink_pcs.ops = &bcm_enet_runner_phylink_pcs_ops; + priv->phylink_pcs.poll = priv->port_ops->pcs_poll; + + priv->phylink_config.legacy_pre_march2020 = true; + priv->phylink_config.dev = &netdev->dev; + priv->phylink_config.type = PHYLINK_NETDEV; + priv->port_ops->get_mac_capabilities( + &priv->phylink_config.mac_capabilities); + priv->port_ops->get_supported_interfaces( + priv->phylink_config.supported_interfaces); + + priv->phylink = phylink_create(&priv->phylink_config, + pdev->dev.fwnode, + phy_mode, + &bcm_enet_runner_phylink_ops); + if (IS_ERR(priv->phylink)) + return PTR_ERR(priv->phylink); + + ret = phylink_of_phy_connect(priv->phylink, pdev->dev.of_node, 0); + if (ret) { + dev_err(&pdev->dev, "failed to connect to PHY\n"); + goto out; + } + + priv->netdev_notifier.notifier_call = bcm_enet_runner_netdev_notifier; + ret = register_netdevice_notifier(&priv->netdev_notifier); + if (ret) { + dev_err(&pdev->dev, "failed to register DSA notifier\n"); + goto out; + } + priv->netdev_notifier_registered = true; + priv->dgasp_nb.notifier_call = bcm_enet_runner_dgasp_handler; + + ret = register_netdev(netdev); + if (ret) + goto out; + + platform_set_drvdata(pdev, priv); + return 0; + +out: + if (priv->netdev_notifier_registered) + unregister_netdevice_notifier(&priv->netdev_notifier); + if (priv->phylink) + phylink_destroy(priv->phylink); + return ret; +} + +/* + * + */ +static int bcm_enet_runner_remove(struct platform_device *pdev) +{ + struct bcm_enet_runner_priv *priv = platform_get_drvdata(pdev); + + unregister_netdev(priv->netdev); + unregister_netdevice_notifier(&priv->netdev_notifier); + phylink_destroy(priv->phylink); + return 0; +} + +static const struct of_device_id bcm63158_enet_runner_of_match[] = { + { .compatible = "brcm,bcm63158-enet-runner-unimac", + .data = (void *)BCM_RUNNER_PORT_UNIMAC }, + { .compatible = "brcm,bcm63158-enet-runner-xport" , + .data = (void *)BCM_RUNNER_PORT_XPORT }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, bcm63158_enet_runner_of_match); + +/* + * + */ +struct platform_driver bcm63158_enet_runner_driver = { + .probe = bcm_enet_runner_probe, + .remove = bcm_enet_runner_remove, + .driver = { + .name = "bcm63158_enet_runner", + .of_match_table = bcm63158_enet_runner_of_match, + .owner = THIS_MODULE, + }, +}; + +static int __init bcm63158_enet_runner_init(void) +{ + bcm63158_dbg_root = debugfs_create_dir("bcm63158_enet_runner", NULL); + if (!bcm63158_dbg_root) + return -ENOMEM; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_notifier.notifier_call = ff_notifier_event_cb; + register_netdevice_notifier(&ff_notifier); +#endif + return platform_driver_register(&bcm63158_enet_runner_driver); +} + +static void __exit bcm63158_enet_runner_exit(void) +{ +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + unregister_netdevice_notifier(&ff_notifier); +#endif + platform_driver_unregister(&bcm63158_enet_runner_driver); + debugfs_remove_recursive(bcm63158_dbg_root); +} + + +module_init(bcm63158_enet_runner_init); +module_exit(bcm63158_enet_runner_exit); + +MODULE_DESCRIPTION("BCM63158 ethernet runner driver"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_LICENSE("GPL"); diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.c 2023-05-31 17:11:03.409680387 +0200 @@ -0,0 +1,389 @@ +#include "port_unimac.h" + +#define GEN_MIB_STAT(m) \ + sizeof(((struct unimac_mib *)0)->m), \ + offsetof(struct unimac_mib, m) + +static const struct bcm_runner_ethtool_stat unimac_mib_estat[] = { + { "rx_64", GEN_MIB_STAT(rx_64), UNIMAC_MIB_GR64_REG, }, + { "rx_65_127", GEN_MIB_STAT(rx_65_127), UNIMAC_MIB_GR127_REG, }, + { "rx_128_255", GEN_MIB_STAT(rx_128_255), UNIMAC_MIB_GR255_REG, }, + { "rx_256_511", GEN_MIB_STAT(rx_256_511), UNIMAC_MIB_GR511_REG, }, + { "rx_512_1023", GEN_MIB_STAT(rx_512_1023), UNIMAC_MIB_GR1023_REG, }, + { "rx_1024_1518", GEN_MIB_STAT(rx_1024_1518), UNIMAC_MIB_GR1518_REG, }, + { "rx_1519_1522_vlan", GEN_MIB_STAT(rx_1519_1522_vlan), UNIMAC_MIB_GRMGV_REG, }, + { "rx_1519_2047", GEN_MIB_STAT(rx_1519_2047), UNIMAC_MIB_GR2047_REG, }, + { "rx_2048_4095", GEN_MIB_STAT(rx_2048_4095), UNIMAC_MIB_GR4095_REG, }, + { "rx_4096_9216", GEN_MIB_STAT(rx_4096_9216), UNIMAC_MIB_GR9216_REG, }, + { "rx_all_pkts", GEN_MIB_STAT(rx_all_pkts), UNIMAC_MIB_GRPKT_REG, }, + { "rx_all_octets", GEN_MIB_STAT(rx_all_octets), UNIMAC_MIB_GRBYT_REG, }, + { "rx_mult", GEN_MIB_STAT(rx_mult), UNIMAC_MIB_GRMCA_REG, }, + { "rx_brdcast", GEN_MIB_STAT(rx_brdcast), UNIMAC_MIB_GRBCA_REG, }, + { "rx_crc", GEN_MIB_STAT(rx_crc), UNIMAC_MIB_GRFCS_REG, }, + { "rx_cntrl", GEN_MIB_STAT(rx_cntrl), UNIMAC_MIB_GRXCF_REG, }, + { "rx_pause", GEN_MIB_STAT(rx_pause), UNIMAC_MIB_GRXPF_REG, }, + { "rx_und", GEN_MIB_STAT(rx_und), UNIMAC_MIB_GRXUO_REG, }, + { "rx_align", GEN_MIB_STAT(rx_align), UNIMAC_MIB_GRALN_REG, }, + { "rx_frame_len", GEN_MIB_STAT(rx_frame_len), UNIMAC_MIB_GRFLR_REG, }, + { "rx_code", GEN_MIB_STAT(rx_code), UNIMAC_MIB_GRCDE_REG, }, + { "rx_carrier", GEN_MIB_STAT(rx_carrier), UNIMAC_MIB_GRFCR_REG, }, + { "rx_oversize", GEN_MIB_STAT(rx_oversize), UNIMAC_MIB_GROVR_REG, }, + { "rx_jabber", GEN_MIB_STAT(rx_jabber), UNIMAC_MIB_GRJBR_REG, }, + { "rx_too_big", GEN_MIB_STAT(rx_too_big), UNIMAC_MIB_GRMTUE_REG, }, + { "rx_gd_pkts", GEN_MIB_STAT(rx_gd_pkts), UNIMAC_MIB_GRPOK_REG, }, + { "rx_unicast", GEN_MIB_STAT(rx_unicast), UNIMAC_MIB_GRUC_REG, }, + { "rx_ppp", GEN_MIB_STAT(rx_ppp), UNIMAC_MIB_GRPPP_REG, }, + { "rx_crc_match", GEN_MIB_STAT(rx_crc_match), UNIMAC_MIB_GRCRC_REG, }, + { "tx_64", GEN_MIB_STAT(tx_64), UNIMAC_MIB_TR64_REG, }, + { "tx_65_127", GEN_MIB_STAT(tx_65_127), UNIMAC_MIB_TR127_REG, }, + { "tx_128_255", GEN_MIB_STAT(tx_128_255), UNIMAC_MIB_TR255_REG, }, + { "tx_256_511", GEN_MIB_STAT(tx_256_511), UNIMAC_MIB_TR511_REG, }, + { "tx_512_1023", GEN_MIB_STAT(tx_512_1023), UNIMAC_MIB_TR1023_REG, }, + { "tx_1024_1518", GEN_MIB_STAT(tx_1024_1518), UNIMAC_MIB_TR1518_REG, }, + { "tx_1519_1522_vlan", GEN_MIB_STAT(tx_1519_1522_vlan), UNIMAC_MIB_TRMGV_REG, }, + { "tx_1523_2047", GEN_MIB_STAT(tx_1523_2047), UNIMAC_MIB_TR2047_REG, }, + { "tx_2048_4095", GEN_MIB_STAT(tx_2048_4095), UNIMAC_MIB_TR4095_REG, }, + { "tx_4096_9216", GEN_MIB_STAT(tx_4096_9216), UNIMAC_MIB_TR9216_REG, }, + { "tx_all_pkts", GEN_MIB_STAT(tx_all_pkts), UNIMAC_MIB_GTPKT_REG, }, + { "tx_mult", GEN_MIB_STAT(tx_mult), UNIMAC_MIB_GTMCA_REG, }, + { "tx_brdcast", GEN_MIB_STAT(tx_brdcast), UNIMAC_MIB_GTBCA_REG, }, + { "tx_pause", GEN_MIB_STAT(tx_pause), UNIMAC_MIB_GTXPF_REG, }, + { "tx_control", GEN_MIB_STAT(tx_control), UNIMAC_MIB_GTXCF_REG, }, + { "tx_fcs", GEN_MIB_STAT(tx_fcs), UNIMAC_MIB_GTFCS_REG, }, + { "tx_oversize", GEN_MIB_STAT(tx_oversize), UNIMAC_MIB_GTOVR_REG, }, + { "tx_defer", GEN_MIB_STAT(tx_defer), UNIMAC_MIB_GTDRF_REG, }, + { "tx_ex_defer", GEN_MIB_STAT(tx_ex_defer), UNIMAC_MIB_GTEDF_REG, }, + { "tx_1_col", GEN_MIB_STAT(tx_1_col), UNIMAC_MIB_GTSCL_REG, }, + { "tx_m_col", GEN_MIB_STAT(tx_m_col), UNIMAC_MIB_GTMCL_REG, }, + { "tx_late_col", GEN_MIB_STAT(tx_late_col), UNIMAC_MIB_GTLCL_REG, }, + { "tx_ex_col", GEN_MIB_STAT(tx_ex_col), UNIMAC_MIB_GTXCL_REG, }, + { "tx_frag", GEN_MIB_STAT(tx_frag), UNIMAC_MIB_GTFRG_REG, }, + { "tx_col", GEN_MIB_STAT(tx_col), UNIMAC_MIB_GTNCL_REG, }, + { "tx_jabber", GEN_MIB_STAT(tx_jabber), UNIMAC_MIB_GTJBR_REG, }, + { "tx_gd_octets", GEN_MIB_STAT(tx_gd_octets), UNIMAC_MIB_GTBYT_REG, }, + { "tx_gd_pkts", GEN_MIB_STAT(tx_gd_pkts), UNIMAC_MIB_GTPOK_REG, }, + { "tx_unicast", GEN_MIB_STAT(tx_unicast), UNIMAC_MIB_GTUC_REG, }, + { "rx_runt0_pkts", GEN_MIB_STAT(rx_runt0_pkts), UNIMAC_MIB_RRPKT_REG, }, + { "rx_runt1_pkts", GEN_MIB_STAT(rx_runt1_pkts), UNIMAC_MIB_RRUND_REG, }, + { "rx_runt2_pkts", GEN_MIB_STAT(rx_runt2_pkts), UNIMAC_MIB_RRFRG_REG, }, + { "rx_runt2_bytes", GEN_MIB_STAT(rx_runt2_bytes), UNIMAC_MIB_RRBYT_REG, }, +}; + +/* + * + */ +static void mode_unimac_stats_update(void *mode_priv, + struct net_device_stats *s) +{ + struct unimac_priv *port = mode_priv; + u32 val; + + val = mac_mib_reg_readl(port, UNIMAC_MIB_GRFCS_REG); + s->rx_crc_errors = val; + + val = mac_mib_reg_readl(port, UNIMAC_MIB_GRFLR_REG); + s->rx_length_errors = val; + + val = mac_mib_reg_readl(port, UNIMAC_MIB_GRCDE_REG); + val += mac_mib_reg_readl(port, UNIMAC_MIB_GRJBR_REG); + val += mac_mib_reg_readl(port, UNIMAC_MIB_GRALN_REG); + s->rx_errors = val; +} + + +/* + * read mib data + */ +static void mode_unimac_mib_update(void *mode_priv) +{ + struct unimac_priv *port = mode_priv; + size_t i; + + for (i = 0; i < ARRAY_SIZE(unimac_mib_estat); i++) { + const struct bcm_runner_ethtool_stat *s; + u32 val; + char *p; + + s = &unimac_mib_estat[i]; + + val = mac_mib_reg_readl(port, s->reg); + p = (char *)&port->mib + s->offset; + + if (s->size == sizeof(u64)) + *(u64 *)p = val; + else + *(u32 *)p = val; + } +} + +/* + * + */ +static void *mode_unimac_mib_get_data(void *mode_priv) +{ + struct unimac_priv *port = mode_priv; + return &port->mib; +} + + +/* + * reset unimac + */ +static void unimac_reset(struct unimac_priv *port) +{ + u32 val; + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val |= UNIMAC_CFG_CMD_SW_RESET_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); + msleep(1); + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val &= ~UNIMAC_CFG_CMD_SW_RESET_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); +} + +/* + * setup unimac for given speed + */ +static void unimac_setup(struct unimac_priv *port, unsigned int speed) +{ + u32 val; + + /* set correct speed */ + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val |= UNIMAC_CFG_CMD_CTRL_FRM_EN_MASK; + val |= UNIMAC_CFG_CMD_PROMISC_EN_MASK; + val &= ~UNIMAC_CFG_CMD_SPEED_MASK; + switch (speed) { + case SPEED_10: + val |= UNIMAC_CFG_CMD_SPEED_10 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + case SPEED_100: + val |= UNIMAC_CFG_CMD_SPEED_100 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + case SPEED_1000: + val |= UNIMAC_CFG_CMD_SPEED_1000 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + case SPEED_2500: + val |= UNIMAC_CFG_CMD_SPEED_2500 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + } + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); + + val = mac_misc_reg_readl(port, UNIMAC_MISC_CFG_REG); + val |= UNIMAC_MISC_CFG_GMII_DIRECT_MASk; + mac_misc_reg_writel(port, UNIMAC_MISC_CFG_REG, val); +} + +/* + * + */ +static void unimac_enable(struct unimac_priv *port) +{ + u32 val; + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val |= UNIMAC_CFG_CMD_RX_EN_MASK; + val |= UNIMAC_CFG_CMD_TX_EN_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); +} + +/* + * disable unimac rx/tx + */ +static void unimac_disable(struct unimac_priv *port) +{ + u32 val; + + val = mac_misc_reg_readl(port, UNIMAC_MISC_CFG_REG); + val &= ~UNIMAC_MISC_CFG_GMII_DIRECT_MASk; + mac_misc_reg_writel(port, UNIMAC_MISC_CFG_REG, val); + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val &= ~UNIMAC_CFG_CMD_RX_EN_MASK; + val &= ~UNIMAC_CFG_CMD_TX_EN_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); + + unimac_reset(port); +} + +/* + * + */ +static void mode_unimac_mtu_set(void *mode_priv, unsigned int size) +{ + struct unimac_priv *port = mode_priv; + u32 val; + + /* (from vendor BSP init) seems to have no effect on rx */ + mac_cfg_reg_writel(port, UNIMAC_CFG_RX_MAX_PKT_SIZE_REG, size); + + /* this will truncate any bigger RX packet to size (size + * includes FCS), and increment rx_too_big MIB counter. TX + * path effect not tested */ + mac_cfg_reg_writel(port, UNIMAC_CFG_FRM_LEN_REG, size); + + /* (from vendor BSP init) seems to have no effect on rx */ + val = mac_misc_reg_readl(port, UNIMAC_MISC_EXT_CFG1_REG); + val &= ~UNIMAC_MISC_EXT_CFG1_MAX_PKT_SIZE_MASK; + val |= size; + mac_misc_reg_writel(port, UNIMAC_MISC_EXT_CFG1_REG, val); +} + +/* + * + */ +static void mode_phylink_link_up(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + int speed, + int duplex, + struct phy_device *phy) +{ + struct unimac_priv *port = mode_priv; + unimac_setup(port, speed); + unimac_enable(port); +} + +/* + * + */ +static void mode_phylink_link_down(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface) +{ + struct unimac_priv *port = mode_priv; + unimac_disable(port); +} + +/* + * + */ +static void *mode_unimac_init(void *port_priv, + const struct bcm_xrdp_enet_params *params) + +{ + struct unimac_priv *port = port_priv; + port->regs = params->mac_regs; + return port_priv; +} + +static void mode_unimac_stop(void *mode_priv) +{ + struct unimac_priv *port = mode_priv; + bcm_runner_fw_tx_stop_wait(port->priv); +} + +/* + * + */ +static u32 mode_get_bbh_id(void *port_priv) +{ + struct unimac_priv *port = port_priv; + return port->bbh_id; +} + +/* + * + */ +static void mode_unimac_release(void *mode_priv) +{ +} + +const struct bcm_enet_mode_ops unimac_mode_ops = { + .name = "gmii", + + .init = mode_unimac_init, + .stop = mode_unimac_stop, + .release = mode_unimac_release, + .get_bbh_id = mode_get_bbh_id, + .mtu_set = mode_unimac_mtu_set, + .stats_update = mode_unimac_stats_update, + + /* mib operation */ + .mib_estat = unimac_mib_estat, + .mib_estat_count = ARRAY_SIZE(unimac_mib_estat), + .mib_update = mode_unimac_mib_update, + .mib_get_data = mode_unimac_mib_get_data, + + /* + * phylink callback + */ + .phylink_link_down = mode_phylink_link_down, + .phylink_link_up = mode_phylink_link_up, +}; + +/* + * + */ +static void *unimac_port_init(struct bcm_enet_runner_priv *priv) +{ + struct unimac_priv *port; + int ret; + + port = devm_kzalloc(&priv->pdev->dev, sizeof (*port), GFP_KERNEL); + if (!port) + return ERR_PTR(-ENODEV); + + port->priv = priv; + + ret = of_property_read_u32(priv->pdev->dev.of_node, + "enet-runner,bbh", + &port->bbh_id); + if (ret) + return ERR_PTR(ret); + + return port; +} + +/* + * + */ +static void unimac_port_release(void *data) +{ + struct unimac_priv *port = data; + devm_kfree(&port->priv->pdev->dev, port); +} + +/* + * + */ +static int unimac_mode_select(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_GMII: + return 0; + default: + return -ENOTSUPP; + } +} + +/* + * + */ +static void unimac_get_supported_interfaces(unsigned long *modes) +{ + __set_bit(PHY_INTERFACE_MODE_GMII, modes); +} + +/* + * + */ +static void unimac_get_mac_capabilities(unsigned long *caps) +{ + *caps = MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD; +} + +const struct bcm_enet_port_ops port_unimac_ops = { + .modes = { + &unimac_mode_ops, + }, + .mode_count = 1, + + .init = unimac_port_init, + .release = unimac_port_release, + .mode_select = unimac_mode_select, + .get_supported_interfaces = unimac_get_supported_interfaces, + .get_mac_capabilities = unimac_get_mac_capabilities, +}; diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.h 2023-03-09 15:06:11.360234118 +0100 @@ -0,0 +1,119 @@ +#ifndef PORT_UNIMAC_H_ +#define PORT_UNIMAC_H_ + +#include "bcm63158_enet_runner.h" +#include "regs/unimac_regs.h" + +/* + * unimac MIB + */ +struct unimac_mib { + u32 rx_64; + u32 rx_65_127; + u32 rx_128_255; + u32 rx_256_511; + u32 rx_512_1023; + u32 rx_1024_1518; + u32 rx_1519_1522_vlan; + u32 rx_1519_2047; + u32 rx_2048_4095; + u32 rx_4096_9216; + + u32 rx_all_pkts; + u64 rx_all_octets; + u32 rx_mult; + u32 rx_brdcast; + u32 rx_crc; + u32 rx_cntrl; + u32 rx_pause; + u32 rx_und; + u32 rx_align; + u32 rx_frame_len; + u32 rx_code; + u32 rx_carrier; + u32 rx_oversize; + u32 rx_jabber; + u32 rx_too_big; + + u32 rx_gd_pkts; + u32 rx_unicast; + u32 rx_ppp; + u32 rx_crc_match; + + u32 tx_64; + u32 tx_65_127; + u32 tx_128_255; + u32 tx_256_511; + u32 tx_512_1023; + u32 tx_1024_1518; + u32 tx_1519_1522_vlan; + u32 tx_1523_2047; + u32 tx_2048_4095; + u32 tx_4096_9216; + + u32 tx_all_pkts; + u32 tx_mult; + u32 tx_brdcast; + u32 tx_pause; + u32 tx_control; + u32 tx_fcs; + u32 tx_oversize; + u32 tx_defer; + u32 tx_ex_defer; + u32 tx_1_col; + u32 tx_m_col; + u32 tx_late_col; + u32 tx_ex_col; + u32 tx_frag; + u32 tx_col; + u32 tx_jabber; + + u64 tx_gd_octets; + u32 tx_gd_pkts; + u32 tx_unicast; + + u32 rx_runt0_pkts; + u32 rx_runt1_pkts; + u32 rx_runt2_pkts; + u32 rx_runt2_bytes; +}; + +struct unimac_priv { + struct bcm_enet_runner_priv *priv; + void __iomem *regs; + struct unimac_mib mib; + u32 bbh_id; +}; + +/* + * io accessors + */ +static inline u32 mac_cfg_reg_readl(struct unimac_priv *port, u32 offset) +{ + return ioread32(port->regs + UNIMAC_CFG_OFFSET(port->bbh_id) + offset); +} + +static inline void mac_cfg_reg_writel(struct unimac_priv *port, u32 offset, + u32 val) +{ + iowrite32(val, port->regs + UNIMAC_CFG_OFFSET(port->bbh_id) + offset); +} + +static inline u32 mac_misc_reg_readl(struct unimac_priv *port, u32 offset) +{ + return ioread32(port->regs + UNIMAC_MISC_OFFSET(port->bbh_id) + offset); +} + +static inline void mac_misc_reg_writel(struct unimac_priv *port, u32 offset, + u32 val) +{ + iowrite32(val, port->regs + UNIMAC_MISC_OFFSET(port->bbh_id) + offset); +} + +static inline u32 mac_mib_reg_readl(struct unimac_priv *port, u32 offset) +{ + return ioread32(port->regs + UNIMAC_MIB_OFFSET(port->bbh_id) + offset); +} + + +#endif /* PORT_UNIMAC_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.c 2023-10-10 18:55:15.599801041 +0200 @@ -0,0 +1,271 @@ +#include "port_xport.h" + +/* + * fetch pinctrl for rogue1_in related stuff for xport, and select the + * rogue1 state. + */ +static int xport_set_pinctrl_rogue1(struct xport_priv *port) +{ + int err = 0; + struct device *dev = &port->priv->pdev->dev; + struct pinctrl_state *pins_rogue1; + + if (port->pinctrl) { + dev_dbg(dev, "we already have a pinctrl for this port?!\n"); + goto lookup_state; + } + + port->pinctrl = devm_pinctrl_get(dev); + if (IS_ERR(port->pinctrl)) { + port->pinctrl = NULL; + return PTR_ERR(port->pinctrl); + } + +lookup_state: + pins_rogue1 = pinctrl_lookup_state(port->pinctrl, "rogue1"); + if (IS_ERR(pins_rogue1)) { + dev_err(dev, "unable to get rogue1 pinctrl state.\n"); + err = PTR_ERR(pins_rogue1); + goto err_put_pinctrl; + } + + err = pinctrl_select_state(port->pinctrl, pins_rogue1); + if (err) { + dev_err(dev, "unable to set xport pinctrl state to 'rogue1'\n"); + goto err_put_pinctrl; + } + + return 0; + +err_put_pinctrl: + devm_pinctrl_put(port->pinctrl); + port->pinctrl = NULL; + return err; +} + +/* + * just release the pinctrl for the port, we do not otherwise need to + * manipulate the rs0 gpio here, and the testbed needs this gpio to + * test the rogue_in function. releasing the pinctrl will make it + * accessible via fbxgpio. + */ +static int xport_set_pinctrl_rs0(struct xport_priv *port) +{ + if (port->pinctrl) + devm_pinctrl_put(port->pinctrl); + port->pinctrl = NULL; + + return 0; +} + +/* + * switch pinctrl state on xport, called from port_xport_epon or + * port_xport_xlmac code, when switching the port mode. + */ +int xport_switch_pinctrl(struct xport_priv *port, int which) +{ + struct device *dev = &port->priv->pdev->dev; + int err; + + switch (which) { + case XPORT_PIN_ROGUE1: + err = xport_set_pinctrl_rogue1(port); + break; + + case XPORT_PIN_RS0: + err = xport_set_pinctrl_rs0(port); + break; + + default: + dev_warn(dev, "invalid xport pin ID %d\n", which); + return -EINVAL; + } + + if (err) { + dev_err(dev, "unable to change xport pinctrl state.\n"); + return err; + } + + return 0; +} + +/* + * + */ +static void *xport_init(struct bcm_enet_runner_priv *priv) +{ + struct resource *res_wan_top; + struct resource *res_xport; + struct resource *res_xlif; + struct resource *res_epon; + struct reset_control *wan_ae_rst; + struct xport_priv *port; + int ret; + + port = devm_kzalloc(&priv->pdev->dev, sizeof (*port), GFP_KERNEL); + if (!port) + return ERR_PTR(-ENODEV); + + port->priv = priv; + + ret = of_property_read_u32(priv->pdev->dev.of_node, + "enet-runner,xport-ae-bbh", + &port->ae_bbh_id); + if (ret) + return ERR_PTR(ret); + + ret = of_property_read_u32(priv->pdev->dev.of_node, + "enet-runner,xport-pon-bbh", + &port->pon_bbh_id); + if (ret) + return ERR_PTR(ret); + + res_wan_top = platform_get_resource_byname(priv->pdev, + IORESOURCE_MEM, "wan_top"); + if (!res_wan_top) { + dev_err(&priv->pdev->dev, "unable to get wan_top resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[0] = devm_ioremap_resource(&priv->pdev->dev, res_wan_top); + if (IS_ERR(port->regs[0])) { + dev_err(&priv->pdev->dev, "unable to ioremap regs\n"); + return port->regs[0]; + } + port->regs_size[0] = resource_size(res_wan_top); + + res_xport = platform_get_resource_byname(priv->pdev, + IORESOURCE_MEM, "xport"); + if (!res_xport) { + dev_err(&priv->pdev->dev, "unable to get xport resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[1] = devm_ioremap_resource(&priv->pdev->dev, res_xport); + if (IS_ERR(port->regs[1])) { + dev_err(&priv->pdev->dev, "unable to ioremap regs\n"); + return port->regs[1]; + } + port->regs_size[1] = resource_size(res_xport); + + res_xlif = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, + "xlif"); + if (!res_xlif) { + dev_err(&priv->pdev->dev, "unable to get xlif resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[2] = devm_ioremap_resource(&priv->pdev->dev, res_xlif); + if (IS_ERR(port->regs[2])) { + dev_err(&priv->pdev->dev, "unable to ioremap regs\n"); + return port->regs[2]; + } + port->regs_size[2] = resource_size(res_xlif); + + res_epon = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, + "epon"); + if (!res_epon) { + dev_err(&priv->pdev->dev, "unable to get epon resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[3] = devm_ioremap_resource(&priv->pdev->dev, res_epon); + if (IS_ERR(port->regs[3])) { + dev_err(&priv->pdev->dev, "unable to ioremap epon regs\n"); + return port->regs[3]; + } + port->regs_size[3] = resource_size(res_epon); + + wan_ae_rst = devm_reset_control_get(&priv->pdev->dev, "wan_ae"); + if (IS_ERR(wan_ae_rst)) { + dev_err(&priv->pdev->dev, "missing wan_ae reset control: %ld\n", + PTR_ERR(wan_ae_rst)); + return ERR_PTR(-ENODEV); + } + port->wan_ae_rst = wan_ae_rst; + + /* + * default to forcing LBE to 1, this is connected to TX + * disabled so it will disable TX by default + * + * this is only applied by AE mode, the PON mode will disable + * it + * + */ + port->lbe_force = true; + port->lbe_force_value = true; + + return port; +} + +/* + * + */ +static void xport_pcs_shutdown(void *data) +{ + struct xport_priv *port = data; + xport_serdes_shutdown(port); +} + +/* + * + */ +static void xport_release(void *data) +{ + struct xport_priv *port = data; + devm_kfree(&port->priv->pdev->dev, port); +} + +/* + * + */ +static int xport_mode_select(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_10GBASER: + return 0; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + return 1; + default: + return -ENOTSUPP; + } +} + +/* + * + */ +static void xport_get_supported_interfaces(unsigned long *modes) +{ + __set_bit(PHY_INTERFACE_MODE_1000BASEX, modes); + __set_bit(PHY_INTERFACE_MODE_2500BASEX, modes); + __set_bit(PHY_INTERFACE_MODE_SGMII, modes); + __set_bit(PHY_INTERFACE_MODE_10GBASER, modes); + __set_bit(PHY_INTERFACE_MODE_10000_1000_BASEPRX_U, modes); +} + +/* + * + */ +static void xport_get_mac_capabilities(unsigned long *caps) +{ + *caps = MAC_1000FD | MAC_2500FD | MAC_10000FD; +} + +const struct bcm_enet_port_ops port_xport_ops = { + .modes = { + &xport_xlmac_mode_ops, + &xport_epon_mode_ops, + }, + .mode_count = 2, + + .init = xport_init, + .release = xport_release, + .pcs_poll = 1, + .pcs_shutdown = xport_pcs_shutdown, + .mode_select = xport_mode_select, + .get_supported_interfaces = xport_get_supported_interfaces, + .get_mac_capabilities = xport_get_mac_capabilities, +}; diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.h 2023-10-10 18:55:15.599801041 +0200 @@ -0,0 +1,120 @@ +#ifndef PORT_XPORT_H_ +#define PORT_XPORT_H_ + +#include "bcm63158_enet_runner.h" +#include +#include +#include + +struct xport_priv { + struct bcm_enet_runner_priv *priv; + + void __iomem *regs[4]; + u32 regs_size[4]; + struct reset_control *wan_ae_rst; + u32 ae_bbh_id; + u32 pon_bbh_id; + + bool lbe_force; + bool lbe_force_value; + + struct pinctrl *pinctrl; +}; + +/* + * serdes utils + */ +struct serdes_params { + u32 tx_pll_vco_div4; + u32 tx_pll_vco_div2; + u32 rx_pll_vco_div4; + u32 rx_pll_vco_div2; + u32 rx_pll_id; + u32 tx_pll_id; + + u32 tx_pll_force_kvh_bw; + u32 rx_pll_force_kvh_bw; + u32 tx_pll_kvh_force; + u32 rx_pll_kvh_force; + + u32 tx_pll_2rx_bw; + u32 rx_pll_2rx_bw; + + u32 rx_pll_fracn_div; + u32 rx_pll_fracn_ndiv; + + u32 tx_pll_fracn_div; + u32 tx_pll_fracn_ndiv; + + u32 tx_pll_fracn_sel; + u32 rx_pll_fracn_sel; + + u32 rx_pll_ditheren; + u32 tx_pll_ditheren; + + u32 rx_pll_mode; + u32 tx_pll_mode; + + u32 rx_tx_rate_ratio; + + u32 rx_pon_mac_ctrl; + u32 tx_pon_mac_ctrl; + u32 tx_sync_e_ctrl; + + u32 rx_osr_mode; + u32 tx_osr_mode; + + bool do_rx_pi_spacing; + u32 clk90_offset; + u32 p1_offset; + + bool do_pll_charge_pump; + bool do_pll_charge_pump_10g; + bool do_vga_rf; + bool do_sigdetect; + bool do_ae; + u32 dsc_a_cdr_control_2; + + bool serdes_ae_full_rate; + bool serdes_ae_20b_width; +}; + +struct serdes_misc3_params { + u32 misc3_if_select; + u32 misc3_laser_mode; + bool misc3_sgmii; +}; + +int xport_serdes_set_params(struct xport_priv *port, + const struct serdes_params *params, + const struct serdes_misc3_params *m3params); +void xport_serdes_update_m3_params(struct xport_priv *port, + const struct serdes_misc3_params *m3params); +int xport_serdes_pcs_read_reg(struct xport_priv *port, + u16 lane, u16 address); +int xport_serdes_pcs_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask); + +void xport_serdes_lbe_force_enable(struct xport_priv *port); + +void xport_serdes_lbe_force_disable(struct xport_priv *port); + +void xport_serdes_lbe_dont_force(struct xport_priv *port); + +void xport_serdes_lbe_get_forced_state(struct xport_priv *port, + bool *force, bool *forced_value); + +void xport_serdes_shutdown(struct xport_priv *port); + + +extern const struct bcm_enet_mode_ops xport_xlmac_mode_ops; +extern const struct bcm_enet_mode_ops xport_epon_mode_ops; + +enum { + XPORT_PIN_ROGUE1, + XPORT_PIN_RS0, +}; +int xport_switch_pinctrl(struct xport_priv *port, int which); + +#endif /* PORT_XPORT_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.c 2023-09-01 15:04:29.529632893 +0200 @@ -0,0 +1,3201 @@ +#include "port_xport_epon.h" +#include "regs/serdes_regs.h" + +/* + * maximum number of LLID supported by hardware + */ +#define BCM_LLID_COUNT 32 +#define BCM_L2_COUNT BCM_LLID_COUNT + +/* + * maximum number of pending grants per LLID for hardware + */ +#define BCM_MAX_PENDING_GRANTS 16 + +/* + * estimated time from packet xmit to actual hardware tx, used during + * discovery to avoid scheduling packet in the past + */ +#define SOFTWARE_TX_LATENCY_TQ USEC_TO_TQ(20) + +/* + * llid index we force, to ease debugging + */ +#define USER_LLID_IDX 0 +#define BROADCAST_LLID_IDX 31 + +/* + * default burst cap + */ +#define DEFAULT_BURST_CAP 1024 + +/* + * standard MPCP frame destination address + */ +static const u8 mpcp_frame_da[6] = { 0x01, 0x80, 0xc2, 0x00, 0x00, 0x01 }; + +enum epon_stat_type { + EPON_STAT_XPCS_RX, + EPON_STAT_XPCS_RX64, + EPON_STAT_XIF, + EPON_STAT_LIF, + EPON_STAT_EPN, + EPON_STAT_EPN_RAM, + EPON_STAT_EPN_L1_ACC, + EPON_STAT_LOCAL, +}; + +#define GEN_MIB_STAT(m) \ + sizeof(((struct eponmac_mib *)0)->m), \ + offsetof(struct eponmac_mib, m) + +#define GEN_EPN_RAM_STAT(m, llid, port, ram_off) \ + #m, \ + GEN_MIB_STAT(m), \ + ((llid << 24) | (port << 16) | ram_off), \ + EPON_STAT_EPN_RAM, + +#define GEN_LOCAL_STAT(m) \ + #m, \ + GEN_MIB_STAT(m), \ + 0, \ + EPON_STAT_LOCAL, + +const struct bcm_runner_ethtool_stat epon_mib_estat[] = { + { "xpcs_rx_framer_misbrst", GEN_MIB_STAT(xpcs_rx_framer_misbrst), + XPCSRX_RX_FRAMER_MISBRST_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_framer_bd_err", GEN_MIB_STAT(xpcs_rx_framer_bd_err), + XPCSRX_RX_FRAMER_BD_ERR_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_64b66b_ipg_det", GEN_MIB_STAT(xpcs_rx_64b66b_ipg_det), + XPCSRX_RX_64B66B_IPG_DET_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_nque_in", GEN_MIB_STAT(xpcs_rx_fec_nque_in), + XPCSRX_RX_FEC_NQUE_IN_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_nque_out", GEN_MIB_STAT(xpcs_rx_fec_nque_out), + XPCSRX_RX_FEC_NQUE_OUT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_start", GEN_MIB_STAT(xpcs_rx_idle_start), + XPCSRX_RX_IDLE_START_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_stop", GEN_MIB_STAT(xpcs_rx_idle_stop), + XPCSRX_RX_IDLE_STOP_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_cw_fail", GEN_MIB_STAT(xpcs_rx_fec_cw_fail), + XPCSRX_RX_FEC_CW_FAIL_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_cw_tot", GEN_MIB_STAT(xpcs_rx_fec_cw_tot), + XPCSRX_RX_FEC_CW_TOT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_correct", GEN_MIB_STAT(xpcs_rx_fec_correct), + XPCSRX_RX_FEC_CORRECT_CNT_LO_REG, EPON_STAT_XPCS_RX64, }, + { "xpcs_rx_fec_ones_cor", GEN_MIB_STAT(xpcs_rx_fec_ones_cor), + XPCSRX_RX_FEC_ONES_COR_CNT_LO_REG, EPON_STAT_XPCS_RX64, }, + { "xpcs_rx_fec_zeros_cor", GEN_MIB_STAT(xpcs_rx_fec_zeros_cor), + XPCSRX_RX_FEC_ZEROS_COR_CNT_LO_REG, EPON_STAT_XPCS_RX64, }, + { "xpcs_rx_64b66b_fail", GEN_MIB_STAT(xpcs_rx_64b66b_fail), + XPCSRX_RX_64B66B_FAIL_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_frmr_bad_sh", GEN_MIB_STAT(xpcs_rx_frmr_bad_sh), + XPCSRX_RX_FRMR_BAD_SH_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_psudo", GEN_MIB_STAT(xpcs_rx_psudo), + XPCSRX_RX_PSUDO_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_prbs", GEN_MIB_STAT(xpcs_rx_prbs), + XPCSRX_RX_PRBS_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_64b66b_start", GEN_MIB_STAT(xpcs_rx_64b66b_start), + XPCSRX_RX_64B66B_START_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_good_pkt", GEN_MIB_STAT(xpcs_rx_idle_good_pkt), + XPCSRX_RX_IDLE_GOOD_PKT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_err_pkt", GEN_MIB_STAT(xpcs_rx_idle_err_pkt), + XPCSRX_RX_IDLE_ERR_PKT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_64b66b_stop", GEN_MIB_STAT(xpcs_rx_64b66b_stop), + XPCSRX_RX_64B66B_STOP_CNT_REG, EPON_STAT_XPCS_RX, }, + + { "xif_pmc_frame_rx", GEN_MIB_STAT(xif_pmc_frame_rx), + XIF_PMC_FRAME_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_byte_rx", GEN_MIB_STAT(xif_pmc_byte_rx), + XIF_PMC_BYTE_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_runt_rx", GEN_MIB_STAT(xif_pmc_runt_rx), + XIF_PMC_RUNT_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_cw_err_rx", GEN_MIB_STAT(xif_pmc_cw_err_rx), + XIF_PMC_CW_ERR_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_crc8_err_rx", GEN_MIB_STAT(xif_pmc_crc8_err_rx), + XIF_PMC_CRC8_ERR_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_data_frm_tx", GEN_MIB_STAT(xif_xpn_data_frm), + XIF_XPN_DATA_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_data_byte_tx", GEN_MIB_STAT(xif_xpn_data_byte), + XIF_XPN_DATA_BYTE_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_mpcp_frm_tx", GEN_MIB_STAT(xif_xpn_mpcp_frm), + XIF_XPN_MPCP_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_oam_frm_tx", GEN_MIB_STAT(xif_xpn_oam_frm), + XIF_XPN_OAM_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_oam_byte_tx", GEN_MIB_STAT(xif_xpn_oam_byte), + XIF_XPN_OAM_BYTE_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_oversize_frm_tx", GEN_MIB_STAT(xif_xpn_oversize_frm), + XIF_XPN_OVERSIZE_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_sec_abort_frm_rx", GEN_MIB_STAT(xif_sec_abort_frm), + XIF_SEC_ABORT_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_tx_neg_event", GEN_MIB_STAT(xif_pmc_tx_neg_event), + XIF_PMC_TX_NEG_EVENT_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_idle_pkt", GEN_MIB_STAT(xif_xpn_idle_pkt), + XIF_XPN_IDLE_PKT_CNT_REG, EPON_STAT_XIF, }, + + { "lif_rx_line_code_err_cnt", GEN_MIB_STAT(lif_rx_line_code_err_cnt), + LIF_RX_LINE_CODE_ERR_CNT_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_mpcp_frm", GEN_MIB_STAT(lif_rx_agg_mpcp_frm), + LIF_RX_AGG_MPCP_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_good_frm", GEN_MIB_STAT(lif_rx_agg_good_frm), + LIF_RX_AGG_GOOD_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_good_byte", GEN_MIB_STAT(lif_rx_agg_good_byte), + LIF_RX_AGG_GOOD_BYTE_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_undersz_frm", GEN_MIB_STAT(lif_rx_agg_undersz_frm), + LIF_RX_AGG_UNDERSZ_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_oversz_frm", GEN_MIB_STAT(lif_rx_agg_oversz_frm), + LIF_RX_AGG_OVERSZ_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_crc8_frm", GEN_MIB_STAT(lif_rx_agg_crc8_frm), + LIF_RX_AGG_CRC8_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_fec_frm", GEN_MIB_STAT(lif_rx_agg_fec_frm), + LIF_RX_AGG_FEC_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_fec_byte", GEN_MIB_STAT(lif_rx_agg_fec_byte), + LIF_RX_AGG_FEC_BYTE_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_fec_exc_err_frm", + GEN_MIB_STAT(lif_rx_agg_fec_exc_err_frm), + LIF_RX_AGG_FEC_EXC_ERR_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_nonfec_good_frm", + GEN_MIB_STAT(lif_rx_agg_nonfec_good_frm), + LIF_RX_AGG_NONFEC_GOOD_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_nonfec_good_byte", + GEN_MIB_STAT(lif_rx_agg_nonfec_good_byte), + LIF_RX_AGG_NONFEC_GOOD_BYTE_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_bytes", GEN_MIB_STAT(lif_rx_agg_err_bytes), + LIF_RX_AGG_ERR_BYTES_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_zeroes", GEN_MIB_STAT(lif_rx_agg_err_zeroes), + LIF_RX_AGG_ERR_ZEROES_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_no_err_blks", GEN_MIB_STAT(lif_rx_agg_no_err_blks), + LIF_RX_AGG_NO_ERR_BLKS_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_cor_blks", GEN_MIB_STAT(lif_rx_agg_cor_blks), + LIF_RX_AGG_COR_BLKS_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_uncor_blks", GEN_MIB_STAT(lif_rx_agg_uncor_blks), + LIF_RX_AGG_UNCOR_BLKS_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_ones", GEN_MIB_STAT(lif_rx_agg_err_ones), + LIF_RX_AGG_ERR_ONES_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_frm", GEN_MIB_STAT(lif_rx_agg_err_frm), + LIF_RX_AGG_ERR_FRM_REG, EPON_STAT_LIF, }, + { "lif_tx_pkt_cnt", GEN_MIB_STAT(lif_tx_pkt_cnt), + LIF_TX_PKT_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_byte_cnt", GEN_MIB_STAT(lif_tx_byte_cnt), + LIF_TX_BYTE_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_non_fec_pkt_cnt", GEN_MIB_STAT(lif_tx_non_fec_pkt_cnt), + LIF_TX_NON_FEC_PKT_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_non_fec_byte_cnt", GEN_MIB_STAT(lif_tx_non_fec_byte_cnt), + LIF_TX_NON_FEC_BYTE_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_fec_pkt_cnt", GEN_MIB_STAT(lif_tx_fec_pkt_cnt), + LIF_TX_FEC_PKT_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_fec_byte_cnt", GEN_MIB_STAT(lif_tx_fec_byte_cnt), + LIF_TX_FEC_BYTE_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_fec_blk_cnt", GEN_MIB_STAT(lif_tx_fec_blk_cnt), + LIF_TX_FEC_BLK_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_mpcp_pkt_cnt", GEN_MIB_STAT(lif_tx_mpcp_pkt_cnt), + LIF_TX_MPCP_PKT_CNT_REG, EPON_STAT_LIF, }, + + { GEN_EPN_RAM_STAT(epn00_rx_bytes, 0, 0, 0) }, + { GEN_EPN_RAM_STAT(epn00_rx_fcs, 0, 0, 1) }, + { GEN_EPN_RAM_STAT(epn00_rx_oam, 0, 0, 2) }, + { GEN_EPN_RAM_STAT(epn00_rx_gate, 0, 0, 3) }, + { GEN_EPN_RAM_STAT(epn00_rx_64, 0, 0, 4) }, + { GEN_EPN_RAM_STAT(epn00_rx_65_127, 0, 0, 5) }, + { GEN_EPN_RAM_STAT(epn00_rx_128_255, 0, 0, 6) }, + { GEN_EPN_RAM_STAT(epn00_rx_256_511, 0, 0, 7) }, + { GEN_EPN_RAM_STAT(epn00_rx_512_1023, 0, 0, 8) }, + { GEN_EPN_RAM_STAT(epn00_rx_1024_1518, 0, 0, 9) }, + { GEN_EPN_RAM_STAT(epn00_rx_1519_2047, 0, 0, 10) }, + { GEN_EPN_RAM_STAT(epn00_rx_2048_4095, 0, 0, 11) }, + { GEN_EPN_RAM_STAT(epn00_rx_4096_9216, 0, 0, 12) }, + { GEN_EPN_RAM_STAT(epn00_rx_gt_9216, 0, 0, 13) }, + { GEN_EPN_RAM_STAT(epn00_rx_oversize, 0, 0, 14) }, + { GEN_EPN_RAM_STAT(epn00_rx_bcast, 0, 0, 15) }, + { GEN_EPN_RAM_STAT(epn00_rx_mcast, 0, 0, 16) }, + { GEN_EPN_RAM_STAT(epn00_rx_unicast, 0, 0, 17) }, + { GEN_EPN_RAM_STAT(epn00_rx_undersized, 0, 0, 18) }, + { GEN_EPN_RAM_STAT(epn00_rx_oam_bytes, 0, 0, 19) }, + { GEN_EPN_RAM_STAT(epn00_rx_register, 0, 0, 20) }, + + { GEN_EPN_RAM_STAT(epn00_tx_bytes, 0, 1, 0) }, + { GEN_EPN_RAM_STAT(epn00_tx_oam, 0, 1, 1) }, + { GEN_EPN_RAM_STAT(epn00_tx_report, 0, 1, 2) }, + { GEN_EPN_RAM_STAT(epn00_tx_64, 0, 1, 3) }, + { GEN_EPN_RAM_STAT(epn00_tx_65_127, 0, 1, 4) }, + { GEN_EPN_RAM_STAT(epn00_tx_128_255, 0, 1, 5) }, + { GEN_EPN_RAM_STAT(epn00_tx_256_511, 0, 1, 6) }, + { GEN_EPN_RAM_STAT(epn00_tx_512_1023, 0, 1, 7) }, + { GEN_EPN_RAM_STAT(epn00_tx_1024_1518, 0, 1, 8) }, + { GEN_EPN_RAM_STAT(epn00_tx_1519_2047, 0, 1, 9) }, + { GEN_EPN_RAM_STAT(epn00_tx_2048_4095, 0, 1, 10) }, + { GEN_EPN_RAM_STAT(epn00_tx_4096_9216, 0, 1, 11) }, + { GEN_EPN_RAM_STAT(epn00_tx_gt_9216, 0, 1, 12) }, + { GEN_EPN_RAM_STAT(epn00_tx_oam_bytes, 0, 1, 13) }, + { GEN_EPN_RAM_STAT(epn00_tx_bcast, 0, 1, 14) }, + { GEN_EPN_RAM_STAT(epn00_tx_mcast, 0, 1, 15) }, + { GEN_EPN_RAM_STAT(epn00_tx_unicast, 0, 1, 16) }, + { "epn00_unused_tq", GEN_MIB_STAT(epn00_unused_tq), + 0, EPN_UNUSED_TQ_CNTx_0_7_REG(0), }, + { "epn00_l1_acc_bytes", GEN_MIB_STAT(epn00_l1_acc_bytes), + 0, EPON_STAT_EPN_L1_ACC, }, + + { GEN_EPN_RAM_STAT(epn24_rx_bytes, 24, 0, 0) }, + { GEN_EPN_RAM_STAT(epn24_rx_fcs, 24, 0, 1) }, + { GEN_EPN_RAM_STAT(epn24_rx_bcast, 24, 0, 15) }, + { GEN_EPN_RAM_STAT(epn24_rx_mcast, 24, 0, 16) }, + { GEN_EPN_RAM_STAT(epn25_rx_bytes, 25, 0, 0) }, + { GEN_EPN_RAM_STAT(epn25_rx_fcs, 25, 0, 1) }, + { GEN_EPN_RAM_STAT(epn25_rx_bcast, 25, 0, 15) }, + { GEN_EPN_RAM_STAT(epn25_rx_mcast, 25, 0, 16) }, + { GEN_EPN_RAM_STAT(epn26_rx_bytes, 26, 0, 0) }, + { GEN_EPN_RAM_STAT(epn26_rx_fcs, 26, 0, 1) }, + { GEN_EPN_RAM_STAT(epn26_rx_bcast, 26, 0, 15) }, + { GEN_EPN_RAM_STAT(epn26_rx_mcast, 26, 0, 16) }, + { GEN_EPN_RAM_STAT(epn27_rx_bytes, 27, 0, 0) }, + { GEN_EPN_RAM_STAT(epn27_rx_fcs, 27, 0, 1) }, + { GEN_EPN_RAM_STAT(epn27_rx_bcast, 27, 0, 15) }, + { GEN_EPN_RAM_STAT(epn27_rx_mcast, 27, 0, 16) }, + { GEN_EPN_RAM_STAT(epn28_rx_bytes, 28, 0, 0) }, + { GEN_EPN_RAM_STAT(epn28_rx_fcs, 28, 0, 1) }, + { GEN_EPN_RAM_STAT(epn28_rx_bcast, 28, 0, 15) }, + { GEN_EPN_RAM_STAT(epn28_rx_mcast, 28, 0, 16) }, + { GEN_EPN_RAM_STAT(epn29_rx_bytes, 29, 0, 0) }, + { GEN_EPN_RAM_STAT(epn29_rx_fcs, 29, 0, 1) }, + { GEN_EPN_RAM_STAT(epn29_rx_bcast, 29, 0, 15) }, + { GEN_EPN_RAM_STAT(epn29_rx_mcast, 29, 0, 16) }, + { GEN_EPN_RAM_STAT(epn30_rx_bytes, 30, 0, 0) }, + { GEN_EPN_RAM_STAT(epn30_rx_fcs, 30, 0, 1) }, + { GEN_EPN_RAM_STAT(epn30_rx_bcast, 30, 0, 15) }, + { GEN_EPN_RAM_STAT(epn30_rx_mcast, 30, 0, 16) }, + { GEN_EPN_RAM_STAT(epn31_rx_bytes, 31, 0, 0) }, + { GEN_EPN_RAM_STAT(epn31_rx_fcs, 31, 0, 1) }, + { GEN_EPN_RAM_STAT(epn31_rx_bcast, 31, 0, 15) }, + { GEN_EPN_RAM_STAT(epn31_rx_mcast, 31, 0, 16) }, + + { "epn_unmap_big", GEN_MIB_STAT(epn_unmap_big), + EPN_UNMAP_BIG_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_frame", GEN_MIB_STAT(epn_unmap_frame), + EPN_UNMAP_FRAME_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_fcs", GEN_MIB_STAT(epn_unmap_fcs), + EPN_UNMAP_FCS_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_gate", GEN_MIB_STAT(epn_unmap_gate), + EPN_UNMAP_GATE_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_oam", GEN_MIB_STAT(epn_unmap_oam), + EPN_UNMAP_OAM_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_small", GEN_MIB_STAT(epn_unmap_small), + EPN_UNMAP_SMALL_CNT_REG, EPON_STAT_EPN, }, + + { GEN_LOCAL_STAT(reg_mpcp_rx) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_invalid) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_unk_opcode) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc_info_mismatch) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc_late) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc_last_slot) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_for_other) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_unk_flag) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_dereg) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_nack) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_timeout) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_other_err) }, + { GEN_LOCAL_STAT(reg_mpcp_tx_reg_req) }, + { GEN_LOCAL_STAT(reg_mpcp_tx_reg_ack) }, +}; + +/* + * + */ +static const struct serdes_params serdes_params_10g_1g = { + .tx_pll_vco_div2 = 0x0, + .rx_pll_vco_div2 = 0x0, + .tx_pll_vco_div4 = 0x0, + .rx_pll_vco_div4 = 0x0, + .rx_pll_id = serdes_PLL_1, + .tx_pll_id = serdes_PLL_0, + + .tx_pll_force_kvh_bw = 0x1, + .rx_pll_force_kvh_bw = 0x1, + .tx_pll_kvh_force = 0x1, + .rx_pll_kvh_force = 0x1, + + .tx_pll_2rx_bw = 0x0, + .rx_pll_2rx_bw = 0x0, + + .tx_pll_fracn_sel = 0x1, + .rx_pll_fracn_sel = 0x1, + + .tx_pll_ditheren = 0x1, + .rx_pll_ditheren = 0x1, + + .rx_pll_fracn_div = 0x10000, + .rx_pll_fracn_ndiv = 0x0ce, + + .tx_pll_fracn_div = 0x00000, + .tx_pll_fracn_ndiv = 0x0c8, + + .rx_pll_mode = 0x5, + .tx_pll_mode = 0x5, + + .rx_tx_rate_ratio = 0x5, + + .rx_pon_mac_ctrl = 0x7, + .tx_pon_mac_ctrl = 0x0, + .tx_sync_e_ctrl = 0x0, + + .rx_osr_mode = 0x0, + .tx_osr_mode = 0x7, + + .do_rx_pi_spacing = true, + .clk90_offset = 32, + .p1_offset = 0, + .dsc_a_cdr_control_2 = 0x030, + + .do_pll_charge_pump = true, + .do_pll_charge_pump_10g = true, + .do_vga_rf = true, + .do_ae = false, + .do_sigdetect = false, + .serdes_ae_full_rate = false, + .serdes_ae_20b_width = false, +}; + +static const struct serdes_misc3_params serdes_m3params_10g_1g = { + .misc3_if_select = 5, + .misc3_laser_mode = 0, +}; + +/* + * + */ +static u32 extract_mac_addr_lo(const u8 *addr) +{ + return ((u32)addr[2] << 24) | + ((u32)addr[3] << 16) | + ((u32)addr[4] << 8) | + ((u32)addr[5]); +} + +/* + * + */ +static u32 extract_mac_addr_hi(const u8 *addr) +{ + return ((u32)addr[0] << 8) | addr[1]; +} + +/* + * + */ +static u32 get_register_req_data_size(bool include_preambles) +{ + size_t len = 0; + + if (include_preambles) + len += PREAMBLE_LEN_BYTES; + /* ethernet payload cannot be smaller than 60 or it has to be + * padded */ + len += max_t(size_t, + ETH_HLEN + + sizeof (struct mpcp_hdr) + + sizeof (struct mpcp_register_req), + ETH_ZLEN); + if (include_preambles) { + len += ETH_FCS_LEN; + len += IPG_BYTES_1G; + } + return len; +} + +/* + * + */ +static u32 get_register_req_data_duration(struct xport_epon_priv *mode) +{ + if (mode->up_speed == 1000) + return BYTES_TO_TQ_1G(get_register_req_data_size(true)); + else { + /* FIXME: implement */ + BUG(); + } +} + +/* + * + */ +static u16 get_broadcast_llid(struct xport_epon_priv *mode) +{ + if (mode->down_speed == 10000) + return BROADCAST_LLID_10G; + else + return BROADCAST_LLID_1G; +} + +/* + * + */ +static u16 get_disc_info_caps(struct xport_epon_priv *mode, u16 *mask) +{ + u16 value = 0; + + /* OLT must support our upstream speed */ + if (mode->up_speed == 1000) { + if (mask) + *mask &= ~MPCP_DISCINFO_1G_CAP; + value |= MPCP_DISCINFO_1G_CAP; + } else { + if (mask) + *mask &= ~MPCP_DISCINFO_10G_CAP; + value |= MPCP_DISCINFO_10G_CAP; + } + + /* only use discovery window for our upstream speed */ + if (mode->up_speed == 1000) { + if (mask) + *mask &= ~MPCP_DISCINFO_1G_WINDOW; + value |= MPCP_DISCINFO_1G_WINDOW; + } else { + if (mask) + *mask &= ~MPCP_DISCINFO_10G_WINDOW; + value |= MPCP_DISCINFO_10G_WINDOW; + } + return value; +} + +/* + * + */ +static void epon_reset_modules(struct xport_epon_priv *mode, + bool active, u32 mask) +{ + u32 val; + + val = epon_top_reg_readl(mode, EPON_TOP_RESET_REG); + /* reset is active low */ + if (!active) + val |= mask; + else + val &= ~mask; + epon_top_reg_writel(mode, EPON_TOP_RESET_REG, val); +} + +/* + * + */ +static int xpcs_rx_init(struct xport_epon_priv *mode) +{ + u32 val; + size_t i; + + /* release xpcs rx reset */ + epon_reset_modules(mode, false, RESET_XPCSRXRST_N_MASK); + msleep(20); + + val = epon_xpcsrx_reg_readl(mode, XPCSRX_RX_RST_REG); + val |= RX_RST_CFGXPCSRXCLK161RSTN_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_RST_REG, val); + udelay(10); + + /* poll until ready */ + for (i = 0; i < 100; i++) { + val = epon_xpcsrx_reg_readl(mode, XPCSRX_RX_RAM_ECC_INT_STAT_REG); + if (val & RX_RAM_ECC_INT_STAT_INTRXIDLERAMINITDONE_MASK) + break; + msleep(1); + } + + if (!(val & RX_RAM_ECC_INT_STAT_INTRXIDLERAMINITDONE_MASK)) { + netdev_err(mode->port->priv->netdev, + "xpcsrx RAM init failed\n"); + return 1; + } + + /* start with FEC enabled */ + val = RX_FRAMER_CTL_CFGXPCSRXFRMREN_MASK | + RX_FRAMER_CTL_CFGXPCSRXFRAMEFEC_MASK | + RX_FRAMER_CTL_CFGXPCSRXFRMREBDVLDEN_MASK | + RX_FRAMER_CTL_CFGXPCSRXFRMRSPULKEN_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_FRAMER_CTL_REG, val); + + val = RX_FEC_CTL_CFGXPCSRXFECEN_MASK | + RX_FEC_CTL_CFGXPCSRXFECIDLEINS_MASK | + RX_FEC_CTL_CFGXPCSRXFECFAILBLKSH0_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_FEC_CTL_REG, val); + + val = RX_INT_STAT_INTRXIDLEDAJIT_MASK | + RX_INT_STAT_INTRXFRMRMISBRST_MASK | + RX_INT_STAT_INTRXIDLESOPEOPGAPBIG_MASK | + RX_INT_STAT_INTRXIDLEFRCINS_MASK | + RX_INT_STAT_INTRX64B66BMINIPGERR_MASK | + RX_INT_STAT_INTRXFECNQUECNTNEQ_MASK | + RX_INT_STAT_INTRXIDLEFIFOUNDRUN_MASK | + RX_INT_STAT_INTRXIDLEFIFOOVRRUN_MASK | + RX_INT_STAT_INTRXFECHIGHCOR_MASK | + RX_INT_STAT_INTRXFECDECSTOPONERR_MASK | + RX_INT_STAT_INTRXFECDECPASS_MASK | + RX_INT_STAT_INTRXSTATFRMRHIGHBER_MASK | + RX_INT_STAT_INTRXFRMREXITBYSP_MASK | + RX_INT_STAT_INTRXFRMRBADSHMAX_MASK | + RX_INT_STAT_INTRXDSCRAMBURSTSEQOUT_MASK | + RX_INT_STAT_INTRXTESTPSUDOLOCK_MASK | + RX_INT_STAT_INTRXTESTPSUDOTYPE_MASK | + RX_INT_STAT_INTRXTESTPSUDOERR_MASK | + RX_INT_STAT_INTRXTESTPRBSLOCK_MASK | + RX_INT_STAT_INTRXTESTPRBSERR_MASK | + RX_INT_STAT_INTRXFECPSISTDECFAIL_MASK | + RX_INT_STAT_INTRXFRAMERBADSH_MASK | + RX_INT_STAT_INTRXFRAMERCWLOSS_MASK | + RX_INT_STAT_INTRXFRAMERCWLOCK_MASK | + RX_INT_STAT_INTRXFECDECFAIL_MASK | + RX_INT_STAT_INTRX64B66BDECERR_MASK | + RX_INT_STAT_INTRXFRMRNOLOCKLOS_MASK | + RX_INT_STAT_INTRXFRMRROGUE_MASK | + RX_INT_STAT_INT_REGS_ERR_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_INT_STAT_REG, val); + + return 0; +} + +/* + * + */ +static void xif_set_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int llid, + bool enabled) +{ + u32 val; + + val = epon_xif_reg_readl(mode, XIF_LLIDx_0_31_REG(llid_idx)); + val &= ~XIF_LLIDx_0_31_CFGONULLID0_MASK; + val |= llid << XIF_LLIDx_0_31_CFGONULLID0_SHIFT; + if (enabled) + val |= (1 << (16 + XIF_LLIDx_0_31_CFGONULLID0_SHIFT)); + else + val &= ~(1 << (16 + XIF_LLIDx_0_31_CFGONULLID0_SHIFT)); + epon_xif_reg_writel(mode, XIF_LLIDx_0_31_REG(llid_idx), val); +} + +/* + * + */ +static u32 xif_get_local_mpcp_time(struct xport_epon_priv *mode) +{ + return epon_xif_reg_readl(mode, XIF_MPCP_TIME_REG); +} + +/* + * + */ +static int xif_data_port_write(struct xport_epon_priv *mode, + unsigned int port, + u32 addr) +{ + u32 val; + size_t i; + + val = (addr << XIF_PORT_COMMAND_PORTADDRESS_SHIFT) | + (1 << XIF_PORT_COMMAND_PORTOPCODE_SHIFT) | + (port << XIF_PORT_COMMAND_PORTSELECT_SHIFT); + + epon_xif_reg_writel(mode, XIF_PORT_COMMAND_REG, val); + + for (i = 0; i < 100; i++) { + val = epon_xif_reg_readl(mode, XIF_PORT_COMMAND_REG); + if ((val & XIF_PORT_COMMAND_DATAPORTBUSY_MASK)) + break; + udelay(5); + } + + if ((val & XIF_PORT_COMMAND_DATAPORTBUSY_MASK)) { + netdev_err(mode->port->priv->netdev, + "xif data port busy does not clear\n"); + return 1; + } + + return 0; +} + +/* + * + */ +static void xif_set_down_key(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int key_idx, + const uint8_t key[16], + const uint8_t sci[8]) +{ + u32 val; + + BUG_ON(key_idx > 1); + + /* make sure decryption is enabled */ + val = epon_xif_reg_readl(mode, XIF_CTL_REG); + val &= ~XIF_CTL_RXENCRYPTMODE_MASK; + val |= XIF_CTL_RXENCRYPTEN_MASK; + epon_xif_reg_writel(mode, XIF_CTL_REG, val); + + /* load the key */ + memcpy(&val, key + 0, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(3), val); + memcpy(&val, key + 4, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(2), val); + memcpy(&val, key + 8, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(1), val); + memcpy(&val, key + 12, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(0), val); + + memcpy(&val, sci, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(5), val); + memcpy(&val, sci + 4, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(4), val); + + /* enable decrypt for this key */ + val = 1; + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(7), val); + + val = (llid_idx << 1) | key_idx; + /* port 0 => rx key */ + xif_data_port_write(mode, 0, val); +} + +/* + * + */ +static void +xif_get_llid_last_rx_encrypt(struct xport_epon_priv *mode, + unsigned int llid_idx, + bool *last_encrypted, + unsigned int *last_encrypted_key_id) +{ + u32 val; + + val = epon_xif_reg_readl(mode, XIF_SECRX_ENCRYPT_REG); + *last_encrypted = (val & (1 << llid_idx)); + + val = epon_xif_reg_readl(mode, XIF_SECRX_KEYNUM_REG); + *last_encrypted_key_id = (val & (1 << llid_idx)) ? 1 : 0; +} + +/* + * + */ +static int xif_init(struct xport_epon_priv *mode) +{ + u32 val; + size_t i; + + /* release xif reset */ + epon_reset_modules(mode, false, RESET_XIFRST_N_MASK); + msleep(20); + + /* xif control, RAM init */ + val = XIF_CTL_XIFDTPORTRSTN_MASK; + epon_xif_reg_writel(mode, XIF_CTL_REG, val); + udelay(10); + + for (i = 0; i < 1000; i++) { + val = epon_xif_reg_readl(mode, XIF_CTL_REG); + if (!(val & XIF_CTL_XIFNOTRDY_MASK)) + break; + msleep(1); + } + + if ((val & XIF_CTL_XIFNOTRDY_MASK)) { + netdev_err(mode->port->priv->netdev, + "xif RAM init failed\n"); + return 1; + } + + val |= XIF_CTL_CFGPMCRXENCRC8CHK_MASK; + val |= XIF_CTL_PMCRXRSTN_MASK; + val |= XIF_CTL_SECRXRSTN_MASK; + epon_xif_reg_writel(mode, XIF_CTL_REG, val); + + /* oversize */ + val = epon_xif_reg_readl(mode, XIF_XPN_OVERSIZE_THRESH_REG); + val &= ~XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_MASK; + val |= 10000 << XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_SHIFT; + epon_xif_reg_writel(mode, XIF_XPN_OVERSIZE_THRESH_REG, val); + + /* interrupt status */ + val = XIF_INT_STATUS_SECRXRPLYPRTCTABRTINT_MASK | + XIF_INT_STATUS_SECTXPKTNUMMAXINT_MASK | + XIF_INT_STATUS_TSFULLUPDINT_MASK | + XIF_INT_STATUS_TXHANGINT_MASK | + XIF_INT_STATUS_NEGTIMEINT_MASK | + XIF_INT_STATUS_PMCTSJTTRINT_MASK | + XIF_INT_STATUS_SECRXOUTFFOVRFLWINT_MASK; + epon_xif_reg_writel(mode, XIF_INT_STATUS_REG, val); + + if (mode->down_speed == 10000) { + if (xpcs_rx_init(mode)) + return 1; + } + + if (mode->up_speed == 10000) { + /* FIXME: implement */ + BUG(); + } + + return 0; +} + +/* + * + */ +static void lif_set_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int llid, + bool enabled) +{ + u32 val; + u32 reg; + + switch (llid_idx) { + case 0 ... 7: + reg = LIF_LLIDx_0_7_REG(llid_idx); + break; + case 16 ... 23: + reg = LIF_LLIDx_16_23_REG(llid_idx); + break; + case 24 ... 31: + reg = LIF_LLIDx_24_31_REG(llid_idx); + break; + default: + BUG(); + break; + } + + val = epon_lif_reg_readl(mode, reg); + val &= ~LIF_LLIDx_0_7_CFGLLID0_MASK; + val |= llid << LIF_LLIDx_0_7_CFGLLID0_SHIFT; + if (enabled) + val |= (1 << (16 + LIF_LLIDx_0_7_CFGLLID0_SHIFT)); + else + val &= ~(1 << (16 + LIF_LLIDx_0_7_CFGLLID0_SHIFT)); + epon_lif_reg_writel(mode, reg, val); +} + +/* + * + */ +static void lif_set_laser_normal_op(struct xport_epon_priv *mode, + bool normal_op) +{ + u32 val; + + val = epon_lif_reg_readl(mode, LIF_PON_CONTROL_REG); + if (normal_op) + val |= LIF_PON_CONTROL_CFLASEREN_MASK; + else + val &= ~LIF_PON_CONTROL_CFLASEREN_MASK; + epon_lif_reg_writel(mode, LIF_PON_CONTROL_REG, val); +} + +/* + * + */ +static void lif_set_idle_time(struct xport_epon_priv *mode, + unsigned int front, + unsigned int back) +{ + u32 val; + + /* 'front' idle time before sending (for non FEC mode) */ + val = front << LIF_LASER_OFF_IDLE_CFTXINITIDLE_SHIFT; + /* turn off the laser 'back' tq before end of grant */ + val |= (1 << 7) | (back << LIF_LASER_OFF_IDLE_CFTXLASEROFFDELTA_SHIFT); + epon_lif_reg_writel(mode, LIF_LASER_OFF_IDLE_REG, val); + + /* 'front' idle time before sending (for FEC mode) */ + val = front << LIF_FEC_INIT_IDLE_CFTXFECINITIDLE_SHIFT; + epon_lif_reg_writel(mode, LIF_FEC_INIT_IDLE_REG, val); + + /* fixup MPCP offset so that it corresponds to first bytes of + * DA */ + val = front + BYTES_TO_TQ_1G(PREAMBLE_LEN_BYTES); + epon_lif_reg_writel(mode, LIF_SEC_UP_MPCP_OFFSET_REG, val); +} + +/* + * + */ +static int lif_init(struct xport_epon_priv *mode) +{ + u32 val; + + /* release lif reset */ + epon_reset_modules(mode, false, RESET_LIFRST_N_MASK); + msleep(20); + + /* pon control */ + val = LIF_PON_CONTROL_CFGRXDATABITFLIP_MASK | + LIF_PON_CONTROL_CFPPSCLKRBC_MASK; + if (!mode->laser_active_hi) { + /* XXX: this is not a typo, polarity is reversed */ + val |= LIF_PON_CONTROL_CFTXLASERONACTHI_MASK; + } + epon_lif_reg_writel(mode, LIF_PON_CONTROL_REG, val); + + /* interop control */ + val = (2 << LIF_PON_INTER_OP_CONTROL_CFTXIPGCNT_SHIFT) | + (6 << LIF_PON_INTER_OP_CONTROL_CFTXPIPEDELAY_SHIFT); + epon_lif_reg_writel(mode, LIF_PON_INTER_OP_CONTROL_REG, val); + + /* fec control, globally enable FEC, still needs to be enabled + * per llid */ + val = LIF_FEC_CONTROL_CFFECTXENABLE_MASK | + LIF_FEC_CONTROL_CFFECTXFECPERLLID_MASK | + LIF_FEC_CONTROL_CFFECRXENABLE_MASK; + epon_lif_reg_writel(mode, LIF_FEC_CONTROL_REG, val); + + /* security control */ + val = epon_lif_reg_readl(mode, LIF_SEC_CONTROL_REG); + val |= LIF_SEC_CONTROL_SECDNRSTN_PRE_MASK; + val |= LIF_SEC_CONTROL_SECUPRSTN_PRE_MASK; + epon_lif_reg_writel(mode, LIF_SEC_CONTROL_REG, val); + + /* pon control, enable tx only */ + val = epon_lif_reg_readl(mode, LIF_PON_CONTROL_REG); + val |= LIF_PON_CONTROL_LIFTXRSTN_PRE_MASK; + val |= LIF_PON_CONTROL_LIFTXEN_MASK; + epon_lif_reg_writel(mode, LIF_PON_CONTROL_REG, val); + + /* clear all interrupts */ + val = LIF_INT_STATUS_INT_SOP_SFEC_IPG_VIOLATION_MASK | + LIF_INT_STATUS_LASERONMAX_MASK | + LIF_INT_STATUS_LASEROFF_MASK | + LIF_INT_STATUS_SECDNREPLAYPROTCTABORT_MASK | + LIF_INT_STATUS_SECUPPKTNUMOVERFLOW_MASK | + LIF_INT_STATUS_INTLASEROFFDURBURST_MASK | + LIF_INT_STATUS_INTRXBERTHRESHEXC_MASK | + LIF_INT_STATUS_INTFECRXFECRECVSTATUS_MASK | + LIF_INT_STATUS_INTFECRXCORERRFIFOFULLSTATUS_MASK | + LIF_INT_STATUS_INTFECRXCORERRFIFOUNEXPEMPTY_MASK | + LIF_INT_STATUS_INTFECBUFPOPEMPTYPUSH_MASK | + LIF_INT_STATUS_INTFECBUFPOPEMPTYNOPUSH_MASK | + LIF_INT_STATUS_INTFECBUFPUSHFULL_MASK | + LIF_INT_STATUS_INTUPTIMEFULLUPDSTAT_MASK | + LIF_INT_STATUS_INTFROUTOFALIGNSTAT_MASK | + LIF_INT_STATUS_INTGRNTSTARTTIMELAGSTAT_MASK | + LIF_INT_STATUS_INTABORTRXFRMSTAT_MASK | + LIF_INT_STATUS_INTNORXCLKSTAT_MASK | + LIF_INT_STATUS_INTRXMAXLENERRSTAT_MASK | + LIF_INT_STATUS_INTRXERRAFTALIGNSTAT_MASK | + LIF_INT_STATUS_INTRXSYNCHACQSTAT_MASK | + LIF_INT_STATUS_INTRXOUTOFSYNCHSTAT_MASK; + epon_lif_reg_writel(mode, LIF_INT_STATUS_REG, val); + + /* enable laser monitoring interrupt */ + val = LIF_INT_STATUS_LASERONMAX_MASK; + epon_lif_reg_writel(mode, LIF_INT_MASK_REG, val); + + /* setup laser monitoring threshold */ + val = USEC_TO_TQ(250 * 1000); + epon_lif_reg_writel(mode, LIF_LSR_MON_A_MAX_THR_REG, val); + + /* enable laser monitoring */ + val = LIF_LSR_MON_A_CTRL_PBILASERMONRSTA_N_PRE_MASK; + if (mode->laser_active_hi) + val |= LIF_LSR_MON_A_CTRL_CFGLSRMONACTHI_MASK; + epon_lif_reg_writel(mode, LIF_LSR_MON_A_CTRL_REG, val); + + if (mode->down_speed == 1000) { + /* FIXME: implement */ + BUG(); + } + + return 0; +} + +/* + * + */ +static void epon_hw_set_idle_time(struct xport_epon_priv *mode, + unsigned int laser_on_time, + unsigned int sync_time, + unsigned int laser_off_time, + bool for_discovery) +{ + unsigned int front, back, total; + unsigned int timestamp_off; + u32 val; + + /* + * sanity check, don't go below what hardware can do + */ + if (laser_on_time < DEF_LASER_ON_TIME) + laser_on_time = DEF_LASER_ON_TIME; + if (laser_off_time < DEF_LASER_OFF_TIME) + laser_off_time = DEF_LASER_OFF_TIME; + + front = sync_time + laser_on_time; + back = laser_off_time; + total = front + back; + + switch (mode->up_speed) { + case 1000: + lif_set_idle_time(mode, front, back); + break; + case 10000: + /* FIXME: implement */ + BUG(); + break; + } + + timestamp_off = BYTES_TO_TQ_1G(PREAMBLE_LEN_BYTES) + front; + val = front << UP_TIME_STAMP_OFF_TIMESTAMPOFFSETFEC_SHIFT; + val |= front << UP_TIME_STAMP_OFF_TIMESTAMPOFFSET_SHIFT; + epon_epn_reg_writel(mode, EPN_UP_TIME_STAMP_OFF_REG, val); + + if (for_discovery) { + val = total << DISC_GRANT_OVR_HD_DISCGNTOVRHD_SHIFT; + epon_epn_reg_writel(mode, EPN_DISC_GRANT_OVR_HD_REG, val); + + /* note: bcm driver accounts FEC here */ + val = (total + get_register_req_data_duration(mode)) << + DN_DISCOVERY_SIZE_CFGDISCSIZE_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_DISCOVERY_SIZE_REG, val); + } else { + val = (total << GRANT_OVR_HD_GNTOVRHDFEC_SHIFT) | + (total << GRANT_OVR_HD_GNTOVRHD_SHIFT); + epon_epn_reg_writel(mode, EPN_GRANT_OVR_HD_REG, val); + } +} + +/* + * set laser on/off + sync time to use in normal operation + */ +static void epon_hw_set_normal_idle_time(struct xport_epon_priv *mode, + unsigned int laser_on_time, + unsigned int sync_time, + unsigned int laser_off_time) +{ + epon_hw_set_idle_time(mode, + laser_on_time, + sync_time, + laser_off_time, + false); +} + +/* + * set laser on/off + sync time to use during discovery + */ +static void epon_hw_set_disc_idle_time(struct xport_epon_priv *mode, + unsigned int laser_on_time, + unsigned int sync_time, + unsigned int laser_off_time) +{ + epon_hw_set_idle_time(mode, + laser_on_time, + sync_time, + laser_off_time, + true); +} + +/* + * + */ +static void epn_init_l2_sizes(struct xport_epon_priv *mode) +{ + /* FIXME: this depends on reporting type */ + const u32 l2_size = 824; + u32 start_addr; + size_t i; + + start_addr = 0; + for (i = 0; i < 8; i++) { + u32 end_addr, val; + + end_addr = start_addr + (l2_size >> 2); + val = (end_addr << TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUEEND0_SHIFT) | + (start_addr << TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUESTART0_SHIFT); + epon_epn_reg_writel(mode, + EPN_TX_L2S_QUE_CONFIGx_0_7_REG(i), + val); + start_addr = end_addr + 1; + } + + for (i = 8; i < 32; i++) { + u32 end_addr, val; + + end_addr = start_addr + (l2_size >> 2); + val = (end_addr << TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUEEND8_SHIFT) | + (start_addr << TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUESTART8_SHIFT); + epon_epn_reg_writel(mode, + EPN_TX_L2S_QUE_CONFIGx_8_31_REG(i), + val); + start_addr = end_addr + 1; + } +} + +/* + * + */ +static void epon_hw_set_laser_normal_op(struct xport_epon_priv *mode, + bool normal_op) +{ + if (mode->up_speed == 1000) + lif_set_laser_normal_op(mode, normal_op); + else { + /* FIXME: implement */ + BUG(); + } +} + +/* + * + */ +static bool epon_hw_get_los(struct xport_epon_priv *mode) +{ + bool los; + u32 val; + + switch (mode->down_speed) { + case 10000: + { + val = epon_xpcsrx_reg_readl(mode, XPCSRX_RX_INT_STAT_REG); + los = (val & RX_INT_STAT_INTRXFRAMERCWLOSS_MASK); + if (!los) + break; + + /* clear interrupt */ + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_INT_STAT_REG, + RX_INT_STAT_INTRXFRAMERCWLOSS_MASK); + break; + } + default: + BUG(); + break; + } + return los; +} + +/* + * + */ +static void epon_hw_set_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + u16 llid, + bool enabled) +{ + if (mode->up_speed == 10000 || mode->down_speed == 10000) + xif_set_llid(mode, llid_idx, llid, enabled); + + if (mode->up_speed == 1000 || mode->down_speed == 1000) + lif_set_llid(mode, llid_idx, llid, enabled); +} + +/* + * + */ +static void epon_hw_pass_gates_frames(struct xport_epon_priv *mode, + unsigned int llid_idx, + bool pass) +{ + u32 val; + + val = epon_epn_reg_readl(mode, EPN_PASS_GATES_REG); + if (pass) + val |= (1 << llid_idx); + else + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_PASS_GATES_REG, val); +} + +/* + * + */ +static u32 epon_hw_get_local_mpcp_time(struct xport_epon_priv *mode) +{ + if (mode->down_speed == 10000) + return xif_get_local_mpcp_time(mode); + else { + /* implement for LIF */ + BUG(); + return 0; + } +} + +/* + * + */ +static void epon_hw_set_down_key(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int key_idx, + const uint8_t key[16], + const uint8_t sci[8]) +{ + if (mode->down_speed == 10000) + xif_set_down_key(mode, llid_idx, key_idx, key, sci); + else { + /* implement for LIF */ + BUG(); + } +} + +/* + * + */ +static void +epon_hw_get_llid_last_rx_encrypt(struct xport_epon_priv *mode, + unsigned int llid_idx, + bool *last_encrypted, + unsigned int *last_encrypted_key_id) +{ + if (mode->down_speed == 10000) + xif_get_llid_last_rx_encrypt(mode, llid_idx, + last_encrypted, + last_encrypted_key_id); + else { + /* implement for LIF */ + BUG(); + } +} + +/* + * + */ +static int epon_hw_data_port_read(struct xport_epon_priv *mode, + unsigned int port, + unsigned int ram_offset, + u32 *ret_value) +{ + u32 val; + size_t i; + + epon_epn_reg_writel(mode, EPN_DATA_PORT_ADDR_REG, ram_offset); + + val = (port << DATA_PORT_COMMAND_DPORTSELECT_SHIFT); + epon_epn_reg_writel(mode, EPN_DATA_PORT_COMMAND_REG, val); + + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_DATA_PORT_COMMAND_REG); + if ((val & DATA_PORT_COMMAND_DPORTBUSY_MASK)) + break; + udelay(5); + } + + if ((val & DATA_PORT_COMMAND_DPORTBUSY_MASK)) { + netdev_err(mode->port->priv->netdev, + "data port busy does not clear\n"); + *ret_value = 0xdeadbeef; + return 1; + } + + *ret_value = epon_epn_reg_readl(mode, EPN_DATA_PORT_DATA_0_REG); + return 0; +} + +/* + * + */ +static void epon_hw_link_remove_llid(struct xport_epon_priv *mode, + unsigned int llid_idx) +{ + epon_hw_set_llid(mode, llid_idx, 0, false); +} + +/* + * + */ +static void epon_hw_link_update_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int new_llid) +{ + /* FIXME: should reset grant FIFOs and maybe do other stuff */ + epon_hw_set_llid(mode, llid_idx, new_llid, true); +} + +/* + * + */ +static void epon_hw_link_start_tx(struct xport_epon_priv *mode, + unsigned int llid_idx) +{ + u32 val; + size_t i; + + /* unreset L2 & L1 fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_L2_RPT_FIFO_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L2_RPT_FIFO_REG, val); + + val = epon_epn_reg_readl(mode, EPN_RESET_L1_ACCUMULATOR_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L1_ACCUMULATOR_REG, val); + + /* start upstream processing */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_UPSTREAM_REG, val); + + /* monitor feedback */ + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_FB_REG); + if (val & (1 << llid_idx)) + break; + udelay(5); + } + + if (!(val & (1 << llid_idx))) { + netdev_err(mode->port->priv->netdev, + "upstream feedback wont toggle for llid %u\n", + llid_idx); + } + + /* unreset grant fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_GNT_FIFO_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_GNT_FIFO_REG, val); + + /* start processing grants */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_GRANTS_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_GRANTS_REG, val); +} + +/* + * + */ +static bool epon_hw_l2_queue_is_empty(struct xport_epon_priv *mode, + unsigned int l2_idx) +{ + u32 val; + + /* check that L2 is empty */ + val = epon_epn_reg_readl(mode, EPN_TX_L2S_QUE_EMPTY_REG); + if (val & (1 << l2_idx)) + return true; + return false; +} + +/* + * + */ +static void epon_hw_link_stop_tx(struct xport_epon_priv *mode, + unsigned int llid_idx) +{ + u32 val; + size_t i, j; + + /* stop processing grants */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_GRANTS_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_GRANTS_REG, val); + + /* stop upstream processing */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_UPSTREAM_REG, val); + + /* monitor feedback */ + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_FB_REG); + if (!(val & (1 << llid_idx))) + break; + udelay(5); + } + + if ((val & (1 << llid_idx))) { + netdev_err(mode->port->priv->netdev, + "upstream feedback wont clear for llid %u\n", + llid_idx); + } + + for (i = 0; i < 100; i++) { + /* flush l2 FIFO until its empty */ + val = llid_idx << L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_SHIFT; + epon_epn_reg_writel(mode, + EPN_L2S_FLUSH_CONFIG_REG, + val); + val |= L2S_FLUSH_CONFIG_CFGFLUSHL2SEN_MASK; + epon_epn_reg_writel(mode, + EPN_L2S_FLUSH_CONFIG_REG, + val); + + for (j = 0; j < 100; j++) { + val = epon_epn_reg_readl(mode, + EPN_L2S_FLUSH_CONFIG_REG); + if (val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK) + break; + udelay(5); + } + + if (!(val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK)) { + netdev_err(mode->port->priv->netdev, + "L2 flush not done %u\n", llid_idx); + break; + } + + val = llid_idx << L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_SHIFT; + epon_epn_reg_writel(mode, + EPN_L2S_FLUSH_CONFIG_REG, + val); + for (j = 0; j < 100; j++) { + val = epon_epn_reg_readl(mode, + EPN_L2S_FLUSH_CONFIG_REG); + if (!(val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK)) + break; + udelay(5); + } + + if ((val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK)) { + netdev_err(mode->port->priv->netdev, + "L2 flush does not stop %u\n", llid_idx); + break; + } + + udelay(100); + + if (epon_hw_l2_queue_is_empty(mode, llid_idx) && + bcm_runner_fw_bbh_is_empty(mode->port->priv)) + break; + } + + if (!epon_hw_l2_queue_is_empty(mode, llid_idx)) + netdev_err(mode->port->priv->netdev, + "L2 queue %u not empty after reset\n", llid_idx); + + if (!bcm_runner_fw_bbh_is_empty(mode->port->priv)) + netdev_err(mode->port->priv->netdev, + "BBH queue %u not empty after reset\n", llid_idx); + + /* reset L2 & L1 fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_L1_ACCUMULATOR_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L1_ACCUMULATOR_REG, val); + + val = epon_epn_reg_readl(mode, EPN_RESET_L2_RPT_FIFO_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L2_RPT_FIFO_REG, val); + + /* reset grant fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_GNT_FIFO_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_GNT_FIFO_REG, val); + +} + +/* + * + */ +static void epon_hw_set_burst_cap(struct xport_epon_priv *mode, + unsigned int burst_cap) +{ + u32 val; + + /* update max grant size */ + val = epon_epn_reg_readl(mode, EPN_MAX_GNT_SIZE_REG); + val &= ~MAX_GNT_SIZE_MAXGNTSIZE_MASK; + val |= burst_cap << MAX_GNT_SIZE_MAXGNTSIZE_SHIFT; + epon_epn_reg_writel(mode, EPN_MAX_GNT_SIZE_REG, val); + + if (mode->up_speed == 1000) + epon_epn_reg_writel(mode, EPN_BURST_CAPx_0_7_REG(0), + burst_cap); + else { + /* FIXME: implement */ + BUG(); + } +} + +/* + * + */ +static void epon_hw_init(struct xport_epon_priv *mode) +{ + size_t i; + u32 val; + + /* sanity check */ + val = epon_top_reg_readl(mode, EPON_TOP_SCRATCH_REG); + if (val != 0x1baddad) { + netdev_err(mode->port->priv->netdev, + "epon module not functional\n"); + return; + } + + /* put all ePON blocks in reset */ + epon_reset_modules(mode, true, + RESET_EPNRST_N_MASK | + RESET_LIFRST_N_MASK | + RESET_NCORST_N_MASK | + RESET_CLKPRGRST_N_MASK | + RESET_TODRST_N_MASK | + RESET_XIFRST_N_MASK | + RESET_XPCSTXRST_N_MASK | + RESET_XPCSRXRST_N_MASK); + msleep(20); + + /* clear all epon top interrupts */ + val = INTERRUPT_INT_1PPS_MASK | + INTERRUPT_INT_XPCS_TX_MASK | + INTERRUPT_INT_XPCS_RX_MASK | + INTERRUPT_INT_XIF_MASK | + INTERRUPT_INT_NCO_MASK | + INTERRUPT_INT_LIF_MASK | + INTERRUPT_INT_EPN_MASK; + epon_top_reg_writel(mode, EPON_TOP_INTERRUPT_REG, val); + + /* + * set epon top rate + */ + val = 0; + switch (mode->down_speed) { + case 1000: + break; + case 10000: + val |= CONTROL_CFGTENGIGDNS_MASK; + break; + default: + BUG(); + break; + } + + switch (mode->up_speed) { + case 1000: + break; + case 10000: + val |= CONTROL_CFGTENGIGPONUP_MASK; + break; + default: + BUG(); + break; + } + epon_top_reg_writel(mode, EPON_TOP_CONTROL_REG, val); + + /* release epn reset */ + epon_reset_modules(mode, false, RESET_EPNRST_N_MASK); + msleep(20); + + /* epn control 0 */ + val = CONTROL_0_PRVDROPUNMAPPPEDLLID_MASK | + CONTROL_0_CFGREPLACEUPFCS_MASK | + CONTROL_0_CFGAPPENDUPFCS_MASK | + CONTROL_0_DRXRST_PRE_N_MASK | + CONTROL_0_DRXEN_MASK | + CONTROL_0_UTXRST_PRE_N_MASK | + CONTROL_0_UTXEN_MASK; + val &= ~CONTROL_0_RPTSELECT_MASK; + val |= (1 << CONTROL_0_RPTSELECT_SHIFT); + epon_epn_reg_writel(mode, EPN_CONTROL_0_REG, val); + + /* max grant size */ + val = epon_epn_reg_readl(mode, EPN_MAX_GNT_SIZE_REG); + val &= ~MAX_GNT_SIZE_MAXGNTSIZE_MASK; + val |= 20000 << MAX_GNT_SIZE_MAXGNTSIZE_SHIFT; + epon_epn_reg_writel(mode, EPN_MAX_GNT_SIZE_REG, val); + + /* time stamp diff */ + val = epon_epn_reg_readl(mode, EPN_TIME_STAMP_DIFF_REG); + val &= ~TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_MASK; + val |= 0x40UL << TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_SHIFT; + epon_epn_reg_writel(mode, EPN_TIME_STAMP_DIFF_REG, val); + + /* main int status */ + epon_epn_reg_writel(mode, EPN_MAIN_INT_STATUS_REG, 0xffffffff); + + /* grant time start delta */ + val = epon_epn_reg_readl(mode, EPN_GNT_TIME_START_DELTA_REG); + val &= ~GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_MASK; + val |= 0x3e8UL << GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_SHIFT; + epon_epn_reg_writel(mode, EPN_GNT_TIME_START_DELTA_REG, val); + + /* grand start time margin */ + val = epon_epn_reg_readl(mode, EPN_DN_RD_GNT_MARGIN_REG); + val &= ~DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_MASK; + val |= 0x3ffUL << DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_RD_GNT_MARGIN_REG, val); + + /* misalign threshold */ + val = epon_epn_reg_readl(mode, EPN_DN_GNT_MISALIGN_THR_REG); + val &= ~DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_MASK; + val |= 0 << DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_SHIFT; + val &= ~DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_MASK; + val |= 2 << DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_GNT_MISALIGN_THR_REG, val); + + /* misalign pause */ + val = epon_epn_reg_readl(mode, EPN_DN_GNT_MISALIGN_PAUSE_REG); + val &= ~DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_MASK; + val |= 300 << DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_GNT_MISALIGN_PAUSE_REG, val); + + /* grant interval */ + val = epon_epn_reg_readl(mode, EPN_GNT_INTERVAL_REG); + val &= ~GNT_INTERVAL_GNTINTERVAL_MASK; + /* 1 second in 262us units */ + val |= (1000000 / 262) << GNT_INTERVAL_GNTINTERVAL_SHIFT; + epon_epn_reg_writel(mode, EPN_GNT_INTERVAL_REG, val); + + /* report byte length */ + val = epon_epn_reg_readl(mode, EPN_REPORT_BYTE_LENGTH_REG); + val &= ~REPORT_BYTE_LENGTH_PRVRPTBYTELEN_MASK; + val |= 84 << REPORT_BYTE_LENGTH_PRVRPTBYTELEN_SHIFT; + epon_epn_reg_writel(mode, EPN_REPORT_BYTE_LENGTH_REG, val); + + /* minimum grant setup set */ + val = epon_epn_reg_readl(mode, EPN_MINIMUM_GRANT_SETUP_REG); + val &= ~MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_MASK; + val |= 0x64UL << MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_SHIFT; + epon_epn_reg_writel(mode, EPN_MINIMUM_GRANT_SETUP_REG, val); + + /* spare register */ + val = SPARE_CTL_ECOJIRA758ENABLE_MASK; + epon_epn_reg_writel(mode, EPN_SPARE_CTL_REG, val); + + /* put all l1/l2 queue in reset*/ + epon_epn_reg_writel(mode, EPN_RESET_L1_ACCUMULATOR_REG, 0xffffffffUL); + epon_epn_reg_writel(mode, EPN_RESET_L2_RPT_FIFO_REG, 0xffffffffUL); + + /* disable grant processing on all LLIDs */ + epon_epn_reg_writel(mode, EPN_ENABLE_GRANTS_REG, 0); + + /* keep grant fifo in reset */ + epon_epn_reg_writel(mode, EPN_RESET_GNT_FIFO_REG, 0xffffffffUL); + + /* stop upstream processing */ + epon_epn_reg_writel(mode, EPN_ENABLE_UPSTREAM_REG, 0); + + /* monitor feedback */ + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_FB_REG); + if (val == 0) + break; + udelay(5); + } + + if (val) + netdev_err(mode->port->priv->netdev, + "failed to disable upstream on all llid\n"); + + /* epn control 1 */ + val = CONTROL_1_CFGSTALEGNTCHK_MASK | + CONTROL_1_DISABLEDISCSCALE_MASK | + CONTROL_1_CLRONRD_MASK | + 0; + epon_epn_reg_writel(mode, EPN_CONTROL_1_REG, val); + + /* setup discovery filter so we only accept discovery gates + * for the correct upstream speed */ + if (mode->down_speed == 10000) { + u16 mask, value; + + /* default to not care */ + mask = 0xffff; + value = get_disc_info_caps(mode, &mask); + + val = (mask << DISCOVERY_FILTER_PRVDISCINFOMASK_SHIFT) | + (value << DISCOVERY_FILTER_PRVDISCINFOVALUE_SHIFT); + epon_epn_reg_writel(mode, EPN_DISCOVERY_FILTER_REG, val); + } + + /* setup DA mac address for report frames, use standard mpcp + * multicast */ + epon_epn_reg_writel(mode, EPN_OLT_MAC_ADDR_HI_REG, + extract_mac_addr_hi(mpcp_frame_da)); + epon_epn_reg_writel(mode, EPN_OLT_MAC_ADDR_LO_REG, + extract_mac_addr_lo(mpcp_frame_da)); + + /* setup our mac address on every LLID, this should be if we + * do multiple TX LLID because they have to be different */ + for (i = 0; i < 8; i++) { + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_0_7_LO_REG(i), + extract_mac_addr_lo(mode->mac_addr)); + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_0_7_HI_REG(i), + extract_mac_addr_hi(mode->mac_addr)); + } + for (i = 8; i < 32; i++) { + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_8_31_LO_REG(i), + extract_mac_addr_lo(mode->mac_addr)); + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_8_31_LO_REG(i), + extract_mac_addr_hi(mode->mac_addr)); + } + + if (mode->up_speed == 1000 || mode->down_speed == 1000) { + if (lif_init(mode)) + return; + } + + if (mode->down_speed == 10000 || mode->up_speed == 10000) { + if (xif_init(mode)) + return; + } + + epon_hw_set_laser_normal_op(mode, true); + + /* set default reporting mode using only one queue (set before + * in control_0), clear all multi-prio bits */ + val = epon_epn_reg_readl(mode, EPN_MULTI_PRI_CFG_0_REG); + val &= ~MULTI_PRI_CFG_0_CFGRPTMULTIPRI0_MASK; + val &= ~MULTI_PRI_CFG_0_CFGRPTSWAPQS0_MASK; + val &= ~MULTI_PRI_CFG_0_CFGRPTGNTSOUTST0_MASK; + val &= ~MULTI_PRI_CFG_0_CFGSHAREDL2_MASK; + val &= ~MULTI_PRI_CFG_0_CFGSHAREDBURSTCAP_MASK; + epon_epn_reg_writel(mode, EPN_MULTI_PRI_CFG_0_REG, val); + + /* setup timer to trigger an interrupt if we don't get grants + * on a llid, (unit is 262 us) */ + epon_epn_reg_writel(mode, + EPN_GNT_INTERVAL_REG, + (10 * 1000 * 1000) / 262); + + /* setup L2 sizes */ + epn_init_l2_sizes(mode); + + for (i = 0; i < 8; i++) { + /* same as typo in bcm code */ + bcm_xrdp_api_pon_flow_id_set(mode->port->priv->xrdp, + i, 1); + } + + epon_hw_set_burst_cap(mode, DEFAULT_BURST_CAP); +} + +/* + * + */ +static void mode_epon_mib_update(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + size_t i; + + for (i = 0; i < ARRAY_SIZE(epon_mib_estat); i++) { + const struct bcm_runner_ethtool_stat *s; + u64 val; + bool incr; + char *p; + + s = &epon_mib_estat[i]; + val = 0; + incr = false; + switch (s->type) { + case EPON_STAT_XPCS_RX: + val = epon_xpcsrx_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_XPCS_RX64: + val = epon_xpcsrx_reg_readl(mode, s->reg); + val |= (u64)epon_xpcsrx_reg_readl(mode, + s->reg + 0x4) << 32; + incr = true; + break; + case EPON_STAT_XIF: + val = epon_xif_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_LIF: + val = epon_lif_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_EPN: + val = epon_epn_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_EPN_L1_ACC: + { + u32 val32; + unsigned int l1 = s->reg; + + val32 = (l1 << L1_ACCUMULATOR_SEL_CFGL1SUVASIZESEL_SHIFT) | + (l1 << L1_ACCUMULATOR_SEL_CFGL1SSVASIZESEL_SHIFT); + epon_epn_reg_writel(mode, EPN_L1_ACCUMULATOR_SEL_REG, + val32); + val = epon_epn_reg_readl(mode, EPN_L1_SVA_BYTES_REG); + incr = false; + break; + } + case EPON_STAT_EPN_RAM: + { + unsigned int llid, port, stat, ram_offset; + u32 val32; + + llid = (s->reg >> 24) & 0xff; + port = (s->reg >> 16) & 0xff; + stat = (s->reg) & 0xffff; + + ram_offset = 0; + switch (port) { + case 0: + ram_offset = (llid * 21) + stat; + break; + case 1: + ram_offset = (llid * 17) + stat; + break; + } + + epon_hw_data_port_read(mode, port, ram_offset, &val32); + val = val32; + incr = true; + break; + } + case EPON_STAT_LOCAL: + continue; + } + + p = (char *)&mode->mib + s->offset; + if (incr) + *(u64 *)p += val; + else + *(u64 *)p = val; + } +} + +/* + * + */ +static void *mode_epon_mib_get_data(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + return &mode->mib; +} + +/* + * + */ +static void mode_epon_mtu_set(void *mode_priv, unsigned int size) +{ + struct xport_epon_priv *mode = mode_priv; + epon_epn_reg_writel(mode, EPN_MAX_FRAME_SIZE_REG, size); +} + +/* + * + */ +static void __epon_link_start(struct xport_epon_priv *mode, + struct epon_link *link, + bool start_tx) +{ + if (!link->rx_enabled) { + epon_hw_link_update_llid(mode, link->idx, link->llid); + link->rx_enabled = true; + } + + if (start_tx) { + epon_hw_link_start_tx(mode, link->idx); + link->tx_enabled = true; + } +} + +/* + * + */ +static void epon_link_update_llid(struct xport_epon_priv *mode, + struct epon_link *link, + unsigned int llid) +{ + link->llid = llid; + epon_hw_link_update_llid(mode, link->idx, link->llid); +} + +/* + * + */ +static void epon_link_start_rx_only(struct xport_epon_priv *mode, + struct epon_link *link, + unsigned int llid) +{ + link->llid = llid; + __epon_link_start(mode, link, false); +} + +/* + * + */ +static void epon_link_start_bidir(struct xport_epon_priv *mode, + struct epon_link *link, + unsigned int llid) +{ + link->llid = llid; + __epon_link_start(mode, link, true); +} + +/* + * + */ +static void epon_link_pass_gates_frame(struct xport_epon_priv *mode, + struct epon_link *link, + bool pass) +{ + epon_hw_pass_gates_frames(mode, link->idx, pass); +} + + +/* + * + */ +static void epon_link_stop(struct xport_epon_priv *mode, + struct epon_link *link) +{ + if (link->tx_enabled) { + epon_hw_link_stop_tx(mode, link->idx); + link->tx_enabled = false; + } + + if (link->rx_enabled) { + epon_hw_link_remove_llid(mode, link->idx); + link->rx_enabled = false; + } + + epon_link_pass_gates_frame(mode, link, false); +} + +/* + * + */ +static struct epon_link *epon_link_find(struct xport_epon_priv *mode, + unsigned int llid) +{ + struct epon_link *link, *ret_link; + + ret_link = NULL; + mutex_lock(&mode->links_lock); + list_for_each_entry(link, &mode->links_list, next) { + if (link->llid == llid) { + ret_link = link; + break; + } + } + mutex_unlock(&mode->links_lock); + return ret_link; +} + +/* + * + */ +static struct epon_link *epon_link_alloc(struct xport_epon_priv *mode, + int force_idx) +{ + struct epon_link *link = NULL; + unsigned int idx; + + mutex_lock(&mode->links_lock); + + if (!mode->links_free) + goto end; + + /* choose llid idx */ + if (force_idx != -1) { + if (!(mode->links_free & (1ULL << force_idx))) { + WARN(1, "forced llid %d is not free\n", force_idx); + goto end; + } + idx = force_idx; + } else + idx = ffs(mode->links_free) - 1; + + link = kzalloc(sizeof (*link), GFP_KERNEL); + link->idx = idx; + mode->links_free &= ~(1ULL << idx); + list_add_tail(&link->next, &mode->links_list); + +end: + mutex_unlock(&mode->links_lock); + return link; +} + +/* + * + */ +static void __epon_link_release(struct xport_epon_priv *mode, + struct epon_link *link) +{ + WARN_ON(link->tx_enabled || link->rx_enabled); + list_del(&link->next); + mode->links_free |= (1ULL << link->idx); + kfree(link); +} + +/* + * + */ +static void epon_link_release(struct xport_epon_priv *mode, + struct epon_link *link) +{ + mutex_lock(&mode->links_lock); + __epon_link_release(mode, link); + mutex_unlock(&mode->links_lock); +} + +/* + * + */ +static void epon_schedule_reset_backoff(struct xport_epon_priv *mode) +{ + netdev_info(mode->port->priv->netdev, + "scheduling reset in %u ms\n", + mode->epon_reset_duration_ms); + bcm_enet_runner_schedule_reset(mode->port->priv, + mode->epon_reset_duration_ms); + mode->epon_reset_duration_ms *= 2; + if (mode->epon_reset_duration_ms > 5000) + mode->epon_reset_duration_ms = 5000; +} + +/* + * + */ +static int mpcp_rcv_handler(struct sk_buff *skb, + struct net_device *dev, + struct packet_type *pt, + struct net_device *orig_dev) +{ + struct xport_epon_priv *mode = pt->af_packet_priv; + struct mpcp_hdr *hdr; + struct sk_buff *nskb = NULL; + + /* + * do nothing if until global link status is correct + * + * not necessary per-se, but this avoids processing frames + * when the link just came up, or when it's down and we are + * waiting for manager to reset + */ + if (mode->glob_link_state != EPON_GLINK_UP) + goto drop; + + if (!pskb_may_pull(skb, sizeof (struct mpcp_hdr))) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + + hdr = (struct mpcp_hdr *)skb->data; + switch (be16_to_cpu(hdr->opcode)) { + case MPCP_OPCODE_GATE: + case MPCP_OPCODE_REGISTER: + case MPCP_OPCODE_REGISTER_ACK: + mode->mib.reg_mpcp_rx++; + break; + default: + mode->mib.reg_mpcp_rx_unk_opcode++; + goto drop; + } + + switch (mode->reg_state) { + case EPON_REG_WAIT_DISCOVERY: + { + struct mpcp_disc_gate *disc; + struct mpcp_disc_gate10g *disc_10g; + struct mpcp_hdr *rhdr; + struct mpcp_register_req *reg_req; + size_t disc_size, reg_req_size, to_pad; + u32 now, disc_start, disc_remain, disc_end, reg_req_duration; + u32 sync_time, rnd_value, window_len; + u32 slot, slot_count, slot_skip; + u32 val; + + if (be16_to_cpu(hdr->opcode) != MPCP_OPCODE_GATE) + goto drop; + + if (mode->down_speed == 10000) + disc_size = sizeof (*disc_10g); + else + disc_size = sizeof (*disc); + + if (!pskb_may_pull(skb, sizeof (*hdr) + disc_size)) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + disc = (struct mpcp_disc_gate *)(hdr + 1); + if (!(disc->nb_grants_flags & MPCP_GATE_F_IS_DISC)) + goto drop; + + if (mode->down_speed == 1000) { + sync_time = be16_to_cpu(disc->sync_time); + } else { + u16 caps = get_disc_info_caps(mode, NULL); + + disc_10g = (struct mpcp_disc_gate10g *)(disc); + if ((be16_to_cpu(disc_10g->disc_info) & caps) != caps) { + mode->mib.reg_mpcp_rx_disc_info_mismatch++; + goto drop; + } + + sync_time = be16_to_cpu(disc_10g->sync_time); + } + + mode->mib.reg_mpcp_rx_disc++; + + /* if first frame, then just capture capture synctime */ + if (!mode->reg_cfg.valid_sync_time || + mode->reg_cfg.sync_time != sync_time) { + mode->reg_cfg.valid_sync_time = true; + mode->reg_cfg.sync_time = sync_time; + epon_hw_set_disc_idle_time(mode, + DEF_LASER_ON_TIME, + mode->reg_cfg.sync_time, + DEF_LASER_OFF_TIME); + goto drop; + } + + rnd_value = get_random_u32(); + + /* + * allocate reply skb now, do all costly operation + * before calculating the remaining time + */ + reg_req_size = get_register_req_data_size(false); + nskb = dev_alloc_skb(reg_req_size); + if (!nskb) { + mode->mib.reg_mpcp_rx_other_err++; + goto drop; + } + + skb_reset_network_header(nskb); + rhdr = skb_put(nskb, sizeof (*rhdr) + sizeof (*reg_req)); + rhdr->opcode = cpu_to_be16(MPCP_OPCODE_REGISTER_REQ); + /* timestamp will be updated by hardware */ + rhdr->timestamp = cpu_to_be32(0xdeadbeef); + reg_req = (struct mpcp_register_req *)(rhdr + 1); + reg_req->flags = MPCP_REGREQ_F_REGISTER; + reg_req->pending_grants = BCM_MAX_PENDING_GRANTS; + reg_req->disc_info = cpu_to_be16(get_disc_info_caps(mode, + NULL)); + reg_req->laser_on = DEF_LASER_ON_TIME; + reg_req->laser_off = DEF_LASER_OFF_TIME; + /* pad remaining bytes with zero */ + to_pad = reg_req_size - ETH_HLEN - nskb->len; + memset(skb_put(nskb, to_pad), 0, to_pad); + + nskb->dev = mode->port->priv->netdev; + nskb->protocol = htons(ETH_P_PAUSE); + dev_hard_header(nskb, nskb->dev, ETH_P_PAUSE, + mpcp_frame_da, NULL, 0); + + /* + * reply packet is ready, check time left we have to + * reply + */ + now = epon_hw_get_local_mpcp_time(mode); + window_len = be16_to_cpu(disc->length); + disc_start = be32_to_cpu(disc->start_time); + disc_end = disc_start + window_len; + if (now >= disc_end) { + /* really late */ + mode->mib.reg_mpcp_rx_disc_late++; + goto drop; + } + + /* make sure we have time to send the frame before end + * of discovery */ + disc_remain = disc_end - now; + reg_req_duration = get_register_req_data_duration(mode) + + DEF_LASER_ON_TIME + + DEF_LASER_OFF_TIME + + mode->reg_cfg.sync_time; + + /* if remaining time is too small (time for us to + * schedule tx), dont even try */ + if (disc_remain < reg_req_duration || + reg_req_duration - disc_remain < SOFTWARE_TX_LATENCY_TQ) { + mode->mib.reg_mpcp_rx_disc_late++; + goto drop; + } + + /* + * Take a random offset inside transmit inside window. + * + * Since everyone else has the same reg_req_duration + * value, divide window into equal slots so we reduce + * chance of colliding (of course, only works if + * everyone does the same...) + */ + slot_count = window_len / reg_req_duration; + slot_skip = 0; + + /* don't use slots that are already late */ + if (now + SOFTWARE_TX_LATENCY_TQ > disc_start) + slot_skip = DIV_ROUND_UP(now + SOFTWARE_TX_LATENCY_TQ - + disc_start, + reg_req_duration); + + slot = slot_skip + (rnd_value % (slot_count - slot_skip)); + mode->mib.reg_mpcp_rx_disc_last_slot = slot; + + /* program hardware to skip this number of tq before + * sending register_req */ + val = (slot * reg_req_duration) << + DN_DISCOVERY_SEED_CFGDISCSEED_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_DISCOVERY_SEED_REG, val); + + /* finally send packet */ + dev_queue_xmit(nskb); + nskb = NULL; + mode->mib.reg_mpcp_tx_reg_req++; + +#if 0 + printk("DISC_WINDOW: [%u - %u], slot: count:%u " + "skip:%d chosen:%d\n", + be32_to_cpu(disc->start_time) - now, + disc_remain, + slot_count, + slot_skip, + slot); +#endif + mode->reg_state = EPON_REG_WAIT_REGISTER; + mode->reg_state_last_change = jiffies; + break; + } + + case EPON_REG_WAIT_REGISTER: + { + struct mpcp_register *reg; + struct mpcp_register10g *reg_10g; + struct mpcp_register_ack *reg_ack; + struct mpcp_hdr *rhdr; + size_t reg_size, reg_ack_size, to_pad; + + if (be16_to_cpu(hdr->opcode) != MPCP_OPCODE_REGISTER) + goto drop; + + if (mode->down_speed == 10000) + reg_size = sizeof (*reg_10g); + else + reg_size = sizeof (*reg); + + if (!pskb_may_pull(skb, sizeof (*hdr) + reg_size)) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + /* the frame is sent to us on the broadcast LLID, we + * have to make sure it's addressed to us only */ + if (skb->pkt_type != PACKET_HOST) { + mode->mib.reg_mpcp_rx_reg_for_other++; + goto drop; + } + + reg = (struct mpcp_register *)(hdr + 1); + switch (reg->flags) { + case MPCP_REG_F_REREGISTER: + case MPCP_REG_F_DEREGISTER: + /* go back to previous state */ + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + mode->reg_state_last_change = jiffies; + mode->mib.reg_mpcp_rx_reg_dereg++; + goto drop; + + case MPCP_REG_F_NACK: + /* go back to previous state, might backoff + * here */ + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + mode->reg_state_last_change = jiffies; + mode->mib.reg_mpcp_rx_reg_nack++; + goto drop; + + case MPCP_REG_F_ACK: + /* fallthrough */ + break; + + default: + mode->mib.reg_mpcp_rx_reg_unk_flag++; + goto drop; + } + + /* registration success, update LLID with assigned one */ + mode->reg_cfg.assigned_llid = be16_to_cpu(reg->assigned_port); + + /* filter gates from now */ + epon_link_pass_gates_frame(mode, mode->user_link, false); + + /* now filter the new llid */ + epon_link_update_llid(mode, + mode->user_link, + mode->reg_cfg.assigned_llid); + + /* capture and apply the OLT parameters */ + mode->reg_cfg.sync_time = be16_to_cpu(reg->sync_time); + if (mode->down_speed == 10000) { + reg_10g = (struct mpcp_register10g *)(reg); + mode->reg_cfg.laser_on_time = reg_10g->target_laser_on; + mode->reg_cfg.laser_off_time = reg_10g->target_laser_off; + } else { + mode->reg_cfg.laser_on_time = DEF_LASER_ON_TIME; + mode->reg_cfg.laser_off_time = DEF_LASER_OFF_TIME; + } + + epon_hw_set_normal_idle_time(mode, + mode->reg_cfg.laser_on_time, + mode->reg_cfg.sync_time, + mode->reg_cfg.laser_off_time); + + + /* send registration ACK */ + reg_ack_size = max_t(size_t, + ETH_HLEN + + sizeof (struct mpcp_hdr) + + sizeof (struct mpcp_register_ack), + ETH_ZLEN); + nskb = dev_alloc_skb(reg_ack_size); + if (!nskb) { + mode->mib.reg_mpcp_rx_other_err++; + goto drop; + } + + skb_reset_network_header(nskb); + rhdr = skb_put(nskb, sizeof (*rhdr) + sizeof (*reg_ack)); + rhdr->opcode = cpu_to_be16(MPCP_OPCODE_REGISTER_ACK); + /* timestamp will be updated by hardware */ + rhdr->timestamp = cpu_to_be32(0xdeadbeef); + reg_ack = (struct mpcp_register_ack *)(rhdr + 1); + reg_ack->flags = MPCP_REGACK_F_ACK; + reg_ack->echoed_assigned_port = + cpu_to_be16(mode->reg_cfg.assigned_llid); + reg_ack->echoed_sync_time = + cpu_to_be16(mode->reg_cfg.sync_time); + /* pad remaining bytes with zero */ + to_pad = reg_ack_size - ETH_HLEN - nskb->len; + memset(skb_put(nskb, to_pad), 0, to_pad); + + nskb->dev = mode->port->priv->netdev; + nskb->protocol = htons(ETH_P_PAUSE); + dev_hard_header(nskb, nskb->dev, ETH_P_PAUSE, + mpcp_frame_da, NULL, 0); + + dev_queue_xmit(nskb); + nskb = NULL; + mode->mib.reg_mpcp_tx_reg_ack++; + + /* clear some IRQs that link monitoring will be + * checking from now */ + epon_epn_reg_writel(mode, + EPN_MAIN_INT_STATUS_REG, + MAIN_INT_STATUS_INTDNOUTOFORDER_MASK | + MAIN_INT_STATUS_INTDNTIMENOTINSYNC_MASK); + epon_epn_reg_writel(mode, + EPN_GNT_INTV_INT_STATUS_REG, + ~0); + + netdev_info(mode->port->priv->netdev, + "MPCP registration complete, llid 0x%04x\n", + mode->reg_cfg.assigned_llid); + mode->reg_state = EPON_REG_COMPLETE; + mode->reg_state_last_change = jiffies; + break; + } + + case EPON_REG_COMPLETE: + { + struct mpcp_register *reg; + struct mpcp_register10g *reg_10g; + size_t reg_size; + + if (be16_to_cpu(hdr->opcode) != MPCP_OPCODE_REGISTER) + goto drop; + + if (mode->down_speed == 10000) + reg_size = sizeof (*reg_10g); + else + reg_size = sizeof (*reg); + + if (!pskb_may_pull(skb, sizeof (*hdr) + reg_size)) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + if (skb->pkt_type != PACKET_HOST) { + mode->mib.reg_mpcp_rx_reg_for_other++; + goto drop; + } + + reg = (struct mpcp_register *)(hdr + 1); + switch (reg->flags) { + case MPCP_REG_F_REREGISTER: + case MPCP_REG_F_DEREGISTER: + netdev_info(mode->port->priv->netdev, + "received MPCP deregister\n"); + mode->reg_state = EPON_REG_FAILED; + mode->reg_state_last_change = jiffies; + phylink_mac_change(mode->port->priv->phylink, false); + epon_schedule_reset_backoff(mode); + goto drop; + + default: + goto drop; + } + } + + case EPON_REG_FAILED: + goto drop; + } + + +drop: + if (nskb) + kfree_skb(nskb); + kfree_skb(skb); + return NET_RX_DROP; +} + +/* + * + */ +static void glob_link_work_resched(struct xport_epon_priv *mode) +{ + queue_delayed_work(mode->epon_wq, + &mode->glob_link_work, HZ / 5); +} + +/* + * + */ +static struct { + u32 mask; + const char *name; + bool fatal; + bool ignore_when_not_reg; +} epn_irqs[] = { + { + MAIN_INT_STATUS_INTBBHUPFRABORT_MASK, + "BBHUPFRABORT", + false, + }, + { + MAIN_INT_STATUS_INTCOL2SBURSTCAPOVERFLOWPRES_MASK, + "COL2SBURSTCAPOVERFLOWPRES", + false, + }, + { + MAIN_INT_STATUS_INTCOEMPTYRPT_MASK, + "COEMPTYRPT", + false, + }, + { + MAIN_INT_STATUS_INTCODRXERRABORTPRES_MASK, + "CODRXERRABORTPRES", + false, + }, + { + MAIN_INT_STATUS_INTL2SFIFOOVERRUN_MASK, + "L2SFIFOOVERRUN", + true, + }, + { + MAIN_INT_STATUS_INTCO1588TSINT_MASK, + "CO1588TSINT", + false, + }, + { + MAIN_INT_STATUS_INTCODELSTALEGNT_MASK, + "CODELSTALEGNT", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTNONPOLL_MASK, + "COGNTNONPOLL", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTMISALIGN_MASK, + "COGNTMISALIGN", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTTOOFAR_MASK, + "COGNTTOOFAR", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTINTERVAL_MASK, + "COGNTINTERVAL", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTMISSABORT_MASK, + "COGNTMISSABORT", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTFULLABORT_MASK, + "COGNTFULLABORT", + false, + }, + { + MAIN_INT_STATUS_INTBADUPFRLEN_MASK, + "BADUPFRLEN", + true, + }, + { + MAIN_INT_STATUS_INTUPTARDYPACKET_MASK, + "UPTARDYPACKET", + false, + }, + { + MAIN_INT_STATUS_INTBIFIFOOVERRUN_MASK, + "BIFIFOOVERRUN", + true, + }, + { + MAIN_INT_STATUS_INTDNSTATSOVERRUN_MASK, + "DNSTATSOVERRUN", + false, + }, + { + MAIN_INT_STATUS_INTUPSTATSOVERRUN_MASK, + "UPSTATSOVERRUN", + false, + }, + { + MAIN_INT_STATUS_INTDNOUTOFORDER_MASK, + "DNOUTOFORDER", + false, + true, + }, + { + MAIN_INT_STATUS_INTTRUANTBBHHALT_MASK, + "TRUANTBBHHALT", + true, + }, + { + MAIN_INT_STATUS_INTCOBBHUPSFAULT_MASK, + "COBBHUPSFAULT", + true, + }, + { + MAIN_INT_STATUS_INTDNTIMENOTINSYNC_MASK, + "DNTIMENOTINSYNC", + true, + true, + }, +}; + +/* + * + */ +static bool epon_has_fatal_pending_irq(struct xport_epon_priv *mode) +{ + u32 val; + size_t i; + bool fatal; + bool reg_done; + + /* make sure we still receive grant */ + if (mode->reg_state == EPON_REG_COMPLETE) { + val = epon_epn_reg_readl(mode, EPN_GNT_INTV_INT_STATUS_REG); + if ((val & (1 << 0))) { + netdev_err(mode->port->priv->netdev, + "not receiving any grant on user " + "llid anymore\n"); + return true; + } + } + + val = epon_epn_reg_readl(mode, EPN_MAIN_INT_STATUS_REG); + if (!val) + return false; + + reg_done = (mode->reg_state == EPON_REG_COMPLETE); + fatal = false; + for (i = 0; i < ARRAY_SIZE(epn_irqs); i++) { + if (!(epn_irqs[i].mask & val)) + continue; + + if (epn_irqs[i].ignore_when_not_reg && !reg_done) + continue; + + netdev_err(mode->port->priv->netdev, + "%slink IRQ pending: %s\n", + epn_irqs[i].fatal ? "fatal " : "", + epn_irqs[i].name); + + fatal |= epn_irqs[i].fatal; + } + + epon_epn_reg_writel(mode, EPN_MAIN_INT_STATUS_REG, val); + return fatal; +} + +/* + * + */ +static void glob_link_work(struct work_struct *w) +{ + struct delayed_work *dwork = to_delayed_work(w); + struct xport_epon_priv *mode; + bool link; + + mode = container_of(dwork, struct xport_epon_priv, glob_link_work); + + /* check for laser monitoring error */ + switch (mode->up_speed) { + case 1000: + { + u32 val = epon_lif_reg_readl(mode, LIF_INT_STATUS_REG); + if (val & LIF_INT_STATUS_LASERONMAX_MASK) { + netdev_err(mode->port->priv->netdev, + "laser monitoring error\n"); + mode->lasermon_event_count++; + epon_lif_reg_writel(mode, + LIF_INT_STATUS_REG, + LIF_INT_STATUS_LASERONMAX_MASK); + } + break; + } + case 10000: + /* FIXME implement */ + break; + } + + + switch (mode->glob_link_state) { + case EPON_GLINK_DOWN: + link = !epon_hw_get_los(mode); + if (!link) { + glob_link_work_resched(mode); + return; + } + + mode->glob_link_state = EPON_GLINK_UP; + phylink_mac_change(mode->port->priv->phylink, true); + glob_link_work_resched(mode); + break; + + case EPON_GLINK_UP: + link = !epon_hw_get_los(mode); + if (!link) { + netdev_info(mode->port->priv->netdev, + "PCS link down\n"); + mode->glob_link_state = EPON_GLINK_FAILED; + phylink_mac_change(mode->port->priv->phylink, false); + bcm_enet_runner_schedule_reset(mode->port->priv, 0); + return; + } + + if (epon_has_fatal_pending_irq(mode)) { + netdev_err(mode->port->priv->netdev, + "fatal IRQ, will reset\n"); + mode->glob_link_state = EPON_GLINK_FAILED; + phylink_mac_change(mode->port->priv->phylink, false); + epon_schedule_reset_backoff(mode); + return; + } + + if (mode->reg_state == EPON_REG_WAIT_REGISTER && + time_after(jiffies, + mode->reg_state_last_change + HZ * 5)) { + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + mode->reg_state_last_change = jiffies; + mode->mib.reg_mpcp_rx_reg_timeout++; + if (mode->mib.reg_mpcp_rx_reg_timeout < 5) + netdev_info(mode->port->priv->netdev, + "restart stalled registration\n"); + else { + netdev_err(mode->port->priv->netdev, + "registration stalled for too " + "long, hard reset\n"); + epon_schedule_reset_backoff(mode); + return; + } + } + + glob_link_work_resched(mode); + break; + + case EPON_GLINK_FAILED: + break; + } +} + +/* + * + */ +static int __epon_start(struct xport_epon_priv *mode, + unsigned int down_speed, unsigned int up_speed) +{ + xport_switch_pinctrl(mode->port, XPORT_PIN_ROGUE1); + + switch (down_speed) { + case 10000: + break; + default: + BUG(); + return -ENOTSUPP; + } + + switch (up_speed) { + case 1000: + break; + default: + BUG(); + return -ENOTSUPP; + } + + BUG_ON(mode->glob_link_state != EPON_GLINK_DOWN); + BUG_ON(mode->reg_state != EPON_REG_WAIT_DISCOVERY); + mode->reg_state_last_change = jiffies; + mode->user_cfg.burst_cap = DEFAULT_BURST_CAP; + + mode->down_speed = down_speed; + mode->up_speed = up_speed; + mode->start_count++; + + /* create static links we need */ + mode->user_link = epon_link_alloc(mode, USER_LLID_IDX); + if (!mode->user_link) + return 1; + + mode->bcast_link = epon_link_alloc(mode, BROADCAST_LLID_IDX); + if (!mode->bcast_link) { + epon_link_release(mode, mode->bcast_link); + mode->bcast_link = NULL; + return 1; + } + + /* low level hardware init */ + xport_serdes_set_params(mode->port, &serdes_params_10g_1g, + &serdes_m3params_10g_1g); + epon_hw_init(mode); + + /* start link work & enable registration */ + epon_link_start_rx_only(mode, + mode->bcast_link, + get_broadcast_llid(mode)); + epon_link_start_bidir(mode, + mode->user_link, + get_broadcast_llid(mode)); + epon_link_pass_gates_frame(mode, + mode->user_link, + true); + + dev_add_pack(&mode->reg_tap); + glob_link_work_resched(mode); + return 0; +} + +/* + * + */ +static void __epon_stop(struct xport_epon_priv *mode) +{ + struct epon_link *link; + + /* stop */ + cancel_delayed_work_sync(&mode->glob_link_work); + dev_remove_pack(&mode->reg_tap); + flush_workqueue(mode->epon_wq); + + /* make sure carrier is off */ + phylink_mac_change(mode->port->priv->phylink, false); + netif_carrier_off(mode->port->priv->netdev); + + /* try to avoid any spurious TX while we reset */ + epon_hw_set_laser_normal_op(mode, false); + + /* NOTE: netdevice queues are stopped */ + bcm_runner_fw_stop_tx(mode->port->priv); + + /* nothing is touching hardware now, stop all links */ + mutex_lock(&mode->links_lock); + list_for_each_entry(link, &mode->links_list, next) + epon_link_stop(mode, link); + mutex_unlock(&mode->links_lock); + + if (!bcm_runner_fw_tx_is_stopped(mode->port->priv)) + netdev_err(mode->port->priv->netdev, + "failed to stop TX runner DMA\n"); + + /* + * reset state + */ + mode->glob_link_state = EPON_GLINK_DOWN; + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + memset(&mode->reg_cfg, 0, sizeof (mode->reg_cfg)); + memset(&mode->user_cfg, 0, sizeof (mode->user_cfg)); + + epon_link_release(mode, mode->bcast_link); + mode->bcast_link = NULL; + epon_link_release(mode, mode->user_link); + mode->user_link = NULL; + mode->down_speed = 0; + mode->up_speed = 0; +} + +/* + * + */ +static int __epon_add_mcast_llid(struct xport_epon_priv *mode, + unsigned int llid) +{ + struct epon_link *link; + + if (epon_link_find(mode, llid)) + return -EEXIST; + + link = epon_link_alloc(mode, -1); + if (!link) + return -ENOSPC; + + epon_link_start_rx_only(mode, link, llid); + mode->links_mcast |= (1 << link->idx); + return 0; +} + +/* + * + */ +static int __epon_del_mcast_llid(struct xport_epon_priv *mode, + unsigned int llid) +{ + struct epon_link *link; + + link = epon_link_find(mode, llid); + if (!link) + return -ENOENT; + + epon_link_stop(mode, link); + epon_link_release(mode, link); + mode->links_mcast &= ~(1 << link->idx); + return 0; +} + +/* + * + */ +static void __epon_del_all_mcast_llid(struct xport_epon_priv *mode) +{ + struct epon_link *link, *tmp; + + mutex_lock(&mode->links_lock); + list_for_each_entry_safe(link, tmp, &mode->links_list, next) { + if ((1 << link->idx) & mode->links_mcast) { + epon_link_stop(mode, link); + __epon_link_release(mode, link); + } + } + mutex_unlock(&mode->links_lock); + mode->links_mcast = 0; +} + +/* + * + */ +static int epon_start(struct xport_epon_priv *mode, + unsigned int down_speed, unsigned int up_speed) + +{ + int ret; + + bcm_enet_runner_unschedule_reset(mode->port->priv); + + mutex_lock(&mode->epon_lock); + if (WARN_ON(mode->epon_started)) { + netdev_err(mode->port->priv->netdev, + "tried to start epon twice"); + mutex_unlock(&mode->epon_lock); + return -EBUSY; + } + + ret = __epon_start(mode, down_speed, up_speed); + if (!ret) + mode->epon_started = true; + mutex_unlock(&mode->epon_lock); + + return ret; +} + +/* + * + */ +static void epon_stop(struct xport_epon_priv *mode) +{ + mutex_lock(&mode->epon_lock); + if (mode->epon_started) { + __epon_stop(mode); + mode->epon_started = false; + } + memset(&mode->mib, 0, sizeof (mode->mib)); + __epon_del_all_mcast_llid(mode); + mutex_unlock(&mode->epon_lock); + bcm_enet_runner_unschedule_reset(mode->port->priv); +} + +/* + * + */ +static int mode_get_epon_param(void *mode_priv, + struct ethtool_epon_param *param) +{ + struct xport_epon_priv *mode = mode_priv; + bool last_encrypted; + unsigned int last_encrypted_key_id; + + memset(param, 0, sizeof (*param)); + param->change_count = mode->start_count; + param->lasermon_event_count = mode->lasermon_event_count; + + if (!mode->epon_started) + return 0; + + mutex_lock(&mode->epon_lock); + param->burst_cap = mode->user_cfg.burst_cap; + param->discovery_rx = (mode->mib.reg_mpcp_rx_disc > 0); + param->registered = (mode->reg_state == EPON_REG_COMPLETE); + if (!param->registered) { + mutex_unlock(&mode->epon_lock); + return 0; + } + + param->llid = mode->reg_cfg.assigned_llid; + param->down_encrypt = mode->user_cfg.down_enc_enabled; + + memcpy(param->key_sci, mode->user_cfg.key_sci, + sizeof (param->key_sci)); + memcpy(param->down_key0, mode->user_cfg.down_key0, + sizeof (param->down_key0)); + memcpy(param->down_key1, mode->user_cfg.down_key1, + sizeof (param->down_key1)); + + epon_hw_get_llid_last_rx_encrypt(mode, + mode->user_link->idx, + &last_encrypted, + &last_encrypted_key_id); + param->down_last_rx_encrypted = last_encrypted; + param->down_last_rx_key_id = last_encrypted_key_id; + + mutex_unlock(&mode->epon_lock); + return 0; +} + +/* + * + */ +static int mode_set_epon_param(void *mode_priv, + const struct ethtool_epon_param *param) +{ + struct xport_epon_priv *mode = mode_priv; + int ret; + + if (!mode->epon_started) + return -ENETDOWN; + + switch (param->cmd) { + case ETHTOOL_SEPON_KEYS: + { + u8 *d; + const u8 *s; + + if (param->keys_update_id == 0) { + s = param->down_key0; + d = mode->user_cfg.down_key0; + } else if (param->keys_update_id == 1) { + s = param->down_key1; + d = mode->user_cfg.down_key1; + } else + return -EINVAL; + + memcpy(d, s, sizeof (mode->user_cfg.down_key0)); + memcpy(mode->user_cfg.key_sci, param->key_sci, + sizeof (mode->user_cfg.key_sci)); + + mutex_lock(&mode->epon_lock); + epon_hw_set_down_key(mode, + mode->user_link->idx, + param->keys_update_id, + s, + param->key_sci); + mutex_unlock(&mode->epon_lock); + break; + } + case ETHTOOL_SEPON_ENCRYPT: + mode->user_cfg.down_enc_enabled = param->down_encrypt; + break; + case ETHTOOL_SEPON_BURST: + mode->user_cfg.burst_cap = param->burst_cap; + mutex_lock(&mode->epon_lock); + epon_hw_set_burst_cap(mode, mode->user_cfg.burst_cap); + mutex_unlock(&mode->epon_lock); + break; + case ETHTOOL_SEPON_RESTART: + netdev_info(mode->port->priv->netdev, + "restart link request from userspace\n"); + bcm_enet_runner_schedule_reset(mode->port->priv, 0); + break; + case ETHTOOL_SEPON_ADD_MCLLID: + mutex_lock(&mode->epon_lock); + ret = __epon_add_mcast_llid(mode, param->mcast_llid); + mutex_unlock(&mode->epon_lock); + return ret; + case ETHTOOL_SEPON_DEL_MCLLID: + mutex_lock(&mode->epon_lock); + ret = __epon_del_mcast_llid(mode, param->mcast_llid); + mutex_unlock(&mode->epon_lock); + return ret; + case ETHTOOL_SEPON_CLR_MCLLID: + mutex_lock(&mode->epon_lock); + __epon_del_all_mcast_llid(mode); + mutex_unlock(&mode->epon_lock); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +/* + * + */ +static int mode_phylink_pcs_config(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + const unsigned long *advertising) +{ + struct xport_epon_priv *mode = mode_priv; + + switch (interface) { + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + epon_start(mode, 10000, 1000); + break; + default: + BUG(); + break; + } + + return 0; +} + +/* + * called for each packet during netdevice xmit + */ +static bool mode_epon_can_send(void *mode_priv, unsigned int protocol) +{ + struct xport_epon_priv *mode = mode_priv; + + switch (protocol) { + case ETH_P_PAUSE: + return true; + default: + return mode->reg_state == EPON_REG_COMPLETE; + } +} + +/* + * + */ +static void mode_phylink_link_up(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + int speed, int duplex, + struct phy_device *phy) +{ + /* not used */ +} + +/* + * + */ +static void mode_phylink_link_down(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface) +{ + /* not used */ +} + +/* + * + */ +static void mode_phylink_pcs_an_restart(void *mode_priv) +{ + /* not supported */ +} + +/* + * + */ +static int mode_phylink_pcs_get_state(void *mode_priv, + struct phylink_link_state *state) +{ + struct xport_epon_priv *mode = mode_priv; + + /* fake link down after failed registration */ + state->link = ((mode->glob_link_state == EPON_GLINK_UP) && + (mode->reg_state != EPON_REG_FAILED)); + if (state->link) { + state->an_complete = 1; + state->speed = 10000; + state->duplex = 1; + } + + return 0; +} + +/* + * called when netdevice is started or after phylink interface change + */ +static void mode_epon_stop(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + epon_stop(mode); +} + +/* + * called when netdevice is started or after phylink interface change + */ +static void *mode_epon_init(void *port_priv, + const struct bcm_xrdp_enet_params *params) +{ + struct xport_priv *port = port_priv; + struct xport_epon_priv *mode; + char name[64]; + size_t i; + + mode = kzalloc(sizeof (*mode), GFP_KERNEL); + if (!mode) + return ERR_PTR(-ENOMEM); + + mode->port = port; + INIT_DELAYED_WORK(&mode->glob_link_work, glob_link_work); + mutex_init(&mode->links_lock); + INIT_LIST_HEAD(&mode->links_list); + mode->links_free = (1 << USER_LLID_IDX) | (1 << BROADCAST_LLID_IDX); + /* ethtool mib only reports llid 24 to 30 rx bytes, don't use + * other llid */ + for (i = 24; i < 31; i++) + mode->links_free |= (1 << i); + + mutex_init(&mode->epon_lock); + mode->epon_reset_duration_ms = 100; + + /* capture mac address */ + memcpy(mode->mac_addr, + mode->port->priv->netdev->dev_addr, + ETH_ALEN); + + /* set default config */ + mode->laser_active_hi = true; + + scnprintf(name, sizeof (name), "%s-epon", port->priv->netdev->name); + mode->epon_wq = create_singlethread_workqueue(name); + if (!mode->epon_wq) { + kfree(mode); + return ERR_PTR(-ENOMEM); + } + + /* setup MPCP TAP */ + mode->reg_tap.type = cpu_to_be16(ETH_P_PAUSE); + mode->reg_tap.func = mpcp_rcv_handler; + mode->reg_tap.af_packet_priv = mode; + mode->reg_tap.ignore_outgoing = true; + mode->reg_tap.dev = port->priv->netdev; + + mode_epon_dbg_init(mode); + return mode; +} + +/* + * called when netdevice is stopped or after phylink interface change + */ +static void mode_epon_release(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + mode_epon_dbg_release(mode); + destroy_workqueue(mode->epon_wq); + kfree(mode); +} + +/* + * + */ +static u32 mode_get_bbh_id(void *port_priv) +{ + struct xport_priv *port = port_priv; + return port->pon_bbh_id; +} + +struct oam_event_notif_pdu { + u16 sequence; + u8 tlv_type; + u8 len; + u8 oui[3]; + u8 code; + u8 raised; + u16 object_type; + u16 object_instance; +} __attribute__((packed)); + +/* + * + */ +static int +mode_epon_dgasp_gen_data(void *mode_priv, u8 *buf, size_t buf_len) +{ + const u8 dpoe_oui[3] = { 0x00, 0x10, 0x00 }; + struct xport_epon_priv *mode = mode_priv; + struct ethhdr *eth; + struct oam_event_notif_pdu *pdu; + u8 *p; + + if (buf_len < sizeof (struct ethhdr) + 4 + sizeof (*pdu)) + return -EINVAL; + + p = buf; + eth = (struct ethhdr *)p; + memcpy(eth->h_dest, "\x01\x80\xc2\x00\x00\x02", 6); + memcpy(eth->h_source, mode->mac_addr, 6); + eth->h_proto = cpu_to_be16(ETH_P_SLOW); + p += sizeof (*eth); + + /* SLOW_PROTO_SUBTYPE_OAM */ + *p++ = 0x3; + + /* OAM proto flags (16 bits), local+remote stable + dgasp */ + *p++ = 0x00; + *p++ = 0x52; + + /* Event Notification PDU */ + *p++ = 0x01; + + pdu = (struct oam_event_notif_pdu *)p; + pdu->sequence = 0; + pdu->tlv_type = 0xfe; /* org specific */ + pdu->len = sizeof (*pdu); + memcpy(pdu->oui, &dpoe_oui, 3); + pdu->code = 0x41; /* power failure */ + pdu->raised = 1; + pdu->object_type = 0; + pdu->object_instance = 0; + p += sizeof (*pdu); + + return p - buf; +} + +const struct bcm_enet_mode_ops xport_epon_mode_ops = { + .name = "EPON", + + .init = mode_epon_init, + .release = mode_epon_release, + .can_send = mode_epon_can_send, + + .stop = mode_epon_stop, + .get_bbh_id = mode_get_bbh_id, + .mtu_set = mode_epon_mtu_set, + + .dgasp_supported = true, + .dgasp_gen_data = mode_epon_dgasp_gen_data, + + /* ethtool operations*/ + .get_epon_param = mode_get_epon_param, + .set_epon_param = mode_set_epon_param, + + /* mib operation */ + .mib_estat = epon_mib_estat, + .mib_estat_count = ARRAY_SIZE(epon_mib_estat), + .mib_update = mode_epon_mib_update, + .mib_get_data = mode_epon_mib_get_data, + + /* + * phylink callback + */ + .phylink_link_down = mode_phylink_link_down, + .phylink_link_up = mode_phylink_link_up, + .phylink_pcs_config = mode_phylink_pcs_config, + .phylink_pcs_get_state = mode_phylink_pcs_get_state, + .phylink_pcs_an_restart = mode_phylink_pcs_an_restart, +}; diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.h 2023-03-09 15:06:11.360234118 +0100 @@ -0,0 +1,490 @@ +#ifndef PORT_XPORT_EPON_H_ +#define PORT_XPORT_EPON_H_ + +#include + +#include "port_xport.h" + +#include "regs/epon_epon_top.h" +#include "regs/epon_epn.h" +#include "regs/epon_epn_onu_mac_addr.h" +#include "regs/epon_epn_tx_l1s_shp.h" +#include "regs/epon_epon_top.h" +#include "regs/epon_lif.h" +#include "regs/epon_nco_addr.h" +#include "regs/epon_xif.h" +#include "regs/epon_xpcsrx.h" +#include "regs/epon_xpcstx.h" + +/* + * EPON definitions + */ +#define BROADCAST_LLID_1G 0x7fff +#define BROADCAST_LLID_10G 0x7ffe + +#define NSEC_TO_TQ(x) ((x) / 16) +#define USEC_TO_TQ(x) (((x) * 1000) / 16) +#define TQ_TO_NSEC(x) ((x) * 16) +#define BYTES_TO_TQ_1G(x) ((x) / 2) +#define PREAMBLE_LEN_BYTES 8 +#define IPG_BYTES_1G 12 + +/* default laser on/off time per specification */ +#define DEF_LASER_ON_TIME 32 +#define DEF_LASER_OFF_TIME 32 + +/* + * MPCP protocol + */ +enum { + MPCP_OPCODE_PAUSE = 1, + MPCP_OPCODE_GATE = 2, + MPCP_OPCODE_REPORT = 3, + MPCP_OPCODE_REGISTER_REQ = 4, + MPCP_OPCODE_REGISTER = 5, + MPCP_OPCODE_REGISTER_ACK = 6, +}; + +struct mpcp_hdr { + __be16 opcode; + __be32 timestamp; +} __packed; + +struct mpcp_grant_hdr { + __be32 start_time; + __be16 len; +} __packed; + +struct mpcp_gate { + u8 nb_grants_flags; + struct mpcp_grant_hdr grants[0]; +} __packed; + +#define MPCP_GATE_F_IS_DISC (1 << 3) + +struct mpcp_disc_gate { + u8 nb_grants_flags; + __be32 start_time; + __be16 length; + __be16 sync_time; +} __packed; + +enum { + MPCP_DISCINFO_1G_CAP = (1 << 0), + MPCP_DISCINFO_10G_CAP = (1 << 1), + + MPCP_DISCINFO_1G_WINDOW = (1 << 4), + MPCP_DISCINFO_10G_WINDOW = (1 << 5), +}; + +struct mpcp_disc_gate10g { + u8 nb_grants_flags; + __be32 start_time; + __be16 length; + __be16 sync_time; + __be16 disc_info; +} __packed; + +enum { + MPCP_REGREQ_F_REGISTER = 1, + MPCP_REGREQ_F_DEREGISTER = 3, +}; + +struct mpcp_register_req { + u8 flags; + u8 pending_grants; + /* remaining fields only in 10G, but since framed is zero + * padded, it does not matter if they are present or not, a 1G + * OLT won't make a difference between those and padding */ + __be16 disc_info; + u8 laser_on; + u8 laser_off; +} __packed; + + +enum { + MPCP_REG_F_REREGISTER = 1, + MPCP_REG_F_DEREGISTER = 2, + MPCP_REG_F_ACK = 3, + MPCP_REG_F_NACK = 4, +}; + +struct mpcp_register { + __be16 assigned_port; + u8 flags; + __be16 sync_time; + u8 echoed_pending_grants; +} __packed; + +struct mpcp_register10g { + __be16 assigned_port; + u8 flags; + __be16 sync_time; + u8 echoed_pending_grants; + u8 target_laser_on; + u8 target_laser_off; +} __packed; + + +enum { + MPCP_REGACK_F_NACK = 0, + MPCP_REGACK_F_ACK = 1, +}; + +struct mpcp_register_ack { + u8 flags; + __be16 echoed_assigned_port; + __be16 echoed_sync_time; +} __packed; + + +/* + * eponmac MIB + */ +struct eponmac_mib { + /* + * XPCS RX + */ + u64 xpcs_rx_framer_misbrst; + u64 xpcs_rx_framer_bd_err; + u64 xpcs_rx_64b66b_ipg_det; + u64 xpcs_rx_fec_nque_in; + u64 xpcs_rx_fec_nque_out; + u64 xpcs_rx_idle_start; + u64 xpcs_rx_idle_stop; + u64 xpcs_rx_fec_cw_fail; + u64 xpcs_rx_fec_cw_tot; + u64 xpcs_rx_fec_correct; + u64 xpcs_rx_fec_ones_cor; + u64 xpcs_rx_fec_zeros_cor; + u64 xpcs_rx_64b66b_fail; + u64 xpcs_rx_frmr_bad_sh; + u64 xpcs_rx_psudo; + u64 xpcs_rx_prbs; + u64 xpcs_rx_64b66b_start; + u64 xpcs_rx_idle_good_pkt; + u64 xpcs_rx_idle_err_pkt; + u64 xpcs_rx_64b66b_stop; + + /* + * XIF + */ + u64 xif_pmc_frame_rx; + u64 xif_pmc_byte_rx; + u64 xif_pmc_runt_rx; + u64 xif_pmc_cw_err_rx; + u64 xif_pmc_crc8_err_rx; + u64 xif_xpn_data_frm; + u64 xif_xpn_data_byte; + u64 xif_xpn_mpcp_frm; + u64 xif_xpn_oam_frm; + u64 xif_xpn_oam_byte; + u64 xif_xpn_oversize_frm; + u64 xif_sec_abort_frm; + u64 xif_pmc_tx_neg_event; + u64 xif_xpn_idle_pkt; + + /* + * LIF + */ + u64 lif_rx_line_code_err_cnt; + u64 lif_rx_agg_mpcp_frm; + u64 lif_rx_agg_good_frm; + u64 lif_rx_agg_good_byte; + u64 lif_rx_agg_undersz_frm; + u64 lif_rx_agg_oversz_frm; + u64 lif_rx_agg_crc8_frm; + u64 lif_rx_agg_fec_frm; + u64 lif_rx_agg_fec_byte; + u64 lif_rx_agg_fec_exc_err_frm; + u64 lif_rx_agg_nonfec_good_frm; + u64 lif_rx_agg_nonfec_good_byte; + u64 lif_rx_agg_err_bytes; + u64 lif_rx_agg_err_zeroes; + u64 lif_rx_agg_no_err_blks; + u64 lif_rx_agg_cor_blks; + u64 lif_rx_agg_uncor_blks; + u64 lif_rx_agg_err_ones; + u64 lif_rx_agg_err_frm; + u64 lif_tx_pkt_cnt; + u64 lif_tx_byte_cnt; + u64 lif_tx_non_fec_pkt_cnt; + u64 lif_tx_non_fec_byte_cnt; + u64 lif_tx_fec_pkt_cnt; + u64 lif_tx_fec_byte_cnt; + u64 lif_tx_fec_blk_cnt; + u64 lif_tx_mpcp_pkt_cnt; + + /* + * EPN RAM + */ + u64 epn00_rx_bytes; + u64 epn00_rx_fcs; + u64 epn00_rx_oam; + u64 epn00_rx_gate; + u64 epn00_rx_64; + u64 epn00_rx_65_127; + u64 epn00_rx_128_255; + u64 epn00_rx_256_511; + u64 epn00_rx_512_1023; + u64 epn00_rx_1024_1518; + u64 epn00_rx_1519_2047; + u64 epn00_rx_2048_4095; + u64 epn00_rx_4096_9216; + u64 epn00_rx_gt_9216; + u64 epn00_rx_oversize; + u64 epn00_rx_bcast; + u64 epn00_rx_mcast; + u64 epn00_rx_unicast; + u64 epn00_rx_undersized; + u64 epn00_rx_oam_bytes; + u64 epn00_rx_register; + u64 epn00_tx_bytes; + u64 epn00_tx_oam; + u64 epn00_tx_report; + u64 epn00_tx_64; + u64 epn00_tx_65_127; + u64 epn00_tx_128_255; + u64 epn00_tx_256_511; + u64 epn00_tx_512_1023; + u64 epn00_tx_1024_1518; + u64 epn00_tx_1519_2047; + u64 epn00_tx_2048_4095; + u64 epn00_tx_4096_9216; + u64 epn00_tx_gt_9216; + u64 epn00_tx_oam_bytes; + u64 epn00_tx_bcast; + u64 epn00_tx_mcast; + u64 epn00_tx_unicast; + + /* only used for mcast/bcast */ + u64 epn24_rx_bytes; + u64 epn24_rx_fcs; + u64 epn24_rx_bcast; + u64 epn24_rx_mcast; + u64 epn25_rx_bytes; + u64 epn25_rx_fcs; + u64 epn25_rx_bcast; + u64 epn25_rx_mcast; + u64 epn26_rx_bytes; + u64 epn26_rx_fcs; + u64 epn26_rx_bcast; + u64 epn26_rx_mcast; + u64 epn27_rx_bytes; + u64 epn27_rx_fcs; + u64 epn27_rx_bcast; + u64 epn27_rx_mcast; + u64 epn28_rx_bytes; + u64 epn28_rx_fcs; + u64 epn28_rx_bcast; + u64 epn28_rx_mcast; + u64 epn29_rx_bytes; + u64 epn29_rx_fcs; + u64 epn29_rx_bcast; + u64 epn29_rx_mcast; + u64 epn30_rx_bytes; + u64 epn30_rx_fcs; + u64 epn30_rx_bcast; + u64 epn30_rx_mcast; + u64 epn31_rx_bytes; + u64 epn31_rx_fcs; + u64 epn31_rx_bcast; + u64 epn31_rx_mcast; + + /* + * EPN reg + */ + u64 epn00_l1_acc_bytes; + u64 epn00_unused_tq; + u64 epn_unmap_big; + u64 epn_unmap_frame; + u64 epn_unmap_fcs; + u64 epn_unmap_gate; + u64 epn_unmap_oam; + u64 epn_unmap_small; + + /* + * registration + */ + u64 reg_mpcp_rx; + u64 reg_mpcp_rx_invalid; + u64 reg_mpcp_rx_unk_opcode; + u64 reg_mpcp_rx_disc; + u64 reg_mpcp_rx_disc_info_mismatch; + u64 reg_mpcp_rx_disc_late; + u64 reg_mpcp_rx_disc_last_slot; + u64 reg_mpcp_rx_reg_for_other; + u64 reg_mpcp_rx_reg_unk_flag; + u64 reg_mpcp_rx_reg_dereg; + u64 reg_mpcp_rx_reg_nack; + u64 reg_mpcp_rx_reg_timeout; + u64 reg_mpcp_rx_other_err; + u64 reg_mpcp_tx_reg_req; + u64 reg_mpcp_tx_reg_ack; + u64 reg_fsm_state; +}; + +struct epon_link { + unsigned int idx; + unsigned int llid; + bool rx_enabled; + bool tx_enabled; + struct list_head next; +}; + +struct epon_reg_config { + unsigned int laser_on_time; + unsigned int laser_off_time; + + bool valid_sync_time; + unsigned int sync_time; + + u16 assigned_llid; +}; + +struct epon_user_config { + u32 burst_cap; + bool down_enc_enabled; + u8 key_sci[8]; + u8 down_key0[16]; + u8 down_key1[16]; +}; + +/* + * global link status (PCS + time sync) + */ +enum epon_global_link_state { + EPON_GLINK_DOWN, + EPON_GLINK_UP, + EPON_GLINK_FAILED, +}; + +enum epon_registration_state { + EPON_REG_WAIT_DISCOVERY, + EPON_REG_WAIT_REGISTER, + EPON_REG_COMPLETE, + EPON_REG_FAILED, +}; + +struct xport_epon_priv { + struct xport_priv *port; + struct dentry *regs_dbg; + struct eponmac_mib mib; + struct workqueue_struct *epon_wq; + struct packet_type reg_tap; + + /* + * pon configuration, cannot be changed while epon is started + */ + u8 mac_addr[6]; + bool laser_active_hi; + + /* + * link list, empty when epon is not started + */ + struct mutex links_lock; + struct list_head links_list; + u32 links_free; + u32 links_mcast; + + struct mutex epon_lock; + bool epon_started; + unsigned int epon_reset_duration_ms; + + /* + * current epon state + */ + unsigned int down_speed; + unsigned int up_speed; + u32 start_count; + unsigned int lasermon_event_count; + struct epon_link *user_link; + struct epon_link *bcast_link; + struct delayed_work glob_link_work; + enum epon_global_link_state glob_link_state; + enum epon_registration_state reg_state; + unsigned long reg_state_last_change; + struct epon_reg_config reg_cfg; + struct epon_user_config user_cfg; +}; + +/* + * io accessors + */ +static inline u32 epon_top_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + EPON_TOP_OFFSET_0 + offset); +} + +static inline void epon_top_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + + EPON_TOP_OFFSET_0 + offset); +} + +static inline u32 epon_epn_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + EPN_OFFSET_0 + offset); +} + +static inline void epon_epn_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + EPN_OFFSET_0 + offset); +} + +static inline u32 epon_xif_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + XIF_OFFSET_0 + offset); +} + +static inline void epon_xif_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + XIF_OFFSET_0 + offset); +} + +static inline u32 epon_lif_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + LIF_OFFSET_0 + offset); +} + +static inline void epon_lif_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + LIF_OFFSET_0 + offset); +} + +static inline u32 epon_xpcsrx_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + XPCSRX_OFFSET_0 + offset); +} + +static inline void epon_xpcsrx_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + XPCSRX_OFFSET_0 + offset); +} + +static inline u32 epon_xpcstx_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + XPCSTX_OFFSET_0 + offset); +} + +static inline void epon_xpcstx_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + XPCSTX_OFFSET_0 + offset); +} + +void mode_epon_dbg_init(struct xport_epon_priv *mode); +void mode_epon_dbg_release(struct xport_epon_priv *mode); + +#endif /* PORT_XPORT_EPON_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon_dbg.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon_dbg.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon_dbg.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon_dbg.c 2023-03-09 15:06:11.360234118 +0100 @@ -0,0 +1,537 @@ +#include "port_xport_epon.h" + +enum { + REG_XPCS_RX, + REG_XIF, + REG_LIF, + REG_EPN, +}; + +struct reg_desc { + const char *name; + u32 offset; + unsigned int type; +}; + +static const struct reg_desc epon_regs[] = { + { "EPN_CONTROL_0", EPN_CONTROL_0_REG, REG_EPN, }, + { "EPN_CONTROL_1", EPN_CONTROL_1_REG, REG_EPN, }, + { "EPN_ENABLE_GRANTS", EPN_ENABLE_GRANTS_REG, REG_EPN, }, + { "EPN_DROP_DISC_GATES", EPN_DROP_DISC_GATES_REG, REG_EPN, }, + { "EPN_DIS_FCS_CHK", EPN_DIS_FCS_CHK_REG, REG_EPN, }, + { "EPN_PASS_GATES", EPN_PASS_GATES_REG, REG_EPN, }, + { "EPN_CFG_MISALGN_FB", EPN_CFG_MISALGN_FB_REG, REG_EPN, }, + { "EPN_DISCOVERY_FILTER", EPN_DISCOVERY_FILTER_REG, REG_EPN, }, + { "EPN_MINIMUM_GRANT_SETUP", EPN_MINIMUM_GRANT_SETUP_REG, REG_EPN, }, + { "EPN_RESET_GNT_FIFO", EPN_RESET_GNT_FIFO_REG, REG_EPN, }, + { "EPN_RESET_L1_ACCUMULATOR", EPN_RESET_L1_ACCUMULATOR_REG, REG_EPN, }, + { "EPN_L1_ACCUMULATOR_SEL", EPN_L1_ACCUMULATOR_SEL_REG, REG_EPN, }, + { "EPN_L1_SVA_BYTES", EPN_L1_SVA_BYTES_REG, REG_EPN, }, + { "EPN_L1_UVA_BYTES", EPN_L1_UVA_BYTES_REG, REG_EPN, }, + { "EPN_L1_SVA_OVERFLOW", EPN_L1_SVA_OVERFLOW_REG, REG_EPN, }, + { "EPN_L1_UVA_OVERFLOW", EPN_L1_UVA_OVERFLOW_REG, REG_EPN, }, + { "EPN_RESET_RPT_PRI", EPN_RESET_RPT_PRI_REG, REG_EPN, }, + { "EPN_RESET_L2_RPT_FIFO", EPN_RESET_L2_RPT_FIFO_REG, REG_EPN, }, + { "EPN_ENABLE_UPSTREAM", EPN_ENABLE_UPSTREAM_REG, REG_EPN, }, + { "EPN_ENABLE_UPSTREAM_FB", EPN_ENABLE_UPSTREAM_FB_REG, REG_EPN, }, + { "EPN_ENABLE_UPSTREAM_FEC", EPN_ENABLE_UPSTREAM_FEC_REG, REG_EPN, }, + { "EPN_REPORT_BYTE_LENGTH", EPN_REPORT_BYTE_LENGTH_REG, REG_EPN, }, + { "EPN_MAIN_INT_STATUS", EPN_MAIN_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_FULL_INT_STATUS", EPN_GNT_FULL_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_FULL_INT_MASK", EPN_GNT_FULL_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_MISS_INT_STATUS", EPN_GNT_MISS_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_MISS_INT_MASK", EPN_GNT_MISS_INT_MASK_REG, REG_EPN, }, + { "EPN_DISC_RX_INT_STATUS", EPN_DISC_RX_INT_STATUS_REG, REG_EPN, }, + { "EPN_DISC_RX_INT_MASK", EPN_DISC_RX_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_INTV_INT_STATUS", EPN_GNT_INTV_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_INTV_INT_MASK", EPN_GNT_INTV_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_FAR_INT_STATUS", EPN_GNT_FAR_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_FAR_INT_MASK", EPN_GNT_FAR_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_MISALGN_INT_STATUS", EPN_GNT_MISALGN_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_MISALGN_INT_MASK", EPN_GNT_MISALGN_INT_MASK_REG, REG_EPN, }, + { "EPN_NP_GNT_INT_STATUS", EPN_NP_GNT_INT_STATUS_REG, REG_EPN, }, + { "EPN_NP_GNT_INT_MASK", EPN_NP_GNT_INT_MASK_REG, REG_EPN, }, + { "EPN_DEL_STALE_INT_STATUS", EPN_DEL_STALE_INT_STATUS_REG, REG_EPN, }, + { "EPN_DEL_STALE_INT_MASK", EPN_DEL_STALE_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_PRES_INT_STATUS", EPN_GNT_PRES_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_PRES_INT_MASK", EPN_GNT_PRES_INT_MASK_REG, REG_EPN, }, + { "EPN_RPT_PRES_INT_STATUS", EPN_RPT_PRES_INT_STATUS_REG, REG_EPN, }, + { "EPN_RPT_PRES_INT_MASK", EPN_RPT_PRES_INT_MASK_REG, REG_EPN, }, + { "EPN_DRX_ABORT_INT_STATUS", EPN_DRX_ABORT_INT_STATUS_REG, REG_EPN, }, + { "EPN_DRX_ABORT_INT_MASK", EPN_DRX_ABORT_INT_MASK_REG, REG_EPN, }, + { "EPN_EMPTY_RPT_INT_STATUS", EPN_EMPTY_RPT_INT_STATUS_REG, REG_EPN, }, + { "EPN_EMPTY_RPT_INT_MASK", EPN_EMPTY_RPT_INT_MASK_REG, REG_EPN, }, + { "EPN_BCAP_OVERFLOW_INT_STATUS", EPN_BCAP_OVERFLOW_INT_STATUS_REG, REG_EPN, }, + { "EPN_BCAP_OVERFLOW_INT_MASK", EPN_BCAP_OVERFLOW_INT_MASK_REG, REG_EPN, }, + { "EPN_BBH_DNS_FAULT_INT_STATUS", EPN_BBH_DNS_FAULT_INT_STATUS_REG, REG_EPN, }, + { "EPN_BBH_DNS_FAULT_INT_MASK", EPN_BBH_DNS_FAULT_INT_MASK_REG, REG_EPN, }, + { "EPN_BBH_UPS_FAULT_INT_STATUS", EPN_BBH_UPS_FAULT_INT_STATUS_REG, REG_EPN, }, + { "EPN_BBH_UPS_FAULT_INT_MASK", EPN_BBH_UPS_FAULT_INT_MASK_REG, REG_EPN, }, + { "EPN_BBH_UPS_ABORT_INT_STATUS", EPN_BBH_UPS_ABORT_INT_STATUS_REG, REG_EPN, }, + { "EPN_BBH_UPS_ABORT_INT_MASK", EPN_BBH_UPS_ABORT_INT_MASK_REG, REG_EPN, }, + { "EPN_MAIN_INT_MASK", EPN_MAIN_INT_MASK_REG, REG_EPN, }, + { "EPN_MAX_GNT_SIZE", EPN_MAX_GNT_SIZE_REG, REG_EPN, }, + { "EPN_MAX_FRAME_SIZE", EPN_MAX_FRAME_SIZE_REG, REG_EPN, }, + { "EPN_GRANT_OVR_HD", EPN_GRANT_OVR_HD_REG, REG_EPN, }, + { "EPN_POLL_SIZE", EPN_POLL_SIZE_REG, REG_EPN, }, + { "EPN_DN_RD_GNT_MARGIN", EPN_DN_RD_GNT_MARGIN_REG, REG_EPN, }, + { "EPN_GNT_TIME_START_DELTA", EPN_GNT_TIME_START_DELTA_REG, REG_EPN, }, + { "EPN_TIME_STAMP_DIFF", EPN_TIME_STAMP_DIFF_REG, REG_EPN, }, + { "EPN_UP_TIME_STAMP_OFF", EPN_UP_TIME_STAMP_OFF_REG, REG_EPN, }, + { "EPN_GNT_INTERVAL", EPN_GNT_INTERVAL_REG, REG_EPN, }, + { "EPN_DN_GNT_MISALIGN_THR", EPN_DN_GNT_MISALIGN_THR_REG, REG_EPN, }, + { "EPN_DN_GNT_MISALIGN_PAUSE", EPN_DN_GNT_MISALIGN_PAUSE_REG, REG_EPN, }, + { "EPN_NON_POLL_INTV", EPN_NON_POLL_INTV_REG, REG_EPN, }, + { "EPN_FORCE_FCS_ERR", EPN_FORCE_FCS_ERR_REG, REG_EPN, }, + { "EPN_GRANT_OVERLAP_LIMIT", EPN_GRANT_OVERLAP_LIMIT_REG, REG_EPN, }, + { "EPN_AES_CONFIGURATION_0", EPN_AES_CFG_0_REG, REG_EPN, }, + { "EPN_DISC_GRANT_OVR_HD", EPN_DISC_GRANT_OVR_HD_REG, REG_EPN, }, + { "EPN_DN_DISCOVERY_SEED", EPN_DN_DISCOVERY_SEED_REG, REG_EPN, }, + { "EPN_DN_DISCOVERY_INC", EPN_DN_DISCOVERY_INC_REG, REG_EPN, }, + { "EPN_DN_DISCOVERY_SIZE", EPN_DN_DISCOVERY_SIZE_REG, REG_EPN, }, + { "EPN_FEC_IPG_LENGTH", EPN_FEC_IPG_LENGTH_REG, REG_EPN, }, + { "EPN_FAKE_REPORT_VALUE_EN", EPN_FAKE_REPORT_VALUE_EN_REG, REG_EPN, }, + { "EPN_FAKE_REPORT_VALUE", EPN_FAKE_REPORT_VALUE_REG, REG_EPN, }, + { "EPN_BURST_CAP_0", EPN_BURST_CAPx_0_7_REG(0), REG_EPN, }, + { "EPN_BURST_CAP_1", EPN_BURST_CAPx_0_7_REG(1), REG_EPN, }, + { "EPN_BURST_CAP_2", EPN_BURST_CAPx_0_7_REG(2), REG_EPN, }, + { "EPN_BURST_CAP_3", EPN_BURST_CAPx_0_7_REG(3), REG_EPN, }, + { "EPN_BURST_CAP_4", EPN_BURST_CAPx_0_7_REG(4), REG_EPN, }, + { "EPN_BURST_CAP_5", EPN_BURST_CAPx_0_7_REG(5), REG_EPN, }, + { "EPN_BURST_CAP_6", EPN_BURST_CAPx_0_7_REG(6), REG_EPN, }, + { "EPN_BURST_CAP_7", EPN_BURST_CAPx_0_7_REG(7), REG_EPN, }, + + { "EPN_QUEUE_LLID_MAP_0", EPN_QUEUE_LLID_MAPx_0_7_REG(0), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_1", EPN_QUEUE_LLID_MAPx_0_7_REG(1), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_2", EPN_QUEUE_LLID_MAPx_0_7_REG(2), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_3", EPN_QUEUE_LLID_MAPx_0_7_REG(3), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_4", EPN_QUEUE_LLID_MAPx_0_7_REG(4), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_5", EPN_QUEUE_LLID_MAPx_0_7_REG(5), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_6", EPN_QUEUE_LLID_MAPx_0_7_REG(6), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_7", EPN_QUEUE_LLID_MAPx_0_7_REG(7), REG_EPN, }, + + { "EPN_VALID_OPCODE_MAP", EPN_VALID_OPCODE_MAP_REG, REG_EPN, }, + { "EPN_UP_PACKET_TX_MARGIN", EPN_UP_PACKET_TX_MARGIN_REG, REG_EPN, }, + { "EPN_MULTI_PRI_CFG_0", EPN_MULTI_PRI_CFG_0_REG, REG_EPN, }, + { "EPN_SHARED_BCAP_OVRFLOW", EPN_SHARED_BCAP_OVRFLOW_REG, REG_EPN, }, + { "EPN_FORCED_REPORT_EN", EPN_FORCED_REPORT_EN_REG, REG_EPN, }, + { "EPN_FORCED_REPORT_MAX_INTERVAL", EPN_FORCED_REPORT_MAX_INTERVAL_REG, REG_EPN, }, + { "EPN_L2S_FLUSH_CONFIG", EPN_L2S_FLUSH_CONFIG_REG, REG_EPN, }, + { "EPN_DATA_PORT_COMMAND", EPN_DATA_PORT_COMMAND_REG, REG_EPN, }, + { "EPN_DATA_PORT_ADDRESS", EPN_DATA_PORT_ADDR_REG, REG_EPN, }, + { "EPN_DATA_PORT_DATA_0", EPN_DATA_PORT_DATA_0_REG, REG_EPN, }, + { "EPN_UNMAP_BIG_CNT", EPN_UNMAP_BIG_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_FRAME_CNT", EPN_UNMAP_FRAME_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_FCS_CNT", EPN_UNMAP_FCS_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_GATE_CNT", EPN_UNMAP_GATE_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_OAM_CNT", EPN_UNMAP_OAM_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_SMALL_CNT", EPN_UNMAP_SMALL_CNT_REG, REG_EPN, }, + { "EPN_FIF_DEQUEUE_EVENT_CNT", EPN_FIF_DEQUEUE_EVENT_CNT_REG, REG_EPN, }, + { "EPN_UNUSED_TQ_CNT0", EPN_UNUSED_TQ_CNTx_0_7_REG(0), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT1", EPN_UNUSED_TQ_CNTx_0_7_REG(1), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT2", EPN_UNUSED_TQ_CNTx_0_7_REG(2), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT3", EPN_UNUSED_TQ_CNTx_0_7_REG(3), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT4", EPN_UNUSED_TQ_CNTx_0_7_REG(4), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT5", EPN_UNUSED_TQ_CNTx_0_7_REG(5), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT6", EPN_UNUSED_TQ_CNTx_0_7_REG(6), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT7", EPN_UNUSED_TQ_CNTx_0_7_REG(7), REG_EPN, }, + + { "EPN_BBH_UP_FAULT_HALT_EN", EPN_BBH_UP_FAULT_HALT_EN_REG, REG_EPN, }, + { "EPN_BBH_UP_TARDY_HALT_EN", EPN_BBH_UP_TARDY_HALT_EN_REG, REG_EPN, }, + { "EPN_DEBUG_STATUS_0", EPN_DEBUG_STATUS_0_REG, REG_EPN, }, + { "EPN_DEBUG_STATUS_1", EPN_DEBUG_STATUS_1_REG, REG_EPN, }, + { "EPN_DEBUG_L2S_PTR_SEL", EPN_DEBUG_L2S_PTR_SEL_REG, REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_0", EPN_ONU_MAC_ADDRx_0_7_LO_REG(0), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_0", EPN_ONU_MAC_ADDRx_0_7_HI_REG(0), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_1", EPN_ONU_MAC_ADDRx_0_7_LO_REG(1), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_1", EPN_ONU_MAC_ADDRx_0_7_HI_REG(1), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_2", EPN_ONU_MAC_ADDRx_0_7_LO_REG(2), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_2", EPN_ONU_MAC_ADDRx_0_7_HI_REG(2), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_3", EPN_ONU_MAC_ADDRx_0_7_LO_REG(3), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_3", EPN_ONU_MAC_ADDRx_0_7_HI_REG(3), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_4", EPN_ONU_MAC_ADDRx_0_7_LO_REG(4), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_4", EPN_ONU_MAC_ADDRx_0_7_HI_REG(4), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_5", EPN_ONU_MAC_ADDRx_0_7_LO_REG(5), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_5", EPN_ONU_MAC_ADDRx_0_7_HI_REG(5), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_6", EPN_ONU_MAC_ADDRx_0_7_LO_REG(6), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_6", EPN_ONU_MAC_ADDRx_0_7_HI_REG(6), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_7", EPN_ONU_MAC_ADDRx_0_7_LO_REG(7), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_7", EPN_ONU_MAC_ADDRx_0_7_HI_REG(7), REG_EPN, }, + { "EPN_OLT_MAC_ADDR_LO", EPN_OLT_MAC_ADDR_LO_REG, REG_EPN, }, + { "EPN_OLT_MAC_ADDR_HI", EPN_OLT_MAC_ADDR_HI_REG, REG_EPN, }, + + { "EPN_TX_L1S_SHP_CONFIG_0", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_0", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_1", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_1", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_2", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_2", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_3", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_3", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_4", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_4", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_5", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_5", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_6", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_6", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_7", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(7), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_7", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(7), REG_EPN, }, + + { "EPN_TX_L1S_SHP_DQU_EMPTY", EPN_TX_L1S_SHP_DQU_EMPTY_REG, REG_EPN, }, + { "EPN_TX_L1S_UNSHAPED_EMPTY", EPN_TX_L1S_UNSHAPED_EMPTY_REG, REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_0", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_1", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_2", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_3", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_4", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_5", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_6", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_7", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(7), REG_EPN, }, + + { "EPN_TX_L2S_QUE_CONFIG_0", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_1", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_2", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_3", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_4", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_5", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_6", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_7", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(7), REG_EPN, }, + + { "EPN_TX_L2S_QUE_EMPTY", EPN_TX_L2S_QUE_EMPTY_REG, REG_EPN, }, + { "EPN_TX_L2S_QUE_FULL", EPN_TX_L2S_QUE_FULL_REG, REG_EPN, }, + { "EPN_TX_L2S_QUE_STOPPED", EPN_TX_L2S_QUE_STOPPED_REG, REG_EPN, }, + + { "EPN_TX_CTC_BURST_LIMIT_0", EPN_TX_CTC_BURST_LIMITx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_1", EPN_TX_CTC_BURST_LIMITx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_2", EPN_TX_CTC_BURST_LIMITx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_3", EPN_TX_CTC_BURST_LIMITx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_4", EPN_TX_CTC_BURST_LIMITx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_5", EPN_TX_CTC_BURST_LIMITx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_6", EPN_TX_CTC_BURST_LIMITx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_7", EPN_TX_CTC_BURST_LIMITx_0_7_REG(7), REG_EPN, }, + + { "EPN_BBH_MAX_OUTSTANDING_TARDY_PACKETS", EPN_BBH_MAX_OUTSTANDING_TARDY_PACKETS_REG, REG_EPN, }, + { "EPN_MIN_REPORT_VALUE_DIFFERENCE", EPN_MIN_REPORT_VALUE_DIFFERENCE_REG, REG_EPN, }, + { "EPN_BBH_STATUS_FIFO_OVERFLOW", EPN_BBH_STATUS_FIFO_OVERFLOW_REG, REG_EPN, }, + { "EPN_SPARE_CTL", EPN_SPARE_CTL_REG, REG_EPN, }, + { "EPN_TS_SYNC_OFFSET", EPN_TS_SYNC_OFFSET_REG, REG_EPN, }, + { "EPN_DN_TS_OFFSET", EPN_DN_TS_OFFSET_REG, REG_EPN, }, + { "EPN_UP_TS_OFFSET_LO", EPN_UP_TS_OFFSET_LO_REG, REG_EPN, }, + { "EPN_UP_TS_OFFSET_HI", EPN_UP_TS_OFFSET_HI_REG, REG_EPN, }, + { "EPN_TWO_STEP_TS_CTL", EPN_TWO_STEP_TS_CTL_REG, REG_EPN, }, + { "EPN_TWO_STEP_TS_VALUE_LO", EPN_TWO_STEP_TS_VALUE_LO_REG, REG_EPN, }, + { "EPN_TWO_STEP_TS_VALUE_HI", EPN_TWO_STEP_TS_VALUE_HI_REG, REG_EPN, }, + { "EPN_1588_TIMESTAMP_INT_STATUS", EPN_1588_TIMESTAMP_INT_STATUS_REG, REG_EPN, }, + { "EPN_1588_TIMESTAMP_INT_MASK", EPN_1588_TIMESTAMP_INT_MASK_REG, REG_EPN, }, + { "EPN_UP_PACKET_FETCH_MARGIN", EPN_UP_PACKET_FETCH_MARGIN_REG, REG_EPN, }, + { "EPN_DN_1588_TIMESTAMP", EPN_DN_1588_TIMESTAMP_REG, REG_EPN, }, + { "EPN_PERSISTENT_REPORT_CFG", EPN_PERSISTENT_REPORT_CFG_REG, REG_EPN, }, + { "EPN_PERSISTENT_REPORT_ENABLES", EPN_PERSISTENT_REPORT_ENABLES_REG, REG_EPN, }, + { "EPN_PERSISTENT_REPORT_REQUEST_SIZE", EPN_PERSISTENT_REPORT_REQUEST_SIZE_REG, REG_EPN, }, + { "EPN_AES_CONFIGURATION_1", EPN_AES_CFG_1_REG, REG_EPN, }, + + + /* + * LIF + */ + { "LIF_PON_CONTROL", LIF_PON_CONTROL_REG, REG_LIF, }, + { "LIF_PON_INTER_OP_CONTROL", LIF_PON_INTER_OP_CONTROL_REG , REG_LIF, }, + { "LIF_FEC_CONTROL", LIF_FEC_CONTROL_REG , REG_LIF, }, + { "LIF_SEC_CONTROL", LIF_SEC_CONTROL_REG , REG_LIF, }, + { "LIF_MACSEC", LIF_MACSEC_REG , REG_LIF, }, + { "LIF_INT_STATUS", LIF_INT_STATUS_REG , REG_LIF, }, + { "LIF_INT_MASK", LIF_INT_MASK_REG , REG_LIF, }, + { "LIF_DATA_PORT_COMMAND", LIF_DATA_PORT_COMMAND_REG , REG_LIF, }, + + { "LIF_LLID_0", LIF_LLIDx_0_7_REG(0), REG_LIF, }, + { "LIF_LLID_1", LIF_LLIDx_0_7_REG(1), REG_LIF, }, + { "LIF_LLID_2", LIF_LLIDx_0_7_REG(2), REG_LIF, }, + { "LIF_LLID_3", LIF_LLIDx_0_7_REG(3), REG_LIF, }, + { "LIF_LLID_4", LIF_LLIDx_0_7_REG(4), REG_LIF, }, + { "LIF_LLID_5", LIF_LLIDx_0_7_REG(5), REG_LIF, }, + { "LIF_LLID_6", LIF_LLIDx_0_7_REG(6), REG_LIF, }, + { "LIF_LLID_7", LIF_LLIDx_0_7_REG(7), REG_LIF, }, + { "LIF_LLID_16", LIF_LLIDx_16_23_REG(0), REG_LIF, }, + { "LIF_LLID_17", LIF_LLIDx_16_23_REG(1), REG_LIF, }, + { "LIF_LLID_18", LIF_LLIDx_16_23_REG(2), REG_LIF, }, + { "LIF_LLID_19", LIF_LLIDx_16_23_REG(3), REG_LIF, }, + { "LIF_LLID_20", LIF_LLIDx_16_23_REG(4), REG_LIF, }, + { "LIF_LLID_21", LIF_LLIDx_16_23_REG(5), REG_LIF, }, + { "LIF_LLID_22", LIF_LLIDx_16_23_REG(6), REG_LIF, }, + { "LIF_LLID_23", LIF_LLIDx_16_23_REG(7), REG_LIF, }, + + { "LIF_TIME_REF_CNT", LIF_TIME_REF_CNT_REG , REG_LIF, }, + { "LIF_TIMESTAMP_UPD_PER", LIF_TIMESTAMP_UPD_PER_REG , REG_LIF, }, + { "LIF_TP_TIME", LIF_TP_TIME_REG , REG_LIF, }, + { "LIF_MPCP_TIME", LIF_MPCP_TIME_REG , REG_LIF, }, + { "LIF_MAXLEN_CTR", LIF_MAXLEN_CTR_REG , REG_LIF, }, + { "LIF_LASER_ON_DELTA", LIF_LASER_ON_DELTA_REG , REG_LIF, }, + { "LIF_LASER_OFF_IDLE", LIF_LASER_OFF_IDLE_REG , REG_LIF, }, + { "LIF_FEC_INIT_IDLE", LIF_FEC_INIT_IDLE_REG , REG_LIF, }, + { "LIF_FEC_ERR_ALLOW", LIF_FEC_ERR_ALLOW_REG , REG_LIF, }, + { "LIF_SEC_KEY_SEL", LIF_SEC_KEY_SEL_REG , REG_LIF, }, + { "LIF_DN_ENCRYPT_STAT", LIF_DN_ENCRYPT_STAT_REG , REG_LIF, }, + { "LIF_SEC_UP_KEY_STAT", LIF_SEC_UP_KEY_STAT_REG , REG_LIF, }, + { "LIF_SEC_UP_ENCRYPT_STAT", LIF_SEC_UP_ENCRYPT_STAT_REG , REG_LIF, }, + { "LIF_SEC_UP_MPCP_OFFSET", LIF_SEC_UP_MPCP_OFFSET_REG , REG_LIF, }, + { "LIF_FEC_PER_LLID", LIF_FEC_PER_LLID_REG , REG_LIF, }, + { "LIF_RX_LINE_CODE_ERR_CNT", LIF_RX_LINE_CODE_ERR_CNT_REG , REG_LIF, }, + { "LIF_RX_AGG_MPCP_FRM", LIF_RX_AGG_MPCP_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_GOOD_FRM", LIF_RX_AGG_GOOD_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_GOOD_BYTE", LIF_RX_AGG_GOOD_BYTE_REG , REG_LIF, }, + { "LIF_RX_AGG_UNDERSZ_FRM", LIF_RX_AGG_UNDERSZ_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_OVERSZ_FRM", LIF_RX_AGG_OVERSZ_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_CRC8_FRM", LIF_RX_AGG_CRC8_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_FEC_FRM", LIF_RX_AGG_FEC_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_FEC_BYTE", LIF_RX_AGG_FEC_BYTE_REG , REG_LIF, }, + { "LIF_RX_AGG_FEC_EXC_ERR_FRM", LIF_RX_AGG_FEC_EXC_ERR_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_NONFEC_GOOD_FRM", LIF_RX_AGG_NONFEC_GOOD_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_NONFEC_GOOD_BYTE", LIF_RX_AGG_NONFEC_GOOD_BYTE_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_BYTES", LIF_RX_AGG_ERR_BYTES_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_ZEROES", LIF_RX_AGG_ERR_ZEROES_REG , REG_LIF, }, + { "LIF_RX_AGG_NO_ERR_BLKS", LIF_RX_AGG_NO_ERR_BLKS_REG , REG_LIF, }, + { "LIF_RX_AGG_COR_BLKS", LIF_RX_AGG_COR_BLKS_REG , REG_LIF, }, + { "LIF_RX_AGG_UNCOR_BLKS", LIF_RX_AGG_UNCOR_BLKS_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_ONES", LIF_RX_AGG_ERR_ONES_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_FRM", LIF_RX_AGG_ERR_FRM_REG , REG_LIF, }, + { "LIF_TX_PKT_CNT", LIF_TX_PKT_CNT_REG , REG_LIF, }, + { "LIF_TX_BYTE_CNT", LIF_TX_BYTE_CNT_REG , REG_LIF, }, + { "LIF_TX_NON_FEC_PKT_CNT", LIF_TX_NON_FEC_PKT_CNT_REG , REG_LIF, }, + { "LIF_TX_NON_FEC_BYTE_CNT", LIF_TX_NON_FEC_BYTE_CNT_REG , REG_LIF, }, + { "LIF_TX_FEC_PKT_CNT", LIF_TX_FEC_PKT_CNT_REG , REG_LIF, }, + { "LIF_TX_FEC_BYTE_CNT", LIF_TX_FEC_BYTE_CNT_REG , REG_LIF, }, + { "LIF_TX_FEC_BLK_CNT", LIF_TX_FEC_BLK_CNT_REG , REG_LIF, }, + { "LIF_TX_MPCP_PKT_CNT", LIF_TX_MPCP_PKT_CNT_REG , REG_LIF, }, + { "LIF_DEBUG_TX_DATA_PKT_CNT", LIF_DEBUG_TX_DATA_PKT_CNT_REG , REG_LIF, }, + { "LIF_FEC_LLID_STATUS", LIF_FEC_LLID_STATUS_REG , REG_LIF, }, + { "LIF_SEC_RX_TEK_IG_IV_LLID", LIF_SEC_RX_TEK_IG_IV_LLID_REG , REG_LIF, }, + { "LIF_PON_BER_INTERV_THRESH", LIF_PON_BER_INTERV_THRESH_REG , REG_LIF, }, + { "LIF_LSR_MON_A_CTRL", LIF_LSR_MON_A_CTRL_REG , REG_LIF, }, + { "LIF_LSR_MON_A_MAX_THR", LIF_LSR_MON_A_MAX_THR_REG , REG_LIF, }, + { "LIF_LSR_MON_A_BST_LEN", LIF_LSR_MON_A_BST_LEN_REG , REG_LIF, }, + { "LIF_LSR_MON_A_BST_CNT", LIF_LSR_MON_A_BST_CNT_REG , REG_LIF, }, + { "LIF_DEBUG_PON_SM", LIF_DEBUG_PON_SM_REG , REG_LIF, }, + { "LIF_DEBUG_FEC_SM", LIF_DEBUG_FEC_SM_REG , REG_LIF, }, + { "LIF_AE_PKTNUM_WINDOW", LIF_AE_PKTNUM_WINDOW_REG , REG_LIF, }, + { "LIF_AE_PKTNUM_THRESH", LIF_AE_PKTNUM_THRESH_REG , REG_LIF, }, + { "LIF_AE_PKTNUM_STAT", LIF_AE_PKTNUM_STAT_REG , REG_LIF, }, + + { "LIF_LLID_8", LIF_LLIDx_8_15_REG(0), REG_LIF, }, + { "LIF_LLID_9", LIF_LLIDx_8_15_REG(1), REG_LIF, }, + { "LIF_LLID_10", LIF_LLIDx_8_15_REG(2), REG_LIF, }, + { "LIF_LLID_11", LIF_LLIDx_8_15_REG(3), REG_LIF, }, + { "LIF_LLID_12", LIF_LLIDx_8_15_REG(4), REG_LIF, }, + { "LIF_LLID_13", LIF_LLIDx_8_15_REG(5), REG_LIF, }, + { "LIF_LLID_14", LIF_LLIDx_8_15_REG(6), REG_LIF, }, + { "LIF_LLID_15", LIF_LLIDx_8_15_REG(7), REG_LIF, }, + + { "LIF_LLID_24", LIF_LLIDx_24_31_REG(0), REG_LIF, }, + { "LIF_LLID_25", LIF_LLIDx_24_31_REG(1), REG_LIF, }, + { "LIF_LLID_26", LIF_LLIDx_24_31_REG(2), REG_LIF, }, + { "LIF_LLID_27", LIF_LLIDx_24_31_REG(3), REG_LIF, }, + { "LIF_LLID_28", LIF_LLIDx_24_31_REG(4), REG_LIF, }, + { "LIF_LLID_29", LIF_LLIDx_24_31_REG(5), REG_LIF, }, + { "LIF_LLID_30", LIF_LLIDx_24_31_REG(6), REG_LIF, }, + { "LIF_LLID_31", LIF_LLIDx_24_31_REG(7), REG_LIF, }, + + { "LIF_VLAN_TYPE", LIF_VLAN_TYPE_REG , REG_LIF, }, + { "LIF_P2P_AE_SCI_EN", LIF_P2P_AE_SCI_EN_REG , REG_LIF, }, + + { "LIF_P2P_AE_SCI_LO_0", LIF_P2P_AE_SCI_LOx_REG(0) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_0", LIF_P2P_AE_SCI_HIx_REG(0) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_1", LIF_P2P_AE_SCI_LOx_REG(1) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_1", LIF_P2P_AE_SCI_HIx_REG(1) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_2", LIF_P2P_AE_SCI_LOx_REG(2) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_2", LIF_P2P_AE_SCI_HIx_REG(2) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_3", LIF_P2P_AE_SCI_LOx_REG(3) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_3", LIF_P2P_AE_SCI_HIx_REG(3) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_4", LIF_P2P_AE_SCI_LOx_REG(4) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_4", LIF_P2P_AE_SCI_HIx_REG(4) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_5", LIF_P2P_AE_SCI_LOx_REG(5) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_5", LIF_P2P_AE_SCI_HIx_REG(5) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_6", LIF_P2P_AE_SCI_LOx_REG(6) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_6", LIF_P2P_AE_SCI_HIx_REG(6) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_7", LIF_P2P_AE_SCI_LOx_REG(7) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_7", LIF_P2P_AE_SCI_HIx_REG(7) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_8", LIF_P2P_AE_SCI_LOx_REG(8) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_8", LIF_P2P_AE_SCI_HIx_REG(8) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_9", LIF_P2P_AE_SCI_LOx_REG(9) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_9", LIF_P2P_AE_SCI_HIx_REG(9) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_10", LIF_P2P_AE_SCI_LOx_REG(10) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_10", LIF_P2P_AE_SCI_HIx_REG(10) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_11", LIF_P2P_AE_SCI_LOx_REG(11) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_11", LIF_P2P_AE_SCI_HIx_REG(11) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_12", LIF_P2P_AE_SCI_LOx_REG(12) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_12", LIF_P2P_AE_SCI_HIx_REG(12) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_13", LIF_P2P_AE_SCI_LOx_REG(13) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_13", LIF_P2P_AE_SCI_HIx_REG(13) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_14", LIF_P2P_AE_SCI_LOx_REG(14) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_14", LIF_P2P_AE_SCI_HIx_REG(14) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_15", LIF_P2P_AE_SCI_LOx_REG(15) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_15", LIF_P2P_AE_SCI_HIx_REG(15) , REG_LIF, }, + + { "LIF_SEC_UP_KEY_STAT_1", LIF_SEC_UP_KEY_STAT_1_REG , REG_LIF, }, + { "LIF_SEC_KEY_SEL_1", LIF_SEC_KEY_SEL_1_REG , REG_LIF, }, + { "LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL", LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_REG , REG_LIF, }, + { "LIF_P2P_AUTONEG_CONTROL", LIF_P2P_AUTONEG_CONTROL_REG , REG_LIF, }, + { "LIF_P2P_AUTONEG_STATUS", LIF_P2P_AUTONEG_STATUS_REG , REG_LIF, }, + + /* + * XIF + */ + { "XIF_CTL", XIF_CTL_REG, REG_XIF, }, + { "XIF_INT_STATUS", XIF_INT_STATUS_REG, REG_XIF, }, + { "XIF_INT_MASK", XIF_INT_MASK_REG, REG_XIF, }, + { "XIF_PORT_DATA_REG_0", XIF_PORT_DATA_REG(0), REG_XIF, }, + { "XIF_PORT_DATA_REG_1", XIF_PORT_DATA_REG(1), REG_XIF, }, + { "XIF_PORT_DATA_REG_2", XIF_PORT_DATA_REG(2), REG_XIF, }, + { "XIF_PORT_DATA_REG_3", XIF_PORT_DATA_REG(3), REG_XIF, }, + { "XIF_PORT_DATA_REG_4", XIF_PORT_DATA_REG(4), REG_XIF, }, + { "XIF_PORT_DATA_REG_5", XIF_PORT_DATA_REG(5), REG_XIF, }, + { "XIF_PORT_DATA_REG_6", XIF_PORT_DATA_REG(6), REG_XIF, }, + { "XIF_PORT_DATA_REG_7", XIF_PORT_DATA_REG(7), REG_XIF, }, + { "XIF_MACSEC", XIF_MACSEC_REG, REG_XIF, }, + { "XIF_XPN_XMT_OFFSET", XIF_XPN_XMT_OFFSET_REG, REG_XIF, }, + { "XIF_XPN_TIMESTAMP_OFFSET", XIF_XPN_TIMESTAMP_OFFSET_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_CTL", XIF_XPN_PKTGEN_CTL_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_LLID", XIF_XPN_PKTGEN_LLID_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_PKT_CNT", XIF_XPN_PKTGEN_PKT_CNT_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_PKT_SIZE", XIF_XPN_PKTGEN_PKT_SIZE_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_IPG", XIF_XPN_PKTGEN_IPG_REG, REG_XIF, }, + { "XIF_TS_JITTER_THRESH", XIF_TS_JITTER_THRESH_REG, REG_XIF, }, + { "XIF_TS_UPDATE", XIF_TS_UPDATE_REG, REG_XIF, }, + { "XIF_GNT_OVERHEAD", XIF_GNT_OVERHEAD_REG, REG_XIF, }, + { "XIF_DISCOVER_OVERHEAD", XIF_DISCOVER_OVERHEAD_REG, REG_XIF, }, + { "XIF_DISCOVER_INFO", XIF_DISCOVER_INFO_REG, REG_XIF, }, + { "XIF_XPN_OVERSIZE_THRESH", XIF_XPN_OVERSIZE_THRESH_REG, REG_XIF, }, + { "XIF_SECRX_KEYNUM", XIF_SECRX_KEYNUM_REG, REG_XIF, }, + { "XIF_SECRX_ENCRYPT", XIF_SECRX_ENCRYPT_REG, REG_XIF, }, + { "XIF_PMC_FRAME_RX_CNT", XIF_PMC_FRAME_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_BYTE_RX_CNT", XIF_PMC_BYTE_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_RUNT_RX_CNT", XIF_PMC_RUNT_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_CW_ERR_RX_CNT", XIF_PMC_CW_ERR_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_CRC8_ERR_RX_CNT", XIF_PMC_CRC8_ERR_RX_CNT_REG, REG_XIF, }, + { "XIF_XPN_DATA_FRM_CNT", XIF_XPN_DATA_FRM_CNT_REG, REG_XIF, }, + { "XIF_XPN_DATA_BYTE_CNT", XIF_XPN_DATA_BYTE_CNT_REG, REG_XIF, }, + { "XIF_XPN_MPCP_FRM_CNT", XIF_XPN_MPCP_FRM_CNT_REG, REG_XIF, }, + { "XIF_XPN_OAM_FRM_CNT", XIF_XPN_OAM_FRM_CNT_REG, REG_XIF, }, + { "XIF_XPN_OAM_BYTE_CNT", XIF_XPN_OAM_BYTE_CNT_REG, REG_XIF, }, + { "XIF_XPN_OVERSIZE_FRM_CNT", XIF_XPN_OVERSIZE_FRM_CNT_REG, REG_XIF, }, + { "XIF_SEC_ABORT_FRM_CNT", XIF_SEC_ABORT_FRM_CNT_REG, REG_XIF, }, + { "XIF_PMC_TX_NEG_EVENT_CNT", XIF_PMC_TX_NEG_EVENT_CNT_REG, REG_XIF, }, + { "XIF_XPN_IDLE_PKT_CNT", XIF_XPN_IDLE_PKT_CNT_REG, REG_XIF, }, + { "XIF_MAX_MPCP_UPDATE", XIF_MAX_MPCP_UPDATE_REG, REG_XIF, }, + { "XIF_IPG_INSERTION", XIF_IPG_INSERTION_REG, REG_XIF, }, + { "XIF_TRANSPORT_TIME", XIF_TRANSPORT_TIME_REG, REG_XIF, }, + { "XIF_MPCP_TIME", XIF_MPCP_TIME_REG, REG_XIF, }, + { "XIF_OVERLAP_GNT_OH", XIF_OVERLAP_GNT_OH_REG, REG_XIF, }, + { "XIF_MAC_MODE", XIF_MAC_MODE_REG, REG_XIF, }, + { "XIF_PMCTX_CTL", XIF_PMCTX_CTL_REG, REG_XIF, }, + { "XIF_SEC_CTL", XIF_SEC_CTL_REG, REG_XIF, }, + { "XIF_AE_PKTNUM_WINDOW", XIF_AE_PKTNUM_WINDOW_REG, REG_XIF, }, + { "XIF_AE_PKTNUM_THRESH", XIF_AE_PKTNUM_THRESH_REG, REG_XIF, }, + { "XIF_SECTX_KEYNUM", XIF_SECTX_KEYNUM_REG, REG_XIF, }, + { "XIF_SECTX_ENCRYPT", XIF_SECTX_ENCRYPT_REG, REG_XIF, }, + { "XIF_AE_PKTNUM_STAT", XIF_AE_PKTNUM_STAT_REG, REG_XIF, }, + { "XIF_MPCP_UPDATE", XIF_MPCP_UPDATE_REG, REG_XIF, }, + { "XIF_BURST_PRELAUNCH_OFFSET", XIF_BURST_PRELAUNCH_OFFSET_REG, REG_XIF, }, + { "XIF_VLAN_TYPE", XIF_VLAN_TYPE_REG, REG_XIF, }, + { "XIF_P2P_AE_SCI_EN", XIF_P2P_AE_SCI_EN_REG, REG_XIF, }, + { "XIF_SECTX_KEYNUM_1", XIF_SECTX_KEYNUM_1_REG, REG_XIF, }, + { "XIF_SECRX_KEYNUM_1", XIF_SECRX_KEYNUM_1_REG, REG_XIF, }, +}; + +/* + * regs dump functions + */ +static void *regs_dump_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos < ARRAY_SIZE(epon_regs)) ? pos : NULL; +} + +static void *regs_dump_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return (++(*pos) < ARRAY_SIZE(epon_regs)) ? pos : NULL; +} + +static void regs_dump_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int regs_dump_seq_show(struct seq_file *s, void *v) +{ + struct xport_epon_priv *mode = s->private; + const struct reg_desc *rdesc; + int i = *(loff_t *)v; + u32 val; + + rdesc = &epon_regs[i]; + switch (rdesc->type) { + case REG_EPN: + val = epon_epn_reg_readl(mode, rdesc->offset); + break; + case REG_LIF: + val = epon_lif_reg_readl(mode, rdesc->offset); + break; + case REG_XIF: + val = epon_xif_reg_readl(mode, rdesc->offset); + break; + default: + BUG(); + break; + } + + seq_printf(s, "%-40s\t0x%08x\n", + rdesc->name, val); + + return 0; +} + +static const struct seq_operations regs_dump_seq_ops = { + .start = regs_dump_seq_start, + .next = regs_dump_seq_next, + .stop = regs_dump_seq_stop, + .show = regs_dump_seq_show, +}; + +static int regs_dump_open(struct inode *inode, struct file *filep) +{ + struct xport_epon_priv *mode = inode->i_private; + int ret; + + ret = seq_open(filep, ®s_dump_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = mode; + return 0; +} + +static const struct file_operations regs_dump_fops = { + .owner = THIS_MODULE, + .open = regs_dump_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +void mode_epon_dbg_init(struct xport_epon_priv *mode) +{ + char name[32]; + + snprintf(name, sizeof(name), "epon_regs"); + mode->regs_dbg = debugfs_create_file(name, 0400, + bcm63158_dbg_root, + mode, + ®s_dump_fops); + +} + +void mode_epon_dbg_release(struct xport_epon_priv *mode) +{ + if (mode->regs_dbg) + debugfs_remove(mode->regs_dbg); +} diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_serdes.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_serdes.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_serdes.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_serdes.c 2023-05-31 17:11:03.413680496 +0200 @@ -0,0 +1,1686 @@ +#include "port_xport.h" +#include "regs/wan_top.h" +#include "regs/serdes_regs.h" + +#undef DUMP_SERDES_IO + +#ifdef DUMP_SERDES_IO +struct reg_dump_desc { + const char *name; + unsigned int reg; + bool skip_dump; + bool skip_consec; +}; + +const struct reg_dump_desc wan_top_regs[] = { + { "SCRATCH_REG", + WAN_TOP_SCRATCH_REG, }, + { "RESET_REG", + WAN_TOP_RESET_REG, }, + { "GPON_GEARBOX_0_REG", + WAN_TOP_GPON_GEARBOX_0_REG, }, + { "GPON_PATTERN_CFG1_REG", + WAN_TOP_GPON_PATTERN_CFG1_REG, }, + { "GPON_PATTERN_CFG2_REG", + WAN_TOP_GPON_PATTERN_CFG2_REG, }, + { "GPON_GEARBOX_2_REG", + WAN_TOP_GPON_GEARBOX_2_REG, }, + { "EARLY_TXEN_TXEN_REG", + WAN_TOP_EARLY_TXEN_TXEN_REG, }, + { "RESCAL_AL_CFG_REG", + WAN_TOP_RESCAL_AL_CFG_REG, }, + { "RESCAL_STATUS_0_REG", + WAN_TOP_RESCAL_STATUS_0_REG, }, + { "RESCAL_STATUS_1_REG", + WAN_TOP_RESCAL_STATUS_1_REG, }, + { "MISC_0_REG", + WAN_TOP_MISC_0_REG, }, + { "MISC_1_REG", + WAN_TOP_MISC_1_REG, }, + { "MISC_2_REG", + WAN_TOP_MISC_2_REG, }, + { "MISC_3_REG", + WAN_TOP_MISC_3_REG, }, + { "MISC_4_REG", + WAN_TOP_MISC_4_REG, }, + { "SERDES_PLL_CTL_REG", + WAN_TOP_SERDES_PLL_CTL_REG, }, + { "SERDES_TEMP_CTL_REG", + WAN_TOP_SERDES_TEMP_CTL_REG, }, + { "SERDES_PRAM_CTL_REG", + WAN_TOP_SERDES_PRAM_CTL_REG, }, + { "SERDES_PRAM_CTL_2_REG", + WAN_TOP_SERDES_PRAM_CTL_2_REG, }, + { "SERDES_PRAM_CTL_3_REG", + WAN_TOP_SERDES_PRAM_CTL_3_REG, }, + { "PMI_LP_0_REG", + WAN_TOP_PMI_LP_0_REG, true }, + { "PMI_LP_1_REG", + WAN_TOP_PMI_LP_1_REG, true }, + { "PMI_LP_2_REG", + WAN_TOP_PMI_LP_2_REG, true }, + { "PMI_LP_3_REG", + WAN_TOP_PMI_LP_3_REG, true }, + { "PMI_LP_4_REG", + WAN_TOP_PMI_LP_4_REG, true }, + { "TOD_CONFIG_0_REG", + WAN_TOP_TOD_CONFIG_0_REG, }, + { "TOD_CONFIG_1_REG", + WAN_TOP_TOD_CONFIG_1_REG, }, + { "TOD_CONFIG_2_REG", + WAN_TOP_TOD_CONFIG_2_REG, }, + { "TOD_CONFIG_3_REG", + WAN_TOP_TOD_CONFIG_3_REG, }, + { "TOD_CONFIG_4_REG", + WAN_TOP_TOD_CONFIG_4_REG, }, + { "TOD_CONFIG_5_REG", + WAN_TOP_TOD_CONFIG_5_REG, }, + { "TOD_TS48_MSB_REG", + WAN_TOP_TOD_TS48_MSB_REG, }, + { "TOD_TS48_LSB_REG", + WAN_TOP_TOD_TS48_LSB_REG, }, + { "TOD_TS64_MSB_REG", + WAN_TOP_TOD_TS64_MSB_REG, }, + { "TOD_TS64_LSB_REG", + WAN_TOP_TOD_TS64_LSB_REG, }, + { "TOD_STATUS_0_REG", + WAN_TOP_TOD_STATUS_0_REG, }, + { "TOD_STATUS_1_REG", + WAN_TOP_TOD_STATUS_1_REG, }, + { "SERDES_STATUS_REG", + WAN_TOP_SERDES_STATUS_REG, }, + { "INT_STATUS_REG", + WAN_TOP_INT_STATUS_REG, }, + { "INT_MASK_REG", + WAN_TOP_INT_MASK_REG, }, + { "CLK_DEJITTER_SAMPLING_CTL_0_REG", + WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_REG, }, + { "CLK_DEJITTER_SAMPLING_CTL_1_REG", + WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_REG, }, + { "CLK_SAMPLE_COUNTER_REG", + WAN_TOP_CLK_SAMPLE_COUNTER_REG, }, + { "SYNCE_PLL_CONFIG_REG", + WAN_TOP_SYNCE_PLL_CONFIG_REG, }, + { "OSR_CONTROL_REG", + WAN_TOP_OSR_CONTROL_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_STATUS_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_REG, }, + { "AE_GEARBOX_CONTROL_0_REG", + WAN_TOP_AE_GEARBOX_CONTROL_0_REG, }, + { "VOLTAGE_REGULATOR_DIVIDER_IDER_REG", + WAN_TOP_VOLTAGE_REGULATOR_DIVIDER_IDER_REG, }, + { "CLOCK_SYNC_CONFIG_REG", + WAN_TOP_CLOCK_SYNC_CONFIG_REG, }, + { "AEPCS_IEEE_REGID_REG", + WAN_TOP_AEPCS_IEEE_REGID_REG, }, + { "FORCE_LBE_CONTROL_REG", + WAN_TOP_FORCE_LBE_CONTROL_REG, }, + { "NGPON_GEARBOX_RX_CTL_0_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_0_REG, }, + { "NGPON_GEARBOX_RX_CTL_1_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_1_REG, }, + { "NGPON_GEARBOX_RX_CTL_2_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_2_REG, }, + { "NGPON_GEARBOX_RX_CTL_3_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_3_REG, }, + { "NGPON_GEARBOX_TX_CTL_REG", + WAN_TOP_NGPON_GEARBOX_TX_CTL_REG, }, + { "NGPON_GEARBOX_STATUS_REG", + WAN_TOP_NGPON_GEARBOX_STATUS_REG, }, + { "EPON_10G_GEARBOX_REG", + WAN_TOP_EPON_10G_GEARBOX_REG, }, +}; + +const struct reg_dump_desc serdes_regs[] = { + { "DSC_A_cdr_control_0", DSC_A_cdr_control_0 }, + { "DSC_A_cdr_control_1", DSC_A_cdr_control_1 }, + { "DSC_A_cdr_control_2", DSC_A_cdr_control_2 }, + { "DSC_A_rx_pi_control", DSC_A_rx_pi_control }, + { "DSC_A_cdr_status_integ_reg", DSC_A_cdr_status_integ_reg }, + { "DSC_A_cdr_status_phase_error", DSC_A_cdr_status_phase_error }, + { "DSC_A_rx_pi_cnt_bin_d", DSC_A_rx_pi_cnt_bin_d }, + { "DSC_A_rx_pi_cnt_bin_p", DSC_A_rx_pi_cnt_bin_p }, + { "DSC_A_rx_pi_cnt_bin_m", DSC_A_rx_pi_cnt_bin_m }, + { "DSC_A_rx_pi_diff_bin", DSC_A_rx_pi_diff_bin }, + { "DSC_A_trnsum_cntl_5", DSC_A_trnsum_cntl_5 }, + { "DSC_A_dsc_uc_ctrl", DSC_A_dsc_uc_ctrl }, + { "DSC_A_dsc_scratch", DSC_A_dsc_scratch }, + { "DSC_B_dsc_sm_ctrl_0", DSC_B_dsc_sm_ctrl_0 }, + { "DSC_B_dsc_sm_ctrl_1", DSC_B_dsc_sm_ctrl_1 }, + { "DSC_B_dsc_sm_ctrl_2", DSC_B_dsc_sm_ctrl_2 }, + { "DSC_B_dsc_sm_ctrl_3", DSC_B_dsc_sm_ctrl_3 }, + { "DSC_B_dsc_sm_ctrl_4", DSC_B_dsc_sm_ctrl_4 }, + { "DSC_B_dsc_sm_ctrl_5", DSC_B_dsc_sm_ctrl_5 }, + { "DSC_B_dsc_sm_ctrl_6", DSC_B_dsc_sm_ctrl_6 }, + { "DSC_B_dsc_sm_ctrl_7", DSC_B_dsc_sm_ctrl_7 }, + { "DSC_B_dsc_sm_ctrl_8", DSC_B_dsc_sm_ctrl_8 }, + { "DSC_B_dsc_sm_ctrl_9", DSC_B_dsc_sm_ctrl_9 }, + { "DSC_B_dsc_sm_status_dsc_lock", DSC_B_dsc_sm_status_dsc_lock }, + { "DSC_B_dsc_sm_status_dsc_state_one_hot", DSC_B_dsc_sm_status_dsc_state_one_hot }, + { "DSC_B_dsc_sm_status_dsc_state_eee_one_hot", DSC_B_dsc_sm_status_dsc_state_eee_one_hot }, + { "DSC_B_dsc_sm_status_restart", DSC_B_dsc_sm_status_restart }, + { "DSC_B_dsc_sm_status_dsc_state", DSC_B_dsc_sm_status_dsc_state }, + { "DSC_C_dfe_common_ctl", DSC_C_dfe_common_ctl }, + { "DSC_C_dfe_1_ctl", DSC_C_dfe_1_ctl }, + { "DSC_C_dfe_1_pat_ctl", DSC_C_dfe_1_pat_ctl }, + { "DSC_C_dfe_2_ctl", DSC_C_dfe_2_ctl }, + { "DSC_C_dfe_2_pat_ctl", DSC_C_dfe_2_pat_ctl }, + { "DSC_C_dfe_3_ctl", DSC_C_dfe_3_ctl }, + { "DSC_C_dfe_3_pat_ctl", DSC_C_dfe_3_pat_ctl }, + { "DSC_C_dfe_4_ctl", DSC_C_dfe_4_ctl }, + { "DSC_C_dfe_4_pat_ctl", DSC_C_dfe_4_pat_ctl }, + { "DSC_C_dfe_5_ctl", DSC_C_dfe_5_ctl }, + { "DSC_C_dfe_5_pat_ctl", DSC_C_dfe_5_pat_ctl }, + { "DSC_C_dfe_vga_override", DSC_C_dfe_vga_override }, + { "DSC_C_vga_ctl", DSC_C_vga_ctl }, + { "DSC_C_vga_pat_eyediag_ctl", DSC_C_vga_pat_eyediag_ctl }, + { "DSC_C_p1_frac_offs_ctl", DSC_C_p1_frac_offs_ctl }, + { "DSC_D_trnsum_ctl_1", DSC_D_trnsum_ctl_1 }, + { "DSC_D_trnsum_ctl_2", DSC_D_trnsum_ctl_2 }, + { "DSC_D_trnsum_ctl_3", DSC_D_trnsum_ctl_3 }, + { "DSC_D_trnsum_ctl_4", DSC_D_trnsum_ctl_4 }, + { "DSC_D_trnsum_sts_1", DSC_D_trnsum_sts_1 }, + { "DSC_D_trnsum_sts_2", DSC_D_trnsum_sts_2 }, + { "DSC_D_trnsum_sts_3", DSC_D_trnsum_sts_3 }, + { "DSC_D_trnsum_sts_4", DSC_D_trnsum_sts_4 }, + { "DSC_D_trnsum_sts_5", DSC_D_trnsum_sts_5 }, + { "DSC_D_trnsum_sts_6", DSC_D_trnsum_sts_6 }, + { "DSC_D_vga_p1eyediag_sts", DSC_D_vga_p1eyediag_sts }, + { "DSC_D_dfe_1_sts", DSC_D_dfe_1_sts }, + { "DSC_D_dfe_2_sts", DSC_D_dfe_2_sts }, + { "DSC_D_dfe_3_4_5_sts", DSC_D_dfe_3_4_5_sts }, + { "DSC_D_vga_tap_bin", DSC_D_vga_tap_bin }, + { "DSC_E_dsc_e_ctrl", DSC_E_dsc_e_ctrl }, + { "DSC_E_dsc_e_pf_ctrl", DSC_E_dsc_e_pf_ctrl }, + { "DSC_E_dsc_e_pf2_lowp_ctrl", DSC_E_dsc_e_pf2_lowp_ctrl }, + { "DSC_E_dsc_e_offset_adj_data_odd", DSC_E_dsc_e_offset_adj_data_odd }, + { "DSC_E_dsc_e_offset_adj_data_even", DSC_E_dsc_e_offset_adj_data_even }, + { "DSC_E_dsc_e_offset_adj_p1_odd", DSC_E_dsc_e_offset_adj_p1_odd }, + { "DSC_E_dsc_e_offset_adj_p1_even", DSC_E_dsc_e_offset_adj_p1_even }, + { "DSC_E_dsc_e_offset_adj_m1_odd", DSC_E_dsc_e_offset_adj_m1_odd }, + { "DSC_E_dsc_e_offset_adj_m1_even", DSC_E_dsc_e_offset_adj_m1_even }, + { "DSC_E_dsc_e_dc_offset", DSC_E_dsc_e_dc_offset }, + { "DSC_F_ONU10G_looptiming_ctrl_0", DSC_F_ONU10G_looptiming_ctrl_0 }, + { "TX_PI_LBE_tx_pi_control_0", TX_PI_LBE_tx_pi_control_0 }, + { "TX_PI_LBE_tx_pi_control_1", TX_PI_LBE_tx_pi_control_1 }, + { "TX_PI_LBE_tx_pi_control_2", TX_PI_LBE_tx_pi_control_2 }, + { "TX_PI_LBE_tx_pi_control_3", TX_PI_LBE_tx_pi_control_3 }, + { "TX_PI_LBE_tx_pi_control_4", TX_PI_LBE_tx_pi_control_4 }, + { "TX_PI_LBE_tx_pi_control_6", TX_PI_LBE_tx_pi_control_6 }, + { "TX_PI_LBE_tx_pi_status_0", TX_PI_LBE_tx_pi_status_0 }, + { "TX_PI_LBE_tx_pi_status_1", TX_PI_LBE_tx_pi_status_1 }, + { "TX_PI_LBE_tx_pi_status_2", TX_PI_LBE_tx_pi_status_2 }, + { "TX_PI_LBE_tx_pi_status_3", TX_PI_LBE_tx_pi_status_3 }, + { "TX_PI_LBE_tx_lbe_control_0", TX_PI_LBE_tx_lbe_control_0 }, + { "CKRST_CTRL_OSR_MODE_CONTROL", CKRST_CTRL_OSR_MODE_CONTROL }, + { "CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL }, + { "CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL", CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL }, + { "CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL }, + { "CKRST_CTRL_LANE_DEBUG_RESET_CONTROL", CKRST_CTRL_LANE_DEBUG_RESET_CONTROL }, + { "CKRST_CTRL_UC_ACK_LANE_CONTROL", CKRST_CTRL_UC_ACK_LANE_CONTROL }, + { "CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL", CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL }, + { "CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL", CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL }, + { "CKRST_CTRL_PMD_LANE_MODE_STATUS", CKRST_CTRL_PMD_LANE_MODE_STATUS }, + { "CKRST_CTRL_LANE_DP_RESET_STATE_STATUS", CKRST_CTRL_LANE_DP_RESET_STATE_STATUS }, + { "CKRST_CTRL_LN_MASK", CKRST_CTRL_LN_MASK }, + { "CKRST_CTRL_OSR_MODE_STATUS", CKRST_CTRL_OSR_MODE_STATUS }, + { "CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS", CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS }, + { "CKRST_CTRL_PLL_SELECT_CONTROL", CKRST_CTRL_PLL_SELECT_CONTROL }, + { "CKRST_CTRL_LN_S_RSTB_CONTROL", CKRST_CTRL_LN_S_RSTB_CONTROL }, + { "AMS_RX_RX_CONTROL_0", AMS_RX_RX_CONTROL_0 }, + { "AMS_RX_RX_CONTROL_1", AMS_RX_RX_CONTROL_1 }, + { "AMS_RX_RX_CONTROL_2", AMS_RX_RX_CONTROL_2 }, + { "AMS_RX_RX_CONTROL_3", AMS_RX_RX_CONTROL_3 }, + { "AMS_RX_RX_CONTROL_4", AMS_RX_RX_CONTROL_4 }, + { "AMS_RX_RX_INTCTRL", AMS_RX_RX_INTCTRL }, + { "AMS_RX_RX_STATUS", AMS_RX_RX_STATUS }, + { "AMS_TX_TX_CONTROL_0", AMS_TX_TX_CONTROL_0 }, + { "AMS_TX_TX_CONTROL_1", AMS_TX_TX_CONTROL_1 }, + { "AMS_TX_TX_CONTROL_2", AMS_TX_TX_CONTROL_2 }, + { "AMS_TX_TX_INTCTRL", AMS_TX_TX_INTCTRL }, + { "AMS_TX_TX_STATUS", AMS_TX_TX_STATUS }, + { "AMS_COM_PLL_CONTROL_0", AMS_COM_PLL_CONTROL_0 }, + { "AMS_COM_PLL_CONTROL_1", AMS_COM_PLL_CONTROL_1 }, + { "AMS_COM_PLL_CONTROL_2", AMS_COM_PLL_CONTROL_2 }, + { "AMS_COM_PLL_CONTROL_3", AMS_COM_PLL_CONTROL_3 }, + { "AMS_COM_PLL_CONTROL_4", AMS_COM_PLL_CONTROL_4 }, + { "AMS_COM_PLL_CONTROL_5", AMS_COM_PLL_CONTROL_5 }, + { "AMS_COM_PLL_CONTROL_6", AMS_COM_PLL_CONTROL_6 }, + { "AMS_COM_PLL_CONTROL_7", AMS_COM_PLL_CONTROL_7 }, + { "AMS_COM_PLL_CONTROL_8", AMS_COM_PLL_CONTROL_8 }, + { "AMS_COM_PLL_INTCTRL", AMS_COM_PLL_INTCTRL }, + { "AMS_COM_PLL_STATUS", AMS_COM_PLL_STATUS }, + { "SIGDET_SIGDET_CTRL_0", SIGDET_SIGDET_CTRL_0 }, + { "SIGDET_SIGDET_CTRL_1", SIGDET_SIGDET_CTRL_1 }, + { "SIGDET_SIGDET_CTRL_2", SIGDET_SIGDET_CTRL_2 }, + { "SIGDET_SIGDET_CTRL_3", SIGDET_SIGDET_CTRL_3 }, + { "SIGDET_SIGDET_STATUS_0", SIGDET_SIGDET_STATUS_0 }, + { "TLB_RX_prbs_chk_cnt_config", TLB_RX_prbs_chk_cnt_config }, + { "TLB_RX_prbs_chk_config", TLB_RX_prbs_chk_config }, + { "TLB_RX_dig_lpbk_config", TLB_RX_dig_lpbk_config }, + { "TLB_RX_tlb_rx_misc_config", TLB_RX_tlb_rx_misc_config }, + { "TLB_RX_prbs_chk_en_timer_control", TLB_RX_prbs_chk_en_timer_control }, + { "TLB_RX_dig_lpbk_pd_status", TLB_RX_dig_lpbk_pd_status }, + { "TLB_RX_prbs_chk_lock_status", TLB_RX_prbs_chk_lock_status }, + { "TLB_RX_prbs_chk_err_cnt_msb_status", TLB_RX_prbs_chk_err_cnt_msb_status }, + { "TLB_RX_prbs_chk_err_cnt_lsb_status", TLB_RX_prbs_chk_err_cnt_lsb_status }, + { "TLB_RX_pmd_rx_lock_status", TLB_RX_pmd_rx_lock_status }, + { "TLB_TX_patt_gen_config", TLB_TX_patt_gen_config }, + { "TLB_TX_prbs_gen_config", TLB_TX_prbs_gen_config }, + { "TLB_TX_rmt_lpbk_config", TLB_TX_rmt_lpbk_config }, + { "TLB_TX_tlb_tx_misc_config", TLB_TX_tlb_tx_misc_config }, + { "TLB_TX_tx_pi_loop_timing_config", TLB_TX_tx_pi_loop_timing_config }, + { "TLB_TX_rmt_lpbk_pd_status", TLB_TX_rmt_lpbk_pd_status }, + { "DIG_COM_REVID0", DIG_COM_REVID0 }, + { "DIG_COM_RESET_CONTROL_PMD", DIG_COM_RESET_CONTROL_PMD }, + { "DIG_COM_RESET_CONTROL_CORE_DP", DIG_COM_RESET_CONTROL_CORE_DP }, + { "DIG_COM_DEBUG_CONTROL", DIG_COM_DEBUG_CONTROL }, + { "DIG_COM_TOP_USER_CONTROL_0", DIG_COM_TOP_USER_CONTROL_0 }, + { "DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL", DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL }, + { "DIG_COM_RST_SEQ_TIMER_CONTROL", DIG_COM_RST_SEQ_TIMER_CONTROL }, + { "DIG_COM_CORE_DP_RESET_STATE_STATUS", DIG_COM_CORE_DP_RESET_STATE_STATUS }, + { "DIG_COM_REVID1", DIG_COM_REVID1 }, + { "DIG_COM_REVID2", DIG_COM_REVID2 }, + { "PATT_GEN_patt_gen_seq_0", PATT_GEN_patt_gen_seq_0 }, + { "PATT_GEN_patt_gen_seq_1", PATT_GEN_patt_gen_seq_1 }, + { "PATT_GEN_patt_gen_seq_2", PATT_GEN_patt_gen_seq_2 }, + { "PATT_GEN_patt_gen_seq_3", PATT_GEN_patt_gen_seq_3 }, + { "PATT_GEN_patt_gen_seq_4", PATT_GEN_patt_gen_seq_4 }, + { "PATT_GEN_patt_gen_seq_5", PATT_GEN_patt_gen_seq_5 }, + { "PATT_GEN_patt_gen_seq_6", PATT_GEN_patt_gen_seq_6 }, + { "PATT_GEN_patt_gen_seq_7", PATT_GEN_patt_gen_seq_7 }, + { "PATT_GEN_patt_gen_seq_8", PATT_GEN_patt_gen_seq_8 }, + { "PATT_GEN_patt_gen_seq_9", PATT_GEN_patt_gen_seq_9 }, + { "PATT_GEN_patt_gen_seq_10", PATT_GEN_patt_gen_seq_10 }, + { "PATT_GEN_patt_gen_seq_11", PATT_GEN_patt_gen_seq_11 }, + { "PATT_GEN_patt_gen_seq_12", PATT_GEN_patt_gen_seq_12 }, + { "PATT_GEN_patt_gen_seq_13", PATT_GEN_patt_gen_seq_13 }, + { "PATT_GEN_patt_gen_seq_14", PATT_GEN_patt_gen_seq_14 }, + { "TX_FED_txfir_control1", TX_FED_txfir_control1 }, + { "TX_FED_txfir_control2", TX_FED_txfir_control2 }, + { "TX_FED_txfir_control3", TX_FED_txfir_control3 }, + { "TX_FED_txfir_status1", TX_FED_txfir_status1 }, + { "TX_FED_txfir_status2", TX_FED_txfir_status2 }, + { "TX_FED_txfir_status3", TX_FED_txfir_status3 }, + { "TX_FED_txfir_status4", TX_FED_txfir_status4 }, + { "TX_FED_micro_control", TX_FED_micro_control }, + { "TX_FED_misc_control1", TX_FED_misc_control1 }, + { "TX_FED_txfir_control4", TX_FED_txfir_control4 }, + { "TX_FED_misc_status0", TX_FED_misc_status0 }, + { "PLL_CAL_COM_CTL_0", PLL_CAL_COM_CTL_0 }, + { "PLL_CAL_COM_CTL_1", PLL_CAL_COM_CTL_1 }, + { "PLL_CAL_COM_CTL_2", PLL_CAL_COM_CTL_2 }, + { "PLL_CAL_COM_CTL_3", PLL_CAL_COM_CTL_3 }, + { "PLL_CAL_COM_CTL_4", PLL_CAL_COM_CTL_4 }, + { "PLL_CAL_COM_CTL_5", PLL_CAL_COM_CTL_5 }, + { "PLL_CAL_COM_CTL_6", PLL_CAL_COM_CTL_6 }, + { "PLL_CAL_COM_CTL_7", PLL_CAL_COM_CTL_7 }, + { "PLL_CAL_COM_CTL_STATUS_0", PLL_CAL_COM_CTL_STATUS_0, false, false }, + { "PLL_CAL_COM_CTL_STATUS_1", PLL_CAL_COM_CTL_STATUS_1, false, false }, + { "TXCOM_CL72_tap_preset_control", TXCOM_CL72_tap_preset_control }, + { "TXCOM_CL72_debug_1_register", TXCOM_CL72_debug_1_register }, + { "CORE_PLL_COM_PMD_CORE_MODE_STATUS", CORE_PLL_COM_PMD_CORE_MODE_STATUS }, + { "CORE_PLL_COM_RESET_CONTROL_PLL_DP", CORE_PLL_COM_RESET_CONTROL_PLL_DP }, + { "CORE_PLL_COM_TOP_USER_CONTROL", CORE_PLL_COM_TOP_USER_CONTROL }, + { "CORE_PLL_COM_UC_ACK_CORE_CONTROL", CORE_PLL_COM_UC_ACK_CORE_CONTROL }, + { "CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS", CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS }, + { "CORE_PLL_COM_CORE_PLL_COM_STATUS_2", CORE_PLL_COM_CORE_PLL_COM_STATUS_2 }, + { "MICRO_A_ramword", MICRO_A_ramword }, + { "MICRO_A_address", MICRO_A_address }, + { "MICRO_A_command", MICRO_A_command }, + { "MICRO_A_ram_wrdata", MICRO_A_ram_wrdata }, + { "MICRO_A_ram_rddata", MICRO_A_ram_rddata }, + { "MICRO_A_download_status", MICRO_A_download_status }, + { "MICRO_A_sfr_status", MICRO_A_sfr_status }, + { "MICRO_A_mdio_uc_mailbox_msw", MICRO_A_mdio_uc_mailbox_msw }, + { "MICRO_A_mdio_uc_mailbox_lsw", MICRO_A_mdio_uc_mailbox_lsw }, + { "MICRO_A_uc_mdio_mailbox_lsw", MICRO_A_uc_mdio_mailbox_lsw }, + { "MICRO_A_command2", MICRO_A_command2 }, + { "MICRO_A_uc_mdio_mailbox_msw", MICRO_A_uc_mdio_mailbox_msw }, + { "MICRO_A_command3", MICRO_A_command3 }, + { "MICRO_A_command4", MICRO_A_command4 }, + { "MICRO_A_temperature_status", MICRO_A_temperature_status }, + { "MICRO_B_program_ram_control1", MICRO_B_program_ram_control1 }, + { "MICRO_B_dataram_control1", MICRO_B_dataram_control1 }, + { "MICRO_B_iram_control1", MICRO_B_iram_control1 }, + { "MDIO_MMDSEL_AER_COM_mdio_maskdata", MDIO_MMDSEL_AER_COM_mdio_maskdata }, + { "MDIO_MMDSEL_AER_COM_mdio_brcst_port_addr", MDIO_MMDSEL_AER_COM_mdio_brcst_port_addr }, + { "MDIO_MMDSEL_AER_COM_mdio_mmd_select", MDIO_MMDSEL_AER_COM_mdio_mmd_select }, + { "MDIO_MMDSEL_AER_COM_mdio_aer", MDIO_MMDSEL_AER_COM_mdio_aer }, + { "MDIO_BLK_ADDR_BLK_ADDR", MDIO_BLK_ADDR_BLK_ADDR }, +}; + +/* + * + */ +static const struct reg_dump_desc *find_wan_top_reg(unsigned int reg) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(wan_top_regs); i++) { + if (reg == wan_top_regs[i].reg) + return &wan_top_regs[i]; + } + return NULL; +} + +/* + * + */ +static const struct reg_dump_desc *find_serdes_reg(unsigned int reg) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(serdes_regs); i++) { + if (reg == serdes_regs[i].reg) + return &serdes_regs[i]; + } + return NULL; +} + +/* + * + */ +static void dump_wan_top_regs(struct xport_priv *port) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(wan_top_regs); i++) { + printk("%30s: %08x\n", + wan_top_regs[i].name, + wan_top_readl(port, wan_top_regs[i].reg)); + } +} +#endif + +/* + * + */ +static __maybe_unused const char *get_serdes_lane(unsigned int lane) +{ + static char buf[64]; + + buf[0] = 0; + if (lane & serdes_PLL_1) + strcat(buf, "PLL_1/"); + else + strcat(buf, "PLL_0/"); + + switch ((lane & LANE_BRDCST)) { + case LANE_0: + strcat(buf, "L0"); + break; + case LANE_1: + strcat(buf, "L1"); + break; + case LANE_2: + strcat(buf, "L2"); + break; + case LANE_3: + strcat(buf, "L3"); + break; + case LANE_BRDCST: + strcat(buf, "LBCAST"); + break; + default: + strcat(buf, "LUNKN"); + break; + } + return buf; +} + +/* + * + */ +static u32 __wan_top_readl(struct xport_priv *port, u32 reg) +{ + BUG_ON(reg >= port->regs_size[0]); + return readl(port->regs[0] + reg); +} + +/* + * + */ +static u32 wan_top_readl(struct xport_priv *port, u32 reg) +{ +#ifdef DUMP_SERDES_IO + const struct reg_dump_desc *d; +#endif + u32 val; + +#ifdef DUMP_SERDES_IO + d = find_wan_top_reg(reg); + BUG_ON(!d); +#endif + + BUG_ON(reg >= port->regs_size[0]); + val = readl(port->regs[0] + reg); +#ifdef DUMP_SERDES_IO + if (!d->skip_dump) + printk("wan_top_readl: %s => %x\n", d->name, val); +#endif + return val; +} + +/* + * + */ +static void wan_top_writel(struct xport_priv *port, u32 reg, u32 val) +{ + u32 reread; +#ifdef DUMP_SERDES_IO + u32 before; + const struct reg_dump_desc *d; +#endif + + BUG_ON(reg >= port->regs_size[0]); + +#ifdef DUMP_SERDES_IO + d = find_wan_top_reg(reg); + BUG_ON(!d); + before = __wan_top_readl(port, reg); +#endif + writel(val, port->regs[0] + reg); + +#ifdef DUMP_SERDES_IO + if (!d->skip_dump) + printk("wan_top_write: %s <= %x (prev %x)\n", + d->name, val, before); +#endif + + reread = __wan_top_readl(port, reg); + if (reread != val) + WARN(1, "failed to reread from reg:%u %08x != %08x\n", + reg, val, reread); +} + +/* + * + */ +static void wan_top_clear(struct xport_priv *port, u32 reg, u32 mask) +{ + u32 val; + + val = wan_top_readl(port, reg); + val &= ~mask; + wan_top_writel(port, reg, val); +} + +/* + * + */ +static void wan_top_set(struct xport_priv *port, u32 reg, u32 mask) +{ + u32 val; + + val = wan_top_readl(port, reg); + val |= mask; + wan_top_writel(port, reg, val); +} + +/* + * + */ +static int serdes_op_wait(struct xport_priv *port, + u32 status_reg, u32 *ret_val) +{ + size_t i; + + for (i = 0; i < 1000; i++) { + u32 val; + + val = wan_top_readl(port, status_reg); + if (!(val & WAN_TOP_PMI_LP_3_PMI_LP_ACK_MASK)) { + udelay(1); + continue; + } + + if (val & WAN_TOP_PMI_LP_3_PMI_LP_ERR_MASK) + return 2; + + *ret_val = val & WAN_TOP_PMI_LP_3_PMI_LP_RDDATA_MASK; + return 0; + } + + return 1; +} + +/* + * + */ +static int __serdes_read_reg(struct xport_priv *port, + u16 lane, u16 address, + bool is_misc, + bool no_dump) +{ + u32 val, status_reg; + int ret, wait_ret; +#ifdef DUMP_SERDES_IO + const struct reg_dump_desc *d; + static u32 last_reg; + + d = find_serdes_reg(address); + BUG_ON(!d); +#endif + + if (is_misc) + lane |= DEVID_1; + else + lane |= DEVID_0; + val = (lane << 16) | address; + wan_top_writel(port, WAN_TOP_PMI_LP_1_REG, val); + + if (is_misc) + val = WAN_TOP_PMI_LP_0_MISC_EN_MASK; + else + val = WAN_TOP_PMI_LP_0_PCS_EN_MASK; + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, val); + + if (is_misc) + status_reg = WAN_TOP_PMI_LP_3_REG; + else + status_reg = WAN_TOP_PMI_LP_4_REG; + + wait_ret = serdes_op_wait(port, status_reg, &ret); + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, 0); + udelay(5); + + if (wait_ret) { + /* FIXME */ + /* netdev_err(port->priv->netdev, */ + /* "serdes reg read failed: " */ + /* "ret:%d tgt:%s lane:%x address:%x\n", */ + /* wait_ret, */ + /* is_misc ? "misc" : "pcs", */ + /* lane, address); */ + return -1; + } + +#ifdef DUMP_SERDES_IO + if (!no_dump && !d->skip_dump) { + if (!d->skip_consec || + last_reg != ((lane << 16) | address)) { + /* printk("serdes_readl: %s %s <= %04x\n", */ + /* get_serdes_lane(lane), d->name, ret); */ + printk("serdes_readl: %04x@%04x <= %04x\n", + lane, address, ret); + } + last_reg = (lane << 16) | address; + } +#endif + + return ret; +} + +/* + * + */ +static int __serdes_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask, + bool is_misc) +{ + u32 val, status_reg; + u16 nmask = ~mask; + int ret, wait_ret; +#ifdef DUMP_SERDES_IO + const struct reg_dump_desc *d; + int old, reread; +#endif + + if (is_misc) + lane |= DEVID_1; + else + lane |= DEVID_0; + +#ifdef DUMP_SERDES_IO + d = find_serdes_reg(address); + BUG_ON(!d); + old = __serdes_read_reg(port, lane, address, is_misc, true); +#endif + + val = (lane << 16) | address; + wan_top_writel(port, WAN_TOP_PMI_LP_1_REG, val); + + val = (wrdata << WAN_TOP_PMI_LP_2_PMI_LP_WRDATA_SHIFT); + val |= (nmask << WAN_TOP_PMI_LP_2_PMI_LP_MASKDATA_SHIFT); + wan_top_writel(port, WAN_TOP_PMI_LP_2_REG, val); + + if (is_misc) + val = WAN_TOP_PMI_LP_0_MISC_EN_MASK; + else + val = WAN_TOP_PMI_LP_0_PCS_EN_MASK; + val |= WAN_TOP_PMI_LP_0_WRITE_MASK; + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, val); + udelay(5); + + if (is_misc) + status_reg = WAN_TOP_PMI_LP_3_REG; + else + status_reg = WAN_TOP_PMI_LP_4_REG; + + wait_ret = serdes_op_wait(port, status_reg, &ret); + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, 0); + udelay(5); + + if (wait_ret) { + netdev_err(port->priv->netdev, + "serdes reg write failed: ret:%d tgt:%s lane:%x " + "address:%x val/mask:%04x/%04x\n", + wait_ret, is_misc ? "misc" : "pcs", + lane, address, wrdata, mask); + return -1; + } + +#ifdef DUMP_SERDES_IO + reread = __serdes_read_reg(port, lane, address, is_misc, true); + if (!d->skip_dump) { + /* printk("serdes_write: %s %s <= %04x / %04x\n", */ + /* get_serdes_lane(lane), d->name, wrdata, mask); */ + printk("serdes_write: %04x@%04x (%04x/%04x): %04x -> %04x\n", + lane, address, wrdata, mask, old, reread); + } +#endif + return 0; +} + +/* + * + */ +static int serdes_misc_read_reg(struct xport_priv *port, + u16 lane, u16 address) +{ + return __serdes_read_reg(port, lane, address, true, false); +} + +/* + * + */ +static int serdes_misc_check_reg(struct xport_priv *port, + u16 lane, u16 address, u16 exp_value) +{ + int ret; + + ret = serdes_misc_read_reg(port, lane, address); + if (ret < 0) + return ret; + + if ((u16)ret != exp_value) { + WARN(1, "serdes check reg failed: address:%04x %04x != %08x\n", + address, ret, exp_value); + return -1; + } + return 0; +} + +/* + * + */ +static int serdes_misc_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask) +{ + return __serdes_write_reg(port, lane, address, wrdata, mask, true); +} + +/* + * + */ +static int serdes_misc_write_check_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask, + u16 exp_value) +{ + int ret; + + ret = __serdes_write_reg(port, lane, address, wrdata, mask, true); + if (ret < 0) + return ret; + return serdes_misc_check_reg(port, lane, address, exp_value); +} + +/* + * + */ +int xport_serdes_pcs_read_reg(struct xport_priv *port, + u16 lane, u16 address) +{ + return __serdes_read_reg(port, lane, address, false, false); +} + +/* + * + */ +int xport_serdes_pcs_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask) +{ + return __serdes_write_reg(port, lane, address, wrdata, mask, false); +} + +/* + * + */ +static int serdes_poll_pll_lock(struct xport_priv *port, + unsigned int pll_id) +{ + int ret; + size_t i; + + for (i = 0; i < 1000; i++) { + ret = serdes_misc_read_reg(port, pll_id, + PLL_CAL_COM_CTL_STATUS_0); + if (ret < 0) + return 1; + + if (ret & 0x0100) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "PLL %d lock timeout\n", pll_id); + return 1; +} + +/* + * + */ +static int serdes_poll_dsc_lock(struct xport_priv *port) + +{ + int ret; + size_t i; + + for (i = 0; i < 10000; i++) { + ret = serdes_misc_read_reg(port, LANE_0, + DSC_B_dsc_sm_status_dsc_lock); + if (ret < 0) + return 1; + + if (ret & 0x1) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "DSC lock timeout\n"); + return 1; +} + +/* + * + */ +static int serdes_poll_pmd_rx_lock(struct xport_priv *port) + +{ + int ret; + size_t i; + + for (i = 0; i < 10000; i++) { + ret = serdes_misc_read_reg(port, LANE_0, + TLB_RX_pmd_rx_lock_status); + if (ret < 0) + return 1; + + if (ret & 0x1) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "PMD rx lock timeout\n"); + return 1; +} + +/* + * + */ +static int wan_top_poll_pll_lock(struct xport_priv *port, + unsigned int pll_id) +{ + u32 val; + size_t i; + + for (i = 0; i < 10000; i++) { + u32 mask; + + val = wan_top_readl(port, WAN_TOP_SERDES_STATUS_REG); + + if (pll_id == serdes_PLL_0) + mask = WAN_TOP_SERDES_STATUS_PMD_PLL0_LOCK_MASK; + else + mask = WAN_TOP_SERDES_STATUS_PMD_PLL1_LOCK_MASK; + + if (val & mask) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "WAN TOP PLL %d lock timeout\n", + pll_id); + return 1; +} + +/* + * + */ +static void __serdes_lbe_op(struct xport_priv *port, + bool force, bool forced_value) +{ + u32 val; + + val = wan_top_readl(port, WAN_TOP_FORCE_LBE_CONTROL_REG); + + if (!force) { + val &= ~WAN_TOP_FORCE_LBE_CONTROL_OE_MASK; + val &= ~WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK; + val &= ~WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK; + val &= ~WAN_TOP_FORCE_LBE_CONTROL_MASK; + } else { + val |= WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK; + val |= WAN_TOP_FORCE_LBE_CONTROL_OE_MASK; + val |= WAN_TOP_FORCE_LBE_CONTROL_MASK; + + if (!forced_value) + val &= ~WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK; + else + val |= WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK; + } + + wan_top_writel(port, WAN_TOP_FORCE_LBE_CONTROL_REG, val); +} + +/* + * + */ +void xport_serdes_lbe_force_enable(struct xport_priv *port) +{ + __serdes_lbe_op(port, true, true); +} + +/* + * + */ +void xport_serdes_lbe_force_disable(struct xport_priv *port) +{ + __serdes_lbe_op(port, true, false); +} + +/* + * + */ +void xport_serdes_lbe_dont_force(struct xport_priv *port) +{ + __serdes_lbe_op(port, false, false); +} + +/* + * + */ +void xport_serdes_lbe_get_forced_state(struct xport_priv *port, + bool *force, bool *forced_value) +{ + u32 val; + + val = wan_top_readl(port, WAN_TOP_FORCE_LBE_CONTROL_REG); + *force = (val & WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK); + *forced_value = (val & WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK); +} + +/* + * + */ +static void set_clk90_offset(struct xport_priv *port, + uint8_t desired_m1_d_offset) +{ + u8 steps, count, d_location, now_m1_location, next_m1_location; + u16 rd_serdes; + + desired_m1_d_offset = desired_m1_d_offset % 64; + rd_serdes = serdes_misc_read_reg(port, LANE_0, DSC_A_rx_pi_cnt_bin_m); + now_m1_location = (rd_serdes & 0x7f); + d_location = (rd_serdes & 0x7f00) >> 8; + next_m1_location = d_location + desired_m1_d_offset; + + /* calculate number of movement steps and direction */ + if (next_m1_location >= now_m1_location) { + steps = next_m1_location - now_m1_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x4401, + 0x74ff); + } else { + steps = now_m1_location - next_m1_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x4001, + 0x74ff); + } + + /* move the Slicer(P) the required steps */ + for (count = 0; count < steps; count++) + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0200, + 0x0200); + + rd_serdes = serdes_misc_read_reg(port, LANE_0, DSC_A_rx_pi_cnt_bin_m); +#if 0 + d_location = (rd_serdes & 0x7f00) >> 8; + now_m1_location = (rd_serdes & 0x7f); + printk("0xd009 = 0x%04x\n", rd_serdes); + printk("d_location = %d\n", d_location); + printk("now_m1_location = %d\n", now_m1_location); + printk("Done Slicer-M1-Adjustment\n"); +#endif +} + +/* + * + */ +static void set_clkp1_offset(struct xport_priv *port, + u8 desired_p_d_offset) +{ + u8 step, count, d_location, now_p_location, next_p_location; + u16 rd_serdes; + + desired_p_d_offset = desired_p_d_offset % 64; + rd_serdes = serdes_misc_read_reg(port, LANE_0, + DSC_A_rx_pi_cnt_bin_d); + d_location = (rd_serdes & 0x7f); + now_p_location = (rd_serdes & 0x7f00) >> 8; + next_p_location = d_location + desired_p_d_offset; + + /* calculate number of movement steps and direction */ + if (next_p_location >= now_p_location) { + step = next_p_location - now_p_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x2401, + 0x74ff); + } else { + step = now_p_location - next_p_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x2001, + 0x74ff); + } + + /* move the Slicer(P) the required steps */ + for (count = 0; count < step; count++) + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0200, + 0x0200); + + rd_serdes = serdes_misc_read_reg(port, LANE_0, DSC_A_rx_pi_cnt_bin_d); +#if 0 + d_location = (rd_serdes & 0x7f); + now_p_location = (rd_serdes & 0x7f00) >> 8; + printk("0xd007 = 0x%04x\n", rd_serdes); + printk("d_location = %d\n", d_location); + printk("now_p_location = %d\n", now_p_location); + printk("Done Slicer-P-Adjustment\n"); +#endif +} + +/* + * + */ +static void rx_pi_spacing(struct xport_priv *port, + u8 desired_m1_d_offset, + u8 desired_p_d_offset) +{ + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0800, + 0x0800); + set_clk90_offset(port, desired_m1_d_offset); + set_clkp1_offset(port, desired_p_d_offset); + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0000, + 0x7800); +} + +/* + * + */ +static void xport_serdes_reset_ctl(struct xport_priv *port, + bool do_assert) +{ + u32 val; + + /* assert & deassert all reset (from bcm code) */ + val = WAN_TOP_MISC_2_PMD_POR_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_1_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_0_DP_H_RSTB_MASK; + if (do_assert) + wan_top_writel(port, WAN_TOP_MISC_2_REG, 0); + else + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); +} + +/* + * + */ +int xport_serdes_set_params(struct xport_priv *port, + const struct serdes_params *params, + const struct serdes_misc3_params *m3params) +{ + u32 val; + u16 wr_data, wr_mask; + + /* + * init WAN TOP block + */ + xport_serdes_reset_ctl(port, true); + udelay(10); + xport_serdes_reset_ctl(port, false); + udelay(10); + + /* rescal reset */ + /* FIXME: first two lines from xgae driver only */ + /* val = WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_PWRDN_MASK; */ + /* wan_top_writel(port, WAN_TOP_RESCAL_AL_CFG_REG, val); */ + val = WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_RSTB_MASK; + wan_top_writel(port, WAN_TOP_RESCAL_AL_CFG_REG, val); + udelay(100); + val = wan_top_readl(port, WAN_TOP_RESCAL_STATUS_0_REG); + if (!(val & WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_DONE_MASK)) { + netdev_err(port->priv->netdev, "rescal status is not done\n"); + return 1; + } + if (!(val & WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_VALID_MASK)) { + netdev_err(port->priv->netdev, "rescal status is not valid\n"); + return 1; + } + + /* make sure we reset forced state of LBE */ + xport_serdes_lbe_dont_force(port); + + /* test scratch registers */ + wan_top_writel(port, WAN_TOP_SCRATCH_REG, 0x01234567); + wan_top_writel(port, WAN_TOP_SCRATCH_REG, 0x89abcdef); + + /* assert all resets */ + wan_top_writel(port, WAN_TOP_MISC_2_REG, 0); + udelay(5); + + /* reset all remaining registers (xgae driver) */ + wan_top_writel(port, WAN_TOP_MISC_0_REG, 0); + wan_top_writel(port, WAN_TOP_MISC_1_REG, 0); + wan_top_writel(port, WAN_TOP_MISC_2_REG, 0); + wan_top_writel(port, WAN_TOP_MISC_3_REG, 0); + wan_top_writel(port, WAN_TOP_SERDES_PLL_CTL_REG, 0); + wan_top_writel(port, WAN_TOP_SERDES_PRAM_CTL_REG, 0); + wan_top_writel(port, WAN_TOP_OSR_CONTROL_REG, 0); + udelay(5); + + /* set correct refclk (LCREF 50Mhz refclock) */ + val = WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_REFIN_EN_MASK | + WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_REFIN_EN_MASK | + WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_LCREF_SEL_MASK; + wan_top_writel(port, WAN_TOP_SERDES_PLL_CTL_REG, val); + + /* wait for clock to be stable */ + mdelay(10); + + /* de-assert resets */ + val = WAN_TOP_MISC_2_PMD_POR_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_1_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_0_DP_H_RSTB_MASK; + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); + + /* disable laser while we change config */ + wan_top_clear(port, WAN_TOP_MISC_3_REG, WAN_TOP_MISC_3_LASER_OE_MASK); + + /* set oversample mode */ + val = wan_top_readl(port, WAN_TOP_MISC_2_REG); + val &= ~WAN_TOP_MISC_2_PMD_RX_OSR_MODE_MASK; + val &= ~WAN_TOP_MISC_2_PMD_TX_OSR_MODE_MASK; + val |= params->rx_osr_mode << WAN_TOP_MISC_2_PMD_RX_OSR_MODE_SHIFT; + val |= params->tx_osr_mode << WAN_TOP_MISC_2_PMD_TX_OSR_MODE_SHIFT; + /* FIXME: this is AE_25 in PON driver, dunno what it is*/ +// val |= (1 << 24); + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); + + /* set correct interface */ + val = wan_top_readl(port, WAN_TOP_MISC_3_REG); + val |= m3params->misc3_if_select << WAN_TOP_MISC_3_WAN_IFSELECT_SHIFT; + val |= m3params->misc3_laser_mode << WAN_TOP_MISC_3_LASER_MODE_SHIFT; + if (m3params->misc3_sgmii) + val |= WAN_TOP_MISC_3_SGMII_MODE_MASK; + wan_top_writel(port, WAN_TOP_MISC_3_REG, val); + + /* set epon gearbox configuration */ + if (!params->do_ae) { + val = wan_top_readl(port, WAN_TOP_EPON_10G_GEARBOX_REG); + val |= WAN_TOP_EPON_10G_GEARBOX_RX_CGEN_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_TX_CGEN_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_RX_GBOX_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_TX_GBOX_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_CLK_EN_MASK; + wan_top_writel(port, WAN_TOP_EPON_10G_GEARBOX_REG, val); + udelay(10); + } + + /* set OSR gearbox */ + val = wan_top_readl(port, WAN_TOP_OSR_CONTROL_REG); + val &= ~WAN_TOP_OSR_CFG_GPON_RX_CLK_MASK; + val |= (2 << WAN_TOP_OSR_CFG_GPON_RX_CLK_SHIFT); + wan_top_writel(port, WAN_TOP_OSR_CONTROL_REG, val); + + /* + * now init serdes + */ + + /* sanity check */ + serdes_misc_write_check_reg(port, LANE_BRDCST, DIG_COM_REVID0, + 0x0000, 0xffff, 0x42e5); + serdes_misc_write_check_reg(port, LANE_BRDCST, DIG_COM_REVID1, + 0x0000, 0xffff, 0x1034); + serdes_misc_write_check_reg(port, LANE_BRDCST, DIG_COM_REVID2, + 0x0000, 0xffff, 0x0000); + serdes_misc_write_check_reg(port, LANE_BRDCST, + MDIO_MMDSEL_AER_COM_mdio_maskdata, + 0x0000, 0xffff, 0x0000); + serdes_misc_write_check_reg(port, LANE_BRDCST, + MDIO_MMDSEL_AER_COM_mdio_maskdata, + 0xaaaa, 0xffff, 0xaaaa); + serdes_misc_write_check_reg(port, LANE_BRDCST, + MDIO_MMDSEL_AER_COM_mdio_maskdata, + 0x5555, 0xffff, 0x5555); + + /* make sure PLL0 is used for tx and PLL1 for rx in dual pll + * mode */ + BUG_ON(params->tx_pll_id > params->rx_pll_id); + BUG_ON(params->tx_pll_id == params->rx_pll_id && + params->tx_pll_id != serdes_PLL_0); + + /* power up needed PLL */ + serdes_misc_write_reg(port, LANE_0 | params->tx_pll_id, + AMS_COM_PLL_INTCTRL, + 0, + (1 << 2)); + + if (params->rx_pll_id != params->tx_pll_id) { + serdes_misc_write_reg(port, LANE_0 | params->rx_pll_id, + AMS_COM_PLL_INTCTRL, + 0, + (1 << 2)); + } else { + /* make sure second pll is disabled */ + serdes_misc_write_reg(port, LANE_0 | serdes_PLL_1, + AMS_COM_PLL_INTCTRL, + (1 << 2), + (1 << 2)); + } + + /* select PLL for tx clock (0 => PLL0, 1 => PLL1) */ + serdes_misc_write_reg(port, LANE_BRDCST, + CKRST_CTRL_PLL_SELECT_CONTROL, + (params->tx_pll_id == serdes_PLL_1) ? (1 << 0) : 0, + (1 << 0)); + + /* select PLL for rx clock (0 => PLL0, 1 => PLL1) */ + serdes_misc_write_reg(port, LANE_BRDCST, + CKRST_CTRL_PLL_SELECT_CONTROL, + (params->rx_pll_id == serdes_PLL_1) ? (1 << 1) : 0, + (1 << 1)); + + // TX AMS_COM_PLL_CONTROL_1 + wr_data = (((params->tx_pll_vco_div4 << 7) & (0x0001 << 7)) | + ((params->tx_pll_vco_div2 << 6) & (0x0001 << 6))); + wr_mask = (0x0001 << 7) | + (0x0001 << 6); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_1, + wr_data, + wr_mask); + + // TX AMS_COM_PLL_CONTROL_4 + wr_data = (((params->tx_pll_force_kvh_bw << 14) & (0x0001 << 14)) | + ((params->tx_pll_kvh_force << 12) & (0x0003 << 12)) | + ((params->tx_pll_2rx_bw << 8) & (0x0003 << 8))); + wr_mask = (0x0001 << 14) | + (0x0003 << 12) | + (0x0003 << 8); + serdes_misc_write_reg(port, + params->tx_pll_id, + AMS_COM_PLL_CONTROL_4, + wr_data, + wr_mask); + + // TX AMS_COM_PLL_CONTROL_7 + wr_data = (((params->tx_pll_fracn_div & 0xffff) << 0) & (0xffff << 0)); + wr_mask = (0xffff << 0); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_7, + wr_data, + wr_mask); + + // TX AMS_COM_PLL_CONTROL_8 + wr_data = (((params->tx_pll_fracn_sel << 15) & (0x0001 << 15)) | + ((params->tx_pll_ditheren << 14) & (0x0001 << 14)) | + ((params->tx_pll_fracn_ndiv << 4) & (0x03ff << 4)) | + ((((params->tx_pll_fracn_div & 0x30000) >> 16) << 0) & (0x0003 << 0))); + wr_mask = (0x0001 << 15) | + (0x0001 << 14) | + (0x03ff << 4) | + (0x0003 << 0); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_8, + wr_data, + wr_mask); + + // TX PLL_CAL_COM_CTL_7 + wr_data = ((params->tx_pll_mode << 0) & (0x000f << 0)); + wr_mask = (0x000f << 0); + serdes_misc_write_reg(port, params->tx_pll_id, + PLL_CAL_COM_CTL_7, + wr_data, + wr_mask); + + if (params->rx_pll_id != params->tx_pll_id) { + // RX AMS_COM_PLL_CONTROL_1 + wr_data = (((params->rx_pll_vco_div4 << 7) & (0x0001 << 7)) | + ((params->rx_pll_vco_div2 << 6) & (0x0001 << 6))); + wr_mask = (0x0001 << 7) | + (0x0001 << 6); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_1, + wr_data, + wr_mask); + + // RX AMS_COM_PLL_CONTROL_4 + wr_data = (((params->rx_pll_force_kvh_bw << 14) & (0x0001 << 14)) | + ((params->rx_pll_kvh_force << 12) & (0x0003 << 12)) | + ((params->rx_pll_2rx_bw << 8) & (0x0003 << 8))); + wr_mask = (0x0001 << 14) | + (0x0003 << 12) | + (0x0003 << 8); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_4, + wr_data, + wr_mask); + + // RX AMS_COM_PLL_CONTROL_7 + wr_data = (((params->rx_pll_fracn_div & 0xffff) << 0) & (0xffff << 0)); + wr_mask = (0xffff << 0); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_7, + wr_data, + wr_mask); + + // RX AMS_COM_PLL_CONTROL_8 + wr_data = (((params->rx_pll_fracn_sel << 15) & (0x0001 << 15)) | + ((params->rx_pll_ditheren << 14) & (0x0001 << 14)) | + ((params->rx_pll_fracn_ndiv << 4) & (0x03ff << 4)) | + ((((params->rx_pll_fracn_div & 0x30000) >> 16) << 0) & (0x0003 << 0))); + wr_mask = (0x0001 << 15) | + (0x0001 << 14) | + (0x03ff << 4) | + (0x0003 << 0); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_8, + wr_data, + wr_mask); + + // RX PLL_CAL_COM_CTL_7 + wr_data = ((params->rx_pll_mode << 0) & (0x000f << 0)); + wr_mask = (0x000f << 0); + serdes_misc_write_reg(port, params->rx_pll_id, + PLL_CAL_COM_CTL_7, + wr_data, + wr_mask); + } + + if (params->do_pll_charge_pump) { + /* from PON driver only */ + // pll_iqp [04:01] = 0x5 = default + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x000a, 0x001e); + } + + if (params->do_pll_charge_pump_10g) { + /* from PON driver only */ + // 0xD0B2[bit0]=en_HRz<1> =1, 0xD0B0[bit11]=en_HRz<0>=1 -->>> en_HRz = 6[kOhm] + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0001, + 0x0001); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_0, + 0x0800, + 0x0800); + + if (params->rx_pll_id != params->tx_pll_id) { + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0001, + 0x0001); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_0, + 0x0800, + 0x0800); + } + + // set PLL-Current-ChargePump=ipq[bit4:1]= 0x0 -->>> 50[uA] + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0000, + 0x001e); + + if (params->rx_pll_id != params->tx_pll_id) { + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0000, + 0x001e); + } + } + + /* from PON driver only */ + //* #Looptiming Control + //#(*) DSC_F_ONU10G_looptiming_ctrl_0. + // RX line rate to TX line rate ratio + // 000: 1 to 1 001: 1.25 to 1 010: 2 to 1 + // 011: 4 to 1 100: 5 to 1 101: 8.25 to 1 + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_F_ONU10G_looptiming_ctrl_0, + params->rx_tx_rate_ratio, + 0x0007); + + /* from PON driver only */ + //#(5.a) RX=OS4 and TX=OS8 // address 0xD080 = 16'hc074 + // # OSR Mode Value: 0= OSx1, 1=OSx2, 4=OSX4, 7=OSX8, A =OSx16 (revB0) + // # rx_osr_mode_frc = 1 + // # rx_osr_mode_frc_val = mode dependent + // # tx_osr_mode_frc = 1 + // # tx_osr_mode_frc_val = mode dependent + wr_data = (((params->tx_osr_mode << 4) | (0x0001 << 15)) | + (params->rx_osr_mode | (0x0001 << 14))); + serdes_misc_write_reg(port, serdes_PLL_0, + CKRST_CTRL_OSR_MODE_CONTROL, + wr_data, + 0xffff); + + /* from PON driver, value different in xgae and init is done + * later */ + /* #(*) TX Phase Interpolator Control 0 (0xD070) */ + serdes_misc_write_reg(port, LANE_BRDCST, + TX_PI_LBE_tx_pi_control_0, + 0x2003, /* 0x2000 in xgae driver */ + 0xffff); + + /* + * CDR programming + */ + // cdr_freq_en=1, cdr_integ_sat_sel=0, cdr_freq_override_en=0, cdr_phase_sat_ctrl=1 + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_A_cdr_control_0, + 0x0005, + 0x7ff7); + + /* Configure DSC_A_cdr_control_2 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_A_cdr_control_2, + params->dsc_a_cdr_control_2, + 0x1ff3); + + /* Configure DSC_B_dsc_sm_ctrl_7 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_B_dsc_sm_ctrl_7, + 0x0000, + 0xffff); + + /* Configure DSC_A_cdr_control_1 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_A_cdr_control_1, + 0x0690, + 0xffff); + + /*Configure DSC_B_dsc_sm_ctrl_8 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_B_dsc_sm_ctrl_8, + 0x0010, + 0xcfff); + + /* from PON driver only */ + if (params->do_vga_rf) { + // (*) Analog = VGA, and PF programming + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_E_dsc_e_pf_ctrl, + 0x0007, + 0x000F); // _set_rx_pf_main(7); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_E_dsc_e_pf2_lowp_ctrl, + 0x0003, + 0x0007); // _set_rx_pf2(3); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_C_dfe_vga_override, + 0x0000, + 0x3E00); // _set_rx_vga(32); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_C_dfe_vga_override, + 0x0100, + 0x01FF); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_C_dfe_vga_override, + 0x8000, + 0x8000); + } + + /* + * (#11) RX-&-TX PON_MAC_CLK Division Control and SYNC_E_CLK + */ + // TX AMS_TX_TX_CONTROL_1 [ 0xD0A1 ] + wr_data = (((params->tx_pon_mac_ctrl << 4) & (0x0007 << 4)) | + ((params->tx_sync_e_ctrl << 1) & (0x0007 << 1))); + wr_mask = (0x0007 << 4) | + (0x0007 << 1); + serdes_misc_write_reg(port, LANE_BRDCST, + AMS_TX_TX_CONTROL_1, + wr_data, + wr_mask); + + // TX AMS_RX_RX_CONTROL_2 [ 0xD092 ] + wr_data = (((params->rx_pon_mac_ctrl << 0) & (0x0007 << 0))); + wr_mask = (0x0007 << 0); + serdes_misc_write_reg(port, LANE_BRDCST, + AMS_RX_RX_CONTROL_2, + wr_data, + wr_mask); + + /* + * Enable PLL's. De-assert core_dp_s_rstb --> will start the + * PLL calibration. + * + */ + + /* afe_s_pll_pwrdn=1, core_dp_s_rs=0 */ + serdes_misc_write_reg(port, params->tx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x4000, + 0x6000); + if (params->tx_pll_id != params->rx_pll_id) + serdes_misc_write_reg(port, params->rx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x4000, + 0x6000); + udelay(1); + + /* afe_s_pll_pwrdn=0, core_dp_s_rs=1 */ + serdes_misc_write_reg(port, params->tx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x2000, + 0x6000); + if (params->tx_pll_id != params->rx_pll_id) + serdes_misc_write_reg(port, params->rx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x2000, + 0x6000); + + /* poll for PLL lock */ + if (serdes_poll_pll_lock(port, params->tx_pll_id)) + return 1; + + if (params->tx_pll_id != params->rx_pll_id) { + if (serdes_poll_pll_lock(port, params->rx_pll_id)) + return 1; + } + + /* also poll for PLL lock in wan top block */ + if (wan_top_poll_pll_lock(port, params->tx_pll_id)) + return 1; + + if (params->tx_pll_id != params->rx_pll_id) { + if (wan_top_poll_pll_lock(port, params->rx_pll_id)) + return 1; + } + + /* + * #(11) De-assert ln_dp_s_rstb + */ + + /* note: LANE_BRDCST in xgae driver only */ + // ln_dp_s_rstb = 1 = serdes data-path out of reset (0xd081) + serdes_misc_write_reg(port, LANE_BRDCST, + CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL, + 0x0002, + 0x0002); + + /* note: LANE_BRDCST in xgae driver only */ + serdes_misc_write_reg(port, LANE_BRDCST, + AMS_TX_TX_CONTROL_0, + 0x0000, + 0x00c0); + + /* + * xgae driver configures sigdetect, pon driver disable it + */ + if (params->do_sigdetect) { + serdes_misc_write_reg(port, LANE_0, + DSC_B_dsc_sm_ctrl_0, + 0x0008, + 0xffff); + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_3, + 0x0023, + 0xffff); + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_1, + 0xa00a, + 0); + } else { + /* Ignore SigDetect: 0xd010[09] = ignore_sigdet =1 */ + serdes_misc_write_reg(port, LANE_0, + DSC_B_dsc_sm_ctrl_0, + 0x0200, + 0x0200); + + // 0xD0C1 bits 6, 5 and 0 + // energy_detect_frc_val -> 1 + // energy_detect_frc -> 1 + // afe_signal_detect_dis -> 1 + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_1, + 0x0061, + 0x0061); + + + // 0xD0C2 bits 0-2 and 4-6: + // los_thresh -> 0 + // signal_detect_thresh -> 0 + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_2, + 0x0000, + 0x0077); + + // 0xD0C3 bits 6-7: + // analog_sd_override -> 1 + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_3, + 0x0040, + 0x00C0); + } + + /* check DSC lock */ + if (serdes_poll_dsc_lock(port)) + return 1; + + /* check PMD rx lock */ + if (serdes_poll_pmd_rx_lock(port)) + return 1; + + // (*) PLL PPM Adjustment for RX=10G modes + /* FIXME, only done in PON driver and 10G_10G mode, which is + * not yet implemented here */ + + /* Adjust RX PI intial location */ + if (params->do_rx_pi_spacing) + rx_pi_spacing(port, params->clk90_offset, params->p1_offset); + + /* set AE 10G gearbox */ + val = 0; + if (params->serdes_ae_full_rate) + val |= WAN_TOP_AE_GEARBOX_CONTROL_0_CR_FULL_RATE_MODE_MASK; + if (params->serdes_ae_20b_width) + val |= WAN_TOP_AE_GEARBOX_CONTROL_0_CR_WIDTH_MODE_MASK; + wan_top_writel(port, WAN_TOP_AE_GEARBOX_CONTROL_0_REG, val); + + /* reset WAN AE */ + if (params->do_ae) + reset_control_reset(port->wan_ae_rst); + + /* reset WAN TOP pcs */ + wan_top_clear(port, WAN_TOP_RESET_REG, WAN_TOP_RESET_CFG_PCS_RESET_N_MASK); + msleep(10); + wan_top_set(port, WAN_TOP_RESET_REG, WAN_TOP_RESET_CFG_PCS_RESET_N_MASK); + msleep(1); + + if (!params->do_ae) { + /* FIXME: bcm pon driver has early TX config for pon + * 1G and optics BCM_I2C_PON_OPTICS_TYPE_PMD, which + * does not seem to apply to us */ + } + + /* enable laser now that config is done */ + wan_top_set(port, WAN_TOP_MISC_3_REG, WAN_TOP_MISC_3_LASER_OE_MASK); + + return 0; +} + +void xport_serdes_update_m3_params(struct xport_priv *port, + const struct serdes_misc3_params *m3params) +{ + u32 val; + + val = wan_top_readl(port, WAN_TOP_MISC_3_REG); + val &= ~WAN_TOP_MISC_3_WAN_IFSELECT_MASK; + val |= m3params->misc3_if_select << WAN_TOP_MISC_3_WAN_IFSELECT_SHIFT; + wan_top_writel(port, WAN_TOP_MISC_3_REG, val); + +} + +void xport_serdes_shutdown(struct xport_priv *port) +{ + xport_serdes_reset_ctl(port, true); +} + diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.c 2023-06-27 11:46:28.030561125 +0200 @@ -0,0 +1,1234 @@ +#include "port_xport_xlmac.h" +#include "regs/serdes_regs.h" + +#define GEN_MIB_STAT(m) \ + sizeof(((struct xlmac_mib *)0)->m), \ + offsetof(struct xlmac_mib, m) + +const struct bcm_runner_ethtool_stat xlmac_mib_estat[] = { + { "rx_64", GEN_MIB_STAT(rx_64), XPORT_MIB_CORE_GRX64_REG, }, + { "rx_127", GEN_MIB_STAT(rx_127), XPORT_MIB_CORE_GRX127_REG, }, + { "rx_255", GEN_MIB_STAT(rx_255), XPORT_MIB_CORE_GRX255_REG, }, + { "rx_511", GEN_MIB_STAT(rx_511), XPORT_MIB_CORE_GRX511_REG, }, + { "rx_1023", GEN_MIB_STAT(rx_1023), XPORT_MIB_CORE_GRX1023_REG, }, + { "rx_1518", GEN_MIB_STAT(rx_1518), XPORT_MIB_CORE_GRX1518_REG, }, + { "rx_1522", GEN_MIB_STAT(rx_1522), XPORT_MIB_CORE_GRX1522_REG, }, + { "rx_2047", GEN_MIB_STAT(rx_2047), XPORT_MIB_CORE_GRX2047_REG, }, + { "rx_4095", GEN_MIB_STAT(rx_4095), XPORT_MIB_CORE_GRX4095_REG, }, + { "rx_9216", GEN_MIB_STAT(rx_9216), XPORT_MIB_CORE_GRX9216_REG, }, + { "rx_16383", GEN_MIB_STAT(rx_16383), XPORT_MIB_CORE_GRX16383_REG, }, + { "rx_all_pkt", GEN_MIB_STAT(rx_pkt), XPORT_MIB_CORE_GRXPKT_REG, }, + { "rx_unicast", GEN_MIB_STAT(rx_uca), XPORT_MIB_CORE_GRXUCA_REG, }, + { "rx_multicast", GEN_MIB_STAT(rx_mca), XPORT_MIB_CORE_GRXMCA_REG, }, + { "rx_bcast", GEN_MIB_STAT(rx_bca), XPORT_MIB_CORE_GRXBCA_REG, }, + { "rx_fcs", GEN_MIB_STAT(rx_fcs), XPORT_MIB_CORE_GRXFCS_REG, }, + { "rx_control", GEN_MIB_STAT(rx_cf), XPORT_MIB_CORE_GRXCF_REG, }, + { "rx_pause", GEN_MIB_STAT(rx_pf), XPORT_MIB_CORE_GRXPF_REG, }, + { "rx_pfc", GEN_MIB_STAT(rx_pp), XPORT_MIB_CORE_GRXPP_REG, }, + { "rx_unsupp_opcode", GEN_MIB_STAT(rx_uo), XPORT_MIB_CORE_GRXUO_REG, }, + { "rx_unsupp_da", GEN_MIB_STAT(rx_uda), XPORT_MIB_CORE_GRXUDA_REG, }, + { "rx_wrong_sa", GEN_MIB_STAT(rx_wsa), XPORT_MIB_CORE_GRXWSA_REG, }, + { "rx_align", GEN_MIB_STAT(rx_aln), XPORT_MIB_CORE_GRXALN_REG, }, + { "rx_length", GEN_MIB_STAT(rx_flr), XPORT_MIB_CORE_GRXFLR_REG, }, + { "rx_code_err", GEN_MIB_STAT(rx_frerr), XPORT_MIB_CORE_GRXFRERR_REG, }, + { "rx_false_carrier", GEN_MIB_STAT(rx_fcr), XPORT_MIB_CORE_GRXFCR_REG, }, + { "rx_oversize", GEN_MIB_STAT(rx_ovr), XPORT_MIB_CORE_GRXOVR_REG, }, + { "rx_jabber", GEN_MIB_STAT(rx_jbr), XPORT_MIB_CORE_GRXJBR_REG, }, + { "rx_bad_mtu", GEN_MIB_STAT(rx_mtue), XPORT_MIB_CORE_GRXMTUE_REG, }, + { "rx_matched_crc", GEN_MIB_STAT(rx_mcrc), XPORT_MIB_CORE_GRXMCRC_REG, }, + { "rx_promisc", GEN_MIB_STAT(rx_prm), XPORT_MIB_CORE_GRXPRM_REG, }, + { "rx_vlan", GEN_MIB_STAT(rx_vln), XPORT_MIB_CORE_GRXVLN_REG, }, + { "rx_dvlan", GEN_MIB_STAT(rx_dvln), XPORT_MIB_CORE_GRXDVLN_REG, }, + { "rx_trunc", GEN_MIB_STAT(rx_trfu), XPORT_MIB_CORE_GRXTRFU_REG, }, + { "rx_good", GEN_MIB_STAT(rx_pok), XPORT_MIB_CORE_GRXPOK_REG, }, + { "rx_pfcoff0", GEN_MIB_STAT(rx_pfcoff0), XPORT_MIB_CORE_GRXPFCOFF0_REG, }, + { "rx_pfcoff1", GEN_MIB_STAT(rx_pfcoff1), XPORT_MIB_CORE_GRXPFCOFF1_REG, }, + { "rx_pfcoff2", GEN_MIB_STAT(rx_pfcoff2), XPORT_MIB_CORE_GRXPFCOFF2_REG, }, + { "rx_pfcoff3", GEN_MIB_STAT(rx_pfcoff3), XPORT_MIB_CORE_GRXPFCOFF3_REG, }, + { "rx_pfcoff4", GEN_MIB_STAT(rx_pfcoff4), XPORT_MIB_CORE_GRXPFCOFF4_REG, }, + { "rx_pfcoff5", GEN_MIB_STAT(rx_pfcoff5), XPORT_MIB_CORE_GRXPFCOFF5_REG, }, + { "rx_pfcoff6", GEN_MIB_STAT(rx_pfcoff6), XPORT_MIB_CORE_GRXPFCOFF6_REG, }, + { "rx_pfcoff7", GEN_MIB_STAT(rx_pfcoff7), XPORT_MIB_CORE_GRXPFCOFF7_REG, }, + { "rx_pfcp0", GEN_MIB_STAT(rx_pfcp0), XPORT_MIB_CORE_GRXPFCP0_REG, }, + { "rx_pfcp1", GEN_MIB_STAT(rx_pfcp1), XPORT_MIB_CORE_GRXPFCP1_REG, }, + { "rx_pfcp2", GEN_MIB_STAT(rx_pfcp2), XPORT_MIB_CORE_GRXPFCP2_REG, }, + { "rx_pfcp3", GEN_MIB_STAT(rx_pfcp3), XPORT_MIB_CORE_GRXPFCP3_REG, }, + { "rx_pfcp4", GEN_MIB_STAT(rx_pfcp4), XPORT_MIB_CORE_GRXPFCP4_REG, }, + { "rx_pfcp5", GEN_MIB_STAT(rx_pfcp5), XPORT_MIB_CORE_GRXPFCP5_REG, }, + { "rx_pfcp6", GEN_MIB_STAT(rx_pfcp6), XPORT_MIB_CORE_GRXPFCP6_REG, }, + { "rx_pfcp7", GEN_MIB_STAT(rx_pfcp7), XPORT_MIB_CORE_GRXPFCP7_REG, }, + { "rx_schcrc", GEN_MIB_STAT(rx_schcrc), XPORT_MIB_CORE_GRXSCHCRC_REG, }, + { "rx_bytes", GEN_MIB_STAT(rx_byt), XPORT_MIB_CORE_GRXBYT_REG, }, + { "rx_runt", GEN_MIB_STAT(rx_rpkt), XPORT_MIB_CORE_GRXRPKT_REG, }, + { "rx_undersize", GEN_MIB_STAT(rx_und), XPORT_MIB_CORE_GRXUND_REG, }, + { "rx_frag", GEN_MIB_STAT(rx_frg), XPORT_MIB_CORE_GRXFRG_REG, }, + { "rx_runt_bytes", GEN_MIB_STAT(rx_rbyt), XPORT_MIB_CORE_GRXRBYT_REG, }, + { "tx_64", GEN_MIB_STAT(tx_64), XPORT_MIB_CORE_GTX64_REG, }, + { "tx_127", GEN_MIB_STAT(tx_127), XPORT_MIB_CORE_GTX127_REG, }, + { "tx_255", GEN_MIB_STAT(tx_255), XPORT_MIB_CORE_GTX255_REG, }, + { "tx_511", GEN_MIB_STAT(tx_511), XPORT_MIB_CORE_GTX511_REG, }, + { "tx_1023", GEN_MIB_STAT(tx_1023), XPORT_MIB_CORE_GTX1023_REG, }, + { "tx_1518", GEN_MIB_STAT(tx_1518), XPORT_MIB_CORE_GTX1518_REG, }, + { "tx_1522", GEN_MIB_STAT(tx_1522), XPORT_MIB_CORE_GTX1522_REG, }, + { "tx_2047", GEN_MIB_STAT(tx_2047), XPORT_MIB_CORE_GTX2047_REG, }, + { "tx_4095", GEN_MIB_STAT(tx_4095), XPORT_MIB_CORE_GTX4095_REG, }, + { "tx_9216", GEN_MIB_STAT(tx_9216), XPORT_MIB_CORE_GTX9216_REG, }, + { "tx_16383", GEN_MIB_STAT(tx_16383), XPORT_MIB_CORE_GTX16383_REG, }, + { "tx_good", GEN_MIB_STAT(tx_pok), XPORT_MIB_CORE_GTXPOK_REG, }, + { "tx_all_pkt", GEN_MIB_STAT(tx_pkt), XPORT_MIB_CORE_GTXPKT_REG, }, + { "tx_unicast", GEN_MIB_STAT(tx_uca), XPORT_MIB_CORE_GTXUCA_REG, }, + { "tx_multicast", GEN_MIB_STAT(tx_mca), XPORT_MIB_CORE_GTXMCA_REG, }, + { "tx_bcast", GEN_MIB_STAT(tx_bca), XPORT_MIB_CORE_GTXBCA_REG, }, + { "tx_pause", GEN_MIB_STAT(tx_pf), XPORT_MIB_CORE_GTXPF_REG, }, + { "tx_pfc", GEN_MIB_STAT(tx_pfc), XPORT_MIB_CORE_GTXPFC_REG, }, + { "tx_jabber", GEN_MIB_STAT(tx_jbr), XPORT_MIB_CORE_GTXJBR_REG, }, + { "tx_fcs", GEN_MIB_STAT(tx_fcs), XPORT_MIB_CORE_GTXFCS_REG, }, + { "tx_control", GEN_MIB_STAT(tx_cf), XPORT_MIB_CORE_GTXCF_REG, }, + { "tx_oversize", GEN_MIB_STAT(tx_ovr), XPORT_MIB_CORE_GTXOVR_REG, }, + { "tx_defer", GEN_MIB_STAT(tx_dfr), XPORT_MIB_CORE_GTXDFR_REG, }, + { "tx_multi_defer", GEN_MIB_STAT(tx_edf), XPORT_MIB_CORE_GTXEDF_REG, }, + { "tx_col", GEN_MIB_STAT(tx_scl), XPORT_MIB_CORE_GTXSCL_REG, }, + { "tx_multi_col", GEN_MIB_STAT(tx_mcl), XPORT_MIB_CORE_GTXMCL_REG, }, + { "tx_late_col", GEN_MIB_STAT(tx_lcl), XPORT_MIB_CORE_GTXLCL_REG, }, + { "tx_excess_col", GEN_MIB_STAT(tx_xcl), XPORT_MIB_CORE_GTXXCL_REG, }, + { "tx_fragment", GEN_MIB_STAT(tx_frg), XPORT_MIB_CORE_GTXFRG_REG, }, + { "tx_err", GEN_MIB_STAT(tx_err), XPORT_MIB_CORE_GTXERR_REG, }, + { "tx_vlan", GEN_MIB_STAT(tx_vln), XPORT_MIB_CORE_GTXVLN_REG, }, + { "tx_dvlan", GEN_MIB_STAT(tx_dvln), XPORT_MIB_CORE_GTXDVLN_REG, }, + { "tx_runt", GEN_MIB_STAT(tx_rpkt), XPORT_MIB_CORE_GTXRPKT_REG, }, + { "tx_underrun", GEN_MIB_STAT(tx_ufl), XPORT_MIB_CORE_GTXUFL_REG, }, + { "tx_pfcp0", GEN_MIB_STAT(tx_pfcp0), XPORT_MIB_CORE_GTXPFCP0_REG, }, + { "tx_pfcp1", GEN_MIB_STAT(tx_pfcp1), XPORT_MIB_CORE_GTXPFCP1_REG, }, + { "tx_pfcp2", GEN_MIB_STAT(tx_pfcp2), XPORT_MIB_CORE_GTXPFCP2_REG, }, + { "tx_pfcp3", GEN_MIB_STAT(tx_pfcp3), XPORT_MIB_CORE_GTXPFCP3_REG, }, + { "tx_pfcp4", GEN_MIB_STAT(tx_pfcp4), XPORT_MIB_CORE_GTXPFCP4_REG, }, + { "tx_pfcp5", GEN_MIB_STAT(tx_pfcp5), XPORT_MIB_CORE_GTXPFCP5_REG, }, + { "tx_pfcp6", GEN_MIB_STAT(tx_pfcp6), XPORT_MIB_CORE_GTXPFCP6_REG, }, + { "tx_pfcp7", GEN_MIB_STAT(tx_pfcp7), XPORT_MIB_CORE_GTXPFCP7_REG, }, + { "tx_tot_col", GEN_MIB_STAT(tx_ncl), XPORT_MIB_CORE_GTXNCL_REG, }, + { "tx_bytes", GEN_MIB_STAT(tx_byt), XPORT_MIB_CORE_GTXBYT_REG, }, + { "rx_lpi", GEN_MIB_STAT(rx_lpi), XPORT_MIB_CORE_GRXLPI_REG, }, + { "rx_dlpi", GEN_MIB_STAT(rx_dlpi), XPORT_MIB_CORE_GRXDLPI_REG, }, + { "tx_lpi", GEN_MIB_STAT(tx_lpi), XPORT_MIB_CORE_GTXLPI_REG, }, + { "tx_dlpi", GEN_MIB_STAT(tx_dlpi), XPORT_MIB_CORE_GTXDLPI_REG, }, + { "rx_ptllfc", GEN_MIB_STAT(rx_ptllfc), XPORT_MIB_CORE_GRXPTLLFC_REG, }, + { "rx_ltllfc", GEN_MIB_STAT(rx_ltllfc), XPORT_MIB_CORE_GRXLTLLFC_REG, }, + { "rx_llfcfcs", GEN_MIB_STAT(rx_llfcfcs), XPORT_MIB_CORE_GRXLLFCFCS_REG, }, + { "tx_ltllfc", GEN_MIB_STAT(tx_ltllfc), XPORT_MIB_CORE_GTXLTLLFC_REG, }, +}; + +/* + * + */ +static void mode_xlmac_stats_update(void *mode_priv, + struct net_device_stats *s) +{ + struct xport_xlmac_priv *mode = mode_priv; + u64 val; + + val = xport_mib_core_readl(mode, XPORT_MIB_CORE_GRXFCS_REG); + s->rx_crc_errors = val; + + val = xport_mib_core_readl(mode, XPORT_MIB_CORE_GRXFLR_REG); + s->rx_length_errors = val; + + val = xport_mib_core_readl(mode, XPORT_MIB_CORE_GRXFRERR_REG); + val += xport_mib_core_readl(mode, XPORT_MIB_CORE_GRXJBR_REG); + val += xport_mib_core_readl(mode, XPORT_MIB_CORE_GRXALN_REG); + s->rx_errors = val; +} + +/* + * + */ +static void mode_xlmac_mib_update(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + size_t i; + + for (i = 0; i < ARRAY_SIZE(xlmac_mib_estat); i++) { + const struct bcm_runner_ethtool_stat *s; + u64 val; + char *p; + + s = &xlmac_mib_estat[i]; + val = xport_mib_core_readl(mode, s->reg); + p = (char *)&mode->mib + s->offset; + *(u64 *)p = val; + } +} + +/* + * + */ +static void *mode_xlmac_mib_get_data(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + return &mode->mib; +} + +/* + * + */ +static void mode_xlmac_mtu_set(void *mode_priv, unsigned int size) +{ + struct xport_xlmac_priv *mode = mode_priv; + + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_RX_MAX_SIZE_REG, + size); +} + +/* + * + */ +static void xlmac_setup(struct xport_xlmac_priv *mode, unsigned int speed) +{ + u64 val64; + u32 val; + + /* release XLIF credits */ + val = xlif_reg_readl(mode, XLIF_TX_IF_SET_CREDITS_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_SET_CREDITS_EN_MASK; + xlif_reg_writel(mode, XLIF_TX_IF_SET_CREDITS_REG(mode->xlmac_id), val); + + /* Enable 2.5G/10G AE PFC_STATS_EN for Hardware work around */ + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_PFC_CTRL_REG); + val64 |= PFC_CTRL_PFC_STATS_EN_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_PFC_CTRL_REG, val64); + + val = xport_reg_readl(mode, XPORT_REG_XPORT_CNTRL_1_REG); + /* FIXME: should be set if we ever use more than 1 port */ + val &= ~XPORT_CNTRL_1_REG_MSBUS_CLK_SEL_MASK; + val &= ~XPORT_CNTRL_1_REG_TIMEOUT_RST_DISABLE_MASK; + if (speed == 10000) + val |= XPORT_CNTRL_1_REG_P0_MODE_MASK; + else + val &= ~XPORT_CNTRL_1_REG_P0_MODE_MASK; + xport_reg_writel(mode, XPORT_REG_XPORT_CNTRL_1_REG, val); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_TX_CTRL_REG); + val64 |= TX_CTRL_PAD_EN_MASK; + val64 &= ~TX_CTRL_CRC_MODE_MASK; + /* XLMAC_TX_CTRL_CRC_MODE_PER_PKT == 3 */ + val64 |= (3 << TX_CTRL_CRC_MODE_SHIFT); /* FIXME: set it back to 2 */ + val64 &= ~TX_CTRL_TX_THRESHOLD_MASK; + val64 |= (2ULL << TX_CTRL_TX_THRESHOLD_SHIFT); + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_TX_CTRL_REG, val64); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_RX_CTRL_REG); + /* CRC validated by BBH, so keep it */ + val64 &= ~RX_CTRL_STRIP_CRC_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_RX_CTRL_REG, val64); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 &= ~CTRL_EXTENDED_HIG2_EN_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_MODE_REG); + val64 &= ~MODE_SPEED_MODE_MASK; + switch (speed) { + case 10: + val64 |= 0 << MODE_SPEED_MODE_SHIFT; + break; + case 100: + val64 |= 1 << MODE_SPEED_MODE_SHIFT; + break; + case 1000: + val64 |= 2 << MODE_SPEED_MODE_SHIFT; + break; + case 2500: + val64 |= 3 << MODE_SPEED_MODE_SHIFT; + break; + case 10000: + val64 |= 4 << MODE_SPEED_MODE_SHIFT; + break; + default: + BUG(); + break; + } + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_MODE_REG, val64); + + /* release xlmac reset */ + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 &= ~CTRL_SOFT_RESET_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); + + /* setup mbus in work conserving mode, clear weight of unused + * ports */ + val = xport_mab_reg_readl(mode, XPORT_MAB_TX_WRR_CTRL_REG); + val |= TX_WRR_CTRL_ARB_MODE_MASK; + val &= ~TX_WRR_CTRL_P2_WEIGHT_MASK; + val &= ~TX_WRR_CTRL_P3_WEIGHT_MASK; + xport_mab_reg_writel(mode, XPORT_MAB_TX_WRR_CTRL_REG, val); + + /* release msbus reset */ + val = xport_mab_reg_readl(mode, XPORT_MAB_CNTRL_REG); + val &= ~(1 << (CNTRL_GMII_TX_RST_SHIFT + mode->xlmac_id)); + val &= ~(1 << (CNTRL_GMII_RX_RST_SHIFT + mode->xlmac_id)); + if (mode->xlmac_id == 0) { + val &= ~CNTRL_XGMII_TX_RST_MASK; + val &= ~CNTRL_XGMII_RX_RST_MASK; + } + xport_mab_reg_writel(mode, XPORT_MAB_CNTRL_REG, val); +} + +/* + * + */ +static void xlmac_reset(struct xport_xlmac_priv *mode) +{ + u64 val64; + u32 val; + + /* + * msbus reset + */ + val = xport_mab_reg_readl(mode, XPORT_MAB_CNTRL_REG); + val |= 1 << (CNTRL_GMII_TX_RST_SHIFT + mode->xlmac_id); + val |= 1 << (CNTRL_GMII_RX_RST_SHIFT + mode->xlmac_id); + + if (mode->xlmac_id == 0) { + val |= CNTRL_XGMII_TX_RST_MASK; + val |= CNTRL_XGMII_RX_RST_MASK; + } + xport_mab_reg_writel(mode, XPORT_MAB_CNTRL_REG, val); + + /* + * xlmac reset + */ + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 |= CTRL_SOFT_RESET_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); + + /* reset XLIF credits */ + xlif_reg_writel(mode, XLIF_TX_IF_SET_CREDITS_REG(mode->xlmac_id), + XLIF_TX_IF_SET_CREDITS_EN_MASK); +} + +/* + * + */ +static void xlmac_enable(struct xport_xlmac_priv *mode) +{ + u64 val64; + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 |= CTRL_TX_EN_MASK; + val64 |= CTRL_RX_EN_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); +} + +/* + * + */ +static void xlmac_disable(struct xport_xlmac_priv *mode) +{ + xlmac_reset(mode); + mdelay(1); +} + +/* + * + */ +static void xlif_init(struct xport_xlmac_priv *mode) +{ + u32 val; + + val = xlif_reg_readl(mode, XLIF_TX_IF_IF_ENABLE_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_IF_ENABLE_DISABLE_WITH_CREDITS_MASK; + val &= ~XLIF_TX_IF_IF_ENABLE_DISABLE_WO_CREDITS_MASK; + xlif_reg_writel(mode, XLIF_TX_IF_IF_ENABLE_REG(mode->xlmac_id), val); + + val = xlif_reg_readl(mode, + XLIF_TX_IF_URUN_PORT_ENABLE_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_URUN_PORT_ENABLE_ENABLE_MASK; + xlif_reg_writel(mode, XLIF_TX_IF_URUN_PORT_ENABLE_REG(mode->xlmac_id), + val); + + val = xlif_reg_readl(mode, XLIF_TX_IF_TX_THRESHOLD_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_TX_THRESHOLD_VALUE_MASK; + /* value from bcm code */ + val |= (0xc << XLIF_TX_IF_TX_THRESHOLD_VALUE_SHIFT); + xlif_reg_writel(mode, XLIF_TX_IF_TX_THRESHOLD_REG(mode->xlmac_id), val); + + val = xlif_reg_readl(mode, XLIF_RX_IF_IF_DIS_REG(mode->xlmac_id)); + val &= ~XLIF_RX_IF_IF_DIS_DISABLE_MASK; + xlif_reg_writel(mode, XLIF_RX_IF_IF_DIS_REG(mode->xlmac_id), val); +} + +/* + * + */ +static void serdes_setup_pcs_1000basex(struct xport_xlmac_priv *mode, + const unsigned long *advertising) +{ + int val; + + /* setup serdes in fiber mode */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1); + val |= SerdesDigital_FibreSgmiiModeFibre; + val &= ~(SerdesDigital_SigDetEn | + SerdesDigital_InvertSigDet); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1, + val, 0xffff); + + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X2); + /* disable feature that tries to detect autoneg mismatch and + * auto-disable autoneg if it sees that remote is not sending + * autoneg codewords */ + val &= ~SerdesDigital_EnableParallelDetection; + + /* enable feature that report link as down when it receives a + * valid 8b/10b signal, but only autoneg codeword */ + val |= SerdesDigital_DisableFalseLink; + + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X2, + val, 0xff); + + /* setup autoneg */ + val = 0; + if (phylink_test(advertising, Autoneg)) { + val = ADVERTISE_1000XFULL; + if (phylink_test(advertising, Pause)) + val |= ADVERTISE_1000XPAUSE; + if (phylink_test(advertising, Asym_Pause)) + val |= ADVERTISE_1000XPSE_ASYM; + } + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_ADVERTISE, + val, 0xffff); + + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + val |= BMCR_SPEED1000 | BMCR_FULLDPLX; + val &= ~BMCR_ISOLATE; + if (phylink_test(advertising, Autoneg)) + val |= BMCR_ANENABLE | BMCR_ANRESTART; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_BMCR, + val, 0xffff); +} + +/* + * + */ +static void serdes_setup_pcs_sgmii(struct xport_xlmac_priv *mode) +{ + int val; + + /* setup serdes in sgmii mode */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1); + val &= ~(SerdesDigital_FibreSgmiiModeFibre | + SerdesDigital_SigDetEn | + SerdesDigital_InvertSigDet); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1, + val, 0xffff); + + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X2); + /* disable feature that tries to detect autoneg mismatch and + * auto-disable autoneg if it sees that remote is not sending + * autoneg codewords */ + val &= ~SerdesDigital_EnableParallelDetection; + + val |= SerdesDigital_AutoNegoFastTimer; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X2, + val, 0xff); + + /* enable autoneg */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + val &= ~(BMCR_SPEED1000 | BMCR_SPEED100 | BMCR_FULLDPLX); + val |= BMCR_ANENABLE | BMCR_ANRESTART; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_BMCR, + val, 0xffff); +} + +/* + * + */ +static void serdes_setup_pcs_10g(struct xport_xlmac_priv *mode) +{ + int val; + + /* setup serdes in fiber mode */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1); + val |= SerdesDigital_FibreSgmiiModeFibre; + val &= ~(SerdesDigital_SigDetEn | + SerdesDigital_InvertSigDet); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1, + val, 0xffff); + + /* no autoneg on 10Gbase-R */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + val &= ~BMCR_ANENABLE; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_BMCR, + val, 0xffff); + + /* init from BCM */ + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, XGXSBLK0_XGXSCTRL, + 0x260f, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, XGXSBLK1_LANECTRL0, + 0x1011, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_misc1, + 0x6015, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + Digital5_parDetINDControl1, + 0x5015, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + Digital5_parDetINDControl2, + 0x0008, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital5_Misc7 , + 0x0008, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital5_Misc6, + 0x2a00, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital4_Misc3, + 0x8188, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital4_Misc4, + 0x6000, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, tx66_Control, + 0x4041, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, tx66_Control, + 0x4001, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + rx66b1_rx66b1_Control1 , + rfifo_ptr_sw_rst, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + rx66b1_rx66b1_Control1 , + 0, 0xffff); +} + +/* + * + */ +static void serdes_pcs_restart_aneg(struct xport_xlmac_priv *mode) +{ + int val; + + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + if (val < 0) + return; + val |= BMCR_ANRESTART; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + MII_BMCR, val, 0xffff); +} + +/* + * + */ +static void serdes_pcs_get_sync_ok(struct xport_xlmac_priv *mode, + bool *sync_ok_1g, + bool *sync_ok_10g) +{ + size_t i; + int ret; + + for (i = 0; sync_ok_1g && i < 3; i++) { + *sync_ok_1g = false; + + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + SerdesDigital_Status1000X2); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + if (i == 0) { + /* ignore first read */ + continue; + } + + if (!(ret & Status1000X2_sync_ok)) + break; + + if ((ret & Status1000X2_sync_failed)) + break; + + /* + * on 10GEPON link, sync_ok can go to 1 briefly + * + * to avoid false detection, sync failed must stay 0 + * and sync ok must stay one for two iterations + */ + if (i == 2 && sync_ok_1g) + *sync_ok_1g = true; + } + + if (sync_ok_10g) { + *sync_ok_10g = false; + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + SerdesDigital_rx66_Status); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + *sync_ok_10g = !!(ret & (1 << 3)); + } +} + +static const struct serdes_params serdes_params_1g = { + .tx_pll_vco_div2 = 0, + .tx_pll_vco_div4 = 0, + .rx_pll_id = serdes_PLL_0, + .tx_pll_id = serdes_PLL_0, + + .tx_pll_force_kvh_bw = 0x1, + .tx_pll_kvh_force = 0, + + .tx_pll_2rx_bw = 0, + + .tx_pll_fracn_sel = 0x1, + + .tx_pll_ditheren = 0x1, + + .tx_pll_fracn_div = 0x00000, + .tx_pll_fracn_ndiv = 0x0c8, + + .tx_pll_mode = 0x5, + + .rx_tx_rate_ratio = 0, + + .rx_pon_mac_ctrl = 0, + .tx_pon_mac_ctrl = 0, + .tx_sync_e_ctrl = 0, + + .rx_osr_mode = 0x7, + .tx_osr_mode = 0x7, + + .do_rx_pi_spacing = false, + .clk90_offset = 0, + .p1_offset = 0, + .dsc_a_cdr_control_2 = 0x00f0, + + .do_pll_charge_pump = false, + .do_pll_charge_pump_10g = false, + .do_vga_rf = false, + .do_sigdetect = false, + .do_ae = true, + .serdes_ae_full_rate = true, + .serdes_ae_20b_width = false, +}; + +static const struct serdes_params serdes_params_2d5g = { + .tx_pll_vco_div2 = 0, + .tx_pll_vco_div4 = 0, + .rx_pll_id = serdes_PLL_0, + .tx_pll_id = serdes_PLL_0, + + .tx_pll_force_kvh_bw = 0x1, + .tx_pll_kvh_force = 0, + + .tx_pll_2rx_bw = 0, + + .tx_pll_fracn_sel = 0x1, + + .tx_pll_ditheren = 0x1, + + .tx_pll_fracn_div = 0x00000, + .tx_pll_fracn_ndiv = 0x0fa, + + .tx_pll_mode = 0x5, + + .rx_tx_rate_ratio = 0, + + .rx_pon_mac_ctrl = 0x5, + .tx_pon_mac_ctrl = 0x5, + .tx_sync_e_ctrl = 0x1, + + .rx_osr_mode = 0x4, + .tx_osr_mode = 0x4, + + .do_rx_pi_spacing = false, + .clk90_offset = 0, + .p1_offset = 0, + .dsc_a_cdr_control_2 = 0x00f0, + + .do_pll_charge_pump = false, + .do_pll_charge_pump_10g = false, + .do_vga_rf = false, + .do_sigdetect = false, + .do_ae = true, + .serdes_ae_full_rate = true, + .serdes_ae_20b_width = false, +}; + +static const struct serdes_misc3_params serdes_m3params_1g_1000basex = { + .misc3_if_select = 1, + .misc3_laser_mode = 0, +}; + +static const struct serdes_misc3_params serdes_m3params_1g_2500basex = { + .misc3_if_select = 2, + .misc3_laser_mode = 0, +}; + +static const struct serdes_misc3_params serdes_m3params_1g_sgmii = { + .misc3_if_select = 1, + .misc3_laser_mode = 0, + .misc3_sgmii = 1, +}; + +static const struct serdes_misc3_params serdes_m3params_100m_sgmii = { + .misc3_if_select = 0, + .misc3_laser_mode = 0, + .misc3_sgmii = 1, +}; + +static const struct serdes_params serdes_params_10g = { + .tx_pll_vco_div2 = 0, + .tx_pll_vco_div4 = 0, + .rx_pll_id = serdes_PLL_0, + .tx_pll_id = serdes_PLL_0, + + .tx_pll_force_kvh_bw = 0x1, + .tx_pll_kvh_force = 0, + + .tx_pll_2rx_bw = 0, + + .tx_pll_fracn_sel = 0x1, + + .tx_pll_ditheren = 0x1, + + .tx_pll_fracn_div = 0x10000, + .tx_pll_fracn_ndiv = 0x0ce, + + .tx_pll_mode = 0x2, + + .rx_tx_rate_ratio = 0, + + .rx_pon_mac_ctrl = 0x3, + .tx_pon_mac_ctrl = 0x3, + .tx_sync_e_ctrl = 0x7, + + .rx_osr_mode = 0x0, + .tx_osr_mode = 0x0, + + .do_rx_pi_spacing = false, + .clk90_offset = 0, + .p1_offset = 0, + .dsc_a_cdr_control_2 = 0x00c0, /* 0x30 in pon driver */ + + .do_pll_charge_pump = false, + .do_pll_charge_pump_10g = false, + .do_vga_rf = false, + .do_sigdetect = false, + .do_ae = true, + .serdes_ae_full_rate = true, + .serdes_ae_20b_width = true, +}; + +static const struct serdes_misc3_params serdes_m3params_10g = { + .misc3_if_select = 3, + .misc3_laser_mode = 0, +}; + +/* + * + */ +static int mode_phylink_pcs_config(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + const unsigned long *advertising) +{ + struct xport_xlmac_priv *mode = mode_priv; + const struct serdes_params *serdes_params; + const struct serdes_misc3_params *serdes_m3params; + int val; + + xlmac_disable(mode); + xport_switch_pinctrl(mode->port, XPORT_PIN_RS0); + + mode->interface = interface; + mode->aneg_error_reported = false; + + /* + * choose correct serdes params + */ + switch (interface) { + case PHY_INTERFACE_MODE_1000BASEX: + serdes_params = &serdes_params_1g; + serdes_m3params = &serdes_m3params_1g_1000basex; + break; + case PHY_INTERFACE_MODE_SGMII: + serdes_params = &serdes_params_1g; + serdes_m3params = &serdes_m3params_1g_sgmii; + break; + case PHY_INTERFACE_MODE_2500BASEX: + serdes_params = &serdes_params_2d5g; + serdes_m3params = &serdes_m3params_1g_2500basex; + break; + case PHY_INTERFACE_MODE_10GBASER: + serdes_params = &serdes_params_10g; + serdes_m3params = &serdes_m3params_10g; + break; + default: + BUG(); + break; + } + + xport_serdes_set_params(mode->port, serdes_params, serdes_m3params); + + /* + * restore LBE forced value + */ + if (!mode->port->lbe_force) + xport_serdes_lbe_dont_force(mode->port); + else if (mode->port->lbe_force_value) + xport_serdes_lbe_force_enable(mode->port); + else + xport_serdes_lbe_force_disable(mode->port); + + /* from BCM AE code */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + CL49_UserB0_Control); + val &= ~CL49_fast_lock_cya; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + CL49_UserB0_Control, + val, 0xffff); + + /* from BCM AE code */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + XgxsBlk10_tx_pi_control4); + val |= tx_pi_sm_enable_override_value; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + XgxsBlk10_tx_pi_control4, + val, 0xffff); + + switch (interface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + serdes_setup_pcs_1000basex(mode, advertising); + break; + case PHY_INTERFACE_MODE_SGMII: + serdes_setup_pcs_sgmii(mode); + break; + case PHY_INTERFACE_MODE_10GBASER: + serdes_setup_pcs_10g(mode); + default: + break; + } + + return 0; +} + +/* + * + */ +static void mode_phylink_link_up(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + int speed, int duplex, + struct phy_device *phy) +{ + struct xport_xlmac_priv *mode = mode_priv; + + xlmac_setup(mode, speed); + xlmac_enable(mode); +} + +/* + * + */ +static void mode_phylink_link_down(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface) +{ + struct xport_xlmac_priv *mode = mode_priv; + xlmac_disable(mode); +} + +/* + * + */ +static void mode_phylink_pcs_an_restart(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + + mode->aneg_error_reported = false; + serdes_pcs_restart_aneg(mode); +} + +/* + * + */ +static void pcs_get_state_1000basex(struct xport_xlmac_priv *mode, + struct phylink_link_state *state) +{ + bool link, an_complete; + bool tx_pause, rx_pause, aneg_failed; + int fd_bit; + int lpa, ret; + + state->link = 0; + + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + SerdesDigital_Status1000X1); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + link = (ret & Status1000X1_link); + if (!phylink_test(state->advertising, Autoneg)) { + state->link = link; + if (link) { + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) + state->speed = SPEED_2500; + else + state->speed = SPEED_1000; + state->duplex = DUPLEX_FULL; + } + return; + } + + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, MII_BMSR); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + an_complete = (ret & BMSR_ANEGCOMPLETE); + + lpa = xport_serdes_pcs_read_reg(mode->port, LANE_0, MII_LPA); + if (lpa < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + state->an_complete = an_complete; + + if (!state->an_complete) { + state->link = 0; + return; + } + + /* resolve autoneg result, we only support full duplex */ + fd_bit = ETHTOOL_LINK_MODE_1000baseX_Full_BIT; + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) + fd_bit = ETHTOOL_LINK_MODE_2500baseX_Full_BIT; + else + fd_bit = ETHTOOL_LINK_MODE_1000baseX_Full_BIT; + mii_lpa_mod_linkmode_x(state->lp_advertising, lpa, fd_bit); + + /* check for autoneg failure on duplex */ + aneg_failed = false; + + if (!linkmode_test_bit(fd_bit, state->advertising) || + !linkmode_test_bit(fd_bit, state->lp_advertising)) + aneg_failed = true; + + linkmode_resolve_pause(state->advertising, + state->lp_advertising, + &tx_pause, &rx_pause); + + if (tx_pause) + state->pause |= MLO_PAUSE_TX; + if (rx_pause) + state->pause |= MLO_PAUSE_RX; + + if (aneg_failed) { + if (!mode->aneg_error_reported) { + netdev_err(mode->port->priv->netdev, + "autoneg error (lpa 0x%x)", lpa); + mode->aneg_error_reported = true; + } + return; + } + + state->link = link; + if (link) { + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) + state->speed = SPEED_2500; + else + state->speed = SPEED_1000; + state->duplex = DUPLEX_FULL; + } +} + +/* + * + */ +static void pcs_get_state_sgmii(struct xport_xlmac_priv *mode, + struct phylink_link_state *state) +{ + bool an_complete; + int lpa, ret, val; + + state->link = 0; + + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, MII_BMSR); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + an_complete = (ret & BMSR_ANEGCOMPLETE); + + lpa = xport_serdes_pcs_read_reg(mode->port, LANE_0, MII_LPA); + if (lpa < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + if (!(lpa & LPA_SGMII)) { + /* remote is not an SGMII PHY */ + return; + } + + state->link = !!(lpa & LPA_SGMII_LINK); + if (!state->link) { + mode->sgmii_config_set = false; + return; + } + + state->duplex = (lpa & LPA_SGMII_FULL_DUPLEX) ? + DUPLEX_FULL : DUPLEX_HALF; + + switch (lpa & LPA_SGMII_SPD_MASK) { + case LPA_SGMII_1000: + state->speed = SPEED_1000; + break; + case LPA_SGMII_100: + //state->speed = SPEED_100; + + /* for unknown reason, only 1Gbit/s is working, + * revisit later */ + state->link = 0; + break; + default: + /* other speed not supported */ + state->link = 0; + return; + } + + if (mode->sgmii_config_set) + return; + + switch (state->speed) { + case SPEED_100: + xport_serdes_update_m3_params(mode->port, + &serdes_m3params_100m_sgmii); + break; + case SPEED_1000: + xport_serdes_update_m3_params(mode->port, + &serdes_m3params_1g_sgmii); + break; + } + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + val &= ~(BMCR_SPEED1000 | BMCR_SPEED10); + val |= BMCR_FULLDPLX; + + switch (state->speed) { + case SPEED_100: + val |= BMCR_SPEED100; + break; + case SPEED_1000: + val |= BMCR_SPEED1000; + break; + } + + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_BMCR, + val, 0xffff); + mode->sgmii_config_set = true; +} + +/* + * + */ +static void pcs_get_state_10gbaser(struct xport_xlmac_priv *mode, + struct phylink_link_state *state) +{ + int ret; + + state->link = 0; + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + XGXSBLK4_xgxsStatus1); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + state->link = !!(ret & XgxsStatus1_LinkStat); + if (state->link) { + state->speed = SPEED_10000; + state->duplex = DUPLEX_FULL; + } +} + +/* + * + */ +static int mode_phylink_pcs_get_state(void *mode_priv, + struct phylink_link_state *state) +{ + struct xport_xlmac_priv *mode = mode_priv; + + switch (state->interface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + pcs_get_state_1000basex(mode, state); + break; + case PHY_INTERFACE_MODE_SGMII: + pcs_get_state_sgmii(mode, state); + break; + case PHY_INTERFACE_MODE_10GBASER: + pcs_get_state_10gbaser(mode, state); + break; + default: + WARN(1, "invalid interface"); + break; + } + + return 0; +} + +/* + * + */ +static u32 mode_get_priv_flags(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + bool sync_ok_1g, sync_ok_10g; + u32 val; + + val = (mode->port->lbe_force ? 1 : 0) << + PRIV_FLAGS_FORCE_LBE_OE_BIT; + val |= (mode->port->lbe_force_value ? 1 : 0) << + PRIV_FLAGS_FORCE_LBE_OE_VAL_BIT; + + serdes_pcs_get_sync_ok(mode, &sync_ok_1g, &sync_ok_10g); + + switch (mode->interface) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + if (sync_ok_1g) + val |= 1 << PRIV_FLAGS_ST_SYNC_OK_BIT; + break; + case PHY_INTERFACE_MODE_10GBASER: + if (sync_ok_10g) + val |= 1 << PRIV_FLAGS_ST_SYNC_OK_BIT; + break; + default: + break; + } + + return val; +} + +/* + * + */ +static int mode_set_priv_flags(void *mode_priv, u32 flags) +{ + struct xport_xlmac_priv *mode = mode_priv; + + if (!(flags & (1 << PRIV_FLAGS_FORCE_LBE_OE_BIT))) { + mode->port->lbe_force = false; + xport_serdes_lbe_dont_force(mode->port); + } else { + mode->port->lbe_force = true; + if (flags & (1 << PRIV_FLAGS_FORCE_LBE_OE_VAL_BIT)) { + mode->port->lbe_force_value = true; + xport_serdes_lbe_force_enable(mode->port); + } else { + mode->port->lbe_force_value = false; + xport_serdes_lbe_force_disable(mode->port); + } + } + + return 0; +} + +/* + * called when netdevice is stopped or after phylink interface change + */ +static void mode_xlmac_stop(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + + bcm_runner_fw_tx_stop_wait(mode->port->priv); +} + +/* + * called when netdevice is started or after phylink interface change + */ +static void *mode_xlmac_init(void *port_priv, + const struct bcm_xrdp_enet_params *params) +{ + struct xport_priv *port = port_priv; + struct xport_xlmac_priv *mode; + + mode = kzalloc(sizeof (*mode), GFP_KERNEL); + if (!mode) + return ERR_PTR(-ENOMEM); + + mode->port = port; + + xlif_init(mode); + xlmac_reset(mode); + + return mode; +} + +/* + * called when netdevice is stopped or after phylink interface change + */ +static void mode_xlmac_release(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + kfree(mode); +} + +/* + * + */ +static u32 mode_get_bbh_id(void *port_priv) +{ + struct xport_priv *port = port_priv; + return port->ae_bbh_id; +} + +const struct bcm_enet_mode_ops xport_xlmac_mode_ops = { + .name = "AE", + + .init = mode_xlmac_init, + .release = mode_xlmac_release, + + .stop = mode_xlmac_stop, + .get_bbh_id = mode_get_bbh_id, + .mtu_set = mode_xlmac_mtu_set, + .stats_update = mode_xlmac_stats_update, + + /* mib operation */ + .mib_estat = xlmac_mib_estat, + .mib_estat_count = ARRAY_SIZE(xlmac_mib_estat), + .mib_update = mode_xlmac_mib_update, + .mib_get_data = mode_xlmac_mib_get_data, + + /* get/set private on netdevice */ + .get_priv_flags = mode_get_priv_flags, + .set_priv_flags = mode_set_priv_flags, + + /* + * phylink callback + */ + .phylink_link_down = mode_phylink_link_down, + .phylink_link_up = mode_phylink_link_up, + .phylink_pcs_config = mode_phylink_pcs_config, + .phylink_pcs_get_state = mode_phylink_pcs_get_state, + .phylink_pcs_an_restart = mode_phylink_pcs_an_restart, +}; diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.h 2023-05-31 17:11:03.413680496 +0200 @@ -0,0 +1,255 @@ +#ifndef PORT_XPORT_XLMAC_H_ +#define PORT_XPORT_XLMAC_H_ + +#include "port_xport.h" + +#include "regs/xport_xlmac_core.h" +#include "regs/xport_xlmac_reg.h" +#include "regs/xport_mib_core.h" +#include "regs/xport_reg.h" +#include "regs/xport_mib_reg.h" +#include "regs/xport_mab.h" +#include "regs/xlif.h" + +struct xlmac_mib { + u64 rx_64; + u64 rx_127; + u64 rx_255; + u64 rx_511; + u64 rx_1023; + u64 rx_1518; + u64 rx_1522; + u64 rx_2047; + u64 rx_4095; + u64 rx_9216; + u64 rx_16383; + u64 rx_pkt; + u64 rx_uca; + u64 rx_mca; + u64 rx_bca; + u64 rx_fcs; + u64 rx_cf; + u64 rx_pf; + u64 rx_pp; + u64 rx_uo; + u64 rx_uda; + u64 rx_wsa; + u64 rx_aln; + u64 rx_flr; + u64 rx_frerr; + u64 rx_fcr; + u64 rx_ovr; + u64 rx_jbr; + u64 rx_mtue; + u64 rx_mcrc; + u64 rx_prm; + u64 rx_vln; + u64 rx_dvln; + u64 rx_trfu; + u64 rx_pok; + u64 rx_pfcoff0; + u64 rx_pfcoff1; + u64 rx_pfcoff2; + u64 rx_pfcoff3; + u64 rx_pfcoff4; + u64 rx_pfcoff5; + u64 rx_pfcoff6; + u64 rx_pfcoff7; + u64 rx_pfcp0; + u64 rx_pfcp1; + u64 rx_pfcp2; + u64 rx_pfcp3; + u64 rx_pfcp4; + u64 rx_pfcp5; + u64 rx_pfcp6; + u64 rx_pfcp7; + u64 rx_schcrc; + u64 rx_byt; + u64 rx_rpkt; + u64 rx_und; + u64 rx_frg; + u64 rx_rbyt; + u64 tx_64; + u64 tx_127; + u64 tx_255; + u64 tx_511; + u64 tx_1023; + u64 tx_1518; + u64 tx_1522; + u64 tx_2047; + u64 tx_4095; + u64 tx_9216; + u64 tx_16383; + u64 tx_pok; + u64 tx_pkt; + u64 tx_uca; + u64 tx_mca; + u64 tx_bca; + u64 tx_pf; + u64 tx_pfc; + u64 tx_jbr; + u64 tx_fcs; + u64 tx_cf; + u64 tx_ovr; + u64 tx_dfr; + u64 tx_edf; + u64 tx_scl; + u64 tx_mcl; + u64 tx_lcl; + u64 tx_xcl; + u64 tx_frg; + u64 tx_err; + u64 tx_vln; + u64 tx_dvln; + u64 tx_rpkt; + u64 tx_ufl; + u64 tx_pfcp0; + u64 tx_pfcp1; + u64 tx_pfcp2; + u64 tx_pfcp3; + u64 tx_pfcp4; + u64 tx_pfcp5; + u64 tx_pfcp6; + u64 tx_pfcp7; + u64 tx_ncl; + u64 tx_byt; + u64 rx_lpi; + u64 rx_dlpi; + u64 tx_lpi; + u64 tx_dlpi; + u64 rx_ptllfc; + u64 rx_ltllfc; + u64 rx_llfcfcs; + u64 tx_ltllfc; +}; + +struct xport_xlmac_priv { + struct xport_priv *port; + + unsigned int xlmac_id; + struct xlmac_mib mib; + + phy_interface_t interface; + bool aneg_error_reported; + + int sgmii_serdes_speed; + bool sgmii_config_set; +}; + + +/* + * io accessors + */ +static inline u32 xlif_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[2] + offset); +} + +static inline void xlif_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[2] + offset); +} + +static inline u32 xport_xlmreg_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + + XPORT_XLMAC_REG_OFFSET_0 + offset); +} + +static inline void xport_xlmreg_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + + XPORT_XLMAC_REG_OFFSET_0 + offset); +} + +static inline u64 xport_xlmcore_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + u32 val32, hold; + u64 ret; + + /* indirect access */ + val32 = ioread32(mode->port->regs[1] + + XPORT_XLMAC_CORE_OFFSET(mode->xlmac_id) + offset); + hold = xport_xlmreg_reg_readl(mode, + XPORT_XLMAC_REG_DIR_ACC_DATA_READ_REG); + + ret = (((u64)hold) << 32) | val32; + return ret; +} + +static inline void xport_xlmcore_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u64 val) +{ + u32 val32, hold; + + val32 = val & 0xffffffff; + hold = val >> 32; + + xport_xlmreg_reg_writel(mode, + XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_REG, + hold); + iowrite32(val, mode->port->regs[1] + + XPORT_XLMAC_CORE_OFFSET(mode->xlmac_id) + offset); +} + +static inline u32 xport_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + + XPORT_REG_OFFSET_0 + offset); +} + +static inline void xport_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + + XPORT_REG_OFFSET_0 + offset); +} + +static inline u32 xport_mib_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + + XPORT_MIB_REG_OFFSET_0 + offset); +} + +static inline void xport_mib_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + XPORT_MIB_REG_OFFSET_0 + offset); +} + +static inline u64 xport_mib_core_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + u32 val32, hold; + u64 ret; + + /* indirect access */ + val32 = ioread32(mode->port->regs[1] + + XPORT_MIB_CORE_OFFSET(mode->xlmac_id) + offset); + hold = xport_mib_reg_readl(mode, + XPORT_MIB_REG_DIR_ACC_DATA_READ_REG); + + ret = (((u64)hold) << 32) | val32; + return ret; +} + +static inline u32 xport_mab_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + XPORT_MAB_OFFSET_0 + offset); +} + +static inline void xport_mab_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + XPORT_MAB_OFFSET_0 + offset); +} + +#endif /* PORT_XPORT_XLMAC_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn.h 2023-03-09 15:06:11.360234118 +0100 @@ -0,0 +1,3456 @@ +#ifndef EPON_EPN_H_ +#define EPON_EPN_H_ + +/* relative to epon */ +#define EPN_OFFSET_0 0x1000 + +/* + * Register + * + * This register controls and configures the modules in the EPON block. + */ +#define EPN_CONTROL_0_REG 0x0 + +/* + * Enable IEEE 1588 packet timestamping, applicable only inpoint-to-point + * mode. +*/ +#define CONTROL_0_CFGEN1588TS_MASK 0x80000000 + +/* + * Replaces FCS of upstream packet, resulting in no change in + * packet'slength. + * Set cfgAppendUpFcs/cfgReplaceUpFcs to 0 for pass-through. +*/ +#define CONTROL_0_CFGREPLACEUPFCS_MASK 0x40000000 + +/* + * Appends FCS to upstream packet, resulting in increase of packet'slength + * +4 bytes. + * Set cfgAppendUpFcs/cfgReplaceUpFcs to 0 forpass-through. +*/ +#define CONTROL_0_CFGAPPENDUPFCS_MASK 0x20000000 + +/* + * Drops Single Copy Broadcast packets that are unmapped by the LIF. + * 0: + * Ignore LLID bit 15. + * 1: + * Drop packets that have LLID bit 15 set and have LLID index bit 5set. +*/ +#define CONTROL_0_CFGDROPSCB_MASK 0x10000000 + +/* + * Ignores the first queue set limits. + * This is only applied whenThreshold First Queue Service Discipline is + * enabled. + * 0: + * Transmit packets in the order they were last reported in thefirst queue + * set. + * 1: + * Transmit packets in the order they were last reported in theun-capped + * queue set. +*/ +#define CONTROL_0_MODUNCAPPEDREPORTLIMIT_MASK 0x8000000 + +/* + * Enables Threshold First Queue Service Discipline. + * This is onlyapplied to multi-priority reporting mode. + * 0: + * Strict priority. + * The highest priority packet is transmitted. + * This mode 'pulls' late-arriving/un-reported high priority packetsahead + * of previously reported lower priority packets. + * 1: + * Transmit packets in the order they were last reported. +*/ +#define CONTROL_0_MODMPQUESETFIRST_MASK 0x4000000 + +/* + * Propagates the ONU's local MPCP time by replacing the last fourbytes of + * a GATE frame with the MPCP time the GATE arrived at theONU. + * This only applies to downstream gate messages passed from theEpn to the + * BBH. + * 0: + * Do not propagate the local MPCP time1: + * Propagate the local MPCP time +*/ +#define CONTROL_0_PRVLOCALMPCPPROPAGATION_MASK 0x1000000 + +/* + * Allows accumulator 3 to be prefetched before accumulator 0 isemptied and + * the accumulator shift occurs. + * This eliminates the racestarting when the accumulators shift and their + * values are reported(i. + * e. + * accumulator 3 will fully represent the current queue state). + * 0: + * Do not prefetch accumulator 31: + * Prefetch accumulator 3 +*/ +#define CONTROL_0_PRVTEKMODEPREFETCH_MASK 0x800000 + +/* + * Causes non-zero accumulator values to be incremented before + * beingreported upstream. + * 0: + * No accumulator values are incremented1: + * Non-zero accumulator values are incremented +*/ +#define CONTROL_0_PRVINCNONZEROACCUM_MASK 0x200000 + +/* + * Disables FCS checking of un-mapped frames. + * This is intended to beused when passing unmapped frames to a UNI port. + * 0: + * All FCS errored un-mapped frames are discarded1: + * All un-mapped frames are passed to a UNI port +*/ +#define CONTROL_0_PRVNOUNMAPPPEDFCS_MASK 0x100000 + +/* + * Causes discovery gates for empty queues to be discarded. + * 0: + * All discovery gates are processed1: + * Discovery gates for empty queues are discarded +*/ +#define CONTROL_0_PRVSUPRESSDISCEN_MASK 0x80000 + +/* + * Overrides the value in EPON Downstream Max Size Frame register. + * 0: + * Use Downstream Max Size Frame register value1: + * The maximum frame size for non-VLAN frames is 1518 and themaximum size + * for VLAN-tagged frames is 1522 +*/ +#define CONTROL_0_CFGVLANMAX_MASK 0x40000 + +/* + * Determines which types of upstream frames are affected when + * forcingupstream FCS errors (as configured in EPON Force FCS Error + * register)0: + * Force FCS errors on all upstream frames. + * 1: + * Force FCS errors on user data frames only (not REPORT orprocessor + * frames). +*/ +#define CONTROL_0_FCSERRONLYDATAFR_MASK 0x20000 + +/* + * Determines handling of traffic not mapped to a provisioned LLID0: + * Forward unmapped packets1: + * Drop unmapped packets +*/ +#define CONTROL_0_PRVDROPUNMAPPPEDLLID_MASK 0x1000 + +/* + * Controls LLID mode bit suppression0: + * LLID mode enabled1: + * Suppress LLID mode by masking bit-15 of the LLID +*/ +#define CONTROL_0_PRVSUPPRESSLLIDMODEBIT_MASK 0x800 + +/* + * Discovery gate destination address filter enable. + * 0: + * Always ignore discovery gate DA value1: + * Process discovery gate only if the following criteria are met. + * Please keep in mind the functionality provided by the legacy + * "DropDiscovery Gate" controls. + * No discovery gate will be processed if thediscovery gate's LLID index + * has been provisioned to "Drop DiscoveryGates". + * Also, only the first 8 LLID index values are eligible fordiscovery gate + * processing. + * Discovery gates with any other LLID indexvalues received from the LIF + * will not be processed. + * When this feature is disabled the discovery DA is ignored. + * When thisfeature is enabled there are four possible scenarios: + * (1) Received broadcast LLID (0x7FFF) and a unicast (not broadcastand not + * multicast) DA. + * Discovery gate is processed if one of the provisioned ONT addressesmust + * match the discovery gate's DA. + * (2) Received broadcast LLID (0x7FFF) and a broadcast DA. + * Discovery gate is processed. + * i. + * e. + * , the discovery gate's DA isignored. + * (3) Received a non-broadcast LLID and a unicast DA. + * Discovery gate is processed if the discovery gate's LLID + * indexprovisioned ONT address matches its DA. + * (4) Received a non-broadcast LLID and a broadcast DA. + * Discovery gate is processed. + * i. + * e. + * , the discovery gate's DA isignored. + * Please remember the "Drop Discovery Gate" control takes precedenceover + * all other configuration options +*/ +#define CONTROL_0_MODDISCOVERYDAFILTEREN_MASK 0x400 + +/* + * Selects the number of Queue Sets generated for all LLID Indexes0: + * Dual queue set (default)1: + * Multi queue set ('Teknovus-style')Others: + * Reserved +*/ +#define CONTROL_0_RPTSELECT_SHIFT 8 +#define CONTROL_0_RPTSELECT_MASK 0x300 + +/* + * Disables Shaped Virtual Accumulator backpressure of BBH queue + * statusinterface. + * 0: + * SVA normal operation. + * Allows shapers to backpressure the BBHqueue status interface. + * 1: + * Disables Shaped Virtual Accumulator backpressure of BBH queuestatus + * interface. + * . +*/ +#define CONTROL_0_PRVDISABLESVAQUESTATUSBP_MASK 0x80 + +/* + * Places the upstream transmitter (UTX) in loopback mode. + * 0: + * UTX normal operation1: + * UTX is in loopback mode. + * This setting is also used for Point toPoint mode (in conjunction with + * settings in the LIF Controlregister). +*/ +#define CONTROL_0_UTXLOOPBACK_MASK 0x40 + +/* + * UTX Enable bit. + * 0: + * Disable the UTX block1: + * Enable UTX operation +*/ +#define CONTROL_0_UTXEN_MASK 0x20 + +/* + * Reset the EPN upstream transmitter (UTX) logic. + * Asserting (activelow) this bit resets all UTX state machines and + * pointers. + * Note thatthis does not reset the UTX configuration registers. + * 0: + * Hold the UTX in reset1: + * Normal UTX operation +*/ +#define CONTROL_0_UTXRST_PRE_N_MASK 0x10 + +/* + * Prevents any downstream traffic from being sent to the BBH. + * Thiscontrol is only applied between downstream packets. + * So, it can betoggled any time the drxEn bit is set. + * 0: + * Normal operation. + * 1: + * No data is sent to BBH. +*/ +#define CONTROL_0_CFGDISABLEDNS_MASK 0x8 + +/* + * Places the downstream receiver (DRX) in loopback mode. + * The loopbackmode disables the EPON processing in EPN's downstream data + * path. + * Itdoes not 'loopback' any data. + * 0: + * DRX normal operation1: + * DRX is in loopback mode +*/ +#define CONTROL_0_DRXLOOPBACK_MASK 0x4 + +/* + * DRX Enable bit. + * 0: + * Disable the DRX block1: + * Enable DRX operation +*/ +#define CONTROL_0_DRXEN_MASK 0x2 + +/* + * Reset the EPN downstream receiver (DRX) logic. + * Asserting (activelow) this bit resets all DRX state machines and + * pointers. + * Note thatthis does not reset the DRX configuration registers. + * 0: + * Hold the DRX in reset1: + * Normal DRX operation +*/ +#define CONTROL_0_DRXRST_PRE_N_MASK 0x1 + + +/* + * Register + * + * This register controls and configures the modules in the EPN block. + */ +#define EPN_CONTROL_1_REG 0x4 + +/* + * When this bit is set, the EPON MAC will tag completely tardyupstream + * packets as an idle packet by replacingthe SOF transfer type with 5'd23. + * The XIF will detect the idlepacket SOF tag and replace the entire packet + * with idles. + * In the case of 1G the 5'd23 SOF is converted to 3'd6 to get past + * theTimeStamp logic and then converted to 3'd5 so the LIFcan detect the + * idle packet SOF tag and replace the entire packetwith idles. + * Partially tardy packets are still faked and their FCS valuesreplaced + * with zeros. + * Do not enable this feature for AE or P2Poperating modes. + * Default value is 0 +*/ +#define CONTROL_1_CFGIDLEPACKETTXENABLE_MASK 0x800000 + +/* + * When this bit is set, the EPON MAC will not dither the MPCPcorrection + * values sent to the LIF. + * Default value is 0 +*/ +#define CONTROL_1_CFGDISABLEMPCPCORRECTIONDITHERING_MASK 0x400000 + +/* + * Enables adjustment of "destructively overlapped" grants. + * Destructively overlapped grants are grants that overlap by more thanthe + * provisioned grant overhead (Lon + Loff + Sync time). + * 0: + * Disable adjustment of destructively overlapped grants. + * Destuctively overlapped grants are dropped and the + * GrantMisaligninterrupt sets. + * 1: + * Destructively overlapped grants are adjusted to limit overlap tothe + * grant overhead value (which maximizes the useful length of theearlier + * grant). +*/ +#define CONTROL_1_PRVOVERLAPPEDGNTENABLE_MASK 0x200000 + +/* Reset the grant misalignment hardware */ +#define CONTROL_1_RSTMISALIGNTHR_MASK 0x100000 + +/* + * When this bit is set, the EPON MAC will check the grant FIFOs forstale + * grants, and delete them. + * A stale grant has a grant start timethat is smaller (earlier) than the + * local ONU time. + * Default value is1 +*/ +#define CONTROL_1_CFGSTALEGNTCHK_MASK 0x40000 + +/* + * Global upstream FEC enable. + * When this bit is set, the EPON MAC willtake into account FEC overhead + * when generating report frames andfilling grants. + * Please note that the per-LLID index bit must also beset. +*/ +#define CONTROL_1_FECRPTEN_MASK 0x20000 + +/* + * Enables an alternate scheme in the L1-to-L2 strict-priorityscheduler. + * This alternate scheme is useful only when bothcfgSharedBurstCap and + * cfgSharedL2 are set ("TK3715 CTCcompatibility" mode). + * Note: + * Support for this bit begins in Revision B0. + * 0: + * Default scheme. + * 1: + * Alternate mode. + * Use only in multi-priority mode whencfgSharedBurstCap is set. +*/ +#define CONTROL_1_CFGL1L2TRUESTRICT_MASK 0x80 + +/* + * Sets the number of priorities for multi-priority mode. + * The 24available L2s queues are sequentially mapped to the + * prioritieswithin each LLID index. + * For example in mode "01": + * L2s queue 0 ismapped to LLID index 0 priority 0; L2s queue 1 is mapped + * to LLIDindex 0 priority 1; L2s queue 2 is mapped to LLID index 0 + * priority2; L2s queue 3 is mapped to LLID index 1 priority 0; and so on. + * 00: + * Multi-priority mode disabled. + * 01: + * Eight LLID indexes with 3 priorities each. + * 10: + * Six LLID indexes with 4 priorities each. + * 11: + * Three LLID indexes with 8-priorities each. +*/ +#define CONTROL_1_CFGCTCRPT_SHIFT 5 +#define CONTROL_1_CFGCTCRPT_MASK 0x60 + +/* + * Disables incremental (+1, -1) correction of local downstream MPCPtime. + * When set, MPCP time is updated only when the differencebetween the local + * MPCP time and the timestamp received in an MPCPDUis different by greater + * than the EPN Time Stamp Differentialregister value. +*/ +#define CONTROL_1_CFGTSCORRDIS_MASK 0x10 + +/* When set the ONU will ignore the force report bit on discoveryframes. */ +#define CONTROL_1_CFGNODISCRPT_MASK 0x8 + +/* + * When this bit is set, the start time offset for a discovery responsewill + * be equal to the discovery seed. + * Units of the offset are 16-bittimes. +*/ +#define CONTROL_1_DISABLEDISCSCALE_MASK 0x4 + +/* All statistics RAM reads will clear the read location. */ +#define CONTROL_1_CLRONRD_MASK 0x2 + + +/* + * Register + * + * This register allows per-LLID control over whether the EPON MAC + * acceptsgrants from the OLT. + */ +#define EPN_ENABLE_GRANTS_REG 0x8 + +/* + * Enable Grants on LLID Index 0. + * Reset default is 1. +*/ +#define ENABLE_GRANTS_ENGNTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over whether the EPON MACprocesses + * Discovery Gates. + */ +#define EPN_DROP_DISC_GATES_REG 0xc + +/* Discard Discovery Gates on LLID Index 0. */ +#define DROP_DISC_GATES_SINKDISCGATESx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over Ethernet frame CRC checkingin + * the EPON downstream block. + */ +#define EPN_DIS_FCS_CHK_REG 0x10 + +/* Do not check FCS on downstream frames received on LLID index 0 */ +#define DIS_FCS_CHK_DISABLEFCSCHKx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over whether the EPON MAC + * passesdownstream gate frames to the BBH. + */ +#define EPN_PASS_GATES_REG 0x14 + +/* If set, downstream gate frames will be passed to the BBH for LLID 0 */ +#define PASS_GATES_PASSGATELLIDx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over grant misalignment + * checkingand feedback. + */ +#define EPN_CFG_MISALGN_FB_REG 0x18 + +/* + * 0: + * Ignore misalignment condition1: + * Enable grant misalignment detection on LLID Index 0. + * Whendetected, EPON MAC will temporarily report empty queue status(REPORT + * frame) on the LLID Index. +*/ +#define CFG_MISALGN_FB_CFGMISALIGNFEEDBACKx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * The 10G Discovery Information field is 16 bits right after the Synctime + * in the Disc Gate. + * The 10G discovery gate filter consistes of twobit-fields: + * a 16-bit Disc Info Value and 16-bit Disc Info Mask. + * For allbits in Disc Info Value whose corresponding Mask bits are clear + * (notmasked), the bits in Disc Info Value must exactly match + * thecorresponding bits in the GATE Discovery Information field. + * If theydon't match, drop the GATE (nothing is added into the Grant + * FIFO). + * Ifthey match, the Start Time and Length are added to the Grant FIFO. + */ +#define EPN_DISCOVERY_FILTER_REG 0x1c + +/* + * Any mask bit that is set will exclude its corresponding bit from + * theabove comparison (i. + * e. + * set mask bits are considered "don't carebits). +*/ +#define DISCOVERY_FILTER_PRVDISCINFOMASK_SHIFT 16 +#define DISCOVERY_FILTER_PRVDISCINFOMASK_MASK 0xffff0000 + +/* The value to match */ +#define DISCOVERY_FILTER_PRVDISCINFOVALUE_SHIFT 0 +#define DISCOVERY_FILTER_PRVDISCINFOVALUE_MASK 0xffff + + +/* + * Register + * + * The EPN requires a minimum amount of time to process each grant. + * Thisprocessing time includes the time for the BBH to fetch a packet + * andsetup time for theupstream data to be processed by the LIF/XIF. + * It is possible forbackpressure generated by the BBH and LIF/XIF to stall + * the grantprocessing beyond the time required to process the grant. + * Any grants that are not processed this many TimeQuanta before it + * GrantStart Time will be aborted and a grant miss-abort interrupt will + * begenerated. + */ +#define EPN_MINIMUM_GRANT_SETUP_REG 0x20 + +/* + * Minimum amount of grant processing time required to guarantee + * theupstream data will be transmitted. + * The units are EPON TimeQuanta(16 nS). +*/ +#define MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_SHIFT 0 +#define MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_MASK 0xffff + + +/* + * Register + * + * This register allows resetting of the Grant FIFOs on a per-LLID basis. + */ +#define EPN_RESET_GNT_FIFO_REG 0x24 + +/* Resets the read and write pointers for grant FIFO 0. */ +#define RESET_GNT_FIFO_RSTGNTFIFOx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows resetting of the L1 accumulators. + */ +#define EPN_RESET_L1_ACCUMULATOR_REG 0x28 + +/* Set the respective bit(s) to reset L1 accumulator(s). */ +#define RESET_L1_ACCUMULATOR_CFGL1SCLRACUM_SHIFT 0 +#define RESET_L1_ACCUMULATOR_CFGL1SCLRACUM_MASK 0xffffffff + + +/* + * Register + * + * This register selects which virtual accumulator sizes are reported. + */ +#define EPN_L1_ACCUMULATOR_SEL_REG 0x2c + +/* Selects which L1S Un-shaped Virtual Accumulator size will bereported. */ +#define L1_ACCUMULATOR_SEL_CFGL1SUVASIZESEL_SHIFT 5 +#define L1_ACCUMULATOR_SEL_CFGL1SUVASIZESEL_MASK 0x3e0 + +/* Selects which L1S Shaped Virtual Accumulator size will be reported. */ +#define L1_ACCUMULATOR_SEL_CFGL1SSVASIZESEL_SHIFT 0 +#define L1_ACCUMULATOR_SEL_CFGL1SSVASIZESEL_MASK 0x1f + + +/* + * Register - read-only + * + * Signed number of bytes in the selected L1S Shaped Virtual Accumulator + */ +#define EPN_L1_SVA_BYTES_REG 0x30 + +/* + * Signed number of bytes in the selected L1S Shaped VirtualAccumulator. + * Bit-29 is the sign bit. + * A negative number indicates the Runner/BBHcreated a rounding errorBit-28 + * can be considered an overflow indication. + * Bits 27-0 are the actual number of bytes. +*/ +#define L1_SVA_BYTES_L1SSVASIZE_SHIFT 0 +#define L1_SVA_BYTES_L1SSVASIZE_MASK 0x3fffffff + + +/* + * Register - read-only + * + * Signed number of bytes in the selected L1S Un-shaped VirtualAccumulator + */ +#define EPN_L1_UVA_BYTES_REG 0x34 + +/* + * Signed number of bytes in the selected L1S Un-shaped VirtualAccumulator. + * Bit-29 is the sign bit. + * A negative number indicates the Runner/BBHcreated a rounding errorBit-28 + * can be considered an overflow indication. + * Bits 27-0 are the actual number of bytes. +*/ +#define L1_UVA_BYTES_L1SUVASIZE_SHIFT 0 +#define L1_UVA_BYTES_L1SUVASIZE_MASK 0x3fffffff + + +/* + * Register - read-only + * + * Indicates which SVAs have overflowed + */ +#define EPN_L1_SVA_OVERFLOW_REG 0x38 + +/* + * Indicates which SVAs have overflowed. + * The overflow can only becorrected by reset. +*/ +#define L1_SVA_OVERFLOW_L1SSVAOVERFLOW_SHIFT 0 +#define L1_SVA_OVERFLOW_L1SSVAOVERFLOW_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates which UVAs have overflowed + */ +#define EPN_L1_UVA_OVERFLOW_REG 0x3c + +/* + * Indicates which UVAs have overflowed. + * The overflow can only becorrected by reset. +*/ +#define L1_UVA_OVERFLOW_L1SUVAOVERFLOW_SHIFT 0 +#define L1_UVA_OVERFLOW_L1SUVAOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + * This register allows real-time forcing the per-priority report valuesto + * zero. + * This applies only to multi-priority reporting modes (CTC,NTT). + * Note: + * These bits are used for debug only. + */ +#define EPN_RESET_RPT_PRI_REG 0x40 + +/* Force priority 0 report values to zero. */ +#define RESET_RPT_PRI_NULLRPTPRIx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows resetting of the L2 Report FIFO pointers. + * Thecorresponding L2 accumulators are also cleared. + */ +#define EPN_RESET_L2_RPT_FIFO_REG 0x44 + +/* Set the respective bit(s) to reset L2 FIFO(s). */ +#define RESET_L2_RPT_FIFO_CFGL2SCLRQUE_SHIFT 0 +#define RESET_L2_RPT_FIFO_CFGL2SCLRQUE_MASK 0xffffffff + + +/* + * Register + * + * This register allows per-LLID enabling of upstream traffic. + * Disablingthe upstream on a particular LLID Index means that: + * 1. + * REPORT frames sent upstream on the LLID Index will report NOdata2. + * Grants on the LLID Index will be acted upon (the laser willturn on and + * any requested REPORT frame will be sent), but no userframes will be + * pulled from FIF and sent upstream. + */ +#define EPN_ENABLE_UPSTREAM_REG 0x48 + +/* Set the respective bit(s) to enable the upstream LLID(s). */ +#define ENABLE_UPSTREAM_CFGENABLEUPSTREAMREG_SHIFT 0 +#define ENABLE_UPSTREAM_CFGENABLEUPSTREAMREG_MASK 0xffffffff + + +/* + * Register - read-only + * + * Feedback register to indicate pending/complete changes in the EPNEnable + * Upstream register. + * A non-zero result from a bitwise XOR betweenthis register and EPN Enable + * Upstream indicates that a new valuewritten to EPN Enable Upstream has + * not yet taken effect. + */ +#define EPN_ENABLE_UPSTREAM_FB_REG 0x4c + +/* + * Indicates the operational state of the upstream LLIDs. + * SeeEPN_ENABLE_UPSTREAM register description for details. +*/ +#define ENABLE_UPSTREAM_FB_CFGENABLEUPSTREAMFEEDBACK_SHIFT 0 +#define ENABLE_UPSTREAM_FB_CFGENABLEUPSTREAMFEEDBACK_MASK 0xffffffff + + +/* + * Register + * + * Per-LLID index based upstream FEC enable. + * Set the bit corresponding tothe LLID index to enable FEC overhead to be + * added to the packet lengthadjustment. + * Please note that the global FEC enable in Control register1 must also be + * set. + * For 10G upstream operation, per-LLID FEC enable isnot supported; set all + * of these bits for FEC operation, and clear allof them for non-FEC. + */ +#define EPN_ENABLE_UPSTREAM_FEC_REG 0x50 + +/* Set the respective bit(s) to enable upstream FEC for LLID(s). */ +#define ENABLE_UPSTREAM_FEC_CFGENABLEUPSTREAMFEC_SHIFT 0 +#define ENABLE_UPSTREAM_FEC_CFGENABLEUPSTREAMFEC_MASK 0xffffffff + + +/* + * Register + * + * The number of bytes of 10G upstream payload that should be reserved fora + * piggy-back report. + * Note that if the "force report" is not set then this register is + * notused. + * Also, this value must be increased by 16-bytes for FEC-lessupstream 10G + * mode. + * The extra bytes are required to compensate for the10G upstream + * "scrambler sync pattern". + */ +#define EPN_REPORT_BYTE_LENGTH_REG 0x54 + +/* Number of bytes reserved for upstream report. */ +#define REPORT_BYTE_LENGTH_PRVRPTBYTELEN_SHIFT 0 +#define REPORT_BYTE_LENGTH_PRVRPTBYTELEN_MASK 0xff + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + * The Data Port Busy Interrupt indicates whether or not the data port + * isfree to do another RAM access. + * The Grant Full interrupt indicates that a grant was aborted due to + * itsgrant FIFO being full. + * The Missed Grant interrupt indicates that a grant missed its time + * totransmit and was aborted. + * This occurs from the MPCP time havingexceeded the start time when the + * grant is to be scheduled. + * (Note thatgrant start time is adjusted by the Grant Start Time Delta + * register forthis calculation)The Grant Interval interrupt indicates that + * an LLID is not receivinggates quickly enough. + * If the amount of time elapsed since receiving aGate frame exceeds a + * programmed value the interrupt will be asserted. + * See the EPON LLID Grant Interval register. + * The Discovery Gate interrupt indicates that a discovery gate + * wasreceived. + * The Local Time Not Synced interrupt is used to indicate that the + * ONU'slocal time is out of sync with EPON time. + * The time a MPCPDU framesarrives is compared with the value of its time + * stamp. + * If thisdifference is greater than value specified by the Time + * StampDifferential register the interrupt will assert. + * The Local Time Synced interrupt is used to indicate that the ONU'slocal + * time is in sync with the OLT EPON time. + * The time a MPCPDU framesarrives is compared with the value of its time + * stamp. + * If thisdifference is less than or equal to the value specified by the + * TimeStamp Differential register the interrupt will assert. + */ +#define EPN_MAIN_INT_STATUS_REG 0x58 + +/* + * Indicates the Runner/BBH aborted an upstream frame transfer. + * Pleasereference the Runner/BBH documentation for a list of events + * thatwill cause Runner/BBH to abort packets. +*/ +#define MAIN_INT_STATUS_INTBBHUPFRABORT_MASK 0x80000000 + +/* + * Coalesced per-L2 burst cap overflow event indicator. + * This istriggered when the burst cap is dynamically resized below + * respectiveL2 accumulator's value. +*/ +#define MAIN_INT_STATUS_INTCOL2SBURSTCAPOVERFLOWPRES_MASK 0x40000000 + +/* + * Coalesced Empty Report interrupt. + * One or more LLID indexes has atransmitted a report in which all time + * quanta values were zero. + * SeeEPON Empty Report Interrupt Status for per-LLID Index interruptbits. +*/ +#define MAIN_INT_STATUS_INTCOEMPTYRPT_MASK 0x20000000 + +/* + * The Drx detected an error that required the frame to be aborted. + * Culpable errors are FCS, oversize-frame, or undersize-frame. + * Note: + * The intDrxErrorAbortMask will prevent this 'coalesced bit frombeing set. + * This is in contrast to the 'individual' bits (0x41b)still being set even + * if the interrupt is masked. +*/ +#define MAIN_INT_STATUS_INTCODRXERRABORTPRES_MASK 0x10000000 + +/* + * The Level 2 structure FIFO has overflowed. + * A frame length has beenlost. + * The Runner/BBH and EPN must be reset to recover from this. +*/ +#define MAIN_INT_STATUS_INTL2SFIFOOVERRUN_MASK 0x8000000 + +/* + * Coalesced 1588 timestamp interrupt. + * SeeEPN_1588_TIMESTAMP_INT_STATUS for the interupts. +*/ +#define MAIN_INT_STATUS_INTCO1588TSINT_MASK 0x4000000 + +/* + * Coalesced Report FIFO non-empty interrupt. + * One or more LLID indiceshas a frame length present in its report FIFO. + * See EPON ReportPresent Interrupt Status for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCORPTPRES_MASK 0x2000000 + +/* + * Coalesced Grant Ready interrupt. + * One or more LLID indexes has agrant present in its Grant RAM. + * See EPON Grant Present InterruptStatus for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTPRES_MASK 0x1000000 + +/* + * Coalesced stale grant delete interrupt. + * One or more LLID indexesdeleted a grant deleted from its grant RAM. + * See EPON Deleted StaleGrant Interrupt Status for per-LLID Index + * interrupt bits. +*/ +#define MAIN_INT_STATUS_INTCODELSTALEGNT_MASK 0x800000 + +/* + * Coalesced grant non-poll interrupt. + * One or more LLID indexesexceeded the Non-poll grant interval. + * See EPON Non-Poll GrantInterrupt Status for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTNONPOLL_MASK 0x400000 + +/* + * Coalesced grant misalign interrupt. + * One or more LLID indexesreceived a grant that was not aligned on frame + * boundaries. + * See EPONGrant Misalign Interrupt Status for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTMISALIGN_MASK 0x200000 + +/* + * Coalesced grant too far abort interrupt. + * One or more LLID indexesreceived a grant for greater than 34 seconds + * into the future. + * SeeEPON Grant Too Far Interrupt Status for per-LLID Index interruptbits. + * Note: + * This interrupt can set during registration of the first LLIDIndex + * (before the local MPCP clock is synchronized to the OLT). + * Firmware should check and clear this interrupt while registering + * thefirst link. +*/ +#define MAIN_INT_STATUS_INTCOGNTTOOFAR_MASK 0x100000 + +/* + * Coalesced grant interval interrupt. + * One or more LLID indexes is notreceiving gates fast enough. + * See EPON Grant Interval InterruptStatus for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTINTERVAL_MASK 0x80000 + +/* + * Coalesced Discovery Gate received interrupt. + * One or more LLIDindexes received a Discovery Gate. + * See EPON Discovery Gate InterruptStatus for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTDISCOVERY_MASK 0x40000 + +/* + * Coalesced grant miss abort interrupt. + * One or more LLID indexesaborted a grant because it missed its slot time + * to transmit. + * SeeEPON Grant Miss Interrupt Status for per-LLID Index interrupt bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTMISSABORT_MASK 0x20000 + +/* + * Coalesced grant full abort interrupt. + * One or more LLID indexesaborted a grant due to its grant FIFO being + * full. + * See EPON GrantFull Interrupt Status for per-LLID Index interrupt bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTFULLABORT_MASK 0x10000 + +/* + * [FATAL] The EPN received an upstream frame whose length did notmatch the + * expected frame length. + * This is a fatal event. + * The entiredata path must be reset to recover from this event. +*/ +#define MAIN_INT_STATUS_INTBADUPFRLEN_MASK 0x8000 + +/* + * The Runner/BBH upstream data path failed to deliver upstream data intime + * to meet the upPacketTxMargin requirement. +*/ +#define MAIN_INT_STATUS_INTUPTARDYPACKET_MASK 0x4000 + +/* Report frame has been transmitted by EPON MAC. */ +#define MAIN_INT_STATUS_INTUPRPTFRXMT_MASK 0x2000 + +/* + * [FATAL] The burst information FIFO over ran. + * This is a fatal eventand requires the entire device to be reset and + * re-initialized. +*/ +#define MAIN_INT_STATUS_INTBIFIFOOVERRUN_MASK 0x1000 + +/* + * A grant passed to the Upstream transmitter has size greater thanthat + * defined EPON Max Grant Size register. +*/ +#define MAIN_INT_STATUS_INTBURSTGNTTOOBIG_MASK 0x800 + +/* + * A grant written into EPON grant RAM has size greater than thatdefined + * EPON Max Grant Size register. +*/ +#define MAIN_INT_STATUS_INTWRGNTTOOBIG_MASK 0x400 + +/* + * A grant received by EPON MAC has size greater than that defined inthe + * EPON Max Grant Size register. +*/ +#define MAIN_INT_STATUS_INTRCVGNTTOOBIG_MASK 0x200 + +/* + * EPON block cannot accumulate statistics quickly enough to count + * runtframes. + * Bursts of frames less than 20 bytes in size will cause thisinterrupt. +*/ +#define MAIN_INT_STATUS_INTDNSTATSOVERRUN_MASK 0x100 + +/* EPON block was not able to process an upstream transmission event. */ +#define MAIN_INT_STATUS_INTUPSTATSOVERRUN_MASK 0x80 + +/* An out of order grant was received */ +#define MAIN_INT_STATUS_INTDNOUTOFORDER_MASK 0x40 + +/* + * [FATAL] Fatal Event. + * The Runner/BBH upstream data path stoppeddelivering packets. + * All upstream traffic for all LLID indexes hasbeen halted. + * Any upstream grants received are terminated with emptyreports (if + * requested). + * The only way to recover from this fatalevent is to reset the entire + * upstream data path. + * Check the EPN Fatal Upstream Fault Interrupt Status register to seewhich + * LLID(s) experienced the fault. +*/ +#define MAIN_INT_STATUS_INTTRUANTBBHHALT_MASK 0x20 + +/* + * Grant length is less than overhead. + * Possible configuration error. +*/ +#define MAIN_INT_STATUS_INTUPINVLDGNTLEN_MASK 0x10 + +/* + * [FATAL] Coalesced per-LLID index Runner/BBH fatal upstream deliveryfault + * indicator. + * Runner/BBH has lost coherency with the EPN. + * Thefour trigger events are: + * 1. + * Runner/BBH aborted a packet2. + * Runner/BBH transferred a packet shorter than was requested3. + * Runner/BBH transferred a packet longer than was requested4. + * Runner/BBH stopped transferring packets (as indicated + * byintTruantBbhHalt, below)Check the EPN Fatal Upstream Fault Interrupt + * Status register to seewhich LLID(s) experienced the fault. +*/ +#define MAIN_INT_STATUS_INTCOBBHUPSFAULT_MASK 0x8 + +/* ONU timer is in sync */ +#define MAIN_INT_STATUS_INTDNTIMEINSYNC_MASK 0x4 + +/* ONU timer is out of sync */ +#define MAIN_INT_STATUS_INTDNTIMENOTINSYNC_MASK 0x2 + +/* + * EPON Data Port is ready0: + * Data Port is busy1: + * Data Port is ready +*/ +#define MAIN_INT_STATUS_INTDPORTRDY_MASK 0x1 + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_FULL_INT_STATUS_REG 0x5c + +/* LLID index 0 aborted a grant due to its grant FIFO being full. */ +#define GNT_FULL_INT_STATUS_INTDNGNTFULLABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_FULL_INT_MASK_REG 0x60 + +/* + * Mask LLID index 0 aborted a grant due to its grant FIFO being + * fullinterrupt. +*/ +#define GNT_FULL_INT_MASK_MASKINTDNGNTFULLABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_MISS_INT_STATUS_REG 0x64 + +/* LLID index 0 aborted a grant because it missed its slot time totransmit. */ +#define GNT_MISS_INT_STATUS_INTDNGNTMISSABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_MISS_INT_MASK_REG 0x68 + +/* + * Mask LLID index 0 aborted a grant because it missed its slot time + * totransmit interrupt. +*/ +#define GNT_MISS_INT_MASK_MASKINTDNGNTMISSABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_DISC_RX_INT_STATUS_REG 0x6c + +/* LLID index 0 received a discovery gate */ +#define DISC_RX_INT_STATUS_INTDNGNTDISCOVERYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_DISC_RX_INT_MASK_REG 0x70 + +/* Mask LLID index 0 received a discovery gate interrupt. */ +#define DISC_RX_INT_MASK_MASKINTDNGNTDISCOVERYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_INTV_INT_STATUS_REG 0x74 + +/* + * LLID index 0 failed to receive a GATE within a time period definedby the + * EPN Grant Interval register. +*/ +#define GNT_INTV_INT_STATUS_INTDNGNTINTERVALx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_INTV_INT_MASK_REG 0x78 + +/* + * Mask LLID index 0 failed to receive a GATE within a time perioddefined + * by the EPN Grant Interval register interrupt. +*/ +#define GNT_INTV_INT_MASK_MASKINTDNGNTINTERVALx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_FAR_INT_STATUS_REG 0x7c + +/* + * LLID index 0 received (and aborted) a grant with a start timegreater + * than 34 sec in the future +*/ +#define GNT_FAR_INT_STATUS_INTDNGNTTOOFARx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_FAR_INT_MASK_REG 0x80 + +/* + * Mask LLID index 0 received (and aborted) a grant with a start + * timegreater than 34 sec in the future interrupt +*/ +#define GNT_FAR_INT_MASK_MASKDNGNTTOOFARx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_MISALGN_INT_STATUS_REG 0x84 + +/* LLID index 0 received a misaligned grant */ +#define GNT_MISALGN_INT_STATUS_INTDNGNTMISALIGNx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_MISALGN_INT_MASK_REG 0x88 + +/* Mask LLID index 0 received a misaligned grant interrupt */ +#define GNT_MISALGN_INT_MASK_MASKINTDNGNTMISALIGNx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_NP_GNT_INT_STATUS_REG 0x8c + +/* Non poll grant interval exceeded on LLID Index 0 */ +#define NP_GNT_INT_STATUS_INTDNGNTNONPOLLx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_NP_GNT_INT_MASK_REG 0x90 + +/* Non poll grant interval exceeded on LLID Index 0 interrupt mask */ +#define NP_GNT_INT_MASK_MASKDNGNTNONPOLLx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_DEL_STALE_INT_STATUS_REG 0x94 + +/* Stale grant deleted from LLID Index 0 grant RAM. */ +#define DEL_STALE_INT_STATUS_INTDELSTALEGNTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * Interrupt mask for EPN_DEL_STALE_INT_STATUS + */ +#define EPN_DEL_STALE_INT_MASK_REG 0x98 + +/* Stale grant deleted from LLID Index 0 grant RAM interrupt mask. */ +#define DEL_STALE_INT_MASK_MASKINTDELSTALEGNTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write a 1 to it. + */ +#define EPN_GNT_PRES_INT_STATUS_REG 0x9c + +/* Grant present in LLID Index 0 grant RAM */ +#define GNT_PRES_INT_STATUS_INTDNGNTRDYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_PRES_INT_MASK_REG 0xa0 + +/* Grant present in LLID Index 0 grant RAM interrupt mask */ +#define GNT_PRES_INT_MASK_MASKDNGNTRDYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_RPT_PRES_INT_STATUS_REG 0xa4 + +/* Frame length present in LLID Index 0 report FIFO */ +#define RPT_PRES_INT_STATUS_INTUPRPTFIFOx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_RPT_PRES_INT_MASK_REG 0xa8 + +/* Frame length present in LLID Index 0 report FIFO interrupt mask */ +#define RPT_PRES_INT_MASK_MASKINTUPRPTFIFOx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the Drx error abort events. + * These bits are sticky; to clear a bit, write 1 to it. + */ +#define EPN_DRX_ABORT_INT_STATUS_REG 0xac + +/* + * The Drx detected an error that required an LLID Index 0-31 + * (bitwise)frame be aborted in the RDP +*/ +#define DRX_ABORT_INT_STATUS_INTDRXERRABORT_SHIFT 0 +#define DRX_ABORT_INT_STATUS_INTDRXERRABORT_MASK 0xffffffff + + +/* + * Register + * + * This register contains interrupt mask for the Drx error abort events. + */ +#define EPN_DRX_ABORT_INT_MASK_REG 0xb0 + +/* + * Mask the Drx detected an error that required an LLID Index 0-31(bitwise) + * frame be aborted in the RDP interrupt. +*/ +#define DRX_ABORT_INT_MASK_MASKINTDRXERRABORT_SHIFT 0 +#define DRX_ABORT_INT_MASK_MASKINTDRXERRABORT_MASK 0xffffffff + + +/* + * Register + * + * This register contains interrupt status for the EPON module's + * emptyreport transmission. + * Any time the EPON module sends a report upstreamand all the report + * values are zero, the bit corresponding to the LLIDindex will be set. + * These bits are sticky; to clear a bit, write 1 toit. + */ +#define EPN_EMPTY_RPT_INT_STATUS_REG 0xb4 + +/* Time quanta values present in LLID Index 0 report were all zero. */ +#define EMPTY_RPT_INT_STATUS_INTEMPTYRPTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module's emptyreport + * transmission. + * Any time the EPON module sends a report upstreamand all the report + * values are zero, the bit corresponding to the LLIDindex will be set. + */ +#define EPN_EMPTY_RPT_INT_MASK_REG 0xb8 + +/* + * Mask time quanta values present in LLID Index 0 report were all + * zerointerrupt. +*/ +#define EMPTY_RPT_INT_MASK_MASKINTEMPTYRPTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status indicating when the + * L2accumulators exceed their burst-cap values. + * These bits are sticky; toclear a bit, write 1 to it. + */ +#define EPN_BCAP_OVERFLOW_INT_STATUS_REG 0xbc + +/* + * Indicates that the L2 accumulator 0-31 (bitwise) has exceeded itsburst + * cap value. +*/ +#define BCAP_OVERFLOW_INT_STATUS_INTL2SBURSTCAPOVERFLOW_SHIFT 0 +#define BCAP_OVERFLOW_INT_STATUS_INTL2SBURSTCAPOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + * This register contains interrupt mask indicating when the L2accumulators + * exceed their burst-cap values. + */ +#define EPN_BCAP_OVERFLOW_INT_MASK_REG 0xc0 + +/* + * Mask interrupt indicating that the L2 accumulator 0-31 (bitwise) + * hasexceeded its burst cap value. +*/ +#define BCAP_OVERFLOW_INT_MASK_MASKINTL2SBURSTCAPOVERFLOW_SHIFT 0 +#define BCAP_OVERFLOW_INT_MASK_MASKINTL2SBURSTCAPOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define EPN_BBH_DNS_FAULT_INT_STATUS_REG 0xc4 + +/* + * Indicates the downstream BBH interface failed to transfer thedownstream + * fast enough. + * This occurs when the Epn dropped adownstream packet (sent abort). +*/ +#define BBH_DNS_FAULT_INT_STATUS_INTBBHDNSOVERFLOW_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_BBH_DNS_FAULT_INT_MASK_REG 0xc8 + +/* Mask downstream BBH data path overflow interrupt. */ +#define BBH_DNS_FAULT_INT_MASK_MASKINTBBHDNSOVERFLOW_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_BBH_UPS_FAULT_INT_STATUS_REG 0xcc + +/* + * Indicates upstream LLID index 0 has lost coherency with theRunner/BBH. + * This condition can be recovered by resetting the datapath associated + * with the LLID index. + * Note: + * Do not clear these interrupts until the LLID index data pathhas been + * reset or the LLID index's upstream traffic has beendisabled using 'EPN + * Enable Upstream' register. +*/ +#define BBH_UPS_FAULT_INT_STATUS_INTBBHUPSFAULTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + */ +#define EPN_BBH_UPS_FAULT_INT_MASK_REG 0xd0 + +/* + * Mask upstream LLID index 0 has lost coherency with the + * Runner/BBHinterrupt. +*/ +#define BBH_UPS_FAULT_INT_MASK_MASKINTBBHUPSFAULTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + */ +#define EPN_BBH_UPS_ABORT_INT_STATUS_REG 0xd4 + +/* + * [FATAL] This bit indicates that BBH aborted an upstream packet at atime + * it was considered tardy by EPN. + * It is valid only if bit 31 ofregister 0x4b0 (fatalTardyBbhAbortEn) is + * set. + * 0: + * BBH has not aborted a tardy upstream packet. + * 1: + * BBH has aborted a tardy upstream packet. + * All upstream datatraffic has been disabled. + * EPN must be reset to recover from thiscondition. +*/ +#define BBH_UPS_ABORT_INT_STATUS_TARDYBBHABORT_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_BBH_UPS_ABORT_INT_MASK_REG 0xd8 + +/* + * Mask BBH aborted an upstream packet at a time it was consideredtardy by + * EPN interrupt. +*/ +#define BBH_UPS_ABORT_INT_MASK_MASKTARDYBBHABORT_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_MAIN_INT_MASK_REG 0xdc + +#define MAIN_INT_MASK_BBHUPFRABORTMASK_MASK 0x80000000 +#define MAIN_INT_MASK_INTL2SBURSTCAPOVERFLOWMASK_MASK 0x40000000 +#define MAIN_INT_MASK_INTCOEMPTYRPTMASK_MASK 0x20000000 +#define MAIN_INT_MASK_INTDRXERRABORTMASK_MASK 0x10000000 +#define MAIN_INT_MASK_INTL2SFIFOOVERRUNMASK_MASK 0x8000000 +#define MAIN_INT_MASK_INTCO1588TSMASK_MASK 0x4000000 +#define MAIN_INT_MASK_INTCORPTPRESMASK_MASK 0x2000000 +#define MAIN_INT_MASK_INTCOGNTPRESMASK_MASK 0x1000000 +#define MAIN_INT_MASK_INTCODELSTALEGNTMASK_MASK 0x800000 +#define MAIN_INT_MASK_INTCOGNTNONPOLLMASK_MASK 0x400000 +#define MAIN_INT_MASK_INTCOGNTMISALIGNMASK_MASK 0x200000 +#define MAIN_INT_MASK_INTCOGNTTOOFARMASK_MASK 0x100000 +#define MAIN_INT_MASK_INTCOGNTINTERVALMASK_MASK 0x80000 +#define MAIN_INT_MASK_INTCOGNTDISCOVERYMASK_MASK 0x40000 +#define MAIN_INT_MASK_INTCOGNTMISSABORTMASK_MASK 0x20000 +#define MAIN_INT_MASK_INTCOGNTFULLABORTMASK_MASK 0x10000 +#define MAIN_INT_MASK_BADUPFRLENMASK_MASK 0x8000 +#define MAIN_INT_MASK_UPTARDYPACKETMASK_MASK 0x4000 +#define MAIN_INT_MASK_UPRPTFRXMTMASK_MASK 0x2000 +#define MAIN_INT_MASK_INTBIFIFOOVERRUNMASK_MASK 0x1000 +#define MAIN_INT_MASK_BURSTGNTTOOBIGMASK_MASK 0x800 +#define MAIN_INT_MASK_WRGNTTOOBIGMASK_MASK 0x400 +#define MAIN_INT_MASK_RCVGNTTOOBIGMASK_MASK 0x200 +#define MAIN_INT_MASK_DNSTATSOVERRUNMASK_MASK 0x100 +#define MAIN_INT_MASK_INTUPSTATSOVERRUNMASK_MASK 0x80 +#define MAIN_INT_MASK_DNOUTOFORDERMASK_MASK 0x40 +#define MAIN_INT_MASK_TRUANTBBHHALTMASK_MASK 0x20 +#define MAIN_INT_MASK_UPINVLDGNTLENMASK_MASK 0x10 +#define MAIN_INT_MASK_INTCOBBHUPSFAULTMASK_MASK 0x8 +#define MAIN_INT_MASK_DNTIMEINSYNCMASK_MASK 0x4 +#define MAIN_INT_MASK_DNTIMENOTINSYNCMASK_MASK 0x2 +#define MAIN_INT_MASK_DPORTRDYMASK_MASK 0x1 + +/* + * Register + * + * The Maximum Grant Size register sets the threshold for the three + * GrantToo Big interrupts (in the EPN Main Interrupt Status register). + */ +#define EPN_MAX_GNT_SIZE_REG 0xe0 + +/* + * Sets the Grant Size threshold for the three Grant Too Biginterrupts. + * Units are TQ. +*/ +#define MAX_GNT_SIZE_MAXGNTSIZE_SHIFT 0 +#define MAX_GNT_SIZE_MAXGNTSIZE_MASK 0xffff + + +/* + * Register + * + * Provisions the maximum allowable downstream frame size. + * The resetdefault is 1536. + * This register is overridden by the cfgVlanMaxSize bit. + * The maximum allowable value for this register is 2000 in 1G/2G mode + * and10000 in 10G mode. + */ +#define EPN_MAX_FRAME_SIZE_REG 0xe4 + +/* + * Maximum allowable downstream frame size. + * Frames larger than thisvalue are discarded. +*/ +#define MAX_FRAME_SIZE_CFGMAXFRAMESIZE_SHIFT 0 +#define MAX_FRAME_SIZE_CFGMAXFRAMESIZE_MASK 0x3fff + + +/* + * Register + * + * Defines how much of the grant length is consumed by laser on time,laser + * off time, and idle (sync) time. + * This value is subtracted from thegrant length and the remainder is used + * to fill frames from FIF queuesinto the upstream burst. + * This register is used in both 1G and 10Gupstream modes. + * The units are in TQ. + * Reset default is 0. + * NOTE: + * In 10G mode the Xif requires 2 extra TimeQuanta for "Eob". + * Also,in FECless 10G mode the Epn's "Report Byte Length" must have an + * extra16-bytes added to its value to account for 10G "scrambler sync + * time". + */ +#define EPN_GRANT_OVR_HD_REG 0xe8 + +/* + * 1G upstream mode -> Grant length consumed by overhead when FEC + * isenabled. + * 10G upstream mode -> Not used. +*/ +#define GRANT_OVR_HD_GNTOVRHDFEC_SHIFT 16 +#define GRANT_OVR_HD_GNTOVRHDFEC_MASK 0xffff0000 + +/* + * 1G upstream mode -> Grant length consumed by overhead when FEC + * isdisabled. + * 10G upstream mode -> Grant length consumed by overhead. + * Used forboth FEC and FEC-less modes. +*/ +#define GRANT_OVR_HD_GNTOVRHD_SHIFT 0 +#define GRANT_OVR_HD_GNTOVRHD_MASK 0xffff + + +/* + * Register + * + * Sets the size of polling grants for the purpose of generating + * thednGntNonPoll interrupts. + * If a received grant's length, less EPN GrantLength Overhead, is less + * than or equal to the poll size, the grant isconsidered a poll and resets + * the poll grant interval timer for the LLIDIndex. + * Reset default is 64 decimal. + */ +#define EPN_POLL_SIZE_REG 0xec + +/* + * Size of polling grants when FEC is enabled. + * Units are TQ. + * Defaultsto 64. +*/ +#define POLL_SIZE_POLLSIZEFEC_SHIFT 16 +#define POLL_SIZE_POLLSIZEFEC_MASK 0xffff0000 + +/* + * Size of polling grants when FEC is disabled. + * Units are TQ. + * Defaultsto 64. +*/ +#define POLL_SIZE_POLLSIZE_SHIFT 0 +#define POLL_SIZE_POLLSIZE_MASK 0xffff + + +/* + * Register + * + * This register determines how far in advance of the Grant Start Timethat + * grants are considered for removal from the DRX Grant FIFO. + * Once agrant is chosen (the various LLID Indexes compete for the next + * burstslot - the Index with a grant that is within Read Grant Margin + * andclosest to its Grant Start Time wins), it is popped from its grant + * FIFOand held until it meets the Grant Start Time Delta criteria + * (seebelow). + * The units of this register are TQ. + * The reset default value is 256decimal. + */ +#define EPN_DN_RD_GNT_MARGIN_REG 0xf0 + +/* + * How far in advance of Grant Start Time to consider a grant forremoval + * from the grant FIFO. +*/ +#define DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_SHIFT 0 +#define DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_MASK 0xffff + + +/* + * Register + * + * This value determines how far in advance of the Grant Start Time thatthe + * next selected grant (already extracted from the Grant FIFO) will + * behanded to the EPN UTX (upstream transmit) logic and start to + * pre-fetchframes. + * .The units of this register are TQ. + * The reset default value is 640decimal. + */ +#define EPN_GNT_TIME_START_DELTA_REG 0xf4 + +/* + * This value determines how far in advance of the Grant Start Timethat the + * next selected grant (already extracted from the Grant FIFO)will be + * handed to the EPN UTX (upstream transmit) logic and start topre-fetch + * frames. + * .The units of this register are TQ. + * The reset default value is 640decimal. +*/ +#define GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_SHIFT 0 +#define GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_MASK 0xffff + + +/* + * Register + * + * This register sets a threshold for + * LocalTimeInSync/LocalTimeNotSyncinterrupts, and for local time reference + * updates. + * When the differencebetween the EPON MAC's local time and an MPCPDU's + * timestamp exceedsthis value the LocalTimeNotSync interrupt is asserted. + * The units ofthis register are TQ. + * Reset default is 10 decimal. + */ +#define EPN_TIME_STAMP_DIFF_REG 0xf8 + +/* + * Threshold for local time reference updates and related interrupts. + * Reset default is10 decimal. +*/ +#define TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_SHIFT 0 +#define TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_MASK 0xffff + + +/* + * Register + * + * This register helps determine the value for the Timestamp fieldinserted + * into REPORT and Processor frames. + * This value specifies anoffset from the Grant Start Time of the upstream + * burst. + * The valueprogrammed here will be roughly equivalent to the sum of + * Laser-On timeplus IDLE time plus Preamble time. + * The goal is for the Timestampinserted into a frame to match the MPCP + * time at which the first byte ofthe frame's Destination Address is + * transmitted. + */ +#define EPN_UP_TIME_STAMP_OFF_REG 0xfc + +/* + * Offset from Grant Start Time to use as the Timestamp field inREPORTs and + * processor-sent packets when FEC is enabled. + * Only used for 1G modes. + * Units are TQ. +*/ +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSETFEC_SHIFT 16 +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSETFEC_MASK 0xffff0000 + +/* + * Offset from Grant Start Time to use as the Timestamp field inREPORTs and + * processor-sent packets when FEC is disabled. + * Used for both 1G no FEC and all 10G modes. + * Units are TQ. +*/ +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSET_SHIFT 0 +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSET_MASK 0xffff + + +/* + * Register + * + * This register specifies the maximum allowed time between GATE + * messagesreceived on an LLID. + * If the time elapsed is greater than the specifiedvalue, the Gate + * Interval interrupt asserts for that LLID Index. + * Theunits of this register are 262 us. + * The maximum interval is ~17 seconds. + */ +#define EPN_GNT_INTERVAL_REG 0x100 + +/* Grant interval */ +#define GNT_INTERVAL_GNTINTERVAL_SHIFT 0 +#define GNT_INTERVAL_GNTINTERVAL_MASK 0xffff + + +/* + * Register + * + * Sets the threshold for misalignment detection and handling. + * A grant misalignment condition is detected by the ONU whenever a grantto + * the ONU cannot be used efficiently (due to the grant size notaligning to + * even frame boundaries). + * When cfgGntMisalignX bits are set, the ONU uses this register + * todetermine a misalignment condition and to take corrective action. + * prvUnusedGntThresh determines how many unused TQ there must be in agiven + * grant in order for it to be considered misaligned. + * gntMisalignThresh indicates how many consecutive misaligned grants + * mustbe received in order to trigger handling of this condition. + * The ONU handles the misaligned condition by temporarily reporting 0("no + * data") in that LLID's REPORT frames. + */ +#define EPN_DN_GNT_MISALIGN_THR_REG 0x104 + +/* + * Sets the minimum number of unused time quanta in a grant required + * inorder for it to be considered misaligned. +*/ +#define DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_SHIFT 16 +#define DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_MASK 0xffff0000 + +/* + * Sets the number of misaligned grants needed to trigger + * misalignmenthandling. + * The value set here is one fewer than the desired number ofconsecutive + * misaligned grants, i. + * e. + * setting a value of 2 means thatthree misaligned grants in a row will + * trigger misalignment handling. +*/ +#define DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_SHIFT 0 +#define DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_MASK 0x3ff + + +/* + * Register + * + * Indicates for how long after the misalignment condition is detectedthat + * the LLID Index's reporting will be "paused". + * This is achievedthrough reporting queue report values of zero. + * Units are 1 us. + */ +#define EPN_DN_GNT_MISALIGN_PAUSE_REG 0x108 + +/* How long to stall reporting of queue status. */ +#define DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_SHIFT 0 +#define DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_MASK 0xffff + + +/* + * Register + * + * Defines the amount of time required for triggering the non poll + * grantinterrupts. + */ +#define EPN_NON_POLL_INTV_REG 0x10c + +/* + * If amount of time since last non poll grant exceed this value, + * therespective LLID's interrupt will assert. + * Units of 65 us. +*/ +#define NON_POLL_INTV_NONPOLLGNTINTV_SHIFT 0 +#define NON_POLL_INTV_NONPOLLGNTINTV_MASK 0xffff + + +/* + * Register + * + * Forces upstream FCS errors on the selected LLID(s). + */ +#define EPN_FORCE_FCS_ERR_REG 0x110 + +/* Force bad FCS for frames transmitting out of LLID 0 */ +#define FORCE_FCS_ERR_FORCEFCSERRx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * Defines how much overlap is allowed between consecutive grants to + * thesame ONU. + * Effectively this register defines how much of the grantoverhead the Epn + * should attempt to recover when processing overlappedgrants. + * Normally this register is provisioned with the same value as inthe EPN + * Grant Overhead Length register. + * However, if the Xif or Lifrequire extra overhead not associated with + * Lon/Sync/Loff, then thisregister value must be smaller than the EPN + * Grant Overhead Lengthregister value. + * This register is used in both 1G and 10G upstream modes. + * The units arein TQ. + * Reset default is 0. + * NOTE: + * In 10G upstream mode this register must be provisioned to matchthe value + * written to the XIF Overlapping Grant Overhead register(0x0364). + * The proper value is calculated as: + * EPN Grant Overlap Limit = Lon + Sync Time + Loff - 1 (start of burst) -1 + * (Idle Sync) - 3 (XIF Overlapping Grant Overhead). + */ +#define EPN_GRANT_OVERLAP_LIMIT_REG 0x114 + +/* + * Number of time quanta by which two consecutive grants are allowed + * tooverlap +*/ +#define GRANT_OVERLAP_LIMIT_PRVGRANTOVERLAPLIMIT_SHIFT 0 +#define GRANT_OVERLAP_LIMIT_PRVGRANTOVERLAPLIMIT_MASK 0xffff + + +/* + * Register + * + * Allows control over reporting the extra per-packet overhead + * associatedwith 802. + * 1AE encryption. + * The AES overhead compensation logic supportstwo overhead modes: + * implicit SCI and explicit SCI. + * The implicit SCImode increases the per-packet overhead by 24 bytes. + * Explicit SCI modeincreases the per-packet overhead by 32 bytes. + */ +#define EPN_AES_CFG_0_REG 0x118 + +/* + * LLID index 0 AES overhead mode. + * 0: + * Implicit SCI AES overhead mode. + * 1: + * Explicit SCI AES overhead mode. + * .. + * LLID index 15 AES overhead mode. + * 30: + * Implicit SCI AES overhead mode. + * 31: + * Explicit SCI AES overhead mode. +*/ +#define AES_CFG_0_PRVUPSTREAMAESMODE_0_SHIFT 0 +#define AES_CFG_0_PRVUPSTREAMAESMODE_0_MASK 0xffffffff + + +/* + * Register + * + * The amount of overhead used in discovery gates. + */ +#define EPN_DISC_GRANT_OVR_HD_REG 0x11c + +/* + * This defines the amount of overhead used for Discovery gates. + * Unitsare 16-bit words. +*/ +#define DISC_GRANT_OVR_HD_DISCGNTOVRHD_SHIFT 0 +#define DISC_GRANT_OVR_HD_DISCGNTOVRHD_MASK 0xffff + + +/* + * Register + * + * Serves as the seed for generating the random offset during + * discoverygates. + * When this register is written the discovery random offset becomethis + * value + */ +#define EPN_DN_DISCOVERY_SEED_REG 0x120 + +/* + * Specifies basis for generating the discovery offset. + * Units are TQ. +*/ +#define DN_DISCOVERY_SEED_CFGDISCSEED_SHIFT 0 +#define DN_DISCOVERY_SEED_CFGDISCSEED_MASK 0xfff + + +/* + * Register + * + * Sets the amount by which the discovery random offset is incremented. + */ +#define EPN_DN_DISCOVERY_INC_REG 0x124 + +/* Units are TQ */ +#define DN_DISCOVERY_INC_CFGDISCINC_SHIFT 0 +#define DN_DISCOVERY_INC_CFGDISCINC_MASK 0x3ff + + +/* + * Register + * + * Size of the grant for responses to Discovery Gates. + * When a DiscoveryGate is received from the PON, EPN substitutes this + * value into thegrant length as the grant goes into the Grant FIFO. + * Normally, the valueset in this register will be 42 greater than what is + * set in EPNDiscovery Gate Overhead. + */ +#define EPN_DN_DISCOVERY_SIZE_REG 0x128 + +/* + * Size of response to discovery gate. + * Units are TQ. +*/ +#define DN_DISCOVERY_SIZE_CFGDISCSIZE_SHIFT 0 +#define DN_DISCOVERY_SIZE_CFGDISCSIZE_MASK 0xffff + + +/* + * Register + * + * Specifies the IPG and REPORT frame sizes used in computating + * reportedvalues. + * cfgRptLen and cfgFecRptLen are also used to qualify grantlengths and + * generate the intInvGntLength interrupt. + * Note the operating modes in which each of these fields is used: + * cfgFecIpgLength - Used only in 1G upstream FEC. + * Note 8-bytes ofoverhead are built in to the Epn's 1G upstream FEC + * calculations. + * cfgFecRptLen - Used only in 1G upstream, for LLIDs which areFEC-enabled. + * cfgRptLen - Used in 1G upstream for non-FEC LLIDs. + * Also used in 10Gupstream, whether or not FEC is enabled (FEC is global + * at 10Gupstream). + */ +#define EPN_FEC_IPG_LENGTH_REG 0x12c + +/* + * 10G and 1G upstream: + * The number of the bytes in the sum of IPG +PREAMBLE. + * This value must be programmed before the upstream isenabled. + * It must not be modified while the upstream is active. + * Default is 20. + * Units are bytes. +*/ +#define FEC_IPG_LENGTH_MODIPGPREAMBLEBYTES_SHIFT 24 +#define FEC_IPG_LENGTH_MODIPGPREAMBLEBYTES_MASK 0x1f000000 + +/* + * 1G upstream non-FEC: + * The length of the REPORT Frame + IPG +PREAMBLE. + * Used for non-FEC LLIDs. + * Use default value of 42. + * 10G upstream FEC : + * The length of the Report Frame + IPG + PREAMBLE +FEC. + * Set to 13. + * 10G upstream non-FEC : + * The length of the Report Frame + IPG +PREAMBLE. + * Set to 5. + * Defaults to 42 for 1G non-FEC. + * Units are TQ. +*/ +#define FEC_IPG_LENGTH_CFGRPTLEN_SHIFT 16 +#define FEC_IPG_LENGTH_CFGRPTLEN_MASK 0xff0000 + +/* + * The length of the REPORT Frame + IPG + PREAMBLE + FEC. + * Used only for1G FEC upstream operation. + * Default is 58 for 1G upstream FEC. + * Units are TQ. +*/ +#define FEC_IPG_LENGTH_CFGFECRPTLENGTH_SHIFT 8 +#define FEC_IPG_LENGTH_CFGFECRPTLENGTH_MASK 0xff00 + +/* + * Length of IPG to be used in 1G upstream FEC computations. + * There are8-bytes of overhead built into the Epn's 1G upstream + * FECcalculations. + * This means that if this register is set to zero then the Epn willadd + * 8-bytes of overhead to each packet transmitted upstream. + * The size of the 1G upstream FEC IPG+preamble used by the Epn + * is(cfgFecIpgLength + 8). + * The smallest supported FEC IPG+preamble value is 8. + * To use theLIF's short preamble (7-byte minimum) capability; set the + * LIF's IPGvalue to 1 and set the Epn's cfgFecIpgLength to 0. + * Default 10. + * Units are bytes. +*/ +#define FEC_IPG_LENGTH_CFGFECIPGLENGTH_SHIFT 0 +#define FEC_IPG_LENGTH_CFGFECIPGLENGTH_MASK 0xff + + +/* + * Register + * + * Enables a mode in which an LLID Index falsely reports that it has + * data,even when it does not. + * This mode is enabled per-LLID Index. + * Enablingthis mode for an LLID Index causes it to report the value set in + * EPNFake Report Value, regardless of any actual data that is in + * itsassociated queue(s). + */ +#define EPN_FAKE_REPORT_VALUE_EN_REG 0x130 + +/* + * Per-LLID Index bits for enabling fake reporting. + * Setting a bit willcause that Index to send fake reports (when requested + * by a ForceReport grant) with the value specified in EPN Fake Report + * Value. +*/ +#define FAKE_REPORT_VALUE_EN_FAKEREPORTVALUEEN_SHIFT 0 +#define FAKE_REPORT_VALUE_EN_FAKEREPORTVALUEEN_MASK 0xffffffff + + +/* + * Register + * + * Specifies the value sent in fake reports. + */ +#define EPN_FAKE_REPORT_VALUE_REG 0x134 + +/* + * The value to be used when sending fake reports. + * This value is inunits of bytes. + * (This value is converted to TQ as necessary for theconfigured upstream + * data rate. + * ) +*/ +#define FAKE_REPORT_VALUE_FAKEREPORTVALUE_SHIFT 0 +#define FAKE_REPORT_VALUE_FAKEREPORTVALUE_MASK 0x1fffff + + +/* + * Register + * + * Specifies which of the first 16 MPCP opcode values should have theirMPCP + * time overwritten. + * Opcode values 0 and 1 are always disabled. + * The14 MPCP opcode values in the range of 2-15 can be enabled by + * settingthe corresponding bit. + * The reset default value is 0x0058. + */ +#define EPN_VALID_OPCODE_MAP_REG 0x178 + +/* + * The 14 MPCP opcode values in the range of 2-15 can be enabled bysetting + * the corresponding bit. + * Note: + * Opcode values 0 and 1 must always be disabled! +*/ +#define VALID_OPCODE_MAP_PRVVALIDMPCPOPCODES_SHIFT 0 +#define VALID_OPCODE_MAP_PRVVALIDMPCPOPCODES_MASK 0xffff + + +/* + * Register + * + * Specifies the setup time margin for upstream data transfers to LIF. + * This margin is used to police the arrival time of data from + * theRunner/BBH upstream data path. + * If BBH fails to deliver (any part of) apacket in time, EPON inserts a + * "fake packet" into the upstream burst tosubstitute for the + * late-delivered packet. + * When the actual packet iseventually delivered from BBH, EPON discards + * it. + * Fake packets arezero-padded and contain a guaranteed-bad FCS. + * The upPacketTxMargin value needs to be larger than the upstream datapath + * latency. + * The upstream data path latency is composed of LIF datapath delay + MPCP + * time jitter + EPN data path delay (upTimeStampOff +42 + 1 + 10). + * Please note that EPN's 10 TQ upstream data path latencyincludes 3 TQ for + * the LIF to respond to valid data on the upstreamEPN-to-LIF interface, + * and LIF's upstream data path latency includes theprovisioned + * upTimeStampOff value. + * This is because the LIF does notprocess a grant until it receives data + * from the EPN. + * So, the initialpacket data must arrive 42 time quanta before the Grant + * Start Time. + */ +#define EPN_UP_PACKET_TX_MARGIN_REG 0x17c + +/* + * Minimum upstream data setup time for LIF/XIF. + * Units are TQ. +*/ +#define UP_PACKET_TX_MARGIN_UPPACKETTXMARGIN_SHIFT 0 +#define UP_PACKET_TX_MARGIN_UPPACKETTXMARGIN_MASK 0xffff + + +/* + * Register + * + * This register configures Multi-Priority reporting for all LLID indices + */ +#define EPN_MULTI_PRI_CFG_0_REG 0x180 + +/* + * Enables deficit accounting in the CTC scheduler. + * Applies only whenthe CTC scheduler is configured for weighted + * round-robin operation. +*/ +#define MULTI_PRI_CFG_0_CFGCTCSCHDEFICITEN_MASK 0x1000 + +/* + * Determines an internal burst cap value for any priority/L2 which hasits + * burst cap set to zero. + * The internal burst cap value is used bythe L1-to-L2 packet transfer + * logic. + * 0: + * Use an internal burst cap value of zero. + * (Do not use. + * )1: + * Use an internal burst cap value of 2 KB. + * Reset default. + * 2: + * Use a "max value" internal burst cap: + * 128KB for 1G upstream. + * 3. + * Reserved (do not use) +*/ +#define MULTI_PRI_CFG_0_PRVZEROBURSTCAPOVERRIDEMODE_SHIFT 8 +#define MULTI_PRI_CFG_0_PRVZEROBURSTCAPOVERRIDEMODE_MASK 0x300 + +/* + * For the burst-cap limited queue set, configures whether each + * queuereport/priority uses a separate L2 queue, or a shared one. + * Settingthis bit, along with cfgSharedBurstCap, configures EPN into + * aTK3715-compatible reporting mode. + * Note: + * Using a shared L2 queue effectively disables the CTC outputscheduler, + * since packets from all priorities are merged into asingle pipe and + * scheduled (in strict priority) upon entry to the L2queue. + * 0: + * Each priority level uses its own dedicated L2 queue. + * 1: + * All priority levels use a single, shared L2 queue +*/ +#define MULTI_PRI_CFG_0_CFGSHAREDL2_MASK 0x40 + +/* + * For the burst-cap limited queue set, configures whether each + * queuereport/priority is individually limited to the Burst Cap, or + * whetherthe sum of all queue report values is limited to the Burst Cap. + * 0: + * Limit each queue report value to a Burst Cap. + * Each queuereport/priority uses the Burst Cap corresponding to its L2 + * FIFO. + * This bit has effect only when cfgRptMultiPri is 1. + * Note: + * Setting this bit, along with cfgSharedL2, configures EPN intoa + * TK3715-compatible reporting mode. + * 1: + * Limit the sum of the queue reports/priorities to the Burst Capvalue. + * (Use the Burst Cap value corresponding to the lowest L2 FIFOassigned to + * the LLID index). + * Note: + * The following offsets must be included in the burst cap valuecalculation + * when "shared burst cap mode" is enabled. + * Decrease thedesired burst cap value by 21 bytes in 1G non-FEC mode, 193 + * bytes in1G FEC mode. +*/ +#define MULTI_PRI_CFG_0_CFGSHAREDBURSTCAP_MASK 0x20 + +/* + * Configures whether Multi-Priority REPORT frames includealready-granted + * frames. + * 0: + * Report frames do NOT include frames that have already beengranted. + * This is the setting for NTT operation. + * 1: + * Report frames DO include frames that have already been granted(but not + * yet sent upstream). + * This bit has effect only when cfgRptMultiPri is 1. +*/ +#define MULTI_PRI_CFG_0_CFGRPTGNTSOUTST0_MASK 0x10 + +/* + * Determines the order within a queue set in which priorities arereported + * on. + * 0: + * Priorities are reported low to high. + * 1: + * Priorities are reported high to low. + * This bit has effect only when cfgRptMultiPri0 is 1. +*/ +#define MULTI_PRI_CFG_0_CFGRPTHIPRIFIRST0_MASK 0x8 + +/* + * Configure order of queue sets. + * 0: + * The first queue set reports the full packet buffer queue depths;the + * second queue set reports up to the T/Burst Cap 0 threshold. + * 1: + * Swap queue sets in Multi-Priority REPORT frames. + * The first Queueset reports up to the T/Burst Cap 0 threshold; the second + * queue setreports the the full packet buffer queue depths. + * This bit has effect only when cfgRptMultiPri0 is 1. +*/ +#define MULTI_PRI_CFG_0_CFGRPTSWAPQS0_MASK 0x4 + +/* + * Configure Multi-Priority mode. + * 0: + * Disable Multi-Priority mode. + * The reporting style is selected byReport Select bit (bit 8 in the EPON + * Control 0 register). + * 1: + * Configured for Multi-Priority reporting mode. +*/ +#define MULTI_PRI_CFG_0_CFGRPTMULTIPRI0_MASK 0x1 + + +/* + * Register - read-only + * + */ +#define EPN_SHARED_BCAP_OVRFLOW_REG 0x184 + +#define SHARED_BCAP_OVRFLOW_SHAREDBURSTCAPOVERFLOW_SHIFT 0 +#define SHARED_BCAP_OVRFLOW_SHAREDBURSTCAPOVERFLOW_MASK 0x7ff + +/* + * Register + * + * Option to force an upstream report for an LLID Index that has + * notreceived an upstream grant with the "force report" bit set in more + * than50 mS. + * This mode is enabled per-LLID Index. + * Discovery gates will nothave their "force report" bits set. + * This bit should not be enabledunless the LLID index is registered with + * the OLT. + */ +#define EPN_FORCED_REPORT_EN_REG 0x188 + +/* + * Per-LLID Index bits for enabling forced reporting. + * Setting a bitwill cause that Index to send a report as part of the first + * upstreamburst that occurs more than the number of mS provisioned + * incfgMaxReportInterval" after the last report was sent. +*/ +#define FORCED_REPORT_EN_CFGFORCEREPORTEN_SHIFT 0 +#define FORCED_REPORT_EN_CFGFORCEREPORTEN_MASK 0xffffffff + + +/* + * Register + * + * Option to force an upstream report for an LLID Index that has + * notreceived an upstream grant with the "force report" bit set in more + * than50 mS. + * This mode is enabled per-LLID Index. + * Discovery gates will nothave their "force report" bits set. + * This bit should not be enabledunless the LLID index is registered with + * the OLT. + */ +#define EPN_FORCED_REPORT_MAX_INTERVAL_REG 0x18c + +/* The number of mS after the last report was sent to force the report. */ +#define FORCED_REPORT_MAX_INTERVAL_CFGMAXREPORTINTERVAL_SHIFT 0 +#define FORCED_REPORT_MAX_INTERVAL_CFGMAXREPORTINTERVAL_MASK 0x3f + + +/* + * Register + * + * Provides a mechanism to flush an L2 queue. + * The associated LLID indexmust be upstream disabled (including waiting + * for the upstream LLIDindex enable feedback confirmation) before starting + * the flushmechanism. + * Once an LLID index has been disabled, the L2 queues thatcomprise it may + * be flushed one at a time via this register. + * A flush isstarted by writing the cfgFlushL2sSel field and setting + * thecfgFlushL2sEn bit. + * The flushL2sDone bit will be set by the hardwarewhen the selected L2 + * queue has been flushed. + * Note: + * Do not change thecfgFlushL2sSel value unless both "flushL2sDone" and + * "cfgFlushL2sEn" arelow. + */ +#define EPN_L2S_FLUSH_CONFIG_REG 0x190 + +/* + * Enables the selected L2 queue to be flushed. + * This configuration bitmust be forced low and "flushL2sDone" must be read + * back as low;before, "cfgFlushL2sSel" is written. + * 0: + * L2 queue flush is disabled1: + * L2 queue flush is enabled +*/ +#define L2S_FLUSH_CONFIG_CFGFLUSHL2SEN_MASK 0x80000000 + +/* + * This bit is set when the selected L2 queue has no more packets toflush. + * This bit will always be zero when the enable bit is zero. +*/ +#define L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK 0x40000000 + +/* + * Selects the L2 queue that will be flushed when the enable is set. + * Do not write this register unless both "flushL2sDone" andcfgFlushL2sEn" + * are low. +*/ +#define L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_SHIFT 0 +#define L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_MASK 0x1f + + +/* + * Register + * + * This set of registers allows processor access to RAMs controlled by + * themodules in the EPON block. + * Data Port Control indicates whether a reador write access is occurring. + * Data Port Select indicates which RAM isbeing accessed. + * Writing to the Data Port Command register (offset 0)initiates the memory + * access. + * The processor may only access the Downstream Statistics RAM andUpstream + * Statistics RAM during run time. + * Accessing the L2 queue RAM maycause the EPON to fail in an unknown and + * random way. + * The flow for a write operation is as follows. + * 1. + * Check if the Data Port Interrupt is ready. + * 2. + * Update the Data Port Address register. + * 3. + * Update the Data Port Data register4. + * Update the Data Port Command register. + * Write a "1" to the DataPort Control and the RAM's index into the Data + * Port Select. + * 5. + * The operation is completed when the Data Port Interrupt isready again. + * The flow for a read operation is as follows. + * 1. + * Check if the Data Port Interrupt is ready. + * 2. + * Update the Data Port Address register. + * 3. + * Update the Data Port Command register. + * Write a "0" to the DataPort Control and the RAM's index into the Data + * Port Select. + * 4. + * Check to see if the Data Port Interrupt is read. + * 5. + * Read the Data Port Data register to get the operation'sresults. + * RAM Name RAM Size AutoInit?Downstream Statistics 672 x 32 YesUpstream + * Statistics 1088 x 32 YesL2 Queue RAM 16384 x 22 NoThe Downstream + * Statistics RAMs accumulate statistics for 32 LLIDs. + * EachLLID occupies 21 RAM offsets. + * Downstream Statistics RAM definition areas follows : + * LLID Index RAM Locations0 0 - 201 21 - 412 42 - 62. + * .n (up to 32) (n*21) - (n*21)+20RAM Offset Description0 Total bytes + * received1 FCS Errors2 OAM frames received3 GATE frames received4 64 byte + * frames received5 65 - 127 byte frames received6 128 - 255 byte frames + * received7 256 - 511 byte frames received8 512 - 1023 byte frames + * received9 1024 - 1518 byte frames received10 1519 - 2047 byte frames + * received11 2048 - 4095 byte frames received12 4096 - 9216 byte frames + * received13 Greater than 9216 byte frames received14 Oversized frames + * received15 Broadcast frames received16 Multicast frames received17 + * Unicast frames received18 Undersized frames received19 OAM bytes + * received20 Register frames receivedThe Upstream Statistics RAMs + * accumulate statistics for 32 LLIDs. + * EachLLID occupies 17 RAM offsets. + * It is logically divided into 64segments. + * The lower 32 segments contain the normal upstream statisticsfor each of + * the 32 LLID Indexes. + * The upper 32 segments are used toreport the "fake packet" statistics. + * Fake packets are inserted intoupstream bursts to substitute for packets + * that are delivered late fromthe Runner/BBH subsystem. + * Fake packets are zero-padded and contain aguaranteed-bad FCS. + * Note that a faked packet can cause broadcast andmulticast packets to be + * reported as unicast packets, depending onwhether the Runner/BBH upstream + * data delivery failure occurred beforethe DA data was delivered. + * LLID Index RAM Locations0 0 - 161 17 - 332 34 - 50. + * .n (up to 32) (n*17) - (n*17)+16Fake packet 0 544 - 560Fake packet 1 561 + * - 577Fake packet 2 578 - 594. + * .Fake packet n [544+(n*17)] - [544+(n*17)+16]RAM Offset Description0 + * Total bytes sent1 OAM frames sent2 REPORT frames sent3 64 byte frames + * sent4 65 - 127 byte frames sent5 128 - 255 byte frames sent6 256 - 511 + * byte frames sent7 512 - 1023 byte frames sent8 1024 - 1518 byte frames + * sent9 1519 - 2047 byte frames sent10 2048 - 4095 byte frames sent11 4096 + * - 9216 byte frames sent12 Greater than 9216 byte frames sent13 OAM bytes + * sent14 Broadcast frames sent15 Multicast frames sent16 Unicast frames + * sentNotes: + * Total bytes sent do not include OAM or Report frames. + * The various frame "bucket" statistics do not include OAM or + * Reportframes. + * Oversized frames are frames that are greater than the value specifiedby + * the EPON Max Frame Size register. + * The exception is when cfgVlanMaxmode is used. + * In this case an oversized condition occurs when a frameis greater than + * 1522 byte when a VLAN tag is present, otherwise greaterthan 1518 bytesAn + * undersized frame condition occurs when the received frame is lessthan 64 + * bytes in length and has a valid FCS. + * The Unused Words counts the number of words that in a grant that theLLID + * was not able to send upstream traffic on. + * If the LLID received agrant for 2K words, but it has only 1K words of + * data, the unused wordcount will increase by 1 K. + * In most cases this condition should nothappen. + * It indicates that the OLT is granting inefficiently. + * Therecould be a problem with the ONU's EPON overhead setting + * beingincorrect. + */ +#define EPN_DATA_PORT_COMMAND_REG 0x194 + +/* + * Indicates access to RAM is in progress. + * 0: + * Data port is ready to accept a command1: + * Data port is busy +*/ +#define DATA_PORT_COMMAND_DPORTBUSY_MASK 0x80000000 + +/* + * Selects RAM to be access0: + * Downstream statistics RAM1: + * Upstream statistics RAM2: + * Reserved3: + * L2 Queue RAM4-31: + * Reserved +*/ +#define DATA_PORT_COMMAND_DPORTSELECT_SHIFT 4 +#define DATA_PORT_COMMAND_DPORTSELECT_MASK 0x1f0 + +/* + * Indicates data port operation0: + * Do a RAM read operation1: + * Do a RAM write operation +*/ +#define DATA_PORT_COMMAND_DPORTCONTROL_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_DATA_PORT_ADDR_REG 0x198 + +/* Address for RAM accesses. */ +#define DATA_PORT_ADDR_DPORTADDR_SHIFT 0 +#define DATA_PORT_ADDR_DPORTADDR_MASK 0x3fff + + +/* + * Register + * + */ +#define EPN_DATA_PORT_DATA_0_REG 0x19c + +/* Low-order data dword for data port accesses */ +#define DATA_PORT_DATA_0_DPORTDATA0_SHIFT 0 +#define DATA_PORT_DATA_0_DPORTDATA0_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_BIG_CNT_REG 0x1a0 + +/* Counts illegally large frames. */ +#define UNMAP_BIG_CNT_UNMAPBIGERRCNT_SHIFT 0 +#define UNMAP_BIG_CNT_UNMAPBIGERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_FRAME_CNT_REG 0x1a4 + +/* Counts valid frames that are not Gates or OAM frames. */ +#define UNMAP_FRAME_CNT_UNMAPFRCNT_SHIFT 0 +#define UNMAP_FRAME_CNT_UNMAPFRCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_FCS_CNT_REG 0x1a8 + +/* Counts frame with FCS errors. */ +#define UNMAP_FCS_CNT_UNMAPFCSERRCNT_SHIFT 0 +#define UNMAP_FCS_CNT_UNMAPFCSERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_GATE_CNT_REG 0x1ac + +/* Counts un-mapped gate frames. */ +#define UNMAP_GATE_CNT_UNMAPGATECNT_SHIFT 0 +#define UNMAP_GATE_CNT_UNMAPGATECNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_OAM_CNT_REG 0x1b0 + +/* Counts un-mapped OAM frames. */ +#define UNMAP_OAM_CNT_UNMAPOAMCNT_SHIFT 0 +#define UNMAP_OAM_CNT_UNMAPOAMCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_SMALL_CNT_REG 0x1b4 + +/* Counts illegally small frames. */ +#define UNMAP_SMALL_CNT_UNMAPSMALLERRCNT_SHIFT 0 +#define UNMAP_SMALL_CNT_UNMAPSMALLERRCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define EPN_FIF_DEQUEUE_EVENT_CNT_REG 0x1b8 + +/* Debug only! */ +#define FIF_DEQUEUE_EVENT_CNT_FIFDEQUEUEEVENTCNT_SHIFT 0 +#define FIF_DEQUEUE_EVENT_CNT_FIFDEQUEUEEVENTCNT_MASK 0xffffffff + + +/* + * Register + * + * Per-LLID index Runner/BBH upstream fault halt enable. + * This allows thedefault fatal upstream fault halt behavior to be + * disabled. + * The resetdefault value is enabled (all ones). + * This register should only be usedfor debug. + * All the bits in this register must be set during normaloperation. + */ +#define EPN_BBH_UP_FAULT_HALT_EN_REG 0x1dc + +/* + * Per-LLID Index Runner/BBH upstream fault halt enable. + * 0: + * Do not disable upstream data traffic. + * 1: + * Disable upstream data traffic for LLID indexes the Runner/BBHfaulted on. +*/ +#define BBH_UP_FAULT_HALT_EN_BBHUPSFAULTHALTEN_SHIFT 0 +#define BBH_UP_FAULT_HALT_EN_BBHUPSFAULTHALTEN_MASK 0xffffffff + + +/* + * Register + * + * Per-LLID index Runner/BBH upstream fault halt enable. + * This allows thedefault fatal upstream fault halt behavior to be + * disabled. + * The resetdefault value is enabled (all ones). + * This register should only be usedfor debug. + * All the bits in this register must be set during normaloperation. + */ +#define EPN_BBH_UP_TARDY_HALT_EN_REG 0x1e0 + +/* + * Disable all upstream data traffic when the BHH aborts a tardypacket. + * 0: + * Do not disable upstream data traffic on tardy/abort1: + * Disable all upstream data traffic when the BBH aborts a tardypacket. +*/ +#define BBH_UP_TARDY_HALT_EN_FATALTARDYBBHABORTEN_MASK 0x1 + + +/* + * Register - read-only + * + * This register contains the real time status bits to aid debugging theEPN + * module. + */ +#define EPN_DEBUG_STATUS_0_REG 0x1e4 + +/* Indicates which LLID's report FIFO is full */ +#define DEBUG_STATUS_0_L2SQUEFULLDEBUG_SHIFT 8 +#define DEBUG_STATUS_0_L2SQUEFULLDEBUG_MASK 0xff00 + +#define DEBUG_STATUS_0_DNDLUFULL_MASK 0x10 +/* SEC and EPN downstream */ +#define DEBUG_STATUS_0_DNSECFULL_MASK 0x8 + +/* SEC and EPN upstream interface FIFO is full */ +#define DEBUG_STATUS_0_EPNLIFFIFOFULL_MASK 0x4 + + +/* + * Register - read-only + * + * This register contains the real time status bits to aid debugging theEPN + * module. + */ +#define EPN_DEBUG_STATUS_1_REG 0x1e8 + +/* LLID Index 0 has grant(s) pending */ +#define DEBUG_STATUS_1_GNTRDYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + */ +#define EPN_DEBUG_L2S_PTR_SEL_REG 0x1ec + +#define DEBUG_L2S_PTR_SEL_CFGL2SDEBUGPTRSEL_SHIFT 16 +#define DEBUG_L2S_PTR_SEL_CFGL2SDEBUGPTRSEL_MASK 0x70000 +#define DEBUG_L2S_PTR_SEL_L2SDEBUGPTRSTATE_SHIFT 0 +#define DEBUG_L2S_PTR_SEL_L2SDEBUGPTRSTATE_MASK 0x7fff + +/* + * Register + * + * This register stores a MAC address for the OLT. + * This address isinserted as the DA in REPORT frames sent upstream. + */ +#define EPN_OLT_MAC_ADDR_LO_REG 0x230 + +/* OLT MAC Address */ +#define OLT_MAC_ADDR_LO_OLTADDRLO_SHIFT 0 +#define OLT_MAC_ADDR_LO_OLTADDRLO_MASK 0xffffffff + + +/* + * Register + * + * This register stores a MAC address for the OLT. + * This address isinserted as the DA in REPORT frames sent upstream. + */ +#define EPN_OLT_MAC_ADDR_HI_REG 0x234 + +/* OLT MAC Address */ +#define OLT_MAC_ADDR_HI_OLTADDRHI_SHIFT 0 +#define OLT_MAC_ADDR_HI_OLTADDRHI_MASK 0xffff + + +/* + * Register - read-only + * + * Indicates empty status of L1 shaped queues + */ +#define EPN_TX_L1S_SHP_DQU_EMPTY_REG 0x278 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L1 accumulator is not empty1: + * L1 accumulator is empty +*/ +#define TX_L1S_SHP_DQU_EMPTY_L1SDQUQUEEMPTY_SHIFT 0 +#define TX_L1S_SHP_DQU_EMPTY_L1SDQUQUEEMPTY_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates status of L1 unshaped-empty accumulators + */ +#define EPN_TX_L1S_UNSHAPED_EMPTY_REG 0x27c + +/* + * Each bit in this register contains the status of the + * respectiveaccumulators0: + * L1 unshaped accumulator is not empty1: + * L1 unshaped accumulator is empty +*/ +#define TX_L1S_UNSHAPED_EMPTY_L1SUNSHAPEDQUEEMPTY_SHIFT 0 +#define TX_L1S_UNSHAPED_EMPTY_L1SUNSHAPEDQUEEMPTY_MASK 0xffffffff + + +/* + * Register - read-only + * + * L2 queue empty status + */ +#define EPN_TX_L2S_QUE_EMPTY_REG 0x2c0 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L2 queue is not empty1: + * L2 queue is empty +*/ +#define TX_L2S_QUE_EMPTY_L2SQUEEMPTY_SHIFT 0 +#define TX_L2S_QUE_EMPTY_L2SQUEEMPTY_MASK 0xffffffff + + +/* + * Register - read-only + * + * L2 queue full status + */ +#define EPN_TX_L2S_QUE_FULL_REG 0x2c4 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L2 queue is not full1: + * L2 queue is full +*/ +#define TX_L2S_QUE_FULL_L2SQUEFULL_SHIFT 0 +#define TX_L2S_QUE_FULL_L2SQUEFULL_MASK 0xffffffff + + +/* + * Register - read-only + * + * L2 queue stopped status + */ +#define EPN_TX_L2S_QUE_STOPPED_REG 0x2c8 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L2 queue is not stopped1: + * L2 queue is stopped +*/ +#define TX_L2S_QUE_STOPPED_L2SSTOPPEDQUEUES_SHIFT 0 +#define TX_L2S_QUE_STOPPED_L2SSTOPPEDQUEUES_MASK 0xffffffff + + +/* + * Register + * + * Everytime the BBH fails to deliver a packet in time to be + * transmittedupstreamit is placed in failed state and the Epn increments a + * tardy packetcounter. + * Every time the BBH delivers a packetwhile it is in the failed state the + * tardy packet counter isdecremented. + * The BBH will be taken out of thefailed state when the tardy packet + * counter reaches 0. + * If the tardypacket countervalue exceeds the value of this register; then + * the BBH becomes truantand the Epn stops upstream traffic untilthe Epn is + * reset. + * It is expected the BBH, runner and Epn will be resetat the same time. + */ +#define EPN_BBH_MAX_OUTSTANDING_TARDY_PACKETS_REG 0x2ec + +/* + * Maximum number of packets outstanding tardy packet the BBH canaccumulate + * at one time. +*/ +#define BBH_MAX_OUTSTANDING_TARDY_PACKETS_CFGMAXOUTSTANDINGTARDYPACKETS_SHIFT 0 +#define BBH_MAX_OUTSTANDING_TARDY_PACKETS_CFGMAXOUTSTANDINGTARDYPACKETS_MASK 0x3ff + + +/* + * Register + * + * The Virtual Thresholds are determined from the smaller of the queue + * setshaper and the accumulated queue length. + * The Virtual Thresholds mustalso prevent pathological values from being + * reported. + * The reportedvalue should be at least one maximum frame length greater + * than theprevious queue set threshold or else it will be reported as + * zero. + * Thisprevents a head of line blocking issue if a large frame is at the + * headof the queue and also prevents from reporting illegally short + * grantlengths. + * Everytime the BBH fails to deliver a packet in time to betransmitted + * upstream + */ +#define EPN_MIN_REPORT_VALUE_DIFFERENCE_REG 0x2f0 + +/* The smallest allowable difference between ajacent non-zero queuesets. */ +#define MIN_REPORT_VALUE_DIFFERENCE_PRVMINREPORTDIFF_SHIFT 0 +#define MIN_REPORT_VALUE_DIFFERENCE_PRVMINREPORTDIFF_MASK 0x3fff + + +/* + * Register - read-only + * + * Indicates which BBH queue status interface event FIFOs have overflowed. + * Note: + * These bits are used for debug only. + */ +#define EPN_BBH_STATUS_FIFO_OVERFLOW_REG 0x2f4 + +/* + * Indicates which BBH queue status interface event FIFOs haveoverflowed. + * The overflow can only be corrected by reset. +*/ +#define BBH_STATUS_FIFO_OVERFLOW_UTXBBHSTATUSFIFOOVERFLOW_SHIFT 0 +#define BBH_STATUS_FIFO_OVERFLOW_UTXBBHSTATUSFIFOOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + * Spare RW bits + */ +#define EPN_SPARE_CTL_REG 0x2f8 + +/* Spare RW bits */ +#define SPARE_CTL_CFGEPNSPARE_SHIFT 2 +#define SPARE_CTL_CFGEPNSPARE_MASK 0xfffffffc + +/* + * Set this bit to enable store and forward upstream AE operation. + * Only set this bit when operating in Point-to-Point or ActiveEthernet + * modes. +*/ +#define SPARE_CTL_ECOUTXSNFENABLE_MASK 0x2 + +/* + * Set this bit to prevent transmitting when the LLID's shapers areempty. + * This will preventthe ONU from using excess bandwidth granted to it by + * the OLT. + * Do not set this bit when operating in Point-to-Point or ActiveEthernet + * modes. +*/ +#define SPARE_CTL_ECOJIRA758ENABLE_MASK 0x1 + + +/* + * Register + * + * Timestamp synchronizer offset. + */ +#define EPN_TS_SYNC_OFFSET_REG 0x2fc + +/* + * Provides lowest 6 bits of timestamp synchronizer, from 250 MHzdomain to + * 125 MHz. +*/ +#define TS_SYNC_OFFSET_CFGTSSYNCOFFSET_SHIFT 0 +#define TS_SYNC_OFFSET_CFGTSSYNCOFFSET_MASK 0x3f + + +/* + * Register + * + * Downstream timestamp offset. + */ +#define EPN_DN_TS_OFFSET_REG 0x300 + +/* Provides signed offset for downstream packet timestamping. */ +#define DN_TS_OFFSET_CFGDNTSOFFSET_SHIFT 0 +#define DN_TS_OFFSET_CFGDNTSOFFSET_MASK 0xffffffff + + +/* + * Register + * + * Upstream timestamp offset, lower 32 bits. + */ +#define EPN_UP_TS_OFFSET_LO_REG 0x304 + +/* Provides signed offset for upstream packet timestamping. */ +#define UP_TS_OFFSET_LO_CFGUPTSOFFSET_LO_SHIFT 0 +#define UP_TS_OFFSET_LO_CFGUPTSOFFSET_LO_MASK 0xffffffff + + +/* + * Register + * + * Upstream timestamp offset, upper 16 bits. + */ +#define EPN_UP_TS_OFFSET_HI_REG 0x308 + +/* Provides signed offset for upstream packet timestamping. */ +#define UP_TS_OFFSET_HI_CFGUPTSOFFSET_HI_SHIFT 0 +#define UP_TS_OFFSET_HI_CFGUPTSOFFSET_HI_MASK 0xffff + + +/* + * Register + * + * Provides control for the reading of two step timestamp FIFO, 4 + * entriesdeep. + */ +#define EPN_TWO_STEP_TS_CTL_REG 0x30c + +/* + * Provides the reading of the two step timestamp FIFO. + * A write valueof 1 will advance the FIFO to the next entry. + * The 48-bits value isprovided by + * registersEPN_TWO_STEP_TS_VALUE_HI/EPN_TWO_STEP_TS_VALUE_LO. +*/ +#define TWO_STEP_TS_CTL_TWOSTEPFFRD_MASK 0x80000000 + +/* Indicates the number of entries in the two step timestamp FIFO. */ +#define TWO_STEP_TS_CTL_TWOSTEPFFENTRIES_SHIFT 0 +#define TWO_STEP_TS_CTL_TWOSTEPFFENTRIES_MASK 0x7 + + +/* + * Register - read-only + * + * Lower 32-bits of 48-bits timestamp value, applicable for two + * steptimestamping. + */ +#define EPN_TWO_STEP_TS_VALUE_LO_REG 0x310 + +/* Lower 32-bits of two-step timestamp value for IEEE 1588timestamping. */ +#define TWO_STEP_TS_VALUE_LO_TWOSTEPTIMESTAMP_LO_SHIFT 0 +#define TWO_STEP_TS_VALUE_LO_TWOSTEPTIMESTAMP_LO_MASK 0xffffffff + + +/* + * Register - read-only + * + * Upper 16-bits of 48-bits timestamp value, applicable for two + * steptimestamping. + */ +#define EPN_TWO_STEP_TS_VALUE_HI_REG 0x314 + +/* Upper 16-bits of two-step timestamp value for IEEE 1588timestamping. */ +#define TWO_STEP_TS_VALUE_HI_TWOSTEPTIMESTAMP_HI_SHIFT 0 +#define TWO_STEP_TS_VALUE_HI_TWOSTEPTIMESTAMP_HI_MASK 0xffff + + +/* + * Register + * + * This register contains interrupt status for 1588 timestamp. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_1588_TIMESTAMP_INT_STATUS_REG 0x318 + +/* + * Indicated 1588 timestamp packet was aborted due to illegal checksumor + * timestamp offsets. +*/ +#define EPN_1588_TIMESTAMP_INT_STATUS_INT1588PKTABORT_MASK 0x2 + +/* + * Indicates timestamp in two step FIFO is available for reading. + * The48-bits value is provided by + * registersEPN_TWO_STEP_TS_VALUE_HI/EPN_TWO_STEP_TS_VALUE_LO. +*/ +#define EPN_1588_TIMESTAMP_INT_STATUS_INT1588TWOSTEPFFINT_MASK 0x1 + + +/* + * Register + * + * This register contains interrupt mask for 1588 timestamp interrupts. + */ +#define EPN_1588_TIMESTAMP_INT_MASK_REG 0x31c + +/* Mask 1588 timestamp packet abort. */ +#define EPN_1588_TIMESTAMP_INT_MASK_TS1588PKTABORT_MASK_MASK 0x2 + +/* Mask two step FIFO interrupt. */ +#define EPN_1588_TIMESTAMP_INT_MASK_TS1588TWOSTEPFF_MASK_MASK 0x1 + + +/* + * Register + * + * Specifies the setup time margin for the BBH to fetch upstream data + * totransfer to EPN. + * This margin MUST be used when the Epn is provisioned to delay the + * bursttermination while waiting for the Runner/BBH upstream queue status + * tobe updated. + * (see prvBbhQueStatDelay)The Power-On Reset default value of 0 will + * disable this delay. + * The units are in TimeQuanta (TQ = 16nS). + * The estimated DDR latency is2 [uS]. + * So, the minimum non-zero value for this register is 223 [TQ]. + */ +#define EPN_UP_PACKET_FETCH_MARGIN_REG 0x320 + +/* + * Minimum BBH upstream packet request latency. + * Units are TQ. +*/ +#define UP_PACKET_FETCH_MARGIN_UPPACKETFETCHMARGIN_SHIFT 0 +#define UP_PACKET_FETCH_MARGIN_UPPACKETFETCHMARGIN_MASK 0xffff + + +/* + * Register - read-only + * + * Provides real time indication of 1588 downstream timestamp. + * A changein value indicates downstream traffic to BBH. + */ +#define EPN_DN_1588_TIMESTAMP_REG 0x324 + +/* 32-bits timestamp value of downstream packet. */ +#define DN_1588_TIMESTAMP_DN_1588_TS_SHIFT 0 +#define DN_1588_TIMESTAMP_DN_1588_TS_MASK 0xffffffff + + +/* + * Register + * + * Specifies how long reports should persist. + */ +#define EPN_PERSISTENT_REPORT_CFG_REG 0x328 + +/* + * How long report persistance lasts. + * (How many report persistance timer ticks after the last non-zeroreport + * should empty reportsbe replaced with a persistant report)Units are + * report perisitance timer ticks. +*/ +#define PERSISTENT_REPORT_CFG_CFGPERSRPTDURATION_SHIFT 16 +#define PERSISTENT_REPORT_CFG_CFGPERSRPTDURATION_MASK 0x3ff0000 + +/* + * How many clock cycles are in each report persistance timer tick. + * The 125 MHz core clock rate requires 125 clocks per 1 uS tick. + * Units are core clock cycles. +*/ +#define PERSISTENT_REPORT_CFG_CFGPERSRPTTICKSIZE_SHIFT 0 +#define PERSISTENT_REPORT_CFG_CFGPERSRPTTICKSIZE_MASK 0xffff + + +/* + * Register + * + * Per LLID enable for persistent reporting. + */ +#define EPN_PERSISTENT_REPORT_ENABLES_REG 0x32c + +/* + * Per LLID enable for persistent reporting. + * Set the bit to enablepersistent reporting. + * 0: + * Disable persistent reporting. + * 1: + * Enable persistent reporting. +*/ +#define PERSISTENT_REPORT_ENABLES_CFGPERSRPTENABLE_SHIFT 0 +#define PERSISTENT_REPORT_ENABLES_CFGPERSRPTENABLE_MASK 0xffffffff + + +/* + * Register + * + * How many Time Quanta the persistent report should request. + */ +#define EPN_PERSISTENT_REPORT_REQUEST_SIZE_REG 0x330 + +/* + * How many Time Quanta the persistent report should request. + * Smallervalues waste less upstream bandwidth. + * Units are Time Quanta. +*/ +#define PERSISTENT_REPORT_REQUEST_SIZE_CFGPERSRPTREQTQ_SHIFT 0 +#define PERSISTENT_REPORT_REQUEST_SIZE_CFGPERSRPTREQTQ_MASK 0xffff + + +/* + * Register + * + * Allows control over reporting the extra per-packet overhead + * associatedwith 802. + * 1AE encryption. + * The AES overhead compensation logic supportstwo overhead modes: + * implicit SCI and explicit SCI. + * The implicit SCImode increases the per-packet overhead by 24 bytes. + * Explicit SCI modeincreases the per-packet overhead by 32 bytes. + */ +#define EPN_AES_CFG_1_REG 0x334 + +/* + * LLID index 16 AES overhead mode. + * 0: + * Implicit SCI AES overhead mode. + * 1: + * Explicit SCI AES overhead mode. + * .. + * LLID index 31 AES overhead mode. + * 30: + * Implicit SCI AES overhead mode. + * 31: + * Explicit SCI AES overhead mode. +*/ +#define AES_CFG_1_PRVUPSTREAMAESMODE_1_SHIFT 0 +#define AES_CFG_1_PRVUPSTREAMAESMODE_1_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * These registers limit how much data can be reported in REPORT frames. + * The EPON MAC reports data (that is sitting in the FIFO Queues) inbetween + * 1 and 4 "chunks". + * The size of these chunks is determined by theBurst Cap settings here. + * The units for these registers are 1 TQ for 1Gupstream mode. + * The units are one-tenth of a TQ for 10G upstream mode. + * To provision 4 TQ in 1G upstream mode, write a value of 4. + * To provision4 TQ in 10G upstream mode write a value of 40. + * Note that when register0x400 bit 21 is set that the provisioned value + * must be one time quantumless than the maximum value that should be + * reported to the OLT. + * When configured in shared burst cap mode, the burst cap value must + * bereduced by the following amounts (relative to the threshold/token + * sizevalue sent from the OLT)Mode Reduction Amount + * (bytes)---------------- -----------------------------------1G non-FEC 21 + * + number of CTC priority levels1G FEC 193 + number of CTC priority + * levels10G 20 + number of CTC priority levels10G implicit SCI 44 + number + * of CTC priority levels10G explicit SCI 52 + number of CTC priority + * levels + */ +#define EPN_BURST_CAPx_0_7_REG(x) (0x138 + (x) * 0x4) + +/* + * Defines maximum size of a report on LLID index 0 in Tek mode and onL2 0 + * in multi-priority mode. +*/ +#define BURST_CAPx_0_7_BURSTCAP0_SHIFT 0 +#define BURST_CAPx_0_7_BURSTCAP0_MASK 0xfffff + + +/* + * Registers - is [ 0 => 8 ] + * + */ +#define EPN_QUEUE_LLID_MAPx_0_7_REG(x) (0x158 + (x) * 0x4) + +/* Selects the L2 FIFO to which Queue 0 is mapped. */ +#define QUEUE_LLID_MAPx_0_7_QUELLIDMAP0_SHIFT 0 +#define QUEUE_LLID_MAPx_0_7_QUELLIDMAP0_MASK 0x1f + + +/* + * Registers - is [ 0 => 8 ] + * + * Statistics register that accumulates the number of upstream unused + * timequanta for an upstream LLID. + * The register saturates at maximum value. + * The register will clear uponread. + */ +#define EPN_UNUSED_TQ_CNTx_0_7_REG(x) (0x1bc + (x) * 0x4) + +/* The number of unused time quanta for LLID 0. */ +#define UNUSED_TQ_CNTx_0_7_UNUSEDTQCNT0_SHIFT 0 +#define UNUSED_TQ_CNTx_0_7_UNUSEDTQCNT0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * This register allows the effects of the upstream shaper 0 to be masked. + * When multiple priority queues point to a common shaping bucket, thelow + * priority traffic can use all the credits prior to a high priorityframe + * arriving. + * The high priority would then incur additional latencywaiting for credits + * to accrue. + * This adds undesirable delay to the datapath. + * This feature separates the queues that apply credit to a shaperand those + * that are masked by the shaper. + * The Shaping function has aninput that credits the shaping bucket when a + * frame is sent. + * It also hasan output that masks a queue from being eligible to transmit + * when theshaping rate is violated. + * In this case the low priority queue will bothcredit and be masked by the + * shaper as typically done. + * The high priorityon the other hand will credit the shaper, but not be + * limited by it. + * Theshaper will then be allowed to go into a deficit. + * In most cases thehigh priority is a small portion of the total + * bandwidth. + * In some caseshowever it may be desired to limit the high priority + * traffic with adifferent shaper. + */ +#define EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(x) (0x280 + (x) * 0x4) + +/* + * Each mask bit in this register controls the effect of shaper 0 onthe + * respective queue0: + * Shaper 0 can affect this queue1: + * Shaper 0 does not affect this queue +*/ +#define TX_L1S_SHP_QUE_MASKx_0_7_CFGSHPMASK0_SHIFT 0 +#define TX_L1S_SHP_QUE_MASKx_0_7_CFGSHPMASK0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * This registers configures the base addresses of the L2 structure 0. + * Internally the least significant two bits are treated as constants: + * Thetwo least significant start address bits are 0 and the two + * leastsignificant end address bits are 1. + * Therefore the queue base addressescannot be read directly from the + * register contents without performingsome mental gymnastics. + * Try to picture a 2-bit left shift and stuffoperation. + * The base address granularity is 4 entries. + * It is criticalthat the number of entries allocated for each FIFO be + * sufficient toaccommodate the worst case number of frames that can be + * contained inthe associated Fif queue. + * A general rule-of-thumb would be to dividethe number of bytes in the + * respective Fif queue by 80. + * The quotient+1will be the minimum number of entries that should be + * allocated. + * Do notforget to round up to the nearest 4-entry quanta. + * If the L2 is beingsized to match the burst cap (instead of the entire + * Fif queue size) donot forget to multiply the quotient+1 by four (or by 5 + * ifprvTekModePrefetch is set) when operating in Teknovus mode. + * There arefour burst cap values reported in Teknovus modeNote: + * This register cannot be programmed "on-the-fly". + * The queuestart/end address values should be changed only when its + * associatedclear L2 report FIFO" bit is set. + */ +#define EPN_TX_L2S_QUE_CONFIGx_0_7_REG(x) (0x2a0 + (x) * 0x4) + +/* Queue 0 End address */ +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUEEND0_SHIFT 16 +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUEEND0_MASK 0xfff0000 + +/* Queue 0 Start address */ +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUESTART0_SHIFT 0 +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUESTART0_MASK 0xfff + + +/* + * Registers - is [ 0 => 8 ] + * + * This register configures the maximum number of bytes that L2 queue 0can + * transmit during any given round. + * A round ends when all L2 queueshave reached their respective burst limit + * or there is no more data totransmit. + * Note that setting a burst limit to zero enables therespective L2 queue + * to transmit in strict priority. + * Also, any burstlimits that are set to 1 will cause those L2 queues to + * transmit inround-robin" fashion. + * It is possible to allocate bandwidth as apercentage. + * Simply multiply the desired percentage by 2000 bytes (themaximum frame + * length) and write that value in the associated burstlimit register. + * Example bandwidth sharing configuration: + * Priority Burst Limit Description-------- ----------- ------------0 0 + * High priority unlimited bandwidth1 0 Low priority unlimited bandwidth2 1 + * Equal priority UNI 1 unlimited bandwidth3 1 Equal priority UNI 2 + * unlimited bandwidth4 1 Equal priority UNI 3 unlimited bandwidth5 1 Equal + * priority UNI 4 unlimited bandwidth6 0 High priority best effort + * bandwidth7 0 Low priority best effort bandwidthPriority 0 is for the + * highest priority traffic. + * i. + * e. + * , ManagementtrafficPriority 1 is for real-time traffic. + * i. + * e. + * , VOIPPriorities 2, 3, 4 and 5 equally share bandwidth, i. + * e. + * Premium businesstraffic. + * Priorities 6 and 7 provide two classes of best effort traffic, i. + * e. + * twoclasses of consumer trafficPlease note that the EPN shaper is the + * mechanism used to limit theamount of traffic. + */ +#define EPN_TX_CTC_BURST_LIMITx_0_7_REG(x) (0x2cc + (x) * 0x4) + +/* L2 queue 0 CTC mode burst limit */ +#define TX_CTC_BURST_LIMITx_0_7_PRVBURSTLIMIT0_SHIFT 0 +#define TX_CTC_BURST_LIMITx_0_7_PRVBURSTLIMIT0_MASK 0x3ffff + + +/* + * Registers - is [ 0 => 24 ] + * + * These registers limit how much data can be reported in REPORT frames. + * The EPON MAC reports data (that is sitting in the FIFO Queues) inbetween + * 1 and 4 "chunks". + * The size of these chunks is determined by theBurst Cap settings here. + * The units for these registers are 1 TQ for 1Gupstream mode. + * The units are one-tenth of a TQ for 10G upstream mode. + * To provision 4 TQ in 1G upstream mode, write a value of 4. + * To provision4 TQ in 10G upstream mode write a value of 40. + * Note that when register0x400 bit 21 is set that the provisioned value + * must be one time quantumless than the maximum value that should be + * reported to the OLT. + * When configured in shared burst cap mode, the burst cap value must + * bereduced by the following amounts (relative to the threshold/token + * sizevalue sent from the OLT)Mode Reduction Amount + * (bytes)---------------- -----------------------------------1G non-FEC 21 + * + number of CTC priority levels1G FEC 193 + number of CTC priority + * levels10G 20 + number of CTC priority levels10G implicit SCI 44 + number + * of CTC priority levels10G explicit SCI 52 + number of CTC priority + * levels + */ +#define EPN_BURST_CAPx_8_31_REG(x) (0x338 + (x) * 0x4) + +/* + * Defines maximum size of a report on LLID index 8 in Tek mode and onL2 8 + * in multi-priority mode. +*/ +#define BURST_CAPx_8_31_BURSTCAP8_SHIFT 0 +#define BURST_CAPx_8_31_BURSTCAP8_MASK 0xfffff + + +/* + * Registers - is [ 0 => 24 ] + * + */ +#define EPN_QUEUE_LLID_MAPx_8_31_REG(x) (0x398 + (x) * 0x4) + +/* Selects the L2 FIFO to which Queue 8 is mapped. */ +#define QUEUE_LLID_MAPx_8_31_QUELLIDMAP8_SHIFT 0 +#define QUEUE_LLID_MAPx_8_31_QUELLIDMAP8_MASK 0x1f + + +/* + * Registers - is [ 0 => 24 ] + * + * Statistics register that accumulates the number of upstream unused + * timequanta for an upstream LLID. + * The register saturates at maximum value. + * The register will clear uponread. + */ +#define EPN_UNUSED_TQ_CNTx_8_31_REG(x) (0x3f8 + (x) * 0x4) + +/* The number of unused time quanta for LLID 8. */ +#define UNUSED_TQ_CNTx_8_31_UNUSEDTQCNT8_SHIFT 0 +#define UNUSED_TQ_CNTx_8_31_UNUSEDTQCNT8_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 24 ] + * + * This register allows the effects of the upstream shaper 8 to be masked. + * When multiple priority queues point to a common shaping bucket, thelow + * priority traffic can use all the credits prior to a high priorityframe + * arriving. + * The high priority would then incur additional latencywaiting for credits + * to accrue. + * This adds undesirable delay to the datapath. + * This feature separates the queues that apply credit to a shaperand those + * that are masked by the shaper. + * The Shaping function has aninput that credits the shaping bucket when a + * frame is sent. + * It also hasan output that masks a queue from being eligible to transmit + * when theshaping rate is violated. + * In this case the low priority queue will bothcredit and be masked by the + * shaper as typically done. + * The high priorityon the other hand will credit the shaper, but not be + * limited by it. + * Theshaper will then be allowed to go into a deficit. + * In most cases thehigh priority is a small portion of the total + * bandwidth. + * In some caseshowever it may be desired to limit the high priority + * traffic with adifferent shaper. + */ +#define EPN_TX_L1S_SHP_QUE_MASKx_8_31_REG(x) (0x5d8 + (x) * 0x4) + +/* + * Each mask bit in this register controls the effect of shaper 8 onthe + * respective queue0: + * Shaper 8 can affect this queue1: + * Shaper 8 does not affect this queue +*/ +#define TX_L1S_SHP_QUE_MASKx_8_31_CFGSHPMASK8_SHIFT 0 +#define TX_L1S_SHP_QUE_MASKx_8_31_CFGSHPMASK8_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 24 ] + * + * This registers configures the base addresses of the L2 structure 8. + * Internally the least significant two bits are treated as constants: + * Thetwo least significant start address bits are 0 and the two + * leastsignificant end address bits are 1. + * Therefore the queue base addressescannot be read directly from the + * register contents without performingsome mental gymnastics. + * Try to picture a 2-bit left shift and stuffoperation. + * The base address granularity is 4 entries. + * It is criticalthat the number of entries allocated for each FIFO be + * sufficient toaccommodate the worst case number of frames that can be + * contained inthe associated Fif queue. + * A general rule-of-thumb would be to dividethe number of bytes in the + * respective Fif queue by 80. + * The quotient+1will be the minimum number of entries that should be + * allocated. + * Do notforget to round up to the nearest 4-entry quanta. + * If the L2 is beingsized to match the burst cap (instead of the entire + * Fif queue size) donot forget to multiply the quotient+1 by four (or by 5 + * ifprvTekModePrefetch is set) when operating in Teknovus mode. + * There arefour burst cap values reported in Teknovus modeNote: + * This register cannot be programmed "on-the-fly". + * The queuestart/end address values should be changed only when its + * associatedclear L2 report FIFO" bit is set. + */ +#define EPN_TX_L2S_QUE_CONFIGx_8_31_REG(x) (0x638 + (x) * 0x4) + +/* Queue 8 End address */ +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUEEND8_SHIFT 16 +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUEEND8_MASK 0xfff0000 + +/* Queue 8 Start address */ +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUESTART8_SHIFT 0 +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUESTART8_MASK 0xfff + + +/* + * Registers - is [ 0 => 24 ] + * + * This register configures the maximum number of bytes that L2 queue 8can + * transmit during any given round. + * A round ends when all L2 queueshave reached their respective burst limit + * or there is no more data totransmit. + * Note that setting a burst limit to zero enables therespective L2 queue + * to transmit in strict priority. + * Also, any burstlimits that are set to 1 will cause those L2 queues to + * transmit inround-robin" fashion. + * It is possible to allocate bandwidth as apercentage. + * Simply multiply the desired percentage by 2000 bytes (themaximum frame + * length) and write that value in the associated burstlimit register. + * Example bandwidth sharing configuration: + * Priority Burst Limit Description-------- ----------- ------------0 0 + * High priority unlimited bandwidth1 0 Low priority unlimited bandwidth2 1 + * Equal priority UNI 1 unlimited bandwidth3 1 Equal priority UNI 2 + * unlimited bandwidth4 1 Equal priority UNI 3 unlimited bandwidth5 1 Equal + * priority UNI 4 unlimited bandwidth6 0 High priority best effort + * bandwidth7 0 Low priority best effort bandwidthPriority 0 is for the + * highest priority traffic. + * i. + * e. + * , ManagementtrafficPriority 1 is for real-time traffic. + * i. + * e. + * , VOIPPriorities 2, 3, 4 and 5 equally share bandwidth, i. + * e. + * Premium businesstraffic. + * Priorities 6 and 7 provide two classes of best effort traffic, i. + * e. + * twoclasses of consumer trafficPlease note that the EPN shaper is the + * mechanism used to limit theamount of traffic. + */ +#define EPN_TX_CTC_BURST_LIMITx_8_31_REG(x) (0x698 + (x) * 0x4) + +/* L2 queue 8 CTC mode burst limit */ +#define TX_CTC_BURST_LIMITx_8_31_PRVBURSTLIMIT8_SHIFT 0 +#define TX_CTC_BURST_LIMITx_8_31_PRVBURSTLIMIT8_MASK 0x3ffff + + +/* + * Registers - is [ 0 => 48 ] + * + * How many additional Time Quanta the queue sets should use in 10G mode. + * This feature is intended to be used inSIEPON mode. + */ +#define EPN_10G_ABC_SIZEx_REG(x) (0x6f8 + (x) * 0x4) + +/* + * How many additional Time Quanta LLID 0 queue set 2 should use in + * 10Gmode. + * If all three ABC registers are non-zero; this LLID's effective burstcap + * will be: + * burstCap0 + cfgAddBurstCap0_1 + cfgAddBurstCap0_2 +cfgAddBurstCap0_3. + * Units are Time Quanta. +*/ +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_2_SHIFT 16 +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_2_MASK 0xffff0000 + +/* + * How many additional Time Quanta LLID 0 queue set 1 should use in + * 10Gmode. + * If all three ABC registers are non-zero; this LLID's effective burstcap + * will be: + * burstCap0 + cfgAddBurstCap0_1 + cfgAddBurstCap0_2 +cfgAddBurstCap0_3. + * Units are Time Quanta. +*/ +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_1_SHIFT 0 +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_1_MASK 0xffff + + +#endif /* ! EPON_EPN_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_onu_mac_addr.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_onu_mac_addr.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_onu_mac_addr.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_onu_mac_addr.h 2023-03-09 15:06:11.360234118 +0100 @@ -0,0 +1,22 @@ +#ifndef EPON_EPN_ONU_MAC_ADDR_H_ +#define EPON_EPN_ONU_MAC_ADDR_H_ + +/* relative to epon */ + +/* + * Register + * + * These registers store a MAC address for each bidirectional ONU LLID. + * These addresses are inserted as the SA in REPORT frames sent upstream. + * Note: + * ONU MAC Address registers 8 through 23 are used only in + * loopbackoperation. + */ + +#define EPN_ONU_MAC_ADDRx_0_7_LO_REG(x) (0x1f0 + (x) * 8) +#define EPN_ONU_MAC_ADDRx_0_7_HI_REG(x) (0x1f4 + (x) * 8) + +#define EPN_ONU_MAC_ADDRx_8_31_LO_REG(x) (0x458 + (x) * 8) +#define EPN_ONU_MAC_ADDRx_8_31_HI_REG(x) (0x45c + (x) * 8) + +#endif /* ! EPON_EPN_ONU_MAC_ADDR_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_tx_l1s_shp.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_tx_l1s_shp.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_tx_l1s_shp.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_tx_l1s_shp.h 2023-03-09 15:06:11.360234118 +0100 @@ -0,0 +1,53 @@ +#ifndef EPON_EPN_TX_L1S_SHP_H_ +#define EPON_EPN_TX_L1S_SHP_H_ + +/* relative to epon */ + +/* + * Register + * + * This register configures upstream shaper i. + * There are 32 shapersavailable for shaping upstream traffic. + * The cfgShpEn bits are bit wiseselects for enabling shaping of the + * associated queues. + * Each shaper canhave shaping enabled on select queues or on all of the + * queues. + * If thebit is set, the corresponding shaper will be used for shaping + * creditsand control of its associated queue. + * The cfgShpRate and cfgMaxBstSizedefine the shaping. + * The cfgShpRate value represents the number of bytesthat are added to the + * shaper's byte credit accumulator each clockcycle. + * Given a 125 MHz clock-cycle; the cfgShpRate is in units of 2^-19Gbps + * (~1907. + * 34863 bps). + * The maximum burst size is in units of 256bytes. + */ +#define EPN_TX_L1S_SHP_CONFIGx_0_7_REG(x) (0x238 + (x) * 8) + +/* Shaper i Rate */ +#define CONFIG_CFGSHPRATE_SHIFT 8 +#define CONFIG_CFGSHPRATE_MASK 0x7fffff00 + +/* Shaper i Maximum Burst Size */ +#define CONFIG_CFGSHPBSTSIZE_SHIFT 0 +#define CONFIG_CFGSHPBSTSIZE_MASK 0xff + + +/* + * Register + * + * The bit wise selects for enabling shaping of the associated queues. + * Each shaper can have shaping enabled on select queues or on all of + * thequeues. + * If the bit is set, the corresponding shaper will be used forshaping + * credits and control of its associated queue. + */ +#define EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(x) (0x23c + (x) * 8) +#define EPN_TX_L1S_SHP_QUE_EN_REG 0x4 + +/* Set the bit(s) corresponding to the queue(s) this shaper shouldpolice. */ +#define QUE_EN_CFGSHPEN_SHIFT 0 +#define QUE_EN_CFGSHPEN_MASK 0xffffffff + + +#endif /* ! EPON_EPN_TX_L1S_SHP_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epon_top.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epon_top.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epon_top.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epon_top.h 2023-03-09 15:06:11.360234118 +0100 @@ -0,0 +1,306 @@ +#ifndef EPON_EPON_TOP_H_ +#define EPON_EPON_TOP_H_ + +/* relative to epon */ +#define EPON_TOP_OFFSET_0 0x0 + +/* + * Register + * + * Register used for testing read and write access into epon_top block. + */ +#define EPON_TOP_SCRATCH_REG 0x0 + +/* Scratch pad. */ +#define SCRATCH_SCRATCH_SHIFT 0 +#define SCRATCH_SCRATCH_MASK 0xffffffff + + +/* + * Register + * + */ +#define EPON_TOP_RESET_REG 0x4 + +/* Active low reset for XPcsRx module. */ +#define RESET_XPCSRXRST_N_MASK 0x80 + +/* Active low reset for XPcsTx module. */ +#define RESET_XPCSTXRST_N_MASK 0x40 + +/* Active low reset for XIF module. */ +#define RESET_XIFRST_N_MASK 0x20 + +/* Active low reset for Tod module. */ +#define RESET_TODRST_N_MASK 0x10 + +/* Active low reset for ClkPrgSwch module. */ +#define RESET_CLKPRGRST_N_MASK 0x8 + +/* Active low reset for Nco module. */ +#define RESET_NCORST_N_MASK 0x4 + +/* Active low reset for Lif module. */ +#define RESET_LIFRST_N_MASK 0x2 + +/* Active low reset for Epn module. */ +#define RESET_EPNRST_N_MASK 0x1 + + +/* + * Register + * + * Top level interrupts for all EPON blocks. + */ +#define EPON_TOP_INTERRUPT_REG 0x8 + +/* Interrupt from 1 pps input. */ +#define INTERRUPT_INT_1PPS_MASK 0x80 + +/* Interrupt from XPcsTx module. */ +#define INTERRUPT_INT_XPCS_TX_MASK 0x40 + +/* Interrupt from XPcsRx module. */ +#define INTERRUPT_INT_XPCS_RX_MASK 0x20 + +/* Interrupt from XIF module. */ +#define INTERRUPT_INT_XIF_MASK 0x10 + +/* Interrupt from NCO module. */ +#define INTERRUPT_INT_NCO_MASK 0x8 + +/* Interrupt from LIF module. */ +#define INTERRUPT_INT_LIF_MASK 0x4 + +/* Interrupt from EPN module. */ +#define INTERRUPT_INT_EPN_MASK 0x1 + + +/* + * Register + * + * Top level interrupts for all EPON blocks. + * For any bit, a value of 1will enable the interrupt, and a value of 0 + * will mask the interrupt. + * By default, all interrupts are masked. + */ +#define EPON_TOP_INTERRUPT_MASK_REG 0xc + +/* Mask for interrupt from 1 pps input. */ +#define INTERRUPT_MASK_INT_1PPS_MASK_MASK 0x80 + +/* Mask for interrupt from XPcsTx module. */ +#define INTERRUPT_MASK_INT_XPCS_TX_MASK_MASK 0x40 + +/* Mask for interrupt from XPcsRx module. */ +#define INTERRUPT_MASK_INT_XPCS_RX_MASK_MASK 0x20 + +/* Mask for interrupt from XIF module. */ +#define INTERRUPT_MASK_INT_XIF_MASK_MASK 0x10 + +/* Mask for interrupt from NCO module. */ +#define INTERRUPT_MASK_INT_NCO_MASK_MASK 0x8 + +/* Mask for interrupt from LIF module. */ +#define INTERRUPT_MASK_INT_LIF_MASK_MASK 0x4 + +/* Mask for interrupt from EPN module. */ +#define INTERRUPT_MASK_INT_EPN_MASK_MASK 0x1 + + +/* + * Register + * + * High level configuration for the EPON block. + */ +#define EPON_TOP_CONTROL_REG 0x10 + +/* + * 0:1G downstream mode + * 1:2G downstream mode +*/ +#define CONTROL_CFGTWOGIGPONDNS_MASK 0x4 + +/* + * 0: + * 1G uptream mode 1: + * 10G upstream mode +*/ +#define CONTROL_CFGTENGIGPONUP_MASK 0x2 + +/* + * 0: + * 1G downstream mode 1: + * 10G downstream mode +*/ +#define CONTROL_CFGTENGIGDNS_MASK 0x1 + + +/* + * Register + * + * High level configuration for the EPON block. + */ +#define EPON_TOP_ONE_PPS_MPCP_OFFSET_REG 0x14 + +/* Provides additional offset to MPCP sampling due to 1 pps inputassertion. */ +#define ONE_PPS_MPCP_OFFSET_CFG_1PPS_MPCP_OFFSET_SHIFT 0 +#define ONE_PPS_MPCP_OFFSET_CFG_1PPS_MPCP_OFFSET_MASK 0xffffffff + + +/* + * Register - read-only + * + * High level configuration for the EPON block. + */ +#define EPON_TOP_ONE_PPS_CAPTURED_MPCP_TIME_REG 0x18 + +/* Captured MPCP time due to 1 pps input assertion. */ +#define ONE_PPS_CAPTURED_MPCP_TIME_CAPTURE_1PPS_MPCP_TIME_SHIFT 0 +#define ONE_PPS_CAPTURED_MPCP_TIME_CAPTURE_1PPS_MPCP_TIME_MASK 0xffffffff + + +/* + * Register + * + * Register used for 48-bit timestamp Time Of Day (TOD) configuration. + */ +#define EPON_TOP_TOD_CONFIG_REG 0x1c + +/* + * When this bit is set, hardware will update the internal + * nanosecondcounter, cfg_tod_ns[31: + * 0], when the local MPCP time equalscfg_tod_mpcp[31: + * 0]. + * Software should set this bit and wait untilhardware clears it before + * setting it again. +*/ +#define TOD_CONFIG_CFG_TOD_LOAD_NS_MASK 0x80000000 + +/* + * When this bit is set, hardware will latch the internal ts48, ns, + * andseconds counters. + * Software should set this bit and wait untilhardware clears it before + * setting it again. + * Once hardware hascleared the bit, the timers are available to be read. +*/ +#define TOD_CONFIG_CFG_TOD_READ_MASK 0x800000 + +/* + * Select the block to read the timers from. + * 0: + * Reserved. + * 1: + * 1G EPON. + * 2: + * 10G EPON. + * 3: + * AE. + * This field should not be changed whilecfg_tod_read is set. +*/ +#define TOD_CONFIG_CFG_TOD_READ_SEL_SHIFT 21 +#define TOD_CONFIG_CFG_TOD_READ_SEL_MASK 0x600000 + +/* + * Allow 1PPS pulse to clear the counter if set. + * If not set, the 1PPSpulse will have no effect on the TS48. +*/ +#define TOD_CONFIG_CFG_TOD_PPS_CLEAR_MASK 0x100000 + +/* + * The rising edge will be latched, and cfg_tod_seconds will be loadedon + * the next 1PPS pulse or when the next second rolls over. +*/ +#define TOD_CONFIG_CFG_TOD_LOAD_MASK 0x80000 + +/* Number of seconds to be loaded. */ +#define TOD_CONFIG_CFG_TOD_SECONDS_SHIFT 0 +#define TOD_CONFIG_CFG_TOD_SECONDS_MASK 0x7ffff + + +/* + * Register + * + * Register used to load nanosecond counter. + */ +#define EPON_TOP_TOD_NS_REG 0x20 + +/* + * Value to be loaded when the MPCP time reaches cfg_tod_mpcp. + * Thisfield should not be updated while cfg_tod_load_ns is set. +*/ +#define TOD_NS_CFG_TOD_NS_SHIFT 0 +#define TOD_NS_CFG_TOD_NS_MASK 0xffffffff + + +/* + * Register + * + * Register used to hold MPCP value that will be used to determine whenthe + * nanosecond counter is updated. + * This field should not be updatedwhile cfg_tod_load_ns is set. + */ +#define EPON_TOP_TOD_MPCP_REG 0x24 + +/* MPCP value to wait for before loading cfg_tod_ns. */ +#define TOD_MPCP_CFG_TOD_MPCP_SHIFT 0 +#define TOD_MPCP_CFG_TOD_MPCP_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back + * fromEPON/AE block. + */ +#define EPON_TOP_TS48_MSB_REG 0x28 + +/* Upper 16-bits of TS48. */ +#define TS48_MSB_TS48_EPON_READ_MSB_SHIFT 0 +#define TS48_MSB_TS48_EPON_READ_MSB_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back + * fromEPON/AE block. + */ +#define EPON_TOP_TS48_LSB_REG 0x2c + +/* Lower 32-bits of TS48. */ +#define TS48_LSB_TS48_EPON_READ_LSB_SHIFT 0 +#define TS48_LSB_TS48_EPON_READ_LSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for seconds read back from EPON/AE block. + */ +#define EPON_TOP_TSEC_REG 0x30 + +/* + * Seconds[18: + * 0]. +*/ +#define TSEC_TSEC_EPON_READ_SHIFT 0 +#define TSEC_TSEC_EPON_READ_MASK 0x7ffff + + +/* + * Register - read-only + * + * Register used for nanoseconds read back from EPON/AE block. + */ +#define EPON_TOP_TNS_EPON_REG 0x34 + +/* + * Nanoseconds[31: + * 0]. +*/ +#define TNS_EPON_TNS_EPON_READ_SHIFT 0 +#define TNS_EPON_TNS_EPON_READ_MASK 0xffffffff + + +#endif /* ! EPON_EPON_TOP_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_lif.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_lif.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_lif.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_lif.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,2489 @@ +#ifndef EPON_LIF_H_ +#define EPON_LIF_H_ + +/* relative to epon */ +#define LIF_OFFSET_0 0x1800 + +/* + * Register + * + * This register controls and configures the LIF PON module. + * Configurationbits dealing directly with the operational mode, laser + * control, andloopback are here. + */ +#define LIF_PON_CONTROL_REG 0x0 + +/* Enable adaptive short preamble for P2P mode. */ +#define LIF_PON_CONTROL_CFP2PMODEADAPTIVESHORTPRE_MASK 0x40000000 + +/* Disable runt packet filtering. */ +#define LIF_PON_CONTROL_CFGDISRUNTFILTER_MASK 0x20000000 + +/* + * Maximum number of allowable comma errors before LOS is asserted. + * 0: + * Functionality Disabled +*/ +#define LIF_PON_CONTROL_CFMAXCOMMAERRCNT_SHIFT 25 +#define LIF_PON_CONTROL_CFMAXCOMMAERRCNT_MASK 0x1e000000 + +/* + * Selects between three 802. + * 3 synchronization state machines: + * 0: + * 802. + * 3ah-65 FEC (single code word traversal)1: + * 802. + * 3-36 non FEC (single code word traversal)2: + * Legacy (based on FEC, but traverses state machine two code wordsat a + * time). + * 3: + * Reserved +*/ +#define LIF_PON_CONTROL_CFSYNCSMSELECT_SHIFT 23 +#define LIF_PON_CONTROL_CFSYNCSMSELECT_MASK 0x1800000 + +/* + * Force aborts any NonFec frames in the PON module. + * This abort occursbefore the FecRx module; therefore any frames dropped + * at this pointwill not have statistics tabulated. + * 0: + * Disabled1: + * Enabled +*/ +#define LIF_PON_CONTROL_CFPONRXFORCENONFECABORT_MASK 0x400000 + +/* + * Force aborts any FEC frames in the PON module. + * This abort occursbefore the FecRx module; therefore any frames dropped + * at this pointwill not have statistics tabulated. + * 0: + * Disabled1: + * Enabled +*/ +#define LIF_PON_CONTROL_CFPONRXFORCEFECABORT_MASK 0x200000 + +/* + * Controls the order of the 10B/20B sent from the SERDES to the LIFmodule. + * 0: + * Receive data is unflipped. + * 1: + * Receive data is flipped. + * Default : + * 1 +*/ +#define LIF_PON_CONTROL_CFGRXDATABITFLIP_MASK 0x100000 + +/* + * Enable upstream padding of MPCP/OAM in an 802. + * 1ae encrypted link toinclude security overhead. +*/ +#define LIF_PON_CONTROL_CFGENMPCPOAMPAD_MASK 0x40000 + +/* Enable IDLE packet support to prevent upstream underrun. */ +#define LIF_PON_CONTROL_CFGENTXIDLEPKT_MASK 0x20000 + +/* + * Lock synchronization state indefinitely. + * This bit must be used inconjunction with cfEnableExtendSync. +*/ +#define LIF_PON_CONTROL_CFENABLESOFTWARESYNCHOLD_MASK 0x10000 + +/* + * Extend synchronization state. + * This can be used to improve FEC gain. +*/ +#define LIF_PON_CONTROL_CFENABLEEXTENDSYNC_MASK 0x8000 + +/* + * Allow alignment state machine to achieve code word lock in threeidles, + * as opposed to four. +*/ +#define LIF_PON_CONTROL_CFENABLEQUICKSYNC_MASK 0x4000 + +/* + * No function in this release of EPON. + * Default: + * 1 +*/ +#define LIF_PON_CONTROL_CFPPSEN_MASK 0x2000 + +/* + * 0: + * 1PPS is not aligned to the 10MHz clock. + * 1: + * 1PPS is aligned to the positive edge of the 10MHz clock. + * Default: + * 1 +*/ +#define LIF_PON_CONTROL_CFPPSCLKRBC_MASK 0x1000 + +/* + * 0: + * Disable Loop Back from Downstream to Upstream in the LIF. + * 1: + * Enable Loop Back from Downstream to Upstream in the LIF. +*/ +#define LIF_PON_CONTROL_CFRX2TXLPBACK_MASK 0x800 + +/* + * 0: + * Disable Loop Back from Upstream to Downstream in the LIF. + * 1: + * Enable Loop Back from Upstream to Downstream in the LIF. + * Note: + * Due to a bug in BCM6838A0, RX stats will not tabulatecorrectly while in + * this loopback mode. + * TX stats should be usedinstead. +*/ +#define LIF_PON_CONTROL_CFTX2RXLPBACK_MASK 0x400 + +/* + * 0: + * IDLE words continue to transmit while laser is turned off. + * 1: + * Transmitted data bus is de-asserted to zero when laser is turnedoff. +*/ +#define LIF_PON_CONTROL_CFTXDATAENDURLON_MASK 0x200 + +/* + * 0: + * LIF sends standard EPON Preamble. + * 1: + * LIF sends Ethernet Preamble for Point-to-Point operation. +*/ +#define LIF_PON_CONTROL_CFP2PMODE_MASK 0x100 + +/* + * 0: + * Send Standard P2P Ethernet Preamble. + * 1: + * Send Short (7 byte) P2P Ethernet Preamble. + * This bit must be setwith cfP2PMode if full line rate is desired with odd + * sized frames. + * If this bit is not set in P2P mode, only even sized frames arecapable of + * line rate. + * The link partner must also be short preamblereceive capable. +*/ +#define LIF_PON_CONTROL_CFP2PSHORTPRE_MASK 0x80 + +/* + * The output enable control for the 1Gbps upstream laser control(TXEN) + * pin. + * 0: + * 1G laser control pin is tri-stated1: + * 1G laser control is driven by the LIF module. +*/ +#define LIF_PON_CONTROL_CFLASEREN_MASK 0x40 + +/* + * 0: + * Laser is turned on at grant start time. + * 1: + * Laser is turned on continuously. +*/ +#define LIF_PON_CONTROL_CFTXLASERON_MASK 0x20 + +/* + * 0: + * Configures the Laser On signal as active low. + * 1: + * Configures the Laser On signal as active high. +*/ +#define LIF_PON_CONTROL_CFTXLASERONACTHI_MASK 0x10 + +/* + * Resets the transmit side of the LIF. + * 0: + * Reset LIF TX. + * 1: + * Normal operation. +*/ +#define LIF_PON_CONTROL_LIFTXRSTN_PRE_MASK 0x8 + +/* + * Resets the receive side of the LIF. + * 0: + * Reset LIF RX. + * 1: + * Normal operation. +*/ +#define LIF_PON_CONTROL_LIFRXRSTN_PRE_MASK 0x4 + +/* + * Enables LIF TX for operation. + * 0: + * Disable the external interface to and from the LIF TX. + * 1: + * Enable the external interface to and from the LIF TX. +*/ +#define LIF_PON_CONTROL_LIFTXEN_MASK 0x2 + +/* + * Enables LIF RX for operation. + * 0: + * Disable the external interface to and from the LIF RX. + * 1: + * Enable the external interface to and from the LIF RX. +*/ +#define LIF_PON_CONTROL_LIFRXEN_MASK 0x1 + + +/* + * Register + * + * This register controls and configures the LIF PON module + * specificallydealing with interoperability. + */ +#define LIF_PON_INTER_OP_CONTROL_REG 0x4 + +/* + * Units are in code group pairs (two 10b code groups). + * 0: + * Disable Ipg Filter (Legacy Behavior)1-3: + * DO NOT USE, Illegal Values, allows faster than line rateoperation. + * 4-15: + * Allow 4 to 15 code group pairs to elapse after a frame beforebecoming + * receptive to a SOP or SFEC again. + * Default: + * 5 code group pairs or "10 bytes of IPG". + * Per spec, "12bytes of IPG" is line rate, but thedefault setting allows + * for a rate that is slightly faster than linerate for tolerance purposes. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFIPGFILTER_SHIFT 27 +#define LIF_PON_INTER_OP_CONTROL_CFIPGFILTER_MASK 0x78000000 + +/* + * Allows for control of logic which blocks laser enable based oncondition + * of downstream sync. + * 0: + * Allow for los to block laser enable. + * 1: + * Laser will toggle regardless of state of downstream code groupsync +*/ +#define LIF_PON_INTER_OP_CONTROL_CFDISABLELOSLASERBLOCK_MASK 0x4000000 + +/* + * All unmapped LLIDs will be redirected and mapped to Index 0. + * 0: + * Unmapped LLIDs will appear to be unmapped to EPN. + * 1: + * Unmapped LLIDs will appear on Index 0 to EPN. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFGLLIDPROMISCUOUSMODE_MASK 0x2000000 + +/* + * Masks MSB of 16 bit raw LLID for Index translation. + * 0: + * Don't mask, look at full 16 bits. + * 1: + * Mask bit[15], map based on [14: + * 0]. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFGLLIDMODMSK_MASK 0x1000000 + +/* + * Allows SFEC to consume 4 bytes of IPG per standard. + * 0: + * 4 Additional bytes of IPG will be added for SFEC. + * 1: + * SFEC will carve 4 bytes out of existing IPG. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFUSEFECIPG_MASK 0x800000 + +/* + * Enable inverted CRC-8 checking. + * 0: + * Disable CRC-8 checking. + * Packets with inverted CRC-8 arediscarded. + * 1: + * Enable CRC-8 checking. + * Packets with inverted CRC-8 are consideredvalid. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8INVCHK_MASK 0x400000 + +/* + * 0: + * CRC-8 is checked from LSB to MSB in the downstream direction. + * 1: + * CRC-8 is checked from MSB to LSB in the downstream direction. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8BITSWAP_MASK 0x200000 + +/* + * 0: + * CRC-8 is checked by shifting data from MSB to LSB in thedownstream + * direction. + * 1: + * CRC-8 is checked by shifting data from LSB to MSB in thedownstream + * direction. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8MSB2LSB_MASK 0x100000 + +/* + * 0: + * Enable Crc-8 checking. + * 1: + * Disable Crc-8 checking. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8DISABLE_MASK 0x80000 + +/* + * 0: + * Bit 15 of LLID in the upstream path is zero. + * 1: + * Bit 15 of LLID in the upstream path is set. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXLLIDBIT15SET_MASK 0x20000 + +/* + * 0: + * Transmit correct Crc-81: + * Transmit inverted Crc-8 on a per packet basis. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8INV_MASK 0x10000 + +/* + * 0: + * Transmit correct Crc-81: + * Transmit bad Crc-8 +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8BAD_MASK 0x8000 + +/* + * 0: + * Generated upstream Crc-8 byte is transmitted from Lsb to Msb. + * 1: + * Generated upstream Crc-8 byte is transmitted from Msb to Lsb. + * Note: + * This feature is added to give the ONU more flexibility oftransmitting + * the Crc-8 byte. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8BITSWAP_MASK 0x4000 + +/* + * 0: + * Generate upstream Crc-8 by shifting data from Lsb to Msb. + * 1: + * Generate upstream Crc-8 by shifting data from Msb to Lsb. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8MSB2LSB_MASK 0x2000 + +/* + * 0: + * Normal operation. + * 1: + * Enable the LIF module to transmit short pre-amble in the upstreampath. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXSHORTPRE_MASK 0x1000 + +/* + * LIF upstream IPG counter. + * Each unit represents one time quanta or16ns. + * Default: + * 2 +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXIPGCNT_SHIFT 8 +#define LIF_PON_INTER_OP_CONTROL_CFTXIPGCNT_MASK 0xf00 + +/* + * 0: + * Normal OperationGreater than 0: + * This bit field is used for testing with Panasonictransceivers. + * The pattern of 10'b10_1010_1010 (2AA) will transmit atthe beginning of + * every burst. + * The number transmitted word isprogrammable based on the configuration of + * cfInitIdle in register0x10d. + * The amount transmitted is always a portion of cfInitIdle upto a maximum + * of 16. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXAASYNCLEN_SHIFT 4 +#define LIF_PON_INTER_OP_CONTROL_CFTXAASYNCLEN_MASK 0xf0 + +/* + * Pipeline delay to be added on to laser on time and laser off + * timeDefault: + * 6 +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXPIPEDELAY_SHIFT 0 +#define LIF_PON_INTER_OP_CONTROL_CFTXPIPEDELAY_MASK 0xf + + +/* + * Register + * + * This register controls and configures the LIF FEC sub-module block. + * Configuration bits dealing directly with forward error correction + * arehere. + */ +#define LIF_FEC_CONTROL_REG 0x8 + +/* + * 0: + * Uncorrectable frames are aborted. + * 1: + * Uncorrectable frames are forwarded. +*/ +#define LIF_FEC_CONTROL_CFFECRXERRORPROP_MASK 0x20 + +/* + * Aborts non-FEC frames after the FecRx module. + * Statistics will stillbe tabulated for frames aborted through this + * manner. + * 0: + * Non-FEC frames are forwarded. + * 1: + * Non-FEC frames are aborted. +*/ +#define LIF_FEC_CONTROL_CFFECRXFORCENONFECABORT_MASK 0x10 + +/* + * Aborts FEC frames after the FecRx module. + * Statistics will still betabulated for frames aborted through this + * manner. + * 0: + * FEC frames are forwarded. + * 1: + * FEC frames are aborted. +*/ +#define LIF_FEC_CONTROL_CFFECRXFORCEFECABORT_MASK 0x8 + +/* + * Enable FEC on Receiver0: + * FEC Disabled1: + * FEC Enabled +*/ +#define LIF_FEC_CONTROL_CFFECRXENABLE_MASK 0x4 + +/* + * Enables per LLID Fec Parity Generation. + * This bit, cfFecTxEn, corresponding llid enable bit + * cfFecTxFecLlidEn#below must be set. + * 0: + * Disabled1: + * Enabled +*/ +#define LIF_FEC_CONTROL_CFFECTXFECPERLLID_MASK 0x2 + +/* + * Enable FEC on Transmitter0: + * FEC Disabled1: + * FEC Enabled +*/ +#define LIF_FEC_CONTROL_CFFECTXENABLE_MASK 0x1 + + +/* + * Register + * + * This register controls and configures the LIF SEC sub-module block. + * Configuration bits dealing directly with security encryption are here. + */ +#define LIF_SEC_CONTROL_REG 0xc + +/* Disable OAM encryption. */ +#define LIF_SEC_CONTROL_CFGDISMPCPENCRYPT_MASK 0x80000000 + +/* Disable OAM encryption. */ +#define LIF_SEC_CONTROL_CFGDISOAMENCRYPT_MASK 0x40000000 + +/* Enables downstream security short length support. */ +#define LIF_SEC_CONTROL_CFGSECENSHORTLEN_MASK 0x20000000 + +/* Enables downstream security packet number rollover. */ +#define LIF_SEC_CONTROL_CFGSECDNENPKTNUMRLOVR_MASK 0x10000000 + +/* Enables upstream security packet number rollover. */ +#define LIF_SEC_CONTROL_CFGSECUPENPKTNUMRLOVR_MASK 0x8000000 + +/* Enables replay protection on RX security. */ +#define LIF_SEC_CONTROL_CFGENAEREPLAYPRCT_MASK 0x4000000 + +/* Enables legacy RCC priority encoding mode for EPON encryption. */ +#define LIF_SEC_CONTROL_CFGENLEGACYRCC_MASK 0x2000000 + +/* + * Enables fake AES mode in the upstream for FPGA testing. + * 0: + * Normal operation. + * 1: + * Enable fake AES. +*/ +#define LIF_SEC_CONTROL_ENFAKEUPAES_MASK 0x1000000 + +/* + * Enables fake AES mode in the downstream for FPGA testing. + * 0: + * Normal operation. + * 1: + * Enable fake AES. +*/ +#define LIF_SEC_CONTROL_ENFAKEDNAES_MASK 0x800000 + +/* + * FEC IPG Len used by SEC to support certain security modes. + * Default: + * 0xa +*/ +#define LIF_SEC_CONTROL_CFGFECIPGLEN_SHIFT 13 +#define LIF_SEC_CONTROL_CFGFECIPGLEN_MASK 0x1fe000 + +/* + * Disable downstream DA/SA encryption. + * 0: + * Enable DA/SA encryption1: + * Disable DA/SA encryption +*/ +#define LIF_SEC_CONTROL_DISDNDASAENCRPT_MASK 0x1000 + +/* + * 0: + * Single Churning encryption (do not use)1: + * Triple Churning encryptionThis bit matters only when dnEncryptScheme is + * set to "CEPON". + * Default: + * 1 +*/ +#define LIF_SEC_CONTROL_ENTRIPLECHURN_MASK 0x800 + +/* + * 0: + * In EPON mode, all packets must be either encrypted ornon-encrypted; a + * mixture of both is not allowed. + * The turning on/offof encryption can be initiated only by the OLT. + * 1: + * In EPON mode, mixing of encrypted and non-encrypted packets isallowed + * for a particular LLID. + * Default: + * 1 +*/ +#define LIF_SEC_CONTROL_ENEPNMIXENCRYPT_MASK 0x400 + +/* + * Disable upstream DA/SA encryption. + * 0: + * Enable DA/SA encryption1: + * Disable DA/SA encryption +*/ +#define LIF_SEC_CONTROL_DISUPDASAENCRPT_MASK 0x200 + +/* + * Defines the upstream security decryption scheme. + * 0: + * Teknovus encryption1: + * Reserved2: + * EPON encryption +*/ +#define LIF_SEC_CONTROL_SECUPENCRYPTSCHEME_SHIFT 7 +#define LIF_SEC_CONTROL_SECUPENCRYPTSCHEME_MASK 0x180 + +/* + * Defines the downstream security decryption scheme. + * 0: + * Teknovus encryption1: + * Reserved2: + * EPON encryption3: + * CEPON encryption4: + * Zero-overhead encryption5: + * AE encryption +*/ +#define LIF_SEC_CONTROL_SECDNENCRYPTSCHEME_SHIFT 4 +#define LIF_SEC_CONTROL_SECDNENCRYPTSCHEME_MASK 0x70 + +/* + * Resets upstream SEC. + * 0: + * Reset UP SEC. + * 1: + * Normal operation +*/ +#define LIF_SEC_CONTROL_SECUPRSTN_PRE_MASK 0x8 + +/* + * Resets downstream SEC. + * 0: + * Reset DN SEC. + * 1: + * Normal operation. +*/ +#define LIF_SEC_CONTROL_SECDNRSTN_PRE_MASK 0x4 + +/* + * Global enable for upstream encryption0: + * Disable upstream encryption. + * 1: + * Enable upstream encryption. +*/ +#define LIF_SEC_CONTROL_SECENUP_MASK 0x2 + +/* + * Global enable for downstream decryption0: + * Disable downstream decryption. + * 1: + * Enable downstream decryption. +*/ +#define LIF_SEC_CONTROL_SECENDN_MASK 0x1 + + +/* + * Register + * + * This register specifies the 802. + * 1ae MacSec Ethertype to be insertedinto the packet. + */ +#define LIF_MACSEC_REG 0x10 + +/* Defines the MacSec Ethertype. */ +#define LIF_MACSEC_CFGMACSECETHERTYPE_SHIFT 0 +#define LIF_MACSEC_CFGMACSECETHERTYPE_MASK 0xffff + + +/* + * Register + * + * This register contains interrupt status for LIF modules. + * These bits are sticky; to clear a bit, write 1 to it. + */ +#define LIF_INT_STATUS_REG 0x14 + +/* + * [NON-FATAL]Indicates that an SOP or SFEC was detected in an IPG window + * inexcess of what was provisioned in cfIpgFilter. + * Please seecfIpgFilter for more details. +*/ +#define LIF_INT_STATUS_INT_SOP_SFEC_IPG_VIOLATION_MASK 0x200000 + +/* + * Indicates laser enable on time exceeed the maximum threshold, asdefined + * by register LIF_LSR_MON_A_MAX_THR. +*/ +#define LIF_INT_STATUS_LASERONMAX_MASK 0x100000 + +/* Indicates laser enable deassertion. */ +#define LIF_INT_STATUS_LASEROFF_MASK 0x80000 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thereceived packet was aborted due to replay protection. +*/ +#define LIF_INT_STATUS_SECDNREPLAYPROTCTABORT_MASK 0x40000 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thetransmit packet number exceeded the maximum threshold and + * about tooverflow. + * Threshold is programmed in register LIF_AE_PKTNUM_THRESH. +*/ +#define LIF_INT_STATUS_SECUPPKTNUMOVERFLOW_MASK 0x20000 + +/* + * [NON-FATAL]Laser was turned off in the middle of a burst. + * This usuallyindicates misconfiguration which results in EPN + * "overstuffing" aburst. + * Note: + * This interrupt will fire while in P2P or in DN2UP Loopbackmode. + * S/W is to mask this bit during those modes. + * A fix may beintroduced into later revisions of chip to fix this cosmetic + * issue(FLEXIPON-138). +*/ +#define LIF_INT_STATUS_INTLASEROFFDURBURST_MASK 0x10000 + +/* + * [NON-FATAL]Line code error threshold was exceeded. + * Program with LIF RX BER Threshold and Interval register (0x1b4) +*/ +#define LIF_INT_STATUS_INTRXBERTHRESHEXC_MASK 0x8000 + +/* The LIF detected a FEC receive frame. */ +#define LIF_INT_STATUS_INTFECRXFECRECVSTATUS_MASK 0x4000 + +/* + * [FATAL] Error location FIFO in Corrector logic has overflowed; somedata + * blocks will go uncorrected. + * This is considered a fatal interrupt because this introduces FECblock + * level inconsistencies, which may cause the correction of thewrong + * blocks. +*/ +#define LIF_INT_STATUS_INTFECRXCORERRFIFOFULLSTATUS_MASK 0x2000 + +/* + * Error location FIFO in Corrector logic has gone empty beforefinishing a + * FEC frame. + * This is considered a fatal interrupt becausethis introduces FEC block + * level inconsistencies, which may cause thecorrection of the wrong + * blocks. +*/ +#define LIF_INT_STATUS_INTFECRXCORERRFIFOUNEXPEMPTY_MASK 0x1000 + +/* + * [FATAL] Data was popped from an empty FEC Buffer pipeline, + * whichsimultaneously was having data pushed into it from the FEC + * BufferSRAM. +*/ +#define LIF_INT_STATUS_INTFECBUFPOPEMPTYPUSH_MASK 0x800 + +/* + * [FATAL] Data was popped from an empty FEC Buffer pipeline, + * whichsimultaneously no data was being pushed into the pipeline from + * theFEC Buffer SRAM. +*/ +#define LIF_INT_STATUS_INTFECBUFPOPEMPTYNOPUSH_MASK 0x400 + +/* + * [FATAL] Data was read from FEC Buffer SRAM and pushed into a fullFEC + * Buffer pipeline. + * This is fatal. + * Write a one to clear this bit. +*/ +#define LIF_INT_STATUS_INTFECBUFPUSHFULL_MASK 0x200 + +/* + * [NON-FATAL] Gate frame's MPCP timestamp vastly different thancurrent + * MPCP time. + * Triggered afull timestamp update. +*/ +#define LIF_INT_STATUS_INTUPTIMEFULLUPDSTAT_MASK 0x100 + +/* + * [FATAL] LIF detects a frame from Epn Utx that should be first frameof + * the burst but it is not. +*/ +#define LIF_INT_STATUS_INTFROUTOFALIGNSTAT_MASK 0x80 + +/* + * [FATAL] LIF detects a grant start time that is less than its + * currenttimer. +*/ +#define LIF_INT_STATUS_INTGRNTSTARTTIMELAGSTAT_MASK 0x40 + +/* [NON-FATAL] LIF had to abort frames due to misalignment. */ +#define LIF_INT_STATUS_INTABORTRXFRMSTAT_MASK 0x20 + +/* [NON-FATAL] LIF detects an idle condition for received clock. */ +#define LIF_INT_STATUS_INTNORXCLKSTAT_MASK 0x10 + +/* + * [NON-FATAL] Lif detects a runaway frame. + * LIF could not detect an endof frame character for 64K clocks. +*/ +#define LIF_INT_STATUS_INTRXMAXLENERRSTAT_MASK 0x8 + +/* + * [NON-FATAL] LIF detects code error after it has successfullyacquired + * sync. +*/ +#define LIF_INT_STATUS_INTRXERRAFTALIGNSTAT_MASK 0x4 + +/* [NON-FATAL] LIF is successfully acquired sync. */ +#define LIF_INT_STATUS_INTRXSYNCHACQSTAT_MASK 0x2 + +/* + * [NON-FATAL] LIF is out of sync. + * This condition indicates that theLIF could not align to IDLE characters + * or it detects code errors. +*/ +#define LIF_INT_STATUS_INTRXOUTOFSYNCHSTAT_MASK 0x1 + + +/* + * Register + * + * This register contains interrupt masks for LIF modules. + */ +#define LIF_INT_MASK_REG 0x18 + +/* + * [NON-FATAL]Mask for int_sop_sfec_ipg_violation interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INT_SOP_SFEC_IPG_VIOLATION_MASK_MASK 0x200000 + +/* Mask. */ +#define LIF_INT_MASK_LASERONMAXMASK_MASK 0x100000 + +/* Mask. */ +#define LIF_INT_MASK_LASEROFFMASK_MASK 0x80000 + +/* Mask for replay protection abort interrupt */ +#define LIF_INT_MASK_SECDNREPLAYPROTCTABORTMSK_MASK 0x40000 + +/* Mask for packet number overflow interrupt */ +#define LIF_INT_MASK_SECUPPKTNUMOVERFLOWMSK_MASK 0x20000 + +/* + * Mask for laserOffDurBurstMask interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTLASEROFFDURBURSTMASK_MASK 0x10000 + +/* + * Mask for rxBerThreshExc interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXBERTHRESHEXCMASK_MASK 0x8000 + +/* + * Mask for fecRxFrmRecv interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECRXFECRECVMASK_MASK 0x4000 + +/* + * Mask for fecCorrErrFifFullMask interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECRXCORERRFIFOFULLMASK_MASK 0x2000 + +/* + * Mask for FecRxCorErrFifoUnExpEmpty interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECRXCORERRFIFOUNEXPEMPTYMASK_MASK 0x1000 + +/* + * Mask for fecBufPopEmptyPush interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECBUFPOPEMPTYPUSHMASK_MASK 0x800 + +/* + * Mask for fecBufPopEmptyNoPush interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECBUFPOPEMPTYNOPUSHMASK_MASK 0x400 + +/* + * Mask for fecBufPushFull interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECBUFPUSHFULLMASK_MASK 0x200 + +/* + * Mask for upTimeFullUpdStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTUPTIMEFULLUPDMASK_MASK 0x100 + +/* + * Mask for frmOutOfAlignStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFROUTOFALIGNMASK_MASK 0x80 + +/* + * Mask for grntStartTimeLagStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTGRNTSTARTTIMELAGMASK_MASK 0x40 + +/* + * Mask for rxFrmAbortStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTABORTRXFRMMASK_MASK 0x20 + +/* + * Mask for noRxClkStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTNORXCLKMASK_MASK 0x10 + +/* + * Mask for noRxClkStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXMAXLENERRMASK_MASK 0x8 + +/* + * Mask for rxErrAftAlignStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXERRAFTALIGNMASK_MASK 0x4 + +/* + * Mask for rxSynchAcqStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXSYNCHACQMASK_MASK 0x2 + +/* + * Mask for rxOutOfSyncStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXOUTOFSYNCHMASK_MASK 0x1 + + +/* + * Register + * + * This set of registers allows reading the LIF per-LLID statistics. + * Italso allows general access to the LIF internal RAMs. + * All RAMs areinitialized to zero upon hardware reset. + * The following describes dataport read/write sequences: + * Write cycle: + * 1) Write the address of the RAM entry to Offset 1. + * 2) Write data to be written to Offsets 2 through 5 (as requiredfor the + * given RAM's width). + * 3) Write to Offset 0 to select the RAM and to indicate Writecycle. + * 4) Poll on Offset 0 until the dataPortBusy bit is cleared. + * Read cycle: + * 1) Write the address of the RAM entry to Offset 1. + * 2) Write to Offset 0 to select the RAM and to indicate Read cycle. + * 3) Poll on Offset 0 until the dataPortBusy bit is cleared. + * 4) Read Offsets 2 through 5 (as needed according to the width ofthe + * accessed RAM) to retrieve the RAM read data. + * The following paragraphs describe the port data format for each RAM: + * Statistics Downstream Per LLID - Stores the statistics information + * foreach downstream LLID (32 bidirectional). + * The memory is auto-initialized within the hardware, and can be + * accessedas soon as the module is brought out of reset. + * The statistics arecleared on read. + * portData0[31: + * 0] - Desired statisticLLID Index RAM LocationsBidirectional 0 0 - + * 15Bidirectional 1 16 - 31. + * .. + * Bidirectional 30 480-495Bidirectional 31 496-511Table: + * RAM Offset Description Remarks0 Bidir Downstream Good Frames Received + * Not Aborted Prior toFEC1 Bidir Downstream Good Bytes Received Not + * Aborted Prior toFEC2 Bidir Downstream Oversized Frames As defined by + * LIFSanitizer Register (0x134)3 Bidir Downstream NonFEC Good Frames + * Received NonFEC Framesregardless of FEC Enable4 Bidir Downstream NonFEC + * Good Bytes Received NonFEC Bytesregardless of FEC Enable5 Bidir + * Downstream FEC Good Frames Received Will incrementeven if FEC is + * disabled. + * 6 Bidir Downstream FEC Good Bytes Received Will incrementeven if FEC is + * disabled. + * 7 Bidir Downstream FEC Frames Exceeded Error Threshold8 Bidir Downstream + * FEC Data Blocks No Errors9 Bidir Downstream FEC Data Blocks Corrected10 + * Bidir Downstream FEC Data Blocks Uncorrected11 Bidir Downstream FEC Data + * Corrected Bytes12 Bidir Downstream FEC Data Corrected Zeroes13 Bidir + * Downstream FEC Data Corrected Ones14 Bidir Downstream Undersized + * Frames15 Bidir Downstream Errored FramesSEC Downstream Key RAM - + * specifies the security key. + * When writing tothe key RAM, the mode and encryption key MUST be + * specified. + * All keysmust be written to EVEN offsets. + * For LLID X, the corresponding RAMoffset for the even key is X*2, while + * the odd key is (X*2) + 1. + * CEPON encryption mode: + * portData0 - Specifies input to 1st churning key generation. + * Bits [15: + * 0] specify P16 - P1; and bits [23: + * 16] specify X8 - X1. + * portData1 - Specifies input to 2nd churning key generation. + * The input is byte shift of 1st churning key. + * Bits [7: + * 0]specify P16 - P8; bits [15: + * 8] specify X8 - X1; andbits [23: + * 16] specify P7 - P1. + * portData2 - Specifies input to 3rd churning key generation. + * The input is byte shift of 2nd churning key. + * Bits [7: + * 0] specify X8 -X1; and bits [23: + * 8] specify P16 - P1. + * portData3 - Specifies P-input to churning function. + * Bits [15: + * 0]specify P16 - P1. + * Same data as portData0. + * Broadcom and NTT encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * 802. + * 1ae encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits implicit SCIportData5 - Specifies bits [127: + * 64] of the 64-bits implicit SCIportData6 - Specifies bits [31: + * 64] of the initial packet number forreplay protection. + * portData7[9] - encryption enable. + * When cleared, 802. + * 1ae packets willpass through undecrypted. + * Zero-ovehead encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits implicit SCIportData5 - Specifies bits [127: + * 64] of the 64-bits implicit SCIportData6 - Specifies bits [31: + * 64] of the initial packet number forreplay protection. + * SEC Upstream Key RAM - specifies the security key. + * When writing to thekey RAM, the mode and encryption key MUST be + * specified. + * Each LLIDoccupies 2 entries (N and N+1), ie. + * LLID Index 0 corresponds to entries0 and 1, while LLID Index 1 + * corresponds to entries 2 and 3. + * Controlinformation via portData4 will need to be conveyed to indicate to + * theSEC Receiver (OLT 1G RX) which key (0/1) will need to be loaded. + * Broadcom and NTT encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData7[8] - key number. + * portData7[9] - encryption enable. + * 802. + * 1ae encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits explicit SCI. + * portData5 - Specifies bits [127: + * 64] of the 64-bits explicit SCI. + * portData6 - Specifies bits [31: + * 64] of the initial packet number. + * portData7[7: + * 0] - TCI[7: + * 0]TCI[1: + * 0] - key number. + * In PON mode, only TCI[0] is utilized foreven/odd key. + * Must match key number specified in portData7[8]. + * In P2Pmode, TCI[1: + * 0]specifies 1 of 4 keys. + * TCI[3: + * 2] - encryption mode bits : + * TCI[3] - E encryption bit; TCI[2] -C change bit. + * - E=0; C=0 : + * Authentication only. + * Data is not encryption. + * Only ICV is inserted at the end of packet. + * - E=0; C=1 : + * Reserved. + * - E=1; C=0 : + * Reserved. + * - E=1; C=1 : + * Encryption/authentication. + * Data is encryptedand ICV inserted. + * TCI[4] - single copy broadcast. + * Set to 0. + * TCI[5] - SC specifies whether SecTag's SCI isimplicit(0)/explicit(1). + * TCI[6] - ES end station byte. + * Set to 0. + * TCI[7] - V version number. + * Set to 0. + * portData7[8] - key number. + * portData7[9] - encryption enable. + * Zero-ovehead encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits implicit SCI. + * portData5 - Specifies bits [127: + * 64] of the 64-bits implicit SCI. + * portData6 - Specifies bits [31: + * 64] of the initial packet number. + * portData7[8] - key number. + * portData7[9] - encryption enable. + */ +#define LIF_DATA_PORT_COMMAND_REG 0x1c + +/* + * Indicates access to RAM is in progress. + * 0: + * Data port is ready to accept a command1: + * Data port is busy +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_BUSY_MASK 0x80000000 + +/* + * 0 = Previous Data Port Operation Successful1 = Previous Data Port + * Operation Failed +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_ERROR_MASK 0x40000000 + +/* + * Selects the internal RAM for access: + * 0: + * Downstream Statistics (per-LLID)(256 x 32 bits)1: + * SEC Downstream Key (64 x 225 bits)2: + * FEC Downstream Data (2048 x 20 bits)*3: + * SEC Upstream Key (32 x 234 bits)5: + * FEC Downstream Partial Syndrome (16 x 136 bits)*6: + * FEC Downstream Full Syndrome (16 x 136 bits) *7: + * FEC Upstream Parity (16 x 128)*See LIF Data Port Data register for bit + * descriptions of these RAMs. + * * Module level resets must be active to access these rams. +*/ +#define LIF_DATA_PORT_COMMAND_RAM_SELECT_SHIFT 24 +#define LIF_DATA_PORT_COMMAND_RAM_SELECT_MASK 0x3f000000 + +/* + * Specifies RAM read or write operation. + * 0: + * Read1: + * Write2-255: + * NO OP +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_OP_CODE_SHIFT 16 +#define LIF_DATA_PORT_COMMAND_DATA_PORT_OP_CODE_MASK 0xff0000 + +/* + * Specifies the RAM address for the port operation. + * Note: + * This field is also used by the LIF memory initializationlogic, so it has + * a non-zero value after reset. + * Default: + * 0xffff +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_ADDR_SHIFT 0 +#define LIF_DATA_PORT_COMMAND_DATA_PORT_ADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 7 ] + * + */ +#define LIF_DATA_PORT_DATA_REG(x) (0x20 + (x) * 0x4) + +/* + * For write operations, the data to be written to the RAM location. + * For read operations, the data read back from the RAM location. +*/ +#define LIF_DATA_PORT_DATA_PBIPORTDATA_SHIFT 0 +#define LIF_DATA_PORT_DATA_PBIPORTDATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_0_7_REG(x) (0x40 + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 0. + * In downstream P2P, 802. + * 1ae mode, registersLIF_P2P_AE_SCI_LO[0: + * 15]/LIF_P2P_AE_SCI_HI[0: + * 15]provide lookup with packet's explicit SCI to an index. +*/ +#define LIF_LLIDx_0_7_CFGLLID0_SHIFT 0 +#define LIF_LLIDx_0_7_CFGLLID0_MASK 0x1ffff + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_16_23_REG(x) (0x60 + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 16. +*/ +#define LIF_LLIDx_16_23_CFGLLID16_SHIFT 0 +#define LIF_LLIDx_16_23_CFGLLID16_MASK 0x1ffff + + +/* + * Register + * + * This register provides programmable parameters for dynamic updates tothe + * MPCP timer. + */ +#define LIF_TIME_REF_CNT_REG 0x80 + +/* + * If the (absolute) difference between the timestamp received in aGATE + * message and the MPCP timer is larger than this value, then afull update" + * occurs: + * the downstream timestamp is transferred intothe MPCP timer. + * Default: + * 0x20 +*/ +#define LIF_TIME_REF_CNT_CFFULLUPDATEVALUE_SHIFT 16 +#define LIF_TIME_REF_CNT_CFFULLUPDATEVALUE_MASK 0xff0000 + +/* + * If the difference between the timestamp received in a GATE messageand + * the MPCP timer is negative AND larger than this value (but notlarger + * than cfFullUpdate) then the MPCP timer is held for one TQ(effectively + * decrementing it). + * Default: + * 0x2 +*/ +#define LIF_TIME_REF_CNT_CFMAXNEGVALUE_SHIFT 8 +#define LIF_TIME_REF_CNT_CFMAXNEGVALUE_MASK 0xff00 + +/* + * If the difference between the timestamp received in a GATE messageand + * the MPCP timer is positive AND larger than this value (but notlarger + * than cfFullUpdate) then the MPCP timer is incremented by twoTQ. + * Default: + * 0x4 +*/ +#define LIF_TIME_REF_CNT_CFMAXPOSVALUE_SHIFT 0 +#define LIF_TIME_REF_CNT_CFMAXPOSVALUE_MASK 0xff + + +/* + * Register + * + * This register provides the LIF the ability to filter MPCP + * timecorrections when the EPON MAC requests them too frequently. + * Thisregister specifies a time period after an update during which the + * LIFwill ignore MPCP time corrections from EPN. + */ +#define LIF_TIMESTAMP_UPD_PER_REG 0x84 + +/* + * Time period after an MPCP time correction during which LIF + * ignoresfurther MPCP time corrections. + * The units are TQ. +*/ +#define LIF_TIMESTAMP_UPD_PER_CFTIMESTAMPUPDPER_SHIFT 0 +#define LIF_TIMESTAMP_UPD_PER_CFTIMESTAMPUPDPER_MASK 0xffff + + +/* + * Register + * + * The one pulse per second signal is asserted when the local MPCP + * timeincrements past the value programmed in cfTransportTime. + * Software mustupdate this register once per second. + */ +#define LIF_TP_TIME_REG 0x88 + +/* MPCP time at which the pulse per second output will be asserted. */ +#define LIF_TP_TIME_CFTRANSPORTTIME_SHIFT 0 +#define LIF_TP_TIME_CFTRANSPORTTIME_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides the receive MPCP time of the most recently received + * downstreampacket. + * It is updated only when a downstream packet is received. + */ +#define LIF_MPCP_TIME_REG 0x8c + +/* Provides the least significant 32 bits of the receive time. */ +#define LIF_MPCP_TIME_LTMPCPTIME_SHIFT 0 +#define LIF_MPCP_TIME_LTMPCPTIME_MASK 0xffffffff + + +/* + * Register + * + * Max Length setting for the receive sanitizer. + * The sanitizer ensuresthat frames entering latter LIF receive logic are + * truncated to auseable size. + */ +#define LIF_MAXLEN_CTR_REG 0x90 + +/* + * Approximately the maximum number of double words which the frame + * cancontain before being truncated by the LIF Sanitizer circuit. + * Thedefault of 1005 corresponds to a frame length of 2000 bytes. + * Default: + * 1005 +*/ +#define LIF_MAXLEN_CTR_CFRXMAXFRAMELENGTH_SHIFT 0 +#define LIF_MAXLEN_CTR_CFRXMAXFRAMELENGTH_MASK 0x3fff + + +/* + * Register + * + * Specifies an offset, before or after the grant start time, to turn onthe + * laser. + * Units are double-octet words. + */ +#define LIF_LASER_ON_DELTA_REG 0x94 + +/* + * [11: + * 0] Offset (+/-) from Grant Start time to turn laser on[12] 0: + * Positive value: + * turn on laser after the grant start time. + * 1: + * Negative value: + * turn on laser prior to the grant starttime +*/ +#define LIF_LASER_ON_DELTA_CFTXLASERONDELTA_SHIFT 0 +#define LIF_LASER_ON_DELTA_CFTXLASERONDELTA_MASK 0x1fff + + +/* + * Register + * + * Defines when to turn the laser off and the number of IDLE characters + * totransmit at the beginning of a grant of nonFEC frames. + * Units aredouble-octet words (TQ). + */ +#define LIF_LASER_OFF_IDLE_REG 0x98 + +/* + * A period during which the LIF transmits idle characters before + * thetransmission burst of non-FEC frames. +*/ +#define LIF_LASER_OFF_IDLE_CFTXINITIDLE_SHIFT 16 +#define LIF_LASER_OFF_IDLE_CFTXINITIDLE_MASK 0xffff0000 + +/* + * [6: + * 0] Offset (+/-) from Grant End time at which to turn laser off[7]: + * 0: + * Positive value: + * turn off laser after end of grant slot. + * 1: + * Negative value: + * turn off laser before end of grant slot. +*/ +#define LIF_LASER_OFF_IDLE_CFTXLASEROFFDELTA_SHIFT 0 +#define LIF_LASER_OFF_IDLE_CFTXLASEROFFDELTA_MASK 0xff + + +/* + * Register + * + * Defines the number of IDLE characters to transmit at the beginning of + * agrant of FEC frames. + * Units are double-octet words (TQ). + */ +#define LIF_FEC_INIT_IDLE_REG 0x9c + +/* + * A period during which the LIF transmits idle characters before + * thetransmission burst of FEC frames. +*/ +#define LIF_FEC_INIT_IDLE_CFTXFECINITIDLE_SHIFT 0 +#define LIF_FEC_INIT_IDLE_CFTXFECINITIDLE_MASK 0xffff + + +/* + * Register + * + * Allowed hamming distance between received SFEC/TFEC and referencevalue. + */ +#define LIF_FEC_ERR_ALLOW_REG 0xa0 + +/* + * The number of bit error allow for TFEC detection. + * Default : + * 0x5 +*/ +#define LIF_FEC_ERR_ALLOW_CFRXTFECBITERRALLOW_SHIFT 4 +#define LIF_FEC_ERR_ALLOW_CFRXTFECBITERRALLOW_MASK 0xf0 + +/* + * The number of bit error allow for SFEC detection. + * Default : + * 0x5 +*/ +#define LIF_FEC_ERR_ALLOW_CFRXSFECBITERRALLOW_SHIFT 0 +#define LIF_FEC_ERR_ALLOW_CFRXSFECBITERRALLOW_MASK 0xf + + +/* + * Register - read-only + * + * This register is a read-only status of the last downstream key + * selectedon the 32 downstream LLIDs. + * This register allows for software to detecta key switchover or to + * determine the current downstream key. + */ +#define LIF_SEC_KEY_SEL_REG 0xa4 + +/* + * [31: + * 0] Key select status for bidirectional LLIDs; bitwise encodedper LLID + * index +*/ +#define LIF_SEC_KEY_SEL_KEYSEL_SHIFT 0 +#define LIF_SEC_KEY_SEL_KEYSEL_MASK 0xffffffff + + +/* + * Register + * + * Provides per-LLID status of downstream encryption. + * Clear a bit (disable encryption on an LLID) by writing 1 to it. + */ +#define LIF_DN_ENCRYPT_STAT_REG 0xa8 + +/* + * Provides the status of the current encryption mode for each LLID. + * InEPON mode (and with bit enEpnMixEncryption set in the LIF + * ControlRegister) encryption for an LLID can be disabled only by writing + * "1to the appropriate bit in this register. + * 0: + * Encryption disabled1: + * Encryption enabledBitwise encoded per LLID index. +*/ +#define LIF_DN_ENCRYPT_STAT_ENENCRYPT_SHIFT 0 +#define LIF_DN_ENCRYPT_STAT_ENENCRYPT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides per-LLID status of upstream security key. + */ +#define LIF_SEC_UP_KEY_STAT_REG 0xac + +/* + * Provides current active key for upstream LLIDs. + * Bitwise encoded perLLID index. +*/ +#define LIF_SEC_UP_KEY_STAT_KEYUPSEL_SHIFT 0 +#define LIF_SEC_UP_KEY_STAT_KEYUPSEL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides per-LLID status of upstream security. + */ +#define LIF_SEC_UP_ENCRYPT_STAT_REG 0xb0 + +/* + * Provides per-LLID status of the current upstream encryption mode. + * 0: + * Encryption disabled1: + * Encryption enabledBitwise encoded per LLID index. +*/ +#define LIF_SEC_UP_ENCRYPT_STAT_ENUPENCRYPT_SHIFT 0 +#define LIF_SEC_UP_ENCRYPT_STAT_ENUPENCRYPT_MASK 0xffffffff + + +/* + * Register + * + * Provides MPCP correction for EPON encryption. + */ +#define LIF_SEC_UP_MPCP_OFFSET_REG 0xb4 + +/* Provides MPCP offset correction. */ +#define LIF_SEC_UP_MPCP_OFFSET_SECUPMPCPOFFSET_SHIFT 0 +#define LIF_SEC_UP_MPCP_OFFSET_SECUPMPCPOFFSET_MASK 0xffffffff + + +/* + * Register + * + * Provides upstream per LLID FEC enabling. + */ +#define LIF_FEC_PER_LLID_REG 0xb8 + +/* Per-LLID FEC Enable for LLID 0-31. */ +#define LIF_FEC_PER_LLID_CFFECTXFECENLLID_SHIFT 0 +#define LIF_FEC_PER_LLID_CFFECTXFECENLLID_MASK 0xffffffff + + +/* + * Register + * + * Aggregate statistics for the LIF receive channel. + * These registerssaturate at their maximum and clear when read. + * Note: + * These registers are also writable for test/diagnostics purposes. + */ +#define LIF_RX_LINE_CODE_ERR_CNT_REG 0xbc + +/* Counter value. */ +#define LIF_RX_LINE_CODE_ERR_CNT_RXLINECODEERRCNT_SHIFT 0 +#define LIF_RX_LINE_CODE_ERR_CNT_RXLINECODEERRCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_MPCP_FRM_REG 0xc0 + +/* Counter value. */ +#define LIF_RX_AGG_MPCP_FRM_RXAGGMPCPCNT_SHIFT 0 +#define LIF_RX_AGG_MPCP_FRM_RXAGGMPCPCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_GOOD_FRM_REG 0xc4 + +/* Counter value. */ +#define LIF_RX_AGG_GOOD_FRM_RXAGGGOODCNT_SHIFT 0 +#define LIF_RX_AGG_GOOD_FRM_RXAGGGOODCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_GOOD_BYTE_REG 0xc8 + +/* Counter value. */ +#define LIF_RX_AGG_GOOD_BYTE_RXAGGGOODBYTESCNT_SHIFT 0 +#define LIF_RX_AGG_GOOD_BYTE_RXAGGGOODBYTESCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_UNDERSZ_FRM_REG 0xcc + +/* Counter value. */ +#define LIF_RX_AGG_UNDERSZ_FRM_RXAGGUNDERSZCNT_SHIFT 0 +#define LIF_RX_AGG_UNDERSZ_FRM_RXAGGUNDERSZCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_OVERSZ_FRM_REG 0xd0 + +/* Counter value. */ +#define LIF_RX_AGG_OVERSZ_FRM_RXAGGOVERSZCNT_SHIFT 0 +#define LIF_RX_AGG_OVERSZ_FRM_RXAGGOVERSZCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_CRC8_FRM_REG 0xd4 + +/* Counter value. */ +#define LIF_RX_AGG_CRC8_FRM_RXAGGCRC8ERRCNT_SHIFT 0 +#define LIF_RX_AGG_CRC8_FRM_RXAGGCRC8ERRCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_FEC_FRM_REG 0xd8 + +/* Counter value. */ +#define LIF_RX_AGG_FEC_FRM_RXAGGFEC_SHIFT 0 +#define LIF_RX_AGG_FEC_FRM_RXAGGFEC_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_FEC_BYTE_REG 0xdc + +/* Counter value. */ +#define LIF_RX_AGG_FEC_BYTE_RXAGGFECBYTES_SHIFT 0 +#define LIF_RX_AGG_FEC_BYTE_RXAGGFECBYTES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_FEC_EXC_ERR_FRM_REG 0xe0 + +/* Counter value. */ +#define LIF_RX_AGG_FEC_EXC_ERR_FRM_RXAGGFECEXCEEDERRS_SHIFT 0 +#define LIF_RX_AGG_FEC_EXC_ERR_FRM_RXAGGFECEXCEEDERRS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_NONFEC_GOOD_FRM_REG 0xe4 + +/* Counter value. */ +#define LIF_RX_AGG_NONFEC_GOOD_FRM_RXAGGNONFECGOOD_SHIFT 0 +#define LIF_RX_AGG_NONFEC_GOOD_FRM_RXAGGNONFECGOOD_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_NONFEC_GOOD_BYTE_REG 0xe8 + +/* Counter value. */ +#define LIF_RX_AGG_NONFEC_GOOD_BYTE_RXAGGNONFECGOODBYTES_SHIFT 0 +#define LIF_RX_AGG_NONFEC_GOOD_BYTE_RXAGGNONFECGOODBYTES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_BYTES_REG 0xec + +/* Counter value. */ +#define LIF_RX_AGG_ERR_BYTES_RXAGGERRBYTES_SHIFT 0 +#define LIF_RX_AGG_ERR_BYTES_RXAGGERRBYTES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_ZEROES_REG 0xf0 + +/* Counter value. */ +#define LIF_RX_AGG_ERR_ZEROES_RXAGGERRZEROES_SHIFT 0 +#define LIF_RX_AGG_ERR_ZEROES_RXAGGERRZEROES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_NO_ERR_BLKS_REG 0xf4 + +/* Counter value. */ +#define LIF_RX_AGG_NO_ERR_BLKS_RXAGGNOERRBLKS_SHIFT 0 +#define LIF_RX_AGG_NO_ERR_BLKS_RXAGGNOERRBLKS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_COR_BLKS_REG 0xf8 + +/* Counter value. */ +#define LIF_RX_AGG_COR_BLKS_RXAGGCORRBLKS_SHIFT 0 +#define LIF_RX_AGG_COR_BLKS_RXAGGCORRBLKS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_UNCOR_BLKS_REG 0xfc + +/* Counter value. */ +#define LIF_RX_AGG_UNCOR_BLKS_RXAGGUNCORRBLKS_SHIFT 0 +#define LIF_RX_AGG_UNCOR_BLKS_RXAGGUNCORRBLKS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_ONES_REG 0x100 + +/* Counter value. */ +#define LIF_RX_AGG_ERR_ONES_RXAGGERRONES_SHIFT 0 +#define LIF_RX_AGG_ERR_ONES_RXAGGERRONES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_FRM_REG 0x104 + +/* Counter value. */ +#define LIF_RX_AGG_ERR_FRM_RXAGGERROREDCNT_SHIFT 0 +#define LIF_RX_AGG_ERR_FRM_RXAGGERROREDCNT_MASK 0xffffffff + + +/* + * Register + * + * Aggregate statistics for the LIF transmit channel. + * These registerssaturate at their maximum value and clear when read. + * Note: + * These registers are also writable for test/diagnostics purposes. + */ +#define LIF_TX_PKT_CNT_REG 0x108 + +/* Counter value. */ +#define LIF_TX_PKT_CNT_TXFRAMECNT_SHIFT 0 +#define LIF_TX_PKT_CNT_TXFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_BYTE_CNT_REG 0x10c + +/* Counter value. */ +#define LIF_TX_BYTE_CNT_TXBYTECNT_SHIFT 0 +#define LIF_TX_BYTE_CNT_TXBYTECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_NON_FEC_PKT_CNT_REG 0x110 + +/* Counter value. */ +#define LIF_TX_NON_FEC_PKT_CNT_TXNONFECFRAMECNT_SHIFT 0 +#define LIF_TX_NON_FEC_PKT_CNT_TXNONFECFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_NON_FEC_BYTE_CNT_REG 0x114 + +/* Counter value. */ +#define LIF_TX_NON_FEC_BYTE_CNT_TXNONFECBYTECNT_SHIFT 0 +#define LIF_TX_NON_FEC_BYTE_CNT_TXNONFECBYTECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_FEC_PKT_CNT_REG 0x118 + +/* Counter value. */ +#define LIF_TX_FEC_PKT_CNT_TXFECFRAMECNT_SHIFT 0 +#define LIF_TX_FEC_PKT_CNT_TXFECFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + * Count of FEC bytes transmitted by Line-Coder. + */ +#define LIF_TX_FEC_BYTE_CNT_REG 0x11c + +/* Counter value. */ +#define LIF_TX_FEC_BYTE_CNT_TXFECBYTECNT_SHIFT 0 +#define LIF_TX_FEC_BYTE_CNT_TXFECBYTECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_FEC_BLK_CNT_REG 0x120 + +/* Counter value. */ +#define LIF_TX_FEC_BLK_CNT_TXFECBLKSCNT_SHIFT 0 +#define LIF_TX_FEC_BLK_CNT_TXFECBLKSCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_MPCP_PKT_CNT_REG 0x124 + +/* Counter value. */ +#define LIF_TX_MPCP_PKT_CNT_TXMPCPFRAMECNT_SHIFT 0 +#define LIF_TX_MPCP_PKT_CNT_TXMPCPFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + * Count of transmitted frames. + * For debug. + */ +#define LIF_DEBUG_TX_DATA_PKT_CNT_REG 0x128 + +/* Counter value. */ +#define LIF_DEBUG_TX_DATA_PKT_CNT_TXDATAFRAMECNT_SHIFT 0 +#define LIF_DEBUG_TX_DATA_PKT_CNT_TXDATAFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + * Provides sticky status of which LLIDs have received FEC-encoded frames. + * Status is provided bitwise per-LLID; each status bit can be cleared + * bywriting 1 to it. + */ +#define LIF_FEC_LLID_STATUS_REG 0x12c + +/* + * [31: + * 0] stkyFecFecvLlid Per-LLID FEC receive status forbidirectional LLIDs. + * 0: + * No FEC frames detected1: + * FEC frame reception detected +*/ +#define LIF_FEC_LLID_STATUS_STKYFECREVCLLIDBMSK_SHIFT 0 +#define LIF_FEC_LLID_STATUS_STKYFECREVCLLIDBMSK_MASK 0xffffffff + + +/* + * Register + * + * Provides a programmable LLID field that will allow for theinitialization + * vector (in TEK mode only) belonging to non-Raman framesto be preserved + * across Raman frames. + */ +#define LIF_SEC_RX_TEK_IG_IV_LLID_REG 0x130 + +/* + * [15: + * 0] cfIgIvNullLlid Program with the 16 bit LLID of theRaman generated + * random frames. + * [16] cfIgIvNullLlidEn Enable Ignore LLID functionality. +*/ +#define LIF_SEC_RX_TEK_IG_IV_LLID_CFIGIVNULLLLID_SHIFT 0 +#define LIF_SEC_RX_TEK_IG_IV_LLID_CFIGIVNULLLLID_MASK 0x1ffff + + +/* + * Register + * + * Provides control for determining when to assert an interrupt when + * adefined number of programmable errors are observed within a + * definedwindow of time. + * These parameters directly control the behavior ofintRxBerThreshExc. + */ +#define LIF_PON_BER_INTERV_THRESH_REG 0x134 + +/* + * Programmable interval of time. + * Units are in 16 ns increments, for amaximum of 1 ms. +*/ +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERINTERVAL_SHIFT 15 +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERINTERVAL_MASK 0xffff8000 + +/* + * Programmable error threshold. + * Maximum number of errors seen within aprogrammed interval. +*/ +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERTHRESHLD_SHIFT 2 +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERTHRESHLD_MASK 0x7ffc + +/* + * 0: + * Disabled1: + * Count Line Code Errors2: + * Count Corrected Symbols3: + * Count Uncorrectable Blocks (9 symbol errors) +*/ +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERCNTRL_SHIFT 0 +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERCNTRL_MASK 0x3 + + +/* + * Register + * + * Provides control over the laser monitor. + */ +#define LIF_LSR_MON_A_CTRL_REG 0x138 + +/* Provides status of laser enable, directly from the I/O pin inputstage. */ +#define LIF_LSR_MON_A_CTRL_IOPBILASERENS1A_MASK 0x20 + +/* + * Laser monitor polarity. + * 0 - active low; 1 - active high. +*/ +#define LIF_LSR_MON_A_CTRL_CFGLSRMONACTHI_MASK 0x10 + +/* + * Main reset for laser monitor. + * 0: + * Reset1: + * Normal operation +*/ +#define LIF_LSR_MON_A_CTRL_PBILASERMONRSTA_N_PRE_MASK 0x1 + + +/* + * Register + * + * Defines a threshold for the laserOnMaxInt interrupt. + * laserOnMaxIntasserts when the laser enable signal stays active for a + * time greaterthan or equal to the laserOnMaxThresh setting. + * laserOnMaxThresh isexpressed in units of TQ. + * However, be aware that the laser monitoroperates from the core epnClk125 + * clock, so there may be some inaccuracyif the transmitter is running + * loop-timed (i. + * e. + * from the recoveredreceive clock). + * In addition, the laser-on time can jitter by 8 ns (1/2TQ) even for + * non-loop timed applications as the laser monitor on-timecounter may not + * be TQ-aligned so an off-by-one error will occur halfthe time. + */ +#define LIF_LSR_MON_A_MAX_THR_REG 0x13c + +/* + * Specifies the threshold for laserOnMaxInt. + * Units are TQ. + * Default: + * 0x80ffff +*/ +#define LIF_LSR_MON_A_MAX_THR_CFGLASERMONMAXA_SHIFT 0 +#define LIF_LSR_MON_A_MAX_THR_CFGLASERMONMAXA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates the laser-on time of the burst that set laserOffInt (i. + * e. + * thefirst burst which ended while laserOffInt was clear). + * Value is latchedupon assertion of laserOffInt. + */ +#define LIF_LSR_MON_A_BST_LEN_REG 0x140 + +/* Indicates length of most recent burst, in TQ. */ +#define LIF_LSR_MON_A_BST_LEN_LASERONTIMEA_SHIFT 0 +#define LIF_LSR_MON_A_BST_LEN_LASERONTIMEA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the number of bursts (laser-off events) since the last + * LaserMonitor reset or since the last read of this register. + * This registerclears when read. + */ +#define LIF_LSR_MON_A_BST_CNT_REG 0x144 + +/* + * This value increments on the negating edge of laser enable. + * Saturates at 0xffffffff; and clears on read. +*/ +#define LIF_LSR_MON_A_BST_CNT_LASERMONBRSTCNTA_SHIFT 0 +#define LIF_LSR_MON_A_BST_CNT_LASERMONBRSTCNTA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides status of state machines in the PON receive side of the LIF. + */ +#define LIF_DEBUG_PON_SM_REG 0x148 + +/* 10B Alignment State Machine States */ +#define LIF_DEBUG_PON_SM_ALIGNCSQQ_SHIFT 8 +#define LIF_DEBUG_PON_SM_ALIGNCSQQ_MASK 0x3f00 + +/* 8B State Machine States */ +#define LIF_DEBUG_PON_SM_RXFECIFCSQQ_SHIFT 0 +#define LIF_DEBUG_PON_SM_RXFECIFCSQQ_MASK 0x1f + + +/* + * Register - read-only + * + * Provides status of state machines in the FEC receive side of the LIF. + */ +#define LIF_DEBUG_FEC_SM_REG 0x14c + +/* FEC Receive Syndrome States */ +#define LIF_DEBUG_FEC_SM_RXSYNCSQQ_SHIFT 16 +#define LIF_DEBUG_FEC_SM_RXSYNCSQQ_MASK 0x1f0000 + +/* FEC Receive Corrector States */ +#define LIF_DEBUG_FEC_SM_RXCORCS_SHIFT 8 +#define LIF_DEBUG_FEC_SM_RXCORCS_MASK 0x300 + +/* FEC Receive Output States */ +#define LIF_DEBUG_FEC_SM_FECRXOUTCS_SHIFT 0 +#define LIF_DEBUG_FEC_SM_FECRXOUTCS_MASK 0x1f + + +/* + * Register + * + * Provides the tolerance for packet number reception in replay + * protectionmode. + * Only applicable in 802. + * 1ae security mode. + */ +#define LIF_AE_PKTNUM_WINDOW_REG 0x150 + +/* + * In replay protection, the packet number is checked against theexpected + * packet number. + * If it is greater than or equal to, packetwill be accepted. + * Otherwise, it will be discarded. + * This registerprovides the tolerance by subtracting the current expected + * packetnumber by this amount. +*/ +#define LIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_SHIFT 0 +#define LIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_MASK 0xffffffff + + +/* + * Register + * + * Provides the threshold to warn of impending packet number rollover + * ontransmit. + */ +#define LIF_AE_PKTNUM_THRESH_REG 0x154 + +/* Defines the maximum packet number rollover. */ +#define LIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_SHIFT 0 +#define LIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides the status of packet number. + */ +#define LIF_AE_PKTNUM_STAT_REG 0x158 + +/* + * Provides the LLID index whose packet number exceeded the maximumpacket + * number threhsold. +*/ +#define LIF_AE_PKTNUM_STAT_SECUPINDXWTPKTNUMMAX_SHIFT 16 +#define LIF_AE_PKTNUM_STAT_SECUPINDXWTPKTNUMMAX_MASK 0x1f0000 + +/* Provides the LLID index that was aborted due to replay protection. */ +#define LIF_AE_PKTNUM_STAT_SECDNINDXWTPKTNUMABORT_SHIFT 0 +#define LIF_AE_PKTNUM_STAT_SECDNINDXWTPKTNUMABORT_MASK 0x1f + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_8_15_REG(x) (0x15c + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 8. + * In downstream P2P, 802. + * 1ae mode, registersLIF_P2P_AE_SCI_LO[0: + * 15]/LIF_P2P_AE_SCI_HI[0: + * 15]provide lookup with packet's explicit SCI to an index. +*/ +#define LIF_LLIDx_8_15_CFGLLID8_SHIFT 0 +#define LIF_LLIDx_8_15_CFGLLID8_MASK 0x1ffff + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_24_31_REG(x) (0x17c + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 24. +*/ +#define LIF_LLIDx_24_31_CFGLLID24_SHIFT 0 +#define LIF_LLIDx_24_31_CFGLLID24_MASK 0x1ffff + + +/* + * Register + * + * Provides a programmable VLAN type identifier for upstream P2P traffic. + */ +#define LIF_VLAN_TYPE_REG 0x19c + +/* Defines a VLAN type, in addition to 0x8100. */ +#define LIF_VLAN_TYPE_CFGVLANTYPE_SHIFT 0 +#define LIF_VLAN_TYPE_CFGVLANTYPE_MASK 0xffff + + +/* + * Register + * + * Enables SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define LIF_P2P_AE_SCI_EN_REG 0x1a0 + +/* + * Enables SCI lookup, viaLIF_P2P_AE_SCI_LO_[0: + * 15]/LIF_P2P_AE_SCI_HI[0: + * 15] registers. + * Each bitcorresponds to index 0 - 15. +*/ +#define LIF_P2P_AE_SCI_EN_CFGP2PSCIEN_SHIFT 0 +#define LIF_P2P_AE_SCI_EN_CFGP2PSCIEN_MASK 0xffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define LIF_P2P_AE_SCI_LOx_REG(x) (0x1a4 + (x) * 0x8) + +/* + * Defines the lower 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byLIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define LIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_SHIFT 0 +#define LIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define LIF_P2P_AE_SCI_HIx_REG(x) (0x1a8 + (x) * 0x8) + +/* + * Defines the upper 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byLIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define LIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_SHIFT 0 +#define LIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides additon per-LLID status of upstream security key for 802. + * 1aeP2P. + */ +#define LIF_SEC_UP_KEY_STAT_1_REG 0x224 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by LIF_SEC_UP_KEY_STAT. +*/ +#define LIF_SEC_UP_KEY_STAT_1_KEYUPSEL_HI_SHIFT 0 +#define LIF_SEC_UP_KEY_STAT_1_KEYUPSEL_HI_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides addition per-LLID status of downstream security key for802. + * 1ae P2P. + */ +#define LIF_SEC_KEY_SEL_1_REG 0x228 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by LIF_SEC_KEY_SEL. +*/ +#define LIF_SEC_KEY_SEL_1_KEYSEL_HI_SHIFT 0 +#define LIF_SEC_KEY_SEL_1_KEYSEL_HI_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_REG 0x22c + +/* + * Used to pad plain text frames in 802. + * 1AE encryption mode with afixed number of IPG equivalent to theAE + * overhead. + * Overhead B is equivalent to 16TQ or 32 bytes ofpreceding IPG for + * explicit SCI. +*/ +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_B_IDLE_PAD_SHIFT 6 +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_B_IDLE_PAD_MASK 0xfc0 + +/* + * Used to pad plain text frames in 802. + * 1AE encryption mode with afixed number of IPG equivalent to theAE + * overhead. + * Overhead A is equivalent to 12TQ or 24 bytes ofpreceding IPG for + * implicit SCI. +*/ +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_A_IDLE_PAD_SHIFT 0 +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_A_IDLE_PAD_MASK 0x3f + + +/* + * Register + * + * Autonegotiation Configuration + */ +#define LIF_P2P_AUTONEG_CONTROL_REG 0x230 + +/* + * Link Timer to allow link partner time to process current statebefore + * advancing to next stateHW Default is about 33. + * 5 msS/W should set to 0x0fff for 2. + * 0ms timer for SGMII Style Formatting +*/ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_LINKTIMER_SHIFT 16 +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_LINKTIMER_MASK 0xffff0000 + +/* + * Mode Select for Auto Neg0 = CL37 Style (33. + * 5ms link timer)1 = SGMII Style (2. + * 0ms link timer)See LP ability and advertisement registers for format +*/ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_MODE_SEL_MASK 0x4 + +/* + * 0 = Restart Disabled / Completed1 = Trigger RestartH/W will clear to 0 + * when restart occurs. +*/ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_RESTART_MASK 0x2 + +/* 0 = Disable Autonegotiation1 = Enable Autonegotiation */ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_EN_MASK 0x1 + + +/* + * Register - read-only + * + * Autonegotiation Status + */ +#define LIF_P2P_AUTONEG_STATUS_REG 0x234 + +/* + * 0 = Remote Fault Not Detected from Link Partner1 = Remote Fault Detected + * from Link PartnerWill only update after AN process. + * Will reset upon restart. +*/ +#define LIF_P2P_AUTONEG_STATUS_AN_LP_REMOTE_FAULT_MASK 0x4 + +/* + * 0 = No sync after AN complete1 = Sync after AN completeWill only update + * after AN process. + * Will reset upon restart. +*/ +#define LIF_P2P_AUTONEG_STATUS_AN_SYNC_STATUS_MASK 0x2 + +/* + * 0 = Autoneg Not Complete1 = Autoneg CompletedWill only update after AN + * process. + * Will reset upon restart. +*/ +#define LIF_P2P_AUTONEG_STATUS_AN_COMPLETE_MASK 0x1 + + +/* + * Register + * + * Autonegotiation Ability / Config Register of this device + */ +#define LIF_P2P_AUTONEG_ABILITY_CONFIG_REG_REG 0x238 + +/* + * Defines the Autonegotiation Ability / Config Register of this + * devicecf_autoneg_mode_sel = 0 (CL37)Bits[15]: + * NP, Next Page[14]: + * ACK (H/W overwrite)[13]: + * RF2, Remote Fault[12]: + * RF1, Remote Fault[11: + * 9]: + * Reserved[8]: + * PS2, Asymmetric Pause[7]: + * PS1, Symmetric Pause[6]: + * HD, Half Duplex[5]: + * FD, Full Duplex[4: + * 0]: + * Reservedcf_autoneg_mode_sel = 1 (SGMII)Bits[15]: + * Link State (HW Controlled) 1 = Link Up, 0 = Link Down[14]: + * ACK (H/W overwrite)[13]: + * Reserved[12]: + * Duplex mode: + * 1 = Full Duplex, 0 = Half Duplex[11: + * 10]: + * 11 = Reserved, 10 = 1000Mbps, 01 = 100Mbps, 00 = 10 Mbps[9: + * 1]: + * Reserved[0]: + * Set 1 to per SGMII Spec (S/W must set) +*/ +#define LIF_P2P_AUTONEG_ABILITY_CONFIG_REG_CF_LIF_P2P_AE_AUTONEG_CONFIG_ABILITY_SHIFT 0 +#define LIF_P2P_AUTONEG_ABILITY_CONFIG_REG_CF_LIF_P2P_AE_AUTONEG_CONFIG_ABILITY_MASK 0xffff + + +/* + * Register - read-only + * + * Autonegotiation Ability / Config Register of Link Partner + */ +#define LIF_P2P_AUTONEG_LINK_PARTNER_ABILITY_CONFIG_READ_REG 0x23c + +/* + * Defines the Autonegotiation Ability / Config Register of LINKPARTNEROnly + * updates when AN is completecf_autoneg_mode_sel = 0 (CL37)Bits[15]: + * NP, Next Page[14]: + * ACK (H/W overwrite)[13]: + * RF2, Remote Fault[12]: + * RF1, Remote Fault[11: + * 9]: + * Reserved[8]: + * PS2, Asymmetric Pause[7]: + * PS1, Symmetric Pause[6]: + * HD, Half Duplex[5]: + * FD, Full Duplex[4: + * 0]: + * Reservedcf_autoneg_mode_sel = 1 (SGMII)Bits[15]: + * Link State (HW Controlled) 1 = Link Up, 0 = Link Down[14]: + * ACK (H/W overwrite)[13]: + * Reserved[12]: + * Duplex mode: + * 1 = Full Duplex, 0 = Half Duplex[11: + * 10]: + * 11 = Reserved, 10 = 1000Mbps, 01 = 100Mbps, 00 = 10 Mbps[9: + * 1]: + * Reserved[0]: + * Set 1 to per SGMII Spec (S/W must set) +*/ +#define LIF_P2P_AUTONEG_LINK_PARTNER_ABILITY_CONFIG_READ_CF_LIF_P2P_AE_AUTONEG_LP_ABILITY_READ_SHIFT 0 +#define LIF_P2P_AUTONEG_LINK_PARTNER_ABILITY_CONFIG_READ_CF_LIF_P2P_AE_AUTONEG_LP_ABILITY_READ_MASK 0xffff + + +#endif /* ! EPON_LIF_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_nco_addr.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_nco_addr.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_nco_addr.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_nco_addr.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,309 @@ +#ifndef EPON_NCO_ADDR_H_ +#define EPON_NCO_ADDR_H_ + +/* relative to epon */ +#define NCO_ADDR_OFFSET_0 0x2000 + +/* + * Register + * + * This register is used to provision the Numerically ControlledOscillator + * (NCO) function. + */ +#define NCO_ADDR_NCO_CFG_REG 0x0 + +/* + * Bypass the programmable duty cycle when cfgSrcOut is set to 1 or + * 2(direct Lif/Xif pass through). + * Default : + * 1 +*/ +#define NCO_CFG_CFGBYPASS_MASK 0x80 + +/* + * Selects the 10MHz output source0: + * NCO drives 10MHz output1: + * Lif 10MHz drives 10MHz output2: + * Reserved3: + * Reserved +*/ +#define NCO_CFG_CFGSRCOUT10MHZ_SHIFT 5 +#define NCO_CFG_CFGSRCOUT10MHZ_MASK 0x60 + +/* + * Selects the one PPS output source. + * 0: + * NCO drives one PPS output1: + * lifPpsSig drives one PPS output2: + * xifPpsSig drives one PPS output3: + * Output is zeroThe output source should be set to the Lif or Xif input + * until theNCO converges. + * Only then should the NCO output be selected as theone PPS source. +*/ +#define NCO_CFG_CFGSRCOUT_SHIFT 3 +#define NCO_CFG_CFGSRCOUT_MASK 0x18 + +/* + * Selects the input reference source. + * 0: + * NCO "free runs" at 125 MHz core clock. + * 1: + * NCO tracks lifPpsSig2: + * NCO tracks xifPpsSig3: + * Reserved +*/ +#define NCO_CFG_CFGSRCIN_SHIFT 1 +#define NCO_CFG_CFGSRCIN_MASK 0x6 + +/* + * Set this bit to reset the NCO logic. + * Note: + * This does not reset the NCO configuration registers. + * 0: + * Normal NCO operation1: + * Hold the NCO logic in resetDefault: + * 1 +*/ +#define NCO_CFG_CFGNCOCLR_MASK 0x1 + + +/* + * Register + * + * This register is used to detect the presence and synchronization lockof + * the 1PPS signals. + * These bits are sticky; to clear a bit, write 1 to it. + */ +#define NCO_ADDR_NCO_INT_REG 0x4 + +/* + * The NCO has not detected a 1pps input edge within +/-1us of the + * NCOgenerated edge. +*/ +#define NCO_INT_INTNONCOSYNC_MASK 0x4 + +/* No edges of the Xif 1PPS signal have been detected over 2 NCOperiods. */ +#define NCO_INT_INTNOXIFPPS_MASK 0x2 + +/* No edges of the Lif 1PPS signal have been detected over 2 NCOperiods. */ +#define NCO_INT_INTNOLIFPPS_MASK 0x1 + + +/* + * Register + * + * This register is used to mask NCO interrupts. + */ +#define NCO_ADDR_NCO_MSK_REG 0x8 + +/* Mask for intNoNcoSync */ +#define NCO_MSK_INTNONCOSYNCMASK_MASK 0x4 + +/* Mask for intNoXifPps */ +#define NCO_MSK_INTNOXIFPPSMASK_MASK 0x2 + +/* Mask for intNoLifPps */ +#define NCO_MSK_INTNOLIFPPSMASK_MASK 0x1 + + +/* + * Register + * + * This register is used to provision the NCO's one pulse per second(1PPS) + * period. + */ +#define NCO_ADDR_NCO_1PPS_PERIOD_REG 0xc + +/* + * This register sets the period of the 1PPS signal, in units of 100ns. + * Default: + * 10,000,000 +*/ +#define NCO_1PPS_PERIOD_CFG1PPSPERIOD_SHIFT 0 +#define NCO_1PPS_PERIOD_CFG1PPSPERIOD_MASK 0xffffff + + +/* + * Register + * + * This register is used to provision the NCO's 8 KHz period. + */ +#define NCO_ADDR_NCO_8KHZ_PERIOD_REG 0x10 + +/* + * This register sets the period of the 8 KHz signal, in units of 100ns. + * Default: + * 1,250 +*/ +#define NCO_8KHZ_PERIOD_CFG8KHZPERIOD_SHIFT 0 +#define NCO_8KHZ_PERIOD_CFG8KHZPERIOD_MASK 0xffffff + + +/* + * Register + * + * This register is used to provision the NCO's initial period + * integralvalue. + * The reset default is calculated as (8nS/100nS)*(2^32) => 343,597,394 + */ +#define NCO_ADDR_NCO_CENTER_FREQUENCY_REG 0x14 + +/* + * Initial NCO period integralDefault is 343,597,394. + * The NCO Period Count register may be readto align the input frequency + * with the default to speed up lockingtime. +*/ +#define NCO_CENTER_FREQUENCY_CFGNCODEFAULT_SHIFT 0 +#define NCO_CENTER_FREQUENCY_CFGNCODEFAULT_MASK 0xffffffff + + +/* + * Register + * + * This register is used to provision the NCO's integral gain value. + * The provisioned value must be within the range of 15ppm. + * The value is in 0. + * 001 ppb units + */ +#define NCO_ADDR_NCO_INT_GAIN_REG 0x18 + +/* + * NCO integral gain in number of 0. + * 001 ppb quanta. + * The gain may be increased for faster convergence, and then decreasedfor + * increased accuracy and holdover. + * Default is 0x400. +*/ +#define NCO_INT_GAIN_CFGNCOGAIN_SHIFT 0 +#define NCO_INT_GAIN_CFGNCOGAIN_MASK 0xffff + + +/* + * Register + * + * This register is used to provision the NCO's initial period + * integralvalue. + * The reset default is calculated as (8nS/100nS)*(2^32) => 343,597,394 + */ +#define NCO_ADDR_NCO_PRO_GAIN_REG 0x1c + +/* + * NCO proportional gain in number of 0. + * 2 ppb quanta. + * The gain may be increased for faster convergence, and then decreasedfor + * increased accuracy and holdover. + * Default is 0x400 +*/ +#define NCO_PRO_GAIN_CFGNCOPROPGAIN_SHIFT 0 +#define NCO_PRO_GAIN_CFGNCOPROPGAIN_MASK 0xffff + + +/* + * Register - read-only + * + * The value in this register is the NCO's current period integral. + * The value is in xxx units. + * (This value reflects the relationship between the accuracy of + * thereference clock frequency and the accuracy of the 125 MHz core + * clockfrequency. + * The closer this value is to the ideal value calculated for the + * NCOInitial Period Integral Value in register 0x0c5,the closer the core + * 125 MHz frequency error matches the referenceclock's frequency error. + * )Note: + * Once the system has locked to a valid downstream reference andreached + * steady state,the value in this register can be transferred to the "NCO + * InitialPeriod Integral Value" in register 0x0c5. + * This will ensure that the NCO's "hold-over" frequency will closelymatch + * the reference frequency. + */ +#define NCO_ADDR_NCO_CNT_REG 0x20 + +/* Current NCO period integral value. */ +#define NCO_CNT_NCOCNT_SHIFT 0 +#define NCO_CNT_NCOCNT_MASK 0xffffffff + + +/* + * Register + * + * This register is used to set the NCO's 1PPS duty cycle. + * The provisioned value represents the "high time" of the 1PPS signal + * andis in 100 nS units. + */ +#define NCO_ADDR_NCO_1PPS_HALF_REG 0x24 + +/* + * This register sets the portion of the 1PPS period that the signal + * ishigh. + * This value should be set to the duty cycle high %% times + * thecfg1ppsPeriod (e. + * g. + * 10%% * 10,000,000 = 1,000,000). + * Default is 5,000,000 (50%% duty cycle). +*/ +#define NCO_1PPS_HALF_CFG1PPSHALFPERIOD_SHIFT 0 +#define NCO_1PPS_HALF_CFG1PPSHALFPERIOD_MASK 0xffffff + + +/* + * Register + * + * This register is used to provision the NCO's 8 KHz duty cycle. + * The provisioned value represents the "high time" of the 8 KHz signaland + * is in 100 nS units. + */ +#define NCO_ADDR_NCO_8KHZ_HALF_REG 0x28 + +/* + * This register sets the portion of the 8 KHz period that the signalis + * high. + * Reset default is 625 (50/50 duty cycle). +*/ +#define NCO_8KHZ_HALF_CFG8KHZHALFPERIOD_SHIFT 0 +#define NCO_8KHZ_HALF_CFG8KHZHALFPERIOD_MASK 0xffffff + + +/* + * Register - read-only + * + * This register is used to measure the incoming clock period in terms + * ofthe local oscillator. + */ +#define NCO_ADDR_NCO_PERIOD_CNT_REG 0x2c + +/* + * The number of 8ns clocks in one input period. + * This register willread zero until the first period is complete. + * It will be updated on each subsequent period. + * This value may beused to program the NCO default period for faster lock + * time. + * For a 1PPS, the cfgNcoDefault should equal 343,597,394 *125M/periodCnt. +*/ +#define NCO_PERIOD_CNT_PERIODCNT_SHIFT 0 +#define NCO_PERIOD_CNT_PERIODCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This register is used to measure the incoming clock phase error in 8 + * nsunits. + */ +#define NCO_ADDR_NCO_PHS_ERR_CNT_REG 0x30 + +/* + * The number of 8 ns clocks between the ppsNco rising edge and the LIFPPS + * input signal rising edge. + * This is an up/down counter: + * LIF PPS leading represents a positiveerror, and ppsNco input leading + * represents a negative error. + * The error will saturate at 0x7ff on a positive error and 0x800 on + * anegative error. + * This register is updated for each rising edge sample following thefirst + * negative edge of ppsNco at start up. +*/ +#define NCO_PHS_ERR_CNT_NCOPHSERR_SHIFT 0 +#define NCO_PHS_ERR_CNT_NCOPHSERR_MASK 0xfff + + +#endif /* ! EPON_NCO_ADDR_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xif.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xif.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xif.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xif.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,1190 @@ +#ifndef EPON_XIF_H_ +#define EPON_XIF_H_ + +/* relative to epon */ +#define XIF_OFFSET_0 0x2800 + +/* + * Register + * + * XIF control register. + */ +#define XIF_CTL_REG 0x0 + +/* + * Global downstream receive encryption enable : + * 0 - Normal operation;1 - Enable encryption. +*/ +#define XIF_CTL_RXENCRYPTEN_MASK 0x80000000 + +/* + * Disable DA/SA downstream decryption : + * 0 - Normal operation; 1 -Disable DA/SA decryption. +*/ +#define XIF_CTL_CFGDISRXDASAENCRPT_MASK 0x40000000 + +/* + * Downstream receive security mode : + * 0 - Zero overhead; 2 - 802. + * 1ae; 3- 3Churn. +*/ +#define XIF_CTL_RXENCRYPTMODE_SHIFT 28 +#define XIF_CTL_RXENCRYPTMODE_MASK 0x30000000 + +/* + * Global upstream transmit encryption enable : + * 0 - Normal operation;1 - Enable encryption. +*/ +#define XIF_CTL_TXENCRYPTEN_MASK 0x8000000 + +/* + * Disable DA/SA upstream encryption : + * 0 - Normal operation; 1 -Disable DA/SA encryption. +*/ +#define XIF_CTL_CFGDISTXDASAENCRPT_MASK 0x4000000 + +/* + * Upstream transmit security mode : + * 0 - Zero overhead; 2 - 802. + * 1ae. +*/ +#define XIF_CTL_TXENCRYPTMODE_SHIFT 24 +#define XIF_CTL_TXENCRYPTMODE_MASK 0x3000000 + +/* + * Masks MSB of 16 bit raw LLID for Index translation. + * 0: + * Don't mask, look at full 16 bits. + * 1: + * Mask bit[15], map based on [14: + * 0]. +*/ +#define XIF_CTL_CFGLLIDMODEMSK_MASK 0x400000 + +/* + * Enable bad upstream FCS generation : + * 0 - Normal operation; 1 -Enable bad FCS generation of 0's. +*/ +#define XIF_CTL_CFGXPNBADCRC32_MASK 0x200000 + +/* + * Disable Discovery Info field : + * 0 - Normal operation; 1 - DisableDISCOVERY info. +*/ +#define XIF_CTL_CFGDISDISCINFO_MASK 0x100000 + +/* + * Enable PMC loopback : + * 0 - Normal operation; 1 - Loopback. + * NOTAPPLICABLE in ONU since Tx/Rx clocks are not the same clock. +*/ +#define XIF_CTL_CFGPMCTX2RXLPBK_MASK 0x80000 + +/* + * Enable upstream bad CRC8 transmission : + * 0 - Normal operation; 1 -Enable bad CRC8 generation. +*/ +#define XIF_CTL_CFGPMCTXENCRC8BAD_MASK 0x40000 + +/* + * Enable point-2-point mode for downstream and upstream : + * 0 - PON mode. + * Upstream's preamble will be of type 0x55_55_d5_55. + * Downstream expects the same preamble type else packet will beaborted. + * CRC8 checking is configurable by bit "cfgPmcRxEnCrc8Chk". + * 1 - P2P mode. + * Upstream's preamble will be of type 0x55_55_55_55. + * Downstream expects the same preamble type else packet will beaborted. + * CRC8 checking will be disabled. +*/ +#define XIF_CTL_CFGENP2P_MASK 0x20000 + +/* + * All unmapped LLIDs will be redirected and mapped to Index 00: + * Unmapped LLIDs will appear to be unmapped to EPN;1: + * Unmapped LLIs will appear on Index 0 to EPN. + * ", +*/ +#define XIF_CTL_CFGLLIDPROMISCUOUSMODE_MASK 0x10000 + +/* Enable IDLE packet support to prevent upstream underrun. */ +#define XIF_CTL_CFGENIDLEPKTSUP_MASK 0x8000 + +/* + * Enable PMC-RX checking of CRC8 : + * 0 - Disable; 1 - Enable. +*/ +#define XIF_CTL_CFGPMCRXENCRC8CHK_MASK 0x4000 + +/* Enable 1st IDLE packet in a burst to be converted to IDLEs. */ +#define XIF_CTL_CFGEN1STIDLEPKTCONVERT_MASK 0x2000 + +/* + * Enable upstream FEC : + * 0 - no FEC. + * 1 - FEC. +*/ +#define XIF_CTL_CFGFECEN_MASK 0x1000 + +/* Enable legacy receive timestamp update. */ +#define XIF_CTL_CFGLEGACYRCVTSUPD_MASK 0x800 + +/* + * Enable FCS pass through : + * 0 - Modify packet's FCS; 1 - Pass throughwith no FCS modification. + * Feature is only supported in A0. +*/ +#define XIF_CTL_CFGXPNENCRCPASSTHRU_MASK 0x400 + +/* + * Debug function to disable timestamp modification of MPCP packet. + * 0 -Normal Operation; 1 - Disable timestamp modification. +*/ +#define XIF_CTL_CFGXPNDISTIMESTAMPMOD_MASK 0x200 + +/* + * XIF not ready indication due to RAM init : + * 1 - Not ready. + * 0 - Readyfor operation. + * All RAMs are initialized to 0's. +*/ +#define XIF_CTL_XIFNOTRDY_MASK 0x100 + +/* + * Active low reset for RAM data port. + * RAM init starts upondeassertion. + * Bit xifNotRdy is to be polled for completion +*/ +#define XIF_CTL_XIFDTPORTRSTN_MASK 0x80 + +/* + * Reset control for transmit XPN module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_XPNTXRSTN_MASK 0x40 + +/* + * Reset control for transmit PMC module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_PMCTXRSTN_MASK 0x20 + +/* + * Reset control for transmit security module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_SECTXRSTN_MASK 0x10 + +/* + * Disable OAM encryption. + * 0 - Normal Operation. + * 1 - Disable MPCPencryption. +*/ +#define XIF_CTL_CFGDISTXOAMENCRPT_MASK 0x8 + +/* + * Disable MPCP encryption. + * 0 - Normal Operation. + * 1 - Disable MPCPencryption. +*/ +#define XIF_CTL_CFGDISTXMPCPENCRPT_MASK 0x4 + +/* + * Reset control for receive PMC module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_PMCRXRSTN_MASK 0x2 + +/* + * Reset control for receive security module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_SECRXRSTN_MASK 0x1 + + +/* + * Register + * + * Interrupts. + */ +#define XIF_INT_STATUS_REG 0x4 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thereceived packet was aborted due to replay protection. +*/ +#define XIF_INT_STATUS_SECRXRPLYPRTCTABRTINT_MASK 0x80 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thetransmit packet number exceeded the maximum threshold and + * about tooverflow. + * Threshold is programmed in register XIF_AE_PKTNUM_THRESH. +*/ +#define XIF_INT_STATUS_SECTXPKTNUMMAXINT_MASK 0x40 + +/* + * Indicates full MPCP timestamp update due to value greater thanthreshold + * programmed into cfgTsFullUpdThr in register XIF_TS_UPDATE. +*/ +#define XIF_INT_STATUS_TSFULLUPDINT_MASK 0x10 + +/* [FATAL] Indicates request to transmit never got serviced. */ +#define XIF_INT_STATUS_TXHANGINT_MASK 0x8 + +/* + * [FATAL] Indicates scheduled transmit time is negative, relative tothe + * current MPCP time. +*/ +#define XIF_INT_STATUS_NEGTIMEINT_MASK 0x4 + +/* + * [NON-FATAL] Indicates the magnitude of the MPCP timestamp + * updatedexceeded the value programmed into XIF_TS_JITTER_THRESH register. +*/ +#define XIF_INT_STATUS_PMCTSJTTRINT_MASK 0x2 + +/* [FATAL] Indicates SEC-RX output FIFO overflowed. */ +#define XIF_INT_STATUS_SECRXOUTFFOVRFLWINT_MASK 0x1 + + +/* + * Register + * + * Interrupt masks, active low : + * 0 - mask interrupt; 1 - enable interrupt. + */ +#define XIF_INT_MASK_REG 0x8 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKSECRXREPLAYPROTCTABORT_MASK 0x80 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKPKTNUMTHRESHINT_MASK 0x40 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKTSFULLUPDINT_MASK 0x10 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKTXHANGINT_MASK 0x8 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKNEGTIMEINT_MASK 0x4 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKPMCTSJTTRINT_MASK 0x2 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKSECRXOUTFFINT_MASK 0x1 + + +/* + * Register + * + * Provides dataPort read/write access to various RAMs. + */ +#define XIF_PORT_COMMAND_REG 0xc + +/* + * Indicates dataPort access is in progress. + * Bit must be clearedbefore the next dataPort access can be issued. +*/ +#define XIF_PORT_COMMAND_DATAPORTBUSY_MASK 0x80000000 + +/* + * Selects the RAM for access : + * 0 - RX key; 2 - TX key; 4 - RX IV; 5 -TX IV. +*/ +#define XIF_PORT_COMMAND_PORTSELECT_SHIFT 24 +#define XIF_PORT_COMMAND_PORTSELECT_MASK 0x3f000000 + +/* + * Indicates write access : + * 0 - read; 1 - write. +*/ +#define XIF_PORT_COMMAND_PORTOPCODE_SHIFT 16 +#define XIF_PORT_COMMAND_PORTOPCODE_MASK 0xff0000 + +/* Specifies the RAM address for access. */ +#define XIF_PORT_COMMAND_PORTADDRESS_SHIFT 0 +#define XIF_PORT_COMMAND_PORTADDRESS_MASK 0xffff + + +/* + * Registers - is [ 0 => 7 ] + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XIF_PORT_DATA_REG(x) (0x14 + (x) * 0x4) + +/* + * TX/RX SEC key RAM, key[31: + * 0]. +*/ +#define XIF_PORT_DATA_PORTDATA_SHIFT 0 +#define XIF_PORT_DATA_PORTDATA_MASK 0xffffffff + + +/* + * Register + * + * This register specifies the 802. + * 1ae MacSec Ethertype to be insertedinto the packet. + */ +#define XIF_MACSEC_REG 0x34 + +/* Defines the MacSec Ethertype. */ +#define XIF_MACSEC_CFGMACSECETHERTYPE_SHIFT 0 +#define XIF_MACSEC_CFGMACSECETHERTYPE_MASK 0xffff + + +/* + * Register + * + * Specifies the transmit offset, relative to the current MPCP. + */ +#define XIF_XPN_XMT_OFFSET_REG 0x38 + +/* + * Specifies the transmit offset, to account for the delay throughSEC-TX + * and PMC-TX. +*/ +#define XIF_XPN_XMT_OFFSET_CFGXPNXMTOFFSET_SHIFT 0 +#define XIF_XPN_XMT_OFFSET_CFGXPNXMTOFFSET_MASK 0xffff + + +/* + * Register + * + * Specifies the offset to add to MPCP's timestamp. + */ +#define XIF_XPN_TIMESTAMP_OFFSET_REG 0x3c + +/* Debug funtion to add the offset to the regenerated MPCP's timestamp. */ +#define XIF_XPN_TIMESTAMP_OFFSET_CFGXPNMPCPTSOFFSET_SHIFT 0 +#define XIF_XPN_TIMESTAMP_OFFSET_CFGXPNMPCPTSOFFSET_MASK 0xffffffff + + +/* + * Register + * + * This register controls Xif's packet generator. + * When enabled the packetgenerator's frames will be inserted in place of + * the normal downstreamdata. + */ +#define XIF_XPN_PKTGEN_CTL_REG 0x40 + +/* Burst since, in TQ unit. */ +#define XIF_XPN_PKTGEN_CTL_CFGONUBURSTSIZE_SHIFT 16 +#define XIF_XPN_PKTGEN_CTL_CFGONUBURSTSIZE_MASK 0xffff0000 + +/* Enable back-2-back grants for overlap testing. */ +#define XIF_XPN_PKTGEN_CTL_CFGENBCK2BCKPKTGEN_MASK 0x20 + +/* Enable all MPCP packet generation. */ +#define XIF_XPN_PKTGEN_CTL_CFGENALLMPCPPKTGEN_MASK 0x10 + +/* Starts packet generator. */ +#define XIF_XPN_PKTGEN_CTL_CFGXPNSTARTPKTGEN_MASK 0x2 + +/* Enables packet generator. */ +#define XIF_XPN_PKTGEN_CTL_CFGXPNENPKTGEN_MASK 0x1 + + +/* + * Register + * + * Specifies the packet generation LLID for index 0 and 1. + */ +#define XIF_XPN_PKTGEN_LLID_REG 0x44 + +/* LLID for index 1. */ +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID1_SHIFT 16 +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID1_MASK 0xffff0000 + +/* LLID for index 0. */ +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID0_SHIFT 0 +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID0_MASK 0xffff + + +/* + * Register + * + * Specifies the number of packet to transmit. + */ +#define XIF_XPN_PKTGEN_PKT_CNT_REG 0x48 + +/* + * Burst mode generation : + * 0 - continuous; 1 - burst mode as defined bycfgXpnPktGenBurstSize. +*/ +#define XIF_XPN_PKTGEN_PKT_CNT_CFGXPNPKTGENBURSTMODE_MASK 0x80000000 + +/* Number of packets to transmit. */ +#define XIF_XPN_PKTGEN_PKT_CNT_CFGXPNPKTGENBURSTSIZE_SHIFT 0 +#define XIF_XPN_PKTGEN_PKT_CNT_CFGXPNPKTGENBURSTSIZE_MASK 0xffffff + + +/* + * Register + * + * Specifies the size of each packet. + */ +#define XIF_XPN_PKTGEN_PKT_SIZE_REG 0x4c + +/* + * Size mode : + * 0 - fixed packet size, defined by cfgXpnPktGenSizeStart;1 - increment + * packet size, from cfgXpnPktGenSizeStart tocfgXpnPktGenSizeEnd. +*/ +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZEINCR_MASK 0x80000000 + +/* Indicates the ending size. */ +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZEEND_SHIFT 16 +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZEEND_MASK 0xfff0000 + +/* Indicates the starting size. */ +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZESTART_SHIFT 0 +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZESTART_MASK 0xfff + + +/* + * Register + * + * IPG insertion for packet generator. + */ +#define XIF_XPN_PKTGEN_IPG_REG 0x50 + +/* IPG insertion for back-2-back grants. */ +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENBCK2BCKIPG_SHIFT 16 +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENBCK2BCKIPG_MASK 0xffff0000 + +/* IPG insertion in between packets. */ +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENIPG_SHIFT 0 +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENIPG_MASK 0xffff + + +/* + * Register + * + * Specifies the threshold to generate pmcRxTsJitter interrupt. + */ +#define XIF_TS_JITTER_THRESH_REG 0x54 + +/* + * Defines the value to generate jitter interrupt when timestamp + * updateexceeds this threshold. +*/ +#define XIF_TS_JITTER_THRESH_CFGTSJTTRTHRESH_SHIFT 0 +#define XIF_TS_JITTER_THRESH_CFGTSJTTRTHRESH_MASK 0x7fffffff + + +/* + * Register + * + * Provides timestamp update control. + */ +#define XIF_TS_UPDATE_REG 0x58 + +/* + * Defines the full update threshold. + * Timestamp update is done in 1 TQincrement. + * If update is equal to or greater than threshold, fullupdate will result. +*/ +#define XIF_TS_UPDATE_CFGTSFULLUPDTHR_SHIFT 16 +#define XIF_TS_UPDATE_CFGTSFULLUPDTHR_MASK 0xffff0000 + +/* + * Provides auto timestamp update for debugging. + * This is to test fortimestamp jitter. +*/ +#define XIF_TS_UPDATE_CFGENAUTOTSUPD_MASK 0x8000 + +/* Defines the period between MPCP timestamp update. */ +#define XIF_TS_UPDATE_CFGTSUPDPER_SHIFT 0 +#define XIF_TS_UPDATE_CFGTSUPDPER_MASK 0xff + + +/* + * Register + * + * Specifies the burst overhead for normal grant. + */ +#define XIF_GNT_OVERHEAD_REG 0x5c + +/* Burst overhead of laser_on + sync_time. */ +#define XIF_GNT_OVERHEAD_CFGGNTOH_SHIFT 0 +#define XIF_GNT_OVERHEAD_CFGGNTOH_MASK 0xffff + + +/* + * Register + * + * Specifies the burst overhead for discovery grant. + */ +#define XIF_DISCOVER_OVERHEAD_REG 0x60 + +/* Burst overhead of laser_on + sync_time. */ +#define XIF_DISCOVER_OVERHEAD_CFGDISCOH_SHIFT 0 +#define XIF_DISCOVER_OVERHEAD_CFGDISCOH_MASK 0xffff + + +/* + * Register + * + * Specifies the discovery information field. + */ +#define XIF_DISCOVER_INFO_REG 0x64 + +/* + * Defines the discovery info field : + * 0 - upstream 1G; 1 - upstream10G; 4 - open 1G window; 5 - open 10G + * window. +*/ +#define XIF_DISCOVER_INFO_CFGDISCINFOFLD_SHIFT 0 +#define XIF_DISCOVER_INFO_CFGDISCINFOFLD_MASK 0xffff + + +/* + * Register + * + * Specifies the oversize threshold to increment oversize stat. + */ +#define XIF_XPN_OVERSIZE_THRESH_REG 0x68 + +/* + * Increments oversize stat when packet's size is greater than or equalto + * threshold. +*/ +#define XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_SHIFT 0 +#define XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_MASK 0x3fff + + +/* + * Register - read-only + * + * Provides downstream encryption key number stat, per LLID. + */ +#define XIF_SECRX_KEYNUM_REG 0x6c + +/* Key number stat. */ +#define XIF_SECRX_KEYNUM_KEYSTATRX_SHIFT 0 +#define XIF_SECRX_KEYNUM_KEYSTATRX_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides downstream encryption stat, per LLID. + */ +#define XIF_SECRX_ENCRYPT_REG 0x70 + +/* Encryption stat. */ +#define XIF_SECRX_ENCRYPT_ENCRSTATRX_SHIFT 0 +#define XIF_SECRX_ENCRYPT_ENCRSTATRX_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX receive frame count stat. + */ +#define XIF_PMC_FRAME_RX_CNT_REG 0x78 + +/* + * Frame count stat. + * Peg at max value. +*/ +#define XIF_PMC_FRAME_RX_CNT_PMCRXFRAMECNT_SHIFT 0 +#define XIF_PMC_FRAME_RX_CNT_PMCRXFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX byte count stat. + */ +#define XIF_PMC_BYTE_RX_CNT_REG 0x7c + +/* + * Byte count stat. + * Peg at max value. +*/ +#define XIF_PMC_BYTE_RX_CNT_PMCRXBYTECNT_SHIFT 0 +#define XIF_PMC_BYTE_RX_CNT_PMCRXBYTECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX runt count stat. + */ +#define XIF_PMC_RUNT_RX_CNT_REG 0x80 + +/* + * Runt count stat. + * Peg at max value. +*/ +#define XIF_PMC_RUNT_RX_CNT_PMCRXRUNTCNT_SHIFT 0 +#define XIF_PMC_RUNT_RX_CNT_PMCRXRUNTCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX code word error stat. + */ +#define XIF_PMC_CW_ERR_RX_CNT_REG 0x84 + +/* + * Codeword error stat. + * Peg at max value. +*/ +#define XIF_PMC_CW_ERR_RX_CNT_PMCRXCWERRCNT_SHIFT 0 +#define XIF_PMC_CW_ERR_RX_CNT_PMCRXCWERRCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX crc8 error stat. + */ +#define XIF_PMC_CRC8_ERR_RX_CNT_REG 0x88 + +/* + * CRC-8 error stat. + * Peg at max value. +*/ +#define XIF_PMC_CRC8_ERR_RX_CNT_PMCRXCRC8ERRCNT_SHIFT 0 +#define XIF_PMC_CRC8_ERR_RX_CNT_PMCRXCRC8ERRCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit data frame count. + */ +#define XIF_XPN_DATA_FRM_CNT_REG 0x8c + +/* + * Data frame count stat, excluding MPCP/OAM. + * Peg at max. +*/ +#define XIF_XPN_DATA_FRM_CNT_XPNDTFRAMECNT_SHIFT 0 +#define XIF_XPN_DATA_FRM_CNT_XPNDTFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit data byte count. + */ +#define XIF_XPN_DATA_BYTE_CNT_REG 0x90 + +/* + * Data byte count stat, excluding MPCP/OAM. + * Peg at max. +*/ +#define XIF_XPN_DATA_BYTE_CNT_XPNDTBYTECNT_SHIFT 0 +#define XIF_XPN_DATA_BYTE_CNT_XPNDTBYTECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit MPCP frame count. + */ +#define XIF_XPN_MPCP_FRM_CNT_REG 0x94 + +/* + * MPCP frame count stat. + * Peg at max. +*/ +#define XIF_XPN_MPCP_FRM_CNT_XPNMPCPFRAMECNT_SHIFT 0 +#define XIF_XPN_MPCP_FRM_CNT_XPNMPCPFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit OAM frame count. + */ +#define XIF_XPN_OAM_FRM_CNT_REG 0x98 + +/* + * MPCP frame count stat. + * Peg at max. +*/ +#define XIF_XPN_OAM_FRM_CNT_XPNOAMFRAMECNT_SHIFT 0 +#define XIF_XPN_OAM_FRM_CNT_XPNOAMFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit OAM byte count. + */ +#define XIF_XPN_OAM_BYTE_CNT_REG 0x9c + +/* + * OAM byte count stat. + * Peg at max. +*/ +#define XIF_XPN_OAM_BYTE_CNT_XPNOAMBYTECNT_SHIFT 0 +#define XIF_XPN_OAM_BYTE_CNT_XPNOAMBYTECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit oversize frame stat. + */ +#define XIF_XPN_OVERSIZE_FRM_CNT_REG 0xa0 + +/* Oversize frame, as defined by XIF_XPN_OVERSIZE_THRESH register. */ +#define XIF_XPN_OVERSIZE_FRM_CNT_XPNDTOVERSIZECNT_SHIFT 0 +#define XIF_XPN_OVERSIZE_FRM_CNT_XPNDTOVERSIZECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * SEC-RX abort frame stat. + */ +#define XIF_SEC_ABORT_FRM_CNT_REG 0xa4 + +/* + * Abort frame stat. + * Peg at max. +*/ +#define XIF_SEC_ABORT_FRM_CNT_SECRXABORTFRMCNT_SHIFT 0 +#define XIF_SEC_ABORT_FRM_CNT_SECRXABORTFRMCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-TX negative transmit time event. + */ +#define XIF_PMC_TX_NEG_EVENT_CNT_REG 0xa8 + +/* + * Negative event count stat. + * Peg at max value. +*/ +#define XIF_PMC_TX_NEG_EVENT_CNT_PMCTXNEGEVENTCNT_SHIFT 0 +#define XIF_PMC_TX_NEG_EVENT_CNT_PMCTXNEGEVENTCNT_MASK 0xff + + +/* + * Register - read-only + * + * Idle packet count. + */ +#define XIF_XPN_IDLE_PKT_CNT_REG 0xac + +/* + * Idle packet count stat. + * Peg at max value. +*/ +#define XIF_XPN_IDLE_PKT_CNT_XPNIDLEFRAMECNT_SHIFT 0 +#define XIF_XPN_IDLE_PKT_CNT_XPNIDLEFRAMECNT_MASK 0xffff + + +/* + * Registers - is [ 0 => 32 ] + * + * Configures LLID index 0 translation. + */ +#define XIF_LLIDx_0_31_REG(x) (0xc0 + (x) * 0x4) + +/* + * Defines the 16-bits LLID for index 0 : + * [15: + * 0] - LLID; [16] - enableLLID. + * In upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup withVLAN's VID to index 0. + * In downstream P2P, 802. + * 1ae mode, registersXIF_P2P_AE_SCI_LO[0: + * 15]/XIF_P2P_AE_SCI_HI[0: + * 15] provide lookup withpacket's explicit SCI to an index. +*/ +#define XIF_LLIDx_0_31_CFGONULLID0_SHIFT 0 +#define XIF_LLIDx_0_31_CFGONULLID0_MASK 0x1ffff + + +/* + * Register + * + * Specifies the maximum MPCP update. + */ +#define XIF_MAX_MPCP_UPDATE_REG 0x140 + +/* Maximum MPCP update value. */ +#define XIF_MAX_MPCP_UPDATE_CFGMAXPOSMPCPUPD_SHIFT 0 +#define XIF_MAX_MPCP_UPDATE_CFGMAXPOSMPCPUPD_MASK 0xffffffff + + +/* + * Register + * + * Specifies the IPG insertion between packets. + */ +#define XIF_IPG_INSERTION_REG 0x144 + +/* + * Enable short IPG insertion, average of 8 bytes. + * Should only beenabled only in FEC mode. + * Otherwise, average of 12 bytes isinserted. +*/ +#define XIF_IPG_INSERTION_CFGSHORTIPG_MASK 0x200 + +/* Debug function to enable IPG insertion. */ +#define XIF_IPG_INSERTION_CFGINSERTIPG_MASK 0x100 + +/* + * Configure the number of IPG word (2 bytes) to insert. + * Only validwhen cfgInsertIpg is asserted. +*/ +#define XIF_IPG_INSERTION_CFGIPGWORD_SHIFT 0 +#define XIF_IPG_INSERTION_CFGIPGWORD_MASK 0x7f + + +/* + * Register + * + * Specifies the MPCP time to generate a one pulse per second (PPS)signal. + */ +#define XIF_TRANSPORT_TIME_REG 0x148 + +/* PPS is generated when the current MPCP is equal to the programmedvalue. */ +#define XIF_TRANSPORT_TIME_CFTRANSPORTTIME_SHIFT 0 +#define XIF_TRANSPORT_TIME_CFTRANSPORTTIME_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides the current MPCP time. + */ +#define XIF_MPCP_TIME_REG 0x14c + +/* Current MPCP time. */ +#define XIF_MPCP_TIME_CURMPCPTS_SHIFT 0 +#define XIF_MPCP_TIME_CURMPCPTS_MASK 0xffffffff + + +/* + * Register + * + * Provides the overhead for overlapping grant. + */ +#define XIF_OVERLAP_GNT_OH_REG 0x150 + +/* Provides the amount the laser_on time and laser_off time mayoverlap. */ +#define XIF_OVERLAP_GNT_OH_CFGOVRLPOH_SHIFT 0 +#define XIF_OVERLAP_GNT_OH_CFGOVRLPOH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the MAC mode of operation. + */ +#define XIF_MAC_MODE_REG 0x154 + +/* + * Enable point-2-point transmission without grant. + * Must also set bitcfgEnP2P. +*/ +#define XIF_MAC_MODE_CFGENNOGNTXMT_MASK 0x2 + + +/* + * Register + * + * Provides the control for PMC. + */ +#define XIF_PMCTX_CTL_REG 0x158 + +/* + * Define the MPCP update period. + * A value of 0xff disables update. +*/ +#define XIF_PMCTX_CTL_CFGMPCPUPDPERIOD_SHIFT 16 +#define XIF_PMCTX_CTL_CFGMPCPUPDPERIOD_MASK 0xff0000 + +/* + * Disable the requirement of 4 IDLEs preceeding start character toconsider + * packet valid. +*/ +#define XIF_PMCTX_CTL_CFGDIS4IDLEB4STARTCHAR_MASK 0x20 + +/* Enable upstream IDLE discard */ +#define XIF_PMCTX_CTL_CFGENIDLEDSCRD_MASK 0x10 + +/* + * Selects the source of transmit MPCP time : + * 0 - RX; 1 - TX. +*/ +#define XIF_PMCTX_CTL_CFGSELTXPONTIME_MASK 0x8 + +/* Enable continous MPCP update. */ +#define XIF_PMCTX_CTL_CFGMPCPCONTUPD_MASK 0x4 + +/* + * Enable the restriction of positive MPCP update, limitted + * bycfgMaxPosMpcpUpd value set in register XIF_MAX_MPCP_UPDATE. +*/ +#define XIF_PMCTX_CTL_CFGENMAXMPCPUPD_MASK 0x2 + +/* + * Enable the discard of packet with negative scheduled transmit + * time,relative to the current MPCP. +*/ +#define XIF_PMCTX_CTL_CFGENNEGTIMEABORT_MASK 0x1 + + +/* + * Register + * + * Provides control for security. + */ +#define XIF_SEC_CTL_REG 0x15c + +/* + * [A0 BUG] - HWBCM6858-457Enables downstream short length support. + * This feature cannot besupported inA0. + * The workaround would be to disable this feature by clearing thebit. +*/ +#define XIF_SEC_CTL_CFGSECRXENSHORTLEN_MASK 0x40 + +/* Enable fake AES on TX security. */ +#define XIF_SEC_CTL_CFGENSECTXFAKEAES_MASK 0x20 + +/* Enable fake AES on RX security. */ +#define XIF_SEC_CTL_CFGENSECRXFAKEAES_MASK 0x10 + +/* Enables packet number rollover on receive. */ +#define XIF_SEC_CTL_CFGSECRXENPKTNUMRLOVR_MASK 0x8 + +/* Enables packet number rollover on transmit. */ +#define XIF_SEC_CTL_CFGSECTXENPKTNUMRLOVR_MASK 0x2 + +/* Enables replay protection on RX security. */ +#define XIF_SEC_CTL_CFGENAEREPLAYPRCT_MASK 0x1 + + +/* + * Register + * + * Provides the tolerance for packet number reception in replay + * protectionmode. + * Only applicable in 802. + * 1ae security mode. + */ +#define XIF_AE_PKTNUM_WINDOW_REG 0x160 + +/* + * In replay protection, the packet number is checked against theexpected + * packet number. + * If it is greater than or equal to, packetwill be accepted. + * Otherwise, it will be discarded. + * This registerprovides the tolerance by subtracting the current expected + * packetnumber by this amount. +*/ +#define XIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_SHIFT 0 +#define XIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_MASK 0xffffffff + + +/* + * Register + * + * Provides the threshold to warn of impending packet number rollover + * ontransmit. + */ +#define XIF_AE_PKTNUM_THRESH_REG 0x164 + +/* Defines the threshold of impending packet number rollover. */ +#define XIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_SHIFT 0 +#define XIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides upstream encryption key number stat, per LLID. + */ +#define XIF_SECTX_KEYNUM_REG 0x168 + +/* KeyNumber stat */ +#define XIF_SECTX_KEYNUM_KEYSTATTX_SHIFT 0 +#define XIF_SECTX_KEYNUM_KEYSTATTX_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides upstream encryption stat, per LLID. + */ +#define XIF_SECTX_ENCRYPT_REG 0x16c + +/* Encryption stat. */ +#define XIF_SECTX_ENCRYPT_ENCRSTATTX_SHIFT 0 +#define XIF_SECTX_ENCRYPT_ENCRSTATTX_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides packet number status. + */ +#define XIF_AE_PKTNUM_STAT_REG 0x170 + +/* + * Provides the LLID index whose packet number exceeded the maximumpacket + * number threhsold. +*/ +#define XIF_AE_PKTNUM_STAT_SECTXINDXWTPKTNUMMAX_SHIFT 16 +#define XIF_AE_PKTNUM_STAT_SECTXINDXWTPKTNUMMAX_MASK 0x1f0000 + +/* Provides the LLID index that was aborted due to replay protection. */ +#define XIF_AE_PKTNUM_STAT_SECRXINDXWTPKTNUMABORT_SHIFT 0 +#define XIF_AE_PKTNUM_STAT_SECRXINDXWTPKTNUMABORT_MASK 0x1f + + +/* + * Register - read-only + * + * Debug register showing time between MPCP updates. + */ +#define XIF_MPCP_UPDATE_REG 0x174 + +/* Time between MPCP updates. */ +#define XIF_MPCP_UPDATE_MPCPUPDPERIOD_SHIFT 0 +#define XIF_MPCP_UPDATE_MPCPUPDPERIOD_MASK 0xffffffff + + +/* + * Register + * + * Provides prelaunch time of burst data from ONU, relative to + * thegrant-start-time. + */ +#define XIF_BURST_PRELAUNCH_OFFSET_REG 0x178 + +/* Defines the prelaunch time of burst data, in unit of TQ. */ +#define XIF_BURST_PRELAUNCH_OFFSET_CFGBURSTPRELAUNCHOFFSET_SHIFT 0 +#define XIF_BURST_PRELAUNCH_OFFSET_CFGBURSTPRELAUNCHOFFSET_MASK 0xffffffff + + +/* + * Register + * + * Provides a programmable VLAN type identifier for upstream P2P traffic. + */ +#define XIF_VLAN_TYPE_REG 0x17c + +/* Defines a VLAN type, in addition to 0x8100. */ +#define XIF_VLAN_TYPE_CFGVLANTYPE_SHIFT 0 +#define XIF_VLAN_TYPE_CFGVLANTYPE_MASK 0xffff + + +/* + * Register + * + * Enables SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define XIF_P2P_AE_SCI_EN_REG 0x180 + +/* + * Enables SCI lookup, viaXIF_P2P_AE_SCI_LO[0: + * 15]/XIF_P2P_AE_SCI_HI[0: + * 15] registers. + * Each bitcorresponds to index 0 - 15. +*/ +#define XIF_P2P_AE_SCI_EN_CFGP2PSCIEN_SHIFT 0 +#define XIF_P2P_AE_SCI_EN_CFGP2PSCIEN_MASK 0xffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define XIF_P2P_AE_SCI_LOx_REG(x) (0x184 + (x) * 0x8) + +/* + * Defines the lower 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byXIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define XIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_SHIFT 0 +#define XIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define XIF_P2P_AE_SCI_HIx_REG(x) (0x188 + (x) * 0x8) + +/* + * Defines the upper 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byXIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define XIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_SHIFT 0 +#define XIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides additon per-LLID status of upstream security key for 802. + * 1aeP2P. + */ +#define XIF_SECTX_KEYNUM_1_REG 0x204 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by XIF_SECTX_KEYNUM. +*/ +#define XIF_SECTX_KEYNUM_1_KEYSTATTX_HI_SHIFT 0 +#define XIF_SECTX_KEYNUM_1_KEYSTATTX_HI_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides addition per-LLID status of downstream security key for802. + * 1ae P2P. + */ +#define XIF_SECRX_KEYNUM_1_REG 0x208 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by XIF_SECRX_KEYNUM. +*/ +#define XIF_SECRX_KEYNUM_1_KEYSTATRX_HI_SHIFT 0 +#define XIF_SECRX_KEYNUM_1_KEYSTATRX_HI_MASK 0xffffffff + + +#endif /* ! EPON_XIF_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcsrx.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcsrx.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcsrx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcsrx.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,1623 @@ +#ifndef EPON_XPCSRX_H_ +#define EPON_XPCSRX_H_ + +/* relative to epon */ +#define XPCSRX_OFFSET_0 0x3000 + +/* + * Register + * + * Provides reset for submodules within XPCS RX and XSBI. + */ +#define XPCSRX_RX_RST_REG 0x0 + +/* Active low reset for 161 MHz domain in XPCS RX. */ +#define RX_RST_CFGXPCSRXCLK161RSTN_MASK 0x1 + + +/* + * Register + * + * Interrupt status for XPcsRx module. + */ +#define XPCSRX_RX_INT_STAT_REG 0x4 + +/* DA jitter detected. */ +#define RX_INT_STAT_INTRXIDLEDAJIT_MASK 0x40000000 + +/* Missing burst detected. */ +#define RX_INT_STAT_INTRXFRMRMISBRST_MASK 0x20000000 + +/* Over size packet detected. */ +#define RX_INT_STAT_INTRXIDLESOPEOPGAPBIG_MASK 0x10000000 + +/* + * No idle insert opportunity in 2000 bytes. + * Idle insert was forced. +*/ +#define RX_INT_STAT_INTRXIDLEFRCINS_MASK 0x8000000 + +/* Min IPG error detected. */ +#define RX_INT_STAT_INTRX64B66BMINIPGERR_MASK 0x4000000 + +/* FEC CW store/foward enqueue input and output count not equal. */ +#define RX_INT_STAT_INTRXFECNQUECNTNEQ_MASK 0x2000000 + +/* + * Idle insert FIFO under run. + * Fatal +*/ +#define RX_INT_STAT_INTRXIDLEFIFOUNDRUN_MASK 0x1000000 + +/* + * Idle insert FIFO over run. + * Fatal +*/ +#define RX_INT_STAT_INTRXIDLEFIFOOVRRUN_MASK 0x800000 + +/* + * FEC high correction alarm. + * High FEC correctoin occured overcfgXPcsRxFecCorIntval +*/ +#define RX_INT_STAT_INTRXFECHIGHCOR_MASK 0x400000 + +/* FEC CW decode fail and FEC decoder is frozen percfgXPcsRxFecStopOnErr */ +#define RX_INT_STAT_INTRXFECDECSTOPONERR_MASK 0x80000 + +/* FEC CW decode passed. */ +#define RX_INT_STAT_INTRXFECDECPASS_MASK 0x40000 + +/* Framer has high BER. */ +#define RX_INT_STAT_INTRXSTATFRMRHIGHBER_MASK 0x20000 + +/* Framer exited by hitting max count on SP. */ +#define RX_INT_STAT_INTRXFRMREXITBYSP_MASK 0x10000 + +/* Framer hit bad SH max count. */ +#define RX_INT_STAT_INTRXFRMRBADSHMAX_MASK 0x8000 + +/* Burst sequence out of order. */ +#define RX_INT_STAT_INTRXDSCRAMBURSTSEQOUT_MASK 0x4000 + +/* Test pattern psudo lock. */ +#define RX_INT_STAT_INTRXTESTPSUDOLOCK_MASK 0x2000 + +/* Test pattern psudo type. */ +#define RX_INT_STAT_INTRXTESTPSUDOTYPE_MASK 0x1000 + +/* Test pattern psudo error. */ +#define RX_INT_STAT_INTRXTESTPSUDOERR_MASK 0x800 + +/* Test pattern PRBS lock. */ +#define RX_INT_STAT_INTRXTESTPRBSLOCK_MASK 0x400 + +/* Test pattern PRBS error. */ +#define RX_INT_STAT_INTRXTESTPRBSERR_MASK 0x200 + +/* Three consecative failed FEC CW decode. */ +#define RX_INT_STAT_INTRXFECPSISTDECFAIL_MASK 0x100 + +/* Framer detected bad SH while in lock. */ +#define RX_INT_STAT_INTRXFRAMERBADSH_MASK 0x80 + +/* Framer went into loss. */ +#define RX_INT_STAT_INTRXFRAMERCWLOSS_MASK 0x40 + +/* Framer went into lock. */ +#define RX_INT_STAT_INTRXFRAMERCWLOCK_MASK 0x20 + +/* FEC CW decode failed. */ +#define RX_INT_STAT_INTRXFECDECFAIL_MASK 0x10 + +/* 66b to 64b decode error has occured. */ +#define RX_INT_STAT_INTRX64B66BDECERR_MASK 0x8 + +/* No frmrCwLk before the no lock timer expired. */ +#define RX_INT_STAT_INTRXFRMRNOLOCKLOS_MASK 0x4 + +/* SP count hit max in ranging but no lock */ +#define RX_INT_STAT_INTRXFRMRROGUE_MASK 0x2 + +/* register access error has occured. */ +#define RX_INT_STAT_INT_REGS_ERR_MASK 0x1 + + +/* + * Register + * + * Interrupt mask for XPcsRx module. + */ +#define XPCSRX_RX_INT_MSK_REG 0x8 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEDAJIT_MASK 0x40000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRMISBRST_MASK 0x20000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLESOPEOPGAPBIG_MASK 0x10000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEFRCINS_MASK 0x8000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRX64B66BMINIPGERR_MASK 0x4000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECNQUECNTNEQ_MASK 0x2000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEFIFOUNDRUN_MASK 0x1000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEFIFOOVRRUN_MASK 0x800000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECHIGHCOR_MASK 0x400000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECDECSTOPONERR_MASK 0x80000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECDECPASS_MASK 0x40000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXSTATFRMRHIGHBER_MASK 0x20000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMREXITBYSP_MASK 0x10000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRBADSHMAX_MASK 0x8000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXDSCRAMBURSTSEQOUT_MASK 0x4000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPSUDOLOCK_MASK 0x2000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPSUDOTYPE_MASK 0x1000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPSUDOERR_MASK 0x800 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPRBSLOCK_MASK 0x400 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPRBSERR_MASK 0x200 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECPSISTDECFAIL_MASK 0x100 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRAMERBADSH_MASK 0x80 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRAMERCWLOSS_MASK 0x40 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRAMERCWLOCK_MASK 0x20 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECDECFAIL_MASK 0x10 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRX64B66BDECERR_MASK 0x8 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRNOLOCKLOS_MASK 0x4 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRROGUE_MASK 0x2 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSK_INT_REGS_ERR_MASK 0x1 + + +/* + * Register + * + * Provides control over framer in XPCS RX. + */ +#define XPCSRX_RX_FRAMER_CTL_REG 0xc + +/* + * 1 = block loading ofr alingMux0Sel when spLkCntMax achievedThis wasthe + * ECO or PIONEER B2 +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRFRCEARLYALIGN_MASK 0x8000 + +/* + * 0 = use framing mode for mux select = alignMux0SelQ forbdEbdAlignedData1 + * = use framing mode for mux select = alignMux0SelQQfor bdEbdAlignedData +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRMODEA_MASK 0x4000 + +/* + * Allows framer to not require any space between EBD and BD faterframing + * once during overlaping grants. + * cfgXPcsRxFrmrOverlapGntEn must be set to use this bit. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMROVERLAPBDEBDZERO_MASK 0x2000 + +/* + * Allows framer to not require spLkCntMax (look for BD withoutpreceeding + * SP) after framing once during overlaping grants. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMROVERLAPGNTEN_MASK 0x1000 + +/* + * Enable for burst mode framing using old alignment + * (xsbiPcsRxFifoVldinstead of xsbiPcsRxFifoVldQ) for alignMuxSelQ and + * alignMuzSelQQ. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRAMEBURSTOLDALIGN_MASK 0x200 + +/* + * 0 - Use falling edge of SP count max and no framer lock to countmissing + * burst. + * 1 - Use unassigned strobe for detection of missingburst. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRMISBRSTTYPE_MASK 0x100 + +/* In burst mode only look at EBD at the end of codewords. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMREBDVLDEN_MASK 0x80 + +/* FPGA only. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRBDCNTEN_MASK 0x40 + +/* Allows framer to lose lock from 16 bad SH in 62 blocks for burstmode. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRBURSTBADSHEN_MASK 0x20 + +/* Allows framer to lose lock from detection of sync pattern. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRSPULKEN_MASK 0x10 + +/* Enable for burst mode framing. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRAMEBURST_MASK 0x8 + +/* Enable for framer. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMREN_MASK 0x4 + +/* Allows for ignoring of FEC persist decode fail in clause 76 framing. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRBLKFECFAIL_MASK 0x2 + +/* Enable for FEC framing. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRAMEFEC_MASK 0x1 + + +/* + * Register + * + * Provides control over FEC in XPCS RX. + */ +#define XPCSRX_RX_FEC_CTL_REG 0x10 + +/* + * Freezes FEC decoder from writing and reading FEC RAM when an erroris + * decoded. + * No recovery after wards, requires that XPCS RX be reset. +*/ +#define RX_FEC_CTL_CFGXPCSRXFECSTOPONERR_MASK 0x400 + +/* + * Tells FEC stats engine to count CW enqueued insted of total FECdecoded + * CW +*/ +#define RX_FEC_CTL_CFGXPCSRXFECCNTNQUECW_MASK 0x200 + +/* Reset the store and foward FIFO. */ +#define RX_FEC_CTL_CFGXPCSRXFECNQUERST_MASK 0x100 + +/* + * 0 - Count every bit correction for the FEC CW. + * 1 - Count only a single correction per 8 bits. + * This only affects the corrected ones and corrected zero stats. + * The total corrected is not effected by this control. +*/ +#define RX_FEC_CTL_CFGXPCSRXFECONEZEROMODE_MASK 0x80 + +/* Stop FEC decoder from making corrections. */ +#define RX_FEC_CTL_CFGXPCSRXFECBLKCORRECT_MASK 0x40 + +/* Replace all FEC CW with IEEE test CW. */ +#define RX_FEC_CTL_CFGXPCSRXFECNQUETESTPAT_MASK 0x20 + +/* + * 0 - Do not blank out SH for failed FEC CW decodes. + * 1 - Blank out SHfor failed FEC CW. + * CW will pass as /E. +*/ +#define RX_FEC_CTL_CFGXPCSRXFECFAILBLKSH0_MASK 0x10 + +/* Enable stripping of FEC parity for FEC decode bypass. */ +#define RX_FEC_CTL_CFGXPCSRXFECSTRIP_MASK 0x8 + +/* Elable FEC decode bypass. */ +#define RX_FEC_CTL_CFGXPCSRXFECBYPAS_MASK 0x4 + +/* Enable idle insert to replace FEC parity lost in FEC decode. */ +#define RX_FEC_CTL_CFGXPCSRXFECIDLEINS_MASK 0x2 + +/* Enable FEC decode. */ +#define RX_FEC_CTL_CFGXPCSRXFECEN_MASK 0x1 + + +/* + * Register + * + * Provides control over descrambler in XPCS RX. + */ +#define XPCSRX_RX_DSCRAM_CTL_REG 0x14 + +/* Enable descrambler bypass. */ +#define RX_DSCRAM_CTL_CFGXPCSRXDSCRAMBYPAS_MASK 0x1 + + +/* + * Register + * + * Provides control over 64b/66b decoder in XPCS RX. + */ +#define XPCSRX_RX_64B66B_CTL_REG 0x18 + +/* Defalut to T7 to T4 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK1_SHIFT 24 +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK1_MASK 0xff000000 + +/* Defalut to T7 to T4 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK0_SHIFT 16 +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK0_MASK 0xff0000 + +/* Defalut to S0 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK1_SHIFT 12 +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK1_MASK 0x3000 + +/* Defalut to S0 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK0_SHIFT 8 +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK0_MASK 0x300 + +/* Compare S one pipe behind T. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BTDLAY_SHIFT 4 +#define RX_64B66B_CTL_CFGXPCSRX64B66BTDLAY_MASK 0x30 + +/* Enable 64B/66B decoder bypass. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BDECBYPAS_MASK 0x1 + + +/* + * Register + * + * Provides control over test circuits in XPCS RX. + */ +#define XPCSRX_RX_TEST_CTL_REG 0x1c + +/* Enable PRBS test pattern detector. */ +#define RX_TEST_CTL_CFGXPCSRXTESTPRBSDETEN_MASK 0x2 + +/* Enable psudo test pattern detector. */ +#define RX_TEST_CTL_CFGXPCSRXTESTPSUDODETEN_MASK 0x1 + + +/* + * Register + * + * Sets the delay time to start read of burst from idle insert FIFO. + */ +#define XPCSRX_RX_IDLE_RD_TIMER_DLY_REG 0x20 + +/* + * The delay time to start read of burst (default is 8'd60 ticks). + * Sets the delay to 8'd232 for 10K MTU. +*/ +#define RX_IDLE_RD_TIMER_DLY_CFGXPCSRXIDLERDDELAYTIMERMAX_SHIFT 0 +#define RX_IDLE_RD_TIMER_DLY_CFGXPCSRXIDLERDDELAYTIMERMAX_MASK 0xff + + +/* + * Register + * + * Sets the size for over size frames based on delta between SOP and EOP. + */ +#define XPCSRX_RX_IDLE_GAP_SIZ_MAX_REG 0x24 + +/* + * Max size in blocks without an idle insert opportunity before idleinsert + * is forced. +*/ +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLEOVRSIZMAX_SHIFT 16 +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLEOVRSIZMAX_MASK 0x7ff0000 + +/* Max distance in blocks between SOP and EOP. */ +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLESOPEOPGAP_SHIFT 0 +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLESOPEOPGAP_MASK 0xffff + + +/* + * Register + * + * Sets the delay for indicating lock to FEC decode circuit. + * For FEC modes use the defalut of 8'd280. + * For FEC bypass modes use the defalut of 8'd26. + */ +#define XPCSRX_RX_FRAMER_LK_MAX_REG 0x28 + +/* Max delay for framer to inditcate to FEC circuit lock has beenachieved. */ +#define RX_FRAMER_LK_MAX_CFGXPCSRXFRMRCWLKTIMERMAX_SHIFT 0 +#define RX_FRAMER_LK_MAX_CFGXPCSRXFRMRCWLKTIMERMAX_MASK 0x1ff + + +/* + * Register + * + * Sets the delay for indicating unlock to FEC decode circuit. + * For FEC modes use the defalut of 8'd280. + * For FEC bypass modes use the defalut of 8'd26. + */ +#define XPCSRX_RX_FRAMER_UNLK_MAX_REG 0x2c + +/* Max delay for framer to inditcate to FEC circuit unlock has occured. */ +#define RX_FRAMER_UNLK_MAX_CFGXPCSRXFRMRCWUNLKTIMERMAX_SHIFT 0 +#define RX_FRAMER_UNLK_MAX_CFGXPCSRXFRMRCWUNLKTIMERMAX_MASK 0x1ff + + +/* + * Register + * + * Sets the SH value for the BD for the framer. + */ +#define XPCSRX_RX_FRAMER_BD_SH_REG 0x30 + +/* BD sync header. */ +#define RX_FRAMER_BD_SH_CFGXPCSRXOLTBDSH_SHIFT 0 +#define RX_FRAMER_BD_SH_CFGXPCSRXOLTBDSH_MASK 0x3 + + +/* + * Register + * + * Sets the low 32 bit value for the BD for the framer. + */ +#define XPCSRX_RX_FRAMER_BD_LO_REG 0x34 + +/* Low 32 bit value for the BD. */ +#define RX_FRAMER_BD_LO_CFGXPCSRXOLTBDLO_SHIFT 0 +#define RX_FRAMER_BD_LO_CFGXPCSRXOLTBDLO_MASK 0xffffffff + + +/* + * Register + * + * Sets the high 32 bit value for the BD for the framer. + */ +#define XPCSRX_RX_FRAMER_BD_HI_REG 0x38 + +/* High 32 bit value for the BD. */ +#define RX_FRAMER_BD_HI_CFGXPCSRXOLTBDHI_SHIFT 0 +#define RX_FRAMER_BD_HI_CFGXPCSRXOLTBDHI_MASK 0xffffffff + + +/* + * Register + * + * Sets the SH value for the EBD for the framer. + */ +#define XPCSRX_RX_FRAMER_EBD_SH_REG 0x3c + +/* EBD sync header. */ +#define RX_FRAMER_EBD_SH_CFGXPCSRXOLTEBDSH_SHIFT 0 +#define RX_FRAMER_EBD_SH_CFGXPCSRXOLTEBDSH_MASK 0x3 + + +/* + * Register + * + * Sets the low 32 bit value for the EBD for the framer. + */ +#define XPCSRX_RX_FRAMER_EBD_LO_REG 0x40 + +/* Low 32 bit value for the EBD. */ +#define RX_FRAMER_EBD_LO_CFGXPCSRXOLTEBDLO_SHIFT 0 +#define RX_FRAMER_EBD_LO_CFGXPCSRXOLTEBDLO_MASK 0xffffffff + + +/* + * Register + * + * Sets the high 32 bit value for the EBD for the framer. + */ +#define XPCSRX_RX_FRAMER_EBD_HI_REG 0x44 + +/* High 32 bit value for the EBD. */ +#define RX_FRAMER_EBD_HI_CFGXPCSRXOLTEBDHI_SHIFT 0 +#define RX_FRAMER_EBD_HI_CFGXPCSRXOLTEBDHI_MASK 0xffffffff + + +/* + * Register - read-only + * + * Raw value for interrupt status. + */ +#define XPCSRX_RX_STATUS_REG 0x48 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEDAJIT_MASK 0x40000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRMISBRST_MASK 0x20000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLESOPEOPGAPBIG_MASK 0x10000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEFRCINS_MASK 0x8000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRX64B66BMINIPGERR_MASK 0x4000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECNQUECNTNEQ_MASK 0x2000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEFIFOUNDRUN_MASK 0x1000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEFIFOOVRRUN_MASK 0x800000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECHIGHCOR_MASK 0x400000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECDECPASS_MASK 0x40000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXSTATFRMRHIGHBER_MASK 0x20000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMREXITBYSP_MASK 0x10000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRBADSHMAX_MASK 0x8000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXDSCRAMBURSTSEQOUT_MASK 0x4000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPSUDOLOCK_MASK 0x2000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPSUDOTYPE_MASK 0x1000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPSUDOERR_MASK 0x800 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPRBSLOCK_MASK 0x400 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPRBSERR_MASK 0x200 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECPSISTDECFAIL_MASK 0x100 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRAMERBADSH_MASK 0x80 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRAMERCWLOSS_MASK 0x40 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRAMERCWLOCK_MASK 0x20 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECDECFAIL_MASK 0x10 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRX64B66BDECERR_MASK 0x8 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRNOLOCKLOS_MASK 0x4 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRROGUE_MASK 0x2 + + +/* + * Register + * + * Sets number of SP detected in order to validate lock or unlock. + */ +#define XPCSRX_RX_FRAMER_LK_ULK_MAX_REG 0x4c + +/* The number of consecutive SP before a BD required to gain lock. */ +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPLKMAX_SHIFT 16 +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPLKMAX_MASK 0x1fff0000 + +/* The number of consecutive SP required to lose lock. */ +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPULKMAX_SHIFT 0 +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPULKMAX_MASK 0x1fff + + +/* + * Register + * + * Sets the SH value for the SP for the framer. + */ +#define XPCSRX_RX_FRAMER_SP_SH_REG 0x50 + +/* The SH value for SP. */ +#define RX_FRAMER_SP_SH_CFGXPCSRXOLTSPSH_SHIFT 0 +#define RX_FRAMER_SP_SH_CFGXPCSRXOLTSPSH_MASK 0x3 + + +/* + * Register + * + * Sets the low 32 bit value for the SP for the framer. + */ +#define XPCSRX_RX_FRAMER_SP_LO_REG 0x54 + +/* The lowest 32 bit value for the SP. */ +#define RX_FRAMER_SP_LO_CFGXPCSRXOLTSPLO_SHIFT 0 +#define RX_FRAMER_SP_LO_CFGXPCSRXOLTSPLO_MASK 0xffffffff + + +/* + * Register + * + * Sets the high 32 bit value for the SP for the framer. + */ +#define XPCSRX_RX_FRAMER_SP_HI_REG 0x58 + +/* The highest 32 bit value for the SP. */ +#define RX_FRAMER_SP_HI_CFGXPCSRXOLTSPHI_SHIFT 0 +#define RX_FRAMER_SP_HI_CFGXPCSRXOLTSPHI_MASK 0xffffffff + + +/* + * Register - read-only + * + * The current value of framer state machine. + */ +#define XPCSRX_RX_FRAMER_STATE_REG 0x5c + +/* The state of the framer state machine. */ +#define RX_FRAMER_STATE_XPCSRXFRMRSTATE_SHIFT 0 +#define RX_FRAMER_STATE_XPCSRXFRMRSTATE_MASK 0xf + + +/* + * Register + * + * Sets the hamming distance for SP + */ +#define XPCSRX_RX_FRAMER_BD_EBD_HAM_REG 0x60 + +/* Hamming distance for SP. */ +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRSPHAM_SHIFT 8 +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRSPHAM_MASK 0xf00 + +/* Hamming distance for EBD. */ +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMREBDHAM_SHIFT 4 +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMREBDHAM_MASK 0xf0 + +/* Hamming distance for BD. */ +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRBDHAM_SHIFT 0 +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRBDHAM_MASK 0xf + + +/* + * Register + * + * The count of the possible missing bursts that were detected. + * This isbased on SP detect and SP loss with no BD found. + */ +#define XPCSRX_RX_FRAMER_MISBRST_CNT_REG 0x64 + +/* Count of possibe missed burst. */ +#define RX_FRAMER_MISBRST_CNT_RXFRMRMISBRSTCNT_SHIFT 0 +#define RX_FRAMER_MISBRST_CNT_RXFRMRMISBRSTCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of bit errors found in the last BD when lock was declared. + */ +#define XPCSRX_RX_FRAMER_BD_ERR_REG 0x68 + +/* A count of the errors in BD when it was found. */ +#define RX_FRAMER_BD_ERR_XPCSRXSTATFRMRBDERR_SHIFT 0 +#define RX_FRAMER_BD_ERR_XPCSRXSTATFRMRBDERR_MASK 0xf + + +/* + * Register + * + * Config for LOS based on no lock during a time interval + */ +#define XPCSRX_RX_FRAMER_ROGUE_CTL_REG 0x6c + +/* + * 0 - Rogue detection is disable. + * 1 - Rogue detection is enable. +*/ +#define RX_FRAMER_ROGUE_CTL_CFGXPCSRXFRMRROGUEEN_MASK 0x80000000 + +/* + * If SP count hits treshold and the ranging window endswithout a lockthen + * a rogue detectoin alarm is set. +*/ +#define RX_FRAMER_ROGUE_CTL_CFGXPCSRXFRMRROGUESPTRESH_SHIFT 0 +#define RX_FRAMER_ROGUE_CTL_CFGXPCSRXFRMRROGUESPTRESH_MASK 0xffff + + +/* + * Register + * + * Config for LOS based on no lock during a time interval + */ +#define XPCSRX_RX_FRAMER_NOLOCK_CTL_REG 0x70 + +/* + * 0 - No lock LOS detection is disable. + * 1 - No lock LOS detection isenable. +*/ +#define RX_FRAMER_NOLOCK_CTL_CFGXPCSRXFRMRNOLOCKLOSEN_MASK 0x80000000 + +/* + * Interval for LOS based on no lock found during this time. + * These are6. + * 206 ns steps with default of 1ms. + * The counter is 24 bits with a maxinterval of 104 ms. +*/ +#define RX_FRAMER_NOLOCK_CTL_CFGXPCSRXFRMRNOLOCKLOSINTVAL_SHIFT 0 +#define RX_FRAMER_NOLOCK_CTL_CFGXPCSRXFRMRNOLOCKLOSINTVAL_MASK 0xffffff + + +/* + * Register + * + * Min IPG violation detection count. + */ +#define XPCSRX_RX_64B66B_IPG_DET_CNT_REG 0x74 + +/* + * This is the number of times that a realtionship between the EOP andSOP + * is found. + * The defalut is set to detect min-IPG violations. +*/ +#define RX_64B66B_IPG_DET_CNT_RX64B66BIPGDETCNT_SHIFT 0 +#define RX_64B66B_IPG_DET_CNT_RX64B66BIPGDETCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of FEC CW written to the store/foward enqueue FIFO. + */ +#define XPCSRX_RX_FEC_NQUE_IN_CNT_REG 0x78 + +/* The number of FEC CW written into the store/foward FIFO. */ +#define RX_FEC_NQUE_IN_CNT_RXFECNQUEINCNT_SHIFT 0 +#define RX_FEC_NQUE_IN_CNT_RXFECNQUEINCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of FEC codewrods read from the store/foward + * enqueueFIFO. + */ +#define XPCSRX_RX_FEC_NQUE_OUT_CNT_REG 0x7c + +/* The number of FEC CW read from the store/foward FIFO. */ +#define RX_FEC_NQUE_OUT_CNT_RXFECNQUEOUTCNT_SHIFT 0 +#define RX_FEC_NQUE_OUT_CNT_RXFECNQUEOUTCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of SOP detected in the IDLE insert circuit. + */ +#define XPCSRX_RX_IDLE_START_CNT_REG 0x80 + +/* The number of SOP that the idle insertion logic detected. */ +#define RX_IDLE_START_CNT_RXIDLESTARTCNT_SHIFT 0 +#define RX_IDLE_START_CNT_RXIDLESTARTCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of EOP detected in the IDLE insert circuit. + */ +#define XPCSRX_RX_IDLE_STOP_CNT_REG 0x84 + +/* The number of EOP that the idle insertion logic detected. */ +#define RX_IDLE_STOP_CNT_RXIDLESTOPCNT_SHIFT 0 +#define RX_IDLE_STOP_CNT_RXIDLESTOPCNT_MASK 0xffffffff + + +/* + * Register + * + * Time interval setting (in 6. + * 2 ns quanta) over which the number of FECcorrectines is counted. + * Used for creating high FEC correction alarm. + */ +#define XPCSRX_RX_FEC_COR_INTVAL_REG 0x88 + +/* Number of 161 MHz clock period for the ber interval (default is1ms). */ +#define RX_FEC_COR_INTVAL_CFGXPCSRXFECCORINTVAL_SHIFT 0 +#define RX_FEC_COR_INTVAL_CFGXPCSRXFECCORINTVAL_MASK 0xffffff + + +/* + * Register + * + * The threshold on the number of FEC correctoins made over a timerinterval + * that will cause the FEC high correction alarm. + */ +#define XPCSRX_RX_FEC_COR_TRESH_REG 0x8c + +/* + * Number of FEC corrections made over a given time interval that + * willtrigger the FEC high correction alarm (defalut = 0 = off). +*/ +#define RX_FEC_COR_TRESH_CFGXPCSRXFECCORTRESH_SHIFT 0 +#define RX_FEC_COR_TRESH_CFGXPCSRXFECCORTRESH_MASK 0xffffff + + +/* + * Register + * + * Count the number of uncorrectable FEC CW that have been recieved. + */ +#define XPCSRX_RX_FEC_CW_FAIL_CNT_REG 0x90 + +/* The number of uncorrectable FEC CW that have been recieved. */ +#define RX_FEC_CW_FAIL_CNT_RXFECDECCWFAILCNT_SHIFT 0 +#define RX_FEC_CW_FAIL_CNT_RXFECDECCWFAILCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of total FEC CW that have been recievec. + */ +#define XPCSRX_RX_FEC_CW_TOT_CNT_REG 0x94 + +/* The number of total FEC CW that have been recieved. */ +#define RX_FEC_CW_TOT_CNT_RXFECDECCWTOTCNT_SHIFT 0 +#define RX_FEC_CW_TOT_CNT_RXFECDECCWTOTCNT_MASK 0xffffffff + + +/* + * Register + * + * The number of correctoins made in the FEC CW that have been recieved. + * Lower 32 bits of a 39 bit stat. + * Read this location before reading the upper 7 bis + * atXPCSRX_FEC_CORRECT_CNT_UPERER. + */ +#define XPCSRX_RX_FEC_CORRECT_CNT_LO_REG 0x98 + +/* Lower 32 bits of number of bits that the FEC corrected. */ +#define RX_FEC_CORRECT_CNT_LO_RXFECDECERRCORCNTLOWER_SHIFT 0 +#define RX_FEC_CORRECT_CNT_LO_RXFECDECERRCORCNTLOWER_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of correctoins made in the FEC CW that have been recieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * Read this location after reading the lower 32 bits + * atXPCSRX_FEC_CORRECT_CNT_LOWER. + */ +#define XPCSRX_RX_FEC_CORRECT_CNT_HI_REG 0x9c + +/* Upper 7 bits number of bits that the FEC corrected. */ +#define RX_FEC_CORRECT_CNT_HI_RXFECDECERRCORCNTUPPER_SHIFT 0 +#define RX_FEC_CORRECT_CNT_HI_RXFECDECERRCORCNTUPPER_MASK 0xff + + +/* + * Register + * + * The number of correctoins made in the FEC CW that have been recieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * This is a HW shadow for the upper bits DO NOT USE. + */ +#define XPCSRX_RX_FEC_CORRECT_CNT_SHADOW_REG 0xa0 + +/* Upper 7 of bits that the FEC corrected. */ +#define RX_FEC_CORRECT_CNT_SHADOW_RXFECDECERRCORCNTSHADOW_SHIFT 0 +#define RX_FEC_CORRECT_CNT_SHADOW_RXFECDECERRCORCNTSHADOW_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to ones in the FEC CW that have + * beenrecieved. + * Lower 32 bits of a 39 bit stat. + * Read this location before reading the upper 7 bis + * atXPCSRX_FEC_CORRECT_CNT_UPPER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ONES_COR_CNT_LO_REG 0xa4 + +/* The number of ones that are correctd by the FEC decoder. */ +#define RX_FEC_ONES_COR_CNT_LO_RXFECDECONESCORCNTLOWER_SHIFT 0 +#define RX_FEC_ONES_COR_CNT_LO_RXFECDECONESCORCNTLOWER_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of correctoins made to ones in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * Read this location after reading the lower 32 bits + * atXPCSRX_FEC_CORRECT_CNT_LOWER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ONES_COR_CNT_HI_REG 0xa8 + +/* The number of ones that are correctd by the FEC decoder. */ +#define RX_FEC_ONES_COR_CNT_HI_RXFECDECONESCORCNTUPPER_SHIFT 0 +#define RX_FEC_ONES_COR_CNT_HI_RXFECDECONESCORCNTUPPER_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to ones in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * This is a HW shadow for the upper bits DO NOT USE. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ONES_COR_CNT_SHADOW_REG 0xac + +/* The number of ones that are correctd by the FEC decoder. */ +#define RX_FEC_ONES_COR_CNT_SHADOW_RXFECDECONESCORCNTSHADOW_SHIFT 0 +#define RX_FEC_ONES_COR_CNT_SHADOW_RXFECDECONESCORCNTSHADOW_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to zeros in the FEC CW that have + * beenrecieved. + * Lower 32 bits of a 39 bit stat. + * Read this location before reading the upper 7 bis + * atXPCSRX_FEC_CORRECT_CNT_UPPER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ZEROS_COR_CNT_LO_REG 0xb0 + +/* The number of zeros that are correctd by the FEC decoder. */ +#define RX_FEC_ZEROS_COR_CNT_LO_RXFECDECZEROSCORCNTLOWER_SHIFT 0 +#define RX_FEC_ZEROS_COR_CNT_LO_RXFECDECZEROSCORCNTLOWER_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of correctoins made to zeros in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * Read this location after reading the lower 32 bits + * atXPCSRX_FEC_CORRECT_CNT_LOWER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ZEROS_COR_CNT_HI_REG 0xb4 + +/* The number of zeros that are correctd by the FEC decoder. */ +#define RX_FEC_ZEROS_COR_CNT_HI_RXFECDECZEROSCORCNTUPPER_SHIFT 0 +#define RX_FEC_ZEROS_COR_CNT_HI_RXFECDECZEROSCORCNTUPPER_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to zeros in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * This is a HW shadow for the upper bits DO NOT USE. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ZEROS_COR_CNT_SHADOW_REG 0xb8 + +/* The number of zeros that are correctd by the FEC decoder. */ +#define RX_FEC_ZEROS_COR_CNT_SHADOW_RXFECDECZEROSCORCNTSHADOW_SHIFT 0 +#define RX_FEC_ZEROS_COR_CNT_SHADOW_RXFECDECZEROSCORCNTSHADOW_MASK 0xff + + +/* + * Register - read-only + * + * Captures the write and read pointer for the FEC decoder when a + * faildecode occurs. + */ +#define XPCSRX_RX_FEC_STOP_ON_ERR_READ_POINTER_REG 0xbc + +/* + * Captures the read pointer for the FEC decoder when a fail decodehappens. + * This is for the feature that freezes the FEC decoder when decodesfails. + * Requires cfgXPcsRxFecStopOnErr = 1. +*/ +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRRDPTR_SHIFT 8 +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRRDPTR_MASK 0xff00 + +/* + * Captures the write pointer for the FEC decoder when a fail + * decodehappens. + * This is for the feature that freezes the FEC decoder when decodesfails. + * Requires cfgXPcsRxFecStopOnErr = 1. +*/ +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRWRPTR_SHIFT 0 +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRWRPTR_MASK 0xff + + +/* + * Register - read-only + * + * Captures the location within the burst where the stop on error occured + */ +#define XPCSRX_RX_FEC_STOP_ON_ERR_BURST_LOCATION_REG 0xc0 + +/* + * Captures the location witing hte burst where the stop on erroroccured. + * This is in ticks of 161 clocks. + * Requires cfgXPcsRxFecStopOnErr = 1. +*/ +#define RX_FEC_STOP_ON_ERR_BURST_LOCATION_RXFECSTOPONERRBRSTLOC_SHIFT 0 +#define RX_FEC_STOP_ON_ERR_BURST_LOCATION_RXFECSTOPONERRBRSTLOC_MASK 0xffffff + + +/* + * Register + * + * Count the number of 64b/66b decode errors. + */ +#define XPCSRX_RX_64B66B_FAIL_CNT_REG 0xc4 + +/* The number of 64b/66b decoed errors. */ +#define RX_64B66B_FAIL_CNT_RX64B66BDECERRCNT_SHIFT 0 +#define RX_64B66B_FAIL_CNT_RX64B66BDECERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of bad SH during CW lock. + */ +#define XPCSRX_RX_FRMR_BAD_SH_CNT_REG 0xc8 + +/* The number bad SH while in CW lock. */ +#define RX_FRMR_BAD_SH_CNT_RXFRMRBADSHCNT_SHIFT 0 +#define RX_FRMR_BAD_SH_CNT_RXFRMRBADSHCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of errors in test pattern 2 while in patter lock. + */ +#define XPCSRX_RX_PSUDO_CNT_REG 0xcc + +/* The number of errors in test pattern 2 while in pattern lock. */ +#define RX_PSUDO_CNT_RXTESTPSUDOERRCNT_SHIFT 0 +#define RX_PSUDO_CNT_RXTESTPSUDOERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of errors in test pattern PRBS-31 while in patternlock. + */ +#define XPCSRX_RX_PRBS_CNT_REG 0xd0 + +/* The number of errors in test pattern PRBS-31 while in patern lock. */ +#define RX_PRBS_CNT_RXTESTPRBSERRCNT_SHIFT 0 +#define RX_PRBS_CNT_RXTESTPRBSERRCNT_MASK 0xffffffff + + +/* + * Register + * + * The interval over which SH BER is mearsured in the framer. + * Used togenerate xPcsRxStatFrmrHighBer alarm. + */ +#define XPCSRX_RX_BER_INTVAL_REG 0xd4 + +/* + * Number of 161 MHz clock period for the interval over which SH BER + * iscounter in the framer(default is 256 us). +*/ +#define RX_BER_INTVAL_CFGXPCSRXFRMRBERINTVAL_SHIFT 0 +#define RX_BER_INTVAL_CFGXPCSRXFRMRBERINTVAL_MASK 0xffffff + + +/* + * Register + * + * The threshold on the number of bit errors made over a timer intervalthat + * will cause the high BER alarm. + */ +#define XPCSRX_RX_BER_TRESH_REG 0xd8 + +/* + * Number of SH error permitted over the BER interval. + * (defalut = 0 =off). +*/ +#define RX_BER_TRESH_CFGXPCSRXFRMRBERTRESH_SHIFT 0 +#define RX_BER_TRESH_CFGXPCSRXFRMRBERTRESH_MASK 0x1ff + + +/* + * Register + * + * Count the number of SOP detected in the 64b/66b decoder. + */ +#define XPCSRX_RX_64B66B_START_CNT_REG 0xdc + +/* The number of SOP that the 64b/66b decoder found. */ +#define RX_64B66B_START_CNT_RX64B66BDECSTARTCNT_SHIFT 0 +#define RX_64B66B_START_CNT_RX64B66BDECSTARTCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of good packets detected in the idle insertion logic. + * Based on finding SOP followed by EOP. + */ +#define XPCSRX_RX_IDLE_GOOD_PKT_CNT_REG 0xe0 + +/* The number of good packets found by the idle insertion logic. */ +#define RX_IDLE_GOOD_PKT_CNT_RXIDLEGOODPKTCNT_SHIFT 0 +#define RX_IDLE_GOOD_PKT_CNT_RXIDLEGOODPKTCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of bad packets detected in the idle insertion logic. + */ +#define XPCSRX_RX_IDLE_ERR_PKT_CNT_REG 0xe4 + +/* The number of errored packets found by the idle insertion logic. */ +#define RX_IDLE_ERR_PKT_CNT_RXIDLEERRPKTCNT_SHIFT 0 +#define RX_IDLE_ERR_PKT_CNT_RXIDLEERRPKTCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of EOP detected in the 64b/66b decoder. + */ +#define XPCSRX_RX_64B66B_STOP_CNT_REG 0xe8 + +/* The number of EOP that the 64b/66b decoder found. */ +#define RX_64B66B_STOP_CNT_RX64B66BDECSTOPCNT_SHIFT 0 +#define RX_64B66B_STOP_CNT_RX64B66BDECSTOPCNT_MASK 0xffffffff + + +/* + * Register + * + * Test mode used in FPGA only. + * Count the number of burst recieved out oforder. + */ +#define XPCSRX_RX_BURST_OUT_ODR_CNT_REG 0xec + +/* The number of times recieved burst sequence number was out of order. */ +#define RX_BURST_OUT_ODR_CNT_RXBURSTSEQOUTOFORDERCNT_SHIFT 0 +#define RX_BURST_OUT_ODR_CNT_RXBURSTSEQOUTOFORDERCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Gives delay values for two different DA through the IDLE insertprocess. + */ +#define XPCSRX_RX_IDLE_DA_JIT_DLY_REG 0xf0 + +/* Previous delay for DA through the idle insert process. */ +#define RX_IDLE_DA_JIT_DLY_RXIDLELASTDACNT_SHIFT 16 +#define RX_IDLE_DA_JIT_DLY_RXIDLELASTDACNT_MASK 0x1ff0000 + +/* Current delay for DA through the idle insert process. */ +#define RX_IDLE_DA_JIT_DLY_RXIDLEDACNT_SHIFT 0 +#define RX_IDLE_DA_JIT_DLY_RXIDLEDACNT_MASK 0x1ff + + +/* + * Register + * + * Provides data port access to all XPCS RX RAMS. + * The data port functions as a means to access RAMs by way ofindirection. + * The address, commands and busy status are located in this register. + * XPCSRX_DPORT_CTLThe data to be read or written are accesses at: + * XPCSRX_DPORT_DATA0XPCSRX_DPORT_DATA1XPCSRX_DPORT_DATA2XPCSRX_DPORT_DATA3XPCSRX_DPORT_DATA4The + * control to allow this data port to access data path RAMs arelocated: + * XPCSRX_DPORT_ACCThe control to disable clear on read for XPCS RX Stats + * Ram is located: + * XPCSRX_DPORT_FEC_STATS_CTLThe capture FIFO RAM, FEC decode RAM, FEC + * enqueue RAM and idle insertRAMare data path rams. + * In order to access them a select must be set. + * Thisdisables the data path and allows the data port to have access. + * TheXPCS RXwill not function properly under these conditions. + * Accesses to theseRAMsby this data port is for test only. + * The FEC decode stats RAM also has a control bit associated with it. + * Thiscontrol bit is not associated with permitting access to this RAM. + * Accessesto this RAM by this data port is intended for both the normal + * mode ofoperation and testing. + * This bit is to disable the clear on readfunctionthat occurs with normal + * read accesses to this RAM by this data port. + * CONTRLS: + * To access the capture FIFO RAM, FEC decode RAM, FEC enqueue RAM or + * idleinsert RAM, set the data port select bit in XPCSRX_DPORT_ACC. + * To access the FEC decode stats RAM without clear on read set, set + * thedisable bit in XPCSRX_DPORT_FEC_STATS_CTL. + * Do not set this innormal operation. + * It is intended that statistics are clear on read. + * For writes, set the write values in the data registers. + * Set the address, RAM select and control fields in this register. + * Poll the busy bit in this register. + * Once the busy bit is not set the data port has completed the command. + * For reads, read the data register after the busy bit clears. + * Statistics and Data Fields descriptions for the RAMS: + * RAM | Type | Size | ecc field | + * datafield============================================================================Capture + * FIFO | PD | 256x80 | [79: + * 72] |[71: + * 0]FEC enqueue | RF | 32x80 | [79: + * 72] |[71: + * 0]FEC decode | PD | 256x80 | [79: + * 72] |[71: + * 0]FEC stats | SP | 128x151 | [150: + * 142] |[141: + * 0]Idle insert | PD | 256x82 | [81: + * 73] |[73: + * 0]Data fields descripton: + * Capture FIFO[71: + * 64] XPCS RX control[63: + * 0] XPCS RX dataFEC enqueue[71: + * 0] aligned 66b data geared up to 72bFEC decode[71: + * 0] aligned 66b data geared up to 72bFEC stats RAM[141: + * 103] ones corected statistics[102: + * 64] zeros corrected statistics[63: + * 32] code words decode fails statistics[31: + * 0] code words total statisticsIdle insert[73: + * 72] number of invalid times between valid[71: + * 68] control indication[69: + * 36] four bytes of 8b data[35: + * 32] control indication[31: + * 0] four bytes of 8b data + */ +#define XPCSRX_RX_DPORT_CTL_REG 0xf4 + +/* Data port busy. */ +#define RX_DPORT_CTL_XPCSRXDPBUSY_MASK 0x80000000 + +/* Data port error (always 0 for XPCS RX). */ +#define RX_DPORT_CTL_XPCSRXDPERR_MASK 0x40000000 + +/* Data port command (0 = read and 1 = write). */ +#define RX_DPORT_CTL_CFGXPCSRXDPCTL_SHIFT 20 +#define RX_DPORT_CTL_CFGXPCSRXDPCTL_MASK 0xff00000 + +/* + * Data port RAM select : + * 0 = capture FIFO RAM1 = FEC decode RAM2 = FEC stats RAM3 = FEC enqueue + * RAM4 = idle insert RAM +*/ +#define RX_DPORT_CTL_CFGXPCSRXDPRAMSEL_SHIFT 16 +#define RX_DPORT_CTL_CFGXPCSRXDPRAMSEL_MASK 0xf0000 + +/* + * Data port address. + * NOTE: + * all 16 bits are available but the largest ram in XPCS + * RXXPcsRxCapFifoRam. + * vbis x256. +*/ +#define RX_DPORT_CTL_CFGXPCSRXDPADDR_SHIFT 0 +#define RX_DPORT_CTL_CFGXPCSRXDPADDR_MASK 0xffff + + +/* + * Register + * + * Rreadback register and write register for data port accesses. + */ +#define XPCSRX_RX_DPORT_DATA0_REG 0xf8 + +/* Data port data bits 31 to 0. */ +#define RX_DPORT_DATA0_XPCSRXDPDATA0_SHIFT 0 +#define RX_DPORT_DATA0_XPCSRXDPDATA0_MASK 0xffffffff + + +/* + * Register + * + * Rreadback register and write register for data port accesses. + */ +#define XPCSRX_RX_DPORT_DATA1_REG 0xfc + +/* Data port data bits 63 to 32. */ +#define RX_DPORT_DATA1_XPCSRXDPDATA1_SHIFT 0 +#define RX_DPORT_DATA1_XPCSRXDPDATA1_MASK 0xffffffff + + +/* + * Register + * + * Rreadback register and write register for data port accesses. + */ +#define XPCSRX_RX_DPORT_DATA2_REG 0x100 + +/* Data port data bits 95 to 64. */ +#define RX_DPORT_DATA2_XPCSRXDPDATA2_SHIFT 0 +#define RX_DPORT_DATA2_XPCSRXDPDATA2_MASK 0xffffffff + + +/* + * Register + * + * Provides data port access to all XPCS RX RAMS. + */ +#define XPCSRX_RX_DPORT_ACC_REG 0x104 + +/* Disable data path and selects data port for RAM access. */ +#define RX_DPORT_ACC_CFGXPCSRXIDLERAMDPSEL_MASK 0x8 + +/* Disable data path and selects data port for RAM access. */ +#define RX_DPORT_ACC_CFGXPCSRXFECDECRAMDPSEL_MASK 0x4 + +/* Disable data path and selects data port for RAM access. */ +#define RX_DPORT_ACC_CFGXPCSRXFECNQUERAMDPSEL_MASK 0x2 + + +/* + * Register + * + * Interrupt status for XPcsRx RAMs ECC. + */ +#define XPCSRX_RX_RAM_ECC_INT_STAT_REG 0x108 + +/* Idle insert FIFO RAM init done interrupt. */ +#define RX_RAM_ECC_INT_STAT_INTRXIDLERAMINITDONE_MASK 0x10 + +/* FEC enqueue FIFO RAM init done interrupt. */ +#define RX_RAM_ECC_INT_STAT_INTRXFECNQUERAMINITDONE_MASK 0x8 + +/* FEC decode FIFO RAM init done interrupt. */ +#define RX_RAM_ECC_INT_STAT_INTRXFECDECRAMINITDONE_MASK 0x2 + + +/* + * Register + * + * Interrupt mask for XPcsRx RAMs ECC. + */ +#define XPCSRX_RX_RAM_ECC_INT_MSK_REG 0x10c + +/* Idle insert FIFO RAM init done interrupt mask. */ +#define RX_RAM_ECC_INT_MSK_MSKRXIDLERAMINITDONE_MASK 0x10 + +/* FEC enqueue FIFO RAM init done interrupt mask. */ +#define RX_RAM_ECC_INT_MSK_MSKRXFECNQUERAMINITDONE_MASK 0x8 + +/* FEC decode FIFO RAM init done interrupt mask. */ +#define RX_RAM_ECC_INT_MSK_MSKRXFECDECRAMINITDONE_MASK 0x2 + + +/* + * Register + * + * DFT test mode for PD RAMs + */ +#define XPCSRX_RX_DFT_TESTMODE_REG 0x110 + +/* DFT test mode for PD RAMs */ +#define RX_DFT_TESTMODE_TM_PD_SHIFT 0 +#define RX_DFT_TESTMODE_TM_PD_MASK 0x3ff + + +/* + * Register + * + * Control register to selectively power one or more rowblocks of thememory + * to acieve improved power reduction. + * There is one bit perrowblock for the specific RAM. + * All array contents are lost for therowblocks that are powered down. + * the rowblocks in operational modewill be available for read/write and + * data retention. + * 1 = power down0 = operationalNOTE: + * When powering up, do NOT power up more than one array in one RAMat a + * time. + * It may damage the RAM. + */ +#define XPCSRX_RX_RAM_POWER_PDA_CTL0_REG 0x114 + +/* Array power down control for FEC decode RAM */ +#define RX_RAM_POWER_PDA_CTL0_CFGXPCSRXIDLERAMPDA_MASK 0x8 + +/* Array power down control for FEC decode RAM */ +#define RX_RAM_POWER_PDA_CTL0_CFGXPCSRXFECDECRAMPDA_MASK 0x2 + + +/* + * Register + * + * More Interrupt status for XPcsRx module. + */ +#define XPCSRX_RX_INT_STAT1_REG 0x118 + +/* trailing start at the end of burst */ +#define RX_INT_STAT1_INTRX64B66BTRAILSTART_MASK 0x8 + +/* two stops in a row detected */ +#define RX_INT_STAT1_INTRX64B66BTWOSTOP_MASK 0x4 + +/* two starts in a row detected */ +#define RX_INT_STAT1_INTRX64B66BTWOSTART_MASK 0x2 + +/* leading stop at the start of burst */ +#define RX_INT_STAT1_INTRX64B66BLEADSTOP_MASK 0x1 + + +/* + * Register + * + * More Interrupt mask for XPcsRx module. + */ +#define XPCSRX_RX_INT_MSK1_REG 0x11c + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BTRAILSTART_MASK 0x8 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BTWOSTOP_MASK 0x4 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BTWOSTART_MASK 0x2 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BLEADSTOP_MASK 0x1 + + +/* + * Register + * + * Spare RW bits + */ +#define XPCSRX_RX_SPARE_CTL_REG 0x120 + +/* Spare RW bits */ +#define RX_SPARE_CTL_CFGXPCSRXSPARE_SHIFT 0 +#define RX_SPARE_CTL_CFGXPCSRXSPARE_MASK 0xffffffff + + +#endif /* ! EPON_XPCSRX_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcstx.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcstx.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcstx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcstx.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,454 @@ +#ifndef EPON_XPCSTX_H_ +#define EPON_XPCSTX_H_ + +/* relative to epon */ +#define XPCSTX_OFFSET_0 0x3800 + +/* + * Register + * + * XPCS-TX control register. + */ +#define XPCSTX_TX_CONTROL_REG 0x0 + +/* Enable remote fault detection. */ +#define TX_CONTROL_CFGENRMTFAULTDET125_MASK 0x8000 + +/* Enable the laser enable tri-state output. */ +#define TX_CONTROL_CFGLSRTRISTATEEN125_MASK 0x4000 + +/* + * Debug function has been deprecated. + * It is now utilized to enableIDLE packet support : + * 0 - enable; 1 - disable. +*/ +#define TX_CONTROL_CFGENSEQNUM125_MASK 0x2000 + +/* + * Enable the scrambler to run continously. + * 0 - Only during burst; 1 -Continuosly. +*/ +#define TX_CONTROL_CFGENSCRMBCONT125_MASK 0x800 + +/* + * Laser on polarity : + * 0 - laser on active low; 1 - laser on activehigh. +*/ +#define TX_CONTROL_CFGLSRENACTHI125_MASK 0x400 + +/* Enable laser on always. */ +#define TX_CONTROL_CFGENLSRALWAYS125_MASK 0x200 + +/* Enable laser until the end-of-grant, non-strict IEEE mode. */ +#define TX_CONTROL_CFGENLSRTILENDSLOT125_MASK 0x100 + +/* Flip Gearbox's byte output to SERDES. */ +#define TX_CONTROL_CFGTXOUTBYTEFLIP125_MASK 0x80 + +/* + * Enable transmit Gearbox's output. + * 0 - disable transmit; 1 - enabletransmit. +*/ +#define TX_CONTROL_CFGENTXOUT125_MASK 0x40 + +/* + * Enable transmit scrambler. + * 0 - disable scrambler; 1 - enablescrambler. +*/ +#define TX_CONTROL_CFGENTXSCRB125_MASK 0x20 + +/* + * Enables upstream FEC : + * 0 - nonFEC; 1 - FEC. +*/ +#define TX_CONTROL_CFGENTXFEC125_MASK 0x10 + +/* Indicates XPCS-TX not ready for operation. */ +#define TX_CONTROL_PCSTXNOTRDY_MASK 0x8 + +/* + * Active low reset for RAM data port. + * RAM init starts upondeassertion. + * Bit pcstxNotRdy is to be polled for completion. +*/ +#define TX_CONTROL_PCSTXDTPORTRSTN_MASK 0x2 + +/* + * Reset control for XPCS-TX module. + * 0 - Reset. + * 1 - Normal Operation. +*/ +#define TX_CONTROL_PCSTXRSTN_MASK 0x1 + + +/* + * Register + * + */ +#define XPCSTX_TX_INT_STAT_REG 0x4 + +/* + * Indicates laser enable on time exceeed the maximum threshold, asdefined + * by register XPCS_TX_LASER_MONITOR_MAX_THRESH. +*/ +#define TX_INT_STAT_LASERONMAX_MASK 0x80 + +/* Indicates laser enable deassertion. */ +#define TX_INT_STAT_LASEROFF_MASK 0x40 + +/* [FATAL] Indicates scheduled time lagged current MPCP time. */ +#define TX_INT_STAT_GRANTLAGERR_MASK 0x20 + +/* [NON-FATAL] Indicates back-2-back grants. */ +#define TX_INT_STAT_BACK2BACKGNT_MASK 0x8 + +/* [FATAL] FEC transmit FIFO underrun. */ +#define TX_INT_STAT_FECUNDERRUN_MASK 0x4 + +/* [FATAL] Gearbox underrun. */ +#define TX_INT_STAT_GEARBOXUNDERRUN_MASK 0x2 + +/* [NON-FATAL] Indicates grant slot is too short for transfer. */ +#define TX_INT_STAT_GNTTOOSHORT_MASK 0x1 + + +/* + * Register + * + * Interrupt masks, active low : + * 0 - mask interrupt; 1 - enable interrupt. + */ +#define XPCSTX_TX_INT_MASK_REG 0x8 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_LASERONMAXMASK_MASK 0x80 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_LASEROFFMASK_MASK 0x40 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_GRANTLAGERRMSK_MASK 0x20 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_BACK2BCKGNTMSK_MASK 0x8 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_FECUNDERRUNMSK_MASK 0x4 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_GEARBOXUNDERRUNMSK_MASK 0x2 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_GNTTOOSHORTMSK_MASK 0x1 + + +/* + * Register + * + * Provides dataPort read/write access to various RAMs. + */ +#define XPCSTX_TX_PORT_COMMAND_REG 0xc + +/* + * Indicates dataPort is in progress. + * Bit must be cleared before thenext dataPort access can be issued. +*/ +#define TX_PORT_COMMAND_DATAPORTBUSY_MASK 0x80000000 + +/* + * Selects the RAM for access : + * 0 - FEC vector RAM. +*/ +#define TX_PORT_COMMAND_PORTSELECT_SHIFT 24 +#define TX_PORT_COMMAND_PORTSELECT_MASK 0x3f000000 + +/* + * Indicates write access : + * 0 - read; 1 - write. +*/ +#define TX_PORT_COMMAND_PORTOPCODE_SHIFT 16 +#define TX_PORT_COMMAND_PORTOPCODE_MASK 0xff0000 + +/* Specifies the RAM address for access. */ +#define TX_PORT_COMMAND_PORTADDRESS_SHIFT 0 +#define TX_PORT_COMMAND_PORTADDRESS_MASK 0xffff + + +/* + * Register + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XPCSTX_TX_DATA_PORT_0_REG 0x10 + +/* + * XPCSTX_VEC_RAM[31: + * 0]. +*/ +#define TX_DATA_PORT_0_PORTDATA0_SHIFT 0 +#define TX_DATA_PORT_0_PORTDATA0_MASK 0xffffffff + + +/* + * Register + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XPCSTX_TX_DATA_PORT_1_REG 0x14 + +/* + * XPCSTX_VEC_RAM[63: + * 32]. +*/ +#define TX_DATA_PORT_1_PORTDATA1_SHIFT 0 +#define TX_DATA_PORT_1_PORTDATA1_MASK 0xffffffff + + +/* + * Register + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XPCSTX_TX_DATA_PORT_2_REG 0x18 + +/* + * [1: + * 0] - XPCSTX_VEC_RAM[66: + * 65]. +*/ +#define TX_DATA_PORT_2_PORTDATA2_SHIFT 0 +#define TX_DATA_PORT_2_PORTDATA2_MASK 0xffffffff + + +/* + * Register + * + * Specifies the sync pattern codeword. + */ +#define XPCSTX_TX_SYNC_PATT_CWORD_LO_REG 0x1c + +/* Defines the low order sync pattern codeword. */ +#define TX_SYNC_PATT_CWORD_LO_CFGSYNCPATCWL_SHIFT 0 +#define TX_SYNC_PATT_CWORD_LO_CFGSYNCPATCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the sync pattern codeword. + */ +#define XPCSTX_TX_SYNC_PATT_CWORD_HI_REG 0x20 + +/* Defines the high order sync pattern codeword. */ +#define TX_SYNC_PATT_CWORD_HI_CFGSYNCPATCWH_SHIFT 0 +#define TX_SYNC_PATT_CWORD_HI_CFGSYNCPATCWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the start-of-burst delimiter codeword. + */ +#define XPCSTX_TX_START_BURST_DEL_CWORD_LO_REG 0x24 + +/* Defines the low order start-of-burst delimiter codeword. */ +#define TX_START_BURST_DEL_CWORD_LO_CFGSTRTBRSTDLMTRCWL_SHIFT 0 +#define TX_START_BURST_DEL_CWORD_LO_CFGSTRTBRSTDLMTRCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the start-of-burst delimiter codeword. + */ +#define XPCSTX_TX_START_BURST_DEL_CWORD_HI_REG 0x28 + +/* Defines the high order start-of-burst delimiter codeword. */ +#define TX_START_BURST_DEL_CWORD_HI_CFGSTRTBRSTDLMTRCWH_SHIFT 0 +#define TX_START_BURST_DEL_CWORD_HI_CFGSTRTBRSTDLMTRCWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the end-of-burst terminating codeword. + */ +#define XPCSTX_TX_END_BURST_DEL_CWORD_LO_REG 0x2c + +/* Defines the low order terminating codeword. */ +#define TX_END_BURST_DEL_CWORD_LO_CFGENDBRSTDLMTRCWL_SHIFT 0 +#define TX_END_BURST_DEL_CWORD_LO_CFGENDBRSTDLMTRCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the end-of-burst terminating codeword. + */ +#define XPCSTX_TX_END_BURST_DEL_CWORD_HI_REG 0x30 + +/* Defines the high order terminating codeword. */ +#define TX_END_BURST_DEL_CWORD_HI_CFGENDBRSTDLMTRCWH_SHIFT 0 +#define TX_END_BURST_DEL_CWORD_HI_CFGENDBRSTDLMTRCWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the IDLE codeword. + */ +#define XPCSTX_TX_IDLE_CWORD_LO_REG 0x34 + +/* Defines the low order codeword. */ +#define TX_IDLE_CWORD_LO_CFGIDLECWL_SHIFT 0 +#define TX_IDLE_CWORD_LO_CFGIDLECWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the IDLE codeword. + */ +#define XPCSTX_TX_IDLE_CWORD_HI_REG 0x38 + +/* Defines the high order codeword. */ +#define TX_IDLE_CWORD_HI_CFGIDLECWH_SHIFT 0 +#define TX_IDLE_CWORD_HI_CFGIDLECWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the codeword in between burst. + */ +#define XPCSTX_TX_BURST_PATT_CWORD_LO_REG 0x3c + +/* Defines the low order burst delimiter codeword. */ +#define TX_BURST_PATT_CWORD_LO_CFGBURSTPATCWL_SHIFT 0 +#define TX_BURST_PATT_CWORD_LO_CFGBURSTPATCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the codeword in between burst. + */ +#define XPCSTX_TX_BURST_PATT_CWORD_HI_REG 0x40 + +/* Defines the high order burst delimiter codeword. */ +#define TX_BURST_PATT_CWORD_HI_CFGBURSTPATCWH_SHIFT 0 +#define TX_BURST_PATT_CWORD_HI_CFGBURSTPATCWH_MASK 0xffffffff + + +/* + * Register + * + * Provides control for the laser enable. + */ +#define XPCSTX_TX_LASER_TIME_REG 0x44 + +/* + * Specifies the laser pipeline delay, in unit of 6. + * 2ns (161 MHzclock). +*/ +#define TX_LASER_TIME_CFGLASERPIPE125_SHIFT 16 +#define TX_LASER_TIME_CFGLASERPIPE125_MASK 0x3f0000 + +/* + * Specifies the laser off delay to the actual laser off time, value X. + * Resulting delay = INT(X*2. + * 5)*6. + * 2 ns, based on 161 MHz clock. +*/ +#define TX_LASER_TIME_CFGLASEROFFDLYTQ125_SHIFT 8 +#define TX_LASER_TIME_CFGLASEROFFDLYTQ125_MASK 0xf00 + +/* + * Specifies the laser enable delay to the actual laser on time, valueX. + * Resulting delay = INT(X*2. + * 5)*6. + * 2 ns, based on 161 MHz clock . +*/ +#define TX_LASER_TIME_CFGLASERONDLYTQ125_SHIFT 0 +#define TX_LASER_TIME_CFGLASERONDLYTQ125_MASK 0xf + + +/* + * Register + * + * Specifies the MAC mode of operation. + */ +#define XPCSTX_TX_MAC_MODE_REG 0x48 + +/* Enable point-to-point transmission without grant. */ +#define TX_MAC_MODE_CFGENNOGNTXMT125_MASK 0x2 + + +/* + * Register + * + * Provides control for laser monitor. + */ +#define XPCSTX_TX_LASER_MONITOR_CTL_REG 0x4c + +/* Status of laser enable, directly from I/O pin. */ +#define TX_LASER_MONITOR_CTL_LASERENSTATUS_MASK 0x20 + +/* + * Laser monitor polarity. + * 0 - active low; 1 - active high. +*/ +#define TX_LASER_MONITOR_CTL_CFGLSRMONACTHI_MASK 0x10 + +/* + * Laser monitor reset. + * 0 - Reset; 1 - Normal operation. +*/ +#define TX_LASER_MONITOR_CTL_LASERMONRSTN_MASK 0x1 + + +/* + * Register + * + * Specifies maximum threshold of laser_on assertion before interrupt + * isgenerated. + */ +#define XPCSTX_TX_LASER_MONITOR_MAX_THRESH_REG 0x50 + +/* Maximum assertion threshold, in unit of TQ. */ +#define TX_LASER_MONITOR_MAX_THRESH_CFGLSRMONMAXTQ_SHIFT 0 +#define TX_LASER_MONITOR_MAX_THRESH_CFGLSRMONMAXTQ_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates the burst length of current grant, in unit of TQ (16 ns). + */ +#define XPCSTX_TX_LASER_MONITOR_BURST_LEN_REG 0x54 + +/* Indicates the laser-on time of the burst that set laserOffinterrupt. */ +#define TX_LASER_MONITOR_BURST_LEN_LASERONLENGTH_SHIFT 0 +#define TX_LASER_MONITOR_BURST_LEN_LASERONLENGTH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the number of burst. + * Clear on read. + */ +#define XPCSTX_TX_LASER_MONITOR_BURST_COUNT_REG 0x58 + +/* + * This values increments on deassertion edge of laser enable. + * Peg atmax value of 0xFFFFFFFF +*/ +#define TX_LASER_MONITOR_BURST_COUNT_BURSTCNT_SHIFT 0 +#define TX_LASER_MONITOR_BURST_COUNT_BURSTCNT_MASK 0xffffffff + + +#endif /* ! EPON_XPCSTX_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/serdes_regs.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/serdes_regs.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/serdes_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/serdes_regs.h 2023-05-31 17:11:03.413680496 +0200 @@ -0,0 +1,294 @@ +/*************************************************************************** +// Serdes registers in full chip address map + ***************************************************************************/ +#define PCS_ID 0x0000 + +#define DEVID_0 0x0000 +#define DEVID_1 0x0800 + +#define serdes_PLL_0 0x0000 +#define serdes_PLL_1 0x0100 + +#define LANE_0 0x0000 +#define LANE_1 0x0001 +#define LANE_2 0x0002 +#define LANE_3 0x0003 +#define LANE_BRDCST 0x00FF +#define LANE_01 0x0200 +#define LANE_23 0x0201 + +#define DSC_A_cdr_control_0 0xD001 +#define DSC_A_cdr_control_1 0xD002 +#define DSC_A_cdr_control_2 0xD003 +#define DSC_A_rx_pi_control 0xD004 +#define DSC_A_cdr_status_integ_reg 0xD005 +#define DSC_A_cdr_status_phase_error 0xD006 +#define DSC_A_rx_pi_cnt_bin_d 0xD007 +#define DSC_A_rx_pi_cnt_bin_p 0xD008 +#define DSC_A_rx_pi_cnt_bin_m 0xD009 +#define DSC_A_rx_pi_diff_bin 0xD00A +#define DSC_A_trnsum_cntl_5 0xD00B +#define DSC_A_dsc_uc_ctrl 0xD00D +#define DSC_A_dsc_scratch 0xD00E +#define DSC_B_dsc_sm_ctrl_0 0xD010 +#define DSC_B_dsc_sm_ctrl_1 0xD011 +#define DSC_B_dsc_sm_ctrl_2 0xD012 +#define DSC_B_dsc_sm_ctrl_3 0xD013 +#define DSC_B_dsc_sm_ctrl_4 0xD014 +#define DSC_B_dsc_sm_ctrl_5 0xD015 +#define DSC_B_dsc_sm_ctrl_6 0xD016 +#define DSC_B_dsc_sm_ctrl_7 0xD017 +#define DSC_B_dsc_sm_ctrl_8 0xD018 +#define DSC_B_dsc_sm_ctrl_9 0xD019 +#define DSC_B_dsc_sm_status_dsc_lock 0xD01A +#define DSC_B_dsc_sm_status_dsc_state_one_hot 0xD01B +#define DSC_B_dsc_sm_status_dsc_state_eee_one_hot 0xD01C +#define DSC_B_dsc_sm_status_restart 0xD01D +#define DSC_B_dsc_sm_status_dsc_state 0xD01E +#define DSC_C_dfe_common_ctl 0xD020 +#define DSC_C_dfe_1_ctl 0xD021 +#define DSC_C_dfe_1_pat_ctl 0xD022 +#define DSC_C_dfe_2_ctl 0xD023 +#define DSC_C_dfe_2_pat_ctl 0xD024 +#define DSC_C_dfe_3_ctl 0xD025 +#define DSC_C_dfe_3_pat_ctl 0xD026 +#define DSC_C_dfe_4_ctl 0xD027 +#define DSC_C_dfe_4_pat_ctl 0xD028 +#define DSC_C_dfe_5_ctl 0xD029 +#define DSC_C_dfe_5_pat_ctl 0xD02A +#define DSC_C_dfe_vga_override 0xD02B +#define DSC_C_vga_ctl 0xD02C +#define DSC_C_vga_pat_eyediag_ctl 0xD02D +#define DSC_C_p1_frac_offs_ctl 0xD02E +#define DSC_D_trnsum_ctl_1 0xD030 +#define DSC_D_trnsum_ctl_2 0xD031 +#define DSC_D_trnsum_ctl_3 0xD032 +#define DSC_D_trnsum_ctl_4 0xD033 +#define DSC_D_trnsum_sts_1 0xD034 +#define DSC_D_trnsum_sts_2 0xD035 +#define DSC_D_trnsum_sts_3 0xD036 +#define DSC_D_trnsum_sts_4 0xD037 +#define DSC_D_trnsum_sts_5 0xD038 +#define DSC_D_trnsum_sts_6 0xD039 +#define DSC_D_vga_p1eyediag_sts 0xD03A +#define DSC_D_dfe_1_sts 0xD03B +#define DSC_D_dfe_2_sts 0xD03C +#define DSC_D_dfe_3_4_5_sts 0xD03D +#define DSC_D_vga_tap_bin 0xD03E +#define DSC_E_dsc_e_ctrl 0xD040 +#define DSC_E_dsc_e_pf_ctrl 0xD041 +#define DSC_E_dsc_e_pf2_lowp_ctrl 0xD042 +#define DSC_E_dsc_e_offset_adj_data_odd 0xD043 +#define DSC_E_dsc_e_offset_adj_data_even 0xD044 +#define DSC_E_dsc_e_offset_adj_p1_odd 0xD045 +#define DSC_E_dsc_e_offset_adj_p1_even 0xD046 +#define DSC_E_dsc_e_offset_adj_m1_odd 0xD047 +#define DSC_E_dsc_e_offset_adj_m1_even 0xD048 +#define DSC_E_dsc_e_dc_offset 0xD049 +#define DSC_F_ONU10G_looptiming_ctrl_0 0xD050 +#define TX_PI_LBE_tx_pi_control_0 0xD070 +#define TX_PI_LBE_tx_pi_control_1 0xD071 +#define TX_PI_LBE_tx_pi_control_2 0xD072 +#define TX_PI_LBE_tx_pi_control_3 0xD073 +#define TX_PI_LBE_tx_pi_control_4 0xD074 +#define TX_PI_LBE_tx_pi_control_6 0xD076 +#define TX_PI_LBE_tx_pi_status_0 0xD078 +#define TX_PI_LBE_tx_pi_status_1 0xD079 +#define TX_PI_LBE_tx_pi_status_2 0xD07A +#define TX_PI_LBE_tx_pi_status_3 0xD07B +#define TX_PI_LBE_tx_lbe_control_0 0xD07C +#define CKRST_CTRL_OSR_MODE_CONTROL 0xD080 +#define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL 0xD081 +#define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL 0xD082 +#define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL 0xD083 +#define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL 0xD084 +#define CKRST_CTRL_UC_ACK_LANE_CONTROL 0xD085 +#define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL 0xD086 +#define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL 0xD087 +#define CKRST_CTRL_PMD_LANE_MODE_STATUS 0xD088 +#define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS 0xD089 +#define CKRST_CTRL_LN_MASK 0xD08A +#define CKRST_CTRL_OSR_MODE_STATUS 0xD08B +#define CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS 0xD08C +#define CKRST_CTRL_PLL_SELECT_CONTROL 0xD08D +#define CKRST_CTRL_LN_S_RSTB_CONTROL 0xD08E +#define AMS_RX_RX_CONTROL_0 0xD090 +#define AMS_RX_RX_CONTROL_1 0xD091 +#define AMS_RX_RX_CONTROL_2 0xD092 +#define AMS_RX_RX_CONTROL_3 0xD093 +#define AMS_RX_RX_CONTROL_4 0xD094 +#define AMS_RX_RX_INTCTRL 0xD098 +#define AMS_RX_RX_STATUS 0xD099 +#define AMS_TX_TX_CONTROL_0 0xD0A0 +#define AMS_TX_TX_CONTROL_1 0xD0A1 +#define AMS_TX_TX_CONTROL_2 0xD0A2 +#define AMS_TX_TX_INTCTRL 0xD0A8 +#define AMS_TX_TX_STATUS 0xD0A9 +#define AMS_COM_PLL_CONTROL_0 0xD0B0 +#define AMS_COM_PLL_CONTROL_1 0xD0B1 +#define AMS_COM_PLL_CONTROL_2 0xD0B2 +#define AMS_COM_PLL_CONTROL_3 0xD0B3 +#define AMS_COM_PLL_CONTROL_4 0xD0B4 +#define AMS_COM_PLL_CONTROL_5 0xD0B5 +#define AMS_COM_PLL_CONTROL_6 0xD0B6 +#define AMS_COM_PLL_CONTROL_7 0xD0B7 +#define AMS_COM_PLL_CONTROL_8 0xD0B8 +#define AMS_COM_PLL_INTCTRL 0xD0B9 +#define AMS_COM_PLL_STATUS 0xD0BA +#define SIGDET_SIGDET_CTRL_0 0xD0C0 +#define SIGDET_SIGDET_CTRL_1 0xD0C1 +#define SIGDET_SIGDET_CTRL_2 0xD0C2 +#define SIGDET_SIGDET_CTRL_3 0xD0C3 +#define SIGDET_SIGDET_STATUS_0 0xD0C8 +#define TLB_RX_prbs_chk_cnt_config 0xD0D0 +#define TLB_RX_prbs_chk_config 0xD0D1 +#define TLB_RX_dig_lpbk_config 0xD0D2 +#define TLB_RX_tlb_rx_misc_config 0xD0D3 +#define TLB_RX_prbs_chk_en_timer_control 0xD0D4 +#define TLB_RX_dig_lpbk_pd_status 0xD0D8 +#define TLB_RX_prbs_chk_lock_status 0xD0D9 +#define TLB_RX_prbs_chk_err_cnt_msb_status 0xD0DA +#define TLB_RX_prbs_chk_err_cnt_lsb_status 0xD0DB +#define TLB_RX_pmd_rx_lock_status 0xD0DC +#define TLB_TX_patt_gen_config 0xD0E0 +#define TLB_TX_prbs_gen_config 0xD0E1 +#define TLB_TX_rmt_lpbk_config 0xD0E2 +#define TLB_TX_tlb_tx_misc_config 0xD0E3 +#define TLB_TX_tx_pi_loop_timing_config 0xD0E4 +#define TLB_TX_rmt_lpbk_pd_status 0xD0E8 +#define DIG_COM_REVID0 0xD0F0 +#define DIG_COM_RESET_CONTROL_PMD 0xD0F1 +#define DIG_COM_RESET_CONTROL_CORE_DP 0xD0F2 +#define DIG_COM_DEBUG_CONTROL 0xD0F3 +#define DIG_COM_TOP_USER_CONTROL_0 0xD0F4 +#define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL 0xD0F6 +#define DIG_COM_RST_SEQ_TIMER_CONTROL 0xD0F7 +#define DIG_COM_CORE_DP_RESET_STATE_STATUS 0xD0F8 +#define DIG_COM_REVID1 0xD0FA +#define DIG_COM_REVID2 0xD0FE +#define PATT_GEN_patt_gen_seq_0 0xD100 +#define PATT_GEN_patt_gen_seq_1 0xD101 +#define PATT_GEN_patt_gen_seq_2 0xD102 +#define PATT_GEN_patt_gen_seq_3 0xD103 +#define PATT_GEN_patt_gen_seq_4 0xD104 +#define PATT_GEN_patt_gen_seq_5 0xD105 +#define PATT_GEN_patt_gen_seq_6 0xD106 +#define PATT_GEN_patt_gen_seq_7 0xD107 +#define PATT_GEN_patt_gen_seq_8 0xD108 +#define PATT_GEN_patt_gen_seq_9 0xD109 +#define PATT_GEN_patt_gen_seq_10 0xD10A +#define PATT_GEN_patt_gen_seq_11 0xD10B +#define PATT_GEN_patt_gen_seq_12 0xD10C +#define PATT_GEN_patt_gen_seq_13 0xD10D +#define PATT_GEN_patt_gen_seq_14 0xD10E +#define TX_FED_txfir_control1 0xD110 +#define TX_FED_txfir_control2 0xD111 +#define TX_FED_txfir_control3 0xD112 +#define TX_FED_txfir_status1 0xD113 +#define TX_FED_txfir_status2 0xD114 +#define TX_FED_txfir_status3 0xD115 +#define TX_FED_txfir_status4 0xD116 +#define TX_FED_micro_control 0xD117 +#define TX_FED_misc_control1 0xD118 +#define TX_FED_txfir_control4 0xD119 +#define TX_FED_misc_status0 0xD11B +#define PLL_CAL_COM_CTL_0 0xD120 +#define PLL_CAL_COM_CTL_1 0xD121 +#define PLL_CAL_COM_CTL_2 0xD122 +#define PLL_CAL_COM_CTL_3 0xD123 +#define PLL_CAL_COM_CTL_4 0xD124 +#define PLL_CAL_COM_CTL_5 0xD125 +#define PLL_CAL_COM_CTL_6 0xD126 +#define PLL_CAL_COM_CTL_7 0xD127 +#define PLL_CAL_COM_CTL_STATUS_0 0xD128 +#define PLL_CAL_COM_CTL_STATUS_1 0xD129 +#define TXCOM_CL72_tap_preset_control 0xD132 +#define TXCOM_CL72_debug_1_register 0xD133 +#define CORE_PLL_COM_PMD_CORE_MODE_STATUS 0xD150 +#define CORE_PLL_COM_RESET_CONTROL_PLL_DP 0xD152 +#define CORE_PLL_COM_TOP_USER_CONTROL 0xD154 +#define CORE_PLL_COM_UC_ACK_CORE_CONTROL 0xD155 +#define CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS 0xD158 +#define CORE_PLL_COM_CORE_PLL_COM_STATUS_2 0xD159 +#define MICRO_A_ramword 0xD200 +#define MICRO_A_address 0xD201 +#define MICRO_A_command 0xD202 +#define MICRO_A_ram_wrdata 0xD203 +#define MICRO_A_ram_rddata 0xD204 +#define MICRO_A_download_status 0xD205 +#define MICRO_A_sfr_status 0xD206 +#define MICRO_A_mdio_uc_mailbox_msw 0xD207 +#define MICRO_A_mdio_uc_mailbox_lsw 0xD208 +#define MICRO_A_uc_mdio_mailbox_lsw 0xD209 +#define MICRO_A_command2 0xD20A +#define MICRO_A_uc_mdio_mailbox_msw 0xD20B +#define MICRO_A_command3 0xD20C +#define MICRO_A_command4 0xD20D +#define MICRO_A_temperature_status 0xD20E +#define MICRO_B_program_ram_control1 0xD210 +#define MICRO_B_dataram_control1 0xD214 +#define MICRO_B_iram_control1 0xD218 +#define MDIO_MMDSEL_AER_COM_mdio_maskdata 0xFFDB +#define MDIO_MMDSEL_AER_COM_mdio_brcst_port_addr 0xFFDC +#define MDIO_MMDSEL_AER_COM_mdio_mmd_select 0xFFDD +#define MDIO_MMDSEL_AER_COM_mdio_aer 0xFFDE +#define MDIO_BLK_ADDR_BLK_ADDR 0xFFDF + +#define XGXSBLK0_XGXSCTRL 0x8000 +#define XGXSBLK1_LANECTRL0 0x8015 +#define XGXSBLk1_LANECTRL1 0x8016 + +#define XgxsBlk10_tx_pi_control4 0x00008190 + #define tx_pi_sm_enable_override_value (1<<14) // RXSM Status 0x8366 Read & Clear control + +#define SerdesDigital_misc1 0x8308 +#define Digital4_Misc3 0x833c +#define Digital4_Misc4 0x833d +#define Digital5_parDetINDControl1 0x8347 +#define Digital5_parDetINDControl2 0x8348 +#define Digital5_Misc7 0x8349 +#define Digital5_Misc6 0x8345 +#define tx66_Control 0x83b0 +#define FX100_Control3 0x8402 +#define ieee0Blk_MIICntl 0x0000 +#define FX100_Control1 0x8400 +#define rx66b1_rx66b1_Control1 0x8441 + #define rfifo_ptr_sw_rst (1<<0) + +#define XGXSBLK4_xgxsStatus1 0x00008122 +#define XgxsStatus1_LinkStat (1<<9) +#define XgxsStatus1_Speed_Mask (0xf) +#define XgxsStatus1_Speed_10G (0x6) + +#define SerdesDigital_Control1000X1 0x8300 +#define SerdesDigital_SgmiiMasterMode (1<<5) +#define SerdesDigital_SgmiiAutoMode (1<<4) +#define SerdesDigital_InvertSigDet (1<<3) +#define SerdesDigital_SigDetEn (1<<2) +#define SerdesDigital_FibreSgmiiModeFibre (1<<0) + +#define SerdesDigital_Control1000X2 0x8301 +#define SerdesDigital_AutoNegoFastTimer (1<<6) +#define SerdesDigital_DisableRemoteFaultSending (1<<4) +#define SerdesDigital_FilterForceLink (1<<2) +#define SerdesDigital_DisableFalseLink (1<<1) +#define SerdesDigital_EnableParallelDetection (1<<0) + +#define SerdesDigital_Control1000X3 0x8302 + +#define SerdesDigital_Status1000X1 0x8304 +#define Status1000X1_Sgmii_Mode (1 << 0) +#define Status1000X1_link (1 << 1) +#define Status1000X1_FullDuplex (1 << 0) +#define Status1000X1_SpeedShift 3 +#define Status1000X1_SpeedMask (0x3 << 3) +#define Status1000X1_LinkChanged (1 << 7) + +#define SerdesDigital_Status1000X2 0x8305 +#define Status1000X2_sync_failed (1 << 11) +#define Status1000X2_sync_ok (1 << 10) + +#define SerdesDigital_rx66_Status 0x83c1 + +#define CL49_UserB0_Control 0x8368 + #define CL49_fast_lock_cya (1<<5) diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/unimac_regs.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/unimac_regs.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/unimac_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/unimac_regs.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,482 @@ +#ifndef UNIMAC_REGS_H_ +#define UNIMAC_REGS_H_ + +#define UNIMAC_CFG_OFFSET(mac) (0x0000 + (mac) * 0x1000) +#define UNIMAC_MIB_OFFSET(mac) (0x8000 + (mac) * 0x400) +#define UNIMAC_MISC_OFFSET(mac) (0xa000 + (mac) * 0x400) + +/* + * configuration registers + */ + +/* UniMAC Dummy Register */ +#define UNIMAC_CFG_UMAC_DUMMY_REG (0x0000) + +/* UniMAC Half Duplex Backpressure Control Register */ +#define UNIMAC_CFG_HD_BKP_CNTL_REG (0x0004) + +/* UniMAC Command Register */ +#define UNIMAC_CFG_CMD_REG (0x0008) + +/* + * 1: The MAC transmit function is enabled. 0: The MAC transmit + * function is disabled. The enable works on packet boundary meaning + * that only on the assertion of the bit during every SOP. Reset + * value is 0x0. + */ +#define UNIMAC_CFG_CMD_TX_EN_SHIFT 0 +#define UNIMAC_CFG_CMD_TX_EN_MASK (1 << UNIMAC_CFG_CMD_TX_EN_SHIFT) + +/* + * 1: The MAC receive function is enabled. 0: The MAC receive function + * is disabled. The enable works on packet boundary meaning that only + * on the assertion on the bit during every 0->1 transition of rx_dv. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RX_EN_SHIFT 1 +#define UNIMAC_CFG_CMD_RX_EN_MASK (1 << UNIMAC_CFG_CMD_RX_EN_SHIFT) + + +/* + * 00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: 2500Mbps + * Reset value is 0x2. + */ +#define UNIMAC_CFG_CMD_SPEED_SHIFT 2 +#define UNIMAC_CFG_CMD_SPEED_MASK (0x3 << UNIMAC_CFG_CMD_SPEED_SHIFT) +#define UNIMAC_CFG_CMD_SPEED_10 0 +#define UNIMAC_CFG_CMD_SPEED_100 1 +#define UNIMAC_CFG_CMD_SPEED_1000 2 +#define UNIMAC_CFG_CMD_SPEED_2500 3 + +/* + * 1: All frames are received without Unicast address filtering. + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_PROMISC_EN_SHIFT 4 +#define UNIMAC_CFG_CMD_PROMISC_EN_MASK (1 << UNIMAC_CFG_CMD_PROMISC_EN_SHIFT) + +/* + * 1: Padding is removed along with crc field before the frame is sent to + * the user application. + * + * 0: No padding is removed by the MAC. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_PAD_EN_SHIFT 5 +#define UNIMAC_CFG_CMD_PAD_EN_MASK (1 << UNIMAC_CFG_CMD_PAD_EN_SHIFT) + +/* + * 1: The CRC field of received frames is transmitted to the user application. + * 0: The CRC field is stripped from the frame. + * + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_CRC_FWD_SHIFT 6 +#define UNIMAC_CFG_CMD_CRC_FWD_MASK (1 << UNIMAC_CFG_CMD_CRC_FWD_SHIFT) + +/* + * 1: PAUSE frames are forwarded to the user application. + * 0: The PAUSE frames are terminated and discarded in the MAC. + * + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_PAUSE_FWD_SHIFT 7 +#define UNIMAC_CFG_CMD_PAUSE_FWD_MASK (1 << UNIMAC_CFG_CMD_PAUSE_FWD_SHIFT) + +/* + * 1: Receive PAUSE frames are ignored by the MAC. + * + * 0: The tramsmit process is stiooed for the amount of time specified + * in the pause quanta received within the PAUSE frame. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RX_PAUSE_IGN_SHIFT 8 +#define UNIMAC_CFG_CMD_RX_PAUSE_IGN_MASK (1 << UNIMAC_CFG_CMD_RX_PAUSE_IGN_SHIFT) + +/* + * 1: The MAC overwrites the source MAC address with a programmed MAC + * address in register MAC_0 and MAC_1. + * + * 0: Not modify the source address received from the transmit + * application client. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_TX_ADDR_INSERT_SHIFT 9 +#define UNIMAC_CFG_CMD_TX_ADDR_INSERT_MASK (1 << UNIMAC_CFG_CMD_TX_ADDR_INSERT_SHIFT) + +/* + * Ignored when RTH_SPEED[1]==1, gigabit mode. + * 1: half duplex + * 0: full duplex + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_HD_ENA_SHIFT 10 +#define UNIMAC_CFG_CMD_HD_ENA_MASK (1 << UNIMAC_CFG_CMD_HD_ENA) + +/* + * 1: RX and RX engines are put in reset. + * 0: come out of SW reset. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_SW_RESET_SHIFT 13 +#define UNIMAC_CFG_CMD_SW_RESET_MASK (1 << UNIMAC_CFG_CMD_SW_RESET_SHIFT) + +/* + * Enable GMII/MII loopback + * 1: Loopback enabled. + * 0: Normal operation. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_LCL_LOOP_EN_SHIFT 15 +#define UNIMAC_CFG_CMD_LCL_LOOP_EN_MASK (1 << UNIMAC_CFG_CMD_LCL_LOOP_EN_SHIFT) + +/* + * Enable/Disable auto-configuration. + * 1: Enable + * 0: Disable + * Reset value is 0x0 + */ +#define UNIMAC_CFG_CMD_ENA_EXT_EN_SHIFT 22 +#define UNIMAC_CFG_CMD_ENA_EXT_EN_MASK (1 << UNIMAC_CFG_CMD_ENA_EXT_EN_SHIFT) + +/* + * MAC control frame enable. + * + * 1: MAC control frames with opcode other than 0x0001 are accepted + * and forwarded to the client interface. + * + * 0: MAC control frames with opcode other than 0x0000 and 0x0001 are + * silently discarded. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_CTRL_FRM_EN_SHIFT 23 +#define UNIMAC_CFG_CMD_CTRL_FRM_EN_MASK (1 << UNIMAC_CFG_CMD_CTRL_FRM_EN_SHIFT) + +/* + * Payload length check. + * 0: Check payload length with Length/Type field. + * 1: Check disabled. + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_DIS_LEN_CHECK_SHIFT 26 +#define UNIMAC_CFG_CMD_DIS_LEN_CHECK_IGN_MASK (1 << UNIMAC_CFG_CMD_DIS_LEN_CHECK_SHIFT) + +/* + * Enable remote loopback at the fifo system side. + * 0: Normal operation + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RMT_LOOP_EN_SHIFT 25 +#define UNIMAC_CFG_CMD_RMT_LOOP_EN_MASK (1 << UNIMAC_CFG_CMD_RMT_LOOP_EN_SHIFT) + +/* + * Enable extract/insert of EFM headers. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_PRBL_EN_SHIFT 27 +#define UNIMAC_CFG_CMD_PRBL_EN_MASK (1 << UNIMAC_CFG_CMD_PRBL_EN_SHIFT) + +/* + * Ignore TX PAUSE frame transmit request. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_TX_PAUSE_IGN_SHIFT 28 +#define UNIMAC_CFG_CMD_TX_PAUSE_IGN_MASK (1 << UNIMAC_CFG_CMD_TX_PAUSE_IGN_SHIFT) + +/* + * This mode only works in auto-config mode: + * + * 0: After auto-config, TX_ENA and RX_ENA bits are set to 1. + * + * 1: After auto-config, TX_ENA and RX_ENA bits are set to 0, meaning + * SW will have to come in and enable TX and RX. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_TXRX_EN_SHIFT 29 +#define UNIMAC_CFG_CMD_TXRX_EN_MASK (1 << UNIMAC_CFG_CMD_TXRX_EN_SHIFT) + +/* + * 1: Disable RX side RUNT filtering. + * 0: Enable RUNT filtering. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RUNT_FILT_DIS_SHIFT 30 +#define UNIMAC_CFG_CMD_RUNT_FILT_DIS_MASK (1 << UNIMAC_CFG_CMD_RUNT_FILT_DIS_SHIFT) + + +/* UniMAC MAC address first 4 bytes */ +#define UNIMAC_CFG_MAC0_REG (0x000c) + +/* UniMAC MAC address 2 last bytes */ +#define UNIMAC_CFG_MAC1_REG (0x0010) + +/* UniMAC Frame Length */ +#define UNIMAC_CFG_FRM_LEN_REG (0x0014) + +/* UniMAC Pause Quanta */ +#define UNIMAC_CFG_PAUSE_QUNAT_REG (0x0018) + +/* UniMAC EFM Preamble Length */ +#define UNIMAC_CFG_SFD_OFFSET_REG (0x0040) + +/* UniMAC Mode */ +#define UNIMAC_CFG_MODE_REG (0x0044) + +/* UniMAC Preamble Outer TAG 0 */ +#define UNIMAC_CFG_FRM_TAG0_REG (0x0048) + +/* UniMAC Preamble Outer TAG 1 */ +#define UNIMAC_CFG_FRM_TAG1_REG (0x004c) + +/* UniMAC Inter Packet Gap */ +#define UNIMAC_CFG_TX_IPG_LEN_REG (0x005c) + +/* UniMAC Energy Efficient Ethernet Control */ +#define UNIMAC_CFG_EEE_CTRL_REG (0x0064) + +/* EEE LPI timer */ +#define UNIMAC_CFG_EEE_LPI_TIMER_REG (0x0068) + +/* EEE wakeup timer */ +#define UNIMAC_CFG_EEE_WAKE_TIMER_REG (0x006c) + +/* UniMAC Energy Efficient Ethernet Ref Clock Speed */ +#define UNIMAC_CFG_EEE_REF_COUNT_REG (0x0070) + +/* MII EEE LPI timer */ +#define UNIMAC_CFG_EEE_MII_LPI_TIMER_REG (0x0068) + +/* GMII EEE LPI timer */ +#define UNIMAC_CFG_EEE_GMII_LPI_TIMER_REG (0x006c) + +/* MII EEE wakeup timer */ +#define UNIMAC_CFG_EEE_MII_WAKE_TIMER_REG (0x0080) + +/* GMII EEE wakeup timer */ +#define UNIMAC_CFG_EEE_GMII_WAKE_TIMER_REG (0x0084) + +/* UniMAC Repetitive Pause Control in TX direction */ +#define UNIMAC_CFG_PAUSE_CNTRL_REG (0x0330) + +/* UniMAC RX MAX packet Size Register */ +#define UNIMAC_CFG_RX_MAX_PKT_SIZE_REG (0x0608) + + +/* + * MIB registers + */ + +/* Receive 64B Frame Counter */ +#define UNIMAC_MIB_GR64_REG (0x0000) + +/* Receive 65B to 127B Frame Counter */ +#define UNIMAC_MIB_GR127_REG (0x0004) + +/* Receive 128B to 255B Frame Counter */ +#define UNIMAC_MIB_GR255_REG (0x0008) + +/* Receive 256B to 511B Frame Counter */ +#define UNIMAC_MIB_GR511_REG (0x000c) + +/* Receive 512B to 1023B Frame Counter */ +#define UNIMAC_MIB_GR1023_REG (0x0010) + +/* Receive 1024B to 1518B Frame Counter */ +#define UNIMAC_MIB_GR1518_REG (0x0014) + +/* Receive 1519B to 1522B Good VLAN Frame Counter */ +#define UNIMAC_MIB_GRMGV_REG (0x0018) + +/* Receive 1519B to 2047B Frame Counter */ +#define UNIMAC_MIB_GR2047_REG (0x001c) + +/* Receive 2048B to 4095B Frame Counter */ +#define UNIMAC_MIB_GR4095_REG (0x0020) + +/* Receive 4096B to 9216B Frame Counter */ +#define UNIMAC_MIB_GR9216_REG (0x0024) + +/* Receive Packet Counter */ +#define UNIMAC_MIB_GRPKT_REG (0x0028) + +/* Receive Byte Counter */ +#define UNIMAC_MIB_GRBYT_REG (0x002c) + +/* Receive Multicast Frame Counter */ +#define UNIMAC_MIB_GRMCA_REG (0x0030) + +/* Receive Broadcast Frame Counter */ +#define UNIMAC_MIB_GRBCA_REG (0x0034) + +/* Receive FCS Error Counter */ +#define UNIMAC_MIB_GRFCS_REG (0x0038) + +/* Receive Control Frame Packet Counter */ +#define UNIMAC_MIB_GRXCF_REG (0x003c) + +/* Receive Pause Frame Packet Counter */ +#define UNIMAC_MIB_GRXPF_REG (0x0040) + +/* Receive Unknown OP Code Packet Counter */ +#define UNIMAC_MIB_GRXUO_REG (0x0044) + +/* Receive Alignmenet Error Counter */ +#define UNIMAC_MIB_GRALN_REG (0x0048) + +/* Receive Frame Length Out Of Range Counter */ +#define UNIMAC_MIB_GRFLR_REG (0x004c) + +/* Receive Code Error Packet Counter */ +#define UNIMAC_MIB_GRCDE_REG (0x0050) + +/* Receive Carrier Sense Error Packet Counter */ +#define UNIMAC_MIB_GRFCR_REG (0x0054) + +/* Receive Oversize Packet Counter */ +#define UNIMAC_MIB_GROVR_REG (0x0058) + +/* Receive Jabber Counter */ +#define UNIMAC_MIB_GRJBR_REG (0x005c) + +/* Receive MTU Error Packet Counter */ +#define UNIMAC_MIB_GRMTUE_REG (0x0060) + +/* Receive Good Packet Counter */ +#define UNIMAC_MIB_GRPOK_REG (0x0064) + +/* Receive Unicast Packet Counter */ +#define UNIMAC_MIB_GRUC_REG (0x0068) + +/* Receive PPP Packet Counter */ +#define UNIMAC_MIB_GRPPP_REG (0x006c) + +/* Receive CRC Match Packet Counter */ +#define UNIMAC_MIB_GRCRC_REG (0x0070) + +/* Transmit 64B Frame Counter */ +#define UNIMAC_MIB_TR64_REG (0x0080) + +/* Transmit 65B to 127B Frame Counter */ +#define UNIMAC_MIB_TR127_REG (0x0084) + +/* Transmit 128B to 255B Frame Counter */ +#define UNIMAC_MIB_TR255_REG (0x0088) + +/* Transmit 256B to 511B Frame Counter */ +#define UNIMAC_MIB_TR511_REG (0x008c) + +/* Transmit 512B to 1023B Frame Counter */ +#define UNIMAC_MIB_TR1023_REG (0x0090) + +/* Transmit 1024B to 1518B Frame Counter */ +#define UNIMAC_MIB_TR1518_REG (0x0094) + +/* Transmit 1519B to 1522B Good VLAN Frame Counter */ +#define UNIMAC_MIB_TRMGV_REG (0x0098) + +/* Transmit 1519B to 2047B Frame Counter */ +#define UNIMAC_MIB_TR2047_REG (0x009c) + +/* Transmit 2048B to 4095B Frame Counter */ +#define UNIMAC_MIB_TR4095_REG (0x00a0) + +/* Transmit 4096B to 9216B Frame Counter */ +#define UNIMAC_MIB_TR9216_REG (0x00a4) + +/* Transmit Packet Counter */ +#define UNIMAC_MIB_GTPKT_REG (0x00a8) + +/* Transmit Multicast Packet Counter */ +#define UNIMAC_MIB_GTMCA_REG (0x00ac) + +/* Transmit Broadcast Packet Counter */ +#define UNIMAC_MIB_GTBCA_REG (0x00b0) + +/* Transmit Pause Frame Packet Counter */ +#define UNIMAC_MIB_GTXPF_REG (0x00b4) + +/* Transmit Control Frame Packet Counter */ +#define UNIMAC_MIB_GTXCF_REG (0x00b8) + +/* Transmit FCS Error Counter */ +#define UNIMAC_MIB_GTFCS_REG (0x00bc) + +/* Transmit Oversize Packet Counter */ +#define UNIMAC_MIB_GTOVR_REG (0x00c0) + +/* Transmit Deferral Packet Counter */ +#define UNIMAC_MIB_GTDRF_REG (0x00c4) + +/* Transmit Excessive Deferral Packet Counter */ +#define UNIMAC_MIB_GTEDF_REG (0x00c8) + +/* Transmit Single Collision Packet Counter */ +#define UNIMAC_MIB_GTSCL_REG (0x00cc) + +/* Transmit Multiple Collision Packet Counter */ +#define UNIMAC_MIB_GTMCL_REG (0x00d0) + +/* Transmit Late Collision Packet Counter */ +#define UNIMAC_MIB_GTLCL_REG (0x00d4) + +/* Transmit Excessive Collision Packet Counter */ +#define UNIMAC_MIB_GTXCL_REG (0x00d8) + +/* Transmit Fragments Packet Counter */ +#define UNIMAC_MIB_GTFRG_REG (0x00dc) + +/* Transmit Total Collision Counter */ +#define UNIMAC_MIB_GTNCL_REG (0x00e0) + +/* Transmit Jabber Counter */ +#define UNIMAC_MIB_GTJBR_REG (0x00e4) + +/* Transmit Byte Counter */ +#define UNIMAC_MIB_GTBYT_REG (0x00e8) + +/* Transmit Good Packet Counter */ +#define UNIMAC_MIB_GTPOK_REG (0x00ec) + +/* Transmit Unicast Packet Counter */ +#define UNIMAC_MIB_GTUC_REG (0x00f0) + +/* Receive RUNT Packet Counter */ +#define UNIMAC_MIB_RRPKT_REG (0x0100) + +/* Receive RUNT Packet And Contain A Valid FCS */ +#define UNIMAC_MIB_RRUND_REG (0x0104) + +/* Receive RUNT Packet And Contain Invalid FCS or Alignment Error */ +#define UNIMAC_MIB_RRFRG_REG (0x0108) + +/* Receive RUNT Packet Byte Counter */ +#define UNIMAC_MIB_RRBYT_REG (0x010c) + +/* MIB Control Register */ +#define UNIMAC_MIB_MIB_CNTRL_REG (0x0180) + + +/* + * MISC registers + */ + +/* UNIMAC_CFG Register */ +#define UNIMAC_MISC_CFG_REG (0x0000) +#define UNIMAC_MISC_CFG_GMII_DIRECT_SHIFT 0 +#define UNIMAC_MISC_CFG_GMII_DIRECT_MASk (1 << UNIMAC_MISC_CFG_GMII_DIRECT_SHIFT) + +/* UNIMAC_EXT_CFG1 Register */ +#define UNIMAC_MISC_EXT_CFG1_REG (0x0004) +#define UNIMAC_MISC_EXT_CFG1_MAX_PKT_SIZE_SHIFT 0 +#define UNIMAC_MISC_EXT_CFG1_MAX_PKT_SIZE_MASK (0x3fff << UNIMAC_MISC_EXT_CFG1_MAX_PKT_SIZE_SHIFT) + +/* UNIMAC_EXT_CFG2 Register */ +#define UNIMAC_MISC_EXT_CFG2_REG (0x0008) + +#endif /* !UNIMAC_REGS_H */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/wan_top.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/wan_top.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/wan_top.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/wan_top.h 2023-05-31 17:11:03.413680496 +0200 @@ -0,0 +1,1923 @@ +#ifndef WAN_TOP_H_ +#define WAN_TOP_H_ + +/* relative to core */ +#define SCRATCH_OFFSET_0 0x0 + +/* + * Register + * + * Register used for testing read and write access into wan_top block. + */ +#define WAN_TOP_SCRATCH_REG 0x0 + +/* Scratch pad. */ +#define WAN_TOP_SCRATCH_SCRATCH_SHIFT 0 +#define WAN_TOP_SCRATCH_SCRATCH_MASK 0xffffffff + + +/* + * Register + * + * Various resets to be applied within wan_top. + */ +#define WAN_TOP_RESET_REG 0x4 + +/* + * Active low PCS reset. + * Set to 1 for normal operation +*/ +#define WAN_TOP_RESET_CFG_PCS_RESET_N_MASK 0x1 + + +/* + * Register + * + * Configuration for the GPON gearbox. + */ +#define WAN_TOP_GPON_GEARBOX_0_REG 0x8 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_PTG_STATUS2_SEL_MASK 0x40000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_PTG_STATUS1_SEL_MASK 0x20000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_STATUS_SEL_MASK 0x10000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TXLBE_BIT_ORDER_MASK 0x8000000 + +/* + * This field changes the bit order of the 16-bit Rx data exiting theRx + * FIFO to GPON MAC. + * 0: + * No changes1: + * Rx data is reversed from [15: + * 0] to [0: + * 15] +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_RX_16BIT_ORDER_MASK 0x4000000 + +/* + * This field changes the bit order of the 8-bit Tx data enteringthe Tx + * FIFO. + * 0: + * No changes1: + * Tx data is reversed from [7: + * 0] to [0: + * 7] +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_8BIT_ORDER_MASK 0x2000000 + +/* + * This field changes the bit order of the 16-bit Tx data exitingthe Tx + * FIFO to ONU2G PMD. + * 0: + * Bit 0 is transmitted first1: + * Bit 19 is transmitted first +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_16BIT_ORDER_MASK 0x1000000 + +/* + * Minimum distance allowed between the Tx FIFO write and readpointers. + * The TXFIFO_DRIFTED status bit is asserted ifTX_POINTER_DISTANCE goes + * below this minimum value. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MIN_SHIFT 16 +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MIN_MASK 0x1f0000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_0_FIFO_CFG_0_ASYM_LOOPBACK_MASK 0x2000 + +/* + * Maximum distance allowed between the Tx FIFO write and readpointers. + * The TXFIFO_DRIFTED status bit is asserted ifTX_POINTER_DISTANCE goes + * above this maximum value. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MAX_SHIFT 8 +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MAX_MASK 0x1f00 + +/* This bit enables logically inversion of every Tx bit. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_BIT_INV_MASK 0x80 + +/* + * Delay Tx FIFO write pointer by 1 location (8 Tx bits). + * The pointeris adjusted on every 0 to 1 transition in this register + * field. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_WR_PTR_DLY_MASK 0x40 + +/* + * Advance Tx FIFO write pointer by 1 location (8 Tx bits). + * Thepointer is adjusted on every 0 to 1 transition in this registerfield. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_WR_PTR_ADV_MASK 0x20 + +/* if 1, the TXFIFO_COLLISION status bit resets to 0. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_CLEAR_TXFIFO_COLLISION_MASK 0x10 + +/* + * If 1, the output of Rx FIFO is looped back to the input of Tx FIFO. + * In this case, the SATA PHY Tx data rate is the same as the Rx datarate + * regardless of whether Gen2 or Gen3 is selected. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_LOOPBACK_RX_MASK 0x8 + +/* If 1, the TXFIFO_DRIFTED statsu bit resets to 0. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_CLEAR_TXFIFO_DRIFTED_MASK 0x4 + +/* If 1, the Tx FIFO goes into reset. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_SW_RESET_TXFIFO_RESET_MASK 0x2 + +/* If 1, The Tx Pattern Generator goes into reset. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_SW_RESET_TXPG_RESET_MASK 0x1 + + +/* + * Register + * + * The GPON Gearbox has a pattern generator to be used for laser + * burstenable calibration and during SATA PHY characterization/testing. + */ +#define WAN_TOP_GPON_PATTERN_CFG1_REG 0xc + +/* 8-bit pattern to placed between Tx bursts when PG_MODE is 1. */ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_FILLER_SHIFT 24 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_FILLER_MASK 0xff000000 + +/* + * 8-bit pattern to placed after the HEADER byte in every Tx burst + * whenPG_MODE is 1. +*/ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PAYLOAD_SHIFT 16 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PAYLOAD_MASK 0xff0000 + +/* 8-bit pattern to placed at the start of every Tx burst when PG_MODEis 1. */ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_HEADER_SHIFT 8 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_HEADER_MASK 0xff00 + +/* + * Pattern generator modes: + * 0: + * Pattern generator disabled. + * GPON MAC has control of Tx outputand burst enable. + * 1: + * Generate repetitive Tx bursts. + * Each burst consists of 1 headerbyte and1 or more payload bytes. + * Filler bytes are placed between Txbursts. + * 2: + * Reserved3: + * Reserved4: + * Generate PRBS7 pattern5: + * Generate PRBS15 pattern6: + * Generate PRBS23 pattern7: + * Generate PRBS31 patternMode 0 is for GPON normal operation. + * Mode 1 is for laser burstenable calibration. +*/ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PG_MODE_SHIFT 0 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PG_MODE_MASK 0x7 + + +/* + * Register + * + * The GPON Gearbox has a pattern generator to be used for laser + * burstenable calibration and during SATA PHY characterization/testing. + */ +#define WAN_TOP_GPON_PATTERN_CFG2_REG 0x10 + +/* Number of filler bytes to be placed between Tx bursts when PG_MODEis 1. */ +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_GAP_SIZE_SHIFT 8 +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_GAP_SIZE_MASK 0xff00 + +/* Total length of Tx burst in bytes when PG_MODE is 1. */ +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_BURST_SIZE_SHIFT 0 +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_BURST_SIZE_MASK 0xff + + +/* + * Register + * + * Configuration for the GPON gearbox. + */ +#define WAN_TOP_GPON_GEARBOX_2_REG 0x14 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_CONFIG_BURST_DELAY_CYC_SHIFT 24 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_CONFIG_BURST_DELAY_CYC_MASK 0xf000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_TX_VLD_DELAY_CYC_SHIFT 21 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_TX_VLD_DELAY_CYC_MASK 0xe00000 + +/* + * Initial value to be loaded into Tx FIFO write pointer whenTXFIFO_RESET + * is asserted. + * Legal values are 0 to 19. +*/ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_WR_POINTER_SHIFT 16 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_WR_POINTER_MASK 0x1f0000 + +/* + * Initial value to be loaded into Tx FIFO read pointer whenTXFIFO_REET is + * asserted. + * Legal values are 0 to 31. +*/ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_RD_POINTER_SHIFT 8 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_RD_POINTER_MASK 0x1f00 + + +/* + * Register + * + * EARLY_TXEN_CFG Register valid for (EPON & GPON mode). + */ +#define WAN_TOP_EARLY_TXEN_TXEN_REG 0x18 + +/* + * Early TXEN Enable Logic Bypass. + * 0 = NO_BYPASS +*/ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_EARLY_TXEN_BYPASS_MASK 0x4000000 + +/* + * Mac TXEN input polarity. + * 0 = ACTIVE_LOW +*/ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_INPUT_TXEN_POLARITY_MASK 0x2000000 + +/* + * Mac TXEN output polarity. + * 0 = ACTIVE_LOW +*/ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_OUTPUT_TXEN_POLARITY_MASK 0x1000000 + +/* Early TXEN Toff Time */ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_TOFF_TIME_SHIFT 16 +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_TOFF_TIME_MASK 0xff0000 + +/* Early TXEN Setup Time */ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_SETUP_TIME_SHIFT 8 +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_SETUP_TIME_MASK 0xff00 + +/* Early TXEN Hold Time */ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_HOLD_TIME_SHIFT 0 +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_HOLD_TIME_MASK 0xff + + +/* + * Register + * + * Register used for configuring the RESCAL. + */ +#define WAN_TOP_RESCAL_AL_CFG_REG 0x1c + +/* Connects to i_rstb. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_RSTB_MASK 0x8000 + +/* Connects to i_diag_on. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_DIAG_ON_MASK 0x4000 + +/* Connects to i_pwrdn. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_PWRDN_MASK 0x2000 + +/* Connects to i_rescal_ctrl. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_CTRL_SHIFT 0 +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_CTRL_MASK 0x1fff + + +/* + * Register - read-only + * + * Register used for reading RESCAL status. + */ +#define WAN_TOP_RESCAL_STATUS_0_REG 0x20 + +/* Connects to o_done. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_DONE_MASK 0x4000000 + +/* Connects to o_pon. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PON_SHIFT 22 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PON_MASK 0x3c00000 + +/* Connects to o_prev_comp_cnt. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PREV_COMP_CNT_SHIFT 18 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PREV_COMP_CNT_MASK 0x3c0000 + +/* Connects to o_rescal_ctrl_dfs. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_CTRL_DFS_SHIFT 5 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_CTRL_DFS_MASK 0x3ffe0 + +/* Connects to o_rescal_state. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_STATE_SHIFT 2 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_STATE_MASK 0x1c + +/* Connects to o_rescalcomp. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_COMP_MASK 0x2 + +/* Connects to o_valid. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_VALID_MASK 0x1 + + +/* + * Register - read-only + * + * Register used for reading RESCAL status. + */ +#define WAN_TOP_RESCAL_STATUS_1_REG 0x24 + +/* Connects to o_curr_comp_cnt. */ +#define WAN_TOP_RESCAL_STATUS_1_WAN_RESCAL_CURR_COMP_CNT_SHIFT 0 +#define WAN_TOP_RESCAL_STATUS_1_WAN_RESCAL_CURR_COMP_CNT_MASK 0x3f + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_0_REG 0x28 + +/* + * Reserved mode bus for lane. + * Mode bus for lane used by the PCS tocommunicate lane info to PMD. + * This bus should only be written towhen the lane is in reset since the + * firmware will only read thisafter coming out of reset. + * This signal will be latched to a lanebased register during core_dp_rstb. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_0_PMD_LANE_MODE_SHIFT 16 +#define WAN_TOP_MISC_0_PMD_LANE_MODE_MASK 0xffff0000 + +/* + * 0: + * All other modes 1: + * Explicit 2. + * 5G Full Rate Serdes Mode +*/ +#define WAN_TOP_MISC_0_EPON_GBOX_AE_2P5_FULL_RATE_MODE_MASK 0x1000 + +/* + * 0: + * 10b mode, 1G Operation 1: + * 20b mode, 2G Operation +*/ +#define WAN_TOP_MISC_0_EPON_GBOX_PON_RX_WIDTH_MODE_MASK 0x800 + +/* + * Strap input for selecting the port address to decode on the + * mdiotransaction. +*/ +#define WAN_TOP_MISC_0_ONU2G_PHYA_SHIFT 6 +#define WAN_TOP_MISC_0_ONU2G_PHYA_MASK 0x7c0 + +/* Load vlue in cr_xgwan_top_wan_misc_epon_tx_fifo_off. */ +#define WAN_TOP_MISC_0_EPON_TX_FIFO_OFF_LD_MASK 0x20 + +/* + * Debug bit that disables the 32-bit preamble to allow mdio frames torun + * at 2x speed. +*/ +#define WAN_TOP_MISC_0_MDIO_FAST_MODE_MASK 0x10 + +/* + * MDIO transaction indicator needs to be asserted in a configurationwhere + * an external mdio controller is trying to access the internalPMD + * registers directly. +*/ +#define WAN_TOP_MISC_0_MDIO_MODE_MASK 0x8 + +/* Not used in this chip. */ +#define WAN_TOP_MISC_0_REFOUT_EN_MASK 0x4 + +/* Not used in this chip. */ +#define WAN_TOP_MISC_0_REFIN_EN_MASK 0x2 + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_1_REG 0x2c + +/* + * Reserved mode bus for the entire core. + * Mode bus for core used bythe PCS to communicate core info to PMD . + * This bus should only bewritten to when the core is in reset since the + * firmware will onlyread this after coming out of reset. + * This signal will be latched toa core register during core_dp_rstb. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_1_PMD_CORE_1_MODE_SHIFT 16 +#define WAN_TOP_MISC_1_PMD_CORE_1_MODE_MASK 0xffff0000 + +/* + * Reserved mode bus for the entire core. + * Mode bus for core used bythe PCS to communicate core info to PMD . + * This bus should only bewritten to when the core is in reset since the + * firmware will onlyread this after coming out of reset. + * This signal will be latched toa core register during core_dp_rstb. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_1_PMD_CORE_0_MODE_SHIFT 0 +#define WAN_TOP_MISC_1_PMD_CORE_0_MODE_MASK 0xffff + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_2_REG 0x30 + +/* + * Oversample mode for rx lane. + * Asynchronous signal to the PMD. + * 0 -OSR1. + * 1 - OSR2. +*/ +#define WAN_TOP_MISC_2_PMD_RX_OSR_MODE_SHIFT 20 +#define WAN_TOP_MISC_2_PMD_RX_OSR_MODE_MASK 0xf00000 + +/* + * EEE tx mode function for lane. + * Asynchronous signal to the PMD. +*/ +#define WAN_TOP_MISC_2_PMD_TX_MODE_SHIFT 16 +#define WAN_TOP_MISC_2_PMD_TX_MODE_MASK 0x30000 + +/* + * Oversample mode for tx lane. + * Asynchronous signal to the PMD. + * 0 -OSR1. + * 1 - OSR2. +*/ +#define WAN_TOP_MISC_2_PMD_TX_OSR_MODE_SHIFT 12 +#define WAN_TOP_MISC_2_PMD_TX_OSR_MODE_MASK 0xf000 + +/* Pmd_tx_disable is asserted to squelch the transmit signal for lane. */ +#define WAN_TOP_MISC_2_PMD_TX_DISABLE_MASK 0x200 + +/* + * Lane RX power down. + * Minimum assertion time: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_RX_H_PWRDN_MASK 0x100 + +/* + * Lane TX power down. + * Minimum assertion time: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_TX_H_PWRDN_MASK 0x80 + +/* + * External Loss of signal. + * LOS = 1. + * Signal presence = 0. +*/ +#define WAN_TOP_MISC_2_PMD_EXT_LOS_MASK 0x40 + +/* + * PMD main reset, resets registers, data path for entire coreincluding all + * lanes. + * Active Low. + * Minimum assertion time: + * 25 comclkperiod. +*/ +#define WAN_TOP_MISC_2_PMD_POR_H_RSTB_MASK 0x20 + +/* + * Core reset for datapath for all lanes and corresponding PLL. + * Doesnot reset registers. + * Active Low. + * Minimum assertion time: + * 25 comclkperiod. +*/ +#define WAN_TOP_MISC_2_PMD_CORE_1_DP_H_RSTB_MASK 0x10 + +/* + * Core reset for datapath for all lanes and corresponding PLL. + * Doesnot reset registers. + * Active Low. + * Minimum assertion time: + * 25 comclkperiod. +*/ +#define WAN_TOP_MISC_2_PMD_CORE_0_DP_H_RSTB_MASK 0x8 + +/* + * Lane reset registers and data path. + * Active Low. + * Minimum assertiontime: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_H_RSTB_MASK 0x4 + +/* + * Lane datapath reset, does not reset registers. + * Active Low. + * Minimumassertion time: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_DP_H_RSTB_MASK 0x2 + +/* + * EEE rx mode function for lane. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_2_PMD_RX_MODE_MASK 0x1 + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_3_REG 0x34 + +/* TXFIFO OFF LOAD signal for EPON's gearbox. */ +#define WAN_TOP_MISC_3_EPON_TX_FIFO_OFF_SHIFT 24 +#define WAN_TOP_MISC_3_EPON_TX_FIFO_OFF_MASK 0x3f000000 + +/* + * This field selects the block that the 40-bit debug bus comesfrom. + * 0: + * GPON1: + * XPORT_0 BBH RX2: + * XPORT_0 BBH TX3: + * XPORT_1 BBH RX4: + * XPORT_1 BBH TX5: + * SERDES6: + * XLIF7: + * GPON BBH RX8: + * GPON BBH TX9: + * SAR BBH RX10: + * SAR BBH TX11: + * XPORT12: + * SAR +*/ +#define WAN_TOP_MISC_3_WAN_DEBUG_SEL_SHIFT 12 +#define WAN_TOP_MISC_3_WAN_DEBUG_SEL_MASK 0x1f000 + +/* Allows the bypassing of the NTR double sync and pulse generator. */ +#define WAN_TOP_MISC_3_CFG_NTR_PERIPH_PULSE_BYPASS_MASK 0x800 + +/* Allows the bypassing of the NTR double sync and pulse generator. */ +#define WAN_TOP_MISC_3_CFG_NTR_GPIO_PULSE_BYPASS_MASK 0x400 + +/* + * Selects the source of NTR pulse : + * 0 - programmable clock; 1 - GPON;2 - GPIO, 3 - NCO. +*/ +#define WAN_TOP_MISC_3_CFG_NTR_SRC_SHIFT 8 +#define WAN_TOP_MISC_3_CFG_NTR_SRC_MASK 0x300 + +/* + * 0: + * Output enable for laser is disabled. + * 1: + * Output enable for laseris enabled. +*/ +#define WAN_TOP_MISC_3_LASER_OE_MASK 0x80 + +/* + * Selects between various speed AE modes and GPON mode 0: + * 0: 100M AE + * 1: 1G AE + * 2: 5G AE + * 3: 10G AE + * 4: GPON + * 5-7: Reserved +*/ +#define WAN_TOP_MISC_3_WAN_IFSELECT_SHIFT 4 +#define WAN_TOP_MISC_3_WAN_IFSELECT_MASK 0x70 + +/* + * Bit 0 selects the speed, and bit 1 selects the technology. + * 2: + * GPON;0,1,3 : + * Disable laser. +*/ +#define WAN_TOP_MISC_3_LASER_MODE_SHIFT 1 +#define WAN_TOP_MISC_3_LASER_MODE_MASK 0xe + +/* + * enable SGMII mode + */ +#define WAN_TOP_MISC_3_SGMII_MODE_MASK (1 << 17) + +/* + * 0: + * Normal operation. + * 1: + * Invert laser enable. +*/ +#define WAN_TOP_MISC_3_LASER_INVERT_MASK 0x80000000 + +/* REB going to WAN memories. */ +#define WAN_TOP_MISC_3_MEM_REB_MASK 0x1 + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_4_REG 0xf4 + +/* Specifies the width of NTR pulse, in unit of 4 ns. */ +#define WAN_TOP_MISC_4_CFG_NTR_PULSE_WIDTH_SHIFT 16 +#define WAN_TOP_MISC_4_CFG_NTR_PULSE_WIDTH_MASK 0xffff0000 + + +/* + * Register + * + * Register used for low configuration of PLL clocks. + */ +#define WAN_TOP_SERDES_PLL_CTL_REG 0x38 + +/* + * 0 - select pll1_lcref. + * 1 - select pll0_lcref. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_LCREF_SEL_MASK 0x400 + +/* + * Enables SERDES to drive the pll1_refout pin. + * 0 - output is hiZ. + * 1- output is pad_pll1_refclk. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_REFOUT_EN_MASK 0x200 + +/* + * Reference select. + * 0 - select pad_pll1_refclkp/n. + * 1 - selectpll1_lcrefp/n. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_REFIN_EN_MASK 0x100 + +/* + * 0 - select pll0_lcref. + * 1 - select pll1_lcref. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_LCREF_SEL_MASK 0x4 + +/* + * Enables SERDES to drive the pll0_refout pin. + * 0 - output is hiZ. + * 1- output is pad_pll0_refclk. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_REFOUT_EN_MASK 0x2 + +/* + * Reference select. + * 0 - select pad_pll0_refclkp/n. + * 1 - selectpll0_lcrefp/n. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_REFIN_EN_MASK 0x1 + + +/* + * Register - read-only + * + * Register used for temperature read. + */ +#define WAN_TOP_SERDES_TEMP_CTL_REG 0x3c + +/* + * 10-bit temperature data. + * Please refer to TMON documentation for howto convert this value to a + * useful number. +*/ +#define WAN_TOP_SERDES_TEMP_CTL_WAN_TEMPERATURE_DATA_SHIFT 0 +#define WAN_TOP_SERDES_TEMP_CTL_WAN_TEMPERATURE_DATA_MASK 0x3ff + + +/* + * Register + * + * Register used for PRAM control. + */ +#define WAN_TOP_SERDES_PRAM_CTL_REG 0x40 + +/* + * Perform pRAM operation. + * This field is only valid for the B0 orbeyond. + * Software sets and hardware clears this bit. + * Do not writeto this register if this bit is set. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_GO_MASK 0x80000000 + +/* Program RAM write strobe. */ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_WE_MASK 0x4000000 + +/* + * Program RAM chip select. + * This field is only valid for the A0 versionof the chip. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_CS_MASK 0x2000000 + +/* + * Ability to support parallel bus interface to access program RAM. + * 0- not supported. + * 1 - supported. + * This field is only valid for the A0version of the chip. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_ABILITY_MASK 0x1000000 + +/* + * Deprecated. + * Use the data field in SERDES_PRAM_CTL_2/3. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_DATAIN_SHIFT 16 +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_DATAIN_MASK 0xff0000 + +/* Program RAM address. */ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_ADDR_SHIFT 0 +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_ADDR_MASK 0xffff + + +/* + * Register + * + * Register used for PRAM control. + */ +#define WAN_TOP_SERDES_PRAM_CTL_2_REG 0x44 + +/* + * Bits [31: + * 0] of the 64-bit pRAM write data interface. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_2_CFG_PRAM_DATAIN_0_SHIFT 0 +#define WAN_TOP_SERDES_PRAM_CTL_2_CFG_PRAM_DATAIN_0_MASK 0xffffffff + + +/* + * Register + * + * Register used for PRAM control. + */ +#define WAN_TOP_SERDES_PRAM_CTL_3_REG 0x48 + +/* + * Bits [63: + * 32] of the 64-bit pRAM write data interface. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_3_CFG_PRAM_DATAIN_1_SHIFT 0 +#define WAN_TOP_SERDES_PRAM_CTL_3_CFG_PRAM_DATAIN_1_MASK 0xffffffff + + +/* + * Register + * + * Register used for low priority configuration. + */ +#define WAN_TOP_PMI_LP_0_REG 0x4c + +/* + * Transaction enable control from master. + * This is treated asasynchronous to the PCS. + * The bus master should wait forpcs_pmi_lp_ack to be deasserted before + * pcs_pmi_lp_en is asserted. + * The bus master should then wait for pcs_pmi_lp_ack to be + * assertedindicating that the transaction is complete before it + * deassertspcs_pmi_lp_en. +*/ +#define WAN_TOP_PMI_LP_0_PCS_EN_MASK 0x4 + +/* + * Transaction enable control from master. + * This is treated asasynchronous to the rmic. + * The bus master should wait for pmi_lp_ackto be deasserted before + * pmi_lp_en is asserted. + * The bus master shouldthen wait for pmi_lp_ack to be asserted indicating + * that thetransaction is complete before it deasserts pmi_lp_en. +*/ +#define WAN_TOP_PMI_LP_0_MISC_EN_MASK 0x2 + +/* + * Read/Write control from master. + * 1-write, 0-read. + * This should beasserted before or with the pmi_lp_en and should be driven + * until thenext transaction. +*/ +#define WAN_TOP_PMI_LP_0_WRITE_MASK 0x1 + + +/* + * Register + * + * Register used for low priority configuration. + */ +#define WAN_TOP_PMI_LP_1_REG 0x50 + +/* + * 32-bit address driven by master for read or write transaction. + * Thisshould be asserted before or with the pmi_lp_en and should be + * drivenuntil the next transaction +*/ +#define WAN_TOP_PMI_LP_1_PMI_LP_ADDR_SHIFT 0 +#define WAN_TOP_PMI_LP_1_PMI_LP_ADDR_MASK 0xffffffff + + +/* + * Register + * + * Register used for low priority configuration. + */ +#define WAN_TOP_PMI_LP_2_REG 0x54 + +/* + * 16-bit data bus driven by master for write transaction. + * This shouldbe driven before or with the pmi_lp_en and should be driven + * untilthe next transaction. +*/ +#define WAN_TOP_PMI_LP_2_PMI_LP_WRDATA_SHIFT 16 +#define WAN_TOP_PMI_LP_2_PMI_LP_WRDATA_MASK 0xffff0000 + +/* + * 16-bit mask bus driven by master for write transaction. + * 0 means nomask (wrdata bit is written to register), 1 means mask (wrdata + * bitis ignored). + * This bus has no affect during a read operation. + * Thisshould be asserted before or with the pmi_lp_en and should be + * drivenuntil the next transaction. +*/ +#define WAN_TOP_PMI_LP_2_PMI_LP_MASKDATA_SHIFT 0 +#define WAN_TOP_PMI_LP_2_PMI_LP_MASKDATA_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for low priority read back. + */ +#define WAN_TOP_PMI_LP_3_REG 0x58 + +/* + * Error response from RMIC slave indicating an address error whichmeans + * that either the block address does not exist or that the deviddid not + * match the strap value. + * The ack signal indicates that thetransaction is complete and the error + * signal indicates that therewas an address error with this transaction. + * This signal is assertedalong with the ack signal and should be treated + * an asynchronoussignal the same way as the ack signal. +*/ +#define WAN_TOP_PMI_LP_3_PMI_LP_ERR_MASK 0x20000 + +/* + * Ack response back from the RMIC slave indicating that the write orread + * transaction is complete. + * This signal is driven in the registersblocks clock domain and should be + * treated as an asynchronous inputby the master. +*/ +#define WAN_TOP_PMI_LP_3_PMI_LP_ACK_MASK 0x10000 + +/* + * 16-bit data bus driven RMIC slave during a read transaction. + * Thisdata is latched in the register clock domain but this data + * isguaranteed to be stable by the end of the read transaction so thisdoes + * not have to metastabilized. +*/ +#define WAN_TOP_PMI_LP_3_PMI_LP_RDDATA_SHIFT 0 +#define WAN_TOP_PMI_LP_3_PMI_LP_RDDATA_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for PCS low priority read back. + */ +#define WAN_TOP_PMI_LP_4_REG 0x5c + +/* + * Error response from PCS slave indicating an address error whichmeans + * that either the block address does not exist or that the deviddid not + * match the strap value. + * The ack signal indicates that thetransaction is complete and the error + * signal indicates that therewas an address error with this transaction. + * This signal is assertedalong with the ack signal and should be treated + * an asynchronoussignal the same way as the ack signal. +*/ +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_ERR_MASK 0x20000 + +/* + * Ack response back from the PCS slave indicating that the write orread + * transaction is complete. + * This signal is driven in the registersblocks clock domain and should be + * treated as an asynchronous inputby the master. +*/ +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_ACK_MASK 0x10000 + +/* + * 16-bit data bus driven PCS slave during a read transaction. + * Thisdata is latched in the register clock domain but this data + * isguaranteed to be stable by the end of the read transaction so thisdoes + * not have to metastabilized. +*/ +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_RDDATA_SHIFT 0 +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_RDDATA_MASK 0xffff + + +/* + * Register + * + * Register used for 48-bit timestamp Time Of Day (TOD) configuration. + */ +#define WAN_TOP_TOD_CONFIG_0_REG 0x60 + +/* + * Indicates TOD read is in progress. + * Deassertive value indicatesvalid values at WAN_TOD_TS48/WAN_TOD_TS64 + * registers. +*/ +#define WAN_TOP_TOD_CONFIG_0_TOD_READ_BUSY_MASK 0x400000 + +/* + * 0: + * New mode. + * Transfer TS48 using FIFO. + * 1: + * Legacy mode. + * Transferupper TS48 bits between clock domains. +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_PRE_SYNC_FIFO_DISABLE_MASK 0x200000 + +/* Number of clock ticks between consecutive writes to the TS48 FIFO. */ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_PRE_SYNC_FIFO_LOAD_RATE_SHIFT 16 +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_PRE_SYNC_FIFO_LOAD_RATE_MASK 0x1f0000 + +/* + * Allows 1PPS pulse to load cfg_tod_1pps_ns_offset into nanosecondcounter. + * If not set, the 1PPS pulse will have no effect on theTS48. +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TOD_PPS_CLEAR_MASK 0x8000 + +/* + * Arm the reading of the TS48/TS64 timestamps. + * Values are valid atthe deassertion of tod_read_busy +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TOD_READ_MASK 0x4000 + +/* + * The TS48 offset value. + * In legacy, GPON mode (cfg_ts48_pre_sync_fifo_disable = 1), therising + * edge ofTS48/TS64's bit[9] loads cfg_ts48_offset[8: + * 0] into the lower 9 bitsof the synchronized TS48/TS64. + * In the new mode, the timestamp is transfer to the 250 MHz clockdomain + * via an asynchronousFIFO. + * The offset is added to the output of the FIFO. + * Thecfg_ts48_offset[8] is the signbit, allowing +/- adjustment to the + * timestamp value. + * It is signextended to make theoffset 48-bits. + * In AE mode, the offset is added to the current TS48 value andloading it + * back into AE TS48. + * Loading is accomplished by setting the cfg_tod_load_ts48_offset bit. + * The sign extension ofcfg_ts48_offset[8] also applies. +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_OFFSET_SHIFT 4 +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_OFFSET_MASK 0x3ff0 + +/* + * This field selects the MAC that the timestamp comes from. + * 2: + * GPON4: + * Active Ethernet0,1,3,5,6,7: + * Reserved +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_MAC_SELECT_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_MAC_SELECT_MASK 0x7 + + +/* + * Register + * + * Register used for 48-bit timestamp Time Of Day (TOD) configuration. + */ +#define WAN_TOP_TOD_CONFIG_1_REG 0x64 + +/* + * The rising edge will load the cfg_ts48_offset into AE TS48, subjectto a + * lockout window of 1us before and after rollover. +*/ +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_LOAD_TS48_OFFSET_MASK 0x100000 + +/* + * The rising edge will be latched, and cfg_tod_seconds will be loadedinto + * AE TS48 on the next 1PPS pulse or when the next second rollsover. +*/ +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_LOAD_MASK 0x80000 + +/* Number of seconds to be loaded into AE TS48. */ +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_SECONDS_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_SECONDS_MASK 0x7ffff + + +/* + * Register + * + * Register used for 16-bit timestamp configuration. + */ +#define WAN_TOP_TOD_CONFIG_2_REG 0x68 + +/* + * The TS48 offset value for TX clock timestamp. + * In legacy mode (cfg_ts48_pre_sync_fifo_disable = 1), the rising edgeof + * cfg_ts48_offset[9]loads the lower 9 bits into the 16-bits timestamp. + * In the new mode,the timestamp istransfer to the 250 MHz clock domain via + * an asynchronous FIFO. + * Theoffset is added to theoutput of the FIFO. + * The cfg_ts48_offset[8] is the sign bit,allowing +/- adjustment tothe + * timestamp value. + * It is sign extended to make the offset 48-bits. +*/ +#define WAN_TOP_TOD_CONFIG_2_CFG_TX_OFFSET_SHIFT 16 +#define WAN_TOP_TOD_CONFIG_2_CFG_TX_OFFSET_MASK 0x3ff0000 + +/* + * The TS48 offset value for RX clock timestamp. + * In legacy mode (cfg_ts48_pre_sync_fifo_disable = 1), the rising edgeof + * cfg_ts48_offset[9]loads the lower 9 bits into the 16-bits timestamp. + * In the new mode,the timestamp istransfer to the 250 MHz clock domain via + * an asynchronous FIFO. + * Theoffset is added to theoutput of the FIFO. + * The cfg_ts48_offset[8] is the sign bit,allowing +/- adjustment tothe + * timestamp value. + * It is sign extended to make the offset 48-bits. +*/ +#define WAN_TOP_TOD_CONFIG_2_CFG_RX_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_2_CFG_RX_OFFSET_MASK 0x3ff + + +/* + * Register + * + * Register used for 16-bit timestamp configuration. + */ +#define WAN_TOP_TOD_CONFIG_3_REG 0x6c + +/* + * The TS48 offset value for RX clock timestamp. + * In legacy mode (cfg_ts48_pre_sync_fifo_disable = 1), the rising edgeof + * cfg_ts48_offset[9]loads the lower 9 bits into the 16-bits timestamp. + * In the new mode,the timestamp istransfer to the 250 MHz clock domain via + * an asynchronous FIFO. + * Theoffset is added to theoutput of the FIFO. + * The cfg_ts48_offset[8] is the sign bit,allowing +/- adjustment tothe + * timestamp value. + * It is sign extended to make the offset 48-bits. +*/ +#define WAN_TOP_TOD_CONFIG_3_CFG_REF_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_3_CFG_REF_OFFSET_MASK 0x3ff + + +/* + * Register + * + * Offset for 1pps loading. + */ +#define WAN_TOP_TOD_CONFIG_4_REG 0x70 + +/* + * Value to be loaded into nanosecond counter by 1PPS pulse, + * providedcfg_tod_pps_clear is set. +*/ +#define WAN_TOP_TOD_CONFIG_4_CFG_TOD_1PPS_NS_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_4_CFG_TOD_1PPS_NS_OFFSET_MASK 0x3fffffff + + +/* + * Register + * + * Debug register, used for loading TOD nanosecond counte for + * rollovertesting. + */ +#define WAN_TOP_TOD_CONFIG_5_REG 0x74 + +/* + * Rising edge immediately load cfg_tod_ns_offset into nanosecondcounter. + * This is mainly utilized for debugging. +*/ +#define WAN_TOP_TOD_CONFIG_5_CFG_TOD_LOAD_NS_OFFSET_MASK 0x40000000 + +/* + * Value to be loaded into nanosecond counter. + * The rollover value is at0x3B9ACA00. +*/ +#define WAN_TOP_TOD_CONFIG_5_CFG_TOD_NS_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_5_CFG_TOD_NS_OFFSET_MASK 0x3fffffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS48_MSB_REG 0x78 + +/* Upper 16-bits of TS48. */ +#define WAN_TOP_TOD_TS48_MSB_TS48_WAN_READ_MSB_SHIFT 0 +#define WAN_TOP_TOD_TS48_MSB_TS48_WAN_READ_MSB_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS48_LSB_REG 0x7c + +/* Lower 32-bits of TS48. */ +#define WAN_TOP_TOD_TS48_LSB_TS48_WAN_READ_LSB_SHIFT 0 +#define WAN_TOP_TOD_TS48_LSB_TS48_WAN_READ_LSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 64-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS64_MSB_REG 0x80 + +/* + * Upper value of TS64 : + * AE - second = ts64_wan_read_msb[18: + * 0]GPON - second[33: + * 2] = ts64_wan_read_msb[31: + * 0] +*/ +#define WAN_TOP_TOD_TS64_MSB_TS64_WAN_READ_MSB_SHIFT 0 +#define WAN_TOP_TOD_TS64_MSB_TS64_WAN_READ_MSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 64-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS64_LSB_REG 0x84 + +/* + * Lower value of TS64 : + * AE - nanosecond = ts64_wan_read_lsb[31: + * 0]GPON - second[1: + * 0] = ts64_wan_read_lsb[31: + * 30]; nanosecond =ts64_wan_read_lsb[29: + * 0]; +*/ +#define WAN_TOP_TOD_TS64_LSB_TS64_WAN_READ_LSB_SHIFT 0 +#define WAN_TOP_TOD_TS64_LSB_TS64_WAN_READ_LSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 16-bit timestamp read back. + */ +#define WAN_TOP_TOD_STATUS_0_REG 0x88 + +/* REF clock timestamp. */ +#define WAN_TOP_TOD_STATUS_0_TS16_REF_SYNCE_READ_SHIFT 0 +#define WAN_TOP_TOD_STATUS_0_TS16_REF_SYNCE_READ_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for 16-bit timestamp read back. + */ +#define WAN_TOP_TOD_STATUS_1_REG 0x8c + +/* TX MAC clock timestamp. */ +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_TX_READ_SHIFT 16 +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_TX_READ_MASK 0xffff0000 + +/* RX MAC clock timestamp. */ +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_RX_READ_SHIFT 0 +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_RX_READ_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for various WAN status bits. + */ +#define WAN_TOP_SERDES_STATUS_REG 0x90 + +/* Assertion of this signal indicates that the pll has achieved lock. */ +#define WAN_TOP_SERDES_STATUS_PMD_PLL1_LOCK_MASK 0x400 + +/* + * If set, the SERDES is attempting to enable the laser. + * The actualstate of the laser also depends on the laser output enable. +*/ +#define WAN_TOP_SERDES_STATUS_O_LASER_BURST_EN_MASK 0x200 + +/* + * Error response from RMIC slave indicating an address error whichmeans + * that either the block address does not exist or that the deviddid not + * match the strap value. + * The ack signal indicates that thetransaction is complete and the error + * signal indicates that therewas an address error with this transaction. + * This signal is assertedalong with the ack signal and should be treated + * an asynchronoussignal the same way as the ack signal. +*/ +#define WAN_TOP_SERDES_STATUS_PMI_LP_ERROR_MASK 0x100 + +/* + * Ack response back from the RMIC slave indicating that the write orread + * transaction is complete. + * This signal is driven in the registersblocks clock domain and should be + * treated as an asynchronous inputby the master. +*/ +#define WAN_TOP_SERDES_STATUS_PMI_LP_ACKNOWLEDGE_MASK 0x80 + +/* + * Signal detect status from the analog. + * This signal is not related toany interface clock or data validity. +*/ +#define WAN_TOP_SERDES_STATUS_PMD_SIGNAL_DETECT_0_MASK 0x40 + +/* EEE energy detect. */ +#define WAN_TOP_SERDES_STATUS_PMD_ENERGY_DETECT_0_MASK 0x20 + +/* + * Receive PMD lock. + * WHen this signal is low, the receiver isacquiring lock. + * During this period, the phase of the receive clockand alignment of data + * are not reliable. +*/ +#define WAN_TOP_SERDES_STATUS_PMD_RX_LOCK_0_MASK 0x10 + +/* Transmit clock valid. */ +#define WAN_TOP_SERDES_STATUS_PMD_TX_CLK_VLD_MASK 0x8 + +/* Receive clock valid. */ +#define WAN_TOP_SERDES_STATUS_PMD_RX_CLK_VLD_0_MASK 0x4 + +/* Assertion of this signal indicates that the pll has not achievedlock. */ +#define WAN_TOP_SERDES_STATUS_PMD_RX_LOCK_0_INVERT_MASK 0x2 + +/* Assertion of this signal indicates that the pll has achieved lock. */ +#define WAN_TOP_SERDES_STATUS_PMD_PLL0_LOCK_MASK 0x1 + + +/* + * Register + * + * Interrupts. + */ +#define WAN_TOP_INT_STATUS_REG 0x98 + +/* + * Indicates the sampling of clock counter, as specified bycfg_pll_smpl_prd + * sampling period. +*/ +#define WAN_TOP_INT_STATUS_CLK_SAMPLE_INT_MASK 0x1 + + +/* + * Register + * + * Interrupt masks. + */ +#define WAN_TOP_INT_MASK_REG 0x9c + +/* Interrupt mask, active low. */ +#define WAN_TOP_INT_MASK_MSK_CLK_SAMPLE_INT_MASK 0x1 + + +/* + * Register + * + * Clock dejittering control register. + */ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_REG 0xa0 + +/* + * Specifies the sampling period of the sampling counters, running inthe + * following domains : + * PON_SERDES : + * 10G - 515. + * 625 MHz; 2. + * 5G - 312. + * 5 MHz; 1G - 125 MHz;100FX - 25 MHz; GPON - 155. + * 5 MHz. + * LAN_SERDES : + * 156. + * 25 MHzSGPHY : + * 25 MHzDSL : + * 35. + * 328 MHzThe sampling counter should be set around 100 ms. + * The unit is ineach clock domain's period. + * Hence, sampling period = X value/frequency. +*/ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_CFG_PLL_SMPL_PRD_SHIFT 0 +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_CFG_PLL_SMPL_PRD_MASK 0x3ffffff + + +/* + * Register + * + * Clock dejittering control register. + */ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_REG 0xa4 + +/* Enable PBI write to SyncE_PLL integer/fractional dividers. */ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_CFG_EN_PBI_WR_2_SYNCE_PLL_MASK 0x10 + +/* + * Specifies the source of the sample pulse generator : + * 0 - PON_SERDES;1 - LAN_SERDES; 2 - SGPHY; 3 - DSL; 4 - NTR. + * This samples thecounter running in SyncE_PLL's 250 MHz clock domain. +*/ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_CFG_CLK_SMPL_SRC_SHIFT 0 +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_CFG_CLK_SMPL_SRC_MASK 0x7 + + +/* + * Register - read-only + * + * Clock counter sample register. + */ +#define WAN_TOP_CLK_SAMPLE_COUNTER_REG 0xa8 + +/* + * Sample clock counter value of SyncE_PLL's dejittering counter. + * Value should be read uponreceiving interrupt clk_sample_int. + * Difference in time is obtainedby subtracting currentvalue from previous. + * The value will be different for the differentsampling sources. +*/ +#define WAN_TOP_CLK_SAMPLE_COUNTER_PBI_CLK_CNT_SMPL_SHIFT 0 +#define WAN_TOP_CLK_SAMPLE_COUNTER_PBI_CLK_CNT_SMPL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the SyncE_PLL integer/fractional dividers, applicable + * whencfg_en_pbi_wr_2_syncE_pll is set. + */ +#define WAN_TOP_SYNCE_PLL_CONFIG_REG 0xac + +/* Integer divider. */ +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_INT_SHIFT 24 +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_INT_MASK 0xff000000 + +/* Fractional divider. */ +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_FRAC_SHIFT 0 +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_FRAC_MASK 0xffffff + + +/* + * Register + * + * Register used to control the oversample mode of the SERDES gearboxes. + */ +#define WAN_TOP_OSR_CONTROL_REG 0xb4 + +/* TBD */ +#define WAN_TOP_OSR_TXLBE_SER_ORDER_MASK 0x80 + +/* TBD */ +#define WAN_TOP_OSR_TXLBE_SER_INIT_VAL_SHIFT 4 +#define WAN_TOP_OSR_TXLBE_SER_INIT_VAL_MASK 0x70 + +/* TBD */ +#define WAN_TOP_OSR_TXLBE_SER_EN_MASK 0x8 + +/* + * 0: + * New oversample mode. + * 1: + * Legacy mode. +*/ +#define WAN_TOP_OSR_TXFIFO_RD_LEGACY_MODE_MASK 0x4 + +/* + * 0: + * Select div2 clock. + * 1: + * Select div4 clock. + * 2: + * Select legacy modeclocking. + * 3: + * Reserved. +*/ +#define WAN_TOP_OSR_CFG_GPON_RX_CLK_SHIFT 0 +#define WAN_TOP_OSR_CFG_GPON_RX_CLK_MASK 0x3 + + +/* + * Register - read-only + * + * Register used for various WAN status bits. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_REG 0x94 + +/* + * Status indication based on status_sel signals. + * Ifgpon_gearbox_fifo_status_sel is high, this status will + * begpon_gearbox_fifo_status. + * If gpon_gearbox_ptg_status1_sel is high,this status will be + * gpon_gearbox_ptg_status1. + * Ifgpon_gearbox_ptg_status2_sel is high, this status will + * begpon_gearbox_ptg_status2. +*/ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_CR_RD_DATA_CLX_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_CR_RD_DATA_CLX_MASK 0xffffffff + + +/* + * Register + * + * Register used to control the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_REG 0xb0 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_SIG_PRBS_STATUS_CLR_MASK 0x2000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_INV_MASK 0x1000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_OOL_CNT_SHIFT 19 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_OOL_CNT_MASK 0xf80000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_LOCK_CNT_SHIFT 14 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_LOCK_CNT_MASK 0x7c000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_ERR_CNT_BURST_MODE_MASK 0x2000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_MODE_SEL_SHIFT 10 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_MODE_SEL_MASK 0x1c00 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMEOUT_SHIFT 2 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMEOUT_MASK 0x7c + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMER_MODE_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMER_MODE_MASK 0x3 + + +/* + * Register + * + * Register used to control the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_REG 0xb8 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_EN_MASK 0x80000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_MODE_SHIFT 29 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_MODE_MASK 0x60000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_TIMER_VAL_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_TIMER_VAL_MASK 0xfffff + + +/* + * Register - read-only + * + * Register used to monitor the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_REG 0xbc + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_GPON_GEARBOX_PRBS_STAT_0_VECTOR_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_GPON_GEARBOX_PRBS_STAT_0_VECTOR_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used to monitor the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_REG 0xc0 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_GPON_GEARBOX_PRBS_STAT_1_VECTOR_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_GPON_GEARBOX_PRBS_STAT_1_VECTOR_MASK 0x3 + + +/* + * Register + * + * Register used to control AE Gearbox + */ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_REG 0xc4 + +/* + * Set to 1 then 0 to load initial offset value determined + * bycr_wan_top_ae_gearbox_tx_fifo_offset reg +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_TX_FIFO_OFFSET_SHIFT 4 +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_TX_FIFO_OFFSET_MASK 0x3f0 + +/* + * Set to 1 then 0 to load initial offset value determined + * bycr_wan_top_ae_gearbox_tx_fifo_offset reg +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_TX_FIFO_OFFSET_LD_MASK 0x4 + +/* + * 0 = compatible with sub rate serdes mode1 = compatible with full rate + * serdes mode. + * 100FX - sub rate only. + * 1G - sub/full rate2. + * 5G - sub/full rate10G - full rate only. +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_FULL_RATE_MODE_MASK 0x2 + +/* + * 0 = 10b mode1 = 20b mode100FX - 10b mode1G - 10b mode2. + * 5G - 10b mode10G - 20b mode +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_WIDTH_MODE_MASK 0x1 + + +/* + * Register + * + * Provides the divider for the voltage regulator sync output. + */ +#define WAN_TOP_VOLTAGE_REGULATOR_DIVIDER_IDER_REG 0xc8 + +/* Allows the bypassing of the N divider. */ +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_CLK_BYPASS_MASK 0x200 + +/* + * Specifies the clock source of the voltage regulator sync output : + * 1- VDSL PHY; 0 - 50 MHz XTAL clock. +*/ +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_CLK_SRC_MASK 0x100 + +/* + * N divider value of voltage regulator sync output. + * Assertive 1 valuewill be INT((N/2); and assertive 0, N - INT(N/2). +*/ +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_DIV_SHIFT 0 +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_DIV_MASK 0xff + + +/* + * Register + * + * Provides the configuration for clock syncing. + */ +#define WAN_TOP_CLOCK_SYNC_CONFIG_REG 0xcc + +/* + * Output enable for 1PPS output to GPIO, applicable only + * ifcfg_gpio_1pps_src is cleared. +*/ +#define WAN_TOP_CLOCK_SYNC_CONFIG_CFG_GPIO_1PPS_OEB_MASK 0x4 + +/* + * Selects the source of 1PPS output to GPIO : + * 0 - NCO; 1 - Switch. +*/ +#define WAN_TOP_CLOCK_SYNC_CONFIG_CFG_GPIO_1PPS_SRC_MASK 0x2 + +/* + * Selects the source of sync pulse output to switch : + * 0 - 1PPS; 1 -recovered PHY/SerDes clock. +*/ +#define WAN_TOP_CLOCK_SYNC_CONFIG_CFG_SWITCH_SYNCIN_SRC_MASK 0x1 + + +/* + * Register + * + * Provides the configuration for AE PCS IEEE device ID register. + */ +#define WAN_TOP_AEPCS_IEEE_REGID_REG 0xd0 + +/* The AE PCS IEEE device ID. */ +#define WAN_TOP_AEPCS_IEEEID_REG_CFG_AEPCS_IEEE_REGID_SHIFT 0 +#define WAN_TOP_AEPCS_IEEEID_REG_CFG_AEPCS_IEEE_REGID_MASK 0xffffffff + + +/* + * Register + * + * Register used to force the laser burst enable (LBE) and LBE outputenable + * signals. + */ +#define WAN_TOP_FORCE_LBE_CONTROL_REG 0xd4 + +/* + * This field is only used when cfg_force_lbe_oe is set. + * This signalis then inverted prior to connecting to the OEB pin. + * 0: + * LBE outputenable is set to 0. + * 1: + * LBE output enable is set to 1. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK 0x8 + +/* + * 0: + * The MAC and cr_xgwan_top_wan_misc_wan_cfg_laser_oe control theLBE output + * enable signal. + * 1: + * The LBE output enable signal is forcedto cfg_force_lbe_oe_value. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_OE_MASK 0x4 + +/* + * This field is only used when cfg_force_lbe is set. + * 0: + * LBE is set to0. + * 1: + * LBE is set to 1. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK 0x2 + +/* + * 0: + * The MAC controls the LBE signal. + * 1: + * The LBE signal is forced tocfg_force_lbe_value. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_MASK 0x1 + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_REG 0xd8 + +/* Value for RX output RIFO read pointer. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFIFORDPTR_SHIFT 24 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFIFORDPTR_MASK 0xf000000 + +/* Disable pointer auto-load going into lock for output FIFO. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXPTRAUTOLDDIS_MASK 0x800000 + +/* Number of bad KChar to go out of lock. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXBADK_SHIFT 20 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXBADK_MASK 0x700000 + +/* + * Use only K28. + * 5 for framing. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRMK28ONLY_MASK 0x80000 + +/* Number of good KChar in a row for lock. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXGOODK_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXGOODK_MASK 0x70000 + +/* Force 10b framer to go to HUNT state on rising edge. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCHUNT_MASK 0x8000 + +/* Bitwise flip 32b output data. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXOUTDATAFLIP_MASK 0x4000 + +/* Force mux select to value in cfNGponGboxRxFrcMuxVal. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCMUXSEL_MASK 0x2000 + +/* + * Value that will be forced to mux select when cfNGponGboxRxFrcMuxSelis + * asserted. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCMUXVAL_SHIFT 8 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCMUXVAL_MASK 0x1f00 + +/* Bitwise flip RX 20b gearbox data. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRX20BDATAFLIP_MASK 0x80 + +/* Bitwise flip RX 16b data from SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXSERDATAFLIP_MASK 0x40 + +/* Bitwise invert RX 16b data from SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXSERDATAINV_MASK 0x20 + +/* + * Load value for FIFO read pointer. + * Write pointer will be loaded to0. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFIFOPTRLD_MASK 0x10 + +/* When set, synchronization will be held indefinitely. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXSWSYNCHOLD_MASK 0x8 + +/* + * 0. + * 8B/10B decoder mode operating at 777 MHz. + * 1. + * Pass through modeoperating at 622 MHz. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMODE_MASK 0x4 + +/* Synchronous enable for RX gearbox. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXEN_MASK 0x2 + +/* Asynchronous, active-low, software reset for gearbox. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRSTN_MASK 0x1 + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_1_REG 0xdc + +/* Max counter for 125 us timer. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_1_CFNGPONGBOXRXMAXTIMERCNT_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_1_CFNGPONGBOXRXMAXTIMERCNT_MASK 0x1ffff + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_REG 0xe0 + +/* + * RD+ K28. + * 5 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDP_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDP_MASK 0x3ff0000 + +/* + * RD- K28. + * 5 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDN_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDN_MASK 0x3ff + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_REG 0xe4 + +/* + * RD+ D5. + * 7 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDP_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDP_MASK 0x3ff0000 + +/* + * RD- D5. + * 7 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDN_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDN_MASK 0x3ff + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_REG 0xe8 + +/* + * Value for TX data FIFO read pointer. + * Steps of 2 x txClk (622 MHz),jumps of 32 bits. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFODATARDPTR_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFODATARDPTR_MASK 0xf0000 + +/* + * Value for TX valid FIFO offset. + * Steps of txClk (622 MHz), jumps of16 bits. + * 1 to 15 are advances valid vs data, valid comes out ahead. + * 1=1 clock, 2=2 clocks, 3=3 clocks. + * .. + * 31 to 16 are advances validvs data, valid comes out behind. + * 31=1 clock, 30=2 clocks, 29=3clocks. + * .. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOVLDOFF_SHIFT 8 +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOVLDOFF_MASK 0x1f00 + +/* Flip TX data valid endian on 32b input. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERVLDFLIP_MASK 0x40 + +/* Flip TX data endian on 32b input. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERDATAFLIP_MASK 0x20 + +/* Bitwise invert TX 4b valid to SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERVLDINV_MASK 0x10 + +/* Bitwise invert TX 16b data to SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERDATAINV_MASK 0x8 + +/* + * Load only the offset for TX valid FIFO pointer. + * This is an offsetfrom the data read pointer. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOVLDPTRLD_MASK 0x4 + +/* + * Load value for TX data FIFO read pointer and valid read pointeroffset. + * Data/valid write will be loaded to 0. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOPTRLD_MASK 0x2 + +/* Synchronous enable for TX gearbox. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXEN_MASK 0x1 + + +/* + * Register + * + * Status for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_REG 0xec + +/* Pointer collision. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONTXGBOXFIFOVLDPTRCOL_MASK 0x4000000 + +/* Framer state. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXSTATE_SHIFT 24 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXSTATE_MASK 0x3000000 + +/* Pointer collision. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONTXGBOXFIFODATAPTRCOL_MASK 0x800000 + +/* Number of KChar. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXKCNT_SHIFT 20 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXKCNT_MASK 0x700000 + +/* Pointer delta. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXFIFOPTRDELTA_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXFIFOPTRDELTA_MASK 0xf0000 + +/* 10b sync acquired. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXSYNCACQ_MASK 0x8000 + +/* FIFO pointer collision. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXFIFOPTRCOL_MASK 0x4000 + +/* Line errors. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXCODEERRCNTSTAT_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXCODEERRCNTSTAT_MASK 0x3fff + + +/* + * Register + * + * Configuration for the 10G EPON gearbox. + */ +#define WAN_TOP_EPON_10G_GEARBOX_REG 0xf0 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_RX_CGEN_RSTN_MASK 0x1 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_CGEN_RSTN_MASK 0x2 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_RX_GBOX_RSTN_MASK 0x4 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_GBOX_RSTN_MASK 0x8 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_CLK_EN_MASK 0x10 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_RX_DATA_END_MASK 0x20 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX2RX_LOOP_EN_MASK 0x40 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_FIFO_OFF_LD_MASK 0x80 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_FIFO_OFF_SHIFT 8 +#define WAN_TOP_EPON_10G_GEARBOX_TX_FIFO_OFF_MASK 0x700 + +/* Reserved */ +#define WAN_TOP_EPON_10G_GEARBOX_R0_SHIFT 11 +#define WAN_TOP_EPON_10G_GEARBOX_R0_MASK 0xfffff800 + + +#endif /* ! WAN_TOP_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xlif.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xlif.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xlif.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xlif.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,209 @@ +#ifndef XLIF_H_ +#define XLIF_H_ + +/* + * Register + * + * Interface_Disable + */ +#define XLIF_RX_IF_IF_DIS_REG(x) (0x0 + (x) * 0x200) + +/* Disable */ +#define XLIF_RX_IF_IF_DIS_DISABLE_MASK 0x1 + + +/* + * Register - read-only + * + * Indicate an overflow event (data valid while FIFO is full). + * read clear + */ +#define XLIF_RX_IF_OFLW_FLAG_REG 0x4 + +/* Overflow */ +#define XLIF_RX_IF_OFLW_FLAG_OFLW_MASK 0x1 + + +/* + * Register - read-only + * + * Indicate RX protocol Error. + * read clear + */ +#define XLIF_RX_IF_ERR_FLAG_REG 0x8 + +/* Error */ +#define XLIF_RX_IF_ERR_FLAG_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * eee indications from the XLMAC interface + */ +#define XLIF_EEE_IND_REG(r) (0x78 + (r) * 0x200) + +/* lpi_rx_detect */ +#define XLIF_EEE_IND_LPI_RX_DETECT_MASK 0x1 + +/* lpi_tx_detect */ +#define XLIF_EEE_IND_LPI_TX_DETECT_MASK 0x10 + + +/* + * Register - read-only + * + * . + */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_EN_REG(r) (0x20 + (r) * 0x200) + +/* PFC_EN */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_EN_PFC_EN_MASK 0x1 + +/* LLFC_en */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_EN_LLFC_EN_MASK 0x10 + + +/* + * Register - read-only + * + * . + */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_REG(r) (0x24 + (r) * 0x200) + +/* value */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_VALUE_SHIFT 0 +#define XLIF_RX_FLOW_CONTROL_COSMAP_VALUE_MASK 0xffff + + +/* + * Register + * + * Interface_Enable + */ +#define XLIF_TX_IF_IF_ENABLE_REG(r) (0x40 + (r) * 0x200) + +/* Disable_With_Credits */ +#define XLIF_TX_IF_IF_ENABLE_DISABLE_WITH_CREDITS_MASK 0x1 + +/* Disable_WO_Credits */ +#define XLIF_TX_IF_IF_ENABLE_DISABLE_WO_CREDITS_MASK 0x2 + + +/* + * Register - read-only + * + * Read_Credits + */ +#define XLIF_TX_IF_READ_CREDITS_REG(r) (0x44 + (r) * 0x200) + +/* Value */ +#define XLIF_TX_IF_READ_CREDITS_VALUE_SHIFT 0 +#define XLIF_TX_IF_READ_CREDITS_VALUE_MASK 0x3ff + + +/* + * Register + * + * Set_CreditsThe enable bit and the new value can be set together. + * Then, the enable bit must be turned off, while the new value remain + * stable. + */ +#define XLIF_TX_IF_SET_CREDITS_REG(r) (0x48 + (r) * 0x200) + +/* Value */ +#define XLIF_TX_IF_SET_CREDITS_VALUE_SHIFT 0 +#define XLIF_TX_IF_SET_CREDITS_VALUE_MASK 0x3ff + +/* enable */ +#define XLIF_TX_IF_SET_CREDITS_EN_MASK 0x1000 + + +/* + * Register + * + * Control the values of several output signals on the XRDP -> XLMAC + * interface. + */ +#define XLIF_TX_IF_OUT_CTRL_REG(r) (0x4c + (r) * 0x200) + +/* mac_txerr */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXERR_MASK 0x1 + +/* mac_txcrcerr */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXCRCERR_MASK 0x2 + +/* mac_txosts_sinext */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXOSTS_SINEXT_MASK 0x4 + +/* mac_txcrcmode */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXCRCMODE_SHIFT 4 +#define XLIF_TX_IF_OUT_CTRL_MAC_TXCRCMODE_MASK 0x30 + + +/* + * Register + * + * Underrun_Protection_Enable + */ +#define XLIF_TX_IF_URUN_PORT_ENABLE_REG(r) (0x50 + (r) * 0x200) + +/* Enable */ +#define XLIF_TX_IF_URUN_PORT_ENABLE_ENABLE_MASK 0x1 + + +/* + * Register + * + * TX threshold for the TX CDC FIFO in units of 128 bit. + * The TX CDC FIFO is depth is 16 entries. + */ +#define XLIF_TX_IF_TX_THRESHOLD_REG(r) (0x54 + (r) * 0x200) + +/* Value */ +#define XLIF_TX_IF_TX_THRESHOLD_VALUE_SHIFT 0 +#define XLIF_TX_IF_TX_THRESHOLD_VALUE_MASK 0xf + + +/* + * Register - read-only + * + * cosmap_en indications from the XLMAC Interface + */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_EN_STAT_REG(r) (0x60 + (r) * 0x200) + +/* PFC_EN */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_EN_STAT_PFC_EN_MASK 0x1 + +/* LLFC_en */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_EN_STAT_LLFC_EN_MASK 0x10 + + +/* + * Register - read-only + * + * cosmap_status from the XLMAC Interface + */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_STAT_REG(r) (0x64 + (r) * 0x200) + +/* value */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_STAT_VALUE_SHIFT 0 +#define XLIF_TX_FLOW_CONTROL_COSMAP_STAT_VALUE_MASK 0xffff + + +/* + * Register - read-only + * + * indications from the XLMAC IF + */ +#define XLIF_Q_OFF_IND_REG(r) (0x7c + (r) * 0x200) + +/* Q_OFF */ +#define XLIF_Q_OFF_IND_Q_OFF_SHIFT 0 +#define XLIF_Q_OFF_IND_Q_OFF_MASK 0xff + +/* Failover_on */ +#define XLIF_Q_OFF_IND_FAILOVER_ON_MASK 0x100 + + +#endif /* ! XLIF_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mab.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mab.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mab.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mab.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,164 @@ +#ifndef WAN_TOPXPORT_MAB_H_ +#define WAN_TOPXPORT_MAB_H_ + +/* relative to core */ +#define XPORT_MAB_OFFSET_0 0x3300 + +/* + * Register + * + */ +#define XPORT_MAB_CNTRL_REG 0x0 + +/* + * When this bit is set asynchronous RX and TX FIFOs are reset for a port + * when the link goes down that is when the local fault is detected. +*/ +#define CNTRL_LINK_DOWN_RST_EN_MASK 0x10000 + +/* + * When set resets 10G Port 0 asynchronous TX FIFO and associated logic + * (such as credit logic). +*/ +#define CNTRL_XGMII_TX_RST_MASK 0x1000 + +/* + * When a bit in this vector is set it resets corresponding port (Port 3-0) + * asynchronous TX FIFO and associated logic (such as credit logic and byte + * slicers). +*/ +#define CNTRL_GMII_TX_RST_SHIFT 8 +#define CNTRL_GMII_TX_RST_MASK 0xf00 + +/* When set resets 10G Port 0 asynchronous RX FIFO and associated logic. */ +#define CNTRL_XGMII_RX_RST_MASK 0x10 + +/* + * When a bit in this vector is set it resets corresponding port (Port 3-0) + * asynchronous RX FIFO and associated logic (such as byte packers). +*/ +#define CNTRL_GMII_RX_RST_SHIFT 0 +#define CNTRL_GMII_RX_RST_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MAB_TX_WRR_CTRL_REG 0x4 + +/* + * Arbiter Mode 1'b0 - Fixed Mode. + * TDM slots allocated regardless of the port activity. + * 1'b1 - Work-Conserving Mode. + * TDM slots allocation is affected by the port activity. +*/ +#define TX_WRR_CTRL_ARB_MODE_MASK 0x10000 + +/* P3 weight expressed in TDM time slots. */ +#define TX_WRR_CTRL_P3_WEIGHT_SHIFT 12 +#define TX_WRR_CTRL_P3_WEIGHT_MASK 0xf000 + +/* P2 weight expressed in TDM time slots. */ +#define TX_WRR_CTRL_P2_WEIGHT_SHIFT 8 +#define TX_WRR_CTRL_P2_WEIGHT_MASK 0xf00 + +/* P1 weight expressed in TDM time slots. */ +#define TX_WRR_CTRL_P1_WEIGHT_SHIFT 4 +#define TX_WRR_CTRL_P1_WEIGHT_MASK 0xf0 + +/* + * P0 weight expressed in TDM time slots. + * Note: + * Arbitration weights should not be changed from their default values due + * to XLMAC implementation specifics. + * In 4-port mode MSBUS clock should be set to 4*MAX_PORT_RATE/64. +*/ +#define TX_WRR_CTRL_P0_WEIGHT_SHIFT 0 +#define TX_WRR_CTRL_P0_WEIGHT_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MAB_TX_THRESHOLD_REG 0x8 + +/* + * XGMII0 (P0) asynchronous TX FIFO read depth at which packet dequeue + * starts. +*/ +#define TX_THRESHOLD_XGMII0_TX_THRESHOLD_SHIFT 16 +#define TX_THRESHOLD_XGMII0_TX_THRESHOLD_MASK 0xf0000 + +/* GMII P3 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII3_TX_THRESHOLD_SHIFT 12 +#define TX_THRESHOLD_GMII3_TX_THRESHOLD_MASK 0xf000 + +/* GMII P2 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII2_TX_THRESHOLD_SHIFT 8 +#define TX_THRESHOLD_GMII2_TX_THRESHOLD_MASK 0xf00 + +/* GMII P1 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII1_TX_THRESHOLD_SHIFT 4 +#define TX_THRESHOLD_GMII1_TX_THRESHOLD_MASK 0xf0 + +/* GMII P0 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII0_TX_THRESHOLD_SHIFT 0 +#define TX_THRESHOLD_GMII0_TX_THRESHOLD_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MAB_LINK_DOWN_TX_DATA_REG 0xc + +/* + * When LINK_DOWN_RST_EN = 1 and link is down content of this register is + * sent to serdes over XGMII interface. + * In GMII mode 0 is sent. +*/ +#define LINK_DOWN_TX_DATA_TXCTL_MASK 0x100 + +/* + * When LINK_DOWN_RST_EN = 1 and link is down content of this register is + * sent to serdes over XGMII interface. + * In GMII mode 0's are sent. +*/ +#define LINK_DOWN_TX_DATA_TXD_SHIFT 0 +#define LINK_DOWN_TX_DATA_TXD_MASK 0xff + + +/* + * Register - read-only + * + */ +#define XPORT_MAB_STATUS_REG 0x10 + +/* 10G Port 0 asynchronous RX FIFO over-run status. */ +#define STATUS_XGMII_RX_AFIFO_OVERRUN_MASK 0x8000 + +/* Port 3-0 asynchronous RX FIFO over-run status. */ +#define STATUS_GMII_RX_AFIFO_OVERRUN_VECT_SHIFT 11 +#define STATUS_GMII_RX_AFIFO_OVERRUN_VECT_MASK 0x7800 + +/* 10G Port 0 TX frame under-run status. */ +#define STATUS_XGMII_TX_FRM_UNDERRUN_MASK 0x400 + +/* 10G Port 0 TX credits under-run status. */ +#define STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_MASK 0x200 + +/* Port 3-0 TX credits under-run status. */ +#define STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_SHIFT 5 +#define STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_MASK 0x1e0 + +/* 10G Port 0 asynchronous TX FIFO over-run status. */ +#define STATUS_XGMII_TX_AFIFO_OVERRUN_MASK 0x10 + +/* Port 3-0 asynchronous TX FIFO over-run status. */ +#define STATUS_GMII_TX_AFIFO_OVERRUN_VECT_SHIFT 0 +#define STATUS_GMII_TX_AFIFO_OVERRUN_VECT_MASK 0xf + + +#endif /* ! WAN_TOPXPORT_MAB_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_core.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_core.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_core.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_core.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,117 @@ +#ifndef WAN_TOPXPORT_MIB_CORE_H_ +#define WAN_TOPXPORT_MIB_CORE_H_ + +/* relative to core */ +#define XPORT_MIB_CORE_OFFSET(x) (0x1000 + (x) * 0x400) + +#define XPORT_MIB_CORE_GRX64_REG 0x0 +#define XPORT_MIB_CORE_GRX127_REG 0x8 +#define XPORT_MIB_CORE_GRX255_REG 0x10 +#define XPORT_MIB_CORE_GRX511_REG 0x18 +#define XPORT_MIB_CORE_GRX1023_REG 0x20 +#define XPORT_MIB_CORE_GRX1518_REG 0x28 +#define XPORT_MIB_CORE_GRX1522_REG 0x30 +#define XPORT_MIB_CORE_GRX2047_REG 0x38 +#define XPORT_MIB_CORE_GRX4095_REG 0x40 +#define XPORT_MIB_CORE_GRX9216_REG 0x48 +#define XPORT_MIB_CORE_GRX16383_REG 0x50 +#define XPORT_MIB_CORE_GRXPKT_REG 0x58 +#define XPORT_MIB_CORE_GRXUCA_REG 0x60 +#define XPORT_MIB_CORE_GRXMCA_REG 0x68 +#define XPORT_MIB_CORE_GRXBCA_REG 0x70 +#define XPORT_MIB_CORE_GRXFCS_REG 0x78 +#define XPORT_MIB_CORE_GRXCF_REG 0x80 +#define XPORT_MIB_CORE_GRXPF_REG 0x88 +#define XPORT_MIB_CORE_GRXPP_REG 0x90 +#define XPORT_MIB_CORE_GRXUO_REG 0x98 +#define XPORT_MIB_CORE_GRXUDA_REG 0xa0 +#define XPORT_MIB_CORE_GRXWSA_REG 0xa8 +#define XPORT_MIB_CORE_GRXALN_REG 0xb0 +#define XPORT_MIB_CORE_GRXFLR_REG 0xb8 +#define XPORT_MIB_CORE_GRXFRERR_REG 0xc0 +#define XPORT_MIB_CORE_GRXFCR_REG 0xc8 +#define XPORT_MIB_CORE_GRXOVR_REG 0xd0 +#define XPORT_MIB_CORE_GRXJBR_REG 0xd8 +#define XPORT_MIB_CORE_GRXMTUE_REG 0xe0 +#define XPORT_MIB_CORE_GRXMCRC_REG 0xe8 +#define XPORT_MIB_CORE_GRXPRM_REG 0xf0 +#define XPORT_MIB_CORE_GRXVLN_REG 0xf8 +#define XPORT_MIB_CORE_GRXDVLN_REG 0x100 +#define XPORT_MIB_CORE_GRXTRFU_REG 0x108 +#define XPORT_MIB_CORE_GRXPOK_REG 0x110 +#define XPORT_MIB_CORE_GRXPFCOFF0_REG 0x118 +#define XPORT_MIB_CORE_GRXPFCOFF1_REG 0x120 +#define XPORT_MIB_CORE_GRXPFCOFF2_REG 0x128 +#define XPORT_MIB_CORE_GRXPFCOFF3_REG 0x130 +#define XPORT_MIB_CORE_GRXPFCOFF4_REG 0x138 +#define XPORT_MIB_CORE_GRXPFCOFF5_REG 0x140 +#define XPORT_MIB_CORE_GRXPFCOFF6_REG 0x148 +#define XPORT_MIB_CORE_GRXPFCOFF7_REG 0x150 +#define XPORT_MIB_CORE_GRXPFCP0_REG 0x158 +#define XPORT_MIB_CORE_GRXPFCP1_REG 0x160 +#define XPORT_MIB_CORE_GRXPFCP2_REG 0x168 +#define XPORT_MIB_CORE_GRXPFCP3_REG 0x170 +#define XPORT_MIB_CORE_GRXPFCP4_REG 0x178 +#define XPORT_MIB_CORE_GRXPFCP5_REG 0x180 +#define XPORT_MIB_CORE_GRXPFCP6_REG 0x188 +#define XPORT_MIB_CORE_GRXPFCP7_REG 0x190 +#define XPORT_MIB_CORE_GRXSCHCRC_REG 0x198 +#define XPORT_MIB_CORE_GRXBYT_REG 0x1a0 +#define XPORT_MIB_CORE_GRXRPKT_REG 0x1a8 +#define XPORT_MIB_CORE_GRXUND_REG 0x1b0 +#define XPORT_MIB_CORE_GRXFRG_REG 0x1b8 +#define XPORT_MIB_CORE_GRXRBYT_REG 0x1c0 +#define XPORT_MIB_CORE_GTX64_REG 0x1c8 +#define XPORT_MIB_CORE_GTX127_REG 0x1d0 +#define XPORT_MIB_CORE_GTX255_REG 0x1d8 +#define XPORT_MIB_CORE_GTX511_REG 0x1e0 +#define XPORT_MIB_CORE_GTX1023_REG 0x1e8 +#define XPORT_MIB_CORE_GTX1518_REG 0x1f0 +#define XPORT_MIB_CORE_GTX1522_REG 0x1f8 +#define XPORT_MIB_CORE_GTX2047_REG 0x200 +#define XPORT_MIB_CORE_GTX4095_REG 0x208 +#define XPORT_MIB_CORE_GTX9216_REG 0x210 +#define XPORT_MIB_CORE_GTX16383_REG 0x218 +#define XPORT_MIB_CORE_GTXPOK_REG 0x220 +#define XPORT_MIB_CORE_GTXPKT_REG 0x228 +#define XPORT_MIB_CORE_GTXUCA_REG 0x230 +#define XPORT_MIB_CORE_GTXMCA_REG 0x238 +#define XPORT_MIB_CORE_GTXBCA_REG 0x240 +#define XPORT_MIB_CORE_GTXPF_REG 0x248 +#define XPORT_MIB_CORE_GTXPFC_REG 0x250 +#define XPORT_MIB_CORE_GTXJBR_REG 0x258 +#define XPORT_MIB_CORE_GTXFCS_REG 0x260 +#define XPORT_MIB_CORE_GTXCF_REG 0x268 +#define XPORT_MIB_CORE_GTXOVR_REG 0x270 +#define XPORT_MIB_CORE_GTXDFR_REG 0x278 +#define XPORT_MIB_CORE_GTXEDF_REG 0x280 +#define XPORT_MIB_CORE_GTXSCL_REG 0x288 +#define XPORT_MIB_CORE_GTXMCL_REG 0x290 +#define XPORT_MIB_CORE_GTXLCL_REG 0x298 +#define XPORT_MIB_CORE_GTXXCL_REG 0x2a0 +#define XPORT_MIB_CORE_GTXFRG_REG 0x2a8 +#define XPORT_MIB_CORE_GTXERR_REG 0x2b0 +#define XPORT_MIB_CORE_GTXVLN_REG 0x2b8 +#define XPORT_MIB_CORE_GTXDVLN_REG 0x2c0 +#define XPORT_MIB_CORE_GTXRPKT_REG 0x2c8 +#define XPORT_MIB_CORE_GTXUFL_REG 0x2d0 +#define XPORT_MIB_CORE_GTXPFCP0_REG 0x2d8 +#define XPORT_MIB_CORE_GTXPFCP1_REG 0x2e0 +#define XPORT_MIB_CORE_GTXPFCP2_REG 0x2e8 +#define XPORT_MIB_CORE_GTXPFCP3_REG 0x2f0 +#define XPORT_MIB_CORE_GTXPFCP4_REG 0x2f8 +#define XPORT_MIB_CORE_GTXPFCP5_REG 0x300 +#define XPORT_MIB_CORE_GTXPFCP6_REG 0x308 +#define XPORT_MIB_CORE_GTXPFCP7_REG 0x310 +#define XPORT_MIB_CORE_GTXNCL_REG 0x318 +#define XPORT_MIB_CORE_GTXBYT_REG 0x320 +#define XPORT_MIB_CORE_GRXLPI_REG 0x328 +#define XPORT_MIB_CORE_GRXDLPI_REG 0x330 +#define XPORT_MIB_CORE_GTXLPI_REG 0x338 +#define XPORT_MIB_CORE_GTXDLPI_REG 0x340 +#define XPORT_MIB_CORE_GRXPTLLFC_REG 0x348 +#define XPORT_MIB_CORE_GRXLTLLFC_REG 0x350 +#define XPORT_MIB_CORE_GRXLLFCFCS_REG 0x358 +#define XPORT_MIB_CORE_GTXLTLLFC_REG 0x360 + +#endif /* ! WAN_TOPXPORT_MIB_CORE_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_reg.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_reg.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_reg.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_reg.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,706 @@ +#ifndef WAN_TOPXPORT_MIB_REG_H_ +#define WAN_TOPXPORT_MIB_REG_H_ + +/* relative to core */ +#define XPORT_MIB_REG_OFFSET_0 0x3100 + +/* + * Register + * + */ +#define XPORT_MIB_REG_DIR_ACC_DATA_WRITE_REG 0x0 + +/* + * Direct register access data write register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_SHIFT 0 +#define XPORT_MIB_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_DIR_ACC_DATA_READ_REG 0x4 + +/* + * Direct register access data read register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_DIR_ACC_DATA_READ_REG_READ_DATA_SHIFT 0 +#define XPORT_MIB_DIR_ACC_DATA_READ_REG_READ_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG 0x8 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_OFFSET_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_REG 0xc + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_REG 0x10 + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG 0x14 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_OFFSET_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_REG 0x18 + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_REG 0x1c + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_CNTRL_REG 0x20 + +/* + * RX and TX EEE Duration Counter Behavior 0 : + * Counter behavior is asymmetric mode (100Base-TX, for example). + * 1 : + * Counter behavior is symmetric mode (1000Base-T, for example). +*/ +#define XPORT_MIB_CNTRL_REG_EEE_CNT_MODE_SHIFT 12 +#define XPORT_MIB_CNTRL_REG_EEE_CNT_MODE_MASK 0xf000 + +/* + * When a bit in this vector is set corresponding XLMAC port statistic + * counters saturate at their respective maximum values. +*/ +#define XPORT_MIB_CNTRL_REG_SATURATE_EN_SHIFT 8 +#define XPORT_MIB_CNTRL_REG_SATURATE_EN_MASK 0xf00 + +/* + * When a bit in this vector is set corresponding XLMAC port statistic + * counters are clear-on-read. +*/ +#define XPORT_MIB_CNTRL_REG_COR_EN_SHIFT 4 +#define XPORT_MIB_CNTRL_REG_COR_EN_MASK 0xf0 + +/* + * When a bit in this vector is set corresponding XLMAC port statistic + * counters are reset. +*/ +#define XPORT_MIB_CNTRL_REG_CNT_RST_SHIFT 0 +#define XPORT_MIB_CNTRL_REG_CNT_RST_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_REG 0x24 + +/* + * Timer to generate 10us pulse based on 25MHz refclk. + * Using LFSR to count up to 250 value. +*/ +#define XPORT_MIB_EEE_PULSE_DURATION_CNTRL_REG_CNT_SHIFT 0 +#define XPORT_MIB_EEE_PULSE_DURATION_CNTRL_REG_CNT_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_REG 0x28 + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT0_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT0_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_REG 0x2c + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT1_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT1_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_REG 0x30 + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT2_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT2_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_REG 0x34 + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT3_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT3_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_ECC_CNTRL_REG 0x38 + +/* ECC enable for Tx MIB memories. */ +#define XPORT_MIB_ECC_CNTRL_REG_TX_MIB_ECC_EN_MASK 0x2 + +/* ECC enable for Rx MIB memories. */ +#define XPORT_MIB_ECC_CNTRL_REG_RX_MIB_ECC_EN_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_FORCE_SB_ECC_ERR_REG 0x3c + +/* + * Self-clearing. + * Force Tx MIB memory instance 3 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM3_SERR_MASK 0x100 + +/* + * Self-clearing. + * Force Tx MIB memory instance 2 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM2_SERR_MASK 0x80 + +/* + * Self-clearing. + * Force Tx MIB memory instance 1 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM1_SERR_MASK 0x40 + +/* + * Self-clearing. + * Force Tx MIB memory instance 0 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM0_SERR_MASK 0x20 + +/* + * Self-clearing. + * Force Rx MIB memory instance 4 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM4_SERR_MASK 0x10 + +/* + * Self-clearing. + * Force Rx MIB memory instance 3 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM3_SERR_MASK 0x8 + +/* + * Self-clearing. + * Force Rx MIB memory instance 2 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM2_SERR_MASK 0x4 + +/* + * Self-clearing. + * Force Rx MIB memory instance 1 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM1_SERR_MASK 0x2 + +/* + * Self-clearing. + * Force Rx MIB memory instance 0 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM0_SERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_FORCE_DB_ECC_ERR_REG 0x40 + +/* + * Self-clearing. + * Force Tx MIB memory instance 3 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM3_DERR_MASK 0x100 + +/* + * Self-clearing. + * Force Tx MIB memory instance 2 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM2_DERR_MASK 0x80 + +/* + * Self-clearing. + * Force Tx MIB memory instance 1 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM1_DERR_MASK 0x40 + +/* + * Self-clearing. + * Force Tx MIB memory instance 0 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM0_DERR_MASK 0x20 + +/* + * Self-clearing. + * Force Rx MIB memory instance 4 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM4_DERR_MASK 0x10 + +/* + * Self-clearing. + * Force Rx MIB memory instance 3 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM3_DERR_MASK 0x8 + +/* + * Self-clearing. + * Force Rx MIB memory instance 2 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM2_DERR_MASK 0x4 + +/* + * Self-clearing. + * Force Rx MIB memory instance 1 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM1_DERR_MASK 0x2 + +/* + * Self-clearing. + * Force Rx MIB memory instance 0 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM0_DERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_REG 0x44 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_REG 0x48 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_REG 0x4c + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_REG 0x50 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_REG 0x54 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_REG 0x58 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_REG 0x5c + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_REG 0x60 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_REG 0x64 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +#endif /* ! WAN_TOPXPORT_MIB_REG_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_reg.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_reg.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_reg.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_reg.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,842 @@ +#ifndef WAN_TOPXPORT_REG_H_ +#define WAN_TOPXPORT_REG_H_ + +/* relative to core */ +#define XPORT_REG_OFFSET_0 0x2004 + +/* + * Register - read-only + * + */ +#define XPORT_REG_XPORT_REVISION_REG 0x0 + +/* XPORT revision. */ +#define XPORT_XPORT_REVISION_REG_XPORT_REV_SHIFT 0 +#define XPORT_XPORT_REVISION_REG_XPORT_REV_MASK 0xffffff + + +/* + * Register + * + */ +#define XPORT_REG_LED_PWM_CNTRL_REG 0x68 + +/* When set LED intensity can be controlled using PWM. */ +#define XPORT_LED_PWM_CNTRL_REG_PWM_ENABLE_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_REG_LED_INTENSITY_CNTRL_REG 0x6c + +/* + * LED_ON_TIME PWM modulated ON (low) time. + * LED_ON_LOW and LED_ON_HIGH determine PWM duty cycle for the LED + * intensity. + * Expressed in 50us units. +*/ +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_LOW_SHIFT 16 +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_LOW_MASK 0xffff0000 + +/* + * LED_ON_TIME PWM modulated OFF (high) time. + * LED_ON_LOW and LED_ON_HIGH determine PWM duty cycle for the LED + * intensity. + * Expressed in 50us units. +*/ +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_HIGH_SHIFT 0 +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_HIGH_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_LED_0_CNTRL_REG 0x70 + +/* + * When this bit is set MAC/PHY provided link indication is overridden + * using lnk_status_ovrd. +*/ +#define XPORT_LED_0_CNTRL_REG_LNK_OVRD_EN_MASK 0x8000 + +/* + * When this bit is set MAC/PHY provided speed indications are overridden + * using led_spd_ovrd[2: + * 0]. +*/ +#define XPORT_LED_0_CNTRL_REG_SPD_OVRD_EN_MASK 0x4000 + +/* + * Link status override. + * Used only for LED. +*/ +#define XPORT_LED_0_CNTRL_REG_LNK_STATUS_OVRD_MASK 0x2000 + +/* + * LED speed override. + * Default encoding is: + * 000 : + * 10Mb/s. + * 001 : + * 100Mb/s. + * 010 : + * 1000Mb/s. + * 011 : + * 2. + * 5Gb/s. + * 100 : + * 10Gb/s or higher. + * 101 : + * Custom speed 1. + * 110 : + * Custom speed 2. + * 111 : + * no-link. + * Using this register LED speeds can be encoded in any way that suits + * customer application. +*/ +#define XPORT_LED_0_CNTRL_REG_LED_SPD_OVRD_SHIFT 10 +#define XPORT_LED_0_CNTRL_REG_LED_SPD_OVRD_MASK 0x1c00 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for ACT_LED. +*/ +#define XPORT_LED_0_CNTRL_REG_ACT_LED_POL_SEL_MASK 0x200 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[2]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED2_ACT_POL_SEL_MASK 0x100 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[1]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED1_ACT_POL_SEL_MASK 0x80 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[0]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED0_ACT_POL_SEL_MASK 0x40 + +/* + * Selects source of activity for ACT_LED. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_0_CNTRL_REG_ACT_LED_ACT_SEL_MASK 0x20 + +/* + * Selects source of activity for SPDLNK_LED[2]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED2_ACT_SEL_MASK 0x10 + +/* + * Selects source of activity for SPDLNK_LED[1]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED1_ACT_SEL_MASK 0x8 + +/* + * Selects source of the activity for SPDLNK_LED[0]: + * 0 : + * LED is 0 when link is up and blinks when there is activity. + * 1 : + * LED is 1 and blinks when there is activity. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED0_ACT_SEL_MASK 0x4 + +/* Enables TX_SOP event to contribute to the activity. */ +#define XPORT_LED_0_CNTRL_REG_TX_ACT_EN_MASK 0x2 + +/* Enables RX_SOP event to contribute to the activity. */ +#define XPORT_LED_0_CNTRL_REG_RX_ACT_EN_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_REG_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG 0x74 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Gb/s and higher link speed. + * When SPDLNK_LED_SEL[x] = 1'''b0, SPDLNK_LED[x] is driven by bits [17: + * 0] of Link and Speed Encoding Register. + * When SPDLNK_LED_SEL[x] = 1'''b1, SPDLNK_LED[x] is driven by the + * activity. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_SHIFT 15 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 2500Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_SHIFT 12 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 1000Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_SHIFT 9 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_SHIFT 6 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_SHIFT 3 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_0_LINK_AND_SPEED_ENCODING_REG 0x78 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Gb/s and higherlink speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_SHIFT 15 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 2. + * 5Gb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_SHIFT 12 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 1Gb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_SHIFT 9 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_SHIFT 6 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_SHIFT 3 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_1_CNTRL_REG 0x7c + +/* + * When this bit is set MAC/PHY provided link indication is overridden + * using lnk_status_ovrd. +*/ +#define XPORT_LED_1_CNTRL_REG_LNK_OVRD_EN_MASK 0x8000 + +/* + * When this bit is set MAC/PHY provided speed indications are overridden + * using led_spd_ovrd[2: + * 0]. +*/ +#define XPORT_LED_1_CNTRL_REG_SPD_OVRD_EN_MASK 0x4000 + +/* + * Link status override. + * Used only for LED. +*/ +#define XPORT_LED_1_CNTRL_REG_LNK_STATUS_OVRD_MASK 0x2000 + +/* + * LED speed override. + * Default encoding is: + * 000 : + * 10Mb/s. + * 001 : + * 100Mb/s. + * 010 : + * 1000Mb/s. + * 011 : + * 2. + * 5Gb/s. + * 100 : + * 10Gb/s or higher. + * 101 : + * Custom speed 1. + * 110 : + * Custom speed 2. + * 111 : + * no-link. + * Using this register LED speeds can be encoded in any way that suits + * customer application. +*/ +#define XPORT_LED_1_CNTRL_REG_LED_SPD_OVRD_SHIFT 10 +#define XPORT_LED_1_CNTRL_REG_LED_SPD_OVRD_MASK 0x1c00 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for ACT_LED. +*/ +#define XPORT_LED_1_CNTRL_REG_ACT_LED_POL_SEL_MASK 0x200 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[2]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED2_ACT_POL_SEL_MASK 0x100 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[1]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED1_ACT_POL_SEL_MASK 0x80 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[0]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED0_ACT_POL_SEL_MASK 0x40 + +/* + * Selects source of activity for ACT_LED. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_1_CNTRL_REG_ACT_LED_ACT_SEL_MASK 0x20 + +/* + * Selects source of activity for SPDLNK_LED[2]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED2_ACT_SEL_MASK 0x10 + +/* + * Selects source of activity for SPDLNK_LED[1]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED1_ACT_SEL_MASK 0x8 + +/* + * Selects source of the activity for SPDLNK_LED[0]: + * 0 : + * LED is 0 when link is up and blinks when there is activity. + * 1 : + * LED is 1 and blinks when there is activity. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED0_ACT_SEL_MASK 0x4 + +/* Enables TX_SOP event to contribute to the activity. */ +#define XPORT_LED_1_CNTRL_REG_TX_ACT_EN_MASK 0x2 + +/* Enables RX_SOP event to contribute to the activity. */ +#define XPORT_LED_1_CNTRL_REG_RX_ACT_EN_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_REG_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG 0x80 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Gb/s and higher link speed. + * When SPDLNK_LED_SEL[x] = 1'''b0, SPDLNK_LED[x] is driven by bits [17: + * 0] of Link and Speed Encoding Register. + * When SPDLNK_LED_SEL[x] = 1'''b1, SPDLNK_LED[x] is driven by the + * activity. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_SHIFT 15 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 2500Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_SHIFT 12 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 1000Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_SHIFT 9 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_SHIFT 6 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_SHIFT 3 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_1_LINK_AND_SPEED_ENCODING_REG 0x84 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Gb/s and higherlink speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_SHIFT 15 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 2. + * 5Gb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_SHIFT 12 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 1Gb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_SHIFT 9 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_SHIFT 6 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_SHIFT 3 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_BLINK_RATE_CNTRL_REG 0xd0 + +/* + * Led ON time. + * Expressed in 50us units. +*/ +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_SHIFT 16 +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_MASK 0xffff0000 + +/* + * Led OFF time. + * Expressed in 50us units. +*/ +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_SHIFT 0 +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_LED_SERIAL_CNTRL_REG 0xd4 + +/* + * Indicates number of LED signals per port that are shifted out: + * 11 : + * 4 LEDs per port mode (SPDLNK_LED[2: + * 0] and ACT_LED). + * 10 : + * 3 LEDs per port mode (SPDLNK_LED[2: + * 0]). + * 01 : + * 3 LEDs per port mode (SPDLNK_LED[1: + * 0] and ACT_LED). + * 00 : + * 2 LEDs per port mode (SPDLNK_LED[1: + * 0]) +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_SMODE_SHIFT 23 +#define XPORT_LED_SERIAL_CNTRL_REG_SMODE_MASK 0x1800000 + +/* + * Indicates SLED_CLK frequency. + * 0 : + * SLED_CLK is 6. + * 25Mhz. + * 1 : + * SLED_CLK is 3. + * 125Mhz. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_SLED_CLK_FREQUENCY_MASK 0x400000 + +/* + * When this bit is 1'b1 serial LED clock(SCLK) polarity is inveretd. + * Used with shift registers that trigger on the falling edge. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_SLED_CLK_POL_MASK 0x200000 + +/* + * Serial LED refresh period. + * Expressed in 5ms units. + * Value of 0 means 32x5ms period. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_REFRESH_PERIOD_SHIFT 16 +#define XPORT_LED_SERIAL_CNTRL_REG_REFRESH_PERIOD_MASK 0x1f0000 + +/* + * When the corresponding bit is set, port LEDs are shifted out. + * When all bits are cleared, serial LED interface is disabled. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_PORT_EN_SHIFT 0 +#define XPORT_LED_SERIAL_CNTRL_REG_PORT_EN_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_REFRESH_PERIOD_CNTRL_REG 0xd8 + +/* + * This register is used only in debug purposes. + * It controls REFRESH_PERIOD time unit that is based on 25MHz clock. + * default is 5 ms. +*/ +#define XPORT_REFRESH_PERIOD_CNTRL_REG_REFRESH_PERIOD_CNT_SHIFT 0 +#define XPORT_REFRESH_PERIOD_CNTRL_REG_REFRESH_PERIOD_CNT_MASK 0xffffff + + +/* + * Register + * + */ +#define XPORT_REG_AGGREGATE_LED_CNTRL_REG 0xdc + +/* + * When set to 1'b1 inverts polarity of the link signal that is used for + * aggregate LNK_LED. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_LNK_POL_SEL_MASK 0x40000 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for aggregate ACT_LED. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_ACT_POL_SEL_MASK 0x20000 + +/* + * Selects behavior for aggregate ACT_LED. + * Encoded as: + * 0 : + * LED is 0 when aggregate link is up and blinks when there is activity. + * LED is 1 when aggregate link is down. + * 1 : + * LED is 1 and blinks when there is activity, regardless of the aggregate + * link status. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_ACT_SEL_MASK 0x10000 + +/* + * When the corresponding bit is set, port LEDs are included in aggregate + * LED signals. + * When all bits are cleared, aggregate LED interface is disabled. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_PORT_EN_SHIFT 0 +#define XPORT_AGGREGATE_LED_CNTRL_REG_PORT_EN_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_REG 0xe0 + +/* + * Led ON time. + * Expressed in 50us units. +*/ +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_SHIFT 16 +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_MASK 0xffff0000 + +/* + * Led OFF time. + * Expressed in 50us units. +*/ +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_SHIFT 0 +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_SPARE_CNTRL_REG 0xe4 + +/* + * Spare register. + * Reserved for future use. +*/ +#define XPORT_SPARE_CNTRL_REG_SPARE_REG_SHIFT 0 +#define XPORT_SPARE_CNTRL_REG_SPARE_REG_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_REG_XPORT_CNTRL_1_REG 0x1fc + +/* + * MSBUS clock select. + * 0 : + * 500MHz. + * 1 : + * 644. + * 53125MHz. + * 644. + * 53125MHz clock should be used ONLY when 10G AE and SGMII serdes are + * simultaneously connected to XRDP. +*/ +#define XPORT_CNTRL_1_REG_MSBUS_CLK_SEL_MASK 0x1000 + +/* + * selects port driving WAN LED0 set. + * 0 : + * P0 drives LEDs. + * 1 : + * P1 drives LEDs. +*/ +#define XPORT_CNTRL_1_REG_WAN_LED0_SEL_MASK 0x800 + +/* + * When this bit is set, XPORT internal register bus bridges are not + * automatically reseted/reinitalized when the UBUS slave port times out. +*/ +#define XPORT_CNTRL_1_REG_TIMEOUT_RST_DISABLE_MASK 0x400 + +/* + * P0 Mode: + * 0 : + * P0 operates in GMII mode. + * 1 : + * P0 operates in XGMII mode. +*/ +#define XPORT_CNTRL_1_REG_P0_MODE_MASK 0x100 + + +/* + * Register - read-only + * + */ +#define XPORT_REG_CROSSBAR_STATUS_REG 0x200 + +/* + * When set indicates that full-duplex link is established. + * Half-duplex is not supported and indicates erroneous link. +*/ +#define XPORT_CROSSBAR_STATUS_REG_FULL_DUPLEX_MASK 0x80 + +/* When set indicates that TX PAUSE is negotiated. */ +#define XPORT_CROSSBAR_STATUS_REG_PAUSE_TX_MASK 0x40 + +/* When set indicates that RX PAUSE is negotiated. */ +#define XPORT_CROSSBAR_STATUS_REG_PAUSE_RX_MASK 0x20 + +/* + * When set indicate that link is 2. + * 5Gb. +*/ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_2500_MASK 0x10 + +/* When set indicate that link is 1Gb. */ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_1000_MASK 0x8 + +/* When set indicate that link is 100Mb. */ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_100_MASK 0x4 + +/* When set indicate that link is 10Mb. */ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_10_MASK 0x2 + +/* + * Link Status. + * When 1 indicates that link is up for the selected PHY/RGMII. +*/ +#define XPORT_CROSSBAR_STATUS_REG_LINK_STATUS_MASK 0x1 + + +/* + * Register - read-only + * + */ +#define XPORT_REG_PON_AE_SERDES_STATUS_REG 0x204 + +/* When 0 indicates presence of the optical module. */ +#define XPORT_PON_AE_SERDES_STATUS_REG_MOD_DEF0_MASK 0x40 + +/* + * Non-filtered signal detect (or loss of signal) from the pin as provided + * by the external optical module. + * Please consult used optical module datasheet for polarity. + * NVRAM bit that indicates expected polarity is recommended. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_EXT_SIG_DET_MASK 0x20 + +/* + * PLL1 Lock. + * When 1'b1, indicates that single SERDES PLL1 is locked. + * Only one of PLLs (PLL0 or PLL1) is active at any time, depending on the + * operational mode. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_PLL1_LOCK_MASK 0x10 + +/* + * PLL0 Lock. + * When 1'b1, indicates that single SERDES PLL0 is locked. + * Only one of PLLs (PLL0 or PLL1) is active at any time, depending on the + * operational mode. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_PLL0_LOCK_MASK 0x8 + +/* + * Link Status. + * When 1'b1, indicates that link is up. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_LINK_STATUS_MASK 0x4 + +/* + * CDR Lock. + * When 1'b1, indicates that CDR is locked. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_CDR_LOCK_MASK 0x2 + +/* + * Filtered Rx Signal Detect. + * When 1'b1 indicates presence of the signal on Rx pins. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_RX_SIGDET_MASK 0x1 + + +#endif /* ! WAN_TOPXPORT_REG_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_core.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_core.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_core.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_core.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,2010 @@ +#ifndef WAN_TOPXPORT_XLMAC_CORE_H_ +#define WAN_TOPXPORT_XLMAC_CORE_H_ + +/* relative to core */ +#define XPORT_XLMAC_CORE_OFFSET(x) (0x0 + (x) * 0x400) + +/* + * Register + * + * MAC control. + */ +#define XPORT_XLMAC_CORE_CTRL_REG 0x0 + +/* + * Extended Higig 2 header is also known as sirius header. + * Setting this bit to 0 will disable parsing for the extended header + * bit(5th bit of 8th header byte) in HG2 header and hence all the Higig 2 + * packets will be treated as normal Higig2 packets irrespective of + * extended header bit value. + * Default value of this field is 1 which will enable parsing extended + * header bit in every Higig 2 header. +*/ +#define CTRL_EXTENDED_HIG2_EN_MASK 0x4000 + +/* + * This configuration chooses between link status indication from software + * (SW_LINK_STATUS) or the hardware link status (hw_link_status)indication + * from the TSC. + * If reset, it selects the software link status +*/ +#define CTRL_LINK_STATUS_SELECT_MASK 0x2000 + +/* + * Link status indication from Software. + * If set, indicates that link is active. +*/ +#define CTRL_SW_LINK_STATUS_MASK 0x1000 + +/* + * If set, this will override the one column idle/sequence ordered set + * check before SOP in XGMII mode - effectively supporting reception of + * packets with 1 byte IPG in XGMII mode +*/ +#define CTRL_XGMII_IPG_CHECK_DISABLE_MASK 0x800 + +/* + * Resets the RS layer functionality - Fault detection and related + * responses are disabled and IDLEs are sent on line +*/ +#define CTRL_RS_SOFT_RESET_MASK 0x400 + +/* Reserved */ +#define CTRL_RSVD_5_MASK 0x200 + +/* + * If set, during the local loopback mode, the transmit packets are also + * sent to the transmit line interface, apart from the loopback operation +*/ +#define CTRL_LOCAL_LPBK_LEAK_ENB_MASK 0x100 + +/* Reserved */ +#define CTRL_RSVD_4_MASK 0x80 + +/* + * If set, disables the corresponding port logic and status registers only. + * Packet data and flow control logic is disabled. + * Fault handling is active and the MAC will continue to respond to credits + * from TSC. + * When the soft reset is cleared MAC will issue a fresh set of credits to + * EP in transmit side. +*/ +#define CTRL_SOFT_RESET_MASK 0x40 + +/* + * If set, enable LAG Failover. + * This bit has priority over LOCAL_LPBK. + * The lag failover kicks in when the link status selected by + * LINK_STATUS_SELECT transitions from 1 to 0. + * TSC clock and TSC credits must be active for lag failover. +*/ +#define CTRL_LAG_FAILOVER_EN_MASK 0x20 + +/* + * If set, XLMAC will move from lag failover state to normal operation. + * This bit should be set after link is up. +*/ +#define CTRL_REMOVE_FAILOVER_LPBK_MASK 0x10 + +/* Reserved */ +#define CTRL_RSVD_1_MASK 0x8 + +/* + * If set, enables local loopback from TX to RX. + * This loopback is on the line side after clock domain crossing - from the + * last TX pipeline stage to the first RX pipeline stage. + * Hence, TSC clock and TSC credits must be active for loopback. + * LAG_FAILOVER_EN should be disabled for this bit to work. +*/ +#define CTRL_LOCAL_LPBK_MASK 0x4 + +/* If set, enables MAC receive datapath and flowcontrol logic. */ +#define CTRL_RX_EN_MASK 0x2 + +/* + * If set, enables MAC transmit datapath and flowcontrol logic. + * When disabled, MAC will respond to TSC credits with IDLE codewords. +*/ +#define CTRL_TX_EN_MASK 0x1 + + +/* + * Register + * + * XLMAC Mode register + */ +#define XPORT_XLMAC_CORE_MODE_REG 0x8 + +/* Port Speed, used for LED indications and internal buffer sizing. */ +#define MODE_SPEED_MODE_SHIFT 4 +#define MODE_SPEED_MODE_MASK 0x70 + +/* If set, excludes the SOP byte for CRC calculation in HIGIG modes */ +#define MODE_NO_SOP_FOR_CRC_HG_MASK 0x8 + +/* Packet Header mode. */ +#define MODE_HDR_MODE_SHIFT 0 +#define MODE_HDR_MODE_MASK 0x7 + + +/* + * Register + * + * Spare reg 0 for ECO + */ +#define XPORT_XLMAC_CORE_SPARE0_REG 0x10 + +/* SPARE REGISTER 0 */ +#define SPARE0_RSVD_SHIFT 0 +#define SPARE0_RSVD_MASK 0xffffffff + + +/* + * Register + * + * Spare reg 1 for ECO + */ +#define XPORT_XLMAC_CORE_SPARE1_REG 0x18 + +/* SPARE REGISTER 1 */ +#define SPARE1_RSVD_SHIFT 0 +#define SPARE1_RSVD_MASK 0x3 + + +/* + * Register + * + * Transmit control. + * This XLMAC core register is 42 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_TX_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_TX_CTRL_REG 0x20 + +/* + * Indicates the number of 16-byte cells that are buffered per packet in + * the Tx CDC FIFO, before starting transmission of the packet on the line + * side. + * This setting is useful to prevent underflow issues if the EP logic pumps + * in data at port rate, rather than bursting at full rate. + * This mode will increase the overall latency. + * In quad port mode, this field should be set >= 1 and <= 4 for each port. + * In single port mode, this field should be set >= 1 and <= 16 for the + * four lane port (port0). + * In dual port mode, this field should be set >= 1 and <= 8 for each two + * lane port (port0 and port2). + * In tri1/tri2, this field should be set >= 1 and <= 4 for each single + * lane port, and >= 1 and <= 8 for the two lane port. +*/ +#define TX_CTRL_TX_THRESHOLD_SHIFT 38 +#define TX_CTRL_TX_THRESHOLD_MASK 0x3c000000000 + +/* + * If set, MAC accepts packets from the EP but does not write to the CDC + * FIFO and discards them on the core side without updating the statistics. +*/ +#define TX_CTRL_EP_DISCARD_MASK 0x2000000000 + +/* + * Number of preamble bytes for transmit IEEE packets, this value should + * include the K. + * SOP & SFD character as well +*/ +#define TX_CTRL_TX_PREAMBLE_LENGTH_SHIFT 33 +#define TX_CTRL_TX_PREAMBLE_LENGTH_MASK 0x1e00000000 + +/* + * Number of bytes to transmit before adding THROT_NUM bytes to the IPG. + * This configuration is used for WAN IPG throttling. + * Refer MAC specs for more details. +*/ +#define TX_CTRL_THROT_DENOM_SHIFT 25 +#define TX_CTRL_THROT_DENOM_MASK 0x1fe000000 + +/* + * Number of bytes of extra IPG added whenever THROT_DENOM bytes have been + * transmitted. + * This configuration is used for WAN IPG throttling. + * Refer MAC specs for more details. +*/ +#define TX_CTRL_THROT_NUM_SHIFT 19 +#define TX_CTRL_THROT_NUM_MASK 0x1f80000 + +/* + * Average interpacket gap. + * Must be programmed >= 8. + * Per packet IPG will vary based on DIC for 10G+ speeds. +*/ +#define TX_CTRL_AVERAGE_IPG_SHIFT 12 +#define TX_CTRL_AVERAGE_IPG_MASK 0x7f000 + +/* + * If padding is enabled, packets smaller than PAD_THRESHOLD are padded to + * this size. + * This must be set to a value >= 17 (decimal) +*/ +#define TX_CTRL_PAD_THRESHOLD_SHIFT 5 +#define TX_CTRL_PAD_THRESHOLD_MASK 0xfe0 + +/* If set, enable XLMAC to pad packets smaller than PAD_THRESHOLD on the Tx */ +#define TX_CTRL_PAD_EN_MASK 0x10 + +/* + * If reset, MAC forces the first byte of a packet to be /S/ character + * (0xFB) irrespective of incoming EP data at SOP location in HIGIG modes +*/ +#define TX_CTRL_TX_ANY_START_MASK 0x8 + +/* + * If set, MAC accepts packets from the EP and discards them on the line + * side. + * The statistics are updated. +*/ +#define TX_CTRL_DISCARD_MASK 0x4 + +/* CRC mode for Transmit Side */ +#define TX_CTRL_CRC_MODE_SHIFT 0 +#define TX_CTRL_CRC_MODE_MASK 0x3 + + +/* + * Register + * + * Transmit Source Address. + * This XLMAC core register is 48 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_MAC_SA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_TX_MAC_SA_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_TX_MAC_SA_REG 0x28 + +/* Source Address for PAUSE/PFC packets generated by the MAC */ +#define TX_MAC_SA_CTRL_SA_SHIFT 0 +#define TX_MAC_SA_CTRL_SA_MASK 0xffffffffffff + + +/* + * Register + * + * Receive control. + */ +#define XPORT_XLMAC_CORE_RX_CTRL_REG 0x30 + +/* + * This configuration is used to pass or drop pfc packetw when + * pfc_ether_type is not equal to 0x8808. + * If set, PFC frames are passed to system side. + * Otherwise, PFC frames are dropped in XLMAC. + * This configuration is used in Rx CDC mode only. +*/ +#define RX_CTRL_RX_PASS_PFC_MASK 0x8000 + +/* + * If set, PAUSE frames are passed to sytem side. + * Otherwise, PAUSE frames are dropped in XLMAC This configuration is used + * in Rx CDC mode only. +*/ +#define RX_CTRL_RX_PASS_PAUSE_MASK 0x4000 + +/* + * This configuration is used to drop or pass all control frames (with + * ether type 0x8808) except pause packets. + * If set, all control frames are passed to system side. + * Otherwise, control frames (including pfc frames wih ether type 0x8808) + * are dropped in XLMAC. + * This configuration is used in Rx CDC mode only. +*/ +#define RX_CTRL_RX_PASS_CTRL_MASK 0x2000 + +/* Reserved */ +#define RX_CTRL_RSVD_3_MASK 0x1000 + +/* Reserved */ +#define RX_CTRL_RSVD_2_MASK 0x800 + +/* + * The runt threshold, below which the packets are dropped (CDC mode) or + * marked as runt (Low latency mode). + * Should be programmed < 96 bytes (decimal) +*/ +#define RX_CTRL_RUNT_THRESHOLD_SHIFT 4 +#define RX_CTRL_RUNT_THRESHOLD_MASK 0x7f0 + +/* + * If set, MAC checks for IEEE Ethernet preamble - K. + * SOP + 6 "0x55" preamble bytes + "0xD5" SFD character - if this sequence + * is missing it is treated as an errored packet +*/ +#define RX_CTRL_STRICT_PREAMBLE_MASK 0x8 + +/* If set, CRC is stripped from the received packet */ +#define RX_CTRL_STRIP_CRC_MASK 0x4 + +/* If set, MAC allows any undefined control character to start a packet */ +#define RX_CTRL_RX_ANY_START_MASK 0x2 + +/* Reserved */ +#define RX_CTRL_RSVD_1_MASK 0x1 + + +/* + * Register + * + * Receive source address. + * This XLMAC core register is 48 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_RX_MAC_SA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_RX_MAC_SA_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_RX_MAC_SA_REG 0x38 + +/* + * Source Address recognized for MAC control packets in addition to the + * standard 0x0180C2000001 +*/ +#define RX_MAC_SA_RX_SA_SHIFT 0 +#define RX_MAC_SA_RX_SA_MASK 0xffffffffffff + + +/* + * Register + * + * Receive maximum packet size. + */ +#define XPORT_XLMAC_CORE_RX_MAX_SIZE_REG 0x40 + +/* + * Maximum packet size in receive direction, exclusive of preamble & CRC in + * strip mode. + * Packets greater than this size are truncated to this value. +*/ +#define RX_MAX_SIZE_RX_MAX_SIZE_SHIFT 0 +#define RX_MAX_SIZE_RX_MAX_SIZE_MASK 0x3fff + + +/* + * Register + * + * Inner and Outer VLAN tag fields This XLMAC core register is 34 bits wide + * in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_RX_VLAN_TAG) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + */ +#define XPORT_XLMAC_CORE_RX_VLAN_TAG_REG 0x48 + +/* If set, MAC enables VLAN tag detection using the OUTER_VLAN_TAG */ +#define RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_MASK 0x200000000 + +/* If set, MAC enables VLAN tag detection using the INNER_VLAN_TAG */ +#define RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_MASK 0x100000000 + +/* TPID field for Outer VLAN tag */ +#define RX_VLAN_TAG_OUTER_VLAN_TAG_SHIFT 16 +#define RX_VLAN_TAG_OUTER_VLAN_TAG_MASK 0xffff0000 + +/* TPID field for Inner VLAN tag */ +#define RX_VLAN_TAG_INNER_VLAN_TAG_SHIFT 0 +#define RX_VLAN_TAG_INNER_VLAN_TAG_MASK 0xffff + + +/* + * Register + * + * Control for LSS (ordered set) messages + */ +#define XPORT_XLMAC_CORE_RX_LSS_CTRL_REG 0x50 + +/* + * If set, the Receive Pause, PFC & LLFC timers are reset whenever the link + * status is down, or local or remote faults are received. +*/ +#define RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_MASK 0x80 + +/* + * This bit determines the way MAC handles data during link interruption + * state, if LINK_INTERRUPTION_DISABLE is reset. + * If set, during link interruption state, MAC drops transmit-data + * (statistics are updated) and sends IDLEs on the wire. + * If reset, transmit data is stalled in the internal FIFO under link + * interruption state. +*/ +#define RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_MASK 0x40 + +/* + * This bit determines the way MAC handles data during remote fault state, + * if REMOTE_FAULT_DISABLE is reset. + * If set, during remote fault state, MAC drops transmit-data (statistics + * are updated) and sends IDLEs on the wire. + * If reset, transmit data is stalled in the internal FIFO under remote + * fault state. +*/ +#define RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_MASK 0x20 + +/* + * This bit determines the way MAC handles data during local fault state, + * if LOCAL_FAULT_DISABLE is reset. + * If set, during local fault state, MAC drops transmit-data (statistics + * are updated) and sends remote faults on the wire. + * If reset, transmit data is stalled in the internal FIFO under local + * fault state. +*/ +#define RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_MASK 0x10 + +/* + * This bit determines the transmit response during link interruption + * state. + * The LINK_INTERRUPTION_STATUS bit is always updated irrespective of this + * configuration. + * If set, MAC will continue to transmit data irrespective of + * LINK_INTERRUPTION_STATUS. + * If reset, MAC transmit behavior is governed by + * DROP_TX_DATA_ON_LINK_INTERRUPT configuration. +*/ +#define RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_MASK 0x8 + +/* + * If set, the transmit fault responses are determined from input pins + * rather than internal receive status. + * In this mode, input fault from pins (from a peer MAC) is directly + * relayed on the transmit side of this MAC. + * See specification document for more details. +*/ +#define RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_MASK 0x4 + +/* + * This bit determines the transmit response during remote fault state. + * The REMOTE_FAULT_STATUS bit is always updated irrespective of this + * configuration. + * If set, MAC will continue to transmit data irrespective of + * REMOTE_FAULT_STATUS. + * If reset, MAC transmit behavior is governed by + * DROP_TX_DATA_ON_REMOTE_FAULT configuration. +*/ +#define RX_LSS_CTRL_REMOTE_FAULT_DISABLE_MASK 0x2 + +/* + * This bit determines the transmit response during local fault state. + * The LOCAL_FAULT_STATUS bit is always updated irrespective of this + * configuration. + * If set, MAC will continue to transmit data irrespective of + * LOCAL_FAULT_STATUS. + * If reset, MAC transmit behavior is governed by + * DROP_TX_DATA_ON_LOCAL_FAULT configuration. +*/ +#define RX_LSS_CTRL_LOCAL_FAULT_DISABLE_MASK 0x1 + + +/* + * Register - read-only + * + * Status for RS layer. + * These bits are sticky by nature, and can be cleared by writing to the + * clear register + */ +#define XPORT_XLMAC_CORE_RX_LSS_STATUS_REG 0x58 + +/* + * True when link interruption state is detected as per RS layer state + * machine. + * Sticky bit is cleared by CLEAR_LINK_INTERRUPTION_STATUS. +*/ +#define RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_MASK 0x4 + +/* + * True when remote fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_REMOTE_FAULT_STATUS. +*/ +#define RX_LSS_STATUS_REMOTE_FAULT_STATUS_MASK 0x2 + +/* + * True when local fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_LOCAL_FAULT_STATUS +*/ +#define RX_LSS_STATUS_LOCAL_FAULT_STATUS_MASK 0x1 + + +/* + * Register + * + * Clear the XLMAC_RX_LSS_STATUS register, used for resetting the sticky + * status bits + */ +#define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_REG 0x60 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * LINK_INTERRUPTION_STATUS bit +*/ +#define CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_MASK 0x4 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * REMOTE_FAULT_STATUS bit +*/ +#define CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_MASK 0x2 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * LOCAL_FAULT_STATUS bit +*/ +#define CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_MASK 0x1 + + +/* + * Register + * + * PAUSE control register This XLMAC core register is 37 bits wide in + * hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_PAUSE_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_PAUSE_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_PAUSE_CTRL_REG 0x68 + +/* + * Pause time value sent in the timer field for XOFF state (unit is 512 + * bit-times) +*/ +#define PAUSE_CTRL_PAUSE_XOFF_TIMER_SHIFT 21 +#define PAUSE_CTRL_PAUSE_XOFF_TIMER_MASK 0x1fffe00000 + +/* Reserved */ +#define PAUSE_CTRL_RSVD_2_MASK 0x100000 + +/* Reserved */ +#define PAUSE_CTRL_RSVD_1_MASK 0x80000 + +/* + * When set, enables detection of pause frames in the receive direction and + * pause/resume the transmit data path +*/ +#define PAUSE_CTRL_RX_PAUSE_EN_MASK 0x40000 + +/* + * When set, enables the transmission of pause frames whenever there is a + * transition on txbkp input to MAC from MMU +*/ +#define PAUSE_CTRL_TX_PAUSE_EN_MASK 0x20000 + +/* + * When set, enables the periodic re-generation of XOFF pause frames based + * on the interval specified in PAUSE_REFRESH_TIMER +*/ +#define PAUSE_CTRL_PAUSE_REFRESH_EN_MASK 0x10000 + +/* + * This field specifies the interval at which pause frames are re-generated + * during XOFF state, provided PAUSE_REFRESH_EN is set (unit is 512 + * bit-times) +*/ +#define PAUSE_CTRL_PAUSE_REFRESH_TIMER_SHIFT 0 +#define PAUSE_CTRL_PAUSE_REFRESH_TIMER_MASK 0xffff + + +/* + * Register + * + * PFC control register This XLMAC core register is 38 bits wide in + * hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_PFC_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_PFC_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_PFC_CTRL_REG 0x70 + +/* When set, enables the transmission of PFC frames */ +#define PFC_CTRL_TX_PFC_EN_MASK 0x2000000000 + +/* + * When set, enables detection of PFC frames in the receive direction and + * generation of COSMAPs to MMU based on incoming timer values +*/ +#define PFC_CTRL_RX_PFC_EN_MASK 0x1000000000 + +/* + * When set, enables the generation of receive and transmit PFC events into + * the corresponding statistics vectors (RSV and TSV) +*/ +#define PFC_CTRL_PFC_STATS_EN_MASK 0x800000000 + +/* Reserved */ +#define PFC_CTRL_RSVD_MASK 0x400000000 + +/* + * When set, forces the MAC to generate an XON indication to the MMU for + * all classes of service in the receive direction +*/ +#define PFC_CTRL_FORCE_PFC_XON_MASK 0x200000000 + +/* + * When set, enables the periodic re-generation of PFC frames based on the + * interval specified in PFC_REFRESH_TIMER +*/ +#define PFC_CTRL_PFC_REFRESH_EN_MASK 0x100000000 + +/* + * Pause time value sent in the timer field for classes in XOFF state (unit + * is 512 bit-times) +*/ +#define PFC_CTRL_PFC_XOFF_TIMER_SHIFT 16 +#define PFC_CTRL_PFC_XOFF_TIMER_MASK 0xffff0000 + +/* + * This field specifies the interval at which PFC frames are re-generated + * for a class of service in XOFF state, provided PFC_REFRESH_EN is set + * (unit is 512 bit-times) +*/ +#define PFC_CTRL_PFC_REFRESH_TIMER_SHIFT 0 +#define PFC_CTRL_PFC_REFRESH_TIMER_MASK 0xffff + + +/* + * Register + * + * PFC Ethertype + */ +#define XPORT_XLMAC_CORE_PFC_TYPE_REG 0x78 + +/* + * This field is used in the ETHERTYPE field of the PFC frame that is + * generated and transmitted by the MAC and also used for detection in the + * receive direction +*/ +#define PFC_TYPE_PFC_ETH_TYPE_SHIFT 0 +#define PFC_TYPE_PFC_ETH_TYPE_MASK 0xffff + + +/* + * Register + * + * PFC Opcode + */ +#define XPORT_XLMAC_CORE_PFC_OPCODE_REG 0x80 + +/* + * This field is used in the OPCODE field of the PFC frame that is + * generated and transmitted by the MAC and also used for detection in the + * receive direction +*/ +#define PFC_OPCODE_PFC_OPCODE_SHIFT 0 +#define PFC_OPCODE_PFC_OPCODE_MASK 0xffff + + +/* + * Register + * + * PFC Destination Address. + * This XLMAC core register is 48 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_PFC_DA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_PFC_DA_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_PFC_DA_REG 0x88 + +/* + * This field is used in the destination-address field of the PFC frame + * that is generated and transmitted by the MAC and also used for detection + * in the receive direction +*/ +#define PFC_DA_PFC_MACDA_SHIFT 0 +#define PFC_DA_PFC_MACDA_MASK 0xffffffffffff + + +/* + * Register + * + * LLFC Control Register + */ +#define XPORT_XLMAC_CORE_LLFC_CTRL_REG 0x90 + +/* + * This field indicates the minimum Inter Message Gap that is enforced by + * the MAC between 2 LLFC messages in the transmit direction (unit is 1 + * credit) +*/ +#define LLFC_CTRL_LLFC_IMG_SHIFT 6 +#define LLFC_CTRL_LLFC_IMG_MASK 0x3fc0 + +/* When set, LLFC CRC computation does not include the SOM character */ +#define LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_MASK 0x20 + +/* + * When set, disables the CRC check for LLFC messages in the receive + * direction +*/ +#define LLFC_CTRL_LLFC_CRC_IGNORE_MASK 0x10 + +/* + * When LLFC_IN_IPG_ONLY is reset, the mode of transmission of LLFC + * messages is controlled by this bit depending upon whether the LLFC + * message is XON or XOFF When LLFC_CUT_THROUGH_MODE is reset, all LLFC + * messages are transmitted pre-emptively (within a packet) When + * LLFC_CUT_THROUGH_MODE is set, only XOFF LLFC messages are transmitted + * pre-emptively, XON LLFC messages are transmitted during IPG +*/ +#define LLFC_CTRL_LLFC_CUT_THROUGH_MODE_MASK 0x8 + +/* + * When set, all LLFC messages are transmitted during IPG When reset, the + * mode of insertion of LLFC messages is controlled by + * LLFC_CUT_THROUGH_MODE +*/ +#define LLFC_CTRL_LLFC_IN_IPG_ONLY_MASK 0x4 + +/* + * When set, enables processing of LLFC frames in the receive direction and + * generation of COSMAPs to MMU +*/ +#define LLFC_CTRL_RX_LLFC_EN_MASK 0x2 + +/* + * When set, enables the generation and transmission of LLFC frames in the + * transmit direction +*/ +#define LLFC_CTRL_TX_LLFC_EN_MASK 0x1 + + +/* + * Register + * + * Programmable TX LLFC Message fields. + */ +#define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_REG 0x98 + +/* + * Pause time value sent in the XOFF_TIME field of the outgoing LLFC + * message +*/ +#define TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_SHIFT 12 +#define TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_MASK 0xffff000 + +/* + * This field is used in the FC_OBJ_LOGICAL field of the outgoing LLFC + * message +*/ +#define TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_SHIFT 8 +#define TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_MASK 0xf00 + +/* + * This field is used in the MSG_TYPE_LOGICAL field of the outgoing LLFC + * message +*/ +#define TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_SHIFT 0 +#define TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_MASK 0xff + + +/* + * Register + * + * Programmable RX LLFC Message fields + */ +#define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_REG 0xa0 + +/* + * This value is compared against the FC_OBJ_PHYSICAL field of an incoming + * LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_SHIFT 20 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_MASK 0xf00000 + +/* + * This value is compared against the MSG_TYPE_PHYSICAL field of an + * incoming LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_SHIFT 12 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_MASK 0xff000 + +/* + * This value is compared against the FC_OBJ_LOGICAL field of an incoming + * LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_SHIFT 8 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_MASK 0xf00 + +/* + * This value is compared against the MSG_TYPE_LOGICAL field of an incoming + * LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_SHIFT 0 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_MASK 0xff + + +/* + * Register - read-only + * + * The TimeStamp value of the Tx two-step packets. + * This XLMAC core register is 49 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_TIMESTAMP_FIFO_DATA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + */ +#define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_REG 0xa8 + +/* Active high qualifier for the TimeStamp & SEQUENCE_ID fields. */ +#define TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_MASK 0x1000000000000 + +/* + * The Sequence Identifier extracted from the Timesync packet based on the + * header offset +*/ +#define TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_SHIFT 32 +#define TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_MASK 0xffff00000000 + +/* The TimeStamp value of the Tx two-step enabled packet. */ +#define TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_SHIFT 0 +#define TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_MASK 0xffffffff + + +/* + * Register - read-only + * + * Tx TimeStamp FIFO Status. + */ +#define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_REG 0xb0 + +/* + * Number of TX time stamps currently buffered in TX Time Stamp FIFO. + * A valid entry is popped out whenever XLMAC_TX_TIMESTMAP_FIFO_DATA is + * read +*/ +#define TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_SHIFT 0 +#define TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_MASK 0x7 + + +/* + * Register - read-only + * + * FIFO status register. + * These bits (except LINK_STATUS) are sticky by nature, and can be cleared + * by writing to the clear register. + */ +#define XPORT_XLMAC_CORE_FIFO_STATUS_REG 0xb8 + +/* + * This bit indicates the link status used by XLMAC EEE and lag-failover + * state machines. + * This reflects the live status of the link as seen by the MAC. + * If set, indicates that link is active. +*/ +#define FIFO_STATUS_LINK_STATUS_MASK 0x100 + +/* If set, indicates RX packet fifo overflow */ +#define FIFO_STATUS_RX_PKT_OVERFLOW_MASK 0x80 + +/* If set, indicates overflow occurred in TX two-step Time Stamp FIFO */ +#define FIFO_STATUS_TX_TS_FIFO_OVERFLOW_MASK 0x40 + +/* If set, indicates TX LLFC message fifo overflow */ +#define FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_MASK 0x20 + +/* Reserved */ +#define FIFO_STATUS_RSVD_2_MASK 0x10 + +/* If set, indicates tx packet fifo overflow */ +#define FIFO_STATUS_TX_PKT_OVERFLOW_MASK 0x8 + +/* If set, indicates tx packet fifo underflow */ +#define FIFO_STATUS_TX_PKT_UNDERFLOW_MASK 0x4 + +/* If set, indicates rx message fifo overflow */ +#define FIFO_STATUS_RX_MSG_OVERFLOW_MASK 0x2 + +/* Reserved */ +#define FIFO_STATUS_RSVD_1_MASK 0x1 + + +/* + * Register + * + * Clear XLMAC_FIFO_STATUS register, used for resetting the sticky status + * bits + */ +#define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_REG 0xc0 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_PKT_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_MASK 0x80 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_TS_FIFO_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_MASK 0x40 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_LLFC_MSG_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_MASK 0x20 + +/* Reserved */ +#define CLEAR_FIFO_STATUS_RSVD_2_MASK 0x10 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_PKT_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_MASK 0x8 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_PKT_UNDERFLOW status bit +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_MASK 0x4 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_MSG_OVERFLOW status bit +*/ +#define CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_MASK 0x2 + +/* Reserved */ +#define CLEAR_FIFO_STATUS_RSVD_1_MASK 0x1 + + +/* + * Register - read-only + * + * Lag Failover Status. + */ +#define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_REG 0xc8 + +/* Reserved */ +#define LAG_FAILOVER_STATUS_RSVD_MASK 0x2 + +/* Set when XLMAC is in lag failover state */ +#define LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_MASK 0x1 + + +/* + * Register + * + * Register for EEE Control + */ +#define XPORT_XLMAC_CORE_EEE_CTRL_REG 0xd0 + +/* Reserved */ +#define EEE_CTRL_RSVD_MASK 0x2 + +/* + * When set, enables EEE state machine in the transmit direction and LPI + * detection/prediction in the receive direction +*/ +#define EEE_CTRL_EEE_EN_MASK 0x1 + + +/* + * Register + * + * EEE Timers This XLMAC core register is 64 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_EEE_TIMERS) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_EEE_TIMERS_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_EEE_TIMERS_REG 0xd8 + +/* + * This field controls clock divider used to generate ~1us reference pulses + * used by EEE timers. + * It specifies integer number of clock cycles for 1us reference using + * tsc_clk +*/ +#define EEE_TIMERS_EEE_REF_COUNT_SHIFT 48 +#define EEE_TIMERS_EEE_REF_COUNT_MASK 0xffff000000000000 + +/* + * This is the duration for which MAC must wait to go back to ACTIVE state + * from LPI state when it receives packet/flow-control frames for + * transmission. + * Unit is micro seconds +*/ +#define EEE_TIMERS_EEE_WAKE_TIMER_SHIFT 32 +#define EEE_TIMERS_EEE_WAKE_TIMER_MASK 0xffff00000000 + +/* + * This is the duration for which the MAC must wait in EMPTY state before + * transitioning to LPI state. + * Unit is micro seconds +*/ +#define EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_SHIFT 0 +#define EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_MASK 0xffffffff + + +/* + * Register + * + * EEE One Second Link Status Timer + */ +#define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_REG 0xe0 + +/* + * This is the duration for which EEE FSM must wait when Link status + * becomes active before transitioning to ACTIVE state. + * Unit is micro seconds +*/ +#define EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_SHIFT 0 +#define EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_MASK 0xffffff + + +/* + * Register + * + * HiGig2 and HiHig+ header register - MS bytes This XLMAC core register is + * 64 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_HIGIG_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_HIGIG_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_HIGIG_HDR_0_REG 0xe8 + +/* + * In HiGig2 mode, this register contains bits 127: + * 64 of 16-byte HiGig2 header. + * In HiGig+ mode, bits 31: + * 0 of this register contains bits 95: + * 64 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * pause and PFC frames in the transmit direction. +*/ +#define HIGIG_HDR_0_HIGIG_HDR_0_SHIFT 0 +#define HIGIG_HDR_0_HIGIG_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * HiGig2 and HiHig+ header register - LS bytes This XLMAC core register is + * 64 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_HIGIG_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_HIGIG_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_HIGIG_HDR_1_REG 0xf0 + +/* + * In HiGig2 mode, this register contains bits 63: + * 0 of 16-byte HiGig2 header. + * In HiGig+ mode, this register contains bits 63: + * 0 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * pause and PFC frames in the transmit direction. +*/ +#define HIGIG_HDR_1_HIGIG_HDR_1_SHIFT 0 +#define HIGIG_HDR_1_HIGIG_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * MAC EEE control in GMII mode. + */ +#define XPORT_XLMAC_CORE_GMII_EEE_CTRL_REG 0xf8 + +/* When set, enables LPI prediction */ +#define GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_MASK 0x10000 + +/* + * If GMII_LPI_PREDICT_MODE_EN is set then this field defines the number of + * IDLEs to be received before allowing LPIs to be sent to Link Partner +*/ +#define GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_SHIFT 0 +#define GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_MASK 0xffff + + +/* + * Register + * + * Timestamp Adjust register. + * Refer specification document for more details + */ +#define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_REG 0x100 + +/* + * When set, indicates that the checksum offset is referenced by input port + * checksumoffset, else checksum offset is referenced by txtsoffset +*/ +#define TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_MASK 0x8000 + +/* + * This is an unsigned value to account for synchronization delay of TS + * timer from TS clk to TSC_CLK domain. + * Unit is 1ns. + * The latency is [2. + * 5 TSC_CLK period + 1 TS_CLK period]. +*/ +#define TIMESTAMP_ADJUST_TS_TSTS_ADJUST_SHIFT 9 +#define TIMESTAMP_ADJUST_TS_TSTS_ADJUST_MASK 0x7e00 + +/* + * This is a signed value which is 2s complement added to synchronized + * timestamp to account for MAC pipeline delay in OSTS. + * Unit is 1ns The latency is [6 TSC_CLK period + 1 TS_CLK period ]. +*/ +#define TIMESTAMP_ADJUST_TS_OSTS_ADJUST_SHIFT 0 +#define TIMESTAMP_ADJUST_TS_OSTS_ADJUST_MASK 0x1ff + + +/* + * Register + * + * Timestamp Byte Adjust register. + * Refer specification document for more details + */ +#define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_REG 0x108 + +/* + * When set, enables byte based adjustment for receive timestamp capture. + * This should be enabled in GMII/MII modes only. +*/ +#define TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_MASK 0x200000 + +/* + * This is a per byte unsigned value which is subtracted from sampled + * timestamp to account for timestamp jitter due to wider MSBUS interface. + * Unit is 1ns +*/ +#define TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_SHIFT 11 +#define TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_MASK 0x1ff800 + +/* + * When set, enables byte based adjustment for transmit timestamp capture + * (OSTS and TSTS). + * This should be enabled in GMII/MII modes only. +*/ +#define TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_MASK 0x400 + +/* + * This is a per byte unsigned value which is added to sampled timestamp to + * account for timestamp jitter due to wider MSBUS interface. + * Unit is 1ns +*/ +#define TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_SHIFT 0 +#define TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_MASK 0x3ff + + +/* + * Register + * + * Tx CRC corrupt control register This XLMAC core register is 35 bits wide + * in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_CRC_CORRUPT_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_REG 0x110 + +/* + * Programmable CRC value used to corrupt the Tx CRC. + * The computed CRC is replaced by this programmed CRC value based on + * TX_CRC_CORRUPTION_MODE +*/ +#define TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_SHIFT 3 +#define TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_MASK 0x7fffffff8 + +/* + * When set, the computed CRC is replaced with PROG_TX_CRC, else computed + * CRC is inverted +*/ +#define TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_MASK 0x4 + +/* + * When set, MAC enables the CRC corruption on the transmitted packets. + * Mode of corruption is determined by TX_CRC_CORRUPTION_MODE +*/ +#define TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_MASK 0x2 + +/* + * When set, this bit causes packets with TXERR to corrupt the CRC of the + * packet when it is transmitted. + * When reset, packets with TXERR are transmitted with /E/ termination + * character (/T/ is not enforced); packet CRC is unaffected +*/ +#define TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_MASK 0x1 + + +/* + * Register + * + * Transmit E2EFC/E2ECC control register + */ +#define XPORT_XLMAC_CORE_E2E_CTRL_REG 0x118 + +/* + * When set, dual modid is enabled for E2EFC (Only 32 ports IBP is sent + * out). + * When reset, single modid is enabled for E2EFC (64 ports IBP is sent) +*/ +#define E2E_CTRL_E2EFC_DUAL_MODID_EN_MASK 0x10 + +/* + * When set, legacy E2ECC stage2 loading enabled (single stage2 buffer for + * all ports). + * When reset, new E2ECC stage2 loading enabled (per port stage2 buffer) +*/ +#define E2E_CTRL_E2ECC_LEGACY_IMP_EN_MASK 0x8 + +/* + * When set, dual modid is enabled for E2ECC. + * When reset, single modid is enabled for E2ECC +*/ +#define E2E_CTRL_E2ECC_DUAL_MODID_EN_MASK 0x4 + +/* + * When set, E2ECC/FC frames are not transmitted during pause state. + * When reset, E2ECC/FC frames are transmitted even during pause state + * similar to other flow control frames. +*/ +#define E2E_CTRL_HONOR_PAUSE_FOR_E2E_MASK 0x2 + +/* When set, MAC enables E2EFC/E2ECC frame generation and transmission. */ +#define E2E_CTRL_E2E_ENABLE_MASK 0x1 + + +/* + * Register + * + * E2ECC module header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_MODULE_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_REG 0x120 + +/* + * In HiGig2 mode, this register contains bits 127: + * 64 of 16-byte HiGig2 header. + * In HiGig+ mode, this register contains bits 95: + * 32 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2ECC frames in the transmit direction. +*/ +#define E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_SHIFT 0 +#define E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2ECC module header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_MODULE_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_REG 0x128 + +/* + * In HiGig2 mode, this register contains bits 63: + * 0 of 16-byte HiGig2 header. + * In HiGig+ mode, bits 63: + * 32 of this register contains bits 31: + * 0 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2ECC frames in the transmit direction. +*/ +#define E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_SHIFT 0 +#define E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2ECC Ethernet header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_DATA_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_DATA_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_REG 0x130 + +/* + * This register contains bits 127: + * 64 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2ECC frames in the transmit direction. +*/ +#define E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_SHIFT 0 +#define E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2ECC Ethernet header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_DATA_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_DATA_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_REG 0x138 + +/* + * This register contains bits 63: + * 0 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2ECC frames in the transmit direction. +*/ +#define E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_SHIFT 0 +#define E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC module header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_MODULE_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_REG 0x140 + +/* + * In HiGig2 mode, this register contains bits 127: + * 64 of 16-byte HiGig2 header. + * In HiGig+ mode, this register contains bits 95: + * 32 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2EFC frames in the transmit direction. +*/ +#define E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_SHIFT 0 +#define E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC module header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_MODULE_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_REG 0x148 + +/* + * In HiGig2 mode, this register contains bits 63: + * 0 of 16-byte HiGig2 header. + * In HiGig+ mode, bits 63: + * 32 of this register contains bits 31: + * 0 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2EFC frames in the transmit direction. +*/ +#define E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_SHIFT 0 +#define E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC Ethernet header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_DATA_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_DATA_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_REG 0x150 + +/* + * This register contains bits 127: + * 64 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2EFC frames in the transmit direction. +*/ +#define E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_SHIFT 0 +#define E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC Ethernet header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_DATA_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_DATA_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_REG 0x158 + +/* + * This register contains bits 63: + * 0 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2EFC frames in the transmit direction. +*/ +#define E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_SHIFT 0 +#define E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register - read-only + * + * XLMAC TX FIFO Cell Count register + */ +#define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_REG 0x160 + +/* + * Number of cell counts in XLMAC TX FIFO. + * Should range from 0 to 32 for XLMAC core in single port mode, or 0 to 16 + * if XLMAC core is in dual port mode, or 0 to 8 if XLMAC core is in quad + * port mode during traffic. + * This should reset to 0 after the traffic has stopped for all port modes. +*/ +#define TXFIFO_CELL_CNT_CELL_CNT_SHIFT 0 +#define TXFIFO_CELL_CNT_CELL_CNT_MASK 0x3f + + +/* + * Register - read-only + * + * XLMAC TX FIFO Cell Request Count Register + */ +#define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REG 0x168 + +/* + * Number of cell requests made to Egress Pipeline. + * Should range from 0 to 32 for XLMAC core in single port mode, or 0 to 16 + * if XLMAC core is in dual port mode, or 0 to 8 if XLMAC core is in quad + * port mode during traffic. + * This should saturate at the maximum value for the corresponding port + * mode after traffic has stopped. +*/ +#define TXFIFO_CELL_REQ_CNT_REQ_CNT_SHIFT 0 +#define TXFIFO_CELL_REQ_CNT_REQ_CNT_MASK 0x3f + + +/* + * Register + * + * Memory Control register + */ +#define XPORT_XLMAC_CORE_MEM_CTRL_REG 0x170 + +/* Test mode configuration of Tx CDC Memory */ +#define MEM_CTRL_TX_CDC_MEM_CTRL_TM_SHIFT 12 +#define MEM_CTRL_TX_CDC_MEM_CTRL_TM_MASK 0xfff000 + +/* Test mode configuration of Rx CDC Memory. */ +#define MEM_CTRL_RX_CDC_MEM_CTRL_TM_SHIFT 0 +#define MEM_CTRL_RX_CDC_MEM_CTRL_TM_MASK 0xfff + + +/* + * Register + * + * XLMAC memories ECC control register + */ +#define XPORT_XLMAC_CORE_ECC_CTRL_REG 0x178 + +/* When set, MAC enables Tx CDC memory ECC logic */ +#define ECC_CTRL_TX_CDC_ECC_CTRL_EN_MASK 0x2 + +/* When set, MAC enables Rx CDC memory ECC logic */ +#define ECC_CTRL_RX_CDC_ECC_CTRL_EN_MASK 0x1 + + +/* + * Register + * + * XLMAC memories double bit error control register + */ +#define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_REG 0x180 + +/* + * Tx CDC memory force double bit error enable. + * The LSB 2 bits will be inverted at the next memory read. + * This should never be asserted simultaneously with + * TX_CDC_FORCE_SINGLE_BIT_ERR. + * In order to inject double bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * Rx CDC memory force double bit error enable. + * The LSB 2 bits will be inverted at the next memory read. + * This should never be asserted simultaneously with force + * RX_CDC_FORCE_SINGLE_BIT_ERR. + * In order to inject double bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_MASK 0x1 + + +/* + * Register + * + * XLMAC memories single bit error control register + */ +#define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_REG 0x188 + +/* + * Tx CDC memory force single bit error enable. + * The LSB 1 bit will be inverted at the next memory read. + * This should never be asserted simultaneously with + * TX_CDC_FORCE_DOUBLE_BIT_ERR. + * In order to inject single bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_MASK 0x2 + +/* + * Rx CDC memory force single bit error enable. + * The LSB 1 bit will be inverted at the next memory read. + * This should never be asserted simultaneously with + * RX_CDC_FORCE_DOUBLE_BIT_ERR. + * In order to inject single bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * Rx CDC memory ECC status register. + * These bits are sticky by nature, and can be cleared by writing to the + * clear register. + */ +#define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_REG 0x190 + +/* + * This status bit indicates a double bit error occurred in the Rx CDC + * memory +*/ +#define RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * This status bit indicates a single bit error occurred in the Rx CDC + * memory +*/ +#define RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * Tx CDC memory ECC status register. + * These bits are sticky by nature, and can be cleared by writing to the + * clear register. + */ +#define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_REG 0x198 + +/* + * This status bit indicates a double bit error occurred in the Tx CDC + * memory +*/ +#define TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * This status bit indicates a single bit error occurred in the Tx CDC + * memory +*/ +#define TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register + * + * Clear ECC status register, used to reset the sticky status bits + */ +#define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_REG 0x1a0 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_CDC_DOUBLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_MASK 0x8 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_CDC_SINGLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_MASK 0x4 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_CDC_DOUBLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_CDC_SINGLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * XLMAC interrupt status register + */ +#define XPORT_XLMAC_CORE_INTR_STATUS_REG 0x1a8 + +/* Active high qualifier for the TimeStamp & SEQUENCE_ID fields. */ +#define INTR_STATUS_SUM_TS_ENTRY_VALID_MASK 0x2000 + +/* + * True when link interruption state is detected as per RS layer state + * machine. + * Sticky bit is cleared by CLEAR_LINK_INTERRUPTION_STATUS. +*/ +#define INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_MASK 0x1000 + +/* + * True when remote fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_REMOTE_FAULT_STATUS. +*/ +#define INTR_STATUS_SUM_REMOTE_FAULT_STATUS_MASK 0x800 + +/* + * True when local fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_LOCAL_FAULT_STATUS +*/ +#define INTR_STATUS_SUM_LOCAL_FAULT_STATUS_MASK 0x400 + +/* + * This status bit indicates a double bit error occurred in the Rx CDC + * memory +*/ +#define INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_MASK 0x200 + +/* + * This status bit indicates a single bit error occurred in the Rx CDC + * memory +*/ +#define INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_MASK 0x100 + +/* + * This status bit indicates a double bit error occurred in the Tx CDC + * memory +*/ +#define INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_MASK 0x80 + +/* + * This status bit indicates a single bit error occurred in the Tx CDC + * memory +*/ +#define INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_MASK 0x40 + +/* If set, indicates rx message fifo overflow */ +#define INTR_STATUS_SUM_RX_MSG_OVERFLOW_MASK 0x20 + +/* If set, indicates RX packet fifo overflow */ +#define INTR_STATUS_SUM_RX_PKT_OVERFLOW_MASK 0x10 + +/* If set, indicates overflow occurred in TX two-step Time Stamp FIFO */ +#define INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_MASK 0x8 + +/* If set, indicates TX LLFC message fifo overflow */ +#define INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_MASK 0x4 + +/* If set, indicates tx packet fifo overflow */ +#define INTR_STATUS_SUM_TX_PKT_OVERFLOW_MASK 0x2 + +/* If set, indicates tx packet fifo underflow */ +#define INTR_STATUS_SUM_TX_PKT_UNDERFLOW_MASK 0x1 + + +/* + * Register + * + * XLMAC interrupt enable register + */ +#define XPORT_XLMAC_CORE_INTR_ENABLE_REG 0x1b0 + +/* If set, SUM_TS_ENTRY_VALID can set mac interrupt. */ +#define INTR_ENABLE_EN_TS_ENTRY_VALID_MASK 0x2000 + +/* If set, SUM_LINK_INTERRUPTION_STATUS can set mac interrupt. */ +#define INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_MASK 0x1000 + +/* If set, SUM_REMOTE_FAULT_STATUS can set mac interrupt. */ +#define INTR_ENABLE_EN_REMOTE_FAULT_STATUS_MASK 0x800 + +/* If set, SUM_LOCAL_FAULT_STATUS can set mac interrupt. */ +#define INTR_ENABLE_EN_LOCAL_FAULT_STATUS_MASK 0x400 + +/* If set, SUM_RX_CDC_DOUBLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_MASK 0x200 + +/* If set, SUM_RX_CDC_SINGLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_MASK 0x100 + +/* If set, SUM_TX_CDC_DOUBLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_MASK 0x80 + +/* If set, SUM_TX_CDC_SINGLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_MASK 0x40 + +/* If set, SUM_RX_MSG_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_MSG_OVERFLOW_MASK 0x20 + +/* If set, SUM_RX_PKT_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_PKT_OVERFLOW_MASK 0x10 + +/* If set, SUM_TX_TS_FIFO_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_MASK 0x8 + +/* If set, SUM_TX_LLFC_MSG_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_MASK 0x4 + +/* If set, SUM_TX_PKT_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_PKT_OVERFLOW_MASK 0x2 + +/* If set, SUM_TX_PKT_UNDERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_PKT_UNDERFLOW_MASK 0x1 + + +/* + * Register - read-only + * + * Version ID register + */ +#define XPORT_XLMAC_CORE_VERSION_ID_REG 0x1b8 + +/* XLMAC IP Version ID - corresponds to RTL/DV label */ +#define VERSION_ID_XLMAC_VERSION_SHIFT 0 +#define VERSION_ID_XLMAC_VERSION_MASK 0xffff + + +#endif /* ! WAN_TOPXPORT_XLMAC_CORE_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_reg.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_reg.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_reg.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_reg.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,429 @@ +#ifndef WAN_TOPXPORT_XLMAC_REG_H_ +#define WAN_TOPXPORT_XLMAC_REG_H_ + +/* relative to core */ +#define XPORT_XLMAC_REG_OFFSET_0 0x3000 + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_REG 0x0 + +/* + * Direct register access data write register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_SHIFT 0 +#define XPORT_XLMAC_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_DIR_ACC_DATA_READ_REG 0x4 + +/* + * Direct register access data read register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_DIR_ACC_DATA_READ_REG_READ_DATA_SHIFT 0 +#define XPORT_XLMAC_DIR_ACC_DATA_READ_REG_READ_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG 0x8 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_OFFSET_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_REG 0xc + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_REG 0x10 + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG 0x14 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_OFFSET_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_REG 0x18 + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_REG 0x1c + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_CONFIG_REG 0x20 + +/* Active high XLMAC hard reset. */ +#define XPORT_XLMAC_CONFIG_REG_XLMAC_RESET_MASK 0x200 + +/* + * When set, Rx CDC FIFO read TDM order has same port for 2 consecutive + * cycles. + * This is a strap input for the MAC core and should be changed only while + * hard reset is asserted. +*/ +#define XPORT_XLMAC_CONFIG_REG_RX_DUAL_CYCLE_TDM_EN_MASK 0x100 + +/* + * When set, RX CDC FIFO read TDM generation order for quad mode is + * 0,2,1,3. + * Otherwise, it is 0,1,2,3. + * This is a strap input for the MAC core and should be changed only while + * hard reset is asserted. +*/ +#define XPORT_XLMAC_CONFIG_REG_RX_NON_LINEAR_QUAD_TDM_EN_MASK 0x80 + +/* + * Enables non-linear TDM generation on the receive system interface, based + * on data availability in Rx FIFOs. + * 0 : + * Flex TDM Enabled. + * 1 : + * Flex TDM Disabled. +*/ +#define XPORT_XLMAC_CONFIG_REG_RX_FLEX_TDM_ENABLE_MASK 0x40 + +/* + * Number of ports supported by XLMAC. + * 000 : + * Quad Port. + * All ports are used. + * 001 : + * Tri-Port. + * Ports 0, 1 and 2 are used. + * 010 : + * Tri-Port. + * Ports 0, 2 and 3 are used. + * 011 : + * Dual Port. + * Port 0 and 2 are used. + * 1xx : + * Single Port. + * Port 0 is used. + * Note: + * Valid combinations for 63158 are single Port (P0 active) or Quad Port + * (P0 and/or P1 active). +*/ +#define XPORT_XLMAC_CONFIG_REG_MAC_MODE_SHIFT 3 +#define XPORT_XLMAC_CONFIG_REG_MAC_MODE_MASK 0x38 + +/* + * OSTS time-stamping disable. + * 0 : + * OSTS Enabled. + * 1 : + * OSTS Disabled. +*/ +#define XPORT_XLMAC_CONFIG_REG_OSTS_TIMER_DISABLE_MASK 0x4 + +/* + * Bypasses transmit OSTS functionality. + * When set, reduces Tx path latency. + * 0 : + * Do not bypass transmit OSTS function. + * 1 : + * Bypass transmit OSTS function. + * XLMAC must be reset for this bit to take effect. +*/ +#define XPORT_XLMAC_CONFIG_REG_BYPASS_OSTS_MASK 0x2 + +/* + * 1588 Egress Time-stamping mode. + * 0 : + * Legacy, sign extended 32-bit timestamp mode. + * 1 : + * 48-bit timestamp mode. + * XLMAC must be reset for this bit to take effect. +*/ +#define XPORT_XLMAC_CONFIG_REG_EGR_1588_TIMESTAMPING_MODE_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INTERRUPT_CHECK_REG 0x24 + +/* + * Each bit of this field corresponds to one XLMAC port. + * SW should write 1 to the corresponding bit(s) of this field any time + * XLMAC interrupt is in use and all events obtained by reading XLMAC + * status register are serviced and corresponding statuses cleared. + * Prevents XLMAC interrupt race condition. +*/ +#define XPORT_XLMAC_INTERRUPT_CHECK_REG_XLMAC_INTR_CHECK_SHIFT 0 +#define XPORT_XLMAC_INTERRUPT_CHECK_REG_XLMAC_INTR_CHECK_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_REG 0x28 + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_0_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_0_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_REG 0x2c + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_1_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_1_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_REG 0x30 + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_2_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_2_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_REG 0x34 + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_3_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_3_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_REG 0x40 + +/* + * Remote loopback logic starts reading packet data from the loopback FIFO + * only when at least READ_THRESHOLD entries are available in the FIFO. + * Used to prevent XLMAC TX underflow. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_READ_THRESHOLD_SHIFT 8 +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_READ_THRESHOLD_MASK 0x700 + +/* + * TX PORT_ID[1: + * 0]. + * Valid only when TX_PORT_SEL = 1. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_PORT_ID_SHIFT 6 +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_PORT_ID_MASK 0xc0 + +/* + * When set TX PORT_ID[1: + * 0] comes from this registers. + * When cleared TX PORT_ID[1: + * 0] equals RX PORT_ID[1: + * 0]. + * TX PORT_ID[1: + * 0] is used by remote loopback logic to monitor EP credits and to + * indicate outgoing XLMAC port. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_PORT_SEL_MASK 0x20 + +/* + * When set RXERR is propagated to TXERR. + * When cleared TXERR = 0. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_RXERR_EN_MASK 0x10 + +/* When set CRC is corrupted for the outgoing packet. */ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_CRC_ERR_MASK 0x8 + +/* + * TX CRC Mode. + * Encoded as: + * 00 : + * CRC Append. + * 01 : + * CRC Forward. + * 10 : + * CRC Replace. + * 11 : + * Reserved. + * CRC Append mode should be enabled only if XLMAC is programmed to strip + * off CRC. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_CRC_MODE_SHIFT 1 +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_CRC_MODE_MASK 0x6 + +/* + * When set enables XLMAC Remote (RX to TX) loopback. + * XLMAC must be kept in reset while remote loopback is being enabled and + * released from the reset thereafter. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_RMT_LOOPBACK_EN_MASK 0x1 + + +#endif /* ! WAN_TOPXPORT_XLMAC_REG_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/Makefile linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/Makefile --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/Makefile 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,4 @@ +obj-$(CONFIG_BCM63158_SF2) += bcm63158_sf2.o + +bcm63158_sf2-y += sf2_main.o sf2_fdb.o +bcm63158_sf2-$(CONFIG_DEBUG_FS) += sf2_debug.o diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/leds_top_regs.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/leds_top_regs.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/leds_top_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/leds_top_regs.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,8 @@ +#ifndef LEDS_TOP_REGS_H_ +# define LEDS_TOP_REGS_H_ + +#define LEDS_TOP_FLASH_RATE_REG(_x) (0x10 + (_x) * 4) +#define LEDS_TOP_BRIGHTNESS_REG(_x) (0x20 + (_x) * 4) +#define LEDS_TOP_POLARITY_REG (0xc0) + +#endif /* !LEDS_TOP_REGS_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/serdes_regs.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/serdes_regs.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/serdes_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/serdes_regs.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,7 @@ + +#define BRCM_MIIEXT_BANK 0x1f +# define BRCM_MIIEXT_BANK_MASK 0xfff0 +# define BRCM_MIIEXT_ADDR_RANGE 0xffe0 +# define BRCM_MIIEXT_DEF_BANK 0x8000 +#define BRCM_MIIEXT_OFFSET 0x10 +# define BRCM_MIIEXT_OFF_MASK 0xf diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_debug.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_debug.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_debug.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_debug.c 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,336 @@ +#include +#include +#include "sf2_priv.h" +#include "sf2_regs.h" + +static struct dentry *dbg_root; + +/* + * queues stats functions + */ +static void *queues_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos < SF2_PORT_COUNT) ? pos : NULL; +} + +static void *queues_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return (++(*pos) < SF2_PORT_COUNT) ? pos : NULL; +} + +static void queues_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int queues_seq_show(struct seq_file *s, void *arg) +{ + struct bcm_sf2_priv *priv = s->private; + int i = *(loff_t *)arg; + size_t queue; + u32 cur[SF2_NUM_EGRESS_QUEUES], peak[SF2_NUM_EGRESS_QUEUES]; + u32 v; + + if (!i) { + v = sw_core_readl(priv, SF2_CORE_FC_TOTAL_PEAK_COUNT); + seq_printf(s, "%-20s: %u\n", "total peak", v); + v = sw_core_readl(priv, SF2_CORE_FC_TOTAL_USED_COUNT); + seq_printf(s, "%-20s: %u\n", "total used", v); + seq_printf(s, "%-20s:\n", "usage per port & queue (cur/peak)"); + } + + sw_core_writel(priv, i, SF2_CORE_FC_DIAG_CTRL); + + /* clear latched peak values */ + (void)sw_core_readl(priv, SF2_CORE_FC_PEAK_RX); + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) + (void)sw_core_readl(priv, SF2_CORE_FC_QUEUE_PEAK_COUNT(queue)); + + /* give some time for peak values to adjust */ + msleep(10); + + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) + cur[queue] = sw_core_readl(priv, SF2_CORE_FC_QUEUE_CUR_COUNT(queue)); + + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) { + peak[queue] = sw_core_readw(priv, SF2_CORE_FC_QUEUE_PEAK_COUNT(queue)); + } + + seq_printf(s, "port[%u]: ", i); + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) { + seq_printf(s, "%3d/%-3d ", cur[queue], peak[queue]); + } + + v = sw_core_readw(priv, SF2_CORE_FC_PEAK_RX); + seq_printf(s, "[%3d]\n", v); + return 0; +} + +/* + * dump acb state + */ +static void *acb_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos < SF2_PORT_COUNT - 1) ? pos : NULL; +} + +static void *acb_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return (++(*pos) < SF2_PORT_COUNT - 1) ? pos : NULL; +} + +static void acb_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int acb_seq_show(struct seq_file *s, void *arg) +{ + struct bcm_sf2_priv *priv = s->private; + int i = *(loff_t *)arg; + size_t queue; + + seq_printf(s, "port[%u]: ", i); + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) { + u32 v; + + v = sw_acb_readl(priv, SF2_ACB_QINFLIGHT_REG(i, queue)); + seq_printf(s, "%3d ", v); + } + seq_printf(s, "\n"); + return 0; +} + +static const struct seq_operations queues_seq_ops = { + .start = queues_seq_start, + .next = queues_seq_next, + .stop = queues_seq_stop, + .show = queues_seq_show, +}; + +static const struct seq_operations acb_seq_ops = { + .start = acb_seq_start, + .next = acb_seq_next, + .stop = acb_seq_stop, + .show = acb_seq_show, +}; + +static int queues_open(struct inode *inode, struct file *filep) +{ + struct reg_dump_priv *rpriv = inode->i_private; + int ret; + + ret = seq_open(filep, &queues_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = rpriv; + return 0; +} + +static int acb_open(struct inode *inode, struct file *filep) +{ + struct reg_dump_priv *rpriv = inode->i_private; + int ret; + + ret = seq_open(filep, &acb_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = rpriv; + return 0; +} + +static const struct file_operations queues_fops = { + .owner = THIS_MODULE, + .open = queues_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static const struct file_operations acb_fops = { + .owner = THIS_MODULE, + .open = acb_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/* + * Dump ARL state + */ + +/* Show ARL table */ +static void *arl_show_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos == 0) ? pos : NULL; +} + +static void *arl_show_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return NULL; +} + +static void arl_show_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int arl_dump_entry(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent, + void *data) +{ + struct seq_file *s = (struct seq_file *)data; + seq_printf(s, "Mac %pM Vid: %u Port: %u Valid: %u Age: %u Static %u\n", + ent->mac, ent->vid, ent->port, ent->is_valid, + ent->is_age, ent->is_static); + return 0; +} + +static int arl_show_seq_show(struct seq_file *s, void *arg) +{ + struct bcm_sf2_priv *priv = s->private; + + seq_printf(s, "ACL: \n"); + sf2_arl_for_each(priv, arl_dump_entry, (void *)s); + return 0; +} + +static const struct seq_operations arl_show_seq_ops = { + .start = arl_show_seq_start, + .next = arl_show_seq_next, + .stop = arl_show_seq_stop, + .show = arl_show_seq_show, +}; + +static int arl_show_open(struct inode *inode, struct file *filep) +{ + struct reg_dump_priv *rpriv = inode->i_private; + int ret; + + ret = seq_open(filep, &arl_show_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = rpriv; + return 0; +} + +static const struct file_operations arl_show_fops = { + .owner = THIS_MODULE, + .open = arl_show_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/* Clear ARL entry */ +#define ARL_CLEAR_FILE_SZ 32 +struct arl_clear_file { + struct bcm_sf2_priv *priv; + char buf[ARL_CLEAR_FILE_SZ]; + struct mutex lock; +}; + +static ssize_t arl_clear_parse(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + struct arl_clear_file *fdata = file->private_data; + struct bcm_sf2_priv *priv = fdata->priv; + size_t size; + int ret; + u16 vid; + u8 mac[ETH_ALEN]; + + ret = mutex_lock_interruptible(&fdata->lock); + if (ret) + return ret; + + ret = -EFAULT; + size = min(sizeof(fdata->buf) - 1, len); + if (copy_from_user(fdata->buf, buf, size)) + goto out; + + fdata->buf[size] = '\0'; + ret = sscanf(fdata->buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx %hu", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5], + &vid); + if (ret != 7) { + ret = -EINVAL; + goto out; + } + + dev_info(&priv->pdev->dev, "Clearing mac %pM vid %u\n", mac, vid); + sf2_arl_delete(priv, mac, vid); + ret = len; +out: + mutex_unlock(&fdata->lock); + return ret; +} + +static int arl_clear_open(struct inode *inode, struct file *filep) +{ + struct arl_clear_file *fdata; + struct bcm_sf2_priv *priv = inode->i_private; + + fdata = devm_kzalloc(&priv->pdev->dev, sizeof(*fdata), GFP_KERNEL); + if (fdata == NULL) + return -ENOMEM; + + fdata->priv = priv; + mutex_init(&fdata->lock); + filep->private_data = fdata; + return nonseekable_open(inode, filep); +} + +static int arl_clear_release(struct inode *inode, struct file *file) +{ + struct bcm_sf2_priv *priv = inode->i_private; + devm_kfree(&priv->pdev->dev, file->private_data); + return 0; +} + +static const struct file_operations arl_clear_fops = { + .owner = THIS_MODULE, + .open = arl_clear_open, + .write = arl_clear_parse, + .llseek = no_llseek, + .release = arl_clear_release, +}; + +/* + * + */ +void bcm_sf2_dbg_init(struct bcm_sf2_priv *priv) +{ + struct dentry *dir; + dbg_root = debugfs_create_dir("bcm63158_sf2", NULL); + if (IS_ERR_OR_NULL(dbg_root)) + return; + + debugfs_create_file("queues", 0400, dbg_root, priv, &queues_fops); + debugfs_create_file("acb", 0400, dbg_root, priv, &acb_fops); + + dir = debugfs_create_dir("arl", dbg_root); + if (IS_ERR_OR_NULL(dir)) + return; + debugfs_create_file("show", 0400, dir, priv, &arl_show_fops); + debugfs_create_file("clear", 0200, dir, priv, &arl_clear_fops); +} + +/* + * + */ +void bcm_sf2_dbg_exit(void) +{ + if (!IS_ERR_OR_NULL(dbg_root)) + debugfs_remove_recursive(dbg_root); + dbg_root = NULL; +} diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_fdb.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_fdb.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_fdb.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_fdb.c 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,595 @@ +#include +#include +#include +#include +#include +#include + +#include "../../../net/bridge/br_private.h" +#include "sf2_priv.h" +#include "sf2_regs.h" + +#define SF2_FDB_POLL_DELAY_MS 1500 /* 1.5sec */ + +struct sf2_fdb_entry { + struct net_device *port; + struct hlist_node hlist; + struct list_head next; + u16 vid; + u8 mac[ETH_ALEN]; +}; + +/** + * Get FDB hashtable key from MAC address + * + * @mac: MAC address to compute the key from + * + * @return: The computed key + */ +static inline u64 sf2_mac_to_hkey(const u8 *mac) +{ + u64 key = 0; + ether_addr_copy((u8 *)&key, mac); + return key; +} + +/** + * Get FDB hashtable key from ARL info + * + * @ent: ARL info to compute the key from + * + * @return: The computed key + */ +static inline u64 sf2_arl_entry_to_hkey(const struct sf2_arl_entry *ent) +{ + return sf2_mac_to_hkey(ent->mac); +} + +/** + * Create a FDB entry from ARL info + * + * @priv: Common SD2 private object + * @ent: ARL info to create the FDB entry from + * + * @return: The newly created FDB entry on success, error pointer otherwise + */ +static struct sf2_fdb_entry * +sf2_fdb_add_entry(struct bcm_sf2_priv *priv, const struct sf2_arl_entry *ent) +{ + struct sf2_fdb_entry *fe; + u64 key; + + lockdep_assert_held(&priv->fdb.lock); + + fe = devm_kmalloc(&priv->pdev->dev, sizeof(*fe), GFP_KERNEL); + if (!fe) + return ERR_PTR(-ENOMEM); + ether_addr_copy(fe->mac, ent->mac); + fe->vid = ent->vid; + key = sf2_arl_entry_to_hkey(ent); + fe->port = dsa_to_port(priv->ds, ent->port)->slave; + hash_add(priv->fdb.arl_hash, &fe->hlist, key); + list_add(&fe->next, &priv->fdb.cache); + ++priv->fdb.nr_entries; + return fe; +} + +/** + * Cleanup a FDB entry + * + * @priv: Common SD2 private object + * @fe: FDB entry to clean + */ +static void sf2_fdb_del_entry(struct bcm_sf2_priv *priv, + struct sf2_fdb_entry *fe) +{ + lockdep_assert_held(&priv->fdb.lock); + + --priv->fdb.nr_entries; + hash_del(&fe->hlist); + list_del(&fe->next); + devm_kfree(&priv->pdev->dev, fe); +} + +struct sf2_vlan_notify { + enum switchdev_notifier_type type; + struct switchdev_notifier_fdb_info *info; +}; + +/** + * Notify switchdev subsystem to add/remove FDB entry for a specific vlan + * subdevice. + * + * @dev: VLAN subdevice + * @vid: VLAN ID of the subdevice + * @arg: FDB information + */ +static int _sf2_fdb_notify_vlan(struct net_device *dev, int vid, void *arg) +{ + struct sf2_vlan_notify *vn = (struct sf2_vlan_notify *)arg; + + call_switchdev_notifiers(vn->type, dev, &vn->info->info, NULL); + return 0; +} + +/** + * Notify switchdev subsystem to add/remove FDB entry. + * + * @priv: Common SF2 private structure + * @fe: FDB entry information to add to the bridge + * @added: True if the FDB should be added, false otherwise + */ +static void sf2_fdb_notify(struct bcm_sf2_priv *priv, + struct sf2_fdb_entry *fe, bool added) +{ + struct switchdev_notifier_fdb_info info = { + .addr = fe->mac, + .vid = fe->vid, + .offloaded = added, + }; + struct sf2_vlan_notify vnotify = { + .info = &info, + }; + enum switchdev_notifier_type type; + + type = added ? SWITCHDEV_FDB_ADD_TO_BRIDGE : + SWITCHDEV_FDB_DEL_TO_BRIDGE; + call_switchdev_notifiers(type, fe->port, &info.info, NULL); + vnotify.type = type; + + /* + * XXX This is hackish, vlan are not supported yet, but considering a + * setup where vlan is configured but any MAC learnt in one port could + * not be learnt in other port regardless of the packet vlan, vid + * interface could be used. + * + * Update the fdb for such sub interfaces. + */ + vlan_for_each(fe->port, _sf2_fdb_notify_vlan, &vnotify); +} + +struct sf2_arl_fdb_lookup { + struct bcm_sf2_priv *priv; + const struct sf2_arl_entry *ent; + struct net_bridge_fdb_entry *fdb; +}; + +/** + * Find if there is already a permanent FDB entry corresponding to an ARL one + * in the master bridge of a specific vlan sub interface + * + * @dev: Interface to check if a FDB entry matches in its master bridge + * @vid: Interface vlan id (not used) + * @arg: Holds ARL entry informations to match and filled in with found FDB if + * any + * + * @return: 0 if no FDB has been found, 1 otherwise + */ +static int _sf2_arl_find_permanent_fdb_rcu(struct net_device *dev, int vid, + void *arg) +{ + struct net_device *bdev = netdev_master_upper_dev_get(dev); + struct sf2_arl_fdb_lookup *afl = (struct sf2_arl_fdb_lookup *)arg; + struct net_bridge_fdb_entry *fdb; + struct net_bridge *br; + + if (!bdev || !netif_is_bridge_master(bdev)) + return 0; + + br = netdev_priv(bdev); + fdb = br_fdb_find_rcu(br, afl->ent->mac, afl->ent->vid); + if (!fdb || (!test_bit(BR_FDB_ADDED_BY_USER, &fdb->flags) && + !test_bit(BR_FDB_LOCAL, &fdb->flags))) + return 0; + + afl->fdb = fdb; + return 1; +} + +/** + * Find if there is already a permanent (user added or local) FDB entry + * corresponding to an ARL one in any SF2 port's bridges + * + * @priv: Common SF2 private object + * @ent: ARL entry to search correspond FDB one with + * + * @return: Found FDB entry if any, NULL pointer otherwise + */ +static struct net_bridge_fdb_entry * +sf2_arl_find_permanent_fdb_rcu(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent) +{ + struct net_device *port = dsa_to_port(priv->ds, ent->port)->slave; + struct sf2_arl_fdb_lookup afl = { + .priv = priv, + .ent = ent, + .fdb = NULL, + }; + + _sf2_arl_find_permanent_fdb_rcu(port, 0, &afl); + if (afl.fdb) + goto out; + + vlan_for_each(port, _sf2_arl_find_permanent_fdb_rcu, &afl); +out: + return afl.fdb; +} + +/** + * Synchronize a specific ARL entry with FDB table. This is supposed to be + * called for each ARL entries, at the end of this loop, data should point to + * the actual number of FDB entries that should be purged. + * + * @priv: Common SF2 private structure + * @ent: ARL entry to convert and add into FDB table + * @data: Updated with the number of FDB entry to remove + * + * @return: 0 + */ +static int sf2_arl_sync_entry(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent, + void *data) +{ + unsigned int *nr_purge = (unsigned int *)data; + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct net_bridge_fdb_entry *bfe; + struct net_device *port, *rdev; + const struct dsa_port *dp; + struct sf2_fdb_entry *fe; + u64 key; + + lockdep_assert_held(&fdb->lock); + + if (!ent->is_valid || (ent->port >= SF2_PORT_COUNT)) + goto out; + + dp = dsa_to_port(priv->ds, ent->port); + if ((dp->type != DSA_PORT_TYPE_USER) && + (dp->type != DSA_PORT_TYPE_DSA)) + goto out; + + port = dp->slave; + + rcu_read_lock(); + bfe = sf2_arl_find_permanent_fdb_rcu(priv, ent); + if (bfe) { + rdev = (bfe->dst) ? bfe->dst->dev : NULL; + if (rdev && is_vlan_dev(rdev)) + rdev = vlan_dev_real_dev(rdev); + /* + * Only remove ARL entry if the permanent FDB is for another + * port + */ + if (rdev != port) { + dev_dbg(&priv->pdev->dev, + "Removing ARL entry %pM for permanent FDB\n", + ent->mac); + sf2_arl_delete(priv, ent->mac, ent->vid); + } + rcu_read_unlock(); + goto out; + } + rcu_read_unlock(); + + key = sf2_arl_entry_to_hkey(ent); + hash_for_each_possible(fdb->arl_hash, fe, hlist, key) { + if (ether_addr_equal(ent->mac, fe->mac) && + (ent->vid == fe->vid)) { + /* Move hit beginning of cache list so that at the end + * all unhit fdb will be at in the cache tail */ + list_move(&fe->next, &fdb->cache); + if (!(*nr_purge)) { + dev_err(&priv->pdev->dev, + "FDB cache in weird state"); + goto out; + } + *nr_purge = *nr_purge - 1; + /* update source port */ + if (fe->port != port) { + fe->port = port; + sf2_fdb_notify(priv, fe, true); + } + goto out; + } + } + + /* This is a new entry sync our fdb cache and notify switchdev */ + fe = sf2_fdb_add_entry(priv, ent); + if (IS_ERR(fe)) { + dev_err(&priv->pdev->dev, "Cannot create fdb cache entry"); + goto out; + } + sf2_fdb_notify(priv, fe, true); + +out: + return 0; +} + +/** + * ARL/FDB synchronization worker, called regularly to poll for ARL table + * modifications and synchronize the FDB accordingly. + * + * @work: work structure + */ +static void sf2_fdb_bookkeeping(struct work_struct *work) +{ + struct bcm_sf2_priv *priv = container_of(work, struct bcm_sf2_priv, + fdb.poll_wk.work); + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct sf2_fdb_entry *fe; + unsigned int i, nr_purge = fdb->nr_entries; + u32 lrn = sw_core_readl(priv, SF2_CORE_TOTAL_SA_LRN_CNTR); + + rtnl_lock(); + + if (!lrn) + goto out; + + mutex_lock(&fdb->lock); + + /* Reset SA learn limit */ + sw_core_writel(priv, SF2_CORE_TOTAL_SA_LRN_CNTR_RST_MASK, + SF2_CORE_SA_LRN_CNTR_RST); + + /* + * Insert new sf2 entries and sort the cache in such a way that entries + * that are not in ARL table anymore will be at the end of this cache. + */ + sf2_arl_for_each(priv, sf2_arl_sync_entry, &nr_purge); + + /* + * Purge the first entries which are the ones that are not in sf2's ARL + * table anymore + */ + for (i = 0; i < nr_purge; ++i) { + if (list_empty(&fdb->cache)) { + dev_err(&priv->pdev->dev, "FDB cache in weird state"); + break; + } + fe = list_last_entry(&fdb->cache, struct sf2_fdb_entry, next); + sf2_fdb_notify(priv, fe, false); + sf2_fdb_del_entry(priv, fe); + } + + mutex_unlock(&fdb->lock); +out: + queue_delayed_work(fdb->poll_wq, &fdb->poll_wk, fdb->poll_delay); + rtnl_unlock(); +} + +/** + * Retrieve a SF2 port object from its net_device pointer + * + * @priv: Common SF2 object + * @dev: net_device object to find SF2 port from + * + * @return: The SF2 port if found, NULL pointer otherwise. + */ +static inline struct sf2_port * +sf2_find_port(struct bcm_sf2_priv *priv, struct net_device *dev) +{ + const struct dsa_port *dp; + size_t i; + for (i = 0; i < SF2_PORT_COUNT; ++i) { + dp = dsa_to_port(priv->ds, i); + if (dp->slave == dev) + return &priv->ports[dp->index]; + } + return NULL; +} + +/** + * Miror ARL table according to FDB event worker, called on new FDB event, + * remove an ARL entry if an FDB has been moved from an SF2's port to another + * one not belonging to the switch + * + * @work: Scheduled work data + */ +static void sf2_fdb_update(struct work_struct *work) +{ + struct sf2_switchdev_ev_work *wk = + container_of(work, struct sf2_switchdev_ev_work, work); + struct bcm_sf2_priv *priv = wk->priv; + struct net_device *dev = wk->dev; + struct net_device *rdev = dev; + struct sf2_fdb_entry *fe; + bool found = false; + u64 key; + + rtnl_lock(); + + key = sf2_mac_to_hkey(wk->info.addr); + + if (is_vlan_dev(rdev)) + rdev = vlan_dev_real_dev(rdev); + + mutex_lock(&priv->fdb.lock); + hash_for_each_possible(priv->fdb.arl_hash, fe, hlist, key) { + if (ether_addr_equal(wk->info.addr, fe->mac) && + (wk->info.vid == fe->vid)) { + found = true; + break; + } + } + + if (!found) + goto out; + + /* We are updating the same entry */ + if (unlikely(rdev == fe->port)) { + /* + * If FDB is added_by_user, we should stop synchronizing it with + * ARL + */ + if (wk->info.added_by_user) + sf2_fdb_del_entry(priv, fe); + goto out; + } + + if (unlikely(sf2_find_port(priv, rdev))) { + dev_warn(&priv->pdev->dev, + "FDB is on invalid sf2 port %s should be %s", + dev_name(&dev->dev), dev_name(&fe->port->dev)); + goto out; + } + + /* TODO check for same bridge */ + + dev_dbg(&priv->pdev->dev, "Removing ARL for %pM on port %s", + wk->info.addr, dev_name(&fe->port->dev)); + /* Remove other for other vlan */ + sf2_fdb_notify(priv, fe, false); + sf2_arl_delete(priv, wk->info.addr, wk->info.vid); + sf2_fdb_del_entry(priv, fe); + +out: + mutex_unlock(&priv->fdb.lock); + rtnl_unlock(); + /* + * atomic_set_release is not needed, as release semantic is done by + * previous mutex_unlock() and rtnl_unlock() + */ + atomic_set(&wk->free, 1); + dev_put(dev); +} + +/** + * Switchdev event handler callback + * + * @nb: Switchdev notifier object + * @event: Switchdev event ID + * @ptr: Event data + * + * @return: NOTIFY_DONE on success, NOTIFY_BAD otherwise + */ +static int sf2_switchdev_event(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct net_device *dev = switchdev_notifier_info_to_dev(ptr); + struct switchdev_notifier_fdb_info *fdb_info; + struct sf2_switchdev_ev_work *wk = NULL; + struct bcm_sf2_priv *priv; + int err = NOTIFY_DONE; + size_t i; + + if (event != SWITCHDEV_FDB_ADD_TO_DEVICE) + goto out; + + priv = container_of(nb, struct bcm_sf2_priv, fdb.switchdev_notifier); + fdb_info = container_of(ptr, struct switchdev_notifier_fdb_info, info); + err = NOTIFY_BAD; + + /* Find a usable switchdev event object and take reference on it */ + for (i = 0; i < ARRAY_SIZE(priv->fdb.sd_ev); i++) { + if (atomic_cmpxchg(&priv->fdb.sd_ev[i].free, 1, 0)) { + /* + * atomic_cmpxchg_acquire is not needed as the acquire + * semantic is done by queue_work() + */ + wk = &priv->fdb.sd_ev[i]; + break; + } + } + if (!wk) { + dev_err(&priv->pdev->dev, + "No free switchdev event object found"); + goto out; + } + wk->priv = priv; + wk->dev = dev; + memcpy(&wk->info, fdb_info, sizeof(wk->info)); + ether_addr_copy((u8 *)wk->info.addr, fdb_info->addr); + + /* Do not free dev in the meantime between now and sf2_fdb_update */ + dev_hold(dev); + INIT_WORK(&wk->work, sf2_fdb_update); + queue_work(priv->fdb.update_wq, &wk->work); + + err = NOTIFY_DONE; +out: + return err; +} + +/** + * Init fdb management structure and start ARL polling worker + * + * @priv: Common SF2 private structure to initialize fdb from + * @return: 0 on success, negative number otherwise + */ +int sf2_fdb_init(struct bcm_sf2_priv *priv) +{ + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct device *dev = &priv->pdev->dev; + size_t i; + + fdb->poll_wq = alloc_workqueue("%s-fdb-polling", 0, 0, dev_name(dev)); + if (!fdb->poll_wq) { + dev_err(&priv->pdev->dev, "Cannot allocate poll workqueue\n"); + goto err; + } + + fdb->update_wq = alloc_ordered_workqueue("%s-fdb-update", 0, + dev_name(dev)); + if (fdb->update_wq == NULL) { + dev_err(dev, "cannot create switchdev workqueue\n"); + goto update_err; + } + + for(i = 0; i < ARRAY_SIZE(fdb->sd_ev); ++i) { + fdb->sd_ev[i].info.addr = devm_kmalloc(dev, ETH_ALEN, + GFP_KERNEL); + if (!fdb->sd_ev[i].info.addr) + goto undo_sd_ev; + atomic_set(&fdb->sd_ev[i].free, 1); + } + + hash_init(fdb->arl_hash); + INIT_LIST_HEAD(&fdb->cache); + mutex_init(&fdb->lock); + + sw_core_writel(priv, gen_lan_port_mask(priv), SF2_CORE_SA_LIMIT_ENABLE); + INIT_DELAYED_WORK(&fdb->poll_wk, sf2_fdb_bookkeeping); + fdb->poll_delay = msecs_to_jiffies(SF2_FDB_POLL_DELAY_MS); + + fdb->switchdev_notifier.notifier_call = sf2_switchdev_event; + register_switchdev_notifier(&fdb->switchdev_notifier); + + queue_delayed_work(fdb->poll_wq, &fdb->poll_wk, fdb->poll_delay); + return 0; + +undo_sd_ev: + for(;i > 0; --i) + devm_kfree(dev, fdb->sd_ev[i - 1].info.addr); + destroy_workqueue(fdb->update_wq); +update_err: + destroy_workqueue(fdb->poll_wq); +err: + return -ENOMEM; +} + +/** + * Clenup fdb management structure and stop ARL polling worker + * + * @priv: Common SF2 private structure to cleanup fdb from + */ +void sf2_fdb_exit(struct bcm_sf2_priv *priv) +{ + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct sf2_fdb_entry *fe; + struct hlist_node *tmp; + size_t i; + int bkt; + + unregister_switchdev_notifier(&fdb->switchdev_notifier); + + for(i = 0; i < ARRAY_SIZE(fdb->sd_ev); ++i) + devm_kfree(&priv->pdev->dev, fdb->sd_ev[i].info.addr); + + destroy_workqueue(fdb->poll_wq); + destroy_workqueue(fdb->update_wq); + + hash_for_each_safe(fdb->arl_hash, bkt, tmp, fe, hlist) { + hash_del(&fe->hlist); + sf2_fdb_del_entry(priv, fe); + } +} diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_main.c linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_main.c --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_main.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_main.c 2023-11-22 18:41:18.366268920 +0100 @@ -0,0 +1,2716 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sf2_priv.h" +#include "sf2_regs.h" +#include "serdes_regs.h" +#include "leds_top_regs.h" + +static const struct sf2_port_hw_desc +bcm63158_port_descs[SF2_PORT_COUNT] = { + [0] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 0, + }, + + [1] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 1, + }, + + [2] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 2, + }, + + [3] = { + .port_type = SF2_PORT_T_XBAR_MUX1, + }, + + [4] = { + .port_type = SF2_PORT_T_XBAR_4X3, + .xbar_out_port = 0, + }, + + [5] = { + .port_type = SF2_PORT_T_UNIMAC, + }, + + [6] = { + .port_type = SF2_PORT_T_XBAR_4X3, + .xbar_out_port = 1, + }, + + [7] = { + .port_type = SF2_PORT_T_UNIMAC, + }, + + [8] = { + .port_type = SF2_PORT_T_XBAR_MUX2, + .is_imp = true, + }, +}; + +static const struct sf2_port_hw_desc +bcm63158_xbar_port_descs[SF2_XBAR_IN_PORT_COUNT] = { + [0] = { + .port_type = SF2_PORT_T_SERDES, + }, + + [1] = { + .port_type = SF2_PORT_T_SINGLE_GPHY, + }, + + [2] = { + .port_type = SF2_PORT_T_RGMII, + }, + + [3] = { + .port_type = SF2_PORT_T_RGMII, + }, +}; + +static const char * +bcm63158_xbar_in_port_names[SF2_XBAR_IN_PORT_COUNT] = { + [0] = "P9", + [1] = "P10", + [2] = "P11", + [3] = "P12", +}; + +static const char * +bcm63158_xbar_out_port_names[SF2_XBAR_OUT_PORT_COUNT] = { + [0] = "P4", + [1] = "P6", + [2] = "WAN", +}; + +static const struct sf2_port_hw_desc +bcm63158_mux1_port_descs[2] = { + [0] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 3, + }, + + [1] = { + .port_type = SF2_PORT_T_RGMII, + }, +}; + +static const char * +mux1_in_port_names[2] = { + "P14", + "P13", +}; + +static const char *mux1_out_port_name = "P3"; + +static const struct sf2_port_hw_desc +bcm63158_mux2_port_descs[2] = { + [0] = { + .port_type = SF2_PORT_T_SYSPORT, + }, + + [1] = { + .port_type = SF2_PORT_T_UNIMAC, + }, +}; + +static const char * +mux2_in_port_names[2] = { + "system_port", + "unimac", +}; + +static const char *mux2_out_port_name = "P8"; + + + +/* + * LEDS top helpers for led flash rate, brightness and polarity. + */ + +/* + * 4 registers, with 8 leds handled on each registers. 3 bits rate + * fields every 4 bits. + */ +static void leds_top_set_flash_rate(struct bcm_sf2_priv *priv, int led, + u8 rate) +{ + int reg_off = led / 8; + int reg_shift = (led % 8) * 4; + u32 reg; + + regmap_read(priv->leds_top_regmap, LEDS_TOP_FLASH_RATE_REG(reg_off), + ®); + reg &= ~(0x7 << reg_shift); + reg |= (rate << reg_shift); + regmap_write(priv->leds_top_regmap, LEDS_TOP_FLASH_RATE_REG(reg_off), + reg); +} + +/* + * 4 registers, with 8 leds handled on each registers. 4 bits + * brightness fields every 4 bits. + */ +static void leds_top_set_brightness(struct bcm_sf2_priv *priv, int led, + u8 brightness) +{ + int reg_off = led / 8; + int reg_shift = (led % 8) * 4; + u32 reg; + + regmap_read(priv->leds_top_regmap, LEDS_TOP_BRIGHTNESS_REG(reg_off), + ®); + reg &= ~(0xf << reg_shift); + reg |= (brightness << reg_shift); + regmap_write(priv->leds_top_regmap, LEDS_TOP_BRIGHTNESS_REG(reg_off), + reg); +} + +/* + * 1 register, with 32 leds handled on a signel register, 1 bit + * polarity fields. + */ +static void leds_top_set_polarity(struct bcm_sf2_priv *priv, int led, + int polarity) +{ + u32 reg; + + regmap_read(priv->leds_top_regmap, LEDS_TOP_POLARITY_REG, ®); + if (polarity) + reg |= (1 << led); + else + reg &= ~(1 << led); + regmap_write(priv->leds_top_regmap, LEDS_TOP_POLARITY_REG, reg); +} + +/* + * only handle link/activity leds. + */ +static void sf2_port_leds_control(struct bcm_sf2_priv *priv, + struct sf2_port *port, bool enable) +{ + if (!port->used || port->cfg.led_link_act < 0) + return; + + /* + * LEDS TOP setup + */ + leds_top_set_flash_rate(priv, port->cfg.led_link_act, 0x0); + leds_top_set_brightness(priv, port->cfg.led_link_act, + enable ? 0x8 : 0x0); + leds_top_set_polarity(priv, port->cfg.led_link_act, 0x1); + + /* + * SWITCH_REG setup + */ + if (enable) + sw_reg_writel(priv, LED_CTRL_TX_ACT_EN | LED_CTRL_RX_ACT_EN, + SF2_REG_LED_CTRL(port->id)); + else + sw_reg_writel(priv, 0x0, SF2_REG_LED_CTRL(port->id)); +} + +/* + * + */ +static void sf2_port_control(struct bcm_sf2_priv *priv, int port, bool enable) +{ + u32 reg; + + if (priv->ports[port].enabled == enable) + return; + + if (enable) + dev_info(&priv->pdev->dev, "enabling port %d\n", port); + else + dev_info(&priv->pdev->dev, "disabling port %d\n", port); + + if (bcm63158_port_descs[port].is_imp) { + reg = sw_core_readl(priv, SF2_CORE_IMP_CTL(port)); + /* FIXME */ + sw_core_writel(priv, reg, SF2_CORE_IMP_CTL(port)); + } else { + reg = sw_core_readl(priv, SF2_CORE_PCTL(port)); + if (enable) { + reg &= ~(PCTL_TXDIS | PCTL_RXDIS); + reg &= ~(PCTL_STP_MASK); + reg |= PCTL_STP_NONE; + } else { + reg |= (PCTL_TXDIS | PCTL_RXDIS); + } + sw_core_writel(priv, reg, SF2_CORE_PCTL(port)); + } + + sf2_port_leds_control(priv, &priv->ports[port], enable); + + priv->ports[port].enabled = enable; +} + + +/* + * mdio bus accessors + */ +static int __mdio_wait(struct bcm_sf2_priv *priv) +{ + u32 tries; + + /* at lowest clock speed (500khz), about 64 bits per transfer + * (32 bits preamble) => 128 us total */ + tries = 150; + while (tries) { + u32 cmd_reg; + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + if ((cmd_reg & CMD_BUSY) == 0) + break; + + --tries; + udelay(1); + } + + if (!tries) + return -ETIMEDOUT; + + return 0; +} + +/* + * + */ +static int sf2_mii_c45_addr(struct bcm_sf2_priv *priv, + int port_addr, int dev_addr, int reg) +{ + u32 cmd_reg; + int error; + + cmd_reg = OPCODE_C45_ADDR | + CMD_PHY_ADDR(port_addr) | + CMD_REG_ADDR(dev_addr) | + CMD_DATA(reg); + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + if (error) + return error; + + return 0; +} + +/* + * + */ +static int sf2_mii_read(struct mii_bus *bus, int addr, int reg) +{ + struct bcm_sf2_priv *priv = bus->priv; + u32 cmd_reg, cfg_reg; + int error; + u16 value; + + cfg_reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + cfg_reg |= MDIO_CLAUSE_22_MASK; + sw_mdio_writel(priv, cfg_reg, SF2_MDIO_CFG); + + cmd_reg = OPCODE_C22_READ | + CMD_PHY_ADDR(addr) | + CMD_REG_ADDR(reg); + + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + + if (error) { + dev_err(&priv->pdev->dev, + "errno%d waiting for MDIO phy@%d.\n", error, addr); + return error; + } + + value = sw_mdio_readl(priv, SF2_MDIO_CMD) & CMD_REG_DATA_MASK; + /* printk("sw_mii_read: => value: %x\n", value); */ + return value; +} + +/* + * + */ +static int sf2_mii_read_c45(struct mii_bus *bus, int addr, int dev_addr, int reg) +{ + struct bcm_sf2_priv *priv = bus->priv; + u32 cmd_reg, cfg_reg; + int error; + u16 value; + u16 port_addr = addr; + + cfg_reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + cfg_reg &= ~MDIO_CLAUSE_22_MASK; + sw_mdio_writel(priv, cfg_reg, SF2_MDIO_CFG); + + /* printk("sw_mii_c45_read: port_addr:%u dev_addr:%u reg:%u\n", */ + /* port_addr, dev_addr, reg); */ + + error = sf2_mii_c45_addr(priv, port_addr, dev_addr, reg); + if (error) + return error; + + cmd_reg = OPCODE_C45_READ | + CMD_PHY_ADDR(port_addr) | + CMD_REG_ADDR(dev_addr); + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + + if (error) { + dev_err(&priv->pdev->dev, + "errno%d waiting for MDIO phy@%d.\n", error, addr); + return error; + } + + value = sw_mdio_readl(priv, SF2_MDIO_CMD) & CMD_REG_DATA_MASK; + /* printk("sw_mii_read: => value: %x\n", value); */ + return value; +} + +/* + * + */ +static int sf2_mii_write(struct mii_bus *bus, + int addr, int reg, u16 value) +{ + struct bcm_sf2_priv *priv = bus->priv; + u32 cmd_reg, cfg_reg; + int error; + + cfg_reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + cfg_reg |= MDIO_CLAUSE_22_MASK; + sw_mdio_writel(priv, cfg_reg, SF2_MDIO_CFG); + + cmd_reg = OPCODE_C22_WRITE | + CMD_PHY_ADDR(addr) | + CMD_REG_ADDR(reg) | + CMD_DATA(value); + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + if (error) + return error; + return 0; +} + +/* + * + */ +static int sf2_mii_write_c45(struct mii_bus *bus, + int addr, int dev_addr, int reg, u16 value) +{ + struct bcm_sf2_priv *priv = bus->priv; + u32 cmd_reg, cfg_reg; + int error; + u16 port_addr = addr; + + cfg_reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + cfg_reg &= ~MDIO_CLAUSE_22_MASK; + sw_mdio_writel(priv, cfg_reg, SF2_MDIO_CFG); + + + /* printk("sw_mii_c45_writ: port_addr:%u dev_addr:%u reg:0x%x val:0x%x\n", */ + /* port_addr, dev_addr, reg, value); */ + + error = sf2_mii_c45_addr(priv, port_addr, dev_addr, reg); + if (error) + return error; + + cmd_reg = OPCODE_C45_WRITE | + CMD_PHY_ADDR(port_addr) | + CMD_REG_ADDR(dev_addr) | + CMD_DATA(value); + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + if (error) + return error; + return 0; +} + +/* + * + */ +static int sf2_mii_bus_reset(struct mii_bus *bus) +{ + struct bcm_sf2_priv *priv = bus->priv; + + /* do a dummy mdio transfer */ + if (priv->qphy_en_mask) + (void)mdiobus_read(bus, priv->config.qphy_base_id, MII_BMSR); + if (priv->sphy_en_mask) + (void)mdiobus_read(bus, priv->config.sphy_phy_id, MII_BMSR); + if (priv->serdes_en_mask) + (void)mdiobus_read(bus, priv->config.serdes_phy_id, MII_BMSR); + + return 0; +} + +/* + * powerup workaround needed for 63158, from refsw, initial problem + * not know nor reproduced during testing + */ +static void gphy_init_power_war(struct bcm_sf2_priv *priv) +{ + u32 reg; + + /* assert both reset */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg |= QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg |= SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + /* magic register */ + sw_reg_writel(priv, 1, SF2_REG_PHY_TEST); + + /* powerup */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg &= ~(QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_EXT_PWR_DOWN_ALL); + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg &= ~(SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_EXT_PWR_DOWN); + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + /* powerdown */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg |= (QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_EXT_PWR_DOWN_ALL); + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg |= (SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_EXT_PWR_DOWN); + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + /* deassert both reset */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg &= ~QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg &= ~SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + sw_reg_writel(priv, 0, SF2_REG_PHY_TEST); +} + +/* + * QUAD GPHY block init + */ +static void quad_gphy_block_init(struct bcm_sf2_priv *priv, + unsigned int enabled_port_mask, + unsigned int base_mdio_address) +{ + u32 reg; + + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + + /* set base mdio address */ + reg &= ~QPHY_CTRL_PHY_BASE_ADDR_MASK; + reg |= base_mdio_address << QPHY_CTRL_PHY_BASE_ADDR_SHIFT; + + if (!enabled_port_mask) { + /* power down */ + reg |= QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_EXT_PWR_DOWN_ALL | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_CLK_25_DISABLE; + } else { + reg &= ~(QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_EXT_PWR_DOWN_ALL); + + /* powerdown unused port */ + reg |= (~enabled_port_mask << QPHY_CTRL_EXT_PWR_DOWN_SHIFT) & + QPHY_CTRL_EXT_PWR_DOWN_ALL; + } + + /* toggle reset */ + reg |= QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + msleep(1); + + /* de-assert reset */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg &= ~QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + msleep(1); +} + +/* + * single GPHY block init + */ +static void single_gphy_block_init(struct bcm_sf2_priv *priv, + bool used, + unsigned int mdio_address) +{ + u32 reg; + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + + /* set mdio address */ + reg &= ~SPHY_CTRL_PHY_BASE_ADDR_MASK; + reg |= mdio_address << SPHY_CTRL_PHY_BASE_ADDR_SHIFT; + + if (!used) { + reg |= SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_EXT_PWR_DOWN | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_CLK_25_DISABLE; + } else { + reg &= ~(SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_EXT_PWR_DOWN); + } + + /* toggle reset */ + reg |= SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(1); + + /* de-assert reset */ + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg &= ~SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(1); +} + +/* + * serdes phy block init + */ +static void serdes_phy_block_init(struct bcm_sf2_priv *priv, + bool used, + unsigned int mdio_address, + bool invert_signal_detect) +{ + u32 reg; + + /* configure signal detect logic */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_APD_CTRL); + if (invert_signal_detect) + reg |= SSRD_APD_CTRL_INV_SD; + else + reg &= ~SSRD_APD_CTRL_INV_SD; + + /* + * complete reset and powerdown + */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_CTRL); + reg |= SSRD_CTRL_IDDQ_EN | + SSRD_CTRL_PDOWN_EN | + SSRD_CTRL_RESET_PLL | + SSRD_CTRL_RESET_MDIO | + SSRD_CTRL_RESET_SERDES; + reg &= ~SSRD_CTRL_PHY_BASE_ADDR_MASK; + reg |= mdio_address << SSRD_CTRL_PHY_BASE_ADDR_SHIFT; + sw_reg_writel(priv, reg, SF2_REG_SSRD_CTRL); + msleep(4); + + if (!used) + return; + + /* + * clear powerdown bits. + */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_CTRL); + reg &= ~(SSRD_CTRL_IDDQ_EN | + SSRD_CTRL_PDOWN_EN); + sw_reg_writel(priv, reg, SF2_REG_SSRD_CTRL); + msleep(4); + + /* + * clear reset bits + */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_CTRL); + reg &= ~(SSRD_CTRL_RESET_PLL | + SSRD_CTRL_RESET_MDIO | + SSRD_CTRL_RESET_SERDES); + sw_reg_writel(priv, reg, SF2_REG_SSRD_CTRL); + msleep(4); +} + +/* + * + */ +static void sf2_arl_to_entry(struct sf2_arl_entry *ent, + u64 mac_vid, u32 fwd_entry) +{ + memset(ent, 0, sizeof(*ent)); + ent->port = fwd_entry & ARLTBL_DATA_PORT_ID_MASK; + ent->is_valid = !!(fwd_entry & ARLTBL_VALID); + ent->is_age = !!(fwd_entry & ARLTBL_AGE); + ent->is_static = !!(fwd_entry & ARLTBL_STATIC); + u64_to_ether_addr(mac_vid, ent->mac); + ent->vid = mac_vid >> ARLTBL_VID_S; +} + +/* + * + */ +static int sf2_arl_search_wait(struct bcm_sf2_priv *priv) +{ + unsigned int timeout = 1000; + u8 reg; + + do { + reg = sw_core_readl(priv, SF2_CORE_ARL_SRCH_CTRL); + + if (!(reg & ARL_SRCH_STDN)) + return 0; + + if (reg & ARL_SRCH_VLID) + return 0; + + usleep_range(50, 100); + } while (timeout--); + + return -ETIMEDOUT; +} + +/* + * + */ +static void sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx, + struct sf2_arl_entry *ent) +{ + u64 mac_vid; + u32 fwd_entry; + + mac_vid = sw_core_readll(priv, SF2_CORE_ARL_SRCH_RSTx_MACVID(idx)); + fwd_entry = sw_core_readl(priv, SF2_CORE_ARL_SRCH_RSTx(idx)); + sf2_arl_to_entry(ent, mac_vid, fwd_entry); +} + +/* + * + */ +static int sf2_arl_op_wait(struct bcm_sf2_priv *priv) +{ + unsigned int timeout = 10; + u8 reg; + + do { + reg = sw_core_readl(priv, SF2_CORE_ARL_RWCTL); + if (!(reg & SF2_ARL_START)) + return 0; + + usleep_range(1000, 2000); + } while (timeout--); + + dev_warn(&priv->pdev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); + return -ETIMEDOUT; +} + +/* + * + */ +static int sf2_arl_rw_op(struct bcm_sf2_priv *priv, bool is_write) +{ + u8 reg; + + reg = sw_core_readl(priv, SF2_CORE_ARL_RWCTL); + reg |= SF2_ARL_START; + if (is_write) + reg &= ~SF2_ARL_READ; + else + reg |= SF2_ARL_READ; + + sw_core_writel(priv, reg, SF2_CORE_ARL_RWCTL); + return sf2_arl_op_wait(priv); +} + +/* + * + */ +static int sf2_arl_del_entry(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent, void *data) +{ + u64 mac; + int ret, i; + + /* Convert the array into a 64-bit MAC */ + mac = ether_addr_to_u64(ent->mac); + + /* Perform a read for the given MAC and VID */ + sw_core_writell(priv, mac, SF2_CORE_ARL_MAC_IDX); + sw_core_writell(priv, 0, SF2_CORE_ARL_VID_IDX); + + /* Issue a read operation for this MAC */ + ret = sf2_arl_rw_op(priv, false); + if (ret) + goto out; + + /* make all fwd entries invalid */ + for (i = 0; i < 4; i++) + sw_core_writell(priv, 0, SF2_CORE_ARL_FWDENTRY(i)); + + /* write */ + ret = sf2_arl_rw_op(priv, true); + +out: + if (ret) + dev_err(&priv->pdev->dev, "failed to delete mac from ARL\n"); + return ret; +} + +static void +_sf2_arl_for_each(struct bcm_sf2_priv *priv, + int (*fn)(struct bcm_sf2_priv *, const struct sf2_arl_entry *, + void *), + void *data) +{ + unsigned int count; + int ret; + u8 reg; + + /* Start search operation */ + count = 0; + reg = ARL_SRCH_STDN; + sw_core_writel(priv, reg, SF2_CORE_ARL_SRCH_CTRL); + + do { + int i; + + ret = sf2_arl_search_wait(priv); + if (ret) + return; + + for (i = 0; i < 2; i++) { + struct sf2_arl_entry ent; + + sf2_arl_search_rd(priv, i, &ent); + if (!ent.is_valid) + continue; + + if (fn(priv, &ent, data)) + return; + + } + + } while (count++ < 1024); +} + +void +sf2_arl_for_each(struct bcm_sf2_priv *priv, + int (*fn)(struct bcm_sf2_priv *, const struct sf2_arl_entry *, + void *), + void *data) +{ + return _sf2_arl_for_each(priv, fn, data); +} + +/* + * + */ +static void sf2_arl_clear(struct bcm_sf2_priv *priv) +{ + sf2_arl_for_each(priv, sf2_arl_del_entry, NULL); +} + +/* + * + */ +int sf2_arl_delete(struct bcm_sf2_priv *priv, const u8 *mac, u16 vid) +{ + struct sf2_arl_entry ent = { + .vid = 0, /* Force vid to 0, as there is no VLAN support yet */ + }; + + memcpy(ent.mac, mac, sizeof(ent.mac)); + sf2_arl_del_entry(priv, &ent, NULL); + return 0; +} + +/* + * + */ +static void sf2_hw_init(struct bcm_sf2_priv *priv) +{ + const struct sf2_config *config = &priv->config; + u32 reg; + int loop, i; + + /* + * power up block + * + * NOTE: the bootloader leave the SF2 enabled, doing a + * powerdown is not supported and can result in the switch not + * going out of reset (external abort accessing the registers). + * + * we just deassert reset in case bootloader did not + */ + reset_control_deassert(priv->rst); + msleep(10); + + /* + * soft reset switch (no effect on 63158 :/) + */ + sw_core_writel(priv, + SF2_SOFTWARE_RESET | + SF2_EN_SW_RST, + SF2_CORE_WATCHDOG_CTRL); + for (loop = 0; loop < 10000; loop++) { + reg = sw_core_readl(priv, SF2_CORE_WATCHDOG_CTRL); + if (!(reg & SF2_SOFTWARE_RESET)) + break; + udelay(100); + } + if (loop == 10000) + printk("SF2 soft reset failed\n"); + msleep(1); + + /* make sure forwarding is disabled */ + reg = sw_core_readl(priv, SF2_CORE_SWMODE); + reg &= ~SWMODE_FWD_EN; + sw_core_writel(priv, reg, SF2_CORE_SWMODE); + + /* reset does not work on 63158, restore some registers + * changed by CFE */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + u32 reg; + + reg = (1 << SF2_PORT_COUNT) - 1; + sw_core_writel(priv, reg, SF2_CORE_Px_VLAN_CTL(i)); + } + + /* since reset is not working, handle clear the ARL */ + sf2_arl_clear(priv); + + /* setup crossbar mapping */ + reg = sw_reg_readl(priv, SF2_REG_XBAR_CTRL); + reg &= ~(XBAR_PORT_MASK << XBAR_P4_SHIFT); + reg &= ~(XBAR_PORT_MASK << XBAR_P6_SHIFT); + reg &= ~(XBAR_PORT_MASK << XBAR_WAN_SHIFT); + reg &= ~XBAR_MUX1_MASK; + reg &= ~XBAR_MUX2_MASK; + + reg |= priv->xbar_mapping[0] << XBAR_P4_SHIFT; + reg |= priv->xbar_mapping[1] << XBAR_P6_SHIFT; + reg |= priv->xbar_mapping[2] << XBAR_WAN_SHIFT; + if (priv->mux1_mapping) + reg |= XBAR_MUX1_MASK; + if (priv->mux2_mapping) + reg |= XBAR_MUX2_MASK; + sw_reg_writel(priv, reg, SF2_REG_XBAR_CTRL); + + /* + * QPHY/SPHY has a powerup workaround on 63158 + */ + gphy_init_power_war(priv); + + /* + * init QPHY/SPHY/serdes PHY block + */ + quad_gphy_block_init(priv, priv->qphy_en_mask, + config->qphy_base_id); + single_gphy_block_init(priv, priv->sphy_en_mask != 0, + config->sphy_phy_id); + serdes_phy_block_init(priv, priv->serdes_en_mask != 0, + config->serdes_phy_id, + config->serdes_inv_sd); + + /* + * set MDIO frequency to ~9.6Mhz + * freq = (250Mhz / 2 * (DIV + 1)) + * + * FIXME: should be in device tree + */ + reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + reg &= ~MDIO_CLK_DIV_MASK; + reg |= (12 << MDIO_CLK_DIV_SHIFT); + sw_mdio_writel(priv, reg, SF2_MDIO_CFG); + + /* Wait until hardware enable the ports, or we will kill the + * hardware */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + for (loop = 0; loop < 10000; loop++) { + reg = sw_core_readl(priv, SF2_CORE_PCTL(i)); + if (!(reg & PCTL_RXDIS)) + break; + udelay(100); + } + if (loop == 10000) + printk("SF2 disable port %u failed\n", i); + } + + /* allow "mini jumbo" on all ports */ + reg = sw_core_readl(priv, SF2_CORE_MIB_GD_FM_MAX_SIZE); + reg &= ~SF2_GDM_FM_MAX_SIZE_MASK; + reg |= 2100; + sw_core_writel(priv, reg, SF2_CORE_MIB_GD_FM_MAX_SIZE); + + /* enable imp port to work as a normal port */ + reg = sw_core_readl(priv, SF2_CORE_CTRL); + reg &= 0xffb0; + sw_core_writel(priv, + SF2_CTRL_MII2_VOL_SEL | + SF2_CTRL_MII_DUMB_FWD_EN, + SF2_CORE_CTRL); + + /* enable unmanaged forwarding */ + reg = sw_core_readl(priv, SF2_CORE_SWMODE); + reg |= SWMODE_FWD_EN; + reg &= ~(SWMODE_FWD_MANAGED | SWMODE_RETRY_LIMIT_DIS); + sw_core_writel(priv, reg, SF2_CORE_SWMODE); +} + +/* + * internal serdes PHY access + */ +static int serdes_phy_read(struct bcm_sf2_priv *priv, u32 reg) +{ + return mdiobus_read(priv->mii_bus, priv->config.serdes_phy_id, reg); +} + +static int serdes_phy_write(struct bcm_sf2_priv *priv, u32 reg, u16 value) +{ + return mdiobus_write(priv->mii_bus, priv->config.serdes_phy_id, + reg, value); +} + +/* + * internal serdes PHY read from extended registers + */ +static __maybe_unused int serdes_ephy_read(struct bcm_sf2_priv *priv, int reg) +{ + uint32_t bank; + uint32_t offset; + int val; + int error; + + if (reg < 0x20) + return serdes_phy_read(priv, reg); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = serdes_phy_write(priv, BRCM_MIIEXT_BANK, bank); + val = serdes_phy_read(priv, offset); + if (val < 0) + error = val; + + error |= serdes_phy_write(priv, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + return (error < 0) ? error : val; +} + +/* + * internal serdes PHY write to extended registers + */ +static int serdes_ephy_write(struct bcm_sf2_priv *priv, int reg, u16 value) +{ + uint32_t bank; + uint32_t offset; + int error; + + if (reg < 0x20) + return serdes_phy_write(priv, reg, value); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = serdes_phy_write(priv, BRCM_MIIEXT_BANK, bank); + error |= serdes_phy_write(priv, offset, value); + error |= serdes_phy_write(priv, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + return error; +} + +/* + * internal serdes PHY bulk write to extended registers + */ +static int serdes_ephy_write_array(struct bcm_sf2_priv *priv, + const u16 *vals, size_t count) +{ + size_t i; + + for (i = 0; i < count; i += 2) { + int ret = serdes_ephy_write(priv, vals[i], vals[i + 1]); + if (ret < 0) + return ret; + } + return 0; +} + +/* + * reset internal serdes PHY + */ +static int serdes_reset(struct bcm_sf2_priv *priv) +{ + int retries = 100; + int ret; + + ret = serdes_phy_read(priv, MII_BMCR); + if (ret < 0) + return ret; + + ret |= BMCR_RESET; + ret = serdes_phy_write(priv, MII_BMCR, ret); + if (ret < 0) + return ret; + + do { + ret = serdes_phy_read(priv, MII_BMCR); + if (ret < 0) + return ret; + + msleep(10); + } while (ret & BMCR_RESET && --retries); + + return 0; +} + +/* + * restart aneg on internal serdes PHY + */ +static int serdes_aneg_restart(struct bcm_sf2_priv *priv) +{ + int ret; + + ret = serdes_phy_read(priv, MII_BMCR); + if (ret < 0) + return ret; + + ret |= BMCR_ANRESTART; + + ret = serdes_phy_write(priv, MII_BMCR, ret); + if (ret < 0) + return ret; + + return 0; +} + +/* + * regval + */ +static const u16 serdesRef50mVco6p25[] = { + 0x8000, 0x0c2f, + 0x8308, 0xc000, + 0x8050, 0x5740, + 0x8051, 0x01d0, + 0x8052, 0x19f0, + 0x8053, 0xaab0, + 0x8054, 0x8821, + 0x8055, 0x0044, + 0x8056, 0x8000, + 0x8057, 0x0872, + 0x8058, 0x0000, + + 0x8106, 0x0020, + 0x8054, 0x8021, + 0x8054, 0x8821, +}; + +static const u16 serdesSet2p5GFiber[] = { + 0x0010, 0x0C2F, /* disable pll start sequencer */ + 0x8300, 0x0149, /* enable fiber mode, signal_detect_en, invert signal detect(b2) */ + 0x8308, 0xC010, /* Force 2.5G Fiber, enable 50MHz refclk */ + 0x834a, 0x0001, /* Set os2 mode */ + 0x0000, 0x0140, /* disable AN, set 1G mode */ + 0x0010, 0x2C2F, /* enable pll start sequencer */ +}; + +#if 0 +static u16 serdesSet1GForcedFiber[] = { + 0x0010, 0x0c2f, /* disable pll start sequencer */ + 0x8300, 0x0109, /* Force Invert Signal Polarity */ + 0x8473, 0x1251, + 0x834a, 0x0003, + 0x0000, 0x0140, + 0x0010, 0x2c2f, /* enable pll start sequencer */ +}; +#endif + +static u16 serdesSet1GFiber [] = { + 0x0010, 0x0c2f, /* disable pll start sequencer */ + 0x8300, 0x0149, /* Force Auto Detect, Invert Signal Polarity */ + 0x8473, 0x1251, + 0x834a, 0x0003, + 0x0000, 0x1140, + 0x0010, 0x2c2f, /* enable pll start sequencer */ +}; + +static u16 serdesSet100MForcedSGMII [] = { + 0x0010, 0x0c2f, /* disable pll start sequencer */ + 0x8300, 0x0100, + 0x8301, 0x0007, + 0x8473, 0x1251, + 0x834a, 0x0003, + 0x0000, 0x2100, + 0x0010, 0x2c2f, /* enable pll start sequencer */ +}; + +static void serdes_set_1000basex(struct bcm_sf2_priv *priv) +{ +// printk("serdes_set_1000basex\n"); + serdes_reset(priv); + serdes_ephy_write_array(priv, serdesRef50mVco6p25, + ARRAY_SIZE(serdesRef50mVco6p25)); + msleep(1); + serdes_ephy_write_array(priv, serdesSet1GFiber, + ARRAY_SIZE(serdesSet1GFiber)); + serdes_aneg_restart(priv); +} + +static void serdes_set_2500basex(struct bcm_sf2_priv *priv) +{ +// printk("serdes_set_2500basex\n"); + serdes_reset(priv); + serdes_ephy_write_array(priv, serdesRef50mVco6p25, + ARRAY_SIZE(serdesRef50mVco6p25)); + msleep(1); + serdes_ephy_write_array(priv, serdesSet2p5GFiber, + ARRAY_SIZE(serdesSet2p5GFiber)); +} + +static void serdes_set_sgmii_100(struct bcm_sf2_priv *priv) +{ +// printk("serdes_set_sgmii_100\n"); + serdes_reset(priv); + msleep(1); + serdes_ephy_write_array(priv, serdesSet100MForcedSGMII, + ARRAY_SIZE(serdesSet100MForcedSGMII)); + serdes_aneg_restart(priv); +} + +/* + * + */ +static void sf2_dsa_phylink_get_caps(struct dsa_switch *ds, int port_id, + struct phylink_config *config) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE; + + switch (port->pdesc->port_type) { + case SF2_PORT_T_RGMII: + case SF2_PORT_T_QUAD_GPHY: + case SF2_PORT_T_SINGLE_GPHY: + config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD; + break; + + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + config->mac_capabilities |= MAC_1000 | MAC_2500FD; + break; + + case SF2_PORT_T_SERDES: + config->mac_capabilities |= MAC_100 | MAC_1000FD | MAC_2500FD; + break; + + default: + WARN(1, "invalid hw desc"); + } + + pr_debug("sf2_dsa_phylink_get_caps: port%d caps %08lx\n", port_id, + config->mac_capabilities); +} + +/* + * + */ +static void sf2_dsa_phylink_mac_config(struct dsa_switch *ds, int port_id, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_config port:%d\n", port->id); + + switch (port->pdesc->port_type) { + case SF2_PORT_T_QUAD_GPHY: + case SF2_PORT_T_SINGLE_GPHY: + WARN_ON(mode != MLO_AN_PHY); + + /* should not happen because we check this in validate */ + WARN_ON(state->interface != PHY_INTERFACE_MODE_GMII); + + /* for internal phys, local mac config is adjusted + * automatically, nothing to do */ + return; + + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + case SF2_PORT_T_RGMII: + WARN_ON(mode != MLO_AN_PHY && mode != MLO_AN_FIXED); + + /* should not happen because we check this in validate */ + WARN_ON(state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_GMII); + + if (bcm63158_port_descs[port->id].is_imp) { + u32 reg; + + reg = sw_core_readl(priv, SF2_CORE_STS_OV_IMP_STATE); + reg |= STS_OV_IMP_LINK_MASK | + STS_OV_IMP_MII_SW_OVER_MASK; + + if (state->duplex) + reg |= STS_OV_IMP_FULL_DUPLEX_MASK; + else + reg &= ~STS_OV_IMP_FULL_DUPLEX_MASK; + + reg &= ~STS_OV_IMP_SPEED_ALL_MASK; + switch (state->speed) { + case 10: + reg |= STS_OV_IMP_SPEED_10_MASK; + break; + case 100: + reg |= STS_OV_IMP_SPEED_100_MASK; + break; + case 1000: + case 2500: + reg |= STS_OV_IMP_SPEED_1000_MASK; + break; + } + + if (state->pause & MLO_PAUSE_RX) + reg |= STS_OV_IMP_RX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_IMP_RX_FLOW_CTL_MASK; + + if (state->pause & MLO_PAUSE_TX) + reg |= STS_OV_IMP_TX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_IMP_TX_FLOW_CTL_MASK; + + sw_core_writel(priv, reg, SF2_CORE_STS_OV_IMP_STATE); + } else { + u32 reg; + + reg = sw_core_readl(priv, + SF2_CORE_STS_OV_Px_STATE(port->id)); + + reg |= STS_OV_Px_LINK_MASK | + STS_OV_Px_SW_OVER_MASK; + + if (state->duplex) + reg |= STS_OV_Px_FULL_DUPLEX_MASK; + else + reg &= ~STS_OV_Px_FULL_DUPLEX_MASK; + + reg &= ~STS_OV_Px_SPEED_ALL_MASK; + switch (state->speed) { + case 10: + reg |= STS_OV_Px_SPEED_10_MASK; + break; + case 100: + reg |= STS_OV_Px_SPEED_100_MASK; + break; + case 1000: + case 2500: + reg |= STS_OV_Px_SPEED_1000_MASK; + break; + } + + if (state->pause & MLO_PAUSE_RX) + reg |= STS_OV_Px_RX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_Px_RX_FLOW_CTL_MASK; + + if (state->pause & MLO_PAUSE_TX) + reg |= STS_OV_Px_TX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_Px_TX_FLOW_CTL_MASK; + + sw_core_writel(priv, reg, + SF2_CORE_STS_OV_Px_STATE(port->id)); + } + + /* + * setup high speed IMP ports + */ + if (port->pdesc->port_type == SF2_PORT_T_UNIMAC || + port->pdesc->port_type == SF2_PORT_T_SYSPORT) { + u32 mask, spd, reg; + + switch (port_id) { + case 5: + mask = SW_CTRL_P5_SPEED_MASK; + if (state->speed == 2500) + spd = SW_CTRL_P5_SPEED_2_5G; + else + spd = SW_CTRL_P5_SPEED_1G; + break; + case 7: + mask = SW_CTRL_P7_SPEED_MASK; + if (state->speed == 2500) + spd = SW_CTRL_P7_SPEED_2_5G; + else + spd = SW_CTRL_P7_SPEED_1G; + break; + case 8: + mask = SW_CTRL_P8_SPEED_MASK; + if (state->speed == 2500) + spd = SW_CTRL_P8_SPEED_2_5G; + else + spd = SW_CTRL_P8_SPEED_1G; + break; + + default: + WARN(1, "unknown cpu port"); + mask = 0; + spd = 0; + break; + } + + reg = sw_reg_readl(priv, SF2_REG_SW_CTRL); + reg &= ~mask; + reg |= spd; + sw_reg_writel(priv, reg, SF2_REG_SW_CTRL); + } + break; + + case SF2_PORT_T_SERDES: + switch (state->interface) { + case PHY_INTERFACE_MODE_1000BASEX: + serdes_set_1000basex(priv); + break; + + case PHY_INTERFACE_MODE_SGMII: + if (state->speed == 100) + serdes_set_sgmii_100(priv); + else + serdes_set_1000basex(priv); + break; + + case PHY_INTERFACE_MODE_2500BASEX: + serdes_set_2500basex(priv); + break; + + default: + /* should not happen because we check this in + * validate */ + WARN(1, "unexpected interface mode"); + break; + } + break; + + default: + break; + } +} + +/* + * + */ +static int sf2_dsa_phylink_mac_link_state(struct dsa_switch *ds, int port_id, + struct phylink_link_state *state) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_link_state port:%d\n", port->id); + + /* only called for %MLO_AN_INBAND, so serdes only */ + if (WARN(port->pdesc->port_type != SF2_PORT_T_SERDES, + "mac_link_state called on non serdes port")) + return 0; + + return 0; +} + +/* + * + */ +static void sf2_dsa_phylink_mac_an_restart(struct dsa_switch *ds, int port_id) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_an_restart port:%d\n", port->id); + + /* only called for %MLO_AN_INBAND, so serdes only */ + if (WARN_ON(port->pdesc->port_type != SF2_PORT_T_SERDES)) + return; +} + +/* + * enable/disable EEE LPI request generation by hardware for given port + */ +static void sf2_setup_port_eee(struct bcm_sf2_priv *priv, + struct sf2_port *port, bool enable) +{ + u32 reg; + + reg = sw_core_readl(priv, SF2_CORE_EEE_EN_CTRL_REG); + if (enable) + reg |= BIT(port->id); + else + reg &= ~BIT(port->id); + sw_core_writel(priv, reg, SF2_CORE_EEE_EN_CTRL_REG); +} + +/* + * + */ +static void sf2_dsa_phylink_mac_link_up(struct dsa_switch *ds, int port_id, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phy, + int speed, int duplex, + bool tx_pause, bool rx_pause) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + bool eee_active; + + pr_debug("sf2_phylink_mac_link_up port:%d\n", port->id); + + if (mode == MLO_AN_PHY && phy) + eee_active = (phy_init_eee(phy, 0) >= 0); + + sf2_setup_port_eee(priv, port, eee_active && port->tx_lpi_enabled); +} + +/* + * + */ +static void sf2_dsa_phylink_mac_link_down(struct dsa_switch *ds, int port_id, + unsigned int mode, + phy_interface_t interface) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_link_down port:%d\n", port->id); +} + +static int sf2_dsa_port_setup(struct dsa_switch *ds, int port, + struct phy_device *phy) +{ + struct bcm_sf2_priv *priv = ds->priv; + pr_debug("sf2_dsa_port_setup port:%d", port); + sf2_port_control(priv, port, true); + return 0; +} + +static void sf2_dsa_port_disable(struct dsa_switch *ds, int port) +{ + struct bcm_sf2_priv *priv = ds->priv; + pr_debug("sf2_dsa_port_disable port:%d", port); + sf2_port_control(priv, port, false); +} + +/* + * + */ +static int sf2_dsa_setup(struct dsa_switch *ds) +{ + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + u32 lan_ports, cpu_ports, reg, reg2; + int ret; + struct dsa_port *dp; + + pr_debug("dsa_setup"); + + cpu_ports = gen_cpu_port_mask(priv); + lan_ports = gen_lan_port_mask(priv); + + /* resolve which cpu port to use for each port */ + list_for_each_entry(dp, &ds->dst->ports, list) { + switch (dp->type) { + case DSA_PORT_TYPE_UNUSED: + continue; + + case DSA_PORT_TYPE_CPU: + if (!(cpu_ports & (1 << dp->index))) { + dev_err(&priv->pdev->dev, + "cpu port config mismatch\n"); + return -EINVAL; + } + continue; + + default: + { + int cpu_index; + + if (WARN_ON(!dp->cpu_dp)) + return -EINVAL; + + cpu_index = dp->cpu_dp->index; + + if (cpu_index >= SF2_PORT_COUNT || + !(cpu_ports & (1 << cpu_index))) { + dev_err(&priv->pdev->dev, + "port %u points to invalid " + "cpu port %u\n", dp->index, cpu_index); + return -EINVAL; + } + + priv->ports[dp->index].cfg.cpu_port = cpu_index; + break; + } + } + } + + sf2_hw_init(priv); + + ret = of_mdiobus_register(priv->mii_bus, priv->mdio_np); + if (ret) { + dev_err(&priv->pdev->dev, "failed to register mdio bus"); + goto out_mdio; + } + + /* make sure all lan ports can only talk to cpu port */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + if (!(lan_ports & (1 << i))) + continue; + + sw_core_writel(priv, + (1 << i) | + (1 << priv->ports[i].cfg.cpu_port), + SF2_CORE_Px_VLAN_CTL(i)); + } + + /* enable brcm tag on all cpu ports */ + reg = reg2 = 0; + for (i = 0; i < SF2_PORT_COUNT; i++) { + if (!(cpu_ports & (1 << i))) + continue; + + switch (i) { + case 8: + reg |= SF2_BRCMTAG_P8; + break; + case 5: + reg |= SF2_BRCMTAG_P5; + break; + case 7: + reg |= SF2_BRCMTAG_P7; + break; + default: + reg2 |= SF2_BRCMTAG2_Px(i); + break; + } + } + + sw_core_writel(priv, reg, SF2_CORE_BRCMTAG_CTRL); + sw_core_writel(priv, reg2, SF2_CORE_BRCMTAG2_CTRL); + + /* enable brcmtag priority to TC (queue) mapping on cpu ports */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + unsigned int q; + + if (!(cpu_ports & (1 << i))) + continue; + + /* map 1:1 between prio number and queue id */ + reg = sw_core_readl(priv, SF2_CORE_PORT_TC2_QOS_MAP_PORT(i)); + for (q = 0; q < SF2_NUM_EGRESS_QUEUES; q++) + reg |= q << (PRT_TO_QID_SHIFT * q); + sw_core_writel(priv, reg, SF2_CORE_PORT_TC2_QOS_MAP_PORT(i)); + } + + /* configure & enable ACB */ + reg = sw_acb_readl(priv, SF2_ACB_CONTROL_REG); + reg &= ~ACB_CONTROL_EN_MASK; + reg &= ~ACB_CONTROL_FLUSHQ_MASK; + sw_acb_writel(priv, reg, SF2_ACB_CONTROL_REG); + + for (i = 0; i < SF2_PORT_COUNT; i++) { + size_t q; + + if ((cpu_ports & (1 << i))) + continue; + + for (q = 0; q < SF2_NUM_EGRESS_QUEUES; q++) { + reg = sw_acb_readl(priv, SF2_ACB_QCFG_REG(i, q)); + reg &= ~ACB_QCFG_XOFF_THRESH_MASK; + reg |= 24 << ACB_QCFG_XOFF_THRESH_SHIFT; + sw_acb_writel(priv, reg, SF2_ACB_QCFG_REG(i, q)); + } + } + + reg = sw_acb_readl(priv, SF2_ACB_CONTROL_REG); + reg |= ACB_CONTROL_FLUSHQ_MASK; + sw_acb_writel(priv, reg, SF2_ACB_CONTROL_REG); + reg &= ~ACB_CONTROL_FLUSHQ_MASK; + reg |= ACB_CONTROL_ALG2_MASK; + reg |= ACB_CONTROL_EN_MASK; + sw_acb_writel(priv, reg, SF2_ACB_CONTROL_REG); + + /* + * disable learning on cpu ports + * + * in case there are multiple CPU ports, the mac address from + * the bridge devices will keep flapping between them, since + * we can't install a mac address on multiple ports in the ATU + * we disable learning on those ports. + * + * this means all traffic coming from lan ports that should go + * to the CPU will be flooded by the switch, to avoid that we + * also change the default flood map registers to the switch + * only flood unknown unicast/multicast to the CPU port, which + * will then flood back the packets to the lan ports if + * needed. + * + * there does not seem to be a way to prevent the switch from + * flooding broadcast, so to prevent duplicate flooding, we + * mark those packets as already offloaded in the BRCM tag + * code + */ + sw_core_writel(priv, cpu_ports, SF2_CORE_DIS_LEARN); + sw_core_writel(priv, cpu_ports, SF2_CORE_UFL_FWD_MAP); + sw_core_writel(priv, cpu_ports, SF2_CORE_MFL_FWD_MAP); + sw_core_writel(priv, cpu_ports, SF2_CORE_IPMC_FWD_MAP); + + reg = sw_core_readl(priv, SF2_CORE_NEW_CTRL); + reg |= SF2_NEW_CTRL_MC_FWD_EN | + SF2_NEW_CTRL_UC_FWD_EN; + sw_core_writel(priv, reg, SF2_CORE_NEW_CTRL); + + ret = sf2_fdb_init(priv); + if (ret) { + dev_err(&priv->pdev->dev, "failed to init fdb monitoring"); + goto out_fdb; + } + + return 0; + +out_mdio: + sf2_fdb_exit(priv); +out_fdb: + mdiobus_unregister(priv->mii_bus); + return ret; +} + +/* + * + */ +static void sf2_dsa_teardown(struct dsa_switch *ds) +{ + struct bcm_sf2_priv *priv = ds->priv; + + pr_debug("dsa_teardown"); + + sf2_fdb_exit(priv); + mdiobus_unregister(priv->mii_bus); +} + +/* + * + */ +static enum dsa_tag_protocol sf2_dsa_get_tag_protocol(struct dsa_switch *ds, + int port_id, + enum dsa_tag_protocol mp) +{ + return DSA_TAG_PROTO_BRCM_FBX; +} + +struct sf2_mib_desc { + u8 size; + u8 offset; + const char *name; +}; + +static const struct sf2_mib_desc sf2_mibs[] = { + { 8, 0x00, "TxOctets" }, + { 4, 0x10, "TxBroadcastPkts" }, + { 4, 0x14, "TxMulticastPkts" }, + { 4, 0x18, "TxUnicastPKts" }, + { 4, 0x08, "TxDropPkts" }, + { 4, 0x1c, "TxCollisions" }, + { 4, 0x20, "TxSingleCollision" }, + { 4, 0x24, "TxMultipleCollision" }, + { 4, 0x28, "TxDeferredCollision" }, + { 4, 0x2c, "TxLateCollision" }, + { 4, 0x30, "TxExcessiveCollision" }, + { 4, 0x34, "TxFrameInDiscard" }, + { 4, 0x38, "TxPausePkts" }, + { 4, 0xd0, "TxPkts64Octets" }, + { 4, 0xd4, "TxPkts65to127Octets" }, + { 4, 0xd8, "TxPkts128to255Octets" }, + { 4, 0xdc, "TxPkts256to511Octets" }, + { 4, 0xe0, "TxPkts512to1023Octets" }, + { 4, 0xe4, "TxPkts1024toMaxPktOctets" }, + { 4, 0x0c, "TxQPKTQ0" }, + { 4, 0x3c, "TxQPKTQ1" }, + { 4, 0x40, "TxQPKTQ2" }, + { 4, 0x44, "TxQPKTQ3" }, + { 4, 0x48, "TxQPKTQ4" }, + { 4, 0x4c, "TxQPKTQ5" }, + { 4, 0xc8, "TxQPKTQ6" }, + { 4, 0xcc, "TxQPKTQ7" }, + { 8, 0x50, "RxOctets" }, + { 4, 0x58, "RxUndersizePkts" }, + { 4, 0x5c, "RxPausePkts" }, + { 4, 0x60, "RxPkts64Octets" }, + { 4, 0x64, "RxPkts65to127Octets" }, + { 4, 0x68, "RxPkts128to255Octets" }, + { 4, 0x6c, "RxPkts256to511Octets" }, + { 4, 0x70, "RxPkts512to1023Octets" }, + { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, + { 4, 0x78, "RxOversizePkts" }, + { 4, 0x7c, "RxJabbers" }, + { 4, 0x80, "RxAlignmentErrors" }, + { 4, 0x84, "RxFCSErrors" }, + { 8, 0x88, "RxGoodOctets" }, + { 4, 0x90, "RxDropPkts" }, + { 4, 0x94, "RxUnicastPkts" }, + { 4, 0x98, "RxMulticastPkts" }, + { 4, 0x9c, "RxBroadcastPkts" }, + { 4, 0xa0, "RxSAChanges" }, + { 4, 0xa4, "RxFragments" }, + { 4, 0xa8, "RxJumboPkt" }, + { 4, 0xac, "RxSymblErr" }, + { 4, 0xc0, "RxDiscard" }, + { 4, 0xb0, "InRangeErrCount" }, + { 4, 0xb4, "OutRangeErrCount" }, + { 4, 0xb8, "EEELpiEvent" }, + { 4, 0xbc, "EEELpiDuration" }, +}; + +#define SF2_MIBS_SIZE ARRAY_SIZE(sf2_mibs) + +/* + * + */ +static int sf2_dsa_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct phy_device *phydev; + + switch (sset) { + case ETH_SS_STATS: + return SF2_MIBS_SIZE; + + case ETH_SS_PHY_STATS: + phydev = mdiobus_get_phy(priv->mii_bus, port); + if (!phydev) + return 0; + + return phy_ethtool_get_sset_count(phydev); + } + + return 0; +} + +/* + * + */ +static void sf2_dsa_get_strings(struct dsa_switch *ds, int port, + u32 sset, uint8_t *data) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct phy_device *phydev; + unsigned int i; + + switch (sset) { + case ETH_SS_STATS: + for (i = 0; i < SF2_MIBS_SIZE; i++) + strlcpy(data + i * ETH_GSTRING_LEN, + sf2_mibs[i].name, ETH_GSTRING_LEN); + break; + case ETH_SS_PHY_STATS: + phydev = mdiobus_get_phy(priv->mii_bus, port); + if (!phydev) + return; + + phy_ethtool_get_strings(phydev, data); + break; + } +} + +/* + * + */ +static void sf2_dsa_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + + for (i = 0; i < SF2_MIBS_SIZE; i++) { + const struct sf2_mib_desc *s = &sf2_mibs[i]; + u32 offset = SF2_CORE_Px_MIB(port) + s->offset * 8; + u64 val; + + if (s->size == 8) + val = sw_core_readll(priv, offset); + else + val = sw_core_readl(priv, offset); + + data[i] = val; + } +} + +/* + * + */ +static void sf2_dsa_get_ethtool_phy_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct phy_device *phydev; + + phydev = mdiobus_get_phy(priv->mii_bus, port); + if (!phydev) + return; + + phy_ethtool_get_stats(phydev, NULL, data); +} + +/* + * + */ +static int sf2_dsa_port_join_pxvlan(struct dsa_switch *ds, int port, + const struct dsa_bridge *br) +{ + const struct dsa_port *dp = dsa_to_port(ds, port); + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + u32 pvlan; + + + if (dp->type == DSA_PORT_TYPE_CPU) + return 0; + + /* + * add port to all others ports PBVLAN map when they share the + * same bridge + */ + pvlan = 0; + for (i = 0; i < SF2_PORT_COUNT; i++) { + u32 reg; + + if (i == port) + continue; + + if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), br)) + continue; + + reg = sw_core_readl(priv, SF2_CORE_Px_VLAN_CTL(i)); + reg |= BIT(port); + sw_core_writel(priv, reg, SF2_CORE_Px_VLAN_CTL(i)); + + pvlan |= BIT(i); + } + + pvlan |= (1 << port); + pvlan |= (1 << priv->ports[port].cfg.cpu_port); + sw_core_writel(priv, pvlan, SF2_CORE_Px_VLAN_CTL(port)); + + return 0; +} + +static int sf2_dsa_port_bridge_join(struct dsa_switch *ds, int port, + struct dsa_bridge br, + bool *tx_fwd_offload, + struct netlink_ext_ack *extack) +{ + pr_debug("sf2_dsa_port_bridge_join: port:%d\n", port); + return sf2_dsa_port_join_pxvlan(ds, port, &br); +} + +/* + * + */ +static void sf2_dsa_port_leave_pxvlan(struct dsa_switch *ds, int port, + const struct dsa_bridge *br) +{ + const struct dsa_port *dp = dsa_to_port(ds, port); + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + + if (dp->type == DSA_PORT_TYPE_CPU) + return; + + /* + * remove port from all others ports PBVLAN map when they + * share the same bridge + */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + u32 reg; + + if (i == port) + continue; + + if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), br)) + continue; + + reg = sw_core_readl(priv, SF2_CORE_Px_VLAN_CTL(i)); + reg &= ~BIT(port); + sw_core_writel(priv, reg, SF2_CORE_Px_VLAN_CTL(i)); + } + + /* + * restore port pbvlan to its cpu port + */ + sw_core_writel(priv, + (1 << port) | + (1 << priv->ports[port].cfg.cpu_port), + SF2_CORE_Px_VLAN_CTL(port)); +} + +static void sf2_dsa_port_bridge_leave(struct dsa_switch *ds, int port, + struct dsa_bridge br) +{ + struct bcm_sf2_priv *priv = ds->priv; + u32 reg, new; + + pr_debug("sf2_dsa_port_bridge_leave: port:%d\n", port); + + sf2_dsa_port_leave_pxvlan(ds, port, &br); + + reg = sw_core_readl(priv, SF2_CORE_PCTL(port)); + new = reg & ~PCTL_STP_MASK; + new |= PCTL_STP_NONE; + sw_core_writel(priv, new, SF2_CORE_PCTL(port)); +} + +static void sf2_dsa_port_stp_state_set(struct dsa_switch *ds, int port_id, + u8 state) +{ + struct bcm_sf2_priv *priv = ds->priv; + const struct dsa_port *port = dsa_to_port(ds, port_id); + u32 hw_state; + u32 reg, new; + + if (!port->bridge) + return; + + switch (state) { + case BR_STATE_DISABLED: + hw_state = PCTL_STP_DISABLE; + break; + case BR_STATE_LISTENING: + hw_state = PCTL_STP_LISTEN; + break; + case BR_STATE_LEARNING: + hw_state = PCTL_STP_LEARN; + break; + case BR_STATE_FORWARDING: + hw_state = PCTL_STP_FORWARD; + break; + case BR_STATE_BLOCKING: + hw_state = PCTL_STP_BLOCKED; + break; + default: + dev_err(ds->dev, "invalid STP state: %d\n", state); + return; + } + + reg = sw_core_readl(priv, SF2_CORE_PCTL(port_id)); + new = reg & ~PCTL_STP_MASK; + new |= hw_state; + if (new == reg) + return; + + if (state != BR_STATE_FORWARDING) + sf2_dsa_port_leave_pxvlan(ds, port_id, port->bridge); + else + sf2_dsa_port_join_pxvlan(ds, port_id, port->bridge); + + dev_dbg(ds->dev, "Set STP state of port %d: %d\n", port_id, state); + sw_core_writel(priv, new, SF2_CORE_PCTL(port_id)); + sf2_arl_clear(priv); +} + +static int sf2_dsa_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid, + struct dsa_db db) +{ + struct bcm_sf2_priv *priv = ds->priv; + /* Force vlanid to 0 as there is no ARL vlan support */ + sf2_arl_delete(priv, addr, 0); + return 0; +} + +/* + * + */ +static int sf2_fdb_copy(int port, const struct sf2_arl_entry *ent, + dsa_fdb_dump_cb_t *cb, void *data) +{ + if (!ent->is_valid) + return 0; + + if (port != ent->port) + return 0; + + return cb(ent->mac, ent->vid, ent->is_static, data); +} + +/* + * + */ +static int sf2_dsa_change_mtu(struct dsa_switch *ds, int port, int mtu) +{ + return 0; +} + +/* + * + */ +static int sf2_dsa_get_max_mtu(struct dsa_switch *ds, int port) +{ + return ETH_MAX_MTU; +} + +/* + * + */ +static int sf2_dsa_set_mac_eee(struct dsa_switch *ds, int port_id, + struct ethtool_eee *e) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + /* record requested state, request to enable will be applied + * at link change through phylink callback (cannot access + * phylink eee_active from here) */ + port->tx_lpi_enabled = e->tx_lpi_enabled; + + if (!port->tx_lpi_enabled) + sf2_setup_port_eee(priv, port, false); + + /* update e->tx_lpi_timer in hw */ + sw_core_writel(priv, e->tx_lpi_timer, + SF2_CORE_Px_EEE_SLEEP_TMR_1G_REG(port_id)); + sw_core_writel(priv, e->tx_lpi_timer, + SF2_CORE_Px_EEE_SLEEP_TMR_100M_REG(port_id)); + + return 0; +} + +/* + * + */ +static int sf2_dsa_get_mac_eee(struct dsa_switch *ds, int port_id, + struct ethtool_eee *e) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + /* other eee_ fields are filled by dsa */ + e->tx_lpi_enabled = port->tx_lpi_enabled; + e->tx_lpi_timer = + sw_core_readl(priv, SF2_CORE_Px_EEE_SLEEP_TMR_1G_REG(port_id)); + return 0; +} + +/* + * + */ +static const struct dsa_switch_ops bcm_sf2_dsa_ops = { + .get_tag_protocol = sf2_dsa_get_tag_protocol, + .setup = sf2_dsa_setup, + .teardown = sf2_dsa_teardown, + .port_enable = sf2_dsa_port_setup, + .port_disable = sf2_dsa_port_disable, + .phylink_get_caps = sf2_dsa_phylink_get_caps, + .phylink_mac_config = sf2_dsa_phylink_mac_config, + .phylink_mac_an_restart = sf2_dsa_phylink_mac_an_restart, + .phylink_mac_link_down = sf2_dsa_phylink_mac_link_down, + .phylink_mac_link_up = sf2_dsa_phylink_mac_link_up, + .phylink_mac_link_state = sf2_dsa_phylink_mac_link_state, + .get_strings = sf2_dsa_get_strings, + .get_ethtool_stats = sf2_dsa_get_ethtool_stats, + .get_sset_count = sf2_dsa_get_sset_count, + .get_ethtool_phy_stats = sf2_dsa_get_ethtool_phy_stats, + .port_bridge_join = sf2_dsa_port_bridge_join, + .port_bridge_leave = sf2_dsa_port_bridge_leave, + .port_stp_state_set = sf2_dsa_port_stp_state_set, + .port_fdb_del = sf2_dsa_fdb_del, + .port_max_mtu = sf2_dsa_get_max_mtu, + .port_change_mtu = sf2_dsa_change_mtu, + .set_mac_eee = sf2_dsa_set_mac_eee, + .get_mac_eee = sf2_dsa_get_mac_eee, +}; + +/* + * + */ +static void fixup_xbar_config(struct bcm_sf2_priv *priv) +{ + int xbar_in_used[SF2_XBAR_OUT_PORT_COUNT]; + size_t i; + + memset(xbar_in_used, 0, sizeof (xbar_in_used)); + + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) { + if (priv->xbar_mapping[i] == -1) + continue; + + xbar_in_used[priv->xbar_mapping[i]] = 1; + } + + /* assign unused out port to something */ + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) { + size_t j; + + if (priv->xbar_mapping[i] != -1) + continue; + + for (j = 0; j < ARRAY_SIZE(xbar_in_used); j++) { + if (xbar_in_used[j]) + continue; + + priv->xbar_mapping[i] = j; + xbar_in_used[priv->xbar_mapping[i]] = 1; + break; + } + } +} + +/* + * + */ +static int of_read_sf2_config(struct platform_device *pdev, + struct bcm_sf2_priv *priv) +{ + struct sf2_config *config = &priv->config; + bool xbar_in_used[SF2_XBAR_IN_PORT_COUNT]; + struct device_node *ports_np, *port_np, *wan_port_np; + int i, ret; + u32 val; + + /* + * fill config from device tree + */ + memset(config, 0, sizeof (*config)); + + ret = of_property_read_u32(pdev->dev.of_node, + "sf2,qphy-base-id", + &config->qphy_base_id); + ret |= of_property_read_u32(pdev->dev.of_node, + "sf2,sphy-phy-id", + &config->sphy_phy_id); + ret |= of_property_read_u32(pdev->dev.of_node, + "sf2,serdes-phy-id", + &config->serdes_phy_id); + if (ret) { + dev_err(&pdev->dev, "missing phy id properties"); + return ret; + } + + wan_port_np = of_get_child_by_name(pdev->dev.of_node, + "sf2,wan-port-config"); + if (!wan_port_np) { + dev_err(&pdev->dev, "missing sf2,wan-port-config property"); + return -ENODEV; + } + + priv->wan_port.used = of_device_is_available(wan_port_np); + if (priv->wan_port.used) { + ret = of_property_read_u32(wan_port_np, "xbar-in-port", &val); + if (ret) { + dev_err(&pdev->dev, "missing xbar-in-port " + "property for wan port"); + return -ENODEV; + } + priv->wan_port.cfg.xbar_in_port = val; + } + + ports_np = of_get_child_by_name(pdev->dev.of_node, "ports"); + if (!ports_np) { + dev_err(&pdev->dev, "missing ports property"); + return -ENODEV; + } + + priv->leds_top_regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "leds-top"); + if (IS_ERR(priv->leds_top_regmap)) + return PTR_ERR(priv->leds_top_regmap); + + for_each_available_child_of_node(ports_np, port_np) { + struct sf2_port *port; + struct sf2_port_config *pcfg; + const struct sf2_port_hw_desc *pdesc; + u32 port_id; + + ret = of_property_read_u32(port_np, "reg", &port_id); + if (ret) + return ret; + + if (port_id >= SF2_PORT_COUNT) + return -EINVAL; + + port = &priv->ports[port_id]; + port->id = port_id; + pcfg = &port->cfg; + pcfg->cpu_port = -1; + + pdesc = &bcm63158_port_descs[port_id]; + + port->used = of_device_is_available(port_np); + if (!port->used) + continue; + + if (!of_property_read_u32(port_np, "sf2,led-link-act", &val)) + pcfg->led_link_act = val; + else + pcfg->led_link_act = -1; + + if (!of_property_read_u32(port_np, "sf2,cpu-port", &val)) { + if (val >= SF2_PORT_COUNT) { + dev_err(&pdev->dev, "bad sf2,cpu-port value " + "property for port %d", port_id); + return -EINVAL; + } + pcfg->cpu_port = val; + } + + switch (pdesc->port_type) { + case SF2_PORT_T_XBAR_4X3: + if (of_property_read_u32(port_np, "xbar-in-port", &val)) { + dev_err(&pdev->dev, "missing xbar-in-port " + "property for port %d", port_id); + return -ENODEV; + } + pcfg->xbar_in_port = val; + break; + + case SF2_PORT_T_XBAR_MUX1: + if (of_property_read_u32(port_np, "mux1-in-port", &val)) { + dev_err(&pdev->dev, "missing mux1-in-port " + "property for port %d", port_id); + return -ENODEV; + } + pcfg->mux1_in_port = val; + break; + + case SF2_PORT_T_XBAR_MUX2: + if (of_property_read_u32(port_np, "mux2-in-port", &val)) { + dev_err(&pdev->dev, "missing mux2-in-port " + "property for port %d", port_id); + return -ENODEV; + } + pcfg->mux2_in_port = val; + break; + + default: + break; + } + } + + /* + * check & compute various mappings from config + */ + priv->qphy_en_mask = 0; + priv->sphy_en_mask = 0; + priv->serdes_en_mask = 0; + memset(xbar_in_used, 0, sizeof (xbar_in_used)); + + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) + priv->xbar_mapping[i] = -1; + + /* first round to resolve real port */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + struct sf2_port *port = &priv->ports[i]; + const struct sf2_port_config *pcfg = &port->cfg; + const struct sf2_port_hw_desc *pdesc = &bcm63158_port_descs[i]; + + if (!port->used) + continue; + + port->tx_lpi_enabled = true; + switch (pdesc->port_type) { + case SF2_PORT_T_UNEXISTING: + dev_err(&pdev->dev, + "configured to use non-existing port %u\n", i); + return -EINVAL; + + case SF2_PORT_T_RGMII: + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + case SF2_PORT_T_QUAD_GPHY: + case SF2_PORT_T_SINGLE_GPHY: + case SF2_PORT_T_SERDES: + port->pdesc = pdesc; + break; + + case SF2_PORT_T_XBAR_MUX1: + { + int mux_in; + + mux_in = pcfg->mux1_in_port; + + if (mux_in < 0 || mux_in > 1) { + dev_err(&pdev->dev, + "port %d use non-existing " + "mux in port %u\n", i, mux_in); + return -EINVAL; + } + + priv->mux1_mapping = mux_in; + port->pdesc = &bcm63158_mux1_port_descs[mux_in]; + break; + } + + case SF2_PORT_T_XBAR_MUX2: + { + int mux_in; + + mux_in = pcfg->mux2_in_port; + + if (mux_in < 0 || mux_in > 1) { + dev_err(&pdev->dev, + "port %d use non-existing " + "mux in port %u\n", i, mux_in); + return -EINVAL; + } + + priv->mux2_mapping = mux_in; + port->pdesc = &bcm63158_mux2_port_descs[mux_in]; + break; + } + + case SF2_PORT_T_XBAR_4X3: + { + int xbar_in; + + xbar_in = pcfg->xbar_in_port; + if (xbar_in < 0 || + xbar_in >= ARRAY_SIZE(bcm63158_xbar_port_descs)) { + dev_err(&pdev->dev, + "port %d use non-existing " + "xbar in port %u\n", i, xbar_in); + return -EINVAL; + } + + if (xbar_in_used[xbar_in]) { + dev_err(&pdev->dev, + "port %d use already used " + "xbar in port %u\n", i, xbar_in); + return -EINVAL; + } + + priv->xbar_mapping[pdesc->xbar_out_port] = xbar_in; + port->pdesc = &bcm63158_xbar_port_descs[xbar_in]; + break; + } + } + } + + for (i = 0; i < SF2_PORT_COUNT; i++) { + struct sf2_port *port = &priv->ports[i]; + const struct sf2_port_hw_desc *pdesc = port->pdesc; + + if (!pdesc) + continue; + + switch (pdesc->port_type) { + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + break; + + case SF2_PORT_T_QUAD_GPHY: + WARN_ON(priv->qphy_en_mask & + (1 << pdesc->quad_gphy_port)); + priv->qphy_en_mask |= (1 << pdesc->quad_gphy_port); + break; + + case SF2_PORT_T_SINGLE_GPHY: + WARN_ON(priv->sphy_en_mask != 0); + priv->sphy_en_mask |= 1; + break; + + case SF2_PORT_T_SERDES: + WARN_ON(priv->serdes_en_mask != 0); + priv->serdes_en_mask |= 1; + break; + + default: + break; + } + } + + if (priv->wan_port.used) { + const struct sf2_port_hw_desc *xbar_in_pdesc; + int xbar_in; + + xbar_in = priv->wan_port.cfg.xbar_in_port; + if (xbar_in < 0 || + xbar_in >= ARRAY_SIZE(bcm63158_xbar_port_descs)) { + dev_err(&pdev->dev, + "wan port use non-existing " + "xbar in port %u\n", xbar_in); + return -EINVAL; + } + + if (xbar_in_used[xbar_in]) { + dev_err(&pdev->dev, + "wan port use already used " + "xbar in port %u\n", xbar_in); + return -EINVAL; + } + + priv->xbar_mapping[2] = xbar_in; + xbar_in_pdesc = &bcm63158_xbar_port_descs[xbar_in]; + priv->wan_port.pdesc = xbar_in_pdesc; + + switch (xbar_in_pdesc->port_type) { + case SF2_PORT_T_RGMII: + break; + + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + return -EINVAL; + + case SF2_PORT_T_QUAD_GPHY: + WARN_ON(priv->qphy_en_mask & + (1 << xbar_in_pdesc->quad_gphy_port)); + priv->qphy_en_mask |= + (1 << xbar_in_pdesc->quad_gphy_port); + break; + case SF2_PORT_T_SINGLE_GPHY: + WARN_ON(priv->sphy_en_mask != 0); + priv->sphy_en_mask |= 1; + break; + case SF2_PORT_T_SERDES: + WARN_ON(priv->serdes_en_mask != 0); + priv->serdes_en_mask |= 1; + break; + default: + WARN(1, "invalid hw desc"); + return -EINVAL; + } + } + + fixup_xbar_config(priv); + + return 0; +} + +/* + * + */ +static void dump_sf2_mapping(struct bcm_sf2_priv *priv) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) { + dev_dbg(&priv->pdev->dev, + "XBAR mapping: %s => %s\n", + bcm63158_xbar_in_port_names[priv->xbar_mapping[i]], + bcm63158_xbar_out_port_names[i]); + } + + dev_dbg(&priv->pdev->dev, + "MUX1 mapping: %s => %s\n", + mux1_in_port_names[priv->mux1_mapping], + mux1_out_port_name); + + dev_dbg(&priv->pdev->dev, + "MUX2 mapping: %s => %s\n", + mux2_in_port_names[priv->mux2_mapping], + mux2_out_port_name); +} + + +/* + * reserve & remap registers region + */ +static int remap_regs(struct bcm_sf2_priv *priv) +{ + static const char *regs_name[] = { + "core", + "reg", + "mdio", + "acb", + }; + struct platform_device *pdev = priv->pdev; + struct resource *res; + void *addr[ARRAY_SIZE(regs_name)]; + size_t i; + + for (i = 0; i < ARRAY_SIZE(regs_name); i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + regs_name[i]); + if (!res) { + dev_err(&pdev->dev, "unable to get %s register " + "resource.\n", regs_name[i]); + return -ENODEV; + } + + addr[i] = devm_ioremap_resource(&pdev->dev, res); + if (!addr[i]) { + dev_err(&pdev->dev, "unable to ioremap %s\n", + regs_name[i]); + return -ENOMEM; + } + } + + priv->regs_core = addr[0]; + priv->regs_reg = addr[1]; + priv->regs_mdio = addr[2]; + priv->regs_acb = addr[3]; + + return 0; +} + +/* + * + */ +static int bcm_sf2_probe(struct platform_device *pdev) +{ + struct bcm_sf2_priv *priv; + struct reset_control *rst; + struct mii_bus *bus; + struct dsa_switch *ds; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pdev = pdev; + + ret = of_read_sf2_config(pdev, priv); + if (ret) { + dev_err(&pdev->dev, "invalid device tree config\n"); + return ret; + } + + ret = remap_regs(priv); + if (ret) + return ret; + + rst = devm_reset_control_get(&pdev->dev, "sf2"); + if (IS_ERR(rst)) { + if (PTR_ERR(rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "missing sf2 reset control\n"); + return PTR_ERR(rst); + } + priv->rst = rst; + + priv->mii_bus = devm_mdiobus_alloc(&pdev->dev); + if (!priv->mii_bus) + return -ENOMEM; + + /* + * find mdio bus + */ + bus = priv->mii_bus; + bus->priv = priv; + bus->name = "bcm63158_sf2 MII bus"; + bus->parent = &pdev->dev; + bus->read = sf2_mii_read; + bus->read_c45 = sf2_mii_read_c45; + bus->write = sf2_mii_write; + bus->write_c45 = sf2_mii_write_c45; + bus->reset = sf2_mii_bus_reset; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio", pdev->name); + + priv->mdio_np = of_get_child_by_name(pdev->dev.of_node, "sf2,mdio"); + if (!priv->mdio_np) { + dev_err(&pdev->dev, "missing sf2,mdio node"); + return -ENODEV; + } + + ds = devm_kzalloc(&pdev->dev, sizeof (*ds), GFP_KERNEL); + if (!ds) + return -ENOMEM; + + ds->priv = priv; + ds->num_ports = SF2_PORT_COUNT; + ds->dev = &pdev->dev; + ds->ops = &bcm_sf2_dsa_ops; + priv->ds = ds; + + ret = dsa_register_switch(ds); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "dsa register switch failed: %d\n", + ret); + return ret; + } + + /* all set */ + dump_sf2_mapping(priv); + platform_set_drvdata(pdev, priv); + bcm_sf2_dbg_init(priv); + return 0; +} + +/* + * + */ +static int bcm_sf2_remove(struct platform_device *pdev) +{ + struct bcm_sf2_priv *priv; + + bcm_sf2_dbg_exit(); + priv = platform_get_drvdata(pdev); + dsa_unregister_switch(priv->ds); + platform_set_drvdata(pdev, NULL); + return 0; +} + +static const struct of_device_id bcm63158_sf2_of_match[] = { + { .compatible = "brcm,bcm63158-sf2" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, bcm63158_sf2_of_match); + +/* + * + */ +struct platform_driver bcm63158_sf2_driver = { + .probe = bcm_sf2_probe, + .remove = bcm_sf2_remove, + .driver = { + .name = "bcm63158_sf2", + .of_match_table = bcm63158_sf2_of_match, + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(bcm63158_sf2_driver); + +MODULE_DESCRIPTION("BCM63158 SF2 driver"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_LICENSE("GPL"); diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_priv.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_priv.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_priv.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_priv.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,275 @@ +#ifndef SF2_PRIV_H_ +#define SF2_PRIV_H_ + +#include +#include +#include +#include +#include + +/* + * hardware description of SF2 switch ports & crossbar for 63158 SOC + */ +#define SF2_PORT_COUNT 9 +#define SF2_XBAR_IN_PORT_COUNT 4 +#define SF2_XBAR_OUT_PORT_COUNT 3 +#define SF2_NUM_EGRESS_QUEUES 8 + +enum sf2_port_type { + SF2_PORT_T_UNEXISTING, + SF2_PORT_T_RGMII, + SF2_PORT_T_QUAD_GPHY, + SF2_PORT_T_SINGLE_GPHY, + SF2_PORT_T_SERDES, + SF2_PORT_T_UNIMAC, + SF2_PORT_T_SYSPORT, + + SF2_PORT_T_XBAR_4X3, + SF2_PORT_T_XBAR_MUX1, + SF2_PORT_T_XBAR_MUX2, +}; + +struct sf2_port_hw_desc { + enum sf2_port_type port_type; + int quad_gphy_port; + int xbar_out_port; + bool is_imp; +}; + +/* + * device tree extracted configuration + */ +struct sf2_port_config { + int xbar_in_port; + int mux1_in_port; + int mux2_in_port; + int cpu_port; + int led_link_act; +}; + +struct sf2_config { + /* base mdio address to use for QUAD gphy (will use id => id + 3) */ + unsigned int qphy_base_id; + + /* mdio address to use for single gphy */ + unsigned int sphy_phy_id; + + /* mdio address to use for serdes phy */ + unsigned int serdes_phy_id; + + /* use inverted logic for serdes signal detect */ + bool serdes_inv_sd; +}; + +struct sf2_port { + const struct sf2_port_hw_desc *pdesc; + unsigned int id; + struct sf2_port_config cfg; + bool used; + bool enabled; + bool tx_lpi_enabled; +}; + +struct sf2_switchdev_ev_work { + struct bcm_sf2_priv *priv; + struct net_device *dev; + struct work_struct work; + struct switchdev_notifier_fdb_info info; + atomic_t free; +}; + +#define SF2_SWITCHDEV_EVENT_POOL_SZ 32 +struct bcm_sf2_fdb { + struct workqueue_struct *poll_wq; + struct workqueue_struct *update_wq; + struct notifier_block switchdev_notifier; + struct delayed_work poll_wk; + DECLARE_HASHTABLE(arl_hash, 8); + struct list_head cache; + struct mutex lock; + struct sf2_switchdev_ev_work sd_ev[SF2_SWITCHDEV_EVENT_POOL_SZ]; + unsigned long poll_delay; + unsigned int nr_entries; +}; + +struct bcm_sf2_priv { + void __iomem *regs_core; + void __iomem *regs_reg; + void __iomem *regs_mdio; + void __iomem *regs_acb; + struct regmap *leds_top_regmap; + + struct platform_device *pdev; + struct reset_control *rst; + struct mii_bus *mii_bus; + struct device_node *mdio_np; + struct dsa_switch *ds; + + /* extract DT configuration */ + struct sf2_config config; + + /* logical state extracted from config */ + unsigned int qphy_en_mask; + unsigned int sphy_en_mask; + unsigned int serdes_en_mask; + int xbar_mapping[SF2_XBAR_OUT_PORT_COUNT]; + int mux1_mapping; + int mux2_mapping; + + struct sf2_port ports[SF2_PORT_COUNT]; + struct sf2_port wan_port; + + /* FDB book keeping */ + struct bcm_sf2_fdb fdb; +}; + +static inline u32 gen_port_mask(struct bcm_sf2_priv *priv, bool cpu) +{ + u32 mask; + int i; + + mask = 0; + for (i = 0; i < SF2_PORT_COUNT; i++) { + struct sf2_port *port = &priv->ports[i]; + + if (!port->used) + continue; + + switch (port->pdesc->port_type) { + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + if (cpu) + mask |= (1 << i); + break; + + default: + if (!cpu) + mask |= (1 << i); + break; + } + } + return mask; +} + +static inline u32 gen_cpu_port_mask(struct bcm_sf2_priv *priv) +{ + return gen_port_mask(priv, true); +} + +static inline u32 gen_lan_port_mask(struct bcm_sf2_priv *priv) +{ + return gen_port_mask(priv, false); +} + +/* + * FDB monitoring functions + */ +int sf2_fdb_init(struct bcm_sf2_priv *priv); +void sf2_fdb_exit(struct bcm_sf2_priv *priv); + +/* + * ARL functions + */ + +struct sf2_arl_entry { + u8 port; + u8 mac[ETH_ALEN]; + u16 vid; + u8 is_valid:1; + u8 is_age:1; + u8 is_static:1; +}; + +void +sf2_arl_for_each(struct bcm_sf2_priv *priv, + int (*fn)(struct bcm_sf2_priv *, const struct sf2_arl_entry *, + void *), + void *data); + +int sf2_arl_delete(struct bcm_sf2_priv *priv, const u8 *mac, u16 vid); + +/* + * register accessors + */ +static inline u16 sw_core_readw(struct bcm_sf2_priv *priv, u32 off) +{ + u16 val; + + val = ioread16(priv->regs_core + off); + return val; +} + +static inline u32 sw_core_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + + val = ioread32(priv->regs_core + off); + return val; +} + +static inline void sw_core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_core + off); +} + +static inline void sw_core_writell(struct bcm_sf2_priv *priv, u64 val, u32 off) +{ + iowrite64(val, priv->regs_core + off); +} + +static inline u64 sw_core_readll(struct bcm_sf2_priv *priv, u32 off) +{ + u64 val; + + val = ioread64(priv->regs_core + off); + return val; +} + +static inline u32 sw_reg_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + + val = ioread32(priv->regs_reg + off); + return val; +} + +static inline void sw_reg_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_reg + off); +} + + +static inline u32 sw_mdio_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + + val = ioread32(priv->regs_mdio + off); + return val; +} + +static inline void sw_mdio_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_mdio + off); +} + +static inline u32 sw_acb_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + val = ioread32(priv->regs_acb + off); + return val; +} + +static inline void sw_acb_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_acb + off); +} + +#ifdef CONFIG_DEBUG_FS +void bcm_sf2_dbg_init(struct bcm_sf2_priv *priv); +void bcm_sf2_dbg_exit(void); +#else +static inline void bcm_sf2_dbg_init(struct bcm_sf2_priv *priv) {} +static inline void bcm_sf2_dbg_exit(void) {} +#endif + +#endif diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_regs.h linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_regs.h --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_regs.h 2023-03-09 15:06:11.364234225 +0100 @@ -0,0 +1,338 @@ +#ifndef SF2_REGS_H_ +#define SF2_REGS_H_ + +/* + * apply to bcm63158 + */ + +/* ARL Table MAC/VID Entry N Registers (64 bit) + * + * BCM5325 and BCM5365 share most definitions below + */ +#define ARLTBL_MAC_MASK 0xffffffffffffULL +#define ARLTBL_VID_S 48 +#define ARLTBL_VID_MASK_25 0xff +#define ARLTBL_VID_MASK 0xfff +#define ARLTBL_DATA_PORT_ID_S_25 48 +#define ARLTBL_DATA_PORT_ID_MASK_25 0xf +#define ARLTBL_AGE_25 BIT(61) +#define ARLTBL_STATIC_25 BIT(62) +#define ARLTBL_VALID_25 BIT(63) + +/* ARL Table Data Entry N Registers (32 bit) */ +#define ARLTBL_DATA_PORT_ID_MASK 0x1ff +#define ARLTBL_TC(tc) ((3 & tc) << 11) +#define ARLTBL_AGE BIT(14) +#define ARLTBL_STATIC BIT(15) +#define ARLTBL_VALID BIT(16) + +/* + * CORE register block + */ + +/* + * control (page 0x0) + */ +#define SF2_CORE_PCTL(__p) (__p * 8) +# define PCTL_TXDIS (1 << 0) +# define PCTL_RXDIS (1 << 1) +# define PCTL_STP_NONE (0 << 5) +# define PCTL_STP_DISABLE (1 << 5) +# define PCTL_STP_BLOCKED (2 << 5) +# define PCTL_STP_LISTEN (3 << 5) +# define PCTL_STP_LEARN (4 << 5) +# define PCTL_STP_FORWARD (5 << 5) +# define PCTL_STP_MASK (7 << 5) + +#define SF2_CORE_IMP_CTL(__p) 0x40 +#define IMP_CTL_RX_BCAST_EN (1 << 2) +#define IMP_CTL_RX_MCAST_EN (1 << 3) +#define IMP_CTL_RX_UCAST_EN (1 << 4) + +#define SF2_CORE_SWMODE 0x58 +# define SWMODE_FWD_MANAGED (1 << 0) +# define SWMODE_FWD_EN (1 << 1) +# define SWMODE_RETRY_LIMIT_DIS (1 << 2) + +#define SF2_CORE_NEW_CTRL 0x108 +#define SF2_NEW_CTRL_MC_FWD_EN (1 << 7) +#define SF2_NEW_CTRL_UC_FWD_EN (1 << 6) + +#define SF2_CORE_CTRL 0x110 +# define SF2_CTRL_MII_DUMB_FWD_EN 0x40 +# define SF2_CTRL_MII2_VOL_SEL 0x02 + +#define SF2_CORE_UFL_FWD_MAP 0x190 + +#define SF2_CORE_MFL_FWD_MAP 0x1a0 + +#define SF2_CORE_IPMC_FWD_MAP 0x1b0 + +#define SF2_CORE_DIS_LEARN 0x1e0 + +#define SF2_CORE_WATCHDOG_CTRL 0x3c8 +# define SF2_SOFTWARE_RESET (1 << 7) +# define SF2_EN_CHIP_RST (1 << 6) +# define SF2_EN_SW_RST (1 << 4) + +/* + * management (page 0x2) + */ +#define SF2_CORE_BRCMTAG_CTRL 0x1018 +# define SF2_BRCMTAG_P8 (1 << 0) +# define SF2_BRCMTAG_P5 (1 << 1) +# define SF2_BRCMTAG_P7 (1 << 2) + +#define SF2_CORE_BRCMTAG2_CTRL 0x1050 +# define SF2_BRCMTAG2_Px(x) (1 << (x)) /* for P[012346] */ + +/* + * ARL access (page 0x5) + */ +#define SF2_CORE_ARL_RWCTL (0x2800) +# define SF2_ARL_START (1 << 7) +# define SF2_ARL_READ (1 << 0) + +#define SF2_CORE_ARL_MAC_IDX (0x2810) +#define SF2_CORE_ARL_VID_IDX (0x2840) + +#define SF2_CORE_ARL_MACENTRY(x) (0x2880 + (x) * 0x80) +#define SF2_CORE_ARL_FWDENTRY(x) (0x28c0 + (x) * 0x80) + +#define SF2_CORE_ARL_SRCH_CTRL 0x2a80 +#define ARL_SRCH_VLID BIT(0) +#define ARL_SRCH_STDN BIT(7) + +#define SF2_CORE_ARL_SRCH_ADR 0x2a88 + +#define SF2_CORE_ARL_SRCH_RSTx_MACVID(x) (0x2b00 + (x) * 0x80) + +#define SF2_CORE_ARL_SRCH_RSTx(x) (0x2b40 + (x) * 0x80) + +/* + * flow control (page 0x0a) + */ +#define SF2_CORE_FC_DIAG_CTRL (0x5000) +#define SF2_CORE_FC_QUEUE_CUR_COUNT(x) (SF2_CORE_FC_DIAG_CTRL + 0x30 * 8 + (x) * 16) +#define SF2_CORE_FC_QUEUE_PEAK_COUNT(x) (SF2_CORE_FC_DIAG_CTRL + 0x40 * 8 + (x) * 16) +#define SF2_CORE_FC_TOTAL_PEAK_COUNT (SF2_CORE_FC_DIAG_CTRL + 0x50 * 8) +#define SF2_CORE_FC_TOTAL_USED_COUNT (SF2_CORE_FC_DIAG_CTRL + 0x52 * 8) + +#define SF2_CORE_FC_PEAK_RX (SF2_CORE_FC_DIAG_CTRL + 0x54 * 8) + +/* + * lan threshold regs (page 0x0b) + */ +#define SF2_CORE_LAN_THRESH (0x5800) +#define LAN_THRESH_TXQ_RESERVED(q) (SF2_CORE_LAN_THRESH + 0x00 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_HYST(q) (SF2_CORE_LAN_THRESH + 0x10 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_PAUSE(q) (SF2_CORE_LAN_THRESH + 0x20 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_DROP(q) (SF2_CORE_LAN_THRESH + 0x30 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_TOT_HYST(q) (SF2_CORE_LAN_THRESH + 0x40 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_TOT_PAUSE(q) (SF2_CORE_LAN_THRESH + 0x50 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_TOT_DROP(q) (SF2_CORE_LAN_THRESH + 0x60 * 16 + (q) * 16) + +/* + * mib (page 0x20 => 0x28) + */ +#define SF2_CORE_Px_MIB(x) (0x10000 + (x) * 0x800) + +/* + * QOS (page 0x30) + */ +#define SF2_CORE_PORT_TC2_QOS_MAP_PORT(x) (0x18380 + (x) * 0x20) +#define PRT_TO_QID_SHIFT 3 + +/* + * port based vlan (page 0x31) + */ +#define SF2_CORE_Px_VLAN_CTL(x) (0x18800 + (x) * 0x10) + +#define SF2_CORE_JUMBO_PORT_MASK_REG 0x20008 +# define SF2_JUMBO_EN_10_100_MASK (1 << 24) +# define SF2_JUMBO_FM_PORT_MASK (0x1ff) + +#define SF2_CORE_MIB_GD_FM_MAX_SIZE 0x20028 +# define SF2_GDM_FM_MAX_SIZE_MASK (0x3fff << 0) + +#define SF2_CORE_SA_LIMIT_ENABLE 0x22800 +#define SF2_CORE_SA_LRN_CNTR_RST 0x22810 +# define SF2_CORE_TOTAL_SA_LRN_CNTR_RST_MASK (BIT(15)) +#define SF2_CORE_TOTAL_SA_LIMIT_CTL 0x22880 +#define SF2_CORE_SA_LIMIT_CTL_PORT(x) (0x22890 + (x) * 0x10) +#define SF2_CORE_TOTAL_SA_LRN_CNTR 0x22980 +#define SF2_CORE_SA_LRN_CNTR_PORT(x) (0x22990 + (x) * 0x10) + +/* + * EEE registers + */ +#define SF2_CORE_EEE_EN_CTRL_REG (0x49000) +#define SF2_CORE_Px_EEE_SLEEP_TMR_1G_REG(x) (0x49080 + (x) * 0x20) +#define SF2_CORE_Px_EEE_SLEEP_TMR_100M_REG(x) (0x491a0 + (x) * 0x20) + +/* for P0-P7 */ +#define SF2_CORE_STS_OV_Px_STATE(x) (0x72000 + (x) * 0x10) +# define STS_OV_Px_LINK_MASK (1 << 0) +# define STS_OV_Px_FULL_DUPLEX_MASK (1 << 1) +# define STS_OV_Px_SPEED_10_MASK (0x0 << 2) +# define STS_OV_Px_SPEED_100_MASK (0x1 << 2) +# define STS_OV_Px_SPEED_1000_MASK (0x2 << 2) +# define STS_OV_Px_SPEED_ALL_MASK (0x3 << 2) +# define STS_OV_Px_RX_FLOW_CTL_MASK (1 << 4) +# define STS_OV_Px_TX_FLOW_CTL_MASK (1 << 5) +# define STS_OV_Px_SW_OVER_MASK (1 << 6) + +/* for P8 only */ +#define SF2_CORE_STS_OV_IMP_STATE (0x72080) +# define STS_OV_IMP_LINK_MASK (1 << 0) +# define STS_OV_IMP_FULL_DUPLEX_MASK (1 << 1) +# define STS_OV_IMP_SPEED_10_MASK (0x0 << 2) +# define STS_OV_IMP_SPEED_100_MASK (0x1 << 2) +# define STS_OV_IMP_SPEED_1000_MASK (0x2 << 2) +# define STS_OV_IMP_SPEED_ALL_MASK (0x3 << 2) +# define STS_OV_IMP_RX_FLOW_CTL_MASK (1 << 4) +# define STS_OV_IMP_TX_FLOW_CTL_MASK (1 << 5) +# define STS_OV_IMP_MII_SW_OVER_MASK (1 << 7) + +/* + * REG register block. + */ +#define SF2_REG_SW_CTRL 0x0 +#define SW_CTRL_P5_SPEED_MASK (0x3 << 9) +#define SW_CTRL_P5_SPEED_1G (0x0 << 9) +#define SW_CTRL_P5_SPEED_2G (0x1 << 9) +#define SW_CTRL_P5_SPEED_2_5G (0x2 << 9) +#define SW_CTRL_P5_SPEED_3G (0x3 << 9) +#define SW_CTRL_P7_SPEED_MASK (0x3 << 5) +#define SW_CTRL_P7_SPEED_1G (0x0 << 5) +#define SW_CTRL_P7_SPEED_2G (0x1 << 5) +#define SW_CTRL_P7_SPEED_2_5G (0x2 << 5) +#define SW_CTRL_P7_SPEED_3G (0x3 << 5) +#define SW_CTRL_P8_SPEED_MASK (0x3 << 3) +#define SW_CTRL_P8_SPEED_1G (0x0 << 3) +#define SW_CTRL_P8_SPEED_2G (0x1 << 3) +#define SW_CTRL_P8_SPEED_2_5G (0x2 << 3) +#define SW_CTRL_P8_SPEED_3G (0x3 << 3) + +#define SF2_REG_PHY_TEST 0x18 + +#define SF2_REG_QPHY_CTRL 0x1c +# define QPHY_CTRL_IDDQ_BIAS (1 << 0) +# define QPHY_CTRL_EXT_PWR_DOWN_SHIFT 1 +# define QPHY_CTRL_EXT_PWR_DOWN(__p) (1 << ((__p) + 1)) +# define QPHY_CTRL_EXT_PWR_DOWN_ALL (0xf << QPHY_CTRL_EXT_PWR_DOWN_SHIFT) +# define QPHY_CTRL_FORCE_DLL_EN (1 << 5) +# define QPHY_CTRL_IDDQ_GLOBAL_PWR (1 << 6) +# define QPHY_CTRL_CLK_25_DISABLE (1 << 7) +# define QPHY_CTRL_PHY_RESET (1 << 8) +# define QPHY_CTRL_PHY_BASE_ADDR_SHIFT (12) +# define QPHY_CTRL_PHY_BASE_ADDR_MASK (0x1f << QPHY_CTRL_PHY_BASE_ADDR_SHIFT) + +#define SF2_REG_SPHY_CTRL 0x24 +# define SPHY_CTRL_IDDQ_BIAS (1 << 0) +# define SPHY_CTRL_EXT_PWR_DOWN (1 << 1) +# define SPHY_CTRL_FORCE_DLL_EN (1 << 2) +# define SPHY_CTRL_IDDQ_GLOBAL_PWR (1 << 3) +# define SPHY_CTRL_CLK_25_DISABLE (1 << 4) +# define SPHY_CTRL_PHY_RESET (1 << 5) +# define SPHY_CTRL_PHY_BASE_ADDR_SHIFT (8) +# define SPHY_CTRL_PHY_BASE_ADDR_MASK (0x1f << SPHY_CTRL_PHY_BASE_ADDR_SHIFT) + +#define SF2_REG_LED_CTRL(__p) (0x40 + 0xc * (__p)) +# define LED_CTRL_RX_ACT_EN (1 << 0) +# define LED_CTRL_TX_ACT_EN (1 << 1) +# define LED_CTRL_ACT_SEL (1 << 5) + +#define SF2_REG_XBAR_CTRL 0xcc + +enum { + E_XBAR_MUX_SERDES = 0x0, + E_XBAR_MUX_SGPHY = 0x1, + E_XBAR_MUX_RGMII1 = 0x2, + E_XBAR_MUX_RGMII2 = 0x3, + E_XBAR_MUX_QGPHY = 0x4, +}; + +#define XBAR_PORT_MASK 0x3 +#define XBAR_WAN_SHIFT 6 +#define XBAR_MUX2_MASK (1 << 5) +#define XBAR_MUX1_MASK (1 << 4) +#define XBAR_P6_SHIFT 2 +#define XBAR_P4_SHIFT 0 + + +#define SF2_REG_SSRD_CTRL 0x424 +# define SSRD_CTRL_IDDQ_EN (1 << 0) +# define SSRD_CTRL_PDOWN_EN (1 << 1) +# define SSRD_CTRL_RESET_PLL (1 << 3) +# define SSRD_CTRL_RESET_MDIO (1 << 4) +# define SSRD_CTRL_RESET_SERDES (1 << 5) +# define SSRD_CTRL_PHY_BASE_ADDR_SHIFT 8 +# define SSRD_CTRL_PHY_BASE_ADDR_MASK (0xf << SSRD_CTRL_PHY_BASE_ADDR_SHIFT) + + +#define SF2_REG_SSRD_STAT 0x428 +#define SSRD_STAT_LINK_UP (1 << 0) +#define SSRD_STAT_RX_SIGDET (1 << 1) +#define SSRD_STAT_RX_BITALIGN (1 << 2) +#define SSRD_STAT_RX_SGMII_MODE (1 << 3) +#define SSRD_STAT_RX_SYNC_STATUS (1 << 4) +#define SSRD_STAT_RX_PLL_LOCK (1 << 5) +#define SSRD_STAT_RX_DEBOUNCED_SIGDET (1 << 6) + + +#define SF2_REG_SSRD_APD_CTRL 0x42c +# define SSRD_APD_CTRL_INV_SD (1 << 3) + +/* + * MDIO block + */ +#define SF2_MDIO_CMD 0x0 + +# define CMD_BUSY (1 << 29) +# define CMD_LIFA (1 << 28) + +# define CMD_OPCODE_SHIFT 26 +# define CMD_OPCODE_MASK (3 << CMD_OPCODE_SHIFT) +# define OPCODE_C45_ADDR (0 << CMD_OPCODE_SHIFT) +# define OPCODE_C22_WRITE (1 << CMD_OPCODE_SHIFT) +# define OPCODE_C45_WRITE (1 << CMD_OPCODE_SHIFT) +# define OPCODE_C22_READ (2 << CMD_OPCODE_SHIFT) +# define OPCODE_C45_READ (3 << CMD_OPCODE_SHIFT) + +# define CMD_PHY_ADDR(__phy) ((__phy & 0x1f) << 21) +# define CMD_REG_ADDR(__reg) ((__reg & 0x1f) << 16) + +# define CMD_DATA(__data) ((__data & 0xffff) << 0) +# define CMD_REG_DATA_MASK 0xffff + +#define SF2_MDIO_CFG 0x4 +#define MDIO_CLAUSE_22_MASK (1 << 0) +#define MDIO_CLK_DIV_SHIFT 4 +#define MDIO_CLK_DIV_MASK (0xff << MDIO_CLK_DIV_SHIFT) + + +/* + * ACB block + */ +#define SF2_ACB_CONTROL_REG 0x0 +#define ACB_CONTROL_EN_MASK (1 << 0) +#define ACB_CONTROL_ALG2_MASK (1 << 1) +#define ACB_CONTROL_FLUSHQ_SHIFT 2 +#define ACB_CONTROL_FLUSHQ_MASK (0x7 << ACB_CONTROL_FLUSHQ_SHIFT) +#define ACB_CONTROL_EOP_DELAY_SHIFT 5 +#define ACB_CONTROL_EOP_DELAY_MASK (0xff << ACB_CONTROL_EOP_DELAY_SHIFT) + +#define SF2_ACB_XON_TRESH_REG 0x4 +#define XON_TRESH_XON_BUFS_SHIFT 0 +#define XON_TRESH_XON_BUFS_MASK (0x7ff << XON_TRESH_XON_BUFS_SHIFT) +#define XON_TRESH_TOTAL_XON_BUFS_SHIFT 11 +#define XON_TRESH_TOTAL_XON_BUFS_MASK (0x7ff << XON_TRESH_TOTAL_XON_BUFS_SHIFT) + +#define SF2_ACB_QCFG_REG(p,q) (0x8 + (p) * 8 * 4 + (q) * 4) +#define ACB_QCFG_XOFF_THRESH_SHIFT 0 +#define ACB_QCFG_XOFF_THRESH_MASK (0x7ff << ACB_QCFG_XOFF_THRESH_SHIFT) + +#define SF2_ACB_QINFLIGHT_REG(p,q) (0x108 + ((p) * 8 * 4) + (q) * 4) + +#endif /* !SF2_REGS_H_ */ diff -Nruw linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner./Makefile linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner/Makefile --- linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner/Makefile 2023-03-09 15:06:11.368234332 +0100 @@ -0,0 +1,5 @@ +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_enet_runner_mod.o +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_sf2.o + +bcm63xx_enet_runner_mod-y += bcm63xx_enet_runner.o +bcm63xx_enet_runner_mod-$(CONFIG_DEBUG_FS) += bcm63xx_enet_runner_debug.o diff -Nruw linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx./Kconfig linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx/Kconfig --- linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx/Kconfig 2023-12-21 17:30:06.441516398 +0100 @@ -0,0 +1,14 @@ +config IPQ95XX_ESS + tristate "IPQ95XX ESS driver (edma+ppe)" + select NET_SWITCHDEV + select PHYLINK + select MII + +config IPQ95XX_FBX_FF + bool "fastpath support for freebox boards" + depends on IPQ95XX_ESS + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE diff -Nruw linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx./Makefile linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx/Makefile --- linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/qualcomm/ipq95xx/Makefile 2024-01-04 16:55:44.208658048 +0100 @@ -0,0 +1,13 @@ +obj-$(CONFIG_IPQ95XX_ESS) += ipq95xx_ess.o + +ipq95xx_ess-objs += \ + clocks.o \ + debug.o \ + hwdesc.o \ + fdb.o \ + ipo.o \ + main.o \ + port.o \ + port_ethtool.o \ + port_phylink.o \ + uniphy.o diff -Nruw linux-6.4-fbx/drivers/net/ethernet/wintegra./Kconfig linux-6.4-fbx/drivers/net/ethernet/wintegra/Kconfig --- linux-6.4-fbx/drivers/net/ethernet/wintegra./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/wintegra/Kconfig 2023-03-09 15:06:11.368234332 +0100 @@ -0,0 +1,10 @@ +config NET_VENDOR_WINTEGRA + bool + +config WINTEGRA_WINPATH3_ETH + tristate "Wintegra Winpath3 internal mac support" + depends on WINTEGRA_WINPATH3 + select NET_VENDOR_WINTEGRA + select NET_CORE + select MII + select PHYLIB diff -Nruw linux-6.4-fbx/drivers/net/ethernet/wintegra./Makefile linux-6.4-fbx/drivers/net/ethernet/wintegra/Makefile --- linux-6.4-fbx/drivers/net/ethernet/wintegra./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/ethernet/wintegra/Makefile 2023-03-09 15:06:11.368234332 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_WINTEGRA_WINPATH3_ETH) += wp3_eth.o --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/phy/realtek-hwmon.c 2023-03-13 18:45:13.507496124 +0100 @@ -0,0 +1,138 @@ +/* + * realtek-hwmon.c for realtek-hwmon + * Created by on Mon Mar 8 17:05:09 2021 + */ + +#include +#include +#include +#include + +#include "realtek.h" + +#define RTL8221B_TSRR_REG 0xbd84 +#define RTL8221B_TSRR_TSOUT_SYNC_MASK (0x3ffL) +#define RTL8221B_TSRR_TSOUT_SYNC_SIGN (0x200) + +#if IS_REACHABLE(CONFIG_HWMON) + +static umode_t realtek_hwmon_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + if (type != hwmon_temp) + return 0; + + switch (attr) { + case hwmon_temp_input: + return 0444; + default: + return 0; + } +} + +static int realtek_hwmon_get(struct phy_device *phydev, long *value) +{ + int raw; + + raw = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL8221B_TSRR_REG); + if (raw < 0) + return raw; + + raw &= RTL8221B_TSRR_TSOUT_SYNC_MASK; + + if (raw & RTL8221B_TSRR_TSOUT_SYNC_SIGN) { + /* + * negative value: sign extend it. + */ + *value = raw | ~RTL8221B_TSRR_TSOUT_SYNC_MASK; + } else { + *value = raw; + } + + *value *= 500; + + return 0; +} + +static int realtek_hwmon_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *value) +{ + if (type != hwmon_temp) + return -ENOTSUPP; + + switch (attr) { + case hwmon_temp_input: + return realtek_hwmon_get(dev_get_drvdata(dev), value); + default: + return -ENOTSUPP; + } +} + +static const struct hwmon_ops realtek_hwmon_ops = { + .is_visible = realtek_hwmon_is_visible, + .read = realtek_hwmon_read, +}; + +static u32 realtek_hwmon_temp_config[] = { + HWMON_T_INPUT, + 0, +}; + +static const struct hwmon_channel_info realtek_hwmon_temp = { + .type = hwmon_temp, + .config = realtek_hwmon_temp_config, +}; + +static u32 realtek_hwmon_chip_config[] = { + HWMON_C_REGISTER_TZ, + 0, +}; + +static const struct hwmon_channel_info realtek_hwmon_chip = { + .type = hwmon_chip, + .config = realtek_hwmon_chip_config, +}; + + +static const struct hwmon_channel_info *realtek_hwmon_info[] = { + &realtek_hwmon_chip, + &realtek_hwmon_temp, + NULL, +}; + +static const struct hwmon_chip_info realtek_hwmon_chip_info = { + .ops = &realtek_hwmon_ops, + .info = realtek_hwmon_info, +}; + +int realtek_hwmon_probe(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + char *name; + int i, j; + struct device *hdev; + + name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); + if (!name) + return -ENOMEM; + + for (i = j = 0; name[i]; i++) { + if (isalnum(name[i]) || + name[i] == '.' || name[i] == ':') { + if (i != j) + name[j] = name[i]; + j++; + } + } + name[j] = '\0'; + + hdev = devm_hwmon_device_register_with_info(dev, + name, + phydev, + &realtek_hwmon_chip_info, + NULL); + + return PTR_ERR_OR_ZERO(hdev); +} +#endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/phy/realtek.h 2023-03-13 18:45:13.507496124 +0100 @@ -0,0 +1,19 @@ +/* + * realtek.h for realtek-hwmon + * Created by on Mon Mar 8 17:05:57 2021 + */ + +#pragma once + +#if IS_REACHABLE(CONFIG_HWMON) + +int realtek_hwmon_probe(struct phy_device *phydev); + +#else + +static inline int realtek_hwmon_probe(struct phy_device *phydev) +{ + return 0; +} + +#endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/ahb.h 2024-01-19 17:01:19.853846702 +0100 @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef ATH12K_AHB_H +#define ATH12K_AHB_H + +#include +#include +#include "core.h" +#include "debug.h" + +#define DT_NODE_RPROC_TEXTPD_NAME "d100000.remoteproc:remoteproc_pd4" +#define DT_NODE_RPROC_ROOTPD_NAME "d100000.remoteproc" + +#define ATH12K_AHB_RECOVERY_TIMEOUT (3 * HZ) + +#define ATH12K_AHB_SMP2P_SMEM_MSG GENMASK(15, 0) +#define ATH12K_AHB_SMP2P_SMEM_SEQ_NO GENMASK(31, 16) +#define ATH12K_AHB_SMP2P_SMEM_VALUE_MASK 0xFFFFFFFF +#define ATH12K_PCI_CE_WAKE_IRQ 2 +#define ATH12K_PCI_IRQ_CE0_OFFSET 3 + +enum ath12k_ahb_smp2p_msg_id { + ATH12K_AHB_POWER_SAVE_ENTER = 1, + ATH12K_AHB_POWER_SAVE_EXIT, +}; + +struct ath12k_base; + +struct ath12k_ahb { + struct rproc *tgt_rproc, *tgt_text_rproc, *tgt_rrproc; + struct { + struct device *dev; + struct iommu_domain *iommu_domain; + dma_addr_t msa_paddr; + u32 msa_size; + dma_addr_t ce_paddr; + u32 ce_size; + bool use_tz; + } fw; + struct { + unsigned short seq_no; + unsigned int smem_bit; + struct qcom_smem_state *smem_state; + } smp2p_info; +}; + +static inline struct ath12k_ahb *ath12k_ahb_priv(struct ath12k_base *ab) +{ + return (struct ath12k_ahb *)ab->drv_priv; +} +static inline int ath12k_rproc_register_subsys_notifier(struct ath12k_base *ab) +{ +#ifdef CONFIG_REMOTEPROC +/* + struct ath12k_ahb *ab_ahb = ath12k_ahb_priv(ab); + ab->ssr_atomic_upd_handle = qcom_register_ssr_atomic_notifier(ab_ahb->tgt_rproc->name, + &ab->atomic_ssr_nb); + if (!ab->ssr_atomic_upd_handle) { + ath12k_err(ab, "failed to register user_pd atomic handle\n"); + return -EINVAL; + } + + ab->ssr_upd_handle = qcom_register_ssr_notifier(ab_ahb->tgt_rproc->name, &ab->ssr_nb); + if (!ab->ssr_upd_handle) + return -EINVAL; + + if (ab->userpd_id == USERPD_0) { + ab->ssr_atomic_rpd_handle = qcom_register_ssr_atomic_notifier(ab_ahb->tgt_rrproc->name, + &ab->rpd_atomic_ssr_nb); + if (!ab->ssr_atomic_rpd_handle) { + ath12k_err(ab, "failed to register root_pd atomic handle\n"); + return -EINVAL; + } + ab->ssr_rpd_handle = qcom_register_ssr_notifier(ab_ahb->tgt_rrproc->name, + &ab->rpd_ssr_nb); + if (!ab->ssr_rpd_handle) + return -EINVAL; + } +*/ + return 0; +#else + return -ENODEV; +#endif +} +static inline int ath12k_rproc_unregister_subsys_notifier(struct ath12k_base *ab) +{ +#ifdef CONFIG_REMOTEPROC +/* + if (ab->ssr_upd_handle) + qcom_unregister_ssr_notifier(ab->ssr_upd_handle, &ab->ssr_nb); + if (ab->ssr_atomic_upd_handle) + qcom_unregister_ssr_atomic_notifier(ab->ssr_atomic_upd_handle, + &ab->atomic_ssr_nb); + if (ab->ssr_atomic_rpd_handle) + qcom_unregister_ssr_atomic_notifier(ab->ssr_atomic_rpd_handle, + &ab->rpd_atomic_ssr_nb); + if (ab->ssr_rpd_handle) + qcom_unregister_ssr_notifier(ab->ssr_rpd_handle, &ab->rpd_ssr_nb); +*/ + return 0; +#else + return -ENODEV; +#endif +} + +static const struct ath12k_bus_params ath12k_ahb_bus_params = { + .fixed_bdf_addr = false, + .fixed_mem_region = true, +}; + +static const struct ath12k_bus_params ath12k_internal_pci_bus_params = { + .fixed_bdf_addr = false, + .fixed_mem_region = true, +}; + +#endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/bondif.h 2024-03-18 14:40:14.843741115 +0100 @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __BONDIF_H +#define __BONDIF_H + +#define MAX_MLO_CHIPS 3 +#define MAX_PDEV_PER_SOC 3 + +#define ATH12K_PPE_DS_2G_CORE_MASK 0x1 +#define ATH12K_PPE_DS_5G_CORE_MASK 0x2 +#define ATH12K_PPE_DS_6G_CORE_MASK 0x4 +#define ATH12K_PPE_DS_DEFAULT_CORE_MASK 0x7 + +void ath12k_disable_ppe_for_link_netdev(struct ath12k_base *ab, + struct ath12k_link_vif *arvif, + struct net_device *link_dev); +void ath12k_enable_ppe_for_link_netdev(struct ath12k_base *ab, + struct ath12k_link_vif *arvif, + struct net_device *link_dev); +int ath12k_free_bonddev_for_sfe(struct wireless_dev *wdev, + struct ieee80211_vif *vif, + int link_num); +int ath12k_mac_op_set_multicast_to_unicast(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + const bool enabled); +int ath12k_bond_link_enslave(struct ath12k_link_vif *arvif, struct net_device *link_dev); +void ath12k_bond_link_release(struct ath12k_link_vif *arvif); +void ath12k_bond_enable_ppe_ds(void); +void ath12k_bond_disable_ppe_ds(void); +extern int g_bonded_interface_model; +extern unsigned int ath12k_ppe_ds_enabled; +extern unsigned int ath12k_mlo_capable; +int ath12k_bond_dev_cb(struct wireless_dev *wdev, struct net_device *dev, bool is_register); +extern int (*driver_bond_dev_cb)(struct wireless_dev *wdev, struct net_device *dev, bool is_register); +enum ath12k_bond_state { + ATH12K_BOND_SETUP_INPROGRESS, + ATH12K_BOND_REGISTERED, + ATH12K_BOND_LINK0_REGISTERED, + ATH12K_BOND_LINK1_REGISTERED, + ATH12K_BOND_LINK2_REGISTERED, + +}; +struct ath12k_mld_dev { + struct net_device *netdev; + struct ieee80211_vif *vif; + struct ath12k_vif *ahvif; + struct wireless_dev *wdev; //dummy one for bond registration. Optimize Bond MLO API. + struct net_device *link_dev[MAX_MLO_CHIPS][MAX_PDEV_PER_SOC]; + u8 primary_chipid, primary_pdevid; + bool mcast_dev_set; + bool mcast_to_ucast_en; + unsigned long bond_state; +}; + +#endif //__BONDIF_H --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/coredump.c 2024-03-18 14:40:14.843741115 +0100 @@ -0,0 +1,511 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "coredump.h" +#include "pci.h" +#include "mhi.h" +#include "debug.h" + +struct ath12k_coredump_segment_info ath12k_coredump_seg_info; +EXPORT_SYMBOL(ath12k_coredump_seg_info); +struct ath12k_coredump_info ath12k_coredump_ram_info; +EXPORT_SYMBOL(ath12k_coredump_ram_info); + +static void *ath12k_coredump_find_segment(loff_t user_offset, + struct ath12k_dump_segment *segment, + int num_seg, size_t *data_left) +{ + int i; + + for (i = 0; i < num_seg; i++, segment++) { + if (user_offset < segment->len) { + *data_left = user_offset; + return segment; + } + user_offset -= segment->len; + } + + *data_left = 0; + return NULL; +} + +static ssize_t ath12k_coredump_read_q6dump(char *buffer, loff_t offset, size_t count, + void *data, size_t header_size) +{ + struct ath12k_coredump_state *dump_state = data; + struct ath12k_dump_segment *segments = dump_state->segments; + struct ath12k_dump_segment *seg; + void *elfcore = dump_state->header; + size_t data_left, copy_size, bytes_left = count; + void __iomem *addr; + + /* Copy the header first */ + if (offset < header_size) { + copy_size = header_size - offset; + copy_size = min(copy_size, bytes_left); + + memcpy(buffer, elfcore + offset, copy_size); + offset += copy_size; + bytes_left -= copy_size; + buffer += copy_size; + + return copy_size; + } + + while (bytes_left) { + seg = ath12k_coredump_find_segment(offset - header_size, segments, + dump_state->num_seg, &data_left); + /* End of segments check */ + if (!seg) { + pr_info("Ramdump complete %lld bytes read\n", offset); + return 0; + } + + if (data_left) + copy_size = min_t(size_t, bytes_left, data_left); + else + copy_size = bytes_left; + + addr = (void __iomem *)seg->vaddr; + addr += data_left; + memcpy_fromio(buffer, addr, copy_size); + + offset += copy_size; + buffer += copy_size; + bytes_left -= copy_size; + } + + return count - bytes_left; +} + +static void ath12k_coredump_free_q6dump(void *data) +{ + struct ath12k_coredump_state *dump_state = data; + + complete(&dump_state->dump_done); +} + +void ath12k_coredump_build_inline(struct ath12k_base *ab, + struct ath12k_dump_segment *segments, int num_seg) +{ + struct ath12k_coredump_state dump_state; + struct timespec64 timestamp; + struct ath12k_dump_file_data *file_data; + size_t header_size; + struct ath12k_pci *ar_pci = (struct ath12k_pci *)ab->drv_priv; + struct device *dev; + u8 *buf; + + header_size = sizeof(*file_data); + header_size += num_seg * sizeof(*segments); + header_size = PAGE_ALIGN(header_size); + buf = kzalloc(header_size, GFP_ATOMIC); + if (!buf) { + ath12k_warn(ab, "Failed to allocate memory for coredump\n"); + return; + } + + file_data = (struct ath12k_dump_file_data *)buf; + strscpy(file_data->df_magic, "ATH12K-FW-DUMP", + sizeof(file_data->df_magic)); + file_data->len = cpu_to_le32(header_size); + file_data->version = cpu_to_le32(ATH12K_FW_CRASH_DUMP_V2); + if (ab->hif.bus == ATH12K_BUS_AHB || ab->hif.bus == ATH12K_BUS_HYBRID) { + file_data->chip_id = ab->qmi.target.chip_id; + file_data->qrtr_id = ab->qmi.service_ins_id; + file_data->bus_id = ab->userpd_id; + } else { + file_data->chip_id = cpu_to_le32(ar_pci->dev_id); + file_data->qrtr_id = cpu_to_le32(ar_pci->ab->qmi.service_ins_id); + file_data->bus_id = pci_domain_nr(ar_pci->pdev->bus); + } + dev = ab->dev; + guid_gen(&file_data->guid); + ktime_get_real_ts64(×tamp); + file_data->tv_sec = cpu_to_le64(timestamp.tv_sec); + file_data->tv_nsec = cpu_to_le64(timestamp.tv_nsec); + file_data->num_seg = cpu_to_le32(num_seg); + file_data->seg_size = cpu_to_le32(sizeof(*segments)); + + /* copy segment details to file */ + buf += offsetof(struct ath12k_dump_file_data, seg); + file_data->seg = (struct ath12k_dump_segment *)buf; + memcpy(file_data->seg, segments, num_seg * sizeof(*segments)); + + dump_state.header = file_data; + dump_state.num_seg = num_seg; + dump_state.segments = segments; + init_completion(&dump_state.dump_done); + + dev_coredumpm(dev, THIS_MODULE, &dump_state, header_size, GFP_KERNEL, + ath12k_coredump_read_q6dump, ath12k_coredump_free_q6dump); + + /* Wait until the dump is read and free is called */ + wait_for_completion(&dump_state.dump_done); + kfree(file_data); +} + +static enum ath12k_fw_crash_dump_type +ath12k_coredump_get_dump_type(u32 mem_region_type) +{ + enum ath12k_fw_crash_dump_type dump_type; + + /* note: only add the supported memory type, + which is used to calculate the rem_seg_cnt */ + switch(mem_region_type) { + case HOST_DDR_REGION_TYPE: + dump_type = ATH12K_FW_REMOTE_MEM_DATA; + break; + case CALDB_MEM_REGION_TYPE: + dump_type = ATH12K_FW_CALDB; + break; + case M3_DUMP_REGION_TYPE: + dump_type = ATH12K_FW_M3_DUMP; + break; + case PAGEABLE_MEM_REGION_TYPE: + dump_type = ATH12K_FW_PAGEABLE_DATA; + break; + case MLO_GLOBAL_MEM_REGION_TYPE: + dump_type = ATH12K_FW_MLO_GLOBAL; + break; + default: + dump_type = ATH12K_FW_DUMP_TYPE_MAX; + break; + } + + return dump_type; +} + +static void ath12k_coredump_q6crash_reason(struct ath12k_base *ab) +{ + int i = 0; + uint64_t coredump_offset = 0; + struct ath12k_pci *ar_pci = (struct ath12k_pci *)ab->drv_priv; + struct mhi_controller *mhi_ctrl = ar_pci->mhi_ctrl; + struct mhi_buf *mhi_buf; + struct image_info *rddm_image; + struct ath12k_coredump_q6ramdump_header *ramdump_header; + struct ath12k_coredump_q6ramdump_entry *ramdump_table; + char *msg = NULL; + struct pci_dev *pci_dev = ar_pci->pdev; + + rddm_image = mhi_ctrl->rddm_image; + mhi_buf = rddm_image->mhi_buf; + + ath12k_info(ab, "CRASHED - [DID:DOMAIN:BUS:SLOT] - %x:%04u:%02u:%02u\n", + pci_dev->device, pci_dev->bus->domain_nr, + pci_dev->bus->number, PCI_SLOT(pci_dev->devfn)); + + /* Get RDDM header size */ + ramdump_header = (struct ath12k_coredump_q6ramdump_header *)mhi_buf[0].buf; + ramdump_table = ramdump_header->ramdump_table; + coredump_offset = le32_to_cpu(ramdump_header->header_size); + + /* Traverse ramdump table to get coredump offset */ + while (i < MAX_RAMDUMP_TABLE_SIZE) { + if (!strncmp(ramdump_table->description, COREDUMP_DESC, + sizeof(COREDUMP_DESC)) || + !strncmp(ramdump_table->description, Q6_SFR_DESC, + sizeof(Q6_SFR_DESC))) { + break; + } + coredump_offset += le64_to_cpu(ramdump_table->size); + ramdump_table++; + i++; + } + + if (i == MAX_RAMDUMP_TABLE_SIZE) { + ath12k_warn(ab, "Cannot find '%s' entry in ramdump\n", + COREDUMP_DESC); + return; + } + + /* Locate coredump data from the ramdump segments */ + for (i = 0; i < rddm_image->entries; i++) { + if (coredump_offset < mhi_buf[i].len) { + msg = mhi_buf[i].buf + coredump_offset; + break; + } + + coredump_offset -= mhi_buf[i].len; + } + + if (msg && msg[0]) + ath12k_err(ab, "Fatal error received from wcss!\n%s\n", + msg); +} + +void ath12k_coredump_download_rddm(struct ath12k_base *ab) +{ + struct ath12k_pci *ar_pci = (struct ath12k_pci *)ab->drv_priv; + struct mhi_controller *mhi_ctrl = ar_pci->mhi_ctrl; + struct image_info *rddm_img, *fw_img; + struct ath12k_dump_segment *segment, *seg_info; + int i, rem_seg_cnt = 0, len, num_seg, seg_sz, qdss_seg_cnt = 1; + int skip_count = 0; + enum ath12k_fw_crash_dump_type mem_type; + struct ath12k_coredump_segment_info *chip_seg; + int dump_count; + struct ath12k_hw_group *ag = ab->ag; + bool state = false; + + if (ab->in_panic) + state = true; + + ath12k_mhi_coredump(mhi_ctrl, state); + ath12k_coredump_q6crash_reason(ab); + + rddm_img = mhi_ctrl->rddm_image; + fw_img = mhi_ctrl->fbc_image; + + for (i = 0; i < ab->qmi.mem_seg_count; i++) { + if (ab->qmi.target_mem[i].type == HOST_DDR_REGION_TYPE || + (ab->qmi.target_mem[i].type == CALDB_MEM_REGION_TYPE && ath12k_cold_boot_cal && ab->hw_params->cold_boot_calib) || + ab->qmi.target_mem[i].type == M3_DUMP_REGION_TYPE || + ab->qmi.target_mem[i].type == PAGEABLE_MEM_REGION_TYPE || + ab->qmi.target_mem[i].type == MLO_GLOBAL_MEM_REGION_TYPE) + rem_seg_cnt++; + } + + num_seg = fw_img->entries + rddm_img->entries + rem_seg_cnt; + if (ab->is_qdss_tracing) + num_seg += qdss_seg_cnt; + + len = num_seg * sizeof(*segment); + + segment = kzalloc(len, GFP_NOWAIT); + if (!segment) { + ath12k_err(ab, " Failed to allocate memory for segment for rddm download\n"); + return; + } + + seg_info = segment; + for (i = 0; i < fw_img->entries ; i++) { + if (!fw_img->mhi_buf[i].buf) { + skip_count++; + continue; + } + seg_sz = fw_img->mhi_buf[i].len; + seg_info->len = PAGE_ALIGN(seg_sz); + seg_info->addr = fw_img->mhi_buf[i].dma_addr; + seg_info->vaddr = fw_img->mhi_buf[i].buf; + seg_info->type = ATH12K_FW_CRASH_PAGING_DATA; + seg_info++; + } + + for (i = 0; i < rddm_img->entries; i++) { + if (!rddm_img->mhi_buf[i].buf) { + skip_count++; + continue; + } + seg_sz = rddm_img->mhi_buf[i].len; + seg_info->len = PAGE_ALIGN(seg_sz); + seg_info->addr = rddm_img->mhi_buf[i].dma_addr; + seg_info->vaddr = rddm_img->mhi_buf[i].buf; + seg_info->type = ATH12K_FW_CRASH_RDDM_DATA; + seg_info++; + } + + for (i = 0; i < ab->qmi.mem_seg_count; i++) { + mem_type = ath12k_coredump_get_dump_type(ab->qmi.target_mem[i].type); + if(mem_type == ATH12K_FW_DUMP_TYPE_MAX) { + ath12k_info(ab, "target mem region type %d not supported", ab->qmi.target_mem[i].type); + continue; + } + + if (mem_type == ATH12K_FW_CALDB && + !(ath12k_cold_boot_cal && ab->hw_params->cold_boot_calib)) + continue; + + if (!ab->qmi.target_mem[i].paddr) { + skip_count++; + ath12k_info(ab, "Skipping mem region type %d", ab->qmi.target_mem[i].type); + continue; + } + + seg_info->len = ab->qmi.target_mem[i].size; + seg_info->addr = ab->qmi.target_mem[i].paddr; + seg_info->vaddr = ab->qmi.target_mem[i].v.ioaddr; + seg_info->type = mem_type; + ath12k_info(ab, + "seg vaddr is %px len is 0x%x type %d\n", + seg_info->vaddr, + seg_info->len, + seg_info->type); + seg_info++; + } + + if (ab->is_qdss_tracing) { + seg_info->len = ab->qmi.qdss_mem[0].size; + seg_info->addr = ab->qmi.qdss_mem[0].paddr; + seg_info->vaddr = ab->qmi.qdss_mem[0].v.ioaddr; + seg_info->type = ATH12K_FW_QDSS_DATA; + seg_info++; + } + + num_seg = num_seg - skip_count; + + if (!ab->fw_recovery_support || ab->in_panic) { + if (ag->mlo_capable) { + dump_count = atomic_read(&ath12k_coredump_ram_info.num_chip); + if (dump_count >= ATH12K_MAX_SOCS) { + ath12k_err(ab, "invalid chip number %d\n", + dump_count); + return; + } else { + chip_seg = &ath12k_coredump_ram_info.chip_seg_info[dump_count]; + chip_seg->chip_id = ar_pci->dev_id; + chip_seg->qrtr_id = ar_pci->ab->qmi.service_ins_id; + chip_seg->bus_id = pci_domain_nr(ar_pci->pdev->bus); + chip_seg->num_seg = num_seg; + chip_seg->seg = segment; + atomic_inc(&ath12k_coredump_ram_info.num_chip); + } + } else { + /* This part of code for 12.2 without mlo_capable=1 */ + dump_count = atomic_read(&ath12k_coredump_ram_info.num_chip); + chip_seg = &ath12k_coredump_ram_info.chip_seg_info[dump_count]; + chip_seg->chip_id = ar_pci->dev_id; + chip_seg->qrtr_id = ar_pci->ab->qmi.service_ins_id; + chip_seg->bus_id = pci_domain_nr(ar_pci->pdev->bus); + chip_seg->num_seg = num_seg; + chip_seg->seg = segment; + atomic_inc(&ath12k_coredump_ram_info.num_chip); + } + + chip_seg = &ath12k_coredump_seg_info; + chip_seg->chip_id = ar_pci->dev_id; + chip_seg->qrtr_id = ar_pci->ab->qmi.service_ins_id; + chip_seg->bus_id = pci_domain_nr(ar_pci->pdev->bus); + chip_seg->num_seg = num_seg; + chip_seg->seg = segment; + + ath12k_core_issue_bug_on(ab); + + } else if (!ab->in_panic) { + ath12k_info(ab, "WLAN target is restarting"); + ath12k_coredump_build_inline(ab, segment, num_seg); + kfree(segment); + } + +} + +void ath12k_coredump_qdss_dump(struct ath12k_base *ab, + struct ath12k_qmi_event_qdss_trace_save_data *event_data) +{ + struct ath12k_dump_segment *segment; + int len, num_seg; + void *dump; + + num_seg = event_data->mem_seg_len; + len = sizeof(*segment); + segment = vzalloc(len); + if (!segment) { + ath12k_warn(ab, "fail to alloc memory for qdss\n"); + return; + } + + if (event_data->total_size && + event_data->total_size <= ab->qmi.qdss_mem[0].size) + dump = vzalloc(event_data->total_size); + if (!dump) { + vfree(segment); + return; + } + + if (num_seg == 1) { + segment->len = event_data->mem_seg[0].size; + segment->vaddr = ab->qmi.qdss_mem[0].v.ioaddr; + ath12k_dbg(ab, ATH12K_DBG_QMI, "seg vaddr is 0x%p len is 0x%x\n", + segment->vaddr, segment->len); + segment->type = ATH12K_FW_QDSS_DATA; + } else if (num_seg == 2) { + /*FW sends 2 segments with segment 0 and segment 1 */ + + if (event_data->mem_seg[1].addr != ab->qmi.qdss_mem[0].paddr) { + ath12k_warn(ab, "Invalid seg 0 addr 0x%llx\n", + event_data->mem_seg[1].addr); + goto out; + } + if (event_data->mem_seg[0].size + event_data->mem_seg[1].size != + ab->qmi.qdss_mem[0].size) { + ath12k_warn(ab, "Invalid total size 0x%x 0x%x\n", + event_data->mem_seg[0].size, + event_data->mem_seg[1].size); + goto out; + } + + ath12k_dbg(ab, ATH12K_DBG_QMI, "qdss mem seg0 addr 0x%llx size 0x%x\n", + event_data->mem_seg[0].addr, event_data->mem_seg[0].size); + ath12k_dbg(ab, ATH12K_DBG_QMI, "qdss mem seg1 addr 0x%llx size 0x%x\n", + event_data->mem_seg[1].addr, event_data->mem_seg[1].size); + + memcpy(dump, + ab->qmi.qdss_mem[0].v.ioaddr + event_data->mem_seg[1].size, + event_data->mem_seg[0].size); + memcpy(dump + event_data->mem_seg[0].size, + ab->qmi.qdss_mem[0].v.ioaddr, event_data->mem_seg[1].size); + + segment->len = event_data->mem_seg[0].size + event_data->mem_seg[1].size; + segment->vaddr = dump; + ath12k_dbg(ab, ATH12K_DBG_QMI, "seg vaddr is 0x%p and len is 0x%x\n", + segment->vaddr, segment->len); + segment->type = ATH12K_FW_QDSS_DATA; + } + ath12k_coredump_build_inline(ab, segment, 1); +out: + vfree(segment); + vfree(dump); +} + +void ath12k_coredump_m3_dump(struct ath12k_base *ab, + struct ath12k_qmi_m3_dump_upload_req_data *event_data) +{ + struct target_mem_chunk *target_mem = ab->qmi.target_mem; + struct ath12k_qmi_m3_dump_data m3_dump_data; + void *dump; + int i, ret = 0; + + dump = vzalloc(event_data->size); + if (!dump) { + return; + } + + for (i = 0; i < ab->qmi.mem_seg_count; i++) { + if (target_mem[i].paddr == event_data->addr && + event_data->size <= target_mem[i].size) + break; + } + + if (i == ab->qmi.mem_seg_count) { + ath12k_warn(ab, "qmi invalid paddr from firmware for M3 dump\n"); + ret = -EINVAL; + vfree(dump); + goto send_resp; + } + + m3_dump_data.addr = target_mem[i].v.ioaddr; + m3_dump_data.size = event_data->size; + m3_dump_data.pdev_id = event_data->pdev_id; + m3_dump_data.timestamp = ktime_to_ms(ktime_get()); + + memcpy(dump, m3_dump_data.addr, m3_dump_data.size); + + dev_coredumpv(ab->dev, dump, m3_dump_data.size, + GFP_KERNEL); + +send_resp: + ret = ath12k_qmi_m3_dump_upload_done_ind_send(ab, event_data->pdev_id, ret); + if (ret < 0) + ath12k_warn(ab, "qmi M3 dump upload done failed\n"); +} \ No newline at end of file --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/coredump.h 2024-01-19 17:01:19.853846702 +0100 @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef _COREDUMP_H_ +#define _COREDUMP_H_ + +#define ATH12K_FW_CRASH_DUMP_VERSION 1 +#define ATH12K_FW_CRASH_DUMP_V2 2 + +#define MAX_RAMDUMP_TABLE_SIZE 6 +#define COREDUMP_DESC "Q6-COREDUMP" +#define Q6_SFR_DESC "Q6-SFR" + +#define DESC_STRING_SIZE 20 +#define FILE_NAME_STRING_SIZE 20 + + +enum ath12k_fw_crash_dump_type { + ATH12K_FW_CRASH_PAGING_DATA, + ATH12K_FW_CRASH_RDDM_DATA, + ATH12K_FW_REMOTE_MEM_DATA, + ATH12K_FW_PAGEABLE_DATA, + ATH12K_FW_M3_DUMP, + ATH12K_FW_QDSS_DATA, + ATH12K_FW_CALDB, + ATH12K_FW_AFC, + ATH12K_FW_MLO_GLOBAL, + + /* keep last */ + ATH12K_FW_DUMP_TYPE_MAX, +}; + +struct ath12k_dump_segment { + unsigned long addr; + void *vaddr; + unsigned int len; + unsigned int type; +}; + +struct ath12k_dump_file_data { + /* "ATH12K-FW-DUMP" */ + char df_magic[16]; + __le32 len; + /* file dump version */ + __le32 version; + /* pci device id */ + __le32 chip_id; + /* qrtr instance id */ + __le32 qrtr_id; + /* pci domain id */ + u8 bus_id; + guid_t guid; + /* time-of-day stamp */ + __le64 tv_sec; + /* time-of-day stamp, nano-seconds */ + __le64 tv_nsec; + /* room for growth w/out changing binary format */ + u8 unused[8]; + /* number of segments */ + __le32 num_seg; + /* ath12k_dump_segment struct size */ + __le32 seg_size; + + struct ath12k_dump_segment *seg; + /* struct ath12k_dump_segment + more */ + + u8 data[0]; +} __packed; + +struct ath12k_coredump_state { + struct ath12k_dump_file_data *header; + struct ath12k_dump_segment *segments; + struct completion dump_done; + u32 num_seg; +}; + +struct ath12k_coredump_segment_info { + u32 chip_id; + u32 qrtr_id; + u32 num_seg; + struct ath12k_dump_segment *seg; + u8 bus_id; +}; + +struct ath12k_coredump_info { + atomic_t num_chip; + struct ath12k_coredump_segment_info chip_seg_info[ATH12K_MAX_SOCS]; +}; + +struct ath12k_coredump_q6ramdump_entry { + __le64 base_address; + __le64 actual_phys_address; + __le64 size; + char description[DESC_STRING_SIZE]; + char file_name[FILE_NAME_STRING_SIZE]; +}; + +struct ath12k_coredump_q6ramdump_header { + __le32 version; + __le32 header_size; + struct ath12k_coredump_q6ramdump_entry ramdump_table[MAX_RAMDUMP_TABLE_SIZE]; +}; + +#ifdef CONFIG_WANT_DEV_COREDUMP +void ath12k_coredump_download_rddm(struct ath12k_base *ab); +void ath12k_coredump_build_inline(struct ath12k_base *ab, + struct ath12k_dump_segment *segments, int num_seg); +void ath12k_coredump_qdss_dump(struct ath12k_base *ab, + struct ath12k_qmi_event_qdss_trace_save_data *event_data); +void ath12k_coredump_m3_dump(struct ath12k_base *ab, + struct ath12k_qmi_m3_dump_upload_req_data *event_data); +#else +static inline void ath12k_coredump_download_rddm(struct ath12k_base *ab) +{ +} + +static inline void ath12k_coredump_build_inline(struct ath12k_base *ab, + struct ath12k_dump_segment *segments, + int num_seg) +{ +} +static inline void +ath12k_coredump_qdss_dump(struct ath12k_base *ab, + struct ath12k_qmi_event_qdss_trace_save_data *event_data) +{ +} +static inline void +ath12k_coredump_m3_dump(struct ath12k_base *ab, + struct ath12k_qmi_m3_dump_upload_req_data *event_data) +{ +} +#endif + +#endif + --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debugfs.c 2024-03-18 14:40:14.843741115 +0100 @@ -0,0 +1,5326 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#include "debugfs.h" + +#include "core.h" +#include "debug.h" +#include "wmi.h" +#include "hal_rx.h" +#include "dp_tx.h" +#include "debugfs_htt_stats.h" +#include "peer.h" +#include "qmi.h" + +static struct dentry *debugfs_ath12k; + +static const char *htt_bp_umac_ring[HTT_SW_UMAC_RING_IDX_MAX] = { + "REO2SW1_RING", + "REO2SW2_RING", + "REO2SW3_RING", + "REO2SW4_RING", + "WBM2REO_LINK_RING", + "REO2TCL_RING", + "REO2FW_RING", + "RELEASE_RING", + "PPE_RELEASE_RING", + "TCL2TQM_RING", + "TQM_RELEASE_RING", + "REO_RELEASE_RING", + "WBM2SW0_RELEASE_RING", + "WBM2SW1_RELEASE_RING", + "WBM2SW2_RELEASE_RING", + "WBM2SW3_RELEASE_RING", + "REO_CMD_RING", + "REO_STATUS_RING", +}; + +static const char *htt_bp_lmac_ring[HTT_SW_LMAC_RING_IDX_MAX] = { + "FW2RXDMA_BUF_RING", + "FW2RXDMA_STATUS_RING", + "FW2RXDMA_LINK_RING", + "SW2RXDMA_BUF_RING", + "WBM2RXDMA_LINK_RING", + "RXDMA2FW_RING", + "RXDMA2SW_RING", + "RXDMA2RELEASE_RING", + "RXDMA2REO_RING", + "MONITOR_STATUS_RING", + "MONITOR_BUF_RING", + "MONITOR_DESC_RING", + "MONITOR_DEST_RING", +}; + +static void ath12k_debugfs_fw_stats_reset(struct ath12k *ar) +{ + spin_lock_bh(&ar->data_lock); + ar->fw_stats_done = false; + ath12k_fw_stats_reset(ar); + spin_unlock_bh(&ar->data_lock); +} + +void ath12k_debugfs_fw_stats_process(struct ath12k *ar, + struct ath12k_fw_stats *stats) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_pdev *pdev; + bool is_end; + static unsigned int num_vdev, num_bcn; + size_t total_vdevs_started = 0; + + int i; + if (stats->stats_id == WMI_REQUEST_VDEV_STAT) { + if (list_empty(&stats->vdevs)) { + ath12k_warn(ab, "empty vdev stats"); + return; + } + /* FW sends all the active VDEV stats irrespective of PDEV, + * hence limit until the count of all VDEVs started + */ + for (i = 0; i < ab->num_radios; i++) { + pdev = rcu_dereference(ab->pdevs_active[i]); + if (pdev && pdev->ar) + total_vdevs_started += ar->num_started_vdevs; + } + + is_end = ((++num_vdev) == total_vdevs_started); + + list_splice_tail_init(&stats->vdevs, + &ar->fw_stats.vdevs); + + if (is_end) { + ar->fw_stats_done = true; + num_vdev = 0; + } + return; + } + + if (stats->stats_id == WMI_REQUEST_BCN_STAT) { + if (list_empty(&stats->bcn)) { + ath12k_warn(ab, "empty bcn stats"); + return; + } + /* Mark end until we reached the count of all started VDEVs + * within the PDEV + */ + is_end = ((++num_bcn) == ar->num_started_vdevs); + + list_splice_tail_init(&stats->bcn, + &ar->fw_stats.bcn); + + if (is_end) { + ar->fw_stats_done = true; + num_bcn = 0; + } + } +} + +static ssize_t ath12k_write_wmi_ctrl_path_stats(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + struct wmi_ctrl_path_stats_cmd_param param = {0}; + u8 buf[128] = {0}; + int ret; + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (ret < 0) + return ret; + + buf[ret] = '\0'; + + ret = sscanf(buf, "%u %u", ¶m.stats_id, ¶m.action); + if (ret != 2) + return -EINVAL; + + if (!param.action || param.action > WMI_REQUEST_CTRL_PATH_STAT_RESET) + return -EINVAL; + + ret = ath12k_wmi_send_wmi_ctrl_stats_cmd(ar, ¶m); + return ret ? ret : count; +} + +int wmi_ctrl_path_pdev_stat(struct ath12k *ar, char __user *ubuf, + size_t count, loff_t *ppos) +{ + const int size = 2048; + char *buf; + u8 i; + int len = 0, ret_val; + u16 index_tx = 0; + u16 index_rx = 0; + char fw_tx_mgmt_subtype[WMI_MAX_STRING_LEN] = {0}; + char fw_rx_mgmt_subtype[WMI_MAX_STRING_LEN] = {0}; + struct wmi_ctrl_path_stats_list *stats; + struct wmi_ctrl_path_pdev_stats *pdev_stats; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + list_for_each_entry(stats, &ar->debug.wmi_list, list) { + if (!stats) + break; + + pdev_stats = stats->stats_ptr; + + if (!pdev_stats) + break; + + for (i = 0; i < WMI_MGMT_FRAME_SUBTYPE_MAX; i++) { + index_tx += snprintf(&fw_tx_mgmt_subtype[index_tx], + WMI_MAX_STRING_LEN - index_tx, + " %u:%u,", i, + pdev_stats->tx_mgmt_subtype[i]); + index_rx += snprintf(&fw_rx_mgmt_subtype[index_rx], + WMI_MAX_STRING_LEN - index_rx, + " %u:%u,", i, + pdev_stats->rx_mgmt_subtype[i]); + } + + len += scnprintf(buf + len, size - len, + "WMI_CTRL_PATH_PDEV_TX_STATS:\n"); + len += scnprintf(buf + len, size - len, + "fw_tx_mgmt_subtype = %s\n", + fw_tx_mgmt_subtype); + len += scnprintf(buf + len, size - len, + "fw_rx_mgmt_subtype = %s\n", + fw_rx_mgmt_subtype); + len += scnprintf(buf + len, size - len, + "scan_fail_dfs_violation_time_ms = %u\n", + pdev_stats->scan_fail_dfs_violation_time_ms); + len += scnprintf(buf + len, size - len, + "nol_chk_fail_last_chan_freq = %u\n", + pdev_stats->nol_chk_fail_last_chan_freq); + len += scnprintf(buf + len, size - len, + "nol_chk_fail_time_stamp_ms = %u\n", + pdev_stats->nol_chk_fail_time_stamp_ms); + len += scnprintf(buf + len, size - len, + "tot_peer_create_cnt = %u\n", + pdev_stats->tot_peer_create_cnt); + len += scnprintf(buf + len, size - len, + "tot_peer_del_cnt = %u\n", + pdev_stats->tot_peer_del_cnt); + len += scnprintf(buf + len, size - len, + "tot_peer_del_resp_cnt = %u\n", + pdev_stats->tot_peer_del_resp_cnt); + len += scnprintf(buf + len, size - len, + "vdev_pause_fail_rt_to_sched_algo_fifo_full_cnt = %u\n", + pdev_stats->vdev_pause_fail_rt_to_sched_algo_fifo_full_cnt); + } + + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ret_val = simple_read_from_buffer(ubuf, count, ppos, buf, len); + kfree(buf); + return ret_val; +} + +int wmi_ctrl_path_cal_stat(struct ath12k *ar, char __user *ubuf, + size_t count, loff_t *ppos) +{ + const int size = 4096; + char *buf; + u8 cal_type_mask, cal_prof_mask, is_periodic_cal; + int len = 0, ret_val; + struct wmi_ctrl_path_stats_list *stats; + struct wmi_ctrl_path_cal_stats *cal_stats; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + len += scnprintf(buf + len, size - len, + "WMI_CTRL_PATH_CAL_STATS\n"); + len += scnprintf(buf + len, size - len, + "%-25s %-25s %-17s %-16s %-16s %-16s\n", + "cal_profile", "cal_type", + "cal_triggered_cnt", "cal_fail_cnt", + "cal_fcs_cnt", "cal_fcs_fail_cnt"); + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + list_for_each_entry(stats, &ar->debug.wmi_list, list) { + if (!stats) + break; + + cal_stats = stats->stats_ptr; + + if (!cal_stats) + break; + + cal_prof_mask = FIELD_GET(WMI_CTRL_PATH_CAL_PROF_MASK, + cal_stats->cal_info); + if (cal_prof_mask == WMI_CTRL_PATH_STATS_CAL_PROFILE_INVALID) + continue; + + cal_type_mask = FIELD_GET(WMI_CTRL_PATH_CAL_TYPE_MASK, + cal_stats->cal_info); + is_periodic_cal = FIELD_GET(WMI_CTRL_PATH_IS_PERIODIC_CAL, + cal_stats->cal_info); + + + if (!is_periodic_cal) { + len += scnprintf(buf + len, size - len, + "%-25s %-25s %-17d %-16d %-16d %-16d\n", + wmi_ctrl_path_cal_prof_id_to_name(cal_prof_mask), + wmi_ctrl_path_cal_type_id_to_name(cal_type_mask), + cal_stats->cal_triggered_cnt, + cal_stats->cal_fail_cnt, + cal_stats->cal_fcs_cnt, + cal_stats->cal_fcs_fail_cnt); + } else { + len += scnprintf(buf + len, size - len, + "%-25s %-25s %-17d %-16d %-16d %-16d\n", + "PERIODIC_CAL", + wmi_ctrl_path_periodic_cal_type_id_to_name(cal_type_mask), + cal_stats->cal_triggered_cnt, + cal_stats->cal_fail_cnt, + cal_stats->cal_fcs_cnt, + cal_stats->cal_fcs_fail_cnt); + } + + } + + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ret_val = simple_read_from_buffer(ubuf, count, ppos, buf, len); + kfree(buf); + return ret_val; +} + +int wmi_ctrl_path_awgn_stat(struct ath12k *ar, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct wmi_ctrl_path_stats_list *stats; + struct wmi_ctrl_path_awgn_stats *awgn_stats; + const int size = 2048; + int len = 0, ret_val; + char *buf; + + buf = kzalloc(size, GFP_KERNEL); + + if (!buf) + return -ENOMEM; + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + + list_for_each_entry(stats, &ar->debug.wmi_list, list) { + + if (!stats) + break; + awgn_stats = stats->stats_ptr; + + if (!awgn_stats) + break; + + len += scnprintf(buf + len, size - len, + "WMI_CTRL_PATH_AWGN_STATS_TLV:\n"); + len += scnprintf(buf + len, size - len, + "awgn_send_evt_cnt = %u\n", + awgn_stats->awgn_send_evt_cnt); + len += scnprintf(buf + len, size - len, + "awgn_pri_int_cnt = %u\n", + awgn_stats->awgn_pri_int_cnt); + len += scnprintf(buf + len, size - len, + "awgn_sec_int_cnt = %u\n", + awgn_stats->awgn_sec_int_cnt); + len += scnprintf(buf + len, size - len, + "awgn_pkt_drop_trigger_cnt = %u\n", + awgn_stats->awgn_pkt_drop_trigger_cnt); + len += scnprintf(buf + len, size - len, + "awgn_pkt_drop_trigger_reset_cnt = %u\n", + awgn_stats->awgn_pkt_drop_trigger_reset_cnt); + len += scnprintf(buf + len, size - len, + "awgn_bw_drop_cnt = %u\n", + awgn_stats->awgn_bw_drop_cnt); + len += scnprintf(buf + len, size - len, + "awgn_bw_drop_reset_cnt = %u\n", + awgn_stats->awgn_bw_drop_reset_cnt); + len += scnprintf(buf + len, size - len, + "awgn_cca_int_cnt = %u\n", + awgn_stats->awgn_cca_int_cnt); + len += scnprintf(buf + len, size - len, + "awgn_cca_int_reset_cnt = %u\n", + awgn_stats->awgn_cca_int_reset_cnt); + len += scnprintf(buf + len, size - len, + "awgn_cca_ack_blk_cnt = %u\n", + awgn_stats->awgn_cca_ack_blk_cnt); + len += scnprintf(buf + len, size - len, + "awgn_cca_ack_reset_cnt = %u\n", + awgn_stats->awgn_cca_ack_reset_cnt); + len += scnprintf(buf + len, size - len, + "awgn_int_bw_cnt-AWGN_20[0]: %u\n", + awgn_stats->awgn_int_bw_cnt[0]); + len += scnprintf(buf + len, size - len, + "AWGN_40[1]: %u\n", + awgn_stats->awgn_int_bw_cnt[1]); + len += scnprintf(buf + len, size - len, + "AWGN_80[2]: %u\n", + awgn_stats->awgn_int_bw_cnt[2]); + len += scnprintf(buf + len, size - len, + "AWGN_160[3]: %u\n", + awgn_stats->awgn_int_bw_cnt[3]); + len += scnprintf(buf + len, size - len, + "AWGN_320[5]: %u\n", + awgn_stats->awgn_int_bw_cnt[5]); + } + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ret_val = simple_read_from_buffer(ubuf, count, ppos, buf, len); + kfree(buf); + + return ret_val; +} + +int wmi_ctrl_path_btcoex_stat(struct ath12k *ar, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct wmi_ctrl_path_stats_list *stats; + struct wmi_ctrl_path_btcoex_stats *btcoex_stats; + const int size = 2048; + int len = 0, ret_val; + char *buf; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + mutex_lock(&ar->wmi_ctrl_path_stats_lock); + list_for_each_entry(stats, &ar->debug.wmi_list, list) { + if (!stats) + break; + + btcoex_stats = stats->stats_ptr; + + if (!btcoex_stats) + break; + + len += scnprintf(buf + len, size - len, + "WMI_CTRL_PATH_BTCOEX_STATS:\n"); + len += scnprintf(buf + len, size - len, + "pdev_id = %u\n", + btcoex_stats->pdev_id); + len += scnprintf(buf + len, size - len, + "bt_tx_req_cntr = %u\n", + btcoex_stats->bt_tx_req_cntr); + len += scnprintf(buf + len, size - len, + "bt_rx_req_cntr = %u\n", + btcoex_stats->bt_rx_req_cntr); + len += scnprintf(buf + len, size - len, + "bt_req_nack_cntr = %u\n", + btcoex_stats->bt_req_nack_cntr); + len += scnprintf(buf + len, size - len, + "wl_tx_req_nack_schd_bt_reason_cntr = %u\n", + btcoex_stats->wl_tx_req_nack_schd_bt_reason_cntr); + len += scnprintf(buf + len, size - len, + "wl_tx_req_nack_current_bt_reason_cntr = %u\n", + btcoex_stats->wl_tx_req_nack_current_bt_reason_cntr); + len += scnprintf(buf + len, size - len, + "wl_tx_req_nack_other_wlan_tx_reason_cntr = %u\n", + btcoex_stats->wl_tx_req_nack_other_wlan_tx_reason_cntr); + len += scnprintf(buf + len, size - len, + "wl_in_tx_abort_cntr = %u\n", + btcoex_stats->wl_in_tx_abort_cntr); + len += scnprintf(buf + len, size - len, + "wl_tx_auto_resp_req_cntr = %u\n", + btcoex_stats->wl_tx_auto_resp_req_cntr); + len += scnprintf(buf + len, size - len, + "wl_tx_req_ack_cntr = %u\n", + btcoex_stats->wl_tx_req_ack_cntr); + len += scnprintf(buf + len, size - len, + "wl_tx_req_cntr = %u\n", + btcoex_stats->wl_tx_req_cntr); + } + + ath12k_wmi_crl_path_stats_list_free(ar, &ar->debug.wmi_list); + mutex_unlock(&ar->wmi_ctrl_path_stats_lock); + ret_val = simple_read_from_buffer(ubuf, count, ppos, buf, len); + kfree(buf); + return ret_val; +} + +static ssize_t ath12k_read_wmi_ctrl_path_stats(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int ret_val = 0; + u32 tagid = 0; + + tagid = ar->debug.wmi_ctrl_path_stats_tagid; + + switch (tagid) { + case WMI_CTRL_PATH_PDEV_STATS: + ret_val = wmi_ctrl_path_pdev_stat(ar, ubuf, count, ppos); + break; + case WMI_CTRL_PATH_CAL_STATS: + ret_val = wmi_ctrl_path_cal_stat(ar, ubuf, count, ppos); + break; + case WMI_CTRL_PATH_BTCOEX_STATS: + ret_val = wmi_ctrl_path_btcoex_stat(ar, ubuf, count, ppos); + break; + case WMI_CTRL_PATH_AWGN_STATS: + ret_val = wmi_ctrl_path_awgn_stat(ar, ubuf, count, ppos); + break; + /* Add case for newly wmi ctrl path added stats here */ + default: + /* Unsupported tag */ + ret_val = -EINVAL; + break; + } + + return ret_val; +} + +static const struct file_operations ath12k_fops_wmi_ctrl_stats = { + .write = ath12k_write_wmi_ctrl_path_stats, + .open = simple_open, + .read = ath12k_read_wmi_ctrl_path_stats, +}; + +void ath12k_debugfs_wmi_ctrl_stats(struct ath12k *ar) +{ + + ar->wmi_ctrl_stat = debugfs_create_file("wmi_ctrl_stats", 0644, + ar->debug.debugfs_pdev, + ar, + &ath12k_fops_wmi_ctrl_stats); + + INIT_LIST_HEAD(&ar->debug.wmi_list); + mutex_init(&ar->wmi_ctrl_path_stats_lock); + init_completion(&ar->debug.wmi_ctrl_path_stats_rcvd); +} + +static int ath12k_debugfs_fw_stats_request(struct ath12k *ar, + struct stats_request_params *req_param) +{ + struct ath12k_base *ab = ar->ab; + unsigned long timeout, time_left; + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + /* FW stats can get split when exceeding the stats data buffer limit. + * In that case, since there is no end marking for the back-to-back + * received 'update stats' event, we keep a 3 seconds timeout in case, + * fw_stats_done is not marked yet + */ + timeout = jiffies + msecs_to_jiffies(3 * HZ); + + ath12k_debugfs_fw_stats_reset(ar); + + reinit_completion(&ar->fw_stats_complete); + + ret = ath12k_wmi_send_stats_request_cmd(ar, req_param->stats_id, + req_param->vdev_id, req_param->pdev_id); + + if (ret) { + ath12k_warn(ab, "could not request fw stats (%d)\n", + ret); + return ret; + } + + time_left = + wait_for_completion_timeout(&ar->fw_stats_complete, + 1 * HZ); + if (!time_left) + return -ETIMEDOUT; + + for (;;) { + if (time_after(jiffies, timeout)) + break; + + spin_lock_bh(&ar->data_lock); + if (ar->fw_stats_done) { + spin_unlock_bh(&ar->data_lock); + break; + } + spin_unlock_bh(&ar->data_lock); + } + return 0; +} + +static int ath12k_open_pdev_stats(struct inode *inode, struct file *file) +{ + struct ath12k *ar = inode->i_private; + struct ath12k_base *ab = ar->ab; + struct stats_request_params req_param; + void *buf = NULL; + int ret; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto err_unlock; + } + + buf = vmalloc(ATH12K_FW_STATS_BUF_SIZE); + if (!buf) { + ret = -ENOMEM; + goto err_unlock; + } + + req_param.pdev_id = ar->pdev->pdev_id; + req_param.vdev_id = 0; + req_param.stats_id = WMI_REQUEST_PDEV_STAT; + + ret = ath12k_debugfs_fw_stats_request(ar, &req_param); + if (ret) { + ath12k_warn(ab, "failed to request fw pdev stats: %d\n", ret); + goto err_free; + } + + ath12k_wmi_fw_stats_fill(ar, &ar->fw_stats, req_param.stats_id, + buf); + + file->private_data = buf; + + mutex_unlock(&ar->conf_mutex); + return 0; + +err_free: + vfree(buf); + +err_unlock: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static int ath12k_release_pdev_stats(struct inode *inode, struct file *file) +{ + vfree(file->private_data); + + return 0; +} + +static ssize_t ath12k_read_pdev_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + const char *buf = file->private_data; + size_t len = strlen(buf); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_pdev_stats = { + .open = ath12k_open_pdev_stats, + .release = ath12k_release_pdev_stats, + .read = ath12k_read_pdev_stats, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static int ath12k_open_vdev_stats(struct inode *inode, struct file *file) +{ + struct ath12k *ar = inode->i_private; + struct stats_request_params req_param; + void *buf = NULL; + int ret; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto err_unlock; + } + + buf = vmalloc(ATH12K_FW_STATS_BUF_SIZE); + if (!buf) { + ret = -ENOMEM; + goto err_unlock; + } + + req_param.pdev_id = ar->pdev->pdev_id; + /* VDEV stats is always sent for all active VDEVs from FW */ + req_param.vdev_id = 0; + req_param.stats_id = WMI_REQUEST_VDEV_STAT; + + ret = ath12k_debugfs_fw_stats_request(ar, &req_param); + if (ret) { + ath12k_warn(ar->ab, "failed to request fw vdev stats: %d\n", ret); + goto err_free; + } + + ath12k_wmi_fw_stats_fill(ar, &ar->fw_stats, req_param.stats_id, + buf); + + file->private_data = buf; + + mutex_unlock(&ar->conf_mutex); + return 0; + +err_free: + vfree(buf); + +err_unlock: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static int ath12k_release_vdev_stats(struct inode *inode, struct file *file) +{ + vfree(file->private_data); + + return 0; +} + +static ssize_t ath12k_read_vdev_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + const char *buf = file->private_data; + size_t len = strlen(buf); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_vdev_stats = { + .open = ath12k_open_vdev_stats, + .release = ath12k_release_vdev_stats, + .read = ath12k_read_vdev_stats, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static int ath12k_open_bcn_stats(struct inode *inode, struct file *file) +{ + struct ath12k *ar = inode->i_private; + struct ath12k_link_vif *arvif; + struct stats_request_params req_param; + void *buf = NULL; + int ret; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto err_unlock; + } + + buf = vmalloc(ATH12K_FW_STATS_BUF_SIZE); + if (!buf) { + ret = -ENOMEM; + goto err_unlock; + } + + req_param.stats_id = WMI_REQUEST_BCN_STAT; + req_param.pdev_id = ar->pdev->pdev_id; + + /* loop all active VDEVs for bcn stats */ + list_for_each_entry(arvif, &ar->arvifs, list) { + if (!arvif->is_up) + continue; + + req_param.vdev_id = arvif->vdev_id; + ret = ath12k_debugfs_fw_stats_request(ar, &req_param); + if (ret) { + ath12k_warn(ar->ab, "failed to request fw bcn stats: %d\n", ret); + goto err_free; + } + } + + ath12k_wmi_fw_stats_fill(ar, &ar->fw_stats, req_param.stats_id, + buf); + + /* since beacon stats request is looped for all active VDEVs, saved fw + * stats is not freed for each request until done for all active VDEVs + */ + spin_lock_bh(&ar->data_lock); + ath12k_fw_stats_bcn_free(&ar->fw_stats.bcn); + spin_unlock_bh(&ar->data_lock); + + file->private_data = buf; + + mutex_unlock(&ar->conf_mutex); + return 0; + +err_free: + vfree(buf); + +err_unlock: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static int ath12k_release_bcn_stats(struct inode *inode, struct file *file) +{ + vfree(file->private_data); + + return 0; +} + +static ssize_t ath12k_read_bcn_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + const char *buf = file->private_data; + size_t len = strlen(buf); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_bcn_stats = { + .open = ath12k_open_bcn_stats, + .release = ath12k_release_bcn_stats, + .read = ath12k_read_bcn_stats, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_write_enable_vdev_stats_offload(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + bool enable; + int ret; + + if (kstrtobool_from_user(ubuf, count, &enable)) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (enable == ar->fw_stats.en_vdev_stats_ol) { + ret = count; + goto out; + } + + ar->fw_stats.en_vdev_stats_ol = enable; + ret = count; + +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath12k_read_enable_vdev_stats_offload(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) + +{ + char buf[32] = {0}; + struct ath12k *ar = file->private_data; + int len = 0; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%u\n", + ar->fw_stats.en_vdev_stats_ol); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_vdev_stats_offload = { + .read = ath12k_read_enable_vdev_stats_offload, + .write = ath12k_write_enable_vdev_stats_offload, + .open = simple_open +}; + +static ssize_t ath12k_debug_fw_reset_stats_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + int ret; + size_t len = 0, buf_len = 500; + char *buf; + + buf = kmalloc(buf_len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + spin_lock_bh(&ab->base_lock); + len += scnprintf(buf + len, buf_len - len, + "fw_crash_counter\t\t%d\n", ab->stats.fw_crash_counter); + len += scnprintf(buf + len, buf_len - len, + "last_recovery_time\t\t%d\n", ab->stats.last_recovery_time); + spin_unlock_bh(&ab->base_lock); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + + kfree(buf); + + return ret; +} + +static const struct file_operations fops_fw_reset_stats = { + .open = simple_open, + .read = ath12k_debug_fw_reset_stats_read, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_read_simulate_fw_crash(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + const char buf[] = + "To simulate firmware crash write one of the keywords to this file:\n" + "`assert` - this will send WMI_FORCE_FW_HANG_CMDID to firmware to cause assert.\n" + "`hw-restart` - this will simply queue hw restart without fw/hw actually crashing.\n"; + + return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf)); +} + +/* Simulate firmware crash: + * 'soft': Call wmi command causing firmware hang. This firmware hang is + * recoverable by warm firmware reset. + * 'hard': Force firmware crash by setting any vdev parameter for not allowed + * vdev id. This is hard firmware crash because it is recoverable only by cold + * firmware reset. + */ +static ssize_t ath12k_write_simulate_fw_crash(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_pdev *pdev; + struct ath12k *ar = ab->pdevs[0].ar; + char buf[32] = {0}; + ssize_t rc; + int i, ret, radioup = 0; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + if (ar && ar->state == ATH12K_STATE_ON) { + radioup = 1; + break; + } + } + /* filter partial writes and invalid commands */ + if (*ppos != 0 || count >= sizeof(buf) || count == 0) + return -EINVAL; + + rc = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count); + if (rc < 0) + return rc; + + /* drop the possible '\n' from the end */ + if (buf[*ppos - 1] == '\n') + buf[*ppos - 1] = '\0'; + + if (radioup == 0) { + ret = -ENETDOWN; + goto exit; + } + + if (!strcmp(buf, "assert")) { + ath12k_info(ab, "simulating firmware assert crash\n"); + ret = ath12k_wmi_force_fw_hang_cmd(ar, + ATH12K_WMI_FW_HANG_ASSERT_TYPE, + ATH12K_WMI_FW_HANG_DELAY, false); + } else { + ret = -EINVAL; + goto exit; + } + + if (ret) { + ath12k_warn(ab, "failed to simulate firmware crash: %d\n", ret); + goto exit; + } + + ret = count; + +exit: + return ret; +} + +static const struct file_operations fops_simulate_fw_crash = { + .read = ath12k_read_simulate_fw_crash, + .write = ath12k_write_simulate_fw_crash, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_write_enable_extd_tx_stats(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u32 filter; + int ret; + + if (kstrtouint_from_user(ubuf, count, 0, &filter)) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto out; + } + + if (filter == ar->debug.extd_tx_stats) { + ret = count; + goto out; + } + + ar->debug.extd_tx_stats = filter; + ret = count; + +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath12k_read_enable_extd_tx_stats(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) + +{ + char buf[32] = {0}; + struct ath12k *ar = file->private_data; + int len = 0; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%08x\n", + ar->debug.extd_tx_stats); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_extd_tx_stats = { + .read = ath12k_read_enable_extd_tx_stats, + .write = ath12k_write_enable_extd_tx_stats, + .open = simple_open +}; + +static ssize_t ath12k_write_extd_rx_stats(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + struct htt_rx_ring_tlv_filter tlv_filter = {0}; + u32 enable, ring_id, rx_filter = 0; + int ret, i; + + if (kstrtouint_from_user(ubuf, count, 0, &enable)) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto exit; + } + + if (enable > 1) { + ret = -EINVAL; + goto exit; + } + + if (enable == ar->debug.extd_rx_stats) { + ret = count; + goto exit; + } + + if (enable) { + rx_filter = HTT_RX_FILTER_TLV_FLAGS_MPDU_START; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_START; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_END; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO; + + tlv_filter.rx_filter = rx_filter; + tlv_filter.pkt_filter_flags0 = HTT_RX_FP_MGMT_FILTER_FLAGS0; + tlv_filter.pkt_filter_flags1 = HTT_RX_FP_MGMT_FILTER_FLAGS1; + tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_FILTER_FLASG2; + tlv_filter.pkt_filter_flags3 = HTT_RX_FP_CTRL_FILTER_FLASG3 | + HTT_RX_FP_DATA_FILTER_FLASG3; + } else { + tlv_filter = ath12k_mac_mon_status_filter_default; + } + + ar->debug.rx_filter = tlv_filter.rx_filter; + tlv_filter.offset_valid = false; + + for (i = 0; i < ar->ab->hw_params->num_rxmda_per_pdev; i++) { + ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; + ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, ar->dp.mac_id + i, + HAL_RXDMA_MONITOR_DST, + DP_RXDMA_REFILL_RING_SIZE, + &tlv_filter); + if (ret) { + ath12k_warn(ar->ab, "failed to set rx filter for monitor status ring\n"); + goto exit; + } + } + + ar->debug.extd_rx_stats = enable; + ret = count; +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath12k_read_extd_rx_stats(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[32]; + int len = 0; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%d\n", + ar->debug.extd_rx_stats); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_extd_rx_stats = { + .read = ath12k_read_extd_rx_stats, + .write = ath12k_write_extd_rx_stats, + .open = simple_open, +}; + +static int ath12k_reset_nrp_filter(struct ath12k *ar, + bool reset) +{ + int i = 0; + int ret = 0; + u32 ring_id = 0; + u32 rx_filter = 0; + struct htt_rx_ring_tlv_filter tlv_filter = {0}; + + if (!reset) { + rx_filter = ar->debug.rx_filter; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_MPDU_START; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_START; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_PPDU_END; + rx_filter |= HTT_RX_FILTER_TLV_FLAGS_MPDU_END; + + tlv_filter.rx_filter = rx_filter; + tlv_filter.pkt_filter_flags0 = HTT_RX_MO_MGMT_FILTER_FLAGS0; + tlv_filter.pkt_filter_flags1 = HTT_RX_MO_MGMT_FILTER_FLAGS1; + tlv_filter.pkt_filter_flags2 = HTT_RX_MO_CTRL_FILTER_FLASG2; + tlv_filter.pkt_filter_flags3 = HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | + HTT_RX_MON_MO_DATA_FILTER_FLASG3; + } else { + tlv_filter.rx_filter = ar->debug.rx_filter; + } + tlv_filter.offset_valid = false; + + for (i = 0; i < ar->ab->hw_params->num_rxmda_per_pdev; i++) { + ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; + ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, ar->dp.mac_id + i, + HAL_RXDMA_MONITOR_DST, + DP_RXDMA_REFILL_RING_SIZE, + &tlv_filter); + if (ret) { + ath12k_err(ar->ab, + "failed to setup filter for monitor buf %d\n", ret); + return ret; + } + } + return ret; +} + +void ath12k_debugfs_nrp_cleanup_all(struct ath12k *ar) +{ + struct ath12k_base *ab = ar->ab; + struct ath12k_neighbor_peer *nrp, *tmp; + + spin_lock_bh(&ab->base_lock); + list_for_each_entry_safe(nrp, tmp, &ab->neighbor_peers, list) { + if (nrp->is_filter_on) + complete(&nrp->filter_done); + list_del(&nrp->list); + kfree(nrp); + } + + ab->num_nrps = 0; + spin_unlock_bh(&ab->base_lock); + + debugfs_remove_recursive(ar->debug.debugfs_nrp); +} + +void ath12k_debugfs_nrp_clean(struct ath12k *ar, const u8 *addr) +{ + int i, j; + char fname[MAC_UNIT_LEN * ETH_ALEN] = {0}; + + for (i = 0, j = 0; i < (MAC_UNIT_LEN * ETH_ALEN); i += MAC_UNIT_LEN, j++) { + if (j == ETH_ALEN - 1) { + snprintf(fname + i, sizeof(fname) - i, "%02x", *(addr + j)); + break; + } + snprintf(fname + i, sizeof(fname) - i, "%02x:", *(addr + j)); + } + + spin_lock_bh(&ar->ab->base_lock); + ar->ab->num_nrps--; + spin_unlock_bh(&ar->ab->base_lock); + + debugfs_lookup_and_remove(fname, ar->debug.debugfs_nrp); + if (!ar->ab->num_nrps) { + debugfs_remove_recursive(ar->debug.debugfs_nrp); + ath12k_reset_nrp_filter(ar, true); + } +} + +static ssize_t ath12k_read_nrp_rssi(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + struct ath12k_base *ab = ar->ab; + struct ath12k_link_vif *arvif = NULL; + struct ath12k_neighbor_peer *nrp = NULL, *tmp; + struct ath12k_wmi_peer_create_arg peer_param = {0}; + u8 macaddr[ETH_ALEN] = {0}; + loff_t file_pos = *ppos; + struct path *fpath = &file->f_path; + char *fname = fpath->dentry->d_iname; + char buf[128] = {0}; + int i = 0; + int j = 0; + int len = 0; + int vdev_id = -1; + bool nrp_found = false; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON) { + mutex_unlock(&ar->conf_mutex); + return -ENETDOWN; + } + mutex_unlock(&ar->conf_mutex); + + if (file_pos > 0) + return 0; + + list_for_each_entry(arvif, &ar->arvifs, list) { + if (arvif->ahvif->vdev_type == WMI_VDEV_TYPE_AP) { + vdev_id = arvif->vdev_id; + break; + } + } + if (vdev_id < 0) { + ath12k_warn(ab, "unable to get vdev for AP interface\n"); + return 0; + } + + for (i = 0, j = 0; i < MAC_UNIT_LEN * ETH_ALEN; i += MAC_UNIT_LEN, j++) { + if (sscanf(fname + i, "%hhX", &macaddr[j]) <= 0) + return -EINVAL; + } + + spin_lock_bh(&ab->base_lock); + list_for_each_entry(nrp, &ab->neighbor_peers, list) { + if (ether_addr_equal(macaddr, nrp->addr)) { + reinit_completion(&nrp->filter_done); + nrp->vdev_id = vdev_id; + nrp->is_filter_on = false; + break; + } + } + spin_unlock_bh(&ab->base_lock); + + peer_param.vdev_id = nrp->vdev_id; + peer_param.peer_addr = nrp->addr; + peer_param.peer_type = WMI_PEER_TYPE_DEFAULT; + + if (!ath12k_peer_create(ar, arvif, NULL, &peer_param)) { + spin_lock_bh(&ab->base_lock); + list_for_each_entry_safe(nrp, tmp, &ab->neighbor_peers, list) { + if (ether_addr_equal(nrp->addr, peer_param.peer_addr)) { + nrp_found = true; + break; + } + } + spin_unlock_bh(&ab->base_lock); + + if (nrp_found) { + spin_lock_bh(&ab->base_lock); + nrp->is_filter_on = true; + spin_unlock_bh(&ab->base_lock); + + wait_for_completion_interruptible_timeout(&nrp->filter_done, 5 * HZ); + + spin_lock_bh(&ab->base_lock); + nrp->is_filter_on = false; + spin_unlock_bh(&ab->base_lock); + + len = scnprintf(buf, sizeof(buf), + "Neighbor Peer MAC\t\tRSSI\t\tTime\n"); + len += scnprintf(buf + len, sizeof(buf) - len, "%pM\t\t%u\t\t%lld\n", + nrp->addr, nrp->rssi, nrp->timestamp); + } else { + ath12k_peer_delete(ar, vdev_id, macaddr); + ath12k_warn(ab, "%pM not found in nrp list\n", macaddr); + return -EINVAL; + } + ath12k_peer_delete(ar, vdev_id, macaddr); + } else { + ath12k_warn(ab, "unable to create peer for nrp[%pM]\n", macaddr); + return -EINVAL; + } + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_read_nrp_rssi = { + .read = ath12k_read_nrp_rssi, + .open = simple_open, +}; + +static ssize_t ath12k_write_nrp_mac(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + struct ath12k_base *ab = ar->ab; + struct ath12k_peer *peer = NULL; + struct ath12k_neighbor_peer *nrp = NULL, *tmp = NULL; + u8 mac[ETH_ALEN] = {0}; + char fname[MAC_UNIT_LEN * ETH_ALEN] = {0}; + char *str = NULL; + char *buf = vmalloc(count); + char *ptr = buf; + int i = 0; + int j = 0; + int ret = count; + int action = 0; + ssize_t rc = 0; + bool del_nrp = false; + + mutex_lock(&ar->conf_mutex); + + rc = simple_write_to_buffer(buf, count, ppos, ubuf, count); + if (rc <= 0) + goto exit; + + /* To remove '\n' at end of buffer */ + buf[count - 1] = '\0'; + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto exit; + } + + str = strsep(&buf, ","); + if (!strcmp(str, "add")) + action = NRP_ACTION_ADD; + else if (!strcmp(str, "del")) + action = NRP_ACTION_DEL; + else { + ath12k_err(ab, "error: invalid argument\n"); + goto exit; + } + + memset(mac, 0, sizeof(mac)); + while ((str = strsep(&buf, ":")) != NULL) { + if (i >= ETH_ALEN || kstrtou8(str, 16, mac + i)) { + ath12k_warn(ab, "error: invalid mac address\n"); + goto exit; + } + i++; + } + + if (i != ETH_ALEN) { + ath12k_warn(ab, "error: invalid mac address\n"); + goto exit; + } + + if (!is_valid_ether_addr(mac)) { + ath12k_err(ab, "error: invalid mac address\n"); + goto exit; + } + + for (i = 0, j = 0; i < (MAC_UNIT_LEN * ETH_ALEN); i += MAC_UNIT_LEN, j++) { + if (j == ETH_ALEN - 1) { + snprintf(fname + i, sizeof(fname) - i, "%02x", mac[j]); + break; + } + snprintf(fname + i, sizeof(fname) - i, "%02x:", mac[j]); + } + + switch (action) { + case NRP_ACTION_ADD: + if (ab->num_nrps == (ATH12K_MAX_NRPS - 1)) { + ath12k_warn(ab, "max nrp reached, cannot create more\n"); + goto exit; + } + + list_for_each_entry(nrp, &ab->neighbor_peers, list) { + if (ether_addr_equal(nrp->addr, mac)) { + ath12k_warn(ab, "cannot add existing neighbor peer\n"); + goto exit; + } + } + + spin_lock_bh(&ab->base_lock); + peer = ath12k_peer_find_by_addr(ab, mac); + if (peer) { + ath12k_warn(ab, "cannot add exisitng peer [%pM] as nrp\n", mac); + spin_unlock_bh(&ab->base_lock); + goto exit; + } + spin_unlock_bh(&ab->base_lock); + + nrp = kzalloc(sizeof(*nrp), GFP_KERNEL); + if (!nrp) + goto exit; + + init_completion(&nrp->filter_done); + ether_addr_copy(nrp->addr, mac); + + spin_lock_bh(&ab->base_lock); + list_add_tail(&nrp->list, &ab->neighbor_peers); + spin_unlock_bh(&ab->base_lock); + + if (!ab->num_nrps) { + ar->debug.debugfs_nrp = debugfs_create_dir("nrp_rssi", + ar->debug.debugfs_pdev); + ath12k_reset_nrp_filter(ar, false); + } + spin_lock_bh(&ab->base_lock); + ab->num_nrps++; + spin_unlock_bh(&ab->base_lock); + + debugfs_create_file(fname, 0644, + ar->debug.debugfs_nrp, ar, + &fops_read_nrp_rssi); + break; + case NRP_ACTION_DEL: + if (!ar->ab->num_nrps) { + ath12k_err(ab, "error: no nac added\n"); + goto exit; + } + + spin_lock_bh(&ab->base_lock); + list_for_each_entry_safe(nrp, tmp, &ab->neighbor_peers, list) { + if (ether_addr_equal(nrp->addr, mac)) { + list_del(&nrp->list); + kfree(nrp); + del_nrp = true; + break; + } + } + spin_unlock_bh(&ab->base_lock); + + if (!del_nrp) + ath12k_warn(ab, "cannot delete %pM not added to list\n", mac); + else + ath12k_debugfs_nrp_clean(ar, mac); + break; + default: + break; + } +exit: + mutex_unlock(&ar->conf_mutex); + + vfree(ptr); + return ret; +} + +static const struct file_operations fops_write_nrp_mac = { + .write = ath12k_write_nrp_mac, + .open = simple_open, +}; + +static ssize_t ath12k_read_wmm_stats(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int len = 0; + int size = 2048; + char *buf; + ssize_t retval; + u64 total_wmm_sent_pkts = 0; + u64 total_wmm_received_pkts = 0; + u64 total_wmm_fail_sent = 0; + u64 total_wmm_fail_received = 0; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) { + ath12k_warn(ar->ab,"failed to allocate the buffer%s\n", __func__); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + for (count = 0; count < WME_NUM_AC; count++) { + total_wmm_sent_pkts += ar->wmm_stats.total_wmm_tx_pkts[count]; + total_wmm_received_pkts += ar->wmm_stats.total_wmm_rx_pkts[count]; + total_wmm_fail_sent += ar->wmm_stats.total_wmm_tx_drop[count]; + total_wmm_fail_received += ar->wmm_stats.total_wmm_rx_drop[count]; + } + + len += scnprintf(buf + len, size - len, "Total number of wmm_sent: %llu\n", + total_wmm_sent_pkts); + len += scnprintf(buf + len, size - len, "total number of wmm_received: %llu\n", + total_wmm_received_pkts); + len += scnprintf(buf + len, size - len, "total number of wmm_fail_sent: %llu\n", + total_wmm_fail_sent); + len += scnprintf(buf + len, size - len, "total number of wmm_fail_received: %llu\n", + total_wmm_fail_received); + len += scnprintf(buf + len, size - len, "Num of BE wmm_sent: %llu\n", + ar->wmm_stats.total_wmm_tx_pkts[WME_AC_BE]); + len += scnprintf(buf + len, size - len, "Num of BK wmm_sent: %llu\n", + ar->wmm_stats.total_wmm_tx_pkts[WME_AC_BK]); + len += scnprintf(buf + len, size - len, "Num of VI wmm_sent: %llu\n", + ar->wmm_stats.total_wmm_tx_pkts[WME_AC_VI]); + len += scnprintf(buf + len, size - len, "Num of VO wmm_sent: %llu\n", + ar->wmm_stats.total_wmm_tx_pkts[WME_AC_VO]); + len += scnprintf(buf + len, size - len, "num of be wmm_received: %llu\n", + ar->wmm_stats.total_wmm_rx_pkts[WME_AC_BE]); + len += scnprintf(buf + len, size - len, "num of bk wmm_received: %llu\n", + ar->wmm_stats.total_wmm_rx_pkts[WME_AC_BK]); + len += scnprintf(buf + len, size - len, "num of vi wmm_received: %llu\n", + ar->wmm_stats.total_wmm_rx_pkts[WME_AC_VI]); + len += scnprintf(buf + len, size - len, "num of vo wmm_received: %llu\n", + ar->wmm_stats.total_wmm_rx_pkts[WME_AC_VO]); + len += scnprintf(buf + len, size - len, "num of be wmm_tx_dropped: %llu\n", + ar->wmm_stats.total_wmm_tx_drop[WME_AC_BE]); + len += scnprintf(buf + len, size - len, "num of bk wmm_tx_dropped: %llu\n", + ar->wmm_stats.total_wmm_tx_drop[WME_AC_BK]); + len += scnprintf(buf + len, size - len, "num of vi wmm_tx_dropped: %llu\n", + ar->wmm_stats.total_wmm_tx_drop[WME_AC_VI]); + len += scnprintf(buf + len, size - len, "num of vo wmm_tx_dropped: %llu\n", + ar->wmm_stats.total_wmm_tx_drop[WME_AC_VO]); + len += scnprintf(buf + len, size - len, "num of be wmm_rx_dropped: %llu\n", + ar->wmm_stats.total_wmm_rx_drop[WME_AC_BE]); + len += scnprintf(buf + len, size - len, "num of bk wmm_rx_dropped: %llu\n", + ar->wmm_stats.total_wmm_rx_drop[WME_AC_BK]); + len += scnprintf(buf + len, size - len, "num of vi wmm_rx_dropped: %llu\n", + ar->wmm_stats.total_wmm_rx_drop[WME_AC_VI]); + len += scnprintf(buf + len, size - len, "num of vo wmm_rx_dropped: %llu\n", + ar->wmm_stats.total_wmm_rx_drop[WME_AC_VO]); + + mutex_unlock(&ar->conf_mutex); + + if (len > size) + len = size; + retval = simple_read_from_buffer(ubuf, count, ppos, buf, len); + kfree(buf); + + return retval; +} + +static const struct file_operations fops_wmm_stats = { + .read = ath12k_read_wmm_stats, + .open = simple_open, +}; + +static int ath12k_fill_bp_stats(struct ath12k_base *ab, + struct ath12k_bp_stats *bp_stats, + char *buf, int len, int size) +{ + lockdep_assert_held(&ab->base_lock); + + len += scnprintf(buf + len, size - len, "count: %u\n", + bp_stats->count); + len += scnprintf(buf + len, size - len, "hp: %u\n", + bp_stats->hp); + len += scnprintf(buf + len, size - len, "tp: %u\n", + bp_stats->tp); + len += scnprintf(buf + len, size - len, "seen before: %ums\n\n", + jiffies_to_msecs(jiffies - bp_stats->jiffies)); + return len; +} + +static ssize_t ath12k_debugfs_dump_soc_ring_bp_stats(struct ath12k_base *ab, + char *buf, int size) +{ + struct ath12k_bp_stats *bp_stats; + bool stats_rxd = false; + u8 i, pdev_idx; + int len = 0; + + len += scnprintf(buf + len, size - len, "\nBackpressure Stats\n"); + len += scnprintf(buf + len, size - len, "==================\n"); + + spin_lock_bh(&ab->base_lock); + for (i = 0; i < HTT_SW_UMAC_RING_IDX_MAX; i++) { + bp_stats = &ab->soc_stats.bp_stats.umac_ring_bp_stats[i]; + + if (!bp_stats->count) + continue; + + len += scnprintf(buf + len, size - len, "Ring: %s\n", + htt_bp_umac_ring[i]); + len = ath12k_fill_bp_stats(ab, bp_stats, buf, len, size); + stats_rxd = true; + } + + for (i = 0; i < HTT_SW_LMAC_RING_IDX_MAX; i++) { + for (pdev_idx = 0; pdev_idx < MAX_RADIOS; pdev_idx++) { + bp_stats = + &ab->soc_stats.bp_stats.lmac_ring_bp_stats[i][pdev_idx]; + + if (!bp_stats->count) + continue; + + len += scnprintf(buf + len, size - len, "Ring: %s\n", + htt_bp_lmac_ring[i]); + len += scnprintf(buf + len, size - len, "pdev: %d\n", + pdev_idx); + len = ath12k_fill_bp_stats(ab, bp_stats, buf, len, size); + stats_rxd = true; + } + } + spin_unlock_bh(&ab->base_lock); + + if (!stats_rxd) + len += scnprintf(buf + len, size - len, + "No Ring Backpressure stats received\n\n"); + + return len; +} + +static ssize_t ath12k_debugfs_dump_soc_dp_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_soc_dp_stats *soc_stats = &ab->soc_stats; + struct ath12k *ar; + int len = 0, i, retval; + const int size = 4096; + static const char *rxdma_err[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX] = { + "Overflow", "MPDU len", "FCS", "Decrypt", "TKIP MIC", + "Unencrypt", "MSDU len", "MSDU limit", "WiFi parse", + "AMSDU parse", "SA timeout", "DA timeout", + "Flow timeout", "Flush req"}; + static const char *reo_err[HAL_REO_DEST_RING_ERROR_CODE_MAX] = { + "Desc addr zero", "Desc inval", "AMPDU in non BA", + "Non BA dup", "BA dup", "Frame 2k jump", "BAR 2k jump", + "Frame OOR", "BAR OOR", "No BA session", + "Frame SN equal SSN", "PN check fail", "2k err", + "PN err", "Desc blocked"}; + + static const char *wbm_rel_src[HAL_WBM_REL_SRC_MODULE_MAX] = { + "TQM", "Rxdma", "Reo", "FW", "SW" }; + char *buf; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + len += scnprintf(buf + len, size - len, "SOC RX STATS:\n\n"); + len += scnprintf(buf + len, size - len, "err ring pkts: %u\n", + soc_stats->err_ring_pkts); + len += scnprintf(buf + len, size - len, "Invalid RBM: %u\n\n", + soc_stats->invalid_rbm); + len += scnprintf(buf + len, size - len, "RXDMA errors:\n"); + for (i = 0; i < HAL_REO_ENTR_RING_RXDMA_ECODE_MAX; i++) + len += scnprintf(buf + len, size - len, "%s: handled %u dropped %u\n", + rxdma_err[i], soc_stats->rxdma_error[i], + soc_stats->rxdma_error_drop[i]); + + len += scnprintf(buf + len, size - len, "\nREO errors:\n"); + for (i = 0; i < HAL_REO_DEST_RING_ERROR_CODE_MAX; i++) + len += scnprintf(buf + len, size - len, "%s: handled %u dropped %u\n", + reo_err[i], soc_stats->reo_error[i], + soc_stats->reo_error_drop[i]); + len += scnprintf(buf + len, size - len, "REO excep MSDU buf type:%u\n", + soc_stats->reo_excep_msdu_buf_type); + + len += scnprintf(buf + len, size - len, "\nHAL REO errors:\n"); + len += scnprintf(buf + len, size - len, + "ring0: %u\nring1: %u\nring2: %u\nring3: %u\n", + soc_stats->hal_reo_error[0], + soc_stats->hal_reo_error[1], + soc_stats->hal_reo_error[2], + soc_stats->hal_reo_error[3]); + + len += scnprintf(buf + len, size - len, "\nSOC TX STATS:\n"); + len += scnprintf(buf + len, size - len, "\nTCL Ring Full Failures:\n"); + + for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) + len += scnprintf(buf + len, size - len, "ring%d: %u\n", + i, soc_stats->tx_err.desc_na[i]); + + len += scnprintf(buf + len, size - len, "\nTCL Ring Buffer Alloc Failures:\n"); + for (i = 0; i < DP_TCL_NUM_RING_MAX; i++) + len += scnprintf(buf + len, size - len, "ring%d: %u\n", + i, soc_stats->tx_err.txbuf_na[i]); + + len += scnprintf(buf + len, size - len, + "\nTx Threshold limit: %d\n", + soc_stats->tx_err.pdev_threshold_limit); + + len += scnprintf(buf + len, size - len, + "\nGroup Tx Threshold limit: %u\n", + soc_stats->tx_err.group_threshold_limit); + + len += scnprintf(buf + len, size - len, + "\nMisc Transmit Failures: %d\n", + atomic_read(&soc_stats->tx_err.misc_fail)); + + len += scnprintf(buf + len, size - len, + "\nMon drop descriptor: %u\n", + soc_stats->mon_drop_desc); + + len += scnprintf(buf + len, size - len, + "\nHAL_REO_CMD_DRAIN Counter: %u\n", + soc_stats->hal_reo_cmd_drain); + + len += scnprintf(buf + len, size - len, + "\nREO_CMD_CACHE_FLUSH Failure: %u\n", + soc_stats->reo_cmd_cache_error); + + len += scnprintf(buf + len, size - len, + "\nREO_CMD_UPDATE_RX_QUEUE Failure: %u\n", + soc_stats->reo_cmd_update_rx_queue_error); + + len += scnprintf(buf + len, size - len, + "\nmcast reinject: %u\n", + soc_stats->mcast_reinject); + + len += scnprintf(buf + len, size - len, + "\ntx_wbm_rel_source: 0:%u 1:%u 2:%u 3:%u 4:%u\n", + soc_stats->tx_wbm_rel_source[0], + soc_stats->tx_wbm_rel_source[1], + soc_stats->tx_wbm_rel_source[2], + soc_stats->tx_wbm_rel_source[3], + soc_stats->tx_wbm_rel_source[4]); + + len += scnprintf(buf + len, size - len, + "\ntqm_rel_reason: 0:%u 1:%u 2:%u 3:%u 4:%u 5:%u 6:%u 7:%u 8:%u 9:%u 10:%u 11:%u 12:%u 13:%u 14:%u\n", + soc_stats->tqm_rel_reason[0], + soc_stats->tqm_rel_reason[1], + soc_stats->tqm_rel_reason[2], + soc_stats->tqm_rel_reason[3], + soc_stats->tqm_rel_reason[4], + soc_stats->tqm_rel_reason[5], + soc_stats->tqm_rel_reason[6], + soc_stats->tqm_rel_reason[7], + soc_stats->tqm_rel_reason[8], + soc_stats->tqm_rel_reason[9], + soc_stats->tqm_rel_reason[10], + soc_stats->tqm_rel_reason[11], + soc_stats->tqm_rel_reason[12], + soc_stats->tqm_rel_reason[13], + soc_stats->tqm_rel_reason[14]); + + len += scnprintf(buf + len, size - len, + "\nfw_tx_status: 0:%u 1:%u 2:%u 3:%u 4:%u 5:%u 6:%u\n", + soc_stats->fw_tx_status[0], + soc_stats->fw_tx_status[1], + soc_stats->fw_tx_status[2], + soc_stats->fw_tx_status[3], + soc_stats->fw_tx_status[4], + soc_stats->fw_tx_status[5], + soc_stats->fw_tx_status[6]); + + len += scnprintf(buf + len, size - len, + "\ntx_enqueued: 0:%u 1:%u 2:%u 3:%u\n", + soc_stats->tx_enqueued[0], + soc_stats->tx_enqueued[1], + soc_stats->tx_enqueued[2], + soc_stats->tx_enqueued[3]); + + len += scnprintf(buf + len, size - len, + "\nTx Peers Not Present: %d\n", + soc_stats->tx_err.peers_not_present); + + len += scnprintf(buf + len, size - len, + "\nnull tx complete: 0:%u 1:%u 2:%u 3:%u\n", + soc_stats->null_tx_complete[0], + soc_stats->null_tx_complete[1], + soc_stats->null_tx_complete[2], + soc_stats->null_tx_complete[3]); + + len += scnprintf(buf + len, size - len, + "\ntx_completed: 0:%u 1:%u 2:%u 3:%u\n", + soc_stats->tx_completed[0], + soc_stats->tx_completed[1], + soc_stats->tx_completed[2], + soc_stats->tx_completed[3]); + + + len += scnprintf(buf + len, size - len, "\nbond_tx_ucast_enqueued: "); + for (i = 0; i < MAX_TCL_RING; i++) + len += scnprintf(buf + len, size - len,"%u:%u ", + i, soc_stats->bond_tx_ucast_enqueued[i]); + + len += scnprintf(buf + len, size - len, "\nbond_tx_mcast_enqueued: "); + for (i = 0; i < MAX_TCL_RING; i++) + len += scnprintf(buf + len, size - len, "%u:%u ", + i, soc_stats->bond_tx_mcast_enqueued[i]); + + len += scnprintf(buf + len, size - len, "\nbond_tx_ucast_dropped: "); + for (i = 0; i < MAX_TCL_RING; i++) + len += scnprintf(buf + len, size - len, "%u:%u ", + i, soc_stats->bond_tx_ucast_dropped[i]); + + len += scnprintf(buf + len, size - len, "\nbond_tx_mcast_dropped: "); + for (i = 0; i < MAX_TCL_RING; i++) + len += scnprintf(buf + len, size - len, "%u:%u ", + i, soc_stats->bond_tx_mcast_dropped[i]); + + len += scnprintf(buf + len, size - len, "\nbond_mcast2ucast_tried: "); + for (i = 0; i < MAX_TCL_RING; i++) + len += scnprintf(buf + len, size - len, "%u:%u ", + i, soc_stats->bond_mcast2ucast_tried[i]); + + len += scnprintf(buf + len, size - len, "\nbond_mcast2ucast_converted: "); + for (i = 0; i < MAX_TCL_RING; i++) + len += scnprintf(buf + len, size - len, "%u:%u ", + i, soc_stats->bond_mcast2ucast_converted[i]); + + len += scnprintf(buf + len, size - len, "\nbond_mcast2ucast_drop: "); + for (i = 0; i < MAX_TCL_RING; i++) + len += scnprintf(buf + len, size - len, + "%u:%u ", i, soc_stats->bond_mcast2ucast_drop[i]); + + len += scnprintf(buf + len, size - len, + "\nag tx_pending: %u\n", + atomic_read(&ab->ag->num_dp_tx_pending)); + + for (i = 1; i <= ab->num_radios; i++) { + ar = ath12k_mac_get_ar_by_pdev_id(ab, i); + if (ar) { + len += scnprintf(buf + len, size - len, + "\nar tx_pending [%d]: %u\n", i, + atomic_read(&ar->dp.num_tx_pending)); + } + } + + len += scnprintf(buf + len, size - len, "\nREO Rx Received:\n"); + for (i = 0; i < DP_REO_DST_RING_MAX; i++) + len += scnprintf(buf + len, size - len, + "Ring%d: 0:%u\t1:%u\t2:%u\n", + i + 1, + soc_stats->reo_rx[i][0], + soc_stats->reo_rx[i][1], + soc_stats->reo_rx[i][2]); + + len += scnprintf(buf + len, size - len, "\nREO Fast Rx:\n"); + for (i = 0; i < DP_REO_DST_RING_MAX; i++) + len += scnprintf(buf + len, size - len, + "Ring%d: 0:%u\t1:%u\t2:%u\n", + i + 1, + soc_stats->fast_rx[i][0], + soc_stats->fast_rx[i][1], + soc_stats->fast_rx[i][2]); + + len += scnprintf(buf + len, size - len, "\nREO Non-Fast Rx:\n"); + for (i = 0; i < DP_REO_DST_RING_MAX; i++) + len += scnprintf(buf + len, size - len, + "Ring%d: 0:%u\t1:%u\t2:%u\n", + i + 1, + soc_stats->non_fast_rx[i][0], + soc_stats->non_fast_rx[i][1], + soc_stats->non_fast_rx[i][2]); + + len += scnprintf(buf + len, size - len, "\nRx WBM REL SRC Errors:\n"); + for (i = 0; i < HAL_WBM_REL_SRC_MODULE_MAX; i++) + len += scnprintf(buf + len, size - len, + "%s\t:0:%u\t1:%u\t2:%u\n", + wbm_rel_src[i], + soc_stats->rx_wbm_rel_source[i][0], + soc_stats->rx_wbm_rel_source[i][1], + soc_stats->rx_wbm_rel_source[i][2]); + + len += scnprintf(buf + len, size - len, + "\nFIRST/LAST MSDU BIT MISSING COUNT: %u\n", + soc_stats->first_and_last_msdu_bit_miss); + + len += ath12k_debugfs_dump_soc_ring_bp_stats(ab, buf + len, size - len); + + if (len > size) + len = size; + retval = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return retval; +} + +static ssize_t +ath12k_debugfs_write_soc_dp_stats(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_soc_dp_stats *soc_stats = &ab->soc_stats; + char buf[20] = {0}; + int ret; + + if (count > 20) + return -EFAULT; + + ret = copy_from_user(buf, user_buf, count); + if (ret) + return -EFAULT; + + if (strstr(buf, "reset")) + memset(soc_stats, 0, sizeof(struct ath12k_soc_dp_stats)); + + return count; +} + +static const struct file_operations fops_soc_dp_stats = { + .read = ath12k_debugfs_dump_soc_dp_stats, + .write = ath12k_debugfs_write_soc_dp_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_debugfs_hal_dump_srng_stats_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + int len = 0, retval; + const int size = 4096 * 6; + char *buf; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + len = ath12k_debugfs_hal_dump_srng_stats(ab, buf + len, size - len); + if (len > size) + len = size; + retval = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return retval; +} + +static const struct file_operations fops_dump_hal_stats = { + .read = ath12k_debugfs_hal_dump_srng_stats_read, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_read_trace_qdss(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + const char buf[] = + "1 - this will start qdss trace collection\n" + "0 - this will stop and save the qdss trace collection\n"; + + return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf)); +} + +static ssize_t +ath12k_write_trace_qdss(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_pdev *pdev; + struct ath12k *ar; + int i, ret; + bool radioup = false; + bool qdss_enable; + + if (kstrtobool_from_user(user_buf, count, &qdss_enable)) + return -EINVAL; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + if (ar && ar->state == ATH12K_STATE_ON) { + radioup = true; + break; + } + } + + if (!radioup) { + ath12k_err(ab, "radio is not up\n"); + ret = -ENETDOWN; + goto exit; + } + + if (qdss_enable) { + if (ab->is_qdss_tracing) { + ret = count; + goto exit; + } + ath12k_config_qdss(ab); + } else { + if (!ab->is_qdss_tracing) { + ret = count; + goto exit; + } + ret = ath12k_send_qdss_trace_mode_req(ab, + QMI_WLANFW_QDSS_TRACE_OFF_V01); + if (ret < 0) + ath12k_warn(ab, + "Failed to stop QDSS: %d\n", ret); + } + + ret = count; + +exit: + return ret; +} + +static const struct file_operations fops_trace_qdss = { + .read = ath12k_read_trace_qdss, + .write = ath12k_write_trace_qdss, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static void ath12k_debug_multipd_wmi_pdev_set_param(struct ath12k_base *ab, + const unsigned int value) +{ + struct ath12k_pdev *pdev; + struct ath12k *ar; + struct device *dev = ab->dev; + int radio_idx; + bool multi_pd_arch; + bool assert_userpd; + + multi_pd_arch = of_property_read_bool(dev->of_node, "qcom,multipd_arch"); + + if (!multi_pd_arch) + return; + + for (radio_idx = 0; radio_idx < ab->num_radios; radio_idx++) { + pdev = &ab->pdevs[radio_idx]; + ar = pdev->ar; + + /* Set pdev param to let firmware know which pd to use for + * sending fatal IRQ. + * Non-MLO, fatal error comes from asserted radios's user pd + * MLO, fatal error comes from asserted radio's root pd + */ + if (!ab->ag->mlo_capable) { + assert_userpd = true; + } else { + if (value == ATH12K_FW_RECOVERY_DISABLE || + value == ATH12K_FW_RECOVERY_ENABLE_SSR_ONLY || + value == ATH12K_FW_RECOVERY_ENABLE_AUTO) + assert_userpd = false; + else + assert_userpd = true; + } + + ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_MPD_USERPD_SSR, + assert_userpd, ar->pdev->pdev_id); + } +} + +static ssize_t ath12k_debug_write_fw_recovery(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k *ar; + struct ath12k_pdev *pdev; + struct ath12k_hw_group *ag; + unsigned int value; + enum wmi_fw_hang_recovery_mode_type recovery_mode; + int ret, radio_idx, radioup = 0; + int i; + + if (kstrtouint_from_user(user_buf, count, 0, &value)) + return -EINVAL; + + if (value < ATH12K_FW_RECOVERY_DISABLE || + value > ATH12K_FW_RECOVERY_ENABLE_SSR_ONLY) { + ath12k_warn(ab, "Please enter: 0 = Disable, 1 = Enable (auto recover), " + "2 = Enable SSR Mode1, 3 = Enable SSR only"); + ret = -EINVAL; + goto exit; + } + + ag = ab->ag; + + if (!value) + recovery_mode = ATH12K_WMI_DISABLE_FW_RECOVERY; + else + recovery_mode = (value == ATH12K_FW_RECOVERY_ENABLE_MODE1_AUTO) ? + ATH12K_WMI_FW_HANG_RECOVERY_MODE1 : + ATH12K_WMI_FW_HANG_RECOVERY_MODE0; + + ath12k_debug_multipd_wmi_pdev_set_param(ab, value); + + if (ag->mlo_capable) { + for (i = 0; i < ag->num_chip; i++) { + ab = ag->ab[i]; + mutex_lock(&ab->core_lock); + ab->fw_recovery_support = value; + mutex_unlock(&ab->core_lock); + + /* + * Set MODE0 or MODE 1, if recovery mode addr is valid. + * TODO: Instead of checking recovery mode addr from + * TLV, need to check WMI caps once the support is + * added from FW. + */ + if (ab->recovery_mode_address) { + for (radio_idx = 0; radio_idx < ab->num_radios; radio_idx++) { + + pdev = &ab->pdevs[radio_idx]; + ar = pdev->ar; + if (ar && ar->state == ATH12K_STATE_ON) { + radioup = 1; + break; + } + } + + if (radioup) { + ret = ath12k_wmi_force_fw_hang_cmd(ar, + recovery_mode, + ATH12K_WMI_FW_HANG_DELAY, false); + ath12k_info(ab, "setting FW assert mode [%d] ret [%d]\n", recovery_mode, ret); + } else + continue; + } + } + } else + ab->fw_recovery_support = value ? true : false; + + ret = count; + +exit: + return ret; +} + +static ssize_t ath12k_debug_read_fw_recovery(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + char buf[32]; + size_t len; + + len = scnprintf(buf, sizeof(buf), "%u\n", ab->fw_recovery_support); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_fw_recovery = { + .read = ath12k_debug_read_fw_recovery, + .write = ath12k_debug_write_fw_recovery, + .open = simple_open, +}; + +static ssize_t ath12k_read_fw_dbglog(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + size_t len; + char buf[128]; + + len = scnprintf(buf, sizeof(buf), "%u 0x%016llx\n", + ab->fw_dbglog_param, ab->fw_dbglog_val); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_write_fw_dbglog(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k *ar = ab->pdevs[0].ar; + char buf[128] = {0}; + unsigned int param; + u64 value; + int ret; + + if (!ar) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, + user_buf, count); + if (ret <= 0) + goto out; + + ret = sscanf(buf, "%u %llx", ¶m, &value); + + if (ret != 2) { + ret = -EINVAL; + goto out; + } + + ab->fw_dbglog_param = param; + ab->fw_dbglog_val = value; + ret = ath12k_wmi_dbglog_cfg(ar, param, value); + if (ret) { + ath12k_warn(ar->ab, "dbglog cfg failed from debugfs: %d\n", + ret); + goto out; + } + + ret = count; + +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_fw_dbglog = { + .read = ath12k_read_fw_dbglog, + .write = ath12k_write_fw_dbglog, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static void ath12k_debug_config_mon_status(struct ath12k *ar, bool enable) +{ + struct htt_rx_ring_tlv_filter tlv_filter = {0}; + struct ath12k_base *ab = ar->ab; + int i; + u32 ring_id; + + if (enable) { + tlv_filter = ath12k_mac_mon_status_filter_default; + tlv_filter.rxmon_disable = false; + } else { + tlv_filter.rxmon_disable = true; + } + + for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { + ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; + ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, + ar->dp.mac_id + i, + HAL_RXDMA_MONITOR_DST, + DP_RXDMA_REFILL_RING_SIZE, + &tlv_filter); + } +} + +static ssize_t ath12k_write_stats_disable(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_pdev *pdev; + bool disable; + int ret, i; + u32 mask = 0; + + if (kstrtobool_from_user(user_buf, count, &disable)) + return -EINVAL; + + if (disable != ab->stats_disable) { + ab->stats_disable = disable; + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (pdev && pdev->ar) { + ath12k_debug_config_mon_status(pdev->ar, !disable); + + if (!disable) + mask = HTT_PPDU_STATS_TAG_DEFAULT; + + ath12k_dp_tx_htt_h2t_ppdu_stats_req(pdev->ar, mask); + } + } + } + ret = count; + + return ret; +} + +static ssize_t ath12k_read_stats_disable(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + char buf[3]; + + buf[0] = ab->stats_disable ? '1' : '0'; + buf[1] = '\n'; + buf[2] = 0; + + return simple_read_from_buffer(user_buf, count, ppos, buf, 2);; +} + +static const struct file_operations fops_soc_stats_disable = { + .open = simple_open, + .read = ath12k_read_stats_disable, + .write = ath12k_write_stats_disable, +}; + +static ssize_t ath12k_write_rx_hash_ix3(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_pdev *pdev; + u32 rx_hash; + u8 buf[128] = {0}; + int ret, i, radioup = 0; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (pdev && pdev->ar) { + radioup = 1; + break; + } + } + + if (radioup == 0) { + ath12k_err(ab, "radio is not up\n"); + ret = -ENETDOWN; + goto exit; + } + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (ret < 0) + goto exit; + + buf[ret] = '\0'; + ret = sscanf(buf, "%x", &rx_hash); + if (!ret) { + ret = -EINVAL; + goto exit; + } + + if (rx_hash != ab->rx_hash_ix3) { + ab->rx_hash_ix3 = rx_hash; + if (rx_hash) + ath12k_hal_reo_ring_ctrl_hash_ix3_setup(ab, rx_hash); + } + ret = count; +exit: + return ret; +} + +static ssize_t ath12k_write_rx_hash_ix2(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_pdev *pdev; + u32 rx_hash; + u8 buf[128] = {0}; + int ret, i, radioup = 0; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (pdev && pdev->ar) { + radioup = 1; + break; + } + } + + if (radioup == 0) { + ath12k_err(ab, "radio is not up\n"); + ret = -ENETDOWN; + goto exit; + } + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (ret < 0) + goto exit; + + buf[ret] = '\0'; + ret = sscanf(buf, "%x", &rx_hash); + if (!ret) { + ret = -EINVAL; + goto exit; + } + + if (rx_hash != ab->rx_hash_ix2) { + ab->rx_hash_ix2 = rx_hash; + if (rx_hash) + ath12k_hal_reo_ring_ctrl_hash_ix2_setup(ab, rx_hash); + } + ret = count; +exit: + return ret; +} + +static const struct file_operations fops_soc_rx_hash_ix2 = { + .open = simple_open, + .write = ath12k_write_rx_hash_ix2, +}; + +static const struct file_operations fops_soc_rx_hash_ix3 = { + .open = simple_open, + .write = ath12k_write_rx_hash_ix3, +}; + + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +static ssize_t ath12k_debugfs_dump_ppeds_stats(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_ppeds_stats *ppeds_stats = &ab->ppeds_stats; + int len = 0, retval; + const int size = 4096; + char *buf; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + len += scnprintf(buf + len, size - len, "PPEDS STATS\n"); + len += scnprintf(buf + len, size - len, "-----------\n"); + len += scnprintf(buf + len, size - len, "tcl_prod_cnt %u\n", + ppeds_stats->tcl_prod_cnt); + len += scnprintf(buf + len, size - len, "tcl_cons_cnt %u\n", + ppeds_stats->tcl_cons_cnt); + len += scnprintf(buf + len, size - len, "reo_prod_cnt %u\n", + ppeds_stats->reo_prod_cnt); + len += scnprintf(buf + len, size - len, "reo_cons_cnt %u\n", + ppeds_stats->reo_cons_cnt); + len += scnprintf(buf + len, size - len, "get_tx_desc_cnt %u\n", + ppeds_stats->get_tx_desc_cnt); + len += scnprintf(buf + len, size - len, "enable_intr_cnt %u\n", + ppeds_stats->enable_intr_cnt); + len += scnprintf(buf + len, size - len, "disable_intr_cnt %u\n", + ppeds_stats->disable_intr_cnt); + len += scnprintf(buf + len, size - len, "release_tx_single_cnt %u\n", + ppeds_stats->release_tx_single_cnt); + len += scnprintf(buf + len, size - len, "release_rx_desc_cnt %u\n", + ppeds_stats->release_rx_desc_cnt); + len += scnprintf(buf + len, size - len, "tx_desc_allocated %u\n", + ppeds_stats->tx_desc_allocated); + len += scnprintf(buf + len, size - len, "tx_desc_freed %u\n", + ppeds_stats->tx_desc_freed); + len += scnprintf(buf + len, size - len, "fw2wbm_pkt_drops %u\n", + ppeds_stats->fw2wbm_pkt_drops); + len += scnprintf(buf + len, size - len, "num_rx_desc_freed %u\n", + ppeds_stats->num_rx_desc_freed); + len += scnprintf(buf + len, size - len, "num_rx_desc_realloc %u\n", + ppeds_stats->num_rx_desc_realloc); + + if (len > size) + len = size; + + retval = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + return retval; +} + +static ssize_t +ath12k_debugfs_write_ppeds_stats(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_base *ab = file->private_data; + struct ath12k_ppeds_stats *ppeds_stats = &ab->ppeds_stats; + char buf[20] = {0}; + int ret; + + if (count > sizeof(buf)) + return -EFAULT; + + ret = copy_from_user(buf, user_buf, count); + if (ret) + return -EFAULT; + + if (strstr(buf, "reset")) + memset(ppeds_stats, 0, sizeof(struct ath12k_ppeds_stats)); + + return count; +} + +static const struct file_operations fops_ppeds_stats = { + .read = ath12k_debugfs_dump_ppeds_stats, + .write = ath12k_debugfs_write_ppeds_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; +#endif + +int ath12k_debugfs_pdev_create(struct ath12k_base *ab) +{ + if (test_bit(ATH12K_FLAG_REGISTERED, &ab->dev_flags)) + return 0; + + debugfs_create_file("fw_dbglog_config", 0600, ab->debugfs_soc, ab, + &fops_fw_dbglog); + + debugfs_create_file("set_fw_recovery", 0600, ab->debugfs_soc, ab, + &fops_fw_recovery); + + debugfs_create_file("simulate_fw_crash", 0600, ab->debugfs_soc, ab, + &fops_simulate_fw_crash); + + debugfs_create_file("soc_dp_stats", 0600, ab->debugfs_soc, ab, + &fops_soc_dp_stats); + + debugfs_create_file("dump_srng_stats", 0600, ab->debugfs_soc, ab, + &fops_dump_hal_stats); + + debugfs_create_file("trace_qdss", 0600, ab->debugfs_soc, ab, + &fops_trace_qdss); + + debugfs_create_file("stats_disable", 0600, ab->debugfs_soc, ab, + &fops_soc_stats_disable); + + debugfs_create_file("rx_hash_ix2", 0600, ab->debugfs_soc, ab, + &fops_soc_rx_hash_ix2); + + debugfs_create_file("rx_hash_ix3", 0600, ab->debugfs_soc, ab, + &fops_soc_rx_hash_ix3); + + debugfs_create_file("fw_reset_stats", 0400, ab->debugfs_soc, ab, + &fops_fw_reset_stats); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) + debugfs_create_file("ppeds_stats", 0600, ab->debugfs_soc, ab, + &fops_ppeds_stats); +#endif + return 0; +} + +void ath12k_debugfs_pdev_destroy(struct ath12k_base *ab) +{ +} + +int ath12k_debugfs_soc_create(struct ath12k_base *ab) +{ + char soc_name[64] = { 0 }; + + if (!(IS_ERR_OR_NULL(ab->debugfs_soc))) + return 0; + + if (ab->userpd_id) { + snprintf(soc_name, sizeof(soc_name), "%s_%d", + ab->hw_params->name, ab->userpd_id); + } else { + snprintf(soc_name, sizeof(soc_name), "%s_%s", ab->hw_params->name, + dev_name(ab->dev)); + } + + ab->debugfs_soc = debugfs_create_dir(soc_name, debugfs_ath12k); + + return PTR_ERR_OR_ZERO(ab->debugfs_soc); +} + +void ath12k_debugfs_soc_destroy(struct ath12k_base *ab) +{ + if (!debugfs_ath12k) { + /* ath12k_debugfs_destroy() already removed this directory */ + ab->debugfs_soc = NULL; + return; + } + + debugfs_remove_recursive(ab->debugfs_soc); + ab->debugfs_soc = NULL; +} + +void ath12k_debugfs_fw_stats_init(struct ath12k *ar) +{ + struct dentry *fwstats_dir = debugfs_create_dir("fw_stats", + ar->debug.debugfs_pdev); + + ar->fw_stats.debugfs_fwstats = fwstats_dir; + + /* all stats debugfs files created are under "fw_stats" directory + * created per PDEV + */ + debugfs_create_file("pdev_stats", 0600, fwstats_dir, ar, + &fops_pdev_stats); + debugfs_create_file("vdev_stats", 0600, fwstats_dir, ar, + &fops_vdev_stats); + debugfs_create_file("beacon_stats", 0600, fwstats_dir, ar, + &fops_bcn_stats); + debugfs_create_file("en_vdev_stats_ol", 0600, fwstats_dir, ar, + &fops_vdev_stats_offload); + +} + +int ath12k_pktlog_rx_filter_setting(struct ath12k *ar, + struct htt_rx_ring_tlv_filter + *tlv_filter) +{ + int ret, i; + u32 ring_id; + for (i = 0; i < ar->ab->hw_params->num_rxmda_per_pdev; i++) { + ring_id = ar->dp.rxdma_mon_dst_ring[i].ring_id; + ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, + ar->dp.mac_id + i, + HAL_RXDMA_MONITOR_DST, + DP_RXDMA_REFILL_RING_SIZE, + tlv_filter); + if(ret) + break; + } + return ret; +} + +static int ath12k_pktlog_enable_hybrid_mode(struct ath12k *ar, u32 filter, + u32 mode) +{ + struct ath12k_base *ab = ar->ab; + struct htt_tx_ring_tlv_filter tlv_filter = {0}; + u32 tx_filter, tx_buf_size, ring_id; + int ret; + + if (mode == ATH12K_PKTLOG_MODE_FULL) { + tx_filter = HTT_TX_MON_FILTER_HYBRID_MODE; + tx_buf_size = DP_TX_MONITOR_BUF_SIZE; + } else if (mode == ATH12K_PKTLOG_MODE_LITE) { + ret = ath12k_dp_tx_htt_h2t_ppdu_stats_req(ar, + HTT_PPDU_STATS_TAG_PKTLOG); + if (ret) { + ath12k_err(ar->ab, "failed to enable pktlog lite: %d\n", ret); + goto out; + } + tx_filter = HTT_TX_MON_FILTER_HYBRID_MODE; + tx_buf_size = DP_RX_BUFFER_SIZE_LITE; + } else { + /* TODO: Default tx filter configuration */ + tx_buf_size = DP_TX_MONITOR_BUF_SIZE; + } + + tlv_filter.tx_mon_upstream_tlv_flags0 = tx_filter; + tlv_filter.tx_mon_upstream_tlv_flags2 = + HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32; + + ring_id = ab->dp.tx_mon_buf_ring.refill_buf_ring.ring_id; + ret = ath12k_dp_tx_htt_tx_filter_setup(ab, ring_id, 0, + HAL_TX_MONITOR_BUF, + tx_buf_size, + &tlv_filter); + if (ret) { + ath12k_warn(ab, "failed to set tx filter for monitor buf %d\n", ret); + goto out; + } + + ath12k_dbg(ab, ATH12K_DBG_WMI, "pktlog filter %d hybrid mode %s\n", + filter, ((mode == ATH12K_PKTLOG_MODE_FULL) ? "full" : "lite")); + + ar->debug.pktlog_filter = filter; + ar->debug.pktlog_mode = mode; +out: + return ret; +} + +static ssize_t ath12k_write_pktlog_filter(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + struct ath12k_base *ab = ar->ab; + struct htt_rx_ring_tlv_filter tlv_filter = {0}; + u32 rx_filter = 0, filter, mode; + u8 buf[128] = {0}; + int ret, hybrid_enable, rx_buf_sz; + ssize_t rc; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto out; + } + + rc = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (rc < 0) { + ret = rc; + goto out; + } + buf[rc] = '\0'; + + ret = sscanf(buf, "0x%x %u %d", &filter, &mode, &hybrid_enable); + if (ret < 2) { + ret = -EINVAL; + goto out; + } + + if (ret == 2) + hybrid_enable = 0; + + if ((filter & ATH12K_PKTLOG_RX) && hybrid_enable) { + ret = -EINVAL; + ath12k_warn(ab, + "Invalid configuration. Hybrid mode is only applicable when tx or lite pktlog is used"); + goto out; + } + + /* TODO : Hybrid mode is not supported yet. + * Bring up will happen once the FW design is finalised. + */ + if (hybrid_enable) + filter |= ATH12K_PKTLOG_HYBRID; + ret = ath12k_wmi_pdev_pktlog_enable(ar, filter); + if (ret) { + ath12k_warn(ab, + "failed to enable pktlog filter %x: %d\n", + ar->debug.pktlog_filter, ret); + goto out; + } + + /* + * TODO : Filter setting needs to be revisited after enabling TX monitor + */ + + /* Clear rx filter set for monitor mode and rx status */ + tlv_filter.offset_valid = false; + + ret = ath12k_pktlog_rx_filter_setting(ar, &tlv_filter); + if (ret) { + ath12k_warn(ab, "failed to clear rx filter for monitor dest ring %d\n", + ret); + goto out; + } + + if (filter & ATH12K_PKTLOG_HYBRID) { + ret = ath12k_pktlog_enable_hybrid_mode(ar, filter, mode); + if (ret) { + ath12k_warn(ab, "failed to enable pktlog in hybrid mode\n"); + } else { + ret = count; + } + goto out; + } + +#define HTT_RX_FILTER_TLV_LITE_MODE \ + (HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ + HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \ + HTT_RX_FILTER_TLV_FLAGS_MPDU_START) + + if (mode == ATH12K_PKTLOG_MODE_FULL) { + rx_filter = HTT_RX_FILTER_TLV_LITE_MODE | + HTT_RX_FILTER_TLV_FLAGS_MSDU_START | + HTT_RX_FILTER_TLV_FLAGS_MSDU_END | + HTT_RX_FILTER_TLV_FLAGS_MPDU_END | + HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | + HTT_RX_FILTER_TLV_FLAGS_ATTENTION; + rx_buf_sz = DP_RXDMA_REFILL_RING_SIZE; + } else if (mode == ATH12K_PKTLOG_MODE_LITE) { + ret = ath12k_dp_tx_htt_h2t_ppdu_stats_req(ar, + HTT_PPDU_STATS_TAG_PKTLOG); + if (ret) { + ath12k_err(ab, "failed to enable pktlog lite: %d\n", ret); + goto out; + } + + rx_filter = HTT_RX_FILTER_TLV_LITE_MODE; + rx_buf_sz = DP_RX_BUFFER_SIZE_LITE; + } else { + rx_buf_sz = DP_RX_BUFFER_SIZE; + tlv_filter = ath12k_mac_mon_status_filter_default; + rx_filter = tlv_filter.rx_filter; + + ret = ath12k_dp_tx_htt_h2t_ppdu_stats_req(ar, + HTT_PPDU_STATS_TAG_DEFAULT); + if (ret) { + ath12k_err(ab, "failed to send htt ppdu stats req: %d\n", + ret); + goto out; + } + } + + tlv_filter.rx_filter = rx_filter; + if (rx_filter) { + tlv_filter.pkt_filter_flags0 = + HTT_RX_FP_MGMT_FILTER_FLAGS0 | + HTT_RX_MO_MGMT_FILTER_FLAGS0; + tlv_filter.pkt_filter_flags1 = + HTT_RX_FP_MGMT_FILTER_FLAGS1 | + HTT_RX_MO_MGMT_FILTER_FLAGS1; + tlv_filter.pkt_filter_flags2 = + HTT_RX_FP_CTRL_FILTER_FLASG2 | + HTT_RX_MO_CTRL_FILTER_FLASG2; + tlv_filter.pkt_filter_flags3 = + HTT_RX_FP_CTRL_FILTER_FLASG3 | + HTT_RX_MO_CTRL_FILTER_FLASG3 | + HTT_RX_FP_DATA_FILTER_FLASG3 | + HTT_RX_MO_DATA_FILTER_FLASG3; + } + + ret = ath12k_pktlog_rx_filter_setting(ar, &tlv_filter); + if (ret) { + ath12k_warn(ab, "failed to set rx filter for monitor dest ring %d\n", + ret); + goto out; + } + + ath12k_dbg(ab, ATH12K_DBG_WMI, "pktlog filter %d mode %s\n", + filter, ((mode == ATH12K_PKTLOG_MODE_FULL) ? "full" : "lite")); + + ar->debug.pktlog_filter = filter; + ar->debug.pktlog_mode = mode; + ret = count; + +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath12k_read_pktlog_filter(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) + +{ + char buf[32] = {0}; + struct ath12k *ar = file->private_data; + int len = 0; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%08x %08x\n", + ar->debug.pktlog_filter, + ar->debug.pktlog_mode); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_pktlog_filter = { + .read = ath12k_read_pktlog_filter, + .write = ath12k_write_pktlog_filter, + .open = simple_open +}; + +#define SEGMENT_ID GENMASK(1,0) +#define CHRIP_ID BIT(2) +#define OFFSET GENMASK(10,3) +#define DETECTOR_ID GENMASK(12,11) +#define FHSS BIT(14) + +static ssize_t ath12k_write_simulate_radar(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int ret; + u32 radar_params; + u8 agile = 0, segment = 0, radar_type = 0, chirp = 0, fhss = 0; + int offset = 0; + int len; + char buf[64], *token, *sptr; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) { + return -EFAULT; + } + + /* For backward compatibility */ + if (len <= 2) + goto send_cmd; + + buf[len] = '\0'; + sptr = buf; + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + + if (kstrtou8(token, 16, &segment)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + + if (kstrtou8(token, 16, &radar_type)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + + if (kstrtoint(token, 10, &offset)) + return -EINVAL; + + token = strsep(&sptr, " "); + if (!token) + return -EINVAL; + + if (kstrtou8(token, 16, &agile)) + return -EINVAL; + + if ((segment > 1) || (radar_type > 2) || (agile > 2)) + return -EINVAL; + + if (agile && ar->agile_chandef.chan == NULL) + return -EINVAL; + +send_cmd: + /* radar_type 1 is for chirp, radar_type 2 is for FHSS */ + if (radar_type == 1) + chirp = 1; + if (radar_type == 2) + fhss = 1; + + radar_params = u32_encode_bits(segment, SEGMENT_ID) | + u32_encode_bits(chirp, CHRIP_ID) | + u32_encode_bits(offset, OFFSET) | + u32_encode_bits(agile, DETECTOR_ID) | + u32_encode_bits(fhss, FHSS); + + ret = ath12k_wmi_simulate_radar(ar, radar_params); + if (ret) + return ret; + + return count; +} + +static const struct file_operations fops_simulate_radar = { + .write = ath12k_write_simulate_radar, + .open = simple_open +}; + +static int ath12k_get_tpc_ctl_mode_idx(struct wmi_tpc_stats_event *tpc_stats, + enum wmi_tpc_pream_bw pream_bw, int *mode_idx) +{ + u8 band; + + band = (((tpc_stats->tpc_config.chan_freq) > 5920) ? NL80211_BAND_6GHZ : + (((tpc_stats->tpc_config.chan_freq) > 4800) ? NL80211_BAND_5GHZ : NL80211_BAND_2GHZ)); + + if (band == NL80211_BAND_5GHZ || band == NL80211_BAND_6GHZ) { + switch (pream_bw) { + case WMI_TPC_PREAM_HT20: + case WMI_TPC_PREAM_VHT20: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HT_VHT20_5G_6G; + break; + case WMI_TPC_PREAM_HE20: + case WMI_TPC_PREAM_EHT20: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HE_EHT20_5G_6G; + break; + case WMI_TPC_PREAM_HT40: + case WMI_TPC_PREAM_VHT40: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HT_VHT40_5G_6G; + break; + case WMI_TPC_PREAM_HE40: + case WMI_TPC_PREAM_EHT40: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HE_EHT40_5G_6G; + break; + case WMI_TPC_PREAM_VHT80: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_VHT80_5G_6G; + break; + case WMI_TPC_PREAM_EHT60: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_EHT80_SU_PUNC20; + break; + case WMI_TPC_PREAM_HE80: + case WMI_TPC_PREAM_EHT80: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HE_EHT80_5G_6G; + break; + case WMI_TPC_PREAM_VHT160: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_VHT160_5G_6G; + break; + case WMI_TPC_PREAM_EHT120: + case WMI_TPC_PREAM_EHT140: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_EHT160_SU_PUNC20; + break; + case WMI_TPC_PREAM_HE160: + case WMI_TPC_PREAM_EHT160: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HE_EHT160_5G_6G; + break; + case WMI_TPC_PREAM_EHT200: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_EHT320_SU_PUNC120; + break; + case WMI_TPC_PREAM_EHT240: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_EHT320_SU_PUNC80; + break; + case WMI_TPC_PREAM_EHT280: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_EHT320_SU_PUNC40; + break; + case WMI_TPC_PREAM_EHT320: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HE_EHT320_5G_6G; + break; + default: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_LEGACY_5G_6G; /* for 5G and 6G, default case will be for OFDM */ + break; + } + } else { + switch (pream_bw) { + case WMI_TPC_PREAM_OFDM: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_LEGACY_2G; + break; + case WMI_TPC_PREAM_HT20: + case WMI_TPC_PREAM_VHT20: + case WMI_TPC_PREAM_HE20: + case WMI_TPC_PREAM_EHT20: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HT20_2G; + break; + case WMI_TPC_PREAM_HT40: + case WMI_TPC_PREAM_VHT40: + case WMI_TPC_PREAM_HE40: + case WMI_TPC_PREAM_EHT40: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_HT40_2G; + break; + default: + *mode_idx = ATH12K_TPC_STATS_CTL_MODE_CCK_2G; //for 2G, default case will be CCK + break; + } + } + + return 0; +} + +static s16 ath12k_tpc_get_rate(struct ath12k *ar, + struct wmi_tpc_stats_event *tpc_stats, + u32 rate_idx, u32 num_chains, u32 rate_code, + enum wmi_tpc_pream_bw pream_bw, + enum ath12k_dbg_tpc_stats_type type, + u32 eht_rate_idx) +{ + s8 rates_ctl_min, tpc_ctl; + u8 chain_idx, stm_idx, num_streams; + s16 rates, tpc, reg_pwr; + u32 tot_nss, tot_modes, txbf_on_off; + u32 index_offset1, index_offset2, index_offset3; + int mode, ret, txbf_enabled; + bool is_mu; + + num_streams = 1 + ATH12K_HW_NSS(rate_code); + chain_idx = num_chains - 1; + stm_idx = num_streams - 1; + mode = -1; + + ret = ath12k_get_tpc_ctl_mode_idx(tpc_stats, pream_bw, &mode); + if (ret) { + ath12k_warn(ar->ab, "Invalid mode index received\n"); + tpc = TPC_INVAL; + goto out; + } + + if (num_chains < num_streams) { + tpc = TPC_INVAL; + goto out; + } + + if (__le32_to_cpu(tpc_stats->tpc_config.num_tx_chain) <= 1) { + tpc = TPC_INVAL; + goto out; + } + + if (type == ATH12K_DBG_TPC_STATS_MU_WITH_TXBF || + type == ATH12K_DBG_TPC_STATS_SU_WITH_TXBF) + txbf_enabled = 1; + else + txbf_enabled = 0; + + if (type == ATH12K_DBG_TPC_STATS_MU_WITH_TXBF || + type == ATH12K_DBG_TPC_STATS_MU) { + is_mu = true; + } else { + is_mu = false; + } + + /* Below is the min calculation of ctl array, rates array and + * regulator power table. tpc is minimum of all 3 + */ + if (pream_bw >= WMI_TPC_PREAM_EHT20 && pream_bw <= WMI_TPC_PREAM_EHT320) { + if (is_mu) { + rates = FIELD_GET(ATH12K_TPC_RATE_ARRAY_MU, + le16_to_cpu (tpc_stats->rates_array2.rate_array[eht_rate_idx])); + } else { + rates = FIELD_GET(ATH12K_TPC_RATE_ARRAY_SU, + le16_to_cpu (tpc_stats->rates_array2.rate_array[eht_rate_idx])); + } + } else { + if (is_mu) { + rates = FIELD_GET(ATH12K_TPC_RATE_ARRAY_MU, + le16_to_cpu (tpc_stats->rates_array1.rate_array[rate_idx])); + } else { + rates = FIELD_GET(ATH12K_TPC_RATE_ARRAY_SU, + le16_to_cpu (tpc_stats->rates_array1.rate_array[rate_idx])); + } + } + + if (tpc_stats->tlvs_rcvd & WMI_TPC_CTL_PWR_ARRAY) { + tot_nss = tpc_stats->ctl_array.tpc_ctl_pwr.d1; + tot_modes = tpc_stats->ctl_array.tpc_ctl_pwr.d2; + txbf_on_off = tpc_stats->ctl_array.tpc_ctl_pwr.d3; + index_offset1 = txbf_on_off * tot_modes * tot_nss; + index_offset2 = tot_modes * tot_nss; + index_offset3 = tot_nss; + + tpc_ctl = *(tpc_stats->ctl_array.ctl_pwr_table + + chain_idx * index_offset1 + txbf_enabled * index_offset2 + + mode * index_offset3 + stm_idx); + } else { + tpc_ctl = TPC_MAX; + ath12k_info(ar->ab, + "ctl array for tpc stats not received from fw\n"); + } + + rates_ctl_min = min_t(s16, rates, tpc_ctl); + + reg_pwr = le16_to_cpu(tpc_stats->max_reg_allowed_power.reg_pwr_array[chain_idx]); + + if (reg_pwr < 0) + reg_pwr = TPC_INVAL; + + tpc = min_t(s16, rates_ctl_min, reg_pwr); + + /* MODULATION_LIMIT is the maximum power limit,tpc should not exceed + * modulation limt even if min tpc of all three array is greater + * modulation limit + */ + tpc = min_t(s16, tpc, MODULATION_LIMIT); + +out: + return tpc; +} + +u16 ath12k_get_ratecode(u16 pream_idx, u16 nss, u16 mcs_rate) +{ + u16 mode_type = ~0; + + /* Below assignments are just for printing purpose only */ + switch (pream_idx) { + case WMI_TPC_PREAM_CCK: + mode_type = WMI_RATE_PREAMBLE_CCK; + break; + case WMI_TPC_PREAM_OFDM: + mode_type = WMI_RATE_PREAMBLE_OFDM; + break; + case WMI_TPC_PREAM_HT20: + case WMI_TPC_PREAM_HT40: + mode_type = WMI_RATE_PREAMBLE_HT; + break; + case WMI_TPC_PREAM_VHT20: + case WMI_TPC_PREAM_VHT40: + case WMI_TPC_PREAM_VHT80: + case WMI_TPC_PREAM_VHT160: + mode_type = WMI_RATE_PREAMBLE_VHT; + break; + case WMI_TPC_PREAM_HE20: + case WMI_TPC_PREAM_HE40: + case WMI_TPC_PREAM_HE80: + case WMI_TPC_PREAM_HE160: + mode_type = WMI_RATE_PREAMBLE_HE; + break; + case WMI_TPC_PREAM_EHT20: + case WMI_TPC_PREAM_EHT40: + case WMI_TPC_PREAM_EHT60: + case WMI_TPC_PREAM_EHT80: + case WMI_TPC_PREAM_EHT120: + case WMI_TPC_PREAM_EHT140: + case WMI_TPC_PREAM_EHT160: + case WMI_TPC_PREAM_EHT200: + case WMI_TPC_PREAM_EHT240: + case WMI_TPC_PREAM_EHT280: + case WMI_TPC_PREAM_EHT320: + mode_type = WMI_RATE_PREAMBLE_EHT; + if (mcs_rate == 0 || mcs_rate == 1) + mcs_rate += 14; + else + mcs_rate -= 2; + break; + default: + return mode_type; + } + + return ((mode_type << 8) | ((nss & 0x7) << 5) | (mcs_rate & 0x1F)); +} + +static bool ath12k_he_supports_extra_mcs(struct ath12k *ar, int freq) +{ + struct ath12k_pdev_cap *cap = &ar->pdev->cap; + struct ath12k_band_cap *cap_band; + bool extra_mcs_supported; + + if (freq <= ATH12K_2G_MAX_FREQUENCY) + cap_band = &cap->band[NL80211_BAND_2GHZ]; + else if (freq <= ATH12K_5G_MAX_FREQUENCY) + cap_band = &cap->band[NL80211_BAND_5GHZ]; + else + cap_band = &cap->band[NL80211_BAND_6GHZ]; + + extra_mcs_supported = FIELD_GET(HE_EXTRA_MCS_SUPPORT, cap_band->he_cap_info[1]); + return extra_mcs_supported; +} + +static int ath12k_tpc_fill_pream(struct ath12k *ar, char *buf, int buf_len, int len, + enum wmi_tpc_pream_bw pream_bw, u32 max_rix, int max_nss, int max_rates, + int pream_type, enum ath12k_dbg_tpc_stats_type tpc_type, + int rate_idx, int eht_rate_idx) +{ + int nss, rates, chains; + u8 active_tx_chains; + u16 rate_code; + s16 tpc; + struct wmi_tpc_stats_event *tpc_stats = ar->tpc_stats; + + static const char *const pream_str[] = { + [WMI_TPC_PREAM_CCK] = "CCK", + [WMI_TPC_PREAM_OFDM] = "OFDM", + [WMI_TPC_PREAM_HT20] = "HT20", + [WMI_TPC_PREAM_HT40] = "HT40", + [WMI_TPC_PREAM_VHT20] = "VHT20", + [WMI_TPC_PREAM_VHT40] = "VHT40", + [WMI_TPC_PREAM_VHT80] = "VHT80", + [WMI_TPC_PREAM_VHT160] = "VHT160", + [WMI_TPC_PREAM_HE20] = "HE20", + [WMI_TPC_PREAM_HE40] = "HE40", + [WMI_TPC_PREAM_HE80] = "HE80", + [WMI_TPC_PREAM_HE160] = "HE160", + [WMI_TPC_PREAM_EHT20] = "EHT20", + [WMI_TPC_PREAM_EHT40] = "EHT40", + [WMI_TPC_PREAM_EHT60] = "EHT60", + [WMI_TPC_PREAM_EHT80] = "EHT80", + [WMI_TPC_PREAM_EHT120] = "EHT120", + [WMI_TPC_PREAM_EHT140] = "EHT140", + [WMI_TPC_PREAM_EHT160] = "EHT160", + [WMI_TPC_PREAM_EHT200] = "EHT200", + [WMI_TPC_PREAM_EHT240] = "EHT240", + [WMI_TPC_PREAM_EHT280] = "EHT280", + [WMI_TPC_PREAM_EHT320] = "EHT320"}; + + active_tx_chains = ar->num_tx_chains; + + for (nss = 0; nss < max_nss; nss++) { + for (rates = 0; rates < max_rates; rates++, rate_idx++, max_rix++) { + /* FW send extra MCS(10&11) for VHT and HE rates, + * this is not used. Hence skipping it here + */ + if (pream_type == WMI_RATE_PREAMBLE_VHT && + rates > ATH12K_VHT_MCS_MAX) + continue; + + if (pream_type == WMI_RATE_PREAMBLE_HE && + rates > ATH12K_HE_MCS_MAX) + continue; + + if (pream_type == WMI_RATE_PREAMBLE_EHT && + rates > ATH12K_EHT_MCS_MAX) + continue; + + rate_code = ath12k_get_ratecode(pream_bw, nss, rates); + len += scnprintf(buf + len, buf_len - len, + "%d\t %s\t 0x%03x\t", max_rix, + pream_str[pream_bw], rate_code); + + for (chains = 0; chains < active_tx_chains; chains++) { + if (nss > chains) { + len += scnprintf(buf + len, + buf_len - len, + "\t%s", "NA"); + } else { + tpc = ath12k_tpc_get_rate(ar, tpc_stats, rate_idx, + chains + 1, rate_code, + pream_bw, tpc_type, eht_rate_idx); + + if (tpc == TPC_INVAL) { + len += scnprintf(buf + len, + buf_len - len, "\tNA"); + } else { + len += scnprintf(buf + len, + buf_len - len, "\t%d", + tpc); + } + } + } + len += scnprintf(buf + len, buf_len - len, "\n"); + + if (pream_type == WMI_RATE_PREAMBLE_EHT) + /*For fetching the next eht rates pwr from rates array2*/ + ++eht_rate_idx; + } + } + + return len; +} + +static int ath12k_tpc_stats_print(struct ath12k *ar, + struct wmi_tpc_stats_event *tpc_stats, + char *buf, size_t len, enum ath12k_dbg_tpc_stats_type type) +{ + u32 i, j = 1, eht_idx = 0, pream_idx = 0, rate_pream_idx = 0, total_rates = 0, max_rix = 0; + u8 nss, active_tx_chains; + size_t buf_len = ATH12K_TPC_STATS_BUF_SIZE; + bool he_ext_mcs; + static const char *const type_str[ATH12K_DBG_TPC_MAX_STATS] = { + [ATH12K_DBG_TPC_STATS_SU] = "SU", + [ATH12K_DBG_TPC_STATS_SU_WITH_TXBF] = "SU WITH TXBF", + [ATH12K_DBG_TPC_STATS_MU] = "MU", + [ATH12K_DBG_TPC_STATS_MU_WITH_TXBF] = "MU WITH TXBF"}; + + u8 max_rates[WMI_TPC_PREAM_MAX] = { + [WMI_TPC_PREAM_CCK] = ATH12K_CCK_RATES, + [WMI_TPC_PREAM_OFDM] = ATH12K_OFDM_RATES, + [WMI_TPC_PREAM_HT20] = ATH12K_HT_RATES, + [WMI_TPC_PREAM_HT40] = ATH12K_HT_RATES, + [WMI_TPC_PREAM_VHT20] = ATH12K_VHT_RATES, + [WMI_TPC_PREAM_VHT40] = ATH12K_VHT_RATES, + [WMI_TPC_PREAM_VHT80] = ATH12K_VHT_RATES, + [WMI_TPC_PREAM_VHT160] = ATH12K_VHT_RATES, + [WMI_TPC_PREAM_HE20] = ATH12K_HE_RATES, + [WMI_TPC_PREAM_HE40] = ATH12K_HE_RATES, + [WMI_TPC_PREAM_HE80] = ATH12K_HE_RATES, + [WMI_TPC_PREAM_HE160] = ATH12K_HE_RATES, + [WMI_TPC_PREAM_EHT20] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT40] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT60] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT80] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT120] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT140] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT160] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT200] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT240] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT280] = ATH12K_EHT_RATES, + [WMI_TPC_PREAM_EHT320] = ATH12K_EHT_RATES}; + + u8 max_nss[WMI_TPC_PREAM_MAX] = { + [WMI_TPC_PREAM_CCK] = ATH12K_NSS_1, + [WMI_TPC_PREAM_OFDM] = ATH12K_NSS_1, + [WMI_TPC_PREAM_HT20] = ATH12K_NSS_4, + [WMI_TPC_PREAM_HT40] = ATH12K_NSS_4, + [WMI_TPC_PREAM_VHT20] = ATH12K_NSS_8, + [WMI_TPC_PREAM_VHT40] = ATH12K_NSS_8, + [WMI_TPC_PREAM_VHT80] = ATH12K_NSS_8, + [WMI_TPC_PREAM_VHT160] = ATH12K_NSS_4, + [WMI_TPC_PREAM_HE20] = ATH12K_NSS_8, + [WMI_TPC_PREAM_HE40] = ATH12K_NSS_8, + [WMI_TPC_PREAM_HE80] = ATH12K_NSS_8, + [WMI_TPC_PREAM_HE160] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT20] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT40] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT60] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT80] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT120] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT140] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT160] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT200] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT240] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT280] = ATH12K_NSS_4, + [WMI_TPC_PREAM_EHT320] = ATH12K_NSS_4}; + + u16 rate_idx[WMI_TPC_PREAM_MAX] = {0}, + eht_rate_idx[WMI_TPC_PREAM_MAX] = {0}; + + static const u8 pream_type[WMI_TPC_PREAM_MAX] = { + [WMI_TPC_PREAM_CCK] = WMI_RATE_PREAMBLE_CCK, + [WMI_TPC_PREAM_OFDM] = WMI_RATE_PREAMBLE_OFDM, + [WMI_TPC_PREAM_HT20] = WMI_RATE_PREAMBLE_HT, + [WMI_TPC_PREAM_HT40] = WMI_RATE_PREAMBLE_HT, + [WMI_TPC_PREAM_VHT20] = WMI_RATE_PREAMBLE_VHT, + [WMI_TPC_PREAM_VHT40] = WMI_RATE_PREAMBLE_VHT, + [WMI_TPC_PREAM_VHT80] = WMI_RATE_PREAMBLE_VHT, + [WMI_TPC_PREAM_VHT160] = WMI_RATE_PREAMBLE_VHT, + [WMI_TPC_PREAM_HE20] = WMI_RATE_PREAMBLE_HE, + [WMI_TPC_PREAM_HE40] = WMI_RATE_PREAMBLE_HE, + [WMI_TPC_PREAM_HE80] = WMI_RATE_PREAMBLE_HE, + [WMI_TPC_PREAM_HE160] = WMI_RATE_PREAMBLE_HE, + [WMI_TPC_PREAM_EHT20] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT40] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT60] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT80] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT120] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT140] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT160] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT200] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT240] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT280] = WMI_RATE_PREAMBLE_EHT, + [WMI_TPC_PREAM_EHT320] = WMI_RATE_PREAMBLE_EHT}; + + active_tx_chains = ar->num_tx_chains; + he_ext_mcs = ath12k_he_supports_extra_mcs(ar, tpc_stats->tpc_config.chan_freq); + + /* mcs 12&13 is sent by FW for certain HWs in rate array, skipping it as + * it is not supported + */ + if (he_ext_mcs) { + for (i = WMI_TPC_PREAM_HE20; i <= WMI_TPC_PREAM_HE160; ++i) + max_rates[i] = ATH12K_HE_RATES; + } + + if (type == ATH12K_DBG_TPC_STATS_MU || + type == ATH12K_DBG_TPC_STATS_MU_WITH_TXBF) { + pream_idx = WMI_TPC_PREAM_VHT20; + + for (i = WMI_TPC_PREAM_CCK; i <= WMI_TPC_PREAM_HT40; ++i) { + max_rix += max_nss[i] * max_rates[i]; + } + } + + /* Enumerate all the rate indices */ + for (i = rate_pream_idx + 1 ; i < WMI_TPC_PREAM_MAX; i++) { + nss = (max_nss[i - 1] < tpc_stats->tpc_config.num_tx_chain ? + max_nss[i - 1] : tpc_stats->tpc_config.num_tx_chain); + + rate_idx[i] = rate_idx[i - 1] + max_rates[i - 1] * nss; + + if (pream_type[i] == WMI_RATE_PREAMBLE_EHT) { + eht_rate_idx[j] = eht_rate_idx[j - 1] + max_rates[i] * nss; + /*For Filling the next eht_rate_idx for fetch rates pwr info rates array2*/ + ++j; + } + } + + for (i = 0 ; i < WMI_TPC_PREAM_MAX; i++) { + nss = (max_nss[i] < tpc_stats->tpc_config.num_tx_chain ? + max_nss[i] : tpc_stats->tpc_config.num_tx_chain); + total_rates += max_rates[i] * nss; + } + + len += scnprintf(buf + len, buf_len - len, + "No.of rates-%d\n", total_rates); + + len += scnprintf(buf + len, buf_len - len, + "**************** %s ****************\n", + type_str[type]); + len += scnprintf(buf + len, buf_len - len, + "\t\t\t\tTPC values for Active chains\n"); + len += scnprintf(buf + len, buf_len - len, + "Rate idx Preamble Rate code"); + + for (i = 1; i <= active_tx_chains; ++i) { + len += scnprintf(buf + len, buf_len - len, + "\t%d-Chain", i); + } + + len += scnprintf(buf + len, buf_len - len, "\n"); + + for (i = pream_idx; i < WMI_TPC_PREAM_MAX; i++) { + if (tpc_stats->tpc_config.chan_freq <= 2483) { + if (i == WMI_TPC_PREAM_VHT80 || + i == WMI_TPC_PREAM_VHT160 || + i == WMI_TPC_PREAM_HE80 || + i == WMI_TPC_PREAM_HE160 || + (i >= WMI_TPC_PREAM_EHT60 && + i <= WMI_TPC_PREAM_EHT320)) { + max_rix += max_nss[i] * max_rates[i]; + continue; + } + } else { + if (i == WMI_TPC_PREAM_CCK) { + max_rix += max_rates[i]; + continue; + } + } + + nss = (max_nss[i] < ar->num_tx_chains ? max_nss[i] : ar->num_tx_chains); + + if (!(tpc_stats->tpc_config.caps & (1 << ATH12K_TPC_STATS_SUPPORT_BE_PUNC))) { + if (i == WMI_TPC_PREAM_EHT60 || i == WMI_TPC_PREAM_EHT120 || + i == WMI_TPC_PREAM_EHT140 || i == WMI_TPC_PREAM_EHT200 || + i == WMI_TPC_PREAM_EHT240 || i == WMI_TPC_PREAM_EHT280) { + max_rix += max_nss[i] * max_rates[i]; + continue; + } + } + + len = ath12k_tpc_fill_pream(ar, buf, buf_len, len, i, max_rix, nss, + max_rates[i], pream_type[i], + type, rate_idx[i], eht_rate_idx[eht_idx]); + + if (pream_type[i] == WMI_RATE_PREAMBLE_EHT) + /*For fetch the next index eht rates from rates array2*/ + ++eht_idx; + + max_rix += max_nss[i] * max_rates[i]; + } + return len; +} + +static void ath12k_tpc_stats_fill(struct ath12k *ar, + struct wmi_tpc_stats_event *tpc_stats, + char *buf) +{ + struct wmi_tpc_configs *tpc; + size_t len = 0; + size_t buf_len = ATH12K_TPC_STATS_BUF_SIZE; + + spin_lock_bh(&ar->data_lock); + if (!tpc_stats) { + ath12k_warn(ar->ab, "failed to find tpc stats\n"); + goto unlock; + } + + tpc = &tpc_stats->tpc_config; + len += scnprintf(buf + len, buf_len - len, "\n"); + len += scnprintf(buf + len, buf_len - len, + "*************** TPC config **************\n"); + len += scnprintf(buf + len, buf_len - len, + "* powers are in 0.25 dBm steps\n"); + len += scnprintf(buf + len, buf_len - len, + "reg domain-%d\t\tchan freq-%d\n", + tpc->reg_domain, tpc->chan_freq); + len += scnprintf(buf + len, buf_len - len, + "power limit-%d\t\tmax reg-domain Power-%d\n", + (tpc->twice_max_reg_power) / 2, tpc->power_limit); + len += scnprintf(buf + len, buf_len - len, + "No.of tx chain-%d\t", + ar->num_tx_chains); + + ath12k_tpc_stats_print(ar, tpc_stats, buf, len, + ar->tpc_stats_type); + +unlock: + spin_unlock_bh(&ar->data_lock); +} + +static int ath12k_debug_tpc_stats_request(struct ath12k *ar) +{ + int ret; + unsigned long time_left; + struct ath12k_base *ab = ar->ab; + + lockdep_assert_held(&ar->conf_mutex); + + reinit_completion(&ar->tpc_complete); + + spin_lock_bh(&ar->data_lock); + ar->tpc_request = true; + spin_unlock_bh(&ar->data_lock); + + ret = ath12k_wmi_pdev_get_tpc_table_cmdid(ar); + if (ret) { + ath12k_warn(ab, "failed to request tpc table cmdid: %d\n", ret); + goto out; + } + + time_left = wait_for_completion_timeout(&ar->tpc_complete, + TPC_STATS_WAIT_TIME); + + if (time_left == 0) + ret = -ETIMEDOUT; + +out: + spin_lock_bh(&ar->data_lock); + ar->tpc_request = false; + spin_unlock_bh(&ar->data_lock); + + return ret; +} + +static int ath12k_tpc_stats_open(struct inode *inode, struct file *file) +{ + struct ath12k *ar = inode->i_private; + void *buf; + int ret; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ath12k_warn(ar->ab, "Interface not up\n"); + ret = -ENETDOWN; + goto err_unlock; + } + + buf = kmalloc(ATH12K_TPC_STATS_BUF_SIZE, GFP_KERNEL); + if (!buf) { + ret = -ENOMEM; + goto err_unlock; + } + + ret = ath12k_debug_tpc_stats_request(ar); + if (ret) { + ath12k_warn(ar->ab, "failed to request tpc stats: %d\n", + ret); + spin_lock_bh(&ar->data_lock); + ath12k_wmi_free_tpc_stats_mem(ar); + spin_unlock_bh(&ar->data_lock); + goto err_free; + } + + ath12k_tpc_stats_fill(ar, ar->tpc_stats, buf); + file->private_data = buf; + + spin_lock_bh(&ar->data_lock); + ath12k_wmi_free_tpc_stats_mem(ar); + spin_unlock_bh(&ar->data_lock); + mutex_unlock(&ar->conf_mutex); + + return 0; + +err_free: + kfree(buf); + +err_unlock: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static int ath12k_tpc_stats_release(struct inode *inode, + struct file *file) +{ + kfree(file->private_data); + return 0; +} + +static ssize_t ath12k_tpc_stats_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + const char *buf = file->private_data; + unsigned int len = strlen(buf); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_read_tpc_stats_type(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[32]; + size_t len; + + len = scnprintf(buf, sizeof(buf), "%u\n", ar->tpc_stats_type); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_write_tpc_stats_type(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u8 type; + int ret; + + ret = kstrtou8_from_user(user_buf, count, 0, &type); + if (ret) + return ret; + + if (type >= ATH12K_DBG_TPC_MAX_STATS) + return -E2BIG; + + ar->tpc_stats_type = type; + + ret = count; + + return ret; +} + +static const struct file_operations fops_tpc_stats_type = { + .read = ath12k_read_tpc_stats_type, + .write = ath12k_write_tpc_stats_type, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static const struct file_operations fops_tpc_stats = { + .open = ath12k_tpc_stats_open, + .release = ath12k_tpc_stats_release, + .read = ath12k_tpc_stats_read, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_write_simulate_awgn(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int ret; + u32 chan_bw_interference_bitmap; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto exit; + } + + if (kstrtou32_from_user(user_buf, count, 0, &chan_bw_interference_bitmap)) { + mutex_unlock(&ar->conf_mutex); + return -EINVAL; + } + + ret = ath12k_wmi_simulate_awgn(ar, chan_bw_interference_bitmap); + if (ret) + goto exit; + + ret = count; + +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_simulate_awgn = { + .write = ath12k_write_simulate_awgn, + .open = simple_open +}; + +static ssize_t ath12k_dump_mgmt_stats(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + struct ath12k_link_vif *arvif = NULL; + struct ath12k_mgmt_frame_stats *mgmt_stats; + int len = 0, ret, i; + int size = (TARGET_NUM_VDEVS - 1) * 1500; + char *buf; + const char *mgmt_frm_type[ATH12K_STATS_MGMT_FRM_TYPE_MAX-1] = { + "assoc_req", "assoc_resp", + "reassoc_req", "reassoc_resp", + "probe_req", "probe_resp", + "timing_advertisement", "reserved", + "beacon", "atim", "disassoc", + "auth", "deauth", "action", "action_no_ack"}; + + if (ar->state != ATH12K_STATE_ON) + return -ENETDOWN; + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + mutex_lock(&ar->conf_mutex); + spin_lock_bh(&ar->data_lock); + + list_for_each_entry (arvif, &ar->arvifs, list) { + if (!arvif) + break; + + if (arvif->ahvif->vdev_type == WMI_VDEV_TYPE_MONITOR) + continue; + mgmt_stats = &arvif->ahvif->mgmt_stats; + len += scnprintf(buf + len, size - len, "MGMT frame stats for vdev %u :\n", arvif->vdev_id); + len += scnprintf(buf + len, size - len, " TX stats :\n "); + len += scnprintf(buf + len, size - len, " Success frames:\n"); + for (i = 0; i < ATH12K_STATS_MGMT_FRM_TYPE_MAX-1; i++) + len += scnprintf(buf + len, size - len, " %s: %d\n", + mgmt_frm_type[i], mgmt_stats->tx_succ_cnt[i]); + + len += scnprintf(buf + len, size - len, " Failed frames:\n"); + + for (i = 0; i < ATH12K_STATS_MGMT_FRM_TYPE_MAX-1; i++) + len += scnprintf(buf + len, size - len, " %s: %d\n", + mgmt_frm_type[i], mgmt_stats->tx_fail_cnt[i]); + + len += scnprintf(buf + len, size - len, " RX stats :\n"); + len += scnprintf(buf + len, size - len, " Success frames:\n"); + for (i = 0; i < ATH12K_STATS_MGMT_FRM_TYPE_MAX-1; i++) + len += scnprintf(buf + len, size - len, " %s: %d\n", + mgmt_frm_type[i], mgmt_stats->rx_cnt[i]); + + len += scnprintf(buf + len, size - len, " Tx completion stats :\n"); + len += scnprintf(buf + len, size - len, " success completions:\n"); + + for (i = 0; i < ATH12K_STATS_MGMT_FRM_TYPE_MAX-1; i++) + len += scnprintf(buf + len, size - len, " %s: %d\n", + mgmt_frm_type[i], mgmt_stats->tx_compl_succ[i]); + + len += scnprintf(buf + len, size - len, " failure completions:\n"); + + for (i = 0; i < ATH12K_STATS_MGMT_FRM_TYPE_MAX-1; i++) + len += scnprintf(buf + len, size - len, " %s: %d\n", mgmt_frm_type[i], mgmt_stats->tx_compl_fail[i]); + } + + spin_unlock_bh(&ar->data_lock); + + if (len > size) + len = size; + + ret = simple_read_from_buffer(ubuf, count, ppos, buf, len); + mutex_unlock(&ar->conf_mutex); + kfree(buf); + return ret; +} + +static const struct file_operations fops_dump_mgmt_stats = { + .read = ath12k_dump_mgmt_stats, + .open = simple_open +}; + +static ssize_t ath12k_athdiag_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u8 *buf; + int ret; + + if (*ppos <= 0) + return -EINVAL; + + if (!count) + return 0; + + buf = vmalloc(count); + if (!buf) { + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + + ret = ath12k_qmi_mem_read(ar->ab, *ppos, buf, count); + if (ret < 0) { + ath12k_warn(ar->ab, "failed to read address 0x%08x via diagnose window from debugfs: %d\n", + (u32)(*ppos), ret); + goto exit; + } + + ret = copy_to_user(user_buf, buf, count); + if (ret) { + ret = -EFAULT; + goto exit; + } + + count -= ret; + *ppos += count; + ret = count; + +exit: + vfree(buf); + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath12k_athdiag_write(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u8 *buf; + int ret; + + if (*ppos <= 0) + return -EINVAL; + + if (!count) + return 0; + + mutex_lock(&ar->conf_mutex); + + buf = vmalloc(count); + if (!buf) { + ret = -ENOMEM; + goto error_unlock; + } + + ret = copy_from_user(buf, user_buf, count); + if (ret) { + ret = -EFAULT; + goto exit; + } + + ret = ath12k_qmi_mem_write(ar->ab, *ppos, buf, count); + if (ret < 0) { + ath12k_warn(ar->ab, "failed to write address 0x%08x via diagnose window from debugfs: %d\n", + (u32)(*ppos), ret); + goto exit; + } + + *ppos += count; + ret = count; + +exit: + vfree(buf); + +error_unlock: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_athdiag = { + .read = ath12k_athdiag_read, + .write = ath12k_athdiag_write, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_write_btcoex(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = NULL; + struct ath12k *ar = file->private_data; + char buf[256] = {0}; + size_t buf_size; + int ret = 0,coex = BTCOEX_CONFIGURE_DEFAULT, wlan_weight = 0, + wlan_prio_mask_value = 0; + enum qca_wlan_priority_type wlan_prio_mask = QCA_WLAN_PRIORITY_BE; + + if (!ar) { + ret = -EINVAL; + goto exit; + } + + buf_size = min(count, (sizeof(buf) - 1)); + + if (copy_from_user(buf, ubuf, buf_size)) { + ret = -EFAULT; + goto exit; + } + + buf[buf_size] = '\0'; + ret = sscanf(buf, "%d %d %d" , &coex, &wlan_prio_mask_value, &wlan_weight); + + if (!ret) { + ret = -EINVAL; + goto exit; + } + + if (coex != BTCOEX_ENABLE && coex != BTCOEX_CONFIGURE_DEFAULT && coex) { + ret = -EINVAL; + goto exit; + } + + mutex_lock(&ar->conf_mutex); + + switch (coex) { + case BTCOEX_ENABLE: + if (!test_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags)) + set_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags); + break; + case BTCOEX_CONFIGURE_DEFAULT: + if (!test_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags)) { + ret = -EINVAL; + goto error_unlock; + } + break; + case BTCOEX_DISABLE: + clear_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags); + break; + default: + ret = -EINVAL; + goto error_unlock; + } + + if ((wlan_weight < BTCOEX_CONFIGURE_DEFAULT) || + (wlan_prio_mask_value < BTCOEX_CONFIGURE_DEFAULT) || + (wlan_weight > BTCOEX_MAX_PKT_WEIGHT) || + (wlan_prio_mask_value > QCA_WLAN_PRIORITY_MGMT)) { + ret = -EINVAL; + goto error_unlock; + } + + if (wlan_weight == BTCOEX_CONFIGURE_DEFAULT) + wlan_weight = ar->coex.wlan_weight; + + wlan_prio_mask = ((wlan_prio_mask_value == BTCOEX_CONFIGURE_DEFAULT)? + ar->coex.wlan_prio_mask : wlan_prio_mask_value); + + if (ar->state != ATH12K_STATE_ON && + ar->state != ATH12K_STATE_RESTARTED) { + ath12k_warn(ar->ab, "pdev %d not in ON state\n", ar->pdev->pdev_id); + ret = -ENETDOWN; + goto error_unlock; + } + + arvif = list_first_entry(&ar->arvifs, typeof(*arvif), list); + + if (!arvif->is_started) { + ret = -EINVAL; + goto error_unlock; + } + + ret = ath12k_mac_btcoex_config(ar, arvif, coex, wlan_prio_mask, wlan_weight); + + if (ret) { + ath12k_warn(ar->ab, + "failed to enable coex vdev_id %d ret %d\n", + arvif->vdev_id, ret); + goto error_unlock; + } + + ar->coex.wlan_prio_mask = wlan_prio_mask; + ar->coex.wlan_weight = wlan_weight; + ret = count; + +error_unlock: + mutex_unlock(&ar->conf_mutex); + +exit: + return ret; +} + +static ssize_t ath12k_read_btcoex(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[256] = {0}; + int len = 0; + + if (!ar) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%u %u %u\n", + test_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags), + ar->coex.wlan_prio_mask, + ar->coex.wlan_weight); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_btcoex = { + .read = ath12k_read_btcoex, + .write = ath12k_write_btcoex, + .open = simple_open +}; + +static ssize_t ath12k_write_btcoex_duty_cycle(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = NULL; + struct ath12k *ar = file->private_data; + struct coex_config_arg coex_config; + char buf[256] = {0}; + size_t buf_size; + u32 duty_cycle = 0, wlan_duration = 0; + int ret = 0; + + if (!ar) { + ret = -EINVAL; + goto exit; + } + + buf_size = min(count, (sizeof(buf) - 1)); + + if (copy_from_user(buf, ubuf, buf_size)) { + ret = -EFAULT; + goto exit; + } + + buf[buf_size] = '\0'; + ret = sscanf(buf, "%u %u", &duty_cycle, &wlan_duration); + + if (!ret) { + ret = -EINVAL; + goto exit; + } + + /*Maximum duty_cycle period allowed is 100 Miliseconds*/ + if (duty_cycle < wlan_duration || !duty_cycle || !wlan_duration || duty_cycle > 100000) { + ret = -EINVAL; + goto exit; + } + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON && + ar->state != ATH12K_STATE_RESTARTED) { + ath12k_warn(ar->ab, "pdev %d not in ON state\n", ar->pdev->pdev_id); + ret = -ENETDOWN; + goto error_unlock; + } + + if (!test_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags)) { + ret = -EINVAL; + goto error_unlock; + } + + if (ar->coex.coex_algo_type != COEX_ALGO_OCS) { + ath12k_err(ar->ab,"duty cycle algo is not enabled"); + ret = -EINVAL; + goto error_unlock; + } + + arvif = list_first_entry(&ar->arvifs, typeof(*arvif), list); + + if (!arvif->is_started) { + ret = -EINVAL; + goto error_unlock; + } + + coex_config.vdev_id = arvif->vdev_id; + coex_config.config_type = WMI_COEX_CONFIG_AP_TDM; + coex_config.duty_cycle = duty_cycle; + coex_config.wlan_duration = wlan_duration; + mutex_unlock(&ar->conf_mutex); + + ret = ath12k_send_coex_config_cmd(ar, &coex_config); + + if (ret) { + ath12k_warn(ar->ab, + "failed to set duty cycle vdev_id %d ret %d\n", + coex_config.vdev_id, ret); + goto exit; + } + + mutex_lock(&ar->conf_mutex); + ar->coex.duty_cycle = duty_cycle; + ar->coex.wlan_duration = wlan_duration; + ret = count; + +error_unlock: + mutex_unlock(&ar->conf_mutex); + +exit: + return ret; +} + +static ssize_t ath12k_read_btcoex_duty_cycle(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[256] = {0}; + int len = 0; + + if (!ar) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%d %d\n", + ar->coex.duty_cycle,ar->coex.wlan_duration); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_btcoex_duty_cycle = { + .read = ath12k_read_btcoex_duty_cycle, + .write = ath12k_write_btcoex_duty_cycle, + .open = simple_open +}; + +static ssize_t ath12k_write_btcoex_algo(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = NULL; + struct ath12k *ar = file->private_data; + struct coex_config_arg coex_config; + char buf[256] = {0}; + size_t buf_size; + u32 pta_num = 0, coex_mode = 0, bt_txrx_time = 0, + bt_priority_time = 0, pta_algorithm = 0, + pta_priority = 0; + int ret = 0; + + if (!ar) { + ret = -EINVAL; + goto exit; + } + + buf_size = min(count, (sizeof(buf) - 1)); + + if (copy_from_user(buf, ubuf, buf_size)) { + ret = -EFAULT; + goto exit; + } + + buf[buf_size] = '\0'; + ret = sscanf(buf, "%u 0x%x 0x%x 0x%x 0x%x 0x%x" , &pta_num, &coex_mode, + &bt_txrx_time, &bt_priority_time, + &pta_algorithm, &pta_priority); + + if (!ret) { + ret = -EINVAL; + goto exit; + } + + if (coex_mode > BTCOEX_PTA_MODE || + coex_mode < BTCOEX_THREE_WIRE_MODE || + pta_algorithm >= COEX_ALGO_MAX_SUPPORTED) { + ret = -EINVAL; + goto exit; + } + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON && + ar->state != ATH12K_STATE_RESTARTED) { + ath12k_warn(ar->ab, "pdev %d not in ON state\n", ar->pdev->pdev_id); + ret = -ENETDOWN; + goto error_unlock; + } + + if (!test_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags)) { + ret = -EINVAL; + goto error_unlock; + } + + arvif = list_first_entry(&ar->arvifs, typeof(*arvif), list); + + if (!arvif->is_started) { + ret = -EINVAL; + goto error_unlock; + } + + coex_config.vdev_id = arvif->vdev_id; + coex_config.config_type = WMI_COEX_CONFIG_PTA_INTERFACE; + coex_config.pta_num = pta_num; + coex_config.coex_mode = coex_mode; + coex_config.bt_txrx_time = bt_txrx_time; + coex_config.bt_priority_time = bt_priority_time; + coex_config.pta_algorithm = pta_algorithm; + coex_config.pta_priority = pta_priority; + mutex_unlock(&ar->conf_mutex); + + ret = ath12k_send_coex_config_cmd(ar, &coex_config); + + if (ret) { + ath12k_warn(ar->ab, + "failed to set coex algorithm vdev_id %d ret %d\n", + coex_config.vdev_id, ret); + goto exit; + } + + mutex_lock(&ar->conf_mutex); + ar->coex.pta_num = pta_num; + ar->coex.coex_mode = coex_mode; + ar->coex.bt_active_time_slot = bt_txrx_time; + ar->coex.bt_priority_time_slot = bt_priority_time; + ar->coex.pta_algorithm = pta_algorithm; + ar->coex.pta_priority = pta_priority; + ret = count; + +error_unlock: + mutex_unlock(&ar->conf_mutex); + +exit: + return ret; +} + +static ssize_t ath12k_read_btcoex_algo(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[256] = {0}; + int len = 0; + + if (!ar) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%u %u %u %u %u %u\n", + ar->coex.pta_num, ar->coex.coex_mode, + ar->coex.bt_active_time_slot, + ar->coex.bt_priority_time_slot, + ar->coex.pta_algorithm, ar->coex.pta_priority); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_btcoex_algo = { + .read = ath12k_read_btcoex_algo, + .write = ath12k_write_btcoex_algo, + .open = simple_open +}; + +static ssize_t ath12k_btcoex_pkt_priority_write(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + struct ath12k_link_vif *arvif = NULL; + struct coex_config_arg coex_config; + char buf[128] = {0}; + size_t buf_size; + enum qca_wlan_priority_type wlan_pkt_type = 0; + u32 wlan_pkt_type_continued = 0, wlan_pkt_weight = 0, + bt_pkt_weight = 0; + int ret; + + if (!ar) { + ret = -EINVAL; + goto exit; + } + + buf_size = min(count, (sizeof(buf) - 1)); + + if (copy_from_user(buf, ubuf, buf_size)) { + ret = -EFAULT; + goto exit; + } + + buf[buf_size] = '\0'; + ret = sscanf(buf, "%u %u %u %u" , &wlan_pkt_type, + &wlan_pkt_type_continued, &wlan_pkt_weight, + &bt_pkt_weight); + + if (!ret) { + ret = -EINVAL; + goto exit; + } + + if (wlan_pkt_type > QCA_WLAN_PRIORITY_MGMT || + wlan_pkt_weight > BTCOEX_MAX_PKT_WEIGHT || + bt_pkt_weight > BTCOEX_MAX_PKT_WEIGHT) { + ret = -EINVAL; + goto exit; + } + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON && + ar->state != ATH12K_STATE_RESTARTED) { + ath12k_warn(ar->ab, "pdev %d not in ON state\n", ar->pdev->pdev_id); + ret = -ENETDOWN; + goto error_unlock; + } + + if (!test_bit(ATH12K_FLAG_BTCOEX, &ar->dev_flags)) { + ret = -EINVAL; + goto error_unlock; + } + + arvif = list_first_entry(&ar->arvifs, typeof(*arvif), list); + + if (!arvif->is_started) { + ret = -EINVAL; + goto error_unlock; + } + + coex_config.vdev_id = arvif->vdev_id; + coex_config.config_type = WMI_COEX_CONFIG_WLAN_PKT_PRIORITY; + coex_config.wlan_pkt_type = wlan_pkt_type; + coex_config.wlan_pkt_type_continued = wlan_pkt_type_continued; + coex_config.wlan_pkt_weight = wlan_pkt_weight; + coex_config.bt_pkt_weight = bt_pkt_weight; + mutex_unlock(&ar->conf_mutex); + + ret = ath12k_send_coex_config_cmd(ar, &coex_config); + + if (ret) { + ath12k_warn(ar->ab, + "failed to set coex pkt priority vdev_id %d ret %d\n", + coex_config.vdev_id, ret); + goto exit; + } + + mutex_lock(&ar->conf_mutex); + ar->coex.wlan_pkt_type = wlan_pkt_type; + ar->coex.wlan_pkt_type_continued = wlan_pkt_type_continued; + ar->coex.wlan_weight = wlan_pkt_weight; + ar->coex.bt_weight = bt_pkt_weight; + + ret = count; + +error_unlock: + mutex_unlock(&ar->conf_mutex); + +exit: + return ret; +} + +static ssize_t ath12k_btcoex_pkt_priority_read(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u8 buf[128] = {0}; + size_t len = 0; + + if (!ar) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, + "%u %u %u %u\n",ar->coex.wlan_pkt_type, + ar->coex.wlan_pkt_type_continued, ar->coex.wlan_weight, + ar->coex.bt_weight); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_btcoex_priority = { + .read = ath12k_btcoex_pkt_priority_read, + .write = ath12k_btcoex_pkt_priority_write, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +#ifdef CONFIG_ATH12K_SAWF +static ssize_t ath12k_write_sawf_stats(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u32 sawf_stats; + int ret; + + if (kstrtouint_from_user(ubuf, count, 0, &sawf_stats)) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ath12k_err(ar->ab, "Netdev is down\n"); + ret = -ENETDOWN; + goto out; + } + + if (!ath12k_sawf_enable) + { + ath12k_err(ar->ab, "SAWF support is not enabled\n"); + ret = -EOPNOTSUPP; + goto out; + } + + if (sawf_stats > ATH12K_SAWF_STATS_MAX) { + ret = -EINVAL; + goto out; + } + + ret = count; + + if (sawf_stats == ar->debug.sawf_stats) + goto out; + + ar->debug.sawf_stats = sawf_stats; + +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath12k_read_sawf_stats(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int len = 0; + char buf[32] = {0}; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "%08x\n", + ar->debug.sawf_stats); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_sawf_stats = { + .read = ath12k_read_sawf_stats, + .write = ath12k_write_sawf_stats, + .open = simple_open +}; +#endif /* CONFIG_ATH12K_SAWF */ + +static ssize_t ath12k_read_ani_enable(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int len = 0; + char buf[32]; + + len = scnprintf(buf, sizeof(buf) - len, "%d\n", ar->ani_enabled); + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_write_ani_enable(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int ret; + bool enable; + + if (kstrtobool_from_user(user_buf, count, &enable)) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto exit; + } + + if (ar->ani_enabled == enable) { + ret = count; + goto exit; + } + + ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_ANI_ENABLE, + enable, ar->pdev->pdev_id); + if (ret) { + ath12k_warn(ar->ab, "failed to %s ANI: %d\n", enable ? "enable" : "disable", + ret); + goto exit; + } + + ar->ani_enabled = enable; + ret = count; +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_ani_enable = { + .read = ath12k_read_ani_enable, + .write = ath12k_write_ani_enable, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_read_ani_poll_period(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int len = 0; + char buf[32]; + + if (!ar->ani_enabled) + len = scnprintf(buf, sizeof(buf), "ANI is disabled\n"); + else + len = scnprintf(buf, sizeof(buf) - len, "%u\n", ar->ani_poll_period); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_write_ani_poll_period(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int ret; + u32 ani_poll_period; + + if (kstrtou32_from_user(user_buf, count, 0, &ani_poll_period)) + return -EINVAL; + + if (ani_poll_period > ATH12K_ANI_POLL_PERIOD_MAX) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto exit; + } + + if (!ar->ani_enabled) { + ath12k_warn(ar->ab, "ANI is disabled\n"); + ret = -EINVAL; + goto exit; + } + + ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_ANI_POLL_PERIOD, + ani_poll_period, + ar->pdev->pdev_id); + if (ret) { + ath12k_warn(ar->ab, "failed to send ANI poll period wmi cmd: %d\n", ret); + goto exit; + } + + ar->ani_poll_period = ani_poll_period; + ret = count; +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_ani_poll_period = { + .read = ath12k_read_ani_poll_period, + .write = ath12k_write_ani_poll_period, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_read_ani_listen_period(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + int len = 0; + char buf[32]; + + if (!ar->ani_enabled) + len = scnprintf(buf, sizeof(buf), "ANI is disabled\n"); + else + len = scnprintf(buf, sizeof(buf) - len, "%u\n", ar->ani_listen_period); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_write_ani_listen_period(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u32 ani_listen_period = 0; + int ret; + + if (kstrtou32_from_user(user_buf, count, 0, &ani_listen_period)) + return -EINVAL; + + if (ani_listen_period > ATH12K_ANI_LISTEN_PERIOD_MAX) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto exit; + } + + if (!ar->ani_enabled) { + ath12k_warn(ar->ab, "ANI is disabled\n"); + ret = -EINVAL; + goto exit; + } + + ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, + ani_listen_period, ar->pdev->pdev_id); + if (ret) { + ath12k_warn(ar->ab, "failed to send ANI listen period wmi cmd: %d\n", ret); + goto exit; + } + + ar->ani_listen_period = ani_listen_period; + ret = count; +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_ani_listen_period = { + .read = ath12k_read_ani_listen_period, + .write = ath12k_write_ani_listen_period, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static int ath12k_debug_get_ani_level(struct ath12k *ar) +{ + unsigned long time_left; + int ret; + + lockdep_assert_held(&ar->conf_mutex); + + reinit_completion(&ar->ani_ofdm_event); + + ret = ath12k_wmi_pdev_get_ani_level(ar, WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, + ar->pdev->pdev_id); + if (ret) { + ath12k_warn(ar->ab, "failed to request ofdm ani level: %d\n", ret); + return ret; + } + + time_left = wait_for_completion_timeout(&ar->ani_ofdm_event, 1 * HZ); + if (time_left == 0) + return -ETIMEDOUT; + + return 0; +} + +static ssize_t ath12k_read_ani_level(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[128]; + int ret, len = 0; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto unlock; + } + + if (!ar->ani_enabled) { + len += scnprintf(buf, sizeof(buf), "ANI is disabled\n"); + } else { + ret = ath12k_debug_get_ani_level(ar); + if (ret) { + ath12k_warn(ar->ab, "failed to request ani ofdm level: %d\n", ret); + goto unlock; + } + len += scnprintf(buf, sizeof(buf), "ofdm level %d\n", + ar->ani_ofdm_level); + } + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +unlock: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath12k_write_ani_level(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + s32 ofdm_level; + int ret; + + if (kstrtos32_from_user(user_buf, count, 0, &ofdm_level)) + return -EINVAL; + + if ((ofdm_level < ATH12K_ANI_LEVEL_MIN || ofdm_level > ATH12K_ANI_LEVEL_MAX) && + ofdm_level != ATH12K_ANI_LEVEL_AUTO) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON && ar->state != ATH12K_STATE_RESTARTED) { + ret = -ENETDOWN; + goto exit; + } + + if (!ar->ani_enabled) { + ath12k_warn(ar->ab, "ANI is disabled\n"); + ret = -EINVAL; + goto exit; + } + + ret = ath12k_wmi_pdev_set_param(ar, WMI_PDEV_PARAM_ANI_OFDM_LEVEL, + ofdm_level, ar->pdev->pdev_id); + if (ret) { + ath12k_warn(ar->ab, "failed to set ANI ofdm level :%d\n", ret); + goto exit; + } + + ret = count; +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_ani_level = { + .write = ath12k_write_ani_level, + .read = ath12k_read_ani_level, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +int ath12k_debugfs_register(struct ath12k *ar) +{ + struct ath12k_base *ab = ar->ab; + struct ieee80211_hw *hw = ar->ah->hw; + char pdev_name[5]; + char buf[100] = {0}; + + snprintf(pdev_name, sizeof(pdev_name), "%s%d", "mac", ar->pdev_idx); + + ar->debug.debugfs_pdev = debugfs_create_dir(pdev_name, ab->debugfs_soc); + if (IS_ERR(ar->debug.debugfs_pdev)) + return PTR_ERR(ar->debug.debugfs_pdev); + + /* Create a symlink under ieee80211/phy* */ + snprintf(buf, 100, "../../ath12k/%pd2", ar->debug.debugfs_pdev); + + if (1) { + debugfs_create_symlink("ath12k", hw->wiphy->debugfsdir, buf); + } else { + char dirname[32] = {0}; + + snprintf(dirname, 32, "ath12k_hw%d", ar->link_idx); + debugfs_create_symlink(dirname, hw->wiphy->debugfsdir, buf); + } + + ath12k_debugfs_htt_stats_init(ar); + + ath12k_debugfs_wmi_ctrl_stats(ar); + ath12k_debugfs_fw_stats_init(ar); + ath12k_init_pktlog(ar); + + init_completion(&ar->tpc_complete); + init_completion(&ar->ani_ofdm_event); + + memset(&ar->wmm_stats, 0, sizeof(struct ath12k_wmm_stats)); + + debugfs_create_file("wmm_stats", 0644, + ar->debug.debugfs_pdev, ar, + &fops_wmm_stats); + debugfs_create_file("neighbor_peer", 0644, + ar->debug.debugfs_pdev, ar, + &fops_write_nrp_mac); + debugfs_create_file("ext_tx_stats", 0644, + ar->debug.debugfs_pdev, ar, + &fops_extd_tx_stats); + debugfs_create_file("ext_rx_stats", 0644, + ar->debug.debugfs_pdev, ar, + &fops_extd_rx_stats); + debugfs_create_file("pktlog_filter", 0644, + ar->debug.debugfs_pdev, ar, + &fops_pktlog_filter); + + if (ar->mac.sbands[NL80211_BAND_5GHZ].channels) { + debugfs_create_file("dfs_simulate_radar", 0200, + ar->debug.debugfs_pdev, ar, + &fops_simulate_radar); + debugfs_create_bool("dfs_block_radar_events", 0200, + ar->debug.debugfs_pdev, + &ar->dfs_block_radar_events); + } + + if (ar->mac.sbands[NL80211_BAND_6GHZ].channels) { + debugfs_create_file("simulate_awgn", 0200, + ar->debug.debugfs_pdev, ar, + &fops_simulate_awgn); + } + + + debugfs_create_file("tpc_stats", 0400, + ar->debug.debugfs_pdev, ar, + &fops_tpc_stats); + + debugfs_create_file("tpc_stats_type", 0600, + ar->debug.debugfs_pdev, ar, + &fops_tpc_stats_type); + + debugfs_create_file("dump_mgmt_stats", 0644, + ar->debug.debugfs_pdev, ar, + &fops_dump_mgmt_stats); + + debugfs_create_file("athdiag", S_IRUSR | S_IWUSR, + ar->debug.debugfs_pdev, ar, + &fops_athdiag); + + debugfs_create_file("btcoex", 0644, + ar->debug.debugfs_pdev, ar, + &fops_btcoex); + + debugfs_create_file("btcoex_duty_cycle", 0644, + ar->debug.debugfs_pdev, ar, + &fops_btcoex_duty_cycle); + + debugfs_create_file("btcoex_algorithm", 0644, + ar->debug.debugfs_pdev, ar, + &fops_btcoex_algo); + + debugfs_create_file("btcoex_priority", 0600, + ar->debug.debugfs_pdev, ar, + &fops_btcoex_priority); +#ifdef CONFIG_ATH12K_SAWF + debugfs_create_file("sawf_stats", 0644, + ar->debug.debugfs_pdev, ar, + &fops_sawf_stats); +#endif + debugfs_create_file("ani_enable", 0600, ar->debug.debugfs_pdev, + ar, &fops_ani_enable); + debugfs_create_file("ani_level", 0600, ar->debug.debugfs_pdev, + ar, &fops_ani_level); + debugfs_create_file("ani_poll_period", 0600, + ar->debug.debugfs_pdev, ar, + &fops_ani_poll_period); + debugfs_create_file("ani_listen_period", 0600, + ar->debug.debugfs_pdev, ar, + &fops_ani_listen_period); + return 0; +} + +void ath12k_debugfs_unregister(struct ath12k *ar) +{ + ath12k_deinit_pktlog(ar); + + /* Remove wmi ctrl stats file */ + debugfs_remove(ar->wmi_ctrl_stat); + ar->wmi_ctrl_stat = NULL; +} + +int ath12k_debugfs_create(void) +{ + debugfs_ath12k = debugfs_create_dir("ath12k", NULL); + if (IS_ERR_OR_NULL(debugfs_ath12k)) { + if (IS_ERR(debugfs_ath12k)) + return PTR_ERR(debugfs_ath12k); + else + return -ENOMEM; + } + + return 0; +} + +void ath12k_debugfs_destroy(void) +{ + debugfs_remove_recursive(debugfs_ath12k); + debugfs_ath12k = NULL; +} + +static ssize_t ath12k_write_twt_add_dialog(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = file->private_data; + struct wmi_twt_add_dialog_params params = { 0 }; + u8 buf[128] = {0}; + int ret; + + if (arvif->ar->twt_enabled == 0) { + ath12k_err(arvif->ar->ab, "twt support is not enabled\n"); + return -EOPNOTSUPP; + } + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (ret < 0) + return ret; + + buf[ret] = '\0'; + ret = sscanf(buf, + "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx %u %u %u %u %u %hhu %hhu %hhu %hhu %hhu", + ¶ms.peer_macaddr[0], + ¶ms.peer_macaddr[1], + ¶ms.peer_macaddr[2], + ¶ms.peer_macaddr[3], + ¶ms.peer_macaddr[4], + ¶ms.peer_macaddr[5], + ¶ms.dialog_id, + ¶ms.wake_intvl_us, + ¶ms.wake_intvl_mantis, + ¶ms.wake_dura_us, + ¶ms.sp_offset_us, + ¶ms.twt_cmd, + ¶ms.flag_bcast, + ¶ms.flag_trigger, + ¶ms.flag_flow_type, + ¶ms.flag_protection); + if (ret != 16) + return -EINVAL; + + params.vdev_id = arvif->vdev_id; + + ret = ath12k_wmi_send_twt_add_dialog_cmd(arvif->ar, ¶ms); + if (ret) + return ret; + + return count; +} + +static ssize_t ath12k_write_twt_del_dialog(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = file->private_data; + struct wmi_twt_del_dialog_params params = { 0 }; + u8 buf[64] = {0}; + int ret; + + if (arvif->ar->twt_enabled == 0) { + ath12k_err(arvif->ar->ab, "twt support is not enabled\n"); + return -EOPNOTSUPP; + } + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (ret < 0) + return ret; + + buf[ret] = '\0'; + ret = sscanf(buf, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx %u", + ¶ms.peer_macaddr[0], + ¶ms.peer_macaddr[1], + ¶ms.peer_macaddr[2], + ¶ms.peer_macaddr[3], + ¶ms.peer_macaddr[4], + ¶ms.peer_macaddr[5], + ¶ms.dialog_id); + if (ret != 7) + return -EINVAL; + + params.vdev_id = arvif->vdev_id; + + ret = ath12k_wmi_send_twt_del_dialog_cmd(arvif->ar, ¶ms); + if (ret) + return ret; + + return count; +} + +static ssize_t ath12k_write_twt_pause_dialog(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = file->private_data; + struct wmi_twt_pause_dialog_params params = { 0 }; + u8 buf[64] = {0}; + int ret; + + if (arvif->ar->twt_enabled == 0) { + ath12k_err(arvif->ar->ab, "twt support is not enabled\n"); + return -EOPNOTSUPP; + } + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (ret < 0) + return ret; + + buf[ret] = '\0'; + ret = sscanf(buf, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx %u", + ¶ms.peer_macaddr[0], + ¶ms.peer_macaddr[1], + ¶ms.peer_macaddr[2], + ¶ms.peer_macaddr[3], + ¶ms.peer_macaddr[4], + ¶ms.peer_macaddr[5], + ¶ms.dialog_id); + if (ret != 7) + return -EINVAL; + + params.vdev_id = arvif->vdev_id; + + ret = ath12k_wmi_send_twt_pause_dialog_cmd(arvif->ar, ¶ms); + if (ret) + return ret; + + return count; +} + +static ssize_t ath12k_write_twt_resume_dialog(struct file *file, + const char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = file->private_data; + struct wmi_twt_resume_dialog_params params = { 0 }; + u8 buf[64] = {0}; + int ret; + + if (arvif->ar->twt_enabled == 0) { + ath12k_err(arvif->ar->ab, "twt support is not enabled\n"); + return -EOPNOTSUPP; + } + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, ubuf, count); + if (ret < 0) + return ret; + + buf[ret] = '\0'; + ret = sscanf(buf, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx %u %u %u", + ¶ms.peer_macaddr[0], + ¶ms.peer_macaddr[1], + ¶ms.peer_macaddr[2], + ¶ms.peer_macaddr[3], + ¶ms.peer_macaddr[4], + ¶ms.peer_macaddr[5], + ¶ms.dialog_id, + ¶ms.sp_offset_us, + ¶ms.next_twt_size); + if (ret != 9) + return -EINVAL; + + params.vdev_id = arvif->vdev_id; + + ret = ath12k_wmi_send_twt_resume_dialog_cmd(arvif->ar, ¶ms); + if (ret) + return ret; + + return count; +} + +static ssize_t ath12k_read_rts_threshold(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_link_vif *arvif = file->private_data; + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + u8 link_id = arvif->link_id; + struct ieee80211_bss_conf *link_conf; + int ret, len = 0; + const int size = 20; + char *buf; + + rcu_read_lock(); + link_conf = rcu_dereference(vif->link_conf[link_id]); + + if (!link_conf) { + rcu_read_unlock(); + return -EINVAL; + } + + buf = kzalloc(size, GFP_ATOMIC); + + if (!buf) { + rcu_read_unlock(); + return -ENOMEM; + } + + len = scnprintf(buf + len, size - len, + "%d\n", -1); + rcu_read_unlock(); + ret = simple_read_from_buffer((char *)ubuf, count, ppos, buf, len); + kfree(buf); + return ret; +} + +static const struct file_operations ath12k_fops_rts_threshold = { + .read = ath12k_read_rts_threshold, + .open = simple_open +}; + +static const struct file_operations ath12k_fops_twt_add_dialog = { + .write = ath12k_write_twt_add_dialog, + .open = simple_open +}; + +static const struct file_operations ath12k_fops_twt_del_dialog = { + .write = ath12k_write_twt_del_dialog, + .open = simple_open +}; + +static const struct file_operations ath12k_fops_twt_pause_dialog = { + .write = ath12k_write_twt_pause_dialog, + .open = simple_open +}; + +static const struct file_operations ath12k_fops_twt_resume_dialog = { + .write = ath12k_write_twt_resume_dialog, + .open = simple_open +}; + +static int ath12k_open_link_stats(struct inode *inode, struct file *file) +{ + struct ath12k_vif *ahvif = inode->i_private; + struct ath12k_hw *ah = ahvif->ah; + struct host_link_stats *linkstat = NULL; + size_t len = 0, buf_len = PAGE_SIZE * 2; + char *buf; + int link_id; + + if (!ahvif) + return -EINVAL; + + buf = kzalloc(buf_len, GFP_KERNEL); + if (!buf) + return -ENOMEM; + + file->private_data = buf; + + mutex_lock(&ah->conf_mutex); + for_each_set_bit(link_id, &ahvif->links_map, + IEEE80211_MLD_MAX_NUM_LINKS) { + if (ahvif->link[link_id]) + linkstat = &ahvif->link[link_id]->link_stats; + else + break; + + len += scnprintf(buf + len, buf_len - len, + "link[%d] tx_enqueued = %d\n", + link_id, linkstat->tx_enqueued); + len += scnprintf(buf + len, buf_len - len, + "link[%d] tx_completed = %d\n", + link_id, linkstat->tx_completed); + len += scnprintf(buf + len, buf_len - len, + "link[%d] tx_bcast_mcast = %d\n", + link_id, linkstat->tx_bcast_mcast); + len += scnprintf(buf + len, buf_len - len, + "link[%d] tx_dropped = %d\n", + link_id, linkstat->tx_dropped); + len += scnprintf(buf + len, buf_len - len, + "link[%d] tx_encap_type = 0:%d 1:%d 2:%d 3:%d\n", + link_id, linkstat->tx_encap_type[0], + linkstat->tx_encap_type[1], + linkstat->tx_encap_type[2], + linkstat->tx_encap_type[3]); + len += scnprintf(buf + len, buf_len - len, + "link[%d] tx_encrypt_type = 0:%d 1:%d 2:%d " \ + "3:%d 4:%d 5:%d 6:%d 7:%d 8:%d 9:%d 10:%d 11:%d\n", + link_id, linkstat->tx_encrypt_type[0], + linkstat->tx_encrypt_type[1], + linkstat->tx_encrypt_type[2], + linkstat->tx_encrypt_type[3], + linkstat->tx_encrypt_type[4], + linkstat->tx_encrypt_type[5], + linkstat->tx_encrypt_type[6], + linkstat->tx_encrypt_type[7], + linkstat->tx_encrypt_type[8], + linkstat->tx_encrypt_type[9], + linkstat->tx_encrypt_type[10], + linkstat->tx_encrypt_type[11]); + len += scnprintf(buf + len, buf_len - len, + "link[%d] tx_desc_type = 0:%d 1:%d\n", + link_id, linkstat->tx_desc_type[0], + linkstat->tx_desc_type[1]); + + len += scnprintf(buf + len, buf_len - len, + "------------------------------------------------------\n"); + } + mutex_unlock(&ah->conf_mutex); + return 0; +} + +static int ath12k_release_link_stats(struct inode *inode, struct file *file) +{ + char *buf = file->private_data; + + kfree(buf); + return 0; +} + +static ssize_t ath12k_read_link_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + const char *buf = file->private_data; + size_t len = strlen(buf); + int ret; + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); + return ret; +} + +static const struct file_operations ath12k_fops_link_stats = { + .open = ath12k_open_link_stats, + .release = ath12k_release_link_stats, + .read = ath12k_read_link_stats, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_write_primary_link(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k_vif *ahvif = file->private_data; + struct ath12k_hw *ah = ahvif->ah; + struct ath12k *ar = ah->radio; + u8 primary_link; + + if (kstrtou8_from_user(user_buf, count, 0, &primary_link)) + return -EINVAL; + + if (!(ahvif->links_map & BIT(primary_link))) { + ath12k_warn(ar->ab, "Invalid link id : %u\n", primary_link); + return -EINVAL; + } + + mutex_lock(&ah->conf_mutex); + ahvif->primary_link_id = primary_link; + mutex_unlock(&ah->conf_mutex); + + return count; +} + +static ssize_t ath12k_read_primary_link(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ath12k_vif *ahvif = file->private_data; + struct ath12k_hw *ah = ahvif->ah; + int len = 0; + char buf[32] = {0}; + + mutex_lock(&ah->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, "Primary link_id: %u\n", + ahvif->primary_link_id); + mutex_unlock(&ah->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations ath12k_fops_primary_link = { + .open = simple_open, + .write = ath12k_write_primary_link, + .read = ath12k_read_primary_link, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +void ath12k_debugfs_add_interface(struct ath12k_link_vif *arvif) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + u8 link_id = arvif->link_id; + + if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS) + return; + + if (ahvif->vif->type != NL80211_IFTYPE_AP) + return; + + if (arvif->debugfs_twt) + return; + + if (1) { + arvif->debugfs_twt = debugfs_create_dir("twt", + vif->debugfs_dir); + } else { + } + + if (!arvif->debugfs_twt || IS_ERR(arvif->debugfs_twt)) { + ath12k_warn(arvif->ar->ab, + "failed to create directory %p\n", + arvif->debugfs_twt); + arvif->debugfs_twt = NULL; + return; + } + + debugfs_create_file("add_dialog", 0200, arvif->debugfs_twt, + arvif, &ath12k_fops_twt_add_dialog); + + debugfs_create_file("del_dialog", 0200, arvif->debugfs_twt, + arvif, &ath12k_fops_twt_del_dialog); + + debugfs_create_file("pause_dialog", 0200, arvif->debugfs_twt, + arvif, &ath12k_fops_twt_pause_dialog); + + debugfs_create_file("resume_dialog", 0200, arvif->debugfs_twt, + arvif, &ath12k_fops_twt_resume_dialog); + + if (0) { + if (!arvif->debugfs_rtsthreshold || IS_ERR(arvif->debugfs_rtsthreshold)) { + ath12k_warn(arvif->ar->ab, + "failed to create file %p\n", + arvif->debugfs_rtsthreshold); + debugfs_remove_recursive(arvif->debugfs_twt); + arvif->debugfs_twt = NULL; + arvif->debugfs_rtsthreshold = NULL; + return; + } + } + + if (ahvif->debugfs_linkstats) + return; + + ahvif->debugfs_linkstats = debugfs_create_file("link_stats", + 0200, + vif->debugfs_dir, + ahvif, + &ath12k_fops_link_stats); + if (!ahvif->debugfs_linkstats || + IS_ERR(ahvif->debugfs_linkstats)) { + ath12k_warn(arvif->ar->ab, + "failed to create link_stats file"); + debugfs_remove_recursive(arvif->debugfs_twt); + arvif->debugfs_twt = NULL; + + if (0) { + debugfs_remove(arvif->debugfs_rtsthreshold); + arvif->debugfs_rtsthreshold = NULL; + } + + ahvif->debugfs_linkstats = NULL; + } + + ahvif->debugfs_primary_link = debugfs_create_file("primary_link", + 0644, + vif->debugfs_dir, + ahvif, + &ath12k_fops_primary_link); +} + +void ath12k_debugfs_remove_interface(struct ath12k_link_vif *arvif) +{ + struct ath12k_vif *ahvif = arvif->ahvif; + struct ieee80211_vif *vif = ahvif->vif; + + if (!vif) { + arvif->debugfs_twt = NULL; + arvif->debugfs_rtsthreshold = NULL; + ahvif->debugfs_linkstats = NULL; + ahvif->debugfs_primary_link = NULL; + return; + } + + debugfs_remove(ahvif->debugfs_primary_link); + ahvif->debugfs_primary_link = NULL; + + if (ahvif->debugfs_linkstats) { + debugfs_remove(ahvif->debugfs_linkstats); + ahvif->debugfs_linkstats = NULL; + } + + if (!arvif->debugfs_twt) + return; + + debugfs_remove_recursive(arvif->debugfs_twt); + arvif->debugfs_twt = NULL; + + if (!arvif->debugfs_rtsthreshold) + return; + + debugfs_remove(arvif->debugfs_rtsthreshold); + arvif->debugfs_rtsthreshold = NULL; +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debugfs.h 2024-03-18 14:40:14.843741115 +0100 @@ -0,0 +1,457 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _ATH12K_DEBUGFS_H_ +#define _ATH12K_DEBUGFS_H_ + +#include "hal_tx.h" + +#define ATH12K_TX_POWER_MAX_VAL 70 +#define ATH12K_TX_POWER_MIN_VAL 0 + +#define ATH12K_DRV_TX_STATS_SIZE 1024 + +#define ATH12K_MAX_NRPS 7 +#define MAC_UNIT_LEN 3 + +/* htt_dbg_ext_stats_type */ +enum ath12k_dbg_htt_ext_stats_type { + ATH12K_DBG_HTT_EXT_STATS_RESET = 0, + ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1, + ATH12K_DBG_HTT_EXT_STATS_PDEV_RX = 2, + ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_HWQ = 3, + ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4, + ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5, + ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6, + ATH12K_DBG_HTT_EXT_STATS_TQM_CMDQ = 7, + ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8, + ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE = 9, + ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE = 10, + ATH12K_DBG_HTT_EXT_STATS_PEER_INFO = 11, + ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12, + ATH12K_DBG_HTT_EXT_STATS_TX_MU_HWQ = 13, + ATH12K_DBG_HTT_EXT_STATS_RING_IF_INFO = 14, + ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15, + ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16, + ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17, + ATH12K_DBG_HTT_EXT_STATS_ACTIVE_PEERS_LIST = 18, + ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19, + ATH12K_DBG_HTT_EXT_STATS_TWT_SESSIONS = 20, + ATH12K_DBG_HTT_EXT_STATS_REO_RESOURCE_STATS = 21, + ATH12K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO = 22, + ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23, + ATH12K_DBG_HTT_EXT_STATS_RING_BACKPRESSURE_STATS = 24, + ATH12K_DBG_HTT_EXT_STATS_LATENCY_PROF_STATS = 25, + ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_TRIG_STATS = 26, + ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27, + ATH12K_DBG_HTT_EXT_STATS_FSE_RX = 28, + ATH12K_DBG_HTT_EXT_PEER_CTRL_PATH_TXRX_STATS = 29, + ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE_EXT = 30, + ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE_TXBF = 31, + ATH12K_DBG_HTT_EXT_STATS_TXBF_OFDMA = 32, + ATH12K_DBG_HTT_EXT_STA_11AX_UL_STATS = 33, + ATH12K_DBG_HTT_EXT_VDEV_RTT_RESP_STATS = 34, + ATH12K_DBG_HTT_EXT_PKTLOG_AND_HTT_RING_STATS = 35, + ATH12K_DBG_HTT_EXT_STATS_DLPAGER_STATS = 36, + ATH12K_DBG_HTT_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, + ATH12K_DBG_HTT_EXT_VDEVS_TXRX_STATS = 38, + ATH12K_DBG_HTT_EXT_VDEV_RTT_INITIATOR_STATS = 39, + ATH12K_DBG_HTT_EXT_PDEV_PER_STATS = 40, + ATH12K_DBG_HTT_EXT_AST_ENTRIES = 41, + ATH12K_DBG_HTT_EXT_RX_RING_STATS = 42, + ATH12K_DBG_HTT_STRM_GEN_MPDUS_STATS = 43, + ATH12K_DBG_HTT_STRM_GEN_MPDUS_DETAILS_STATS = 44, + ATH12K_DBG_HTT_DBG_SOC_ERROR_STATS = 45, + ATH12K_DBG_HTT_DBG_PDEV_PUNCTURE_STATS = 46, + ATH12K_DBG_HTT_DBG_EXT_STATS_ML_PEERS_INFO = 47, + ATH12K_DBG_HTT_DBG_ODD_MANDATORY_STATS = 48, + ATH12K_DBG_HTT_DBG_PDEV_SCHED_ALGO_STATS = 49, + ATH12K_DBG_HTT_DBG_ODD_MANDATORY_MUMIMO_STATS = 50, + ATH12K_DBG_HTT_DBG_ODD_MANDATORY_MUOFDMA_STATS = 51, + ATH12K_DBG_HTT_DBG_EXT_PHY_PROF_CAL_STATS = 52, + ATH12K_DGB_HTT_DBG_EXT_STATS_PDEV_BW_MGR = 53, + ATH12K_DGB_HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54, + ATH12K_DBG_HTT_UMAC_RESET_SSR_STATS = 55, + /* keep this last */ + ATH12K_DBG_HTT_NUM_EXT_STATS, +}; + +#define ATH12K_CCK_RATES 4 +#define ATH12K_OFDM_RATES 8 +#define ATH12K_HT_RATES 8 +/* VHT rates includes extra MCS. sent by FW */ +#define ATH12K_VHT_RATES 12 +#define ATH12K_HE_RATES 12 +#define ATH12K_HE_RATES_WITH_EXTRA_MCS 14 +#define ATH12K_EHT_RATES 16 +#define ATH12K_NSS_1 1 +#define ATH12K_NSS_4 4 +#define ATH12K_NSS_8 8 +#define TPC_STATS_WAIT_TIME (1 * HZ) +#define MAX_TPC_PREAM_STR_LEN 7 +/* Max negative power value to indicate error */ +#define TPC_INVAL -128 +#define TPC_MAX 127 +#define TPC_STATS_TOT_ROW 700 +#define TPC_STATS_TOT_COLUMN 100 +#define ATH12K_TPC_STATS_BUF_SIZE (TPC_STATS_TOT_ROW * TPC_STATS_TOT_COLUMN) + +enum ath12k_dbg_tpc_stats_type { + ATH12K_DBG_TPC_STATS_SU, + ATH12K_DBG_TPC_STATS_SU_WITH_TXBF, + ATH12K_DBG_TPC_STATS_MU, + ATH12K_DBG_TPC_STATS_MU_WITH_TXBF, + /*last*/ + ATH12K_DBG_TPC_MAX_STATS, +}; + +enum ath12k_debug_tpc_stats_ctl_mode { + ATH12K_TPC_STATS_CTL_MODE_LEGACY_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_HT_VHT20_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_HE_EHT20_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_HT_VHT40_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_HE_EHT40_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_VHT80_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_HE_EHT80_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_VHT160_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_HE_EHT160_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_HE_EHT320_5G_6G, + ATH12K_TPC_STATS_CTL_MODE_CCK_2G, + ATH12K_TPC_STATS_CTL_MODE_LEGACY_2G, + ATH12K_TPC_STATS_CTL_MODE_HT20_2G, + ATH12K_TPC_STATS_CTL_MODE_HT40_2G, + + ATH12K_TPC_STATS_CTL_MODE_EHT80_SU_PUNC20 = 23, + ATH12K_TPC_STATS_CTL_MODE_EHT160_SU_PUNC20, + ATH12K_TPC_STATS_CTL_MODE_EHT320_SU_PUNC40, + ATH12K_TPC_STATS_CTL_MODE_EHT320_SU_PUNC80, + ATH12K_TPC_STATS_CTL_MODE_EHT320_SU_PUNC120 +}; + +enum ath12k_debug_tpc_stats_support_modes { + ATH12K_TPC_STATS_SUPPORT_160 = 0, + ATH12K_TPC_STATS_SUPPORT_320, + ATH12K_TPC_STATS_SUPPORT_AX, + ATH12K_TPC_STATS_SUPPORT_AX_EXTRA_MCS, + ATH12K_TPC_STATS_SUPPORT_BE, + ATH12K_TPC_STATS_SUPPORT_BE_PUNC, +}; + +struct debug_htt_stats_req { + bool done; + bool override_cfg_param; + u8 pdev_id; + u32 type; + u32 cfg_param[4]; + u8 peer_addr[ETH_ALEN]; + struct completion cmpln; + u32 buf_len; + u8 buf[]; +}; + +struct ath12k_pktlog_hdr { + u16 flags; + u16 missed_cnt; + u16 log_type; + u16 size; + u32 timestamp; + u32 type_specific_data; + struct mlo_timestamp m_timestamp; + u8 payload[]; +} __packed; + +#define ATH12K_HTT_PEER_STATS_RESET BIT(16) + +#define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512) +#define ATH12K_FW_STATS_BUF_SIZE (1024 * 1024) + +enum ath12k_pktlog_filter { + ATH12K_PKTLOG_RX = 0x000000001, + ATH12K_PKTLOG_TX = 0x000000002, + ATH12K_PKTLOG_RCFIND = 0x000000004, + ATH12K_PKTLOG_RCUPDATE = 0x000000008, + ATH12K_PKTLOG_EVENT_SMART_ANT = 0x000000020, + ATH12K_PKTLOG_EVENT_SW = 0x000000040, + ATH12K_PKTLOG_HYBRID = 0x000020000, + ATH12K_PKTLOG_ANY = 0x00000006f, +}; + +enum ath12k_pktlog_mode { + ATH12K_PKTLOG_MODE_LITE = 1, + ATH12K_PKTLOG_MODE_FULL = 2, +}; + +enum ath12k_pktlog_enum { + ATH12K_PKTLOG_TYPE_TX_CTRL = 1, + ATH12K_PKTLOG_TYPE_TX_STAT = 2, + ATH12K_PKTLOG_TYPE_TX_MSDU_ID = 3, + ATH12K_PKTLOG_TYPE_TX_FRM_HDR = 4, + ATH12K_PKTLOG_TYPE_RX_STAT = 5, + ATH12K_PKTLOG_TYPE_RC_FIND = 6, + ATH12K_PKTLOG_TYPE_RC_UPDATE = 7, + ATH12K_PKTLOG_TYPE_TX_VIRT_ADDR = 8, + ATH12K_PKTLOG_TYPE_DBG_PRINT = 9, + ATH12K_PKTLOG_TYPE_RX_CBF = 10, + ATH12K_PKTLOG_TYPE_ANI = 11, + ATH12K_PKTLOG_TYPE_GRPID = 12, + ATH12K_PKTLOG_TYPE_TX_MU = 13, + ATH12K_PKTLOG_TYPE_SMART_ANTENNA = 14, + ATH12K_PKTLOG_TYPE_TX_PFSCHED_CMD = 15, + ATH12K_PKTLOG_TYPE_TX_FW_GENERATED1 = 19, + ATH12K_PKTLOG_TYPE_TX_FW_GENERATED2 = 20, + ATH12K_PKTLOG_TYPE_MAX = 21, + ATH12K_PKTLOG_TYPE_RX_STATBUF = 22, + ATH12K_PKTLOG_TYPE_PPDU_STATS = 23, + ATH12K_PKTLOG_TYPE_LITE_RX = 24, + ATH12K_PKTLOG_TYPE_HOST_SW_EVENT = 30, +}; + +enum ath12k_dbg_aggr_mode { + ATH12K_DBG_AGGR_MODE_AUTO, + ATH12K_DBG_AGGR_MODE_MANUAL, + ATH12K_DBG_AGGR_MODE_MAX, +}; + +enum { + NRP_ACTION_ADD, + NRP_ACTION_DEL, +}; + +struct ath12k_neighbor_peer { + struct list_head list; + struct completion filter_done; + bool is_filter_on; + int vdev_id; + u8 addr[ETH_ALEN]; + u8 rssi; + s64 timestamp; + bool rssi_valid; +}; + +/* + * enum qca_wlan_priority_type - priority mask + * This enum defines priority mask that user can configure + * over BT traffic type which can be passed through + * QCA_WLAN_VENDOR_ATTR_BTCOEX_CONFIG_WLAN_PRIORITY attribute. + * + * @QCA_WLAN_PRIORITY_BE: Bit mask for WLAN Best effort traffic + * @QCA_WLAN_PRIORITY_BK: Bit mask for WLAN Background traffic + * @QCA_WLAN_PRIORITY_VI: Bit mask for WLAN Video traffic + * @QCA_WLAN_PRIORITY_VO: Bit mask for WLAN Voice traffic + * @QCA_WLAN_PRIORITY_BEACON: Bit mask for WLAN BEACON frame + * @QCA_WLAN_PRIORITY_MGMT: Bit mask for WLAN Management frame +*/ +enum qca_wlan_priority_type { + QCA_WLAN_PRIORITY_BE = BIT(0), + QCA_WLAN_PRIORITY_BK = BIT(1), + QCA_WLAN_PRIORITY_VI = BIT(2), + QCA_WLAN_PRIORITY_VO = BIT(3), + QCA_WLAN_PRIORITY_BEACON = BIT(4), + QCA_WLAN_PRIORITY_MGMT = BIT(5), +}; + +#define BTCOEX_ENABLE 1 +#define BTCOEX_DISABLE 0 +#define BTCOEX_CONFIGURE_DEFAULT -1 +#define BTCOEX_THREE_WIRE_MODE 1 +#define BTCOEX_PTA_MODE 2 +#define BTCOEX_MAX_PKT_WEIGHT 255 + +#define ATH12K_ANI_LEVEL_MAX 30 +#define ATH12K_ANI_LEVEL_MIN -5 +#define ATH12K_ANI_LEVEL_AUTO 128 +#define ATH12K_ANI_POLL_PERIOD_MAX 3000 +#define ATH12K_ANI_LISTEN_PERIOD_MAX 3000 + +void ath12k_wmi_crl_path_stats_list_free(struct ath12k *ar, struct list_head *head); + +#ifdef CONFIG_ATH12K_DEBUGFS +int ath12k_debugfs_soc_create(struct ath12k_base *ab); +void ath12k_debugfs_soc_destroy(struct ath12k_base *ab); +int ath12k_debugfs_pdev_create(struct ath12k_base *ab); +void ath12k_debugfs_pdev_destroy(struct ath12k_base *ab); +int ath12k_debugfs_register(struct ath12k *ar); +void ath12k_debugfs_unregister(struct ath12k *ar); +int ath12k_debugfs_create(void); +void ath12k_debugfs_destroy(void); +void ath12k_debugfs_fw_stats_process(struct ath12k *ar, + struct ath12k_fw_stats *stats); + +void ath12k_debugfs_fw_stats_init(struct ath12k *ar); + +void ath12k_debugfs_nrp_clean(struct ath12k *ar, const u8 *addr); +void ath12k_debugfs_nrp_cleanup_all(struct ath12k *ar); + +static inline bool ath12k_debugfs_is_pktlog_lite_mode_enabled(struct ath12k *ar) +{ + return (ar->debug.pktlog_mode == ATH12K_PKTLOG_MODE_LITE); +} + +static inline bool ath12k_debugfs_is_pktlog_rx_stats_enabled(struct ath12k *ar) +{ + return (!ar->debug.pktlog_peer_valid && ar->debug.pktlog_mode); +} + +static inline bool ath12k_debugfs_is_pktlog_peer_valid(struct ath12k *ar, u8 *addr) +{ + return (ar->debug.pktlog_peer_valid && ar->debug.pktlog_mode && + ether_addr_equal(addr, ar->debug.pktlog_peer_addr)); +} + +static inline int ath12k_debugfs_is_extd_tx_stats_enabled(struct ath12k *ar) +{ + return ar->debug.extd_tx_stats; +} + +static inline int ath12k_debugfs_is_extd_rx_stats_enabled(struct ath12k *ar) +{ + return ar->debug.extd_rx_stats; +} + +static inline int ath12k_debugfs_rx_filter(struct ath12k *ar) +{ + return ar->debug.rx_filter; +} + +void ath12k_debugfs_add_interface(struct ath12k_link_vif *arvif); +void ath12k_debugfs_remove_interface(struct ath12k_link_vif *arvif); + +#else +static inline int ath12k_debugfs_create(void) +{ + return 0; +} + +static inline void ath12k_debugfs_destroy(void) +{ +} + +static inline int ath12k_debugfs_soc_create(struct ath12k_base *ab) +{ + return 0; +} + +static inline void ath12k_debugfs_soc_destroy(struct ath12k_base *ab) +{ +} + +static inline int ath12k_debugfs_pdev_create(struct ath12k_base *ab) +{ + return 0; +} + +static inline void ath12k_debugfs_pdev_destroy(struct ath12k_base *ab) +{ +} + +static inline int ath12k_debugfs_register(struct ath12k *ar) +{ + return 0; +} + +static inline void ath12k_debugfs_unregister(struct ath12k *ar) +{ +} + +static inline void ath12k_debugfs_fw_stats_process(struct ath12k *ar, + struct ath12k_fw_stats *stats) +{ +} + +static inline void ath12k_debugfs_fw_stats_init(struct ath12k *ar) +{ +} + +static inline int ath12k_debugfs_is_extd_tx_stats_enabled(struct ath12k *ar) +{ + return 0; +} + +static inline int ath12k_debugfs_is_extd_rx_stats_enabled(struct ath12k *ar) +{ + return 0; +} + +static inline bool ath12k_debugfs_is_pktlog_lite_mode_enabled(struct ath12k *ar) +{ + return false; +} + +static inline bool ath12k_debugfs_is_pktlog_rx_stats_enabled(struct ath12k *ar) +{ + return false; +} + +static inline bool ath12k_debugfs_is_pktlog_peer_valid(struct ath12k *ar, u8 *addr) +{ + return false; +} + +static inline int ath12k_debugfs_rx_filter(struct ath12k *ar) +{ + return 0; +} + +static inline void ath12k_debugfs_add_interface(struct ath12k_link_vif *arvif) +{ +} + +static inline void ath12k_debugfs_remove_interface(struct ath12k_link_vif *arvif) +{ +} + +static inline void ath12k_debugfs_nrp_clean(struct ath12k *ar, const u8 *addr) +{ +} + +static inline void ath12k_debugfs_nrp_cleanup_all(struct ath12k *ar) +{ +} +#endif /* CONFIG_MAC80211_DEBUGFS*/ + +#ifdef CONFIG_ATH12K_PKTLOG +void ath12k_init_pktlog(struct ath12k *ar); +void ath12k_deinit_pktlog(struct ath12k *ar); +void ath12k_htt_pktlog_process(struct ath12k *ar, u8 *data); +void ath12k_htt_ppdu_pktlog_process(struct ath12k *ar, u8 *data, u32 len); +void ath12k_rx_stats_buf_pktlog_process(struct ath12k *ar, u8 *data, + u16 log_type, u32 len); +#else +static inline void ath12k_init_pktlog(struct ath12k *ar) { } + +static inline void ath12k_deinit_pktlog(struct ath12k *ar) { } + +static inline void ath12k_htt_pktlog_process(struct ath12k *ar, + u8 *data) +{ +} + +static inline void ath12k_htt_ppdu_pktlog_process(struct ath12k *ar, + u8 *data, u32 len) +{ +} + +static inline void ath12k_rx_stats_buf_pktlog_process(struct ath12k *ar, + u8 *data, u16 log_type, u32 len) { } +#endif /* CONFIG_ATH12K_PKTLOG */ + + +#ifdef CONFIG_ATH12K_SAWF +static inline unsigned int ath12k_debugfs_is_sawf_stats_enabled(struct ath12k *ar) +{ + return ar->debug.sawf_stats; +} + +#else + +static inline unsigned int ath12k_debugfs_is_sawf_stats_enabled(struct ath12k *ar) +{ + return 0; +} + +#endif + +#endif /* _ATH12K_DEBUGFS_H_ */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debugfs_htt_stats.c 2024-03-18 14:40:14.847741224 +0100 @@ -0,0 +1,9258 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "core.h" +#include "dp_tx.h" +#include "dp_rx.h" +#include "debug.h" +#include "debugfs_htt_stats.h" + +#define HTT_MAX_STRING_LEN 256 +#define HTT_MAX_PRINT_CHAR_PER_ELEM 15 +#define HTT_HISTOGRAM_STATS_LEN 512 + + +#define PRINT_ARRAY_TO_BUF(out, buflen, arr, str, len, newline) \ + do { \ + int index = 0; u8 i; const char *str_val = str; \ + const char *new_line = newline; \ + if (str_val) { \ + index += scnprintf((out + buflen), \ + (ATH12K_HTT_STATS_BUF_SIZE - buflen), \ + "%s = ", str_val); \ + } \ + for (i = 0; i < len; i++) { \ + index += scnprintf((out + buflen) + index, \ + (ATH12K_HTT_STATS_BUF_SIZE - buflen) - index, \ + " %u:%u,", i, arr[i]); \ + } \ + index += scnprintf((out + buflen) + index, \ + (ATH12K_HTT_STATS_BUF_SIZE - buflen) - index, \ + "%s", new_line); \ + buflen += index; \ + } while (0) + +static inline void htt_print_stats_string_tlv(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_stats_string_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 i; + u16 index = 0; + char data[HTT_MAX_STRING_LEN] = {0}; + + tag_len = tag_len >> 2; + + len += scnprintf(buf + len, buf_len - len, "HTT_STATS_STRING_TLV:\n"); + + for (i = 0; i < tag_len; i++) { + index += scnprintf(&data[index], + HTT_MAX_STRING_LEN - index, + "%.*s", 4, (char *)&(htt_stats_buf->data[i])); + if (index >= HTT_MAX_STRING_LEN) + break; + } + + len += scnprintf(buf + len, buf_len - len, "data = %s\n", data); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_pdev_stats_cmn_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_cmn_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_STATS_CMN_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "comp_delivered = %u\n", + htt_stats_buf->comp_delivered); + len += scnprintf(buf + len, buf_len - len, "self_triggers = %u\n", + htt_stats_buf->self_triggers); + len += scnprintf(buf + len, buf_len - len, "hw_queued = %u\n", + htt_stats_buf->hw_queued); + len += scnprintf(buf + len, buf_len - len, "hw_reaped = %u\n", + htt_stats_buf->hw_reaped); + len += scnprintf(buf + len, buf_len - len, "underrun = %u\n", + htt_stats_buf->underrun); + len += scnprintf(buf + len, buf_len - len, "hw_paused = %u\n", + htt_stats_buf->hw_paused); + len += scnprintf(buf + len, buf_len - len, "hw_flush = %u\n", + htt_stats_buf->hw_flush); + len += scnprintf(buf + len, buf_len - len, "hw_filt = %u\n", + htt_stats_buf->hw_filt); + len += scnprintf(buf + len, buf_len - len, "tx_abort = %u\n", + htt_stats_buf->tx_abort); + len += scnprintf(buf + len, buf_len - len, "ppdu_ok = %u\n", + htt_stats_buf->ppdu_ok); + len += scnprintf(buf + len, buf_len - len, "mpdu_requeued = %u\n", + htt_stats_buf->mpdu_requed); + len += scnprintf(buf + len, buf_len - len, "tx_xretry = %u\n", + htt_stats_buf->tx_xretry); + len += scnprintf(buf + len, buf_len - len, "data_rc = %u\n", + htt_stats_buf->data_rc); + len += scnprintf(buf + len, buf_len - len, "mpdu_dropped_xretry = %u\n", + htt_stats_buf->mpdu_dropped_xretry); + len += scnprintf(buf + len, buf_len - len, "illegal_rate_phy_err = %u\n", + htt_stats_buf->illgl_rate_phy_err); + len += scnprintf(buf + len, buf_len - len, "cont_xretry = %u\n", + htt_stats_buf->cont_xretry); + len += scnprintf(buf + len, buf_len - len, "tx_timeout = %u\n", + htt_stats_buf->tx_timeout); + len += scnprintf(buf + len, buf_len - len, "tx_time_dur_data = %u\n", + htt_stats_buf->tx_time_dur_data); + len += scnprintf(buf + len, buf_len - len, "pdev_resets = %u\n", + htt_stats_buf->pdev_resets); + len += scnprintf(buf + len, buf_len - len, "phy_underrun = %u\n", + htt_stats_buf->phy_underrun); + len += scnprintf(buf + len, buf_len - len, "txop_ovf = %u\n", + htt_stats_buf->txop_ovf); + len += scnprintf(buf + len, buf_len - len, "seq_posted = %u\n", + htt_stats_buf->seq_posted); + len += scnprintf(buf + len, buf_len - len, "seq_failed_queueing = %u\n", + htt_stats_buf->seq_failed_queueing); + len += scnprintf(buf + len, buf_len - len, "seq_completed = %u\n", + htt_stats_buf->seq_completed); + len += scnprintf(buf + len, buf_len - len, "seq_restarted = %u\n", + htt_stats_buf->seq_restarted); + len += scnprintf(buf + len, buf_len - len, "seq_txop_repost_stop = %u\n", + htt_stats_buf->seq_txop_repost_stop); + len += scnprintf(buf + len, buf_len - len, "next_seq_cancel = %u\n", + htt_stats_buf->next_seq_cancel); + len += scnprintf(buf + len, buf_len - len, "dl_mu_mimo_seq_posted = %u\n", + htt_stats_buf->mu_seq_posted); + len += scnprintf(buf + len, buf_len - len, "dl_mu_ofdma_seq_posted = %u\n", + htt_stats_buf->mu_ofdma_seq_posted); + len += scnprintf(buf + len, buf_len - len, "ul_mu_mimo_seq_posted = %u\n", + htt_stats_buf->ul_mumimo_seq_posted); + len += scnprintf(buf + len, buf_len - len, "ul_mu_ofdma_seq_posted = %u\n", + htt_stats_buf->ul_ofdma_seq_posted); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_peer_blacklisted = %u\n", + htt_stats_buf->num_mu_peer_blacklisted); + len += scnprintf(buf + len, buf_len - len, "seq_qdepth_repost_stop = %u\n", + htt_stats_buf->seq_qdepth_repost_stop); + len += scnprintf(buf + len, buf_len - len, "seq_min_msdu_repost_stop = %u\n", + htt_stats_buf->seq_min_msdu_repost_stop); + len += scnprintf(buf + len, buf_len - len, "mu_seq_min_msdu_repost_stop = %u\n", + htt_stats_buf->mu_seq_min_msdu_repost_stop); + len += scnprintf(buf + len, buf_len - len, "seq_switch_hw_paused = %u\n", + htt_stats_buf->seq_switch_hw_paused); + len += scnprintf(buf + len, buf_len - len, "next_seq_posted_dsr = %u\n", + htt_stats_buf->next_seq_posted_dsr); + len += scnprintf(buf + len, buf_len - len, "seq_posted_isr = %u\n", + htt_stats_buf->seq_posted_isr); + len += scnprintf(buf + len, buf_len - len, "seq_ctrl_cached = %u\n", + htt_stats_buf->seq_ctrl_cached); + len += scnprintf(buf + len, buf_len - len, "mpdu_count_tqm = %u\n", + htt_stats_buf->mpdu_count_tqm); + len += scnprintf(buf + len, buf_len - len, "msdu_count_tqm = %u\n", + htt_stats_buf->msdu_count_tqm); + len += scnprintf(buf + len, buf_len - len, "mpdu_removed_tqm = %u\n", + htt_stats_buf->mpdu_removed_tqm); + len += scnprintf(buf + len, buf_len - len, "msdu_removed_tqm = %u\n", + htt_stats_buf->msdu_removed_tqm); + len += scnprintf(buf + len, buf_len - len, "remove_mpdus_max_retries = %u\n", + htt_stats_buf->remove_mpdus_max_retries); + len += scnprintf(buf + len, buf_len - len, "mpdus_sw_flush = %u\n", + htt_stats_buf->mpdus_sw_flush); + len += scnprintf(buf + len, buf_len - len, "mpdus_hw_filter = %u\n", + htt_stats_buf->mpdus_hw_filter); + len += scnprintf(buf + len, buf_len - len, "mpdus_truncated = %u\n", + htt_stats_buf->mpdus_truncated); + len += scnprintf(buf + len, buf_len - len, "mpdus_ack_failed = %u\n", + htt_stats_buf->mpdus_ack_failed); + len += scnprintf(buf + len, buf_len - len, "mpdus_expired = %u\n", + htt_stats_buf->mpdus_expired); + len += scnprintf(buf + len, buf_len - len, "mpdus_seq_hw_retry = %u\n", + htt_stats_buf->mpdus_seq_hw_retry); + len += scnprintf(buf + len, buf_len - len, "ack_tlv_proc = %u\n", + htt_stats_buf->ack_tlv_proc); + len += scnprintf(buf + len, buf_len - len, "coex_abort_mpdu_cnt_valid = %u\n", + htt_stats_buf->coex_abort_mpdu_cnt_valid); + len += scnprintf(buf + len, buf_len - len, "coex_abort_mpdu_cnt = %u\n", + htt_stats_buf->coex_abort_mpdu_cnt); + len += scnprintf(buf + len, buf_len - len, "num_total_ppdus_tried_ota = %u\n", + htt_stats_buf->num_total_ppdus_tried_ota); + len += scnprintf(buf + len, buf_len - len, "num_data_ppdus_tried_ota = %u\n", + htt_stats_buf->num_data_ppdus_tried_ota); + len += scnprintf(buf + len, buf_len - len, "local_ctrl_mgmt_enqued = %u\n", + htt_stats_buf->local_ctrl_mgmt_enqued); + len += scnprintf(buf + len, buf_len - len, "local_ctrl_mgmt_freed = %u\n", + htt_stats_buf->local_ctrl_mgmt_freed); + len += scnprintf(buf + len, buf_len - len, "local_data_enqued = %u\n", + htt_stats_buf->local_data_enqued); + len += scnprintf(buf + len, buf_len - len, "local_data_freed = %u\n", + htt_stats_buf->local_data_freed); + len += scnprintf(buf + len, buf_len - len, "mpdu_tried = %u\n", + htt_stats_buf->mpdu_tried); + len += scnprintf(buf + len, buf_len - len, "isr_wait_seq_posted = %u\n", + htt_stats_buf->isr_wait_seq_posted); + len += scnprintf(buf + len, buf_len - len, "tx_active_dur_us_low = %u\n", + htt_stats_buf->tx_active_dur_us_low); + len += scnprintf(buf + len, buf_len - len, "tx_active_dur_us_high = %u\n", + htt_stats_buf->tx_active_dur_us_high); + len += scnprintf(buf + len, buf_len - len, "fes_offsets_err_cnt = %u\n", + htt_stats_buf->fes_offsets_err_cnt); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_urrn_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_urrn_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_TX_PDEV_MAX_URRN_STATS); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_STATS_URRN_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->urrn_stats, "urrn_stats", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_flush_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_flush_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_TX_PDEV_MAX_FLUSH_REASON_STATS); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_STATS_FLUSH_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->flush_errs, "flush_errs", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_sifs_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_sifs_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_TX_PDEV_MAX_SIFS_BURST_STATS); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_STATS_SIFS_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->sifs_status, "sifs_status", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_phy_err_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_phy_err_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_TX_PDEV_MAX_PHY_ERR_STATS); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_STATS_PHY_ERR_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->phy_errs, "phy_errs", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_sifs_hist_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_sifs_hist_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_STATS_SIFS_HIST_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->sifs_hist_status, + "sifs_hist_status", num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_tx_ppdu_stats_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_STATS_TX_PPDU_STATS_TLV_V:\n"); + + len += scnprintf(buf + len, buf_len - len, "num_data_ppdus_legacy_su = %u\n", + htt_stats_buf->num_data_ppdus_legacy_su); + + len += scnprintf(buf + len, buf_len - len, "num_data_ppdus_ac_su = %u\n", + htt_stats_buf->num_data_ppdus_ac_su); + + len += scnprintf(buf + len, buf_len - len, "num_data_ppdus_ax_su = %u\n", + htt_stats_buf->num_data_ppdus_ax_su); + + len += scnprintf(buf + len, buf_len - len, "num_data_ppdus_ac_su_txbf = %u\n", + htt_stats_buf->num_data_ppdus_ac_su_txbf); + + len += scnprintf(buf + len, buf_len - len, "num_data_ppdus_ax_su_txbf = %u\n", + htt_stats_buf->num_data_ppdus_ax_su_txbf); + + stats_req->buf_len = len; +} + +static inline +void htt_print_tx_pdev_mu_ppdu_dist_stats_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_mu_ppdu_dist_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 max = HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST; + char hw_mode_prefix[][3] = {"ac", "ax"}; + u8 j = 0, k = 0; + + if (htt_stats_buf->hw_mode == HTT_STATS_HWMODE_AC) { + len += scnprintf(buf + len, buf_len - len, + "\nHTT_TX_PDEV_MU_PPDU_DISTRIBUTION_STATS:\n"); + } else if (htt_stats_buf->hw_mode == HTT_STATS_HWMODE_AX) { + k = 1; + } else { + /* hw_mode not recognized */ + return; + } + + for (j = 0; j < HTT_STATS_NUM_NR_BINS; j++) { + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_seq_posted_nr4 %u:%u\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_seq_posted[j]); + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_seq_posted_nr8 %u:%u\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_seq_posted[j]); + } + + for (j = 0; j < HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST; j++) { + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_ppdu_posted_per_burst_nr4 %u:%u,\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_ppdu_posted_per_burst[j]); + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_ppdu_posted_per_burst_nr8 %u:%u,\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_ppdu_posted_per_burst + [max + j]); + } + + for (j = 0; j < HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST; j++) { + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_ppdu_completed_per_burst_nr4 %u:%u,\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_ppdu_completed_per_burst[j]); + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_ppdu_completed_per_burst_nr8 %u:%u,\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_ppdu_completed_per_burst + [max + j]); + } + + for (j = 0; j < HTT_STATS_MAX_NUM_SCHED_STATUS; j++) { + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_seq_term_status_nr4 %u:%u,\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_seq_term_status[j]); + len += scnprintf(buf + len, buf_len - len, + "%s_mu_mimo_num_seq_term_status_nr8 %u:%u,\n", + hw_mode_prefix[k], j, + htt_stats_buf->mu_mimo_num_seq_term_status + [HTT_STATS_MAX_NUM_SCHED_STATUS + j]); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = ((tag_len - sizeof(htt_stats_buf->hist_bin_size)) >> 2); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_STATS_TRIED_MPDU_CNT_HIST_TLV_V:\n"); + len += scnprintf(buf + len, buf_len - len, "TRIED_MPDU_CNT_HIST_BIN_SIZE : %u\n", + htt_stats_buf->hist_bin_size); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tried_mpdu_cnt_hist, + "tried_mpdu_cnt_hist = %s\n", num_elements, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_hw_stats_intr_misc_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_hw_stats_intr_misc_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN + 1] = {0}; + + len += scnprintf(buf + len, buf_len - len, "HTT_HW_STATS_INTR_MISC_TLV:\n"); + memcpy(hw_intr_name, &(htt_stats_buf->hw_intr_name[0]), + HTT_STATS_MAX_HW_INTR_NAME_LEN); + len += scnprintf(buf + len, buf_len - len, "hw_intr_name = %s\n", hw_intr_name); + len += scnprintf(buf + len, buf_len - len, "mask = %u\n", + htt_stats_buf->mask); + len += scnprintf(buf + len, buf_len - len, "count = %u\n", + htt_stats_buf->count); + + stats_req->buf_len = len; +} + +static inline void +htt_print_hw_stats_wd_timeout_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_hw_stats_wd_timeout_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN + 1] = {0}; + + len += scnprintf(buf + len, buf_len - len, "HTT_HW_STATS_WD_TIMEOUT_TLV:\n"); + memcpy(hw_module_name, &(htt_stats_buf->hw_module_name[0]), + HTT_STATS_MAX_HW_MODULE_NAME_LEN); + len += scnprintf(buf + len, buf_len - len, "hw_module_name = %s\n", + hw_module_name); + len += scnprintf(buf + len, buf_len - len, "count = %u\n", + htt_stats_buf->count); + + stats_req->buf_len = len; +} + +static inline void htt_print_hw_stats_pdev_errs_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_hw_stats_pdev_errs_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_HW_STATS_PDEV_ERRS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "tx_abort = %u\n", + htt_stats_buf->tx_abort); + len += scnprintf(buf + len, buf_len - len, "tx_abort_fail_count = %u\n", + htt_stats_buf->tx_abort_fail_count); + len += scnprintf(buf + len, buf_len - len, "rx_abort = %u\n", + htt_stats_buf->rx_abort); + len += scnprintf(buf + len, buf_len - len, "rx_abort_fail_count = %u\n", + htt_stats_buf->rx_abort_fail_count); + len += scnprintf(buf + len, buf_len - len, "rx_flush_cnt = %u\n", + htt_stats_buf->rx_flush_cnt); + len += scnprintf(buf + len, buf_len - len, "warm_reset = %u\n", + htt_stats_buf->warm_reset); + len += scnprintf(buf + len, buf_len - len, "cold_reset = %u\n", + htt_stats_buf->cold_reset); + len += scnprintf(buf + len, buf_len - len, "mac_cold_reset_restore_cal = %u\n", + htt_stats_buf->mac_cold_reset_restore_cal); + len += scnprintf(buf + len, buf_len - len, "mac_cold_reset = %u\n", + htt_stats_buf->mac_cold_reset); + len += scnprintf(buf + len, buf_len - len, "mac_warm_reset = %u\n", + htt_stats_buf->mac_warm_reset); + len += scnprintf(buf + len, buf_len - len, "mac_only_reset = %u\n", + htt_stats_buf->mac_only_reset); + len += scnprintf(buf + len, buf_len - len, "phy_warm_reset = %u\n", + htt_stats_buf->phy_warm_reset); + len += scnprintf(buf + len, buf_len - len, "phy_warm_reset_ucode_trig = %u\n", + htt_stats_buf->phy_warm_reset_ucode_trig); + len += scnprintf(buf + len, buf_len - len, "mac_warm_reset_restore_cal = %u\n", + htt_stats_buf->mac_warm_reset_restore_cal); + len += scnprintf(buf + len, buf_len - len, "mac_sfm_reset = %u\n", + htt_stats_buf->mac_sfm_reset); + len += scnprintf(buf + len, buf_len - len, "phy_warm_reset_m3_ssr = %u\n", + htt_stats_buf->phy_warm_reset_m3_ssr); + len += scnprintf(buf + len, buf_len - len, "fw_rx_rings_reset = %u\n", + htt_stats_buf->fw_rx_rings_reset); + len += scnprintf(buf + len, buf_len - len, "tx_flush = %u\n", + htt_stats_buf->tx_flush); + len += scnprintf(buf + len, buf_len - len, "tx_glb_reset = %u\n", + htt_stats_buf->tx_glb_reset); + len += scnprintf(buf + len, buf_len - len, "tx_txq_reset = %u\n", + htt_stats_buf->tx_txq_reset); + len += scnprintf(buf + len, buf_len - len, "rx_timeout_reset = %u\n", + htt_stats_buf->rx_timeout_reset); + len += scnprintf(buf + len, buf_len - len, "PDEV_PHY_WARM_RESET_REASONS:\n"); + len += scnprintf(buf + len, buf_len - len, "phy_warm_reset_reason_phy_m3 = %u\n", + htt_stats_buf->phy_warm_reset_reason_phy_m3); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_tx_hw_stuck = %u\n", + htt_stats_buf->phy_warm_reset_reason_tx_hw_stuck); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_num_cca_rx_frame_stuck = %u\n", + htt_stats_buf->phy_warm_reset_reason_num_cca_rx_frame_stuck); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_wal_rx_recovery_rst_rx_busy = %u\n", + htt_stats_buf->phy_warm_reset_reason_wal_rx_recovery_rst_rx_busy); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_wal_rx_recovery_rst_mac_hang = %u\n", + htt_stats_buf->phy_warm_reset_reason_wal_rx_recovery_rst_mac_hang); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_mac_reset_converted_phy_reset = %u\n", + htt_stats_buf->phy_warm_reset_reason_mac_reset_converted_phy_reset); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_tx_lifetime_expiry_cca_stuck = %u\n", + htt_stats_buf->phy_warm_reset_reason_tx_lifetime_expiry_cca_stuck); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_tx_consecutive_flush9_war = %u\n", + htt_stats_buf->phy_warm_reset_reason_tx_consecutive_flush9_war); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_tx_hwsch_reset_war = %u\n", + htt_stats_buf->phy_warm_reset_reason_tx_hwsch_reset_war); + len += scnprintf(buf + len, buf_len - len, + "phy_warm_reset_reason_hwsch_wdog_or_cca_wdog_war = %u\n\n", + htt_stats_buf->phy_warm_reset_reason_hwsch_wdog_or_cca_wdog_war); + + len += scnprintf(buf + len, buf_len - len, "WAL_RX_RECOVERY_STATS:\n"); + len += scnprintf(buf + len, buf_len - len, + "wal_rx_recovery_rst_mac_hang_count = %u\n", + htt_stats_buf->wal_rx_recovery_rst_mac_hang_count); + len += scnprintf(buf + len, buf_len - len, + "wal_rx_recovery_rst_known_sig_count = %u\n", + htt_stats_buf->wal_rx_recovery_rst_known_sig_count); + len += scnprintf(buf + len, buf_len - len, + "wal_rx_recovery_rst_no_rx_count = %u\n", + htt_stats_buf->wal_rx_recovery_rst_no_rx_count); + len += scnprintf(buf + len, buf_len - len, + "wal_rx_recovery_rst_no_rx_consecutive_count = %u\n", + htt_stats_buf->wal_rx_recovery_rst_no_rx_consecutive_count); + len += scnprintf(buf + len, buf_len - len, + "wal_rx_recovery_rst_rx_busy_count = %u\n", + htt_stats_buf->wal_rx_recovery_rst_rx_busy_count); + len += scnprintf(buf + len, buf_len - len, + "wal_rx_recovery_rst_phy_mac_hang_count = %u\n", + htt_stats_buf->wal_rx_recovery_rst_phy_mac_hang_count); + + stats_req->buf_len = len; +} + +static inline void htt_print_msdu_flow_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_msdu_flow_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 drop_rule = __le32_to_cpu(htt_stats_buf->tx_flow_no__tid_num__drop_rule); + + len += scnprintf(buf + len, buf_len - len, "HTT_MSDU_FLOW_STATS_TLV:"); + len += scnprintf(buf + len, buf_len - len, "last_update_timestamp = %u\n", + htt_stats_buf->last_update_timestamp); + len += scnprintf(buf + len, buf_len - len, "last_add_timestamp = %u\n", + htt_stats_buf->last_add_timestamp); + len += scnprintf(buf + len, buf_len - len, "last_remove_timestamp = %u\n", + htt_stats_buf->last_remove_timestamp); + len += scnprintf(buf + len, buf_len - len, "total_processed_msdu_count = %u\n", + htt_stats_buf->total_processed_msdu_count); + len += scnprintf(buf + len, buf_len - len, "cur_msdu_count_in_flowq = %u\n", + htt_stats_buf->cur_msdu_count_in_flowq); + len += scnprintf(buf + len, buf_len - len, "sw_peer_id = %u\n", + htt_stats_buf->sw_peer_id); + len += scnprintf(buf + len, buf_len - len, "tx_flow_no = %u\n", + u32_get_bits(drop_rule, HTT_MSDU_FLOW_STATS_TX_FLOW_NO)); + len += scnprintf(buf + len, buf_len - len, "tid_num = %u\n", + u32_get_bits(drop_rule, HTT_MSDU_FLOW_STATS_TID_NUM)); + len += scnprintf(buf + len, buf_len - len, "drop_rule = %u\n", + u32_get_bits(drop_rule, HTT_MSDU_FLOW_STATS_DROP_RULE)); + len += scnprintf(buf + len, buf_len - len, "last_cycle_enqueue_count = %u\n", + htt_stats_buf->last_cycle_enqueue_count); + len += scnprintf(buf + len, buf_len - len, "last_cycle_dequeue_count = %u\n", + htt_stats_buf->last_cycle_dequeue_count); + len += scnprintf(buf + len, buf_len - len, "last_cycle_drop_count = %u\n", + htt_stats_buf->last_cycle_drop_count); + len += scnprintf(buf + len, buf_len - len, "current_drop_th = %u\n", + htt_stats_buf->current_drop_th); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_tid_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tid_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char tid_name[MAX_HTT_TID_NAME + 1] = {0}; + u32 tid_num = __le32_to_cpu(htt_stats_buf->sw_peer_id__tid_num); + u32 num_ppdu = __le32_to_cpu(htt_stats_buf->num_sched_pending__num_ppdu_in_hwq); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TID_STATS_TLV:\n"); + memcpy(tid_name, &(htt_stats_buf->tid_name[0]), MAX_HTT_TID_NAME); + len += scnprintf(buf + len, buf_len - len, "tid_name = %s\n", tid_name); + len += scnprintf(buf + len, buf_len - len, "sw_peer_id = %u\n", + u32_get_bits(tid_num, HTT_TX_TID_STATS_SW_PEER_ID)); + len += scnprintf(buf + len, buf_len - len, "tid_num = %u\n", + u32_get_bits(tid_num, HTT_TX_TID_STATS_TID_NUM)); + len += scnprintf(buf + len, buf_len - len, "num_sched_pending = %u\n", + u32_get_bits(tid_num, HTT_TX_TID_STATS_NUM_SCHED_PENDING)); + len += scnprintf(buf + len, buf_len - len, "num_ppdu_in_hwq = %u\n", + u32_get_bits(num_ppdu, HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ)); + len += scnprintf(buf + len, buf_len - len, "tid_flags = 0x%x\n", + htt_stats_buf->tid_flags); + len += scnprintf(buf + len, buf_len - len, "hw_queued = %u\n", + htt_stats_buf->hw_queued); + len += scnprintf(buf + len, buf_len - len, "hw_reaped = %u\n", + htt_stats_buf->hw_reaped); + len += scnprintf(buf + len, buf_len - len, "mpdus_hw_filter = %u\n", + htt_stats_buf->mpdus_hw_filter); + len += scnprintf(buf + len, buf_len - len, "qdepth_bytes = %u\n", + htt_stats_buf->qdepth_bytes); + len += scnprintf(buf + len, buf_len - len, "qdepth_num_msdu = %u\n", + htt_stats_buf->qdepth_num_msdu); + len += scnprintf(buf + len, buf_len - len, "qdepth_num_mpdu = %u\n", + htt_stats_buf->qdepth_num_mpdu); + len += scnprintf(buf + len, buf_len - len, "last_scheduled_tsmp = %u\n", + htt_stats_buf->last_scheduled_tsmp); + len += scnprintf(buf + len, buf_len - len, "pause_module_id = %u\n", + htt_stats_buf->pause_module_id); + len += scnprintf(buf + len, buf_len - len, "block_module_id = %u\n", + htt_stats_buf->block_module_id); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_tid_stats_v1_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tid_stats_v1_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char tid_name[MAX_HTT_TID_NAME + 1] = {0}; + u32 tid_num = __le32_to_cpu(htt_stats_buf->sw_peer_id__tid_num); + u32 num_ppdu = __le32_to_cpu(htt_stats_buf->num_sched_pending__num_ppdu_in_hwq); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TID_STATS_V1_TLV:\n"); + memcpy(tid_name, &(htt_stats_buf->tid_name[0]), MAX_HTT_TID_NAME); + len += scnprintf(buf + len, buf_len - len, "tid_name = %s\n", tid_name); + len += scnprintf(buf + len, buf_len - len, "sw_peer_id = %u\n", + u32_get_bits(tid_num, HTT_TX_TID_STATS_V1_SW_PEER_ID)); + len += scnprintf(buf + len, buf_len - len, "tid_num = %u\n", + u32_get_bits(tid_num, HTT_TX_TID_STATS_V1_TID_NUM)); + len += scnprintf(buf + len, buf_len - len, "num_sched_pending = %u\n", + u32_get_bits(num_ppdu, HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING)); + len += scnprintf(buf + len, buf_len - len, "num_ppdu_in_hwq = %u\n", + u32_get_bits(num_ppdu, HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ)); + len += scnprintf(buf + len, buf_len - len, "tid_flags = 0x%x\n", + htt_stats_buf->tid_flags); + len += scnprintf(buf + len, buf_len - len, "max_qdepth_bytes = %u\n", + htt_stats_buf->max_qdepth_bytes); + len += scnprintf(buf + len, buf_len - len, "max_qdepth_n_msdus = %u\n", + htt_stats_buf->max_qdepth_n_msdus); + len += scnprintf(buf + len, buf_len - len, "rsvd = %u\n", + htt_stats_buf->rsvd); + len += scnprintf(buf + len, buf_len - len, "qdepth_bytes = %u\n", + htt_stats_buf->qdepth_bytes); + len += scnprintf(buf + len, buf_len - len, "qdepth_num_msdu = %u\n", + htt_stats_buf->qdepth_num_msdu); + len += scnprintf(buf + len, buf_len - len, "qdepth_num_mpdu = %u\n", + htt_stats_buf->qdepth_num_mpdu); + len += scnprintf(buf + len, buf_len - len, "last_scheduled_tsmp = %u\n", + htt_stats_buf->last_scheduled_tsmp); + len += scnprintf(buf + len, buf_len - len, "pause_module_id = %u\n", + htt_stats_buf->pause_module_id); + len += scnprintf(buf + len, buf_len - len, "block_module_id = %u\n", + htt_stats_buf->block_module_id); + len += scnprintf(buf + len, buf_len - len, "allow_n_flags = 0x%x\n", + htt_stats_buf->allow_n_flags); + len += scnprintf(buf + len, buf_len - len, "sendn_frms_allowed = %u\n", + htt_stats_buf->sendn_frms_allowed); + + stats_req->buf_len = len; +} + +static inline void htt_print_rx_tid_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_tid_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char tid_name[MAX_HTT_TID_NAME + 1] = {0}; + u32 tid_num = __le32_to_cpu(htt_stats_buf->sw_peer_id__tid_num); + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_TID_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "sw_peer_id = %u\n", + u32_get_bits(tid_num, HTT_RX_TID_STATS_SW_PEER_ID)); + len += scnprintf(buf + len, buf_len - len, "tid_num = %u\n", + u32_get_bits(tid_num, HTT_RX_TID_STATS_TID_NUM)); + memcpy(tid_name, &(htt_stats_buf->tid_name[0]), MAX_HTT_TID_NAME); + len += scnprintf(buf + len, buf_len - len, "tid_name = %s\n", tid_name); + len += scnprintf(buf + len, buf_len - len, "dup_in_reorder = %u\n", + htt_stats_buf->dup_in_reorder); + len += scnprintf(buf + len, buf_len - len, "dup_past_outside_window = %u\n", + htt_stats_buf->dup_past_outside_window); + len += scnprintf(buf + len, buf_len - len, "dup_past_within_window = %u\n", + htt_stats_buf->dup_past_within_window); + len += scnprintf(buf + len, buf_len - len, "rxdesc_err_decrypt = %u\n", + htt_stats_buf->rxdesc_err_decrypt); + + stats_req->buf_len = len; +} + +static inline void htt_print_counter_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_counter_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_COUNTER_TLV:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->counter_name, + "counter_name = %s\n", HTT_MAX_COUNTER_NAME, "\n\n"); + len += scnprintf(buf + len, buf_len - len, "count = %u\n", + htt_stats_buf->count); + + stats_req->buf_len = len; +} + +static inline void htt_print_peer_stats_cmn_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_peer_stats_cmn_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_PEER_STATS_CMN_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "ppdu_cnt = %u\n", + htt_stats_buf->ppdu_cnt); + len += scnprintf(buf + len, buf_len - len, "mpdu_cnt = %u\n", + htt_stats_buf->mpdu_cnt); + len += scnprintf(buf + len, buf_len - len, "msdu_cnt = %u\n", + htt_stats_buf->msdu_cnt); + len += scnprintf(buf + len, buf_len - len, "pause_bitmap = %u\n", + htt_stats_buf->pause_bitmap); + len += scnprintf(buf + len, buf_len - len, "block_bitmap = %u\n", + htt_stats_buf->block_bitmap); + len += scnprintf(buf + len, buf_len - len, "last_rssi = %d\n", + htt_stats_buf->rssi); + len += scnprintf(buf + len, buf_len - len, "enqueued_count = %llu\n", + htt_stats_buf->peer_enqueued_count_low | + ((u64)htt_stats_buf->peer_enqueued_count_high << 32)); + len += scnprintf(buf + len, buf_len - len, "dequeued_count = %llu\n", + htt_stats_buf->peer_dequeued_count_low | + ((u64)htt_stats_buf->peer_dequeued_count_high << 32)); + len += scnprintf(buf + len, buf_len - len, "dropped_count = %llu\n", + htt_stats_buf->peer_dropped_count_low | + ((u64)htt_stats_buf->peer_dropped_count_high << 32)); + len += scnprintf(buf + len, buf_len - len, "transmitted_ppdu_bytes = %llu\n", + htt_stats_buf->ppdu_transmitted_bytes_low | + ((u64)htt_stats_buf->ppdu_transmitted_bytes_high << 32)); + len += scnprintf(buf + len, buf_len - len, "remove_mpdus_max_retries = %u\n", + htt_stats_buf->remove_mpdus_max_retries); + len += scnprintf(buf + len, buf_len - len, "ttl_removed_count = %u\n", + htt_stats_buf->peer_ttl_removed_count); + len += scnprintf(buf + len, buf_len - len, "inactive_time = %u\n", + htt_stats_buf->inactive_time); + + stats_req->buf_len = len; +} + +static inline void htt_print_ast_entry_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_ast_entry_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_addr = __le32_to_cpu(htt_stats_buf->mac_addr.mac_addr_l32); + u32 mac_addr_16 = __le32_to_cpu(htt_stats_buf->mac_addr.mac_addr_h16); + + len += scnprintf(buf + len, buf_len - len, + "mac_addr : %02x:%02x:%02x:%02x:%02x:%02x | ast_index : %u | sw_peer_id : %u | pdev_id : %u | vdev_id : %u\n", + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_0), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_1), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_2), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_3), + u32_get_bits(mac_addr_16, HTT_MAC_ADDR_H16_0), + u32_get_bits(mac_addr_16, HTT_MAC_ADDR_H16_1), + htt_stats_buf->ast_index, htt_stats_buf->sw_peer_id, + htt_stats_buf->pdev_id, htt_stats_buf->vdev_id); + + len += scnprintf(buf + len, buf_len - len, + "next_hop : %u | mcast : %u | monitor_direct :%u | mesh_sta : %u | mec :%u | intra_bss :%u\n", + htt_stats_buf->next_hop, htt_stats_buf->mcast, + htt_stats_buf->monitor_direct, htt_stats_buf->mesh_sta, + htt_stats_buf->mec, htt_stats_buf->intra_bss); + + stats_req->buf_len = len; +} + +static inline void htt_print_peer_details_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_peer_details_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 ast_idx = __le32_to_cpu(htt_stats_buf->vdev_pdev_ast_idx); + u32 mac_addr = __le32_to_cpu(htt_stats_buf->mac_addr.mac_addr_l32); + u32 mac_addr_16 = __le32_to_cpu(htt_stats_buf->mac_addr.mac_addr_h16); + + len += scnprintf(buf + len, buf_len - len, "HTT_PEER_DETAILS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "peer_type = %u\n", + htt_stats_buf->peer_type); + len += scnprintf(buf + len, buf_len - len, "sw_peer_id = %u\n", + htt_stats_buf->sw_peer_id); + len += scnprintf(buf + len, buf_len - len, "vdev_id = %u\n", + u32_get_bits(ast_idx, HTT_PEER_DETAILS_VDEV_ID)); + len += scnprintf(buf + len, buf_len - len, "pdev_id = %u\n", + u32_get_bits(ast_idx, HTT_PEER_DETAILS_PDEV_ID)); + len += scnprintf(buf + len, buf_len - len, "ast_idx = %u\n", + u32_get_bits(ast_idx, HTT_PEER_DETAILS_AST_IDX)); + len += scnprintf(buf + len, buf_len - len, + "mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n", + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_0), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_1), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_2), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_3), + u32_get_bits(mac_addr_16, HTT_MAC_ADDR_H16_0), + u32_get_bits(mac_addr_16, HTT_MAC_ADDR_H16_1)); + len += scnprintf(buf + len, buf_len - len, "peer_flags = 0x%x\n", + htt_stats_buf->peer_flags); + len += scnprintf(buf + len, buf_len - len, "qpeer_flags = 0x%x\n", + htt_stats_buf->qpeer_flags); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_peer_rate_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_peer_rate_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char *tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS] = {NULL}; + u8 j; + + for (j = 0; j < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; j++) { + tx_gi[j] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!tx_gi[j]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PEER_RATE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "tx_ldpc = %u\n", + htt_stats_buf->tx_ldpc); + len += scnprintf(buf + len, buf_len - len, "rts_cnt = %u\n", + htt_stats_buf->rts_cnt); + len += scnprintf(buf + len, buf_len - len, "ack_rssi = %u\n", + htt_stats_buf->ack_rssi); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_mcs, + "tx_mcs = %s\n", HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_su_mcs, "tx_su_mcs", + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_mu_mcs, "tx_mu_mcs", + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_nss, "tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_bw, "tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_stbc, "tx_stbc", + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_pream, "tx_pream", + HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES, "\n"); + + for (j = 0; j < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "tx_gi[%u] = %s ", + j, tx_gi[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_gi[j], NULL, + HTT_TX_PEER_STATS_NUM_MCS_COUNTERS, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_dcm, "tx_dcm", + HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS, "\n\n"); + + stats_req->buf_len = len; + +fail: + for (j = 0; j < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; j++) + kfree(tx_gi[j]); +} + +static inline void htt_print_rx_peer_rate_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_peer_rate_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 i, j; + char *rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] = {NULL}; + char *rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS] = {NULL}; + + for (j = 0; j < HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS; j++) { + rssi_chain[j] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!rssi_chain[j]) + goto fail; + } + + for (j = 0; j < HTT_RX_PEER_STATS_NUM_GI_COUNTERS; j++) { + rx_gi[j] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!rx_gi[j]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_PEER_RATE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "nsts = %u\n", + htt_stats_buf->nsts); + len += scnprintf(buf + len, buf_len - len, "rx_ldpc = %u\n", + htt_stats_buf->rx_ldpc); + len += scnprintf(buf + len, buf_len - len, "rts_cnt = %u\n", + htt_stats_buf->rts_cnt); + len += scnprintf(buf + len, buf_len - len, "rssi_mgmt = %u\n", + htt_stats_buf->rssi_mgmt); + len += scnprintf(buf + len, buf_len - len, "rssi_data = %u\n", + htt_stats_buf->rssi_data); + len += scnprintf(buf + len, buf_len - len, "rssi_comb = %u\n", + htt_stats_buf->rssi_comb); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_mcs, "rx_mcs", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_nss, "rx_nss", + HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_dcm, "rx_dcm", + HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_stbc, "rx_stbc", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_bw, "rx_bw", + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, "rssi_chain[%u] = %s\n", + j, rssi_chain[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rssi_chain[j], NULL, + HTT_RX_PEER_STATS_NUM_BW_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, "\nrssi_chain_ext[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rssi_chain_ext[j], NULL, + HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_RX_PEER_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "rx_gi[%u] = %s\n", + j, rx_gi[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_gi[j], NULL, + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_pream, "rx_pream", + HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\nrx_ulofdma_non_data_ppdu = %u\n", + htt_stats_buf->rx_ulofdma_non_data_ppdu); + len += scnprintf(buf + len, buf_len - len, "rx_ulofdma_data_ppdu = %u\n", + htt_stats_buf->rx_ulofdma_data_ppdu); + len += scnprintf(buf + len, buf_len - len, "rx_ulofdma_mpdu_ok = %u\n", + htt_stats_buf->rx_ulofdma_mpdu_ok); + len += scnprintf(buf + len, buf_len - len, "rx_ulofdma_mpdu_fail = %u\n", + htt_stats_buf->rx_ulofdma_mpdu_fail); + len += scnprintf(buf + len, buf_len - len, "rx_ulmumimo_non_data_ppdu = %u\n", + htt_stats_buf->rx_ulmumimo_non_data_ppdu); + len += scnprintf(buf + len, buf_len - len, "rx_ulmumimo_data_ppdu = %u\n", + htt_stats_buf->rx_ulmumimo_data_ppdu); + len += scnprintf(buf + len, buf_len - len, "rx_ulmumimo_mpdu_ok = %u\n", + htt_stats_buf->rx_ulmumimo_mpdu_ok); + len += scnprintf(buf + len, buf_len - len, "rx_ulmumimo_mpdu_fail = %u\n", + htt_stats_buf->rx_ulmumimo_mpdu_fail); + + len += scnprintf(buf + len, buf_len - len, "rx_ul_fd_rssi = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_ul_fd_rssi, NULL, + HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\nper_chain_rssi_pkt_type = %#x", + htt_stats_buf->per_chain_rssi_pkt_type); + + for (j = 0; j < HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "\nrx_per_chain_rssi_in_dbm[%u] = ", j); + for (i = 0; i < HTT_RX_PDEV_STATS_NUM_BW_COUNTERS; i++) + len += scnprintf(buf + len, + buf_len - len, + " %u:%d,", + i, + htt_stats_buf->rx_per_chain_rssi_in_dbm[j][i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + stats_req->buf_len = len; + +fail: + for (j = 0; j < HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS; j++) + kfree(rssi_chain[j]); + + for (j = 0; j < HTT_RX_PEER_STATS_NUM_GI_COUNTERS; j++) + kfree(rx_gi[j]); +} + +static inline void +htt_print_tx_hwq_mu_mimo_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_mu_mimo_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_HWQ_MU_MIMO_SCH_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_sch_posted = %u\n", + htt_stats_buf->mu_mimo_sch_posted); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_sch_failed = %u\n", + htt_stats_buf->mu_mimo_sch_failed); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_ppdu_posted = %u\n", + htt_stats_buf->mu_mimo_ppdu_posted); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_mu_mimo_mpdu_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_HWQ_MU_MIMO_MPDU_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_mpdus_queued_usr = %u\n", + htt_stats_buf->mu_mimo_mpdus_queued_usr); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_mpdus_tried_usr = %u\n", + htt_stats_buf->mu_mimo_mpdus_tried_usr); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_mpdus_failed_usr = %u\n", + htt_stats_buf->mu_mimo_mpdus_failed_usr); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_mpdus_requeued_usr = %u\n", + htt_stats_buf->mu_mimo_mpdus_requeued_usr); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_err_no_ba_usr = %u\n", + htt_stats_buf->mu_mimo_err_no_ba_usr); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_mpdu_underrun_usr = %u\n", + htt_stats_buf->mu_mimo_mpdu_underrun_usr); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_ampdu_underrun_usr = %u\n", + htt_stats_buf->mu_mimo_ampdu_underrun_usr); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_mu_mimo_cmn_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_mu_mimo_cmn_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__hwq_id__word); + len += scnprintf(buf + len, buf_len - len, "HTT_TX_HWQ_MU_MIMO_CMN_STATS_TLV:\n"); + + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_TX_HWQ_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "hwq_id = %u\n\n", + u32_get_bits(mac_id_word, HTT_TX_HWQ_STATS_HWQ_ID)); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_stats_cmn_tlv(const void *tag_buf, struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_stats_cmn_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__hwq_id__word); + + /* TODO: HKDBG */ + len += scnprintf(buf + len, buf_len - len, "HTT_TX_HWQ_STATS_CMN_TLV:"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_TX_HWQ_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "hwq_id = %u\n", + u32_get_bits(mac_id_word, HTT_TX_HWQ_STATS_HWQ_ID)); + len += scnprintf(buf + len, buf_len - len, "xretry = %u\n", + htt_stats_buf->xretry); + len += scnprintf(buf + len, buf_len - len, "underrun_cnt = %u\n", + htt_stats_buf->underrun_cnt); + len += scnprintf(buf + len, buf_len - len, "flush_cnt = %u\n", + htt_stats_buf->flush_cnt); + len += scnprintf(buf + len, buf_len - len, "filt_cnt = %u\n", + htt_stats_buf->filt_cnt); + len += scnprintf(buf + len, buf_len - len, "null_mpdu_bmap = %u\n", + htt_stats_buf->null_mpdu_bmap); + len += scnprintf(buf + len, buf_len - len, "user_ack_failure = %u\n", + htt_stats_buf->user_ack_failure); + len += scnprintf(buf + len, buf_len - len, "ack_tlv_proc = %u\n", + htt_stats_buf->ack_tlv_proc); + len += scnprintf(buf + len, buf_len - len, "sched_id_proc = %u\n", + htt_stats_buf->sched_id_proc); + len += scnprintf(buf + len, buf_len - len, "null_mpdu_tx_count = %u\n", + htt_stats_buf->null_mpdu_tx_count); + len += scnprintf(buf + len, buf_len - len, "mpdu_bmap_not_recvd = %u\n", + htt_stats_buf->mpdu_bmap_not_recvd); + len += scnprintf(buf + len, buf_len - len, "num_bar = %u\n", + htt_stats_buf->num_bar); + len += scnprintf(buf + len, buf_len - len, "rts = %u\n", + htt_stats_buf->rts); + len += scnprintf(buf + len, buf_len - len, "cts2self = %u\n", + htt_stats_buf->cts2self); + len += scnprintf(buf + len, buf_len - len, "qos_null = %u\n", + htt_stats_buf->qos_null); + len += scnprintf(buf + len, buf_len - len, "mpdu_tried_cnt = %u\n", + htt_stats_buf->mpdu_tried_cnt); + len += scnprintf(buf + len, buf_len - len, "mpdu_queued_cnt = %u\n", + htt_stats_buf->mpdu_queued_cnt); + len += scnprintf(buf + len, buf_len - len, "mpdu_ack_fail_cnt = %u\n", + htt_stats_buf->mpdu_ack_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "mpdu_filt_cnt = %u\n", + htt_stats_buf->mpdu_filt_cnt); + len += scnprintf(buf + len, buf_len - len, "false_mpdu_ack_count = %u\n", + htt_stats_buf->false_mpdu_ack_count); + len += scnprintf(buf + len, buf_len - len, "txq_timeout = %u\n", + htt_stats_buf->txq_timeout); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_difs_latency_stats_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_difs_latency_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 data_len = min_t(u16, (tag_len >> 2), HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_HWQ_DIFS_LATENCY_STATS_TLV_V:"); + len += scnprintf(buf + len, buf_len - len, "hist_intvl = %u", + htt_stats_buf->hist_intvl); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->difs_latency_hist, + "difs_latency_hist", data_len, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_cmd_result_stats_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_cmd_result_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 data_len; + + data_len = min_t(u16, (tag_len >> 2), HTT_TX_HWQ_MAX_CMD_RESULT_STATS); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_HWQ_CMD_RESULT_STATS_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->cmd_result, "cmd_result", + data_len, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_cmd_stall_stats_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_cmd_stall_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems; + + num_elems = min_t(u16, (tag_len >> 2), HTT_TX_HWQ_MAX_CMD_STALL_STATS); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_HWQ_CMD_STALL_STATS_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->cmd_stall_status, + "cmd_stall_status", num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_fes_result_stats_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_fes_result_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems; + + num_elems = min_t(u16, (tag_len >> 2), HTT_TX_HWQ_MAX_FES_RESULT_STATS); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_HWQ_FES_RESULT_STATS_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->fes_result, "fes_result", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_tried_mpdu_cnt_hist_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = ((tag_len - + sizeof(htt_stats_buf->hist_bin_size)) >> 2); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_HWQ_TRIED_MPDU_CNT_HIST_TLV_V:\n"); + len += scnprintf(buf + len, buf_len - len, "TRIED_MPDU_CNT_HIST_BIN_SIZE : %u\n", + htt_stats_buf->hist_bin_size); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tried_mpdu_cnt_hist, + "tried_mpdu_cnt_hist", num_elements, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_hwq_txop_used_cnt_hist_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_hwq_txop_used_cnt_hist_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = tag_len >> 2; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_HWQ_TXOP_USED_CNT_HIST_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->txop_used_cnt_hist, + "txop_used_cnt_hist", num_elements, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_sounding_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + s32 i; + const struct htt_tx_sounding_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + const u32 *cbf_20 = htt_stats_buf->cbf_20; + const u32 *cbf_40 = htt_stats_buf->cbf_40; + const u32 *cbf_80 = htt_stats_buf->cbf_80; + const u32 *cbf_160 = htt_stats_buf->cbf_160; + + if (htt_stats_buf->tx_sounding_mode == HTT_TX_AC_SOUNDING_MODE) { + len += scnprintf(buf + len, buf_len - len, + "\nHTT_TX_AC_SOUNDING_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, + "ac_cbf_20 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_20[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + len += scnprintf(buf + len, buf_len - len, + "ac_cbf_40 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_40[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + len += scnprintf(buf + len, buf_len - len, + "ac_cbf_80 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_80[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + len += scnprintf(buf + len, buf_len - len, + "ac_cbf_160 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_160[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "Sounding User %u = 20MHz: %u, 40MHz : %u, 80MHz: %u, 160MHz: %u\n", + i, + htt_stats_buf->sounding[0], + htt_stats_buf->sounding[1], + htt_stats_buf->sounding[2], + htt_stats_buf->sounding[3]); + } + } else if (htt_stats_buf->tx_sounding_mode == HTT_TX_AX_SOUNDING_MODE) { + len += scnprintf(buf + len, buf_len - len, + "\nHTT_TX_AX_SOUNDING_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, + "ax_cbf_20 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_20[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_20[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + len += scnprintf(buf + len, buf_len - len, + "ax_cbf_40 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_40[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_40[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + len += scnprintf(buf + len, buf_len - len, + "ax_cbf_80 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_80[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_80[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + len += scnprintf(buf + len, buf_len - len, + "ax_cbf_160 = IBF : %u, SU_SIFS : %u, SU_RBO : %u, MU_SIFS : %u, MU_RBO : %u\n", + cbf_160[HTT_IMPLICIT_TXBF_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS], + cbf_160[HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS]); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "Sounding User %u = 20MHz: %u, 40MHz : %u, 80MHz: %u, 160MHz: %u\n", + i, + htt_stats_buf->sounding[0], + htt_stats_buf->sounding[1], + htt_stats_buf->sounding[2], + htt_stats_buf->sounding[3]); + } + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_cmn_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_cmn_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_SELFGEN_CMN_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "su_bar = %u\n", + htt_stats_buf->su_bar); + len += scnprintf(buf + len, buf_len - len, "rts = %u\n", + htt_stats_buf->rts); + len += scnprintf(buf + len, buf_len - len, "cts2self = %u\n", + htt_stats_buf->cts2self); + len += scnprintf(buf + len, buf_len - len, "qos_null = %u\n", + htt_stats_buf->qos_null); + len += scnprintf(buf + len, buf_len - len, "delayed_bar_1 = %u\n", + htt_stats_buf->delayed_bar_1); + len += scnprintf(buf + len, buf_len - len, "delayed_bar_2 = %u\n", + htt_stats_buf->delayed_bar_2); + len += scnprintf(buf + len, buf_len - len, "delayed_bar_3 = %u\n", + htt_stats_buf->delayed_bar_3); + len += scnprintf(buf + len, buf_len - len, "delayed_bar_4 = %u\n", + htt_stats_buf->delayed_bar_4); + len += scnprintf(buf + len, buf_len - len, "delayed_bar_5 = %u\n", + htt_stats_buf->delayed_bar_5); + len += scnprintf(buf + len, buf_len - len, "delayed_bar_6 = %u\n", + htt_stats_buf->delayed_bar_6); + len += scnprintf(buf + len, buf_len - len, "delayed_bar_7 = %u\n", + htt_stats_buf->delayed_bar_7); + len += scnprintf(buf + len, buf_len - len, "bar_with_tqm_head_seq_num = %u\n", + htt_stats_buf->bar_with_tqm_head_seq_num); + len += scnprintf(buf + len, buf_len - len, "bar_with_tid_seq_num = %u\n", + htt_stats_buf->bar_with_tid_seq_num); + len += scnprintf(buf + len, buf_len - len, "su_sw_rts_queued = %u\n", + htt_stats_buf->su_sw_rts_queued); + len += scnprintf(buf + len, buf_len - len, "su_sw_rts_tried = %u\n", + htt_stats_buf->su_sw_rts_tried); + len += scnprintf(buf + len, buf_len - len, "su_sw_rts_err = %u\n", + htt_stats_buf->su_sw_rts_err); + len += scnprintf(buf + len, buf_len - len, "su_sw_rts_flushed = %u\n", + htt_stats_buf->su_sw_rts_flushed); + len += scnprintf(buf + len, buf_len - len, "su_sw_rts_rcvd_cts_diff_bw = %u\n", + htt_stats_buf->su_sw_rts_rcvd_cts_diff_bw); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_ac_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_ac_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_SELFGEN_AC_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndpa_queued = %u\n", + htt_stats_buf->ac_su_ndpa_queued); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndpa_tried = %u", + htt_stats_buf->ac_su_ndpa); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndp_queued = %u\n", + htt_stats_buf->ac_su_ndp_queued); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndp_tried = %u", + htt_stats_buf->ac_su_ndp); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndpa_queued = %u\n", + htt_stats_buf->ac_mu_mimo_ndpa_queued); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndpa_tried = %u", + htt_stats_buf->ac_mu_mimo_ndpa); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndp_queued = %u\n", + htt_stats_buf->ac_mu_mimo_ndp_queued); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndp_tried = %u", + htt_stats_buf->ac_mu_mimo_ndp); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brpoll_1_queued = %u\n", + htt_stats_buf->ac_mu_mimo_brpoll_1_queued); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brpoll_1_tried = %u", + htt_stats_buf->ac_mu_mimo_brpoll_1); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brpoll_2_queued = %u\n", + htt_stats_buf->ac_mu_mimo_brpoll_2_queued); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brpoll_2_tried = %u", + htt_stats_buf->ac_mu_mimo_brpoll_2); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brpoll_3_queued = %u\n", + htt_stats_buf->ac_mu_mimo_brpoll_3_queued); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brpoll_3_tried = %u\n", + htt_stats_buf->ac_mu_mimo_brpoll_3); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_ax_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_ax_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_SELFGEN_AX_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndpa_queued = %u\n", + htt_stats_buf->ax_su_ndpa_queued); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndpa_tried = %u\n", + htt_stats_buf->ax_su_ndpa); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndp_queued = %u\n", + htt_stats_buf->ax_su_ndp_queued); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndp_tried = %u\n", + htt_stats_buf->ax_su_ndp); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndpa_queued = %u\n", + htt_stats_buf->ax_mu_mimo_ndpa_queued); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndpa_tried = %u\n", + htt_stats_buf->ax_mu_mimo_ndpa); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndp_queued = %u\n", + htt_stats_buf->ax_mu_mimo_ndp_queued); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndp_tried = %u\n", + htt_stats_buf->ax_mu_mimo_ndp); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_brpoll_queued, + "ax_mu_mimo_brpollX_queued", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_brpoll, + "ax_mu_mimo_brpollX_tried", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mumimo_trigger, + "ax_ul_mumimo_trigger", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS, "\n"); + len += scnprintf(buf + len, buf_len - len, "ax_basic_trigger = %u\n", + htt_stats_buf->ax_basic_trigger); + len += scnprintf(buf + len, buf_len - len, "ax_bsr_trigger = %u\n", + htt_stats_buf->ax_bsr_trigger); + len += scnprintf(buf + len, buf_len - len, "ax_mu_bar_trigger = %u\n", + htt_stats_buf->ax_mu_bar_trigger); + len += scnprintf(buf + len, buf_len - len, "ax_mu_rts_trigger = %u\n", + htt_stats_buf->ax_mu_rts_trigger); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_ac_err_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_ac_err_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_SELFGEN_AC_ERR_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndp_err = %u\n", + htt_stats_buf->ac_su_ndp_err); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndp_flushed = %u\n", + htt_stats_buf->ac_su_ndp_flushed); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndpa_err = %u\n", + htt_stats_buf->ac_su_ndpa_err); + len += scnprintf(buf + len, buf_len - len, "ac_su_ndpa_flushed = %u\n", + htt_stats_buf->ac_su_ndpa_flushed); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndpa_err = %u\n", + htt_stats_buf->ac_mu_mimo_ndpa_err); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndpa_flushed = %u\n", + htt_stats_buf->ac_mu_mimo_ndpa_flushed); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndp_err = %u\n", + htt_stats_buf->ac_mu_mimo_ndp_err); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_ndp_flushed = %u\n", + htt_stats_buf->ac_mu_mimo_ndp_flushed); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brp1_err = %u\n", + htt_stats_buf->ac_mu_mimo_brp1_err); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brp2_err = %u\n", + htt_stats_buf->ac_mu_mimo_brp2_err); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brp3_err = %u\n", + htt_stats_buf->ac_mu_mimo_brp3_err); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brp1_flushed = %u\n", + htt_stats_buf->ac_mu_mimo_brp1_flushed); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brp2_flushed = %u\n", + htt_stats_buf->ac_mu_mimo_brp2_flushed); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_brp3_flushed = %u\n", + htt_stats_buf->ac_mu_mimo_brp3_flushed); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_ax_err_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_ax_err_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_SELFGEN_AX_ERR_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndp_err = %u\n", + htt_stats_buf->ax_su_ndp_err); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndp_flushed = %u\n", + htt_stats_buf->ax_su_ndp_flushed); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndpa_err = %u\n", + htt_stats_buf->ax_su_ndpa_err); + len += scnprintf(buf + len, buf_len - len, "ax_su_ndpa_flushed = %u\n", + htt_stats_buf->ax_su_ndpa_flushed); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndpa_err = %u\n", + htt_stats_buf->ax_mu_mimo_ndpa_err); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndpa_flushed = %u\n", + htt_stats_buf->ax_mu_mimo_ndpa_flushed); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndp_err = %u\n", + htt_stats_buf->ax_mu_mimo_ndp_err); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_ndp_flushed = %u\n", + htt_stats_buf->ax_mu_mimo_ndp_flushed); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_brp_err, + "ax_mu_mimo_brpX_err", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_brpoll_flushed, + "ax_mu_mimo_brpollX_flushed", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_brp_err_num_cbf_received, + "ax_mu_mimo_num_cbf_rcvd_on_brp_err", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mumimo_trigger_err, + "ax_ul_mumimo_trigger_err", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "ax_basic_trigger_err = %u\n", + htt_stats_buf->ax_basic_trigger_err); + len += scnprintf(buf + len, buf_len - len, "ax_bsr_trigger_err = %u\n", + htt_stats_buf->ax_bsr_trigger_err); + len += scnprintf(buf + len, buf_len - len, "ax_mu_bar_trigger_err = %u\n", + htt_stats_buf->ax_mu_bar_trigger_err); + len += scnprintf(buf + len, buf_len - len, "ax_mu_rts_trigger_err = %u\n", + htt_stats_buf->ax_mu_rts_trigger_err); + + stats_req->buf_len = len; +} + +static inline +void htt_print_tx_selfgen_ac_sched_status_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_ac_sched_status_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_SELFGEN_AC_SCHED_STATUS_STATS_TLV:"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_su_ndpa_sch_status, + "ac_su_ndpa_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_su_ndp_sch_status, + "ac_su_ndp_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_ndpa_sch_status, + "ac_mu_mimo_ndpa_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_ndp_sch_status, + "ac_mu_mimo_ndp_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_brp_sch_status, + "ac_mu_mimo_brp_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_su_ndp_sch_flag_err, + "ac_su_ndp_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_ndp_sch_flag_err, + "ac_mu_mimo_ndp_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_brp_sch_flag_err, + "ac_mu_mimo_brp_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_ax_sched_status_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_ax_sched_status_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_SELFGEN_AX_SCHED_STATUS_STATS_TLV:"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_su_ndpa_sch_status, + "ax_su_ndpa_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_su_ndp_sch_status, + "ax_su_ndp_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_ndpa_sch_status, + "ax_mu_mimo_ndpa_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_ndp_sch_status, + "ax_mu_mimo_ndp_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_brp_sch_status, + "ax_mu_brp_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_bar_sch_status, + "ax_mu_bar_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_basic_trig_sch_status, + "ax_basic_trig_sch_status = %s ", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_su_ndp_sch_flag_err, + "ax_su_ndp_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_ndp_sch_flag_err, + "ax_mu_mimo_ndp_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_brp_sch_flag_err, + "ax_mu_brp_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_bar_sch_flag_err, + "ax_mu_bar_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_basic_trig_sch_flag_err, + "ax_basic_trig_sch_flag_err = %s ", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_dl_mu_ofdma_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "11ax DL MU_OFDMA SCH STATS:\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_ofdma_sch_nusers, + "ax_mu_ofdma_sch_nusers", + HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_ul_mu_ofdma_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "11ax UL MU_OFDMA SCH STATS:\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mu_ofdma_basic_sch_nusers, + "ax_ul_mu_ofdma_basic_sch_nusers", + HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mu_ofdma_bsr_sch_nusers, + "ax_ul_mu_ofdma_bsr_sch_nusers", + HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mu_ofdma_bar_sch_nusers, + "ax_ul_mu_ofdma_bar_sch_nusers", + HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mu_ofdma_brp_sch_nusers, + "ax_ul_mu_ofdma_brp_sch_nusers", + HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_ul_mu_mimo_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_ul_mu_mimo_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "11ax UL MU_MIMO SCH STATS:\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mu_mimo_basic_sch_nusers, + "ax_ul_mu_mimo_basic_sch_nusers", + HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_ul_mu_mimo_brp_sch_nusers, + "ax_ul_mu_mimo_brp_sch_nusers", + HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_dl_mu_mimo_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_dl_mu_mimo_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_MU_MIMO_SCH_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_sch_posted = %u\n", + htt_stats_buf->mu_mimo_sch_posted); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_sch_failed = %u\n", + htt_stats_buf->mu_mimo_sch_failed); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_ppdu_posted = %u\n", + htt_stats_buf->mu_mimo_ppdu_posted); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_sch_posted_per_grp_sz, + "ac_mu_mimo_sch_posted_per_group_index", + HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_sch_posted_per_grp_sz, + "ax_mu_mimo_sch_posted_per_group_index", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "11ac DL MU_MIMO SCH STATS:\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_sch_nusers, + "ac_mu_mimo_sch_nusers", + HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\n11ax DL MU_MIMO SCH STATS:\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_sch_nusers, + "ax_mu_mimo_sch_nusers", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_mu_mimo_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_mu_mimo_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 i; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_MU_MIMO_SCH_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_sch_posted = %u\n", + htt_stats_buf->mu_mimo_sch_posted); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_sch_failed = %u\n", + htt_stats_buf->mu_mimo_sch_failed); + len += scnprintf(buf + len, buf_len - len, "mu_mimo_ppdu_posted = %u\n", + htt_stats_buf->mu_mimo_ppdu_posted); + + len += scnprintf(buf + len, buf_len - len, + "\nac_mu_mimo_sch_posted_per_group_index %u (SU) = %u,\n", + 0, htt_stats_buf->ac_mu_mimo_sch_posted_per_grp_sz[0]); + for (i = 1; i < HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_sch_posted_per_group_index %u (TOTAL STREAMS = %u) = %u,\n", + i, i+1, htt_stats_buf->ac_mu_mimo_sch_posted_per_grp_sz[i]); + } + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_sch_posted_per_group_index %u (TOTAL STREAMS = %u) = %u,\n", + i+HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS, + i+HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS+1, + htt_stats_buf->ac_mu_mimo_sch_posted_per_grp_sz_ext[i]); + } + + len += scnprintf(buf + len, buf_len - len, + "\nax_mu_mimo_sch_posted_per_group_index %u (SU) = %u,\n", + 0, htt_stats_buf->ax_mu_mimo_sch_posted_per_grp_sz[0]); + for (i = 1; i < HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_sch_posted_per_group_index %u (TOTAL STREAMS = %u) = %u,\n", + i, i+1, htt_stats_buf->ax_mu_mimo_sch_posted_per_grp_sz[i]); + } + + len += scnprintf(buf + len, buf_len - len, + "\nbe_mu_mimo_sch_posted_per_group_index %u (SU) = %u,\n", + 0, htt_stats_buf->be_mu_mimo_sch_posted_per_grp_sz[0]); + for (i = 1; i < HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_sch_posted_per_group_index %u (TOTAL STREAMS = %u) = %u,\n", + i, i+1, htt_stats_buf->be_mu_mimo_sch_posted_per_grp_sz[i]); + } + + len += scnprintf(buf + len, buf_len - len, "\n11ac MU_MIMO SCH STATS:\n"); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS; i++) + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_sch_nusers_%u = %u\n", + i, htt_stats_buf->ac_mu_mimo_sch_nusers[i]); + + len += scnprintf(buf + len, buf_len - len, "\n11ax MU_MIMO SCH STATS:\n"); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS; i++) + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_sch_nusers_%u = %u\n", + i, htt_stats_buf->ax_mu_mimo_sch_nusers[i]); + + len += scnprintf(buf + len, buf_len - len, "\n11be MU_MIMO SCH STATS:\n"); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_sch_nusers_%u = %u\n", + i, htt_stats_buf->be_mu_mimo_sch_nusers[i]); + } + + len += scnprintf(buf + len, buf_len - len, "\n11ax OFDMA SCH STATS:\n"); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_sch_nusers_%u = %u\n", + i, htt_stats_buf->ax_ofdma_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ul_ofdma_basic_sch_nusers_%u = %u\n", + i, htt_stats_buf->ax_ul_ofdma_basic_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ul_ofdma_bsr_sch_nusers_%u = %u\n", + i, htt_stats_buf->ax_ul_ofdma_bsr_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ul_ofdma_bar_sch_nusers_%u = %u\n", + i, htt_stats_buf->ax_ul_ofdma_bar_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ul_ofdma_brp_sch_nusers_%u = %u\n", + i, htt_stats_buf->ax_ul_ofdma_brp_sch_nusers[i]); + } + + len += scnprintf(buf + len, buf_len - len, + "\n11ax UL MUMIMO SCH STATS:"); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ax_ul_mumimo_basic_sch_nusers_%u = %u\n", i, + htt_stats_buf->ax_ul_mumimo_basic_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ul_mumimo_brp_sch_nusers_%u = %u\n", i, + htt_stats_buf->ax_ul_mumimo_brp_sch_nusers[i]); + } + + stats_req->buf_len = len; +} + +static inline +void htt_print_tx_pdev_mumimo_grp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_mumimo_grp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int j; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_MUMIMO_GRP_STATS:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->dl_mumimo_grp_best_grp_size, + "dl_mumimo_grp_best_grp_size", HTT_STATS_MAX_MUMIMO_GRP_SZ, + "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->dl_mumimo_grp_best_num_usrs, + "dl_mumimo_grp_best_num_usrs", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->dl_mumimo_grp_tputs, + "dl_mumimo_grp_tputs_observed (per bin = 300 mbps)", + HTT_STATS_MUMIMO_TPUT_NUM_BINS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->dl_mumimo_grp_eligible, + "dl_mumimo_grp eligible", HTT_STATS_MAX_MUMIMO_GRP_SZ, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->dl_mumimo_grp_ineligible, + "dl_mumimo_grp_ineligible", HTT_STATS_MAX_MUMIMO_GRP_SZ, "\n"); + for (j = 0; j < HTT_STATS_MAX_MUMIMO_GRP_SZ; j++) { + len += scnprintf(buf + len, buf_len - len, "grp_id = %u", j); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->dl_mumimo_grp_invalid, NULL, + HTT_STATS_MAX_INVALID_REASON_CODE, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_mumimo_grp_best_grp_size, + "ul_mumimo_grp_best_grp_size", HTT_STATS_MAX_MUMIMO_GRP_SZ, + "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_mumimo_grp_best_num_usrs, + "ul_mumimo_grp_best_num_usrs", + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_mumimo_grp_tputs, + "ul_mumimo_grp_tputs_observed (per bin = 300 mbps)", + HTT_STATS_MUMIMO_TPUT_NUM_BINS, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_mu_mimo_mpdu_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_mpdu_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + if (htt_stats_buf->tx_sched_mode == HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC) { + if (!htt_stats_buf->user_index) + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_MU_MIMO_AC_MPDU_STATS:\n"); + + if (htt_stats_buf->user_index < + HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS) { + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_mpdus_queued_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_queued_usr); + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_mpdus_tried_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_tried_usr); + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_mpdus_failed_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_failed_usr); + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_mpdus_requeued_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_requeued_usr); + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_err_no_ba_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->err_no_ba_usr); + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_mpdu_underrun_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdu_underrun_usr); + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_ampdu_underrun_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->ampdu_underrun_usr); + } + } + + if (htt_stats_buf->tx_sched_mode == HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX) { + if (!htt_stats_buf->user_index) + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_MU_MIMO_AX_MPDU_STATS:\n"); + + if (htt_stats_buf->user_index < + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) { + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_mpdus_queued_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_queued_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_mpdus_tried_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_tried_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_mpdus_failed_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_failed_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_mpdus_requeued_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_requeued_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_err_no_ba_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->err_no_ba_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_mpdu_underrun_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdu_underrun_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_ampdu_underrun_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->ampdu_underrun_usr); + } + } + + if (htt_stats_buf->tx_sched_mode == HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX) { + if (!htt_stats_buf->user_index) + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_AX_MU_OFDMA_MPDU_STATS:\n"); + + if (htt_stats_buf->user_index < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS) { + len += scnprintf(buf + len, buf_len - len, + "ax_mu_ofdma_mpdus_queued_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_queued_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_ofdma_mpdus_tried_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_tried_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_ofdma_mpdus_failed_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_failed_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_ofdma_mpdus_requeued_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdus_requeued_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_ofdma_err_no_ba_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->err_no_ba_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_ofdma_mpdu_underrun_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->mpdu_underrun_usr); + len += scnprintf(buf + len, buf_len - len, + "ax_mu_ofdma_ampdu_underrun_usr_%u = %u\n", + htt_stats_buf->user_index, + htt_stats_buf->ampdu_underrun_usr); + } + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_sched_txq_cmd_posted_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sched_txq_cmd_posted_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elements = min_t(u16, (tag_len >> 2), HTT_TX_PDEV_SCHED_TX_MODE_MAX); + + len += scnprintf(buf + len, buf_len - len, "HTT_SCHED_TXQ_CMD_POSTED_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->sched_cmd_posted, + "sched_cmd_posted", num_elements, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_sched_txq_cmd_reaped_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sched_txq_cmd_reaped_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elements = min_t(u16, (tag_len >> 2), HTT_TX_PDEV_SCHED_TX_MODE_MAX); + + len += scnprintf(buf + len, buf_len - len, "HTT_SCHED_TXQ_CMD_REAPED_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->sched_cmd_reaped, + "sched_cmd_reaped", num_elements, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_sched_txq_sched_order_su_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sched_txq_sched_order_su_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + /* each entry is u32, i.e. 4 bytes */ + u32 sched_order_su_num_entries = + min_t(u32, (tag_len >> 2), HTT_TX_PDEV_NUM_SCHED_ORDER_LOG); + + len += scnprintf(buf + len, buf_len - len, + "HTT_SCHED_TXQ_SCHED_ORDER_SU_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->sched_order_su, "sched_order_su", + sched_order_su_num_entries, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_sched_txq_sched_ineligibility_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sched_txq_sched_ineligibility_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + /* each entry is u32, i.e. 4 bytes */ + u32 sched_ineligibility_num_entries = tag_len >> 2; + + len += scnprintf(buf + len, buf_len - len, + "HTT_SCHED_TXQ_SCHED_INELIGIBILITY_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->sched_ineligibility, + "sched_ineligibility", sched_ineligibility_num_entries, + "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_sched_per_txq_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_sched_per_txq_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__txq_id__word); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, + HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "txq_id = %u\n", + u32_get_bits(mac_id_word, HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID)); + len += scnprintf(buf + len, buf_len - len, "sched_policy = %u\n", + htt_stats_buf->sched_policy); + len += scnprintf(buf + len, buf_len - len, + "last_sched_cmd_posted_timestamp = %u\n", + htt_stats_buf->last_sched_cmd_posted_timestamp); + len += scnprintf(buf + len, buf_len - len, + "last_sched_cmd_compl_timestamp = %u\n", + htt_stats_buf->last_sched_cmd_compl_timestamp); + len += scnprintf(buf + len, buf_len - len, "sched_2_tac_lwm_count = %u\n", + htt_stats_buf->sched_2_tac_lwm_count); + len += scnprintf(buf + len, buf_len - len, "sched_2_tac_ring_full = %u\n", + htt_stats_buf->sched_2_tac_ring_full); + len += scnprintf(buf + len, buf_len - len, "sched_cmd_post_failure = %u\n", + htt_stats_buf->sched_cmd_post_failure); + len += scnprintf(buf + len, buf_len - len, "num_active_tids = %u\n", + htt_stats_buf->num_active_tids); + len += scnprintf(buf + len, buf_len - len, "num_ps_schedules = %u\n", + htt_stats_buf->num_ps_schedules); + len += scnprintf(buf + len, buf_len - len, "sched_cmds_pending = %u\n", + htt_stats_buf->sched_cmds_pending); + len += scnprintf(buf + len, buf_len - len, "num_tid_register = %u\n", + htt_stats_buf->num_tid_register); + len += scnprintf(buf + len, buf_len - len, "num_tid_unregister = %u\n", + htt_stats_buf->num_tid_unregister); + len += scnprintf(buf + len, buf_len - len, "num_qstats_queried = %u\n", + htt_stats_buf->num_qstats_queried); + len += scnprintf(buf + len, buf_len - len, "qstats_update_pending = %u\n", + htt_stats_buf->qstats_update_pending); + len += scnprintf(buf + len, buf_len - len, "last_qstats_query_timestamp = %u\n", + htt_stats_buf->last_qstats_query_timestamp); + len += scnprintf(buf + len, buf_len - len, "num_tqm_cmdq_full = %u\n", + htt_stats_buf->num_tqm_cmdq_full); + len += scnprintf(buf + len, buf_len - len, "num_de_sched_algo_trigger = %u\n", + htt_stats_buf->num_de_sched_algo_trigger); + len += scnprintf(buf + len, buf_len - len, "num_rt_sched_algo_trigger = %u\n", + htt_stats_buf->num_rt_sched_algo_trigger); + len += scnprintf(buf + len, buf_len - len, "num_tqm_sched_algo_trigger = %u\n", + htt_stats_buf->num_tqm_sched_algo_trigger); + len += scnprintf(buf + len, buf_len - len, "notify_sched = %u\n", + htt_stats_buf->notify_sched); + len += scnprintf(buf + len, buf_len - len, "dur_based_sendn_term = %u\n", + htt_stats_buf->dur_based_sendn_term); + len += scnprintf(buf + len, buf_len - len, "su_notify2_sched = %u\n", + htt_stats_buf->su_notify2_sched); + len += scnprintf(buf + len, buf_len - len, "su_optimal_queued_msdus_sched = %u\n", + htt_stats_buf->su_optimal_queued_msdus_sched); + len += scnprintf(buf + len, buf_len - len, "su_delay_timeout_sched = %u\n", + htt_stats_buf->su_delay_timeout_sched); + len += scnprintf(buf + len, buf_len - len, "su_min_txtime_sched_delay = %u\n", + htt_stats_buf->su_min_txtime_sched_delay); + len += scnprintf(buf + len, buf_len - len, "su_no_delay = %u\n", + htt_stats_buf->su_no_delay); + len += scnprintf(buf + len, buf_len - len, "num_supercycles = %u\n", + htt_stats_buf->num_supercycles); + len += scnprintf(buf + len, buf_len - len, "num_subcycles_with_sort = %u\n", + htt_stats_buf->num_subcycles_with_sort); + len += scnprintf(buf + len, buf_len - len, "num_subcycles_no_sort = %u\n", + htt_stats_buf->num_subcycles_no_sort); + + stats_req->buf_len = len; +} + +static inline void htt_print_stats_tx_sched_cmn_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_stats_tx_sched_cmn_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_STATS_TX_SCHED_CMN_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "current_timestamp = %u\n", + htt_stats_buf->current_timestamp); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_tqm_gen_mpdu_stats_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tqm_gen_mpdu_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elements = min_t(u16, (tag_len >> 2), + HTT_TX_TQM_MAX_LIST_MPDU_END_REASON); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TQM_GEN_MPDU_STATS_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->gen_mpdu_end_reason, + "gen_mpdu_end_reason", num_elements, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_tqm_list_mpdu_stats_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tqm_list_mpdu_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_TX_TQM_MAX_LIST_MPDU_END_REASON); + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_TQM_LIST_MPDU_STATS_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->list_mpdu_end_reason, + "list_mpdu_end_reason", num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_tqm_list_mpdu_cnt_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tqm_list_mpdu_cnt_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), + HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TQM_LIST_MPDU_CNT_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->list_mpdu_cnt_hist, + "list_mpdu_cnt_hist", num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_tqm_pdev_stats_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tqm_pdev_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TQM_PDEV_STATS_TLV_V:\n"); + len += scnprintf(buf + len, buf_len - len, "msdu_count = %u\n", + htt_stats_buf->msdu_count); + len += scnprintf(buf + len, buf_len - len, "mpdu_count = %u\n", + htt_stats_buf->mpdu_count); + len += scnprintf(buf + len, buf_len - len, "remove_msdu = %u\n", + htt_stats_buf->remove_msdu); + len += scnprintf(buf + len, buf_len - len, "remove_mpdu = %u\n", + htt_stats_buf->remove_mpdu); + len += scnprintf(buf + len, buf_len - len, "remove_msdu_ttl = %u\n", + htt_stats_buf->remove_msdu_ttl); + len += scnprintf(buf + len, buf_len - len, "send_bar = %u\n", + htt_stats_buf->send_bar); + len += scnprintf(buf + len, buf_len - len, "bar_sync = %u\n", + htt_stats_buf->bar_sync); + len += scnprintf(buf + len, buf_len - len, "notify_mpdu = %u\n", + htt_stats_buf->notify_mpdu); + len += scnprintf(buf + len, buf_len - len, "sync_cmd = %u\n", + htt_stats_buf->sync_cmd); + len += scnprintf(buf + len, buf_len - len, "write_cmd = %u\n", + htt_stats_buf->write_cmd); + len += scnprintf(buf + len, buf_len - len, "hwsch_trigger = %u\n", + htt_stats_buf->hwsch_trigger); + len += scnprintf(buf + len, buf_len - len, "ack_tlv_proc = %u\n", + htt_stats_buf->ack_tlv_proc); + len += scnprintf(buf + len, buf_len - len, "gen_mpdu_cmd = %u\n", + htt_stats_buf->gen_mpdu_cmd); + len += scnprintf(buf + len, buf_len - len, "gen_list_cmd = %u\n", + htt_stats_buf->gen_list_cmd); + len += scnprintf(buf + len, buf_len - len, "remove_mpdu_cmd = %u\n", + htt_stats_buf->remove_mpdu_cmd); + len += scnprintf(buf + len, buf_len - len, "remove_mpdu_tried_cmd = %u\n", + htt_stats_buf->remove_mpdu_tried_cmd); + len += scnprintf(buf + len, buf_len - len, "mpdu_queue_stats_cmd = %u\n", + htt_stats_buf->mpdu_queue_stats_cmd); + len += scnprintf(buf + len, buf_len - len, "mpdu_head_info_cmd = %u\n", + htt_stats_buf->mpdu_head_info_cmd); + len += scnprintf(buf + len, buf_len - len, "msdu_flow_stats_cmd = %u\n", + htt_stats_buf->msdu_flow_stats_cmd); + len += scnprintf(buf + len, buf_len - len, "remove_msdu_cmd = %u\n", + htt_stats_buf->remove_msdu_cmd); + len += scnprintf(buf + len, buf_len - len, "remove_msdu_ttl_cmd = %u\n", + htt_stats_buf->remove_msdu_ttl_cmd); + len += scnprintf(buf + len, buf_len - len, "flush_cache_cmd = %u\n", + htt_stats_buf->flush_cache_cmd); + len += scnprintf(buf + len, buf_len - len, "update_mpduq_cmd = %u\n", + htt_stats_buf->update_mpduq_cmd); + len += scnprintf(buf + len, buf_len - len, "enqueue = %u\n", + htt_stats_buf->enqueue); + len += scnprintf(buf + len, buf_len - len, "enqueue_notify = %u\n", + htt_stats_buf->enqueue_notify); + len += scnprintf(buf + len, buf_len - len, "notify_mpdu_at_head = %u\n", + htt_stats_buf->notify_mpdu_at_head); + len += scnprintf(buf + len, buf_len - len, "notify_mpdu_state_valid = %u\n", + htt_stats_buf->notify_mpdu_state_valid); + len += scnprintf(buf + len, buf_len - len, "sched_udp_notify1 = %u\n", + htt_stats_buf->sched_udp_notify1); + len += scnprintf(buf + len, buf_len - len, "sched_udp_notify2 = %u\n", + htt_stats_buf->sched_udp_notify2); + len += scnprintf(buf + len, buf_len - len, "sched_nonudp_notify1 = %u\n", + htt_stats_buf->sched_nonudp_notify1); + len += scnprintf(buf + len, buf_len - len, "sched_nonudp_notify2 = %u\n", + htt_stats_buf->sched_nonudp_notify2); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_tqm_cmn_stats_tlv(const void *tag_buf, u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tqm_cmn_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TQM_CMN_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "max_cmdq_id = %u\n", + htt_stats_buf->max_cmdq_id); + len += scnprintf(buf + len, buf_len - len, "list_mpdu_cnt_hist_intvl = %u\n", + htt_stats_buf->list_mpdu_cnt_hist_intvl); + len += scnprintf(buf + len, buf_len - len, "add_msdu = %u\n", + htt_stats_buf->add_msdu); + len += scnprintf(buf + len, buf_len - len, "q_empty = %u\n", + htt_stats_buf->q_empty); + len += scnprintf(buf + len, buf_len - len, "q_not_empty = %u\n", + htt_stats_buf->q_not_empty); + len += scnprintf(buf + len, buf_len - len, "drop_notification = %u\n", + htt_stats_buf->drop_notification); + len += scnprintf(buf + len, buf_len - len, "desc_threshold = %u\n", + htt_stats_buf->desc_threshold); + len += scnprintf(buf + len, buf_len - len, "hwsch_tqm_invalid_status = %u\n", + htt_stats_buf->hwsch_tqm_invalid_status); + len += scnprintf(buf + len, buf_len - len, "missed_tqm_gen_mpdus = %u\n", + htt_stats_buf->missed_tqm_gen_mpdus); + + if (tag_len > (offsetof(struct htt_tx_tqm_cmn_stats_tlv, tqm_active_tids) - + offsetof(struct htt_tx_tqm_cmn_stats_tlv, mac_id__word))) { + len += scnprintf(buf + len, buf_len - len, "active_tqm_tids = %u\n", + htt_stats_buf->tqm_active_tids); + len += scnprintf(buf + len, buf_len - len, "inactive_tqm_tids = %u\n", + htt_stats_buf->tqm_inactive_tids); + len += scnprintf(buf + len, buf_len - len, + "tqm_active_msduq_flows = %u\n", + htt_stats_buf->tqm_active_msduq_flows); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_unavailable_error_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_stats_error_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_ERROR_STATS_TLV:"); + len += scnprintf(buf + len, buf_len - len, + "No stats to print for current request: %d", + htt_stats_buf->htt_stats_type); + + stats_req->buf_len = len; +} + +static inline void +htt_print_unsupported_error_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_stats_error_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_ERROR_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "Unsupported HTT stats type: %d\n", + htt_stats_buf->htt_stats_type); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_tqm_error_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tqm_error_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TQM_ERROR_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "q_empty_failure = %u\n", + htt_stats_buf->q_empty_failure); + len += scnprintf(buf + len, buf_len - len, "q_not_empty_failure = %u\n", + htt_stats_buf->q_not_empty_failure); + len += scnprintf(buf + len, buf_len - len, "add_msdu_failure = %u\n", + htt_stats_buf->add_msdu_failure); + len += scnprintf(buf + len, buf_len - len, "TQM_ERROR_RESET_STATS:\n"); + len += scnprintf(buf + len, buf_len - len, "tqm_cache_ctl_err = %u\n", + htt_stats_buf->tqm_cache_ctl_err); + len += scnprintf(buf + len, buf_len - len, "tqm_soft_reset = %u\n", + htt_stats_buf->tqm_soft_reset); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_total_num_in_use_link_descs = %u\n", + htt_stats_buf->tqm_reset_total_num_in_use_link_descs); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_worst_case_num_lost_link_descs = %u\n", + htt_stats_buf->tqm_reset_worst_case_num_lost_link_descs); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_worst_case_num_lost_host_tx_bufs_count = %u\n", + htt_stats_buf->tqm_reset_worst_case_num_lost_host_tx_bufs_count); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_num_in_use_link_descs_internal_tqm = %u\n", + htt_stats_buf->tqm_reset_num_in_use_link_descs_internal_tqm); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_num_in_use_link_descs_wbm_idle_link_ring = %u\n", + htt_stats_buf->tqm_reset_num_in_use_link_descs_wbm_idle_link_ring); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_time_to_tqm_hang_delta_ms = %u\n", + htt_stats_buf->tqm_reset_time_to_tqm_hang_delta_ms); + len += scnprintf(buf + len, buf_len - len, "tqm_reset_recovery_time_ms = %u\n", + htt_stats_buf->tqm_reset_recovery_time_ms); + len += scnprintf(buf + len, buf_len - len, "tqm_reset_num_peers_hdl = %u\n", + htt_stats_buf->tqm_reset_num_peers_hdl); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_cumm_dirty_hw_mpduq_proc_cnt = %u\n", + htt_stats_buf->tqm_reset_cumm_dirty_hw_mpduq_proc_cnt); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_cumm_dirty_hw_msduq_proc = %u\n", + htt_stats_buf->tqm_reset_cumm_dirty_hw_msduq_proc); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_flush_cache_cmd_su_cnt = %u\n", + htt_stats_buf->tqm_reset_flush_cache_cmd_su_cnt); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_flush_cache_cmd_other_cnt = %u\n", + htt_stats_buf->tqm_reset_flush_cache_cmd_other_cnt); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_flush_cache_cmd_trig_type = %u\n", + htt_stats_buf->tqm_reset_flush_cache_cmd_trig_type); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_flush_cache_cmd_trig_cfg = %u\n", + htt_stats_buf->tqm_reset_flush_cache_cmd_trig_cfg); + len += scnprintf(buf + len, buf_len - len, + "tqm_reset_flush_cache_cmd_skip_cmd_status_null = %u\n", + htt_stats_buf->tqm_reset_flush_cache_cmd_skip_cmd_status_null); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_tqm_cmdq_status_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_tqm_cmdq_status_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__cmdq_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_TQM_CMDQ_STATUS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_TX_TQM_CMDQ_STATUS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "cmdq_id = %u\n\n", + u32_get_bits(mac_id_word, HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID)); + len += scnprintf(buf + len, buf_len - len, "sync_cmd = %u\n", + htt_stats_buf->sync_cmd); + len += scnprintf(buf + len, buf_len - len, "write_cmd = %u\n", + htt_stats_buf->write_cmd); + len += scnprintf(buf + len, buf_len - len, "gen_mpdu_cmd = %u\n", + htt_stats_buf->gen_mpdu_cmd); + len += scnprintf(buf + len, buf_len - len, "mpdu_queue_stats_cmd = %u\n", + htt_stats_buf->mpdu_queue_stats_cmd); + len += scnprintf(buf + len, buf_len - len, "mpdu_head_info_cmd = %u\n", + htt_stats_buf->mpdu_head_info_cmd); + len += scnprintf(buf + len, buf_len - len, "msdu_flow_stats_cmd = %u\n", + htt_stats_buf->msdu_flow_stats_cmd); + len += scnprintf(buf + len, buf_len - len, "remove_mpdu_cmd = %u\n", + htt_stats_buf->remove_mpdu_cmd); + len += scnprintf(buf + len, buf_len - len, "remove_msdu_cmd = %u\n", + htt_stats_buf->remove_msdu_cmd); + len += scnprintf(buf + len, buf_len - len, "flush_cache_cmd = %u\n", + htt_stats_buf->flush_cache_cmd); + len += scnprintf(buf + len, buf_len - len, "update_mpduq_cmd = %u\n", + htt_stats_buf->update_mpduq_cmd); + len += scnprintf(buf + len, buf_len - len, "update_msduq_cmd = %u\n", + htt_stats_buf->update_msduq_cmd); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_eapol_packets_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_eapol_packets_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_DE_EAPOL_PACKETS_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "m1_packets = %u\n", + htt_stats_buf->m1_packets); + len += scnprintf(buf + len, buf_len - len, "m2_packets = %u\n", + htt_stats_buf->m2_packets); + len += scnprintf(buf + len, buf_len - len, "m3_packets = %u\n", + htt_stats_buf->m3_packets); + len += scnprintf(buf + len, buf_len - len, "m4_packets = %u\n", + htt_stats_buf->m4_packets); + len += scnprintf(buf + len, buf_len - len, "g1_packets = %u\n", + htt_stats_buf->g1_packets); + len += scnprintf(buf + len, buf_len - len, "g2_packets = %u\n", + htt_stats_buf->g2_packets); + len += scnprintf(buf + len, buf_len - len, "rc4_packets = %u\n", + htt_stats_buf->rc4_packets); + len += scnprintf(buf + len, buf_len - len, "eap_packets = %u\n", + htt_stats_buf->eap_packets); + len += scnprintf(buf + len, buf_len - len, "eapol_start_packets = %u\n", + htt_stats_buf->eapol_start_packets); + len += scnprintf(buf + len, buf_len - len, "eapol_logoff_packets = %u\n", + htt_stats_buf->eapol_logoff_packets); + len += scnprintf(buf + len, buf_len - len, "eapol_encap_asf_packets = %u\n", + htt_stats_buf->eapol_encap_asf_packets); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_classify_failed_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_classify_failed_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_DE_CLASSIFY_FAILED_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "ap_bss_peer_not_found = %u\n", + htt_stats_buf->ap_bss_peer_not_found); + len += scnprintf(buf + len, buf_len - len, "ap_bcast_mcast_no_peer = %u\n", + htt_stats_buf->ap_bcast_mcast_no_peer); + len += scnprintf(buf + len, buf_len - len, "sta_delete_in_progress = %u\n", + htt_stats_buf->sta_delete_in_progress); + len += scnprintf(buf + len, buf_len - len, "ibss_no_bss_peer = %u\n", + htt_stats_buf->ibss_no_bss_peer); + len += scnprintf(buf + len, buf_len - len, "invalid_vdev_type = %u\n", + htt_stats_buf->invalid_vdev_type); + len += scnprintf(buf + len, buf_len - len, "invalid_ast_peer_entry = %u\n", + htt_stats_buf->invalid_ast_peer_entry); + len += scnprintf(buf + len, buf_len - len, "peer_entry_invalid = %u\n", + htt_stats_buf->peer_entry_invalid); + len += scnprintf(buf + len, buf_len - len, "ethertype_not_ip = %u\n", + htt_stats_buf->ethertype_not_ip); + len += scnprintf(buf + len, buf_len - len, "eapol_lookup_failed = %u\n", + htt_stats_buf->eapol_lookup_failed); + len += scnprintf(buf + len, buf_len - len, "qpeer_not_allow_data = %u\n", + htt_stats_buf->qpeer_not_allow_data); + len += scnprintf(buf + len, buf_len - len, "fse_tid_override = %u\n", + htt_stats_buf->fse_tid_override); + len += scnprintf(buf + len, buf_len - len, "ipv6_jumbogram_zero_length = %u\n", + htt_stats_buf->ipv6_jumbogram_zero_length); + len += scnprintf(buf + len, buf_len - len, "qos_to_non_qos_in_prog = %u\n", + htt_stats_buf->qos_to_non_qos_in_prog); + len += scnprintf(buf + len, buf_len - len, "ap_bcast_mcast_eapol = %u\n", + htt_stats_buf->ap_bcast_mcast_eapol); + len += scnprintf(buf + len, buf_len - len, "unicast_on_ap_bss_peer = %u\n", + htt_stats_buf->unicast_on_ap_bss_peer); + len += scnprintf(buf + len, buf_len - len, "ap_vdev_invalid = %u\n", + htt_stats_buf->ap_vdev_invalid); + len += scnprintf(buf + len, buf_len - len, "incomplete_llc = %u\n", + htt_stats_buf->incomplete_llc); + len += scnprintf(buf + len, buf_len - len, "eapol_duplicate_m3 = %u\n", + htt_stats_buf->eapol_duplicate_m3); + len += scnprintf(buf + len, buf_len - len, "eapol_duplicate_m4 = %u\n", + htt_stats_buf->eapol_duplicate_m4); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_classify_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_classify_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_DE_CLASSIFY_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "arp_packets = %u\n", + htt_stats_buf->arp_packets); + len += scnprintf(buf + len, buf_len - len, "igmp_packets = %u\n", + htt_stats_buf->igmp_packets); + len += scnprintf(buf + len, buf_len - len, "dhcp_packets = %u\n", + htt_stats_buf->dhcp_packets); + len += scnprintf(buf + len, buf_len - len, "host_inspected = %u\n", + htt_stats_buf->host_inspected); + len += scnprintf(buf + len, buf_len - len, "htt_included = %u\n", + htt_stats_buf->htt_included); + len += scnprintf(buf + len, buf_len - len, "htt_valid_mcs = %u\n", + htt_stats_buf->htt_valid_mcs); + len += scnprintf(buf + len, buf_len - len, "htt_valid_nss = %u\n", + htt_stats_buf->htt_valid_nss); + len += scnprintf(buf + len, buf_len - len, "htt_valid_preamble_type = %u\n", + htt_stats_buf->htt_valid_preamble_type); + len += scnprintf(buf + len, buf_len - len, "htt_valid_chainmask = %u\n", + htt_stats_buf->htt_valid_chainmask); + len += scnprintf(buf + len, buf_len - len, "htt_valid_guard_interval = %u\n", + htt_stats_buf->htt_valid_guard_interval); + len += scnprintf(buf + len, buf_len - len, "htt_valid_retries = %u\n", + htt_stats_buf->htt_valid_retries); + len += scnprintf(buf + len, buf_len - len, "htt_valid_bw_info = %u\n", + htt_stats_buf->htt_valid_bw_info); + len += scnprintf(buf + len, buf_len - len, "htt_valid_power = %u\n", + htt_stats_buf->htt_valid_power); + len += scnprintf(buf + len, buf_len - len, "htt_valid_key_flags = 0x%x\n", + htt_stats_buf->htt_valid_key_flags); + len += scnprintf(buf + len, buf_len - len, "htt_valid_no_encryption = %u\n", + htt_stats_buf->htt_valid_no_encryption); + len += scnprintf(buf + len, buf_len - len, "fse_entry_count = %u\n", + htt_stats_buf->fse_entry_count); + len += scnprintf(buf + len, buf_len - len, "fse_priority_be = %u\n", + htt_stats_buf->fse_priority_be); + len += scnprintf(buf + len, buf_len - len, "fse_priority_high = %u\n", + htt_stats_buf->fse_priority_high); + len += scnprintf(buf + len, buf_len - len, "fse_priority_low = %u\n", + htt_stats_buf->fse_priority_low); + len += scnprintf(buf + len, buf_len - len, "fse_traffic_ptrn_be = %u\n", + htt_stats_buf->fse_traffic_ptrn_be); + len += scnprintf(buf + len, buf_len - len, "fse_traffic_ptrn_over_sub = %u\n", + htt_stats_buf->fse_traffic_ptrn_over_sub); + len += scnprintf(buf + len, buf_len - len, "fse_traffic_ptrn_bursty = %u\n", + htt_stats_buf->fse_traffic_ptrn_bursty); + len += scnprintf(buf + len, buf_len - len, "fse_traffic_ptrn_interactive = %u\n", + htt_stats_buf->fse_traffic_ptrn_interactive); + len += scnprintf(buf + len, buf_len - len, "fse_traffic_ptrn_periodic = %u\n", + htt_stats_buf->fse_traffic_ptrn_periodic); + len += scnprintf(buf + len, buf_len - len, "fse_hwqueue_alloc = %u\n", + htt_stats_buf->fse_hwqueue_alloc); + len += scnprintf(buf + len, buf_len - len, "fse_hwqueue_created = %u\n", + htt_stats_buf->fse_hwqueue_created); + len += scnprintf(buf + len, buf_len - len, "fse_hwqueue_send_to_host = %u\n", + htt_stats_buf->fse_hwqueue_send_to_host); + len += scnprintf(buf + len, buf_len - len, "mcast_entry = %u\n", + htt_stats_buf->mcast_entry); + len += scnprintf(buf + len, buf_len - len, "bcast_entry = %u\n", + htt_stats_buf->bcast_entry); + len += scnprintf(buf + len, buf_len - len, "htt_update_peer_cache = %u\n", + htt_stats_buf->htt_update_peer_cache); + len += scnprintf(buf + len, buf_len - len, "htt_learning_frame = %u\n", + htt_stats_buf->htt_learning_frame); + len += scnprintf(buf + len, buf_len - len, "fse_invalid_peer = %u\n", + htt_stats_buf->fse_invalid_peer); + len += scnprintf(buf + len, buf_len - len, "mec_notify = %u\n", + htt_stats_buf->mec_notify); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_classify_status_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_classify_status_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_DE_CLASSIFY_STATUS_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "eok = %u\n", + htt_stats_buf->eok); + len += scnprintf(buf + len, buf_len - len, "classify_done = %u\n", + htt_stats_buf->classify_done); + len += scnprintf(buf + len, buf_len - len, "lookup_failed = %u\n", + htt_stats_buf->lookup_failed); + len += scnprintf(buf + len, buf_len - len, "send_host_dhcp = %u\n", + htt_stats_buf->send_host_dhcp); + len += scnprintf(buf + len, buf_len - len, "send_host_mcast = %u\n", + htt_stats_buf->send_host_mcast); + len += scnprintf(buf + len, buf_len - len, "send_host_unknown_dest = %u\n", + htt_stats_buf->send_host_unknown_dest); + len += scnprintf(buf + len, buf_len - len, "send_host = %u\n", + htt_stats_buf->send_host); + len += scnprintf(buf + len, buf_len - len, "status_invalid = %u\n", + htt_stats_buf->status_invalid); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_enqueue_packets_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_enqueue_packets_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_DE_ENQUEUE_PACKETS_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "enqueued_pkts = %u\n", + htt_stats_buf->enqueued_pkts); + len += scnprintf(buf + len, buf_len - len, "to_tqm = %u\n", + htt_stats_buf->to_tqm); + len += scnprintf(buf + len, buf_len - len, "to_tqm_bypass = %u\n", + htt_stats_buf->to_tqm_bypass); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_enqueue_discard_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_enqueue_discard_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_DE_ENQUEUE_DISCARD_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "discarded_pkts = %u\n", + htt_stats_buf->discarded_pkts); + len += scnprintf(buf + len, buf_len - len, "local_frames = %u\n", + htt_stats_buf->local_frames); + len += scnprintf(buf + len, buf_len - len, "is_ext_msdu = %u\n", + htt_stats_buf->is_ext_msdu); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_de_compl_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_compl_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_DE_COMPL_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "tcl_dummy_frame = %u\n", + htt_stats_buf->tcl_dummy_frame); + len += scnprintf(buf + len, buf_len - len, "tqm_dummy_frame = %u\n", + htt_stats_buf->tqm_dummy_frame); + len += scnprintf(buf + len, buf_len - len, "tqm_notify_frame = %u\n", + htt_stats_buf->tqm_notify_frame); + len += scnprintf(buf + len, buf_len - len, "fw2wbm_enq = %u\n", + htt_stats_buf->fw2wbm_enq); + len += scnprintf(buf + len, buf_len - len, "tqm_bypass_frame = %u\n", + htt_stats_buf->tqm_bypass_frame); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_fw2wbm_ring_full_hist_tlv(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_fw2wbm_ring_full_hist_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elements = tag_len >> 2; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_DE_FW2WBM_RING_FULL_HIST_TLV\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->fw2wbm_ring_full_hist, + "fw2wbm_ring_full_hist", num_elements, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_de_cmn_stats_tlv(const void *tag_buf, struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_de_cmn_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_DE_CMN_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "tcl2fw_entry_count = %u\n", + htt_stats_buf->tcl2fw_entry_count); + len += scnprintf(buf + len, buf_len - len, "not_to_fw = %u\n", + htt_stats_buf->not_to_fw); + len += scnprintf(buf + len, buf_len - len, "invalid_pdev_vdev_peer = %u\n", + htt_stats_buf->invalid_pdev_vdev_peer); + len += scnprintf(buf + len, buf_len - len, "tcl_res_invalid_addrx = %u\n", + htt_stats_buf->tcl_res_invalid_addrx); + len += scnprintf(buf + len, buf_len - len, "wbm2fw_entry_count = %u\n", + htt_stats_buf->wbm2fw_entry_count); + len += scnprintf(buf + len, buf_len - len, "invalid_pdev = %u\n", + htt_stats_buf->invalid_pdev); + len += scnprintf(buf + len, buf_len - len, "tcl_res_addrx_timeout = %u\n", + htt_stats_buf->tcl_res_addrx_timeout); + len += scnprintf(buf + len, buf_len - len, "invalid_vdev = %u\n", + htt_stats_buf->invalid_vdev); + len += scnprintf(buf + len, buf_len - len, "invalid_tcl_exp_frame_desc = %u\n", + htt_stats_buf->invalid_tcl_exp_frame_desc); + + stats_req->buf_len = len; +} + +static inline void htt_print_ring_if_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_ring_if_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 tail_idx = __le32_to_cpu(htt_stats_buf->num_elems__prefetch_tail_idx); + u32 head_idx = __le32_to_cpu(htt_stats_buf->head_idx__tail_idx); + u32 shadow_idx = __le32_to_cpu(htt_stats_buf->shadow_head_idx__shadow_tail_idx); + u32 thresh = __le32_to_cpu(htt_stats_buf->lwm_thresh__hwm_thresh); + + len += scnprintf(buf + len, buf_len - len, "HTT_RING_IF_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "base_addr = %u\n", + htt_stats_buf->base_addr); + len += scnprintf(buf + len, buf_len - len, "elem_size = %u\n", + htt_stats_buf->elem_size); + len += scnprintf(buf + len, buf_len - len, "num_elems = %lu\n", + (unsigned long)u32_get_bits(tail_idx, + HTT_RING_IF_STATS_NUM_ELEMS)); + len += scnprintf(buf + len, buf_len - len, "prefetch_tail_idx = %lu\n", + (unsigned long)u32_get_bits(tail_idx, + HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX)); + len += scnprintf(buf + len, buf_len - len, "head_idx = %lu\n", + (unsigned long)u32_get_bits(head_idx, + HTT_RING_IF_STATS_HEAD_IDX)); + len += scnprintf(buf + len, buf_len - len, "tail_idx = %lu\n", + (unsigned long)u32_get_bits(head_idx, + HTT_RING_IF_STATS_TAIL_IDX)); + len += scnprintf(buf + len, buf_len - len, "shadow_head_idx = %lu\n", + (unsigned long)u32_get_bits(shadow_idx, + HTT_RING_IF_STATS_SHADOW_HEAD_IDX)); + len += scnprintf(buf + len, buf_len - len, "shadow_tail_idx = %lu\n", + (unsigned long)u32_get_bits(shadow_idx, + HTT_RING_IF_STATS_SHADOW_TAIL_IDX)); + len += scnprintf(buf + len, buf_len - len, "num_tail_incr = %u\n", + htt_stats_buf->num_tail_incr); + len += scnprintf(buf + len, buf_len - len, "lwm_thresh = %lu\n", + (unsigned long)u32_get_bits(thresh, + HTT_RING_IF_STATS_LWM_THRESH)); + len += scnprintf(buf + len, buf_len - len, "hwm_thresh = %lu\n", + (unsigned long)u32_get_bits(thresh, + HTT_RING_IF_STATS_HWM_THRESH)); + len += scnprintf(buf + len, buf_len - len, "overrun_hit_count = %u\n", + htt_stats_buf->overrun_hit_count); + len += scnprintf(buf + len, buf_len - len, "underrun_hit_count = %u\n", + htt_stats_buf->underrun_hit_count); + len += scnprintf(buf + len, buf_len - len, "prod_blockwait_count = %u\n", + htt_stats_buf->prod_blockwait_count); + len += scnprintf(buf + len, buf_len - len, "cons_blockwait_count = %u\n", + htt_stats_buf->cons_blockwait_count); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->low_wm_hit_count, + "low_wm_hit_count", HTT_STATS_LOW_WM_BINS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->high_wm_hit_count, + "high_wm_hit_count", HTT_STATS_HIGH_WM_BINS, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_ring_if_cmn_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_ring_if_cmn_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_RING_IF_CMN_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "num_records = %u\n", + htt_stats_buf->num_records); + + stats_req->buf_len = len; +} + +static inline void htt_print_sfm_client_user_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sfm_client_user_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = tag_len >> 2; + + len += scnprintf(buf + len, buf_len - len, "HTT_SFM_CLIENT_USER_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->dwords_used_by_user_n, + "dwords_used_by_user_n", num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_sfm_client_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sfm_client_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_SFM_CLIENT_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "client_id = %u\n", + htt_stats_buf->client_id); + len += scnprintf(buf + len, buf_len - len, "buf_min = %u\n", + htt_stats_buf->buf_min); + len += scnprintf(buf + len, buf_len - len, "buf_max = %u\n", + htt_stats_buf->buf_max); + len += scnprintf(buf + len, buf_len - len, "buf_busy = %u\n", + htt_stats_buf->buf_busy); + len += scnprintf(buf + len, buf_len - len, "buf_alloc = %u\n", + htt_stats_buf->buf_alloc); + len += scnprintf(buf + len, buf_len - len, "buf_avail = %u\n", + htt_stats_buf->buf_avail); + len += scnprintf(buf + len, buf_len - len, "num_users = %u\n", + htt_stats_buf->num_users); + + stats_req->buf_len = len; +} + +static inline void htt_print_sfm_cmn_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sfm_cmn_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_SFM_CMN_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "buf_total = %u\n", + htt_stats_buf->buf_total); + len += scnprintf(buf + len, buf_len - len, "mem_empty = %u\n", + htt_stats_buf->mem_empty); + len += scnprintf(buf + len, buf_len - len, "deallocate_bufs = %u\n", + htt_stats_buf->deallocate_bufs); + len += scnprintf(buf + len, buf_len - len, "num_records = %u\n", + htt_stats_buf->num_records); + + stats_req->buf_len = len; +} + +static inline void htt_print_sring_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sring_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__ring_id__arena__ep); + u32 avail_words = __le32_to_cpu(htt_stats_buf->num_avail_words__num_valid_words); + u32 head_tail_ptr = __le32_to_cpu(htt_stats_buf->head_ptr__tail_ptr); + u32 sring_stat = __le32_to_cpu(htt_stats_buf->consumer_empty__producer_full); + u32 tail_ptr = __le32_to_cpu(htt_stats_buf->prefetch_count__internal_tail_ptr); + + len += scnprintf(buf + len, buf_len - len, "HTT_SRING_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_SRING_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "ring_id = %u\n", + u32_get_bits(mac_id_word, HTT_SRING_STATS_RING_ID)); + len += scnprintf(buf + len, buf_len - len, "arena = %u\n", + u32_get_bits(mac_id_word, HTT_SRING_STATS_ARENA)); + len += scnprintf(buf + len, buf_len - len, "ep = %u\n", + u32_get_bits(mac_id_word, HTT_SRING_STATS_EP)); + len += scnprintf(buf + len, buf_len - len, "base_addr_lsb = 0x%x\n", + htt_stats_buf->base_addr_lsb); + len += scnprintf(buf + len, buf_len - len, "base_addr_msb = 0x%x\n", + htt_stats_buf->base_addr_msb); + len += scnprintf(buf + len, buf_len - len, "ring_size = %u\n", + htt_stats_buf->ring_size); + len += scnprintf(buf + len, buf_len - len, "elem_size = %u\n", + htt_stats_buf->elem_size); + len += scnprintf(buf + len, buf_len - len, "num_avail_words = %u\n", + u32_get_bits(avail_words, HTT_SRING_STATS_NUM_AVAIL_WORDS)); + len += scnprintf(buf + len, buf_len - len, "num_valid_words = %u\n", + u32_get_bits(avail_words, HTT_SRING_STATS_NUM_VALID_WORDS)); + len += scnprintf(buf + len, buf_len - len, "head_ptr = %u\n", + u32_get_bits(head_tail_ptr, HTT_SRING_STATS_HEAD_PTR)); + len += scnprintf(buf + len, buf_len - len, "tail_ptr = %u\n", + u32_get_bits(head_tail_ptr, HTT_SRING_STATS_TAIL_PTR)); + len += scnprintf(buf + len, buf_len - len, "consumer_empty = %u\n", + u32_get_bits(sring_stat, HTT_SRING_STATS_CONSUMER_EMPTY)); + len += scnprintf(buf + len, buf_len - len, "producer_full = %u\n", + u32_get_bits(head_tail_ptr, HTT_SRING_STATS_PRODUCER_FULL)); + len += scnprintf(buf + len, buf_len - len, "prefetch_count = %u\n", + u32_get_bits(tail_ptr, HTT_SRING_STATS_PREFETCH_COUNT)); + len += scnprintf(buf + len, buf_len - len, "internal_tail_ptr = %u\n\n", + u32_get_bits(tail_ptr, HTT_SRING_STATS_INTERNAL_TAIL_PTR)); + + stats_req->buf_len = len; +} + +static inline void htt_print_sring_cmn_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sring_cmn_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_SRING_CMN_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "num_records = %u\n", + htt_stats_buf->num_records); + + stats_req->buf_len = len; +} + +static inline void htt_print_tx_pdev_rate_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_rate_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 j; + char *tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS] = {NULL}; + u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS + 1] = { 0 }; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + for (j = 0; j < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; j++) { + tx_gi[j] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!tx_gi[j]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_RATE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "tx_ldpc = %u\n", + htt_stats_buf->tx_ldpc); + len += scnprintf(buf + len, buf_len - len, "ac_mu_mimo_tx_ldpc = %u\n", + htt_stats_buf->ac_mu_mimo_tx_ldpc); + len += scnprintf(buf + len, buf_len - len, "ax_mu_mimo_tx_ldpc = %u\n", + htt_stats_buf->ax_mu_mimo_tx_ldpc); + len += scnprintf(buf + len, buf_len - len, "ofdma_tx_ldpc = %u\n", + htt_stats_buf->ofdma_tx_ldpc); + len += scnprintf(buf + len, buf_len - len, "rts_cnt = %u\n", + htt_stats_buf->rts_cnt); + len += scnprintf(buf + len, buf_len - len, "rts_success = %u\n", + htt_stats_buf->rts_success); + len += scnprintf(buf + len, buf_len - len, "ack_rssi = %u\n", + htt_stats_buf->ack_rssi); + + len += scnprintf(buf + len, buf_len - len, + "Legacy CCK Rates: 1 Mbps: %u, 2 Mbps: %u, 5.5 Mbps: %u, 11 Mbps: %u\n", + htt_stats_buf->tx_legacy_cck_rate[0], + htt_stats_buf->tx_legacy_cck_rate[1], + htt_stats_buf->tx_legacy_cck_rate[2], + htt_stats_buf->tx_legacy_cck_rate[3]); + + len += scnprintf(buf + len, buf_len - len, + "Legacy OFDM Rates: 6 Mbps: %u, 9 Mbps: %u, 12 Mbps: %u, 18 Mbps: %u\n" + " 24 Mbps: %u, 36 Mbps: %u, 48 Mbps: %u, 54 Mbps: %u\n", + htt_stats_buf->tx_legacy_ofdm_rate[0], + htt_stats_buf->tx_legacy_ofdm_rate[1], + htt_stats_buf->tx_legacy_ofdm_rate[2], + htt_stats_buf->tx_legacy_ofdm_rate[3], + htt_stats_buf->tx_legacy_ofdm_rate[4], + htt_stats_buf->tx_legacy_ofdm_rate[5], + htt_stats_buf->tx_legacy_ofdm_rate[6], + htt_stats_buf->tx_legacy_ofdm_rate[7]); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_mcs, "tx_mcs", + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_mcs_ext, "tx_mcs_ext", + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_tx_mcs, + "ac_mu_mimo_tx_mcs", HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_mcs_ext, + "ac_mu_mimo_tx_mcs_ext", + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_mcs, + "ax_mu_mimo_tx_mcs", HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_mcs_ext, + "ax_mu_mimo_tx_mcs_ext", + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_tx_mcs, "ofdma_tx_mcs", + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_tx_mcs_ext, + "ofdma_tx_mcs_ext", + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_nss, "tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_tx_nss, + "ac_mu_mimo_tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_nss, + "ax_mu_mimo_tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_tx_nss, "ofdma_tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_BW_COUNTERS; j++) { + tx_bw[j] = htt_stats_buf->tx_bw[j]; + } + tx_bw[j] = htt_stats_buf->tx_bw_320mhz; + PRINT_ARRAY_TO_BUF(buf, len, tx_bw, "tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS + 1, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_tx_bw, + "ac_mu_mimo_tx_bw", HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_bw, + "ax_mu_mimo_tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_tx_bw, "ofdma_tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_stbc, "tx_stbc", + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_pream, "tx_pream", + HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES, "\n"); + + len += scnprintf(buf + len, buf_len - len, "HE LTF: 1x: %u, 2x: %u, 4x: %u\n", + htt_stats_buf->tx_he_ltf[1], + htt_stats_buf->tx_he_ltf[2], + htt_stats_buf->tx_he_ltf[3]); + + /* SU GI Stats */ + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "tx_gi[%u] = %s\n", + j, tx_gi[j]); + len += scnprintf(buf + len, buf_len - len, " -2:%u,-1:%u,", + htt_stats_buf->tx_gi_ext_2[j][0], + htt_stats_buf->tx_gi_ext_2[j][1]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_gi[j], NULL, + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_gi_ext[j], NULL, + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + + } + + /* AC MU-MIMO GI Stats */ + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, + "ac_mu_mimo_tx_gi[%u] = %s\n", + j, tx_gi[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ac_mu_mimo_tx_gi[j], + NULL, HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_gi_ext[j], + NULL, HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + } + + /* AX MU-MIMO GI Stats */ + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, + "ax_mu_mimo_tx_gi[%u] = %s\n", + j, tx_gi[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_gi[j], + NULL, HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ax_mu_mimo_tx_gi_ext[j], + NULL, HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + } + + /* DL OFDMA GI Stats */ + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "ofdma_tx_gi[%u] = %s\n", + j, tx_gi[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_tx_gi[j], NULL, + HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_tx_gi_ext[j], + NULL, HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_tx_ru_size, + "ofdma_tx_ru_size", + HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_dcm, "tx_dcm", + HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->tx_su_punctured_mode, + "tx_su_punctured_mode", + HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS, "\n"); + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "half_tx_bw = " :"quarter_tx_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_tx_bw[j], NULL, + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "half_ac_mu_mimo_tx_bw = " :"quarter_ac_mu_mimo_tx_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_ac_mu_mimo_tx_bw[j], NULL, + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "half_ax_mu_mimo_tx_bw = " :"quarter_ax_mu_mimo_tx_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_ax_mu_mimo_tx_bw[j], NULL, + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "half_ofdma_tx_bw" :"quarter_ofdma_tx_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_ax_mu_ofdma_tx_bw[j], NULL, + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ofdma_he_sig_b_mcs, + "ofdma_he_sig_b_mcs", + HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->trigger_type_11ax, + "11ax_trigger_type", + HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->trigger_type_11be, + "11be_trigger_type", + HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES, "\n"); + + len += scnprintf(buf + len, buf_len - len, + "ax_su_embedded_trigger_data_ppdu_cnt = %u\n", + htt_stats_buf->ax_su_embedded_trigger_data_ppdu); + + len += scnprintf(buf + len, buf_len - len, + "ax_su_embedded_trigger_data_ppdu_err_cnt = %u\n", + htt_stats_buf->ax_su_embedded_trigger_data_ppdu_err); + + stats_req->buf_len = len; +fail: + for (j = 0; j < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; j++) + kfree(tx_gi[j]); +} + +static inline void htt_print_rx_pdev_rate_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_rate_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 i, j; + char *rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] = {NULL}; + char *rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] = {NULL}; + char *rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] = {NULL}; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + rssi_chain[j] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!rssi_chain[j]) + goto fail; + } + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + rx_gi[j] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!rx_gi[j]) + goto fail; + } + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + rx_pilot_evm_db[j] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!rx_pilot_evm_db[j]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_PDEV_RATE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "nsts = %u\n", + htt_stats_buf->nsts); + len += scnprintf(buf + len, buf_len - len, "rx_ldpc = %u\n", + htt_stats_buf->rx_ldpc); + len += scnprintf(buf + len, buf_len - len, "rts_cnt = %u\n", + htt_stats_buf->rts_cnt); + len += scnprintf(buf + len, buf_len - len, "rssi_mgmt = %u\n", + htt_stats_buf->rssi_mgmt); + len += scnprintf(buf + len, buf_len - len, "rssi_data = %u\n", + htt_stats_buf->rssi_data); + len += scnprintf(buf + len, buf_len - len, "rssi_comb = %u\n", + htt_stats_buf->rssi_comb); + len += scnprintf(buf + len, buf_len - len, "rssi_in_dbm = %d\n", + htt_stats_buf->rssi_in_dbm); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_mcs, "rx_mcs", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_nss, "rx_nss", + HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_dcm, "rx_dcm", + HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_stbc, "rx_stbc", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_bw, "rx_bw", + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "rx_evm_nss_count = %u\n", + htt_stats_buf->nss_count); + + len += scnprintf(buf + len, buf_len - len, "rx_evm_pilot_count = %u\n", + htt_stats_buf->pilot_count); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "pilot_evm_db[%u] = ", j); + for (i = 0; i < HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS; i++) + len += scnprintf(buf + len, + buf_len - len, + " %u:%d,", + i, + htt_stats_buf->rx_pilot_evm_db[j][i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + len += scnprintf(buf + len, buf_len - len, + "pilot_evm_db_mean = "); + for (i = 0; i < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) + len += scnprintf(buf + len, + buf_len - len, + " %u:%d,", i, + htt_stats_buf->rx_pilot_evm_db_mean[i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "rssi_chain[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rssi_chain[j], NULL, + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + } + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, + "rx_gi[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_gi[j], NULL, + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_pream, "rx_pream", + HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES, "\n"); + + len += scnprintf(buf + len, buf_len - len, "rx_11ax_su_ext = %u\n", + htt_stats_buf->rx_11ax_su_ext); + len += scnprintf(buf + len, buf_len - len, "rx_11ac_mumimo = %u\n", + htt_stats_buf->rx_11ac_mumimo); + len += scnprintf(buf + len, buf_len - len, "rx_11ax_mumimo = %u\n", + htt_stats_buf->rx_11ax_mumimo); + len += scnprintf(buf + len, buf_len - len, "rx_11ax_ofdma = %u\n", + htt_stats_buf->rx_11ax_ofdma); + len += scnprintf(buf + len, buf_len - len, "txbf = %u\n", + htt_stats_buf->txbf); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_legacy_cck_rate, + "rx_legacy_cck_rate", + HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_legacy_ofdm_rate, + "rx_legacy_ofdm_rate", + HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "rx_active_dur_us_low = %u\n", + htt_stats_buf->rx_active_dur_us_low); + len += scnprintf(buf + len, buf_len - len, "rx_active_dur_us_high = %u\n", + htt_stats_buf->rx_active_dur_us_high); + len += scnprintf(buf + len, buf_len - len, "rx_11ax_ul_ofdma = %u\n", + htt_stats_buf->rx_11ax_ul_ofdma); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_rx_mcs, + "ul_ofdma_rx_mcs", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "ul_ofdma_rx_gi[%u] = %s\n", + j, rx_gi[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_rx_gi[j], NULL, + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_rx_nss, + "ul_ofdma_rx_nss", + HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_rx_bw, "ul_ofdma_rx_bw", + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "ul_ofdma_rx_stbc = %u\n", + htt_stats_buf->ul_ofdma_rx_stbc); + len += scnprintf(buf + len, buf_len - len, "ul_ofdma_rx_ldpc = %u\n", + htt_stats_buf->ul_ofdma_rx_ldpc); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_ulofdma_non_data_ppdu, + "rx_ulofdma_non_data_ppdu", + HTT_RX_PDEV_MAX_OFDMA_NUM_USER, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_ulofdma_data_ppdu, + "rx_ulofdma_data_ppdu", HTT_RX_PDEV_MAX_OFDMA_NUM_USER, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_ulofdma_mpdu_ok, + "rx_ulofdma_mpdu_ok", HTT_RX_PDEV_MAX_OFDMA_NUM_USER, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_ulofdma_mpdu_fail, + "rx_ulofdma_mpdu_fail", HTT_RX_PDEV_MAX_OFDMA_NUM_USER, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "rx_ul_fd_rssi: nss[%u] = ", j); + for (i = 0; i < HTT_RX_PDEV_MAX_OFDMA_NUM_USER; i++) + len += scnprintf(buf + len, + buf_len - len, + " %u:%d,", + i, htt_stats_buf->rx_ul_fd_rssi[j][i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + len += scnprintf(buf + len, buf_len - len, "per_chain_rssi_pkt_type = %#x\n", + htt_stats_buf->per_chain_rssi_pkt_type); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "rx_per_chain_rssi_in_dbm[%u] = ", j); + for (i = 0; i < HTT_RX_PDEV_STATS_NUM_BW_COUNTERS; i++) + len += scnprintf(buf + len, + buf_len - len, + " %u:%d,", + i, + htt_stats_buf->rx_per_chain_rssi_in_dbm[j][i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_11ax_dl_ofdma_mcs, + "rx_11ax_dl_ofdma_mcs", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_11ax_dl_ofdma_ru, + "rx_11ax_dl_ofdma_ru", + HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_ulofdma_non_data_nusers, + "rx_ulofdma_non_data_nusers", + HTT_RX_PDEV_MAX_OFDMA_NUM_USER, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_ulofdma_data_nusers, + "rx_ulofdma_data_nusers", + HTT_RX_PDEV_MAX_OFDMA_NUM_USER, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; + +fail: + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) + kfree(rssi_chain[j]); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) + kfree(rx_pilot_evm_db[j]); + + for (i = 0; i < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; i++) + kfree(rx_gi[i]); +} + +#define CHAIN_ARRAY_TO_BUF(out, buflen, arr, len) \ + do { \ + int index = 0; u8 i; \ + for (i = 0; i < len; i++) { \ + index += scnprintf((out + buflen) + index, \ + (ATH12K_HTT_STATS_BUF_SIZE - buflen) - index, \ + " %u:%d,", i, arr[i]); \ + } \ + buflen += index; \ + } while (0) + +static inline void htt_print_rx_pdev_rate_ext_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_rate_ext_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 j=0, i; + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_PDEV_RATE_EXT_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "rssi_mcast_in_dbm = %d\n", + htt_stats_buf->rssi_mcast_in_dbm); + len += scnprintf(buf + len, buf_len - len, "rssi_mgmt_in_dbm = %d\n", + htt_stats_buf->rssi_mgmt_in_dbm); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + for (i = 0; i < HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS; i++) + len += scnprintf(buf + len, + buf_len - len, + " %u:%d,", + i, + htt_stats_buf->rx_per_chain_rssi_ext_in_dbm[j][i]); + len += scnprintf(buf + len, buf_len - len, "\nrssi_chain_ext[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rssi_chain_ext[j], + NULL, HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "\nrx_per_chain_rssi_ext_in_dbm[%u] = ", j); + CHAIN_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rx_per_chain_rssi_ext_in_dbm[j], + HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_mcs_ext, + "rx_mcs_ext", HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_stbc_ext, + "rx_stbc_ext", HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "rx_gi_ext[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_gi_ext[j], + NULL, HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_rx_mcs_ext, + "ul_ofdma_rx_mcs_ext", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, + "ul_ofdma_rx_gi_ext[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_rx_gi_ext[j], + NULL, HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_11ax_su_txbf_mcs_ext, + "rx_11ax_su_txbf_mcs_ext", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_11ax_mu_txbf_mcs_ext, + "rx_11ax_mu_txbf_mcs_ext", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_11ax_dl_ofdma_mcs_ext, + "rx_11ax_dl_ofdma_mcs_ext", + HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_bw_ext, + "rx_bw_ext", + HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "half_rx_bw = " : + "quarter_rx_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->reduced_rx_bw[j], + NULL, HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_su_punctured_mode, + "rx_su_punctured_mode", + HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "rssi_chain_ext_2[%u] = ",j); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rssi_chain_ext_2[j], + NULL, HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, + "rx_per_chain_rssi_ext_2_in_dbm[%u] = ", j); + CHAIN_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rx_per_chain_rssi_ext_2_in_dbm[j], + HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS); + len += scnprintf(buf +len, buf_len -len, "\n"); + } + + stats_req->buf_len = len; +} + + +static inline void htt_print_rx_soc_fw_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_soc_fw_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_SOC_FW_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "fw_reo_ring_data_msdu = %u\n", + htt_stats_buf->fw_reo_ring_data_msdu); + len += scnprintf(buf + len, buf_len - len, "fw_to_host_data_msdu_bcmc = %u\n", + htt_stats_buf->fw_to_host_data_msdu_bcmc); + len += scnprintf(buf + len, buf_len - len, "fw_to_host_data_msdu_uc = %u\n", + htt_stats_buf->fw_to_host_data_msdu_uc); + len += scnprintf(buf + len, buf_len - len, + "ofld_remote_data_buf_recycle_cnt = %u\n", + htt_stats_buf->ofld_remote_data_buf_recycle_cnt); + len += scnprintf(buf + len, buf_len - len, + "ofld_remote_free_buf_indication_cnt = %u\n", + htt_stats_buf->ofld_remote_free_buf_indication_cnt); + len += scnprintf(buf + len, buf_len - len, + "ofld_buf_to_host_data_msdu_uc = %u\n", + htt_stats_buf->ofld_buf_to_host_data_msdu_uc); + len += scnprintf(buf + len, buf_len - len, + "reo_fw_ring_to_host_data_msdu_uc = %u\n", + htt_stats_buf->reo_fw_ring_to_host_data_msdu_uc); + len += scnprintf(buf + len, buf_len - len, "wbm_sw_ring_reap = %u\n", + htt_stats_buf->wbm_sw_ring_reap); + len += scnprintf(buf + len, buf_len - len, "wbm_forward_to_host_cnt = %u\n", + htt_stats_buf->wbm_forward_to_host_cnt); + len += scnprintf(buf + len, buf_len - len, "wbm_target_recycle_cnt = %u\n", + htt_stats_buf->wbm_target_recycle_cnt); + len += scnprintf(buf + len, buf_len - len, + "target_refill_ring_recycle_cnt = %u\n", + htt_stats_buf->target_refill_ring_recycle_cnt); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_soc_fw_refill_ring_empty_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_soc_fw_refill_ring_empty_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_RX_STATS_REFILL_MAX_RING); + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_SOC_FW_REFILL_RING_EMPTY_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->refill_ring_empty_cnt, + "refill_ring_empty_cnt", num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v *htt_stats_buf = + tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_RX_RXDMA_MAX_ERR_CODE); + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_SOC_FW_REFILL_RING_NUM_RXDMA_ERR_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rxdma_err, "rxdma_err", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_soc_fw_refill_ring_num_reo_err_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_RX_REO_MAX_ERR_CODE); + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_SOC_FW_REFILL_RING_NUM_REO_ERR_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reo_err, "reo_err", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_reo_debug_stats_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_reo_resource_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_REO_RESOURCE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "sample_id = %u\n", + htt_stats_buf->sample_id); + len += scnprintf(buf + len, buf_len - len, "total_max = %u\n", + htt_stats_buf->total_max); + len += scnprintf(buf + len, buf_len - len, "total_avg = %u\n", + htt_stats_buf->total_avg); + len += scnprintf(buf + len, buf_len - len, "total_sample = %u\n", + htt_stats_buf->total_sample); + len += scnprintf(buf + len, buf_len - len, "non_zeros_avg = %u\n", + htt_stats_buf->non_zeros_avg); + len += scnprintf(buf + len, buf_len - len, "non_zeros_sample = %u\n", + htt_stats_buf->non_zeros_sample); + len += scnprintf(buf + len, buf_len - len, "last_non_zeros_max = %u\n", + htt_stats_buf->last_non_zeros_max); + len += scnprintf(buf + len, buf_len - len, "last_non_zeros_min %u\n", + htt_stats_buf->last_non_zeros_min); + len += scnprintf(buf + len, buf_len - len, "last_non_zeros_avg %u\n", + htt_stats_buf->last_non_zeros_avg); + len += scnprintf(buf + len, buf_len - len, "last_non_zeros_sample %u\n", + htt_stats_buf->last_non_zeros_sample); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_soc_fw_refill_ring_num_refill_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_RX_STATS_REFILL_MAX_RING); + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_SOC_FW_REFILL_RING_NUM_REFILL_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->refill_ring_num_refill, + "refill_ring_num_refill", num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_rx_pdev_fw_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_fw_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_PDEV_FW_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "ppdu_recvd = %u\n", + htt_stats_buf->ppdu_recvd); + len += scnprintf(buf + len, buf_len - len, "mpdu_cnt_fcs_ok = %u\n", + htt_stats_buf->mpdu_cnt_fcs_ok); + len += scnprintf(buf + len, buf_len - len, "mpdu_cnt_fcs_err = %u\n", + htt_stats_buf->mpdu_cnt_fcs_err); + len += scnprintf(buf + len, buf_len - len, "tcp_msdu_cnt = %u\n", + htt_stats_buf->tcp_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, "tcp_ack_msdu_cnt = %u\n", + htt_stats_buf->tcp_ack_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, "udp_msdu_cnt = %u\n", + htt_stats_buf->udp_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, "other_msdu_cnt = %u\n", + htt_stats_buf->other_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, "fw_ring_mpdu_ind = %u\n", + htt_stats_buf->fw_ring_mpdu_ind); + len += scnprintf(buf + len, buf_len - len, "fw_ring_mcast_data_msdu = %u\n", + htt_stats_buf->fw_ring_mcast_data_msdu); + len += scnprintf(buf + len, buf_len - len, "fw_ring_bcast_data_msdu = %u\n", + htt_stats_buf->fw_ring_bcast_data_msdu); + len += scnprintf(buf + len, buf_len - len, "fw_ring_ucast_data_msdu = %u\n", + htt_stats_buf->fw_ring_ucast_data_msdu); + len += scnprintf(buf + len, buf_len - len, "fw_ring_null_data_msdu = %u\n", + htt_stats_buf->fw_ring_null_data_msdu); + len += scnprintf(buf + len, buf_len - len, "fw_ring_mpdu_drop = %u\n", + htt_stats_buf->fw_ring_mpdu_drop); + len += scnprintf(buf + len, buf_len - len, "ofld_local_data_ind_cnt = %u\n", + htt_stats_buf->ofld_local_data_ind_cnt); + len += scnprintf(buf + len, buf_len - len, + "ofld_local_data_buf_recycle_cnt = %u\n", + htt_stats_buf->ofld_local_data_buf_recycle_cnt); + len += scnprintf(buf + len, buf_len - len, "drx_local_data_ind_cnt = %u\n", + htt_stats_buf->drx_local_data_ind_cnt); + len += scnprintf(buf + len, buf_len - len, + "drx_local_data_buf_recycle_cnt = %u\n", + htt_stats_buf->drx_local_data_buf_recycle_cnt); + len += scnprintf(buf + len, buf_len - len, "local_nondata_ind_cnt = %u\n", + htt_stats_buf->local_nondata_ind_cnt); + len += scnprintf(buf + len, buf_len - len, "local_nondata_buf_recycle_cnt = %u\n", + htt_stats_buf->local_nondata_buf_recycle_cnt); + len += scnprintf(buf + len, buf_len - len, "fw_status_buf_ring_refill_cnt = %u\n", + htt_stats_buf->fw_status_buf_ring_refill_cnt); + len += scnprintf(buf + len, buf_len - len, "fw_status_buf_ring_empty_cnt = %u\n", + htt_stats_buf->fw_status_buf_ring_empty_cnt); + len += scnprintf(buf + len, buf_len - len, "fw_pkt_buf_ring_refill_cnt = %u\n", + htt_stats_buf->fw_pkt_buf_ring_refill_cnt); + len += scnprintf(buf + len, buf_len - len, "fw_pkt_buf_ring_empty_cnt = %u\n", + htt_stats_buf->fw_pkt_buf_ring_empty_cnt); + len += scnprintf(buf + len, buf_len - len, "fw_link_buf_ring_refill_cnt = %u\n", + htt_stats_buf->fw_link_buf_ring_refill_cnt); + len += scnprintf(buf + len, buf_len - len, "fw_link_buf_ring_empty_cnt = %u\n", + htt_stats_buf->fw_link_buf_ring_empty_cnt); + len += scnprintf(buf + len, buf_len - len, "host_pkt_buf_ring_refill_cnt = %u\n", + htt_stats_buf->host_pkt_buf_ring_refill_cnt); + len += scnprintf(buf + len, buf_len - len, "host_pkt_buf_ring_empty_cnt = %u\n", + htt_stats_buf->host_pkt_buf_ring_empty_cnt); + len += scnprintf(buf + len, buf_len - len, "mon_pkt_buf_ring_refill_cnt = %u\n", + htt_stats_buf->mon_pkt_buf_ring_refill_cnt); + len += scnprintf(buf + len, buf_len - len, "mon_pkt_buf_ring_empty_cnt = %u\n", + htt_stats_buf->mon_pkt_buf_ring_empty_cnt); + len += scnprintf(buf + len, buf_len - len, + "mon_status_buf_ring_refill_cnt = %u\n", + htt_stats_buf->mon_status_buf_ring_refill_cnt); + len += scnprintf(buf + len, buf_len - len, "mon_status_buf_ring_empty_cnt = %u\n", + htt_stats_buf->mon_status_buf_ring_empty_cnt); + len += scnprintf(buf + len, buf_len - len, "mon_desc_buf_ring_refill_cnt = %u\n", + htt_stats_buf->mon_desc_buf_ring_refill_cnt); + len += scnprintf(buf + len, buf_len - len, "mon_desc_buf_ring_empty_cnt = %u\n", + htt_stats_buf->mon_desc_buf_ring_empty_cnt); + len += scnprintf(buf + len, buf_len - len, "mon_dest_ring_update_cnt = %u\n", + htt_stats_buf->mon_dest_ring_update_cnt); + len += scnprintf(buf + len, buf_len - len, "mon_dest_ring_full_cnt = %u\n", + htt_stats_buf->mon_dest_ring_full_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_suspend_cnt = %u\n", + htt_stats_buf->rx_suspend_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_suspend_fail_cnt = %u\n", + htt_stats_buf->rx_suspend_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_resume_cnt = %u\n", + htt_stats_buf->rx_resume_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_resume_fail_cnt = %u\n", + htt_stats_buf->rx_resume_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_ring_switch_cnt = %u\n", + htt_stats_buf->rx_ring_switch_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_ring_restore_cnt = %u\n", + htt_stats_buf->rx_ring_restore_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_flush_cnt = %u\n", + htt_stats_buf->rx_flush_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_recovery_reset_cnt = %u\n", + htt_stats_buf->rx_recovery_reset_cnt); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_pdev_fw_ring_mpdu_err_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_PDEV_FW_RING_MPDU_ERR_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->fw_ring_mpdu_err, + "fw_ring_mpdu_err", HTT_RX_STATS_RXDMA_MAX_ERR, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_pdev_fw_mpdu_drop_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_fw_mpdu_drop_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_RX_STATS_FW_DROP_REASON_MAX); + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_PDEV_FW_MPDU_DROP_TLV_V:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->fw_mpdu_drop, "fw_mpdu_drop", + num_elems, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_pdev_fw_stats_phy_err_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_fw_stats_phy_err_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_PDEV_FW_STATS_PHY_ERR_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id__word = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "total_phy_err_nct = %u\n", + htt_stats_buf->total_phy_err_cnt); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->phy_err, "phy_errs", + HTT_STATS_PHY_ERR_MAX, "\n\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_cca_stats_hist_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_cca_stats_hist_v1_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "\nHTT_PDEV_CCA_STATS_HIST_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "chan_num = %u\n", + htt_stats_buf->chan_num); + len += scnprintf(buf + len, buf_len - len, "num_records = %u\n", + htt_stats_buf->num_records); + len += scnprintf(buf + len, buf_len - len, "valid_cca_counters_bitmap = 0x%x\n", + htt_stats_buf->valid_cca_counters_bitmap); + len += scnprintf(buf + len, buf_len - len, "collection_interval = %u\n", + htt_stats_buf->collection_interval); + + len += scnprintf(buf + len, buf_len - len, + "HTT_PDEV_STATS_CCA_COUNTERS_TLV:(in usec)\n"); + len += scnprintf(buf + len, buf_len - len, + "| tx_frame| rx_frame| rx_clear| my_rx_frame| cnt| med_rx_idle| med_tx_idle_global| cca_obss|"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_stats_cca_counters_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_stats_cca_counters_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "|%10u| %10u| %10u| %11u| %10u| %11u| %18u| %10u|\n", + htt_stats_buf->tx_frame_usec, + htt_stats_buf->rx_frame_usec, + htt_stats_buf->rx_clear_usec, + htt_stats_buf->my_rx_frame_usec, + htt_stats_buf->usec_cnt, + htt_stats_buf->med_rx_idle_usec, + htt_stats_buf->med_tx_idle_global_usec, + htt_stats_buf->cca_obss_usec); + + stats_req->buf_len = len; +} + +static inline void htt_print_hw_stats_whal_tx_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_hw_stats_whal_tx_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_stats_buf->mac_id__word); + + len += scnprintf(buf + len, buf_len - len, "HTT_HW_STATS_WHAL_TX_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "last_unpause_ppdu_id = %u\n", + htt_stats_buf->last_unpause_ppdu_id); + len += scnprintf(buf + len, buf_len - len, "hwsch_unpause_wait_tqm_write = %u\n", + htt_stats_buf->hwsch_unpause_wait_tqm_write); + len += scnprintf(buf + len, buf_len - len, "hwsch_dummy_tlv_skipped = %u\n", + htt_stats_buf->hwsch_dummy_tlv_skipped); + len += scnprintf(buf + len, buf_len - len, + "hwsch_misaligned_offset_received = %u\n", + htt_stats_buf->hwsch_misaligned_offset_received); + len += scnprintf(buf + len, buf_len - len, "hwsch_reset_count = %u\n", + htt_stats_buf->hwsch_reset_count); + len += scnprintf(buf + len, buf_len - len, "hwsch_dev_reset_war = %u\n", + htt_stats_buf->hwsch_dev_reset_war); + len += scnprintf(buf + len, buf_len - len, "hwsch_delayed_pause = %u\n", + htt_stats_buf->hwsch_delayed_pause); + len += scnprintf(buf + len, buf_len - len, "hwsch_long_delayed_pause = %u\n", + htt_stats_buf->hwsch_long_delayed_pause); + len += scnprintf(buf + len, buf_len - len, "sch_rx_ppdu_no_response = %u\n", + htt_stats_buf->sch_rx_ppdu_no_response); + len += scnprintf(buf + len, buf_len - len, "sch_selfgen_response = %u\n", + htt_stats_buf->sch_selfgen_response); + len += scnprintf(buf + len, buf_len - len, "sch_rx_sifs_resp_trigger= %u\n", + htt_stats_buf->sch_rx_sifs_resp_trigger); + + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_stats_twt_sessions_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_stats_twt_sessions_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_PDEV_STATS_TWT_SESSIONS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "pdev_id = %u\n", + htt_stats_buf->pdev_id); + len += scnprintf(buf + len, buf_len - len, "num_sessions = %u\n", + htt_stats_buf->num_sessions); + + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_stats_twt_session_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_stats_twt_session_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_addr = __le32_to_cpu(htt_stats_buf->peer_mac.mac_addr_l32); + u32 mac_addr_16 = __le32_to_cpu(htt_stats_buf->peer_mac.mac_addr_h16); + + len += scnprintf(buf + len, buf_len - len, "HTT_PDEV_STATS_TWT_SESSION_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "vdev_id = %u\n", + htt_stats_buf->vdev_id); + len += scnprintf(buf + len, buf_len - len, + "peer_mac = %02x:%02x:%02x:%02x:%02x:%02x\n", + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_0), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_1), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_2), + u32_get_bits(mac_addr, HTT_MAC_ADDR_L32_3), + u32_get_bits(mac_addr_16, HTT_MAC_ADDR_H16_0), + u32_get_bits(mac_addr_16, HTT_MAC_ADDR_H16_1)); + len += scnprintf(buf + len, buf_len - len, "flow_id_flags = %u\n", + htt_stats_buf->flow_id_flags); + len += scnprintf(buf + len, buf_len - len, "dialog_id = %u\n", + htt_stats_buf->dialog_id); + len += scnprintf(buf + len, buf_len - len, "wake_dura_us = %u\n", + htt_stats_buf->wake_dura_us); + len += scnprintf(buf + len, buf_len - len, "wake_intvl_us = %u\n", + htt_stats_buf->wake_intvl_us); + len += scnprintf(buf + len, buf_len - len, "sp_offset_us = %u\n", + htt_stats_buf->sp_offset_us); + + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_obss_pd_stats_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_obss_pd_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_PDEV_OBSS_PD_STATS_TLV:\n"); + /* + * Successful/Failure OBSS Transmission stats are omitted out as they + * are not supported in the current chipsets. + */ + len += scnprintf(buf + len, buf_len - len, "num_spatial_reuse_tx = %u\n", + htt_stats_buf->num_sr_tx_transmissions); + len += scnprintf(buf + len, buf_len - len, + "num_spatial_reuse_opportunities = %u\n", + htt_stats_buf->num_spatial_reuse_opportunities); + len += scnprintf(buf + len, buf_len - len, "num_non_srg_opportunities = %u\n", + htt_stats_buf->num_non_srg_opportunities); + len += scnprintf(buf + len, buf_len - len, "num_non_srg_ppdu_tried = %u\n", + htt_stats_buf->num_non_srg_ppdu_tried); + len += scnprintf(buf + len, buf_len - len, "num_non_srg_ppdu_success = %u\n", + htt_stats_buf->num_non_srg_ppdu_success); + len += scnprintf(buf + len, buf_len - len, "num_psr_opportunities = %u\n", + htt_stats_buf->num_psr_opportunities); + len += scnprintf(buf + len, buf_len - len, "num_psr_ppdu_tried = %u\n", + htt_stats_buf->num_psr_ppdu_tried); + len += scnprintf(buf + len, buf_len - len, "num_psr_ppdu_success = %u\n", + htt_stats_buf->num_psr_ppdu_success); + + stats_req->buf_len = len; +} + +static inline void htt_print_backpressure_stats_tlv_v(const u32 *tag_buf, + u8 *data) +{ + struct debug_htt_stats_req *stats_req = + (struct debug_htt_stats_req *)data; + struct htt_ring_backpressure_stats_tlv *htt_stats_buf = + (struct htt_ring_backpressure_stats_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "pdev_id = %u\n", + htt_stats_buf->pdev_id); + len += scnprintf(buf + len, buf_len - len, "Head_idx = %u\n", + htt_stats_buf->current_head_idx); + len += scnprintf(buf + len, buf_len - len, "Tail_idx = %u\n", + htt_stats_buf->current_tail_idx); + len += scnprintf(buf + len, buf_len - len, "Num Backpressure Msgs sent = %u\n", + htt_stats_buf->num_htt_msgs_sent); + len += scnprintf(buf + len, buf_len - len, + "backpressure_time_ms = %u\n", + htt_stats_buf->backpressure_time_ms); + + len += scnprintf(buf + len, buf_len - len, "Ring Backpressure Histogram\n"); + len += scnprintf(buf + len, buf_len - len, + "100ms to 200ms = %u, 200ms to 300ms = %u, 300ms to 400ms = %u\n", + htt_stats_buf->backpressure_hist[0], + htt_stats_buf->backpressure_hist[1], + htt_stats_buf->backpressure_hist[2]); + + len += scnprintf(buf + len, buf_len - len, + "400ms to 500 ms = %u, Above 500ms = %u\n", + htt_stats_buf->backpressure_hist[3], + htt_stats_buf->backpressure_hist[4]); + + len += scnprintf(buf + len, buf_len - len, + "============================"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_be_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_be_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_SELFGEN_BE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "be_su_ndpa_queued = %u\n", + htt_stats_buf->be_su_ndpa_queued); + len += scnprintf(buf + len, buf_len - len, "be_su_ndpa_tried = %u\n", + htt_stats_buf->be_su_ndpa); + len += scnprintf(buf + len, buf_len - len, "be_su_ndp_queued = %u\n", + htt_stats_buf->be_su_ndp_queued); + len += scnprintf(buf + len, buf_len - len, "be_su_ndp_tried = %u\n", + htt_stats_buf->be_su_ndp); + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_ndpa_queued = %u\n", + htt_stats_buf->be_mu_mimo_ndpa_queued); + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_ndpa_tried = %u\n", + htt_stats_buf->be_mu_mimo_ndpa); + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_ndp_queued = %u\n", + htt_stats_buf->be_mu_mimo_ndp_queued); + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_ndp_tried = %u\n", + htt_stats_buf->be_mu_mimo_ndp); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_brpoll_queued, + "be_mu_mimo_brpollX_queued", + HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_brpoll, + "be_mu_mimo_brpollX_tried", + HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_ul_mumimo_trigger, + "be_ul_mumimo_trigger", + HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS, "\n\n"); + + len += scnprintf(buf + len, buf_len - len, + "be_basic_trigger = %u\n", + htt_stats_buf->be_basic_trigger); + len += scnprintf(buf + len, buf_len - len, + "be_ulmumimo_total_trigger = %u\n", + htt_stats_buf->be_ulmumimo_trigger); + len += scnprintf(buf + len, buf_len - len, "be_bsr_trigger = %u\n", + htt_stats_buf->be_bsr_trigger); + len += scnprintf(buf + len, buf_len - len, "be_mu_bar_trigger = %u\n", + htt_stats_buf->be_mu_bar_trigger); + len += scnprintf(buf + len, buf_len - len, "be_mu_rts_trigger = %u\n", + htt_stats_buf->be_mu_rts_trigger); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_selfgen_be_sched_status_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_selfgen_be_sched_status_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_SELFGEN_BE_SCHED_STATUS_STATS_TLV:\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_su_ndpa_sch_status, + "be_su_ndpa_sch_status", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_su_ndp_sch_status, + "be_su_ndp_sch_status", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_ndpa_sch_status, + "be_mu_mimo_ndpa_sch_status", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_ndp_sch_status, + "be_mu_mimo_ndp_sch_status", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_brp_sch_status, + "be_mu_brp_sch_status", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_bar_sch_status, + "be_mu_bar_sch_status", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_basic_trig_sch_status, + "be_basic_trig_sch_status", + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_su_ndp_sch_flag_err, + "be_su_ndp_sch_flag_er", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_ndp_sch_flag_err, + "be_mu_mimo_ndp_sch_flag_err", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_brp_sch_flag_err, + "be_mu_brp_sch_flag_err", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_bar_sch_flag_err, + "be_mu_bar_sch_flag_err", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_basic_trig_sch_flag_err, + "be_basic_trig_sch_flag_err", + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS, "\n\n"); + + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_be_ul_mu_mimo_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 i; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "11be UL MU_MIMO SCH STATS:\n"); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "be_ul_mu_mimo_basic_sch_nusers_%u = %u", i, + htt_stats_buf->be_ul_mu_mimo_basic_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "be_ul_mu_mimo_brp_sch_nusers_%u = %u", i, + htt_stats_buf->be_ul_mu_mimo_brp_sch_nusers[i]); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_be_rate_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_rate_stats_be_tlv *htt_stats_buf = tag_buf; + u8 i, j; + char *tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS]; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) { + tx_gi[i] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!tx_gi[i]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_BE_RATE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "be_mu_mimo_tx_ldpc = %u", + htt_stats_buf->be_mu_mimo_tx_ldpc); + + /* MCS -2 and -1 will be printed first */ + len += scnprintf(buf + len, buf_len - len, " -2:%u,-1:%u,", + htt_stats_buf->be_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS-2], + htt_stats_buf->be_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS-1]); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_tx_mcs, + "be_mu_mimo_tx_mcs", + HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_tx_nss, + "be_mu_mimo_tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_tx_bw, + "be_mu_mimo_tx_bw", + HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS, "\n"); + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_tx_gi[%u] = %s ", j, tx_gi[j]); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_tx_gi[j], + NULL, HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS, "\n"); + } + + if (len >= buf_len) + buf[buf_len - 1] = 0; + else + buf[len] = 0; + + stats_req->buf_len = len; +fail: + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) + kfree(tx_gi[i]); + +} + +static inline void +htt_print_be_ul_mimo_user_stats(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_be_ul_mimo_user_stats_tlv *htt_ul_user_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + if (htt_ul_user_stats_buf->user_index < HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER) { + if (htt_ul_user_stats_buf->user_index == 0) + len += scnprintf(buf + len, buf_len - len, + "HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TLV\n"); + + len += scnprintf(buf + len, buf_len - len, "be_rx_ulmumimo_non_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulmumimo_non_data_ppdu); + len += scnprintf(buf + len, buf_len - len, "be_rx_ulmumimo_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulmumimo_data_ppdu); + len += scnprintf(buf + len, buf_len - len, "be_rx_ulmumimo_mpdu_ok_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulmumimo_mpdu_ok); + len += scnprintf(buf + len, buf_len - len, "be_rx_ulmumimo_mpdu_fail_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulmumimo_mpdu_fail); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_ul_mumimo_trig_be_stats(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_ul_mumimo_trig_be_stats_tlv *htt_ul_mumimo_trig_be_stats_buf = tag_buf; + char *rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS]; + u8 i, j; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_ul_mumimo_trig_be_stats_buf->mac_id__word); + + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) { + rx_gi[i] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!rx_gi[i]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + + len += scnprintf(buf + len, buf_len - len, "rx_11be_ul_mumimo = %u\n", + htt_ul_mumimo_trig_be_stats_buf->rx_11be_ul_mumimo); + + /* TODO: Check if enough space is present before writing BE MCS Counters */ + /* MCS -2 and -1 will be printed first */ + + len += scnprintf(buf + len, buf_len - len, " -2:%u,-1:%u\n", + htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS-2], + htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS-1]); + + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_mcs, + "be_ul_mumimo_rx_mcs", + HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS - 2, "\n\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, " -2:%u,-1:%u\n", + htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_gi[j][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS-2], + htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_gi[j][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS-1]); + + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_gi[j], + NULL, HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS-2, "\n\n"); + + len += scnprintf(buf + len, buf_len - len, + "be_ul_mumimo_rx_gi[%u] = %s ", j, rx_gi[j]); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_nss, + "be_ul_mumimo_rx_nss", + HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_bw, + "be_ul_mumimo_rx_bw", + HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS, "\n\n"); + + len += scnprintf(buf + len, buf_len - len, + "be_ul_mumimo_rx_stbc = %u\n", + htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_stbc); + len += scnprintf(buf + len, buf_len - len, + "be_ul_mumimo_rx_ldpc = %u\n", + htt_ul_mumimo_trig_be_stats_buf->be_ul_mumimo_rx_ldpc); + + for (i = 0; i < HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS; i++) { + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_be_stats_buf->be_rx_ul_mumimo_chain_rssi_in_dbm[i], + NULL, HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS, "\n\n"); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ul_mumimo_rssi_in_dbm: chain[%u] = %s ", + i, htt_ul_mumimo_trig_be_stats_buf->be_rx_ul_mumimo_chain_rssi_in_dbm[i]); + } + + for (i = 0; i < HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER; i++) { + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_be_stats_buf->be_rx_ul_mumimo_target_rssi[i], + NULL, HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS, "\n\n"); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ul_mumimo_target_rssi: user[%u] = %s ", + i, htt_ul_mumimo_trig_be_stats_buf->be_rx_ul_mumimo_target_rssi[i]); + } + + for (i = 0; i < HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER; i++) { + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_be_stats_buf->be_rx_ul_mumimo_fd_rssi[i], + NULL, HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS, "\n\n"); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ul_mumimo_fd_rssi: user[%u] = %s ", + i, htt_ul_mumimo_trig_be_stats_buf->be_rx_ul_mumimo_fd_rssi[i]); + } + + for (i = 0; i < HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER; i++) { + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_be_stats_buf->be_rx_ulmumimo_pilot_evm_dB_mean[i], + NULL, HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS, "\n\n"); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ulmumimo_pilot_evm_dB_mean: user [%u] = %s ", + i, htt_ul_mumimo_trig_be_stats_buf->be_rx_ulmumimo_pilot_evm_dB_mean[i]); + } + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +fail: + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) + kfree(rx_gi[i]); +} + +static inline void +htt_print_be_ul_ofdma_trigger_stats(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_be_ul_trigger_stats_tlv *htt_trigger_stats_buf = tag_buf; + char *rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS]; + u8 i, j; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id_word = __le32_to_cpu(htt_trigger_stats_buf->mac_id__word); + + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) { + rx_gi[i] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!rx_gi[i]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_PDEV_BE_UL_TRIGGER_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id_word, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "rx_11be_ul_ofdma =%u\n", + htt_trigger_stats_buf->rx_11be_ul_ofdma); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_ul_ofdma_rx_mcs, + "be_ul_ofdma_rx_mcs", + HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, + "be_ul_ofdma_rx_gi[%u] = %s ", j, rx_gi[j]); + for (i = 0; i < HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, " %u:%u", i, + htt_trigger_stats_buf->be_ul_ofdma_rx_gi[j][i]); + } + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_ul_ofdma_rx_nss, + "be_ul_ofdma_rx_nss", + HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_ul_ofdma_rx_bw, + "be_ul_ofdma_rx_bw", + HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "be_ul_ofdma_rx_stbc = %u\n", + htt_trigger_stats_buf->be_ul_ofdma_rx_stbc); + len += scnprintf(buf + len, buf_len - len, "be_ul_ofdma_rx_ldpc = %u\n", + htt_trigger_stats_buf->be_ul_ofdma_rx_ldpc); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_rx_ulofdma_data_ru_size_ppdu, + "be_rx_ulofdma_data_ru_size_ppdu", + HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_rx_ulofdma_non_data_ru_size_ppdu, + "be_rx_ulofdma_non_data_ru_size_ppdu", + HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_uplink_sta_aid, + "be_rx_rssi_track_sta_aid", + HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_uplink_sta_target_rssi, + "be_rx_sta_target_rssi", + HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_uplink_sta_fd_rssi, + "be_uplink_sta_fd_rssi", + HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->be_uplink_sta_power_headroom, + "be_rx_sta_power_headroom", + HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +fail: + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) + kfree(rx_gi[i]); +} + +static inline void +htt_print_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 i; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "11BE DL MU_OFDMA SCH STATS:\n"); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "be_mu_ofdma_sch_nusers_%u = %u\n", i, + htt_stats_buf->be_mu_ofdma_sch_nusers[i]); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv *htt_stats_buf = tag_buf; + u8 i; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "\n11ax BE UL MU_OFDMA SCH STATS:"); + + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "be_ul_mu_ofdma_basic_sch_nusers_%u = %u\n", i, + htt_stats_buf->be_ul_mu_ofdma_basic_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "be_ul_mu_ofdma_bsr_sch_nusers_%u = %u\n", i, + htt_stats_buf->be_ul_mu_ofdma_bsr_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "be_ul_mu_ofdma_bar_sch_nusers_%u = %u\n", i, + htt_stats_buf->be_ul_mu_ofdma_bar_sch_nusers[i]); + len += scnprintf(buf + len, buf_len - len, + "be_ul_mu_ofdma_brp_sch_nusers_%u = %u\n", i, + htt_stats_buf-> be_ul_mu_ofdma_brp_sch_nusers[i]); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_rate_stats_be_ofdma_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_rate_stats_be_ofdma_tlv *htt_stats_buf = tag_buf; + u8 i, j; + char *tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS]; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) { + tx_gi[i] = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!tx_gi[i]) + goto fail; + } + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_PDEV_RATE_STATS_BE_OFDMA_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + htt_stats_buf->mac_id__word & 0xFF); + + len += scnprintf(buf + len, buf_len - len, "be_ofdma_tx_ldpc = %u\n", + htt_stats_buf->be_ofdma_tx_ldpc); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_ofdma_tx_mcs, + "be_ofdma_tx_mcs", + HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_ofdma_tx_nss, + "be_ofdma_tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_ofdma_tx_bw, + "be_ofdma_tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_ofdma_eht_sig_mcs, + "be_ofdma_eht_sig_mcs", + HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_ofdma_tx_ru_size, + "be_ofdma_tx_ru_size", + HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, "\n"); + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_tx_gi[%u] = %s ", j, tx_gi[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i, + htt_stats_buf->be_ofdma_tx_gi[j][i]); + } + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + stats_req->buf_len = len; +fail: + for (i = 0; i < HTT_TX_PEER_STATS_NUM_GI_COUNTERS; i++) + kfree(tx_gi[i]); +} + +static inline void +htt_print_tx_selfgen_be_err_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + const struct htt_tx_selfgen_be_err_stats_tlv *htt_stats_buf = tag_buf; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TX_SELFGEN_BE_ERR_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "be_su_ndp_err = %u\n", + htt_stats_buf->be_su_ndp_err); + len += scnprintf(buf + len, buf_len - len, "be_su_ndp_flushed = %u\n", + htt_stats_buf->be_su_ndp_flushed); + len += scnprintf(buf + len, buf_len - len, "be_su_ndpa_err = %u\n", + htt_stats_buf->be_su_ndpa_err); + len += scnprintf(buf + len, buf_len - len, "be_su_ndpa_flushed = %u\n", + htt_stats_buf->be_su_ndpa_flushed); + len += scnprintf(buf + len, buf_len - len, "be_mu_mimo_ndpa_err = %u\n", + htt_stats_buf->be_mu_mimo_ndpa_err); + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_ndpa_flushed = %u\n", + htt_stats_buf->be_mu_mimo_ndpa_flushed); + len += scnprintf(buf + len, buf_len - len, "be_mu_mimo_ndp_err = %u\n", + htt_stats_buf->be_mu_mimo_ndp_err); + len += scnprintf(buf + len, buf_len - len, + "be_mu_mimo_ndp_flushed = %u\n", + htt_stats_buf->be_mu_mimo_ndp_flushed); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_brp_err, + "be_mu_mimo_brpX_err", + HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1, "\n\n"); + + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_brpoll_flushed, + "be_mu_mimo_brpollX_flushed", + HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_mu_mimo_brp_err_num_cbf_received, + "be_mu_mimo_num_cbf_rcvd_on_brp_err", + HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS, "\n\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->be_ul_mumimo_trigger_err, + "be_ul_mumimo_trigger_err", + HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS, "\n\n"); + + len += scnprintf(buf + len, buf_len - len, "be_basic_trigger_err = %u\n", + htt_stats_buf->be_basic_trigger_err); + len += scnprintf(buf + len, buf_len - len, + "be_ulmumimo_total_trigger_err = %u\n", + htt_stats_buf->be_ulmumimo_trigger_err); + len += scnprintf(buf + len, buf_len - len, "be_bsr_trigger_err = %u\n", + htt_stats_buf->be_bsr_trigger_err); + len += scnprintf(buf + len, buf_len - len, + "be_mu_bar_trigger_err = %u\n", + htt_stats_buf->be_mu_bar_trigger_err); + len += scnprintf(buf + len, buf_len - len, + "be_mu_rts_trigger_err = %u\n", + htt_stats_buf->be_mu_rts_trigger_err); +} + +static inline void htt_print_latency_prof_stats_tlv_v(const u32 *tag_buf, u8 *data) +{ + struct debug_htt_stats_req *stats_req = + (struct debug_htt_stats_req *)data; + struct htt_latency_prof_stats_tlv *htt_stats_buf = + (struct htt_latency_prof_stats_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + if (htt_stats_buf->print_header == 1) { + len += scnprintf(buf + len, buf_len - len, + "HTT_STATS_LATENCY_PROF_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, + "| prof_name\t| cnt\t| min\t| max\t| last\t| tot\t| avg \t| hist_intvl\t| hist\t|\n"); + } + + len += scnprintf(buf + len, buf_len - len, + "|%s| %8u| %8u| %8u| %8u| %8u| %8u| %8u| %4u:%4u:%4u|\n", + htt_stats_buf->latency_prof_name, htt_stats_buf->cnt, + htt_stats_buf->min, htt_stats_buf->max, htt_stats_buf->last, + htt_stats_buf->tot, htt_stats_buf->avg, + htt_stats_buf->hist_intvl, htt_stats_buf->hist[0], + htt_stats_buf->hist[1], htt_stats_buf->hist[2]); + + stats_req->buf_len = len; +} + +static inline void htt_print_latency_prof_ctx_tlv(const u32 *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + struct htt_latency_prof_ctx_tlv *htt_stats_buf = + (struct htt_latency_prof_ctx_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_STATS_LATENCY_CTX_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "duration= %u\n", + htt_stats_buf->duration); + len += scnprintf(buf + len, buf_len - len, + "tx_msdu_cnt = %u\n", htt_stats_buf->tx_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, + "tx_mpdu_cnt = %u\n", htt_stats_buf->tx_mpdu_cnt); + len += scnprintf(buf + len, buf_len - len, + "rx_msdu_cnt = %u\n", htt_stats_buf->rx_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, + "rx_mpdu_cnt = %u\n", htt_stats_buf->rx_mpdu_cnt); + + stats_req->buf_len = len; +} + +static inline void htt_print_latency_prof_cnt(const u32 *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + struct htt_latency_prof_cnt_tlv *htt_stats_buf = + (struct htt_latency_prof_cnt_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "prof_enable_cnt = %u\n", + htt_stats_buf->prof_enable_cnt); + + stats_req->buf_len = len; +} + +static inline void htt_print_ul_mumimo_trig_stats(const u32 *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + struct htt_rx_pdev_ul_mumimo_trig_stats_tlv *htt_ul_mumimo_trig_stats_buf = + (struct htt_rx_pdev_ul_mumimo_trig_stats_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id = __le32_to_cpu(htt_ul_mumimo_trig_stats_buf->mac_id__word); + u8 j; + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_PDEV_UL_MUMIMO_TRIG_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id, HTT_STATS_MAC_ID)); + + len += scnprintf(buf + len, buf_len - len, + "rx_11ax_ul_mumimo = %u\n", + htt_ul_mumimo_trig_stats_buf->rx_11ax_ul_mumimo); + + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_mcs, + "ul_mumimo_rx_mcs", HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_mcs_ext, + "ul_mumimo_rx_mcs_ext", + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "\nul_mumimo_rx_gi[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_gi[j], + NULL, HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + len += scnprintf(buf + len, buf_len - len, ", "); + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_gi_ext[j], + NULL, HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_nss, + "ul_mumimo_rx_nss", + HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_bw, + "ul_mumimo_rx_bw", + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\nul_mumimo_rx_stbc = %u", + htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_stbc); + len += scnprintf(buf + len, buf_len - len, "\nul_mumimo_rx_ldpc = %u", + htt_ul_mumimo_trig_stats_buf->ul_mumimo_rx_ldpc); + + for (j = 0; j < HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS; j++) { + len += scnprintf(buf + len, buf_len - len, + "\nrx_ul_mumimo_rssi_in_dbm: chain[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_stats_buf->rx_ul_mumimo_chain_rssi_in_dbm[j], + NULL, HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS; j++) { + len += scnprintf(buf + len, buf_len - len, + "\nrx_ul_mumimo_target_rssi: user[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_stats_buf->rx_ul_mumimo_target_rssi[j], + NULL, HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + } + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS; j++) { + len += scnprintf(buf + len, buf_len - len, + "\nrx_ul_mumimo_fd_rssi: user[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_stats_buf->rx_ul_mumimo_fd_rssi[j], + NULL, HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS, + "\n"); + } + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS; j++) { + len += scnprintf(buf + len, buf_len - len, + "\nrx_ulmumimo_pilot_evm_db_mean: user [%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, + htt_ul_mumimo_trig_stats_buf->rx_ulmumimo_pilot_evm_db_mean[j], + NULL, HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS, + "\n"); + } + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_ul_mimo_user_stats(const u32 *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + struct htt_rx_pdev_ul_mimo_user_stats_tlv *htt_ul_user_stats_buf = + (struct htt_rx_pdev_ul_mimo_user_stats_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + if (htt_ul_user_stats_buf->user_index > HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER) { + if (htt_ul_user_stats_buf->user_index == 0) { + len += scnprintf(buf + len, buf_len - len, + "HTT_STATS_RX_PDEV_UL_MIMO_USER_STATS_TLV:\n"); + } + + len += scnprintf(buf + len, buf_len - len, + "rx_ulmumimo_non_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulmumimo_non_data_ppdu); + + len += scnprintf(buf + len, buf_len - len, + "rx_ulmumimo_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulmumimo_data_ppdu); + + len += scnprintf(buf + len, buf_len - len, + "rx_ulmumimo_mpdu_ok_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulmumimo_mpdu_ok); + + len += scnprintf(buf + len, buf_len - len, + "rx_ulmumimo_mpdu_fail_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulmumimo_mpdu_fail); + } + + stats_req->buf_len = len; +} + +static inline void htt_print_ul_ofdma_user_stats(const u32 *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + struct htt_rx_pdev_ul_ofdma_user_stats_tlv *htt_ul_user_stats_buf = + (struct htt_rx_pdev_ul_ofdma_user_stats_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + if (htt_ul_user_stats_buf->user_index == 0) { + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_PDEV_UL_OFDMA_USER_STAS_TLV:\n"); + } + + len += scnprintf(buf + len, buf_len - len, + "rx_ulofdma_non_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulofdma_non_data_ppdu); + len += scnprintf(buf + len, buf_len - len, + "rx_ulofdma_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulofdma_data_ppdu); + len += scnprintf(buf + len, buf_len - len, + "rx_ulofdma_mpdu_ok_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulofdma_mpdu_ok); + len += scnprintf(buf + len, buf_len - len, + "rx_ulofdma_mpdu_fail_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulofdma_mpdu_fail); + len += scnprintf(buf + len, buf_len - len, + "rx_ulofdma_non_data_nusers_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulofdma_non_data_nusers); + len += scnprintf(buf + len, buf_len - len, + "rx_ulofdma_data_nusers_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->rx_ulofdma_data_nusers); + + stats_req->buf_len = len; +} + +static inline void htt_print_ul_ofdma_trigger_stats(const u32 *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + struct htt_rx_pdev_ul_trigger_stats_tlv *htt_trigger_stats_buf = + (struct htt_rx_pdev_ul_trigger_stats_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 mac_id = __le32_to_cpu(htt_trigger_stats_buf->mac_id__word); + u8 j; + + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_PDEV_UL_TRIGGER_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id, HTT_STATS_MAC_ID)); + len += scnprintf(buf + len, buf_len - len, "rx_11ax_ul_ofdma =%u\n", + htt_trigger_stats_buf->rx_11ax_ul_ofdma); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->ul_ofdma_rx_mcs, + "ul_ofdma_rx_mcs", HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "\nul_ofdma_rx_gi[%u] = ", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->ul_ofdma_rx_gi[j], + NULL, HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS, "\n"); + } + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->ul_ofdma_rx_nss, + "ul_ofdma_rx_nss", HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS, + "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->ul_ofdma_rx_bw, + "ul_ofdma_rx_bw", HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + for (j = 0; j < HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "\nhalf_ul_ofdma_rx_bw = " : + "\nquarter_ul_ofdma_rx_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, + htt_trigger_stats_buf->reduced_ul_ofdma_rx_bw[j], + NULL, HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + } + len += scnprintf(buf + len, buf_len - len, "\nul_ofdma_rx_stbc = %u", + htt_trigger_stats_buf->ul_ofdma_rx_stbc); + len += scnprintf(buf + len, buf_len - len, "\nul_ofdma_rx_ldpc = %u", + htt_trigger_stats_buf->ul_ofdma_rx_ldpc); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->rx_ulofdma_data_ru_size_ppdu, + "rx_ulofdma_non_data_ru_size_ppdu", + HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_trigger_stats_buf->rx_ulofdma_non_data_ru_size_ppdu, + "rx_ulofdma_data_ru_size_ppdu", + HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->uplink_sta_aid, + "rx_rssi_track_sta_aid", HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, + "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->uplink_sta_target_rssi, + "rx_sta_target_rssi", HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->uplink_sta_fd_rssi, + "rx_sta_fd_rssi", HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_trigger_stats_buf->uplink_sta_power_headroom, + "rx_sta_power_headroom", HTT_RX_UL_MAX_UPLINK_RSSI_TRACK, + "\n"); + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_rx_fse_stats_tlv(const u32 *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + struct htt_rx_fse_stats_tlv *htt_stats_buf = + (struct htt_rx_fse_stats_tlv *)tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_STATS_RX_FSE_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "=== Software RX FSE STATS ===\n"); + len += scnprintf(buf + len, buf_len - len, + "Enable count = %u\n", htt_stats_buf->fse_enable_cnt); + len += scnprintf(buf + len, buf_len - len, + "Disable count = %u\n", htt_stats_buf->fse_disable_cnt); + len += scnprintf(buf + len, buf_len - len, + "Cache Invalidate Entry Count = %u\n", + htt_stats_buf->fse_cache_invalidate_entry_cnt); + len += scnprintf(buf + len, buf_len - len, + "Full Cache Invalidate Count = %u\n", + htt_stats_buf->fse_full_cache_invalidate_cnt); + len += scnprintf(buf + len, buf_len - len, + "=== Hardware RX FSE STATS ===\n"); + len += scnprintf(buf + len, buf_len - len, "Cache hits Count = %u\n", + htt_stats_buf->fse_num_cache_hits_cnt); + len += scnprintf(buf + len, buf_len - len, "Cache No. of searches = %u\n", + htt_stats_buf->fse_num_searches_cnt); + len += scnprintf(buf + len, buf_len - len, "Cache occupancy Peak Count:\n"); + len += scnprintf(buf + len, buf_len - len, + " [0] = %u [1-16] = %u [17-32] = %u " + "[33-48] = %u [49-64] = %u [65-80] = %u " + "[81-96] = %u [97-112] = %u [113-127] = %u " + "[128] = %u\n", + htt_stats_buf->fse_cache_occupancy_peak_cnt[0], + htt_stats_buf->fse_cache_occupancy_peak_cnt[1], + htt_stats_buf->fse_cache_occupancy_peak_cnt[2], + htt_stats_buf->fse_cache_occupancy_peak_cnt[3], + htt_stats_buf->fse_cache_occupancy_peak_cnt[4], + htt_stats_buf->fse_cache_occupancy_peak_cnt[5], + htt_stats_buf->fse_cache_occupancy_peak_cnt[6], + htt_stats_buf->fse_cache_occupancy_peak_cnt[7], + htt_stats_buf->fse_cache_occupancy_peak_cnt[8], + htt_stats_buf->fse_cache_occupancy_peak_cnt[9]); + len += scnprintf(buf + len, buf_len - len, + "Cache occupancy Current Count:\n"); + len += scnprintf(buf + len, buf_len - len, + " [0] = %u [1-16] = %u [17-32] = %u " + "[33-48] = %u [49-64] = %u [65-80] = %u " + "[81-96] = %u [97-112] = %u [113-127] = %u " + "[128] = %u\n", + htt_stats_buf->fse_cache_occupancy_curr_cnt[0], + htt_stats_buf->fse_cache_occupancy_curr_cnt[1], + htt_stats_buf->fse_cache_occupancy_curr_cnt[2], + htt_stats_buf->fse_cache_occupancy_curr_cnt[3], + htt_stats_buf->fse_cache_occupancy_curr_cnt[4], + htt_stats_buf->fse_cache_occupancy_curr_cnt[5], + htt_stats_buf->fse_cache_occupancy_curr_cnt[6], + htt_stats_buf->fse_cache_occupancy_curr_cnt[7], + htt_stats_buf->fse_cache_occupancy_curr_cnt[8], + htt_stats_buf->fse_cache_occupancy_curr_cnt[9]); + len += scnprintf(buf + len, buf_len - len, "Cache search Square Count:\n"); + len += scnprintf(buf + len, buf_len - len, + " [0] = %u [1-50] = %u [51-100] = %u " + "[101-200] = %u [201-255] = %u [256] = %u\n", + htt_stats_buf->fse_search_stat_square_cnt[0], + htt_stats_buf->fse_search_stat_square_cnt[1], + htt_stats_buf->fse_search_stat_square_cnt[2], + htt_stats_buf->fse_search_stat_square_cnt[3], + htt_stats_buf->fse_search_stat_square_cnt[4], + htt_stats_buf->fse_search_stat_square_cnt[5]); + + len += scnprintf(buf + len, buf_len - len, + "Cache search Peak Pending Count:\n"); + len += scnprintf(buf + len, buf_len - len, + " [0] = %u [1-2] = %u [3-4] = %u " + "[Greater/Equal to 5] = %u\n", + htt_stats_buf->fse_search_stat_peak_cnt[0], + htt_stats_buf->fse_search_stat_peak_cnt[1], + htt_stats_buf->fse_search_stat_peak_cnt[2], + htt_stats_buf->fse_search_stat_peak_cnt[3]); + len += scnprintf(buf + len, buf_len - len, + "Cache search Number of Pending Count:\n"); + len += scnprintf(buf + len, buf_len - len, + " [0] = %u [1-2] = %u [3-4] = %u " + "[Greater/Equal to 5] = %u\n", + htt_stats_buf->fse_search_stat_search_pending_cnt[0], + htt_stats_buf->fse_search_stat_search_pending_cnt[1], + htt_stats_buf->fse_search_stat_search_pending_cnt[2], + htt_stats_buf->fse_search_stat_search_pending_cnt[3]); + + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_tx_rate_txbf_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_txrate_txbf_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i, j; + + len += scnprintf(buf + len, buf_len - len, + "HTT_STATS_PDEV_TX_RATE_TXBF_STATS:\n"); + len += scnprintf(buf + len, buf_len - len, + "Legacy OFDM Rates: 6 Mbps: %u, 9 Mbps: %u, 12 Mbps: %u, 18 Mbps: %u\n" + " 24 Mbps: %u, 36 Mbps: %u, 48 Mbps: %u, 54 Mbps: %u\n", + htt_stats_buf->tx_legacy_ofdm_rate[0], + htt_stats_buf->tx_legacy_ofdm_rate[1], + htt_stats_buf->tx_legacy_ofdm_rate[2], + htt_stats_buf->tx_legacy_ofdm_rate[3], + htt_stats_buf->tx_legacy_ofdm_rate[4], + htt_stats_buf->tx_legacy_ofdm_rate[5], + htt_stats_buf->tx_legacy_ofdm_rate[6], + htt_stats_buf->tx_legacy_ofdm_rate[7]); + + len += scnprintf(buf + len, buf_len - len, "tx_ol_mcs = "); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_ol_mcs[i]); + + len += scnprintf(buf + len, buf_len - len, "\ntx_ibf_mcs = "); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_ibf_mcs[i]); + + len += scnprintf(buf + len, buf_len - len, "\ntx_txbf_mcs ="); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_txbf_mcs[i]); + + len += scnprintf(buf + len, buf_len - len, "\ntx_ol_nss = "); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_ol_nss[i]); + + len += scnprintf(buf + len, buf_len - len, "\ntx_ibf_nss = "); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_ibf_nss[i]); + + len += scnprintf(buf + len, buf_len - len, "\ntx_txbf_nss = "); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_txbf_nss[i]); + + len += scnprintf(buf + len, buf_len - len, "\ntx_ol_bw = "); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_ol_bw[i]); + + for (j = 0; j < HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "\nhalf_tx_ol_bw = " : "\nquarter_tx_ol_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_tx_su_ol_bw[j], + NULL, HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS, "\n"); + } + + len += scnprintf(buf + len, buf_len - len, "\ntx_ibf_bw = "); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_ibf_bw[i]); + + for (j = 0; j < HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "\nhalf_tx_ibf_bw = " : "\nquarter_tx_ibf_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_tx_su_ibf_bw[j], + NULL, HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS, "\n"); + } + + len += scnprintf(buf + len, buf_len - len, "\ntx_txbf_bw = "); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS; i++) + len += scnprintf(buf + len, buf_len - len, + "%d:%u,", i, htt_stats_buf->tx_su_txbf_bw[i]); + + for (j = 0; j < HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES; j++) { + len += scnprintf(buf + len, buf_len - len, j == 0 ? + "\nhalf_tx_txbf_bw = " : "\nquarter_tx_txbf_bw = "); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_tx_su_txbf_bw[j], + NULL, HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS, "\n"); + } + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_per_rate_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_per_rate_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char mode_prefix[][3] = {"su", "mu"}; + int i = 0, j = 0; + + if (htt_stats_buf->rc_mode == HTT_STATS_RC_MODE_DLSU) { + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PER_STATS:\n"); + len += scnprintf(buf + len, buf_len - len, "PER_STATS_SU:\n"); + } else if (htt_stats_buf->rc_mode == HTT_STATS_RC_MODE_DLMUMIMO) { + len += scnprintf(buf + len, buf_len - len, "\nPER_STATS_DL_MUMIMO:\n"); + j = 1; + } else { + return; + } + + len += scnprintf(buf + len, buf_len - len, "\nPER per BW:\n"); + + len += scnprintf(buf + len, buf_len - len, "ppdus_tried_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_BW_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_bw[i].ppdus_tried); + } + /* + * Now i = HTT_TX_PDEV_STATS_NUM_BW_COUNTERS. + * Adding 320 MHz ppdus tried. + */ + len += scnprintf(buf + len, buf_len - len, + " %u:%u\n", i, htt_stats_buf->per_bw320.ppdus_tried); + + len += scnprintf(buf + len, buf_len - len, "ppdus_ack_failed_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_BW_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_bw[i].ppdus_ack_failed); + } + /* + * Now i = HTT_TX_PDEV_STATS_NUM_BW_COUNTERS. + * Adding 320 MHz ppdus ack failed. + */ + len += scnprintf(buf + len, buf_len - len, + " %u:%u\n", i, htt_stats_buf->per_bw320.ppdus_ack_failed); + + len += scnprintf(buf + len, buf_len - len, "mpdus_tried_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_BW_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_bw[i].mpdus_tried); + } + /* + * Now i = HTT_TX_PDEV_STATS_NUM_BW_COUNTERS. + * Adding 320 MHz mpdus tried. + */ + len += scnprintf(buf + len, buf_len - len, + " %u:%u\n", i, htt_stats_buf->per_bw320.mpdus_tried); + + + len += scnprintf(buf + len, buf_len - len, "mpdus_failed_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_BW_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_bw[i].mpdus_failed); + } + /* + * Now i = HTT_TX_PDEV_STATS_NUM_BW_COUNTERS. + * Adding 320 MHz mpdus failed. + */ + len += scnprintf(buf + len, buf_len - len, + " %u:%u\n", i, htt_stats_buf->per_bw320.mpdus_failed); + + len += scnprintf(buf + len, buf_len - len, "\nPER per NSS:\n"); + + len += scnprintf(buf + len, buf_len - len, "ppdus_tried_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_nss[i].ppdus_tried); + } + + len += scnprintf(buf + len, buf_len - len, "\nppdus_ack_fialed_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_nss[i].ppdus_ack_failed); + } + + len += scnprintf(buf + len, buf_len - len, "\nmpdus_tried_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_nss[i].mpdus_tried); + } + + len += scnprintf(buf + len, buf_len - len, "\nmpdus_failed_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_nss[i].mpdus_failed); + } + + len += scnprintf(buf + len, buf_len - len, "\nPER per Mcs:\n"); + + len += scnprintf(buf + len, buf_len - len, "ppdus_tried_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_mcs[i].ppdus_tried); + } + + len += scnprintf(buf + len, buf_len - len, "\nppdus_ack_failed_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_mcs[i].ppdus_ack_failed); + } + + len += scnprintf(buf + len, buf_len - len, "\nmpdus_tried_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_mcs[i].mpdus_tried); + } + + len += scnprintf(buf + len, buf_len - len, "\nmpdus_failed_%s", mode_prefix[j]); + for (i = 0; i < HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u ", + i, htt_stats_buf->per_mcs[i].mpdus_failed); + } + + len += scnprintf(buf + len, buf_len - len, "\n"); + + if (htt_stats_buf->rc_mode == HTT_STATS_RC_MODE_DLMUMIMO) { + len += scnprintf(buf + len, buf_len - len, "last_probed_bw = %u\n", + htt_stats_buf->last_probed_bw); + len += scnprintf(buf + len, buf_len - len, "last_probed_nss = %u\n", + htt_stats_buf->last_probed_nss); + len += scnprintf(buf + len, buf_len - len, "last_probed_mcs = %u\n", + htt_stats_buf->last_probed_mcs); + } + + stats_req->buf_len = len; +} + +static +inline void htt_print_txbf_ofdma_ndpa_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_ndpa_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_NDPA_STATS_TLV:\n"); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndpa_queued_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndpa_queued[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndpa_tried_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndpa_tried[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndpa_flushed_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndpa_flushed[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndpa_err_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndpa_err[i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + stats_req->buf_len = len; +} + +static +inline void htt_print_txbf_ofdma_ndp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_ndp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_NDP_STATS_TLV:\n"); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndp_queued_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndp_queued[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndp_tried_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndp_tried[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndp_flushed_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndp_flushed[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_ndp_err_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_ndp_err[i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + stats_req->buf_len = len; +} + +static +inline void htt_print_txbf_ofdma_brp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_brp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_BRP_STATS_TLV:\n"); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_brpoll_queued_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_brpoll_queued[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_brpoll_tried_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_brpoll_tried[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_brpoll_flushed_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_brpoll_flushed[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_brp_err_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_brp_err[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_brp_err_num_cbf_rcvd_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_brp_err_num_cbf_rcvd[i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + stats_req->buf_len = len; +} + +static +inline void htt_print_txbf_ofdma_steer_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_steer_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_STEER_STATS_TLV:\n"); + for (i = 0; i < HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS; i++) { + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_num_ppdu_steer_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_num_ppdu_steer[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_num_ppdu_ol_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_num_ppdu_ol[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_num_usrs_prefetch_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_num_usrs_prefetch[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_num_usrs_sound_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_num_usrs_sound[i]); + len += scnprintf(buf + len, buf_len - len, + "ax_ofdma_num_usrs_force_sound_user%d = %u\n", + i, htt_stats_buf->ax_ofdma_num_usrs_force_sound[i]); + len += scnprintf(buf + len, buf_len - len, "\n"); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_ax_ndpa_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_ax_ndpa_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = htt_stats_buf->num_elems_ax_ndpa_arr; + int i, null_output; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_AX_NDPA_STATS_TLV:\n"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_queued) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_queued); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndpa_queued = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_tried) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_tried); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndpa_tried = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_flushed) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_flushed); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndpa_flushed = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_err) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndpa[i].ax_ofdma_ndpa_err); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndpa_err = %s\n", "NONE"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_ax_ndp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_ax_ndp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = htt_stats_buf->num_elems_ax_ndp_arr; + int i, null_output; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_AX_NDP_STATS_TLV:\n"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_queued) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_queued); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndp_queued = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_tried) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_tried); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndp_tried = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_flushed) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_flushed); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndp_flushed = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_err) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_ndp[i].ax_ofdma_ndp_err); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_ndp_err = %s\n", "NONE"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_ax_brp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_ax_brp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = htt_stats_buf->num_elems_ax_brp_arr; + int i, null_output; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_AX_BRP_STATS_TLV:\n"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_brp[i].ax_ofdma_brpoll_queued) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_brp[i].ax_ofdma_brpoll_queued); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_brpoll_queued = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_brp[i].ax_ofdma_brpoll_tried) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_brp[i].ax_ofdma_brpoll_tried); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_brpoll_tried = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_brp[i].ax_ofdma_brpoll_flushed) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_brp[i].ax_ofdma_brpoll_flushed); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_brpoll_flushed = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_brp[i].ax_ofdma_brp_err) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_brp[i].ax_ofdma_brp_err); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_brp_err = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_brp[i].ax_ofdma_brp_err_num_cbf_rcvd) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_brp[i].ax_ofdma_brp_err_num_cbf_rcvd); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_brp_err_num_cbf_rcvd = %s\n", "NONE"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_ax_steer_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_ax_steer_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = htt_stats_buf->num_elems_ax_steer_arr; + int i, null_output; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_AX_STEER_STATS_TLV:\n"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_steer[i].ax_ofdma_num_ppdu_steer) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_steer[i].ax_ofdma_num_ppdu_steer); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_num_ppdu_steer = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_steer[i].ax_ofdma_num_usrs_prefetch) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_steer[i].ax_ofdma_num_usrs_prefetch); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_num_usrs_prefetch = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_steer[i].ax_ofdma_num_usrs_sound) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_steer[i].ax_ofdma_num_usrs_sound); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_num_usrs_sound = %s\n", "NONE"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->ax_steer[i].ax_ofdma_num_usrs_force_sound) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u, ", i + 1, + htt_stats_buf->ax_steer[i].ax_ofdma_num_usrs_force_sound); + } + } + if (null_output) + len += scnprintf(buf + len, buf_len - len, "ax_ofdma_num_usrs_force_sound = %s\n", "NONE"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_be_ndpa_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_be_ndpa_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i, null_output; + u32 num_elements = htt_stats_buf->num_elems_be_ndpa_arr; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TXBF_OFDMA_BE_NDPA_STATS_TLV:\n"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_queued) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_queued); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_ndpa_queued = %s\n", "NONE"); + } + + null_output = 1; + + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_tried) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_tried); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_ndpa_tried = %s\n", "NONE"); + } + + null_output = 1; + + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_flushed) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_flushed); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_ndpa_flushed = %s\n", "NONE"); + } + + null_output = 1; + + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_err) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_ndpa[i].be_ofdma_ndpa_err); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_ndpa_err = %s\n", "NONE"); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_be_ndp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_be_ndp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i, null_output; + + u32 num_elements = htt_stats_buf->num_elems_be_ndp_arr; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_BE_NDP_STATS_TLV:\n"); + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_ndp[i].be_ofdma_ndp_queued) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_ndp[i].be_ofdma_ndp_queued); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_ndp_queued = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_ndp[i].be_ofdma_ndp_flushed) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_ndp[i].be_ofdma_ndp_flushed); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_ndp_flushed = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_ndp[i].be_ofdma_ndp_err) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_ndp[i].be_ofdma_ndp_err); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_ndp_err = %s\n", "NONE"); + } + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_be_brp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_be_brp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i, null_output; + + u32 num_elements = htt_stats_buf->num_elems_be_brp_arr; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_BE_BRP_STATS_TLV:\n"); + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_brp[i].be_ofdma_brpoll_queued) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_brp[i].be_ofdma_brpoll_queued); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_brpoll_queued = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_brp[i].be_ofdma_brpoll_tried) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_brp[i].be_ofdma_brpoll_tried); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_brpoll_tried = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_brp[i].be_ofdma_brpoll_flushed) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_brp[i].be_ofdma_brpoll_flushed); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_brpoll_flushed = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_brp[i].be_ofdma_brp_err) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_brp[i].be_ofdma_brp_err); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_brp_err = %s\n", "NONE"); + } + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_brp[i].be_ofdma_brp_err_num_cbf_rcvd) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_brp[i].be_ofdma_brp_err_num_cbf_rcvd); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_brp_err_num_cbf_rcvd = %s\n", "NONE"); + } + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_be_steer_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_be_steer_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i, null_output; + + u32 num_elements = htt_stats_buf->num_elems_be_steer_arr; + + len += scnprintf(buf + len, buf_len - len, + "HTT_TXBF_OFDMA_BE_STEER_STATS_TLV:\n"); + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_steer[i].be_ofdma_num_ppdu_steer) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_steer[i].be_ofdma_num_ppdu_steer); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_num_ppdu_steer = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_steer[i].be_ofdma_num_ppdu_ol) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_steer[i].be_ofdma_num_ppdu_ol); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_num_ppdu_ol = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_steer[i].be_ofdma_num_usrs_prefetch) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_steer[i].be_ofdma_num_usrs_prefetch); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_num_usrs_prefetch = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_steer[i].be_ofdma_num_usrs_sound) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_steer[i].be_ofdma_num_usrs_sound); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_num_usrs_sound = %s\n", "NONE"); + } + + null_output = 1; + for (i = 0; i < num_elements; i++) { + if (htt_stats_buf->be_steer[i].be_ofdma_num_usrs_force_sound) { + null_output = 0; + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i + 1, + htt_stats_buf->be_steer[i].be_ofdma_num_usrs_force_sound); + } + } + if (null_output) { + len += scnprintf(buf + len, buf_len - len, + "be_ofdma_num_usrs_force_sound = %s\n", "NONE"); + } + + stats_req->buf_len = len; +} + +static inline void +htt_print_dmac_reset_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_dmac_reset_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_DMAC_RESET_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "reset_count = %u\n", + htt_stats_buf->reset_count); + len += scnprintf(buf + len, buf_len - len, "reset_time_hi_ms = 0x%x\n", + htt_stats_buf->reset_time_hi_ms); + len += scnprintf(buf + len, buf_len - len, "reset_time_lo_ms = 0x%x\n", + htt_stats_buf->reset_time_lo_ms); + len += scnprintf(buf + len, buf_len - len, "disengage_time_hi_ms = 0x%x\n", + htt_stats_buf->disengage_time_hi_ms); + len += scnprintf(buf + len, buf_len - len, "disengage_time_lo_ms = 0x%x\n", + htt_stats_buf->disengage_time_lo_ms); + len += scnprintf(buf + len, buf_len - len, "engage_time_hi_ms = 0x%x\n", + htt_stats_buf->engage_time_hi_ms); + len += scnprintf(buf + len, buf_len - len, "engage_time_lo_ms = 0x%x\n", + htt_stats_buf->engage_time_lo_ms); + len += scnprintf(buf + len, buf_len - len, "disengage_count = %u\n", + htt_stats_buf->disengage_count); + len += scnprintf(buf + len, buf_len - len, "drain_dest_ring_mask = %u\n", + htt_stats_buf->drain_dest_ring_mask); + stats_req->buf_len = len; +} + +static inline void +htt_print_be_ul_ofdma_user_stats(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_be_ul_ofdma_user_stats_tlv *htt_ul_user_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + if (htt_ul_user_stats_buf->user_index == 0) { + len += scnprintf(buf + len, buf_len - len, + "HTT_RX_PDEV_BE_UL_OFDMA_USER_STAS_TLV\n"); + } + + len += scnprintf(buf + len, buf_len - len, + "be_rx_ulofdma_non_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulofdma_non_data_ppdu); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ulofdma_data_ppdu_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulofdma_data_ppdu); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ulofdma_mpdu_ok_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulofdma_mpdu_ok); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ulofdma_mpdu_fail_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulofdma_mpdu_fail); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ulofdma_non_data_nusers_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulofdma_non_data_nusers); + len += scnprintf(buf + len, buf_len - len, + "be_rx_ulofdma_data_nusers_%u = %u\n", + htt_ul_user_stats_buf->user_index, + htt_ul_user_stats_buf->be_rx_ulofdma_data_nusers); + + stats_req->buf_len = len; +} + +static inline void +htt_print_phy_tpc_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_phy_tpc_stats_tlv *htt_stats_phy_tpc_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_PHY_TPC_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : pdev_id = %u\n", + htt_stats_phy_tpc_stats_buf->pdev_id); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : tx_power_scale = %u\n", + htt_stats_phy_tpc_stats_buf->tx_power_scale); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : tx_power_scale_db = %u\n", + htt_stats_phy_tpc_stats_buf->tx_power_scale_db); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : min_negative_tx_power = %d\n", + htt_stats_phy_tpc_stats_buf->min_negative_tx_power); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : reg_ctl_domain = %u\n", + htt_stats_phy_tpc_stats_buf->reg_ctl_domain); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : twice_max_rd_power = %u\n", + htt_stats_phy_tpc_stats_buf->twice_max_rd_power); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : max_tx_power = %u\n", + htt_stats_phy_tpc_stats_buf->max_tx_power); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : home_max_tx_power = %u\n", + htt_stats_phy_tpc_stats_buf->home_max_tx_power); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : psd_power = %d\n", + htt_stats_phy_tpc_stats_buf->psd_power); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : eirp_power = %u\n", + htt_stats_phy_tpc_stats_buf->eirp_power); + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : power_type_6ghz = %u\n", + htt_stats_phy_tpc_stats_buf->power_type_6ghz); + + len += scnprintf(buf + len, buf_len - len, + "tpc_stats : max_reg_allowed_power = "); + for (i = 0; i < HTT_STATS_MAX_CHAINS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%d,", i, + htt_stats_phy_tpc_stats_buf->max_reg_allowed_power[i]); + } + + len += scnprintf(buf + len, buf_len - len, + "\ntpc_stats : max_reg_allowed_power_6g = "); + for (i = 0; i < HTT_STATS_MAX_CHAINS; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%d,", i, + htt_stats_phy_tpc_stats_buf->max_reg_allowed_power_6g[i]); + } + + len += scnprintf(buf + len, buf_len - len, + "\ntpc_stats : sub_band_cfreq = "); + for (i = 0; i < HTT_MAX_CH_PWR_INFO_SIZE; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i, + htt_stats_phy_tpc_stats_buf->sub_band_cfreq[i]); + } + + len += scnprintf(buf + len, buf_len - len, + "\ntpc_stats : sub_band_txpower = "); + for (i = 0; i < HTT_MAX_CH_PWR_INFO_SIZE; i++) { + len += scnprintf(buf + len, buf_len - len, + " %u:%u,", i, + htt_stats_phy_tpc_stats_buf->sub_band_txpower[i]); + } + + len += scnprintf(buf + len, buf_len - len, + "\n=========================================== \n"); + stats_req->buf_len = len; +} + +static const char *htt_stats_direction_abbrev(enum htt_stats_direction direction, + struct debug_htt_stats_req *stats_req) +{ + const char *direction_str = "unknown"; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + switch (direction) { + case HTT_STATS_DIRECTION_TX: + direction_str = "tx"; + break; + case HTT_STATS_DIRECTION_RX: + direction_str = "rx"; + break; + default: + len += scnprintf(buf + len, buf_len - len, + "warning: encountered unexpected HTT_STATS_DIRECTION: %d", + direction); + direction_str = "unknown"; + } + + stats_req->buf_len = len; + return direction_str; +} + +static const char *htt_stats_ppdu_type_abbrev(enum htt_stats_ppdu_type ppdu_type, + struct debug_htt_stats_req *stats_req) +{ + const char *ppdu_type_str = "unknown"; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + switch (ppdu_type) { + case HTT_STATS_PPDU_TYPE_MODE_SU: + ppdu_type_str = "su"; + break; + case HTT_STATS_PPDU_TYPE_DL_MU_MIMO: + ppdu_type_str = "dl_mu_mimo"; + break; + case HTT_STATS_PPDU_TYPE_UL_MU_MIMO: + ppdu_type_str = "ul_mu_mimo"; + break; + case HTT_STATS_PPDU_TYPE_DL_MU_OFDMA: + ppdu_type_str = "dl_mu_ofdma"; + break; + case HTT_STATS_PPDU_TYPE_UL_MU_OFDMA: + ppdu_type_str = "ul_mu_ofdma"; + break; + default: + len += scnprintf(buf + len, buf_len - len, + "warning: encountered unexpected HTT_STATS_PPDU_TYPE: %d", + ppdu_type); + } + + stats_req->buf_len = len; + return ppdu_type_str; +} + +static const char *htt_stats_pream_type_abbrev(enum htt_stats_param_type pream_type, + struct debug_htt_stats_req *stats_req) +{ + const char *pream_type_str = "unknown"; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + switch (pream_type) { + case HTT_STATS_PREAM_OFDM: + pream_type_str = "ofdm"; + break; + case HTT_STATS_PREAM_CCK: + pream_type_str = "cck"; + break; + case HTT_STATS_PREAM_HT: + pream_type_str = "ht"; + break; + case HTT_STATS_PREAM_VHT: + pream_type_str = "ac"; + break; + case HTT_STATS_PREAM_HE: + pream_type_str = "ax"; + break; + case HTT_STATS_PREAM_EHT: + pream_type_str = "be"; + break; + default: + len += scnprintf(buf + len, buf_len - len, + "warning: encountered unexpected HTT_STATS_PREAM_TYPE: %d", + pream_type); + } + + stats_req->buf_len = len; + return pream_type_str; +} + +static inline void +htt_print_puncture_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_puncture_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + const char *direction_str = NULL; + const char *preamble_str = NULL; + const char *ppdu_type_str = NULL; + + len += scnprintf(buf + len, buf_len - len, + "HTT_PDEV_PUNCTURE_STATS_TLV:\n"); + + direction_str = htt_stats_direction_abbrev(htt_stats_buf->direction, stats_req); + ppdu_type_str = htt_stats_ppdu_type_abbrev(htt_stats_buf->ppdu_type, stats_req); + preamble_str = htt_stats_pream_type_abbrev(htt_stats_buf->preamble, stats_req); + + len += scnprintf(buf + len, buf_len - len, + "mac_id = %u\n", + HTT_PDEV_PUNCTURE_STATS_MAC_ID_GET(htt_stats_buf->mac_id__word)); + + len += scnprintf(buf + len, buf_len - len, + "%s_%s_%s_last_used_pattern_mask: 0x%08x\n", + direction_str, preamble_str, ppdu_type_str, + htt_stats_buf->last_used_pattern_mask); + + for (i = 0; (i < HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT) && + (i < htt_stats_buf->subband_count); ++i) { + len += scnprintf(buf + len, buf_len - len, + "%s_%s_%s_num_subbands_used_cnt_%02d: %u\n", + direction_str, preamble_str, ppdu_type_str, + i + 1, htt_stats_buf->num_subbands_used_cnt[i]); + } + stats_req->buf_len = len; +} + +static inline void +htt_print_ml_peer_details_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_ml_peer_details_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_ML_PEER_DETAILS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, + "========================\n"); + + len += scnprintf(buf + len, buf_len - len, + "remote_mld_mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n", + (htt_stats_buf->remote_mld_mac_addr.mac_addr_l32 & 0xFF), + (htt_stats_buf->remote_mld_mac_addr.mac_addr_l32 & 0xFF00) >> 8, + (htt_stats_buf->remote_mld_mac_addr.mac_addr_l32 & 0xFF0000) >> 16, + (htt_stats_buf->remote_mld_mac_addr.mac_addr_l32 & 0xFF000000) >> 24, + (htt_stats_buf->remote_mld_mac_addr.mac_addr_h16 & 0xFF), + (htt_stats_buf->remote_mld_mac_addr.mac_addr_h16 & 0xFF00) >> 8); + + len += scnprintf(buf + len, buf_len - len, + "ml_peer_flags = 0x%x\n", + htt_stats_buf->ml_peer_flags); + + len += scnprintf(buf + len, buf_len - len, + "num_links = %u\n", + HTT_ML_PEER_DETAILS_NUM_LINKS_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "ml_peer_id = %u\n", + HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "primary_link_idx = %u\n", + HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "primary_chip_id = %u\n", + HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "link_init_count = %u\n", + HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "non_str = %u\n", + HTT_ML_PEER_DETAILS_NON_STR_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "emlsr = %u\n", + HTT_ML_PEER_DETAILS_EMLSR_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "is_stako = %u\n", + HTT_ML_PEER_DETAILS_IS_STA_KO_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "num_local_links = %u\n", + HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "allocated = %u\n", + HTT_ML_PEER_DETAILS_ALLOCATED_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "participating_chips_bitmap = 0x%x\n", + HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET( + htt_stats_buf->msg_dword_2)); + + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_ml_peer_ext_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_ml_peer_ext_details_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_ML_PEER_EXT_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "====================\n"); + len += scnprintf(buf + len, buf_len - len, + "peer_assoc_ipc_recvd = %u\n", + HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET( + htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "sched_peer_delete_recvd = %u\n", + HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET( + htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "mld_ast_index = %u\n", + HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(htt_stats_buf->msg_dword_1)); + + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_ml_link_info_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_ml_link_info_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_ML_LINK_INFO_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "=====================\n"); + len += scnprintf(buf + len, buf_len - len, + "valid = %u\n", + HTT_ML_LINK_INFO_VALID_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "active = %u\n", + HTT_ML_LINK_INFO_ACTIVE_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "primary = %u\n", + HTT_ML_LINK_INFO_PRIMARY_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "assoc_link = %u\n", + HTT_ML_LINK_INFO_ASSOC_LINK_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "chip_id = %u\n", + HTT_ML_LINK_INFO_CHIP_ID_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "ieee_link_id = %u\n", + HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "hw_link_id = %u\n", + HTT_ML_LINK_INFO_HW_LINK_ID_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "logical_link_id = %u\n", + HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "master_link = %u\n", + HTT_ML_LINK_INFO_MASTER_LINK_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "anchor_link = %u\n", + HTT_ML_LINK_INFO_ANCHOR_LINK_GET(htt_stats_buf->msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, + "initialized = %u\n", + HTT_ML_LINK_INFO_INITIALIZED_GET(htt_stats_buf->msg_dword_1)); + + len += scnprintf(buf + len, buf_len - len, + "sw_peer_id = %u\n", + HTT_ML_LINK_INFO_SW_PEER_ID_GET(htt_stats_buf->msg_dword_2)); + len += scnprintf(buf + len, buf_len - len, + "vdev_id = %u\n", + HTT_ML_LINK_INFO_VDEV_ID_GET(htt_stats_buf->msg_dword_2)); + + len += scnprintf(buf + len, buf_len - len, + "primary_tid_mask = 0x%x\n", + htt_stats_buf->primary_tid_mask); + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_ppdu_dur_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_ppdu_dur_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 i, j; + u16 index = 0; + char data[HTT_MAX_STRING_LEN] = {0}; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_PPDU_DUR_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "pdev_up_time_us_low = %u\n", + htt_stats_buf->pdev_up_time_us_low); + len += scnprintf(buf + len, buf_len - len, "pdev_up_time_us_high = %u\n", + htt_stats_buf->pdev_up_time_us_high); + len += scnprintf(buf + len, buf_len - len, "tx_success_time_us_low = %u\n", + htt_stats_buf->tx_success_time_us_low); + len += scnprintf(buf + len, buf_len - len, "tx_success_time_us_high = %u\n", + htt_stats_buf->tx_success_time_us_high); + len += scnprintf(buf + len, buf_len - len, "tx_fail_time_us_low = %u\n", + htt_stats_buf->tx_fail_time_us_low); + len += scnprintf(buf + len, buf_len - len, "tx_fail_time_us_high = %u\n", + htt_stats_buf->tx_fail_time_us_high); + + /* Split the buffer store mechanism into two to avoid data buffer overflow + */ + for (i = 0; i < HTT_PDEV_STATS_PPDU_DUR_HIST_BINS >> 1; i++) { + index += snprintf(&data[index], + HTT_MAX_STRING_LEN - index, + " %u-%u : %u,", + i * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + (i + 1) * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + htt_stats_buf->tx_ppdu_dur_hist[i]); + } + + len += scnprintf(buf + len, buf_len - len, "tx_ppdu_dur_hist_us_0 = %s\n", data); + memset(data, '\0', sizeof(char) * HTT_MAX_STRING_LEN); + index = 0; + + for (j = i; j < HTT_PDEV_STATS_PPDU_DUR_HIST_BINS; j++) { + index += snprintf(&data[index], + HTT_MAX_STRING_LEN - index, + " %u-%u : %u,", + j * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + (j + 1) * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + htt_stats_buf->tx_ppdu_dur_hist[j]); + } + + len += scnprintf(buf + len, buf_len - len, "tx_ppdu_dur_hist_us_1 = %s\n", data); + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_rx_pdev_ppdu_dur_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_rx_pdev_ppdu_dur_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 i, j; + u16 index = 0; + char data[HTT_MAX_STRING_LEN] = {0}; + + len += scnprintf(buf + len, buf_len - len, "HTT_RX_PDEV_PPDU_DUR_STATS_TLV:\n"); + + /* Split the buffer store mechanism into two to avoid data buffer overflow + */ + for (i = 0; i < HTT_PDEV_STATS_PPDU_DUR_HIST_BINS >> 1; i++) { + index += snprintf(&data[index], + HTT_MAX_STRING_LEN - index, + " %u-%u : %u,", + i * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + (i + 1) * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + htt_stats_buf->rx_ppdu_dur_hist[i]); + } + + len += scnprintf(buf + len, buf_len - len, "rx_ppdu_dur_hist_us_0 = %s\n", data); + memset(data, '\0', sizeof(char) * HTT_MAX_STRING_LEN); + index = 0; + + for (j = i; j < HTT_PDEV_STATS_PPDU_DUR_HIST_BINS; j++) { + index += snprintf(&data[index], + HTT_MAX_STRING_LEN - index, + " %u-%u : %u,", + j * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + (j + 1) * HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US, + htt_stats_buf->rx_ppdu_dur_hist[j]); + } + + len += scnprintf(buf + len, buf_len - len, "rx_ppdu_dur_hist_us_1 = %s\n", data); + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_sched_algo_ofdma_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_sched_algo_ofdma_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rate_based_dlofdma_enabled_count, + "rate_based_dlofdma_enabled_count", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rate_based_dlofdma_disabled_count, + "rate_based_dlofdma_disabled_count", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rate_based_dlofdma_probing_count, + "rate_based_dlofdma_probing_count", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rate_based_dlofdma_monitoring_count, + "rate_based_dlofdma_monitoring_count", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->chan_acc_lat_based_dlofdma_enabled_count, + "chan_acc_lat_based_dlofdma_enabled_count", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->chan_acc_lat_based_dlofdma_disabled_count, + "chan_acc_lat_based_dlofdma_disabled_count", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->chan_acc_lat_based_dlofdma_monitoring_count, + "chan_acc_lat_based_dlofdma_monitoring_count", + HTT_NUM_AC_WMM, "\n"); + + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_latency_prof_cal_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_latency_prof_cal_stats_tlv *htt_stats_buf = tag_buf; + char latency_prof_stat_name[HTT_STATS_MAX_PROF_STATS_NAME_LEN + 1] = {0}; + u32 i, j; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_STATS_LATENCY_PROF_CAL_TLV:\n"); + for (i = 1; i < HTT_STATS_MAX_PROF_CAL; i++) { + memcpy(latency_prof_stat_name, + (htt_stats_buf->latency_prof_name[i]), + HTT_STATS_MAX_PROF_STATS_NAME_LEN); + + len += scnprintf(buf + len, buf_len - len, + "%-32s", + htt_stats_buf->latency_prof_name[i]); + len += scnprintf(buf + len, buf_len - len, + "|%9s|%8s|%8s|%8s|%8s|%8s|%10s|%14s|%8s|%8s|%8s|\n", + "cal_index", "cnt", "min", "max", "last", "tot", + "hist_intvl", "hist", "pf_last", "pf_tot", + "pf_max"); + + for (j = 0; j < htt_stats_buf->CalCnt[i]; j++) { + len += scnprintf(buf + len, buf_len - len, + "|%9u|%8u|%8u|%8u|%8u|%8u|%10u|%4u:%4u:%4u|%8u|%8u|%8u|\n", + htt_stats_buf->enabledCalIdx[i][j], + htt_stats_buf->cnt[i][j], + htt_stats_buf->min[i][j], + htt_stats_buf->max[i][j], + htt_stats_buf->last[i][j], + htt_stats_buf->tot[i][j], + htt_stats_buf->hist_intvl[i][j], + htt_stats_buf->hist[i][j][0], + htt_stats_buf->hist[i][j][1], + htt_stats_buf->hist[i][j][2], + htt_stats_buf->pf_last[i][j], + htt_stats_buf->pf_tot[i][j], + htt_stats_buf->pf_max[i][j]); + } + } + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_ap_edca_params_stats_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_ap_edca_params_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "\nAP EDCA PARAMETERS FOR UL MUMIMO:\n"); + for (i = 0; i < HTT_NUM_AC_WMM; i++) { + len += scnprintf(buf + len, buf_len - len, "ul_mumimo_less_aggressive[%u] = %u\n", + i, htt_stats_buf->ul_mumimo_less_aggressive[i]); + len += scnprintf(buf + len, buf_len - len, "ul_mumimo_medium_aggressive[%u] = %u\n", + i, htt_stats_buf->ul_mumimo_medium_aggressive[i]); + len += scnprintf(buf + len, buf_len - len, "ul_mumimo_highly_aggressive[%u] = %u\n", + i, htt_stats_buf->ul_mumimo_highly_aggressive[i]); + len += scnprintf(buf + len, buf_len - len, "ul_mumimo_default_relaxed[%u] = %u\n", + i, htt_stats_buf->ul_mumimo_default_relaxed[i]); + } + + len += scnprintf(buf + len, buf_len - len, "AP EDCA PARAMETERS FOR UL OFDMA:\n"); + for (i = 0; i < HTT_NUM_AC_WMM; i++) { + len += scnprintf(buf + len, buf_len - len, "ul_muofdma_less_aggressive[%u] = %u\n", + i, htt_stats_buf->ul_muofdma_less_aggressive[i]); + len += scnprintf(buf + len, buf_len - len, "ul_muofdma_medium_aggressive[%u] = %u\n", + i, htt_stats_buf->ul_muofdma_medium_aggressive[i]); + len += scnprintf(buf + len, buf_len - len, "ul_muofdma_highly_aggressive[%u] = %u\n", + i, htt_stats_buf->ul_muofdma_highly_aggressive[i]); + len += scnprintf(buf + len, buf_len - len, "ul_muofdma_default_relaxed[%u] = %u\n", + i, htt_stats_buf->ul_muofdma_default_relaxed[i]); + } + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_ax_steer_mpdu_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_ax_steer_mpdu_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_AX_STEER_MPDU_STATS_TLV:\n"); + + len += scnprintf(buf + len, buf_len - len, "rbo_steer_mpdus_tried = %u\n", + htt_stats_buf->ax_ofdma_rbo_steer_mpdus_tried); + len += scnprintf(buf + len, buf_len - len, "rbo_steer_mpdus_failed = %u\n", + htt_stats_buf->ax_ofdma_rbo_steer_mpdus_failed); + len += scnprintf(buf + len, buf_len - len, "sifs_steer_mpdus_tried = %u\n", + htt_stats_buf->ax_ofdma_sifs_steer_mpdus_tried); + len += scnprintf(buf + len, buf_len - len, "sifs_steer_mpdus_failed = %u\n", + htt_stats_buf->ax_ofdma_sifs_steer_mpdus_failed); + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_txbf_ofdma_be_steer_mpdu_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_txbf_ofdma_be_steer_mpdu_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_TXBF_OFDMA_BE_STEER_MPDU_STATS_TLV:\n"); + + len += scnprintf(buf + len, buf_len - len, "rbo_steer_mpdus_tried = %u\n", + htt_stats_buf->be_ofdma_rbo_steer_mpdus_tried); + len += scnprintf(buf + len, buf_len - len, "rbo_steer_mpdus_failed = %u\n", + htt_stats_buf->be_ofdma_rbo_steer_mpdus_failed); + len += scnprintf(buf + len, buf_len - len, "sifs_steer_mpdus_tried = %u\n", + htt_stats_buf->be_ofdma_sifs_steer_mpdus_tried); + len += scnprintf(buf + len, buf_len - len, "sifs_steer_mpdus_failed = %u\n", + htt_stats_buf->be_ofdma_sifs_steer_mpdus_failed); + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_peer_ax_ofdma_stats(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_peer_ax_ofdma_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_PEER_AX_OFDMA_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "peer_id = %u\n", + htt_stats_buf->peer_id); + len += scnprintf(buf + len, buf_len - len, "ax_basic_trig_count = %u\n", + htt_stats_buf->ax_basic_trig_count); + len += scnprintf(buf + len, buf_len - len, "ax_basic_trig_err = %u\n", + htt_stats_buf->ax_basic_trig_err); + len += scnprintf(buf + len, buf_len - len, "ax_bsr_trig_count = %u\n", + htt_stats_buf->ax_bsr_trig_count); + len += scnprintf(buf + len, buf_len - len, "ax_bsr_trig_err = %u\n", + htt_stats_buf->ax_bsr_trig_err); + len += scnprintf(buf + len, buf_len - len, "ax_mu_bar_trig_count = %u\n", + htt_stats_buf->ax_mu_bar_trig_count); + len += scnprintf(buf + len, buf_len - len, "ax_mu_bar_trig_err = %u\n", + htt_stats_buf->ax_mu_bar_trig_err); + len += scnprintf(buf + len, buf_len - len, "ax_basic_trig_with_per = %u\n", + htt_stats_buf->ax_basic_trig_with_per); + len += scnprintf(buf + len, buf_len - len, "ax_bsr_trig_with_per = %u\n", + htt_stats_buf->ax_bsr_trig_with_per); + len += scnprintf(buf + len, buf_len - len, "ax_mu_bar_trig_with_per = %u\n", + htt_stats_buf->ax_mu_bar_trig_with_per); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->is_airtime_large_for_dl_ofdma, + "is_airtime_large_for_dl_ofdma", 2, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->is_airtime_large_for_ul_ofdma, + "is_airtime_large_for_ul_ofdma", 2, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->last_updated_dl_qdepth, + "last_updated_dl_qdepth", HTT_NUM_AC_WMM, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->last_updated_ul_qdepth, + "last_updated_ul_qdepth", HTT_NUM_AC_WMM, "\n"); + + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_mu_edca_params_stats_tlv_v(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_mu_edca_params_stats_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char *edca_buf = NULL; + + edca_buf = kmalloc(HTT_MAX_STRING_LEN, GFP_ATOMIC); + if (!edca_buf) + goto fail; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_MU_EDCA_PARAMS_STATS_TLV:\n"); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->relaxed_mu_edca, + "irelaxed_mu_edca", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->mumimo_aggressive_mu_edca, + "mumimo_aggressive_mu_edca", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->muofdma_relaxed_mu_edca, + "muofdma_relaxed_mu_edca", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->latency_mu_edca, + "latency_mu_edca", + HTT_NUM_AC_WMM, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->psd_boost_mu_edca, + "psd_boost_mu_edca", + HTT_NUM_AC_WMM, "\n"); + + len += scnprintf(buf + len, buf_len - len, + "=========================================== \n"); + stats_req->buf_len = len; +fail: + kfree(edca_buf); +} + +static inline void +htt_print_odd_pdev_mandatory_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_odd_mandatory_pdev_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_ODD_PDEV_MANDATORY_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "hw_queued = %u\n", + htt_stats_buf->hw_queued); + len += scnprintf(buf + len, buf_len - len, "hw_reaped = %u\n", + htt_stats_buf->hw_reaped); + len += scnprintf(buf + len, buf_len - len, "hw_paused = %u\n", + htt_stats_buf->hw_paused); + len += scnprintf(buf + len, buf_len - len, "hw_filt = %u\n", + htt_stats_buf->hw_filt); + len += scnprintf(buf + len, buf_len - len, "seq_posted = %u\n", + htt_stats_buf->seq_posted); + len += scnprintf(buf + len, buf_len - len, "seq_completed = %u\n", + htt_stats_buf->seq_completed); + len += scnprintf(buf + len, buf_len - len, "underrun = %u\n", + htt_stats_buf->underrun); + len += scnprintf(buf + len, buf_len - len, "hw_flush = %u\n", + htt_stats_buf->hw_flush); + len += scnprintf(buf + len, buf_len - len, "next_seq_posted_dsr = %u\n", + htt_stats_buf->next_seq_posted_dsr); + len += scnprintf(buf + len, buf_len - len, "seq_posted_isr = %u\n", + htt_stats_buf->seq_posted_isr); + len += scnprintf(buf + len, buf_len - len, "mpdu_cnt_fcs_ok = %u\n", + htt_stats_buf->mpdu_cnt_fcs_ok); + len += scnprintf(buf + len, buf_len - len, "mpdu_cnt_fcs_err = %u\n", + htt_stats_buf->mpdu_cnt_fcs_err); + len += scnprintf(buf + len, buf_len - len, "msdu_count_tqm = %u\n", + htt_stats_buf->msdu_count_tqm); + len += scnprintf(buf + len, buf_len - len, "mpdu_count_tqm = %u\n", + htt_stats_buf->mpdu_count_tqm); + len += scnprintf(buf + len, buf_len - len, "mpdus_ack_failed = %u\n", + htt_stats_buf->mpdus_ack_failed); + len += scnprintf(buf + len, buf_len - len, "num_data_ppdus_tried_ota = %u\n", + htt_stats_buf->num_data_ppdus_tried_ota); + len += scnprintf(buf + len, buf_len - len, "ppdu_ok = %u\n", + htt_stats_buf->ppdu_ok); + len += scnprintf(buf + len, buf_len - len, "num_total_ppdus_tried_ota = %u\n", + htt_stats_buf->num_total_ppdus_tried_ota); + len += scnprintf(buf + len, buf_len - len, "thermal_suspend_cnt = %u\n", + htt_stats_buf->thermal_suspend_cnt); + len += scnprintf(buf + len, buf_len - len, "dfs_suspend_cnt = %u\n", + htt_stats_buf->dfs_suspend_cnt); + len += scnprintf(buf + len, buf_len - len, "tx_abort_suspend_cnt = %u\n", + htt_stats_buf->tx_abort_suspend_cnt); + len += scnprintf(buf + len, buf_len - len, "suspended_txq_mask = %u\n", + htt_stats_buf->suspended_txq_mask); + len += scnprintf(buf + len, buf_len - len, "last_suspend_reason = %u\n", + htt_stats_buf->last_suspend_reason); + len += scnprintf(buf + len, buf_len - len, "seq_failed_queueing = %u\n", + htt_stats_buf->seq_failed_queueing); + len += scnprintf(buf + len, buf_len - len, "seq_restarted = %u\n", + htt_stats_buf->seq_restarted); + len += scnprintf(buf + len, buf_len - len, "seq_txop_repost_stop = %u\n", + htt_stats_buf->seq_txop_repost_stop); + len += scnprintf(buf + len, buf_len - len, "next_seq_cancel = %u\n", + htt_stats_buf->next_seq_cancel); + len += scnprintf(buf + len, buf_len - len, "seq_min_msdu_repost_stop = %u\n", + htt_stats_buf->seq_min_msdu_repost_stop); + len += scnprintf(buf + len, buf_len - len, "total_phy_err_cnt = %u\n", + htt_stats_buf->total_phy_err_cnt); + len += scnprintf(buf + len, buf_len - len, "ppdu_recvd = %u\n", + htt_stats_buf->ppdu_recvd); + len += scnprintf(buf + len, buf_len - len, "tcp_msdu_cnt = %u\n", + htt_stats_buf->tcp_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, "tcp_ack_msdu_cnt = %u\n", + htt_stats_buf->tcp_ack_msdu_cnt); + len += scnprintf(buf + len, buf_len - len, "udp_msdu_cnt = %u \n", + htt_stats_buf->udp_msdu_cnt); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->fw_tx_mgmt_subtype, + "fw_tx_mgmt_subtype", + HTT_STATS_SUBTYPE_MAX, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->fw_rx_mgmt_subtype, + "fw_rx_mgmt_subtype", + HTT_STATS_SUBTYPE_MAX, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->fw_ring_mpdu_err, + "fw_ring_mpdu_err", + HTT_STATS_SUBTYPE_MAX, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->fw_rx_mgmt_subtype, + "fw_rx_mgmt_subtype", + HTT_RX_STATS_RXDMA_MAX_ERR, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->urrn_stats, + "urrn_stats", + HTT_TX_PDEV_MAX_URRN_STATS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->sifs_status, + "sifs_status", + HTT_TX_PDEV_MAX_SIFS_BURST_STATS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->fw_rx_mgmt_subtype, + "sifs_hist_status", + HTT_TX_PDEV_SIFS_BURST_HIST_STATS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "rx_suspend_cnt = %u\n", + htt_stats_buf->rx_suspend_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_suspend_fail_cnt = %u\n", + htt_stats_buf->rx_suspend_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_resume_cnt = %u\n", + htt_stats_buf->rx_resume_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_resume_fail_cnt = %u \n", + htt_stats_buf->rx_resume_fail_cnt); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->hwq_beacon_cmd_result, + "hwq_beacon_cmd_result", + HTT_TX_HWQ_MAX_CMD_RESULT_STATS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->hwq_voice_cmd_result, + "hwq_voice_cmd_result", + HTT_TX_HWQ_MAX_CMD_RESULT_STATS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->hwq_video_cmd_result, + "hwq_video_cmd_result", + HTT_TX_HWQ_MAX_CMD_RESULT_STATS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->hwq_best_effort_cmd_result, + "hwq_best_effort_cmd_result", + HTT_TX_HWQ_MAX_CMD_RESULT_STATS, "\n"); + + len += scnprintf(buf + len, buf_len - len, "hwq_beacon_mpdu_tried_cnt = %u\n", + htt_stats_buf->hwq_beacon_mpdu_tried_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_voice_mpdu_tried_cnt = %u\n", + htt_stats_buf->hwq_voice_mpdu_tried_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_video_mpdu_tried_cnt = %u\n", + htt_stats_buf->hwq_video_mpdu_tried_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_best_effort_mpdu_tried_cnt = %u\n", + htt_stats_buf->hwq_best_effort_mpdu_tried_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_beacon_mpdu_queued_cnt = %u\n", + htt_stats_buf->hwq_beacon_mpdu_queued_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_voice_mpdu_queued_cnt = %u\n", + htt_stats_buf->hwq_voice_mpdu_queued_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_video_mpdu_queued_cnt = %u\n", + htt_stats_buf->hwq_video_mpdu_queued_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_best_effort_mpdu_queued_cnt = %u\n", + htt_stats_buf->hwq_best_effort_mpdu_queued_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_beacon_mpdu_ack_fail_cnt = %u\n", + htt_stats_buf->hwq_beacon_mpdu_ack_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_voice_mpdu_ack_fail_cnt = %u\n", + htt_stats_buf->hwq_voice_mpdu_ack_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_video_mpdu_ack_fail_cnt = %u\n", + htt_stats_buf->hwq_video_mpdu_ack_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "hwq_best_effort_mpdu_ack_fail_cnt = %u\n", + htt_stats_buf->hwq_best_effort_mpdu_ack_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "pdev_resets = %u\n", + htt_stats_buf->pdev_resets); + len += scnprintf(buf + len, buf_len - len, "phy_warm_reset = %u\n", + htt_stats_buf->phy_warm_reset); + len += scnprintf(buf + len, buf_len - len, "hwsch_reset_count = %u\n", + htt_stats_buf->hwsch_reset_count); + len += scnprintf(buf + len, buf_len - len, "phy_warm_reset_ucode_trig = %u\n", + htt_stats_buf->phy_warm_reset_ucode_trig); + len += scnprintf(buf + len, buf_len - len, "mac_cold_reset = %u\n", + htt_stats_buf->mac_cold_reset); + len += scnprintf(buf + len, buf_len - len, "mac_warm_reset = %u\n", + htt_stats_buf->mac_warm_reset); + len += scnprintf(buf + len, buf_len - len, "mac_warm_reset_restore_cal = %u\n", + htt_stats_buf->mac_warm_reset_restore_cal); + len += scnprintf(buf + len, buf_len - len, "phy_warm_reset_m3_ssr = %u\n", + htt_stats_buf->phy_warm_reset_m3_ssr); + len += scnprintf(buf + len, buf_len - len, "fw_rx_rings_reset = %u\n", + htt_stats_buf->fw_rx_rings_reset); + len += scnprintf(buf + len, buf_len - len, "tx_flush = %u\n", + htt_stats_buf->tx_flush); + len += scnprintf(buf + len, buf_len - len, "hwsch_dev_reset_war = %u\n", + htt_stats_buf->hwsch_dev_reset_war); + len += scnprintf(buf + len, buf_len - len, "mac_cold_reset_restore_cal = %u\n", + htt_stats_buf->mac_cold_reset_restore_cal); + len += scnprintf(buf + len, buf_len - len, "mac_only_reset = %u\n", + htt_stats_buf->mac_only_reset); + len += scnprintf(buf + len, buf_len - len, "mac_sfm_reset = %u\n", + htt_stats_buf->mac_sfm_reset); + len += scnprintf(buf + len, buf_len - len, "rx_ldpc = %u\n", + htt_stats_buf->rx_ldpc); + len += scnprintf(buf + len, buf_len - len, "tx_ldpc = %u \n", + htt_stats_buf->tx_ldpc); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->gen_mpdu_end_reason, + "gen_mpdu_end_reason", + HTT_TX_TQM_MAX_GEN_MPDU_END_REASON, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->list_mpdu_end_reason, + "list_mpdu_end_reason", + HTT_TX_TQM_MAX_GEN_MPDU_END_REASON, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->tx_mcs, + "tx_mcs", + (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS), "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->tx_nss, + "tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->tx_bw, + "tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->half_tx_bw, + "half_tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->quarter_tx_bw, + "quarter_tx_bw", + HTT_TX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->tx_su_punctured_mode, + "tx_su_punctured_mode", + HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rx_mcs, + "rx_mcs", + (HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS), "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rx_nss, + "rx_nss", + HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rx_bw, + "rx_bw", + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->rx_stbc, + "rx_stbc", + (HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS), "\n"); + + len += scnprintf(buf + len, buf_len - len, "rts_cnt = %u\n", + htt_stats_buf->rts_cnt); + len += scnprintf(buf + len, buf_len - len, "rts_success = %u\n", + htt_stats_buf->rts_success); + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_pdev_mbssid_ctrl_frame_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_mbssid_ctrl_frame_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + HTT_STATS_CMN_MAC_ID_GET(htt_stats_buf->mac_id__word)); + + len += scnprintf(buf + len, buf_len - len, "basic_trigger_across_bss_count = %u\n", + htt_stats_buf->basic_trigger_across_bss); + len += scnprintf(buf + len, buf_len - len, "basic_trigger_within_bss_count = %u\n", + htt_stats_buf->basic_trigger_within_bss); + len += scnprintf(buf + len, buf_len - len, "bsr_trigger_across_bss_count = %u\n", + htt_stats_buf->bsr_trigger_across_bss); + len += scnprintf(buf + len, buf_len - len, "bsr_trigger_within_bss_count = %u\n", + htt_stats_buf->bsr_trigger_within_bss); + len += scnprintf(buf + len, buf_len - len, "MU_RTS_across_bss_count = %u\n", + htt_stats_buf->mu_rts_across_bss); + len += scnprintf(buf + len, buf_len - len, "MU_RTS_within_bss_count = %u\n", + htt_stats_buf->mu_rts_within_bss); + len += scnprintf(buf + len, buf_len - len, "UL_MUMIMO_trigger_across_bss_count = %u\n", + htt_stats_buf->ul_mumimo_trigger_across_bss); + len += scnprintf(buf + len, buf_len - len, "UL_MUMIMO_trigger_within_bss_count = %u\n", + htt_stats_buf->ul_mumimo_trigger_within_bss); + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_mlo_abort_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_mlo_abort_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = tag_len >> 2; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_STATS_MLO_ABORT_TLV_V:\n"); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->mlo_abort_cnt, + "mlo_abort_cnt", + num_elements, "\n"); + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + stats_req->buf_len = len; +} + +static inline void +htt_print_tx_pdev_stats_mlo_txop_abort_tlv_v(const void *tag_buf, + u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_pdev_stats_mlo_txop_abort_tlv_v *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 num_elements = tag_len >> 2; + + len += scnprintf(buf + len, buf_len - len, "HTT_TX_PDEV_STATS_MLO_TXOP_ABORT_TLV_V:\n"); + PRINT_ARRAY_TO_BUF(buf, len, + htt_stats_buf->mlo_txop_abort_cnt, + "mlo_txop_abort_cnt", + num_elements, "\n"); + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + stats_req->buf_len = len; +} + +static inline void htt_print_phy_counters_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_phy_counters_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_PHY_COUNTERS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "rx_ofdma_timing_err_cnt = %u\n", + htt_stats_buf->rx_ofdma_timing_err_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_cck_fail_cnt = %u\n", + htt_stats_buf->rx_cck_fail_cnt); + len += scnprintf(buf + len, buf_len - len, "mactx_abort_cnt = %u\n", + htt_stats_buf->mactx_abort_cnt); + len += scnprintf(buf + len, buf_len - len, "macrx_abort_cnt = %u\n", + htt_stats_buf->macrx_abort_cnt); + len += scnprintf(buf + len, buf_len - len, "phytx_abort_cnt = %u\n", + htt_stats_buf->phytx_abort_cnt); + len += scnprintf(buf + len, buf_len - len, "phyrx_abort_cnt = %u\n", + htt_stats_buf->phyrx_abort_cnt); + len += scnprintf(buf + len, buf_len - len, "phyrx_defer_abort_cnt = %u\n", + htt_stats_buf->phyrx_defer_abort_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_gain_adj_lstf_event_cnt = %u\n", + htt_stats_buf->rx_gain_adj_lstf_event_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_gain_adj_non_legacy_cnt = %u\n", + htt_stats_buf->rx_gain_adj_non_legacy_cnt); + + for (i = 0; i < HTT_MAX_RX_PKT_CNT; i++) + len += scnprintf(buf + len, buf_len - len, "rx_pkt_cnt[%d] = %u\n", + i, htt_stats_buf->rx_pkt_cnt[i]); + + for (i = 0; i < HTT_MAX_RX_PKT_CRC_PASS_CNT; i++) + len += scnprintf(buf + len, buf_len - len, + "rx_pkt_crc_pass_cnt[%d] = %u\n", + i, htt_stats_buf->rx_pkt_crc_pass_cnt[i]); + + for (i = 0; i < HTT_MAX_PER_BLK_ERR_CNT; i++) + len += scnprintf(buf + len, buf_len - len, + "per_blk_err_cnt[%d] = %u\n", + i, htt_stats_buf->per_blk_err_cnt[i]); + + for (i = 0; i < HTT_MAX_RX_OTA_ERR_CNT; i++) + len += scnprintf(buf + len, buf_len - len, + "rx_ota_err_cnt[%d] = %u\n", + i, htt_stats_buf->rx_ota_err_cnt[i]); + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_phy_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_phy_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_PHY_STATS_TLV:\n"); + for (i = 0; i < HTT_STATS_MAX_CHAINS; i++) + len += scnprintf(buf + len, buf_len - len, "bdf_nf_chain[%d] = %d\n", + i, htt_stats_buf->nf_chain[i]); + + for (i = 0; i < HTT_STATS_MAX_CHAINS; i++) + len += scnprintf(buf + len, buf_len - len, "runtime_nf_chain[%d] = %d\n", + i, htt_stats_buf->runtime_nf_chain[i]); + + len += scnprintf(buf + len, buf_len - len, "false_radar_cnt = %u / %u (mins)\n", + htt_stats_buf->false_radar_cnt, + htt_stats_buf->fw_run_time); + len += scnprintf(buf + len, buf_len - len, "radar_cs_cnt = %u\n", + htt_stats_buf->radar_cs_cnt); + len += scnprintf(buf + len, buf_len - len, "ani_level = %d\n", + htt_stats_buf->ani_level); + + len += scnprintf(buf + len, buf_len - len, "current operating bw = %u\n", + htt_stats_buf->current_operating_width); + len += scnprintf(buf + len, buf_len - len, "current device bw = %u\n", + htt_stats_buf->current_device_width); + len += scnprintf(buf + len, buf_len - len, "last radar type = %u\n", + htt_stats_buf->last_radar_type); + len += scnprintf(buf + len, buf_len - len, "dfs regulatory domain = %u\n", + htt_stats_buf->dfs_reg_domain); + len += scnprintf(buf + len, buf_len - len, "radar mask bit = %u\n", + htt_stats_buf->radar_mask_bit); + len += scnprintf(buf + len, buf_len - len, "radar rssi = %d\n", + htt_stats_buf->radar_rssi); + len += scnprintf(buf + len, buf_len - len, "radar dfs flags = %u\n", + htt_stats_buf->radar_dfs_flags); + len += scnprintf(buf + len, buf_len - len, "operating center freq = %u\n", + htt_stats_buf->band_center_frequency_operating); + len += scnprintf(buf + len, buf_len - len, "device center freq = %u\n", + htt_stats_buf->band_center_frequency_device); + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_phy_reset_counters_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_phy_reset_counters_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_PHY_RESET_COUNTERS_TLV:\n"); + + len += scnprintf(buf + len, buf_len - len, "reset_counts : pdev_id = %u\n", + htt_stats_buf->pdev_id); + len += scnprintf(buf + len, buf_len - len, + "reset_counts : cf_active_low_fail_cnt = %u\n", + htt_stats_buf->cf_active_low_fail_cnt); + len += scnprintf(buf + len, buf_len - len, + "reset_counts : cf_active_low_pass_cnt = %u\n", + htt_stats_buf->cf_active_low_pass_cnt); + len += scnprintf(buf + len, buf_len - len, + "reset_counts : phy_off_through_vreg_cnt = %u\n", + htt_stats_buf->phy_off_through_vreg_cnt); + len += scnprintf(buf + len, buf_len - len, + "reset_counts : force_calibration_cnt = %u\n", + htt_stats_buf->force_calibration_cnt); + len += scnprintf(buf + len, buf_len - len, + "reset_counts : rf_mode_switch_phy_off_cnt = %u\n", + htt_stats_buf->rf_mode_switch_phy_off_cnt); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_phy_reset_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_phy_reset_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_PHY_RESET_STATS_TLV:\n"); + + len += scnprintf(buf + len, buf_len - len, "reset_stats : pdev_id = %u\n", + htt_stats_buf->pdev_id); + len += scnprintf(buf + len, buf_len - len, "reset_stats : chan_mhz = %u\n", + htt_stats_buf->chan_mhz); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : chan_band_center_freq1 = %u\n", + htt_stats_buf->chan_band_center_freq1); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : chan_band_center_freq2 = %u\n", + htt_stats_buf->chan_band_center_freq2); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : chan_phy_mode = %u\n", + htt_stats_buf->chan_phy_mode); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : chan_flags = 0x%0x\n", + htt_stats_buf->chan_flags); + len += scnprintf(buf + len, buf_len - len, "reset_stats : chan_num = %u\n", + htt_stats_buf->chan_num); + len += scnprintf(buf + len, buf_len - len, "reset_stats : reset_cause = 0x%0x\n", + htt_stats_buf->reset_cause); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : prev_reset_cause = 0x%0x\n", + htt_stats_buf->prev_reset_cause); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phy_warm_reset_src = 0x%0x\n", + htt_stats_buf->phy_warm_reset_src); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : rx_gain_tbl_mode = %d\n", + htt_stats_buf->rx_gain_tbl_mode); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : xbar_val = 0x%0x\n", + htt_stats_buf->xbar_val); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : force_calibration = %u\n", + htt_stats_buf->force_calibration); + len += scnprintf(buf + len, buf_len - len, "reset_stats : phyrf_mode = %u\n", + htt_stats_buf->phyrf_mode); + len += scnprintf(buf + len, buf_len - len, "reset_stats : phy_homechan = %u\n", + htt_stats_buf->phy_homechan); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phy_tx_ch_mask = 0x%0x\n", + htt_stats_buf->phy_tx_ch_mask); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phy_rx_ch_mask = 0x%0x\n", + htt_stats_buf->phy_rx_ch_mask); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phybb_ini_mask = 0x%0x\n", + htt_stats_buf->phybb_ini_mask); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phyrf_ini_mask = 0x%0x\n", + htt_stats_buf->phyrf_ini_mask); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phy_dfs_en_mask = 0x%0x\n", + htt_stats_buf->phy_dfs_en_mask); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phy_sscan_en_mask = 0x%0x\n", + htt_stats_buf->phy_sscan_en_mask); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phy_synth_sel_mask = 0x%0x\n", + htt_stats_buf->phy_synth_sel_mask); + len += scnprintf(buf + len, buf_len - len, "reset_stats : phy_adfs_freq = %u\n", + htt_stats_buf->phy_adfs_freq); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : cck_fir_settings = 0x%0x\n", + htt_stats_buf->cck_fir_settings); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : phy_dyn_pri_chan = %u\n", + htt_stats_buf->phy_dyn_pri_chan); + len += scnprintf(buf + len, buf_len - len, "reset_stats : cca_thresh = 0x%0x\n", + htt_stats_buf->cca_thresh); + len += scnprintf(buf + len, buf_len - len, "reset_stats : dyn_cca_status = %u\n", + htt_stats_buf->dyn_cca_status); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : rxdesense_thresh_hw = 0x%x\n", + htt_stats_buf->rxdesense_thresh_hw); + len += scnprintf(buf + len, buf_len - len, + "reset_stats : rxdesense_thresh_sw = 0x%x\n", + htt_stats_buf->rxdesense_thresh_sw); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_soc_txrx_stats_common_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_t2h_soc_txrx_stats_common_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_SOC_COMMON_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "soc_drop_count = 0x%08x%08x\n", + htt_stats_buf->inv_peers_msdu_drop_count_hi, + htt_stats_buf->inv_peers_msdu_drop_count_lo); + len += scnprintf(buf + len, buf_len - len, "================================\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_vdev_txrx_stats_hw_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_t2h_vdev_txrx_stats_hw_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_VDEV_TXRX_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "vdev_id = %u\n", + htt_stats_buf->vdev_id); + + len += scnprintf(buf + len, buf_len - len, "rx_msdu_byte_cnt = 0x%08x%08x\n", + htt_stats_buf->rx_msdu_byte_cnt_hi, + htt_stats_buf->rx_msdu_byte_cnt_lo); + + len += scnprintf(buf + len, buf_len - len, "rx_msdu_cnt = 0x%08x%08x\n", + htt_stats_buf->rx_msdu_cnt_hi, + htt_stats_buf->rx_msdu_cnt_lo); + + len += scnprintf(buf + len, buf_len - len, "tx_msdu_byte_cnt = 0x%08x%08x\n", + htt_stats_buf->tx_msdu_byte_cnt_hi, + htt_stats_buf->tx_msdu_byte_cnt_lo); + + len += scnprintf(buf + len, buf_len - len, "tx_msdu_cnt = 0x%08x%08x\n", + htt_stats_buf->tx_msdu_cnt_hi, + htt_stats_buf->tx_msdu_cnt_lo); + + len += scnprintf(buf + len, buf_len - len, + "tx_msdu_excessive_retry_discard_cnt = 0x%08x%08x\n", + htt_stats_buf->tx_msdu_excessive_retry_discard_cnt_hi, + htt_stats_buf->tx_msdu_excessive_retry_discard_cnt_lo); + + len += scnprintf(buf + len, buf_len - len, + "tx_msdu_cong_ctrl_drop_cnt = 0x%08x%08x\n", + htt_stats_buf->tx_msdu_cong_ctrl_drop_cnt_hi, + htt_stats_buf->tx_msdu_cong_ctrl_drop_cnt_lo); + + len += scnprintf(buf + len, buf_len - len, + "tx_msdu_ttl_expire_drop_cnt = 0x%08x%08x\n", + htt_stats_buf->tx_msdu_ttl_expire_drop_cnt_hi, + htt_stats_buf->tx_msdu_ttl_expire_drop_cnt_lo); + + len += scnprintf(buf + len, buf_len - len, "===============================\n"); + + stats_req->buf_len = len; +} + +static +inline void htt_print_peer_ctrl_path_txrx_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_peer_ctrl_path_txrx_stats_tlv *htt_stat_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i; + const char *mgmt_frm_type[ATH12K_STATS_MGMT_FRM_TYPE_MAX] = {"ASSOC_REQ", + "ASSOC_RES", + "REASSOC_REQ", + "REASSOC_RES", + "PRB_REQ", "PRB_RES", + "RESV", "RESV", + "BCN", "ATIM", + "DISASSOC", "AUTH", + "DAUTH", "ACTN", + "RESV", "RESV", }; + + len += scnprintf(buf + len, buf_len - len, + "HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG:\n"); + len += scnprintf(buf + len, buf_len - len, + "peer_mac_addr = %02x:%02x:%02x:%02x:%02x:%02x\n", + htt_stat_buf->peer_mac_addr[0], htt_stat_buf->peer_mac_addr[1], + htt_stat_buf->peer_mac_addr[2], htt_stat_buf->peer_mac_addr[3], + htt_stat_buf->peer_mac_addr[4], htt_stat_buf->peer_mac_addr[5] + ); + + len += scnprintf(buf + len, buf_len - len, "peer_tx_mgmt_fc_subtype:\n"); + for (i = 0; i < ATH12K_STATS_MGMT_FRM_TYPE_MAX; i++) + len += scnprintf(buf + len, buf_len - len, "\t%s[%d]:%u\n", + mgmt_frm_type[i], i, + htt_stat_buf->peer_rx_mgmt_subtype[i]); + + len += scnprintf(buf + len, buf_len - len, "peer_rx_mgmt_fc_subtype:\n"); + for (i = 0; i < ATH12K_STATS_MGMT_FRM_TYPE_MAX; i++) + len += scnprintf(buf + len, buf_len - len, "\t%s[%d]:%u\n", + mgmt_frm_type[i], i, + htt_stat_buf->peer_rx_mgmt_subtype[i]); + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +} + +static +inline void htt_print_pdev_ctrl_path_tx_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pdev_ctrl_path_tx_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG:\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->fw_tx_mgmt_subtype, + "fw_tx_mgmt_subtype", HTT_STATS_SUBTYPE_MAX, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_sched_txq_supercycle_trigger_tlv(const void *tag_buf, u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_sched_txq_supercycle_triggers_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u16 num_elems = min_t(u16, (tag_len >> 2), HTT_SCHED_SUPERCYCLE_TRIGGER_MAX); + + len += scnprintf(buf + len, buf_len - len, + "HTT_SCHED_TXQ_SUPERCYCLE_TRIGGER_V:\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->supercycle_triggers, + "supercycle_triggers", num_elems, "\n"); + + len += scnprintf(buf + len, buf_len - len, "\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_hw_war_tlv(const void *tag_buf, u16 tag_len, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_hw_war_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u8 i; + u32 mac_id = __le32_to_cpu(htt_stats_buf->mac_id__word); + u32 tag_words = tag_len >> 2; + + tag_words--; /* first word beyond TLV header is for mac_id */ + + len += scnprintf(buf + len, buf_len - len, "HTT_HW_WAR_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "mac_id = %u\n", + u32_get_bits(mac_id, HTT_STATS_MAC_ID)); + + for (i = 0; i < tag_words; i++) { + len += scnprintf(buf + len, buf_len - len, "hw_war %u = %u\n", + i, htt_stats_buf->hw_wars[i]); + } + + stats_req->buf_len = len; +} + +static inline void htt_print_peer_sched_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_peer_sched_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_PEER_SCHED_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "peer_id = %u\n", + htt_stats_buf->peer_id); + len += scnprintf(buf + len, buf_len - len, "num_sched_dl = %u\n", + htt_stats_buf->num_sched_dl); + len += scnprintf(buf + len, buf_len - len, "num_sched_ul = %u\n", + htt_stats_buf->num_sched_ul); + len += scnprintf(buf + len, buf_len - len, "peer_tx_active_dur_ms = %llu\n", + (div_u64((htt_stats_buf->peer_tx_active_dur_us_low | + ((unsigned long long)htt_stats_buf->peer_tx_active_dur_us_high << 32)), + 1000))); + len += scnprintf(buf + len, buf_len - len, "peer_rx_active_dur_ms = %llu\n", + (div_u64((htt_stats_buf->peer_rx_active_dur_us_low | + ((unsigned long long)htt_stats_buf->peer_rx_active_dur_us_high << 32)), + 1000))); + len += scnprintf(buf + len, buf_len - len, "peer_curr_rate_kbps = %u\n", + htt_stats_buf->peer_curr_rate_kbps); + + stats_req->buf_len = len; +} + +static void htt_print_sta_ul_ofdma_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_print_sta_ul_ofdma_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + int i, j; + + len += scnprintf(buf + len, buf_len - len, "========STA UL OFDMA STATS=======\n"); + + len += scnprintf(buf + len, buf_len - len, "pdev ID = %d\n", + htt_stats_buf->pdev_id); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->rx_trigger_type, + "STA HW Trigger Type", HTT_STA_UL_OFDMA_NUM_TRIG_TYPE, "\n"); + + len += scnprintf(buf + len, buf_len - len, + " BASIC:%u, BRPOLL:%u, MUBAR:%u, MURTS:%u BSRP:%u Others:%u", + htt_stats_buf->ax_trigger_type[0], + htt_stats_buf->ax_trigger_type[1], + htt_stats_buf->ax_trigger_type[2], + htt_stats_buf->ax_trigger_type[3], + htt_stats_buf->ax_trigger_type[4], + htt_stats_buf->ax_trigger_type[5]); + len += scnprintf(buf + len, buf_len - len, "11ax Trigger Type\n"); + + len += scnprintf(buf + len, buf_len - len, + " HIPRI:%u, LOWPRI:%u, BSR:%u", + htt_stats_buf->num_data_ppdu_responded_per_hwq[0], + htt_stats_buf->num_data_ppdu_responded_per_hwq[1], + htt_stats_buf->num_data_ppdu_responded_per_hwq[2]); + len += scnprintf(buf + len, buf_len - len, "Data PPDU Resp per HWQ\n"); + + len += scnprintf(buf + len, buf_len - len, + " HIPRI:%u, LOWPRI:%u, BSR:%u", + htt_stats_buf->num_null_delimiters_responded_per_hwq[0], + htt_stats_buf->num_null_delimiters_responded_per_hwq[1], + htt_stats_buf->num_null_delimiters_responded_per_hwq[2]); + len += scnprintf(buf + len, buf_len - len, "Null Delim Resp per HWQ\n"); + + len += scnprintf(buf + len, buf_len - len, + " Data:%u, NullDelim:%u", + htt_stats_buf->num_total_trig_responses[0], + htt_stats_buf->num_total_trig_responses[1]); + len += scnprintf(buf + len, buf_len - len, "Trigger Resp Status\n"); + + len += scnprintf(buf + len, buf_len - len, "Last Trigger RX Time Interval = %u\n", + htt_stats_buf->last_trig_rx_time_delta_ms); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_tx_mcs, + "ul_ofdma_tx_mcs", + HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS, "\n"); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_tx_nss, + "ul_ofdma_tx_nss", + HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS, "\n"); + + for (j = 0; j < HTT_TX_PDEV_STATS_NUM_GI_COUNTERS; j++) { + len += scnprintf(buf + len, buf_len - len, "ul_ofdma_tx_gi[%u]", j); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_tx_gi[j], NULL, + HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS, "\n"); + } + + len += scnprintf(buf + len, buf_len - len, "ul_ofdma_tx_ldpc = %u\n", + htt_stats_buf->ul_ofdma_tx_ldpc); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->ul_ofdma_tx_bw, + "ul_ofdma_tx_bw", + HTT_STA_UL_OFDMA_NUM_BW_COUNTERS, "\n"); + + for (i = 0; i < HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES; i++) { + len += scnprintf(buf + len, buf_len - len, + i == 0 ? "half_ul_ofdma_tx_bw" : "quarter_ul_ofdma_tx_bw"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->reduced_ul_ofdma_tx_bw[i], + NULL, HTT_STA_UL_OFDMA_NUM_BW_COUNTERS, "\n"); + } + + len += scnprintf(buf + len, buf_len - len, "Trig Based Tx PPDU = %u\n", + htt_stats_buf->trig_based_ppdu_tx); + len += scnprintf(buf + len, buf_len - len, "RBO Based Tx PPDU = %u\n", + htt_stats_buf->rbo_based_ppdu_tx); + len += scnprintf(buf + len, buf_len - len, "MU to SU EDCA Switch Count = %u\n", + htt_stats_buf->mu_edca_to_su_edca_switch_count); + len += scnprintf(buf + len, buf_len - len, "MU EDCA Params Apply Count = %u\n", + htt_stats_buf->num_mu_edca_param_apply_count); + + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->current_edca_hwq_mode, + "current_edca_hwq_mode[AC]", + HTT_NUM_AC_WMM, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->current_cw_min, + "current_cw_min", + HTT_NUM_AC_WMM, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->current_cw_max, + "current_cw_max", + HTT_NUM_AC_WMM, "\n"); + PRINT_ARRAY_TO_BUF(buf, len, htt_stats_buf->current_aifs, + "current_aifs", + HTT_NUM_AC_WMM, "\n"); + + len += scnprintf(buf + len, buf_len - len, "=============================\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_vdev_rtt_resp_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_vdev_rtt_resp_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_VDEV_RTT_RESP_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "vdev_id = %u\n", + htt_stats_buf->vdev_id); + len += scnprintf(buf + len, buf_len - len, "tx_ftm_suc = %u\n", + htt_stats_buf->tx_ftm_suc); + len += scnprintf(buf + len, buf_len - len, "tx_ftm_suc_retry = %u\n", + htt_stats_buf->tx_ftm_suc_retry); + len += scnprintf(buf + len, buf_len - len, "tx_ftm_fail = %u\n", + htt_stats_buf->tx_ftm_fail); + len += scnprintf(buf + len, buf_len - len, "rx_ftmr_cnt = %u\n", + htt_stats_buf->rx_ftmr_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_ftmr_dup_cnt = %u\n", + htt_stats_buf->rx_ftmr_dup_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_iftmr_cnt = %u\n", + htt_stats_buf->rx_iftmr_cnt); + len += scnprintf(buf + len, buf_len - len, "rx_iftmr_dup_cnt = %u\n", + htt_stats_buf->rx_iftmr_dup_cnt); + len += scnprintf(buf + len, buf_len - len, + "initiator_active_responder_rejected_cnt = %u\n", + htt_stats_buf->initiator_active_responder_rejected_cnt); + len += scnprintf(buf + len, buf_len - len, "responder_terminate_cnt = %u\n", + htt_stats_buf->responder_terminate_cnt); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_vdev_rtt_init_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_vdev_rtt_init_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, "HTT_VDEV_RTT_INIT_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "vdev_id = %u\n", + htt_stats_buf->vdev_id); + len += scnprintf(buf + len, buf_len - len, "tx_ftmr_cnt = %u\n", + htt_stats_buf->tx_ftmr_cnt); + len += scnprintf(buf + len, buf_len - len, "tx_ftmr_fail = %u\n", + htt_stats_buf->tx_ftmr_fail); + len += scnprintf(buf + len, buf_len - len, "tx_ftmr_suc_retry = %u\n", + htt_stats_buf->tx_ftmr_suc_retry); + len += scnprintf(buf + len, buf_len - len, "rx_ftm_cnt = %u\n", + htt_stats_buf->rx_ftm_cnt); + len += scnprintf(buf + len, buf_len - len, "initiator_terminate_cnt = %u\n", + htt_stats_buf->initiator_terminate_cnt); + len += scnprintf(buf + len, buf_len - len, "tx_meas_req_count = %u\n", + htt_stats_buf->tx_meas_req_count); + len += scnprintf(buf + len, buf_len - len, "===============================\n"); + + stats_req->buf_len = len; +} + +static inline void +htt_print_pktlog_and_htt_ring_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_pktlog_and_htt_ring_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + + len += scnprintf(buf + len, buf_len - len, + "HTT_PKTLOG_AND_HTT_RING_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, "pktlog_lite_drop_cnt = %u\n", + htt_stats_buf->pktlog_lite_drop_cnt); + len += scnprintf(buf + len, buf_len - len, "pktlog_tqm_drop_cnt = %u\n", + htt_stats_buf->pktlog_tqm_drop_cnt); + len += scnprintf(buf + len, buf_len - len, "pktlog_ppdu_stats_drop_cnt = %u\n", + htt_stats_buf->pktlog_ppdu_stats_drop_cnt); + len += scnprintf(buf + len, buf_len - len, "pktlog_ppdu_ctrl_drop_cnt = %u\n", + htt_stats_buf->pktlog_ppdu_ctrl_drop_cnt); + len += scnprintf(buf + len, buf_len - len, "pktlog_sw_events_drop_cnt = %u\n", + htt_stats_buf->pktlog_sw_events_drop_cnt); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_dlpager_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_dl_pager_stats_tlv *htt_stats_buf = tag_buf; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 msg_dword_1 = htt_stats_buf->msg_dword_1; + u32 msg_dword_3 = htt_stats_buf->msg_dword_3; + u8 pg_locked = HTT_STATS_PAGE_LOCKED; + u8 pg_unlocked = HTT_STATS_PAGE_UNLOCKED; + int i; + + len += scnprintf(buf + len, buf_len - len, "HTT_DLPAGER_STATS_TLV:\n"); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + len += scnprintf(buf + len, buf_len - len, "ASYNC locked pages = %u\n", + HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_GET(msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, "SYNC locked pages = %u\n", + HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_GET(msg_dword_1)); + len += scnprintf(buf + len, buf_len - len, "Total locked pages = %u\n", + HTT_DLPAGER_TOTAL_LOCKED_PAGES_GET(htt_stats_buf->msg_dword_2)); + len += scnprintf(buf + len, buf_len - len, "Total free pages = %u\n", + HTT_DLPAGER_TOTAL_FREE_PAGES_GET(htt_stats_buf->msg_dword_2)); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + len += scnprintf(buf + len, buf_len - len, "LOCKED PAGES HISTORY\n"); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + len += scnprintf(buf + len, buf_len - len, "last_locked_page_idx = %u\n", + (HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(msg_dword_3)) ? + (HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(msg_dword_3) - 1) : + (HTT_DLPAGER_STATS_MAX_HIST - 1)); + + for (i = 0; i < HTT_DLPAGER_STATS_MAX_HIST; i++) { + len += scnprintf(buf + len, buf_len - len, + "Index - %u : Page Number - %u : Num of pages - %u : Timestamp - %llu us\n", + i, + htt_stats_buf->last_pages_info[pg_locked][i].page_num, + htt_stats_buf->last_pages_info + [pg_locked][i].num_of_pages, + ((htt_stats_buf->last_pages_info + [pg_locked][i].timestamp_lsbs) | + (((unsigned long long)htt_stats_buf->last_pages_info + [pg_locked][i].timestamp_msbs) << 32))); + } + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + len += scnprintf(buf + len, buf_len - len, "UNLOCKED PAGES HISTORY\n"); + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + len += scnprintf(buf + len, buf_len - len, "last_unlocked_page_idx = %u\n", + (HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(msg_dword_3)) ? + (HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(msg_dword_3) - 1) : + (HTT_DLPAGER_STATS_MAX_HIST - 1)); + + for (i = 0; i < HTT_DLPAGER_STATS_MAX_HIST; i++) { + len += scnprintf(buf + len, buf_len - len, + "Index - %u : Page Number - %u : Num of pages - %u : Timestamp - %llu us\n", + i, htt_stats_buf->last_pages_info + [pg_unlocked][i].page_num, + htt_stats_buf->last_pages_info + [pg_unlocked][i].num_of_pages, + ((htt_stats_buf->last_pages_info + [pg_unlocked][i].timestamp_lsbs) | + (((unsigned long long)htt_stats_buf->last_pages_info + [pg_unlocked][i].timestamp_msbs) << 32))); + } + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static inline void htt_print_histogram_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_tx_histogram_stats_tlv *htt_stats_buf = tag_buf; + u8 i = 0; + u16 index = 0; + u8 *buf = stats_req->buf; + u32 len = stats_req->buf_len; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + char data[HTT_HISTOGRAM_STATS_LEN] = {0}; + + len += scnprintf(buf + len, buf_len - len, "low_latency_rate_cnt = %u\n", + htt_stats_buf->low_latency_rate_cnt); + + len += scnprintf(buf + len, buf_len - len, "su_burst_rate_drop_cnt = %u\n", + htt_stats_buf->su_burst_rate_drop_cnt); + + len += scnprintf(buf + len, buf_len - len, "su_burst_rate_drop_fail_cnt = %u\n", + htt_stats_buf->su_burst_rate_drop_fail_cnt); + + len += scnprintf(buf + len, buf_len - len, "PER_HISTOGRAM_STATS\n"); + + index = 0; + memset(data, 0x0, HTT_HISTOGRAM_STATS_LEN); + + for (i = 0 ; i < 25; i++) { + index += scnprintf(&data[index], + HTT_HISTOGRAM_STATS_LEN - index, + " %u:%u,", i, htt_stats_buf->per_histogram_cnt[i]); + if (index >= HTT_HISTOGRAM_STATS_LEN) + break; + } + + len += scnprintf(buf + len, buf_len - len, "Per_histogram_cnt: %s\n", data); + + index = 0; + memset(data, 0x0, HTT_HISTOGRAM_STATS_LEN); + + for (i = 25 ; i < 50; i++) { + index += scnprintf(&data[index], + HTT_HISTOGRAM_STATS_LEN - index, + " %u:%u,", i, htt_stats_buf->per_histogram_cnt[i]); + if (index >= HTT_HISTOGRAM_STATS_LEN) + break; + } + + len += scnprintf(buf + len, buf_len - len, " %s\n", data); + + index = 0; + memset(data, 0x0, HTT_HISTOGRAM_STATS_LEN); + + for (i = 50 ; i < 75; i++) { + index += scnprintf(&data[index], + HTT_HISTOGRAM_STATS_LEN - index, + " %u:%u,", i, htt_stats_buf->per_histogram_cnt[i]); + if (index >= HTT_HISTOGRAM_STATS_LEN) + break; + } + + len += scnprintf(buf + len, buf_len - len, " %s\n", data); + + index = 0; + memset(data, 0x0, HTT_HISTOGRAM_STATS_LEN); + + for (i = 75 ; i < HTT_TX_PDEV_STATS_NUM_PER_COUNTERS; i++) { + index += scnprintf(&data[index], + HTT_HISTOGRAM_STATS_LEN - index, + " %u:%u,", i, htt_stats_buf->per_histogram_cnt[i]); + if (index >= HTT_HISTOGRAM_STATS_LEN) + break; + } + + len += scnprintf(buf + len, buf_len - len, " %s\n", data); + + stats_req->buf_len = len; +} + +static void htt_print_umac_ssr_stats_tlv(const void *tag_buf, + struct debug_htt_stats_req *stats_req) +{ + const struct htt_umac_ssr_stats_tlv *htt_stats_buf = tag_buf; + u32 buf_len = ATH12K_HTT_STATS_BUF_SIZE; + u32 len = stats_req->buf_len; + u8 *buf = stats_req->buf; + + len += scnprintf(buf + len, buf_len - len, "HTT_UMAC_SSR_STATS_TLV:"); + len += scnprintf(buf + len, buf_len - len, "total_done = %u\n", + htt_stats_buf->total_done); + len += scnprintf(buf + len, buf_len - len, "trigger_requests_count = %u\n", + htt_stats_buf->trigger_requests_count); + len += scnprintf(buf + len, buf_len - len, "total_trig_dropped = %u\n", + htt_stats_buf->total_trig_dropped); + len += scnprintf(buf + len, buf_len - len, "umac_disengaged_count = %u\n", + htt_stats_buf->umac_disengaged_count); + len += scnprintf(buf + len, buf_len - len, "umac_soft_reset_count = %u\n", + htt_stats_buf->umac_soft_reset_count); + len += scnprintf(buf + len, buf_len - len, "umac_engaged_count = %u\n", + htt_stats_buf->umac_engaged_count); + len += scnprintf(buf + len, buf_len - len, "last_trigger_request_ms = %u\n", + htt_stats_buf->last_trigger_request_ms); + len += scnprintf(buf + len, buf_len - len, "last_start_ms = %u\n", + htt_stats_buf->last_start_ms); + len += scnprintf(buf + len, buf_len - len, "last_start_disengage_umac_ms = %u\n", + htt_stats_buf->last_start_disengage_umac_ms); + len += scnprintf(buf + len, buf_len - len, "last_enter_ssr_platform_thread_ms = %u\n", + htt_stats_buf->last_enter_ssr_platform_thread_ms); + len += scnprintf(buf + len, buf_len - len, "last_exit_ssr_platform_thread_ms = %u\n", + htt_stats_buf->last_exit_ssr_platform_thread_ms); + len += scnprintf(buf + len, buf_len - len, "last_start_engage_umac_ms = %u\n", + htt_stats_buf->last_start_engage_umac_ms); + len += scnprintf(buf + len, buf_len - len, "post_reset_tqm_sync_cmd_completion_ms = %u\n", + htt_stats_buf->post_reset_tqm_sync_cmd_completion_ms); + len += scnprintf(buf + len, buf_len - len, "last_done_successful_ms = %u\n", + htt_stats_buf->last_done_successful_ms); + len += scnprintf(buf + len, buf_len - len, "last_e2e_delta_ms = %u\n", + htt_stats_buf->last_e2e_delta_ms); + len += scnprintf(buf + len, buf_len - len, "max_e2e_delta_ms = %u\n", + htt_stats_buf->max_e2e_delta_ms); + len += scnprintf(buf + len, buf_len - len, "trigger_count_for_umac_hang = %u\n", + htt_stats_buf->trigger_count_for_umac_hang); + len += scnprintf(buf + len, buf_len - len, "trigger_count_for_mlo_quick_ssr = %u\n", + htt_stats_buf->trigger_count_for_mlo_quick_ssr); + len += scnprintf(buf + len, buf_len - len, "trigger_count_for_unknown_signature = %u\n", + htt_stats_buf->trigger_count_for_unknown_signature); + len += scnprintf(buf + len, buf_len - len, "htt_sync_mlo_initiate_umac_recovery_ms = %u\n", + htt_stats_buf->htt_sync_mlo_initiate_umac_recovery_ms); + len += scnprintf(buf + len, buf_len - len, "htt_sync_do_pre_reset_ms = %u\n", + htt_stats_buf->htt_sync_do_pre_reset_ms); + len += scnprintf(buf + len, buf_len - len, "htt_sync_do_post_reset_start_ms = %u\n", + htt_stats_buf->htt_sync_do_post_reset_start_ms); + len += scnprintf(buf + len, buf_len - len, "htt_sync_do_post_reset_complete_ms = %u\n", + htt_stats_buf->htt_sync_do_post_reset_complete_ms); + + len += scnprintf(buf + len, buf_len - len, + "=================================================\n"); + + stats_req->buf_len = len; +} + +static int ath12k_dbg_htt_ext_stats_parse(struct ath12k_base *ab, + u16 tag, u16 len, const void *tag_buf, + void *user_data) +{ + struct debug_htt_stats_req *stats_req = user_data; + + switch (tag) { + case HTT_STATS_TX_PDEV_CMN_TAG: + htt_print_tx_pdev_stats_cmn_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TX_PDEV_UNDERRUN_TAG: + htt_print_tx_pdev_stats_urrn_tlv_v(tag_buf, len, stats_req); + break; + case HTT_STATS_TX_PDEV_SIFS_TAG: + htt_print_tx_pdev_stats_sifs_tlv_v(tag_buf, len, stats_req); + break; + case HTT_STATS_TX_PDEV_FLUSH_TAG: + htt_print_tx_pdev_stats_flush_tlv_v(tag_buf, len, stats_req); + break; + case HTT_STATS_TX_PDEV_PHY_ERR_TAG: + htt_print_tx_pdev_stats_phy_err_tlv_v(tag_buf, len, stats_req); + break; + case HTT_STATS_TX_PDEV_SIFS_HIST_TAG: + htt_print_tx_pdev_stats_sifs_hist_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG: + htt_print_tx_pdev_stats_tx_ppdu_stats_tlv_v(tag_buf, stats_req); + break; + + case HTT_STATS_MU_PPDU_DIST_TAG: + htt_print_tx_pdev_mu_ppdu_dist_stats_tlv_v(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG: + htt_print_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v(tag_buf, len, + stats_req); + break; + + case HTT_STATS_STRING_TAG: + htt_print_stats_string_tlv(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_HWQ_CMN_TAG: + htt_print_tx_hwq_stats_cmn_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG: + htt_print_tx_hwq_difs_latency_stats_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_HWQ_CMD_RESULT_TAG: + htt_print_tx_hwq_cmd_result_stats_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_HWQ_CMD_STALL_TAG: + htt_print_tx_hwq_cmd_stall_stats_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_HWQ_FES_STATUS_TAG: + htt_print_tx_hwq_fes_result_stats_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG: + htt_print_tx_hwq_tried_mpdu_cnt_hist_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG: + htt_print_tx_hwq_txop_used_cnt_hist_tlv_v(tag_buf, len, stats_req); + break; + case HTT_STATS_TX_TQM_GEN_MPDU_TAG: + htt_print_tx_tqm_gen_mpdu_stats_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_TQM_LIST_MPDU_TAG: + htt_print_tx_tqm_list_mpdu_stats_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG: + htt_print_tx_tqm_list_mpdu_cnt_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_TQM_CMN_TAG: + htt_print_tx_tqm_cmn_stats_tlv(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_TQM_PDEV_TAG: + htt_print_tx_tqm_pdev_stats_tlv_v(tag_buf, stats_req); + break; + + case HTT_STATS_TX_TQM_CMDQ_STATUS_TAG: + htt_print_tx_tqm_cmdq_status_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_EAPOL_PACKETS_TAG: + htt_print_tx_de_eapol_packets_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG: + htt_print_tx_de_classify_failed_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_CLASSIFY_STATS_TAG: + htt_print_tx_de_classify_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG: + htt_print_tx_de_classify_status_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG: + htt_print_tx_de_enqueue_packets_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG: + htt_print_tx_de_enqueue_discard_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG: + htt_print_tx_de_fw2wbm_ring_full_hist_tlv(tag_buf, len, stats_req); + break; + + case HTT_STATS_TX_DE_CMN_TAG: + htt_print_tx_de_cmn_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RING_IF_TAG: + htt_print_ring_if_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG: + htt_print_tx_pdev_mu_mimo_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG: + htt_print_tx_pdev_mumimo_grp_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_DL_MU_OFDMA_STATS_TAG: + htt_print_tx_pdev_dl_mu_ofdma_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_UL_MU_OFDMA_STATS_TAG: + htt_print_tx_pdev_ul_mu_ofdma_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_DL_MU_MIMO_STATS_TAG: + htt_print_tx_pdev_dl_mu_mimo_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_UL_MU_MIMO_STATS_TAG: + htt_print_tx_pdev_ul_mu_mimo_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_SFM_CMN_TAG: + htt_print_sfm_cmn_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_SRING_STATS_TAG: + htt_print_sring_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_FW_STATS_TAG: + htt_print_rx_pdev_fw_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG: + htt_print_rx_pdev_fw_ring_mpdu_err_tlv_v(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG: + htt_print_rx_pdev_fw_mpdu_drop_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_RX_SOC_FW_STATS_TAG: + htt_print_rx_soc_fw_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG: + htt_print_rx_soc_fw_refill_ring_empty_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG: + htt_print_rx_soc_fw_refill_ring_num_refill_tlv_v( + tag_buf, len, stats_req); + break; + case HTT_STATS_RX_REFILL_RXDMA_ERR_TAG: + htt_print_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v( + tag_buf, len, stats_req); + break; + + case HTT_STATS_RX_REFILL_REO_ERR_TAG: + htt_print_rx_soc_fw_refill_ring_num_reo_err_tlv_v( + tag_buf, len, stats_req); + break; + + case HTT_STATS_RX_REO_RESOURCE_STATS_TAG: + htt_print_rx_reo_debug_stats_tlv_v( + tag_buf, stats_req); + break; + case HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG: + htt_print_rx_pdev_fw_stats_phy_err_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_RATE_STATS_TAG: + htt_print_tx_pdev_rate_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_RATE_STATS_TAG: + htt_print_rx_pdev_rate_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG: + htt_print_rx_pdev_rate_ext_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG: + htt_print_tx_pdev_stats_sched_per_txq_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TX_SCHED_CMN_TAG: + htt_print_stats_tx_sched_cmn_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_MPDU_STATS_TAG: + htt_print_tx_pdev_mu_mimo_mpdu_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG: + htt_print_sched_txq_cmd_posted_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_RING_IF_CMN_TAG: + htt_print_ring_if_cmn_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_SFM_CLIENT_USER_TAG: + htt_print_sfm_client_user_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_SFM_CLIENT_TAG: + htt_print_sfm_client_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_TQM_ERROR_STATS_TAG: + htt_print_tx_tqm_error_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG: + htt_print_sched_txq_cmd_reaped_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_SRING_CMN_TAG: + htt_print_sring_cmn_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SOUNDING_STATS_TAG: + htt_print_tx_sounding_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG: + htt_print_tx_selfgen_ac_err_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_CMN_STATS_TAG: + htt_print_tx_selfgen_cmn_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_AC_STATS_TAG: + htt_print_tx_selfgen_ac_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_AX_STATS_TAG: + htt_print_tx_selfgen_ax_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG: + htt_print_tx_selfgen_ax_err_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG: + htt_print_tx_hwq_mu_mimo_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG: + htt_print_tx_hwq_mu_mimo_mpdu_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG: + htt_print_tx_hwq_mu_mimo_cmn_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_HW_INTR_MISC_TAG: + htt_print_hw_stats_intr_misc_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_HW_WD_TIMEOUT_TAG: + htt_print_hw_stats_wd_timeout_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_HW_PDEV_ERRS_TAG: + htt_print_hw_stats_pdev_errs_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_COUNTER_NAME_TAG: + htt_print_counter_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_TID_DETAILS_TAG: + htt_print_tx_tid_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_TID_DETAILS_V1_TAG: + htt_print_tx_tid_stats_v1_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_TID_DETAILS_TAG: + htt_print_rx_tid_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PEER_STATS_CMN_TAG: + htt_print_peer_stats_cmn_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PEER_DETAILS_TAG: + htt_print_peer_details_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PEER_MSDU_FLOWQ_TAG: + htt_print_msdu_flow_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PEER_TX_RATE_STATS_TAG: + htt_print_tx_peer_rate_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PEER_RX_RATE_STATS_TAG: + htt_print_rx_peer_rate_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_DE_COMPL_STATS_TAG: + htt_print_tx_de_compl_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PDEV_CCA_1SEC_HIST_TAG: + case HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG: + case HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG: + htt_print_pdev_cca_stats_hist_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PDEV_CCA_COUNTERS_TAG: + htt_print_pdev_stats_cca_counters_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_WHAL_TX_TAG: + htt_print_hw_stats_whal_tx_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PDEV_TWT_SESSIONS_TAG: + htt_print_pdev_stats_twt_sessions_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PDEV_TWT_SESSION_TAG: + htt_print_pdev_stats_twt_session_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG: + htt_print_sched_txq_sched_order_su_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG: + htt_print_sched_txq_sched_ineligibility_tlv_v(tag_buf, len, stats_req); + break; + + case HTT_STATS_PDEV_OBSS_PD_TAG: + htt_print_pdev_obss_pd_stats_tlv_v(tag_buf, stats_req); + break; + case HTT_STATS_HW_WAR_TAG: + htt_print_hw_war_tlv(tag_buf, len, stats_req); + break; + case HTT_STATS_RING_BACKPRESSURE_STATS_TAG: + htt_print_backpressure_stats_tlv_v(tag_buf, user_data); + break; + + case HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG: + htt_print_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG: + htt_print_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG: + htt_print_tx_pdev_rate_stats_be_ofdma_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG: + htt_print_ul_mumimo_trig_be_stats(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_BE_STATS_TAG: + htt_print_tx_selfgen_be_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG: + htt_print_tx_selfgen_be_err_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG: + htt_print_tx_selfgen_be_sched_status_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG: + htt_print_tx_pdev_be_ul_mu_mimo_sch_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG: + htt_print_be_ul_mimo_user_stats(tag_buf, stats_req); + break; + + case HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG: + htt_print_be_ul_ofdma_trigger_stats(tag_buf, stats_req); + break; + case HTT_STATS_TX_PDEV_BE_RATE_STATS_TAG: + htt_print_tx_pdev_be_rate_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_LATENCY_PROF_STATS_TAG: + htt_print_latency_prof_stats_tlv_v(tag_buf, user_data); + break; + case HTT_STATS_LATENCY_CTX_TAG: + htt_print_latency_prof_ctx_tlv(tag_buf, stats_req); + break; + case HTT_STATS_LATENCY_CNT_TAG: + htt_print_latency_prof_cnt(tag_buf, stats_req); + break; + case HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG: + htt_print_ul_ofdma_trigger_stats(tag_buf, stats_req); + break; + case HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG: + htt_print_ul_ofdma_user_stats(tag_buf, stats_req); + break; + case HTT_STATS_RX_PDEV_UL_MIMO_USER_STATS_TAG: + htt_print_ul_mimo_user_stats(tag_buf, stats_req); + break; + case HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG: + htt_print_ul_mumimo_trig_stats(tag_buf, stats_req); + break; + case HTT_STATS_RX_FSE_STATS_TAG: + htt_print_rx_fse_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PEER_SCHED_STATS_TAG: + htt_print_peer_sched_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG: + htt_print_sched_txq_supercycle_trigger_tlv(tag_buf, len, stats_req); + break; + case HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG: + htt_print_pdev_ctrl_path_tx_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG: + htt_print_pdev_tx_rate_txbf_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG: + htt_print_txbf_ofdma_ndpa_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PER_RATE_STATS_TAG: + htt_print_tx_per_rate_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG: + htt_print_txbf_ofdma_ndp_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG: + htt_print_txbf_ofdma_brp_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG: + htt_print_txbf_ofdma_steer_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG: + htt_print_tx_selfgen_ac_sched_status_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG: + htt_print_tx_selfgen_ax_sched_status_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG: + htt_print_unavailable_error_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG: + htt_print_unsupported_error_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_VDEV_RTT_RESP_STATS_TAG: + htt_print_vdev_rtt_resp_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_VDEV_RTT_INIT_STATS_TAG: + htt_print_vdev_rtt_init_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG: + htt_print_pktlog_and_htt_ring_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_DLPAGER_STATS_TAG: + htt_print_dlpager_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PHY_COUNTERS_TAG: + htt_print_phy_counters_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PHY_STATS_TAG: + htt_print_phy_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_STA_UL_OFDMA_STATS_TAG: + htt_print_sta_ul_ofdma_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PHY_RESET_COUNTERS_TAG: + htt_print_phy_reset_counters_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PHY_RESET_STATS_TAG: + htt_print_phy_reset_stats_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_SOC_TXRX_STATS_COMMON_TAG: + htt_print_soc_txrx_stats_common_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_VDEV_TXRX_STATS_HW_STATS_TAG: + htt_print_vdev_txrx_stats_hw_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_AST_ENTRY_TAG: + htt_print_ast_entry_tlv(tag_buf, stats_req); + break; + + case HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG: + htt_print_peer_ctrl_path_txrx_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG: + htt_print_txbf_ofdma_ax_ndpa_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG: + htt_print_txbf_ofdma_ax_ndp_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG: + htt_print_txbf_ofdma_ax_brp_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG: + htt_print_txbf_ofdma_ax_steer_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG: + htt_print_txbf_ofdma_be_ndpa_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG: + htt_print_txbf_ofdma_be_ndp_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG: + htt_print_txbf_ofdma_be_brp_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG: + htt_print_txbf_ofdma_be_steer_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_DMAC_RESET_STATS_TAG: + htt_print_dmac_reset_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG: + htt_print_be_ul_ofdma_user_stats(tag_buf, stats_req); + break; + case HTT_STATS_PHY_TPC_STATS_TAG: + htt_print_phy_tpc_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PDEV_PUNCTURE_STATS_TAG: + htt_print_puncture_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_ML_PEER_DETAILS_TAG: + htt_print_ml_peer_details_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_ML_PEER_EXT_DETAILS_TAG: + htt_print_ml_peer_ext_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_ML_LINK_INFO_DETAILS_TAG: + htt_print_ml_link_info_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TX_PDEV_PPDU_DUR_TAG: + htt_print_tx_pdev_ppdu_dur_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_RX_PDEV_PPDU_DUR_TAG: + htt_print_rx_pdev_ppdu_dur_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG: + htt_print_pdev_sched_algo_ofdma_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_LATENCY_PROF_CAL_STATS_TAG: + htt_print_latency_prof_cal_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG: + htt_print_tx_pdev_ap_edca_params_stats_tlv_v(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG: + htt_print_txbf_ofdma_ax_steer_mpdu_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG: + htt_print_txbf_ofdma_be_steer_mpdu_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PEER_AX_OFDMA_STATS_TAG: + htt_print_peer_ax_ofdma_stats(tag_buf, stats_req); + break; + case HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG: + htt_print_tx_pdev_mu_edca_params_stats_tlv_v(tag_buf, stats_req); + break; + case HTT_STATS_ODD_PDEV_MANDATORY_TAG: + htt_print_odd_pdev_mandatory_tlv(tag_buf, stats_req); + break; + case HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG: + htt_print_pdev_mbssid_ctrl_frame_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_TX_PDEV_MLO_ABORT_TAG: + htt_print_tx_pdev_stats_mlo_abort_tlv_v(tag_buf, len, stats_req); + break; + case HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG: + htt_print_tx_pdev_stats_mlo_txop_abort_tlv_v(tag_buf, len, stats_req); + break; + case HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG: + htt_print_histogram_stats_tlv(tag_buf, stats_req); + break; + case HTT_STATS_UMAC_SSR_TAG: + htt_print_umac_ssr_stats_tlv(tag_buf, stats_req); + break; + default: + break; + } + + return 0; +} + +void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, + struct sk_buff *skb) +{ + struct ath12k_htt_extd_stats_msg *msg; + struct debug_htt_stats_req *stats_req; + struct ath12k *ar; + u32 len; + u64 cookie; + int ret; + bool send_completion = false; + u8 pdev_id; + + msg = (struct ath12k_htt_extd_stats_msg *)skb->data; + cookie = __le64_to_cpu(msg->cookie); + + if (u64_get_bits(cookie, HTT_STATS_COOKIE_MSB) != HTT_STATS_MAGIC_VALUE) { + ath12k_warn(ab, "received invalid htt ext stats event\n"); + return; + } + + pdev_id = u64_get_bits(cookie, HTT_STATS_COOKIE_LSB); + rcu_read_lock(); + ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); + rcu_read_unlock(); + if (!ar) { + ath12k_warn(ab, "failed to get ar for pdev_id %d\n", pdev_id); + return; + } + + stats_req = ar->debug.htt_stats.stats_req; + if (!stats_req) + return; + + spin_lock_bh(&ar->debug.htt_stats.lock); + + stats_req->done = u32_get_bits(__le32_to_cpu(msg->info1), + HTT_T2H_EXT_STATS_INFO1_DONE); + if (stats_req->done) + send_completion = true; + + spin_unlock_bh(&ar->debug.htt_stats.lock); + + len = u32_get_bits(__le32_to_cpu(msg->info1), HTT_T2H_EXT_STATS_INFO1_LENGTH); + ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, + ath12k_dbg_htt_ext_stats_parse, + stats_req); + if (ret) + ath12k_warn(ab, "Failed to parse tlv %d\n", ret); + + if (send_completion) + complete(&stats_req->cmpln); +} + +static ssize_t ath12k_read_htt_stats_type(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[32]; + size_t len; + + len = scnprintf(buf, sizeof(buf), "%u\n", ar->debug.htt_stats.type); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_write_htt_stats_type(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u32 type; + unsigned int cfg_param[4] = {0}; + int ret, num_args; + u8 *buf; + + buf = vzalloc(count); + if (!buf) + return -ENOMEM; + + if (copy_from_user(buf, user_buf, count)) { + vfree(buf); + return -EFAULT; + } + + num_args = sscanf(buf, "%u %u %u %u %u\n", &type, &cfg_param[0], + &cfg_param[1], &cfg_param[2], &cfg_param[3]); + vfree(buf); + + if (type >= ATH12K_DBG_HTT_NUM_EXT_STATS) + return -E2BIG; + + if (type == ATH12K_DBG_HTT_EXT_STATS_RESET) + return -EPERM; + + ar->debug.htt_stats.type = type; + ar->debug.htt_stats.cfg_param[0] = cfg_param[0]; + ar->debug.htt_stats.cfg_param[1] = cfg_param[1]; + ar->debug.htt_stats.cfg_param[2] = cfg_param[2]; + ar->debug.htt_stats.cfg_param[3] = cfg_param[3]; + + ret = count; + return ret; +} + +static const struct file_operations fops_htt_stats_type = { + .read = ath12k_read_htt_stats_type, + .write = ath12k_write_htt_stats_type, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static int ath12k_prep_htt_stats_cfg_params(struct ath12k *ar, u8 type, + const u8 *mac_addr, + struct htt_ext_stats_cfg_params *cfg_params) +{ + if (!cfg_params) + return -EINVAL; + + switch (type) { + case ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_HWQ: + case ATH12K_DBG_HTT_EXT_STATS_TX_MU_HWQ: + cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_HWQS; + break; + case ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED: + cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_TXQS; + break; + case ATH12K_DBG_HTT_EXT_STATS_TQM_CMDQ: + cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_CMDQS; + break; + case ATH12K_DBG_HTT_EXT_STATS_PEER_INFO: + cfg_params->cfg0 = HTT_STAT_PEER_INFO_MAC_ADDR; + cfg_params->cfg0 |= FIELD_PREP(GENMASK(15, 1), + HTT_PEER_STATS_REQ_MODE_FLUSH_TQM); + cfg_params->cfg1 = HTT_STAT_DEFAULT_PEER_REQ_TYPE; + cfg_params->cfg2 |= FIELD_PREP(GENMASK(7, 0), mac_addr[0]); + cfg_params->cfg2 |= FIELD_PREP(GENMASK(15, 8), mac_addr[1]); + cfg_params->cfg2 |= FIELD_PREP(GENMASK(23, 16), mac_addr[2]); + cfg_params->cfg2 |= FIELD_PREP(GENMASK(31, 24), mac_addr[3]); + cfg_params->cfg3 |= FIELD_PREP(GENMASK(7, 0), mac_addr[4]); + cfg_params->cfg3 |= FIELD_PREP(GENMASK(15, 8), mac_addr[5]); + break; + case ATH12K_DBG_HTT_EXT_STATS_RING_IF_INFO: + case ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO: + cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ALL_RINGS; + break; + case ATH12K_DBG_HTT_EXT_STATS_ACTIVE_PEERS_LIST: + cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS; + break; + case ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS: + cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE; + break; + case ATH12K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO: + cfg_params->cfg0 = HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS; + break; + default: + break; + } + + return 0; +} + +int ath12k_debugfs_htt_stats_req(struct ath12k *ar) +{ + struct debug_htt_stats_req *stats_req = ar->debug.htt_stats.stats_req; + u8 type = stats_req->type; + u64 cookie = 0; + int ret, pdev_id = ar->pdev->pdev_id; + struct htt_ext_stats_cfg_params cfg_params = { 0 }; + + init_completion(&stats_req->cmpln); + + stats_req->done = false; + stats_req->pdev_id = pdev_id; + + cookie = FIELD_PREP(HTT_STATS_COOKIE_MSB, HTT_STATS_MAGIC_VALUE) | + FIELD_PREP(HTT_STATS_COOKIE_LSB, pdev_id); + + ret = ath12k_prep_htt_stats_cfg_params(ar, type, stats_req->peer_addr, + &cfg_params); + if (ret) { + ath12k_warn(ar->ab, "failed to set htt stats cfg params: %d\n", ret); + return ret; + } + if (stats_req->override_cfg_param) { + cfg_params.cfg0 = stats_req->cfg_param[0]; + cfg_params.cfg1 = stats_req->cfg_param[1]; + cfg_params.cfg2 = stats_req->cfg_param[2]; + cfg_params.cfg3 = stats_req->cfg_param[3]; + } + + ret = ath12k_dp_tx_htt_h2t_ext_stats_req(ar, type, &cfg_params, cookie); + if (ret) { + ath12k_warn(ar->ab, "failed to send htt stats request: %d\n", ret); + return ret; + } + + while (!wait_for_completion_timeout(&stats_req->cmpln, 3 * HZ)) { + spin_lock_bh(&ar->debug.htt_stats.lock); + if (!stats_req->done) { + stats_req->done = true; + spin_unlock_bh(&ar->debug.htt_stats.lock); + ath12k_warn(ar->ab, "stats request timed out\n"); + return -ETIMEDOUT; + } + spin_unlock_bh(&ar->debug.htt_stats.lock); + } + + return 0; +} + +static int ath12k_open_htt_stats(struct inode *inode, struct file *file) +{ + struct ath12k *ar = inode->i_private; + struct debug_htt_stats_req *stats_req; + u8 type = ar->debug.htt_stats.type; + int ret; + + if (type == ATH12K_DBG_HTT_EXT_STATS_RESET || + type == ATH12K_DBG_HTT_EXT_STATS_PEER_INFO || + type == ATH12K_DBG_HTT_EXT_PEER_CTRL_PATH_TXRX_STATS) + return -EPERM; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON && + ar->ab->fw_mode != ATH12K_FIRMWARE_MODE_FTM) { + ret = -ENETDOWN; + goto err_unlock; + } + + if (ar->debug.htt_stats.stats_req) { + ret = -EAGAIN; + goto err_unlock; + } + + stats_req = vzalloc(sizeof(*stats_req) + ATH12K_HTT_STATS_BUF_SIZE); + if (!stats_req) { + ret = -ENOMEM; + goto err_unlock; + } + + ar->debug.htt_stats.stats_req = stats_req; + stats_req->type = type; + stats_req->cfg_param[0] = ar->debug.htt_stats.cfg_param[0]; + stats_req->cfg_param[1] = ar->debug.htt_stats.cfg_param[1]; + stats_req->cfg_param[2] = ar->debug.htt_stats.cfg_param[2]; + stats_req->cfg_param[3] = ar->debug.htt_stats.cfg_param[3]; + stats_req->override_cfg_param = !!stats_req->cfg_param[0] || + !!stats_req->cfg_param[1] || + !!stats_req->cfg_param[2] || + !!stats_req->cfg_param[3]; + + ret = ath12k_debugfs_htt_stats_req(ar); + if (ret < 0) + goto out; + + file->private_data = stats_req; + + mutex_unlock(&ar->conf_mutex); + + return 0; +out: + vfree(stats_req); + ar->debug.htt_stats.stats_req = NULL; +err_unlock: + mutex_unlock(&ar->conf_mutex); + + return ret; +} + +static int ath12k_release_htt_stats(struct inode *inode, struct file *file) +{ + struct ath12k *ar = inode->i_private; + + mutex_lock(&ar->conf_mutex); + vfree(file->private_data); + ar->debug.htt_stats.stats_req = NULL; + mutex_unlock(&ar->conf_mutex); + + return 0; +} + +static ssize_t ath12k_read_htt_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct debug_htt_stats_req *stats_req = file->private_data; + char *buf; + u32 length = 0; + + buf = stats_req->buf; + length = min_t(u32, stats_req->buf_len, ATH12K_HTT_STATS_BUF_SIZE); + return simple_read_from_buffer(user_buf, count, ppos, buf, length); +} + +static const struct file_operations fops_dump_htt_stats = { + .open = ath12k_open_htt_stats, + .release = ath12k_release_htt_stats, + .read = ath12k_read_htt_stats, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_read_htt_stats_reset(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + char buf[32]; + size_t len; + + len = scnprintf(buf, sizeof(buf), "%u\n", ar->debug.htt_stats.reset); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_write_htt_stats_reset(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath12k *ar = file->private_data; + u8 type; + struct htt_ext_stats_cfg_params cfg_params = { 0 }; + int ret; + + ret = kstrtou8_from_user(user_buf, count, 0, &type); + if (ret) + return ret; + + if (type >= ATH12K_DBG_HTT_NUM_EXT_STATS || + type == ATH12K_DBG_HTT_EXT_STATS_RESET) + return -E2BIG; + + mutex_lock(&ar->conf_mutex); + cfg_params.cfg0 = HTT_STAT_DEFAULT_RESET_START_OFFSET; + cfg_params.cfg1 = 1 << (cfg_params.cfg0 + type); + ret = ath12k_dp_tx_htt_h2t_ext_stats_req(ar, + ATH12K_DBG_HTT_EXT_STATS_RESET, + &cfg_params, + 0ULL); + if (ret) { + ath12k_warn(ar->ab, "failed to send htt stats request: %d\n", ret); + mutex_unlock(&ar->conf_mutex); + return ret; + } + + ar->debug.htt_stats.reset = type; + mutex_unlock(&ar->conf_mutex); + + ret = count; + + return ret; +} + +static const struct file_operations fops_htt_stats_reset = { + .read = ath12k_read_htt_stats_reset, + .write = ath12k_write_htt_stats_reset, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +void ath12k_debugfs_htt_stats_init(struct ath12k *ar) +{ + spin_lock_init(&ar->debug.htt_stats.lock); + debugfs_create_file("htt_stats_type", 0600, ar->debug.debugfs_pdev, + ar, &fops_htt_stats_type); + debugfs_create_file("htt_stats", 0400, ar->debug.debugfs_pdev, + ar, &fops_dump_htt_stats); + debugfs_create_file("htt_stats_reset", 0600, ar->debug.debugfs_pdev, + ar, &fops_htt_stats_reset); +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h 2024-03-18 14:40:14.847741224 +0100 @@ -0,0 +1,4277 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef DEBUG_HTT_STATS_H +#define DEBUG_HTT_STATS_H + +#define HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) +#define HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) +#define HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 +#define HTT_TLV_HDR_LEN 4 + +enum htt_tlv_tag_t { + HTT_STATS_TX_PDEV_CMN_TAG = 0, + HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, + HTT_STATS_TX_PDEV_SIFS_TAG = 2, + HTT_STATS_TX_PDEV_FLUSH_TAG = 3, + HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, + HTT_STATS_STRING_TAG = 5, + HTT_STATS_TX_HWQ_CMN_TAG = 6, + HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, + HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, + HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, + HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, + HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, + HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, + HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, + HTT_STATS_TX_TQM_CMN_TAG = 14, + HTT_STATS_TX_TQM_PDEV_TAG = 15, + HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, + HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, + HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, + HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, + HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, + HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, + HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, + HTT_STATS_TX_DE_CMN_TAG = 23, + HTT_STATS_RING_IF_TAG = 24, + HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, + HTT_STATS_SFM_CMN_TAG = 26, + HTT_STATS_SRING_STATS_TAG = 27, + HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, + HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, + HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, + HTT_STATS_RX_SOC_FW_STATS_TAG = 31, + HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, + HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, + HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, + HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, + HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, + HTT_STATS_TX_SCHED_CMN_TAG = 37, + HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, + HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, + HTT_STATS_RING_IF_CMN_TAG = 40, + HTT_STATS_SFM_CLIENT_USER_TAG = 41, + HTT_STATS_SFM_CLIENT_TAG = 42, + HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, + HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, + HTT_STATS_SRING_CMN_TAG = 45, + HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, + HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, + HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, + HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, + HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, + HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, + HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, + HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, + HTT_STATS_HW_INTR_MISC_TAG = 54, + HTT_STATS_HW_WD_TIMEOUT_TAG = 55, + HTT_STATS_HW_PDEV_ERRS_TAG = 56, + HTT_STATS_COUNTER_NAME_TAG = 57, + HTT_STATS_TX_TID_DETAILS_TAG = 58, + HTT_STATS_RX_TID_DETAILS_TAG = 59, + HTT_STATS_PEER_STATS_CMN_TAG = 60, + HTT_STATS_PEER_DETAILS_TAG = 61, + HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, + HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, + HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, + HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, + HTT_STATS_WHAL_TX_TAG = 66, + HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, + HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, + HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, + HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, + HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, + HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, + HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, + HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, + HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, + HTT_STATS_PDEV_TWT_SESSION_TAG = 76, + HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, + HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, + HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, + HTT_STATS_TX_SOUNDING_STATS_TAG = 80, + HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, + HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, + HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, + HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, + HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, + HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, + HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, + HTT_STATS_PDEV_OBSS_PD_TAG = 88, + HTT_STATS_HW_WAR_TAG = 89, + HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, + HTT_STATS_LATENCY_PROF_STATS_TAG = 91, + HTT_STATS_LATENCY_CTX_TAG = 92, + HTT_STATS_LATENCY_CNT_TAG = 93, + HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, + HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, + HTT_STATS_RX_PDEV_UL_MIMO_USER_STATS_TAG = 96, + HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, + HTT_STATS_RX_FSE_STATS_TAG = 98, + HTT_STATS_PEER_SCHED_STATS_TAG = 99, + HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, + HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, + HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, + HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, + HTT_STATS_TX_PDEV_DL_MU_MIMO_STATS_TAG = 104, + HTT_STATS_TX_PDEV_UL_MU_MIMO_STATS_TAG = 105, + HTT_STATS_TX_PDEV_DL_MU_OFDMA_STATS_TAG = 106, + HTT_STATS_TX_PDEV_UL_MU_OFDMA_STATS_TAG = 107, + HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, + HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG = 109, + HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG = 110, + HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, + HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, + HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, + HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, + HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, + HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, + HTT_STATS_STA_UL_OFDMA_STATS_TAG = 117, + HTT_STATS_VDEV_RTT_RESP_STATS_TAG = 118, + HTT_STATS_PKTLOG_AND_HTT_RING_STATS_TAG = 119, + HTT_STATS_DLPAGER_STATS_TAG = 120, + HTT_STATS_PHY_COUNTERS_TAG = 121, + HTT_STATS_PHY_STATS_TAG = 122, + HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, + HTT_STATS_PHY_RESET_STATS_TAG = 124, + HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, + HTT_STATS_VDEV_TXRX_STATS_HW_STATS_TAG = 126, + HTT_STATS_VDEV_RTT_INIT_STATS_TAG = 127, + HTT_STATS_PER_RATE_STATS_TAG = 128, + HTT_STATS_MU_PPDU_DIST_TAG = 129, + HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, + /* 11be stats */ + HTT_STATS_TX_PDEV_BE_RATE_STATS_TAG = 131, + HTT_STATS_AST_ENTRY_TAG = 132, + HTT_STATS_TX_PDEV_BE_DL_MU_OFDMA_STATS_TAG = 133, + HTT_STATS_TX_PDEV_BE_UL_MU_OFDMA_STATS_TAG = 134, + HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, + HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_BE_STATS_TAG = 136, + HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, + HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, + HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, + HTT_STATS_TX_PDEV_BE_UL_MU_MIMO_STATS_TAG = 140, + HTT_STATS_RX_PDEV_BE_UL_MIMO_USER_STATS_TAG = 141, + HTT_STATS_RX_RING_STATS_TAG = 142, + HTT_STATS_RX_PDEV_BE_UL_TRIG_STATS_TAG = 143, + HTT_STATS_TX_PDEV_SAWF_RATE_STATS_TAG = 144, + HTT_STATS_STRM_GEN_MPDUS_TAG = 145, + HTT_STATS_STRM_GEN_MPDUS_DETAILS_TAG = 146, + HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, + HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, + HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, + HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, + HTT_STATS_TXBF_OFDMA_BE_NDPA_STATS_TAG = 151, + HTT_STATS_TXBF_OFDMA_BE_NDP_STATS_TAG = 152, + HTT_STATS_TXBF_OFDMA_BE_BRP_STATS_TAG = 153, + HTT_STATS_TXBF_OFDMA_BE_STEER_STATS_TAG = 154, + HTT_STATS_DMAC_RESET_STATS_TAG = 155, + HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG = 156, + HTT_STATS_PHY_TPC_STATS_TAG = 157, + HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, + HTT_STATS_ML_PEER_DETAILS_TAG = 159, + HTT_STATS_ML_PEER_EXT_DETAILS_TAG = 160, + HTT_STATS_ML_LINK_INFO_DETAILS_TAG = 161, + HTT_STATS_TX_PDEV_PPDU_DUR_TAG = 162, + HTT_STATS_RX_PDEV_PPDU_DUR_TAG = 163, + HTT_STATS_ODD_PDEV_MANDATORY_TAG = 164, + HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, + HTT_DBG_ODD_MANDATORY_MUMIMO_TAG = 166, + HTT_DBG_ODD_MANDATORY_MUOFDMA_TAG = 167, + HTT_STATS_LATENCY_PROF_CAL_STATS_TAG = 168, + HTT_STATS_TX_PDEV_MUEDCA_PARAMS_STATS_TAG = 169, + HTT_STATS_PDEV_BW_MGR_STATS_TAG = 170, + HTT_STATS_TX_PDEV_AP_EDCA_PARAMS_STATS_TAG = 171, + HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, + HTT_STATS_TXBF_OFDMA_BE_STEER_MPDU_STATS_TAG = 173, + HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, + HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, + HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, + HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, + HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, + HTT_STATS_UMAC_SSR_TAG = 179, + HTT_STATS_MAX_TAG, +}; + +#define HTT_STATS_MAX_STRING_SZ32 4 +#define HTT_STATS_MACID_INVALID 0xff +#define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10 +#define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13 +#define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5 +#define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10 +#define HTT_PDEV_STATS_PPDU_DUR_HIST_BINS 16 +#define HTT_PDEV_STATS_PPDU_DUR_HIST_INTERVAL_US 250 + +enum htt_tx_pdev_underrun_enum { + HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, + HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, + HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, + HTT_TX_PDEV_MAX_URRN_STATS = 3, +}; + +enum htt_ppdu_stats_ru_size { + HTT_PPDU_STATS_RU_26, + HTT_PPDU_STATS_RU_52, + HTT_PPDU_STATS_RU_52_26, + HTT_PPDU_STATS_RU_106, + HTT_PPDU_STATS_RU_106_26, + HTT_PPDU_STATS_RU_242, + HTT_PPDU_STATS_RU_484, + HTT_PPDU_STATS_RU_484_242, + HTT_PPDU_STATS_RU_996, + HTT_PPDU_STATS_RU_996_484, + HTT_PPDU_STATS_RU_996_484_242, + HTT_PPDU_STATS_RU_996x2, + HTT_PPDU_STATS_RU_996x2_484, + HTT_PPDU_STATS_RU_996x3, + HTT_PPDU_STATS_RU_996x3_484, + HTT_PPDU_STATS_RU_996x4, +}; + +#define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 +#define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 +#define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 +#define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 +#define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 +#define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 + +#define HTT_RX_STATS_REFILL_MAX_RING 4 +#define HTT_RX_STATS_RXDMA_MAX_ERR 16 +#define HTT_RX_STATS_FW_DROP_REASON_MAX 16 + +/* Bytes stored in little endian order */ +/* Length should be multiple of DWORD */ +struct htt_stats_string_tlv { + u32 data[0]; /* Can be variable length */ +} __packed; + +#define HTT_STATS_MAC_ID GENMASK(7, 0) + +/* == TX PDEV STATS == */ +struct htt_tx_pdev_stats_cmn_tlv { + u32 mac_id__word; + u32 hw_queued; + u32 hw_reaped; + u32 underrun; + u32 hw_paused; + u32 hw_flush; + u32 hw_filt; + u32 tx_abort; + u32 mpdu_requed; + u32 tx_xretry; + u32 data_rc; + u32 mpdu_dropped_xretry; + u32 illgl_rate_phy_err; + u32 cont_xretry; + u32 tx_timeout; + u32 pdev_resets; + u32 phy_underrun; + u32 txop_ovf; + u32 seq_posted; + u32 seq_failed_queueing; + u32 seq_completed; + u32 seq_restarted; + u32 mu_seq_posted; + u32 seq_switch_hw_paused; + u32 next_seq_posted_dsr; + u32 seq_posted_isr; + u32 seq_ctrl_cached; + u32 mpdu_count_tqm; + u32 msdu_count_tqm; + u32 mpdu_removed_tqm; + u32 msdu_removed_tqm; + u32 mpdus_sw_flush; + u32 mpdus_hw_filter; + u32 mpdus_truncated; + u32 mpdus_ack_failed; + u32 mpdus_expired; + u32 mpdus_seq_hw_retry; + u32 ack_tlv_proc; + u32 coex_abort_mpdu_cnt_valid; + u32 coex_abort_mpdu_cnt; + u32 num_total_ppdus_tried_ota; + u32 num_data_ppdus_tried_ota; + u32 local_ctrl_mgmt_enqued; + u32 local_ctrl_mgmt_freed; + u32 local_data_enqued; + u32 local_data_freed; + u32 mpdu_tried; + u32 isr_wait_seq_posted; + + u32 tx_active_dur_us_low; + u32 tx_active_dur_us_high; + u32 remove_mpdus_max_retries; + u32 comp_delivered; + u32 ppdu_ok; + u32 self_triggers; + u32 tx_time_dur_data; + u32 seq_qdepth_repost_stop; + u32 mu_seq_min_msdu_repost_stop; + u32 seq_min_msdu_repost_stop; + u32 seq_txop_repost_stop; + u32 next_seq_cancel; + u32 fes_offsets_err_cnt; + u32 num_mu_peer_blacklisted; + u32 mu_ofdma_seq_posted; + u32 ul_mumimo_seq_posted; + u32 ul_ofdma_seq_posted; + + u32 thermal_suspend_cnt; + u32 dfs_suspend_cnt; + u32 tx_abort_suspend_cnt; + u32 tgt_specific_opaque_txq_suspend_info; + u32 last_suspend_reason; +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_pdev_stats_urrn_tlv_v { + u32 urrn_stats[0]; /* HTT_TX_PDEV_MAX_URRN_STATS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_pdev_stats_flush_tlv_v { + u32 flush_errs[0]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ +}; + +#define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(u32) * (_num_elems)) +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_pdev_stats_mlo_abort_tlv_v { + u32 mlo_abort_cnt[0]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ +}; + +#define HTT_TX_PDEV_STATS_MLO_TXOP_ABORT_TLV_SZ(_num_elems) (sizeof(u32) * (_num_elems)) +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_pdev_stats_mlo_txop_abort_tlv_v { + u32 mlo_txop_abort_cnt[0]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_pdev_stats_sifs_tlv_v { + u32 sifs_status[0]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_pdev_stats_phy_err_tlv_v { + u32 phy_errs[0]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_pdev_stats_sifs_hist_tlv_v { + u32 sifs_hist_status[0]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */ +}; + +struct htt_tx_pdev_stats_tx_ppdu_stats_tlv_v { + u32 num_data_ppdus_legacy_su; + u32 num_data_ppdus_ac_su; + u32 num_data_ppdus_ax_su; + u32 num_data_ppdus_ac_su_txbf; + u32 num_data_ppdus_ax_su_txbf; +}; + +/* NOTE: Variable length TLV, use length spec to infer array size . + * + * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ. + * The tries here is the count of the MPDUS within a PPDU that the + * HW had attempted to transmit on air, for the HWSCH Schedule + * command submitted by FW.It is not the retry attempts. + * The histogram bins are 0-29, 30-59, 60-89 and so on. The are + * 10 bins in this histogram. They are defined in FW using the + * following macros + * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 + * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 + */ +struct htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v { + u32 hist_bin_size; + u32 tried_mpdu_cnt_hist[]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ +}; + +/* == SOC ERROR STATS == */ + +/* =============== PDEV ERROR STATS ============== */ +#define HTT_STATS_MAX_HW_INTR_NAME_LEN 8 +struct htt_hw_stats_intr_misc_tlv { + /* Stored as little endian */ + u8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN]; + u32 mask; + u32 count; +}; + +#define HTT_STATS_MAX_HW_MODULE_NAME_LEN 8 +struct htt_hw_stats_wd_timeout_tlv { + /* Stored as little endian */ + u8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN]; + u32 count; +}; + +struct htt_hw_stats_pdev_errs_tlv { + u32 mac_id__word; /* BIT [ 7 : 0] : mac_id */ + u32 tx_abort; + u32 tx_abort_fail_count; + u32 rx_abort; + u32 rx_abort_fail_count; + u32 warm_reset; + u32 cold_reset; + u32 tx_flush; + u32 tx_glb_reset; + u32 tx_txq_reset; + u32 rx_timeout_reset; + u32 mac_cold_reset_restore_cal; + u32 mac_cold_reset; + u32 mac_warm_reset; + u32 mac_only_reset; + u32 phy_warm_reset; + u32 phy_warm_reset_ucode_trig; + u32 mac_warm_reset_restore_cal; + u32 mac_sfm_reset; + u32 phy_warm_reset_m3_ssr; + u32 phy_warm_reset_reason_phy_m3; + u32 phy_warm_reset_reason_tx_hw_stuck; + u32 phy_warm_reset_reason_num_cca_rx_frame_stuck; + u32 phy_warm_reset_reason_wal_rx_recovery_rst_rx_busy; + u32 phy_warm_reset_reason_wal_rx_recovery_rst_mac_hang; + u32 phy_warm_reset_reason_mac_reset_converted_phy_reset; + u32 wal_rx_recovery_rst_mac_hang_count; + u32 wal_rx_recovery_rst_known_sig_count; + u32 wal_rx_recovery_rst_no_rx_count; + u32 wal_rx_recovery_rst_no_rx_consecutive_count; + u32 wal_rx_recovery_rst_rx_busy_count; + u32 wal_rx_recovery_rst_phy_mac_hang_count; + u32 rx_flush_cnt; + u32 phy_warm_reset_reason_tx_lifetime_expiry_cca_stuck; + u32 phy_warm_reset_reason_tx_consecutive_flush9_war; + u32 phy_warm_reset_reason_tx_hwsch_reset_war; + u32 phy_warm_reset_reason_hwsch_wdog_or_cca_wdog_war; + u32 fw_rx_rings_reset; +}; + +struct htt_hw_stats_whal_tx_tlv { + u32 mac_id__word; + u32 last_unpause_ppdu_id; + u32 hwsch_unpause_wait_tqm_write; + u32 hwsch_dummy_tlv_skipped; + u32 hwsch_misaligned_offset_received; + u32 hwsch_reset_count; + u32 hwsch_dev_reset_war; + u32 hwsch_delayed_pause; + u32 hwsch_long_delayed_pause; + u32 sch_rx_ppdu_no_response; + u32 sch_selfgen_response; + u32 sch_rx_sifs_resp_trigger; +}; + +/* ============ PEER STATS ============ */ +#define HTT_MSDU_FLOW_STATS_TX_FLOW_NO GENMASK(15, 0) +#define HTT_MSDU_FLOW_STATS_TID_NUM GENMASK(19, 16) +#define HTT_MSDU_FLOW_STATS_DROP_RULE BIT(20) + +struct htt_msdu_flow_stats_tlv { + u32 last_update_timestamp; + u32 last_add_timestamp; + u32 last_remove_timestamp; + u32 total_processed_msdu_count; + u32 cur_msdu_count_in_flowq; + u32 sw_peer_id; + u32 tx_flow_no__tid_num__drop_rule; + u32 last_cycle_enqueue_count; + u32 last_cycle_dequeue_count; + u32 last_cycle_drop_count; + u32 current_drop_th; +}; + +#define MAX_HTT_TID_NAME 8 + +#define HTT_TX_TID_STATS_SW_PEER_ID GENMASK(15, 0) +#define HTT_TX_TID_STATS_TID_NUM GENMASK(31, 16) +#define HTT_TX_TID_STATS_NUM_SCHED_PENDING GENMASK(7, 0) +#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ GENMASK(15, 8) + +/* Tidq stats */ +struct htt_tx_tid_stats_tlv { + /* Stored as little endian */ + u8 tid_name[MAX_HTT_TID_NAME]; + u32 sw_peer_id__tid_num; + u32 num_sched_pending__num_ppdu_in_hwq; + u32 tid_flags; + u32 hw_queued; + u32 hw_reaped; + u32 mpdus_hw_filter; + + u32 qdepth_bytes; + u32 qdepth_num_msdu; + u32 qdepth_num_mpdu; + u32 last_scheduled_tsmp; + u32 pause_module_id; + u32 block_module_id; + u32 tid_tx_airtime; +}; + +#define HTT_TX_TID_STATS_V1_SW_PEER_ID GENMASK(15, 0) +#define HTT_TX_TID_STATS_V1_TID_NUM GENMASK(31, 16) +#define HTT_TX_TID_STATS_V1_NUM_SCHED_PENDING GENMASK(7, 0) +#define HTT_TX_TID_STATS_V1_NUM_PPDU_IN_HWQ GENMASK(15, 8) + +/* Tidq stats */ +struct htt_tx_tid_stats_v1_tlv { + /* Stored as little endian */ + u8 tid_name[MAX_HTT_TID_NAME]; + u32 sw_peer_id__tid_num; + u32 num_sched_pending__num_ppdu_in_hwq; + u32 tid_flags; + u32 max_qdepth_bytes; + u32 max_qdepth_n_msdus; + u32 rsvd; + + u32 qdepth_bytes; + u32 qdepth_num_msdu; + u32 qdepth_num_mpdu; + u32 last_scheduled_tsmp; + u32 pause_module_id; + u32 block_module_id; + u32 tid_tx_airtime; + u32 allow_n_flags; + u32 sendn_frms_allowed; +}; + +#define HTT_RX_TID_STATS_SW_PEER_ID GENMASK(15, 0) +#define HTT_RX_TID_STATS_TID_NUM GENMASK(31, 16) + +struct htt_rx_tid_stats_tlv { + u32 sw_peer_id__tid_num; + u8 tid_name[MAX_HTT_TID_NAME]; + u32 dup_in_reorder; + u32 dup_past_outside_window; + u32 dup_past_within_window; + u32 rxdesc_err_decrypt; + u32 tid_rx_airtime; +}; + +#define HTT_MAX_COUNTER_NAME 8 +struct htt_counter_tlv { + u8 counter_name[HTT_MAX_COUNTER_NAME]; + u32 count; +}; + +struct htt_peer_stats_cmn_tlv { + u32 ppdu_cnt; + u32 mpdu_cnt; + u32 msdu_cnt; + u32 pause_bitmap; + u32 block_bitmap; + u32 current_timestamp; + u32 peer_tx_airtime; + u32 peer_rx_airtime; + s32 rssi; + u32 peer_enqueued_count_low; + u32 peer_enqueued_count_high; + u32 peer_dequeued_count_low; + u32 peer_dequeued_count_high; + u32 peer_dropped_count_low; + u32 peer_dropped_count_high; + u32 ppdu_transmitted_bytes_low; + u32 ppdu_transmitted_bytes_high; + u32 peer_ttl_removed_count; + u32 inactive_time; + u32 remove_mpdus_max_retries; +}; + +#define HTT_PEER_DETAILS_VDEV_ID GENMASK(7, 0) +#define HTT_PEER_DETAILS_PDEV_ID GENMASK(15, 8) +#define HTT_PEER_DETAILS_AST_IDX GENMASK(31, 16) + +struct htt_peer_details_tlv { + u32 peer_type; + u32 sw_peer_id; + u32 vdev_pdev_ast_idx; + struct htt_mac_addr mac_addr; + u32 peer_flags; + u32 qpeer_flags; +}; + +struct htt_ast_entry_tlv { + u32 sw_peer_id; + u32 ast_index; + u8 pdev_id; + u8 vdev_id; + u8 next_hop; + u8 mcast; + u8 monitor_direct; + u8 mesh_sta; + u8 mec; + u8 intra_bss; + u32 reserved; + struct htt_mac_addr mac_addr; +}; + +enum htt_stats_param_type { + HTT_STATS_PREAM_OFDM, + HTT_STATS_PREAM_CCK, + HTT_STATS_PREAM_HT, + HTT_STATS_PREAM_VHT, + HTT_STATS_PREAM_HE, + HTT_STATS_PREAM_EHT, + HTT_STATS_PREAM_RSVD1, + + HTT_STATS_PREAM_COUNT, +}; + +enum htt_stats_direction { + HTT_STATS_DIRECTION_TX, + HTT_STATS_DIRECTION_RX, +}; + +enum htt_stats_ppdu_type { + HTT_STATS_PPDU_TYPE_MODE_SU, + HTT_STATS_PPDU_TYPE_DL_MU_MIMO, + HTT_STATS_PPDU_TYPE_UL_MU_MIMO, + HTT_STATS_PPDU_TYPE_DL_MU_OFDMA, + HTT_STATS_PPDU_TYPE_UL_MU_OFDMA, +}; + +#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 +#define HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 +#define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4 +#define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5 +#define HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS 4 +#define HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 +#define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4 +#define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 +#define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT + +struct htt_tx_peer_rate_stats_tlv { + u32 tx_ldpc; + u32 rts_cnt; + u32 ack_rssi; + + u32 tx_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; + u32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; + u32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; + /* element 0,1, ...7 -> NSS 1,2, ...8 */ + u32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; + /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + u32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; + u32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; + u32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES]; + + /* Counters to track number of tx packets in each GI + * (400us, 800us, 1600us & 3200us) in each mcs (0-11) + */ + u32 tx_gi[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_MCS_COUNTERS]; + + /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ + u32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; + +}; + +#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 +#define HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 +#define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 +#define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 +#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 +#define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8 +#define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT + +struct htt_rx_peer_rate_stats_tlv { + u32 nsts; + + /* Number of rx ldpc packets */ + u32 rx_ldpc; + /* Number of rx rts packets */ + u32 rts_cnt; + + u32 rssi_mgmt; /* units = dB above noise floor */ + u32 rssi_data; /* units = dB above noise floor */ + u32 rssi_comb; /* units = dB above noise floor */ + u32 rx_mcs[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; + /* element 0,1, ...7 -> NSS 1,2, ...8 */ + u32 rx_nss[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; + u32 rx_dcm[HTT_RX_PEER_STATS_NUM_DCM_COUNTERS]; + u32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; + /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + u32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; + u32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES]; + /* units = dB above noise floor */ + u8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; + + /* Counters to track number of rx packets in each GI in each mcs (0-11) */ + u32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS] + [HTT_RX_PEER_STATS_NUM_MCS_COUNTERS]; + u32 rx_ulofdma_non_data_ppdu; + u32 rx_ulofdma_data_ppdu; + u32 rx_ulofdma_mpdu_ok; + u32 rx_ulofdma_mpdu_fail; + s8 rx_ul_fd_rssi[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; + + u32 per_chain_rssi_pkt_type; + s8 rx_per_chain_rssi_in_dbm[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; + u32 rx_ulmumimo_non_data_ppdu; + u32 rx_ulmumimo_data_ppdu; + u32 rx_ulmumimo_mpdu_ok; + u32 rx_ulmumimo_mpdu_fail; + u8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; + + /* Stats for MCS 12/13 */ + u32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS] + [HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; +}; + +enum htt_peer_stats_req_mode { + HTT_PEER_STATS_REQ_MODE_NO_QUERY, + HTT_PEER_STATS_REQ_MODE_QUERY_TQM, + HTT_PEER_STATS_REQ_MODE_FLUSH_TQM, +}; + +enum htt_peer_stats_tlv_enum { + HTT_PEER_STATS_CMN_TLV = 0, + HTT_PEER_DETAILS_TLV = 1, + HTT_TX_PEER_RATE_STATS_TLV = 2, + HTT_RX_PEER_RATE_STATS_TLV = 3, + HTT_TX_TID_STATS_TLV = 4, + HTT_RX_TID_STATS_TLV = 5, + HTT_MSDU_FLOW_STATS_TLV = 6, + HTT_PEER_SCHED_STATS_TLV = 7, + + HTT_PEER_STATS_MAX_TLV = 31, +}; + +/* =========== MUMIMO HWQ stats =========== */ +/* MU MIMO stats per hwQ */ +struct htt_tx_hwq_mu_mimo_sch_stats_tlv { + u32 mu_mimo_sch_posted; + u32 mu_mimo_sch_failed; + u32 mu_mimo_ppdu_posted; +}; + +struct htt_tx_hwq_mu_mimo_mpdu_stats_tlv { + u32 mu_mimo_mpdus_queued_usr; + u32 mu_mimo_mpdus_tried_usr; + u32 mu_mimo_mpdus_failed_usr; + u32 mu_mimo_mpdus_requeued_usr; + u32 mu_mimo_err_no_ba_usr; + u32 mu_mimo_mpdu_underrun_usr; + u32 mu_mimo_ampdu_underrun_usr; +}; + +#define HTT_TX_HWQ_STATS_MAC_ID GENMASK(7, 0) +#define HTT_TX_HWQ_STATS_HWQ_ID GENMASK(15, 8) + +struct htt_tx_hwq_mu_mimo_cmn_stats_tlv { + u32 mac_id__hwq_id__word; +}; + +/* == TX HWQ STATS == */ +struct htt_tx_hwq_stats_cmn_tlv { + u32 mac_id__hwq_id__word; + + /* PPDU level stats */ + u32 xretry; + u32 underrun_cnt; + u32 flush_cnt; + u32 filt_cnt; + u32 null_mpdu_bmap; + u32 user_ack_failure; + u32 ack_tlv_proc; + u32 sched_id_proc; + u32 null_mpdu_tx_count; + u32 mpdu_bmap_not_recvd; + + /* Selfgen stats per hwQ */ + u32 num_bar; + u32 rts; + u32 cts2self; + u32 qos_null; + + /* MPDU level stats */ + u32 mpdu_tried_cnt; + u32 mpdu_queued_cnt; + u32 mpdu_ack_fail_cnt; + u32 mpdu_filt_cnt; + u32 false_mpdu_ack_count; + + u32 txq_timeout; +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_hwq_difs_latency_stats_tlv_v { + u32 hist_intvl; + /* histogram of ppdu post to hwsch - > cmd status received */ + u32 difs_latency_hist[]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_hwq_cmd_result_stats_tlv_v { + /* Histogram of sched cmd result */ + u32 cmd_result[0]; /* HTT_TX_HWQ_MAX_CMD_RESULT_STATS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_hwq_cmd_stall_stats_tlv_v { + /* Histogram of various pause conitions */ + u32 cmd_stall_status[0]; /* HTT_TX_HWQ_MAX_CMD_STALL_STATS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_hwq_fes_result_stats_tlv_v { + /* Histogram of number of user fes result */ + u32 fes_result[0]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size + * + * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ. + * The tries here is the count of the MPDUS within a PPDU that the HW + * had attempted to transmit on air, for the HWSCH Schedule command + * submitted by FW in this HWQ .It is not the retry attempts. The + * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins + * in this histogram. + * they are defined in FW using the following macros + * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9 + * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30 + */ +struct htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v { + u32 hist_bin_size; + /* Histogram of number of mpdus on tried mpdu */ + u32 tried_mpdu_cnt_hist[]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size + * + * The txop_used_cnt_hist is the histogram of txop per burst. After + * completing the burst, we identify the txop used in the burst and + * incr the corresponding bin. + * Each bin represents 1ms & we have 10 bins in this histogram. + * they are deined in FW using the following macros + * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10 + * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms ) + */ +struct htt_tx_hwq_txop_used_cnt_hist_tlv_v { + /* Histogram of txop used cnt */ + u32 txop_used_cnt_hist[0]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */ +}; + +/* == TX SELFGEN STATS == */ + +enum htt_tx_mumimo_grp_invalid_reason_code_stats { + HTT_TX_MUMIMO_GRP_VALID, + HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, + HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, + HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, + HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, + HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, + HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, + HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, + HTT_TX_MUMIMO_GRP_INVALID, + HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, + HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, +}; + +#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 +#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 +#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 +#define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 +#define HTT_STATS_MAX_MUMIMO_GRP_SZ 8 +#define HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 +#define HTT_STATS_MAX_INVALID_REASON_CODE \ + HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE +/* Reasons stated in htt_tx_mumimo_grp_invalid_reason_code_stats */ +#define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ + (HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE) + +struct htt_tx_selfgen_cmn_stats_tlv { + u32 mac_id__word; + u32 su_bar; + u32 rts; + u32 cts2self; + u32 qos_null; + u32 delayed_bar_1; /* MU user 1 */ + u32 delayed_bar_2; /* MU user 2 */ + u32 delayed_bar_3; /* MU user 3 */ + u32 delayed_bar_4; /* MU user 4 */ + u32 delayed_bar_5; /* MU user 5 */ + u32 delayed_bar_6; /* MU user 6 */ + u32 delayed_bar_7; /* MU user 7 */ + u32 bar_with_tqm_head_seq_num; + u32 bar_with_tid_seq_num; + u32 su_sw_rts_queued; + u32 su_sw_rts_tried; + u32 su_sw_rts_err; + u32 su_sw_rts_flushed; + u32 su_sw_rts_rcvd_cts_diff_bw; +}; + +struct htt_tx_selfgen_ac_stats_tlv { + /* 11AC */ + u32 ac_su_ndpa; + u32 ac_su_ndp; + u32 ac_mu_mimo_ndpa; + u32 ac_mu_mimo_ndp; + u32 ac_mu_mimo_brpoll_1; + u32 ac_mu_mimo_brpoll_2; + u32 ac_mu_mimo_brpoll_3; + u32 ac_su_ndpa_queued; + u32 ac_su_ndp_queued; + u32 ac_mu_mimo_ndpa_queued; + u32 ac_mu_mimo_ndp_queued; + u32 ac_mu_mimo_brpoll_1_queued; + u32 ac_mu_mimo_brpoll_2_queued; + u32 ac_mu_mimo_brpoll_3_queued; +}; + +struct htt_tx_selfgen_ax_stats_tlv { + /* 11AX */ + u32 ax_su_ndpa; + u32 ax_su_ndp; + u32 ax_mu_mimo_ndpa; + u32 ax_mu_mimo_ndp; + union { + struct { + /* deprecated old names */ + u32 ax_mu_mimo_brpoll_1; + u32 ax_mu_mimo_brpoll_2; + u32 ax_mu_mimo_brpoll_3; + u32 ax_mu_mimo_brpoll_4; + u32 ax_mu_mimo_brpoll_5; + u32 ax_mu_mimo_brpoll_6; + u32 ax_mu_mimo_brpoll_7; + }; + u32 ax_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; + }; + u32 ax_basic_trigger; + u32 ax_bsr_trigger; + u32 ax_mu_bar_trigger; + u32 ax_mu_rts_trigger; + u32 ax_su_ndpa_queued; + u32 ax_su_ndp_queued; + u32 ax_mu_mimo_ndpa_queued; + u32 ax_mu_mimo_ndp_queued; + u32 ax_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; + u32 ax_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; +}; + +struct htt_tx_selfgen_ac_err_stats_tlv { + /* 11AC error stats */ + u32 ac_su_ndp_err; + u32 ac_su_ndpa_err; + u32 ac_mu_mimo_ndpa_err; + u32 ac_mu_mimo_ndp_err; + u32 ac_mu_mimo_brp1_err; + u32 ac_mu_mimo_brp2_err; + u32 ac_mu_mimo_brp3_err; + u32 ac_su_ndp_flushed; + u32 ac_su_ndpa_flushed; + u32 ac_mu_mimo_ndpa_flushed; + u32 ac_mu_mimo_ndp_flushed; + u32 ac_mu_mimo_brp1_flushed; + u32 ac_mu_mimo_brp2_flushed; + u32 ac_mu_mimo_brp3_flushed; +}; + +struct htt_tx_selfgen_ax_err_stats_tlv { + /* 11AX error stats */ + u32 ax_su_ndp_err; + u32 ax_su_ndpa_err; + u32 ax_mu_mimo_ndpa_err; + u32 ax_mu_mimo_ndp_err; + union { + struct { + /* deprecated old names */ + u32 ax_mu_mimo_brp1_err; + u32 ax_mu_mimo_brp2_err; + u32 ax_mu_mimo_brp3_err; + u32 ax_mu_mimo_brp4_err; + u32 ax_mu_mimo_brp5_err; + u32 ax_mu_mimo_brp6_err; + u32 ax_mu_mimo_brp7_err; + }; + u32 ax_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; +}; + u32 ax_basic_trigger_err; + u32 ax_bsr_trigger_err; + u32 ax_mu_bar_trigger_err; + u32 ax_mu_rts_trigger_err; + u32 ax_ulmumimo_trigger_err; + u32 ax_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + u32 ax_su_ndpa_flushed; + u32 ax_su_ndp_flushed; + u32 ax_mu_mimo_ndpa_flushed; + u32 ax_mu_mimo_ndp_flushed; + u32 ax_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; + u32 ax_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; +}; + +/* == TX MU STATS == */ +#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 +#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 +#define HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS 8 +#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 +#define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 +#define HTT_STATS_MAX_MUMIMO_GRP_SZ 8 + +struct htt_tx_pdev_mu_mimo_sch_stats_tlv { + /* mu-mimo sw sched cmd stats */ + u32 mu_mimo_sch_posted; + u32 mu_mimo_sch_failed; + /* MU PPDU stats per hwQ */ + u32 mu_mimo_ppdu_posted; + /* + * Counts the number of users in each transmission of + * the given TX mode. + * + * Index is the number of users - 1. + */ + u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; + u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + u32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_mumimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; + u32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; + u32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; + u32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + u32 be_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; + u32 be_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; + u32 ac_mu_mimo_sch_posted_per_grp_sz_ext[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; +}; + +struct htt_tx_pdev_mumimo_grp_stats_tlv { + u32 dl_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ]; + u32 dl_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + u32 dl_mumimo_grp_eligible[HTT_STATS_MAX_MUMIMO_GRP_SZ]; + u32 dl_mumimo_grp_ineligible[HTT_STATS_MAX_MUMIMO_GRP_SZ]; + u32 dl_mumimo_grp_invalid[HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; + u32 dl_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS]; + u32 ul_mumimo_grp_best_grp_size[HTT_STATS_MAX_MUMIMO_GRP_SZ]; + u32 ul_mumimo_grp_best_num_usrs[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + u32 ul_mumimo_grp_tputs[HTT_STATS_MUMIMO_TPUT_NUM_BINS]; +}; + +struct htt_tx_pdev_mu_mimo_mpdu_stats_tlv { + u32 mu_mimo_mpdus_queued_usr; + u32 mu_mimo_mpdus_tried_usr; + u32 mu_mimo_mpdus_failed_usr; + u32 mu_mimo_mpdus_requeued_usr; + u32 mu_mimo_err_no_ba_usr; + u32 mu_mimo_mpdu_underrun_usr; + u32 mu_mimo_ampdu_underrun_usr; + + u32 ax_mu_mimo_mpdus_queued_usr; + u32 ax_mu_mimo_mpdus_tried_usr; + u32 ax_mu_mimo_mpdus_failed_usr; + u32 ax_mu_mimo_mpdus_requeued_usr; + u32 ax_mu_mimo_err_no_ba_usr; + u32 ax_mu_mimo_mpdu_underrun_usr; + u32 ax_mu_mimo_ampdu_underrun_usr; + + u32 ax_ofdma_mpdus_queued_usr; + u32 ax_ofdma_mpdus_tried_usr; + u32 ax_ofdma_mpdus_failed_usr; + u32 ax_ofdma_mpdus_requeued_usr; + u32 ax_ofdma_err_no_ba_usr; + u32 ax_ofdma_mpdu_underrun_usr; + u32 ax_ofdma_ampdu_underrun_usr; +}; + +/* [0]- nr4 , [1]- nr8 */ +#define HTT_STATS_NUM_NR_BINS 2 +/* Termination status stated in htt_tx_wal_tx_isr_sched_status */ +#define HTT_STATS_MAX_NUM_SCHED_STATUS 9 +#define HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 +#define HTT_STATS_MAX_NUM_SCHED_STATUS_WORDS \ + (HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_SCHED_STATUS) +#define HTT_STATS_MAX_MU_PPDU_PER_BURST_WORDS \ + (HTT_STATS_NUM_NR_BINS * HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) + +enum htt_stats_hw_mode { + HTT_STATS_HWMODE_AC = 0, + HTT_STATS_HWMODE_AX = 1, +}; + +struct htt_tx_pdev_mu_ppdu_dist_stats_tlv_v { + u32 hw_mode; /* HTT_STATS_HWMODE_xx */ + u32 mu_mimo_num_seq_term_status[HTT_STATS_MAX_MU_PPDU_PER_BURST_WORDS]; + u32 mu_mimo_num_ppdu_completed_per_burst[HTT_STATS_MAX_MU_PPDU_PER_BURST_WORDS]; + u32 mu_mimo_num_seq_posted[HTT_STATS_NUM_NR_BINS]; + u32 mu_mimo_num_ppdu_posted_per_burst[HTT_STATS_MAX_MU_PPDU_PER_BURST_WORDS]; +}; + +#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 +#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 +#define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 + +struct htt_tx_pdev_mpdu_stats_tlv { + /* mpdu level stats */ + u32 mpdus_queued_usr; + u32 mpdus_tried_usr; + u32 mpdus_failed_usr; + u32 mpdus_requeued_usr; + u32 err_no_ba_usr; + u32 mpdu_underrun_usr; + u32 ampdu_underrun_usr; + u32 user_index; + u32 tx_sched_mode; /* HTT_STATS_TX_SCHED_MODE_xxx */ +}; + +/* == TX SCHED STATS == */ +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_sched_txq_cmd_posted_tlv_v { + u32 sched_cmd_posted[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_sched_txq_cmd_reaped_tlv_v { + u32 sched_cmd_reaped[0]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_sched_txq_sched_order_su_tlv_v { + u32 sched_order_su[0]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ +}; + +enum htt_sched_txq_sched_ineligibility_tlv_enum { + HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, + HTT_SCHED_TID_SKIP_NOTIFY_MPDU, + HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, + HTT_SCHED_TID_SKIP_SCHED_DISABLED, + HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, + HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, + + HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, + HTT_SCHED_TID_SKIP_NO_ENQ, + HTT_SCHED_TID_SKIP_LOW_ENQ, + HTT_SCHED_TID_SKIP_PAUSED, + HTT_SCHED_TID_SKIP_UL, + HTT_SCHED_TID_REMOVE_PAUSED, + HTT_SCHED_TID_REMOVE_NO_ENQ, + HTT_SCHED_TID_REMOVE_UL, + HTT_SCHED_TID_QUERY, + HTT_SCHED_TID_SU_ONLY, + HTT_SCHED_TID_ELIGIBLE, + HTT_SCHED_INELIGIBILITY_MAX, +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_sched_txq_sched_ineligibility_tlv_v { + /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ + u32 sched_ineligibility[0]; +}; + +#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) +#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) + +struct htt_tx_pdev_stats_sched_per_txq_tlv { + u32 mac_id__txq_id__word; + u32 sched_policy; + u32 last_sched_cmd_posted_timestamp; + u32 last_sched_cmd_compl_timestamp; + u32 sched_2_tac_lwm_count; + u32 sched_2_tac_ring_full; + u32 sched_cmd_post_failure; + u32 num_active_tids; + u32 num_ps_schedules; + u32 sched_cmds_pending; + u32 num_tid_register; + u32 num_tid_unregister; + u32 num_qstats_queried; + u32 qstats_update_pending; + u32 last_qstats_query_timestamp; + u32 num_tqm_cmdq_full; + u32 num_de_sched_algo_trigger; + u32 num_rt_sched_algo_trigger; + u32 num_tqm_sched_algo_trigger; + u32 notify_sched; + u32 dur_based_sendn_term; + u32 su_notify2_sched; + u32 su_optimal_queued_msdus_sched; + u32 su_delay_timeout_sched; + u32 su_min_txtime_sched_delay; + u32 su_no_delay; + u32 num_supercycles; + u32 num_subcycles_with_sort; + u32 num_subcycles_no_sort; +}; + +struct htt_stats_tx_sched_cmn_tlv { + /* BIT [ 7 : 0] :- mac_id + * BIT [31 : 8] :- reserved + */ + u32 mac_id__word; + /* Current timestamp */ + u32 current_timestamp; +}; + +/* == TQM STATS == */ +#define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16 +#define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 +#define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_tqm_gen_mpdu_stats_tlv_v { + u32 gen_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_tqm_list_mpdu_stats_tlv_v { + u32 list_mpdu_end_reason[0]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_tx_tqm_list_mpdu_cnt_tlv_v { + u32 list_mpdu_cnt_hist[0]; + /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */ +}; + +struct htt_tx_tqm_pdev_stats_tlv_v { + u32 msdu_count; + u32 mpdu_count; + u32 remove_msdu; + u32 remove_mpdu; + u32 remove_msdu_ttl; + u32 send_bar; + u32 bar_sync; + u32 notify_mpdu; + u32 sync_cmd; + u32 write_cmd; + u32 hwsch_trigger; + u32 ack_tlv_proc; + u32 gen_mpdu_cmd; + u32 gen_list_cmd; + u32 remove_mpdu_cmd; + u32 remove_mpdu_tried_cmd; + u32 mpdu_queue_stats_cmd; + u32 mpdu_head_info_cmd; + u32 msdu_flow_stats_cmd; + u32 remove_msdu_cmd; + u32 remove_msdu_ttl_cmd; + u32 flush_cache_cmd; + u32 update_mpduq_cmd; + u32 enqueue; + u32 enqueue_notify; + u32 notify_mpdu_at_head; + u32 notify_mpdu_state_valid; + /* + * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued + * the flow is non empty), if the number of MSDUs is greater than the threshold, + * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are + * for non-UDP MSDUs. + * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented + * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented + * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented + * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented + * + * Notify signifies that we trigger the scheduler. + */ + u32 sched_udp_notify1; + u32 sched_udp_notify2; + u32 sched_nonudp_notify1; + u32 sched_nonudp_notify2; +}; + +struct htt_tx_tqm_cmn_stats_tlv { + u32 mac_id__word; + u32 max_cmdq_id; + u32 list_mpdu_cnt_hist_intvl; + + /* Global stats */ + u32 add_msdu; + u32 q_empty; + u32 q_not_empty; + u32 drop_notification; + u32 desc_threshold; + u32 hwsch_tqm_invalid_status; + u32 missed_tqm_gen_mpdus; + u32 tqm_active_tids; + u32 tqm_inactive_tids; + u32 tqm_active_msduq_flows; +}; + +struct htt_tx_tqm_error_stats_tlv { + /* Error stats */ + u32 q_empty_failure; + u32 q_not_empty_failure; + u32 add_msdu_failure; + /* TQM reset debug stats */ + u32 tqm_cache_ctl_err; + u32 tqm_soft_reset; + u32 tqm_reset_total_num_in_use_link_descs; + u32 tqm_reset_worst_case_num_lost_link_descs; + u32 tqm_reset_worst_case_num_lost_host_tx_bufs_count; + u32 tqm_reset_num_in_use_link_descs_internal_tqm; + u32 tqm_reset_num_in_use_link_descs_wbm_idle_link_ring; + u32 tqm_reset_time_to_tqm_hang_delta_ms; + u32 tqm_reset_recovery_time_ms; + u32 tqm_reset_num_peers_hdl; + u32 tqm_reset_cumm_dirty_hw_mpduq_proc_cnt; + u32 tqm_reset_cumm_dirty_hw_msduq_proc; + u32 tqm_reset_flush_cache_cmd_su_cnt; + u32 tqm_reset_flush_cache_cmd_other_cnt; + u32 tqm_reset_flush_cache_cmd_trig_type; + u32 tqm_reset_flush_cache_cmd_trig_cfg; + u32 tqm_reset_flush_cache_cmd_skip_cmd_status_null; +}; + +/* == TQM CMDQ stats == */ +#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID GENMASK(7, 0) +#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID GENMASK(15, 8) + +struct htt_tx_tqm_cmdq_status_tlv { + u32 mac_id__cmdq_id__word; + u32 sync_cmd; + u32 write_cmd; + u32 gen_mpdu_cmd; + u32 mpdu_queue_stats_cmd; + u32 mpdu_head_info_cmd; + u32 msdu_flow_stats_cmd; + u32 remove_mpdu_cmd; + u32 remove_msdu_cmd; + u32 flush_cache_cmd; + u32 update_mpduq_cmd; + u32 update_msduq_cmd; +}; + +/* == TX-DE STATS == */ +/* Structures for tx de stats */ +struct htt_tx_de_eapol_packets_stats_tlv { + u32 m1_packets; + u32 m2_packets; + u32 m3_packets; + u32 m4_packets; + u32 g1_packets; + u32 g2_packets; + u32 rc4_packets; + u32 eap_packets; + u32 eapol_start_packets; + u32 eapol_logoff_packets; + u32 eapol_encap_asf_packets; +}; + +struct htt_tx_de_classify_failed_stats_tlv { + u32 ap_bss_peer_not_found; + u32 ap_bcast_mcast_no_peer; + u32 sta_delete_in_progress; + u32 ibss_no_bss_peer; + u32 invalid_vdev_type; + u32 invalid_ast_peer_entry; + u32 peer_entry_invalid; + u32 ethertype_not_ip; + u32 eapol_lookup_failed; + u32 qpeer_not_allow_data; + u32 fse_tid_override; + u32 ipv6_jumbogram_zero_length; + u32 qos_to_non_qos_in_prog; + u32 ap_bcast_mcast_eapol; + u32 unicast_on_ap_bss_peer; + u32 ap_vdev_invalid; + u32 incomplete_llc; + u32 eapol_duplicate_m3; + u32 eapol_duplicate_m4; +}; + +struct htt_tx_de_classify_stats_tlv { + u32 arp_packets; + u32 igmp_packets; + u32 dhcp_packets; + u32 host_inspected; + u32 htt_included; + u32 htt_valid_mcs; + u32 htt_valid_nss; + u32 htt_valid_preamble_type; + u32 htt_valid_chainmask; + u32 htt_valid_guard_interval; + u32 htt_valid_retries; + u32 htt_valid_bw_info; + u32 htt_valid_power; + u32 htt_valid_key_flags; + u32 htt_valid_no_encryption; + u32 fse_entry_count; + u32 fse_priority_be; + u32 fse_priority_high; + u32 fse_priority_low; + u32 fse_traffic_ptrn_be; + u32 fse_traffic_ptrn_over_sub; + u32 fse_traffic_ptrn_bursty; + u32 fse_traffic_ptrn_interactive; + u32 fse_traffic_ptrn_periodic; + u32 fse_hwqueue_alloc; + u32 fse_hwqueue_created; + u32 fse_hwqueue_send_to_host; + u32 mcast_entry; + u32 bcast_entry; + u32 htt_update_peer_cache; + u32 htt_learning_frame; + u32 fse_invalid_peer; + /* + * mec_notify is HTT TX WBM multicast echo check notification + * from firmware to host. FW sends SA addresses to host for all + * multicast/broadcast packets received on STA side. + */ + u32 mec_notify; +}; + +struct htt_tx_de_classify_status_stats_tlv { + u32 eok; + u32 classify_done; + u32 lookup_failed; + u32 send_host_dhcp; + u32 send_host_mcast; + u32 send_host_unknown_dest; + u32 send_host; + u32 status_invalid; +}; + +struct htt_tx_de_enqueue_packets_stats_tlv { + u32 enqueued_pkts; + u32 to_tqm; + u32 to_tqm_bypass; +}; + +struct htt_tx_de_enqueue_discard_stats_tlv { + u32 discarded_pkts; + u32 local_frames; + u32 is_ext_msdu; +}; + +struct htt_tx_de_compl_stats_tlv { + u32 tcl_dummy_frame; + u32 tqm_dummy_frame; + u32 tqm_notify_frame; + u32 fw2wbm_enq; + u32 tqm_bypass_frame; +}; + +/* + * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited + * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release + * ring,which may fail, due to non availability of buffer. Hence we sleep for + * 200us & again request for it. This is a histogram of time we wait, with + * bin of 200ms & there are 10 bin (2 seconds max) + * They are defined by the following macros in FW + * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms + * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT / + * ENTRIES_PER_BIN_COUNT) + */ +struct htt_tx_de_fw2wbm_ring_full_hist_tlv { + u32 fw2wbm_ring_full_hist[0]; +}; + +struct htt_tx_de_cmn_stats_tlv { + u32 mac_id__word; + + /* Global Stats */ + u32 tcl2fw_entry_count; + u32 not_to_fw; + u32 invalid_pdev_vdev_peer; + u32 tcl_res_invalid_addrx; + u32 wbm2fw_entry_count; + u32 invalid_pdev; + u32 tcl_res_addrx_timeout; + u32 invalid_vdev; + u32 invalid_tcl_exp_frame_desc; +}; + +/* == RING-IF STATS == */ +#define HTT_STATS_LOW_WM_BINS 5 +#define HTT_STATS_HIGH_WM_BINS 5 + +#define HTT_RING_IF_STATS_NUM_ELEMS GENMASK(15, 0) +#define HTT_RING_IF_STATS_PREFETCH_TAIL_INDEX GENMASK(31, 16) +#define HTT_RING_IF_STATS_HEAD_IDX GENMASK(15, 0) +#define HTT_RING_IF_STATS_TAIL_IDX GENMASK(31, 16) +#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX GENMASK(15, 0) +#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX GENMASK(31, 16) +#define HTT_RING_IF_STATS_LWM_THRESH GENMASK(15, 0) +#define HTT_RING_IF_STATS_HWM_THRESH GENMASK(31, 16) + +struct htt_ring_if_stats_tlv { + u32 base_addr; /* DWORD aligned base memory address of the ring */ + u32 elem_size; + u32 num_elems__prefetch_tail_idx; + u32 head_idx__tail_idx; + u32 shadow_head_idx__shadow_tail_idx; + u32 num_tail_incr; + u32 lwm_thresh__hwm_thresh; + u32 overrun_hit_count; + u32 underrun_hit_count; + u32 prod_blockwait_count; + u32 cons_blockwait_count; + u32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; + u32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; +}; + +struct htt_ring_if_cmn_tlv { + u32 mac_id__word; + u32 num_records; +}; + +/* == SFM STATS == */ +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_sfm_client_user_tlv_v { + /* Number of DWORDS used per user and per client */ + u32 dwords_used_by_user_n[0]; +}; + +struct htt_sfm_client_tlv { + /* Client ID */ + u32 client_id; + /* Minimum number of buffers */ + u32 buf_min; + /* Maximum number of buffers */ + u32 buf_max; + /* Number of Busy buffers */ + u32 buf_busy; + /* Number of Allocated buffers */ + u32 buf_alloc; + /* Number of Available/Usable buffers */ + u32 buf_avail; + /* Number of users */ + u32 num_users; +}; + +struct htt_sfm_cmn_tlv { + u32 mac_id__word; + /* Indicates the total number of 128 byte buffers + * in the CMEM that are available for buffer sharing + */ + u32 buf_total; + /* Indicates for certain client or all the clients + * there is no dowrd saved in SFM, refer to SFM_R1_MEM_EMPTY + */ + u32 mem_empty; + /* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */ + u32 deallocate_bufs; + /* Number of Records */ + u32 num_records; +}; + +/* == SRNG STATS == */ +#define HTT_SRING_STATS_MAC_ID GENMASK(7, 0) +#define HTT_SRING_STATS_RING_ID GENMASK(15, 8) +#define HTT_SRING_STATS_ARENA GENMASK(23, 16) +#define HTT_SRING_STATS_EP BIT(24) +#define HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) +#define HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) +#define HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) +#define HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) +#define HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) +#define HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) +#define HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) +#define HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) + +struct htt_sring_stats_tlv { + u32 mac_id__ring_id__arena__ep; + u32 base_addr_lsb; /* DWORD aligned base memory address of the ring */ + u32 base_addr_msb; + u32 ring_size; + u32 elem_size; + + u32 num_avail_words__num_valid_words; + u32 head_ptr__tail_ptr; + u32 consumer_empty__producer_full; + u32 prefetch_count__internal_tail_ptr; +}; + +struct htt_sring_cmn_tlv { + u32 num_records; +}; + +/* == PDEV TX RATE CTRL STATS == */ +#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 +#define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 +#define HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 +#define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 +#define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 +#define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 +#define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 +#define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT +#define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 +#define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 +#define HTT_TX_PDEV_STATS_NUM_LTF 4 +#define HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 + +#define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ + (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ + HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS) + +#define HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ + (HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS) + +#define HTT_TX_PDEV_STATS_NUM_PER_COUNTERS 101 + +/* + * Introduce new TX counters to support 320MHz support and punctured modes + */ +enum HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE { + HTT_TX_PDEV_STATS_PUNCTURED_NONE = 0, + HTT_TX_PDEV_STATS_PUNCTURED_20 = 1, + HTT_TX_PDEV_STATS_PUNCTURED_40 = 2, + HTT_TX_PDEV_STATS_PUNCTURED_80 = 3, + HTT_TX_PDEV_STATS_PUNCTURED_120 = 4, + HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5 +}; + +#define HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 /* 0 - Half, 1 - Quarter */ +/* 11be related updates */ +#define HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0...13,-2,-1 */ +#define HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ +#define HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES 6 + +#define HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS 6 +#define HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS 4 + +enum HTT_TX_PDEV_STATS_AX_RU_SIZE { + HTT_TX_PDEV_STATS_AX_RU_SIZE_26, + HTT_TX_PDEV_STATS_AX_RU_SIZE_52, + HTT_TX_PDEV_STATS_AX_RU_SIZE_106, + HTT_TX_PDEV_STATS_AX_RU_SIZE_242, + HTT_TX_PDEV_STATS_AX_RU_SIZE_484, + HTT_TX_PDEV_STATS_AX_RU_SIZE_996, + HTT_TX_PDEV_STATS_AX_RU_SIZE_996x2, + HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS, +}; + +enum HTT_TX_PDEV_STATS_BE_RU_SIZE { + HTT_TX_PDEV_STATS_BE_RU_SIZE_26, + HTT_TX_PDEV_STATS_BE_RU_SIZE_52, + HTT_TX_PDEV_STATS_BE_RU_SIZE_52_26, + HTT_TX_PDEV_STATS_BE_RU_SIZE_106, + HTT_TX_PDEV_STATS_BE_RU_SIZE_106_26, + HTT_TX_PDEV_STATS_BE_RU_SIZE_242, + HTT_TX_PDEV_STATS_BE_RU_SIZE_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_484_242, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996_484_242, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x2_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x3_484, + HTT_TX_PDEV_STATS_BE_RU_SIZE_996x4, + HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, +}; + +struct htt_tx_pdev_rate_stats_tlv { + u32 mac_id__word; + u32 tx_ldpc; + u32 rts_cnt; + /* RSSI value of last ack packet (units = dB above noise floor) */ + u32 ack_rssi; + + u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + + u32 tx_su_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + + /* element 0,1, ...7 -> NSS 1,2, ...8 */ + u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; + + /* Counters to track number of tx packets + * in each GI (400us, 800us, 1600us & 3200us) in each mcs (0-11) + */ + u32 tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + + /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ + u32 tx_dcm[HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; + /* Number of CTS-acknowledged RTS packets */ + u32 rts_success; + + /* + * Counters for legacy 11a and 11b transmissions. + * + * The index corresponds to: + * + * CCK: 0: 1 Mbps, 1: 2 Mbps, 2: 5.5 Mbps, 3: 11 Mbps + * + * OFDM: 0: 6 Mbps, 1: 9 Mbps, 2: 12 Mbps, 3: 18 Mbps, + * 4: 24 Mbps, 5: 36 Mbps, 6: 48 Mbps, 7: 54 Mbps + */ + u32 tx_legacy_cck_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; + u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; + + u32 ac_mu_mimo_tx_ldpc; + u32 ax_mu_mimo_tx_ldpc; + u32 ofdma_tx_ldpc; + + /* + * Counters for 11ax HE LTF selection during TX. + * + * The index corresponds to: + * + * 0: unused, 1: 1x LTF, 2: 2x LTF, 3: 4x LTF + */ + u32 tx_he_ltf[HTT_TX_PDEV_STATS_NUM_LTF]; + + u32 ac_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ax_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + + u32 ac_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 ax_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + + u32 ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + + u32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; + u32 tx_11ax_su_ext; + u32 tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 tx_stbc_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 ax_mu_mimo_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 ofdma_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 ax_mu_mimo_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 ofdma_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 tx_mcs_ext_2[HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; + u32 tx_bw_320mhz; + u32 tx_gi_ext_2[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; + u32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; + u32 reduced_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + /** 11AC VHT DL MU MIMO TX BW stats at reduced channel config */ + u32 reduced_ac_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + /** 11AX HE DL MU MIMO TX BW stats at reduced channel config */ + u32 reduced_ax_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + /** 11AX HE DL MU OFDMA TX BW stats at reduced channel config */ + u32 reduced_ax_mu_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + /** 11AX HE DL MU OFDMA TX RU Size stats */ + u32 ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_AX_RU_SIZE_COUNTERS]; + /** 11AX HE DL MU OFDMA HE-SIG-B MCS stats */ + u32 ofdma_he_sig_b_mcs[HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS]; + /** 11AX HE SU data + embedded trigger PPDU success stats (stats for HETP ack success PPDU cnt) */ + u32 ax_su_embedded_trigger_data_ppdu; + /** 11AX HE SU data + embedded trigger PPDU failure stats (stats for HETP ack failure PPDU cnt) */ + u32 ax_su_embedded_trigger_data_ppdu_err; + /** sta side trigger stats */ + u32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES]; +}; + +/* == PDEV RX RATE CTRL STATS == */ +#define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 +#define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 +#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 +#define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 +#define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 +#define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 +#define HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 +#define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 +#define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT +#define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 +#define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16 + +#define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ +#define HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 /* 14, 15 */ +#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ +#define HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS \ + (HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS + HTT_RX_PDEV_STATS_NUM_BW_COUNTERS) +#define HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS 5 /* 20, 40, 80, 160, 320Mhz */ +#define HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS 8 +#define HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 +#define HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 /* 0-13, -2, -1 */ +#define HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 /* 20,40,80,160,320 MHz */ +#define HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS 8 + +/* HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS: + * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 + * RU size index 1: HTT_UL_OFDMA_V0_RU_SIZE_RU_52 + * RU size index 2: HTT_UL_OFDMA_V0_RU_SIZE_RU_106 + * RU size index 3: HTT_UL_OFDMA_V0_RU_SIZE_RU_242 + * RU size index 4: HTT_UL_OFDMA_V0_RU_SIZE_RU_484 + * RU size index 5: HTT_UL_OFDMA_V0_RU_SIZE_RU_996 + */ +#define HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 +/* HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS: + * RU size index 0: HTT_UL_OFDMA_V0_RU_SIZE_RU_26 + * RU size index 1: HTT_UL_OFDMA_V0_RU_SIZE_RU_52 + * RU size index 2: HTT_UL_OFDMA_V0_RU_SIZE_RU_106 + * RU size index 3: HTT_UL_OFDMA_V0_RU_SIZE_RU_242 + * RU size index 4: HTT_UL_OFDMA_V0_RU_SIZE_RU_484 + * RU size index 5: HTT_UL_OFDMA_V0_RU_SIZE_RU_996 + * RU size index 6: HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2 + */ +#define HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS 7 /* includes 996x2 */ + +#define HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES 2 + +enum HTT_RX_PDEV_STATS_BE_RU_SIZE { + HTT_RX_PDEV_STATS_BE_RU_SIZE_26, + HTT_RX_PDEV_STATS_BE_RU_SIZE_52, + HTT_RX_PDEV_STATS_BE_RU_SIZE_52_26, + HTT_RX_PDEV_STATS_BE_RU_SIZE_106, + HTT_RX_PDEV_STATS_BE_RU_SIZE_106_26, + HTT_RX_PDEV_STATS_BE_RU_SIZE_242, + HTT_RX_PDEV_STATS_BE_RU_SIZE_484, + HTT_RX_PDEV_STATS_BE_RU_SIZE_484_242, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, + HTT_RX_PDEV_STATS_BE_RU_SIZE_996x4, + HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS, +}; + +/* Introduce new RX counters to support 320MHZ support and punctured modes */ +typedef enum { + HTT_RX_PDEV_STATS_PUNCTURED_NONE = 0, + HTT_RX_PDEV_STATS_PUNCTURED_20 = 1, + HTT_RX_PDEV_STATS_PUNCTURED_40 = 2, + HTT_RX_PDEV_STATS_PUNCTURED_80 = 3, + HTT_RX_PDEV_STATS_PUNCTURED_120 = 4, + HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS = 5 +} HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_TYPE; + +struct htt_rx_pdev_rate_stats_tlv { + u32 mac_id__word; + u32 nsts; + + u32 rx_ldpc; + u32 rts_cnt; + + u32 rssi_mgmt; /* units = dB above noise floor */ + u32 rssi_data; /* units = dB above noise floor */ + u32 rssi_comb; /* units = dB above noise floor */ + u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + /* element 0,1, ...7 -> NSS 1,2, ...8 */ + u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 rx_dcm[HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; + u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */ + u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; + u8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + /* units = dB above noise floor */ + + /* Counters to track number of rx packets + * in each GI in each mcs (0-11) + */ + u32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + s32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */ + + u32 rx_11ax_su_ext; + u32 rx_11ac_mumimo; + u32 rx_11ax_mumimo; + u32 rx_11ax_ofdma; + u32 txbf; + u32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; + u32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; + u32 rx_active_dur_us_low; + u32 rx_active_dur_us_high; + + u32 rx_11ax_ul_ofdma; + + u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 ul_ofdma_rx_stbc; + u32 ul_ofdma_rx_ldpc; + + /* record the stats for each user index */ + u32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ + u32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */ + u32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ + u32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */ + + u32 nss_count; + u32 pilot_count; + /* RxEVM stats in dB */ + s32 rx_pilot_evm_db[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS]; + /* rx_pilot_evm_db_mean: + * EVM mean across pilots, computed as + * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_db) + */ + s32 rx_pilot_evm_db_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + s8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */ + /* per_chain_rssi_pkt_type: + * This field shows what type of rx frame the per-chain RSSI was computed + * on, by recording the frame type and sub-type as bit-fields within this + * field: + * BIT [3 : 0] :- IEEE80211_FC0_TYPE + * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE + * BIT [31 : 8] :- Reserved + */ + u32 per_chain_rssi_pkt_type; + s8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 rx_su_ndpa; + u32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 rx_mu_ndpa; + u32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 rx_br_poll; + u32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; + + u32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; + u32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; + u32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; + u32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; + u32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; + u32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; +}; + +struct htt_rx_pdev_rate_ext_stats_tlv { + u8 rssi_chain_ext[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; + s8 rx_per_chain_rssi_ext_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; + s32 rssi_mcast_in_dbm; + s32 rssi_mgmt_in_dbm; + u32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 rx_stbc_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 ul_ofdma_rx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 rx_11ax_su_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 rx_11ax_mu_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 rx_11ax_dl_ofdma_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + u32 rx_mcs_ext_2[HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; + u32 rx_bw_ext[HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS]; + u32 rx_gi_ext_2[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; + u32 rx_su_punctured_mode[HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; + u32 reduced_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + u8 rssi_chain_ext_2[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; + s8 rx_per_chain_rssi_ext_2_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_STATS_NUM_BW_EXT_2_COUNTERS]; +}; + +#define HTT_STATS_CMN_MAC_ID_M 0x000000ff +#define HTT_STATS_CMN_MAC_ID_S 0 + +#define HTT_STATS_CMN_MAC_ID_GET(_var) \ + (((_var) & HTT_STATS_CMN_MAC_ID_M) >> \ + HTT_STATS_CMN_MAC_ID_S) + +#define HTT_STATS_CMN_MAC_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_STATS_CMN_MAC_ID, _val); \ + ((_var) |= ((_val) << HTT_STATS_CMN_MAC_ID_S)); \ + } while (0) + +#define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 + +/* == RX PDEV/SOC STATS == */ +struct htt_rx_soc_fw_stats_tlv { + u32 fw_reo_ring_data_msdu; + u32 fw_to_host_data_msdu_bcmc; + u32 fw_to_host_data_msdu_uc; + u32 ofld_remote_data_buf_recycle_cnt; + u32 ofld_remote_free_buf_indication_cnt; + + u32 ofld_buf_to_host_data_msdu_uc; + u32 reo_fw_ring_to_host_data_msdu_uc; + + u32 wbm_sw_ring_reap; + u32 wbm_forward_to_host_cnt; + u32 wbm_target_recycle_cnt; + + u32 target_refill_ring_recycle_cnt; +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_rx_soc_fw_refill_ring_empty_tlv_v { + u32 refill_ring_empty_cnt[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_rx_soc_fw_refill_ring_num_refill_tlv_v { + u32 refill_ring_num_refill[0]; /* HTT_RX_STATS_REFILL_MAX_RING */ +}; + +/* RXDMA error code from WBM released packets */ +enum htt_rx_rxdma_error_code_enum { + HTT_RX_RXDMA_OVERFLOW_ERR = 0, + HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1, + HTT_RX_RXDMA_FCS_ERR = 2, + HTT_RX_RXDMA_DECRYPT_ERR = 3, + HTT_RX_RXDMA_TKIP_MIC_ERR = 4, + HTT_RX_RXDMA_UNECRYPTED_ERR = 5, + HTT_RX_RXDMA_MSDU_LEN_ERR = 6, + HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7, + HTT_RX_RXDMA_WIFI_PARSE_ERR = 8, + HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9, + HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10, + HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11, + HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12, + HTT_RX_RXDMA_FLUSH_REQUEST = 13, + HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14, + HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15, + + /* This MAX_ERR_CODE should not be used in any host/target messages, + * so that even though it is defined within a host/target interface + * definition header file, it isn't actually part of the host/target + * interface, and thus can be modified. + */ + HTT_RX_RXDMA_MAX_ERR_CODE +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v { + u32 rxdma_err[0]; /* HTT_RX_RXDMA_MAX_ERR_CODE */ +}; + +/* REO error code from WBM released packets */ +enum htt_rx_reo_error_code_enum { + HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0, + HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1, + HTT_RX_AMPDU_IN_NON_BA = 2, + HTT_RX_NON_BA_DUPLICATE = 3, + HTT_RX_BA_DUPLICATE = 4, + HTT_RX_REGULAR_FRAME_2K_JUMP = 5, + HTT_RX_BAR_FRAME_2K_JUMP = 6, + HTT_RX_REGULAR_FRAME_OOR = 7, + HTT_RX_BAR_FRAME_OOR = 8, + HTT_RX_BAR_FRAME_NO_BA_SESSION = 9, + HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10, + HTT_RX_PN_CHECK_FAILED = 11, + HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12, + HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13, + HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14, + HTT_RX_REO_ERR_CODE_RVSD = 15, + + /* This MAX_ERR_CODE should not be used in any host/target messages, + * so that even though it is defined within a host/target interface + * definition header file, it isn't actually part of the host/target + * interface, and thus can be modified. + */ + HTT_RX_REO_MAX_ERR_CODE +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v { + u32 reo_err[0]; /* HTT_RX_REO_MAX_ERR_CODE */ +}; + +/* == RX PDEV STATS == */ +#define HTT_STATS_SUBTYPE_MAX 16 + +struct htt_rx_pdev_fw_stats_tlv { + u32 mac_id__word; + u32 ppdu_recvd; + u32 mpdu_cnt_fcs_ok; + u32 mpdu_cnt_fcs_err; + u32 tcp_msdu_cnt; + u32 tcp_ack_msdu_cnt; + u32 udp_msdu_cnt; + u32 other_msdu_cnt; + u32 fw_ring_mpdu_ind; + u32 fw_ring_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; + u32 fw_ring_ctrl_subtype[HTT_STATS_SUBTYPE_MAX]; + u32 fw_ring_mcast_data_msdu; + u32 fw_ring_bcast_data_msdu; + u32 fw_ring_ucast_data_msdu; + u32 fw_ring_null_data_msdu; + u32 fw_ring_mpdu_drop; + u32 ofld_local_data_ind_cnt; + u32 ofld_local_data_buf_recycle_cnt; + u32 drx_local_data_ind_cnt; + u32 drx_local_data_buf_recycle_cnt; + u32 local_nondata_ind_cnt; + u32 local_nondata_buf_recycle_cnt; + + u32 fw_status_buf_ring_refill_cnt; + u32 fw_status_buf_ring_empty_cnt; + u32 fw_pkt_buf_ring_refill_cnt; + u32 fw_pkt_buf_ring_empty_cnt; + u32 fw_link_buf_ring_refill_cnt; + u32 fw_link_buf_ring_empty_cnt; + + u32 host_pkt_buf_ring_refill_cnt; + u32 host_pkt_buf_ring_empty_cnt; + u32 mon_pkt_buf_ring_refill_cnt; + u32 mon_pkt_buf_ring_empty_cnt; + u32 mon_status_buf_ring_refill_cnt; + u32 mon_status_buf_ring_empty_cnt; + u32 mon_desc_buf_ring_refill_cnt; + u32 mon_desc_buf_ring_empty_cnt; + u32 mon_dest_ring_update_cnt; + u32 mon_dest_ring_full_cnt; + + u32 rx_suspend_cnt; + u32 rx_suspend_fail_cnt; + u32 rx_resume_cnt; + u32 rx_resume_fail_cnt; + u32 rx_ring_switch_cnt; + u32 rx_ring_restore_cnt; + u32 rx_flush_cnt; + u32 rx_recovery_reset_cnt; +}; + +#define HTT_STATS_PHY_ERR_MAX 43 + +struct htt_rx_pdev_fw_stats_phy_err_tlv { + u32 mac_id__word; + u32 total_phy_err_cnt; + /* Counts of different types of phy errs + * The mapping of PHY error types to phy_err array elements is HW dependent. + * The only currently-supported mapping is shown below: + * + * 0 phyrx_err_phy_off Reception aborted due to receiving a PHY_OFF TLV + * 1 phyrx_err_synth_off + * 2 phyrx_err_ofdma_timing + * 3 phyrx_err_ofdma_signal_parity + * 4 phyrx_err_ofdma_rate_illegal + * 5 phyrx_err_ofdma_length_illegal + * 6 phyrx_err_ofdma_restart + * 7 phyrx_err_ofdma_service + * 8 phyrx_err_ppdu_ofdma_power_drop + * 9 phyrx_err_cck_blokker + * 10 phyrx_err_cck_timing + * 11 phyrx_err_cck_header_crc + * 12 phyrx_err_cck_rate_illegal + * 13 phyrx_err_cck_length_illegal + * 14 phyrx_err_cck_restart + * 15 phyrx_err_cck_service + * 16 phyrx_err_cck_power_drop + * 17 phyrx_err_ht_crc_err + * 18 phyrx_err_ht_length_illegal + * 19 phyrx_err_ht_rate_illegal + * 20 phyrx_err_ht_zlf + * 21 phyrx_err_false_radar_ext + * 22 phyrx_err_green_field + * 23 phyrx_err_bw_gt_dyn_bw + * 24 phyrx_err_leg_ht_mismatch + * 25 phyrx_err_vht_crc_error + * 26 phyrx_err_vht_siga_unsupported + * 27 phyrx_err_vht_lsig_len_invalid + * 28 phyrx_err_vht_ndp_or_zlf + * 29 phyrx_err_vht_nsym_lt_zero + * 30 phyrx_err_vht_rx_extra_symbol_mismatch + * 31 phyrx_err_vht_rx_skip_group_id0 + * 32 phyrx_err_vht_rx_skip_group_id1to62 + * 33 phyrx_err_vht_rx_skip_group_id63 + * 34 phyrx_err_ofdm_ldpc_decoder_disabled + * 35 phyrx_err_defer_nap + * 36 phyrx_err_fdomain_timeout + * 37 phyrx_err_lsig_rel_check + * 38 phyrx_err_bt_collision + * 39 phyrx_err_unsupported_mu_feedback + * 40 phyrx_err_ppdu_tx_interrupt_rx + * 41 phyrx_err_unsupported_cbf + * 42 phyrx_err_other + */ + u32 phy_err[HTT_STATS_PHY_ERR_MAX]; +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_rx_pdev_fw_ring_mpdu_err_tlv_v { + /* Num error MPDU for each RxDMA error type */ + u32 fw_ring_mpdu_err[0]; /* HTT_RX_STATS_RXDMA_MAX_ERR */ +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_rx_pdev_fw_mpdu_drop_tlv_v { + /* Num MPDU dropped */ + u32 fw_mpdu_drop[0]; /* HTT_RX_STATS_FW_DROP_REASON_MAX */ +}; + +#define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) +#define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) +#define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) +#define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8) +#define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10) +#define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20) +#define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40) +#define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80) + +struct htt_pdev_stats_cca_counters_tlv { + /* Below values are obtained from the HW Cycles counter registers */ + u32 tx_frame_usec; + u32 rx_frame_usec; + u32 rx_clear_usec; + u32 my_rx_frame_usec; + u32 usec_cnt; + u32 med_rx_idle_usec; + u32 med_tx_idle_global_usec; + u32 cca_obss_usec; +}; + +struct htt_pdev_cca_stats_hist_v1_tlv { + u32 chan_num; + /* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/ + u32 num_records; + u32 valid_cca_counters_bitmap; + u32 collection_interval; + + /* This will be followed by an array which contains the CCA stats + * collected in the last N intervals, + * if the indication is for last N intervals CCA stats. + * Then the pdev_cca_stats[0] element contains the oldest CCA stats + * and pdev_cca_stats[N-1] will have the most recent CCA stats. + * htt_pdev_stats_cca_counters_tlv cca_hist_tlv[1]; + */ +}; + +struct htt_pdev_stats_twt_session_tlv { + u32 vdev_id; + struct htt_mac_addr peer_mac; + u32 flow_id_flags; + + /* TWT_DIALOG_ID_UNAVAILABLE is used + * when TWT session is not initiated by host + */ + u32 dialog_id; + u32 wake_dura_us; + u32 wake_intvl_us; + u32 sp_offset_us; +}; + +struct htt_pdev_stats_twt_sessions_tlv { + u32 pdev_id; + u32 num_sessions; + struct htt_pdev_stats_twt_session_tlv twt_session[]; +}; + +enum htt_rx_reo_resource_sample_id_enum { + /* Global link descriptor queued in REO */ + HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0, + HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1, + HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2, + /*Number of queue descriptors of this aging group */ + HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3, + HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4, + HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5, + HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6, + /* Total number of MSDUs buffered in AC */ + HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7, + HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8, + HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9, + HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10, + + HTT_RX_REO_RESOURCE_STATS_MAX = 16 +}; + +struct htt_rx_reo_resource_stats_tlv_v { + /* Variable based on the Number of records. HTT_RX_REO_RESOURCE_STATS_MAX */ + u32 sample_id; + u32 total_max; + u32 total_avg; + u32 total_sample; + u32 non_zeros_avg; + u32 non_zeros_sample; + u32 last_non_zeros_max; + u32 last_non_zeros_min; + u32 last_non_zeros_avg; + u32 last_non_zeros_sample; +}; + +/* == TX SOUNDING STATS == */ + +enum htt_txbf_sound_steer_modes { + HTT_IMPLICIT_TXBF_STEER_STATS = 0, + HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1, + HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2, + HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3, + HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4, + HTT_TXBF_MAX_NUM_OF_MODES = 5 +}; + +enum htt_stats_sounding_tx_mode { + HTT_TX_AC_SOUNDING_MODE = 0, + HTT_TX_AX_SOUNDING_MODE = 1, +}; + +struct htt_tx_sounding_stats_tlv { + u32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ + /* Counts number of soundings for all steering modes in each bw */ + u32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES]; + u32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES]; + u32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES]; + u32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES]; + /* + * The sounding array is a 2-D array stored as an 1-D array of + * u32. The stats for a particular user/bw combination is + * referenced with the following: + * + * sounding[(user* max_bw) + bw] + * + * ... where max_bw == 4 for 160mhz + */ + u32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; +}; + +struct htt_pdev_obss_pd_stats_tlv { + u32 num_obss_tx_ppdu_success; + u32 num_obss_tx_ppdu_failure; + u32 num_sr_tx_transmissions; + u32 num_spatial_reuse_opportunities; + u32 num_non_srg_opportunities; + u32 num_non_srg_ppdu_tried; + u32 num_non_srg_ppdu_success; + u32 num_srg_opportunities; + u32 num_srg_ppdu_tried; + u32 num_srg_ppdu_success; + u32 num_psr_opportunities; + u32 num_psr_ppdu_tried; + u32 num_psr_ppdu_success; +}; + +struct htt_ring_backpressure_stats_tlv { + u32 pdev_id; + u32 current_head_idx; + u32 current_tail_idx; + u32 num_htt_msgs_sent; + /* Time in milliseconds for which the ring has been in + * its current backpressure condition + */ + u32 backpressure_time_ms; + /* backpressure_hist - histogram showing how many times + * different degrees of backpressure duration occurred: + * Index 0 indicates the number of times ring was + * continuously in backpressure state for 100 - 200ms. + * Index 1 indicates the number of times ring was + * continuously in backpressure state for 200 - 300ms. + * Index 2 indicates the number of times ring was + * continuously in backpressure state for 300 - 400ms. + * Index 3 indicates the number of times ring was + * continuously in backpressure state for 400 - 500ms. + * Index 4 indicates the number of times ring was + * continuously in backpressure state beyond 500ms. + */ + u32 backpressure_hist[5]; +}; + +/* 11BE STATS TLVs */ +enum htt_tx_err_status_t { + HTT_TXERR_NONE, + HTT_TXERR_RESP, /* response timeout, mismatch, + * BW mismatch, mimo ctrl mismatch, + * CRC error.. */ + HTT_TXERR_FILT, /* blocked by tx filtering */ + HTT_TXERR_FIFO, /* fifo, misc errors in HW */ + HTT_TXERR_SWABORT, /* software initialted abort (TX_ABORT) */ + + HTT_TXERR_RESERVED1, + HTT_TXERR_RESERVED2, + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS = 7, + + HTT_TXERR_INVALID = 0xff, +}; + +/* Matching enum for htt_tx_selfgen_sch_tsflag_error_stats */ +enum htt_tx_selfgen_sch_tsflag_error_stats { + HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, + + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS = 8, + HTT_TX_SELFGEN_SCH_TSFLAG_ERROR_STATS_VALID = 8 +}; + +/* 0...13,-2,-1 */ +#define HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS 16 +/* 20,40,80,160,320 MHz */ +#define HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS 5 + +#define HTT_TX_PDEV_STATS_NUM_HE_SIG_B_MCS_COUNTERS 6 +#define HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS 4 + +struct htt_tx_selfgen_be_stats_tlv { + u32 be_su_ndpa; + u32 be_su_ndp; + u32 be_mu_mimo_ndpa; + u32 be_mu_mimo_ndp; + u32 be_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; + u32 be_basic_trigger; + u32 be_bsr_trigger; + u32 be_mu_bar_trigger; + u32 be_mu_rts_trigger; + u32 be_ulmumimo_trigger; + u32 be_su_ndpa_queued; + u32 be_su_ndp_queued; + u32 be_mu_mimo_ndpa_queued; + u32 be_mu_mimo_ndp_queued; + u32 be_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; + u32 be_ul_mumimo_trigger[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; +}; + +struct htt_tx_selfgen_be_err_stats_tlv { + u32 be_su_ndp_err; + u32 be_su_ndpa_err; + u32 be_mu_mimo_ndpa_err; + u32 be_mu_mimo_ndp_err; + u32 be_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; + u32 be_basic_trigger_err; + u32 be_bsr_trigger_err; + u32 be_mu_bar_trigger_err; + u32 be_mu_rts_trigger_err; + u32 be_ulmumimo_trigger_err; + u32 be_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; + u32 be_su_ndpa_flushed; + u32 be_su_ndp_flushed; + u32 be_mu_mimo_ndpa_flushed; + u32 be_mu_mimo_ndp_flushed; + u32 be_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS - 1]; + u32 be_ul_mumimo_trigger_err[HTT_TX_PDEV_STATS_NUM_BE_MUMIMO_USER_STATS]; +}; + +struct htt_tx_selfgen_be_sched_status_stats_tlv { + u32 be_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + u32 be_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + u32 be_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + u32 be_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + u32 be_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + u32 be_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + u32 be_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; +}; + +struct htt_tx_pdev_be_dl_mu_ofdma_sch_stats_tlv { + u32 be_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +}; + +struct htt_tx_pdev_be_ul_mu_ofdma_sch_stats_tlv { + u32 be_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 be_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 be_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 be_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +}; + +struct htt_tx_pdev_be_ul_mu_mimo_sch_stats_tlv { + u32 be_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; + u32 be_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; +}; + +struct htt_tx_pdev_rate_stats_be_tlv { + u32 be_mu_mimo_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + u32 be_mu_mimo_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 be_mu_mimo_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; + u32 be_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + u32 be_mu_mimo_tx_ldpc; +}; + +struct htt_tx_pdev_rate_stats_be_ofdma_tlv { + u32 mac_id__word; + u32 be_ofdma_tx_ldpc; + u32 be_ofdma_tx_mcs[HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + u32 be_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 be_ofdma_tx_bw[HTT_TX_PDEV_STATS_NUM_BE_BW_COUNTERS]; + u32 be_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + u32 be_ofdma_tx_ru_size[HTT_TX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; + u32 be_ofdma_eht_sig_mcs[HTT_TX_PDEV_STATS_NUM_EHT_SIG_MCS_COUNTERS]; +}; + +#define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 +struct htt_rx_pdev_be_ul_trigger_stats_tlv { + u32 mac_id__word; + + u32 rx_11be_ul_ofdma; + u32 be_ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + u32 be_ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + u32 be_ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 be_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; + u32 be_ul_ofdma_rx_stbc; + u32 be_ul_ofdma_rx_ldpc; + + /* + * These are arrays to hold the number of PPDUs that we received per RU. + * E.g. PPDUs (data or non data) received in RU26 will be incremented in + * array offset 0 and similarly RU52 will be incremented in array offset 1 + */ + /* PPDU level */ + u32 be_rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; + u32 be_rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_BE_RU_SIZE_COUNTERS]; + + /* + * These arrays hold Target RSSI (rx power the AP wants), + * FD RSSI (rx power the AP sees) & Power headroom values of STAs + * which can be identified by AIDs, during trigger based RX. + * Array acts a circular buffer and holds values for last 5 STAs + * in the same order as RX. + */ + /* + * STA AID array for identifying which STA the + * Target-RSSI / FD-RSSI / pwr headroom stats are for + */ + u32 be_uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; + + /* + * Trig Target RSSI for STA AID in same index - UNIT(dBm) + */ + s32 be_uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; + + /* + * Trig FD RSSI from STA AID in same index - UNIT(dBm) + */ + s32 be_uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; + + /* + * Trig power headroom for STA AID in same idx - UNIT(dB) + */ + u32 be_uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; +}; + +struct htt_rx_pdev_be_ul_mimo_user_stats_tlv { + u32 user_index; + u32 be_rx_ulmumimo_non_data_ppdu; + u32 be_rx_ulmumimo_data_ppdu; + u32 be_rx_ulmumimo_mpdu_ok; + u32 be_rx_ulmumimo_mpdu_fail; +}; + +struct htt_tx_histogram_stats_tlv { + u32 rate_retry_mcs_drop_cnt; + u32 mcs_drop_rate[HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS]; + u32 per_histogram_cnt[HTT_TX_PDEV_STATS_NUM_PER_COUNTERS]; + u32 low_latency_rate_cnt; + u32 su_burst_rate_drop_cnt; + u32 su_burst_rate_drop_fail_cnt; +}; + +struct htt_rx_pdev_ul_mumimo_trig_be_stats_tlv { + u32 mac_id__word; + + /* Number of times UL MUMIMO RX packets received */ + u32 rx_11be_ul_mumimo; + + /* 11BE EHT UL MU-MIMO RX TB PPDU MCS stats */ + u32 be_ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + /* + * 11BE EHT UL MU-MIMO RX GI & LTF stats. + * Index 0 indicates 1xLTF + 1.6 msec GI + * Index 1 indicates 2xLTF + 1.6 msec GI + * Index 2 indicates 4xLTF + 3.2 msec GI + */ + u32 be_ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_BE_MCS_COUNTERS]; + /* + * 11BE EHT UL MU-MIMO RX TB PPDU NSS stats + * (Increments the individual user NSS in the UL MU MIMO PPDU received) + */ + u32 be_ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; + /* 11BE EHT UL MU-MIMO RX TB PPDU BW stats */ + u32 be_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; + /* Number of times UL MUMIMO TB PPDUs received with STBC */ + u32 be_ul_mumimo_rx_stbc; + /* Number of times UL MUMIMO TB PPDUs received with LDPC */ + u32 be_ul_mumimo_rx_ldpc; + + /* RSSI in dBm for Rx TB PPDUs */ + s8 be_rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; + /* Target RSSI programmed in UL MUMIMO triggers (units dBm) */ + s8 be_rx_ul_mumimo_target_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_NUM_BE_BW_COUNTERS]; + /* FD RSSI measured for Rx UL TB PPDUs (units dBm) */ + s8 be_rx_ul_mumimo_fd_rssi[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; + /* Average pilot EVM measued for RX UL TB PPDU */ + s8 be_rx_ulmumimo_pilot_evm_dB_mean[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER][HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; +}; + +#ifdef CONFIG_ATH12K_DEBUGFS + +void ath12k_debugfs_htt_stats_init(struct ath12k *ar); +void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, + struct sk_buff *skb); +int ath12k_debugfs_htt_stats_req(struct ath12k *ar); + +#else /* CONFIG_ATH12K_DEBUGFS */ + +static inline void ath12k_debugfs_htt_stats_init(struct ath12k *ar) +{ +} + +static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, + struct sk_buff *skb) +{ +} + +static inline int ath12k_debugfs_htt_stats_req(struct ath12k *ar) +{ + return 0; +} + +#endif /* CONFIG_ATH12K_DEBUGFS */ + + +struct htt_rx_pdev_ul_mumimo_trig_stats_tlv { + u32 mac_id__word; + u32 rx_11ax_ul_mumimo; + u32 ul_mumimo_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ul_mumimo_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ul_mumimo_rx_nss[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; + u32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 ul_mumimo_rx_stbc; + u32 ul_mumimo_rx_ldpc; + u32 ul_mumimo_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + u32 ul_mumimo_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + s8 rx_ul_mumimo_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS] + [HTT_RX_PDEV_STATS_TOTAL_BW_COUNTERS]; + s8 rx_ul_mumimo_target_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS] + [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + s8 rx_ul_mumimo_fd_rssi[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS] + [HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; + s8 rx_ulmumimo_pilot_evm_db_mean[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS] + [HTT_RX_PDEV_STATS_ULMUMIMO_NUM_SPATIAL_STREAMS]; + u32 reduced_ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES] + [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; +}; + +struct htt_rx_pdev_ul_mimo_user_stats_tlv { + u32 user_index; + u32 rx_ulmumimo_non_data_ppdu; + u32 rx_ulmumimo_data_ppdu; + u32 rx_ulmumimo_mpdu_ok; + u32 rx_ulmumimo_mpdu_fail; +}; + +struct htt_rx_pdev_ul_ofdma_user_stats_tlv { + u32 user_index; + u32 rx_ulofdma_non_data_ppdu; + u32 rx_ulofdma_data_ppdu; + u32 rx_ulofdma_mpdu_ok; + u32 rx_ulofdma_mpdu_fail; + u32 rx_ulofdma_non_data_nusers; + u32 rx_ulofdma_data_nusers; +}; + +#define HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 + +struct htt_rx_pdev_ul_trigger_stats_tlv { + u32 mac_id__word; + u32 rx_11ax_ul_ofdma; + u32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ul_ofdma_rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; + u32 ul_ofdma_rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 ul_ofdma_rx_stbc; + u32 ul_ofdma_rx_ldpc; + u32 rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; + u32 rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; + + u32 uplink_sta_aid[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; + u32 uplink_sta_target_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; + u32 uplink_sta_fd_rssi[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; + u32 uplink_sta_power_headroom[HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; + u32 reduced_ul_ofdma_rx_bw[HTT_RX_PDEV_STATS_NUM_REDUCED_CHAN_TYPES] + [HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; +}; + +#define HTT_LATENCY_PROFILE_MAX_HIST 3 +#define HTT_STATS_MAX_PROF_STATS_NAME_LEN 32 +#define HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3 +struct htt_latency_prof_stats_tlv { + u32 print_header; + u8 latency_prof_name[HTT_STATS_MAX_PROF_STATS_NAME_LEN]; + u32 cnt; + u32 min; + u32 max; + u32 last; + u32 tot; + u32 avg; + u32 hist_intvl; + u32 hist[HTT_LATENCY_PROFILE_MAX_HIST]; +}; + +struct htt_latency_prof_ctx_tlv { + u32 duration; + u32 tx_msdu_cnt; + u32 tx_mpdu_cnt; + u32 tx_ppdu_cnt; + u32 rx_msdu_cnt; + u32 rx_mpdu_cnt; +}; + +struct htt_latency_prof_cnt_tlv { + u32 prof_enable_cnt; +}; + +#define HTT_RX_MAX_PEAK_OCCUPANCY_INDEX 10 +#define HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX 10 +#define HTT_RX_SQUARE_INDEX 6 +#define HTT_RX_MAX_PEAK_SEARCH_INDEX 4 +#define HTT_RX_MAX_PENDING_SEARCH_INDEX 4 + +struct htt_rx_fse_stats_tlv { + u32 fse_enable_cnt; + u32 fse_disable_cnt; + u32 fse_cache_invalidate_entry_cnt; + u32 fse_full_cache_invalidate_cnt; + u32 fse_num_cache_hits_cnt; + u32 fse_num_searches_cnt; + u32 fse_cache_occupancy_peak_cnt[HTT_RX_MAX_PEAK_OCCUPANCY_INDEX]; + u32 fse_cache_occupancy_curr_cnt[HTT_RX_MAX_CURRENT_OCCUPANCY_INDEX]; + u32 fse_search_stat_square_cnt[HTT_RX_SQUARE_INDEX]; + u32 fse_search_stat_peak_cnt[HTT_RX_MAX_PEAK_SEARCH_INDEX]; + u32 fse_search_stat_search_pending_cnt[HTT_RX_MAX_PENDING_SEARCH_INDEX]; +}; + +/* == PDEV RX RATE EXT STATS == */ +#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 +/* HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS: + * bw index 4 (bw ext index 0): rssi_ext80_low20_chain0 + * bw index 5 (bw ext index 1): rssi_ext80_low_high20_chain0 + * bw index 6 (bw ext index 2): rssi_ext80_high_low20_chain0 + * bw index 7 (bw ext index 3): rssi_ext80_high20_chain0 + */ +#define HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS 4 +#define HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 +#define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 +#define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 + +#define HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES 2 + +struct htt_pdev_txrate_txbf_stats_tlv { + u32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + u32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + u32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + u32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; + u32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; + u32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; + u32 tx_legacy_ofdm_rate[HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; + u32 reduced_tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES] + [HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; + u32 reduced_tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES] + [HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; + u32 reduced_tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_REDUCED_CHAN_TYPES] + [HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; +}; + +struct htt_txbf_ofdma_ndpa_stats_tlv { + u32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +}; + +struct htt_txbf_ofdma_ndp_stats_tlv { + u32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +}; + +struct htt_txbf_ofdma_brp_stats_tlv { + u32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS + 1]; +}; + +struct htt_txbf_ofdma_steer_stats_tlv { + u32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +}; + +struct htt_txbf_ofdma_ax_ndpa_stats_elem_t { + u32 ax_ofdma_ndpa_queued; + u32 ax_ofdma_ndpa_tried; + u32 ax_ofdma_ndpa_flushed; + u32 ax_ofdma_ndpa_err; +}; + +struct htt_txbf_ofdma_ax_ndpa_stats_tlv { + u32 num_elems_ax_ndpa_arr; + u32 arr_elem_size_ax_ndpa; + struct htt_txbf_ofdma_ax_ndpa_stats_elem_t ax_ndpa[1]; +}; + +struct htt_txbf_ofdma_ax_ndp_stats_elem_t { + u32 ax_ofdma_ndp_queued; + u32 ax_ofdma_ndp_tried; + u32 ax_ofdma_ndp_flushed; + u32 ax_ofdma_ndp_err; +}; + +struct htt_txbf_ofdma_ax_ndp_stats_tlv { + u32 num_elems_ax_ndp_arr; + u32 arr_elem_size_ax_ndp; + struct htt_txbf_ofdma_ax_ndp_stats_elem_t ax_ndp[1]; +}; + +struct htt_txbf_ofdma_ax_brp_stats_elem_t { + u32 ax_ofdma_brpoll_queued; + u32 ax_ofdma_brpoll_tried; + u32 ax_ofdma_brpoll_flushed; + u32 ax_ofdma_brp_err; + u32 ax_ofdma_brp_err_num_cbf_rcvd; +}; + +struct htt_txbf_ofdma_ax_brp_stats_tlv { + u32 num_elems_ax_brp_arr; + u32 arr_elem_size_ax_brp; + struct htt_txbf_ofdma_ax_brp_stats_elem_t ax_brp[1]; +}; + +struct htt_txbf_ofdma_ax_steer_stats_elem_t { + u32 ax_ofdma_num_ppdu_steer; + u32 ax_ofdma_num_ppdu_ol; + u32 ax_ofdma_num_usrs_prefetch; + u32 ax_ofdma_num_usrs_sound; + u32 ax_ofdma_num_usrs_force_sound; +}; + +struct htt_txbf_ofdma_ax_steer_stats_tlv { + u32 num_elems_ax_steer_arr; + u32 arr_elem_size_ax_steer; + struct htt_txbf_ofdma_ax_steer_stats_elem_t ax_steer[1]; +}; + +struct htt_txbf_ofdma_ax_steer_mpdu_stats_tlv { + /* 11AX HE OFDMA MPDUs tried in rbo steering */ + u32 ax_ofdma_rbo_steer_mpdus_tried; + /* 11AX HE OFDMA MPDUs failed in rbo steering */ + u32 ax_ofdma_rbo_steer_mpdus_failed; + /* 11AX HE OFDMA MPDUs tried in sifs steering */ + u32 ax_ofdma_sifs_steer_mpdus_tried; + /* 11AX HE OFDMA MPDUs failed in sifs steering */ + u32 ax_ofdma_sifs_steer_mpdus_failed; +}; + +struct htt_txbf_ofdma_be_ndpa_stats_elem_t { + u32 be_ofdma_ndpa_queued; + u32 be_ofdma_ndpa_tried; + u32 be_ofdma_ndpa_flushed; + u32 be_ofdma_ndpa_err; +}; + +struct htt_txbf_ofdma_be_ndpa_stats_tlv { + u32 num_elems_be_ndpa_arr; + u32 arr_elem_size_be_ndpa; + struct htt_txbf_ofdma_be_ndpa_stats_elem_t be_ndpa[1]; +}; + +struct htt_txbf_ofdma_be_ndp_stats_elem_t { + u32 be_ofdma_ndp_queued; + u32 be_ofdma_ndp_tried; + u32 be_ofdma_ndp_flushed; + u32 be_ofdma_ndp_err; +}; + +struct htt_txbf_ofdma_be_ndp_stats_tlv { + u32 num_elems_be_ndp_arr; + u32 arr_elem_size_be_ndp; + struct htt_txbf_ofdma_be_ndp_stats_elem_t be_ndp[1]; +}; + +struct htt_txbf_ofdma_be_brp_stats_elem_t { + u32 be_ofdma_brpoll_queued; + u32 be_ofdma_brpoll_tried; + u32 be_ofdma_brpoll_flushed; + u32 be_ofdma_brp_err; + u32 be_ofdma_brp_err_num_cbf_rcvd; +}; + +struct htt_txbf_ofdma_be_brp_stats_tlv { + u32 num_elems_be_brp_arr; + u32 arr_elem_size_be_brp; + struct htt_txbf_ofdma_be_brp_stats_elem_t be_brp[1]; +}; + +struct htt_txbf_ofdma_be_steer_stats_elem_t { + u32 be_ofdma_num_ppdu_steer; + u32 be_ofdma_num_ppdu_ol; + u32 be_ofdma_num_usrs_prefetch; + u32 be_ofdma_num_usrs_sound; + u32 be_ofdma_num_usrs_force_sound; +}; + +struct htt_txbf_ofdma_be_steer_stats_tlv { + u32 num_elems_be_steer_arr; + u32 arr_elem_size_be_steer; + struct htt_txbf_ofdma_be_steer_stats_elem_t be_steer[1]; +}; + +struct htt_txbf_ofdma_be_steer_mpdu_stats_tlv { + /* 11BE EHT OFDMA MPDUs tried in rbo steering */ + u32 be_ofdma_rbo_steer_mpdus_tried; + /* 11BE EHT OFDMA MPDUs failed in rbo steering */ + u32 be_ofdma_rbo_steer_mpdus_failed; + /* 11BE EHT OFDMA MPDUs tried in sifs steering */ + u32 be_ofdma_sifs_steer_mpdus_tried; + /* 11BE EHT OFDMA MPDUs failed in sifs steering */ + u32 be_ofdma_sifs_steer_mpdus_failed; +}; + +struct htt_dmac_reset_stats_tlv { + u32 reset_count; + u32 reset_time_lo_ms; + u32 reset_time_hi_ms; + u32 disengage_time_lo_ms; + u32 disengage_time_hi_ms; + u32 engage_time_lo_ms; + u32 engage_time_hi_ms; + u32 disengage_count; + u32 engage_count; + u32 drain_dest_ring_mask; +}; + +struct htt_rx_pdev_be_ul_ofdma_user_stats_tlv { + u32 user_index; + u32 be_rx_ulofdma_non_data_ppdu; + u32 be_rx_ulofdma_data_ppdu; + u32 be_rx_ulofdma_mpdu_ok; + u32 be_rx_ulofdma_mpdu_fail; + u32 be_rx_ulofdma_non_data_nusers; + u32 be_rx_ulofdma_data_nusers; +}; + +#define HTT_MAX_RX_PKT_CNT 8 +#define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 +#define HTT_MAX_PER_BLK_ERR_CNT 20 +#define HTT_MAX_RX_OTA_ERR_CNT 14 +#define HTT_STATS_MAX_CHAINS 8 +#define HTT_MAX_CH_PWR_INFO_SIZE 16 +#define HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT 32 + +#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_M 0x000000ff +#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_S 0 + +#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_GET(_var) \ + (((_var) & HTT_PDEV_PUNCTURE_STATS_MAC_ID_M) >> \ + HTT_PDEV_PUNCTURE_STATS_MAC_ID_S) +#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PDEV_PUNCTURE_STATS_MAC_ID, _val); \ + ((_var) |= ((_val) << HTT_PDEV_PUNCTURE_STATS_MAC_ID_S)); \ + } while (0) + +struct htt_phy_tpc_stats_tlv { + u32 pdev_id; + u32 tx_power_scale; + u32 tx_power_scale_db; + u32 min_negative_tx_power; + u32 reg_ctl_domain; + u32 max_reg_allowed_power[HTT_STATS_MAX_CHAINS]; + u32 max_reg_allowed_power_6g[HTT_STATS_MAX_CHAINS]; + u32 twice_max_rd_power; + u32 max_tx_power; + u32 home_max_tx_power; + u32 psd_power; + u32 eirp_power; + u32 power_type_6ghz; + u32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE]; + u32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE]; +}; + +struct htt_pdev_puncture_stats_tlv { + union { + struct { + u32 mac_id:8, + reserved:24; + }; + u32 mac_id__word; + }; + u32 direction; + u32 preamble; + u32 ppdu_type; + u32 subband_count; + u32 last_used_pattern_mask; + u32 num_subbands_used_cnt[HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT]; +}; + +enum { + HTT_STATS_CAL_PROF_COLD_BOOT = 0, + HTT_STATS_CAL_PROF_FULL_CHAN_SWITCH = 1, + HTT_STATS_CAL_PROF_SCAN_CHAN_SWITCH = 2, + HTT_STATS_CAL_PROF_DPD_SPLIT_CAL = 3, + + HTT_STATS_MAX_PROF_CAL = 4, +}; + +#define HTT_STATS_MAX_CAL_IDX_CNT 8 +struct htt_latency_prof_cal_stats_tlv { + + u8 latency_prof_name[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_PROF_STATS_NAME_LEN]; + + /** To verify whether prof cal is enabled or not */ + u32 enable; + + /** current pdev_id */ + u32 pdev_id; + + /** The cnt is incremented when each time the calindex takes place */ + u32 cnt[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** Minimum time taken to complete the calibration - in us */ + u32 min[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** Maximum time taken to complete the calibration -in us */ + u32 max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** Time taken by the cal for its final time execution - in us */ + u32 last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** Total time taken - in us */ + u32 tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** hist_intvl - by default will be set to 2000 us */ + u32 hist_intvl[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** + * If last is less than hist_intvl, then hist[0]++, + * If last is less than hist_intvl << 1, then hist[1]++, + * otherwise hist[2]++. + */ + u32 hist[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT][HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST]; + + /** Pf_last will log the current no of page faults */ + u32 pf_last[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** Sum of all page faults happened */ + u32 pf_tot[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** If pf_last > pf_max then pf_max = pf_last */ + u32 pf_max[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** + * For each cal profile, only certain no of cal indices were invoked, + * this member will store what all the indices got invoked per each + * cal profile + */ + u32 enabledCalIdx[HTT_STATS_MAX_PROF_CAL][HTT_STATS_MAX_CAL_IDX_CNT]; + + /** No of indices invoked per each cal profile */ + u32 CalCnt[HTT_STATS_MAX_PROF_CAL]; +}; + +#define HTT_ML_PEER_DETAILS_NUM_LINKS_M 0x00000003 +#define HTT_ML_PEER_DETAILS_NUM_LINKS_S 0 +#define HTT_ML_PEER_DETAILS_ML_PEER_ID_M 0x00003FFC +#define HTT_ML_PEER_DETAILS_ML_PEER_ID_S 2 +#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M 0x0001C000 +#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S 14 +#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M 0x00060000 +#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S 17 +#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M 0x00380000 +#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S 19 +#define HTT_ML_PEER_DETAILS_NON_STR_M 0x00400000 +#define HTT_ML_PEER_DETAILS_NON_STR_S 22 +#define HTT_ML_PEER_DETAILS_EMLSR_M 0x00800000 +#define HTT_ML_PEER_DETAILS_EMLSR_S 23 +#define HTT_ML_PEER_DETAILS_IS_STA_KO_M 0x01000000 +#define HTT_ML_PEER_DETAILS_IS_STA_KO_S 24 +#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M 0x06000000 +#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S 25 +#define HTT_ML_PEER_DETAILS_ALLOCATED_M 0x08000000 +#define HTT_ML_PEER_DETAILS_ALLOCATED_S 27 + +#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M 0x000000ff +#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S 0 + +#define HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_NUM_LINKS_M) >> \ + HTT_ML_PEER_DETAILS_NUM_LINKS_S) + +#define HTT_ML_PEER_DETAILS_NUM_LINKS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LINKS, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LINKS_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LINKS_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_ML_PEER_ID_M) >> \ + HTT_ML_PEER_DETAILS_ML_PEER_ID_S) + +#define HTT_ML_PEER_DETAILS_ML_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ML_PEER_ID, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_ML_PEER_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ML_PEER_ID_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M) >> \ + HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S) + +#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S)); \ + } while (0) +#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M) >> \ + HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S) + +#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M) >> \ + HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S) + +#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_NON_STR_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_NON_STR_M) >> \ + HTT_ML_PEER_DETAILS_NON_STR_S) + +#define HTT_ML_PEER_DETAILS_NON_STR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NON_STR, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_NON_STR_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NON_STR_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_EMLSR_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_EMLSR_M) >> \ + HTT_ML_PEER_DETAILS_EMLSR_S) + +#define HTT_ML_PEER_DETAILS_EMLSR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_EMLSR, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_EMLSR_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_EMLSR_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_IS_STA_KO_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_IS_STA_KO_M) >> \ + HTT_ML_PEER_DETAILS_IS_STA_KO_S) + +#define HTT_ML_PEER_DETAILS_IS_STA_KO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_IS_STA_KO, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_IS_STA_KO_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_IS_STA_KO_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M) >> \ + HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S) +#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_ALLOCATED_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_ALLOCATED_M) >> \ + HTT_ML_PEER_DETAILS_ALLOCATED_S) + +#define HTT_ML_PEER_DETAILS_ALLOCATED_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ALLOCATED, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_ALLOCATED_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ALLOCATED_S)); \ + } while (0) + +#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) \ + (((_var) & HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M) >> \ + HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S) + +#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP, _val); \ + ((_var) &= ~(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S)); \ + } while (0) + +struct htt_ml_peer_details_tlv { + struct htt_mac_addr remote_mld_mac_addr; + union { + struct { + u32 num_links:2, + ml_peer_id:12, + primary_link_idx:3, + primary_chip_id:2, + link_init_count:3, + non_str:1, + emlsr:1, + is_sta_ko:1, + num_local_links:2, + allocated:1, + reserved:4; + }; + u32 msg_dword_1; + }; + + union { + struct { + u32 participating_chips_bitmap:8, + reserved1:24; + }; + u32 msg_dword_2; + }; + + u32 ml_peer_flags; +}; + +#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M 0x0000003F +#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S 0 +#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M 0x00000FC0 +#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S 6 +#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M 0x0FFFF000 +#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S 12 + +#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \ + (((_var) & HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M) >> \ + HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S) + +#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD, _val); \ + ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S)); \ + } while (0) + +#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) \ + (((_var) & HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M) >> \ + HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S) + +#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD, _val); \ + ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S)); \ + } while (0) + +#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) \ + (((_var) & HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M) >> \ + HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S) + +#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX, _val); \ + ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M)); \ + ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S)); \ + } while (0) + +struct htt_ml_peer_ext_details_tlv { + union { + struct { + u32 peer_assoc_ipc_recvd:6, + sched_peer_delete_recvd:6, + mld_ast_index:16, + reserved:4; + }; + u32 msg_dword_1; + }; +}; + +#define HTT_ML_LINK_INFO_VALID_M 0x00000001 +#define HTT_ML_LINK_INFO_VALID_S 0 +#define HTT_ML_LINK_INFO_ACTIVE_M 0x00000002 +#define HTT_ML_LINK_INFO_ACTIVE_S 1 +#define HTT_ML_LINK_INFO_PRIMARY_M 0x00000004 +#define HTT_ML_LINK_INFO_PRIMARY_S 2 +#define HTT_ML_LINK_INFO_ASSOC_LINK_M 0x00000008 +#define HTT_ML_LINK_INFO_ASSOC_LINK_S 3 +#define HTT_ML_LINK_INFO_CHIP_ID_M 0x00000070 +#define HTT_ML_LINK_INFO_CHIP_ID_S 4 +#define HTT_ML_LINK_INFO_IEEE_LINK_ID_M 0x00007F80 +#define HTT_ML_LINK_INFO_IEEE_LINK_ID_S 7 +#define HTT_ML_LINK_INFO_HW_LINK_ID_M 0x00038000 +#define HTT_ML_LINK_INFO_HW_LINK_ID_S 15 +#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M 0x000C0000 +#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S 18 +#define HTT_ML_LINK_INFO_MASTER_LINK_M 0x00100000 +#define HTT_ML_LINK_INFO_MASTER_LINK_S 20 +#define HTT_ML_LINK_INFO_ANCHOR_LINK_M 0x00200000 +#define HTT_ML_LINK_INFO_ANCHOR_LINK_S 21 +#define HTT_ML_LINK_INFO_INITIALIZED_M 0x00400000 +#define HTT_ML_LINK_INFO_INITIALIZED_S 22 + +#define HTT_ML_LINK_INFO_SW_PEER_ID_M 0x0000ffff +#define HTT_ML_LINK_INFO_SW_PEER_ID_S 0 +#define HTT_ML_LINK_INFO_VDEV_ID_M 0x00ff0000 +#define HTT_ML_LINK_INFO_VDEV_ID_S 16 + +#define HTT_ML_LINK_INFO_VALID_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_VALID_M) >> \ + HTT_ML_LINK_INFO_VALID_S) + +#define HTT_ML_LINK_INFO_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VALID, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_VALID_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_VALID_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_ACTIVE_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_ACTIVE_M) >> \ + HTT_ML_LINK_INFO_ACTIVE_S) + +#define HTT_ML_LINK_INFO_ACTIVE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ACTIVE, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_ACTIVE_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_ACTIVE_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_PRIMARY_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_PRIMARY_M) >> \ + HTT_ML_LINK_INFO_PRIMARY_S) + +#define HTT_ML_LINK_INFO_PRIMARY_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_PRIMARY, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_PRIMARY_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_PRIMARY_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_ASSOC_LINK_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_ASSOC_LINK_M) >> \ + HTT_ML_LINK_INFO_ASSOC_LINK_S) + +#define HTT_ML_LINK_INFO_ASSOC_LINK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ASSOC_LINK, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_ASSOC_LINK_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_ASSOC_LINK_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_CHIP_ID_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_CHIP_ID_M) >> \ + HTT_ML_LINK_INFO_CHIP_ID_S) + +#define HTT_ML_LINK_INFO_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_CHIP_ID, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_CHIP_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_CHIP_ID_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_IEEE_LINK_ID_M) >> \ + HTT_ML_LINK_INFO_IEEE_LINK_ID_S) + +#define HTT_ML_LINK_INFO_IEEE_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_IEEE_LINK_ID, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_IEEE_LINK_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_IEEE_LINK_ID_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_HW_LINK_ID_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_HW_LINK_ID_M) >> \ + HTT_ML_LINK_INFO_HW_LINK_ID_S) + +#define HTT_ML_LINK_INFO_HW_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_HW_LINK_ID, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_HW_LINK_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_HW_LINK_ID_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M) >> \ + HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S) + +#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_LOGICAL_LINK_ID, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_MASTER_LINK_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_MASTER_LINK_M) >> \ + HTT_ML_LINK_INFO_MASTER_LINK_S) + +#define HTT_ML_LINK_INFO_MASTER_LINK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_MASTER_LINK, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_MASTER_LINK_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_MASTER_LINK_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_ANCHOR_LINK_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_ANCHOR_LINK_M) >> \ + HTT_ML_LINK_INFO_ANCHOR_LINK_S) + +#define HTT_ML_LINK_INFO_ANCHOR_LINK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ANCHOR_LINK, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_ANCHOR_LINK_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_ANCHOR_LINK_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_INITIALIZED_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_INITIALIZED_M) >> \ + HTT_ML_LINK_INFO_INITIALIZED_S) + +#define HTT_ML_LINK_INFO_INITIALIZED_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_INITIALIZED, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_INITIALIZED_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_INITIALIZED_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_SW_PEER_ID_M) >> \ + HTT_ML_LINK_INFO_SW_PEER_ID_S) + +#define HTT_ML_LINK_INFO_SW_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_SW_PEER_ID, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_SW_PEER_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_SW_PEER_ID_S)); \ + } while (0) + +#define HTT_ML_LINK_INFO_VDEV_ID_GET(_var) \ + (((_var) & HTT_ML_LINK_INFO_VDEV_ID_M) >> \ + HTT_ML_LINK_INFO_VDEV_ID_S) + +#define HTT_ML_LINK_INFO_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VDEV_ID, _val); \ + ((_var) &= ~(HTT_ML_LINK_INFO_VDEV_ID_M)); \ + ((_var) |= ((_val) << HTT_ML_LINK_INFO_VDEV_ID_S)); \ + } while (0) + +struct htt_ml_link_info_tlv { + union { + struct { + u32 valid:1, + active:1, + primary:1, + assoc_link:1, + chip_id:3, + ieee_link_id:8, + hw_link_id:3, + logical_link_id:2, + master_link:1, + anchor_link:1, + initialized:1, + reserved:9; + }; + u32 msg_dword_1; + }; + + union { + struct { + u32 sw_peer_id:16, + vdev_id:8, + reserved1:8; + }; + u32 msg_dword_2; + }; + + u32 primary_tid_mask; +}; + +struct htt_tx_pdev_ppdu_dur_stats_tlv { + /** Tx PPDU duration histogram **/ + u32 tx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; + u32 tx_success_time_us_low; + u32 tx_success_time_us_high; + u32 tx_fail_time_us_low; + u32 tx_fail_time_us_high; + u32 pdev_up_time_us_low; + u32 pdev_up_time_us_high; +}; + +struct htt_rx_pdev_ppdu_dur_stats_tlv { + /** Tx PPDU duration histogram **/ + u32 rx_ppdu_dur_hist[HTT_PDEV_STATS_PPDU_DUR_HIST_BINS]; +}; + +#define HTT_TX_PDEV_SIFS_BURST_HIST_STATS 10 +#define HTT_TX_PDEV_STATS_SIFS_HIST_TLV_SZ(_num_elems) (sizeof(u32) * (_num_elems)) + +struct htt_pdev_mbssid_ctrl_frame_stats_tlv { + /** mac_id__word: + * BIT [ 7 : 0] :- mac_id + * Use the HTT_STATS_CMN_MAC_ID_GET,_SET macros to + * read/write this bitfield. + * BIT [31 : 8] :- reserved + */ + u32 mac_id__word; + u32 basic_trigger_across_bss; + u32 basic_trigger_within_bss; + u32 bsr_trigger_across_bss; + u32 bsr_trigger_within_bss; + u32 mu_rts_across_bss; + u32 mu_rts_within_bss; + u32 ul_mumimo_trigger_across_bss; + u32 ul_mumimo_trigger_within_bss; +}; + +struct htt_odd_mandatory_pdev_stats_tlv { + u32 hw_queued; + u32 hw_reaped; + u32 hw_paused; + u32 hw_filt; + u32 seq_posted; + u32 seq_completed; + u32 underrun; + u32 hw_flush; + u32 next_seq_posted_dsr; + u32 seq_posted_isr; + u32 mpdu_cnt_fcs_ok; + u32 mpdu_cnt_fcs_err; + u32 msdu_count_tqm; + u32 mpdu_count_tqm; + u32 mpdus_ack_failed; + u32 num_data_ppdus_tried_ota; + u32 ppdu_ok; + u32 num_total_ppdus_tried_ota; + u32 thermal_suspend_cnt; + u32 dfs_suspend_cnt; + u32 tx_abort_suspend_cnt; + u32 suspended_txq_mask; + u32 last_suspend_reason; + u32 seq_failed_queueing; + u32 seq_restarted; + u32 seq_txop_repost_stop; + u32 next_seq_cancel; + u32 seq_min_msdu_repost_stop; + u32 total_phy_err_cnt; + u32 ppdu_recvd; + u32 tcp_msdu_cnt; + u32 tcp_ack_msdu_cnt; + u32 udp_msdu_cnt; + u32 fw_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; + u32 fw_rx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; + u32 fw_ring_mpdu_err[HTT_RX_STATS_RXDMA_MAX_ERR]; + u32 urrn_stats[HTT_TX_PDEV_MAX_URRN_STATS]; + u32 sifs_status[HTT_TX_PDEV_MAX_SIFS_BURST_STATS]; + u32 sifs_hist_status[HTT_TX_PDEV_SIFS_BURST_HIST_STATS]; + u32 rx_suspend_cnt; + u32 rx_suspend_fail_cnt; + u32 rx_resume_cnt; + u32 rx_resume_fail_cnt; + u32 hwq_beacon_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; + u32 hwq_voice_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; + u32 hwq_video_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; + u32 hwq_best_effort_cmd_result[HTT_TX_HWQ_MAX_CMD_RESULT_STATS]; + u32 hwq_beacon_mpdu_tried_cnt; + u32 hwq_voice_mpdu_tried_cnt; + u32 hwq_video_mpdu_tried_cnt; + u32 hwq_best_effort_mpdu_tried_cnt; + u32 hwq_beacon_mpdu_queued_cnt; + u32 hwq_voice_mpdu_queued_cnt; + u32 hwq_video_mpdu_queued_cnt; + u32 hwq_best_effort_mpdu_queued_cnt; + u32 hwq_beacon_mpdu_ack_fail_cnt; + u32 hwq_voice_mpdu_ack_fail_cnt; + u32 hwq_video_mpdu_ack_fail_cnt; + u32 hwq_best_effort_mpdu_ack_fail_cnt; + u32 pdev_resets; + u32 phy_warm_reset; + u32 hwsch_reset_count; + u32 phy_warm_reset_ucode_trig; + u32 mac_cold_reset; + u32 mac_warm_reset; + u32 mac_warm_reset_restore_cal; + u32 phy_warm_reset_m3_ssr; + u32 fw_rx_rings_reset; + u32 tx_flush; + u32 hwsch_dev_reset_war; + u32 mac_cold_reset_restore_cal; + u32 mac_only_reset; + u32 mac_sfm_reset; + u32 tx_ldpc; /* Number of tx PPDUs with LDPC coding */ + u32 rx_ldpc; /* Number of rx PPDUs with LDPC coding */ + u32 gen_mpdu_end_reason[HTT_TX_TQM_MAX_GEN_MPDU_END_REASON]; + u32 list_mpdu_end_reason[HTT_TX_TQM_MAX_LIST_MPDU_END_REASON]; + u32 tx_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; + u32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 half_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 quarter_tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 tx_su_punctured_mode[HTT_TX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; + u32 rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; + u32 rx_nss[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; + u32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; + u32 rts_cnt; + u32 rts_success; +}; + +struct htt_phy_counters_tlv { + u32 rx_ofdma_timing_err_cnt; + u32 rx_cck_fail_cnt; + u32 mactx_abort_cnt; + u32 macrx_abort_cnt; + u32 phytx_abort_cnt; + u32 phyrx_abort_cnt; + u32 phyrx_defer_abort_cnt; + u32 rx_gain_adj_lstf_event_cnt; + u32 rx_gain_adj_non_legacy_cnt; + u32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; + u32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; + u32 per_blk_err_cnt[HTT_MAX_PER_BLK_ERR_CNT]; + u32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; +}; + +struct htt_phy_stats_tlv { + s32 nf_chain[HTT_STATS_MAX_CHAINS]; + u32 false_radar_cnt; + u32 radar_cs_cnt; + s32 ani_level; + u32 fw_run_time; + s32 runtime_nf_chain[HTT_STATS_MAX_CHAINS]; + u32 current_operating_width; + u32 current_device_width; + u32 last_radar_type; + u32 dfs_reg_domain; + u32 radar_mask_bit; + s32 radar_rssi; + u32 radar_dfs_flags; + u32 band_center_frequency_operating; + u32 band_center_frequency_device; +}; + +struct htt_phy_reset_counters_tlv { + u32 pdev_id; + u32 cf_active_low_fail_cnt; + u32 cf_active_low_pass_cnt; + u32 phy_off_through_vreg_cnt; + u32 force_calibration_cnt; + u32 rf_mode_switch_phy_off_cnt; +}; + +struct htt_phy_reset_stats_tlv { + u32 pdev_id; + u32 chan_mhz; + u32 chan_band_center_freq1; + u32 chan_band_center_freq2; + u32 chan_phy_mode; + u32 chan_flags; + u32 chan_num; + u32 reset_cause; + u32 prev_reset_cause; + u32 phy_warm_reset_src; + u32 rx_gain_tbl_mode; + u32 xbar_val; + u32 force_calibration; + u32 phyrf_mode; + u32 phy_homechan; + u32 phy_tx_ch_mask; + u32 phy_rx_ch_mask; + u32 phybb_ini_mask; + u32 phyrf_ini_mask; + u32 phy_dfs_en_mask; + u32 phy_sscan_en_mask; + u32 phy_synth_sel_mask; + u32 phy_adfs_freq; + u32 cck_fir_settings; + u32 phy_dyn_pri_chan; + u32 cca_thresh; + u32 dyn_cca_status; + u32 rxdesense_thresh_hw; + u32 rxdesense_thresh_sw; +}; + +struct htt_peer_ctrl_path_txrx_stats_tlv { + u8 peer_mac_addr[6]; + u8 rsvd[2]; + u32 peer_tx_mgmt_subtype[ATH12K_STATS_MGMT_FRM_TYPE_MAX]; + u32 peer_rx_mgmt_subtype[ATH12K_STATS_MGMT_FRM_TYPE_MAX]; +}; + +struct htt_pdev_ctrl_path_tx_stats_tlv { + /* Num MGMT MPDU transmitted by the target */ + u32 fw_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; +}; + +enum htt_sched_txq_supercycle_triggers_tlv_enum { + HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, + HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, + HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, + HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, + HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, + HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, + HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, + + HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, +}; + +/* NOTE: Variable length TLV, use length spec to infer array size */ +struct htt_sched_txq_supercycle_triggers_tlv { + u32 supercycle_triggers[0]; /*HTT_SCHED_SUPERCYCLE_TRIGGER_MAX*/ +}; + +struct htt_hw_war_stats_tlv { + u32 mac_id__word; + u32 hw_wars[1]; +}; + +struct htt_peer_sched_stats_tlv { + u32 peer_id; + u32 num_sched_dl; + u32 num_sched_ul; + u32 peer_tx_active_dur_us_low; + u32 peer_tx_active_dur_us_high; + u32 peer_rx_active_dur_us_low; + u32 peer_rx_active_dur_us_high; + u32 peer_curr_rate_kbps; +}; + +struct htt_vdev_rtt_resp_stats_tlv { + /* No of Fine Timing Measurement frames transmitted successfully */ + u32 tx_ftm_suc; + /* No of Fine Timing Measurement frames transmitted successfully after retry */ + u32 tx_ftm_suc_retry; + /* No of Fine Timing Measurement frames not transmitted successfully */ + u32 tx_ftm_fail; + /* No of Fine Timing Measurement Request frames received, including initial, + * non-initial, and duplicates + */ + u32 rx_ftmr_cnt; + /* No of duplicate Fine Timing Measurement Request frames received, including + * both initial and non-initial + */ + u32 rx_ftmr_dup_cnt; + /* No of initial Fine Timing Measurement Request frames received */ + u32 rx_iftmr_cnt; + /* No of duplicate initial Fine Timing Measurement Request frames received */ + u32 rx_iftmr_dup_cnt; + /* No of responder sessions rejected when initiator was active */ + u32 initiator_active_responder_rejected_cnt; + /* Responder terminate count */ + u32 responder_terminate_cnt; + u32 vdev_id; +}; + +struct htt_vdev_rtt_init_stats_tlv { + u32 vdev_id; + /* No of Fine Timing Measurement request frames transmitted successfully */ + u32 tx_ftmr_cnt; + /* No of Fine Timing Measurement request frames not transmitted successfully */ + u32 tx_ftmr_fail; + /* No of Fine Timing Measurement request frames transmitted successfully + * after retry + */ + u32 tx_ftmr_suc_retry; + /* No of Fine Timing Measurement frames received, including initial, non-initial + * and duplicates + */ + u32 rx_ftm_cnt; + /* Initiator Terminate count */ + u32 initiator_terminate_cnt; + u32 tx_meas_req_count; +}; + +struct htt_pktlog_and_htt_ring_stats_tlv { + /* No of pktlog payloads that were dropped in htt_ppdu_stats path */ + u32 pktlog_lite_drop_cnt; + /* No of pktlog payloads that were dropped in TQM path */ + u32 pktlog_tqm_drop_cnt; + /* No of pktlog ppdu stats payloads that were dropped */ + u32 pktlog_ppdu_stats_drop_cnt; + /* No of pktlog ppdu ctrl payloads that were dropped */ + u32 pktlog_ppdu_ctrl_drop_cnt; + /* No of pktlog sw events payloads that were dropped */ + u32 pktlog_sw_events_drop_cnt; +}; + +#define HTT_DLPAGER_STATS_MAX_HIST 10 +#define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M 0x000000FF +#define HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S 0 +#define HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M 0x0000FF00 +#define HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S 8 +#define HTT_DLPAGER_TOTAL_LOCKED_PAGES_M 0x0000FFFF +#define HTT_DLPAGER_TOTAL_LOCKED_PAGES_S 0 +#define HTT_DLPAGER_TOTAL_FREE_PAGES_M 0xFFFF0000 +#define HTT_DLPAGER_TOTAL_FREE_PAGES_S 16 +#define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M 0x0000FFFF +#define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S 0 +#define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M 0xFFFF0000 +#define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S 16 + +#define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_GET(_var) \ + (((_var) & HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M) >> \ + HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S) + +#define HTT_DLPAGER_ASYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT, _val); \ + ((_var) &= ~(HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_M));\ + ((_var) |= ((_val) << HTT_DLPAGER_ASYNC_LOCKED_PAGE_COUNT_S)); \ + } while (0) + +#define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_GET(_var) \ + (((_var) & HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M) >> \ + HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S) + +#define HTT_DLPAGER_SYNC_LOCK_PAGE_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT, _val); \ + ((_var) &= ~(HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_M));\ + ((_var) |= ((_val) << HTT_DLPAGER_SYNC_LOCKED_PAGE_COUNT_S)); \ + } while (0) + +#define HTT_DLPAGER_TOTAL_LOCKED_PAGES_GET(_var) \ + (((_var) & HTT_DLPAGER_TOTAL_LOCKED_PAGES_M) >> \ + HTT_DLPAGER_TOTAL_LOCKED_PAGES_S) + +#define HTT_DLPAGER_TOTAL_LOCKED_PAGES_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_DLPAGER_TOTAL_LOCKED_PAGES, _val); \ + ((_var) &= ~(HTT_DLPAGER_TOTAL_LOCKED_PAGES_M)); \ + ((_var) |= ((_val) << HTT_DLPAGER_TOTAL_LOCKED_PAGES_S)); \ + } while (0) + +#define HTT_DLPAGER_TOTAL_FREE_PAGES_GET(_var) \ + (((_var) & HTT_DLPAGER_TOTAL_FREE_PAGES_M) >> \ + HTT_DLPAGER_TOTAL_FREE_PAGES_S) + +#define HTT_DLPAGER_TOTAL_FREE_PAGES_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_DLPAGER_TOTAL_FREE_PAGES, _val); \ + ((_var) &= ~(HTT_DLPAGER_TOTAL_FREE_PAGES_M)); \ + ((_var) |= ((_val) << HTT_DLPAGER_TOTAL_FREE_PAGES_S)); \ + } while (0) + +#define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_GET(_var) \ + (((_var) & HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M) >> \ + HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S) + +#define HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_DLPAGER_LAST_LOCKED_PAGE_IDX, _val); \ + ((_var) &= ~(HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_M)); \ + ((_var) |= ((_val) << HTT_DLPAGER_LAST_LOCKED_PAGE_IDX_S)); \ + } while (0) + +#define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_GET(_var) \ + (((_var) & HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M) >> \ + HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S) + +#define HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX, _val); \ + ((_var) &= ~(HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_M)); \ + ((_var) |= ((_val) << HTT_DLPAGER_LAST_UNLOCKED_PAGE_IDX_S)); \ + } while (0) + +enum { + HTT_STATS_PAGE_LOCKED = 0, + HTT_STATS_PAGE_UNLOCKED = 1, + HTT_STATS_NUM_PAGE_LOCK_STATES +}; + +struct htt_dl_pager_stats_tlv { + /* msg_dword_1 bitfields: + * async_lock : 8, + * sync_lock : 8, + * reserved : 16; + */ + u32 msg_dword_1; + /* mst_dword_2 bitfields: + * total_locked_pages : 16, + * total_free_pages : 16; + */ + u32 msg_dword_2; + /* msg_dword_3 bitfields: + * last_locked_page_idx : 16, + * last_unlocked_page_idx : 16; + */ + u32 msg_dword_3; + + struct { + u32 page_num; + u32 num_of_pages; + /* timestamp is in microsecond units, from SoC timer clock */ + u32 timestamp_lsbs; + u32 timestamp_msbs; + } last_pages_info[HTT_STATS_NUM_PAGE_LOCK_STATES][HTT_DLPAGER_STATS_MAX_HIST]; +}; + +struct htt_stats_error_tlv_v { + u32 htt_stats_type; +}; + +#define HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7 + +struct htt_tx_selfgen_ac_sched_status_stats_tlv { + /* 11AC VHT SU NDPA scheduler completion status reason code */ + u32 ac_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AC VHT SU NDP scheduler completion status reason code */ + u32 ac_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AC VHT SU NDP scheduler error code */ + u32 ac_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + /* 11AC VHT MU MIMO NDPA scheduler completion status reason code */ + u32 ac_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AC VHT MU MIMO NDP scheduler completion status reason code */ + u32 ac_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AC VHT MU MIMO NDP scheduler error code */ + u32 ac_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + /* 11AC VHT MU MIMO BRPOLL scheduler completion status reason code */ + u32 ac_mu_mimo_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AC VHT MU MIMO BRPOLL scheduler error code */ + u32 ac_mu_mimo_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; +}; + +struct htt_tx_selfgen_ax_sched_status_stats_tlv { + /* 11AX HE SU NDPA scheduler completion status reason code */ + u32 ax_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX SU NDP scheduler completion status reason code */ + u32 ax_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX HE SU NDP scheduler error code */ + u32 ax_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + /* 11AX HE MU MIMO NDPA scheduler completion status reason code */ + u32 ax_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX HE MU MIMO NDP scheduler completion status reason code */ + u32 ax_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX HE MU MIMO NDP scheduler error code */ + u32 ax_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + /* 11AX HE MU MIMO MU BRPOLL scheduler completion status reason code */ + u32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX HE MU MIMO MU BRPOLL scheduler error code */ + u32 ax_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + /* 11AX HE MU BAR scheduler completion status reason code */ + u32 ax_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX HE MU BAR scheduler error code */ + u32 ax_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + /* 11AX HE UL OFDMA Basic Trigger scheduler completion status reason code */ + u32 ax_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX HE UL OFDMA Basic Trigger scheduler error code */ + u32 ax_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + /* 11AX HE UL MUMIMO Basic Trigger scheduler completion status reason code */ + u32 ax_ulmumimo_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + /* 11AX HE UL MUMIMO Basic Trigger scheduler error code */ + u32 ax_ulmumimo_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; +}; + +enum htt_stats_rc_mode { + HTT_STATS_RC_MODE_DLSU = 0, + HTT_STATS_RC_MODE_DLMUMIMO = 1, +}; + +struct htt_tx_rate_stats_t { + u32 ppdus_tried; + u32 ppdus_ack_failed; + u32 mpdus_tried; + u32 mpdus_failed; +}; + +struct htt_tx_per_rate_stats_tlv { + u32 rc_mode; + u32 last_probed_mcs; + u32 last_probed_nss; + u32 last_probed_bw; + + struct htt_tx_rate_stats_t per_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; + struct htt_tx_rate_stats_t per_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + struct htt_tx_rate_stats_t per_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + + /** 320MHz extension for PER */ + struct htt_tx_rate_stats_t per_bw320; +}; + +struct htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv { + u32 ax_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +}; + +struct htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv { + u32 ax_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + u32 ax_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +}; + +struct htt_t2h_soc_txrx_stats_common_tlv { + u32 inv_peers_msdu_drop_count_hi; + u32 inv_peers_msdu_drop_count_lo; +}; + +struct htt_t2h_vdev_txrx_stats_hw_stats_tlv { + u32 vdev_id; + u32 rx_msdu_byte_cnt_hi; + u32 rx_msdu_byte_cnt_lo; + u32 rx_msdu_cnt_hi; + u32 rx_msdu_cnt_lo; + u32 tx_msdu_byte_cnt_hi; + u32 tx_msdu_byte_cnt_lo; + u32 tx_msdu_cnt_hi; + u32 tx_msdu_cnt_lo; + u32 tx_msdu_excessive_retry_discard_cnt_hi; + u32 tx_msdu_excessive_retry_discard_cnt_lo; + u32 tx_msdu_cong_ctrl_drop_cnt_hi; + u32 tx_msdu_cong_ctrl_drop_cnt_lo; + u32 tx_msdu_ttl_expire_drop_cnt_hi; + u32 tx_msdu_ttl_expire_drop_cnt_lo; +}; + +struct htt_tx_pdev_dl_mu_mimo_sch_stats_tlv { + /* Number of MU MIMO schedules posted to HW */ + u32 mu_mimo_sch_posted; + /* Number of MU MIMO schedules failed to post */ + u32 mu_mimo_sch_failed; + /* Number of MU MIMO PPDUs posted to HW */ + u32 mu_mimo_ppdu_posted; + /* + * This is the common description for the below sch stats. + * Counts the number of transmissions of each number of MU users + * in each TX mode. + * The array index is the "number of users - 1". + * For example, ac_mu_mimo_sch_nusers[1] counts the number of 11AC MU2 + * TX PPDUs, ac_mu_mimo_sch_nusers[2] counts the number of 11AC MU3 + * TX PPDUs and so on. + * The same is applicable for the other TX mode stats. + */ + /* Represents the count for 11AC DL MU MIMO sequences */ + u32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; + /* Represents the count for 11AX DL MU MIMO sequences */ + u32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + /* Number of 11AC DL MU MIMO schedules posted per group size */ + u32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; + /* Number of 11AX DL MU MIMO schedules posted per group size */ + u32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; +}; + +struct htt_tx_pdev_ul_mu_mimo_sch_stats_tlv { + /* Represents the count for 11AX UL MU MIMO sequences with Basic Triggers */ + u32 ax_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; + /* Represents the count for 11AX UL MU MIMO sequences with BRP Triggers */ + u32 ax_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; +}; + +/* UL RESP Queues 0 - HIPRI, 1 - LOPRI & 2 - BSR */ +#define HTT_STA_UL_OFDMA_NUM_UL_QUEUES 3 + +/* Actual resp type sent by STA for trigger + * 0 - HE TB PPDU, 1 - NULL Delimiter + */ +#define HTT_STA_UL_OFDMA_NUM_RESP_END_TYPE 2 + +/* Counter for MCS 0-13 */ +#define HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS 14 + +/* Counters BW 20,40,80,160,320 */ +#define HTT_STA_UL_OFDMA_NUM_BW_COUNTERS 5 + +/* 0 - Half, 1 - Quarter */ +#define HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES 2 + +#define HTT_NUM_AC_WMM 0x4 + +enum HTT_STA_UL_OFDMA_RX_TRIG_TYPE { + HTT_ULTRIG_QBOOST_TRIGGER = 0, + HTT_ULTRIG_PSPOLL_TRIGGER, + HTT_ULTRIG_UAPSD_TRIGGER, + HTT_ULTRIG_11AX_TRIGGER, + HTT_ULTRIG_11AX_WILDCARD_TRIGGER, + HTT_ULTRIG_11AX_UNASSOC_WILDCARD_TRIGGER, + HTT_STA_UL_OFDMA_NUM_TRIG_TYPE, +}; + +enum HTT_STA_UL_OFDMA_11AX_TRIG_TYPE { + HTT_11AX_TRIGGER_BASIC_E = 0, + HTT_11AX_TRIGGER_BRPOLL_E = 1, + HTT_11AX_TRIGGER_MU_BAR_E = 2, + HTT_11AX_TRIGGER_MU_RTS_E = 3, + HTT_11AX_TRIGGER_BUFFER_SIZE_E = 4, + HTT_11AX_TRIGGER_GCR_MU_BAR_E = 5, + HTT_11AX_TRIGGER_BQRP_E = 6, + HTT_11AX_TRIGGER_NDP_FB_REPORT_POLL_E = 7, + HTT_11AX_TRIGGER_RESERVED_8_E = 8, + HTT_11AX_TRIGGER_RESERVED_9_E = 9, + HTT_11AX_TRIGGER_RESERVED_10_E = 10, + HTT_11AX_TRIGGER_RESERVED_11_E = 11, + HTT_11AX_TRIGGER_RESERVED_12_E = 12, + HTT_11AX_TRIGGER_RESERVED_13_E = 13, + HTT_11AX_TRIGGER_RESERVED_14_E = 14, + HTT_11AX_TRIGGER_RESERVED_15_E = 15, + HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE, +}; + +struct htt_print_sta_ul_ofdma_stats_tlv { + u32 pdev_id; + /* Trigger Type reported by HWSCH on RX reception + * Each index populate enum HTT_STA_UL_OFDMA_RX_TRIG_TYPE + */ + u32 rx_trigger_type[HTT_STA_UL_OFDMA_NUM_TRIG_TYPE]; + /* 11AX Trigger Type on RX reception + * Each index populate enum HTT_STA_UL_OFDMA_11AX_TRIG_TYPE + */ + u32 ax_trigger_type[HTT_STA_UL_OFDMA_NUM_11AX_TRIG_TYPE]; + /* Num data PPDUs/Delims responded to trigs. per HWQ for UL RESP */ + u32 num_data_ppdu_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; + u32 num_null_delimiters_responded_per_hwq[HTT_STA_UL_OFDMA_NUM_UL_QUEUES]; + /* Overall UL STA RESP Status 0 - HE TB PPDU, 1 - NULL Delimiter + * Super set of num_data_ppdu_responded_per_hwq, + * num_null_delimiters_responded_per_hwq + */ + u32 num_total_trig_responses[HTT_STA_UL_OFDMA_NUM_RESP_END_TYPE]; + /* Time interval between current time ms and last successful trigger RX + * 0xFFFFFFFF denotes no trig received / timestamp roll back + */ + u32 last_trig_rx_time_delta_ms; + /* Rate Statistics for UL OFDMA + * UL TB PPDU TX MCS, NSS, GI, BW from STA HWQ + */ + u32 ul_ofdma_tx_mcs[HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; + u32 ul_ofdma_tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + u32 ul_ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] + [HTT_STA_UL_OFDMA_NUM_MCS_COUNTERS]; + u32 ul_ofdma_tx_ldpc; + u32 ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; + + /* Trig based PPDU TX/ RBO based PPDU TX Count */ + u32 trig_based_ppdu_tx; + u32 rbo_based_ppdu_tx; + /* Switch MU EDCA to SU EDCA Count */ + u32 mu_edca_to_su_edca_switch_count; + /* Num MU EDCA applied Count */ + u32 num_mu_edca_param_apply_count; + + /* Current MU EDCA Parameters for WMM ACs + * Mode - 0 - SU EDCA, 1- MU EDCA + */ + u32 current_edca_hwq_mode[HTT_NUM_AC_WMM]; + /* Contention Window minimum. Range: 1 - 10 */ + u32 current_cw_min[HTT_NUM_AC_WMM]; + /* Contention Window maximum. Range: 1 - 10 */ + u32 current_cw_max[HTT_NUM_AC_WMM]; + /* AIFS value - 0 -255 */ + u32 current_aifs[HTT_NUM_AC_WMM]; + u32 reduced_ul_ofdma_tx_bw[HTT_STA_UL_OFDMA_NUM_REDUCED_CHAN_TYPES] + [HTT_STA_UL_OFDMA_NUM_BW_COUNTERS]; +}; + +struct htt_tx_pdev_mu_edca_params_stats_tlv_v { + u32 relaxed_mu_edca[HTT_NUM_AC_WMM]; + u32 mumimo_aggressive_mu_edca[HTT_NUM_AC_WMM]; + u32 mumimo_relaxed_mu_edca[HTT_NUM_AC_WMM]; + u32 muofdma_aggressive_mu_edca[HTT_NUM_AC_WMM]; + u32 muofdma_relaxed_mu_edca[HTT_NUM_AC_WMM]; + u32 latency_mu_edca[HTT_NUM_AC_WMM]; + u32 psd_boost_mu_edca[HTT_NUM_AC_WMM]; +}; + +struct htt_tx_pdev_ap_edca_params_stats_tlv_v { + u32 ul_mumimo_less_aggressive[HTT_NUM_AC_WMM]; + u32 ul_mumimo_medium_aggressive[HTT_NUM_AC_WMM]; + u32 ul_mumimo_highly_aggressive[HTT_NUM_AC_WMM]; + u32 ul_mumimo_default_relaxed[HTT_NUM_AC_WMM]; + u32 ul_muofdma_less_aggressive[HTT_NUM_AC_WMM]; + u32 ul_muofdma_medium_aggressive[HTT_NUM_AC_WMM]; + u32 ul_muofdma_highly_aggressive[HTT_NUM_AC_WMM]; + u32 ul_muofdma_default_relaxed[HTT_NUM_AC_WMM]; +}; + +struct htt_peer_ax_ofdma_stats_tlv { + u32 peer_id; + u32 ax_basic_trig_count; + u32 ax_basic_trig_err; + u32 ax_bsr_trig_count; + u32 ax_bsr_trig_err; + u32 ax_mu_bar_trig_count; + u32 ax_mu_bar_trig_err; + u32 ax_basic_trig_with_per; + u32 ax_bsr_trig_with_per; + u32 ax_mu_bar_trig_with_per; + /* is_airtime_large_for_dl_ofdma, is_airtime_large_for_ul_ofdma + * These fields contain 2 counters each. The first element in each + * array counts how many times the airtime is short enough to use + * OFDMA, and the second element in each array counts how many times the + * airtime is too large to select OFDMA for the PPDUs involving the peer. + */ + u32 is_airtime_large_for_dl_ofdma[2]; + u32 is_airtime_large_for_ul_ofdma[2]; + /* Last updated value of DL and UL queue depths for each peer per AC */ + u32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; + u32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; +}; + +struct htt_pdev_sched_algo_ofdma_stats_tlv { + /** + * BIT [ 7 : 0] :- mac_id + * BIT [31 : 8] :- reserved + */ + union { + struct { + u32 mac_id:8, + reserved:24; + }; + u32 mac_id__word; + }; + u32 rate_based_dlofdma_enabled_count[HTT_NUM_AC_WMM]; + u32 rate_based_dlofdma_disabled_count[HTT_NUM_AC_WMM]; + u32 rate_based_dlofdma_probing_count[HTT_NUM_AC_WMM]; + u32 rate_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM]; + u32 chan_acc_lat_based_dlofdma_enabled_count[HTT_NUM_AC_WMM]; + u32 chan_acc_lat_based_dlofdma_disabled_count[HTT_NUM_AC_WMM]; + u32 chan_acc_lat_based_dlofdma_monitoring_count[HTT_NUM_AC_WMM]; + u32 downgrade_to_dl_su_ru_alloc_fail[HTT_NUM_AC_WMM]; + u32 candidate_list_single_user_disable_ofdma[HTT_NUM_AC_WMM]; + u32 dl_cand_list_dropped_high_ul_qos_weight[HTT_NUM_AC_WMM]; + u32 ax_dlofdma_disabled_due_to_pipelining[HTT_NUM_AC_WMM]; + u32 dlofdma_disabled_su_only_eligible[HTT_NUM_AC_WMM]; + u32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM]; + u32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM]; +}; + +struct htt_umac_ssr_stats_tlv { + u32 total_done; + u32 trigger_requests_count; + u32 total_trig_dropped; + u32 umac_disengaged_count; + u32 umac_soft_reset_count; + u32 umac_engaged_count; + u32 last_trigger_request_ms; + u32 last_start_ms; + u32 last_start_disengage_umac_ms; + u32 last_enter_ssr_platform_thread_ms; + u32 last_exit_ssr_platform_thread_ms; + u32 last_start_engage_umac_ms; + u32 last_done_successful_ms; + u32 last_e2e_delta_ms; + u32 max_e2e_delta_ms; + u32 trigger_count_for_umac_hang; + u32 trigger_count_for_mlo_quick_ssr; + u32 trigger_count_for_unknown_signature; + u32 post_reset_tqm_sync_cmd_completion_ms; + u32 htt_sync_mlo_initiate_umac_recovery_ms; + u32 htt_sync_do_pre_reset_ms; + u32 htt_sync_do_post_reset_start_ms; + u32 htt_sync_do_post_reset_complete_ms; +}; + +#endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debugfs_sta.c 2024-01-19 17:01:19.857846811 +0100 @@ -0,0 +1,1929 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include + +#include "debugfs_sta.h" +#include "core.h" +#include "peer.h" +#include "debug.h" +#include "dp_tx.h" +#include "debugfs_htt_stats.h" +#include "debugfs.h" + +void ath12k_debugfs_sta_add_tx_stats(struct ath12k_link_sta *arsta, + struct ath12k_per_peer_tx_stats *peer_stats, + u8 legacy_rate_idx) +{ + struct rate_info *txrate = &arsta->txrate; + struct ath12k_htt_tx_stats *tx_stats; + int gi, mcs, bw, nss, ru_type, ppdu_type; + + if (!arsta->tx_stats) + return; + + tx_stats = arsta->tx_stats; + gi = FIELD_GET(RATE_INFO_FLAGS_SHORT_GI, arsta->txrate.flags); + mcs = txrate->mcs; + bw = ath12k_mac_mac80211_bw_to_ath12k_bw(txrate->bw); + nss = txrate->nss - 1; + +#define STATS_OP_FMT(name) tx_stats->stats[ATH12K_STATS_TYPE_##name] + + if (txrate->flags & RATE_INFO_FLAGS_EHT_MCS) { + STATS_OP_FMT(SUCC).eht[0][mcs] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).eht[1][mcs] += peer_stats->succ_pkts; + STATS_OP_FMT(FAIL).eht[0][mcs] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).eht[1][mcs] += peer_stats->failed_pkts; + STATS_OP_FMT(RETRY).eht[0][mcs] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).eht[1][mcs] += peer_stats->retry_pkts; + } else if (txrate->flags & RATE_INFO_FLAGS_HE_MCS) { + STATS_OP_FMT(SUCC).he[0][mcs] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).he[1][mcs] += peer_stats->succ_pkts; + STATS_OP_FMT(FAIL).he[0][mcs] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).he[1][mcs] += peer_stats->failed_pkts; + STATS_OP_FMT(RETRY).he[0][mcs] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).he[1][mcs] += peer_stats->retry_pkts; + } else if (txrate->flags & RATE_INFO_FLAGS_VHT_MCS) { + STATS_OP_FMT(SUCC).vht[0][mcs] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).vht[1][mcs] += peer_stats->succ_pkts; + STATS_OP_FMT(FAIL).vht[0][mcs] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).vht[1][mcs] += peer_stats->failed_pkts; + STATS_OP_FMT(RETRY).vht[0][mcs] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).vht[1][mcs] += peer_stats->retry_pkts; + } else if (txrate->flags & RATE_INFO_FLAGS_MCS) { + STATS_OP_FMT(SUCC).ht[0][mcs] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).ht[1][mcs] += peer_stats->succ_pkts; + STATS_OP_FMT(FAIL).ht[0][mcs] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).ht[1][mcs] += peer_stats->failed_pkts; + STATS_OP_FMT(RETRY).ht[0][mcs] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).ht[1][mcs] += peer_stats->retry_pkts; + } else { + mcs = legacy_rate_idx; + + STATS_OP_FMT(SUCC).legacy[0][mcs] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).legacy[1][mcs] += peer_stats->succ_pkts; + STATS_OP_FMT(FAIL).legacy[0][mcs] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).legacy[1][mcs] += peer_stats->failed_pkts; + STATS_OP_FMT(RETRY).legacy[0][mcs] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).legacy[1][mcs] += peer_stats->retry_pkts; + } + + ppdu_type = peer_stats->ppdu_type; + if ((ppdu_type == HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA || + ppdu_type == HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA) && + (txrate->flags & RATE_INFO_FLAGS_HE_MCS || + txrate->flags & RATE_INFO_FLAGS_EHT_MCS)) { + ru_type = peer_stats->ru_tones; + + if (ru_type <= NL80211_RATE_INFO_HE_RU_ALLOC_996) { + STATS_OP_FMT(SUCC).ru_loc[0][ru_type] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).ru_loc[1][ru_type] += peer_stats->succ_pkts; + STATS_OP_FMT(FAIL).ru_loc[0][ru_type] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).ru_loc[1][ru_type] += peer_stats->failed_pkts; + STATS_OP_FMT(RETRY).ru_loc[0][ru_type] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).ru_loc[1][ru_type] += peer_stats->retry_pkts; + if (peer_stats->is_ampdu) { + STATS_OP_FMT(AMPDU).ru_loc[0][ru_type] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).ru_loc[1][ru_type] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + } + } + } + + if (ppdu_type < HTT_PPDU_STATS_PPDU_TYPE_MAX) { + STATS_OP_FMT(SUCC).transmit_type[0][ppdu_type] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).transmit_type[1][ppdu_type] += peer_stats->succ_pkts; + STATS_OP_FMT(FAIL).transmit_type[0][ppdu_type] += + peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).transmit_type[1][ppdu_type] += peer_stats->failed_pkts; + STATS_OP_FMT(RETRY).transmit_type[0][ppdu_type] += + peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).transmit_type[1][ppdu_type] += peer_stats->retry_pkts; + if (peer_stats->is_ampdu) { + STATS_OP_FMT(AMPDU).transmit_type[0][ppdu_type] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).transmit_type[1][ppdu_type] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + } + } + + if (peer_stats->is_ampdu) { + tx_stats->ba_fails += peer_stats->ba_fails; + + if (txrate->flags & RATE_INFO_FLAGS_EHT_MCS) { + STATS_OP_FMT(AMPDU).eht[0][mcs] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).eht[1][mcs] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + } else if (txrate->flags & RATE_INFO_FLAGS_HE_MCS) { + STATS_OP_FMT(AMPDU).he[0][mcs] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).he[1][mcs] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + } else if (txrate->flags & RATE_INFO_FLAGS_MCS) { + STATS_OP_FMT(AMPDU).ht[0][mcs] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).ht[1][mcs] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + } else { + STATS_OP_FMT(AMPDU).vht[0][mcs] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).vht[1][mcs] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + } + STATS_OP_FMT(AMPDU).bw[0][bw] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).nss[0][nss] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).gi[0][gi] += + peer_stats->succ_bytes + peer_stats->retry_bytes; + STATS_OP_FMT(AMPDU).bw[1][bw] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + STATS_OP_FMT(AMPDU).nss[1][nss] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + STATS_OP_FMT(AMPDU).gi[1][gi] += + peer_stats->succ_pkts + peer_stats->retry_pkts; + } else { + tx_stats->ack_fails += peer_stats->ba_fails; + } + + STATS_OP_FMT(SUCC).bw[0][bw] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).nss[0][nss] += peer_stats->succ_bytes; + STATS_OP_FMT(SUCC).gi[0][gi] += peer_stats->succ_bytes; + + STATS_OP_FMT(SUCC).bw[1][bw] += peer_stats->succ_pkts; + STATS_OP_FMT(SUCC).nss[1][nss] += peer_stats->succ_pkts; + STATS_OP_FMT(SUCC).gi[1][gi] += peer_stats->succ_pkts; + + STATS_OP_FMT(FAIL).bw[0][bw] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).nss[0][nss] += peer_stats->failed_bytes; + STATS_OP_FMT(FAIL).gi[0][gi] += peer_stats->failed_bytes; + + STATS_OP_FMT(FAIL).bw[1][bw] += peer_stats->failed_pkts; + STATS_OP_FMT(FAIL).nss[1][nss] += peer_stats->failed_pkts; + STATS_OP_FMT(FAIL).gi[1][gi] += peer_stats->failed_pkts; + + STATS_OP_FMT(RETRY).bw[0][bw] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).nss[0][nss] += peer_stats->retry_bytes; + STATS_OP_FMT(RETRY).gi[0][gi] += peer_stats->retry_bytes; + + STATS_OP_FMT(RETRY).bw[1][bw] += peer_stats->retry_pkts; + STATS_OP_FMT(RETRY).nss[1][nss] += peer_stats->retry_pkts; + STATS_OP_FMT(RETRY).gi[1][gi] += peer_stats->retry_pkts; + + tx_stats->tx_duration += peer_stats->duration; + + tx_stats->ru_start = peer_stats->ru_start; + tx_stats->ru_tones = peer_stats->ru_tones; + + if (peer_stats->mu_grpid <= MAX_MU_GROUP_ID && + peer_stats->ppdu_type != HTT_PPDU_STATS_PPDU_TYPE_SU) { + if (peer_stats->mu_grpid & (MAX_MU_GROUP_ID - 1)) + tx_stats->mu_group[peer_stats->mu_grpid] = + (peer_stats->mu_pos + 1); + } +} + +void ath12k_debugfs_sta_update_txcompl(struct ath12k *ar, + struct hal_tx_status *ts) +{ + ath12k_dp_tx_update_txcompl(ar, ts); +} + +static ssize_t ath12k_dbg_sta_dump_tx_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + struct ath12k_htt_data_stats *stats; + static const char *str_name[ATH12K_STATS_TYPE_MAX] = {"success", "fail", + "retry", "ampdu"}; + static const char *str[ATH12K_COUNTER_TYPE_MAX] = {"bytes", "packets"}; + int len = 0, i, j, k, retval = 0; + const int size = 2 * 4096; + char *buf, mu_group_id[MAX_MU_GROUP_LENGTH] = {0}; + u32 index; + char *fields[] = {[HAL_WBM_REL_HTT_TX_COMP_STATUS_OK] = "Acked pkt count", + [HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL] = "Status ttl pkt count", + [HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP] = "Dropped pkt count", + [HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ] = "Reinj pkt count", + [HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT] = "Inspect pkt count", + [HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY] = "MEC notify pkt count"}; + int idx; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + if (!arsta->tx_stats || !arsta->wbm_tx_stats) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + + spin_lock_bh(&ar->data_lock); + for (k = 0; k < ATH12K_STATS_TYPE_MAX; k++) { + for (j = 0; j < ATH12K_COUNTER_TYPE_MAX; j++) { + stats = &arsta->tx_stats->stats[k]; + len += scnprintf(buf + len, size - len, "%s_%s\n", + str_name[k], + str[j]); + len += scnprintf(buf + len, size - len, "==========\n"); + len += scnprintf(buf + len, size - len, + " EHT MCS %s\n\t", + str[j]); + for (i = 0; i < ATH12K_EHT_MCS_NUM; i++) + len += scnprintf(buf + len, size - len, + "%llu ", + stats->eht[j][i]); + len += scnprintf(buf + len, size - len, "\n"); + len += scnprintf(buf + len, size - len, + " HE MCS %s\n\t", + str[j]); + for (i = 0; i < ATH12K_HE_MCS_NUM; i++) + len += scnprintf(buf + len, size - len, + "%llu ", + stats->he[j][i]); + len += scnprintf(buf + len, size - len, "\n"); + len += scnprintf(buf + len, size - len, + " VHT MCS %s\n\t", + str[j]); + for (i = 0; i < ATH12K_VHT_MCS_NUM; i++) + len += scnprintf(buf + len, size - len, + "%llu ", + stats->vht[j][i]); + len += scnprintf(buf + len, size - len, "\n"); + len += scnprintf(buf + len, size - len, " HT MCS %s\n\t", + str[j]); + for (i = 0; i < ATH12K_HT_MCS_NUM; i++) + len += scnprintf(buf + len, size - len, + "%llu ", stats->ht[j][i]); + len += scnprintf(buf + len, size - len, "\n"); + len += scnprintf(buf + len, size - len, + " BW %s (20,40,80,160,320 MHz)\n", str[j]); + len += scnprintf(buf + len, size - len, + "\t%llu %llu %llu %llu %llu\n", + stats->bw[j][0], stats->bw[j][1], + stats->bw[j][2], stats->bw[j][3], + stats->bw[j][4]); + len += scnprintf(buf + len, size - len, + " NSS %s (1x1,2x2,3x3,4x4)\n", str[j]); + len += scnprintf(buf + len, size - len, + "\t%llu %llu %llu %llu\n", + stats->nss[j][0], stats->nss[j][1], + stats->nss[j][2], stats->nss[j][3]); + len += scnprintf(buf + len, size - len, + " GI %s (0.4us,0.8us,1.6us,3.2us)\n", + str[j]); + len += scnprintf(buf + len, size - len, + "\t%llu %llu %llu %llu\n", + stats->gi[j][0], stats->gi[j][1], + stats->gi[j][2], stats->gi[j][3]); + len += scnprintf(buf + len, size - len, + " legacy rate %s (1,2 ... Mbps)\n ", + str[j]); + for (i = 0; i < ATH12K_LEGACY_NUM; i++) + len += scnprintf(buf + len, size - len, "%llu ", + stats->legacy[j][i]); + + len += scnprintf(buf + len, size - len, "\n ru %s:\n", str[j]); + len += scnprintf(buf + len, size - len, + "\tru 26: %llu\n", stats->ru_loc[j][0]); + len += scnprintf(buf + len, size - len, + "\tru 52: %llu\n", stats->ru_loc[j][1]); + len += scnprintf(buf + len, size - len, + "\tru 106: %llu\n", stats->ru_loc[j][2]); + len += scnprintf(buf + len, size - len, + "\tru 242: %llu\n", stats->ru_loc[j][3]); + len += scnprintf(buf + len, size - len, + "\tru 484: %llu\n", stats->ru_loc[j][4]); + len += scnprintf(buf + len, size - len, + "\tru 996: %llu\n", stats->ru_loc[j][5]); + + len += scnprintf(buf + len, size - len, + " ppdu type %s:\n", str[j]); + if (k == ATH12K_STATS_TYPE_FAIL || + k == ATH12K_STATS_TYPE_RETRY) { + len += scnprintf(buf + len, size - len, + "\tSU/MIMO: %llu\n", + stats->transmit_type[j][0]); + len += scnprintf(buf + len, size - len, + "\tOFDMA/OFDMA_MIMO: %llu\n", + stats->transmit_type[j][2]); + } else { + len += scnprintf(buf + len, size - len, + "\tSU: %llu\n", + stats->transmit_type[j][0]); + len += scnprintf(buf + len, size - len, + "\tMIMO: %llu\n", + stats->transmit_type[j][1]); + len += scnprintf(buf + len, size - len, + "\tOFDMA: %llu\n", + stats->transmit_type[j][2]); + len += scnprintf(buf + len, size - len, + "\tOFDMA_MIMO: %llu\n", + stats->transmit_type[j][3]); + } + } + } + + len += scnprintf(buf + len, size - len, "\n"); + + for (i = 0; i < MAX_MU_GROUP_ID;) { + index = 0; + for (j = 0; j < MAX_MU_GROUP_SHOW && i < MAX_MU_GROUP_ID; j++) { + index += snprintf(&mu_group_id[index], + MAX_MU_GROUP_LENGTH - index, + " %d", + arsta->tx_stats->mu_group[i]); + i++; + } + len += scnprintf(buf + len, size - len, + "User position list for GID %02d->%d: [%s]\n", + i - MAX_MU_GROUP_SHOW, i - 1, mu_group_id); + } + len += scnprintf(buf + len, size - len, + "\nLast Packet RU index [%d], Size [%d]\n", + arsta->tx_stats->ru_start, arsta->tx_stats->ru_tones); + + len += scnprintf(buf + len, size - len, + "\nTX duration\n %llu usecs\n", + arsta->tx_stats->tx_duration); + len += scnprintf(buf + len, size - len, + "BA fails\n %llu\n", arsta->tx_stats->ba_fails); + len += scnprintf(buf + len, size - len, + "ack fails\n %llu\n\n", arsta->tx_stats->ack_fails); + + len += scnprintf(buf + len, size - len, "WBM tx completion stats of data pkts :\n"); + for (idx = 0; idx <= HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY; idx++) { + len += scnprintf(buf + len, size - len, + "%-23s : %llu\n", + fields[idx], + arsta->wbm_tx_stats->wbm_tx_comp_stats[idx]); + } + + spin_unlock_bh(&ar->data_lock); + + if (len > size) + len = size; + retval = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + return retval; +} + +static const struct file_operations fops_tx_stats = { + .read = ath12k_dbg_sta_dump_tx_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_dump_rx_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + struct ath12k_rx_peer_stats *rx_stats; + int len = 0, i, retval = 0; + const int size = 4 * 4096; + char *buf; + int mcs = 0, bw = 0, nss = 0, gi = 0, bw_num = 0, num_run, found; + static const char *legacy_rate_str[HAL_RX_MAX_NUM_LEGACY_RATES] = { + "1Mbps", "2Mbps", "5.5Mbps", "6Mbps", + "9Mbps", "11Mbps", "12Mbps", "18Mbps", + "24Mbps", "36 Mbps", "48Mbps", "54Mbps"}; + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + rx_stats = arsta->rx_stats; + + if (!rx_stats) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + spin_lock_bh(&ar->ab->base_lock); + + len += scnprintf(buf + len, size - len, "RX peer stats:\n"); + len += scnprintf(buf + len, size - len, "Num of MSDUs: %llu\n", + rx_stats->num_msdu); + len += scnprintf(buf + len, size - len, "Num of MSDUs with TCP L4: %llu\n", + rx_stats->tcp_msdu_count); + len += scnprintf(buf + len, size - len, "Num of MSDUs with UDP L4: %llu\n", + rx_stats->udp_msdu_count); + len += scnprintf(buf + len, size - len, "Num of MSDUs part of AMPDU: %llu\n", + rx_stats->ampdu_msdu_count); + len += scnprintf(buf + len, size - len, "Num of MSDUs not part of AMPDU: %llu\n", + rx_stats->non_ampdu_msdu_count); + len += scnprintf(buf + len, size - len, "Num of MSDUs using STBC: %llu\n", + rx_stats->stbc_count); + len += scnprintf(buf + len, size - len, "Num of MSDUs beamformed: %llu\n", + rx_stats->beamformed_count); + len += scnprintf(buf + len, size - len, "Num of MPDUs with FCS ok: %llu\n", + rx_stats->num_mpdu_fcs_ok); + len += scnprintf(buf + len, size - len, "Num of MPDUs with FCS error: %llu\n", + rx_stats->num_mpdu_fcs_err); + len += scnprintf(buf + len, size - len, + "preamble: 11A %llu 11B %llu 11N %llu 11AC %llu 11AX %llu 11BE%llu\n", + rx_stats->pream_cnt[0], rx_stats->pream_cnt[1], + rx_stats->pream_cnt[2], rx_stats->pream_cnt[3], + rx_stats->pream_cnt[4], rx_stats->pream_cnt[6]); + len += scnprintf(buf + len, size - len, + "reception type: SU %llu MU_MIMO %llu MU_OFDMA %llu MU_OFDMA_MIMO %llu\n", + rx_stats->reception_type[0], rx_stats->reception_type[1], + rx_stats->reception_type[2], rx_stats->reception_type[3]); + len += scnprintf(buf + len, size - len, "TID(0-15) Legacy TID(16):"); + for (i = 0; i <= IEEE80211_NUM_TIDS; i++) + len += scnprintf(buf + len, size - len, "%llu ", rx_stats->tid_count[i]); + len += scnprintf(buf + len, size - len, "\nRX Duration:%llu\n", + rx_stats->rx_duration); + + len += scnprintf(buf + len, size - len, "\nRX success packet stats:\n"); + len += scnprintf(buf + len, size - len, "\nEHT packet stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_BE; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->pkt_stats.be_mcs_count[i], + (i + 1) % 7 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nHE packet stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_HE; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->pkt_stats.he_mcs_count[i], + (i + 1) % 6 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nVHT packet stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_VHT; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->pkt_stats.vht_mcs_count[i], + (i + 1) % 5 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nHT packet stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_HT; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->pkt_stats.ht_mcs_count[i], + (i + 1) % 8 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nLegacy rate packet stats:\n"); + for (i = 0; i < HAL_RX_MAX_NUM_LEGACY_RATES; i++) + len += scnprintf(buf + len, size - len, "%s: %llu%s", legacy_rate_str[i], + rx_stats->pkt_stats.legacy_count[i], + (i + 1) % 4 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nNSS packet stats:\n"); + for (i = 0; i < HAL_RX_MAX_NSS; i++) + len += scnprintf(buf + len, size - len, "%dx%d: %llu ", i + 1, i + 1, + rx_stats->pkt_stats.nss_count[i]); + len += scnprintf(buf + len, size - len, + "\n\nGI: 0.8us %llu 0.4us %llu 1.6us %llu 3.2us %llu\n", + rx_stats->pkt_stats.gi_count[0], + rx_stats->pkt_stats.gi_count[1], + rx_stats->pkt_stats.gi_count[2], + rx_stats->pkt_stats.gi_count[3]); + len += scnprintf(buf + len, size - len, + "BW: 20Mhz %llu 40Mhz %llu 80Mhz %llu 160Mhz %llu 320Mhz %llu\n", + rx_stats->pkt_stats.bw_count[0], + rx_stats->pkt_stats.bw_count[1], + rx_stats->pkt_stats.bw_count[2], + rx_stats->pkt_stats.bw_count[3], + rx_stats->pkt_stats.bw_count[4]); + len += scnprintf(buf + len, size - len, "\nRate Table (packets):\n"); + num_run = HAL_RX_BW_MAX * HAL_RX_GI_MAX * HAL_RX_MAX_NSS; + + for (i = 0; i < num_run; i++) { + found = 0; + for (mcs = 0; mcs < (HAL_RX_MAX_MCS_HT + 1); mcs++) + if (rx_stats->pkt_stats.rx_rate[bw][gi][nss][mcs]) { + found = 1; + break; + } + + if (found) { + switch (bw) { + case 0: + bw_num = 20; + break; + case 1: + bw_num = 40; + break; + case 2: + bw_num = 80; + break; + case 3: + bw_num = 160; + break; + case 4: + bw_num = 320; + break; + } + len += scnprintf(buf + len, size - len, "\n%d Mhz gi %d us %dx%d : ", + bw_num, gi, nss + 1, nss + 1); + for (mcs = 0; mcs < (HAL_RX_MAX_MCS_HT + 1); mcs++) { + if (rx_stats->pkt_stats.rx_rate[bw][gi][nss][mcs]) + len += scnprintf(buf + len, size - len, " %d:%llu", + mcs, rx_stats->pkt_stats.rx_rate[bw][gi][nss][mcs]); + } + } + if (nss++ >= HAL_RX_MAX_NSS - 1) { + nss = 0; + if (gi++ >= HAL_RX_GI_MAX - 1) { + gi = 0; + if (bw < HAL_RX_BW_MAX - 1) + bw++; + } + } + } + + len += scnprintf(buf + len, size - len, "\nRX success byte stats:\n"); + len += scnprintf(buf + len, size - len, "\nEHT byte stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_BE; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->byte_stats.be_mcs_count[i], + (i + 1) % 7 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nHE byte stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_HE; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->byte_stats.he_mcs_count[i], + (i + 1) % 6 ? "\t" : "\n"); + + len += scnprintf(buf + len, size - len, "\nVHT byte stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_VHT; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->byte_stats.vht_mcs_count[i], + (i + 1) % 5 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nHT byte stats:\n"); + for (i = 0; i <= HAL_RX_MAX_MCS_HT; i++) + len += scnprintf(buf + len, size - len, "MCS %d: %llu%s", i, + rx_stats->byte_stats.ht_mcs_count[i], + (i + 1) % 8 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nLegacy rate byte stats:\n"); + for (i = 0; i < HAL_RX_MAX_NUM_LEGACY_RATES; i++) + len += scnprintf(buf + len, size - len, "%s: %llu%s", legacy_rate_str[i], + rx_stats->byte_stats.legacy_count[i], + (i + 1) % 4 ? "\t" : "\n"); + len += scnprintf(buf + len, size - len, "\nNSS byte stats:\n"); + for (i = 0; i < HAL_RX_MAX_NSS; i++) + len += scnprintf(buf + len, size - len, "%dx%d: %llu ", i + 1, i + 1, + rx_stats->byte_stats.nss_count[i]); + len += scnprintf(buf + len, size - len, + "\n\nGI: 0.8us %llu 0.4us %llu 1.6us %llu 3.2us %llu\n", + rx_stats->byte_stats.gi_count[0], + rx_stats->byte_stats.gi_count[1], + rx_stats->byte_stats.gi_count[2], + rx_stats->byte_stats.gi_count[3]); + len += scnprintf(buf + len, size - len, + "BW: 20Mhz %llu 40Mhz %llu 80Mhz %llu 160Mhz %llu 320Mhz %llu\n", + rx_stats->byte_stats.bw_count[0], + rx_stats->byte_stats.bw_count[1], + rx_stats->byte_stats.bw_count[2], + rx_stats->byte_stats.bw_count[3], + rx_stats->byte_stats.bw_count[4]); + len += scnprintf(buf + len, size - len, "\nRate Table (bytes):\n"); + + + bw = 0; + gi = 0; + nss = 0; + for (i = 0; i < num_run; i++) { + found = 0; + for (mcs = 0; mcs < (HAL_RX_MAX_MCS_HT + 1); mcs++) + if (rx_stats->byte_stats.rx_rate[bw][gi][nss][mcs]) { + found = 1; + break; + } + + if (found) { + switch (bw) { + case 0: + bw_num = 20; + break; + case 1: + bw_num = 40; + break; + case 2: + bw_num = 80; + break; + case 3: + bw_num = 160; + break; + case 4: + bw_num = 320; + break; + } + len += scnprintf(buf + len, size - len, "\n%d Mhz gi %d us %dx%d : ", + bw_num, gi, nss + 1, nss + 1); + for (mcs = 0; mcs < (HAL_RX_MAX_MCS_HT + 1); mcs++) { + if (rx_stats->byte_stats.rx_rate[bw][gi][nss][mcs]) + len += scnprintf(buf + len, size - len, " %d:%llu", mcs, rx_stats->byte_stats.rx_rate[bw][gi][nss][mcs]); + } + } + + if (nss++ >= HAL_RX_MAX_NSS - 1) { + nss = 0; + if (gi++ >= HAL_RX_GI_MAX - 1) { + gi = 0; + if (bw < HAL_RX_BW_MAX - 1) + bw++; + } + } + } + len += scnprintf(buf + len, size - len, "\n"); + len += scnprintf(buf + len, size - len, + "\nDCM: %llu\nRU26: %llu\nRU52: %llu\nRU106: %llu\nRU242: %llu\nRU484: %llu\nRU996: %llu\n", + rx_stats->dcm_count, rx_stats->ru_alloc_cnt[0], + rx_stats->ru_alloc_cnt[1], rx_stats->ru_alloc_cnt[2], + rx_stats->ru_alloc_cnt[3], rx_stats->ru_alloc_cnt[4], + rx_stats->ru_alloc_cnt[5]); + + len += scnprintf(buf + len, size - len, "\n"); + + spin_unlock_bh(&ar->ab->base_lock); + + if (len > size) + len = size; + retval = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + return retval; +} + +static const struct file_operations fops_rx_stats = { + .read = ath12k_dbg_sta_dump_rx_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static int +ath12k_dbg_sta_open_htt_peer_stats(struct inode *inode, struct file *file) +{ + struct ieee80211_link_sta *link_sta = inode->i_private; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + struct debug_htt_stats_req *stats_req; + int type; + int ret; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + type = ar->debug.htt_stats.type; + if ((type != ATH12K_DBG_HTT_EXT_STATS_PEER_INFO && + type != ATH12K_DBG_HTT_EXT_PEER_CTRL_PATH_TXRX_STATS) || + type == ATH12K_DBG_HTT_EXT_STATS_RESET) { + mutex_unlock(&ah->conf_mutex); + return -EPERM; + } + + stats_req = vzalloc(sizeof(*stats_req) + ATH12K_HTT_STATS_BUF_SIZE); + if (!stats_req) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + ar->debug.htt_stats.stats_req = stats_req; + stats_req->type = ATH12K_DBG_HTT_EXT_STATS_PEER_INFO; + memcpy(stats_req->peer_addr, link_sta->addr, ETH_ALEN); + ret = ath12k_debugfs_htt_stats_req(ar); + mutex_unlock(&ar->conf_mutex); + if (ret < 0) + goto out; + + file->private_data = stats_req; + mutex_unlock(&ah->conf_mutex); + return 0; +out: + vfree(stats_req); + ar->debug.htt_stats.stats_req = NULL; + mutex_unlock(&ah->conf_mutex); + return ret; +} + +static int +ath12k_dbg_sta_release_htt_peer_stats(struct inode *inode, struct file *file) +{ + struct ieee80211_link_sta *link_sta = inode->i_private; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + mutex_lock(&ar->conf_mutex); + vfree(file->private_data); + ar->debug.htt_stats.stats_req = NULL; + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + + return 0; +} + +static ssize_t ath12k_dbg_sta_read_htt_peer_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct debug_htt_stats_req *stats_req = file->private_data; + char *buf; + u32 length = 0; + + buf = stats_req->buf; + length = min_t(u32, stats_req->buf_len, ATH12K_HTT_STATS_BUF_SIZE); + return simple_read_from_buffer(user_buf, count, ppos, buf, length); +} + +static const struct file_operations fops_htt_peer_stats = { + .open = ath12k_dbg_sta_open_htt_peer_stats, + .release = ath12k_dbg_sta_release_htt_peer_stats, + .read = ath12k_dbg_sta_read_htt_peer_stats, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_write_peer_pktlog(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + int ret, enable; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto out; + } + + ret = kstrtoint_from_user(buf, count, 0, &enable); + if (ret) + goto out; + + ar->debug.pktlog_peer_valid = enable; + memcpy(ar->debug.pktlog_peer_addr, link_sta->addr, ETH_ALEN); + + /* Send peer based pktlog enable/disable */ + ret = ath12k_wmi_pdev_peer_pktlog_filter(ar, link_sta->addr, enable); + if (ret) { + ath12k_warn(ar->ab, "failed to set peer pktlog filter %pM: %d\n", + sta->addr, ret); + goto out; + } + + ath12k_dbg(ar->ab, ATH12K_DBG_WMI, "peer pktlog filter set to %d\n", + enable); + ret = count; + +out: + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + return ret; +} + +static ssize_t ath12k_dbg_sta_read_peer_pktlog(struct file *file, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + char buf[32] = {0}; + int len; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf), "%08x %pM\n", + ar->debug.pktlog_peer_valid, + ar->debug.pktlog_peer_addr); + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + + return simple_read_from_buffer(ubuf, count, ppos, buf, len); +} + +static const struct file_operations fops_peer_pktlog = { + .write = ath12k_dbg_sta_write_peer_pktlog, + .read = ath12k_dbg_sta_read_peer_pktlog, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_write_delba(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_sta *sta = file->private_data; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta = &ahsta->deflink; + struct ath12k *ar = arsta->arvif->ar; + u32 tid, initiator, reason; + int ret; + char buf[64] = {0}; + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, + user_buf, count); + if (ret <= 0) + return ret; + + ret = sscanf(buf, "%u %u %u", &tid, &initiator, &reason); + if (ret != 3) + return -EINVAL; + + /* Valid TID values are 0 through 15 */ + if (tid > HAL_DESC_REO_NON_QOS_TID - 1) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON || + ahsta->aggr_mode != ATH12K_DBG_AGGR_MODE_MANUAL) { + ret = count; + goto out; + } + + ret = ath12k_wmi_delba_send(ar, arsta->arvif->vdev_id, sta->addr, + tid, initiator, reason); + if (ret) { + ath12k_warn(ar->ab, "failed to send delba: vdev_id %u peer %pM tid %u initiator %u reason %u\n", + arsta->arvif->vdev_id, sta->addr, tid, initiator, + reason); + } + ret = count; +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_delba = { + .write = ath12k_dbg_sta_write_delba, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_write_addba_resp(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_sta *sta = file->private_data; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta = &ahsta->deflink; + struct ath12k *ar = arsta->arvif->ar; + u32 tid, status; + int ret; + char buf[64] = {0}; + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, + user_buf, count); + if (ret <= 0) + return ret; + + ret = sscanf(buf, "%u %u", &tid, &status); + if (ret != 2) + return -EINVAL; + + /* Valid TID values are 0 through 15 */ + if (tid > HAL_DESC_REO_NON_QOS_TID - 1) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON || + ahsta->aggr_mode != ATH12K_DBG_AGGR_MODE_MANUAL) { + ret = count; + goto out; + } + + ret = ath12k_wmi_addba_set_resp(ar, arsta->arvif->vdev_id, sta->addr, + tid, status); + if (ret) { + ath12k_warn(ar->ab, "failed to send addba response: vdev_id %u peer %pM tid %u status%u\n", + arsta->arvif->vdev_id, sta->addr, tid, status); + } + ret = count; +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_addba_resp = { + .write = ath12k_dbg_sta_write_addba_resp, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_write_addba(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_sta *sta = file->private_data; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta = &ahsta->deflink; + struct ath12k *ar = arsta->arvif->ar; + u32 tid, buf_size; + int ret; + char buf[64] = {0}; + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, + user_buf, count); + if (ret <= 0) + return ret; + + ret = sscanf(buf, "%u %u", &tid, &buf_size); + if (ret != 2) + return -EINVAL; + + /* Valid TID values are 0 through 15 */ + if (tid > HAL_DESC_REO_NON_QOS_TID - 1) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON || + ahsta->aggr_mode != ATH12K_DBG_AGGR_MODE_MANUAL) { + ret = count; + goto out; + } + + ret = ath12k_wmi_addba_send(ar, arsta->arvif->vdev_id, sta->addr, + tid, buf_size); + if (ret) { + ath12k_warn(ar->ab, "failed to send addba request: vdev_id %u peer %pM tid %u buf_size %u\n", + arsta->arvif->vdev_id, sta->addr, tid, buf_size); + } + + ret = count; +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_addba = { + .write = ath12k_dbg_sta_write_addba, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_read_aggr_mode(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_sta *sta = file->private_data; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta = &ahsta->deflink; + struct ath12k *ar = arsta->arvif->ar; + char buf[64]; + int len = 0; + + mutex_lock(&ar->conf_mutex); + len = scnprintf(buf, sizeof(buf) - len, + "aggregation mode: %s\n\n%s\n%s\n", + (ahsta->aggr_mode == ATH12K_DBG_AGGR_MODE_AUTO) ? + "auto" : "manual", "auto = 0", "manual = 1"); + mutex_unlock(&ar->conf_mutex); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t ath12k_dbg_sta_write_aggr_mode(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_sta *sta = file->private_data; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_link_sta *arsta = &ahsta->deflink; + struct ath12k *ar = arsta->arvif->ar; + u32 aggr_mode; + int ret; + + if (kstrtouint_from_user(user_buf, count, 0, &aggr_mode)) + return -EINVAL; + + if (aggr_mode >= ATH12K_DBG_AGGR_MODE_MAX) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + if (ar->state != ATH12K_STATE_ON || + aggr_mode == ahsta->aggr_mode) { + ret = count; + goto out; + } + + ret = ath12k_wmi_addba_clear_resp(ar, arsta->arvif->vdev_id, sta->addr); + if (ret) { + ath12k_warn(ar->ab, "failed to clear addba session ret: %d\n", + ret); + goto out; + } + + ahsta->aggr_mode = aggr_mode; +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct file_operations fops_aggr_mode = { + .read = ath12k_dbg_sta_read_aggr_mode, + .write = ath12k_dbg_sta_write_aggr_mode, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t +ath12k_write_htt_peer_stats_reset(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + struct htt_ext_stats_cfg_params cfg_params = { 0 }; + int ret; + u8 type; + + ret = kstrtou8_from_user(user_buf, count, 0, &type); + if (ret) + return ret; + + if (!type) + return ret; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + mutex_lock(&ar->conf_mutex); + cfg_params.cfg0 = HTT_STAT_PEER_INFO_MAC_ADDR; + cfg_params.cfg0 |= FIELD_PREP(GENMASK(15, 1), + HTT_PEER_STATS_REQ_MODE_FLUSH_TQM); + + cfg_params.cfg1 = HTT_STAT_DEFAULT_PEER_REQ_TYPE; + + cfg_params.cfg2 |= FIELD_PREP(GENMASK(7, 0), link_sta->addr[0]); + cfg_params.cfg2 |= FIELD_PREP(GENMASK(15, 8), link_sta->addr[1]); + cfg_params.cfg2 |= FIELD_PREP(GENMASK(23, 16), link_sta->addr[2]); + cfg_params.cfg2 |= FIELD_PREP(GENMASK(31, 24), link_sta->addr[3]); + + cfg_params.cfg3 |= FIELD_PREP(GENMASK(7, 0), link_sta->addr[4]); + cfg_params.cfg3 |= FIELD_PREP(GENMASK(15, 8), link_sta->addr[5]); + + cfg_params.cfg3 |= ATH12K_HTT_PEER_STATS_RESET; + + ret = ath12k_dp_tx_htt_h2t_ext_stats_req(ar, + ATH12K_DBG_HTT_EXT_STATS_PEER_INFO, + &cfg_params, + 0ULL); + if (ret) { + ath12k_warn(ar->ab, "failed to send htt peer stats request: %d\n", ret); + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + return ret; + } + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + + ret = count; + + return ret; +} + +static const struct file_operations fops_htt_peer_stats_reset = { + .write = ath12k_write_htt_peer_stats_reset, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t +ath12k_dbg_sta_dump_driver_tx_pkts_flow(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + int len = 0, ret_val; + const int size = ATH12K_DRV_TX_STATS_SIZE; + char *buf; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + if (!arsta->tx_stats) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + buf = kzalloc(ATH12K_DRV_TX_STATS_SIZE, GFP_KERNEL); + if (!buf) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + spin_lock_bh(&ar->ab->base_lock); + len += scnprintf(buf + len, size - len, + "Tx packets inflow from mac80211: %u\n", + atomic_read(&arsta->drv_tx_pkts.pkts_in)); + len += scnprintf(buf + len, size - len, + "Tx packets outflow to HW: %u\n", + atomic_read(&arsta->drv_tx_pkts.pkts_out)); + spin_unlock_bh(&ar->ab->base_lock); + + if (len > size) + len = size; + + ret_val = simple_read_from_buffer((char *)user_buf, count, ppos, buf, len); + kfree(buf); + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + return ret_val; +} + +static const struct file_operations fops_driver_tx_pkts_flow = { + .read = ath12k_dbg_sta_dump_driver_tx_pkts_flow, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_reset_tx_stats(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + int ret, reset; + + ret = kstrtoint_from_user(buf, count, 0, &reset); + if (ret) + return ret; + + if (!reset || reset > 1) + return -EINVAL; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + if (!arsta->tx_stats || !arsta->wbm_tx_stats) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + spin_lock_bh(&ar->ab->base_lock); + memset(arsta->tx_stats, 0, sizeof(*arsta->tx_stats)); + atomic_set(&arsta->drv_tx_pkts.pkts_in, 0); + atomic_set(&arsta->drv_tx_pkts.pkts_out, 0); + memset(arsta->wbm_tx_stats->wbm_tx_comp_stats, 0, sizeof(*arsta->wbm_tx_stats)); + spin_unlock_bh(&ar->ab->base_lock); + + mutex_unlock(&ah->conf_mutex); + + ret = count; + return ret; +} + +static const struct file_operations fops_reset_tx_stats = { + .write = ath12k_dbg_sta_reset_tx_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t +ath12k_dbg_sta_dump_driver_rx_pkts_flow(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + struct ath12k_rx_peer_stats *rx_stats; + int len = 0, ret_val = 0; + const int size = 1024; + char *buf; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + rx_stats = arsta->rx_stats; + if (!rx_stats) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + buf = kzalloc(size, GFP_KERNEL); + if (!buf) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + spin_lock_bh(&ar->ab->base_lock); + + len += scnprintf(buf + len, size - len, + "Rx packets inflow from HW: %u\n", + atomic_read(&arsta->drv_rx_pkts.pkts_frm_hw)); + len += scnprintf(buf + len, size - len, + "Rx packets outflow from driver: %u\n", + atomic_read(&arsta->drv_rx_pkts.pkts_out)); + + len += scnprintf(buf + len, size - len, "\n"); + + spin_unlock_bh(&ar->ab->base_lock); + + if (len > size) + len = size; + + ret_val = simple_read_from_buffer(user_buf, count, ppos, buf, len); + kfree(buf); + + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + return ret_val; +} + +static const struct file_operations fops_driver_rx_pkts_flow = { + .read = ath12k_dbg_sta_dump_driver_rx_pkts_flow, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_reset_rx_stats(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + u8 link_id = link_sta->link_id; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + int ret, reset; + + ret = kstrtoint_from_user(buf, count, 0, &reset); + if (ret) + return ret; + + if (!reset || reset > 1) + return -EINVAL; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + if (!arsta->rx_stats) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + spin_lock_bh(&ar->ab->base_lock); + memset(arsta->rx_stats, 0, sizeof(*arsta->rx_stats)); + atomic_set(&arsta->drv_rx_pkts.pkts_frm_hw, 0); + atomic_set(&arsta->drv_rx_pkts.pkts_out, 0); + spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ah->conf_mutex); + + ret = count; + return ret; +} + +static const struct file_operations fops_reset_rx_stats = { + .write = ath12k_dbg_sta_reset_rx_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +#ifdef CONFIG_ATH12K_SAWF +static int ath12k_fill_sawf_tx_delay_stats(struct ath12k_base *ab, struct ath12k_peer *peer, + char *buf, int len, int size, + u8 q_id, u8 tid) +{ + struct ath12k_sawf_stats *sawf_stats; + struct sawf_tx_delay_stats *tx_delay_stats; + + lockdep_assert_held(&ab->base_lock); + + sawf_stats = &peer->sawf_stats; + if (!sawf_stats) + return 0; + + tx_delay_stats = &sawf_stats->tx_delay_stats[tid][q_id]; + + len += scnprintf(buf + len, size - len, "Delay Bins\n"); + len += scnprintf(buf + len, size - len, "Min %u\n", tx_delay_stats->delay_hist.min); + len += scnprintf(buf + len, size - len, "Max %u\n", tx_delay_stats->delay_hist.max); + len += scnprintf(buf + len, size - len, "Avg %u\n", tx_delay_stats->delay_hist.avg); + len += scnprintf(buf + len, size - len, "NWDelay moving avg %u\n", tx_delay_stats->nwdelay_avg); + len += scnprintf(buf + len, size - len, "SWDelay moving avg %u\n", tx_delay_stats->swdelay_avg); + len += scnprintf(buf + len, size - len, "HWDelay moving avg %u\n", tx_delay_stats->hwdelay_avg); + len += scnprintf(buf + len, size - len, "Delay Bound Success %llu\n", tx_delay_stats->success); + len += scnprintf(buf + len, size - len, "Delay Bound Failure %llu\n", tx_delay_stats->failure); + + return len; +} + +static ssize_t ath12k_dbg_sta_dump_sawf_tx_delay_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_sawf_peer_ctx *peer_ctx = NULL; + const int size = 2 * ATH12K_SAWF_STATS_SIZE; + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_sawf_ctx *sawf_ctx; + u8 q_id, tid, max_usr_def_q_sawf; + u8 link_id = link_sta->link_id; + struct ath12k_link_sta *arsta; + struct ath12k_peer *peer; + struct ath12k *ar; + int len = 0; + char *buf; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + buf = kzalloc(size, GFP_KERNEL); + if (!buf) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + spin_lock_bh(&ar->ab->base_lock); + + peer = ath12k_peer_find(ar->ab, arsta->arvif->vdev_id, arsta->addr); + if (!peer) { + ath12k_warn(ar->ab, "mac sta rc update failed to find peer %pM on vdev %i\n", + arsta->addr, arsta->arvif->vdev_id); + spin_unlock_bh(&ar->ab->base_lock); + len = -ENOENT; + goto unlock; + } + + peer_ctx = &peer->sawf_ctx_peer; + + sawf_ctx = ath12k_get_sawf_context(); + if (!sawf_ctx || !peer_ctx) { + spin_unlock_bh(&ar->ab->base_lock); + len = -EINVAL; + goto unlock; + } + + max_usr_def_q_sawf = sawf_ctx->max_msduq_per_tid - + sawf_ctx->default_msduq_per_tid; + + if (!arsta->sawf_svc_id) + goto dump_stats; + + for (tid = 0; tid < ATH12K_SAWF_MAX_TID_SUPPORT; tid++) { + for (q_id = 0; q_id < max_usr_def_q_sawf; q_id++) { + if (arsta->sawf_svc_id == peer_ctx->msduq_table[tid][q_id].svc_id) { + len = ath12k_fill_sawf_tx_delay_stats(ar->ab, peer, buf, len, size, q_id, tid); + goto exit; + } + } + } + +dump_stats: + for (tid = 0; tid < ATH12K_SAWF_MAX_TID_SUPPORT; tid++) { + for (q_id = 0; q_id < max_usr_def_q_sawf; q_id++) + len = ath12k_fill_sawf_tx_delay_stats(ar->ab, peer, buf, len, size, q_id, tid); + } + +exit: + spin_unlock_bh(&ar->ab->base_lock); + if (len > size) + len = size; + if (len) + len = simple_read_from_buffer(user_buf, count, ppos, buf, len); +unlock: + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + kfree(buf); + return len; +} + +static const struct file_operations fops_sawf_tx_delay_stats = { + .read = ath12k_dbg_sta_dump_sawf_tx_delay_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static int ath12k_fill_sawf_tx_stats(struct ath12k_base *ab, struct ath12k_peer *peer, + char *buf, int len, int size, + u8 q_id, u8 tid) +{ + struct sawf_fw_mpdu_stats *svc_intval_stats; + struct sawf_fw_mpdu_stats *burst_size_stats; + struct ath12k_sawf_stats *sawf_stats; + struct sawf_tx_stats *tx_stats; + + lockdep_assert_held(&ab->base_lock); + + sawf_stats = &peer->sawf_stats; + if (!sawf_stats) + return 0; + + tx_stats = &sawf_stats->tx_stats[tid][q_id]; + + svc_intval_stats = &sawf_stats->tx_stats[tid][q_id].svc_intval_stats; + + burst_size_stats = &sawf_stats->tx_stats[tid][q_id].burst_size_stats; + + len += scnprintf(buf + len, size - len, "tx_succ_pkts: %u\n", + tx_stats->tx_success.num_pkts); + len += scnprintf(buf + len, size - len, "tx_succ_bytes: %llu\n", + tx_stats->tx_success.bytes); + len += scnprintf(buf + len, size - len, "tx_ingress_pkts: %u\n", + tx_stats->tx_ingress.num_pkts); + len += scnprintf(buf + len, size - len, "tx_ingress_bytes: %llu\n", + tx_stats->tx_ingress.bytes); + len += scnprintf(buf + len, size - len, "tx_remove_mpdu_pkts: %u\n", + tx_stats->dropped.fw_rem.num_pkts); + len += scnprintf(buf + len, size - len, "tx_remove_mpdu_bytes: %llu\n", + tx_stats->dropped.fw_rem.bytes); + len += scnprintf(buf + len, size - len, "tx_remove_tx_pkts: %u\n", + tx_stats->dropped.fw_rem_tx); + len += scnprintf(buf + len, size - len, "tx_remove_notx_pkts: %u\n", + tx_stats->dropped.fw_rem_notx); + len += scnprintf(buf + len, size - len, "tx_remove_aged_pkts: %u\n", + tx_stats->dropped.age_out); + len += scnprintf(buf + len, size - len, "tx_remove_fw_reason1: %u\n", + tx_stats->dropped.fw_reason1); + len += scnprintf(buf + len, size - len, "tx_remove_fw_reason2: %u\n", + tx_stats->dropped.fw_reason2); + len += scnprintf(buf + len, size - len, "tx_remove_fw_reason3: %u\n", + tx_stats->dropped.fw_reason3); + len += scnprintf(buf + len, size - len, "tx_failed: %u\n", + tx_stats->tx_failed); + len += scnprintf(buf + len, size - len, "queue_depth: %u\n", + tx_stats->queue_depth); + + if (svc_intval_stats) { + len += scnprintf(buf + len, size - len, "Service intvl success_cnt : %llu\n", + svc_intval_stats->success_cnt); + len += scnprintf(buf + len, size - len, "Service intvl failure_cnt : %llu\n", + svc_intval_stats->failure_cnt); + } + + if (burst_size_stats) { + len += scnprintf(buf + len, size - len, "Burst Size success_cnt : %llu\n", + burst_size_stats->success_cnt); + len += scnprintf(buf + len, size - len, "Burst Size failure_cnt : %llu\n", + burst_size_stats->failure_cnt); + } + + return len; +} + +static ssize_t ath12k_dbg_sta_dump_sawf_tx_stats(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_sawf_peer_ctx *peer_ctx = NULL; + const int size = 2 * ATH12K_SAWF_STATS_SIZE; + struct ath12k_hw *ah = ahsta->ahvif->ah; + struct ath12k_sawf_ctx *sawf_ctx; + u8 q_id, tid, max_usr_def_q_sawf; + u8 link_id = link_sta->link_id; + struct ath12k_link_sta *arsta; + struct ath12k_peer *peer; + struct ath12k *ar; + int len = 0; + char *buf; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + buf = kzalloc(size, GFP_KERNEL); + if (!buf) { + mutex_unlock(&ah->conf_mutex); + return -ENOMEM; + } + + mutex_lock(&ar->conf_mutex); + spin_lock_bh(&ar->ab->base_lock); + + peer = ath12k_peer_find(ar->ab, arsta->arvif->vdev_id, arsta->addr); + if (!peer) { + ath12k_warn(ar->ab, "mac sta rc update failed to find peer %pM on vdev %i\n", + arsta->addr, arsta->arvif->vdev_id); + spin_unlock_bh(&ar->ab->base_lock); + len = -ENOENT; + goto unlock; + } + + peer_ctx = &peer->sawf_ctx_peer; + + sawf_ctx = ath12k_get_sawf_context(); + if (!sawf_ctx || !peer_ctx) { + spin_unlock_bh(&ar->ab->base_lock); + len = -EINVAL; + goto unlock; + } + + max_usr_def_q_sawf = sawf_ctx->max_msduq_per_tid - + sawf_ctx->default_msduq_per_tid; + + if (!arsta->sawf_svc_id) + goto dump_stats; + + for (tid = 0; tid < ATH12K_SAWF_MAX_TID_SUPPORT; tid++) { + for (q_id = 0; q_id < max_usr_def_q_sawf; q_id++) { + if (arsta->sawf_svc_id == peer_ctx->msduq_table[tid][q_id].svc_id) { + len = ath12k_fill_sawf_tx_stats(ar->ab, peer, buf, len, size, q_id, tid); + goto exit; + } + } + } + +dump_stats: + for (tid = 0; tid < ATH12K_SAWF_MAX_TID_SUPPORT; tid++) { + for (q_id = 0; q_id < max_usr_def_q_sawf; q_id++) + len = ath12k_fill_sawf_tx_stats(ar->ab, peer, buf, len, size, q_id, tid); + } + +exit: + spin_unlock_bh(&ar->ab->base_lock); + if (len > size) + len = size; + if (len) + len = simple_read_from_buffer(user_buf, count, ppos, buf, len); + +unlock: + mutex_unlock(&ar->conf_mutex); + mutex_unlock(&ah->conf_mutex); + kfree(buf); + return len; +} + +static const struct file_operations fops_sawf_tx_stats = { + .read = ath12k_dbg_sta_dump_sawf_tx_stats, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t ath12k_dbg_sta_set_svc_id(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + struct ieee80211_link_sta *link_sta = file->private_data; + struct ieee80211_sta *sta = link_sta->sta; + struct ath12k_sta *ahsta = ath12k_sta_to_ahsta(sta); + struct ath12k_hw *ah = ahsta->ahvif->ah; + u8 link_id = link_sta->link_id; + struct ath12k_link_sta *arsta; + struct ath12k *ar; + int ret, svc_id; + + ret = kstrtoint_from_user(buf, count, 0, &svc_id); + if (ret) + return ret; + + if (svc_id && (svc_id < ATH12K_SAWF_SVC_CLASS_MIN || + svc_id > ATH12K_SAWF_SVC_CLASS_MAX)) + return -EINVAL; + + mutex_lock(&ah->conf_mutex); + + if (!(BIT(link_id) & ahsta->links_map)) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + arsta = ahsta->link[link_id]; + + if (!arsta || !arsta->arvif->ar) { + mutex_unlock(&ah->conf_mutex); + return -ENOENT; + } + + ar = arsta->arvif->ar; + + spin_lock_bh(&ar->ab->base_lock); + arsta->sawf_svc_id = svc_id; + spin_unlock_bh(&ar->ab->base_lock); + mutex_unlock(&ah->conf_mutex); + + ret = count; + return ret; +} + +static const struct file_operations fops_svc_id = { + .write = ath12k_dbg_sta_set_svc_id, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; +#endif /* CONFIG_ATH12K_SAWF */ + +void ath12k_debugfs_sta_op_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_sta *sta, struct dentry *dir) +{ + debugfs_create_file("aggr_mode", 0644, dir, sta, &fops_aggr_mode); + debugfs_create_file("addba", 0200, dir, sta, &fops_addba); + debugfs_create_file("addba_resp", 0200, dir, sta, &fops_addba_resp); + debugfs_create_file("delba", 0200, dir, sta, &fops_delba); +} + +void ath12k_debugfs_link_sta_op_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_link_sta *link_sta, struct dentry *dir) +{ + u8 link_id = link_sta->link_id; + struct ath12k *ar; + struct ath12k_hw *ah = hw->priv; + + mutex_lock(&ah->conf_mutex); + + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + if (!ar) { + mutex_unlock(&ah->conf_mutex); + return; + } + + if (ath12k_debugfs_is_extd_tx_stats_enabled(ar)) { + debugfs_create_file("tx_stats", 0400, dir, link_sta, + &fops_tx_stats); + debugfs_create_file("reset_tx_stats", 0600, dir, link_sta, + &fops_reset_tx_stats); + debugfs_create_file("driver_tx_pkts_flow", 0400, dir, link_sta, + &fops_driver_tx_pkts_flow); + } + if (ath12k_debugfs_is_extd_rx_stats_enabled(ar)) { + debugfs_create_file("rx_stats", 0400, dir, link_sta, + &fops_rx_stats); + debugfs_create_file("reset_rx_stats", 0600, dir, link_sta, + &fops_reset_rx_stats); + debugfs_create_file("driver_rx_pkts_flow", 0400, dir, link_sta, + &fops_driver_rx_pkts_flow); + } + + debugfs_create_file("htt_peer_stats", 0400, dir, link_sta, + &fops_htt_peer_stats); + + debugfs_create_file("peer_pktlog", 0644, dir, link_sta, + &fops_peer_pktlog); + + if (test_bit(WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET, + ar->ab->wmi_ab.svc_map)) + debugfs_create_file("htt_peer_stats_reset", 0600, dir, link_sta, + &fops_htt_peer_stats_reset); + +#ifdef CONFIG_ATH12K_SAWF + if (ath12k_debugfs_is_sawf_stats_enabled(ar)) { + debugfs_create_file("svc_id", 0400, dir, link_sta, + &fops_svc_id); + debugfs_create_file("sawf_tx_stats", 0400, dir, link_sta, + &fops_sawf_tx_stats); + debugfs_create_file("sawf_tx_delay_stats", 0400, dir, link_sta, + &fops_sawf_tx_delay_stats); + } +#endif + mutex_unlock(&ah->conf_mutex); +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/debugfs_sta.h 2024-01-19 17:01:19.857846811 +0100 @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _ATH12K_DEBUGFS_STA_H_ +#define _ATH12K_DEBUGFS_STA_H_ + +#include + +#include "core.h" +#include "hal_tx.h" +#include "dp_rx.h" + +#ifdef CONFIG_ATH12K_DEBUGFS + +void ath12k_debugfs_sta_op_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_sta *sta, struct dentry *dir); +void ath12k_debugfs_link_sta_op_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + struct ieee80211_link_sta *link_sta, struct dentry *dir); +void ath12k_debugfs_sta_add_tx_stats(struct ath12k_link_sta *arsta, + struct ath12k_per_peer_tx_stats *peer_stats, + u8 legacy_rate_idx); +void ath12k_debugfs_sta_update_txcompl(struct ath12k *ar, + struct hal_tx_status *ts); + +#else /* CONFIG_ATH12K_DEBUGFS */ + +#define ath12k_debugfs_sta_op_add NULL +#define ath12k_debugfs_link_sta_op_add NULL + +static inline void +ath12k_debugfs_sta_add_tx_stats(struct ath12k_link_sta *arsta, + struct ath12k_per_peer_tx_stats *peer_stats, + u8 legacy_rate_idx) +{ +} + +static inline void ath12k_debugfs_sta_update_txcompl(struct ath12k *ar, + struct hal_tx_status *ts) +{ +} + +#endif /* CONFIG_ATH12K_DEBUGFS */ + +#endif /* _ATH12K_DEBUGFS_STA_H_ */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/pcic.c 2024-04-19 16:04:28.957735776 +0200 @@ -0,0 +1,1033 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include "core.h" +#include "pcic.h" +#include "debug.h" +#include "ppe.h" + +unsigned int tx_comp_budget = 0x7F; +module_param_named(tx_comp_budget, tx_comp_budget, uint, 0644); +MODULE_PARM_DESC(tx_comp_budget, "tx_comp_budget"); + +unsigned int ath12k_napi_poll_budget = 0x7f; +module_param_named(napi_budget, ath12k_napi_poll_budget, uint, 0644); +MODULE_PARM_DESC(napi_budget, "Napi budget processing per rx intr"); + +static const char *irq_name[ATH12K_IRQ_NUM_MAX] = { + "bhi", + "mhi-er0", + "mhi-er1", + "ce0", + "ce1", + "ce2", + "ce3", + "ce4", + "ce5", + "ce6", + "ce7", + "ce8", + "ce9", + "ce10", + "ce11", + "ce12", + "ce13", + "ce14", + "ce15", + "host2wbm-desc-feed", + "host2reo-re-injection", + "host2reo-command", + "host2rxdma-monitor-ring3", + "host2rxdma-monitor-ring2", + "host2rxdma-monitor-ring1", + "reo2ost-exception", + "wbm2host-rx-release", + "reo2host-status", + "reo2host-destination-ring4", + "reo2host-destination-ring3", + "reo2host-destination-ring2", + "reo2host-destination-ring1", + "rxdma2host-monitor-destination-mac3", + "rxdma2host-monitor-destination-mac2", + "rxdma2host-monitor-destination-mac1", + "ppdu-end-interrupts-mac3", + "ppdu-end-interrupts-mac2", + "ppdu-end-interrupts-mac1", + "rxdma2host-monitor-status-ring-mac3", + "rxdma2host-monitor-status-ring-mac2", + "rxdma2host-monitor-status-ring-mac1", + "host2rxdma-host-buf-ring-mac3", + "host2rxdma-host-buf-ring-mac2", + "host2rxdma-host-buf-ring-mac1", + "rxdma2host-destination-ring-mac3", + "rxdma2host-destination-ring-mac2", + "rxdma2host-destination-ring-mac1", + "host2tcl-input-ring4", + "host2tcl-input-ring3", + "host2tcl-input-ring2", + "host2tcl-input-ring1", + "wbm2host-tx-completions-ring4", + "wbm2host-tx-completions-ring3", + "wbm2host-tx-completions-ring2", + "wbm2host-tx-completions-ring1", + "tcl2host-status-ring", +}; + +char dp_irq_name[ATH12K_MAX_PCI_DOMAINS + 1][ATH12K_EXT_IRQ_DP_NUM_VECTORS][DP_IRQ_NAME_LEN] = {}; +char dp_pcic_irq_name[ATH12K_MAX_PCI_DOMAINS + 1][ATH12K_EXT_IRQ_DP_NUM_VECTORS][DP_IRQ_NAME_LEN] = {}; +char ce_irq_name[ATH12K_MAX_PCI_DOMAINS + 1][ATH12K_IRQ_NUM_MAX][DP_IRQ_NAME_LEN] = {}; + +void ath12k_pcic_config_static_window(struct ath12k_base *ab) +{ + u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK); + u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK); + u32 window; + + window = (umac_window << 12) | (ce_window << 6); + + iowrite32(WINDOW_ENABLE_BIT | window, ab->mem + WINDOW_REG_ADDRESS); +} + +static void ath12k_pcic_select_static_window(struct ath12k_base *ab, u32 addr) +{ + u32 curr_window, cur_val, prev_window = 0; + volatile u32 read_val = 0; + int retry = 0; + u32 window = u32_get_bits(addr, WINDOW_VALUE_MASK); + + prev_window = readl_relaxed(ab->mem + WINDOW_REG_ADDRESS); + + /* Clear out last 6 bits of window register */ + prev_window = prev_window & ~(0x3f); + + /* Write the new last 6 bits of window register. Only window 1 values + * are changed. Window 2 and 3 are unaffected. + */ + curr_window = prev_window | window; + + /* Skip writing into window register if the read value + * is same as calculated value. + */ + if (curr_window == prev_window) + return; + + cur_val = WINDOW_ENABLE_BIT | curr_window; + writel_relaxed(cur_val, ab->mem + WINDOW_REG_ADDRESS); + + read_val = readl_relaxed(ab->mem + WINDOW_REG_ADDRESS); + + /* If value written is not yet reflected, wait till it is reflected */ + while ((read_val != cur_val) && (retry < 10)) { + mdelay(1); + read_val = readl_relaxed(ab->mem + WINDOW_REG_ADDRESS); + retry++; + } + if (retry == 10) + ath12k_warn(ab, "Failed to set static window for cmem init\n"); +} + +u32 ath12k_pcic_cmem_read32(struct ath12k_base *ab, u32 addr) +{ + u32 val; + + if (addr < WINDOW_START) + return readl_relaxed(ab->mem + addr); + + ath12k_pcic_select_static_window(ab, addr); + + val = readl_relaxed(ab->mem + WINDOW_START + (addr & WINDOW_RANGE_MASK)); + + return val; +} + +void ath12k_pcic_cmem_write32(struct ath12k_base *ab, u32 addr, u32 value) +{ + if (addr < WINDOW_START) { + writel_relaxed(value, ab->mem + addr); + return; + } + + ath12k_pcic_select_static_window(ab, addr); + + writel_relaxed(value, ab->mem + WINDOW_START + (addr & WINDOW_RANGE_MASK)); +} + +u32 ath12k_pcic_get_window_start(struct ath12k_base *ab, u32 offset) +{ + u32 window_start; + + /* If offset lies within DP register range, use 3rd window */ + if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) + window_start = 3 * WINDOW_START; + /* If offset lies within CE register range, use 2nd window */ + else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) + window_start = 2 * WINDOW_START; + else + window_start = WINDOW_START; + + return window_start; +} + +static void ath12k_pcic_free_ext_irq(struct ath12k_base *ab) +{ + int i, j; + + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { + struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + for (j = 0; j < irq_grp->num_irq; j++) + free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); + + netif_napi_del(&irq_grp->napi); + } +} + +void ath12k_pcic_free_irq(struct ath12k_base *ab) +{ + int i, irq_idx; + + for (i = 0; i < ab->hw_params->ce_count; i++) { + if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) + continue; + irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; + free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); + } + + ath12k_pcic_free_ext_irq(ab); +} + +void ath12k_pcic_free_hybrid_irq(struct ath12k_base *ab) +{ + struct platform_device *pdev = ab->pdev; + + ath12k_pcic_free_irq(ab); + platform_msi_domain_free_irqs(&pdev->dev); +} + +static void ath12k_pcic_ce_irq_enable(struct ath12k_base *ab, u16 ce_id) +{ + u32 irq_idx; + + irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; + enable_irq(ab->irq_num[irq_idx]); +} + +static void ath12k_pcic_ce_irq_disable(struct ath12k_base *ab, u16 ce_id) +{ + u32 irq_idx; + + irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; + disable_irq_nosync(ab->irq_num[irq_idx]); +} + +static void ath12k_pcic_ce_irqs_disable(struct ath12k_base *ab) +{ + int i; + + for (i = 0; i < ab->hw_params->ce_count; i++) { + if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) + continue; + ath12k_pcic_ce_irq_disable(ab, i); + } +} + +static void ath12k_pcic_ce_tasklet(struct tasklet_struct *t) +{ + struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); + + ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); + + ath12k_pcic_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); +} + +static irqreturn_t ath12k_pcic_ce_interrupt_handler(int irq, void *arg) +{ + struct ath12k_ce_pipe *ce_pipe = arg; + struct ath12k_base *ab = ce_pipe->ab; + + if (unlikely(!ab->ce_pipe_init_done)) + return IRQ_HANDLED; + + /* last interrupt received for this CE */ + ce_pipe->timestamp = jiffies; + + ath12k_pcic_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); + tasklet_schedule(&ce_pipe->intr_tq); + + return IRQ_HANDLED; +} + +static void ath12k_pcic_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp) +{ + int i; + + for (i = 0; i < irq_grp->num_irq; i++) + disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); +} + +static void __ath12k_pcic_ext_irq_disable(struct ath12k_base *sc) +{ + int i; + + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(sc); i++) { + struct ath12k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; + + ath12k_pcic_ext_grp_disable(irq_grp); + + napi_synchronize(&irq_grp->napi); + napi_disable(&irq_grp->napi); + } +} + +static void ath12k_pcic_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp) +{ + int i; + + for (i = 0; i < irq_grp->num_irq; i++) + enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); +} + +static void ath12k_pcic_sync_ext_irqs(struct ath12k_base *ab) +{ + int i, j, irq_idx; + + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { + struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + for (j = 0; j < irq_grp->num_irq; j++) { + irq_idx = irq_grp->irqs[j]; + synchronize_irq(ab->irq_num[irq_idx]); + } + } +} + +static int ath12k_pcic_ext_grp_napi_poll(struct napi_struct *napi, int budget) +{ + struct ath12k_ext_irq_grp *irq_grp = container_of(napi, + struct ath12k_ext_irq_grp, + napi); + struct ath12k_base *ab = irq_grp->ab; + int work_done; + + work_done = ath12k_dp_service_srng(ab, irq_grp, budget); + if (work_done < budget) { + if(likely(napi_complete_done(napi, work_done))) + ath12k_pcic_ext_grp_enable(irq_grp); + } + + if (work_done > budget) + work_done = budget; + + return work_done; +} + +static irqreturn_t ath12k_pcic_ext_interrupt_handler(int irq, void *arg) +{ + struct ath12k_ext_irq_grp *irq_grp = arg; + + ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); + + /* last interrupt received for this group */ + irq_grp->timestamp = jiffies; + + ath12k_pcic_ext_grp_disable(irq_grp); + + napi_schedule(&irq_grp->napi); + + return IRQ_HANDLED; +} + +void ath12k_pcic_ce_irqs_enable(struct ath12k_base *ab) +{ + int i; + + for (i = 0; i < ab->hw_params->ce_count; i++) { + if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) + continue; + ath12k_pcic_ce_irq_enable(ab, i); + } +} + +static int ath12k_pcic_ext_config_gic_msi_irq(struct ath12k_base *ab, + struct platform_device *pdev, + struct msi_desc *msi_desc, int i) +{ + u32 user_base_data = 0, base_vector = 0, base_idx; + struct ath12k_ext_irq_grp *irq_grp; + int j, budget, ret = 0, num_vectors = 0; + u8 userpd_id; + u32 num_irq = 0; + + userpd_id = ab->userpd_id; + base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; + ret = ath12k_pcic_get_user_msi_assignment(ab, "DP", &num_vectors, + &user_base_data, &base_vector); + if (ret < 0) + return ret; + + irq_grp = &ab->ext_irq_grp[i]; + irq_grp->ab = ab; + irq_grp->grp_id = i; + init_dummy_netdev(&irq_grp->napi_ndev); + + if (ab->hw_params->ring_mask->rx_mon_dest[i]) + budget = NAPI_POLL_WEIGHT; + else + budget = ath12k_napi_poll_budget; + + /* Apply a reduced budget for tx completion to prioritize tx enqueue operation */ + if (ab->hw_params->ring_mask->tx[i]) + budget = tx_comp_budget; + + if (ab->hw_params->ring_mask->tx[i] || + ab->hw_params->ring_mask->rx[i] || + ab->hw_params->ring_mask->rx_err[i] || + ab->hw_params->ring_mask->rx_wbm_rel[i] || + ab->hw_params->ring_mask->reo_status[i] || + ab->hw_params->ring_mask->host2rxdma[i] || + ab->hw_params->ring_mask->ppe2tcl[i] || +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ab->hw_params->ring_mask->wbm2sw6_ppeds_tx_cmpln[i] || +#endif + ab->hw_params->ring_mask->reo2ppe[i] || + ab->hw_params->ring_mask->rx_mon_dest[i]) { + num_irq = 1; + } + + irq_grp->num_irq = num_irq; + irq_grp->irqs[0] = base_idx + i; + + for (j = 0; j < irq_grp->num_irq; j++) { + int irq_idx = irq_grp->irqs[j]; + int vector = (i % num_vectors); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (ab->hw_params->ring_mask->ppe2tcl[i] || + ab->hw_params->ring_mask->wbm2sw6_ppeds_tx_cmpln[i] || + ab->hw_params->ring_mask->reo2ppe[i]) { + ret = ath12k_pcic_get_msi_data(ab, msi_desc, i); + if (ret) { + ath12k_err(ab, "failed to get msi data for irq %d: %d", + msi_desc->irq, ret); + return ret; + } + } else { +#endif + netif_napi_add_weight(&irq_grp->napi_ndev, &irq_grp->napi, + ath12k_pcic_ext_grp_napi_poll, budget); + + scnprintf(dp_pcic_irq_name[userpd_id][i], DP_IRQ_NAME_LEN, + "pcic%u_wlan_dp_%u", userpd_id, i); + irq_set_status_flags(msi_desc->irq, IRQ_DISABLE_UNLAZY); + ret = devm_request_irq(&pdev->dev, msi_desc->irq, + ath12k_pcic_ext_interrupt_handler, IRQF_SHARED, + dp_pcic_irq_name[userpd_id][i], irq_grp); + if (ret) { + ath12k_err(ab, "failed request irq %d: %d\n", irq_idx, ret); + return ret; + } + ab->irq_num[irq_idx] = msi_desc->irq; + ab->ipci.dp_irq_num[vector] = msi_desc->irq; + ab->ipci.dp_msi_data[i] = msi_desc->msg.data; + disable_irq_nosync(ab->irq_num[irq_idx]); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + } +#endif + } + return ret; +} + +static int ath12k_pcic_config_gic_msi_irq(struct ath12k_base *ab, + struct platform_device *pdev, + struct msi_desc *msi_desc, int i) +{ + struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; + int irq_idx, ret; + u8 userpd_id = ab->userpd_id; + + tasklet_setup(&ce_pipe->intr_tq, ath12k_pcic_ce_tasklet); + irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; + + scnprintf(ce_irq_name[userpd_id][irq_idx], DP_IRQ_NAME_LEN, + "pci%u_wlan_ce_%u", userpd_id, i); + + ret = devm_request_irq(&pdev->dev, msi_desc->irq, + ath12k_pcic_ce_interrupt_handler, IRQF_SHARED, + ce_irq_name[userpd_id][irq_idx], ce_pipe); + if (ret) { + ath12k_warn(ab, "failed to request irq %d: %d\n", irq_idx, ret); + return ret; + } + + ab->irq_num[irq_idx] = msi_desc->irq; + ab->ipci.ce_msi_data[i] = msi_desc->msg.data; + ath12k_pcic_ce_irq_disable(ab, i); + + return ret; +} + +static void ath12k_pcic_kill_tasklets(struct ath12k_base *ab) +{ + int i; + + for (i = 0; i < ab->hw_params->ce_count; i++) { + struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; + + if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) + continue; + + tasklet_kill(&ce_pipe->intr_tq); + } +} + +static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab) +{ + int i; + int irq_idx; + + for (i = 0; i < ab->hw_params->ce_count; i++) { + if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) + continue; + + irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; + synchronize_irq(ab->irq_num[irq_idx]); + } +} + +void ath12k_pcic_ce_irq_disable_sync(struct ath12k_base *ab) +{ + ath12k_pcic_ce_irqs_disable(ab); + ath12k_pci_sync_ce_irqs(ab); + ath12k_pcic_kill_tasklets(ab); +} + +int ath12k_pcic_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, + u8 *ul_pipe, u8 *dl_pipe) +{ + const struct service_to_pipe *entry; + bool ul_set = false, dl_set = false; + int i; + + for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { + entry = &ab->hw_params->svc_to_ce_map[i]; + + if (__le32_to_cpu(entry->service_id) != service_id) + continue; + + switch (__le32_to_cpu(entry->pipedir)) { + case PIPEDIR_NONE: + break; + case PIPEDIR_IN: + WARN_ON(dl_set); + *dl_pipe = __le32_to_cpu(entry->pipenum); + dl_set = true; + break; + case PIPEDIR_OUT: + WARN_ON(ul_set); + *ul_pipe = __le32_to_cpu(entry->pipenum); + ul_set = true; + break; + case PIPEDIR_INOUT: + WARN_ON(dl_set); + WARN_ON(ul_set); + *dl_pipe = __le32_to_cpu(entry->pipenum); + *ul_pipe = __le32_to_cpu(entry->pipenum); + dl_set = true; + ul_set = true; + break; + } + } + + if (WARN_ON(!ul_set || !dl_set)) + return -ENOENT; + + return 0; +} + +int ath12k_pcic_get_msi_irq(struct ath12k_base *ab, unsigned int vector) +{ + return ab->msi.irqs[vector]; +} + +int ath12k_pcic_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, + int *num_vectors, u32 *user_base_data, + u32 *base_vector) +{ + const struct ath12k_msi_config *msi_config = ab->msi.config; + int idx; + + for (idx = 0; idx < msi_config->total_users; idx++) { + if (strcmp(user_name, msi_config->users[idx].name) == 0) { + *num_vectors = msi_config->users[idx].num_vectors; + *user_base_data = msi_config->users[idx].base_vector + + ab->msi.ep_base_data; + *base_vector = msi_config->users[idx].base_vector; + + ath12k_dbg(ab, ATH12K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", + user_name, *num_vectors, *user_base_data, + *base_vector); + + return 0; + } + } + + ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); + + return -EINVAL; +} + +void ath12k_pcic_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, + u32 *msi_addr_hi) +{ + *msi_addr_lo = ab->msi.addr_lo; + *msi_addr_hi = ab->msi.addr_hi; +} + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +int ath12k_pcic_ppeds_register_interrupts(struct ath12k_base *ab, int type, int vector, + int ring_num) +{ + + int ret, irq; + u8 bus_id = ab->userpd_id; + struct platform_device *pdev = ab->pdev; + + if (ab->ppeds_node_idx == -1) { + ath12k_err(ab, "invalid ppeds_node_idx in ppeds_register_interrupts\n"); + return -EINVAL; + } + + if (type == HAL_PPE2TCL) { + irq = ab->dp.ppeds_irq[PPEDS_IRQ_PPE2TCL]; + if (!irq) + goto irq_fail; + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + snprintf(&ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE2TCL], sizeof(ab->dp.ppeds_irq_name), + "pci%d_ppe2tcl_%d", bus_id, ab->ppeds_node_idx); + ret = devm_request_irq(&pdev->dev, irq, ath12k_ds_ppe2tcl_irq_handler, + IRQF_SHARED, + ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE2TCL], (void *)ath12k_dp_get_ppe_ds_ctxt(ab)); + if (ret) + goto irq_fail; + ab->dp.ppeds_irq[PPEDS_IRQ_PPE2TCL] = irq; + } else if (type == HAL_REO2PPE) { + irq = ab->dp.ppeds_irq[PPEDS_IRQ_REO2PPE]; + if (!irq) + goto irq_fail; + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + snprintf(&ab->dp.ppeds_irq_name[PPEDS_IRQ_REO2PPE], sizeof(ab->dp.ppeds_irq_name), + "pci%d_reo2ppe_%d", bus_id, ab->ppeds_node_idx); + ret = devm_request_irq(&pdev->dev, irq, ath12k_ds_reo2ppe_irq_handler, + IRQF_SHARED, + ab->dp.ppeds_irq_name[PPEDS_IRQ_REO2PPE], (void *)ath12k_dp_get_ppe_ds_ctxt(ab)); + if (ret) + goto irq_fail; + ab->dp.ppeds_irq[PPEDS_IRQ_REO2PPE] = irq; + } else if (type == HAL_WBM2SW_RELEASE && ring_num == HAL_WBM2SW_PPEDS_TX_CMPLN_RING_NUM) { + irq = ab->dp.ppeds_irq[PPEDS_IRQ_PPE_WBM2SW_REL]; + if (!irq) + goto irq_fail; + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + snprintf(&ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE_WBM2SW_REL], sizeof(ab->dp.ppeds_irq_name), + "pci%d_ppe_wbm_rel_%d", bus_id, ab->ppeds_node_idx); + ret = devm_request_irq(&pdev->dev, irq, ath12k_dp_ppeds_handle_tx_comp, + IRQF_SHARED, + ab->dp.ppeds_irq_name[PPEDS_IRQ_PPE_WBM2SW_REL],(void *)ab); + if (ret) + goto irq_fail; + ab->dp.ppeds_irq[PPEDS_IRQ_PPE_WBM2SW_REL] = irq; + } else { + return 0; + } + disable_irq_nosync(irq); + + return 0; + +irq_fail: + return ret; +} + +void ath12k_pcic_ppeds_irq_disable(struct ath12k_base *ab, enum ppeds_irq_type type) +{ + disable_irq_nosync(ab->dp.ppeds_irq[type]); +} + +void ath12k_pcic_ppeds_irq_enable(struct ath12k_base *ab, enum ppeds_irq_type type) +{ + enable_irq(ab->dp.ppeds_irq[type]); +} + +void ath12k_pcic_ppeds_free_interrupts(struct ath12k_base *ab) +{ + disable_irq_nosync(ab->dp.ppeds_irq[PPEDS_IRQ_PPE2TCL]); + free_irq(ab->dp.ppeds_irq[PPEDS_IRQ_PPE2TCL], ath12k_dp_get_ppe_ds_ctxt(ab)); + + disable_irq_nosync(ab->dp.ppeds_irq[PPEDS_IRQ_REO2PPE]); + free_irq(ab->dp.ppeds_irq[PPEDS_IRQ_REO2PPE], ath12k_dp_get_ppe_ds_ctxt(ab)); + + disable_irq_nosync(ab->dp.ppeds_irq[PPEDS_IRQ_PPE_WBM2SW_REL]); + free_irq(ab->dp.ppeds_irq[PPEDS_IRQ_PPE_WBM2SW_REL], ab); +} + +irqreturn_t ath12k_pcic_dummy_irq_handler(int irq, void *context) +{ + return IRQ_HANDLED; +} + +int ath12k_pcic_get_msi_data(struct ath12k_base *ab, struct msi_desc *msi_desc, + int i) +{ + int ret, type; + struct platform_device *pdev = ab->pdev; + + if (ab->hw_params->ring_mask->ppe2tcl[i]) + type = PPEDS_IRQ_PPE2TCL; + else if (ab->hw_params->ring_mask->reo2ppe[i]) + type = PPEDS_IRQ_REO2PPE; + else if (ab->hw_params->ring_mask->wbm2sw6_ppeds_tx_cmpln[i]) + type = PPEDS_IRQ_PPE_WBM2SW_REL; + else + return -EINVAL; + + /* For multi-platform device, to retrieve msi base address and irq data, + * request a dummy irq store the base address and data to + * provide the required base address/data info in + * hal_srng_init and srng_msi_setup API calls. + */ + ab->dp.ppeds_irq[type] = msi_desc->irq; + ret = devm_request_irq(&pdev->dev, msi_desc->irq, + ath12k_pcic_dummy_irq_handler, IRQF_SHARED, + "dummy", (void *)ab); + + if (ret) + return -EINVAL; + + ab->ipci.dp_msi_data[i] = msi_desc->msg.data; + disable_irq_nosync(ab->dp.ppeds_irq[type]); + free_irq(ab->dp.ppeds_irq[type], (void *)ab); + + return 0; +} +#endif + +void ath12k_pcic_ext_irq_enable(struct ath12k_base *ab) +{ + int i; + + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { + struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + + napi_enable(&irq_grp->napi); + ath12k_pcic_ext_grp_enable(irq_grp); + } +} + +void ath12k_pcic_ext_irq_disable(struct ath12k_base *ab) +{ + __ath12k_pcic_ext_irq_disable(ab); + ath12k_pcic_sync_ext_irqs(ab); +} + +void ath12k_pcic_stop(struct ath12k_base *ab) +{ + ath12k_pcic_ce_irq_disable_sync(ab); + ath12k_ce_cleanup_pipes(ab); +} + +int ath12k_pcic_start(struct ath12k_base *ab) +{ + ath12k_pcic_ce_irqs_enable(ab); + ath12k_ce_rx_post_buf(ab); + + return 0; +} + +u32 ath12k_pcic_ipci_read32(struct ath12k_base *ab, u32 offset) +{ + u32 val, window_start; + + window_start = ath12k_pcic_get_window_start(ab, offset); + val = ioread32(ab->mem + window_start + + (offset & WINDOW_RANGE_MASK)); + + return val; +} + +void ath12k_pcic_ipci_write32(struct ath12k_base *ab, u32 offset, u32 value) +{ + u32 window_start; + + window_start = ath12k_pcic_get_window_start(ab, offset); + iowrite32(value, ab->mem + window_start + + (offset & WINDOW_RANGE_MASK)); +} + +static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) +{ + int i, j, ret, num_vectors = 0; + u32 user_base_data = 0, base_vector = 0, base_idx, budget; + struct ath12k_pci *ar_pci = (struct ath12k_pci *)ab->drv_priv; + + base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; + ret = ath12k_pcic_get_user_msi_assignment(ab, "DP", &num_vectors, + &user_base_data, &base_vector); + if (ret < 0) + return ret; + + if (ath12k_napi_poll_budget < NAPI_POLL_WEIGHT) + ath12k_napi_poll_budget = NAPI_POLL_WEIGHT; + + for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX(ab); i++) { + struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; + u32 num_irq = 0; + + irq_grp->ab = ab; + irq_grp->grp_id = i; + init_dummy_netdev(&irq_grp->napi_ndev); + + if (ab->hw_params->ring_mask->rx_mon_dest[i]) + budget = NAPI_POLL_WEIGHT; + else + budget = ath12k_napi_poll_budget; + + /* Apply a reduced budget for tx completion to prioritize tx + * enqueue operation + */ + if (ab->hw_params->ring_mask->tx[i]) + budget = tx_comp_budget; + netif_napi_add_weight(&irq_grp->napi_ndev, &irq_grp->napi, + ath12k_pcic_ext_grp_napi_poll, budget); + + if (ab->hw_params->ring_mask->tx[i] || + ab->hw_params->ring_mask->rx[i] || + ab->hw_params->ring_mask->rx_err[i] || + ab->hw_params->ring_mask->rx_wbm_rel[i] || + ab->hw_params->ring_mask->reo_status[i] || + ab->hw_params->ring_mask->host2rxdma[i] || + ab->hw_params->ring_mask->ppe2tcl[i] || +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + ab->hw_params->ring_mask->wbm2sw6_ppeds_tx_cmpln[i] || +#endif + ab->hw_params->ring_mask->reo2ppe[i] || + ab->hw_params->ring_mask->rx_mon_dest[i]) { + num_irq = 1; + } + + irq_grp->num_irq = num_irq; + irq_grp->irqs[0] = base_idx + i; + + for (j = 0; j < irq_grp->num_irq; j++) { + int irq_idx = irq_grp->irqs[j]; + int vector = (i % num_vectors) + base_vector; + int irq = ath12k_hif_get_msi_irq(ab, vector); + u8 bus_id = pci_domain_nr(ar_pci->pdev->bus); + + if (bus_id > ATH12K_MAX_PCI_DOMAINS) { + ath12k_dbg(ab, ATH12K_DBG_PCI, "bus_id:%d\n", + bus_id); + bus_id = ATH12K_MAX_PCI_DOMAINS; + } + + ab->irq_num[irq_idx] = irq; + + ath12k_dbg(ab, ATH12K_DBG_PCI, "irq:%d group:%d\n", irq, i); + + scnprintf(dp_irq_name[bus_id][i], DP_IRQ_NAME_LEN, + "pci%u_wlan_dp_%u", bus_id, i); + ath12k_dbg(ab, ATH12K_DBG_PCI, "PCI bus id: pci:%d IRQ Name:%s\n", + bus_id, dp_irq_name[bus_id][i]); + irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); + ret = request_irq(irq, ath12k_pcic_ext_interrupt_handler, + IRQF_SHARED, + dp_irq_name[bus_id][i], irq_grp); + if (ret) { + ath12k_err(ab, "failed request irq %d: %d\n", + vector, ret); + return ret; + } + + disable_irq_nosync(ab->irq_num[irq_idx]); + } + } + + return 0; +} + +int ath12k_pcic_config_irq(struct ath12k_base *ab) +{ + struct ath12k_ce_pipe *ce_pipe; + u32 msi_data_start; + u32 msi_data_count, msi_data_idx; + u32 msi_irq_start; + unsigned int msi_data; + int irq, i, ret, irq_idx; + + ret = ath12k_pcic_get_user_msi_assignment(ab, "CE", &msi_data_count, + &msi_data_start, &msi_irq_start); + if (ret) + return ret; + + /* Configure CE irqs */ + for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { + if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) + continue; + + msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; + irq = ath12k_hif_get_msi_irq(ab, msi_data); + ce_pipe = &ab->ce.ce_pipe[i]; + + irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; + + tasklet_setup(&ce_pipe->intr_tq, ath12k_pcic_ce_tasklet); + + ret = request_irq(irq, ath12k_pcic_ce_interrupt_handler, + IRQF_SHARED, irq_name[irq_idx], + ce_pipe); + if (ret) { + ath12k_err(ab, "failed to request irq %d: %d\n", + irq_idx, ret); + return ret; + } + + ab->irq_num[irq_idx] = irq; + msi_data_idx++; + + ath12k_pcic_ce_irq_disable(ab, i); + } + + ret = ath12k_pci_ext_irq_config(ab); + if (ret) + return ret; + + return 0; +} + +static void ath12k_msi_msg_handler(struct msi_desc *desc, struct msi_msg *msg) +{ + desc->msg.address_lo = msg->address_lo; + desc->msg.address_hi = msg->address_hi; + desc->msg.data = msg->data; +} + +int ath12k_pcic_config_hybrid_irq(struct ath12k_base *ab) +{ + int ret; + struct platform_device *pdev = ab->pdev; + struct msi_desc *msi_desc; + bool ce_done = false; + int user_base_data, base_vector, num_vectors = 0; + int i = 0, j = 0, k = 0; + + if (ab->userpd_id != USERPD_1 && + ab->userpd_id != USERPD_2) { + ath12k_warn(ab, "ath12k userpd invalid %d\n", ab->userpd_id); + return -ENODEV; + } + + ab->msi.config = &ath12k_msi_config[ATH12K_MSI_CONFIG_IPCI]; + + ret = platform_msi_domain_alloc_irqs(&pdev->dev, ab->msi.config->total_vectors, + ath12k_msi_msg_handler); + + if (ret) { + ath12k_warn(ab, "failed to alloc irqs %d ab %pM\n", ret, ab); + return ret; + } + + /* TODO: Need to optimize the below code to have one loop */ + msi_for_each_desc(msi_desc, &pdev->dev, MSI_DESC_ALL) { + ret = ath12k_pcic_get_user_msi_assignment(ab, "CE", &num_vectors, + &user_base_data, &base_vector); + if (ret < 0) + return ret; + + if (i < base_vector) { + i++; + continue; + } + if (j < ab->hw_params->ce_count && i < (num_vectors + base_vector)) { + while(j < ab->hw_params->ce_count && + ath12k_ce_get_attr_flags(ab, j) & CE_ATTR_DIS_INTR) { + ++j; + } + + ret = ath12k_pcic_config_gic_msi_irq(ab, pdev, msi_desc, j); + if (ret) { + ath12k_warn(ab, "failed to request irq %d\n", ret); + return ret; + } + + if (j == 0) { + ab->msi.addr_lo = msi_desc->msg.address_lo; + ab->msi.addr_hi = msi_desc->msg.address_hi; + ab->msi.ep_base_data = msi_desc->msg.data; + ath12k_info(ab, "msi ep base data %d\n", ab->msi.ep_base_data); + } + + j++; + if (j != ab->hw_params->ce_count) + ce_done = false; + + } else { + ret = ath12k_pcic_ext_config_gic_msi_irq(ab, pdev, msi_desc, k); + if (ret) { + ath12k_warn(ab, "failed to config ext msi irq %d\n", ret); + return ret; + } + k++; + } + i++; + } + + i = 0; + + msi_for_each_desc(msi_desc, &pdev->dev, MSI_DESC_ALL) { + ret = ath12k_pcic_get_user_msi_assignment(ab, "CE", &num_vectors, + &user_base_data, &base_vector); + if (ret < 0) + return ret; + + if (i < base_vector) { + i++; + continue; + } + if (i < (num_vectors + base_vector)) { + if (!ce_done && j < ab->hw_params->ce_count) { + while(j < ab->hw_params->ce_count && + ath12k_ce_get_attr_flags(ab, j) & CE_ATTR_DIS_INTR) { + j++; + } + if (j == ab->hw_params->ce_count) { + ce_done = true; + i++; + continue; + } + + ret = ath12k_pcic_config_gic_msi_irq(ab, pdev, msi_desc, j); + if (ret) { + ath12k_warn(ab, "failed to request irq %d\n", ret); + return ret; + } + j++; + } + } else { + if (k >= ATH12K_EXT_IRQ_GRP_NUM_MAX(ab)) + break; + ret = ath12k_pcic_ext_config_gic_msi_irq(ab, pdev, msi_desc, k); + if (ret) { + ath12k_warn(ab, "failed to config ext msi irq %d\n", ret); + return ret; + } + k++; + } + i++; + } + ab->ipci.gic_enabled = 1; + wake_up(&ab->ipci.gic_msi_waitq); + + return ret; +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/pcic.h 2024-01-19 17:01:19.869847139 +0100 @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _ATH11K_PCI_CMN_H +#define _ATH11K_PCI_CMN_H + +#include +#include +#include "core.h" +#include "hif.h" +#include + +#define ATH12K_PCI_IRQ_CE0_OFFSET 3 + +#define WINDOW_ENABLE_BIT 0x40000000 +#define WINDOW_REG_ADDRESS 0x310c +#define WINDOW_VALUE_MASK GENMASK(24, 19) +#define WINDOW_START 0x80000 +#define WINDOW_RANGE_MASK GENMASK(18, 0) + +#define ATH12K_MAX_PCI_DOMAINS 0x5 +#define DP_IRQ_NAME_LEN 20 + +static const struct ath12k_msi_config ath12k_msi_config[] = { + { + /* MSI spec expects number of interrupts to be a power of 2 */ + .total_vectors = 32, + .total_users = 3, + .users = (struct ath12k_msi_user[]) { + { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, + { .name = "CE", .num_vectors = 5, .base_vector = 3 }, + { .name = "DP", .num_vectors = 16, .base_vector = 8 }, + }, + }, + { + /* In DP, we use num_vectors as 9 (6 REGULAR DP INTERRUPTS + 3 PPEDS + * INTERRUPTS) + */ + .total_vectors = 15, + .total_users = 3, + .users = (struct ath12k_msi_user[]) { + { .name = "QDSS", .num_vectors = 1, .base_vector = 0 }, + { .name = "CE", .num_vectors = 5, .base_vector = 1 }, + { .name = "DP", .num_vectors = 9, .base_vector = 6 }, + }, + }, +}; + +int ath12k_pcic_start(struct ath12k_base *ab); +void ath12k_pcic_stop(struct ath12k_base *ab); +void ath12k_pcic_ipci_write32(struct ath12k_base *ab, u32 offset, u32 value); +u32 ath12k_pcic_ipci_read32(struct ath12k_base *ab, u32 offset); +int ath12k_pcic_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, + int *num_vectors, u32 *user_base_data, + u32 *base_vector); +void ath12k_pcic_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, + u32 *msi_addr_hi); +void ath12k_pcic_config_static_window(struct ath12k_base *ab); +int ath12k_pcic_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, + u8 *ul_pipe, u8 *dl_pipe); +void ath12k_pcic_free_hybrid_irq(struct ath12k_base *ab); +void ath12k_pcic_cmem_write32(struct ath12k_base *ab, u32 addr, + u32 value); +u32 ath12k_pcic_cmem_read32(struct ath12k_base *ab, u32 addr); +void ath12k_pcic_ext_irq_enable(struct ath12k_base *ab); +void ath12k_pcic_ext_irq_disable(struct ath12k_base *ab); +u32 ath12k_pcic_get_window_start(struct ath12k_base *ab, u32 offset); +void ath12k_pcic_ce_irqs_enable(struct ath12k_base *ab); +void ath12k_pcic_ce_irq_disable_sync(struct ath12k_base *ab); +int ath12k_pcic_get_msi_irq(struct ath12k_base *ab, unsigned int vector); +int ath12k_pcic_config_hybrid_irq(struct ath12k_base *ab); +int ath12k_pcic_config_irq(struct ath12k_base *ab); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +int ath12k_pcic_ppeds_register_interrupts(struct ath12k_base *ab, int type, + int vector, int ring_num); +void ath12k_pcic_ppeds_free_interrupts(struct ath12k_base *ab); +void ath12k_pcic_ppeds_irq_enable(struct ath12k_base *ab, enum ppeds_irq_type type); +void ath12k_pcic_ppeds_irq_disable(struct ath12k_base *ab, enum ppeds_irq_type type); +int ath12k_pcic_get_msi_data(struct ath12k_base *ab, struct msi_desc *msi_desc, int i); +#endif +void ath12k_pcic_free_irq(struct ath12k_base *ab); +#endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/pktlog.h 2024-03-18 14:40:14.859741552 +0100 @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _PKTLOG_H_ +#define _PKTLOG_H_ + +#ifdef CONFIG_ATH12K_PKTLOG +#define CUR_PKTLOG_VER 10010 /* Packet log version */ +#define PKTLOG_MAGIC_NUM 7735225 +#define PKTLOG_NEW_MAGIC_NUM 2453506 +#define PKTLOG_MAGIC_NUM_FW_VERSION_SUPPORT 0xDECDF1F0 + +/* Masks for setting pktlog events filters */ +#define ATH_PKTLOG_RX 0x000000001 +#define ATH_PKTLOG_TX 0x000000002 +#define ATH_PKTLOG_RCFIND 0x000000004 +#define ATH_PKTLOG_RCUPDATE 0x000000008 + +#define ATH_DEBUGFS_PKTLOG_SIZE_DEFAULT (8 * 1024 * 1024) +#define ATH_PKTLOG_FILTER_DEFAULT (ATH_PKTLOG_TX | ATH_PKTLOG_RX | \ + ATH_PKTLOG_RCFIND | ATH_PKTLOG_RCUPDATE) + +enum { + PKTLOG_FLG_FRM_TYPE_LOCAL_S = 0, + PKTLOG_FLG_FRM_TYPE_REMOTE_S, + PKTLOG_FLG_FRM_TYPE_CLONE_S, + PKTLOG_FLG_FRM_TYPE_UNKNOWN_S +}; + +struct ath12k_pktlog_hdr_arg { + u16 log_type; + u8 *payload; + u16 payload_size; + u8 *pktlog_hdr; +}; + +struct ath12k_pl_fw_info { + u32 pdev_id; + u8 software_image[40]; + u8 chip_info[40]; + u32 pktlog_defs_json_version; +} __packed; + +struct ath12k_pktlog_decode_info { + u8 software_image[40]; + u8 chip_info[40]; + u32 pktlog_defs_json_version; +}; + +struct ath12k_pktlog_bufhdr { + u32 magic_num; /* Used by post processing scripts */ + u32 version; /* Set to CUR_PKTLOG_VER */ + u8 software_image[40]; + u8 chip_info[40]; + u32 pktlog_defs_json_version; +}; + +struct ath12k_pktlog_buf { + struct ath12k_pktlog_bufhdr bufhdr; + int rd_offset; + int wr_offset; + char log_data[0]; +}; + +struct ath12k_pktlog { + struct ath12k_pktlog_buf *buf; + u32 filter; + u32 buf_size; /* Size of buffer in bytes */ + spinlock_t lock; + u8 hdr_size; + u8 hdr_size_field_offset; + u32 fw_version_record; + u32 invalid_decode_info; +}; + +#endif /* CONFIG_ATH12K_PKTLOG */ +#endif /* _PKTLOG_H_ */ + --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/ppe.h 2024-03-18 14:40:14.859741552 +0100 @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef ATH12K_PPE_H +#define ATH12K_PPE_H + +#define ATH12K_PPEDS_DEFAULT_POOL_ID 0 + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + +#define ATH12K_DP_PPEDS_NAPI_DONE_BIT 1 +#define ATH12K_DP_PPEDS_TX_COMP_NAPI_BIT 2 + +struct dp_ppe_ds_idxs { + u32 ppe2tcl_start_idx; + u32 reo2ppe_start_idx; +}; + +void ath12k_dp_srng_ppeds_cleanup(struct ath12k_base *ab); +int ath12k_dp_srng_ppeds_setup(struct ath12k_base *ab); +int ath12k_dp_ppeds_register_soc(struct ath12k_dp *dp, + struct dp_ppe_ds_idxs *idx); +void ath12k_dp_ppeds_stop(struct ath12k_base *ab); +int ath12k_dp_ppeds_start(struct ath12k_base *ab); +int ath12k_ppeds_detach( struct ath12k_base *ab); +int ath12k_ppeds_attach( struct ath12k_base *ab); +int ath12k_mac_op_ppeds_attach_vdev(struct ath12k_link_vif *arvif, + void *vp_arg, int *ppe_vp_num, + struct ieee80211_ppe_vp_ds_params *vp_params); +void ath12k_mac_op_ppeds_detach_vdev(struct ath12k_link_vif *arvif, + struct ieee80211_ppe_vp_ds_params *vp_params); +void ath12k_dp_peer_ppeds_route_setup(struct ath12k *ar, struct ath12k_link_vif *arvif, + struct ath12k_link_sta *arsta); +int ath12k_ppeds_get_handle(struct ath12k_base *ab); +void *ath12k_dp_get_ppe_ds_ctxt(struct ath12k_base *ab); +irqreturn_t ath12k_ds_ppe2tcl_irq_handler(int irq, void *ctxt); +irqreturn_t ath12k_ds_reo2ppe_irq_handler(int irq, void *ctxt); +irqreturn_t ath12k_dp_ppeds_handle_tx_comp(int irq, void *ctxt); +void ath12k_dp_ppeds_update_vp_entry(struct ath12k *ar, + struct ath12k_link_vif *arvif); +void ath12k_dp_ppeds_service_enable_disable(struct ath12k_base *ab, + bool enable); +void ath12k_dp_ppeds_interrupt_stop(struct ath12k_base *ab); +void ath12k_dp_ppeds_stop(struct ath12k_base *ab); +void ath12k_dp_ppeds_interrupt_start(struct ath12k_base *ab); +void ath12k_ppeds_partner_link_start_queues(struct ath12k *ar); +void ath12k_ppeds_partner_link_stop_queues(struct ath12k *ar); +#endif +#endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/sawf.h 2024-03-18 14:40:14.859741552 +0100 @@ -0,0 +1,902 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef ATH12K_SAWF_H +#define ATH12K_SAWF_H + +struct hal_tx_status; +struct stats_config; +struct telemetry_sawftx_stats; +struct telemetry_sawfdelay_stats; + +#ifdef CONFIG_ATH12K_SAWF +#include + +#define ATH12K_MAC_ADDR_SIZE 6 +#define DP_SAWF_INVALID_PARAM -1 + +#define ATH12K_SAWF_SVC_CLASS_MIN 1 +#define ATH12K_SAWF_SVC_CLASS_MAX 128 +#define ATH12K_SAWF_MAX_TID_SUPPORT 8 +#define MAX_Q_PER_TID 8 +/** + ** SAWF_metadata related information. + **/ +#define SAWF_VALID_TAG 0xAA +#define SAWF_TAG_SHIFT 0x18 + +/* Skb mark for SAWF */ +#define SAWF_MSDUQ_ID GENMASK(5, 0) +#define SAWF_PEER_ID GENMASK(15, 6) +#define SAWF_SERVICE_CLASS_ID GENMASK(23, 16) +#define SAWF_TAG_ID GENMASK(31, 24) +#define SAWF_NW_DELAY GENMASK(23, 6) +#define SAWF_NW_DELAY_SHIFT 0x6 +#define SAWF_NW_DELAY_MAX 0x3FFFF + +#define TID_FROM_Q_ID GENMASK(2, 0) +#define FLOW_OVERRIDE_FROM_Q_ID BIT(3) +#define WHO_CLASSIFY_INFO_FROM_Q_ID GENMASK(5, 4) + +#define SAWF_PEER_MSDUQ_INVALID 0xFFFF +#define SAWF_MSDUQ_ID_INVALID 0x3F +#define SAWF_MSDUQ_ID GENMASK(5, 0) +#define SAWF_PEER_ID GENMASK(15, 6) + +#define MSDUQID_TID_MASK GENMASK(2, 0) +#define MSDUQID_Q_MASK GENMASK(5, 3) +/* + * Min throughput limit 0 - 10 Gb/s + * Granularity: 1 Kb/s + */ +#define ATH12K_SAWF_MIN_MIN_THROUGHPUT 0 +#define ATH12K_SAWF_MAX_MIN_THROUGHPUT (10 * 1024 * 1024) + +/* + * Max throughput limit 0 - 10 Gb/s. + * Granularity: 1 Kb/s + */ +#define ATH12K_SAWF_MIN_MAX_THROUGHPUT 0 +#define ATH12K_SAWF_MAX_MAX_THROUGHPUT (10 * 1024 * 1024) + +/* + * Service interval limit 0 - 10 secs. + * Granularity: 100 µs + */ +#define ATH12K_SAWF_MIN_SVC_INTERVAL 0 +#define ATH12K_SAWF_MAX_SVC_INTERVAL (10 * 100 * 100) + +/* + * Burst size 0 - 16 MB. + * Granularity: 1 Byte. + */ +#define ATH12K_SAWF_MIN_BURST_SIZE 0 +#define ATH12K_SAWF_MAX_BURST_SIZE (16 * 1024 * 1024) +/* + * Delay bound limit 0 - 10 secs + * Granularity: 100 µs + */ +#define ATH12K_SAWF_MIN_DELAY_BOUND 0 +#define ATH12K_SAWF_MAX_DELAY_BOUND (10 * 100 * 100) + +/* + * Msdu TTL limit 0 - 10 secs. + * Granularity: 100 µs + */ +#define ATH12K_SAWF_MIN_MSDU_TTL 0 +#define ATH12K_SAWF_MAX_MSDU_TTL (10 * 100 * 100) + +/* + * Priority limit 0 - 127. + * Higher the numerical value, higher is the priority. + */ +#define ATH12K_SAWF_MIN_PRIORITY 0 +#define ATH12K_SAWF_MAX_PRIORITY 127 + +/* + * TID limit 0 - 7 + */ +#define ATH12K_SAWF_MIN_TID 0 +#define ATH12K_SAWF_MAX_TID 7 +/* + * MSDU Loss Rate limit 0 - 100%. + * Granularity: 0.01% + */ +#define ATH12K_SAWF_MIN_MSDU_LOSS_RATE 0 +#define ATH12K_SAWF_MAX_MSDU_LOSS_RATE 10000 + +#define ATH12K_SAWF_STATS_SIZE 4096 + +enum SAWF_SVC_PARAM_DEFAULTS { + SAWF_SVC_PARAM_DEFAULT_MIN_THRUPUT = 0, + SAWF_SVC_PARAM_DEFAULT_MAX_THRUPUT = 0xffffffff, + SAWF_SVC_PARAM_DEFAULT_BURST_SIZE = 0, + SAWF_SVC_PARAM_DEFAULT_SVC_INTERVAL = 0xffffffff, + SAWF_SVC_PARAM_DEFAULT_DELAY_BOUND = 0xffffffff, + SAWF_SVC_PARAM_DEFAULT_TIME_TO_LIVE = 0xffffffff, + SAWF_SVC_PARAM_DEFAULT_PRIORITY = 0, + SAWF_SVC_PARAM_DEFAULT_TID = 0xffffffff, + SAWF_SVC_PARAM_DEFAULT_MSDU_LOSS_RATE = 0, + SAWF_SVC_PARAM_DEFAULT_UL_BURST_SIZE = 0, + SAWF_SVC_PARAM_DEFAULT_UL_MIN_TPUT = 0, + SAWF_SVC_PARAM_DEFAULT_UL_MAX_LATENCY = 0xffffffff, + SAWF_SVC_PARAM_DEFAULT_UL_SVC_INTERVAL = 0xffffffff, + SAWF_SVC_PARAM_DEFAULT_UL_OFDMA_DISABLE = 0, + SAWF_SVC_PARAM_DEFAULT_UL_MU_MIMO_DISABLE = 0, +}; + +#define DELAY_BOUND_ULTRA_LOW 10 +#define DELAY_BOUND_LOW 100 +#define DELAY_BOUND_MID 200 +#define DELAY_BOUND_HIGH 300 +#define SVC_INTERVAL_ULTRA_LOW 20 +#define SVC_INTERVAL_LOW 50 +#define TIME_TO_LIVE_ULTRA_LOW 20 +#define TIME_TO_LIVE_LOW 200 +#define TIME_TO_LIVE_MID 250 + +/** + * struct ath12k_sawf_svc_params - Service Class Parameters + * @svc_id: Service ID + * @app_name: Service class name + * @min_throughput_rate: min throughput in kilobits per second + * @max_throughput_rate: max throughput in kilobits per second + * @burst_size: burst size in bytes + * @service_interval: service interval + * @delay_bound: delay bound in milli seconds + * @msdu_ttl: MSDU Time-To-Live + * @priority: Priority + * @tid: TID + * @msdu_rate_loss: MSDU loss rate in parts per million + * @ul_service_interval: Uplink service interval + * @ul_burst_size: Uplink Burst Size + * @ul_min_tput: Uplink min_throughput + * @ul_max_latency: Uplink max latency + * @ul_ofdma_disable: Disable ofdma + * @ul_mu_mimo_disable: Disale MU MIMO + * @configured: indicating if the serivice class is configured. + */ + +struct ath12k_sawf_svc_params { + u8 svc_id; + u32 min_throughput_rate; + u32 max_throughput_rate; + u32 burst_size; + u32 service_interval; + u32 delay_bound; + u32 msdu_ttl; + u32 priority; + u32 tid; + u32 msdu_rate_loss; + u32 ul_service_interval; + u32 ul_burst_size; + u32 ul_min_tput; + u32 ul_max_latency; + bool ul_ofdma_disable; + bool ul_mu_mimo_disable; + bool configured; +}; + +struct ath12k_ul_params { + struct list_head list; + struct net_device *dest_dev; + struct net_device *src_dev; + u8 dst_mac[ETH_ALEN]; + u8 src_mac[ETH_ALEN]; + u8 fw_service_id; + u8 rv_service_id; + u8 add_or_sub; +}; + +/** + * struct ath12k_sawf_ctx- SAWF context + * @svc_classes: List of all service classes + */ +struct ath12k_sawf_ctx { + struct ath12k_sawf_svc_params svc_classes[ATH12K_SAWF_SVC_CLASS_MAX]; + u32 max_msduq_per_tid; + u32 default_msduq_per_tid; + spinlock_t sawf_svc_lock; + struct workqueue_struct *workqueue; + struct work_struct ul_configure; + struct list_head list; +}; + +/** + * struct ath12k_msduq_map- MSDU Q Map struct + * mapping of MSDUQ with service class ID + * @svc_id: Service Class ID + * @is_reserved: Flag to hold the allocaiton status. + * @msduq_id: unique id of the MSDUQ. + */ +struct ath12k_msduq_map { + u8 svc_id; + bool is_reserved; + u16 msduq_id; +}; + +/** + * struct ath12k_sawf_def_queue_report : default Q map report + */ +struct ath12k_sawf_def_queue_report { + u8 svc_class_id; +}; + +/** + * struct ath12k_sawf_peer_ctx + * A Data base to maintain the allocation status of user deined MSDUQ. + * The allocation is mapped with the service class ID. + * @msduq_table: map table of msduq and svc id per peer + * @def_q_map: default q map report + * @telemetry_peer_ctx: pointer to hold the structure reference + * maintained in telemetry agent module. + */ +struct ath12k_sawf_peer_ctx { + struct ath12k_msduq_map msduq_table[ATH12K_SAWF_MAX_TID_SUPPORT][MAX_Q_PER_TID]; + struct ath12k_sawf_def_queue_report def_q_map[ATH12K_SAWF_MAX_TID_SUPPORT]; + void *telemetry_peer_ctx; +}; + +/* MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ + * + * @details + * The SAWF_DEF_QUEUES_MAP_REQ message is sent by the host to link + * the default MSDU queues for one of the TIDs within the specified peer + * to the specified service class. + * The TID is indirectly specified - each service class is associated + * with a TID. All default MSDU queues for this peer-TID will be + * linked to the service class in question. + * + * |31 16|15 8|7 0| + * |------------------------------+--------------+--------------| + * | peer ID | svc class ID | msg type | + * |------------------------------------------------------------| + * Header fields: + * dword0 - b'7:0 - msg_type: This will be set to + * 0x1c (HTT_H2T_SAWF_DEF_QUEUES_MAP_REQ) + * b'15:8 - service class ID + * b'31:16 - peer ID + */ +struct ath12k_htt_h2t_sawf_def_q_map_req { + u32 info; +}; + +#define HTT_H2T_MSG_TYPE_ID GENMASK(7, 0) +#define HTT_H2T_SAWF_DEF_Q_MAP_SVC_ID GENMASK(15, 8) +#define HTT_H2T_SAWF_DEF_Q_UMAP_SVC_ID GENMASK(15, 8) +#define HTT_H2T_SAWF_DEF_Q_MAP_PEER_ID GENMASK(31, 16) +#define HTT_H2T_SAWF_DEF_Q_UMAP_PEER_ID GENMASK(31, 16) +#define HTT_H2T_SAWF_DEF_Q_MAP_TID_MASK_ID GENMASK(15, 8) +#define HTT_H2T_SAWF_DEF_Q_MAP_ETO_ID BIT(0) +/* MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ + * + * @details + * The SAWF_DEF_QUEUES_UNMAP_REQ message is sent by the host to + * remove the linkage of the specified peer-TID's MSDU queues to + * service classes. + * + * |31 16|15 8|7 0| + * |------------------------------+--------------+--------------| + * | peer ID | svc class ID | msg type | + * |------------------------------------------------------------| + * Header fields: + * dword0 - b'7:0 - msg_type: This will be set to + * 0x1d (HTT_H2T_SAWF_DEF_QUEUES_UNMAP_REQ) + * b'15:8 - service class ID + * b'31:16 - peer ID + * A HTT_H2T_SAWF_DEF_QUEUES_UNMAP_PEER_ID_WILDCARD + * value for peer ID indicates that the target should + * apply the UNMAP_REQ to all peers. + */ +struct ath12k_htt_h2t_sawf_def_q_unmap_req { + u32 info; +}; + +/* MSG_TYPE => HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ + * + * @details + * The SAWF_DEF_QUEUES_MAP_REPORT_REQ message is sent by the host to + * request the target to report what service class the default MSDU queues + * of the specified TIDs within the peer are linked to. + * The target will respond with a SAWF_DEF_QUEUES_MAP_REPORT_CONF message + * to report what service class (if any) the default MSDU queues for + * each of the specified TIDs are linked to. + * + * |31 16|15 8|7 1| 0| + * |------------------------------+--------------+--------------| + * | peer ID | TID mask | msg type | + * |------------------------------------------------------------| + * | reserved |ETO| + * |------------------------------------------------------------| + * Header fields: + * dword0 - b'7:0 - msg_type: This will be set to + * 0x1e (HTT_H2T_SAWF_DEF_QUEUES_MAP_REPORT_REQ) + * b'15:8 - TID mask + * b'31:16 - peer ID + * dword1 - b'0 - "Existing Tids Only" flag + * If this flag is set, the DEF_QUEUES_MAP_REPORT_CONF + * message generated by this REQ will only show the + * mapping for TIDs that actually exist in the target's + * peer object. + * Any TIDs that are covered by a MAP_REQ but which + * do not actually exist will be shown as being + * unmapped (i.e. svc class ID 0xff). + * If this flag is cleared, the MAP_REPORT_CONF message + * will consider not only the mapping of TIDs currently + * existing in the peer, but also the mapping that will + * be applied for any TID objects created within this + * peer in the future. + * b'31:1 - reserved for future use + */ +struct ath12k_htt_h2t_sawf_def_q_map_report_req { + u32 info; + u32 info1; +}; + +#define HTT_T2H_SAWF_Q_MAP_REPORT_INFO0_PEER_ID GENMASK(31, 16) +#define HTT_T2H_SAWF_Q_MAP_REPORT_TID_ID GENMASK(7, 0) +#define HTT_T2H_SAWF_Q_MAP_REPORT_SVC_ID GENMASK(15, 8) + +#define HTT_SAWF_SVC_CLASS_INVALID_ID 0xff + +struct ath12k_htt_t2h_sawf_q_map_report { + u32 info; + u32 tid_report[ATH12K_SAWF_MAX_TID_SUPPORT]; //MAX_TIDT +} __packed; + +/** + * struct wmi_peer_latency_info_params - peer latency info params + * @peer_mac: peer mac address + * @service_interval: service interval in miliseconds + * @burst_size: burst size in bytes + * @latency_tid: tid associated with this latency information + * @ac: Access Category associated with this tid + * @ul_enable: Bit to indicate ul latency enable + * @dl_enable: Bit to indicate dl latency enable + * @flow_id: Flow id associated with tid + * @add_or_sub: Bit to indicate add/delete of latency params + * @sawf_ul_param: Bit to indicate if UL params are for SAWF/SCS + * @max_latency: Maximum latency in milliseconds + * @min_throughput: Minimum throughput in Kbps + */ +struct ath12k_sawf_wmi_peer_latency_param { + u8 svc_id; + u8 peer_mac[ETH_ALEN]; + u32 service_interval; + u32 burst_size; + u32 latency_tid :8, + ac :2, + ul_enable :1, + dl_enable :1, + flow_id :4, + add_or_sub :2, + sawf_ul_param :1, + ofdma_disable :1, + mu_mimo_disable :1, + reserved :11; + u32 max_latency; + u32 min_throughput; +}; + +#define LATENCY_TID_INFO_TID_NUM GENMASK(7, 0) +#define LATENCY_TID_INFO_AC GENMASK(9, 8) +#define LATENCY_TID_INFO_DL_EN BIT(10) +#define LATENCY_TID_INFO_UL_EN BIT(11) +#define LATENCY_TID_INFO_BURST_SZ_SUM GENMASK(13, 12) +#define LATENCY_TID_INFO_MSDUQ_ID GENMASK(17, 14) +#define LATENCY_TID_INFO_UL_OFDMA_DISABLE BIT(18) +#define LATENCY_TID_INFO_UL_MU_MIMO_DISABLE BIT(19) +#define LATENCY_TID_INFO_SAWF_UL_PARAM BIT(20) + +/* struct wmi_peer_tid_latency_config_fixed_param: + * Currently wmi_peer_tid_set_latency_request_fixed_param will be sent + * per TID per latency configured client. + * In future this command might come for multiple latency configured + * clients together. + * The clients are expected to be associated while receiving this command. + * @tlv_header + * TLV tag and len; + * @pdev_id + * device ID + */ +struct wmi_peer_tid_latency_config_fixed_param { + __le32 tlv_header; + __le32 pdev_id; +} __packed; + +/** struct wmi_tid_latency_info + * @tlv_header: + * TLV Tag and Len + * @wmi_mac_addr destmac + * Mac address of end client + * @service_interval + * Maximum expected average delay between 2 schedules in milliseconds + * of given TID type when it has active traffic. + * 0x0 is considered as invalid service interval. + * @burst_size_diff + * Cumulative number of bytes are expected to be transmitted or + * received in the service interval when this specific Peer-TID + * has active traffic. + * If cumulative number of bytes is 0x0, it is considered as + * invalid burst size. In that case, firmware would try to transmit + * and receive as many bytes as it can for this specific Peer-TID. + * This burst size will be added or subtracted from vdev burst size + * based on burst size sum bit in latency tid info. + * The VDEV burst size will be considered to be 0 when no VDEV latency + * command is received. + * If host needs to set burst size for a peer then they can use the + * peer cmd and set burst size sum bit to 1. + * @max_latency + * The maximum end to end latency expectation, in milliseconds. + * If this value is 0x0, it shall be ignored. + * @max_per + * The maximum PER (as a percent) for the peer-TID, in range 1 - 100 + * If this value is 0x0, it shall be ignored. + * @min_tput + * The minimum guaranteed throughput to the peer-TID, in Kbps. + * If this value is 0x0, it shall be ignored. + * @latency_tid_info + * Bits 21-31 - Reserved (Shall be zero) + * Bit 20 - Flag to indicate SAWF UL params (and not mesh latenc + * Bit 19 - Disable UL MU-MIMO. If set, UL MU-MIMO is disabled + * for the specified AC. Note that TID level control is + * not possible for UL MU-MIMO (the granularity is AC). + * Bit 18 - Disable UL OFDMA. If set, UL OFDMA is disabled for + * the specified AC. Note that TID level control is not + * possible for UL OFDMA (the granularity is AC). + * Bits 14-17 - MSDU queue flow id within the TID for configuring + * latency info per MSDU flow queue + * Bit 12-13 - burst size sum. Bit to indicate whether to add or + * subtract burst_size_diff from vdev cmd burst size: + * 1 -> addition + * 2 -> subtraction + * Bit 11 - UL latency config indication. + * If this bit is set then this latency info will + * be used when triggering UL traffic. Until the + * AC specified in bits 8-9 has transferred at least + * burst_size amount of UL data within the service + * period, the AP will continue sending UL triggers + * when the STA has data of the specified access + * category ready to transmit. + * Note that the TID specified in bits 0-7 does not + * apply to UL; the TID-to-AC mapping applied to DL + * data that can be adjusted by the TID specified + * in bits 0-7 and the AC specified in bits 8-9 is + * distinct from the TID-to-AC mapping applied to + * UL data. + * Bit 10 - DL latency config indication. If the bit is set + * then DL TID will use this latency config. + * Bits 8 - 9 - This bit has info on the custom AC of DL TID. + * Also if bit 11 is set, the AP will apply some + * of these latency specs (in particular, burst_size) + * to UL traffic for this AC, by sending UL triggers + * until the desired amount of data has been received + * within the service period. + * Bits 0 - 7 - Specifies the TID of interest that corresponds + * to the AC specified in bits 8-9. This can be + * used to adjust the TID-to-AC mapping applied to + * DL data (if bit 10 is set). + */ +struct wmi_tid_latency_info { + __le32 tlv_header; + struct wmi_mac_addr destmac; + __le32 service_interval; + __le32 burst_size_diff; + __le32 max_latency; + __le32 max_per; + __le32 min_tput; + __le32 latency_tid_info; +} __packed; + +/** + * ath12k_sawf_stats_level - sawf stats level + * @ATH12K_SAWF_STATS_BASIC : sawf basic stats + * @ATH12K_SAWF_STATS_ADVANCED : sawf advanced stats + * @ATH12K_SAWF_STATS_LATENCY : sawf latency stats + */ +enum ath12k_sawf_stats_level { + ATH12K_SAWF_STATS_BASIC = BIT(0), + ATH12K_SAWF_STATS_ADVNCD = BIT(1), + ATH12K_SAWF_STATS_LATENCY = BIT(2), +}; + +#define ATH12K_SAWF_STATS_MAX (ATH12K_SAWF_STATS_BASIC | ATH12K_SAWF_STATS_ADVNCD | ATH12K_SAWF_STATS_LATENCY) + +/** + * struct sawf_fw_mpdu_stats- per-mpdu Tx success/failure snapshot + * @success_cnt: count of pkts successfully transmitted + * @failure_cnt: count of pkts failed to transmit + */ +struct sawf_fw_mpdu_stats { + u64 success_cnt; + u64 failure_cnt; +}; + +/** + * struct dp_pkt_info - packet info + * @num: number of packets + * @bytes: total nunmber of bytes + */ +struct dp_pkt_info { + u32 num_pkts; + u64 bytes; +}; + +/** + * struct sawf_tx_stats- Tx stats + * @tx_success: transmit success stats + * @tx_ingress: enqueue success stats + * @dropped: detailed information for tx-drops + * @svc_intval_stats: success/failure stats per service-interval + * @burst_size_stats: success/failure stats per burst-size + * @tx_failed: tx failure count + * @queue_depth: transmit queue-depth + * @throughput: throughput + * @ingress_rate: ingress-rate + * @tid: tid used for transmit + * @msduq: MSDU queue used for transmit + */ +struct sawf_tx_stats { + struct dp_pkt_info tx_success; + struct dp_pkt_info tx_ingress; + struct { + struct dp_pkt_info fw_rem; + u32 fw_rem_notx; + u32 fw_rem_tx; + u32 age_out; + u32 fw_reason1; + u32 fw_reason2; + u32 fw_reason3; + } dropped; + struct sawf_fw_mpdu_stats svc_intval_stats; + struct sawf_fw_mpdu_stats burst_size_stats; + u32 tx_failed; + u32 queue_depth; + u32 throughput; + u32 ingress_rate; + u8 tid; + u8 msduq; +}; + +/** + * struct ath12k_delay_hist_stats - Histogram of a stats + * @max: Max frequency + * @min: Minimum frequency + * @avg: Average frequency + */ + +enum stats_if_hist_bucket_index { + HIST_BUCKET_0, + HIST_BUCKET_1, + HIST_BUCKET_2, + HIST_BUCKET_3, + HIST_BUCKET_4, + HIST_BUCKET_5, + HIST_BUCKET_6, + HIST_BUCKET_7, + HIST_BUCKET_8, + HIST_BUCKET_9, + HIST_BUCKET_10, + HIST_BUCKET_11, + HIST_BUCKET_12, + HIST_BUCKET_MAX, +}; + +enum stats_if_delay_bucket_index { + DELAY_BUCKET_0, + DELAY_BUCKET_1, + DELAY_BUCKET_2, + DELAY_BUCKET_3, + DELAY_BUCKET_4, + DELAY_BUCKET_5, + DELAY_BUCKET_6, + DELAY_BUCKET_7, + DELAY_BUCKET_8, + DELAY_BUCKET_9, + DELAY_BUCKET_10, + DELAY_BUCKET_11, + DELAY_BUCKET_12, + DELAY_BUCKET_MAX, +}; + +enum hist_types { + HIST_TYPE_SW_ENQEUE_DELAY, + HIST_TYPE_HW_COMP_DELAY, + HIST_TYPE_REAP_STACK, + HIST_TYPE_HW_TX_COMP_DELAY, + HIST_TYPE_MAX, +}; + +struct hist_bucket { + enum hist_types hist_type; + u64 freq[HIST_BUCKET_MAX]; +}; + +struct ath12k_delay_hist_stats { + struct hist_bucket hist; + int max; + int min; + int avg; +}; + +/** + * struct sawf_tx_delay_stats- sawf Tx-delay stats + * @delay_hist: histogram for various delay-buckets + * @nwdelay_avg: moving average for nwdelay + * @swdelay_avg: moving average for swdelay + * @hwdelay_avg: moving average for hwdelay + * @num_pkt: count of pkts for which delay is calculated + * @nwdelay_win_total: total nwdelay for a window + * @swdelay_win_total: total swdelay for a window + * @hwdelay_win_total: total hwdelay for a window + * @success: count of pkts that met delay-bound + * @failure: count of pkts that did not meet delay-bound + */ + +struct sawf_tx_delay_stats { + struct ath12k_delay_hist_stats delay_hist; + + u32 nwdelay_avg; + u32 swdelay_avg; + u32 hwdelay_avg; + u32 num_pkt; + u64 nwdelay_win_total; + u64 swdelay_win_total; + u64 hwdelay_win_total; + u64 success; + u64 failure; +}; +/** + * sawf_stats - sawf stats + * @delay: delay stats per host MSDU queue + * @tx_stats: Tx stats per host MSDU queue + * @lock: Protection for sawf-stats + */ +struct ath12k_sawf_stats { + struct sawf_tx_stats tx_stats[ATH12K_SAWF_MAX_TID_SUPPORT][MAX_Q_PER_TID]; + struct sawf_tx_delay_stats tx_delay_stats[ATH12K_SAWF_MAX_TID_SUPPORT][MAX_Q_PER_TID]; +}; + +/* MSG_TYPE => HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ + * + * @details + * The following field definitions describe the format of the HTT host + * to target message that requests the target to start or stop producing + * ongoing stats of the specified type. + * + * |31|30 |23 16|15 8|7 0| + * |-----------------------------------------------------------| + * |EN| reserved | stats type | reserved | msg type | + * |-----------------------------------------------------------| + * | config param [0] | + * |-----------------------------------------------------------| + * | config param [1] | + * |-----------------------------------------------------------| + * | config param [2] | + * |-----------------------------------------------------------| + * | config param [3] | + * |-----------------------------------------------------------| + * Where: + * - EN is an enable/disable flag + * Header fields: + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this is a streaming stats upload request message + * Value: 0x20 (HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ) + * - STATS_TYPE + * Bits 23:16 + * Purpose: identifies which FW statistics to upload + * Value: Defined values are HTT_STRM_GEN_MPDUS_STATS for basic + * stats and HTT_STRM_GEN_MPDUS_DETAILS_STAT for extended + * stats. + * - ENABLE + * Bit 31 + * Purpose: enable/disable the target's ongoing stats of the specified type + * Value: + * 0 - disable ongoing production of the specified stats type + * 1 - enable ongoing production of the specified stats type + * - CONFIG_PARAM [0] + * Bits 31:0 + * Purpose: give an opaque configuration value to the specified stats type + * Value: stats-type specific configuration value + * - CONFIG_PARAM [1] + * Bits 31:0 + * Purpose: give an opaque configuration value to the specified stats type + * Value: stats-type specific configuration value + * - CONFIG_PARAM [2] + * Bits 31:0 + * Purpose: give an opaque configuration value to the specified stats type + * Value: stats-type specific configuration value + * - CONFIG_PARAM [3] + * Bits 31:0 + * Purpose: give an opaque configuration value to the specified stats type + * Value: stats-type specific configuration value + */ + +#define HTT_STRM_GEN_MPDUS_STATS 43 +#define HTT_STRM_GEN_MPDUS_DETAILS_STATS 44 +#define HTT_H2T_MSG_TYPE_STREAMING_STATS_TYPE GENMASK(23,16) +#define HTT_H2T_MSG_TYPE_STREAMING_STATS_CONFIGURE BIT(31) + +struct ath12k_htt_h2t_sawf_streaming_req { + u32 info; + u32 config_param_0; + u32 config_param_1; + u32 config_param_2; + u32 config_param_3; +}; + +/** + * @brief target -> host streaming statistics upload + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_STREAMING_STATS_IND + * + * @details + * The following field definitions describe the format of the HTT target + * to host streaming stats upload indication message. + * The host can use a HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ message to enable + * the target to produce an ongoing series of HTT_T2H_MSG_TYPE_STREAMING_STATS_IND + * STREAMING_STATS_IND messages, and can also use the + * HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ message to halt the target's production of + * HTT_T2H_MSG_TYPE_STREAMING_STATS_IND messages. + * + * The HTT_T2H_MSG_TYPE_STREAMING_STATS_IND message contains a payload of TLVs + * containing the stats enabled by the host's HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ + * message. + * + * |31 8|7 0| + * |--------------------------------------------------------------| + * | reserved | msg type | + * |--------------------------------------------------------------| + * | type-specific stats info | + * |--------------------------------------------------------------| + * Header fields: + * - MSG_TYPE + * Bits 7:0 + * Purpose: Identifies this as a streaming statistics upload indication + * message. + * Value: 0x2f (HTT_T2H_MSG_TYPE_STREAMING_STATS_IND) + */ + +#define HTT_T2H_STREAMING_STATS_IND_HDR_SIZE 4 +#define SAWF_TTH_TID_MASK GENMASK(3,0) +#define SAWF_TTH_QTYPE_MASK GENMASK(7,4) + +struct htt_stats_strm_gen_mpdus_tlv { +/* + * |31 24|23 20|19 16|15 0| + * |---------+----------+----------+------------------------------| + * |Reserved | QTYPE | TID | Peer ID | + * |--------------------------------------------------------------| + * | svc interval failure | svc interval success | + * |--------------------------------------------------------------| + * | burst size failure | burst size success | + * |--------------------------------------------------------------| +*/ + __le16 peer_id; + __le16 info; + __le16 svc_interval_success; + __le16 svc_interval_failure; + __le16 burst_size_success; + __le16 burst_size_failure; +} __packed; + +struct htt_stats_strm_gen_mpdus_details_tlv { + __le16 peer_id; + __le16 info; + __le16 svc_interval_timestamp_prior_ms; + __le16 svc_interval_timestamp_now_ms; + __le16 svc_interval_interval_spec_ms; + __le16 svc_interval_interval_margin_ms; + /* consumed_bytes_orig: + * Raw count (actually estimate) of how many bytes were removed + * from the MSDU queue by the GEN_MPDUS operation. + */ + __le16 burst_size_consumed_bytes_orig; + /* consumed_bytes_final: + * Adjusted count of removed bytes that incorporates normalizing + * by the actual service interval compared to the expected + * service interval. + * This allows the burst size computation to be independent of + * whether the target is doing GEN_MPDUS at only the service + * interval, or substantially more often than the service + * interval. + * consumed_bytes_final = consumed_bytes_orig / + * (svc_interval / ref_svc_interval) + */ + __le16 burst_size_consumed_bytes_final; + __le16 burst_size_remaining_bytes; + __le16 burst_size_reserved; + __le16 burst_size_burst_size_spec; + __le16 burst_size_margin_bytes; +} __packed; + +extern bool ath12k_sawf_enable; +struct ath12k_sawf_ctx *ath12k_get_sawf_context(void); +void ath12k_sawf_init(struct ath12k_base *ab); +void ath12k_sawf_deinit(struct ath12k_base *ab); +bool ath12k_validate_sawf_param(struct ath12k_sawf_svc_params *params); +bool ath12k_svc_id_configured(u8 svc_id); +bool ath12k_svc_id_valid(u8 svc_id); +void ath12k_update_svc_class(struct ath12k_sawf_svc_params *sawf_params); +bool ath12k_disable_svc_class(u8 svc_id); +int ath12k_get_tid(u8 svc_id); +int ath12k_sawf_reconfigure_on_crash(struct ath12k_base *ab); +int ath12k_create_send_svc_params(struct ath12k_sawf_svc_params *param); +int ath12k_sawf_disable_config(u8 svc_id); +void ath12k_send_ul_configs(struct work_struct *work); +u16 ath12k_sawf_get_msduq(struct net_device *netdev, + u8 *peer_mac, u32 service_id, + u32 dscp, u32 rule_id); +void ath12k_sawf_config_ul(struct net_device *dest_dev, u8 *dst_mac, struct net_device *src_dev, u8 *src_mac, + u8 fw_service_id, u8 rv_service_id, + u8 add_or_sub); +int ath12k_sawf_wmi_config_ul(struct ath12k_base *ab, + struct ath12k_sawf_wmi_peer_latency_param *latency_info); +struct ath12k_base *ath12k_sawf_get_ab_from_netdev(struct net_device *dev, + u8 *peer_mac, + u16 *peer_id); + +int ath12k_sawf_def_qmap_req(struct ath12k_base *ab, + u8 svc_id, u16 peer_id); +int ath12k_sawf_def_qunmap_req(struct ath12k_base *ab, + u8 svc_id, u16 peer_id); +int ath12k_sawf_def_qmap_report_req(struct ath12k_base *ab, + u16 peer_id); + +void ath12k_htt_sawf_def_q_map_report_handler(struct ath12k_base *ab, + struct sk_buff *skb); +void ath12k_sawf_stats_update(struct ath12k *ar, struct sk_buff *skb, + struct hal_tx_status *ts, + struct ath12k_peer *peer, ktime_t timestamp); +void ath12k_sawf_tx_enqueue_peer_stats(struct ath12k_base *ab, + struct ath12k_peer *peer, + u32 msduq_id, u32 len); +int ath12k_htt_sawf_streaming_stats_configure(struct ath12k *ar, + u8 stats_type, + u8 configure, + u32 config_param_0, + u32 config_param_1, + u32 config_param_2, + u32 config_param_3); +void ath12k_htt_sawf_streaming_stats_ind_handler(struct ath12k_base *ab, + struct sk_buff *skb); +int telemetry_extract_data(struct stats_config *cfg, + struct telemetry_sawftx_stats *tx_stats, + struct telemetry_sawfdelay_stats *delay_stats, + struct ath12k_base *ab); +int ath12k_telemetry_sla_reset_stats(u8 svc_id, u8 *peer_mac, u8 *mld_mac_addr, + u8 set_clear); +int ath12k_telemetry_get_sawf_tx_stats_tput(void *ptr, void *stats, u64 *in_bytes, + u64 *in_cnt, u64 *tx_bytes, + u64 *tx_cnt, u8 tid_v, u8 msduq_id); +int ath12k_telemetry_get_sawf_tx_stats_mpdu(void *ptr, void *stats, u64 *svc_int_pass, + u64 *svc_int_fail, u64 *burst_pass, + u64 *burst_fail, u8 tid_v, u8 msduq_id); +int ath12k_telemetry_get_sawf_tx_stats_drop(void *ptr, void *stats, u64 *pass, + u64 *drop, u64 *drop_ttl, + u8 tid, u8 msduq_id); +void ath12k_telemetry_notify_breach(u8 *mac_addr, u8 svc_id, u8 param, + bool set_clear, u8 tid); +void ath12k_sdwf_fill_hbucket_type(struct ath12k_peer *peer); +#else /* CONFIG_ATH12K_SAWF */ + +static inline void ath12k_sawf_init(struct ath12k_base *ab) { + return; +} + +static inline void ath12k_sawf_deinit(struct ath12k_base *ab) { + return; +} + +static inline void ath12k_sawf_stats_update(struct ath12k *ar, struct sk_buff *skb, + struct hal_tx_status *ts, + struct ath12k_peer *peer, + ktime_t timestamp) +{ + return; +} +#endif /* CONFIG_ATH12K_SAWF */ +#endif /* ATH11K_SAWF_H */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/spectral.h 2024-01-19 17:01:19.873847249 +0100 @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef ATH12K_SPECTRAL_H +#define ATH12K_SPECTRAL_H + +#include "../spectral_common.h" +#include "dbring.h" + +/* enum ath12k_spectral_mode: + * + * @SPECTRAL_DISABLED: spectral mode is disabled + * @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with + * something else. + * @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples + * is performed manually. + */ +enum ath12k_spectral_mode { + ATH12K_SPECTRAL_DISABLED = 0, + ATH12K_SPECTRAL_BACKGROUND, + ATH12K_SPECTRAL_MANUAL, +}; + +struct ath12k_spectral { + struct ath12k_dbring rx_ring; + /* Protects enabled */ + spinlock_t lock; + struct rchan *rfs_scan; /* relay(fs) channel for spectral scan */ + struct dentry *scan_ctl; + struct dentry *scan_count; + struct dentry *scan_bins; + enum ath12k_spectral_mode mode; + u16 count; + u8 fft_size; + bool enabled; + bool is_primary; + u32 ch_width; + struct wmi_spectral_capabilities_event spectral_cap; +}; + +#ifdef CONFIG_ATH12K_SPECTRAL + +int ath12k_spectral_init(struct ath12k_base *ab); +void ath12k_spectral_deinit(struct ath12k_base *ab); +int ath12k_spectral_vif_stop(struct ath12k_link_vif *arvif); +void ath12k_spectral_reset_buffer(struct ath12k *ar); +enum ath12k_spectral_mode ath12k_spectral_get_mode(struct ath12k *ar); +struct ath12k_dbring *ath12k_spectral_get_dbring(struct ath12k *ar); + +#else + +static inline int ath12k_spectral_init(struct ath12k_base *ab) +{ + return 0; +} + +static inline void ath12k_spectral_deinit(struct ath12k_base *ab) +{ +} + +static inline int ath12k_spectral_vif_stop(struct ath12k_link_vif *arvif) +{ + return 0; +} + +static inline void ath12k_spectral_reset_buffer(struct ath12k *ar) +{ +} + +static inline +enum ath12k_spectral_mode ath12k_spectral_get_mode(struct ath12k *ar) +{ + return ATH12K_SPECTRAL_DISABLED; +} + +static inline +struct ath12k_dbring *ath12k_spectral_get_dbring(struct ath12k *ar) +{ + return NULL; +} + +#endif /* CONFIG_ATH12K_SPECTRAL */ +#endif /* ATH12K_SPECTRAL_H */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/telemetry.h 2024-01-19 17:01:19.873847249 +0100 @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef ATH12K_TELEMETRY_H +#define ATH12K_TELEMETRY_H + +#ifdef CONFIG_ATH12K_SAWF + +/** + * struct ath12k_sla_samples_cfg- telemetry sawf sla samples configuration + * @moving_avg_pkt: Number of packets per window to calculate moving average + * @moving_avg_win: Number of windows to calculate moving average + * @sla_num_pkt: Number of packets for SLA detection + * @sla_time_sec: Number of seconds for SLA detection + */ +struct ath12k_sla_samples_cfg { + u32 moving_avg_pkt; + u32 moving_avg_win; + u32 sla_num_pkt; + u32 sla_time_sec; +}; + +/** + * struct ath12k_sla_thershold_cfg- telemetry sawf sla + * thershold configuration + * @svc_id: service class id + * @min_throughput_rate: min throughput thershold percentage + * @max_throughput_rate: max throughput thershold percentage + * @burst_size: burst size thershold percentage + * @service_interval: service interval thershold percentage + * @delay_bound: delay bound thershold percentage + * @msdu_ttl: MSDU Time-To-Live thershold percentage + * @msdu_rate_loss: MSDU loss rate thershold percentage + */ +struct ath12k_sla_thershold_cfg { + u8 svc_id; + u32 min_throughput_rate; + u32 max_throughput_rate; + u32 burst_size; + u32 service_interval; + u32 delay_bound; + u32 msdu_ttl; + u32 msdu_rate_loss; +}; + + +/** + * struct ath12k_sla_detect- telemetry sawf sla + * sla breach detection option + * @SLA_DETECT_NUM_PACKET: Number of packets per window + * @SLA_DETECT_PER_SECOND: Number of windows + * @SLA_DETECT_MOV_AVG: Number of packets to calculate + * moving average for SLA detection + * @SLA_DETECT_NUM_SECOND: Number of seconds for SLA detection + */ +enum ath12k_sla_detect { + SLA_DETECT_NUM_PACKET, + SLA_DETECT_PER_SECOND, + SLA_DETECT_MOV_AVG, + SLA_DETECT_NUM_SECOND, + SLA_DETECT_MAX, +}; + +/** + * struct ath12k_sla_detect_cfg- telemetry sawf sla + * breach detection configuration + * @sla_detect: sla detection option + * @min_throughput_rate: min throughput thershold percentage + * @max_throughput_rate: max throughput thershold percentage + * @burst_size: burst size thershold percentage + * @service_interval: service interval thershold percentage + * @delay_bound: delay bound thershold percentage + * @msdu_ttl: MSDU Time-To-Live thershold percentage + * @msdu_rate_loss: MSDU loss rate thershold percentage + */ +struct ath12k_sla_detect_cfg { + enum ath12k_sla_detect sla_detect; + u32 min_throughput_rate; + u32 max_throughput_rate; + u32 burst_size; + u32 service_interval; + u32 delay_bound; + u32 msdu_ttl; + u32 msdu_rate_loss; +}; + +/** + * struct ath12k_telemetry_ctx- Telemetry context + */ +struct ath12k_telemetry_ctx { + struct ath12k_sla_samples_cfg sla_samples_params; + struct ath12k_sla_thershold_cfg sla_thershold_params; + struct ath12k_sla_detect_cfg sla_detect_params; +}; + +void ath12k_telemetry_init(struct ath12k_base *ab); +void ath12k_telemetry_deinit(struct ath12k_base *ab); +struct ath12k_telemetry_ctx *get_telemetry_context(void); +int ath12k_telemetry_sawf_sla_samples_config(struct ath12k_sla_samples_cfg param); +int ath12k_telemetry_sawf_sla_thershold_config(struct ath12k_sla_thershold_cfg param); +int ath12k_telemetry_sawf_sla_detection_config(struct ath12k_sla_detect_cfg param); +bool ath12k_telemetry_get_sla_num_pkts(u32 *pkt_num); +bool ath12k_telemetry_get_sla_mov_avg_num_pkt(u32 *mov_avg); +#else /* CONFIG_ATH12K_SAWF */ + +static inline void ath12k_telemetry_init(struct ath12k_base *ab) { + return; +} + +static inline void ath12k_telemetry_deinit(struct ath12k_base *ab) { + return; +} + +#endif /* CONFIG_ATH12K_SAWF */ +#endif /* ATH12K_TELEMETRY_H */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/telemetry_agent_if.h 2024-01-19 17:01:19.873847249 +0100 @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef ATH12K_TELEMETRY_AGENT_IF_H +#define ATH12K_TELEMETRY_AGENT_IF_H + +u32 ath12k_telemetry_agent_init(void); +u32 ath12k_telemetry_agent_deinit(void); + +int ath12k_sawf_get_tput_stats(void *soc, void *arg, u64 *in_bytes, + u64 *in_cnt, u64 *tx_bytes, + u64 *tx_cnt, u8 tid, u8 msduq); +int ath12k_sawf_get_mpdu_stats(void *soc, void *arg, u64 *svc_int_pass, + u64 *svc_int_fail, u64 *burst_pass, + u64 *burst_fail, u8 tid, u8 msduq); +int ath12k_sawf_get_drop_stats(void *soc, void *arg, u64 *pass, + u64 *drop, u64 *drop_ttl, + u8 tid, u8 msduq); +void ath12k_sawf_notify_breach(u8 *mac_addr, u8 svc_id, u8 param, + bool set_clear, u8 tid); +void *ath12k_telemetry_peer_ctx_alloc(void *peer, void *sawf_stats, + u8 *mac_addr, + u8 svc_id, u8 hostq_id); +void ath12k_telemetry_peer_ctx_free(void *telemetry_peer_ctx); +bool ath12k_telemetry_update_tid_msduq(void *telemetry_peer_ctx, + u8 hostq_id, u8 tid, u8 msduq_idx); +bool ath12k_telemetry_set_mov_avg_params(u32 num_pkt, u32 num_win); +bool ath12k_telemetry_set_sla_params(u32 num_pkt, u32 time_sec); +bool ath12k_telemetry_set_sla_cfg(u8 svc_id, u8 min_tput_rate, u8 max_tput_rate, + u8 burst_size, u8 svc_interval, u8 delay_bound, + u8 msdu_ttl, u8 msdu_rate_loss); +bool ath12k_telemetry_set_svclass_cfg(bool enable, u8 svc_id, + u32 min_tput_rate, + u32 max_tput_rate, + u32 burst_size, + u32 svc_interval, + u32 delay_bound, + u32 msdu_ttl, + u32 msdu_rate_loss); +bool ath12k_telemetry_set_sla_detect_cfg(u8 detect_type, + u8 min_tput_rate, + u8 max_tput_rate, + u8 burst_size, + u8 svc_interval, + u8 delay_bound, + u8 msdu_ttl, + u8 msdu_rate_loss); +bool ath12k_telemetry_update_delay(void *telemetry_ctx, u8 tid, + u8 queue, u64 pass, u64 fail); +bool ath12k_telemetry_update_delay_mvng(void *telemetry_ctx, + u8 tid, u8 queue, + u64 nwdelay_winavg, + u64 swdelay_winavg, + u64 hwdelay_winavg); +bool ath12k_telemetry_update_msdu_drop(void *telemetry_ctx, u8 tid, + u8 queue, u64 success, + u64 failure_drop, + u64 failure_ttl); +bool ath12k_telemetry_get_rate(void *telemetry_ctx, u8 tid, u8 queue, + u32 *egress_rate, u32 *ingress_rate); +bool ath12k_telemetry_get_mov_avg(void *telemetry_ctx, u8 tid, u8 queue, + u32 *nwdelay_avg, u32 *swdelay_avg, + u32 *hwdelay_avg); +int ath12k_telemetry_reset_peer_stats(u8 *peer_mac); +#endif /* ATH12K_TELEMETRY_AGENT_IF_H */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/testmode.c 2024-01-19 17:01:19.877847358 +0100 @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "testmode.h" +#include +#include "debug.h" +#include "wmi.h" +#include "hw.h" +#include "core.h" +#include "hif.h" +#include "testmode_i.h" + +#define ATH12K_FTM_SEGHDR_CURRENT_SEQ GENMASK(3, 0) +#define ATH12K_FTM_SEGHDR_TOTAL_SEGMENTS GENMASK(7, 4) + +static const struct nla_policy ath12k_tm_policy[ATH12K_TM_ATTR_MAX + 1] = { + [ATH12K_TM_ATTR_CMD] = { .type = NLA_U32 }, + [ATH12K_TM_ATTR_DATA] = { .type = NLA_BINARY, + .len = ATH12K_TM_DATA_MAX_LEN }, + [ATH12K_TM_ATTR_WMI_CMDID] = { .type = NLA_U32 }, + [ATH12K_TM_ATTR_VERSION_MAJOR] = { .type = NLA_U32 }, + [ATH12K_TM_ATTR_VERSION_MINOR] = { .type = NLA_U32 }, + [ATH12K_TM_ATTR_FWLOG] = { .type = NLA_BINARY, + .len = 2048 }, + [ATH12K_TM_ATTR_LINK_IDX] = { .type = NLA_U8 }, + [ATH12K_TM_ATTR_DUAL_MAC] = { .type = NLA_U8 }, +}; + +void ath12k_fwlog_write(struct ath12k_base *ab, u8 *data, int len) +{ + struct sk_buff *nl_skb; + int ret, i; + struct ath12k *ar = NULL; + struct ath12k_pdev *pdev; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + if (pdev && pdev->ar) { + ar = pdev->ar; + break; + } + } + + if (!ar) + return; + + nl_skb = cfg80211_testmode_alloc_event_skb(ar->ah->hw->wiphy, len, GFP_ATOMIC); + + if (!nl_skb) { + ath12k_warn(ab, "failed to allocate skb for fwlog event\n"); + return; + } + + ret = nla_put(nl_skb, ATH12K_TM_ATTR_FWLOG, len, data); + if (ret) { + ath12k_warn(ab, "failed to put fwlog wmi event to nl: %d\n", ret); + kfree_skb(nl_skb); + return; + } + + if (ab->ag->mlo_capable) { + ret = nla_put_u8(nl_skb, ATH12K_TM_ATTR_LINK_IDX, ar->link_idx); + if (ret) { + ath12k_warn(ab, "failed to put link idx wmi event to nl: %d\n", ret); + kfree_skb(nl_skb); + return; + } + } + + if (ab->num_radios == 2) + ret = nla_put_u8(nl_skb, ATH12K_TM_ATTR_DUAL_MAC, ab->num_radios); + + if (ret) { + ath12k_warn(ab, "failed to put dual mac wmi event to nl: %d\n", ret); + kfree_skb(nl_skb); + return; + } + + cfg80211_testmode_event(nl_skb, GFP_ATOMIC); +} + +/* Returns true if callee consumes the skb and the skb should be discarded. + * Returns false if skb is not used. Does not sleep. + */ +struct ath12k *ath12k_tm_get_ar(struct ath12k_base *ab) +{ + struct ath12k_pdev *pdev; + struct ath12k *ar = NULL; + int i; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + if (ar) { + if (ar->state == ATH12K_STATE_TM) + break; + } + } + return ar; +} +/* This function handles unsegmented events. Data in various events are aggregated +* in application layer, this event is unsegmented from host perspective. +*/ +void ath12k_tm_wmi_event_unsegmented(struct ath12k_base *ab, u32 cmd_id, struct sk_buff *skb) +{ + struct sk_buff *nl_skb; + struct ath12k *ar; + + ath12k_dbg(ab, ATH12K_DBG_TESTMODE, + "testmode event wmi cmd_id %d skb length %d\n", + cmd_id, skb->len); + + ath12k_dbg_dump(ab, ATH12K_DBG_TESTMODE, NULL, "", skb->data, skb->len); + + ar = ath12k_tm_get_ar(ab); + if (!ar) { + ath12k_warn(ab, "testmode event not handled due to invalid pdev\n"); + return; + } + + spin_lock_bh(&ar->data_lock); + + + nl_skb = cfg80211_testmode_alloc_event_skb(ar->ah->hw->wiphy, + 2 * nla_total_size(sizeof(u32)) + + nla_total_size(skb->len), + GFP_ATOMIC); + if (!nl_skb) { + ath12k_warn(ab, + "failed to allocate skb for testmode wmi event\n"); + goto out; + } + if (nla_put_u32(nl_skb, ATH12K_TM_ATTR_CMD, ATH12K_TM_CMD_WMI) || + nla_put_u32(nl_skb, ATH12K_TM_ATTR_WMI_CMDID, cmd_id) || + nla_put(nl_skb, ATH12K_TM_ATTR_DATA, skb->len, skb->data)) { + ath12k_warn(ab, "failed to populate testmode unsegmented event\n"); + kfree_skb(nl_skb); + goto out; + } + + + cfg80211_testmode_event(nl_skb, GFP_ATOMIC); + spin_unlock_bh(&ar->data_lock); + return; + +out: + spin_unlock_bh(&ar->data_lock); + ath12k_warn(ab, "Failed to send testmode event to higher layers\n"); +} + +/* This function handles segmented events. +* Data of various events received from fw is aggregated and +* sent to application layer +*/ +int ath12k_tm_process_event(struct ath12k_base *ab, u32 cmd_id, + const struct wmi_ftm_event_msg *ftm_msg, + u16 length) +{ + struct sk_buff *nl_skb; + int ret = 0; + struct ath12k *ar; + u8 const *buf_pos; + u16 datalen; + u8 total_segments, current_seq; + u32 data_pos; + u32 pdev_id; + + ath12k_dbg(ab, ATH12K_DBG_TESTMODE, + "testmode event wmi cmd_id %d ftm event msg %pK datalen %d\n", + cmd_id, ftm_msg, length); + ath12k_dbg_dump(ab, ATH12K_DBG_TESTMODE, NULL, "", ftm_msg, length); + pdev_id = DP_HW2SW_MACID(ftm_msg->seg_hdr.pdev_id); + + if (pdev_id >= ab->num_radios) { + ath12k_warn(ab, "testmode event not handled due to invalid pdev id\n"); + return -EINVAL; + } + + ar = ab->pdevs[pdev_id].ar; + if (!ar) { + ath12k_warn(ab, "testmode event not handled due to absence of pdev\n"); + return -ENODEV; + } + + current_seq = FIELD_GET(ATH12K_FTM_SEGHDR_CURRENT_SEQ, + ftm_msg->seg_hdr.segmentinfo); + total_segments = FIELD_GET(ATH12K_FTM_SEGHDR_TOTAL_SEGMENTS, + ftm_msg->seg_hdr.segmentinfo); + datalen = length - (sizeof(struct wmi_ftm_seg_hdr)); + buf_pos = ftm_msg->data; + + spin_lock_bh(&ar->data_lock); + if (current_seq == 0) { + ab->ftm_event_obj.expected_seq = 0; + ab->ftm_event_obj.data_pos = 0; + } + + data_pos = ab->ftm_event_obj.data_pos; + + if ((data_pos + datalen) > ATH12K_FTM_EVENT_MAX_BUF_LENGTH) { + ath12k_warn(ab, + "Invalid event length date_pos[%d] datalen[%d]\n", + data_pos, datalen); + goto out; + } + + memcpy(&ab->ftm_event_obj.eventdata[data_pos], buf_pos, datalen); + data_pos += datalen; + + if (++ab->ftm_event_obj.expected_seq != total_segments) { + ab->ftm_event_obj.data_pos = data_pos; + ath12k_dbg(ab, ATH12K_DBG_TESTMODE, + "partial data received current_seq[%d], total_seg[%d]\n", + current_seq, total_segments); + goto out; + } + + ath12k_dbg(ab, ATH12K_DBG_TESTMODE, + "total data length[%d] = [%d]\n", + data_pos, ftm_msg->seg_hdr.len); + nl_skb = cfg80211_testmode_alloc_event_skb(ar->ah->hw->wiphy, + 2 * nla_total_size(sizeof(u32)) + + nla_total_size(data_pos), + GFP_ATOMIC); + if (!nl_skb) { + ath12k_warn(ab, + "failed to allocate skb for testmode wmi event\n"); + goto out; + } + + if (nla_put_u32(nl_skb, ATH12K_TM_ATTR_CMD, + ATH12K_TM_CMD_WMI_FTM) || + nla_put_u32(nl_skb, ATH12K_TM_ATTR_WMI_CMDID, cmd_id) || + nla_put(nl_skb, ATH12K_TM_ATTR_DATA, data_pos, + &ab->ftm_event_obj.eventdata[0])) { + ath12k_warn(ab, "failed to populate testmode event"); + kfree_skb(nl_skb); + goto out; + } + + cfg80211_testmode_event(nl_skb, GFP_ATOMIC); +out: + spin_unlock_bh(&ar->data_lock); + return ret; + +} +static int ath12k_tm_cmd_get_version(struct ath12k *ar, struct nlattr *tb[]) +{ + struct sk_buff *skb; + int ret; + + ath12k_dbg(ar->ab, ATH12K_DBG_TESTMODE, + "testmode cmd get version_major %d version_minor %d\n", + ATH12K_TESTMODE_VERSION_MAJOR, + ATH12K_TESTMODE_VERSION_MINOR); + + skb = cfg80211_testmode_alloc_reply_skb(ar->ah->hw->wiphy, + nla_total_size(sizeof(u32))); + if (!skb) + return -ENOMEM; + + if (nla_put_u32(skb, ATH12K_TM_ATTR_VERSION_MAJOR, + ATH12K_TESTMODE_VERSION_MAJOR) || + nla_put_u32(skb, ATH12K_TM_ATTR_VERSION_MINOR, + ATH12K_TESTMODE_VERSION_MINOR)) { + kfree_skb(skb); + return ret; + } + + return cfg80211_testmode_reply(skb); +} + +static int ath12k_tm_cmd_testmode_start(struct ath12k *ar, struct nlattr *tb[]) +{ + int ret; + ath12k_dbg(ar->ab, ATH12K_DBG_TESTMODE, " enter testmode cmd fw start\n"); + mutex_lock(&ar->conf_mutex); + + if (ar->state == ATH12K_STATE_TM) { + ret = -EALREADY; + goto err; + } + + /* start utf only when the driver is not in use */ + if (ar->state != ATH12K_STATE_OFF) { + ret = -EBUSY; + goto err; + } + + ar->ab->ftm_event_obj.eventdata = + kzalloc(ATH12K_FTM_EVENT_MAX_BUF_LENGTH, GFP_KERNEL); + if (!ar->ab->ftm_event_obj.eventdata) { + ret = -ENOMEM; + goto err; + } + + ar->state = ATH12K_STATE_TM; + ar->ftm_msgref = 0; + mutex_unlock(&ar->conf_mutex); + ath12k_dbg(ar->ab, ATH12K_DBG_TESTMODE, " enter testmode cmd started\n"); + return 0; +err: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static int ath12k_tm_cmd_wmi(struct ath12k *ar, struct nlattr *tb[], + struct ieee80211_vif *vif, u8 link_id) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct sk_buff *skb; + struct ath12k_vif *ahvif; + struct ath12k_link_vif *arvif; + struct ath12k_hw *ah = ar->ah; + u32 cmd_id, buf_len; + int ret, tag; + void *buf; + u32 *ptr; + + mutex_lock(&ar->conf_mutex); + + if (!tb[ATH12K_TM_ATTR_DATA]) { + ret = -EINVAL; + goto out; + } + + if (!tb[ATH12K_TM_ATTR_WMI_CMDID]) { + ret = -EINVAL; + goto out; + } + + buf = nla_data(tb[ATH12K_TM_ATTR_DATA]); + buf_len = nla_len(tb[ATH12K_TM_ATTR_DATA]); + if (!buf_len) { + ath12k_warn(ar->ab, "No data present in testmode command\n"); + ret = -EINVAL; + goto out; + } + cmd_id = nla_get_u32(tb[ATH12K_TM_ATTR_WMI_CMDID]); + + ptr = (u32 *)buf; + tag = FIELD_GET(WMI_TLV_TAG, *ptr); + ptr++; + + if (tag == WMI_TAG_PDEV_SET_PARAM_CMD) + *ptr = ar->pdev->pdev_id; + + if (ar->ab->fw_mode != ATH12K_FIRMWARE_MODE_FTM && + (tag == WMI_TAG_VDEV_SET_PARAM_CMD || tag == WMI_TAG_UNIT_TEST_CMD)) { + if (vif) { + mutex_lock(&ah->conf_mutex); + ahvif = (struct ath12k_vif *)vif->drv_priv; + arvif = ahvif->link[link_id]; + if (!arvif) { + ath12k_warn(ar->ab, "failed to find link interface\n"); + mutex_unlock(&ah->conf_mutex); + ret = -EINVAL; + goto out; + } + *ptr = arvif->vdev_id; + mutex_unlock(&ah->conf_mutex); + } + else { + ret = -EINVAL; + ath12k_warn(ar->ab, "vdev is not up for given vdev id, so failed to send wmi command (testmode): %d\n", + ret); + goto out; + } + } + + ath12k_dbg(ar->ab, ATH12K_DBG_TESTMODE, + "testmode cmd wmi cmd_id %d buf length %d\n", + cmd_id, buf_len); + + ath12k_dbg_dump(ar->ab, ATH12K_DBG_TESTMODE, NULL, "", buf, buf_len); + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, buf_len); + if (!skb) { + ret = -ENOMEM; + goto out; + } + + memcpy(skb->data, buf, buf_len); + + ret = ath12k_wmi_cmd_send(wmi, skb, cmd_id); + if (ret) { + dev_kfree_skb(skb); + ath12k_warn(ar->ab, "failed to transmit wmi command (testmode): %d\n", + ret); + goto out; + } + + ret = 0; + +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static int ath12k_tm_cmd_process_ftm(struct ath12k *ar, struct nlattr *tb[]) +{ + struct ath12k_wmi_pdev *wmi = ar->wmi; + struct sk_buff *skb; + u32 cmd_id, buf_len, hdr_info; + int ret; + void *buf; + + /* if buf_len is 0 no data is sent, return error */ + u8 segnumber = 0, seginfo; + u16 chunk_len, total_bytes, num_segments; + u8 *bufpos; + struct wmi_ftm_cmd *ftm_cmd; + mutex_lock(&ar->conf_mutex); + ath12k_dbg(ar->ab, ATH12K_DBG_TESTMODE, "ar->state %d\n", ar->state); + if (ar->state != ATH12K_STATE_TM) { + ret = -ENETDOWN; + goto out; + } + + if (!tb[ATH12K_TM_ATTR_DATA]) { + ret = -EINVAL; + goto out; + } + + buf = nla_data(tb[ATH12K_TM_ATTR_DATA]); + buf_len = nla_len(tb[ATH12K_TM_ATTR_DATA]); + cmd_id = WMI_PDEV_UTF_CMDID; + ath12k_dbg(ar->ab, ATH12K_DBG_TESTMODE, + "testmode cmd wmi cmd_id %d buf %pK buf_len %d\n", + cmd_id, buf, buf_len); + ath12k_dbg_dump(ar->ab, ATH12K_DBG_TESTMODE, NULL, "", buf, buf_len); + bufpos = buf; + total_bytes = buf_len; + num_segments = total_bytes / MAX_WMI_UTF_LEN; + if (buf_len - (num_segments * MAX_WMI_UTF_LEN)) + num_segments++; + + while (buf_len) { + if (buf_len > MAX_WMI_UTF_LEN) + chunk_len = MAX_WMI_UTF_LEN; /* MAX message */ + else + chunk_len = buf_len; + + skb = ath12k_wmi_alloc_skb(wmi->wmi_ab, (chunk_len + + sizeof(struct wmi_ftm_cmd))); + + if (!skb) { + ret = -ENOMEM; + goto out; + } + + ftm_cmd = (struct wmi_ftm_cmd *)skb->data; + hdr_info = FIELD_PREP(WMI_TLV_TAG, WMI_TAG_ARRAY_BYTE) | + FIELD_PREP(WMI_TLV_LEN, (chunk_len + + sizeof(struct wmi_ftm_seg_hdr))); + ftm_cmd->tlv_header = hdr_info; + ftm_cmd->seg_hdr.len = total_bytes; + ftm_cmd->seg_hdr.msgref = ar->ftm_msgref; + seginfo = FIELD_PREP(ATH12K_FTM_SEGHDR_TOTAL_SEGMENTS, num_segments) | + FIELD_PREP(ATH12K_FTM_SEGHDR_CURRENT_SEQ, segnumber); + ftm_cmd->seg_hdr.segmentinfo = seginfo; + segnumber++; + memcpy(&ftm_cmd->data, bufpos, chunk_len); + ret = ath12k_wmi_cmd_send(wmi, skb, cmd_id); + if (ret) { + ath12k_warn(ar->ab, "ftm wmi command fail: %d\n", ret); + goto out; + } + + buf_len -= chunk_len; + bufpos += chunk_len; + } + ++ar->ftm_msgref; + ret = 0; +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} +int ath12k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + /*u8 link_id, */void *data, int len) +{ + u8 link_id = 0; + struct ath12k_hw *ah = hw->priv; + struct ath12k *ar; + struct ath12k_base *ab; + struct nlattr *tb[ATH12K_TM_ATTR_MAX + 1]; + enum ath12k_tm_cmd cmd_type; + int ret = 0; + + + ret = nla_parse(tb, ATH12K_TM_ATTR_MAX, data, len, ath12k_tm_policy, + NULL); + if (ret) + return ret; + + if (!tb[ATH12K_TM_ATTR_CMD]) + return -EINVAL; + + cmd_type = nla_get_u32(tb[ATH12K_TM_ATTR_CMD]); + mutex_lock(&ah->conf_mutex); + + if (vif == NULL && (cmd_type == ATH12K_TM_CMD_WMI_FTM || + cmd_type == ATH12K_TM_CMD_TESTMODE_START || + cmd_type == ATH12K_TM_CMD_WMI)) { + if (ah->num_radio) + ar = ah->radio; + } else { + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + } + + if (!ar) { + ath12k_err(NULL, + "unable to determine device\n"); + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + + if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS) { + ath12k_warn(ar->ab, "invalid link id specified\n"); + mutex_unlock(&ah->conf_mutex); + return -EINVAL; + } + + ab = ar->ab; + mutex_unlock(&ah->conf_mutex); + + switch (cmd_type) { + case ATH12K_TM_CMD_WMI: + return ath12k_tm_cmd_wmi(ar, tb, vif, link_id); + case ATH12K_TM_CMD_TESTMODE_START: + return ath12k_tm_cmd_testmode_start(ar, tb); + case ATH12K_TM_CMD_GET_VERSION: + return ath12k_tm_cmd_get_version(ar, tb); + case ATH12K_TM_CMD_WMI_FTM: + set_bit(ATH12K_FLAG_FTM_SEGMENTED, &ab->dev_flags); + return ath12k_tm_cmd_process_ftm(ar, tb); + case ATH12K_TM_CMD_TESTMODE_STOP: + return 0; + default: + return -EOPNOTSUPP; + } +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/testmode.h 2024-01-19 17:01:19.877847358 +0100 @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include "core.h" +#include "hif.h" + +#ifdef CONFIG_NL80211_TESTMODE + +void ath12k_tm_wmi_event_unsegmented(struct ath12k_base *ab, u32 cmd_id, struct sk_buff *skb); +int ath12k_tm_process_event(struct ath12k_base *ab, u32 cmd_id, + const struct wmi_ftm_event_msg *ftm_msg, + u16 length); +int ath12k_tm_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, + /* u8 link_id, */void *data, int len); +void ath12k_fwlog_write(struct ath12k_base *ab, u8 *data, int len); +#else + +static inline void ath12k_tm_wmi_event_unsegmented(struct ath12k_base *ab, u32 cmd_id, + struct sk_buff *skb) +{ + return; +} + +static inline int ath12k_tm_process_event(struct ath12k_base *ab, u32 cmd_id, + const struct wmi_ftm_event_msg *msg, + u16 length) +{ + return 0; +} +static inline int ath12k_tm_cmd(struct ieee80211_hw *hw, + struct ieee80211_vif *vif, + /*u8 link_id, */void *data, int len) +{ + return 0; +} + +static inline void ath12k_fwlog_write(struct ath12k_base *ab, u8 *data, int len) +{ + +} +#endif --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/testmode_i.h 2024-01-19 17:01:19.877847358 +0100 @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* "API" level of the ath12k testmode interface. Bump it after every + * incompatible interface change. + */ +#define ATH12K_TESTMODE_VERSION_MAJOR 1 + +/* Bump this after every _compatible_ interface change, for example + * addition of a new command or an attribute. + */ +#define ATH12K_TESTMODE_VERSION_MINOR 0 + +#define ATH12K_TM_DATA_MAX_LEN 5000 +#define ATH12K_FTM_EVENT_MAX_BUF_LENGTH 2048 + +enum ath12k_tm_attr { + __ATH12K_TM_ATTR_INVALID = 0, + ATH12K_TM_ATTR_CMD = 1, + ATH12K_TM_ATTR_DATA = 2, + ATH12K_TM_ATTR_WMI_CMDID = 3, + ATH12K_TM_ATTR_VERSION_MAJOR = 4, + ATH12K_TM_ATTR_VERSION_MINOR = 5, + ATH12K_TM_ATTR_WMI_OP_VERSION = 6, + ATH12K_TM_ATTR_FWLOG = 7, + ATH12K_TM_ATTR_LINK_IDX = 8, + ATH12K_TM_ATTR_DUAL_MAC = 9, + + /* keep last */ + __ATH12K_TM_ATTR_AFTER_LAST, + ATH12K_TM_ATTR_MAX = __ATH12K_TM_ATTR_AFTER_LAST - 1, +}; + +/* All ath12k testmode interface commands specified in + * ATH12K_TM_ATTR_CMD + */ +enum ath12k_tm_cmd { + /* Returns the supported ath12k testmode interface version in + * ATH12K_TM_ATTR_VERSION. Always guaranteed to work. User space + * uses this to verify it's using the correct version of the + * testmode interface + */ + ATH12K_TM_CMD_GET_VERSION = 0, + + /* Boots the UTF firmware, the netdev interface must be down at thetime. */ + ATH12K_TM_CMD_TESTMODE_START = 1, + + /* Shuts down the UTF firmware and puts the driver back into OFFstate.*/ + ATH12K_TM_CMD_TESTMODE_STOP = 2, + + /* The command used to transmit a WMI command to the firmware and + * the event to receive WMI events from the firmware. Without + * struct wmi_cmd_hdr header, only the WMI payload. Command id is + * provided with ATH12K_TM_ATTR_WMI_CMDID and payload in + * ATH12K_TM_ATTR_DATA. + */ + ATH12K_TM_CMD_WMI = 3, + + /* The command used to transmit a FTM WMI command to the firmware + * and the event to receive WMI events from the firmware.The data + * received only contain the payload, Need to add the tlv + * header and send the cmd to fw with commandid WMI_PDEV_UTF_CMDID. + */ + ATH12K_TM_CMD_WMI_FTM = 4, +}; --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/thermal.c 2024-01-30 08:24:48.934651329 +0100 @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "core.h" +#include "debug.h" + +static int +ath12k_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + *state = ATH12K_THERMAL_THROTTLE_MAX; + + return 0; +} + +static int +ath12k_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, + unsigned long *state) +{ + struct ath12k *ar = cdev->devdata; + + mutex_lock(&ar->conf_mutex); + *state = ar->thermal.throttle_state; + mutex_unlock(&ar->conf_mutex); + + return 0; +} + +static int +ath12k_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, + unsigned long throttle_state) +{ + struct ath12k *ar = cdev->devdata; + int ret; + + if (throttle_state > ATH12K_THERMAL_THROTTLE_MAX) { + ath12k_warn(ar->ab, "throttle state %ld is exceeding the limit %d\n", + throttle_state, ATH12K_THERMAL_THROTTLE_MAX); + return -EINVAL; + } + mutex_lock(&ar->conf_mutex); + ret = ath12k_thermal_set_throttling(ar, throttle_state); + if (ret == 0) + ar->thermal.throttle_state = throttle_state; + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static const struct thermal_cooling_device_ops ath12k_thermal_ops = { + .get_max_state = ath12k_thermal_get_max_throttle_state, + .get_cur_state = ath12k_thermal_get_cur_throttle_state, + .set_cur_state = ath12k_thermal_set_cur_throttle_state, +}; + +static ssize_t ath12k_thermal_show_temp(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ath12k *ar = dev_get_drvdata(dev); + int ret, temperature; + unsigned long time_left; + + mutex_lock(&ar->conf_mutex); + + /* Can't get temperature when the card is off, unless in FTM mode */ + if (!ath12k_ftm_mode && ar->state != ATH12K_STATE_ON) { + ret = -ENETDOWN; + goto out; + } + + reinit_completion(&ar->thermal.wmi_sync); + ret = ath12k_wmi_send_pdev_temperature_cmd(ar); + if (ret) { + ath12k_warn(ar->ab, "failed to read temperature %d\n", ret); + goto out; + } + + if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) { + ret = -ESHUTDOWN; + goto out; + } + + time_left = wait_for_completion_timeout(&ar->thermal.wmi_sync, + ATH12K_THERMAL_SYNC_TIMEOUT_HZ); + if (!time_left) { + ath12k_warn(ar->ab, "failed to synchronize thermal read\n"); + ret = -ETIMEDOUT; + goto out; + } + + spin_lock_bh(&ar->data_lock); + temperature = ar->thermal.temperature; + spin_unlock_bh(&ar->data_lock); + + /* display in millidegree celcius */ + ret = snprintf(buf, PAGE_SIZE, "%d\n", temperature * 1000); +out: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +void ath12k_thermal_event_temperature(struct ath12k *ar, int temperature) +{ + spin_lock_bh(&ar->data_lock); + ar->thermal.temperature = temperature; + spin_unlock_bh(&ar->data_lock); + complete(&ar->thermal.wmi_sync); +} + +static SENSOR_DEVICE_ATTR(temp1_input, 0444, ath12k_thermal_show_temp, + NULL, 0); + +static struct attribute *ath12k_hwmon_attrs[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(ath12k_hwmon); + +int ath12k_thermal_set_throttling(struct ath12k *ar, u32 throttle_state) +{ + struct ath12k_base *sc = ar->ab; + struct ath12k_wmi_thermal_mitigation_arg param; + int ret = 0; + + lockdep_assert_held(&ar->conf_mutex); + + if (ar->state != ATH12K_STATE_ON) + return 0; + + memset(¶m, 0, sizeof(param)); + param.pdev_id = ar->pdev->pdev_id; + param.enable = throttle_state ? 1 : 0; + param.dc = ATH12K_THERMAL_DEFAULT_DUTY_CYCLE; + param.dc_per_event = 0xFFFFFFFF; + + param.levelconf[0].tmplwm = ATH12K_THERMAL_TEMP_LOW_MARK; + param.levelconf[0].tmphwm = ATH12K_THERMAL_TEMP_HIGH_MARK; + param.levelconf[0].dcoffpercent = throttle_state; + param.levelconf[0].priority = 0; /* disable all data tx queues */ + ret = ath12k_wmi_send_thermal_mitigation_cmd(ar, ¶m); + if (ret) { + ath12k_warn(sc, "failed to send thermal mitigation duty cycle %u ret %d\n", + throttle_state, ret); + } + return ret; +} + +int ath12k_thermal_register(struct ath12k_base *ab) +{ + struct thermal_cooling_device *cdev; + struct ath12k *ar; + struct ath12k_pdev *pdev; + struct ieee80211_hw *hw; + int i, ret; + char pdev_name[20]; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + if (!ar) + continue; + + hw = ar->ah->hw; + memset(pdev_name, 0, sizeof(pdev_name)); + + cdev = thermal_cooling_device_register("ath12k_thermal", ar, + &ath12k_thermal_ops); + + if (IS_ERR(cdev)) { + ath12k_err(ab, "failed to setup thermal device result: %ld\n", + PTR_ERR(cdev)); + ret = -EINVAL; + goto err_thermal_destroy; + } + + snprintf(pdev_name, sizeof(pdev_name), "%s%d", "cooling_device", + ar->link_idx); + + ar->thermal.cdev = cdev; + + ret = sysfs_create_link(&hw->wiphy->dev.kobj, &cdev->device.kobj, + pdev_name); + if (ret) { + ath12k_err(ab, "failed to create cooling device symlink\n"); + goto err_thermal_destroy; + } + + if (!IS_REACHABLE(CONFIG_HWMON)) + return 0; + + ar->thermal.hwmon_dev = hwmon_device_register_with_groups(&hw->wiphy->dev, + "ath12k_hwmon", ar, + ath12k_hwmon_groups); + if (IS_ERR(ar->thermal.hwmon_dev)) { + ath12k_err(ar->ab, "failed to register hwmon device: %ld\n", + PTR_ERR(ar->thermal.hwmon_dev)); + ar->thermal.hwmon_dev = NULL; + ret = -EINVAL; + goto err_thermal_destroy; + } + } + + return 0; + +err_thermal_destroy: + ath12k_thermal_unregister(ab); + return ret; +} + +void ath12k_thermal_unregister(struct ath12k_base *ab) +{ + struct ath12k *ar; + struct ath12k_pdev *pdev; + struct ieee80211_hw *hw; + int i; + char pdev_name[20]; + + for (i = 0; i < ab->num_radios; i++) { + pdev = &ab->pdevs[i]; + ar = pdev->ar; + if (!ar) + continue; + + hw = ar->ah->hw; + memset(pdev_name, 0, sizeof(pdev_name)); + + snprintf(pdev_name, sizeof(pdev_name), "%s%d", "cooling_device", + ar->link_idx); + + if (ar->thermal.hwmon_dev) { + hwmon_device_unregister(ar->thermal.hwmon_dev); + ar->thermal.hwmon_dev = NULL; + } + + sysfs_remove_link(&hw->wiphy->dev.kobj, pdev_name); + thermal_cooling_device_unregister(ar->thermal.cdev); + } +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/thermal.h 2024-01-19 17:01:19.877847358 +0100 @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _ATH12K_THERMAL_ +#define _ATH12K_THERMAL_ + +#define ATH12K_THERMAL_TEMP_LOW_MARK -100 +#define ATH12K_THERMAL_TEMP_HIGH_MARK 150 +#define ATH12K_THERMAL_THROTTLE_MAX 100 +#define ATH12K_THERMAL_DEFAULT_DUTY_CYCLE 100 +#define ATH12K_HWMON_NAME_LEN 15 +#define ATH12K_THERMAL_SYNC_TIMEOUT_HZ (5 * HZ) + +#define THERMAL_LEVELS 1 +struct thermal_mitigation_params { + u32 pdev_id; + u32 enable; + u32 dc; + u32 dc_per_event; + struct tt_level_config levelconf[THERMAL_LEVELS]; +}; + +struct ath12k_thermal { + struct thermal_cooling_device *cdev; + struct completion wmi_sync; + struct device *hwmon_dev; + + /* protected by conf_mutex */ + u32 throttle_state; + /* temperature value in Celcius degree + * protected by data_lock + */ + int temperature; +}; + +#if IS_REACHABLE(CONFIG_THERMAL) +int ath12k_thermal_register(struct ath12k_base *sc); +void ath12k_thermal_unregister(struct ath12k_base *sc); +int ath12k_thermal_set_throttling(struct ath12k *ar, u32 throttle_state); +void ath12k_thermal_event_temperature(struct ath12k *ar, int temperature); +#else +static inline int ath12k_thermal_register(struct ath12k_base *sc) +{ + return 0; +} + +static inline void ath12k_thermal_unregister(struct ath12k_base *sc) +{ +} + +static inline int ath12k_thermal_set_throttling(struct ath12k *ar, u32 throttle_state) +{ + return 0; +} + +static inline void ath12k_thermal_event_temperature(struct ath12k *ar, + int temperature) +{ +} + +#endif +#endif /* _ATH12K_THERMAL_ */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/umac_reset.c 2024-03-18 14:40:14.859741552 +0100 @@ -0,0 +1,502 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "coredump.h" +#include "dp_tx.h" +#include "dp_rx.h" +#include "debug.h" +#include "hif.h" +#include "dp.h" +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT +#include "ppe.h" +#endif + +int ath12k_htt_umac_reset_msg_send(struct ath12k_base *ab, + struct ath12k_htt_umac_reset_setup_cmd_params *params) +{ + struct sk_buff *skb; + struct htt_dp_umac_reset_setup_req_cmd *cmd; + int ret; + int len = sizeof(*cmd); + + skb = ath12k_htc_alloc_skb(ab, len); + if (!skb) + return -ENOMEM; + + skb_put(skb, len); + cmd = (struct htt_dp_umac_reset_setup_req_cmd *)skb->data; + cmd->msg_info = u32_encode_bits(HTT_H2T_MSG_TYPE_UMAC_RESET_PREREQUISITE_SETUP, + HTT_H2T_MSG_TYPE_SET); + cmd->msg_info |= u32_encode_bits(0, HTT_H2T_MSG_METHOD); + cmd->msg_info |= u32_encode_bits(0, HTT_T2H_MSG_METHOD); + cmd->msi_data = params->msi_data; + cmd->msg_shared_mem.size = sizeof(struct htt_h2t_paddr_size); + cmd->msg_shared_mem.addr_lo = params->addr_lo; + cmd->msg_shared_mem.addr_hi = params->addr_hi; + + + ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); + + if (ret) { + ath12k_warn(ab, "DP UMAC INIT msg send failed ret:%d\n", ret); + goto err_free; + } + + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "DP UMAC INIT msg sent from host\n"); + return 0; + +err_free: + dev_kfree_skb_any(skb); + return ret; +} + +int ath12k_htt_umac_reset_send_start_pre_reset_cmd(struct ath12k_base *ab, int is_initiator, + int is_target_recovery) +{ + struct sk_buff *skb; + struct h2t_umac_hang_recovery_start_pre_reset *cmd; + int ret; + int len = sizeof(*cmd); + + skb = ath12k_htc_alloc_skb(ab, len); + if (!skb) + return -ENOMEM; + + skb_put(skb, len); + cmd = (struct h2t_umac_hang_recovery_start_pre_reset*)skb->data; + memset(cmd, 0, sizeof(*cmd)); + cmd->hdr = u32_encode_bits(HTT_H2T_MSG_TYPE_UMAC_RESET_START_PRE_RESET, + HTT_H2T_UMAC_RESET_MSG_TYPE); + cmd->hdr |= u32_encode_bits(is_initiator, HTT_H2T_UMAC_RESET_IS_INITIATOR_SET); + cmd->hdr |= u32_encode_bits(is_target_recovery, HTT_H2T_UMAC_RESET_IS_TARGET_RECOVERY_SET); + + ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); + if (ret) { + ath12k_warn(ab, "failed to send htt umac reset pre reset start: %d\n", + ret); + dev_kfree_skb_any(skb); + return ret; + } + + return 0; +} + +int ath12k_get_umac_reset_intr_offset(struct ath12k_base *ab) +{ + int i; + + for (i = 0; i < ATH12K_EXT_IRQ_NUM_MAX; i++) { + if (ab->hw_params->ring_mask->umac_dp_reset[i]) + return i; + } + return 0; +} + +int ath12k_htt_umac_reset_setup_cmd(struct ath12k_base *ab) +{ + int msi_data_count; + struct ath12k_htt_umac_reset_setup_cmd_params params = {}; + u32 msi_data_start, msi_irq_start; + int ret, intr_ctxt; + struct ath12k_dp_umac_reset *umac_reset = &ab->dp_umac_reset; + + intr_ctxt = ath12k_get_umac_reset_intr_offset(ab); + ret = ath12k_hif_get_user_msi_vector(ab, "DP", + &msi_data_count, &msi_data_start, + &msi_irq_start); + if (ret) + params.msi_data = ATH12K_UMAC_RESET_IPC; + else + params.msi_data = (intr_ctxt % msi_data_count) + msi_data_start; + params.addr_lo = umac_reset->shmem_paddr_aligned & HAL_ADDR_LSB_REG_MASK; + params.addr_hi = (u64)umac_reset->shmem_paddr_aligned >> HAL_ADDR_MSB_REG_SHIFT; + + return ath12k_htt_umac_reset_msg_send(ab, ¶ms); +} + +int ath12k_dp_umac_reset_init(struct ath12k_base *ab) +{ + struct ath12k_dp_umac_reset *umac_reset; + int alloc_size, ret; + + if (!ab->hw_params->support_umac_reset) + return 0; + + umac_reset = &ab->dp_umac_reset; + umac_reset->magic_num = ATH12K_DP_UMAC_RESET_SHMEM_MAGIC_NUM; + + alloc_size = sizeof(struct ath12k_dp_htt_umac_reset_recovery_msg_shmem_t) + + ATH12K_DP_UMAC_RESET_SHMEM_ALIGN - 1; + + umac_reset->shmem_vaddr_unaligned = dma_alloc_coherent(ab->dev, + alloc_size, + &umac_reset->shmem_paddr_unaligned, + GFP_KERNEL); + if (!umac_reset->shmem_vaddr_unaligned) { + ath12k_warn(ab, "Failed to allocate memory with size:%u\n", alloc_size); + return -ENOMEM; + } + + umac_reset->shmem_vaddr_aligned = + PTR_ALIGN(umac_reset->shmem_vaddr_unaligned, ATH12K_DP_UMAC_RESET_SHMEM_ALIGN); + umac_reset->shmem_paddr_aligned = + umac_reset->shmem_paddr_unaligned + ((unsigned long)umac_reset->shmem_vaddr_aligned - + (unsigned long)umac_reset->shmem_vaddr_unaligned); + umac_reset->shmem_size = alloc_size; + umac_reset->shmem_vaddr_aligned->magic_num = ATH12K_DP_UMAC_RESET_SHMEM_MAGIC_NUM; + umac_reset->intr_offset = ath12k_get_umac_reset_intr_offset(ab); + memset(&umac_reset->ts, 0, sizeof(struct ath12k_umac_reset_ts)); + + ret = ath12k_hif_dp_umac_reset_irq_config(ab); + if (ret) { + ath12k_warn(ab, "Failed to register interrupt for UMAC RECOVERY\n"); + goto shmem_free; + } + + ret = ath12k_htt_umac_reset_setup_cmd(ab); + if (ret) { + ath12k_warn(ab, "Unable to setup UMAC RECOVERY\n"); + goto free_irq; + } + + ath12k_hif_dp_umac_reset_enable_irq(ab); + return 0; + +free_irq: + ath12k_hif_dp_umac_reset_free_irq(ab); +shmem_free: + dma_free_coherent(ab->dev, + umac_reset->shmem_size, + umac_reset->shmem_vaddr_unaligned, + umac_reset->shmem_paddr_unaligned); + umac_reset->shmem_vaddr_unaligned = NULL; + return ret; +} + +void ath12k_umac_reset_pre_reset_validation(struct ath12k_base *ab, bool *is_initiator, + bool *is_target_recovery) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset; + *is_initiator = *is_target_recovery = false; + + if (!ag) + return; + + mlo_umac_reset = &ag->mlo_umac_reset; + + spin_lock_bh(&mlo_umac_reset->lock); + if (mlo_umac_reset->initiator_chip == ab->chip_id) + *is_initiator = true; + if (mlo_umac_reset->umac_reset_info & BIT(1)) + *is_target_recovery = true; + spin_unlock_bh(&mlo_umac_reset->lock); +} + +void ath12k_umac_reset_completion(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset = &ag->mlo_umac_reset; + + if (!mlo_umac_reset) + return; + + if (!(mlo_umac_reset->umac_reset_info & BIT(0))) + return; + + spin_lock_bh(&mlo_umac_reset->lock); + mlo_umac_reset->umac_reset_info = 0; + mlo_umac_reset->initiator_chip = 0; + spin_unlock_bh(&mlo_umac_reset->lock); +} + +void ath12k_umac_reset_send_htt(struct ath12k_base *ab, int tx_event) +{ + struct ath12k_dp_umac_reset *umac_reset = &ab->dp_umac_reset; + struct ath12k_dp_htt_umac_reset_recovery_msg_shmem_t *shmem_vaddr_aligned; + bool is_initiator, is_target_recovery; + int ret; + + shmem_vaddr_aligned = umac_reset->shmem_vaddr_aligned; + + switch(tx_event) { + case ATH12K_UMAC_RESET_TX_CMD_TRIGGER_DONE: + ath12k_umac_reset_pre_reset_validation(ab, &is_initiator, + &is_target_recovery); + ret = ath12k_htt_umac_reset_send_start_pre_reset_cmd(ab, + is_initiator, + is_target_recovery); + ab->dp_umac_reset.ts.trigger_done = jiffies_to_msecs(jiffies); + if (ret) + ath12k_warn(ab, "Unable to send umac trigger\n"); + break; + case ATH12K_UMAC_RESET_TX_CMD_PRE_RESET_DONE: + shmem_vaddr_aligned->h2t_msg = u32_encode_bits(1, + ATH12K_HTT_UMAC_RESET_MSG_SHMEM_PRE_RESET_DONE_SET); + ab->dp_umac_reset.ts.pre_reset_done = jiffies_to_msecs(jiffies); + break; + case ATH12K_UMAC_RESET_TX_CMD_POST_RESET_START_DONE: + shmem_vaddr_aligned->h2t_msg = u32_encode_bits(1, + ATH12K_HTT_UMAC_RESET_MSG_SHMEM_POST_RESET_START_DONE_SET); + ab->dp_umac_reset.ts.post_reset_done = jiffies_to_msecs(jiffies); + break; + case ATH12K_UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE: + shmem_vaddr_aligned->h2t_msg = u32_encode_bits(1, + ATH12K_HTT_UMAC_RESET_MSG_SHMEM_POST_RESET_COMPLETE_DONE); + ab->dp_umac_reset.ts.post_reset_complete_done = jiffies_to_msecs(jiffies); + break; + } + + if (tx_event == ATH12K_UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE) { + ath12k_umac_reset_completion(ab); + ath12k_info(ab, "MLO UMAC Recovery completed\n"); + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "Time taken for trigger_start:%llums " + "trigger_done: %llums pre_reset:%llums post_reset:%llums " + "post_reset_complete:%llums", + ab->dp_umac_reset.ts.trigger_start, ab->dp_umac_reset.ts.trigger_done, + ab->dp_umac_reset.ts.pre_reset_done - ab->dp_umac_reset.ts.pre_reset_start, + ab->dp_umac_reset.ts.post_reset_done - ab->dp_umac_reset.ts.post_reset_start, + ab->dp_umac_reset.ts.post_reset_complete_done - ab->dp_umac_reset.ts.post_reset_complete_start); + memset(&umac_reset->ts, 0, sizeof(struct ath12k_umac_reset_ts)); + } + + return; +} + +int ath12k_umac_reset_notify_target(struct ath12k_base *ab, int tx_event) +{ + struct ath12k_base *partner_ab; + struct ath12k_hw_group *ag = ab->ag; + int i; + + for (i = 0; i < ag->num_chip; i++) { + partner_ab = ag->ab[i]; + + if (test_bit(ATH12K_FLAG_RECOVERY, &partner_ab->dev_flags)) + continue; + + ath12k_umac_reset_send_htt(partner_ab, tx_event); + } + + return 0; +} + +void ath12k_umac_reset_initiate_recovery(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset = &ag->mlo_umac_reset; + + if (!mlo_umac_reset) + return; + + spin_lock_bh(&mlo_umac_reset->lock); + + if (mlo_umac_reset->umac_reset_info & + ATH12K_IS_UMAC_RESET_IN_PROGRESS) { + spin_unlock_bh(&mlo_umac_reset->lock); + ath12k_warn(ab, "UMAC RECOVERY IS IN PROGRESS\n"); + return; + } + mlo_umac_reset->umac_reset_info = BIT(0); /* UMAC recovery is in progress */ + mlo_umac_reset->umac_reset_info |= BIT(1); /* Target recovery */ + atomic_set(&mlo_umac_reset->response_chip, 0); + mlo_umac_reset->initiator_chip = ab->chip_id; + spin_unlock_bh(&mlo_umac_reset->lock); +} + +void ath12k_umac_reset_notify_target_sync_and_send(struct ath12k_base *ab, + enum dp_umac_reset_tx_cmd tx_event) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset = &ag->mlo_umac_reset; + + if (atomic_read(&mlo_umac_reset->response_chip) >= ab->ag->num_started) { + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "response chip:%d num_started:%d sending notify\n", + atomic_read(&mlo_umac_reset->response_chip), ab->ag->num_started); + ath12k_umac_reset_notify_target(ab, tx_event); + atomic_set(&mlo_umac_reset->response_chip, 0); + } else { + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "response_chip:%d num_started:%d not matching.. hold on notify\n", + atomic_read(&mlo_umac_reset->response_chip), ab->ag->num_started); + } + return; +} + +void ath12k_umac_reset_notify_pre_reset_done(struct ath12k_base *ab) +{ + struct ath12k_dp *dp = &ab->dp; + + if (dp->ppeds_service_running) + return; + + ath12k_umac_reset_notify_target_sync_and_send(ab, + ATH12K_UMAC_RESET_TX_CMD_PRE_RESET_DONE); + ab->dp_umac_reset.umac_pre_reset_in_prog = false; +} + +void ath12k_umac_reset_handle_pre_reset(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset = &ag->mlo_umac_reset; + + set_bit(ATH12K_FLAG_UMAC_PRERESET_START, &ab->dev_flags); + ath12k_dp_reset_interrupt_mask(ab); + atomic_inc(&mlo_umac_reset->response_chip); + +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (ab->ppeds_handle) { + ath12k_dp_ppeds_service_enable_disable(ab, true); + ab->dp_umac_reset.umac_pre_reset_in_prog = true; + ath12k_dp_ppeds_interrupt_stop(ab); + ath12k_dp_ppeds_stop(ab); + ath12k_dp_ppeds_service_enable_disable(ab, false); + } +#endif + if (!test_bit(ATH12K_FLAG_PPE_DS_ENABLED, &ab->dev_flags)) + ath12k_umac_reset_notify_target_sync_and_send(ab, + ATH12K_UMAC_RESET_TX_CMD_PRE_RESET_DONE); + return; +} + +void ath12k_umac_reset_handle_post_reset_complete(struct ath12k_base *ab) +{ + struct ath12k_hw_group *ag = ab->ag; + struct ath12k_mlo_dp_umac_reset *mlo_umac_reset = &ag->mlo_umac_reset; + + clear_bit(ATH12K_FLAG_UMAC_PRERESET_START, &ab->dev_flags); + + atomic_inc(&mlo_umac_reset->response_chip); + ath12k_dp_restore_interrupt_mask(ab); +#ifdef CONFIG_ATH12K_PPE_DS_SUPPORT + if (ab->ppeds_handle) { + ath12k_dp_ppeds_start(ab); + ath12k_dp_ppeds_interrupt_start(ab); + } +#endif + ath12k_umac_reset_notify_target_sync_and_send(ab, ATH12K_UMAC_RESET_TX_CMD_POST_RESET_COMPLETE_DONE); + ath12k_dp_peer_tid_setup(ab); + return; +} + +void ath12k_dp_umac_reset_action(struct ath12k_base *ab, + enum dp_umac_reset_recover_action rx_event) +{ + switch(rx_event) { + case ATH12K_UMAC_RESET_INIT_UMAC_RECOVERY: + case ATH12K_UMAC_RESET_INIT_TARGET_RECOVERY_SYNC_USING_UMAC: + ath12k_umac_reset_initiate_recovery(ab); + ab->dp_umac_reset.ts.trigger_start = jiffies_to_msecs(jiffies); + ath12k_umac_reset_notify_target(ab, ATH12K_UMAC_RESET_TX_CMD_TRIGGER_DONE); + break; + case ATH12K_UMAC_RESET_DO_POST_RESET_COMPLETE: + ab->dp_umac_reset.ts.post_reset_complete_start = jiffies_to_msecs(jiffies); + ath12k_umac_reset_handle_post_reset_complete(ab); + break; + case ATH12K_UMAC_RESET_DO_POST_RESET_START: + ab->dp_umac_reset.ts.post_reset_start = jiffies_to_msecs(jiffies); + ath12k_umac_reset_handle_post_reset_start(ab); + break; + case ATH12K_UMAC_RESET_DO_PRE_RESET: + ab->dp_umac_reset.ts.pre_reset_start = jiffies_to_msecs(jiffies); + ath12k_umac_reset_handle_pre_reset(ab); + break; + default: + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "Unknown UMAC RESET event received\n"); + break; + } + return; +} + +void ath12k_dp_umac_reset_handle(struct ath12k_base *ab) +{ + struct ath12k_dp_umac_reset *umac_reset = &ab->dp_umac_reset; + struct ath12k_dp_htt_umac_reset_recovery_msg_shmem_t *shmem_vaddr; + int rx_event, num_event = 0; + u32 t2h_msg; + + shmem_vaddr = umac_reset->shmem_vaddr_aligned; + if (!shmem_vaddr) { + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "Shared memory address NULL\n"); + return; + } + + if (shmem_vaddr->magic_num != umac_reset->magic_num) { + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "Shared memory address is invalid shmem:0x%x u:0x%x\n", + shmem_vaddr->magic_num, umac_reset->magic_num); + return; + } + + t2h_msg = shmem_vaddr->t2h_msg; + shmem_vaddr->t2h_msg = 0; + + rx_event = ATH12K_UMAC_RESET_RX_EVENT_NONE; + + if (u32_get_bits(t2h_msg, HTT_ATH12K_UMAC_RESET_T2H_INIT_UMAC_RECOVERY)) { + rx_event |= ATH12K_UMAC_RESET_INIT_UMAC_RECOVERY; + num_event++; + } + + if (u32_get_bits(t2h_msg, HTT_ATH12K_UMAC_RESET_T2H_INIT_TARGET_RECOVERY_SYNC_USING_UMAC)) { + rx_event |= ATH12K_UMAC_RESET_INIT_TARGET_RECOVERY_SYNC_USING_UMAC; + num_event++; + } + + if (u32_get_bits(t2h_msg, HTT_ATH12K_UMAC_RESET_T2H_DO_PRE_RESET)) { + rx_event |= ATH12K_UMAC_RESET_DO_PRE_RESET; + num_event++; + } + + if (u32_get_bits(t2h_msg, HTT_ATH12K_UMAC_RESET_T2H_DO_POST_RESET_START)) { + rx_event |= ATH12K_UMAC_RESET_DO_POST_RESET_START; + num_event++; + } + + if (u32_get_bits(t2h_msg, HTT_ATH12K_UMAC_RESET_T2H_DO_POST_RESET_COMPLETE)) { + rx_event |= ATH12K_UMAC_RESET_DO_POST_RESET_COMPLETE; + num_event++; + } + + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "Deduced rx event:%d num:%d\n", rx_event, num_event); + + if (num_event > 1) { + ath12k_dbg(ab, ATH12K_DBG_DP_UMAC_RESET, "Multiple event notified in single msg\n"); + WARN_ON_ONCE(1); + return; + } + + ath12k_dp_umac_reset_action(ab, rx_event); + return; +} + +void ath12k_dp_umac_reset_deinit(struct ath12k_base *ab) +{ + struct ath12k_dp_umac_reset *umac_reset; + + if (!ab->hw_params->support_umac_reset) + return; + + umac_reset = &ab->dp_umac_reset; + + if (!umac_reset) + return; + + ath12k_hif_dp_umac_reset_free_irq(ab); + + if (umac_reset->shmem_vaddr_unaligned) { + dma_free_coherent(ab->dev, + umac_reset->shmem_size, + umac_reset->shmem_vaddr_unaligned, + umac_reset->shmem_paddr_unaligned); + umac_reset->shmem_vaddr_unaligned = NULL; + + } +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/vendor.c 2024-03-18 14:40:14.859741552 +0100 @@ -0,0 +1,1317 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ +#include +#include +#include "core.h" +#include "debug.h" +#include "mac.h" +#include "telemetry.h" +#include "sawf.h" +#include "bondif.h" + +#ifdef CONFIG_ATH12K_SAWF +static const struct nla_policy +ath12k_vendor_sdwf_phy_policy[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_PHY_OPERATION] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS] = {.type = NLA_NESTED}, + [QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_SAMPLES_PARAMS] = {.type = NLA_NESTED}, + [QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_DETECT_PARAMS] = {.type = NLA_NESTED}, + [QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_THRESHOLD_PARAMS] = {.type = NLA_NESTED}, +}; + +static const struct nla_policy +ath12k_vendor_sdwf_dev_policy[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_DEV_OPERATION] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS] = {.type = NLA_NESTED}, + [QCA_WLAN_VENDOR_ATTR_SDWF_DEV_STREAMING_STATS_PARAMS] = {.type = NLA_NESTED}, + [QCA_WLAN_VENDOR_ATTR_SDWF_DEV_RESET_STATS] = {.type = NLA_NESTED}, + [QCA_WLAN_VENDOR_ATTR_SDWF_DEV_SLA_BREACHED_PARAMS] = {.type = NLA_NESTED}, +}; + +static const struct nla_policy +ath12k_vendor_sdwf_svc_policy[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MIN_TP] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX_TP] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_BURST_SIZE] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_INTERVAL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_DELAY_BOUND] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_TTL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_PRIO] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_TID] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_RATE_LOSS] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_SVC_INTERVAL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MIN_TPUT] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MAX_LATENCY ] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_BURST_SIZE] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_OFDMA_DISABLE] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MU_MIMO_DISABLE] = {.type = NLA_U8}, +}; + +static const struct nla_policy +ath12k_vendor_sdwf_def_qmap_req_policy[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_SVC_ID] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR] = {.type = NLA_STRING, .len = 18}, + [QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_TID] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_STATUS] = {.type = NLA_U8}, +}; + +static const struct nla_policy +ath12k_vendor_telemetry_sdwf_sla_thershold_config_policy[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_SVC_ID] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MIN_TP] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MAX_TP] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_BURST_SIZE] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_INTERVAL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_DELAY_BOUND] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MSDU_TTL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MSDU_RATE_LOSS] = {.type = NLA_U32}, +}; + +static const struct nla_policy +ath12k_vendor_telemetry_sdwf_sla_detect_config_policy[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_PARAM] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MIN_TP] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MAX_TP] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_BURST_SIZE] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_INTERVAL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_DELAY_BOUND] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MSDU_TTL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MSDU_RATE_LOSS ] = {.type = NLA_U32}, +}; + +static const struct nla_policy +ath12k_vendor_telemetry_sdwf_sla_samples_config_policy[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MOVING_AVG_PKT] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MOVING_AVG_WIN] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_SLA_NUM_PKT] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_SLA_TIME_SEC] = {.type = NLA_U32}, +}; + +static const struct nla_policy +ath12k_vendor_sawf_streaming[QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_BASIC_STATS] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_EXTND_STATS] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_MLO_LINK_ID] = {.type = NLA_U32}, +}; + +static const struct nla_policy +ath12k_telemetric_req_policy[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_TELEMETRIC_LEVEL] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_TELEMETRIC_OBJECT] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_TELEMETRIC_TYPE] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_TELEMETRIC_AGGREGATE] = {.type = NLA_FLAG}, + [QCA_WLAN_VENDOR_ATTR_TELEMETRIC_FEATURE_FLAG] = {.type = NLA_U64}, + [QCA_WLAN_VENDOR_ATTR_TELEMETRIC_STA_MAC] = {.type = NLA_BINARY, + .len = ETH_ALEN}, + [QCA_WLAN_VENDOR_ATTR_TELEMETRIC_SERVICEID] = {.type = NLA_U8}, +}; + +static const struct nla_policy +ath12k_telemetric_sla_policy[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MAC] = {.type = NLA_BINARY, + .len = ETH_ALEN}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SVC_ID] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_TYPE] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SET_CLEAR] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MLD_MAC] = {.type = NLA_BINARY, + .len = ETH_ALEN}, + [QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_AC] = {.type = NLA_U8}, +}; + +#endif + +static const struct nla_policy +ath12k_vendor_scs_config_policy[QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DST_MAC_ADDR] = {.type = NLA_BINARY, + .len = ETH_ALEN}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_SERVICE_INTERVAL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_BURST_SIZE] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DELAY_BOUND] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_MINIMUM_DATA_RATE] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_REQUEST_TYPE] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_USER_PRIORITY] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_ACCESS_CATEGORY] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DIRECTION] = {.type = NLA_U8}, +}; + +#ifdef CONFIG_ATH12K_SAWF +static const struct nla_policy +ath12k_ds_policy[QCA_WLAN_VENDOR_ATTR_DS_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_CONFIG_EHT_MLO_MODE] = {.type = NLA_U8}, +}; + + +static void ath12k_set_default_values(struct ath12k_sawf_svc_params *param) +{ + param->min_throughput_rate = SAWF_SVC_PARAM_DEFAULT_MIN_THRUPUT; + param->max_throughput_rate = SAWF_SVC_PARAM_DEFAULT_MAX_THRUPUT; + param->burst_size = SAWF_SVC_PARAM_DEFAULT_BURST_SIZE; + param->service_interval = SAWF_SVC_PARAM_DEFAULT_SVC_INTERVAL; + param->delay_bound = SAWF_SVC_PARAM_DEFAULT_DELAY_BOUND; + param->msdu_ttl = SAWF_SVC_PARAM_DEFAULT_TIME_TO_LIVE; + param->priority = SAWF_SVC_PARAM_DEFAULT_PRIORITY; + param->tid = SAWF_SVC_PARAM_DEFAULT_TID; + param->msdu_rate_loss = SAWF_SVC_PARAM_DEFAULT_MSDU_LOSS_RATE; + param->ul_burst_size = SAWF_SVC_PARAM_DEFAULT_UL_BURST_SIZE; + param->ul_min_tput = SAWF_SVC_PARAM_DEFAULT_UL_MIN_TPUT; + param->ul_max_latency = SAWF_SVC_PARAM_DEFAULT_UL_MAX_LATENCY; + param->ul_service_interval = SAWF_SVC_PARAM_DEFAULT_UL_SVC_INTERVAL; + param->ul_ofdma_disable = SAWF_SVC_PARAM_DEFAULT_UL_OFDMA_DISABLE; + param->ul_mu_mimo_disable = SAWF_SVC_PARAM_DEFAULT_UL_MU_MIMO_DISABLE; +} + +static int ath12k_vendor_set_sdwf_config(struct wiphy *wiphy, + struct wireless_dev *wdev, + struct nlattr *svc_params) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX + 1]; + struct ath12k_sawf_svc_params sdwf_param; + int ret = 0; + + memset(&sdwf_param, 0, sizeof(struct ath12k_sawf_svc_params)); + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX, + svc_params, + ath12k_vendor_sdwf_svc_policy, NULL); + if (ret) { + ath12k_err(NULL, "Invalid attribute with SAWF configure command\n"); + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID]) { + sdwf_param.svc_id = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID]); + } else { + ath12k_err(NULL, "Mandatory attributes not available\n"); + return -EINVAL; + } + + ath12k_set_default_values(&sdwf_param); + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MIN_TP]) + sdwf_param.min_throughput_rate = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MIN_TP]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX_TP]) + sdwf_param.max_throughput_rate = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX_TP]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_BURST_SIZE]) + sdwf_param.burst_size = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_BURST_SIZE]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_INTERVAL]) + sdwf_param.service_interval = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_INTERVAL]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_DELAY_BOUND]) + sdwf_param.delay_bound = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_DELAY_BOUND]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_TTL]) + sdwf_param.msdu_ttl = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_TTL]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_PRIO]) + sdwf_param.priority = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_PRIO]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_TID]) + sdwf_param.tid = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_TID]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_RATE_LOSS]) + sdwf_param.msdu_rate_loss = nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_RATE_LOSS]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_SVC_INTERVAL]) + sdwf_param.ul_service_interval = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_SVC_INTERVAL]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_BURST_SIZE]) + sdwf_param.ul_burst_size = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_BURST_SIZE]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MIN_TPUT]) + sdwf_param.ul_min_tput = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MIN_TPUT]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MAX_LATENCY ]) + sdwf_param.ul_max_latency = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MAX_LATENCY ]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_OFDMA_DISABLE]) + sdwf_param.ul_ofdma_disable = + nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_OFDMA_DISABLE]); + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MU_MIMO_DISABLE]) + sdwf_param.ul_mu_mimo_disable = + nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MU_MIMO_DISABLE]); + + ret = ath12k_create_send_svc_params(&sdwf_param); + + return ret; +} + +static int ath12k_vendor_disable_sdwf_config(struct nlattr *svc_params) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX + 1]; + u8 svc_id = 0; + int ret = 0; + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX, + svc_params, + ath12k_vendor_sdwf_svc_policy, NULL); + if (ret) { + ath12k_err(NULL, "Invalid attributes with SAWF disable command\n"); + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID]) { + svc_id = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID]); + } else { + ath12k_err(NULL, "Mandatory attribute not available\n"); + return -EINVAL; + } + + ret = ath12k_sawf_disable_config(svc_id); + return ret; +} + +static int ath12k_vendor_view_sdwf_config(struct wiphy *wiphy, + struct wireless_dev *wdev, + struct sk_buff *msg, + const void *data, + int data_len, + unsigned long *storage) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_MAX + 1]; + struct nlattr *svc[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX + 1]; + struct ath12k_sawf_ctx *sdwf_ctx; + struct ath12k_sawf_svc_params *svc_class; + struct nlattr *sdwf_svc_classes, *sdwf_svc_class; + int ret = 0, i, j = 0; + int tailroom = 0, nest_start_length = 0, nest_end_length = 0, nested_range = 0; + u8 svc_id = 0; + + if (!ath12k_sawf_enable) + return -EOPNOTSUPP; + + sdwf_ctx = ath12k_get_sawf_context(); + if (!sdwf_ctx) { + ath12k_err(NULL, "SAWF context not available\n"); + return -ENODATA; + } + + ret = nla_parse(tb, QCA_WLAN_VENDOR_ATTR_SDWF_PHY_MAX, data, data_len, + ath12k_vendor_sdwf_phy_policy, NULL); + + if (ret) { + ath12k_err(NULL, "Invalid attributes with SAWF commands\n"); + return -EINVAL; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_OPERATION] && + nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_OPERATION]) == QCA_WLAN_VENDOR_SDWF_PHY_OPER_SVC_GET) { + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS]) { + ret = nla_parse_nested(svc, QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX, + tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS], + ath12k_vendor_sdwf_svc_policy, NULL); + if (ret) { + ath12k_err(NULL, "Invalid attribute with SAWF view command\n"); + return -EINVAL; + } + if (svc[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID]) { + bool isconfigured; + + svc_id = nla_get_u8(svc[QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID]); + if (!ath12k_svc_id_valid(svc_id)) { + ath12k_err(NULL, "Invalid Service ID: %u\n", svc_id); + return -EINVAL; + } + spin_lock_bh(&sdwf_ctx->sawf_svc_lock); + isconfigured = ath12k_svc_id_configured(svc_id); + spin_unlock_bh(&sdwf_ctx->sawf_svc_lock); + if (!isconfigured) + return -EINVAL; + } + } + } else { + ath12k_err(NULL, "Invalid attribute with SAWF view command\n"); + return -EINVAL; + } + /* return 0 to end the dump */ + if (storage && (*storage == ATH12K_SAWF_SVC_CLASS_MAX)) + return 0; + + sdwf_svc_classes = nla_nest_start(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS); + + if (!sdwf_svc_classes) + return -ENOBUFS; + + tailroom = skb_tailroom(msg); + spin_lock_bh(&sdwf_ctx->sawf_svc_lock); + for (i = (svc_id) ? (svc_id - 1) : (*storage); + i < ATH12K_SAWF_SVC_CLASS_MAX && tailroom > nested_range; + i += (svc_id) ? (ATH12K_SAWF_SVC_CLASS_MAX) : (1)) { + if (!sdwf_ctx->svc_classes[i].configured) + continue; + + svc_class = &sdwf_ctx->svc_classes[i]; + nest_start_length = msg->len; + sdwf_svc_class = nla_nest_start(msg, j); + if (nla_put_u8(msg, QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID, + svc_class->svc_id) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MIN_TP, + svc_class->min_throughput_rate) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX_TP, + svc_class->max_throughput_rate) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_BURST_SIZE, + svc_class->burst_size) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_INTERVAL, + svc_class->service_interval) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_DELAY_BOUND, + svc_class->delay_bound) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_TTL, + svc_class->msdu_ttl) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_PRIO, + svc_class->priority) || + nla_put_u32(msg, QCA_WLAN_VENDOR_ATTR_SDWF_SVC_TID, + svc_class->tid) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_RATE_LOSS, + svc_class->msdu_rate_loss) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_SVC_INTERVAL, + svc_class->ul_service_interval) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MIN_TPUT, + svc_class->ul_min_tput) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MAX_LATENCY, + svc_class->ul_max_latency) || + nla_put_u32(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_BURST_SIZE, + svc_class->ul_burst_size) || + nla_put_u8(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_OFDMA_DISABLE, + svc_class->ul_ofdma_disable) || + nla_put_u8(msg, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MU_MIMO_DISABLE, + svc_class->ul_mu_mimo_disable)) + goto nla_put_failure; + + nest_end_length = nla_nest_end(msg, sdwf_svc_class); + nested_range = nest_end_length - nest_start_length; + tailroom -= nested_range; + j++; + } + spin_unlock_bh(&sdwf_ctx->sawf_svc_lock); + nla_nest_end(msg, sdwf_svc_classes); + + *storage = (svc_id) ? (ATH12K_SAWF_SVC_CLASS_MAX) : (i); + + if (!j) + return 0; + + return msg->len; + +nla_put_failure: + spin_unlock_bh(&sdwf_ctx->sawf_svc_lock); + return -ENOBUFS; +} + +static int ath12k_vendor_sdwf_def_qmap_req(struct wireless_dev *wdev, + struct nlattr *def_q_params) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX + 1]; + struct ath12k_base *ab = NULL; + u8 svc_id; + u8 *mac_addr_p = NULL; + u16 peer_id = 0xFFFF; + u8 mac_addr[ATH12K_MAC_ADDR_SIZE] = { 0 }; + int ret = 0; + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX, + def_q_params, + ath12k_vendor_sdwf_def_qmap_req_policy, NULL); + if (ret) { + ath12k_warn(NULL, "invalid sawf def q map policy attribute\n"); + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR]) { + mac_addr_p = nla_data(tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR]); + if (sscanf(mac_addr_p, + "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &mac_addr[0], + &mac_addr[1], + &mac_addr[2], + &mac_addr[3], + &mac_addr[4], + &mac_addr[5]) != ATH12K_MAC_ADDR_SIZE) { + ath12k_warn(NULL, "invalid Macaddr %s\n", mac_addr_p); + return -1; + } + } + svc_id = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_SVC_ID]); + + ath12k_dbg(NULL, ATH12K_DBG_SAWF, + "Default Q map:svcid[%u]macaddr[%pM]\n", svc_id, mac_addr); + + ab = ath12k_sawf_get_ab_from_netdev(wdev->netdev, mac_addr, &peer_id); + if (ab) + ret = ath12k_sawf_def_qmap_req(ab, svc_id, peer_id); + + return ret; +} + +static int ath12k_vendor_sdwf_def_qunmap_req(struct wireless_dev *wdev, + struct nlattr *def_q_params) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX + 1]; + struct ath12k_base *ab; + u8 svc_id; + u16 peer_id = 0xFFFF; + u8 *mac_addr_p = NULL; + u8 mac_addr[ATH12K_MAC_ADDR_SIZE] = { 0 }; + int ret = 0; + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX, + def_q_params, + ath12k_vendor_sdwf_def_qmap_req_policy, NULL); + if (ret) { + ath12k_warn(NULL, "invalid sawf def q unmap policy attribute\n"); + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR]) { + mac_addr_p = nla_data(tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR]); + if (sscanf(mac_addr_p, + "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &mac_addr[0], + &mac_addr[1], + &mac_addr[2], + &mac_addr[3], + &mac_addr[4], + &mac_addr[5]) != ATH12K_MAC_ADDR_SIZE) { + ath12k_warn(NULL, "invalid Macaddr %s\n", mac_addr_p); + return -1; + } + } + svc_id = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_SVC_ID]); + + ath12k_dbg(NULL, ATH12K_DBG_SAWF, + "Default Q unmap:svcid[%u]macaddr[%pM]\n", svc_id, mac_addr); + + ab = ath12k_sawf_get_ab_from_netdev(wdev->netdev, mac_addr, &peer_id); + + if (ab) + ret = ath12k_sawf_def_qunmap_req(ab, svc_id, peer_id); + + return ret; +} + +static int ath12k_vendor_sdwf_def_qmap_report_req(struct wireless_dev *wdev, + struct nlattr *def_q_params) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX + 1]; + struct ath12k_base *ab = NULL; + u16 peer_id = 0xFFFF; + u8 *mac_addr_p = NULL; + u8 mac_addr[ATH12K_MAC_ADDR_SIZE] = { 0 }; + int ret = 0; + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX, + def_q_params, + ath12k_vendor_sdwf_def_qmap_req_policy, NULL); + if (ret) { + ath12k_warn(NULL, "invalid sawf def q map report req policy attribute\n"); + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR]) { + mac_addr_p = nla_data(tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR]); + if (sscanf(mac_addr_p, + "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", + &mac_addr[0], + &mac_addr[1], + &mac_addr[2], + &mac_addr[3], + &mac_addr[4], + &mac_addr[5]) != ATH12K_MAC_ADDR_SIZE) { + ath12k_warn(NULL, "invalid Macaddr %s\n", mac_addr_p); + return -1; + } + } + ath12k_dbg(NULL, ATH12K_DBG_SAWF, + "Default Q map report:macaddr[%pM]\n", mac_addr); + + ab = ath12k_sawf_get_ab_from_netdev(wdev->netdev, mac_addr, &peer_id); + if (ab) + ret = ath12k_sawf_def_qmap_report_req(ab, peer_id); + + return ret; +} + +static int ath12k_vendor_telemetry_sdwf_sla_samples_config(struct nlattr *sla_samples) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MAX + 1]; + struct ath12k_sla_samples_cfg t_param; + int ret = 0; + + if (!ath12k_sawf_enable) { + ath12k_warn(NULL, "sawf is not enabled \n"); + return -ENOSYS; + } + + memset(&t_param, 0, sizeof(struct ath12k_sla_samples_cfg)); + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MAX, + sla_samples, + ath12k_vendor_telemetry_sdwf_sla_samples_config_policy, NULL); + if (ret) { + ath12k_warn(NULL, "invalid set telemetry sla samples config policy attribute\n"); + return ret; + } + + t_param.moving_avg_pkt = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MOVING_AVG_PKT]); + t_param.moving_avg_win = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MOVING_AVG_WIN]); + t_param.sla_num_pkt = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_SLA_NUM_PKT]); + t_param.sla_time_sec = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_SLA_TIME_SEC]); + + ret = ath12k_telemetry_sawf_sla_samples_config(t_param); + return ret; +} + +static int ath12k_vendor_telemetry_sdwf_sla_thershold_config(struct nlattr *sla_threshold) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MAX + 1]; + struct ath12k_sla_thershold_cfg t_param; + int ret = 0; + + memset(&t_param, 0, sizeof(struct ath12k_sla_thershold_cfg)); + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MAX, + sla_threshold, + ath12k_vendor_telemetry_sdwf_sla_thershold_config_policy, NULL); + if (ret) { + ath12k_warn(NULL, "invalid telemetry sla thershold config policy attribute\n"); + return ret; + } + + t_param.svc_id = + nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_SVC_ID]); + t_param.min_throughput_rate = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MIN_TP]); + t_param.max_throughput_rate = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MAX_TP]); + t_param.burst_size = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_BURST_SIZE]); + t_param.service_interval = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_INTERVAL]); + t_param.delay_bound = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_DELAY_BOUND]); + t_param.msdu_ttl = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MSDU_TTL]); + t_param.msdu_rate_loss = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MSDU_RATE_LOSS]); + + ret = ath12k_telemetry_sawf_sla_thershold_config(t_param); + + return ret; +} + +static int ath12k_vendor_telemetry_sdwf_sla_detection_config(struct nlattr *sla_detect) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MAX + 1]; + struct ath12k_sla_detect_cfg t_param; + int ret = 0; + + memset(&t_param, 0, sizeof(struct ath12k_sla_detect_cfg)); + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MAX, + sla_detect, + ath12k_vendor_telemetry_sdwf_sla_detect_config_policy, NULL); + if (ret) { + ath12k_warn(NULL, "invalid telemetry sdwf sla detection config policy attribute\n"); + return ret; + } + + t_param.sla_detect = + nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_PARAM]); + t_param.min_throughput_rate = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MIN_TP]); + t_param.max_throughput_rate = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MAX_TP]); + t_param.burst_size = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_BURST_SIZE]); + t_param.service_interval = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_INTERVAL]); + t_param.delay_bound = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_DELAY_BOUND]); + t_param.msdu_ttl = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MSDU_TTL]); + t_param.msdu_rate_loss = + nla_get_u32(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MSDU_RATE_LOSS ]); + + ret = ath12k_telemetry_sawf_sla_detection_config(t_param); + + return ret; +} + +static struct ath12k *ath12k_get_ar_from_wdev(struct wireless_dev *wdev, u8 link_id) +{ + struct ieee80211_vif *vif = NULL; + struct ath12k_vif *ahvif = NULL; + struct ieee80211_hw *hw = NULL; + struct ath12k *ar = NULL; + + vif = wdev_to_ieee80211_vif(wdev); + if (!vif) + return NULL; + + ahvif = (struct ath12k_vif *)vif->drv_priv; + if (!ahvif) + return NULL; + + mutex_lock(&ahvif->ah->conf_mutex); + hw = ahvif->ah->hw; + if (!hw) { + mutex_unlock(&ahvif->ah->conf_mutex); + return NULL; + } + + ar = ath12k_get_ar_by_vif(hw, vif, link_id); + mutex_unlock(&ahvif->ah->conf_mutex); + + return ar; +} + +static int ath12k_vendor_sdwf_streaming_stats_configure(struct wireless_dev *wdev, + struct nlattr *streaming_stats) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_MAX + 1]; + struct ath12k *ar = NULL; + int ret = 0; + u8 basic_stats_configure, extnd_stats_configure, link_id; + + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_MAX, + streaming_stats, + ath12k_vendor_sawf_streaming, NULL); + if (ret) { + ath12k_warn(NULL, "invalid sawf streaming stats configuration\n"); + return ret; + } + + if (wdev->valid_links) { /* MLO case */ + if (!tb[QCA_WLAN_VENDOR_ATTR_SDWF_MLO_LINK_ID]) + return -EINVAL; + link_id = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_MLO_LINK_ID]); + if (!(wdev->valid_links & BIT(link_id))) + return -ENOLINK; + } else { /* NON-MLO case */ + if (!tb[QCA_WLAN_VENDOR_ATTR_SDWF_MLO_LINK_ID]) + link_id = 0; + else + return -EINVAL; + } + + ar = ath12k_get_ar_from_wdev(wdev, link_id); + if (!ar) + return -ENODATA; + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_BASIC_STATS]) { + basic_stats_configure = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_BASIC_STATS]); + ret = ath12k_htt_sawf_streaming_stats_configure(ar, HTT_STRM_GEN_MPDUS_STATS, + basic_stats_configure, 0, 0, 0, 0); + if (ret) + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_EXTND_STATS]) { + extnd_stats_configure = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_EXTND_STATS]); + ret = ath12k_htt_sawf_streaming_stats_configure(ar, HTT_STRM_GEN_MPDUS_DETAILS_STATS, + extnd_stats_configure, 0, 0, 0, 0); + } + + return ret; +} + +static int telemetry_build_nd_send_reply_msg(struct wiphy *wiphy, struct stats_config *cfg, + u8 *mac_addr, struct unified_stats *stats) +{ + struct sk_buff *skb = NULL; + void *data = NULL; + struct nlattr *attr; + u32 storage = 0, multiple_reply_len = 0; + int rem_len = 0, data_len = 0, nla_size = nla_total_size(0), ret = 0; + u8 i, feat = 0; + bool data_pending = false, multiple_reply_set = false; + char *vap="wifi"; + + do { + skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, NLMSG_DEFAULT_SIZE); + if (!skb) + return -ENOMEM; + + if (nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_STATS_LEVEL, cfg->lvl) || + nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_STATS_OBJECT, STATS_OBJ_STA) || + nla_put(skb, QCA_WLAN_VENDOR_ATTR_STATS_OBJ_ID, ETH_ALEN, mac_addr) || + nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_STATS_SERVICEID, cfg->serviceid) || + nla_put_string(skb, QCA_WLAN_VENDOR_ATTR_STATS_PARENT_IF, vap) || + nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_STATS_TYPE, cfg->type)) { + kfree_skb(skb); + return -ENOMEM; + } + + if (data_pending) { + multiple_reply_set = true; + data_pending = false; + /* Length to include the flag QCA_WLAN_VENDOR_ATTR_STATS_MULTI_REPLY */ + multiple_reply_len = nla_size; + } + + attr = nla_nest_start(skb, QCA_WLAN_VENDOR_ATTR_STATS_RECURSIVE); + for (i = feat; i < STATS_FEAT_MAX; i++) { + if (!stats->feat[i] || !stats->size[i]) + continue; + + rem_len = skb_tailroom(skb); + if (rem_len < 0) { + ath12k_err(NULL, "SAWF: skb is corrupted\n"); + kfree_skb(skb); + return -ECANCELED; + } + rem_len -= multiple_reply_len; + rem_len -= nla_size; + rem_len = (rem_len > 0) ? rem_len : 0; + + if (stats->size[i] >= rem_len) { + data_len = rem_len; + data = stats->feat[i] + storage; + stats->size[i] -= rem_len; + storage += data_len; + feat = i; + data_pending = true; + } else { + data_len = stats->size[i]; + data = stats->feat[i] + storage; + storage = 0; + } + if (nla_put(skb, i+1, data_len, data)) { + kfree_skb(skb); + return -ENOMEM; + } + + if (data_pending) + break; + } + + nla_nest_end(skb, attr); + + if (multiple_reply_set && nla_put_flag(skb, QCA_WLAN_VENDOR_ATTR_STATS_MULTI_REPLY)) { + kfree_skb(skb); + return -ENOMEM; + } + + ret = cfg80211_vendor_cmd_reply(skb); + if (ret) { + kfree_skb(skb); + ath12k_err(NULL, "SAWF: stats msg send failed with err=%d\n", ret); + return ret; + } + } while(data_pending); + + return ret; +} + +static int ath12k_vendor_telemetry_getstats(struct wiphy *wiphy, + struct wireless_dev *wdev, + const void *data, + int data_len) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_MAX + 1]; + struct stats_config cfg; + struct unified_stats *stats; + struct telemetry_sawfdelay_stats *delay_stats = NULL; + struct telemetry_sawftx_stats *tx_stats = NULL; + struct ath12k_base *ab = NULL; + int ret = 0, i; + u16 peer_id = 0xFFFF; + u8 mac_addr[ETH_ALEN] = { 0 }; + + if (!ath12k_sawf_enable) + return -EOPNOTSUPP; + + ret = nla_parse(tb, QCA_WLAN_VENDOR_ATTR_TELEMETRIC_MAX, data, data_len, + ath12k_telemetric_req_policy, NULL); + + if (ret) { + ath12k_err(NULL, "Invalid attribute with telemetry getstats command\n"); + return ret; + } + + memset(&cfg, 0, sizeof(struct stats_config)); + + if (wiphy) + cfg.wiphy = wiphy; + if (tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_LEVEL]) + cfg.lvl = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_LEVEL]); + if (tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_OBJECT]) + cfg.obj = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_OBJECT]); + if (tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_TYPE]) + cfg.type = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_TYPE]); + if (tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_AGGREGATE]) + cfg.aggregate = true; + if (tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_FEATURE_FLAG]) + cfg.feat = nla_get_u64(tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_FEATURE_FLAG]); + if (tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_STA_MAC] && + (nla_len(tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_STA_MAC]) == ETH_ALEN)) { + memcpy(mac_addr, nla_data(tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_STA_MAC]), ETH_ALEN); + cfg.mac = mac_addr; + } + if (tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_SERVICEID]) + cfg.serviceid = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_TELEMETRIC_SERVICEID]); + + if (!(cfg.feat)) + return -EINVAL; + + ab = ath12k_sawf_get_ab_from_netdev(wdev->netdev, mac_addr, &peer_id); + if (!ab) + return -ENODATA; + + stats = kzalloc(sizeof(struct unified_stats), GFP_KERNEL); + if (!stats) + return -ENOMEM; + + if (cfg.feat & STATS_FEAT_FLG_SAWFTX) { + tx_stats = kzalloc(sizeof(struct telemetry_sawftx_stats), GFP_KERNEL); + if (!tx_stats) { + ret = -ENOMEM; + goto end_stats; + } + stats->feat[STATS_FEAT_SAWFTX] = tx_stats; + stats->size[STATS_FEAT_SAWFTX] = sizeof(struct telemetry_sawftx_stats); + } + + if (cfg.feat & STATS_FEAT_FLG_SAWFDELAY) { + delay_stats = kzalloc(sizeof(struct telemetry_sawfdelay_stats), GFP_KERNEL); + if (!delay_stats) { + ret = -ENOMEM; + goto end_stats; + } + stats->feat[STATS_FEAT_SAWFDELAY] = delay_stats; + stats->size[STATS_FEAT_SAWFDELAY] = sizeof(struct telemetry_sawfdelay_stats); + } + + ret = telemetry_extract_data(&cfg, tx_stats, delay_stats, ab); + if (ret) + goto end_stats; + + ret = telemetry_build_nd_send_reply_msg(wiphy, &cfg, mac_addr, stats); + +end_stats: + for (i = 0; i < STATS_FEAT_MAX; i++) { + if (stats->feat[i]) + kfree(stats->feat[i]); + stats->feat[i] = NULL; + } + kfree(stats); + + return ret; +} + +static int ath12k_vendor_ds_handler(struct wiphy *wihpy, + struct wireless_dev *wdev, + const void *data, + int data_len) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_DS_MAX + 1]; + int ret = 0; + int ml_netdev = 0; + + if (!g_bonded_interface_model) + return 0; + + ret = nla_parse(tb, QCA_WLAN_VENDOR_ATTR_DS_MAX, data, data_len, + ath12k_ds_policy, NULL); + + if (ret) { + ath12k_err(NULL, "Invalid attribute with ds %d\n", ret); + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_CONFIG_EHT_MLO_MODE]) + ml_netdev = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_CONFIG_EHT_MLO_MODE]); + + ath12k_dbg(NULL, ATH12K_DBG_PPE, + "Marking dev [%s] as mlo netdev. %d\n", wdev->netdev->name, ml_netdev); + wdev->ml_netdev = ml_netdev; + + return 0; +} + +static int ath12k_vendor_telemetry_sla_reset_stats(struct nlattr *clr_stats) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_MAX + 1]; + int ret = 0; + u8 svc_id, mac_addr[ETH_ALEN] = { 0 }, mld_mac_addr[ETH_ALEN] = { 0 }, set_clear; + + ret = nla_parse_nested(tb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_MAX, + clr_stats, + ath12k_telemetric_sla_policy, NULL); + + if (ret) { + ath12k_err(NULL, "Invalid attribute with telemetry sla reset stats command\n"); + return ret; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SVC_ID]) + svc_id = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SVC_ID]); + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MAC] && + (nla_len(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MAC]) == ETH_ALEN)) + memcpy(mac_addr, nla_data(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MAC]), + ETH_ALEN); + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MLD_MAC] && + (nla_len(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MLD_MAC]) == ETH_ALEN)) + memcpy(mld_mac_addr, nla_data(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MLD_MAC]), + ETH_ALEN); + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SET_CLEAR]) + set_clear = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SET_CLEAR]); + + return ath12k_telemetry_sla_reset_stats(svc_id, mac_addr, mld_mac_addr, + set_clear); +} + +void ath12k_vendor_telemetry_notify_breach(struct ieee80211_vif *vif, u8 *mac_addr, + u8 svc_id, u8 param, bool set_clear, + u8 tid, u8 *mld_addr) +{ + struct nlattr *notify_params; + struct wireless_dev *wdev; + struct sk_buff *skb; + u8 access_category; + + wdev = ieee80211_vif_to_wdev(vif); + + if (!wdev) + return; + + if (!wdev->wiphy) + return; + + skb = cfg80211_vendor_event_alloc(wdev->wiphy, wdev, NLMSG_DEFAULT_SIZE, + 0, GFP_KERNEL); + if (!skb) { + ath12k_err(NULL, "No memory available to send notify breach event\n"); + return; + } + + switch (tid) { + case 0: + case 3: + access_category = 0; //AC_BE + break; + case 1: + case 2: + access_category = 1; //AC_BK + break; + case 4: + case 5: + access_category = 2; //AC_VI + break; + case 6: + case 7: + access_category = 3; //AC_VO + break; + default: + ath12k_err(NULL, "Invalid TID = %u for notifying breach event\n", tid); + goto err; + } + + notify_params = nla_nest_start(skb, QCA_WLAN_VENDOR_ATTR_SDWF_DEV_SLA_BREACHED_PARAMS); + if (nla_put(skb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MAC, ETH_ALEN, mac_addr) || + (mld_addr && nla_put(skb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MLD_MAC, + ETH_ALEN, mld_addr)) || + nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SVC_ID, svc_id) || + nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_TYPE, param) || + nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SET_CLEAR, set_clear) || + nla_put_u8(skb, QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_AC, access_category)) { + ath12k_err(NULL, "No memory available at NL to send notify breach event\n"); + goto err; + } + + nla_nest_end(skb, notify_params); + cfg80211_vendor_event(skb, GFP_KERNEL); + return; +err: + kfree(skb); + return; +} + +static int ath12k_vendor_sdwf_phy_operations(struct wiphy *wiphy, + struct wireless_dev *wdev, + const void *data, + int data_len) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_MAX + 1]; + u8 sdwf_oper; + int ret = 0; + + if (!ath12k_sawf_enable) + return -EOPNOTSUPP; + + ret = nla_parse(tb, QCA_WLAN_VENDOR_ATTR_SDWF_PHY_MAX, data, data_len, + ath12k_vendor_sdwf_phy_policy, NULL); + if (ret) { + ath12k_err(NULL, "Invalid attributes with SAWF radio level commands\n"); + goto end; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_OPERATION]) { + sdwf_oper = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_OPERATION]); + } else { + ath12k_err(NULL, "SAWF radio level operation missing\n"); + ret = -EINVAL; + goto end; + } + + switch (sdwf_oper) { + case QCA_WLAN_VENDOR_SDWF_PHY_OPER_SVC_SET: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS]) { + ret = ath12k_vendor_set_sdwf_config(wiphy, wdev, + tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS]); + } else { + ath12k_err(NULL, "SAWF svc parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_PHY_OPER_SVC_DEL: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS]) { + ret = ath12k_vendor_disable_sdwf_config(tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS]); + } else { + ath12k_err(NULL, "SAWF service id missing with delete operation\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_PHY_OPER_SLA_SAMPLES_SET: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_SAMPLES_PARAMS]) { + ret = ath12k_vendor_telemetry_sdwf_sla_samples_config(tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_SAMPLES_PARAMS]); + } else { + ath12k_err(NULL, "SAWF sla samples parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_PHY_OPER_SLA_BREACH_DETECTION_SET: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_DETECT_PARAMS]) { + ret = ath12k_vendor_telemetry_sdwf_sla_detection_config(tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_DETECT_PARAMS]); + } else { + ath12k_err(NULL, "SAWF sla breach detect parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_PHY_OPER_SLA_THRESHOLD_SET: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_THRESHOLD_PARAMS]) { + ret = ath12k_vendor_telemetry_sdwf_sla_thershold_config(tb[QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_THRESHOLD_PARAMS]); + } else { + ath12k_err(NULL, "SAWF sla threshold parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + default: + ath12k_err(NULL, "Invalid operation with SAWF radio level commands\n"); + ret = -EINVAL; + } +end: + return ret; +} + +static int ath12k_vendor_sdwf_dev_operations(struct wiphy *wiphy, + struct wireless_dev *wdev, + const void *data, + int data_len) +{ + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_MAX + 1]; + u8 sdwf_oper; + int ret = 0; + + if (!ath12k_sawf_enable) + return -EOPNOTSUPP; + + ret = nla_parse(tb, QCA_WLAN_VENDOR_ATTR_SDWF_DEV_MAX, data, data_len, + ath12k_vendor_sdwf_dev_policy, NULL); + if (ret) { + ath12k_err(NULL, "Invalid attributes with SAWF device level commands\n"); + goto end; + } + + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_OPERATION]) { + sdwf_oper = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_OPERATION]); + } else { + ath12k_err(NULL, "SAWF device level operation missing\n"); + ret = -EINVAL; + goto end; + } + + switch (sdwf_oper) { + case QCA_WLAN_VENDOR_SDWF_DEV_OPER_DEF_Q_MAP: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS]) { + ret = ath12k_vendor_sdwf_def_qmap_req(wdev, + tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS]); + } else { + ath12k_err(NULL, "SAWF default Queue map parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_DEV_OPER_DEF_Q_UNMAP: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS]) { + ret = ath12k_vendor_sdwf_def_qunmap_req(wdev, tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS]); + } else { + ath12k_err(NULL, "SAWF default Queue unmap parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_DEV_OPER_DEF_Q_MAP_GET: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS]) { + ret = ath12k_vendor_sdwf_def_qmap_report_req(wdev, tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS]); + } else { + ath12k_err(NULL, "SAWF default Queue map report parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_DEV_OPER_STREAMING_STATS: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_STREAMING_STATS_PARAMS]) { + ret = ath12k_vendor_sdwf_streaming_stats_configure(wdev, tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_STREAMING_STATS_PARAMS]); + } else { + ath12k_err(NULL, "SAWF default streaming statsparameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + case QCA_WLAN_VENDOR_SDWF_DEV_OPER_RESET_STATS: + if (tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_RESET_STATS]) { + ret = ath12k_vendor_telemetry_sla_reset_stats(tb[QCA_WLAN_VENDOR_ATTR_SDWF_DEV_RESET_STATS]); + } else { + ath12k_err(NULL, "SAWF clear telemetry stats parameters missing\n"); + ret = -EINVAL; + goto end; + } + break; + default: + ath12k_err(NULL, "Invalid operation = %d with SAWF device level commands\n", sdwf_oper); + ret = -EINVAL; + } +end: + return ret; +} +#endif /* CONFIG_ATH12K_SAWF */ + +#define NL_VENDOR_GET_ATTR(res, info, attr, bit) \ + do { \ + struct nlattr *nl_attr; \ + nl_attr = info[QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_##attr]; \ + if (nl_attr) \ + res = nla_get_u##bit(nl_attr); \ + } while (0) + +static int ath12k_vendor_set_scs_qos_params(struct wiphy *wihpy, + struct wireless_dev *wdev, + const void *data, + int data_len) +{ + struct nlattr *info[QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_MAX + 1]; + struct ath12k_latency_params params = { 0 }; + u8 *peer_mac; + int ret; + + ret = nla_parse(info, QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_MAX, + data, data_len, ath12k_vendor_scs_config_policy, NULL); + if (ret) { + ath12k_err(NULL, "Invalid SCS attributes\n"); + return ret; + } + + NL_VENDOR_GET_ATTR(params.service_interval, info, SERVICE_INTERVAL, 32); + NL_VENDOR_GET_ATTR(params.burst_size, info, BURST_SIZE, 32); + NL_VENDOR_GET_ATTR(params.delay_bound, info, DELAY_BOUND, 32); + NL_VENDOR_GET_ATTR(params.min_data_rate, info, MINIMUM_DATA_RATE, 32); + NL_VENDOR_GET_ATTR(params.req_type, info, REQUEST_TYPE, 8); + NL_VENDOR_GET_ATTR(params.user_priority, info, USER_PRIORITY, 8); + NL_VENDOR_GET_ATTR(params.ac, info, ACCESS_CATEGORY, 8); + NL_VENDOR_GET_ATTR(params.direction, info, DIRECTION, 8); + if (info[QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DST_MAC_ADDR]) { + peer_mac = nla_data(info[QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DST_MAC_ADDR]); + memcpy(params.peer_mac, peer_mac, ETH_ALEN); + } + + ret = ath12k_mac_op_set_scs(wdev, ¶ms); + + return ret; +} + +static struct wiphy_vendor_command ath12k_vendor_commands[] = { +#ifdef CONFIG_ATH12K_SAWF + { + .info.vendor_id = QCA_NL80211_VENDOR_ID, + .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_SDWF_PHY_OPS, + .doit = ath12k_vendor_sdwf_phy_operations, + .dumpit = ath12k_vendor_view_sdwf_config, + .policy = ath12k_vendor_sdwf_phy_policy, + .maxattr = QCA_WLAN_VENDOR_ATTR_SDWF_PHY_MAX, + }, + { + .info.vendor_id = QCA_NL80211_VENDOR_ID, + .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_SDWF_DEV_OPS, + .doit = ath12k_vendor_sdwf_dev_operations, + .policy = ath12k_vendor_sdwf_dev_policy, + .maxattr = QCA_WLAN_VENDOR_ATTR_SDWF_DEV_MAX, + .flags = WIPHY_VENDOR_CMD_NEED_NETDEV, + }, + { + .info.vendor_id = QCA_NL80211_VENDOR_ID, + .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_TELEMETRIC_DATA, + .doit = ath12k_vendor_telemetry_getstats, + .policy = ath12k_telemetric_req_policy, + .maxattr = QCA_WLAN_VENDOR_ATTR_TELEMETRIC_MAX, + .flags = WIPHY_VENDOR_CMD_NEED_NETDEV, + }, + { + .info.vendor_id = QCA_NL80211_VENDOR_ID, + .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_SET_WIFI_CONFIGURATION, + .doit = ath12k_vendor_ds_handler, + .policy = ath12k_ds_policy, + .maxattr = QCA_WLAN_VENDOR_ATTR_DS_MAX, + .flags = WIPHY_VENDOR_CMD_NEED_NETDEV, + }, +#endif /* CONFIG_ATH12K_SAWF */ + { + .info.vendor_id = QCA_NL80211_VENDOR_ID, + .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_SCS_RULE_CONFIG, + .doit = ath12k_vendor_set_scs_qos_params, + .policy = ath12k_vendor_scs_config_policy, + .maxattr = QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_MAX, + .flags = WIPHY_VENDOR_CMD_NEED_NETDEV, + }, +}; + +static const struct nl80211_vendor_cmd_info ath12k_vendor_events[] = { +#ifdef CONFIG_ATH12K_SAWF + { + .vendor_id = QCA_NL80211_VENDOR_ID, + .subcmd = QCA_NL80211_VENDOR_SUBCMD_SDWF_DEV_OPS, + }, +#endif +}; + +int ath12k_vendor_register(struct ath12k_hw *ah) +{ + ah->hw->wiphy->vendor_commands = ath12k_vendor_commands; + ah->hw->wiphy->n_vendor_commands = ARRAY_SIZE(ath12k_vendor_commands); + ah->hw->wiphy->vendor_events = ath12k_vendor_events; + ah->hw->wiphy->n_vendor_events = ARRAY_SIZE(ath12k_vendor_events); + return 0; +} --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/ath12k/vendor.h 2024-03-18 14:40:14.859741552 +0100 @@ -0,0 +1,590 @@ +// SPDX-License-Identifier: BSD-3-Clause-Clear +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ +#ifndef ATH12K_VENDOR_H +#define ATH12K_VENDOR_H + +#define QCA_NL80211_VENDOR_ID 0x001374 + +enum qca_nl80211_vendor_subcmds { + /* Wi-Fi configuration subcommand */ + QCA_NL80211_VENDOR_SUBCMD_SET_WIFI_CONFIGURATION = 74, + QCA_NL80211_VENDOR_SUBCMD_SCS_RULE_CONFIG = 218, +#ifdef CONFIG_ATH12K_SAWF + QCA_NL80211_VENDOR_SUBCMD_SDWF_PHY_OPS = 235, + QCA_NL80211_VENDOR_SUBCMD_SDWF_DEV_OPS = 236, + QCA_NL80211_VENDOR_SUBCMD_TELEMETRIC_DATA = 334, +#endif +}; + +#ifdef CONFIG_ATH12K_SAWF +enum qca_wlan_vendor_attr_sdwf_phy { + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_OPERATION = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SVC_PARAMS = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_SAMPLES_PARAMS = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_DETECT_PARAMS = 4, + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_SLA_THRESHOLD_PARAMS = 5, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_PHY_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_sdwf_phy_oper { + QCA_WLAN_VENDOR_SDWF_PHY_OPER_SVC_SET = 0, + QCA_WLAN_VENDOR_SDWF_PHY_OPER_SVC_DEL = 1, + QCA_WLAN_VENDOR_SDWF_PHY_OPER_SVC_GET = 2, + QCA_WLAN_VENDOR_SDWF_PHY_OPER_SLA_SAMPLES_SET = 3, + QCA_WLAN_VENDOR_SDWF_PHY_OPER_SLA_BREACH_DETECTION_SET = 4, + QCA_WLAN_VENDOR_SDWF_PHY_OPER_SLA_THRESHOLD_SET = 5, +}; + +enum qca_wlan_vendor_attr_sdwf_svc { + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_ID = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MIN_TP = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX_TP = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_BURST_SIZE = 4, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_INTERVAL = 5, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_DELAY_BOUND = 6, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_TTL = 7, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_PRIO = 8, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_TID = 9, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MSDU_RATE_LOSS = 10, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_SVC_INTERVAL = 11, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MIN_TPUT = 12, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MAX_LATENCY = 13, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_BURST_SIZE = 14, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_OFDMA_DISABLE = 15, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_UL_MU_MIMO_DISABLE = 16, + /* The below are used by MCC */ + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_BUFFER_LATENCY_TOLERANCE = 17, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_TX_TRIGGER_DSCP = 18, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_TX_REPLACE_DSCP = 19, + + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_SVC_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_attr_sdwf_sla_samples { + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MOVING_AVG_PKT = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MOVING_AVG_WIN = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_SLA_NUM_PKT = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_SLA_TIME_SEC = 4, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_SAMPLES_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_attr_sdwf_sla_detect { + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_PARAM = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MIN_TP = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MAX_TP = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_BURST_SIZE = 4, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_INTERVAL = 5, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_DELAY_BOUND = 6, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MSDU_TTL = 7, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MSDU_RATE_LOSS = 8, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_DETECT_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_sdwf_sla_detect_param { + QCA_WLAN_VENDOR_SDWF_SLA_DETECT_PARAM_NUM_PACKET, + QCA_WLAN_VENDOR_SDWF_SLA_DETECT_PARAM_PER_SECOND, + QCA_WLAN_VENDOR_SDWF_SLA_DETECT_PARAM_MOV_AVG, + QCA_WLAN_VENDOR_SDWF_SLA_DETECT_PARAM_NUM_SECOND, + QCA_WLAN_VENDOR_SDWF_SLA_DETECT_PARAM_MAX, +}; + +enum qca_wlan_vendor_attr_sdwf_sla_threshold { + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_SVC_ID = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MIN_TP = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MAX_TP = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_BURST_SIZE = 4, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_INTERVAL = 5, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_DELAY_BOUND = 6, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MSDU_TTL = 7, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MSDU_RATE_LOSS = 8, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_THRESHOLD_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_attr_sdwf_dev { + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_OPERATION = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_DEF_Q_PARAMS = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_STREAMING_STATS_PARAMS = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_RESET_STATS = 4, + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_SLA_BREACHED_PARAMS = 5, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_DEV_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_sdwf_dev_oper { + QCA_WLAN_VENDOR_SDWF_DEV_OPER_DEF_Q_MAP = 0, + QCA_WLAN_VENDOR_SDWF_DEV_OPER_DEF_Q_UNMAP = 1, + QCA_WLAN_VENDOR_SDWF_DEV_OPER_DEF_Q_MAP_GET = 2, + QCA_WLAN_VENDOR_SDWF_DEV_OPER_STREAMING_STATS = 3, + QCA_WLAN_VENDOR_SDWF_DEV_OPER_RESET_STATS = 4, + QCA_WLAN_VENDOR_SDWF_DEV_OPER_BREACH_DETECTED = 5, +}; + +enum qca_wlan_vendor_attr_sdwf_def_q_map { + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_SVC_ID = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAC_ADDR = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_TID = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_STATUS = 4, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_DEF_Q_MAP_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_attr_sdwf_streaming_stats { + QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_BASIC_STATS = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_EXTND_STATS = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_MLO_LINK_ID = 3, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_STREAMING_AFTER_LAST - 1, +}; + +enum qca_wlan_vendor_attr_sdwf_sla_breach_param { + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MAC = 1, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SVC_ID = 2, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_TYPE = 3, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_SET_CLEAR = 4, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_PEER_MLD_MAC = 5, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_AC = 6, + + /* Keep last */ + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_MAX = + QCA_WLAN_VENDOR_ATTR_SDWF_SLA_BREACH_PARAM_AFTER_LAST - 1 +}; + +enum qca_wlan_vendor_sdwf_sla_breach_type { + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_INVALID = 0, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_MIN_THROUGHPUT, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_MAX_THROUGHPUT, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_BURST_SIZE, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_SERVICE_INTERVAL, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_DELAY_BOUND, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_MSDU_TTL, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_MSDU_LOSS, + QCA_WLAN_VENDOR_SDWF_SLA_BREACH_PARAM_TYPE_MAX, +}; + +/** + * enum qca_wlan_vendor_attr_telemetric: Defines attributes to be used in + * request message of QCA_NL80211_VENDOR_SUBCMD_TELEMETRIC_DATA vendor command. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_LEVEL: Defines stats levels like Basic or + * Advance or Debug. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_OBJECT: Defines stats objects like STA or + * VAP or Radio or SoC. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_TYPE: Defines stats types like Data or + * control. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_AGGREGATE: Defines aggregation flag for + * driver agrregation. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_FEATURE_FLAG: Defines feature flags for + * which stats is requested. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_STA_MAC: Defines STA MAC Address if the + * request is for particular STA object. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_SERVICEID: Defines serviceid for sawf stats. + * + * @QCA_WLAN_VENDOR_ATTR_TELEMETRIC_MAX: Defines maximum attribute counts to be + * used in QCA_NL80211_VENDOR_SUBCMD_TELEMETRIC_DATA vendor command request. + */ +enum qca_wlan_vendor_attr_telemetric { + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_LEVEL = 1, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_OBJECT, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_TYPE, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_AGGREGATE, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_FEATURE_FLAG, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_STA_MAC, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_SERVICEID, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_MLD_LINK, + + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_MAX = + QCA_WLAN_VENDOR_ATTR_TELEMETRIC_AFTER_LAST -1, +}; + +/** + * enum qca_wlan_vendor_attr_stats: Defines attributes to be used in response of + * QCA_NL80211_VENDOR_SUBCMD_TELEMETRIC_DATA vendor command. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_LEVEL: Used for stats levels like Basic or + * Advance or Debug. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_OBJECT: Required (u8) + * Used with the command, carrying stats, to specify for which stats_object enum. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_OBJ_ID: Used for Object ID like for STA MAC + * address or for VAP or Radio or SoC respective interface name. + * + * QCA_WLAN_VENDOR_ATTR_STATS_SERVICEID: Used for sawf levels stats like per + * peer or per peer per serviceclass. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_PARENT_IF: Used for Parent Object interface name + * like for STA VAP name, for VAP Radio interface name and for Radio SoC + * interface name. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_TYPE: Used for stats types like Data or + * control. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_RECURSIVE: Required (NESTED Flag) + * Used with the command to specify the nested stats. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_MULTI_REPLY: Set this flag if current reply + * messageis holding data from previous reply. + * + * @QCA_WLAN_VENDOR_ATTR_STATS_MAX: Defines maximum attriutes can be used in + * QCA_NL80211_VENDOR_SUBCMD_TELEMETRIC_DATA vendor command response. + */ + +enum qca_wlan_vendor_attr_stats { + QCA_WLAN_VENDOR_ATTR_STATS_LEVEL = 1, + QCA_WLAN_VENDOR_ATTR_STATS_OBJECT, + QCA_WLAN_VENDOR_ATTR_STATS_OBJ_ID, + QCA_WLAN_VENDOR_ATTR_STATS_SERVICEID, + QCA_WLAN_VENDOR_ATTR_STATS_PARENT_IF, + QCA_WLAN_VENDOR_ATTR_STATS_TYPE, + QCA_WLAN_VENDOR_ATTR_STATS_RECURSIVE, + QCA_WLAN_VENDOR_ATTR_STATS_MULTI_REPLY, + QCA_WLAN_VENDOR_ATTR_STATS_MAX, +}; + +struct telemetry_sawf_tx_stat { + struct dp_pkt_info tx_success; + struct dp_pkt_info tx_ingress; + struct { + struct dp_pkt_info fw_rem; + u32 fw_rem_notx; + u32 fw_rem_tx; + u32 age_out; + u32 fw_reason1; + u32 fw_reason2; + u32 fw_reason3; + } dropped; + struct sawf_fw_mpdu_stats svc_intval_stats; + struct sawf_fw_mpdu_stats burst_size_stats; + u32 tx_failed; + u32 queue_depth; + u32 throughput; + u32 ingress_rate; +}; + +struct telemetry_sawftx_stats { + struct telemetry_sawf_tx_stat tx[ATH12K_SAWF_MAX_TID_SUPPORT][MAX_Q_PER_TID]; + u8 tid; + u8 msduq; +}; + +struct telemetry_sawf_delay_stat { + struct ath12k_delay_hist_stats delay_hist; + u8 cur_win; + u32 nwdelay_avg; + u32 swdelay_avg; + u32 hwdelay_avg; + u64 delay_bound_success; + u64 delay_bound_failure; +}; + +struct telemetry_sawfdelay_stats { + struct telemetry_sawf_delay_stat delay[ATH12K_SAWF_MAX_TID_SUPPORT][MAX_Q_PER_TID]; + u8 tid; + u8 msduq; +}; + +/** + * enum qca_wlan_vendor_attr_feat: Defines nested attributes to be used in + * response of QCA_NL80211_VENDOR_SUBCMD_TELEMETRIC_DATA vendor command. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_ME: Used for Multicast Enhancement stats for a + * particular stats object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_RX: Used for Rx stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_TX: Used for Tx stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_AST: Used for AST stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_CFR: Used for CFR stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_FWD: Used for BSS stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_RAW: Used for RAW mode stats for a particular + * object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_TSO: Used for TSO stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_TWT: Used for TWT stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_VOW: Used for VOW stats for a particular object. +* + * @QCA_WLAN_VENDOR_ATTR_FEAT_WDI: Used for WDI stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_WMI: Used for WMI stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_IGMP: Used for IGMP stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_LINK: Used for Link related stats for a particular + * object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_MESH: Used for Mesh related stats for a particular + * object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_RATE: Used for Rate stats for a particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_NAWDS: Used for NAWDS related stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_DELAY: Used for DELAY related stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_JITTER: Used for JITTER related stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_TXCAP: Used for TXCAP realted stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_MONITOR: Used for MONITOR realted stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_SAWFDELAY: Used for SAWFDELAY related stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_SAWFTX: Used for SAWFTX related stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_DETER: Used for DETERMINISTIC related stats for a + * particular object. + * + * @QCA_WLAN_VENDOR_ATTR_FEAT_MAX: Defines Maximum count of feature attributes. + */ +enum qca_wlan_vendor_attr_feat { + QCA_WLAN_VENDOR_ATTR_FEAT_ME = 1, + QCA_WLAN_VENDOR_ATTR_FEAT_RX, + QCA_WLAN_VENDOR_ATTR_FEAT_TX, + QCA_WLAN_VENDOR_ATTR_FEAT_AST, + QCA_WLAN_VENDOR_ATTR_FEAT_CFR, + QCA_WLAN_VENDOR_ATTR_FEAT_FWD, + QCA_WLAN_VENDOR_ATTR_FEAT_RAW, + QCA_WLAN_VENDOR_ATTR_FEAT_TSO, + QCA_WLAN_VENDOR_ATTR_FEAT_TWT, + QCA_WLAN_VENDOR_ATTR_FEAT_VOW, + QCA_WLAN_VENDOR_ATTR_FEAT_WDI, + QCA_WLAN_VENDOR_ATTR_FEAT_WMI, + QCA_WLAN_VENDOR_ATTR_FEAT_IGMP, + QCA_WLAN_VENDOR_ATTR_FEAT_LINK, + QCA_WLAN_VENDOR_ATTR_FEAT_MESH, + QCA_WLAN_VENDOR_ATTR_FEAT_RATE, + QCA_WLAN_VENDOR_ATTR_FEAT_NAWDS, + QCA_WLAN_VENDOR_ATTR_FEAT_DELAY, + QCA_WLAN_VENDOR_ATTR_FEAT_JITTER, + QCA_WLAN_VENDOR_ATTR_FEAT_TXCAP, + QCA_WLAN_VENDOR_ATTR_FEAT_MONITOR, + QCA_WLAN_VENDOR_ATTR_FEAT_SAWFDELAY, + QCA_WLAN_VENDOR_ATTR_FEAT_SAWFTX, + QCA_WLAN_VENDOR_ATTR_FEAT_DETER, + /** + * New attribute must be add before this. + * Also define the corresponding feature + * index in enum stats_feat. + */ + QCA_WLAN_VENDOR_ATTR_FEAT_MAX, +}; + +enum stats_feat { + STATS_FEAT_ME, + STATS_FEAT_RX, + STATS_FEAT_TX, + STATS_FEAT_AST, + STATS_FEAT_CFR, + STATS_FEAT_FWD, + STATS_FEAT_RAW, + STATS_FEAT_TSO, + STATS_FEAT_TWT, + STATS_FEAT_VOW, + STATS_FEAT_WDI, + STATS_FEAT_WMI, + STATS_FEAT_IGMP, + STATS_FEAT_LINK, + STATS_FEAT_MESH, + STATS_FEAT_RATE, + STATS_FEAT_NAWDS, + STATS_FEAT_DELAY, + STATS_FEAT_JITTER, + STATS_FEAT_TXCAP, + STATS_FEAT_MONITOR, + STATS_FEAT_SAWFDELAY, + STATS_FEAT_SAWFTX, + STATS_FEAT_DETER, + STATS_FEAT_MAX, +}; + +/** + * enum stats_level: Defines detailing levels + * @STATS_LVL_BASIC: Very minimal stats data + * @STATS_LVL_ADVANCE: Mostly feature specific stats data + * @STATS_LVL_DEBUG: Stats data for debug purpose + * @STATS_LVL_MAX: Max supported Stats levels + */ +enum stats_level { + STATS_LVL_BASIC, + STATS_LVL_ADVANCE, + STATS_LVL_DEBUG, + STATS_LVL_MAX = STATS_LVL_DEBUG, +}; + +/** + * enum stats_object: Defines the Stats specific to object + * @STATS_OBJ_STA: Stats for station/peer associated to AP + * @STATS_OBJ_VAP: Stats for VAP + * @STATS_OBJ_MLD: Stats for MLD group + * @STATS_OBJ_RADIO: Stats for particular Radio + * @STATS_OBJ_AP: Stats for SoC + * @STATS_OBJ_MAX: Max supported objects + */ +enum stats_object { + STATS_OBJ_STA, + STATS_OBJ_VAP, + STATS_OBJ_MLD, + STATS_OBJ_RADIO, + STATS_OBJ_AP, + STATS_OBJ_MAX = STATS_OBJ_AP, +}; + +/** + * enum stats_type: Defines the Stats for specific category + * @STATS_TYPE_DATA: Stats for Data frames + * @STATS_TYPE_CTRL: Stats for Control/Management frames + * @STATS_TYPE_MAX: Max supported types + */ +enum stats_type { + STATS_TYPE_DATA, + STATS_TYPE_CTRL, + STATS_TYPE_MAX = STATS_TYPE_CTRL, +}; + +/** + * struct stats_config: Structure to hold user configurations + * @wiphy: Pointer to wiphy structure which came as part of User request + * @feat: Feat flag set to dedicated bit of this field + * @lvl: Requested level of Stats (i.e. Basic, Advance or Debug) + * @obj: Requested stats for object (i.e. AP, Radio, Vap or STA) + * @type: Requested stats category + * @aggregate: Aggregate in driver + * @serviceid: service id for checking the level of sawf stats + */ +struct stats_config { + struct wiphy *wiphy; + u64 feat; + enum stats_level lvl; + enum stats_object obj; + enum stats_type type; + bool aggregate; + u8 serviceid; + u8 *mac; +}; + +#define STATS_FEAT_FLG_SAWFDELAY 0x00400000 +#define STATS_FEAT_FLG_SAWFTX 0x00800000 +/** + * struct unified_stats: Structure to carry all feature specific stats in driver + * level for stats response setup + * All features are void pointers and its corresponding sizes. + * This can hold Basic or Advance or Debug structures independently. + */ +struct unified_stats { + void *feat[STATS_FEAT_MAX]; + u_int32_t size[STATS_FEAT_MAX]; +}; + +enum qca_wlan_vendor_attr_ds { + QCA_WLAN_VENDOR_ATTR_DS_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_CONFIG_EHT_MLO_MODE = 90, + /* Keep last */ + QCA_WLAN_VENDOR_ATTR_DS_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_DS_MAX = + QCA_WLAN_VENDOR_ATTR_DS_AFTER_LAST - 1 +}; + +void ath12k_vendor_telemetry_notify_breach(struct ieee80211_vif *vif, u8 *mac_addr, + u8 svc_id, u8 param, bool set_clear, + u8 tid, u8 *mld_addr); +#endif /* CONFIG_ATH12K_SAWF */ + +int ath12k_vendor_register(struct ath12k_hw *ah); + +enum qca_wlan_vendor_attr_scs_rule_config { + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_RULE_ID = 1, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_REQUEST_TYPE = 2, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_OUTPUT_TID = 3, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_CLASSIFIER_TYPE = 4, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_VERSION = 5, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_SRC_IPV4_ADDR = 6, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_DST_IPV4_ADDR = 7, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_SRC_IPV6_ADDR = 8, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_DST_IPV6_ADDR = 9, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_SRC_PORT = 10, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_DST_PORT = 11, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_DSCP = 12, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_NEXT_HEADER = 13, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS4_FLOW_LABEL = 14, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS10_PROTOCOL_INSTANCE = 15, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS10_NEXT_HEADER = 16, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS10_FILTER_MASK = 17, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_TCLAS10_FILTER_VALUE = 18, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_SERVICE_CLASS_ID = 19, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DST_MAC_ADDR = 20, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_NETDEV_IF_INDEX = 21, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_SERVICE_INTERVAL = 22, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_BURST_SIZE = 23, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DELAY_BOUND = 24, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_MINIMUM_DATA_RATE = 25, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_USER_PRIORITY = 26, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_ACCESS_CATEGORY = 27, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_DIRECTION = 28, + + /* Keep last */ + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_MAX = + QCA_WLAN_VENDOR_ATTR_SCS_RULE_CONFIG_AFTER_LAST - 1, +}; + +#endif /* QCA_VENDOR_H */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/net/wireless/ath/testmode_i.h 2023-10-05 12:33:41.379635169 +0200 @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: BSD-3-Clause-Clear */ +/* + * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* "API" level of the ath testmode interface. Bump it after every + * incompatible interface change. + */ +#define ATH_TESTMODE_VERSION_MAJOR 1 + +/* Bump this after every _compatible_ interface change, for example + * addition of a new command or an attribute. + */ +#define ATH_TESTMODE_VERSION_MINOR 0 + +#define ATH_TM_DATA_MAX_LEN 5000 +#define ATH_FTM_EVENT_MAX_BUF_LENGTH 2048 + +enum ath_tm_attr { + __ATH_TM_ATTR_INVALID = 0, + ATH_TM_ATTR_CMD = 1, + ATH_TM_ATTR_DATA = 2, + ATH_TM_ATTR_WMI_CMDID = 3, + ATH_TM_ATTR_VERSION_MAJOR = 4, + ATH_TM_ATTR_VERSION_MINOR = 5, + ATH_TM_ATTR_WMI_OP_VERSION = 6, + ATH_TM_ATTR_FWLOG = 7, + ATH_TM_ATTR_DUAL_MAC = 9, + + /* keep last */ + __ATH_TM_ATTR_AFTER_LAST, + ATH_TM_ATTR_MAX = __ATH_TM_ATTR_AFTER_LAST - 1, +}; + +/* All ath testmode interface commands specified in + * ATH_TM_ATTR_CMD + */ +enum ath_tm_cmd { + /* Returns the supported ath testmode interface version in + * ATH_TM_ATTR_VERSION. Always guaranteed to work. User space + * uses this to verify it's using the correct version of the + * testmode interface + */ + ATH_TM_CMD_GET_VERSION = 0, + + /* Set ar state to test mode. */ + ATH_TM_CMD_TESTMODE_START = 1, + + /* Set ar state back into OFF state. */ + ATH_TM_CMD_TESTMODE_STOP = 2, + + /* The command used to transmit a WMI command to the firmware and + * the event to receive WMI events from the firmware. Without + * struct wmi_cmd_hdr header, only the WMI payload. Command id is + * provided with ATH_TM_ATTR_WMI_CMDID and payload in + * ATH_TM_ATTR_DATA. + */ + ATH_TM_CMD_WMI = 3, + + /* The command used to transmit a FTM WMI command to the firmware + * and the event to receive WMI events from the firmware. The data + * received only contain the payload. Need to add the tlv + * header and send the cmd to fw with commandid WMI_PDEV_UTF_CMDID. + */ + ATH_TM_CMD_WMI_FTM = 4, +}; diff -Nruw linux-6.4-fbx/drivers/net/wireless/marvell/mwl8k_new./Makefile linux-6.4-fbx/drivers/net/wireless/marvell/mwl8k_new/Makefile --- linux-6.4-fbx/drivers/net/wireless/marvell/mwl8k_new./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/net/wireless/marvell/mwl8k_new/Makefile 2023-03-10 17:18:24.474042758 +0100 @@ -0,0 +1,12 @@ +mwl8k_new-$(CONFIG_DEBUG_FS) += debugfs.o +mwl8k_new-y += fw.o +mwl8k_new-y += main.o +mwl8k_new-y += utils.o + +mwl8k_new-y += svc_console.o +mwl8k_new-y += svc_dma_test.o +mwl8k_new-y += svc_vtty.o + +mwl8k_new-y += wifi_core.o + +obj-$(CONFIG_MWL8K_NEW) += mwl8k_new.o --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/of/configfs.c 2023-02-27 20:55:42.852893915 +0100 @@ -0,0 +1,279 @@ +/* + * Configfs entries for device-tree + * + * Copyright (C) 2013 - Pantelis Antoniou + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "of_private.h" + +struct cfs_overlay_item { + struct config_item item; + + char path[PATH_MAX]; + + const struct firmware *fw; + struct device_node *overlay; + int ov_id; + + void *dtbo; + int dtbo_size; +}; + +static inline struct cfs_overlay_item *to_cfs_overlay_item( + struct config_item *item) +{ + return item ? container_of(item, struct cfs_overlay_item, item) : NULL; +} + +static ssize_t cfs_overlay_item_path_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + return sprintf(page, "%s\n", overlay->path); +} + +static ssize_t cfs_overlay_item_path_store(struct config_item *item, + const char *page, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + const char *p = page; + char *s; + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy to path buffer (and make sure it's always zero terminated */ + count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); + overlay->path[sizeof(overlay->path) - 1] = '\0'; + + /* strip trailing newlines */ + s = overlay->path + strlen(overlay->path); + while (s > overlay->path && *--s == '\n') + *s = '\0'; + + pr_debug("%s: path is '%s'\n", __func__, overlay->path); + + err = request_firmware(&overlay->fw, overlay->path, NULL); + if (err != 0) + goto out_err; + + err = of_overlay_fdt_apply((void *)overlay->fw->data, + overlay->fw->size, + &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + + release_firmware(overlay->fw); + overlay->fw = NULL; + + overlay->path[0] = '\0'; + return err; +} + +static ssize_t cfs_overlay_item_status_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + return sprintf(page, "%s\n", + overlay->ov_id >= 0 ? "applied" : "unapplied"); +} + +CONFIGFS_ATTR(cfs_overlay_item_, path); +CONFIGFS_ATTR_RO(cfs_overlay_item_, status); + +static struct configfs_attribute *cfs_overlay_attrs[] = { + &cfs_overlay_item_attr_path, + &cfs_overlay_item_attr_status, + NULL, +}; + +ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, + void *buf, size_t max_count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + pr_debug("%s: buf=%p max_count=%zu\n", __func__, + buf, max_count); + + if (overlay->dtbo == NULL) + return 0; + + /* copy if buffer provided */ + if (buf != NULL) { + /* the buffer must be large enough */ + if (overlay->dtbo_size > max_count) + return -ENOSPC; + + memcpy(buf, overlay->dtbo, overlay->dtbo_size); + } + + return overlay->dtbo_size; +} + +ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, + const void *buf, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy the contents */ + overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); + if (overlay->dtbo == NULL) + return -ENOMEM; + + overlay->dtbo_size = count; + + err = of_overlay_fdt_apply((void *)overlay->fw->data, + overlay->dtbo_size, + &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + kfree(overlay->dtbo); + overlay->dtbo = NULL; + overlay->dtbo_size = 0; + + return err; +} + +CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); + +static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { + &cfs_overlay_item_attr_dtbo, + NULL, +}; + +static void cfs_overlay_release(struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + if (overlay->ov_id >= 0) + of_overlay_remove(&overlay->ov_id); + if (overlay->fw) + release_firmware(overlay->fw); + /* kfree with NULL is safe */ + kfree(overlay->dtbo); + kfree(overlay); +} + +static struct configfs_item_operations cfs_overlay_item_ops = { + .release = cfs_overlay_release, +}; + +static struct config_item_type cfs_overlay_type = { + .ct_item_ops = &cfs_overlay_item_ops, + .ct_attrs = cfs_overlay_attrs, + .ct_bin_attrs = cfs_overlay_bin_attrs, + .ct_owner = THIS_MODULE, +}; + +static struct config_item *cfs_overlay_group_make_item( + struct config_group *group, const char *name) +{ + struct cfs_overlay_item *overlay; + + overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); + if (!overlay) + return ERR_PTR(-ENOMEM); + overlay->ov_id = -1; + + config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); + return &overlay->item; +} + +static void cfs_overlay_group_drop_item(struct config_group *group, + struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + config_item_put(&overlay->item); +} + +static struct configfs_group_operations overlays_ops = { + .make_item = cfs_overlay_group_make_item, + .drop_item = cfs_overlay_group_drop_item, +}; + +static struct config_item_type overlays_type = { + .ct_group_ops = &overlays_ops, + .ct_owner = THIS_MODULE, +}; + +static struct configfs_group_operations of_cfs_ops = { + /* empty - we don't allow anything to be created */ +}; + +static struct config_item_type of_cfs_type = { + .ct_group_ops = &of_cfs_ops, + .ct_owner = THIS_MODULE, +}; + +struct config_group of_cfs_overlay_group; + +static struct configfs_subsystem of_cfs_subsys = { + .su_group = { + .cg_item = { + .ci_namebuf = "device-tree", + .ci_type = &of_cfs_type, + }, + }, + .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), +}; + +static int __init of_cfs_init(void) +{ + int ret; + + pr_info("%s\n", __func__); + + config_group_init(&of_cfs_subsys.su_group); + config_group_init_type_name(&of_cfs_overlay_group, "overlays", + &overlays_type); + configfs_add_default_group(&of_cfs_overlay_group, + &of_cfs_subsys.su_group); + + ret = configfs_register_subsystem(&of_cfs_subsys); + if (ret != 0) { + pr_err("%s: failed to register subsys\n", __func__); + goto out; + } + pr_info("%s: OK\n", __func__); +out: + return ret; +} +late_initcall(of_cfs_init); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/pci/controller/pcie-bcm63xx.c 2023-03-13 18:45:13.507496124 +0100 @@ -0,0 +1,1228 @@ +/* + * pcie-bcm63xx.c for pcie-bcm63x + * Created by on Wed Jun 5 14:08:58 2019 + */ + +/* + * inspired by pcie-bcm63xx.c from broadcom refsw release 5.02L.07-test9 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "pcie-bcm63xx.h" +#include "../pci.h" + +struct port_config { + u32 speed; + u32 num_lanes; + u32 ssc; + u64 dram_size; +}; + +#define MSI_MAP_SIZE 32 + +struct bcm63xx_pcie { + struct device *dev; + struct pci_host_bridge *host; + + unsigned long regs_phys; + void __iomem *regs; + + int irq; + struct resource io_res; + resource_size_t io_offset; + struct resource mem_res; + resource_size_t mem_offset; + struct resource bus_range; + + u32 core_speed; + struct port_config pcfg; + u32 misc_revision; + int rcal_1um_vert_value; + + int msi_irq; + struct mutex msi_lock; + struct irq_domain *msi_domain; + DECLARE_BITMAP(msi_used, MSI_MAP_SIZE); +}; + +#define to_bcm63xx_pcie(chip) container_of(chip, struct bcm63xx_pcie, chip) + +/* + * make it so that resource_size() return 0. + */ +static inline void make_invalid_resource(struct resource *r) +{ + r->start = 0; + r->end = -1; +} + +static inline void bcm_pcie_writel(u32 val, struct bcm63xx_pcie *pcie, + u32 offset) +{ + dev_dbg(pcie->dev, "bcm_pcie_writel: value %08x offset %08x\n", + val, offset); + writel(val, pcie->regs + offset); +} + +static inline u32 bcm_pcie_readl(struct bcm63xx_pcie *pcie, u32 offset) +{ + u32 val = readl(pcie->regs + offset); + + dev_dbg(pcie->dev, "bcm_pcie_readl: value %08x offset %08x\n", + val, offset); + return val; +} + +/* + * PCIe phy indirect read/write helpers. + */ +#define PCIE_PHY_TRIES 100 + +static int bcm_pcie_phy_read(struct bcm63xx_pcie *pcie, u32 phyaddr, u32 regaddr, + u32 *out_data) +{ + + u32 reg; + int tries = PCIE_PHY_TRIES; + + reg = PHY_ADDR_READ | + PHY_ADDR_PHY(phyaddr) | + PHY_ADDR_REG(regaddr); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PHY_ADDR); + udelay(1000); + + do { + u32 v = bcm_pcie_readl(pcie, BCM63XX_PCIE_PHY_RD_DATA); + + if (v & PHY_RD_DATA_DONE) { + *out_data = v & PHY_RD_DATA_MASK; + return 0; + } + udelay(10); + --tries; + } while (tries < PCIE_PHY_TRIES); + + dev_err(pcie->dev, "bcm_pcie_phy_read: timedout reading from " + "phy %x reg %x.\n", + phyaddr, regaddr); + return -ETIMEDOUT; +} + +static int bcm_pcie_phy_write(struct bcm63xx_pcie *pcie, u32 phyaddr, + u32 regaddr, u32 data) +{ + u32 reg; + int tries = PCIE_PHY_TRIES; + + reg = PHY_ADDR_WRITE | + PHY_ADDR_PHY(phyaddr) | + PHY_ADDR_REG(regaddr); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PHY_ADDR); + udelay(1000); + + reg = (data & PHY_WR_DATA_MASK) | PHY_WR_DATA_TRIG; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PHY_WR_DATA); + + do { + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_PHY_WR_DATA); + if (reg & PHY_WR_DATA_TRIG) + return 0; + --tries; + } while (tries < PCIE_PHY_TRIES); + + dev_err(pcie->dev, "bcm_pcie_phy_write: timedout writing from " + "phy %x reg %x.\n", + phyaddr, regaddr); + return -ETIMEDOUT; +} + +/* + * UBUS configuration + */ +static int bcm63xx_pcie_ubus_config(struct ubus4_master *m) +{ + ubus_master_apply_credits(m); + ubus_master_set_congestion_threshold(m, 0); + ubus_master_remap_port(m); + return 0; +} + +/* + * fetch various resources from device tree. + */ +static int bcm63xx_pcie_parse_ranges(struct bcm63xx_pcie *pcie) +{ + struct of_pci_range_parser parser; + struct of_pci_range range; + int error; + + error = of_pci_range_parser_init(&parser, pcie->dev->of_node); + if (error) { + dev_err(pcie->dev, "of_pci_range_parser_init failed: %d\n", + error); + return error; + } + + for_each_of_pci_range(&parser, &range){ + struct resource res; + + error = of_pci_range_to_resource(&range, pcie->dev->of_node, + &res); + if (error) + return error; + + switch (range.flags & IORESOURCE_TYPE_BITS) { + case IORESOURCE_MEM: + pcie->mem_res = res; + pcie->mem_offset = res.start - range.pci_addr; + break; + case IORESOURCE_IO: + pcie->io_offset = res.start - range.pci_addr; + pcie->io_res = res; + break; + } + } + + error = of_pci_parse_bus_range(pcie->dev->of_node, &pcie->bus_range); + if (error) { + dev_warn(pcie->dev, "unable to parse bus range. using " + "0-255.\n"); + pcie->bus_range.flags = IORESOURCE_BUS; + pcie->bus_range.start = 0x0; + pcie->bus_range.end = 0xff; + } + + dev_dbg(pcie->dev, "IO resource: %pR\n", &pcie->io_res); + dev_dbg(pcie->dev, "MEM resource: %pR\n", &pcie->mem_res); + dev_dbg(pcie->dev, "BUS resource: %pR\n", &pcie->bus_range); + + return 0; +} + +static int get_soc_dram_size(struct bcm63xx_pcie *pcie, u64 *out_dram_size) +{ + struct of_phandle_args args; + int err; + u64 reg[2]; + + err = of_parse_phandle_with_args(pcie->dev->of_node, "brcm,dram", + 0, 0, &args); + if (err) { + dev_err(pcie->dev, "unable to parse brcm,dram phandle.\n"); + return err; + } + + err = of_property_read_u64_array(args.np, "reg", reg, 2); + if (err) { + dev_err(pcie->dev, "unable to read reg from dram node: %d.\n", + err); + return err; + } + + *out_dram_size = reg[1]; + return 0; +} + +/* + * SoC specific DT configuration. speed can be overridden here, or + * left at 0 (use SoC default supported speed). + * + * SSC might be of interest for the hardware folks and CE + * certification. + * + * omitted from here: + * - phy low power mode select. + * - keep PCIe core powered on on link down during init. + * - error logging activation. + */ +static int bcm63xx_pcie_parse_dt_port_config(struct bcm63xx_pcie *pcie) +{ + int error; + + error = of_property_read_u32(pcie->dev->of_node, "brcm,speed", + &pcie->pcfg.speed); + if (error) + pcie->pcfg.speed = PCIE_SPEED_DEFAULT; + + error = of_property_read_u32(pcie->dev->of_node, "brcm,num-lanes", + &pcie->pcfg.num_lanes); + if (error) + pcie->pcfg.num_lanes = 1; + + error = of_property_read_u32(pcie->dev->of_node, "brcm,ssc", + &pcie->pcfg.ssc); + if (error) + pcie->pcfg.ssc = 0; + + error = get_soc_dram_size(pcie, &pcie->pcfg.dram_size); + if (error) + /* + * this is mandatory. + */ + return error; + + dev_dbg(pcie->dev, "speed: %d, num-lanes: %d, ssc: %d.\n", + pcie->pcfg.speed, pcie->pcfg.num_lanes, pcie->pcfg.ssc); + return 0; +} + +/* + * read vendor/device id, get chip revision from PCIe misc registers. + */ +static int bcm63xx_pcie_init(struct bcm63xx_pcie *pcie) +{ + u32 reg; + u32 link_width; + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_VENDOR_ID); + if (reg == 0xdeaddead) { + dev_err(pcie->dev, "dead read from PCIe register, is the " + "PCIe cable bad?\n"); + return -ENXIO; + } + + dev_dbg(pcie->dev, "vendor %04x, device %04x\n", + VENDOR_ID_VENDOR(reg), VENDOR_ID_DEVICE(reg)); + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_LINK_CAP); + link_width = LINK_CAP_WIDTH(reg); + pcie->core_speed = LINK_CAP_SPEED(reg); + + dev_dbg(pcie->dev, "link speed: 0x%x, width 0x%x\n", pcie->core_speed, + link_width); + + if (pcie->pcfg.num_lanes > link_width) { + dev_info(pcie->dev, "limiting num-lanes to %d\n", link_width); + pcie->pcfg.num_lanes = link_width; + } + + if (pcie->pcfg.speed > pcie->core_speed) { + dev_info(pcie->dev, "limiting speed to gen%d\n", + pcie->core_speed); + pcie->pcfg.speed = pcie->core_speed; + } + + pcie->misc_revision = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_REVISION); + dev_dbg(pcie->dev, "misc revision: 0x%04x\n", pcie->misc_revision); + + if (pcie->misc_revision < 0x320) { + /* + * chip revisions below 0x320 need access to the MISC + * register block to reset the PCIe core, which we do + * not need to support on the bcm63158. + * + * revisit later if needed. + */ + dev_err(pcie->dev, "chip revision 0x%04x unsupported. " + "can't reset PCIe chip.\n", pcie->misc_revision); + return -ENOTSUPP; + } + return 0; +} + +static int bcm63xx_pcie_phy_configure_gen2(struct bcm63xx_pcie *pcie) +{ + dev_info(pcie->dev, "configuring for GEN2 speed.\n"); + + /* + * nothing do do for bcm63158, work arounds for chip revision + * below 0x303 (everybody needs a 0x303) are fixed on chip + * revision 0x320 (available on bcm63158). + * + * we only need to configure SSC if required. + */ + if (!pcie->pcfg.ssc) + return 0; + + if (pcie->misc_revision < 0x303) { + /* + * SSC Parameters + * Workaround (for early gen2 cards): + * Block 0x1100, Register 0xA = 0xea3c + * Block 0x1100, Register 0xB = 0x04e7 + * Block 0x1100, Register 0xC = 0x0039 + *-Block 0x1100 fixed in 63148A0, 63381B0, 63138B0 + * but ok to write anyway + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x1100); + bcm_pcie_phy_write(pcie, 0, 0x0a, 0xea3c); + bcm_pcie_phy_write(pcie, 0, 0x0b, 0x04e7); + bcm_pcie_phy_write(pcie, 0, 0x0c, 0x0039); + } + + /* + * SSC Parameters + * Block 0x2200, Register 5 = 0x5044 + * // VCO parameters for fractional mode, -175ppm + * Block 0x2200, Register 6 = 0xfef1 + * // VCO parameters for fractional mode, -175ppm + * Block 0x2200, Register 7 = 0xe818 + * // VCO parameters for fractional mode, -175ppm + * + * Notes: + * - Only need to apply those fixes when enabling Spread + * Spectrum Clocking (SSC), which would likely be a flash + * option + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x2200); + bcm_pcie_phy_write(pcie, 0, 0x05, 0x5044); + bcm_pcie_phy_write(pcie, 0, 0x06, 0xfef1); + bcm_pcie_phy_write(pcie, 0, 0x07, 0xe818); + + return 0; +} + +static int bcm63xx_pcie_phy_configure_gen3(struct bcm63xx_pcie *pcie) +{ + dev_info(pcie->dev, "configuring for GEN3 speed.\n"); + + /* + * nothing do do for bcm63158, work arounds for chip revision + * below 0x320 are fixed on chip revision 0x322 (available on + * bcm63158). chip revision 0x320 seems to be found only on + * bcm63158 A0 (which we do not use). + * + * we only need to enable SSC if required. + */ + + if (!pcie->pcfg.ssc) + return 0; + + /* + * no GEN3 pcie cores on 63158, revisit later if needed. + */ + return -ENOTSUPP; +} + +/* + * resistor calibration configuration: this is fetched from the + * bcm(63158) procmon driver, and programmed to the PCIe hardware + * here. + */ +static int bcm63xx_pcie_gen12_rescal_set(struct bcm63xx_pcie *pcie) +{ + u32 data; + + if (pcie->rcal_1um_vert_value < 0) { + dev_warn(pcie->dev, "invalid rcal 1um vert value %d, " + "rescal unchanged.\n", pcie->rcal_1um_vert_value); + return 0; + } + + dev_info(pcie->dev, "bcm63xx_pcie_gen12_rescal_set: 0x%x\n", + pcie->rcal_1um_vert_value); + + /* + * Rcal Calibration Timers + * Block 0x1000, Register 1, bit 4(enable), and 3:0 (value) + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x1000); + bcm_pcie_phy_read(pcie, 0, 1, &data); + data = ((data & 0xffe0) | (pcie->rcal_1um_vert_value & 0xf) | + (1 << 4)); /* enable */ + bcm_pcie_phy_write(pcie, 0, 1, data); + + return 0; +} + +static int bcm63xx_pcie_rescal_set(struct bcm63xx_pcie *pcie) +{ + int error = 0; + + switch (pcie->core_speed) { + case PCIE_SPEED_GEN3: + return -ENOTSUPP; + default: + error = bcm63xx_pcie_gen12_rescal_set(pcie); + break; + } + + if (error) + return error; + return 0; +} + +static int bcm63xx_pcie_phy_config(struct bcm63xx_pcie *pcie) +{ + int error = 0; + + error = bcm63xx_pcie_rescal_set(pcie); + if (error) + return error; + + switch (pcie->core_speed) { + case PCIE_SPEED_GEN1: + /* nothing to do for gen1/default speed */ + break; + case PCIE_SPEED_GEN2: + error = bcm63xx_pcie_phy_configure_gen2(pcie); + break; + case PCIE_SPEED_GEN3: + error = bcm63xx_pcie_phy_configure_gen3(pcie); + break; + } + + if (error) { + dev_err(pcie->dev, "unable to configure PCIe phy for GEN%d\n", + pcie->core_speed); + return error; + } + + return 0; +} + +static int bcm63xx_pcie_phy_enable_ssc_gen2(struct bcm63xx_pcie *pcie, + bool enable) +{ + u32 data; + int timeout = 40; + + dev_info(pcie->dev, "%sabling SSC on GEN2 phy.\n", + enable ? "en" : "dis"); + + /* + * SSC disabled when PCIe core comes out of reset to allow PLL + * sync to happen write sscControl0 register + * ssc_mode_enable_ovrd & ssc_mode_enable_ovrd_val + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x1100); + bcm_pcie_phy_read(pcie, 0, 0x02, &data); + if (enable) + data |= 0xc000; /* bit 15:14 11'b to enable SSC */ + else + data &= ~0xc000; /* bit 15:14 00'b to disable SSC */ + bcm_pcie_phy_write(pcie, 0, 0x02, data); + + /* + * TODO: Check the status to see if SSC is set or not + */ + while (timeout) { + bcm_pcie_phy_read(pcie, 0, 0x01, &data); + + /* + * bit 10 reflects state of SSC ? Then what to make of + * the TODO comment above ? + */ + if (!!(data & (1 << 10)) == enable) + break; + --timeout; + udelay(1000); + } + + if (!timeout) + return -ETIMEDOUT; + + return 0; +} + +static int bcm63xx_pcie_phy_enable_ssc_gen3(struct bcm63xx_pcie *pcie, + bool enable) +{ + dev_info(pcie->dev, "%sabling SSC on GEN3 phy.\n", + enable ? "en" : "dis"); + + /* + * no GEN3 pcie cores on 63158, revisit later if needed. + */ + return -ENOTSUPP; +} + +static int bcm63xx_pcie_phy_enable_ssc(struct bcm63xx_pcie *pcie, bool enable) +{ + int error = 0; + + if (!pcie->pcfg.ssc) + return 0; + + switch (pcie->core_speed) { + case PCIE_SPEED_DEFAULT: + case PCIE_SPEED_GEN1: + break; + case PCIE_SPEED_GEN2: + error = bcm63xx_pcie_phy_enable_ssc_gen2(pcie, enable); + break; + case PCIE_SPEED_GEN3: + error = bcm63xx_pcie_phy_enable_ssc_gen3(pcie, enable); + break; + } + + if (error) { + dev_err(pcie->dev, "unable to %sable SSC: %d\n", + enable ? "en" : "dis", error); + return error; + } + return 0; +} + +static void __bcm63xx_pcie_set_reset(struct bcm63xx_pcie *pcie, bool assert) +{ + u32 reg; + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_CTRL); + if (assert) + reg &= ~MISC_CTRL_PCIE_RESETn; + else + reg |= MISC_CTRL_PCIE_RESETn; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_CTRL); +} + +static inline void bcm63xx_pcie_assert_reset(struct bcm63xx_pcie *pcie) +{ + __bcm63xx_pcie_set_reset(pcie, true); +} + +static inline void bcm63xx_pcie_deassert_reset(struct bcm63xx_pcie *pcie) +{ + __bcm63xx_pcie_set_reset(pcie, false); + +} + +static int bcm63xx_pcie_core_set_speed(struct bcm63xx_pcie *pcie) +{ + u32 reg; + + if (pcie->pcfg.speed == PCIE_SPEED_DEFAULT) + return 0; + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_PRIV1_LINK_CAP); + reg &= ~PRIV1_LINK_CAP_SPEED_MASK; + reg |= PRIV1_LINK_CAP_SPEED(pcie->pcfg.speed); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PRIV1_LINK_CAP); + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_LINK_STATUS_CONTROL2); + reg &= ~LINK_STATUS_CONTROL2_SPEED_MASK; + reg |= LINK_STATUS_CONTROL2_SPEED(pcie->pcfg.speed); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_LINK_STATUS_CONTROL2); + + mdelay(10); + + return 0; +} + +/* + * reset PCIe core, configure phy, and release core reset. + */ +static int bcm63xx_pcie_reset(struct bcm63xx_pcie *pcie) +{ + int error; + + bcm63xx_pcie_assert_reset(pcie); + + error = bcm63xx_pcie_phy_config(pcie); + if (error) + return error; + + /* + * disable SSC for now, enable it after link up. + */ + error = bcm63xx_pcie_phy_enable_ssc(pcie, false); + if (error) + return error; + + /* + * TODO: enable phy low power mode here ? + */ + + error = bcm63xx_pcie_core_set_speed(pcie); + if (error) + return error; + + bcm63xx_pcie_deassert_reset(pcie); + mdelay(500); + + return 0; +} + +static bool bcm63xx_pcie_check_link_up(struct bcm63xx_pcie *pcie) +{ + u32 v = bcm_pcie_readl(pcie, BCM63XX_PCIE_DL_STATUS); + + return !!(v & DL_STATUS_LINK_UP); +} + +static void bcm63xx_pcie_add_resources(struct bcm63xx_pcie *pcie) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + + if (resource_size(&pcie->io_res)) { + dev_err(pcie->dev, "adding resource %pR as IO@#!\n", + &pcie->io_res); + pci_add_resource(&bridge->windows, &pcie->io_res); + } + pci_add_resource(&bridge->windows, &pcie->mem_res); + pci_add_resource(&bridge->windows, &pcie->bus_range); +} + +static int bcm63xx_pcie_core_config(struct bcm63xx_pcie *pcie) +{ + u32 reg; + u32 size, size_val; + + /* + * clear legacy interrupt. + */ + bcm_pcie_writel(CPU_INTR1_PCIE_INTD_CPU_INTR | + CPU_INTR1_PCIE_INTC_CPU_INTR | + CPU_INTR1_PCIE_INTB_CPU_INTR | + CPU_INTR1_PCIE_INTA_CPU_INTR, pcie, + BCM63XX_PCIE_CPU_INTR1_MASK_CLEAR); + + /* + * configure MEM window + */ + reg = WIN_LIMIT_END(pcie->mem_res.end) | + WIN_LIMIT_BASE(pcie->mem_res.start); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_WIN_LIMIT(0)); + + reg = WIN_LO_BASE_ADDR(pcie->mem_res.start); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_WIN_LO(0)); + bcm_pcie_writel(0x0, pcie, BCM63XX_PCIE_MISC_WIN_HI(0)); + + /* + * incoming DDR memory configuration (BAR1) + * + * FIXME: are BAR2 and BAR3 configuration needed ? Or are + * BAR1/BAR2/BAR3 poor naming for DDR chip selects ? + */ + size = pcie->pcfg.dram_size >> 16; /* in 64k units */ + size_val = 0; + while (size) { + ++size_val; + size >>= 1; + } + bcm_pcie_writel(size_val, pcie, BCM63XX_PCIE_MISC_BAR_CONFIG_LO(0)); + + bcm_pcie_writel(UBUS_BAR_ACCESS_EN, pcie, + BCM63XX_PCIE_MISC_UBUS_BAR_REMAP(0)); + + /* + * setup PCI class code. + */ + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_PRIV1_ID_VAL3); + reg &= PRIV1_ID_VAL3_REV_ID_MASK; + reg |= PCI_CLASS_BRIDGE_PCI << 8; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PRIV1_ID_VAL3); + + /* + * disable data bus error for enumeration + */ + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_MISC_CTRL); + reg |= MISC_CTRL_CFG_READ_UR_MODE; + + /* + * misc performance settings + */ + reg |= (MISC_CTRL_MAX_BURST_SIZE_128B | MISC_CTRL_PCIE_IN_WR_COMBINE | + MISC_CTRL_PCIE_RCB_MPS_MODE | MISC_CTRL_PCIE_RCB_64B_MODE); + + reg &= ~misc_ctrl_burst_align_mask(pcie->misc_revision); + if (pcie->misc_revision >= 0x320) + reg |= misc_ctrl_burst_align(pcie->misc_revision, 4); + else if (pcie->misc_revision == 0x310) + reg |= misc_ctrl_burst_align(pcie->misc_revision, 3); + else + reg |= misc_ctrl_burst_align(pcie->misc_revision, 1); + if (pcie->misc_revision == 0x310) { + /* + * workaround for UBUS4 Logic Bug in this revision + * Limit the max burst to 64B + */ + reg &= ~MISC_CTRL_MAX_BURST_SIZE_MASK; + reg |= MISC_CTRL_MAX_BURST_SIZE_64B; + } + + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_MISC_CTRL); + + /* + * wait for UBUS reply for burst writes + */ + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_UBUS_CTRL); + reg |= MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_UBUS_CTRL); + + bcm63xx_pcie_phy_enable_ssc(pcie, true); + + return 0; +} + +void __iomem *bcm63xx_pcie_map_bus(struct pci_bus *the_bus, unsigned int devfn, + int where) +{ + struct pci_host_bridge *host = pci_find_host_bridge(the_bus); + struct bcm63xx_pcie *pcie = pci_host_bridge_priv(host); + unsigned int bus = the_bus->number; + unsigned int dev = PCI_SLOT(devfn), fun = PCI_FUNC(devfn); + + if (pci_is_root_bus(the_bus) && dev > 0) + /* + * device #0 access only on the root bus. + */ + return NULL; + + if (pci_is_root_bus(the_bus)) + /* + * root bus/bridge configuration space is mapped at + * the start of the PCIe register area. + */ + return pcie->regs + where; + + bcm_pcie_writel(EXT_CFG_INDEX_BUS_NUM(bus) | + EXT_CFG_INDEX_DEV_NUM(dev) | + EXT_CFG_INDEX_FUN_NUM(fun), pcie, + BCM63XX_PCIE_EXT_CFG_INDEX); + + return pcie->regs + BCM63XX_PCIE_EXT_CONF_SPACE + where; +} + +struct pci_ops bcm63xx_pcie_ops = { + .map_bus = bcm63xx_pcie_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + +/* + * top IRQ chip: do what is needed for parent chip (the bottom one), + * and also invoke PCI layer mask/unmask where applicable. + */ +static void bcm63xx_pcie_msi_top_irq_ack(struct irq_data *d) +{ + irq_chip_ack_parent(d); +} + +static void bcm63xx_pcie_msi_top_irq_mask(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void bcm63xx_pcie_msi_top_irq_unmask(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +struct irq_chip bcm63xx_pcie_msi_top_irq_chip = { + .name = "PCIe MSI ", + .irq_ack = bcm63xx_pcie_msi_top_irq_ack, + .irq_enable = bcm63xx_pcie_msi_top_irq_unmask, + .irq_disable = bcm63xx_pcie_msi_top_irq_mask, + .irq_unmask = bcm63xx_pcie_msi_top_irq_unmask, + .irq_mask = bcm63xx_pcie_msi_top_irq_mask, +}; + +/* + * bottom IRQ chip: program the PCIE controller registers as needed. + * + * NOTE: bcm63xx has a direct CLEAR/SET register, so this avoids the + * need of a spinlock, unlike pcie-rcar-host.c + */ +static void bcm63xx_pcie_msi_bottom_irq_ack(struct irq_data *d) +{ + struct bcm63xx_pcie *pcie = irq_data_get_irq_chip_data(d); + + bcm_pcie_writel(BIT(d->hwirq), pcie, BCM63XX_PCIE_MSI_CLEAR); +} + +static void bcm63xx_pcie_msi_bottom_irq_mask(struct irq_data *d) +{ + struct bcm63xx_pcie *pcie = irq_data_get_irq_chip_data(d); + + bcm_pcie_writel(BIT(d->hwirq), pcie, BCM63XX_PCIE_MSI_MASK_SET); +} + +static void bcm63xx_pcie_msi_bottom_irq_unmask(struct irq_data *d) +{ + struct bcm63xx_pcie *pcie = irq_data_get_irq_chip_data(d); + + bcm_pcie_writel(BIT(d->hwirq), pcie, BCM63XX_PCIE_MSI_MASK_CLEAR); +} + +static int bcm63xx_pcie_msi_set_affinity(struct irq_data *d, + const struct cpumask *mask, + bool force) +{ + return -EINVAL; +} + +static void bcm63xx_pcie_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + msg->address_lo = BCM63XX_PCIE_MSI_ADDR_MAGIC; + msg->address_hi = 0; + msg->data = (BCM63XX_PCIE_MSI_DATA_MAGIC | d->hwirq); +} + +struct irq_chip bcm63xx_pcie_msi_bottom_irq_chip = { + .name = "BCM63XX MSI", + .irq_ack = bcm63xx_pcie_msi_bottom_irq_ack, + .irq_mask = bcm63xx_pcie_msi_bottom_irq_mask, + .irq_unmask = bcm63xx_pcie_msi_bottom_irq_unmask, + .irq_set_affinity = bcm63xx_pcie_msi_set_affinity, + .irq_compose_msi_msg = bcm63xx_pcie_compose_msi_msg, +}; + +static int bcm63xx_pcie_msi_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct bcm63xx_pcie *pcie = domain->host_data; + int hwirq; + int i; + + mutex_lock(&pcie->msi_lock); + hwirq = bitmap_find_free_region(pcie->msi_used, MSI_MAP_SIZE, + order_base_2(nr_irqs)); + mutex_unlock(&pcie->msi_lock); + + if (hwirq < 0) { + dev_err(pcie->dev, "unable to satisfy MSI request of %d MSI " + "irqs.", nr_irqs); + return -ENOSPC; + } + + for (i = 0; i< nr_irqs; ++i) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &bcm63xx_pcie_msi_bottom_irq_chip, + domain->host_data, + handle_edge_irq, NULL, NULL); + } + + return 0; +} + +static void bcm63xx_pcie_msi_domain_free(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs) +{ + struct bcm63xx_pcie *pcie = domain->host_data; + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + + mutex_lock(&pcie->msi_lock); + bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); + mutex_unlock(&pcie->msi_lock); +} + + +struct irq_domain_ops bcm63xx_pcie_msi_domain_ops = { + .alloc = bcm63xx_pcie_msi_domain_alloc, + .free = bcm63xx_pcie_msi_domain_free, +}; + +static struct msi_domain_info bcm63xx_pcie_msi_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_MULTI_PCI_MSI), + .chip = &bcm63xx_pcie_msi_top_irq_chip, +}; + +static irqreturn_t bcm63xx_pcie_msi_irq(int irq, void *dev_id) +{ + struct bcm63xx_pcie *pcie = dev_id; + unsigned long stat; + + stat = bcm_pcie_readl(pcie, BCM63XX_PCIE_MSI_STATUS); + if (!stat) + return IRQ_NONE; + + while (stat) { + u32 index = find_first_bit(&stat, MSI_MAP_SIZE); + unsigned int irq; + + stat &= ~(1 << index); + irq = irq_find_mapping(pcie->msi_domain->parent, index); + if (irq) { + generic_handle_irq(irq); + } else + dev_err(pcie->dev, "unexpected MSI: %u\n", index); + } + + return IRQ_HANDLED; +} + +static int bcm63xx_pcie_msi_setup(struct bcm63xx_pcie *pcie) +{ + int err; + struct irq_domain *parent; + struct fwnode_handle *fwnode = dev_fwnode(pcie->dev); + mutex_init(&pcie->msi_lock); + + parent = irq_domain_create_linear(fwnode, + MSI_MAP_SIZE, + &bcm63xx_pcie_msi_domain_ops, + pcie); + if (!parent) { + dev_err(pcie->dev, "unable to create parent IRQ domain.\n"); + return -ENOMEM; + } + irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); + + pcie->msi_domain = pci_msi_create_irq_domain(fwnode, + &bcm63xx_pcie_msi_info, + parent); + if (!pcie->msi_domain) { + dev_err(pcie->dev, "unable to create MSI domain.\n"); + err = -ENOMEM; + goto err_remove_parent; + } + + err = devm_request_irq(pcie->dev, pcie->msi_irq, bcm63xx_pcie_msi_irq, + IRQF_SHARED, "msi_irq", pcie); + if (err) { + dev_err(pcie->dev, "unable to requiet PCIe MSI IRQ.\n"); + goto err_remove_msi_domain; + } + + /* + * Program the Root Complex Registers for matching address hi + * and low. + * + * The address should be unique with in the + * downstream/upstream BAR mapping + */ + bcm_pcie_writel(BCM63XX_PCIE_MSI_ADDR_MAGIC | + MSI_BAR_CONFIG_LO_ENABLE_MASK, + pcie, + BCM63XX_PCIE_MSI_BAR_CONFIG_LO); + + bcm_pcie_writel(0, + pcie, + BCM63XX_PCIE_MSI_BAR_CONFIG_HI); + + /* + * Program the RC registers for matching data pattern + */ + bcm_pcie_writel(BCM63XX_PCIE_MSI_DATA_MAGIC | + MSI_DATA_CONFIG_MATCH_MASK, + pcie, + BCM63XX_PCIE_MSI_DATA_CONFIG); + + /* + * Clear all MSI interrupts initially + */ + bcm_pcie_writel(0xffffffff, pcie, BCM63XX_PCIE_MSI_CLEAR); + + /* + * disable all available MSI vectors + */ + bcm_pcie_writel(0xffffffff, pcie, BCM63XX_PCIE_MSI_MASK_SET); + + + /* + * Enable MSI interrupt at L1 Intr1 controller + */ + bcm_pcie_writel(CPU_INTR1_PCIE_MSI_INTR_CPU_INTR, pcie, + BCM63XX_PCIE_CPU_INTR1_MASK_CLEAR); + + return 0; + +err_remove_msi_domain: + irq_domain_remove(pcie->msi_domain); +err_remove_parent: + irq_domain_remove(parent); + return err; +} + +static int bcm63xx_pcie_probe(struct platform_device *pdev) +{ + struct reset_control *reset; + struct ubus4_master *master; + int error; + struct bcm63xx_pcie *pcie; + struct pci_host_bridge *host; + struct resource *res; + struct pci_bus *child; + int rcal_1um_vert_value; + + dev_dbg(&pdev->dev, "probe.\n"); + + reset = devm_reset_control_get(&pdev->dev, "pcie0"); + if (IS_ERR(reset)) { + if (PTR_ERR(reset) != -EPROBE_DEFER) + dev_err(&pdev->dev, "missing pcie0 reset control\n"); + return PTR_ERR(reset); + } + + master = ubus4_master_of_get(pdev->dev.of_node); + if (IS_ERR(master)) { + dev_err(&pdev->dev, "unable to get UBUS master: %ld.\n", + PTR_ERR(master)); + return PTR_ERR(master); + } + + rcal_1um_vert_value = procmon_get_rcal(pdev->dev.of_node); + if (rcal_1um_vert_value == -EPROBE_DEFER) + /* + * should this be fatal for non EPROBE_DEFER cases? + */ + return rcal_1um_vert_value; + + host = devm_pci_alloc_host_bridge(&pdev->dev, sizeof (*pcie)); + if (!host) + return -ENOMEM; + + pcie = pci_host_bridge_priv(host); + pcie->rcal_1um_vert_value = rcal_1um_vert_value; + + make_invalid_resource(&pcie->mem_res); + make_invalid_resource(&pcie->io_res); + make_invalid_resource(&pcie->bus_range); + + pcie->msi_irq = platform_get_irq_byname(pdev, "intr"); + if (pcie->msi_irq < 0) + return pcie->msi_irq; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to get PCIe registers resource.\n"); + return -ENOENT; + } + dev_dbg(&pdev->dev, "PCIe registers: %pR\n", res); + + pcie->dev = &pdev->dev; + pcie->regs_phys = res->start; + + error = bcm63xx_pcie_parse_ranges(pcie); + if (error) + return error; + + host->busnr = pcie->bus_range.start; + host->dev.parent = &pdev->dev; + host->ops = &bcm63xx_pcie_ops; + host->map_irq = of_irq_parse_and_map_pci; + host->swizzle_irq = pci_common_swizzle; + + pcie->irq = irq_of_parse_and_map(pcie->dev->of_node, 0); + if (!pcie->irq) { + dev_err(pcie->dev, "unable to get IRQ.\n"); + /* can only assume it's not there :( */ + return -ENOENT; + } + + error = bcm63xx_pcie_parse_dt_port_config(pcie); + if (error) + return error; + + + /* power up block */ + error = reset_control_deassert(reset); + if (error) { + dev_err(&pdev->dev, "unable to deassert reset.\n"); + return error; + } + mdelay(10); + + error = bcm63xx_pcie_ubus_config(master); + if (error) { + dev_err(&pdev->dev, "unable to configure PCIe UBUS master.\n"); + return error; + } + + pcie->regs = devm_ioremap_resource(&pdev->dev, res); + if (!pcie->regs) { + dev_err(&pdev->dev, "unable to ioremap registers.\n"); + return -ENOMEM; + } + + error = bcm63xx_pcie_init(pcie); + if (error) + return error; + + error = bcm63xx_pcie_reset(pcie); + if (error) + return error; + + if (!bcm63xx_pcie_check_link_up(pcie)) { + dev_err(pcie->dev, "PCIe link: DOWN.\n"); + return -ENXIO; + } else { + u32 link_status = bcm_pcie_readl(pcie, + BCM63XX_PCIE_LINK_STATUS); + dev_info(pcie->dev, "PCIe link: UP, GEN%d, %d lane(s).\n", + LINK_STATUS_SPEED(link_status), + LINK_STATUS_WIDTH(link_status)); + } + + bcm63xx_pcie_add_resources(pcie); + + error = bcm63xx_pcie_core_config(pcie); + if (error) + return error; + + error = bcm63xx_pcie_msi_setup(pcie); + if (error) + return error; + + error = pci_scan_root_bus_bridge(host); + if (error) { + dev_err(&pdev->dev, "unable to scan root bus bridge: %d\n", + error); + return error; + } + + pci_bus_size_bridges(host->bus); + pci_bus_assign_resources(host->bus); + list_for_each_entry(child, &host->bus->children, node) + pcie_bus_configure_settings(child); + + pci_bus_add_devices(host->bus); + +#if 0 + /* + * now create the PCI bus proper. + */ + pcie->bus = pci_create_root_bus(&pdev->dev, pcie->bus_range.start, + &bcm63xx_pcie_ops, pcie, + &pcie->resources); + if (!pcie->bus) { + dev_err(pcie->dev, "unable to create root bus.\n"); + return -ENXIO; + } + + pci_scan_child_bus(pcie->bus); + pci_assign_unassigned_bus_resources(pcie->bus); + pci_bus_add_devices(pcie->bus); + + /* Configure PCI Express settings */ + list_for_each_entry(child, &pcie->bus->children, node) + pcie_bus_configure_settings(child); +#endif + + return 0; +} + +static const struct of_device_id bcm63xx_pcie_match[] = { + { .compatible = "brcm,bcm63xx-pcie" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63xx_pcie_of_match); + +struct platform_driver bcm63xx_pcie_driver = { + .probe = bcm63xx_pcie_probe, + .remove = NULL, /* FIXME*/ + .driver = { + .name = "bcm63xx-pcie", + .owner = THIS_MODULE, + .of_match_table = bcm63xx_pcie_match, + }, +}; + +module_platform_driver(bcm63xx_pcie_driver); + + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63XX SoCs PCIe root complex driver."); +MODULE_LICENSE("GPL v2"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/pci/controller/pcie-bcm63xx.h 2023-03-13 18:45:13.507496124 +0100 @@ -0,0 +1,130 @@ +/* + * pcie-bcm63xx.h for pcie-bcm63xx + * Created by on Mon Jun 10 16:54:54 2019 + */ + +#pragma once + +#define _F(_v, _s, _m) (((_v) & (_m)) << (_s)) + +/* + * TYPE 1 RC configuration registers + */ +#define BCM63XX_PCIE_VENDOR_ID 0x0000 +#define VENDOR_ID_VENDOR(x) ((x) & 0xffff) +#define VENDOR_ID_DEVICE(x) (((x) >> 16) & 0xffff) + +#define BCM63XX_PCIE_LINK_CAP 0x00b8 +#define LINK_CAP_SPEED(x) ((x) & 0xf) +#define LINK_CAP_WIDTH(x) (((x) >> 4) & 0x3f) + +#define BCM63XX_PCIE_LINK_STATUS 0x00bc +#define LINK_STATUS_WIDTH(x) (((x) >> 20) & 0x3f) +#define LINK_STATUS_SPEED(x) (((x) >> 16) & 0xf) + +#define BCM63XX_PCIE_LINK_STATUS_CONTROL2 0x00dc +#define LINK_STATUS_CONTROL2_SPEED_MASK _F(0x3, 0, 0x3) +#define LINK_STATUS_CONTROL2_SPEED(x) _F(x, 0, 0x3) + +#define BCM63XX_PCIE_PRIV1_LINK_CAP (0x0428 + 0xb4) +#define PRIV1_LINK_CAP_SPEED_MASK _F(0x3, 0, 0x3) +#define PRIV1_LINK_CAP_SPEED(x) _F(x, 0, 0x3) + +#define BCM63XX_PCIE_PRIV1_ID_VAL3 (0x428 + 0x14) +#define PRIV1_ID_VAL3_REV_ID_MASK (0xff << 24) + +#define BCM63XX_PCIE_PHY_ADDR 0x1100 +#define PHY_ADDR_READ (1 << 20) +#define PHY_ADDR_WRITE (0 << 20) +#define PHY_ADDR_PHY(x) _F(x, 16, 0xf) +#define PHY_ADDR_REG(x) _F(x, 0x0, 0x1f) + +#define BCM63XX_PCIE_DL_STATUS 0x1048 +#define DL_STATUS_LINK_UP (0x2000) + +#define BCM63XX_PCIE_PHY_WR_DATA 0x1104 +#define PHY_WR_DATA_TRIG (1 << 31) +#define PHY_WR_DATA_MASK 0xffff +#define BCM63XX_PCIE_PHY_RD_DATA 0x1108 +#define PHY_RD_DATA_DONE (1 << 31) +#define PHY_RD_DATA_MASK 0xffff + +#define BCM63XX_PCIE_MISC_MISC_CTRL (0x4008) +#define MISC_CTRL_MAX_BURST_SIZE_64B (0 << 20) +#define MISC_CTRL_MAX_BURST_SIZE_128B (1 << 20) +#define MISC_CTRL_MAX_BURST_SIZE_MASK (3 << 20) +static inline u32 misc_ctrl_burst_align_mask(u32 rev) +{ + return rev >= 0x310 ? (7 << 17) : (1 << 19); +} +static inline u32 misc_ctrl_burst_align(u32 rev, u32 b) +{ + return rev >= 0x310 ? (b << 17) : (b << 19); +} +#define MISC_CTRL_CFG_READ_UR_MODE (1 << 13) +#define MISC_CTRL_PCIE_IN_WR_COMBINE (1 << 11) +#define MISC_CTRL_PCIE_RCB_MPS_MODE (1 << 10) +#define MISC_CTRL_PCIE_RCB_64B_MODE (1 << 7) + +#define BCM63XX_PCIE_MISC_WIN_LO(win) (0x400c + (win) * 8) +#define WIN_LO_BASE_ADDR(x) ((x) & 0xfff00000) +#define BCM63XX_PCIE_MISC_WIN_HI(win) (0x4010 + (win) * 8) + +#define BCM63XX_PCIE_MISC_BAR_CONFIG_LO(bar) (0x402c + (bar) * 8) + +#define BCM63XX_PCIE_MISC_UBUS_CTRL (0x40a4) +#define MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY (1 << 14) + + +#define BCM63XX_PCIE_MISC_UBUS_BAR_REMAP(bar) (0x40ac + (bar) * 8) +#define UBUS_BAR_ACCESS_EN (1 << 0) + +#define BCM63XX_PCIE_MISC_CTRL 0x4064 +#define MISC_CTRL_PCIE_RESETn (1 << 2) + +#define BCM63XX_PCIE_MISC_REVISION 0x406c + +#define BCM63XX_PCIE_MISC_WIN +#define BCM63XX_PCIE_MISC_WIN_LIMIT(win) (0x4070 + (win) * 4) +#define WIN_LIMIT_END(x) ((x) & 0xfff00000) +#define WIN_LIMIT_BASE(x) (((x) >> 16) & 0xffff0) + +#define BCM63XX_PCIE_EXT_CONF_SPACE 0x8000 + +#define BCM63XX_PCIE_EXT_CFG_INDEX 0x9000 +#define EXT_CFG_INDEX_BUS_NUM(x) _F(x, 20, 0xff) +#define EXT_CFG_INDEX_DEV_NUM(x) _F(x, 15, 0x1f) +#define EXT_CFG_INDEX_FUN_NUM(x) _F(x, 12, 0x7) + +#define BCM63XX_PCIE_CPU_INTR1_MASK_CLEAR 0x940c +#define CPU_INTR1_PCIE_INTA_CPU_INTR (1 << 1) +#define CPU_INTR1_PCIE_INTB_CPU_INTR (1 << 2) +#define CPU_INTR1_PCIE_INTC_CPU_INTR (1 << 3) +#define CPU_INTR1_PCIE_INTD_CPU_INTR (1 << 4) +#define CPU_INTR1_PCIE_INTR_CPU_INTR (1 << 5) +#define CPU_INTR1_PCIE_NMI_CPU_INTR (1 << 6) +#define CPU_INTR1_PCIE_UBUS_CPU_INTR (1 << 7) +#define CPU_INTR1_PCIE_MSI_INTR_CPU_INTR (1 << 9) + +#define BCM63XX_PCIE_MSI_DATA_MAGIC 0x0000BCA0 +#define BCM63XX_PCIE_MSI_ADDR_MAGIC 0xFFFFFFFC + +#define BCM63XX_PCIE_MSI_BASE 0x4500 + +#define BCM63XX_PCIE_MSI_STATUS (0x4500) +#define BCM63XX_PCIE_MSI_CLEAR (0x4508) +#define BCM63XX_PCIE_MSI_MASK_SET (0x4510) +#define BCM63XX_PCIE_MSI_MASK_CLEAR (0x4514) + +/* #define BCM63XX_PCIE_MSI_MSI_INTR_MASK 0xFFFFFFFF */ +/* #define BCM63XX_PCIE_MSI_MSI_INTR_SHIFT 0 */ + + +#define BCM63XX_PCIE_MSI_BAR_CONFIG_LO (0x4044) +#define MSI_BAR_CONFIG_LO_MATCH_ADDR_MASK 0xfffffffc +#define MSI_BAR_CONFIG_LO_ENABLE_MASK (1 << 0) + +#define BCM63XX_PCIE_MSI_BAR_CONFIG_HI (0x4048) + +#define BCM63XX_PCIE_MSI_DATA_CONFIG (0x404C) +#define MSI_DATA_CONFIG_MATCH_MASK 0xffe00000 --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/phy/xdsl_phy_api.c 2023-02-24 19:07:30.754305868 +0100 @@ -0,0 +1,205 @@ +#include +#include +#include +#include + +static DEFINE_MUTEX(phy_device_list_mutex); +static LIST_HEAD(phy_device_list); + +/* + * + */ +static struct xdsl_phy *__phy_lookup(struct device_node *node, + unsigned int id) +{ + struct xdsl_phy *pd; + + list_for_each_entry(pd, &phy_device_list, next) { + if (node) { + if (pd->of_node == node) + return pd; + } else { + if (pd->id == id) + return pd; + } + } + return NULL; +} + +/* + * + */ +struct xdsl_phy *xdsl_phy_attach(struct device_node *node, + unsigned int id, + void (*change_cb)(struct xdsl_phy *, + void *), + void *change_priv) +{ + struct xdsl_phy *phy_dev; + + if (!node && !id) + return ERR_PTR(-EINVAL); + + mutex_lock(&phy_device_list_mutex); + + phy_dev = __phy_lookup(node, id); + + if (!phy_dev) { + mutex_unlock(&phy_device_list_mutex); + return ERR_PTR(-EPROBE_DEFER); + } + + if (phy_dev->in_use) { + mutex_unlock(&phy_device_list_mutex); + return ERR_PTR(-EBUSY); + } + + try_module_get(phy_dev->owner); + + phy_dev->in_use = true; + phy_dev->started = false; + phy_dev->change_cb = change_cb; + phy_dev->change_priv = change_priv; + + mutex_unlock(&phy_device_list_mutex); + + return phy_dev; +} + +EXPORT_SYMBOL(xdsl_phy_attach); + +/* + * + */ +static void initial_change_work_func(struct work_struct *work) +{ + struct xdsl_phy *phy_dev = container_of(work, + struct xdsl_phy, + initial_change_work); + + mutex_lock(&phy_dev->lock); + if (!phy_dev->in_use || !phy_dev->change_cb || !phy_dev->started) { + mutex_unlock(&phy_dev->lock); + return; + } + + phy_dev->initial_change_pending = false; + phy_dev->change_cb(phy_dev, phy_dev->change_priv); + mutex_unlock(&phy_dev->lock); +} + +/* + * + */ +void xdsl_phy_start(struct xdsl_phy *phy_dev) +{ + mutex_lock(&phy_dev->lock); + phy_dev->started = true; + phy_dev->initial_change_pending = true; + schedule_work(&phy_dev->initial_change_work); + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_start); + +/* + * + */ +void xdsl_phy_stop(struct xdsl_phy *phy_dev) +{ + mutex_lock(&phy_dev->lock); + phy_dev->started = false; + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_stop); + +/* + * + */ +void xdsl_phy_detach(struct xdsl_phy *phy_dev) +{ + WARN_ON(!phy_dev->in_use); + + mutex_lock(&phy_dev->lock); + phy_dev->in_use = false; + phy_dev->started = false; + cancel_work_sync(&phy_dev->initial_change_work); + phy_dev->initial_change_pending = false; + phy_dev->change_cb = NULL; + phy_dev->change_priv = NULL; + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_detach); + +/* + * + */ +void xdsl_phy_device_notify_change(struct xdsl_phy *phy_dev) +{ + mutex_lock(&phy_dev->lock); + if (!phy_dev->in_use || !phy_dev->change_cb || !phy_dev->started) { + mutex_unlock(&phy_dev->lock); + return; + } + + cancel_work_sync(&phy_dev->initial_change_work); + phy_dev->initial_change_pending = false; + phy_dev->change_cb(phy_dev, phy_dev->change_priv); + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_device_notify_change); + +/* + * + */ +int xdsl_phy_device_register(struct xdsl_phy *phy_dev) +{ + if (!phy_dev->ops || + !phy_dev->ops->get_status || + !phy_dev->owner) + return -EINVAL; + + mutex_lock(&phy_device_list_mutex); + + if (__phy_lookup(phy_dev->of_node, phy_dev->id)) { + mutex_unlock(&phy_device_list_mutex); + return -EEXIST; + } + + mutex_init(&phy_dev->lock); + mutex_init(&phy_dev->ops_lock); + phy_dev->in_use = false; + phy_dev->started = false; + INIT_WORK(&phy_dev->initial_change_work, initial_change_work_func); + phy_dev->initial_change_pending = false; + phy_dev->change_cb = NULL; + phy_dev->change_priv = NULL; + + list_add(&phy_dev->next, &phy_device_list); + mutex_unlock(&phy_device_list_mutex); + + return 0; +} + +EXPORT_SYMBOL(xdsl_phy_device_register); + +/* + * + */ +void xdsl_phy_device_unregister(struct xdsl_phy *phy_dev) +{ + if (WARN_ON(phy_dev->in_use)) + return; + + cancel_work_sync(&phy_dev->initial_change_work); + mutex_lock(&phy_device_list_mutex); + list_del(&phy_dev->next); + mutex_unlock(&phy_device_list_mutex); +} + +EXPORT_SYMBOL(xdsl_phy_device_unregister); + +MODULE_LICENSE("GPL"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/pinctrl/bcm/pinctrl-bcm63138.c 2023-09-01 15:04:29.529632893 +0200 @@ -0,0 +1,1004 @@ +/* + * Driver for Broadcom BCM63138 pinctrl + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../pinctrl-utils.h" + +#define GPIO_DIR_REG(cfg, gpio) ((gpio / 32) * 4 + cfg->gpio_dir_offset) +#define GPIO_VAL_REG(cfg, gpio) ((gpio / 32) * 4 + cfg->gpio_val_offset) +#define BCM_MAX_GPIOS 160 + + +/* + * registers relative to cfg->testport_offset. + */ +#define GPIO_TPORT_DATA_MSB_REG(cfg) (cfg->testport_offset + 0x00) +#define GPIO_TPORT_DATA_LSB_REG(cfg) (cfg->testport_offset + 0x04) +#define TPORT_DATA_PIN_SHIFT 0 +#define TPORT_DATA_FUNC_SHIFT 12 +#define TPORT_DATA_FUNC_GPIO 5 + +#define GPIO_TPORT_CMD_REG(cfg) (cfg->testport_offset + 0x08) +#define TPORT_CMD_LOAD 0x21 + +/* + * register definition for extirq + */ +#define EXT_IRQ_MAX_COUNT 8 + +#define EXTIRQ_CFG_LVL_STICKY_MASK(x) (1 << (0 + (x))) +#define EXTIRQ_CFG_SENSE_HI_MASK(x) (1 << (8 + (x))) +#define EXTIRQ_CFG_EDGE_BOTH_MASK(x) (1 << (16 + (x))) +#define EXTIRQ_CFG_LEVEL_MASK(x) (1 << (24 + (x))) + +struct bcm63138_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +struct bcm63xx_pinctrl_soc_config; + +struct bcm63138_pinctrl { + struct device *dev; + void __iomem *base; + + struct pinctrl_desc desc; + struct pinctrl_dev *pctl_dev; + + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range *range; + + struct bcm63138_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + spinlock_t lock; + + void __iomem *irq_base; + int ext_irq_map[EXT_IRQ_MAX_COUNT]; + u8 ext_irq_revmap[BCM_MAX_GPIOS]; + struct irq_fwspec ext_irq_parents[EXT_IRQ_MAX_COUNT]; + + const struct bcm63xx_pinctrl_soc_config *cfg; +}; + +static const char * const bcm63138_pin_functions[] = { + "mux0", + "mux1", + "mux2", + "mux3", + "mux4", + "mux5", + "mux6", +}; + +struct bcm63xx_desc_function { + const char *name; + const unsigned char num; +}; + +struct bcm63xx_desc_pin { + struct pinctrl_pin_desc pin; + const struct bcm63xx_desc_function *functions; +}; + +struct bcm63xx_pinctrl_soc_config { + const struct bcm63xx_desc_pin *pin_descs; + size_t nr_pin_descs; + + /* from base gpio */ + u32 gpio_dir_offset; + u32 gpio_val_offset; + u32 testport_offset; + + /* from base irq */ + unsigned int ext_irq_count; + u32 ext_irq_ctrl_offset; + u32 ext_irq_status_offset; + u32 ext_irq_clear_offset; + u32 ext_irq_mask_offset; + u32 ext_irq_mask_set_offset; + u32 ext_irq_mask_clear_offset; + u32 ext_irq_mux_sel0_offset; + u32 ext_irq_mux_sel1_offset; +}; + +#define BCM63XX_PIN(_pin, ...) \ + { \ + .pin = _pin, \ + .functions = (struct bcm63xx_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define BCM63XX_FUNCTION(_num, _name) \ + { \ + .num = _num, \ + .name = _name, \ + } + +#include "pindesc-bcm63138.h" +#include "pindesc-bcm63158.h" + +struct bcm63xx_pinctrl_soc_config bcm63138_soc_config = { + .pin_descs = bcm63138_desc_pins, + .nr_pin_descs = ARRAY_SIZE(bcm63138_desc_pins), + + .gpio_dir_offset = 0x00, + .gpio_val_offset = 0x14, + .testport_offset = 0x3c, +}; + +struct bcm63xx_pinctrl_soc_config bcm63158_soc_config = { + .pin_descs = bcm63158_desc_pins, + .nr_pin_descs = ARRAY_SIZE(bcm63158_desc_pins), + + .gpio_dir_offset = 0x00, + .gpio_val_offset = 0x20, + .testport_offset = 0x54, + + .ext_irq_count = 8, + .ext_irq_ctrl_offset = 0x00, + .ext_irq_status_offset = 0x04, + .ext_irq_clear_offset = 0x0c, + .ext_irq_mask_offset = 0x10, + .ext_irq_mask_set_offset = 0x14, + .ext_irq_mask_clear_offset = 0x18, + .ext_irq_mux_sel0_offset = 0x24, + .ext_irq_mux_sel1_offset = 0x28, +}; + +/* Pinctrl functions */ +static struct bcm63138_pinctrl_group * +bcm63138_pctrl_find_group_by_pin(struct bcm63138_pinctrl *pctl, u32 pin) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct bcm63138_pinctrl_group *grp = pctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static bool bcm63138_pctrl_is_function_valid(struct bcm63138_pinctrl *pctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < pctl->cfg->nr_pin_descs; i++) { + const struct bcm63xx_desc_pin *pin = &pctl->cfg->pin_descs[i]; + const struct bcm63xx_desc_function *func = pin->functions; + + if (pin->pin.number != pin_num) + continue; + + while (func && func->name) { + if (func->num == fnum) + return true; + func++; + } + + break; + } + + return false; +} + +static int +bcm63138_pctrl_dt_node_to_map_func(struct bcm63138_pinctrl *pctl, + u32 pin, u32 fnum, + struct bcm63138_pinctrl_group *grp, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = grp->name; + + if (!bcm63138_pctrl_is_function_valid(pctl, pin, fnum)) { + dev_err(pctl->dev, "invalid function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + (*map)[*num_maps].data.mux.function = bcm63138_pin_functions[fnum]; + (*num_maps)++; + + return 0; +} + +static int bcm63138_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + return pctl->ngroups; +} + +static const char *bcm63138_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + return pctl->groups[group].name; +} + +static int bcm63138_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + return 0; +} + +static int bcm63138_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + struct bcm63138_pinctrl *pctl; + struct bcm63138_pinctrl_group *grp; + struct property *pins; + u32 pinfunc, pin, func; + unsigned reserve = 0; + int num_pins, num_funcs, maps_per_pin, i, err; + + pctl = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { + dev_err(pctl->dev, "missing pins property in node %s .\n", + node->name); + return -EINVAL; + } + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + maps_per_pin = 0; + + if (num_funcs) + maps_per_pin++; + + if (num_pins >= 1) + maps_per_pin++; + + if (!num_pins || !maps_per_pin) + return -EINVAL; + + reserve = num_pins * maps_per_pin; + + err = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, num_maps, reserve); + if (err) + return err; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "pinmux", + i, &pinfunc); + if (err) + return err; + + pin = BCM63138_GET_PIN_NO(pinfunc); + func = BCM63138_GET_PIN_FUNC(pinfunc); + + if (!bcm63138_pctrl_is_function_valid(pctl, pin, func)) { + dev_err(pctl->dev, "invalid function.\n"); + return -EINVAL; + } + + grp = bcm63138_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", + pin); + return -EINVAL; + } + + err = bcm63138_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, + reserved_maps, num_maps); + if (err) + return err; + } + + return 0; +} + +static int bcm63138_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = bcm63138_pctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static const struct pinctrl_ops bcm63138_pctrl_ops = { + .dt_node_to_map = bcm63138_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, + .get_groups_count = bcm63138_pctrl_get_groups_count, + .get_group_name = bcm63138_pctrl_get_group_name, + .get_group_pins = bcm63138_pctrl_get_group_pins, +}; + +/* Pinmux functions */ + +static int bcm63138_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm63138_pin_functions); +} + +static const char *bcm63138_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm63138_pin_functions[selector]; +} + +static int bcm63138_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + *groups = pctl->grp_names; + *num_groups = pctl->ngroups; + return 0; +} + +static void set_mux(struct bcm63138_pinctrl *pctl, + unsigned int pin, + unsigned int function) +{ + dev_dbg(pctl->dev, "setting mux for pin%d function%d\n", + pin, function); + + iowrite32(0, + pctl->base + GPIO_TPORT_DATA_MSB_REG(pctl->cfg)); + + iowrite32(pin << TPORT_DATA_PIN_SHIFT | + function << TPORT_DATA_FUNC_SHIFT, + pctl->base + GPIO_TPORT_DATA_LSB_REG(pctl->cfg)); + + iowrite32(TPORT_CMD_LOAD, + pctl->base + GPIO_TPORT_CMD_REG(pctl->cfg)); +} + +static int bcm63138_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct bcm63138_pinctrl_group *g = pctl->groups + group; + + if (!bcm63138_pctrl_is_function_valid(pctl, g->pin, function)) { + dev_err(pctl->dev, "invalid function %d on group %d .\n", + function, group); + return -EINVAL; + } + + set_mux(pctl, g->pin, function); + return 0; +} + +static int bcm63138_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + set_mux(pctl, offset, TPORT_DATA_FUNC_GPIO); + return 0; +} + +static const struct pinmux_ops bcm63138_pmx_ops = { + .get_functions_count = bcm63138_pmx_get_funcs_cnt, + .get_function_name = bcm63138_pmx_get_func_name, + .get_function_groups = bcm63138_pmx_get_func_groups, + .set_mux = bcm63138_pmx_set_mux, + .gpio_request_enable = bcm63138_pmx_gpio_request_enable, + .strict = true, +}; + +/* + * GPIO functions + */ +static int bcm63138_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + + val = ioread32(pctl->base + GPIO_VAL_REG(pctl->cfg, offset)); + return !!(val & (1 << (offset % 32))); +} + +static void __bcm63138_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + + val = ioread32(pctl->base + GPIO_VAL_REG(pctl->cfg, offset)); + if (value) + val |= (1 << (offset % 32)); + else + val &= ~(1 << (offset % 32)); + iowrite32(val, pctl->base + GPIO_VAL_REG(pctl->cfg, offset)); +} + +static void bcm63138_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + unsigned long flags; + + spin_lock_irqsave(&pctl->lock, flags); + + __bcm63138_gpio_set(chip, offset, value); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static int bcm63138_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pctl->lock, flags); + + val = ioread32(pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + val &= ~(1 << (offset % 32)); + iowrite32(val, pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + + spin_unlock_irqrestore(&pctl->lock, flags); + return 0; +} + +static int bcm63138_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pctl->lock, flags); + + __bcm63138_gpio_set(chip, offset, value); + + val = ioread32(pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + val |= (1 << (offset % 32)); + iowrite32(val, pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + + spin_unlock_irqrestore(&pctl->lock, flags); + return 0; +} + +static int bcm63138_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + + val = ioread32(pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + return (val & (1 << (offset % 32))) ? 0 : 1; +} + +/* + * + */ +static int bcm63138_pctrl_build_state(struct platform_device *pdev) +{ + struct bcm63138_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->cfg->nr_pin_descs; + + /* Allocate groups */ + pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->groups), GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + /* We assume that one pin is one group, use pin name as group name. */ + pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->grp_names), GFP_KERNEL); + if (!pctl->grp_names) + return -ENOMEM; + + for (i = 0; i < pctl->cfg->nr_pin_descs; i++) { + const struct bcm63xx_desc_pin *pin = &pctl->cfg->pin_descs[i]; + struct bcm63138_pinctrl_group *group = &pctl->groups[i]; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + pctl->grp_names[i] = pin->pin.name; + } + + return 0; +} + +/* + * + */ +static void bcm63138_gpio_irq_ack(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct bcm63138_pinctrl *pctl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned int ext_irq = pctl->ext_irq_revmap[hwirq]; + + writel(1 << ext_irq, + pctl->irq_base + pctl->cfg->ext_irq_clear_offset); + if (d->parent_data->chip) + irq_chip_eoi_parent(d); +} + +/* + * + */ +static void bcm63138_gpio_irq_mask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct bcm63138_pinctrl *pctl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned int ext_irq = pctl->ext_irq_revmap[hwirq]; + + irq_chip_mask_parent(d); + writel(1 << ext_irq, + pctl->irq_base + pctl->cfg->ext_irq_mask_clear_offset); + gpiochip_disable_irq(gc, irqd_to_hwirq(d)); +} + +/* + * + */ +static void bcm63138_gpio_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct bcm63138_pinctrl *pctl = gpiochip_get_data(gc); + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned int ext_irq = pctl->ext_irq_revmap[hwirq]; + + gpiochip_enable_irq(gc, irqd_to_hwirq(d)); + writel(1 << ext_irq, + pctl->irq_base + pctl->cfg->ext_irq_mask_set_offset); + if (d->parent_data->chip) + irq_chip_unmask_parent(d); +} + +/* + * + */ +static int bcm63138_gpio_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct bcm63138_pinctrl *pctl = gpiochip_get_data(gc); + unsigned long flags; + irq_hw_number_t hwirq = irqd_to_hwirq(d); + unsigned int ext_irq = pctl->ext_irq_revmap[hwirq]; + unsigned int irq_bit = (1 << ext_irq); + bool is_level, rising_or_high, dual_edge; + u32 val; + + if (WARN_ON(ext_irq >= pctl->cfg->ext_irq_count)) + return -EINVAL; + + is_level = false; + rising_or_high = false; + dual_edge = false; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_RISING: + rising_or_high = true; + break; + case IRQ_TYPE_EDGE_FALLING: + break; + case IRQ_TYPE_EDGE_BOTH: + dual_edge = true; + break; + case IRQ_TYPE_LEVEL_HIGH: + is_level = true; + rising_or_high = true; + break; + case IRQ_TYPE_LEVEL_LOW: + is_level = true; + break; + default: + dev_err(pctl->dev, "invalid GPIO IRQ type 0x%x\n", type); + return -EINVAL; + } + + spin_lock_irqsave(&pctl->lock, flags); + + /* mask it */ + writel(irq_bit, + pctl->irq_base + pctl->cfg->ext_irq_mask_set_offset); + + /* setup */ + val = readl(pctl->irq_base + pctl->cfg->ext_irq_ctrl_offset); + val &= ~EXTIRQ_CFG_LVL_STICKY_MASK(ext_irq); + val &= ~EXTIRQ_CFG_SENSE_HI_MASK(ext_irq); + val &= ~EXTIRQ_CFG_EDGE_BOTH_MASK(ext_irq); + + if (is_level) + val |= EXTIRQ_CFG_LEVEL_MASK(ext_irq); + else + val &= ~EXTIRQ_CFG_LEVEL_MASK(ext_irq); + + if (rising_or_high) + val |= EXTIRQ_CFG_SENSE_HI_MASK(ext_irq); + else + val &= ~EXTIRQ_CFG_SENSE_HI_MASK(ext_irq); + + if (dual_edge) + val |= EXTIRQ_CFG_EDGE_BOTH_MASK(ext_irq); + else + val &= ~EXTIRQ_CFG_EDGE_BOTH_MASK(ext_irq); + + writel(val, pctl->irq_base + pctl->cfg->ext_irq_ctrl_offset); + + /* setup mux to correct gpio */ + val = readl(pctl->irq_base + pctl->cfg->ext_irq_mux_sel0_offset); + val &= ~(0xf << (ext_irq * 4)); + val |= (hwirq & 0xf) << (ext_irq * 4); + writel(val, pctl->irq_base + pctl->cfg->ext_irq_mux_sel0_offset); + + val = readl(pctl->irq_base + pctl->cfg->ext_irq_mux_sel1_offset); + val &= ~(0xf << (ext_irq * 4)); + val |= (hwirq >> 4) << (ext_irq * 4); + writel(val, pctl->irq_base + pctl->cfg->ext_irq_mux_sel1_offset); + + if (is_level) + irq_set_handler_locked(d, handle_level_irq); + else + irq_set_handler_locked(d, handle_edge_irq); + + /* clear pending if any */ + writel(irq_bit, + pctl->irq_base + pctl->cfg->ext_irq_clear_offset); + + /* unmask */ + writel(irq_bit, + pctl->irq_base + pctl->cfg->ext_irq_mask_clear_offset); + + spin_unlock_irqrestore(&pctl->lock, flags); + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + +static void +bcm63138_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(data); + seq_printf(p, dev_name(gc->parent)); +} + +static const struct irq_chip bcm63138_gpio_irq_chip = { + .irq_ack = bcm63138_gpio_irq_ack, + .irq_mask = bcm63138_gpio_irq_mask, + .irq_unmask = bcm63138_gpio_irq_unmask, + .irq_set_type = bcm63138_gpio_irq_set_type, + .irq_print_chip = bcm63138_gpio_irq_print_chip, + .flags = IRQCHIP_IMMUTABLE, + GPIOCHIP_IRQ_RESOURCE_HELPERS, +}; + +/* + * + */ +static int +bcm63138_gpio_irq_child_to_parent_hwirq(struct gpio_chip *gc, + unsigned int child, + unsigned int child_type, + unsigned int *parent, + unsigned int *parent_type) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(gc); + unsigned long flags; + unsigned int i; + int ext_irq; + + /* allocate an external irq number */ + spin_lock_irqsave(&pctl->lock, flags); + ext_irq = -1; + for (i = 0; i < pctl->cfg->ext_irq_count; i++) { + if (pctl->ext_irq_map[i] == -1) { + pctl->ext_irq_map[i] = child; + pctl->ext_irq_revmap[child] = i; + ext_irq = i; + break; + } + } + spin_unlock_irqrestore(&pctl->lock, flags); + + if (ext_irq < 0) + return -ENOSPC; + + *parent_type = IRQ_TYPE_LEVEL_HIGH; + /* actually return the index in ext_irq_parents[] so that + * populate_parent_alloc_arg() callback returns the correct + * fwargs to lookup in GIC */ + *parent = ext_irq; + + return 0; +} + +/* + * + */ +static int +bcm63138_gpio_irq_populate_parent_fwspec(struct gpio_chip *gc, + union gpio_irq_fwspec *gfwspec, + unsigned int parent_hwirq, + unsigned int parent_type) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(gc); + struct irq_fwspec *fwspec = &gfwspec->fwspec; + + *fwspec = pctl->ext_irq_parents[parent_hwirq]; + return 0; +} + +/* + * + */ +static void +bcm63138_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs) +{ + struct irq_data *d; + unsigned long flags; + + d = irq_domain_get_irq_data(domain, virq); + if (d) { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct bcm63138_pinctrl *pctl = gpiochip_get_data(gc); + + spin_lock_irqsave(&pctl->lock, flags); + pctl->ext_irq_map[irqd_to_hwirq(d)] = -1; + spin_unlock_irqrestore(&pctl->lock, flags); + } + + irq_domain_free_irqs_common(domain, virq, nr_irqs); +} + +/* + * + */ +static int bcm63138_gpio_irq_init(struct platform_device *pdev, + struct bcm63138_pinctrl *pctl) +{ + struct gpio_chip *chip = &pctl->gpio_chip; + struct gpio_irq_chip *girq = &chip->irq; + struct irq_domain *parent_domain; + struct device_node *irq_parent; + struct resource *res; + unsigned int i; + int irq, ret; + + if (!pctl->cfg->ext_irq_count) + return 0; + + /* if device tree does not include any interrupt, don't + * register irq chip */ + irq = platform_get_irq_optional(pdev, 0); + if (irq < 0) + return 0; + + for (i = 0; i < pctl->cfg->ext_irq_count; i++) { + struct of_phandle_args map; + int ret; + + ret = of_irq_parse_one(pdev->dev.of_node, i, &map); + if (ret) { + dev_err(&pdev->dev, "irq %d missing\n", i); + return ret; + } + + of_phandle_args_to_fwspec(pdev->dev.of_node, + map.args, map.args_count, + &pctl->ext_irq_parents[i]); + } + + BUG_ON(pctl->cfg->ext_irq_count > EXT_IRQ_MAX_COUNT); + BUG_ON(pctl->cfg->nr_pin_descs > BCM_MAX_GPIOS); + + for (i = 0; i < pctl->cfg->ext_irq_count; i++) + pctl->ext_irq_map[i] = -1; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res) { + dev_err(&pdev->dev, "could not get irq memory\n"); + return -ENODEV; + } + + pctl->irq_base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctl->irq_base)) { + dev_err(&pdev->dev, "could not remap irq memory: %d\n", ret); + return PTR_ERR(pctl->irq_base); + } + + irq_parent = of_irq_find_parent(pdev->dev.of_node); + if (!irq_parent) { + dev_err(&pdev->dev, "No IRQ parent node\n"); + return -ENODEV; + } + + parent_domain = irq_find_host(irq_parent); + of_node_put(irq_parent); + if (!parent_domain) { + dev_err(&pdev->dev, "No IRQ parent domain\n"); + return -ENODEV; + } + + /* setup mux to invalid gpios */ + writel(0xffffffff, + pctl->irq_base + pctl->cfg->ext_irq_mux_sel0_offset); + writel(0xffffffff, + pctl->irq_base + pctl->cfg->ext_irq_mux_sel1_offset); + + gpio_irq_chip_set_chip(girq, &bcm63138_gpio_irq_chip); + girq->fwnode = dev_fwnode(&pdev->dev); + girq->parent_domain = parent_domain; + girq->child_to_parent_hwirq = bcm63138_gpio_irq_child_to_parent_hwirq; + girq->populate_parent_alloc_arg = + bcm63138_gpio_irq_populate_parent_fwspec; + girq->child_irq_domain_ops.free = bcm63138_gpio_irq_domain_free; + + return 0; +} + +static const struct of_device_id bcm63138_pinctrl_match[] = { + { .compatible = "brcm,bcm63138-pinctrl", .data = &bcm63138_soc_config }, + { .compatible = "brcm,bcm63158-pinctrl", .data = &bcm63158_soc_config }, + {} +}; + +/* + * + */ +static int bcm63138_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct bcm63138_pinctrl *pctl; + struct resource *res_mem; + struct pinctrl_pin_desc *pins; + struct gpio_chip *gpio_chip; + unsigned int i; + int ret; + const struct of_device_id *match; + + match = of_match_device(bcm63138_pinctrl_match, &pdev->dev); + if (!match) + return -EINVAL; + + pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + pctl->dev = dev; + pctl->cfg = match->data; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) { + dev_err(dev, "could not get IO memory\n"); + return -ENODEV; + } + + ret = bcm63138_pctrl_build_state(pdev); + if (ret) { + dev_err(dev, "build state failed: %d\n", ret); + return -EINVAL; + } + + pctl->base = devm_ioremap_resource(dev, res_mem); + if (IS_ERR(pctl->base)) + return PTR_ERR(pctl->base); + + /* prepare actual pins from desc */ + pins = devm_kcalloc(&pdev->dev, pctl->cfg->nr_pin_descs, + sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->cfg->nr_pin_descs; i++) + pins[i] = pctl->cfg->pin_descs[i].pin; + + spin_lock_init(&pctl->lock); + pctl->desc.name = dev_name(&pdev->dev); + pctl->desc.owner = THIS_MODULE; + pctl->desc.pins = pins; + pctl->desc.npins = pctl->cfg->nr_pin_descs; + pctl->desc.pctlops = &bcm63138_pctrl_ops; + pctl->desc.pmxops = &bcm63138_pmx_ops; + + pctl->pctl_dev = devm_pinctrl_register(dev, &pctl->desc, pctl); + if (IS_ERR(pctl->pctl_dev)) + return PTR_ERR(pctl->pctl_dev); + + /* add gpio chip */ + gpio_chip = &pctl->gpio_chip; + gpio_chip->base = -1; + gpio_chip->label = "bcm63138-gpio"; + gpio_chip->request = gpiochip_generic_request; + gpio_chip->free = gpiochip_generic_free; + gpio_chip->get = bcm63138_gpio_get; + gpio_chip->set = bcm63138_gpio_set; + gpio_chip->direction_input = bcm63138_gpio_direction_input; + gpio_chip->direction_output = bcm63138_gpio_direction_output; + gpio_chip->get_direction = bcm63138_gpio_get_direction; + gpio_chip->ngpio = pctl->cfg->nr_pin_descs; + gpio_chip->fwnode = dev_fwnode(dev); + gpio_chip->parent = dev; + + ret = bcm63138_gpio_irq_init(pdev, pctl); + if (ret) + return ret; + + ret = devm_gpiochip_add_data(dev, gpio_chip, pctl); + if (ret) + return ret; + + ret = gpiochip_add_pin_range(gpio_chip, pctl->desc.name, + 0, 0, pctl->cfg->nr_pin_descs); + if (ret) + return ret; + + return 0; +}; + +static struct platform_driver bcm63138_pinctrl_driver = { + .probe = bcm63138_pinctrl_probe, + .driver = { + .name = "bcm63138_pinctrl", + .of_match_table = bcm63138_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; + +builtin_platform_driver(bcm63138_pinctrl_driver); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/pinctrl/bcm/pindesc-bcm63138.h 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,790 @@ +static const struct bcm63xx_desc_pin bcm63138_desc_pins[] = { + BCM63XX_PIN( + PINCTRL_PIN(0, "GPIO_00"), + BCM63XX_FUNCTION(1, "SER_LED_DATA"), + BCM63XX_FUNCTION(4, "LED_00"), + BCM63XX_FUNCTION(5, "GPIO_00") + ), + BCM63XX_PIN( + PINCTRL_PIN(1, "GPIO_01"), + BCM63XX_FUNCTION(1, "SER_LED_CLK"), + BCM63XX_FUNCTION(4, "LED_01"), + BCM63XX_FUNCTION(5, "GPIO_01") + ), + BCM63XX_PIN( + PINCTRL_PIN(2, "GPIO_02"), + BCM63XX_FUNCTION(1, "SER_LED_MASK"), + BCM63XX_FUNCTION(4, "LED_02"), + BCM63XX_FUNCTION(5, "GPIO_02") + ), + BCM63XX_PIN( + PINCTRL_PIN(3, "GPIO_03"), + BCM63XX_FUNCTION(1, "UART2_CTS"), + BCM63XX_FUNCTION(2, "NTR_PULSE_IN_0"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_0"), + BCM63XX_FUNCTION(4, "LED_03"), + BCM63XX_FUNCTION(5, "GPIO_03") + ), + BCM63XX_PIN( + PINCTRL_PIN(4, "GPIO_04"), + BCM63XX_FUNCTION(1, "UART2_RTS"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_0"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_1"), + BCM63XX_FUNCTION(4, "LED_04"), + BCM63XX_FUNCTION(5, "GPIO_04") + ), + BCM63XX_PIN( + PINCTRL_PIN(5, "GPIO_05"), + BCM63XX_FUNCTION(1, "UART2_SIN"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_2"), + BCM63XX_FUNCTION(4, "LED_05"), + BCM63XX_FUNCTION(5, "GPIO_05") + ), + BCM63XX_PIN( + PINCTRL_PIN(6, "GPIO_06"), + BCM63XX_FUNCTION(1, "UART2_SOUT"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_3"), + BCM63XX_FUNCTION(4, "LED_06"), + BCM63XX_FUNCTION(5, "GPIO_06") + ), + BCM63XX_PIN( + PINCTRL_PIN(7, "GPIO_07"), + BCM63XX_FUNCTION(1, "SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_1"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_4"), + BCM63XX_FUNCTION(4, "LED_07"), + BCM63XX_FUNCTION(5, "GPIO_07") + ), + BCM63XX_PIN( + PINCTRL_PIN(8, "GPIO_08"), + BCM63XX_FUNCTION(1, "SPIM_SS4_B"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_5"), + BCM63XX_FUNCTION(4, "LED_08"), + BCM63XX_FUNCTION(5, "GPIO_08") + ), + BCM63XX_PIN( + PINCTRL_PIN(9, "GPIO_09"), + BCM63XX_FUNCTION(1, "SPIM_SS3_B"), + BCM63XX_FUNCTION(2, "LD1_DIN"), + BCM63XX_FUNCTION(4, "LED_09"), + BCM63XX_FUNCTION(5, "GPIO_09") + ), + BCM63XX_PIN( + PINCTRL_PIN(10, "GPIO_10"), + BCM63XX_FUNCTION(1, "SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "LD1_DCLK"), + BCM63XX_FUNCTION(4, "LED_10"), + BCM63XX_FUNCTION(5, "GPIO_10") + ), + BCM63XX_PIN( + PINCTRL_PIN(11, "GPIO_11"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_6"), + BCM63XX_FUNCTION(4, "LED_11"), + BCM63XX_FUNCTION(5, "GPIO_11") + ), + BCM63XX_PIN( + PINCTRL_PIN(12, "GPIO_12"), + BCM63XX_FUNCTION(1, "NTR_PULSE_IN"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_7"), + BCM63XX_FUNCTION(4, "LED_12"), + BCM63XX_FUNCTION(5, "GPIO_12") + ), + BCM63XX_PIN( + PINCTRL_PIN(13, "GPIO_13"), + BCM63XX_FUNCTION(1, "NTR_PULSE_OUT_0"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_8"), + BCM63XX_FUNCTION(4, "LED_13"), + BCM63XX_FUNCTION(5, "GPIO_13") + ), + BCM63XX_PIN( + PINCTRL_PIN(14, "GPIO_14"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_9"), + BCM63XX_FUNCTION(4, "LED_14"), + BCM63XX_FUNCTION(5, "GPIO_14") + ), + BCM63XX_PIN( + PINCTRL_PIN(15, "GPIO_15"), + BCM63XX_FUNCTION(4, "LED_15"), + BCM63XX_FUNCTION(5, "GPIO_15") + ), + BCM63XX_PIN( + PINCTRL_PIN(16, "GPIO_16"), + BCM63XX_FUNCTION(3, "DECT_PD_0"), + BCM63XX_FUNCTION(4, "LED_16"), + BCM63XX_FUNCTION(5, "GPIO_16") + ), + BCM63XX_PIN( + PINCTRL_PIN(17, "GPIO_17"), + BCM63XX_FUNCTION(3, "DECT_PD_1"), + BCM63XX_FUNCTION(4, "LED_17"), + BCM63XX_FUNCTION(5, "GPIO_17") + ), + BCM63XX_PIN( + PINCTRL_PIN(18, "GPIO_18"), + BCM63XX_FUNCTION(1, "VREG_CLK"), + BCM63XX_FUNCTION(4, "LED_18"), + BCM63XX_FUNCTION(5, "GPIO_18") + ), + BCM63XX_PIN( + PINCTRL_PIN(19, "GPIO_19"), + BCM63XX_FUNCTION(4, "LED_19"), + BCM63XX_FUNCTION(5, "GPIO_19") + ), + BCM63XX_PIN( + PINCTRL_PIN(20, "GPIO_20"), + BCM63XX_FUNCTION(2, "UART2_CTS"), + BCM63XX_FUNCTION(4, "LED_20"), + BCM63XX_FUNCTION(5, "GPIO_20") + ), + BCM63XX_PIN( + PINCTRL_PIN(21, "GPIO_21"), + BCM63XX_FUNCTION(2, "UART2_RTS"), + BCM63XX_FUNCTION(4, "LED_21"), + BCM63XX_FUNCTION(5, "GPIO_21") + ), + BCM63XX_PIN( + PINCTRL_PIN(22, "GPIO_22"), + BCM63XX_FUNCTION(2, "UART2_SIN"), + BCM63XX_FUNCTION(4, "LED_22"), + BCM63XX_FUNCTION(5, "GPIO_22") + ), + BCM63XX_PIN( + PINCTRL_PIN(23, "GPIO_23"), + BCM63XX_FUNCTION(2, "UART2_SOUT"), + BCM63XX_FUNCTION(4, "LED_23"), + BCM63XX_FUNCTION(5, "GPIO_23") + ), + BCM63XX_PIN( + PINCTRL_PIN(24, "GPIO_24"), + BCM63XX_FUNCTION(1, "NTR_PULSE_OUT_1"), + BCM63XX_FUNCTION(3, "I2C_SDA"), + BCM63XX_FUNCTION(4, "LED_24"), + BCM63XX_FUNCTION(5, "GPIO_24") + ), + BCM63XX_PIN( + PINCTRL_PIN(25, "GPIO_25"), + BCM63XX_FUNCTION(1, "SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_IN"), + BCM63XX_FUNCTION(3, "I2C_SCL"), + BCM63XX_FUNCTION(4, "LED_25"), + BCM63XX_FUNCTION(5, "GPIO_25") + ), + BCM63XX_PIN( + PINCTRL_PIN(26, "GPIO_26"), + BCM63XX_FUNCTION(1, "SPIM_SS3_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_0"), + BCM63XX_FUNCTION(3, "NTR_PULSE_IN"), + BCM63XX_FUNCTION(4, "LED_26"), + BCM63XX_FUNCTION(5, "GPIO_26") + ), + BCM63XX_PIN( + PINCTRL_PIN(27, "GPIO_27"), + BCM63XX_FUNCTION(1, "SPIM_SS4_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_1"), + BCM63XX_FUNCTION(3, "UART2_SIN"), + BCM63XX_FUNCTION(4, "LED_27"), + BCM63XX_FUNCTION(5, "GPIO_27") + ), + BCM63XX_PIN( + PINCTRL_PIN(28, "GPIO_28"), + BCM63XX_FUNCTION(1, "SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "AE_LOS"), + BCM63XX_FUNCTION(3, "UART2_SOUT"), + BCM63XX_FUNCTION(4, "LED_28"), + BCM63XX_FUNCTION(5, "GPIO_28") + ), + BCM63XX_PIN( + PINCTRL_PIN(29, "GPIO_29"), + BCM63XX_FUNCTION(1, "SER_LED_DATA"), + BCM63XX_FUNCTION(4, "LED_29"), + BCM63XX_FUNCTION(5, "GPIO_29") + ), + BCM63XX_PIN( + PINCTRL_PIN(30, "GPIO_30"), + BCM63XX_FUNCTION(1, "SER_LED_CLK"), + BCM63XX_FUNCTION(4, "LED_30"), + BCM63XX_FUNCTION(5, "GPIO_30") + ), + BCM63XX_PIN( + PINCTRL_PIN(31, "GPIO_31"), + BCM63XX_FUNCTION(1, "SER_LED_MASK"), + BCM63XX_FUNCTION(4, "LED_31"), + BCM63XX_FUNCTION(5, "GPIO_31") + ), + BCM63XX_PIN( + PINCTRL_PIN(32, "GPIO_32"), + BCM63XX_FUNCTION(1, "EXT_IRQ_0"), + BCM63XX_FUNCTION(5, "GPIO_32") + ), + BCM63XX_PIN( + PINCTRL_PIN(33, "GPIO_33"), + BCM63XX_FUNCTION(1, "EXT_IRQ_1"), + BCM63XX_FUNCTION(5, "GPIO_33") + ), + BCM63XX_PIN( + PINCTRL_PIN(34, "GPIO_34"), + BCM63XX_FUNCTION(1, "EXT_IRQ_2"), + BCM63XX_FUNCTION(5, "GPIO_34") + ), + BCM63XX_PIN( + PINCTRL_PIN(35, "GPIO_35"), + BCM63XX_FUNCTION(1, "EXT_IRQ_3"), + BCM63XX_FUNCTION(2, "SYS_IRQ_OUT"), + BCM63XX_FUNCTION(5, "GPIO_35") + ), + BCM63XX_PIN( + PINCTRL_PIN(36, "GPIO_36"), + BCM63XX_FUNCTION(1, "EXT_IRQ_4"), + BCM63XX_FUNCTION(2, "AE_LOS"), + BCM63XX_FUNCTION(5, "GPIO_36") + ), + BCM63XX_PIN( + PINCTRL_PIN(37, "GPIO_37"), + BCM63XX_FUNCTION(1, "EXT_IRQ_5"), + BCM63XX_FUNCTION(2, "VREG_CLK"), + BCM63XX_FUNCTION(5, "GPIO_37") + ), + BCM63XX_PIN( + PINCTRL_PIN(38, "GPIO_38"), + BCM63XX_FUNCTION(3, "NAND_CE_B"), + BCM63XX_FUNCTION(5, "GPIO_38") + ), + BCM63XX_PIN( + PINCTRL_PIN(39, "GPIO_39"), + BCM63XX_FUNCTION(3, "NAND_RE_B"), + BCM63XX_FUNCTION(5, "GPIO_39") + ), + BCM63XX_PIN( + PINCTRL_PIN(40, "GPIO_40"), + BCM63XX_FUNCTION(3, "NAND_RB_B"), + BCM63XX_FUNCTION(5, "GPIO_40") + ), + BCM63XX_PIN( + PINCTRL_PIN(41, "GPIO_41"), + BCM63XX_FUNCTION(3, "NAND_DATA_00"), + BCM63XX_FUNCTION(5, "GPIO_41") + ), + BCM63XX_PIN( + PINCTRL_PIN(42, "GPIO_42"), + BCM63XX_FUNCTION(1, "DECT_PD_0"), + BCM63XX_FUNCTION(3, "NAND_DATA_01"), + BCM63XX_FUNCTION(5, "GPIO_42") + ), + BCM63XX_PIN( + PINCTRL_PIN(43, "GPIO_43"), + BCM63XX_FUNCTION(1, "DECT_PD_1"), + BCM63XX_FUNCTION(3, "NAND_DATA_02"), + BCM63XX_FUNCTION(5, "GPIO_43") + ), + BCM63XX_PIN( + PINCTRL_PIN(44, "GPIO_44"), + BCM63XX_FUNCTION(3, "NAND_DATA_03"), + BCM63XX_FUNCTION(5, "GPIO_44") + ), + BCM63XX_PIN( + PINCTRL_PIN(45, "GPIO_45"), + BCM63XX_FUNCTION(3, "NAND_DATA_04"), + BCM63XX_FUNCTION(5, "GPIO_45") + ), + BCM63XX_PIN( + PINCTRL_PIN(46, "GPIO_46"), + BCM63XX_FUNCTION(3, "NAND_DATA_05"), + BCM63XX_FUNCTION(5, "GPIO_46") + ), + BCM63XX_PIN( + PINCTRL_PIN(47, "GPIO_47"), + BCM63XX_FUNCTION(3, "NAND_DATA_06"), + BCM63XX_FUNCTION(5, "GPIO_47") + ), + BCM63XX_PIN( + PINCTRL_PIN(48, "GPIO_48"), + BCM63XX_FUNCTION(3, "NAND_DATA_07"), + BCM63XX_FUNCTION(5, "GPIO_48") + ), + BCM63XX_PIN( + PINCTRL_PIN(49, "GPIO_49"), + BCM63XX_FUNCTION(3, "NAND_ALE"), + BCM63XX_FUNCTION(5, "GPIO_49") + ), + BCM63XX_PIN( + PINCTRL_PIN(50, "GPIO_50"), + BCM63XX_FUNCTION(3, "NAND_WE_B"), + BCM63XX_FUNCTION(5, "GPIO_50") + ), + BCM63XX_PIN( + PINCTRL_PIN(51, "GPIO_51"), + BCM63XX_FUNCTION(3, "NAND_CLE"), + BCM63XX_FUNCTION(5, "GPIO_51") + ), + BCM63XX_PIN( + PINCTRL_PIN(52, "GPIO_52"), + BCM63XX_FUNCTION(1, "LD0_PWRUP"), + BCM63XX_FUNCTION(2, "I2C_SDA"), + BCM63XX_FUNCTION(5, "GPIO_52") + ), + BCM63XX_PIN( + PINCTRL_PIN(53, "GPIO_53"), + BCM63XX_FUNCTION(1, "LD0_DIN"), + BCM63XX_FUNCTION(2, "I2C_SCL"), + BCM63XX_FUNCTION(5, "GPIO_53") + ), + BCM63XX_PIN( + PINCTRL_PIN(54, "GPIO_54"), + BCM63XX_FUNCTION(1, "LD1_PWRUP"), + BCM63XX_FUNCTION(5, "GPIO_54") + ), + BCM63XX_PIN( + PINCTRL_PIN(55, "GPIO_55"), + BCM63XX_FUNCTION(1, "LD0_DCLK"), + BCM63XX_FUNCTION(5, "GPIO_55") + ), + BCM63XX_PIN( + PINCTRL_PIN(56, "GPIO_56"), + BCM63XX_FUNCTION(1, "PCM_SDIN"), + BCM63XX_FUNCTION(5, "GPIO_56") + ), + BCM63XX_PIN( + PINCTRL_PIN(57, "GPIO_57"), + BCM63XX_FUNCTION(1, "PCM_SDOUT"), + BCM63XX_FUNCTION(5, "GPIO_57") + ), + BCM63XX_PIN( + PINCTRL_PIN(58, "GPIO_58"), + BCM63XX_FUNCTION(1, "PCM_CLK"), + BCM63XX_FUNCTION(5, "GPIO_58") + ), + BCM63XX_PIN( + PINCTRL_PIN(59, "GPIO_59"), + BCM63XX_FUNCTION(1, "PCM_FS"), + BCM63XX_FUNCTION(5, "GPIO_59") + ), + BCM63XX_PIN( + PINCTRL_PIN(60, "MII1_COL"), + BCM63XX_FUNCTION(1, "MII1_COL"), + BCM63XX_FUNCTION(5, "GPIO_60") + ), + BCM63XX_PIN( + PINCTRL_PIN(61, "MII1_CRS"), + BCM63XX_FUNCTION(1, "MII1_CRS"), + BCM63XX_FUNCTION(5, "GPIO_61") + ), + BCM63XX_PIN( + PINCTRL_PIN(62, "MII1_RXCLK"), + BCM63XX_FUNCTION(1, "MII1_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_62") + ), + BCM63XX_PIN( + PINCTRL_PIN(63, "MII1_RXER"), + BCM63XX_FUNCTION(1, "MII1_RXER"), + BCM63XX_FUNCTION(5, "GPIO_63") + ), + BCM63XX_PIN( + PINCTRL_PIN(64, "MII1_RXDV"), + BCM63XX_FUNCTION(1, "MII1_RXDV"), + BCM63XX_FUNCTION(5, "GPIO_64") + ), + BCM63XX_PIN( + PINCTRL_PIN(65, "MII_RXD_00"), + BCM63XX_FUNCTION(1, "MII_RXD_00"), + BCM63XX_FUNCTION(5, "GPIO_65") + ), + BCM63XX_PIN( + PINCTRL_PIN(66, "MII_RXD_01"), + BCM63XX_FUNCTION(1, "MII_RXD_01"), + BCM63XX_FUNCTION(5, "GPIO_66") + ), + BCM63XX_PIN( + PINCTRL_PIN(67, "MII_RXD_02"), + BCM63XX_FUNCTION(1, "MII_RXD_02"), + BCM63XX_FUNCTION(5, "GPIO_67") + ), + BCM63XX_PIN( + PINCTRL_PIN(68, "MII_RXD_03"), + BCM63XX_FUNCTION(1, "MII_RXD_03"), + BCM63XX_FUNCTION(5, "GPIO_68") + ), + BCM63XX_PIN( + PINCTRL_PIN(69, "MII_TXCLK"), + BCM63XX_FUNCTION(1, "MII_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_69") + ), + BCM63XX_PIN( + PINCTRL_PIN(70, "MII_TXEN"), + BCM63XX_FUNCTION(1, "MII_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_70") + ), + BCM63XX_PIN( + PINCTRL_PIN(71, "MII_TXER"), + BCM63XX_FUNCTION(1, "MII_TXER"), + BCM63XX_FUNCTION(5, "GPIO_71") + ), + BCM63XX_PIN( + PINCTRL_PIN(72, "MII_TXD_00"), + BCM63XX_FUNCTION(1, "MII_TXD_00"), + BCM63XX_FUNCTION(5, "GPIO_72") + ), + BCM63XX_PIN( + PINCTRL_PIN(73, "MII_TXD_01"), + BCM63XX_FUNCTION(1, "MII_TXD_01"), + BCM63XX_FUNCTION(5, "GPIO_73") + ), + BCM63XX_PIN( + PINCTRL_PIN(74, "MII_TXD_02"), + BCM63XX_FUNCTION(1, "MII_TXD_02"), + BCM63XX_FUNCTION(5, "GPIO_74") + ), + BCM63XX_PIN( + PINCTRL_PIN(75, "MII_TXD_03"), + BCM63XX_FUNCTION(1, "MII_TXD_03"), + BCM63XX_FUNCTION(5, "GPIO_75") + ), + BCM63XX_PIN( + PINCTRL_PIN(76, "RGMII1_RXCLK"), + BCM63XX_FUNCTION(1, "RGMII1_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_76") + ), + BCM63XX_PIN( + PINCTRL_PIN(77, "RGMII1_RXCTL"), + BCM63XX_FUNCTION(1, "RGMII1_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_77") + ), + BCM63XX_PIN( + PINCTRL_PIN(78, "RGMII1_RXD_00"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_00"), + BCM63XX_FUNCTION(5, "GPIO_78") + ), + BCM63XX_PIN( + PINCTRL_PIN(79, "RGMII1_RXD_01"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_01"), + BCM63XX_FUNCTION(5, "GPIO_79") + ), + BCM63XX_PIN( + PINCTRL_PIN(80, "RGMII1_RXD_02"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_02"), + BCM63XX_FUNCTION(5, "GPIO_80") + ), + BCM63XX_PIN( + PINCTRL_PIN(81, "RGMII1_RXD_03"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_03"), + BCM63XX_FUNCTION(5, "GPIO_81") + ), + BCM63XX_PIN( + PINCTRL_PIN(82, "RGMII1_TXCLK"), + BCM63XX_FUNCTION(1, "RGMII1_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_82") + ), + BCM63XX_PIN( + PINCTRL_PIN(83, "RGMII1_TXCTL"), + BCM63XX_FUNCTION(1, "RGMII1_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_83") + ), + BCM63XX_PIN( + PINCTRL_PIN(84, "RGMII1_TXD_00"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_00"), + BCM63XX_FUNCTION(5, "GPIO_84") + ), + BCM63XX_PIN( + PINCTRL_PIN(85, "RGMII1_TXD_01"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_01"), + BCM63XX_FUNCTION(5, "GPIO_85") + ), + BCM63XX_PIN( + PINCTRL_PIN(86, "RGMII1_TXD_02"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_02"), + BCM63XX_FUNCTION(5, "GPIO_86") + ), + BCM63XX_PIN( + PINCTRL_PIN(87, "RGMII1_TXD_03"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_03"), + BCM63XX_FUNCTION(5, "GPIO_87") + ), + BCM63XX_PIN( + PINCTRL_PIN(88, "RGMII2_RXCLK"), + BCM63XX_FUNCTION(1, "RGMII2_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_88") + ), + BCM63XX_PIN( + PINCTRL_PIN(89, "RGMII2_RXCTL"), + BCM63XX_FUNCTION(1, "RGMII2_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_89") + ), + BCM63XX_PIN( + PINCTRL_PIN(90, "RGMII2_RXD_00"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_00"), + BCM63XX_FUNCTION(5, "GPIO_90") + ), + BCM63XX_PIN( + PINCTRL_PIN(91, "RGMII2_RXD_01"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_01"), + BCM63XX_FUNCTION(5, "GPIO_91") + ), + BCM63XX_PIN( + PINCTRL_PIN(92, "RGMII2_RXD_02"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_02"), + BCM63XX_FUNCTION(5, "GPIO_92") + ), + BCM63XX_PIN( + PINCTRL_PIN(93, "RGMII2_RXD_03"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_03"), + BCM63XX_FUNCTION(5, "GPIO_93") + ), + BCM63XX_PIN( + PINCTRL_PIN(94, "RGMII2_TXCLK"), + BCM63XX_FUNCTION(1, "RGMII2_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_94") + ), + BCM63XX_PIN( + PINCTRL_PIN(95, "RGMII2_TXCTL"), + BCM63XX_FUNCTION(1, "RGMII2_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_95") + ), + BCM63XX_PIN( + PINCTRL_PIN(96, "RGMII2_TXD_00"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_00"), + BCM63XX_FUNCTION(5, "GPIO_96") + ), + BCM63XX_PIN( + PINCTRL_PIN(97, "RGMII2_TXD_01"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_01"), + BCM63XX_FUNCTION(5, "GPIO_97") + ), + BCM63XX_PIN( + PINCTRL_PIN(98, "RGMII2_TXD_02"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_02"), + BCM63XX_FUNCTION(5, "GPIO_98") + ), + BCM63XX_PIN( + PINCTRL_PIN(99, "RGMII2_TXD_03"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_03"), + BCM63XX_FUNCTION(5, "GPIO_99") + ), + BCM63XX_PIN( + PINCTRL_PIN(100, "RGMII3_RXCLK"), + BCM63XX_FUNCTION(1, "RGMII3_RXCLK"), + BCM63XX_FUNCTION(4, "LED_00"), + BCM63XX_FUNCTION(5, "GPIO_100") + ), + BCM63XX_PIN( + PINCTRL_PIN(101, "RGMII3_RXCTL"), + BCM63XX_FUNCTION(1, "RGMII3_RXCTL"), + BCM63XX_FUNCTION(4, "LED_01"), + BCM63XX_FUNCTION(5, "GPIO_101") + ), + BCM63XX_PIN( + PINCTRL_PIN(102, "RGMII3_RXD_00"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_00"), + BCM63XX_FUNCTION(4, "LED_02"), + BCM63XX_FUNCTION(5, "GPIO_102") + ), + BCM63XX_PIN( + PINCTRL_PIN(103, "RGMII3_RXD_01"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_01"), + BCM63XX_FUNCTION(4, "LED_03"), + BCM63XX_FUNCTION(5, "GPIO_103") + ), + BCM63XX_PIN( + PINCTRL_PIN(104, "RGMII3_RXD_02"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_02"), + BCM63XX_FUNCTION(4, "LED_04"), + BCM63XX_FUNCTION(5, "GPIO_104") + ), + BCM63XX_PIN( + PINCTRL_PIN(105, "RGMII3_RXD_03"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_03"), + BCM63XX_FUNCTION(4, "LED_05"), + BCM63XX_FUNCTION(5, "GPIO_105") + ), + BCM63XX_PIN( + PINCTRL_PIN(106, "RGMII3_TXCLK"), + BCM63XX_FUNCTION(1, "RGMII3_TXCLK"), + BCM63XX_FUNCTION(4, "LED_06"), + BCM63XX_FUNCTION(5, "GPIO_106") + ), + BCM63XX_PIN( + PINCTRL_PIN(107, "RGMII3_TXCTL"), + BCM63XX_FUNCTION(1, "RGMII3_TXCTL"), + BCM63XX_FUNCTION(4, "LED_07"), + BCM63XX_FUNCTION(5, "GPIO_107") + ), + BCM63XX_PIN( + PINCTRL_PIN(108, "RGMII3_TXD_00"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_00"), + BCM63XX_FUNCTION(4, "LED_08"), + BCM63XX_FUNCTION(5, "GPIO_108"), + BCM63XX_FUNCTION(6, "LED_20") + ), + BCM63XX_PIN( + PINCTRL_PIN(109, "RGMII3_TXD_01"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_01"), + BCM63XX_FUNCTION(4, "LED_09"), + BCM63XX_FUNCTION(5, "GPIO_109"), + BCM63XX_FUNCTION(6, "LED_21") + ), + BCM63XX_PIN( + PINCTRL_PIN(110, "RGMII3_TXD_02"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_02"), + BCM63XX_FUNCTION(4, "LED_10"), + BCM63XX_FUNCTION(5, "GPIO_110") + ), + BCM63XX_PIN( + PINCTRL_PIN(111, "RGMII3_TXD_03"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_03"), + BCM63XX_FUNCTION(4, "LED_11"), + BCM63XX_FUNCTION(5, "GPIO_111") + ), + BCM63XX_PIN( + PINCTRL_PIN(112, "RGMII_MDC"), + BCM63XX_FUNCTION(1, "RGMII_MDC"), + BCM63XX_FUNCTION(5, "GPIO_112") + ), + BCM63XX_PIN( + PINCTRL_PIN(113, "RGMII_MDIO"), + BCM63XX_FUNCTION(1, "RGMII_MDIO"), + BCM63XX_FUNCTION(5, "GPIO_113") + ), + BCM63XX_PIN( + PINCTRL_PIN(114, "BMU_AC_EN"), + BCM63XX_FUNCTION(1, "BMU_AC_EN"), + BCM63XX_FUNCTION(5, "GPIO_114") + ), + BCM63XX_PIN( + PINCTRL_PIN(115, "BMU_DIS_CTRL"), + BCM63XX_FUNCTION(1, "BMU_DIS_CTRL"), + BCM63XX_FUNCTION(5, "GPIO_115") + ), + BCM63XX_PIN( + PINCTRL_PIN(116, "BMU_ENA"), + BCM63XX_FUNCTION(1, "BMU_ENA"), + BCM63XX_FUNCTION(5, "GPIO_116") + ), + BCM63XX_PIN( + PINCTRL_PIN(117, "BMU_ENB"), + BCM63XX_FUNCTION(1, "BMU_ENB"), + BCM63XX_FUNCTION(2, "I2C_SDA"), + BCM63XX_FUNCTION(5, "GPIO_117") + ), + BCM63XX_PIN( + PINCTRL_PIN(118, "BMU_OWA"), + BCM63XX_FUNCTION(1, "BMU_OWA"), + BCM63XX_FUNCTION(5, "GPIO_118") + ), + BCM63XX_PIN( + PINCTRL_PIN(119, "BMU_OWB"), + BCM63XX_FUNCTION(1, "BMU_OWB"), + BCM63XX_FUNCTION(2, "I2C_SCL"), + BCM63XX_FUNCTION(5, "GPIO_119") + ), + BCM63XX_PIN( + PINCTRL_PIN(120, "BMU_PWM_OUT"), + BCM63XX_FUNCTION(1, "BMU_PWM_OUT"), + BCM63XX_FUNCTION(5, "GPIO_120") + ), + BCM63XX_PIN( + PINCTRL_PIN(121, "UART0_SIN"), + BCM63XX_FUNCTION(1, "UART0_SIN"), + BCM63XX_FUNCTION(5, "GPIO_121") + ), + BCM63XX_PIN( + PINCTRL_PIN(122, "UART0_SOUT"), + BCM63XX_FUNCTION(1, "UART0_SOUT"), + BCM63XX_FUNCTION(5, "GPIO_122") + ), + BCM63XX_PIN( + PINCTRL_PIN(123, "SPI_CLK"), + BCM63XX_FUNCTION(0, "SPI_CLK"), + BCM63XX_FUNCTION(5, "GPIO_123") + ), + BCM63XX_PIN( + PINCTRL_PIN(124, "SPI_MOSI"), + BCM63XX_FUNCTION(0, "SPI_MOSI"), + BCM63XX_FUNCTION(5, "GPIO_124") + ), + BCM63XX_PIN( + PINCTRL_PIN(125, "SPI_MISO"), + BCM63XX_FUNCTION(0, "SPI_MISO"), + BCM63XX_FUNCTION(1, "SPI_MISO"), + BCM63XX_FUNCTION(5, "GPIO_125") + ), + BCM63XX_PIN( + PINCTRL_PIN(126, "SPI_SSB0"), + BCM63XX_FUNCTION(0, "SPI_SSB0"), + BCM63XX_FUNCTION(1, "SPI_SSB0"), + BCM63XX_FUNCTION(5, "GPIO_126") + ), + BCM63XX_PIN( + PINCTRL_PIN(127, "SPI_SSB1"), + BCM63XX_FUNCTION(0, "SPI_SSB1"), + BCM63XX_FUNCTION(1, "SPI_SSB1"), + BCM63XX_FUNCTION(5, "GPIO_127") + ), + BCM63XX_PIN( + PINCTRL_PIN(128, "PCIE0_CLKREQ_B"), + BCM63XX_FUNCTION(0, "PCIE0_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_128") + ), + BCM63XX_PIN( + PINCTRL_PIN(129, "PCIE0_RST_B"), + BCM63XX_FUNCTION(0, "PCIE0_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_129") + ), + BCM63XX_PIN( + PINCTRL_PIN(130, "PCIE1_CLKREQ_B"), + BCM63XX_FUNCTION(0, "PCIE1_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_130") + ), + BCM63XX_PIN( + PINCTRL_PIN(131, "PCIE1_RST_B"), + BCM63XX_FUNCTION(0, "PCIE1_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_131") + ), + BCM63XX_PIN( + PINCTRL_PIN(132, "USB0_PWRFLT"), + BCM63XX_FUNCTION(1, "USB0_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_132") + ), + BCM63XX_PIN( + PINCTRL_PIN(133, "USB0_PWRON"), + BCM63XX_FUNCTION(1, "USB0_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_133") + ), + BCM63XX_PIN( + PINCTRL_PIN(134, "USB1_PWRFLT"), + BCM63XX_FUNCTION(1, "USB1_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_134") + ), + BCM63XX_PIN( + PINCTRL_PIN(135, "USB1_PWRON"), + BCM63XX_FUNCTION(1, "USB1_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_135") + ), + BCM63XX_PIN( + PINCTRL_PIN(136, "RESET_OUT_B"), + BCM63XX_FUNCTION(0, "RESET_OUT_B"), + BCM63XX_FUNCTION(5, "GPIO_136") + ), + BCM63XX_PIN( + PINCTRL_PIN(137, "DECT_RDI"), + BCM63XX_FUNCTION(1, "DECT_RDI"), + BCM63XX_FUNCTION(5, "GPIO_137") + ), + BCM63XX_PIN( + PINCTRL_PIN(138, "DECT_BTDO"), + BCM63XX_FUNCTION(1, "DECT_BTDO"), + BCM63XX_FUNCTION(5, "GPIO_138") + ), + BCM63XX_PIN( + PINCTRL_PIN(139, "DECT_MWR_LE"), + BCM63XX_FUNCTION(1, "DECT_MWR_LE"), + BCM63XX_FUNCTION(5, "GPIO_139") + ), + BCM63XX_PIN( + PINCTRL_PIN(140, "DECT_MWR_SK"), + BCM63XX_FUNCTION(1, "DECT_MWR_SK"), + BCM63XX_FUNCTION(5, "GPIO_140") + ), + BCM63XX_PIN( + PINCTRL_PIN(141, "DECT_MWR_SIO"), + BCM63XX_FUNCTION(1, "DECT_MWR_SIO"), + BCM63XX_FUNCTION(5, "GPIO_141") + ), +}; --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/pinctrl/bcm/pindesc-bcm63158.h 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,759 @@ +static const struct bcm63xx_desc_pin bcm63158_desc_pins[] = { + BCM63XX_PIN( + PINCTRL_PIN(0, "GPIO_00"), + BCM63XX_FUNCTION(1, "A_SER_LED_DATA"), + BCM63XX_FUNCTION(4, "A_LED_00"), + BCM63XX_FUNCTION(5, "GPIO_00") + ), + BCM63XX_PIN( + PINCTRL_PIN(1, "GPIO_01"), + BCM63XX_FUNCTION(1, "A_SER_LED_CLK"), + BCM63XX_FUNCTION(4, "A_LED_01"), + BCM63XX_FUNCTION(5, "GPIO_01") + ), + BCM63XX_PIN( + PINCTRL_PIN(2, "GPIO_02"), + BCM63XX_FUNCTION(1, "A_SER_LED_MASK"), + BCM63XX_FUNCTION(4, "A_LED_02"), + BCM63XX_FUNCTION(5, "GPIO_02") + ), + BCM63XX_PIN( + PINCTRL_PIN(3, "GPIO_03"), + BCM63XX_FUNCTION(1, "A_UART2_CTS"), + BCM63XX_FUNCTION(2, "B_PPS_IN"), + BCM63XX_FUNCTION(4, "A_LED_03"), + BCM63XX_FUNCTION(5, "GPIO_03") + ), + BCM63XX_PIN( + PINCTRL_PIN(4, "GPIO_04"), + BCM63XX_FUNCTION(1, "A_UART2_RTS"), + BCM63XX_FUNCTION(2, "B_PPS_OUT"), + BCM63XX_FUNCTION(4, "A_LED_04"), + BCM63XX_FUNCTION(5, "GPIO_04") + ), + BCM63XX_PIN( + PINCTRL_PIN(5, "GPIO_05"), + BCM63XX_FUNCTION(1, "A_UART2_SIN"), + BCM63XX_FUNCTION(4, "A_LED_05"), + BCM63XX_FUNCTION(5, "GPIO_05") + ), + BCM63XX_PIN( + PINCTRL_PIN(6, "GPIO_06"), + BCM63XX_FUNCTION(1, "A_UART2_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_06"), + BCM63XX_FUNCTION(5, "GPIO_06") + ), + BCM63XX_PIN( + PINCTRL_PIN(7, "GPIO_07"), + BCM63XX_FUNCTION(1, "A_SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "B_NTR_OUT"), + BCM63XX_FUNCTION(4, "A_LED_07"), + BCM63XX_FUNCTION(5, "GPIO_07"), + BCM63XX_FUNCTION(6, "B_NTR_IN") + ), + BCM63XX_PIN( + PINCTRL_PIN(8, "GPIO_08"), + BCM63XX_FUNCTION(1, "A_SPIM_SS4_B"), + BCM63XX_FUNCTION(4, "A_LED_08"), + BCM63XX_FUNCTION(5, "GPIO_08") + ), + BCM63XX_PIN( + PINCTRL_PIN(9, "GPIO_09"), + BCM63XX_FUNCTION(1, "A_SPIM_SS3_B"), + BCM63XX_FUNCTION(3, "B_USBD_ID"), + BCM63XX_FUNCTION(4, "A_LED_09"), + BCM63XX_FUNCTION(5, "GPIO_09"), + BCM63XX_FUNCTION(6, "A_AE_SERDES_MOD_DEF0") + ), + BCM63XX_PIN( + PINCTRL_PIN(10, "GPIO_10"), + BCM63XX_FUNCTION(1, "A_SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "A_PMD_EXT_LOS"), + BCM63XX_FUNCTION(3, "B_USBD_VBUS_PRESENT"), + BCM63XX_FUNCTION(4, "A_LED_10"), + BCM63XX_FUNCTION(5, "GPIO_10"), + BCM63XX_FUNCTION(6, "A_AE_FIBER_DETECT") + ), + BCM63XX_PIN( + PINCTRL_PIN(11, "GPIO_11"), + BCM63XX_FUNCTION(2, "A_I2C_SDA_0"), + BCM63XX_FUNCTION(4, "A_LED_11"), + BCM63XX_FUNCTION(5, "GPIO_11") + ), + BCM63XX_PIN( + PINCTRL_PIN(12, "GPIO_12"), + BCM63XX_FUNCTION(1, "A_PPS_IN"), + BCM63XX_FUNCTION(2, "A_I2C_SCL_0"), + BCM63XX_FUNCTION(4, "A_LED_12"), + BCM63XX_FUNCTION(5, "GPIO_12"), + BCM63XX_FUNCTION(6, "C_SGMII_SERDES_MOD_DEF0") + ), + BCM63XX_PIN( + PINCTRL_PIN(13, "GPIO_13"), + BCM63XX_FUNCTION(1, "A_PPS_OUT"), + BCM63XX_FUNCTION(4, "A_LED_13"), + BCM63XX_FUNCTION(5, "GPIO_13") + ), + BCM63XX_PIN( + PINCTRL_PIN(14, "GPIO_14"), + BCM63XX_FUNCTION(1, "A_NTR_OUT"), + BCM63XX_FUNCTION(2, "I2S_RX_SDATA"), + BCM63XX_FUNCTION(4, "A_LED_14"), + BCM63XX_FUNCTION(5, "GPIO_14"), + BCM63XX_FUNCTION(6, "A_NTR_IN") + ), + BCM63XX_PIN( + PINCTRL_PIN(15, "GPIO_15"), + BCM63XX_FUNCTION(2, "SW_SPIS_CLK"), + BCM63XX_FUNCTION(4, "A_LED_15"), + BCM63XX_FUNCTION(5, "GPIO_15"), + BCM63XX_FUNCTION(6, "B_I2C_SDA_1") + ), + BCM63XX_PIN( + PINCTRL_PIN(16, "GPIO_16"), + BCM63XX_FUNCTION(2, "SW_SPIS_SS_B"), + BCM63XX_FUNCTION(4, "A_LED_16"), + BCM63XX_FUNCTION(5, "GPIO_16"), + BCM63XX_FUNCTION(6, "B_I2C_SCL_1") + ), + BCM63XX_PIN( + PINCTRL_PIN(17, "GPIO_17"), + BCM63XX_FUNCTION(2, "SW_SPIS_MISO"), + BCM63XX_FUNCTION(4, "A_LED_17"), + BCM63XX_FUNCTION(5, "GPIO_17"), + BCM63XX_FUNCTION(6, "C_UART3_SIN") + ), + BCM63XX_PIN( + PINCTRL_PIN(18, "GPIO_18"), + BCM63XX_FUNCTION(2, "SW_SPIS_MOSI"), + BCM63XX_FUNCTION(4, "A_LED_18"), + BCM63XX_FUNCTION(5, "GPIO_18"), + BCM63XX_FUNCTION(6, "C_UART3_SOUT") + ), + BCM63XX_PIN( + PINCTRL_PIN(19, "GPIO_19"), + BCM63XX_FUNCTION(2, "VREG_SYNC"), + BCM63XX_FUNCTION(4, "A_LED_19"), + BCM63XX_FUNCTION(5, "GPIO_19"), + BCM63XX_FUNCTION(6, "A_SGMII_FIBER_DETECT") + ), + BCM63XX_PIN( + PINCTRL_PIN(20, "GPIO_20"), + BCM63XX_FUNCTION(1, "SPIS_CLK"), + BCM63XX_FUNCTION(2, "B_UART2_CTS"), + BCM63XX_FUNCTION(3, "B_UART3_SIN"), + BCM63XX_FUNCTION(4, "A_LED_20"), + BCM63XX_FUNCTION(5, "GPIO_20"), + BCM63XX_FUNCTION(6, "A_SGMII_SERDES_MOD_DEF0") + ), + BCM63XX_PIN( + PINCTRL_PIN(21, "GPIO_21"), + BCM63XX_FUNCTION(1, "SPIS_SS_B"), + BCM63XX_FUNCTION(2, "B_UART2_RTS"), + BCM63XX_FUNCTION(3, "B_UART3_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_21"), + BCM63XX_FUNCTION(5, "GPIO_21"), + BCM63XX_FUNCTION(6, "C_SGMII_FIBER_DETECT") + ), + BCM63XX_PIN( + PINCTRL_PIN(22, "GPIO_22"), + BCM63XX_FUNCTION(1, "SPIS_MISO"), + BCM63XX_FUNCTION(2, "B_UART2_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_22"), + BCM63XX_FUNCTION(5, "GPIO_22") + ), + BCM63XX_PIN( + PINCTRL_PIN(23, "GPIO_23"), + BCM63XX_FUNCTION(1, "SPIS_MOSI"), + BCM63XX_FUNCTION(2, "B_UART2_SIN"), + BCM63XX_FUNCTION(4, "A_LED_23"), + BCM63XX_FUNCTION(5, "GPIO_23") + ), + BCM63XX_PIN( + PINCTRL_PIN(24, "GPIO_24"), + BCM63XX_FUNCTION(2, "B_UART1_SOUT"), + BCM63XX_FUNCTION(3, "B_I2C_SDA_0"), + BCM63XX_FUNCTION(4, "A_LED_24"), + BCM63XX_FUNCTION(5, "GPIO_24") + ), + BCM63XX_PIN( + PINCTRL_PIN(25, "GPIO_25"), + BCM63XX_FUNCTION(1, "B_SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "B_UART1_SIN"), + BCM63XX_FUNCTION(3, "B_I2C_SCL_0"), + BCM63XX_FUNCTION(4, "A_LED_25"), + BCM63XX_FUNCTION(5, "GPIO_25") + ), + BCM63XX_PIN( + PINCTRL_PIN(26, "GPIO_26"), + BCM63XX_FUNCTION(1, "B_SPIM_SS3_B"), + BCM63XX_FUNCTION(2, "A_I2C_SDA_1"), + BCM63XX_FUNCTION(3, "A_UART3_SIN"), + BCM63XX_FUNCTION(4, "A_LED_26"), + BCM63XX_FUNCTION(5, "GPIO_26") + ), + BCM63XX_PIN( + PINCTRL_PIN(27, "GPIO_27"), + BCM63XX_FUNCTION(1, "B_SPIM_SS4_B"), + BCM63XX_FUNCTION(2, "A_I2C_SCL_1"), + BCM63XX_FUNCTION(3, "A_UART3_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_27"), + BCM63XX_FUNCTION(5, "GPIO_27") + ), + BCM63XX_PIN( + PINCTRL_PIN(28, "GPIO_28"), + BCM63XX_FUNCTION(1, "B_SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "I2S_MCLK"), + BCM63XX_FUNCTION(4, "A_LED_28"), + BCM63XX_FUNCTION(5, "GPIO_28") + ), + BCM63XX_PIN( + PINCTRL_PIN(29, "GPIO_29"), + BCM63XX_FUNCTION(1, "B_SER_LED_DATA"), + BCM63XX_FUNCTION(2, "I2S_LRCK"), + BCM63XX_FUNCTION(4, "A_LED_29"), + BCM63XX_FUNCTION(5, "GPIO_29") + ), + BCM63XX_PIN( + PINCTRL_PIN(30, "GPIO_30"), + BCM63XX_FUNCTION(1, "B_SER_LED_CLK"), + BCM63XX_FUNCTION(2, "I2S_SCLK"), + BCM63XX_FUNCTION(4, "A_LED_30"), + BCM63XX_FUNCTION(5, "GPIO_30") + ), + BCM63XX_PIN( + PINCTRL_PIN(31, "GPIO_31"), + BCM63XX_FUNCTION(1, "B_SER_LED_MASK"), + BCM63XX_FUNCTION(2, "I2S_TX_SDATA"), + BCM63XX_FUNCTION(4, "A_LED_31"), + BCM63XX_FUNCTION(5, "GPIO_31") + ), + BCM63XX_PIN( + PINCTRL_PIN(32, "GPIO_32"), + BCM63XX_FUNCTION(2, "VDSL_CTRL0"), + BCM63XX_FUNCTION(5, "GPIO_32") + ), + BCM63XX_PIN( + PINCTRL_PIN(33, "GPIO_33"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_1"), + BCM63XX_FUNCTION(3, "B_WAN_EARLY_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_33") + ), + BCM63XX_PIN( + PINCTRL_PIN(34, "GPIO_34"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_2"), + BCM63XX_FUNCTION(3, "B_ROGUE_IN"), + BCM63XX_FUNCTION(5, "GPIO_34") + ), + BCM63XX_PIN( + PINCTRL_PIN(35, "GPIO_35"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_3"), + BCM63XX_FUNCTION(3, "B_SGMII_FIBER_DETECT"), + BCM63XX_FUNCTION(5, "GPIO_35") + ), + BCM63XX_PIN( + PINCTRL_PIN(36, "GPIO_36"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_4"), + BCM63XX_FUNCTION(3, "B_SGMII_SERDES_MOD_DEF0"), + BCM63XX_FUNCTION(5, "GPIO_36") + ), + BCM63XX_PIN( + PINCTRL_PIN(37, "GPIO_37"), + BCM63XX_FUNCTION(1, "B_PMD_EXT_LOS"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_5"), + BCM63XX_FUNCTION(3, "B_AE_FIBER_DETECT"), + BCM63XX_FUNCTION(5, "GPIO_37") + ), + BCM63XX_PIN( + PINCTRL_PIN(38, "GPIO_38"), + BCM63XX_FUNCTION(2, "B_VREG_SYNC"), + BCM63XX_FUNCTION(3, "B_AE_SERDES_MOD_DEF0"), + BCM63XX_FUNCTION(5, "GPIO_38") + ), + BCM63XX_PIN( + PINCTRL_PIN(39, "GPIO_39"), + BCM63XX_FUNCTION(2, "A_WAN_EARLY_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_39") + ), + BCM63XX_PIN( + PINCTRL_PIN(40, "GPIO_40"), + BCM63XX_FUNCTION(2, "A_ROGUE_IN"), + BCM63XX_FUNCTION(5, "GPIO_40") + ), + BCM63XX_PIN( + PINCTRL_PIN(41, "GPIO_41"), + BCM63XX_FUNCTION(2, "SYS_IRQ_OUT"), + BCM63XX_FUNCTION(3, "C_WAN_EARLY_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_41") + ), + BCM63XX_PIN( + PINCTRL_PIN(42, "GPIO_42"), + BCM63XX_FUNCTION(1, "PCM_SDIN"), + BCM63XX_FUNCTION(4, "A_UART1_SIN"), + BCM63XX_FUNCTION(5, "GPIO_42") + ), + BCM63XX_PIN( + PINCTRL_PIN(43, "GPIO_43"), + BCM63XX_FUNCTION(1, "PCM_SDOUT"), + BCM63XX_FUNCTION(4, "A_UART1_SOUT"), + BCM63XX_FUNCTION(5, "GPIO_43") + ), + BCM63XX_PIN( + PINCTRL_PIN(44, "GPIO_44"), + BCM63XX_FUNCTION(1, "PCM_CLK"), + BCM63XX_FUNCTION(4, "A_USBD_VBUS_PRESENT"), + BCM63XX_FUNCTION(5, "GPIO_44") + ), + BCM63XX_PIN( + PINCTRL_PIN(45, "GPIO_45"), + BCM63XX_FUNCTION(1, "PCM_FS"), + BCM63XX_FUNCTION(4, "A_USBD_ID"), + BCM63XX_FUNCTION(5, "GPIO_45") + ), + BCM63XX_PIN( + PINCTRL_PIN(46, "GPIO_46"), + BCM63XX_FUNCTION(2, "C_VREG_SYNC"), + BCM63XX_FUNCTION(5, "GPIO_46") + ), + BCM63XX_PIN( + PINCTRL_PIN(47, "GPIO_47"), + BCM63XX_FUNCTION(3, "NAND_WP"), + BCM63XX_FUNCTION(5, "GPIO_47") + ), + BCM63XX_PIN( + PINCTRL_PIN(48, "GPIO_48"), + BCM63XX_FUNCTION(3, "NAND_CE_B"), + BCM63XX_FUNCTION(5, "GPIO_48") + ), + BCM63XX_PIN( + PINCTRL_PIN(49, "GPIO_49"), + BCM63XX_FUNCTION(3, "NAND_RE_B"), + BCM63XX_FUNCTION(5, "GPIO_49") + ), + BCM63XX_PIN( + PINCTRL_PIN(50, "GPIO_50"), + BCM63XX_FUNCTION(3, "NAND_RB_B"), + BCM63XX_FUNCTION(5, "GPIO_50") + ), + BCM63XX_PIN( + PINCTRL_PIN(51, "GPIO_51"), + BCM63XX_FUNCTION(3, "NAND_DATA_0"), + BCM63XX_FUNCTION(5, "GPIO_51") + ), + BCM63XX_PIN( + PINCTRL_PIN(52, "GPIO_52"), + BCM63XX_FUNCTION(3, "NAND_DATA_1"), + BCM63XX_FUNCTION(5, "GPIO_52") + ), + BCM63XX_PIN( + PINCTRL_PIN(53, "GPIO_53"), + BCM63XX_FUNCTION(3, "NAND_DATA_2"), + BCM63XX_FUNCTION(5, "GPIO_53") + ), + BCM63XX_PIN( + PINCTRL_PIN(54, "GPIO_54"), + BCM63XX_FUNCTION(3, "NAND_DATA_3"), + BCM63XX_FUNCTION(5, "GPIO_54") + ), + BCM63XX_PIN( + PINCTRL_PIN(55, "GPIO_55"), + BCM63XX_FUNCTION(3, "NAND_DATA_4"), + BCM63XX_FUNCTION(5, "GPIO_55") + ), + BCM63XX_PIN( + PINCTRL_PIN(56, "GPIO_56"), + BCM63XX_FUNCTION(3, "NAND_DATA_5"), + BCM63XX_FUNCTION(5, "GPIO_56") + ), + BCM63XX_PIN( + PINCTRL_PIN(57, "GPIO_57"), + BCM63XX_FUNCTION(3, "NAND_DATA_6"), + BCM63XX_FUNCTION(5, "GPIO_57") + ), + BCM63XX_PIN( + PINCTRL_PIN(58, "GPIO_58"), + BCM63XX_FUNCTION(3, "NAND_DATA_7"), + BCM63XX_FUNCTION(5, "GPIO_58") + ), + BCM63XX_PIN( + PINCTRL_PIN(59, "GPIO_59"), + BCM63XX_FUNCTION(3, "NAND_ALE"), + BCM63XX_FUNCTION(5, "GPIO_59") + ), + BCM63XX_PIN( + PINCTRL_PIN(60, "GPIO_60"), + BCM63XX_FUNCTION(3, "NAND_WE_B"), + BCM63XX_FUNCTION(5, "GPIO_60") + ), + BCM63XX_PIN( + PINCTRL_PIN(61, "GPIO_61"), + BCM63XX_FUNCTION(3, "NAND_CLE"), + BCM63XX_FUNCTION(5, "GPIO_61") + ), + BCM63XX_PIN( + PINCTRL_PIN(62, "GPIO_62"), + BCM63XX_FUNCTION(2, "NAND_CE2_B"), + BCM63XX_FUNCTION(3, "EMMC_CLK"), + BCM63XX_FUNCTION(5, "GPIO_62") + ), + BCM63XX_PIN( + PINCTRL_PIN(63, "GPIO_63"), + BCM63XX_FUNCTION(2, "NAND_CE1_B"), + BCM63XX_FUNCTION(3, "EMMC_CMD"), + BCM63XX_FUNCTION(5, "GPIO_63") + ), + BCM63XX_PIN( + PINCTRL_PIN(64, "GPIO_64"), + BCM63XX_FUNCTION(1, "RGMII0_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_64"), + BCM63XX_FUNCTION(6, "B_LED_00") + ), + BCM63XX_PIN( + PINCTRL_PIN(65, "GPIO_65"), + BCM63XX_FUNCTION(5, "GPIO_65"), + BCM63XX_FUNCTION(6, "B_LED_01") + ), + BCM63XX_PIN( + PINCTRL_PIN(66, "GPIO_66"), + BCM63XX_FUNCTION(1, "RGMII0_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_66"), + BCM63XX_FUNCTION(6, "B_LED_02") + ), + BCM63XX_PIN( + PINCTRL_PIN(67, "GPIO_67"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_0"), + BCM63XX_FUNCTION(5, "GPIO_67"), + BCM63XX_FUNCTION(6, "B_LED_03") + ), + BCM63XX_PIN( + PINCTRL_PIN(68, "GPIO_68"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_1"), + BCM63XX_FUNCTION(5, "GPIO_68"), + BCM63XX_FUNCTION(6, "B_LED_04") + ), + BCM63XX_PIN( + PINCTRL_PIN(69, "GPIO_69"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_2"), + BCM63XX_FUNCTION(5, "GPIO_69"), + BCM63XX_FUNCTION(6, "B_LED_05") + ), + BCM63XX_PIN( + PINCTRL_PIN(70, "GPIO_70"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_3"), + BCM63XX_FUNCTION(5, "GPIO_70"), + BCM63XX_FUNCTION(6, "B_LED_06") + ), + BCM63XX_PIN( + PINCTRL_PIN(71, "GPIO_71"), + BCM63XX_FUNCTION(1, "RGMII0_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_71"), + BCM63XX_FUNCTION(6, "B_LED_07") + ), + BCM63XX_PIN( + PINCTRL_PIN(72, "GPIO_72"), + BCM63XX_FUNCTION(1, "RGMII0_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_72"), + BCM63XX_FUNCTION(6, "B_LED_08") + ), + BCM63XX_PIN( + PINCTRL_PIN(73, "GPIO_73"), + BCM63XX_FUNCTION(5, "GPIO_73"), + BCM63XX_FUNCTION(6, "B_LED_09") + ), + BCM63XX_PIN( + PINCTRL_PIN(74, "GPIO_74"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_0"), + BCM63XX_FUNCTION(5, "GPIO_74"), + BCM63XX_FUNCTION(6, "B_LED_10") + ), + BCM63XX_PIN( + PINCTRL_PIN(75, "GPIO_75"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_1"), + BCM63XX_FUNCTION(5, "GPIO_75"), + BCM63XX_FUNCTION(6, "B_LED_11") + ), + BCM63XX_PIN( + PINCTRL_PIN(76, "GPIO_76"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_2"), + BCM63XX_FUNCTION(5, "GPIO_76"), + BCM63XX_FUNCTION(6, "B_LED_12") + ), + BCM63XX_PIN( + PINCTRL_PIN(77, "GPIO_77"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_3"), + BCM63XX_FUNCTION(5, "GPIO_77"), + BCM63XX_FUNCTION(6, "B_LED_13") + ), + BCM63XX_PIN( + PINCTRL_PIN(78, "GPIO_78"), + BCM63XX_FUNCTION(5, "GPIO_78"), + BCM63XX_FUNCTION(6, "B_LED_14") + ), + BCM63XX_PIN( + PINCTRL_PIN(79, "GPIO_79"), + BCM63XX_FUNCTION(5, "GPIO_79"), + BCM63XX_FUNCTION(6, "B_LED_15") + ), + BCM63XX_PIN( + PINCTRL_PIN(80, "GPIO_80"), + BCM63XX_FUNCTION(1, "RGMII1_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_80"), + BCM63XX_FUNCTION(6, "B_LED_16") + ), + BCM63XX_PIN( + PINCTRL_PIN(81, "GPIO_81"), + BCM63XX_FUNCTION(1, "RGMII1_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_81"), + BCM63XX_FUNCTION(6, "B_LED_17") + ), + BCM63XX_PIN( + PINCTRL_PIN(82, "GPIO_82"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_0"), + BCM63XX_FUNCTION(5, "GPIO_82"), + BCM63XX_FUNCTION(6, "B_LED_18") + ), + BCM63XX_PIN( + PINCTRL_PIN(83, "GPIO_83"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_1"), + BCM63XX_FUNCTION(5, "GPIO_83"), + BCM63XX_FUNCTION(6, "B_LED_19") + ), + BCM63XX_PIN( + PINCTRL_PIN(84, "GPIO_84"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_2"), + BCM63XX_FUNCTION(5, "GPIO_84"), + BCM63XX_FUNCTION(6, "B_LED_20") + ), + BCM63XX_PIN( + PINCTRL_PIN(85, "GPIO_85"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_3"), + BCM63XX_FUNCTION(5, "GPIO_85"), + BCM63XX_FUNCTION(6, "B_LED_21") + ), + BCM63XX_PIN( + PINCTRL_PIN(86, "GPIO_86"), + BCM63XX_FUNCTION(1, "RGMII1_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_86"), + BCM63XX_FUNCTION(6, "B_LED_22") + ), + BCM63XX_PIN( + PINCTRL_PIN(87, "GPIO_87"), + BCM63XX_FUNCTION(1, "RGMII1_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_87"), + BCM63XX_FUNCTION(6, "B_LED_23") + ), + BCM63XX_PIN( + PINCTRL_PIN(88, "GPIO_88"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_0"), + BCM63XX_FUNCTION(5, "GPIO_88"), + BCM63XX_FUNCTION(6, "B_LED_24") + ), + BCM63XX_PIN( + PINCTRL_PIN(89, "GPIO_89"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_1"), + BCM63XX_FUNCTION(5, "GPIO_89"), + BCM63XX_FUNCTION(6, "B_LED_25") + ), + BCM63XX_PIN( + PINCTRL_PIN(90, "GPIO_90"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_2"), + BCM63XX_FUNCTION(5, "GPIO_90"), + BCM63XX_FUNCTION(6, "B_LED_26") + ), + BCM63XX_PIN( + PINCTRL_PIN(91, "GPIO_91"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_3"), + BCM63XX_FUNCTION(5, "GPIO_91"), + BCM63XX_FUNCTION(6, "B_LED_27") + ), + BCM63XX_PIN( + PINCTRL_PIN(92, "GPIO_92"), + BCM63XX_FUNCTION(1, "RGMII2_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_92"), + BCM63XX_FUNCTION(6, "B_LED_28") + ), + BCM63XX_PIN( + PINCTRL_PIN(93, "GPIO_93"), + BCM63XX_FUNCTION(1, "RGMII2_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_93"), + BCM63XX_FUNCTION(6, "B_LED_29") + ), + BCM63XX_PIN( + PINCTRL_PIN(94, "GPIO_94"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_0"), + BCM63XX_FUNCTION(5, "GPIO_94"), + BCM63XX_FUNCTION(6, "B_LED_30") + ), + BCM63XX_PIN( + PINCTRL_PIN(95, "GPIO_95"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_1"), + BCM63XX_FUNCTION(5, "GPIO_95"), + BCM63XX_FUNCTION(6, "B_LED_31") + ), + BCM63XX_PIN( + PINCTRL_PIN(96, "GPIO_96"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_2"), + BCM63XX_FUNCTION(5, "GPIO_96") + ), + BCM63XX_PIN( + PINCTRL_PIN(97, "GPIO_97"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_3"), + BCM63XX_FUNCTION(5, "GPIO_97") + ), + BCM63XX_PIN( + PINCTRL_PIN(98, "GPIO_98"), + BCM63XX_FUNCTION(1, "RGMII2_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_98") + ), + BCM63XX_PIN( + PINCTRL_PIN(99, "GPIO_99"), + BCM63XX_FUNCTION(1, "RGMII2_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_99") + ), + BCM63XX_PIN( + PINCTRL_PIN(100, "GPIO_100"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_0"), + BCM63XX_FUNCTION(5, "GPIO_100") + ), + BCM63XX_PIN( + PINCTRL_PIN(101, "GPIO_101"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_1"), + BCM63XX_FUNCTION(5, "GPIO_101") + ), + BCM63XX_PIN( + PINCTRL_PIN(102, "GPIO_102"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_2"), + BCM63XX_FUNCTION(5, "GPIO_102") + ), + BCM63XX_PIN( + PINCTRL_PIN(103, "GPIO_103"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_3"), + BCM63XX_FUNCTION(5, "GPIO_103") + ), + BCM63XX_PIN( + PINCTRL_PIN(104, "GPIO_104"), + BCM63XX_FUNCTION(1, "RGMII_MDC"), + BCM63XX_FUNCTION(5, "GPIO_104") + ), + BCM63XX_PIN( + PINCTRL_PIN(105, "GPIO_105"), + BCM63XX_FUNCTION(1, "RGMII_MDIO"), + BCM63XX_FUNCTION(5, "GPIO_105") + ), + BCM63XX_PIN( + PINCTRL_PIN(106, "GPIO_106"), + BCM63XX_FUNCTION(1, "UART0_SDIN"), + BCM63XX_FUNCTION(5, "GPIO_106") + ), + BCM63XX_PIN( + PINCTRL_PIN(107, "GPIO_107"), + BCM63XX_FUNCTION(1, "UART0_SDOUT"), + BCM63XX_FUNCTION(5, "GPIO_107") + ), + BCM63XX_PIN( + PINCTRL_PIN(108, "GPIO_108"), + BCM63XX_FUNCTION(0, "SPIM_CLK"), + BCM63XX_FUNCTION(5, "GPIO_108") + ), + BCM63XX_PIN( + PINCTRL_PIN(109, "GPIO_109"), + BCM63XX_FUNCTION(0, "SPIM_MOSI"), + BCM63XX_FUNCTION(5, "GPIO_109") + ), + BCM63XX_PIN( + PINCTRL_PIN(110, "GPIO_110"), + BCM63XX_FUNCTION(0, "SPIM_MISO"), + BCM63XX_FUNCTION(5, "GPIO_110") + ), + BCM63XX_PIN( + PINCTRL_PIN(111, "GPIO_111"), + BCM63XX_FUNCTION(0, "SPIM_SS0_B"), + BCM63XX_FUNCTION(5, "GPIO_111") + ), + BCM63XX_PIN( + PINCTRL_PIN(112, "GPIO_112"), + BCM63XX_FUNCTION(0, "SPIM_SS1_B"), + BCM63XX_FUNCTION(5, "GPIO_112") + ), + BCM63XX_PIN( + PINCTRL_PIN(113, "GPIO_113"), + BCM63XX_FUNCTION(1, "PCIE0a_CLKREQ_B"), + BCM63XX_FUNCTION(2, "PCIE2b_CLKREQ_B"), + BCM63XX_FUNCTION(3, "PCIE1c_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_113") + ), + BCM63XX_PIN( + PINCTRL_PIN(114, "GPIO_114"), + BCM63XX_FUNCTION(1, "PCIE0a_RST_B"), + BCM63XX_FUNCTION(2, "PCIE2b_RST_B"), + BCM63XX_FUNCTION(3, "PCIE1c_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_114") + ), + BCM63XX_PIN( + PINCTRL_PIN(115, "GPIO_115"), + BCM63XX_FUNCTION(1, "PCIE1a_CLKREQ_B"), + BCM63XX_FUNCTION(2, "PCIE0b_CLKREQ_B"), + BCM63XX_FUNCTION(3, "PCIE2c_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_115") + ), + BCM63XX_PIN( + PINCTRL_PIN(116, "GPIO_116"), + BCM63XX_FUNCTION(1, "PCIE1a_RST_B"), + BCM63XX_FUNCTION(2, "PCIE0b_RST_B"), + BCM63XX_FUNCTION(3, "PCIE2c_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_116") + ), + BCM63XX_PIN( + PINCTRL_PIN(117, "GPIO_117"), + BCM63XX_FUNCTION(1, "PCIE2a_CLKREQ_B"), + BCM63XX_FUNCTION(2, "PCIE1b_CLKREQ_B"), + BCM63XX_FUNCTION(3, "PCIE0c_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_117") + ), + BCM63XX_PIN( + PINCTRL_PIN(118, "GPIO_118"), + BCM63XX_FUNCTION(1, "PCIE2a_RST_B"), + BCM63XX_FUNCTION(2, "PCIE1b_RST_B"), + BCM63XX_FUNCTION(3, "PCIE0c_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_118") + ), + BCM63XX_PIN( + PINCTRL_PIN(119, "GPIO_119"), + BCM63XX_FUNCTION(1, "PCIE3_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_119") + ), + BCM63XX_PIN( + PINCTRL_PIN(120, "GPIO_120"), + BCM63XX_FUNCTION(0, "PCIE3_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_120") + ), + BCM63XX_PIN( + PINCTRL_PIN(121, "GPIO_121"), + BCM63XX_FUNCTION(1, "USB0a_PWRFLT"), + BCM63XX_FUNCTION(2, "USB1b_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_121") + ), + BCM63XX_PIN( + PINCTRL_PIN(122, "GPIO_122"), + BCM63XX_FUNCTION(1, "USB0a_PWRON"), + BCM63XX_FUNCTION(2, "USB1b_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_122") + ), + BCM63XX_PIN( + PINCTRL_PIN(123, "GPIO_123"), + BCM63XX_FUNCTION(1, "USB1a_PWRFLT"), + BCM63XX_FUNCTION(2, "USB0b_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_123") + ), + BCM63XX_PIN( + PINCTRL_PIN(124, "GPIO_124"), + BCM63XX_FUNCTION(1, "USB1a_PWRON"), + BCM63XX_FUNCTION(2, "USB0b_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_124") + ), + BCM63XX_PIN( + PINCTRL_PIN(125, "GPIO_125"), + BCM63XX_FUNCTION(0, "RESET_OUT_B"), + BCM63XX_FUNCTION(5, "GPIO_125") + ), +}; diff -Nruw linux-6.4-fbx/drivers/platform/fbxgw7r./Kconfig linux-6.4-fbx/drivers/platform/fbxgw7r/Kconfig --- linux-6.4-fbx/drivers/platform/fbxgw7r./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/platform/fbxgw7r/Kconfig 2023-03-09 15:24:23.846931646 +0100 @@ -0,0 +1,6 @@ +config FBXGW7R_PLATFORM + bool "Freebox Gateway V7 specific drivers" + +config FBXGW7R_SWITCH + bool "Freebox Gateway V7 in kernel switch init code." + depends on FBXGW7R_PLATFORM diff -Nruw linux-6.4-fbx/drivers/platform/fbxgw7r./Makefile linux-6.4-fbx/drivers/platform/fbxgw7r/Makefile --- linux-6.4-fbx/drivers/platform/fbxgw7r./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/platform/fbxgw7r/Makefile 2023-03-09 15:24:23.846931646 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FBXGW7R_SWITCH) += fbxgw7r-switch.o diff -Nruw linux-6.4-fbx/drivers/platform/intelce./Kconfig linux-6.4-fbx/drivers/platform/intelce/Kconfig --- linux-6.4-fbx/drivers/platform/intelce./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/platform/intelce/Kconfig 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,18 @@ +# +# IntelCE devices configuration +# + +menu "IntelCE devices" + +config INTELCE_GPIO + tristate "GPIO support" + select ARCH_REQUIRE_GPIOLIB + help + IntelCE 3100/4100 GPIO support. + +config INTELCE_DFX + tristate "DFX reporting support" + help + IntelCE 3100/4100 DFX fuse reporting support. + +endmenu diff -Nruw linux-6.4-fbx/drivers/platform/intelce./Makefile linux-6.4-fbx/drivers/platform/intelce/Makefile --- linux-6.4-fbx/drivers/platform/intelce./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/platform/intelce/Makefile 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,2 @@ +obj-$(CONFIG_INTELCE_GPIO) += gpio-intelce.o +obj-$(CONFIG_INTELCE_DFX) += dfx.o diff -Nruw linux-6.4-fbx/drivers/platform/ipq./Kconfig linux-6.4-fbx/drivers/platform/ipq/Kconfig --- linux-6.4-fbx/drivers/platform/ipq./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/platform/ipq/Kconfig 2023-07-20 17:19:14.610365797 +0200 @@ -0,0 +1,19 @@ + +menuconfig QCOM_IPQ_PLATFORM + bool "Qualcomm IPQ Platform Specific Device Drivers" + default y + depends on ARCH_QCOM || COMPILE_TEST + help + Say Y here to get to see options for device drivers for + various Qualcomm IPQ platforms. This option alone does not + add any kernel code. + + If you say N, all options in this submenu will be skipped + and disabled. + +if QCOM_IPQ_PLATFORM + +config IPQ_SEC_UPGRADE + bool "Qualcomm IPQ sec-upgrade driver." + +endif diff -Nruw linux-6.4-fbx/drivers/platform/ipq./Makefile linux-6.4-fbx/drivers/platform/ipq/Makefile --- linux-6.4-fbx/drivers/platform/ipq./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/platform/ipq/Makefile 2023-07-20 17:19:14.610365797 +0200 @@ -0,0 +1 @@ +obj-$(CONFIG_IPQ_SEC_UPGRADE) += sec-upgrade.o --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/bpcm_defs.h 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,76 @@ +#ifndef BPCM_DEFS_H_ +#define BPCM_DEFS_H_ + +/* + * BPCM (Block Power Control Module) registers definitions + */ +#define _F(value, shift, mask) (((value) & mask) << shift) +#define BPCM_SR_CONTROL_REG 0x28 + +#define BPCM_ZONE_REG(z) (0x40 + 0x10 * (z)) +#define BPCM_ZONE_MANUAL_CLK_EN (1 << 0) +#define BPCM_ZONE_MANUAL_RESET_CTL (1 << 1) +#define BPCM_ZONE_FREQ_SCALE_USED (1 << 2) +#define BPCM_ZONE_DPG_CAPABLE (1 << 3) +#define BPCM_ZONE_MANUAL_MEM_PWR(x) _F(x, 4, 0x3) +#define BPCM_ZONE_MANUAL_MEM_PWR_MASK _F(0x3, 4, 0x3) +#define BPCM_ZONE_MANUAL_ISO_CTL (1 << 6) +#define BPCM_ZONE_MANUAL_CTL (1 << 7) +#define BPCM_ZONE_DPG_CTL_EN (1 << 8) +#define BPCM_ZONE_PWR_DN_REQ (1 << 9) +#define BPCM_ZONE_PWR_UP_REQ (1 << 10) +#define BPCM_ZONE_MEM_PWR_CTL_EN (1 << 11) +#define BPCM_ZONE_BLK_RESET_ASSERT (1 << 12) +#define BPCM_ZONE_PWR_CNTL_STATE(x) _F(x, 19, 0x1f) +#define BPCM_ZONE_PWR_CNTL_STATE_MASK _F(0x1f, 19, 0x1f) +#define BPCM_ZONE_FREQ_SCALAR_DYN_SEL (1 << 24) +#define BPCM_ZONE_PWR_OFF_STATE (1 << 25) +#define BPCM_ZONE_PWR_ON_STATE (1 << 26) +#define BPCM_ZONE_PWR_GOOD (1 << 27) +#define BPCM_ZONE_DPG_PWR_STATE (1 << 28) +#define BPCM_ZONE_MEM_PWR_STATE (1 << 29) +#define BPCM_ZONE_ISO_STATE (1 << 30) +#define BPCM_ZONE_RESET_STATE (1 << 31) + +#define BPCM_ARM_CONTROL_REG 0x30 +#define BPCM_ARM_PWR_CONTROL_BASE_REG 0x34 +#define BPCM_ARM_PWR_CONTROL_REG(x) (BPCM_ARM_PWR_CONTROL_BASE_REG + (x) * 0x4) +#define BPCM_ARM_NEON_L2_REG 0x3c + + +/* ARM Control register definitions */ +#define CORE_PWR_CTRL_SHIFT 0 +#define CORE_PWR_CTRL_MASK 0x3 +#define PLL_PWR_ON BIT(8) +#define PLL_LDO_PWR_ON BIT(9) +#define PLL_CLAMP_ON BIT(10) +#define CPU_RESET_N(x) BIT(13 + (x)) +#define NEON_RESET_N BIT(15) +#define PWR_CTRL_STATUS_SHIFT 28 +#define PWR_CTRL_STATUS_MASK 0x3 +#define PWR_DOWN_SHIFT 30 +#define PWR_DOWN_MASK 0x3 + +/* CPU Power control register definitions */ +#define MEM_PWR_OK BIT(0) +#define MEM_PWR_ON BIT(1) +#define MEM_CLAMP_ON BIT(2) +#define MEM_PWR_OK_STATUS BIT(4) +#define MEM_PWR_ON_STATUS BIT(5) +#define MEM_PDA_SHIFT 8 +#define MEM_PDA_MASK 0xf +#define MEM_PDA_CPU_MASK 0x1 +#define MEM_PDA_NEON_MASK 0xf +#define CLAMP_ON BIT(15) +#define PWR_OK_SHIFT 16 +#define PWR_OK_MASK 0xf +#define PWR_ON_SHIFT 20 +#define PWR_CPU_MASK 0x03 +#define PWR_NEON_MASK 0x01 +#define PWR_ON_MASK 0xf +#define PWR_OK_STATUS_SHIFT 24 +#define PWR_OK_STATUS_MASK 0xf +#define PWR_ON_STATUS_SHIFT 28 +#define PWR_ON_STATUS_MASK 0xf + +#endif /* ! BPCM_DEFS_H_ */ --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/memc-bcm63158.c 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,305 @@ +/* + * memc-bcm63158.c for memc-bcm63158 + * Created by on Mon Apr 20 18:06:35 2020 + */ + +#include +#include +#include +#include +#include +#include + +#define MEMC_IDLE_PAD_CONTROL 0x20034 +#define MEMC_IDLE_PAD_EN0 0x20038 +#define MEMC_IDLE_PAD_EN1 0x2003c + +#define MEMC_CLK_MHZ 533 +#define MEMC_IDLE_THRESH_USEC 20 + +#define MEMC_AUTO_SR_REG 0x0025c +#define MEMC_AUTO_SR_EN (1 << 31) +#define MEMC_AUTO_SR_THRESH_MASK 0x7fffffff +#define MEMC_AUTO_SR_THRESH_VAL(v) ((v) & MEMC_AUTO_SR_THRESH_MASK) + +#define MEMC_GLOBAL_CONFIG_REG 0x00004 +#define MEMC_GLOBAL_CONFIG_SLOW_CLK_EN (1 << 26) + +struct bcm63158_memc_priv { + void __iomem *regs; + struct resource regs_res; + struct platform_device *pdev; + + u32 sr_idle_thresh; + bool auto_sr_en; + + struct mutex mutex; + + struct dentry *debugfs_dir; +}; + +static inline u32 memc_readl(struct bcm63158_memc_priv *priv, u32 off) +{ + u32 ret; + + ret = readl(priv->regs + off); + dev_dbg(&priv->pdev->dev, "memc_readl(): @%08llx: %08x", + priv->regs_res.start + off, ret); + return ret; +} + +static inline void memc_writel(u32 v, struct bcm63158_memc_priv *priv, u32 off) +{ + dev_dbg(&priv->pdev->dev, "memc_writel(): @%08llx: %08x", + priv->regs_res.start + off, v); + writel(v, priv->regs + off); +} + +/* + * same init as in the refsw. + */ +static void bcm63158_memc_idle_pad_init(struct bcm63158_memc_priv *priv) +{ + mutex_lock(&priv->mutex); + + memc_writel(0xe, priv, MEMC_IDLE_PAD_CONTROL); + memc_writel(0x6df, priv, MEMC_IDLE_PAD_EN0); + memc_writel(0x3fffff, priv, MEMC_IDLE_PAD_EN1); + + mutex_unlock(&priv->mutex); +} + +/* + * set idle time in usec after which the MEMC will go automatically in + * self-refresh mode. + */ +static int bcm63158_memc_auto_sr_thresh_set(struct bcm63158_memc_priv *priv, + u32 v) +{ + u32 reg; + + v *= MEMC_CLK_MHZ; + if ((v & MEMC_AUTO_SR_THRESH_MASK) != v) + return -EINVAL; + + mutex_lock(&priv->mutex); + + reg = memc_readl(priv, MEMC_AUTO_SR_REG); + reg &= ~MEMC_AUTO_SR_THRESH_MASK; + reg |= MEMC_AUTO_SR_THRESH_VAL(v); + memc_writel(reg, priv, MEMC_AUTO_SR_REG); + + mutex_unlock(&priv->mutex); + return 0; +} + +/* + * enable or disable automatic self refresh + */ +static void bcm63158_memc_auto_sr_enable(struct bcm63158_memc_priv *priv, + bool en) +{ + u32 reg; + + mutex_lock(&priv->mutex); + + reg = memc_readl(priv, MEMC_AUTO_SR_REG); + if (en) + reg |= MEMC_AUTO_SR_EN; + else + reg &= ~MEMC_AUTO_SR_EN; + memc_writel(reg, priv, MEMC_AUTO_SR_REG); + + mutex_unlock(&priv->mutex); +} + +/* + * same as refsw. + */ +static void bcm63158_memc_enable_slow_clock(struct bcm63158_memc_priv *priv) +{ + u32 reg; + + mutex_lock(&priv->mutex); + + reg = memc_readl(priv, MEMC_GLOBAL_CONFIG_REG); + reg |= MEMC_GLOBAL_CONFIG_SLOW_CLK_EN; + memc_writel(reg, priv, MEMC_GLOBAL_CONFIG_REG); + + mutex_unlock(&priv->mutex); +} + +/* + * auto-sr-en debugfs stuff + */ +static int bcm63158_memc_autosr_en_read(void *_priv, u64 *val) +{ + struct bcm63158_memc_priv *priv = _priv; + + *val = !!(memc_readl(priv, MEMC_AUTO_SR_REG) & MEMC_AUTO_SR_EN); + return 0; +} + +static int bcm63158_memc_autosr_en_write(void *_priv, u64 val) +{ + struct bcm63158_memc_priv *priv = _priv; + + bcm63158_memc_auto_sr_enable(priv, !!val); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(memc_autosr_en_fops, bcm63158_memc_autosr_en_read, + bcm63158_memc_autosr_en_write, "%llu\n"); + +/* + * auto-sr-thresh debugfs stuff + */ +static int bcm63158_memc_autosr_thresh_read(void *_priv, u64 *val) +{ + struct bcm63158_memc_priv *priv = _priv; + + *val = (memc_readl(priv, MEMC_AUTO_SR_REG) & MEMC_AUTO_SR_THRESH_MASK) + / MEMC_CLK_MHZ; + return 0; +} + +static int bcm63158_memc_autosr_thresh_write(void *_priv, u64 val) +{ + struct bcm63158_memc_priv *priv = _priv; + + return bcm63158_memc_auto_sr_thresh_set(priv, val); +} + + +DEFINE_SIMPLE_ATTRIBUTE(memc_autosr_thresh_fops, + bcm63158_memc_autosr_thresh_read, + bcm63158_memc_autosr_thresh_write, "%llu\n"); + +/* + * create debugfs entries, always report success, as debugfs support + * may not be compiled in. + */ +static int bcm63158_memc_create_debugfs(struct bcm63158_memc_priv *priv) +{ + priv->debugfs_dir = debugfs_create_dir("bcm63158-memc", NULL); + if (IS_ERR(priv->debugfs_dir)) { + dev_warn(&priv->pdev->dev, "unable to create debugfs " + "directory"); + priv->debugfs_dir = NULL; + return 0; + } + + debugfs_create_file("auto-sr-en", S_IWUSR | S_IRUSR, + priv->debugfs_dir, priv, + &memc_autosr_en_fops); + debugfs_create_file("auto-sr-thresh", S_IWUSR | S_IRUSR, + priv->debugfs_dir, priv, + &memc_autosr_thresh_fops); + + return 0; +} + +/* + * remove debugfs entries + */ +static int bcm63158_memc_remove_debugfs(struct bcm63158_memc_priv *priv) +{ + if (priv->debugfs_dir) + debugfs_remove_recursive(priv->debugfs_dir); + + return 0; +} + + +static int bcm63158_memc_probe(struct platform_device *pdev) +{ + struct resource *res; + struct bcm63158_memc_priv *priv; + + dev_dbg(&pdev->dev, "probe"); + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to get resource for MEMC " + "registers."); + return -ENXIO; + } + priv->regs_res = *res; + + priv->regs = devm_ioremap_resource(&pdev->dev, &priv->regs_res); + if (IS_ERR(priv->regs)) { + dev_err(&pdev->dev, "unable to ioremap MEMC registers"); + return PTR_ERR(priv->regs); + } + + mutex_init(&priv->mutex); + priv->pdev = pdev; + + /* + * default values, possibly overridden with OF + */ + priv->sr_idle_thresh = MEMC_IDLE_THRESH_USEC; + priv->auto_sr_en = false; + + of_property_read_u32(pdev->dev.of_node, "brcm,auto-sr-thresh", + &priv->sr_idle_thresh); + priv->auto_sr_en = of_property_read_bool(pdev->dev.of_node, + "brcm,auto-sr-en"); + + dev_info(&pdev->dev, "auto-sr-thresh: %d", priv->sr_idle_thresh); + dev_info(&pdev->dev, "auto-sr-en: %d", priv->auto_sr_en); + + /* + * init + */ + bcm63158_memc_idle_pad_init(priv); + bcm63158_memc_enable_slow_clock(priv); + + /* + * set default values or OF values. + */ + bcm63158_memc_auto_sr_thresh_set(priv, priv->sr_idle_thresh); + bcm63158_memc_auto_sr_enable(priv, priv->auto_sr_en); + + /* + * create debugfs attributes + */ + bcm63158_memc_create_debugfs(priv); + dev_set_drvdata(&pdev->dev, priv); + + return 0; +} + +static int bcm63158_memc_remove(struct platform_device *pdev) +{ + struct bcm63158_memc_priv *priv = dev_get_drvdata(&pdev->dev); + + dev_dbg(&pdev->dev, "remove"); + bcm63158_memc_remove_debugfs(priv); + return 0; +} + +static const struct of_device_id bcm63158_memc_of_match[] = { + { .compatible = "brcm,bcm63158-memc" }, + {}, +}; + +static struct platform_driver bcm63158_memc_driver = { + .probe = bcm63158_memc_probe, + .remove = bcm63158_memc_remove, + .driver = { + .name = "bcm63158-memc", + .owner = THIS_MODULE, + .of_match_table = bcm63158_memc_of_match, + } +}; + +module_platform_driver(bcm63158_memc_driver); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63158 SoC MEMC driver."); +MODULE_LICENSE("GPL v2"); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/pmc.c 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,2237 @@ +/* + * drivers/soc/bcm63xx/pmc.c + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "bcm63xx-pmc: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bpcm_defs.h" + +#define VERBOSE_PMC + +/* + * PMC registers offsets + */ +#define PMC_CTRL_REG (0x1000) +#define PMC_HOST_MBOX_IN_REG (0x1028) +#define PMC_HOST_MBOX_OUT_REG (0x102c) +#define PMC_ADDR2_WIN_MASK_REG (0x1078) +#define PMC_ADDR2_WIN_BASEIN_REG (0x107c) +#define PMC_ADDR2_WIN_BASEOUT_REG (0x1080) +#define PMC_TIM2CTRL_REG (0x10b4) +#define PMC_TIM2CNT_REG (0x10b8) + +#define PMC_DQM_REQ_REG(__x) (0x1c00 + 4 * __x) +#define PMC_DQM_RPL_REG(__x) (0x1c10 + 4 * __x) +#define PMC_QSTATUS (0x1f00) +#define PMC_DQM_STS_REG (0x1820) +#define PMC_DQM_STS_NOTEMPTY (1 << 1) + +enum { + PMC_RSTATE_EXECUTING_BOOTROM, + PMC_RSTATE_WAITING_BMU_COMPLETE, + PMC_RSTATE_AVS_COMPLETE_WAITING_FOR_IMAGE, + PMC_RSTATE_AUTHENTICATING_IMAGE, + PMC_RSTATE_AUTHENTICATION_FAILED, + PMC_RSTATE_RESERVED, + PMC_RSTATE_FATAL_ERROR, + PMC_RSTATE_RUNNING +}; + +/* + * list of known PMB devices & their respective "addresses" + */ +#define PMB_BUS_ID_SHIFT 8 + +enum pmc_bus_id { + PMB_BUS_SF2, + PMB_BUS_SAR, + PMB_BUS_AIP, + PMB_BUS_AFEPLL, + PMB_BUS_RDP, + PMB_BUS_RDPPLL, + PMB_BUS_USB30_2X, +}; + +struct pmc_addr_info { + bool valid; + unsigned int dev; + unsigned int bus_id; +}; + +static const struct pmc_addr_info bcm63138_pmc_addr_info[PMB_ADDR_LAST] = { + [PMB_ADDR_SF2] = { true, 1, 1 }, + [PMB_ADDR_AIP] = { true, 4, 0 }, + [PMB_ADDR_SAR] = { true, 6, 1 }, + [PMB_ADDR_RDP] = { true, 7, 1 }, + [PMB_ADDR_RDPPLL] = { true, 11, 1 }, + [PMB_ADDR_USB30_2X] = { true, 17, 1 }, + [PMB_ADDR_VDSL3_MIPS] = { true, 21, 0 }, + [PMB_ADDR_VDSL3_CORE] = { true, 22, 0 }, + [PMB_ADDR_VDSL3_CORE] = { true, 22, 0 }, + [PMB_ADDR_AFEPLL] = { true, 23, 0 }, +}; + +static const struct pmc_addr_info bcm63158_pmc_addr_info[PMB_ADDR_LAST] = { + [PMB_ADDR_SYSTEMPORT] = { true, 0, 0 }, + [PMB_ADDR_SF2] = { true, 0, 1 }, + [PMB_ADDR_PCIE0] = { true, 8, 0 }, + [PMB_ADDR_PCIE1] = { true, 9, 0 }, + [PMB_ADDR_PCIE2] = { true, 10, 0 }, + [PMB_ADDR_PCIE3] = { true, 12, 1 }, + [PMB_ADDR_USB30_2X] = { true, 13, 1 }, + [PMB_ADDR_WAN] = { true, 15, 1 }, + [PMB_ADDR_XRDP] = { true, 16, 1 }, + [PMB_ADDR_XRDP_RC0] = { true, 17, 1 }, + [PMB_ADDR_XRDP_RC1] = { true, 18, 1 }, + [PMB_ADDR_XRDP_RC2] = { true, 19, 1 }, + [PMB_ADDR_XRDP_RC3] = { true, 20, 1 }, + [PMB_ADDR_XRDP_RC4] = { true, 21, 1 }, + [PMB_ADDR_XRDP_RC5] = { true, 22, 1 }, + [PMB_ADDR_VDSL3_CORE] = { true, 23, 0 }, + [PMB_ADDR_VDSL3_PMB] = { true, 24, 0 }, + [PMB_ADDR_AFEPLL] = { true, 26, 0 }, + [PMB_ADDR_BIU_PLL] = { true, 38, 0 }, +}; + +/* + * list of known PMC commands + */ +enum { + PMC_CMD_RESERVED = 0, + PMC_CMD_GET_DEV_PRESENCE, + PMC_CMD_GET_SW_STRAP, + PMC_CMD_GET_HW_REV, + PMC_CMD_GET_NUM_ZONES, + PMC_CMD_PING, + PMC_CMD_GET_NEXT_LOG_ENTRY, + PMC_CMD_GET_RMON_AND_SIGMA, + PMC_CMD_SET_CLOCK_HIGH_GEAR, + PMC_CMD_SET_CLOCK_LOW_GEAR, + PMC_CMD_SET_CLOCK_GEAR, + + PMC_CMD_READ_BPCM_REG, + PMC_CMD_READ_ZONE_REG, + PMC_CMD_WRITE_BPCM_REG, + PMC_CMD_WRITE_ZONE_REG, + PMC_CMD_SET_RUN_STATE, + PMC_CMD_SET_POWER_STATE, + PMC_CMD_SHUTDOWN_ALLOWED, + PMC_CMD_GET_SELECT0, + PMC_CMD_GET_SELECT3, + PMC_CMD_GET_AVS_DISABLE_STATE, + + PMC_CMD_GET_PVT, + PMC_CMD_POWER_DEV_ONOFF, + PMC_CMD_POWER_ZONE_ONOFF, + PMC_CMD_RESET_DEVICE, + PMC_CMD_RESET_ZONE, + PMC_CMD_ALLOCATE_G2UDQM, + PMC_CMD_QSM_AVAILABLE, + PMC_CMD_REVISION, + PMC_CMD_REGISTER_CMD_HANDLER, + PMC_CMD_FIND_UNUSED_COMMAND, + + PMC_CMD_LOCK_CMD_TABLE, + PMC_CMD_JUMPAPP, + PMC_CMD_STALL, + PMC_CMD_CLOSEAVS, +}; + +struct pmc_command { + struct { + union { + struct { + u32 cmd_id: 8; + u32 error: 8; + u32 msgid: 8; + u32 srcport: 8; + }; + u32 all; + }; + } word0; + + struct { + union { + struct { + u32 zone_idx: 10; + u32 dev_addr: 10; + u32 island: 4; + u32 log_num: 8; + }; + u32 all; + }; + } word1; + + union { + + struct { + u32 params[2]; + } generic_params; + + struct { + u32 word2; + u32 word3; + } command_response; + + struct { + u8 reserved[2]; + u8 restore; + u8 state; + + u32 unused; + } command_power; + + struct { + u16 margin_mv_slow; + u16 max_mv; + u16 margin_mv_fast; + u16 min_mv; + } close_avs_63158; + }; +}; + +struct bcm63xx_pmc { + struct device *dev; + u32 soc_id; + void __iomem *base; + unsigned int req_sequnum; + struct mutex pmc_lock; + struct reset_controller_dev rcdev; + + bool init_done; + struct dentry *debugfs_dir; + + u16 avs_margin_ff; + u16 avs_margin_ss; +}; + +#define to_pmc_reset_priv(p) \ + container_of((p), struct bcm63xx_pmc, rcdev) + +static struct bcm63xx_pmc *pmc = &(struct bcm63xx_pmc) {}; + +static int __init pmc_create_debugfs(struct bcm63xx_pmc *pmc); + +/* + * + */ +static int __pmc_send_command(struct bcm63xx_pmc *priv, + struct pmc_command *cmd, + struct pmc_command *rsp) +{ + u32 tries = 50000; + + priv->req_sequnum = (priv->req_sequnum + 1) & 0xff; + cmd->word0.msgid = priv->req_sequnum; + + /* + * write request command to PMC registers. + */ + writel(cmd->word0.all, priv->base + PMC_DQM_REQ_REG(0)); + writel(cmd->word1.all, priv->base + PMC_DQM_REQ_REG(1)); + writel(cmd->generic_params.params[0], priv->base + PMC_DQM_REQ_REG(2)); + writel(cmd->generic_params.params[1], priv->base + PMC_DQM_REQ_REG(3)); + + /* + * wait for PMC to reply. + */ + while (tries) { + u32 sts; + + udelay(10); + sts = readl(priv->base + PMC_DQM_STS_REG); + if ((sts & PMC_DQM_STS_NOTEMPTY)) + goto finished; + --tries; + } + + /* timeout */ + dev_err(priv->dev, "PMC command %d (seq %d)failed.\n", + cmd->word0.cmd_id, priv->req_sequnum); + return -ETIMEDOUT; + +finished: + memset(rsp, 0, sizeof (*rsp)); + rsp->word0.all = readl(priv->base + PMC_DQM_RPL_REG(0)); + rsp->word1.all = readl(priv->base + PMC_DQM_RPL_REG(1)); + rsp->generic_params.params[0] = readl(priv->base + PMC_DQM_RPL_REG(2)); + rsp->generic_params.params[1] = readl(priv->base + PMC_DQM_RPL_REG(3)); + + if (rsp->word0.msgid == priv->req_sequnum) { + /* + * PMC replied to correct command, look into error of + * the reply. + */ + if (rsp->word0.error) { + dev_info(priv->dev, "PMC reported error: %d\n", + rsp->word0.error); + return -EIO; + } + } else { + /* + * PMC is drunk ? + */ + dev_err(priv->dev, "PMC reported completion cmd seq %d " + "(PMC drunk?)\n", rsp->word0.msgid); + return -EILSEQ; + } + + return 0; +} + +/* + * + */ +static int pmc_send_command(struct bcm63xx_pmc *priv, struct pmc_command *cmd, + struct pmc_command *rsp) +{ + int ret; + + mutex_lock(&priv->pmc_lock); + ret = __pmc_send_command(priv, cmd, rsp); + mutex_unlock(&priv->pmc_lock); + return ret; +} + +/* + * + */ +static u32 pmc_get_dev_addr(struct bcm63xx_pmc *priv, enum pmc_addr_id addr_id) +{ + const struct pmc_addr_info *info; + + switch (priv->soc_id) { + case 0x63138: + info = bcm63138_pmc_addr_info; + break; + case 0x63158: + info = bcm63158_pmc_addr_info; + break; + default: + WARN(1, "missing addr info for this soc id"); + return 0; + } + + BUG_ON(!info[addr_id].valid); + return info[addr_id].dev | (info[addr_id].bus_id << PMB_BUS_ID_SHIFT); +} + +/* + * + */ +static int pmc_power_on_cmd(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_POWER_DEV_ONOFF; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + cmd.command_power.state = 1; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + return 0; +} + +/* + * + */ +static int pmc_power_off_cmd(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_POWER_DEV_ONOFF; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + cmd.command_power.state = 0; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + return 0; +} + +/* + * + */ +int pmc_read_bpcm_register(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, + u32 word_offset, u32 *value) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_READ_BPCM_REG; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + + cmd.generic_params.params[0] = word_offset >> 2; + cmd.generic_params.params[1] = 0; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *value = rsp.command_response.word2; + + return 0; +} +EXPORT_SYMBOL_GPL(pmc_read_bpcm_register); + +/* + * + */ +int pmc_get_avs_state(struct bcm63xx_pmc *priv, int island, bool *state) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_GET_AVS_DISABLE_STATE; + cmd.word1.island = island; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *state = !rsp.command_response.word2; + return 0; +} + +/* + * + */ +static int pmc_close_avs(struct bcm63xx_pmc *pmc) +{ + struct pmc_command cmd, rsp; + int error; + + /* + * PMC_CMD_CLOSEAVS command format is different on non 63158 + * SoCs. + */ + if (pmc->soc_id != 0x63158) + return -ENXIO; + + pr_info("PMC: close AVS with %u mv (SS silicon) and " + "%u mv (FF silicon)\n", pmc->avs_margin_ss, + pmc->avs_margin_ff); + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_CLOSEAVS; + + /* + * NOTE: keep min_mv and max_mv to 0 to let the firmware use + * the default values for minimum and maximum AVS tension. + */ + cmd.close_avs_63158.margin_mv_fast = pmc->avs_margin_ff; + cmd.close_avs_63158.margin_mv_slow = pmc->avs_margin_ss; + + error = pmc_send_command(pmc, &cmd, &rsp); + if (error) { + pr_err("PMC close AVS failed: %d\n", error); + return error; + } + + return 0; +} + +/* + * + */ +int pmc_get_rmon(struct bcm63xx_pmc *priv, u32 *v) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_GET_RMON_AND_SIGMA; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *v = rsp.command_response.word3; + return 0; +} + +/* + * + */ +int pmc_write_bpcm_register(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, + u32 word_offset, u32 value) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_WRITE_BPCM_REG; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + cmd.generic_params.params[0] = word_offset >> 2; + cmd.generic_params.params[1] = value; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + return 0; +} +EXPORT_SYMBOL_GPL(pmc_write_bpcm_register); + +/* Perform a value write, then spin until the value shifted by shift + * is seen, masked with mask and is different from cond. + */ +static int pmc_wr_rd_bpcm_mask(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, + u32 word_offset, u32 *val, + u32 shift, u32 mask, u32 cond) +{ + int ret; + int limit = 1000; + u32 dev_addr = pmc_get_dev_addr(priv, addr_id); + + ret = pmc_write_bpcm_register(priv, dev_addr, + word_offset, *val); + if (ret) + return ret; + + do { + ret = pmc_read_bpcm_register(priv, dev_addr, + word_offset, val); + if (ret) + return ret; + + udelay(10); + + if (--limit < 0) { + ret = -ETIMEDOUT; + break; + } + + } while (((*val >> shift) & mask) != cond); + + return ret; +} + +/* + * control cpu reset/power + */ +static int pmc_cpu_power_on(struct bcm63xx_pmc *priv, unsigned int cpu) +{ + u32 ctrl, val; + int ret; + + /* Check if the CPU is already on and save the ARM_CONTROL register + * value since we will use it later for CPU de-assert once done with + * the CPU-specific power sequence + */ + ret = pmc_read_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, &ctrl); + if (ret) + goto out; + + if (ctrl & CPU_RESET_N(cpu)) { + pr_info("CPU%d is already powered on, reset it\n", cpu); + + ctrl &= ~CPU_RESET_N(cpu); + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, ctrl); + mdelay(1); + ctrl |= CPU_RESET_N(cpu); + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, ctrl); + ret = 0; + goto out; + } + + /* Power on CPU */ + ret = pmc_read_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), &val); + if (ret) + goto out; + + val |= (PWR_CPU_MASK << PWR_ON_SHIFT); + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), &val, + PWR_ON_STATUS_SHIFT, + PWR_CPU_MASK, PWR_CPU_MASK); + if (ret) + goto out; + + val |= (PWR_CPU_MASK << PWR_OK_SHIFT); + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), &val, + PWR_OK_STATUS_SHIFT, + PWR_CPU_MASK, PWR_CPU_MASK); + if (ret) + goto out; + + val &= ~CLAMP_ON; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), val); + if (ret) + goto out; + + /* Power on CPU RAM */ + val &= ~(MEM_PDA_MASK << MEM_PDA_SHIFT); + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), val); + if (ret) + goto out; + + val |= MEM_PWR_ON; + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), + &val, + 0, MEM_PWR_ON_STATUS, MEM_PWR_ON_STATUS); + if (ret) + goto out; + + val |= MEM_PWR_OK; + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), + &val, + 0, MEM_PWR_OK_STATUS, MEM_PWR_OK_STATUS); + if (ret) + goto out; + + val &= ~MEM_CLAMP_ON; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), val); + if (ret) + goto out; + + /* De-assert CPU reset */ + ctrl |= CPU_RESET_N(cpu); + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, ctrl); + +out: + return ret; +} + +#if 0 +static int pmc_power_off_zone(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, int zone) +{ + u32 zone_reg; + int err; + + err = pmc_read_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + &zone_reg); + if (err) + return err; + + zone_reg &= ~BPCM_ZONE_PWR_UP_REQ; + zone_reg |= BPCM_ZONE_PWR_DN_REQ; + + err = pmc_write_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + zone_reg); + if (err) + return err; + + return 0; +} +#endif + +static int pmc_power_on_zone(struct bcm63xx_pmc *priv, enum pmc_addr_id addr_id, + int zone) +{ + u32 zone_reg; + int err; + + err = pmc_read_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + &zone_reg); + if (err) + return err; + + zone_reg &= ~BPCM_ZONE_PWR_DN_REQ; + zone_reg |= BPCM_ZONE_PWR_UP_REQ; + zone_reg |= BPCM_ZONE_DPG_CTL_EN; + zone_reg |= BPCM_ZONE_MEM_PWR_CTL_EN; + zone_reg |= BPCM_ZONE_BLK_RESET_ASSERT; + + err = pmc_write_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + zone_reg); + if (err) + return err; + + return 0; +} + +/* + * control StarFighter2 (switch) power + */ +static int pmc_sf2_power_on(struct bcm63xx_pmc *priv) +{ + /* FIXME: SF2 GMII CLOCK HERE ? */ + return pmc_power_on_cmd(priv, PMB_ADDR_SF2); +} + +static int pmc_sf2_power_off(struct bcm63xx_pmc *priv) +{ + return pmc_power_off_cmd(priv, PMB_ADDR_SF2); +} + +/* + * control SAR power + */ +# define PMB_SAR_SR_CONTROL 0x28 +# define PMB_SAR_SR_CONTROL_RESET 0xffffff01 +# define PMB_SAR_SR_CONTROL_UNRESET 0xffffff00 + +static int pmc_sar_soft_reset(struct bcm63xx_pmc *priv) +{ + int ret; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_SAR, + PMB_SAR_SR_CONTROL, + PMB_SAR_SR_CONTROL_RESET); + if (ret) + return ret; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_SAR, + PMB_SAR_SR_CONTROL, + PMB_SAR_SR_CONTROL_UNRESET); + if (ret) + return ret; + + return 0; +} + +static int pmc_sar_power_on(struct bcm63xx_pmc *priv) +{ + int ret; + + ret = pmc_power_on_cmd(priv, PMB_ADDR_SAR); + if (ret) + return ret; + + return pmc_sar_soft_reset(priv); +} + +static int pmc_sar_power_off(struct bcm63xx_pmc *priv) +{ + return pmc_power_off_cmd(priv, PMB_ADDR_SAR); +} + +/* + * control USB host power + */ +static int pmc_usbh_power_on(struct bcm63xx_pmc *priv) +{ + return pmc_power_on_cmd(priv, PMB_ADDR_USB30_2X); +} + +static int pmc_usbh_power_off(struct bcm63xx_pmc *priv) +{ + return pmc_power_off_cmd(priv, PMB_ADDR_USB30_2X); +} + +/* + * control Runner Data Path power + */ +# define RDP_PLL_RESETS 0x10 +# define RDP_PLL_RESET_BIT0 (1 << 0) +# define RDP_PLL_RESET_BIT1 (1 << 1) + +# define RDP_PLL_NDIV 0x1c +# define NDIV_INT_MASK 0x3ff + +# define RDP_PLL_PDIV 0x20 +# define PDIV_MASK 0x7 + +# define RDP_PLL_CH01_CFG 0x2c +# define CH01_MDIV0_MASK 0xff + +# define RDP_PLL_STATUS 0x3c +# define RDP_PLL_STATUS_READY (1 << 31) + +# define PMB_RDP_SR_CONTROL 0x28 +# define PMB_RDP_SR_CONTROL_UNRESET 0xffffffff +# define PMB_RDP_SR_CONTROL_RESET 0x0 + +static int pmc_rdp_pll_init(struct bcm63xx_pmc *priv) +{ + unsigned int tries = 100; + int ret; + u32 reg; + + /* + * powerdown PLLs. + */ + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, 0x0); + if (ret) + return ret; + + /* + * release first stage reset. + */ + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, ®); + if (ret) + return ret; + + reg |= RDP_PLL_RESET_BIT0; + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, reg); + if (ret) + return ret; + + /* + * wait for PLL ready bit. + */ + do { + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_STATUS, + ®); + if (ret) + return ret; + } while (--tries && !(reg & RDP_PLL_STATUS_READY)); + + if (!tries) { + dev_err(priv->dev, "timedout waiting for RDP PLL ready.\n"); + return -ETIMEDOUT; + } + + /* + * release second stage reset. + */ + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, ®); + if (ret) + return ret; + + reg |= RDP_PLL_RESET_BIT1; + + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, reg); + if (ret) + return ret; + + return 0; +} + +static int pmc_rdp_power_on(struct bcm63xx_pmc *priv) +{ + int ret; + + ret = pmc_rdp_pll_init(priv); + if (ret) + return ret; + + /* + * hold RDP into reset + */ + ret = pmc_write_bpcm_register(priv, PMB_ADDR_RDP, + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_RESET); + if (ret) + return ret; + + ret = pmc_power_off_cmd(priv, PMB_ADDR_RDP); + if (ret) + return ret; + + ret = pmc_power_on_cmd(priv, PMB_ADDR_RDP); + if (ret) + return ret; + + /* + * hold RDP into reset + */ + ret = pmc_write_bpcm_register(priv, PMB_ADDR_RDP, + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_UNRESET); + if (ret) + return ret; + + return 0; +} + +static int pmc_rdp_power_off(struct bcm63xx_pmc *priv) +{ + return 0; +} + +/* + * XRDP power control + */ +static const enum pmc_addr_id xrdp_blocks[] = { + PMB_ADDR_XRDP, + PMB_ADDR_XRDP_RC0, + PMB_ADDR_XRDP_RC1, + PMB_ADDR_XRDP_RC2, + PMB_ADDR_XRDP_RC3, + PMB_ADDR_XRDP_RC4, + PMB_ADDR_XRDP_RC5, +}; + +static int pmc_xrdp_power_on(struct bcm63xx_pmc *priv) +{ + size_t i; + int ret; + + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_power_off_cmd(priv, xrdp_blocks[i]); + if (ret) + return ret; + } + + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_power_on_cmd(priv, xrdp_blocks[i]); + if (ret) + return ret; + } + + /* + * hold & release reset + */ + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_write_bpcm_register(priv, xrdp_blocks[i], + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_RESET); + if (ret) + return ret; + } + + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_write_bpcm_register(priv, xrdp_blocks[i], + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_UNRESET); + if (ret) + return ret; + } + + return 0; +} + +static int pmc_xrdp_power_off(struct bcm63xx_pmc *priv) +{ + return 0; +} + +/* + * power on single lane PCI express port. + */ +static int pmc_pcieX_power_on(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id) +{ + int err; + + dev_dbg(priv->dev, "pcie power on address id %d.\n", addr_id); + + err = pmc_power_on_zone(priv, addr_id, 0); + if (err) + return err; + + err = pmc_write_bpcm_register(priv, addr_id, + BPCM_SR_CONTROL_REG, 0x0); + if (err) + return err; + + return 0; +} + +/* + * power on dual lane PCI express port, lanes 0-1 + */ +static int pmc_pcie01_power_on(struct bcm63xx_pmc *priv) +{ + int err; + + dev_dbg(priv->dev, "pcie01 power on.\n"); + + /* + * power on first lane + */ + err = pmc_power_on_zone(priv, PMB_ADDR_PCIE0, 0); + if (err) + return err; + + /* + * power on second lane + */ + err = pmc_power_on_zone(priv, PMB_ADDR_PCIE1, 0); + if (err) + return err; + + /* + * write all 0s in second lane SR control. + */ + err = pmc_write_bpcm_register(priv, PMB_ADDR_PCIE1, + BPCM_SR_CONTROL_REG, 0x0); + if (err) + return err; + + /* + * write 0xff to reset SR control + */ + err = pmc_write_bpcm_register(priv, PMB_ADDR_PCIE0, + BPCM_SR_CONTROL_REG, 0xff); + if (err) + return err; + mdelay(10); + + /* + * bit7: 1 - Strap override for dual lane support + * bit6: Strap value, 0 - dual lane, 1 - single lane + */ + err = pmc_write_bpcm_register(priv, PMB_ADDR_PCIE0, + BPCM_SR_CONTROL_REG, 0x80); + if (err) + return err; + + return 0; +} + +static int pmc_pcieX_power_off(struct bcm63xx_pmc *priv, enum pmc_addr_id osef) +{ + dev_info(priv->dev, "pcie0 power off.\n"); + return -ENOTSUPP; +} +static int pmc_pcie01_power_off(struct bcm63xx_pmc *priv) +{ + dev_info(priv->dev, "pcie01 power off.\n"); + return -ENOTSUPP; +} + +static inline enum pmc_addr_id reset_to_pmc_addr_id(unsigned long reset) +{ + switch (reset) { + case PMC_R_PCIE0: + return PMB_ADDR_PCIE0; + case PMC_R_PCIE1: + return PMB_ADDR_PCIE1; + case PMC_R_PCIE2: + return PMB_ADDR_PCIE2; + case PMC_R_PCIE3: + return PMB_ADDR_PCIE3; + default: + BUG(); + } +} + +/* + * WAN_AE reset + */ +#define PMB_WAN_AE_SR_CONTROL 0x28 +# define PMB_WAN_AE_SR_CTRL_RX_RCLK16_SW_RESET_MASK (1 << 12) +# define PMB_WAN_AE_SR_CTRL_RX_RBC125_SW_RESET_MASK (1 << 13) +# define PMB_WAN_AE_SR_CTRL_RX_TCLK16_SW_RESET_MASK (1 << 14) +# define PMB_WAN_AE_SR_CTRL_RX_CLK125_SW_RESET_MASK (1 << 15) + +static int pmc_wan_ae_soft_reset(struct bcm63xx_pmc *priv) +{ + u32 val; + int ret; + + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_WAN, + BPCM_SR_CONTROL_REG, &val); + if (ret) + return ret; + + val |= PMB_WAN_AE_SR_CTRL_RX_RCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_RBC125_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_TCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_CLK125_SW_RESET_MASK; + + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_WAN, + BPCM_SR_CONTROL_REG, + val); + if (ret) + return ret; + + udelay(5); + + val &= ~(PMB_WAN_AE_SR_CTRL_RX_RCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_RBC125_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_TCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_CLK125_SW_RESET_MASK); + + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_WAN, + BPCM_SR_CONTROL_REG, + val); + if (ret) + return ret; + + return 0; +} + +/* + * reset controller ops + */ +static int pmc_reset_op_action(struct bcm63xx_pmc *priv, + unsigned long idx, + unsigned int action) +{ + switch (idx) { + case PMC_R_CPU1: + if (action == 0) + return pmc_cpu_power_on(priv, 1); + break; + + case PMC_R_RDP: + switch (action) { + case 0: + return pmc_rdp_power_on(priv); + case 1: + return pmc_rdp_power_off(priv); + default: + break; + } + break; + + case PMC_R_XRDP: + switch (action) { + case 0: + return pmc_xrdp_power_on(priv); + case 1: + return pmc_xrdp_power_off(priv); + default: + break; + } + break; + + case PMC_R_SF2: + switch (action) { + case 0: + return pmc_sf2_power_on(priv); + case 1: + return pmc_sf2_power_off(priv); + default: + break; + } + break; + + case PMC_R_SAR: + switch (action) { + case 0: + return pmc_sar_power_on(priv); + case 1: + return pmc_sar_power_off(priv); + case 2: + return pmc_sar_soft_reset(priv); + default: + break; + } + break; + + case PMC_R_USBH: + switch (action) { + case 0: + return pmc_usbh_power_on(priv); + case 1: + return pmc_usbh_power_off(priv); + default: + break; + } + break; + + case PMC_R_PCIE0: + case PMC_R_PCIE1: + case PMC_R_PCIE2: + case PMC_R_PCIE3: + switch (action) { + case 0: + return pmc_pcieX_power_on(priv, + reset_to_pmc_addr_id(idx)); + case 1: + return pmc_pcieX_power_off(priv, + reset_to_pmc_addr_id(idx)); + } + break; + + case PMC_R_PCIE01: + switch (action) { + case 0: + return pmc_pcie01_power_on(priv); + case 1: + return pmc_pcie01_power_off(priv); + } + break; + + case PMC_R_WAN_AE: + switch (action) { + case 2: + return pmc_wan_ae_soft_reset(priv); + default: + break; + } + break; + + default: + dev_err(priv->dev, "unknown reset idx %lu", idx); + return -ENODEV; + } + + dev_err(priv->dev, "unhandled action %u for id %lu", action, idx); + return -ENOTSUPP; +} + +static int pmc_assert_op_callback(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + return pmc_reset_op_action(to_pmc_reset_priv(rcdev), idx, 1); +} + +static int pmc_deassert_op_callback(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + return pmc_reset_op_action(to_pmc_reset_priv(rcdev), idx, 0); +} + +static int pmc_reset_op_callback(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + return pmc_reset_op_action(to_pmc_reset_priv(rcdev), idx, 2); +} + +static const struct reset_control_ops pmc_reset_controller_ops = { + .assert = pmc_assert_op_callback, + .deassert = pmc_deassert_op_callback, + .reset = pmc_reset_op_callback, +}; + +/* + * hwmon info + */ +static int pmc_get_pvt(struct bcm63xx_pmc *priv, + unsigned int island, + unsigned int sel, + unsigned int *value) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_GET_PVT; + cmd.word1.dev_addr = 0; + cmd.word1.zone_idx = 0; + cmd.word1.island = island; + cmd.generic_params.params[0] = sel; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *value = rsp.command_response.word2; + return 0; +} + +static ssize_t pmc_revision_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int revision, change; + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_REVISION; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + change = rsp.command_response.word2; + revision = rsp.command_response.word3; + + return snprintf(buf, PAGE_SIZE, "%x-%d\n", revision, change); +} + +static SENSOR_DEVICE_ATTR(revision, 0444, pmc_revision_show, NULL, 0); + +static ssize_t pmc_thermal_show_temp(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int value, temp; + int error; + + error = pmc_get_pvt(priv, 0, 0, &value); + if (error) + return error; + + temp = (41004000 - 48705 * value) / 100; + return snprintf(buf, PAGE_SIZE, "%u\n", temp); +} + +static SENSOR_DEVICE_ATTR(temp1_input, 0444, pmc_thermal_show_temp, + NULL, 0); + +static ssize_t pmc_thermal_show_in(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int value, in, reg, island; + int sel = to_sensor_dev_attr(attr)->index; + int divider; + int error; + + island = (sel >> 8) & 0xff; + reg = sel & 0xff; + + error = pmc_get_pvt(priv, island, reg, &value); + if (error) + return error; + + switch (reg) { + case 1: + case 2: + divider = 10; + break; + case 3: + case 4: + divider = 7; + break; + case 5: + divider = 4; + break; + case 6: + divider = 2; + break; + default: + divider = 1; + break; + } + + in = (8800 * value) / (divider * 1024); + return snprintf(buf, PAGE_SIZE, "%u\n", in); +} + +/* V0.85_0 */ +static SENSOR_DEVICE_ATTR(in1_input, 0444, pmc_thermal_show_in, NULL, 0x0001); + +/* V0.85_1 */ +static SENSOR_DEVICE_ATTR(in2_input, 0444, pmc_thermal_show_in, NULL, 0x0002); + +/* Vin */ +static SENSOR_DEVICE_ATTR(in3_input, 0444, pmc_thermal_show_in, NULL, 0x0003); + +/* V1.0 */ +static SENSOR_DEVICE_ATTR(in4_input, 0444, pmc_thermal_show_in, NULL, 0x0004); + +/* V1.8 */ +static SENSOR_DEVICE_ATTR(in5_input, 0444, pmc_thermal_show_in, NULL, 0x0005); + +/* V3.3 */ +static SENSOR_DEVICE_ATTR(in6_input, 0444, pmc_thermal_show_in, NULL, 0x0006); + +/* Vin */ +static SENSOR_DEVICE_ATTR(in9_input, 0444, pmc_thermal_show_in, NULL, 0x0103); + +/* + * AFE PLL + */ +static ssize_t pmc_show_afepll(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int offset = to_sensor_dev_attr(attr)->index; + int ret; + u32 val; + + ret = pmc_read_bpcm_register(priv, PMB_ADDR_AFEPLL, offset, &val); + if (ret) + return ret; + + return snprintf(buf, PAGE_SIZE, "0x%x\n", val); +} + +/* vdsl pll */ +static SENSOR_DEVICE_ATTR(afepll_rosc_control_input, + 0444, pmc_show_afepll, NULL, 0x10); + +static SENSOR_DEVICE_ATTR(afepll_rosc_count_input, + 0444, pmc_show_afepll, NULL, 0x1c); + +static SENSOR_DEVICE_ATTR(afepll_sr_control_input, + 0444, pmc_show_afepll, NULL, 0x28); + +static struct attribute *pmc_hwmon_attrs[] = { + &sensor_dev_attr_revision.dev_attr.attr, + + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_in1_input.dev_attr.attr, + &sensor_dev_attr_in2_input.dev_attr.attr, + &sensor_dev_attr_in3_input.dev_attr.attr, + &sensor_dev_attr_in4_input.dev_attr.attr, + &sensor_dev_attr_in5_input.dev_attr.attr, + &sensor_dev_attr_in6_input.dev_attr.attr, + &sensor_dev_attr_in9_input.dev_attr.attr, + + &sensor_dev_attr_afepll_rosc_control_input.dev_attr.attr, + &sensor_dev_attr_afepll_rosc_count_input.dev_attr.attr, + &sensor_dev_attr_afepll_sr_control_input.dev_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(pmc_hwmon); + + +/* + * called by SMP ops early in the boot process + */ +int bcm63xx_pmc_cpu_power_on(unsigned int cpu) +{ + /* make sure early init has been called */ + if (WARN_ON(!pmc->base)) + return -ENODEV; + + if (WARN_ON(cpu > 1)) + return -ENODEV; + + return pmc_cpu_power_on(pmc, cpu); +} + +/* + * load PMC firmware overlay if needed + * + * called with PMC lock held + */ +static int __pmc_init(struct bcm63xx_pmc *pmc) +{ + return 0; +} + +static int bcm63xx_pmc_probe(struct platform_device *pdev) +{ + struct reset_controller_dev *rcdev; + struct resource *res; + struct device *hwmon_dev; + void __iomem *base; + int ret; + + /* + * Early initialisation should have configured an initial + * register mapping and setup the soc data pointer. If these + * are not valid then something went badly wrong! + */ + if (WARN_ON(!pmc->base)) + return -ENODEV; + + /* take over the memory region from the early initialization */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pmc->dev = &pdev->dev; + + /* switch to newly reserved base address & init PMC */ + mutex_lock(&pmc->pmc_lock); + iounmap(pmc->base); + pmc->base = base; + + ret = __pmc_init(pmc); + if (ret) { + iounmap(pmc->base); + pmc->base = NULL; + mutex_unlock(&pmc->pmc_lock); + return ret; + } + mutex_unlock(&pmc->pmc_lock); + + /* register as reset controller */ + rcdev = &pmc->rcdev; + rcdev->ops = &pmc_reset_controller_ops; + rcdev->of_node = pdev->dev.of_node; + rcdev->of_reset_n_cells = 1; + rcdev->nr_resets = PMC_R_LAST; + + ret = devm_reset_controller_register(&pdev->dev, rcdev); + if (ret) { + pr_err("failed to register reset controller: %d", ret); + return ret; + } + + /* register as hwmon */ + if (IS_ENABLED(CONFIG_HWMON)) { + hwmon_dev = + devm_hwmon_device_register_with_groups(&pdev->dev, "pmc", + pmc, + pmc_hwmon_groups); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + } + + pmc_create_debugfs(pmc); + + pmc->init_done = true; + return 0; +} + +static const struct of_device_id bcm63xx_pmc_match[] = { + { .compatible = "brcm,bcm63138-pmc", .data = (void *)0x63138 }, + { .compatible = "brcm,bcm63158-pmc", .data = (void *)0x63158 }, + { } +}; + +static struct platform_driver bcm63xx_pmc_driver = { + .driver = { + .name = "bcm63xx-pmc", + .suppress_bind_attrs = true, + .of_match_table = bcm63xx_pmc_match, + }, + .probe = bcm63xx_pmc_probe, +}; + +builtin_platform_driver(bcm63xx_pmc_driver); + +/* + * fetch PMC firmware revision and check that it matches SOC id + */ +static int pmc_check_revision(struct bcm63xx_pmc *priv) +{ + struct pmc_command cmd, rsp; + int ret; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_REVISION; + cmd.word1.dev_addr = 0; + + ret = pmc_send_command(priv, &cmd, &rsp); + if (ret) { + pr_err("failed to retrieve PMC revision\n"); + return ret; + } + + if (rsp.command_response.word2 != priv->soc_id) { + pr_err("PMC revision mismatch (0x%08x != 0x%08x)\n", + rsp.command_response.word2, priv->soc_id); + return -ENODEV; + } + + pr_debug("PMC firmware revision: 0x%08x", rsp.command_response.word3); + return 0; +} + +/* + * additionnal code to load into PMC + */ +#define PMC_IMAGE_ALIGN (1 << 13) + +static const __attribute__((aligned(PMC_IMAGE_ALIGN))) u8 pmc_63138_image[] = { + 0x27, 0xbd, 0xff, 0x10, 0x8f, 0x82, 0x06, 0x00, 0xaf, 0xb1, 0x00, 0xcc, + 0xaf, 0xb0, 0x00, 0xc8, 0x00, 0xa0, 0x88, 0x21, 0xaf, 0xbf, 0x00, 0xec, + 0xaf, 0xbe, 0x00, 0xe8, 0xaf, 0xb7, 0x00, 0xe4, 0xaf, 0xb6, 0x00, 0xe0, + 0xaf, 0xb5, 0x00, 0xdc, 0xaf, 0xb4, 0x00, 0xd8, 0xaf, 0xb3, 0x00, 0xd4, + 0xaf, 0xb2, 0x00, 0xd0, 0x00, 0x80, 0x80, 0x21, 0x00, 0x40, 0xf8, 0x09, + 0x00, 0xa0, 0x20, 0x21, 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0x00, 0x70, 0x18, 0x21, 0x00, 0xc3, 0x10, 0x2a, + 0x00, 0x62, 0x30, 0x0b, 0x3c, 0x02, 0x80, 0x00, 0x02, 0x62, 0x50, 0x21, + 0x24, 0x02, 0x22, 0x60, 0x70, 0xc2, 0x10, 0x02, 0x24, 0x03, 0x1c, 0x00, + 0x00, 0x43, 0x00, 0x1a, 0x8f, 0x90, 0x01, 0x88, 0x00, 0x0a, 0x50, 0x40, + 0x02, 0x0a, 0x50, 0x21, 0x00, 0x00, 0x10, 0x12, 0x14, 0xc0, 0x00, 0x08, + 0xa5, 0x42, 0x00, 0x20, 0x0f, 0xf0, 0x41, 0xb8, 0x3c, 0x04, 0x80, 0x08, + 0x8e, 0x02, 0x00, 0x48, 0x00, 0x40, 0xf8, 0x09, 0x00, 0x00, 0x00, 0x00, + 0x0b, 0xf0, 0x43, 0xe2, 0x8f, 0xbf, 0x00, 0x54, 0x8f, 0xa4, 0x00, 0x20, + 0x8f, 0xa5, 0x00, 0x24, 0x24, 0x07, 0x03, 0xe8, 0x00, 0x85, 0x00, 0x1a, + 0x00, 0x00, 0x10, 0x12, 0x70, 0x46, 0x18, 0x02, 0x00, 0x67, 0x00, 0x1a, + 0x8f, 0xa3, 0x00, 0x28, 0x00, 0x00, 0x38, 0x12, 0x70, 0x43, 0x10, 0x02, + 0x24, 0x03, 0xfc, 0x18, 0x00, 0x43, 0x00, 0x1a, 0x00, 0x00, 0x10, 0x12, + 0x02, 0x42, 0x10, 0x21, 0x00, 0xe2, 0x10, 0x21, 0x00, 0xc2, 0x38, 0x21, + 0x28, 0xe2, 0x02, 0xd4, 0x14, 0x40, 0x00, 0x05, 0x24, 0x13, 0x02, 0xd4, + 0x24, 0x03, 0x03, 0x3e, 0x28, 0xe6, 0x03, 0x3f, 0x00, 0x60, 0x98, 0x21, + 0x00, 0xe6, 0x98, 0x0b, 0x3c, 0x04, 0x00, 0x12, 0x0f, 0xf0, 0x41, 0xb8, + 0x02, 0x64, 0x20, 0x25, 0x03, 0xd1, 0x10, 0x23, 0x24, 0x03, 0x27, 0x10, + 0x70, 0x43, 0x10, 0x02, 0x02, 0x77, 0x30, 0x23, 0x00, 0x54, 0x00, 0x1a, + 0x00, 0x00, 0x40, 0x12, 0x70, 0xc8, 0xb8, 0x02, 0x02, 0xe3, 0x00, 0x1a, + 0x00, 0x00, 0xb8, 0x12, 0x02, 0xfe, 0xb8, 0x21, 0x03, 0xd7, 0x10, 0x2b, + 0x02, 0xe2, 0xf0, 0x0b, 0x26, 0xe2, 0x00, 0x20, 0x00, 0x51, 0x18, 0x2b, + 0x00, 0x43, 0x88, 0x0b, 0x24, 0x02, 0x00, 0x02, 0x16, 0xc2, 0xff, 0x56, + 0x24, 0x13, 0x00, 0x01, 0x3c, 0x04, 0x00, 0x08, 0x0f, 0xf0, 0x41, 0xb8, + 0x24, 0x84, 0x00, 0x06, 0x0f, 0xf0, 0x41, 0xea, 0x02, 0xe0, 0x20, 0x21, + 0x8f, 0xa3, 0x00, 0x5c, 0x26, 0x05, 0x00, 0x18, 0xa6, 0x03, 0x00, 0x26, + 0x26, 0x04, 0x00, 0x10, 0x0f, 0xf0, 0x42, 0x78, 0xa6, 0x15, 0x00, 0x24, + 0x3c, 0x02, 0xb6, 0x08, 0x94, 0x44, 0x01, 0x16, 0x30, 0x84, 0xff, 0xff, + 0x0f, 0xf0, 0x41, 0xea, 0x24, 0x84, 0x00, 0x10, 0x8f, 0x85, 0x01, 0x88, + 0x24, 0xa4, 0x00, 0x14, 0x0f, 0xf0, 0x42, 0x78, 0x24, 0xa5, 0x00, 0x1c, + 0x8f, 0xbf, 0x00, 0x54, 0x8f, 0xbe, 0x00, 0x50, 0x8f, 0xb7, 0x00, 0x4c, + 0x8f, 0xb6, 0x00, 0x48, 0x8f, 0xb5, 0x00, 0x44, 0x8f, 0xb4, 0x00, 0x40, + 0x8f, 0xb3, 0x00, 0x3c, 0x8f, 0xb2, 0x00, 0x38, 0x8f, 0xb1, 0x00, 0x34, + 0x8f, 0xb0, 0x00, 0x30, 0x03, 0xe0, 0x00, 0x08, 0x27, 0xbd, 0x00, 0x58, + 0x00, 0x80, 0x10, 0x21, 0x8c, 0x45, 0x00, 0x0c, 0x0b, 0xf0, 0x42, 0xf5, + 0x8c, 0x84, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static int __init pmc_load_plugin_bcm63138(struct bcm63xx_pmc *pmc, u32 state) +{ + unsigned long image_link_addr = 0x9fc10000; + const void *image_virt_addr = pmc_63138_image; + struct pmc_command cmd, rsp; + int ret; + + if (state != PMC_RSTATE_AVS_COMPLETE_WAITING_FOR_IMAGE) { + WARN(1, "expected AVS_COMPLETE_WAITING_FOR_IMAGE state"); + return 0; + } + + writel(~(PMC_IMAGE_ALIGN - 1), + pmc->base + PMC_ADDR2_WIN_MASK_REG); + writel(image_link_addr & 0x1fffffff, + pmc->base + PMC_ADDR2_WIN_BASEIN_REG); + writel(virt_to_phys(image_virt_addr), + pmc->base + PMC_ADDR2_WIN_BASEOUT_REG); + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_REGISTER_CMD_HANDLER; + cmd.generic_params.params[0] = 96; + cmd.generic_params.params[1] = image_link_addr; + + ret = pmc_send_command(pmc, &cmd, &rsp); + if (ret) { + pr_err("failed to register command handler\n"); + return ret; + } + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = 96; + cmd.generic_params.params[0] = 75; + cmd.generic_params.params[1] = 75; + + ret = pmc_send_command(pmc, &cmd, &rsp); + if (ret) { + pr_err("failed to send cmd 96\n"); + return ret; + } + + return 0; +} + +static const char *pmc_run_state_str[] = { + [PMC_RSTATE_EXECUTING_BOOTROM] = "EXECUTING_BOOTROM", + [PMC_RSTATE_WAITING_BMU_COMPLETE] = "WAITING_BMU_COMPLETE", + [PMC_RSTATE_AVS_COMPLETE_WAITING_FOR_IMAGE] = + "AVS_COMPLETE_WAITING_FOR_IMAGE", + [PMC_RSTATE_AUTHENTICATING_IMAGE] = "AUTHENTICATING_IMAGE", + [PMC_RSTATE_AUTHENTICATION_FAILED] = "AUTHENTICATION_FAILED", + [PMC_RSTATE_RESERVED] = "RESERVED", + [PMC_RSTATE_FATAL_ERROR] = "FATAL_ERROR", + [PMC_RSTATE_RUNNING] = "RUNNING", +}; + +static int __init pmc_load_plugin(struct bcm63xx_pmc *pmc) +{ + u32 val; + + val = readl(pmc->base + PMC_HOST_MBOX_IN_REG); + val = (val >> 24) & 0x7; + pr_info("PMC state is '%s'\n", pmc_run_state_str[val]); + + switch (pmc->soc_id) { + case 0x63138: + return pmc_load_plugin_bcm63138(pmc, val); + case 0x63158: + return 0; + default: + WARN(1, "no load plugin defined"); + return 0; + } +} + +static int pmc_avs_state_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + int error; + bool state; + + error = pmc_get_avs_state(pmc, 0, &state); + if (error) + return error; + + *val = state ? 1 : 0; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_avs_state_fops, + pmc_avs_state_read, + NULL, "%llu\n"); + +static int pmc_pred_voltage_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + int error; + u32 v; + + error = pmc_get_rmon(pmc, &v); + if (error) + return error; + + *val = (v >> 16) & 0xffff; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_pred_voltage_fops, + pmc_pred_voltage_read, + NULL, "%lld\n"); + +static int pmc_avs_margin_ss_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + + *val = pmc->avs_margin_ss; + return 0; +} + +static int pmc_avs_margin_ss_write(void *priv, u64 val) +{ + struct bcm63xx_pmc *pmc = priv; + + if (val > 0xff) + return -EINVAL; + + pmc->avs_margin_ss = val; + + if (pmc->avs_margin_ff && pmc->avs_margin_ss) + return pmc_close_avs(pmc); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_avs_margin_ss_fops, + pmc_avs_margin_ss_read, + pmc_avs_margin_ss_write, + "%lld\n"); + +static int pmc_avs_margin_ff_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + + *val = pmc->avs_margin_ff; + return 0; +} + +static int pmc_avs_margin_ff_write(void *priv, u64 val) +{ + struct bcm63xx_pmc *pmc = priv; + + if (val > 0xff) + return -EINVAL; + + pmc->avs_margin_ff = val; + + if (pmc->avs_margin_ff && pmc->avs_margin_ss) + return pmc_close_avs(pmc); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_avs_margin_ff_fops, + pmc_avs_margin_ff_read, + pmc_avs_margin_ff_write, + "%lld\n"); + +static int __init pmc_create_debugfs(struct bcm63xx_pmc *pmc) +{ + pmc->debugfs_dir = debugfs_create_dir("bcm63xx-pmc", NULL); + if (IS_ERR(pmc->debugfs_dir)) { + dev_warn(pmc->dev, "unable to create debugfs directory"); + pmc->debugfs_dir = NULL; + return 0; + } + + debugfs_create_file("avs-state", S_IRUSR, pmc->debugfs_dir, + pmc, &pmc_avs_state_fops); + debugfs_create_file("avs-pred-voltage", S_IRUSR, pmc->debugfs_dir, + pmc, &pmc_pred_voltage_fops); + debugfs_create_file("avs-margin-ss", S_IRUSR | S_IWUSR, + pmc->debugfs_dir, pmc, &pmc_avs_margin_ss_fops); + debugfs_create_file("avs-margin-ff", S_IRUSR | S_IWUSR, + pmc->debugfs_dir, pmc, &pmc_avs_margin_ff_fops); + return 0; +} + +/* + * Early initialization to allow access to registers in the very early boot + * process (mostly for SMP bootup) + */ +static int __init bcm63xx_pmc_early_init(void) +{ + const struct of_device_id *match; + struct device_node *np; + struct resource regs; + int ret; + bool avs_state; + + np = of_find_matching_node_and_match(NULL, bcm63xx_pmc_match, &match); + if (!np) { + pr_warn("DT node not found, PMC disabled\n"); + return 0; + } + + if (of_address_to_resource(np, 0, ®s) < 0) { + pr_err("failed to get PMC registers\n"); + of_node_put(np); + return -ENXIO; + } + + of_node_put(np); + + mutex_init(&pmc->pmc_lock); + pmc->soc_id = (u32)(uintptr_t)match->data; + pmc->base = ioremap(regs.start, resource_size(®s)); + if (!pmc->base) { + pr_err("failed to map PMC registers\n"); + return -ENXIO; + } + + pmc_load_plugin(pmc); + ret = pmc_check_revision(pmc); + if (ret) + goto fail; + + ret = pmc_get_avs_state(pmc, 0, &avs_state); + if (ret) + pr_err("PMC: unable to get AVS state.\n"); + else + pr_info("PMC: AVS state is %sabled\n", + avs_state ? "en" : "dis"); + + return 0; + +fail: + pr_err("PMC init failed"); + iounmap(pmc->base); + pmc->base = NULL; + return ret; +} + +early_initcall(bcm63xx_pmc_early_init); + + +/* + * special wrappers for bcm_adsl + */ +static enum pmc_addr_id pmc_find_dev_addr_id(struct bcm63xx_pmc *priv, + unsigned int dev_addr) +{ + const struct pmc_addr_info *info; + size_t i; + + switch (priv->soc_id) { + case 0x63138: + info = bcm63138_pmc_addr_info; + break; + case 0x63158: + info = bcm63158_pmc_addr_info; + break; + default: + WARN(1, "missing addr info for this soc id"); + return 0; + } + + for (i = 0; i < PMB_ADDR_LAST; i++) { + unsigned int addr; + + if (!info[i].valid) + continue; + + addr = (info[i].dev | (info[i].bus_id << PMB_BUS_ID_SHIFT)); + if (addr == dev_addr) + return i; + } + + printk("cannot find dev addr id for dev_addr:0x%x\n", dev_addr); + BUG(); +} + +int PowerOnDevice(int devAddr) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + return pmc_power_on_cmd(pmc, id); +} +EXPORT_SYMBOL(PowerOnDevice); + +int PowerOffDevice(int devAddr) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + return pmc_power_off_cmd(pmc, id); +} +EXPORT_SYMBOL(PowerOffDevice); + +int ReadBPCMRegister(int devAddr, int wordOffset, u32 *value) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + int ret; + + ret = pmc_read_bpcm_register(pmc, id, wordOffset << 2, value); + return ret; +} + +EXPORT_SYMBOL(ReadBPCMRegister); + +int WriteBPCMRegister(int devAddr, int wordOffset, u32 value) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + return pmc_write_bpcm_register(pmc, id, wordOffset << 2, value); +} + +EXPORT_SYMBOL(WriteBPCMRegister); + +struct bcm63xx_pmc *pmc_of_get(struct device_node *np) +{ + return pmc->init_done ? pmc : ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL_GPL(pmc_of_get); --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/procmon-bcm63158.c 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,171 @@ +/* + * procmon-bcm63158.c for procmon-bcm63158 + * Created by on Thu Oct 3 19:14:44 2019 + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct bcm63158_procmon_priv { + void __iomem *regs; + struct device *dev; + struct list_head list; +}; + + +static DEFINE_MUTEX(procmon_list_mutex); +static LIST_HEAD(procmon_list); + +static int bcm63158_procmon_probe(struct platform_device *pdev) +{ + struct bcm63158_procmon_priv *priv; + + dev_info(&pdev->dev, "probe.\n"); + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, priv); + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (!priv->regs) + return -ENOMEM; + + mutex_lock(&procmon_list_mutex); + list_add_tail(&priv->list, &procmon_list); + mutex_unlock(&procmon_list_mutex); + + return 0; +} + +static const struct of_device_id bcm63158_procmon_match[] = { + { .compatible = "brcm,bcm63158-procmon" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63158_procmon_of_match); + +struct platform_driver bcm63158_procmon_driver = { + .probe = bcm63158_procmon_probe, + .remove = NULL, /* FIXME*/ + .driver = { + .name = "bcm63158-procmon", + .owner = THIS_MODULE, + .of_match_table = bcm63158_procmon_match, + }, +}; +builtin_platform_driver(bcm63158_procmon_driver); + +#define PROCMON_MISC_REG(i) (0x50 + (i) * 4) + +#define PROCMON_EXT_REG (0x50 + 0xc) +# define EXT_REG_RMON_SATURATED_VALUE 0x3a0 +# define EXT_REG_RMON_VALUE_MASK 0xffff +# define EXT_REG_RMON_VALID (1 << 16) + +/* + * this is the meaty part of this driver. calculation method comes + * directly from broadcom refsw. + */ +int bcm63158_procmon_calc_rcal(struct bcm63158_procmon_priv *priv, + int resistor) +{ + u32 res_int, res_ext; + u32 ext_reg; + int ratio, ratio1, ret; + + dev_dbg(priv->dev, "getting rcal setting for resistor %d", resistor); + + /* + * make sure the resistor selection is valid + */ + if (resistor < RCAL_0P25UM_HORZ || resistor > RCAL_1UM_VERT) + return -EINVAL; + + ext_reg = readl(priv->regs + PROCMON_EXT_REG); + if ((ext_reg & EXT_REG_RMON_VALID) == 0) { + dev_err(priv->dev, "resistor data is not collected by the " + "PMC.\n"); + return -EIO; + } + + if ((ext_reg & EXT_REG_RMON_VALUE_MASK) > + EXT_REG_RMON_SATURATED_VALUE) { + dev_err(priv->dev, "ext reg is saturated.\n"); + return -EIO; + } + + res_ext = ext_reg & EXT_REG_RMON_VALUE_MASK; + res_int = readl(priv->regs + PROCMON_MISC_REG(resistor >> 1)); + if (resistor & 1) + res_int >>= 16; + + /* + * Ratio = CLAMP((INT) (128.0 * V(REXT)/V(RINT)), 0, 255) + */ + ratio = (128 * res_ext) / res_int; + if (ratio > 255) + ratio = 255; + + /* + * Ratio1 = CLAMP(128 - (Ratio - 128) * 4, 0, 255) + */ + ratio1 = 128 - (ratio - 128) * 4; + if (ratio1 < 0) + ratio1 = 0; + if (ratio1 > 255) + ratio1 = 255; + + /* + * convert to 4 bit rcal setting value + */ + ret = (ratio1 >> 4) & 0xf; + + dev_dbg(priv->dev, "getrcal for resistor%d, int %d, ext %d, " + "ratio %d ratio1 %d, rcal %d\n", + resistor, res_int, res_ext, ratio, ratio1, ret); + + return ret; +} + +int procmon_get_rcal(struct device_node *np) +{ + int err; + struct of_phandle_args args; + struct bcm63158_procmon_priv *priv; + + err = of_parse_phandle_with_args(np, "procmon", "#procmon-cells", + 0, &args); + if (err) { + printk("unable to parse procmon phandle.\n"); + return err; + } + + if (args.args_count != 1) + return -EINVAL; + + mutex_lock(&procmon_list_mutex); + list_for_each_entry (priv, &procmon_list, list) { + if (priv->dev->of_node == args.np) { + mutex_unlock(&procmon_list_mutex); + goto found; + } + } + mutex_unlock(&procmon_list_mutex); + return -EPROBE_DEFER; + +found: + return bcm63158_procmon_calc_rcal(priv, args.args[0]); +} +EXPORT_SYMBOL(procmon_get_rcal); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63158 SoC PROCMON driver."); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/rdp./Makefile linux-6.4-fbx/drivers/soc/bcm/bcm63xx/rdp/Makefile --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/rdp./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/rdp/Makefile 2023-03-09 15:06:11.376234546 +0100 @@ -0,0 +1,9 @@ +obj-y += rdp_drv.o + +rdp_drv-y += \ + rdp.o \ + rdp_api.o \ + rdp_io.o \ + rdp_ioctl.o + +rdp_drv-$(CONFIG_DEBUG_FS) += rdp_debug.o --- /dev/null 2024-03-28 18:35:30.816070989 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/ubus4-bcm63158.c 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,875 @@ +/* + * ubus4-bcm63158.c for bcm63158-soc + * Created by on Fri Jun 7 14:30:40 2019 + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * UBUS coherency port configuration registes. + */ +#define UBUS_COHERENCY_LUT(x) (0x00 + 4 * (x)) +#define UBUS_COHERENCY_QUEUE_DEPTH(x) (0x80 + 4 * (x)) +#define UBUS_COHERENCY_CBS_THRESH(x) (0x90 + 4 * (x)) +#define UBUS_COHERENCY_CIR_INCR(x) (0xb0 + 4 * (x)) +#define UBUS_COHERENCY_REF_CNT(x) (0xc0 + 4 * (x)) +#define UBUS_COHERENCY_MAX_BONUS(x) (0xd0 + 4 * (x)) + +static inline void get_lut_queue_id_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 8; + *shift = (id % 8) * 4; + *mask = 0xf; +} + +static inline void get_queue_depth_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 4; + *shift = (id % 4) * 8; + *mask = 0xff; +} + +static inline void get_cbs_thresh_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 2; + *shift = (id % 2) * 16; + *mask = 0xffff; +} + +static inline void get_cir_incr_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 4; + *shift = (id % 4) * 8; + *mask = 0xff; +} + +static inline void get_ref_cnt_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 4; + *shift = (id % 4) * 8; + *mask = 0xff; +} + +static inline void get_max_bonus_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 8; + *shift = (id % 8) * 4; + *mask = 0x7; +} + +#define UBUS_LUT_COUNT 32 +#define UBUS_QUEUE_DEPTH_COUNT 4 +#define UBUS_CBS_THRESH_COUNT 8 +#define UBUS_CIR_INCR_COUNT 4 +#define UBUS_REF_CNT_COUNT 4 +#define UBUS_MAX_BONUS_COUNT 2 + + +#define UBUS_COHERENCY_WLU_SCRPID(x) (0xd8 + 4 * (x)) +/* + * ubus masters bas addresses + */ +#define UBUS_PORT_PCIE0_OFFSET 0x00C000 +#define UBUS_PORT_DSLCPU_OFFSET 0x01C000 +#define UBUS_PORT_B53_OFFSET 0x020000 +#define UBUS_PORT_PMC_OFFSET 0x02C000 +#define UBUS_PORT_PER_OFFSET 0x034000 +#define UBUS_PORT_PER_DMA_OFFSET 0x03C000 +#define UBUS_PORT_SWH_OFFSET 0x048000 +#define UBUS_PORT_SPU_OFFSET 0x050000 +#define UBUS_PORT_DSL_OFFSET 0x05C000 +#define UBUS_PORT_PCIE2_OFFSET 0x064000 +#define UBUS_PORT_PCIE3_OFFSET 0x06C000 +#define UBUS_PORT_USB_OFFSET 0x074000 +#define UBUS_PORT_DMA0_OFFSET 0x47C000 +#define UBUS_PORT_DMA1_OFFSET 0x480000 +#define UBUS_PORT_RQ0_OFFSET 0x498000 +#define UBUS_PORT_NATC_OFFSET 0x4B8000 +#define UBUS_PORT_DQM_OFFSET 0x4BC000 +#define UBUS_PORT_QM_OFFSET 0x4C4000 + + +static DEFINE_MUTEX(ubus_list_mutex); +static LIST_HEAD(ubus_list); + +struct ubus_credit { + u32 port_id; + u32 credit; +}; + +struct ubus_master_desc { + unsigned long regs_offset; + u32 port_id; + struct ubus_credit *credits; +}; + +#define UBUS_MASTER_DESC(_reg_offset, _port_id, ...) \ + { \ + .regs_offset = _reg_offset, \ + .port_id = _port_id, \ + .credits = (struct ubus_credit[]){ \ + __VA_ARGS__, { } }, \ + } + +#define UBUS_CREDIT(_port_id, _credit) \ + { .port_id = _port_id, .credit = _credit } + +/* + * locations of each masters control registers, and SoC specific + * credits tables. + */ +struct ubus_master_desc bcm63158_masters[] = { + UBUS_MASTER_DESC(UBUS_PORT_B53_OFFSET, UBUS_PORT_ID_BIU, + UBUS_CREDIT(UBUS_PORT_ID_MEMC, 3), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PER_OFFSET, UBUS_PORT_ID_PER, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1)), + UBUS_MASTER_DESC(UBUS_PORT_USB_OFFSET, UBUS_PORT_ID_USB, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 2), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1)), + UBUS_MASTER_DESC(UBUS_PORT_SPU_OFFSET, UBUS_PORT_ID_SPU, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 5), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 4), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8)), + UBUS_MASTER_DESC(UBUS_PORT_DSL_OFFSET, UBUS_PORT_ID_DSL, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PER_DMA_OFFSET, UBUS_PORT_ID_PERDMA, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 5), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 4), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8)), + UBUS_MASTER_DESC(UBUS_PORT_PCIE0_OFFSET, UBUS_PORT_ID_PCIE0, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 4), + UBUS_CREDIT(UBUS_PORT_ID_PCIE0, 1), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PCIE2_OFFSET, UBUS_PORT_ID_PCIE2, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 3), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PCIE3_OFFSET, UBUS_PORT_ID_PCIE3, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 6), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1)), + UBUS_MASTER_DESC(UBUS_PORT_DSLCPU_OFFSET, UBUS_PORT_ID_DSLCPU, + UBUS_CREDIT(UBUS_PORT_ID_MEMC, 8), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PMC_OFFSET, UBUS_PORT_ID_PMC, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_MEMC, 1), + UBUS_CREDIT(UBUS_PORT_ID_USB, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE0, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE3, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE2, 1), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_PMC, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_SWH, 1), + UBUS_CREDIT(UBUS_PORT_ID_SPU, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 1), + UBUS_CREDIT(UBUS_PORT_ID_QM, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_SWH_OFFSET, UBUS_PORT_ID_SWH, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 8), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 8), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8)), + UBUS_MASTER_DESC(UBUS_PORT_QM_OFFSET, UBUS_PORT_ID_QM, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 16), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_DQM_OFFSET, UBUS_PORT_ID_DQM, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 2), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_DMA0_OFFSET, UBUS_PORT_ID_DMA0, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 8), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_NATC_OFFSET, UBUS_PORT_ID_NATC, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 2), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_RQ0_OFFSET, UBUS_PORT_ID_RQ0, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 11), + UBUS_CREDIT(UBUS_PORT_ID_USB, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE0, 2), + UBUS_CREDIT(UBUS_PORT_ID_PCIE3, 2), + UBUS_CREDIT(UBUS_PORT_ID_PCIE2, 2), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SWH, 1), + UBUS_CREDIT(UBUS_PORT_ID_SPU, 1), + UBUS_CREDIT(UBUS_PORT_ID_QM, 10), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 2), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 2), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 10), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), +}; + +struct biu_config { + const char *blk_name; + u32 mstr_node; + u32 src_pid; + u32 queue_id; + u32 depth; + u32 ref_cnt[4]; + u32 cir; + u32 cbs; + u32 bonus; + +}; + +enum { + E_DDR_2133_x32, + E_DDR_2133_x16, + E_DDR_1600_x32, + E_DDR_1600_x16, +}; + +#define DDR_SPEED_800_10_10_10 6 +#define DDR_SPEED_800_11_11_11 7 + +#define DDR_SPEED(mcb) ((mcb) & 0x1f) +#define DDR_DEV_WIDTH(mcb) (((mcb) >> 5) & 0x7) + +#define DDR_WIDTH_x16 0 +#define DDR_WIDTH_x32 1 +#define DDR_WIDTH_x8 2 + + +static u32 get_ddr_refcnt_index(u32 mcb) +{ + u32 speed = DDR_SPEED(mcb); + u32 width = DDR_DEV_WIDTH(mcb); + + if (speed == DDR_SPEED_800_11_11_11 || + speed == DDR_SPEED_800_10_10_10) { + switch (width) { + case DDR_WIDTH_x16: + return E_DDR_1600_x16; + case DDR_WIDTH_x32: + return E_DDR_1600_x32; + default: + BUG(); + } + } else { + switch (width) { + case DDR_WIDTH_x16: + return E_DDR_2133_x16; + case DDR_WIDTH_x32: + return E_DDR_2133_x32; + default: + BUG(); + } + } + BUG(); + return 0xaa55aa55; +} + +static struct biu_config biu_config_bcm63158[32 + 1] = { + /* queue depth will be set based on ubus credits */ + [UBUS_PORT_ID_PER] = { + .blk_name = "PCM", + .src_pid = 3, + .queue_id = 7, + .cir = 2, + .cbs = 128, + .bonus = 0, + .ref_cnt = {12, 18, 22, 40 }, + .mstr_node = UBUS_PORT_ID_PER + }, + [UBUS_PORT_ID_USB] = { + .blk_name = "USB", + .src_pid = 4, + .queue_id = 6, + .cir = 3, + .cbs = 128, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_USB + }, + [UBUS_PORT_ID_SPU] = { + .blk_name = "SPU", + .src_pid = 5, + .queue_id = 9, + .cir = 1, + .cbs = 1, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_SPU + }, + [UBUS_PORT_ID_PERDMA] = { + .blk_name = "M2M", + .src_pid = 7, + .queue_id = 8, + .cir = 1, + .cbs = 1, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PERDMA + }, + [UBUS_PORT_ID_PCIE0] = { + .blk_name = "PCIe0", + .src_pid = 8, + .queue_id = 3, + .cir = 6, + .cbs = 128, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PCIE0 + }, + [UBUS_PORT_ID_PCIE2] = { + .blk_name = "PCIe2", + .src_pid = 9, + .queue_id = 4, + .cir = 3, + .cbs = 128, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PCIE2 + }, + [UBUS_PORT_ID_PCIE3] = { + .blk_name = "PCIe3", + .src_pid = 10, + .queue_id = 5, + .cir = 9, + .cbs = 256, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PCIE3 + }, + [UBUS_PORT_ID_QM] = { + .blk_name = "QM", + .src_pid = 22, + .queue_id = 10, + .cir = 38, + .cbs = 512, + .bonus = 4, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_QM + }, + [UBUS_PORT_ID_DQM] = { + .blk_name = "QM_DQM", + .src_pid = 23, + .queue_id = 1, + .cir = 5, + .cbs = 256, + .bonus = 4, + .ref_cnt = {6, 9, 11, 20 }, + .mstr_node = UBUS_PORT_ID_DQM + }, + [UBUS_PORT_ID_DMA0] = { + .blk_name = "DMA0", + .src_pid = 24, + .queue_id = 11, + .cir = 39, + .cbs = 128, + .bonus = 4, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_DMA0 + }, + [UBUS_PORT_ID_NATC] = { + .blk_name = "NAT$", + .src_pid = 26, + .queue_id = 2, + .cir = 6, + .cbs = 512, + .bonus = 4, + .ref_cnt = {21, 36, 45, 81 }, + .mstr_node = UBUS_PORT_ID_NATC + }, + [UBUS_PORT_ID_RQ0] = { + .blk_name = "RNR", + .src_pid = 32, + .queue_id = 0, + .cir = 14, + .cbs = 256, + .bonus = 4, + .ref_cnt = {12, 18, 22, 40 }, + .mstr_node = UBUS_PORT_ID_RQ0 + }, +}; + +#define UBUS_MASTER_TOKEN_REG(port) (0x400 + (port) * 4) + +#define UBUS_CONG_THRESHOLD_REG (0xc) + +#define UBUS_MASTER_DECODE_CONTROL (0x600) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_MASK (0x3 << 4) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_DEF (0x0 << 4) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_INPUT (0x1 << 4) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_CFG_REG (0x2 << 4) + +#define UBUS_MASTER_DECODE_CACHE_CONFIG (0x604) + + +struct ubus4_bcm63158 { + struct device *dev; + struct list_head list; + + struct resource regs; + struct ubus4_master *masters; + size_t nr_masters; + + unsigned long coherency_control_regs_phys; + void __iomem *coherency_control_regs; + u32 ddr_mcb; +}; + +struct ubus4_master { + struct ubus4_bcm63158 *ubus; + unsigned long regs_phys; + void __iomem *regs; + u32 port_id; + + const struct ubus_credit *credits; + size_t nr_credits; +}; + +static inline u32 ubus_master_readl(struct ubus4_master *m, u32 off) +{ + u32 ret; + + ret = readl(m->regs + off); + dev_dbg(m->ubus->dev, "read %08x at %08lx\n", ret, m->regs_phys + off); + return ret; +} + +static inline void ubus_master_writel(u32 val, struct ubus4_master *m, u32 off) +{ + dev_dbg(m->ubus->dev, "write %08x at %08lx\n", val, + m->regs_phys + off); + writel(val, m->regs + off); +} + +static inline void ubus_cohcfg_writel(u32 val, struct ubus4_bcm63158 *ubus, + u32 off) +{ + dev_dbg(ubus->dev, "coherency config write %08x at %08lx\n", + val, ubus->coherency_control_regs_phys + off); + writel(val, ubus->coherency_control_regs + off); +} + +static inline u32 ubus_cohcfg_readl(struct ubus4_bcm63158 *ubus, u32 off) +{ + u32 ret; + ret = readl(ubus->coherency_control_regs + off); + dev_dbg(ubus->dev, "coherency config read %08x at %08lx\n", + ret, ubus->coherency_control_regs_phys + off); + return ret; +} + +struct ubus4_master *ubus_get_master(struct ubus4_bcm63158 *ubus, + u32 port_id) +{ + size_t i; + for (i = 0; i < ubus->nr_masters; ++i) + if (ubus->masters[i].port_id == port_id) + return &ubus->masters[i]; + return NULL; +} + +void ubus_master_apply_credits(struct ubus4_master *m) +{ + size_t i; + + for (i = 0; i < m->nr_credits; ++i) { + const struct ubus_credit *c = &m->credits[i]; + + ubus_master_writel(c->credit, m, + UBUS_MASTER_TOKEN_REG(c->port_id)); + } +} +EXPORT_SYMBOL(ubus_master_apply_credits); + +void ubus_master_set_congestion_threshold(struct ubus4_master *m, u32 v) +{ + ubus_master_writel(v, m, UBUS_CONG_THRESHOLD_REG); +} +EXPORT_SYMBOL(ubus_master_set_congestion_threshold); + +void ubus_master_remap_port(struct ubus4_master *m) +{ + u32 v; + + ubus_master_writel(0x1, m, UBUS_MASTER_DECODE_CACHE_CONFIG); + + /* + * on bcm63158, only master cache control configuration is + * needed. + */ + v = ubus_master_readl(m, UBUS_MASTER_DECODE_CONTROL); + v &= ~UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_MASK; + v |= UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_CFG_REG; + ubus_master_writel(v, m, UBUS_MASTER_DECODE_CONTROL); +} +EXPORT_SYMBOL(ubus_master_remap_port); + +static int ubus_setup_master(struct ubus4_bcm63158 *ubus, + struct ubus4_master *the, + struct ubus_master_desc *desc) +{ + struct resource res; + + the->port_id = desc->port_id; + the->credits = desc->credits; + the->nr_credits = 0; + while (the->credits[the->nr_credits].port_id && + the->credits[the->nr_credits].credit) + ++the->nr_credits; + + dev_dbg(ubus->dev, "master %d, credits %zu\n", + the->port_id, the->nr_credits); + + res.start = ubus->regs.start + desc->regs_offset; + res.end = res.start + 0x1000 - 1; + res.name = "ubus master register"; + res.flags = ubus->regs.flags; + res.desc = ubus->regs.desc; + res.parent = NULL; + + if (!resource_contains(&ubus->regs, &res)) { + dev_err(ubus->dev, "registers for master %d are outside main " + "register space.", the->port_id); + return -EINVAL; + } + + the->ubus = ubus; + the->regs_phys = res.start; + the->regs = devm_ioremap_resource(ubus->dev, &res); + if (!the->regs) + return -ENOMEM; + + dev_dbg(ubus->dev, "master%d registers %pR\n", the->port_id, &res); + return 0; +} + +static void ubus_enable_all_wlu_srcpid(struct ubus4_bcm63158 *ubus) +{ + int i; + + for (i = 0; i < 8; ++i) { + ubus_cohcfg_readl(ubus, UBUS_COHERENCY_WLU_SCRPID(i)); + ubus_cohcfg_writel(0xffffffff, ubus, + UBUS_COHERENCY_WLU_SCRPID(i)); + } +} + + +static void ubus_reset_biu_cfg(struct ubus4_bcm63158 *ubus) +{ + int i; + + for (i = 0; i < UBUS_LUT_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_LUT(i)); + for (i = 0; i < UBUS_QUEUE_DEPTH_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_QUEUE_DEPTH(i)); + for (i = 0; i < UBUS_CBS_THRESH_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_CBS_THRESH(i)); + for (i = 0; i < UBUS_CIR_INCR_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_CIR_INCR(i)); + for (i = 0; i < UBUS_REF_CNT_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_REF_CNT(i)); + for (i = 0; i < UBUS_MAX_BONUS_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_MAX_BONUS(i)); +} + +static void ubus_configure_biu(struct ubus4_bcm63158 *ubus, + struct biu_config *biu_cfg) +{ + u32 offset, shift, mask; + u32 reg; + u32 ddr_refcount = get_ddr_refcnt_index(ubus->ddr_mcb); + + dev_dbg(ubus->dev, "configuring BIU for %s\n", biu_cfg->blk_name); + + /* + * assign queue ID + */ + get_lut_queue_id_params(biu_cfg->src_pid, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_LUT(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->queue_id << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_LUT(offset)); + + /* + * assign queue depth + */ + get_queue_depth_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_QUEUE_DEPTH(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->depth << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_QUEUE_DEPTH(offset)); + + /* + * assign CBS threshold. + */ + get_cbs_thresh_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_CBS_THRESH(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->cbs << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_CBS_THRESH(offset)); + + /* + * assign CIR increment + */ + get_cir_incr_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_CIR_INCR(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->cir << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_CIR_INCR(offset)); + + /* + * assign ref count. + */ + get_ref_cnt_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_REF_CNT(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->ref_cnt[ddr_refcount] << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_REF_CNT(offset)); + + /* + * assign max bonus + */ + get_max_bonus_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_MAX_BONUS(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->bonus << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_MAX_BONUS(offset)); +} + +static void ubus_calc_queue_depth_from_credits(struct ubus4_bcm63158 *ubus, + struct biu_config *biu_configs, + size_t nr_biu_configs) +{ + size_t i; + u32 total_depth = 0; + + for (i = 0; i < nr_biu_configs; ++i) { + struct biu_config *cfg = &biu_configs[i]; + struct ubus4_master *m; + size_t j; + + if (!cfg->blk_name) + continue ; + + m = ubus_get_master(ubus, cfg->mstr_node); + if (!m) + continue ; + + for (j = 0; j < m->nr_credits; ++j) + if (m->credits[j].port_id == UBUS_PORT_ID_BIU) + cfg->depth = m->credits[j].credit; + } + + for (i = 0; i < nr_biu_configs; ++i) { + struct biu_config *cfg = &biu_configs[i]; + + total_depth += cfg->depth; + } + if (total_depth > 64) + /* + * NOTE: the refsw invokes BUG() here which is a bit + * heavy handed. + */ + dev_warn(ubus->dev, "total depth %u is greater than 64.\n", + total_depth); + else + dev_info(ubus->dev, "total depth %u ok.\n", + total_depth); +} + +static int ubus_get_ddr_mcb(struct ubus4_bcm63158 *ubus, u32 *mcb) +{ + struct of_phandle_args args; + int err; + + err = of_parse_phandle_with_args(ubus->dev->of_node, "brcm,dram", + 0, 0, &args); + if (err) + return err; + + err = of_property_read_u32(args.np, "brcm,ddr-mcb", mcb); + if (err) + return err; + + return 0; +} + +static int bcm63158_ubus4_probe(struct platform_device *pdev) +{ + struct ubus4_bcm63158 *ubus; + struct resource *res_regs, *coh_regs; + int err; + size_t i; + + dev_dbg(&pdev->dev, "probe.\n"); + + res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_regs) { + dev_err(&pdev->dev, "unable to get registers resource.\n"); + return -ENOENT; + } + + coh_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!coh_regs) { + dev_err(&pdev->dev, "unable to get coherency control registers " + "resource.\n"); + return -ENOENT; + } + + dev_info(&pdev->dev, "registers: %pR\n", res_regs); + + + ubus = devm_kzalloc(&pdev->dev, sizeof (*ubus), GFP_KERNEL); + if (!ubus) + return -ENOMEM; + + dev_info(&pdev->dev, "coherency control registers: %pR\n", + coh_regs); + ubus->coherency_control_regs_phys = coh_regs->start; + ubus->coherency_control_regs = devm_ioremap_resource(&pdev->dev, + coh_regs); + if (!ubus->coherency_control_regs) + return -ENOMEM; + + ubus->dev = &pdev->dev; + ubus->regs = *res_regs; + + err = ubus_get_ddr_mcb(ubus, &ubus->ddr_mcb); + if (err) { + dev_err(&pdev->dev, "unable to get DDR mcb from device " + "tree.\n"); + return err; + } + + ubus->nr_masters = ARRAY_SIZE(bcm63158_masters); + ubus->masters = devm_kzalloc(&pdev->dev, + sizeof (*ubus->masters) * ubus->nr_masters, + GFP_KERNEL); + if (!ubus->masters) + return -ENOMEM; + + + for (i = 0; i < ubus->nr_masters; ++i) { + err = ubus_setup_master(ubus, + &ubus->masters[i], + &bcm63158_masters[i]); + if (err) + return err; + } + + for (i = 0; i < ubus->nr_masters; ++i) { + ubus_master_apply_credits(&ubus->masters[i]); + } + for (i = 0; i < ubus->nr_masters; ++i) { + ubus_master_remap_port(&ubus->masters[i]); + } + ubus_enable_all_wlu_srcpid(ubus); + ubus_reset_biu_cfg(ubus); + ubus_calc_queue_depth_from_credits(ubus, biu_config_bcm63158, + ARRAY_SIZE(biu_config_bcm63158)); + + for (i = 0; i < ARRAY_SIZE(biu_config_bcm63158); ++i) { + if (biu_config_bcm63158[i].blk_name) + ubus_configure_biu(ubus, &biu_config_bcm63158[i]); + } + + mutex_lock(&ubus_list_mutex); + list_add_tail(&ubus->list, &ubus_list); + mutex_unlock(&ubus_list_mutex); + + return 0; +} + +static const struct of_device_id bcm63158_ubus4_match[] = { + { .compatible = "brcm,bcm63158-ubus4" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63158_ubus4_of_match); + +struct platform_driver bcm63158_ubus4_driver = { + .probe = bcm63158_ubus4_probe, + .remove = NULL, /* FIXME*/ + .driver = { + .name = "bcm63158-ubus4", + .owner = THIS_MODULE, + .of_match_table = bcm63158_ubus4_match, + }, +}; + +builtin_platform_driver(bcm63158_ubus4_driver); + +struct ubus4_master *ubus4_master_of_get_index(struct device_node *np, + int index) +{ + int err; + struct of_phandle_args args; + struct ubus4_bcm63158 *ubus; + + err = of_parse_phandle_with_args(np, "ubus", "#ubus-cells", index, + &args); + if (err) { + printk("unable to parse ubus phandle.\n"); + return ERR_PTR(err); + } + + if (args.args_count != 1) + return ERR_PTR(-EINVAL); + + mutex_lock(&ubus_list_mutex); + list_for_each_entry (ubus, &ubus_list, list) { + if (ubus->dev->of_node == args.np) { + mutex_unlock(&ubus_list_mutex); + goto found; + } + } + mutex_unlock(&ubus_list_mutex); + return ERR_PTR(-EPROBE_DEFER); + +found: + return ubus_get_master(ubus, args.args[0]); +} +EXPORT_SYMBOL(ubus4_master_of_get_index); + +struct ubus4_master *ubus4_master_of_get(struct device_node *np) +{ + return ubus4_master_of_get_index(np, 0); +} +EXPORT_SYMBOL(ubus4_master_of_get); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63158 SoC UBUS driver."); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./Makefile linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/Makefile --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/Makefile 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,8 @@ +obj-$(CONFIG_SOC_BCM63XX_XRDP) += xrdp_drv.o + +xrdp_drv-y += \ + xrdp.o \ + xrdp_api.o + +xrdp_drv-$(CONFIG_SOC_BCM63XX_XRDP_IOCTL) += xrdp_ioctl.o +xrdp_drv-$(CONFIG_DEBUG_FS) += xrdp_debug.o diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,91 @@ +#ifndef XRDP_REGS_H_ +#define XRDP_REGS_H_ + +enum { + BB_ID_FIRST = 0, + BB_ID_RNR0 = 0, /* 0x0 */ + BB_ID_RNR1 = 1, /* 0x1 */ + BB_ID_RNR2 = 2, /* 0x2 */ + BB_ID_RNR3 = 3, /* 0x3 */ + BB_ID_RNR4 = 4, /* 0x4 */ + BB_ID_RNR5 = 5, /* 0x5 */ + BB_ID_CNPL = 17, /* 0x11 */ + BB_ID_DISPATCHER_REORDER = 18, /* 0x12 */ + BB_ID_DMA0 = 19, /* 0x13 */ + BB_ID_SDMA0 = 21, /* 0x15 */ + BB_ID_SDMA1 = 22, /* 0x16 */ + BB_ID_FPM = 23, /* 0x17 */ + BB_ID_HASH = 24, /* 0x18 */ + BB_ID_NATC = 25, /* 0x19 */ + BB_ID_QM_CP_SDMA = 26, /* 0x1a */ + BB_ID_QM_RNR_GRID = 27, /* 0x1b */ + BB_ID_QM_BBHTX = 28, /* 0x1c */ + BB_ID_QM_TOP = 29, /* 0x1d */ + BB_ID_QM_CP_MACHINE = 30, /* 0x1e */ + BB_ID_RX_BBH_0 = 31, /* 0x1f */ + BB_ID_TX_LAN = 32, /* 0x20 */ + BB_ID_RX_BBH_1 = 33, /* 0x21 */ + BB_ID_RX_BBH_2 = 35, /* 0x23 */ + BB_ID_ACB = 47, /* 0x2f */ + BB_ID_SBPM = 48, /* 0x30 */ + BB_ID_TCAM_0 = 49, /* 0x31 */ + BB_ID_RX_PON = 50, /* 0x32 */ + BB_ID_TX_PON = 51, /* 0x33 */ + BB_ID_TX_PON_STAT = 52, /* 0x34 */ + BB_ID_RX_DSL = 53, /* 0x35 */ + BB_ID_TX_DSL = 54, /* 0x36 */ + BB_ID_TX_DSL_STAT = 55, /* 0x37 */ + BB_ID_RX_10G = 56, /* 0x38 */ + BB_ID_TX_10G = 57, /* 0x39 */ + BB_ID_RX_2P5 = 58, /* 0x3a */ + BB_ID_TX_2P5 = 59, /* 0x3b */ + BB_ID_LAST = 59 +}; + +#define BB_MSG_RNR_TO_BBH_TX_QUEUE_SHIFT 6 + + +enum xrdp_regs_area { + XRDP_AREA_CORE, + XRDP_AREA_WAN_TOP, +}; + +#define RNR_SRAM_OFFSET(x) (0x00c00000 + 0x20000 * (x)) +#define RNR_SRAM_SIZE (16 * 1024) + +#define RNR_INST_OFFSET(x) (0x00c10000 + 0x20000 * (x)) +#define RNR_INST_SIZE 32768 + +#define RNR_CNXT_OFFSET(x) (0x00c18000 + 0x20000 * (x)) +#define RNR_CNXT_SIZE 1536 + +#define RNR_PRED_OFFSET(x) (0x00c1c000 + 0x20000 * (x)) +#define RNR_PRED_SIZE 2048 + +#define RDP_PSRAM_OFFSET (0x600000) +#define RDP_PSRAM_SIZE (256 * 1024) + +/* relative to core */ +#define UNIMAC_OFFSET (0xda0000) + +#include "xrdp_regs_acb_if.h" +#include "xrdp_regs_bac_if.h" +#include "xrdp_regs_bbh_rx.h" +#include "xrdp_regs_bbh_tx.h" +#include "xrdp_regs_cnpl.h" +#include "xrdp_regs_dma.h" +#include "xrdp_regs_dqm.h" +#include "xrdp_regs_dsptchr.h" +#include "xrdp_regs_fpm.h" +#include "xrdp_regs_hash.h" +#include "xrdp_regs_natc.h" +#include "xrdp_regs_psram.h" +#include "xrdp_regs_qm.h" +#include "xrdp_regs_rnr_quad.h" +#include "xrdp_regs_rnr_regs.h" +#include "xrdp_regs_sbpm.h" +#include "xrdp_regs_tcam.h" +#include "xrdp_regs_ubus_mstr.h" +#include "xrdp_regs_ubus_slv.h" + +#endif /* XRDP_REGS_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_acb_if.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_acb_if.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_acb_if.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_acb_if.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,131 @@ +#ifndef XRDP_REGS_ACB_IF_H_ +#define XRDP_REGS_ACB_IF_H_ + +/* relative to core */ +#define ACB_IF_OFFSET_0 0xe50800 + +/* + * Register + * + * misc configs 0 + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0 0x0 + +/* add to the len of each packet 4B of crc */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0_CRC_ADD_MASK 0x1 + +/* + * location byte for the valid bit in the result(last bit in that byte): + * 0: + * bit 7. + * .. + * 7: + * bit 63 +*/ +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0_VAL_LOC_SHIFT 4 +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0_VAL_LOC_MASK 0x70 + + +/* + * Registers - is [ 0 => 2 ] - read-only + * + * Number of commands that were processed for each command type (order - + * intend, sent, stat). + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_TYPE(x) (0x100 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_TYPE_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_TYPE_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 2 ] - read-only + * + * Number of commands that were processed for each IMP(0,1,2). + * e. + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_IMP(x) (0x110 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_IMP_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_IMP_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Number of commands (for each of - intend, sent) that were for aggregated + * packets. + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_AGG(x) (0x120 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_AGG_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_AGG_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Number of buffers that were counted for each command(order - intend, + * sent). + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_BUFFS(x) (0x130 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_BUFFS_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_BUFFS_VAL_MASK 0xffffffff + + +/* + * Register + * + * bits rd_clr and wrap for the pm counters(above) + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_GEN_CFG 0x150 + +/* read clear bit */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_GEN_CFG_RD_CLR_MASK 0x1 + +/* read clear bit */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_GEN_CFG_WRAP_MASK 0x2 + + +/* + * Register + * + * selects the debug vecore + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGSEL 0x200 + +/* selects th debug vector */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGSEL_VS_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGSEL_VS_MASK 0x7f + + +/* + * Register - read-only + * + * the debug bus + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGBUS 0x204 + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGBUS_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGBUS_VAL_MASK 0x1fffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * status register (msb, lsb) + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_STAT(x) (0x240 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_STAT_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_STAT_VAL_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_ACB_IF_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_bac_if.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bac_if.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_bac_if.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bac_if.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,285 @@ +#ifndef XRDP_REGS_BAC_IF_H_ +#define XRDP_REGS_BAC_IF_H_ + +/* relative to core */ +#define BAC_IF_OFFSET(x) (0xe40000 + (x) * 0x1000) + +/* + * Register + * + * FULL threshold of result fifo for rdy indication to engine: + * If there are less words than thr left - there will be !rdy indication to + * engine, even if there is antry empty, and result will not be pushed into + * fifo. + * - NOT USED ANYMORE! + */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_RSLT_F_FULL_THR 0x0 + +/* threshold */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_RSLT_F_FULL_THR_THR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_RSLT_F_FULL_THR_THR_MASK 0xf + + +/* + * Register + * + * route override info for the route address decoder + */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE 0x4 + +/* en override route address */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_EN_MASK 0x1 + +/* id to override route address */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ID_SHIFT 4 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ID_MASK 0x3f0 + +/* addr to override route address */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ADDR_SHIFT 16 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ADDR_MASK 0x3ff0000 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL 0xc + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 127 ] - read-only + * + * ingress fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO(x) (0x100 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * cmd fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO(x) (0x500 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * result fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO(x) (0x600 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * egress fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO(x) (0x700 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * reply params array debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR(x) (0x800 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_MASK 0x80000000 + + +/* + * Register - read-only + * + * number of bb transactions that enter the ingress fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT 0xc00 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of commands (eob) that enter the command fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT 0xc04 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of commands (eob) that enter the engine from the accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT 0xc08 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of results (eob) that enter the result fifo of accl_if from the + * engine + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT 0xc10 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of results (eob) that leave the result fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT 0xc14 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of bb transactions that leave the egress fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT 0xc18 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of commands that entered and were longer than the max command + * size for the accelerator configured in HW parameter + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C 0xc30 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * reply params array is full (no free entries), and a new command has + * arrived + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C 0xc34 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * reply params array is empty, and a new result has arrived + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C 0xc38 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_MASK 0xffffffff + + +/* + * Register + * + * bits rd_clr and wrap for the counters + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG 0xcfc + +/* read clear bit */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_MASK 0x1 + +/* read clear bit */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_MASK 0x2 + + +#endif /* ! XRDP_REGS_BAC_IF_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_bbh_rx.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_rx.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_bbh_rx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_rx.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,1387 @@ +#ifndef XRDP_REGS_BBH_RX_H_ +#define XRDP_REGS_BBH_RX_H_ + +/* relative to core */ +#define BBH_RX_OFFSET_0 0xd94000 + +/* relative to core */ +#define BBH_RX_OFFSET_1 0xd94400 + +/* relative to core */ +#define BBH_RX_OFFSET_2 0xd94800 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_3 0x8000 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_4 0x8400 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_5 0x8800 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_6 0x8c00 + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * The BB defines the Route address for the specific unit. + */ +#define BBH_RX_GENERAL_CFG_BBCFG 0x0 + +/* + * SDMA BB ID. + * This ID defines the BB ID of the SDMA that the BBH communicates with. +*/ +#define GENERAL_CFG_BBCFG_SDMABBID_SHIFT 0 +#define GENERAL_CFG_BBCFG_SDMABBID_MASK 0x3f + +/* + * Dispatcher BB ID. + * This ID defines the BB ID of the Dispatcher that the BBH communicates + * with. +*/ +#define GENERAL_CFG_BBCFG_DISPBBID_SHIFT 8 +#define GENERAL_CFG_BBCFG_DISPBBID_MASK 0x3f00 + +/* + * SBPM BB ID. + * This ID defines the BB ID of the SBPM that the BBH communicates with. +*/ +#define GENERAL_CFG_BBCFG_SBPMBBID_SHIFT 16 +#define GENERAL_CFG_BBCFG_SBPMBBID_MASK 0x3f0000 + + +/* + * Register + * + * For every reassembled packet in the PSRAM the BBH writes a packet + * descriptor (PD) into the Dispatcher. + * The PDs are arranged using a link list in the Dispatcher. + * The Dispatcher has 32 virtual queues (ingress queues) and the BBH may be + * assigned to each of the 32 virtual queues of the DispatcherThis register + * defines virtual queue for normal and exclusive packets. + */ +#define BBH_RX_GENERAL_CFG_DISPVIQ 0x4 + +/* Defines the Dispatchers Virtual Ingress Queue for normal packets */ +#define GENERAL_CFG_DISPVIQ_NORMALVIQ_SHIFT 0 +#define GENERAL_CFG_DISPVIQ_NORMALVIQ_MASK 0x1f + +/* Defines the Dispatchers Virtual Ingress Queue for exclusive packets */ +#define GENERAL_CFG_DISPVIQ_EXCLVIQ_SHIFT 8 +#define GENERAL_CFG_DISPVIQ_EXCLVIQ_MASK 0x1f00 + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNDATALSB 0x8 + +/* + * Pattern Data[31: + * 0] +*/ +#define GENERAL_CFG_PATTERNDATALSB_PATTERNDATALSB_SHIFT 0 +#define GENERAL_CFG_PATTERNDATALSB_PATTERNDATALSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNDATAMSB 0xc + +/* + * Pattern Data[63: + * 32] +*/ +#define GENERAL_CFG_PATTERNDATAMSB_PATTERNDATAMSB_SHIFT 0 +#define GENERAL_CFG_PATTERNDATAMSB_PATTERNDATAMSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNMASKLSB 0x10 + +/* + * Pattern mask[31: + * 0] +*/ +#define GENERAL_CFG_PATTERNMASKLSB_PATTERNMASKLSB_SHIFT 0 +#define GENERAL_CFG_PATTERNMASKLSB_PATTERNMASKLSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNMASKMSB 0x14 + +/* + * Pattern Mask[63: + * 32] +*/ +#define GENERAL_CFG_PATTERNMASKMSB_PATTERNMASKMSB_SHIFT 0 +#define GENERAL_CFG_PATTERNMASKMSB_PATTERNMASKMSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to special packet types (e. + * g. + * pause). + * This register enables this function + */ +#define BBH_RX_GENERAL_CFG_EXCLQCFG 0x18 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PLOAMEN_MASK 0x1 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PRI3EN_MASK 0x2 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PAUSEEN_MASK 0x4 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PFCEN_MASK 0x8 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_CTRLEN_MASK 0x10 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_MULTEN_MASK 0x20 + +/* + * Defines the pattern recognition offset within the packet. + * Offset is 8 bytes resolution +*/ +#define GENERAL_CFG_EXCLQCFG_PATTENOFFSET_SHIFT 8 +#define GENERAL_CFG_EXCLQCFG_PATTENOFFSET_MASK 0xf00 + +/* Must be enabled if pattern recognition is used */ +#define GENERAL_CFG_EXCLQCFG_PATTERNEN_MASK 0x10000 + +/* Must be enabled if Exclusive VIQ is used */ +#define GENERAL_CFG_EXCLQCFG_EXCEN_MASK 0x100000 + + +/* + * Register + * + * The BBH reassembles the incoming data in the SRAM. + * The Data is written into the SRAM using the SDMA. + * The data is organized in a configurable number of chunks of 128 bytes. + * The BBH arranges the written data in the SDMA in these chunks. + * It arranges the data in a predefined address space in the SDMA memory + * and manages the chunks in a cyclic FIFO style. + * For every write chunk the BBH writes a write descriptor. + * The write descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style as well. + * This register defines the Data and descriptors base addresses. + */ +#define BBH_RX_GENERAL_CFG_SDMAADDR 0x1c + +/* + * The Data FIFO base address within the SDMA address space. + * The address is in chunk resolution (128 bytes). + * The value should be identical to the relevant configuration in the SDMA. +*/ +#define GENERAL_CFG_SDMAADDR_DATABASE_SHIFT 0 +#define GENERAL_CFG_SDMAADDR_DATABASE_MASK 0x3f + +/* + * The Descriptor FIFO base address within the SDMA address space. + * The address is in chunk descriptor resolution (8 bytes). + * The value should be identical to the relevant configuration in the SDMA. +*/ +#define GENERAL_CFG_SDMAADDR_DESCBASE_SHIFT 8 +#define GENERAL_CFG_SDMAADDR_DESCBASE_MASK 0x3f00 + + +/* + * Register + * + * The BBH reassembles the incoming data in the SRAM. + * The Data is written into the SRAM using the SDMA. + * The data is organized in a configurable number of chunks of 128 bytes. + * The BBH arranges the written data in the SDMA in these chunks. + * It arranges the data in a predefined address space in the SDMA memory + * and manages the chunks in a cyclic FIFO style. + * For every write chunk the BBH writes a write descriptor. + * The write descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style as well. + * The BBH handles the congestion over the SDMA write chunks according to 2 + * priorities (low + high, exclusive). + * This field defines the number of occupied write chunks for dropping + * normal or high priority packets. + * If the number of occupied chunk is lower than this threshold, then all + * packets are passed. + * If the number of occupied chunk is equal or higher than this threshold, + * then only exclusive priority packets are passed. + * This register defines the Data and descriptors FIFO sizes and the + * exclusive threshold. + */ +#define BBH_RX_GENERAL_CFG_SDMACFG 0x20 + +/* Defines the size of the Chunk descripors FIFO in the DMA. */ +#define GENERAL_CFG_SDMACFG_NUMOFCD_SHIFT 0 +#define GENERAL_CFG_SDMACFG_NUMOFCD_MASK 0x7f + +/* + * This field defines the number of occupied write chunks for dropping + * normal or high priority packets. +*/ +#define GENERAL_CFG_SDMACFG_EXCLTH_SHIFT 8 +#define GENERAL_CFG_SDMACFG_EXCLTH_MASK 0x7f00 + +/* + * BBH has two methods to keep coherency: + * 1. + * Write reply for last chunk only2. + * Write reply for each chunk1 - enables the first method0 - enables the + * second method +*/ +#define GENERAL_CFG_SDMACFG_COHERENCYEN_MASK 0x10000 + + +/* + * Register + * + * There are 4 global configuration for Minimum packet size. + * Each flow can get one out of these 4 global configurations. + * Packets shorter than this threshold will be discarded. + */ +#define BBH_RX_GENERAL_CFG_MINPKT0 0x24 + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT0_SHIFT 0 +#define GENERAL_CFG_MINPKT0_MINPKT0_MASK 0xff + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT1_SHIFT 8 +#define GENERAL_CFG_MINPKT0_MINPKT1_MASK 0xff00 + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT2_SHIFT 16 +#define GENERAL_CFG_MINPKT0_MINPKT2_MASK 0xff0000 + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT3_SHIFT 24 +#define GENERAL_CFG_MINPKT0_MINPKT3_MASK 0xff000000 + + +/* + * Register + * + * There are 4 global configuration for Maximum packet size. + * Each flow can get one out of these 4 global configurations. + * Packets longer than this threshold will be discarded. + */ +#define BBH_RX_GENERAL_CFG_MAXPKT0 0x28 + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT0_MAXPKT0_SHIFT 0 +#define GENERAL_CFG_MAXPKT0_MAXPKT0_MASK 0x3fff + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT0_MAXPKT1_SHIFT 16 +#define GENERAL_CFG_MAXPKT0_MAXPKT1_MASK 0x3fff0000 + + +/* + * Register + * + * There are 4 global configuration for Maximum packet size. + * Each flow can get one out of these 4 global configurations. + * Packets longer than this threshold will be discarded. + */ +#define BBH_RX_GENERAL_CFG_MAXPKT1 0x2c + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT1_MAXPKT2_SHIFT 0 +#define GENERAL_CFG_MAXPKT1_MAXPKT2_MASK 0x3fff + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT1_MAXPKT3_SHIFT 16 +#define GENERAL_CFG_MAXPKT1_MAXPKT3_MASK 0x3fff0000 + + +/* + * Register + * + * The BBH writes the packets into the PSRAM. + * The start of data offset is configurable. + * This register defines the SOP (start of packet) offset. + */ +#define BBH_RX_GENERAL_CFG_SOPOFFSET 0x30 + +/* + * The SOP offset in bytes. + * Allowed values: + * 0-127. + * This value should match the relevant configuration in the Runner block. +*/ +#define GENERAL_CFG_SOPOFFSET_SOPOFFSET_SHIFT 0 +#define GENERAL_CFG_SOPOFFSET_SOPOFFSET_MASK 0x7f + + +/* + * Register + * + * The BBH manages a flow control indication towards the Ethernet MAC + * according to BB messages from the FW. + * Each FW command will assert the flow control indication towards the + * Ethernet MAC and will trigger a timer. + * When the timer expires, the BBH will de-assert the flow control + * indication. + * This register also disable BBH packet drop due to no space in the SDMA, + * SBPM or Dispatcher. + */ +#define BBH_RX_GENERAL_CFG_FLOWCTRL 0x34 + +/* + * Timer value before de-asserting the flow control indication. + * The duration of the time is determined according to the BBH clock + * frequency. +*/ +#define GENERAL_CFG_FLOWCTRL_TIMER_SHIFT 0 +#define GENERAL_CFG_FLOWCTRL_TIMER_MASK 0xffffff + +/* Disable dropping packets due to no space in the Dispatcher. */ +#define GENERAL_CFG_FLOWCTRL_DISPDROPDIS_MASK 0x1000000 + +/* Disable dropping packets due to no space in the SDMA. */ +#define GENERAL_CFG_FLOWCTRL_SDMADROPDIS_MASK 0x2000000 + +/* Disable dropping packets due to no space in the SBPM. */ +#define GENERAL_CFG_FLOWCTRL_SBPMDROPDIS_MASK 0x4000000 + +/* Asserting this bit will force a flow control indication towards the MAC */ +#define GENERAL_CFG_FLOWCTRL_FCFORCE_MASK 0x10000000 + + +/* + * Register + * + * The BBH omits the 4 CRC bytes of the packet for all packets except + * PLOAMs and OMCI (marked as exclusive priority). + * The configuration will disable this functionality. + */ +#define BBH_RX_GENERAL_CFG_CRCOMITDIS 0x38 + +/* Disable CRC omitting. */ +#define GENERAL_CFG_CRCOMITDIS_CRCOMITDIS_MASK 0x1 + + +/* + * Register + * + * Controls the BBH enable configuration + */ +#define BBH_RX_GENERAL_CFG_ENABLE 0x3c + +/* + * When de-asserted, the BBH will not read new fragment/packet from the + * MAC. + * The BBH will Gracefully enable/disable (on fragment boundary for + * N/X/GPON/2 and on packet boundary for the rest) +*/ +#define GENERAL_CFG_ENABLE_PKTEN_MASK 0x1 + +/* When de-asserted, the BBH will not pre-fetch SBPM buffers */ +#define GENERAL_CFG_ENABLE_SBPMEN_MASK 0x2 + + +/* + * Register + * + * When asserted, G999. + * 1 fragments are received by the BBH. + * The BBH will pass the G999. + * 1 header in the PD instead of the 1588 time-stamp. + */ +#define BBH_RX_GENERAL_CFG_G9991EN 0x40 + +/* + * Enable G999. + * 1 +*/ +#define GENERAL_CFG_G9991EN_ENABLE_MASK 0x1 + +/* + * Enable G999. + * 1 transfer of bytes 4-7 instead of bytes 0-3 +*/ +#define GENERAL_CFG_G9991EN_BYTES4_7ENABLE_MASK 0x2 + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines X. + */ +#define BBH_RX_GENERAL_CFG_PERFLOWTH 0x44 + +/* + * According to this threshold: + * Flows 32 - th will have set 0 configurations. + * Flows (th+1) - 255 will have set 1 configurations. +*/ +#define GENERAL_CFG_PERFLOWTH_FLOWTH_SHIFT 0 +#define GENERAL_CFG_PERFLOWTH_FLOWTH_MASK 0xff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the configurations sets. + */ +#define BBH_RX_GENERAL_CFG_PERFLOWSETS 0x48 + +/* + * Set 0 of the general configuration. + * Selects between 4 global minimum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL0_SHIFT 0 +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL0_MASK 0x3 + +/* + * Set 0 of the general configuration. + * Selects between 4 global maximum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL0_SHIFT 2 +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL0_MASK 0xc + +/* + * Set 1 of the general configuration. + * Selects between 4 global minimum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL1_SHIFT 4 +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL1_MASK 0x30 + +/* + * Set 1 of the general configuration. + * Selects between 4 global maximum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL1_SHIFT 6 +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL1_MASK 0xc0 + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the minimum packet size for flows 0-15. + */ +#define BBH_RX_GENERAL_CFG_MINPKTSEL0 0x50 + +/* + * Selects one of the 4 global configurations for minimum packet size. + * Bits {2n, 2n+1} refers to flow n. +*/ +#define GENERAL_CFG_MINPKTSEL0_MINPKTSEL_SHIFT 0 +#define GENERAL_CFG_MINPKTSEL0_MINPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the minimum packet size for flows 16-31. + */ +#define BBH_RX_GENERAL_CFG_MINPKTSEL1 0x54 + +/* + * Selects one of the 4 global configurations for minimum packet size. + * Bits {2n, 2n+1} refers to flow n+16. +*/ +#define GENERAL_CFG_MINPKTSEL1_MINPKTSEL_SHIFT 0 +#define GENERAL_CFG_MINPKTSEL1_MINPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the maximum packet size for flows 0-15. + */ +#define BBH_RX_GENERAL_CFG_MAXPKTSEL0 0x58 + +/* + * Selects one of the 4 global configurations for maximum packet size. + * Bits {2n, 2n+1} refers to flow n. +*/ +#define GENERAL_CFG_MAXPKTSEL0_MAXPKTSEL_SHIFT 0 +#define GENERAL_CFG_MAXPKTSEL0_MAXPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the maximum packet size for flows 16-31. + */ +#define BBH_RX_GENERAL_CFG_MAXPKTSEL1 0x5c + +/* + * Selects one of the 4 global configurations for maximum packet size. + * Bits {2n, 2n+1} refers to flow n+16. +*/ +#define GENERAL_CFG_MAXPKTSEL1_MAXPKTSEL_SHIFT 0 +#define GENERAL_CFG_MAXPKTSEL1_MAXPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * When the BBH functions as a PON BBH, this bit selects between N/X/GPON/2 + * and 10G/EPON functionality + */ +#define BBH_RX_GENERAL_CFG_MACMODE 0x60 + +/* + * Relevant for PON BBH only. + * Distinguish between GPON (GPON, XGPON, NGPON2) to EPON (EPON, 10GEPON): + * 0: + * N/X/GPON/21: + * 10G/EPON +*/ +#define GENERAL_CFG_MACMODE_MACMODE_MASK 0x1 + +/* + * Relevant for GPON BBH only. + * Distinguish between GPON and XGPON (XGPON, NGPON2): + * 0: + * GPON1: + * N/X/GPON/2 +*/ +#define GENERAL_CFG_MACMODE_GPONMODE_MASK 0x2 + +/* + * Relevant for VDSL BBH only. + * Distinguish between VDSL and non VDSL: + * 0: + * Non VDSL1: + * VDSL +*/ +#define GENERAL_CFG_MACMODE_MACVDSL_MASK 0x4 + + +/* + * Register + * + * Configure max on the fly requests to SBPM + */ +#define BBH_RX_GENERAL_CFG_SBPMCFG 0x64 + +/* Configure max on the fly requests to SBPM */ +#define GENERAL_CFG_SBPMCFG_MAXREQ_SHIFT 0 +#define GENERAL_CFG_SBPMCFG_MAXREQ_MASK 0xf + + +/* + * Register + * + * This register enable reset of internal units (for WA perposes). + */ +#define BBH_RX_GENERAL_CFG_RXRSTRST 0x68 + +/* + * Writing 1 to this register will reset the input buffer. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_INBUFRST_MASK 0x1 + +/* + * Writing 1 to this register will reset the Burst buffer. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_BURSTBUFRST_MASK 0x2 + +/* + * Writing 1 to this register will reset the ingress context. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_INGRESSCNTXT_MASK 0x4 + +/* + * Writing 1 to this register will reset the IH buffer enable. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_CMDFIFORST_MASK 0x8 + +/* + * Writing 1 to this register will reset the SBPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define GENERAL_CFG_RXRSTRST_SBPMFIFORST_MASK 0x10 + +/* + * Writing 1 to this register will reset the coherency FIFO. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_COHERENCYFIFORST_MASK 0x20 + +/* + * Writing 1 to this register will reset the reassembly context table. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define GENERAL_CFG_RXRSTRST_CNTXTRST_MASK 0x40 + +/* + * Writing 1 to this register will reset the SDMA write pointer. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_SDMARST_MASK 0x80 + + +/* + * Register + * + * Selects one out of 10 possible debug vectors + */ +#define BBH_RX_GENERAL_CFG_RXDBGSEL 0x6c + +/* Selects one out of 10 possible debug vectors */ +#define GENERAL_CFG_RXDBGSEL_RXDBGSEL_SHIFT 0 +#define GENERAL_CFG_RXDBGSEL_RXDBGSEL_MASK 0xf + + +/* + * Register + * + * This register enables changing the route address for a specified BB ID + */ +#define BBH_RX_GENERAL_CFG_BBHRX_RADDR_DECODER 0x70 + +/* This field contains the users BB id for override */ +#define GENERAL_CFG_BBHRX_RADDR_DECODER_ID_2OVERWR_SHIFT 0 +#define GENERAL_CFG_BBHRX_RADDR_DECODER_ID_2OVERWR_MASK 0x3f + +/* The new RA */ +#define GENERAL_CFG_BBHRX_RADDR_DECODER_OVERWR_RA_SHIFT 8 +#define GENERAL_CFG_BBHRX_RADDR_DECODER_OVERWR_RA_MASK 0x3ff00 + +/* the overwr mechanism will be used only if this bit is active (1). */ +#define GENERAL_CFG_BBHRX_RADDR_DECODER_OVERWR_EN_MASK 0x1000000 + + +/* + * Register + * + * There an option to disable CRC error counting for this flow. + */ +#define BBH_RX_GENERAL_CFG_NONETH 0x74 + +/* Non Ethernet flow ID */ +#define GENERAL_CFG_NONETH_FLOWID_SHIFT 0 +#define GENERAL_CFG_NONETH_FLOWID_MASK 0xff + +/* When asserted, CRC errors will not be counted for that flow. */ +#define GENERAL_CFG_NONETH_ENABLE_MASK 0x100 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define BBH_RX_GENERAL_CFG_CLK_GATE_CNTRL 0x78 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define GENERAL_CFG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register - read-only + * + * This counter counts the number of incoming good packets. + * It counts the packets from all flows together. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_INPKT 0x100 + +/* This counter counts the number of incoming good packets. */ +#define PM_COUNTERS_INPKT_INPKT_SHIFT 0 +#define PM_COUNTERS_INPKT_INPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Third flow error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_THIRDFLOW 0x104 + +/* PM counter value. */ +#define PM_COUNTERS_THIRDFLOW_PMVALUE_SHIFT 0 +#define PM_COUNTERS_THIRDFLOW_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to SOP after SOP error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_SOPASOP 0x108 + +/* PM counter value. */ +#define PM_COUNTERS_SOPASOP_PMVALUE_SHIFT 0 +#define PM_COUNTERS_SOPASOP_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Too short error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_TOOSHORT 0x10c + +/* PM counter value. */ +#define PM_COUNTERS_TOOSHORT_PMVALUE_SHIFT 0 +#define PM_COUNTERS_TOOSHORT_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Too long error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_TOOLONG 0x110 + +/* PM counter value. */ +#define PM_COUNTERS_TOOLONG_PMVALUE_SHIFT 0 +#define PM_COUNTERS_TOOLONG_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to CRC error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_CRCERROR 0x114 + +/* PM counter value. */ +#define PM_COUNTERS_CRCERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_CRCERROR_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to XGPON encryption error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_ENCRYPTERROR 0x118 + +/* PM counter value. */ +#define PM_COUNTERS_ENCRYPTERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_ENCRYPTERROR_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Dispatcher congestion error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_DISPCONG 0x11c + +/* PM counter value. */ +#define PM_COUNTERS_DISPCONG_PMVALUE_SHIFT 0 +#define PM_COUNTERS_DISPCONG_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to NO SBPM SBN error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSBPMSBN 0x124 + +/* PM counter value. */ +#define PM_COUNTERS_NOSBPMSBN_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSBPMSBN_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to No SDMA CD error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSDMACD 0x12c + +/* PM counter value. */ +#define PM_COUNTERS_NOSDMACD_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSDMACD_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of incoming good PLOAMs. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_INPLOAM 0x130 + +/* This counter counts the number of incoming PLOAMs. */ +#define PM_COUNTERS_INPLOAM_INPLOAM_SHIFT 0 +#define PM_COUNTERS_INPLOAM_INPLOAM_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the PLOAMs drop due to CRC error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM 0x134 + +/* PM counter value. */ +#define PM_COUNTERS_CRCERRORPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_CRCERRORPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Dispatcher congestion error + * for PLOAM. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_DISPCONGPLOAM 0x138 + +/* PM counter value. */ +#define PM_COUNTERS_DISPCONGPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_DISPCONGPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the PLOAMs drop due to No SBPM SBN error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM 0x13c + +/* PM counter value. */ +#define PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to No SDMA CD error for PLOAMs. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM 0x140 + +/* PM counter value. */ +#define PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the events of EPON type sequence which is wrong, + * meaning no sop after header, or sop/header in the middle of packet + * (before eop). + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_EPONTYPERROR 0x144 + +/* PM counter value. */ +#define PM_COUNTERS_EPONTYPERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_EPONTYPERROR_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of RUNT packets received from the XLMAC. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_RUNTERROR 0x148 + +/* PM counter value. */ +#define PM_COUNTERS_RUNTERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_RUNTERROR_PMVALUE_MASK 0xffff + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX0LSB 0x200 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX0LSB_INREASS_MASK 0x1 + +/* Flow ID */ +#define DEBUG_CNTXTX0LSB_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX0LSB_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX0LSB_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX0LSB_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX0MSB 0x204 + +/* Current BN */ +#define DEBUG_CNTXTX0MSB_CURBN_SHIFT 0 +#define DEBUG_CNTXTX0MSB_CURBN_MASK 0x1fff + +/* First BN */ +#define DEBUG_CNTXTX0MSB_FIRSTBN_SHIFT 16 +#define DEBUG_CNTXTX0MSB_FIRSTBN_MASK 0x7fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX1LSB 0x208 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX1LSB_INREASS_MASK 0x1 + +/* Flow ID */ +#define DEBUG_CNTXTX1LSB_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX1LSB_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX1LSB_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX1LSB_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX1MSB 0x20c + +/* Current BN */ +#define DEBUG_CNTXTX1MSB_CURBN_SHIFT 0 +#define DEBUG_CNTXTX1MSB_CURBN_MASK 0x1fff + +/* First BN */ +#define DEBUG_CNTXTX1MSB_FIRSTBN_SHIFT 16 +#define DEBUG_CNTXTX1MSB_FIRSTBN_MASK 0x7fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX0INGRESS 0x210 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX0INGRESS_INREASS_MASK 0x1 + +/* SOP */ +#define DEBUG_CNTXTX0INGRESS_SOP_MASK 0x10 + +/* Priority */ +#define DEBUG_CNTXTX0INGRESS_PRIORITY_SHIFT 6 +#define DEBUG_CNTXTX0INGRESS_PRIORITY_MASK 0xc0 + +/* Flow ID */ +#define DEBUG_CNTXTX0INGRESS_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX0INGRESS_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX0INGRESS_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX0INGRESS_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX1INGRESS 0x214 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX1INGRESS_INREASS_MASK 0x1 + +/* SOP */ +#define DEBUG_CNTXTX1INGRESS_SOP_MASK 0x10 + +/* Priority */ +#define DEBUG_CNTXTX1INGRESS_PRIORITY_SHIFT 6 +#define DEBUG_CNTXTX1INGRESS_PRIORITY_MASK 0xc0 + +/* Flow ID */ +#define DEBUG_CNTXTX1INGRESS_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX1INGRESS_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX1INGRESS_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX1INGRESS_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * Input buf used words + */ +#define BBH_RX_DEBUG_IBUW 0x218 + +/* Used words */ +#define DEBUG_IBUW_UW_SHIFT 0 +#define DEBUG_IBUW_UW_MASK 0x7 + + +/* + * Register - read-only + * + * Burst buf used words + */ +#define BBH_RX_DEBUG_BBUW 0x21c + +/* Used words */ +#define DEBUG_BBUW_UW_SHIFT 0 +#define DEBUG_BBUW_UW_MASK 0xf + + +/* + * Register - read-only + * + * Coherency FIFO used words + */ +#define BBH_RX_DEBUG_CFUW 0x220 + +/* Used words */ +#define DEBUG_CFUW_UW_SHIFT 0 +#define DEBUG_CFUW_UW_MASK 0x3f + + +/* + * Register - read-only + * + * The register reflects 2 ACK counters: + * SDMACONNECT + */ +#define BBH_RX_DEBUG_ACKCNT 0x224 + +/* SDMA ACK counter */ +#define DEBUG_ACKCNT_SDMA_SHIFT 0 +#define DEBUG_ACKCNT_SDMA_MASK 0x1f + +/* Connect ACK counter */ +#define DEBUG_ACKCNT_CONNECT_SHIFT 8 +#define DEBUG_ACKCNT_CONNECT_MASK 0x1f00 + + +/* + * Register - read-only + * + * The register 2 pending coherency counters: + * NormalExclusive + */ +#define BBH_RX_DEBUG_COHERENCYCNT 0x228 + +/* Normal */ +#define DEBUG_COHERENCYCNT_NORMAL_SHIFT 0 +#define DEBUG_COHERENCYCNT_NORMAL_MASK 0x1f + +/* Exclusive */ +#define DEBUG_COHERENCYCNT_EXCLUSIVE_SHIFT 8 +#define DEBUG_COHERENCYCNT_EXCLUSIVE_MASK 0x1f00 + + +/* + * Register - read-only + * + * selected debug vector + */ +#define BBH_RX_DEBUG_DBGVEC 0x22c + +/* selected debug vector */ +#define DEBUG_DBGVEC_DBGVEC_SHIFT 0 +#define DEBUG_DBGVEC_DBGVEC_MASK 0x1fffff + + +/* + * Register - read-only + * + * Upload FIFO used words + */ +#define BBH_RX_DEBUG_UFUW 0x230 + +/* Used words */ +#define DEBUG_UFUW_UW_SHIFT 0 +#define DEBUG_UFUW_UW_MASK 0x7 + + +/* + * Register - read-only + * + * This register holds 2 credit counters: + * NormalExclusive + */ +#define BBH_RX_DEBUG_CREDITCNT 0x234 + +/* Normal */ +#define DEBUG_CREDITCNT_NORMAL_SHIFT 0 +#define DEBUG_CREDITCNT_NORMAL_MASK 0x1f + +/* Exclusive */ +#define DEBUG_CREDITCNT_EXCLUSIVE_SHIFT 8 +#define DEBUG_CREDITCNT_EXCLUSIVE_MASK 0x1f00 + + +/* + * Register - read-only + * + * Number of used SDMA CDs + */ +#define BBH_RX_DEBUG_SDMACNT 0x238 + +/* Used CDs */ +#define DEBUG_SDMACNT_UCD_SHIFT 0 +#define DEBUG_SDMACNT_UCD_MASK 0x7f + + +/* + * Register - read-only + * + * CMD FIFO used words + */ +#define BBH_RX_DEBUG_CMFUW 0x23c + +/* Used words */ +#define DEBUG_CMFUW_UW_SHIFT 0 +#define DEBUG_CMFUW_UW_MASK 0x7 + + +/* + * Registers - is [ 0 => 15 ] - read-only + * + * The BBH RX hold a FIFO with 16 BN. + */ +#define BBH_RX_DEBUG_SBNFIFO(x) (0x240 + (x) * 0x4) + +/* BN */ +#define DEBUG_SBNFIFO_BNENTRY_SHIFT 0 +#define DEBUG_SBNFIFO_BNENTRY_MASK 0x3fff + +/* SBN is Valid */ +#define DEBUG_SBNFIFO_VALID_MASK 0x10000 + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * The BBH RX hold a FIFO with 8 command. + */ +#define BBH_RX_DEBUG_CMDFIFO(x) (0x280 + (x) * 0x4) + +/* CMD */ +#define DEBUG_CMDFIFO_CMDENTRY_SHIFT 0 +#define DEBUG_CMDFIFO_CMDENTRY_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * The BBH RX hold a recycle FIFO with up to 2 BN. + */ +#define BBH_RX_DEBUG_SBNRECYCLEFIFO(x) (0x290 + (x) * 0x4) + +/* BN */ +#define DEBUG_SBNRECYCLEFIFO_BNENTRY_SHIFT 0 +#define DEBUG_SBNRECYCLEFIFO_BNENTRY_MASK 0x3fff + +/* SBN is Valid */ +#define DEBUG_SBNRECYCLEFIFO_VALID_MASK 0x10000 + + +/* + * Register - read-only + * + * Read of 4 coherency counters: + * CD CMD sent (1 per flow)EOP ACK received (1 per flow) + */ +#define BBH_RX_DEBUG_COHERENCYCNT2 0x2a0 + +/* CD sent */ +#define DEBUG_COHERENCYCNT2_CDSENT_SHIFT 0 +#define DEBUG_COHERENCYCNT2_CDSENT_MASK 0x7f + +/* EOP ACK received */ +#define DEBUG_COHERENCYCNT2_ACKRECEIVED_SHIFT 8 +#define DEBUG_COHERENCYCNT2_ACKRECEIVED_MASK 0x7f00 + + +/* + * Register + * + * Information of the following: + * - Dispatcher drop due to coherency FIFO full- SDMA drop due to coherency + * method 2 counters over 63 (dec) + */ +#define BBH_RX_DEBUG_DROPSTATUS 0x2a4 + +/* + * Dispatcher drop due to coherency FIFO full. + * Writing 1 to this bit clears it +*/ +#define DEBUG_DROPSTATUS_DISPSTATUS_MASK 0x1 + +/* + * SDMA drop due to coherency method 2 counters over 63 (dec). + * Writing 1 to this bit clears it +*/ +#define DEBUG_DROPSTATUS_SDMASTATUS_MASK 0x2 + + +#endif /* ! XRDP_REGS_BBH_RX_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_bbh_tx.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_tx.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_bbh_tx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_tx.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,2073 @@ +#ifndef XRDP_REGS_BBH_TX_H_ +#define XRDP_REGS_BBH_TX_H_ + +/* relative to core */ +#define BBH_TX_OFFSET_0 0xd90000 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_1 0x0 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_2 0x2000 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_3 0x4000 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_4 0x6000 + +/* + * Register + * + * The BBH supports working with different MAC types. + * Each MAC requires different interface and features. + * This register defines the type of MAC the BBH works with. + */ +#define BBH_TX_COMMON_CFGS_MACTYPE 0x0 + +/* MAC type */ +#define COMMON_CFGS_MACTYPE_TYPE_SHIFT 0 +#define COMMON_CFGS_MACTYPE_TYPE_MASK 0x7 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define BBH_TX_COMMON_CFGS_BBCFG_1_TX 0x4 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_DMASRC_SHIFT 0 +#define COMMON_CFGS_BBCFG_1_TX_DMASRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_SDMASRC_SHIFT 8 +#define COMMON_CFGS_BBCFG_1_TX_SDMASRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_SBPMSRC_SHIFT 16 +#define COMMON_CFGS_BBCFG_1_TX_SBPMSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_FPMSRC_SHIFT 24 +#define COMMON_CFGS_BBCFG_1_TX_FPMSRC_MASK 0x3f000000 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define BBH_TX_COMMON_CFGS_BBCFG_2_TX 0x8 + +/* + * source id. + * This id is used to determine the route to the 1st (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_SHIFT 0 +#define COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the 2nd (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_SHIFT 8 +#define COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the Runner that is responsible + * for sending status messages (WAN only). +*/ +#define COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_SHIFT 16 +#define COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the Runner which is + * responsible for sending DBR/Ghost messages (WAN only). +*/ +#define COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_SHIFT 24 +#define COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_MASK 0x3f000000 + + +/* + * Register + * + * Configurations for determining the address to read from the DDR/PSRAm + */ +#define BBH_TX_COMMON_CFGS_DDRCFG_TX 0xc + +/* The data is arranged in the DDR in a fixed size buffers. */ +#define COMMON_CFGS_DDRCFG_TX_BUFSIZE_SHIFT 0 +#define COMMON_CFGS_DDRCFG_TX_BUFSIZE_MASK 0x7 + +/* The packet offset byte resulotion. */ +#define COMMON_CFGS_DDRCFG_TX_BYTERESUL_MASK 0x8 + +/* Static offset in 8-bytes resolution for non aggregated packets in DDR */ +#define COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_SHIFT 4 +#define COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_MASK 0x1ff0 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define COMMON_CFGS_DDRCFG_TX_HNSIZE0_SHIFT 16 +#define COMMON_CFGS_DDRCFG_TX_HNSIZE0_MASK 0x7f0000 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define COMMON_CFGS_DDRCFG_TX_HNSIZE1_SHIFT 24 +#define COMMON_CFGS_DDRCFG_TX_HNSIZE1_MASK 0x7f000000 + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner +b +: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_COMMON_CFGS_RNRCFG_1(x) (0x10 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define COMMON_CFGS_RNRCFG_1_TCONTADDR_SHIFT 0 +#define COMMON_CFGS_RNRCFG_1_TCONTADDR_MASK 0xffff + +/* + * Defines the SKB free address within the Runner address space. + * The address is in 8-bytes resolution. +*/ +#define COMMON_CFGS_RNRCFG_1_SKBADDR_SHIFT 16 +#define COMMON_CFGS_RNRCFG_1_SKBADDR_MASK 0xffff0000 + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_COMMON_CFGS_RNRCFG_2(x) (0x18 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define COMMON_CFGS_RNRCFG_2_PTRADDR_SHIFT 0 +#define COMMON_CFGS_RNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define COMMON_CFGS_RNRCFG_2_TASK_SHIFT 16 +#define COMMON_CFGS_RNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Register + * + * The BBH reads the packet data from the DDR in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the DMA + * memory space. + * The read descriptors are arranged in a predefined space in the DMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define BBH_TX_COMMON_CFGS_DMACFG_TX 0x20 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define COMMON_CFGS_DMACFG_TX_DESCBASE_SHIFT 0 +#define COMMON_CFGS_DMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define COMMON_CFGS_DMACFG_TX_DESCSIZE_SHIFT 6 +#define COMMON_CFGS_DMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define COMMON_CFGS_DMACFG_TX_MAXREQ_SHIFT 16 +#define COMMON_CFGS_DMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define COMMON_CFGS_DMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on read requests of a + * jumbo packet (>2K) +*/ +#define COMMON_CFGS_DMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * The BBH reads the packet data from the PSRAM in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the SDMA + * memory space. + * The read descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define BBH_TX_COMMON_CFGS_SDMACFG_TX 0x24 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define COMMON_CFGS_SDMACFG_TX_DESCBASE_SHIFT 0 +#define COMMON_CFGS_SDMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define COMMON_CFGS_SDMACFG_TX_DESCSIZE_SHIFT 6 +#define COMMON_CFGS_SDMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define COMMON_CFGS_SDMACFG_TX_MAXREQ_SHIFT 16 +#define COMMON_CFGS_SDMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define COMMON_CFGS_SDMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on Jumbo packets (>2k) + * read requests +*/ +#define COMMON_CFGS_SDMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * When packet transmission is done, the BBH releases the SBPM buffers. + * This register defines which release command is used: + * 1. + * Normal free with context2. + * Special free with context3. + * free without context + */ +#define BBH_TX_COMMON_CFGS_SBPMCFG 0x28 + +/* When this bit is enabled, the BBH will use free without context command. */ +#define COMMON_CFGS_SBPMCFG_FREENOCNTXT_MASK 0x1 + +/* + * When this bit is enabled, the BBH will use special free with context + * command. + * This bit is relevant only if free without context_en is configured to 0. +*/ +#define COMMON_CFGS_SBPMCFG_SPECIALFREE_MASK 0x2 + +/* maximum number of pending on the fly get next commands */ +#define COMMON_CFGS_SBPMCFG_MAXGN_SHIFT 8 +#define COMMON_CFGS_SBPMCFG_MAXGN_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define BBH_TX_COMMON_CFGS_DDRTMBASEL(x) (0x2c + (x) * 0x4) + +/* + * DDR TM base. + * The address is in bytes resolution. + * The address should be aligned to 128 bytes. +*/ +#define COMMON_CFGS_DDRTMBASEL_DDRTMBASE_SHIFT 0 +#define COMMON_CFGS_DDRTMBASEL_DDRTMBASE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define BBH_TX_COMMON_CFGS_DDRTMBASEH(x) (0x34 + (x) * 0x4) + +/* MSB of DDR TM base. */ +#define COMMON_CFGS_DDRTMBASEH_DDRTMBASE_SHIFT 0 +#define COMMON_CFGS_DDRTMBASEH_DDRTMBASE_MASK 0xff + + +/* + * Register + * + * The BBH orders data both from DDR and PSRAM. + * The returned data is stored in two FIFOs for reordering. + * The two FIFOs are implemented in a single RAM. + * This register defines the division of the RAM to two FIFOs. + */ +#define BBH_TX_COMMON_CFGS_DFIFOCTRL 0x3c + +/* + * The size of the PSRAM data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the PSRAM. +*/ +#define COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_SHIFT 0 +#define COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_MASK 0x3ff + +/* + * The size of the DDR data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the DDR. +*/ +#define COMMON_CFGS_DFIFOCTRL_DDRSIZE_SHIFT 10 +#define COMMON_CFGS_DFIFOCTRL_DDRSIZE_MASK 0xffc00 + +/* + * the base address of the PSRAM data FIFO in 8 bytes resolution. + * The DDR data FIFO base address is always 0. + * In case the whole RAM is to be dedicated to PSRAM data, the base should + * be 0 as well, and the DDR FIFO size should be configured to 0. +*/ +#define COMMON_CFGS_DFIFOCTRL_PSRAMBASE_SHIFT 20 +#define COMMON_CFGS_DFIFOCTRL_PSRAMBASE_MASK 0x3ff00000 + + +/* + * Register + * + * configurations related to different arbitration processes (ordering PDs, + * ordering data) + */ +#define BBH_TX_COMMON_CFGS_ARB_CFG 0x40 + +/* + * this configuration determines whether to give high priority to a current + * transmitting queue or not. +*/ +#define COMMON_CFGS_ARB_CFG_HIGHTRXQ_MASK 0x1 + + +/* + * Register + * + * override configuration for the route of one of the peripherals + * (DMA/SDMMA/FPM/SBPM?Runners) + */ +#define BBH_TX_COMMON_CFGS_BBROUTE 0x44 + +/* route address */ +#define COMMON_CFGS_BBROUTE_ROUTE_SHIFT 0 +#define COMMON_CFGS_BBROUTE_ROUTE_MASK 0x3ff + +/* destination source id */ +#define COMMON_CFGS_BBROUTE_DEST_SHIFT 10 +#define COMMON_CFGS_BBROUTE_DEST_MASK 0xfc00 + +/* enable */ +#define COMMON_CFGS_BBROUTE_EN_MASK 0x10000 + + +/* + * Registers - is [ 0 => 19 ] + * + * configuration which queue is managed by each of the two runners. + * Each register in this array configures 2 queues. + */ +#define BBH_TX_COMMON_CFGS_Q2RNR(x) (0x48 + (x) * 0x4) + +/* Q0 configuration */ +#define COMMON_CFGS_Q2RNR_Q0_MASK 0x1 + +/* Q1 configuration */ +#define COMMON_CFGS_Q2RNR_Q1_MASK 0x2 + + +/* + * Register + * + * which task in the runner to wake-up when requesting a PD for a certain + * q. + * This register holds the task number of the first 8 queues. + * For queues 8-40 (if they exist) the task that will be waking is the one + * appearing in the PD_RNR_CFG regs, depending on which runner this queue + * is associated with. + */ +#define BBH_TX_COMMON_CFGS_PERQTASK 0xa0 + +#define COMMON_CFGS_PERQTASK_TASKx_SHIFT(x) (4 * (x)) +#define COMMON_CFGS_PERQTASK_TASKx_MASK(x) (0xf << (4 * (x))) + + +/* + * Register + * + * This register enables reset of internal units (for possible WA + * purposes). + */ +#define BBH_TX_COMMON_CFGS_TXRSTCMD 0xb0 + +/* + * Writing 1 to this register will reset the segmentation context table. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_CNTXTRST_MASK 0x1 + +/* + * Writing 1 to this register will reset the PDs FIFOs. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_PDFIFORST_MASK 0x2 + +/* + * Writing 1 to this register will reset the DMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_DMAPTRRST_MASK 0x4 + +/* + * Writing 1 to this register will reset the SDMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_SDMAPTRRST_MASK 0x8 + +/* + * Writing 1 to this register will reset the BPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_BPMFIFORST_MASK 0x10 + +/* + * Writing 1 to this register will reset the SBPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_SBPMFIFORST_MASK 0x20 + +/* + * Writing 1 to this register will reset the order keeper FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_OKFIFORST_MASK 0x40 + +/* + * Writing 1 to this register will reset the DDR data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_DDRFIFORST_MASK 0x80 + +/* + * Writing 1 to this register will reset the SRAM data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_SRAMFIFORST_MASK 0x100 + +/* + * Writing 1 to this register will reset the SKB pointers. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_SKBPTRRST_MASK 0x200 + +/* + * Writing 1 to this register will reset the EPON status FIFOs (per queue + * 32 fifos). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_STSFIFORST_MASK 0x400 + +/* + * Writing 1 to this register will reset the EPON request FIFO (8 entries + * FIFO that holds the packet requests from the EPON MAC). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_REQFIFORST_MASK 0x800 + +/* + * Writing 1 to this register will reset the EPON/GPON MSG FIFOThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_MSGFIFORST_MASK 0x1000 + +/* + * Writing 1 to this register will reset the GET NEXT FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_GNXTFIFORST_MASK 0x2000 + +/* + * Writing 1 to this register will reset the FIRST BN FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_FBNFIFORST_MASK 0x4000 + + +/* + * Register + * + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. + */ +#define BBH_TX_COMMON_CFGS_DBGSEL 0xb4 + +/* + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. +*/ +#define COMMON_CFGS_DBGSEL_DBGSEL_SHIFT 0 +#define COMMON_CFGS_DBGSEL_DBGSEL_MASK 0x1f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define BBH_TX_COMMON_CFGS_CLK_GATE_CNTRL 0xb8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * general purpose register + */ +#define BBH_TX_COMMON_CFGS_GPR 0xbc + +/* general purpose register */ +#define COMMON_CFGS_GPR_GPR_SHIFT 0 +#define COMMON_CFGS_GPR_GPR_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 19 ] + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the Status FIFO, 1st BN FIFO and get-next FIFO is the same + * as the size of the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PDBASE(x) (0x100 + (x) * 0x4) + +/* The base of PD FIFO for queue 0. */ +#define WAN_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define WAN_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define WAN_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define WAN_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 19 ] + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PDSIZE(x) (0x150 + (x) * 0x4) + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define WAN_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define WAN_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define WAN_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define WAN_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 19 ] + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PDWKUPH(x) (0x200 + (x) * 0x4) + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define WAN_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define WAN_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define WAN_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 16 +#define WAN_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff0000 + + +/* + * Registers - is [ 0 => 19 ] + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PD_BYTE_TH(x) (0x250 + (x) * 0x4) + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define BBH_TX_WAN_CFGS_PD_BYTE_TH_EN 0x300 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define WAN_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define BBH_TX_WAN_CFGS_PDEMPTY 0x304 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define WAN_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define WAN_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner + * address. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_STSRNRCFG_1(x) (0x310 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define WAN_CFGS_STSRNRCFG_1_TCONTADDR_SHIFT 0 +#define WAN_CFGS_STSRNRCFG_1_TCONTADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_STSRNRCFG_2(x) (0x320 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define WAN_CFGS_STSRNRCFG_2_PTRADDR_SHIFT 0 +#define WAN_CFGS_STSRNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define WAN_CFGS_STSRNRCFG_2_TASK_SHIFT 16 +#define WAN_CFGS_STSRNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner + * address. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_MSGRNRCFG_1(x) (0x330 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define WAN_CFGS_MSGRNRCFG_1_TCONTADDR_SHIFT 0 +#define WAN_CFGS_MSGRNRCFG_1_TCONTADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_MSGRNRCFG_2(x) (0x340 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define WAN_CFGS_MSGRNRCFG_2_PTRADDR_SHIFT 0 +#define WAN_CFGS_MSGRNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define WAN_CFGS_MSGRNRCFG_2_TASK_SHIFT 16 +#define WAN_CFGS_MSGRNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Register + * + * Configurations related to EPON MAC. + */ +#define BBH_TX_WAN_CFGS_EPNCFG 0x350 + +/* + * In case of fatal length error - a mismatch between the request message + * from MAC and its relevant PD from Runner - the BBH can stop performing + * or continue regardless of the error. + * The error is also reflected to the SW in a counter. +*/ +#define WAN_CFGS_EPNCFG_STPLENERR_MASK 0x1 + +/* + * configures the width of the comparison of the packet ength. + * The length field in the EPON request interface is 11 bit, while it is 14 + * bit in the pd. + * If this bit is 0, then the comparison of the length will be between the + * 11 bit of the interface and the 11 lsb bits of the pd. + * If this ibt is 1, the comparison will be done between the 11 bits of the + * interface, concatenated with 3 zeros and the 14 bits of the pd +*/ +#define WAN_CFGS_EPNCFG_CMP_WIDTH_MASK 0x2 + +/* + * determines whether the BBH will consider the sts_full vector state when + * pushing STS messages to the MAC or not. + * The status fifos inside the MAC should never go full as they are mirror + * of the BBH PD FIFOs, but in cases where the MAC design behaves different + * than expected, we want the BBH to be able to operate as in 1G EPON mode +*/ +#define WAN_CFGS_EPNCFG_CONSIDERFULL_MASK 0x4 + +/* + * configuration whether to add 4 bytes per packet to the length received + * in the status message from the Runner so the MAC would know the actual + * length to be transmitted. +*/ +#define WAN_CFGS_EPNCFG_ADDCRC_MASK 0x8 + + +/* + * Register + * + * interface for SW to access the flow id to port-id table + */ +#define BBH_TX_WAN_CFGS_FLOW2PORT 0x354 + +/* + * write data. + * 15:0 - port-id - default is 0x000016 - regenerate CRC - enabled by + * default + * 17 - enc enable - disabled by default +*/ +#define WAN_CFGS_FLOW2PORT_WDATA_SHIFT 0 +#define WAN_CFGS_FLOW2PORT_WDATA_MASK 0x3ffff + +/* address */ +#define WAN_CFGS_FLOW2PORT_A_SHIFT 18 +#define WAN_CFGS_FLOW2PORT_A_MASK 0x3fc0000 + +/* rd/wr cmd */ +#define WAN_CFGS_FLOW2PORT_CMD_MASK 0x4000000 + + +/* + * Register + * + * The BBH is responsible for indicating the EPON MAC that the current + * packet that is being transmitted is a 1588 paacket. + * The BBH gets the 1588 parameters in the PD and forward it to the MAC. + * This register is used to enable this feature. + */ +#define BBH_TX_WAN_CFGS_TS 0x358 + +/* 1588 enable */ +#define WAN_CFGS_TS_EN_MASK 0x1 + + +/* + * Register + * + * VDSL max word lenrelevant only for VDSL BBH + */ +#define BBH_TX_WAN_CFGS_MAXWLEN 0x360 + +/* VDSL max word len */ +#define WAN_CFGS_MAXWLEN_MAXWLEN_SHIFT 0 +#define WAN_CFGS_MAXWLEN_MAXWLEN_MASK 0xffff + + +/* + * Register + * + * VDSL Flush indicationrelevant only for VDSL BBH + */ +#define BBH_TX_WAN_CFGS_FLUSH 0x364 + +/* VDSL flush */ +#define WAN_CFGS_FLUSH_FLUSH_SHIFT 0 +#define WAN_CFGS_FLUSH_FLUSH_MASK 0xffff + +/* soft reset */ +#define WAN_CFGS_FLUSH_SRST_N_MASK 0x80000000 + + +/* + * Register + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PDBASE 0x400 + +/* The base of PD FIFO for queue 0. */ +#define LAN_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define LAN_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define LAN_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define LAN_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PDSIZE 0x450 + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define LAN_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define LAN_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define LAN_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define LAN_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Register + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PDWKUPH 0x500 + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define LAN_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define LAN_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define LAN_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 8 +#define LAN_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff00 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PD_BYTE_TH 0x550 + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define BBH_TX_LAN_CFGS_PD_BYTE_TH_EN 0x600 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define LAN_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define BBH_TX_LAN_CFGS_PDEMPTY 0x604 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define LAN_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define LAN_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Register + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the XLMAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + */ +#define BBH_TX_LAN_CFGS_TXTHRESH 0x608 + +/* DDR Transmit threshold in 8 bytes resoltion */ +#define LAN_CFGS_TXTHRESH_DDRTHRESH_SHIFT 0 +#define LAN_CFGS_TXTHRESH_DDRTHRESH_MASK 0x1ff + +/* SRAM Transmit threshold in 8 bytes resoltion */ +#define LAN_CFGS_TXTHRESH_SRAMTHRESH_SHIFT 16 +#define LAN_CFGS_TXTHRESH_SRAMTHRESH_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that no traffic is about + * to arrive so the XLMAC may try to enter power saving mode. + * This register is used to enable this feature. + */ +#define BBH_TX_LAN_CFGS_EEE 0x60c + +/* enable bit */ +#define LAN_CFGS_EEE_EN_MASK 0x1 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that it should and + * calculate timestamp for the current packet that is being transmitted. + * The BBH gets the timestamping parameters in the PD and forward it to the + * XLMAC. + * This register is used to enable this feature. + */ +#define BBH_TX_LAN_CFGS_TS 0x610 + +/* enable bit */ +#define LAN_CFGS_TS_EN_MASK 0x1 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 6 queues. + * Each queue is dedicated to one MAC interface. + * A total of 48 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 48 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PDBASE(x) (0x700 + (x) * 0x4) + +/* The base of PD FIFO for queue 0. */ +#define UNIFIED_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define UNIFIED_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define UNIFIED_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define UNIFIED_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 6 queues. + * Each queue is dedicated to one MAC interface. + * A total of 48 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 48 + * PDs. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PDSIZE(x) (0x750 + (x) * 0x4) + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PDWKUPH(x) (0x800 + (x) * 0x4) + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 8 +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff00 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PD_BYTE_TH(x) (0x850 + (x) * 0x4) + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define BBH_TX_UNIFIED_CFGS_PD_BYTE_TH_EN 0x900 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define UNIFIED_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define BBH_TX_UNIFIED_CFGS_PDEMPTY 0x904 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define UNIFIED_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define UNIFIED_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Register + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the XLMAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + * This threshold is used by the non unified BBH. + * for unified BBH it should be set to 0. + */ +#define BBH_TX_UNIFIED_CFGS_GTXTHRESH 0x908 + +/* DDR Transmit threshold in 8 bytes resoltion */ +#define UNIFIED_CFGS_GTXTHRESH_DDRTHRESH_SHIFT 0 +#define UNIFIED_CFGS_GTXTHRESH_DDRTHRESH_MASK 0x1ff + +/* SRAM Transmit threshold in 8 bytes resoltion */ +#define UNIFIED_CFGS_GTXTHRESH_SRAMTHRESH_SHIFT 16 +#define UNIFIED_CFGS_GTXTHRESH_SRAMTHRESH_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that no traffic is about + * to arrive so the XLMAC may try to enter power saving mode. + * This register is used to enable this feature per MAC + */ +#define BBH_TX_UNIFIED_CFGS_EEE 0x90c + +/* enable bit */ +#define UNIFIED_CFGS_EEE_EN_SHIFT 0 +#define UNIFIED_CFGS_EEE_EN_MASK 0xff + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that it should and + * calculate timestamp for the current packet that is being transmitted. + * The BBH gets the timestamping parameters in the PD and forward it to the + * XLMAC. + * This register is used to enable this feature per MAC + */ +#define BBH_TX_UNIFIED_CFGS_TS 0x910 + +/* enable bit */ +#define UNIFIED_CFGS_TS_EN_SHIFT 0 +#define UNIFIED_CFGS_TS_EN_MASK 0xff + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FEBASE(x) (0x920 + (x) * 0x4) + +/* The base of FE FIFO for queue 0. */ +#define UNIFIED_CFGS_FEBASE_FIFOBASE0_SHIFT 0 +#define UNIFIED_CFGS_FEBASE_FIFOBASE0_MASK 0x7ff + +/* The base of FE FIFO for queue 1. */ +#define UNIFIED_CFGS_FEBASE_FIFOBASE1_SHIFT 16 +#define UNIFIED_CFGS_FEBASE_FIFOBASE1_MASK 0x7ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FESIZE(x) (0x940 + (x) * 0x4) + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FESIZE_FIFOSIZE0_SHIFT 0 +#define UNIFIED_CFGS_FESIZE_FIFOSIZE0_MASK 0x7ff + +/* + * The size of FE FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FESIZE_FIFOSIZE1_SHIFT 16 +#define UNIFIED_CFGS_FESIZE_FIFOSIZE1_MASK 0x7ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FEPDBASE(x) (0x960 + (x) * 0x4) + +/* The base of FE PD FIFO for queue 0. */ +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE0_SHIFT 0 +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE0_MASK 0xff + +/* The base of FE PD FIFO for queue 1. */ +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE1_SHIFT 16 +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE1_MASK 0xff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FEPDSIZE(x) (0x980 + (x) * 0x4) + +/* + * The size of FE PD FIFO for queue 0. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE0_SHIFT 0 +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE0_MASK 0xff + +/* + * The size of FE PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE1_SHIFT 16 +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE1_MASK 0xff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The unified BBH TX serves multiple MACs. + * The TX arbitration between these MACs is WRR. + * This register array determines the weight of each MAC. + * Each register in the array represents 2 MACs. + */ +#define BBH_TX_UNIFIED_CFGS_TXWRR(x) (0x9a0 + (x) * 0x4) + +/* weight of MAC0 */ +#define UNIFIED_CFGS_TXWRR_W0_SHIFT 0 +#define UNIFIED_CFGS_TXWRR_W0_MASK 0xf + +/* weight of MAC1 */ +#define UNIFIED_CFGS_TXWRR_W1_SHIFT 16 +#define UNIFIED_CFGS_TXWRR_W1_MASK 0xf0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the MAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + */ +#define BBH_TX_UNIFIED_CFGS_TXTHRESH(x) (0x9e0 + (x) * 0x4) + +/* Transmit threshold in 8 bytes resoltion for mac 0 */ +#define UNIFIED_CFGS_TXTHRESH_THRESH0_SHIFT 0 +#define UNIFIED_CFGS_TXTHRESH_THRESH0_MASK 0x1ff + +/* Transmit threshold in 8 bytes resolution for MAC1 */ +#define UNIFIED_CFGS_TXTHRESH_THRESH1_SHIFT 16 +#define UNIFIED_CFGS_TXTHRESH_THRESH1_MASK 0x1ff0000 + + +/* + * Register - read-only + * + * This counter counts the number of received PD for packets to be + * transmitted from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_SRAMPD 0xa00 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define DEBUG_COUNTERS_SRAMPD_SRAMPD_SHIFT 0 +#define DEBUG_COUNTERS_SRAMPD_SRAMPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received PDs for packets to be + * transmitted from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_DDRPD 0xa04 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define DEBUG_COUNTERS_DDRPD_DDRPD_SHIFT 0 +#define DEBUG_COUNTERS_DDRPD_DDRPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_PDDROP 0xa08 + +/* + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. +*/ +#define DEBUG_COUNTERS_PDDROP_PDDROP_SHIFT 0 +#define DEBUG_COUNTERS_PDDROP_PDDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of STS messages which were received from + * Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_STSCNT 0xa10 + +/* This counter counts the number of received status messages. */ +#define DEBUG_COUNTERS_STSCNT_STSCNT_SHIFT 0 +#define DEBUG_COUNTERS_STSCNT_STSCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of STS which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_STSDROP 0xa14 + +/* + * This counter counts the number of STS which were dropped due to PD FIFO + * full. +*/ +#define DEBUG_COUNTERS_STSDROP_STSDROP_SHIFT 0 +#define DEBUG_COUNTERS_STSDROP_STSDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG (DBR/Ghost) messages which were + * received from Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_MSGCNT 0xa18 + +/* This counter counts the number of received DBR/ghost messages. */ +#define DEBUG_COUNTERS_MSGCNT_MSGCNT_SHIFT 0 +#define DEBUG_COUNTERS_MSGCNT_MSGCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_MSGDROP 0xa1c + +/* + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. +*/ +#define DEBUG_COUNTERS_MSGDROP_MSGDROP_SHIFT 0 +#define DEBUG_COUNTERS_MSGDROP_MSGDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number Get next responses with a null BN. + * It counts the packets for all TCONTs together. + * This counter is cleared when read and freezes when maximum value is + * reached. + * This counter is relevant for Ethernet only. + */ +#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL 0xa20 + +/* This counter counts the number Get next responses with a null BN. */ +#define DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_SHIFT 0 +#define DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of packets that were flushed (bn was + * released without sending the data to the EPON MAC) due to flush request. + * The counter is global for all queues. + * The counter is read clear. + */ +#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS 0xa24 + +/* This counter counts the number of flushed packets */ +#define DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_SHIFT 0 +#define DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of times a length error (mismatch between + * a request from the MAC and a PD from the Runner) occured. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_LENERR 0xa28 + +/* This counter counts the number of times a length error occuered */ +#define DEBUG_COUNTERS_LENERR_LENERR_SHIFT 0 +#define DEBUG_COUNTERS_LENERR_LENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter Counts aggregation length error events. + * If one or more of the packets in an aggregated PD is shorter than 60 + * bytes, this counter will be incremented by 1. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR 0xa2c + +/* + * This counter counts the number of times an aggregation length error + * occuered +*/ +#define DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_SHIFT 0 +#define DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_SRAMPKT 0xa30 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define DEBUG_COUNTERS_SRAMPKT_SRAMPKT_SHIFT 0 +#define DEBUG_COUNTERS_SRAMPKT_SRAMPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_DDRPKT 0xa34 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define DEBUG_COUNTERS_DDRPKT_DDRPKT_SHIFT 0 +#define DEBUG_COUNTERS_DDRPKT_DDRPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the SRAM. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_SRAMBYTE 0xa38 + +/* This counter counts the number of transmitted bytes from the SRAM. */ +#define DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_SHIFT 0 +#define DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the DDR. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_DDRBYTE 0xa3c + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define DEBUG_COUNTERS_DDRBYTE_DDRBYTE_SHIFT 0 +#define DEBUG_COUNTERS_DDRBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Register + * + * writing to this register creates a rd_en pulse to the selected array the + * SW wants to access. + * Each bit in the register represents one of the arrays the SW can access. + * The address inside the array is determined in the previous register + * (sw_rd_address). + * When writing to this register the SW should assert only one bit. + * If more than one is asserted, The HW will return the value read from the + * lsb selected array. + */ +#define BBH_TX_DEBUG_COUNTERS_SWRDEN 0xa40 + +/* rd from the PD FIFO */ +#define DEBUG_COUNTERS_SWRDEN_PDSEL_MASK 0x1 + +/* rd from the PD valid array */ +#define DEBUG_COUNTERS_SWRDEN_PDVSEL_MASK 0x2 + +/* rd from the PD empty array */ +#define DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_MASK 0x4 + +/* rd from the PD Full array */ +#define DEBUG_COUNTERS_SWRDEN_PDFULLSEL_MASK 0x8 + +/* rd from the PD beliow empty array */ +#define DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_MASK 0x10 + +/* rd from the PD full for wakeup empty array */ +#define DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_MASK 0x20 + +/* rd from the first BN array */ +#define DEBUG_COUNTERS_SWRDEN_FBNSEL_MASK 0x40 + +/* rd from the first BN valid array */ +#define DEBUG_COUNTERS_SWRDEN_FBNVSEL_MASK 0x80 + +/* rd from the first BN empty array */ +#define DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_MASK 0x100 + +/* rd from the first BN full array */ +#define DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_MASK 0x200 + +/* rd from the first Get Next array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_MASK 0x400 + +/* rd from the get_next valid array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_MASK 0x800 + +/* rd from the get next empty array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_MASK 0x1000 + +/* rd from the get next full array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_MASK 0x2000 + +/* rd from the gpon context array */ +#define DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_MASK 0x4000 + +/* rd from the BPM FIFO */ +#define DEBUG_COUNTERS_SWRDEN_BPMSEL_MASK 0x8000 + +/* rd from the BPM FLUSH FIFO */ +#define DEBUG_COUNTERS_SWRDEN_BPMFSEL_MASK 0x10000 + +/* rd from the SBPM FIFO */ +#define DEBUG_COUNTERS_SWRDEN_SBPMSEL_MASK 0x20000 + +/* rd from the SBPM FLUSH FIFO */ +#define DEBUG_COUNTERS_SWRDEN_SBPMFSEL_MASK 0x40000 + +/* rd from the STS FIFO */ +#define DEBUG_COUNTERS_SWRDEN_STSSEL_MASK 0x80000 + +/* rd from the STS valid array */ +#define DEBUG_COUNTERS_SWRDEN_STSVSEL_MASK 0x100000 + +/* rd from the STS empty array */ +#define DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_MASK 0x200000 + +/* rd from the STS Full array */ +#define DEBUG_COUNTERS_SWRDEN_STSFULLSEL_MASK 0x400000 + +/* rd from the STS beliow empty array */ +#define DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_MASK 0x800000 + +/* rd from the STS full for wakeup empty array */ +#define DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_MASK 0x1000000 + +/* rd from the MSG FIFO */ +#define DEBUG_COUNTERS_SWRDEN_MSGSEL_MASK 0x2000000 + +/* rd from the msg valid array */ +#define DEBUG_COUNTERS_SWRDEN_MSGVSEL_MASK 0x4000000 + +/* rd from the epon request FIFO */ +#define DEBUG_COUNTERS_SWRDEN_EPNREQSEL_MASK 0x8000000 + +/* rd from the DATA FIFO (SRAM and DDR) */ +#define DEBUG_COUNTERS_SWRDEN_DATASEL_MASK 0x10000000 + +/* rd from the reorder FIFO */ +#define DEBUG_COUNTERS_SWRDEN_REORDERSEL_MASK 0x20000000 + +/* rd from the Timestamp Info FIFO */ +#define DEBUG_COUNTERS_SWRDEN_TSINFOSEL_MASK 0x40000000 + +/* rd from the MAC TX FIFO. */ +#define DEBUG_COUNTERS_SWRDEN_MACTXSEL_MASK 0x80000000 + + +/* + * Register + * + * the address inside the array the SW wants to read + */ +#define BBH_TX_DEBUG_COUNTERS_SWRDADDR 0xa44 + +/* The address inside the array the sw wants to read */ +#define DEBUG_COUNTERS_SWRDADDR_RDADDR_SHIFT 0 +#define DEBUG_COUNTERS_SWRDADDR_RDADDR_MASK 0x7ff + + +/* + * Register - read-only + * + * indirect memories and arrays read data + */ +#define BBH_TX_DEBUG_COUNTERS_SWRDDATA 0xa48 + +/* data */ +#define DEBUG_COUNTERS_SWRDDATA_DATA_SHIFT 0 +#define DEBUG_COUNTERS_SWRDDATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted packets through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT(x) (0xa50 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_SHIFT 0 +#define DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted bytes through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE(x) (0xa70 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_SHIFT 0 +#define DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * an array including all the debug vectors of the BBH TX. + * entries 30 and 31 are DSL debug. + */ +#define BBH_TX_DEBUG_COUNTERS_DBGOUTREG(x) (0xa90 + (x) * 0x4) + +/* Selected debug vector. */ +#define DEBUG_COUNTERS_DBGOUTREG_DBGVEC_SHIFT 0 +#define DEBUG_COUNTERS_DBGOUTREG_DBGVEC_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * 40 bit vector in which each bit represents if the segmentation SM is + * currently handling a PD of a certain TCONT. + * first address is for TCONTS [31: + * 0]second is for TCONTS [39: + * 32] + */ +#define BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION(x) (0xb20 + (x) * 0x4) + +/* in_segmentation indication */ +#define DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_SHIFT 0 +#define DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_BBH_TX_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_cnpl.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_cnpl.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_cnpl.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_cnpl.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,405 @@ +#ifndef XRDP_REGS_CNPL_H_ +#define XRDP_REGS_CNPL_H_ + +/* relative to core */ +#define CNPL_OFFSET_0 0xe48000 + +/* + * Registers - is [ 0 => 3071 ] + * + * mem_entry + */ +#define CNPL_MEMORY_DATA(x) (0x0 + (x) * 0x4) + +/* data */ +#define MEMORY_DATA_DATA_SHIFT 0 +#define MEMORY_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * location profiles + */ +#define CNPL_COUNTERS_CFGS_CN_LOC_PROF(x) (0x4000 + (x) * 0x4) + +/* + * counters group base address (in 8B resolution: + * 0 is 0x0, 1 is 0x8, . + * .. + * ) +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_BA_SHIFT 0 +#define COUNTERS_CFGS_CN_LOC_PROF_BA_MASK 0x7ff + +/* + * number of bytes that will hold each sub-counter. + * 0: + * 1B1: + * 2B2: + * 4B +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_CN0_BYTS_SHIFT 11 +#define COUNTERS_CFGS_CN_LOC_PROF_CN0_BYTS_MASK 0x1800 + +/* + * 1: + * each counter of the group is double sub-cntr0: + * each counter of the group is single +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_DOUBLLE_MASK 0x2000 + +/* + * 1: + * wrap at max value0: + * freeze at max value +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_WRAP_MASK 0x4000 + +/* + * 1: + * read clear when reading0: + * read no-clear when reading +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_CLR_MASK 0x8000 + + +/* + * Registers - is [ 0 => 1 ] + * + * 1st reg for location profiles + */ +#define CNPL_POLICERS_CFGS_PL_LOC_PROF0(x) (0x4100 + (x) * 0x4) + +/* + * buckets base address(in 8B resolution: + * 0 is 0x0, 1 is 0x8, . + * .. + * ) +*/ +#define POLICERS_CFGS_PL_LOC_PROF0_BK_BA_SHIFT 0 +#define POLICERS_CFGS_PL_LOC_PROF0_BK_BA_MASK 0x7ff + +/* + * params base address(in 8B resolution: + * 0 is 0x0, 1 is 0x8, . + * .. + * ) +*/ +#define POLICERS_CFGS_PL_LOC_PROF0_PA_BA_SHIFT 11 +#define POLICERS_CFGS_PL_LOC_PROF0_PA_BA_MASK 0x3ff800 + +/* + * 1: + * each policer is dual bucket0: + * each policer is single bucket +*/ +#define POLICERS_CFGS_PL_LOC_PROF0_DOUBLLE_MASK 0x400000 + + +/* + * Registers - is [ 0 => 1 ] + * + * 2nd reg for location profiles + */ +#define CNPL_POLICERS_CFGS_PL_LOC_PROF1(x) (0x4108 + (x) * 0x4) + +/* Index of 1st policer of the group. */ +#define POLICERS_CFGS_PL_LOC_PROF1_PL_ST_SHIFT 0 +#define POLICERS_CFGS_PL_LOC_PROF1_PL_ST_MASK 0xff + +/* Index of last policer of the group. */ +#define POLICERS_CFGS_PL_LOC_PROF1_PL_END_SHIFT 8 +#define POLICERS_CFGS_PL_LOC_PROF1_PL_END_MASK 0xff00 + + +/* + * Registers - is [ 0 => 2 ] + * + * calculation type register. + * 0: + * green, yellow, red1: + * red, yellow, green + */ +#define CNPL_POLICERS_CFGS_PL_CALC_TYPE(x) (0x4110 + (x) * 0x4) + +/* 32b vector for 32 policers */ +#define POLICERS_CFGS_PL_CALC_TYPE_VEC_SHIFT 0 +#define POLICERS_CFGS_PL_CALC_TYPE_VEC_MASK 0xffffffff + + +/* + * Register + * + * periodic update parameters + */ +#define CNPL_POLICERS_CFGS_PER_UP 0x4120 + +/* + * period in 8k cycles quanta (16. + * 384us for 500MHz) +*/ +#define POLICERS_CFGS_PER_UP_N_SHIFT 0 +#define POLICERS_CFGS_PER_UP_N_MASK 0xff + +/* + * 1: + * enable periodic update0: + * disable periodic update +*/ +#define POLICERS_CFGS_PER_UP_EN_MASK 0x100 + + +/* + * Register + * + * arbiter sw priorities + */ +#define CNPL_MISC_ARB_PRM 0x4200 + +/* + * 0: + * fixed lower1: + * rr with fw (default)2: + * fixed higher +*/ +#define MISC_ARB_PRM_SW_PRIO_SHIFT 0 +#define MISC_ARB_PRM_SW_PRIO_MASK 0x3 + + +/* + * Register + * + * command register + */ +#define CNPL_SW_IF_SW_CMD 0x4300 + +/* value of register */ +#define SW_IF_SW_CMD_VAL_SHIFT 0 +#define SW_IF_SW_CMD_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * status register + */ +#define CNPL_SW_IF_SW_STAT 0x4304 + +/* + * 0: + * DONE (ready)1: + * PROC(not ready) +*/ +#define SW_IF_SW_STAT_CN_RD_ST_MASK 0x1 + +/* + * 0: + * DONE (ready)1: + * PROC(not ready) +*/ +#define SW_IF_SW_STAT_PL_PLC_ST_MASK 0x2 + +/* + * 0: + * DONE (ready)1: + * PROC(not ready) +*/ +#define SW_IF_SW_STAT_PL_RD_ST_MASK 0x4 + + +/* + * Register - read-only + * + * rdata register - policer command result + */ +#define CNPL_SW_IF_SW_PL_RSLT 0x4310 + +/* red, yellow, green, non-active */ +#define SW_IF_SW_PL_RSLT_COL_SHIFT 30 +#define SW_IF_SW_PL_RSLT_COL_MASK 0xc0000000 + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * rdata register - policer read command result. + * 2 register for 2 buckets. + * If the group has only one bucket per policer - the policers are returned + * in the registers as a full line: + * the even policers are in reg0 (0,2,4,. + * .), and the odd are in reg1. + */ +#define CNPL_SW_IF_SW_PL_RD(x) (0x4314 + (x) * 0x4) + +/* value of read data */ +#define SW_IF_SW_PL_RD_RD_SHIFT 0 +#define SW_IF_SW_PL_RD_RD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * rdata register - counters read command result. + * 8 register for 32B batch. + * In read of single counter (burst size=1) the output will be in reg0 (the + * 32b where the counter is). + * In read of burst of counters, the counters are returned in the registers + * as a full line: + * addr[2: + * 0]=0 section of line in reg0,2,4,6 and the addr[2: + * 0]=4 are in reg1,3,5,7 (this means that if the start of burst is at + * addr[2: + * 0]=4 section of line, the wanted output should be from reg1). + */ +#define CNPL_SW_IF_SW_CNT_RD(x) (0x4320 + (x) * 0x4) + +/* value of read data */ +#define SW_IF_SW_CNT_RD_RD_SHIFT 0 +#define SW_IF_SW_CNT_RD_RD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 10 ] - read-only + * + * Number of commands that were processed by the engine. + */ +#define CNPL_PM_COUNTERS_ENG_CMDS(x) (0x4400 + (x) * 0x4) + +/* value */ +#define PM_COUNTERS_ENG_CMDS_VAL_SHIFT 0 +#define PM_COUNTERS_ENG_CMDS_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Number of wait cycles that the command waited until there was an idle + * engine. + */ +#define CNPL_PM_COUNTERS_CMD_WAIT(x) (0x4440 + (x) * 0x4) + +/* value */ +#define PM_COUNTERS_CMD_WAIT_VAL_SHIFT 0 +#define PM_COUNTERS_CMD_WAIT_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles from last read clear + */ +#define CNPL_PM_COUNTERS_TOT_CYC 0x4450 + +/* value */ +#define PM_COUNTERS_TOT_CYC_VAL_SHIFT 0 +#define PM_COUNTERS_TOT_CYC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles that there was gnt from main arbiter + */ +#define CNPL_PM_COUNTERS_GNT_CYC 0x4454 + +/* value */ +#define PM_COUNTERS_GNT_CYC_VAL_SHIFT 0 +#define PM_COUNTERS_GNT_CYC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles that there was gnt with request of more than one agent + */ +#define CNPL_PM_COUNTERS_ARB_CYC 0x4458 + +/* value */ +#define PM_COUNTERS_ARB_CYC_VAL_SHIFT 0 +#define PM_COUNTERS_ARB_CYC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * errors in policer update: + * the update period finished, and not all policers have been updated yet. + */ +#define CNPL_PM_COUNTERS_PL_UP_ERR 0x4460 + +/* value */ +#define PM_COUNTERS_PL_UP_ERR_VAL_SHIFT 0 +#define PM_COUNTERS_PL_UP_ERR_VAL_MASK 0xffffffff + + +/* + * Register + * + * bits rd_clr and wrap for the pm counters(above) + */ +#define CNPL_PM_COUNTERS_GEN_CFG 0x44fc + +/* read clear bit */ +#define PM_COUNTERS_GEN_CFG_RD_CLR_MASK 0x1 + +/* read clear bit */ +#define PM_COUNTERS_GEN_CFG_WRAP_MASK 0x2 + + +/* + * Register + * + * selects the debug vecore + */ +#define CNPL_DEBUG_DBGSEL 0x4500 + +/* selects th debug vector */ +#define DEBUG_DBGSEL_VS_SHIFT 0 +#define DEBUG_DBGSEL_VS_MASK 0x7f + + +/* + * Register - read-only + * + * the debug bus + */ +#define CNPL_DEBUG_DBGBUS 0x4504 + +/* debug vector */ +#define DEBUG_DBGBUS_VB_SHIFT 0 +#define DEBUG_DBGBUS_VB_MASK 0x1fffff + + +/* + * Register - read-only + * + * vector of all the requests of the clients (tx fifo not empty) + */ +#define CNPL_DEBUG_REQ_VEC 0x4508 + +/* still more commands for arbitration */ +#define DEBUG_REQ_VEC_REQ_SHIFT 0 +#define DEBUG_REQ_VEC_REQ_MASK 0x7f + + +/* + * Register - read-only + * + * which counter is updated, and where are we in the period cycle + */ +#define CNPL_DEBUG_POL_UP_ST 0x4510 + +/* number of iteration we are(each represent 8192 cycles) */ +#define DEBUG_POL_UP_ST_ITR_NUM_SHIFT 0 +#define DEBUG_POL_UP_ST_ITR_NUM_MASK 0xff + +/* + * number of policer now updated. + * (80 means we finished updated of all policers for this period) +*/ +#define DEBUG_POL_UP_ST_POL_NUM_SHIFT 8 +#define DEBUG_POL_UP_ST_POL_NUM_MASK 0xff00 + + +#endif /* ! XRDP_REGS_CNPL_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_dma.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dma.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_dma.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dma.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,404 @@ +#ifndef XRDP_REGS_DMA_H_ +#define XRDP_REGS_DMA_H_ + +/* relative to core */ +#define DMA_OFFSET(x) (0xd98800 + (x) * 0x400) + +/* + * Register + * + * Broadbus route override + */ +#define DMA_CONFIG_BBROUTEOVRD 0x0 + +/* destination ID */ +#define CONFIG_BBROUTEOVRD_DEST_SHIFT 0 +#define CONFIG_BBROUTEOVRD_DEST_MASK 0x3f + +/* the route to be used (override the default route) */ +#define CONFIG_BBROUTEOVRD_ROUTE_SHIFT 8 +#define CONFIG_BBROUTEOVRD_ROUTE_MASK 0x3ff00 + +/* override enable */ +#define CONFIG_BBROUTEOVRD_OVRD_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers defines the memory allocation for the + * peripherals, for upstream. + * The allocation is of number of 128byte buffers out of the total 48 + * buffers for both sdma and dma. + * The allocation is done by defining a only the number of allocated + * buffers. + * base address is calculated by HW, when base of peripheral 0 is 0. + * Note that the memory allocation should not contain wrap around. + * The number of allocated CDs is the same of data buffers. + */ +#define DMA_CONFIG_NUM_OF_WRITES(x) (0x4 + (x) * 0x4) + +/* the number of 128bytes buffers allocated to the peripheral. */ +#define CONFIG_NUM_OF_WRITES_NUMOFBUFF_SHIFT 0 +#define CONFIG_NUM_OF_WRITES_NUMOFBUFF_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers controls the number of read requests of each + * peripheral within the read requests RAM. + * total of 64 requests are divided between peripherals. + * Base address of peripheral 0 is 0, base of peripheral 1 is 0 + + * periph0_num_of_read_requests and so on. + */ +#define DMA_CONFIG_NUM_OF_READS(x) (0x24 + (x) * 0x4) + +/* number of read requests */ +#define CONFIG_NUM_OF_READS_RR_NUM_SHIFT 0 +#define CONFIG_NUM_OF_READS_RR_NUM_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * the in/out of urgent thresholds mark the number of write requests in the + * queue in which the peripherals priority is changed. + * The two thresholds should create hysteresis. + * The moving into urgent threshold must always be greater than the moving + * out of urgent threshold. + */ +#define DMA_CONFIG_U_THRESH(x) (0x44 + (x) * 0x4) + +/* moving into urgent threshold */ +#define CONFIG_U_THRESH_INTO_U_SHIFT 0 +#define CONFIG_U_THRESH_INTO_U_MASK 0x3f + +/* moving out ot urgent threshold */ +#define CONFIG_U_THRESH_OUT_OF_U_SHIFT 8 +#define CONFIG_U_THRESH_OUT_OF_U_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The arbitration between the requests of the different peripherals is + * done in two stages: + * 1. + * Strict priority - chooses the peripherals with the highest priority + * among all perpherals who have a request pending. + * 2. + * Weighted Round-Robin between all peripherals with the same priority. + * This array of registers allow configuration of the priority of each + * peripheral (both rx and tx) in the following manner: + * There are 4 levels of priorities, when each bit in the register + * represents a different level of priority. + * One should assert the relevant bit according to the desired priority + * -For the lowest - 0001For the highest - 1000 + */ +#define DMA_CONFIG_PRI(x) (0x64 + (x) * 0x4) + +/* priority of rx side (upload) of the peripheral */ +#define CONFIG_PRI_RXPRI_SHIFT 0 +#define CONFIG_PRI_RXPRI_MASK 0xf + +/* priority of tx side (download) of the peripheral */ +#define CONFIG_PRI_TXPRI_SHIFT 4 +#define CONFIG_PRI_TXPRI_MASK 0xf0 + + +/* + * Registers - is [ 0 => 7 ] + * + * Broadbus source address of the DMA peripherals. + * Register per peripheral (rx and tx). + * The source is used to determine the route address to the different + * peripherals. + */ +#define DMA_CONFIG_PERIPH_SOURCE(x) (0x84 + (x) * 0x4) + +/* bb source of rx side (upload) of the peripheral */ +#define CONFIG_PERIPH_SOURCE_RXSOURCE_SHIFT 0 +#define CONFIG_PERIPH_SOURCE_RXSOURCE_MASK 0x3f + +/* bb source of tx side (download) of the peripheral */ +#define CONFIG_PERIPH_SOURCE_TXSOURCE_SHIFT 8 +#define CONFIG_PERIPH_SOURCE_TXSOURCE_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The second phase of the arbitration between requests is weighted round + * robin between requests of peripherals with the same priority. + * This array of registers allow configurtion of the weight of each + * peripheral (rx and tx). + * The actual weight will be weight + 1, meaning configuration of 0 is + * actual weight of 1. + */ +#define DMA_CONFIG_WEIGHT(x) (0xa4 + (x) * 0x4) + +/* weight of rx side (upload) of the peripheral */ +#define CONFIG_WEIGHT_RXWEIGHT_SHIFT 0 +#define CONFIG_WEIGHT_RXWEIGHT_MASK 0x7 + +/* weight of tx side (download) of the peripheral */ +#define CONFIG_WEIGHT_TXWEIGHT_SHIFT 8 +#define CONFIG_WEIGHT_TXWEIGHT_MASK 0x700 + + +/* + * Register + * + * Resets the pointers of the peripherals FIFOs within the DMA. + * Bit per peripheral side (rx and tx). + * For rx side resets the data and CD FIFOs. + * For tx side resets the read requests FIFO. + */ +#define DMA_CONFIG_PTRRST 0xd0 + +/* + * vector in which each bit represents a peripheral. + * LSB represent RX peripherals and MSB represent TX peripherals. + * When asserted, the relevant FIFOS of the selected peripheral will be + * reset to zero +*/ +#define CONFIG_PTRRST_RSTVEC_SHIFT 0 +#define CONFIG_PTRRST_RSTVEC_MASK 0xffff + + +/* + * Register + * + * max number of on the fly read commands the DMA may issue to DDR before + * receiving any data. + */ +#define DMA_CONFIG_MAX_OTF 0xd4 + +/* max on the fly */ +#define CONFIG_MAX_OTF_MAX_SHIFT 0 +#define CONFIG_MAX_OTF_MAX_MASK 0x3f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define DMA_CONFIG_CLK_GATE_CNTRL 0xd8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define CONFIG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define CONFIG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * debug bus select + */ +#define DMA_CONFIG_DBG_SEL 0xe0 + +/* select */ +#define CONFIG_DBG_SEL_DBGSEL_SHIFT 0 +#define CONFIG_DBG_SEL_DBGSEL_MASK 0x3 + + +/* + * Register - read-only + * + * Each peripheral is represented in a bit on the not empty vector. + * LSB is for rx peripherals, MSB for tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * not empty. + * The not empty vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define DMA_DEBUG_NEMPTY 0x100 + +/* indication of the queue state */ +#define DEBUG_NEMPTY_NEMPTY_SHIFT 0 +#define DEBUG_NEMPTY_NEMPTY_MASK 0xffff + + +/* + * Register - read-only + * + * Each peripheral, a is represented in a bit on the urgent vector. + * 8 LSB are rx peripherlas, 8 MSB are tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * in urgent state. + * The urgent vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define DMA_DEBUG_URGNT 0x104 + +/* indication whether the queue is in urgent state or not */ +#define DEBUG_URGNT_URGNT_SHIFT 0 +#define DEBUG_URGNT_URGNT_MASK 0xffff + + +/* + * Register - read-only + * + * The decision of the dma schedule rand the next peripheral to be served, + * represented by its source address + */ +#define DMA_DEBUG_SELSRC 0x108 + +/* the next peripheral to be served by the dma */ +#define DEBUG_SELSRC_SEL_SRC_SHIFT 0 +#define DEBUG_SELSRC_SEL_SRC_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of write requests currently pending for each rx peripheral. + */ +#define DMA_DEBUG_REQ_CNT_RX(x) (0x110 + (x) * 0x4) + +/* the number of pending write requests */ +#define DEBUG_REQ_CNT_RX_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_RX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of read requestscurrently pending for each TX peripheral. + */ +#define DMA_DEBUG_REQ_CNT_TX(x) (0x130 + (x) * 0x4) + +/* the number of pending read requests */ +#define DEBUG_REQ_CNT_TX_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_TX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of write requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define DMA_DEBUG_REQ_CNT_RX_ACC(x) (0x150 + (x) * 0x4) + +/* the number of pending write requests */ +#define DEBUG_REQ_CNT_RX_ACC_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_RX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of read requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define DMA_DEBUG_REQ_CNT_TX_ACC(x) (0x170 + (x) * 0x4) + +/* the number of pending write requests */ +#define DEBUG_REQ_CNT_TX_ACC_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_TX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Register + * + * the address and cs of the ram the user wishes to read using the indirect + * access read mechanism. + */ +#define DMA_DEBUG_RDADD 0x200 + +/* address within the ram */ +#define DEBUG_RDADD_ADDRESS_SHIFT 0 +#define DEBUG_RDADD_ADDRESS_MASK 0x3ff + +/* chip select for write data ram */ +#define DEBUG_RDADD_DATACS_MASK 0x10000 + +/* chip select for chunk descriptors ram */ +#define DEBUG_RDADD_CDCS_MASK 0x20000 + +/* chip select for read requests ram */ +#define DEBUG_RDADD_RRCS_MASK 0x40000 + + +/* + * Register + * + * After determining the address and cs, the user should assert this bit + * for indicating that the address and cs are valid. + */ +#define DMA_DEBUG_RDVALID 0x204 + +/* indirect read request is valid */ +#define DEBUG_RDVALID_VALID_MASK 0x1 + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * The returned read data from the selected RAM. + * Array of 4 registers (128 bits total). + * The width of the different memories is as follows: + * write data - 128 bitschunk descriptors - 36 bitsread requests - 42 + * bitsread data - 64 bitsThe the memories with width smaller than 128, the + * data will appear in the first registers of the array, for example: + * data from the cd RAM will appear in - {reg1[5: + * 0], reg0[31: + * 0]}. + */ +#define DMA_DEBUG_RDDATA(x) (0x208 + (x) * 0x4) + +/* read data from ram */ +#define DEBUG_RDDATA_DATA_SHIFT 0 +#define DEBUG_RDDATA_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * When assertd indicats that the data in the previous array is valid. + * Willremain asserted until the user deasserts the valid bit in regiser + * RDVALID. + */ +#define DMA_DEBUG_RDDATARDY 0x218 + +/* read data ready */ +#define DEBUG_RDDATARDY_READY_MASK 0x1 + + +#endif /* ! XRDP_REGS_DMA_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_dqm.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dqm.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_dqm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dqm.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,424 @@ +#ifndef XRDP_REGS_DQM_H_ +#define XRDP_REGS_DQM_H_ + +/* relative to core */ +#define DQM_OFFSET_0 0x180034 + +/* + * Register + * + * Maximum number of entries in words for all the queues. + */ +#define DQM_MAX_ENTRIES_WORDS 0x0 + +/* + * Represents the maximum number of entries the queue can hold (in words). + * This is a global settings. +*/ +#define MAX_ENTRIES_WORDS_MAX_SHIFT 0 +#define MAX_ENTRIES_WORDS_MAX_MASK 0x7ffff + + +/* + * Register + * + * FPM Address Register + */ +#define DQM_FPM_ADDR 0x18 + +/* + * This is the FPM address to be used by components in this module. + * The same address is used to alloc and free a token in the FPM. +*/ +#define FPM_ADDR_FPMADDRESS_SHIFT 0 +#define FPM_ADDR_FPMADDRESS_MASK 0xffffffff + + +/* + * Register + * + * DQMOL Interrupt Status Register. + */ +#define DQM_IRQ_STS 0x1c + +/* + * DQMOL Pushing a Full Queue IRQ Status (RW1C). + * This is a sticky high bit and needs to be cleared by writing to it. +*/ +#define IRQ_STS_PUSHFULLQ_MASK 0x2 + +/* + * DQMOL Popping an Empty Queue IRQ Status (RW1C). + * This is a sticky high bit and needs to be cleared by writing to it. +*/ +#define IRQ_STS_POPEMPTYQ_MASK 0x1 + + +/* + * Register + * + * DQMOL Interrupt Mask Register. + */ +#define DQM_IRQ_MSK 0x20 + +/* DQMOL Pushing a Full Queue IRQ Mask */ +#define IRQ_MSK_PUSHFULLQ_MASK 0x2 + +/* DQMOL Popping an Empty Queue IRQ Mask */ +#define IRQ_MSK_POPEMPTYQ_MASK 0x1 + + +/* + * Register + * + * Token buffer size. + */ +#define DQM_BUF_SIZE 0x24 + +/* + * Buffer Size. + * This is an encoded value. + * 0 => 256 byte buffer, 1 => 512 byte buffer, 2 => 1024 byte buffer, 3 => + * 2048 byte buffer. +*/ +#define BUF_SIZE_POOL_0_SIZE_SHIFT 0 +#define BUF_SIZE_POOL_0_SIZE_MASK 0x3 + + +/* + * Register + * + * Token buffer base address + */ +#define DQM_BUF_BASE 0x28 + +/* + * Buffer base address for bits[39: + * 8]. + * Address bits [7: + * 0] is always assumed to be 0. +*/ +#define BUF_BASE_BASE_SHIFT 0 +#define BUF_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * Shows the number of tokens used by DQMOL + */ +#define DQM_TOKENS_USED 0x30 + +/* + * Represents the current number of tokens used by the queue data + * structure. + * This count does not include tokens that are prefetched. +*/ +#define TOKENS_USED_COUNT_SHIFT 0 +#define TOKENS_USED_COUNT_MASK 0xffffffff + + +/* + * Register + * + * counter for number of pushed transactions + */ +#define DQM_NUM_PUSHED 0x34 + +/* Represents the current number of pushed transaction across all queues */ +#define NUM_PUSHED_COUNT_SHIFT 0 +#define NUM_PUSHED_COUNT_MASK 0xffffffff + + +/* + * Register + * + * counter for number of popped transactions + */ +#define DQM_NUM_POPPED 0x38 + +/* Represents the current number of popped transaction across all queues */ +#define NUM_POPPED_COUNT_SHIFT 0 +#define NUM_POPPED_COUNT_MASK 0xffffffff + + +/* + * Register + * + * MUX Select for Diags + */ +#define DQM_DIAG_SEL 0x3c + +/* MUX Select for routing diag data to the Diag Data Register */ +#define DIAG_SEL_SEL_SHIFT 0 +#define DIAG_SEL_SEL_MASK 0xff + + +/* + * Register - read-only + * + */ +#define DQM_DIAG_DATA 0x40 + +/* data presented as diag readback data. */ +#define DIAG_DATA_DATA_SHIFT 0 +#define DIAG_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * DQMOL Interrupt Test Register. + */ +#define DQM_IRQ_TST 0x44 + +/* Test the PushFullQ irq */ +#define IRQ_TST_PUSHFULLQTST_MASK 0x2 + +/* Test the PopEmptyQ irq */ +#define IRQ_TST_POPEMPTYQTST_MASK 0x1 + + +/* + * Register - read-only + * + * content from prefetch token fifo + */ +#define DQM_TOKEN_FIFO_STATUS 0x48 + +/* token fifo full */ +#define TOKEN_FIFO_STATUS_FULL_MASK 0x20000 + +/* token fifo empty */ +#define TOKEN_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* token fifo depth count */ +#define TOKEN_FIFO_STATUS_LEVEL_SHIFT 8 +#define TOKEN_FIFO_STATUS_LEVEL_MASK 0x1f00 + +/* token fifo read pointer */ +#define TOKEN_FIFO_STATUS_RD_LOC_SHIFT 0 +#define TOKEN_FIFO_STATUS_RD_LOC_MASK 0xf + + +/* + * Registers - is [ 0 => 15 ] - read-only + * + * content from prefetch token fifo + */ +#define DQM_TOKEN_FIFO(x) (0x4c + (x) * 0x4) + +/* Token value read from the token fifo */ +#define TOKEN_FIFO_TOKEN_SHIFT 0 +#define TOKEN_FIFO_TOKEN_MASK 0xffffffff + + +/* + * Register + * + * counter for number of popped with no commit transactions + */ +#define DQM_NUM_POPPED_NO_COMMIT 0x8c + +/* + * Represents the current number of popped with no-commit transaction + * across all queues +*/ +#define NUM_POPPED_NO_COMMIT_COUNT_SHIFT 0 +#define NUM_POPPED_NO_COMMIT_COUNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * Number of token unused space available on queue. + * This register is available on the DSPRAM read bus. + */ +#define DQM_STATUS(x) (0x7cc + (x) * 0x4) + +/* Queue data for the current Line is stored locally in the QSM. */ +#define STATUS_CURR_LINE_DATA_IS_LOCAL_MASK 0x80000000 + +/* Queue data for the next Line is stored locally in the QSM. */ +#define STATUS_NEXT_LINE_DATA_IS_LOCAL_MASK 0x40000000 + +/* Queue Available Unused Token Space (in words). */ +#define STATUS_Q_AVL_TKN_SPACE_SHIFT 0 +#define STATUS_Q_AVL_TKN_SPACE_MASK 0x7ffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + */ +#define DQM_HEAD_PTR(x) (0xfcc + (x) * 0x8) + +/* + * Queue Head Pointer (in words). + * This is a read-only field and will reset to 0 whenever CNTRL_CFGB is + * programmed +*/ +#define HEAD_PTR_Q_HEAD_PTR_SHIFT 0 +#define HEAD_PTR_Q_HEAD_PTR_MASK 0xfffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + */ +#define DQM_TAIL_PTR(x) (0xfd0 + (x) * 0x8) + +/* + * Queue Tail Pointer (in words). + * This is a read-only field and will reset to 0 whenever CNTRL_CFGB is + * programmed +*/ +#define TAIL_PTR_Q_TAIL_PTR_SHIFT 0 +#define TAIL_PTR_Q_TAIL_PTR_MASK 0xfffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * Number of token space available in Queue + */ +#define DQM_DQMOL_SIZE(x) (0x1fcc + (x) * 0x20) + +/* Maximum number of entries allotted to the queue before it's full */ +#define DQMOL_SIZE_MAX_ENTRIES_SHIFT 4 +#define DQMOL_SIZE_MAX_ENTRIES_MASK 0x7ffff0 + +/* + * When set, this puts the DQM OL queue into legacy DQM mode, there's no + * offloading of data. + * All queue data are stored in the QSM memory. +*/ +#define DQMOL_SIZE_Q_DISABLE_OFFLOAD_MASK 0x8 + +/* + * Queue Token Size (in words). + * This is a base-0 value. + * A value of 0 means the token is 1 word long. + * A value of 1 means the token is 2 words long. + * This maxes out at a value of 3 to mean that a token is 4 words long. +*/ +#define DQMOL_SIZE_Q_TKN_SIZE_SHIFT 0 +#define DQMOL_SIZE_Q_TKN_SIZE_MASK 0x3 + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * Starting queue address and size of memory space + */ +#define DQM_DQMOL_CFGA(x) (0x1fd0 + (x) * 0x20) + +/* + * Queue Memory Size (in words). + * It is required that the Queue Memory Size be whole multiple of the + * QUEUE_x_CNTRL_SIZE. + * Q_TKN_SIZE. + * For example, if Q_TKN_SIZE == 2 (which represents a 3 word token), then + * the Queue Memory Size must be 3, 6, 9, 12, etc. +*/ +#define DQMOL_CFGA_Q_SIZE_SHIFT 16 +#define DQMOL_CFGA_Q_SIZE_MASK 0xffff0000 + +/* + * Queue Start Address (word addr). + * The hardware takes this word address and adds the base address of the + * Queue Shared Memory (0x4000 byte addr) to form the physical address for + * the Queue. +*/ +#define DQMOL_CFGA_Q_START_ADDR_SHIFT 0 +#define DQMOL_CFGA_Q_START_ADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Number of tokens and low watermark setting + */ +#define DQM_DQMOL_CFGB(x) (0x1fd4 + (x) * 0x20) + +/* When set, the DQMOL is enabled and ready for use. */ +#define DQMOL_CFGB_ENABLE_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_PUSHTOKEN(x) (0x1fdc + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_PUSHTOKEN_TOKEN_SHIFT 0 +#define DQMOL_PUSHTOKEN_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_PUSHTOKENNEXT(x) (0x1fe0 + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_PUSHTOKENNEXT_TOKEN_SHIFT 0 +#define DQMOL_PUSHTOKENNEXT_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_POPTOKEN(x) (0x1fe4 + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_POPTOKEN_TOKEN_SHIFT 0 +#define DQMOL_POPTOKEN_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_POPTOKENNEXT(x) (0x1fe8 + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_POPTOKENNEXT_TOKEN_SHIFT 0 +#define DQMOL_POPTOKENNEXT_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15360 ] + * + * Note that in the UTP has 48KB of memory space. + * With DFAP/GFAP/DTP,there are only 16KB of shared memory space. + * The entirememory space is carved out here as a placeholder in the + * DFAP/GFAP/DTP's case. + * QSM memory + */ +#define DQM_QueueSharedMem_qsmdata(x) (0x1ffcc + (x) * 0x4) + +/* data */ +#define QueueSharedMem_qsmdata_DATA_SHIFT 0 +#define QueueSharedMem_qsmdata_DATA_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_DQM_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_dsptchr.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dsptchr.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_dsptchr.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dsptchr.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,2288 @@ +#ifndef XRDP_REGS_DSPTCHR_H_ +#define XRDP_REGS_DSPTCHR_H_ + +/* relative to core */ +#define DSPTCHR_OFFSET_0 0xd80000 + +/* + * Register + * + * Enable of dispatcher reorder + */ +#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG 0x0 + +/* Enable dispatcher reorder block */ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_EN_MASK 0x1 + +/* Dispatcher reorder block is RDY */ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_MASK 0x100 + +/* + * Enables parallel operation of Re-Order scheduler to Re-Order SM. + * Reduces Re-Order cycle from 16 clocks to 7. +*/ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_MASK 0x10000 + +/* Enable per Q Egress congestion monitoring */ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_MASK 0x20000 + +/* + * Enables Enhanced performance mode of Dispatcher Load balancing and + * Dispatcher SM. + * This allows Disptach of PD to RNR instead of every 14 clocks, every 11 + * clocks. +*/ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_DSPTCHR_PER_ENH_POD_MASK 0x40000 + + +/* + * Register + * + * Enable control for each VIQ/VEQ + */ +#define DSPTCHR_REORDER_CFG_VQ_EN 0x4 + +/* Enable Virtual Q control - 32 bit vector. */ +#define REORDER_CFG_VQ_EN_EN_SHIFT 0 +#define REORDER_CFG_VQ_EN_EN_MASK 0xffffffff + + +/* + * Register + * + * Allow override of a specific BB destination with a new Route ADDR + */ +#define DSPTCHR_REORDER_CFG_BB_CFG 0x8 + +/* Source ID - Dispatcher */ +#define REORDER_CFG_BB_CFG_SRC_ID_SHIFT 0 +#define REORDER_CFG_BB_CFG_SRC_ID_MASK 0x3f + +/* Enable dispatcher reorder block */ +#define REORDER_CFG_BB_CFG_DST_ID_OVRIDE_SHIFT 8 +#define REORDER_CFG_BB_CFG_DST_ID_OVRIDE_MASK 0x3f00 + +/* Use this route address instead of pre-configured */ +#define REORDER_CFG_BB_CFG_ROUTE_OVRIDE_SHIFT 16 +#define REORDER_CFG_BB_CFG_ROUTE_OVRIDE_MASK 0x3ff0000 + +/* Enable dispatcher reorder block */ +#define REORDER_CFG_BB_CFG_OVRIDE_EN_MASK 0x10000000 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL 0xc + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 31 ] + * + * Ingress Queues congestion state. + */ +#define DSPTCHR_CONGESTION_INGRS_CONGSTN(x) (0x80 + (x) * 0x4) + +/* First Level congestion threshold. */ +#define CONGESTION_INGRS_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_INGRS_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_INGRS_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_INGRS_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_INGRS_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_INGRS_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 31 ] + * + * Egress Queues congestion state per Q. + */ +#define DSPTCHR_CONGESTION_EGRS_CONGSTN(x) (0x100 + (x) * 0x4) + +/* First Level congestion threshold. */ +#define CONGESTION_EGRS_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_EGRS_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_EGRS_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_EGRS_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_EGRS_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_EGRS_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Register + * + * Egress congestion states (Total Count) + */ +#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN 0x180 + +/* First Level congestion threshold. */ +#define CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Register + * + * Congestion levels of FLL state. + * Once no mode BDs are availabe congestion indication will be risen on all + * PDs. + */ +#define DSPTCHR_CONGESTION_GLBL_CONGSTN 0x184 + +/* First Level congestion threshold. */ +#define CONGESTION_GLBL_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_GLBL_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_GLBL_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_GLBL_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_GLBL_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_GLBL_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Register - read-only + * + * This register reflects the current congestion levels in the dispatcher. + */ +#define DSPTCHR_CONGESTION_CONGSTN_STATUS 0x188 + +/* Global congestion levels (according to FLL buffer availability) */ +#define CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_SHIFT 0 +#define CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_MASK 0x3 + +/* Global Egress congestion levels */ +#define CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_SHIFT 8 +#define CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_MASK 0x300 + +/* SBPM congestion levels according to SPBM messages */ +#define CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_SHIFT 16 +#define CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_MASK 0x30000 + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW 0x18c + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH 0x190 + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW 0x194 + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH 0x198 + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Ingress size + */ +#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE(x) (0x280 + (x) * 0x4) + +/* Common number of buffers allocated to this Q. */ +#define INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_SHIFT 0 +#define INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_MASK 0x3ff + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Ingress Limits + */ +#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS(x) (0x300 + (x) * 0x4) + +/* + * Maximum number of buffers allowed to be allocated to the specific VIQ + * from the common Pool +*/ +#define INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_SHIFT 0 +#define INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_MASK 0x3ff + +/* + * Maximum number of buffers allowed to be allocated to the specific VIQ + * from the guaranteed Pool +*/ +#define INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_SHIFT 10 +#define INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_MASK 0xffc00 + +/* + * Holds the value of the the accumulated credits. + * this is sent to the BBH/RNR. + * BBH disregards the value. + * RNR uses it to to calculate the amount of available credits. +*/ +#define INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_SHIFT 20 +#define INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_MASK 0xfff00000 + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Coherency counter + */ +#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY(x) (0x380 + (x) * 0x4) + +/* + * Coherency counter value. + * BBH sends a coherency message per PD. + * Coherency messages are counted and only if there is at least 1 coherency + * message can a PD be forwarded to the RNR for processing. +*/ +#define INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_SHIFT 0 +#define INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_MASK 0x3ff + +/* + * Enable coherency counting. + * In case RNR is allocated to a specific VIQ it will not send coherency + * messages so there is no need to take them into consideration during PD + * dispatch +*/ +#define INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_MASK 0x400 + +/* Reserve */ +#define INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_SHIFT 11 +#define INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_MASK 0xfffff800 + + +/* + * Registers - is [ 0 => 31 ] + * + * Configuration for each Q including BB_ID, Target address, valid + */ +#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG(x) (0x400 + (x) * 0x4) + +/* + * BroadBud ID: + * To which BroadBud agent (RNR/BBH) is the current Q associated with +*/ +#define QUEUE_MAPPING_CRDT_CFG_BB_ID_SHIFT 0 +#define QUEUE_MAPPING_CRDT_CFG_BB_ID_MASK 0xff + +/* + * Target address within the BB agent where the credit message should be + * written to. + * In case of RNR: + * 27:16 - Ram address + * 31:28 - Task number to wakeup +*/ +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_SHIFT 16 +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_MASK 0xffff0000 + +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_NORMAL 2 +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_EXCL 2 + +/* + * Registers - is [ 0 => 15 ] + * + * Dispatched address will be calculated ADD= BASE_ADD + (TASK_NUM x OFFSET) + * + */ +#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD(x) (0x480 + (x) * 0x4) + +/* Base address within each RNR, 8 bytes unit (1 == 0x8) */ +#define QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_SHIFT 0 +#define QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_MASK 0xffff + +/* + * OFFSET address, in conjunction with base address for each task there + * will be a different address to where to send the PDADD = BASE_ADD + + * (OFFSET_ADD x TASK)PD size is 128bits + * + * 8 bytes unit +*/ +#define QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_SHIFT 16 +#define QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_MASK 0xffff0000 + + +/* + * Register + * + * What is the destination of each VIQ. + * to Dispatcher and from there to Processing RNR or Reorder and from there + * to the QM + */ +#define DSPTCHR_QUEUE_MAPPING_Q_DEST 0x4c0 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q0_MASK 0x1 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q1_MASK 0x2 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q2_MASK 0x4 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q3_MASK 0x8 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q4_MASK 0x10 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q5_MASK 0x20 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q6_MASK 0x40 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q7_MASK 0x80 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q8_MASK 0x100 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q9_MASK 0x200 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q10_MASK 0x400 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q11_MASK 0x800 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q12_MASK 0x1000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q13_MASK 0x2000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q14_MASK 0x4000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q15_MASK 0x8000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q16_MASK 0x10000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q17_MASK 0x20000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q18_MASK 0x40000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q19_MASK 0x80000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q20_MASK 0x100000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q21_MASK 0x200000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q22_MASK 0x400000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q23_MASK 0x800000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q24_MASK 0x1000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q25_MASK 0x2000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q26_MASK 0x4000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q27_MASK 0x8000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q28_MASK 0x10000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q29_MASK 0x20000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q30_MASK 0x40000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q31_MASK 0x80000000 + + +/* + * Register + * + * common pool max size + */ +#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT 0x4d0 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_CMN_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_CMN_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * common pool size + */ +#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE 0x4d4 + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * Guaranteed pool max size + */ +#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT 0x4d8 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * Guaranteed pool size + */ +#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE 0x4dc + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * Multi Cast pool max size + */ +#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT 0x4e0 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * Multi Cast pool size + */ +#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE 0x4e4 + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * This counter counts the amount of buffers taken by runner for MultiCast + * purposes (or any other the requires adding new PDs to a Virtual Egress + * Queue - VEQ + */ +#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT 0x4e8 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_RNR_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_RNR_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * This counter counts the amount of buffers taken by runner for MultiCast + * purposes (or any other the requires adding new PDs to a Virtual Egress + * Qeueu - VEQ) + */ +#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE 0x4ec + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * This counter counts how many buffers are currenly being handled by all + * RNRs + */ +#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE 0x4f0 + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Registers - is [ 0 => 63 ] + * + * Address 0 -> 255:224 + * Address 4 -> 223:192 + * Address 8 -> 191:160 + * Address C -> 159:128 + * Address 10 -> 127:96 + * Address 14 -> 95:64 + * Address 18 -> 63:32 + * Address 1C -> 31:0 + * + * 8 RG x 8 Regs per RG = 64 registers + */ +#define DSPTCHR_MASK_MSK_TSK_255_0(x) (0x500 + (x) * 0x4) + +/* MASK */ +#define MASK_MSK_TSK_255_0_MASK_SHIFT 0 +#define MASK_MSK_TSK_255_0_MASK_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] + * + * Queue Mask: + * Per RNR group holds a vector of which tasks are related to the group + */ +#define DSPTCHR_MASK_MSK_Q(x) (0x600 + (x) * 0x4) + +/* MASK */ +#define MASK_MSK_Q_MASK_SHIFT 0 +#define MASK_MSK_Q_MASK_MASK 0xffffffff + + +/* + * Register + * + * Describes which VEQ are part of the Delay Q group. + */ +#define DSPTCHR_MASK_DLY_Q 0x620 + +/* MASK */ +#define MASK_DLY_Q_MASK_SHIFT 0 +#define MASK_DLY_Q_MASK_MASK 0xffffffff + + +/* + * Register + * + * Describes which VEQ are part of the Non-Delay Q group. + */ +#define DSPTCHR_MASK_NON_DLY_Q 0x624 + +/* MASK */ +#define MASK_NON_DLY_Q_MASK_SHIFT 0 +#define MASK_NON_DLY_Q_MASK_MASK 0xffffffff + + +/* + * Register + * + * These registers hold the available credit for the Re-Order to sent PDs + * to the QM via Delay Q. + */ +#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT 0x630 + +/* + * The amount of free credits the re-order can utilize to send PDs to the + * QM +*/ +#define EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_SHIFT 0 +#define EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_MASK 0xff + + +/* + * Register + * + * These registers hold the available credit for the Re-Order to sent PDs + * to the QM via Non-Delay Q. + */ +#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT 0x634 + +/* + * The amount of free credits the re-order can utilize to send PDs to the + * QM +*/ +#define EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_SHIFT 0 +#define EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_MASK 0xff + + +/* + * Register + * + * Size of all egress queues. + * affected from PDs sent to dispatch and from multicast connect + */ +#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE 0x638 + +/* + * Accumulates all buffers that are marked as egress (after dispatch and + * before sending to QM) +*/ +#define EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_SHIFT 0 +#define EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_MASK 0x3ff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Size of all egress queues. + * affected from PDs sent to dispatch and from multicast connect + */ +#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE(x) (0x680 + (x) * 0x4) + +/* + * Accumulates all buffers that are marked as egress (after dispatch and + * before sending to QM) +*/ +#define EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_SHIFT 0 +#define EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_MASK 0x3ff + + +/* + * Register + * + * Bit per queue, wakeup request from RNR to a specific Q. + * Once a wakeup request message is sent to dsptchr it will be latched + * until the amount of credits pass a threshold + */ +#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ 0x770 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q0_MASK 0x1 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q1_MASK 0x2 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q2_MASK 0x4 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q3_MASK 0x8 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q4_MASK 0x10 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q5_MASK 0x20 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q6_MASK 0x40 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q7_MASK 0x80 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q8_MASK 0x100 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q9_MASK 0x200 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q10_MASK 0x400 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q11_MASK 0x800 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q12_MASK 0x1000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q13_MASK 0x2000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q14_MASK 0x4000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q15_MASK 0x8000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q16_MASK 0x10000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q17_MASK 0x20000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q18_MASK 0x40000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q19_MASK 0x80000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q20_MASK 0x100000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q21_MASK 0x200000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q22_MASK 0x400000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q23_MASK 0x800000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q24_MASK 0x1000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q25_MASK 0x2000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q26_MASK 0x4000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q27_MASK 0x8000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q28_MASK 0x10000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q29_MASK 0x20000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q30_MASK 0x40000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q31_MASK 0x80000000 + + +/* + * Register + * + * Wakeup Thresholds in which to indicate RNR + */ +#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD 0x774 + +/* + * Wakeup threshold. + * Once number of Guaranteed buffer count crosses the threshold and there + * is a pending wakeup request, the dispatcher will issue a wakeup message + * to the appropriate runner according to a predefind address configuration +*/ +#define WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_SHIFT 0 +#define WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_MASK 0x3ff + + +/* + * Registers - is [ 0 => 31 ] + * + * DWRR info per Q. + * including amount of credits per Q. + * If Q has below zero credits and Quantum size + */ +#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO(x) (0x780 + (x) * 0x4) + +/* + * availabe credits in bytes. + * Q will not be permitted to dispatch PDs if credit levels are below zero +*/ +#define DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_SHIFT 0 +#define DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_MASK 0xfffff + +/* + * Bit will be enabled if credit levels are below zero. + * 2 compliment +*/ +#define DISPTCH_SCHEDULING_DWRR_INFO_NGTV_MASK 0x100000 + +/* + * Quantum size. + * Should be configured according to Q rate. + * in Bytes +*/ +#define DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_SHIFT 21 +#define DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_MASK 0xffe00000 + + +/* + * Register + * + * Queues with credits above zero. + * This will allow for the Q to participate in the scheduling round + */ +#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT 0x800 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q0_MASK 0x1 + +/* Valid Credits. */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q1_MASK 0x2 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q2_MASK 0x4 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q3_MASK 0x8 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q4_MASK 0x10 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q5_MASK 0x20 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q6_MASK 0x40 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q7_MASK 0x80 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q8_MASK 0x100 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q9_MASK 0x200 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q10_MASK 0x400 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q11_MASK 0x800 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q12_MASK 0x1000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q13_MASK 0x2000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q14_MASK 0x4000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q15_MASK 0x8000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q16_MASK 0x10000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q17_MASK 0x20000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q18_MASK 0x40000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q19_MASK 0x80000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q20_MASK 0x100000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q21_MASK 0x200000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q22_MASK 0x400000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q23_MASK 0x800000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q24_MASK 0x1000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q25_MASK 0x2000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q26_MASK 0x4000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q27_MASK 0x8000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q28_MASK 0x10000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q29_MASK 0x20000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q30_MASK 0x40000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q31_MASK 0x80000000 + + +/* + * Register + * + * Selects which Load Balancing mechanism to use + */ +#define DSPTCHR_LOAD_BALANCING_LB_CFG 0x850 + +/* RoundRobin = 0StrictPriority = 1 */ +#define LOAD_BALANCING_LB_CFG_LB_MODE_MASK 0x1 + +/* + * Configures the threshold in which the LB mechanism opens activates a new + * RNR +*/ +#define LOAD_BALANCING_LB_CFG_SP_THRSHLD_SHIFT 8 +#define LOAD_BALANCING_LB_CFG_SP_THRSHLD_MASK 0x1f00 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0..15 belong to RNR 0 + * Tasks 16..32 Belong to RNR 1 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1 0x860 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_0_1_RNR0_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_0_1_RNR0_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_0_1_RNR1_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_0_1_RNR1_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0..15 belong to RNR 2 + * Tasks 16..32 Belong to RNR 3 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3 0x864 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_2_3_RNR2_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_2_3_RNR2_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_2_3_RNR3_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_2_3_RNR3_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 4Tasks 16. + * .32 Belong to RNR 5 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5 0x868 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_4_5_RNR4_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_4_5_RNR4_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_4_5_RNR5_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_4_5_RNR5_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 6Tasks 16. + * .32 Belong to RNR 7 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7 0x86c + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_6_7_RNR6_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_6_7_RNR6_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_6_7_RNR7_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_6_7_RNR7_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 8Tasks 16. + * .32 Belong to RNR 9 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9 0x870 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_8_9_RNR8_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_8_9_RNR8_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_8_9_RNR9_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_8_9_RNR9_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 10Tasks 16. + * .32 Belong to RNR 11 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11 0x874 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_10_11_RNR10_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_10_11_RNR10_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_10_11_RNR11_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_10_11_RNR11_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 12Tasks 16. + * .32 Belong to RNR 13 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13 0x878 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_12_13_RNR12_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_12_13_RNR12_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_12_13_RNR13_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_12_13_RNR13_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 14Tasks 16. + * .32 Belong to RNR 15 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15 0x87c + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_14_15_RNR14_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_14_15_RNR14_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_14_15_RNR15_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_14_15_RNR15_MASK 0xffff0000 + + +/* + * Registers - is [ 0 => 31 ] + * + * This ram is used to map each task to which group does it belong to. + */ +#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING(x) (0x900 + (x) * 0x4) + +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSKx_SHIFT(x) ((x) * 3) + +/* + * Can be Task 0/8/16... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_SHIFT 0 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_MASK 0x7 + +/* + * Can be Task 1/9/17... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_SHIFT 3 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_MASK 0x38 + +/* + * Can be Task 2/10/18... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_SHIFT 6 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_MASK 0x1c0 + +/* + * Can be Task 3/11/19... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_SHIFT 9 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_MASK 0xe00 + +/* + * Can be Task 4/12/20... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_SHIFT 12 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_MASK 0x7000 + +/* + * Can be Task 5/13/21... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_SHIFT 15 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_MASK 0x38000 + +/* + * Can be Task 6/14/22... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_SHIFT 18 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_MASK 0x1c0000 + +/* + * Can be Task 7/15/23... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_SHIFT 21 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_MASK 0xe00000 + + +/* + * Register + * + * Available tasks in all runners related to a RNR Group. + * In case value is zero there are no tasks available for this RNR Group + * for dispatch hence it should be excluded from the next RNR Group + * selection + */ +#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3 0x980 + +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_x_SHIFT(x) ((x) * 8) + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_SHIFT 0 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_MASK 0xff + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_SHIFT 8 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_MASK 0xff00 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_SHIFT 16 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_MASK 0xff0000 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_SHIFT 24 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_MASK 0xff000000 + + +/* + * Register + * + * Available tasks in all runners related to a RNR Group. + * In case value is zero there are no tasks available for this RNR Group + * for dispatch hence it should be excluded from the next RNR Group + * selection + */ +#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7 0x984 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_SHIFT 0 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_MASK 0xff + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_SHIFT 8 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_MASK 0xff00 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_SHIFT 16 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_MASK 0xff0000 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_SHIFT 24 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_MASK 0xff000000 + + +/* + * Register + * + * This register contains the current active TM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR 0x990 + +/* Buffer returned to Fll */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_MASK 0x1 + +/* Drop PD counted */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_MASK 0x2 + +/* Unknown message entered the dispatcher */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_MASK 0x4 + +/* + * Number of buffers returned to FLL exceeds the pre-defined allocated + * buffer amount (due to linked list bug) +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_MASK 0x8 + +/* + * Number of buffers returned to FLL decreased under zero and reached a + * negative amount (due to linked list bug) +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_MASK 0x10 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM 0x994 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER 0x998 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR 0x99c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_MASK 0xffffffff + + +/* + * Register + * + * This register contains the current active TM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR 0x9a0 + +/* New Entry added to Destination queue 0 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_MASK 0x1 + +/* New Entry added to Destination queue 1 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_MASK 0x2 + +/* New Entry added to Destination queue 2 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_MASK 0x4 + +/* New Entry added to Destination queue 3 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_MASK 0x8 + +/* New Entry added to Destination queue 4 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_MASK 0x10 + +/* New Entry added to Destination queue 5 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_MASK 0x20 + +/* New Entry added to Destination queue 6 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_MASK 0x40 + +/* New Entry added to Destination queue 7 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_MASK 0x80 + +/* New Entry added to Destination queue 8 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_MASK 0x100 + +/* New Entry added to Destination queue 9 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_MASK 0x200 + +/* New Entry added to Destination queue 10 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_MASK 0x400 + +/* New Entry added to Destination queue 11 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_MASK 0x800 + +/* New Entry added to Destination queue 12 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_MASK 0x1000 + +/* New Entry added to Destination queue 13 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_MASK 0x2000 + +/* New Entry added to Destination queue 14 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_MASK 0x4000 + +/* New Entry added to Destination queue 15 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_MASK 0x8000 + +/* New Entry added to Destination queue 16 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_MASK 0x10000 + +/* New Entry added to Destination queue 17 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_MASK 0x20000 + +/* New Entry added to Destination queue 18 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_MASK 0x40000 + +/* New Entry added to Destination queue 19 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_MASK 0x80000 + +/* New Entry added to Destination queue 20 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_MASK 0x100000 + +/* New Entry added to Destination queue 21 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_MASK 0x200000 + +/* New Entry added to Destination queue 22 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_MASK 0x400000 + +/* New Entry added to Destination queue 23 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_MASK 0x800000 + +/* New Entry added to Destination queue 24 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_MASK 0x1000000 + +/* New Entry added to Destination queue 25 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_MASK 0x2000000 + +/* New Entry added to Destination queue 26 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_MASK 0x4000000 + +/* New Entry added to Destination queue 27 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_MASK 0x8000000 + +/* New Entry added to Destination queue 28 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_MASK 0x10000000 + +/* New Entry added to Destination queue 29 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_MASK 0x20000000 + +/* New Entry added to Destination queue 30 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_MASK 0x40000000 + +/* New Entry added to Destination queue 31 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_MASK 0x80000000 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM 0x9a4 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER 0x9a8 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR 0x9ac + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_MASK 0xffffffff + + +/* + * Register + * + * Debug Bypass control + */ +#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL 0x9b0 + +/* Enable bypass mode */ +#define DEBUG_DBG_BYPSS_CNTRL_EN_BYP_MASK 0x1 + +/* What BBID to use for NON_DELAY Q when in Bypass mode */ +#define DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_SHIFT 8 +#define DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_MASK 0xff00 + +/* What BBID to use for DELAY Q when in Bypass mode */ +#define DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_SHIFT 16 +#define DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_MASK 0xff0000 + + +/* + * Register + * + * Counts the amount of active Tasks in RNR + */ +#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7 0x9b4 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_SHIFT 0 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_MASK 0xf + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_SHIFT 4 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_MASK 0xf0 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_SHIFT 8 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_MASK 0xf00 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_SHIFT 12 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_MASK 0xf000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_SHIFT 16 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_MASK 0xf0000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_SHIFT 20 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_MASK 0xf00000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_SHIFT 24 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_MASK 0xf000000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_SHIFT 28 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_MASK 0xf0000000 + + +/* + * Register + * + * Counts the amount of active Tasks in RNR + */ +#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15 0x9b8 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_SHIFT 0 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_MASK 0xf + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_SHIFT 4 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_MASK 0xf0 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_SHIFT 8 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_MASK 0xf00 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_SHIFT 12 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_MASK 0xf000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_SHIFT 16 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_MASK 0xf0000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_SHIFT 20 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_MASK 0xf00000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_SHIFT 24 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_MASK 0xf000000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_SHIFT 28 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_MASK 0xf0000000 + + +/* + * Register + * + * Debug bus control which vector to output to the top level + */ +#define DSPTCHR_DEBUG_DBG_BUS_CNTRL 0x9bc + +/* Selects with vector to output */ +#define DEBUG_DBG_BUS_CNTRL_DBG_SEL_SHIFT 0 +#define DEBUG_DBG_BUS_CNTRL_DBG_SEL_MASK 0x1f + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_0 0x9c0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_0_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_0_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_1 0x9c4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_1_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_1_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_2 0x9c8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_2_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_2_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_3 0x9cc + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_3_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_3_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_4 0x9d0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_4_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_4_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_5 0x9d4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_5_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_5_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_6 0x9d8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_6_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_6_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_7 0x9dc + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_7_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_7_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_8 0x9e0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_8_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_8_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_9 0x9e4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_9_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_9_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_10 0x9e8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_10_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_10_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_11 0x9ec + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_11_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_11_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_12 0x9f0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_12_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_12_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_13 0x9f4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_13_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_13_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_14 0x9f8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_14_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_14_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_15 0x9fc + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_15_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_15_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_16 0xa00 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_16_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_16_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_17 0xa04 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_17_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_17_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_18 0xa08 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_18_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_18_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_19 0xa0c + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_19_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_19_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_20 0xa10 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_20_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_20_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_21 0xa14 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_21_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_21_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_22 0xa18 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_22_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_22_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_23 0xa1c + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_23_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_23_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register + * + * Controls which information to log + */ +#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL 0xa70 + +/* Selects mode to log */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_SHIFT 0 +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_MASK 0x3 + +/* Enable statistics */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_MASK 0x100 + +/* Clears all counters */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_MASK 0x200 + +/* Selects RNR to log */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_SHIFT 16 +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_MASK 0xf0000 + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Debug counter + */ +#define DSPTCHR_DEBUG_STATISTICS_DBG_CNT(x) (0xa80 + (x) * 0x4) + +/* Debug bus vector value */ +#define DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Pointer to the first BD in the link list of this queue. + */ +#define DSPTCHR_QDES_HEAD(x) (0x2000 + (x) * 0x20) + +/* Pointer to the first BD in the link list of this queue. */ +#define QDES_HEAD_HEAD_SHIFT 0 +#define QDES_HEAD_HEAD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * 32 bit wrap around counter. + * Counts number of packets that left this queue since start of queue + * activity. + */ +#define DSPTCHR_QDES_BFOUT(x) (0x2004 + (x) * 0x20) + +/* + * 32 bit wrap around counter. + * Counts number of packets that left this queue since start of queue + * activity. +*/ +#define QDES_BFOUT_BFOUT_SHIFT 0 +#define QDES_BFOUT_BFOUT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * 32 bit wrap around counter. + * Counts number of packets that entered this queue since start of queue + * activity. + */ +#define DSPTCHR_QDES_BUFIN(x) (0x2008 + (x) * 0x20) + +/* + * 32 bit wrap around counter. + * Counts number of packets that entered this queue since start of queue + * activity. +*/ +#define QDES_BUFIN_BUFIN_SHIFT 0 +#define QDES_BUFIN_BUFIN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Pointer to the last BD in the linked list of this queue. + */ +#define DSPTCHR_QDES_TAIL(x) (0x200c + (x) * 0x20) + +/* Pointer to the last BD in the linked list of this queue. */ +#define QDES_TAIL_TAIL_SHIFT 0 +#define QDES_TAIL_TAIL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * If this bit is set then the first BD attached to this Q is a null BD. + * In this case, its Data Pointer field is not valid, but its Next BD + * pointer field is valid. + * When it is set, the NullBD field for this queue is not valid. + */ +#define DSPTCHR_QDES_FBDNULL(x) (0x2010 + (x) * 0x20) + +/* + * If this bit is set then the first BD attached to this Q is a null BD. + * In this case, its Data Pointer field is not valid, but its Next BD + * pointer field is valid. + * When it is set, the NullBD field for this queue is not valid. +*/ +#define QDES_FBDNULL_FBDNULL_MASK 0x1 + + +/* + * Registers - is [ 0 => 31 ] + * + * 32 bits index of a Null BD that belongs to this queue. + * Both the data buffer pointer and the next BD field are non valid. + * The pointer defines a memory allocation for a BD that might be used or + * not. + */ +#define DSPTCHR_QDES_NULLBD(x) (0x2014 + (x) * 0x20) + +/* + * 32 bits index of a Null BD that belongs to this queue. + * Both the data buffer pointer and the next BD field are non valid. + * The pointer defines a memory allocation for a BD that might be used or + * not. +*/ +#define QDES_NULLBD_NULLBD_SHIFT 0 +#define QDES_NULLBD_NULLBD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * number of entries available in queue. + * bufin - bfout + */ +#define DSPTCHR_QDES_BUFAVAIL(x) (0x2018 + (x) * 0x20) + +/* + * number of entries available in queue. + * bufin - bfout +*/ +#define QDES_BUFAVAIL_BUFAVAIL_SHIFT 0 +#define QDES_BUFAVAIL_BUFAVAIL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Head Buffer, Used for the dispatching logic + */ +#define DSPTCHR_QDES_REG_Q_HEAD(x) (0x2600 + (x) * 0x4) + +/* Q HEAD */ +#define QDES_REG_Q_HEAD_HEAD_SHIFT 0 +#define QDES_REG_Q_HEAD_HEAD_MASK 0x3ff + + +/* + * Register + * + * This register will hold the for each VIQ if the Head of the Q is valid + * or not. + * These Queues are for Dispatch + */ +#define DSPTCHR_QDES_REG_VIQ_HEAD_VLD 0x2680 + +/* + * Q head valid. + * Each bit indicates for a specific VIQ if the head is valid or not +*/ +#define QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_SHIFT 0 +#define QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_MASK 0xffffffff + + +/* + * Register + * + * This register will hold for each VIQ if the Coherency counter is larger + * than zero. + */ +#define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD 0x2684 + +/* + * Q Coherency counter is valid. + * Each bit indicates for a specific VIQ if the there is more than one + * coherency message for that Q. + * meaning the head of the VIQ can be dispatched +*/ +#define QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_SHIFT 0 +#define QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_MASK 0xffffffff + + +/* + * Register + * + * This register will hold the for each VEQ if the Head of the Q is valid + * or notThese Queues are for ReOrder + */ +#define DSPTCHR_QDES_REG_VEQ_HEAD_VLD 0x2688 + +/* + * Q head valid. + * Each bit indicates for a specific VIQ if the head is valid or not +*/ +#define QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_SHIFT 0 +#define QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_MASK 0xffffffff + + +/* + * Register + * + * Todays implementation does not require that QDES available buffer be + * different than zero. + * so this register controls whether or not to it should affect poping from + * the QDES or not + */ +#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL 0x268c + +/* Should buf_avail in the QDES affect poping from head of linked list */ +#define QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_MASK 0x1 + +/* Should buf_avail in the QDES affect poping from head of linked list */ +#define QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_MASK 0x2 + + +/* + * Register + * + * Pointer to the first BD in the link list of this queue. + */ +#define DSPTCHR_FLLDES_HEAD 0x2700 + +/* Pointer to the first BD in the link list of this queue. */ +#define FLLDES_HEAD_HEAD_SHIFT 0 +#define FLLDES_HEAD_HEAD_MASK 0xffffffff + + +/* + * Register + * + * 32 bit wrap around counter. + * Counts number of entries that left this queue since start of queue + * activity. + */ +#define DSPTCHR_FLLDES_BFOUT 0x2704 + +/* + * 32 bit wrap around counter. + * Counts number of entries that left this queue since start of queue + * activity. +*/ +#define FLLDES_BFOUT_COUNT_SHIFT 0 +#define FLLDES_BFOUT_COUNT_MASK 0xffffffff + + +/* + * Register + * + * 32 bit wrap around counter. + * Counts number of entries that entered this queue since start of queue + * activity. + */ +#define DSPTCHR_FLLDES_BFIN 0x2708 + +/* + * 32 bit wrap around counter. + * Counts number of entries that entered this queue since start of queue + * activity. +*/ +#define FLLDES_BFIN_BFIN_SHIFT 0 +#define FLLDES_BFIN_BFIN_MASK 0xffffffff + + +/* + * Register + * + * Pointer to the last BD in the linked list of this queue. + */ +#define DSPTCHR_FLLDES_TAIL 0x270c + +/* Pointer to the last BD in the linked list of this queue. */ +#define FLLDES_TAIL_TAIL_SHIFT 0 +#define FLLDES_TAIL_TAIL_MASK 0xffffffff + + +/* + * Register + * + * 32 bit counter that counts the number of packets arrived when there is + * no free BD in the FLL. + */ +#define DSPTCHR_FLLDES_FLLDROP 0x2710 + +/* + * 32 bit counter that counts the number of packets arrived when there is + * no free BD in the FLL. +*/ +#define FLLDES_FLLDROP_DRPCNT_SHIFT 0 +#define FLLDES_FLLDROP_DRPCNT_MASK 0xffffffff + + +/* + * Register + * + * Low threshold Interrupt. + * When number of bytes reach this level, then an interrupt is generated to + * the Host. + */ +#define DSPTCHR_FLLDES_LTINT 0x2714 + +/* + * Low threshold Interrupt. + * When number of bytes reach this level, then an interrupt is generated to + * the Host. +*/ +#define FLLDES_LTINT_MINBUF_SHIFT 0 +#define FLLDES_LTINT_MINBUF_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of entries available in queue. + * bufin - bfout + */ +#define DSPTCHR_FLLDES_BUFAVAIL 0x2720 + +/* + * number of entries available in queue. + * bufin - bfout +*/ +#define FLLDES_BUFAVAIL_BUFAVAIL_SHIFT 0 +#define FLLDES_BUFAVAIL_BUFAVAIL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Save the MIN size of free BD in the system that has been recorded during + * work. + */ +#define DSPTCHR_FLLDES_FREEMIN 0x2724 + +/* minum value of free BD recorded */ +#define FLLDES_FREEMIN_FREEMIN_SHIFT 0 +#define FLLDES_FREEMIN_FREEMIN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1023 ] + * + * This Memory holds the Buffer Descriptor (BD) entries. + */ +#define DSPTCHR_BDRAM_DATA(x) (0x3000 + (x) * 0x4) + +/* Data Buffer entry */ +#define BDRAM_DATA_DATA_SHIFT 2 +#define BDRAM_DATA_DATA_MASK 0xffc + + +/* + * Registers - is [ 0 => 4095 ] + * + * This memory holds the Packet descriptors. + */ +#define DSPTCHR_PDRAM_DATA(x) (0x4000 + (x) * 0x4) + +/* Data Buffer entry */ +#define PDRAM_DATA_DATA_SHIFT 0 +#define PDRAM_DATA_DATA_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_DSPTCHR_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_fpm.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_fpm.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_fpm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_fpm.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,1952 @@ +#ifndef XRDP_REGS_FPM_H_ +#define XRDP_REGS_FPM_H_ + +/* relative to core */ +#define FPM_OFFSET_0 0xa00000 + +/* + * Register + * + */ +#define FPM_FPM_CTL 0x0 + +/* + * Test port mux control bits used to drive test signals from different + * submodules. +*/ +#define FPM_CTL_TP_MUX_CNTRL_SHIFT 27 +#define FPM_CTL_TP_MUX_CNTRL_MASK 0xf8000000 + +/* + * Disabling check for index memory corrupt during alloc/free/mcast + * updates. + * This should be used for debug purposes only 0 = Enable memory corruption + * check (normal operation) 1 = Disable memory corruption check +*/ +#define FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_MASK 0x2000000 + +/* + * Stop loading allocation fifo/cache with new tokens. + * This is should be used for debug purposes only 0 = Enable loading new + * tokens (normal operation) 1 = Disable loading new tokens +*/ +#define FPM_CTL_STOP_ALLOC_CACHE_LOAD_MASK 0x1000000 + +/* Enable POOL2 token allocation / deallocation 0 = Disabled 1 = Enabled */ +#define FPM_CTL_POOL2_ENABLE_MASK 0x20000 + +/* Enable POOL1 token allocation / deallocation 0 = Disabled 1 = Enabled */ +#define FPM_CTL_POOL1_ENABLE_MASK 0x10000 + +/* + * Set to 1 to hold the FPM Broadbus interface in reset. + * This is useful for maintaining a known state on that interface when + * Runner is powered down. +*/ +#define FPM_CTL_FPM_BB_SOFT_RESET_MASK 0x4000 + +/* + * Clear memory - Initialize all bits of the usage index array memory to + * zero's This is a self clearing bit. + * Once software writes a 1'b1 to enable, hardware initializes the memory + * and resets this bit back to 1'b0 at completion of initialization. + * Software can poll this bit and check for a value a zero that indicates + * initialization completion status +*/ +#define FPM_CTL_INIT_MEM_MASK 0x10 + +/* + * Clear memory - Initialize all bits of the usage index array memory to + * zero's This is a self clearing bit. + * Once software writes a 1'b1 to enable, hardware initializes the memory + * and resets this bit back to 1'b0 at completion of initialization. + * Software can poll this bit and check for a value a zero that indicates + * initialization completion status +*/ +#define FPM_CTL_INIT_MEM_POOL2_MASK 0x8 + + +/* + * Register + * + */ +#define FPM_FPM_CFG1 0x4 + +/* + * Index memory search method (For more info refer to FPM architecture wiki + * page) 0 = Method 1 1 = Method 2 +*/ +#define FPM_CFG1_POOL1_SEARCH_MODE_MASK 0x1 + + +/* + * Register + * + */ +#define FPM_FPM_WEIGHT 0x8 + +/* Weight assigned to each free to pool for DDR1 */ +#define FPM_WEIGHT_DDR1_FREE_WEIGHT_SHIFT 24 +#define FPM_WEIGHT_DDR1_FREE_WEIGHT_MASK 0xff000000 + +/* Weight assigned to each alloc from pool for DDR1 */ +#define FPM_WEIGHT_DDR1_ALLOC_WEIGHT_SHIFT 16 +#define FPM_WEIGHT_DDR1_ALLOC_WEIGHT_MASK 0xff0000 + +/* Weight assigned to each free to pool for DDR0 */ +#define FPM_WEIGHT_DDR0_FREE_WEIGHT_SHIFT 8 +#define FPM_WEIGHT_DDR0_FREE_WEIGHT_MASK 0xff00 + +/* Weight assigned to each alloc from pool for DDR0 */ +#define FPM_WEIGHT_DDR0_ALLOC_WEIGHT_SHIFT 0 +#define FPM_WEIGHT_DDR0_ALLOC_WEIGHT_MASK 0xff + + +/* + * Register + * + */ +#define FPM_FPM_BB_CFG 0xc + +/* + * Select pool/DDR to be used when FPM_BB allocates tokens 11 = reserved 10 + * = allocate from both pools 01 = pool1/DDR1 00 = pool0/DDR0 +*/ +#define FPM_BB_CFG_BB_DDR_SEL_SHIFT 0 +#define FPM_BB_CFG_BB_DDR_SEL_MASK 0x3 + + +/* + * Register + * + * Mask bits are active high and are disabled by default. + * Software enables desired bits as necessary + */ +#define FPM_POOL1_INTR_MSK 0x10 + +/* Expired token recovered interrupt mask. */ +#define POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_MASK 0x4000 + +/* Expired token detect interrupt mask. */ +#define POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_MASK 0x2000 + +/* Illegal token request interrupt mask. */ +#define POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_MASK 0x1000 + +/* Illegal/un-implemented register/memory space access interrupt mask. */ +#define POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_MASK 0x800 + +/* XON_STATE interrupt mask. */ +#define POOL1_INTR_MSK_XON_MSK_MASK 0x400 + +/* XOFF_STATE interrupt mask. */ +#define POOL1_INTR_MSK_XOFF_MSK_MASK 0x200 + +/* Index Memory corrupt interrupt mask. */ +#define POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_MASK 0x100 + +/* Free or Mcast update on disabled pool interrupt mask . */ +#define POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_MASK 0x80 + +/* Token multi-cast value update request with index out-of-range. */ +#define POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x40 + +/* Token multi-cast value update request with invalid token. */ +#define POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_MASK 0x20 + +/* De-allocation token request with index out-of-range. */ +#define POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x10 + +/* De-allocation token request with invalid token. */ +#define POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_MASK 0x8 + +/* Usage Index Pool is fully allocated interrupt mask. */ +#define POOL1_INTR_MSK_POOL_FULL_MSK_MASK 0x4 + +/* De-Allocation FIFO Full Interrupt mask. */ +#define POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_MASK 0x2 + +/* Allocation FIFO Full Interrupt mask. */ +#define POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_MASK 0x1 + + +/* + * Register + * + * Interrupt bits are active high. + * When a bit in this register is set to 1 and the corresponding bit in + * interrupt mask register is set to 1, interrupt to CPU will occur. + * When set (1), interrupts bits can be cleared (0) by writing a 1 to the + * desired bit. + */ +#define FPM_POOL1_INTR_STS 0x14 + +/* + * Expired token recovered interrupt. + * This is set when an expired token has been recoveredand returned to pool + * as an available token. +*/ +#define POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_MASK 0x4000 + +/* + * Expired token detect interrupt. + * This is set when the token recovery logic detects a token that has been + * held for the entire duration of the aging timer. +*/ +#define POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_MASK 0x2000 + +/* + * Illegal token request interrupt. + * This will be active when the pool is disabled, there is a request for a + * new token and the alloc fifo for the selected token size is empty. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_MASK 0x1000 + +/* + * Illegal/un-implemented register/memory space access interrupt. + * This will be active when there is an attempt to read from an + * unimplemented register or memory space. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_MASK 0x800 + +/* + * Number of available tokens is greater than or equal to XON_THRESHOLD + * value in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL1_INTR_STS_XON_STATE_STS_MASK 0x400 + +/* + * Number of available tokens is less than or equal to XOFF_THRESHOLD value + * in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL1_INTR_STS_XOFF_STATE_STS_MASK 0x200 + +/* + * Index Memory is corrupted. + * During updates of the usage array, token manager checks if the use count + * and search tree value in the array has a legal value. + * If the use count or search tree value is not correct before updating, + * logic generates an error and interrupt. + * As long as the interrupt is active no more valid tokens will be + * allocated because this is a catastrophic error. + * Following are the two error conditions that are checked - 1. + * During search for a free token, a particular token use count value + * indicates it is allocated (use count is greater than 0), but + * corresponding upper level search tree value indicates the token is still + * available (with bit value of 1'b0, instead of 1'b1). + * This is an error. + * 2. + * During search for a free token, a particular token use count value + * indicates that it is free (use count is 0), but corresponding upper + * level search tree value indicates the token is not available (with bit + * value of 1'b1, instead of 1'b0). + * This is an error. +*/ +#define POOL1_INTR_STS_MEMORY_CORRUPT_STS_MASK 0x100 + +/* + * Free or Mcast update on disabled pool interrupt. + * This bit goes active when a free or multi-cast request is received and + * FPM is not enabled, i. + * e. + * , pool enable bit in FPM control register is not set to 1'b1. +*/ +#define POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_MASK 0x80 + +/* + * Token multi-cast value update request with index out-of-range Interrupt. + * This is set when the token index is not aligned to the pool size. + * This is determined by examining the pool select field (bits[29: + * 28]) and the 3 lsbs of the token index (bits[14: + * 12]). + * There is no associated count for this error. + * Note: + * this error is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x40 + +/* + * Token multi-cast value update request with invalid token Interrupt. + * Invalid multi-cast token is determined when one or more the following + * conditions are met - 1. + * Incoming multi-cast request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming multi-cast request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming multi-cast request token has use count field (bit[6: + * 0]) set to zero 4. + * Incoming multi-cast request token entry in the usage array indicates it + * is not an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * 5. + * After updating the use count value, the new use count value exceeds 0x7E + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_MASK 0x20 + +/* + * De-allocation token request with index out-of-range Interrupt. + * Free token index out of range is determined when one or more of the + * following conditions are met - 1. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 2. + * The buffer size indicated by the size field (bits[11: + * 0]) is greater than the size of the allocated token. + * There is no associated count for this error. + * Note: + * item 1 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x10 + +/* + * De-allocation token request with invalid token Interrupt. + * Invalid free token is determined when one or more the following + * conditions are met - 1. + * Incoming free request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming free request token entry in the usage array indicates it is not + * an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_MASK 0x8 + +/* + * Usage Index Pool is fully allocated interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that token pool is fully allocated and there are no free + * tokens available. + * This bit will be active (high) as long as there no free tokens available + * to allocate. + * This bit is intended to be used for debug purpose only. +*/ +#define POOL1_INTR_STS_POOL_FULL_STS_MASK 0x4 + +/* + * De-Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that de-allocation FIFO is full with tokens needs to be + * freed and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL1_INTR_STS_FREE_FIFO_FULL_STS_MASK 0x2 + +/* + * Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that allocation FIFO is full with new tokens to be + * allocated and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_MASK 0x1 + + +/* + * Register + * + * Software sets desired stall bits that upon corresponding active + * interrupt status will stall FPM from new allocation, de-allocation, and + * mcast update process. + * Listed below are the supported interrupt statuses 1. + * Invalid free token (bit[3] of interrupt status register 0x14) 2. + * Invalid free token with index out-of-range (bit[4] of interrupt status + * register 0x14) 3. + * Invalid mcast token (bit[5] of interrupt status register 0x14) 4. + * Invalid mcast token with index out-of-range (bit[6] of interrupt status + * register 0x14) 5. + * Memory corrupt status (bit[8] of interrupt status register 0x14) When + * state machine is stalled, registers and memory can still be accessed. + * Any new token allocation request will be serviced with valid tokens (if + * available in alloc cache) and invalid tokens (if alloc cache is empty). + * Any new de-allocation/mcast update requests will be either stored in + * de-allocation fifo (if there is space in free fifo) or dropped (if free + * fifo is full). + * Bit locations in this register matches the location of corrseponding + * interrupt status bits in register 0x14. + * To un-stall (enable) state machine interrupt status bits (in register + * 0x14) corresponding to these mask bits should be cleared. + * Stall mask bits are active high and are disabled by default. + * This is for debug purposes only. + */ +#define FPM_POOL1_STALL_MSK 0x18 + +/* Stall FPM on Index Memory corrupt interrupt status. */ +#define POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_MASK 0x100 + +/* + * Stall FPM on Token multi-cast value update request with index + * out-of-range interrupt status. +*/ +#define POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x40 + +/* + * Stall FPM on Token multi-cast value update request with invalid token + * interrupt status. +*/ +#define POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_MASK 0x20 + +/* + * Stall FPM on De-allocation token request with index out-of-range + * interrupt status. +*/ +#define POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x10 + +/* + * Stall FPM on De-allocation token request with invalid token interrupt + * status. +*/ +#define POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_MASK 0x8 + + +/* + * Register + * + * Mask bits are active high and are disabled by default. + * Software enables desired bits as necessary + */ +#define FPM_POOL2_INTR_MSK 0x1c + +/* Expired token recovered interrupt mask. */ +#define POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_MASK 0x4000 + +/* Expired token detect interrupt mask. */ +#define POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_MASK 0x2000 + +/* Illegal token request interrupt mask. */ +#define POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_MASK 0x1000 + +/* Illegal/un-implemented register/memory space access interrupt mask. */ +#define POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_MASK 0x800 + +/* XON_STATE interrupt mask. */ +#define POOL2_INTR_MSK_XON_MSK_MASK 0x400 + +/* XOFF_STATE interrupt mask. */ +#define POOL2_INTR_MSK_XOFF_MSK_MASK 0x200 + +/* Index Memory corrupt interrupt mask. */ +#define POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_MASK 0x100 + +/* Free or Mcast update on disabled pool interrupt mask . */ +#define POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_MASK 0x80 + +/* Token multi-cast value update request with index out-of-range. */ +#define POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x40 + +/* Token multi-cast value update request with invalid token. */ +#define POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_MASK 0x20 + +/* De-allocation token request with index out-of-range. */ +#define POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x10 + +/* De-allocation token request with invalid token. */ +#define POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_MASK 0x8 + +/* Usage Index Pool is fully allocated interrupt mask. */ +#define POOL2_INTR_MSK_POOL_FULL_MSK_MASK 0x4 + +/* De-Allocation FIFO Full Interrupt mask. */ +#define POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_MASK 0x2 + +/* Allocation FIFO Full Interrupt mask. */ +#define POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_MASK 0x1 + + +/* + * Register + * + * Interrupt bits are active high. + * When a bit in this register is set to 1 and the corresponding bit in + * interrupt mask register is set to 1, interrupt to CPU will occur. + * When set (1), interrupts bits can be cleared (0) by writing a 1 to the + * desired bit. + */ +#define FPM_POOL2_INTR_STS 0x20 + +/* + * Expired token recovered interrupt. + * This is set when an expired token has been recoveredand returned to pool + * as an available token. +*/ +#define POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_MASK 0x4000 + +/* + * Expired token detect interrupt. + * This is set when the token recovery logic detects a token that has been + * held for the entire duration of the aging timer. +*/ +#define POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_MASK 0x2000 + +/* + * Illegal token request interrupt. + * This will be active when the pool is disabled, there is a request for a + * new token and the alloc fifo for the selected token size is empty. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_MASK 0x1000 + +/* + * Illegal/un-implemented register/memory space access interrupt. + * This will be active when there is an attempt to read from an + * unimplemented register or memory space. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_MASK 0x800 + +/* + * Number of available tokens is greater than or equal to XON_THRESHOLD + * value in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL2_INTR_STS_XON_STATE_STS_MASK 0x400 + +/* + * Number of available tokens is less than or equal to XOFF_THRESHOLD value + * in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL2_INTR_STS_XOFF_STATE_STS_MASK 0x200 + +/* + * Index Memory is corrupted. + * During updates of the usage array, token manager checks if the use count + * and search tree value in the array has a legal value. + * If the use count or search tree value is not correct before updating, + * logic generates an error and interrupt. + * As long as the interrupt is active no more valid tokens will be + * allocated because this is a catastrophic error. + * Following are the two error conditions that are checked - 1. + * During search for a free token, a particular token use count value + * indicates it is allocated (use count is greater than 0), but + * corresponding upper level search tree value indicates the token is still + * available (with bit value of 1'b0, instead of 1'b1). + * This is an error. + * 2. + * During search for a free token, a particular token use count value + * indicates that it is free (use count is 0), but corresponding upper + * level search tree value indicates the token is not available (with bit + * value of 1'b1, instead of 1'b0). + * This is an error. +*/ +#define POOL2_INTR_STS_MEMORY_CORRUPT_STS_MASK 0x100 + +/* + * Free or Mcast update on disabled pool interrupt. + * This bit goes active when a free or multi-cast request is received and + * FPM is not enabled, i. + * e. + * , pool enable bit in FPM control register is not set to 1'b1. +*/ +#define POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_MASK 0x80 + +/* + * Token multi-cast value update request with index out-of-range Interrupt. + * This is set when the token index is not aligned to the pool size. + * This is determined by examining the pool select field (bits[29: + * 28]) and the 3 lsbs of the token index (bits[14: + * 12]). + * There is no associated count for this error. + * Note: + * this error is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x40 + +/* + * Token multi-cast value update request with invalid token Interrupt. + * Invalid multi-cast token is determined when one or more the following + * conditions are met - 1. + * Incoming multi-cast request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming multi-cast request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming multi-cast request token has use count field (bit[6: + * 0]) set to zero 4. + * Incoming multi-cast request token entry in the usage array indicates it + * is not an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * 5. + * After updating the use count value, the new use count value exceeds 0x7E + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_MASK 0x20 + +/* + * De-allocation token request with index out-of-range Interrupt. + * Free token index out of range is determined when one or more of the + * following conditions are met - 1. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 2. + * The buffer size indicated by the size field (bits[11: + * 0]) is greater than the size of the allocated token. + * There is no associated count for this error. + * Note: + * item 1 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x10 + +/* + * De-allocation token request with invalid token Interrupt. + * Invalid free token is determined when one or more the following + * conditions are met - 1. + * Incoming free request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming free request token entry in the usage array indicates it is not + * an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_MASK 0x8 + +/* + * Usage Index Pool is fully allocated interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that token pool is fully allocated and there are no free + * tokens available. + * This bit will be active (high) as long as there no free tokens available + * to allocate. + * This bit is intended to be used for debug purpose only. +*/ +#define POOL2_INTR_STS_POOL_FULL_STS_MASK 0x4 + +/* + * De-Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that de-allocation FIFO is full with tokens needs to be + * freed and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL2_INTR_STS_FREE_FIFO_FULL_STS_MASK 0x2 + +/* + * Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that allocation FIFO is full with new tokens to be + * allocated and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_MASK 0x1 + + +/* + * Register + * + * Software sets desired stall bits that upon corresponding active + * interrupt status will stall FPM from new allocation, de-allocation, and + * mcast update process. + * Listed below are the supported interrupt statuses 1. + * Invalid free token (bit[3] of interrupt status register 0x14) 2. + * Invalid free token with index out-of-range (bit[4] of interrupt status + * register 0x14) 3. + * Invalid mcast token (bit[5] of interrupt status register 0x14) 4. + * Invalid mcast token with index out-of-range (bit[6] of interrupt status + * register 0x14) 5. + * Memory corrupt status (bit[8] of interrupt status register 0x14) When + * state machine is stalled, registers and memory can still be accessed. + * Any new token allocation request will be serviced with valid tokens (if + * available in alloc cache) and invalid tokens (if alloc cache is empty). + * Any new de-allocation/mcast update requests will be either stored in + * de-allocation fifo (if there is space in free fifo) or dropped (if free + * fifo is full). + * Bit locations in this register matches the location of corrseponding + * interrupt status bits in register 0x14. + * To un-stall (enable) state machine interrupt status bits (in register + * 0x14) corresponding to these mask bits should be cleared. + * Stall mask bits are active high and are disabled by default. + * This is for debug purposes only. + */ +#define FPM_POOL2_STALL_MSK 0x24 + +/* Stall FPM on Index Memory corrupt interrupt status. */ +#define POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_MASK 0x100 + +/* + * Stall FPM on Token multi-cast value update request with index + * out-of-range interrupt status. +*/ +#define POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x40 + +/* + * Stall FPM on Token multi-cast value update request with invalid token + * interrupt status. +*/ +#define POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_MASK 0x20 + +/* + * Stall FPM on De-allocation token request with index out-of-range + * interrupt status. +*/ +#define POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x10 + +/* + * Stall FPM on De-allocation token request with invalid token interrupt + * status. +*/ +#define POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_MASK 0x8 + + +/* + * Register + * + */ +#define FPM_POOL1_CFG1 0x40 + +/* + * Selects the size of the buffer to be used in the pool. + * All buffers must be the same size. + * 0 - 512 byte buffers 1 - 256 byte buffers all other values - reserved +*/ +#define POOL1_CFG1_FPM_BUF_SIZE_SHIFT 24 +#define POOL1_CFG1_FPM_BUF_SIZE_MASK 0x7000000 + + +/* + * Register + * + * This register sets the physical base address of this memory. + * The memory block should be the number of buffers times the buffer size. + * This is mainly used for multi-pool memory configuration. + * NOTE: + * POOL_BASE_ADDRESS[7: + * 2] and reserved[1: + * 0] field must be written with 0x00 in the BCM3382 because + * itstoken-to-address converter assumes the buffers start on a 2kB + * boundary. + */ +#define FPM_POOL1_CFG2 0x44 + +/* + * Buffer base address. + * 7: + * 2 must be 0x00. +*/ +#define POOL1_CFG2_POOL_BASE_ADDRESS_SHIFT 2 +#define POOL1_CFG2_POOL_BASE_ADDRESS_MASK 0xfffffffc + + +/* + * Register + * + * This register sets the physical base address of this memory. + * The memory block should be the number of buffers times the buffer size. + * This is mainly used for multi-pool memory configuration. + */ +#define FPM_POOL1_CFG3 0x48 + +/* + * Buffer base address. + * 7: + * 2 must be 0x00. +*/ +#define POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_SHIFT 2 +#define POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_MASK 0xfffffffc + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free pool + * overflows and underflows. + * A overflow condition occurs when pool is empty, ie. + * , no tokens are allocated and free/mcast request is encountered. + * A underflow condition occurs when pool is full, ie. + * , there are no free tokens and a allocation request is encountered. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear both both counters. + */ +#define FPM_POOL1_STAT1 0x50 + +/* Free Pool overflow count */ +#define POOL1_STAT1_OVRFL_SHIFT 16 +#define POOL1_STAT1_OVRFL_MASK 0xffff0000 + +/* Free Pool underflow count */ +#define POOL1_STAT1_UNDRFL_SHIFT 0 +#define POOL1_STAT1_UNDRFL_MASK 0xffff + + +/* + * Register - read-only + * + * This read only register provide status of index memory, alloc & free + * cache/fifos. + * These are real time statuses and bits are not sticky. + * Write to any bits will have no effect. + */ +#define FPM_POOL1_STAT2 0x54 + +/* + * POOL is full This indicates that all tokens have been allocated and + * there no free tokens available. + * This bit will be active as long as all usage array is fully allocated. +*/ +#define POOL1_STAT2_POOL_FULL_MASK 0x80000000 + +/* FREE_FIFO is full. */ +#define POOL1_STAT2_FREE_FIFO_FULL_MASK 0x20000000 + +/* FREE_FIFO is empty */ +#define POOL1_STAT2_FREE_FIFO_EMPTY_MASK 0x10000000 + +/* ALLOC_FIFO is full */ +#define POOL1_STAT2_ALLOC_FIFO_FULL_MASK 0x8000000 + +/* ALLOC_FIFO is empty. */ +#define POOL1_STAT2_ALLOC_FIFO_EMPTY_MASK 0x4000000 + +/* + * Count of tokens available for allocation. + * This provides a count of number of free tokens that available for + * allocation in the usage array. + * This value is updated instantaneously as tokens are allocated or freed + * from the array. +*/ +#define POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_SHIFT 0 +#define POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free token + * requests with in-valid tokens When the counter values reaches maximum + * count, it will hold the max value and not increment the count value + * unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL1_STAT3 0x58 + +/* + * Count of de-allocate token requests with invalid tokens. + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[3] + * explanation in this document. +*/ +#define POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_SHIFT 0 +#define POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of multi-cast + * token update requests with in-valid tokens. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL1_STAT4 0x5c + +/* + * Count of multi-cast token update requests with either valid bit not set, + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[5] + * explanation in this document. +*/ +#define POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_SHIFT 0 +#define POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the alloc token that + * causes memory corrupt interrupt (intr[8]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL1_STAT5 0x60 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes memory corrupt interrupt active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value, in addition, memory corrupt + * status bit (bit[8]) in interrupt status register 0x14 should be cleared. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Buffer size in bytes +*/ +#define POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_SHIFT 0 +#define POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the free token that + * causes invalid free request or free token with index out-of-range + * interrupts (intr[3] or intr[4]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL1_STAT6 0x64 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL1_STAT6_INVALID_FREE_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[3] or intr[4] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are either zeros or + * can reflect the length of the packet associated with the freed token) + * Bit[30] - Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Reserved +*/ +#define POOL1_STAT6_INVALID_FREE_TOKEN_SHIFT 0 +#define POOL1_STAT6_INVALID_FREE_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the multi-cast token + * that causes invalid mcast request or mcast token with index out-of-range + * interrupts (intr[5] or intr[6]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL1_STAT7 0x68 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[5] or intr[6] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11] - Mcast update type (refer to register 0x224[11]) + * Bit[10: + * 7] - Reserved Bit[6: + * 0] - Mcast value +*/ +#define POOL1_STAT7_INVALID_MCAST_TOKEN_SHIFT 0 +#define POOL1_STAT7_INVALID_MCAST_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This register allows software to read the lowest value the + * NUM_OF_TOKENS_AVAILABLE count reached since the last time it was + * cleared. + * Any write to this register will reset the value back to the maximum + * number of tokens (0x10000) + */ +#define FPM_POOL1_STAT8 0x6c + +/* Lowest value the NUM_OF_TOKENS_AVAIL count has reached. */ +#define POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_SHIFT 0 +#define POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free pool + * overflows and underflows. + * A overflow condition occurs when pool is empty, ie. + * , no tokens are allocated and free/mcast request is encountered. + * A underflow condition occurs when pool is full, ie. + * , there are no free tokens and a allocation request is encountered. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear both both counters. + */ +#define FPM_POOL2_STAT1 0x70 + +/* Free Pool overflow count */ +#define POOL2_STAT1_OVRFL_SHIFT 16 +#define POOL2_STAT1_OVRFL_MASK 0xffff0000 + +/* Free Pool underflow count */ +#define POOL2_STAT1_UNDRFL_SHIFT 0 +#define POOL2_STAT1_UNDRFL_MASK 0xffff + + +/* + * Register - read-only + * + * This read only register provide status of index memory, alloc & free + * cache/fifos. + * These are real time statuses and bits are not sticky. + * Write to any bits will have no effect. + */ +#define FPM_POOL2_STAT2 0x74 + +/* + * POOL is full This indicates that all tokens have been allocated and + * there no free tokens available. + * This bit will be active as long as all usage array is fully allocated. +*/ +#define POOL2_STAT2_POOL_FULL_MASK 0x80000000 + +/* FREE_FIFO is full. */ +#define POOL2_STAT2_FREE_FIFO_FULL_MASK 0x20000000 + +/* FREE_FIFO is empty */ +#define POOL2_STAT2_FREE_FIFO_EMPTY_MASK 0x10000000 + +/* ALLOC_FIFO is full */ +#define POOL2_STAT2_ALLOC_FIFO_FULL_MASK 0x8000000 + +/* ALLOC_FIFO is empty. */ +#define POOL2_STAT2_ALLOC_FIFO_EMPTY_MASK 0x4000000 + +/* + * Count of tokens available for allocation. + * This provides a count of number of free tokens that available for + * allocation in the usage array. + * This value is updated instantaneously as tokens are allocated or freed + * from the array. +*/ +#define POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_SHIFT 0 +#define POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free token + * requests with in-valid tokens When the counter values reaches maximum + * count, it will hold the max value and not increment the count value + * unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL2_STAT3 0x78 + +/* + * Count of de-allocate token requests with invalid tokens. + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[3] + * explanation in this document. +*/ +#define POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_SHIFT 0 +#define POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of multi-cast + * token update requests with in-valid tokens. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL2_STAT4 0x7c + +/* + * Count of multi-cast token update requests with either valid bit not set, + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[5] + * explanation in this document. +*/ +#define POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_SHIFT 0 +#define POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the alloc token that + * causes memory corrupt interrupt (intr[8]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL2_STAT5 0x80 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes memory corrupt interrupt active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value, in addition, memory corrupt + * status bit (bit[8]) in interrupt status register 0x14 should be cleared. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Buffer size in bytes +*/ +#define POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_SHIFT 0 +#define POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the free token that + * causes invalid free request or free token with index out-of-range + * interrupts (intr[3] or intr[4]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL2_STAT6 0x84 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL2_STAT6_INVALID_FREE_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[3] or intr[4] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are either zeros or + * can reflect the length of the packet associated with the freed token) + * Bit[30] - Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Reserved +*/ +#define POOL2_STAT6_INVALID_FREE_TOKEN_SHIFT 0 +#define POOL2_STAT6_INVALID_FREE_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the multi-cast token + * that causes invalid mcast request or mcast token with index out-of-range + * interrupts (intr[5] or intr[6]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL2_STAT7 0x88 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[5] or intr[6] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11] - Mcast update type (refer to register 0x224[11]) + * Bit[10: + * 7] - Reserved Bit[6: + * 0] - Mcast value +*/ +#define POOL2_STAT7_INVALID_MCAST_TOKEN_SHIFT 0 +#define POOL2_STAT7_INVALID_MCAST_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This register allows software to read the lowest value the + * NUM_OF_TOKENS_AVAILABLE count reached since the last time it was + * cleared. + * Any write to this register will reset the value back to the maximum + * number of tokens (0x10000) + */ +#define FPM_POOL2_STAT8 0x8c + +/* Lowest value the NUM_OF_TOKENS_AVAIL count has reached. */ +#define POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_SHIFT 0 +#define POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_MASK 0x3ffff + + +/* + * Register + * + */ +#define FPM_POOL1_XON_XOFF_CFG 0xc0 + +/* XON Threshold value */ +#define POOL1_XON_XOFF_CFG_XON_THRESHOLD_SHIFT 16 +#define POOL1_XON_XOFF_CFG_XON_THRESHOLD_MASK 0xffff0000 + +/* XOFF Threshold value */ +#define POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_SHIFT 0 +#define POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_MASK 0xffff + + +/* + * Register + * + */ +#define FPM_FPM_NOT_EMPTY_CFG 0xd0 + +/* Threshold value for reasserting pool_not_empty to FPM_BB */ +#define FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_SHIFT 0 +#define FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_MASK 0x3f + + +/* + * Register + * + */ +#define FPM_MEM_CTL 0x100 + +/* + * Write control bit for Usage index array memory. + * This is a self clearing bit, cleared by hardware to zero once memory + * write is complete. + * Software can write more locations if the bit value is zero +*/ +#define MEM_CTL_MEM_WR_MASK 0x80000000 + +/* + * Read control bit for Usage index array memory. + * This is a self clearing bit, cleared by hardware to zero once memory + * read is complete. + * Software can read more locations if the bit value is zero +*/ +#define MEM_CTL_MEM_RD_MASK 0x40000000 + +/* + * 2'b00 = Reserved 2'b01 = FPM Memory 2'b10 = Reserved 2'b11 = When memory + * is enabled, bit[31]=1, this value will allow a write to + * NUM_OF_TOKENS_AVAILABLE field [17: + * 0] in POOL1_STAT2 register (offset 0x54). + * This should be used for debug purposes only +*/ +#define MEM_CTL_MEM_SEL_SHIFT 28 +#define MEM_CTL_MEM_SEL_MASK 0x30000000 + +/* Memory address for write/read location This is DWord aligned address */ +#define MEM_CTL_MEM_ADDR_SHIFT 2 +#define MEM_CTL_MEM_ADDR_MASK 0x3fffc + + +/* + * Register + * + */ +#define FPM_MEM_DATA1 0x104 + +/* + * Memory Data 1 This contains the lower 32 bits (bits[31: + * 0]) of 32/64 bit data +*/ +#define MEM_DATA1_MEM_DATA1_SHIFT 0 +#define MEM_DATA1_MEM_DATA1_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_MEM_DATA2 0x108 + +/* + * Memory Data 2 This contains the upper 32 bits (bits[63: + * 32]) of 64 bit data. + * The value in this register should be ignored during 32 bit access +*/ +#define MEM_DATA2_MEM_DATA2_SHIFT 0 +#define MEM_DATA2_MEM_DATA2_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_TOKEN_RECOVER_CTL 0x130 + +/* + * This is a self-clearing bit. + * Write a 1 to the bit to reset the RECOVERED_TOKEN_COUNT to 0. +*/ +#define TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_MASK 0x40 + +/* + * This is a self-clearing bit. + * Write a 1 to the bit to reset the EXPIRED_TOKEN_COUNT to 0. +*/ +#define TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_MASK 0x20 + +/* + * Non-automated token recovery. + * This bit can be used when automatic token return is not enabled. + * When software gets an interrupt indicating that the token recovery + * process has detected expired tokens, it can set this bit to force the + * expired tokens to be reclaimed. + * 1 = Enabled 0 = Disabled +*/ +#define TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_MASK 0x10 + +/* + * Enable automatic return of marked tokens to the freepool 1 = Enabled 0 = + * Disabled +*/ +#define TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_MASK 0x8 + +/* + * Enable remarking of tokens for multiple passes through the token + * recovery process. + * The mark bit is set on all tokens on the first pass through the loop. + * When this bit is set, the mark bits will be set again on all subsequent + * passes through the loop. + * It is anticipated that this bit will always be set when token recovery + * is enabled. + * It is provided as a potential debug tool. + * 1 = Enabled 0 = Disabled +*/ +#define TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_MASK 0x4 + +/* + * If token recovery is enabled, the single-pass control will indicate + * whether the hardware should perform just one iteration of the token + * recovery process or will continuously loop through the token recovery + * process. + * 1 = Single pass 0 = Auto repeat +*/ +#define TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_MASK 0x2 + +/* Token recovery enable 1 = Enabled 0 = Disabled */ +#define TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_MASK 0x1 + + +/* + * Register + * + */ +#define FPM_SHORT_AGING_TIMER 0x134 + +/* Aging timer used in token recovery */ +#define SHORT_AGING_TIMER_TIMER_SHIFT 0 +#define SHORT_AGING_TIMER_TIMER_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_LONG_AGING_TIMER 0x138 + +/* Aging timer used in token recovery */ +#define LONG_AGING_TIMER_TIMER_SHIFT 0 +#define LONG_AGING_TIMER_TIMER_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_CACHE_RECYCLE_TIMER 0x13c + +/* + * Timer used in token recovery logic. + * Upon expiration of timer, one token from the allocate cache will be + * freed. + * Over time, all cached tokens will be recycled back to the freepool. + * This will prevent the cached tokens frm being aged out by the token + * recovery logic. + * This timer should be set to a value so that all tokens can be recycled + * before the aging timer expires. +*/ +#define CACHE_RECYCLE_TIMER_RECYCLE_TIMER_SHIFT 0 +#define CACHE_RECYCLE_TIMER_RECYCLE_TIMER_MASK 0xffff + + +/* + * Register - read-only + * + */ +#define FPM_EXPIRED_TOKEN_COUNT_POOL1 0x140 + +/* + * Cumulative count of the number of expired tokens detected in the token + * recovery process. + * The count can be cleared by setting the CLR_EXPIRED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define EXPIRED_TOKEN_COUNT_POOL1_COUNT_SHIFT 0 +#define EXPIRED_TOKEN_COUNT_POOL1_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + */ +#define FPM_RECOVERED_TOKEN_COUNT_POOL1 0x144 + +/* + * Cumulative count of the number of expired tokens that were freed in the + * token recovery process. + * The count can be cleared by setting the CLR_RECOVERED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define RECOVERED_TOKEN_COUNT_POOL1_COUNT_SHIFT 0 +#define RECOVERED_TOKEN_COUNT_POOL1_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + */ +#define FPM_EXPIRED_TOKEN_COUNT_POOL2 0x148 + +/* + * Cumulative count of the number of expired tokens detected in the token + * recovery process. + * The count can be cleared by setting the CLR_EXPIRED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define EXPIRED_TOKEN_COUNT_POOL2_COUNT_SHIFT 0 +#define EXPIRED_TOKEN_COUNT_POOL2_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + */ +#define FPM_RECOVERED_TOKEN_COUNT_POOL2 0x14c + +/* + * Cumulative count of the number of expired tokens that were freed in the + * token recovery process. + * The count can be cleared by setting the CLR_RECOVERED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define RECOVERED_TOKEN_COUNT_POOL2_COUNT_SHIFT 0 +#define RECOVERED_TOKEN_COUNT_POOL2_COUNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_TOKEN_RECOVER_START_END_POOL1 0x150 + +/* Start of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL1_START_INDEX_SHIFT 16 +#define TOKEN_RECOVER_START_END_POOL1_START_INDEX_MASK 0xfff0000 + +/* End of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL1_END_INDEX_SHIFT 0 +#define TOKEN_RECOVER_START_END_POOL1_END_INDEX_MASK 0xfff + + +/* + * Register + * + */ +#define FPM_TOKEN_RECOVER_START_END_POOL2 0x154 + +/* Start of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL2_START_INDEX_SHIFT 16 +#define TOKEN_RECOVER_START_END_POOL2_START_INDEX_MASK 0xfff0000 + +/* End of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL2_END_INDEX_SHIFT 0 +#define TOKEN_RECOVER_START_END_POOL2_END_INDEX_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL1_ALLOC_DEALLOC 0x400 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL1_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL1_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL1_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL1_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL1_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL1_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL2_ALLOC_DEALLOC 0x408 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL2_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL2_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL2_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL2_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL2_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL2_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL3_ALLOC_DEALLOC 0x410 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL3_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL3_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL3_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL3_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL3_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL3_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL4_ALLOC_DEALLOC 0x418 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL4_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL4_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL4_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL4_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL4_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL4_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + */ +#define FPM_SPARE 0x420 + +#define SPARE_SPARE_BITS_SHIFT 0 +#define SPARE_SPARE_BITS_MASK 0xffffffff + +/* + * Register + * + * Update/Modify the multi-cast value of the token + */ +#define FPM_POOL_MULTI 0x424 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token multi-cast value is updated without this bit set, that causes + * an error and the token will be ignored, error counter in register offset + * 0xBC will be incremented. +*/ +#define POOL_MULTI_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL_MULTI_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL_MULTI_TOKEN_INDEX_SHIFT 12 +#define POOL_MULTI_TOKEN_INDEX_MASK 0x1ffff000 + +/* + * 1'b0 - Count value is replaced with new value in bits[6: + * 0] 1'b1 - Count value is incremented by value in bits[6: + * 0] +*/ +#define POOL_MULTI_UPDATE_TYPE_MASK 0x800 + +/* New Multi-cast Value */ +#define POOL_MULTI_TOKEN_MULTI_SHIFT 0 +#define POOL_MULTI_TOKEN_MULTI_MASK 0x7f + + +/* + * Register + * + * Write this register to force FPM_BB transaction + */ +#define FPM_FPM_BB_FORCE 0x30000 + +/* Write 1 to force BB transaction */ +#define FPM_BB_FORCE_FORCE_MASK 0x1 + + +/* + * Register + * + * Control to be sent on forced transaction + */ +#define FPM_FPM_BB_FORCED_CTRL 0x30004 + +/* Forced control */ +#define FPM_BB_FORCED_CTRL_CTRL_SHIFT 0 +#define FPM_BB_FORCED_CTRL_CTRL_MASK 0xfff + + +/* + * Register + * + * Address to be sent on forced transaction + */ +#define FPM_FPM_BB_FORCED_ADDR 0x30008 + +/* Forced TA address */ +#define FPM_BB_FORCED_ADDR_TA_ADDR_SHIFT 0 +#define FPM_BB_FORCED_ADDR_TA_ADDR_MASK 0xffff + +/* Forced destination address */ +#define FPM_BB_FORCED_ADDR_DEST_ADDR_SHIFT 16 +#define FPM_BB_FORCED_ADDR_DEST_ADDR_MASK 0x3f0000 + + +/* + * Register + * + * Data to be sent on forced transaction + */ +#define FPM_FPM_BB_FORCED_DATA 0x3000c + +/* Forced data */ +#define FPM_BB_FORCED_DATA_DATA_SHIFT 0 +#define FPM_BB_FORCED_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * set configuration for BB decoder + */ +#define FPM_FPM_BB_DECODE_CFG 0x30010 + +/* destination id */ +#define FPM_BB_DECODE_CFG_DEST_ID_SHIFT 0 +#define FPM_BB_DECODE_CFG_DEST_ID_MASK 0x3f + +/* Enable override */ +#define FPM_BB_DECODE_CFG_OVERRIDE_EN_MASK 0x40 + +/* route address */ +#define FPM_BB_DECODE_CFG_ROUTE_ADDR_SHIFT 7 +#define FPM_BB_DECODE_CFG_ROUTE_ADDR_MASK 0x1ff80 + + +/* + * Register + * + * Set SW addr to read FPM_BB FIFOs + */ +#define FPM_FPM_BB_DBG_CFG 0x30014 + +/* SW address for reading FPM BB RXFIFO */ +#define FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_SHIFT 0 +#define FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_MASK 0xf + +/* SW address for reading FPM BB TXFIFO */ +#define FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_SHIFT 4 +#define FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_MASK 0xf0 + +/* SW reset for FPM BB RXFIFO */ +#define FPM_BB_DBG_CFG_RXFIFO_SW_RST_MASK 0x100 + +/* SW reset for FPM BB TXFIFO */ +#define FPM_BB_DBG_CFG_TXFIFO_SW_RST_MASK 0x200 + + +/* + * Register - read-only + * + * Status of FPM BB RXFIFO + */ +#define FPM_FPM_BB_DBG_RXFIFO_STS 0x30018 + +/* FIFO is empty */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_MASK 0x1 + +/* FIFO is full */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_MASK 0x2 + +/* Used words */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_SHIFT 8 +#define FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_MASK 0x1f00 + +/* Write counter */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_SHIFT 16 +#define FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_MASK 0x1f0000 + +/* Write counter */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_SHIFT 24 +#define FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_MASK 0x1f000000 + + +/* + * Register - read-only + * + * Status of FPM BB TXFIFO + */ +#define FPM_FPM_BB_DBG_TXFIFO_STS 0x3001c + +/* FIFO is empty */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_MASK 0x1 + +/* FIFO is full */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_MASK 0x2 + +/* Used words */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_SHIFT 8 +#define FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_MASK 0x1f00 + +/* Write counter */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_SHIFT 16 +#define FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_MASK 0x1f0000 + +/* Write counter */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_SHIFT 24 +#define FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_MASK 0x1f000000 + + +/* + * Register - read-only + * + * Data from FPM BB RXFIFO bits [31: + * 0] + */ +#define FPM_FPM_BB_DBG_RXFIFO_DATA1 0x30020 + +/* data */ +#define FPM_BB_DBG_RXFIFO_DATA1_DATA_SHIFT 0 +#define FPM_BB_DBG_RXFIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB RXFIFO bits [39: + * 32] + */ +#define FPM_FPM_BB_DBG_RXFIFO_DATA2 0x30024 + +/* data */ +#define FPM_BB_DBG_RXFIFO_DATA2_DATA_SHIFT 0 +#define FPM_BB_DBG_RXFIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB TXFIFO bits [31: + * 0] + */ +#define FPM_FPM_BB_DBG_TXFIFO_DATA1 0x30028 + +/* data */ +#define FPM_BB_DBG_TXFIFO_DATA1_DATA_SHIFT 0 +#define FPM_BB_DBG_TXFIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB TXFIFO bits [63: + * 32] + */ +#define FPM_FPM_BB_DBG_TXFIFO_DATA2 0x3002c + +/* data */ +#define FPM_BB_DBG_TXFIFO_DATA2_DATA_SHIFT 0 +#define FPM_BB_DBG_TXFIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB TXFIFO bits [79: + * 64] + */ +#define FPM_FPM_BB_DBG_TXFIFO_DATA3 0x30030 + +/* data */ +#define FPM_BB_DBG_TXFIFO_DATA3_DATA_SHIFT 0 +#define FPM_BB_DBG_TXFIFO_DATA3_DATA_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_FPM_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_hash.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_hash.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_hash.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_hash.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,1039 @@ +#ifndef XRDP_REGS_HASH_H_ +#define XRDP_REGS_HASH_H_ + +/* relative to core */ +#define HASH_OFFSET_0 0xe20000 + +/* + * Register + * + * Power saving mode -detect that the accelerator has no activity and enter + * to power saving mode + */ +#define HASH_GENERAL_CFG_PWR_SAV_EN 0x0 + +/* . */ +#define HASH_GENERAL_CFG_PWR_SAV_EN_VALUE_MASK 0x1 + + +/* + * Register + * + * Determines the padding value added to keys according to the selected + * MASK + */ +#define HASH_GENERAL_CFG_PAD_HIGH 0x4 + +/* + * Determines the padding value added to keys according to the selected + * MASK +*/ +#define HASH_GENERAL_CFG_PAD_HIGH_VAL_SHIFT 0 +#define HASH_GENERAL_CFG_PAD_HIGH_VAL_MASK 0xfffffff + + +/* + * Register + * + * Determines the padding value added to keys according to the selected + * MASK + */ +#define HASH_GENERAL_CFG_PAD_LOW 0x8 + +/* + * Determines the padding value added to keys according to the selected + * MASK +*/ +#define HASH_GENERAL_CFG_PAD_LOW_VAL_SHIFT 0 +#define HASH_GENERAL_CFG_PAD_LOW_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * In case of multiple match this reg captures the hit indication per + * engine. + * This is a read clear reg. + */ +#define HASH_GENERAL_CFG_MULT_HIT_ERR 0xc + +/* + * In case of multiple match this reg captures the hit indication per + * engine. + * This is a read clear reg. +*/ +#define HASH_GENERAL_CFG_MULT_HIT_ERR_VAL_SHIFT 0 +#define HASH_GENERAL_CFG_MULT_HIT_ERR_VAL_MASK 0xf + + +/* + * Register + * + * Consist of chicken bit per specific fix + */ +#define HASH_GENERAL_CFG_UNDO_FIX 0x10 + +/* + * The bug fixed lacking in identification and reporting when a multiple + * hit occurs in the first search. +*/ +#define HASH_GENERAL_CFG_UNDO_FIX_FRST_MUL_HIT_MASK 0x1 + + +/* + * Register - read-only + * + * Number of key hitsThis reg is frozen when freeze bit asserted. + */ +#define HASH_PM_COUNTERS_HITS 0x100 + +/* . */ +#define HASH_PM_COUNTERS_HITS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HITS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of key searchesThis register is updated only when freeze register + * is not set + */ +#define HASH_PM_COUNTERS_SRCHS 0x104 + +/* . */ +#define HASH_PM_COUNTERS_SRCHS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_SRCHS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_MISS 0x108 + +/* . */ +#define HASH_PM_COUNTERS_MISS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_MISS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_1ST_ACS 0x10c + +/* . */ +#define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_2ND_ACS 0x110 + +/* . */ +#define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_3RD_ACS 0x114 + +/* . */ +#define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_4TH_ACS 0x118 + +/* . */ +#define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_MASK 0xffffffff + + +/* + * Register + * + * Freezes counters update - used to read all relevant counters at the same + * point. + */ +#define HASH_PM_COUNTERS_FRZ_CNT 0x150 + +/* Freezes counters update */ +#define HASH_PM_COUNTERS_FRZ_CNT_VAL_MASK 0x1 + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table : + * Configuration of LUT: + * table params + main flag + */ +#define HASH_LKUP_TBL_CFG_TBL_CFG(x) (0x200 + (x) * 0x10) + +/* + * Base address of the hash ram per engine. + * Varies between 0 to 1535Indicates from which address start looking the + * key. + * Note, base address must be aligned to table size - table size of 128 + * cant get base 64 +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_SHIFT 0 +#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_MASK 0x7ff + +/* + * Number of entries in the table per engine. + * Total entries should be multiplied with the number of engines - by 4. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_SHIFT 16 +#define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_MASK 0x70000 + +/* + * Max Search depth per engine. + * Supports up to 16 and cannot exceed table size. + * For performance requirement it should be limited to 4 +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_SHIFT 20 +#define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_MASK 0xf00000 + +/* + * CAM Search is enabled. + * If the key not found in the hash table and this flag enabled the key + * will be searched in the CAm. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_MASK 0x1000000 + +/* + * Direct lookup enable. + * Allows accessing the table without hash calculation- direct access. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_MASK 0x2000000 + +/* Hash function type */ +#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_MASK 0x4000000 + +/* + * If the key smaller than 60 bit, then it supported to store in the + * remaining bits an internal context data 3B or 6B. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_SHIFT 28 +#define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_MASK 0x30000000 + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table : + * key Mask on bits [59: + * 32]Key consist of 60-bit. + * by configuring mask the user can use different key lengths. + * if the key is smaller than 60 bit it is padded with constant value + * according the the mask register. + */ +#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH(x) (0x204 + (x) * 0x10) + +/* + * MASK HIGH applied on the 28 msb of the current part of key for the + * current search table. + * The value used for padding purpose and comparison to the hash content. +*/ +#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_SHIFT 0 +#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_MASK 0xfffffff + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table key Mask on bits [31: + * 0]Key consist of 60-bit. + * By configuring mask the user can use different key lengths. + * If the key is smaller than 60 bit it is padded with constant value + * according to the mask register. + */ +#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW(x) (0x208 + (x) * 0x10) + +/* + * MASK LOW applied on the 32 lsb of the current part of key for the + * current search table. + * The value used for padding purpose and comparison to the hash content. +*/ +#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_SHIFT 0 +#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table: + * LUT Context Table configurations (base addr + entry context size) + */ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG(x) (0x20c + (x) * 0x10) + +/* + * Context table base address in the RAM (6Bytes X 3264entries) . + * Indicates from which address start looking at the context. + * The address varies between 0 to 3264 (including 196 CAM entries)It + * should be calculated according below formula: + * Context_base_addr[12: + * 0] = sum of (table_size_per_engine*num_of_eng*context_size)/6 for all + * preceding tables +*/ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_SHIFT 0 +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_MASK 0xfff + +/* + * Indicates the first entry of the particular table in the context table. + * It should be calculated according to below formula: + * First_hash_index = sum of (table_size_per_engine*num_of_eng) for all + * preceding tables +*/ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_SHIFT 12 +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_MASK 0x1fff000 + +/* + * Context entry size (in the context RAM). + * Varies between 0B to 12B in steps of 3BContext may also be extracted + * directly from Look-up Table (up to 6B). +*/ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_SHIFT 28 +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_MASK 0x70000000 + + +/* + * Register + * + * Look-up table: + * LUT Context Table configurations (base addr + entry context size) + */ +#define HASH_CAM_CFG_CNTXT_CFG 0x400 + +/* + * Context table base address in the RAM (6Bytes X 3264entries) . + * Indicates from which address start looking at the context. + * The address varies between 0 to 3264 (including 196 CAM entries)It + * should be calculated according below formula: + * Context_base_addr[12: + * 0] = sum of (table_size*context_size)/6 for all preceding tables +*/ +#define HASH_CAM_CFG_CNTXT_CFG_BASE_ADDRESS_SHIFT 0 +#define HASH_CAM_CFG_CNTXT_CFG_BASE_ADDRESS_MASK 0xfff + + +/* + * Register + * + * TCAM Operation: + * 0 - CAM READ1 - CAM Write2 - CAM Compare3 - CAM valid bit resetWriting + * to this register triggers the operation. + * All other relevant register should be ready before SW writes to this + * register. + */ +#define HASH_CAM_INDIRECT_OP 0x800 + +/* . */ +#define HASH_CAM_INDIRECT_OP_CMD_SHIFT 0 +#define HASH_CAM_INDIRECT_OP_CMD_MASK 0xf + + +/* + * Register - read-only + * + * Raised when the CAM operation is completed (cleared by HW on writing to + * the OPERATION register) + */ +#define HASH_CAM_INDIRECT_OP_DONE 0x804 + +/* . */ +#define HASH_CAM_INDIRECT_OP_DONE_VAL_MASK 0x1 + + +/* + * Register
+ * + * Key Address to be used in RD/WR opoerations. + */ +#define HASH_CAM_INDIRECT_ADDR 0x808 + +/* + * This bit indicate if the operation (RD/WR) is performed on the key0 or + * key1 part of the entry +*/ +#define HASH_CAM_INDIRECT_ADDR_KEY1_IND_MASK 0x1 + +/* Address of the entry */ +#define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_SHIFT 1 +#define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_MASK 0x7e + + +/* + * Register + * + * Valid value to be written - this value is relevant during write + * operation on key0. + */ +#define HASH_CAM_INDIRECT_VLID_IN 0x80c + +/* . */ +#define HASH_CAM_INDIRECT_VLID_IN_VALID_MASK 0x1 + + +/* + * Register + * + * Valid value read from the CAM - this value is relevant during read + * operation on key0. + */ +#define HASH_CAM_INDIRECT_VLID_OUT 0x814 + +/* . */ +#define HASH_CAM_INDIRECT_VLID_OUT_VALID_MASK 0x1 + + +/* + * Register - read-only + * + * The result of a search operation + */ +#define HASH_CAM_INDIRECT_RSLT 0x818 + +/* indicate if a match was found */ +#define HASH_CAM_INDIRECT_RSLT_MATCH_MASK 0x1 + +/* index related to a match result */ +#define HASH_CAM_INDIRECT_RSLT_INDEX_SHIFT 4 +#define HASH_CAM_INDIRECT_RSLT_INDEX_MASK 0x3f0 + + +/* + * Registers - is [ 0 => 1 ] + * + * Key to be used in Write/Compare operations. + * The Key is 64bit long and is represented by 2 registers. + * The lower address register corresponds to the most significant bits of + * the key. + */ +#define HASH_CAM_INDIRECT_KEY_IN(x) (0x820 + (x) * 0x4) + +/* . */ +#define HASH_CAM_INDIRECT_KEY_IN_VALUE_SHIFT 0 +#define HASH_CAM_INDIRECT_KEY_IN_VALUE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Key returned from the CAM in a read operation. + * The Key is 64bit long and is represented by 2 registers. + * The lower address register correspond to the most significant bits of + * the key. + */ +#define HASH_CAM_INDIRECT_KEY_OUT(x) (0x840 + (x) * 0x4) + +/* . */ +#define HASH_CAM_INDIRECT_KEY_OUT_VALUE_SHIFT 0 +#define HASH_CAM_INDIRECT_KEY_OUT_VALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * . + */ +#define HASH_CAM_BIST_BIST_STATUS 0x900 + +/* . */ +#define HASH_CAM_BIST_BIST_STATUS_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_STATUS_VALUE_MASK 0xffffffff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN 0x904 + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_MASK 0x1 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_DATA 0x908 + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_MASK 0xffffffff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL 0x90c + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_DATA_VALID 0x910 + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_MASK 0x1 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_EN 0x914 + +/* . */ +#define HASH_CAM_BIST_BIST_EN_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_EN_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_MODE 0x918 + +/* . */ +#define HASH_CAM_BIST_BIST_MODE_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_MODE_VALUE_MASK 0x3 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_RST_L 0x91c + +/* . */ +#define HASH_CAM_BIST_BIST_RST_L_VALUE_MASK 0x1 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT 0x920 + +/* . */ +#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_DBG_EN 0x924 + +/* . */ +#define HASH_CAM_BIST_DBG_EN_VALUE_SHIFT 0 +#define HASH_CAM_BIST_DBG_EN_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_CASCADE_SELECT 0x928 + +/* . */ +#define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_MASK 0x7 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_BLOCK_SELECT 0x92c + +/* . */ +#define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_MASK 0xf + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_REPAIR_ENABLE 0x930 + +/* . */ +#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_MASK 0x1 + + +/* + * Register + * + * This register contains the current active hash interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define HASH_INTR_CTRL_ISR 0xa00 + +/* Command cfg field is invalid (equals to 0) */ +#define HASH_INTR_CTRL_ISR_INVLD_CMD_MASK 0x1 + +/* + * During the search process same key was found a valid in multiple + * engines. +*/ +#define HASH_INTR_CTRL_ISR_MULT_MATCH_MASK 0x2 + +/* hash table index over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_MASK 0x4 + +/* hash table over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_MASK 0x8 + +/* hash table index over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_MASK 0x10 + +/* hash table index over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_MASK 0x20 + +/* Context table index over flow */ +#define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_MASK 0x40 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define HASH_INTR_CTRL_ISM 0xa04 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define HASH_INTR_CTRL_ISM_ISM_SHIFT 0 +#define HASH_INTR_CTRL_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define HASH_INTR_CTRL_IER 0xa08 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define HASH_INTR_CTRL_IER_IEM_SHIFT 0 +#define HASH_INTR_CTRL_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define HASH_INTR_CTRL_ITR 0xa0c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define HASH_INTR_CTRL_ITR_IST_SHIFT 0 +#define HASH_INTR_CTRL_ITR_IST_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG0 0xa30 + +/* read debug register */ +#define HASH_DEBUG_DBG0_VAL_SHIFT 0 +#define HASH_DEBUG_DBG0_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG1 0xa34 + +/* read debug register */ +#define HASH_DEBUG_DBG1_VAL_SHIFT 0 +#define HASH_DEBUG_DBG1_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG2 0xa38 + +/* read debug register */ +#define HASH_DEBUG_DBG2_VAL_SHIFT 0 +#define HASH_DEBUG_DBG2_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG3 0xa3c + +/* read debug register */ +#define HASH_DEBUG_DBG3_VAL_SHIFT 0 +#define HASH_DEBUG_DBG3_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG4 0xa40 + +/* read debug register */ +#define HASH_DEBUG_DBG4_VAL_SHIFT 0 +#define HASH_DEBUG_DBG4_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG5 0xa44 + +/* read debug register */ +#define HASH_DEBUG_DBG5_VAL_SHIFT 0 +#define HASH_DEBUG_DBG5_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG6 0xa48 + +/* read debug register */ +#define HASH_DEBUG_DBG6_VAL_SHIFT 0 +#define HASH_DEBUG_DBG6_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG7 0xa4c + +/* read debug register */ +#define HASH_DEBUG_DBG7_VAL_SHIFT 0 +#define HASH_DEBUG_DBG7_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG8 0xa50 + +/* read debug register */ +#define HASH_DEBUG_DBG8_VAL_SHIFT 0 +#define HASH_DEBUG_DBG8_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG9 0xa54 + +/* read debug register */ +#define HASH_DEBUG_DBG9_VAL_SHIFT 0 +#define HASH_DEBUG_DBG9_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG10 0xa58 + +/* read debug register */ +#define HASH_DEBUG_DBG10_VAL_SHIFT 0 +#define HASH_DEBUG_DBG10_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG11 0xa5c + +/* read debug register */ +#define HASH_DEBUG_DBG11_VAL_SHIFT 0 +#define HASH_DEBUG_DBG11_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG12 0xa60 + +/* read debug register */ +#define HASH_DEBUG_DBG12_VAL_SHIFT 0 +#define HASH_DEBUG_DBG12_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG13 0xa64 + +/* read debug register */ +#define HASH_DEBUG_DBG13_VAL_SHIFT 0 +#define HASH_DEBUG_DBG13_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG14 0xa68 + +/* read debug register */ +#define HASH_DEBUG_DBG14_VAL_SHIFT 0 +#define HASH_DEBUG_DBG14_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG15 0xa6c + +/* read debug register */ +#define HASH_DEBUG_DBG15_VAL_SHIFT 0 +#define HASH_DEBUG_DBG15_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG16 0xa70 + +/* read debug register */ +#define HASH_DEBUG_DBG16_VAL_SHIFT 0 +#define HASH_DEBUG_DBG16_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG17 0xa74 + +/* read debug register */ +#define HASH_DEBUG_DBG17_VAL_SHIFT 0 +#define HASH_DEBUG_DBG17_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG18 0xa78 + +/* read debug register */ +#define HASH_DEBUG_DBG18_VAL_SHIFT 0 +#define HASH_DEBUG_DBG18_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG19 0xa7c + +/* read debug register */ +#define HASH_DEBUG_DBG19_VAL_SHIFT 0 +#define HASH_DEBUG_DBG19_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG20 0xa80 + +/* read debug register */ +#define HASH_DEBUG_DBG20_VAL_SHIFT 0 +#define HASH_DEBUG_DBG20_VAL_MASK 0xffffffff + + +/* + * Register + * + * debug select mux + */ +#define HASH_DEBUG_DBG_SEL 0xa84 + +/* debug sel */ +#define HASH_DEBUG_DBG_SEL_VAL_SHIFT 0 +#define HASH_DEBUG_DBG_SEL_VAL_MASK 0x1f + + +/* + * Registers - is [ 0 => 65 ] + * + * Each bit in the ram represents hash/CAM entry. + * (6K hash entries + 64 CAM entries)/32= 194 rowsBit 0 at the ram + * corresponds to entry 0 (eng0), Bit 1 at the ram corresponds to entry 1 + * (eng1), and so on. + * . + */ +#define HASH_AGING_RAM_AGING(x) (0x7000 + (x) * 0x4) + +/* . */ +#define HASH_AGING_RAM_AGING_DATA_SHIFT 0 +#define HASH_AGING_RAM_AGING_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1215 ] + * + * 24 most significant bits of an entry (first 3B) + */ +#define HASH_CONTEXT_RAM_CONTEXT_47_24(x) (0x8000 + (x) * 0x8) + +/* . */ +#define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_SHIFT 0 +#define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_MASK 0xffffff + + +/* + * Registers - is [ 0 => 1215 ] + * + * 24 least significant bits of an entry (second 3B) + */ +#define HASH_CONTEXT_RAM_CONTEXT_23_0(x) (0x8004 + (x) * 0x8) + +/* . */ +#define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_SHIFT 0 +#define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_MASK 0xffffff + + +/* + * Registers - is [ 0 => 2047 ] + * + * Includes the MSB field of the hash entry + */ +#define HASH_RAM_ENG_HIGH(x) (0x10000 + (x) * 0x8) + +/* + * This field contains one of the two: + * key extension or internal context data. + * It defined by table configuration. +*/ +#define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_SHIFT 0 +#define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 2047 ] + * + * Includes the MSB field of the hash entry + */ +#define HASH_RAM_ENG_LOW(x) (0x10004 + (x) * 0x8) + +/* + * Indicates not to search at this entry due to the ongoing update of the + * entry. +*/ +#define HASH_RAM_ENG_LOW_SKP_MASK 0x1 + +/* + * Determines the table config number, between 1-7. + * Config 0 is used to indicate invalid entry +*/ +#define HASH_RAM_ENG_LOW_CFG_SHIFT 1 +#define HASH_RAM_ENG_LOW_CFG_MASK 0xe + +/* + * Includes the first part of the key. + * This field is preserved for key use only. +*/ +#define HASH_RAM_ENG_LOW_KEY_11_0_SHIFT 4 +#define HASH_RAM_ENG_LOW_KEY_11_0_MASK 0xfff0 + +/* + * This field contains one of the two: + * key extension or internal context data. + * It defined by table configuration. +*/ +#define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_SHIFT 16 +#define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_MASK 0xffff0000 + + +#endif /* ! XRDP_REGS_HASH_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_natc.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_natc.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_natc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_natc.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,1511 @@ +#ifndef XRDP_REGS_NATC_H_ +#define XRDP_REGS_NATC_H_ + +/* relative to core */ +#define NATC_OFFSET_0 0xe50000 + + +/* + * + * register set NATC + * + */ + +/* + * Register + * + * NAT Cache Control and Status Register. + */ +#define NATC_CONTROL_STATUS 0x0 + +/* + * Enables NAT table offload to DDR functionality. + * NATC_CONTROL_STATUS2 register should be configured before enabling this + * feature. +*/ +#define CONTROL_STATUS_DDR_ENABLE_MASK 0x80000000 + +/* + * Default behavior for an ADD command is to do a LOOKUP first to see if + * the entrywith the same key already exists and replace it; this is to + * avoid having duplicatedentries in the table for ADD command. + * When this bit is set an ADD command willeither replace the entry with + * the matched key or add an entry to an empty entrydepending on whichever + * one is encountered first during multi-hash. + * Enablingthis bit speeds up the ADD command. +*/ +#define CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_MASK 0x40000000 + +#define CONTROL_STATUS_UNUSED4_SHIFT 28 +#define CONTROL_STATUS_UNUSED4_MASK 0x30000000 +/* + * Swap 64-bit word within 128-bit word for DDR memory read/write + * accesses(i. + * e. + * , [127: + * 0] becomes {[63: + * 0], [127: + * 64]}). + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_MASK 0x8000000 + +/* + * Swap 32-bit word within 64-bit word for statistics (counter) memory + * accesses(i. + * e. + * , [63: + * 0] becomes {[31: + * 0], [63: + * 32]}) +*/ +#define CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_MASK 0x4000000 + +/* + * Reverse bytes within 32-bit word for statistics (counter) memory + * accesses(i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}) +*/ +#define CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x2000000 + +/* + * Swap all bytes on DDR interface. + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_MASK 0x1000000 + +#define CONTROL_STATUS_UNUSED3_MASK 0x800000 +/* + * Swap 32-bit word within 64-bit word for key_result register accesses(i. + * e. + * , [63: + * 0] becomes {[31: + * 0], [63: + * 32]}) +*/ +#define CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_MASK 0x400000 + +/* + * Reverse bytes within 32-bit word for key_result register accesses(i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}) +*/ +#define CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x200000 + +#define CONTROL_STATUS_UNUSED2_SHIFT 18 +#define CONTROL_STATUS_UNUSED2_MASK 0x1c0000 +/* + * This bit is only valid when CACHE_UPDATE_ON_DDR_MISS bit is set to 1. + * This bit determines whether pending FIFO entry will be checked + * todetermine whether cache update on DDR miss will happen or not. + * 1h: + * Enable; DDR miss entry fetched from DDR will be cached if pending + * FIFOcontains entries which have the same hash value as DDR miss entry. + * 0h: + * Disable; DDR miss entry fetched from DDR will always be cached. +*/ +#define CONTROL_STATUS_PENDING_FIFO_ENTRY_CHECK_ENABLE_MASK 0x20000 + +/* + * This bit determines whether DDR lookup will cache the entry for DDR miss + * entry. + * 1h: + * Enable; DDR miss entry fetched from DDR will be cached. + * 0h: + * Disable; DDR miss entry fetched from DDR will not be cached. +*/ +#define CONTROL_STATUS_CACHE_UPDATE_ON_DDR_MISS_MASK 0x10000 + +/* + * 0h: + * Enable DDR lookup when cache misses using register interface lookup1h: + * Disable DDR lookup when cache misses using register interface lookup +*/ +#define CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_MASK 0x8000 + +/* Reset regfile_FIFO. */ +#define CONTROL_STATUS_REGFILE_FIFO_RESET_MASK 0x4000 + +/* + * Hash algorithm used for internal caching0h: + * 32-bit rolling XOR hash is used as cache hash function. + * 1h: + * CRC32 hash is used as cache hash function. + * CRC32 is reduced to 10-bit usingthe same method as in 32-bit rolling XOR + * hash. + * 2h: + * CRC32 hash is used as cache hash function. + * CRC32[9: + * 0] is used as hash value3h: + * CRC32 hash is used as cache hash function. + * CRC32[25: + * 16] is used as hash value. +*/ +#define CONTROL_STATUS_NAT_HASH_MODE_SHIFT 12 +#define CONTROL_STATUS_NAT_HASH_MODE_MASK 0x3000 + +/* + * Maximum number of multi-hash iterationsValue of 0 is 1 iteration, 1 is 2 + * iterations, 2 is 3 iterations, etc. +*/ +#define CONTROL_STATUS_MULTI_HASH_LIMIT_SHIFT 8 +#define CONTROL_STATUS_MULTI_HASH_LIMIT_MASK 0xf00 + +/* + * Decrement Count Wraparound Enable0h: + * Do not decrement counters for decrement command when counters reach 01h: + * Always decrement counters for decrement command; will wrap around from 0 + * to all 1's +*/ +#define CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_MASK 0x80 + +/* + * NAT Arbitration MechanismRound-robin arbitrationStrict priority + * arbitrationlisted from highest to lowest priority -- NAT0, NAT1, NAT2, + * NAT3, RunnerStrict priority arbitration (priority reversed from + * above)listed from highest to lowest priority -- Runner, NAT3, NAT2, + * NAT1, NAT0 +*/ +#define CONTROL_STATUS_NAT_ARB_ST_SHIFT 5 +#define CONTROL_STATUS_NAT_ARB_ST_MASK 0x60 + +/* + * Enables incrementing or decrementing hit counter by 1 and byte counter + * by PKT_LENon successful lookups using register interfaceBY default, + * counters only increment on successful lookups on Runner interface +*/ +#define CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_MASK 0x10 + +/* + * Disables clearing counters when an existing entry is replaced by ADD + * command +*/ +#define CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_MASK 0x8 + +/* Disables counters from incrementing when hit */ +#define CONTROL_STATUS_NATC_SMEM_DISABLE_MASK 0x4 + +/* + * Enables all NATC state machines and input FIFO;Clearing this bit will + * halt all state machines gracefully to idle states,all outstanding + * transactions in the FIFO will remain in the FIFO and NATCwill stop + * accepting new commands; All configuration registers should beconfigured + * before enabling this bit. +*/ +#define CONTROL_STATUS_NATC_ENABLE_MASK 0x2 + +/* + * Self Clearing Block Reset (including resetting all registers to default + * values) +*/ +#define CONTROL_STATUS_NATC_RESET_MASK 0x1 + + +/* + * Register + * + * NAT Cache Control and Status Register + */ +#define NATC_CONTROL_STATUS2 0x4 + +/* Reverse bytes within 18-bit DDR hash value */ +#define CONTROL_STATUS2_DDR_HASH_SWAP_MASK 0x80000000 + +/* + * Hash algorithm used for DDR lookupHash value is DDR table size + * dependent. + * 0h: + * 32-bit rolling XOR hash is used as DDR hash function. + * It is reduced to N-bitDDR table size is 8K, N = 13. + * DDR table size is 16K, N = 14. + * DDR table size is 32K, N = 15. + * DDR table size is 64K, N = 16. + * DDR table size is 128K, N = 17. + * DDR table size is 256K, N = 18. + * 1h: + * CRC32 hash is used as DDR hash function. + * CRC32 is reduced to N-bit usingthe same method as in 32-bit rolling XOR + * hash. + * DDR table size is 8K, N = 13. + * DDR table size is 16K, N = 14. + * DDR table size is 32K, N = 15. + * DDR table size is 64K, N = 16. + * DDR table size is 128K, N = 17. + * DDR table size is 256K, N = 18. + * 2h: + * CRC32 hash is used as DDR hash function. + * CRC32[N: + * 0] is used as hash valueDDR table size is 8K, N = 12. + * DDR table size is 16K, N = 13. + * DDR table size is 32K, N = 14. + * DDR table size is 64K, N = 15. + * DDR table size is 128K, N = 16. + * DDR table size is 256K, N = 17. + * 3h: + * CRC32 hash is used as DDR hash function. + * CRC32[31: + * N] is used as hash valueDDR table size is 8K, N = 19. + * DDR table size is 16K, N = 18. + * DDR table size is 32K, N = 17. + * DDR table size is 64K, N = 16. + * DDR table size is 128K, N = 15. + * DDR table size is 256K, N = 14. +*/ +#define CONTROL_STATUS2_DDR_HASH_MODE_SHIFT 29 +#define CONTROL_STATUS2_DDR_HASH_MODE_MASK 0x60000000 + +/* + * Swap 32-bit word within 64-bit word for DDR memory read/write + * accesses(i. + * e. + * , [63: + * 0] becomes {[31: + * 0], [63: + * 32]}). + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_MASK 0x10000000 + +/* + * Reverse bytes within 32-bit word for DDR memory read/write accesses(i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}). + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x8000000 + +/* (debug command) Do not set this bit to 1 */ +#define CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_MASK 0x4000000 + +/* + * Timer tick for pseudo-LRUTimer is incremented on every system clock + * cycleTimer is incremented on every packet arrival to NAT block +*/ +#define CONTROL_STATUS2_AGE_TIMER_TICK_MASK 0x2000000 + +/* + * Timer value used for pseudo-LRU;When timer fires the 8-bit age value of + * every entry in the cache isdecremented (cap at 0). + * The entry with lower value isthe older entry. + * The default setting keeps track of 2s age at~7ms resolution. + * 0: + * 1 tick1: + * 2 ticks2: + * 4 ticks3: + * 8 ticks4: + * 16 ticks. + * .. + * .31: + * 2^31 TICKS +*/ +#define CONTROL_STATUS2_AGE_TIMER_SHIFT 20 +#define CONTROL_STATUS2_AGE_TIMER_MASK 0x1f00000 + +/* + * Replacement algorithm for cachingLowest-multi-hash-iteration number is + * used to select the final replacemententry if multiple entries were + * chosen by the selected algorithm. + * Forinstance, if HIT_COUNT algorithm were selected, and 2nd, 3rd and + * 7thentry all have the same hit_count values, 2nd entry will be evicted. + * If CACHE_DISABLE or EVICTION_DISABLE is set, HIT_COUNT algorithmcan only + * keep track of the hit count while the entry is in the cache. + * When the entry is evicted hit count for that entry is lost. + * Replacement algorithm prioritizes pseudo-LRU over + * lowest-hit-countReplacement algorithm prioritizes lowest-hit-count over + * pseudo-LRUReplacement algorithm uses pseudo-LRUReplacement algorithm + * uses least-hit-countReplacement algorithm prioritizes pseudo-LRU over + * pseudo-randomReplacement algorithm prioritizes lowest-hit-count over + * pseudo-randomReplacement algorithm uses pseudo-random + * algorithmReplacement algorithm prioritizes highest-hit-count + * overmost-recently-useReplacement algorithm prioritizes pseudo-LRU over + * lowest-byte-countReplacement algorithm prioritizes lowest-byte-count + * over pseudo-LRUReplacement algorithm uses least-byte-countReplacement + * algorithm prioritizes lowest-byte-count over pseudo-randomReplacement + * algorithm prioritizes highest-byte-count overmost-recently-use +*/ +#define CONTROL_STATUS2_CACHE_ALGO_SHIFT 16 +#define CONTROL_STATUS2_CACHE_ALGO_MASK 0xf0000 + +#define CONTROL_STATUS2_UNUSED1_SHIFT 8 +#define CONTROL_STATUS2_UNUSED1_MASK 0xff00 +#define CONTROL_STATUS2_UNUSED0_SHIFT 6 +#define CONTROL_STATUS2_UNUSED0_MASK 0xc0 +/* + * This bit determines whether register interface lookup will cache the + * entry from DDR1h: + * Enable; entry fetched from DDR will be cached using register interface + * lookup command0h: + * Disable; entry fetched from DDR will not be cached using register + * interface lookup command +*/ +#define CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_MASK 0x20 + +/* + * Reverse bytes within 32-bit word for DDR counters on read/write + * accesses. + * (i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}) +*/ +#define CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x10 + +#define CONTROL_STATUS2_UNUSED5_MASK 0x8 +/* + * (debug command) Do not set this bit to 1Enable replacing existing cache + * counters with DDR fetched entry +*/ +#define CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_MASK 0x4 + +/* (debug command) Do not set this bit to 1 */ +#define CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_MASK 0x2 + +/* + * Disable counter eviction to DDR; this bit is effective when + * CACHE_DISABLE is 0Set this bit when counters are not used; NATC + * performance will improve dueto reduced DDR accesses; CACHE_ALGO should + * not use HIT_COUNT and BYTE_COUNT +*/ +#define CONTROL_STATUS2_EVICTION_DISABLE_MASK 0x1 + + +/* + * Register + * + * NAT Cache Table Control Register + */ +#define NATC_TABLE_CONTROL 0x8 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 7lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_MASK 0x800000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 6lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_MASK 0x400000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 5lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_MASK 0x200000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 4lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_MASK 0x100000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 3lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_MASK 0x80000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 2lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_MASK 0x40000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 1lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_MASK 0x20000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 0lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_MASK 0x10000 + +/* + * Length of the key for DDR table 70h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL7_MASK 0x8000 + +/* + * DDR table 7 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL7_MASK 0x4000 + +/* + * Length of the key for DDR table 60h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL6_MASK 0x2000 + +/* + * DDR table 6 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL6_MASK 0x1000 + +/* + * Length of the key for DDR table 50h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL5_MASK 0x800 + +/* + * DDR table 5 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL5_MASK 0x400 + +/* + * Length of the key for DDR table 40h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL4_MASK 0x200 + +/* + * DDR table 4 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL4_MASK 0x100 + +/* + * Length of the key for DDR table 30h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL3_MASK 0x80 + +/* + * DDR table 3 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL3_MASK 0x40 + +/* + * Length of the key for DDR table 20h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL2_MASK 0x20 + +/* + * DDR table 2 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL2_MASK 0x10 + +/* + * Length of the key for DDR table 10h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL1_MASK 0x8 + +/* + * DDR table 1 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL1_MASK 0x4 + +/* + * Length of the key for DDR table 00h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL0_MASK 0x2 + +/* + * DDR table 0 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL0_MASK 0x1 + + + +/* + * + * register sets NATC_CFG, is [ 0 => 8 ] + * + */ + +/* + * Register + * + * Lower 32-bit of the base address of DDR key tableAddress must be 64-bit + * aligned (bit 2 through 0 are zero's)In order maximum number of key + * fetches,for 16-byte key, bit 3 should be 0 to align at 16 byte + * boundaryfor 32-byte key, bit 3 and 4 should be 0 to align at 32 bytes + * boundary + */ +#define NATC_CFG_DDR_KEY_BASE_ADDR_LO(r) (0x2d0 + (r) * 0x10) + +#define DDR_KEY_BASE_ADDR_LO_BAR_SHIFT 3 +#define DDR_KEY_BASE_ADDR_LO_BAR_MASK 0xfffffff8 +#define DDR_KEY_BASE_ADDR_LO_ZEROS_SHIFT 0 +#define DDR_KEY_BASE_ADDR_LO_ZEROS_MASK 0x7 + +/* + * Register + * + * Upper 8-bit of the base address of DDR key tableFor 32-bit system this + * field should be left as 0 + */ +#define NATC_CFG_DDR_KEY_BASE_ADDR_HI(r) (0x2d4 + (r) * 0x10) + +#define DDR_KEY_BASE_ADDR_HI_ZEROS_SHIFT 8 +#define DDR_KEY_BASE_ADDR_HI_ZEROS_MASK 0xffffff00 +#define DDR_KEY_BASE_ADDR_HI_BAR_SHIFT 0 +#define DDR_KEY_BASE_ADDR_HI_BAR_MASK 0xff + +/* + * Register + * + * Lower 32-bit of the base address of DDR context tableAddress must be + * 64-bit aligned (bit 2 through 0 are zero's) + */ +#define NATC_CFG_DDR_RESULT_BASE_ADDR_LO(r) (0x2d8 + (r) * 0x10) + +#define DDR_RESULT_BASE_ADDR_LO_BAR_SHIFT 3 +#define DDR_RESULT_BASE_ADDR_LO_BAR_MASK 0xfffffff8 +#define DDR_RESULT_BASE_ADDR_LO_ZEROS_SHIFT 0 +#define DDR_RESULT_BASE_ADDR_LO_ZEROS_MASK 0x7 + +/* + * Register + * + * Upper 8-bit of the base address of DDR context tableFor 32-bit system + * this field should be left as 0 + */ +#define NATC_CFG_DDR_RESULT_BASE_ADDR_HI(r) (0x2dc + (r) * 0x10) + +#define DDR_RESULT_BASE_ADDR_HI_ZEROS_SHIFT 8 +#define DDR_RESULT_BASE_ADDR_HI_ZEROS_MASK 0xffffff00 +#define DDR_RESULT_BASE_ADDR_HI_BAR_SHIFT 0 +#define DDR_RESULT_BASE_ADDR_HI_BAR_MASK 0xff + + +/* + * + * register sets NATC_CTRS, is [ 0 => 8 ] + * + */ + +/* + * Register + * + * NATC CACHE HIT COUNT + */ +#define NATC_CTRS_CACHE_HIT_COUNT(r) (0x350 + (r) * 0x14) + +/* 32-bit total cache hit count value for statistics collection */ +#define CACHE_HIT_COUNT_CACHE_HIT_COUNT_SHIFT 0 +#define CACHE_HIT_COUNT_CACHE_HIT_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NATC CACHE MISS COUNT + */ +#define NATC_CTRS_CACHE_MISS_COUNT(r) (0x354 + (r) * 0x14) + +/* 32-bit total cache miss count value for statistics collection */ +#define CACHE_MISS_COUNT_CACHE_MISS_COUNT_SHIFT 0 +#define CACHE_MISS_COUNT_CACHE_MISS_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NATC DDR REQUEST COUNT + */ +#define NATC_CTRS_DDR_REQUEST_COUNT(r) (0x358 + (r) * 0x14) + +/* 32-bit total DDR request count value for statistics collection */ +#define DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_SHIFT 0 +#define DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NATC DDR EVICT COUNT + */ +#define NATC_CTRS_DDR_EVICT_COUNT(r) (0x35c + (r) * 0x14) + +/* + * 32-bit total DDR evict count value for statistics collection. + * It does not include the flush command evict count. +*/ +#define DDR_EVICT_COUNT_DDR_EVICT_COUNT_SHIFT 0 +#define DDR_EVICT_COUNT_DDR_EVICT_COUNT_MASK 0xffffffff + + +/* + * Register + * + * DDR BLOCK COUNT + */ +#define NATC_CTRS_DDR_BLOCK_COUNT(r) (0x360 + (r) * 0x14) + +/* 32-bit total DDR blocked access count value for statistics collection */ +#define DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_SHIFT 0 +#define DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_MASK 0xffffffff + + + +/* + * + * register set NATC_DDR_CFG + * + */ + +/* + * Register + * + * DDR Size Register + */ +#define NATC_DDR_CFG_SIZE 0x410 + +/* + * Number of entries in DDR table 7See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL7_SHIFT 21 +#define SIZE_DDR_SIZE_TBL7_MASK 0xe00000 + +/* + * Number of entries in DDR table 6See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL6_SHIFT 18 +#define SIZE_DDR_SIZE_TBL6_MASK 0x1c0000 + +/* + * Number of entries in DDR table 5See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL5_SHIFT 15 +#define SIZE_DDR_SIZE_TBL5_MASK 0x38000 + +/* + * Number of entries in DDR table 4See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL4_SHIFT 12 +#define SIZE_DDR_SIZE_TBL4_MASK 0x7000 + +/* + * Number of entries in DDR table 3See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL3_SHIFT 9 +#define SIZE_DDR_SIZE_TBL3_MASK 0xe00 + +/* + * Number of entries in DDR table 2See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL2_SHIFT 6 +#define SIZE_DDR_SIZE_TBL2_MASK 0x1c0 + +/* + * Number of entries in DDR table 10=8k; 1=16k; 2=32k; 3=64k; 4=128k; + * 5=256k; 6=invalid; 7=invalidSee description of DDR_SIZE_TBL0 +*/ +#define SIZE_DDR_SIZE_TBL1_SHIFT 3 +#define SIZE_DDR_SIZE_TBL1_MASK 0x38 + +/* + * Number of entries in DDR table 0Value of 6 or above is invalidTo compute + * the actual size of the table, add DDR_BINS_PER_BUCKET fieldto the table + * size selection;For instance, if DDR_BINS_PER_BUCKET is 3 (4 bins per + * bucket)and DDR_size is 3 (64k entries), the actual size of the table in + * DDR is(64*1024+3) multiply by total length (TOTAL_LEN) of key and + * context in bytesExtra 3 entries are used to store collided entries of + * the last entryvalue 256k 5256k entriesvalue 128k 4128k entriesvalue 64k + * 364k entriesvalue 32k 232k entriesvalue 16k 116k entriesvalue 8k 08k + * entriesdefault 0h +*/ +#define SIZE_DDR_SIZE_TBL0_SHIFT 0 +#define SIZE_DDR_SIZE_TBL0_MASK 0x7 + + +/* + * Register + * + * DDR Bins Per Bucket Register 0 + */ +#define NATC_DDR_CFG_BINS_PER_BUCKET_0 0x414 + +/* + * Number of entries per bucket in DDR table 3See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_SHIFT 24 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_MASK 0xff000000 + +/* + * Number of entries per bucket in DDR table 2See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_SHIFT 16 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_MASK 0xff0000 + +/* + * Number of entries per bucket in DDR table 1See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_SHIFT 8 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_MASK 0xff00 + +/* + * Number of entries per bucket in DDR table 0This is limited by bus max + * burst size. + * For instance, ifUBUS supports max burst size of 128 bytes, key length is + * 16bytes, maximum DDR_BINS_PER_BUCKET that can be programmedis 128 bytes + * / 16-bytes (bytes per bin) = 8 entries0h: + * 1 entry1h: + * 2 entries2h: + * 3 entries3h: + * 4 entries4h: + * 5 entries5h: + * 6 entries6h: + * 7 entries7h: + * 8 entries. + * .. + * .. + * .. + * .. + * .. + * .. +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_SHIFT 0 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_MASK 0xff + + +/* + * Register + * + * DDR Bins Per Bucket Register 1 + */ +#define NATC_DDR_CFG_BINS_PER_BUCKET_1 0x418 + +/* + * Number of entries per bucket in DDR table 7See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_SHIFT 24 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_MASK 0xff000000 + +/* + * Number of entries per bucket in DDR table 6See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_SHIFT 16 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_MASK 0xff0000 + +/* + * Number of entries per bucket in DDR table 5See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_SHIFT 8 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_MASK 0xff00 + +/* + * Number of entries per bucket in DDR table 4See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_SHIFT 0 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_MASK 0xff + + +/* + * Register + * + * DDR TABLE Total Length Register + */ +#define NATC_DDR_CFG_TOTAL_LEN 0x41c + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 7See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL7_SHIFT 21 +#define TOTAL_LEN_TOTAL_LEN_TBL7_MASK 0xe00000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 6See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL6_SHIFT 18 +#define TOTAL_LEN_TOTAL_LEN_TBL6_MASK 0x1c0000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 5See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL5_SHIFT 15 +#define TOTAL_LEN_TOTAL_LEN_TBL5_MASK 0x38000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 4See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL4_SHIFT 12 +#define TOTAL_LEN_TOTAL_LEN_TBL4_MASK 0x7000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 3See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL3_SHIFT 9 +#define TOTAL_LEN_TOTAL_LEN_TBL3_MASK 0xe00 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 2See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL2_SHIFT 6 +#define TOTAL_LEN_TOTAL_LEN_TBL2_MASK 0x1c0 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 1See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL1_SHIFT 3 +#define TOTAL_LEN_TOTAL_LEN_TBL1_MASK 0x38 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 0The context length (including 8-byte counters) is calculated by + * TOTAL_LEN minus KEY_LENThe maximum value should not exceed hardware + * capability. + * For instance, most projects have max of 80-bytes and BCM63158 has max + * value of 144-byte. + * 0h: + * 48-byte1h: + * 64-byte2h: + * 80-byte3h: + * 96-byte4h: + * 112-byte5h: + * 128-byte6h: + * 144-byte7h: + * 160-byte +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL0_SHIFT 0 +#define TOTAL_LEN_TOTAL_LEN_TBL0_MASK 0x7 + + +/* + * Register + * + * NAT State Machine Status Register + */ +#define NATC_DDR_CFG_SM_STATUS 0x420 + +/* + * Debug bus select. + * 2'b00: + * prb_nat_control. + * 2'b01: + * prb_cmd_control. + * 2'b10: + * prb_wb_control. + * 2'b11: + * prb_ddr_control. +*/ +#define SM_STATUS_DEBUG_SEL_SHIFT 24 +#define SM_STATUS_DEBUG_SEL_MASK 0x3000000 + +/* + * APB to RBUS bridge state machine. + * 2'b00: + * APB_ST_IDLE. + * 2'b01: + * APB_ST_RW. + * 2'b10: + * AOB_ST_END. +*/ +#define SM_STATUS_APB_STATE_SHIFT 22 +#define SM_STATUS_APB_STATE_MASK 0xc00000 + +/* + * DDR request state machine. + * 2'b00: + * DDR_REQ_ST_IDLE. + * 2'b01: + * DDR_REQ_ST_WRITE_HEADER. + * 2'b10: + * DDR_REQ_ST_WRITE_HEADER_DELAY. +*/ +#define SM_STATUS_DDR_REQ_STATE_SHIFT 20 +#define SM_STATUS_DDR_REQ_STATE_MASK 0x300000 + +/* + * DDR reply state machine. + * 3'b000: + * DDR_REP_ST_IDLE. + * 3'b001: + * DDR_REP_ST_READ_DATA. + * 3'b010: + * DDR_REP_ST_READ_RESULT. + * 3'b011: + * DDR_REP_ST_READ_WAIT. + * 3'b100: + * DDR_REP_ST_EVICT_WR_NON_CACHEABLE. +*/ +#define SM_STATUS_DDR_REP_STATE_SHIFT 17 +#define SM_STATUS_DDR_REP_STATE_MASK 0xe0000 + +/* + * Runner command state machine. + * 1'b0: + * RUNNER_CMD_ST_IDLE. + * 1'b1: + * RUNNER_CMD_ST_WRITE_RUNNER_FIFO. +*/ +#define SM_STATUS_RUNNER_CMD_STATE_MASK 0x10000 + +/* + * Write-back state machine. + * 1'b0: + * WB_ST_IDLE. + * 1'b1: + * WB_ST_WRITE_BACIF. +*/ +#define SM_STATUS_WB_STATE_MASK 0x8000 + +/* + * Nat state machine. + * 15'b000000000000000: + * NAT_ST_IDLE. + * 15'b000000000000001: + * NAT_ST_IDLE_WRITE_SMEM. + * 15'b000000000000010: + * NAT_ST_IDLE_DDR_PENDING. + * 15'b000000000000100: + * NAT_ST_HASH. + * 15'b000000000001000: + * NAT_ST_NAT_MEM_READ_REQ. + * 15'b000000000010000: + * NAT_ST_NAT_MEM_WRITE_REQ. + * 15'b000000000100000: + * NAT_ST_READ_SMEM. + * 15'b000000001000000: + * NAT_ST_UPDATE_DDR. + * 15'b000000010000000: + * NAT_ST_IDLE_BLOCKING_PENDING. + * 15'b000000100000000: + * NAT_ST_EVICT_WAIT. + * 15'b000001000000000: + * NAT_ST_CHECK_NON_CACHEABLE. + * 15'b000010000000000: + * NAT_ST_WAIT. + * 15'b000100000000000: + * NAT_ST_WAIT_NATC_MEM_REQ_DONE. + * 15'b001000000000000: + * NAT_ST_CACHE_FLUSH. + * 15'b010000000000000: + * NAT_ST_DDR_MISS_0. + * 15'b100000000000000: + * NAT_ST_DDR_MISS_1. +*/ +#define SM_STATUS_NAT_STATE_SHIFT 0 +#define SM_STATUS_NAT_STATE_MASK 0x7fff + + + +/* + * + * register sets NATC_ENG, is [ 0 => 4 ] + * + */ + +/* + * Register + * + * NAT Command and Status Register + */ +#define NATC_ENG_COMMAND_STATUS(r) (0x10 + (r) * 0xb0) + +/* + * This filed specifies the DDR BIN number to be compared for DEL + * commandwhen DEL_CMD_MODE is set to 1 +*/ +#define COMMAND_STATUS_DEL_CMD_DDR_BIN_SHIFT 20 +#define COMMAND_STATUS_DEL_CMD_DDR_BIN_MASK 0xff00000 + +/* + * DEL Command DDR-bin matching mode enable0h: + * DEL command deletes the cache entry with matching key1h: + * DEL command deletes the cache entry with matching key and matching DDR + * binnumber specified in DEL_CMD_DDR_BIN field +*/ +#define COMMAND_STATUS_DEL_CMD_MODE_MASK 0x20000 + +/* + * Cache Flush enableWhen set, LOOKUP command is used to flush counters + * from cache into DDR. + * This command does not use key to lookup the cache entry. + * Instead it usescache index number located in 10-MSB bits of key + * specified in NAT_KEY_RESULT register. + * For 16 bytes key, the cache index will be located in{NAT_KEY_RESULT[15], + * NAT_KEY_RESULT[14][7: + * 6]} (15th byte of NAT_KEY_RESULT register andbits 7: + * 6 of 14th byte of NAT_KEY_RESULT register). + * For 32 bytes key, the cache index will be located in{NAT_KEY_RESULT[31], + * NAT_KEY_RESULT[30][7: + * 6]} (31th byte of NAT_KEY_RESULT register andbits 7: + * 6 of 30th byte of NAT_KEY_RESULT register). + * 0h: + * LOOKUP command is used as normal lookup command. + * 1h: + * LOOKUP command is used as cache flush command. +*/ +#define COMMAND_STATUS_CACHE_FLUSH_MASK 0x10000 + +/* + * Decrement-counter mode enableWhen set, LOOKUP command will decrement hit + * counter by 1 and decrementbyte counter by the value specified in + * PKT_LEN, on a successful lookup. + * NATC_SMEM_INCREMENT_ON_REG_LOOKUP must be set to 1 for it to be + * effective0h: + * LOOKUP command will increment hit counter and byte counter1h: + * LOOKUP command will decrement hit counter and byte counter +*/ +#define COMMAND_STATUS_DECR_COUNT_MASK 0x8000 + +/* + * Select the DDR Table on which the command will operate0h: + * DDR table 01h: + * DDR table 12h: + * DDR table 23h: + * DDR table 34h: + * DDR table 45h: + * DDR table 56h: + * DDR table 67h: + * DDR table 7 +*/ +#define COMMAND_STATUS_NAT_TBL_SHIFT 12 +#define COMMAND_STATUS_NAT_TBL_MASK 0x7000 + +/* + * Cache multi-hash iteration count statusValue of 0 is iteration 1, 1 is + * iteration 2, 2 is iteration 3, etc. + * cache miss returns 0 count. +*/ +#define COMMAND_STATUS_MULTIHASH_COUNT_SHIFT 8 +#define COMMAND_STATUS_MULTIHASH_COUNT_MASK 0xf00 + +/* This bit is set when a LOOKUP command has a cache hit */ +#define COMMAND_STATUS_CACHE_HIT_MASK 0x80 + +/* This bit is set when a LOOKUP command has a miss */ +#define COMMAND_STATUS_MISS_MASK 0x40 + +/* + * This bit is set for the following 2 casesFor ADD command all multi-hash + * entries are occupied (i. + * e, no room to ADD)For DEL command entry is not found and cannot be + * deleted +*/ +#define COMMAND_STATUS_ERROR_MASK 0x20 + +/* + * Interface BusyThis bit is set when command is issued but still in + * progress been processed. + * When command completes this bit will be cleared. +*/ +#define COMMAND_STATUS_BUSY_MASK 0x10 + +#define COMMAND_STATUS_UNUSED0_MASK 0x8 +/* + * Command to be executedThis command only operates on the entries in cache + * except LOOKUP command whereentry can be fetched from DDR. + * Writing to this field causes BUSY bit to be set. + * Note: + * For all commands, key consists of all 0's indicates unused entry in + * h/wand therefore cannot be used. + * No-OperationLookupAdd (to cache only)Del (from cache only)Hash (debug + * command)Hashes are stored in different set of COMMAND_STATUS register + * (i. + * e. + * Hashes for HASH command issued using NAT0 register are returnedat NAT1 + * KEY_RESULT registers; hashes for NAT1 HASH commandare returned at NAT0 + * KEY_RESULT; hashes for NAT2 HASH command arereturned at NAT3 KEY_RESULT; + * hashes for NAT3 HASH command arereturned at NAT2 KEY_RESULT register). + * Internal Cache command (debug command)Do not use this command +*/ +#define COMMAND_STATUS_COMMAND_SHIFT 0 +#define COMMAND_STATUS_COMMAND_MASK 0x7 + + +/* + * Register - read-only + * + * NAT Hash Value + */ +#define NATC_ENG_HASH(r) (0x18 + (r) * 0xb0) + +/* + * hash value; only valid on a successful lookup/add/del commandFor cache + * hit 10-bit hash value is returned. + * For cache miss and DDR_ENABLE is 0, first hash value (10-bit) is + * returned. + * For cache miss, DDR_ENABLE is 1 and DDR is a hit, 18-bit DDR hash value + * + DDR bin count is returned. + * For cache miss, DDR_ENABLE is 1 and DDR is a miss, 18-bit DDR hash value + * is returned. +*/ +#define HASH_HASH_SHIFT 0 +#define HASH_HASH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Hit Count + */ +#define NATC_ENG_HIT_COUNT(r) (0x1c + (r) * 0xb0) + +/* + * bits 27: + * 0 are 28-bit hit count value. + * bits 31: + * 28 are 4 lsb of 36-bit byte count value. + * only valid on a successful lookup or delete command. +*/ +#define HIT_COUNT_HIT_COUNT_SHIFT 0 +#define HIT_COUNT_HIT_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Byte Count + */ +#define NATC_ENG_BYTE_COUNT(r) (0x20 + (r) * 0xb0) + +/* + * 32-bit msb of 36-bit byte count value. + * {BYTE_COUNT, HIT_COUNT[31: + * 28]} is the 36-bit byte count value. + * only valid on a successful lookup or delete command +*/ +#define BYTE_COUNT_BYTE_COUNT_SHIFT 0 +#define BYTE_COUNT_BYTE_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NAT PKT Length + */ +#define NATC_ENG_PKT_LEN(r) (0x24 + (r) * 0xb0) + +#define PKT_LEN_UNUSED_SHIFT 16 +#define PKT_LEN_UNUSED_MASK 0xffff0000 +/* 16-bit packet length value used to increment or decrement byte counter */ +#define PKT_LEN_PKT_LEN_SHIFT 0 +#define PKT_LEN_PKT_LEN_MASK 0xffff + + +/* + * Registers - is [ 0 => 33 ] + * + * NAT key & context (excluding 8-byte counters) register; context is + * placed after the key;Key consists of all 0's indicates unused entry in + * hardware and therefore should not beused for lookup/hash/del/add + * commands; Key should contain an encoded type field(e. + * g. + * Unused=0, IPv4=1, IPv4m=2, IPv6=3, IPv6m=4, etc) to uniquely + * identifyeach key so the keys with shorter length of one type is not + * misidentifiedas the longer key of another type when the shorter key + * matches the beginningof the longer key. + * When multiple DDR table mode is used, DDR table number should builtinto + * the key so the same real key in 2 different DDR tables can be + * distinguished. + * For HASH debug command, this register stores the nth multi-hash + * value;For 256_BIT_MODE 10-bit hash value is store at bit 14: + * 5. + * For 512_BIT_MODE,9-bit hash value is stored at bit 14: + * 6; For HASH debug command,hashes for HASH command issued using NAT0 + * register are returnedat NAT1 KEY_RESULT registers; hashes for NAT1 HASH + * commandare returned at NAT0 KEY_RESULT; hashes for NAT2 HASH command + * arereturned at NAT3 KEY_RESULT; hashes for NAT3 HASH command arereturned + * at NAT2 KEY_RESULT register. + */ +#define NATC_ENG_KEY_RESULT(r, x) (0x30 + (r) * 0xb0 + (x) * 0x4) + +#define KEY_RESULT_NAT_KEY_RESULT_SHIFT 0 +#define KEY_RESULT_NAT_KEY_RESULT_MASK 0xffffffff + + +/* + * + * register set NATC_INDIR + * + */ + +/* + * Register + * + */ +#define NATC_INDIR_C_INDIR_ADDR_REG 0x700 + +/* + * NAT Cache Memory and Statics Memory Transaction. + * 1 : + * NAT Cache Memory and Statics Memory Write. + * 0 : + * NAT Cache Memory and Statics Memory Read. +*/ +#define C_INDIR_ADDR_REG_W_R_MASK 0x400 + +/* NAT Cache Entry number. */ +#define C_INDIR_ADDR_REG_NATC_ENTRY_SHIFT 0 +#define C_INDIR_ADDR_REG_NATC_ENTRY_MASK 0x3ff + + +/* + * Registers - is [ 0 => 36 ] + * + */ +#define NATC_INDIR_C_INDIR_DATA_REG(x) (0x710 + (x) * 0x4) + +/* + * Indirect register access data register, bits[31: + * 0]. + * -------------------------------------------------------For NAT Cache nd + * Statics Memory write operation,first, write all the data to Indirect + * Data Registers[N-1: + * 0],N is number of words including key, result, hit count and byte count. + * Indirect Data Register[1: + * 0] are for Statics Memory. + * Indirect Data register[0] is for hit count and 4 lsb of byte count. + * Indirect Data register[0] bits 27: + * 0 are 28-bit hit count. + * Indirect Data register[0] bits 31: + * 28 are 4 lsb of 36-bit byte count. + * Indirect Data Register[1] is for 32 msb of 36-bit byte count. + * {Indirect Data Register[1], Indirect Data register[0][31: + * 28]} is the 36-bit byte count. + * indirect Data register [N-1: + * 2] are for NAT Cache Memory (key and result), key is first,followed by + * result, followed by {ddr_miss, nat_ddr_bin, nat_tbl}then followed by a + * write to Indirect Address Register to set upNAT Cache Entry Number and + * W_R bit to 1, this will initiate the write operation. + * --------------------------------------------------------For NAT Cache + * Memory and statics Memory read operation,first, write to Indirect + * Address Register to set upNAT Cache Entry Number and W_R bit to 0, this + * will initiate the read operation. + * the read data from NAT Cache Memory and statics Memory will be loaded + * into Indirect Data Registers[N-1: + * 0]. + * then followed by read from Indirect Data Registers[N-1: + * 0] for all data. +*/ +#define C_INDIR_DATA_REG_DATA_SHIFT 0 +#define C_INDIR_DATA_REG_DATA_MASK 0xffffffff + + + +/* + * + * register sets NATC_KEY_MASK, is [ 0 => 8 ] + * + */ + +/* + * Register + * + * NAT Cache key Mask Register + */ +#define NATC_KEY_MASK(r) (0x3f0 + (r) * 0x4) + +/* + * Specifies the key mask for each byte in the key. + * each bit corresponds to one byte. + * 0 enables the compare and 1 disables the compare. + * bit 0 corresponds to byte 0bit 1 corresponds to byte 1bit 2 corresponds + * to byte 2. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .bit 31 corresponds to byte 31 +*/ +#define NATC_KEY_MASK_KEY_MASK_SHIFT 0 +#define NATC_KEY_MASK_KEY_MASK_MASK 0xffffffff + + + +/* + * + * register set NATC_REGFILE + * + */ + +/* + * Register + * + * REGFILE FIFO Start Address register 0Actual FIFO size is 2 more than the + * number programmed inthis register due to input and output holder + * registerswhich account for 2 additional depth. + * The actual FIFO 0 (DDR_KEY_REQ_FIFO) size isREGFILE_FIFO_START_ADDR_1 - + * REGFILE_FIFO_START_ADDR_0 + 2. + * The actual FIFO 1 (DDR_RESULT_REQ_FIFO) size isREGFILE_FIFO_START_ADDR_2 + * - REGFILE_FIFO_START_ADDR_1 + 2. + * The actual FIFO 2 (DDR_KEY_REQ_PIPE) size isREGFILE_FIFO_START_ADDR_3 - + * REGFILE_FIFO_START_ADDR_2 + 2. + * The actual FIFO 3 (BLOCKING_PENDING_FIFO) size + * isREGFILE_FIFO_START_ADDR_4 - REGFILE_FIFO_START_ADDR_3 + 2. + */ +#define NATC_REGFILE_FIFO_START_ADDR_0 0x424 + +/* REGFILE FIFO 2 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_SHIFT 24 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_MASK 0xff000000 + +/* REGFILE FIFO 2 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_SHIFT 16 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_MASK 0xff0000 + +/* REGFILE FIFO 1 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_SHIFT 8 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_MASK 0xff00 + +/* REGFILE FIFO 0 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_SHIFT 0 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_MASK 0xff + + +/* + * Register + * + * REGFILE FIFO Start Address register 1Actual FIFO size is 2 more than the + * number programmed inthis register due to input and output holder + * registerswhich account for 2 additional depth. + * The delta between REGFILE_FIFO_START_ADDR_4 and + * REGFILE_FIFO_START_ADDR_5,REGFILE_FIFO_START_ADDR_5 and + * REGFILE_FIFO_START_ADDR_6,REGFILE_FIFO_START_ADDR_6 and + * REGFILE_FIFO_START_ADDR_7need to be identical since these are used for + * the same wide FIFO. + * The actual FIFO 4 (DDR_WRITE_RESULT_FIFO) size + * isREGFILE_FIFO_START_ADDR_5 - REGFILE_FIFO_START_ADDR_4 + 2. + * The actual FIFO 5 (DDR_WRITE_RESULT_FIFO) size + * isREGFILE_FIFO_START_ADDR_6 - REGFILE_FIFO_START_ADDR_5 + 2. + * The actual FIFO 6 (DDR_WRITE_RESULT_FIFO) size + * isREGFILE_FIFO_START_ADDR_7 - REGFILE_FIFO_START_ADDR_6 + 2. + * The actual FIFO 7 size is the same as FIFO 4, 5, 6 + */ +#define NATC_REGFILE_FIFO_START_ADDR_1 0x428 + +/* + * REGFILE FIFO 7 Start Address -- Note that this entry is not used in + * 68460 +*/ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_SHIFT 24 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_MASK 0xff000000 + +/* REGFILE FIFO 6 Start Address */ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_SHIFT 16 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_MASK 0xff0000 + +/* REGFILE FIFO 5 Start Address */ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_SHIFT 8 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_MASK 0xff00 + +/* REGFILE FIFO 4 Start Address */ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_SHIFT 0 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_MASK 0xff + + +#endif /* ! XRDP_REGS_NATC_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_psram.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_psram.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_psram.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_psram.h 2023-03-09 15:06:11.380234652 +0100 @@ -0,0 +1,729 @@ +#ifndef XRDP_REGS_PSRAM_H_ +#define XRDP_REGS_PSRAM_H_ + +/* relative to core */ +#define PSRAM_OFFSET_0 0x600000 + +/* + * Registers - is [ 0 => 65535 ] + * + * psram_mem_entry + */ +#define PSRAM_MEMORY_DATA(x) (0x0 + (x) * 0x4) + +/* data */ +#define PSRAM_MEMORY_DATA_DATA_SHIFT 0 +#define PSRAM_MEMORY_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * control reg + */ +#define PSRAM_CFGS_CTRL 0x799400 + +/* + * 1: + * enable memory banks permutations0: + * disable +*/ +#define PSRAM_CFGS_CTRL_PERM_EN_MASK 0x1 + +/* + * 1: + * enable memory banks combinations0: + * disable +*/ +#define PSRAM_CFGS_CTRL_COMB_EN_MASK 0x2 + +/* + * 1: + * enable full combinations(also on same 4-banks)0: + * disable full combinations(allow only on opposite 4-banks) +*/ +#define PSRAM_CFGS_CTRL_COMB_FULL_MASK 0x4 + +/* + * 1: + * all 8 banks are active0: + * only 4 banks are active +*/ +#define PSRAM_CFGS_CTRL_BANKS8_MASK 0x8 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB0_REQIN_ESWAP_MASK 0x10 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB0_REPOUT_ESWAP_MASK 0x20 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB1_REQIN_ESWAP_MASK 0x40 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB1_REPOUT_ESWAP_MASK 0x80 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB2_REQIN_ESWAP_MASK 0x100 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB2_REPOUT_ESWAP_MASK 0x200 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB3_REQIN_ESWAP_MASK 0x400 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB3_REPOUT_ESWAP_MASK 0x800 + +/* + * 1: + * stall ec client if wants to read same page as one of the pages in the + * ubus write buffers0: + * dont stall +*/ +#define PSRAM_CFGS_CTRL_COH_EN_EC0_MASK 0x1000 + +/* + * 1: + * stall ec client if wants to read same page as one of the pages in the + * ubus write buffers0: + * dont stall +*/ +#define PSRAM_CFGS_CTRL_COH_EN_EC1_MASK 0x2000 + +/* + * 1: + * stall ec client if wants to read same page as one of the pages in the + * ubus write buffers0: + * dont stall +*/ +#define PSRAM_CFGS_CTRL_COH_EN_EC2_MASK 0x4000 + +/* arbitration weight for client 0 - currently not used. */ +#define PSRAM_CFGS_CTRL_WT_0_SHIFT 15 +#define PSRAM_CFGS_CTRL_WT_0_MASK 0x38000 + +/* arbitration weight for client 1 - currently not used. */ +#define PSRAM_CFGS_CTRL_WT_1_SHIFT 18 +#define PSRAM_CFGS_CTRL_WT_1_MASK 0x1c0000 + +/* arbitration weight for client 2 - currently not used. */ +#define PSRAM_CFGS_CTRL_WT_2_SHIFT 21 +#define PSRAM_CFGS_CTRL_WT_2_MASK 0xe00000 + +/* + * 1: + * rr between all clients0: + * ubus is high priority (def) +*/ +#define PSRAM_CFGS_CTRL_ARB_RR_MASK 0x1000000 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define PSRAM_CFGS_CLK_GATE_CNTRL 0x79940c + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define PSRAM_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * this register contains a bit for enable/disable of the counters. + * The counters will be reset to zero on the positive edge of the enable + * bit, and will count until the time window which is decrement counter, + * will reach zero, or until the enable bit will be de-asserted. + */ +#define PSRAM_PM_COUNTERS_MUEN 0x799500 + +/* enable monitor for client 0 */ +#define PSRAM_PM_COUNTERS_MUEN_CL0MEN_MASK 0x1 + +/* enable monitor for client 1 */ +#define PSRAM_PM_COUNTERS_MUEN_CL1MEN_MASK 0x2 + +/* enable monitor for client 2 */ +#define PSRAM_PM_COUNTERS_MUEN_CL2MEN_MASK 0x4 + +/* enable monitor for client 3 */ +#define PSRAM_PM_COUNTERS_MUEN_CL3MEN_MASK 0x8 + +/* enable monitor for client 4 */ +#define PSRAM_PM_COUNTERS_MUEN_CL4MEN_MASK 0x10 + +/* enable monitor for client 5 */ +#define PSRAM_PM_COUNTERS_MUEN_CL5MEN_MASK 0x20 + +/* enable monitor for client 6 */ +#define PSRAM_PM_COUNTERS_MUEN_CL6MEN_MASK 0x40 + + +/* + * Register + * + * determines the time window in which we perform the bandwidth + * monitoring(on cyclic mode - when cyclic_bw_check_en=1) + */ +#define PSRAM_PM_COUNTERS_BWCL 0x799504 + +/* measure time window in clock cycles */ +#define PSRAM_PM_COUNTERS_BWCL_TW_SHIFT 0 +#define PSRAM_PM_COUNTERS_BWCL_TW_MASK 0xffffffff + + +/* + * Register + * + * pm_bw_check_en - start of new monitoring session. + * resets counters on rise. + * cyclic_bw_check_en - if this enabled - when the bw period reaches its + * limit - the counters are reet. + */ +#define PSRAM_PM_COUNTERS_BWEN 0x799508 + +/* + * start of new monitoring session. + * zeroes counters on rise. +*/ +#define PSRAM_PM_COUNTERS_BWEN_BWCEN_MASK 0x1 + +/* + * if this enabled - when the bw period reaches its limit - the counters + * are reset. +*/ +#define PSRAM_PM_COUNTERS_BWEN_CBWCEN_MASK 0x100 + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the maximum time in clock cycles the client + * has waited from the moment it had a request pending to the time the + * request gained arbitration. + */ +#define PSRAM_PM_COUNTERS_MAX_TIME(x) (0x799510 + (x) * 0x4) + +/* max wait time */ +#define PSRAM_PM_COUNTERS_MAX_TIME_MAX_SHIFT 0 +#define PSRAM_PM_COUNTERS_MAX_TIME_MAX_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the accumulated time in clock cycles the + * client has waited from the moment it had a request pending to the time + * the request gained arbitration. + * For each access to arbiter, it will be at least 1 cycle. + */ +#define PSRAM_PM_COUNTERS_ACC_TIME(x) (0x799530 + (x) * 0x4) + +/* max wait time */ +#define PSRAM_PM_COUNTERS_ACC_TIME_MAX_SHIFT 0 +#define PSRAM_PM_COUNTERS_ACC_TIME_MAX_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the accumulated number of requests that was + * served per user. + */ +#define PSRAM_PM_COUNTERS_ACC_REQ(x) (0x799550 + (x) * 0x4) + +/* accumulated number of served requests */ +#define PSRAM_PM_COUNTERS_ACC_REQ_REQ_SHIFT 0 +#define PSRAM_PM_COUNTERS_ACC_REQ_REQ_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the Result of th elast measure of + * accumulated time in clock cycles the client has waited from the moment + * it had a request pending to the time the request gained arbitration. + */ +#define PSRAM_PM_COUNTERS_LAST_ACC_TIME(x) (0x799570 + (x) * 0x4) + +/* accumulated wait time */ +#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_SHIFT 0 +#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the last result of accumulated number of + * requests that was served per user on cyclic measure. + */ +#define PSRAM_PM_COUNTERS_LAST_ACC_REQ(x) (0x799590 + (x) * 0x4) + +/* accumulated number of served requests */ +#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_SHIFT 0 +#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter holds the sum of the WR_CNT array. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC 0x7995b0 + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter holds the sum of the RD_CNT array. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC 0x7995b4 + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words written to the + * psram per client. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT(x) (0x7995b8 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words read from the + * psram per client. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT(x) (0x7995d8 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter is a sum of the WR_CNT_LAST counters, which holds the + * number of double words written to the psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC 0x7995f8 + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter is a sum of the RD_CNT_LAST counters, which holds the + * number of double words written to the psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC 0x7995fc + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words written to the + * psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST(x) (0x799600 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words read from the + * psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST(x) (0x799620 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were requests (even one) + */ +#define PSRAM_PM_COUNTERS_ARB_REQ 0x799640 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_REQ_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_REQ_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were more that 1 request for arbitration + */ +#define PSRAM_PM_COUNTERS_ARB_ARB 0x799644 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_ARB_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_ARB_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were commands combinations + */ +#define PSRAM_PM_COUNTERS_ARB_COMB 0x799648 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_COMB_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_COMB_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were commands combinations in the same 4 banks + */ +#define PSRAM_PM_COUNTERS_ARB_COMB_4 0x79964c + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of totsl banks that were accessed during commands combinations + * cycles + */ +#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS 0x799650 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_MASK 0xffffffff + + +/* + * Register + * + * selects the debug vecore + */ +#define PSRAM_DEBUG_DBGSEL 0x799700 + +/* selects the debug vector */ +#define PSRAM_DEBUG_DBGSEL_VS_SHIFT 0 +#define PSRAM_DEBUG_DBGSEL_VS_MASK 0xff + + +/* + * Register - read-only + * + * the debug bus + */ +#define PSRAM_DEBUG_DBGBUS 0x799704 + +/* debug vector */ +#define PSRAM_DEBUG_DBGBUS_VB_SHIFT 0 +#define PSRAM_DEBUG_DBGBUS_VB_MASK 0xffffffff + + +/* + * Register - read-only + * + * vector of all the requests of the clients + */ +#define PSRAM_DEBUG_REQ_VEC 0x799708 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_MASK 0x1 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_MASK 0x2 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_MASK 0x4 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_MASK 0x8 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_MASK 0x10 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_MASK 0x20 + + +/* + * Register + * + * debug capture config + */ +#define PSRAM_DEBUG_DBG_CAP_CFG1 0x799780 + +/* selects bank to capture */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_MASK 0x7 + +/* selects bank address to capture */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_SHIFT 4 +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_MASK 0xfff0 + +/* capture write enable */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_MASK 0x10000 + +/* capture read enable */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_MASK 0x20000 + + +/* + * Register + * + * debug capture config + */ +#define PSRAM_DEBUG_DBG_CAP_CFG2 0x799784 + +/* + * maximum of captures for write. + * 0 means infinite. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_MASK 0xff + +/* + * maximum of captures for read. + * 0 means infinite. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_SHIFT 8 +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_MASK 0xff00 + +/* + * reset the counting and start new one. + * should be asserted, then deasserted, then counting starts again. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_MASK 0x10000 + +/* + * reset the counting and start new one. + * should be asserted, then deasserted, then counting starts again. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_MASK 0x20000 + + +/* + * Register - read-only + * + * debug capture status + */ +#define PSRAM_DEBUG_DBG_CAP_ST 0x799788 + +/* + * actual current capture num for write. + * max is FFFF (no wrap). +*/ +#define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_MASK 0xff + +/* + * actual current capture num for read. + * max is FFFF (no wrap). +*/ +#define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_SHIFT 8 +#define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_MASK 0xff00 + + +/* + * Register - read-only + * + * debug capture write data0 register [32*1-1: + * 32*0] + */ +#define PSRAM_DEBUG_DBG_CAP_W0 0x799790 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W0_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W0_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write data1 register [32*2-1: + * 32*1] + */ +#define PSRAM_DEBUG_DBG_CAP_W1 0x799794 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W1_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W1_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write data2 register [32*3-1: + * 32*2] + */ +#define PSRAM_DEBUG_DBG_CAP_W2 0x799798 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W2_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W2_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write data3 register [32*4-1: + * 32*3] + */ +#define PSRAM_DEBUG_DBG_CAP_W3 0x79979c + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W3_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W3_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write mask register (16b for 16B=128b of data in bank row) + */ +#define PSRAM_DEBUG_DBG_CAP_WMSK 0x7997a0 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_WMSK_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_WMSK_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data0 register [32*1-1: + * 32*0] + */ +#define PSRAM_DEBUG_DBG_CAP_R0 0x7997b0 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R0_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R0_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data1 register [32*2-1: + * 32*1] + */ +#define PSRAM_DEBUG_DBG_CAP_R1 0x7997b4 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R1_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R1_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data2 register [32*3-1: + * 32*2] + */ +#define PSRAM_DEBUG_DBG_CAP_R2 0x7997b8 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R2_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R2_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data3 register [32*4-1: + * 32*3] + */ +#define PSRAM_DEBUG_DBG_CAP_R3 0x7997bc + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R3_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R3_CV_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_PSRAM_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_qm.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_qm.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_qm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_qm.h 2023-03-09 15:06:11.384234759 +0100 @@ -0,0 +1,4528 @@ +#ifndef XRDP_REGS_QM_H_ +#define XRDP_REGS_QM_H_ + +/* relative to core */ +#define QM_OFFSET_0 0x100000 + +/* + * Register + * + * QM Enable register + */ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL 0x0 + +/* + * FPM Prefetch Enable. + * Setting this bit to 1 will start filling up the FPM pool prefetch FIFOs. + * Seeting this bit to 0, will stop FPM prefetches. +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_MASK 0x1 + +/* + * When this bit is set the QM will send credits to the REORDER block. + * Disabling this bit will stop sending credits to the reorder. +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_MASK 0x2 + +/* + * When this bit is set the QM will pop PDs from the DQM and place them in + * the runner SRAM +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_MASK 0x4 + +/* + * When this bit is set Fixed arbitration will be done in pops from the + * remote FIFOs (Non delayed highest priority). + * If this bit is cleared RR arbitration is done +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_MASK 0x100 + +/* + * When this bit is set Fixed arbitration will be done in DQM pushes (CPU + * highest priority, then non-delayed queues and then normal queues. + * If this bit is cleared RR arbitration is done. +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_MASK 0x200 + + +/* + * Register + * + * QM soft reset register + */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL 0x4 + +/* FPM Prefetch FIFO0 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_MASK 0x1 + +/* FPM Prefetch FIFO1 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_MASK 0x2 + +/* FPM Prefetch FIFO2 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_MASK 0x4 + +/* FPM Prefetch FIFO3 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_MASK 0x8 + +/* Normal Remote FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_MASK 0x10 + +/* Non-delayed Remote FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_MASK 0x20 + +/* Pre Copy Machine FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_MASK 0x40 + +/* Copy Machine RD PD FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_MASK 0x80 + +/* Pre Copy Machine FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_MASK 0x100 + +/* BB0 OUTPUT FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_MASK 0x200 + +/* BB1 Output FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_MASK 0x400 + +/* BB1 Input FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_MASK 0x800 + +/* TM FIFOs Pointers SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_MASK 0x1000 + +/* Non delayed output FIFO Pointers SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_MASK 0x2000 + + +/* + * Register + * + * QM Enable register + */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL 0x8 + +/* Indicates whether the Drop/max_occupancy packets counter is read clear. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABLE_MASK 0x1 + +/* Indicates whether the Drop/max_occupancy bytes counter is read clear. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENABLE_MASK 0x2 + +/* + * This bit defines the functionality of the drop packets counter. + * 0 - Functions as the drop packets counter1 - Functions as the max + * packets occupancy holder +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SELECT_MASK 0x4 + +/* + * This bit defines the functionality of the drop bytes counter. + * 0 - Functions as the drop bytes counter1 - Functions as the max bytes + * occupancy holder +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_SELECT_MASK 0x8 + +/* + * Indicates The value to put in the last_search field of the SBPM free + * with context message +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_MASK 0x10 + +/* Disables WRED influence on drop condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_MASK 0x20 + +/* Disables DDR_PD_CONGESTION influence on drop/bpcondition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_MASK 0x40 + +/* Disables DDR_BYTE_CONGESTION influence on drop/bp condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_MASK 0x80 + +/* Disables DDR_OCCUPANCY influence on drop/bp condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_MASK 0x100 + +/* Disables DDR_FPM_CONGESTION influence on drop/bp condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_MASK 0x200 + +/* Disables FPM_UG influence on drop condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_MASK 0x400 + +/* Disables QUEUE_OCCUPANCY_DDR_COPY_DECISION influence on copy condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECISION_DISABLE_MASK 0x800 + +/* Disables PSRAM_OCCUPANCY_DDR_COPY_DECISION influence on copy condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECISION_DISABLE_MASK 0x1000 + +/* When set, the multicast bit of the PD will not be sent to BBH TX */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_MASK 0x2000 + +/* + * When set, aggregations are not closed automatically when queue open + * aggregation time expired. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_DISABLE_MASK 0x4000 + +/* + * When cleared, given that there is an FPM congestion situation and all + * prefetch FPM buffers are full then a min pool size buffer will be freed + * each 1us. + * This is done due to the fact that exclusive indication is received only + * togeter with buffer allocation reply and if this will not be done then a + * deadlock could occur. + * Setting this bit will disable this mechanism. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MECHANISM_DISABLE_MASK 0x8000 + +/* + * FPM over subscription mechanism. + * Each queue will have one out of 8 reserved byte threshold profiles. + * Each profile defines 8 bit threshold with 512byte resolution. + * Once the global FPM counter pass configurable threshold the system goes + * to buffer reservation congestion state. + * In this state any PD entering a queue which passes the reserved byte + * threshold will be dropped. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_MASK 0x10000 + +/* Dont drop pd with fpm allocation. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_MASK 0x20000 + +/* 0 for 64B/Queue1 for 128B/Queue */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_MASK 0x40000 + +/* + * Controls the timing of updating the overhead counters with packets which + * goes through aggregation. + * 0 - updates when the packets enters QM1 - updates when aggregation is + * done. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_AGG_EN_MASK 0x80000 + +/* Disables FPM_UG influence on flow control wake up messages to FW. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_MASK 0x100000 + +/* + * Enables to write packet transaction to multiple slave (unlimited), if + * disable only one ubus slave allowed. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_MASK 0x200000 + +/* global priority bit to aggregated PDs which go through reprocessing. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_MASK 0x400000 + +/* Disables PSRAM_OCCUPANCY_DROP influence on drop condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DROP_DISABLE_MASK 0x800000 + +/* 0 According to length1 8-byte aligned */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_DDR_WRITE_ALIGNMENT_MASK 0x1000000 + +/* + * Controls if the exclusive indication in PD marks the PD as dont drop or + * as dont drop if the fpm in exclusive state1 - global dont drop0 - FPM + * exclusive state dont drop +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_MASK 0x2000000 + +/* + * when set 1 backpressure will be applied when the DONT_DROP pd should be + * dropped. + * for example, 0 fpm buffers available and the PD should be copied to DDR. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_BP_EN_MASK 0x4000000 + +/* + * If the bit enable, QM round up to 4 every packet length added ghost + * counters. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GPON_DBR_CEIL_MASK 0x8000000 + +/* + * Drop counter counts WRED drops by color per queue. + * In order to enable this feature the drop counter should be configured to + * count drops. + * if the drop counter is configured count max occupancy per queue, it will + * override WRED drops count. + * color 0 - is written in dropped bytes field (word0)color 1 - is written + * in dropped pkts field (word1) +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_WRED_DROPS_MASK 0x10000000 + + +/* + * Register + * + * FPM Control Register + */ +#define QM_GLOBAL_CFG_FPM_CONTROL 0xc + +/* + * This field indicates whether crossing the per pool FPM buffer prefetch + * FIFO occupancy thresholds will result in dropping packets or in applying + * back pressure to the re-order. + * 0 - drop packets1 - apply back pressure +*/ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_MASK 0x1 + +/* + * This field indicates whether crossing the FPM congestion threshold will + * result in dropping packets or in applying back pressure to the re-order. + * 0 - drop packets1 - apply back pressure +*/ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_MASK 0x2 + +/* + * FPM prefetch minimum pool size. + * The supported FPM pool sizes are derived from this value: + * * FPM_PREFETCH_MIN_POOL_SIZEx1* FPM_PREFETCH_MIN_POOL_SIZEx2* + * FPM_PREFETCH_MIN_POOL_SIZEx4* FPM_PREFETCH_MIN_POOL_SIZEx8The optional + * values for this field: + * 0 - 256Byte1 - 512Byte2 - 1024Byte3 - 2048Byte +*/ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_SHIFT 8 +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_MASK 0x300 + +/* The allowed on the fly FPM prefetch pending Alloc requests to the FPM. */ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_SHIFT 16 +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_MASK 0x7f0000 + + +/* + * Register + * + * DDR Byte Congestion Control Register + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL 0x10 + +/* + * This field indicates whether crossing the DDR bytes thresholds (the + * number of bytes waiting to be copied to DDR) will result in dropping + * packets or in applying back pressure to the re-order. + * 0 - apply back pressure1 - drop packets +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABLE_MASK 0x1 + + +/* + * Register + * + * DDR Byte Congestion Lower Threshold + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LO_THR 0x14 + +/* + * DDR copy bytes Lower Threshold. + * When working in packet drop mode (DDR_BYTES_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then all packets + * are dropped. + * * If (DDR_BYTES_MID_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (DDR_BYTES_LOWER_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_MID_THR), then packets in low priority are dropped. + * * If (DDR copy bytes counter) <= (DDR_BYTES_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_BYTES_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_BYTES_LOWER_THR + * and DDR_BYTES_MID_THR are dont care). +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LO_THR_DDR_BYTES_LOWER_THR_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LO_THR_DDR_BYTES_LOWER_THR_MASK 0x3fffffff + + +/* + * Register + * + * DDR Byte Congestion Middle Threshold + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR 0x18 + +/* + * DDR copy bytes Lower Threshold. + * When working in packet drop mode (DDR_BYTES_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then all packets + * are dropped. + * * If (DDR_BYTES_MID_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (DDR_BYTES_LOWER_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_MID_THR), then packets in low priority are dropped. + * * If (DDR copy bytes counter) <= (DDR_BYTES_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_BYTES_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_BYTES_LOWER_THR + * and DDR_BYTES_MID_THR are dont care). +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_MASK 0x3fffffff + + +/* + * Register + * + * DDR Byte Congestion Higher Threshold + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR 0x1c + +/* + * DDR copy bytes Lower Threshold. + * When working in packet drop mode (DDR_BYTES_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then all packets + * are dropped. + * * If (DDR_BYTES_MID_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (DDR_BYTES_LOWER_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_MID_THR), then packets in low priority are dropped. + * * If (DDR copy bytes counter) <= (DDR_BYTES_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_BYTES_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_BYTES_LOWER_THR + * and DDR_BYTES_MID_THR are dont care). +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_MASK 0x3fffffff + + +/* + * Register + * + * DDR PD Congestion Control Register + */ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL 0x20 + +/* + * This field indicates whether crossing the DDR Pipe thresholds will + * result in dropping packets or in applying back pressure to the re-order. + * 0 - apply back pressure1 - drop packets +*/ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_MASK 0x1 + +/* + * DDR copy Pipe Lower Threshold. + * When working in packet drop mode (DDR_PD_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then packets in + * low/high priority are dropped (only exclusive packets are not dropped). + * * If (DDR_PIPE_LOWER_THR) < (DDR copy pipe occupancy) <= + * (DDR_PIPE_HIGHER_THR), then packets in low priority are dropped. + * * If (DDR copy pipe occupancy) <= (DDR_PIPE_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_PD_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_PIPE_LOWER_THR is + * dont care). +*/ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_SHIFT 8 +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_MASK 0xff00 + +/* + * DDR copy Pipe Lower Threshold. + * When working in packet drop mode (DDR_PD_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then packets in + * low/high priority are dropped (only exclusive packets are not dropped). + * * If (DDR_PIPE_LOWER_THR) < (DDR copy pipe occupancy) <= + * (DDR_PIPE_HIGHER_THR), then packets in low priority are dropped. + * * If (DDR copy pipe occupancy) <= (DDR_PIPE_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_PD_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_PIPE_LOWER_THR is + * dont care). + * IMPORTANT: + * recommended maximum value is 0x7B in order to avoid performance + * degradation when working with aggregation timeout enable +*/ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_SHIFT 16 +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_MASK 0xff0000 + + +/* + * Register + * + * QM PD Congestion Control Register + */ +#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL 0x24 + +/* + * If the number of PDs for a certain queue exceeds this value, then PDs + * will be dropped. +*/ +#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_SHIFT 0 +#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_MASK 0xfffffff + + +/* + * Register + * + * Absolute Adress drop queue + */ +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE 0x28 + +/* + * Absolute address drop queue. + * Absolute address PDs which are dropped will be redirected into this + * configured queue. + * FW will be responsible for reclaiming their DDR space. +*/ +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_SHIFT 0 +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_MASK 0x1ff + +/* + * Absolute address drop queue enable. + * Enables the mechanism in which absolute address PDs which are dropped + * are be redirected into this configured queue. + * FW will be responsible for reclaiming their DDR space. +*/ +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_MASK 0x10000 + + +/* + * Register + * + * Aggregation Control register + */ +#define QM_GLOBAL_CFG_AGGREGATION_CTRL 0x2c + +/* This field indicates the maximum number of bytes in an aggregated PD. */ +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_SHIFT 0 +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_MASK 0x3ff + +/* This field indicates the maximum number of packets in an aggregated PD */ +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_SHIFT 16 +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_MASK 0x30000 + + +/* + * Register + * + * FPM Base Address + */ +#define QM_GLOBAL_CFG_FPM_BASE_ADDR 0x30 + +/* + * FPM Base Address. + * This is the 32-bit MSBs out of the 40-bit address. + * Multiply this field by 256 to get the 40-bit address. + * Example: + * If desired base address is 0x0080_0000The FPM_BASE_ADDR field should be + * configured to: + * 0x0000_8000. +*/ +#define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_SHIFT 0 +#define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_MASK 0xffffffff + + +/* + * Register + * + * FPM Base Address for PDs that have the coherent bit set + */ +#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR 0x34 + +/* + * FPM Base Address. + * This is the 32-bit MSBs out of the 40-bit address. + * Multiply this field by 256 to get the 40-bit address. + * Example: + * If desired base address is 0x0080_0000The FPM_BASE_ADDR field should be + * configured to: + * 0x0000_8000. +*/ +#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_SHIFT 0 +#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_MASK 0xffffffff + + +/* + * Register + * + * DDR SOP Offset options + */ +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET 0x38 + +/* DDR SOP Offset option 0 */ +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_MASK 0x7ff + +/* DDR SOP Offset option 1 */ +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_SHIFT 16 +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_MASK 0x7ff0000 + + +/* + * Register + * + * EPON Ghost reporting configuration + */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL 0x3c + +/* EPON Line Rate0 - 1G1 - 10G */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_MASK 0x1 + +/* + * If this bit is not set then 4-bytes will be added to the ghost reporting + * accumulated bytes and to the byte overhead calculation input +*/ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_MASK 0x2 + +/* Enables to overwrite CRC addition specified MAC FLOW in the field below. */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_EN_MASK 0x4 + +/* MAC flow ID to force disable CRC addition */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_SHIFT 3 +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_MASK 0x7f8 + +/* FEC IPG Length */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_SHIFT 16 +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_MASK 0x7ff0000 + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Queue Full indicationEach register includes a batch of 32 queues + * non-empty indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_DQM_FULL(x) (0x40 + (x) * 0x4) + +/* + * Queue Full indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_SHIFT 0 +#define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Queue Not Empty indicationEach register includes a batch of 32 queues + * non-empty indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_DQM_NOT_EMPTY(x) (0x70 + (x) * 0x4) + +/* + * Queue Not empty indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_SHIFT 0 +#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Queue pop ready indication (Some queues may be non-empty, but due to PD + * offload they are not immediatly ready to be popped. + * Pop can be issued, but in this case the result could be delayed). + * Each register includes a batch of 32 queues non-empty indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_DQM_POP_READY(x) (0xa0 + (x) * 0x4) + +/* + * Queue pop ready indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_SHIFT 0 +#define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Aggregation context valid. + * This indicates that the queue is in the process of packet aggregation. + * Each register includes a batch of 32 queues aggregation valid + * indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID(x) (0xd0 + (x) * 0x4) + +/* + * QM ingress aggregation context valid indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_SHIFT 0 +#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_MASK 0xffffffff + + +/* + * Register + * + * Open aggregation will be forced to close after internal timer + * expiration. + * The first byte (0-7bits) controls the granularity of the internal + * counter (valid value 0x0-0x3)The second byte (8-15bits) controls the + * timout value (valid values 0x0-0x7), which is counted according to + * granularity cycles. + * the 16bit is enable for the mechanism + */ +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL 0x100 + +/* + * defines the granularity of the prescaler counter: + * 0 = 10bits1 = 11bits2 = 12bits3 = 13bits4 = 14bits5 = 15bits6 = + * 16bitsdebug: + * 7 = 5bits +*/ +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_SHIFT 0 +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_MASK 0x7 + +/* + * Aggregation timeout value, counted in prescaler counters cycles. + * valid values = [1. + * .7] +*/ +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_SHIFT 8 +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_MASK 0x700 + + +/* + * Register + * + * FPM global user group counter: + * UG0-3 + UG7 + */ +#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT 0x118 + +/* FPM global counter */ +#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_SHIFT 0 +#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_MASK 0xffff + + +/* + * Register + * + * 0-8b: + * queue to flush9b: + * enable flush + */ +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE 0x11c + +/* Queue num */ +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_SHIFT 0 +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_MASK 0x1ff + +/* flush queue enable */ +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_MASK 0x200 + + +/* + * Registers - is [ 0 => 3 ] + * + * Hold 2 thresholds per FPM pool for priority management + */ +#define QM_FPM_POOLS_THR(x) (0x200 + (x) * 0x20) + +/* + * FPM Lower Threshold. + * When working in packet drop mode (FPM_BP_ENABLE=0), Then: + * * If (FPM pool occupancy) <= (FPM_LOWER_THR), then packets in low/high + * priority are dropped (only exclusive packets are not dropped). + * * If (FPM_LOWER_THR) < (FPM pool occupancy) <= (FPM_HIGHER_THR), then + * packets in low priority are dropped. + * * If (FPM pool occupancy) > (FPM_HIGHER_THR), then no packets are + * dropped. + * When working in backpressure mode (FPM_BP_ENABLE=1), Then if (FPM pool + * occupancy) < (FPM_LOWER_THR), then backpressure is applied to re-order + * (in this case FPM_HIGHER_THR is dont care). +*/ +#define QM_FPM_POOLS_THR_FPM_LOWER_THR_SHIFT 0 +#define QM_FPM_POOLS_THR_FPM_LOWER_THR_MASK 0x7f + +/* + * FPM Higher Threshold. + * When working in packet drop mode (FPM_BP_ENABLE=0), Then: + * * If (FPM pool occupancy) <= (FPM_LOWER_THR), then packets in low/high + * priority are dropped (only exclusive packets are not dropped). + * * If (FPM_LOWER_THR) < (FPM pool occupancy) <= (FPM_HIGHER_THR), then + * packets in low priority are dropped. + * * If (FPM pool occupancy) > (FPM_HIGHER_THR), then no packets are + * dropped. + * When working in backpressure mode (FPM_BP_ENABLE=1), Then if (FPM pool + * occupancy) < (FPM_LOWER_THR), then backpressure is applied to re-order + * (in this case FPM_HIGHER_THR is dont care). +*/ +#define QM_FPM_POOLS_THR_FPM_HIGHER_THR_SHIFT 8 +#define QM_FPM_POOLS_THR_FPM_HIGHER_THR_MASK 0x7f00 + + +/* + * Registers - is [ 0 => 3 ] + * + * Holds FPM user group lower threshold. + */ +#define QM_FPM_USR_GRP_LO_THR(x) (0x280 + (x) * 0x20) + +/* + * FPM group Lower Threshold. + * * If (FPM User Group Counter) > (FPM_GRP_HIGHER_THR), all packets in + * this user group are dropped. + * * If (FPM_GRP_MID_THR) < (FPM User Group Counter) <= + * (FPM_GRP_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (FPM_GRP_LOWER_THR) < (FPM User Group Counter) <= + * (FPM_GRP_MID_THR), then packets in low priority are dropped. + * * If (FPM User Group Counter) <= (FPM_GRP_LOWER_THR), then no packets + * are dropped. +*/ +#define QM_FPM_USR_GRP_LO_THR_FPM_GRP_LOWER_THR_SHIFT 0 +#define QM_FPM_USR_GRP_LO_THR_FPM_GRP_LOWER_THR_MASK 0xffff + + +/* + * Registers - is [ 0 => 3 ] + * + * Holds FPM user group middle threshold. + * *IMPORTANT* if buffer reservations is enabled, the following should be + * honored: + * HIGHER_THR-MID_THR > 16 + */ +#define QM_FPM_USR_GRP_MID_THR(x) (0x284 + (x) * 0x20) + +/* + * FPM group Lower Threshold. + * * If (FPM User Group Counter) > (FPM_GRP_HIGHER_THR), all packets in + * this user group are dropped. + * * If (FPM_GRP_MID_THR) < (FPM User Group Counter) <= + * (FPM_GRP_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (FPM_GRP_LOWER_THR) < (FPM User Group Counter) <= + * (FPM_GRP_MID_THR), then packets in low priority are dropped. + * * If (FPM User Group Counter) <= (FPM_GRP_LOWER_THR), then no packets + * are dropped. +*/ +#define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_SHIFT 0 +#define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_MASK 0xffff + + +/* + * Registers - is [ 0 => 3 ] + * + * Holds FPM user group higher threshold. + * *IMPORTANT* if buffer reservations is enabled, the following should be + * honored: + * HIGHER_THR-MID_THR > 16 + */ +#define QM_FPM_USR_GRP_HIGHER_THR(x) (0x288 + (x) * 0x20) + +/* + * FPM group Lower Threshold. + * * If (FPM User Group Counter) > (FPM_GRP_HIGHER_THR), all packets in + * this user group are dropped. + * * If (FPM_GRP_MID_THR) < (FPM User Group Counter) <= + * (FPM_GRP_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (FPM_GRP_LOWER_THR) < (FPM User Group Counter) <= + * (FPM_GRP_MID_THR), then packets in low priority are dropped. + * * If (FPM User Group Counter) <= (FPM_GRP_LOWER_THR), then no packets + * are dropped. +*/ +#define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_SHIFT 0 +#define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_MASK 0xffff + + +/* + * Registers - is [ 0 => 3 ] + * + * FPM user group buffer counter + */ +#define QM_FPM_USR_GRP_CNT(x) (0x28c + (x) * 0x20) + +/* FPM user group counter */ +#define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_SHIFT 0 +#define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_MASK 0xffff + + +/* + * Registers - is [ 0 => 15 ] + * + * Runners Configurations + */ +#define QM_RUNNER_GRP_RNR_CONFIG(x) (0x300 + (x) * 0x10) + +/* Runner BB ID associated with this configuration. */ +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_SHIFT 0 +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_MASK 0x3f + +/* Runner Task number to be woken up when the update FIFO is written to. */ +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_SHIFT 8 +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_MASK 0xf00 + +/* Enable this runner interface */ +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_MASK 0x10000 + + +/* + * Registers - is [ 0 => 15 ] + * + * Consecutive queues which are associated with this runner + */ +#define QM_RUNNER_GRP_QUEUE_CONFIG(x) (0x304 + (x) * 0x10) + +/* + * Indicates the Queue that starts this runner group. + * Queues belonging to the runner group are defined by the following + * equation: + * START_QUEUE <= runner_queues <= END_QUEUE +*/ +#define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_SHIFT 0 +#define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_MASK 0x1ff + +/* + * Indicates the Queue that ends this runner group. + * Queues belonging to the runner group are defined by the following + * equation: + * START_QUEUE <= runner_queues <= END_QUEUE +*/ +#define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_SHIFT 16 +#define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 15 ] + * + * head of the queue PD FIFO attributes + */ +#define QM_RUNNER_GRP_PDFIFO_CONFIG(x) (0x308 + (x) * 0x10) + +/* + * PD FIFO Base Address. + * This is an 8-byte address (Byte_addr = BASE_ADDR*8). +*/ +#define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_SHIFT 3 +#define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_MASK 0x3ff8 + +/* PD FIFO Size0 - 2 entries1 - 4 entries2 - 8 entries */ +#define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_SHIFT 16 +#define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_MASK 0x30000 + + +/* + * Registers - is [ 0 => 15 ] + * + * Update FIFO attributes + */ +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG(x) (0x30c + (x) * 0x10) + +/* + * PD FIFO Base Address. + * This is an 8-byte address (Byte_addr = BASE_ADDR*8). +*/ +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_SHIFT 3 +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_MASK 0x3ff8 + +/* + * PD FIFO Size0 - 8 entries1 - 16 entries2 - 32 entries3 - 64 entries4 - + * 128 entries5 - 256 entries +*/ +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_SHIFT 16 +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_MASK 0x70000 + + +/* + * Register + * + * This register contains the current active QM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define QM_INTR_CTRL_ISR 0x400 + +/* HW tried to pop a PD from the DQM of an empty queue. */ +#define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_MASK 0x1 + +/* HW tried to pop a PD into the DQM of a full queue. */ +#define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_MASK 0x2 + +/* CPU tried to pop a PD from the DQM of an empty queue. */ +#define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_MASK 0x4 + +/* CPU tried to push a PD into the DQM of a full queue. */ +#define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_MASK 0x8 + +/* A PD arrived to the Normal queue without having any credits */ +#define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_MASK 0x10 + +/* A PD arrived to the NON-delayed queue without having any credits */ +#define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CREDIT_MASK 0x20 + +/* A PD arrived with a non valid queue number (>287) */ +#define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_MASK 0x40 + +/* + * An aggregation of PDs was done in which the coherent bit of the PD + * differs between them (The coherent bit of the first aggregated PD was + * used) +*/ +#define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_MASK 0x80 + +/* + * A PD with force copy bit set was received on the non-delayed queue (in + * this queue the copy machine is bypassed) +*/ +#define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_MASK 0x100 + +/* + * A PD was marked to be copied, but there does not exist an FPM pool + * buffer large enough to hold it. +*/ +#define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_MASK 0x200 + +/* + * A PD was marked with a target_mem=1 (located in PSRAM) and on the other + * hand, the absolute address indication was set. +*/ +#define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTION_MASK 0x400 + +/* 1588 Packet is dropped when the QM PD occupancy exceeds threshold (64K) */ +#define QM_INTR_CTRL_ISR_QM_1588_DROP_MASK 0x800 + +/* A PD was marked as a 1588 and multicast together. */ +#define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTION_MASK 0x1000 + +/* + * The byte drop counter of one of the queues reached its maximum value and + * a new value was pushed. +*/ +#define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_MASK 0x2000 + +/* + * The Packet drop counter of one of the queues reached its maximum value + * and a new value was pushed. +*/ +#define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_MASK 0x4000 + +/* The Total byte counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_MASK 0x8000 + +/* The Total PD counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_MASK 0x10000 + +/* The UG0 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_MASK 0x20000 + +/* The UG1 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_MASK 0x40000 + +/* The UG2 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_MASK 0x80000 + +/* The UG3 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_MASK 0x100000 + +/* + * QM aggregation timers wraps around. + * In this case it isnt guaranteed that the aggregation will be closed on + * pre-defined timeout expiration. + * However the aggregation should be closed eventually. +*/ +#define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_MASK 0x200000 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define QM_INTR_CTRL_ISM 0x404 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define QM_INTR_CTRL_ISM_ISM_SHIFT 0 +#define QM_INTR_CTRL_ISM_ISM_MASK 0x3fffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define QM_INTR_CTRL_IER 0x408 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define QM_INTR_CTRL_IER_IEM_SHIFT 0 +#define QM_INTR_CTRL_IER_IEM_MASK 0x3fffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define QM_INTR_CTRL_ITR 0x40c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define QM_INTR_CTRL_ITR_IST_SHIFT 0 +#define QM_INTR_CTRL_ITR_IST_MASK 0x3fffff + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define QM_CLK_GATE_CLK_GATE_CNTRL 0x500 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Access Control + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL(x) (0x600 + (x) * 0x40) + +/* Queue Number */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_MASK 0x1ff + +/* + * Command: + * 00 - Nothing01 - Write10 - Read11 - Read No commit (entry not + * popped)Will trigger a read/write from the selected RAMIMPORTANT: + * Read is for debug purpose only. + * shouldnt be used during regular QM work on the requested queue (HW pop). + * Popping the same queue both from CPU and HW could cause to race + * condition which will cause to incorrect data output. + * It could occur when there is only one entry in the queue which is + * accessed both from the CPU and the HW. +*/ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_SHIFT 16 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_MASK 0x30000 + +/* Indicates that read/write to DQM is done */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_MASK 0x1000000 + +/* Indicates that that an error occured (write on full or read on empty) */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_MASK 0x2000000 + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0(x) (0x610 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1(x) (0x614 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2(x) (0x618 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3(x) (0x61c + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0(x) (0x620 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1(x) (0x624 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2(x) (0x628 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3(x) (0x62c + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * This RAM holds all queue attributes. + * Not all of the 32-bits in the address space are implemented. + * WRED Profile 3: + * 0Copy decision profile 6: + * 4Copy to DDR 7DDR copy disable 8Aggregation Disable 9FPM User Group 11: + * 10Exclusive Priority 12802. + * 1AE 13SCI 14FEC Enable 15 + */ +#define QM_QUEUE_CONTEXT_CONTEXT(x) (0x800 + (x) * 0x4) + +/* Defines to which WRED Profile this queue belongs to. */ +#define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_SHIFT 0 +#define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_MASK 0xf + +/* Defines to which Copy Decision Profile this queue belongs to. */ +#define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_SHIFT 4 +#define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_MASK 0x70 + +/* Defines this queue to always copy to DDR. */ +#define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_MASK 0x80 + +/* Defines this queue never to copy to DDR. */ +#define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_MASK 0x100 + +/* Defines this queue never to aggregated PDs. */ +#define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_MASK 0x200 + +/* Defines to which FPM UG this queue belongs to. */ +#define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_SHIFT 10 +#define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_MASK 0x1c00 + +/* Defines this queue with exclusive priority. */ +#define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_MASK 0x2000 + +/* + * Defines this queue as 802. + * 1AE for EPON packet overhead calculations. +*/ +#define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_MASK 0x4000 + +/* Configures SCI for EPON packet overhead calculations. */ +#define QM_QUEUE_CONTEXT_CONTEXT_SCI_MASK 0x8000 + +/* FEC enable configuration for EPON packet overhead calculations. */ +#define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_MASK 0x10000 + +/* + * FPM reservation profile. + * Once the QM goes over global FPM reservation threshold. + * Queue with more bytes the defined in the profile will be dropped. + * Profile 0 means no drop due to FPM reservation for the queues with this + * profile. +*/ +#define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_SHIFT 17 +#define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_MASK 0xe0000 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color min thresholds + */ +#define QM_WRED_PROFILE_COLOR_MIN_THR_0(x) (0x1000 + (x) * 0x30) + +/* + * WRED Color Min Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_MASK 0xffffff + +/* + * 0 - flow control disable. + * regular WRED profile1 - flow control enable. + * no WRED drop, wake up appropriate runner task when crossed. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color min thresholds + */ +#define QM_WRED_PROFILE_COLOR_MIN_THR_1(x) (0x1004 + (x) * 0x30) + +/* + * WRED Color Min Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_MASK 0xffffff + +/* + * 0 - flow control disable. + * regular WRED profile1 - flow control enable. + * no WRED drop, wake up appropriate runner task when crossed. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color max thresholds + */ +#define QM_WRED_PROFILE_COLOR_MAX_THR_0(x) (0x1010 + (x) * 0x30) + +/* + * WRED Color Max Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_MASK 0xffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color max thresholds + */ +#define QM_WRED_PROFILE_COLOR_MAX_THR_1(x) (0x1014 + (x) * 0x30) + +/* + * WRED Color Max Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_MASK 0xffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color slopes + */ +#define QM_WRED_PROFILE_COLOR_SLOPE_0(x) (0x1020 + (x) * 0x30) + +/* WRED Color slope mantissa. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_MASK 0xff + +/* WRED Color slope exponent. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_SHIFT 8 +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color slopes + */ +#define QM_WRED_PROFILE_COLOR_SLOPE_1(x) (0x1024 + (x) * 0x30) + +/* WRED Color slope mantissa. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_MASK 0xff + +/* WRED Color slope exponent. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_SHIFT 8 +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * DDR Pipe and PSRAM threshold configurations for DDR copy decision logic + */ +#define QM_COPY_DECISION_PROFILE_THR(x) (0x1800 + (x) * 0x20) + +/* + * Queue Occupancy Threshold. + * When passing this threhold, packets will be copied to the DDR +*/ +#define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_SHIFT 0 +#define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_MASK 0x3fffffff + +/* + * Indicates which of the two PSRAM threshold crossing indications coming + * from the SBPM will be used for the copy decision. + * when going over the chosen threshold, packets will be copied to the DDR. + * 0 - Lower threshold1 - Higher threshold +*/ +#define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 639 ] + * + * Counter. + * word0: + * {15`b0,pkt_cnt[16: + * 0]}word1: + * {2`b0,byte_cnt[29: + * 0]}word2: + * {15b0,res_cnt[16: + * 0]}word3: + * reservedThere are three words per queue starting at queue0 up to queue + * 159/287. + */ +#define QM_TOTAL_VALID_COUNTER_COUNTER(x) (0x2000 + (x) * 0x4) + +/* DATA */ +#define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_SHIFT 0 +#define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 319 ] + * + * Counter. + * word0: + * {15`b0,pkt_cnt[16: + * 0]}word1: + * {2`b0,byte_cnt[29: + * 0]}There are two words per queue starting at queue0 up to queue 287. + */ +#define QM_DQM_VALID_COUNTER_COUNTER(x) (0x3000 + (x) * 0x4) + +/* DATA */ +#define QM_DQM_VALID_COUNTER_COUNTER_DATA_SHIFT 0 +#define QM_DQM_VALID_COUNTER_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 319 ] - read-only + * + * Counter. + * word0: + * {6`b0,pkt_cnt[25: + * 0]}word1: + * {byte_cnt[31: + * 0]}in WRED drop mode: + * word0 - color1 dropped packetsword1 - color0 dropped packetsThere are + * two words per queue starting at queue0 up to queue 287. + */ +#define QM_DROP_COUNTER_COUNTER(x) (0x4000 + (x) * 0x4) + +/* DATA */ +#define QM_DROP_COUNTER_COUNTER_DATA_SHIFT 0 +#define QM_DROP_COUNTER_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 319 ] + * + * Counter - For each of the 32-queues in a batch, this counter stores a + * 32-bit accumulated and overhead byte counter per queue. + * word0: + * {accumulated_bytes[31: + * 0]}word1: + * {accumulated_overhead[31: + * 0}There are two words per queue starting at queue0 up to queue 127. + */ +#define QM_EPON_RPT_CNT_COUNTER(x) (0x5000 + (x) * 0x4) + +/* DATA */ +#define QM_EPON_RPT_CNT_COUNTER_DATA_SHIFT 0 +#define QM_EPON_RPT_CNT_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 4 ] - read-only + * + * Status bit vector - For each of the 32-queues in a batch, this status + * indicates which queue counter has been updated. + */ +#define QM_EPON_RPT_CNT_QUEUE_STATUS(x) (0x5500 + (x) * 0x4) + +/* + * Status bit vector - a bit per queue indicates if the queue has been + * updated. +*/ +#define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_SHIFT 0 +#define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL0 0x5800 + +/* DATA */ +#define QM_RD_DATA_POOL0_DATA_SHIFT 0 +#define QM_RD_DATA_POOL0_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL1 0x5804 + +/* DATA */ +#define QM_RD_DATA_POOL1_DATA_SHIFT 0 +#define QM_RD_DATA_POOL1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL2 0x5808 + +/* DATA */ +#define QM_RD_DATA_POOL2_DATA_SHIFT 0 +#define QM_RD_DATA_POOL2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL3 0x580c + +/* DATA */ +#define QM_RD_DATA_POOL3_DATA_SHIFT 0 +#define QM_RD_DATA_POOL3_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * PDFIFO per queue rd/wr pointers + */ +#define QM_PDFIFO_PTR(x) (0x6000 + (x) * 0x4) + +/* PDFIFO WR pointers */ +#define QM_PDFIFO_PTR_WR_PTR_SHIFT 0 +#define QM_PDFIFO_PTR_WR_PTR_MASK 0xf + +/* PDFIFO RD pointers */ +#define QM_PDFIFO_PTR_RD_PTR_SHIFT 8 +#define QM_PDFIFO_PTR_RD_PTR_MASK 0xf00 + + +/* + * Registers - is [ 0 => 15 ] - read-only + * + * Update FIFO rd/wr pointers + */ +#define QM_UPDATE_FIFO_PTR(x) (0x6500 + (x) * 0x4) + +/* UF WR pointers */ +#define QM_UPDATE_FIFO_PTR_WR_PTR_SHIFT 0 +#define QM_UPDATE_FIFO_PTR_WR_PTR_MASK 0x1ff + +/* UF RD pointers */ +#define QM_UPDATE_FIFO_PTR_RD_PTR_SHIFT 9 +#define QM_UPDATE_FIFO_PTR_RD_PTR_MASK 0xfe00 + + +/* + * Registers - is [ 0 => 4 ] - read-only + * + * Debug - Read the head of the FIFO + */ +#define QM_RD_DATA(x) (0x8800 + (x) * 0x4) + +/* DATA */ +#define QM_RD_DATA_DATA_SHIFT 0 +#define QM_RD_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * Pop an entry in the FIFO + */ +#define QM_POP 0x8820 + +/* Pop FIFO entry */ +#define QM_POP_POP_MASK 0x1 + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * CM Common Input FIFO - debug access + */ +#define QM_CM_COMMON_INPUT_FIFO_DATA(x) (0x9000 + (x) * 0x4) + +/* DATA */ +#define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Normal Remote FIFO - debug access + */ +#define QM_NORMAL_RMT_FIFO_DATA(x) (0x9100 + (x) * 0x4) + +/* DATA */ +#define QM_NORMAL_RMT_FIFO_DATA_DATA_SHIFT 0 +#define QM_NORMAL_RMT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Non-delayed Remote FIFO - debug access + */ +#define QM_NON_DELAYED_RMT_FIFO_DATA(x) (0x9200 + (x) * 0x4) + +/* DATA */ +#define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_SHIFT 0 +#define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * Egress data FIFO - debug access + */ +#define QM_EGRESS_DATA_FIFO_DATA(x) (0x9300 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_DATA_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_DATA_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Egress RR FIFO - debug access + */ +#define QM_EGRESS_RR_FIFO_DATA(x) (0x9400 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_RR_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_RR_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * Egress BB Input FIFO - debug access + */ +#define QM_EGRESS_BB_INPUT_FIFO_DATA(x) (0x9500 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Egress BB Output FIFO - debug access + */ +#define QM_EGRESS_BB_OUTPUT_FIFO_DATA(x) (0x9600 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * QM BB Output FIFO - debug access + */ +#define QM_BB_OUTPUT_FIFO_DATA(x) (0x9700 + (x) * 0x4) + +/* DATA */ +#define QM_BB_OUTPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_BB_OUTPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Non delayed output FIFO - debug access + */ +#define QM_NON_DELAYED_OUT_FIFO_DATA(x) (0x9800 + (x) * 0x4) + +/* DATA */ +#define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 639 ] - read-only + * + * Aggregation context - debug access + */ +#define QM_CONTEXT_DATA(x) (0xa000 + (x) * 0x4) + +/* DATA */ +#define QM_CONTEXT_DATA_DATA_SHIFT 0 +#define QM_CONTEXT_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] + * + * Reserved FPM buffers in units of min. + * FPM buffer. + * entry0 -> profile0. + * .. + * entry7 -> profile7 + */ +#define QM_FPM_BUFFER_RESERVATION_DATA(x) (0xc000 + (x) * 0x4) + +/* DATA */ +#define QM_FPM_BUFFER_RESERVATION_DATA_DATA_SHIFT 0 +#define QM_FPM_BUFFER_RESERVATION_DATA_DATA_MASK 0xffff + + +/* + * Register + * + * FPM user group ctrl + */ +#define QM_FLOW_CTRL_UG_CTRL 0xc100 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG0_EN_MASK 0x1 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG1_EN_MASK 0x2 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG2_EN_MASK 0x4 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG3_EN_MASK 0x8 + + +/* + * Register + * + * Keeps status vector of user group + wred are under flow control. + * 3: + * 0 - {ug3,ug2,ug1,ug0}, 4 - OR on wred_sourcefor UG -queues which passed + * the mid. + * thr. + * is set to 1. + * the user groups indication is de-asserted when the occupancy reaches the + * low thr. + * 4bits - bit for each user group. + * for WRED/occupancy -If one of the queues which pass color1 min occupancy + * marked as 1. + * when the occupancy is reduced to below than color0 min occupancy in all + * queues the bit is set to 0. + * FW can set/reset the value, it will updated when flow control which is + * relevant to the corresponding bit takes place. + */ +#define QM_FLOW_CTRL_STATUS 0xc104 + +/* User group 0 status */ +#define QM_FLOW_CTRL_STATUS_UG0_MASK 0x1 + +/* User group 1 status */ +#define QM_FLOW_CTRL_STATUS_UG1_MASK 0x2 + +/* User group 2 status */ +#define QM_FLOW_CTRL_STATUS_UG2_MASK 0x4 + +/* User group 3 status */ +#define QM_FLOW_CTRL_STATUS_UG3_MASK 0x8 + +/* OR on all wred flow control queues */ +#define QM_FLOW_CTRL_STATUS_WRED_MASK 0x10 + +/* reserved */ +#define QM_FLOW_CTRL_STATUS_R0_SHIFT 5 +#define QM_FLOW_CTRL_STATUS_R0_MASK 0xffffffe0 + + +/* + * Registers - is [ 0 => 4 ] + * + * Keeps status vector of queues which are under flow control: + * queues which passed the color1 low threshold is set to 1. + * the queue indication is de-asserted when the queue byte occupancy + * reaches the color0 low threshold. + * 320bits - bit for each queue number (up to 320 queues). + */ +#define QM_FLOW_CTRL_WRED_SOURCE(x) (0xc108 + (x) * 0x4) + +/* each bit represents queue */ +#define QM_FLOW_CTRL_WRED_SOURCE_SRC_SHIFT 0 +#define QM_FLOW_CTRL_WRED_SOURCE_SRC_MASK 0xffffffff + + +/* + * Register + * + * lossless flow control configuration + */ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG 0xc130 + +/* Runner BB ID */ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_SHIFT 0 +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_MASK 0x3f + +/* Runner task */ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_SHIFT 8 +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_MASK 0xf00 + +/* + * Runner enable. + * if disable, the lossless flow control is disabled. +*/ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_MASK 0x10000 + + +/* + * Register + * + * Controls Debug bus select: + * 5h1: + * qm_dbg_bus = qm_bb_input_dbg_bus;5h2: + * qm_dbg_bus = qm_bb_output_dbg_bus;5h3: + * qm_dbg_bus = qm_cm_dbg_bus;5h4: + * qm_dbg_bus = qm_ddr_write_dbg_bus;5h5: + * qm_dbg_bus = qm_counters_dbg_bus;5h6: + * qm_dbg_bus = qm_cpu_if_dbg_bus;5h7: + * qm_dbg_bus = qm_dqm_push_dbg_bus;5h8: + * qm_dbg_bus = qm_egress_dbg_bus;5h9: + * qm_dbg_bus = qm_fpm_prefetch_dbg_bus;5ha: + * qm_dbg_bus = qm_ingress_dbg_bus;5hb: + * qm_dbg_bus = qm_rmt_fifos_dbg_bus;5hc: + * qm_dbg_bus = {19b0,bbh_debug_0};5hd: + * qm_dbg_bus = {19b0,bbh_debug_1};5he: + * qm_dbg_bus = {19b0,bbh_debug_2};5hf: + * qm_dbg_bus = {19b0,bbh_debug_3};5h10: + * qm_dbg_bus = {19b0,bbh_debug_4};5h11: + * qm_dbg_bus = {19b0,bbh_debug_5};5h12: + * qm_dbg_bus = {19b0,bbh_debug_6};5h13: + * qm_dbg_bus = {19b0,bbh_debug_7};5h14: + * qm_dbg_bus = {19b0,bbh_debug_8};5h15: + * qm_dbg_bus = {19b0,bbh_debug_9};5h16: + * qm_dbg_bus = {19b0,dma_debug_vec};5h17: + * qm_dbg_bus = {8b0,dqm_diag_r}; + */ +#define QM_DEBUG_SEL 0x16000 + +/* Counter */ +#define QM_DEBUG_SEL_SELECT_SHIFT 0 +#define QM_DEBUG_SEL_SELECT_MASK 0x1f + +/* Enable register controlled debug select */ +#define QM_DEBUG_SEL_ENABLE_MASK 0x80000000 + + +/* + * Register - read-only + * + * Debug Bus sampling + */ +#define QM_DEBUG_BUS_LSB 0x16004 + +/* Data */ +#define QM_DEBUG_BUS_LSB_DATA_SHIFT 0 +#define QM_DEBUG_BUS_LSB_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug Bus sampling + */ +#define QM_DEBUG_BUS_MSB 0x16008 + +/* Data */ +#define QM_DEBUG_BUS_MSB_DATA_SHIFT 0 +#define QM_DEBUG_BUS_MSB_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Spare configuration for ECO purposes + */ +#define QM_QM_SPARE_CONFIG 0x1600c + +/* Data */ +#define QM_QM_SPARE_CONFIG_DATA_SHIFT 0 +#define QM_QM_SPARE_CONFIG_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and non-reprocessing packets from + * all queues + */ +#define QM_GOOD_LVL1_PKTS_CNT 0x16010 + +/* Counter */ +#define QM_GOOD_LVL1_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL1_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and non-reprocessing bytes from + * all queues + */ +#define QM_GOOD_LVL1_BYTES_CNT 0x16014 + +/* Counter */ +#define QM_GOOD_LVL1_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL1_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and reprocessing packets from all + * queues + */ +#define QM_GOOD_LVL2_PKTS_CNT 0x16018 + +/* Counter */ +#define QM_GOOD_LVL2_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL2_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and reprocessing bytes from all + * queues + */ +#define QM_GOOD_LVL2_BYTES_CNT 0x1601c + +/* Counter */ +#define QM_GOOD_LVL2_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL2_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of copied packets to the DDR from all queues + */ +#define QM_COPIED_PKTS_CNT 0x16020 + +/* Counter */ +#define QM_COPIED_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_COPIED_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of copied bytes to the DDR from all queues + */ +#define QM_COPIED_BYTES_CNT 0x16024 + +/* Counter */ +#define QM_COPIED_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_COPIED_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of aggregated packets from all queues + */ +#define QM_AGG_PKTS_CNT 0x16028 + +/* Counter */ +#define QM_AGG_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of aggregated bytes from all queues + */ +#define QM_AGG_BYTES_CNT 0x1602c + +/* Counter */ +#define QM_AGG_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_AGG_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 1-packet PD from all + * queues + */ +#define QM_AGG_1_PKTS_CNT 0x16030 + +/* Counter */ +#define QM_AGG_1_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_1_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 2-packet PD from all + * queues + */ +#define QM_AGG_2_PKTS_CNT 0x16034 + +/* Counter */ +#define QM_AGG_2_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_2_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 3-packet PD from all + * queues + */ +#define QM_AGG_3_PKTS_CNT 0x16038 + +/* Counter */ +#define QM_AGG_3_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_3_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 4-packet PD from all + * queues + */ +#define QM_AGG_4_PKTS_CNT 0x1603c + +/* Counter */ +#define QM_AGG_4_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_4_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to WRED + */ +#define QM_WRED_DROP_CNT 0x16040 + +/* Counter */ +#define QM_WRED_DROP_CNT_COUNTER_SHIFT 0 +#define QM_WRED_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to FPM + * congestion indication + */ +#define QM_FPM_CONGESTION_DROP_CNT 0x16048 + +/* Counter */ +#define QM_FPM_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to DDR PD + * congestion + */ +#define QM_DDR_PD_CONGESTION_DROP_CNT 0x16050 + +/* Counter */ +#define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to DDR + * byte congestion (number of bytes waiting to be copied exceeded the + * thresholds) + */ +#define QM_DDR_BYTE_CONGESTION_DROP_CNT 0x16054 + +/* Counter */ +#define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to QM PD + * congestion (this value is limited by the DQM) + */ +#define QM_QM_PD_CONGESTION_DROP_CNT 0x16058 + +/* Counter */ +#define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets requeued due to absolute address + * drops from all queues + */ +#define QM_QM_ABS_REQUEUE_CNT 0x1605c + +/* Counter */ +#define QM_QM_ABS_REQUEUE_CNT_COUNTER_SHIFT 0 +#define QM_QM_ABS_REQUEUE_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO0_STATUS 0x16060 + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO1_STATUS 0x16064 + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO2_STATUS 0x16068 + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO3_STATUS 0x1606c + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_NORMAL_RMT_FIFO_STATUS 0x16070 + +/* Used words */ +#define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_NORMAL_RMT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS 0x16074 + +/* Used words */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS 0x16078 + +/* Used words */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_PRE_CM_FIFO_STATUS 0x1607c + +/* Used words */ +#define QM_PRE_CM_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_PRE_CM_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_PRE_CM_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_PRE_CM_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_CM_RD_PD_FIFO_STATUS 0x16080 + +/* Used words */ +#define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_CM_RD_PD_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_CM_RD_PD_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_CM_WR_PD_FIFO_STATUS 0x16084 + +/* Used words */ +#define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_CM_WR_PD_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_CM_WR_PD_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS 0x16088 + +/* Used words */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_BB0_OUTPUT_FIFO_STATUS 0x1608c + +/* Used words */ +#define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_BB0_OUTPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_BB1_OUTPUT_FIFO_STATUS 0x16090 + +/* Used words */ +#define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_BB1_OUTPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_BB1_INPUT_FIFO_STATUS 0x16094 + +/* Used words */ +#define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_BB1_INPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_BB1_INPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_EGRESS_DATA_FIFO_STATUS 0x16098 + +/* Used words */ +#define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_EGRESS_DATA_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_EGRESS_RR_FIFO_STATUS 0x1609c + +/* Used words */ +#define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_EGRESS_RR_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_EGRESS_RR_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Registers - is [ 0 => 1 ] + * + * BB ROUTE Override: + * 0 - for QM_TOP1 - for RNR_GRID + */ +#define QM_BB_ROUTE_OVR(x) (0x160a0 + (x) * 0x4) + +/* BB rout address decode Override enable */ +#define QM_BB_ROUTE_OVR_OVR_EN_MASK 0x1 + +/* Destination ID */ +#define QM_BB_ROUTE_OVR_DEST_ID_SHIFT 8 +#define QM_BB_ROUTE_OVR_DEST_ID_MASK 0x3f00 + +/* Route Address */ +#define QM_BB_ROUTE_OVR_ROUTE_ADDR_SHIFT 16 +#define QM_BB_ROUTE_OVR_ROUTE_ADDR_MASK 0x3ff0000 + + +/* + * Register - read-only + * + * Holds the Ingress Status + */ +#define QM_QM_INGRESS_STAT 0x160b0 + +/* Stat */ +#define QM_QM_INGRESS_STAT_STAT_SHIFT 0 +#define QM_QM_INGRESS_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the Egress Status + */ +#define QM_QM_EGRESS_STAT 0x160b4 + +/* Stat */ +#define QM_QM_EGRESS_STAT_STAT_SHIFT 0 +#define QM_QM_EGRESS_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the CM Status + */ +#define QM_QM_CM_STAT 0x160b8 + +/* Stat */ +#define QM_QM_CM_STAT_STAT_SHIFT 0 +#define QM_QM_CM_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the FPM Prefetch Status + */ +#define QM_QM_FPM_PREFETCH_STAT 0x160bc + +/* Stat */ +#define QM_QM_FPM_PREFETCH_STAT_STAT_SHIFT 0 +#define QM_QM_FPM_PREFETCH_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * QM connect ack counter + */ +#define QM_QM_CONNECT_ACK_COUNTER 0x160c0 + +/* Pending SBPM Connect ACKs counter */ +#define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_SHIFT 0 +#define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_MASK 0xff + + +/* + * Register - read-only + * + * QM DDR WR reply Counter + */ +#define QM_QM_DDR_WR_REPLY_COUNTER 0x160c4 + +/* Pending DDR WR Replies counter */ +#define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_SHIFT 0 +#define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_MASK 0xff + + +/* + * Register - read-only + * + * QM DDR pipe byte counter + */ +#define QM_QM_DDR_PIPE_BYTE_COUNTER 0x160c8 + +/* Pending bytes to be copied to the DDR */ +#define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_SHIFT 0 +#define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_MASK 0xfffffff + + +/* + * Register - read-only + * + * Indicates the number of PDs currently in the Absolute address drop + * queue. + */ +#define QM_QM_ABS_REQUEUE_VALID_COUNTER 0x160cc + +/* Counter */ +#define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_SHIFT 0 +#define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_MASK 0x7fff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * PD captured when an illegal PD was detected and the relevant interrupt + * was generated. + */ +#define QM_QM_ILLEGAL_PD_CAPTURE(x) (0x160d0 + (x) * 0x4) + +/* PD */ +#define QM_QM_ILLEGAL_PD_CAPTURE_PD_SHIFT 0 +#define QM_QM_ILLEGAL_PD_CAPTURE_PD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Last ingress processed PD capture + */ +#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE(x) (0x160e0 + (x) * 0x4) + +/* PD */ +#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_SHIFT 0 +#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Last copy machine processed PD capture + */ +#define QM_QM_CM_PROCESSED_PD_CAPTURE(x) (0x160f0 + (x) * 0x4) + +/* PD */ +#define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_SHIFT 0 +#define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Counts the total number of packets dropped for all queues due to FPM + * pool priority thresholds. + * Counter per pool + */ +#define QM_FPM_POOL_DROP_CNT(x) (0x16100 + (x) * 0x4) + +/* Counter */ +#define QM_FPM_POOL_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_POOL_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Counts the total number of packets dropped from all queues due to FPM + * user group priority thresholds. + * Counter per UG (0-3) + */ +#define QM_FPM_GRP_DROP_CNT(x) (0x16110 + (x) * 0x4) + +/* Counter */ +#define QM_FPM_GRP_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_GRP_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to buffer + * reservation mechanism. + */ +#define QM_FPM_BUFFER_RES_DROP_CNT 0x16120 + +/* Counter */ +#define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to psram + * egress congestion. + */ +#define QM_PSRAM_EGRESS_CONG_DRP_CNT 0x16124 + +/* Counter */ +#define QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_SHIFT 0 +#define QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 2559 ] - read-only + * + * CM Residue - debug access + */ +#define QM_DATA(x) (0x20000 + (x) * 0x4) + +/* DATA */ +#define QM_DATA_DATA_SHIFT 0 +#define QM_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * VPB Base address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE 0x40004 + +/* base */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * VPB mask address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK 0x40008 + +/* mask */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_MASK 0xffffffff + + +/* + * Register + * + * APB Base address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE 0x4000c + +/* base */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * APB mask address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK 0x40010 + +/* mask */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_MASK 0xffffffff + + +/* + * Register + * + * DQM Base address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE 0x40014 + +/* base */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * DQM mask address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK 0x40018 + +/* mask */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_MASK 0xffffffff + + +/* + * Register + * + * The BBH supports working with different MAC types. + * Each MAC requires different interface and features. + * This register defines the type of MAC the BBH works with. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_MACTYPE 0x50000 + +/* MAC type */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_MACTYPE_TYPE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_MACTYPE_TYPE_MASK 0x7 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX 0x50004 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_DMASRC_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_DMASRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SDMASRC_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SDMASRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SBPMSRC_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SBPMSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_FPMSRC_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_FPMSRC_MASK 0x3f000000 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX 0x50008 + +/* + * source id. + * This id is used to determine the route to the 1st (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the 2nd (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the Runner that is responsible + * for sending status messages (WAN only). +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the Runner which is + * responsible for sending DBR/Ghost messages (WAN only). +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_MASK 0x3f000000 + + +/* + * Register + * + * Configurations for determining the address to read from the DDR/PSRAm + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX 0x5000c + +/* The data is arranged in the DDR in a fixed size buffers. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_BUFSIZE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_BUFSIZE_MASK 0x7 + +/* The packet offset byte resulotion. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_BYTERESUL_MASK 0x8 + +/* Static offset in 8-bytes resolution for non aggregated packets in DDR */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_SHIFT 4 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_MASK 0x1ff0 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE0_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE0_MASK 0x7f0000 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE1_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE1_MASK 0x7f000000 + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner + * address. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1(x) (0x50010 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_TCONTADDR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_TCONTADDR_MASK 0xffff + +/* + * Defines the SKB free address within the Runner address space. + * The address is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_SKBADDR_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_SKBADDR_MASK 0xffff0000 + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2(x) (0x50018 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_PTRADDR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_TASK_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Register + * + * The BBH reads the packet data from the DDR in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the DMA + * memory space. + * The read descriptors are arranged in a predefined space in the DMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX 0x50020 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCSIZE_SHIFT 6 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_MAXREQ_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on read requests of a + * jumbo packet (>2K) +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * The BBH reads the packet data from the PSRAM in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the SDMA + * memory space. + * The read descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX 0x50024 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCSIZE_SHIFT 6 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_MAXREQ_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on Jumbo packets (>2k) + * read requests +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * When packet transmission is done, the BBH releases the SBPM buffers. + * This register defines which release command is used: + * 1. + * Normal free with context2. + * Special free with context3. + * free without context + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG 0x50028 + +/* When this bit is enabled, the BBH will use free without context command. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_FREENOCNTXT_MASK 0x1 + +/* + * When this bit is enabled, the BBH will use special free with context + * command. + * This bit is relevant only if free without context_en is configured to 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_SPECIALFREE_MASK 0x2 + +/* maximum number of pending on the fly get next commands */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_MAXGN_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_MAXGN_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEL(x) (0x5002c + (x) * 0x4) + +/* + * DDR TM base. + * The address is in bytes resolution. + * The address should be aligned to 128 bytes. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEL_DDRTMBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEL_DDRTMBASE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEH(x) (0x50034 + (x) * 0x4) + +/* MSB of DDR TM base. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEH_DDRTMBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEH_DDRTMBASE_MASK 0xff + + +/* + * Register + * + * The BBH orders data both from DDR and PSRAM. + * The returned data is stored in two FIFOs for reordering. + * The two FIFOs are implemented in a single RAM. + * This register defines the division of the RAM to two FIFOs. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL 0x5003c + +/* + * The size of the PSRAM data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the PSRAM. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_MASK 0x3ff + +/* + * The size of the DDR data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the DDR. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_DDRSIZE_SHIFT 10 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_DDRSIZE_MASK 0xffc00 + +/* + * the base address of the PSRAM data FIFO in 8 bytes resolution. + * The DDR data FIFO base address is always 0. + * In case the whole RAM is to be dedicated to PSRAM data, the base should + * be 0 as well, and the DDR FIFO size should be configured to 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMBASE_SHIFT 20 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMBASE_MASK 0x3ff00000 + + +/* + * Register + * + * configurations related to different arbitration processes (ordering PDs, + * ordering data) + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_ARB_CFG 0x50040 + +/* + * this configuration determines whether to give high priority to a current + * transmitting queue or not. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_ARB_CFG_HIGHTRXQ_MASK 0x1 + + +/* + * Register + * + * override configuration for the route of one of the peripherals + * (DMA/SDMMA/FPM/SBPM?Runners) + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE 0x50044 + +/* route address */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_ROUTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_ROUTE_MASK 0x3ff + +/* destination source id */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_DEST_SHIFT 10 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_DEST_MASK 0xfc00 + +/* enable */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_EN_MASK 0x10000 + + +/* + * Registers - is [ 0 => 19 ] + * + * configuration which queue is managed by each of the two runners. + * Each register in this array configures 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_Q2RNR(x) (0x50048 + (x) * 0x4) + +/* Q0 configuration */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_Q2RNR_Q0_MASK 0x1 + +/* Q1 configuration */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_Q2RNR_Q1_MASK 0x2 + + +/* + * Register + * + * which task in the runner to wake-up when requesting a PD for a certain + * q. + * This register holds the task number of the first 8 queues. + * For queues 8-40 (if they exist) the task that will be waking is the one + * appearing in the PD_RNR_CFG regs, depending on which runner this queue + * is associated with. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK 0x500a0 + +/* task number for queue 0 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK0_MASK 0xf + +/* task number for queue 1 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK1_SHIFT 4 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK1_MASK 0xf0 + +/* task number for queue 2 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK2_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK2_MASK 0xf00 + +/* task number for queue 3 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK3_SHIFT 12 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK3_MASK 0xf000 + +/* task number for queue 4 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK4_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK4_MASK 0xf0000 + +/* task number for queue 5 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK5_SHIFT 20 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK5_MASK 0xf00000 + +/* task number for queue 6 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK6_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK6_MASK 0xf000000 + +/* task number for queue 7 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK7_SHIFT 28 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK7_MASK 0xf0000000 + + +/* + * Register + * + * This register enables reset of internal units (for possible WA + * purposes). + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD 0x500b0 + +/* + * Writing 1 to this register will reset the segmentation context table. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_CNTXTRST_MASK 0x1 + +/* + * Writing 1 to this register will reset the PDs FIFOs. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_PDFIFORST_MASK 0x2 + +/* + * Writing 1 to this register will reset the DMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_DMAPTRRST_MASK 0x4 + +/* + * Writing 1 to this register will reset the SDMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SDMAPTRRST_MASK 0x8 + +/* + * Writing 1 to this register will reset the BPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_BPMFIFORST_MASK 0x10 + +/* + * Writing 1 to this register will reset the SBPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SBPMFIFORST_MASK 0x20 + +/* + * Writing 1 to this register will reset the order keeper FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_OKFIFORST_MASK 0x40 + +/* + * Writing 1 to this register will reset the DDR data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_DDRFIFORST_MASK 0x80 + +/* + * Writing 1 to this register will reset the SRAM data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SRAMFIFORST_MASK 0x100 + +/* + * Writing 1 to this register will reset the SKB pointers. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SKBPTRRST_MASK 0x200 + +/* + * Writing 1 to this register will reset the EPON status FIFOs (per queue + * 32 fifos). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_STSFIFORST_MASK 0x400 + +/* + * Writing 1 to this register will reset the EPON request FIFO (8 entries + * FIFO that holds the packet requests from the EPON MAC). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_REQFIFORST_MASK 0x800 + +/* + * Writing 1 to this register will reset the EPON/GPON MSG FIFOThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_MSGFIFORST_MASK 0x1000 + +/* + * Writing 1 to this register will reset the GET NEXT FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_GNXTFIFORST_MASK 0x2000 + +/* + * Writing 1 to this register will reset the FIRST BN FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_FBNFIFORST_MASK 0x4000 + + +/* + * Register + * + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DBGSEL 0x500b4 + +/* + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DBGSEL_DBGSEL_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DBGSEL_DBGSEL_MASK 0x1f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL 0x500b8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * general purpose register + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_GPR 0x500bc + +/* general purpose register */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_GPR_GPR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_GPR_GPR_MASK 0xffffffff + + +/* + * Register + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE 0x50400 + +/* The base of PD FIFO for queue 0. */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE 0x50450 + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Register + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH 0x50500 + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff00 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH 0x50550 + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_EN 0x50600 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDEMPTY 0x50604 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Register + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the XLMAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH 0x50608 + +/* DDR Transmit threshold in 8 bytes resoltion */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_DDRTHRESH_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_DDRTHRESH_MASK 0x1ff + +/* SRAM Transmit threshold in 8 bytes resoltion */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_SRAMTHRESH_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_SRAMTHRESH_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that no traffic is about + * to arrive so the XLMAC may try to enter power saving mode. + * This register is used to enable this feature. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_EEE 0x5060c + +/* enable bit */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_EEE_EN_MASK 0x1 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that it should and + * calculate timestamp for the current packet that is being transmitted. + * The BBH gets the timestamping parameters in the PD and forward it to the + * XLMAC. + * This register is used to enable this feature. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TS 0x50610 + +/* enable bit */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TS_EN_MASK 0x1 + + +/* + * Register - read-only + * + * This counter counts the number of received PD for packets to be + * transmitted from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD 0x50a00 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received PDs for packets to be + * transmitted from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD 0x50a04 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP 0x50a08 + +/* + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of STS messages which were received from + * Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT 0x50a10 + +/* This counter counts the number of received status messages. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of STS which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP 0x50a14 + +/* + * This counter counts the number of STS which were dropped due to PD FIFO + * full. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG (DBR/Ghost) messages which were + * received from Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT 0x50a18 + +/* This counter counts the number of received DBR/ghost messages. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP 0x50a1c + +/* + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number Get next responses with a null BN. + * It counts the packets for all TCONTs together. + * This counter is cleared when read and freezes when maximum value is + * reached. + * This counter is relevant for Ethernet only. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL 0x50a20 + +/* This counter counts the number Get next responses with a null BN. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of packets that were flushed (bn was + * released without sending the data to the EPON MAC) due to flush request. + * The counter is global for all queues. + * The counter is read clear. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS 0x50a24 + +/* This counter counts the number of flushed packets */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of times a length error (mismatch between + * a request from the MAC and a PD from the Runner) occured. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR 0x50a28 + +/* This counter counts the number of times a length error occuered */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter Counts aggregation length error events. + * If one or more of the packets in an aggregated PD is shorter than 60 + * bytes, this counter will be incremented by 1. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR 0x50a2c + +/* + * This counter counts the number of times an aggregation length error + * occuered +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT 0x50a30 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT 0x50a34 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the SRAM. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE 0x50a38 + +/* This counter counts the number of transmitted bytes from the SRAM. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the DDR. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE 0x50a3c + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Register + * + * writing to this register creates a rd_en pulse to the selected array the + * SW wants to access. + * Each bit in the register represents one of the arrays the SW can access. + * The address inside the array is determined in the previous register + * (sw_rd_address). + * When writing to this register the SW should assert only one bit. + * If more than one is asserted, The HW will return the value read from the + * lsb selected array. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN 0x50a40 + +/* rd from the PD FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDSEL_MASK 0x1 + +/* rd from the PD valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDVSEL_MASK 0x2 + +/* rd from the PD empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_MASK 0x4 + +/* rd from the PD Full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_MASK 0x8 + +/* rd from the PD beliow empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_MASK 0x10 + +/* rd from the PD full for wakeup empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_MASK 0x20 + +/* rd from the first BN array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNSEL_MASK 0x40 + +/* rd from the first BN valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_MASK 0x80 + +/* rd from the first BN empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_MASK 0x100 + +/* rd from the first BN full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_MASK 0x200 + +/* rd from the first Get Next array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_MASK 0x400 + +/* rd from the get_next valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_MASK 0x800 + +/* rd from the get next empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_MASK 0x1000 + +/* rd from the get next full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_MASK 0x2000 + +/* rd from the gpon context array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_MASK 0x4000 + +/* rd from the BPM FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMSEL_MASK 0x8000 + +/* rd from the BPM FLUSH FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_MASK 0x10000 + +/* rd from the SBPM FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_MASK 0x20000 + +/* rd from the SBPM FLUSH FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_MASK 0x40000 + +/* rd from the STS FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSSEL_MASK 0x80000 + +/* rd from the STS valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSVSEL_MASK 0x100000 + +/* rd from the STS empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_MASK 0x200000 + +/* rd from the STS Full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_MASK 0x400000 + +/* rd from the STS beliow empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_MASK 0x800000 + +/* rd from the STS full for wakeup empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_MASK 0x1000000 + +/* rd from the MSG FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGSEL_MASK 0x2000000 + +/* rd from the msg valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_MASK 0x4000000 + +/* rd from the epon request FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_MASK 0x8000000 + +/* rd from the DATA FIFO (SRAM and DDR) */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_DATASEL_MASK 0x10000000 + +/* rd from the reorder FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_MASK 0x20000000 + +/* rd from the Timestamp Info FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_MASK 0x40000000 + +/* rd from the MAC TX FIFO. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_MASK 0x80000000 + + +/* + * Register + * + * the address inside the array the SW wants to read + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR 0x50a44 + +/* The address inside the array the sw wants to read */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_MASK 0x7ff + + +/* + * Register - read-only + * + * indirect memories and arrays read data + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA 0x50a48 + +/* data */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted packets through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDPKT(x) (0x50a50 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted bytes through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDBYTE(x) (0x50a70 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * an array including all the debug vectors of the BBH TX. + * entries 30 and 31 are DSL debug. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG(x) (0x50a90 + (x) * 0x4) + +/* Selected debug vector. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * 40 bit vector in which each bit represents if the segmentation SM is + * currently handling a PD of a certain TCONT. + * first address is for TCONTS [31: + * 0]second is for TCONTS [39: + * 32] + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_IN_SEGMENTATION(x) (0x50b20 + (x) * 0x4) + +/* in_segmentation indication */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_MASK 0xffffffff + + +/* + * Register + * + * Broadbus route override + */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD 0x60000 + +/* destination ID */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_MASK 0x3f + +/* the route to be used (override the default route) */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_MASK 0x3ff00 + +/* override enable */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_OVRD_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers defines the memory allocation for the + * peripherals, for upstream. + * The allocation is of number of 128byte buffers out of the total 48 + * buffers for both sdma and dma. + * The allocation is done by defining a only the number of allocated + * buffers. + * base address is calculated by HW, when base of peripheral 0 is 0. + * Note that the memory allocation should not contain wrap around. + * The number of allocated CDs is the same of data buffers. + */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES(x) (0x60004 + (x) * 0x4) + +/* the number of 128bytes buffers allocated to the peripheral. */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers controls the number of read requests of each + * peripheral within the read requests RAM. + * total of 64 requests are divided between peripherals. + * Base address of peripheral 0 is 0, base of peripheral 1 is 0 + + * periph0_num_of_read_requests and so on. + */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS(x) (0x60024 + (x) * 0x4) + +/* number of read requests */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * the in/out of urgent thresholds mark the number of write requests in the + * queue in which the peripherals priority is changed. + * The two thresholds should create hysteresis. + * The moving into urgent threshold must always be greater than the moving + * out of urgent threshold. + */ +#define QM_DMA_QM_DMA_CONFIG_U_THRESH(x) (0x60044 + (x) * 0x4) + +/* moving into urgent threshold */ +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_MASK 0x3f + +/* moving out ot urgent threshold */ +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The arbitration between the requests of the different peripherals is + * done in two stages: + * 1. + * Strict priority - chooses the peripherals with the highest priority + * among all perpherals who have a request pending. + * 2. + * Weighted Round-Robin between all peripherals with the same priority. + * This array of registers allow configuration of the priority of each + * peripheral (both rx and tx) in the following manner: + * There are 4 levels of priorities, when each bit in the register + * represents a different level of priority. + * One should assert the relevant bit according to the desired priority + * -For the lowest - 0001For the highest - 1000 + */ +#define QM_DMA_QM_DMA_CONFIG_PRI(x) (0x60064 + (x) * 0x4) + +/* priority of rx side (upload) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_MASK 0xf + +/* priority of tx side (download) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_SHIFT 4 +#define QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_MASK 0xf0 + + +/* + * Registers - is [ 0 => 7 ] + * + * Broadbus source address of the DMA peripherals. + * Register per peripheral (rx and tx). + * The source is used to determine the route address to the different + * peripherals. + */ +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE(x) (0x60084 + (x) * 0x4) + +/* bb source of rx side (upload) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_MASK 0x3f + +/* bb source of tx side (download) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The second phase of the arbitration between requests is weighted round + * robin between requests of peripherals with the same priority. + * This array of registers allow configurtion of the weight of each + * peripheral (rx and tx). + * The actual weight will be weight + 1, meaning configuration of 0 is + * actual weight of 1. + */ +#define QM_DMA_QM_DMA_CONFIG_WEIGHT(x) (0x600a4 + (x) * 0x4) + +/* weight of rx side (upload) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_MASK 0x7 + +/* weight of tx side (download) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_MASK 0x700 + + +/* + * Register + * + * Resets the pointers of the peripherals FIFOs within the DMA. + * Bit per peripheral side (rx and tx). + * For rx side resets the data and CD FIFOs. + * For tx side resets the read requests FIFO. + */ +#define QM_DMA_QM_DMA_CONFIG_PTRRST 0x600d0 + +/* + * vector in which each bit represents a peripheral. + * LSB represent RX peripherals and MSB represent TX peripherals. + * When asserted, the relevant FIFOS of the selected peripheral will be + * reset to zero +*/ +#define QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_MASK 0xffff + + +/* + * Register + * + * max number of on the fly read commands the DMA may issue to DDR before + * receiving any data. + */ +#define QM_DMA_QM_DMA_CONFIG_MAX_OTF 0x600d4 + +/* max on the fly */ +#define QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_MASK 0x3f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL 0x600d8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * debug bus select + */ +#define QM_DMA_QM_DMA_CONFIG_DBG_SEL 0x600e0 + +/* select */ +#define QM_DMA_QM_DMA_CONFIG_DBG_SEL_DBGSEL_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_DBG_SEL_DBGSEL_MASK 0x3 + + +/* + * Register - read-only + * + * Each peripheral is represented in a bit on the not empty vector. + * LSB is for rx peripherals, MSB for tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * not empty. + * The not empty vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define QM_DMA_QM_DMA_DEBUG_NEMPTY 0x60100 + +/* indication of the queue state */ +#define QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_MASK 0xffff + + +/* + * Register - read-only + * + * Each peripheral, a is represented in a bit on the urgent vector. + * 8 LSB are rx peripherlas, 8 MSB are tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * in urgent state. + * The urgent vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define QM_DMA_QM_DMA_DEBUG_URGNT 0x60104 + +/* indication whether the queue is in urgent state or not */ +#define QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_MASK 0xffff + + +/* + * Register - read-only + * + * The decision of the dma schedule rand the next peripheral to be served, + * represented by its source address + */ +#define QM_DMA_QM_DMA_DEBUG_SELSRC 0x60108 + +/* the next peripheral to be served by the dma */ +#define QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of write requests currently pending for each rx peripheral. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX(x) (0x60110 + (x) * 0x4) + +/* the number of pending write requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of read requestscurrently pending for each TX peripheral. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX(x) (0x60130 + (x) * 0x4) + +/* the number of pending read requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of write requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC(x) (0x60150 + (x) * 0x4) + +/* the number of pending write requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of read requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC(x) (0x60170 + (x) * 0x4) + +/* the number of pending write requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Register + * + * the address and cs of the ram the user wishes to read using the indirect + * access read mechanism. + */ +#define QM_DMA_QM_DMA_DEBUG_RDADD 0x60200 + +/* address within the ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_MASK 0x3ff + +/* chip select for write data ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_DATACS_MASK 0x10000 + +/* chip select for chunk descriptors ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_CDCS_MASK 0x20000 + +/* chip select for read requests ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_RRCS_MASK 0x40000 + + +/* + * Register + * + * After determining the address and cs, the user should assert this bit + * for indicating that the address and cs are valid. + */ +#define QM_DMA_QM_DMA_DEBUG_RDVALID 0x60204 + +/* indirect read request is valid */ +#define QM_DMA_QM_DMA_DEBUG_RDVALID_VALID_MASK 0x1 + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * The returned read data from the selected RAM. + * Array of 4 registers (128 bits total). + * The width of the different memories is as follows: + * write data - 128 bitschunk descriptors - 36 bitsread requests - 42 + * bitsread data - 64 bitsThe the memories with width smaller than 128, the + * data will appear in the first registers of the array, for example: + * data from the cd RAM will appear in - {reg1[5: + * 0], reg0[31: + * 0]}. + */ +#define QM_DMA_QM_DMA_DEBUG_RDDATA(x) (0x60208 + (x) * 0x4) + +/* read data from ram */ +#define QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * When assertd indicats that the data in the previous array is valid. + * Willremain asserted until the user deasserts the valid bit in regiser + * RDVALID. + */ +#define QM_DMA_QM_DMA_DEBUG_RDDATARDY 0x60218 + +/* read data ready */ +#define QM_DMA_QM_DMA_DEBUG_RDDATARDY_READY_MASK 0x1 + + +#endif /* ! XRDP_REGS_QM_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_rnr_quad.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_quad.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_rnr_quad.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_quad.h 2023-03-09 15:06:11.384234759 +0100 @@ -0,0 +1,1707 @@ +#ifndef XRDP_REGS_RNR_QUAD_H_ +#define XRDP_REGS_RNR_QUAD_H_ + +/* relative to core */ +#define RNR_QUAD_OFFSET_0 0xd08400 + +/* + * Register + * + * Engineering Configuration reserved for Broadlight use + */ +#define RNR_QUAD_PARSER_CORE_CFG_ENG 0x0 + +/* + * eng_cnfg[0] - IP filters on IPV6 on LSByte not MSByte + * eng_cnfg[1] - IP DAfields shows LSByte not MSbyte + * eng_cnfg[2] - enable error instead of brdcst at classifier summary word + * eng_cnfg[3] - Free + * eng_cnfg[8] - * Free + * eng_cnfg[9] - Free + * eng_cnfg[10] - Free + * eng_cnfg[11] - Free + * eng_cnfg[12] - Free + * eng_cnfg[13] - Free + * eng_cnfg[14] - mask of ah ext header excepetion + * eng_cnfg[15] - enable old mode of AH at IPV6 + * eng_cnfg[16] - enable old mode of AH at IPV4 + * eng_cnfg[17] - Free + * eng_cnfg[18] - dont allow 0xFFFF as valid ipv4 header cksum resultss +*/ +#define PARSER_CORE_CFG_ENG_CFG_SHIFT 0 +#define PARSER_CORE_CFG_ENG_CFG_MASK 0xffffffff + + +/* + * Register + * + * Parser Miscellaneous Configuration + */ +#define RNR_QUAD_PARSER_CORE_CFG_PARSER_MISC_CFG 0x4 + +/* + * Define which status bit cause exception bit in summary word to be set, + * the cuse vector is {4h0,ip fragment, ip version error, ip checksum + * error, ip_header length error} +*/ +#define PARSER_CORE_CFG_PARSER_MISC_CFG_EXCEPTION_EN_SHIFT 0 +#define PARSER_CORE_CFG_PARSER_MISC_CFG_EXCEPTION_EN_MASK 0x3fff + +/* + * Defines which TCP falgs set will cause TCP_FLAG bit in summary word to + * be set +*/ +#define PARSER_CORE_CFG_PARSER_MISC_CFG_TCP_FLAGS_FILT_SHIFT 16 +#define PARSER_CORE_CFG_PARSER_MISC_CFG_TCP_FLAGS_FILT_MASK 0xff0000 + +/* Profile US */ +#define PARSER_CORE_CFG_PARSER_MISC_CFG_PROFILE_US_SHIFT 28 +#define PARSER_CORE_CFG_PARSER_MISC_CFG_PROFILE_US_MASK 0x70000000 + + +/* + * Register + * + * Config VID Filter 0 & 1 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_0_1 0x8 + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_0_1_VID_0_SHIFT 0 +#define PARSER_CORE_CFG_VID_0_1_VID_0_MASK 0xfff + +/* VLAND ID Filter 0 Enable */ +#define PARSER_CORE_CFG_VID_0_1_VID_0_EN_MASK 0x8000 + +/* VLAN ID Filter 1 for second VLAN of register */ +#define PARSER_CORE_CFG_VID_0_1_VID_1_SHIFT 16 +#define PARSER_CORE_CFG_VID_0_1_VID_1_MASK 0xfff0000 + +/* VLAND ID Filter 1 Enable */ +#define PARSER_CORE_CFG_VID_0_1_VID_1_EN_MASK 0x80000000 + + +/* + * Register + * + * Config VID Filter 2 & 3 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_2_3 0xc + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_2_3_VID_2_SHIFT 0 +#define PARSER_CORE_CFG_VID_2_3_VID_2_MASK 0xfff + +/* VLAND ID Filter 2 Enable */ +#define PARSER_CORE_CFG_VID_2_3_VID_2_EN_MASK 0x8000 + +/* VLAN ID Filter 3 ofr second VLAN of register */ +#define PARSER_CORE_CFG_VID_2_3_VID_3_SHIFT 16 +#define PARSER_CORE_CFG_VID_2_3_VID_3_MASK 0xfff0000 + +/* VLAND ID Filter 3 Enable */ +#define PARSER_CORE_CFG_VID_2_3_VID_3_EN_MASK 0x80000000 + + +/* + * Register + * + * Config VID Filter 4 & 5 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_4_5 0x10 + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_4_5_VID_4_SHIFT 0 +#define PARSER_CORE_CFG_VID_4_5_VID_4_MASK 0xfff + +/* VLAND ID Filter 4 Enable */ +#define PARSER_CORE_CFG_VID_4_5_VID_4_EN_MASK 0x8000 + +/* VLAN ID Filter 5 ofr second VLAN of register */ +#define PARSER_CORE_CFG_VID_4_5_VID_5_SHIFT 16 +#define PARSER_CORE_CFG_VID_4_5_VID_5_MASK 0xfff0000 + +/* VLAND ID Filter 5 Enable */ +#define PARSER_CORE_CFG_VID_4_5_VID_5_EN_MASK 0x80000000 + + +/* + * Register + * + * Config VID Filter 6 & 7 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_6_7 0x14 + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_6_7_VID_6_SHIFT 0 +#define PARSER_CORE_CFG_VID_6_7_VID_6_MASK 0xfff + +/* VLAND ID Filter 6 Enable */ +#define PARSER_CORE_CFG_VID_6_7_VID_6_EN_MASK 0x8000 + +/* VLAN ID Filter 7 ofr second VLAN of register */ +#define PARSER_CORE_CFG_VID_6_7_VID_7_SHIFT 16 +#define PARSER_CORE_CFG_VID_6_7_VID_7_MASK 0xfff0000 + +/* VLAND ID Filter 7 Enable */ +#define PARSER_CORE_CFG_VID_6_7_VID_7_EN_MASK 0x80000000 + + +/* + * Register + * + * Config the IP Address filtering. + * Notice that the enable bit is located in the IP_FILTERS_CFG[4] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER0_CFG 0x18 + +/* + * 32-bit address to match SIP or DIP (according to predefined + * configuration in IP_FILTERS_CFG register) +*/ +#define PARSER_CORE_CFG_IP_FILTER0_CFG_IP_ADDRESS_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER0_CFG_IP_ADDRESS_MASK 0xffffffff + + +/* + * Register + * + * Config the IP Address filtering. + * Notice that the enable bit is located in the IP_FILTERS_CFG[5] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER1_CFG 0x1c + +/* + * 32-bit address to match SIP or DIP (according to predefined + * configuration in IP_FILTERS_CFG register) +*/ +#define PARSER_CORE_CFG_IP_FILTER1_CFG_IP_ADDRESS_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER1_CFG_IP_ADDRESS_MASK 0xffffffff + + +/* + * Register + * + * Config the IP Address masking. + * Notice that the enable bit is located in the IP_FILTERS_CFG[4] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER0_MASK_CFG 0x28 + +/* 32-bit address mask */ +#define PARSER_CORE_CFG_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_MASK 0xffffffff + + +/* + * Register + * + * Config the IP Address masking. + * Notice that the enable bit is located in the IP_FILTERS_CFG[5] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER1_MASK_CFG 0x2c + +/* 32-bit address mask */ +#define PARSER_CORE_CFG_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_MASK 0xffffffff + + +/* + * Register + * + * IP Address Filters (0. + * .3) configurations: + * (1) SIP or DIP selection config per each filter(1) Valid bit per each + * filter + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTERS_CFG 0x38 + +/* + * IP Filter0 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_MASK 0x1 + +/* + * IP Filter1 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_MASK 0x2 + +/* + * IP Filter2 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_MASK 0x4 + +/* + * IP Filter3 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_MASK 0x8 + +/* + * IP Filter0 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER0_VALID_MASK 0x10 + +/* + * IP Filter1 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER1_VALID_MASK 0x20 + +/* + * IP Filter2 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER2_VALID_MASK 0x40 + +/* + * IP Filter3 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER3_VALID_MASK 0x80 + + +/* + * Register + * + * Identifies SNAP tunneling organization code + */ +#define RNR_QUAD_PARSER_CORE_CFG_SNAP_ORG_CODE 0x3c + +/* Used defined SNAP organization code */ +#define PARSER_CORE_CFG_SNAP_ORG_CODE_CODE_SHIFT 0 +#define PARSER_CORE_CFG_SNAP_ORG_CODE_CODE_MASK 0xffffff + +/* enable RFC1042 0x00000 organization code */ +#define PARSER_CORE_CFG_SNAP_ORG_CODE_EN_RFC1042_MASK 0x1000000 + +/* + * enables 802. + * 1Q 0x0000f8 organization code +*/ +#define PARSER_CORE_CFG_SNAP_ORG_CODE_EN_8021Q_MASK 0x2000000 + + +/* + * Register + * + * PPP Protocol Code to indicate L3 is IP + */ +#define RNR_QUAD_PARSER_CORE_CFG_PPP_IP_PROT_CODE 0x40 + +/* PPP Protocol code to identify L3 is IP */ +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_0_SHIFT 0 +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_0_MASK 0xffff + +/* PPP Protocol code to identify L3 is IP */ +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_1_SHIFT 16 +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_1_MASK 0xffff0000 + + +/* + * Register + * + * Ethertype values to identify the presence of VLAN QTAG + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_ETHTYPE 0x44 + +/* Ethertype to identify VLAN QTAG */ +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_0_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_0_MASK 0xffff + +/* Ethertype to identify VLAN QTAG */ +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_1_SHIFT 16 +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_1_MASK 0xffff0000 + + +/* + * Register + * + * Configures user Ethertype values + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_ETHTYPE_0_1 0x48 + +/* User Ethertype 0 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_0_SHIFT 0 +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_0_MASK 0xffff + +/* User Ethertype 1 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_1_SHIFT 16 +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_1_MASK 0xffff0000 + + +/* + * Register + * + * Configures user Ethertype values + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_ETHTYPE_2_3 0x4c + +/* User Ethertype 2 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_2_SHIFT 0 +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_2_MASK 0xffff + +/* User Ethertype 3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_3_SHIFT 16 +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_3_MASK 0xffff0000 + + +/* + * Register + * + * Configure protocol and enables user Ethertype + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_ETHTYPE_CONFIG 0x50 + +/* Pointer to L3 protocol for User Ethertype 0 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_SHIFT 0 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_MASK 0x3 + +/* Pointer to L3 protocol for User Ethertype 1 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_SHIFT 2 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_MASK 0xc + +/* Pointer to L3 protocol for User Ethertype 2 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_SHIFT 4 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_MASK 0x30 + +/* Pointer to L3 protocol for User Ethertype 3 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_SHIFT 6 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_MASK 0xc0 + +/* Enable user Ethertype 3-0 (LSB is for user ethertype 0) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_SHIFT 8 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_MASK 0xf00 + +/* 4 byte offset for User Ethertype 0 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_SHIFT 16 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_MASK 0xf0000 + +/* 4 byte offset for User Ethertype 1 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_SHIFT 20 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_MASK 0xf00000 + +/* 4 byte offset for User Ethertype 2 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_SHIFT 24 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_MASK 0xf000000 + +/* 4 byte offset for User Ethertype 3 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_SHIFT 28 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_MASK 0xf0000000 + + +/* + * Register + * + * IPV6 Header Extension Filter Mask register + */ +#define RNR_QUAD_PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG 0x54 + +/* hop by hop match filter mask */ +#define PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_MASK 0x1 + +/* Routing extension header option match filter mask */ +#define PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_MASK 0x2 + +/* Destination Options extension header option match filter mask */ +#define PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_MASK 0x4 + + +/* + * Register + * + * Qtag Nesting config + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_NEST 0x58 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_0_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_0_MASK 0x7 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_1_SHIFT 3 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_1_MASK 0x38 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_2_SHIFT 6 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_2_MASK 0x1c0 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_0_SHIFT 9 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_0_MASK 0xe00 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_1_SHIFT 12 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_1_MASK 0x7000 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_2_SHIFT 15 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_2_MASK 0x38000 + + +/* + * Register + * + * QTAG Hard Nest Profile 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_HARD_NEST_0 0x5c + +/* + * bit 2-0: + * Enable 8100 as VLAN for outer, 2nd, and inner VLANs (inner is bit 2). + * bit 5-3: + * Enable 88a8 as VLAN for outer, 2nd, and inner VLANs. + * bit 8-6: + * Enable 9100 as VLAN for outer, 2nd, and inner VLANs. + * bit 11-9: + * Enable 9200 as VLAN for outer, 2nd, and inner VLANs. +*/ +#define PARSER_CORE_CFG_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_MASK 0xfff + + +/* + * Register + * + * QTAG Hard Nest Profile 1 + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_HARD_NEST_1 0x60 + +/* Hard Nest Profile */ +#define PARSER_CORE_CFG_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_MASK 0xfff + + +/* + * Register + * + * QTAG Hard Nest Profile 2 + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_HARD_NEST_2 0x64 + +/* Hard Nest Profile */ +#define PARSER_CORE_CFG_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_MASK 0xfff + + +/* + * Register + * + * IP Protocols to be matched to IP Protocol field and to be indicated in + * the output summary word + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_IP_PROT 0x68 + +/* User defined IP protocol 0 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_0_SHIFT 0 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_0_MASK 0xff + +/* User defined IP protocol 1 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_1_SHIFT 8 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_1_MASK 0xff00 + +/* User defined IP protocol 2 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_2_SHIFT 16 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_2_MASK 0xff0000 + +/* User defined IP protocol 3 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_3_SHIFT 24 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_3_MASK 0xff000000 + + +/* + * Register + * + * Config DA filter 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_VAL_L 0x70 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT0_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter0 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_VAL_H 0x74 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT0_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter1 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_VAL_L 0x78 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT1_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter1 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_VAL_H 0x7c + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT1_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter2 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT2_VAL_L 0x80 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT2_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT2_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter2 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT2_VAL_H 0x84 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT2_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT2_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter3 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT3_VAL_L 0x88 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT3_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT3_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter3 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT3_VAL_H 0x8c + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT3_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT3_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter4 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT4_VAL_L 0x90 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT4_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT4_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter4 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT4_VAL_H 0x94 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT4_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT4_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter5 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT5_VAL_L 0x98 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT5_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT5_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter5 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT5_VAL_H 0x9c + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT5_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT5_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter6 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT6_VAL_L 0xa0 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT6_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT6_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter6 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT6_VAL_H 0xa4 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT6_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT6_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter7 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT7_VAL_L 0xa8 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT7_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT7_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter7 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT7_VAL_H 0xac + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT7_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT7_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter8 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT8_VAL_L 0xb0 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT8_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT8_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter8 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT8_VAL_H 0xb4 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT8_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT8_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA Filter mask 15: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_MASK_L 0xc8 + +/* + * Current DA Filter mask bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT0_MASK_L_DA_FILT_MASK_L_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_MASK_L_DA_FILT_MASK_L_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter0 mask 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_MASK_H 0xcc + +/* + * Current DA Filter mask bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA Filter1 mask 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_MASK_L 0xd0 + +/* + * Current DA Filter mask bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT1_MASK_L_DA_FILT_MASK_L_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_MASK_L_DA_FILT_MASK_L_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter1 mask 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_MASK_H 0xd4 + +/* + * Current DA Filter mask bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_MASK 0xffff + + +/* + * Register + * + * Valid configuration of all DA filters: + * there is a dedicated bit per each DA filter that says if the current DA + * filter is valid or not. + * Used for on-the-fly DA filter value (mask) modifications, since the DA + * filter parameters are not assigned on single SW register. + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT_VALID_CFG_0 0xd8 + +/* DA Filter0 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_MASK 0x1 + +/* DA Filter1 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_MASK 0x2 + +/* DA Filter2 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_MASK 0x4 + +/* DA Filter3 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_MASK 0x8 + +/* DA Filter4 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_MASK 0x10 + +/* DA Filter5 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_MASK 0x20 + +/* DA Filter6 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_MASK 0x40 + +/* DA Filter7 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_MASK 0x80 + +/* DA Filter8 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_MASK 0x100 + + +/* + * Register + * + * Valid configuration of all DA filters: + * there is a dedicated bit per each DA filter that says if the current DA + * filter is valid or not. + * Used for on-the-fly DA filter value (mask) modifications, since the DA + * filter parameters are not assigned on single SW register. + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT_VALID_CFG_1 0xdc + +/* DA Filter0 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_MASK 0x1 + +/* DA Filter1 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_MASK 0x2 + +/* DA Filter2 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_MASK 0x4 + +/* DA Filter3 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_MASK 0x8 + +/* DA Filter4 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_MASK 0x10 + +/* DA Filter5 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_MASK 0x20 + +/* DA Filter6 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_MASK 0x40 + +/* DA Filter7 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_MASK 0x80 + +/* DA Filter8 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_MASK 0x100 + + +/* + * Register + * + * Valid configuration of all DA filters: + * there is a dedicated bit per each DA filter that says if the current DA + * filter is valid or not. + * Used for on-the-fly DA filter value (mask) modifications, since the DA + * filter parameters are not assigned on single SW register. + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT_VALID_CFG_2 0xe0 + +/* DA Filter0 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_MASK 0x1 + +/* DA Filter1 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_MASK 0x2 + +/* DA Filter2 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_MASK 0x4 + +/* DA Filter3 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_MASK 0x8 + +/* DA Filter4 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_MASK 0x10 + +/* DA Filter5 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_MASK 0x20 + +/* DA Filter6 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_MASK 0x40 + +/* DA Filter7 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_MASK 0x80 + +/* DA Filter8 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_MASK 0x100 + + +/* + * Register + * + * GRE Protocol + */ +#define RNR_QUAD_PARSER_CORE_CFG_GRE_PROTOCOL_CFG 0xe4 + +/* GRE_PROTOCOL */ +#define PARSER_CORE_CFG_GRE_PROTOCOL_CFG_GRE_PROTOCOL_SHIFT 0 +#define PARSER_CORE_CFG_GRE_PROTOCOL_CFG_GRE_PROTOCOL_MASK 0xffff + + +/* + * Register + * + * Prop Tag Configuration + */ +#define RNR_QUAD_PARSER_CORE_CFG_PROP_TAG_CFG 0xe8 + +/* profile 0 tag size, valid values are 0,2,4,6,8 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_0_SHIFT 0 +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_0_MASK 0x1f + +/* profile 1 tag size, valid values are 0,2,4,6,8 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_1_SHIFT 5 +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_1_MASK 0x3e0 + +/* profile 2 tag size, valid values are 0,2,4,6,8 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_2_SHIFT 10 +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_2_MASK 0x7c00 + +/* Pre-DA Profile 0 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_PRE_DA_DPROFILE_0_MASK 0x8000 + +/* Pre-DA Profile 1 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_PRE_DA_DPROFILE_1_MASK 0x10000 + +/* Pre-DA Profile 2 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_PRE_DA_DPROFILE_2_MASK 0x20000 + + +/* + * Register + * + * DMA arbiter Configuration + */ +#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG 0x100 + +/* Select whether to use DDR FIFO only for DDR accesses */ +#define GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_MASK 0x1 + +/* Scheduling policy for token arbiter */ +#define GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_MASK 0x2 + +/* + * chicken bit to disable external flow control. + * Packetw wil always be sent, no matter what token count says +*/ +#define GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_MASK 0x4 + +/* Set congestion threshold */ +#define GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_SHIFT 4 +#define GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_MASK 0x1f0 + + +/* + * Register + * + * Configure PSRAM0 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE 0x104 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM0_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM0_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM1 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE 0x108 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM1_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM1_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM2 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE 0x10c + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM2_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM2_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM3 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE 0x110 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM3_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM3_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR0 base + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE 0x114 + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR0_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR0_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR1 base + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE 0x118 + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR1_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR1_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM0 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK 0x11c + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM0_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM0_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM1 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK 0x120 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM1_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM1_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM2 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK 0x124 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM2_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM2_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM3 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK 0x128 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM3_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM3_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR0 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK 0x12c + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR0_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR0_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR1 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK 0x130 + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR1_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR1_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Profiling configuration + */ +#define RNR_QUAD_GENERAL_CONFIG_PROF_CONFIG 0x134 + +/* Select which 12-bits from 32-bit counter value to be recorded by tracer */ +#define GENERAL_CONFIG_PROF_CONFIG_COUNTER_LSB_SEL_SHIFT 0 +#define GENERAL_CONFIG_PROF_CONFIG_COUNTER_LSB_SEL_MASK 0x1f + +/* Enable tracing for core 0 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_0_MASK 0x100 + +/* Enable tracing for core 1 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_1_MASK 0x200 + +/* Enable tracing for core 2 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_2_MASK 0x400 + +/* Enable tracing for core 3 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_3_MASK 0x800 + +/* Enable tracing for core 4 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_4_MASK 0x1000 + +/* Enable tracing for core 5 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_5_MASK 0x2000 + + +/* + * Register + * + * Breakpoint 0 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG 0x140 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_0_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_0_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_0_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_0_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 1 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG 0x144 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_1_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_1_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_1_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_1_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 2 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG 0x148 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_2_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_2_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_2_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_2_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 3 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG 0x14c + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_3_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_3_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_3_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_3_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 4 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG 0x150 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_4_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_4_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_4_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_4_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 5 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG 0x154 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_5_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_5_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_5_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_5_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 6 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG 0x158 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_6_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_6_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_6_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_6_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 7 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG 0x15c + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_7_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_7_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_7_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_7_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint general configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG 0x160 + +/* Breakpoint handler routine address */ +#define GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_MASK 0x1fff + +/* New PC to be updated by breakpoint handler routine */ +#define GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_SHIFT 16 +#define GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_MASK 0x1fff0000 + + +/* + * Register + * + * Powersaving configuration + */ +#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG 0x170 + +/* + * Select how many clocks to wait in IDLE condition before enetrin + * powersave state +*/ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_SHIFT 0 +#define GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_MASK 0xff + +/* Enable powersavingfor core 0 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_MASK 0x100 + +/* Enable powersave for core 1 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_MASK 0x200 + +/* Enable powersave for core 2 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_MASK 0x400 + +/* Enable powersave for core 3 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_MASK 0x800 + +/* Enable powersave for core 4 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_MASK 0x1000 + +/* Enable powersave for core 5 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_MASK 0x2000 + + +/* + * Register - read-only + * + * Powersave status indications + */ +#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS 0x174 + +/* Core 0 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_MASK 0x1 + +/* Core 0 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_MASK 0x2 + +/* Core 2 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_MASK 0x4 + +/* Core 3 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_MASK 0x8 + +/* Core 4 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_4_STATUS_MASK 0x10 + +/* Core 5 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_5_STATUS_MASK 0x20 + + +/* + * Register + * + * FIFOs configuration + */ +#define RNR_QUAD_DEBUG_FIFO_CONFIG 0x200 + +/* Apply software reset to PSRAM header FIFO in EC arbiter */ +#define DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_MASK 0x1 + +/* Apply software reset to PSRAM data FIFO in EC arbiter */ +#define DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_MASK 0x2 + +/* Apply software reset to DDR header FIFO in EC arbiter */ +#define DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_MASK 0x4 + +/* Software read address for PSRAM header FIFO */ +#define DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_SHIFT 8 +#define DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_MASK 0xf00 + +/* Software read address for PSRAM data FIFO */ +#define DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_SHIFT 12 +#define DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_MASK 0xf000 + +/* Software read address for DDR header FIFO */ +#define DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_SHIFT 16 +#define DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_MASK 0xf0000 + + +/* + * Register - read-only + * + * PSRAM Header FIFO status + */ +#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS 0x204 + +/* FIFO full indication */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Push write counter value */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_SHIFT 4 +#define DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_MASK 0x1f0 + +/* Pop read counter value */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_SHIFT 12 +#define DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_MASK 0x1f000 + +/* Used words value */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_SHIFT 20 +#define DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_MASK 0x1f00000 + + +/* + * Register - read-only + * + * PSRAM Data FIFO status + */ +#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS 0x208 + +/* FIFO full indication */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Almost FIFO full indication */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_MASK 0x4 + +/* Push write counter value */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_SHIFT 4 +#define DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_MASK 0x1f0 + +/* Pop read counter value */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_SHIFT 12 +#define DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_MASK 0x1f000 + +/* Used words value */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_SHIFT 20 +#define DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_MASK 0x1f00000 + + +/* + * Register - read-only + * + * DDR Header FIFO status + */ +#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS 0x20c + +/* FIFO full indication */ +#define DEBUG_DDR_HDR_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Push write counter value */ +#define DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_SHIFT 4 +#define DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_MASK 0x1f0 + +/* Pop read counter value */ +#define DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_SHIFT 12 +#define DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_MASK 0x1f000 + +/* Used words value */ +#define DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_SHIFT 20 +#define DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_MASK 0x1f00000 + + +/* + * Register - read-only + * + * DDR Data FIFO status + */ +#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS 0x210 + +/* FIFO full indication */ +#define DEBUG_DDR_DATA_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Almost FIFO full indication */ +#define DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_MASK 0x4 + +/* rite counter value */ +#define DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_SHIFT 4 +#define DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_MASK 0x1ff0 + +/* Read counter value */ +#define DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_SHIFT 16 +#define DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_MASK 0x1ff0000 + + +/* + * Register - read-only + * + * DDR Data FIFO status 2 + */ +#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2 0x214 + +/* Current read address */ +#define DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_SHIFT 0 +#define DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_MASK 0xff + +/* Used words */ +#define DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_SHIFT 8 +#define DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_MASK 0x1ff00 + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1 0x220 + +/* Data */ +#define DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_SHIFT 0 +#define DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2 0x224 + +/* Data */ +#define DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_SHIFT 0 +#define DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1 0x228 + +/* Data */ +#define DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_SHIFT 0 +#define DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2 0x22c + +/* Data */ +#define DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_SHIFT 0 +#define DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1 0x230 + +/* Data */ +#define DEBUG_DDR_HDR_FIFO_DATA1_DATA_SHIFT 0 +#define DEBUG_DDR_HDR_FIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2 0x234 + +/* Data */ +#define DEBUG_DDR_HDR_FIFO_DATA2_DATA_SHIFT 0 +#define DEBUG_DDR_HDR_FIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 35 ] + * + * Token value for flow control + */ +#define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL(x) (0x400 + (x) * 0x4) + +/* Value */ +#define EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_SHIFT 0 +#define EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * Decode for PSRAM Queue + */ +#define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE(x) (0x600 + (x) * 0x4) + +/* Value */ +#define UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_SHIFT 0 +#define UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * Decode for DDR Queue + */ +#define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE(x) (0x640 + (x) * 0x4) + +/* Value */ +#define UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_SHIFT 0 +#define UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_RNR_QUAD_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_rnr_regs.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_regs.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_rnr_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_regs.h 2023-03-09 15:06:11.384234759 +0100 @@ -0,0 +1,570 @@ +#ifndef XRDP_REGS_RNR_REGS_H_ +#define XRDP_REGS_RNR_REGS_H_ + +/* relative to core */ +#define RNR_REGS_OFFSET_0 0xd00000 + +/* relative to core */ +#define RNR_REGS_OFFSET_1 0xd01000 + +/* relative to core */ +#define RNR_REGS_OFFSET_2 0xd02000 + +/* relative to core */ +#define RNR_REGS_OFFSET_3 0xd03000 + +/* relative to core */ +#define RNR_REGS_OFFSET_4 0xd04000 + +/* relative to core */ +#define RNR_REGS_OFFSET_5 0xd05000 + +/* + * Register + * + * Global control + */ +#define RNR_REGS_CFG_GLOBAL_CTRL 0x0 + +/* + * Runner enable. + * When reset runner pipe is halted, instruction memory and context memory + * can be accessed by the CPU. + * The CPU can reset or set this bitThe firmware can reset this bit by + * writing to the disable bit at the runner I/O control register. +*/ +#define CFG_GLOBAL_CTRL_EN_MASK 0x1 + +/* + * Notifies about DMA illegal access (>16 cycles on UBUS). + * Sticky bit. + * cleared by writing 1 to this bit. +*/ +#define CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_MASK 0x2 + +#define CFG_GLOBAL_CTRL_MICRO_SEC_VAL_SHIFT 8 +#define CFG_GLOBAL_CTRL_MICRO_SEC_VAL_MASK 0x3ff00 + +/* + * Register + * + * Writing to this register generates a request towards the runner + * scheduler. + */ +#define RNR_REGS_CFG_CPU_WAKEUP 0x4 + +/* The thread number to be invoked by the CPU. */ +#define CFG_CPU_WAKEUP_THREAD_NUM_SHIFT 0 +#define CFG_CPU_WAKEUP_THREAD_NUM_MASK 0xf + + +/* + * Register + * + * Interrupt control - UNUSED in 6858 + */ +#define RNR_REGS_CFG_INT_CTRL 0x8 + +/* + * While any of this field bits is set interrupt line 0 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT0_STS_SHIFT 0 +#define CFG_INT_CTRL_INT0_STS_MASK 0xff + +/* + * While any of this field bits is set interrupt line 0 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT1_STS_SHIFT 8 +#define CFG_INT_CTRL_INT1_STS_MASK 0xff00 + +/* + * While this bit is set interrupt line 2 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT2_STS_MASK 0x10000 + +/* + * While this bit is set interrupt line 3 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT3_STS_MASK 0x20000 + +/* + * While this bit is set interrupt line 4 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT4_STS_MASK 0x40000 + +/* + * While this bit is set interrupt line 5 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT5_STS_MASK 0x80000 + +/* + * While this bit is set interrupt line 6 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT6_STS_MASK 0x100000 + +/* + * While this bit is set interrupt line 6 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT7_STS_MASK 0x200000 + +/* + * While this bit is set interrupt line 8 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT8_STS_MASK 0x400000 + +/* + * While this bit is set interrupt line 9 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT9_STS_MASK 0x800000 + +#define CFG_INT_CTRL_FIT_FAIL_STS_MASK 0x80000000 + +/* + * Register + * + * Interrupt mask - UNUSED in 6858 + */ +#define RNR_REGS_CFG_INT_MASK 0xc + +/* Mask INT0 causes */ +#define CFG_INT_MASK_INT0_MASK_SHIFT 0 +#define CFG_INT_MASK_INT0_MASK_MASK 0xff + +/* INT1 mask cause */ +#define CFG_INT_MASK_INT1_MASK_SHIFT 8 +#define CFG_INT_MASK_INT1_MASK_MASK 0xff00 + +/* INT2 mask cause */ +#define CFG_INT_MASK_INT2_MASK_MASK 0x10000 + +/* INT3 mask cause */ +#define CFG_INT_MASK_INT3_MASK_MASK 0x20000 + +/* INT4 mask cause */ +#define CFG_INT_MASK_INT4_MASK_MASK 0x40000 + +/* INT5 mask cause */ +#define CFG_INT_MASK_INT5_MASK_MASK 0x80000 + +/* INT6 mask cause */ +#define CFG_INT_MASK_INT6_MASK_MASK 0x100000 + +/* INT7 mask cause */ +#define CFG_INT_MASK_INT7_MASK_MASK 0x200000 + +/* INT8 mask cause */ +#define CFG_INT_MASK_INT8_MASK_MASK 0x400000 + +/* INT9 mask cause */ +#define CFG_INT_MASK_INT9_MASK_MASK 0x800000 + + +/* + * Register + * + * General configuration + */ +#define RNR_REGS_CFG_GEN_CFG 0x30 + +/* + * Disable DMA old flow control. + * When set to 1, DMA will not check read FIFO occupancy when issuing READ + * requests, relying instead on DMA backpressure mechanism vs read + * dispatcher block. +*/ +#define CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_MASK 0x1 + +/* set to 1 to test fit fail interrupt. */ +#define CFG_GEN_CFG_TEST_FIT_FAIL_MASK 0x2 + + +/* + * Register + * + * CAM configuration + */ +#define RNR_REGS_CFG_CAM_CFG 0x34 + +/* + * CAM operation is stopped when reaching an entry with a value matching + * this field. + * For a 32-bit or 64-bit CAM entries, this value is concatenated. +*/ +#define CFG_CAM_CFG_STOP_VALUE_SHIFT 0 +#define CFG_CAM_CFG_STOP_VALUE_MASK 0xffff + + +/* + * Register + * + * DMA DDR config Register. + * Contains configurations such as buffer size and ddr base address that + * are used for DDR address calculations (from buffer number) when DMA + * instruction addr_calc flag is set. + */ +#define RNR_REGS_CFG_DDR_CFG 0x40 + +/* DMA base address for ADDR_CALC */ +#define CFG_DDR_CFG_DMA_BASE_SHIFT 0 +#define CFG_DDR_CFG_DMA_BASE_MASK 0xfffff + +/* 3 bits indicating buffer size */ +#define CFG_DDR_CFG_DMA_BUF_SIZE_SHIFT 20 +#define CFG_DDR_CFG_DMA_BUF_SIZE_MASK 0x700000 + +/* DMA static offset */ +#define CFG_DDR_CFG_DMA_STATIC_OFFSET_SHIFT 24 +#define CFG_DDR_CFG_DMA_STATIC_OFFSET_MASK 0xff000000 + + +/* + * Register + * + * DMA PSRAM config Register. + * Contains configurations such as buffer size and ddr base address that + * are used for DDR address calculations (from buffer number) when DMA + * instruction addr_calc flag is set. + */ +#define RNR_REGS_CFG_PSRAM_CFG 0x44 + +/* DMA base address for ADDR_CALC */ +#define CFG_PSRAM_CFG_DMA_BASE_SHIFT 0 +#define CFG_PSRAM_CFG_DMA_BASE_MASK 0xfffff + +/* 3 bits indicating buffer size */ +#define CFG_PSRAM_CFG_DMA_BUF_SIZE_SHIFT 20 +#define CFG_PSRAM_CFG_DMA_BUF_SIZE_MASK 0x700000 + +/* DMA static offset */ +#define CFG_PSRAM_CFG_DMA_STATIC_OFFSET_SHIFT 24 +#define CFG_PSRAM_CFG_DMA_STATIC_OFFSET_MASK 0xff000000 + + +/* + * Register + * + * Ramrd mask for range search. + * The register holds 2 mask that can be chosen by runner core for range + * seraches. + */ +#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG 0x48 + +/* + * Mask 0 for range serach. + * according to the number of 1 in the mask the cam machine can differ + * between the Key and TAG +*/ +#define CFG_RAMRD_RANGE_MASK_CFG_MASK0_SHIFT 0 +#define CFG_RAMRD_RANGE_MASK_CFG_MASK0_MASK 0xffff + +/* + * Mask 0 for range serach. + * according to the number of 1 in the mask the cam machine can differ + * between the Key and TAG +*/ +#define CFG_RAMRD_RANGE_MASK_CFG_MASK1_SHIFT 16 +#define CFG_RAMRD_RANGE_MASK_CFG_MASK1_MASK 0xffff0000 + + +/* + * Register + * + * scheduler configuration + */ +#define RNR_REGS_CFG_SCH_CFG 0x4c + +/* Configure priority mode for scheduler operation */ +#define CFG_SCH_CFG_SCHEDULER_MODE_SHIFT 0 +#define CFG_SCH_CFG_SCHEDULER_MODE_MASK 0x7 + + +/* + * Register + * + * breakpoint configuration + */ +#define RNR_REGS_CFG_BKPT_CFG 0x50 + +/* Enable breakpoint 0 */ +#define CFG_BKPT_CFG_BKPT_0_EN_MASK 0x1 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_0_USE_THREAD_MASK 0x2 + +/* Enable breakpoint 1 */ +#define CFG_BKPT_CFG_BKPT_1_EN_MASK 0x4 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_1_USE_THREAD_MASK 0x8 + +/* Enable breakpoint 2 */ +#define CFG_BKPT_CFG_BKPT_2_EN_MASK 0x10 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_2_USE_THREAD_MASK 0x20 + +/* Enable breakpoint 3 */ +#define CFG_BKPT_CFG_BKPT_3_EN_MASK 0x40 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_3_USE_THREAD_MASK 0x80 + +/* Enable breakpoint 4 */ +#define CFG_BKPT_CFG_BKPT_4_EN_MASK 0x100 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_4_USE_THREAD_MASK 0x200 + +/* Enable breakpoint 5 */ +#define CFG_BKPT_CFG_BKPT_5_EN_MASK 0x400 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_5_USE_THREAD_MASK 0x800 + +/* Enable breakpoint 6 */ +#define CFG_BKPT_CFG_BKPT_6_EN_MASK 0x1000 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_6_USE_THREAD_MASK 0x2000 + +/* Enable breakpoint 7 */ +#define CFG_BKPT_CFG_BKPT_7_EN_MASK 0x4000 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_7_USE_THREAD_MASK 0x8000 + +/* Configure step mode */ +#define CFG_BKPT_CFG_STEP_MODE_MASK 0x10000 + +/* Value for new flags */ +#define CFG_BKPT_CFG_NEW_FLAGS_VAL_SHIFT 20 +#define CFG_BKPT_CFG_NEW_FLAGS_VAL_MASK 0xf00000 + + +/* + * Register + * + * break point immediate + */ +#define RNR_REGS_CFG_BKPT_IMM 0x54 + +/* Enable immediate breakpoint */ +#define CFG_BKPT_IMM_ENABLE_MASK 0x1 + + +/* + * Register - read-only + * + * breakpoint status + */ +#define RNR_REGS_CFG_BKPT_STS 0x58 + +/* Breakpoint address */ +#define CFG_BKPT_STS_BKPT_ADDR_SHIFT 0 +#define CFG_BKPT_STS_BKPT_ADDR_MASK 0x1fff + +/* Breakpoint active indication */ +#define CFG_BKPT_STS_ACTIVE_MASK 0x10000 + + +/* + * Register - read-only + * + * Program counterstatus + */ +#define RNR_REGS_CFG_PC_STS 0x5c + +/* Current program counter address */ +#define CFG_PC_STS_CURRENT_PC_ADDR_SHIFT 0 +#define CFG_PC_STS_CURRENT_PC_ADDR_MASK 0x1fff + +/* Call stack return address */ +#define CFG_PC_STS_PC_RET_SHIFT 16 +#define CFG_PC_STS_PC_RET_MASK 0x1fff0000 + + +/* + * Register - read-only + * + * profiling status + */ +#define RNR_REGS_CFG_PROF_STS 0xb0 + +/* Trace write pointer */ +#define CFG_PROF_STS_TRACE_WRITE_PNT_SHIFT 0 +#define CFG_PROF_STS_TRACE_WRITE_PNT_MASK 0x1fff + +/* No active task */ +#define CFG_PROF_STS_IDLE_NO_ACTIVE_TASK_MASK 0x2000 + +/* Current thread num */ +#define CFG_PROF_STS_CURR_THREAD_NUM_SHIFT 14 +#define CFG_PROF_STS_CURR_THREAD_NUM_MASK 0x3c000 + +/* Status of profiling ON/OFF */ +#define CFG_PROF_STS_PROFILING_ACTIVE_MASK 0x40000 + +/* + * Sticky bit, indicating trace event FIFO overrun. + * Cleared by writing bit [31] of PROFILING_CFG_1 register +*/ +#define CFG_PROF_STS_TRACE_FIFO_OVERRUN_MASK 0x80000 + + +/* + * Register + * + * profiling confuguration 0 + */ +#define RNR_REGS_CFG_PROF_CFG_0 0xb4 + +/* Base address for trace buffer */ +#define CFG_PROF_CFG_0_TRACE_BASE_ADDR_SHIFT 0 +#define CFG_PROF_CFG_0_TRACE_BASE_ADDR_MASK 0x1fff + +/* Trace buffer MAX address */ +#define CFG_PROF_CFG_0_TRACE_MAX_ADDR_SHIFT 16 +#define CFG_PROF_CFG_0_TRACE_MAX_ADDR_MASK 0x1fff0000 + + +/* + * Register + * + * profiling confuguration 1 + */ +#define RNR_REGS_CFG_PROF_CFG_1 0xb8 + +/* Wraparound when writing trace buffer */ +#define CFG_PROF_CFG_1_TRACE_WRAPAROUND_MASK 0x1 + +/* Select all tasks or single task mode */ +#define CFG_PROF_CFG_1_TRACE_MODE_MASK 0x2 + +/* Select whether to log IDLE in context swap events */ +#define CFG_PROF_CFG_1_TRACE_DISABLE_IDLE_IN_MASK 0x4 + +/* + * Enable/disable logging of scheduler events (wakeups). + * Relevant only for single task mode +*/ +#define CFG_PROF_CFG_1_TRACE_DISABLE_WAKEUP_LOG_MASK 0x8 + +/* Select task for single task operation */ +#define CFG_PROF_CFG_1_TRACE_TASK_SHIFT 4 +#define CFG_PROF_CFG_1_TRACE_TASK_MASK 0xf0 + +/* Select mode for IDLE counter */ +#define CFG_PROF_CFG_1_IDLE_COUNTER_SOURCE_SEL_MASK 0x100 + +/* Apply software reset to event FIFO */ +#define CFG_PROF_CFG_1_TRACE_RESET_EVENT_FIFO_MASK 0x40000000 + +/* Write 1 to clear event FIFO overrun sticky bit */ +#define CFG_PROF_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_MASK 0x80000000 + + +/* + * Register - read-only + * + * Display profiling counter value + */ +#define RNR_REGS_CFG_PROF_COUNTER 0xbc + +/* Current 32-bit value of counter */ +#define CFG_PROF_COUNTER_VAL_SHIFT 0 +#define CFG_PROF_COUNTER_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * stall count + */ +#define RNR_REGS_CFG_STALL_CNT1 0xc0 + +/* Count load stalls */ +#define CFG_STALL_CNT1_LD_STALL_CNT_SHIFT 0 +#define CFG_STALL_CNT1_LD_STALL_CNT_MASK 0xffff + +/* Count accelerator stalls */ +#define CFG_STALL_CNT1_ACC_STALL_CNT_SHIFT 16 +#define CFG_STALL_CNT1_ACC_STALL_CNT_MASK 0xffff0000 + + +/* + * Register - read-only + * + * stall count + */ +#define RNR_REGS_CFG_STALL_CNT2 0xc4 + +/* Count load io stalls */ +#define CFG_STALL_CNT2_LDIO_STALL_CNT_SHIFT 0 +#define CFG_STALL_CNT2_LDIO_STALL_CNT_MASK 0xffff + +/* Count store stalls */ +#define CFG_STALL_CNT2_STORE_STALL_CNT_SHIFT 16 +#define CFG_STALL_CNT2_STORE_STALL_CNT_MASK 0xffff0000 + + +/* + * Register - read-only + * + * idle count + */ +#define RNR_REGS_CFG_IDLE_CNT1 0xc8 + +/* IDLE countReserved */ +#define CFG_IDLE_CNT1_IDLE_CNT_SHIFT 0 +#define CFG_IDLE_CNT1_IDLE_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Mispredicted jumps count + */ +#define RNR_REGS_CFG_JMP_CNT 0xcc + +/* Counts jumps with prediction miss, when prediction was dont jump */ +#define CFG_JMP_CNT_UNTAKEN_JMP_CNT_SHIFT 0 +#define CFG_JMP_CNT_UNTAKEN_JMP_CNT_MASK 0xffff + +/* Counts jumps with prediction miss, when prediction was jump */ +#define CFG_JMP_CNT_TAKEN_JMP_CNT_SHIFT 16 +#define CFG_JMP_CNT_TAKEN_JMP_CNT_MASK 0xffff0000 + + +/* + * Register + * + * 32 bit register for metal fixes. + */ +#define RNR_REGS_CFG_METAL_FIX_REG 0xf0 + +/* 32 bit register for metal fix */ +#define CFG_METAL_FIX_REG_METAL_FIX_SHIFT 0 +#define CFG_METAL_FIX_REG_METAL_FIX_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_RNR_REGS_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_sbpm.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_sbpm.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_sbpm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_sbpm.h 2023-03-09 15:06:11.384234759 +0100 @@ -0,0 +1,1204 @@ +#ifndef XRDP_REGS_SBPM_H_ +#define XRDP_REGS_SBPM_H_ + +/* relative to core */ +#define SBPM_OFFSET_0 0xd98000 + +/* + * Register + * + * request for building the free list using HW accelerator + */ +#define SBPM_REGS_INIT_FREE_LIST 0x0 + +/* init_base_addr */ +#define REGS_INIT_FREE_LIST_INIT_BASE_ADDR_SHIFT 0 +#define REGS_INIT_FREE_LIST_INIT_BASE_ADDR_MASK 0x3fff + +/* init_offset */ +#define REGS_INIT_FREE_LIST_INIT_OFFSET_SHIFT 14 +#define REGS_INIT_FREE_LIST_INIT_OFFSET_MASK 0xfffc000 + +/* + * The bit is used as busy indication of buffer allocation request status + * (busy status) by CPU. + * BPM asserts this bit on each valid request and de-asserts when request + * is treated. +*/ +#define REGS_INIT_FREE_LIST_BSY_MASK 0x40000000 + +/* + * The bit is used as ready indication of buffer allocation request status + * (ready status) by CPU. + * BPM asserts this bit when request is treated and de-asserts when new + * valid request is accepted, thus this is READY indication +*/ +#define REGS_INIT_FREE_LIST_RDY_MASK 0x80000000 + + +/* + * Register + * + * request for a new buffer + */ +#define SBPM_REGS_BN_ALLOC 0x4 + +/* + * Source address used by Alloc BN command (may be used for alloc on behalf + * another user) +*/ +#define REGS_BN_ALLOC_SA_SHIFT 14 +#define REGS_BN_ALLOC_SA_MASK 0xfc000 + + +/* + * Register - read-only + * + * reply for a new buffer alloc + */ +#define SBPM_REGS_BN_ALLOC_RPLY 0x8 + +/* alloc_bn_valid */ +#define REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_MASK 0x1 + +/* alloc_bn */ +#define REGS_BN_ALLOC_RPLY_ALLOC_BN_SHIFT 1 +#define REGS_BN_ALLOC_RPLY_ALLOC_BN_MASK 0x7ffe + +/* ack */ +#define REGS_BN_ALLOC_RPLY_ACK_MASK 0x8000 + +/* nack */ +#define REGS_BN_ALLOC_RPLY_NACK_MASK 0x10000 + +/* + * Exclusive bit is indication of Exclusive_high status of client with + * related Alloc request +*/ +#define REGS_BN_ALLOC_RPLY_EXCL_HIGH_MASK 0x20000 + +/* + * Exclusive bit is indication of Exclusive_low status of client with + * related Alloc request +*/ +#define REGS_BN_ALLOC_RPLY_EXCL_LOW_MASK 0x40000 + +/* busy */ +#define REGS_BN_ALLOC_RPLY_BUSY_MASK 0x40000000 + +/* rdy */ +#define REGS_BN_ALLOC_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * Request for freeing buffers of a packet offline with context (lower + * 32-bit) + */ +#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW 0xc + +/* head_bn */ +#define REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_SHIFT 0 +#define REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_MASK 0x3fff + +/* + * Source addres used for free comand (may be used for freeing BN on behalf + * another port) +*/ +#define REGS_BN_FREE_WITH_CONTXT_LOW_SA_SHIFT 14 +#define REGS_BN_FREE_WITH_CONTXT_LOW_SA_MASK 0xfc000 + +/* Offset (or length) = number of BNs in packet that is going to be freed */ +#define REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_SHIFT 24 +#define REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_MASK 0x7f000000 + +/* Ack request */ +#define REGS_BN_FREE_WITH_CONTXT_LOW_ACK_MASK 0x80000000 + + +/* + * Register + * + * Request for freeing buffers of a packet offline with context (higher + * 32-bit) + */ +#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH 0x10 + +/* Last BN in packet that is going to be freed */ +#define REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_SHIFT 0 +#define REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_MASK 0x3fff + + +/* + * Register + * + * Multicast counter increment. + * Contains the BN, which is head of the packet to be multicast and its + * counter value + */ +#define SBPM_REGS_MCST_INC 0x14 + +/* bufer number */ +#define REGS_MCST_INC_BN_SHIFT 0 +#define REGS_MCST_INC_BN_MASK 0x3fff + +/* MCST value that should be added to current mulicast counter */ +#define REGS_MCST_INC_MCST_VAL_SHIFT 14 +#define REGS_MCST_INC_MCST_VAL_MASK 0x3fc000 + +/* Acknowledge request */ +#define REGS_MCST_INC_ACK_REQ_MASK 0x400000 + + +/* + * Register - read-only + * + * mcst_inc_rply + */ +#define SBPM_REGS_MCST_INC_RPLY 0x18 + +/* Acknowledge reply of MCST command */ +#define REGS_MCST_INC_RPLY_MCST_ACK_MASK 0x1 + +/* + * The bit is used as busy indication of MCST request status (busy status) + * by CPUSBPM asserts this bit on each valid request and de-asserts when + * request is treated: + * 1 - request is busy,0- request is not busy (ready) +*/ +#define REGS_MCST_INC_RPLY_BSY_MASK 0x40000000 + +/* + * The bit is used as ready indication of MCST request status (ready + * status) by CPU. + * SBPM asserts this bit when request is treated and de-asserts when new + * valid request is accepted, thus this is READY indication: + * 1 - request is ready,0- request is not ready (busy) +*/ +#define REGS_MCST_INC_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * request for connection between two buffers in a linked list. + * The connection request may be replied with ACK message if the ACK + * request bit is asserted. + * This command is used as write command. + */ +#define SBPM_REGS_BN_CONNECT 0x1c + +/* bn */ +#define REGS_BN_CONNECT_BN_SHIFT 0 +#define REGS_BN_CONNECT_BN_MASK 0x3fff + +/* ack_req for Connect command (should be always set) */ +#define REGS_BN_CONNECT_ACK_REQ_MASK 0x4000 + +/* Used for Direct Write (for work arround) */ +#define REGS_BN_CONNECT_WR_REQ_MASK 0x8000 + +/* pointed_bn */ +#define REGS_BN_CONNECT_POINTED_BN_SHIFT 16 +#define REGS_BN_CONNECT_POINTED_BN_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * bn_connect_rply + */ +#define SBPM_REGS_BN_CONNECT_RPLY 0x20 + +/* Acknowledge reply on Connect request */ +#define REGS_BN_CONNECT_RPLY_CONNECT_ACK_MASK 0x1 + +/* busy bit */ +#define REGS_BN_CONNECT_RPLY_BUSY_MASK 0x40000000 + +/* ready bit */ +#define REGS_BN_CONNECT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * a pointer to a buffer in a packet linked list and request for the next + * buffer in the listthis command is used as read command. + */ +#define SBPM_REGS_GET_NEXT 0x24 + +/* Get Next Buffer of current BN (used in this field) */ +#define REGS_GET_NEXT_BN_SHIFT 0 +#define REGS_GET_NEXT_BN_MASK 0x3fff + + +/* + * Register - read-only + * + * get_next_rply + */ +#define SBPM_REGS_GET_NEXT_RPLY 0x28 + +/* Used for validation of Next BN reply */ +#define REGS_GET_NEXT_RPLY_BN_VALID_MASK 0x1 + +/* Next BN - reply of Get_next command */ +#define REGS_GET_NEXT_RPLY_NEXT_BN_SHIFT 1 +#define REGS_GET_NEXT_RPLY_NEXT_BN_MASK 0x7ffe + +/* Next BN is null indication */ +#define REGS_GET_NEXT_RPLY_BN_NULL_MASK 0x8000 + +/* mcst cnt val */ +#define REGS_GET_NEXT_RPLY_MCNT_VAL_SHIFT 16 +#define REGS_GET_NEXT_RPLY_MCNT_VAL_MASK 0xff0000 + +/* Get Next command is busy */ +#define REGS_GET_NEXT_RPLY_BUSY_MASK 0x40000000 + +/* Get Next command is ready */ +#define REGS_GET_NEXT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * control for the bl_clk_control module + */ +#define SBPM_REGS_SBPM_CLK_GATE_CNTRL 0x2c + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_SHIFT 20 +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * bn_free_without_contxt + */ +#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT 0x38 + +/* Head BN = First BN in packet that is going to be freed */ +#define REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_SHIFT 0 +#define REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_MASK 0x3fff + +/* + * source address used for command (may be used for performing command on + * behalf another port) +*/ +#define REGS_BN_FREE_WITHOUT_CONTXT_SA_SHIFT 14 +#define REGS_BN_FREE_WITHOUT_CONTXT_SA_MASK 0xfc000 + +/* ACK request - should be always set */ +#define REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_MASK 0x80000000 + + +/* + * Register - read-only + * + * bn_free_without_contxt_rply + */ +#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY 0x3c + +/* Acknowledge on Free command */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_MASK 0x1 + +/* ACK status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_MASK 0x8000 + +/* NACK status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_MASK 0x10000 + +/* Exclusive_high status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_MASK 0x20000 + +/* Exclusive_low status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_MASK 0x40000 + +/* Busy bit of command (command is currently in execution) */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_MASK 0x40000000 + +/* Ready bit of command (ready for new command execution) */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register - read-only + * + * bn_free_with_contxt_rply + */ +#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY 0x40 + +/* Free command acknowledge */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_MASK 0x1 + +/* ACK status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_MASK 0x8000 + +/* NACK status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_MASK 0x10000 + +/* Exclusive high status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_MASK 0x20000 + +/* Exclusive low status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_MASK 0x40000 + +/* Busy bit of command */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_MASK 0x40000000 + +/* Ready bit of command */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * Global Threshold for Allocated Buffers. + * SBPM will issue BN in the accepted range upon to Global threshold setup. + * Ths register also holds global hysteresis value for ACK/NACK transition + * setting. + * We cross to Nack state if BAC equals the threshold. + * We cross down to Ack if BAC equals the thrshold minus the histeresis + * value. + */ +#define SBPM_REGS_SBPM_GL_TRSH 0x4c + +/* Global Threshold for Allocated BN = maximal total number of BNs in SBPM */ +#define REGS_SBPM_GL_TRSH_GL_BAT_SHIFT 0 +#define REGS_SBPM_GL_TRSH_GL_BAT_MASK 0x3fff + +/* + * Global Hysteresis for Allocated BN = hysteresis value related to maximal + * total threshold of SRAM BNs +*/ +#define REGS_SBPM_GL_TRSH_GL_BAH_SHIFT 16 +#define REGS_SBPM_GL_TRSH_GL_BAH_MASK 0x3fff0000 + + +/* + * Register + * + * Threshold for Allocated Buffers of UG0Ths register also holds UG0 + * hysteresis value for ACK/NACK transition setting. + * We cross to Nack state if BAC equals the threshold. + * We cross down to Ack if BAC equals the thrshold minus the histeresis + * value. + */ +#define SBPM_REGS_SBPM_UG0_TRSH 0x50 + +/* Current UG Threshold for Allocated BN */ +#define REGS_SBPM_UG0_TRSH_UG_BAT_SHIFT 0 +#define REGS_SBPM_UG0_TRSH_UG_BAT_MASK 0x3fff + +/* Current UG hysteresis Threshold for Allocated BN */ +#define REGS_SBPM_UG0_TRSH_UG_BAH_SHIFT 16 +#define REGS_SBPM_UG0_TRSH_UG_BAH_MASK 0x3fff0000 + + +/* + * Register + * + * Threshold for Allocated Buffers of UG1Ths register also holds UG1 + * hysteresis value for ACK/NACK transition setting. + * We cross to Nack state if BAC equals the threshold. + * We cross down to Ack if BAC equals the thrshold minus the histeresis + * value. + */ +#define SBPM_REGS_SBPM_UG1_TRSH 0x54 + +/* Current UG Threshold for Allocated BN */ +#define REGS_SBPM_UG1_TRSH_UG_BAT_SHIFT 0 +#define REGS_SBPM_UG1_TRSH_UG_BAT_MASK 0x3fff + +/* Current UG hysteresis delta Threshold for Allocated BN */ +#define REGS_SBPM_UG1_TRSH_UG_BAH_SHIFT 16 +#define REGS_SBPM_UG1_TRSH_UG_BAH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM select the debug bus + */ +#define SBPM_REGS_SBPM_DBG 0x74 + +/* + * select bus. + * the bus index should be mentioned in onehot writting: + * bus0 = 0001bus1 = 0010bus2 = 0100bus3 = 1000 +*/ +#define REGS_SBPM_DBG_SELECT_BUS_SHIFT 0 +#define REGS_SBPM_DBG_SELECT_BUS_MASK 0xf + + +/* + * Register - read-only + * + * SBPM UG0 allocated BN counter + */ +#define SBPM_REGS_SBPM_UG0_BAC 0x78 + +/* UG0 counter for allocated BNs */ +#define REGS_SBPM_UG0_BAC_UG0BAC_SHIFT 0 +#define REGS_SBPM_UG0_BAC_UG0BAC_MASK 0x3fff + + +/* + * Register - read-only + * + * SBPM UG1 allocated BN Counter + */ +#define SBPM_REGS_SBPM_UG1_BAC 0x7c + +/* Baffer Allocated Counter */ +#define REGS_SBPM_UG1_BAC_UG1BAC_SHIFT 0 +#define REGS_SBPM_UG1_BAC_UG1BAC_MASK 0x3fff + + +/* + * Register - read-only + * + * SBPM global BN Counter + */ +#define SBPM_REGS_SBPM_GL_BAC 0x98 + +/* Global BN counter */ +#define REGS_SBPM_GL_BAC_BAC_SHIFT 0 +#define REGS_SBPM_GL_BAC_BAC_MASK 0x3fff + + +/* + * Register + * + * SBPM UG0 Exclusive high and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH 0x9c + +/* exclusive high threshold */ +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM UG1 Exclusive high and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH 0x100 + +/* exclusive high threshold */ +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM UG0 Exclusive low and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH 0x104 + +/* exclusive low threshold */ +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM UG1 Exclusive low and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH 0x108 + +/* exclusive low threshold */ +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * This register is status set of all 8 Ugs: + * Ack/NACK state and in addition Exclusive state pereach of 8 UGs + */ +#define SBPM_REGS_SBPM_UG_STATUS 0x11c + +/* + * Ack/Nack status per UG. + * 0 - NACK1 - ACKbit [0] in field matches UG0 ACK status,bit [1] in field + * matches UG1 ACK status,bit [2] in field matches UG2 ACK status,bit [3] + * in field matches UG3 ACK status,bit [4] in field matches UG4 ACK + * status,bit [5] in field matches UG5 ACK status,bit [6] in field matches + * UG6 ACK status,bit [7] in field matches UG7 ACK status, +*/ +#define REGS_SBPM_UG_STATUS_UG_ACK_STTS_SHIFT 0 +#define REGS_SBPM_UG_STATUS_UG_ACK_STTS_MASK 0x3 + +/* + * High EXCL/Non-Excl status per UG. + * 0 - non_exclusive1 - exclusive +*/ +#define REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_SHIFT 16 +#define REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_MASK 0x30000 + +/* + * Low EXCL/Non-Excl status per UG. + * 0 - non_exclusive1 - exclusive +*/ +#define REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_SHIFT 18 +#define REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_MASK 0xc0000 + + +/* + * Register + * + * Parameters and thresholds used for Error handling: + * error detection, max search enable and threshold, etc. + */ +#define SBPM_REGS_ERROR_HANDLING_PARAMS 0x138 + +/* Depth (or maximal threshold) for search during Free without context */ +#define REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_SHIFT 0 +#define REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_MASK 0x7f + +/* Enable for max search during Free without context */ +#define REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_MASK 0x80 + +/* Enable for Last BN checking during Free with context */ +#define REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_MASK 0x100 + +/* Freeze Ug/Global counters + mask access to SBPM RAM while in ERROR state */ +#define REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_MASK 0x200 + + +/* + * Register - read-only + * + * SBPM IIR low (Interrupt information register) + */ +#define SBPM_REGS_SBPM_IIR_LOW 0x148 + +/* Interrupt command source address (latched from BB SA or CPU code) */ +#define REGS_SBPM_IIR_LOW_CMD_SA_SHIFT 0 +#define REGS_SBPM_IIR_LOW_CMD_SA_MASK 0x3f + +/* Interrupt command target address (latched from BB TA or CPU request) */ +#define REGS_SBPM_IIR_LOW_CMD_TA_SHIFT 6 +#define REGS_SBPM_IIR_LOW_CMD_TA_MASK 0x1c0 + +/* + * Interrupt command data lowest 23-bit (latched from BB data[22: + * 0] or CPU request data) +*/ +#define REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_SHIFT 9 +#define REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_MASK 0xfffffe00 + + +/* + * Register - read-only + * + * SBPM IIR high (Interrupt information register) + */ +#define SBPM_REGS_SBPM_IIR_HIGH 0x14c + +/* + * Data (bits [63: + * 23], without reserved bits) of the command that caused interrupt +*/ +#define REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_SHIFT 0 +#define REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_MASK 0xffffffff + + +/* + * Register - read-only + * + * SBPM debug vector0 includes 21 bit of control/state machine of CMD pipe + */ +#define SBPM_REGS_SBPM_DBG_VEC0 0x150 + +/* Alloc State Machine{update, rd_head_cnxt} */ +#define REGS_SBPM_DBG_VEC0_ALLOC_SM_SHIFT 0 +#define REGS_SBPM_DBG_VEC0_ALLOC_SM_MASK 0x3 + +/* Connect State Machine{update} */ +#define REGS_SBPM_DBG_VEC0_CNNCT_SM_MASK 0x4 + +/* Multicast incr State Machine{read,check,error,update} */ +#define REGS_SBPM_DBG_VEC0_MCINT_SM_SHIFT 3 +#define REGS_SBPM_DBG_VEC0_MCINT_SM_MASK 0x78 + +/* Free w cnxt State Machine{read,check,update,error} */ +#define REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_SHIFT 7 +#define REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_MASK 0x780 + +/* Free w/o cnxt State Machine{read,check,update,error} */ +#define REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_SHIFT 11 +#define REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_MASK 0x7800 + +/* + * Get next State Machine: + * {read,reply} +*/ +#define REGS_SBPM_DBG_VEC0_GN_SM_SHIFT 15 +#define REGS_SBPM_DBG_VEC0_GN_SM_MASK 0x18000 + +/* + * Those are the 4 Multi get next states: + * {rd_next,error,rd_last,wait} +*/ +#define REGS_SBPM_DBG_VEC0_MULTI_GN_SM_SHIFT 17 +#define REGS_SBPM_DBG_VEC0_MULTI_GN_SM_MASK 0x1e0000 + +/* the value of the head of FREE list */ +#define REGS_SBPM_DBG_VEC0_FREE_LST_HD_SHIFT 21 +#define REGS_SBPM_DBG_VEC0_FREE_LST_HD_MASK 0xffe00000 + + +/* + * Register - read-only + * + * SBPM debug vector1 includes 21 bit of control/state machine of CMD pipe + */ +#define SBPM_REGS_SBPM_DBG_VEC1 0x154 + +/* sbpm_ingress2egress_valid bit */ +#define REGS_SBPM_DBG_VEC1_IN2E_VALID_MASK 0x1 + +/* multi_get_next_valid bits */ +#define REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_SHIFT 1 +#define REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_MASK 0x1e + +/* sbpm_ug_active 2 bits */ +#define REGS_SBPM_DBG_VEC1_UG_ACTIVE_SHIFT 5 +#define REGS_SBPM_DBG_VEC1_UG_ACTIVE_MASK 0x60 + +/* sbpm_tx_cmd_fifo_full bit */ +#define REGS_SBPM_DBG_VEC1_TX_CMD_FULL_MASK 0x80 + +/* sbpm_rx_fifo_pop bit */ +#define REGS_SBPM_DBG_VEC1_RX_FIFO_POP_MASK 0x100 + +/* sbpm_ram_init_start bit */ +#define REGS_SBPM_DBG_VEC1_RAM_INIT_START_MASK 0x200 + +/* sbpm_ram_init_done bit */ +#define REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_MASK 0x400 + +/* RX FIFO Data in pipe */ +#define REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_SHIFT 11 +#define REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_MASK 0x1ff800 + +/* sbpm_free_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_FREE_DECODE_MASK 0x200000 + +/* sbpm_in2e_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_IN2E_DECODE_MASK 0x400000 + +/* sbpm_free_wo_cnxt_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_MASK 0x800000 + +/* sbpm_get_next_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_MASK 0x1000000 + +/* sbpm_multi_get_next_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_MASK 0x2000000 + +/* sbpm_cnct_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_CNCT_DECODE_MASK 0x4000000 + +/* sbpm_free_w_cnxt_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_FREE_W_DECODE_MASK 0x8000000 + +/* sbpm_mcinc_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_MCIN_DECODE_MASK 0x10000000 + +/* sbpm_alloc_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_ALLOC_DECODE_MASK 0x20000000 + + +/* + * Register - read-only + * + * This is one of the TX_handler debug vectors + */ +#define SBPM_REGS_SBPM_DBG_VEC2 0x174 + +/* sbpm_tx_data_fifo_full */ +#define REGS_SBPM_DBG_VEC2_TX_DATA_FULL_MASK 0x1 + +/* sbpm_tx_fifo_empty */ +#define REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_MASK 0x2 + +/* sbpm_tx_cmd_local_stts_fifo_full */ +#define REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_MASK 0x4 + +/* sbpm_tx_cmd_local_stts_fifo_empty */ +#define REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_MASK 0x8 + +/* sbpm_tx_cmd_fifo_full */ +#define REGS_SBPM_DBG_VEC2_TX_CMD_FULL_MASK 0x10 + +/* sbpm_tx_cmd_fifo_empty */ +#define REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_MASK 0x20 + +/* + * bb_decoder_dest_idThis is the ID of the user that will recieve a message + * from SBPM +*/ +#define REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_SHIFT 6 +#define REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_MASK 0xfc0 + +/* sbpm_tx_bbh_send_in_progress bit */ +#define REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_MASK 0x1000 + +/* sbpm_sp_2send - this is the user ID that is about to get stts msg */ +#define REGS_SBPM_DBG_VEC2_SP_2SEND_SHIFT 13 +#define REGS_SBPM_DBG_VEC2_SP_2SEND_MASK 0x7e000 + +/* + * sbpm_tx2data_fifo_taddr[2: + * 0] this is the opcode that describe the type of the reply +*/ +#define REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_SHIFT 19 +#define REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_MASK 0x380000 + +/* sbpm_cpu_access bit */ +#define REGS_SBPM_DBG_VEC2_CPU_ACCESS_MASK 0x400000 + +/* sbpm_bbh_access bit */ +#define REGS_SBPM_DBG_VEC2_BBH_ACCESS_MASK 0x800000 + +/* sbpm_rnr_access bit */ +#define REGS_SBPM_DBG_VEC2_RNR_ACCESS_MASK 0x1000000 + + +/* + * Register - read-only + * + * This is one of TX_handler debug vectors + */ +#define SBPM_REGS_SBPM_DBG_VEC3 0x178 + +/* ALLOC_RPLY bit */ +#define REGS_SBPM_DBG_VEC3_ALLOC_RPLY_MASK 0x1 + +/* BN_RPLY value */ +#define REGS_SBPM_DBG_VEC3_BN_RPLY_SHIFT 1 +#define REGS_SBPM_DBG_VEC3_BN_RPLY_MASK 0xffe + +/* sbpm_txfifo_alloc_ack */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_MASK 0x1000 + +/* sbpm_txfifo_mcinc_ack */ +#define REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_MASK 0x2000 + +/* sbpm_txfifo_cnct_ack */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_MASK 0x4000 + +/* sbpm_txfifo_get_next_reply */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_MASK 0x8000 + +/* sbpm_txfifo_multi_get_next_reply */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_MASK 0x10000 + +/* sbpm_tx_msg_pipe_cur_sm */ +#define REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_SHIFT 17 +#define REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_MASK 0x60000 + +/* sbpm_send_stat_sm_ps */ +#define REGS_SBPM_DBG_VEC3_SEND_STT_SM_MASK 0x80000 + +/* sbpm_txfifo_ingress2egress_stts_change */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_MASK 0x100000 + + +/* + * Register + * + * This register mark all the SPs which are BBHs. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_BBH_LOW 0x17c + +/* sbpm_sp_bbh_low bit i tells us if SP #i is a BBH (1) or not (0) */ +#define REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_SHIFT 0 +#define REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs which are BBHs. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_BBH_HIGH 0x180 + +/* + * Not in use in 68360!sbpm_sp_bbh_high bit i tells us if SP #i is a BBH + * (1) or not (0) +*/ +#define REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_SHIFT 0 +#define REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs which are runners. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_RNR_LOW 0x184 + +/* sbpm_sp_rnr_low bit i tells us if SP #i is a runner (1) or not (0) */ +#define REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_SHIFT 0 +#define REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs which are runners. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_RNR_HIGH 0x188 + +/* + * Not in use in 68360!sbpm_sp_rnr_high bit i tells us if SP #i is a runner + * (1) or not (0) +*/ +#define REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_SHIFT 0 +#define REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_MASK 0xffffffff + + +/* + * Register + * + * bit i value determine if SP number i belongs to UG0 (ingress) or UG1 + * (egress) + */ +#define SBPM_REGS_SBPM_UG_MAP_LOW 0x18c + +/* + * bit i value determine if SP number i belongs to UG0 (ingress) or UG1 + * (egress) +*/ +#define REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_SHIFT 0 +#define REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_MASK 0xffffffff + + +/* + * Register + * + * bit i value determine if SP number i belongs to UG0 (ingress) or UG1 + * (egress) + */ +#define SBPM_REGS_SBPM_UG_MAP_HIGH 0x190 + +/* + * Not in use in 68360!bit i value determine if SP number i belongs to UG0 + * (ingress) or UG1 (egress) +*/ +#define REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_SHIFT 0 +#define REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_MASK 0xffffffff + + +/* + * Register - read-only + * + * bit i value determine if SP number i got nack or not + */ +#define SBPM_REGS_SBPM_NACK_MASK_LOW 0x194 + +/* bit i value determine if SP number i got nack or not */ +#define REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_SHIFT 0 +#define REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_MASK 0xffffffff + + +/* + * Register - read-only + * + * bit i value determine if SP number i got nack or not + */ +#define SBPM_REGS_SBPM_NACK_MASK_HIGH 0x198 + +/* bit i value determine if SP number i got nack or not */ +#define REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_SHIFT 0 +#define REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs that should get exclusive messages + */ +#define SBPM_REGS_SBPM_EXCL_MASK_LOW 0x19c + +/* This register mark all the SPs that should get exclusive messagesyes no */ +#define REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_SHIFT 0 +#define REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs that should get exclusive messages + */ +#define SBPM_REGS_SBPM_EXCL_MASK_HIGH 0x1a0 + +/* + * Not in use in 68360!This register mark all the SPs that should get + * exclusive messagesyes no +*/ +#define REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_SHIFT 0 +#define REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_MASK 0xffffffff + + +/* + * Register + * + * This register let you choose one user that you would like to change its + * default RA. + */ +#define SBPM_REGS_SBPM_RADDR_DECODER 0x1a4 + +/* + * this field contains the users id that you want to override its default + * RA +*/ +#define REGS_SBPM_RADDR_DECODER_ID_2OVERWR_SHIFT 0 +#define REGS_SBPM_RADDR_DECODER_ID_2OVERWR_MASK 0x3f + +/* The new RA */ +#define REGS_SBPM_RADDR_DECODER_OVERWR_RA_SHIFT 6 +#define REGS_SBPM_RADDR_DECODER_OVERWR_RA_MASK 0xffc0 + +/* the overwr mechanism will be used only if this bit is active (1). */ +#define REGS_SBPM_RADDR_DECODER_OVERWR_VALID_MASK 0x10000 + + +/* + * Register + * + * If SW want to write a whole word into the SBPMs RAM, it needs first to + * write the data to this register and then, send connect request with the + * wr_req bit asserted, with the address (BN field). + */ +#define SBPM_REGS_SBPM_WR_DATA 0x1a8 + +/* + * If SW want to write a whole word into the SBPMs RAM, it needs first to + * write the data to this register and then, send connect request with the + * wr_req bit asserted, with the address (BN field). + * In 68360 the only the 15 LSB are used +*/ +#define REGS_SBPM_WR_DATA_SBPM_WR_DATA_SHIFT 0 +#define REGS_SBPM_WR_DATA_SBPM_WR_DATA_MASK 0x3fffff + + +/* + * Register + * + * This register tracks the max values of the UG counters. + * it can be reset/modified by SW. + */ +#define SBPM_REGS_SBPM_UG_BAC_MAX 0x1ac + +/* + * This is the maximum value that have been recorded on the UG0 counter. + * SW can write to this field in order to change the max record (for + * example write 0 to reset it) +*/ +#define REGS_SBPM_UG_BAC_MAX_UG0BACMAX_SHIFT 0 +#define REGS_SBPM_UG_BAC_MAX_UG0BACMAX_MASK 0x3fff + +/* + * This is the maximum value that have been recorded on the UG1 counter. + * SW can write to this field in order to change the max record (for + * example write 0 to reset it) +*/ +#define REGS_SBPM_UG_BAC_MAX_UG1BACMAX_SHIFT 14 +#define REGS_SBPM_UG_BAC_MAX_UG1BACMAX_MASK 0xfffc000 + + +/* + * Register + * + * sbpm spare register + */ +#define SBPM_REGS_SBPM_SPARE 0x1b0 + +/* sbpm_gl_bac_clear_en */ +#define REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_MASK 0x1 + + +/* + * Register + * + * This register contains the current active TM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define SBPM_INTR_CTRL_ISR 0x200 + +/* + * This error bit indicates underrun state of SBPM Buffer Allocated Counter + * (one of User Groups). + * SW can clear this bit by writing 1 to this field +*/ +#define INTR_CTRL_ISR_BAC_UNDERRUN_MASK 0x1 + +/* + * This error bit indicates if the Multi Cast value of a buffer is in + * overflow as a result of erroneous MCINC command +*/ +#define INTR_CTRL_ISR_MCST_OVERFLOW_MASK 0x2 + +/* + * This bit indicates error state on Last BN checking during Free with + * context request. + * SW can clear this bit by writing 1 to this field. +*/ +#define INTR_CTRL_ISR_CHECK_LAST_ERR_MASK 0x4 + +/* + * This bit indicates error state on maximal search checking during Free + * without context request. + * SW can clear this bit by writing 1 to this field. +*/ +#define INTR_CTRL_ISR_MAX_SEARCH_ERR_MASK 0x8 + +/* + * This bit indicates invalid ingress2egress command (caused BAC + * under/overrun). + * SW can clear this bit by writing 1 to this field. +*/ +#define INTR_CTRL_ISR_INVALID_IN2E_MASK 0x10 + +/* + * This bit indicates Null encounter during one of the next BNs. + * SW can clear this bit by writing 0 to this field. +*/ +#define INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_MASK 0x20 + +/* + * This bit indicates connection of the NULL buffer to another buufer. + * SW can clear this bit by writing 0 to this field. +*/ +#define INTR_CTRL_ISR_CNCT_NULL_MASK 0x40 + +/* + * This bit indicates allocation of the NULL buffer. + * SW can clear this bit by writing 0 to this field. +*/ +#define INTR_CTRL_ISR_ALLOC_NULL_MASK 0x80 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define SBPM_INTR_CTRL_ISM 0x204 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define INTR_CTRL_ISM_ISM_SHIFT 0 +#define INTR_CTRL_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define SBPM_INTR_CTRL_IER 0x208 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define INTR_CTRL_IER_IEM_SHIFT 0 +#define INTR_CTRL_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define SBPM_INTR_CTRL_ITR 0x20c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define INTR_CTRL_ITR_IST_SHIFT 0 +#define INTR_CTRL_ITR_IST_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_SBPM_H_ */ diff -Nruw linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_tcam.h linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_tcam.h --- linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp./regs/xrdp_regs_tcam.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-6.4-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_tcam.h 2023-03-09 15:06:11.384234759 +0100 @@ -0,0 +1,225 @@ +#ifndef XRDP_REGS_TCAM_H_ +#define XRDP_REGS_TCAM_H_ + +/* relative to core */ +#define TCAM_OFFSET_0 0xe00000 + +/* + * Registers - is [ 0 => 2047 ] + * + * Each 64 bit entry in the context ram occupies two addresses: + * For 64bit entry number i: + * the 32 least significant bits of the context are in address 2*ithe 32 + * most significant bits of the context are in address 2*i +1 + */ +#define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT(x) (0x0 + (x) * 0x4) + +/* . */ +#define CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_SHIFT 0 +#define CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_MASK 0xffffffff + + +/* + * Register + * + * The TCAM is divided into 8 banks. + * banks can be disabled to save power. + * bit i correspond to addresses i*128: + * i*128+127 + */ +#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN 0x2000 + +/* . */ +#define CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_SHIFT 0 +#define CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_MASK 0xff + + +/* + * Registers - is [ 0 => 7 ] + * + * Global Mask - 256bit mask for all entries. + * Default value enable all bits. + */ +#define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK(x) (0x2010 + (x) * 0x4) + +/* . */ +#define CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_SHIFT 0 +#define CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 256bit key searches + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256 0x2100 + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 256bit key hits + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256 0x2104 + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 512it key searches + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512 0x2108 + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 512bit key hits + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512 0x210c + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_MASK 0xffffffff + + +/* + * Register + * + * TCAM Operation: + * 0 - TCAM READ1 - TCAM Write2 - TCAM Compare3 - TCAM valid bit + * resetWriting to this register triggers the operation. + * All other relevant register should be ready before SW writes to this + * register. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP 0x2200 + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_SHIFT 0 +#define INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_MASK 0xf + + +/* + * Register - read-only + * + * Raised when the TCAM operation is completed (cleared by HW on write to + * the OPERATION regiser) + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE 0x2204 + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_MASK 0x1 + + +/* + * Register
+ * + * Key Address to be used in RD/WR opoerations. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR 0x2208 + +/* + * This bit indicate if the operation (RD/WR) is performed on the key0 or + * key1 part of the entry +*/ +#define INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_MASK 0x1 + +/* Address of the entry */ +#define INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_SHIFT 1 +#define INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_MASK 0x7fe + + +/* + * Register + * + * Valid value to be written - this value is relevant during write + * operation on key0. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN 0x220c + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_MASK 0x1 + + +/* + * Register + * + * Valid value read from the TCAM - this value is relevant during read + * operation on key0. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT 0x2214 + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_MASK 0x1 + + +/* + * Register - read-only + * + * The result of a search operation + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT 0x2218 + +/* indicate if a match was found */ +#define INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_MASK 0x1 + +/* index related to a match result */ +#define INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_SHIFT 4 +#define INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_MASK 0x3ff0 + + +/* + * Registers - is [ 0 => 7 ] + * + * Key to be used in Write/Compare operations. + * The Key is 256bit long and is represented by 8 registers. + * The lower address register correspond to the least significant bits of + * the key. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN(x) (0x2220 + (x) * 0x4) + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_SHIFT 0 +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * Key returned from the CAM in a read operation. + * The Key is 256bit long and is represented by 8 registers. + * The lower address register correspond to the least significant bits of + * the key. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT(x) (0x2240 + (x) * 0x4) + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_SHIFT 0 +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_MASK 0xffffffff + + +/* + * Register