diff -ruw linux-5.4.60/arch/arm64/boot/dts/amlogic/Makefile linux-5.4.60-fbx/arch/arm64/boot/dts/amlogic/Makefile --- linux-5.4.60/arch/arm64/boot/dts/amlogic/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/arch/arm64/boot/dts/amlogic/Makefile 2021-03-04 13:20:57.000838854 +0100 @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +DTC_FLAGS += -@ +dtb-$(CONFIG_ARCH_MESON) += fbxwmr.dtb fbxwmr-r1.dtb fbxwmr-r2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb diff -ruw linux-5.4.60/arch/arm64/boot/dts/broadcom/Makefile linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/Makefile --- linux-5.4.60/arch/arm64/boot/dts/broadcom/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/Makefile 2021-03-04 13:20:57.004172187 +0100 @@ -6,3 +6,4 @@ subdir-y += northstar2 subdir-y += stingray +subdir-y += bcm63xx diff -ruw linux-5.4.60/arch/arm64/boot/dts/marvell/Makefile linux-5.4.60-fbx/arch/arm64/boot/dts/marvell/Makefile --- linux-5.4.60/arch/arm64/boot/dts/marvell/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/arch/arm64/boot/dts/marvell/Makefile 2021-03-04 13:20:57.010838855 +0100 @@ -10,3 +10,17 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_dsl_lte.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_pon.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_test_module.dtb + +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp2_ftth_p2p.dtb + +# export symbols in DTBs file to allow overlay usage +DTC_FLAGS += -@ diff -ruw linux-5.4.60/arch/arm64/include/asm/cputype.h linux-5.4.60-fbx/arch/arm64/include/asm/cputype.h --- linux-5.4.60/arch/arm64/include/asm/cputype.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/arch/arm64/include/asm/cputype.h 2021-03-04 13:20:57.027505522 +0100 @@ -94,6 +94,7 @@ #define HISI_CPU_PART_TSV110 0xD01 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) +#define MIDR_CORTEX_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) diff -ruw linux-5.4.60/arch/arm64/include/asm/memory.h linux-5.4.60-fbx/arch/arm64/include/asm/memory.h --- linux-5.4.60/arch/arm64/include/asm/memory.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/arch/arm64/include/asm/memory.h 2021-03-04 13:20:57.030838855 +0100 @@ -84,7 +84,7 @@ #define KASAN_SHADOW_OFFSET _AC(CONFIG_KASAN_SHADOW_OFFSET, UL) #define KASAN_SHADOW_END ((UL(1) << (64 - KASAN_SHADOW_SCALE_SHIFT)) \ + KASAN_SHADOW_OFFSET) -#define KASAN_THREAD_SHIFT 1 +#define KASAN_THREAD_SHIFT 2 #else #define KASAN_THREAD_SHIFT 0 #define KASAN_SHADOW_END (_PAGE_END(VA_BITS_MIN)) diff -ruw linux-5.4.60/arch/arm64/include/asm/pgtable-hwdef.h linux-5.4.60-fbx/arch/arm64/include/asm/pgtable-hwdef.h --- linux-5.4.60/arch/arm64/include/asm/pgtable-hwdef.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/arch/arm64/include/asm/pgtable-hwdef.h 2021-03-04 13:20:57.030838855 +0100 @@ -147,7 +147,11 @@ #define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1) #define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */ #define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */ +#ifdef CONFIG_ARCH_BCM63XX_SHARED_OSH +#define PTE_SHARED (_AT(pteval_t, 2) << 8) /* SH[1:0], outer shareable */ +#else #define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */ +#endif #define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */ #define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */ #define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */ @@ -263,12 +267,19 @@ #define TCR_SH0_SHIFT 12 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT) +#define TCR_SH0_OUTER (UL(2) << TCR_SH0_SHIFT) #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT) #define TCR_SH1_SHIFT 28 #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT) +#define TCR_SH1_OUTER (UL(2) << TCR_SH1_SHIFT) #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT) + +#ifdef CONFIG_ARCH_BCM63XX_SHARED_OSH +#define TCR_SHARED (TCR_SH0_OUTER | TCR_SH1_OUTER) +#else #define TCR_SHARED (TCR_SH0_INNER | TCR_SH1_INNER) +#endif #define TCR_TG0_SHIFT 14 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT) diff -ruw linux-5.4.60/arch/arm64/Kconfig.platforms linux-5.4.60-fbx/arch/arm64/Kconfig.platforms --- linux-5.4.60/arch/arm64/Kconfig.platforms 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/arch/arm64/Kconfig.platforms 2021-03-04 13:20:57.000838854 +0100 @@ -51,6 +51,22 @@ help This enables support for Broadcom iProc based SoCs +config ARCH_BCM63XX + bool "Broadcom BCM63XX family" + select PINCTRL + select GPIOLIB + select PINCTRL_BCM63138 + help + This enables support for Broadcom BCM63XX Family + +config ARCH_BCM63XX_SHARED_OSH + bool "Make shared pages and translation table walks outer shareable" + depends on ARCH_BCM63XX + default y + help + This is required for HW coherency on bcm63158. Say Y here if + you are compiling a kernel for a bcm63158 board. + config ARCH_BERLIN bool "Marvell Berlin SoC Family" select DW_APB_ICTL diff -ruw linux-5.4.60/block/blk-core.c linux-5.4.60-fbx/block/blk-core.c --- linux-5.4.60/block/blk-core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/blk-core.c 2021-03-04 13:20:57.497505542 +0100 @@ -1319,7 +1319,7 @@ } } -void blk_account_io_done(struct request *req, u64 now) +void blk_account_io_done(struct request *req, u64 now, blk_status_t error) { /* * Account IO completion. flush_rq isn't accounted as a @@ -1333,6 +1333,10 @@ part_stat_lock(); part = req->part; + if (error) { + int rw = rq_data_dir(req); + part_stat_inc(part, io_errors[rw]); + } update_io_ticks(part, jiffies); part_stat_inc(part, ios[sgrp]); part_stat_add(part, nsecs[sgrp], now - req->start_time_ns); diff -ruw linux-5.4.60/block/blk-flush.c linux-5.4.60-fbx/block/blk-flush.c --- linux-5.4.60/block/blk-flush.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/blk-flush.c 2021-03-04 13:20:57.497505542 +0100 @@ -165,10 +165,21 @@ rq->flush.seq |= seq; cmd_flags = rq->cmd_flags; - if (likely(!error)) + if (likely(!error)) { seq = blk_flush_cur_seq(rq); - else + } else { seq = REQ_FSEQ_DONE; + printk_once(KERN_ERR "%s: flush failed: data integrity problem\n", + rq->rq_disk ? rq->rq_disk->disk_name : "?"); + /* + * returning an error to the FS is wrong: the data is all + * there, it just might not be written out in the expected + * order and thus have a window where the integrity is suspect + * in a crash. Given the small likelihood of actually + * crashing, we should just log a warning here. + */ + error = 0; + } switch (seq) { case REQ_FSEQ_PREFLUSH: diff -ruw linux-5.4.60/block/blk.h linux-5.4.60-fbx/block/blk.h --- linux-5.4.60/block/blk.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/blk.h 2021-03-04 13:20:57.500838876 +0100 @@ -187,7 +187,7 @@ void blk_account_io_start(struct request *req, bool new_io); void blk_account_io_completion(struct request *req, unsigned int bytes); -void blk_account_io_done(struct request *req, u64 now); +void blk_account_io_done(struct request *req, u64 now, blk_status_t error); /* * Internal elevator interface diff -ruw linux-5.4.60/block/blk-mq.c linux-5.4.60-fbx/block/blk-mq.c --- linux-5.4.60/block/blk-mq.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/blk-mq.c 2021-03-04 13:20:57.497505542 +0100 @@ -552,7 +552,7 @@ if (rq->internal_tag != -1) blk_mq_sched_completed_request(rq, now); - blk_account_io_done(rq, now); + blk_account_io_done(rq, now, error); if (rq->end_io) { rq_qos_done(rq->q, rq); diff -ruw linux-5.4.60/block/partition-generic.c linux-5.4.60-fbx/block/partition-generic.c --- linux-5.4.60/block/partition-generic.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/partition-generic.c 2021-03-04 13:20:57.500838876 +0100 @@ -128,6 +128,7 @@ "%8lu %8lu %8llu %8u " "%8u %8u %8u " "%8lu %8lu %8llu %8u" + "%8lu %lu" "\n", part_stat_read(p, ios[STAT_READ]), part_stat_read(p, merges[STAT_READ]), @@ -143,7 +144,9 @@ part_stat_read(p, ios[STAT_DISCARD]), part_stat_read(p, merges[STAT_DISCARD]), (unsigned long long)part_stat_read(p, sectors[STAT_DISCARD]), - (unsigned int)part_stat_read_msecs(p, STAT_DISCARD)); + (unsigned int)part_stat_read_msecs(p, STAT_DISCARD), + part_stat_read(p, io_errors[READ]), + part_stat_read(p, io_errors[WRITE])); } ssize_t part_inflight_show(struct device *dev, struct device_attribute *attr, @@ -345,7 +348,7 @@ queue_limit_discard_alignment(&disk->queue->limits, start); p->nr_sects = len; p->partno = partno; - p->policy = get_disk_ro(disk); + p->policy = get_disk_ro(disk) || (flags & ADDPART_FLAG_RO); if (info) { struct partition_meta_info *pinfo = alloc_part_info(disk); diff -ruw linux-5.4.60/block/partitions/check.c linux-5.4.60-fbx/block/partitions/check.c --- linux-5.4.60/block/partitions/check.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/partitions/check.c 2021-03-04 13:20:57.500838876 +0100 @@ -24,6 +24,7 @@ #include "acorn.h" #include "amiga.h" #include "atari.h" +#include "dt.h" #include "ldm.h" #include "mac.h" #include "msdos.h" @@ -40,6 +41,10 @@ int warn_no_part = 1; /*This is ugly: should make genhd removable media aware*/ static int (*check_part[])(struct parsed_partitions *) = { +#ifdef CONFIG_OF_PARTITION + dt_partition, +#endif + /* * Probe partition formats with tables at disk address 0 * that also have an ADFS boot block at 0xdc0. diff -ruw linux-5.4.60/block/partitions/Kconfig linux-5.4.60-fbx/block/partitions/Kconfig --- linux-5.4.60/block/partitions/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/partitions/Kconfig 2021-03-04 13:20:57.500838876 +0100 @@ -268,3 +268,11 @@ help Say Y here if you want to read the partition table from bootargs. The format for the command line is just like mtdparts. + +config OF_PARTITION + bool "Device tree partition support" if PARTITION_ADVANCED + depends on OF + +config OF_PARTITION_IGNORE_RO + bool "ignore read-only flag" + depends on OF_PARTITION diff -ruw linux-5.4.60/block/partitions/Makefile linux-5.4.60-fbx/block/partitions/Makefile --- linux-5.4.60/block/partitions/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/block/partitions/Makefile 2021-03-04 13:20:57.500838876 +0100 @@ -21,3 +21,4 @@ obj-$(CONFIG_EFI_PARTITION) += efi.o obj-$(CONFIG_KARMA_PARTITION) += karma.o obj-$(CONFIG_SYSV68_PARTITION) += sysv68.o +obj-$(CONFIG_OF_PARTITION) += dt.o diff -ruw linux-5.4.60/drivers/base/property.c linux-5.4.60-fbx/drivers/base/property.c --- linux-5.4.60/drivers/base/property.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/base/property.c 2021-03-04 13:20:57.590838880 +0100 @@ -17,6 +17,7 @@ #include #include #include +#include struct fwnode_handle *dev_fwnode(struct device *dev) { @@ -838,6 +839,21 @@ { char *res; +#ifdef CONFIG_FBXSERIAL + u32 index; + int ret; + + ret = fwnode_property_read_u32(fwnode, "fbxserial-mac-address", + &index); + if (ret == 0) { + res = (void *)fbxserialinfo_get_mac_addr(index); + if (res) { + memcpy(addr, res, alen); + return res; + } + } +#endif + res = fwnode_get_mac_addr(fwnode, "mac-address", addr, alen); if (res) return res; diff -ruw linux-5.4.60/drivers/base/regmap/internal.h linux-5.4.60-fbx/drivers/base/regmap/internal.h --- linux-5.4.60/drivers/base/regmap/internal.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/base/regmap/internal.h 2021-03-04 13:20:57.590838880 +0100 @@ -294,4 +294,6 @@ return reg >> map->reg_stride_order; } +void *regmap_mmio_ctx_get_base(const void *priv); + #endif diff -ruw linux-5.4.60/drivers/base/regmap/regmap.c linux-5.4.60-fbx/drivers/base/regmap/regmap.c --- linux-5.4.60/drivers/base/regmap/regmap.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/base/regmap/regmap.c 2021-03-04 13:20:57.590838880 +0100 @@ -3110,6 +3110,15 @@ } EXPORT_SYMBOL_GPL(regmap_parse_val); +#ifdef CONFIG_REGMAP_MMIO +void *regmap_get_mmio_base_address(struct regmap *map) +{ + return regmap_mmio_ctx_get_base(map->bus_context); +} + +EXPORT_SYMBOL_GPL(regmap_get_mmio_base_address); +#endif + static int __init regmap_initcall(void) { regmap_debugfs_initcall(); diff -ruw linux-5.4.60/drivers/base/regmap/regmap-mmio.c linux-5.4.60-fbx/drivers/base/regmap/regmap-mmio.c --- linux-5.4.60/drivers/base/regmap/regmap-mmio.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/base/regmap/regmap-mmio.c 2021-03-04 13:20:57.590838880 +0100 @@ -376,4 +376,10 @@ } EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk); +void *regmap_mmio_ctx_get_base(const void *priv) +{ + struct regmap_mmio_context *ctx = (struct regmap_mmio_context *)priv; + return ctx->regs; +} + MODULE_LICENSE("GPL v2"); diff -ruw linux-5.4.60/drivers/bluetooth/btrtl.c linux-5.4.60-fbx/drivers/bluetooth/btrtl.c --- linux-5.4.60/drivers/bluetooth/btrtl.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/bluetooth/btrtl.c 2021-03-04 13:20:57.610838881 +0100 @@ -17,8 +17,12 @@ #define VERSION "0.1" +#define RTL_CHIP_8723CS_CG 3 +#define RTL_CHIP_8723CS_VF 4 +#define RTL_CHIP_8723CS_XX 5 #define RTL_EPATCH_SIGNATURE "Realtech" #define RTL_ROM_LMP_3499 0x3499 +#define RTL_ROM_LMP_8703B 0x8703 #define RTL_ROM_LMP_8723A 0x1200 #define RTL_ROM_LMP_8723B 0x8723 #define RTL_ROM_LMP_8723D 0x8873 @@ -31,6 +35,7 @@ #define IC_MATCH_FL_HCIREV (1 << 1) #define IC_MATCH_FL_HCIVER (1 << 2) #define IC_MATCH_FL_HCIBUS (1 << 3) +#define IC_MATCH_FL_CHIP_TYPE (1 << 4) #define IC_INFO(lmps, hcir) \ .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV, \ .lmp_subver = (lmps), \ @@ -42,6 +47,7 @@ __u16 hci_rev; __u8 hci_ver; __u8 hci_bus; + __u8 chip_type; bool config_needed; bool has_rom_version; char *fw_name; @@ -89,6 +95,39 @@ .fw_name = "rtl_bt/rtl8723b_fw.bin", .cfg_name = "rtl_bt/rtl8723b_config" }, + /* 8723CS-CG */ + { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | + IC_MATCH_FL_HCIBUS, + .lmp_subver = RTL_ROM_LMP_8703B, + .chip_type = RTL_CHIP_8723CS_CG, + .hci_bus = HCI_UART, + .config_needed = true, + .has_rom_version = true, + .fw_name = "rtl_bt/rtl8723cs_cg_fw.bin", + .cfg_name = "rtl_bt/rtl8723cs_cg_config" }, + + /* 8723CS-VF */ + { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | + IC_MATCH_FL_HCIBUS, + .lmp_subver = RTL_ROM_LMP_8703B, + .chip_type = RTL_CHIP_8723CS_VF, + .hci_bus = HCI_UART, + .config_needed = true, + .has_rom_version = true, + .fw_name = "rtl_bt/rtl8723cs_vf_fw.bin", + .cfg_name = "rtl_bt/rtl8723cs_vf_config" }, + + /* 8723CS-XX */ + { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_CHIP_TYPE | + IC_MATCH_FL_HCIBUS, + .lmp_subver = RTL_ROM_LMP_8703B, + .chip_type = RTL_CHIP_8723CS_XX, + .hci_bus = HCI_UART, + .config_needed = true, + .has_rom_version = true, + .fw_name = "rtl_bt/rtl8723cs_xx_fw.bin", + .cfg_name = "rtl_bt/rtl8723cs_xx_config" }, + /* 8723D */ { IC_INFO(RTL_ROM_LMP_8723B, 0xd), .config_needed = true, @@ -129,6 +168,15 @@ .fw_name = "rtl_bt/rtl8821c_fw.bin", .cfg_name = "rtl_bt/rtl8821c_config" }, + /* 8761BTV */ + { .match_flags = IC_MATCH_FL_LMPSUBV | IC_MATCH_FL_HCIREV, + .lmp_subver = RTL_ROM_LMP_8761A, + .hci_rev = 0xb, + .config_needed = false, + .has_rom_version = true, + .fw_name = "rtl_bt/rtl8761b_fw.bin", + .cfg_name = "rtl_bt/rtl8761b_config" }, + /* 8761A */ { IC_MATCH_FL_LMPSUBV, RTL_ROM_LMP_8761A, 0x0, .config_needed = false, @@ -152,7 +200,8 @@ }; static const struct id_table *btrtl_match_ic(u16 lmp_subver, u16 hci_rev, - u8 hci_ver, u8 hci_bus) + u8 hci_ver, u8 hci_bus, + u8 chip_type) { int i; @@ -169,6 +218,9 @@ if ((ic_id_table[i].match_flags & IC_MATCH_FL_HCIBUS) && (ic_id_table[i].hci_bus != hci_bus)) continue; + if ((ic_id_table[i].match_flags & IC_MATCH_FL_CHIP_TYPE) && + (ic_id_table[i].chip_type != chip_type)) + continue; break; } @@ -251,10 +303,12 @@ { RTL_ROM_LMP_8723B, 1 }, { RTL_ROM_LMP_8821A, 2 }, { RTL_ROM_LMP_8761A, 3 }, + { RTL_ROM_LMP_8703B, 7 }, { RTL_ROM_LMP_8822B, 8 }, { RTL_ROM_LMP_8723B, 9 }, /* 8723D */ { RTL_ROM_LMP_8821A, 10 }, /* 8821C */ { RTL_ROM_LMP_8822B, 13 }, /* 8822C */ + { RTL_ROM_LMP_8761A, 14 }, }; min_size = sizeof(struct rtl_epatch_header) + sizeof(extension_sig) + 3; @@ -399,7 +453,7 @@ for (i = 0; i < frag_num; i++) { struct sk_buff *skb; - BT_DBG("download fw (%d/%d)", i, frag_num); + BT_DBG("download fw (%d/%d)", i + 1, frag_num); if (i > 0x7f) dl_cmd->index = (i & 0x7f) + 1; @@ -523,6 +577,69 @@ return ret; } +static bool rtl_has_chip_type(u16 lmp_subver) +{ + switch (lmp_subver) { + case RTL_ROM_LMP_8703B: + return true; + default: + break; + } + + return false; +} + +static int rtl_read_chip_type(struct hci_dev *hdev, u8 *type) +{ + struct rtl_chip_type_evt *chip_type; + struct sk_buff *skb; + const unsigned char cmd_buf[] = {0x00, 0x94, 0xa0, 0x00, 0xb0}; + + /* Read RTL chip type command */ + skb = __hci_cmd_sync(hdev, 0xfc61, 5, cmd_buf, HCI_INIT_TIMEOUT); + if (IS_ERR(skb)) { + rtl_dev_err(hdev, "Read chip type failed (%ld)", + PTR_ERR(skb)); + return PTR_ERR(skb); + } + + if (skb->len != sizeof(*chip_type)) { + rtl_dev_err(hdev, "RTL chip type event length mismatch"); + kfree_skb(skb); + return -EIO; + } + + chip_type = (struct rtl_chip_type_evt *)skb->data; + rtl_dev_info(hdev, "chip_type status=%x type=%x", + chip_type->status, chip_type->type); + + *type = chip_type->type & 0x0f; + + kfree_skb(skb); + return 0; +} + +void btrtl_show_version(struct hci_dev *hdev) +{ + + struct sk_buff *skb; + struct hci_rp_read_local_version *resp; + + skb = btrtl_read_local_version(hdev); + if (IS_ERR(skb)) + return; + + resp = (struct hci_rp_read_local_version *)skb->data; + rtl_dev_info(hdev, + "rtl: hci_ver=%02x hci_rev=%04x lmp_ver=%02x lmp_subver=%04x", + resp->hci_ver, + le16_to_cpu(resp->hci_rev), + resp->lmp_ver, + le16_to_cpu(resp->lmp_subver)); + kfree_skb(skb); +} +EXPORT_SYMBOL_GPL(btrtl_show_version); + void btrtl_free(struct btrtl_device_info *btrtl_dev) { kfree(btrtl_dev->fw_data); @@ -539,7 +656,7 @@ struct hci_rp_read_local_version *resp; char cfg_name[40]; u16 hci_rev, lmp_subver; - u8 hci_ver; + u8 hci_ver, chip_type = 0; int ret; btrtl_dev = kzalloc(sizeof(*btrtl_dev), GFP_KERNEL); @@ -564,8 +681,14 @@ lmp_subver = le16_to_cpu(resp->lmp_subver); kfree_skb(skb); + if (rtl_has_chip_type(lmp_subver)) { + ret = rtl_read_chip_type(hdev, &chip_type); + if (ret) + goto err_free; + } + btrtl_dev->ic_info = btrtl_match_ic(lmp_subver, hci_rev, hci_ver, - hdev->bus); + hdev->bus, chip_type); if (!btrtl_dev->ic_info) { rtl_dev_info(hdev, "unknown IC info, lmp subver %04x, hci rev %04x, hci ver %04x", @@ -638,6 +761,7 @@ case RTL_ROM_LMP_8821A: case RTL_ROM_LMP_8761A: case RTL_ROM_LMP_8822B: + case RTL_ROM_LMP_8703B: return btrtl_setup_rtl8723b(hdev, btrtl_dev); default: rtl_dev_info(hdev, "assuming no firmware upload needed"); @@ -656,7 +780,12 @@ return PTR_ERR(btrtl_dev); ret = btrtl_download_firmware(hdev, btrtl_dev); + if (ret) + goto out_free; + + btrtl_apply_quirks(hdev, btrtl_dev); +out_free: btrtl_free(btrtl_dev); /* Enable controller to do both LE scan and BR/EDR inquiry @@ -796,6 +925,24 @@ } EXPORT_SYMBOL_GPL(btrtl_get_uart_settings); +void btrtl_apply_quirks(struct hci_dev *hdev, + struct btrtl_device_info *btrtl_dev) +{ + switch (btrtl_dev->ic_info->lmp_subver) { + case RTL_ROM_LMP_8703B: + /* 8723CS reports two pages for local ext features, + * but it doesn't support any features from page 2 - + * it either responds with garbage or with error status + */ + set_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, + &hdev->quirks); + break; + default: + break; + } +} +EXPORT_SYMBOL_GPL(btrtl_apply_quirks); + MODULE_AUTHOR("Daniel Drake "); MODULE_DESCRIPTION("Bluetooth support for Realtek devices ver " VERSION); MODULE_VERSION(VERSION); @@ -805,10 +952,18 @@ MODULE_FIRMWARE("rtl_bt/rtl8723b_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8723bs_fw.bin"); MODULE_FIRMWARE("rtl_bt/rtl8723bs_config.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_fw.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8723cs_cg_config.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_fw.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8723cs_vf_config.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_fw.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8723cs_xx_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8723ds_fw.bin"); MODULE_FIRMWARE("rtl_bt/rtl8723ds_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8761a_fw.bin"); MODULE_FIRMWARE("rtl_bt/rtl8761a_config.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8761b_fw.bin"); +MODULE_FIRMWARE("rtl_bt/rtl8761b_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8821a_fw.bin"); MODULE_FIRMWARE("rtl_bt/rtl8821a_config.bin"); MODULE_FIRMWARE("rtl_bt/rtl8822b_fw.bin"); diff -ruw linux-5.4.60/drivers/bluetooth/btrtl.h linux-5.4.60-fbx/drivers/bluetooth/btrtl.h --- linux-5.4.60/drivers/bluetooth/btrtl.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/bluetooth/btrtl.h 2021-03-04 13:20:57.610838881 +0100 @@ -14,6 +14,11 @@ struct btrtl_device_info; +struct rtl_chip_type_evt { + __u8 status; + __u8 type; +} __packed; + struct rtl_download_cmd { __u8 index; __u8 data[RTL_FRAG_LEN]; @@ -60,7 +65,10 @@ struct btrtl_device_info *btrtl_dev, unsigned int *controller_baudrate, u32 *device_baudrate, bool *flow_control); +void btrtl_apply_quirks(struct hci_dev *hdev, + struct btrtl_device_info *btrtl_dev); +void btrtl_show_version(struct hci_dev *hdev); #else static inline struct btrtl_device_info *btrtl_initialize(struct hci_dev *hdev, @@ -98,4 +106,9 @@ return -ENOENT; } +static inline void btrtl_apply_quirks(struct hci_dev *hdev, + struct btrtl_device_info *btrtl_dev) +{ +} + #endif diff -ruw linux-5.4.60/drivers/bluetooth/hci_h5.c linux-5.4.60-fbx/drivers/bluetooth/hci_h5.c --- linux-5.4.60/drivers/bluetooth/hci_h5.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/bluetooth/hci_h5.c 2021-03-04 13:20:57.610838881 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -92,6 +93,7 @@ const struct h5_vnd *vnd; const char *id; + struct gpio_desc *reset_gpio; struct gpio_desc *enable_gpio; struct gpio_desc *device_wake_gpio; }; @@ -807,6 +809,11 @@ if (h5->vnd->acpi_gpio_map) devm_acpi_dev_add_driver_gpios(dev, h5->vnd->acpi_gpio_map); + } else { + h5->vnd = (const struct h5_vnd *) + of_device_get_match_data(&serdev->dev); + of_property_read_string(serdev->dev.of_node, + "firmware-postfix", &h5->id); } h5->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); @@ -818,6 +825,10 @@ if (IS_ERR(h5->device_wake_gpio)) return PTR_ERR(h5->device_wake_gpio); + h5->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(h5->reset_gpio)) + return PTR_ERR(h5->reset_gpio); + return hci_uart_register_device(&h5->serdev_hu, &h5p); } @@ -890,6 +901,12 @@ err = btrtl_download_firmware(h5->hu->hdev, btrtl_dev); /* Give the device some time before the hci-core sends it a reset */ usleep_range(10000, 20000); + if (err) + goto out_free; + + /* show version after download */ + btrtl_show_version(h5->hu->hdev); + btrtl_apply_quirks(h5->hu->hdev, btrtl_dev); out_free: btrtl_free(btrtl_dev); @@ -904,8 +921,15 @@ serdev_device_set_parity(h5->hu->serdev, SERDEV_PARITY_EVEN); serdev_device_set_baudrate(h5->hu->serdev, 115200); + /* make sure reset is held */ + gpiod_set_value_cansleep(h5->reset_gpio, 1); + msleep(10); + /* The controller needs up to 500ms to wakeup */ gpiod_set_value_cansleep(h5->enable_gpio, 1); + /* Take it out of reset */ + gpiod_set_value_cansleep(h5->reset_gpio, 0); + msleep(100); gpiod_set_value_cansleep(h5->device_wake_gpio, 1); msleep(500); } @@ -913,6 +937,7 @@ static void h5_btrtl_close(struct h5 *h5) { gpiod_set_value_cansleep(h5->device_wake_gpio, 0); + gpiod_set_value_cansleep(h5->reset_gpio, 1); gpiod_set_value_cansleep(h5->enable_gpio, 0); } @@ -976,7 +1001,7 @@ {}, }; -static struct h5_vnd rtl_vnd = { +static __maybe_unused struct h5_vnd rtl_vnd = { .setup = h5_btrtl_setup, .open = h5_btrtl_open, .close = h5_btrtl_close, @@ -984,6 +1009,7 @@ .resume = h5_btrtl_resume, .acpi_gpio_map = acpi_btrtl_gpios, }; + #endif #ifdef CONFIG_ACPI @@ -1000,12 +1026,27 @@ SET_SYSTEM_SLEEP_PM_OPS(h5_serdev_suspend, h5_serdev_resume) }; +static struct h5_vnd rtl8723_of_vnd = { + .setup = h5_btrtl_setup, + .open = h5_btrtl_open, + .close = h5_btrtl_close, +}; + +static const struct of_device_id h5_of_match[] = { + { .compatible = "realtek,rtl8723bs-bt", .data = &rtl8723_of_vnd }, + { .compatible = "realtek,rtl8723cs-bt", .data = &rtl8723_of_vnd }, + { .compatible = "realtek,rtl8761btv-bt", .data = &rtl8723_of_vnd }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, h5_of_match); + static struct serdev_device_driver h5_serdev_driver = { .probe = h5_serdev_probe, .remove = h5_serdev_remove, .driver = { .name = "hci_uart_h5", .acpi_match_table = ACPI_PTR(h5_acpi_match), + .of_match_table = of_match_ptr(h5_of_match), .pm = &h5_serdev_pm_ops, }, }; diff -ruw linux-5.4.60/drivers/bluetooth/Kconfig linux-5.4.60-fbx/drivers/bluetooth/Kconfig --- linux-5.4.60/drivers/bluetooth/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/bluetooth/Kconfig 2021-03-04 13:20:57.607505547 +0100 @@ -211,7 +211,6 @@ depends on BT_HCIUART depends on BT_HCIUART_SERDEV depends on GPIOLIB - depends on ACPI select BT_HCIUART_3WIRE select BT_RTL help diff -ruw linux-5.4.60/drivers/char/hw_random/Kconfig linux-5.4.60-fbx/drivers/char/hw_random/Kconfig --- linux-5.4.60/drivers/char/hw_random/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/char/hw_random/Kconfig 2021-03-04 13:20:57.620838881 +0100 @@ -88,6 +88,11 @@ If unsure, say Y. +config HW_RANDOM_BCM63XX + tristate "Broadcom BCM63xx Random Number Generator support" + depends on ARCH_BCM_63XX || BCM63XX + default HW_RANDOM + config HW_RANDOM_IPROC_RNG200 tristate "Broadcom iProc/STB RNG200 support" depends on ARCH_BCM_IPROC || ARCH_BRCMSTB diff -ruw linux-5.4.60/drivers/char/hw_random/Makefile linux-5.4.60-fbx/drivers/char/hw_random/Makefile --- linux-5.4.60/drivers/char/hw_random/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/char/hw_random/Makefile 2021-03-04 13:20:57.620838881 +0100 @@ -28,6 +28,7 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o obj-$(CONFIG_HW_RANDOM_HISI) += hisi-rng.o obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o +obj-$(CONFIG_HW_RANDOM_BCM63XX) += bcm63xx-rng.o obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o diff -ruw linux-5.4.60/drivers/char/Kconfig linux-5.4.60-fbx/drivers/char/Kconfig --- linux-5.4.60/drivers/char/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/char/Kconfig 2021-03-04 13:20:57.617505548 +0100 @@ -26,6 +26,15 @@ kind of kernel debugging operations. When in doubt, say "N". +config DEVPHYSMEM + bool "/dev/physmem virtual device support" + default n + help + Say Y here if you want to support the /dev/physmem device. The + /dev/physmem device allows unprivileged access to physical memory + unused by the kernel. + When in doubt, say "N". + source "drivers/tty/serial/Kconfig" source "drivers/tty/serdev/Kconfig" diff -ruw linux-5.4.60/drivers/char/mem.c linux-5.4.60-fbx/drivers/char/mem.c --- linux-5.4.60/drivers/char/mem.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/char/mem.c 2021-03-04 13:20:57.624172215 +0100 @@ -29,6 +29,8 @@ #include #include #include +#include + #include #include #include @@ -434,6 +436,14 @@ return mmap_mem(file, vma); } +static int mmap_physmem(struct file * file, struct vm_area_struct * vma) +{ + if (vma->vm_pgoff < max_pfn && !capable(CAP_SYS_RAWIO)) + return -EPERM; + + return mmap_mem(file, vma); +} + /* * This function reads the *virtual* memory as seen by the kernel. */ @@ -870,6 +880,11 @@ return 0; } +static int open_physmem(struct inode * inode, struct file * filp) +{ + return 0; +} + #define zero_lseek null_lseek #define full_lseek null_lseek #define write_zero write_null @@ -935,6 +950,14 @@ .write = write_full, }; +static const struct file_operations __maybe_unused physmem_fops = { + .mmap = mmap_physmem, + .open = open_physmem, +#ifndef CONFIG_MMU + .get_unmapped_area = get_unmapped_area_mem, +#endif +}; + static const struct memdev { const char *name; umode_t mode; @@ -958,6 +981,9 @@ #ifdef CONFIG_PRINTK [11] = { "kmsg", 0644, &kmsg_fops, 0 }, #endif +#ifdef CONFIG_DEVPHYSMEM + [16] = { "physmem", 0, &physmem_fops, FMODE_UNSIGNED_OFFSET }, +#endif }; static int memory_open(struct inode *inode, struct file *filp) diff -ruw linux-5.4.60/drivers/cpufreq/Kconfig linux-5.4.60-fbx/drivers/cpufreq/Kconfig --- linux-5.4.60/drivers/cpufreq/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/cpufreq/Kconfig 2021-03-04 13:20:57.690838885 +0100 @@ -327,5 +327,10 @@ This adds the CPUFreq driver support for Freescale QorIQ SoCs which are capable of changing the CPU's frequency dynamically. +config BCM63158_CPUFREQ + tristate "CPU frequency scaling driver for BCM63158 SoC" + depends on ARCH_BCM63XX + endif + endmenu diff -ruw linux-5.4.60/drivers/cpufreq/Makefile linux-5.4.60-fbx/drivers/cpufreq/Makefile --- linux-5.4.60/drivers/cpufreq/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/cpufreq/Makefile 2021-03-04 13:20:57.690838885 +0100 @@ -111,3 +111,5 @@ obj-$(CONFIG_SPARC_US2E_CPUFREQ) += sparc-us2e-cpufreq.o obj-$(CONFIG_SPARC_US3_CPUFREQ) += sparc-us3-cpufreq.o obj-$(CONFIG_UNICORE32) += unicore2-cpufreq.o + +obj-$(CONFIG_BCM63158_CPUFREQ) += bcm63158-cpufreq.o diff -ruw linux-5.4.60/drivers/hid/hid-quirks.c linux-5.4.60-fbx/drivers/hid/hid-quirks.c --- linux-5.4.60/drivers/hid/hid-quirks.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/hid/hid-quirks.c 2021-03-04 13:20:58.437505585 +0100 @@ -684,6 +684,7 @@ #if IS_ENABLED(CONFIG_HID_ZYDACRON) { HID_USB_DEVICE(USB_VENDOR_ID_ZYDACRON, USB_DEVICE_ID_ZYDACRON_REMOTE_CONTROL) }, #endif + { HID_BLUETOOTH_DEVICE(0x10eb, 0x0023) }, { } }; diff -ruw linux-5.4.60/drivers/hid/Kconfig linux-5.4.60-fbx/drivers/hid/Kconfig --- linux-5.4.60/drivers/hid/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/hid/Kconfig 2021-03-04 13:20:58.430838917 +0100 @@ -439,6 +439,11 @@ help Support for ViewSonic/Signotec PD1011 signature pad. +config HID_FBX_REMOTE_AUDIO + tristate "Freebox BLE remote audio driver" + depends on HID && SND + select SND_PCM + config HID_GYRATION tristate "Gyration remote control" depends on HID diff -ruw linux-5.4.60/drivers/hid/Makefile linux-5.4.60-fbx/drivers/hid/Makefile --- linux-5.4.60/drivers/hid/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/hid/Makefile 2021-03-04 13:20:58.430838917 +0100 @@ -50,6 +50,7 @@ obj-$(CONFIG_HID_GFRM) += hid-gfrm.o obj-$(CONFIG_HID_GOOGLE_HAMMER) += hid-google-hammer.o obj-$(CONFIG_HID_GT683R) += hid-gt683r.o +obj-$(CONFIG_HID_FBX_REMOTE_AUDIO) += hid-fbx-remote-audio.o obj-$(CONFIG_HID_GYRATION) += hid-gyration.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-kbd.o obj-$(CONFIG_HID_HOLTEK) += hid-holtek-mouse.o diff -ruw linux-5.4.60/drivers/hwmon/adt7475.c linux-5.4.60-fbx/drivers/hwmon/adt7475.c --- linux-5.4.60/drivers/hwmon/adt7475.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/hwmon/adt7475.c 2021-03-04 13:20:58.450838918 +0100 @@ -128,7 +128,19 @@ /* Macro to read the registers */ -#define adt7475_read(reg) i2c_smbus_read_byte_data(client, (reg)) +static inline s32 __adt7475_read(const struct i2c_client *client, u8 cmd) +{ + s32 ret; + + ret = i2c_smbus_read_byte_data(client, cmd); + if (ret < 0) { + printk("__adt7475_read error: %d\n", ret); + return 0; + } + return ret; +} + +#define adt7475_read(reg) __adt7475_read(client, (reg)) /* Macros to easily index the registers */ diff -ruw linux-5.4.60/drivers/hwmon/Kconfig linux-5.4.60-fbx/drivers/hwmon/Kconfig --- linux-5.4.60/drivers/hwmon/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/hwmon/Kconfig 2021-03-04 13:20:58.447505585 +0100 @@ -1922,6 +1922,17 @@ If you say yes here you get support for the temperature and power sensors for APM X-Gene SoC. +config SENSORS_KIRKWOOD_CORETEMP + tristate "Kirkwood core temperature censor" + depends on MACH_KIRKWOOD + +config SENSORS_LD6710_FBX + tristate "LD6710 hardware monitoring driver (as seen on Freebox hardware)" + depends on I2C + +config SENSORS_AP806 + tristate "Marvell AP806/CP110 hardware monitoring driver" + if ACPI comment "ACPI drivers" diff -ruw linux-5.4.60/drivers/hwmon/Makefile linux-5.4.60-fbx/drivers/hwmon/Makefile --- linux-5.4.60/drivers/hwmon/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/hwmon/Makefile 2021-03-04 13:20:58.447505585 +0100 @@ -87,6 +87,7 @@ obj-$(CONFIG_SENSORS_JC42) += jc42.o obj-$(CONFIG_SENSORS_K8TEMP) += k8temp.o obj-$(CONFIG_SENSORS_K10TEMP) += k10temp.o +obj-$(CONFIG_SENSORS_LD6710_FBX) += ld6710-fbx.o obj-$(CONFIG_SENSORS_LINEAGE) += lineage-pem.o obj-$(CONFIG_SENSORS_LOCHNAGAR) += lochnagar-hwmon.o obj-$(CONFIG_SENSORS_LM63) += lm63.o @@ -177,6 +178,8 @@ obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o obj-$(CONFIG_SENSORS_XGENE) += xgene-hwmon.o +obj-$(CONFIG_SENSORS_KIRKWOOD_CORETEMP)+= kirkwood-coretemp.o +obj-$(CONFIG_SENSORS_AP806) += ap806-hwmon.o obj-$(CONFIG_SENSORS_OCC) += occ/ obj-$(CONFIG_PMBUS) += pmbus/ diff -ruw linux-5.4.60/drivers/i2c/busses/Kconfig linux-5.4.60-fbx/drivers/i2c/busses/Kconfig --- linux-5.4.60/drivers/i2c/busses/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/i2c/busses/Kconfig 2021-03-04 13:20:58.474172253 +0100 @@ -473,7 +473,7 @@ config I2C_BRCMSTB tristate "BRCM Settop/DSL I2C controller" depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM_63XX || \ - COMPILE_TEST + ARCH_BCM63XX || COMPILE_TEST default y help If you say yes to this option, support will be included for the @@ -1376,6 +1376,10 @@ to SLIMpro (On chip coprocessor) mailbox mechanism. If unsure, say N. +config I2C_WP3 + tristate "Wintegra WP3 I2C controll" + depends on WINTEGRA_WINPATH3 + config SCx200_ACB tristate "Geode ACCESS.bus support" depends on X86_32 && PCI diff -ruw linux-5.4.60/drivers/i2c/busses/Makefile linux-5.4.60-fbx/drivers/i2c/busses/Makefile --- linux-5.4.60/drivers/i2c/busses/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/i2c/busses/Makefile 2021-03-04 13:20:58.474172253 +0100 @@ -123,6 +123,7 @@ obj-$(CONFIG_I2C_XLP9XX) += i2c-xlp9xx.o obj-$(CONFIG_I2C_RCAR) += i2c-rcar.o obj-$(CONFIG_I2C_ZX2967) += i2c-zx2967.o +obj-$(CONFIG_I2C_WP3) += i2c-wp3.o # External I2C/SMBus adapter drivers obj-$(CONFIG_I2C_DIOLAN_U2C) += i2c-diolan-u2c.o diff -ruw linux-5.4.60/drivers/i2c/i2c-core-base.c linux-5.4.60-fbx/drivers/i2c/i2c-core-base.c --- linux-5.4.60/drivers/i2c/i2c-core-base.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/i2c/i2c-core-base.c 2021-03-04 13:20:58.487505587 +0100 @@ -223,12 +223,14 @@ bri->set_sda(adap, scl); ndelay(RECOVERY_NDELAY / 2); + if (0) { if (scl) { ret = i2c_generic_bus_free(adap); if (ret == 0) break; } } + } /* If we can't check bus status, assume recovery worked */ if (ret == -EOPNOTSUPP) diff -ruw linux-5.4.60/drivers/input/misc/Kconfig linux-5.4.60-fbx/drivers/input/misc/Kconfig --- linux-5.4.60/drivers/input/misc/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/input/misc/Kconfig 2021-03-04 13:20:58.604172259 +0100 @@ -894,4 +894,9 @@ To compile this driver as a module, choose M here: the module will be called stpmic1_onkey. +config INPUT_SMSC_CAP1066 + tristate "SMSC CAP1066 capacitive sensor driver" + select I2C + select INPUT_POLLDEV + endif diff -ruw linux-5.4.60/drivers/input/misc/Makefile linux-5.4.60-fbx/drivers/input/misc/Makefile --- linux-5.4.60/drivers/input/misc/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/input/misc/Makefile 2021-03-04 13:20:58.604172259 +0100 @@ -85,4 +85,4 @@ obj-$(CONFIG_INPUT_XEN_KBDDEV_FRONTEND) += xen-kbdfront.o obj-$(CONFIG_INPUT_YEALINK) += yealink.o obj-$(CONFIG_INPUT_IDEAPAD_SLIDEBAR) += ideapad_slidebar.o - +obj-$(CONFIG_INPUT_SMSC_CAP1066) += smsc_cap1066.o diff -ruw linux-5.4.60/drivers/Kconfig linux-5.4.60-fbx/drivers/Kconfig --- linux-5.4.60/drivers/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/Kconfig 2021-03-04 13:20:57.530838878 +0100 @@ -18,6 +18,8 @@ source "drivers/gnss/Kconfig" +source "drivers/fbxprocfs/Kconfig" + source "drivers/mtd/Kconfig" source "drivers/of/Kconfig" @@ -78,6 +80,10 @@ source "drivers/gpio/Kconfig" +source "drivers/fbxgpio/Kconfig" + +source "drivers/fbxjtag/Kconfig" + source "drivers/w1/Kconfig" source "drivers/power/Kconfig" @@ -86,6 +92,8 @@ source "drivers/thermal/Kconfig" +source "drivers/fbxwatchdog/Kconfig" + source "drivers/watchdog/Kconfig" source "drivers/ssb/Kconfig" diff -ruw linux-5.4.60/drivers/leds/Kconfig linux-5.4.60-fbx/drivers/leds/Kconfig --- linux-5.4.60/drivers/leds/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/leds/Kconfig 2021-03-04 13:20:58.647505594 +0100 @@ -823,6 +823,16 @@ Say Y to enable the LM36274 LED driver for TI LMU devices. This supports the LED device LM36274. +config LEDS_LED1202 + tristate "LED support for STMicroElectronics LED1202" + depends on LEDS_CLASS && I2C && OF + help + This option enables support for the LED1202 12-channel + LED driver. + + To compile this driver as a module, choose M here: the module + will be called leds-led1202. + comment "LED Triggers" source "drivers/leds/trigger/Kconfig" diff -ruw linux-5.4.60/drivers/leds/Makefile linux-5.4.60-fbx/drivers/leds/Makefile --- linux-5.4.60/drivers/leds/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/leds/Makefile 2021-03-04 13:20:58.647505594 +0100 @@ -85,6 +85,7 @@ obj-$(CONFIG_LEDS_TI_LMU_COMMON) += leds-ti-lmu-common.o obj-$(CONFIG_LEDS_LM3697) += leds-lm3697.o obj-$(CONFIG_LEDS_LM36274) += leds-lm36274.o +obj-$(CONFIG_LEDS_LED1202) += leds-led1202.o # LED SPI Drivers obj-$(CONFIG_LEDS_CR0014114) += leds-cr0014114.o diff -ruw linux-5.4.60/drivers/Makefile linux-5.4.60-fbx/drivers/Makefile --- linux-5.4.60/drivers/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/Makefile 2021-03-04 13:20:57.530838878 +0100 @@ -16,7 +16,9 @@ obj-$(CONFIG_GPIOLIB) += gpio/ obj-y += pwm/ +obj-$(CONFIG_FREEBOX_GPIO) += fbxgpio/ obj-y += pci/ +obj-$(CONFIG_FREEBOX_JTAG) += fbxjtag/ obj-$(CONFIG_PARISC) += parisc/ obj-$(CONFIG_RAPIDIO) += rapidio/ @@ -117,6 +119,7 @@ obj-y += power/ obj-$(CONFIG_HWMON) += hwmon/ obj-$(CONFIG_THERMAL) += thermal/ +obj-$(CONFIG_FREEBOX_WATCHDOG) += fbxwatchdog/ obj-$(CONFIG_WATCHDOG) += watchdog/ obj-$(CONFIG_MD) += md/ obj-$(CONFIG_BT) += bluetooth/ @@ -186,3 +189,5 @@ obj-$(CONFIG_GNSS) += gnss/ obj-$(CONFIG_INTERCONNECT) += interconnect/ obj-$(CONFIG_COUNTER) += counter/ + +obj-$(CONFIG_FREEBOX_PROCFS) += fbxprocfs/ diff -ruw linux-5.4.60/drivers/media/dvb-core/dvb_frontend.c linux-5.4.60-fbx/drivers/media/dvb-core/dvb_frontend.c --- linux-5.4.60/drivers/media/dvb-core/dvb_frontend.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/media/dvb-core/dvb_frontend.c 2021-03-04 13:20:58.687505596 +0100 @@ -807,6 +807,7 @@ if (fe->exit != DVB_FE_DEVICE_REMOVED) fe->exit = DVB_FE_NORMAL_EXIT; mb(); + wake_up_all(&fepriv->events.wait_queue); if (!fepriv->thread) return; @@ -2715,6 +2716,9 @@ poll_wait(file, &fepriv->events.wait_queue, wait); + if (fe->exit) + return POLLERR | POLLHUP; + if (fepriv->events.eventw != fepriv->events.eventr) return (EPOLLIN | EPOLLRDNORM | EPOLLPRI); diff -ruw linux-5.4.60/drivers/media/rc/keymaps/Makefile linux-5.4.60-fbx/drivers/media/rc/keymaps/Makefile --- linux-5.4.60/drivers/media/rc/keymaps/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/media/rc/keymaps/Makefile 2021-03-04 13:20:58.817505601 +0100 @@ -91,6 +91,7 @@ rc-pv951.o \ rc-hauppauge.o \ rc-rc6-mce.o \ + rc-rc6-freebox.o \ rc-real-audio-220-32-keys.o \ rc-reddo.o \ rc-snapstream-firefly.o \ diff -ruw linux-5.4.60/drivers/media/usb/dvb-usb/dib0700_devices.c linux-5.4.60-fbx/drivers/media/usb/dvb-usb/dib0700_devices.c --- linux-5.4.60/drivers/media/usb/dvb-usb/dib0700_devices.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/media/usb/dvb-usb/dib0700_devices.c 2021-03-04 13:20:58.840838936 +0100 @@ -3912,6 +3912,7 @@ { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_STK8096PVR) }, /* 85 */{ USB_DEVICE(USB_VID_HAMA, USB_PID_HAMA_DVBT_HYBRID) }, { USB_DEVICE(USB_VID_MICROSOFT, USB_PID_XBOX_ONE_TUNER) }, + { USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_HOOK_DEFAULT_STK7770P) }, { 0 } /* Terminating entry */ }; MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table); @@ -5154,6 +5155,30 @@ { NULL }, }, }, + }, { DIB0700_DEFAULT_DEVICE_PROPERTIES, + .num_adapters = 1, + .adapter = { + { + DIB0700_NUM_FRONTENDS(1), + .fe = {{ + .caps = DVB_USB_ADAP_HAS_PID_FILTER | DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF, + .pid_filter_count = 32, + .pid_filter = stk70x0p_pid_filter, + .pid_filter_ctrl = stk70x0p_pid_filter_ctrl, + .frontend_attach = stk7770p_frontend_attach, + .tuner_attach = dib7770p_tuner_attach, + + DIB0700_DEFAULT_STREAMING_CONFIG(0x02), + }}, + }, + }, + .num_device_descs = 1, + .devices = { + { "DiBcom STK7770P reference design no IR", + { &dib0700_usb_id_table[87], NULL }, + { NULL }, + }, + }, }, }; diff -ruw linux-5.4.60/drivers/mfd/Kconfig linux-5.4.60-fbx/drivers/mfd/Kconfig --- linux-5.4.60/drivers/mfd/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mfd/Kconfig 2021-03-04 13:20:58.880838938 +0100 @@ -1967,6 +1967,16 @@ This driver provides common support for accessing the device, additional drivers must be enabled in order to use the functionality of the device. +config MFD_FBXGW7R_PANEL + tristate "Freebox fbxgw7r panel support" + depends on FB + depends on SPI_MASTER + depends on OF + select FB_SYS_FOPS + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_DEFERRED_IO menu "Multimedia Capabilities Port drivers" depends on ARCH_SA1100 diff -ruw linux-5.4.60/drivers/mfd/Makefile linux-5.4.60-fbx/drivers/mfd/Makefile --- linux-5.4.60/drivers/mfd/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mfd/Makefile 2021-03-04 13:20:58.880838938 +0100 @@ -255,4 +255,5 @@ obj-$(CONFIG_MFD_ROHM_BD70528) += rohm-bd70528.o obj-$(CONFIG_MFD_ROHM_BD718XX) += rohm-bd718x7.o obj-$(CONFIG_MFD_STMFX) += stmfx.o +obj-$(CONFIG_MFD_FBXGW7R_PANEL) += fbxgw7r-panel.o diff -ruw linux-5.4.60/drivers/misc/eeprom/at24.c linux-5.4.60-fbx/drivers/misc/eeprom/at24.c --- linux-5.4.60/drivers/misc/eeprom/at24.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/misc/eeprom/at24.c 2021-03-04 13:20:58.904172272 +0100 @@ -566,7 +566,6 @@ struct at24_data *at24; struct regmap *regmap; bool writable; - u8 test_byte; int err; i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C); @@ -587,8 +586,10 @@ page_size = 1; flags = cdata->flags; +#ifndef CONFIG_NVMEM_IGNORE_RO if (device_property_present(dev, "read-only")) flags |= AT24_FLAG_READONLY; +#endif if (device_property_present(dev, "no-read-rollover")) flags |= AT24_FLAG_NO_RDROL; @@ -705,17 +706,6 @@ pm_runtime_set_active(dev); pm_runtime_enable(dev); - /* - * Perform a one-byte test read to verify that the - * chip is functional. - */ - err = at24_read(at24, 0, &test_byte, 1); - pm_runtime_idle(dev); - if (err) { - pm_runtime_disable(dev); - return -ENODEV; - } - dev_info(dev, "%u byte %s EEPROM, %s, %u bytes/write\n", byte_len, client->name, writable ? "writable" : "read-only", at24->write_max); diff -ruw linux-5.4.60/drivers/misc/eeprom/Kconfig linux-5.4.60-fbx/drivers/misc/eeprom/Kconfig --- linux-5.4.60/drivers/misc/eeprom/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/misc/eeprom/Kconfig 2021-03-04 13:20:58.904172272 +0100 @@ -129,4 +129,8 @@ This driver can also be built as a module. If so, the module will be called ee1004. +config EEPROM_EE1004_RAW + tristate "SPD EEPROMs on DDR4 memory modules (non smbus)" + depends on I2C && SYSFS + endmenu diff -ruw linux-5.4.60/drivers/misc/eeprom/Makefile linux-5.4.60-fbx/drivers/misc/eeprom/Makefile --- linux-5.4.60/drivers/misc/eeprom/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/misc/eeprom/Makefile 2021-03-04 13:20:58.904172272 +0100 @@ -8,3 +8,4 @@ obj-$(CONFIG_EEPROM_DIGSY_MTC_CFG) += digsy_mtc_eeprom.o obj-$(CONFIG_EEPROM_IDT_89HPESX) += idt_89hpesx.o obj-$(CONFIG_EEPROM_EE1004) += ee1004.o +obj-$(CONFIG_EEPROM_EE1004_RAW) += ee1004_raw.o diff -ruw linux-5.4.60/drivers/misc/Kconfig linux-5.4.60-fbx/drivers/misc/Kconfig --- linux-5.4.60/drivers/misc/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/misc/Kconfig 2021-03-04 13:20:58.900838939 +0100 @@ -5,6 +5,9 @@ menu "Misc devices" +config WINTEGRA_MMAP + bool "wintegra mmap driver" + config SENSORS_LIS3LV02D tristate depends on INPUT @@ -379,6 +382,18 @@ To compile this driver as a module, choose M here: the module will be called vmw_balloon. +config INTELCE_PIC16PMU + tristate "PIC16 PMU, LED, hwmon support" + select INPUT_POLLDEV + select NEW_LEDS + select I2C + select HWMON + select ARCH_REQUIRE_GPIOLIB + ---help--- + Freebox v6 HD PIC16 PMU interface support, enables + control of the on-board LEDs and reports the power status, + reset status and button status. + config PCH_PHUB tristate "Intel EG20T PCH/LAPIS Semicon IOH(ML7213/ML7223/ML7831) PHUB" select GENERIC_NET_UTILS @@ -400,6 +415,15 @@ To compile this driver as a module, choose M here: the module will be called pch_phub. +config FBXSERIAL_OF + bool "read fbxserial through DT chosen node" + depends on OF + select ARCH_HAS_FBXSERIAL + +config RANDOM_OF + bool "get Linux PRNG random through dt chosen node." + depends on OF + config LATTICE_ECP3_CONFIG tristate "Lattice ECP3 FPGA bitstream configuration via SPI" depends on SPI && SYSFS @@ -481,4 +505,6 @@ source "drivers/misc/ocxl/Kconfig" source "drivers/misc/cardreader/Kconfig" source "drivers/misc/habanalabs/Kconfig" +source "drivers/misc/remoti/Kconfig" +source "drivers/misc/hdmi-cec/Kconfig" endmenu diff -ruw linux-5.4.60/drivers/misc/Makefile linux-5.4.60-fbx/drivers/misc/Makefile --- linux-5.4.60/drivers/misc/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/misc/Makefile 2021-03-04 13:20:58.900838939 +0100 @@ -3,6 +3,7 @@ # Makefile for misc devices that really don't fit anywhere else. # +obj-$(CONFIG_WINTEGRA_MMAP) += wintegra_mmap.o obj-$(CONFIG_IBM_ASM) += ibmasm/ obj-$(CONFIG_IBMVMC) += ibmvmc.o obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot.o @@ -23,7 +24,10 @@ obj-$(CONFIG_SENSORS_APDS990X) += apds990x.o obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o obj-$(CONFIG_KGDB_TESTS) += kgdbts.o +obj-$(CONFIG_FBXSERIAL_OF) += fbxserial_of.o +obj-$(CONFIG_RANDOM_OF) += random_of.o obj-$(CONFIG_SGI_XP) += sgi-xp/ +obj-$(CONFIG_INTELCE_PIC16PMU) += pic16-pmu.o obj-$(CONFIG_SGI_GRU) += sgi-gru/ obj-$(CONFIG_CS5535_MFGPT) += cs5535-mfgpt.o obj-$(CONFIG_HP_ILO) += hpilo.o @@ -38,6 +42,7 @@ obj-y += cb710/ obj-$(CONFIG_VMWARE_BALLOON) += vmw_balloon.o obj-$(CONFIG_PCH_PHUB) += pch_phub.o +obj-y += hdmi-cec/ obj-y += ti-st/ obj-y += lis3lv02d/ obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/ @@ -57,3 +62,4 @@ obj-$(CONFIG_PVPANIC) += pvpanic.o obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o +obj-y += remoti/ diff -ruw linux-5.4.60/drivers/mmc/core/block.c linux-5.4.60-fbx/drivers/mmc/core/block.c --- linux-5.4.60/drivers/mmc/core/block.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mmc/core/block.c 2021-03-04 13:20:58.930838940 +0100 @@ -2319,7 +2319,7 @@ md->parent = parent; set_disk_ro(md->disk, md->read_only || default_ro); md->disk->flags = GENHD_FL_EXT_DEVT; - if (area_type & (MMC_BLK_DATA_AREA_RPMB | MMC_BLK_DATA_AREA_BOOT)) + if (area_type & (MMC_BLK_DATA_AREA_RPMB)) md->disk->flags |= GENHD_FL_NO_PART_SCAN | GENHD_FL_SUPPRESS_PARTITION_INFO; diff -ruw linux-5.4.60/drivers/mmc/host/Kconfig linux-5.4.60-fbx/drivers/mmc/host/Kconfig --- linux-5.4.60/drivers/mmc/host/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mmc/host/Kconfig 2021-03-04 13:20:58.934172273 +0100 @@ -976,7 +976,7 @@ config MMC_SDHCI_BRCMSTB tristate "Broadcom SDIO/SD/MMC support" - depends on ARCH_BRCMSTB || BMIPS_GENERIC + depends on ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM63XX depends on MMC_SDHCI_PLTFM default y help diff -ruw linux-5.4.60/drivers/mmc/host/sdhci-brcmstb.c linux-5.4.60-fbx/drivers/mmc/host/sdhci-brcmstb.c --- linux-5.4.60/drivers/mmc/host/sdhci-brcmstb.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mmc/host/sdhci-brcmstb.c 2021-03-04 13:20:58.940838940 +0100 @@ -82,6 +82,7 @@ static const struct of_device_id sdhci_brcm_of_match[] = { { .compatible = "brcm,bcm7425-sdhci" }, { .compatible = "brcm,bcm7445-sdhci" }, + { .compatible = "brcm,bcm63xx-sdhci" }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); diff -ruw linux-5.4.60/drivers/mtd/Kconfig linux-5.4.60-fbx/drivers/mtd/Kconfig --- linux-5.4.60/drivers/mtd/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/Kconfig 2021-03-04 13:20:58.947505608 +0100 @@ -23,6 +23,9 @@ WARNING: some of the tests will ERASE entire MTD device which they test. Do not use these tests unless you really know what you do. +config MTD_ERASE_PRINTK + bool "write to kernel log when a block is erased" + menu "Partition parsers" source "drivers/mtd/parsers/Kconfig" endmenu diff -ruw linux-5.4.60/drivers/mtd/mtdchar.c linux-5.4.60-fbx/drivers/mtd/mtdchar.c --- linux-5.4.60/drivers/mtd/mtdchar.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/mtdchar.c 2021-03-04 13:20:58.954172274 +0100 @@ -176,6 +176,7 @@ { struct mtd_oob_ops ops; + memset(&ops, 0, sizeof (ops)); ops.mode = MTD_OPS_RAW; ops.datbuf = kbuf; ops.oobbuf = NULL; @@ -270,6 +271,7 @@ { struct mtd_oob_ops ops; + memset(&ops, 0, sizeof (ops)); ops.mode = MTD_OPS_RAW; ops.datbuf = kbuf; ops.oobbuf = NULL; @@ -753,6 +755,11 @@ erase->len = einfo32.length; } +#ifdef CONFIG_MTD_ERASE_PRINTK + printk(KERN_DEBUG "mtd: %s: ERASE offset=@%08llx\n", + mtd->name, erase->addr); +#endif + ret = mtd_erase(mtd, erase); kfree(erase); } diff -ruw linux-5.4.60/drivers/mtd/mtdcore.c linux-5.4.60-fbx/drivers/mtd/mtdcore.c --- linux-5.4.60/drivers/mtd/mtdcore.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/mtdcore.c 2021-03-04 13:20:58.954172274 +0100 @@ -307,6 +307,43 @@ } static DEVICE_ATTR(bbt_blocks, S_IRUGO, mtd_bbtblocks_show, NULL); +static ssize_t mtd_nand_type_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mtd->nand_type); +} +static DEVICE_ATTR(nand_type, S_IRUGO, mtd_nand_type_show, NULL); + +static ssize_t mtd_nand_manufacturer_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", mtd->nand_manufacturer); +} +static DEVICE_ATTR(nand_manufacturer, S_IRUGO, mtd_nand_manufacturer_show, NULL); + +static ssize_t mtd_nand_onfi_ecc_bits_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%d\n", mtd->onfi_ecc_bits); +} +static DEVICE_ATTR(onfi_ecc_bits, S_IRUGO, mtd_nand_onfi_ecc_bits_show, NULL); + +static ssize_t mtd_nand_onfi_model_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct mtd_info *mtd = dev_get_drvdata(dev); + + return snprintf(buf, PAGE_SIZE, "%s\n", + mtd->onfi_model ? mtd->onfi_model : "unknown"); +} +static DEVICE_ATTR(onfi_model, S_IRUGO, mtd_nand_onfi_model_show, NULL); + static struct attribute *mtd_attrs[] = { &dev_attr_type.attr, &dev_attr_flags.attr, @@ -325,6 +362,10 @@ &dev_attr_bad_blocks.attr, &dev_attr_bbt_blocks.attr, &dev_attr_bitflip_threshold.attr, + &dev_attr_nand_type.attr, + &dev_attr_nand_manufacturer.attr, + &dev_attr_onfi_ecc_bits.attr, + &dev_attr_onfi_model.attr, NULL, }; ATTRIBUTE_GROUPS(mtd); diff -ruw linux-5.4.60/drivers/mtd/mtdpart.c linux-5.4.60-fbx/drivers/mtd/mtdpart.c --- linux-5.4.60/drivers/mtd/mtdpart.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/mtdpart.c 2021-03-04 13:20:58.954172274 +0100 @@ -350,6 +350,10 @@ slave->mtd.oobavail = parent->oobavail; slave->mtd.subpage_sft = parent->subpage_sft; slave->mtd.pairing = parent->pairing; + slave->mtd.nand_type = parent->nand_type; + slave->mtd.nand_manufacturer = parent->nand_manufacturer; + slave->mtd.onfi_ecc_bits = parent->onfi_ecc_bits; + slave->mtd.onfi_model = parent->onfi_model; slave->mtd.name = name; slave->mtd.owner = parent->owner; diff -ruw linux-5.4.60/drivers/mtd/nand/raw/Kconfig linux-5.4.60-fbx/drivers/mtd/nand/raw/Kconfig --- linux-5.4.60/drivers/mtd/nand/raw/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/nand/raw/Kconfig 2021-03-04 13:20:58.957505608 +0100 @@ -34,6 +34,14 @@ comment "Raw/parallel NAND flash controllers" +config MTD_FORCE_BAD_BLOCK_ERASE + bool "Force erase on bad blocks (useful for bootloader parts)" + default n + help + Enable this option only when you need to force an erase on + blocks being marked as "bad" by Linux (i.e: other ECC/bad block + marker layout). + config MTD_NAND_DENALI tristate @@ -53,6 +61,10 @@ Enable the driver for NAND flash on platforms using a Denali NAND controller as a DT device. +config MTD_NAND_DENALI_FBX + tristate "NAND Denali controller support" + depends on PCI + config MTD_NAND_AMS_DELTA tristate "Amstrad E3 NAND controller" depends on MACH_AMS_DELTA || COMPILE_TEST diff -ruw linux-5.4.60/drivers/mtd/nand/raw/Makefile linux-5.4.60-fbx/drivers/mtd/nand/raw/Makefile --- linux-5.4.60/drivers/mtd/nand/raw/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/nand/raw/Makefile 2021-03-04 13:20:58.957505608 +0100 @@ -10,6 +10,7 @@ obj-$(CONFIG_MTD_NAND_DENALI) += denali.o obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o +obj-$(CONFIG_MTD_NAND_DENALI_FBX) += denali_nand.o obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o obj-$(CONFIG_MTD_NAND_TANGO) += tango_nand.o diff -ruw linux-5.4.60/drivers/mtd/parsers/Kconfig linux-5.4.60-fbx/drivers/mtd/parsers/Kconfig --- linux-5.4.60/drivers/mtd/parsers/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/parsers/Kconfig 2021-03-04 13:20:58.967505609 +0100 @@ -67,6 +67,10 @@ flash memory node, as described in Documentation/devicetree/bindings/mtd/partition.txt. +config MTD_OF_PARTS_IGNORE_RO + bool "ignore read-only flag" + depends on MTD_OF_PARTS + config MTD_PARSER_IMAGETAG tristate "Parser for BCM963XX Image Tag format partitions" depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST @@ -160,3 +164,14 @@ 'FIS directory' images, enable this option. endif # MTD_REDBOOT_PARTS + +config MTD_FBX6HD_PARTS + tristate "Freebox V6 HD partitioning support" + help + Freebox V6 HD partitioning support + +config MTD_FBX6HD_PARTS_WRITE_ALL + bool "make all partitions writeable" + depends on MTD_FBX6HD_PARTS + help + Freebox V6 HD partitions support diff -ruw linux-5.4.60/drivers/mtd/parsers/Makefile linux-5.4.60-fbx/drivers/mtd/parsers/Makefile --- linux-5.4.60/drivers/mtd/parsers/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/parsers/Makefile 2021-03-04 13:20:58.967505609 +0100 @@ -9,3 +9,4 @@ obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o +obj-$(CONFIG_MTD_FBX6HD_PARTS) += fbx6hd-mtdparts.o diff -ruw linux-5.4.60/drivers/mtd/parsers/ofpart.c linux-5.4.60-fbx/drivers/mtd/parsers/ofpart.c --- linux-5.4.60/drivers/mtd/parsers/ofpart.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/parsers/ofpart.c 2021-03-04 13:20:58.967505609 +0100 @@ -111,8 +111,10 @@ partname = of_get_property(pp, "name", &len); parts[i].name = partname; +#ifndef CONFIG_MTD_OF_PARTS_IGNORE_RO if (of_get_property(pp, "read-only", &len)) parts[i].mask_flags |= MTD_WRITEABLE; +#endif if (of_get_property(pp, "lock", &len)) parts[i].mask_flags |= MTD_POWERUP_LOCK; diff -ruw linux-5.4.60/drivers/mtd/spi-nor/spi-nor.c linux-5.4.60-fbx/drivers/mtd/spi-nor/spi-nor.c --- linux-5.4.60/drivers/mtd/spi-nor/spi-nor.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/mtd/spi-nor/spi-nor.c 2021-03-04 13:20:58.970838942 +0100 @@ -178,6 +178,7 @@ struct flash_info { char *name; + uint32_t ext_id; /* * This array stores the ID bytes. @@ -196,7 +197,8 @@ u16 page_size; u16 addr_width; - u16 flags; + u32 flags; + #define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */ #define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */ #define SST_WRITE BIT(2) /* use SST byte programming */ @@ -234,6 +236,9 @@ #define USE_CLSR BIT(14) /* use CLSR command */ #define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */ +#define ALT_PROBE BIT(16) /* only match during alt_probe */ +#define ALT_PROBE_ATMEL BIT(17) /* only match during alt_probe_atmel */ + /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups; }; @@ -2033,6 +2038,7 @@ /* Used when the "_ext_id" is two bytes at most */ #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + .ext_id = (_ext_id), \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -2047,6 +2053,7 @@ .flags = (_flags), #define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ + .ext_id = (_ext_id), \ .id = { \ ((_jedec_id) >> 16) & 0xff, \ ((_jedec_id) >> 8) & 0xff, \ @@ -2503,6 +2510,22 @@ /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ { "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + + /* Used on Freebox Gateways ... */ + + /* Atmel */ + { "at25f512b", INFO(0x1f6500, 0x1f65, 32 * 1024, 2, + ALT_PROBE_ATMEL) }, + /* Macronix */ + { "mx25l512", INFO(0xc20500, 0xc205, 64 * 1024, 1, + ALT_PROBE | SECT_4K) }, + /* SST */ + { "sst25vf512a", INFO(0xbf4800, 0xbf48, 32 * 1024, 2, ALT_PROBE) }, + + /* EON */ + { "en25f05", INFO(0x1c0500, 0x1c05, 64 * 1024, 1, + ALT_PROBE | SECT_4K) }, + { }, }; @@ -2541,6 +2564,69 @@ return ERR_PTR(-ENODEV); } +static const struct flash_info *spi_nor_alt_read_id(struct spi_nor *nor) +{ + u8 data[2]; + u16 id; + int err, tmp; + const struct flash_info *info; + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID_ALT, 1), + SPI_MEM_OP_ADDR(3, 0, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(sizeof (data), data, 1)); + + BUG_ON(!nor->spimem); + + err = spi_mem_exec_op(nor->spimem, &op); + if (err < 0) { + dev_err(nor->dev, "error %d reading alt ID\n", err); + return ERR_PTR(err); + } + + id = (data[1] << 8) | data[0]; + + for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { + info = &spi_nor_ids[tmp]; + if ((info->flags & ALT_PROBE) && (info->ext_id == id)) + return info; + } + + dev_err(nor->dev, "unrecognized ALT id %04x\n", id); + return ERR_PTR(-ENODEV); +} + +static const struct flash_info *spi_nor_atmel_id(struct spi_nor *nor) +{ + u8 data[2]; + u16 id; + int err, tmp; + const struct flash_info *info; + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(0x15, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_IN(sizeof (data), data, 1)); + + BUG_ON(!nor->spimem); + + err = spi_mem_exec_op(nor->spimem, &op); + if (err < 0) { + dev_err(nor->dev, "error %d reading atmel ID\n", err); + return ERR_PTR(err); + } + id = (data[1] << 8) | data[0]; + + for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) { + info = &spi_nor_ids[tmp]; + if ((info->flags & ALT_PROBE_ATMEL) && (info->ext_id == id)) + return info; + } + + dev_err(nor->dev, "unrecognized ATMEL id %04x\n", id); + return ERR_PTR(-ENODEV); +} + static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { @@ -4746,6 +4832,19 @@ return NULL; } +static void sst_write_enable(struct spi_nor *nor) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_EWRSR, 1), + SPI_MEM_OP_NO_ADDR, + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); + write_enable(nor); + BUG_ON(!nor->spimem); + spi_mem_exec_op(nor->spimem, &op); + write_sr(nor, 0); +} + static int spi_nor_set_addr_width(struct spi_nor *nor) { if (nor->addr_width) { @@ -4803,6 +4902,12 @@ if (name && info->id_len) { const struct flash_info *jinfo; + jinfo = spi_nor_alt_read_id(nor); + if (IS_ERR(jinfo)) + /* try ATMEL */ + jinfo = spi_nor_atmel_id(nor); + if (IS_ERR(jinfo)) + /* try JEDEC */ jinfo = spi_nor_read_id(nor); if (IS_ERR(jinfo)) { return jinfo; @@ -4891,6 +4996,9 @@ /* Init flash parameters based on flash_info struct and SFDP */ spi_nor_init_params(nor); + if (info->ext_id == 0xbf48) + sst_write_enable(nor); + if (!mtd->name) mtd->name = dev_name(dev); mtd->priv = nor; diff -ruw linux-5.4.60/drivers/net/ethernet/broadcom/Kconfig linux-5.4.60-fbx/drivers/net/ethernet/broadcom/Kconfig --- linux-5.4.60/drivers/net/ethernet/broadcom/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/Kconfig 2021-03-04 13:20:59.017505610 +0100 @@ -60,6 +60,45 @@ This driver supports the ethernet MACs in the Broadcom 63xx MIPS chipset family (BCM63XX). +config BCM63XX_ENET_RUNNER + tristate "Broadcom 63xx (63138) runner ethernet support" + select MII + select FIXED_PHY + select PHYLIB + select BCM7XXX_PHY + select BROADCOM_PHY + select SOC_BCM63XX_RDP + +config BCM63158_SF2 + tristate "Broadcom 63158 SF2 support" + select MII + select PHYLINK + select BCM7XXX_PHY + select BROADCOM_PHY + select NET_DSA + select NET_DSA_TAG_BRCM_FBX + +config BCM63158_SYSTEMPORT + tristate "Broadcom 63158 SYSTEMPORT internal MAC support" + depends on OF + select MII + select PHYLINK + +config BCM63158_ENET_RUNNER + tristate "Broadcom 63158 runner ethernet support" + select MII + select PHYLINK + select SOC_BCM63XX_XRDP + +config BCM63158_ENET_RUNNER_FF + bool "fastpath support for freebox boards" + depends on BCM63158_ENET_RUNNER + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config BCMGENET tristate "Broadcom GENET internal MAC support" depends on HAS_IOMEM diff -ruw linux-5.4.60/drivers/net/ethernet/broadcom/Makefile linux-5.4.60-fbx/drivers/net/ethernet/broadcom/Makefile --- linux-5.4.60/drivers/net/ethernet/broadcom/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/Makefile 2021-03-04 13:20:59.017505610 +0100 @@ -16,3 +16,5 @@ obj-$(CONFIG_BGMAC_PLATFORM) += bgmac-platform.o obj-$(CONFIG_SYSTEMPORT) += bcmsysport.o obj-$(CONFIG_BNXT) += bnxt/ +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_enet_runner/ +obj-y += bcm63158/ diff -ruw linux-5.4.60/drivers/net/ethernet/Kconfig linux-5.4.60-fbx/drivers/net/ethernet/Kconfig --- linux-5.4.60/drivers/net/ethernet/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/ethernet/Kconfig 2021-03-04 13:20:58.997505609 +0100 @@ -180,6 +180,7 @@ source "drivers/net/ethernet/tundra/Kconfig" source "drivers/net/ethernet/via/Kconfig" source "drivers/net/ethernet/wiznet/Kconfig" +source "drivers/net/ethernet/wintegra/Kconfig" source "drivers/net/ethernet/xilinx/Kconfig" source "drivers/net/ethernet/xircom/Kconfig" diff -ruw linux-5.4.60/drivers/net/ethernet/Makefile linux-5.4.60-fbx/drivers/net/ethernet/Makefile --- linux-5.4.60/drivers/net/ethernet/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/ethernet/Makefile 2021-03-04 13:20:58.997505609 +0100 @@ -92,6 +92,7 @@ obj-$(CONFIG_NET_VENDOR_TUNDRA) += tundra/ obj-$(CONFIG_NET_VENDOR_VIA) += via/ obj-$(CONFIG_NET_VENDOR_WIZNET) += wiznet/ +obj-$(CONFIG_NET_VENDOR_WINTEGRA) += wintegra/ obj-$(CONFIG_NET_VENDOR_XILINX) += xilinx/ obj-$(CONFIG_NET_VENDOR_XIRCOM) += xircom/ obj-$(CONFIG_NET_VENDOR_SYNOPSYS) += synopsys/ diff -ruw linux-5.4.60/drivers/net/ethernet/marvell/Kconfig linux-5.4.60-fbx/drivers/net/ethernet/marvell/Kconfig --- linux-5.4.60/drivers/net/ethernet/marvell/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/ethernet/marvell/Kconfig 2021-03-04 13:20:59.164172284 +0100 @@ -23,6 +23,7 @@ depends on INET select PHYLIB select MVMDIO + select MII ---help--- This driver supports the gigabit ethernet MACs in the Marvell Discovery PPC/MIPS chipset family (MV643XX) and @@ -31,6 +32,15 @@ Some boards that use the Discovery chipset are the Momenco Ocelot C and Jaguar ATX and Pegasos II. +config MV643XX_ETH_FBX_FF + bool "fastpath support for freebox boards" + depends on MV643XX_ETH + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config MVMDIO tristate "Marvell MDIO interface support" depends on HAS_IOMEM @@ -86,10 +96,20 @@ depends on ARCH_MVEBU || COMPILE_TEST select MVMDIO select PHYLINK + select MII ---help--- This driver supports the network interface units in the Marvell ARMADA 375, 7K and 8K SoCs. +config MVPP2_FBX_FF + bool "fastpath support for freebox boards" + depends on MVPP2 + select IP_FFN + select IPV6_FFN + select IPV6_SIT_6RD + select BRIDGE + select FBXBRIDGE + config PXA168_ETH tristate "Marvell pxa168 ethernet support" depends on HAS_IOMEM diff -ruw linux-5.4.60/drivers/net/phy/aquantia_main.c linux-5.4.60-fbx/drivers/net/phy/aquantia_main.c --- linux-5.4.60/drivers/net/phy/aquantia_main.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/aquantia_main.c 2021-03-04 13:20:59.287505623 +0100 @@ -12,6 +12,7 @@ #include #include #include +#include #include "aquantia.h" @@ -20,6 +21,7 @@ #define PHY_ID_AQR105 0x03a1b4a2 #define PHY_ID_AQR106 0x03a1b4d0 #define PHY_ID_AQR107 0x03a1b4e0 +#define PHY_ID_AQR112 0x31c31d12 #define PHY_ID_AQCS109 0x03a1b5c2 #define PHY_ID_AQR405 0x03a1b4b0 @@ -34,6 +36,8 @@ #define MDIO_AN_VEND_PROV 0xc400 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) +#define MDIO_AN_VEND_PROV_AQ5000BASET_FULL BIT(11) +#define MDIO_AN_VEND_PROV_AQ2500BASET_FULL BIT(10) #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 @@ -87,6 +91,27 @@ #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) +#define VEND1_GLOBAL_MAILBOX_CONTROL 0x0200 +#define VEND1_GLOBAL_MAILBOX_EXECUTE BIT(15) +#define VEND1_GLOBAL_MAILBOX_WRITE BIT(14) +#define VEND1_GLOBAL_MAILBOX_RESET_CRC BIT(12) +#define VEND1_GLOBAL_MAILBOX_BUSY BIT(8) + +#define VEND1_GLOBAL_MAILBOX_CRC 0x0201 + +#define VEND1_GLOBAL_MAILBOX_ADDR_MSW 0x0202 +#define VEND1_GLOBAL_MAILBOX_ADDR_LSW 0x0203 + +#define VEND1_GLOBAL_MAILBOX_DATA_MSW 0x0204 +#define VEND1_GLOBAL_MAILBOX_DATA_LSW 0x0205 + +#define VEND1_GLOBAL_UP_CONTROL 0xc001 +#define VEND1_GLOBAL_UP_RESET BIT(15) +#define VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE BIT(6) +#define VEND1_GLOBAL_UP_RUN_STALL BIT(0) + +#define VEND1_GLOBAL_FAULT 0xc850 + #define VEND1_GLOBAL_RSVD_STAT1 0xc885 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) @@ -121,6 +146,23 @@ #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) +/* addresses of memory segments in the phy */ +#define DRAM_BASE_ADDR 0x3FFE0000 +#define IRAM_BASE_ADDR 0x40000000 + +/* firmware image format constants */ +#define VERSION_STRING_SIZE 0x40 +#define VERSION_STRING_OFFSET 0x0200 +#define HEADER_OFFSET 0x300 + +struct aqr_fw_header { + u8 padding[4]; + u8 iram_offset[3]; + u8 iram_size[3]; + u8 dram_offset[3]; + u8 dram_size[3]; +}; + struct aqr107_hw_stat { const char *name; int reg; @@ -230,9 +272,22 @@ phydev->advertising)) reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; + /* + * set the corresponding bits for 2.5G & 5G in proprietary + * NBASE-T mode (called aqrates) + */ + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, + phydev->advertising)) + reg |= MDIO_AN_VEND_PROV_AQ2500BASET_FULL; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + phydev->advertising)) + reg |= MDIO_AN_VEND_PROV_AQ5000BASET_FULL; + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, MDIO_AN_VEND_PROV_1000BASET_HALF | - MDIO_AN_VEND_PROV_1000BASET_FULL, reg); + MDIO_AN_VEND_PROV_1000BASET_FULL | + MDIO_AN_VEND_PROV_AQ2500BASET_FULL | + MDIO_AN_VEND_PROV_AQ5000BASET_FULL, reg); if (ret < 0) return ret; if (ret > 0) @@ -344,6 +399,7 @@ static int aqr107_read_status(struct phy_device *phydev) { int val, ret; + bool use_custom_rates; ret = aqr_read_status(phydev); if (ret) @@ -375,13 +431,21 @@ break; } + val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); + if (val < 0) + return val; + + use_custom_rates = (val & (MDIO_AN_VEND_PROV_AQ2500BASET_FULL | + MDIO_AN_VEND_PROV_AQ5000BASET_FULL)); + + if (!use_custom_rates) { val = aqr107_read_downshift_event(phydev); if (val <= 0) return val; - phydev_warn(phydev, "Downshift occurred! Cabling may be defective.\n"); - /* Read downshifted rate from vendor register */ + } + return aqr107_read_rate(phydev); } @@ -480,7 +544,7 @@ build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); - phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", + phydev_info(phydev, "FW %u.%u, Build %u, Provisioning %u\n", fw_major, fw_minor, build_id, prov_id); } @@ -509,6 +573,265 @@ return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); } +static const u16 _crc16_lookuptable[256] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0 +}; + +static u16 crc16_ccitt(u16 crc, const u8 *buf, size_t len) +{ + while (len--) { + crc = ((crc << 8) ^ _crc16_lookuptable[((crc >> 8) ^ + ((*buf++) & 0x00FF))]); + } + return crc; +} + +/* load data into the phy's memory */ +static int aqr112_load_chunk(struct phy_device *phydev, uint32_t addr, + const uint8_t *data, size_t len) +{ + u16 crc = 0; + int up_crc; + size_t pos; + int err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_CONTROL, + VEND1_GLOBAL_MAILBOX_RESET_CRC); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_ADDR_MSW, addr >> 16); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_ADDR_LSW, addr & 0xfffc); + if (err < 0) + return err; + + for (pos = 0; pos < len; pos += min_t(u32, sizeof(u32), len - pos)) { + u32 word = 0; + + memcpy(&word, &data[pos], min_t(u32, sizeof(u32), len - pos)); + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_DATA_MSW, + word >> 16); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_DATA_LSW, + word & 0xffff); + if (err < 0) + return err; + + err = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_CONTROL, + (VEND1_GLOBAL_MAILBOX_EXECUTE | + VEND1_GLOBAL_MAILBOX_WRITE)); + if (err < 0) + return err; + + /* keep a big endian CRC to match the phy processor */ + word = cpu_to_be32(word); + crc = crc16_ccitt(crc, (uint8_t *)&word, sizeof(word)); + } + + up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_MAILBOX_CRC); + if (up_crc < 0) + return up_crc; + + if (crc != up_crc) { + dev_err(&phydev->mdio.dev, + "crc mismatch: calculated 0x%04hx phy 0x%04hx\n", + crc, up_crc); + return -EIO; + } + return 0; +} + +static u32 unpack_u24(const u8 *data) +{ + return (data[2] << 16) + (data[1] << 8) + data[0]; +} + +static int aqr112_upload_firmware(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + const struct firmware *fw; + const struct aqr_fw_header *header; + char file_name[64]; + char version[VERSION_STRING_SIZE + 1]; + u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size; + u16 calculated_crc, read_crc; + int ret; + + scnprintf(file_name, sizeof (file_name), "aquantia_phy/fw.uc"); + ret = request_firmware_direct(&fw, file_name, dev); + if (ret) { + dev_err(dev, "failed to load firmware %s, ret: %d\n", + file_name, ret); + return ret; + } + + if (fw->size < 16) { + dev_err(dev, "firmware too small\n"); + ret = -EINVAL; + goto fail; + } + + read_crc = (fw->data[fw->size - 2] << 8) | fw->data[fw->size - 1]; + calculated_crc = crc16_ccitt(0, fw->data, fw->size - 2); + if (read_crc != calculated_crc) { + dev_err(dev, "bad firmware crc: file 0x%04x " + "calculated 0x%04x\n", + read_crc, calculated_crc); + ret = -EINVAL; + goto fail; + } + + /* Find the DRAM and IRAM sections within the firmware file. */ + primary_offset = ((fw->data[9] & 0xf) << 8 | fw->data[8]) << 12; + header = (const struct aqr_fw_header *) + &fw->data[primary_offset + HEADER_OFFSET]; + + iram_offset = primary_offset + unpack_u24(header->iram_offset); + iram_size = unpack_u24(header->iram_size); + + dram_offset = primary_offset + unpack_u24(header->dram_offset); + dram_size = unpack_u24(header->dram_size); + + strlcpy(version, + (char *)&fw->data[dram_offset + VERSION_STRING_OFFSET], + VERSION_STRING_SIZE); + version[VERSION_STRING_SIZE] = 0; + + dev_info(dev, "loading firmare version '%s'...\n", version); + + /* stall the microcprocessor */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_UP_CONTROL, + (VEND1_GLOBAL_UP_RUN_STALL | + VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE)); + if (ret < 0) + goto fail; + + ret = aqr112_load_chunk(phydev, DRAM_BASE_ADDR, + &fw->data[dram_offset], + dram_size); + if (ret) + goto fail; + + ret = aqr112_load_chunk(phydev, IRAM_BASE_ADDR, + &fw->data[iram_offset], + iram_size); + if (ret) + goto fail; + + /* make sure soft reset and low power mode are clear */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0, 0); + if (ret) + goto fail; + + /* Release the microprocessor. UP_RESET must be held for 100 usec. */ + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_UP_CONTROL, + (VEND1_GLOBAL_UP_RUN_STALL | + VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE | + VEND1_GLOBAL_UP_RESET)); + if (ret) + goto fail; + + msleep(10); + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, + VEND1_GLOBAL_UP_CONTROL, + VEND1_GLOBAL_UP_RUN_STALL_OVERRIDE); + if (ret) + goto fail; + + ret = 0; + +fail: + release_firmware(fw); + return ret; +} + +static int aqr112_config_init(struct phy_device *phydev) +{ + int ret; + + /* Check that the PHY interface type is compatible */ + if (phydev->interface != PHY_INTERFACE_MODE_NA && + phydev->interface != PHY_INTERFACE_MODE_SGMII && + phydev->interface != PHY_INTERFACE_MODE_2500BASEX) { + phydev_err(phydev, "requested interface mode not supp\n"); + return -ENODEV; + } + + ret = aqr112_upload_firmware(phydev); + if (ret) + return ret; + + aqr107_wait_reset_complete(phydev); + aqr107_chip_info(phydev); + + /* ensure that a latched downshift event is cleared */ + aqr107_read_downshift_event(phydev); + + return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); +} + +static int aqr112_get_features(struct phy_device *phydev) +{ + int ret; + + ret = genphy_c45_pma_read_abilities(phydev); + if (ret) + return ret; + + ret = phy_set_max_speed(phydev, SPEED_2500); + if (ret) + return ret; + + return 0; +} + static int aqcs109_config_init(struct phy_device *phydev) { int ret; @@ -657,6 +980,20 @@ .link_change_notify = aqr107_link_change_notify, }, { + PHY_ID_MATCH_MODEL(PHY_ID_AQR112), + .name = "Aquantia AQR112", + .probe = aqr107_probe, + .config_init = aqr112_config_init, + .config_aneg = aqr_config_aneg, + .read_status = aqr107_read_status, + .get_features = aqr112_get_features, + .suspend = aqr107_suspend, + .resume = aqr107_resume, + .get_sset_count = aqr107_get_sset_count, + .get_strings = aqr107_get_strings, + .get_stats = aqr107_get_stats, +}, +{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), .name = "Aquantia AQCS109", .probe = aqr107_probe, @@ -692,6 +1029,7 @@ { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, + { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, { } diff -ruw linux-5.4.60/drivers/net/phy/bcm7xxx.c linux-5.4.60-fbx/drivers/net/phy/bcm7xxx.c --- linux-5.4.60/drivers/net/phy/bcm7xxx.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/bcm7xxx.c 2021-03-04 13:20:59.287505623 +0100 @@ -39,6 +39,7 @@ struct bcm7xxx_phy_priv { u64 *stats; + bool printed; }; static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev) @@ -136,6 +137,7 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev) { + struct bcm7xxx_phy_priv *priv = phydev->priv; u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags); u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags); u8 count; @@ -147,8 +149,11 @@ if (rev == 0) rev = phydev->phy_id & ~phydev->drv->phy_id_mask; - pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n", + if (!priv->printed) { + pr_info("%s: %s PHY revision: 0x%02x, patch: %d\n", phydev_name(phydev), phydev->drv->name, rev, patch); + priv->printed = true; + } /* Dummy read to a register to workaround an issue upon reset where the * internal inverter may not allow the first MDIO transaction to pass @@ -365,11 +370,15 @@ static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev) { + struct bcm7xxx_phy_priv *priv = phydev->priv; u8 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; int ret = 0; - pr_info_once("%s: %s PHY revision: 0x%02x\n", + if (!priv->printed) { + pr_info("%s: %s PHY revision: 0x%02x\n", phydev_name(phydev), phydev->drv->name, rev); + priv->printed = true; + } /* Dummy read to a register to workaround a possible issue upon reset * where the internal inverter may not allow the first MDIO transaction @@ -591,6 +600,7 @@ BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"), BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"), BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"), + BCM7XXX_28NM_GPHY(PHY_ID_BCM63138, "Broadcom BCM63138"), BCM7XXX_40NM_EPHY(PHY_ID_BCM7346, "Broadcom BCM7346"), BCM7XXX_40NM_EPHY(PHY_ID_BCM7362, "Broadcom BCM7362"), BCM7XXX_40NM_EPHY(PHY_ID_BCM7425, "Broadcom BCM7425"), @@ -615,6 +625,7 @@ { PHY_ID_BCM7439, 0xfffffff0, }, { PHY_ID_BCM7435, 0xfffffff0, }, { PHY_ID_BCM7445, 0xfffffff0, }, + { PHY_ID_BCM63138, 0xfffffff0, }, { } }; diff -ruw linux-5.4.60/drivers/net/phy/broadcom.c linux-5.4.60-fbx/drivers/net/phy/broadcom.c --- linux-5.4.60/drivers/net/phy/broadcom.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/broadcom.c 2021-03-04 13:20:59.287505623 +0100 @@ -600,6 +600,315 @@ bcm_phy_get_stats(phydev, priv->stats, stats, data); } + +#define BRCM_MIIEXT_BANK 0x1f +# define BRCM_MIIEXT_BANK_MASK 0xfff0 +# define BRCM_MIIEXT_ADDR_RANGE 0xffe0 +# define BRCM_MIIEXT_DEF_BANK 0x8000 +#define BRCM_MIIEXT_OFFSET 0x10 +# define BRCM_MIIEXT_OFF_MASK 0xf + +#if 0 +static int bcm63138_ephy_read(struct phy_device *phydev, int reg) +{ + uint32_t bank; + uint32_t offset; + int val; + int error; + + if (reg < 0x20) + return phy_read(phydev, reg); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = phy_write(phydev, BRCM_MIIEXT_BANK, bank); + val = phy_read(phydev, offset); + if (val < 0) + error = val; + + error |= phy_write(phydev, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + return (error < 0) ? error : val; +} +#endif + +static int bcm63138_ephy_write(struct phy_device *phydev, int reg, u16 value) +{ + uint32_t bank; + uint32_t offset; + int error; + + if (reg < 0x20) + return phy_write(phydev, reg, value); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = phy_write(phydev, BRCM_MIIEXT_BANK, bank); + error |= phy_write(phydev, offset, value); + error |= phy_write(phydev, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + + return error; +} + +static int bcm63138s_get_features(struct phy_device *phydev) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(features) = { 0, }; + + linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, features); + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, features); + linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, features); + + linkmode_copy(phydev->supported, features); + linkmode_copy(phydev->advertising, features); + + return 0; +} + +static int bcm63138s_config_init(struct phy_device *phydev) +{ + static const unsigned short cfg_1000x[] = { + 0x0010, 0x0c2f, + 0x8182, 0x4000, + 0x8186, 0x003c, + 0x8300, 0x015d, + 0x8301, 0x7, + 0x0, 0x1140, + 0x0010, 0x2c2f + }; + int err; + size_t i; + + err = genphy_soft_reset(phydev); + if (err < 0) + return err; + + for (i = 0; i < ARRAY_SIZE(cfg_1000x); i += 2) + bcm63138_ephy_write(phydev, cfg_1000x[i], cfg_1000x[i + 1]); + + return 0; +} + +/** + * ethtool_adv_to_fiber_adv_t + * @ethadv: the ethtool advertisement settings + * + * A small helper function that translates ethtool advertisement + * settings to phy autonegotiation advertisements for the + * MII_ADV register for fiber link. + */ +static inline u32 ethtool_adv_to_fiber_adv_t(unsigned long *adv) +{ + u32 result = 0; + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, adv)) + result |= ADVERTISE_1000XFULL; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, adv)) + result |= ADVERTISE_1000XFULL; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, adv)) + result |= ADVERTISE_1000XHALF; + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, adv) && + linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, adv)) + result |= ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM; + else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, adv)) + result |= ADVERTISE_1000XPAUSE; + + return result; +} + +static int bcm63138s_config_aneg(struct phy_device *phydev) +{ + int oldadv, adv, err; + int changed; + + if (phydev->autoneg != AUTONEG_ENABLE) + return genphy_setup_forced(phydev); + + /* Setup fiber advertisement */ + adv = phy_read(phydev, MII_ADVERTISE); + if (adv < 0) + return adv; + + oldadv = adv; + adv &= ~(ADVERTISE_1000XFULL | + ADVERTISE_1000XHALF | + ADVERTISE_1000XPSE_ASYM | + ADVERTISE_1000XPAUSE); + adv |= ethtool_adv_to_fiber_adv_t(phydev->advertising); + + if (adv != oldadv) { + err = phy_write(phydev, MII_ADVERTISE, adv); + if (err < 0) + return err; + + changed = 1; + } + + if (changed == 0) { + /* Advertisement hasn't changed, but maybe aneg was never on to + * begin with? Or maybe phy was isolated? + */ + int ctl = phy_read(phydev, MII_BMCR); + + if (ctl < 0) + return ctl; + + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) + changed = 1; /* do restart aneg */ + } + + /* Only restart aneg if we are advertising something different + * than we were before. + */ + if (changed > 0) + changed = genphy_restart_aneg(phydev); + + return changed; +} + +/** + * fiber_lpa_to_ethtool_lpa_t + * @lpa: value of the MII_LPA register for fiber link + * + * A small helper function that translates MII_LPA + * bits to ethtool LP advertisement settings. + */ +static void fiber_lpa_to_ethtool_lpa_t(u32 lpa, unsigned long *res) +{ + linkmode_zero(res); + + if (lpa & LPA_1000XHALF) + linkmode_set_bit( ADVERTISED_1000baseT_Half, res); + if (lpa & LPA_1000XFULL) + linkmode_set_bit(ADVERTISED_1000baseT_Full, res); +} + +static int bcm63138s_read_status_page_an(struct phy_device *phydev) +{ + int lpa, adv, common_adv; + + lpa = phy_read(phydev, MII_LPA); + if (lpa < 0) + return lpa; + + adv = phy_read(phydev, MII_ADVERTISE); + if (adv < 0) + return adv; + + common_adv = lpa & adv; + + phydev->speed = SPEED_10; + phydev->duplex = DUPLEX_HALF; + fiber_lpa_to_ethtool_lpa_t(lpa, phydev->lp_advertising); + + phydev->pause = 0; + phydev->asym_pause = 0; + + if (common_adv & (LPA_1000XHALF | LPA_1000XFULL)) { + phydev->speed = SPEED_1000; + if (common_adv & LPA_1000XFULL) + phydev->duplex = DUPLEX_FULL; + } + + if (phydev->duplex == DUPLEX_FULL) { + if (!(lpa & LPA_1000XPAUSE)) { + phydev->pause = 0; + phydev->asym_pause = 0; + } else if ((lpa & LPA_1000XPAUSE_ASYM)) { + phydev->pause = 1; + phydev->asym_pause = 1; + } else { + phydev->pause = 1; + phydev->asym_pause = 0; + } + } + + return 0; +} + +static int bcm63138s_read_status_page_fixed(struct phy_device *phydev) +{ + int bmcr = phy_read(phydev, MII_BMCR); + + if (bmcr < 0) + return bmcr; + + if (bmcr & BMCR_FULLDPLX) + phydev->duplex = DUPLEX_FULL; + else + phydev->duplex = DUPLEX_HALF; + + phydev->speed = SPEED_1000; + phydev->pause = 0; + phydev->asym_pause = 0; + + return 0; +} + +static int bcm63138s_read_status(struct phy_device *phydev) +{ + int err; + + genphy_update_link(phydev); + + if (phydev->autoneg == AUTONEG_ENABLE) + err = bcm63138s_read_status_page_an(phydev); + else + err = bcm63138s_read_status_page_fixed(phydev); + + return err; +} + +#define MISC_ADDR(base, channel) base, channel + +#define AFE_TXCONFIG_0 MISC_ADDR(0x39, 1) +#define AFE_TXCONFIG_1 MISC_ADDR(0x3a, 2) +#define AFE_TX_IQ_RX_LP MISC_ADDR(0x39, 0) +#define AFE_TEMPSEN_OTHERS MISC_ADDR(0x3b, 0) + +static void r_rc_cal_reset(struct phy_device *phydev) +{ + /* Reset R_CAL/RC_CAL Engine */ + bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0010); + + /* Disable Reset R_AL/RC_CAL Engine */ + bcm_phy_write_exp_sel(phydev, 0x00b0, 0x0000); +} + +static int bcm63158_config_init(struct phy_device *phydev) +{ + /* Turn off AOF */ + bcm_phy_write_misc(phydev, AFE_TXCONFIG_0, 0x0000); + + /* 1g AB symmetry Iq */ + bcm_phy_write_misc(phydev, AFE_TXCONFIG_1, 0x0BCC); + + /* LPF BW */ + bcm_phy_write_misc(phydev, AFE_TX_IQ_RX_LP, 0x233F); + + /* RCAL +6LSB to make impedance from 112 to 100ohm */ + bcm_phy_write_misc(phydev, AFE_TEMPSEN_OTHERS, 0xAD40); + + /* since rcal make R smaller, make master current -4% */ + bcm_phy_write_misc(phydev, DSP_TAP10, 0x091B); + + /* From EEE excel config file for Vitesse fix */ + /* rx_on_tune 8 -> 0xf */ + bcm_phy_write_misc(phydev, 0x0021, 0x0002, 0x87F6); + + /* 100tx EEE bandwidth */ + bcm_phy_write_misc(phydev, 0x0022, 0x0002, 0x017D); + + /* enable ffe zero det for Vitesse interop */ + bcm_phy_write_misc(phydev, 0x0026, 0x0002, 0x0015); + + /* Reset R_CAL/RC_CAL engine */ + r_rc_cal_reset(phydev); + + return 0; +} + static struct phy_driver broadcom_drivers[] = { { .phy_id = PHY_ID_BCM5411, @@ -745,6 +1054,27 @@ .config_init = bcm54xx_config_init, .ack_interrupt = bcm_phy_ack_intr, .config_intr = bcm_phy_config_intr, +}, { + .phy_id = PHY_ID_BCM63138S, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM63138S", + .get_features = bcm63138s_get_features, + .config_init = bcm63138s_config_init, + .config_aneg = bcm63138s_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = bcm63138s_read_status, +}, { + .phy_id = PHY_ID_BCM63158, + .phy_id_mask = 0xfffffff0, + .name = "Broadcom BCM63158", + .features = PHY_GBIT_FEATURES, + .flags = PHY_IS_INTERNAL, + .config_init = bcm63158_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .suspend = genphy_suspend, + .resume = genphy_resume, } }; module_phy_driver(broadcom_drivers); @@ -767,6 +1097,8 @@ { PHY_ID_BCM5241, 0xfffffff0 }, { PHY_ID_BCM5395, 0xfffffff0 }, { PHY_ID_BCM89610, 0xfffffff0 }, + { PHY_ID_BCM63138S, 0xfffffff0 }, + { PHY_ID_BCM63158, 0xfffffff0 }, { } }; diff -ruw linux-5.4.60/drivers/net/phy/mdio_bus.c linux-5.4.60-fbx/drivers/net/phy/mdio_bus.c --- linux-5.4.60/drivers/net/phy/mdio_bus.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/mdio_bus.c 2021-03-04 13:20:59.290838956 +0100 @@ -404,8 +404,16 @@ bus->reset_gpiod = gpiod; gpiod_set_value_cansleep(gpiod, 1); + if (bus->reset_delay_us < 1000) udelay(bus->reset_delay_us); + else + mdelay(bus->reset_delay_us / 1000); + gpiod_set_value_cansleep(gpiod, 0); + if (bus->reset_delay_us < 1000) + udelay(bus->reset_delay_us); + else + mdelay(bus->reset_delay_us / 1000); } if (bus->reset) diff -ruw linux-5.4.60/drivers/net/phy/phy.c linux-5.4.60-fbx/drivers/net/phy/phy.c --- linux-5.4.60/drivers/net/phy/phy.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/phy.c 2021-03-04 13:20:59.290838956 +0100 @@ -29,7 +29,7 @@ #include #include -#define PHY_STATE_TIME HZ +#define PHY_STATE_TIME (HZ / 2) #define PHY_STATE_STR(_state) \ case PHY_##_state: \ diff -ruw linux-5.4.60/drivers/net/phy/phy-core.c linux-5.4.60-fbx/drivers/net/phy/phy-core.c --- linux-5.4.60/drivers/net/phy/phy-core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/phy-core.c 2021-03-04 13:20:59.290838956 +0100 @@ -8,7 +8,7 @@ const char *phy_speed_to_str(int speed) { - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 69, + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 75, "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "If a speed or mode has been added please update phy_speed_to_str " "and the PHY settings array.\n"); @@ -113,6 +113,10 @@ PHY_SETTING( 20000, FULL, 20000baseKR2_Full ), PHY_SETTING( 20000, FULL, 20000baseMLD2_Full ), /* 10G */ + PHY_SETTING( 10000, FULL, 10000_1000basePRX_D_Full ), + PHY_SETTING( 10000, FULL, 10000_1000basePRX_U_Full ), + PHY_SETTING( 10000, FULL, 10000basePR_D_Full ), + PHY_SETTING( 10000, FULL, 10000basePR_U_Full ), PHY_SETTING( 10000, FULL, 10000baseCR_Full ), PHY_SETTING( 10000, FULL, 10000baseER_Full ), PHY_SETTING( 10000, FULL, 10000baseKR_Full ), @@ -128,6 +132,8 @@ PHY_SETTING( 2500, FULL, 2500baseT_Full ), PHY_SETTING( 2500, FULL, 2500baseX_Full ), /* 1G */ + PHY_SETTING( 1000, FULL, 1000basePX_D_Full ), + PHY_SETTING( 1000, FULL, 1000basePX_U_Full ), PHY_SETTING( 1000, FULL, 1000baseKX_Full ), PHY_SETTING( 1000, FULL, 1000baseT_Full ), PHY_SETTING( 1000, HALF, 1000baseT_Half ), diff -ruw linux-5.4.60/drivers/net/phy/phy_device.c linux-5.4.60-fbx/drivers/net/phy/phy_device.c --- linux-5.4.60/drivers/net/phy/phy_device.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/phy_device.c 2021-03-04 13:20:59.290838956 +0100 @@ -1767,7 +1767,7 @@ * drops can be detected. Do not double-read the status * in polling mode to detect such short link drops. */ - if (!phy_polling_mode(phydev)) { + if (!phy_polling_mode(phydev) || !phydev->link) { status = phy_read(phydev, MII_BMSR); if (status < 0) return status; diff -ruw linux-5.4.60/drivers/net/phy/phylink.c linux-5.4.60-fbx/drivers/net/phy/phylink.c --- linux-5.4.60/drivers/net/phy/phylink.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/phylink.c 2021-03-04 13:20:59.290838956 +0100 @@ -311,6 +311,25 @@ phylink_set(pl->supported, 10000baseER_Full); break; + case PHY_INTERFACE_MODE_1000BASEPX_D: + phylink_set(pl->supported, 1000basePX_D_Full); + break; + case PHY_INTERFACE_MODE_1000BASEPX_U: + phylink_set(pl->supported, 1000basePX_U_Full); + break; + case PHY_INTERFACE_MODE_10000BASEPR_D: + phylink_set(pl->supported, 10000basePR_D_Full); + break; + case PHY_INTERFACE_MODE_10000BASEPR_U: + phylink_set(pl->supported, 10000basePR_U_Full); + break; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_D: + phylink_set(pl->supported, 10000_1000basePRX_D_Full); + break; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + phylink_set(pl->supported, 10000_1000basePRX_U_Full); + break; + default: phylink_err(pl, "incorrect link mode %s for in-band status\n", @@ -1853,4 +1872,34 @@ } EXPORT_SYMBOL_GPL(phylink_helper_basex_speed); +int phylink_set_interface_mode(struct phylink *pl, int mode) +{ + int err; + + pl->link_config.interface = mode; + err = phylink_validate(pl, pl->supported, &pl->link_config); + if (err) + pr_err("unable to validate phylink new interface mode.\n"); + + return err; + +} +EXPORT_SYMBOL_GPL(phylink_set_interface_mode); + +void phylink_revalidate(struct phylink *pl) +{ + linkmode_zero(pl->supported); + phylink_set(pl->supported, MII); + phylink_set(pl->supported, Autoneg); + phylink_set(pl->supported, Asym_Pause); + phylink_set(pl->supported, Pause); + pl->link_config.an_enabled = true; + pl->link_an_mode = MLO_AN_INBAND; + pl->link_interface = PHY_INTERFACE_MODE_NA; + linkmode_copy(pl->link_config.advertising, pl->supported); + phylink_validate(pl, pl->supported, &pl->link_config); + +} +EXPORT_SYMBOL_GPL(phylink_revalidate); + MODULE_LICENSE("GPL v2"); diff -ruw linux-5.4.60/drivers/net/phy/realtek.c linux-5.4.60-fbx/drivers/net/phy/realtek.c --- linux-5.4.60/drivers/net/phy/realtek.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/realtek.c 2021-03-04 13:20:59.290838956 +0100 @@ -11,6 +11,8 @@ #include #include #include +#include +#include #define RTL821x_PHYSR 0x11 #define RTL821x_PHYSR_DUPLEX BIT(13) @@ -49,10 +51,20 @@ #define RTL_GENERIC_PHYID 0x001cc800 +#define RTL8211F_LCR_PAGE 0xd04 +#define RTL8211F_LCR_REG 0x10 +#define RTL8211F_LED_MODE_MASK(num) (0x1b << ((num) * 5)) +#define RTL8211F_LED_MODE_SEL(num, mode) ((mode) << ((num) * 5)) + MODULE_DESCRIPTION("Realtek PHY driver"); MODULE_AUTHOR("Johnson Leung"); MODULE_LICENSE("GPL"); +#define MAX_LEDS 3 +struct rtl8211f_private { + u8 leds_mode[MAX_LEDS]; +}; + static int rtl821x_read_page(struct phy_device *phydev) { return __phy_read(phydev, RTL821x_PAGE_SELECT); @@ -169,12 +181,27 @@ CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); } +static void rtl8211f_config_led(struct phy_device *phydev) +{ + struct rtl8211f_private *priv = phydev->priv; + size_t i; + + /* Configure led */ + for (i = 0; i < MAX_LEDS; ++i) { + phy_modify_paged(phydev, RTL8211F_LCR_PAGE, RTL8211F_LCR_REG, + RTL8211F_LED_MODE_MASK(i), + RTL8211F_LED_MODE_SEL(i, priv->leds_mode[i])); + } +} + static int rtl8211f_config_init(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; u16 val; int ret; + rtl8211f_config_led(phydev); + /* enable TX-delay for rgmii-{id,txid}, and disable it for rgmii and * rgmii-rxid. The RX-delay can be enabled by the external RXDLY pin. */ @@ -209,6 +236,69 @@ return 0; } +#ifdef CONFIG_OF_MDIO +static int rtl8211f_dt_led_modes_get(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct device_node *of_node = dev->of_node; + struct rtl8211f_private *priv = phydev->priv; + int nr, i, ret; + char *led_dt_prop = "rtl8211f,led-mode"; + uint8_t mode[MAX_LEDS << 1]; + + if (!of_node) + return -ENODEV; + + nr = of_property_read_variable_u8_array(of_node, led_dt_prop, mode, 0, + ARRAY_SIZE(mode)); + + /* nr should be even */ + if (nr & 0x1) + return -EINVAL; + + ret = -EINVAL; + for (i = 0; i < nr; i += 2) { + if (mode[i] >= MAX_LEDS) + goto out; + if ((mode[i + 1] & ~RTL8211F_LED_MODE_MASK(0)) != 0) + goto out; + priv->leds_mode[mode[i]] = mode[i + 1]; + } + + ret = 0; + +out: + return ret; +} + + +#else +static int rtl8211f_dt_led_modes_get(struct phy_device *phydev) +{ + return 0; +} +#endif /* CONFIG_OF_MDIO */ + +static int rtl8211f_probe(struct phy_device *phydev) +{ + struct rtl8211f_private *priv; + u8 default_mode[MAX_LEDS] = { + [0] = RTL8211F_LED_MODE_10M | RTL8211F_LED_MODE_100M | + RTL8211F_LED_MODE_1000M | RTL8211F_LED_MODE_ACT, + [1] = RTL8211F_LED_MODE_10M | RTL8211F_LED_MODE_100M | + RTL8211F_LED_MODE_1000M, + [2] = RTL8211F_LED_MODE_1000M | RTL8211F_LED_MODE_ACT, + }; + + priv = devm_kmalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); + if (priv == NULL) + return -ENOMEM; + + memcpy(priv->leds_mode, default_mode, sizeof(priv->leds_mode)); + phydev->priv = priv; + return rtl8211f_dt_led_modes_get(phydev); +} + static int rtl8211e_config_init(struct phy_device *phydev) { int ret = 0, oldpage; @@ -514,6 +604,7 @@ }, { PHY_ID_MATCH_EXACT(0x001cc916), .name = "RTL8211F Gigabit Ethernet", + .probe = &rtl8211f_probe, .config_init = &rtl8211f_config_init, .ack_interrupt = &rtl8211f_ack_interrupt, .config_intr = &rtl8211f_config_intr, diff -ruw linux-5.4.60/drivers/net/phy/sfp.h linux-5.4.60-fbx/drivers/net/phy/sfp.h --- linux-5.4.60/drivers/net/phy/sfp.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/sfp.h 2021-03-04 13:20:59.294172289 +0100 @@ -14,6 +14,7 @@ int (*module_info)(struct sfp *sfp, struct ethtool_modinfo *modinfo); int (*module_eeprom)(struct sfp *sfp, struct ethtool_eeprom *ee, u8 *data); + int (*get_sfp_state)(struct sfp *sfp, struct ethtool_sfp_state *st); }; int sfp_add_phy(struct sfp_bus *bus, struct phy_device *phydev); diff -ruw linux-5.4.60/drivers/net/phy/swphy.c linux-5.4.60-fbx/drivers/net/phy/swphy.c --- linux-5.4.60/drivers/net/phy/swphy.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/phy/swphy.c 2021-03-04 13:20:59.294172289 +0100 @@ -29,6 +29,7 @@ SWMII_SPEED_10 = 0, SWMII_SPEED_100, SWMII_SPEED_1000, + SWMII_SPEED_2500, SWMII_DUPLEX_HALF = 0, SWMII_DUPLEX_FULL, }; @@ -51,6 +52,10 @@ .lpagb = LPA_1000FULL | LPA_1000HALF, .estat = ESTATUS_1000_TFULL | ESTATUS_1000_THALF, }, + [SWMII_SPEED_2500] = { + .bmsr = BMSR_ESTATEN, + .lpagb = LPA_1000FULL | LPA_1000HALF, + }, }; static const struct swmii_regs duplex[] = { @@ -71,6 +76,8 @@ static int swphy_decode_speed(int speed) { switch (speed) { + case 2500: + return SWMII_SPEED_2500; case 1000: return SWMII_SPEED_1000; case 100: diff -ruw linux-5.4.60/drivers/net/ppp/ppp_generic.c linux-5.4.60-fbx/drivers/net/ppp/ppp_generic.c --- linux-5.4.60/drivers/net/ppp/ppp_generic.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/ppp/ppp_generic.c 2021-03-04 13:20:59.294172289 +0100 @@ -174,6 +174,7 @@ struct ppp *ppp; /* ppp unit we're connected to */ struct net *chan_net; /* the net channel belongs to */ struct list_head clist; /* link in list of channels per unit */ + int stopped; /* channel is stopped */ rwlock_t upl; /* protects `ppp' */ #ifdef CONFIG_PPP_MULTILINK u8 avail; /* flag used in multilink stuff */ @@ -1409,10 +1410,28 @@ ppp_send_frame(ppp, skb); /* If there's no work left to do, tell the core net code that we can accept some more. */ - if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq)) + if (!ppp->xmit_pending && !skb_peek(&ppp->file.xq)) { + /* only enable net queue if at least one + * channel is not stopped */ + struct list_head *list; + struct channel *pch; + bool need_wake; + + list = &ppp->channels; + need_wake = false; + while ((list = list->next) != &ppp->channels) { + pch = list_entry(list, struct channel, clist); + if (!pch->stopped) { + need_wake = true; + break; + } + } + + if (need_wake) netif_wake_queue(ppp->dev); else netif_stop_queue(ppp->dev); + } } else { kfree_skb(skb); } @@ -2725,10 +2744,24 @@ if (!pch) return; + pch->stopped = 0; ppp_channel_push(pch); } /* + * Callback from a channel when it want to prevent further transmit on it + */ +void +ppp_output_stop(struct ppp_channel *chan) +{ + struct channel *pch = chan->ppp; + + if (pch == 0) + return; + pch->stopped = 1; +} + +/* * Compression control. */ @@ -3325,6 +3358,7 @@ EXPORT_SYMBOL(ppp_input); EXPORT_SYMBOL(ppp_input_error); EXPORT_SYMBOL(ppp_output_wakeup); +EXPORT_SYMBOL(ppp_output_stop); EXPORT_SYMBOL(ppp_register_compressor); EXPORT_SYMBOL(ppp_unregister_compressor); MODULE_LICENSE("GPL"); diff -ruw linux-5.4.60/drivers/net/ppp/pptp.c linux-5.4.60-fbx/drivers/net/ppp/pptp.c --- linux-5.4.60/drivers/net/ppp/pptp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/ppp/pptp.c 2021-03-04 13:20:59.294172289 +0100 @@ -358,6 +358,7 @@ po = lookup_chan(htons(header->call_id), iph->saddr); if (po) { skb_dst_drop(skb); + skb->mark = 0; nf_reset_ct(skb); return sk_receive_skb(sk_pppox(po), skb, 0); } diff -ruw linux-5.4.60/drivers/net/tun.c linux-5.4.60-fbx/drivers/net/tun.c --- linux-5.4.60/drivers/net/tun.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/tun.c 2021-03-04 13:20:59.297505623 +0100 @@ -68,6 +68,10 @@ #include #include #include +#include +#include +#include +#include #include #include @@ -194,6 +198,31 @@ unsigned long updated ____cacheline_aligned_in_smp; }; +/* + * smalltun definitions + */ +#define SMALLTUN_MAGIC 0x6660 +#define SMALLTUN_VERSION 0x1 + +#define TYPE_MASK 0xf +#define TYPE_CLT (1 << 3) + +#define TYPE_TRIGGER 0x0 +#define TYPE_CHALLENGE 0x1 +#define TYPE_CLIENT_HELLO 0x2 +#define TYPE_SERVER_HELLO 0x3 + +#define TYPE_CLT_DATA (TYPE_CLT | 0x0) +#define TYPE_CLT_GET_PARAMS (TYPE_CLT | 0x1) +#define TYPE_CLT_PARAMS (TYPE_CLT | 0x2) + +struct smalltun_pkt_hdr { + u16 magic; + u8 version; + u8 flag_type; + u8 data[0]; +}; + #define TUN_NUM_FLOW_ENTRIES 1024 #define TUN_MASK_FLOW_ENTRIES (TUN_NUM_FLOW_ENTRIES - 1) @@ -213,6 +242,11 @@ kuid_t owner; kgid_t group; + struct smalltun_fp smalltun_fps[4]; + unsigned int smalltun_valid_count; + unsigned int smalltun_valid[4]; + struct rtable *smalltun_rt_cache[4]; + struct net_device *dev; netdev_features_t set_features; #define TUN_USER_FEATURES (NETIF_F_HW_CSUM|NETIF_F_TSO_ECN|NETIF_F_TSO| \ @@ -1027,6 +1061,184 @@ return 0; } +static int smalltun_is_fastpath(struct tun_struct *tun, + struct sk_buff *skb) +{ + struct iphdr *iph; + const struct smalltun_fp *fp; + struct rtable **prt_cache, *rt_cache; + struct flowi4 fl; + bool match; + size_t i; + + if (!tun->smalltun_valid_count) + return 0; + + if (skb->protocol != htons(ETH_P_IP)) + return 0; + + if (!pskb_may_pull(skb, sizeof(struct iphdr))) + return 0; + + iph = ip_hdr(skb); + + /* lookup smalltun fastpath */ + fp = NULL; + rt_cache = NULL; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) + continue; + + if (iph->daddr == tun->smalltun_fps[i].inner_dst) { + fp = &tun->smalltun_fps[i]; + prt_cache = &tun->smalltun_rt_cache[i]; + break; + } + } + + if (!fp) + return 0; + + if (fp->af != AF_INET) { + /* FIXME: implement IPv6 transport */ + return 0; + } + + if (!pskb_may_pull(skb, iph->ihl * 4)) + return 0; + + match = false; + for (i = 0; i < fp->rule_count; i++) { + const struct smalltun_rule *r = &fp->rules[i]; + unsigned int sport, dport; + + if (iph->protocol != r->proto) + continue; + + switch (iph->protocol) { + case IPPROTO_UDP: + { + const struct udphdr *udp; + udp = (struct udphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = ntohs(udp->source); + dport = ntohs(udp->dest); + break; + } + case IPPROTO_TCP: + { + const struct tcphdr *tcp; + tcp = (struct tcphdr *)((u8 *)iph + (iph->ihl << 2)); + sport = ntohs(tcp->source); + dport = ntohs(tcp->dest); + break; + } + default: + match = true; + break; + } + + if (match) + break; + + if (r->src_port_start && r->src_port_end) { + if (sport < ntohs(r->src_port_start) || + sport > ntohs(r->src_port_end)) + continue; + } + + if (r->dst_port_start && r->dst_port_end) { + if (dport < ntohs(r->dst_port_start) || + dport > ntohs(r->dst_port_end)) + continue; + } + match = true; + } + + if (!match) + return 0; + + if (fp->af == AF_INET) { + struct iphdr *oiph; + struct udphdr *oudph; + struct smalltun_pkt_hdr *pkt; + unsigned int payload_len; + + payload_len = skb->len; + + if (skb_cow_head(skb, + sizeof (struct iphdr) + + sizeof (struct udphdr) + + sizeof (struct smalltun_pkt_hdr))) + return 0; + + pkt = skb_push(skb, sizeof (struct smalltun_pkt_hdr)); + oudph = skb_push(skb, sizeof (struct udphdr)); + skb_reset_transport_header(skb); + oiph = skb_push(skb, sizeof (struct iphdr)); + skb_reset_network_header(skb); + + /* ip */ + oiph->version = 4; + oiph->tos = 0; + oiph->id = 0; + oiph->ihl = 5; + oiph->frag_off = 0; + oiph->ttl = 64; + oiph->protocol = IPPROTO_UDP; + memcpy(&oiph->saddr, fp->outer_src, 4); + memcpy(&oiph->daddr, fp->outer_dst, 4); + + /* udp */ + oudph->source = fp->outer_src_port; + oudph->dest = fp->outer_dst_port; + oudph->len = htons(payload_len + sizeof (*oudph) + + sizeof (*pkt)); + oudph->check = 0; + + /* smalltun */ + pkt->magic = htons(SMALLTUN_MAGIC); + pkt->version = SMALLTUN_VERSION; + pkt->flag_type = TYPE_CLT_DATA; + + memset(&fl, 0x00, sizeof (fl)); + memcpy(&fl.saddr, fp->outer_src, 4); + memcpy(&fl.daddr, fp->outer_dst, 4); + + if (*prt_cache && (*prt_cache)->dst.obsolete > 0) { + rt_cache = *prt_cache; + *prt_cache = NULL; + ip_rt_put(rt_cache); + } + + rt_cache = *prt_cache; + if (!rt_cache) { + rt_cache = ip_route_output_key(&init_net, &fl); + if (IS_ERR(rt_cache)) { + pr_err("ip_route_output_key(%pI4): %li\n", + &fl.daddr, PTR_ERR(rt_cache)); + return 0; + } + + if (!rt_cache->dst.dev) { + pr_err("ip_route_output_key(%pI4): no dev\n", + &fl.daddr); + return 0; + } + + *prt_cache = rt_cache; + } + + skb_dst_set(skb, dst_clone(&rt_cache->dst)); + skb->dev = skb_dst(skb)->dev; + ip_local_out(&init_net, NULL, skb); + return 1; + } + + /* find route */ + + return 0; +} + /* Net device start xmit */ static void tun_automq_xmit(struct tun_struct *tun, struct sk_buff *skb) { @@ -1104,6 +1316,11 @@ */ skb_orphan(skb); + if (smalltun_is_fastpath(tun, skb)) { + rcu_read_unlock(); + return NETDEV_TX_OK; + } + nf_reset_ct(skb); if (ptr_ring_produce(&tfile->tx_ring, skb)) @@ -3347,6 +3564,100 @@ ret = open_related_ns(&net->ns, get_net_ns); break; + case TUNSMALLTUNSETFP: + { + struct smalltun_fp fp; + unsigned int i; + int free_idx; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* look for duplicate */ + ret = 0; + free_idx = -1; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (!tun->smalltun_valid[i]) { + if (free_idx == -1) + free_idx = i; + continue; + } + + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = -EEXIST; + break; + } + } + + if (ret) + break; + + if (free_idx == -1) { + ret = -ENOSPC; + break; + } + + memcpy(&tun->smalltun_fps[free_idx], &fp, sizeof (fp)); + tun->smalltun_valid[free_idx] = 1; + tun->smalltun_valid_count++; + tun_debug(KERN_INFO, tun, "new fp rule for %pI4 <=> %pI4 (%u rules)\n", + &fp.inner_src, + &fp.inner_dst, + fp.rule_count); + + if (fp.af == AF_INET) { + tun_debug(KERN_INFO, tun, "outer %pI4:%u <=> %pI4:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } else { + tun_debug(KERN_INFO, tun, "outer %pI6:%u <=> %pI6:%u\n", + fp.outer_src, + ntohs(fp.outer_src_port), + fp.outer_dst, + ntohs(fp.outer_dst_port)); + } + break; + } + + case TUNSMALLTUNDELFP: + { + struct smalltun_fp fp; + unsigned int i; + + ret = -EFAULT; + if (copy_from_user(&fp, argp, sizeof(fp))) + break; + + /* lookup */ + ret = -ENOENT; + for (i = 0; i < ARRAY_SIZE(tun->smalltun_fps); i++) { + if (fp.inner_src == tun->smalltun_fps[i].inner_src && + fp.inner_dst == tun->smalltun_fps[i].inner_dst) { + ret = 0; + break; + } + } + + if (ret) + break; + + tun->smalltun_valid[i] = 0; + tun->smalltun_valid_count--; + if (tun->smalltun_rt_cache[i]) { + ip_rt_put(tun->smalltun_rt_cache[i]); + tun->smalltun_rt_cache[i] = NULL; + } + + tun_debug(KERN_INFO, tun, "removed fp rule for %pI4 <=> %pI4\n", + &fp.inner_src, + &fp.inner_dst); + break; + } + default: ret = -EINVAL; break; diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/core.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/core.c --- linux-5.4.60/drivers/net/wireless/ath/ath10k/core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/core.c 2021-03-04 13:20:59.314172291 +0100 @@ -88,6 +88,7 @@ .rri_on_ddr = false, .hw_filter_reset_required = true, .fw_diag_ce_download = false, + .uart_pin_workaround = true, .tx_stats_over_pktlog = true, }, { @@ -1090,6 +1091,7 @@ static int ath10k_fetch_cal_file(struct ath10k *ar) { char filename[100]; + unsigned int i; /* pre-cal--.bin */ scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", @@ -1103,6 +1105,11 @@ scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); + for (i = 0; filename[i]; i++) { + if (filename[i] == ':') + filename[i] = '_'; + } + ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); if (IS_ERR(ar->cal_file)) /* calibration file is optional, don't print any warnings */ @@ -2221,6 +2228,7 @@ switch (ar->state) { case ATH10K_STATE_ON: + case ATH10K_STATE_PRE_ON: ar->state = ATH10K_STATE_RESTARTING; ath10k_halt(ar); ath10k_scan_finish(ar); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/core.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/core.h --- linux-5.4.60/drivers/net/wireless/ath/ath10k/core.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/core.h 2021-03-04 13:20:59.314172291 +0100 @@ -646,10 +646,12 @@ void *cal_data; u32 enable_extd_tx_stats; u8 fw_dbglog_mode; + u32 burst_dur[4]; }; enum ath10k_state { ATH10K_STATE_OFF = 0, + ATH10K_STATE_PRE_ON, ATH10K_STATE_ON, /* When doing firmware recovery the device is first powered down. @@ -946,6 +948,7 @@ struct ieee80211_ops *ops; struct device *dev; u8 mac_addr[ETH_ALEN]; + const char *fem_name; enum ath10k_hw_rev hw_rev; u16 dev_id; @@ -1120,6 +1123,8 @@ struct work_struct register_work; struct work_struct restart_work; + struct work_struct powerup_work; + bool powerup_pending; /* cycle count is reported twice for each visited channel during scan. * access protected by data_lock diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/debug.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/debug.c --- linux-5.4.60/drivers/net/wireless/ath/ath10k/debug.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/debug.c 2021-03-04 13:20:59.314172291 +0100 @@ -2510,6 +2510,79 @@ .llseek = default_llseek, }; +static ssize_t ath10k_write_burst_dur(struct file *file, const char __user *user_buf, + size_t count, loff_t *ppos) +{ + + struct ath10k *ar = file->private_data; + u32 dur[4]; + int ret; + int ac; + char buf[128]; + + simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, user_buf, count); + + /* make sure that buf is null terminated */ + buf[sizeof(buf) - 1] = 0; + + ret = sscanf(buf, "%u %u %u %u", &dur[0], &dur[1], &dur[2], &dur[3]); + + if (!ret) + return -EINVAL; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_ON && + ar->state != ATH10K_STATE_RESTARTED) { + ret = -ENETDOWN; + goto exit; + } + + for (ac = 0; ac < 4; ac++) { + if (dur[ac] < MIN_BURST_DUR || dur[ac] > MAX_BURST_DUR) { + ret = -EINVAL; + goto exit; + } + + ret = ath10k_wmi_pdev_set_param(ar, ar->wmi.pdev_param->aggr_burst, + (SM(ac, ATH10K_AGGR_BURST_AC) | + SM(dur[ac], ATH10K_AGGR_BURST_DUR))); + if (ret) { + ath10k_warn(ar, "failed to set aggr burst duration for ac %d: %d\n", ac, ret); + goto exit; + } + ar->debug.burst_dur[ac] = dur[ac]; + } + + ret = count; + +exit: + mutex_unlock(&ar->conf_mutex); + return ret; +} + +static ssize_t ath10k_read_burst_dur(struct file *file, char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath10k *ar = file->private_data; + int len = 0; + char buf[128]; + + len = scnprintf(buf, sizeof(buf) - len, "%u %u %u %u\n", + ar->debug.burst_dur[0], ar->debug.burst_dur[1], + ar->debug.burst_dur[2], ar->debug.burst_dur[3]); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static const struct file_operations fops_burst_dur = { + .read = ath10k_read_burst_dur, + .write = ath10k_write_burst_dur, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + int ath10k_debug_create(struct ath10k *ar) { ar->debug.cal_data = vzalloc(ATH10K_DEBUG_CAL_DATA_LEN); @@ -2596,6 +2669,9 @@ debugfs_create_file("ani_enable", 0600, ar->debug.debugfs_phy, ar, &fops_ani_enable); + debugfs_create_file("burst_dur", S_IRUSR | S_IWUSR, + ar->debug.debugfs_phy, ar, &fops_burst_dur); + if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { debugfs_create_file("dfs_simulate_radar", 0200, ar->debug.debugfs_phy, ar, &fops_simulate_radar); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/debug.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/debug.h --- linux-5.4.60/drivers/net/wireless/ath/ath10k/debug.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/debug.h 2021-03-04 13:20:59.314172291 +0100 @@ -80,6 +80,15 @@ __printf(2, 3) void ath10k_err(struct ath10k *ar, const char *fmt, ...); __printf(2, 3) void ath10k_warn(struct ath10k *ar, const char *fmt, ...); +#define ATH10K_AGGR_BURST_AC_MASK 0xff000000 +#define ATH10K_AGGR_BURST_AC_LSB 24 +#define ATH10K_AGGR_BURST_DUR_MASK 0x00ffffff +#define ATH10K_AGGR_BURST_DUR_LSB 0 + +/* burst duration in usec */ +#define MIN_BURST_DUR 0 +#define MAX_BURST_DUR 8000 + void ath10k_debug_print_hwfw_info(struct ath10k *ar); void ath10k_debug_print_board_info(struct ath10k *ar); void ath10k_debug_print_boot_info(struct ath10k *ar); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/htt.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/htt.h --- linux-5.4.60/drivers/net/wireless/ath/ath10k/htt.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/htt.h 2021-03-04 13:20:59.314172291 +0100 @@ -2225,7 +2225,7 @@ * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size, * rounded up to a cache line size. */ -#define HTT_RX_BUF_SIZE 1920 +#define HTT_RX_BUF_SIZE 2048 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc)) /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/mac.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/mac.c --- linux-5.4.60/drivers/net/wireless/ath/ath10k/mac.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/mac.c 2021-03-04 13:20:59.317505624 +0100 @@ -2515,7 +2515,7 @@ const u16 *vht_mcs_mask; u8 ampdu_factor; u8 max_nss, vht_mcs; - int i; + int i, nss160; if (WARN_ON(ath10k_mac_vif_chan(vif, &def))) return; @@ -2575,23 +2575,45 @@ __le16_to_cpu(vht_cap->vht_mcs.tx_highest); arg->peer_vht_rates.tx_mcs_set = ath10k_peer_assoc_h_vht_limit( __le16_to_cpu(vht_cap->vht_mcs.tx_mcs_map), vht_mcs_mask); + arg->peer_bw_rxnss_override = 0; + nss160 = 1; /* 1x1 default config for VHT160 */ + + /* only local 4x4 configuration do support 2x2 for VHT160, + * everything else must use 1x1 + */ + + if (ar->cfg_rx_chainmask == 15) + nss160 = arg->peer_num_spatial_streams < 2 ? 1 : 2; + + /* if peer provides 1x1 nss160 information using max rate + * vht information, we reduce local nss160 to 1x1. + * consider that it has been observed that some client + * devices provide zero here, no matter which transmission + * rate is possible. in that case the local nss configuration + * will be used at maxmimum configuration possible. (see above) + */ - ath10k_dbg(ar, ATH10K_DBG_MAC, "mac vht peer %pM max_mpdu %d flags 0x%x\n", - sta->addr, arg->peer_max_mpdu, arg->peer_flags); + if (arg->peer_vht_rates.rx_max_rate == 780) + nss160 = 1; - if (arg->peer_vht_rates.rx_max_rate && - (sta->vht_cap.cap & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK)) { - switch (arg->peer_vht_rates.rx_max_rate) { - case 1560: - /* Must be 2x2 at 160Mhz is all it can do. */ - arg->peer_bw_rxnss_override = 2; - break; - case 780: - /* Can only do 1x1 at 160Mhz (Long Guard Interval) */ - arg->peer_bw_rxnss_override = 1; + /* in case if peer is connected with vht160 or vht80+80, + * we need to properly adjust rxnss parameters otherwise + * firmware will raise a assert + */ + switch (arg->peer_phymode) { + case MODE_11AC_VHT80_80: + arg->peer_bw_rxnss_override = BW_NSS_FWCONF_80_80(nss160); + /* fall through */ + case MODE_11AC_VHT160: + arg->peer_bw_rxnss_override |= BW_NSS_FWCONF_160(nss160); + break; + default: break; } - } + + ath10k_dbg(ar, ATH10K_DBG_MAC, "mac vht peer %pM max_mpdu %d flags 0x%x peer_bw_rxnss_override 0x%x\n", + sta->addr, arg->peer_max_mpdu, arg->peer_flags, + arg->peer_bw_rxnss_override); } static void ath10k_peer_assoc_h_qos(struct ath10k *ar, @@ -2743,9 +2765,9 @@ ath10k_peer_assoc_h_crypto(ar, vif, sta, arg); ath10k_peer_assoc_h_rates(ar, vif, sta, arg); ath10k_peer_assoc_h_ht(ar, vif, sta, arg); + ath10k_peer_assoc_h_phymode(ar, vif, sta, arg); ath10k_peer_assoc_h_vht(ar, vif, sta, arg); ath10k_peer_assoc_h_qos(ar, vif, sta, arg); - ath10k_peer_assoc_h_phymode(ar, vif, sta, arg); return 0; } @@ -4556,13 +4578,6 @@ vht_cap.cap |= val; } - /* Currently the firmware seems to be buggy, don't enable 80+80 - * mode until that's resolved. - */ - if ((ar->vht_cap_info & IEEE80211_VHT_CAP_SHORT_GI_160) && - (ar->vht_cap_info & IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK) == 0) - vht_cap.cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; - mcs_map = 0; for (i = 0; i < 8; i++) { if ((i < ar->num_rf_chains) && (ar->cfg_tx_chainmask & BIT(i))) @@ -4734,13 +4749,18 @@ const char *fem_name; int ret; + if (ar->fem_name) + fem_name = ar->fem_name; + else { node = ar->dev->of_node; if (!node) return -ENOENT; - ret = of_property_read_string_index(node, "ext-fem-name", 0, &fem_name); + ret = of_property_read_string_index(node, "ext-fem-name", + 0, &fem_name); if (ret) return -ENOENT; + } /* * If external Front End module used in hardware, then default base band timing @@ -4759,12 +4779,83 @@ return 0; } +static int ath10k_get_powered(struct ieee80211_hw *hw, bool *up, bool *busy) +{ + struct ath10k *ar = hw->priv; + *up = (ar->state == ATH10K_STATE_ON || + ar->state == ATH10K_STATE_PRE_ON); + *busy = ar->powerup_pending; + return 0; +} + +static int ath10k_set_powered(struct ieee80211_hw *hw) +{ + struct ath10k *ar = hw->priv; + + switch (ar->state) { + case ATH10K_STATE_OFF: + case ATH10K_STATE_PRE_ON: + break; + default: + return 0; + } + + if (ar->powerup_pending) + return 0; + + queue_work(ar->workqueue, &ar->powerup_work); + ar->powerup_pending = true; + return 0; +} + +static void ath10k_powerup_work(struct work_struct *work) +{ + struct ath10k *ar = container_of(work, struct ath10k, powerup_work); + int ret; + + mutex_lock(&ar->conf_mutex); + + if (ar->state != ATH10K_STATE_OFF) { + mutex_unlock(&ar->conf_mutex); + return; + } + + ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); + if (ret) { + ath10k_err(ar, "Could not init hif: %d\n", ret); + goto err_off; + } + + ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, + &ar->normal_mode_fw); + if (ret) { + ath10k_err(ar, "Could not init core: %d\n", ret); + goto err_power_down; + } + + ar->state = ATH10K_STATE_PRE_ON; + ar->powerup_pending = false; + mutex_unlock(&ar->conf_mutex); + return; + +err_power_down: + ath10k_hif_power_down(ar); + +err_off: + ar->state = ATH10K_STATE_OFF; + + ar->powerup_pending = false; + mutex_unlock(&ar->conf_mutex); + return; +} + static int ath10k_start(struct ieee80211_hw *hw) { struct ath10k *ar = hw->priv; u32 param; int ret = 0; struct wmi_bb_timing_cfg_arg bb_timing = {0}; + bool skip_core_start = false; /* * This makes sense only when restarting hw. It is harmless to call @@ -4779,6 +4870,10 @@ case ATH10K_STATE_OFF: ar->state = ATH10K_STATE_ON; break; + case ATH10K_STATE_PRE_ON: + skip_core_start = true; + ar->state = ATH10K_STATE_ON; + break; case ATH10K_STATE_RESTARTING: ar->state = ATH10K_STATE_RESTARTED; break; @@ -4793,6 +4888,7 @@ goto err; } + if (!skip_core_start) { ret = ath10k_hif_power_up(ar, ATH10K_FIRMWARE_MODE_NORMAL); if (ret) { ath10k_err(ar, "Could not init hif: %d\n", ret); @@ -4805,6 +4901,7 @@ ath10k_err(ar, "Could not init core: %d\n", ret); goto err_power_down; } + } param = ar->wmi.pdev_param->pmf_qos; ret = ath10k_wmi_pdev_set_param(ar, param, 1); @@ -4963,6 +5060,9 @@ ath10k_drain_tx(ar); + cancel_work_sync(&ar->powerup_work); + ar->powerup_pending = false; + mutex_lock(&ar->conf_mutex); if (ar->state != ATH10K_STATE_OFF) { ath10k_halt(ar); @@ -7131,7 +7231,7 @@ struct ieee80211_channel *channel) { int ret; - enum wmi_bss_survey_req_type type = WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR; + enum wmi_bss_survey_req_type type = WMI_BSS_SURVEY_REQ_TYPE_READ; lockdep_assert_held(&ar->conf_mutex); @@ -8187,6 +8287,8 @@ static const struct ieee80211_ops ath10k_ops = { .tx = ath10k_mac_op_tx, .wake_tx_queue = ath10k_mac_op_wake_tx_queue, + .get_powered = ath10k_get_powered, + .set_powered = ath10k_set_powered, .start = ath10k_start, .stop = ath10k_stop, .config = ath10k_config, @@ -8397,6 +8499,7 @@ .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT(NL80211_CHAN_WIDTH_20) | BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_160) | BIT(NL80211_CHAN_WIDTH_80), #endif }, @@ -8521,6 +8624,7 @@ .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT(NL80211_CHAN_WIDTH_20) | BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_160) | BIT(NL80211_CHAN_WIDTH_80), #endif }, @@ -8539,6 +8643,7 @@ .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | BIT(NL80211_CHAN_WIDTH_20) | BIT(NL80211_CHAN_WIDTH_40) | + BIT(NL80211_CHAN_WIDTH_160) | BIT(NL80211_CHAN_WIDTH_80), #endif }, @@ -8578,6 +8683,8 @@ #define WRD_METHOD "WRDD" #define WRDD_WIFI (0x07) +#define ATH10K_DFS_PULSE_VALID_DIFF_TS 100 + static u32 ath10k_mac_wrdd_get_mcc(struct ath10k *ar, union acpi_object *wrdd) { union acpi_object *mcc_pkg; @@ -8791,6 +8898,7 @@ ieee80211_hw_set(ar->hw, SUPPORT_FAST_XMIT); ieee80211_hw_set(ar->hw, CONNECTION_MONITOR); ieee80211_hw_set(ar->hw, SUPPORTS_PER_STA_GTK); + ieee80211_hw_set(ar->hw, APVLAN_NEED_MCAST_TO_UCAST); ieee80211_hw_set(ar->hw, WANT_MONITOR_VIF); ieee80211_hw_set(ar->hw, CHANCTX_STA_CSA); ieee80211_hw_set(ar->hw, QUEUE_CONTROL); @@ -8955,6 +9063,8 @@ if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { /* Init ath dfs pattern detector */ ar->ath_common.debug_mask = ATH_DBG_DFS; + ar->ath_common.dfs_pulse_valid_diff_ts = + ATH10K_DFS_PULSE_VALID_DIFF_TS; ar->dfs_detector = dfs_pattern_detector_init(&ar->ath_common, NL80211_DFS_UNSET); @@ -8972,6 +9082,15 @@ if (!ar->hw_params.hw_ops->set_coverage_class) ar->ops->set_coverage_class = NULL; + /* Current wake_tx_queue implementation imposes a significant + * performance penalty in some setups. The tx scheduling code needs + * more work anyway so disable the wake_tx_queue unless firmware + * supports the pull-push mechanism. + */ + if (!test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, + ar->running_fw->fw_file.fw_features)) + ar->ops->wake_tx_queue = NULL; + ret = ath_regd_init(&ar->ath_common.regulatory, ar->hw->wiphy, ath10k_reg_notifier); if (ret) { @@ -9002,6 +9121,9 @@ ar->hw->weight_multiplier = ATH10K_AIRTIME_WEIGHT_MULTIPLIER; + INIT_WORK(&ar->powerup_work, ath10k_powerup_work); + ar->powerup_pending = false; + ret = ieee80211_register_hw(ar->hw); if (ret) { ath10k_err(ar, "failed to register ieee80211: %d\n", ret); @@ -9013,16 +9135,20 @@ ar->hw->wiphy->software_iftypes |= BIT(NL80211_IFTYPE_AP_VLAN); } +#ifndef CONFIG_ATH_REG_IGNORE if (!ath_is_world_regd(&ar->ath_common.regulatory)) { ret = regulatory_hint(ar->hw->wiphy, ar->ath_common.regulatory.alpha2); if (ret) goto err_unregister; } +#endif return 0; +#ifndef CONFIG_ATH_REG_IGNORE err_unregister: +#endif ieee80211_unregister_hw(ar->hw); err_dfs_detector_exit: @@ -9040,6 +9166,7 @@ void ath10k_mac_unregister(struct ath10k *ar) { ieee80211_unregister_hw(ar->hw); + cancel_work_sync(&ar->powerup_work); if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED) && ar->dfs_detector) ar->dfs_detector->exit(ar->dfs_detector); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/pci.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/pci.c --- linux-5.4.60/drivers/net/wireless/ath/ath10k/pci.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/pci.c 2021-03-04 13:20:59.317505624 +0100 @@ -9,6 +9,7 @@ #include #include #include +#include #include "core.h" #include "debug.h" @@ -30,6 +31,7 @@ static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; +static char *fem_name; module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); @@ -37,6 +39,9 @@ module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); +module_param(fem_name, charp, 0660); +MODULE_PARM_DESC(fem_name, "force FEM type"); + /* how long wait to wait for target to initialise, in ms */ #define ATH10K_PCI_TARGET_WAIT 3000 #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 @@ -714,7 +719,8 @@ /* Check if the shared legacy irq is for us */ cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CAUSE_ADDRESS); - if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) + if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL) && + cause != 0xdeadbeef) return true; return false; @@ -2652,12 +2658,6 @@ return 0; } -static int ath10k_pci_qca99x0_soft_chip_reset(struct ath10k *ar) -{ - ath10k_pci_irq_disable(ar); - return ath10k_pci_qca99x0_chip_reset(ar); -} - static int ath10k_pci_safe_chip_reset(struct ath10k *ar) { struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); @@ -3498,7 +3498,7 @@ .get_num_banks = ath10k_pci_get_num_banks, }; -static int ath10k_pci_probe(struct pci_dev *pdev, +static int __ath10k_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pci_dev) { int ret = 0; @@ -3539,21 +3539,21 @@ case QCA99X0_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA99X0; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9984_1_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9984; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; case QCA9888_2_0_DEVICE_ID: hw_rev = ATH10K_HW_QCA9888; pci_ps = false; - pci_soft_reset = ath10k_pci_qca99x0_soft_chip_reset; + pci_soft_reset = NULL;; pci_hard_reset = ath10k_pci_qca99x0_chip_reset; targ_cpu_to_ce_addr = ath10k_pci_qca99x0_targ_cpu_to_ce_addr; break; @@ -3592,6 +3592,7 @@ ar_pci->targ_cpu_to_ce_addr = targ_cpu_to_ce_addr; ar->ce_priv = &ar_pci->ce; + ar->fem_name = fem_name; ar->id.vendor = pdev->vendor; ar->id.device = pdev->device; ar->id.subsystem_vendor = pdev->subsystem_vendor; @@ -3751,6 +3752,23 @@ ath10k_pci_pm_suspend, ath10k_pci_pm_resume); +static int ath10k_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *pci_dev) +{ + int cnt = 0; + int rv; + do { + rv = __ath10k_pci_probe(pdev, pci_dev); + if (rv == 0) + return rv; + + pr_err("ath10k: failed to probe PCI : %d, retry-count: %d\n", rv, cnt); + mdelay(10); /* let the ath10k firmware gerbil take a small break */ + } while (cnt++ < 3); + + return rv; +} + static struct pci_driver ath10k_pci_driver = { .name = "ath10k_pci", .id_table = ath10k_pci_id_table, diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/thermal.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/thermal.c --- linux-5.4.60/drivers/net/wireless/ath/ath10k/thermal.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/thermal.c 2021-03-04 13:20:59.320838957 +0100 @@ -160,7 +160,9 @@ if (!test_bit(WMI_SERVICE_THERM_THROT, ar->wmi.svc_map)) return 0; - cdev = thermal_cooling_device_register("ath10k_thermal", ar, + cdev = thermal_cooling_device_register_with_parent(ar->dev, + "ath10k_thermal", + ar, &ath10k_thermal_ops); if (IS_ERR(cdev)) { diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/wmi.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/wmi.c --- linux-5.4.60/drivers/net/wireless/ath/ath10k/wmi.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/wmi.c 2021-03-04 13:20:59.320838957 +0100 @@ -1681,10 +1681,11 @@ .bw160 = WMI_10_2_PEER_160MHZ, }; -void ath10k_wmi_put_wmi_channel(struct wmi_channel *ch, +void ath10k_wmi_put_wmi_channel(struct ath10k *ar, struct wmi_channel *ch, const struct wmi_channel_arg *arg) { u32 flags = 0; + struct ieee80211_channel *chan = NULL; memset(ch, 0, sizeof(*ch)); @@ -1700,13 +1701,35 @@ flags |= WMI_CHAN_FLAG_HT40_PLUS; if (arg->chan_radar) flags |= WMI_CHAN_FLAG_DFS; - + ch->band_center_freq2 = 0; ch->mhz = __cpu_to_le32(arg->freq); ch->band_center_freq1 = __cpu_to_le32(arg->band_center_freq1); - if (arg->mode == MODE_11AC_VHT80_80) + if (arg->mode == MODE_11AC_VHT80_80) { ch->band_center_freq2 = __cpu_to_le32(arg->band_center_freq2); - else - ch->band_center_freq2 = 0; + chan = ieee80211_get_channel(ar->hw->wiphy, + arg->band_center_freq2 - 10); + } + if (arg->mode == MODE_11AC_VHT160) { + if (arg->freq > arg->band_center_freq1) { + ch->band_center_freq1 = + __cpu_to_le32(arg->band_center_freq1 + 40); + /* Minus 40 to get secondary segment's center frequency + * And minus 10 to get a defined 5G channel frequency. + */ + chan = ieee80211_get_channel(ar->hw->wiphy, + arg->band_center_freq1 - 40 - 10); + } else { + ch->band_center_freq1 = + __cpu_to_le32(arg->band_center_freq1 - 40); + chan = ieee80211_get_channel(ar->hw->wiphy, + arg->band_center_freq1 + 40 - 10); + } + ch->band_center_freq2 = __cpu_to_le32(arg->band_center_freq1); + } + + if (chan && chan->flags & IEEE80211_CHAN_RADAR) + flags |= WMI_CHAN_FLAG_DFS_CFREQ2; + ch->min_power = arg->min_power; ch->max_power = arg->max_power; ch->reg_power = arg->max_reg_power; @@ -7089,7 +7112,7 @@ memcpy(cmd->ssid.ssid, arg->ssid, arg->ssid_len); } - ath10k_wmi_put_wmi_channel(&cmd->chan, &arg->channel); + ath10k_wmi_put_wmi_channel(ar, &cmd->chan, &arg->channel); ath10k_dbg(ar, ATH10K_DBG_WMI, "wmi vdev %s id 0x%x flags: 0x%0X, freq %d, mode %d, ch_flags: 0x%0X, max_power: %d\n", @@ -7461,7 +7484,7 @@ ch = &arg->channels[i]; ci = &cmd->chan_info[i]; - ath10k_wmi_put_wmi_channel(ci, ch); + ath10k_wmi_put_wmi_channel(ar, ci, ch); } return skb; @@ -7552,12 +7575,7 @@ struct wmi_10_4_peer_assoc_complete_cmd *cmd = buf; ath10k_wmi_peer_assoc_fill_10_2(ar, buf, arg); - if (arg->peer_bw_rxnss_override) - cmd->peer_bw_rxnss_override = - __cpu_to_le32((arg->peer_bw_rxnss_override - 1) | - BIT(PEER_BW_RXNSS_OVERRIDE_OFFSET)); - else - cmd->peer_bw_rxnss_override = 0; + cmd->peer_bw_rxnss_override = __cpu_to_le32(arg->peer_bw_rxnss_override); } static int @@ -8869,7 +8887,7 @@ for (i = 0; i < cap->peer_chan_len; i++) { chan = (struct wmi_channel *)&peer_cap->peer_chan_list[i]; - ath10k_wmi_put_wmi_channel(chan, &chan_arg[i]); + ath10k_wmi_put_wmi_channel(ar, chan, &chan_arg[i]); } ath10k_dbg(ar, ATH10K_DBG_WMI, diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/wmi.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/wmi.h --- linux-5.4.60/drivers/net/wireless/ath/ath10k/wmi.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/wmi.h 2021-03-04 13:20:59.320838957 +0100 @@ -2085,6 +2085,8 @@ /* Indicate reason for channel switch */ #define WMI_CHANNEL_CHANGE_CAUSE_CSA (1 << 13) +/* DFS required on channel for 2nd segment of VHT160 and VHT80+80*/ +#define WMI_CHAN_FLAG_DFS_CFREQ2 (1 << 15) #define WMI_MAX_SPATIAL_STREAM 3 /* default max ss */ @@ -6478,7 +6480,19 @@ __le32 info0; /* WMI_PEER_ASSOC_INFO0_ */ } __packed; -#define PEER_BW_RXNSS_OVERRIDE_OFFSET 31 +#define BW_NSS_FWCONF_MAP_ENABLE BIT(31) +#define BW_NSS_FWCONF_MAP_160MHZ_LSB (0) +#define BW_NSS_FWCONF_MAP_160MHZ_MASK (0x00000007) +#define BW_NSS_FWCONF_MAP_80_80MHZ_LSB (3) +#define BW_NSS_FWCONF_MAP_80_80MHZ_MASK (0x00000038) +#define BW_NSS_FWCONF_MAP_MASK (0x0000003F) + +#define GET_BW_NSS_FWCONF_160(x) (MS(x, BW_NSS_FWCONF_MAP_160MHZ) + 1) +#define GET_BW_NSS_FWCONF_80_80(x) (MS(x, BW_NSS_FWCONF_MAP_80_80MHZ) + 1) + +/* Values defined to set 160 MHz Bandwidth NSS Mapping into FW*/ +#define BW_NSS_FWCONF_160(x) (BW_NSS_FWCONF_MAP_ENABLE | SM(x - 1, BW_NSS_FWCONF_MAP_160MHZ)) +#define BW_NSS_FWCONF_80_80(x) (BW_NSS_FWCONF_MAP_ENABLE | SM(x - 1, BW_NSS_FWCONF_MAP_80_80MHZ)) struct wmi_10_4_peer_assoc_complete_cmd { struct wmi_10_2_peer_assoc_complete_cmd cmd; @@ -7312,7 +7326,7 @@ const struct wmi_start_scan_arg *arg); void ath10k_wmi_set_wmm_param(struct wmi_wmm_params *params, const struct wmi_wmm_params_arg *arg); -void ath10k_wmi_put_wmi_channel(struct wmi_channel *ch, +void ath10k_wmi_put_wmi_channel(struct ath10k *ar, struct wmi_channel *ch, const struct wmi_channel_arg *arg); int ath10k_wmi_start_scan_verify(const struct wmi_start_scan_arg *arg); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath10k/wmi-tlv.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.c --- linux-5.4.60/drivers/net/wireless/ath/ath10k/wmi-tlv.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath10k/wmi-tlv.c 2021-03-04 13:20:59.320838957 +0100 @@ -2063,7 +2063,7 @@ tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_CHANNEL); tlv->len = __cpu_to_le16(sizeof(*ch)); ch = (void *)tlv->value; - ath10k_wmi_put_wmi_channel(ch, &arg->channel); + ath10k_wmi_put_wmi_channel(ar, ch, &arg->channel); ptr += sizeof(*tlv); ptr += sizeof(*ch); @@ -2703,7 +2703,7 @@ tlv->len = __cpu_to_le16(sizeof(*ci)); ci = (void *)tlv->value; - ath10k_wmi_put_wmi_channel(ci, ch); + ath10k_wmi_put_wmi_channel(ar, ci, ch); chans += sizeof(*tlv); chans += sizeof(*ci); @@ -3404,7 +3404,7 @@ tlv->tag = __cpu_to_le16(WMI_TLV_TAG_STRUCT_CHANNEL); tlv->len = __cpu_to_le16(sizeof(*chan)); chan = (void *)tlv->value; - ath10k_wmi_put_wmi_channel(chan, &chan_arg[i]); + ath10k_wmi_put_wmi_channel(ar, chan, &chan_arg[i]); ptr += sizeof(*tlv); ptr += sizeof(*chan); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/ar9003_calib.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ar9003_calib.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/ar9003_calib.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ar9003_calib.c 2021-03-04 13:20:59.334172292 +0100 @@ -165,6 +165,8 @@ if (ret < 0) return ret; + ath9k_hw_update_cca_threshold(ah); + /* start NF calibration, without updating BB NF register */ ath9k_hw_start_nfcal(ah, false); } diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/ar9003_phy.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/ar9003_phy.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.c 2021-03-04 13:20:59.334172292 +0100 @@ -1927,6 +1927,116 @@ } } +/* + * Adaptive CCA threshold - Calculate and update CCA threshold periodically + * after NF calibration and at the end of initialization sequence during every + * chip reset. + * + * Step 1: Compute NF_max_primary and NF_max_extension + * If noise floor completes, + * NF_max_primary = max of noise floor read across all chains in primary channel + * NF_max_extension = max of noise floor read across all chains in extension channel + * else + * NF_max_primary = NF_max_extension = the value that is forced into HW as noise floor + * + * Step 2: Compute CCA_threshold_primary and CCA_threshold_extension + * CCA_threshold_primary = CCA_detection_level – CCA_detection_margin – NF_max_primary + * CCA_threshold_extension = CCA_detection_level – CCA_detection_margin – NF_max_extension + * + * Step 3: Program CCA thresholds + * + */ +void ar9003_update_cca_threshold(struct ath_hw *ah) +{ + struct ath9k_hw_cal_data *cal = ah->caldata; + struct ath9k_nfcal_hist *h; + u_int16_t cca_detection_margin_pri, cca_detection_margin_ext; + int16_t nf, nf_max_primary, nf_max_extension, nf_nominal, + derived_max_cca, max_cca_cap, cca_threshold_primary, + cca_threshold_extension; + u_int8_t chainmask; + int chan, chain, i, init_nf = 0; + + if (!ah->adaptive_cca_threshold_enabled) + return; + + if (!cal) + return; + + h = cal->nfCalHist; + + if (IS_CHAN_2GHZ(ah->curchan)) + nf = ah->nf_2g.max; + else + nf = ah->nf_5g.max; + + nf_max_primary = nf_max_extension = nf; + + chainmask = ah->rxchainmask & ah->caps.rx_chainmask; + + /* Compute max of noise floor read across all chains in primary channel */ + for (chan = 0; chan < 2 /*ctl,ext*/; chan++) { + ath_dbg(ath9k_hw_common(ah), CALIBRATE, "chan: %s\n", + !chan ? "ctrl" : "extn"); + + for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) { + if (!((chainmask >> chain) & 0x1)) + continue; + + i = chan * AR9300_MAX_CHAINS + chain; + if (!init_nf) { + nf = h[i].privNF; + init_nf = 1; + } + + ath_dbg(ath9k_hw_common(ah), CALIBRATE, "privNF[%d]: %d\n", + i, h[i].privNF); + nf = (nf > h[i].privNF) ? nf : h[i].privNF; + } + + if (!chan) + nf_max_primary = nf; + else + nf_max_extension = nf; + } + + if (IS_CHAN_HT40(ah->curchan)) + nf_nominal = NF_NOM_40MHZ; + else + nf_nominal = NF_NOM_20MHZ; + + cca_detection_margin_pri = ah->cca_detection_margin; + if (nf_max_primary < nf_nominal) + cca_detection_margin_pri += (nf_nominal - nf_max_primary); + + cca_detection_margin_ext = ah->cca_detection_margin; + if (nf_max_extension < nf_nominal) + cca_detection_margin_ext += (nf_nominal - nf_max_extension); + + derived_max_cca = ah->cca_detection_level - ah->cca_detection_margin - BEST_CASE_NOISE_FLOOR; + max_cca_cap = derived_max_cca < MAX_CCA_THRESHOLD ? derived_max_cca : MAX_CCA_THRESHOLD; + + ath_dbg(ath9k_hw_common(ah), CALIBRATE, "derived_max_cca: %d, max_cca_cap: %d\n", + derived_max_cca, max_cca_cap); + + cca_threshold_primary = ah->cca_detection_level - cca_detection_margin_pri - nf_max_primary; + cca_threshold_primary = cca_threshold_primary < max_cca_cap ? + (cca_threshold_primary > MIN_CCA_THRESHOLD ? + cca_threshold_primary : MIN_CCA_THRESHOLD) : max_cca_cap; + cca_threshold_extension = ah->cca_detection_level - cca_detection_margin_ext - nf_max_extension; + cca_threshold_extension = cca_threshold_extension < max_cca_cap ? + (cca_threshold_extension > MIN_CCA_THRESHOLD ? + cca_threshold_extension : MIN_CCA_THRESHOLD) : max_cca_cap; + + ath_dbg(ath9k_hw_common(ah), CALIBRATE, + "nf_max_primary: %d, nf_max_extension: %d, cca_pri: %d, cca_ext: %d\n", + nf_max_primary, nf_max_extension, cca_threshold_primary, cca_threshold_extension); + + REG_RMW_FIELD(ah, AR_PHY_CCA_0, AR_PHY_CCA_THRESH62, cca_threshold_primary); + REG_RMW_FIELD(ah, AR_PHY_EXTCHN_PWRTHR1, AR_PHY_EXT_CCA0_THRESH62, cca_threshold_extension); + REG_RMW_FIELD(ah, AR_PHY_CCA_CTRL_0, AR_PHY_EXT_CCA0_THRESH62_MODE, 0x0); +} + void ar9003_hw_attach_phy_ops(struct ath_hw *ah) { struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); @@ -1962,6 +2072,7 @@ priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; priv_ops->set_radar_params = ar9003_hw_set_radar_params; priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; + priv_ops->update_cca_threshold = ar9003_update_cca_threshold; ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/ar9003_phy.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.h --- linux-5.4.60/drivers/net/wireless/ath/ath9k/ar9003_phy.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ar9003_phy.h 2021-03-04 13:20:59.334172292 +0100 @@ -399,6 +399,8 @@ #define AR_PHY_EXT_CCA0_THRESH62_S 0 #define AR_PHY_EXT_CCA0_THRESH62_1 0x000001FF #define AR_PHY_EXT_CCA0_THRESH62_1_S 0 +#define AR_PHY_EXT_CCA0_THRESH62_MODE 0x00040000 +#define AR_PHY_EXT_CCA0_THRESH62_MODE_S 18 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0 @@ -1326,4 +1328,10 @@ #define AR9300_DFS_FIRPWR -28 +#define BEST_CASE_NOISE_FLOOR -130 +#define MAX_CCA_THRESHOLD 90 +#define MIN_CCA_THRESHOLD 0 +#define NF_NOM_20MHZ -101 +#define NF_NOM_40MHZ -98 + #endif /* AR9003_PHY_H */ diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/ath9k.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ath9k.h --- linux-5.4.60/drivers/net/wireless/ath/ath9k/ath9k.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/ath9k.h 2021-03-04 13:20:59.334172292 +0100 @@ -1150,4 +1150,18 @@ static inline void ath_ahb_exit(void) {}; #endif +#ifdef CONFIG_ATH9K_TX99 +extern int ath9k_enable_tx99; + +static inline bool ath9k_tx99_enabled(void) +{ + return ath9k_enable_tx99 > 0; +} +#else +static inline bool ath9k_tx99_enabled(void) +{ + return false; +} +#endif + #endif /* ATH9K_H */ diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/calib.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/calib.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/calib.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/calib.c 2021-03-04 13:20:59.337505624 +0100 @@ -230,12 +230,17 @@ REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF); + if (ah->adaptive_cca_threshold_enabled) { + REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, + AR_PHY_AGC_CONTROL_NO_UPDATE_NF); + } else { if (update) REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); else REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF); + } REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); } @@ -472,9 +477,13 @@ * the baseband update the internal NF value itself, similar to * what is being done after a full reset. */ - if (!test_bit(NFCAL_PENDING, &caldata->cal_flags)) - ath9k_hw_start_nfcal(ah, true); - else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) + if (!test_bit(NFCAL_PENDING, &caldata->cal_flags)) { + bool do_fast_recalib; + + ath9k_hw_update_cca_threshold(ah); + do_fast_recalib = !ah->adaptive_cca_threshold_enabled; + ath9k_hw_start_nfcal(ah, do_fast_recalib); + } else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) ath9k_hw_getnf(ah, ah->curchan); set_bit(NFCAL_INTF, &caldata->cal_flags); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/debug.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/debug.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/debug.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/debug.c 2021-03-04 13:20:59.337505624 +0100 @@ -1237,6 +1237,101 @@ .llseek = default_llseek, }; +static ssize_t read_file_cca_detection_level(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + char buf[32]; + unsigned int len; + + len = sprintf(buf, "%d\n", ah->cca_detection_level); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t write_file_cca_detection_level(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + long val; + char buf[32]; + ssize_t len; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + + if (kstrtol(buf, 0, &val)) + return -EINVAL; + + if (val > 0) + return -EINVAL; + + ah->cca_detection_level = val; + + return count; +} + +static const struct file_operations fops_cca_detection_level = { + .read = read_file_cca_detection_level, + .write = write_file_cca_detection_level, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + +static ssize_t read_file_cca_detection_margin(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + char buf[32]; + unsigned int len; + + len = sprintf(buf, "%d\n", ah->cca_detection_margin); + + return simple_read_from_buffer(user_buf, count, ppos, buf, len); +} + +static ssize_t write_file_cca_detection_margin(struct file *file, + const char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct ath_softc *sc = file->private_data; + struct ath_hw *ah = sc->sc_ah; + unsigned long val; + char buf[32]; + ssize_t len; + + len = min(count, sizeof(buf) - 1); + if (copy_from_user(buf, user_buf, len)) + return -EFAULT; + + buf[len] = '\0'; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + ah->cca_detection_margin = val; + + return count; +} + +static const struct file_operations fops_cca_detection_margin = { + .read = read_file_cca_detection_margin, + .write = write_file_cca_detection_margin, + .open = simple_open, + .owner = THIS_MODULE, + .llseek = default_llseek, +}; + /* Ethtool support for get-stats */ #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO" @@ -1445,6 +1540,11 @@ debugfs_create_file("nf_override", 0600, sc->debug.debugfs_phy, sc, &fops_nf_override); - + debugfs_create_file("cca_detection_level", 0600, + sc->debug.debugfs_phy, sc, &fops_cca_detection_level); + debugfs_create_file("cca_detection_margin", 0600, + sc->debug.debugfs_phy, sc, &fops_cca_detection_margin); + debugfs_create_bool("adaptive_cca_threshold_enabled", 0600, sc->debug.debugfs_phy, + &sc->sc_ah->adaptive_cca_threshold_enabled); return 0; } diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/hw.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/hw.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/hw.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/hw.c 2021-03-04 13:20:59.340838958 +0100 @@ -396,6 +396,7 @@ { struct ath_common *common = ath9k_hw_common(ah); + ah->config.dma_beacon_response_time = 1; ah->config.sw_beacon_response_time = 6; ah->config.cwm_ignore_extcca = false; @@ -1839,6 +1840,7 @@ ar9003_mci_2g5g_switch(ah, false); ath9k_hw_loadnf(ah, ah->curchan); + ath9k_hw_update_cca_threshold(ah); ath9k_hw_start_nfcal(ah, true); if (AR_SREV_9271(ah)) @@ -2064,6 +2066,7 @@ if (AR_SREV_9300_20_OR_LATER(ah)) { ath9k_hw_loadnf(ah, chan); + ath9k_hw_update_cca_threshold(ah); ath9k_hw_start_nfcal(ah, true); } diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/hw.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/hw.h --- linux-5.4.60/drivers/net/wireless/ath/ath9k/hw.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/hw.h 2021-03-04 13:20:59.340838958 +0100 @@ -666,7 +666,7 @@ struct ath_hw_radar_conf *conf); int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan, u8 *ini_reloaded); - + void (*update_cca_threshold)(struct ath_hw *ah); /* ANI */ void (*ani_cache_ini_regs)(struct ath_hw *ah); @@ -983,6 +983,10 @@ bool msi_enabled; u32 msi_mask; u32 msi_reg; + + bool adaptive_cca_threshold_enabled; + s16 cca_detection_level; + u16 cca_detection_margin; }; struct ath_bus_ops { diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/hw-ops.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/hw-ops.h --- linux-5.4.60/drivers/net/wireless/ath/ath9k/hw-ops.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/hw-ops.h 2021-03-04 13:20:59.340838958 +0100 @@ -260,6 +260,14 @@ ath9k_hw_private_ops(ah)->set_radar_params(ah, &ah->radar_conf); } +static inline void ath9k_hw_update_cca_threshold(struct ath_hw *ah) +{ + if (!ath9k_hw_private_ops(ah)->update_cca_threshold) + return; + + ath9k_hw_private_ops(ah)->update_cca_threshold(ah); +} + static inline void ath9k_hw_init_cal_settings(struct ath_hw *ah) { ath9k_hw_private_ops(ah)->init_cal_settings(ah); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/init.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/init.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/init.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/init.c 2021-03-04 13:20:59.340838958 +0100 @@ -80,6 +80,16 @@ module_param_named(use_msi, ath9k_use_msi, int, 0444); MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible"); +int ath9k_use_adaptive_cca; +module_param_named(use_adaptive_cca, ath9k_use_adaptive_cca, int, 0444); +MODULE_PARM_DESC(use_adaptive_cca, "enable adaptive cca by default"); + +#ifdef CONFIG_ATH9K_TX99 +int ath9k_enable_tx99; +module_param_named(enable_tx99, ath9k_enable_tx99, int, 0444); +MODULE_PARM_DESC(enable_tx99, "Enable TX99, which will disable STA/AP mode support"); +#endif + bool is_ath9k_unloaded; #ifdef CONFIG_MAC80211_LEDS @@ -666,6 +676,9 @@ ah->hw_version.devid = devid; ah->ah_flags |= AH_USE_EEPROM; ah->led_pin = -1; + ah->cca_detection_level = -70; + ah->cca_detection_margin = 3; + ah->adaptive_cca_threshold_enabled = ath9k_use_adaptive_cca; ah->reg_ops.read = ath9k_ioread32; ah->reg_ops.multi_read = ath9k_multi_ioread32; ah->reg_ops.write = ath9k_iowrite32; @@ -694,6 +707,7 @@ common->debug_mask = ath9k_debug; common->btcoex_enabled = ath9k_btcoex_enable == 1; common->disable_ani = false; + common->dfs_pulse_valid_diff_ts = 0; /* * Platform quirks. @@ -946,7 +960,7 @@ NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE | NL80211_FEATURE_P2P_GO_CTWIN; - if (!IS_ENABLED(CONFIG_ATH9K_TX99)) { + if (!ath9k_tx99_enabled()) { hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_P2P_GO) | BIT(NL80211_IFTYPE_P2P_CLIENT) | diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/main.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/main.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/main.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/main.c 2021-03-04 13:20:59.340838958 +0100 @@ -1252,7 +1252,7 @@ struct ath_node *an = &avp->mcast_node; mutex_lock(&sc->mutex); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) { + if (ath9k_tx99_enabled()) { if (sc->cur_chan->nvifs >= 1) { mutex_unlock(&sc->mutex); return -EOPNOTSUPP; @@ -1302,7 +1302,7 @@ mutex_lock(&sc->mutex); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) { + if (ath9k_tx99_enabled()) { mutex_unlock(&sc->mutex); return -EOPNOTSUPP; } @@ -1362,7 +1362,7 @@ struct ath_hw *ah = sc->sc_ah; struct ath_common *common = ath9k_hw_common(ah); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return; sc->ps_enabled = true; @@ -1381,7 +1381,7 @@ struct ath_hw *ah = sc->sc_ah; struct ath_common *common = ath9k_hw_common(ah); - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return; sc->ps_enabled = false; @@ -1962,7 +1962,7 @@ unsigned long flags; int pos; - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return -EOPNOTSUPP; spin_lock_irqsave(&common->cc_lock, flags); @@ -2012,7 +2012,7 @@ struct ath_softc *sc = hw->priv; struct ath_hw *ah = sc->sc_ah; - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return; mutex_lock(&sc->mutex); diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath9k/recv.c linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/recv.c --- linux-5.4.60/drivers/net/wireless/ath/ath9k/recv.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath9k/recv.c 2021-03-04 13:20:59.340838958 +0100 @@ -377,7 +377,7 @@ struct ath_common *common = ath9k_hw_common(sc->sc_ah); u32 rfilt; - if (IS_ENABLED(CONFIG_ATH9K_TX99)) + if (ath9k_tx99_enabled()) return 0; rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST diff -ruw linux-5.4.60/drivers/net/wireless/ath/ath.h linux-5.4.60-fbx/drivers/net/wireless/ath/ath.h --- linux-5.4.60/drivers/net/wireless/ath/ath.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/ath.h 2021-03-04 13:20:59.314172291 +0100 @@ -184,6 +184,8 @@ int last_rssi; struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; + + int dfs_pulse_valid_diff_ts; }; static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common) diff -ruw linux-5.4.60/drivers/net/wireless/ath/dfs_pattern_detector.c linux-5.4.60-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c --- linux-5.4.60/drivers/net/wireless/ath/dfs_pattern_detector.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/dfs_pattern_detector.c 2021-03-04 13:20:59.344172292 +0100 @@ -273,6 +273,7 @@ { u32 i; struct channel_detector *cd; + int diff_ts; /* * pulses received for a non-supported or un-initialized @@ -285,8 +286,9 @@ if (cd == NULL) return false; + diff_ts = event->ts - dpd->last_pulse_ts; /* reset detector on time stamp wraparound, caused by TSF reset */ - if (event->ts < dpd->last_pulse_ts) + if (diff_ts < dpd->common->dfs_pulse_valid_diff_ts) dpd_reset(dpd); dpd->last_pulse_ts = event->ts; diff -ruw linux-5.4.60/drivers/net/wireless/ath/dfs_pattern_detector.h linux-5.4.60-fbx/drivers/net/wireless/ath/dfs_pattern_detector.h --- linux-5.4.60/drivers/net/wireless/ath/dfs_pattern_detector.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/dfs_pattern_detector.h 2021-03-04 13:20:59.344172292 +0100 @@ -24,7 +24,7 @@ /* tolerated deviation of radar time stamp in usecs on both sides * TODO: this might need to be HW-dependent */ -#define PRI_TOLERANCE 16 +#define PRI_TOLERANCE 6 /** * struct ath_dfs_pool_stats - DFS Statistics for global pools diff -ruw linux-5.4.60/drivers/net/wireless/ath/Kconfig linux-5.4.60-fbx/drivers/net/wireless/ath/Kconfig --- linux-5.4.60/drivers/net/wireless/ath/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/Kconfig 2021-03-04 13:20:59.310838957 +0100 @@ -37,6 +37,9 @@ This option enables tracepoints for atheros wireless drivers. Currently, ath9k makes use of this facility. +config ATH_REG_IGNORE + bool "ignore all eeprom regulation" + config ATH_REG_DYNAMIC_USER_REG_HINTS bool "Atheros dynamic user regulatory hints" depends on CFG80211_CERTIFICATION_ONUS diff -ruw linux-5.4.60/drivers/net/wireless/ath/key.c linux-5.4.60-fbx/drivers/net/wireless/ath/key.c --- linux-5.4.60/drivers/net/wireless/ath/key.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/key.c 2021-03-04 13:20:59.344172292 +0100 @@ -524,7 +524,7 @@ idx = ath_reserve_key_cache_slot(common, key->cipher); break; default: - idx = key->keyidx; + idx = ath_reserve_key_cache_slot(common, key->cipher); break; } } else if (key->keyidx) { diff -ruw linux-5.4.60/drivers/net/wireless/ath/regd.c linux-5.4.60-fbx/drivers/net/wireless/ath/regd.c --- linux-5.4.60/drivers/net/wireless/ath/regd.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/ath/regd.c 2021-03-04 13:20:59.344172292 +0100 @@ -345,6 +345,10 @@ struct ieee80211_channel *ch; unsigned int i; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif + for (band = 0; band < NUM_NL80211_BANDS; band++) { if (!wiphy->bands[band]) continue; @@ -378,6 +382,10 @@ { struct ieee80211_supported_band *sband; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif + sband = wiphy->bands[NL80211_BAND_2GHZ]; if (!sband) return; @@ -407,6 +415,9 @@ struct ieee80211_channel *ch; unsigned int i; +#ifdef CONFIG_ATH_REG_IGNORE + return; +#endif if (!wiphy->bands[NL80211_BAND_5GHZ]) return; @@ -639,6 +650,11 @@ const struct ieee80211_regdomain *regd; wiphy->reg_notifier = reg_notifier; + +#ifdef CONFIG_ATH_REG_IGNORE + return 0; +#endif + wiphy->regulatory_flags |= REGULATORY_STRICT_REG | REGULATORY_CUSTOM_REG; @@ -703,7 +719,7 @@ regdmn == CTRY_DEFAULT) { printk(KERN_DEBUG "ath: EEPROM indicates default " "country code should be used\n"); - reg->country_code = CTRY_UNITED_STATES; + reg->country_code = CTRY_FRANCE; } if (reg->country_code == CTRY_DEFAULT) { diff -ruw linux-5.4.60/drivers/net/wireless/marvell/Kconfig linux-5.4.60-fbx/drivers/net/wireless/marvell/Kconfig --- linux-5.4.60/drivers/net/wireless/marvell/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/marvell/Kconfig 2021-03-04 13:20:59.414172295 +0100 @@ -25,4 +25,8 @@ To compile this driver as a module, choose M here: the module will be called mwl8k. If unsure, say N. +config MWL8K_NEW + tristate "Marvell 88W8xxx PCI/PCIe NEW" + depends on MAC80211 && PCI + endif # WLAN_VENDOR_MARVELL diff -ruw linux-5.4.60/drivers/net/wireless/marvell/Makefile linux-5.4.60-fbx/drivers/net/wireless/marvell/Makefile --- linux-5.4.60/drivers/net/wireless/marvell/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/net/wireless/marvell/Makefile 2021-03-04 13:20:59.414172295 +0100 @@ -5,3 +5,4 @@ obj-$(CONFIG_MWIFIEX) += mwifiex/ obj-$(CONFIG_MWL8K) += mwl8k.o +obj-$(CONFIG_MWL8K_NEW) += mwl8k_new/ diff -ruw linux-5.4.60/drivers/nvmem/core.c linux-5.4.60-fbx/drivers/nvmem/core.c --- linux-5.4.60/drivers/nvmem/core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/nvmem/core.c 2021-03-04 13:20:59.504172299 +0100 @@ -396,8 +396,10 @@ config->name ? config->id : nvmem->id); } +#ifndef CONFIG_NVMEM_IGNORE_RO nvmem->read_only = device_property_present(config->dev, "read-only") || config->read_only || !nvmem->reg_write; +#endif nvmem->dev.groups = nvmem_sysfs_get_groups(nvmem, config); diff -ruw linux-5.4.60/drivers/nvmem/Kconfig linux-5.4.60-fbx/drivers/nvmem/Kconfig --- linux-5.4.60/drivers/nvmem/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/nvmem/Kconfig 2021-03-04 13:20:59.504172299 +0100 @@ -24,6 +24,9 @@ This interface is mostly used by userspace applications to read/write directly into nvmem. +config NVMEM_IGNORE_RO + bool "ignore read-only flags" + config NVMEM_IMX_IIM tristate "i.MX IC Identification Module support" depends on ARCH_MXC || COMPILE_TEST diff -ruw linux-5.4.60/drivers/of/fdt.c linux-5.4.60-fbx/drivers/of/fdt.c --- linux-5.4.60/drivers/of/fdt.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/of/fdt.c 2021-03-04 13:20:59.507505632 +0100 @@ -28,6 +28,7 @@ #include /* for COMMAND_LINE_SIZE */ #include +#include #include "of_private.h" @@ -745,6 +746,39 @@ return 0; } +/* + * iterate list of built-in dtb to find a compatible match + */ +const void __init *of_fdt_find_compatible_dtb(const char *name) +{ + struct fdt_header { + __be32 magic; + __be32 totalsize; + }; + const struct fdt_header *blob, *best; + unsigned int best_score = ~0; + + best = NULL; + blob = (const struct fdt_header *)__dtb_start; + while ((void *)blob < (void *)__dtb_end && + (be32_to_cpu(blob->magic) == OF_DT_HEADER)) { + unsigned int score; + u32 size; + + score = of_fdt_is_compatible(blob, 0, name); + if (score > 0 && score < best_score) { + best = blob; + best_score = score; + } + + size = be32_to_cpu(blob->totalsize); + blob = (const struct fdt_header *) + PTR_ALIGN((void *)blob + size, STRUCT_ALIGNMENT); + } + + return best; +} + /** * of_flat_dt_is_compatible - Return true if given node has compat in compatible list * @node: node to test @@ -1040,6 +1074,40 @@ return 0; } +#ifdef CONFIG_RANDOM_OF +/* + * get random seed area from device tree, and reserve it early enough + * so that it remains untouched until we can properly add it to the + * entropy pool. + */ +extern u64 random_seed_start; +extern u64 random_seed_size; + +static void __init early_init_dt_handle_random_seed(unsigned long node) +{ + const __be32 *prop; + int len; + + prop = of_get_flat_dt_prop(node, "fbx,random-seed", &len); + if (!prop) + return; + + if (len != 16) { + pr_err("bad fbx,random-seed size %d vs %d!\n", 16, len); + return ; + } + + random_seed_start = dt_mem_next_cell(2, &prop); + random_seed_size = dt_mem_next_cell(2, &prop); + + memblock_reserve(random_seed_start, random_seed_size); +} +#else +static inline void early_init_dt_handle_random_seed(unsigned long node) +{ +} +#endif + int __init early_init_dt_scan_chosen(unsigned long node, const char *uname, int depth, void *data) { @@ -1092,6 +1160,8 @@ fdt_totalsize(initial_boot_params)); } + early_init_dt_handle_random_seed(node); + /* break now */ return 1; } diff -ruw linux-5.4.60/drivers/of/Kconfig linux-5.4.60-fbx/drivers/of/Kconfig --- linux-5.4.60/drivers/of/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/of/Kconfig 2021-03-04 13:20:59.504172299 +0100 @@ -35,6 +35,11 @@ If unsure, say N here, but this option is safe to enable. +config OF_DTB_BUILTIN_LIST + string "Link given list of DTB files into kernel" + help + Specify filename without .dtb extension + config OF_FLATTREE bool select DTC @@ -103,6 +108,13 @@ config OF_NUMA bool +config OF_CONFIGFS + bool "Device Tree Overlay ConfigFS interface" + select CONFIGFS_FS + select OF_OVERLAY + help + Enable a simple user-space driven DT overlay interface. + config OF_DMA_DEFAULT_COHERENT # arches should select this if DMA is coherent by default for OF devices bool diff -ruw linux-5.4.60/drivers/of/Makefile linux-5.4.60-fbx/drivers/of/Makefile --- linux-5.4.60/drivers/of/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/of/Makefile 2021-03-04 13:20:59.504172299 +0100 @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-y = base.o device.o platform.o property.o obj-$(CONFIG_OF_KOBJ) += kobj.o +obj-$(CONFIG_OF_CONFIGFS) += configfs.o obj-$(CONFIG_OF_DYNAMIC) += dynamic.o obj-$(CONFIG_OF_FLATTREE) += fdt.o obj-$(CONFIG_OF_EARLY_FLATTREE) += fdt_address.o diff -ruw linux-5.4.60/drivers/of/of_net.c linux-5.4.60-fbx/drivers/of/of_net.c --- linux-5.4.60/drivers/of/of_net.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/of/of_net.c 2021-03-04 13:20:59.507505632 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include /** * of_get_phy_mode - Get phy mode for given device_node @@ -97,6 +98,13 @@ const void *of_get_mac_address(struct device_node *np) { const void *addr; +#ifdef CONFIG_FBXSERIAL + struct property *pp; + + pp = of_find_property(np, "fbxserial-mac-address", NULL); + if (pp && pp->length == 4) + return fbxserialinfo_get_mac_addr(be32_to_cpu(*(u32*)pp->value)); +#endif addr = of_get_mac_addr(np, "mac-address"); if (addr) diff -ruw linux-5.4.60/drivers/of/overlay.c linux-5.4.60-fbx/drivers/of/overlay.c --- linux-5.4.60/drivers/of/overlay.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/of/overlay.c 2021-03-04 13:20:59.507505632 +0100 @@ -362,7 +362,7 @@ } if (!of_node_check_flag(target->np, OF_OVERLAY)) - pr_err("WARNING: memory leak will occur if overlay removed, property: %pOF/%s\n", + pr_debug("WARNING: memory leak will occur if overlay removed, property: %pOF/%s\n", target->np, new_prop->name); if (ret) { diff -ruw linux-5.4.60/drivers/pci/controller/Kconfig linux-5.4.60-fbx/drivers/pci/controller/Kconfig --- linux-5.4.60/drivers/pci/controller/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/pci/controller/Kconfig 2021-03-04 13:20:59.514172300 +0100 @@ -265,6 +265,11 @@ This can lead to data corruption if drivers perform concurrent config and MMIO accesses. +config PCIE_BCM63XX + tristate "BCM63XX SoCs PCIe endpoint driver." + depends on ARCH_BCM63XX || COMPILE_TEST + depends on OF + config VMD depends on PCI_MSI && X86_64 && SRCU select X86_DEV_DMA_OPS diff -ruw linux-5.4.60/drivers/pci/controller/Makefile linux-5.4.60-fbx/drivers/pci/controller/Makefile --- linux-5.4.60/drivers/pci/controller/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/pci/controller/Makefile 2021-03-04 13:20:59.514172300 +0100 @@ -29,6 +29,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o +obj-$(CONFIG_PCIE_BCM63XX) += pcie-bcm63xx.o obj-$(CONFIG_VMD) += vmd.o # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW obj-y += dwc/ diff -ruw linux-5.4.60/drivers/pci/quirks.c linux-5.4.60-fbx/drivers/pci/quirks.c --- linux-5.4.60/drivers/pci/quirks.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/pci/quirks.c 2021-03-04 13:20:59.527505633 +0100 @@ -3083,6 +3083,8 @@ dev->is_hotplug_bridge = 1; } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PI7C9X20303SL, + quirk_hotplug_bridge); /* * This is a quirk for the Ricoh MMC controller found as a part of some diff -ruw linux-5.4.60/drivers/phy/broadcom/Kconfig linux-5.4.60-fbx/drivers/phy/broadcom/Kconfig --- linux-5.4.60/drivers/phy/broadcom/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/phy/broadcom/Kconfig 2021-03-04 13:20:59.537505634 +0100 @@ -29,6 +29,11 @@ help Enable this to support the Broadcom Kona USB 2.0 PHY. +config PHY_BRCM_USB_63138 + tristate "Broadcom 63138 USB 2.0/3.0 PHY Driver" + depends on ARCH_BCM_63XX || COMPILE_TEST + select GENERIC_PHY + config PHY_BCM_NS_USB2 tristate "Broadcom Northstar USB 2.0 PHY Driver" depends on ARCH_BCM_IPROC || COMPILE_TEST diff -ruw linux-5.4.60/drivers/phy/broadcom/Makefile linux-5.4.60-fbx/drivers/phy/broadcom/Makefile --- linux-5.4.60/drivers/phy/broadcom/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/phy/broadcom/Makefile 2021-03-04 13:20:59.537505634 +0100 @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PHY_CYGNUS_PCIE) += phy-bcm-cygnus-pcie.o +obj-$(CONFIG_PHY_BRCM_USB_63138) += phy-brcm-usb-63138.o obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o obj-$(CONFIG_PHY_BCM_NS_USB2) += phy-bcm-ns-usb2.o obj-$(CONFIG_PHY_BCM_NS_USB3) += phy-bcm-ns-usb3.o diff -ruw linux-5.4.60/drivers/phy/Kconfig linux-5.4.60-fbx/drivers/phy/Kconfig --- linux-5.4.60/drivers/phy/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/phy/Kconfig 2021-03-04 13:20:59.537505634 +0100 @@ -49,6 +49,10 @@ help This option enables support for APM X-Gene SoC multi-purpose PHY. +config XDSL_PHY_API + tristate "xDSL PHY API" + select GENERIC_PHY + source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/broadcom/Kconfig" diff -ruw linux-5.4.60/drivers/phy/Makefile linux-5.4.60-fbx/drivers/phy/Makefile --- linux-5.4.60/drivers/phy/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/phy/Makefile 2021-03-04 13:20:59.537505634 +0100 @@ -8,6 +8,8 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o obj-$(CONFIG_PHY_XGENE) += phy-xgene.o obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o +obj-$(CONFIG_XDSL_PHY_API) += xdsl_phy_api.o + obj-$(CONFIG_ARCH_SUNXI) += allwinner/ obj-$(CONFIG_ARCH_MESON) += amlogic/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff -ruw linux-5.4.60/drivers/phy/marvell/Kconfig linux-5.4.60-fbx/drivers/phy/marvell/Kconfig --- linux-5.4.60/drivers/phy/marvell/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/phy/marvell/Kconfig 2021-03-04 13:20:59.540838967 +0100 @@ -103,3 +103,11 @@ The PHY driver will be used by Marvell udc/ehci/otg driver. To compile this driver as a module, choose M here. + +config PHY_UTMI_CP110 + bool "Marvell CP110 UTMI PHY Driver" + depends on ARCH_MVEBU + depends on OF + help + Enable this to support Marvell USB2.0 PHY driver for Marvell + CP110-based SoCs (A7K and A8K). diff -ruw linux-5.4.60/drivers/phy/marvell/Makefile linux-5.4.60-fbx/drivers/phy/marvell/Makefile --- linux-5.4.60/drivers/phy/marvell/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/phy/marvell/Makefile 2021-03-04 13:20:59.540838967 +0100 @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o obj-$(CONFIG_PHY_PXA_28NM_USB2) += phy-pxa-28nm-usb2.o obj-$(CONFIG_PHY_PXA_USB) += phy-pxa-usb.o +obj-$(CONFIG_PHY_UTMI_CP110) += phy-utmi-cp110.o diff -ruw linux-5.4.60/drivers/pinctrl/bcm/Kconfig linux-5.4.60-fbx/drivers/pinctrl/bcm/Kconfig --- linux-5.4.60/drivers/pinctrl/bcm/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/pinctrl/bcm/Kconfig 2021-03-04 13:20:59.547505634 +0100 @@ -28,6 +28,15 @@ help Say Y here to enable the Broadcom BCM2835 GPIO driver. +config PINCTRL_BCM63138 + bool "Broadcom 63138 pinmux driver" + depends on OF && (ARCH_BCM_63XX || ARCH_BCM63XX || COMPILE_TEST) + default ARCH_BCM_63XX + select PINMUX + select PINCONF + select GENERIC_PINCONF + select GPIOLIB + config PINCTRL_IPROC_GPIO bool "Broadcom iProc GPIO (with PINCONF) driver" depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST) diff -ruw linux-5.4.60/drivers/pinctrl/bcm/Makefile linux-5.4.60-fbx/drivers/pinctrl/bcm/Makefile --- linux-5.4.60/drivers/pinctrl/bcm/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/pinctrl/bcm/Makefile 2021-03-04 13:20:59.547505634 +0100 @@ -3,6 +3,7 @@ obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o +obj-$(CONFIG_PINCTRL_BCM63138) += pinctrl-bcm63138.o obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o diff -ruw linux-5.4.60/drivers/platform/Kconfig linux-5.4.60-fbx/drivers/platform/Kconfig --- linux-5.4.60/drivers/platform/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/platform/Kconfig 2021-03-04 13:20:59.597505636 +0100 @@ -13,3 +13,9 @@ source "drivers/platform/mellanox/Kconfig" source "drivers/platform/olpc/Kconfig" + +if X86_INTEL_CE +source "drivers/platform/intelce/Kconfig" +endif + +source "drivers/platform/fbxgw7r/Kconfig" diff -ruw linux-5.4.60/drivers/platform/Makefile linux-5.4.60-fbx/drivers/platform/Makefile --- linux-5.4.60/drivers/platform/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/platform/Makefile 2021-03-04 13:20:59.597505636 +0100 @@ -9,3 +9,5 @@ obj-$(CONFIG_OLPC_EC) += olpc/ obj-$(CONFIG_GOLDFISH) += goldfish/ obj-$(CONFIG_CHROME_PLATFORMS) += chrome/ +obj-$(CONFIG_X86_INTEL_CE) += intelce/ +obj-$(CONFIG_FBXGW7R_PLATFORM) += fbxgw7r/ diff -ruw linux-5.4.60/drivers/soc/bcm/Kconfig linux-5.4.60-fbx/drivers/soc/bcm/Kconfig --- linux-5.4.60/drivers/soc/bcm/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/soc/bcm/Kconfig 2021-03-04 13:20:59.834172314 +0100 @@ -34,5 +34,6 @@ If unsure, say N. source "drivers/soc/bcm/brcmstb/Kconfig" +source "drivers/soc/bcm/bcm63xx/Kconfig" endmenu diff -ruw linux-5.4.60/drivers/soc/bcm/Makefile linux-5.4.60-fbx/drivers/soc/bcm/Makefile --- linux-5.4.60/drivers/soc/bcm/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/soc/bcm/Makefile 2021-03-04 13:20:59.834172314 +0100 @@ -2,3 +2,4 @@ obj-$(CONFIG_BCM2835_POWER) += bcm2835-power.o obj-$(CONFIG_RASPBERRYPI_POWER) += raspberrypi-power.o obj-$(CONFIG_SOC_BRCMSTB) += brcmstb/ +obj-$(CONFIG_SOC_BCM63XX) += bcm63xx/ diff -ruw linux-5.4.60/drivers/spi/Kconfig linux-5.4.60-fbx/drivers/spi/Kconfig --- linux-5.4.60/drivers/spi/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/spi/Kconfig 2021-03-04 13:20:59.847505647 +0100 @@ -147,7 +147,7 @@ config SPI_BCM63XX_HSSPI tristate "Broadcom BCM63XX HS SPI controller driver" - depends on BCM63XX || ARCH_BCM_63XX || COMPILE_TEST + depends on BCM63XX || ARCH_BCM63XX || ARCH_BCM_63XX || COMPILE_TEST help This enables support for the High Speed SPI controller present on newer Broadcom BCM63XX SoCs. @@ -539,6 +539,12 @@ help This selects a driver for the PPC4xx SPI Controller. +config SPI_TDM_ORION + tristate "Orion TDM SPI master" + depends on PLAT_ORION + help + This enables using the TDM SPI master controller on the Orion chips. + config SPI_PXA2XX tristate "PXA2xx SSP SPI master" depends on (ARCH_PXA || ARCH_MMP || PCI || ACPI) diff -ruw linux-5.4.60/drivers/spi/Makefile linux-5.4.60-fbx/drivers/spi/Makefile --- linux-5.4.60/drivers/spi/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/spi/Makefile 2021-03-04 13:20:59.847505647 +0100 @@ -76,6 +76,7 @@ obj-$(CONFIG_SPI_ORION) += spi-orion.o obj-$(CONFIG_SPI_PIC32) += spi-pic32.o obj-$(CONFIG_SPI_PIC32_SQI) += spi-pic32-sqi.o +obj-$(CONFIG_SPI_TDM_ORION) += orion_tdm_spi.o obj-$(CONFIG_SPI_PL022) += spi-pl022.o obj-$(CONFIG_SPI_PPC4xx) += spi-ppc4xx.o spi-pxa2xx-platform-objs := spi-pxa2xx.o spi-pxa2xx-dma.o diff -ruw linux-5.4.60/drivers/spi/spi-bcm63xx-hsspi.c linux-5.4.60-fbx/drivers/spi/spi-bcm63xx-hsspi.c --- linux-5.4.60/drivers/spi/spi-bcm63xx-hsspi.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/spi/spi-bcm63xx-hsspi.c 2021-03-04 13:20:59.847505647 +0100 @@ -57,7 +57,7 @@ #define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40) #define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20) -#define CLK_CTRL_FREQ_CTRL_MASK 0x0000ffff +#define CLK_CTRL_FREQ_CTRL_MASK 0x000007ff #define CLK_CTRL_SPI_CLK_2X_SEL BIT(14) #define CLK_CTRL_ACCUM_RST_ON_LOOP BIT(15) @@ -107,6 +107,8 @@ u32 speed_hz; u8 cs_polarity; + + int dummy_cs; }; static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, @@ -132,6 +134,8 @@ u32 reg; reg = DIV_ROUND_UP(2048, DIV_ROUND_UP(bs->speed_hz, hz)); + if (reg > CLK_CTRL_FREQ_CTRL_MASK) + reg = CLK_CTRL_FREQ_CTRL_MASK; __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, bs->regs + HSSPI_PROFILE_CLK_CTRL_REG(profile)); @@ -152,6 +156,17 @@ mutex_unlock(&bs->bus_mutex); } +/* + * use the DT-specified dummy chip select or fallback to the previous + * behaviour (dummy_cs = !cs). + */ +static inline int bcm63xx_hsspi_get_dummy_cs(struct bcm63xx_hsspi *bs, int cs) +{ + if (bs->dummy_cs >= 0) + return bs->dummy_cs; + return !cs; +} + static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) { struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master); @@ -161,6 +176,7 @@ int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; + int dummy_cs = bcm63xx_hsspi_get_dummy_cs(bs, chip_select); bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); @@ -192,14 +208,14 @@ tx += curr_step; } - __raw_writew(opcode | curr_step, bs->fifo); + iowrite16be(opcode | curr_step, bs->fifo); /* enable interrupt */ __raw_writel(HSSPI_PINGx_CMD_DONE(0), bs->regs + HSSPI_INT_MASK_REG); /* start the transfer */ - __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | + __raw_writel(dummy_cs << PINGPONG_CMD_SS_SHIFT | chip_select << PINGPONG_CMD_PROFILE_SHIFT | PINGPONG_COMMAND_START_NOW, bs->regs + HSSPI_PINGPONG_COMMAND_REG(0)); @@ -281,7 +297,7 @@ * e. At the end restore the polarities again to their default values. */ - dummy_cs = !spi->chip_select; + dummy_cs = bcm63xx_hsspi_get_dummy_cs(bs, spi->chip_select); bcm63xx_hsspi_set_cs(bs, dummy_cs, true); list_for_each_entry(t, &msg->transfers, transfer_list) { @@ -335,6 +351,7 @@ struct clk *clk, *pll_clk = NULL; int irq, ret; u32 reg, rate, num_cs = HSSPI_SPI_MAX_CS; + u32 dummy_cs; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -387,6 +404,13 @@ bs->speed_hz = rate; bs->fifo = (u8 __iomem *)(bs->regs + HSSPI_FIFO_REG(0)); + if (of_property_read_u32(dev->of_node, "broadcom,dummy-cs", + &dummy_cs) < 0 || dummy_cs >= 8) + bs->dummy_cs = -1; + else + bs->dummy_cs = dummy_cs; + dev_info(&pdev->dev, "using dummy chip select %d\n", bs->dummy_cs); + mutex_init(&bs->bus_mutex); init_completion(&bs->done); diff -ruw linux-5.4.60/drivers/thermal/thermal_core.c linux-5.4.60-fbx/drivers/thermal/thermal_core.c --- linux-5.4.60/drivers/thermal/thermal_core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/thermal/thermal_core.c 2021-03-04 13:21:00.014172322 +0100 @@ -931,6 +931,7 @@ /** * __thermal_cooling_device_register() - register a new thermal cooling device + * @dev: parent device * @np: a pointer to a device tree node. * @type: the thermal cooling device type. * @devdata: device private data. @@ -946,7 +947,7 @@ * ERR_PTR. Caller must check return value with IS_ERR*() helpers. */ static struct thermal_cooling_device * -__thermal_cooling_device_register(struct device_node *np, +__thermal_cooling_device_register(struct device *pdev, struct device_node *np, const char *type, void *devdata, const struct thermal_cooling_device_ops *ops) { @@ -982,6 +983,7 @@ cdev->devdata = devdata; thermal_cooling_device_setup_sysfs(cdev); dev_set_name(&cdev->device, "cooling_device%d", cdev->id); + cdev->device.parent = pdev; result = device_register(&cdev->device); if (result) { ida_simple_remove(&thermal_cdev_ida, cdev->id); @@ -1024,11 +1026,30 @@ thermal_cooling_device_register(const char *type, void *devdata, const struct thermal_cooling_device_ops *ops) { - return __thermal_cooling_device_register(NULL, type, devdata, ops); + return __thermal_cooling_device_register(NULL, NULL, type, devdata, ops); } EXPORT_SYMBOL_GPL(thermal_cooling_device_register); /** + * thermal_cooling_device_register_with_parent() - register a new thermal cooling device + * @pdev: parent device + * @type: the thermal cooling device type. + * @devdata: device private data. + * @ops: standard thermal cooling devices callbacks. + * + * Same as thermal_cooling_device_register but take also the parent device. + * Then, hwpath will include the parent device to uniquely identify this device + */ +struct thermal_cooling_device * +thermal_cooling_device_register_with_parent(struct device *pdev, + const char *type, void *devdata, + const struct thermal_cooling_device_ops *ops) +{ + return __thermal_cooling_device_register(pdev, NULL, type, devdata, ops); +} +EXPORT_SYMBOL_GPL(thermal_cooling_device_register_with_parent); + +/** * thermal_of_cooling_device_register() - register an OF thermal cooling device * @np: a pointer to a device tree node. * @type: the thermal cooling device type. @@ -1048,7 +1069,7 @@ const char *type, void *devdata, const struct thermal_cooling_device_ops *ops) { - return __thermal_cooling_device_register(np, type, devdata, ops); + return __thermal_cooling_device_register(NULL, np, type, devdata, ops); } EXPORT_SYMBOL_GPL(thermal_of_cooling_device_register); @@ -1088,7 +1109,7 @@ if (!ptr) return ERR_PTR(-ENOMEM); - tcd = __thermal_cooling_device_register(np, type, devdata, ops); + tcd = __thermal_cooling_device_register(NULL, np, type, devdata, ops); if (IS_ERR(tcd)) { devres_free(ptr); return tcd; diff -ruw linux-5.4.60/drivers/tty/serial/Kconfig linux-5.4.60-fbx/drivers/tty/serial/Kconfig --- linux-5.4.60/drivers/tty/serial/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/tty/serial/Kconfig 2021-03-04 13:21:00.027505655 +0100 @@ -1134,6 +1134,11 @@ BCM68xx (PON) BCM7xxx (STB) - DOCSIS console +config SERIAL_BCM63XX_HS + tristate "Broadcom BCM63xx HS UART support" + select SERIAL_CORE + depends on ARCH_BCM63XX || COMPILE_TEST + config SERIAL_BCM63XX_CONSOLE bool "Console on BCM63xx serial port" depends on SERIAL_BCM63XX=y diff -ruw linux-5.4.60/drivers/tty/serial/Makefile linux-5.4.60-fbx/drivers/tty/serial/Makefile --- linux-5.4.60/drivers/tty/serial/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/tty/serial/Makefile 2021-03-04 13:21:00.027505655 +0100 @@ -30,6 +30,7 @@ obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o +obj-$(CONFIG_SERIAL_BCM63XX_HS) += bcm63xx-hs-uart.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_MAX310X) += max310x.o diff -ruw linux-5.4.60/drivers/usb/host/Kconfig linux-5.4.60-fbx/drivers/usb/host/Kconfig --- linux-5.4.60/drivers/usb/host/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/usb/host/Kconfig 2021-03-04 13:21:00.080838992 +0100 @@ -70,13 +70,13 @@ If unsure, say N. config USB_XHCI_MVEBU - tristate "xHCI support for Marvell Armada 375/38x/37xx" + tristate "xHCI support for Marvell Armada 375/38x/37xx/70x0/80x0" select USB_XHCI_PLATFORM depends on HAS_IOMEM depends on ARCH_MVEBU || COMPILE_TEST ---help--- Say 'Y' to enable the support for the xHCI host controller - found in Marvell Armada 375/38x/37xx ARM SOCs. + found in Marvell Armada 375/38x/37xx/70x0/80x0 ARM SOCs. config USB_XHCI_RCAR tristate "xHCI support for Renesas R-Car SoCs" @@ -734,6 +734,10 @@ If unsure, say N. +config USB_BCM63158 + tristate "Broadcom BCM63158 SoC USB host driver" + depends on ARCH_BCM63XX || COMPILE_TEST + config USB_HCD_SSB tristate "SSB usb host driver" depends on SSB diff -ruw linux-5.4.60/drivers/usb/host/Makefile linux-5.4.60-fbx/drivers/usb/host/Makefile --- linux-5.4.60/drivers/usb/host/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/usb/host/Makefile 2021-03-04 13:21:00.080838992 +0100 @@ -88,3 +88,4 @@ obj-$(CONFIG_USB_HCD_SSB) += ssb-hcd.o obj-$(CONFIG_USB_FOTG210_HCD) += fotg210-hcd.o obj-$(CONFIG_USB_MAX3421_HCD) += max3421-hcd.o +obj-$(CONFIG_USB_BCM63158) += usb-bcm63158.o diff -ruw linux-5.4.60/drivers/usb/host/xhci-plat.c linux-5.4.60-fbx/drivers/usb/host/xhci-plat.c --- linux-5.4.60/drivers/usb/host/xhci-plat.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/usb/host/xhci-plat.c 2021-03-04 13:21:00.090838992 +0100 @@ -127,6 +127,8 @@ .compatible = "marvell,armada3700-xhci", .data = &xhci_plat_marvell_armada3700, }, { + .compatible = "marvell,armada-8k-xhci", + }, { .compatible = "renesas,xhci-r8a7790", .data = &xhci_plat_renesas_rcar_gen2, }, { diff -ruw linux-5.4.60/drivers/usb/storage/usb.c linux-5.4.60-fbx/drivers/usb/storage/usb.c --- linux-5.4.60/drivers/usb/storage/usb.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/usb/storage/usb.c 2021-03-04 13:21:00.120838993 +0100 @@ -67,7 +67,7 @@ MODULE_DESCRIPTION("USB Mass Storage driver for Linux"); MODULE_LICENSE("GPL"); -static unsigned int delay_use = 1; +static unsigned int delay_use = 5; module_param(delay_use, uint, S_IRUGO | S_IWUSR); MODULE_PARM_DESC(delay_use, "seconds to delay before using a new device"); diff -ruw linux-5.4.60/drivers/video/fbdev/Kconfig linux-5.4.60-fbx/drivers/video/fbdev/Kconfig --- linux-5.4.60/drivers/video/fbdev/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/video/fbdev/Kconfig 2021-03-04 13:21:00.130838993 +0100 @@ -2263,6 +2263,24 @@ called sm712fb. If you want to compile it as a module, say M here and read . +config FB_SSD1320 + tristate "SSD1320 OLED driver" + depends on FB && SPI + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + select FB_BACKLIGHT + +config FB_SSD1327 + tristate "SSD1327 OLED driver" + depends on FB && SPI + select FB_SYS_FILLRECT + select FB_SYS_COPYAREA + select FB_SYS_IMAGEBLIT + select FB_SYS_FOPS + select FB_BACKLIGHT + source "drivers/video/fbdev/omap/Kconfig" source "drivers/video/fbdev/omap2/Kconfig" source "drivers/video/fbdev/mmp/Kconfig" diff -ruw linux-5.4.60/drivers/video/fbdev/Makefile linux-5.4.60-fbx/drivers/video/fbdev/Makefile --- linux-5.4.60/drivers/video/fbdev/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/video/fbdev/Makefile 2021-03-04 13:21:00.130838993 +0100 @@ -131,6 +131,8 @@ obj-$(CONFIG_FB_DA8XX) += da8xx-fb.o obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o obj-$(CONFIG_FB_SIMPLE) += simplefb.o +obj-$(CONFIG_FB_SSD1327) += ssd1327.o +obj-$(CONFIG_FB_SSD1320) += ssd1320.o # the test framebuffer is last obj-$(CONFIG_FB_VIRTUAL) += vfb.o diff -ruw linux-5.4.60/drivers/video/Kconfig linux-5.4.60-fbx/drivers/video/Kconfig --- linux-5.4.60/drivers/video/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/drivers/video/Kconfig 2021-03-04 13:21:00.127505660 +0100 @@ -46,5 +46,4 @@ endif - endmenu diff -ruw linux-5.4.60/fs/exec.c linux-5.4.60-fbx/fs/exec.c --- linux-5.4.60/fs/exec.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/fs/exec.c 2021-03-04 13:21:00.760839022 +0100 @@ -1729,6 +1729,23 @@ return PTR_ERR(filename); /* + * handle current->exec_mode: + * - if unlimited, then nothing to do. + * - if once, then set it to denied and continue (next execve + * after this one will fail). + * - if denied, then effectively fail the execve call with EPERM. + */ + switch (current->exec_mode) { + case EXEC_MODE_UNLIMITED: + break; + case EXEC_MODE_ONCE: + current->exec_mode = EXEC_MODE_DENIED; + break; + case EXEC_MODE_DENIED: + return -EPERM; + } + + /* * We move the actual failure in case of RLIMIT_NPROC excess from * set*uid() to execve() because too many poorly written programs * don't check setuid() return code. Here we additionally recheck diff -ruw linux-5.4.60/fs/Kconfig linux-5.4.60-fbx/fs/Kconfig --- linux-5.4.60/fs/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/fs/Kconfig 2021-03-30 15:48:29.595052528 +0200 @@ -143,6 +143,7 @@ source "fs/fat/Kconfig" source "fs/ntfs/Kconfig" +source "fs/exfat/Kconfig" endmenu endif # BLOCK @@ -286,6 +287,8 @@ source "fs/nfs/Kconfig" source "fs/nfsd/Kconfig" +source "fs/cifsd/Kconfig" + config GRACE_PERIOD tristate diff -ruw linux-5.4.60/fs/Makefile linux-5.4.60-fbx/fs/Makefile --- linux-5.4.60/fs/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/fs/Makefile 2021-03-30 15:48:29.595052528 +0200 @@ -91,6 +91,7 @@ obj-$(CONFIG_NFS_FS) += nfs/ obj-$(CONFIG_EXPORTFS) += exportfs/ obj-$(CONFIG_NFSD) += nfsd/ +obj-$(CONFIG_SMB_SERVER) += cifsd/ obj-$(CONFIG_LOCKD) += lockd/ obj-$(CONFIG_NLS) += nls/ obj-$(CONFIG_UNICODE) += unicode/ @@ -132,3 +133,4 @@ obj-$(CONFIG_PSTORE) += pstore/ obj-$(CONFIG_EFIVAR_FS) += efivarfs/ obj-$(CONFIG_EROFS_FS) += erofs/ +obj-$(CONFIG_EXFAT_FS_FBX) += exfat/ diff -ruw linux-5.4.60/fs/proc/array.c linux-5.4.60-fbx/fs/proc/array.c --- linux-5.4.60/fs/proc/array.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/fs/proc/array.c 2021-03-04 13:21:00.864172360 +0100 @@ -149,6 +149,21 @@ return task_state_array[task_state_index(tsk)]; } +static const char *const task_exec_mode_array[] = { + "0 (Denied)", + "1 (Once)", + "2 (Unlimited)", +}; + +static inline const char *get_task_exec_mode(struct task_struct *tsk) +{ + unsigned int exec_mode = tsk->exec_mode; + + if (exec_mode > EXEC_MODE_UNLIMITED) + return "? (Invalid)"; + return task_exec_mode_array[exec_mode]; +} + static inline void task_state(struct seq_file *m, struct pid_namespace *ns, struct pid *pid, struct task_struct *p) { @@ -378,6 +393,12 @@ seq_putc(m, '\n'); } +static inline void task_exec_mode(struct seq_file *m, + struct task_struct *p) +{ + seq_printf(m, "Exec mode: %s\n", get_task_exec_mode(p)); +} + static void task_cpus_allowed(struct seq_file *m, struct task_struct *task) { seq_printf(m, "Cpus_allowed:\t%*pb\n", @@ -424,6 +445,7 @@ task_cpus_allowed(m, task); cpuset_task_status_allowed(m, task); task_context_switch_counts(m, task); + task_exec_mode(m, task); return 0; } diff -ruw linux-5.4.60/fs/pstore/inode.c linux-5.4.60-fbx/fs/pstore/inode.c --- linux-5.4.60/fs/pstore/inode.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/fs/pstore/inode.c 2021-03-30 15:48:29.605052529 +0200 @@ -321,9 +321,10 @@ goto fail; inode->i_mode = S_IFREG | 0444; inode->i_fop = &pstore_file_operations; - scnprintf(name, sizeof(name), "%s-%s-%llu%s", + scnprintf(name, sizeof(name), "%s-%s-%s%llu%s", pstore_type_to_name(record->type), - record->psi->name, record->id, + record->psi->name, record->old ? "old-" : "", + record->id, record->compressed ? ".enc.z" : ""); private = kzalloc(sizeof(*private), GFP_KERNEL); diff -ruw linux-5.4.60/fs/pstore/ram.c linux-5.4.60-fbx/fs/pstore/ram.c --- linux-5.4.60/fs/pstore/ram.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/fs/pstore/ram.c 2021-03-30 15:48:29.605052529 +0200 @@ -131,6 +131,7 @@ record->type = prz->type; record->id = id; + record->old = prz->old_zone; return prz; } @@ -516,7 +517,7 @@ static int ramoops_init_przs(const char *name, struct device *dev, struct ramoops_context *cxt, struct persistent_ram_zone ***przs, - phys_addr_t *paddr, size_t mem_sz, + phys_addr_t *paddr, void *vaddr, size_t mem_sz, ssize_t record_size, unsigned int *cnt, u32 sig, u32 flags) { @@ -580,7 +581,7 @@ else label = kasprintf(GFP_KERNEL, "ramoops:%s(%d/%d)", name, i, *cnt - 1); - prz_ar[i] = persistent_ram_new(*paddr, zone_sz, sig, + prz_ar[i] = persistent_ram_new(*paddr, vaddr, zone_sz, sig, &cxt->ecc_info, cxt->memtype, flags, label); kfree(label); @@ -612,7 +613,7 @@ static int ramoops_init_prz(const char *name, struct device *dev, struct ramoops_context *cxt, struct persistent_ram_zone **prz, - phys_addr_t *paddr, size_t sz, u32 sig) + phys_addr_t *paddr, void *vaddr, size_t sz, u32 sig) { char *label; @@ -627,7 +628,7 @@ } label = kasprintf(GFP_KERNEL, "ramoops:%s", name); - *prz = persistent_ram_new(*paddr, sz, sig, &cxt->ecc_info, + *prz = persistent_ram_new(*paddr, vaddr, sz, sig, &cxt->ecc_info, cxt->memtype, PRZ_FLAG_ZAP_OLD, label); kfree(label); if (IS_ERR(*prz)) { @@ -794,12 +795,14 @@ dump_mem_sz = cxt->size - cxt->console_size - cxt->ftrace_size - cxt->pmsg_size; err = ramoops_init_przs("dmesg", dev, cxt, &cxt->dprzs, &paddr, + pdata->mem_ptr, dump_mem_sz, cxt->record_size, &cxt->max_dump_cnt, 0, 0); if (err) goto fail_out; err = ramoops_init_prz("console", dev, cxt, &cxt->cprz, &paddr, + pdata->mem_ptr, cxt->console_size, 0); if (err) goto fail_init_cprz; @@ -808,6 +811,7 @@ ? nr_cpu_ids : 1; err = ramoops_init_przs("ftrace", dev, cxt, &cxt->fprzs, &paddr, + pdata->mem_ptr, cxt->ftrace_size, -1, &cxt->max_ftrace_cnt, LINUX_VERSION_CODE, (cxt->flags & RAMOOPS_FLAG_FTRACE_PER_CPU) @@ -816,6 +820,7 @@ goto fail_init_fprz; err = ramoops_init_prz("pmsg", dev, cxt, &cxt->mprz, &paddr, + pdata->mem_ptr, cxt->pmsg_size, 0); if (err) goto fail_init_mprz; diff -ruw linux-5.4.60/fs/pstore/ram_core.c linux-5.4.60-fbx/fs/pstore/ram_core.c --- linux-5.4.60/fs/pstore/ram_core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/fs/pstore/ram_core.c 2021-03-30 15:48:29.605052529 +0200 @@ -34,6 +34,7 @@ uint32_t sig; atomic_t start; atomic_t size; + atomic_t flags; uint8_t data[0]; }; @@ -395,6 +396,7 @@ { atomic_set(&prz->buffer->start, 0); atomic_set(&prz->buffer->size, 0); + atomic_set(&prz->buffer->flags, 0); persistent_ram_update_header_ecc(prz); } @@ -463,13 +465,16 @@ return va; } -static int persistent_ram_buffer_map(phys_addr_t start, phys_addr_t size, +static int persistent_ram_buffer_map(phys_addr_t start, void *vaddr, + phys_addr_t size, struct persistent_ram_zone *prz, int memtype) { prz->paddr = start; prz->size = size; - if (pfn_valid(start >> PAGE_SHIFT)) + if (vaddr) + prz->vaddr = vaddr; + else if (pfn_valid(start >> PAGE_SHIFT)) prz->vaddr = persistent_ram_vmap(start, size, memtype); else prz->vaddr = persistent_ram_iomap(start, size, memtype, @@ -516,6 +521,15 @@ pr_debug("found existing buffer, size %zu, start %zu\n", buffer_size(prz), buffer_start(prz)); persistent_ram_save_old(prz); + + if (atomic_read(&prz->buffer->flags) > 0) { + pr_info("old ramoops!\n"); + prz->old_zone = true; + } else { + pr_info("fresh ramoops!\n"); + atomic_set(&prz->buffer->flags, 1); + } + persistent_ram_update_header_ecc(prz); } } else { pr_debug("no valid data in buffer (sig = 0x%08x)\n", @@ -558,7 +572,8 @@ kfree(prz); } -struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, size_t size, +struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, + void *vaddr, size_t size, u32 sig, struct persistent_ram_ecc_info *ecc_info, unsigned int memtype, u32 flags, char *label) { @@ -576,7 +591,7 @@ prz->flags = flags; prz->label = kstrdup(label, GFP_KERNEL); - ret = persistent_ram_buffer_map(start, size, prz, memtype); + ret = persistent_ram_buffer_map(start, vaddr, size, prz, memtype); if (ret) goto err; diff -ruw linux-5.4.60/include/asm-generic/vmlinux.lds.h linux-5.4.60-fbx/include/asm-generic/vmlinux.lds.h --- linux-5.4.60/include/asm-generic/vmlinux.lds.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/asm-generic/vmlinux.lds.h 2021-03-04 13:21:00.920839029 +0100 @@ -264,7 +264,7 @@ #define KERNEL_DTB() \ STRUCT_ALIGN(); \ __dtb_start = .; \ - KEEP(*(.dtb.init.rodata)) \ + KEEP(*(.dtb.rodata)) \ __dtb_end = .; /* @@ -354,6 +354,7 @@ . = ALIGN((align)); \ .rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \ __start_rodata = .; \ + KERNEL_DTB() \ *(.rodata) *(.rodata.*) \ RO_AFTER_INIT_DATA /* Read only after init */ \ . = ALIGN(8); \ @@ -644,7 +645,6 @@ TIMER_OF_TABLES() \ CPU_METHOD_OF_TABLES() \ CPUIDLE_METHOD_OF_TABLES() \ - KERNEL_DTB() \ IRQCHIP_OF_MATCH_TABLE() \ ACPI_PROBE_TABLE(irqchip) \ ACPI_PROBE_TABLE(timer) \ diff -ruw linux-5.4.60/include/linux/brcmphy.h linux-5.4.60-fbx/include/linux/brcmphy.h --- linux-5.4.60/include/linux/brcmphy.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/brcmphy.h 2021-03-04 13:21:00.954172363 +0100 @@ -27,6 +27,9 @@ #define PHY_ID_BCM57780 0x03625d90 #define PHY_ID_BCM89610 0x03625cd0 +#define PHY_ID_BCM63138 0x600d85c0 +#define PHY_ID_BCM63138S 0x0143bff0 + #define PHY_ID_BCM7250 0xae025280 #define PHY_ID_BCM7255 0xae025120 #define PHY_ID_BCM7260 0xae025190 @@ -48,6 +51,8 @@ #define PHY_ID_BCM_CYGNUS 0xae025200 #define PHY_ID_BCM_OMEGA 0xae025100 +#define PHY_ID_BCM63158 0xae0251c1 + #define PHY_BCM_OUI_MASK 0xfffffc00 #define PHY_BCM_OUI_1 0x00206000 #define PHY_BCM_OUI_2 0x0143bc00 diff -ruw linux-5.4.60/include/linux/ethtool.h linux-5.4.60-fbx/include/linux/ethtool.h --- linux-5.4.60/include/linux/ethtool.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/ethtool.h 2021-03-04 13:21:00.967505698 +0100 @@ -404,6 +404,14 @@ struct ethtool_fecparam *); void (*get_ethtool_phy_stats)(struct net_device *, struct ethtool_stats *, u64 *); + int (*get_epon_param)(struct net_device *, + struct ethtool_epon_param *); + int (*set_epon_param)(struct net_device *, + const struct ethtool_epon_param *); + int (*set_shaper_param)(struct net_device *, + const struct ethtool_shaper_params *); + int (*get_shaper_param)(struct net_device *, + struct ethtool_shaper_params *); }; struct ethtool_rx_flow_rule { diff -ruw linux-5.4.60/include/linux/genhd.h linux-5.4.60-fbx/include/linux/genhd.h --- linux-5.4.60/include/linux/genhd.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/genhd.h 2021-03-04 13:21:00.970839031 +0100 @@ -91,6 +91,7 @@ unsigned long io_ticks; unsigned long time_in_queue; local_t in_flight[2]; + unsigned long io_errors[2]; }; #define PARTITION_META_INFO_VOLNAMELTH 64 @@ -614,6 +615,7 @@ #define ADDPART_FLAG_NONE 0 #define ADDPART_FLAG_RAID 1 #define ADDPART_FLAG_WHOLEDISK 2 +#define ADDPART_FLAG_RO 4 extern int blk_alloc_devt(struct hd_struct *part, dev_t *devt); extern void blk_free_devt(dev_t devt); diff -ruw linux-5.4.60/include/linux/if_vlan.h linux-5.4.60-fbx/include/linux/if_vlan.h --- linux-5.4.60/include/linux/if_vlan.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/if_vlan.h 2021-03-04 13:21:00.977505698 +0100 @@ -12,6 +12,7 @@ #include #include #include +#include #define VLAN_HLEN 4 /* The additional bytes required by VLAN * (in addition to the Ethernet header) @@ -134,6 +135,7 @@ int (*action)(struct net_device *dev, int vid, void *arg), void *arg); extern struct net_device *vlan_dev_real_dev(const struct net_device *dev); +extern struct net_device *vlan_dev_upper_dev(const struct net_device *dev); extern u16 vlan_dev_vlan_id(const struct net_device *dev); extern __be16 vlan_dev_vlan_proto(const struct net_device *dev); @@ -200,7 +202,7 @@ mp = vlan_dev_priv(dev)->egress_priority_map[(skprio & 0xF)]; while (mp) { - if (mp->priority == skprio) { + if (mp->priority == (skprio & TC_H_MIN_MASK)) { return mp->vlan_qos; /* This should already be shifted * to mask correctly with the * VLAN's TCI */ @@ -242,6 +244,12 @@ { BUG(); return NULL; +} + +static inline struct net_device *vlan_dev_upper_dev(const struct net_device *dev) +{ + BUG(); + return NULL; } static inline u16 vlan_dev_vlan_id(const struct net_device *dev) diff -ruw linux-5.4.60/include/linux/in.h linux-5.4.60-fbx/include/linux/in.h --- linux-5.4.60/include/linux/in.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/in.h 2021-03-04 13:21:00.980839031 +0100 @@ -30,6 +30,9 @@ return 0; case IPPROTO_AH: /* SPI */ return 4; + case IPPROTO_IPV6: + /* third byte of ipv6 destination address */ + return 36; default: return -EINVAL; } diff -ruw linux-5.4.60/include/linux/miscdevice.h linux-5.4.60-fbx/include/linux/miscdevice.h --- linux-5.4.60/include/linux/miscdevice.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/miscdevice.h 2021-03-04 13:21:01.004172366 +0100 @@ -21,6 +21,7 @@ #define APOLLO_MOUSE_MINOR 7 /* unused */ #define PC110PAD_MINOR 9 /* unused */ /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */ +#define TALDEV_MINOR 74 /* Marvell TAL device */ #define WATCHDOG_MINOR 130 /* Watchdog timer */ #define TEMP_MINOR 131 /* Temperature Sensor */ #define APM_MINOR_DEV 134 diff -ruw linux-5.4.60/include/linux/mtd/mtd.h linux-5.4.60-fbx/include/linux/mtd/mtd.h --- linux-5.4.60/include/linux/mtd/mtd.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/mtd/mtd.h 2021-03-04 13:21:01.010839033 +0100 @@ -247,6 +247,12 @@ */ unsigned int bitflip_threshold; + /* NAND related attributes */ + const char *nand_type; + const char *nand_manufacturer; + const char *onfi_model; + uint8_t onfi_ecc_bits; + /* Kernel-only stuff starts here. */ const char *name; int index; diff -ruw linux-5.4.60/include/linux/mtd/spi-nor.h linux-5.4.60-fbx/include/linux/mtd/spi-nor.h --- linux-5.4.60/include/linux/mtd/spi-nor.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/mtd/spi-nor.h 2021-03-04 13:21:01.010839033 +0100 @@ -56,9 +56,11 @@ #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */ #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */ #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */ +#define SPINOR_OP_EWRSR 0x50 /* SST: Enable write to status reg */ #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */ #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */ #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */ +#define SPINOR_OP_RDID_ALT 0x90 /* Read ID (alt) */ #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */ #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */ #define SPINOR_OP_RDCR 0x35 /* Read configuration register */ @@ -598,6 +600,8 @@ ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len, const u_char *write_buf); int (*erase)(struct spi_nor *nor, loff_t offs); + int (*read_alt_id)(struct spi_nor *nor, u8 cmd, u8 *val, int len); + int (*read_atmel_id)(struct spi_nor *nor, u8 cmd, u8 *val, int len); int (*clear_sr_bp)(struct spi_nor *nor); struct spi_nor_flash_parameter params; diff -ruw linux-5.4.60/include/linux/netdevice.h linux-5.4.60-fbx/include/linux/netdevice.h --- linux-5.4.60/include/linux/netdevice.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/netdevice.h 2021-03-04 13:21:01.014172366 +0100 @@ -65,6 +65,20 @@ struct bpf_prog; struct xdp_buff; +#ifdef CONFIG_NETRXTHREAD + +#define RXTHREAD_MAX_PKTS 512 +struct krxd { + struct sk_buff_head pkt_queue; + unsigned int stats_pkts; + unsigned int stats_dropped; + wait_queue_head_t wq; + struct task_struct *task; +}; + +extern struct krxd gkrxd[CONFIG_NETRXTHREAD_RX_QUEUE]; +#endif + void netdev_set_default_ethtool_ops(struct net_device *dev, const struct ethtool_ops *ops); @@ -1522,6 +1536,8 @@ IFF_FAILOVER_SLAVE = 1<<28, IFF_L3MDEV_RX_HANDLER = 1<<29, IFF_LIVE_RENAME_OK = 1<<30, + IFF_FBXBRIDGE = 1ULL<<31, + IFF_FBXBRIDGE_PORT = 1ULL<<32, }; #define IFF_802_1Q_VLAN IFF_802_1Q_VLAN @@ -1554,6 +1570,8 @@ #define IFF_FAILOVER_SLAVE IFF_FAILOVER_SLAVE #define IFF_L3MDEV_RX_HANDLER IFF_L3MDEV_RX_HANDLER #define IFF_LIVE_RENAME_OK IFF_LIVE_RENAME_OK +#define IFF_FBXBRIDGE IFF_FBXBRIDGE +#define IFF_FBXBRIDGE_PORT IFF_FBXBRIDGE_PORT /** * struct net_device - The DEVICE structure. @@ -1858,7 +1876,7 @@ const struct header_ops *header_ops; unsigned int flags; - unsigned int priv_flags; + u64 priv_flags; unsigned short gflags; unsigned short padded; @@ -4616,6 +4634,16 @@ return dev->priv_flags & IFF_BRIDGE_PORT; } +static inline bool netif_is_fbxbridge_master(const struct net_device *dev) +{ + return dev->priv_flags & IFF_FBXBRIDGE; +} + +static inline bool netif_is_fbxbridge_port(const struct net_device *dev) +{ + return dev->priv_flags & IFF_FBXBRIDGE_PORT; +} + static inline bool netif_is_ovs_master(const struct net_device *dev) { return dev->priv_flags & IFF_OPENVSWITCH; diff -ruw linux-5.4.60/include/linux/netfilter/nf_conntrack_ftp.h linux-5.4.60-fbx/include/linux/netfilter/nf_conntrack_ftp.h --- linux-5.4.60/include/linux/netfilter/nf_conntrack_ftp.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/netfilter/nf_conntrack_ftp.h 2021-03-04 13:21:01.014172366 +0100 @@ -22,6 +22,11 @@ u_int16_t seq_aft_nl_num[IP_CT_DIR_MAX]; /* pickup sequence tracking, useful for conntrackd */ u_int16_t flags[IP_CT_DIR_MAX]; +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + unsigned int is_fbxbridge; + unsigned long fbxbridge_remote; + unsigned long fbxbridge_wan; +#endif }; /* For NAT to hook in when we find a packet which describes what other diff -ruw linux-5.4.60/include/linux/netfilter/nf_conntrack_sip.h linux-5.4.60-fbx/include/linux/netfilter/nf_conntrack_sip.h --- linux-5.4.60/include/linux/netfilter/nf_conntrack_sip.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/netfilter/nf_conntrack_sip.h 2021-03-04 13:21:01.014172366 +0100 @@ -5,6 +5,7 @@ #include #include #include +#include #define SIP_PORT 5060 #define SIP_TIMEOUT 3600 @@ -30,6 +31,10 @@ enum sip_expectation_classes class; }; +struct nf_ct_sip_expect { + u8 cid_hash[SHA256_DIGEST_SIZE]; +}; + #define SDP_MEDIA_TYPE(__name, __class) \ { \ .name = (__name), \ diff -ruw linux-5.4.60/include/linux/netfilter/nf_conntrack_tcp.h linux-5.4.60-fbx/include/linux/netfilter/nf_conntrack_tcp.h --- linux-5.4.60/include/linux/netfilter/nf_conntrack_tcp.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/netfilter/nf_conntrack_tcp.h 2021-03-04 13:21:01.014172366 +0100 @@ -28,6 +28,7 @@ /* For SYN packets while we may be out-of-sync */ u_int8_t last_wscale; /* Last window scaling factor seen */ u_int8_t last_flags; /* Last flags set */ + u_int32_t no_window_track; }; #endif /* _NF_CONNTRACK_TCP_H */ diff -ruw linux-5.4.60/include/linux/of_fdt.h linux-5.4.60-fbx/include/linux/of_fdt.h --- linux-5.4.60/include/linux/of_fdt.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/of_fdt.h 2021-03-04 13:21:01.017505700 +0100 @@ -89,6 +89,7 @@ extern void unflatten_and_copy_device_tree(void); extern void early_init_devtree(void *); extern void early_get_first_memblock_info(void *, phys_addr_t *); +const void *of_fdt_find_compatible_dtb(const char *name); #else /* CONFIG_OF_EARLY_FLATTREE */ static inline int early_init_dt_scan_chosen_stdout(void) { return -ENODEV; } static inline void early_init_fdt_scan_reserved_mem(void) {} diff -ruw linux-5.4.60/include/linux/pci_ids.h linux-5.4.60-fbx/include/linux/pci_ids.h --- linux-5.4.60/include/linux/pci_ids.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/pci_ids.h 2021-03-04 13:21:01.020839033 +0100 @@ -1838,6 +1838,7 @@ #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 +#define PCI_DEVICE_ID_PI7C9X20303SL 0xa303 #define PCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 #define PCI_SUBDEVICE_ID_CHASE_PCIFAST4 0x0031 diff -ruw linux-5.4.60/include/linux/phy.h linux-5.4.60-fbx/include/linux/phy.h --- linux-5.4.60/include/linux/phy.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/phy.h 2021-03-04 13:21:01.020839033 +0100 @@ -102,6 +102,14 @@ /* 10GBASE-KR, XFI, SFI - single lane 10G Serdes */ PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_USXGMII, + + PHY_INTERFACE_MODE_1000BASEPX_D, + PHY_INTERFACE_MODE_1000BASEPX_U, + PHY_INTERFACE_MODE_10000BASEPR_D, + PHY_INTERFACE_MODE_10000BASEPR_U, + PHY_INTERFACE_MODE_10000_1000_BASEPRX_D, + PHY_INTERFACE_MODE_10000_1000_BASEPRX_U, + PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -179,6 +187,18 @@ return "10gbase-kr"; case PHY_INTERFACE_MODE_USXGMII: return "usxgmii"; + case PHY_INTERFACE_MODE_1000BASEPX_D: + return "1000base-px-d"; + case PHY_INTERFACE_MODE_1000BASEPX_U: + return "1000base-px-u"; + case PHY_INTERFACE_MODE_10000BASEPR_D: + return "10000base-pr-d"; + case PHY_INTERFACE_MODE_10000BASEPR_U: + return "10000base-pr-u"; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_D: + return "10000_1000base-prx-d"; + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + return "10000_1000base-prx-u"; default: return "unknown"; } diff -ruw linux-5.4.60/include/linux/phylink.h linux-5.4.60-fbx/include/linux/phylink.h --- linux-5.4.60/include/linux/phylink.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/phylink.h 2021-03-04 13:21:01.020839033 +0100 @@ -279,4 +279,7 @@ void phylink_set_port_modes(unsigned long *bits); void phylink_helper_basex_speed(struct phylink_link_state *state); +int phylink_set_interface_mode(struct phylink *pl, int mode); +void phylink_revalidate(struct phylink *pl); + #endif diff -ruw linux-5.4.60/include/linux/ppp_channel.h linux-5.4.60-fbx/include/linux/ppp_channel.h --- linux-5.4.60/include/linux/ppp_channel.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/ppp_channel.h 2021-03-04 13:21:01.030839034 +0100 @@ -45,6 +45,9 @@ /* Called by the channel when it can send some more data. */ extern void ppp_output_wakeup(struct ppp_channel *); +/* Called by the channel when it want to prevent further transmit on it */ +extern void ppp_output_stop(struct ppp_channel *); + /* Called by the channel to process a received PPP packet. The packet should have just the 2-byte PPP protocol header. */ extern void ppp_input(struct ppp_channel *, struct sk_buff *); diff -ruw linux-5.4.60/include/linux/pstore.h linux-5.4.60-fbx/include/linux/pstore.h --- linux-5.4.60/include/linux/pstore.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/pstore.h 2021-03-30 15:48:29.605052529 +0200 @@ -64,6 +64,7 @@ * @reason: kdump reason for notification * @part: position in a multipart record * @compressed: whether the buffer is compressed + * @old: reflects underlying prz old_zone. * */ struct pstore_record { @@ -79,6 +80,7 @@ enum kmsg_dump_reason reason; unsigned int part; bool compressed; + bool old; }; /** diff -ruw linux-5.4.60/include/linux/pstore_ram.h linux-5.4.60-fbx/include/linux/pstore_ram.h --- linux-5.4.60/include/linux/pstore_ram.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/pstore_ram.h 2021-03-30 15:48:29.605052529 +0200 @@ -75,6 +75,10 @@ * @old_log_size: * bytes contained in @old_log * + * @old_zone: + * tells whether the zone has just been freshly created, and has + * been read for the first time, this boot, or if it is old, and + * has been created many boots ago. */ struct persistent_ram_zone { phys_addr_t paddr; @@ -97,9 +101,12 @@ char *old_log; size_t old_log_size; + + bool old_zone; }; -struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, size_t size, +struct persistent_ram_zone *persistent_ram_new(phys_addr_t start, + void *addr, size_t size, u32 sig, struct persistent_ram_ecc_info *ecc_info, unsigned int memtype, u32 flags, char *label); void persistent_ram_free(struct persistent_ram_zone *prz); @@ -128,6 +135,7 @@ struct ramoops_platform_data { unsigned long mem_size; phys_addr_t mem_address; + void *mem_ptr; unsigned int mem_type; unsigned long record_size; unsigned long console_size; diff -ruw linux-5.4.60/include/linux/regmap.h linux-5.4.60-fbx/include/linux/regmap.h --- linux-5.4.60/include/linux/regmap.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/regmap.h 2021-03-04 13:21:01.037505700 +0100 @@ -1278,6 +1278,7 @@ int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq); struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data); +void __iomem *regmap_get_mmio_base_address(struct regmap *map); #else /* diff -ruw linux-5.4.60/include/linux/sched.h linux-5.4.60-fbx/include/linux/sched.h --- linux-5.4.60/include/linux/sched.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/sched.h 2021-03-04 13:21:01.040839034 +0100 @@ -621,6 +621,12 @@ struct wake_q_node *next; }; +enum task_exec_mode { + EXEC_MODE_DENIED, + EXEC_MODE_ONCE, + EXEC_MODE_UNLIMITED, +}; + struct task_struct { #ifdef CONFIG_THREAD_INFO_IN_TASK /* @@ -643,6 +649,7 @@ /* Per task flags (PF_*), defined further below: */ unsigned int flags; unsigned int ptrace; + enum task_exec_mode exec_mode; #ifdef CONFIG_SMP struct llist_node wake_entry; diff -ruw linux-5.4.60/include/linux/sfp.h linux-5.4.60-fbx/include/linux/sfp.h --- linux-5.4.60/include/linux/sfp.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/sfp.h 2021-03-04 13:21:01.044172368 +0100 @@ -506,6 +506,7 @@ int sfp_get_module_info(struct sfp_bus *bus, struct ethtool_modinfo *modinfo); int sfp_get_module_eeprom(struct sfp_bus *bus, struct ethtool_eeprom *ee, u8 *data); +int sfp_get_sfp_state(struct sfp_bus *bus, struct ethtool_sfp_state *st); void sfp_upstream_start(struct sfp_bus *bus); void sfp_upstream_stop(struct sfp_bus *bus); struct sfp_bus *sfp_register_upstream(struct fwnode_handle *fwnode, @@ -544,6 +545,12 @@ { return -EOPNOTSUPP; } + +static inline int sfp_get_sfp_state(struct sfp_bus *the_bus, + struct ethtool_sfp_state *st) +{ + return -EOPNOTSUPP; +} static inline void sfp_upstream_start(struct sfp_bus *bus) { diff -ruw linux-5.4.60/include/linux/skbuff.h linux-5.4.60-fbx/include/linux/skbuff.h --- linux-5.4.60/include/linux/skbuff.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/skbuff.h 2021-03-04 13:21:01.047505701 +0100 @@ -604,6 +604,13 @@ typedef unsigned char *sk_buff_data_t; #endif +enum { + FFN_STATE_INIT = 0, + FFN_STATE_FORWARDABLE, + FFN_STATE_FAST_FORWARDED, + FFN_STATE_INCOMPATIBLE, +}; + /** * struct sk_buff - socket buffer * @next: Next buffer in list @@ -730,11 +737,20 @@ #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) unsigned long _nfct; #endif + +#if defined(CONFIG_IP_FFN) || defined(CONFIG_IPV6_FFN) + int ffn_state; + int ffn_orig_tos; +#endif unsigned int len, data_len; __u16 mac_len, hdr_len; +#ifdef CONFIG_NETRXTHREAD + int rxthread_prio; +#endif + /* Following fields are _not_ copied in __copy_skb_header() * Note that queue_mapping is here mostly to fill a hole. */ @@ -2632,6 +2648,10 @@ * get_rps_cpus() for example only access one 64 bytes aligned block : * NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8) */ +#ifdef CONFIG_NETSKBPAD +#define NET_SKB_PAD CONFIG_NETSKBPAD +#endif + #ifndef NET_SKB_PAD #define NET_SKB_PAD max(32, L1_CACHE_BYTES) #endif diff -ruw linux-5.4.60/include/linux/tcp.h linux-5.4.60-fbx/include/linux/tcp.h --- linux-5.4.60/include/linux/tcp.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/tcp.h 2021-03-04 13:21:01.054172368 +0100 @@ -225,7 +225,8 @@ fastopen_connect:1, /* FASTOPEN_CONNECT sockopt */ fastopen_no_cookie:1, /* Allow send/recv SYN+data without a cookie */ is_sack_reneg:1, /* in recovery from loss with SACK reneg? */ - unused:2; + linear_rto : 1, + unused:1; u8 nonagle : 4,/* Disable Nagle algorithm? */ thin_lto : 1,/* Use linear timeouts for thin streams */ recvmsg_inq : 1,/* Indicate # of bytes in queue upon recvmsg */ diff -ruw linux-5.4.60/include/linux/thermal.h linux-5.4.60-fbx/include/linux/thermal.h --- linux-5.4.60/include/linux/thermal.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/linux/thermal.h 2021-03-04 13:21:01.054172368 +0100 @@ -444,6 +444,9 @@ struct thermal_cooling_device *thermal_cooling_device_register(const char *, void *, const struct thermal_cooling_device_ops *); +struct thermal_cooling_device *thermal_cooling_device_register_with_parent( + struct device *pdev, const char *, void *, + const struct thermal_cooling_device_ops *); struct thermal_cooling_device * thermal_of_cooling_device_register(struct device_node *np, const char *, void *, const struct thermal_cooling_device_ops *); diff -ruw linux-5.4.60/include/media/dvb-usb-ids.h linux-5.4.60-fbx/include/media/dvb-usb-ids.h --- linux-5.4.60/include/media/dvb-usb-ids.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/media/dvb-usb-ids.h 2021-03-04 13:21:01.067505702 +0100 @@ -117,6 +117,7 @@ #define USB_PID_DELOCK_USB2_DVBT 0xb803 #define USB_PID_DIBCOM_HOOK_DEFAULT 0x0064 #define USB_PID_DIBCOM_HOOK_DEFAULT_REENUM 0x0065 +#define USB_PID_DIBCOM_HOOK_DEFAULT_STK7770P 0x0066 #define USB_PID_DIBCOM_MOD3000_COLD 0x0bb8 #define USB_PID_DIBCOM_MOD3000_WARM 0x0bb9 #define USB_PID_DIBCOM_MOD3001_COLD 0x0bc6 diff -ruw linux-5.4.60/include/net/bluetooth/hci.h linux-5.4.60-fbx/include/net/bluetooth/hci.h --- linux-5.4.60/include/net/bluetooth/hci.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/bluetooth/hci.h 2021-03-04 13:21:01.074172369 +0100 @@ -204,6 +204,13 @@ * */ HCI_QUIRK_NON_PERSISTENT_SETUP, + + /* When this quirk is set, max_page for local extended features + * is set to 1, even if controller reports higher number. Some + * controllers (e.g. RTL8723CS) report more pages, but they + * don't actually support features declared there. + */ + HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, }; /* HCI device flags */ diff -ruw linux-5.4.60/include/net/cfg80211.h linux-5.4.60-fbx/include/net/cfg80211.h --- linux-5.4.60/include/net/cfg80211.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/cfg80211.h 2021-03-04 13:21:01.077505702 +0100 @@ -117,6 +117,7 @@ (IEEE80211_CHAN_NO_HT40PLUS | IEEE80211_CHAN_NO_HT40MINUS) #define IEEE80211_DFS_MIN_CAC_TIME_MS 60000 +#define IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS 600000 #define IEEE80211_DFS_MIN_NOP_TIME_MS (30 * 60 * 1000) /** @@ -1823,6 +1824,17 @@ }; /** + * struct mesh_setup - 802.11s mesh setup configuration + * @ie: vendor information elements + * @ie_len: length of vendor information elements + * These parameters are updated peroidically after mesh creation. + */ +struct mesh_vendor_ie { + const u8 *ie; + u8 ie_len; +}; + +/** * struct ocb_setup - 802.11p OCB mode setup configuration * @chandef: defines the channel to use * @@ -3684,6 +3696,10 @@ int (*add_mpath)(struct wiphy *wiphy, struct net_device *dev, const u8 *dst, const u8 *next_hop); + int (*update_mpp)(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst, const u8 *next_hop); + int (*delete_mpp)(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst); int (*del_mpath)(struct wiphy *wiphy, struct net_device *dev, const u8 *dst); int (*change_mpath)(struct wiphy *wiphy, struct net_device *dev, @@ -3708,6 +3724,12 @@ const struct mesh_config *conf, const struct mesh_setup *setup); int (*leave_mesh)(struct wiphy *wiphy, struct net_device *dev); + int (*update_mesh_vendor_node_metrics_ie)(struct wiphy *wiphy, + struct net_device *dev, + const struct mesh_vendor_ie *vendor_ie); + int (*update_mesh_vendor_path_metrics_ie)(struct wiphy *wiphy, + struct net_device *dev, + const struct mesh_vendor_ie *vendor_ie); int (*join_ocb)(struct wiphy *wiphy, struct net_device *dev, struct ocb_setup *setup); @@ -7449,7 +7471,40 @@ */ bool cfg80211_iftype_allowed(struct wiphy *wiphy, enum nl80211_iftype iftype, bool is_4addr, u8 check_swif); - +/** + * cfg80211_notify_mesh_peer_node_metrics - notify cfg80211 of new mesh peer node metrics + * + * @dev: network device + * @macaddr: the MAC address of the new candidate + * @stype: Management frame sub type + * @signal: Frame received signal strength + * @beacon_int: Beacon interval advertised in received beacon frame + * @ie: vendor specific information elements advertised by the peer candidate + * @ie_len: lenght of the vendor specific information elements buffer + * @gfp: allocation flags + * + * This function notifies cfg80211 that the mesh peer management frame has been + * detected, most likely via a beacon or, less likely, via a probe response, probe request. + * cfg80211 then sends a notification to userspace. + */ +void cfg80211_notify_mesh_peer_node_metrics(struct net_device *dev, + const u8 *macaddr, u16 stype, s8 signal, + u32 beacon_int, const u8 *ie, u8 ie_len, gfp_t gfp); +/** + * cfg80211_notify_mesh_peer_path_metrics - notify cfg80211 of mesh peer path metrics recieved + * + * @dev: network device + * @macaddr: the MAC address of the new candidate + * @ie: information elements advertised by the peer candidate + * @ie_len: lenght of the information elements buffer + * @gfp: allocation flags + * + * This function notifies cfg80211 that the mesh path metrics has been + * recieved, most likely via a beacon or, less likely, via a probe response. + * cfg80211 then sends a notification to userspace. + */ +void cfg80211_notify_mesh_peer_path_metrics(struct net_device *dev, const u8 *macaddr, + const u8 *ie, u8 ie_len, gfp_t gfp); /* Logging, debugging and troubleshooting/diagnostic helpers. */ diff -ruw linux-5.4.60/include/net/dsa.h linux-5.4.60-fbx/include/net/dsa.h --- linux-5.4.60/include/net/dsa.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/dsa.h 2021-03-04 13:21:01.080839036 +0100 @@ -42,6 +42,7 @@ #define DSA_TAG_PROTO_8021Q_VALUE 12 #define DSA_TAG_PROTO_SJA1105_VALUE 13 #define DSA_TAG_PROTO_KSZ8795_VALUE 14 +#define DSA_TAG_PROTO_BRCM_FBX_VALUE 15 enum dsa_tag_protocol { DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE, @@ -59,6 +60,7 @@ DSA_TAG_PROTO_8021Q = DSA_TAG_PROTO_8021Q_VALUE, DSA_TAG_PROTO_SJA1105 = DSA_TAG_PROTO_SJA1105_VALUE, DSA_TAG_PROTO_KSZ8795 = DSA_TAG_PROTO_KSZ8795_VALUE, + DSA_TAG_PROTO_BRCM_FBX = DSA_TAG_PROTO_BRCM_FBX_VALUE, }; struct packet_type; @@ -123,11 +125,6 @@ struct dsa_platform_data *pd; /* - * The switch port to which the CPU is attached. - */ - struct dsa_port *cpu_dp; - - /* * Data for the individual switch chips. */ struct dsa_switch *ds[DSA_MAX_SWITCHES]; @@ -179,6 +176,8 @@ DSA_PORT_TYPE_DSA, DSA_PORT_TYPE_USER, } type; + bool is_def_cpu_port; + struct device_node *force_cpu_dn; struct dsa_switch *ds; unsigned int index; @@ -601,6 +600,7 @@ struct net_device *master; unsigned int port_number; unsigned int switch_number; + unsigned int cpu_port_number; }; static inline struct net_device * diff -ruw linux-5.4.60/include/net/ip6_tunnel.h linux-5.4.60-fbx/include/net/ip6_tunnel.h --- linux-5.4.60/include/net/ip6_tunnel.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/ip6_tunnel.h 2021-03-04 13:21:01.080839036 +0100 @@ -18,6 +18,18 @@ /* determine capability on a per-packet basis */ #define IP6_TNL_F_CAP_PER_PACKET 0x40000 +/* IPv6 tunnel FMR */ +struct __ip6_tnl_fmr { + struct __ip6_tnl_fmr *next; /* next fmr in list */ + struct in6_addr ip6_prefix; + struct in_addr ip4_prefix; + + __u8 ip6_prefix_len; + __u8 ip4_prefix_len; + __u8 ea_len; + __u8 offset; +}; + struct __ip6_tnl_parm { char name[IFNAMSIZ]; /* name of tunnel device */ int link; /* ifindex of underlying L2 interface */ @@ -29,6 +41,7 @@ __u32 flags; /* tunnel flags */ struct in6_addr laddr; /* local tunnel end-point address */ struct in6_addr raddr; /* remote tunnel end-point address */ + struct __ip6_tnl_fmr *fmrs; /* FMRs */ __be16 i_flags; __be16 o_flags; diff -ruw linux-5.4.60/include/net/ip.h linux-5.4.60-fbx/include/net/ip.h --- linux-5.4.60/include/net/ip.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/ip.h 2021-03-04 13:21:01.080839036 +0100 @@ -685,6 +685,20 @@ #endif /* + * Functions provided by ip_ffn.c + */ + +enum { + IP_FFN_FINISH_OUT, + IP_FFN_LOCAL_IN, +}; + +extern void ip_ffn_init(void); +extern int ip_ffn_process(struct sk_buff *skb); +extern void ip_ffn_add(struct sk_buff *skb, int when); +extern void ip_ffn_flush_all(void); + +/* * Functions provided by ip_forward.c */ diff -ruw linux-5.4.60/include/net/ipv6.h linux-5.4.60-fbx/include/net/ipv6.h --- linux-5.4.60/include/net/ipv6.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/ipv6.h 2021-03-04 13:21:01.080839036 +0100 @@ -1032,6 +1032,7 @@ int ip6_output(struct net *net, struct sock *sk, struct sk_buff *skb); int ip6_forward(struct sk_buff *skb); int ip6_input(struct sk_buff *skb); +int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb); int ip6_mc_input(struct sk_buff *skb); void ip6_protocol_deliver_rcu(struct net *net, struct sk_buff *skb, int nexthdr, bool have_final); @@ -1161,4 +1162,19 @@ const struct in6_addr *addr, unsigned int mode); int ipv6_sock_mc_drop(struct sock *sk, int ifindex, const struct in6_addr *addr); + +/* + * Functions provided by ipv6_ffn.c + */ + +enum { + IPV6_FFN_FINISH_OUT, + IPV6_FFN_LOCAL_IN, +}; + +extern void ipv6_ffn_init(void); +extern int ipv6_ffn_process(struct sk_buff *skb); +extern void ipv6_ffn_add(struct sk_buff *skb, int when); +extern void ipv6_ffn_flush_all(void); + #endif /* _NET_IPV6_H */ diff -ruw linux-5.4.60/include/net/mac80211.h linux-5.4.60-fbx/include/net/mac80211.h --- linux-5.4.60/include/net/mac80211.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/mac80211.h 2021-03-04 13:21:01.084172370 +0100 @@ -2337,6 +2337,8 @@ IEEE80211_HW_SUPPORTS_ONLY_HE_MULTI_BSSID, IEEE80211_HW_AMPDU_KEYBORDER_SUPPORT, + IEEE80211_HW_APVLAN_NEED_MCAST_TO_UCAST, + /* keep last, obviously */ NUM_IEEE80211_HW_FLAGS }; @@ -3759,6 +3761,8 @@ struct sk_buff *skb); int (*start)(struct ieee80211_hw *hw); void (*stop)(struct ieee80211_hw *hw); + int (*set_powered)(struct ieee80211_hw *hw); + int (*get_powered)(struct ieee80211_hw *hw, bool *up, bool *busy); #ifdef CONFIG_PM int (*suspend)(struct ieee80211_hw *hw, struct cfg80211_wowlan *wowlan); int (*resume)(struct ieee80211_hw *hw); @@ -5816,6 +5820,13 @@ void ieee80211_send_bar(struct ieee80211_vif *vif, u8 *ra, u16 tid, u16 ssn); /** + * same as ieee80211_send_bar but for given STA, allow sending to a + * STA on AP_VLAN and get a valid control->sta in the driver + */ +void ieee80211_send_bar_sta(struct ieee80211_sta *pubsta, + u16 tid, u16 ssn); + +/** * ieee80211_manage_rx_ba_offl - helper to queue an RX BA work * @vif: &struct ieee80211_vif pointer from the add_interface callback * @addr: station mac address @@ -6417,4 +6428,10 @@ struct cfg80211_nan_match_params *match, gfp_t gfp); +/** + * force dtim count value on given VIF + */ +void ieee80211_force_dtim(struct ieee80211_vif *vif, + unsigned int dtim_count); + #endif /* MAC80211_H */ diff -ruw linux-5.4.60/include/net/netfilter/nf_conntrack_expect.h linux-5.4.60-fbx/include/net/netfilter/nf_conntrack_expect.h --- linux-5.4.60/include/net/netfilter/nf_conntrack_expect.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/netfilter/nf_conntrack_expect.h 2021-03-04 13:21:01.084172370 +0100 @@ -58,13 +58,24 @@ #endif struct rcu_head rcu; + + /* private expect information. */ + char data[32] __aligned(8); }; +#define NF_CT_EXPECT_BUILD_BUG_ON(structsize) \ + BUILD_BUG_ON((structsize) > FIELD_SIZEOF(struct nf_conntrack_expect, data)) + static inline struct net *nf_ct_exp_net(struct nf_conntrack_expect *exp) { return nf_ct_net(exp->master); } +static inline void *nf_ct_exp_data(struct nf_conntrack_expect *exp) +{ + return (void *)exp->data; +} + #define NF_CT_EXP_POLICY_NAME_LEN 16 struct nf_conntrack_expect_policy { diff -ruw linux-5.4.60/include/net/netfilter/nf_conntrack.h linux-5.4.60-fbx/include/net/netfilter/nf_conntrack.h --- linux-5.4.60/include/net/netfilter/nf_conntrack.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/netfilter/nf_conntrack.h 2021-03-04 13:21:01.084172370 +0100 @@ -100,6 +100,9 @@ u_int32_t secmark; #endif + union nf_conntrack_man_proto nat_src_proto_min; + union nf_conntrack_man_proto nat_src_proto_max; + /* Extensions */ struct nf_ct_ext *ext; diff -ruw linux-5.4.60/include/net/sock.h linux-5.4.60-fbx/include/net/sock.h --- linux-5.4.60/include/net/sock.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/net/sock.h 2021-03-04 13:21:01.090839037 +0100 @@ -174,6 +174,7 @@ unsigned char skc_reuseport:1; unsigned char skc_ipv6only:1; unsigned char skc_net_refcnt:1; + unsigned char skc_reuse_conflict; int skc_bound_dev_if; union { struct hlist_node skc_bind_node; @@ -350,6 +351,7 @@ #define sk_reuseport __sk_common.skc_reuseport #define sk_ipv6only __sk_common.skc_ipv6only #define sk_net_refcnt __sk_common.skc_net_refcnt +#define sk_reuse_conflict __sk_common.skc_reuse_conflict #define sk_bound_dev_if __sk_common.skc_bound_dev_if #define sk_bind_node __sk_common.skc_bind_node #define sk_prot __sk_common.skc_prot @@ -819,6 +821,7 @@ SOCK_TXTIME, SOCK_XDP, /* XDP is attached */ SOCK_TSTAMP_NEW, /* Indicates 64 bit timestamps always */ + SOCK_UDP_DUP_UNICAST, }; #define SK_FLAGS_TIMESTAMP ((1UL << SOCK_TIMESTAMP) | (1UL << SOCK_TIMESTAMPING_RX_SOFTWARE)) diff -ruw linux-5.4.60/include/uapi/asm-generic/socket.h linux-5.4.60-fbx/include/uapi/asm-generic/socket.h --- linux-5.4.60/include/uapi/asm-generic/socket.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/asm-generic/socket.h 2021-03-04 13:21:01.114172371 +0100 @@ -30,9 +30,10 @@ #define SO_PEERCRED 17 #define SO_RCVLOWAT 18 #define SO_SNDLOWAT 19 +#endif + #define SO_RCVTIMEO_OLD 20 #define SO_SNDTIMEO_OLD 21 -#endif /* Security levels - as per NRL IPv6 - don't actually do anything */ #define SO_SECURITY_AUTHENTICATION 22 @@ -119,6 +120,8 @@ #define SO_DETACH_REUSEPORT_BPF 68 +#define SO_UDP_DUP_UNICAST 100 + #if !defined(__KERNEL__) #if __BITS_PER_LONG == 64 || (defined(__x86_64__) && defined(__ILP32__)) diff -ruw linux-5.4.60/include/uapi/linux/ethtool.h linux-5.4.60-fbx/include/uapi/linux/ethtool.h --- linux-5.4.60/include/uapi/linux/ethtool.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/ethtool.h 2021-03-04 13:21:01.124172371 +0100 @@ -221,6 +221,8 @@ ETHTOOL_RX_COPYBREAK, ETHTOOL_TX_COPYBREAK, ETHTOOL_PFC_PREVENTION_TOUT, /* timeout in msecs */ + ETHTOOL_MAC_MODE, + /* * Add your fresh new tunable attribute above and remember to update * tunable_strings[] in net/core/ethtool.c @@ -1329,6 +1331,69 @@ #define ETHTOOL_FEC_RS (1 << ETHTOOL_FEC_RS_BIT) #define ETHTOOL_FEC_BASER (1 << ETHTOOL_FEC_BASER_BIT) +/** + * struct ethtool_epon_param + * @cmd: Command number = %ETHTOOL_GEPON_PARAM or %ETHTOOL_SEPON_* + */ +struct ethtool_epon_param { + __u32 cmd; + __u8 discovery_rx; + __u8 registered; + __u16 llid; + __u32 burst_cap; + __u32 change_count; + __u32 keys_update_id; + __u8 key_sci[8]; + __u8 down_key0[16]; + __u8 down_key1[16]; + __u32 down_encrypt; + __u32 down_last_rx_encrypted; + __u32 down_last_rx_key_id; + __u16 mcast_llid; + __u16 pad; +}; + +/* + * currently a 1:1 mapping for SFP SM in drivers/net/phy/sfp.c + */ +enum { + ETHTOOL_SFP_S_DOWN = 0, + ETHTOOL_SFP_S_INIT, + ETHTOOL_SFP_S_WAIT_LOS, + ETHTOOL_SFP_S_LINK_UP, + ETHTOOL_SFP_S_TX_FAULT, + ETHTOOL_SFP_S_REINIT, + ETHTOOL_SFP_S_TX_DISABLE, +}; + +/** + * struct ethtool_sfp_state + * @cmd: Command number = %ETHTOOL_GSFP_STATE + */ +struct ethtool_sfp_state { + __u32 cmd; + + __u32 fsm_state; + + __u8 o_pwren; + __u8 o_txdis; + __u8 i_presence; + __u8 i_rxlos; + __u8 i_txfault; +}; + +/** + * struct ethtool_shaper_params + * @cmd: %ETHTOOL_GSHAPER_PARAMS / %ETHTOOL_SSHAPER_PARAMS + */ +struct ethtool_shaper_params { + __u32 cmd; + + __u64 rate; + __u32 burst; + __u32 mtu; +}; + /* CMDs currently supported */ #define ETHTOOL_GSET 0x00000001 /* DEPRECATED, Get settings. * Please use ETHTOOL_GLINKSETTINGS @@ -1424,6 +1489,20 @@ #define ETHTOOL_GFECPARAM 0x00000050 /* Get FEC settings */ #define ETHTOOL_SFECPARAM 0x00000051 /* Set FEC settings */ +#define ETHTOOL_GEPON_PARAM 0x00000052 /* Get EPON params */ +#define ETHTOOL_SEPON_KEYS 0x00000053 /* Set EPON encryption keys */ +#define ETHTOOL_SEPON_ENCRYPT 0x00000054 /* Set EPON encryption keys */ +#define ETHTOOL_SEPON_RESTART 0x00000055 /* restart epon link */ +#define ETHTOOL_SEPON_BURST 0x00000056 /* update burst value */ +#define ETHTOOL_SEPON_ADD_MCLLID 0x00000057 /* add epon llid */ +#define ETHTOOL_SEPON_DEL_MCLLID 0x00000058 /* remove epon llid */ +#define ETHTOOL_SEPON_CLR_MCLLID 0x00000059 /* remove all epon llid */ + +#define ETHTOOL_GSFP_STATE 0x00000060 /* get SFP state (IOs/FSM) */ + +#define ETHTOOL_SSHAPER_PARAMS 0x00000061 /* set HW TX shaper params */ +#define ETHTOOL_GSHAPER_PARAMS 0x00000062 /* get HW TX shaper params */ + /* compatibility with older code */ #define SPARC_ETH_GSET ETHTOOL_GSET #define SPARC_ETH_SSET ETHTOOL_SSET @@ -1508,6 +1587,13 @@ ETHTOOL_LINK_MODE_100baseT1_Full_BIT = 67, ETHTOOL_LINK_MODE_1000baseT1_Full_BIT = 68, + ETHTOOL_LINK_MODE_1000basePX_D_Full_BIT = 69, + ETHTOOL_LINK_MODE_1000basePX_U_Full_BIT = 70, + ETHTOOL_LINK_MODE_10000basePR_D_Full_BIT = 71, + ETHTOOL_LINK_MODE_10000basePR_U_Full_BIT = 72, + ETHTOOL_LINK_MODE_10000_1000basePRX_D_Full_BIT = 73, + ETHTOOL_LINK_MODE_10000_1000basePRX_U_Full_BIT = 74, + /* must be last entry */ __ETHTOOL_LINK_MODE_MASK_NBITS }; diff -ruw linux-5.4.60/include/uapi/linux/if_ether.h linux-5.4.60-fbx/include/uapi/linux/if_ether.h --- linux-5.4.60/include/uapi/linux/if_ether.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/if_ether.h 2021-03-04 13:21:01.127505705 +0100 @@ -116,6 +116,7 @@ #define ETH_P_802_3_MIN 0x0600 /* If the value in the ethernet type is less than this value * then the frame is Ethernet II. Else it is 802.3 */ +#define ETH_P_NMESH_MBH 0xFFFE /* NMESHD beacon eth protocol */ /* * Non DIX types. Won't clash for 1500 types. diff -ruw linux-5.4.60/include/uapi/linux/if_tun.h linux-5.4.60-fbx/include/uapi/linux/if_tun.h --- linux-5.4.60/include/uapi/linux/if_tun.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/if_tun.h 2021-03-04 13:21:01.127505705 +0100 @@ -62,6 +62,32 @@ #define TUNSETCARRIER _IOW('T', 226, int) #define TUNGETDEVNETNS _IO('T', 227) + +struct smalltun_rule { + __u8 proto; + __be16 src_port_start; + __be16 src_port_end; + __be16 dst_port_start; + __be16 dst_port_end; +}; + +struct smalltun_fp { + __be32 inner_src; + __be32 inner_dst; + + __u32 af; + __u8 outer_src[16]; + __u8 outer_dst[16]; + __be16 outer_src_port; + __be16 outer_dst_port; + + struct smalltun_rule rules[8]; + __u32 rule_count; +}; + +#define TUNSMALLTUNSETFP _IOW('T', 228, struct smalltun_fp) +#define TUNSMALLTUNDELFP _IOW('T', 229, struct smalltun_fp) + /* TUNSETIFF ifr flags */ #define IFF_TUN 0x0001 #define IFF_TAP 0x0002 diff -ruw linux-5.4.60/include/uapi/linux/if_tunnel.h linux-5.4.60-fbx/include/uapi/linux/if_tunnel.h --- linux-5.4.60/include/uapi/linux/if_tunnel.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/if_tunnel.h 2021-03-04 13:21:01.127505705 +0100 @@ -77,10 +77,23 @@ IFLA_IPTUN_ENCAP_DPORT, IFLA_IPTUN_COLLECT_METADATA, IFLA_IPTUN_FWMARK, + IFLA_IPTUN_FMRS, __IFLA_IPTUN_MAX, }; #define IFLA_IPTUN_MAX (__IFLA_IPTUN_MAX - 1) +enum { + IFLA_IPTUN_FMR_UNSPEC, + IFLA_IPTUN_FMR_IP6_PREFIX, + IFLA_IPTUN_FMR_IP4_PREFIX, + IFLA_IPTUN_FMR_IP6_PREFIX_LEN, + IFLA_IPTUN_FMR_IP4_PREFIX_LEN, + IFLA_IPTUN_FMR_EA_LEN, + IFLA_IPTUN_FMR_OFFSET, + __IFLA_IPTUN_FMR_MAX, +}; +#define IFLA_IPTUN_FMR_MAX (__IFLA_IPTUN_FMR_MAX - 1) + enum tunnel_encap_types { TUNNEL_ENCAP_NONE, TUNNEL_ENCAP_FOU, diff -ruw linux-5.4.60/include/uapi/linux/libc-compat.h linux-5.4.60-fbx/include/uapi/linux/libc-compat.h --- linux-5.4.60/include/uapi/linux/libc-compat.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/libc-compat.h 2021-03-04 13:21:01.130839039 +0100 @@ -49,11 +49,11 @@ #ifndef _UAPI_LIBC_COMPAT_H #define _UAPI_LIBC_COMPAT_H -/* We have included glibc headers... */ -#if defined(__GLIBC__) +/* We have included libc headers... */ +#if !defined(__KERNEL__) -/* Coordinate with glibc net/if.h header. */ -#if defined(_NET_IF_H) && defined(__USE_MISC) +/* Coordinate with libc net/if.h header. */ +#if defined(_NET_IF_H) && (!defined(__GLIBC__) || defined(__USE_MISC)) /* GLIBC headers included first so don't define anything * that would already be defined. */ @@ -65,9 +65,11 @@ /* Everything up to IFF_DYNAMIC, matches net/if.h until glibc 2.23 */ #define __UAPI_DEF_IF_NET_DEVICE_FLAGS 0 /* For the future if glibc adds IFF_LOWER_UP, IFF_DORMANT and IFF_ECHO */ +#ifndef IFF_ECHO #ifndef __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO #define __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO 1 #endif /* __UAPI_DEF_IF_NET_DEVICE_FLAGS_LOWER_UP_DORMANT_ECHO */ +#endif /* IFF_ECHO */ #else /* _NET_IF_H */ @@ -170,7 +172,7 @@ * or we are being included in the kernel, then define everything * that we need. Check for previous __UAPI_* definitions to give * unsupported C libraries a way to opt out of any kernel definition. */ -#else /* !defined(__GLIBC__) */ +#else /* !defined(__KERNEL__) */ /* Definitions for if.h */ #ifndef __UAPI_DEF_IF_IFCONF @@ -262,6 +264,6 @@ #define __UAPI_DEF_XATTR 1 #endif -#endif /* __GLIBC__ */ +#endif /* __KERNEL__ */ #endif /* _UAPI_LIBC_COMPAT_H */ diff -ruw linux-5.4.60/include/uapi/linux/nl80211.h linux-5.4.60-fbx/include/uapi/linux/nl80211.h --- linux-5.4.60/include/uapi/linux/nl80211.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/nl80211.h 2021-03-04 13:21:01.137505705 +0100 @@ -1324,6 +1324,10 @@ NL80211_CMD_UPDATE_OWE_INFO, NL80211_CMD_PROBE_MESH_LINK, + NL80211_CMD_MESH_PEER_NODE_METRICS, + NL80211_CMD_MESH_PEER_PATH_METRICS, + NL80211_CMD_SET_MPP, + NL80211_CMD_DEL_MPP, /* add new commands above here */ @@ -2834,6 +2838,7 @@ NL80211_ATTR_WIPHY_EDMG_CHANNELS, NL80211_ATTR_WIPHY_EDMG_BW_CONFIG, + NL80211_ATTR_SIGNAL_STRENGTH, /* add attributes here, update the policy in nl80211.c */ @@ -2842,6 +2847,8 @@ NL80211_ATTR_MAX = __NL80211_ATTR_AFTER_LAST - 1 }; +# define NL80211_QBC_UPDATE_NODE_METRICS_IE 1 +# define NL80211_QBC_UPDATE_PATH_METRICS_IE 2 /* source-level API compatibility */ #define NL80211_ATTR_SCAN_GENERATION NL80211_ATTR_GENERATION #define NL80211_ATTR_MESH_PARAMS NL80211_ATTR_MESH_CONFIG diff -ruw linux-5.4.60/include/uapi/linux/serial_core.h linux-5.4.60-fbx/include/uapi/linux/serial_core.h --- linux-5.4.60/include/uapi/linux/serial_core.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/serial_core.h 2021-03-04 13:21:01.140839039 +0100 @@ -293,4 +293,7 @@ /* Freescale Linflex UART */ #define PORT_LINFLEXUART 122 +/* BCM63xx HS */ +#define PORT_BCM63XX_HS 123 + #endif /* _UAPILINUX_SERIAL_CORE_H */ diff -ruw linux-5.4.60/include/uapi/linux/sockios.h linux-5.4.60-fbx/include/uapi/linux/sockios.h --- linux-5.4.60/include/uapi/linux/sockios.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/sockios.h 2021-03-04 13:21:01.140839039 +0100 @@ -153,6 +153,14 @@ #define SIOCSHWTSTAMP 0x89b0 /* set and get config */ #define SIOCGHWTSTAMP 0x89b1 /* get config */ +/* fbxbridge call */ +#define SIOCGFBXBRIDGE 0x89c0 /* fbxbridge support */ +#define SIOCSFBXBRIDGE 0x89c1 /* Set fbxbridge options */ + +/* fbxdiverter call */ +#define SIOCGFBXDIVERT 0x89d0 /* fbxdiverter support */ +#define SIOCSFBXDIVERT 0x89d1 /* Set fbxdiverter options */ + /* Device private ioctl calls */ /* diff -ruw linux-5.4.60/include/uapi/linux/swab.h linux-5.4.60-fbx/include/uapi/linux/swab.h --- linux-5.4.60/include/uapi/linux/swab.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/swab.h 2021-03-04 13:21:01.140839039 +0100 @@ -3,7 +3,7 @@ #define _UAPI_LINUX_SWAB_H #include -#include +#include #include #include diff -ruw linux-5.4.60/include/uapi/linux/tcp.h linux-5.4.60-fbx/include/uapi/linux/tcp.h --- linux-5.4.60/include/uapi/linux/tcp.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/tcp.h 2021-03-04 13:21:01.144172372 +0100 @@ -134,6 +134,8 @@ #define TCP_REPAIR_OFF 0 #define TCP_REPAIR_OFF_NO_WP -1 /* Turn off without window probes */ +#define TCP_LINEAR_RTO 128 /* force use of linear timeouts */ + struct tcp_repair_opt { __u32 opt_code; __u32 opt_val; diff -ruw linux-5.4.60/include/uapi/linux/tty.h linux-5.4.60-fbx/include/uapi/linux/tty.h --- linux-5.4.60/include/uapi/linux/tty.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/include/uapi/linux/tty.h 2021-03-04 13:21:01.144172372 +0100 @@ -38,5 +38,6 @@ #define N_NCI 25 /* NFC NCI UART */ #define N_SPEAKUP 26 /* Speakup communication with synths */ #define N_NULL 27 /* Null ldisc used for error handling */ +#define N_REMOTI 28 /* RemoTI over UART */ #endif /* _UAPI_LINUX_TTY_H */ diff -ruw linux-5.4.60/init/initramfs.c linux-5.4.60-fbx/init/initramfs.c --- linux-5.4.60/init/initramfs.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/init/initramfs.c 2021-03-04 13:21:01.157505706 +0100 @@ -10,6 +10,7 @@ #include #include #include +#include static ssize_t __init xwrite(int fd, const char *p, size_t count) { @@ -621,6 +622,10 @@ { ssize_t written; int fd; +#ifdef CONFIG_FBX_DECRYPT_INITRD + int ret; + extern int fbx_decrypt_initrd(char *start, u32 size); +#endif unpack_to_rootfs(__initramfs_start, __initramfs_size); @@ -630,6 +635,15 @@ if (fd < 0) return; +#ifdef CONFIG_FBX_DECRYPT_INITRD + ret = fbx_decrypt_initrd((char*)initrd_start, + initrd_end - initrd_start); + if (ret) { + printk(KERN_ERR "Decrypt failed: %i\n", ret); + return; + } +#endif + written = xwrite(fd, (char *)initrd_start, initrd_end - initrd_start); if (written != initrd_end - initrd_start) pr_err("/initrd.image: incomplete write (%zd != %ld)\n", diff -ruw linux-5.4.60/init/init_task.c linux-5.4.60-fbx/init/init_task.c --- linux-5.4.60/init/init_task.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/init/init_task.c 2021-03-04 13:21:01.157505706 +0100 @@ -66,6 +66,7 @@ .stack = init_stack, .usage = REFCOUNT_INIT(2), .flags = PF_KTHREAD, + .exec_mode = EXEC_MODE_UNLIMITED, .prio = MAX_PRIO - 20, .static_prio = MAX_PRIO - 20, .normal_prio = MAX_PRIO - 20, diff -ruw linux-5.4.60/init/Kconfig linux-5.4.60-fbx/init/Kconfig --- linux-5.4.60/init/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/init/Kconfig 2021-03-04 13:21:01.157505706 +0100 @@ -74,6 +74,15 @@ Maximum of each of the number of arguments and environment variables passed to init from the kernel command line. + +config CROSS_COMPILE + string "Cross-compiler tool prefix" + help + Same as running 'make CROSS_COMPILE=prefix-' but stored for + default make runs in this kernel build directory. You don't + need to set this unless you want the configured kernel build + directory to select the cross-compiler automatically. + config COMPILE_TEST bool "Compile also drivers which will not load" depends on !UML @@ -671,6 +680,15 @@ 13 => 8 KB for each CPU 12 => 4 KB for each CPU +config FBX_DECRYPT_INITRD + bool "Decrypt initrd at boot" + depends on BLK_DEV_RAM + default n + +config FBX_DECRYPT_INITRD_KEY + string "Decryption key" + depends on FBX_DECRYPT_INITRD + # # Architectures with an unreliable sched_clock() should select this: # diff -ruw linux-5.4.60/init/Makefile linux-5.4.60-fbx/init/Makefile --- linux-5.4.60/init/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/init/Makefile 2021-03-04 13:21:01.157505706 +0100 @@ -15,6 +15,8 @@ obj-y += init_task.o +obj-$(CONFIG_FBX_DECRYPT_INITRD)+= fbx_decrypt_initrd.o rc4.o + mounts-y := do_mounts.o mounts-$(CONFIG_BLK_DEV_RAM) += do_mounts_rd.o mounts-$(CONFIG_BLK_DEV_INITRD) += do_mounts_initrd.o diff -ruw linux-5.4.60/kernel/fork.c linux-5.4.60-fbx/kernel/fork.c --- linux-5.4.60/kernel/fork.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/kernel/fork.c 2021-03-04 13:21:01.280839045 +0100 @@ -944,6 +944,12 @@ #ifdef CONFIG_MEMCG tsk->active_memcg = NULL; #endif + + /* + * inherit parent exec_mode. + */ + tsk->exec_mode = orig->exec_mode; + return tsk; free_stack: diff -ruw linux-5.4.60/kernel/sys.c linux-5.4.60-fbx/kernel/sys.c --- linux-5.4.60/kernel/sys.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/kernel/sys.c 2021-03-04 13:21:01.304172379 +0100 @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -2486,6 +2487,18 @@ return -EINVAL; error = GET_TAGGED_ADDR_CTRL(); break; + case PR_SET_EXEC_MODE: + if (arg2 != EXEC_MODE_UNLIMITED && + arg2 != EXEC_MODE_ONCE && + arg2 != EXEC_MODE_DENIED) + return -EINVAL; + + if (arg2 > current->exec_mode) + return -EPERM; + current->exec_mode = arg2; + return 0; + case PR_GET_EXEC_MODE: + return current->exec_mode; default: error = -EINVAL; break; diff -ruw linux-5.4.60/lib/Kconfig linux-5.4.60-fbx/lib/Kconfig --- linux-5.4.60/lib/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/lib/Kconfig 2021-03-04 13:21:01.320839047 +0100 @@ -635,6 +635,13 @@ config STRING_SELFTEST tristate "Test string functions" +config ARCH_HAS_FBXSERIAL + bool + +config FBXSERIAL + bool "fbxserial" + select CRC32 + endmenu config GENERIC_LIB_ASHLDI3 diff -ruw linux-5.4.60/lib/Makefile linux-5.4.60-fbx/lib/Makefile --- linux-5.4.60/lib/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/lib/Makefile 2021-03-04 13:21:01.320839047 +0100 @@ -290,3 +290,5 @@ obj-$(CONFIG_GENERIC_LIB_CMPDI2) += cmpdi2.o obj-$(CONFIG_GENERIC_LIB_UCMPDI2) += ucmpdi2.o obj-$(CONFIG_OBJAGG) += objagg.o + +obj-$(CONFIG_FBXSERIAL) += fbxserial.o diff -ruw linux-5.4.60/Makefile linux-5.4.60-fbx/Makefile --- linux-5.4.60/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/Makefile 2021-04-21 12:07:02.445231322 +0200 @@ -355,6 +355,8 @@ # CROSS_COMPILE can be set on the command line # make CROSS_COMPILE=ia64-linux- # Alternatively CROSS_COMPILE can be set in the environment. +# A third alternative is to store a setting in .config so that plain +# "make" in the configured kernel build directory always uses that. # Default value for CROSS_COMPILE is not to prefix executables # Note: Some architectures assign CROSS_COMPILE in their arch/*/Makefile ARCH ?= $(SUBARCH) @@ -387,6 +389,9 @@ KCONFIG_CONFIG ?= .config export KCONFIG_CONFIG +CONFIG_CROSS_COMPILE := $(shell grep ^CONFIG_CROSS_COMPILE= $(KCONFIG_CONFIG) | cut -f 2 -d = | tr -d '"') +CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%) + # SHELL used by kbuild CONFIG_SHELL := sh @@ -1181,7 +1186,7 @@ quiet_cmd_headers_install = INSTALL $(INSTALL_HDR_PATH)/include cmd_headers_install = \ mkdir -p $(INSTALL_HDR_PATH); \ - rsync -mrl --include='*/' --include='*\.h' --exclude='*' \ + rsync -cmrl --include='*/' --include='*\.h' --exclude='*' \ usr/include $(INSTALL_HDR_PATH) PHONY += headers_install diff -ruw linux-5.4.60/net/8021q/vlan.c linux-5.4.60-fbx/net/8021q/vlan.c --- linux-5.4.60/net/8021q/vlan.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/8021q/vlan.c 2021-03-04 13:21:01.367505716 +0100 @@ -210,7 +210,7 @@ /* Attach a VLAN device to a mac address (ie Ethernet Card). * Returns 0 if the device was created or a negative error code otherwise. */ -static int register_vlan_device(struct net_device *real_dev, u16 vlan_id) +int register_vlan_device(struct net_device *real_dev, u16 vlan_id) { struct net_device *new_dev; struct vlan_dev_priv *vlan; diff -ruw linux-5.4.60/net/8021q/vlan_core.c linux-5.4.60-fbx/net/8021q/vlan_core.c --- linux-5.4.60/net/8021q/vlan_core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/8021q/vlan_core.c 2021-03-04 13:21:01.367505716 +0100 @@ -98,6 +98,12 @@ } EXPORT_SYMBOL(__vlan_find_dev_deep_rcu); +struct net_device *vlan_dev_upper_dev(const struct net_device *dev) +{ + return vlan_dev_priv(dev)->real_dev; +} +EXPORT_SYMBOL(vlan_dev_upper_dev); + struct net_device *vlan_dev_real_dev(const struct net_device *dev) { struct net_device *ret = vlan_dev_priv(dev)->real_dev; diff -ruw linux-5.4.60/net/8021q/vlanproc.c linux-5.4.60-fbx/net/8021q/vlanproc.c --- linux-5.4.60/net/8021q/vlanproc.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/8021q/vlanproc.c 2021-03-04 13:21:01.370839049 +0100 @@ -252,7 +252,7 @@ stats = dev_get_stats(vlandev, &temp); seq_printf(seq, - "%s VID: %d REORDER_HDR: %i dev->priv_flags: %hx\n", + "%s VID: %d REORDER_HDR: %i dev->priv_flags: %llx\n", vlandev->name, vlan->vlan_id, (int)(vlan->flags & 1), vlandev->priv_flags); diff -ruw linux-5.4.60/net/bluetooth/hci_event.c linux-5.4.60-fbx/net/bluetooth/hci_event.c --- linux-5.4.60/net/bluetooth/hci_event.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bluetooth/hci_event.c 2021-03-04 13:21:01.384172383 +0100 @@ -684,7 +684,9 @@ if (rp->status) return; - if (hdev->max_page < rp->max_page) + if (!test_bit(HCI_QUIRK_BROKEN_LOCAL_EXT_FTR_MAX_PAGE, + &hdev->quirks) && + hdev->max_page < rp->max_page) hdev->max_page = rp->max_page; if (rp->page < HCI_MAX_PAGES) diff -ruw linux-5.4.60/net/bluetooth/hci_request.c linux-5.4.60-fbx/net/bluetooth/hci_request.c --- linux-5.4.60/net/bluetooth/hci_request.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bluetooth/hci_request.c 2021-03-04 13:21:01.384172383 +0100 @@ -1130,13 +1130,14 @@ return ad_len; /* use complete name if present and fits */ - complete_len = strlen(hdev->dev_name); - if (complete_len && complete_len <= HCI_MAX_SHORT_NAME_LENGTH) + complete_len = strnlen(hdev->dev_name, sizeof (hdev->dev_name)); + if (complete_len && complete_len <= HCI_MAX_SHORT_NAME_LENGTH) { return eir_append_data(ptr, ad_len, EIR_NAME_COMPLETE, hdev->dev_name, complete_len + 1); + } /* use short name if present */ - short_len = strlen(hdev->short_name); + short_len = strnlen(hdev->short_name, sizeof (hdev->short_name)); if (short_len) return eir_append_data(ptr, ad_len, EIR_NAME_SHORT, hdev->short_name, short_len + 1); diff -ruw linux-5.4.60/net/bridge/br_device.c linux-5.4.60-fbx/net/bridge/br_device.c --- linux-5.4.60/net/bridge/br_device.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bridge/br_device.c 2021-03-04 13:21:01.387505716 +0100 @@ -225,6 +225,7 @@ struct net_bridge *br = netdev_priv(dev); dev->mtu = new_mtu; + br->forced_mtu = new_mtu; /* this flag will be cleared if the MTU was automatically adjusted */ br_opt_toggle(br, BROPT_MTU_SET_BY_USER, true); diff -ruw linux-5.4.60/net/bridge/br_fdb.c linux-5.4.60-fbx/net/bridge/br_fdb.c --- linux-5.4.60/net/bridge/br_fdb.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bridge/br_fdb.c 2021-03-04 13:21:01.387505716 +0100 @@ -554,28 +554,48 @@ return ret; } -void br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, +bool br_fdb_update_only(struct net_bridge *br, + struct net_bridge_port *source, + const unsigned char *addr) +{ + struct net_bridge_fdb_entry *fdb; + + fdb = br_fdb_find_rcu(br, addr, 0); + if (!fdb) + return false; + + fdb->updated = jiffies; + return true; +} + +int br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid, bool added_by_user) { struct net_bridge_fdb_entry *fdb; bool fdb_modified = false; + int ret = 0; /* some users want to always flood. */ if (hold_time(br) == 0) - return; + return ret; /* ignore packets unless we are using this port */ if (!(source->state == BR_STATE_LEARNING || source->state == BR_STATE_FORWARDING)) - return; + return ret; fdb = fdb_find_rcu(&br->fdb_hash_tbl, addr, vid); if (likely(fdb)) { + + if (likely(fdb->added_by_user)) + return ret; + /* attempt to update an entry for a local interface */ if (unlikely(fdb->is_local)) { if (net_ratelimit()) br_warn(br, "received packet on %s with own address as source address (addr:%pM, vlan:%u)\n", source->dev->name, addr, vid); + ret = -ELOOP; } else { unsigned long now = jiffies; @@ -611,6 +631,7 @@ */ spin_unlock(&br->hash_lock); } + return ret; } static int fdb_to_nud(const struct net_bridge *br, diff -ruw linux-5.4.60/net/bridge/br_forward.c linux-5.4.60-fbx/net/bridge/br_forward.c --- linux-5.4.60/net/bridge/br_forward.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bridge/br_forward.c 2021-03-04 13:21:01.387505716 +0100 @@ -22,12 +22,28 @@ const struct sk_buff *skb) { struct net_bridge_vlan_group *vg; + const unsigned char *dest; + struct net_bridge_fdb_entry *fdb_dst = NULL; + u16 vid = 0; + int ret = 0; + + dest = skb_mac_header(skb); + + rcu_read_lock(); + if (is_unicast_ether_addr(dest)) { + if (br_vlan_enabled(p->dev)) + br_vlan_get_tag(skb, &vid); + fdb_dst = br_fdb_find_rcu(p->br, dest, vid); + } vg = nbp_vlan_group_rcu(p); - return ((p->flags & BR_HAIRPIN_MODE) || skb->dev != p->dev) && - br_allowed_egress(vg, skb) && p->state == BR_STATE_FORWARDING && + ret = ((p->flags & BR_HAIRPIN_MODE) || skb->dev != p->dev) && + br_allowed_egress(vg, skb) && ((p->state == BR_STATE_FORWARDING) || + ((p->state == BR_STATE_BLOCKING) && fdb_dst && fdb_dst->added_by_user)) && nbp_switchdev_allowed_egress(p, skb) && !br_skb_isolated(p, skb); + rcu_read_unlock(); + return ret; } int br_dev_queue_push_xmit(struct net *net, struct sock *sk, struct sk_buff *skb) diff -ruw linux-5.4.60/net/bridge/br_if.c linux-5.4.60-fbx/net/bridge/br_if.c --- linux-5.4.60/net/bridge/br_if.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bridge/br_if.c 2021-03-04 13:21:01.387505716 +0100 @@ -490,13 +490,13 @@ static int br_mtu_min(const struct net_bridge *br) { const struct net_bridge_port *p; - int ret_mtu = 0; + int ret_mtu = min_t(unsigned int, br->forced_mtu, ETH_DATA_LEN); list_for_each_entry(p, &br->port_list, list) if (!ret_mtu || ret_mtu > p->dev->mtu) ret_mtu = p->dev->mtu; - return ret_mtu ? ret_mtu : ETH_DATA_LEN; + return ret_mtu; } void br_mtu_auto_adjust(struct net_bridge *br) diff -ruw linux-5.4.60/net/bridge/br_input.c linux-5.4.60-fbx/net/bridge/br_input.c --- linux-5.4.60/net/bridge/br_input.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bridge/br_input.c 2021-03-04 13:21:01.387505716 +0100 @@ -87,8 +87,10 @@ /* insert into forwarding database after filtering to avoid spoofing */ br = p->br; - if (p->flags & BR_LEARNING) - br_fdb_update(br, p, eth_hdr(skb)->h_source, vid, false); + if (p->flags & BR_LEARNING && + br_fdb_update(br, p, eth_hdr(skb)->h_source, vid, false)) { + goto drop; + } local_rcv = !!(br->dev->flags & IFF_PROMISC); if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) { @@ -151,7 +153,7 @@ if (dst) { unsigned long now = jiffies; - if (dst->is_local) + if (dst->is_local && !dst->added_by_user) return br_pass_frame_up(skb); if (now != dst->used) @@ -249,6 +251,34 @@ return RX_HANDLER_CONSUMED; } +/* Don't forward packets to originating port or forwarding disabled */ +static inline int br_drop_input_pkt(const struct net_bridge_port *p, + const struct sk_buff *skb) +{ + const unsigned char *dest; + struct net_bridge_fdb_entry *fdb_dst = NULL; + u16 vid = 0; + int ret = 1; + + dest = skb_mac_header(skb); + + if (!is_unicast_ether_addr(dest)) + goto out; + + rcu_read_lock(); + if (br_vlan_enabled(p->dev)) + br_vlan_get_tag(skb, &vid); + + fdb_dst = br_fdb_find_rcu(p->br, dest, vid); + if (fdb_dst) + ret = 0; + + rcu_read_unlock(); + +out: + return ret; +} + /* * Return NULL if skb is handled * note: already called with rcu_read_lock @@ -340,6 +370,10 @@ forward: switch (p->state) { + case BR_STATE_BLOCKING: + if (br_drop_input_pkt(p, skb)) + goto drop; + /* fall through */ case BR_STATE_FORWARDING: case BR_STATE_LEARNING: if (ether_addr_equal(p->br->dev->dev_addr, dest)) diff -ruw linux-5.4.60/net/bridge/br_private.h linux-5.4.60-fbx/net/bridge/br_private.h --- linux-5.4.60/net/bridge/br_private.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bridge/br_private.h 2021-03-04 13:21:01.387505716 +0100 @@ -417,6 +417,7 @@ int offload_fwd_mark; #endif struct hlist_head fdb_list; + unsigned int forced_mtu; }; struct br_input_skb_cb { @@ -565,7 +566,10 @@ unsigned long off); int br_fdb_insert(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid); -void br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, +bool br_fdb_update_only(struct net_bridge *br, + struct net_bridge_port *source, + const unsigned char *addr); +int br_fdb_update(struct net_bridge *br, struct net_bridge_port *source, const unsigned char *addr, u16 vid, bool added_by_user); int br_fdb_delete(struct ndmsg *ndm, struct nlattr *tb[], diff -ruw linux-5.4.60/net/bridge/br_private_stp.h linux-5.4.60-fbx/net/bridge/br_private_stp.h --- linux-5.4.60/net/bridge/br_private_stp.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/bridge/br_private_stp.h 2021-03-04 13:21:01.387505716 +0100 @@ -23,7 +23,7 @@ #define BR_MAX_MAX_AGE (40*HZ) #define BR_MIN_PATH_COST 1 -#define BR_MAX_PATH_COST 65535 +#define BR_MAX_PATH_COST 5000000 struct br_config_bpdu { unsigned int topology_change:1; diff -ruw linux-5.4.60/net/core/dev.c linux-5.4.60-fbx/net/core/dev.c --- linux-5.4.60/net/core/dev.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/core/dev.c 2021-03-04 13:21:01.397505717 +0100 @@ -143,6 +143,7 @@ #include #include #include +#include #include "net-sysfs.h" @@ -151,6 +152,9 @@ /* This should be increased if a protocol with a bigger head is added. */ #define GRO_MAX_HEAD (MAX_HEADER + 128) +int (*nmesh_mbh_bridge_rx)(struct sk_buff *skb) __rcu __read_mostly; +EXPORT_SYMBOL_GPL(nmesh_mbh_bridge_rx); + static DEFINE_SPINLOCK(ptype_lock); static DEFINE_SPINLOCK(offload_lock); struct list_head ptype_base[PTYPE_HASH_SIZE] __read_mostly; @@ -165,6 +169,10 @@ struct netlink_ext_ack *extack); static struct napi_struct *napi_by_id(unsigned int napi_id); +#ifdef CONFIG_NETRXTHREAD +struct krxd gkrxd[CONFIG_NETRXTHREAD_RX_QUEUE]; +#endif + /* * The @dev_base_head list is protected by @dev_base_lock and the rtnl * semaphore. @@ -1095,22 +1103,6 @@ net = dev_net(dev); - /* Some auto-enslaved devices e.g. failover slaves are - * special, as userspace might rename the device after - * the interface had been brought up and running since - * the point kernel initiated auto-enslavement. Allow - * live name change even when these slave devices are - * up and running. - * - * Typically, users of these auto-enslaving devices - * don't actually care about slave name change, as - * they are supposed to operate on master interface - * directly. - */ - if (dev->flags & IFF_UP && - likely(!(dev->priv_flags & IFF_LIVE_RENAME_OK))) - return -EBUSY; - down_write(&devnet_rename_sem); if (strncmp(newname, dev->name, IFNAMSIZ) == 0) { @@ -4429,6 +4421,23 @@ return ret; } +/* Start Freebox added code */ +#if defined(CONFIG_FREEBOX_DIVERTER) || defined(CONFIG_FREEBOX_DIVERTER_MODULE) +int (*fbxdiverter_hook)(struct sk_buff *); + +static int handle_fbxdiverter(struct sk_buff *skb) +{ + /* try_module_get is missing here, so there is a race on + * fbxdiverter module deletion */ + if (!fbxdiverter_hook) + return 0; + return fbxdiverter_hook(skb); +} + +EXPORT_SYMBOL(fbxdiverter_hook); +#endif + + /** * netif_rx - post buffer to the network code * @skb: buffer to post @@ -4711,28 +4720,117 @@ return 0; } +static int __netif_receive_skb_core_end(struct sk_buff **pskb, bool pfmemalloc, + struct packet_type **ppt_prev); + static int __netif_receive_skb_core(struct sk_buff **pskb, bool pfmemalloc, struct packet_type **ppt_prev) { - struct packet_type *ptype, *pt_prev; - rx_handler_func_t *rx_handler; +#ifdef CONFIG_NETRXTHREAD + unsigned int len; + struct krxd *krxd; +#endif struct sk_buff *skb = *pskb; - struct net_device *orig_dev; - bool deliver_exact = false; - int ret = NET_RX_DROP; - __be16 type; net_timestamp_check(!netdev_tstamp_prequeue, skb); trace_netif_receive_skb(skb); - orig_dev = skb->dev; - skb_reset_network_header(skb); if (!skb_transport_header_was_set(skb)) skb_reset_transport_header(skb); skb_reset_mac_len(skb); +#if defined(CONFIG_FREEBOX_DIVERTER) || defined(CONFIG_FREEBOX_DIVERTER_MODULE) + if (handle_fbxdiverter(skb)) + return NET_RX_SUCCESS; +#endif + +#ifndef CONFIG_NETRXTHREAD + return __netif_receive_skb_core_end(pskb, pfmemalloc, ppt_prev); +#else + if (pfmemalloc) + return __netif_receive_skb_core_end(pskb, pfmemalloc, ppt_prev); + + BUILD_BUG_ON(ARRAY_SIZE(gkrxd) < 2); + krxd = &gkrxd[skb->rxthread_prio & 1]; + + /* queue the packet to the rx thread */ + local_bh_disable(); + len = skb_queue_len(&krxd->pkt_queue); + if (len < RXTHREAD_MAX_PKTS) { + __skb_queue_tail(&krxd->pkt_queue, skb); + krxd->stats_pkts++; + if (!len) + wake_up(&krxd->wq); + } else { + krxd->stats_dropped++; + dev_kfree_skb(skb); + } + local_bh_enable(); + return NET_RX_SUCCESS; +#endif +} + +#ifdef CONFIG_NETRXTHREAD +static int krxd_action(void *data) +{ + struct krxd *krxd = (struct krxd *)data; + unsigned int queue = krxd - gkrxd; + struct sk_buff *skb; + + set_user_nice(current, queue > 0 ? -10 : -5); + current->flags |= PF_NOFREEZE; + __set_current_state(TASK_RUNNING); + + local_bh_disable(); + while (1) { + struct packet_type *pt_prev = NULL; + struct net_device *orig_dev; + + skb = skb_dequeue(&krxd->pkt_queue); + if (!skb) { + local_bh_enable(); + wait_event_interruptible(krxd->wq, + skb_queue_len(&krxd->pkt_queue)); + set_current_state(TASK_RUNNING); + local_bh_disable(); + continue; + } + + rcu_read_lock(); + orig_dev = skb->dev; + __netif_receive_skb_core_end(&skb, false, &pt_prev); + if (pt_prev) + INDIRECT_CALL_INET(pt_prev->func, + ipv6_rcv, ip_rcv, skb, + skb->dev, pt_prev, orig_dev); + rcu_read_unlock(); + + /* only schedule when working on lowest prio queue */ + if (queue == 0 && need_resched()) { + local_bh_enable(); + schedule(); + local_bh_disable(); + } + } + return 0; +} +#endif + +static int __netif_receive_skb_core_end(struct sk_buff **pskb, bool pfmemalloc, + struct packet_type **ppt_prev) +{ + struct sk_buff *skb = *pskb; + struct packet_type *ptype, *pt_prev; + rx_handler_func_t *rx_handler; + struct net_device *orig_dev; + bool deliver_exact = false; + int ret = NET_RX_DROP; + __be16 type; + int (*nmesh_mbh_rx)(struct sk_buff *skb); + + orig_dev = skb->dev; pt_prev = NULL; another_round: @@ -4761,6 +4859,13 @@ goto out; } + if ((skb->protocol == cpu_to_be16(ETH_P_NMESH_MBH)) || + unlikely(is_multicast_ether_addr(eth_hdr(skb)->h_dest))) { + nmesh_mbh_rx = rcu_dereference(nmesh_mbh_bridge_rx); + if (nmesh_mbh_rx && nmesh_mbh_rx(skb)) + goto out; + } + if (skb_skip_tc_classify(skb)) goto skip_classify; @@ -4885,7 +4990,9 @@ if (pt_prev) { if (unlikely(skb_orphan_frags_rx(skb, GFP_ATOMIC))) goto drop; - *ppt_prev = pt_prev; + else + ret = INDIRECT_CALL_INET(pt_prev->func, ipv6_rcv, ip_rcv, skb, + skb->dev, pt_prev, orig_dev); } else { drop: if (!deliver_exact) @@ -4916,10 +5023,16 @@ struct packet_type *pt_prev = NULL; int ret; +#ifdef CONFIG_NETRXTHREAD + (void)orig_dev; + ret = __netif_receive_skb_core(&skb, pfmemalloc, &pt_prev); +#else ret = __netif_receive_skb_core(&skb, pfmemalloc, &pt_prev); if (pt_prev) ret = INDIRECT_CALL_INET(pt_prev->func, ipv6_rcv, ip_rcv, skb, skb->dev, pt_prev, orig_dev); +#endif + return ret; } @@ -10236,6 +10349,24 @@ open_softirq(NET_TX_SOFTIRQ, net_tx_action); open_softirq(NET_RX_SOFTIRQ, net_rx_action); +#ifdef CONFIG_NETRXTHREAD + for (i = 0; i < CONFIG_NETRXTHREAD_RX_QUEUE; i++) { + struct krxd *krxd = &gkrxd[i]; + struct task_struct *task; + + skb_queue_head_init(&krxd->pkt_queue); + init_waitqueue_head(&krxd->wq); + task = kthread_create(krxd_action, krxd, "krxthread_%u", i); + if (IS_ERR(task)) { + printk(KERN_ERR "unable to create krxd\n"); + return -ENOMEM; + } + krxd->task = task; + wake_up_process(task); + } +#endif + + rc = cpuhp_setup_state_nocalls(CPUHP_NET_DEV_DEAD, "net/dev:dead", NULL, dev_cpu_dead); WARN_ON(rc < 0); diff -ruw linux-5.4.60/net/core/ethtool.c linux-5.4.60-fbx/net/core/ethtool.c --- linux-5.4.60/net/core/ethtool.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/core/ethtool.c 2021-03-04 13:21:01.400839050 +0100 @@ -126,6 +126,7 @@ [ETHTOOL_RX_COPYBREAK] = "rx-copybreak", [ETHTOOL_TX_COPYBREAK] = "tx-copybreak", [ETHTOOL_PFC_PREVENTION_TOUT] = "pfc-prevention-tout", + [ETHTOOL_MAC_MODE] = "mac-mode", }; static const char @@ -2274,6 +2275,11 @@ tuna->type_id != ETHTOOL_TUNABLE_U16) return -EINVAL; break; + case ETHTOOL_MAC_MODE: + if (tuna->len != sizeof(u32) || + tuna->type_id != ETHTOOL_TUNABLE_U32) + return -EINVAL; + break; default: return -EINVAL; } @@ -2556,6 +2562,87 @@ return dev->ethtool_ops->set_fecparam(dev, &fecparam); } +static int ethtool_get_eponparam(struct net_device *dev, void __user *useraddr) +{ + struct ethtool_epon_param eponparam = { .cmd = ETHTOOL_GEPON_PARAM }; + int rc; + + if (!dev->ethtool_ops->get_epon_param) + return -EOPNOTSUPP; + + rc = dev->ethtool_ops->get_epon_param(dev, &eponparam); + if (rc) + return rc; + + if (copy_to_user(useraddr, &eponparam, sizeof(eponparam))) + return -EFAULT; + return 0; +} + +static int ethtool_set_eponparam(struct net_device *dev, void __user *useraddr) +{ + struct ethtool_epon_param eponparam; + + if (!dev->ethtool_ops->set_epon_param) + return -EOPNOTSUPP; + + if (copy_from_user(&eponparam, useraddr, sizeof(eponparam))) + return -EFAULT; + + return dev->ethtool_ops->set_epon_param(dev, &eponparam); +} + +static int ethtool_get_sfp_state(struct net_device *dev, void __user *useraddr) +{ + struct ethtool_sfp_state sfp_state; + int rc; + + if (!dev->sfp_bus) { + printk("no SFP bus ya twat.\n"); + return -ENODEV; + } + + rc = sfp_get_sfp_state(dev->sfp_bus, &sfp_state); + if (rc) + return rc; + + if (copy_to_user(useraddr, &sfp_state, sizeof (sfp_state))) + return -EFAULT; + return 0; +} + +static int ethtool_get_shaper_params(struct net_device *dev, void __user *uaddr) +{ + struct ethtool_shaper_params sp; + int rc; + + if (!dev->ethtool_ops->get_shaper_param) + return -EOPNOTSUPP; + + memset(&sp, 0, sizeof (sp)); + rc = dev->ethtool_ops->get_shaper_param(dev, &sp); + if (rc) + return rc; + + if (copy_to_user(uaddr, &sp, sizeof (sp))) + return -EFAULT; + + return 0; +} + +static int ethtool_set_shaper_params(struct net_device *dev, void __user *uaddr) +{ + struct ethtool_shaper_params sp; + + if (!dev->ethtool_ops->set_shaper_param) + return -EOPNOTSUPP; + + if (copy_from_user(&sp, uaddr, sizeof (sp))) + return -EFAULT; + + return dev->ethtool_ops->set_shaper_param(dev, &sp); +} + /* The main entry point in this file. Called from net/core/dev_ioctl.c */ int dev_ethtool(struct net *net, struct ifreq *ifr) @@ -2831,6 +2918,27 @@ case ETHTOOL_SFECPARAM: rc = ethtool_set_fecparam(dev, useraddr); break; + case ETHTOOL_GEPON_PARAM: + rc = ethtool_get_eponparam(dev, useraddr); + break; + case ETHTOOL_SEPON_KEYS: + case ETHTOOL_SEPON_ENCRYPT: + case ETHTOOL_SEPON_RESTART: + case ETHTOOL_SEPON_BURST: + case ETHTOOL_SEPON_ADD_MCLLID: + case ETHTOOL_SEPON_DEL_MCLLID: + case ETHTOOL_SEPON_CLR_MCLLID: + rc = ethtool_set_eponparam(dev, useraddr); + break; + case ETHTOOL_GSFP_STATE: + rc = ethtool_get_sfp_state(dev, useraddr); + break; + case ETHTOOL_SSHAPER_PARAMS: + rc = ethtool_set_shaper_params(dev, useraddr); + break; + case ETHTOOL_GSHAPER_PARAMS: + rc = ethtool_get_shaper_params(dev, useraddr); + break; default: rc = -EOPNOTSUPP; } diff -ruw linux-5.4.60/net/core/net-procfs.c linux-5.4.60-fbx/net/core/net-procfs.c --- linux-5.4.60/net/core/net-procfs.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/core/net-procfs.c 2021-03-04 13:21:01.400839050 +0100 @@ -272,6 +272,84 @@ .show = ptype_seq_show, }; +#ifdef CONFIG_NETRXTHREAD +/* + * This is invoked by the /proc filesystem handler to display a device + * in detail. + */ +static void *krxthread_seq_start(struct seq_file *seq, loff_t *pos) +{ + int *queue; + + if (*pos > CONFIG_NETRXTHREAD_RX_QUEUE) + return NULL; + + queue = kmalloc(sizeof(*queue), GFP_KERNEL); + if (!queue) + return NULL; + *queue = ((int)*pos - 1); + + return queue; +} + +static void *krxthread_seq_next(struct seq_file *seq, void *v, loff_t *pos) +{ + int *queue = v; + + if (*pos == CONFIG_NETRXTHREAD_RX_QUEUE) + return NULL; + + ++*queue; + *pos = *queue + 1; + return queue; +} + +static void krxthread_seq_stop(struct seq_file *seq, void *v) +{ + kfree(v); +} + +static void krxthread_seq_printf_stats(struct seq_file *seq, int queue) +{ + seq_printf(seq, "%8u %12u %12u\n", + queue, + gkrxd[queue].stats_pkts, + gkrxd[queue].stats_dropped); +} + +static int krxthread_seq_show(struct seq_file *seq, void *v) +{ + int *queue = v; + + if (*queue == -1) + seq_printf(seq, "%8s %12s %12s\n", + "queue", "packets", "drops"); + else + krxthread_seq_printf_stats(seq, *queue); + return 0; +} + +static const struct seq_operations krxthread_seq_ops = { + .start = krxthread_seq_start, + .next = krxthread_seq_next, + .stop = krxthread_seq_stop, + .show = krxthread_seq_show, +}; + +static int krxthread_seq_open(struct inode *inode, struct file *file) +{ + return seq_open(file, &krxthread_seq_ops); +} + +static const struct file_operations krxthread_seq_fops = { + .owner = THIS_MODULE, + .open = krxthread_seq_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; +#endif /* KRXTHREAD */ + static int __net_init dev_proc_net_init(struct net *net) { int rc = -ENOMEM; @@ -288,6 +366,11 @@ if (wext_proc_init(net)) goto out_ptype; +#ifdef CONFIG_NETRXTHREAD + if (!proc_create("krxthread", S_IRUGO, net->proc_net, + &krxthread_seq_fops)) + goto out_ptype; +#endif rc = 0; out: return rc; diff -ruw linux-5.4.60/net/core/net-sysfs.c linux-5.4.60-fbx/net/core/net-sysfs.c --- linux-5.4.60/net/core/net-sysfs.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/core/net-sysfs.c 2021-03-04 13:21:01.400839050 +0100 @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -633,7 +634,24 @@ }; #if IS_ENABLED(CONFIG_WIRELESS_EXT) || IS_ENABLED(CONFIG_CFG80211) +static ssize_t show_nl80211_iftype(struct device *dev, + struct device_attribute *attr, char *buf) +{ + const struct net_device *netdev = to_net_dev(dev); + ssize_t ret = 0; + + if (!rtnl_trylock()) + return restart_syscall(); + if (netdev->ieee80211_ptr) + ret = sprintf(buf, "%d\n", netdev->ieee80211_ptr->iftype); + rtnl_unlock(); + + return ret; +} +static DEVICE_ATTR(nl80211_iftype, S_IRUGO, show_nl80211_iftype, NULL); + static struct attribute *wireless_attrs[] = { + &dev_attr_nl80211_iftype.attr, NULL }; diff -ruw linux-5.4.60/net/core/skbuff.c linux-5.4.60-fbx/net/core/skbuff.c --- linux-5.4.60/net/core/skbuff.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/core/skbuff.c 2021-03-04 13:21:01.404172384 +0100 @@ -944,6 +944,10 @@ memcpy(&new->headers_start, &old->headers_start, offsetof(struct sk_buff, headers_end) - offsetof(struct sk_buff, headers_start)); + +#ifdef CONFIG_IP_FFN + new->ffn_state = FFN_STATE_INIT; +#endif CHECK_SKB_FIELD(protocol); CHECK_SKB_FIELD(csum); CHECK_SKB_FIELD(hash); @@ -5128,11 +5132,12 @@ skb->offload_l3_fwd_mark = 0; #endif + skb->mark = 0; + if (!xnet) return; ipvs_reset(skb); - skb->mark = 0; skb->tstamp = 0; } EXPORT_SYMBOL_GPL(skb_scrub_packet); diff -ruw linux-5.4.60/net/core/sock.c linux-5.4.60-fbx/net/core/sock.c --- linux-5.4.60/net/core/sock.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/core/sock.c 2021-03-04 13:21:01.404172384 +0100 @@ -1177,6 +1177,10 @@ ret = sock_setbindtodevice_locked(sk, val); break; + case SO_UDP_DUP_UNICAST: + sock_valbool_flag(sk, SOCK_UDP_DUP_UNICAST, valbool); + break; + default: ret = -ENOPROTOOPT; break; @@ -1510,6 +1514,10 @@ v.val64 = sock_gen_cookie(sk); break; + case SO_UDP_DUP_UNICAST: + v.val = sock_flag(sk, SOCK_UDP_DUP_UNICAST); + break; + case SO_ZEROCOPY: v.val = sock_flag(sk, SOCK_ZEROCOPY); break; diff -ruw linux-5.4.60/net/dsa/dsa2.c linux-5.4.60-fbx/net/dsa/dsa2.c --- linux-5.4.60/net/dsa/dsa2.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/dsa/dsa2.c 2021-03-04 13:21:01.410839051 +0100 @@ -194,12 +194,27 @@ return complete; } -static struct dsa_port *dsa_tree_find_first_cpu(struct dsa_switch_tree *dst) +static struct dsa_port *dsa_tree_find_default_cpu(struct dsa_switch_tree *dst) { struct dsa_switch *ds; struct dsa_port *dp; int device, port; + /* first look for port marked as default cpu port */ + for (device = 0; device < DSA_MAX_SWITCHES; device++) { + ds = dst->ds[device]; + if (!ds) + continue; + + for (port = 0; port < ds->num_ports; port++) { + dp = &ds->ports[port]; + + if (dp->is_def_cpu_port) + return dp; + } + } + + /* if not found, take first cpu port, if any */ for (device = 0; device < DSA_MAX_SWITCHES; device++) { ds = dst->ds[device]; if (!ds) @@ -216,40 +231,72 @@ return NULL; } -static int dsa_tree_setup_default_cpu(struct dsa_switch_tree *dst) +static struct dsa_port *dsa_port_get_cpu_port(struct dsa_switch *ds, + struct dsa_port *dp) { - struct dsa_switch *ds; + struct device_node *cpu_dn; + int port; + + cpu_dn = of_parse_phandle(dp->dn, "dsa,cpu-port", 0); + if (!cpu_dn) + return ERR_PTR(-ENOENT); + + for (port = 0; port < ds->num_ports; port++) { struct dsa_port *dp; + + dp = &ds->ports[port]; + if (!dsa_port_is_cpu(dp)) + continue; + + if (dp->dn == cpu_dn) + return dp; + } + + dev_err(ds->dev, "failed to find cpu port referenced by phandle"); + return ERR_PTR(-EINVAL); +} + +static int dsa_tree_setup_cpu_port(struct dsa_switch_tree *dst) +{ + struct dsa_switch *ds; + struct dsa_port *dp, *def_cpu; int device, port; - /* DSA currently only supports a single CPU port */ - dst->cpu_dp = dsa_tree_find_first_cpu(dst); - if (!dst->cpu_dp) { + def_cpu = dsa_tree_find_default_cpu(dst); + if (!def_cpu) { pr_warn("Tree has no master device\n"); return -EINVAL; } - /* Assign the default CPU port to all ports of the fabric */ for (device = 0; device < DSA_MAX_SWITCHES; device++) { ds = dst->ds[device]; if (!ds) continue; for (port = 0; port < ds->num_ports; port++) { + struct dsa_port *cpu_dp; + dp = &ds->ports[port]; - if (dsa_port_is_user(dp) || dsa_port_is_dsa(dp)) - dp->cpu_dp = dst->cpu_dp; - } + if (!dsa_port_is_user(dp) && !dsa_port_is_dsa(dp)) + continue; + + /* if port has dedicated cpu port, use it instead */ + cpu_dp = dsa_port_get_cpu_port(ds, dp); + if (!IS_ERR(cpu_dp)) { + dp->cpu_dp = cpu_dp; + continue; } - return 0; + if (PTR_ERR(cpu_dp) == -EINVAL) + return -EINVAL; + + /* assigned default port */ + dp->cpu_dp = def_cpu; + } } -static void dsa_tree_teardown_default_cpu(struct dsa_switch_tree *dst) -{ - /* DSA currently only supports a single CPU port */ - dst->cpu_dp = NULL; + return 0; } static int dsa_port_setup(struct dsa_port *dp) @@ -506,21 +553,52 @@ } } -static int dsa_tree_setup_master(struct dsa_switch_tree *dst) +static int dsa_tree_setup_masters(struct dsa_switch_tree *dst) { - struct dsa_port *cpu_dp = dst->cpu_dp; - struct net_device *master = cpu_dp->master; + struct dsa_switch *ds; + struct dsa_port *dp; + int device, port; + int err = 0; + + for (device = 0; device < DSA_MAX_SWITCHES; device++) { + ds = dst->ds[device]; + if (!ds) + continue; + + for (port = 0; port < ds->num_ports; port++) { + dp = &ds->ports[port]; - /* DSA currently supports a single pair of CPU port and master device */ - return dsa_master_setup(master, cpu_dp); + if (dp->type == DSA_PORT_TYPE_CPU) { + struct net_device *master = dp->master; + err = dsa_master_setup(master, dp); + if (err) + return err; + } + } + } + return 0; } -static void dsa_tree_teardown_master(struct dsa_switch_tree *dst) +static void dsa_tree_teardown_masters(struct dsa_switch_tree *dst) { - struct dsa_port *cpu_dp = dst->cpu_dp; - struct net_device *master = cpu_dp->master; + struct dsa_switch *ds; + struct dsa_port *dp; + int device, port; + + for (device = 0; device < DSA_MAX_SWITCHES; device++) { + ds = dst->ds[device]; + if (!ds) + continue; - return dsa_master_teardown(master); + for (port = 0; port < ds->num_ports; port++) { + dp = &ds->ports[port]; + + if (dp->type == DSA_PORT_TYPE_CPU) { + struct net_device *master = dp->master; + dsa_master_teardown(master); + } + } + } } static int dsa_tree_setup(struct dsa_switch_tree *dst) @@ -538,15 +616,15 @@ if (!complete) return 0; - err = dsa_tree_setup_default_cpu(dst); + err = dsa_tree_setup_cpu_port(dst); if (err) return err; err = dsa_tree_setup_switches(dst); if (err) - goto teardown_default_cpu; + return err; - err = dsa_tree_setup_master(dst); + err = dsa_tree_setup_masters(dst); if (err) goto teardown_switches; @@ -558,8 +636,6 @@ teardown_switches: dsa_tree_teardown_switches(dst); -teardown_default_cpu: - dsa_tree_teardown_default_cpu(dst); return err; } @@ -569,12 +645,10 @@ if (!dst->setup) return; - dsa_tree_teardown_master(dst); + dsa_tree_teardown_masters(dst); dsa_tree_teardown_switches(dst); - dsa_tree_teardown_default_cpu(dst); - pr_info("DSA: tree %d torn down\n", dst->index); dst->setup = false; @@ -650,6 +724,7 @@ dp->tag_ops = tag_ops; dp->master = master; dp->dst = dst; + dp->is_def_cpu_port = of_property_read_bool(dp->dn, "dsa,def-cpu-port"); return 0; } diff -ruw linux-5.4.60/net/dsa/dsa.c linux-5.4.60-fbx/net/dsa/dsa.c --- linux-5.4.60/net/dsa/dsa.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/dsa/dsa.c 2021-03-04 13:21:01.410839051 +0100 @@ -232,7 +232,7 @@ s = this_cpu_ptr(p->stats64); u64_stats_update_begin(&s->syncp); s->rx_packets++; - s->rx_bytes += skb->len; + s->rx_bytes += skb->len + ETH_HLEN; u64_stats_update_end(&s->syncp); if (dsa_skb_defer_rx_timestamp(p, skb)) diff -ruw linux-5.4.60/net/dsa/dsa_priv.h linux-5.4.60-fbx/net/dsa/dsa_priv.h --- linux-5.4.60/net/dsa/dsa_priv.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/dsa/dsa_priv.h 2021-03-04 13:21:01.410839051 +0100 @@ -193,6 +193,13 @@ void *dsa_defer_xmit(struct sk_buff *skb, struct net_device *dev); +extern const struct net_device_ops dsa_slave_netdev_ops; + +static inline bool dsa_is_slave(const struct net_device *dev) +{ + return (dev->netdev_ops == &dsa_slave_netdev_ops); +} + static inline struct dsa_port *dsa_slave_to_port(const struct net_device *dev) { struct dsa_slave_priv *p = netdev_priv(dev); diff -ruw linux-5.4.60/net/dsa/Kconfig linux-5.4.60-fbx/net/dsa/Kconfig --- linux-5.4.60/net/dsa/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/dsa/Kconfig 2021-03-04 13:21:01.410839051 +0100 @@ -49,6 +49,10 @@ Broadcom switches which places the tag before the Ethernet header (prepended). +config NET_DSA_TAG_BRCM_FBX + tristate "Tag driver for Broadcom switches using in-frame headers" + select NET_DSA_TAG_BRCM_COMMON + config NET_DSA_TAG_GSWIP tristate "Tag driver for Lantiq / Intel GSWIP switches" help diff -ruw linux-5.4.60/net/dsa/slave.c linux-5.4.60-fbx/net/dsa/slave.c --- linux-5.4.60/net/dsa/slave.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/dsa/slave.c 2021-03-04 13:21:01.410839051 +0100 @@ -209,7 +209,7 @@ ndm->ndm_family = AF_BRIDGE; ndm->ndm_pad1 = 0; ndm->ndm_pad2 = 0; - ndm->ndm_flags = NTF_SELF; + ndm->ndm_flags = NTF_SELF | NTF_OFFLOADED; ndm->ndm_type = 0; ndm->ndm_ifindex = dump->dev->ifindex; ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; @@ -1221,7 +1221,7 @@ return dp->ds->devlink ? &dp->devlink_port : NULL; } -static const struct net_device_ops dsa_slave_netdev_ops = { +const struct net_device_ops dsa_slave_netdev_ops = { .ndo_open = dsa_slave_open, .ndo_stop = dsa_slave_close, .ndo_start_xmit = dsa_slave_xmit, @@ -1379,6 +1379,7 @@ struct dsa_notifier_register_info rinfo = { .switch_number = dp->ds->index, .port_number = dp->index, + .cpu_port_number = dp->cpu_dp ? dp->cpu_dp->index : 0, .master = master, .info.dev = dev, }; diff -ruw linux-5.4.60/net/dsa/tag_brcm.c linux-5.4.60-fbx/net/dsa/tag_brcm.c --- linux-5.4.60/net/dsa/tag_brcm.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/dsa/tag_brcm.c 2021-03-04 13:21:01.410839051 +0100 @@ -146,7 +146,8 @@ } #endif -#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) || \ + IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_FBX) static struct sk_buff *brcm_tag_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -172,7 +173,9 @@ return nskb; } +#endif +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) static const struct dsa_device_ops brcm_netdev_ops = { .name = "brcm", .proto = DSA_TAG_PROTO_BRCM, @@ -213,6 +216,38 @@ MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM_PREPEND); #endif +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_FBX) +static struct sk_buff * +brcm_tag_rcv_fbx(struct sk_buff *skb, struct net_device *dev, + struct packet_type *pt) +{ + struct sk_buff *nskb = brcm_tag_rcv(skb, dev, pt); + + if (!nskb) + return nskb; + + /* if the packet was broadcast, the switch already did the + * flood to the other ports */ + if (nskb->pkt_type == PACKET_BROADCAST) + nskb->offload_fwd_mark = 1; + else + nskb->offload_fwd_mark = 0; + + return nskb; +} + +static const struct dsa_device_ops brcm_fbx_netdev_ops = { + .name = "brcm-fbx", + .proto = DSA_TAG_PROTO_BRCM_FBX, + .xmit = brcm_tag_xmit, + .rcv = brcm_tag_rcv_fbx, + .overhead = BRCM_TAG_LEN, +}; + +DSA_TAG_DRIVER(brcm_fbx_netdev_ops); +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_BRCM_FBX); +#endif + static struct dsa_tag_driver *dsa_tag_driver_array[] = { #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM) &DSA_TAG_DRIVER_NAME(brcm_netdev_ops), @@ -220,6 +255,9 @@ #if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_PREPEND) &DSA_TAG_DRIVER_NAME(brcm_prepend_netdev_ops), #endif +#if IS_ENABLED(CONFIG_NET_DSA_TAG_BRCM_FBX) + &DSA_TAG_DRIVER_NAME(brcm_fbx_netdev_ops), +#endif }; module_dsa_tag_drivers(dsa_tag_driver_array); diff -ruw linux-5.4.60/net/ipv4/ipconfig.c linux-5.4.60-fbx/net/ipv4/ipconfig.c --- linux-5.4.60/net/ipv4/ipconfig.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/ipconfig.c 2021-03-04 13:21:01.424172385 +0100 @@ -198,16 +198,62 @@ static struct ic_device *ic_first_dev __initdata; /* List of open device */ static struct ic_device *ic_dev __initdata; /* Selected device */ -static bool __init ic_is_init_dev(struct net_device *dev) +static bool __init ic_is_init_dev(struct net_device *dev, bool partial) { + char *p = NULL; + bool ret; + if (dev->flags & IFF_LOOPBACK) return false; - return user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : + + if (partial) { + p = strchr(user_dev_name, '.'); + if (p) + *p = 0; + } + + ret = false; + if (user_dev_name[0] ? !strcmp(dev->name, user_dev_name) : (!(dev->flags & IFF_LOOPBACK) && (dev->flags & (IFF_POINTOPOINT|IFF_BROADCAST)) && - strncmp(dev->name, "dummy", 5)); + strncmp(dev->name, "dummy", 5))) + ret = true; + if (p) + *p = '.'; + return ret; } +#ifdef CONFIG_VLAN_8021Q +int register_vlan_device(struct net_device *real_dev, u16 vlan_id); + +static void __init prepare_vlan(void) +{ + unsigned short oflags; + struct net_device *dev; + char *p; + u16 vid; + + if (!strchr(user_dev_name, '.')) + return; + + p = strchr(user_dev_name, '.'); + *p = 0; + vid = simple_strtoul(p + 1, NULL, 10); + dev = __dev_get_by_name(&init_net, user_dev_name); + if (!dev) + goto fail; + + oflags = dev->flags; + if (dev_change_flags(dev, oflags | IFF_UP, NULL) < 0) + goto fail; + + register_vlan_device(dev, vid); + +fail: + *p = '.'; +} +#endif + static int __init ic_open_devs(void) { struct ic_device *d, **last; @@ -226,8 +272,13 @@ pr_err("IP-Config: Failed to open %s\n", dev->name); } +#ifdef CONFIG_VLAN_8021Q + /* register vlan device if needed */ + prepare_vlan(); +#endif + for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, false)) { int able = 0; if (dev->mtu >= 364) able |= IC_BOOTP; @@ -276,10 +327,12 @@ int wait, elapsed; for_each_netdev(&init_net, dev) - if (ic_is_init_dev(dev) && netif_carrier_ok(dev)) + if (ic_is_init_dev(dev, false) && netif_carrier_ok(dev)) goto have_carrier; + rtnl_unlock(); msleep(1); + rtnl_lock(); if (time_before(jiffies, next_msg)) continue; @@ -705,8 +758,10 @@ e += len; } if (*vendor_class_identifier) { +#ifdef IPCONFIG_DEBUG pr_info("DHCP: sending class identifier \"%s\"\n", vendor_class_identifier); +#endif *e++ = 60; /* Class-identifier */ len = strlen(vendor_class_identifier); *e++ = len; @@ -1414,7 +1469,7 @@ rtnl_lock(); for_each_netdev(&init_net, dev) { - if (ic_is_init_dev(dev)) { + if (ic_is_init_dev(dev, true)) { found = 1; break; } diff -ruw linux-5.4.60/net/ipv4/ip_input.c linux-5.4.60-fbx/net/ipv4/ip_input.c --- linux-5.4.60/net/ipv4/ip_input.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/ip_input.c 2021-03-04 13:21:01.420839051 +0100 @@ -223,8 +223,12 @@ } } -static int ip_local_deliver_finish(struct net *net, struct sock *sk, struct sk_buff *skb) +int ip_local_deliver_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ip_ffn_add(skb, IP_FFN_LOCAL_IN); +#endif __skb_pull(skb, skb_network_header_len(skb)); rcu_read_lock(); @@ -520,6 +524,11 @@ if (skb == NULL) return NET_RX_DROP; +#ifdef CONFIG_IP_FFN + if (!ip_ffn_process(skb)) + return NET_RX_SUCCESS; +#endif + return NF_HOOK(NFPROTO_IPV4, NF_INET_PRE_ROUTING, net, NULL, skb, dev, NULL, ip_rcv_finish); diff -ruw linux-5.4.60/net/ipv4/ip_output.c linux-5.4.60-fbx/net/ipv4/ip_output.c --- linux-5.4.60/net/ipv4/ip_output.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/ip_output.c 2021-03-04 13:21:01.420839051 +0100 @@ -218,6 +218,11 @@ return res; } +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ip_ffn_add(skb, IP_FFN_FINISH_OUT); +#endif + rcu_read_lock_bh(); neigh = ip_neigh_for_gw(rt, skb, &is_v6gw); if (!IS_ERR(neigh)) { @@ -429,6 +434,11 @@ skb->dev = dev; skb->protocol = htons(ETH_P_IP); +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FAST_FORWARDED) + return ip_finish_output(net, sk, skb); +#endif + return NF_HOOK_COND(NFPROTO_IPV4, NF_INET_POST_ROUTING, net, sk, skb, NULL, dev, ip_finish_output, @@ -1733,4 +1743,7 @@ #if defined(CONFIG_IP_MULTICAST) igmp_mc_init(); #endif +#ifdef CONFIG_IP_FFN + ip_ffn_init(); +#endif } diff -ruw linux-5.4.60/net/ipv4/ip_tunnel_core.c linux-5.4.60-fbx/net/ipv4/ip_tunnel_core.c --- linux-5.4.60/net/ipv4/ip_tunnel_core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/ip_tunnel_core.c 2021-03-04 13:21:01.420839051 +0100 @@ -34,6 +34,9 @@ #include #include #include +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) +#include +#endif const struct ip_tunnel_encap_ops __rcu * iptun_encaps[MAX_IPTUN_ENCAP_OPS] __read_mostly; @@ -56,6 +59,11 @@ skb_scrub_packet(skb, xnet); skb_clear_hash_if_not_l4(skb); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + if (proto == IPPROTO_IPV6) + nf_ct_set(skb, NULL, IP_CT_UNTRACKED); +#endif + skb_dst_set(skb, &rt->dst); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); diff -ruw linux-5.4.60/net/ipv4/Makefile linux-5.4.60-fbx/net/ipv4/Makefile --- linux-5.4.60/net/ipv4/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/Makefile 2021-03-04 13:21:01.417505717 +0100 @@ -20,6 +20,8 @@ obj-$(CONFIG_NET_IP_TUNNEL) += ip_tunnel.o obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o + +obj-$(CONFIG_IP_FFN) += ip_ffn.o obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o obj-$(CONFIG_IP_MROUTE) += ipmr.o diff -ruw linux-5.4.60/net/ipv4/netfilter/ip_tables.c linux-5.4.60-fbx/net/ipv4/netfilter/ip_tables.c --- linux-5.4.60/net/ipv4/netfilter/ip_tables.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/netfilter/ip_tables.c 2021-03-04 13:21:01.424172385 +0100 @@ -1102,6 +1102,8 @@ return ret; } +extern void fbxbr_flush_cache(void); + static int do_replace(struct net *net, const void __user *user, unsigned int len) { @@ -1141,6 +1143,15 @@ tmp.num_counters, tmp.counters); if (ret) goto free_newinfo_untrans; + +#ifdef CONFIG_IP_FFN + ip_ffn_flush_all(); +#endif + +#ifdef CONFIG_FBXBRIDGE + fbxbr_flush_cache(); +#endif + return 0; free_newinfo_untrans: diff -ruw linux-5.4.60/net/ipv4/netfilter/Kconfig linux-5.4.60-fbx/net/ipv4/netfilter/Kconfig --- linux-5.4.60/net/ipv4/netfilter/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/netfilter/Kconfig 2021-03-04 13:21:01.424172385 +0100 @@ -6,6 +6,13 @@ menu "IP: Netfilter Configuration" depends on INET && NETFILTER +config IP_FFN + bool "IP: Fast forwarding and NAT" + +config IP_FFN_PROCFS + bool "IP: Fast forwarding and NAT /proc/net entries" + depends on IP_FFN + config NF_DEFRAG_IPV4 tristate default n diff -ruw linux-5.4.60/net/ipv4/tcp.c linux-5.4.60-fbx/net/ipv4/tcp.c --- linux-5.4.60/net/ipv4/tcp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/tcp.c 2021-03-04 13:21:01.427505718 +0100 @@ -2924,6 +2924,13 @@ err = -EINVAL; break; + case TCP_LINEAR_RTO: + if (val < 0 || val > 1) + err = -EINVAL; + else + tp->linear_rto = val; + break; + case TCP_REPAIR: if (!tcp_can_repair_sock(sk)) err = -EPERM; @@ -3549,6 +3556,9 @@ case TCP_THIN_DUPACK: val = 0; break; + case TCP_LINEAR_RTO: + val = tp->linear_rto; + break; case TCP_REPAIR: val = tp->repair; diff -ruw linux-5.4.60/net/ipv4/tcp_timer.c linux-5.4.60-fbx/net/ipv4/tcp_timer.c --- linux-5.4.60/net/ipv4/tcp_timer.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/tcp_timer.c 2021-03-04 13:21:01.430839052 +0100 @@ -556,6 +556,10 @@ icsk->icsk_retransmits <= TCP_THIN_LINEAR_RETRIES) { icsk->icsk_backoff = 0; icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); + + } else if (sk->sk_state == TCP_ESTABLISHED && tp->linear_rto) { + icsk->icsk_backoff = 0; + icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); } else { /* Use normal (exponential) backoff */ icsk->icsk_rto = min(icsk->icsk_rto << 1, TCP_RTO_MAX); diff -ruw linux-5.4.60/net/ipv4/udp.c linux-5.4.60-fbx/net/ipv4/udp.c --- linux-5.4.60/net/ipv4/udp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv4/udp.c 2021-03-04 13:21:01.430839052 +0100 @@ -304,6 +304,49 @@ inet_sk(sk)->inet_num = snum; udp_sk(sk)->udp_port_hash = snum; udp_sk(sk)->udp_portaddr_hash ^= snum; + + /* resolve udp reuse conflict */ + if (sk->sk_reuse) { + struct sock *sk2; + bool found; + + found = false; + sk_for_each(sk2, &hslot->head) { + if (!net_eq(sock_net(sk2), net) || + sk2 == sk || + (udp_sk(sk2)->udp_port_hash != snum)) + continue; + + if (sk2->sk_bound_dev_if && + sk->sk_bound_dev_if && + sk2->sk_bound_dev_if != sk->sk_bound_dev_if) + continue; + + if (!inet_rcv_saddr_equal(sk, sk2, true)) + continue; + + found = true; + break; + } + + sk_for_each(sk2, &hslot->head) { + if (!net_eq(sock_net(sk2), net) || + sk2 == sk || + (udp_sk(sk2)->udp_port_hash != snum)) + continue; + + if (sk2->sk_bound_dev_if && + sk->sk_bound_dev_if && + sk2->sk_bound_dev_if != sk->sk_bound_dev_if) + continue; + + if (!inet_rcv_saddr_equal(sk, sk2, true)) + continue; + + sk->sk_reuse_conflict = found; + } + } + if (sk_unhashed(sk)) { if (sk->sk_reuseport && udp_reuseport_add_sock(sk, hslot)) { @@ -2208,6 +2251,90 @@ return 0; } +/* + * Unicast goes to one listener and all sockets with dup flag + * + * Note: called only from the BH handler context. + * + * Note2: it is okay to use the udp_table.hash table only here + * and not udp_table.hash2 table as the sock is always hashed in + * both udp_table.hash and udp_table.hash2. This might impact + * performance if the sock hash bucket hosts more than 10 socks + * but has the benefit of keeping the code simplier. + * + * Note3: __udp_is_mcast_sock() does not have really anything to + * do with multicast, it used there to deliver the packet only to + * the sockets that are bound to the ip:port/interface the skbuff + * is targeted to. + */ +static int __udp4_lib_uc_conflict_deliver(struct net *net, struct sk_buff *skb, + struct udphdr *uh, + __be32 saddr, __be32 daddr, + struct udp_table *udptable, + int proto) +{ + struct sock *sk, *first = NULL; + unsigned short hnum = ntohs(uh->dest); + struct udp_hslot *hslot = udp_hashslot(udptable, net, hnum); + int dif = skb->dev->ifindex; + unsigned int offset = offsetof(typeof(*sk), sk_node); + struct hlist_node *node; + struct sk_buff *nskb; + int sdif = inet_sdif(skb); + bool found_non_dup; + + found_non_dup = false; + sk_for_each_entry_offset_rcu(sk, node, &hslot->head, offset) { + bool need_deliver; + + if (!__udp_is_mcast_sock(net, sk, uh->dest, daddr, + uh->source, saddr, dif, sdif, hnum)) + continue; + + if (sock_flag(sk, SOCK_UDP_DUP_UNICAST)) + need_deliver = true; + else { + if (!found_non_dup) + need_deliver = true; + else + need_deliver = false; + found_non_dup = true; + } + + if (!need_deliver) + continue; + + if (!first) { + first = sk; + continue; + } + nskb = skb_clone(skb, GFP_ATOMIC); + + if (unlikely(!nskb)) { + atomic_inc(&sk->sk_drops); + __UDP_INC_STATS(net, UDP_MIB_RCVBUFERRORS, + IS_UDPLITE(sk)); + __UDP_INC_STATS(net, UDP_MIB_INERRORS, + IS_UDPLITE(sk)); + continue; + } + + if (udp_queue_rcv_skb(sk, nskb) > 0) + consume_skb(nskb); + } + + if (first) { + if (udp_queue_rcv_skb(first, skb) > 0) + consume_skb(skb); + } else { + kfree_skb(skb); + __UDP_INC_STATS(net, UDP_MIB_IGNOREDMULTI, + proto == IPPROTO_UDPLITE); + } + + return 0; +} + /* Initialize UDP checksum. If exited with zero value (success), * CHECKSUM_UNNECESSARY means, that no more checks are required. * Otherwise, csum completion requires checksumming packet body, @@ -2332,9 +2459,15 @@ saddr, daddr, udptable, proto); sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable); - if (sk) - return udp_unicast_rcv_skb(sk, skb, uh); + if (sk) { + if (sk->sk_reuse_conflict) + return __udp4_lib_uc_conflict_deliver(net, + skb, uh, + saddr, daddr, + udptable, proto); + return udp_unicast_rcv_skb(sk, skb, uh); + } if (!xfrm4_policy_check(NULL, XFRM_POLICY_IN, skb)) goto drop; nf_reset_ct(skb); diff -ruw linux-5.4.60/net/ipv6/addrconf.c linux-5.4.60-fbx/net/ipv6/addrconf.c --- linux-5.4.60/net/ipv6/addrconf.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/addrconf.c 2021-03-04 13:21:01.434172386 +0100 @@ -2281,12 +2281,27 @@ return 0; } +static int addrconf_ifid_ppp(u8 *eui, struct net_device *dev) +{ + if (is_zero_ether_addr(dev->perm_addr)) + return -1; + + memcpy(eui, dev->perm_addr, 3); + memcpy(eui + 5, dev->perm_addr + 3, 3); + eui[3] = 0xFF; + eui[4] = 0xFE; + eui[0] ^= 2; + return 0; +} + static int ipv6_generate_eui64(u8 *eui, struct net_device *dev) { switch (dev->type) { case ARPHRD_ETHER: case ARPHRD_FDDI: return addrconf_ifid_eui48(eui, dev); + case ARPHRD_PPP: + return addrconf_ifid_ppp(eui, dev); case ARPHRD_ARCNET: return addrconf_ifid_arcnet(eui, dev); case ARPHRD_INFINIBAND: @@ -3340,6 +3355,7 @@ if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_FDDI) && + (dev->type != ARPHRD_PPP) && (dev->type != ARPHRD_ARCNET) && (dev->type != ARPHRD_INFINIBAND) && (dev->type != ARPHRD_IEEE1394) && diff -ruw linux-5.4.60/net/ipv6/af_inet6.c linux-5.4.60-fbx/net/ipv6/af_inet6.c --- linux-5.4.60/net/ipv6/af_inet6.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/af_inet6.c 2021-03-04 13:21:01.434172386 +0100 @@ -1086,6 +1086,10 @@ if (err) goto udpv6_fail; +#ifdef CONFIG_IPV6_FFN + ipv6_ffn_init(); +#endif + err = udplitev6_init(); if (err) goto udplitev6_fail; diff -ruw linux-5.4.60/net/ipv6/ip6_input.c linux-5.4.60-fbx/net/ipv6/ip6_input.c --- linux-5.4.60/net/ipv6/ip6_input.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/ip6_input.c 2021-03-04 13:21:01.437505718 +0100 @@ -281,6 +281,12 @@ skb = ip6_rcv_core(skb, dev, net); if (skb == NULL) return NET_RX_DROP; + +#ifdef CONFIG_IPV6_FFN + if (!ipv6_ffn_process(skb)) + return NET_RX_SUCCESS; +#endif + return NF_HOOK(NFPROTO_IPV6, NF_INET_PRE_ROUTING, net, NULL, skb, dev, NULL, ip6_rcv_finish); @@ -444,8 +450,13 @@ kfree_skb(skb); } -static int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb) +int ip6_input_finish(struct net *net, struct sock *sk, struct sk_buff *skb) { +#ifdef CONFIG_IPV6_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ipv6_ffn_add(skb, IPV6_FFN_LOCAL_IN); +#endif + rcu_read_lock(); ip6_protocol_deliver_rcu(net, skb, 0, false); rcu_read_unlock(); diff -ruw linux-5.4.60/net/ipv6/ip6_output.c linux-5.4.60-fbx/net/ipv6/ip6_output.c --- linux-5.4.60/net/ipv6/ip6_output.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/ip6_output.c 2021-03-04 13:21:01.437505718 +0100 @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include @@ -106,6 +107,11 @@ return res; } +#ifdef CONFIG_IPV6_FFN + if (skb->ffn_state == FFN_STATE_FORWARDABLE) + ipv6_ffn_add(skb, IPV6_FFN_FINISH_OUT); +#endif + rcu_read_lock_bh(); nexthop = rt6_nexthop((struct rt6_info *)dst, &ipv6_hdr(skb)->daddr); neigh = __ipv6_neigh_lookup_noref(dst->dev, nexthop); @@ -172,6 +178,11 @@ return 0; } +#ifdef CONFIG_IP_FFN + if (skb->ffn_state == FFN_STATE_FAST_FORWARDED) + return ip6_finish_output(net, sk, skb); +#endif + return NF_HOOK_COND(NFPROTO_IPV6, NF_INET_POST_ROUTING, net, sk, skb, NULL, dev, ip6_finish_output, @@ -565,6 +576,8 @@ hdr->hop_limit--; + skb->priority = rt_tos2priority(ipv6_get_dsfield(hdr)); + return NF_HOOK(NFPROTO_IPV6, NF_INET_FORWARD, net, NULL, skb, skb->dev, dst->dev, ip6_forward_finish); diff -ruw linux-5.4.60/net/ipv6/ip6_tunnel.c linux-5.4.60-fbx/net/ipv6/ip6_tunnel.c --- linux-5.4.60/net/ipv6/ip6_tunnel.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/ip6_tunnel.c 2021-03-04 13:21:01.437505718 +0100 @@ -67,9 +67,9 @@ module_param(log_ecn_error, bool, 0644); MODULE_PARM_DESC(log_ecn_error, "Log packets received with corrupted ECN"); -static u32 HASH(const struct in6_addr *addr1, const struct in6_addr *addr2) +static u32 HASH(const struct in6_addr *addr) { - u32 hash = ipv6_addr_hash(addr1) ^ ipv6_addr_hash(addr2); + u32 hash = ipv6_addr_hash(addr); return hash_32(hash, IP6_TUNNEL_HASH_SIZE_SHIFT); } @@ -136,20 +136,29 @@ static struct ip6_tnl * ip6_tnl_lookup(struct net *net, const struct in6_addr *remote, const struct in6_addr *local) { - unsigned int hash = HASH(remote, local); + unsigned int hash = HASH(local); struct ip6_tnl *t; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); struct in6_addr any; + struct __ip6_tnl_fmr *fmr; for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { - if (ipv6_addr_equal(local, &t->parms.laddr) && - ipv6_addr_equal(remote, &t->parms.raddr) && - (t->dev->flags & IFF_UP)) + if (!ipv6_addr_equal(local, &t->parms.laddr) || + !(t->dev->flags & IFF_UP)) + continue; + + if (ipv6_addr_equal(remote, &t->parms.raddr)) + return t; + + for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { + if (ipv6_prefix_equal(remote, &fmr->ip6_prefix, + fmr->ip6_prefix_len)) return t; } + } memset(&any, 0, sizeof(any)); - hash = HASH(&any, local); + hash = HASH(local); for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { if (ipv6_addr_equal(local, &t->parms.laddr) && ipv6_addr_any(&t->parms.raddr) && @@ -157,7 +166,7 @@ return t; } - hash = HASH(remote, &any); + hash = HASH(&any); for_each_ip6_tunnel_rcu(ip6n->tnls_r_l[hash]) { if (ipv6_addr_equal(remote, &t->parms.raddr) && ipv6_addr_any(&t->parms.laddr) && @@ -197,7 +206,7 @@ if (!ipv6_addr_any(remote) || !ipv6_addr_any(local)) { prio = 1; - h = HASH(remote, local); + h = HASH(local); } return &ip6n->tnls[prio][h]; } @@ -378,6 +387,12 @@ struct net *net = t->net; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); + while (t->parms.fmrs) { + struct __ip6_tnl_fmr *next = t->parms.fmrs->next; + kfree(t->parms.fmrs); + t->parms.fmrs = next; + } + if (dev == ip6n->fb_tnl_dev) RCU_INIT_POINTER(ip6n->tnls_wc[0], NULL); else @@ -767,6 +782,107 @@ } EXPORT_SYMBOL_GPL(ip6_tnl_rcv_ctl); +/** + * ip4ip6_fmr_calc - calculate target / source IPv6-address based on FMR + * @dest: destination IPv6 address buffer + * @skb: received socket buffer + * @fmr: MAP FMR + * @xmit: Calculate for xmit or rcv + **/ +static void ip4ip6_fmr_calc(struct in6_addr *dest, + const struct iphdr *iph, const uint8_t *end, + const struct __ip6_tnl_fmr *fmr, bool xmit) +{ + int psidlen = fmr->ea_len - (32 - fmr->ip4_prefix_len); + u8 *portp = NULL; + bool use_dest_addr; + const struct iphdr *dsth = iph; + + if ((u8*)dsth >= end) + return; + + /* find significant IP header */ + if (iph->protocol == IPPROTO_ICMP) { + struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); + if (ih && ((u8*)&ih[1]) <= end && ( + ih->type == ICMP_DEST_UNREACH || + ih->type == ICMP_SOURCE_QUENCH || + ih->type == ICMP_TIME_EXCEEDED || + ih->type == ICMP_PARAMETERPROB || + ih->type == ICMP_REDIRECT)) + dsth = (const struct iphdr*)&ih[1]; + } + + /* in xmit-path use dest port by default and source port only if + this is an ICMP reply to something else; vice versa in rcv-path */ + use_dest_addr = (xmit && dsth == iph) || (!xmit && dsth != iph); + + /* get dst port */ + if (((u8*)&dsth[1]) <= end && ( + dsth->protocol == IPPROTO_UDP || + dsth->protocol == IPPROTO_TCP || + dsth->protocol == IPPROTO_SCTP || + dsth->protocol == IPPROTO_DCCP)) { + /* for UDP, TCP, SCTP and DCCP source and dest port + follow IPv4 header directly */ + portp = ((u8*)dsth) + dsth->ihl * 4; + + if (use_dest_addr) + portp += sizeof(u16); + } else if (iph->protocol == IPPROTO_ICMP) { + struct icmphdr *ih = (struct icmphdr*)(((u8*)dsth) + dsth->ihl * 4); + + /* use icmp identifier as port */ + if (((u8*)&ih) <= end && ( + (use_dest_addr && ( + ih->type == ICMP_ECHOREPLY || + ih->type == ICMP_TIMESTAMPREPLY || + ih->type == ICMP_INFO_REPLY || + ih->type == ICMP_ADDRESSREPLY)) || + (!use_dest_addr && ( + ih->type == ICMP_ECHO || + ih->type == ICMP_TIMESTAMP || + ih->type == ICMP_INFO_REQUEST || + ih->type == ICMP_ADDRESS) + ))) + portp = (u8*)&ih->un.echo.id; + } + + if ((portp && &portp[2] <= end) || psidlen == 0) { + int frombyte = fmr->ip6_prefix_len / 8; + int fromrem = fmr->ip6_prefix_len % 8; + int bytes = sizeof(struct in6_addr) - frombyte; + const u32 *addr = (use_dest_addr) ? &iph->daddr : &iph->saddr; + u64 eabits = ((u64)ntohl(*addr)) << (32 + fmr->ip4_prefix_len); + u64 t = 0; + + /* extract PSID from port and add it to eabits */ + u16 psidbits = 0; + if (psidlen > 0) { + psidbits = ((u16)portp[0]) << 8 | ((u16)portp[1]); + psidbits >>= 16 - psidlen - fmr->offset; + psidbits = (u16)(psidbits << (16 - psidlen)); + eabits |= ((u64)psidbits) << (48 - (fmr->ea_len - psidlen)); + } + + /* rewrite destination address */ + *dest = fmr->ip6_prefix; + memcpy(&dest->s6_addr[10], addr, sizeof(*addr)); + dest->s6_addr16[7] = htons(psidbits >> (16 - psidlen)); + + if (bytes > sizeof(u64)) + bytes = sizeof(u64); + + /* insert eabits */ + memcpy(&t, &dest->s6_addr[frombyte], bytes); + t = be64_to_cpu(t) & ~(((((u64)1) << fmr->ea_len) - 1) + << (64 - fmr->ea_len - fromrem)); + t = cpu_to_be64(t | (eabits >> fromrem)); + memcpy(&dest->s6_addr[frombyte], &t, bytes); + } +} + + static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb, const struct tnl_ptk_info *tpi, struct metadata_dst *tun_dst, @@ -819,6 +935,27 @@ skb_reset_network_header(skb); memset(skb->cb, 0, sizeof(struct inet6_skb_parm)); + if (tpi->proto == htons(ETH_P_IP) && + !ipv6_addr_equal(&ipv6h->saddr, &tunnel->parms.raddr)) { + /* Packet didn't come from BR, so lookup FMR */ + struct __ip6_tnl_fmr *fmr; + struct in6_addr expected = tunnel->parms.raddr; + for (fmr = tunnel->parms.fmrs; fmr; fmr = fmr->next) + if (ipv6_prefix_equal(&ipv6h->saddr, + &fmr->ip6_prefix, fmr->ip6_prefix_len)) + break; + + /* Check that IPv6 matches IPv4 source to prevent spoofing */ + if (fmr) + ip4ip6_fmr_calc(&expected, ip_hdr(skb), + skb_tail_pointer(skb), fmr, false); + + if (!ipv6_addr_equal(&ipv6h->saddr, &expected)) { + rcu_read_unlock(); + goto drop; + } + } + __skb_tunnel_rx(skb, tunnel->dev, tunnel->net); err = dscp_ecn_decapsulate(tunnel, ipv6h, skb); @@ -951,6 +1088,7 @@ opt->ops.opt_nflen = 8; } + /** * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own * @t: the outgoing tunnel device @@ -1232,6 +1370,7 @@ struct ip6_tnl *t = netdev_priv(dev); const struct iphdr *iph; int encap_limit = -1; + struct __ip6_tnl_fmr *fmr; struct flowi6 fl6; __u8 dsfield; __u32 mtu; @@ -1280,6 +1419,18 @@ fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL); dsfield = INET_ECN_encapsulate(dsfield, ipv4_get_dsfield(iph)); + /* try to find matching FMR */ + for (fmr = t->parms.fmrs; fmr; fmr = fmr->next) { + unsigned mshift = 32 - fmr->ip4_prefix_len; + if (ntohl(fmr->ip4_prefix.s_addr) >> mshift == + ntohl(ip_hdr(skb)->daddr) >> mshift) + break; + } + + /* change dstaddr according to FMR */ + if (fmr) + ip4ip6_fmr_calc(&fl6.daddr, ip_hdr(skb), skb_tail_pointer(skb), fmr, true); + if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6)) return -1; @@ -1497,6 +1648,14 @@ t->parms.link = p->link; t->parms.proto = p->proto; t->parms.fwmark = p->fwmark; + + while (t->parms.fmrs) { + struct __ip6_tnl_fmr *next = t->parms.fmrs->next; + kfree(t->parms.fmrs); + t->parms.fmrs = next; + } + t->parms.fmrs = p->fmrs; + dst_cache_reset(&t->dst_cache); ip6_tnl_link_config(t); return 0; @@ -1535,6 +1694,7 @@ p->flowinfo = u->flowinfo; p->link = u->link; p->proto = u->proto; + p->fmrs = NULL; memcpy(p->name, u->name, sizeof(u->name)); } @@ -1919,13 +2079,22 @@ return 0; } -static void ip6_tnl_netlink_parms(struct nlattr *data[], +static const struct nla_policy ip6_tnl_fmr_policy[IFLA_IPTUN_FMR_MAX + 1] = { + [IFLA_IPTUN_FMR_IP6_PREFIX] = { .len = sizeof(struct in6_addr) }, + [IFLA_IPTUN_FMR_IP4_PREFIX] = { .len = sizeof(struct in_addr) }, + [IFLA_IPTUN_FMR_IP6_PREFIX_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_IP4_PREFIX_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_EA_LEN] = { .type = NLA_U8 }, + [IFLA_IPTUN_FMR_OFFSET] = { .type = NLA_U8 } +}; + +static int ip6_tnl_netlink_parms(struct nlattr *data[], struct __ip6_tnl_parm *parms) { memset(parms, 0, sizeof(*parms)); if (!data) - return; + return 0; if (data[IFLA_IPTUN_LINK]) parms->link = nla_get_u32(data[IFLA_IPTUN_LINK]); @@ -1956,6 +2125,52 @@ if (data[IFLA_IPTUN_FWMARK]) parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]); + + if (data[IFLA_IPTUN_FMRS]) { + unsigned rem; + struct nlattr *fmr; + + nla_for_each_nested(fmr, data[IFLA_IPTUN_FMRS], rem) { + struct nlattr *fmrd[IFLA_IPTUN_FMR_MAX + 1], *c; + struct __ip6_tnl_fmr *nfmr; + int err; + + err = nla_parse_nested_deprecated(fmrd, IFLA_IPTUN_FMR_MAX, + fmr, ip6_tnl_fmr_policy, NULL); + if (err) + return err; + + if (!(nfmr = kzalloc(sizeof(*nfmr), GFP_KERNEL))) + return -ENOMEM; + + nfmr->offset = 6; + + if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX])) + nla_memcpy(&nfmr->ip6_prefix, fmrd[IFLA_IPTUN_FMR_IP6_PREFIX], + sizeof(nfmr->ip6_prefix)); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX])) + nla_memcpy(&nfmr->ip4_prefix, fmrd[IFLA_IPTUN_FMR_IP4_PREFIX], + sizeof(nfmr->ip4_prefix)); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP6_PREFIX_LEN])) + nfmr->ip6_prefix_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_IP4_PREFIX_LEN])) + nfmr->ip4_prefix_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_EA_LEN])) + nfmr->ea_len = nla_get_u8(c); + + if ((c = fmrd[IFLA_IPTUN_FMR_OFFSET])) + nfmr->offset = nla_get_u8(c); + + nfmr->next = parms->fmrs; + parms->fmrs = nfmr; + } + } + + return 0; } static bool ip6_tnl_netlink_encap_parms(struct nlattr *data[], @@ -2009,7 +2224,9 @@ return err; } - ip6_tnl_netlink_parms(data, &nt->parms); + err = ip6_tnl_netlink_parms(data, &nt->parms); + if (err) + return err; if (nt->parms.collect_md) { if (rtnl_dereference(ip6n->collect_md_tun)) @@ -2036,6 +2253,7 @@ struct net *net = t->net; struct ip6_tnl_net *ip6n = net_generic(net, ip6_tnl_net_id); struct ip_tunnel_encap ipencap; + int err; if (dev == ip6n->fb_tnl_dev) return -EINVAL; @@ -2046,7 +2264,10 @@ if (err < 0) return err; } - ip6_tnl_netlink_parms(data, &p); + err = ip6_tnl_netlink_parms(data, &p); + if (err) + return err; + if (p.collect_md) return -EINVAL; @@ -2071,6 +2292,12 @@ static size_t ip6_tnl_get_size(const struct net_device *dev) { + const struct ip6_tnl *t = netdev_priv(dev); + struct __ip6_tnl_fmr *c; + int fmrs = 0; + for (c = t->parms.fmrs; c; c = c->next) + ++fmrs; + return /* IFLA_IPTUN_LINK */ nla_total_size(4) + @@ -2100,6 +2327,24 @@ nla_total_size(0) + /* IFLA_IPTUN_FWMARK */ nla_total_size(4) + + /* IFLA_IPTUN_FMRS */ + nla_total_size(0) + + ( + /* nest */ + nla_total_size(0) + + /* IFLA_IPTUN_FMR_IP6_PREFIX */ + nla_total_size(sizeof(struct in6_addr)) + + /* IFLA_IPTUN_FMR_IP4_PREFIX */ + nla_total_size(sizeof(struct in_addr)) + + /* IFLA_IPTUN_FMR_EA_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_IP6_PREFIX_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_IP4_PREFIX_LEN */ + nla_total_size(1) + + /* IFLA_IPTUN_FMR_OFFSET */ + nla_total_size(1) + ) * fmrs + 0; } @@ -2107,6 +2352,9 @@ { struct ip6_tnl *tunnel = netdev_priv(dev); struct __ip6_tnl_parm *parm = &tunnel->parms; + struct __ip6_tnl_fmr *c; + int fmrcnt = 0; + struct nlattr *fmrs; if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) || nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) || @@ -2116,9 +2364,27 @@ nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) || nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) || nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) || - nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark)) + nla_put_u32(skb, IFLA_IPTUN_FWMARK, parm->fwmark) || + !(fmrs = nla_nest_start_noflag(skb, IFLA_IPTUN_FMRS))) goto nla_put_failure; + for (c = parm->fmrs; c; c = c->next) { + struct nlattr *fmr = nla_nest_start_noflag(skb, ++fmrcnt); + if (!fmr || + nla_put(skb, IFLA_IPTUN_FMR_IP6_PREFIX, + sizeof(c->ip6_prefix), &c->ip6_prefix) || + nla_put(skb, IFLA_IPTUN_FMR_IP4_PREFIX, + sizeof(c->ip4_prefix), &c->ip4_prefix) || + nla_put_u8(skb, IFLA_IPTUN_FMR_IP6_PREFIX_LEN, c->ip6_prefix_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_IP4_PREFIX_LEN, c->ip4_prefix_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_EA_LEN, c->ea_len) || + nla_put_u8(skb, IFLA_IPTUN_FMR_OFFSET, c->offset)) + goto nla_put_failure; + + nla_nest_end(skb, fmr); + } + nla_nest_end(skb, fmrs); + if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) || nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) || @@ -2158,6 +2424,7 @@ [IFLA_IPTUN_ENCAP_DPORT] = { .type = NLA_U16 }, [IFLA_IPTUN_COLLECT_METADATA] = { .type = NLA_FLAG }, [IFLA_IPTUN_FWMARK] = { .type = NLA_U32 }, + [IFLA_IPTUN_FMRS] = { .type = NLA_NESTED }, }; static struct rtnl_link_ops ip6_link_ops __read_mostly = { diff -ruw linux-5.4.60/net/ipv6/Makefile linux-5.4.60-fbx/net/ipv6/Makefile --- linux-5.4.60/net/ipv6/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/Makefile 2021-03-04 13:21:01.434172386 +0100 @@ -15,6 +15,7 @@ ipv6-offload := ip6_offload.o tcpv6_offload.o exthdrs_offload.o ipv6-$(CONFIG_SYSCTL) = sysctl_net_ipv6.o +ipv6-$(CONFIG_IPV6_FFN) += ip6_ffn.o ipv6-$(CONFIG_IPV6_MROUTE) += ip6mr.o ipv6-$(CONFIG_XFRM) += xfrm6_policy.o xfrm6_state.o xfrm6_input.o \ diff -ruw linux-5.4.60/net/ipv6/netfilter/ip6_tables.c linux-5.4.60-fbx/net/ipv6/netfilter/ip6_tables.c --- linux-5.4.60/net/ipv6/netfilter/ip6_tables.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/netfilter/ip6_tables.c 2021-03-04 13:21:01.440839052 +0100 @@ -1158,6 +1158,10 @@ tmp.num_counters, tmp.counters); if (ret) goto free_newinfo_untrans; + +#ifdef CONFIG_IPV6_FFN + ipv6_ffn_flush_all(); +#endif return 0; free_newinfo_untrans: diff -ruw linux-5.4.60/net/ipv6/netfilter/Kconfig linux-5.4.60-fbx/net/ipv6/netfilter/Kconfig --- linux-5.4.60/net/ipv6/netfilter/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/netfilter/Kconfig 2021-03-04 13:21:01.440839052 +0100 @@ -6,6 +6,13 @@ menu "IPv6: Netfilter Configuration" depends on INET && IPV6 && NETFILTER +config IPV6_FFN + bool "IPv6: Fast forwarding and NAT" + +config IPV6_FFN_PROCFS + bool "IPv6: Fast forwarding and NAT /proc/net entries" + depends on IPV6_FFN + config NF_SOCKET_IPV6 tristate "IPv6 socket lookup support" help diff -ruw linux-5.4.60/net/ipv6/udp.c linux-5.4.60-fbx/net/ipv6/udp.c --- linux-5.4.60/net/ipv6/udp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/ipv6/udp.c 2021-03-04 13:21:01.444172385 +0100 @@ -743,6 +743,82 @@ * Note: called only from the BH handler context, * so we don't need to lock the hashes. */ +static int __udp6_lib_uc_conflict_deliver(struct net *net, struct sk_buff *skb, + const struct in6_addr *saddr, const struct in6_addr *daddr, + struct udp_table *udptable, int proto) +{ + struct sock *sk, *first = NULL; + const struct udphdr *uh = udp_hdr(skb); + unsigned short hnum = ntohs(uh->dest); + struct udp_hslot *hslot = udp_hashslot(udptable, net, hnum); + unsigned int offset = offsetof(typeof(*sk), sk_node); + int dif = inet6_iif(skb); + int sdif = inet6_sdif(skb); + struct hlist_node *node; + struct sk_buff *nskb; + bool found_non_dup; + + found_non_dup = false; + sk_for_each_entry_offset_rcu(sk, node, &hslot->head, offset) { + bool need_deliver; + + if (!__udp_v6_is_mcast_sock(net, sk, uh->dest, daddr, + uh->source, saddr, dif, sdif, hnum)) + + continue; + + /* If zero checksum and no_check is not on for + * the socket then skip it. + */ + if (!uh->check && !udp_sk(sk)->no_check6_rx) + continue; + + if (sock_flag(sk, SOCK_UDP_DUP_UNICAST)) + need_deliver = true; + else { + if (!found_non_dup) + need_deliver = true; + else + need_deliver = false; + found_non_dup = true; + } + + if (!need_deliver) + continue; + + if (!first) { + first = sk; + continue; + } + nskb = skb_clone(skb, GFP_ATOMIC); + if (unlikely(!nskb)) { + atomic_inc(&sk->sk_drops); + __UDP6_INC_STATS(net, UDP_MIB_RCVBUFERRORS, + IS_UDPLITE(sk)); + __UDP6_INC_STATS(net, UDP_MIB_INERRORS, + IS_UDPLITE(sk)); + continue; + } + + if (udpv6_queue_rcv_skb(sk, nskb) > 0) + consume_skb(nskb); + } + + if (first) { + if (udpv6_queue_rcv_skb(first, skb) > 0) + consume_skb(skb); + } else { + kfree_skb(skb); + __UDP6_INC_STATS(net, UDP_MIB_IGNOREDMULTI, + proto == IPPROTO_UDPLITE); + } + return 0; +} + +/* + * Note: called only from the BH handler context, + * so we don't need to lock the hashes. + */ static int __udp6_lib_mcast_deliver(struct net *net, struct sk_buff *skb, const struct in6_addr *saddr, const struct in6_addr *daddr, struct udp_table *udptable, int proto) @@ -913,6 +989,12 @@ if (sk) { if (!uh->check && !udp_sk(sk)->no_check6_rx) goto report_csum_error; + + if (sk->sk_reuse_conflict) + return __udp6_lib_uc_conflict_deliver(net, skb, + saddr, daddr, + udptable, proto); + return udp6_unicast_rcv_skb(sk, skb, uh); } diff -ruw linux-5.4.60/net/Kconfig linux-5.4.60-fbx/net/Kconfig --- linux-5.4.60/net/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/Kconfig 2021-03-04 13:21:01.370839049 +0100 @@ -60,6 +60,20 @@ menu "Networking options" +config NETSKBPAD + int "Size reserved by dev_alloc_skb" + default 32 + +config NETRXTHREAD + bool "Do rx network processing in kernel thread" + depends on BROKEN_ON_SMP + +config NETRXTHREAD_RX_QUEUE + int "Number of rx queues" + default 1 + depends on NETRXTHREAD + +source "net/nmesh-mbh/Kconfig" source "net/packet/Kconfig" source "net/unix/Kconfig" source "net/tls/Kconfig" @@ -216,6 +230,8 @@ source "net/tipc/Kconfig" source "net/atm/Kconfig" source "net/l2tp/Kconfig" +source "net/fbxatm/Kconfig" +source "net/fbxbridge/Kconfig" source "net/802/Kconfig" source "net/bridge/Kconfig" source "net/dsa/Kconfig" diff -ruw linux-5.4.60/net/mac80211/agg-tx.c linux-5.4.60-fbx/net/mac80211/agg-tx.c --- linux-5.4.60/net/mac80211/agg-tx.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/agg-tx.c 2021-03-04 13:21:01.447505719 +0100 @@ -139,6 +139,14 @@ } EXPORT_SYMBOL(ieee80211_send_bar); +void ieee80211_send_bar_sta(struct ieee80211_sta *pubsta, + u16 tid, u16 ssn) +{ + struct sta_info *sta = container_of(pubsta, struct sta_info, sta); + ieee80211_send_bar(&sta->sdata->vif, pubsta->addr, tid, ssn); +} +EXPORT_SYMBOL(ieee80211_send_bar_sta); + void ieee80211_assign_tid_tx(struct sta_info *sta, int tid, struct tid_ampdu_tx *tid_tx) { @@ -290,7 +298,6 @@ ieee80211_assign_tid_tx(sta, tid, NULL); ieee80211_agg_splice_finish(sta->sdata, tid); - ieee80211_agg_start_txq(sta, tid, false); kfree_rcu(tid_tx, rcu_head); } @@ -860,6 +867,7 @@ { struct ieee80211_sub_if_data *sdata = sta->sdata; bool send_delba = false; + bool stop_txq = false; ht_dbg(sdata, "Stopping Tx BA session for %pM tid %d\n", sta->sta.addr, tid); @@ -877,9 +885,12 @@ send_delba = true; ieee80211_remove_tid_tx(sta, tid); + stop_txq = true; unlock_sta: spin_unlock_bh(&sta->lock); + if (stop_txq) + ieee80211_agg_start_txq(sta, tid, false); if (send_delba) ieee80211_send_delba(sdata, sta->sta.addr, tid, diff -ruw linux-5.4.60/net/mac80211/cfg.c linux-5.4.60-fbx/net/mac80211/cfg.c --- linux-5.4.60/net/mac80211/cfg.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/cfg.c 2021-03-04 13:21:01.450839053 +0100 @@ -1926,6 +1926,59 @@ return 0; } +static int ieee80211_update_mpp(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst, const u8 *next_hop) +{ + struct ieee80211_sub_if_data *sdata; + int ret = 0; + struct mesh_path *mppath; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + + rcu_read_lock(); + + mppath = mpp_path_lookup(sdata, dst); + if (!mppath) { + ret = mpp_path_add(sdata, dst, next_hop); + if (!ret) { + mppath = mpp_path_lookup(sdata, dst); + spin_lock_bh(&mppath->state_lock); + mppath->flags |= MESH_PATH_FIXED; + spin_unlock_bh(&mppath->state_lock); + } + } else { + spin_lock_bh(&mppath->state_lock); + if (!ether_addr_equal(mppath->mpp, next_hop)) + memcpy(mppath->mpp, next_hop, ETH_ALEN); + mppath->exp_time = jiffies; + mppath->flags |= MESH_PATH_FIXED; + spin_unlock_bh(&mppath->state_lock); + } + rcu_read_unlock(); + return ret; +} + +static int ieee80211_delete_mpp(struct wiphy *wiphy, struct net_device *dev, + const u8 *dst) +{ + struct ieee80211_sub_if_data *sdata; + int ret = 0; + struct mesh_path *mppath; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + rcu_read_lock(); + mppath = mpp_path_lookup(sdata, dst); + if (mppath) { + spin_lock_bh(&mppath->state_lock); + mppath->flags &= ~MESH_PATH_FIXED; + spin_unlock_bh(&mppath->state_lock); + } else { + ret = -ENOENT; + } + rcu_read_unlock(); + return ret; +} + static int ieee80211_get_mesh_config(struct wiphy *wiphy, struct net_device *dev, struct mesh_config *conf) @@ -2104,6 +2157,36 @@ return 0; } +static int ieee80211_update_mesh_vendor_node_metrics_ie(struct wiphy *wiphy, + struct net_device *dev, + const struct mesh_vendor_ie *vendor_ie) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_if_mesh *ifmsh; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + ifmsh = &sdata->u.mesh; + memcpy(ifmsh->node_vendor_ie, vendor_ie->ie, vendor_ie->ie_len); + ifmsh->node_vendor_ie_len = vendor_ie->ie_len; + ieee80211_mbss_info_change_notify(sdata, BSS_CHANGED_BEACON); + return 0; +} + +static int ieee80211_update_mesh_vendor_path_metrics_ie(struct wiphy *wiphy, + struct net_device *dev, + const struct mesh_vendor_ie *vendor_ie) +{ + struct ieee80211_sub_if_data *sdata; + struct ieee80211_if_mesh *ifmsh; + + sdata = IEEE80211_DEV_TO_SUB_IF(dev); + ifmsh = &sdata->u.mesh; + memcpy(ifmsh->mpm_vendor_ie, vendor_ie->ie, vendor_ie->ie_len); + ifmsh->mpm_vendor_ie_len = vendor_ie->ie_len; + ieee80211_mbss_info_change_notify(sdata, BSS_CHANGED_BEACON); + return 0; +} + static int ieee80211_join_mesh(struct wiphy *wiphy, struct net_device *dev, const struct mesh_config *conf, const struct mesh_setup *setup) @@ -2127,8 +2210,10 @@ err = ieee80211_vif_use_channel(sdata, &setup->chandef, IEEE80211_CHANCTX_SHARED); mutex_unlock(&sdata->local->mtx); - if (err) + if (err) { + kfree(ifmsh->ie); return err; + } return ieee80211_start_mesh(sdata); } @@ -3993,10 +4078,14 @@ .dump_mpath = ieee80211_dump_mpath, .get_mpp = ieee80211_get_mpp, .dump_mpp = ieee80211_dump_mpp, + .update_mpp = ieee80211_update_mpp, + .delete_mpp = ieee80211_delete_mpp, .update_mesh_config = ieee80211_update_mesh_config, .get_mesh_config = ieee80211_get_mesh_config, .join_mesh = ieee80211_join_mesh, .leave_mesh = ieee80211_leave_mesh, + .update_mesh_vendor_node_metrics_ie = ieee80211_update_mesh_vendor_node_metrics_ie, + .update_mesh_vendor_path_metrics_ie = ieee80211_update_mesh_vendor_path_metrics_ie, #endif .join_ocb = ieee80211_join_ocb, .leave_ocb = ieee80211_leave_ocb, diff -ruw linux-5.4.60/net/mac80211/debugfs.c linux-5.4.60-fbx/net/mac80211/debugfs.c --- linux-5.4.60/net/mac80211/debugfs.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/debugfs.c 2021-03-04 13:21:01.450839053 +0100 @@ -272,6 +272,7 @@ FLAG(SUPPORTS_MULTI_BSSID), FLAG(SUPPORTS_ONLY_HE_MULTI_BSSID), FLAG(AMPDU_KEYBORDER_SUPPORT), + FLAG(APVLAN_NEED_MCAST_TO_UCAST), #undef FLAG }; diff -ruw linux-5.4.60/net/mac80211/driver-ops.c linux-5.4.60-fbx/net/mac80211/driver-ops.c --- linux-5.4.60/net/mac80211/driver-ops.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/driver-ops.c 2021-03-04 13:21:01.450839053 +0100 @@ -49,6 +49,30 @@ local->started = false; } +int drv_get_powered(struct ieee80211_local *local, bool *up, bool *busy) +{ + int ret = -EOPNOTSUPP; + + might_sleep(); + + if (local->ops->get_powered) + ret = local->ops->get_powered(&local->hw, up, busy); + + return ret; +} + +int drv_set_powered(struct ieee80211_local *local) +{ + int ret = -EOPNOTSUPP; + + might_sleep(); + + if (local->ops->set_powered) + ret = local->ops->set_powered(&local->hw); + + return ret; +} + int drv_add_interface(struct ieee80211_local *local, struct ieee80211_sub_if_data *sdata) { diff -ruw linux-5.4.60/net/mac80211/driver-ops.h linux-5.4.60-fbx/net/mac80211/driver-ops.h --- linux-5.4.60/net/mac80211/driver-ops.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/driver-ops.h 2021-03-04 13:21:01.450839053 +0100 @@ -85,6 +85,8 @@ int drv_start(struct ieee80211_local *local); void drv_stop(struct ieee80211_local *local); +int drv_get_powered(struct ieee80211_local *local, bool *up, bool *busy); +int drv_set_powered(struct ieee80211_local *local); #ifdef CONFIG_PM static inline int drv_suspend(struct ieee80211_local *local, diff -ruw linux-5.4.60/net/mac80211/ethtool.c linux-5.4.60-fbx/net/mac80211/ethtool.c --- linux-5.4.60/net/mac80211/ethtool.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/ethtool.c 2021-03-04 13:21:01.450839053 +0100 @@ -46,6 +46,22 @@ }; #define STA_STATS_LEN ARRAY_SIZE(ieee80211_gstrings_sta_stats) +struct ethtool_priv_flags_strings { + const char string[ETH_GSTRING_LEN]; +}; + +enum { + POWERED_SUPPORTED = (1 << 0), + POWERED_STATUS = (1 << 1), + POWERED_CHANGE_BUSY = (1 << 2), +}; + +static const struct ethtool_priv_flags_strings ieee80211_pflags_strings[] = { + { .string = "powered-supported" }, + { .string = "powered-status" }, + { .string = "powered-change-busy", }, +}; + static int ieee80211_get_sset_count(struct net_device *dev, int sset) { struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); @@ -56,6 +72,9 @@ rv += drv_get_et_sset_count(sdata, sset); + if (sset == ETH_SS_PRIV_FLAGS) + rv += ARRAY_SIZE(ieee80211_pflags_strings); + if (rv == 0) return -EOPNOTSUPP; return rv; @@ -212,6 +231,9 @@ memcpy(data, ieee80211_gstrings_sta_stats, sz_sta_stats); } drv_get_et_strings(sdata, sset, &(data[sz_sta_stats])); + if (sset == ETH_SS_PRIV_FLAGS) + memcpy(data, ieee80211_pflags_strings, + sizeof (ieee80211_pflags_strings)); } static int ieee80211_get_regs_len(struct net_device *dev) @@ -229,6 +251,35 @@ regs->len = 0; } +static u32 ieee80211_get_priv_flags(struct net_device *dev) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; + bool powered, powered_busy; + u32 ret; + + ret = 0; + if (!drv_get_powered(local, &powered, &powered_busy)) { + ret |= POWERED_SUPPORTED; + if (powered) + ret |= POWERED_STATUS; + if (powered_busy) + ret |= POWERED_CHANGE_BUSY; + } + return ret; +} + +static int ieee80211_set_priv_flags(struct net_device *dev, u32 flags) +{ + struct ieee80211_sub_if_data *sdata = IEEE80211_DEV_TO_SUB_IF(dev); + struct ieee80211_local *local = sdata->local; + + if (flags & (POWERED_STATUS)) + return drv_set_powered(local); + + return 0; +} + const struct ethtool_ops ieee80211_ethtool_ops = { .get_drvinfo = cfg80211_get_drvinfo, .get_regs_len = ieee80211_get_regs_len, @@ -239,4 +290,6 @@ .get_strings = ieee80211_get_strings, .get_ethtool_stats = ieee80211_get_stats, .get_sset_count = ieee80211_get_sset_count, + .set_priv_flags = ieee80211_set_priv_flags, + .get_priv_flags = ieee80211_get_priv_flags, }; diff -ruw linux-5.4.60/net/mac80211/ieee80211_i.h linux-5.4.60-fbx/net/mac80211/ieee80211_i.h --- linux-5.4.60/net/mac80211/ieee80211_i.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/ieee80211_i.h 2021-03-04 13:21:01.450839053 +0100 @@ -721,6 +721,13 @@ struct mesh_table *mpp_paths; /* Store paths for MPP&MAP */ int mesh_paths_generation; int mpp_paths_generation; + + /* Store Vendor specific node metrics IE */ + u8 node_vendor_ie[260]; + u8 node_vendor_ie_len; + /* Store Vendor specific mesh path metrics IE */ + u8 mpm_vendor_ie[260]; + u8 mpm_vendor_ie_len; }; #ifdef CONFIG_MAC80211_MESH @@ -1532,6 +1539,13 @@ bool parse_error; }; +struct ieee802_11_mesh_vendor_specific_elems { + const u8 *ie_start; + u8 ie_len; + /* whether a parse error occurred while retrieving these elements */ + bool parse_error; +}; + static inline struct ieee80211_local *hw_to_local( struct ieee80211_hw *hw) { @@ -1983,6 +1997,9 @@ struct ieee802_11_elems *elems, u64 filter, u32 crc, u8 *transmitter_bssid, u8 *bss_bssid); +u32 ieee802_11_parse_mesh_vendor_elems(const u8 *start, size_t len, bool action, + struct ieee802_11_mesh_vendor_specific_elems *elems, + u64 filter, u32 crc, u8 type); static inline void ieee802_11_parse_elems(const u8 *start, size_t len, bool action, struct ieee802_11_elems *elems, diff -ruw linux-5.4.60/net/mac80211/key.c linux-5.4.60-fbx/net/mac80211/key.c --- linux-5.4.60/net/mac80211/key.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/key.c 2021-03-04 13:21:01.450839053 +0100 @@ -172,6 +172,12 @@ * Hence, don't send GTKs for VLAN interfaces to the driver. */ if (!(key->conf.flags & IEEE80211_KEY_FLAG_PAIRWISE)) { + if (ieee80211_hw_check(&key->local->hw, + APVLAN_NEED_MCAST_TO_UCAST)) { + /* no need to fail, this key will + * never be used */ + return 0; + } ret = 1; goto out_unsupported; } diff -ruw linux-5.4.60/net/mac80211/mesh.c linux-5.4.60-fbx/net/mac80211/mesh.c --- linux-5.4.60/net/mac80211/mesh.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/mesh.c 2021-03-30 15:48:29.608385862 +0200 @@ -338,20 +338,31 @@ u8 offset, len; const u8 *data; - if (!ifmsh->ie || !ifmsh->ie_len) - return 0; /* fast-forward to vendor IEs */ - offset = ieee80211_ie_split_vendor(ifmsh->ie, ifmsh->ie_len, 0); + if (ifmsh->node_vendor_ie_len) { + offset = ieee80211_ie_split_vendor(ifmsh->node_vendor_ie, ifmsh->node_vendor_ie_len, 0); - if (offset < ifmsh->ie_len) { - len = ifmsh->ie_len - offset; - data = ifmsh->ie + offset; + if (offset < ifmsh->node_vendor_ie_len) { + len = ifmsh->node_vendor_ie_len - offset; + data = ifmsh->node_vendor_ie + offset; if (skb_tailroom(skb) < len) return -ENOMEM; skb_put_data(skb, data, len); } + } + if (ifmsh->mpm_vendor_ie_len) { + offset = ieee80211_ie_split_vendor(ifmsh->mpm_vendor_ie, ifmsh->mpm_vendor_ie_len, 0); + + if (offset < ifmsh->mpm_vendor_ie_len) { + len = ifmsh->mpm_vendor_ie_len - offset; + data = ifmsh->mpm_vendor_ie + offset; + if (skb_tailroom(skb) < len) + return -ENOMEM; + skb_put_data(skb, data, len); + } + } return 0; } @@ -766,7 +777,9 @@ 2 + sizeof(struct ieee80211_vht_operation) + ie_len_he_cap + 2 + 1 + sizeof(struct ieee80211_he_operation) + - ifmsh->ie_len; + ifmsh->ie_len + + ifmsh->node_vendor_ie_len + + ifmsh->mpm_vendor_ie_len; bcn = kzalloc(sizeof(*bcn) + head_len + tail_len, GFP_KERNEL); /* need an skb for IE builders to operate on */ @@ -1220,12 +1233,18 @@ size_t baselen; int freq; enum nl80211_band band = rx_status->band; + struct ieee802_11_mesh_vendor_specific_elems velems; + u32 beacon_int; + bool is_neigh_conn_estab; /* ignore ProbeResp to foreign address */ if (stype == IEEE80211_STYPE_PROBE_RESP && !ether_addr_equal(mgmt->da, sdata->vif.addr)) return; + if (stype == IEEE80211_STYPE_BEACON) + beacon_int = mgmt->u.beacon.beacon_int; + baselen = (u8 *) mgmt->u.probe_resp.variable - (u8 *) mgmt; if (baselen > len) return; @@ -1252,6 +1271,37 @@ if (mesh_matches_local(sdata, &elems)) { mpl_dbg(sdata, "rssi_threshold=%d,rx_status->signal=%d\n", sdata->u.mesh.mshcfg.rssi_threshold, rx_status->signal); + is_neigh_conn_estab = mesh_neighbour_connection_established(sdata, mgmt->sa, rx_status); + ieee802_11_parse_mesh_vendor_elems(mgmt->u.probe_resp.variable, + len - baselen, + false, &velems, 0, 0, + NL80211_QBC_UPDATE_NODE_METRICS_IE); + + if (velems.parse_error == false) { + if (is_neigh_conn_estab) + cfg80211_notify_mesh_peer_node_metrics(sdata->dev, mgmt->sa, stype, + rx_status->signal, + beacon_int, + velems.ie_start, + velems.ie_len, + GFP_KERNEL); + elems.total_len -= (velems.ie_len + 2); + } + + ieee802_11_parse_mesh_vendor_elems(mgmt->u.probe_resp.variable, + len - baselen, + false, &velems, 0, 0, + NL80211_QBC_UPDATE_PATH_METRICS_IE); + if (velems.parse_error == false) { + if (is_neigh_conn_estab) + cfg80211_notify_mesh_peer_path_metrics(sdata->dev, mgmt->sa, + velems.ie_start, + velems.ie_len, + GFP_KERNEL); + + elems.total_len -= (velems.ie_len + 2); + } + if (!sdata->u.mesh.user_mpm || sdata->u.mesh.mshcfg.rssi_threshold == 0 || sdata->u.mesh.mshcfg.rssi_threshold < rx_status->signal) @@ -1362,11 +1412,20 @@ bool fwd_csa = true; size_t baselen; u8 *pos; + struct sta_info *sta = NULL; if (mgmt->u.action.u.measurement.action_code != WLAN_ACTION_SPCT_CHL_SWITCH) return; + /* Process action frames received from connected mesh nodes */ + rcu_read_lock(); + sta = sta_info_get(sdata, mgmt->bssid); + if (!sta) { + rcu_read_unlock(); + return; + } + rcu_read_unlock(); pos = mgmt->u.action.u.chan_switch.variable; baselen = offsetof(struct ieee80211_mgmt, u.action.u.chan_switch.variable); diff -ruw linux-5.4.60/net/mac80211/mesh.h linux-5.4.60-fbx/net/mac80211/mesh.h --- linux-5.4.60/net/mac80211/mesh.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/mesh.h 2021-03-30 15:48:29.608385862 +0200 @@ -297,7 +297,9 @@ struct ieee80211_mgmt *mgmt, size_t len, struct ieee80211_rx_status *rx_status); void mesh_sta_cleanup(struct sta_info *sta); - +bool mesh_neighbour_connection_established(struct ieee80211_sub_if_data *sdata, + u8 *hw_addr, + struct ieee80211_rx_status *rx_status); /* Private interfaces */ /* Mesh paths */ int mesh_path_error_tx(struct ieee80211_sub_if_data *sdata, diff -ruw linux-5.4.60/net/mac80211/mesh_plink.c linux-5.4.60-fbx/net/mac80211/mesh_plink.c --- linux-5.4.60/net/mac80211/mesh_plink.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/mesh_plink.c 2021-03-30 15:48:29.608385862 +0200 @@ -1226,3 +1226,32 @@ mgmt->bssid, NULL); mesh_process_plink_frame(sdata, mgmt, &elems, rx_status); } + +/* + * mesh_neighbour_connection_established - return if connection has been established with neighbor. + * + * @sdata: local meshif + * @addr: peer's address + * @elems: IEs from beacon or mesh peering frame + * + * + */ +bool mesh_neighbour_connection_established(struct ieee80211_sub_if_data *sdata, + u8 *hw_addr, + struct ieee80211_rx_status *rx_status) +{ + struct sta_info *sta; + bool ret = false; + + rcu_read_lock(); + sta = sta_info_get(sdata, hw_addr); + if (!sta) + goto out; + + if (sta->mesh->plink_state == NL80211_PLINK_ESTAB) + ret = true; + +out: + rcu_read_unlock(); + return ret; +} diff -ruw linux-5.4.60/net/mac80211/rx.c linux-5.4.60-fbx/net/mac80211/rx.c --- linux-5.4.60/net/mac80211/rx.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/rx.c 2021-03-04 13:21:01.454172386 +0100 @@ -2756,9 +2756,11 @@ mpp_path_add(sdata, proxied_addr, mpp_addr); } else { spin_lock_bh(&mppath->state_lock); - if (!ether_addr_equal(mppath->mpp, mpp_addr)) + if (!ether_addr_equal(mppath->mpp, mpp_addr) && + !(mppath->flags & MESH_PATH_FIXED)) { memcpy(mppath->mpp, mpp_addr, ETH_ALEN); mppath->exp_time = jiffies; + } spin_unlock_bh(&mppath->state_lock); } rcu_read_unlock(); @@ -2823,6 +2825,7 @@ } IEEE80211_IFSTA_MESH_CTR_INC(ifmsh, fwded_frames); + fwd_skb->dev = sdata->dev; ieee80211_add_pending_skb(local, fwd_skb); out: if (is_multicast_ether_addr(hdr->addr1)) @@ -4577,7 +4580,7 @@ * The same happens when we're not even started, * but that's worth a warning. */ - if (WARN_ON(!local->started)) + if (!local->started) goto drop; if (likely(!(status->flag & RX_FLAG_FAILED_PLCP_CRC))) { diff -ruw linux-5.4.60/net/mac80211/sta_info.c linux-5.4.60-fbx/net/mac80211/sta_info.c --- linux-5.4.60/net/mac80211/sta_info.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/sta_info.c 2021-03-04 13:21:01.454172386 +0100 @@ -277,9 +277,10 @@ return; local_bh_disable(); - if (!test_sta_flag(sta, WLAN_STA_PS_STA)) + if (!test_sta_flag(sta, WLAN_STA_PS_STA)) { + if (test_sta_flag(sta, WLAN_STA_PS_DELIVER)) ieee80211_sta_ps_deliver_wakeup(sta); - else if (test_and_clear_sta_flag(sta, WLAN_STA_PSPOLL)) + } else if (test_and_clear_sta_flag(sta, WLAN_STA_PSPOLL)) ieee80211_sta_ps_deliver_poll_response(sta); else if (test_and_clear_sta_flag(sta, WLAN_STA_UAPSD)) ieee80211_sta_ps_deliver_uapsd(sta); diff -ruw linux-5.4.60/net/mac80211/status.c linux-5.4.60-fbx/net/mac80211/status.c --- linux-5.4.60/net/mac80211/status.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/status.c 2021-03-04 13:21:01.457505719 +0100 @@ -876,13 +876,15 @@ struct ieee80211_bar *bar; int shift = 0; int tid = IEEE80211_NUM_TIDS; + bool ack_requested; rates_idx = ieee80211_tx_get_rates(hw, info, &retry_count); + ack_requested = !(info->flags & IEEE80211_TX_CTL_NO_ACK); sband = local->hw.wiphy->bands[info->band]; fc = hdr->frame_control; - if (status->sta) { + if (status->sta && ack_requested) { sta = container_of(status->sta, struct sta_info, sta); shift = ieee80211_vif_get_shift(&sta->sdata->vif); @@ -1101,6 +1103,7 @@ struct ieee80211_supported_band *sband; int retry_count; bool acked, noack_success; + bool ack_requested; if (status->skb) return __ieee80211_tx_status(hw, status); @@ -1112,10 +1115,11 @@ sband = hw->wiphy->bands[info->band]; + ack_requested = !(info->flags & IEEE80211_TX_CTL_NO_ACK); acked = !!(info->flags & IEEE80211_TX_STAT_ACK); noack_success = !!(info->flags & IEEE80211_TX_STAT_NOACK_TRANSMITTED); - if (pubsta) { + if (pubsta && ack_requested) { struct sta_info *sta; sta = container_of(pubsta, struct sta_info, sta); diff -ruw linux-5.4.60/net/mac80211/tx.c linux-5.4.60-fbx/net/mac80211/tx.c --- linux-5.4.60/net/mac80211/tx.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/tx.c 2021-03-04 13:21:01.457505719 +0100 @@ -1256,6 +1256,9 @@ (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE)) return NULL; + if (unlikely(ieee80211_is_ctl(hdr->frame_control))) + return NULL; + if (unlikely(!ieee80211_is_data_present(hdr->frame_control))) { if ((!ieee80211_is_mgmt(hdr->frame_control) || ieee80211_is_bufferable_mmpdu(hdr->frame_control) || @@ -3961,6 +3964,9 @@ return false; if (sdata->wdev.use_4addr) return false; + if (ieee80211_hw_check(&sdata->local->hw, + APVLAN_NEED_MCAST_TO_UCAST)) + break; /* fall through */ case NL80211_IFTYPE_AP: /* check runtime toggle for this bss */ diff -ruw linux-5.4.60/net/mac80211/util.c linux-5.4.60-fbx/net/mac80211/util.c --- linux-5.4.60/net/mac80211/util.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/mac80211/util.c 2021-03-04 13:21:01.457505719 +0100 @@ -250,7 +250,8 @@ local_bh_disable(); spin_lock(&fq->lock); - if (sdata->vif.type == NL80211_IFTYPE_AP) + if ((sdata->vif.type == NL80211_IFTYPE_AP) && + ieee80211_sdata_running(sdata)) ps = &sdata->bss->ps; sdata->vif.txqs_stopped[ac] = false; @@ -891,6 +892,63 @@ } EXPORT_SYMBOL(ieee80211_queue_delayed_work); +u32 ieee802_11_parse_mesh_vendor_elems(const u8 *start, size_t len, bool action, + struct ieee802_11_mesh_vendor_specific_elems *elems, + u64 filter, u32 crc, u8 type) +{ + size_t left = len; + const u8 *pos = start; + bool calc_crc = filter != 0; + + memset(elems, 0, sizeof(*elems)); + elems->parse_error = true; + + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) { + break; + } + + if (calc_crc && id < 64 && (filter & (1ULL << id))) + crc = crc32_be(crc, pos - 2, elen + 2); + + + switch (id) { + case WLAN_EID_VENDOR_SPECIFIC: + if (elen >= 4 && pos[0] == 0xC0 && pos[1] == 0xFF && + pos[2] == 0xEE && pos[3] == type) { + /* Qubercomm OUI (C0:FF:EE) */ + + if (calc_crc) + crc = crc32_be(crc, pos - 2, elen + 2); + + elems->ie_start = pos; + elems->ie_len = elen; + elems->parse_error = false; + + } + break; + default: + break; + } + + if (elems->parse_error == false) + break; + + left -= elen; + pos += elen; + } + + return crc; + +} +EXPORT_SYMBOL(ieee802_11_parse_mesh_vendor_elems); + static u32 _ieee802_11_parse_elems_crc(const u8 *start, size_t len, bool action, struct ieee802_11_elems *elems, @@ -3808,6 +3866,32 @@ ps->dtim_count = dtim_count; } +void ieee80211_force_dtim(struct ieee80211_vif *vif, + unsigned int dtim_count) +{ + struct ieee80211_sub_if_data *sdata = vif_to_sdata(vif); + u8 dtim_period = sdata->vif.bss_conf.dtim_period; + struct ps_data *ps; + + if (sdata->vif.type == NL80211_IFTYPE_AP || + sdata->vif.type == NL80211_IFTYPE_AP_VLAN) { + if (!sdata->bss) + return; + + ps = &sdata->bss->ps; + } else if (ieee80211_vif_is_mesh(&sdata->vif)) { + ps = &sdata->u.mesh.ps; + } else { + return; + } + + if (WARN_ON_ONCE(dtim_count >= dtim_period)) + return; + + ps->dtim_count = dtim_count; +} +EXPORT_SYMBOL(ieee80211_force_dtim); + static u8 ieee80211_chanctx_radar_detect(struct ieee80211_local *local, struct ieee80211_chanctx *ctx) { diff -ruw linux-5.4.60/net/Makefile linux-5.4.60-fbx/net/Makefile --- linux-5.4.60/net/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/Makefile 2021-03-04 13:21:01.370839049 +0100 @@ -39,6 +39,12 @@ obj-$(CONFIG_STREAM_PARSER) += strparser/ obj-$(CONFIG_ATM) += atm/ obj-$(CONFIG_L2TP) += l2tp/ +ifneq ($(CONFIG_FBXATM),) +obj-y += fbxatm/ +endif +ifneq ($(CONFIG_FBXBRIDGE),) +obj-y += fbxbridge/ +endif obj-$(CONFIG_DECNET) += decnet/ obj-$(CONFIG_PHONET) += phonet/ ifneq ($(CONFIG_VLAN_8021Q),) @@ -87,3 +93,4 @@ obj-$(CONFIG_QRTR) += qrtr/ obj-$(CONFIG_NET_NCSI) += ncsi/ obj-$(CONFIG_XDP_SOCKETS) += xdp/ +obj-$(CONFIG_NET_NMESH_MBH) += nmesh-mbh/ diff -ruw linux-5.4.60/net/netfilter/Kconfig linux-5.4.60-fbx/net/netfilter/Kconfig --- linux-5.4.60/net/netfilter/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/Kconfig 2021-03-04 13:21:01.460839053 +0100 @@ -333,6 +333,7 @@ config NF_CONNTRACK_SIP tristate "SIP protocol support" default m if NETFILTER_ADVANCED=n + select CRYPTO_LIB_SHA256 help SIP is an application-layer control protocol that can establish, modify, and terminate multimedia sessions (conferences) such as diff -ruw linux-5.4.60/net/netfilter/nf_conntrack_core.c linux-5.4.60-fbx/net/netfilter/nf_conntrack_core.c --- linux-5.4.60/net/netfilter/nf_conntrack_core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_conntrack_core.c 2021-03-04 13:21:01.467505720 +0100 @@ -592,6 +592,14 @@ #endif } +#ifdef CONFIG_IP_FFN +extern void ip_ffn_ct_destroy(struct nf_conn *ct); +#endif + +#ifdef CONFIG_IPV6_FFN +extern void ipv6_ffn_ct_destroy(struct nf_conn *ct); +#endif + static void destroy_conntrack(struct nf_conntrack *nfct) { @@ -600,6 +608,15 @@ pr_debug("destroy_conntrack(%p)\n", ct); WARN_ON(atomic_read(&nfct->use) != 0); +#ifdef CONFIG_IP_FFN + if (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num == AF_INET) + ip_ffn_ct_destroy(ct); +#endif +#ifdef CONFIG_IPV6_FFN + if (ct->tuplehash[IP_CT_DIR_ORIGINAL].tuple.src.l3num == AF_INET6) + ipv6_ffn_ct_destroy(ct); +#endif + if (unlikely(nf_ct_is_template(ct))) { nf_ct_tmpl_free(ct); return; diff -ruw linux-5.4.60/net/netfilter/nf_conntrack_ftp.c linux-5.4.60-fbx/net/netfilter/nf_conntrack_ftp.c --- linux-5.4.60/net/netfilter/nf_conntrack_ftp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_conntrack_ftp.c 2021-03-04 13:21:01.467505720 +0100 @@ -27,6 +27,10 @@ #include #define HELPER_NAME "ftp" +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) +#include +#include +#endif MODULE_LICENSE("GPL"); MODULE_AUTHOR("Rusty Russell "); @@ -398,6 +402,17 @@ return NF_ACCEPT; } +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + if (!ct_ftp_info->is_fbxbridge && skb->dev->fbx_bridge) { + struct fbxbridge *fbxbr; + + fbxbr = skb->dev->fbx_bridge; + ct_ftp_info->is_fbxbridge = 1; + ct_ftp_info->fbxbridge_remote = ntohl(fbxbr->br_remote_ipaddr); + ct_ftp_info->fbxbridge_wan = fbxbr->wan_ipaddr; + } +#endif + th = skb_header_pointer(skb, protoff, sizeof(_tcph), &_tcph); if (th == NULL) return NF_ACCEPT; @@ -484,6 +499,50 @@ * Doesn't matter unless NAT is happening. */ daddr = &ct->tuplehash[!dir].tuple.dst.u3; +#if defined(CONFIG_FREEBOX_BRIDGE) || defined(CONFIG_FREEBOX_BRIDGE_MODULE) + if (ct_ftp_info->is_fbxbridge && + search[dir][i].ftptype == NF_CT_FTP_PORT) { + unsigned long orig_ip_addr; + unsigned short orig_port; + char buffer[sizeof("nnn,nnn,nnn,nnn,nnn,nnn")]; + unsigned int len; + __be32 addr; + + /* kludge: if we are here, then this is a local pkt + * that has gone through internal fbxbridge snat. + * + * If we see a port command, then we mangle packet to + * change ip address given to the remote bridge + * address */ + + /* check address is packet is the one fbxbridge + * changed */ + orig_ip_addr = cmd.u3.ip; + if (orig_ip_addr != ct_ftp_info->fbxbridge_wan) + goto donttouch; + + /* now mangle the remote address */ + orig_port = cmd.u.tcp.port; + addr = ct_ftp_info->fbxbridge_remote; + len = sprintf(buffer, "%u,%u,%u,%u,%u,%u", + ((unsigned char *)&addr)[0], + ((unsigned char *)&addr)[1], + ((unsigned char *)&addr)[2], + ((unsigned char *)&addr)[3], + orig_port >> 8 , orig_port & 0xFF); + + nf_nat_mangle_tcp_packet(skb, ct, ctinfo, matchoff, + matchlen, buffer, len); + + /* then adjust as if nothing happened */ + matchlen = len; + cmd.u3.ip = ct_ftp_info->fbxbridge_remote; + } +donttouch: + +#endif + + /* Update the ftp info */ if ((cmd.l3num == nf_ct_l3num(ct)) && memcmp(&cmd.u3.all, &ct->tuplehash[dir].tuple.src.u3.all, diff -ruw linux-5.4.60/net/netfilter/nf_conntrack_helper.c linux-5.4.60-fbx/net/netfilter/nf_conntrack_helper.c --- linux-5.4.60/net/netfilter/nf_conntrack_helper.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_conntrack_helper.c 2021-03-04 13:21:01.467505720 +0100 @@ -35,7 +35,7 @@ EXPORT_SYMBOL_GPL(nf_ct_helper_hsize); static unsigned int nf_ct_helper_count __read_mostly; -static bool nf_ct_auto_assign_helper __read_mostly = false; +static bool nf_ct_auto_assign_helper __read_mostly = true; module_param_named(nf_conntrack_helper, nf_ct_auto_assign_helper, bool, 0644); MODULE_PARM_DESC(nf_conntrack_helper, "Enable automatic conntrack helper assignment (default 0)"); diff -ruw linux-5.4.60/net/netfilter/nf_conntrack_proto_tcp.c linux-5.4.60-fbx/net/netfilter/nf_conntrack_proto_tcp.c --- linux-5.4.60/net/netfilter/nf_conntrack_proto_tcp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_conntrack_proto_tcp.c 2021-03-04 13:21:01.467505720 +0100 @@ -1088,7 +1088,8 @@ break; } - if (!tcp_in_window(ct, &ct->proto.tcp, dir, index, + if (!ct->proto.tcp.no_window_track && + !tcp_in_window(ct, &ct->proto.tcp, dir, index, skb, dataoff, th)) { spin_unlock_bh(&ct->lock); return -NF_ACCEPT; @@ -1163,6 +1164,38 @@ return NF_ACCEPT; } +#ifdef CONFIG_IP_FFN +int external_tcpv4_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET, + .net = nf_ct_net(ct), + }; + return nf_conntrack_tcp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + +#ifdef CONFIG_IPV6_FFN +int external_tcpv6_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET6, + .net = nf_ct_net(ct), + }; + return nf_conntrack_tcp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + static bool tcp_can_early_drop(const struct nf_conn *ct) { switch (ct->proto.tcp.state) { diff -ruw linux-5.4.60/net/netfilter/nf_conntrack_proto_udp.c linux-5.4.60-fbx/net/netfilter/nf_conntrack_proto_udp.c --- linux-5.4.60/net/netfilter/nf_conntrack_proto_udp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_conntrack_proto_udp.c 2021-03-04 13:21:01.467505720 +0100 @@ -122,6 +122,38 @@ return NF_ACCEPT; } +#ifdef CONFIG_IP_FFN +int external_udpv4_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET, + .net = nf_ct_net(ct), + }; + return nf_conntrack_udp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + +#ifdef CONFIG_IPV6_FFN +int external_udpv6_packet(struct nf_conn *ct, + struct sk_buff *skb, + unsigned int dataoff, + enum ip_conntrack_info ctinfo) +{ + /* fixme: is is always PRE_ROUTING ?*/ + struct nf_hook_state state = { + .hook = NF_INET_PRE_ROUTING, + .pf = AF_INET6, + .net = nf_ct_net(ct), + }; + return nf_conntrack_udp_packet(ct, skb, dataoff, ctinfo, &state); +} +#endif + #ifdef CONFIG_NF_CT_PROTO_UDPLITE static void udplite_error_log(const struct sk_buff *skb, const struct nf_hook_state *state, diff -ruw linux-5.4.60/net/netfilter/nf_conntrack_sip.c linux-5.4.60-fbx/net/netfilter/nf_conntrack_sip.c --- linux-5.4.60/net/netfilter/nf_conntrack_sip.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_conntrack_sip.c 2021-03-04 13:21:01.467505720 +0100 @@ -35,6 +35,8 @@ MODULE_ALIAS("ip_conntrack_sip"); MODULE_ALIAS_NFCT_HELPER(HELPER_NAME); +#define MAX_CALLS 8 + #define MAX_PORTS 8 static unsigned short ports[MAX_PORTS]; static unsigned int ports_c; @@ -825,7 +827,8 @@ return found; } -static void flush_expectations(struct nf_conn *ct, bool media) +static void __flush_expectations(struct nf_conn *ct, bool media, + const u8 *cid_hash) { struct nf_conn_help *help = nfct_help(ct); struct nf_conntrack_expect *exp; @@ -835,6 +838,15 @@ hlist_for_each_entry_safe(exp, next, &help->expectations, lnode) { if ((exp->class != SIP_EXPECT_SIGNALLING) ^ media) continue; + if (media && cid_hash) { + const struct nf_ct_sip_expect *exp_sip_info; + exp_sip_info = nf_ct_exp_data(exp); + + if (memcmp(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash))) + continue; + } + if (!nf_ct_remove_expect(exp)) continue; if (!media) @@ -843,12 +855,36 @@ spin_unlock_bh(&nf_conntrack_expect_lock); } +static void flush_sig_expectations(struct nf_conn *ct) +{ + return __flush_expectations(ct, false, NULL); +} + +static void flush_media_expectations(struct nf_conn *ct, + const char *msg_data, + unsigned int msg_len) +{ + unsigned int matchoff, matchlen; + u8 cid_hash[SHA256_DIGEST_SIZE]; + struct sha256_state s; + + sha256_init(&s); + if (ct_sip_get_header(ct, msg_data, 0, msg_len, + SIP_HDR_CALL_ID, + &matchoff, &matchlen) > 0) + sha256_update(&s, msg_data + matchoff, matchlen); + sha256_final(&s, cid_hash); + + __flush_expectations(ct, true, cid_hash); +} + static int set_expected_rtp_rtcp(struct sk_buff *skb, unsigned int protoff, unsigned int dataoff, const char **dptr, unsigned int *datalen, union nf_inet_addr *daddr, __be16 port, enum sip_expectation_classes class, - unsigned int mediaoff, unsigned int medialen) + unsigned int mediaoff, unsigned int medialen, + const u8 *cid_hash) { struct nf_conntrack_expect *exp, *rtp_exp, *rtcp_exp; enum ip_conntrack_info ctinfo; @@ -861,6 +897,7 @@ u_int16_t base_port; __be16 rtp_port, rtcp_port; const struct nf_nat_sip_hooks *hooks; + struct nf_ct_sip_expect *exp_sip_info; saddr = NULL; if (sip_direct_media) { @@ -953,18 +990,29 @@ goto err1; } - if (skip_expect) + if (skip_expect) { + exp_sip_info = nf_ct_exp_data(exp); + memcpy(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash)); return NF_ACCEPT; + } rtp_exp = nf_ct_expect_alloc(ct); if (rtp_exp == NULL) goto err1; + exp_sip_info = nf_ct_exp_data(rtp_exp); + memcpy(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash)); nf_ct_expect_init(rtp_exp, class, nf_ct_l3num(ct), saddr, daddr, IPPROTO_UDP, NULL, &rtp_port); + rtcp_exp = nf_ct_expect_alloc(ct); if (rtcp_exp == NULL) goto err2; + exp_sip_info = nf_ct_exp_data(rtcp_exp); + memcpy(exp_sip_info->cid_hash, cid_hash, + sizeof (exp_sip_info->cid_hash)); nf_ct_expect_init(rtcp_exp, class, nf_ct_l3num(ct), saddr, daddr, IPPROTO_UDP, NULL, &rtcp_port); @@ -1039,10 +1087,20 @@ const struct nf_nat_sip_hooks *hooks; unsigned int port; const struct sdp_media_type *t; + struct sha256_state s; + u8 cid_hash[SHA256_DIGEST_SIZE]; int ret = NF_ACCEPT; hooks = rcu_dereference(nf_nat_sip_hooks); + /* extract caller id if any */ + sha256_init(&s); + if (ct_sip_get_header(ct, *dptr, 0, *datalen, + SIP_HDR_CALL_ID, + &matchoff, &matchlen) > 0) + sha256_update(&s, *dptr + matchoff, matchlen); + sha256_final(&s, cid_hash); + /* Find beginning of session description */ if (ct_sip_get_sdp_header(ct, *dptr, 0, *datalen, SDP_HDR_VERSION, SDP_HDR_UNSPEC, @@ -1101,7 +1159,7 @@ ret = set_expected_rtp_rtcp(skb, protoff, dataoff, dptr, datalen, &rtp_addr, htons(port), t->class, - mediaoff, medialen); + mediaoff, medialen, cid_hash); if (ret != NF_ACCEPT) { nf_ct_helper_log(skb, ct, "cannot add expectation for voice"); @@ -1145,7 +1203,7 @@ (code >= 200 && code <= 299)) return process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); else if (ct_sip_info->invite_cseq == cseq) - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1162,7 +1220,7 @@ (code >= 200 && code <= 299)) return process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); else if (ct_sip_info->invite_cseq == cseq) - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1179,7 +1237,7 @@ (code >= 200 && code <= 299)) return process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); else if (ct_sip_info->invite_cseq == cseq) - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1193,7 +1251,7 @@ struct nf_ct_sip_master *ct_sip_info = nfct_help_data(ct); unsigned int ret; - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); ret = process_sdp(skb, protoff, dataoff, dptr, datalen, cseq); if (ret == NF_ACCEPT) ct_sip_info->invite_cseq = cseq; @@ -1208,7 +1266,7 @@ enum ip_conntrack_info ctinfo; struct nf_conn *ct = nf_ct_get(skb, &ctinfo); - flush_expectations(ct, true); + flush_media_expectations(ct, *dptr, *datalen); return NF_ACCEPT; } @@ -1387,7 +1445,7 @@ } flush: - flush_expectations(ct, false); + flush_sig_expectations(ct); return NF_ACCEPT; } @@ -1642,17 +1700,17 @@ }, [SIP_EXPECT_AUDIO] = { .name = "audio", - .max_expected = 2 * IP_CT_DIR_MAX, + .max_expected = MAX_CALLS * 2 * IP_CT_DIR_MAX, .timeout = 3 * 60, }, [SIP_EXPECT_VIDEO] = { .name = "video", - .max_expected = 2 * IP_CT_DIR_MAX, + .max_expected = MAX_CALLS * 2 * IP_CT_DIR_MAX, .timeout = 3 * 60, }, [SIP_EXPECT_IMAGE] = { .name = "image", - .max_expected = IP_CT_DIR_MAX, + .max_expected = MAX_CALLS * IP_CT_DIR_MAX, .timeout = 3 * 60, }, }; @@ -1667,6 +1725,7 @@ int i, ret; NF_CT_HELPER_BUILD_BUG_ON(sizeof(struct nf_ct_sip_master)); + NF_CT_EXPECT_BUILD_BUG_ON(sizeof(struct nf_ct_sip_expect)); if (ports_c == 0) ports[ports_c++] = SIP_PORT; diff -ruw linux-5.4.60/net/netfilter/nf_nat_core.c linux-5.4.60-fbx/net/netfilter/nf_nat_core.c --- linux-5.4.60/net/netfilter/nf_nat_core.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_nat_core.c 2021-03-04 13:21:01.470839054 +0100 @@ -661,6 +661,11 @@ else ct->status |= IPS_SRC_NAT_DONE; + if (maniptype == NF_NAT_MANIP_SRC) { + ct->nat_src_proto_min = range->min_proto; + ct->nat_src_proto_max = range->max_proto; + } + return NF_ACCEPT; } EXPORT_SYMBOL(nf_nat_setup_info); diff -ruw linux-5.4.60/net/netfilter/nf_nat_ftp.c linux-5.4.60-fbx/net/netfilter/nf_nat_ftp.c --- linux-5.4.60/net/netfilter/nf_nat_ftp.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_nat_ftp.c 2021-03-04 13:21:01.470839054 +0100 @@ -69,7 +69,8 @@ struct nf_conntrack_expect *exp) { union nf_inet_addr newaddr; - u_int16_t port; + u_int16_t port, sport, eport; + unsigned int i; int dir = CTINFO2DIR(ctinfo); struct nf_conn *ct = exp->master; char buffer[sizeof("|1||65535|") + INET6_ADDRSTRLEN]; @@ -86,8 +87,26 @@ * this one. */ exp->expectfn = nf_nat_follow_master; + if (dir == IP_CT_DIR_ORIGINAL && + (ct->status & IPS_SRC_NAT) && + ct->nat_src_proto_min.all && + ct->nat_src_proto_max.all) { + sport = ntohs(ct->nat_src_proto_min.all); + eport = ntohs(ct->nat_src_proto_max.all); + } else { + sport = 1024; + eport = 65535; + } + + port = ntohs(exp->saved_proto.tcp.port); + if (port < sport || port > eport) { + get_random_bytes(&port, sizeof (port)); + port %= eport - sport; + port += sport; + } + /* Try to get same port: if not, try to change it. */ - for (port = ntohs(exp->saved_proto.tcp.port); port != 0; port++) { + for (i = 0; i < eport - sport + 1; i++) { int ret; exp->tuple.dst.u.tcp.port = htons(port); @@ -98,6 +117,10 @@ port = 0; break; } + + port++; + if (port > eport) + port = sport; } if (port == 0) { diff -ruw linux-5.4.60/net/netfilter/nf_nat_helper.c linux-5.4.60-fbx/net/netfilter/nf_nat_helper.c --- linux-5.4.60/net/netfilter/nf_nat_helper.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_nat_helper.c 2021-03-04 13:21:01.470839054 +0100 @@ -188,6 +188,14 @@ range.flags = NF_NAT_RANGE_MAP_IPS; range.min_addr = range.max_addr = ct->master->tuplehash[!exp->dir].tuple.dst.u3; + + if (ct->master->nat_src_proto_min.all && + ct->master->nat_src_proto_max.all) { + range.flags |= NF_NAT_RANGE_PROTO_SPECIFIED; + range.min_proto = ct->master->nat_src_proto_min; + range.max_proto = ct->master->nat_src_proto_max; + } + nf_nat_setup_info(ct, &range, NF_NAT_MANIP_SRC); /* For DST manip, map port here to where it's expected. */ diff -ruw linux-5.4.60/net/netfilter/nf_nat_proto.c linux-5.4.60-fbx/net/netfilter/nf_nat_proto.c --- linux-5.4.60/net/netfilter/nf_nat_proto.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_nat_proto.c 2021-03-04 13:21:01.470839054 +0100 @@ -385,6 +385,8 @@ { #if IS_ENABLED(CONFIG_IPV6) struct ipv6hdr *ipv6h; + const __be32 *to; + __be32 *from; __be16 frag_off; int hdroff; u8 nexthdr; @@ -407,10 +409,24 @@ ipv6h = (void *)skb->data + iphdroff; manip_addr: - if (maniptype == NF_NAT_MANIP_SRC) - ipv6h->saddr = target->src.u3.in6; - else - ipv6h->daddr = target->dst.u3.in6; + if (maniptype == NF_NAT_MANIP_SRC) { + from = ipv6h->saddr.s6_addr32; + to = target->src.u3.in6.s6_addr32; + } else { + from = ipv6h->daddr.s6_addr32; + to = target->dst.u3.in6.s6_addr32; + } + + if (skb->ip_summed == CHECKSUM_COMPLETE) { + __be32 diff[] = { + ~from[0], ~from[1], ~from[2], ~from[3], + to[0], to[1], to[2], to[3], + }; + + skb->csum = ~csum_partial(diff, sizeof(diff), ~skb->csum); + } + + memcpy(from, to, sizeof (struct in6_addr)); #endif return true; diff -ruw linux-5.4.60/net/netfilter/nf_nat_sip.c linux-5.4.60-fbx/net/netfilter/nf_nat_sip.c --- linux-5.4.60/net/netfilter/nf_nat_sip.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/netfilter/nf_nat_sip.c 2021-03-04 13:21:01.470839054 +0100 @@ -365,6 +365,15 @@ range_set_for_snat = 1; } + if (range_set_for_snat) { + if (ct->master->nat_src_proto_min.all && + ct->master->nat_src_proto_max.all) { + range.flags |= NF_NAT_RANGE_PROTO_SPECIFIED; + range.min_proto = ct->master->nat_src_proto_min; + range.max_proto = ct->master->nat_src_proto_max; + } + } + /* Perform SRC manip. */ if (range_set_for_snat) nf_nat_setup_info(ct, &range, NF_NAT_MANIP_SRC); @@ -382,10 +391,11 @@ enum ip_conntrack_dir dir = CTINFO2DIR(ctinfo); struct nf_ct_sip_master *ct_sip_info = nfct_help_data(ct); union nf_inet_addr newaddr; - u_int16_t port; + u_int16_t port, sport, eport; __be16 srcport; char buffer[INET6_ADDRSTRLEN + sizeof("[]:nnnnn")]; unsigned int buflen; + unsigned int i; /* Connection will come from reply */ if (nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.src.u3, @@ -410,7 +420,24 @@ exp->dir = !dir; exp->expectfn = nf_nat_sip_expected; - for (; port != 0; port++) { + if (dir == IP_CT_DIR_ORIGINAL && + (ct->status & IPS_SRC_NAT) && + ct->nat_src_proto_min.all && + ct->nat_src_proto_max.all) { + sport = ntohs(ct->nat_src_proto_min.all); + eport = ntohs(ct->nat_src_proto_max.all); + } else { + sport = 1024; + eport = 65535; + } + + if (port < sport || port > eport) { + get_random_bytes(&port, sizeof (port)); + port %= eport - sport; + port += sport; + } + + for (i = 0; i < eport - sport + 1; i++) { int ret; exp->tuple.dst.u.udp.port = htons(port); @@ -421,6 +448,10 @@ port = 0; break; } + + port++; + if (port > eport) + port = sport; } if (port == 0) { @@ -580,7 +611,8 @@ enum ip_conntrack_info ctinfo; struct nf_conn *ct = nf_ct_get(skb, &ctinfo); enum ip_conntrack_dir dir = CTINFO2DIR(ctinfo); - u_int16_t port; + u_int16_t port, sport, eport; + unsigned int i; /* Connection will come from reply */ if (nf_inet_addr_cmp(&ct->tuplehash[dir].tuple.src.u3, @@ -601,17 +633,37 @@ rtcp_exp->dir = !dir; rtcp_exp->expectfn = nf_nat_sip_expected; + if (dir == IP_CT_DIR_ORIGINAL && + (ct->status & IPS_SRC_NAT) && + ct->nat_src_proto_min.all && + ct->nat_src_proto_max.all) { + sport = ntohs(ct->nat_src_proto_min.all); + eport = ntohs(ct->nat_src_proto_max.all); + } else { + sport = 1024; + eport = 65535; + } + + port = ntohs(rtp_exp->tuple.dst.u.udp.port); + if (port < sport || port > eport - 1) { + get_random_bytes(&port, sizeof (port)); + port %= eport - sport; + port += sport; + } + /* Try to get same pair of ports: if not, try to change them. */ - for (port = ntohs(rtp_exp->tuple.dst.u.udp.port); - port != 0; port += 2) { + for (i = 0; i < eport - sport + 1; i += 2) { int ret; rtp_exp->tuple.dst.u.udp.port = htons(port); ret = nf_ct_expect_related(rtp_exp, NF_CT_EXP_F_SKIP_MASTER); - if (ret == -EBUSY) + if (ret == -EBUSY) { + port += 2; + if (port > eport) + port = sport; continue; - else if (ret < 0) { + } else if (ret < 0) { port = 0; break; } @@ -622,12 +674,19 @@ break; else if (ret == -EBUSY) { nf_ct_unexpect_related(rtp_exp); + port += 2; + if (port > eport) + port = sport; continue; } else if (ret < 0) { nf_ct_unexpect_related(rtp_exp); port = 0; break; } + + port += 2; + if (port > eport) + port = sport; } if (port == 0) { diff -ruw linux-5.4.60/net/sched/sch_drr.c linux-5.4.60-fbx/net/sched/sch_drr.c --- linux-5.4.60/net/sched/sch_drr.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/sched/sch_drr.c 2021-03-04 13:21:01.500839054 +0100 @@ -334,7 +334,9 @@ cl = drr_find_class(sch, res.classid); return cl; } - return NULL; + + /* default to first minor if it exists, or drop */ + return drr_find_class(sch, TC_H_MAKE(TC_H_MAJ(sch->handle), 1)); } static int drr_enqueue(struct sk_buff *skb, struct Qdisc *sch, diff -ruw linux-5.4.60/net/socket.c linux-5.4.60-fbx/net/socket.c --- linux-5.4.60/net/socket.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/socket.c 2021-03-04 13:21:01.514172389 +0100 @@ -1066,6 +1066,29 @@ return err; } +static DEFINE_MUTEX(fbxbridge_ioctl_mutex); +static int (*fbxbridge_ioctl_hook)(struct net *, unsigned int cmd, void __user *arg) = NULL; + +void fbxbridge_set(int (*hook)(struct net *, unsigned int, void __user *)) +{ + mutex_lock(&fbxbridge_ioctl_mutex); + fbxbridge_ioctl_hook = hook; + mutex_unlock(&fbxbridge_ioctl_mutex); +} + +static DEFINE_MUTEX(fbxdiverter_ioctl_mutex); +static int (*fbxdiverter_ioctl_hook) (struct net *, unsigned int cmd, void __user *arg) = NULL; + +void fbxdiverter_ioctl_set(int (*hook) (struct net *, unsigned int, + void __user *)) +{ + mutex_lock(&fbxdiverter_ioctl_mutex); + fbxdiverter_ioctl_hook = hook; + mutex_unlock(&fbxdiverter_ioctl_mutex); +} + +EXPORT_SYMBOL(fbxdiverter_ioctl_set); + /* * With an ioctl, arg may well be a user mode pointer, but we don't know * what to do with it - that's up to the protocol still. @@ -1165,6 +1188,17 @@ err = open_related_ns(&net->ns, get_net_ns); break; + case SIOCGFBXDIVERT: + case SIOCSFBXDIVERT: + err = -ENOPKG; + if (!fbxdiverter_ioctl_hook) + request_module("fbxdiverter"); + + mutex_lock(&fbxdiverter_ioctl_mutex); + if (fbxdiverter_ioctl_hook) + err = fbxdiverter_ioctl_hook(net, cmd, argp); + mutex_unlock(&fbxdiverter_ioctl_mutex); + break; case SIOCGSTAMP_OLD: case SIOCGSTAMPNS_OLD: if (!sock->ops->gettstamp) { @@ -1185,6 +1219,17 @@ cmd == SIOCGSTAMP_NEW, false); break; + case SIOCGFBXBRIDGE: + case SIOCSFBXBRIDGE: + err = -ENOPKG; + if (!fbxbridge_ioctl_hook) + request_module("fbxbridge"); + + mutex_lock(&fbxbridge_ioctl_mutex); + if (fbxbridge_ioctl_hook) + err = fbxbridge_ioctl_hook(net, cmd, argp); + mutex_unlock(&fbxbridge_ioctl_mutex); + break; default: err = sock_do_ioctl(net, sock, cmd, arg); break; diff -ruw linux-5.4.60/net/unix/af_unix.c linux-5.4.60-fbx/net/unix/af_unix.c --- linux-5.4.60/net/unix/af_unix.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/unix/af_unix.c 2021-03-04 13:21:01.524172389 +0100 @@ -279,8 +279,10 @@ sk_for_each(s, &unix_socket_table[hash ^ type]) { struct unix_sock *u = unix_sk(s); +#ifdef UNIX_ABSTRACT_IGNORE_NETNS if (!net_eq(sock_net(s), net)) continue; +#endif if (u->addr->len == len && !memcmp(u->addr->name, sunname, len)) diff -ruw linux-5.4.60/net/unix/Kconfig linux-5.4.60-fbx/net/unix/Kconfig --- linux-5.4.60/net/unix/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/unix/Kconfig 2021-03-04 13:21:01.524172389 +0100 @@ -25,6 +25,9 @@ depends on UNIX default y +config UNIX_ABSTRACT_IGNORE_NETNS + bool "make abstract namespace global to all network namespaces" + config UNIX_DIAG tristate "UNIX: socket monitoring interface" depends on UNIX diff -ruw linux-5.4.60/net/wireless/core.h linux-5.4.60-fbx/net/wireless/core.h --- linux-5.4.60/net/wireless/core.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/wireless/core.h 2021-03-04 13:21:01.527505723 +0100 @@ -331,6 +331,12 @@ struct net_device *dev, struct mesh_setup *setup, const struct mesh_config *conf); +int cfg80211_update_mesh_vendor_node_metrics_ie(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct mesh_vendor_ie *vendor_ie); +int cfg80211_update_mesh_vendor_path_metrics_ie(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct mesh_vendor_ie *vendor_ie); int __cfg80211_leave_mesh(struct cfg80211_registered_device *rdev, struct net_device *dev); int cfg80211_leave_mesh(struct cfg80211_registered_device *rdev, diff -ruw linux-5.4.60/net/wireless/mesh.c linux-5.4.60-fbx/net/wireless/mesh.c --- linux-5.4.60/net/wireless/mesh.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/wireless/mesh.c 2021-03-04 13:21:01.527505723 +0100 @@ -217,6 +217,34 @@ return err; } +int cfg80211_update_mesh_vendor_node_metrics_ie(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct mesh_vendor_ie *vendor_ie) +{ + struct wireless_dev *wdev = dev->ieee80211_ptr; + int err; + + wdev_lock(wdev); + err = rdev_update_mesh_vendor_node_metrics_ie(rdev, dev, vendor_ie); + wdev_unlock(wdev); + + return err; +} + +int cfg80211_update_mesh_vendor_path_metrics_ie(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct mesh_vendor_ie *vendor_ie) +{ + struct wireless_dev *wdev = dev->ieee80211_ptr; + int err; + + wdev_lock(wdev); + err = rdev_update_mesh_vendor_path_metrics_ie(rdev, dev, vendor_ie); + wdev_unlock(wdev); + + return err; +} + int cfg80211_set_mesh_channel(struct cfg80211_registered_device *rdev, struct wireless_dev *wdev, struct cfg80211_chan_def *chandef) diff -ruw linux-5.4.60/net/wireless/nl80211.c linux-5.4.60-fbx/net/wireless/nl80211.c --- linux-5.4.60/net/wireless/nl80211.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/wireless/nl80211.c 2021-03-04 13:21:01.530839056 +0100 @@ -6407,6 +6407,51 @@ return err; } +static int nl80211_set_mpp(struct sk_buff *skb, struct genl_info *info) +{ + struct cfg80211_registered_device *rdev = info->user_ptr[0]; + struct net_device *dev = info->user_ptr[1]; + u8 *dst = NULL; + u8 *next_hop = NULL; + + if (!info->attrs[NL80211_ATTR_MAC]) + return -EINVAL; + + if (!info->attrs[NL80211_ATTR_MPATH_NEXT_HOP]) + return -EINVAL; + + dst = nla_data(info->attrs[NL80211_ATTR_MAC]); + next_hop = nla_data(info->attrs[NL80211_ATTR_MPATH_NEXT_HOP]); + + if (!rdev->ops->update_mpp) + return -EOPNOTSUPP; + + if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_MESH_POINT) + return -EOPNOTSUPP; + + return rdev_update_mpp(rdev, dev, dst, next_hop); +} + +static int nl80211_del_mpp(struct sk_buff *skb, struct genl_info *info) +{ + struct cfg80211_registered_device *rdev = info->user_ptr[0]; + struct net_device *dev = info->user_ptr[1]; + u8 *dst; + + if (!info->attrs[NL80211_ATTR_MAC]) + return -EINVAL; + + if (!rdev->ops->delete_mpp) + return -EOPNOTSUPP; + + if (dev->ieee80211_ptr->iftype != NL80211_IFTYPE_MESH_POINT) + return -EOPNOTSUPP; + + dst = nla_data(info->attrs[NL80211_ATTR_MAC]); + + return rdev_delete_mpp(rdev, dev, dst); +} + static int nl80211_set_bss(struct sk_buff *skb, struct genl_info *info) { struct cfg80211_registered_device *rdev = info->user_ptr[0]; @@ -12906,8 +12951,30 @@ struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct wireless_dev *wdev = __cfg80211_wdev_from_attrs(genl_info_net(info), info->attrs); - int i, err; + int i, err = 0; u32 vid, subcmd; + struct net_device *dev = wdev->netdev; + struct mesh_vendor_ie mv_ie; + struct nlattr *ieattr; + u8 type; + + + if (wdev->iftype == NL80211_IFTYPE_MESH_POINT) { + if (info->attrs[NL80211_ATTR_VENDOR_DATA] && + info->attrs[NL80211_ATTR_VENDOR_SUBCMD]) { + if (!info->attrs[NL80211_ATTR_VENDOR_DATA]) + return -EINVAL; + ieattr = info->attrs[NL80211_ATTR_VENDOR_DATA]; + mv_ie.ie = nla_data(ieattr); + mv_ie.ie_len = nla_len(ieattr); + type = nla_get_u32(info->attrs[NL80211_ATTR_VENDOR_SUBCMD]); + if (type == NL80211_QBC_UPDATE_NODE_METRICS_IE) + err = cfg80211_update_mesh_vendor_node_metrics_ie(rdev, dev, &mv_ie); + else if (type == NL80211_QBC_UPDATE_PATH_METRICS_IE) + err = cfg80211_update_mesh_vendor_path_metrics_ie(rdev, dev, &mv_ie); + return err; + } + } if (!rdev->wiphy.vendor_commands) return -EOPNOTSUPP; @@ -14085,6 +14152,20 @@ NL80211_FLAG_NEED_RTNL, }, { + .cmd = NL80211_CMD_SET_MPP, + .doit = nl80211_set_mpp, + .flags = GENL_UNS_ADMIN_PERM, + .internal_flags = NL80211_FLAG_NEED_NETDEV_UP | + NL80211_FLAG_NEED_RTNL, + }, + { + .cmd = NL80211_CMD_DEL_MPP, + .doit = nl80211_del_mpp, + .flags = GENL_UNS_ADMIN_PERM, + .internal_flags = NL80211_FLAG_NEED_NETDEV_UP | + NL80211_FLAG_NEED_RTNL, + }, + { .cmd = NL80211_CMD_SET_BSS, .validate = GENL_DONT_VALIDATE_STRICT | GENL_DONT_VALIDATE_DUMP, .doit = nl80211_set_bss, @@ -15473,6 +15554,94 @@ } EXPORT_SYMBOL(cfg80211_notify_new_peer_candidate); +void cfg80211_notify_mesh_peer_path_metrics(struct net_device *dev, const u8 *macaddr, + const u8 *ie, u8 ie_len, gfp_t gfp) +{ + struct wireless_dev *wdev = dev->ieee80211_ptr; + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); + struct sk_buff *msg; + void *hdr; + + if (WARN_ON(wdev->iftype != NL80211_IFTYPE_MESH_POINT)) + return; + + msg = nlmsg_new(100 + ie_len, gfp); + if (!msg) + return; + + hdr = nl80211hdr_put(msg, 0, 0, 0, NL80211_CMD_MESH_PEER_PATH_METRICS); + if (!hdr) { + nlmsg_free(msg); + return; + } + + if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) || + nla_put_string(msg, NL80211_ATTR_IFNAME, dev->name) || + nla_put_u32(msg, NL80211_ATTR_IFINDEX, dev->ifindex) || + nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, macaddr) || + (ie_len && ie && + nla_put(msg, NL80211_ATTR_IE, ie_len , ie))) + goto nla_put_failure; + + genlmsg_end(msg, hdr); + + genlmsg_multicast_netns(&nl80211_fam, wiphy_net(&rdev->wiphy), msg, 0, + NL80211_MCGRP_MLME, gfp); + return; + + nla_put_failure: + genlmsg_cancel(msg, hdr); + nlmsg_free(msg); +} +EXPORT_SYMBOL(cfg80211_notify_mesh_peer_path_metrics); + + +void cfg80211_notify_mesh_peer_node_metrics(struct net_device *dev, + const u8 *macaddr, u16 stype, s8 signal, + u32 beacon_int, const u8 *ie, u8 ie_len, gfp_t gfp) +{ + struct wireless_dev *wdev = dev->ieee80211_ptr; + struct cfg80211_registered_device *rdev = wiphy_to_rdev(wdev->wiphy); + struct sk_buff *msg; + void *hdr; + + if (WARN_ON(wdev->iftype != NL80211_IFTYPE_MESH_POINT)) + return; + + msg = nlmsg_new(100 + ie_len, gfp); + if (!msg) + return; + + hdr = nl80211hdr_put(msg, 0, 0, 0, NL80211_CMD_MESH_PEER_NODE_METRICS); + if (!hdr) { + nlmsg_free(msg); + return; + } + + if (nla_put_u32(msg, NL80211_ATTR_WIPHY, rdev->wiphy_idx) || + nla_put_string(msg, NL80211_ATTR_IFNAME, dev->name) || + nla_put_u32(msg, NL80211_ATTR_IFINDEX, dev->ifindex) || + nla_put(msg, NL80211_ATTR_MAC, ETH_ALEN, macaddr) || + nla_put_u16(msg, NL80211_ATTR_FRAME_TYPE, stype) || + nla_put_s8(msg, NL80211_ATTR_SIGNAL_STRENGTH, signal) || + nla_put_u32(msg, NL80211_ATTR_BEACON_INTERVAL, beacon_int) || + (ie_len && ie && + nla_put(msg, NL80211_ATTR_IE, ie_len , ie))) + goto nla_put_failure; + + genlmsg_end(msg, hdr); + + genlmsg_multicast_netns(&nl80211_fam, wiphy_net(&rdev->wiphy), msg, 0, + NL80211_MCGRP_MLME, gfp); + return; + + nla_put_failure: + genlmsg_cancel(msg, hdr); + nlmsg_free(msg); +} +EXPORT_SYMBOL(cfg80211_notify_mesh_peer_node_metrics); + + void nl80211_michael_mic_failure(struct cfg80211_registered_device *rdev, struct net_device *netdev, const u8 *addr, enum nl80211_key_type key_type, int key_id, diff -ruw linux-5.4.60/net/wireless/rdev-ops.h linux-5.4.60-fbx/net/wireless/rdev-ops.h --- linux-5.4.60/net/wireless/rdev-ops.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/wireless/rdev-ops.h 2021-03-04 13:21:01.530839056 +0100 @@ -278,6 +278,28 @@ return ret; } +static inline int rdev_update_mpp(struct cfg80211_registered_device *rdev, + struct net_device *dev, u8 *dst, u8 *next_hop) +{ + int ret; + + trace_rdev_update_mpp(&rdev->wiphy, dev, dst, next_hop); + ret = rdev->ops->update_mpp(&rdev->wiphy, dev, dst, next_hop); + trace_rdev_return_int(&rdev->wiphy, ret); + return ret; +} + +static inline int rdev_delete_mpp(struct cfg80211_registered_device *rdev, + struct net_device *dev, u8 *dst) +{ + int ret; + + trace_rdev_delete_mpp(&rdev->wiphy, dev, dst); + ret = rdev->ops->delete_mpp(&rdev->wiphy, dev, dst); + trace_rdev_return_int(&rdev->wiphy, ret); + return ret; +} + static inline int rdev_dump_mpath(struct cfg80211_registered_device *rdev, struct net_device *dev, int idx, u8 *dst, u8 *next_hop, struct mpath_info *pinfo) @@ -339,6 +361,23 @@ return ret; } +static inline int rdev_update_mesh_vendor_node_metrics_ie(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct mesh_vendor_ie *ie) +{ + int ret; + ret = rdev->ops->update_mesh_vendor_node_metrics_ie(&rdev->wiphy, dev, ie); + return ret; +} + +static inline int rdev_update_mesh_vendor_path_metrics_ie(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct mesh_vendor_ie *ie) +{ + int ret; + ret = rdev->ops->update_mesh_vendor_path_metrics_ie(&rdev->wiphy, dev, ie); + return ret; +} static inline int rdev_leave_mesh(struct cfg80211_registered_device *rdev, struct net_device *dev) diff -ruw linux-5.4.60/net/wireless/reg.c linux-5.4.60-fbx/net/wireless/reg.c --- linux-5.4.60/net/wireless/reg.c 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/wireless/reg.c 2021-03-04 13:21:01.530839056 +0100 @@ -1761,6 +1761,9 @@ if (chan->flags & IEEE80211_CHAN_RADAR) { chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS; + if (chan->center_freq >= 5600 && + chan->center_freq <= 5650) + chan->dfs_cac_ms = IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS; if (reg_rule->dfs_cac_ms) chan->dfs_cac_ms = reg_rule->dfs_cac_ms; } @@ -1781,9 +1784,14 @@ if (chan->flags & IEEE80211_CHAN_RADAR) { if (reg_rule->dfs_cac_ms) chan->dfs_cac_ms = reg_rule->dfs_cac_ms; + else { + if (chan->center_freq >= 5600 && + chan->center_freq <= 5650) + chan->dfs_cac_ms = IEEE80211_DFS_WEATHER_MIN_CAC_TIME_MS; else chan->dfs_cac_ms = IEEE80211_DFS_MIN_CAC_TIME_MS; } + } if (chan->orig_mpwr) { /* diff -ruw linux-5.4.60/net/wireless/trace.h linux-5.4.60-fbx/net/wireless/trace.h --- linux-5.4.60/net/wireless/trace.h 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/net/wireless/trace.h 2021-03-04 13:21:01.534172390 +0100 @@ -813,6 +813,11 @@ TP_ARGS(wiphy, netdev, mac) ); +DEFINE_EVENT(wiphy_netdev_mac_evt, rdev_delete_mpp, + TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, const u8 *mac), + TP_ARGS(wiphy, netdev, mac) +); + TRACE_EVENT(rdev_dump_station, TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, int _idx, u8 *mac), @@ -888,6 +893,12 @@ TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, u8 *dst, u8 *next_hop), TP_ARGS(wiphy, netdev, dst, next_hop) +); + +DEFINE_EVENT(mpath_evt, rdev_update_mpp, + TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, u8 *dst, + u8 *next_hop), + TP_ARGS(wiphy, netdev, dst, next_hop) ); TRACE_EVENT(rdev_dump_mpath, diff -ruw linux-5.4.60/scripts/dtc/include-prefixes/arm64/amlogic/Makefile linux-5.4.60-fbx/scripts/dtc/include-prefixes/arm64/amlogic/Makefile --- linux-5.4.60/scripts/dtc/include-prefixes/arm64/amlogic/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/scripts/dtc/include-prefixes/arm64/amlogic/Makefile 2021-03-04 13:20:57.000838854 +0100 @@ -1,4 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 +DTC_FLAGS += -@ +dtb-$(CONFIG_ARCH_MESON) += fbxwmr.dtb fbxwmr-r1.dtb fbxwmr-r2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb diff -ruw linux-5.4.60/scripts/dtc/include-prefixes/arm64/broadcom/Makefile linux-5.4.60-fbx/scripts/dtc/include-prefixes/arm64/broadcom/Makefile --- linux-5.4.60/scripts/dtc/include-prefixes/arm64/broadcom/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/scripts/dtc/include-prefixes/arm64/broadcom/Makefile 2021-03-04 13:20:57.004172187 +0100 @@ -6,3 +6,4 @@ subdir-y += northstar2 subdir-y += stingray +subdir-y += bcm63xx diff -ruw linux-5.4.60/scripts/dtc/include-prefixes/arm64/marvell/Makefile linux-5.4.60-fbx/scripts/dtc/include-prefixes/arm64/marvell/Makefile --- linux-5.4.60/scripts/dtc/include-prefixes/arm64/marvell/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/scripts/dtc/include-prefixes/arm64/marvell/Makefile 2021-03-04 13:20:57.010838855 +0100 @@ -10,3 +10,17 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_dsl_lte.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_ftth_pon.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp1_test_module.dtb +dtb-$(CONFIG_ARCH_MVEBU) += fbxgw7r_exp2_test_module.dtb + +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp1_ftth_p2p.dtb +dtb-$(CONFIG_ARCH_MVEBU) += jbxgw7r_exp2_ftth_p2p.dtb + +# export symbols in DTBs file to allow overlay usage +DTC_FLAGS += -@ diff -ruw linux-5.4.60/scripts/Makefile.build linux-5.4.60-fbx/scripts/Makefile.build --- linux-5.4.60/scripts/Makefile.build 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/scripts/Makefile.build 2021-03-04 13:21:01.547505724 +0100 @@ -431,7 +431,7 @@ # module is turned into a multi object module, $^ will contain header file # dependencies recorded in the .*.cmd file. quiet_cmd_link_multi-m = LD [M] $@ - cmd_link_multi-m = $(LD) $(ld_flags) -r -o $@ $(filter %.o,$^) + cmd_link_multi-m = $(LD) $(ld_flags) -r -o $@ $(filter %.o %.a,$^) $(multi-used-m): FORCE $(call if_changed,link_multi-m) diff -ruw linux-5.4.60/scripts/Makefile.lib linux-5.4.60-fbx/scripts/Makefile.lib --- linux-5.4.60/scripts/Makefile.lib 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/scripts/Makefile.lib 2021-03-04 13:21:01.547505724 +0100 @@ -256,11 +256,11 @@ DTC_FLAGS += $(DTC_FLAGS_$(basetarget)) # Generate an assembly file to wrap the output of the device tree compiler -quiet_cmd_dt_S_dtb= DTB $@ +quiet_cmd_dt_S_dtb= DTB_bin $@ cmd_dt_S_dtb= \ { \ echo '\#include '; \ - echo '.section .dtb.init.rodata,"a"'; \ + echo '.section .dtb.rodata,"a"'; \ echo '.balign STRUCT_ALIGNMENT'; \ echo '.global __dtb_$(subst -,_,$(*F))_begin'; \ echo '__dtb_$(subst -,_,$(*F))_begin:'; \ @@ -273,6 +273,8 @@ $(obj)/%.dtb.S: $(obj)/%.dtb FORCE $(call if_changed,dt_S_dtb) +.PRECIOUS: $(src)/%.dtb.S + quiet_cmd_dtc = DTC $@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ diff -ruw linux-5.4.60/sound/soc/kirkwood/Kconfig linux-5.4.60-fbx/sound/soc/kirkwood/Kconfig --- linux-5.4.60/sound/soc/kirkwood/Kconfig 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/sound/soc/kirkwood/Kconfig 2021-03-04 13:21:01.724172398 +0100 @@ -16,3 +16,8 @@ Say Y if you want to add support for SoC audio on the Armada 370 Development Board. +config SND_KIRKWOOD_SOC_FBXGW2R + tristate "Soc Audio support for fbxgw2r" + depends on SND_KIRKWOOD_SOC && MACH_FBXGW2R && I2C + select SND_KIRKWOOD_SOC_I2S + select SND_SOC_CS42L52 diff -ruw linux-5.4.60/sound/soc/kirkwood/Makefile linux-5.4.60-fbx/sound/soc/kirkwood/Makefile --- linux-5.4.60/sound/soc/kirkwood/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/sound/soc/kirkwood/Makefile 2021-03-04 13:21:01.724172398 +0100 @@ -6,3 +6,6 @@ snd-soc-armada-370-db-objs := armada-370-db.o obj-$(CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB) += snd-soc-armada-370-db.o + +snd-soc-fbxgw2r-objs := kirkwood-fbxgw2r.o +obj-$(CONFIG_SND_KIRKWOOD_SOC_FBXGW2R) += snd-soc-fbxgw2r.o diff -ruw linux-5.4.60/usr/Makefile linux-5.4.60-fbx/usr/Makefile --- linux-5.4.60/usr/Makefile 2020-08-21 13:05:39.000000000 +0200 +++ linux-5.4.60-fbx/usr/Makefile 2021-03-04 13:21:01.924172407 +0100 @@ -27,7 +27,7 @@ # Generate the initramfs cpio archive hostprogs-y := gen_init_cpio -initramfs := $(CONFIG_SHELL) $(srctree)/$(src)/gen_initramfs_list.sh +initramfs := $(BASH) $(srctree)/$(src)/gen_initramfs_list.sh ramfs-input := $(if $(filter-out "",$(CONFIG_INITRAMFS_SOURCE)), \ $(shell echo $(CONFIG_INITRAMFS_SOURCE)),-d) ramfs-args := \ diff -Nruw linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm63158.dtsi linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm63158.dtsi --- linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm63158.dtsi 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm63158.dtsi 2021-03-04 13:20:57.004172187 +0100 @@ -0,0 +1,1072 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define USE_PSCI // comment when booting on broadcom CFE. + +#define SDIO_EMMC_SPI 95 +#define SPU_GMAC_SPI 75 +#define HS_SPI_SPI 37 +#define BSC_I2C0_SPI 82 +#define BSC_I2C1_SPI 83 +#define PCIE0_SPI 60 +#define PCIE1_SPI 61 +#define PCIE2_SPI 62 +#define PCIE3_SPI 63 +#define HS_UART_SPI 34 +#define XHCI_SPI 123 +#define OHCI0_SPI 124 +#define EHCI0_SPI 125 +#define OHCI1_SPI 121 +#define EHCI1_SPI 122 + +#define DRAM_BASE 0x0 +#define DRAM_DEF_SIZE 0x08000000 + +/dts-v1/; + +/memreserve/ 0x00000000 0x00020000; + +/ { + model = "Broadcom-v8A"; + compatible = "brcm,brcm-v8A"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + +#ifdef USE_PSCI + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; +#define CPU_ENABLE_METHOD "psci" +#else +#define CPU_ENABLE_METHOD "spin-table" +#endif + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + B53_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + next-level-cache = <&L2_0>; + }; + B53_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = CPU_ENABLE_METHOD; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&L2_0>; + }; + B53_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = CPU_ENABLE_METHOD; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&L2_0>; + }; + B53_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = CPU_ENABLE_METHOD; + cpu-release-addr = <0x0 0xfff8>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&B53_0>, + <&B53_1>, + <&B53_2>, + <&B53_3>; + }; + + soc_dram: memory@00000000 { + device_type = "memory"; + reg = <0x00000000 DRAM_BASE 0x0 DRAM_DEF_SIZE>; + + // this is overwritten by bootloader with correct value + brcm,ddr-mcb = <0x4142b>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secureos@0x10000000 { + no-map; + reg = <0x0 0x10000000 0x0 0x01000000>; + }; + optee-shared-area@0x11000000 { + no-map; + reg = <0x0 0x11000000 0x0 0x00800000>; + }; + dsl_reserved: dsl_reserved { + compatible = "shared-dma-pool"; + /* + * only 3MB are actually used, but because of pointer alignment + * arithmetics done by the driver, they need to be at the end of an + * 8MB aligned region, must be at an address lower than 256M too + */ + size = <0x0 0x00800000>; + alignment = <0x0 0x00800000>; + alloc-ranges = <0x0 0x0 0x0 0x10000000>; + no-map; + no-cache; + }; + rdp_reserved_tm: rdp_reserved_tm { + compatible = "shared-dma-pool"; + size = <0x0 0x00800000>; + alloc-ranges = <0x0 0x0 0x0 0x10000000>; + no-map; + no-cache; + }; + }; + + uartclk: uartclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + spiclk: spiclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <(200 * 1000 * 1000)>; + }; + + pcie01: pcidual@80040000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80040000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xC0000000 0 0xC0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE01>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE0>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE0_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <2>; + brcm,dram = <&soc_dram>; + }; + + pcie0: pci@80040000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80040000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xC0000000 0 0xC0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE0>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE0>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE0_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + brcm,dram = <&soc_dram>; + }; + + pcie1: pci@80050000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80050000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xD0000000 0 0xD0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE1>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE0>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE1_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + brcm,dram = <&soc_dram>; + }; + + pcie2: pci@80060000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80060000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xE0000000 0 0xE0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE2>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE2>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE2_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + brcm,dram = <&soc_dram>; + }; + + pcie3: pci@80070000 { + status = "disabled"; + device_type = "pci"; + compatible = "brcm,bcm63xx-pcie"; + reg = <0x0 0x80070000 0x0 0xa000>; + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0xB0000000 0 0xB0000000 0 0x10000000>; + bus-range = <0x0 0xff>; + + resets = <&pmc PMC_R_PCIE3>; + reset-names = "pcie0"; + + ubus = <&ubus4 UBUS_PORT_ID_PCIE3>; + procmon = <&procmon RCAL_1UM_VERT>; + + interrupt-names = "intr"; + interrupts = ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI PCIE3_SPI IRQ_TYPE_LEVEL_HIGH>; + + brcm,num-lanes = <1>; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0x80000000 0x0 0x04000000>; + + xtm: xtm@80130000 { + compatible = "brcm,bcm63158-xtm"; + status = "disabled"; + + interrupts = ; + reg = <0x0 0x130000 0x0 0x4000>; + + xdsl-phy = <&xdsl_phy>; + xtm-runner,xrdp = <&xrdp>; + }; + + memc: memc@0x80180000 { + compatible = "brcm,bcm63158-memc"; + reg = <0x0 0x180000 0x0 0x40000>; + }; + + pmc: pmc@80200000 { + compatible = "brcm,bcm63158-pmc"; + reg = <0x0 0x200000 0x0 0x10000>; + #reset-cells = <1>; + }; + + procmon: procmon@80280000 { + compatible = "brcm,bcm63158-procmon"; + reg = <0x0 0x280000 0x0 0x100>; + #procmon-cells = <1>; + }; + + ubus4: ubus4@80300000 { + compatible = "brcm,bcm63158-ubus4"; + reg = <0x0 0x03000000 0x0 0x00500000>, + <0x0 0x10a0400 0x0 0x400>; + reg-names = "master-config", "coherency-config"; + #ubus-cells = <1>; + brcm,dram = <&soc_dram>; + }; + + sf2: sf2@80400000 { + compatible = "brcm,bcm63158-sf2"; + reg = <0x0 0x400000 0x0 0x80000>, + <0x0 0x480000 0x0 0x500>, + <0x0 0x4805c0 0x0 0x10>, + <0x0 0x480600 0x0 0x200>, + <0x0 0x480800 0x0 0x500>; + reg-names = "core", "reg", "mdio", "fcb", "acb"; + resets = <&pmc PMC_R_SF2>; + reset-names = "sf2"; + status = "disabled"; + + sf2,qphy-base-id = <1>; + sf2,sphy-phy-id = <5>; + sf2,serdes-phy-id = <6>; + + leds-top = <&leds_top_syscon>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + sf2_port0: port@0 { + // this is a normal port + reg = <0>; + status = "disabled"; + phy-handle = <&sf2_qphy0>; + phy-connection-type = "gmii"; + }; + + sf2_port1: port@1 { + // this is a normal port + reg = <1>; + status = "disabled"; + phy-handle = <&sf2_qphy1>; + phy-connection-type = "gmii"; + }; + + sf2_port2: port@2 { + // this is a normal port + reg = <2>; + status = "disabled"; + phy-handle = <&sf2_qphy2>; + phy-connection-type = "gmii"; + }; + + sf2_port3: port@3 { + // this is a normal port + reg = <3>; + status = "disabled"; + /* 0: quad phy3, 1: rgmii2 */ + mux1-in-port = <0>; + phy-handle = <&sf2_qphy3>; + phy-connection-type = "gmii"; + }; + + sf2_port4: port@4 { + // this is a normal port + reg = <4>; + status = "disabled"; + /* default config is xbar to sphy */ + xbar-in-port = <2>; + phy-handle = <&sf2_sphy>; + phy-connection-type = "gmii"; + }; + + sf2_port5: port@5 { + // this is a CPU port + reg = <5>; + status = "disabled"; + phy-connection-type = "internal"; + ethernet = <&runner_unimac1>; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + sf2_port6: port@6 { + // this is a normal port + reg = <6>; + status = "disabled"; + xbar-in-port = <1>; + /* default config is xbar to serdes */ + phy-connection-type = "sgmii"; + }; + + sf2_port7: port@7 { + // this is a CPU port + reg = <7>; + status = "disabled"; + ethernet = <&runner_unimac2>; + phy-connection-type = "internal"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + sf2_port8: port@8 { + // this is a CPU port + reg = <8>; + status = "disabled"; + /* 0: system port, 1: unimac bbh */ + mux2-in-port = <1>; + + dsa,def-cpu-port; + //ethernet = <&systemport>; + ethernet = <&runner_unimac0>; + + phy-connection-type = "internal"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + }; + + sf2,wan-port-config { + status = "disabled"; + xbar-in-port = <0>; + }; + + sf2,mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* XXX: depends on sf2,qphy-base-id */ + sf2_qphy0: ethernetphy@1 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <1>; + }; + sf2_qphy1: ethernet-phy@2 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <2>; + }; + sf2_qphy2: ethernet-phy@3 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <3>; + }; + sf2_qphy3: ethernet-phy@4 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <4>; + }; + /* XXX: depends on sf2,sphy-base-id */ + sf2_sphy: ethernet-phy@5 { + compatible = "ethernet-phy-idae02.51c1", "ethernet-phy-ieee802.3-c22"; + status = "disabled"; + reg = <5>; + }; + }; + }; + + systemport: systemport@80490000 { + compatible = "brcm,systemport-63158"; + reg = <0x0 0x490000 0x0 0x4650>; + local-mac-address = [ 00 07 CB 00 00 FE ]; + interrupts = , + ; + status = "disabled"; + dma-coherent; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + xdsl_phy: xdsl-phy@80650000 { + compatible = "brcm,bcm63158-xdsl-phy"; + status = "disabled"; + + memory-region = <&dsl_reserved>; + interrupts = ; + reg = <0x0 0x650000 0x0 0x20000>, + <0x0 0x800000 0x0 0xe0000>, + <0x0 0x9A0000 0x0 0x660000>; + reg-names = "phy", "lmem", "xmem"; + + pinctrl-0 = <&ld0_pins>; + pinctrl-names = "default"; + + ubus = <&ubus4 UBUS_PORT_ID_DSLCPU>, + <&ubus4 UBUS_PORT_ID_DSL>; + }; + + gic: interrupt-controller@81000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x1001000 0 0x1000>, + <0x0 0x1002000 0 0x2000>; + }; + + usb: usb@8000d000 { + status = "disabled"; + compatible = "brcm,bcm63158-usb"; + + reg = <0x0 0xd000 0x0 0x1000>, + <0x0 0xc200 0x0 0x100>, + <0x0 0xc300 0x0 0x100>, + <0x0 0xc400 0x0 0x100>, + <0x0 0xc500 0x0 0x100>, + <0x0 0xc600 0x0 0x100>; + reg-names = "xhci", "usb-control", "ehci0", + "ohci0", "ehci1", "ohci1"; + dma-coherent; + + interrupts = , + , + , + , + ; + interrupt-names = "xhci", "ehci0", "ohci0", + "ehci1", "ohci1"; + + resets = <&pmc PMC_R_USBH>; + reset-names = "xhci-pmc-reset"; + + ubus = <&ubus4 UBUS_PORT_ID_USB>; + }; + + xrdp: xrdp@82000000 { + compatible = "brcm,bcm63158-xrdp"; + reg = <0x0 0x2000000 0x0 0x1000000>, + <0x0 0x0170000 0x0 0x10000>; + reg-names = "core", "wan_top"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "fpm", + "hash", + "qm", + "dsptchr", + "sbpm", + "runner0", + "runner1", + "runner2", + "runner3", + "runner4", + "runner5", + "queue0", + "queue1", + "queue2", + "queue3", + "queue4", + "queue5", + "queue6", + "queue7", + "queue8", + "queue9", + "queue10", + "queue11", + "queue12", + "queue13", + "queue14", + "queue15", + "queue16", + "queue17", + "queue18", + "queue19", + "queue20", + "queue21", + "queue22", + "queue23", + "queue24", + "queue25", + "queue26", + "queue27", + "queue28", + "queue29", + "queue30", + "queue31"; + + memory-region = <&rdp_reserved_tm>; + resets = <&pmc PMC_R_XRDP>; + reset-names = "rdp"; + ubus = <&ubus4 UBUS_PORT_ID_QM>, + <&ubus4 UBUS_PORT_ID_DQM>, + <&ubus4 UBUS_PORT_ID_NATC>, + <&ubus4 UBUS_PORT_ID_DMA0>, + <&ubus4 UBUS_PORT_ID_RQ0>, + <&ubus4 UBUS_PORT_ID_SWH>; + }; + + runner_unimac0: runner-unimac0 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-unimac"; + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,bbh = <0>; + dma-coherent; + + phy-mode = "gmii"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + runner_unimac1: runner-unimac1 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-unimac"; + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,bbh = <1>; + dma-coherent; + + phy-mode = "gmii"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + runner_unimac2: runner-unimac2 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-unimac"; + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,bbh = <2>; + dma-coherent; + + phy-mode = "gmii"; + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + runner_xport0: runner-xport0 { + status = "disabled"; + compatible = "brcm,bcm63158-enet-runner-xport"; + reg = <0x0 0x00144000 0x0 0x100>, + <0x0 0x00138000 0x0 0x6fff>, + <0x0 0x00147800 0x0 0xe80>, + <0x0 0x00140000 0x0 0x3fff>; + reg-names = "wan_top", "xport", "xlif", "epon"; + dma-coherent; + + resets = <&pmc PMC_R_WAN_AE>; + reset-names = "wan_ae"; + + local-mac-address = [ 00 07 CB 00 00 FE ]; + enet-runner,xrdp = <&xrdp>; + enet-runner,xport-pon-bbh = <3>; + enet-runner,xport-ae-bbh = <4>; + + //phy-mode = "1000base-x"; + phy-mode = "10gbase-kr"; + managed = "in-band-status"; + }; + }; + + ubus@ff800000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff800000 0x0 0x62000>; + + leds_top_syscon: system-controller@ff800800 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0x800 0x0 0x100>; + }; + + sdhci: sdhci@ff810000 { + status = "disabled"; + compatible = "brcm,bcm63xx-sdhci"; + reg = <0x0 0x00010000 0x0 0x100>; + interrupts = ; + no-1-8v; + bus-width = <8>; + }; + + arm_serial0: serial@ff812000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x12000 0x0 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + arm_serial2: serial@ff814000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x14000 0x0 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&uartclk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + + timer: timer@400 { + compatible = "syscon", "brcm,bcm63158-timer"; + reg = <0x0 0x400 0x0 0x94>, + <0x0 0x5a03c 0x0 0x4>; + reg-names = "timer", "top-reset-status"; + interrupts = ; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&timer>; + offset = <0x8c>; + mask = <1>; + }; + + pinctrl: pinctrl@500 { + compatible = "brcm,bcm63158-pinctrl"; + reg = <0x0 0x500 0x0 0x60>; + + gpio-controller; + #gpio-cells = <2>; + + emmc_pins: emmc-pins-0 { + emmc-d0 { + pinmux = ; + }; + emmc-d1 { + pinmux = ; + }; + emmc-d2 { + pinmux = ; + }; + emmc-d3 { + pinmux = ; + }; + emmc-d4 { + pinmux = ; + }; + emmc-d5 { + pinmux = ; + }; + emmc-d6 { + pinmux = ; + }; + emmc-d7 { + pinmux = ; + }; + emmc-clk { + pinmux = ; + }; + emmc-cmd { + pinmux = ; + }; + }; + + spi_pins: spi-pins { + spi-clk { + pinmux = ; + }; + spi-mosi { + pinmux = ; + }; + spi-miso { + pinmux = ; + }; + + /* + * board DTS will have to specify SPI + * SS pins as required. + */ + }; + + i2c0_pins: i2c0-pins { + i2c-sda { + pinmux = ; + }; + i2c-scl { + pinmux = ; + }; + }; + + i2c1_pins: i2c1-pins { + i2c-sda { + pinmux = ; + }; + i2c-scl { + pinmux = ; + }; + }; + + pcie0_pins: pcie0-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcie1_pins: pcie1-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcie2_pins: pcie2-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcie3_pins: pcie3-pins { + pcie-rst { + pinmux = ; + }; + pcie-clk { + pinmux = ; + }; + }; + + pcm_pins: pcm-pins { + pcm-clk { + pinmux = ; + }; + pcm-fsync { + pinmux = ; + }; + pcm-sdin { + pinmux = ; + }; + pcm-sdout { + pinmux = ; + }; + }; + + hs_uart_pins: hs-uart-pins { + hs-uart-sout { + pinmux = ; + }; + hs-uart-sin { + pinmux = ; + }; + hs-uart-cts { + pinmux = ; + }; + hs-uart-rts { + pinmux = ; + }; + }; + + usb01_pins: usb01-pins { + pwr0-en { + pinmux = ; + }; + pwr0-fault { + pinmux = ; + }; + pwr1-en { + pinmux = ; + }; + pwr1-fault { + pinmux = ; + }; + }; + + usb0_pins: usb0-pins { + pwr0-en { + pinmux = ; + }; + pwr0-fault { + pinmux = ; + }; + }; + + usb1_pins: usb1-pins { + pwr0-en { + pinmux = ; + }; + pwr0-fault { + pinmux = ; + }; + }; + + ld0_pins: ld0-pins { + ld0_pwr_up { + pinmux = ; + }; + + ld0_din { + pinmux = ; + }; + + ld0_dclk { + pinmux = ; + }; + }; + + ld1_pins: ld1-pins-0 { + ld1_pwr_up { + pinmux = ; + }; + + ld1_din { + pinmux = ; + }; + + ld1_dclk { + pinmux = ; + }; + }; + + gphy01_link_act_leds: gphy01-link-act-leds { + gphy0_link_act_led { + pinmux = ; + }; + gphy1_link_act_led { + pinmux = ; + }; + }; + }; + + hs_spim: spi@1000 { + status = "disabled"; + compatible = "brcm,bcm6328-hsspi"; + reg = <0x0 0x1000 0x0 0x600>; + interrupts = ; + clocks = <&spiclk>; + clock-names = "hsspi"; + #address-cells = <1>; + #size-cells = <0>; + }; + + hs_uart: hs-uart@10400 { + status = "disabled"; + compatible = "brcm,bcm63xx-hs-uart"; + reg = <0x0 0x00010400 0x0 0x1e0>; + interrupts = ; + clocks = <&uartclk>; + }; + + i2c_bsc0: i2c@2100 { + status = "disabled"; + compatible = "brcm,brcmper-i2c"; + reg = <0x0 0x2100 0x0 0x60>; + interrupts = ; + }; + + i2c_bsc1: i2c@5a800 { + status = "disabled"; + compatible = "brcm,brcmper-i2c"; + reg = <0x0 0x5a800 0x0 0x60>; + interrupts = ; + }; + + bcm_pcm: bcm_pcm@60000 { + status = "disabled"; + compatible = "brcm,bcm63158-pcm"; + reg = <0x0 0x60000 0x0 0x2000>; + interrupts = , + , + ; + interrupt-names = "pcm", "dma0", "dma1"; + }; + + bcm63158_cpufreq { + compatible = "brcm,bcm63158-cpufreq"; + pmc = <&pmc>; + }; + }; +}; diff -Nruw linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm963158ref1d.dts linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm963158ref1d.dts --- linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./bcm963158ref1d.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/bcm963158ref1d.dts 2021-03-04 13:20:57.007505521 +0100 @@ -0,0 +1,331 @@ +/* + * Broadcom BCM63158 Reference Board REF1 DTS + */ + +/dts-v1/; + +#include "bcm63158.dtsi" + +/ { + compatible = "brcm,BCM963158REF1", "brcm,bcm63158"; + model = "Broadcom BCM963158REF1"; + + chosen { + bootargs = "console=ttyAMA0,115200"; + stdout-path = &arm_serial0; + }; + + reserved-memory { + ramoops@3fff0000 { + compatible = "ramoops"; + /* RAM top - 64k */ + reg = <0x0 0x3fff0000 0x0 (64 * 1024)>; + record-size = <(64 * 1024)>; + ecc-size = <16>; + no-dump-oops; + }; + }; + + bcm963158ref1d-fbxgpio { + compatible = "fbx,fbxgpio"; + + wps-button { + gpio = <&pinctrl 41 0>; + input; + }; + dsl0-link-led { + gpio = <&pinctrl 18 0>; + output-low; + }; + + sfp-ae-pwren { + gpio = <&pinctrl 3 0>; + output-low; + }; + sfp-ae-rs0 { + gpio = <&pinctrl 40 0>; + input; + }; + sfp-ae-rs1 { + gpio = <&pinctrl 12 0>; + output-low; + }; + + sfp-ae-presence { + gpio = <&pinctrl 9 0>; + input; + }; + sfp-ae-rxlos { + gpio = <&pinctrl 8 0>; + input; + }; + + sfp-sgmii-presence { + gpio = <&pinctrl 20 0>; + input; + }; + sfp-sgmii-rxlos { + gpio = <&pinctrl 21 0>; + input; + }; + }; + + i2c0_gpio: i2c0-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 24 0 /* sda */ + &pinctrl 25 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1_gpio: i2c1-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 15 0 /* sda */ + &pinctrl 16 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&arm_serial0 { + status = "okay"; +}; + +&sf2 { + status = "okay"; +}; + +&sf2_port0 { + status = "okay"; + label = "swp1"; +}; + +&sf2_port1 { + status = "okay"; + label = "swp2"; +}; + +&sf2_port2 { + status = "okay"; + label = "swp3"; +}; + +&sf2_port3 { + status = "okay"; + label = "swp4"; +}; + +&sf2_port4 { + status = "okay"; + label = "swp5"; +}; + +&sf2_port8 { + status = "okay"; +}; + +&sf2_qphy0 { + status = "okay"; +}; + +&sf2_qphy1 { + status = "okay"; +}; + +&sf2_qphy2 { + status = "okay"; +}; + +&sf2_qphy3 { + status = "okay"; +}; + +&sf2_sphy { + status = "okay"; +}; + +&systemport { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&sdhci { + status = "okay"; + + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + partitions-main { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%d"; + + bank0@0 { + label = "bank0"; + reg = /bits/64 <0 (32 * 1024 * 1024)>; + read-only; + }; + + bank1@0 { + label = "bank1"; + reg = /bits/64 <(-1) (256 * 1024 * 1024)>; + }; + + nvram@0 { + label = "nvram"; + reg = /bits/64 <(-1) (4 * 1024 * 1024)>; + }; + + config@0 { + label = "config"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + new-bank0@0 { + label = "new_bank0"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + userdata@0 { + label = "userdata"; + reg = /bits/64 <(-1) (-1)>; + }; + }; + + + partitions-boot { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%dboot0"; + + cfe@0 { + label = "cfe"; + reg = /bits/64 <0 (1 * 1024 * 1024)>; + read-only; + }; + + serial@0 { + label = "fbxserial"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + + fbxboot@0 { + label = "fbxboot"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + }; +}; + +&spi_pins { + spi-ss0 { + pinmux = ; + }; + spi-ss1 { + pinmux = ; + }; +}; + +&hs_spim { + status = "okay"; + num-cs = <2>; + broadcom,dummy-cs = <2>; + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + serial-flash@0 { + compatible = "m25p80"; + reg = <0>; + spi-max-frequency = <(50 * 1000 * 1000)>; + label = "serial-flash"; + }; + + /* TO TEST SLAC */ + /* + spi-slac@1 { + compatible = "microsemi,le9641"; + reg = <1>; + spi-max-frequency = <(1 * 1000 * 1000)>; + }; + */ + + /* TO TEST LCD */ + /* + ssd1320@1 { + compatible = "solomon,ssd1320"; + reg = <1>; + spi-max-frequency = <(9 * 1000 * 1000)>; + ssd1320,width = <160>; + ssd1320,height = <100>; + ssd1320,segs-hw-skip = <0>; + ssd1320,coms-hw-skip = <30>; + ssd1320,rotate = <180>; + ssd1320,watchdog = <300>; + ssd1320,data-select-gpio = <&pinctrl 14 GPIO_ACTIVE_HIGH>; + ssd1320,reset-gpio = <&pinctrl 4 GPIO_ACTIVE_HIGH>; + }; + */ +}; + +&pcie01 { + status = "okay"; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie2 { + status = "okay"; + pinctrl-0 = <&pcie2_pins>; + pinctrl-names = "default"; +}; + + +&pcie3 { + status = "okay"; + pinctrl-0 = <&pcie3_pins>; + pinctrl-names = "default"; +}; + +&xdsl_phy { + status = "okay"; + + pinctrl-0 = <&ld0_pins>, <&ld1_pins>; + pinctrl-names = "default"; + + afe-id-0 = <(BCM63XX_XDSLPHY_AFE_CHIP_CH0 | + BCM63XX_XDSLPHY_AFE_LD_6304 | + BCM63XX_XDSLPHY_AFE_FE_ANNEXA | + BCM63XX_XDSLPHY_AFE_FE_REV_6304_REV_12_4_60 | + BCM63XX_XDSLPHY_AFE_FE_RNC)>; + + afe-id-1 = <(BCM63XX_XDSLPHY_AFE_CHIP_CH1 | + BCM63XX_XDSLPHY_AFE_LD_6304 | + BCM63XX_XDSLPHY_AFE_FE_ANNEXA | + BCM63XX_XDSLPHY_AFE_FE_REV_6304_REV_12_4_60 | + BCM63XX_XDSLPHY_AFE_FE_RNC)>; +}; + +/* TO TEST TELEPHONY */ +/* +&bcm_pcm { + status = "okay"; + pinctrl-0 = <&pcm_pins>; + pinctrl-names = "default"; +}; +*/ + +&usb { + status = "okay"; + + pinctrl-0 = <&usb01_pins>; + pinctrl-names = "default"; + + brcm,pwren-low; + brcm,pwrflt-low; +}; diff -Nruw linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r.dts linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r.dts --- linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./fbxgw8r.dts 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/fbxgw8r.dts 2021-03-30 16:07:01.585102883 +0200 @@ -0,0 +1,619 @@ +/* + * Freebox FBXGW8R Board DTS + */ + +/dts-v1/; + +#include +#include "bcm63158.dtsi" + +/ { + compatible = "freebox,fbxgw8r", "brcm,bcm63158"; + model = "Freebox FBXGW8R"; + + chosen { + bootargs = "console=ttyAMA0,115200"; + stdout-path = &arm_serial0; + }; + + reserved-memory { + ramoops@1fff0000 { + compatible = "ramoops"; + /* RAM top - 64k */ + reg = <0x0 0x1fff0000 0x0 (64 * 1024)>; + record-size = <(64 * 1024)>; + ecc-size = <16>; + no-dump-oops; + }; + }; + + fbxgw8r-gpio { + compatible = "fbx,fbxgpio"; + + wan-sfp-txfault { + gpio = <&pinctrl 11 0>; + input; + }; + wan-sfp-pwren { + gpio = <&pinctrl 14 0>; + output-low; + }; + wan-sfp-presence { + gpio = <&pinctrl 9 0>; + input; + }; + wan-sfp-pwrgood { + gpio = <&pinctrl 41 0>; + input; + }; + wan-sfp-rxlos { + gpio = <&pinctrl 10 0>; + input; + }; + wan-sfp-rs1 { + gpio = <&pinctrl 12 0>; + output-high; + }; + wan-sfp-rogue-in { + gpio = <&pinctrl 40 0>; + output-high; + }; + + led-white { + gpio = <&pinctrl 82 0>; + output-high; + }; + led-red { + gpio = <&pinctrl 83 0>; + output-low; + }; + + boot-eth { + gpio = <&pinctrl 37 0>; + input; + }; + + ha-rst { + gpio = <&pinctrl 91 0>; + output-low; + }; + poe-on { + gpio = <&pinctrl 20 0>; + output-low; + }; + + backlight-en { + gpio = <&pinctrl 81 0>; + output-low; + }; + + w-disable-1 { + gpio = <&pinctrl 98 0>; + output-low; + }; + w-disable-2 { + gpio = <&pinctrl 99 0>; + output-low; + }; + + board-id-0 { + gpio = <&pinctrl 35 0>; + input; + }; + board-id-1 { + gpio = <&pinctrl 28 0>; + input; + }; + board-id-2 { + gpio = <&pinctrl 29 0>; + input; + }; + board-id-3 { + gpio = <&pinctrl 30 0>; + input; + }; + board-id-4 { + gpio = <&pinctrl 31 0>; + input; + }; + board-id-5 { + gpio = <&pinctrl 13 0>; + input; + }; + }; + + keypad { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + autorepeat = <1>; + + keyup { + label = "key up"; + linux,code = ; + gpios = <&pinctrl 97 GPIO_ACTIVE_HIGH>; + }; + keydown { + label = "key down"; + linux,code = ; + gpios = <&pinctrl 96 GPIO_ACTIVE_HIGH>; + }; + keyright { + label = "key right"; + linux,code = ; + gpios = <&pinctrl 102 GPIO_ACTIVE_HIGH>; + }; + keyleft { + label = "key left"; + linux,code = ; + gpios = <&pinctrl 86 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c0_gpio: i2c0-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 24 0 /* sda */ + &pinctrl 25 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1_gpio: i2c1-gpio { + compatible = "i2c-gpio"; + gpios = <&pinctrl 15 0 /* sda */ + &pinctrl 16 0 /* scl */ + >; + i2c-gpio,delay-us = <10>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + adt7475@2e { + compatible = "adi,adt7475"; + reg = <0x2e>; + }; + + ld6710-fbx@68 { + compatible = "leadtrend,ld6710-fbx"; + reg = <0x68>; + }; + }; + + aliases { + i2c0 = &i2c0_gpio; + i2c1 = &i2c1_gpio; + }; +}; + +&pinctrl { + gpio-line-names = "", /* 0 */ + "", /* 1 */ + "", /* 2 */ + "bt-rst", /* 3 */ + "", /* 4 */ + "", /* 5 */ + "", /* 6 */ + "", /* 7 */ + "", /* 8 */ + "wan-sfp-presence", /* 9 */ + "wan-sfp-rxlos", /* 10 */ + "wan-sfp-txfault", /* 11 */ + "wan-sfp-rs1", /* 12 */ + "", /* 13 */ + "wan-sfp-pwren", /* 14 */ + "", /* 15 */ + "", /* 16 */ + "", /* 17 */ + "", /* 18 */ + "i2c-int", /* 19 */ + "poe-on", /* 20 */ + "fan-int", /* 21 */ + "", /* 22 */ + "fxs-int", /* 23 */ + "", /* 24 */ + "", /* 25 */ + "phy25-int", /* 26 */ + "phy25-reset", /* 27 */ + "", /* 28 */ + "", /* 29 */ + "", /* 30 */ + "", /* 31 */ + "", /* 32 */ + "", /* 33 */ + "", /* 34 */ + "", /* 35 */ + "oled-rst", /* 36 */ + "boot-eth", /* 37 */ + "", /* 38 */ + "", /* 39 */ + "", /* 40 */ + "wan-sfp-pwrgood", /* 41 */ + "", /* 42 */ + "", /* 43 */ + "", /* 44 */ + "", /* 45 */ + "", /* 46 */ + "", /* 47 */ + "", /* 48 */ + "", /* 49 */ + "", /* 50 */ + "", /* 51 */ + "", /* 52 */ + "", /* 53 */ + "", /* 54 */ + "", /* 55 */ + "", /* 56 */ + "", /* 57 */ + "", /* 58 */ + "", /* 59 */ + "", /* 60 */ + "", /* 61 */ + "", /* 62 */ + "", /* 63 */ + "", /* 64 */ + "", /* 65 */ + "", /* 66 */ + "", /* 67 */ + "", /* 68 */ + "", /* 69 */ + "", /* 70 */ + "", /* 71 */ + "", /* 72 */ + "", /* 73 */ + "", /* 74 */ + "", /* 75 */ + "", /* 76 */ + "", /* 77 */ + "", /* 78 */ + "", /* 79 */ + "oled-data-select", /* 80 */ + "backlight-en", /* 81 */ + "led-white", /* 82 */ + "led-red", /* 83 */ + "", /* 84 */ + "", /* 85 */ + "keypad-left", /* 86 */ + "oled-vcc", /* 87 */ + "bt-rst", /* 88 */ + "ha-swd-clk", /* 89 */ + "ha-swd-io", /* 90 */ + "ha-rst", /* 91 */ + "", /* 92 */ + "", /* 93 */ + "", /* 94 */ + "", /* 95 */ + "keypad-up", /* 96 */ + "keypad-down", /* 97 */ + "w-disable-1", /* 98 */ + "w-disable-2", /* 99 */ + "", /* 100 */ + "", /* 101 */ + "keypad-right", /* 102 */ + "", /* 103 */ + "", /* 104 */ + "", /* 105 */ + "", /* 106 */ + "", /* 107 */ + "", /* 108 */ + "", /* 109 */ + "", /* 110 */ + "", /* 111 */ + "", /* 112 */ + "", /* 113 */ + "", /* 114 */ + "", /* 115 */ + "", /* 116 */ + "", /* 117 */ + "", /* 118 */ + "", /* 119 */ + "", /* 120 */ + "", /* 121 */ + "", /* 122 */ + "", /* 123 */ + "", /* 124 */ + "", /* 125 */ + "", /* 126 */ + "", /* 127 */ + "", /* 128 */ + "", /* 129 */ + ""; /* 130 */ + + arm_serial2_pins: arm-serial2-pins-0 { + arm_serial2_sout { + pinmux = ; + }; + arm_serial2_sin { + pinmux = ; + }; + }; +}; + +&arm_serial0 { + status = "okay"; +}; + + +&arm_serial2 { + /* home automation */ + status = "okay"; + pinctrl-0 = <&arm_serial2_pins>; + pinctrl-names = "default"; +}; + +&sf2 { + status = "okay"; + + pinctrl-0 = <&gphy01_link_act_leds>; + pinctrl-names = "default"; + + sf2,mdio { + reset-gpio = <&pinctrl 27 GPIO_ACTIVE_LOW>; + reset-delay-us = <100000>; + + /* aquantia PHY */ + aq_phy: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + status = "okay"; + reg = <8>; + }; + }; +}; + +&sf2_port0 { + status = "okay"; + label = "swp1"; + sf2,led-link-act = <20>; +}; + +&sf2_port1 { + status = "okay"; + label = "swp2"; + sf2,led-link-act = <21>; + dsa,cpu-port = <&sf2_port7>; +}; + +&sf2_port5 { + status = "okay"; +}; + +&sf2_port6 { + status = "okay"; + xbar-in-port = <0>; + phy-handle = <&aq_phy>; + label = "swp3"; + dsa,cpu-port = <&sf2_port5>; +}; + +&sf2_port7 { + status = "okay"; +}; + +&sf2_port8 { + status = "okay"; +}; + +&sf2_qphy0 { + status = "okay"; +}; + +&sf2_qphy1 { + status = "okay"; +}; + +&runner_unimac0 { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&runner_unimac1 { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&runner_unimac2 { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&runner_xport0 { + status = "okay"; + fbxserial-mac-address = <0>; +}; + +&sdhci { + status = "okay"; + + pinctrl-0 = <&emmc_pins>; + pinctrl-names = "default"; + + partitions-main { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%d"; + + bank0@0 { + label = "bank0"; + reg = /bits/64 <0 (32 * 1024 * 1024)>; + read-only; + }; + + bank1@0 { + label = "bank1"; + reg = /bits/64 <(-1) (256 * 1024 * 1024)>; + }; + + nvram@0 { + label = "nvram"; + reg = /bits/64 <(-1) (4 * 1024 * 1024)>; + }; + + config@0 { + label = "config"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + new-bank0@0 { + label = "new_bank0"; + reg = /bits/64 <(-1) (32 * 1024 * 1024)>; + }; + + fbxmbr@0 { + label = "fbxmbr"; + reg = /bits/64 <(-1) (4096)>; + }; + + fortknox@0 { + label = "fortknox"; + reg = /bits/64 <(-1) (128 * 1024 * 1024)>; + }; + + userdata@0 { + label = "userdata"; + reg = /bits/64 <(-1) (-1)>; + }; + + }; + + + partitions-boot { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <2>; + disk-name = "mmcblk%dboot0"; + + cfe@0 { + label = "cfe0"; + reg = /bits/64 <0 (256 * 1024)>; + read-only; + }; + cfe@1 { + label = "cfe1"; + reg = /bits/64 <(-1) (256 * 1024)>; + read-only; + }; + cfe@2 { + label = "cfe2"; + reg = /bits/64 <(-1) (256 * 1024)>; + read-only; + }; + + serial@0 { + label = "fbxserial"; + reg = /bits/64 <(1024 * 1024) (8 * 1024)>; + read-only; + }; + + fbxboot@0 { + label = "fbxboot"; + reg = /bits/64 <(-1) (8 * 1024)>; + read-only; + }; + + calibration@0 { + label = "calibration"; + reg = /bits/64 <(-1) (64 * 1024)>; + read-only; + }; + }; +}; + +&xdsl_phy { + status = "okay"; + + pinctrl-0 = <&ld0_pins>; + pinctrl-names = "default"; + + afe-id-0 = <(BCM63XX_XDSLPHY_AFE_CHIP_CH0 | + BCM63XX_XDSLPHY_AFE_LD_6303 | + BCM63XX_XDSLPHY_AFE_FE_ANNEXA | + BCM63XX_XDSLPHY_AFE_FE_REV_6303_REV_12_3_60 | + BCM63XX_XDSLPHY_AFE_FE_RNC)>; +}; + +&spi_pins { + spi-ss0 { + pinmux = ; + }; + spi-ss1 { + pinmux = ; + }; +}; + +&hs_spim { + status = "okay"; + num-cs = <2>; + broadcom,dummy-cs = <2>; + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + ssd1320@0 { + compatible = "solomon,ssd1320"; + reg = <0>; + spi-max-frequency = <(14 * 1000 * 1000)>; + ssd1320,width = <160>; + ssd1320,height = <80>; + ssd1320,segs-hw-skip = <0>; + ssd1320,coms-hw-skip = <40>; + ssd1320,rotate = <180>; + ssd1320,watchdog = <300>; + ssd1320,vcc-gpio = <&pinctrl 87 GPIO_ACTIVE_HIGH>; + ssd1320,data-select-gpio = <&pinctrl 80 GPIO_ACTIVE_HIGH>; + ssd1320,reset-gpio = <&pinctrl 36 GPIO_ACTIVE_LOW>; + }; + + spi-slac@1 { + compatible = "microsemi,le9641"; + reg = <1>; + spi-max-frequency = <(1 * 1000 * 1000)>; + }; +}; + +&bcm_pcm { + status = "okay"; + pinctrl-0 = <&pcm_pins>; + pinctrl-names = "default"; +}; + +&usb { + status = "okay"; + + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + brcm,pwren-high; + brcm,pwrflt-low; +}; + +&pcie0 { + status = "okay"; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie1 { + status = "okay"; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; +}; + +&hs_uart { + status = "okay"; + pinctrl-0 = <&hs_uart_pins>; + pinctrl-names = "default"; + bluetooth { + compatible = "realtek,rtl8761btv-bt"; + firmware-postfix = "1M5"; + reset-gpio = <&pinctrl 88 GPIO_ACTIVE_LOW>; + }; +}; + +&xtm { + status = "okay"; +}; + +&memc { + // status = "disabled"; + brcm,auto-sr-en; + brcm,auto-sr-thresh = <20>; +}; diff -Nruw linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./Makefile linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/Makefile --- linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/arch/arm64/boot/dts/broadcom/bcm63xx/Makefile 2021-03-04 13:20:57.004172187 +0100 @@ -0,0 +1,5 @@ +dtb-$(CONFIG_ARCH_BCM63XX) += bcm963158ref1d.dtb fbxgw8r.dtb + +always := $(dtb-y) +subdir-y := $(dts-dirs) +clean-files := *.dtb --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/block/partitions/dt.c 2021-03-04 13:20:57.500838876 +0100 @@ -0,0 +1,205 @@ +#define PREFIX "dtparts" + +#include +#include +#include +#include "check.h" +#include "dt.h" + +/** + * match_one: - Determines if a string matches a simple pattern + * @s: the string to examine for presence of the pattern + * @p: the string containing the pattern + */ +static int match_one(char *s, const char *p) +{ + char *meta, *from, *to; + + while (1) { + int len = -1; + + meta = strchr(p, '%'); + if (!meta) + return strcmp(p, s) == 0; + + if (strncmp(p, s, meta-p)) + return 0; + + s += meta - p; + p = meta + 1; + + if (isdigit(*p)) + len = simple_strtoul(p, (char **) &p, 10); + else if (*p == '%') { + if (*s++ != '%') + return 0; + p++; + continue; + } + + from = s; + switch (*p++) { + case 's': { + size_t str_len = strlen(s); + + if (str_len == 0) + return 0; + if (len == -1 || len > str_len) + len = str_len; + to = s + len; + break; + } + case 'd': + simple_strtol(s, &to, 0); + goto num; + case 'u': + simple_strtoul(s, &to, 0); + goto num; + case 'o': + simple_strtoul(s, &to, 8); + goto num; + case 'x': + simple_strtoul(s, &to, 16); + + num: + if (to == from) + return 0; + break; + default: + return 0; + } + s = to; + } +} + +/* + * + */ +static struct device_node *find_first_parent_node(const struct device *ddev) +{ + while (ddev && !ddev->of_node) + ddev = ddev->parent; + + if (!ddev) + return NULL; + return ddev->of_node; +} + +/* + * + */ +int dt_partition(struct parsed_partitions *state) +{ + struct device *ddev = disk_to_dev(state->bdev->bd_disk); + struct device_node *np, *part_node, *pp; + u64 disk_size, last_end; + int nr_parts, i; + + /* find first parent device with a non null device tree + * node */ + np = find_first_parent_node(ddev); + if (!np) + return -1; + + part_node = NULL; + for_each_child_of_node(np, pp) { + char diskname[BDEVNAME_SIZE]; + const char *pattern; + + if (!of_device_is_compatible(pp, "fixed-partitions")) + continue; + + /* check device name match pattern */ + bdevname(state->bdev, diskname); + + if (of_property_read_string(pp, "disk-name", &pattern)) { + part_node = pp; + break; + } + + if (match_one(diskname, pattern)) { + part_node = pp; + break; + } + } + + if (!part_node) + return -1; + + /* First count the subnodes */ + nr_parts = 0; + for_each_child_of_node(part_node, pp) + nr_parts++; + + if (nr_parts == 0) + return 0; + + disk_size = get_capacity(state->bdev->bd_disk) << 9; + + last_end = 0; + i = 1; + for_each_child_of_node(part_node, pp) { + struct partition_meta_info *info; + char tmp[sizeof (info->volname) + 4]; + const __be32 *reg; + const char *partname; + int a_cells, s_cells; + u64 size, offset; + int len; + + reg = of_get_property(pp, "reg", &len); + if (!reg) { + pr_err("part %pOF (%pOF) missing reg property.\n", + pp, np); + return -1; + } + + a_cells = of_n_addr_cells(pp); + s_cells = of_n_size_cells(pp); + if (len / 4 != a_cells + s_cells) { + pr_err("ofpart partition %pOF (%pOF) " + "error parsing reg property.\n", + pp, np); + return -1; + } + + partname = of_get_property(pp, "label", &len); + if (!partname) + partname = of_get_property(pp, "name", &len); + + if (i >= state->limit) { + pr_err("too many partitions\n"); + return -1; + } + + offset = of_read_number(reg, a_cells); + if (offset == (u64)-1) { + offset = last_end; + } + + size = of_read_number(reg + a_cells, s_cells); + if (size == (u64)-1) + size = disk_size - offset; + + last_end = offset + size; + put_partition(state, i, offset >> 9, size >> 9); + + info = &state->parts[i].info; + strlcpy(info->volname, partname, sizeof (info->volname)); + state->parts[i].has_info = true; + + if (!IS_ENABLED(CONFIG_OF_PARTITION_IGNORE_RO) && + of_get_property(pp, "read-only", &len)) + state->parts[i].flags |= ADDPART_FLAG_RO; + + snprintf(tmp, sizeof(tmp), "(%s/%s)", + info->volname, + state->parts[i].flags ? "ro" : "rw"); + strlcat(state->pp_buf, tmp, PAGE_SIZE); + + i++; + } + + strlcat(state->pp_buf, "\n", PAGE_SIZE); + return 1; +} --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/block/partitions/dt.h 2021-03-04 13:20:57.500838876 +0100 @@ -0,0 +1 @@ +int dt_partition(struct parsed_partitions *); --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/config 2021-04-21 12:15:44.268568297 +0200 @@ -0,0 +1,4305 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm64 5.4.60 Kernel Configuration +# + +# +# Compiler: aarch64-linux-musl-gcc (freebox) 10.2.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=100200 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_ASM_INLINE=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="/opt/toolchains/aarch64-musl-1.2.2-gcc-10.2.0-binutils-2.36-gdb-7.12.1-2/bin/aarch64-linux-musl-" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_USELIB is not set +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ_FULL is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_SCHED_AVG_IRQ=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# CONFIG_CPU_ISOLATION is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_IKCONFIG=y +# CONFIG_IKCONFIG_PROC is not set +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +# CONFIG_FBX_DECRYPT_INITRD is not set +CONFIG_GENERIC_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_CGROUPS=y +# CONFIG_MEMCG is not set +# CONFIG_BLK_CGROUP is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUP_PIDS is not set +# CONFIG_CGROUP_RDMA is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_CGROUP_PERF is not set +# CONFIG_CGROUP_DEBUG is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set +CONFIG_NET_NS=y +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INITRAMFS_FORCE is not set +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_RD_LZ4 is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set +# CONFIG_SYSFS_SYSCALL is not set +CONFIG_SYSCTL_SYSCALL=y +# CONFIG_FHANDLE is not set +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_IO_URING is not set +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y +# CONFIG_BPF_SYSCALL is not set +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +# CONFIG_RSEQ is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_PROFILING is not set +# end of General setup + +CONFIG_ARM64=y +CONFIG_64BIT=y +CONFIG_MMU=y +CONFIG_ARM64_PAGE_SHIFT=12 +CONFIG_ARM64_CONT_SHIFT=4 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +# CONFIG_ZONE_DMA32 is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_SMP=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_PROC_KCORE_TEXT=y + +# +# Platform selection +# +# CONFIG_ARCH_ACTIONS is not set +# CONFIG_ARCH_AGILEX is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_ALPINE is not set +# CONFIG_ARCH_BCM2835 is not set +# CONFIG_ARCH_BCM_IPROC is not set +CONFIG_ARCH_BCM63XX=y +CONFIG_ARCH_BCM63XX_SHARED_OSH=y +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_BITMAIN is not set +# CONFIG_ARCH_BRCMSTB is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_K3 is not set +# CONFIG_ARCH_LAYERSCAPE is not set +# CONFIG_ARCH_LG1K is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_MEDIATEK is not set +# CONFIG_ARCH_MESON is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SEATTLE is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_SYNQUACER is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_THUNDER is not set +# CONFIG_ARCH_THUNDER2 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZX is not set +# CONFIG_ARCH_ZYNQMP is not set +# end of Platform selection + +# +# Kernel Features +# + +# +# ARM errata workarounds via the alternatives framework +# +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_819472=y +# CONFIG_ARM64_ERRATUM_832075 is not set +CONFIG_ARM64_ERRATUM_843419=y +# CONFIG_ARM64_ERRATUM_1024718 is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1463225 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_CAVIUM_ERRATUM_30115 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set +# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set +# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set +# CONFIG_HISILICON_ERRATUM_161600802 is not set +# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +# end of ARM errata workarounds via the alternatives framework + +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_16K_PAGES is not set +# CONFIG_ARM64_64K_PAGES is not set +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PA_BITS=48 +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_NR_CPUS=4 +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NUMA is not set +CONFIG_HOLES_IN_ZONE=y +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HW_PERF_EVENTS=y +CONFIG_SYS_SUPPORTS_HUGETLBFS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_SECCOMP=y +# CONFIG_PARAVIRT is not set +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +# CONFIG_KEXEC_FILE is not set +# CONFIG_CRASH_DUMP is not set +# CONFIG_XEN is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +# CONFIG_HARDEN_BRANCH_PREDICTOR is not set +# CONFIG_HARDEN_EL2_VECTORS is not set +# CONFIG_ARM64_SSBD is not set +# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set +# CONFIG_ARM64_SW_TTBR0_PAN is not set +CONFIG_ARM64_TAGGED_ADDR_ABI=y +# CONFIG_COMPAT is not set + +# +# ARMv8.1 architectural features +# +CONFIG_ARM64_HW_AFDBM=y +CONFIG_ARM64_PAN=y +# CONFIG_ARM64_VHE is not set +# end of ARMv8.1 architectural features + +# +# ARMv8.2 architectural features +# +CONFIG_ARM64_UAO=y +# CONFIG_ARM64_PMEM is not set +# CONFIG_ARM64_RAS_EXTN is not set +# CONFIG_ARM64_CNP is not set +# end of ARMv8.2 architectural features + +# +# ARMv8.3 architectural features +# +# CONFIG_ARM64_PTR_AUTH is not set +# end of ARMv8.3 architectural features + +# CONFIG_ARM64_SVE is not set +CONFIG_ARM64_MODULE_PLTS=y +# CONFIG_ARM64_PSEUDO_NMI is not set +# CONFIG_RANDOMIZE_BASE is not set +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +# end of Kernel Features + +# +# Boot options +# +CONFIG_CMDLINE="console=ttyAMA0,115200 earlycon=pl011,mmio32,0xff812000 debug ip=:::::swp1:dhcp root=/dev/nfs" +CONFIG_CMDLINE_FORCE=y +# CONFIG_EFI is not set +# end of Boot options + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM is not set +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# end of Power management options + +# +# CPU Power Management +# + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# end of CPU Idle + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +CONFIG_CPU_FREQ_GOV_USERSPACE=y +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +# CONFIG_QORIQ_CPUFREQ is not set +CONFIG_BCM63158_CPUFREQ=y +# end of CPU Frequency scaling +# end of CPU Power Management + +# +# Firmware Drivers +# +# CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set +# CONFIG_FW_CFG_SYSFS is not set +CONFIG_HAVE_ARM_SMCCC=y +CONFIG_ARM_PSCI_FW=y +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_EFI_EARLYCON=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +# CONFIG_VIRTUALIZATION is not set +# CONFIG_ARM64_CRYPTO is not set + +# +# General architecture-dependent options +# +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_KEEPINITRD=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ASM_MODVERSIONS=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +# CONFIG_STACKPROTECTOR is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_64BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_REFCOUNT_FULL=y +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_PLUGIN_HOSTCC="g++" +CONFIG_HAVE_GCC_PLUGINS=y +CONFIG_GCC_PLUGINS=y +# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_OF_PARTITION=y +# CONFIG_OF_PARTITION_IGNORE_RO is not set +# end of Partition Types + +CONFIG_BLK_MQ_PCI=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y +CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK=y +CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_READ_LOCK=y +CONFIG_ARCH_INLINE_READ_LOCK_BH=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_READ_UNLOCK=y +CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y +CONFIG_ARCH_INLINE_WRITE_LOCK=y +CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +# CONFIG_MEMORY_HOTPLUG is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +# CONFIG_MEMORY_FAILURE is not set +# CONFIG_TRANSPARENT_HUGEPAGE is not set +# CONFIG_CLEANCACHE is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_NET_EGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_NETSKBPAD=64 +CONFIG_NET_NMESH_MBH=y +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_ABSTRACT_IGNORE_NETNS=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=y +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +# CONFIG_NET_KEY_MIGRATE is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IP_TUNNEL=y +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +# CONFIG_INET_ESP_OFFLOAD is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_ESP_OFFLOAD=y +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +CONFIG_INET6_TUNNEL=y +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_GRE is not set +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_INGRESS is not set +# CONFIG_NETFILTER_NETLINK_ACCT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NETFILTER_NETLINK_OSF is not set +CONFIG_NF_CONNTRACK=y +# CONFIG_NF_LOG_NETDEV is not set +# CONFIG_NF_CONNTRACK_MARK is not set +# CONFIG_NF_CONNTRACK_ZONES is not set +CONFIG_NF_CONNTRACK_PROCFS=y +# CONFIG_NF_CONNTRACK_EVENTS is not set +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +# CONFIG_NF_CONNTRACK_TIMESTAMP is not set +# CONFIG_NF_CONNTRACK_LABELS is not set +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +# CONFIG_NF_CT_PROTO_UDPLITE is not set +# CONFIG_NF_CONNTRACK_AMANDA is not set +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +CONFIG_NF_CONNTRACK_PPTP=m +# CONFIG_NF_CONNTRACK_SANE is not set +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_TFTP=y +# CONFIG_NF_CT_NETLINK is not set +CONFIG_NF_NAT=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=m +CONFIG_NF_NAT_SIP=m +CONFIG_NF_NAT_TFTP=y +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +# CONFIG_NF_TABLES is not set +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +# CONFIG_NETFILTER_XT_CONNMARK is not set + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set +CONFIG_NETFILTER_XT_TARGET_DSCP=y +# CONFIG_NETFILTER_XT_TARGET_HL is not set +# CONFIG_NETFILTER_XT_TARGET_HMARK is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_LOG is not set +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_NAT=y +# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=y +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_BPF is not set +# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +CONFIG_NETFILTER_XT_MATCH_DCCP=y +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +CONFIG_NETFILTER_XT_MATCH_DSCP=y +# CONFIG_NETFILTER_XT_MATCH_ECN is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +# CONFIG_NETFILTER_XT_MATCH_L2TP is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +CONFIG_NETFILTER_XT_MATCH_OWNER=y +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=y +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +CONFIG_NETFILTER_XT_MATCH_STATE=y +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_IP_FFN=y +CONFIG_IP_FFN_PROCFS=y +CONFIG_NF_DEFRAG_IPV4=y +# CONFIG_NF_SOCKET_IPV4 is not set +CONFIG_NF_TPROXY_IPV4=y +# CONFIG_NF_DUP_IPV4 is not set +# CONFIG_NF_LOG_ARP is not set +# CONFIG_NF_LOG_IPV4 is not set +CONFIG_NF_REJECT_IPV4=y +CONFIG_NF_NAT_PPTP=m +CONFIG_NF_NAT_H323=m +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_RPFILTER is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +# CONFIG_IP_NF_TARGET_SYNPROXY is not set +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +# CONFIG_IP_NF_TARGET_NETMAP is not set +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_MANGLE=y +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +# CONFIG_IP_NF_TARGET_ECN is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +# CONFIG_IP_NF_ARPTABLES is not set +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +CONFIG_IPV6_FFN=y +CONFIG_IPV6_FFN_PROCFS=y +# CONFIG_NF_SOCKET_IPV6 is not set +CONFIG_NF_TPROXY_IPV6=y +# CONFIG_NF_DUP_IPV6 is not set +CONFIG_NF_REJECT_IPV6=y +# CONFIG_NF_LOG_IPV6 is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=y +# CONFIG_IP6_NF_RAW is not set +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +# CONFIG_IP6_NF_TARGET_NPT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=y +# CONFIG_NF_CONNTRACK_BRIDGE is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_FBXATM=y +CONFIG_FBXATM_STACK=y +# CONFIG_FBXATM_REMOTE_STUB is not set +# CONFIG_FBXATM_REMOTE_DRIVER is not set +CONFIG_FBXBRIDGE=y +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +CONFIG_HAVE_NET_DSA=y +CONFIG_NET_DSA=y +# CONFIG_NET_DSA_TAG_8021Q is not set +CONFIG_NET_DSA_TAG_BRCM_COMMON=y +CONFIG_NET_DSA_TAG_BRCM=y +# CONFIG_NET_DSA_TAG_BRCM_PREPEND is not set +CONFIG_NET_DSA_TAG_BRCM_FBX=y +# CONFIG_NET_DSA_TAG_GSWIP is not set +# CONFIG_NET_DSA_TAG_DSA is not set +# CONFIG_NET_DSA_TAG_EDSA is not set +# CONFIG_NET_DSA_TAG_MTK is not set +# CONFIG_NET_DSA_TAG_KSZ is not set +# CONFIG_NET_DSA_TAG_QCA is not set +# CONFIG_NET_DSA_TAG_LAN9303 is not set +# CONFIG_NET_DSA_TAG_SJA1105 is not set +# CONFIG_NET_DSA_TAG_TRAILER is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +CONFIG_NET_SCH_SFQ=y +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +CONFIG_NET_SCH_DRR=y +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +CONFIG_NET_SCH_INGRESS=y +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +CONFIG_NET_CLS_U32=y +# CONFIG_CLS_U32_PERF is not set +CONFIG_CLS_U32_MARK=y +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +# CONFIG_NET_EMATCH is not set +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_SAMPLE is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +CONFIG_NET_ACT_SKBEDIT=y +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_MPLS is not set +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_SKBMOD is not set +# CONFIG_NET_ACT_IFE is not set +# CONFIG_NET_ACT_TUNNEL_KEY is not set +# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_TC_SKB_EXT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +CONFIG_NET_SWITCHDEV=y +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +CONFIG_BPF_JIT=y +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +CONFIG_NET_PKTGEN=y +# end of Network testing +# end of Networking options + +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +CONFIG_BT=y +CONFIG_BT_BREDR=y +# CONFIG_BT_RFCOMM is not set +# CONFIG_BT_BNEP is not set +CONFIG_BT_HIDP=y +CONFIG_BT_HS=y +CONFIG_BT_LE=y +# CONFIG_BT_LEDS is not set +# CONFIG_BT_SELFTEST is not set +CONFIG_BT_DEBUGFS=y + +# +# Bluetooth device drivers +# +CONFIG_BT_RTL=y +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIUART_H4=y +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +# CONFIG_BT_HCIUART_LL is not set +CONFIG_BT_HCIUART_3WIRE=y +# CONFIG_BT_HCIUART_INTEL is not set +# CONFIG_BT_HCIUART_BCM is not set +CONFIG_BT_HCIUART_RTL=y +# CONFIG_BT_HCIUART_QCA is not set +# CONFIG_BT_HCIUART_AG6XX is not set +# CONFIG_BT_HCIUART_MRVL is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_MTKSDIO is not set +# CONFIG_BT_MTKUART is not set +# end of Bluetooth device drivers + +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_CERTIFICATION_ONUS=y +# CONFIG_CFG80211_REQUIRE_SIGNED_REGDB is not set +# CONFIG_CFG80211_REG_CELLULAR_HINTS is not set +# CONFIG_CFG80211_REG_RELAX_NO_IR is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +# CONFIG_CFG80211_WEXT is not set +CONFIG_MAC80211=y +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +CONFIG_NET_DEVLINK=y +# CONFIG_FAILOVER is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_ARM_AMBA=y +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +CONFIG_PCI_SYSCALL=y +CONFIG_PCIEPORTBUS=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +# CONFIG_PCIEASPM is not set +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +# CONFIG_PCIE_BW is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# PCI controller drivers +# + +# +# Cadence PCIe controllers support +# +# CONFIG_PCIE_CADENCE_HOST is not set +# end of Cadence PCIe controllers support + +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_HOST_GENERIC is not set +# CONFIG_PCIE_XILINX is not set +# CONFIG_PCI_XGENE is not set +# CONFIG_PCIE_ALTERA is not set +# CONFIG_PCI_HOST_THUNDER_PEM is not set +# CONFIG_PCI_HOST_THUNDER_ECAM is not set +CONFIG_PCIE_BCM63XX=y + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_HISI is not set +# CONFIG_PCIE_KIRIN is not set +# CONFIG_PCI_MESON is not set +# CONFIG_PCIE_AL is not set +# end of DesignWare PCI Core Support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +# CONFIG_RAPIDIO is not set + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_EXTRA_FIRMWARE="aquantia_phy/fw.uc xrdp/dsl_firmware/bcm63xx_dsl_runner.rpgm xrdp/enet_firmware/bcm63xx_enet_runner.rpgm" +CONFIG_EXTRA_FIRMWARE_DIR="firmware" +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y +# CONFIG_FW_LOADER_COMPRESS is not set +# end of Firmware loader + +CONFIG_WANT_DEV_COREDUMP=y +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +CONFIG_GENERIC_ARCH_TOPOLOGY=y +# end of Generic Driver Options + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_MOXTET is not set +# CONFIG_VEXPRESS_CONFIG is not set +# end of Bus devices + +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +CONFIG_FREEBOX_PROCFS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_ERASE_PRINTK=y + +# +# Partition parsers +# +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_OF_PARTS_IGNORE_RO is not set +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_FBX6HD_PARTS is not set +# end of Partition parsers + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# end of RAM/ROM/Flash chip drivers + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set +# end of Mapping drivers for chip access + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MCHP23K256 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# end of Self-contained MTD device drivers + +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_RAW_NAND is not set +# CONFIG_MTD_SPI_NAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# end of LPDDR & LPDDR2 PCM memory drivers + +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_MTK_QUADSPI is not set +# CONFIG_MTD_UBI is not set +# CONFIG_MTD_HYPERBUS is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_DTB_BUILTIN_LIST="" +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_OF_RESOLVE=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_WINTEGRA_MMAP is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_INTELCE_PIC16PMU is not set +CONFIG_FBXSERIAL_OF=y +CONFIG_RANDOM_OF=y +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# CONFIG_EEPROM_EE1004_RAW is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# +# CONFIG_VOP_BUS is not set + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# end of Intel MIC & related support + +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set + +# +# RemoTI support +# +# end of RemoTI support + +# +# HDMI CEC support +# +# CONFIG_HDMI_CEC is not set +# end of HDMI CEC support +# end of Misc devices + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_HAVE_PATA_PLATFORM=y +# CONFIG_ATA is not set +CONFIG_MD=y +# CONFIG_BLK_DEV_MD is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_UNSTRIPED is not set +CONFIG_DM_CRYPT=y +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set +# CONFIG_DM_MIRROR is not set +# CONFIG_DM_RAID is not set +# CONFIG_DM_ZERO is not set +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +CONFIG_DUMMY=y +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +CONFIG_TUN=y +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_B53 is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_NET_DSA_LOOP is not set +# CONFIG_NET_DSA_LANTIQ_GSWIP is not set +# CONFIG_NET_DSA_MT7530 is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ9477 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_SJA1105 is not set +# CONFIG_NET_DSA_QCA8K is not set +# CONFIG_NET_DSA_REALTEK_SMI is not set +# CONFIG_NET_DSA_SMSC_LAN9303_I2C is not set +# CONFIG_NET_DSA_SMSC_LAN9303_MDIO is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_AURORA is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCM63XX_ENET_RUNNER is not set +CONFIG_BCM63158_SF2=y +CONFIG_BCM63158_SYSTEMPORT=y +CONFIG_BCM63158_ENET_RUNNER=y +CONFIG_BCM63158_ENET_RUNNER_FF=y +# CONFIG_BCMGENET is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2X is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_BNXT is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HP is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +CONFIG_R8169=m +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLINK=y +CONFIG_PHYLIB=y +CONFIG_SWPHY=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +# CONFIG_SFP is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_AMD_PHY is not set +CONFIG_AQUANTIA_PHY=y +# CONFIG_AX88796B_PHY is not set +# CONFIG_AT803X_PHY is not set +CONFIG_BCM7XXX_PHY=y +# CONFIG_BCM87XX_PHY is not set +CONFIG_BCM_NET_PHYLIB=y +CONFIG_BROADCOM_PHY=y +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=m +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=y +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_FILTER is not set +CONFIG_PPP_MPPE=y +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPPOE=y +CONFIG_PPTP=y +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=y +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH_COMMON=y +CONFIG_WLAN_VENDOR_ATH=y +CONFIG_ATH_DEBUG=y +CONFIG_ATH_REG_IGNORE=y +# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set +# CONFIG_ATH5K is not set +# CONFIG_ATH5K_PCI is not set +CONFIG_ATH9K_HW=m +CONFIG_ATH9K_COMMON=m +CONFIG_ATH9K_COMMON_DEBUG=y +CONFIG_ATH9K_BTCOEX_SUPPORT=y +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI=y +# CONFIG_ATH9K_AHB is not set +CONFIG_ATH9K_DEBUGFS=y +CONFIG_ATH9K_STATION_STATISTICS=y +CONFIG_ATH9K_TX99=y +# CONFIG_ATH9K_DFS_CERTIFIED is not set +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +# CONFIG_ATH9K_PCOEM is not set +# CONFIG_ATH9K_PCI_NO_EEPROM is not set +# CONFIG_ATH9K_HTC is not set +# CONFIG_ATH9K_HWRNG is not set +# CONFIG_ATH9K_COMMON_SPECTRAL is not set +# CONFIG_CARL9170 is not set +# CONFIG_ATH6KL is not set +# CONFIG_AR5523 is not set +# CONFIG_WIL6210 is not set +CONFIG_ATH10K=y +CONFIG_ATH10K_CE=y +CONFIG_ATH10K_PCI=m +# CONFIG_ATH10K_AHB is not set +# CONFIG_ATH10K_SDIO is not set +# CONFIG_ATH10K_USB is not set +CONFIG_ATH10K_DEBUG=y +CONFIG_ATH10K_DEBUGFS=y +# CONFIG_ATH10K_SPECTRAL is not set +CONFIG_ATH10K_DFS_CERTIFIED=y +# CONFIG_WCN36XX is not set +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_VIRT_WIFI is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_GPIO is not set +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_CAP11XX is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_E3X0_BUTTON is not set +# CONFIG_INPUT_MSM_VIBRATOR is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +# CONFIG_INPUT_SMSC_CAP1066 is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_NULL_TTY is not set +# CONFIG_LDISC_AUTOLOAD is not set +# CONFIG_DEVMEM is not set +# CONFIG_DEVPHYSMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +CONFIG_SERIAL_BCM63XX_HS=m +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# end of Serial drivers + +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_CAVIUM is not set +# CONFIG_HW_RANDOM_OPTEE is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_DEVPORT is not set +# CONFIG_XILLYBUS is not set +# end of Character devices + +CONFIG_RANDOM_TRUST_BOOTLOADER=y + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_MUX_GPMUX is not set +# CONFIG_I2C_MUX_LTC4306 is not set +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +# CONFIG_I2C_MUX_MLXCPLD is not set +# end of Multiplexer I2C Chip support + +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_BRCMSTB=y +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +CONFIG_I2C_GPIO=y +# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set +# CONFIG_I2C_NOMADIK is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_THUNDERX is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_AXI_SPI_ENGINE is not set +CONFIG_SPI_BCM63XX_HSSPI=y +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_DESIGNWARE is not set +# CONFIG_SPI_NXP_FLEXSPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_SIFIVE is not set +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_THUNDERX is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_ZYNQMP_GQSPI is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_SLAVE is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# end of PTP clock support + +CONFIG_PINCTRL=y +CONFIG_PINMUX=y +CONFIG_PINCONF=y +CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PINCTRL_OCELOT is not set +CONFIG_PINCTRL_BCM63138=y +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers +# +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_CADENCE is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_FTGPIO010 is not set +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SYSCON is not set +# CONFIG_GPIO_XGENE is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_AMD_FCH is not set +# end of Memory mapped GPIO drivers + +# +# I2C GPIO expanders +# +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_PCA953X=y +# CONFIG_GPIO_PCA953X_IRQ is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_TPIC2810 is not set +# end of I2C GPIO expanders + +# +# MFD GPIO expanders +# +# end of MFD GPIO expanders + +# +# PCI GPIO expanders +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_PCI_IDIO_16 is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +# CONFIG_GPIO_RDC321X is not set +# end of PCI GPIO expanders + +# +# SPI GPIO expanders +# +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_XRA1403 is not set +# end of SPI GPIO expanders + +# +# USB GPIO expanders +# +# end of USB GPIO expanders + +# CONFIG_GPIO_MOCKUP is not set +CONFIG_FREEBOX_GPIO=y +CONFIG_FREEBOX_GPIO_DT=y +# CONFIG_FREEBOX_JTAG is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +CONFIG_POWER_RESET=y +# CONFIG_POWER_RESET_BRCMSTB is not set +# CONFIG_POWER_RESET_GPIO is not set +# CONFIG_POWER_RESET_GPIO_RESTART is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_RESET_XGENE is not set +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +# CONFIG_SYSCON_REBOOT_MODE is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_POWER_SUPPLY_HWMON is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_MANAGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_RT9455 is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +CONFIG_SENSORS_ADT7475=y +# CONFIG_SENSORS_AS370 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31722 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_LD6710_FBX=m +# CONFIG_SENSORS_AP806 is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_STATISTICS=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +# CONFIG_THERMAL_HWMON is not set +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_BANG_BANG=y +CONFIG_THERMAL_GOV_USER_SPACE=y +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +# CONFIG_CPU_THERMAL is not set +# CONFIG_CLOCK_THERMAL is not set +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_MMIO is not set +# CONFIG_QORIQ_THERMAL is not set +CONFIG_FREEBOX_WATCHDOG=y +# CONFIG_FREEBOX_WATCHDOG_CHAR is not set +CONFIG_FREEBOX_WATCHDOG_BCM63XX_OF=y +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77620 is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_STPMIC1 is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_FBXGW7R_PANEL is not set +# CONFIG_RAVE_SP_CORE is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +CONFIG_RC_CORE=y +# CONFIG_RC_MAP is not set +# CONFIG_LIRC is not set +# CONFIG_RC_DECODERS is not set +# CONFIG_RC_DEVICES is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +# CONFIG_MEDIA_CAMERA_SUPPORT is not set +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_SDR_SUPPORT is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_DVB_CORE=y +# CONFIG_DVB_NET is not set +CONFIG_DVB_MAX_ADAPTERS=8 +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_ULE_DEBUG is not set + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Analog/digital TV USB devices +# + +# +# Digital TV USB devices +# +CONFIG_DVB_USB=y +# CONFIG_DVB_USB_DEBUG is not set +# CONFIG_DVB_USB_A800 is not set +# CONFIG_DVB_USB_DIBUSB_MB is not set +# CONFIG_DVB_USB_DIBUSB_MC is not set +CONFIG_DVB_USB_DIB0700=m +# CONFIG_DVB_USB_UMT_010 is not set +# CONFIG_DVB_USB_CXUSB is not set +# CONFIG_DVB_USB_M920X is not set +# CONFIG_DVB_USB_DIGITV is not set +# CONFIG_DVB_USB_VP7045 is not set +# CONFIG_DVB_USB_VP702X is not set +# CONFIG_DVB_USB_GP8PSK is not set +# CONFIG_DVB_USB_NOVA_T_USB2 is not set +# CONFIG_DVB_USB_TTUSB2 is not set +# CONFIG_DVB_USB_DTT200U is not set +# CONFIG_DVB_USB_OPERA1 is not set +# CONFIG_DVB_USB_AF9005 is not set +# CONFIG_DVB_USB_PCTV452E is not set +# CONFIG_DVB_USB_DW2102 is not set +# CONFIG_DVB_USB_CINERGY_T2 is not set +# CONFIG_DVB_USB_DTV5100 is not set +# CONFIG_DVB_USB_AZ6027 is not set +# CONFIG_DVB_USB_TECHNISAT_USB2 is not set +CONFIG_DVB_USB_V2=y +# CONFIG_DVB_USB_AF9015 is not set +CONFIG_DVB_USB_AF9035=m +# CONFIG_DVB_USB_ANYSEE is not set +# CONFIG_DVB_USB_AU6610 is not set +# CONFIG_DVB_USB_AZ6007 is not set +# CONFIG_DVB_USB_CE6230 is not set +# CONFIG_DVB_USB_EC168 is not set +# CONFIG_DVB_USB_GL861 is not set +# CONFIG_DVB_USB_LME2510 is not set +# CONFIG_DVB_USB_MXL111SF is not set +# CONFIG_DVB_USB_RTL28XXU is not set +# CONFIG_DVB_USB_DVBSKY is not set +# CONFIG_DVB_USB_ZD1301 is not set +# CONFIG_DVB_TTUSB_BUDGET is not set +# CONFIG_DVB_TTUSB_DEC is not set +# CONFIG_SMS_USB_DRV is not set +# CONFIG_DVB_B2C2_FLEXCOP_USB is not set +# CONFIG_DVB_AS102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_MEDIA_PCI_SUPPORT is not set +# CONFIG_DVB_PLATFORM_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_SMS_SDIO_DRV is not set +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) +# +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_MEDIA_ATTACH=y + +# +# Media SPI Adapters +# +# CONFIG_CXD2880_SPI_DRV is not set +# end of Media SPI Adapters + +CONFIG_MEDIA_TUNER=y + +# +# Customize TV tuners +# +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA18250 is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_XC4000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +CONFIG_MEDIA_TUNER_IT913X=m +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# end of Customize TV tuners + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +CONFIG_DVB_M88DS3103=m + +# +# Multistandard (cable + terrestrial) frontends +# +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set + +# +# DVB-S (satellite) frontends +# +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set + +# +# DVB-T (terrestrial) frontends +# +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +CONFIG_DVB_AF9013=m +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +CONFIG_DVB_RTL2830=m +CONFIG_DVB_RTL2832=m +CONFIG_DVB_SI2168=m +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_CXD2880 is not set + +# +# DVB-C (cable) frontends +# +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +CONFIG_DVB_LGDT3306A=m +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_S5H1411 is not set + +# +# ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set + +# +# ISDB-S (satellite) & ISDB-T (terrestrial) frontends +# +# CONFIG_DVB_TC90522 is not set +# CONFIG_DVB_MN88443X is not set + +# +# Digital terrestrial only tuners/PLL +# +# CONFIG_DVB_PLL is not set +CONFIG_DVB_TUNER_DIB0070=m +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# SEC control devices for DVB-S +# +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +CONFIG_DVB_AF9033=m +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set + +# +# Common Interface (EN50221) controller drivers +# +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set +# end of Customise DVB Frontends + +# +# Graphics support +# +# CONFIG_VGA_ARB is not set +# CONFIG_DRM is not set +# CONFIG_DRM_DP_CEC is not set + +# +# ARM devices +# +# end of ARM devices + +# +# ACP (Audio CoProcessor) Configuration +# +# end of ACP (Audio CoProcessor) Configuration + +CONFIG_DRM_RCAR_WRITEBACK=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_BACKLIGHT=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_ARMCLCD is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_FB_SM712 is not set +CONFIG_FB_SSD1320=y +# CONFIG_FB_SSD1327 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_GPIO is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# end of Backlight & LCD device support + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +# CONFIG_FRAMEBUFFER_CONSOLE is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +# CONFIG_HIDRAW is not set +# CONFIG_UHID is not set +# CONFIG_HID_GENERIC is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PLANTRONICS is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +# CONFIG_USB_HID is not set +# CONFIG_HID_PID is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set +# end of USB HID Boot Protocol drivers +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_PCI is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PLATFORM=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +CONFIG_USB_BCM63158=m +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_CHAOSKEY is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +# CONFIG_USB_ULPI is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set +# CONFIG_MMC_SDHCI_CADENCE is not set +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQHCI is not set +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_MTK is not set +CONFIG_MMC_SDHCI_BRCMSTB=y +# CONFIG_MMC_SDHCI_XENON is not set +# CONFIG_MMC_SDHCI_OMAP is not set +# CONFIG_MMC_SDHCI_AM654 is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_AN30259A is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_CR0014114 is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_LM3692X is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP3952 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_LP8860 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_IS31FL319X is not set +# CONFIG_LEDS_IS31FL32XX is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_SYSCON is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_LED1202 is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_MTD is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set +# CONFIG_VIRTIO_MENU is not set + +# +# Microsoft Hyper-V guest support +# +# end of Microsoft Hyper-V guest support + +# CONFIG_GREYBUS is not set +# CONFIG_STAGING is not set +# CONFIG_GOLDFISH is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +# CONFIG_FBXGW7R_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_VERSATILE is not set +# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI514 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_CLK_QORIQ is not set +# CONFIG_COMMON_CLK_XGENE is not set +# CONFIG_COMMON_CLK_VC5 is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# end of Common Clock Framework + +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +CONFIG_FSL_ERRATUM_A008585=y +CONFIG_HISILICON_ERRATUM_161010101=y +CONFIG_ARM64_ERRATUM_858921=y +# end of Clock Source drivers + +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# CONFIG_SOC_BRCMSTB is not set +CONFIG_SOC_BCM63XX=y +CONFIG_UBUS4_BCM63158=y +CONFIG_PROCMON_BCM63158=y +# CONFIG_SOC_BCM63XX_RDP is not set +CONFIG_SOC_BCM63XX_XRDP=y +# CONFIG_SOC_BCM63XX_XRDP_IOCTL is not set +CONFIG_SOC_MEMC_BCM63158=m +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_MAX_NR=1 +CONFIG_ARM_GIC_V2M=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_GIC_V3_ITS_PCI=y +# CONFIG_AL_FIC is not set +CONFIG_PARTITION_PERCPU=y +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_TI_SYSCON is not set + +# +# PHY Subsystem +# +CONFIG_GENERIC_PHY=y +# CONFIG_PHY_XGENE is not set +CONFIG_XDSL_PHY_API=m +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# CONFIG_ARM_CCI_PMU is not set +# CONFIG_ARM_CCN is not set +CONFIG_ARM_PMU=y +# CONFIG_ARM_DSU_PMU is not set +# CONFIG_ARM_SPE_PMU is not set +# end of Performance monitor support + +CONFIG_RAS=y + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_IGNORE_RO is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +CONFIG_TEE=y + +# +# TEE drivers +# +CONFIG_OPTEE=y +CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1 +# end of TEE drivers + +CONFIG_PM_OPP=y +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_VALIDATE_FS_PARSER is not set +CONFIG_FS_IOMAP=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_ONLINE_SCRUB is not set +# CONFIG_XFS_WARN is not set +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set +# CONFIG_VIRTIO_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=850 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +# CONFIG_NTFS_RW is not set +CONFIG_EXFAT_FS_FBX=y +# end of DOS/FAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +# CONFIG_HUGETLBFS is not set +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +CONFIG_HFS_FS=y +CONFIG_HFSPLUS_FS=y +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_CRAMFS=y +CONFIG_CRAMFS_BLOCKDEV=y +CONFIG_CRAMFS_MTD=y +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SQUASHFS_LZ4 is not set +# CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_ZSTD is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +# CONFIG_PSTORE_DEFLATE_COMPRESS is not set +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=y +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +# CONFIG_NFSD_BLOCKLAYOUT is not set +# CONFIG_NFSD_SCSILAYOUT is not set +# CONFIG_NFSD_FLEXFILELAYOUT is not set +CONFIG_SMB_SERVER=y +CONFIG_SMB_INSECURE_SERVER=y +CONFIG_SMB_SERVER_CHECK_CAP_NET_ADMIN=y +# CONFIG_SMB_SERVER_KERBEROS5 is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +# end of File systems + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="yama,loadpin,safesetid,integrity" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_KPP=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Public-key cryptography +# +# CONFIG_CRYPTO_RSA is not set +# CONFIG_CRYPTO_DH is not set +CONFIG_CRYPTO_ECC=y +CONFIG_CRYPTO_ECDH=y +# CONFIG_CRYPTO_ECRDSA is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CHACHA20POLY1305=y +# CONFIG_CRYPTO_AEGIS128 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_ESSIV=y + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_POLY1305=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SHA3=y +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +CONFIG_CRYPTO_CHACHA20=y +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +# CONFIG_CRYPTO_HW is not set + +# +# Certificates for signature checking +# +# end of Certificates for signature checking + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +# CONFIG_CORDIC is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +# CONFIG_INDIRECT_PIO is not set +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_REED_SOLOMON=y +CONFIG_REED_SOLOMON_ENC8=y +CONFIG_REED_SOLOMON_DEC8=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_ARCH_HAS_SETUP_DMA_OPS=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_SWIOTLB=y +CONFIG_DMA_REMAP=y +CONFIG_DMA_DIRECT_REMAP=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +# CONFIG_IRQ_POLL is not set +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONT_8x16=y +CONFIG_FONT_AUTOSELECT=y +CONFIG_SG_POOL=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +CONFIG_ARCH_HAS_FBXSERIAL=y +CONFIG_FBXSERIAL=y +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_INSTALL is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_MISC is not set + +# +# Memory Debugging +# +CONFIG_PAGE_EXTENSION=y +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y +# CONFIG_PAGE_OWNER is not set +CONFIG_PAGE_POISONING=y +CONFIG_PAGE_POISONING_NO_SANITY=y +# CONFIG_PAGE_POISONING_ZERO is not set +# CONFIG_DEBUG_RODATA_TEST is not set +CONFIG_DEBUG_OBJECTS=y +CONFIG_DEBUG_OBJECTS_SELFTEST=y +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y +CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set +# CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN is not set +# CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_DEBUG_VM=y +# CONFIG_DEBUG_VM_VMACACHE is not set +CONFIG_DEBUG_VM_RB=y +CONFIG_DEBUG_VM_PGFLAGS=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_DEBUG_VIRTUAL=y +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y +CONFIG_CC_HAS_KASAN_GENERIC=y +# CONFIG_KASAN is not set +CONFIG_KASAN_STACK=1 +# end of Memory Debugging + +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Lockups and Hangs +# +# CONFIG_SOFTLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=1 +# CONFIG_WQ_WATCHDOG is not set +# end of Debug Lockups and Hangs + +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=10 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +CONFIG_DEBUG_TIMEKEEPING=y + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +CONFIG_HAVE_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_PLIST is not set +CONFIG_DEBUG_SG=y +CONFIG_DEBUG_NOTIFIERS=y +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +# CONFIG_DEBUG_WX is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +# CONFIG_ARM64_RELOC_TEST is not set +# CONFIG_CORESIGHT is not set +# end of Kernel hacking --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/cpufreq/bcm63158-cpufreq.c 2021-03-04 13:20:57.690838885 +0100 @@ -0,0 +1,431 @@ +/* + * bcm63158-cpufreq.c for bcm63158-cpufreq + * Created by on Fri Jun 26 16:07:36 2020 + */ + +#include +#include +#include +#include +#include +#include + +#include + +struct bcm63158_cpufreq { + struct bcm63xx_pmc *pmc; + struct device *dev; + struct cpufreq_driver drv; + struct cpufreq_frequency_table *freq_table; +}; + +/* + * CPU frequency change on 63158 + */ +#define BIU_PLL_RESET_REG (0x4 << 2) +#define BIU_PLL_RESET_BYP_EN (1 << 20) +#define BIU_PLL_RESET_PLL_RST (1 << 3) + +#define BIU_PLL_PDIV_REG (0x8 << 2) +#define BIU_PLL_PDIV_NDIV_OVERRIDE (1 << 31) + +#define BIU_PLL_NDIV_REG (0x7 << 2) +#define BIU_PLL_NDIV_NDIV_MASK (0x3ff) + +#define BIU_PLL_POSTDIV_REG (0xb << 2) +#define BIU_PLL_POSTDIV_DIV0_MASK (0xff) +#define BIU_PLL_POSTDIV_DIV0_OVERRIDE (1 << 15) + +#define BIU_PLL_STAT_REG (0xf << 2) +#define BIU_PLL_STAT_PLL_LOCK (1 << 31) + +static void biu_pll_bypass_enable(struct bcm63xx_pmc *pmc, bool en) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, ®); + + if (en) + reg |= BIU_PLL_RESET_BYP_EN; + else + reg &= ~BIU_PLL_RESET_BYP_EN; + + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, reg); +} + +static bool biu_pll_get_bypass_enable(struct bcm63xx_pmc *pmc) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, ®); + return !!(reg & BIU_PLL_RESET_BYP_EN); +} + +static void biu_pll_reset_assert(struct bcm63xx_pmc *pmc, bool en) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, ®); + if (en) + reg |= BIU_PLL_RESET_PLL_RST; + else + reg &= ~BIU_PLL_RESET_PLL_RST; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_RESET_REG, reg); +} + +static void biu_pll_set_ndiv_override(struct bcm63xx_pmc *pmc, bool en) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_PDIV_REG, ®); + if (en) + reg |= BIU_PLL_PDIV_NDIV_OVERRIDE; + else + reg &= ~BIU_PLL_PDIV_NDIV_OVERRIDE; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_PDIV_REG, reg); +} + +static u32 biu_pll_get_ndiv(struct bcm63xx_pmc *pmc) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_NDIV_REG, ®); + return reg & BIU_PLL_NDIV_NDIV_MASK; +} + +static void biu_pll_set_ndiv(struct bcm63xx_pmc *pmc, u32 ndiv) +{ + u32 reg; + + ndiv &= BIU_PLL_NDIV_NDIV_MASK; + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_NDIV_REG, ®); + reg &= ~BIU_PLL_NDIV_NDIV_MASK; + reg |= ndiv; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_NDIV_REG, reg); +} + +static u32 biu_pll_get_mdiv(struct bcm63xx_pmc *pmc) +{ + u32 reg; + + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + ®); + + return reg & BIU_PLL_POSTDIV_DIV0_MASK; +} + +static void biu_pll_set_mdiv(struct bcm63xx_pmc *pmc, u8 mdiv) +{ + u32 reg; + + if (mdiv == biu_pll_get_mdiv(pmc)) + return ; + + mdiv &= BIU_PLL_POSTDIV_DIV0_MASK; + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + ®); + reg &= ~BIU_PLL_POSTDIV_DIV0_OVERRIDE; + reg &= ~BIU_PLL_POSTDIV_DIV0_MASK; + reg |= mdiv; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + reg); + usleep_range(1000, 1200); + + reg |= BIU_PLL_POSTDIV_DIV0_OVERRIDE; + pmc_write_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_POSTDIV_REG, + reg); + usleep_range(10000, 12000); +} + +static int biu_pll_wait_lock(struct bcm63xx_pmc *pmc) +{ + int tries = 1000; + + do { + u32 reg; + pmc_read_bpcm_register(pmc, PMB_ADDR_BIU_PLL, BIU_PLL_STAT_REG, + ®); + + if (reg & BIU_PLL_STAT_PLL_LOCK) + break; + usleep_range(1000, 2000); + --tries; + } while (tries > 0); + + return tries > 0 ? 0 : -ETIMEDOUT; +} + +/* + * unless bypass clock is enabled, cpu frequency in mhz is: + * + * 50 * ndiv / mdiv + * + * mdiv is usually 2, unless for CPU speeds higher than 1675 mhz, in + * which case it is 1. + */ +static int pmc_cpufreq_get(struct bcm63158_cpufreq *priv) +{ + struct bcm63xx_pmc *pmc = priv->pmc; + u32 ndiv; + u32 mdiv; + + if (biu_pll_get_bypass_enable(pmc)) { + /* + * 400 mhz slow clock cpu clocking is active. + */ + return 400; + } + + ndiv = biu_pll_get_ndiv(pmc); + mdiv = biu_pll_get_mdiv(pmc); + return 50 * ndiv / mdiv; +} + +/* + * this will change the CPU speed to the requested frequency. + * + * valid frequencies are: 400, then 550 to 1675 mhz, frequency is + * rounted down to the nearest 25mhz. Frequencies from 1700 to 2200 + * mhz are possible, rounded down to the nearest 50 mhz. + * + * Frequencies from 1700 to 2200 Mhz are in the overclocking range and + * the CPU may not work reliably in that case. + */ +static int pmc_cpufreq_set(struct bcm63158_cpufreq *priv, unsigned int val) +{ + struct bcm63xx_pmc *pmc = priv->pmc; + u32 mdiv, ndiv; + int error; + u32 ndiv_lo, ndiv_hi; + + val /= 1000; + + if (val > 2200) + return -EINVAL; + + if (val > 1675) { + mdiv = 1; + ndiv_lo = 34; + ndiv_hi = 44; + } else { + mdiv = 2; + ndiv_lo = 22; + ndiv_hi = 67; + } + + ndiv = mdiv * val / 50; + + if ((ndiv < ndiv_lo || ndiv > ndiv_hi) && val != 400) { + dev_warn(priv->dev, "%u: unsupported frequency.\n", val); + return -EINVAL; + } + + /* + * enabling bypass clock will clock the CPU at 400 mhz from a + * clock that will remain stable while we configure the + * divisors. + */ + biu_pll_bypass_enable(pmc, true); + biu_pll_reset_assert(pmc, true); + + if (val == 400) + /* + * just leave the system with the slow clock strap + * frequency. + */ + return 0; + + /* + * set ndiv + */ + biu_pll_set_ndiv_override(pmc, true); + biu_pll_set_ndiv(pmc, ndiv); + + /* + * deassert PLL and wait for it to lock. + */ + biu_pll_reset_assert(pmc, false); + error = biu_pll_wait_lock(pmc); + if (error) { + /* + * if the pll fails to lock it looks like the system + * will be left in a usable state as long as we keep + * the bypass enabled. cpu freq will be 400 Mhz, the + * slow clock strap freq. + */ + dev_crit(priv->dev, "BIU pll failed to lock. " + "leaving PLL bypass enabled (%u Mhz was wanted).\n", + val); + return error; + } + + /* + * set post divider (mdiv) + */ + biu_pll_set_mdiv(pmc, mdiv); + + /* + * disable clock bypass, the cpu will after be clocked at the + * requested frequency. + */ + biu_pll_bypass_enable(pmc, false); + return 0; +} + +static int bcm63158_cpufreq_init(struct cpufreq_policy *policy) +{ + struct bcm63158_cpufreq *priv = cpufreq_get_driver_data(); + + policy->cpuinfo.max_freq = 1675000; + policy->cpuinfo.min_freq = 400000; + policy->cur = pmc_cpufreq_get(priv) * 1000; + policy->cpuinfo.transition_latency = 20 * 1000 * 1000; /* 20 msec */ + policy->freq_table = priv->freq_table; + policy->driver_data = cpufreq_get_driver_data(); + + /* + * All cores share the same clock and thus the same policy. + */ + cpumask_setall(policy->cpus); + + return 0; +} + +static int bcm63158_cpufreq_target_index(struct cpufreq_policy *policy, + unsigned int index) +{ + struct bcm63158_cpufreq *priv = policy->driver_data; + + pmc_cpufreq_set(priv, policy->freq_table[index].frequency); + return 0; +} + +static int add_freq_entry(struct cpufreq_frequency_table *tbl, + unsigned int freq_mhz, size_t *cur, size_t size) +{ + if (*cur >= size) { + pr_err("unable to add frequency %u to table: no room left.\n", + freq_mhz); + return -ENOSPC; + } + + tbl = &tbl[*cur]; + tbl->frequency = freq_mhz ? (freq_mhz * 1000) : CPUFREQ_TABLE_END; + ++(*cur); + return 0; +} + +/* + * NOTE: the hardware could do 550 Mhz, but in some case the BIU PLL + * won't lock at that frequency. just don't advertise 550 Mhz in the + * frequency table. + */ +#define FREQ_LOW 575 +#define FREQ_HI 1575 + +/* + * the hardware can work in 25 mhz frequency increments, but it's + * probably not needed that much to have this kind of granularity. + * + * Also the 45 possible frequencies make it that the stats/trans_table + * sysfs attribute cannot work due to its content being larger than 4k + * (the max for sysfs attributes). + * + * allow all frequencies between FREQ_LO and FREQ_HI in 100 mhz + * increment as a result. + */ +#define FREQ_INC 100 + +static int bcm63158_cpufreq_build_table(struct bcm63158_cpufreq *priv) +{ + size_t nr_freqs; + size_t cur_freq; + unsigned int freq; + struct cpufreq_frequency_table *table; + int error; + + nr_freqs = (FREQ_HI - FREQ_LOW) / FREQ_INC + 1; + nr_freqs += 2; /* account for 400 mhz entry and end element */ + + table = devm_kzalloc(priv->dev, sizeof (*table) * nr_freqs, + GFP_KERNEL); + if (!table) + return -ENOMEM; + + cur_freq = 0; + error = add_freq_entry(table, 400, &cur_freq, nr_freqs); + if (error) + return error; + + for (freq = FREQ_LOW; freq <= FREQ_HI; freq += FREQ_INC) { + error = add_freq_entry(table, freq, &cur_freq, nr_freqs); + if (error) + return error; + } + + error = add_freq_entry(table, 0, &cur_freq, nr_freqs); + if (error) + return error; + + priv->freq_table = table; + return 0; +} + +static int bcm63158_cpufreq_probe(struct platform_device *pdev) +{ + struct bcm63158_cpufreq *priv; + int err; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pmc = pmc_of_get(pdev->dev.of_node); + if (IS_ERR(priv)) + return PTR_ERR(priv); + + + dev_set_drvdata(&pdev->dev, priv); + + strlcpy(priv->drv.name, "bcm63158-cpufreq", sizeof (priv->drv.name)); + priv->drv.init = bcm63158_cpufreq_init; + priv->drv.verify = cpufreq_generic_frequency_table_verify; + priv->drv.target_index = bcm63158_cpufreq_target_index; + priv->drv.driver_data = priv; + priv->drv.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK; + priv->dev = &pdev->dev; + + err = bcm63158_cpufreq_build_table(priv); + if (err) + return err; + + return cpufreq_register_driver(&priv->drv); +} + +static int __exit bcm63158_cpufreq_remove(struct platform_device *pdev) +{ + struct bcm63158_cpufreq *priv = dev_get_drvdata(&pdev->dev); + + cpufreq_unregister_driver(&priv->drv); + return 0; +} + +static const struct of_device_id bcm63158_cpufreq_of_match[] = { + { .compatible = "brcm,bcm63158-cpufreq" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63158_cpufreq_of_match); + +static struct platform_driver bcm63158_cpufreq_pdriver = { + .driver = { + .name = "bcm63158-cpufreq", + .of_match_table = bcm63158_cpufreq_of_match, + }, + .probe = bcm63158_cpufreq_probe, + .remove = bcm63158_cpufreq_remove, +}; +module_platform_driver(bcm63158_cpufreq_pdriver); + +MODULE_AUTHOR("Nicolas Schichan +#include +#include +#include +#include +#include +#include +#include + +#define PFX "fbxgpio_core: " + +/* #define DEBUG */ +#ifdef DEBUG +#define dprint(Fmt, Arg...) printk(PFX Fmt, Arg) +#else +#define dprint(Fmt, Arg...) do { } while (0) +#endif + +static struct class *fbxgpio_class; + +/* + * retrieval of a struct fbxgpio_pin from a phandle in the device + * tree. + */ +struct fbxgpio_of_mach_data { + struct fbxgpio_pin *match; + struct device_node *np; +}; + +static int match_fbxgpio_of_node(struct device *dev, void *data) +{ + struct fbxgpio_of_mach_data *md = data; + struct fbxgpio_pin *pin = dev_get_drvdata(dev); + + if (pin->of_node == md->np) { + md->match = pin; + return 1; + } + return 0; +} + +struct fbxgpio_pin *fbxgpio_of_get(struct device_node *np, const char *propname, + int index) +{ + struct fbxgpio_of_mach_data md; + + /* + * get the pin device_node. + */ + md.match = NULL; + md.np = of_parse_phandle(np, propname, index); + if (!md.np) + return ERR_PTR(-ENOENT); + + /* + * find the struct fbxgpio_pin behind that device_node. + */ + class_for_each_device(fbxgpio_class, NULL, &md, + match_fbxgpio_of_node); + + return md.match ? md.match : ERR_PTR(-ENOENT); +} +EXPORT_SYMBOL(fbxgpio_of_get); + +/* + * show direction in for gpio associated with class_device dev. + */ +static ssize_t show_direction(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + int dir, ret = 0; + + p = dev_get_drvdata(dev); + + if (p->ops->get_direction) + dir = p->ops->get_direction(p->pin_num); + else + dir = p->direction; + + switch (dir) { + case GPIO_DIR_IN: + ret += sprintf(buf, "input\n"); + break; + case GPIO_DIR_OUT: + ret += sprintf(buf, "output\n"); + break; + default: + ret += sprintf(buf, "unknown\n"); + break; + } + return ret; +} + +/* + * store direction. return -EINVAL if direction string is bad. return + * -EPERM if flag FBXGPIO_PIN_DIR_RW is set in flags. + */ +static ssize_t store_direction(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int dir; + struct fbxgpio_pin *p; + int match_len = 0; + int i, ret; + static const char *word_match[] = { + [GPIO_DIR_IN] = "input", + [GPIO_DIR_OUT] = "output", + }; + + if (*buf == ' ' || *buf == '\t' || *buf == '\r' || *buf == '\n') + /* silently eat any spaces/tab/linefeed/carriagereturn */ + return 1; + + p = dev_get_drvdata(dev); + if (!(p->flags & FBXGPIO_PIN_DIR_RW)) { + dprint("pin %s direction is read only.\n", p->pin_name); + return -EPERM; + } + dir = 0; + for (i = 0; i < 2; ++i) { + if (size >= strlen(word_match[i]) && + !strncmp(buf, word_match[i], strlen(word_match[i]))) { + dir = i; + match_len = strlen(word_match[i]); + break ; + } + } + if (i == 2) + return -EINVAL; + + ret = p->ops->set_direction(p->pin_num, dir); + if (ret) + return ret; + p->direction = dir; + + return match_len; +} + +/* + * show input data for input gpio pins. + */ +static ssize_t show_datain(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_OUT) + return -EINVAL; + val = p->ops->get_datain(p->pin_num); + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + return sprintf(buf, "%i\n", val); +} + +/* + * show output data for output gpio pins. + */ +static ssize_t show_dataout(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int val; + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + if (p->direction == GPIO_DIR_IN) + return -EINVAL; + if (p->ops->get_dataout) + val = p->ops->get_dataout(p->pin_num); + else + val = p->cur_dataout; + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + return sprintf(buf, "%i\n", val); +} + +/* + * store new dataout value for output gpio pins. + */ +static ssize_t store_dataout(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + int val; + struct fbxgpio_pin *p; + + if (*buf == ' ' || *buf == '\t' || *buf == '\r' || *buf == '\n') + /* silently eat any spaces/tab/linefeed/carriagereturn */ + return 1; + + p = dev_get_drvdata(dev); + + if (p->direction != GPIO_DIR_OUT) + return -EINVAL; + + switch (*buf) { + case '0': + val = 0; + break ; + case '1': + val = 1; + break ; + default: + return -EINVAL; + } + + p->cur_dataout = val; + + if (p->flags & FBXGPIO_PIN_REVERSE_POL) + val = 1 - val; + p->ops->set_dataout(p->pin_num, val); + return 1; +} + +/* + * show pin number associated with gpio pin. + */ +static ssize_t show_pinnum(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxgpio_pin *p; + + p = dev_get_drvdata(dev); + return sprintf(buf, "%i\n", p->pin_num); +} + +/* + * attribute list associated with each class device. + */ +static struct device_attribute gpio_attributes[] = { + __ATTR(direction, 0600, show_direction, store_direction), + __ATTR(data_in, 0400, show_datain, NULL), + __ATTR(data_out, 0600, show_dataout, store_dataout), + __ATTR(pin_num, 0400, show_pinnum, NULL), +}; + +static int fbxgpio_register_pin(struct platform_device *ppdev, + struct fbxgpio_pin *pin) +{ + struct device *dev; + int i, ret; + + dprint("registering pin %s\n", pin->pin_name); + + /* ensure ops is valid */ + if (!pin->ops) { + printk(KERN_ERR PFX "no operation set for pin %s\n", + pin->pin_name); + return -EINVAL; + } + + dev = device_create(fbxgpio_class, &ppdev->dev, 0, pin, + "%s", pin->pin_name); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) { + ret = device_create_file(dev, &gpio_attributes[i]); + if (ret) + goto err_out; + } + + /* ensure pin direction matches hardware state */ + if (pin->ops->get_direction && + pin->direction != pin->ops->get_direction(pin->pin_num)) { + printk(KERN_WARNING PFX "pin %s default direction does not " + "match current hardware state, fixing.\n", + pin->pin_name); + pin->ops->set_direction(pin->pin_num, pin->direction); + } + pin->dev = dev; + return 0; + +err_out: + for (; i >= 0; i--) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); + return ret; +} + +static void fbxgpio_unregister_pin(struct fbxgpio_pin *pin) +{ + struct device *dev; + int i; + + dprint("unregistering pin %s\n", pin->pin_name); + dev = pin->dev; + pin->dev = NULL; + + for (i = 0; i < ARRAY_SIZE(gpio_attributes); i++) + device_remove_file(dev, &gpio_attributes[i]); + device_unregister(dev); +} + +static int fbxgpio_platform_probe(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + int err = 0; + + p = pdev->dev.platform_data; + while (p->pin_name) { + err = fbxgpio_register_pin(pdev, p); + if (err) + return err; + ++p; + } + return 0; +} + +static int fbxgpio_platform_remove(struct platform_device *pdev) +{ + struct fbxgpio_pin *p; + + p = pdev->dev.platform_data; + while (p->pin_name) { + fbxgpio_unregister_pin(p); + ++p; + } + return 0; +} + +static struct platform_driver fbxgpio_platform_driver = +{ + .probe = fbxgpio_platform_probe, + .remove = fbxgpio_platform_remove, + .driver = { + .name = "fbxgpio", + } +}; + +static int __init fbxgpio_init(void) +{ + int ret; + + fbxgpio_class = class_create(THIS_MODULE, "fbxgpio"); + if (IS_ERR(fbxgpio_class)) + return PTR_ERR(fbxgpio_class); + + ret = platform_driver_register(&fbxgpio_platform_driver); + if (ret) { + printk(KERN_ERR PFX "unable to register fbxgpio driver.\n"); + class_destroy(fbxgpio_class); + return ret; + } + return 0; +} + +static void __exit fbxgpio_exit(void) +{ + platform_driver_unregister(&fbxgpio_platform_driver); + class_destroy(fbxgpio_class); +} + +subsys_initcall(fbxgpio_init); +module_exit(fbxgpio_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); diff -Nruw linux-5.4.60-fbx/drivers/fbxgpio./fbxgpio_dt.c linux-5.4.60-fbx/drivers/fbxgpio/fbxgpio_dt.c --- linux-5.4.60-fbx/drivers/fbxgpio./fbxgpio_dt.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxgpio/fbxgpio_dt.c 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,264 @@ +/* + * fbxgpio_dt.c for fbxgpio + * Created by on Tue Aug 1 14:01:01 2017 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static atomic_t last_id = ATOMIC_INIT(0); + +/* + * fbxgpio driver fetching gpios names and configuration from + * device-tree. + */ + +struct fbxgpio_dt_priv { + struct fbxgpio_pin *pins; + unsigned int npins; + + /* dynamically created platform_device for fbxgpio_core */ + struct platform_device *top_pdev; +}; + + +/* + * small shim layer for gpiolib <-> fbxgpio_operations. + * + * gpio direction change is unsupported, does userspace really need + * it? + */ +static int fbxgpio_dt_get_data(int gpio) +{ + return gpio_get_value_cansleep(gpio); +} + +static void fbxgpio_dt_set_dataout(int gpio, int value) +{ + gpio_set_value_cansleep(gpio, value); +} + +static int fbxgpio_dt_set_direction(int gpio, int dir) +{ + if (dir == GPIO_DIR_OUT) + return gpio_direction_output(gpio, 0); + else + return gpio_direction_input(gpio); +} + +static const struct fbxgpio_operations fbxgpio_dt_ops = { + .get_datain = fbxgpio_dt_get_data, + .get_dataout = fbxgpio_dt_get_data, + .set_dataout = fbxgpio_dt_set_dataout, + .set_direction = fbxgpio_dt_set_direction, +}; + +/* + * fill an fbxgpio_pin with the configuration found in a device tree + * node. + * + * required properties are: + * - gpio: a phandle to a standard linux gpio. + * + * - the name of the node: the name of the gpio as it will appear under + * /sys/class/fbxgpio/ + * + * - //: how to declare gpio and + * actually setup it unless no-claim is given + * + * - : just declare gpio, but don't request & setup it + */ +static int fbxgpio_dt_fill_gpio(struct platform_device *pdev, + struct device_node *np, + struct fbxgpio_pin *pin) +{ + enum of_gpio_flags flags; + int error; + + error = of_property_read_string(np, "name", &pin->pin_name); + if (error) { + dev_err(&pdev->dev, "gpio has no name.\n"); + return error; + } + + pin->pin_num = of_get_named_gpio_flags(np, "gpio", 0, &flags); + if (pin->pin_num < 0) { + if (pin->pin_num != -EPROBE_DEFER) + dev_err(&pdev->dev, + "unable to get gpio desc for %s: %d.\n", + pin->pin_name, pin->pin_num); + return pin->pin_num; + } + + if (of_property_read_bool(np, "input")) { + pin->direction = GPIO_DIR_IN; + } else if (of_property_read_bool(np, "output-low")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 0; + } else if (of_property_read_bool(np, "output-high")) { + pin->direction = GPIO_DIR_OUT; + pin->cur_dataout = 1; + } else { + dev_err(&pdev->dev, + "no state specified for %s\n", + pin->pin_name); + return -EINVAL; + } + + if (flags & OF_GPIO_ACTIVE_LOW) { + pin->flags |= FBXGPIO_PIN_REVERSE_POL; + if (pin->direction == GPIO_DIR_OUT) + pin->cur_dataout = 1 - pin->cur_dataout; + } + + if (!of_property_read_bool(np, "no-claim")) { + error = gpio_request(pin->pin_num, "fbxgpio-dt"); + if (error) { + dev_err(&pdev->dev, "unable to request gpio%d (%s): %d\n", + pin->pin_num, pin->pin_name, error); + return error; + } + pin->claimed = true; + + if (pin->direction == GPIO_DIR_OUT) + gpio_direction_output(pin->pin_num, pin->cur_dataout); + else + gpio_direction_input(pin->pin_num); + } + + if (of_property_read_bool(np, "bidir")) + pin->flags = FBXGPIO_PIN_DIR_RW; + + pin->of_node = np; + pin->ops = &fbxgpio_dt_ops; + return 0; +} + +static int fbxgpio_dt_probe(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv; + struct device_node *fbxgpio_node; + u32 cur_gpio; + int error = 0; + size_t priv_alloc_size; + int i; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, priv); + + /* + * first pass to get the number of struct fbxgpio_pin to + * allocate. + */ + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + ++priv->npins; + } + + /* + * allocate pins: use npins + 1 for zeroed end sentinel. + */ + priv_alloc_size = (priv->npins + 1) * sizeof (struct fbxgpio_pin); + priv->pins = devm_kzalloc(&pdev->dev, priv_alloc_size, GFP_KERNEL); + if (!priv->pins) + return -ENOMEM; + + /* + * second pass to fill the priv->pins array. + */ + cur_gpio = 0; + for_each_available_child_of_node(pdev->dev.of_node, fbxgpio_node) { + error = fbxgpio_dt_fill_gpio(pdev, fbxgpio_node, + &priv->pins[cur_gpio]); + if (error) + goto out_free_gpios; + ++cur_gpio; + } + + dev_info(&pdev->dev, "%u gpios.\n", priv->npins); + + /* + * create and register a platform device for fbxgpio_core. + */ + priv->top_pdev = platform_device_register_data(&pdev->dev, + "fbxgpio", + atomic_inc_return(&last_id), + priv->pins, + priv_alloc_size); + + if (IS_ERR(priv->top_pdev)) { + dev_err(&pdev->dev, "unable to register fbxgpio platform " + "device: %ld\n", PTR_ERR(priv->top_pdev)); + return PTR_ERR(priv->top_pdev); + } + + for (i = 0; i < priv->npins; i++) { + struct fbxgpio_pin *pin = &priv->pins[i]; + + if (pin->direction == GPIO_DIR_OUT) + dev_dbg(&pdev->dev, + "%sgpio %d (%s) is output, default %d\n", + pin->claimed ? "unclaimed " : "", + pin->pin_num, pin->pin_name, pin->cur_dataout); + else + dev_dbg(&pdev->dev, + "%sgpio %d (%s) is input\n", + pin->claimed ? "unclaimed " : "", + pin->pin_num, pin->pin_name); + } + + return 0; + +out_free_gpios: + while (cur_gpio) { + --cur_gpio; + if (priv->pins[cur_gpio].claimed) + gpio_free(priv->pins[cur_gpio].pin_num); + } + return error; +} + +static int fbxgpio_dt_remove(struct platform_device *pdev) +{ + struct fbxgpio_dt_priv *priv = dev_get_drvdata(&pdev->dev); + unsigned int i; + + platform_device_unregister(priv->top_pdev); + + for (i = 0; i < priv->npins; ++i) { + if (priv->pins[i].claimed) + gpio_free(priv->pins[i].pin_num); + } + + return 0; +} + +static const struct of_device_id fbxgpio_dt_of_match_table[] = { + { .compatible = "fbx,fbxgpio" }, + { }, +}; +MODULE_DEVICE_TABLE(of, fbxgpio_dt_of_match_table); + +static struct platform_driver fbxgpio_dt_platform_driver = { + .probe = fbxgpio_dt_probe, + .remove = fbxgpio_dt_remove, + .driver = { + .name = "fbxgpio-dt", + .of_match_table = fbxgpio_dt_of_match_table, + }, +}; + +module_platform_driver(fbxgpio_dt_platform_driver); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("DT Freebox GPIO Driver"); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-5.4.60-fbx/drivers/fbxgpio./Kconfig linux-5.4.60-fbx/drivers/fbxgpio/Kconfig --- linux-5.4.60-fbx/drivers/fbxgpio./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxgpio/Kconfig 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,7 @@ +config FREEBOX_GPIO + tristate "Freebox GPIO control interface" + default n + +config FREEBOX_GPIO_DT + tristate "Freebox GPIO DT binding." + default n diff -Nruw linux-5.4.60-fbx/drivers/fbxgpio./Makefile linux-5.4.60-fbx/drivers/fbxgpio/Makefile --- linux-5.4.60-fbx/drivers/fbxgpio./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxgpio/Makefile 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,2 @@ +obj-$(CONFIG_FREEBOX_GPIO) += fbxgpio_core.o +obj-$(CONFIG_FREEBOX_GPIO_DT) += fbxgpio_dt.o diff -Nruw linux-5.4.60-fbx/drivers/fbxjtag./Kconfig linux-5.4.60-fbx/drivers/fbxjtag/Kconfig --- linux-5.4.60-fbx/drivers/fbxjtag./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxjtag/Kconfig 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,3 @@ +config FREEBOX_JTAG + tristate "Freebox JTAG control interface" + default n diff -Nruw linux-5.4.60-fbx/drivers/fbxjtag./Makefile linux-5.4.60-fbx/drivers/fbxjtag/Makefile --- linux-5.4.60-fbx/drivers/fbxjtag./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxjtag/Makefile 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FREEBOX_JTAG) += fbxjtag.o diff -Nruw linux-5.4.60-fbx/drivers/fbxprocfs./fbxprocfs.c linux-5.4.60-fbx/drivers/fbxprocfs/fbxprocfs.c --- linux-5.4.60-fbx/drivers/fbxprocfs./fbxprocfs.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxprocfs/fbxprocfs.c 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,299 @@ +/* + * Freebox ProcFs interface + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define PFX "fbxprocfs: " + + +static struct list_head clients; +static struct mutex clients_mutex; + +static struct proc_dir_entry *root; + +/* + * register a fbxprocfs client with given dirname, caller should + * consider returned struct opaque + */ +struct fbxprocfs_client *fbxprocfs_add_client(const char *dirname, + struct module *owner) +{ + struct fbxprocfs_client *ret, *p; + + ret = NULL; + mutex_lock(&clients_mutex); + + /* check for duplicate */ + list_for_each_entry(p, &clients, list) { + if (!strcmp(dirname, p->dirname)) + goto out; + } + + if (!(ret = kmalloc(sizeof (*ret), GFP_KERNEL))) { + printk(KERN_ERR PFX "kmalloc failed\n"); + goto out; + } + + /* try to create client directory */ + if (!(ret->dir = proc_mkdir(dirname, root))) { + printk(KERN_ERR PFX "can't create %s dir\n", dirname); + kfree(ret); + ret = NULL; + goto out; + } + + atomic_set(&ret->refcount, 1); + ret->dirname = dirname; + list_add(&ret->list, &clients); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * unregister a fbxprocfs client, make sure usage count is zero + */ +int fbxprocfs_remove_client(struct fbxprocfs_client *client) +{ + int ret; + + mutex_lock(&clients_mutex); + + ret = 0; + if (atomic_read(&client->refcount) > 1) { + ret = -EBUSY; + goto out; + } + + remove_proc_entry(client->dirname, root); + list_del(&client->list); + kfree(client); + +out: + mutex_unlock(&clients_mutex); + return ret; +} + +/* + * remove given entries from client directory + */ +static int +__remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + remove_proc_entry(ro_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + remove_proc_entry(rw_desc[i].name, client->dir); + atomic_dec(&client->refcount); + } + + return 0; +} + +/* + * replacement for NULL rfunc. + */ +static int bad_rfunc(struct seq_file *m, void *ptr) +{ + return -EACCES; +} + +/* + * fbxprocfs write path is now handled by seq_file code. this + * simplifies client code greatly. + */ +static int fbxprocfs_open(struct inode *inode, struct file *file) +{ + const struct fbxprocfs_desc *desc = PDE_DATA(inode); + + return single_open(file, desc->rfunc ? desc->rfunc : bad_rfunc, + (void*)desc->id); +} + +/* + * no particular help from kernel in the write path, fetch user buffer + * in a kernel buffer and call write func. + */ +static ssize_t fbxprocfs_write(struct file *file, const char __user *ubuf, + size_t len, loff_t *off) +{ + /* + * get fbxprocfs desc via the proc_dir_entry in file inode + */ + struct fbxprocfs_desc *d = PDE_DATA(file_inode(file)); + char *kbuf; + int ret; + + /* + * must have a wfunc callback. + */ + if (!d->wfunc) + return -EACCES; + + /* + * allow up to SZ_4K bytes to be written. + */ + if (len > SZ_4K) + return -EOVERFLOW; + + /* + * alloc and fetch kernel buffer containing user data. + */ + kbuf = kmalloc(SZ_4K, GFP_KERNEL); + if (!kbuf) + return -ENOMEM; + + ret = -EFAULT; + if (copy_from_user(kbuf, ubuf, len)) + goto kfree; + + ret = d->wfunc(file, kbuf, len, (void*)d->id); + +kfree: + kfree(kbuf); + return ret; +} + +/* + * fbxprocfs file operations, read stuff is handled by seq_file code. + */ +static const struct file_operations fbxprocfs_fops = { + .open = fbxprocfs_open, + .llseek = seq_lseek, + .read = seq_read, + .release = single_release, + .write = fbxprocfs_write, +}; + +/* + * replaces create_proc_read_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_read_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, 0, base, &fbxprocfs_fops, + (void*)desc); +} + +/* + * replaces create_proc_entry removed in latest kernels. + */ +static struct proc_dir_entry *__create_proc_entry( + const struct fbxprocfs_desc *desc, + struct proc_dir_entry *base) +{ + return proc_create_data(desc->name, S_IFREG | S_IWUSR | S_IRUGO, + base, &fbxprocfs_fops, (void*)desc); +} + +/* + * create given entries in client directory + */ +static int +__create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + struct proc_dir_entry *proc; + int i; + + for (i = 0; ro_desc && ro_desc[i].name; i++) { + if (!(proc = __create_proc_read_entry(&ro_desc[i], + client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + for (i = 0; rw_desc && rw_desc[i].name; i++) { + if (!(proc = __create_proc_entry(&rw_desc[i], client->dir))) { + printk(KERN_ERR PFX "can't create %s/%s entry\n", + client->dirname, ro_desc[i].name); + goto err; + } + atomic_inc(&client->refcount); + } + + return 0; + +err: + __remove_entries(client, ro_desc, rw_desc); + return -1; +} + +int +fbxprocfs_create_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __create_entries(client, ro_desc, rw_desc); + return ret; +} + +int +fbxprocfs_remove_entries(struct fbxprocfs_client *client, + const struct fbxprocfs_desc *ro_desc, + const struct fbxprocfs_desc *rw_desc) +{ + int ret; + + ret = __remove_entries(client, ro_desc, rw_desc); + return ret; +} + + +static int __init +fbxprocfs_init(void) +{ + INIT_LIST_HEAD(&clients); + mutex_init(&clients_mutex); + + /* create freebox directory */ + if (!(root = proc_mkdir("freebox", NULL))) { + printk(KERN_ERR PFX "can't create freebox/ dir\n"); + return -EIO; + } + return 0; +} + +static void __exit +fbxprocfs_exit(void) +{ + remove_proc_entry("freebox", NULL); +} + +module_init(fbxprocfs_init); +module_exit(fbxprocfs_exit); + +EXPORT_SYMBOL(fbxprocfs_create_entries); +EXPORT_SYMBOL(fbxprocfs_remove_entries); +EXPORT_SYMBOL(fbxprocfs_add_client); +EXPORT_SYMBOL(fbxprocfs_remove_client); + +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_AUTHOR("Maxime Bizon "); + diff -Nruw linux-5.4.60-fbx/drivers/fbxprocfs./Kconfig linux-5.4.60-fbx/drivers/fbxprocfs/Kconfig --- linux-5.4.60-fbx/drivers/fbxprocfs./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxprocfs/Kconfig 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,2 @@ +config FREEBOX_PROCFS + tristate "Freebox procfs interface" diff -Nruw linux-5.4.60-fbx/drivers/fbxprocfs./Makefile linux-5.4.60-fbx/drivers/fbxprocfs/Makefile --- linux-5.4.60-fbx/drivers/fbxprocfs./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxprocfs/Makefile 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FREEBOX_PROCFS) += fbxprocfs.o diff -Nruw linux-5.4.60-fbx/drivers/fbxwatchdog./fbxwatchdog_bcm63xx_of.c linux-5.4.60-fbx/drivers/fbxwatchdog/fbxwatchdog_bcm63xx_of.c --- linux-5.4.60-fbx/drivers/fbxwatchdog./fbxwatchdog_bcm63xx_of.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxwatchdog/fbxwatchdog_bcm63xx_of.c 2021-03-30 15:48:29.471719189 +0200 @@ -0,0 +1,500 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fbxwatchdog.h" + +enum bcm63xx_wdt_reg { + /* Watchdog default count register */ + WDT_DEFVAL_REG, + /* Watchdog control register */ + WDT_CTL_REG, + /* Watchdog reset length register */ + WDT_RSTLEN_REG, +}; + +enum bcmtimer_chip_id { + WDT_6328, + WDT_63158, +}; + +static const u32 regs_offsets_6328[] = { + [WDT_DEFVAL_REG] = 0x28, + [WDT_CTL_REG] = 0x2c, + [WDT_RSTLEN_REG] = 0x30, +}; + +static const u32 regs_offsets_63158[] = { + [WDT_DEFVAL_REG] = 0xc0, + [WDT_CTL_REG] = 0xc4, + [WDT_RSTLEN_REG] = 0xc8, +}; + +#define PERF_TIMER64_RESET_REASON 0x48 +#define PERF_TIMER64_RESET_REASON_WD0 (1 << 31) +#define PERF_TIMER64_RESET_REASON_WD1 (1 << 30) +#define PERF_TIMER64_RESET_REASON_USR_MASK 0xff +#define PERF_TIMER64_RESET_REASON_USR_PANPAN 'P' + +/* Watchdog control register constants */ +#define WDT_START_1 (0xff00) +#define WDT_START_2 (0x00ff) +#define WDT_STOP_1 (0xee00) +#define WDT_STOP_2 (0x00ee) + +#define PFX "fbxwatchdog_bcm63xx: " + +struct bcm_priv { + void __iomem *regs; + void __iomem *reg_top_reset_status; + const u32 *regs_offsets; + int irq; + enum bcmtimer_chip_id chip_id; + struct platform_device *pdev; + + struct notifier_block panic_notifier; + u32 timer64_reset_reason; + u32 top_reset_status; +}; + +#define nb_to_bcm_priv(nb) container_of(nb, struct bcm_priv, \ + panic_notifier) + +/* + * io helpers to access mac registers + */ +static inline u32 wdt_readl(struct bcm_priv *priv, enum bcm63xx_wdt_reg reg) +{ + return readl(priv->regs + priv->regs_offsets[reg]); +} + +static inline void wdt_writel(struct bcm_priv *priv, u32 val, + enum bcm63xx_wdt_reg reg) +{ + writel(val, priv->regs + priv->regs_offsets[reg]); +} + +/* + * IRQ handler, called when half the hw countdown is reached + */ +static irqreturn_t bcm63xx_wdt_irq(int irq, void *dev_id) +{ + struct fbxwatchdog *wdt = dev_id; + struct bcm_priv *priv; + + priv = wdt->priv; + spin_lock(&wdt->lock); + + if (!wdt->enabled) { + printk(KERN_CRIT "watchdog is still enabled, stopping !\n"); + wdt_writel(priv, WDT_STOP_1, WDT_CTL_REG); + wdt_writel(priv, WDT_STOP_2, WDT_CTL_REG); + goto out; + } + + /* clear interrupt and reload */ + wdt_writel(priv, WDT_START_1, WDT_CTL_REG); + wdt_writel(priv, WDT_START_2, WDT_CTL_REG); + + if (wdt->cb) + wdt->cb(wdt); + +out: + spin_unlock(&wdt->lock); + return IRQ_HANDLED; +} + +static int bcm63xx_wdt_init(struct fbxwatchdog *wdt) +{ + struct bcm_priv *priv = wdt->priv; + int ret; + u32 countdown; + + ret = request_irq(priv->irq, bcm63xx_wdt_irq, 0, + "fbxwatchdog_bcm63xx", wdt); + if (ret) { + printk(KERN_ERR PFX "request_irq failed: %d\n", ret); + return ret; + } + + /* irq is triggerd at half time, install a 1 sec watchdog, + * that gives 2 irq/s (freq is 50Mhz) */ + countdown = (50 * 1000 * 1000); + wdt_writel(wdt->priv, countdown, WDT_DEFVAL_REG); + + return 0; +} + +static int bcm63xx_wdt_cleanup(struct fbxwatchdog *wdt) +{ + struct bcm_priv *priv = wdt->priv; + + free_irq(priv->irq, wdt); + return 0; +} + +static int bcm63xx_wdt_start(struct fbxwatchdog *wdt) +{ + printk(KERN_INFO PFX "watchdog enabled\n"); + wdt_writel(wdt->priv, WDT_START_1, WDT_CTL_REG); + wdt_writel(wdt->priv, WDT_START_2, WDT_CTL_REG); + return 0; +} + +static int bcm63xx_wdt_stop(struct fbxwatchdog *wdt) +{ + wdt_writel(wdt->priv, WDT_STOP_1, WDT_CTL_REG); + wdt_writel(wdt->priv, WDT_STOP_2, WDT_CTL_REG); + printk(KERN_INFO PFX "watchdog disabled\n"); + return 0; +} + +struct reset_reason { + int bit; + char *reason; +}; + +struct reset_reason bcm63158_reasons[] = { + { .bit = 31, .reason = "por-reset", }, + { .bit = 30, .reason = "hw-reset", }, + { .bit = 29, .reason = "sw-reset", }, + { .bit = 28, .reason = "pcie-reset", }, +}; + +/* + * all potentially self clearing data in the registers is stored in + * the priv structure for further reuse in + * bcm63xx_wdt_show_reset_reason. + */ +static void bcm63xx_wdt_report_reset_status(struct fbxwatchdog *wdt) +{ + struct bcm_priv *priv = wdt->priv; + + if (priv->chip_id != WDT_63158) + return ; + + if (priv->reg_top_reset_status) { + size_t i; + u32 reg = readl(priv->reg_top_reset_status); + + dev_info(&priv->pdev->dev, "%08x (TOP reset status)\n", reg); + + for (i = 0; i < ARRAY_SIZE(bcm63158_reasons); ++i) { + struct reset_reason *r = &bcm63158_reasons[i]; + + dev_info(&priv->pdev->dev, " %s: %u\n", + r->reason, !!(reg & (1 << r->bit))); + } + priv->top_reset_status = reg; + } + + /* + * NOTE: WD0 & WD1 fields in the PERF_TIMER64_RESET_REASON + * register will self clear on first register read. + */ + priv->timer64_reset_reason = readl(priv->regs + + PERF_TIMER64_RESET_REASON); + + dev_info(&priv->pdev->dev, "%08x (PERF timer64 reset reason)", + priv->timer64_reset_reason); + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD0) + dev_info(&priv->pdev->dev, " wd0 (nominal reboot)\n"); + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD1) + dev_info(&priv->pdev->dev, " wd1 (abnormal reboot)\n"); + + if ((priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_USR_MASK) == + PERF_TIMER64_RESET_REASON_USR_PANPAN) + dev_info(&priv->pdev->dev, " a panic was in progress.\n"); + + /* + * explicitely clear user defined bits in reset reason register. + */ + writel(0x0, priv->regs + PERF_TIMER64_RESET_REASON); +} + +extern int panic_timeout; + +/* + * watchdog panic notifier. in the unlikely case of a panic, the + * watchdog refreshing via the interrupt will be out of order. + * + * This will result in the board resetting before panic_timeout can + * elapse. + * + * In that case rearm the watchdog so that it fires at panic_timeout + + * 1 second. + */ +static int bcm63xx_wdt_on_panic(struct notifier_block *nb, + unsigned long code, void *unused) +{ + struct bcm_priv *priv = nb_to_bcm_priv(nb); + static int in_panic; + u32 new_wdt_countdown = (panic_timeout + 1) * (50 * 1000 * 1000); + + /* + * avoid recursive calls. + */ + if (in_panic) + return NOTIFY_DONE; + in_panic = 1; + + + dev_info(&priv->pdev->dev, "rearming watchdog to expire in %u " + "seconds.\n", panic_timeout + 1); + + wdt_writel(priv, new_wdt_countdown, WDT_DEFVAL_REG); + + wdt_writel(priv, WDT_START_1, WDT_CTL_REG); + wdt_writel(priv, WDT_START_2, WDT_CTL_REG); + + if (priv->chip_id == WDT_63158) + /* + * write PANPAN as user defined reason to the reset + * reason register. In the unlikely event a crashzone + * log cannot be read back, it will preserve the knowledge + * that the board crashed due to a panic. + */ + writel(PERF_TIMER64_RESET_REASON_USR_PANPAN, + priv->regs + PERF_TIMER64_RESET_REASON); + + return NOTIFY_DONE; +} + +ssize_t bcm63xx_wdt_show_reset_reason(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + size_t i; + struct fbxwatchdog *wdt = dev_get_drvdata(dev); + struct bcm_priv *priv = wdt->priv; + size_t retsize; + + if (priv->chip_id != WDT_63158) + return -ENOTSUPP; + + /* + * no register access here, bcm63xx_wdt_report_reset_status() + * will store them in priv, as most of them are self clear on + * first read. + */ + *buf = '\0'; + + /* + * first iterate on the top reset status reset reasons. + */ + for (i = 0; i < ARRAY_SIZE(bcm63158_reasons); ++i) { + const struct reset_reason *r = &bcm63158_reasons[i]; + + if (priv->top_reset_status & (1 << r->bit)) { + strcat(buf, r->reason); + strcat(buf, ","); + } + } + + /* + * watchdog status in PERF_TIMER64_RESET_REASON register. in + * our context, wd0 is used to reboot the box normally. wd1 + * (managed by this driver) will reboot the board if something + * goes wrong and the hardware watchdog isn't refreshed. + * + * in a nutshell: + * wd0 -> normal boot, used by ATF via the PSCI reset call + * wd1 -> boot due to a hardware watchdog trigger. + */ + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD0) + strcat(buf, "wd0,"); + if (priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_WD1) + strcat(buf, "wd1,watchdog,"); + + /* + * user defined reboot bits in PERF_TIMER64_RESET_REASON_REG. + */ + if ((priv->timer64_reset_reason & PERF_TIMER64_RESET_REASON_USR_MASK) == + PERF_TIMER64_RESET_REASON_USR_PANPAN) + strcat(buf, "panic,"); + + /* + * '\n'-terminate the string. + */ + retsize = strlen(buf); + if (retsize) + buf[retsize - 1] = '\n'; + + return strlen(buf); +} + +static DEVICE_ATTR(reset_reason, 0444, bcm63xx_wdt_show_reset_reason, NULL); + +static struct attribute *bcm63xx_wdt_attrs[] = { + &dev_attr_reset_reason.attr, + NULL +}; + +static const struct attribute_group bcm63xx_wdt_attrs_group = { + .attrs = bcm63xx_wdt_attrs, +}; + +/* + * + */ +static int fbxwatchdog_bcm63xx_probe(struct platform_device *pdev) +{ + struct fbxwatchdog *wdt; + struct bcm_priv *priv; + struct resource *res; + int ret, irq_number; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pdev = pdev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to get register core resource\n"); + return -ENODEV; + } + + priv->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->regs)) { + dev_err(&pdev->dev, "unable to ioremap regs\n"); + return PTR_ERR(priv->regs); + } + + /* + * ioremap optional reset cause register. + */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (res) { + priv->reg_top_reset_status = devm_ioremap_resource(&pdev->dev, + res); + if (IS_ERR(priv->reg_top_reset_status)) { + dev_err(&pdev->dev, "unable to ioremap TOP reset " + "status register.\n"); + return PTR_ERR(priv->reg_top_reset_status); + } + dev_info(&pdev->dev, "TOP reset status regiser: %pR", res); + } + + priv->chip_id = (unsigned long)of_device_get_match_data(&pdev->dev); + switch (priv->chip_id) { + case WDT_6328: + irq_number = 4; + priv->regs_offsets = regs_offsets_6328; + break; + case WDT_63158: + irq_number = 0; + priv->regs_offsets = regs_offsets_63158; + break; + default: + return -ENODEV; + } + + priv->irq = platform_get_irq(pdev, irq_number); + if (priv->irq < 0) { + dev_err(&pdev->dev, "cannot get watchdog irq\n"); + return priv->irq; + } + + wdt = devm_kzalloc(&pdev->dev, sizeof (*wdt), GFP_KERNEL); + if (!wdt) { + printk(KERN_WARNING PFX "unable to allocate memory for " + "watchdog.\n"); + return -ENOMEM; + } + + wdt->name = pdev->name; + wdt->priv = priv; + wdt->wdt_init = bcm63xx_wdt_init; + wdt->wdt_cleanup = bcm63xx_wdt_cleanup; + wdt->wdt_start = bcm63xx_wdt_start; + wdt->wdt_stop = bcm63xx_wdt_stop; + + ret = fbxwatchdog_register(wdt); + if (ret) { + printk(KERN_WARNING PFX "unable to register watchdog %s.\n", + wdt->name); + return ret; + } + bcm63xx_wdt_report_reset_status(wdt); + + priv->panic_notifier.notifier_call = bcm63xx_wdt_on_panic, + atomic_notifier_chain_register(&panic_notifier_list, + &priv->panic_notifier); + + ret = sysfs_create_group(&wdt->dev->kobj, &bcm63xx_wdt_attrs_group); + if (ret) { + dev_info(&pdev->dev, "sysfs_create_group failed: %pe\n", + ERR_PTR(ret)); + goto err_unregister_notifier; + } + + platform_set_drvdata(pdev, wdt); + return 0; + +err_unregister_notifier: + atomic_notifier_chain_unregister(&panic_notifier_list, + &priv->panic_notifier); + fbxwatchdog_unregister(wdt); + return ret; +} + +/* + * + */ +static int fbxwatchdog_bcm63xx_remove(struct platform_device *pdev) +{ + struct fbxwatchdog *wdt; + struct bcm_priv *priv; + + wdt = platform_get_drvdata(pdev); + if (!wdt) + return -ENODEV; + priv = wdt->priv; + + sysfs_remove_group(&wdt->dev->kobj, &bcm63xx_wdt_attrs_group); + atomic_notifier_chain_unregister(&panic_notifier_list, + &priv->panic_notifier); + fbxwatchdog_unregister(wdt); + + return 0; +} + +static const struct of_device_id bcmtimer_of_table[] = { + { .compatible = "brcm,bcm6328-timer", .data = (void *)WDT_6328}, + { .compatible = "brcm,bcm63158-timer", .data = (void *)WDT_63158 }, + { } +}; +MODULE_DEVICE_TABLE(of, bcmtimer_of_table); + +struct platform_driver fbxwatchdog_bcm63xx_driver = { + .probe = fbxwatchdog_bcm63xx_probe, + .remove = fbxwatchdog_bcm63xx_remove, + .driver = { + .name = "bcm63xx_wdt", + .of_match_table = of_match_ptr(bcmtimer_of_table), + }, +}; + +static int __init fbxwatchdog_bcm63xx_of_init(void) +{ + platform_driver_register(&fbxwatchdog_bcm63xx_driver); + return 0; +} + +static void __exit fbxwatchdog_bcm63xx_of_exit(void) +{ + platform_driver_unregister(&fbxwatchdog_bcm63xx_driver); +} + +module_init(fbxwatchdog_bcm63xx_of_init); +module_exit(fbxwatchdog_bcm63xx_of_exit); + +MODULE_AUTHOR("Maxime Bizon"); +MODULE_LICENSE("GPL"); diff -Nruw linux-5.4.60-fbx/drivers/fbxwatchdog./fbxwatchdog_core.c linux-5.4.60-fbx/drivers/fbxwatchdog/fbxwatchdog_core.c --- linux-5.4.60-fbx/drivers/fbxwatchdog./fbxwatchdog_core.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxwatchdog/fbxwatchdog_core.c 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,297 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fbxwatchdog.h" + +#define SOFTTIMER_FREQ (HZ / 10) + +#define PFX "fbxwatchdog: " + +static struct class *fbxwatchdog_class; + +static ssize_t +show_enabled(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxwatchdog *wdt; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + return snprintf(buf, PAGE_SIZE, "%i\n", wdt->enabled); +} + +/* + * start/stop watchdog depending on the value of the first character + * of buf. set countdown_min to a sane value. + */ +static ssize_t +store_enabled(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct fbxwatchdog *wdt; + unsigned long flags; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + if (size == 0) + return 0; + + + spin_lock_irqsave(&wdt->lock, flags); + switch (*buf) { + case '0': + if (wdt->enabled) { + wdt->enabled = 0; + wdt->wdt_stop(wdt); + } + break; + + case '1': + if (!wdt->enabled) { + wdt->enabled = 1; + wdt->wdt_start(wdt); + wdt->countdown_min = INT_MAX; + } + break; + + default: + break; + } + spin_unlock_irqrestore(&wdt->lock, flags); + + return size; +} + +static ssize_t +show_countdown(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxwatchdog *wdt; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + return snprintf(buf, PAGE_SIZE, "%i\n", wdt->countdown); +} + +/* + * update watchdog countdown with the userland value given in buf. + */ +static ssize_t +store_countdown(struct device *dev, + struct device_attribute *attr, const char *buf, size_t size) +{ + struct fbxwatchdog *wdt; + int countdown; + char *ptr; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + if (size == 0) + return 0; + + ptr = kzalloc(size + 1, GFP_KERNEL); + if (!ptr) + return -ENOMEM; + strlcpy(ptr, buf, size + 1); + + countdown = simple_strtoul(ptr, NULL, 10); + wdt->countdown = countdown; + kfree(ptr); + + return size; +} + +static ssize_t +show_countdown_min(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct fbxwatchdog *wdt; + + wdt = dev_get_drvdata(dev); + if (!wdt) { + printk(KERN_DEBUG "ignoring request to dead watchdog.\n"); + return -ENODEV; + } + + return snprintf(buf, PAGE_SIZE, "%i\n", wdt->countdown_min); +} + +static struct device_attribute wdt_attributes[] = { + __ATTR(enabled, 0600, show_enabled, store_enabled), + __ATTR(countdown, 0600, show_countdown, store_countdown), + __ATTR(countdown_min, 0400, show_countdown_min, NULL), +}; + +/* + * software timer callback: decrement countdown and update + * countdown_min if needed. this is called 10 times per second. + */ +static void fbxwatchdog_timer_cb(struct timer_list *t) +{ + struct fbxwatchdog *wdt = from_timer(wdt, t, timer); + + if (wdt->enabled) { + wdt->countdown -= jiffies_to_msecs(SOFTTIMER_FREQ); + if (wdt->countdown < wdt->countdown_min) + wdt->countdown_min = wdt->countdown; + } + + wdt->timer.expires = jiffies + SOFTTIMER_FREQ; + add_timer(&wdt->timer); +} + +/* + * called from half life interrupt handler, panic if countdown is too + * low (ie if userland has not reset countdown to before it reached + * 0). + */ +static void fbxwatchdog_halflife_cb(struct fbxwatchdog *wdt) +{ + if (wdt->countdown <= 0) { + wdt->wdt_stop(wdt); + panic("software fbxwatchdog triggered"); + } +} + +/* + * register a new watchdog device. + */ +int fbxwatchdog_register(struct fbxwatchdog *wdt) +{ + struct device *dev; + int i = 0, err = 0; + + if (wdt == NULL) + return -EFAULT; + + printk(KERN_INFO PFX "registering watchdog %s\n", wdt->name); + + dev = device_create(fbxwatchdog_class, NULL, 0, wdt, "%s", wdt->name); + if (IS_ERR(dev)) { + printk(KERN_ERR PFX "unable to allocate device.\n"); + err = PTR_ERR(dev); + goto out_error; + } + wdt->dev = dev; + + for (i = 0; i < ARRAY_SIZE(wdt_attributes); i++) { + err = device_create_file(dev, &wdt_attributes[i]); + if (err) + goto out_error; + } + + /* start countdown soft timer */ + timer_setup(&wdt->timer, fbxwatchdog_timer_cb, 0); + wdt->timer.expires = jiffies + SOFTTIMER_FREQ; + add_timer(&wdt->timer); + + spin_lock_init(&wdt->lock); + + wdt->cb = fbxwatchdog_halflife_cb; + err = wdt->wdt_init(wdt); + if (err) { + printk(KERN_ERR PFX "unable to do low level init of " + "watchdog %s.\n", wdt->name); + goto out_del_timer; + } + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR + err = fbxwatchdog_char_add(wdt); + if (err) { + printk(KERN_ERR PFX "unable to add %s to the fbxwatchdog char " + "device interface.\n", wdt->name); + goto out_wdt_cleanup; + } +#endif + + return 0; + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR +out_wdt_cleanup: + wdt->wdt_cleanup(wdt); +#endif + +out_del_timer: + del_timer_sync(&wdt->timer); +out_error: + if (wdt->dev) { + for (; i >= 0; i--) + device_remove_file(dev, &wdt_attributes[i]); + device_unregister(dev); + } + return err; +} + +int fbxwatchdog_unregister(struct fbxwatchdog *wdt) +{ + int i; + + printk(KERN_INFO PFX "registering watchdog %s\n", wdt->name); + + if (wdt->enabled) { + unsigned long flags; + + printk(KERN_WARNING "removing enabled watchdog.\n"); + spin_lock_irqsave(&wdt->lock, flags); + wdt->wdt_stop(wdt); + spin_unlock_irqrestore(&wdt->lock, flags); + } + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR + fbxwatchdog_char_remove(wdt); +#endif + wdt->wdt_cleanup(wdt); + del_timer_sync(&wdt->timer); + for (i = 0; i < ARRAY_SIZE(wdt_attributes); i++) + device_remove_file(wdt->dev, &wdt_attributes[i]); + device_unregister(wdt->dev); + wdt->dev = NULL; + return 0; +} + +static int __init fbxwatchdog_init(void) +{ + printk(KERN_INFO PFX "2007, Freebox SA.\n"); + fbxwatchdog_class = class_create(THIS_MODULE, "fbxwatchdog"); + if (IS_ERR(fbxwatchdog_class)) + return PTR_ERR(fbxwatchdog_class); + return 0; +} + +static void __exit fbxwatchdog_exit(void) +{ + class_destroy(fbxwatchdog_class); +} + + +EXPORT_SYMBOL_GPL(fbxwatchdog_register); +EXPORT_SYMBOL_GPL(fbxwatchdog_unregister); + +module_init(fbxwatchdog_init); +module_exit(fbxwatchdog_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Freebox Watchdog Core - www.freebox.fr"); diff -Nruw linux-5.4.60-fbx/drivers/fbxwatchdog./fbxwatchdog.h linux-5.4.60-fbx/drivers/fbxwatchdog/fbxwatchdog.h --- linux-5.4.60-fbx/drivers/fbxwatchdog./fbxwatchdog.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxwatchdog/fbxwatchdog.h 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,47 @@ +#ifndef FBXWATCHDOG_H +# define FBXWATCHDOG_H + +struct fbxwatchdog { + const char *name; + void *priv; + + int enabled; + int countdown; + int countdown_min; + + int (*wdt_init)(struct fbxwatchdog *wdt); + int (*wdt_cleanup)(struct fbxwatchdog *wdt); + + /* + * wdt_start and wdt_stop are called with wdt->lock held and irq + * disabled. + */ + int (*wdt_start)(struct fbxwatchdog *wdt); + int (*wdt_stop)(struct fbxwatchdog *wdt); + + /* + * cb is called from interrupt/softirq context (depends on the + * underlying driver/hardware). + */ + void (*cb)(struct fbxwatchdog *wdt); + + struct timer_list timer; + + struct device *dev; + + /* + * protect interrupt handlers & start/stop methods running in + * thead context. + */ + spinlock_t lock; +}; + +int fbxwatchdog_register(struct fbxwatchdog *wdt); +int fbxwatchdog_unregister(struct fbxwatchdog *wdt); + +#ifdef CONFIG_FREEBOX_WATCHDOG_CHAR +int fbxwatchdog_char_add(struct fbxwatchdog *wdt); +void fbxwatchdog_char_remove(struct fbxwatchdog *wdt); +#endif + +#endif /* !FBXWATCHDOG_H */ diff -Nruw linux-5.4.60-fbx/drivers/fbxwatchdog./Kconfig linux-5.4.60-fbx/drivers/fbxwatchdog/Kconfig --- linux-5.4.60-fbx/drivers/fbxwatchdog./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxwatchdog/Kconfig 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,24 @@ +menuconfig FREEBOX_WATCHDOG + tristate "Freebox Watchdog" + default n + +if FREEBOX_WATCHDOG + +config FREEBOX_WATCHDOG_CHAR + bool "Freebox Watchdog char device interface." + default n + +config FREEBOX_WATCHDOG_ORION + tristate "Marvell Orion support" + depends on PLAT_ORION + +config FREEBOX_WATCHDOG_BCM63XX + tristate "Broadcom 63xx Freebox Watchdog support" + depends on BCM63XX + default n + +config FREEBOX_WATCHDOG_BCM63XX_OF + tristate "Broadcom 63xx Freebox Watchdog support (generic)" + depends on OF && !FREEBOX_WATCHDOG_BCM63XX + +endif diff -Nruw linux-5.4.60-fbx/drivers/fbxwatchdog./Makefile linux-5.4.60-fbx/drivers/fbxwatchdog/Makefile --- linux-5.4.60-fbx/drivers/fbxwatchdog./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/fbxwatchdog/Makefile 2021-03-04 13:20:57.760838887 +0100 @@ -0,0 +1,10 @@ +obj-$(CONFIG_FREEBOX_WATCHDOG) += fbxwatchdog.o + +fbxwatchdog-objs = fbxwatchdog_core.o +ifeq ($(CONFIG_FREEBOX_WATCHDOG_CHAR),y) +fbxwatchdog-objs += fbxwatchdog_char.o +endif + +obj-$(CONFIG_FREEBOX_WATCHDOG_ORION) += fbxwatchdog_orion.o +obj-$(CONFIG_FREEBOX_WATCHDOG_BCM63XX) += fbxwatchdog_bcm63xx.o +obj-$(CONFIG_FREEBOX_WATCHDOG_BCM63XX_OF) += fbxwatchdog_bcm63xx_of.o --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/hwmon/ld6710-fbx.c 2021-03-04 13:20:58.457505585 +0100 @@ -0,0 +1,343 @@ +/* + * ld6710-fbx.c for ld6710-fbx + * Created by on Wed Sep 25 15:01:56 2019 + */ + +/* + * Driver for LD6710 power deliverance with freebox specific + * firmware. The power supply temperature report on the I2C register + * space is a feature of the ROMed firmware on the chip, which depends + * on the OEM. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LD6710_CHIPVER 0x00 +#define LD6710_FWVER 0x01 + +#define LD6710_SINK_CURRENT 0x10 +#define LD6710_SINK_CURRENT_MAX 0x11 + +#define LD6710_SINK_TEMP 0x20 +#define LD6710_SINK_TEMP_TURNOFF 0x21 +#define LD6710_SINK_TEMP_TURNON 0x22 + +#define LD6710_SINK_STATUS 0x30 +#define SINK_STATUS_OTP (1 << 0) +#define SINK_STATUS_OCP (1 << 1) +#define SINK_STATUS_OVP (1 << 2) + +struct ld6710_priv { + struct device *hwmon_dev; + struct i2c_client *client; + struct mutex mutex; +}; + +static int ld6710_read(struct ld6710_priv *priv, u8 addr) +{ + int ret; + + ret = i2c_smbus_read_byte_data(priv->client, addr); + if (ret < 0) { + dev_err(&priv->client->dev, "i2c read error at address %02x\n", + addr); + return 0xff; + } + return ret; +} + +static void ld6710_write(struct ld6710_priv *priv, u8 addr, u8 value) +{ + i2c_smbus_write_byte_data(priv->client, addr, value); +} + +static struct ld6710_priv *to_ld6710_priv(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + return i2c_get_clientdata(client); +} + +/* + * chip / fw + */ +static ssize_t version_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + u32 v; + + mutex_lock(&priv->mutex); + v = ld6710_read(priv, sattr->nr); + mutex_unlock(&priv->mutex); + + return sprintf(buf, "0x%02x\n", v); +} + +static SENSOR_DEVICE_ATTR_2_RO(chipver, version, LD6710_CHIPVER, 0); +static SENSOR_DEVICE_ATTR_2_RO(fwver, version, LD6710_FWVER, 0); + +static struct attribute *ld6710_ver_attrs[] = { + &sensor_dev_attr_chipver.dev_attr.attr, + &sensor_dev_attr_fwver.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_ver_group = { + .attrs = ld6710_ver_attrs, +}; + +/* + * sink current (mA) + */ +static ssize_t current_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + u32 v; + + mutex_lock(&priv->mutex); + v = ld6710_read(priv, sattr->nr) * 100; + mutex_unlock(&priv->mutex); + + return sprintf(buf, "%d\n", v); +} + +static ssize_t current_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + val /= 100; + if (val > 255) + return -EINVAL; + + mutex_lock(&priv->mutex); + ld6710_write(priv, sattr->nr, val); + mutex_unlock(&priv->mutex); + + return count; +} + +static SENSOR_DEVICE_ATTR_2_RO(sink_current, current, LD6710_SINK_CURRENT, 0); +static SENSOR_DEVICE_ATTR_2_RO(in1_input, current, LD6710_SINK_CURRENT, 0); +static SENSOR_DEVICE_ATTR_2_RW(sink_current_max, current, + LD6710_SINK_CURRENT_MAX, 0); + +static struct attribute *ld6710_sink_current_attrs[] = { + &sensor_dev_attr_in1_input.dev_attr.attr, + &sensor_dev_attr_sink_current.dev_attr.attr, + &sensor_dev_attr_sink_current_max.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_sink_current_group = { + .attrs = ld6710_sink_current_attrs, +}; + +/* + * sink temperature (1/1000th degree) + */ +static ssize_t temperature_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + u32 v; + + mutex_lock(&priv->mutex); + v = ld6710_read(priv, sattr->nr) * 1000; + mutex_unlock(&priv->mutex); + + return sprintf(buf, "%d\n", v); +} + +static ssize_t temperature_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct ld6710_priv *priv = to_ld6710_priv(dev); + struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr); + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + val /= 1000; + if (val > 255) + return -EINVAL; + + mutex_lock(&priv->mutex); + ld6710_write(priv, sattr->nr, val); + mutex_unlock(&priv->mutex); + + return count; +} + +static SENSOR_DEVICE_ATTR_2_RO(temp1_input, temperature, LD6710_SINK_TEMP, 0); +static SENSOR_DEVICE_ATTR_2_RW(temp1_turnoff, temperature, + LD6710_SINK_TEMP_TURNOFF, 0); +static SENSOR_DEVICE_ATTR_2_RW(temp1_turnon, temperature, + LD6710_SINK_TEMP_TURNON, 0); + + +static struct attribute *ld6710_sink_temp_attrs[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_turnoff.dev_attr.attr, + &sensor_dev_attr_temp1_turnon.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_sink_temp_group = { + .attrs = ld6710_sink_temp_attrs, +}; + +/* + * status + */ +static ssize_t status_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return version_show(dev, attr, buf); +} + +static SENSOR_DEVICE_ATTR_2_RO(status, status, LD6710_SINK_STATUS, 0); + +static struct attribute *ld6710_status_attrs[] = { + &sensor_dev_attr_status.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ld6710_status_group = { + .attrs = ld6710_status_attrs, +}; + + +static void ld6710_fbx_remove_files(struct i2c_client *client) +{ + sysfs_remove_group(&client->dev.kobj, &ld6710_ver_group); + sysfs_remove_group(&client->dev.kobj, &ld6710_sink_current_group); + sysfs_remove_group(&client->dev.kobj, &ld6710_sink_temp_group); + sysfs_remove_group(&client->dev.kobj, &ld6710_status_group); +} + +static int ld6710_fbx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ld6710_priv *priv; + u8 chipver, fwver; + int error; + + dev_info(&client->dev, "probe\n"); + + priv = devm_kzalloc(&client->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->client = client; + mutex_init(&priv->mutex); + i2c_set_clientdata(client, priv); + + /* + * read chipver and fwver and check that they look sane. + */ + chipver = ld6710_read(priv, LD6710_CHIPVER); + fwver = ld6710_read(priv, LD6710_FWVER); + if (chipver == 0xff || fwver == 0xff) { + dev_err(&client->dev, "invalid chip version of firmware " + "version.\n"); + return -ENXIO; + } + + dev_info(&client->dev, "LD6710 chip %02x, fw %02x\n", + chipver, fwver); + + /* + * create attributes + */ + error = sysfs_create_group(&client->dev.kobj, &ld6710_ver_group); + if (error) + goto remove_files; + + error = sysfs_create_group(&client->dev.kobj, + &ld6710_sink_current_group); + if (error) + goto remove_files; + + error = sysfs_create_group(&client->dev.kobj, &ld6710_sink_temp_group); + if (error) + goto remove_files; + + error = sysfs_create_group(&client->dev.kobj, &ld6710_status_group); + if (error) + goto remove_files; + + /* + * register hwmon device. + */ + priv->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(priv->hwmon_dev)) { + dev_err(&client->dev, "unable to register hwmon device.\n"); + error = PTR_ERR(priv->hwmon_dev); + goto remove_files; + } + + return 0; + +remove_files: + ld6710_fbx_remove_files(client); + return error; +} + +static int ld6710_fbx_remove(struct i2c_client *client) +{ + struct ld6710_priv *priv = i2c_get_clientdata(client); + + dev_info(&client->dev, "remove\n"); + + hwmon_device_unregister(priv->hwmon_dev); + ld6710_fbx_remove_files(priv->client); + + return 0; +} + +static const struct of_device_id ld6710_fbx_of_match[] = { + { .compatible = "leadtrend,ld6710-fbx" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ld6710_fbx_of_match); + + +static const unsigned short ld6710_addrs[] = { 0x68, /* maybe some others ? */ + I2C_CLIENT_END }; + +static struct i2c_driver ld6710_fbx_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "ld6710_fbx", + .of_match_table = of_match_ptr(ld6710_fbx_of_match), + }, + .probe = ld6710_fbx_probe, + .remove = ld6710_fbx_remove, + .address_list = ld6710_addrs, +}; + +module_i2c_driver(ld6710_fbx_driver); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Nicolas Schichan "); --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/misc/fbxserial_of.c 2021-03-04 13:20:58.907505606 +0100 @@ -0,0 +1,38 @@ +#include +#include +#include +#include + +static struct fbx_serial serial_info; + +const struct fbx_serial *arch_get_fbxserial(void) +{ + return &serial_info; +} + +EXPORT_SYMBOL(arch_get_fbxserial); + +/* + * + */ +static __init int fbxserial_of_read(void) +{ + struct device_node *np; + const void *fbxserial_data; + int len; + + np = of_find_node_by_path("/chosen"); + if (!np) + return 0; + + fbxserial_data = of_get_property(np, "fbx,serialinfo", &len); + if (!fbxserial_data) + return 0; + + fbxserialinfo_read(fbxserial_data, &serial_info); + add_device_randomness(&serial_info, sizeof (serial_info)); + + return 0; +} + +arch_initcall(fbxserial_of_read); diff -Nruw linux-5.4.60-fbx/drivers/misc/hdmi-cec./Kconfig linux-5.4.60-fbx/drivers/misc/hdmi-cec/Kconfig --- linux-5.4.60-fbx/drivers/misc/hdmi-cec./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/misc/hdmi-cec/Kconfig 2021-03-04 13:20:58.914172272 +0100 @@ -0,0 +1,15 @@ +menu "HDMI CEC support" + +config HDMI_CEC + tristate "HDMI CEC (Consumer Electronics Control) support" + ---help--- + HDMI Consumer Electronics Control support. + +config HDMI_CEC_REMOTI + tristate "RemoTI CEC driver" + depends on HDMI_CEC + select REMOTI + ---help--- + HDMI CEC driver using RemoTI IPCs. + +endmenu diff -Nruw linux-5.4.60-fbx/drivers/misc/hdmi-cec./Makefile linux-5.4.60-fbx/drivers/misc/hdmi-cec/Makefile --- linux-5.4.60-fbx/drivers/misc/hdmi-cec./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/misc/hdmi-cec/Makefile 2021-03-04 13:20:58.914172272 +0100 @@ -0,0 +1,6 @@ +obj-$(CONFIG_HDMI_CEC) += hdmi-cec.o +hdmi-cec-objs += core.o dev.o + +# drivers +obj-$(CONFIG_HDMI_CEC_REMOTI) += remoti-cec.o +remoti-cec-objs := remoti.o --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/misc/random_of.c 2021-03-04 13:20:58.924172273 +0100 @@ -0,0 +1,43 @@ +/* + * random_of.c for of_random + * Created by on Tue Jul 2 19:13:55 2019 + */ + +#include +#include +#include +#include +#include + +u64 random_seed_start; +u64 random_seed_size; + +/* + * add data from the area reserved early in fdt.c to the linux PRNG + * pool, via add_device_randomness(). + */ +static __init int random_of_seed(void) +{ + void __iomem *p; + + if (!random_seed_size || !random_seed_start) + /* + * most likely the fbx,random-seed property is not + * present in the device tree. + */ + return 0; + + pr_info("random: %llx-%llx\n", random_seed_start, + random_seed_start + random_seed_size); + + p = ioremap_cache(random_seed_start, random_seed_size); + if (!p) { + pr_err("unable to ioremap_cache() random seed."); + return -ENOMEM; + } + add_device_randomness(p, random_seed_size); + memset(p, 0, random_seed_size); + return 0; +} + +arch_initcall(random_of_seed); diff -Nruw linux-5.4.60-fbx/drivers/misc/remoti./Kconfig linux-5.4.60-fbx/drivers/misc/remoti/Kconfig --- linux-5.4.60-fbx/drivers/misc/remoti./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/misc/remoti/Kconfig 2021-03-04 13:20:58.924172273 +0100 @@ -0,0 +1,26 @@ +menu "RemoTI support" + +config REMOTI + tristate "RemoTI support" + depends on FBX6HD + ---help--- + Texas Instruments RemoTI stack. + +config REMOTI_LEDS + tristate "RemoTI LEDS support" + depends on REMOTI + depends on LEDS_CLASS + ---help--- + RemoTI LEDS class driver support. + +config REMOTI_GPIO + tristate "RemoTI gpio support" + depends on REMOTI + ---help--- + gpiochip driver for the RemoTI RNP + +config REMOTI_USER + tristate "RemoTI userspace access" + depends on REMOTI + +endmenu diff -Nruw linux-5.4.60-fbx/drivers/misc/remoti./Makefile linux-5.4.60-fbx/drivers/misc/remoti/Makefile --- linux-5.4.60-fbx/drivers/misc/remoti./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/misc/remoti/Makefile 2021-03-04 13:20:58.924172273 +0100 @@ -0,0 +1,9 @@ +obj-$(CONFIG_REMOTI) += remoti.o +obj-$(CONFIG_REMOTI_GPIO) += remoti-gpio.o +obj-$(CONFIG_REMOTI_LEDS) += remoti-leds.o +obj-$(CONFIG_REMOTI_USER) += remoti-user.o + +remoti-objs := core.o core-sysfs.o +remoti-gpio-objs := gpio.o +remoti-leds-objs := leds.o +remoti-user-objs := user.o diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./bcmsysport_63158.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/bcmsysport_63158.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./bcmsysport_63158.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/bcmsysport_63158.c 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,2378 @@ +/* + * Broadcom BCM7xxx System Port Ethernet MAC driver + * + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bcmsysport_63158.h" + +/* I/O accessors register helpers */ +#define BCM_SYSPORT_IO_MACRO(name, offset) \ +static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off) \ +{ \ + u32 reg = readl_relaxed(priv->base + offset + off); \ + return reg; \ +} \ +static inline void name##_writel(struct bcm_sysport_priv *priv, \ + u32 val, u32 off) \ +{ \ + writel_relaxed(val, priv->base + offset + off); \ +} \ + +BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET); +BCM_SYSPORT_IO_MACRO(intrl2_1, SYS_PORT_INTRL2_1_OFFSET); +BCM_SYSPORT_IO_MACRO(umac, SYS_PORT_UMAC_OFFSET); +BCM_SYSPORT_IO_MACRO(gib, SYS_PORT_GIB_OFFSET); +BCM_SYSPORT_IO_MACRO(tdma, SYS_PORT_TDMA_OFFSET); +BCM_SYSPORT_IO_MACRO(rxchk, SYS_PORT_RXCHK_OFFSET); +BCM_SYSPORT_IO_MACRO(txchk, SYS_PORT_TXCHK_OFFSET); +BCM_SYSPORT_IO_MACRO(rbuf, SYS_PORT_RBUF_OFFSET); +BCM_SYSPORT_IO_MACRO(tbuf, SYS_PORT_TBUF_OFFSET); +BCM_SYSPORT_IO_MACRO(topctrl, SYS_PORT_TOPCTRL_OFFSET); + +/* On SYSTEMPORT Lite, any register after RDMA_STATUS has the exact + * same layout, except it has been moved by 4 bytes up, *sigh* + */ +static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off) +{ + if (priv->is_lite && off >= RDMA_STATUS) + off += 4; + return readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off); +} + +static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off) +{ + if (priv->is_lite && off >= RDMA_STATUS) + off += 4; + writel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off); +} + +static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit) +{ + if (!priv->is_lite) { + return BIT(bit); + } else { + if (bit >= ACB_ALGO) + return BIT(bit + 1); + else + return BIT(bit); + } +} + +/* L2-interrupt masking/unmasking helpers, does automatic saving of the applied + * mask in a software copy to avoid CPU_MASK_STATUS reads in hot-paths. + */ +#define BCM_SYSPORT_INTR_L2(which) \ +static inline void intrl2_##which##_mask_clear(struct bcm_sysport_priv *priv, \ + u32 mask) \ +{ \ + priv->irq##which##_mask &= ~(mask); \ + intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR); \ +} \ +static inline void intrl2_##which##_mask_set(struct bcm_sysport_priv *priv, \ + u32 mask) \ +{ \ + intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET); \ + priv->irq##which##_mask |= (mask); \ +} \ + +BCM_SYSPORT_INTR_L2(0) +BCM_SYSPORT_INTR_L2(1) + +/* Register accesses to GISB/RBUS registers are expensive (few hundred + * nanoseconds), so keep the check for 64-bits explicit here to save + * one register write per-packet on 32-bits platforms. + */ +static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv, + void __iomem *d, + dma_addr_t addr) +{ +#ifdef CONFIG_PHYS_ADDR_T_64BIT + writel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK, + d + DESC_ADDR_HI_STATUS_LEN); +#endif + writel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO); +} + +/* Ethtool operations */ +static int bcm_sysport_set_rx_csum(struct net_device *dev, + netdev_features_t wanted) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + u32 reg; + + priv->rx_chk_en = !!(wanted & NETIF_F_RXCSUM); + reg = rxchk_readl(priv, RXCHK_CONTROL); + if (priv->rx_chk_en) + reg |= RXCHK_EN; + else + reg &= ~RXCHK_EN; + + /* If UniMAC forwards CRC, we need to skip over it to get + * a valid CHK bit to be set in the per-packet status word + */ + if (priv->rx_chk_en && priv->crc_fwd) + reg |= RXCHK_SKIP_FCS; + else + reg &= ~RXCHK_SKIP_FCS; + + /* If Broadcom tags are enabled (e.g: using a switch), make + * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom + * tag after the Ethernet MAC Source Address. + */ + if (netdev_uses_dsa(dev)) + reg |= RXCHK_BRCM_TAG_EN; + else + reg &= ~RXCHK_BRCM_TAG_EN; + + rxchk_writel(priv, reg, RXCHK_CONTROL); + + return 0; +} + +static int bcm_sysport_set_tx_csum(struct net_device *dev, + netdev_features_t wanted) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + u32 reg; + + /* Hardware transmit checksum requires us to enable the Transmit status + * block prepended to the packet contents + */ + priv->tsb_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); + reg = tdma_readl(priv, TDMA_CONTROL); + if (priv->tsb_en) + reg |= tdma_control_bit(priv, TSB_EN); + else + reg &= ~tdma_control_bit(priv, TSB_EN); + tdma_writel(priv, reg, TDMA_CONTROL); + + return 0; +} + +static int bcm_sysport_set_features(struct net_device *dev, + netdev_features_t features) +{ + netdev_features_t changed = features ^ dev->features; + netdev_features_t wanted = dev->wanted_features; + int ret = 0; + + if (changed & NETIF_F_RXCSUM) + ret = bcm_sysport_set_rx_csum(dev, wanted); + if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) + ret = bcm_sysport_set_tx_csum(dev, wanted); + + return ret; +} + +/* Hardware counters must be kept in sync because the order/offset + * is important here (order in structure declaration = order in hardware) + */ +static const struct bcm_sysport_stats bcm_sysport_gstrings_stats[] = { + /* general stats */ + STAT_NETDEV64(rx_packets), + STAT_NETDEV64(tx_packets), + STAT_NETDEV64(rx_bytes), + STAT_NETDEV64(tx_bytes), + STAT_NETDEV(rx_errors), + STAT_NETDEV(tx_errors), + STAT_NETDEV(rx_dropped), + STAT_NETDEV(tx_dropped), + STAT_NETDEV(multicast), + /* UniMAC RSV counters */ + STAT_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), + STAT_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), + STAT_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), + STAT_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), + STAT_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), + STAT_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), + STAT_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), + STAT_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), + STAT_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), + STAT_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), + STAT_MIB_RX("rx_pkts", mib.rx.pkt), + STAT_MIB_RX("rx_bytes", mib.rx.bytes), + STAT_MIB_RX("rx_multicast", mib.rx.mca), + STAT_MIB_RX("rx_broadcast", mib.rx.bca), + STAT_MIB_RX("rx_fcs", mib.rx.fcs), + STAT_MIB_RX("rx_control", mib.rx.cf), + STAT_MIB_RX("rx_pause", mib.rx.pf), + STAT_MIB_RX("rx_unknown", mib.rx.uo), + STAT_MIB_RX("rx_align", mib.rx.aln), + STAT_MIB_RX("rx_outrange", mib.rx.flr), + STAT_MIB_RX("rx_code", mib.rx.cde), + STAT_MIB_RX("rx_carrier", mib.rx.fcr), + STAT_MIB_RX("rx_oversize", mib.rx.ovr), + STAT_MIB_RX("rx_jabber", mib.rx.jbr), + STAT_MIB_RX("rx_mtu_err", mib.rx.mtue), + STAT_MIB_RX("rx_good_pkts", mib.rx.pok), + STAT_MIB_RX("rx_unicast", mib.rx.uc), + STAT_MIB_RX("rx_ppp", mib.rx.ppp), + STAT_MIB_RX("rx_crc", mib.rx.rcrc), + /* UniMAC TSV counters */ + STAT_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), + STAT_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), + STAT_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), + STAT_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), + STAT_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), + STAT_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), + STAT_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), + STAT_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), + STAT_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), + STAT_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), + STAT_MIB_TX("tx_pkts", mib.tx.pkts), + STAT_MIB_TX("tx_multicast", mib.tx.mca), + STAT_MIB_TX("tx_broadcast", mib.tx.bca), + STAT_MIB_TX("tx_pause", mib.tx.pf), + STAT_MIB_TX("tx_control", mib.tx.cf), + STAT_MIB_TX("tx_fcs_err", mib.tx.fcs), + STAT_MIB_TX("tx_oversize", mib.tx.ovr), + STAT_MIB_TX("tx_defer", mib.tx.drf), + STAT_MIB_TX("tx_excess_defer", mib.tx.edf), + STAT_MIB_TX("tx_single_col", mib.tx.scl), + STAT_MIB_TX("tx_multi_col", mib.tx.mcl), + STAT_MIB_TX("tx_late_col", mib.tx.lcl), + STAT_MIB_TX("tx_excess_col", mib.tx.ecl), + STAT_MIB_TX("tx_frags", mib.tx.frg), + STAT_MIB_TX("tx_total_col", mib.tx.ncl), + STAT_MIB_TX("tx_jabber", mib.tx.jbr), + STAT_MIB_TX("tx_bytes", mib.tx.bytes), + STAT_MIB_TX("tx_good_pkts", mib.tx.pok), + STAT_MIB_TX("tx_unicast", mib.tx.uc), + /* UniMAC RUNT counters */ + STAT_RUNT("rx_runt_pkts", mib.rx_runt_cnt), + STAT_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), + STAT_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), + STAT_RUNT("rx_runt_bytes", mib.rx_runt_bytes), + /* RXCHK misc statistics */ + STAT_RXCHK("rxchk_bad_csum", mib.rxchk_bad_csum, RXCHK_BAD_CSUM_CNTR), + STAT_RXCHK("rxchk_other_pkt_disc", mib.rxchk_other_pkt_disc, + RXCHK_OTHER_DISC_CNTR), + /* RBUF misc statistics */ + STAT_RBUF("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, RBUF_OVFL_DISC_CNTR), + STAT_RBUF("rbuf_err_cnt", mib.rbuf_err_cnt, RBUF_ERR_PKT_CNTR), + STAT_MIB_SOFT("alloc_rx_buff_failed", mib.alloc_rx_buff_failed), + STAT_MIB_SOFT("rx_dma_failed", mib.rx_dma_failed), + STAT_MIB_SOFT("tx_dma_failed", mib.tx_dma_failed), + /* Per TX-queue statistics are dynamically appended */ +}; + +#define BCM_SYSPORT_STATS_LEN ARRAY_SIZE(bcm_sysport_gstrings_stats) + +static void bcm_sysport_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver)); + strlcpy(info->version, "0.1", sizeof(info->version)); + strlcpy(info->bus_info, "platform", sizeof(info->bus_info)); +} + +static u32 bcm_sysport_get_msglvl(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + + return priv->msg_enable; +} + +static void bcm_sysport_set_msglvl(struct net_device *dev, u32 enable) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + + priv->msg_enable = enable; +} + +static inline bool bcm_sysport_lite_stat_valid(enum bcm_sysport_stat_type type) +{ + switch (type) { + case BCM_SYSPORT_STAT_NETDEV: + case BCM_SYSPORT_STAT_NETDEV64: + case BCM_SYSPORT_STAT_RXCHK: + case BCM_SYSPORT_STAT_RBUF: + case BCM_SYSPORT_STAT_SOFT: + return true; + default: + return false; + } +} + +static int bcm_sysport_get_sset_count(struct net_device *dev, int string_set) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + const struct bcm_sysport_stats *s; + unsigned int i, j; + + switch (string_set) { + case ETH_SS_STATS: + for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { + s = &bcm_sysport_gstrings_stats[i]; + if (priv->is_lite && + !bcm_sysport_lite_stat_valid(s->type)) + continue; + j++; + } + /* Include per-queue statistics */ + return j + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT; + default: + return -EOPNOTSUPP; + } +} + +static void bcm_sysport_get_strings(struct net_device *dev, + u32 stringset, u8 *data) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + const struct bcm_sysport_stats *s; + char buf[128]; + int i, j; + + switch (stringset) { + case ETH_SS_STATS: + for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { + s = &bcm_sysport_gstrings_stats[i]; + if (priv->is_lite && + !bcm_sysport_lite_stat_valid(s->type)) + continue; + + memcpy(data + j * ETH_GSTRING_LEN, s->stat_string, + ETH_GSTRING_LEN); + j++; + } + + for (i = 0; i < dev->num_tx_queues; i++) { + snprintf(buf, sizeof(buf), "txq%d_packets", i); + memcpy(data + j * ETH_GSTRING_LEN, buf, + ETH_GSTRING_LEN); + j++; + + snprintf(buf, sizeof(buf), "txq%d_bytes", i); + memcpy(data + j * ETH_GSTRING_LEN, buf, + ETH_GSTRING_LEN); + j++; + } + break; + default: + break; + } +} + +static void bcm_sysport_update_mib_counters(struct bcm_sysport_priv *priv) +{ + int i, j = 0; + + for (i = 0; i < BCM_SYSPORT_STATS_LEN; i++) { + const struct bcm_sysport_stats *s; + u8 offset = 0; + u32 val = 0; + char *p; + + s = &bcm_sysport_gstrings_stats[i]; + switch (s->type) { + case BCM_SYSPORT_STAT_NETDEV: + case BCM_SYSPORT_STAT_NETDEV64: + case BCM_SYSPORT_STAT_SOFT: + continue; + case BCM_SYSPORT_STAT_MIB_RX: + case BCM_SYSPORT_STAT_MIB_TX: + case BCM_SYSPORT_STAT_RUNT: + if (priv->is_lite) + continue; + + if (s->type != BCM_SYSPORT_STAT_MIB_RX) + offset = UMAC_MIB_STAT_OFFSET; + val = umac_readl(priv, UMAC_MIB_START + j + offset); + break; + case BCM_SYSPORT_STAT_RXCHK: + val = rxchk_readl(priv, s->reg_offset); + if (val == ~0) + rxchk_writel(priv, 0, s->reg_offset); + break; + case BCM_SYSPORT_STAT_RBUF: + val = rbuf_readl(priv, s->reg_offset); + if (val == ~0) + rbuf_writel(priv, 0, s->reg_offset); + break; + } + + j += s->stat_sizeof; + p = (char *)priv + s->stat_offset; + *(u32 *)p = val; + } + + netif_dbg(priv, hw, priv->netdev, "updated MIB counters\n"); +} + +static void bcm_sysport_update_tx_stats(struct bcm_sysport_priv *priv, + u64 *tx_bytes, u64 *tx_packets) +{ + struct bcm_sysport_tx_ring *ring; + u64 bytes = 0, packets = 0; + unsigned int start; + unsigned int q; + + for (q = 0; q < priv->netdev->num_tx_queues; q++) { + ring = &priv->tx_rings[q]; + do { + start = u64_stats_fetch_begin_irq(&priv->syncp); + bytes = ring->bytes; + packets = ring->packets; + } while (u64_stats_fetch_retry_irq(&priv->syncp, start)); + + *tx_bytes += bytes; + *tx_packets += packets; + } +} + +static void bcm_sysport_get_stats(struct net_device *dev, + struct ethtool_stats *stats, u64 *data) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct bcm_sysport_stats64 *stats64 = &priv->stats64; + struct u64_stats_sync *syncp = &priv->syncp; + struct bcm_sysport_tx_ring *ring; + u64 tx_bytes = 0, tx_packets = 0; + unsigned int start; + int i, j; + + if (netif_running(dev)) { + bcm_sysport_update_mib_counters(priv); + bcm_sysport_update_tx_stats(priv, &tx_bytes, &tx_packets); + stats64->tx_bytes = tx_bytes; + stats64->tx_packets = tx_packets; + } + + for (i = 0, j = 0; i < BCM_SYSPORT_STATS_LEN; i++) { + const struct bcm_sysport_stats *s; + char *p; + + s = &bcm_sysport_gstrings_stats[i]; + if (s->type == BCM_SYSPORT_STAT_NETDEV) + p = (char *)&dev->stats; + else if (s->type == BCM_SYSPORT_STAT_NETDEV64) + p = (char *)stats64; + else + p = (char *)priv; + + if (priv->is_lite && !bcm_sysport_lite_stat_valid(s->type)) + continue; + p += s->stat_offset; + + if (s->stat_sizeof == sizeof(u64) && + s->type == BCM_SYSPORT_STAT_NETDEV64) { + do { + start = u64_stats_fetch_begin_irq(syncp); + data[i] = *(u64 *)p; + } while (u64_stats_fetch_retry_irq(syncp, start)); + } else + data[i] = *(u32 *)p; + j++; + } + + /* For SYSTEMPORT Lite since we have holes in our statistics, j would + * be equal to BCM_SYSPORT_STATS_LEN at the end of the loop, but it + * needs to point to how many total statistics we have minus the + * number of per TX queue statistics + */ + j = bcm_sysport_get_sset_count(dev, ETH_SS_STATS) - + dev->num_tx_queues * NUM_SYSPORT_TXQ_STAT; + + for (i = 0; i < dev->num_tx_queues; i++) { + ring = &priv->tx_rings[i]; + data[j] = ring->packets; + j++; + data[j] = ring->bytes; + j++; + } +} + +static void bcm_sysport_get_wol(struct net_device *dev, + struct ethtool_wolinfo *wol) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + u32 reg; + + wol->supported = WAKE_MAGIC | WAKE_MAGICSECURE; + wol->wolopts = priv->wolopts; + + if (!(priv->wolopts & WAKE_MAGICSECURE)) + return; + + /* Return the programmed SecureOn password */ + reg = umac_readl(priv, UMAC_PSW_MS); + put_unaligned_be16(reg, &wol->sopass[0]); + reg = umac_readl(priv, UMAC_PSW_LS); + put_unaligned_be32(reg, &wol->sopass[2]); +} + +static int bcm_sysport_set_wol(struct net_device *dev, + struct ethtool_wolinfo *wol) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct device *kdev = &priv->pdev->dev; + u32 supported = WAKE_MAGIC | WAKE_MAGICSECURE; + + if (!device_can_wakeup(kdev)) + return -ENOTSUPP; + + if (wol->wolopts & ~supported) + return -EINVAL; + + /* Program the SecureOn password */ + if (wol->wolopts & WAKE_MAGICSECURE) { + umac_writel(priv, get_unaligned_be16(&wol->sopass[0]), + UMAC_PSW_MS); + umac_writel(priv, get_unaligned_be32(&wol->sopass[2]), + UMAC_PSW_LS); + } + + /* Flag the device and relevant IRQ as wakeup capable */ + if (wol->wolopts) { + device_set_wakeup_enable(kdev, 1); + if (priv->wol_irq_disabled) + enable_irq_wake(priv->wol_irq); + priv->wol_irq_disabled = 0; + } else { + device_set_wakeup_enable(kdev, 0); + /* Avoid unbalanced disable_irq_wake calls */ + if (!priv->wol_irq_disabled) + disable_irq_wake(priv->wol_irq); + priv->wol_irq_disabled = 1; + } + + priv->wolopts = wol->wolopts; + + return 0; +} + +static int bcm_sysport_get_coalesce(struct net_device *dev, + struct ethtool_coalesce *ec) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + u32 reg; + + reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(0)); + + ec->tx_coalesce_usecs = (reg >> RING_TIMEOUT_SHIFT) * 8192 / 1000; + ec->tx_max_coalesced_frames = reg & RING_INTR_THRESH_MASK; + + reg = rdma_readl(priv, RDMA_MBDONE_INTR); + + ec->rx_coalesce_usecs = (reg >> RDMA_TIMEOUT_SHIFT) * 8192 / 1000; + ec->rx_max_coalesced_frames = reg & RDMA_INTR_THRESH_MASK; + + return 0; +} + +static int bcm_sysport_set_coalesce(struct net_device *dev, + struct ethtool_coalesce *ec) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + unsigned int i; + u32 reg; + + /* Base system clock is 125Mhz, DMA timeout is this reference clock + * divided by 1024, which yield roughly 8.192 us, our maximum value has + * to fit in the RING_TIMEOUT_MASK (16 bits). + */ + if (ec->tx_max_coalesced_frames > RING_INTR_THRESH_MASK || + ec->tx_coalesce_usecs > (RING_TIMEOUT_MASK * 8) + 1 || + ec->rx_max_coalesced_frames > RDMA_INTR_THRESH_MASK || + ec->rx_coalesce_usecs > (RDMA_TIMEOUT_MASK * 8) + 1) + return -EINVAL; + + if ((ec->tx_coalesce_usecs == 0 && ec->tx_max_coalesced_frames == 0) || + (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)) + return -EINVAL; + + for (i = 0; i < dev->num_tx_queues; i++) { + reg = tdma_readl(priv, TDMA_DESC_RING_INTR_CONTROL(i)); + reg &= ~(RING_INTR_THRESH_MASK | + RING_TIMEOUT_MASK << RING_TIMEOUT_SHIFT); + reg |= ec->tx_max_coalesced_frames; + reg |= DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000, 8192) << + RING_TIMEOUT_SHIFT; + tdma_writel(priv, reg, TDMA_DESC_RING_INTR_CONTROL(i)); + } + + reg = rdma_readl(priv, RDMA_MBDONE_INTR); + reg &= ~(RDMA_INTR_THRESH_MASK | + RDMA_TIMEOUT_MASK << RDMA_TIMEOUT_SHIFT); + reg |= ec->rx_max_coalesced_frames; + reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192) << + RDMA_TIMEOUT_SHIFT; + rdma_writel(priv, reg, RDMA_MBDONE_INTR); + + return 0; +} + +static void bcm_sysport_free_cb(struct bcm_sysport_cb *cb) +{ + dev_consume_skb_any(cb->skb); + cb->skb = NULL; + dma_unmap_addr_set(cb, dma_addr, 0); +} + +static struct sk_buff *bcm_sysport_rx_refill(struct bcm_sysport_priv *priv, + struct bcm_sysport_cb *cb) +{ + struct device *kdev = &priv->pdev->dev; + struct net_device *ndev = priv->netdev; + struct sk_buff *skb, *rx_skb; + dma_addr_t mapping; + + /* Allocate a new SKB for a new packet */ + skb = netdev_alloc_skb(priv->netdev, RX_BUF_LENGTH); + if (!skb) { + priv->mib.alloc_rx_buff_failed++; + netif_err(priv, rx_err, ndev, "SKB alloc failed\n"); + return NULL; + } + + mapping = dma_map_single(kdev, skb->data, + RX_BUF_LENGTH, DMA_FROM_DEVICE); + if (dma_mapping_error(kdev, mapping)) { + priv->mib.rx_dma_failed++; + dev_kfree_skb_any(skb); + netif_err(priv, rx_err, ndev, "DMA mapping failure\n"); + return NULL; + } + + /* Grab the current SKB on the ring */ + rx_skb = cb->skb; + if (likely(rx_skb)) + dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), + RX_BUF_LENGTH, DMA_FROM_DEVICE); + + /* Put the new SKB on the ring */ + cb->skb = skb; + dma_unmap_addr_set(cb, dma_addr, mapping); + dma_desc_set_addr(priv, cb->bd_addr, mapping); + + netif_dbg(priv, rx_status, ndev, "RX refill\n"); + + /* Return the current SKB to the caller */ + return rx_skb; +} + +static int bcm_sysport_alloc_rx_bufs(struct bcm_sysport_priv *priv) +{ + struct bcm_sysport_cb *cb; + struct sk_buff *skb; + unsigned int i; + + for (i = 0; i < priv->num_rx_bds; i++) { + cb = &priv->rx_cbs[i]; + skb = bcm_sysport_rx_refill(priv, cb); + if (skb) + dev_kfree_skb(skb); + if (!cb->skb) + return -ENOMEM; + } + + return 0; +} + +/* Poll the hardware for up to budget packets to process */ +static unsigned int bcm_sysport_desc_rx(struct bcm_sysport_priv *priv, + unsigned int budget) +{ + struct bcm_sysport_stats64 *stats64 = &priv->stats64; + struct net_device *ndev = priv->netdev; + unsigned int processed = 0, to_process; + struct bcm_sysport_cb *cb; + struct sk_buff *skb; + unsigned int p_index; + u16 len, status; + struct bcm_rsb *rsb; + + /* Clear status before servicing to reduce spurious interrupts */ + intrl2_0_writel(priv, INTRL2_0_RDMA_MBDONE, INTRL2_CPU_CLEAR); + + /* Determine how much we should process since last call, SYSTEMPORT Lite + * groups the producer and consumer indexes into the same 32-bit + * which we access using RDMA_CONS_INDEX + */ + if (!priv->is_lite) + p_index = rdma_readl(priv, RDMA_PROD_INDEX); + else + p_index = rdma_readl(priv, RDMA_CONS_INDEX); + p_index &= RDMA_PROD_INDEX_MASK; + + to_process = (p_index - priv->rx_c_index) & RDMA_CONS_INDEX_MASK; + + netif_dbg(priv, rx_status, ndev, + "p_index=%d rx_c_index=%d to_process=%d\n", + p_index, priv->rx_c_index, to_process); + + while ((processed < to_process) && (processed < budget)) { + cb = &priv->rx_cbs[priv->rx_read_ptr]; + skb = bcm_sysport_rx_refill(priv, cb); + + + /* We do not have a backing SKB, so we do not a corresponding + * DMA mapping for this incoming packet since + * bcm_sysport_rx_refill always either has both skb and mapping + * or none. + */ + if (unlikely(!skb)) { + netif_err(priv, rx_err, ndev, "out of memory!\n"); + ndev->stats.rx_dropped++; + ndev->stats.rx_errors++; + goto next; + } + + /* Extract the Receive Status Block prepended */ + rsb = (struct bcm_rsb *)skb->data; + len = (rsb->rx_status_len >> DESC_LEN_SHIFT) & DESC_LEN_MASK; + status = (rsb->rx_status_len >> DESC_STATUS_SHIFT) & + DESC_STATUS_MASK; + + netif_dbg(priv, rx_status, ndev, + "p=%d, c=%d, rd_ptr=%d, len=%d, flag=0x%04x\n", + p_index, priv->rx_c_index, priv->rx_read_ptr, + len, status); + + if (unlikely(len > RX_BUF_LENGTH)) { + netif_err(priv, rx_status, ndev, "oversized packet\n"); + ndev->stats.rx_length_errors++; + ndev->stats.rx_errors++; + dev_kfree_skb_any(skb); + goto next; + } + + if (unlikely(!(status & DESC_EOP) || !(status & DESC_SOP))) { + netif_err(priv, rx_status, ndev, "fragmented packet!\n"); + ndev->stats.rx_dropped++; + ndev->stats.rx_errors++; + dev_kfree_skb_any(skb); + goto next; + } + + if (unlikely(status & (RX_STATUS_ERR | RX_STATUS_OVFLOW))) { + netif_err(priv, rx_err, ndev, "error packet\n"); + if (status & RX_STATUS_OVFLOW) + ndev->stats.rx_over_errors++; + ndev->stats.rx_dropped++; + ndev->stats.rx_errors++; + dev_kfree_skb_any(skb); + goto next; + } + + skb_put(skb, len); + + /* Hardware validated our checksum */ + if (likely(status & DESC_L4_CSUM)) + skb->ip_summed = CHECKSUM_UNNECESSARY; + + /* Hardware pre-pends packets with 2bytes before Ethernet + * header plus we have the Receive Status Block, strip off all + * of this from the SKB. + */ + skb_pull(skb, sizeof(*rsb) + 2); + len -= (sizeof(*rsb) + 2); + + /* UniMAC may forward CRC */ + if (priv->crc_fwd) { + skb_trim(skb, len - ETH_FCS_LEN); + len -= ETH_FCS_LEN; + } + + skb->protocol = eth_type_trans(skb, ndev); + ndev->stats.rx_packets++; + ndev->stats.rx_bytes += len; + u64_stats_update_begin(&priv->syncp); + stats64->rx_packets++; + stats64->rx_bytes += len; + u64_stats_update_end(&priv->syncp); + + napi_gro_receive(&priv->napi, skb); +next: + processed++; + priv->rx_read_ptr++; + + if (priv->rx_read_ptr == priv->num_rx_bds) + priv->rx_read_ptr = 0; + } + + return processed; +} + +static void bcm_sysport_tx_reclaim_one(struct bcm_sysport_tx_ring *ring, + struct bcm_sysport_cb *cb, + unsigned int *bytes_compl, + unsigned int *pkts_compl) +{ + struct bcm_sysport_priv *priv = ring->priv; + struct device *kdev = &priv->pdev->dev; + + if (cb->skb) { + *bytes_compl += cb->skb->len; + dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr), + dma_unmap_len(cb, dma_len), + DMA_TO_DEVICE); + (*pkts_compl)++; + bcm_sysport_free_cb(cb); + /* SKB fragment */ + } else if (dma_unmap_addr(cb, dma_addr)) { + *bytes_compl += dma_unmap_len(cb, dma_len); + dma_unmap_page(kdev, dma_unmap_addr(cb, dma_addr), + dma_unmap_len(cb, dma_len), DMA_TO_DEVICE); + dma_unmap_addr_set(cb, dma_addr, 0); + } +} + +/* Reclaim queued SKBs for transmission completion, lockless version */ +static unsigned int __bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, + struct bcm_sysport_tx_ring *ring) +{ + unsigned int pkts_compl = 0, bytes_compl = 0; + struct net_device *ndev = priv->netdev; + unsigned int txbds_processed = 0; + struct bcm_sysport_cb *cb; + unsigned int txbds_ready; + unsigned int c_index; + u32 hw_ind; + + /* Clear status before servicing to reduce spurious interrupts */ + if (!ring->priv->is_lite) + intrl2_1_writel(ring->priv, BIT(ring->index), INTRL2_CPU_CLEAR); + else + intrl2_0_writel(ring->priv, BIT(ring->index + + INTRL2_0_TDMA_MBDONE_SHIFT), INTRL2_CPU_CLEAR); + + /* Compute how many descriptors have been processed since last call */ + hw_ind = tdma_readl(priv, TDMA_DESC_RING_PROD_CONS_INDEX(ring->index)); + c_index = (hw_ind >> RING_CONS_INDEX_SHIFT) & RING_CONS_INDEX_MASK; + txbds_ready = (c_index - ring->c_index) & RING_CONS_INDEX_MASK; + + netif_dbg(priv, tx_done, ndev, + "ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n", + ring->index, ring->c_index, c_index, txbds_ready); + + while (txbds_processed < txbds_ready) { + cb = &ring->cbs[ring->clean_index]; + bcm_sysport_tx_reclaim_one(ring, cb, &bytes_compl, &pkts_compl); + + ring->desc_count++; + txbds_processed++; + + if (likely(ring->clean_index < ring->size - 1)) + ring->clean_index++; + else + ring->clean_index = 0; + } + + u64_stats_update_begin(&priv->syncp); + ring->packets += pkts_compl; + ring->bytes += bytes_compl; + u64_stats_update_end(&priv->syncp); + + ring->c_index = c_index; + + netif_dbg(priv, tx_done, ndev, + "ring=%d c_index=%d pkts_compl=%d, bytes_compl=%d\n", + ring->index, ring->c_index, pkts_compl, bytes_compl); + + return pkts_compl; +} + +/* Locked version of the per-ring TX reclaim routine */ +static unsigned int bcm_sysport_tx_reclaim(struct bcm_sysport_priv *priv, + struct bcm_sysport_tx_ring *ring) +{ + struct netdev_queue *txq; + unsigned int released; + unsigned long flags; + + txq = netdev_get_tx_queue(priv->netdev, ring->index); + + spin_lock_irqsave(&ring->lock, flags); + released = __bcm_sysport_tx_reclaim(priv, ring); + if (released) + netif_tx_wake_queue(txq); + + spin_unlock_irqrestore(&ring->lock, flags); + + return released; +} + +/* Locked version of the per-ring TX reclaim, but does not wake the queue */ +static void bcm_sysport_tx_clean(struct bcm_sysport_priv *priv, + struct bcm_sysport_tx_ring *ring) +{ + unsigned long flags; + + spin_lock_irqsave(&ring->lock, flags); + __bcm_sysport_tx_reclaim(priv, ring); + spin_unlock_irqrestore(&ring->lock, flags); +} + +static int bcm_sysport_tx_poll(struct napi_struct *napi, int budget) +{ + struct bcm_sysport_tx_ring *ring = + container_of(napi, struct bcm_sysport_tx_ring, napi); + unsigned int work_done = 0; + + work_done = bcm_sysport_tx_reclaim(ring->priv, ring); + + if (work_done == 0) { + napi_complete(napi); + /* re-enable TX interrupt */ + if (!ring->priv->is_lite) + intrl2_1_mask_clear(ring->priv, BIT(ring->index)); + else + intrl2_0_mask_clear(ring->priv, BIT(ring->index + + INTRL2_0_TDMA_MBDONE_SHIFT)); + + return 0; + } + + return budget; +} + +static void bcm_sysport_tx_reclaim_all(struct bcm_sysport_priv *priv) +{ + unsigned int q; + + for (q = 0; q < priv->netdev->num_tx_queues; q++) + bcm_sysport_tx_reclaim(priv, &priv->tx_rings[q]); +} + +static int bcm_sysport_poll(struct napi_struct *napi, int budget) +{ + struct bcm_sysport_priv *priv = + container_of(napi, struct bcm_sysport_priv, napi); + unsigned int work_done = 0; + + work_done = bcm_sysport_desc_rx(priv, budget); + + priv->rx_c_index += work_done; + priv->rx_c_index &= RDMA_CONS_INDEX_MASK; + + /* SYSTEMPORT Lite groups the producer/consumer index, producer is + * maintained by HW, but writes to it will be ignore while RDMA + * is active + */ + if (!priv->is_lite) + rdma_writel(priv, priv->rx_c_index, RDMA_CONS_INDEX); + else + rdma_writel(priv, priv->rx_c_index << 16, RDMA_CONS_INDEX); + + if (work_done < budget) { + napi_complete_done(napi, work_done); + /* re-enable RX interrupts */ + intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE); + } + + return work_done; +} + +static __maybe_unused void bcm_sysport_resume_from_wol(struct bcm_sysport_priv *priv) +{ + u32 reg; + + /* Clear the MagicPacket detection logic */ + reg = umac_readl(priv, UMAC_MPD_CTRL); + reg &= ~MPD_EN; + umac_writel(priv, reg, UMAC_MPD_CTRL); + + reg = intrl2_0_readl(priv, INTRL2_CPU_STATUS); + if (reg & INTRL2_0_MPD) + netdev_info(priv->netdev, "Wake-on-LAN (MPD) interrupt!\n"); + + if (reg & INTRL2_0_BRCM_MATCH_TAG) { + reg = rxchk_readl(priv, RXCHK_BRCM_TAG_MATCH_STATUS) & + RXCHK_BRCM_TAG_MATCH_MASK; + netdev_info(priv->netdev, + "Wake-on-LAN (filters 0x%02x) interrupt!\n", reg); + } + + netif_dbg(priv, wol, priv->netdev, "resumed from WOL\n"); +} + +/* RX and misc interrupt routine */ +static irqreturn_t bcm_sysport_rx_isr(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct bcm_sysport_tx_ring *txr; + unsigned int ring, ring_bit; + + priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & + ~intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); + intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); + + if (unlikely(priv->irq0_stat == 0)) { + netdev_warn(priv->netdev, "spurious RX interrupt\n"); + return IRQ_NONE; + } + + if (priv->irq0_stat & INTRL2_0_RDMA_MBDONE) { + if (likely(napi_schedule_prep(&priv->napi))) { + /* disable RX interrupts */ + intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE); + __napi_schedule_irqoff(&priv->napi); + } + } + + /* TX ring is full, perform a full reclaim since we do not know + * which one would trigger this interrupt + */ + if (priv->irq0_stat & INTRL2_0_TX_RING_FULL) + bcm_sysport_tx_reclaim_all(priv); + + if (!priv->is_lite) + goto out; + + for (ring = 0; ring < dev->num_tx_queues; ring++) { + ring_bit = BIT(ring + INTRL2_0_TDMA_MBDONE_SHIFT); + if (!(priv->irq0_stat & ring_bit)) + continue; + + txr = &priv->tx_rings[ring]; + + if (likely(napi_schedule_prep(&txr->napi))) { + intrl2_0_mask_set(priv, ring_bit); + __napi_schedule(&txr->napi); + } + } +out: + return IRQ_HANDLED; +} + +/* TX interrupt service routine */ +static irqreturn_t bcm_sysport_tx_isr(int irq, void *dev_id) +{ + struct net_device *dev = dev_id; + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct bcm_sysport_tx_ring *txr; + unsigned int ring; + + priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & + ~intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS); + intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); + + if (unlikely(priv->irq1_stat == 0)) { + netdev_warn(priv->netdev, "spurious TX interrupt\n"); + return IRQ_NONE; + } + + for (ring = 0; ring < dev->num_tx_queues; ring++) { + if (!(priv->irq1_stat & BIT(ring))) + continue; + + txr = &priv->tx_rings[ring]; + + if (likely(napi_schedule_prep(&txr->napi))) { + intrl2_1_mask_set(priv, BIT(ring)); + __napi_schedule_irqoff(&txr->napi); + } + } + + return IRQ_HANDLED; +} + +static irqreturn_t bcm_sysport_wol_isr(int irq, void *dev_id) +{ + struct bcm_sysport_priv *priv = dev_id; + + pm_wakeup_event(&priv->pdev->dev, 0); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_NET_POLL_CONTROLLER +static void bcm_sysport_poll_controller(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + + disable_irq(priv->irq0); + bcm_sysport_rx_isr(priv->irq0, priv); + enable_irq(priv->irq0); + + if (!priv->is_lite) { + disable_irq(priv->irq1); + bcm_sysport_tx_isr(priv->irq1, priv); + enable_irq(priv->irq1); + } +} +#endif + +static struct sk_buff *bcm_sysport_insert_tsb(struct sk_buff *skb, + struct net_device *dev) +{ + struct sk_buff *nskb; + struct bcm_tsb *tsb; + u32 csum_info; + u8 ip_proto; + u16 csum_start; + u16 ip_ver; + + /* Re-allocate SKB if needed */ + if (unlikely(skb_headroom(skb) < sizeof(*tsb))) { + nskb = skb_realloc_headroom(skb, sizeof(*tsb)); + dev_kfree_skb(skb); + if (!nskb) { + dev->stats.tx_errors++; + dev->stats.tx_dropped++; + return NULL; + } + skb = nskb; + } + + tsb = skb_push(skb, sizeof(*tsb)); + /* Zero-out TSB by default */ + memset(tsb, 0, sizeof(*tsb)); + + if (skb->ip_summed == CHECKSUM_PARTIAL) { + ip_ver = htons(skb->protocol); + switch (ip_ver) { + case ETH_P_IP: + ip_proto = ip_hdr(skb)->protocol; + break; + case ETH_P_IPV6: + ip_proto = ipv6_hdr(skb)->nexthdr; + break; + default: + return skb; + } + + /* Get the checksum offset and the L4 (transport) offset */ + csum_start = skb_checksum_start_offset(skb) - sizeof(*tsb); + csum_info = (csum_start + skb->csum_offset) & L4_CSUM_PTR_MASK; + csum_info |= (csum_start << L4_PTR_SHIFT); + + if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { + csum_info |= L4_LENGTH_VALID; + if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) + csum_info |= L4_UDP; + } else { + csum_info = 0; + } + + tsb->l4_ptr_dest_map = csum_info; + } + + return skb; +} + +static netdev_tx_t bcm_sysport_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct device *kdev = &priv->pdev->dev; + struct bcm_sysport_tx_ring *ring; + struct bcm_sysport_cb *cb; + struct netdev_queue *txq; + unsigned int skb_len; + unsigned long flags; + dma_addr_t mapping; + u32 len_status, addr_lo; + u16 queue; + int ret; + + queue = skb_get_queue_mapping(skb); + txq = netdev_get_tx_queue(dev, queue); + ring = &priv->tx_rings[queue]; + + /* lock against tx reclaim in BH context and TX ring full interrupt */ + spin_lock_irqsave(&ring->lock, flags); + if (unlikely(ring->desc_count == 0)) { + netif_tx_stop_queue(txq); + netdev_err(dev, "queue %d awake and ring full!\n", queue); + ret = NETDEV_TX_BUSY; + goto out; + } + + /* The Ethernet switch we are interfaced with needs packets to be at + * least 64 bytes (including FCS) otherwise they will be discarded when + * they enter the switch port logic. When Broadcom tags are enabled, we + * need to make sure that packets are at least 68 bytes + * (including FCS and tag) because the length verification is done after + * the Broadcom tag is stripped off the ingress packet. + */ + if (skb_put_padto(skb, ETH_ZLEN + ENET_BRCM_TAG_LEN)) { + ret = NETDEV_TX_OK; + goto out; + } + + /* Insert TSB and checksum infos */ + if (priv->tsb_en) { + skb = bcm_sysport_insert_tsb(skb, dev); + if (!skb) { + ret = NETDEV_TX_OK; + goto out; + } + } + + skb_len = skb->len; + + mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); + if (dma_mapping_error(kdev, mapping)) { + priv->mib.tx_dma_failed++; + netif_err(priv, tx_err, dev, "DMA map failed at %p (len=%d)\n", + skb->data, skb_len); + ret = NETDEV_TX_OK; + goto out; + } + + /* Remember the SKB for future freeing */ + cb = &ring->cbs[ring->curr_desc]; + cb->skb = skb; + dma_unmap_addr_set(cb, dma_addr, mapping); + dma_unmap_len_set(cb, dma_len, skb_len); + + addr_lo = lower_32_bits(mapping); + len_status = upper_32_bits(mapping) & DESC_ADDR_HI_MASK; + len_status |= (skb_len << DESC_LEN_SHIFT); + len_status |= (DESC_SOP | DESC_EOP | TX_STATUS_APP_CRC) << + DESC_STATUS_SHIFT; + if (skb->ip_summed == CHECKSUM_PARTIAL) + len_status |= (DESC_L4_CSUM << DESC_STATUS_SHIFT); + + ring->curr_desc++; + if (ring->curr_desc == ring->size) + ring->curr_desc = 0; + ring->desc_count--; + + /* Ports are latched, so write upper address first */ + tdma_writel(priv, addr_lo, TDMA_WRITE_PORT_HI(ring->index)); + tdma_writel(priv, len_status, TDMA_WRITE_PORT_LO(ring->index)); + + /* Check ring space and update SW control flow */ + if (ring->desc_count == 0) + netif_tx_stop_queue(txq); + + netif_dbg(priv, tx_queued, dev, "ring=%d desc_count=%d, curr_desc=%d\n", + ring->index, ring->desc_count, ring->curr_desc); + + ret = NETDEV_TX_OK; +out: + spin_unlock_irqrestore(&ring->lock, flags); + return ret; +} + +static void bcm_sysport_tx_timeout(struct net_device *dev) +{ + netdev_warn(dev, "transmit timeout!\n"); + + netif_trans_update(dev); + dev->stats.tx_errors++; + + netif_tx_wake_all_queues(dev); +} + +/* phylib adjust link callback */ +static void bcm_sysport_adj_link(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct phy_device *phydev = dev->phydev; + unsigned int changed = 0; + u32 cmd_bits = 0, reg; + + if (priv->old_link != phydev->link) { + changed = 1; + priv->old_link = phydev->link; + } + + if (priv->old_duplex != phydev->duplex) { + changed = 1; + priv->old_duplex = phydev->duplex; + } + + if (priv->is_lite) + goto out; + + switch (phydev->speed) { + case SPEED_2500: + cmd_bits = CMD_SPEED_2500; + break; + case SPEED_1000: + cmd_bits = CMD_SPEED_1000; + break; + case SPEED_100: + cmd_bits = CMD_SPEED_100; + break; + case SPEED_10: + cmd_bits = CMD_SPEED_10; + break; + default: + break; + } + cmd_bits <<= CMD_SPEED_SHIFT; + + if (phydev->duplex == DUPLEX_HALF) + cmd_bits |= CMD_HD_EN; + + if (priv->old_pause != phydev->pause) { + changed = 1; + priv->old_pause = phydev->pause; + } + + if (!phydev->pause) + cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE; + + if (!changed) + return; + + if (phydev->link) { + reg = umac_readl(priv, UMAC_CMD); + reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) | + CMD_HD_EN | CMD_RX_PAUSE_IGNORE | + CMD_TX_PAUSE_IGNORE); + reg |= cmd_bits; + umac_writel(priv, reg, UMAC_CMD); + } +out: + if (changed) + phy_print_status(phydev); +} + +static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, + unsigned int index) +{ + struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; + size_t size; + u32 reg; + + /* Simple descriptors partitioning for now */ + size = 256; + + ring->cbs = kcalloc(size, sizeof(struct bcm_sysport_cb), GFP_KERNEL); + if (!ring->cbs) { + netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); + return -ENOMEM; + } + + /* Initialize SW view of the ring */ + spin_lock_init(&ring->lock); + ring->priv = priv; + netif_tx_napi_add(priv->netdev, &ring->napi, bcm_sysport_tx_poll, 64); + ring->index = index; + ring->size = size; + ring->clean_index = 0; + ring->alloc_size = ring->size; + ring->desc_count = ring->size; + ring->curr_desc = 0; + + /* Initialize HW ring */ + tdma_writel(priv, RING_EN, TDMA_DESC_RING_HEAD_TAIL_PTR(index)); + tdma_writel(priv, 0, TDMA_DESC_RING_COUNT(index)); + tdma_writel(priv, 1, TDMA_DESC_RING_INTR_CONTROL(index)); + tdma_writel(priv, 0, TDMA_DESC_RING_PROD_CONS_INDEX(index)); + tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); + tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); + + /* Do not use tdma_control_bit() here because TSB_SWAP1 collides + * with the original definition of ACB_ALGO + */ + reg = tdma_readl(priv, TDMA_CONTROL); + if (priv->is_lite) + reg &= ~BIT(TSB_SWAP1); + /* Set a correct TSB format based on host endian */ + if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + reg |= tdma_control_bit(priv, TSB_SWAP0); + else + reg &= ~tdma_control_bit(priv, TSB_SWAP0); + tdma_writel(priv, reg, TDMA_CONTROL); + + /* Program the number of descriptors as MAX_THRESHOLD and half of + * its size for the hysteresis trigger + */ + tdma_writel(priv, ring->size | + 1 << RING_HYST_THRESH_SHIFT, + TDMA_DESC_RING_MAX_HYST(index)); + + /* Enable the ring queue in the arbiter */ + reg = tdma_readl(priv, TDMA_TIER1_ARB_0_QUEUE_EN); + reg |= (1 << index); + tdma_writel(priv, reg, TDMA_TIER1_ARB_0_QUEUE_EN); + + napi_enable(&ring->napi); + + netif_dbg(priv, hw, priv->netdev, + "TDMA cfg, size=%d\n", + ring->size); + + return 0; +} + +static void bcm_sysport_fini_tx_ring(struct bcm_sysport_priv *priv, + unsigned int index) +{ + struct bcm_sysport_tx_ring *ring = &priv->tx_rings[index]; + u32 reg; + + /* Caller should stop the TDMA engine */ + reg = tdma_readl(priv, TDMA_STATUS); + if (!(reg & TDMA_DISABLED)) + netdev_warn(priv->netdev, "TDMA not stopped!\n"); + + /* ring->cbs is the last part in bcm_sysport_init_tx_ring which could + * fail, so by checking this pointer we know whether the TX ring was + * fully initialized or not. + */ + if (!ring->cbs) + return; + + napi_disable(&ring->napi); + netif_napi_del(&ring->napi); + + bcm_sysport_tx_clean(priv, ring); + + kfree(ring->cbs); + ring->cbs = NULL; + + ring->size = 0; + ring->alloc_size = 0; + + netif_dbg(priv, hw, priv->netdev, "TDMA fini done\n"); +} + +/* RDMA helper */ +static inline int rdma_enable_set(struct bcm_sysport_priv *priv, + unsigned int enable) +{ + unsigned int timeout = 1000; + u32 reg; + + reg = rdma_readl(priv, RDMA_CONTROL); + if (enable) + reg |= RDMA_EN; + else + reg &= ~RDMA_EN; + rdma_writel(priv, reg, RDMA_CONTROL); + + /* Poll for RMDA disabling completion */ + do { + reg = rdma_readl(priv, RDMA_STATUS); + if (!!(reg & RDMA_DISABLED) == !enable) + return 0; + usleep_range(1000, 2000); + } while (timeout-- > 0); + + netdev_err(priv->netdev, "timeout waiting for RDMA to finish\n"); + + return -ETIMEDOUT; +} + +/* TDMA helper */ +static inline int tdma_enable_set(struct bcm_sysport_priv *priv, + unsigned int enable) +{ + unsigned int timeout = 1000; + u32 reg; + + reg = tdma_readl(priv, TDMA_CONTROL); + if (enable) + reg |= tdma_control_bit(priv, TDMA_EN); + else + reg &= ~tdma_control_bit(priv, TDMA_EN); + tdma_writel(priv, reg, TDMA_CONTROL); + + /* Poll for TMDA disabling completion */ + do { + reg = tdma_readl(priv, TDMA_STATUS); + if (!!(reg & TDMA_DISABLED) == !enable) + return 0; + + usleep_range(1000, 2000); + } while (timeout-- > 0); + + netdev_err(priv->netdev, "timeout waiting for TDMA to finish\n"); + + return -ETIMEDOUT; +} + +static int bcm_sysport_init_rx_ring(struct bcm_sysport_priv *priv) +{ + struct bcm_sysport_cb *cb; + u32 reg; + int ret; + int i; + + /* Initialize SW view of the RX ring */ + priv->num_rx_bds = priv->num_rx_desc_words / WORDS_PER_DESC; + priv->rx_bds = priv->base + SYS_PORT_RDMA_OFFSET; + priv->rx_c_index = 0; + priv->rx_read_ptr = 0; + priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct bcm_sysport_cb), + GFP_KERNEL); + if (!priv->rx_cbs) { + netif_err(priv, hw, priv->netdev, "CB allocation failed\n"); + return -ENOMEM; + } + + for (i = 0; i < priv->num_rx_bds; i++) { + cb = priv->rx_cbs + i; + cb->bd_addr = priv->rx_bds + i * DESC_SIZE; + } + + ret = bcm_sysport_alloc_rx_bufs(priv); + if (ret) { + netif_err(priv, hw, priv->netdev, "SKB allocation failed\n"); + return ret; + } + + /* Initialize HW, ensure RDMA is disabled */ + reg = rdma_readl(priv, RDMA_STATUS); + if (!(reg & RDMA_DISABLED)) + rdma_enable_set(priv, 0); + + rdma_writel(priv, 0, RDMA_WRITE_PTR_LO); + rdma_writel(priv, 0, RDMA_WRITE_PTR_HI); + rdma_writel(priv, 0, RDMA_PROD_INDEX); + rdma_writel(priv, 0, RDMA_CONS_INDEX); + rdma_writel(priv, priv->num_rx_bds << RDMA_RING_SIZE_SHIFT | + RX_BUF_LENGTH, RDMA_RING_BUF_SIZE); + /* Operate the queue in ring mode */ + rdma_writel(priv, 0, RDMA_START_ADDR_HI); + rdma_writel(priv, 0, RDMA_START_ADDR_LO); + + rdma_writel(priv, 1, RDMA_MBDONE_INTR); + + netif_dbg(priv, hw, priv->netdev, + "RDMA cfg, num_rx_bds=%d, rx_bds=%p\n", + priv->num_rx_bds, priv->rx_bds); + + return 0; +} + +static void bcm_sysport_fini_rx_ring(struct bcm_sysport_priv *priv) +{ + struct bcm_sysport_cb *cb; + unsigned int i; + u32 reg; + + /* Caller should ensure RDMA is disabled */ + reg = rdma_readl(priv, RDMA_STATUS); + if (!(reg & RDMA_DISABLED)) + netdev_warn(priv->netdev, "RDMA not stopped!\n"); + + for (i = 0; i < priv->num_rx_bds; i++) { + cb = &priv->rx_cbs[i]; + if (dma_unmap_addr(cb, dma_addr)) + dma_unmap_single(&priv->pdev->dev, + dma_unmap_addr(cb, dma_addr), + RX_BUF_LENGTH, DMA_FROM_DEVICE); + bcm_sysport_free_cb(cb); + } + + kfree(priv->rx_cbs); + priv->rx_cbs = NULL; + + netif_dbg(priv, hw, priv->netdev, "RDMA fini done\n"); +} + +static void bcm_sysport_set_rx_mode(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + u32 reg; + + if (priv->is_lite) + return; + + reg = umac_readl(priv, UMAC_CMD); + if (dev->flags & IFF_PROMISC) + reg |= CMD_PROMISC; + else + reg &= ~CMD_PROMISC; + umac_writel(priv, reg, UMAC_CMD); + + /* No support for ALLMULTI */ + if (dev->flags & IFF_ALLMULTI) + return; +} + +static inline void umac_enable_set(struct bcm_sysport_priv *priv, + u32 mask, unsigned int enable) +{ + u32 reg; + + if (!priv->is_lite) { + reg = umac_readl(priv, UMAC_CMD); + if (enable) + reg |= mask; + else + reg &= ~mask; + umac_writel(priv, reg, UMAC_CMD); + } else { + reg = gib_readl(priv, GIB_CONTROL); + if (enable) + reg |= mask; + else + reg &= ~mask; + gib_writel(priv, reg, GIB_CONTROL); + } + + /* UniMAC stops on a packet boundary, wait for a full-sized packet + * to be processed (1 msec). + */ + if (enable == 0) + usleep_range(1000, 2000); +} + +static inline void umac_reset(struct bcm_sysport_priv *priv) +{ + u32 reg; + + if (priv->is_lite) + return; + + reg = umac_readl(priv, UMAC_CMD); + reg |= CMD_SW_RESET; + umac_writel(priv, reg, UMAC_CMD); + udelay(10); + reg = umac_readl(priv, UMAC_CMD); + reg &= ~CMD_SW_RESET; + umac_writel(priv, reg, UMAC_CMD); +} + +static void umac_set_hw_addr(struct bcm_sysport_priv *priv, + unsigned char *addr) +{ + u32 mac0 = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | + addr[3]; + u32 mac1 = (addr[4] << 8) | addr[5]; + + if (!priv->is_lite) { + umac_writel(priv, mac0, UMAC_MAC0); + umac_writel(priv, mac1, UMAC_MAC1); + } else { + gib_writel(priv, mac0, GIB_MAC0); + gib_writel(priv, mac1, GIB_MAC1); + } +} + +static void topctrl_flush(struct bcm_sysport_priv *priv) +{ + topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); + topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); + mdelay(1); + topctrl_writel(priv, 0, RX_FLUSH_CNTL); + topctrl_writel(priv, 0, TX_FLUSH_CNTL); +} + +static int bcm_sysport_change_mac(struct net_device *dev, void *p) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct sockaddr *addr = p; + + if (!is_valid_ether_addr(addr->sa_data)) + return -EINVAL; + + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); + + /* interface is disabled, changes to MAC will be reflected on next + * open call + */ + if (!netif_running(dev)) + return 0; + + umac_set_hw_addr(priv, dev->dev_addr); + + return 0; +} + +static void bcm_sysport_get_stats64(struct net_device *dev, + struct rtnl_link_stats64 *stats) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct bcm_sysport_stats64 *stats64 = &priv->stats64; + unsigned int start; + + netdev_stats_to_stats64(stats, &dev->stats); + + bcm_sysport_update_tx_stats(priv, &stats->tx_bytes, + &stats->tx_packets); + + do { + start = u64_stats_fetch_begin_irq(&priv->syncp); + stats->rx_packets = stats64->rx_packets; + stats->rx_bytes = stats64->rx_bytes; + } while (u64_stats_fetch_retry_irq(&priv->syncp, start)); +} + +static void bcm_sysport_netif_start(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + + /* Enable NAPI */ + napi_enable(&priv->napi); + + /* Enable RX interrupt and TX ring full interrupt */ + intrl2_0_mask_clear(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); + + phy_start(dev->phydev); + + /* Enable TX interrupts for the TXQs */ + if (!priv->is_lite) + intrl2_1_mask_clear(priv, 0xffffffff); + else + intrl2_0_mask_clear(priv, INTRL2_0_TDMA_MBDONE_MASK); +} + +static void rbuf_init(struct bcm_sysport_priv *priv) +{ + u32 reg; + + reg = rbuf_readl(priv, RBUF_CONTROL); + reg |= RBUF_4B_ALGN | RBUF_RSB_EN; + reg &= ~RBUF_RSB_SWAP1; + + /* Set a correct RSB format based on host endian */ + if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) + reg |= RBUF_RSB_SWAP0; + else + reg &= ~RBUF_RSB_SWAP0; + rbuf_writel(priv, reg, RBUF_CONTROL); +} + +static inline void bcm_sysport_mask_all_intrs(struct bcm_sysport_priv *priv) +{ + intrl2_0_mask_set(priv, 0xffffffff); + intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); + if (!priv->is_lite) { + intrl2_1_mask_set(priv, 0xffffffff); + intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); + } +} + +static inline void gib_set_pad_extension(struct bcm_sysport_priv *priv) +{ + u32 reg; + + reg = gib_readl(priv, GIB_CONTROL); + /* Include Broadcom tag in pad extension and fix up IPG_LENGTH */ + if (netdev_uses_dsa(priv->netdev)) { + reg &= ~(GIB_PAD_EXTENSION_MASK << GIB_PAD_EXTENSION_SHIFT); + reg |= ENET_BRCM_TAG_LEN << GIB_PAD_EXTENSION_SHIFT; + } + reg &= ~(GIB_IPG_LEN_MASK << GIB_IPG_LEN_SHIFT); + reg |= 12 << GIB_IPG_LEN_SHIFT; + gib_writel(priv, reg, GIB_CONTROL); +} + +static int bcm_sysport_open(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + struct phy_device *phydev; + unsigned int i; + int ret; + + /* Reset UniMAC */ + umac_reset(priv); + + /* Flush TX and RX FIFOs at TOPCTRL level */ + topctrl_flush(priv); + + /* Disable the UniMAC RX/TX */ + umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 0); + + /* Enable RBUF 2bytes alignment and Receive Status Block */ + rbuf_init(priv); + + /* Set maximum frame length */ + if (!priv->is_lite) + umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); + else + gib_set_pad_extension(priv); + + /* Set MAC address */ + umac_set_hw_addr(priv, dev->dev_addr); + + /* Read CRC forward */ + if (!priv->is_lite) + priv->crc_fwd = !!(umac_readl(priv, UMAC_CMD) & CMD_CRC_FWD); + else + priv->crc_fwd = !((gib_readl(priv, GIB_CONTROL) & + GIB_FCS_STRIP) >> GIB_FCS_STRIP_SHIFT); + + phydev = of_phy_connect(dev, priv->phy_dn, bcm_sysport_adj_link, + 0, priv->phy_interface); + if (!phydev) { + netdev_err(dev, "could not attach to PHY\n"); + return -ENODEV; + } + + /* Reset house keeping link status */ + priv->old_duplex = -1; + priv->old_link = -1; + priv->old_pause = -1; + + /* mask all interrupts and request them */ + bcm_sysport_mask_all_intrs(priv); + + ret = request_irq(priv->irq0, bcm_sysport_rx_isr, 0, dev->name, dev); + if (ret) { + netdev_err(dev, "failed to request RX interrupt\n"); + goto out_phy_disconnect; + } + + if (!priv->is_lite) { + ret = request_irq(priv->irq1, bcm_sysport_tx_isr, 0, + dev->name, dev); + if (ret) { + netdev_err(dev, "failed to request TX interrupt\n"); + goto out_free_irq0; + } + } + + /* Initialize both hardware and software ring */ + for (i = 0; i < dev->num_tx_queues; i++) { + ret = bcm_sysport_init_tx_ring(priv, i); + if (ret) { + netdev_err(dev, "failed to initialize TX ring %d\n", + i); + goto out_free_tx_ring; + } + } + + /* Initialize linked-list */ + tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); + + /* Initialize RX ring */ + ret = bcm_sysport_init_rx_ring(priv); + if (ret) { + netdev_err(dev, "failed to initialize RX ring\n"); + goto out_free_rx_ring; + } + + /* Turn on RDMA */ + ret = rdma_enable_set(priv, 1); + if (ret) + goto out_free_rx_ring; + + /* Turn on TDMA */ + ret = tdma_enable_set(priv, 1); + if (ret) + goto out_clear_rx_int; + + /* Turn on UniMAC TX/RX */ + umac_enable_set(priv, CMD_RX_EN | CMD_TX_EN, 1); + + bcm_sysport_netif_start(dev); + + netif_tx_start_all_queues(dev); + + return 0; + +out_clear_rx_int: + intrl2_0_mask_set(priv, INTRL2_0_RDMA_MBDONE | INTRL2_0_TX_RING_FULL); +out_free_rx_ring: + bcm_sysport_fini_rx_ring(priv); +out_free_tx_ring: + for (i = 0; i < dev->num_tx_queues; i++) + bcm_sysport_fini_tx_ring(priv, i); + if (!priv->is_lite) + free_irq(priv->irq1, dev); +out_free_irq0: + free_irq(priv->irq0, dev); +out_phy_disconnect: + phy_disconnect(phydev); + return ret; +} + +static void bcm_sysport_netif_stop(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + + /* stop all software from updating hardware */ + netif_tx_disable(dev); + napi_disable(&priv->napi); + phy_stop(dev->phydev); + + /* mask all interrupts */ + bcm_sysport_mask_all_intrs(priv); +} + +static int bcm_sysport_stop(struct net_device *dev) +{ + struct bcm_sysport_priv *priv = netdev_priv(dev); + unsigned int i; + int ret; + + bcm_sysport_netif_stop(dev); + + /* Disable UniMAC RX */ + umac_enable_set(priv, CMD_RX_EN, 0); + + ret = tdma_enable_set(priv, 0); + if (ret) { + netdev_err(dev, "timeout disabling RDMA\n"); + return ret; + } + + /* Wait for a maximum packet size to be drained */ + usleep_range(2000, 3000); + + ret = rdma_enable_set(priv, 0); + if (ret) { + netdev_err(dev, "timeout disabling TDMA\n"); + return ret; + } + + /* Disable UniMAC TX */ + umac_enable_set(priv, CMD_TX_EN, 0); + + /* Free RX/TX rings SW structures */ + for (i = 0; i < dev->num_tx_queues; i++) + bcm_sysport_fini_tx_ring(priv, i); + bcm_sysport_fini_rx_ring(priv); + + free_irq(priv->irq0, dev); + if (!priv->is_lite) + free_irq(priv->irq1, dev); + + /* Disconnect from PHY */ + phy_disconnect(dev->phydev); + + return 0; +} + +static const struct ethtool_ops bcm_sysport_ethtool_ops = { + .get_drvinfo = bcm_sysport_get_drvinfo, + .get_msglevel = bcm_sysport_get_msglvl, + .set_msglevel = bcm_sysport_set_msglvl, + .get_link = ethtool_op_get_link, + .get_strings = bcm_sysport_get_strings, + .get_ethtool_stats = bcm_sysport_get_stats, + .get_sset_count = bcm_sysport_get_sset_count, + .get_wol = bcm_sysport_get_wol, + .set_wol = bcm_sysport_set_wol, + .get_coalesce = bcm_sysport_get_coalesce, + .set_coalesce = bcm_sysport_set_coalesce, + .get_link_ksettings = phy_ethtool_get_link_ksettings, + .set_link_ksettings = phy_ethtool_set_link_ksettings, +}; + +static const struct net_device_ops bcm_sysport_netdev_ops = { + .ndo_start_xmit = bcm_sysport_xmit, + .ndo_tx_timeout = bcm_sysport_tx_timeout, + .ndo_open = bcm_sysport_open, + .ndo_stop = bcm_sysport_stop, + .ndo_set_features = bcm_sysport_set_features, + .ndo_set_rx_mode = bcm_sysport_set_rx_mode, + .ndo_set_mac_address = bcm_sysport_change_mac, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = bcm_sysport_poll_controller, +#endif + .ndo_get_stats64 = bcm_sysport_get_stats64, +}; + +#define REV_FMT "v%2x.%02x" + +static const struct bcm_sysport_hw_params bcm_sysport_params[] = { + [SYSTEMPORT_63158] = { + .num_rx_desc_words = SP_NUM_HW_RX_DESC_WORDS, + }, +}; + +static const struct of_device_id bcm_sysport_of_match[] = { + { .compatible = "brcm,systemport-63158", + .data = &bcm_sysport_params[SYSTEMPORT_63158] }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, bcm_sysport_of_match); + +static int bcm_sysport_probe(struct platform_device *pdev) +{ + const struct bcm_sysport_hw_params *params; + const struct of_device_id *of_id = NULL; + struct bcm_sysport_priv *priv; + struct device_node *dn; + struct net_device *dev; + const void *macaddr; + struct resource *r; + u32 txq, rxq; + int ret; + + dn = pdev->dev.of_node; + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + of_id = of_match_node(bcm_sysport_of_match, dn); + if (!of_id || !of_id->data) + return -EINVAL; + + /* Fairly quickly we need to know the type of adapter we have */ + params = of_id->data; + + /* Read the Transmit/Receive Queue properties */ + if (of_property_read_u32(dn, "systemport,num-txq", &txq)) + txq = TDMA_ACTUAL_NUM_RINGS; + if (of_property_read_u32(dn, "systemport,num-rxq", &rxq)) + rxq = 1; + + /* Sanity check the number of transmit queues */ + if (!txq || txq > TDMA_NUM_RINGS) + return -EINVAL; + + dev = alloc_etherdev_mqs(sizeof(*priv), txq, rxq); + if (!dev) + return -ENOMEM; + + /* Initialize private members */ + priv = netdev_priv(dev); + + /* Allocate number of TX rings */ + priv->tx_rings = devm_kcalloc(&pdev->dev, txq, + sizeof(struct bcm_sysport_tx_ring), + GFP_KERNEL); + if (!priv->tx_rings) + return -ENOMEM; + + priv->is_lite = params->is_lite; + priv->num_rx_desc_words = params->num_rx_desc_words; + + priv->irq0 = platform_get_irq(pdev, 0); + if (!priv->is_lite) { + priv->irq1 = platform_get_irq(pdev, 1); + priv->wol_irq = platform_get_irq(pdev, 2); + } else { + priv->wol_irq = platform_get_irq(pdev, 1); + } + if (priv->irq0 <= 0 || (priv->irq1 <= 0 && !priv->is_lite)) { + dev_err(&pdev->dev, "invalid interrupts\n"); + ret = -EINVAL; + goto err_free_netdev; + } + + priv->base = devm_ioremap_resource(&pdev->dev, r); + if (IS_ERR(priv->base)) { + ret = PTR_ERR(priv->base); + goto err_free_netdev; + } + + priv->netdev = dev; + priv->pdev = pdev; + + priv->phy_interface = of_get_phy_mode(dn); + /* Default to GMII interface mode */ + if (priv->phy_interface < 0) + priv->phy_interface = PHY_INTERFACE_MODE_GMII; + + /* In the case of a fixed PHY, the DT node associated + * to the PHY is the Ethernet MAC DT node. + */ + if (of_phy_is_fixed_link(dn)) { + ret = of_phy_register_fixed_link(dn); + if (ret) { + dev_err(&pdev->dev, "failed to register fixed PHY\n"); + goto err_free_netdev; + } + + priv->phy_dn = dn; + } + + /* Initialize netdevice members */ + macaddr = of_get_mac_address(dn); + if (!macaddr || !is_valid_ether_addr(macaddr)) { + dev_warn(&pdev->dev, "using random Ethernet MAC\n"); + eth_hw_addr_random(dev); + } else { + ether_addr_copy(dev->dev_addr, macaddr); + } + + SET_NETDEV_DEV(dev, &pdev->dev); + dev_set_drvdata(&pdev->dev, dev); + dev->ethtool_ops = &bcm_sysport_ethtool_ops; + dev->netdev_ops = &bcm_sysport_netdev_ops; + netif_napi_add(dev, &priv->napi, bcm_sysport_poll, 64); + + /* HW supported features, none enabled by default */ + dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_HIGHDMA | + NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; + + /* Request the WOL interrupt and advertise suspend if available */ + priv->wol_irq_disabled = 1; + ret = devm_request_irq(&pdev->dev, priv->wol_irq, + bcm_sysport_wol_isr, 0, dev->name, priv); + if (!ret) + device_set_wakeup_capable(&pdev->dev, 1); + + /* Set the needed headroom once and for all */ + BUILD_BUG_ON(sizeof(struct bcm_tsb) != 8); + dev->needed_headroom += sizeof(struct bcm_tsb); + + /* libphy will adjust the link state accordingly */ + netif_carrier_off(dev); + + u64_stats_init(&priv->syncp); + + ret = register_netdev(dev); + if (ret) { + dev_err(&pdev->dev, "failed to register net_device\n"); + goto err_deregister_fixed_link; + } + + priv->rev = topctrl_readl(priv, REV_CNTL) & REV_MASK; + dev_info(&pdev->dev, + "Broadcom SYSTEMPORT%s" REV_FMT + " at 0x%p (irqs: %d, %d, TXQs: %d, RXQs: %d)\n", + priv->is_lite ? " Lite" : "", + (priv->rev >> 8) & 0xff, priv->rev & 0xff, + priv->base, priv->irq0, priv->irq1, txq, rxq); + + return 0; + +err_deregister_fixed_link: + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); +err_free_netdev: + free_netdev(dev); + return ret; +} + +static int bcm_sysport_remove(struct platform_device *pdev) +{ + struct net_device *dev = dev_get_drvdata(&pdev->dev); + struct device_node *dn = pdev->dev.of_node; + + /* Not much to do, ndo_close has been called + * and we use managed allocations + */ + unregister_netdev(dev); + if (of_phy_is_fixed_link(dn)) + of_phy_deregister_fixed_link(dn); + free_netdev(dev); + dev_set_drvdata(&pdev->dev, NULL); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int bcm_sysport_suspend_to_wol(struct bcm_sysport_priv *priv) +{ + struct net_device *ndev = priv->netdev; + unsigned int timeout = 1000; + u32 reg; + + /* Password has already been programmed */ + reg = umac_readl(priv, UMAC_MPD_CTRL); + reg |= MPD_EN; + reg &= ~PSW_EN; + if (priv->wolopts & WAKE_MAGICSECURE) + reg |= PSW_EN; + umac_writel(priv, reg, UMAC_MPD_CTRL); + + /* Make sure RBUF entered WoL mode as result */ + do { + reg = rbuf_readl(priv, RBUF_STATUS); + if (reg & RBUF_WOL_MODE) + break; + + udelay(10); + } while (timeout-- > 0); + + /* Do not leave the UniMAC RBUF matching only MPD packets */ + if (!timeout) { + reg = umac_readl(priv, UMAC_MPD_CTRL); + reg &= ~MPD_EN; + umac_writel(priv, reg, UMAC_MPD_CTRL); + netif_err(priv, wol, ndev, "failed to enter WOL mode\n"); + return -ETIMEDOUT; + } + + /* UniMAC receive needs to be turned on */ + umac_enable_set(priv, CMD_RX_EN, 1); + + netif_dbg(priv, wol, ndev, "entered WOL mode\n"); + + return 0; +} + +static int bcm_sysport_suspend(struct device *d) +{ + struct net_device *dev = dev_get_drvdata(d); + struct bcm_sysport_priv *priv = netdev_priv(dev); + unsigned int i; + int ret = 0; + u32 reg; + + if (!netif_running(dev)) + return 0; + + netif_device_detach(dev); + + bcm_sysport_netif_stop(dev); + + phy_suspend(dev->phydev); + + /* Disable UniMAC RX */ + umac_enable_set(priv, CMD_RX_EN, 0); + + ret = rdma_enable_set(priv, 0); + if (ret) { + netdev_err(dev, "RDMA timeout!\n"); + return ret; + } + + /* Disable RXCHK if enabled */ + if (priv->rx_chk_en) { + reg = rxchk_readl(priv, RXCHK_CONTROL); + reg &= ~RXCHK_EN; + rxchk_writel(priv, reg, RXCHK_CONTROL); + } + + /* Flush RX pipe */ + if (!priv->wolopts) + topctrl_writel(priv, RX_FLUSH, RX_FLUSH_CNTL); + + ret = tdma_enable_set(priv, 0); + if (ret) { + netdev_err(dev, "TDMA timeout!\n"); + return ret; + } + + /* Wait for a packet boundary */ + usleep_range(2000, 3000); + + umac_enable_set(priv, CMD_TX_EN, 0); + + topctrl_writel(priv, TX_FLUSH, TX_FLUSH_CNTL); + + /* Free RX/TX rings SW structures */ + for (i = 0; i < dev->num_tx_queues; i++) + bcm_sysport_fini_tx_ring(priv, i); + bcm_sysport_fini_rx_ring(priv); + + /* Get prepared for Wake-on-LAN */ + if (device_may_wakeup(d) && priv->wolopts) + ret = bcm_sysport_suspend_to_wol(priv); + + return ret; +} + +static int bcm_sysport_resume(struct device *d) +{ + struct net_device *dev = dev_get_drvdata(d); + struct bcm_sysport_priv *priv = netdev_priv(dev); + unsigned int i; + u32 reg; + int ret; + + if (!netif_running(dev)) + return 0; + + umac_reset(priv); + + /* We may have been suspended and never received a WOL event that + * would turn off MPD detection, take care of that now + */ + bcm_sysport_resume_from_wol(priv); + + /* Initialize both hardware and software ring */ + for (i = 0; i < dev->num_tx_queues; i++) { + ret = bcm_sysport_init_tx_ring(priv, i); + if (ret) { + netdev_err(dev, "failed to initialize TX ring %d\n", + i); + goto out_free_tx_rings; + } + } + + /* Initialize linked-list */ + tdma_writel(priv, TDMA_LL_RAM_INIT_BUSY, TDMA_STATUS); + + /* Initialize RX ring */ + ret = bcm_sysport_init_rx_ring(priv); + if (ret) { + netdev_err(dev, "failed to initialize RX ring\n"); + goto out_free_rx_ring; + } + + /* RX pipe enable */ + topctrl_writel(priv, 0, RX_FLUSH_CNTL); + + ret = rdma_enable_set(priv, 1); + if (ret) { + netdev_err(dev, "failed to enable RDMA\n"); + goto out_free_rx_ring; + } + + /* Enable rxhck */ + if (priv->rx_chk_en) { + reg = rxchk_readl(priv, RXCHK_CONTROL); + reg |= RXCHK_EN; + rxchk_writel(priv, reg, RXCHK_CONTROL); + } + + rbuf_init(priv); + + /* Set maximum frame length */ + if (!priv->is_lite) + umac_writel(priv, UMAC_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); + else + gib_set_pad_extension(priv); + + /* Set MAC address */ + umac_set_hw_addr(priv, dev->dev_addr); + + umac_enable_set(priv, CMD_RX_EN, 1); + + /* TX pipe enable */ + topctrl_writel(priv, 0, TX_FLUSH_CNTL); + + umac_enable_set(priv, CMD_TX_EN, 1); + + ret = tdma_enable_set(priv, 1); + if (ret) { + netdev_err(dev, "TDMA timeout!\n"); + goto out_free_rx_ring; + } + + phy_resume(dev->phydev); + + bcm_sysport_netif_start(dev); + + netif_device_attach(dev); + + return 0; + +out_free_rx_ring: + bcm_sysport_fini_rx_ring(priv); +out_free_tx_rings: + for (i = 0; i < dev->num_tx_queues; i++) + bcm_sysport_fini_tx_ring(priv, i); + return ret; +} +#endif + +static SIMPLE_DEV_PM_OPS(bcm_sysport_pm_ops, + bcm_sysport_suspend, bcm_sysport_resume); + +static struct platform_driver bcm_sysport_63158_driver = { + .probe = bcm_sysport_probe, + .remove = bcm_sysport_remove, + .driver = { + .name = "brcm-systemport", + .of_match_table = bcm_sysport_of_match, + .pm = &bcm_sysport_pm_ops, + }, +}; +module_platform_driver(bcm_sysport_63158_driver); + +MODULE_AUTHOR("Broadcom Corporation"); +MODULE_DESCRIPTION("Broadcom System Port Ethernet MAC driver"); +MODULE_ALIAS("platform:brcm-systemport-63158"); +MODULE_LICENSE("GPL"); diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./bcmsysport_63158.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/bcmsysport_63158.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./bcmsysport_63158.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/bcmsysport_63158.h 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,759 @@ +/* + * Broadcom BCM7xxx System Port Ethernet MAC driver + * + * Copyright (C) 2014 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __BCM_SYSPORT_H +#define __BCM_SYSPORT_H + +#include + +/* Receive/transmit descriptor format */ +#define DESC_ADDR_LO 0x00 + +#define DESC_ADDR_HI_STATUS_LEN 0x04 +#define DESC_ADDR_HI_SHIFT 0 +#define DESC_ADDR_HI_MASK 0xff +#define DESC_STATUS_SHIFT 8 +#define DESC_STATUS_MASK 0x3ff +#define DESC_LEN_SHIFT 18 +#define DESC_LEN_MASK 0x7fff + +/* HW supports 40-bit addressing hence the */ +#define DESC_SIZE (WORDS_PER_DESC * sizeof(u32)) + +/* Default RX buffer allocation size */ +#define RX_BUF_LENGTH 2048 + +/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(4) + FCS(4) = 1526. + * 1536 is multiple of 256 bytes + */ +#define ENET_BRCM_TAG_LEN 4 +#define ENET_PAD 10 +#define UMAC_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ + ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) + +/* Transmit status block */ +struct bcm_tsb { + u32 pcp_dei_vid; +#define PCP_DEI_MASK 0xf +#define VID_SHIFT 4 +#define VID_MASK 0xfff + u32 l4_ptr_dest_map; +#define L4_CSUM_PTR_MASK 0x1ff +#define L4_PTR_SHIFT 9 +#define L4_PTR_MASK 0x1ff +#define L4_UDP (1 << 18) +#define L4_LENGTH_VALID (1 << 19) +#define DEST_MAP_SHIFT 20 +#define DEST_MAP_MASK 0x1ff +}; + +/* Receive status block uses the same + * definitions as the DMA descriptor + */ +struct bcm_rsb { + u32 rx_status_len; + u32 brcm_egress_tag; +}; + +/* Common Receive/Transmit status bits */ +#define DESC_L4_CSUM (1 << 7) +#define DESC_SOP (1 << 8) +#define DESC_EOP (1 << 9) + +/* Receive Status bits */ +#define RX_STATUS_UCAST 0 +#define RX_STATUS_BCAST 0x04 +#define RX_STATUS_MCAST 0x08 +#define RX_STATUS_L2_MCAST 0x0c +#define RX_STATUS_ERR (1 << 4) +#define RX_STATUS_OVFLOW (1 << 5) +#define RX_STATUS_PARSE_FAIL (1 << 6) + +/* Transmit Status bits */ +#define TX_STATUS_VLAN_NO_ACT 0x00 +#define TX_STATUS_VLAN_PCP_TSB 0x01 +#define TX_STATUS_VLAN_QUEUE 0x02 +#define TX_STATUS_VLAN_VID_TSB 0x03 +#define TX_STATUS_OWR_CRC (1 << 2) +#define TX_STATUS_APP_CRC (1 << 3) +#define TX_STATUS_BRCM_TAG_NO_ACT 0 +#define TX_STATUS_BRCM_TAG_ZERO 0x10 +#define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20 +#define TX_STATUS_BRCM_TAG_ONE_TSB 0x30 +#define TX_STATUS_SKIP_BYTES (1 << 6) + +/* Specific register definitions */ +#define SYS_PORT_TOPCTRL_OFFSET 0 +#define REV_CNTL 0x00 +#define REV_MASK 0xffff + +#define RX_FLUSH_CNTL 0x04 +#define RX_FLUSH (1 << 0) + +#define TX_FLUSH_CNTL 0x08 +#define TX_FLUSH (1 << 0) + +#define MISC_CNTL 0x0c +#define SYS_CLK_SEL (1 << 0) +#define TDMA_EOP_SEL (1 << 1) + +/* Level-2 Interrupt controller offsets and defines */ +#define SYS_PORT_INTRL2_0_OFFSET 0x200 +#define SYS_PORT_INTRL2_1_OFFSET 0x240 +#define INTRL2_CPU_STATUS 0x00 +#define INTRL2_CPU_SET 0x04 +#define INTRL2_CPU_CLEAR 0x08 +#define INTRL2_CPU_MASK_STATUS 0x0c +#define INTRL2_CPU_MASK_SET 0x10 +#define INTRL2_CPU_MASK_CLEAR 0x14 + +/* Level-2 instance 0 interrupt bits */ +#define INTRL2_0_GISB_ERR (1 << 0) +#define INTRL2_0_RBUF_OVFLOW (1 << 1) +#define INTRL2_0_TBUF_UNDFLOW (1 << 2) +#define INTRL2_0_MPD (1 << 3) +#define INTRL2_0_BRCM_MATCH_TAG (1 << 4) +#define INTRL2_0_RDMA_MBDONE (1 << 5) +#define INTRL2_0_OVER_MAX_THRESH (1 << 6) +#define INTRL2_0_BELOW_HYST_THRESH (1 << 7) +#define INTRL2_0_FREE_LIST_EMPTY (1 << 8) +#define INTRL2_0_TX_RING_FULL (1 << 9) +#define INTRL2_0_DESC_ALLOC_ERR (1 << 10) +#define INTRL2_0_UNEXP_PKTSIZE_ACK (1 << 11) + +/* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */ +#define INTRL2_0_TDMA_MBDONE_SHIFT 12 +#define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT) + +/* RXCHK offset and defines */ +#define SYS_PORT_RXCHK_OFFSET 0x300 + +#define RXCHK_CONTROL 0x00 +#define RXCHK_EN (1 << 0) +#define RXCHK_SKIP_FCS (1 << 1) +#define RXCHK_BAD_CSUM_DIS (1 << 2) +#define RXCHK_BRCM_TAG_EN (1 << 3) +#define RXCHK_BRCM_TAG_MATCH_SHIFT 4 +#define RXCHK_BRCM_TAG_MATCH_MASK 0xff +#define RXCHK_PARSE_TNL (1 << 12) +#define RXCHK_VIOL_EN (1 << 13) +#define RXCHK_VIOL_DIS (1 << 14) +#define RXCHK_INCOM_PKT (1 << 15) +#define RXCHK_V6_DUPEXT_EN (1 << 16) +#define RXCHK_V6_DUPEXT_DIS (1 << 17) +#define RXCHK_ETHERTYPE_DIS (1 << 18) +#define RXCHK_L2_HDR_DIS (1 << 19) +#define RXCHK_L3_HDR_DIS (1 << 20) +#define RXCHK_MAC_RX_ERR_DIS (1 << 21) +#define RXCHK_PARSE_AUTH (1 << 22) + +#define RXCHK_BRCM_TAG0 0x04 +#define RXCHK_BRCM_TAG(i) ((i) * RXCHK_BRCM_TAG0) +#define RXCHK_BRCM_TAG0_MASK 0x24 +#define RXCHK_BRCM_TAG_MASK(i) ((i) * RXCHK_BRCM_TAG0_MASK) +#define RXCHK_BRCM_TAG_MATCH_STATUS 0x44 +#define RXCHK_ETHERTYPE 0x48 +#define RXCHK_BAD_CSUM_CNTR 0x4C +#define RXCHK_OTHER_DISC_CNTR 0x50 + +/* TXCHCK offsets and defines */ +#define SYS_PORT_TXCHK_OFFSET 0x380 +#define TXCHK_PKT_RDY_THRESH 0x00 + +/* Receive buffer offset and defines */ +#define SYS_PORT_RBUF_OFFSET 0x400 + +#define RBUF_CONTROL 0x00 +#define RBUF_RSB_EN (1 << 0) +#define RBUF_4B_ALGN (1 << 1) +#define RBUF_BRCM_TAG_STRIP (1 << 2) +#define RBUF_BAD_PKT_DISC (1 << 3) +#define RBUF_RESUME_THRESH_SHIFT 4 +#define RBUF_RESUME_THRESH_MASK 0xff +#define RBUF_OK_TO_SEND_SHIFT 12 +#define RBUF_OK_TO_SEND_MASK 0xff +#define RBUF_CRC_REPLACE (1 << 20) +#define RBUF_OK_TO_SEND_MODE (1 << 21) +/* SYSTEMPORT Lite uses two bits here */ +#define RBUF_RSB_SWAP0 (1 << 22) +#define RBUF_RSB_SWAP1 (1 << 23) +#define RBUF_ACPI_EN (1 << 23) + +#define RBUF_PKT_RDY_THRESH 0x04 + +#define RBUF_STATUS 0x08 +#define RBUF_WOL_MODE (1 << 0) +#define RBUF_MPD (1 << 1) +#define RBUF_ACPI (1 << 2) + +#define RBUF_OVFL_DISC_CNTR 0x0c +#define RBUF_ERR_PKT_CNTR 0x10 + +/* Transmit buffer offset and defines */ +#define SYS_PORT_TBUF_OFFSET 0x600 + +#define TBUF_CONTROL 0x00 +#define TBUF_BP_EN (1 << 0) +#define TBUF_MAX_PKT_THRESH_SHIFT 1 +#define TBUF_MAX_PKT_THRESH_MASK 0x1f +#define TBUF_FULL_THRESH_SHIFT 8 +#define TBUF_FULL_THRESH_MASK 0x1f + +/* UniMAC offset and defines */ +#define SYS_PORT_UMAC_OFFSET 0x800 + +#define UMAC_CMD 0x008 +#define CMD_TX_EN (1 << 0) +#define CMD_RX_EN (1 << 1) +#define CMD_SPEED_SHIFT 2 +#define CMD_SPEED_10 0 +#define CMD_SPEED_100 1 +#define CMD_SPEED_1000 2 +#define CMD_SPEED_2500 3 +#define CMD_SPEED_MASK 3 +#define CMD_PROMISC (1 << 4) +#define CMD_PAD_EN (1 << 5) +#define CMD_CRC_FWD (1 << 6) +#define CMD_PAUSE_FWD (1 << 7) +#define CMD_RX_PAUSE_IGNORE (1 << 8) +#define CMD_TX_ADDR_INS (1 << 9) +#define CMD_HD_EN (1 << 10) +#define CMD_SW_RESET (1 << 13) +#define CMD_LCL_LOOP_EN (1 << 15) +#define CMD_AUTO_CONFIG (1 << 22) +#define CMD_CNTL_FRM_EN (1 << 23) +#define CMD_NO_LEN_CHK (1 << 24) +#define CMD_RMT_LOOP_EN (1 << 25) +#define CMD_PRBL_EN (1 << 27) +#define CMD_TX_PAUSE_IGNORE (1 << 28) +#define CMD_TX_RX_EN (1 << 29) +#define CMD_RUNT_FILTER_DIS (1 << 30) + +#define UMAC_MAC0 0x00c +#define UMAC_MAC1 0x010 +#define UMAC_MAX_FRAME_LEN 0x014 + +#define UMAC_TX_FLUSH 0x334 + +#define UMAC_MIB_START 0x400 + +/* There is a 0xC gap between the end of RX and beginning of TX stats and then + * between the end of TX stats and the beginning of the RX RUNT + */ +#define UMAC_MIB_STAT_OFFSET 0xc + +#define UMAC_MIB_CTRL 0x580 +#define MIB_RX_CNT_RST (1 << 0) +#define MIB_RUNT_CNT_RST (1 << 1) +#define MIB_TX_CNT_RST (1 << 2) + +/* These offsets are valid for SYSTEMPORT and SYSTEMPORT Lite */ +#define UMAC_MPD_CTRL 0x620 +#define MPD_EN (1 << 0) +#define MSEQ_LEN_SHIFT 16 +#define MSEQ_LEN_MASK 0xff +#define PSW_EN (1 << 27) + +#define UMAC_PSW_MS 0x624 +#define UMAC_PSW_LS 0x628 +#define UMAC_MDF_CTRL 0x650 +#define UMAC_MDF_ADDR 0x654 + +/* Only valid on SYSTEMPORT Lite */ +#define SYS_PORT_GIB_OFFSET 0x1000 + +#define GIB_CONTROL 0x00 +#define GIB_TX_EN (1 << 0) +#define GIB_RX_EN (1 << 1) +#define GIB_TX_FLUSH (1 << 2) +#define GIB_RX_FLUSH (1 << 3) +#define GIB_GTX_CLK_SEL_SHIFT 4 +#define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT) +#define GIB_GTX_CLK_125MHZ (1 << GIB_GTX_CLK_SEL_SHIFT) +#define GIB_GTX_CLK_250MHZ (2 << GIB_GTX_CLK_SEL_SHIFT) +#define GIB_FCS_STRIP_SHIFT 6 +#define GIB_FCS_STRIP (1 << GIB_FCS_STRIP_SHIFT) +#define GIB_LCL_LOOP_EN (1 << 7) +#define GIB_LCL_LOOP_TXEN (1 << 8) +#define GIB_RMT_LOOP_EN (1 << 9) +#define GIB_RMT_LOOP_RXEN (1 << 10) +#define GIB_RX_PAUSE_EN (1 << 11) +#define GIB_PREAMBLE_LEN_SHIFT 12 +#define GIB_PREAMBLE_LEN_MASK 0xf +#define GIB_IPG_LEN_SHIFT 16 +#define GIB_IPG_LEN_MASK 0x3f +#define GIB_PAD_EXTENSION_SHIFT 22 +#define GIB_PAD_EXTENSION_MASK 0x3f + +#define GIB_MAC1 0x08 +#define GIB_MAC0 0x0c + +/* Receive DMA offset and defines */ +#define SYS_PORT_RDMA_OFFSET 0x2000 + +#define RDMA_CONTROL 0x1000 +#define RDMA_EN (1 << 0) +#define RDMA_RING_CFG (1 << 1) +#define RDMA_DISC_EN (1 << 2) +#define RDMA_BUF_DATA_OFFSET_SHIFT 4 +#define RDMA_BUF_DATA_OFFSET_MASK 0x3ff + +#define RDMA_STATUS 0x1004 +#define RDMA_DISABLED (1 << 0) +#define RDMA_DESC_RAM_INIT_BUSY (1 << 1) +#define RDMA_BP_STATUS (1 << 2) + +#define RDMA_SCB_BURST_SIZE 0x1008 + +#define RDMA_RING_BUF_SIZE 0x100c +#define RDMA_RING_SIZE_SHIFT 16 + +#define RDMA_WRITE_PTR_HI 0x1010 +#define RDMA_WRITE_PTR_LO 0x1014 +#define RDMA_PROD_INDEX 0x1018 +#define RDMA_PROD_INDEX_MASK 0xffff + +#define RDMA_CONS_INDEX 0x101c +#define RDMA_CONS_INDEX_MASK 0xffff + +#define RDMA_START_ADDR_LO 0x1020 +#define RDMA_START_ADDR_HI 0x1024 + +#define RDMA_MBDONE_INTR 0x1028 +#define RDMA_INTR_THRESH_MASK 0x1ff +#define RDMA_TIMEOUT_SHIFT 16 +#define RDMA_TIMEOUT_MASK 0xffff + +#define RDMA_XON_XOFF_THRESH 0x102c +#define RDMA_XON_XOFF_THRESH_MASK 0xffff +#define RDMA_XOFF_THRESH_SHIFT 16 + +#define RDMA_READ_PTR_LO 0x1030 +#define RDMA_READ_PTR_HI 0x1034 + +#define RDMA_DEBUG 0x1048 + +/* Transmit DMA offset and defines */ +#define TDMA_ACTUAL_NUM_RINGS 16 /* rings = queues */ +#define TDMA_NUM_RINGS 32 /* rings = queues */ +#define TDMA_PORT_SIZE DESC_SIZE /* two 32-bits words */ + +#define SYS_PORT_TDMA_OFFSET 0x4000 +#define TDMA_WRITE_PORT_OFFSET 0x0000 +#define TDMA_WRITE_PORT_HI(i) (TDMA_WRITE_PORT_OFFSET + \ + (i) * TDMA_PORT_SIZE) +#define TDMA_WRITE_PORT_LO(i) (TDMA_WRITE_PORT_OFFSET + \ + sizeof(u32) + (i) * TDMA_PORT_SIZE) + +#define TDMA_READ_PORT_OFFSET (TDMA_WRITE_PORT_OFFSET + \ + (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) +#define TDMA_READ_PORT_HI(i) (TDMA_READ_PORT_OFFSET + \ + (i) * TDMA_PORT_SIZE) +#define TDMA_READ_PORT_LO(i) (TDMA_READ_PORT_OFFSET + \ + sizeof(u32) + (i) * TDMA_PORT_SIZE) + +#define TDMA_READ_PORT_CMD_OFFSET (TDMA_READ_PORT_OFFSET + \ + (TDMA_NUM_RINGS * TDMA_PORT_SIZE)) +#define TDMA_READ_PORT_CMD(i) (TDMA_READ_PORT_CMD_OFFSET + \ + (i) * sizeof(u32)) + +#define TDMA_DESC_RING_00_BASE (TDMA_READ_PORT_CMD_OFFSET + \ + (TDMA_NUM_RINGS * sizeof(u32))) + +/* Register offsets and defines relatives to a specific ring number */ +#define RING_HEAD_TAIL_PTR 0x00 +#define RING_HEAD_MASK 0x7ff +#define RING_TAIL_SHIFT 11 +#define RING_TAIL_MASK 0x7ff +#define RING_FLUSH (1 << 24) +#define RING_EN (1 << 25) + +#define RING_COUNT 0x04 +#define RING_COUNT_MASK 0x7ff +#define RING_BUFF_DONE_SHIFT 11 +#define RING_BUFF_DONE_MASK 0x7ff + +#define RING_MAX_HYST 0x08 +#define RING_MAX_THRESH_MASK 0x7ff +#define RING_HYST_THRESH_SHIFT 11 +#define RING_HYST_THRESH_MASK 0x7ff + +#define RING_INTR_CONTROL 0x0c +#define RING_INTR_THRESH_MASK 0x7ff +#define RING_EMPTY_INTR_EN (1 << 15) +#define RING_TIMEOUT_SHIFT 16 +#define RING_TIMEOUT_MASK 0xffff + +#define RING_PROD_CONS_INDEX 0x10 +#define RING_PROD_INDEX_MASK 0xffff +#define RING_CONS_INDEX_SHIFT 16 +#define RING_CONS_INDEX_MASK 0xffff + +#define RING_MAPPING 0x14 +#define RING_QID_MASK 0x3 +#define RING_PORT_ID_SHIFT 3 +#define RING_PORT_ID_MASK 0x7 +#define RING_IGNORE_STATUS (1 << 6) +#define RING_FAILOVER_EN (1 << 7) +#define RING_CREDIT_SHIFT 8 +#define RING_CREDIT_MASK 0xffff + +#define RING_PCP_DEI_VID 0x18 +#define RING_VID_MASK 0x7ff +#define RING_DEI (1 << 12) +#define RING_PCP_SHIFT 13 +#define RING_PCP_MASK 0x7 +#define RING_PKT_SIZE_ADJ_SHIFT 16 +#define RING_PKT_SIZE_ADJ_MASK 0xf + +#define TDMA_DESC_RING_SIZE 48 + +/* Defininition for a given TX ring base address */ +#define TDMA_DESC_RING_BASE(i) (TDMA_DESC_RING_00_BASE + \ + ((i) * TDMA_DESC_RING_SIZE)) + +/* Ring indexed register addreses */ +#define TDMA_DESC_RING_HEAD_TAIL_PTR(i) (TDMA_DESC_RING_BASE(i) + \ + RING_HEAD_TAIL_PTR) +#define TDMA_DESC_RING_COUNT(i) (TDMA_DESC_RING_BASE(i) + \ + RING_COUNT) +#define TDMA_DESC_RING_MAX_HYST(i) (TDMA_DESC_RING_BASE(i) + \ + RING_MAX_HYST) +#define TDMA_DESC_RING_INTR_CONTROL(i) (TDMA_DESC_RING_BASE(i) + \ + RING_INTR_CONTROL) +#define TDMA_DESC_RING_PROD_CONS_INDEX(i) \ + (TDMA_DESC_RING_BASE(i) + \ + RING_PROD_CONS_INDEX) +#define TDMA_DESC_RING_MAPPING(i) (TDMA_DESC_RING_BASE(i) + \ + RING_MAPPING) +#define TDMA_DESC_RING_PCP_DEI_VID(i) (TDMA_DESC_RING_BASE(i) + \ + RING_PCP_DEI_VID) + +#define TDMA_CONTROL 0x600 +#define TDMA_EN 0 +#define TSB_EN 1 +/* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we + * keep the SYSTEMPORT layout here and adjust with tdma_control_bit() + */ +#define TSB_SWAP0 2 +#define TSB_SWAP1 3 +#define ACB_ALGO 3 +#define BUF_DATA_OFFSET_SHIFT 4 +#define BUF_DATA_OFFSET_MASK 0x3ff +#define VLAN_EN 14 +#define SW_BRCM_TAG 15 +#define WNC_KPT_SIZE_UPDATE 16 +#define SYNC_PKT_SIZE 17 +#define ACH_TXDONE_DELAY_SHIFT 18 +#define ACH_TXDONE_DELAY_MASK 0xff + +#define TDMA_STATUS 0x604 +#define TDMA_DISABLED (1 << 0) +#define TDMA_LL_RAM_INIT_BUSY (1 << 1) + +#define TDMA_SCB_BURST_SIZE 0x608 +#define TDMA_OVER_MAX_THRESH_STATUS 0x60c +#define TDMA_OVER_HYST_THRESH_STATUS 0x610 +#define TDMA_TPID 0x614 + +#define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618 +#define TDMA_FREE_HEAD_MASK 0x7ff +#define TDMA_FREE_TAIL_SHIFT 11 +#define TDMA_FREE_TAIL_MASK 0x7ff + +#define TDMA_FREE_LIST_COUNT 0x61c +#define TDMA_FREE_LIST_COUNT_MASK 0x7ff + +#define TDMA_TIER2_ARB_CTRL 0x620 +#define TDMA_ARB_MODE_RR 0 +#define TDMA_ARB_MODE_WEIGHT_RR 0x1 +#define TDMA_ARB_MODE_STRICT 0x2 +#define TDMA_ARB_MODE_DEFICIT_RR 0x3 +#define TDMA_CREDIT_SHIFT 4 +#define TDMA_CREDIT_MASK 0xffff + +#define TDMA_TIER1_ARB_0_CTRL 0x624 +#define TDMA_ARB_EN (1 << 0) + +#define TDMA_TIER1_ARB_0_QUEUE_EN 0x628 +#define TDMA_TIER1_ARB_1_CTRL 0x62c +#define TDMA_TIER1_ARB_1_QUEUE_EN 0x630 +#define TDMA_TIER1_ARB_2_CTRL 0x634 +#define TDMA_TIER1_ARB_2_QUEUE_EN 0x638 +#define TDMA_TIER1_ARB_3_CTRL 0x63c +#define TDMA_TIER1_ARB_3_QUEUE_EN 0x640 + +#define TDMA_SCB_ENDIAN_OVERRIDE 0x644 +#define TDMA_LE_MODE (1 << 0) +#define TDMA_REG_MODE (1 << 1) + +#define TDMA_TEST 0x648 +#define TDMA_TP_OUT_SEL (1 << 0) +#define TDMA_MEM_TM (1 << 1) + +#define TDMA_DEBUG 0x64c + +/* Transmit/Receive descriptor */ +struct dma_desc { + u32 addr_status_len; + u32 addr_lo; +}; + +/* Number of Receive hardware descriptor words */ +#define SP_NUM_HW_RX_DESC_WORDS 1024 +#define SP_LT_NUM_HW_RX_DESC_WORDS 256 + +/* Internal linked-list RAM size */ +#define SP_NUM_TX_DESC 1536 +#define SP_LT_NUM_TX_DESC 256 + +#define WORDS_PER_DESC (sizeof(struct dma_desc) / sizeof(u32)) + +/* Rx/Tx common counter group.*/ +struct bcm_sysport_pkt_counters { + u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ + u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ + u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ + u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ + u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ + u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ + u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ + u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ + u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ + u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ +}; + +/* RSV, Receive Status Vector */ +struct bcm_sysport_rx_counters { + struct bcm_sysport_pkt_counters pkt_cnt; + u32 pkt; /* RO (0x428) Received pkt count*/ + u32 bytes; /* RO Received byte count */ + u32 mca; /* RO # of Received multicast pkt */ + u32 bca; /* RO # of Receive broadcast pkt */ + u32 fcs; /* RO # of Received FCS error */ + u32 cf; /* RO # of Received control frame pkt*/ + u32 pf; /* RO # of Received pause frame pkt */ + u32 uo; /* RO # of unknown op code pkt */ + u32 aln; /* RO # of alignment error count */ + u32 flr; /* RO # of frame length out of range count */ + u32 cde; /* RO # of code error pkt */ + u32 fcr; /* RO # of carrier sense error pkt */ + u32 ovr; /* RO # of oversize pkt*/ + u32 jbr; /* RO # of jabber count */ + u32 mtue; /* RO # of MTU error pkt*/ + u32 pok; /* RO # of Received good pkt */ + u32 uc; /* RO # of unicast pkt */ + u32 ppp; /* RO # of PPP pkt */ + u32 rcrc; /* RO (0x470),# of CRC match pkt */ +}; + +/* TSV, Transmit Status Vector */ +struct bcm_sysport_tx_counters { + struct bcm_sysport_pkt_counters pkt_cnt; + u32 pkts; /* RO (0x4a8) Transmited pkt */ + u32 mca; /* RO # of xmited multicast pkt */ + u32 bca; /* RO # of xmited broadcast pkt */ + u32 pf; /* RO # of xmited pause frame count */ + u32 cf; /* RO # of xmited control frame count */ + u32 fcs; /* RO # of xmited FCS error count */ + u32 ovr; /* RO # of xmited oversize pkt */ + u32 drf; /* RO # of xmited deferral pkt */ + u32 edf; /* RO # of xmited Excessive deferral pkt*/ + u32 scl; /* RO # of xmited single collision pkt */ + u32 mcl; /* RO # of xmited multiple collision pkt*/ + u32 lcl; /* RO # of xmited late collision pkt */ + u32 ecl; /* RO # of xmited excessive collision pkt*/ + u32 frg; /* RO # of xmited fragments pkt*/ + u32 ncl; /* RO # of xmited total collision count */ + u32 jbr; /* RO # of xmited jabber count*/ + u32 bytes; /* RO # of xmited byte count */ + u32 pok; /* RO # of xmited good pkt */ + u32 uc; /* RO (0x4f0) # of xmited unicast pkt */ +}; + +struct bcm_sysport_mib { + struct bcm_sysport_rx_counters rx; + struct bcm_sysport_tx_counters tx; + u32 rx_runt_cnt; + u32 rx_runt_fcs; + u32 rx_runt_fcs_align; + u32 rx_runt_bytes; + u32 rxchk_bad_csum; + u32 rxchk_other_pkt_disc; + u32 rbuf_ovflow_cnt; + u32 rbuf_err_cnt; + u32 alloc_rx_buff_failed; + u32 rx_dma_failed; + u32 tx_dma_failed; +}; + +/* HW maintains a large list of counters */ +enum bcm_sysport_stat_type { + BCM_SYSPORT_STAT_NETDEV = -1, + BCM_SYSPORT_STAT_NETDEV64, + BCM_SYSPORT_STAT_MIB_RX, + BCM_SYSPORT_STAT_MIB_TX, + BCM_SYSPORT_STAT_RUNT, + BCM_SYSPORT_STAT_RXCHK, + BCM_SYSPORT_STAT_RBUF, + BCM_SYSPORT_STAT_SOFT, +}; + +/* Macros to help define ethtool statistics */ +#define STAT_NETDEV(m) { \ + .stat_string = __stringify(m), \ + .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ + .stat_offset = offsetof(struct net_device_stats, m), \ + .type = BCM_SYSPORT_STAT_NETDEV, \ +} + +#define STAT_NETDEV64(m) { \ + .stat_string = __stringify(m), \ + .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \ + .stat_offset = offsetof(struct bcm_sysport_stats64, m), \ + .type = BCM_SYSPORT_STAT_NETDEV64, \ +} + +#define STAT_MIB(str, m, _type) { \ + .stat_string = str, \ + .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ + .stat_offset = offsetof(struct bcm_sysport_priv, m), \ + .type = _type, \ +} + +#define STAT_MIB_RX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_RX) +#define STAT_MIB_TX(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_MIB_TX) +#define STAT_RUNT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_RUNT) +#define STAT_MIB_SOFT(str, m) STAT_MIB(str, m, BCM_SYSPORT_STAT_SOFT) + +#define STAT_RXCHK(str, m, ofs) { \ + .stat_string = str, \ + .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ + .stat_offset = offsetof(struct bcm_sysport_priv, m), \ + .type = BCM_SYSPORT_STAT_RXCHK, \ + .reg_offset = ofs, \ +} + +#define STAT_RBUF(str, m, ofs) { \ + .stat_string = str, \ + .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \ + .stat_offset = offsetof(struct bcm_sysport_priv, m), \ + .type = BCM_SYSPORT_STAT_RBUF, \ + .reg_offset = ofs, \ +} + +/* TX bytes and packets */ +#define NUM_SYSPORT_TXQ_STAT 2 + +struct bcm_sysport_stats { + char stat_string[ETH_GSTRING_LEN]; + int stat_sizeof; + int stat_offset; + enum bcm_sysport_stat_type type; + /* reg offset from UMAC base for misc counters */ + u16 reg_offset; +}; + +struct bcm_sysport_stats64 { + /* 64bit stats on 32bit/64bit Machine */ + u64 rx_packets; + u64 rx_bytes; + u64 tx_packets; + u64 tx_bytes; +}; + +/* Software house keeping helper structure */ +struct bcm_sysport_cb { + struct sk_buff *skb; /* SKB for RX packets */ + void __iomem *bd_addr; /* Buffer descriptor PHYS addr */ + + DEFINE_DMA_UNMAP_ADDR(dma_addr); + DEFINE_DMA_UNMAP_LEN(dma_len); +}; + +enum bcm_sysport_type { + SYSTEMPORT_63158 = 0, +}; + +struct bcm_sysport_hw_params { + bool is_lite; + unsigned int num_rx_desc_words; +}; + +/* Software view of the TX ring */ +struct bcm_sysport_tx_ring { + spinlock_t lock; /* Ring lock for tx reclaim/xmit */ + struct napi_struct napi; /* NAPI per tx queue */ + unsigned int index; /* Ring index */ + unsigned int size; /* Ring current size */ + unsigned int alloc_size; /* Ring one-time allocated size */ + unsigned int desc_count; /* Number of descriptors */ + unsigned int curr_desc; /* Current descriptor */ + unsigned int c_index; /* Last consumer index */ + unsigned int clean_index; /* Current clean index */ + struct bcm_sysport_cb *cbs; /* Transmit control blocks */ + struct bcm_sysport_priv *priv; /* private context backpointer */ + unsigned long packets; /* packets statistics */ + unsigned long bytes; /* bytes statistics */ +}; + +/* Driver private structure */ +struct bcm_sysport_priv { + void __iomem *base; + u32 irq0_stat; + u32 irq0_mask; + u32 irq1_stat; + u32 irq1_mask; + bool is_lite; + unsigned int num_rx_desc_words; + struct napi_struct napi ____cacheline_aligned; + struct net_device *netdev; + struct platform_device *pdev; + int irq0; + int irq1; + int wol_irq; + + /* Transmit rings */ + struct bcm_sysport_tx_ring *tx_rings; + + /* Receive queue */ + void __iomem *rx_bds; + struct bcm_sysport_cb *rx_cbs; + unsigned int num_rx_bds; + unsigned int rx_read_ptr; + unsigned int rx_c_index; + + /* PHY device */ + struct device_node *phy_dn; + phy_interface_t phy_interface; + int old_pause; + int old_link; + int old_duplex; + + /* Misc fields */ + unsigned int rx_chk_en:1; + unsigned int tsb_en:1; + unsigned int crc_fwd:1; + u16 rev; + u32 wolopts; + unsigned int wol_irq_disabled:1; + + /* MIB related fields */ + struct bcm_sysport_mib mib; + + /* Ethtool */ + u32 msg_enable; + + struct bcm_sysport_stats64 stats64; + + /* For atomic update generic 64bit value on 32bit Machine */ + struct u64_stats_sync syncp; +}; +#endif /* __BCM_SYSPORT_H */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/bcm63158_enet_runner.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/bcm63158_enet_runner.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/bcm63158_enet_runner.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/bcm63158_enet_runner.h 2021-04-21 09:44:50.968505152 +0200 @@ -0,0 +1,254 @@ +#ifndef BCM63158_ENET_RUNNER_H_ +#define BCM63158_ENET_RUNNER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "enet_fw_defs.h" + +#define BCM_ENET_RUNNER_MAX_RXQ 1 +#define BCM_ENET_RUNNER_MAX_TXQ 2 + +enum bcm_runner_port_type { + BCM_RUNNER_PORT_UNIMAC, + BCM_RUNNER_PORT_XPORT, +}; + +/* + * note: RDP has a maximum MTU hardcoded, prevent setting mac do a + * value higher than it has + */ +#define BCM_RUNNER_MAC_MAX_MTU 2048 + +/* + * ethtool private flags + */ +#define PRIV_FLAGS_FORCE_LBE_OE_BIT 0 +#define PRIV_FLAGS_FORCE_LBE_OE_VAL_BIT 1 +#define PRIV_FLAGS_ST_SYNC_OK_BIT 2 + +struct bcm_runner_ethtool_stat { + char stat_string[ETH_GSTRING_LEN]; + unsigned int size; + unsigned int offset; + unsigned int reg; + unsigned int type; +}; + +struct rx_queue { + int index; + unsigned int ring_size; + unsigned int rx_curr_desc; + unsigned int rx_desc_area_size; + + struct rx_desc *rx_desc_area; + dma_addr_t rx_desc_dma; + void **frags; +}; + +struct tx_queue_pdata { + /* keep SKB & len separated because if we + * transmit a clone, then len may change and + * during reclaim we must unmap using same len + * that was mapped */ + void *data; + unsigned int len; +}; + +struct tx_queue { + /* + * "hot" fields first + */ + spinlock_t tx_lock; + unsigned int ring_size; + unsigned int tx_cur_desc; + unsigned int tx_dirty_desc; + struct tx_desc *tx_desc_area; + struct tx_queue_pdata *tx_desc_pdata; + + int index; + unsigned int tx_desc_area_size; + dma_addr_t tx_desc_dma; + + uint8_t use_dsa:1; + uint8_t dsa_port:4; + uint8_t dsa_queue:3; + uint8_t dsa_imp_port:4; +}; + +/* + * per port/mode operations + */ +struct bcm_enet_runner_priv; + +struct bcm_enet_mode_ops { + const char *name; + + /* called *before* init */ + u32 (*get_bbh_id)(void *port_priv); + + /* called only before netdevice is registred or when netdevice + * is down */ + void *(*init)(void *port_priv, + const struct bcm_xrdp_enet_params *); + void (*release)(void *mode_priv); + + /* called on netdevice stop, after runner & netdev queue are + * stopped, no start() operation, first phylink_mac_config() + * calls act the start() operation */ + void (*stop)(void *mode_priv); + + /* set interface mtu */ + void (*mtu_set)(void *mode_priv, unsigned int size); + + /* check if sending this packet type is allowed */ + bool (*can_send)(void *mode_priv, unsigned int protocol); + + /* mib operation */ + const struct bcm_runner_ethtool_stat *mib_estat; + size_t mib_estat_count; + void (*mib_update)(void *mode_priv); + void *(*mib_get_data)(void *mode_priv); + + /* get/set private on netdevice */ + u32 (*get_priv_flags)(void *mode_priv); + int (*set_priv_flags)(void *mode_priv, u32 flags); + + /* ethtool epon params callback */ + int (*get_epon_param)(void *mode_priv, + struct ethtool_epon_param *); + int (*set_epon_param)(void *mode_priv, + const struct ethtool_epon_param *); + + /* + * phylink callback + */ + void (*phylink_validate)(void *mode_priv, + unsigned long *supported, + struct phylink_link_state *state); + + void (*phylink_mac_config)(void *mode_priv, + unsigned int pl_mode, + const struct phylink_link_state *); + void (*phylink_link_down)(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface); + + void (*phylink_link_up)(void *mode_priv, + unsigned int plmode, + phy_interface_t interface, + struct phy_device *phy); + int (*phylink_pcs_link_state)(void *mode_priv, + struct phylink_link_state *); + void (*phylink_pcs_an_restart)(void *mode_priv); +}; + +struct bcm_enet_port_ops { + const struct bcm_enet_mode_ops *modes[4]; + size_t mode_count; + + /* called once at modprobe/rmmod */ + void *(*init)(struct bcm_enet_runner_priv *); + void (*release)(void *port_priv); +}; + +struct bcm_dsa_port { + struct net_device *slave_netdev; + unsigned int imp_port; + unsigned int port; + struct list_head next; +}; + +struct queue_info { + char irq_name[32]; + cpumask_t irq_affinity_mask; + struct irq_affinity_notify affinity_notifier; +}; + +struct bcm_enet_runner_priv { + struct napi_struct napi; + u32 irq_mask; + u32 work_todo; + u32 work_batch; + + struct rx_queue rxq[BCM_ENET_RUNNER_MAX_RXQ]; + unsigned int rxq_size; + + struct tx_queue txq[BCM_ENET_RUNNER_MAX_TXQ]; + u8 txq_port_map[DSA_MAX_PORTS]; + unsigned int txq_count; + unsigned int txq_size; + + unsigned int pkt_size; + unsigned int frag_size; + + struct net_device *netdev; + struct bcm_xrdp_priv *xrdp; + struct phylink *phylink; + struct phylink_config phylink_config; + struct platform_device *pdev; + + bool reset_scheduled; + struct delayed_work reset_link_work; + + const struct bcm_enet_port_ops *port_ops; + void *port_priv; + + unsigned int mode_idx; + const struct bcm_enet_mode_ops *mode_ops; + void *mode_priv; + + struct bcm_xrdp_enet_params xrdp_params; + struct queue_info rxq_info[BCM_ENET_RUNNER_MAX_RXQ]; + struct queue_info txq_info[BCM_ENET_RUNNER_MAX_TXQ]; + + struct notifier_block dsa_notifier; + bool dsa_notifier_registered; + struct list_head dsa_ports; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + unsigned int ff_hw_id; + struct tx_queue *ff_txq; + struct task_struct *ff_reclaim_thread; +#endif +}; + +extern struct dentry *bcm63158_dbg_root; + +extern const size_t bcm_runner_fw_estat_count; +extern const struct bcm_runner_ethtool_stat bcm_runner_fw_estat[]; +u64 bcm_runner_fw_read_estat(struct bcm_enet_runner_priv *priv, int idx); +void bcm_runner_fw_stop_tx(struct bcm_enet_runner_priv *priv); +bool bcm_runner_fw_tx_is_stopped(struct bcm_enet_runner_priv *priv); +void bcm_runner_fw_tx_stop_wait(struct bcm_enet_runner_priv *priv); +bool bcm_runner_fw_bbh_is_empty(struct bcm_enet_runner_priv *priv); + +int bcm_enet_runner_toggle_mode(struct bcm_enet_runner_priv *priv, + unsigned int new_mode_idx); + +void bcm_enet_runner_schedule_reset(struct bcm_enet_runner_priv *priv, + unsigned int delay_ms); +void bcm_enet_runner_unschedule_reset(struct bcm_enet_runner_priv *priv); + + +extern const struct ethtool_ops bcm_runner_ethtool_ops; +extern const struct bcm_enet_port_ops port_unimac_ops; +extern const struct bcm_enet_port_ops port_xport_ops; + +#endif /* BCM63158_ENET_RUNNER_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/enet_fw_defs.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/enet_fw_defs.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/enet_fw_defs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/enet_fw_defs.h 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,220 @@ +#ifndef ENET_FW_DEFS_H_ +#define ENET_FW_DEFS_H_ + +#define RX_FQM_BURST 8 +#define RX_FQM_SIZE (RX_FQM_BURST * 3) + +// +// RX global "registers" area, 16 bytes needed +// +#define RX_CONTROL_REG 0x0 +#define RX_CONTROL_RX_EN_SHIFT 0 +#define RX_CONTROL_RX_EN_MASK (1 << RX_CONTROL_RX_EN_SHIFT) +#define RX_CONTROL_RX_EN_F_OFFSET RX_CONTROL_RX_EN_SHIFT +#define RX_CONTROL_RX_EN_F_WIDTH 1 +#define RX_DESC_ADDRESS_REG 0x4 +#define RX_DESC_COUNT_REG 0x8 +#define RX_IRQ_MASK_REG 0xc + +// +// RX Free Queue Manager "registers" area, follows global, 32 + RX_FQM_SCRATCH_AREA size needed +// +#define RX_FQM_STATUS_REG 0x10 +#define RX_FQM_STATUS_RX_EN_SHIFT 0 +#define RX_FQM_STATUS_RX_EN_MASK (1 << RX_FQM_STATUS_RX_EN_SHIFT) +#define RX_FQM_STATUS_RX_EN_F_OFFSET RX_FQM_STATUS_RX_EN_SHIFT +#define RX_FQM_STATUS_RX_EN_F_WIDTH 1 + +#define RX_FQM_STAT_DBG_TASK_CALL_REG 0x14 +#define RX_FQM_STAT_DBG_CPU_RING_IDX_REG 0x18 +#define RX_FQM_STAT_DBG_FULL_REG 0x1c +#define RX_FQM_STAT_DBG_HOST_NOBUF_REG 0x20 + +#define RX_FQM_HEAD_IDX_REG 0x24 /* 8 bits */ +#define RX_FQM_TAIL_IDX_REG 0x25 /* 8 bits */ + +#define RX_FQM_SCRATCH_AREA 0x30 /* RX_FQM_SIZE * CPU_RX_DESC_LEN */ + +// +// RX xfer "registers" area, starts after global regs +// +#define RX_IF_REGS_BASE_OFF 0x100 +#define RX_IF_REGS_PERIF_SIZE 0x50 + +#define RX_XF_STATUS_REG 0x0 +#define RX_XF_STATUS_RX_EN_SHIFT 0 +#define RX_XF_STATUS_RX_EN_MASK (1 << RX_XF_STATUS_RX_EN_SHIFT) +#define RX_XF_STATUS_RX_EN_F_OFFSET RX_XF_STATUS_RX_EN_SHIFT +#define RX_XF_STATUS_RX_EN_F_WIDTH 1 + +#define RX_XF_STAT_RX_CNT_PKT_REG 0x04 +#define RX_XF_STAT_RX_CNT_DROP_NOBUF_REG 0x08 +#define RX_XF_STAT_RX_CNT_DROP_RXDIS_REG 0x0c +#define RX_XF_STAT_RX_CNT_DROP_RXERR_REG 0x10 + +#define RX_XF_STAT_DBG_TASK_CALL_REG 0x14 +#define RX_XF_STAT_DBG_LAST_PD0_REG 0x18 +#define RX_XF_STAT_DBG_LAST_PD1_REG 0x1c +#define RX_XF_STAT_DBG_LAST_PD2_REG 0x20 +#define RX_XF_STAT_DBG_LAST_PD3_REG 0x24 +#define RX_XF_STAT_DBG_LAST_SN_REG 0x28 +#define RX_XF_STAT_DBG_LAST_BN_REG 0x2c +#define RX_XF_STAT_DBG_LAST_PLEN_REG 0x30 +#define RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG 0x34 +#define RX_XF_STAT_DBG_INVALID_PD_CNT_REG 0x38 +#define RX_XF_SCRATCH_CPU_WBACK_DESC 0x3c /* 4 bytes needed */ +#define RX_XF_SCRATCH_CPU_DESC 0x40 /* CPU_RX_DESC_LEN space needed */ +#define RX_XF_SCRATCH_SBPM_REPLY 0x48 /* 8 bytes needed */ + +// +// CPU RX descriptor +// +#define CPU_RX_DESC_LEN 8 +#define CPU_RX_DESC_LEN_LOG2 3 + +#define CPU_RX_DESC0_LEN_SHIFT 0 +#define CPU_RX_DESC0_LEN_MASK (0xffff << CPU_RX_DESC0_LEN_SHIFT) +#define CPU_RX_DESC0_LEN_F_OFFSET CPU_RX_DESC0_LEN_SHIFT +#define CPU_RX_DESC0_LEN_F_WIDTH 16 + +// internal field +#define CPU_RX_DESC0_ABS_IDX_SHIFT 16 +#define CPU_RX_DESC0_ABS_IDX_MASK (0x3fff << CPU_RX_DESC0_ABS_IDX_SHIFT) +#define CPU_RX_DESC0_ABS_IDX_F_OFFSET CPU_RX_DESC0_ABS_IDX_SHIFT +#define CPU_RX_DESC0_ABS_IDX_F_WIDTH 14 + +#define CPU_RX_DESC0_HW_OWNED_SHIFT 31 +#define CPU_RX_DESC0_HW_OWNED_MASK (1 << CPU_RX_DESC0_HW_OWNED_SHIFT) +#define CPU_RX_DESC0_HW_OWNED_F_OFFSET CPU_RX_DESC0_HW_OWNED_SHIFT +#define CPU_RX_DESC0_HW_OWNED_F_WIDTH 1 + +#define CPU_RX_DESC1_OFFSET 4 + +#ifdef __KERNEL__ +struct rx_desc { + __be32 flags_len; + __be32 address; +}; +#endif + + +// +// TX "registers" area, 512 bytes needed +// + +/* fix TX_SCRATCH_SENT_DESC_QIDX if you change this */ +#define TXQ_MAX_COUNT 2 +#define TX_DESC_READ_BURST 8 +#define TX_PD_SEND_BURST 4 + +/* global scoped */ +#define TX_CONTROL_REG 0x0 /* 32 bits */ +#define TX_CONTROL_TX_EN_SHIFT 0 +#define TX_CONTROL_TX_EN_MASK (1 << TX_CONTROL_TX_EN_SHIFT) +#define TX_CONTROL_TX_EN_F_OFFSET TX_CONTROL_TX_EN_SHIFT +#define TX_CONTROL_TX_EN_F_WIDTH 1 + +#define TX_STATUS_REG 0x4 /* 32 bits */ +#define TX_STATUS_TX_EN_SHIFT 0 +#define TX_STATUS_TX_EN_MASK (1 << TX_STATUS_TX_EN_SHIFT) +#define TX_STATUS_TX_EN_F_OFFSET TX_STATUS_TX_EN_SHIFT +#define TX_STATUS_TX_EN_F_WIDTH 1 + +#define TX_BBH_PD_QUEUE_SIZE_REG 0x8 /* 16 bits, must be power of 2 - 1, min value is 3 */ +#define TX_BBH_MDU_QUEUE_ADDR_REG 0xa /* 16 bits */ +#define TX_BBH_BB_ID_REG 0xc /* 8 bits */ +#define TX_EPON_REPORTING_REG 0xd /* 8 bits */ + +#define TX_STAT_CNT_TX_DISABLED_REG 0x10 /* 32 bits */ + +#define TX_STAT_DBG_TASK_CALL_REG 0x14 /* 32 bits */ +#define TX_STAT_DBG_FIFO_FULL_REG 0x18 /* 32 bits */ +#define TX_STAT_DBG_MDU_FW_RECLAIM_IDX_REG 0x1c /* 32 bits */ +#define TX_STAT_DBG_MDU_FW_PUSH_IDX_REG 0x20 /* 32 bits */ + +#define TX_SCRATCH_MAX1 0x24 +#define TX_SCRATCH_MAX2 0x28 +#define TX_SCRATCH_MAX3 0x2c + +/* used for dma & temp */ +#define TX_SCRATCH_SENT_DESC_QIDX 0x30 /* 256 bits: 1 bit for each desc, XXX: works for 2 TX queues only */ +#define TX_SCRATCH_ZERO 0x50 /* 4 bytes needed */ +#define TX_SCRATCH_ACB_STAT_BUF 0x60 /* 8 bytes needed */ + +/* per-queue scoped */ +#define TXQ_REGS_BASE_OFF 0x80 +#define TXQ_REGS_PERQ_SIZE 0x80 +#define TXQ_REGS_PERQ_SIZE_LOG2 7 /* == 128 (0x80) */ + +#define TXQ_OFF_DESC_ADDRESS_REG 0x0 /* 32 bits, DDR queue base address */ +#define TXQ_OFF_DESC_COUNT_REG 0x4 /* 32 bits, must be power of 2, max 2^15 */ +#define TXQ_OFF_IRQ_MASK_REG 0x8 /* 32 bits */ +#define TXQ_OFF_ACB_ENABLED_REG 0xc /* 8 bits */ +#define TXQ_OFF_ACB_QIDX_REG 0xd /* 8 bits */ +#define TXQ_OFF_ACB_CONTROL_REG 0xe /* 16 bits */ +#define TXQ_OFF_TX_DESC_IDX 0x10 /* 8 bits */ +#define TXQ_OFF_TX_DESC_CNT 0x11 /* 8 bits */ +#define TXQ_OFF_RING_PUSH_IDX_REG 0x12 /* 16 bits */ +#define TXQ_OFF_RING_RECLAIM_IDX_REG 0x14 /* 16 bits */ +#define TXQ_OFF_STAT_CNT_PKT_SENT_REG 0x18 /* 32 bits */ +#define TXQ_OFF_STAT_CNT_PKT_RECLAIMED_REG 0x1c /* 32 bits */ +#define TXQ_OFF_STAT_CNT_ACB_QFULL 0x20 /* 32 bits */ +#define TXQ_OFF_ACB_TX_BUF 0x30 /* 16 bytes needed */ +#define TXQ_OFF_TX_DESCS_BUF 0x40 /* CPU_TX_DESC_LEN * TX_DESC_READ_BURST size needed */ + + +/* + * ACB control field format + */ +#define TXQ_ACBCTRL_EGRESS_QUEUE_SHIFT 0 +#define TXQ_ACBCTRL_EGRESS_PORT_SHIFT 3 +#define TXQ_ACBCTRL_IMP_PORT_SHIFT 6 + +#ifdef __KERNEL__ +static inline unsigned int enet_fw_imp_port_map(unsigned int p) +{ + switch (p) { + case 5: + return 1; + case 7: + return 2; + case 8: + return 0; + } + WARN(1, "unknown imp port %d", p); + return 0; +} +#endif + +/* + * runner enet tx descriptor + */ +#define CPU_TX_DESC_LEN 8 +#define CPU_TX_DESC_LEN_LOG2 3 + +#define CPU_TX_DESC0_LEN_SHIFT 0 +#define CPU_TX_DESC0_LEN_MASK (0xffff << CPU_TX_DESC0_LEN_SHIFT) +#define CPU_TX_DESC0_LEN_F_OFFSET CPU_TX_DESC0_LEN_SHIFT +#define CPU_TX_DESC0_LEN_F_WIDTH 16 + +#define CPU_TX_DESC0_HW_OWNED_SHIFT 31 +#define CPU_TX_DESC0_HW_OWNED_MASK (1 << CPU_TX_DESC0_HW_OWNED_SHIFT) +#define CPU_TX_DESC0_HW_OWNED_F_OFFSET CPU_TX_DESC0_HW_OWNED_SHIFT +#define CPU_TX_DESC0_HW_OWNED_F_WIDTH 1 + +/* internal fw use */ +#define CPU_TX_DESC0_ACB_DONE_SHIFT 30 +#define CPU_TX_DESC0_ACB_DONE_MASK (1 << CPU_TX_DESC0_ACB_DONE_SHIFT) +#define CPU_TX_DESC0_ACB_DONE_F_OFFSET CPU_TX_DESC0_ACB_DONE_SHIFT +#define CPU_TX_DESC0_ACB_DONE_F_WIDTH 1 + +#define CPU_TX_DESC1_OFFSET 4 + +#ifdef __KERNEL__ +struct tx_desc { + __be32 flags_len; + __be32 address; +}; +#endif + +#endif /* !ENET_FW_DEFS_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/ethtool.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/ethtool.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/ethtool.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/ethtool.c 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,305 @@ +#include "bcm63158_enet_runner.h" + +static char bcm_enet_runner_driver_name[] = "bcm63158_enet_runner"; +static char bcm_enet_runner_driver_version[] = "1.0"; + +/* + * ethtool callbacks + */ +static void bcm_runner_get_drvinfo(struct net_device *netdev, + struct ethtool_drvinfo *drvinfo) +{ + strlcpy(drvinfo->driver, bcm_enet_runner_driver_name, sizeof(drvinfo->driver)); + strlcpy(drvinfo->version, bcm_enet_runner_driver_version, + sizeof(drvinfo->version)); + strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version)); + strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info)); +} + +struct ethtool_priv_flags_strings { + const char string[ETH_GSTRING_LEN]; +}; + +static const struct ethtool_priv_flags_strings bcm_runner_priv_flags_strings[] = { + { .string = "force-lbe-output" }, + { .string = "force-lbe-output-value" }, + { .string = "st-sync-ok" }, +}; + +static int bcm_runner_get_sset_count(struct net_device *netdev, + int string_set) +{ + struct bcm_enet_runner_priv *priv; + + priv = netdev_priv(netdev); + + switch (string_set) { + case ETH_SS_STATS: + if (!priv->mode_ops) + return 0; + + return priv->mode_ops->mib_estat_count + bcm_runner_fw_estat_count; + + case ETH_SS_PRIV_FLAGS: + return ARRAY_SIZE(bcm_runner_priv_flags_strings); + + default: + return -EINVAL; + } +} + +static void bcm_runner_get_strings(struct net_device *netdev, + u32 stringset, u8 *data) +{ + struct bcm_enet_runner_priv *priv; + int i, offset; + + priv = netdev_priv(netdev); + switch (stringset) { + case ETH_SS_STATS: + { + const struct bcm_runner_ethtool_stat *estat; + size_t estat_count; + + if (!priv->mode_ops) + return; + + estat = priv->mode_ops->mib_estat; + estat_count = priv->mode_ops->mib_estat_count; + + offset = 0; + for (i = 0; i < estat_count; i++) { + memcpy(data + (i + offset) * ETH_GSTRING_LEN, + estat[i].stat_string, + ETH_GSTRING_LEN); + } + offset += estat_count; + for (i = 0; i < bcm_runner_fw_estat_count; i++) { + memcpy(data + (i + offset) * ETH_GSTRING_LEN, + bcm_runner_fw_estat[i].stat_string, + ETH_GSTRING_LEN); + } + break; + } + + case ETH_SS_PRIV_FLAGS: + memcpy(data, bcm_runner_priv_flags_strings, + sizeof (bcm_runner_priv_flags_strings)); + break; + } +} + + +static void bcm_runner_get_ethtool_stats(struct net_device *netdev, + struct ethtool_stats *stats, + u64 *data) +{ + struct bcm_enet_runner_priv *priv; + size_t i, offset; + + priv = netdev_priv(netdev); + + offset = 0; + if (priv->mode_ops) { + const struct bcm_runner_ethtool_stat *estat; + size_t estat_count; + void *mib_data; + + estat = priv->mode_ops->mib_estat; + estat_count = priv->mode_ops->mib_estat_count; + + priv->mode_ops->mib_update(priv->mode_priv); + mib_data = priv->mode_ops->mib_get_data(priv->mode_priv); + + for (i = 0; i < estat_count; i++) { + const struct bcm_runner_ethtool_stat *s; + char *p; + + s = &estat[i]; + p = (char *)mib_data + s->offset; + data[offset + i] = (s->size == sizeof(u64)) ? + *(u64 *)p : *(u32 *)p; + } + offset += estat_count; + } + + for (i = 0; i < bcm_runner_fw_estat_count; i++) + data[offset + i] = bcm_runner_fw_read_estat(priv, i); +} + +static int bcm_runner_nway_reset(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + return phylink_ethtool_nway_reset(priv->phylink); +} + +static int +bcm_runner_get_link_ksettings(struct net_device *dev, + struct ethtool_link_ksettings *cmd) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + return phylink_ethtool_ksettings_get(priv->phylink, cmd); +} + +static int +bcm_runner_set_link_ksettings(struct net_device *dev, + const struct ethtool_link_ksettings *cmd) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + return phylink_ethtool_ksettings_set(priv->phylink, cmd); +} + +static int +bcm_runner_set_priv_flags(struct net_device *dev, u32 flags) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops) + return -ENETDOWN; + + if (!priv->mode_ops->set_priv_flags) + return -EOPNOTSUPP; + + return priv->mode_ops->set_priv_flags(priv->mode_priv, flags); +} + +static u32 +bcm_runner_get_priv_flags(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops || !priv->mode_ops->get_priv_flags) + return 0; + + return priv->mode_ops->get_priv_flags(priv->mode_priv); +} + +static int +bcm_runner_get_tunable(struct net_device *dev, + const struct ethtool_tunable *tunable, + void *data) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + int ret = 0; + + switch (tunable->id) { + case ETHTOOL_MAC_MODE: + *(u32 *)data = priv->mode_idx; + break; + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static int +bcm_runner_set_tunable(struct net_device *dev, + const struct ethtool_tunable *tunable, + const void *data) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + int ret = 0; + + switch (tunable->id) { + case ETHTOOL_MAC_MODE: + { + unsigned int new_mode_idx; + + new_mode_idx = *(u32 *)data; + if (new_mode_idx == priv->mode_idx) + break; + + ret = bcm_enet_runner_toggle_mode(priv, new_mode_idx); + break; + } + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + +static int +bcm_runner_get_epon_param(struct net_device *dev, + struct ethtool_epon_param *param) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops) + return -ENETDOWN; + + if (!priv->mode_ops->get_epon_param) + return -EOPNOTSUPP; + + return priv->mode_ops->get_epon_param(priv->mode_priv, param); +} + +static int +bcm_runner_set_epon_param(struct net_device *dev, + const struct ethtool_epon_param *param) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (!priv->mode_ops) + return -ENETDOWN; + + if (!priv->mode_ops->set_epon_param) + return -EOPNOTSUPP; + + return priv->mode_ops->set_epon_param(priv->mode_priv, param); +} + +static void +bcm_runner_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + er->rx_max_pending = 4096; + er->tx_max_pending = 4096; + + er->rx_pending = priv->rxq_size; + er->tx_pending = priv->txq_size; +} + +static int +bcm_runner_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + + if (er->rx_mini_pending || er->rx_jumbo_pending) + return -EINVAL; + + if (netif_running(dev)) + return -EBUSY; + + priv->rxq_size = er->rx_pending; + priv->txq_size = er->tx_pending; + + return 0; +} + +const struct ethtool_ops bcm_runner_ethtool_ops = { + .get_drvinfo = bcm_runner_get_drvinfo, + .get_ethtool_stats = bcm_runner_get_ethtool_stats, + .get_link = ethtool_op_get_link, + .get_sset_count = bcm_runner_get_sset_count, + .get_strings = bcm_runner_get_strings, + .get_priv_flags = bcm_runner_get_priv_flags, + .set_priv_flags = bcm_runner_set_priv_flags, + + .get_tunable = bcm_runner_get_tunable, + .set_tunable = bcm_runner_set_tunable, + + .get_epon_param = bcm_runner_get_epon_param, + .set_epon_param = bcm_runner_set_epon_param, + + .nway_reset = bcm_runner_nway_reset, + .get_link_ksettings = bcm_runner_get_link_ksettings, + .set_link_ksettings = bcm_runner_set_link_ksettings, + + .get_ringparam = bcm_runner_get_ringparam, + .set_ringparam = bcm_runner_set_ringparam, +}; diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/main.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/main.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/main.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/main.c 2021-04-21 09:44:50.971838485 +0200 @@ -0,0 +1,4308 @@ +#include +#include +#include +#include "bcm63158_enet_runner.h" +#include "enet_fw_defs.h" + +struct dentry *bcm63158_dbg_root; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../../../net/bridge/br_private.h" +#include "../../../net/fbxbridge/fbxbr_private.h" +#include "../../../net/dsa/dsa_priv.h" +#endif + +#define RX_OFFSET (ALIGN(NET_SKB_PAD, SMP_CACHE_BYTES) + 2) + + +/* Ingress and egress opcodes */ +#define BRCM_OPCODE_SHIFT 5 +#define BRCM_OPCODE_MASK 0x7 + +/* Ingress fields */ +/* 1st byte in the tag */ +#define BRCM_IG_TC_SHIFT 2 +#define BRCM_IG_TC_MASK 0x7 +/* 2nd byte in the tag */ +#define BRCM_IG_TE_MASK 0x3 +#define BRCM_IG_TS_SHIFT 7 +/* 3rd byte in the tag */ +#define BRCM_IG_DSTMAP2_MASK 1 +#define BRCM_IG_DSTMAP1_MASK 0xff + +/* + * for FW dev (driver won't write to fw area) + */ +#undef NO_FW_IO + +/* + * discard all rx traffic and re-arm descriptor (for benchmark) + */ +#undef DBG_RX_DISCARD_ALL + +/* + * for dev (debug print on rx/tx) + */ +#undef RX_DBG_PRINT +#undef TX_DBG_PRINT +#undef FFTX_DBG_PRINT + +#ifdef RX_DBG_PRINT +#define rxdbg(...) printk(__VA_ARGS__) +#else +#define rxdbg(...) +#endif + +#ifdef TX_DBG_PRINT +#define txdbg(...) printk(__VA_ARGS__) +#else +#define txdbg(...) +#endif + +#ifdef FFTX_DBG_PRINT +#define fftxdbg(...) printk(__VA_ARGS__) +#else +#define fftxdbg(...) +#endif + +/* + * io accessors, RX global regs + */ +static inline u8 fw_rx_reg_readb(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread8(priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline u16 fw_rx_reg_readh(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread16be(priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline u32 fw_rx_reg_readl(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread32be(priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline void fw_rx_reg_writel(struct bcm_enet_runner_priv *priv, u32 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite32be(val, priv->xrdp_params.rx_regs + offset); +#endif +} + +static inline u32 fw_rx_xf_off(u32 xf_id, u32 reg) +{ + return RX_IF_REGS_BASE_OFF + xf_id * RX_IF_REGS_PERIF_SIZE + reg; +} + +/* + * io accessors, TX global regs + */ +static inline u8 fw_tx_reg_readb(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread8(priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline u16 fw_tx_reg_readh(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread16be(priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline u32 fw_tx_reg_readl(struct bcm_enet_runner_priv *priv, u32 offset) +{ +#ifdef NO_FW_IO + return 0; +#else + return ioread32be(priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline u32 fw_txqoff(u32 qidx, u32 reg) +{ + return TXQ_REGS_BASE_OFF + qidx * TXQ_REGS_PERQ_SIZE + reg; +} + +static inline void fw_tx_reg_writel(struct bcm_enet_runner_priv *priv, u32 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite32be(val, priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline void fw_tx_reg_writeh(struct bcm_enet_runner_priv *priv, u16 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite16be(val, priv->xrdp_params.tx_regs + offset); +#endif +} + +static inline void fw_tx_reg_writeb(struct bcm_enet_runner_priv *priv, u8 val, u32 offset) +{ +#ifndef NO_FW_IO + iowrite8(val, priv->xrdp_params.tx_regs + offset); +#endif +} + +/* + * FF declarations + */ +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +struct ff_dev_desc { + bool is_hardware; + const char *netdev_name; + const char *bridge_name; +}; + +struct ff_dev_ctx { + __be16 vlan_id; + uint8_t is_hardware:1; + uint8_t hw_id:2; + uint8_t active:1; + uint8_t use_dsa:1; + uint8_t dsa_port:3; + u8 hwaddr[6]; + + struct net_device *netdev; + struct net_device *br_netdev; + struct net_bridge_port *br_port; + struct fbxbr_port *fbxbr_port; + struct net_device *real_netdev; +}; + +struct ff_tun_ctx { + struct net_device *netdev; + u16 mtu; + u8 active:1; + + /* sit parameters */ + union ff_tun_params { + struct { + u32 src; + u32 s6rd_prefix; + u32 s6rd_pmask; + u8 s6rd_plen; + } sit; + + struct { + /* map parameters */ + u32 ipv4_prefix; + u32 ipv4_pmask; + u8 ipv4_plen; + u8 ipv6_plen; + struct in6_addr src; + struct in6_addr br; + + u64 ipv6_prefix; + u32 ea_addr_mask; + u16 ea_port_mask; + u8 psid_len; + u8 ea_lshift; + } map; + } u; +}; + +enum { + FF_HWDEV_ID_UNIMAC0, + FF_HWDEV_ID_UNIMAC1, + FF_HWDEV_ID_UNIMAC2, + FF_HWDEV_ID_FTTH, + + FF_HWDEV_ID_LAST = FF_HWDEV_ID_FTTH, +}; + +enum { + FF_DEV_WLAN1, + FF_DEV_SWP1, + FF_DEV_SWP2, + FF_DEV_SWP3, + FF_DEV_WAN, + + FF_DEV_LAST = FF_DEV_WAN, + FF_DEV_LAN_LAST = FF_DEV_SWP3, +}; + +struct ff_ctx { + struct ff_dev_ctx devs[FF_DEV_LAST + 1]; + struct ff_tun_ctx tun; + u32 jiffies; + struct bcm_enet_runner_priv *ports_by_hw_id[FF_HWDEV_ID_LAST + 1]; + + struct ff_dev_desc devs_desc[FF_DEV_LAST + 1]; + char tun_netdev_name[IFNAMSIZ]; +}; + +static struct notifier_block ff_notifier; +static DEFINE_MUTEX(ff_notifier_mutex); +static bool ff_enabled; + +static struct ff_ctx ff = { + .devs_desc = { + [FF_DEV_WLAN1] = { + .is_hardware = false, + .netdev_name = "wlan1", + .bridge_name = "br0", + }, + + [FF_DEV_SWP1] = { + .is_hardware = true, + .netdev_name = "swp1", + .bridge_name = "br0", + }, + + [FF_DEV_SWP2] = { + .is_hardware = true, + .netdev_name = "swp2", + .bridge_name = "br0", + }, + + [FF_DEV_SWP3] = { + .is_hardware = true, + .netdev_name = "swp3", + .bridge_name = "br0", + }, + + [FF_DEV_WAN] = { + .is_hardware = true, + .netdev_name = "ftthpub0", + }, + }, +}; + +static DEFINE_SPINLOCK(ff_lock); + + +/* + * + */ +static bool __ff_tx_queue_full(struct tx_queue *txq) +{ + unsigned int cur_desc, next_desc; + + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + if (unlikely(next_desc == txq->tx_dirty_desc)) + return true; + + return false; +} + +/* + * + */ +static bool __ff_tx_queue_can_reclaim(struct tx_queue *txq) +{ + struct tx_desc *desc; + unsigned int dirty_desc; + u32 flags_len; + + dirty_desc = txq->tx_dirty_desc; + if (dirty_desc == txq->tx_cur_desc) + return false; + + desc = &txq->tx_desc_area[dirty_desc]; + flags_len = be32_to_cpu(desc->flags_len); + + if ((flags_len & CPU_TX_DESC0_HW_OWNED_MASK)) + return false; + + return true; +} + +static void *ff_tx_queue_frag_reclaim(struct bcm_enet_runner_priv *priv, + unsigned int needed_frag_size) +{ + struct tx_desc *desc; + struct tx_queue *txq = priv->ff_txq; + unsigned int dirty_desc, next_desc; + void *frag; + unsigned int frag_size; + + spin_lock(&txq->tx_lock); + if (!__ff_tx_queue_can_reclaim(txq)) { + spin_unlock(&txq->tx_lock); + return NULL; + } + + dirty_desc = txq->tx_dirty_desc; + desc = &txq->tx_desc_area[dirty_desc]; + frag = txq->tx_desc_pdata[dirty_desc].data; + frag_size = txq->tx_desc_pdata[dirty_desc].len; + txq->tx_desc_pdata[dirty_desc].data = NULL; + + next_desc = dirty_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + txq->tx_dirty_desc = next_desc; + spin_unlock(&txq->tx_lock); + + if (needed_frag_size != frag_size) { + fftxdbg("ffrecl[%s/q%u]: desc_idx:%u, bad size:%u != %u\n", + priv->netdev->name, + txq->index, + dirty_desc, + frag_size, + needed_frag_size); + skb_free_frag(frag); + return NULL; + } + + fftxdbg("ffrecl[%s/q%u]: desc_idx:%u frag:%pS size:%u\n", + priv->netdev->name, + txq->index, + dirty_desc, + frag, + frag_size); + + return frag; +} + +static void *ff_reclaim_any_sent_frag(unsigned int pkt_size, + unsigned int rx_ff_dev_idx, + int ff_peek_first_dev_idx) +{ + struct bcm_enet_runner_priv *oport; + unsigned int hw_id, idx_todo, hwid_done; + void *frag; + size_t i; + + BUG_ON(!ff.devs[ff_peek_first_dev_idx].is_hardware); + hw_id = ff.devs[ff_peek_first_dev_idx].hw_id; + oport = ff.ports_by_hw_id[hw_id]; + frag = ff_tx_queue_frag_reclaim(oport, pkt_size); + if (frag) + return frag; + + /* + * failed, try other tx queues this port can ff packets to + */ + if (rx_ff_dev_idx == FF_DEV_WAN) { + idx_todo = ((1 << FF_DEV_SWP1) | + (1 << FF_DEV_SWP2) | + (1 << FF_DEV_SWP3)); + } else { + idx_todo = (1 << FF_DEV_WAN); + } + + idx_todo &= ~(1 << ff_peek_first_dev_idx); + hwid_done = (1 << hw_id); + + for (i = 0; idx_todo && i < FF_DEV_LAST + 1; i++) { + if (!(idx_todo & (1 << i))) + continue; + + BUG_ON(!ff.devs[i].is_hardware); + hw_id = ff.devs[i].hw_id; + if (hwid_done & (1 << hw_id)) + continue; + + oport = ff.ports_by_hw_id[hw_id]; + + frag = ff_tx_queue_frag_reclaim(oport, pkt_size); + if (frag) + return frag; + + hwid_done |= (1 << hw_id); + } + return NULL; +} + +#endif + +static int rxq_refill_desc(struct bcm_enet_runner_priv *priv, + struct rx_queue *rxq, + int desc_idx, + bool unmap, + void *forced_frag) +{ + struct rx_desc *desc; + void *frag; + bool frag_allocated = true; + dma_addr_t addr; + u32 val; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (forced_frag) { + frag = forced_frag; + frag_allocated = false; + } + else +#endif + frag = napi_alloc_frag(priv->frag_size); + + if (!frag) + return -ENOMEM; + + desc = &rxq->rx_desc_area[desc_idx]; + if (unmap) { + addr = be32_to_cpu(desc->address); + dma_unmap_single(priv->netdev->dev.parent, + addr, + priv->pkt_size, + DMA_FROM_DEVICE); + } + + addr = dma_map_single(priv->netdev->dev.parent, + frag + RX_OFFSET, + priv->pkt_size, + DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(priv->netdev->dev.parent, addr))) { + printk("dma_map_single failed\n"); + if (frag_allocated) { + rxq->frags[desc_idx] = NULL; + skb_free_frag(frag); + } + return -ENOMEM; + } + + rxdbg("rxq_refill_desc: idx:%u addr:0x%08x\n", + desc_idx, addr); + + rxq->frags[desc_idx] = frag; + desc->address = cpu_to_be32(addr); + wmb(); + val = CPU_RX_DESC0_HW_OWNED_MASK | + (priv->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + desc->flags_len = cpu_to_be32(val); + return 0; +} + +/* + * FF stuff + */ +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +static inline u32 ff_gen_netmask(u8 len) +{ + return htonl(~((1 << (32 - len)) - 1)); +} + +static void __ff_tun_set_params(bool active, + unsigned int mtu, + const union ff_tun_params *tp) +{ + if (!active) { + if (!ff.tun.active) + return; + + printk(KERN_DEBUG "ff: tunnel now NOT active\n"); + ff.tun.active = 0; + return; + } + + if (ff.tun.active) { + if (ff.tun.mtu == mtu && !memcmp(tp, &ff.tun.u, sizeof (*tp))) + return; + } + + ff.tun.mtu = mtu; + memcpy(&ff.tun.u, tp, sizeof (*tp)); + + if (!ff.tun.active) + printk(KERN_DEBUG "ff: tunnel now active\n"); + else + printk(KERN_DEBUG "ff: tunnel params updated\n"); + + ff.tun.active = true; +} + +static void __ff_tun_read_params(void) +{ + union ff_tun_params tp; + const struct ff_dev_ctx *wan_ff_dev; + + if (!ff.tun.netdev) + return; + + wan_ff_dev = &ff.devs[FF_DEV_WAN]; + if (!wan_ff_dev->netdev) { + __ff_tun_set_params(false, 0, NULL); + return; + } + + memset(&tp, 0, sizeof (tp)); + + if (ff.tun.netdev->type == ARPHRD_SIT) { + const struct ip_tunnel *tun = netdev_priv(ff.tun.netdev); + const struct ip_tunnel_6rd_parm *ip6rd = &tun->ip6rd; + + if (!ip6rd->prefixlen || ip6rd->prefixlen > 32) { + printk(KERN_DEBUG "ff: unsupported 6rd plen\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + if (ff.tun.netdev->mtu + sizeof (struct iphdr) > wan_ff_dev->netdev->mtu) { + printk(KERN_DEBUG "ff: WAN mtu too " + "small for tunnel (%u => %u)\n", + ff.tun.netdev->mtu, wan_ff_dev->netdev->mtu); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.sit.src = tun->parms.iph.saddr; + tp.sit.s6rd_prefix = ip6rd->prefix.s6_addr32[0]; + tp.sit.s6rd_pmask = ff_gen_netmask(ip6rd->prefixlen); + tp.sit.s6rd_plen = ip6rd->prefixlen; + __ff_tun_set_params(true, ff.tun.netdev->mtu, &tp); + return; + } + + if (ff.tun.netdev->type == ARPHRD_TUNNEL6) { + const struct ip6_tnl *t = netdev_priv(ff.tun.netdev); + const struct __ip6_tnl_parm *prm = &t->parms; + const struct __ip6_tnl_fmr *fmr; + + if (ff.tun.netdev->mtu + sizeof (struct ipv6hdr) > + wan_ff_dev->netdev->mtu) { + printk(KERN_DEBUG "ff: WAN mtu too " + "small for tunnel (%u => %u)\n", + ff.tun.netdev->mtu, wan_ff_dev->netdev->mtu); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.map.src = prm->laddr; + tp.map.br = prm->raddr; + + fmr = prm->fmrs; + if (!fmr) { + tp.map.ipv4_prefix = 0; + __ff_tun_set_params(true, ff.tun.netdev->mtu, &tp); + return; + } + + if (fmr->ip6_prefix_len < 32 || + (fmr->ip6_prefix_len + 32 - fmr->ip4_prefix_len > 64)) { + printk(KERN_DEBUG "ff: unsupp MAP-E: eabits " + "span 32 bits\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + if (fmr->offset) { + printk(KERN_DEBUG "ff: unsupp MAP-E: non zero " + "PSID offset\n"); + __ff_tun_set_params(false, 0, NULL); + return; + } + + tp.map.ipv4_prefix = fmr->ip4_prefix.s_addr; + tp.map.ipv4_pmask = ff_gen_netmask(fmr->ip4_prefix_len); + tp.map.ipv4_plen = fmr->ip4_prefix_len; + tp.map.ipv6_plen = fmr->ip6_prefix_len; + memcpy(&tp.map.ipv6_prefix, &fmr->ip6_prefix, 8); + + tp.map.ea_addr_mask = ~ff_gen_netmask(fmr->ip4_prefix_len); + if (fmr->ea_len <= 32 - fmr->ip4_prefix_len) { + /* v4 prefix or full IP */ + u32 addr_bits; + + addr_bits = fmr->ip4_prefix_len + fmr->ea_len; + if (addr_bits != 32) + tp.map.ea_addr_mask &= ff_gen_netmask(addr_bits); + tp.map.psid_len = 0; + } else { + u8 psid_len; + + psid_len = fmr->ea_len - (32 - fmr->ip4_prefix_len); + tp.map.psid_len = psid_len; + tp.map.ea_port_mask = ff_gen_netmask(psid_len); + } + + tp.map.ea_lshift = 32 - (fmr->ip6_prefix_len - 32) - + fmr->ea_len; + + __ff_tun_set_params(true, ff.tun.netdev->mtu, &tp); + return; + } +} + +static void __ff_tun_capture(void) +{ + struct net_device *dev; + + if (ff.tun.netdev) { + printk(KERN_ERR "ff: error: tun already registered\n"); + return; + } + + dev = dev_get_by_name(&init_net, ff.tun_netdev_name); + if (!dev) { + return; + } + + if (dev->type != ARPHRD_SIT && dev->type != ARPHRD_TUNNEL6) { + return; + } + + if (!(dev->flags & IFF_UP)) { + dev_put(ff.tun.netdev); + return; + } + + ff.tun.netdev = dev; + __ff_tun_read_params(); + printk(KERN_INFO "ff: tun dev grabbed\n"); +} + +static void __ff_tun_release(void) +{ + int was_on = 0; + + if (ff.tun.netdev) { + dev_put(ff.tun.netdev); + ff.tun.netdev = NULL; + was_on = 1; + } + if (was_on) + printk(KERN_INFO "ff: tun dev released\n"); +} + +static void ff_notifier_event_tunnel(struct net_device *dev, + unsigned long event) +{ + spin_lock_bh(&ff_lock); + + switch (event) { + case NETDEV_UP: + if (!ff.tun.netdev) + __ff_tun_capture(); + break; + + case NETDEV_CHANGE: + case NETDEV_CHANGEMTU: + if (ff.tun.netdev == dev) + __ff_tun_read_params(); + break; + + case NETDEV_GOING_DOWN: + case NETDEV_DOWN: + case NETDEV_UNREGISTER: + if (ff.tun.netdev == dev) + __ff_tun_release(); + break; + } + + spin_unlock_bh(&ff_lock); +} + +static int ff_dev_resolve_bridge(struct ff_dev_ctx *ff_dev, + const char *bridge_name) +{ + bool ok = false; + + rcu_read_lock(); + + if (netif_is_bridge_port(ff_dev->netdev)) { + struct net_bridge_port *br_port; + struct net_bridge *br; + + br_port = br_port_get_rcu(ff_dev->netdev); + if (!br_port) + goto done; + + br = br_port->br; + if (strcmp(br->dev->name, bridge_name)) + goto done; + + ff_dev->br_port = br_port; + if (br->dev->flags & IFF_UP) { + memcpy(ff_dev->hwaddr, br->dev->dev_addr, 6); + ff_dev->br_netdev = br->dev; + ok = true; + } + } + + if (netif_is_fbxbridge_port(ff_dev->netdev)) { + struct fbxbr_port *fbxbr_port; + struct fbxbr *fbxbr; + + fbxbr_port = fbxbr_port_get_rcu(ff_dev->netdev); + if (!fbxbr_port) + goto done; + + fbxbr = fbxbr_port->br; + if (strcmp(fbxbr->dev->name, bridge_name)) + goto done; + + ff_dev->fbxbr_port = fbxbr_port_get_rcu(ff_dev->netdev); + if (fbxbr->dev->flags & IFF_UP) + ok = true; + } + +done: + rcu_read_unlock(); + return ok ? 0 : 1; +} + +static bool ff_dev_bridge_is_up(struct ff_dev_ctx *ff_dev) +{ + if (ff_dev->br_port) + return ff_dev->br_port->br->dev->flags & IFF_UP; + if (ff_dev->fbxbr_port) + return ff_dev->fbxbr_port->br->dev->flags & IFF_UP; + return false; +} + +static void ff_dev_mark_active(struct ff_dev_ctx *ff_dev) +{ + spin_lock_bh(&ff_lock); + ff_dev->active = true; + spin_unlock_bh(&ff_lock); + printk(KERN_INFO "ff: ff_dev %s: now active\n", ff_dev->netdev->name); +} + +static void ff_dev_mark_inactive(struct ff_dev_ctx *ff_dev) +{ + bool was_active; + + spin_lock_bh(&ff_lock); + was_active = ff_dev->active; + ff_dev->active = false; + spin_unlock_bh(&ff_lock); + + if (was_active) + printk(KERN_INFO "ff: ff_dev %s: now inactive\n", ff_dev->netdev->name); +} + +static void ff_notifier_event_dev(struct net_device *netdev, + unsigned long event, + unsigned int dev_idx) +{ + const struct ff_dev_desc *desc = &ff.devs_desc[dev_idx]; + struct ff_dev_ctx *ff_dev = &ff.devs[dev_idx]; + struct net_device *real_netdev = netdev; + size_t i; + + switch (event) { + case NETDEV_UP: + { + struct dsa_port *dsap = NULL; + bool found; + + if (ff_dev->active) { + /* ignore up event while already active */ + return; + } + + if (is_vlan_dev(netdev)) { + ff_dev->vlan_id = ntohs(vlan_dev_vlan_id(netdev)); + real_netdev = vlan_dev_upper_dev(netdev); + } else + ff_dev->vlan_id = 0; + + if (dsa_is_slave(real_netdev)) { + dsap = dsa_slave_to_port(real_netdev); + real_netdev = dsa_slave_to_master(real_netdev); + } + + if (real_netdev != netdev && !(real_netdev->flags & IFF_UP)) + return; + + /* does this device matches one hardware port */ + if (!desc->is_hardware) + ff_dev->is_hardware = 0; + else { + found = false; + for (i = 0; i < ARRAY_SIZE(ff.ports_by_hw_id); i++) { + struct bcm_enet_runner_priv *port; + + port = ff.ports_by_hw_id[i]; + + if (!port) + continue; + if (port->netdev != real_netdev) + continue; + + found = true; + break; + } + + if (!found) + return; + + if (dsap) { + ff_dev->use_dsa = 1; + ff_dev->dsa_port = dsap->index; + } + ff_dev->hw_id = i; + ff_dev->is_hardware = 1; + } + + dev_hold(netdev); + ff_dev->netdev = netdev; + ff_dev->real_netdev = real_netdev; + memcpy(ff_dev->hwaddr, netdev->dev_addr, 6); + + if (dev_idx == FF_DEV_WAN) { + spin_lock_bh(&ff_lock); + __ff_tun_read_params(); + spin_unlock_bh(&ff_lock); + } + + /* resolve bridge */ + if (desc->bridge_name) { + if (ff_dev_resolve_bridge(ff_dev, desc->bridge_name)) + return; + } + + ff_dev_mark_active(ff_dev); + break; + } + + case NETDEV_CHANGEUPPER: + if (!desc->bridge_name || !ff_dev->netdev) + return; + + if (!ff_dev->active) { + if (!ff_dev_resolve_bridge(ff_dev, desc->bridge_name)) + ff_dev_mark_active(ff_dev); + } else { + if (!ff_dev_bridge_is_up(ff_dev)) + ff_dev_mark_inactive(ff_dev); + } + break; + + case NETDEV_GOING_DOWN: + case NETDEV_DOWN: + case NETDEV_UNREGISTER: + if (!ff_dev->netdev) + return; + + ff_dev_mark_inactive(ff_dev); + + /* remove all references */ + dev_put(netdev); + ff_dev->netdev = NULL; + ff_dev->real_netdev = NULL; + ff_dev->br_port = NULL; + ff_dev->fbxbr_port = NULL; + ff_dev->br_netdev = NULL; + break; + } +} + +static int ff_notifier_event(struct net_device *dev, unsigned long event) +{ + size_t i; + + mutex_lock(&ff_notifier_mutex); + + /* + * check for tun match + */ + if (!strcmp(dev->name, ff.tun_netdev_name)) { + ff_notifier_event_tunnel(dev, event); + mutex_unlock(&ff_notifier_mutex); + return 0; + } + + /* + * check for dev match + */ + for (i = 0; i < ARRAY_SIZE(ff.devs_desc); i++) { + if (!strcmp(dev->name, ff.devs_desc[i].netdev_name)) { + ff_notifier_event_dev(dev, event, i); + mutex_unlock(&ff_notifier_mutex); + return 0; + } + } + + /* + * check for bridge/fbxbridge match + * + * bridge can change up/down status, but lower netdev will not get + * CHANGE_UPPER + */ + if (netif_is_bridge_master(dev) || netif_is_fbxbridge_master(dev)) { + size_t i; + + for (i = 0; i < ARRAY_SIZE(ff.devs_desc); i++) { + struct ff_dev_ctx *ff_dev = &ff.devs[i]; + const char *bridge_name = ff.devs_desc[i].bridge_name; + + if (!bridge_name) + continue; + + if (!ff_dev->netdev) + continue; + + if (!ff_dev->active) { + if (!ff_dev_resolve_bridge(ff_dev, + bridge_name)) + ff_dev_mark_active(ff_dev); + } else { + if (!ff_dev_bridge_is_up(ff_dev)) + ff_dev_mark_inactive(ff_dev); + } + } + } + + /* + * check for real_dev match + */ + for (i = 0; i < ARRAY_SIZE(ff.devs); i++) { + if (dev == ff.devs[i].real_netdev) + ff_notifier_event_dev(ff.devs[i].netdev, event, i); + } + + mutex_unlock(&ff_notifier_mutex); + return 0; +} + +static int ff_notifier_event_cb(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct net_device *dev = netdev_notifier_info_to_dev(ptr); + + if (!net_eq(dev_net(dev), &init_net)) + return 0; + + ff_notifier_event(dev, event); + return 0; +} + +/* + * ipv4 forward cache private data + */ +struct ff_priv { + struct in6_addr tun_dest_ip6; + struct dst_entry *tun_dst; +}; + +static void ff_priv_release(const struct ff_priv *priv) +{ + dst_release(priv->tun_dst); +} + +static void ff_priv_destructor_cb(void *data) +{ + const struct ff_priv *priv = (const struct ff_priv *)data; + ff_priv_release(priv); +} + +static const struct ff_priv *ffn_get_ro_priv(const struct ffn_lookup_entry *e) +{ + if (e->manip.priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (const struct ff_priv *)e->manip.ffn_priv_area; +} + +static struct ff_priv *ffn_get_rw_priv(struct ffn_lookup_entry *e) +{ + BUILD_BUG_ON(sizeof (e->manip.ffn_priv_area) < + sizeof (struct ff_priv)); + + if (e->manip.priv_destructor && + e->manip.priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (struct ff_priv *)e->manip.ffn_priv_area; +} + +static const struct ff_priv *fwc_get_ro_priv(const struct fbxbr_fwcache *fwc) +{ + if (fwc->priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (const struct ff_priv *)fwc->priv_area; +} + +static struct ff_priv *fwc_get_rw_priv(const struct fbxbr_fwcache *fwc) +{ + BUILD_BUG_ON(sizeof (fwc->priv_area) < sizeof (struct ff_priv)); + + if (fwc->priv_destructor && + fwc->priv_destructor != ff_priv_destructor_cb) + return NULL; + + return (struct ff_priv *)fwc->priv_area; +} + +/* + * ipv6 forward cache private data + */ +struct ff6_priv { + u32 tun_dest_ip; + struct dst_entry *tun_dst; +}; + +static void ff6_priv_release(const struct ff6_priv *priv) +{ + dst_release(priv->tun_dst); +} + +static void ff6_priv_destructor_cb(void *data) +{ + const struct ff6_priv *priv = (const struct ff6_priv *)data; + ff6_priv_release(priv); +} + +static const struct ff6_priv *ffn6_get_ro_priv(const struct ffn6_lookup_entry *e6) +{ + if (e6->manip.priv_destructor != ff6_priv_destructor_cb) + return NULL; + + return (const struct ff6_priv *)e6->manip.ffn_priv_area; +} + +static struct ff6_priv *ffn6_get_rw_priv(struct ffn6_lookup_entry *e6) +{ + BUILD_BUG_ON(sizeof (e6->manip.ffn_priv_area) < + sizeof (struct ff6_priv)); + + if (e6->manip.priv_destructor && + e6->manip.priv_destructor != ff6_priv_destructor_cb) + return NULL; + + return (struct ff6_priv *)e6->manip.ffn_priv_area; +} + + +/* + * + */ +static u32 ff_tun_extract_6rd_addr(const struct in6_addr *d) +{ + u32 a1, a2; + + a1 = ntohl(d->s6_addr32[0] & ~ff.tun.u.sit.s6rd_pmask); + a1 <<= ff.tun.u.sit.s6rd_plen; + + a2 = ntohl(d->s6_addr32[1] & ff.tun.u.sit.s6rd_pmask); + a2 >>= (32 - ff.tun.u.sit.s6rd_plen); + return htonl(a1 | a2); +} + +/* + * + */ +static void ff_tun_gen_mape_addr(u32 addr, u16 port, struct in6_addr *dest) +{ + u32 eabits; + u16 psid; + + eabits = ntohl(addr & ff.tun.u.map.ea_addr_mask) << ff.tun.u.map.psid_len; + psid = 0; + if (ff.tun.u.map.psid_len) { + psid = ntohs(port & ff.tun.u.map.ea_port_mask) >> + (16 - ff.tun.u.map.psid_len); + eabits |= psid; + } + + memcpy(dest, &ff.tun.u.map.ipv6_prefix, 8); + dest->s6_addr32[1] |= htonl(eabits << ff.tun.u.map.ea_lshift); + + dest->s6_addr32[2] = htonl(ntohl(addr) >> 16); + dest->s6_addr32[3] = htonl((ntohl(addr) << 16) | psid); +} + +/* + * broadcom DSA + */ +#define BRCM_TAG_LEN 4 + +#define BRCM_OPCODE_SHIFT 5 +#define BRCM_OPCODE_MASK 0x7 + +struct ff_pkt_info { + __be16 vlan_id; + u8 is_dsa:1; + u8 dsa_port:3; + u8 is_ipv4:1; + u8 l3_hdr_offset; + u16 l3_plen; +}; + +/* 2nd byte in the tag */ +#define BRCM_EG_CID_MASK 0xff + +/* 3rd byte in the tag */ +#define BRCM_EG_RC_MASK 0xff +#define BRCM_EG_RC_RSVD (3 << 6) +#define BRCM_EG_RC_EXCEPTION (1 << 5) +#define BRCM_EG_RC_PROT_SNOOP (1 << 4) +#define BRCM_EG_RC_PROT_TERM (1 << 3) +#define BRCM_EG_RC_SWITCH (1 << 2) +#define BRCM_EG_RC_MAC_LEARN (1 << 1) +#define BRCM_EG_RC_MIRROR (1 << 0) +#define BRCM_EG_TC_SHIFT 5 +#define BRCM_EG_TC_MASK 0x7 +#define BRCM_EG_PID_MASK 0x1f + +/* + * + */ +static bool ff_send(struct bcm_enet_runner_priv *priv, + struct tx_queue *txq, + u32 dma_buf_addr, + void *frag, + u32 frag_size, + unsigned int send_len, + int extra_pad_len) +{ + const struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + struct tx_desc *tx_desc; + unsigned int cur_desc, next_desc; + u32 flags_len; + + /* make sure we have room */ + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + if (WARN_ON(unlikely(next_desc == txq->tx_dirty_desc))) + return 1; + + /* pad small packets (add more for DSA packets) */ + if (send_len < 60 + extra_pad_len) + send_len = 60 + extra_pad_len; + + dma_sync_single_for_device(priv->netdev->dev.parent, + dma_buf_addr, + send_len, + DMA_TO_DEVICE); + + txq->tx_desc_pdata[cur_desc].data = frag; + txq->tx_desc_pdata[cur_desc].len = frag_size; + + /* point to the next available desc */ + txq->tx_cur_desc = next_desc; + + /* update descriptor index */ + flags_len = CPU_TX_DESC0_HW_OWNED_MASK | + (send_len << CPU_TX_DESC0_LEN_SHIFT); + + fftxdbg("ffxmit[%s/q%u]: desc_idx:%u frag:%pS len:%u size:%u\n", + priv->netdev->name, + txq->index, + cur_desc, frag, send_len, frag_size); + + tx_desc = &txq->tx_desc_area[cur_desc]; + tx_desc->address = cpu_to_be32(dma_buf_addr); + wmb(); + tx_desc->flags_len = cpu_to_be32(flags_len); + wmb(); + + bcm_xrdp_api_wakeup(priv->xrdp, + params->tx_core_id, + params->txq_wakeup_thread[0]); + + return 0; +} + +/* + * + */ +static int ff_parse_packet(struct bcm_enet_runner_priv *port, + struct ff_pkt_info *info, + const void *frag, + size_t offset, + size_t eth_len) +{ + const struct ethhdr *eth; + const uint16_t *proto; + + eth = (const struct ethhdr *)((uint8_t *)frag + offset); + + /* extract DSA info */ + if (netdev_uses_dsa(port->netdev)) { + const u8 *brcm_tag; + + brcm_tag = (const u8 *)ð->h_proto; + + if (unlikely((brcm_tag[0] >> BRCM_OPCODE_SHIFT) & BRCM_OPCODE_MASK)) + return 1; + + if (unlikely(brcm_tag[2] & BRCM_EG_RC_RSVD)) + return 1; + + info->is_dsa = 1; + info->dsa_port = brcm_tag[3] & BRCM_EG_PID_MASK; + proto = (const uint16_t *)(brcm_tag + BRCM_TAG_LEN); + eth_len -= BRCM_TAG_LEN; + } else + proto = (const uint16_t *)ð->h_proto; + + if (*proto == htons(ETH_P_8021Q)) { + const struct vlan_hdr *vhdr; + + vhdr = (const struct vlan_hdr *)(proto + 1); + info->vlan_id = vhdr->h_vlan_TCI; + + proto = (const uint16_t *)&vhdr->h_vlan_encapsulated_proto; + info->l3_hdr_offset = (const void *)(vhdr + 1) - (const void *)eth; + info->l3_plen = eth_len - VLAN_ETH_HLEN; + } else { + info->vlan_id = 0; + info->l3_hdr_offset = (const void *)(proto + 1) - (const void *)eth; + info->l3_plen = eth_len - ETH_HLEN; + } + + if (*proto == htons(ETH_P_IP)) { + if (info->l3_plen < sizeof (struct iphdr)) + return 1; + info->is_ipv4 = 1; + return 0; + } + + info->is_ipv4 = 0; + if (*proto == htons(ETH_P_IPV6)) { + if (info->l3_plen < sizeof (struct ipv6hdr)) + return 1; + return 0; + } + + return 1; +} + +enum ff_xmit_mode { + FF_XMIT_IPV4, + FF_XMIT_IPV6, + FF_XMIT_IPV6_IN_IPV4, + FF_XMIT_IPV4_IN_IPV6, +}; + +/* + * + */ +static bool ff_receive(struct bcm_enet_runner_priv *rx_port, + struct rx_queue *rxq, + unsigned int rx_desc_idx, + void *frag, + size_t frag_size, + size_t offset, size_t eth_len) +{ + struct rx_desc *rx_desc; + struct ff_pkt_info pinfo; + struct ethhdr *eth; + struct bcm_enet_runner_priv *tx_port; + struct net_device_stats *tx_hw_stats; + struct net_device *last_rx_dev, *next_tx_dev; + struct ffn_lookup_entry *e = NULL; + struct ffn6_lookup_entry *e6 = NULL; + struct nf_conn *ct = NULL; + enum ff_xmit_mode xmit_mode; + const struct in6_addr *tun_v6_pdest = NULL; + struct net_device *tx_dev; + struct ff_dev_ctx *tx_ff_dev, *rx_ff_dev; + u32 tun_v4_dest = 0; + u8 dest_hw[6]; + u32 buf_addr; + unsigned int timeout; + void *l2_hdr, *l3_hdr, *l4_hdr; + bool l3_is_ipv4, l4_is_tcp; + u16 proto; + u16 *pproto; + size_t i, rx_ff_dev_idx, tx_ff_dev_idx; + bool parsed; + void *new_frag; + + /* make sure we have headroom for the worst case scenario */ + BUILD_BUG_ON(NET_SKB_PAD < + (sizeof (struct ipv6hdr) + VLAN_HLEN + BRCM_TAG_LEN)); + + if (!ff_enabled) + return false; + + if (eth_len < ETH_HLEN) + return false; + + /* locate rx ff device */ + parsed = false; + for (i = 0; i < ARRAY_SIZE(ff.devs); i++) { + if (!ff.devs[i].active) + continue; + + if (ff.devs[i].hw_id != rx_port->ff_hw_id) + continue; + + /* candidate, fully parse packet */ + if (!parsed && + ff_parse_packet(rx_port, &pinfo, frag, offset, eth_len)) + return false; + + parsed = true; + + /* make sure this is the right device */ + if (ff.devs[i].use_dsa) { + if (!pinfo.is_dsa) + continue; + + if (ff.devs[i].dsa_port != pinfo.dsa_port) + continue; + } + + if (ff.devs[i].vlan_id != pinfo.vlan_id) + continue; + + /* device match! */ + break; + } + + if (i == ARRAY_SIZE(ff.devs)) + return false; + + rx_ff_dev_idx = i; + rx_ff_dev = &ff.devs[rx_ff_dev_idx]; + last_rx_dev = rx_ff_dev->netdev; + + /* find opposing device */ + if (rx_ff_dev_idx == FF_DEV_WAN) { + if (!ff.devs[FF_DEV_LAN_LAST].active) + return false; + + /* XXX: to get bridge/fbxbridge device, assume to be + * the same on all devices, real tx dev not yet + * known */ + if (!ff.devs[FF_DEV_LAN_LAST].fbxbr_port) + tx_dev = ff.devs[FF_DEV_LAN_LAST].br_netdev; + else + tx_dev = ff.devs[FF_DEV_LAN_LAST].netdev; + } else { + if (!ff.devs[FF_DEV_WAN].active) + return false; + + tx_dev = ff.devs[FF_DEV_WAN].netdev; + } + + if (WARN_ON(!tx_dev)) + return false; + + /* make sure packet is for our mac address */ + eth = (struct ethhdr *)((uint8_t *)frag + offset); + if (memcmp(eth->h_dest, ff.devs[i].hwaddr, 6)) + return false; + + l3_is_ipv4 = pinfo.is_ipv4; + l3_hdr = (u8 *)eth + pinfo.l3_hdr_offset; + + if (l3_is_ipv4) { + struct iphdr *iph; + struct fbxbr_fwcache *fwc; + struct fbxbr *fbxbr = NULL; + struct fbxbr_port *fbxbr_fwd_port = NULL; + u16 sport, dport; + u8 ip_proto; + +handle_ipv4: + iph = (struct iphdr *)l3_hdr; + + /* lookup IP ffn entry */ + if (iph->ihl > 5 || (iph->frag_off & htons(IP_MF | IP_OFFSET))) + return false; + + if (iph->ttl <= 1) + return false; + + ip_proto = iph->protocol; + if (ip_proto == IPPROTO_TCP) { + struct tcphdr *tcph; + + if (pinfo.l3_plen < sizeof (*iph) + sizeof (*tcph)) + return false; + + tcph = (struct tcphdr *)((u8 *)iph + 20); + if (tcph->fin || + tcph->syn || + tcph->rst || + !tcph->ack) { + return false; + } + + sport = tcph->source; + dport = tcph->dest; + l4_hdr = tcph; + l4_is_tcp = true; + + } else if (ip_proto == IPPROTO_UDP) { + struct udphdr *udph; + + if (pinfo.l3_plen < sizeof (*iph) + sizeof (*udph)) + return false; + + udph = (struct udphdr *)((u8 *)iph + 20); + sport = udph->source; + dport = udph->dest; + l4_hdr = udph; + l4_is_tcp = false; + + } else if (ip_proto == IPPROTO_IPV6) { + struct ipv6hdr *ip6hdr; + u32 ip6rd_daddr; + + if (!ff.tun.active) + return false; + + /* must be for us */ + if (iph->daddr != ff.tun.u.sit.src) + return false; + + /* check len */ + if (pinfo.l3_plen < sizeof (struct iphdr) + + sizeof (struct ipv6hdr)) + return false; + + ip6hdr = (struct ipv6hdr *)(iph + 1); + + /* must belong to 6rd prefix */ + if ((ip6hdr->daddr.s6_addr32[0] & + ff.tun.u.sit.s6rd_pmask) != ff.tun.u.sit.s6rd_prefix) + return false; + + /* 6rd address */ + ip6rd_daddr = ff_tun_extract_6rd_addr(&ip6hdr->daddr); + if (ip6rd_daddr != ff.tun.u.sit.src) + return false; + + /* TODO: should check for spoofing here */ + l3_hdr = ip6hdr; + pinfo.l3_plen -= 20; + l3_is_ipv4 = false; + goto handle_ipv6; + + } else + return false; + + if (netif_is_fbxbridge_port(last_rx_dev)) { + struct fbxbr_fwcache_key k; + struct fbxbr_port *p; + u32 hash; + + p = fbxbr_port_get_rcu(last_rx_dev); + fbxbr = p->br; + + if (p->is_wan) { + k.wan_ip = iph->saddr; + k.lan_ip = iph->daddr; + k.wan_port = sport; + k.lan_port = dport; + fbxbr_fwd_port = fbxbr->lan_port; + } else { + k.lan_ip = iph->saddr; + k.wan_ip = iph->daddr; + k.lan_port = sport; + k.wan_port = dport; + fbxbr_fwd_port = fbxbr->wan_port; + } + k.is_tcp = l4_is_tcp; + + if (!unlikely(fbxbr_fwd_port)) + return false; + + hash = fbxbr_fwcache_hash(&k); + fwc = __fbxbr_fwcache_lookup(p->br, hash, &k); + if (!fwc) + return false; + + next_tx_dev = fbxbr_fwd_port->dev; + e = NULL; + } else { + e = __ffn_get(iph->saddr, iph->daddr, + sport, dport, l4_is_tcp); + if (!e) + return false; + + if (e->manip.dst->obsolete > 0) + return false; + + ct = e->manip.ct; + + /* only fast forward TCP connections in established state */ + if (l4_is_tcp && + ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) + return false; + + next_tx_dev = e->manip.dst->dev; + fwc = NULL; + } + + /* find out if the packet is to be sent as-is or + * tunneled */ + if (ff.tun.netdev && next_tx_dev == ff.tun.netdev) { + const struct ff_priv *ff_priv; + struct ff_priv *ff_wpriv; + struct dst_entry *v6_dst; + const struct in6_addr *pdest, *nexthop; + struct in6_addr dest; + struct rt6_info *rt6; + struct neighbour *neigh; + + /* IPv4 tunneled into MAP-E device */ + if (!ff.tun.active) { + return false; + } + + if (pinfo.l3_plen > ff.tun.mtu) + return false; + + /* lookup ipv6 route cache */ + if (e) + ff_priv = ffn_get_ro_priv(e); + else + ff_priv = fwc_get_ro_priv(fwc); + + if (ff_priv) { + if (ff_priv->tun_dst->obsolete < 0) { + /* valid route found */ + v6_dst = ff_priv->tun_dst; + pdest = &ff_priv->tun_dest_ip6; + goto cached_ipv6_route; + } + + ff_priv_release(ff_priv); + if (e) + e->manip.priv_destructor = NULL; + else + fwc->priv_destructor = NULL; + } + + /* cache miss, compute IPv6 destination */ + if (ff.tun.u.map.ipv4_prefix && + (iph->daddr & ff.tun.u.map.ipv4_pmask) == + ff.tun.u.map.ipv4_prefix) { + /* compute dest using FMR */ + ff_tun_gen_mape_addr(iph->daddr, dport, &dest); + pdest = &dest; + } else { + /* next hop is BR */ + pdest = &ff.tun.u.map.br; + } + + /* v6 route lookup */ + rt6 = rt6_lookup(&init_net, pdest, NULL, 0, NULL, 0); + if (!rt6) + return false; + + if (e) + ff_wpriv = ffn_get_rw_priv(e); + else + ff_wpriv = fwc_get_rw_priv(fwc); + if (!ff_wpriv) + return false; + + /* cache this inside FFN private area */ + ff_wpriv->tun_dst = (struct dst_entry *)rt6; + memcpy(&ff_wpriv->tun_dest_ip6, pdest, 16); + if (e) + e->manip.priv_destructor = ff_priv_destructor_cb; + else + fwc->priv_destructor = ff_priv_destructor_cb; + ff_priv = ff_wpriv; + + v6_dst = (struct dst_entry *)rt6; + +cached_ipv6_route: + if (v6_dst->dev != tx_dev) { + return false; + } + + /* is the neighboor ready ? */ + rt6 = (struct rt6_info *)v6_dst; + nexthop = rt6_nexthop(rt6, (struct in6_addr *)pdest); + if (!nexthop) { + return false; + } + + neigh = __ipv6_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + xmit_mode = FF_XMIT_IPV4_IN_IPV6; + tun_v6_pdest = &ff_priv->tun_dest_ip6; + + } else if (next_tx_dev == tx_dev) { + struct neighbour *neigh; + const struct rtable *rt; + + /* is the neighboor ready ? */ + if (e) { + u32 nexthop; + + rt = (const struct rtable *)e->manip.dst; + nexthop = (__force u32)rt_nexthop(rt, + e->manip.new_dip); + neigh = __ipv4_neigh_lookup_noref(tx_dev, + nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + + memcpy(dest_hw, neigh->ha, 6); + } else { + if (!fbxbr_fwd_port->is_wan) { + if (!fbxbr->have_hw_addr) + return false; + memcpy(dest_hw, fbxbr->lan_hwaddr, 6); + } else { + __be32 nh; + + nh = iph->daddr; + if ((nh & fbxbr->wan_netmask) != + (fbxbr->wan_ipaddr & + fbxbr->wan_netmask)) { + rt = fbxbr_fwd_port->rt; + if (!rt || + rt->dst.obsolete > 0) + return false; + + nh = rt_nexthop(rt, nh); + } + + neigh = __ipv4_neigh_lookup_noref( + tx_dev, nh); + if (!neigh || + !(neigh->nud_state & NUD_VALID)) + return false; + + memcpy(dest_hw, neigh->ha, 6); + } + } + + xmit_mode = FF_XMIT_IPV4; + } else + return false; + + } else { + struct ipv6hdr *ip6hdr; + u16 sport, dport; + u8 ip_proto; + +handle_ipv6: + ip6hdr = (struct ipv6hdr *)l3_hdr; + + if (ip6hdr->hop_limit <= 1 || !ip6hdr->payload_len) + return false; + + if (ntohs(ip6hdr->payload_len) > pinfo.l3_plen) + return false; + + ip_proto = ip6hdr->nexthdr; + + if (ip_proto == IPPROTO_TCP) { + struct tcphdr *tcph; + + if (pinfo.l3_plen < sizeof (*ip6hdr) + sizeof (*tcph)) + return false; + + tcph = (struct tcphdr *)((u8 *)ip6hdr + + sizeof (*ip6hdr)); + + if (tcph->fin || + tcph->syn || + tcph->rst || + !tcph->ack) { + return false; + } + + sport = tcph->source; + dport = tcph->dest; + l4_hdr = tcph; + l4_is_tcp = true; + + } else if (ip_proto == IPPROTO_UDP) { + struct udphdr *udph; + + if (pinfo.l3_plen < sizeof (*ip6hdr) + sizeof (*udph)) + return false; + + udph = (struct udphdr *)((u8 *)ip6hdr + + sizeof (*ip6hdr)); + sport = udph->source; + dport = udph->dest; + l4_hdr = udph; + l4_is_tcp = false; + + } else if (ip_proto == IPPROTO_IPIP) { + struct iphdr *iph; + + if (!ff.tun.active) + return false; + + /* must be for us */ + if (memcmp(&ip6hdr->daddr, &ff.tun.u.map.src, 16)) + return false; + + /* check len */ + if (pinfo.l3_plen < sizeof (struct iphdr) + + sizeof (struct ipv6hdr)) + return false; + + iph = (struct iphdr *)(ip6hdr + 1); + + /* does it come from BR ? */ + if (memcmp(&ip6hdr->saddr, &ff.tun.u.map.br, 16)) { + struct in6_addr exp_src_addr; + + /* no, check FMR for spoofing */ + if (!ff.tun.u.map.ipv4_prefix) + return false; + + /* check up to PSID to reduce lookup + * depth */ + ff_tun_gen_mape_addr(iph->saddr, 0, + &exp_src_addr); + if (!ipv6_prefix_equal(&ip6hdr->saddr, + &exp_src_addr, + ff.tun.u.map.ipv6_plen + + ff.tun.u.map.ipv4_plen)) + return false; + } + + last_rx_dev = ff.tun.netdev; + if (!last_rx_dev) + return false; + + l3_hdr = iph; + pinfo.l3_plen -= sizeof (*ip6hdr); + l3_is_ipv4 = true; + goto handle_ipv4; + + } else + return false; + + e6 = __ffn6_get(ip6hdr->saddr.s6_addr32, + ip6hdr->daddr.s6_addr32, + sport, dport, l4_is_tcp); + + if (!e6) { + return false; + } + + if (e6->manip.dst->obsolete > 0) { + return false; + } + + ct = e6->manip.ct; + + /* only fast forward TCP connections in established state */ + if (l4_is_tcp && + ct->proto.tcp.state != TCP_CONNTRACK_ESTABLISHED) { + return false; + } + + /* find out if the packet is to be sent as-is or + * tunneled */ + if (ff.tun.netdev && e6->manip.dst->dev == ff.tun.netdev) { + const struct ff6_priv *ff6_priv; + struct ff6_priv *ff6_wpriv; + struct dst_entry *v4_dst; + struct flowi4 fl4; + struct rtable *rt; + struct neighbour *neigh; + u32 dest, nexthop; + + /* IPv6 tunneled into SIT device using 6rd */ + if (!ff.tun.active) { + return false; + } + + if (pinfo.l3_plen > ff.tun.mtu) + return false; + + /* lookup ipv4 route cache */ + ff6_priv = ffn6_get_ro_priv(e6); + if (ff6_priv) { + if (!ff6_priv->tun_dst->obsolete) { + /* valid route found */ + v4_dst = ff6_priv->tun_dst; + dest = ff6_priv->tun_dest_ip; + goto cached_ipv4_route; + } + + ff6_priv_release(ff6_priv); + e6->manip.priv_destructor = NULL; + } + + /* cache miss, compute IPv4 destination */ + if ((ip6hdr->daddr.s6_addr32[0] & + ff.tun.u.sit.s6rd_pmask) == ff.tun.u.sit.s6rd_prefix) { + /* next hop via prefix */ + dest = ff_tun_extract_6rd_addr(&ip6hdr->daddr); + } else { + const struct in6_addr *nh6; + struct rt6_info *rt6; + + /* next hop via route */ + rt6 = (struct rt6_info *)e6->manip.dst; + nh6 = rt6_nexthop(rt6, + (struct in6_addr *)e6->manip.new_dip); + if (!nh6) { + return false; + } + + /* should be a v4 mapped */ + if (nh6->s6_addr32[0] != 0 || + nh6->s6_addr32[1] != 0 || + nh6->s6_addr32[2] != 0) { + return false; + } + + dest = nh6->s6_addr32[3]; + } + + /* v4 route lookup */ + rt = ip_route_output_ports(&init_net, &fl4, NULL, + dest, ff.tun.u.sit.src, + 0, 0, + IPPROTO_IPV6, 0, + 0); + if (IS_ERR(rt) || + rt->rt_type != RTN_UNICAST) + return false; + + ff6_wpriv = ffn6_get_rw_priv(e6); + if (!ff6_wpriv) + return false; + + /* cache this inside FFN private area */ + ff6_wpriv->tun_dst = (struct dst_entry *)rt; + ff6_wpriv->tun_dest_ip = dest; + e6->manip.priv_destructor = ff6_priv_destructor_cb; + + v4_dst = (struct dst_entry *)rt; + ff6_priv = ff6_wpriv; + +cached_ipv4_route: + if (v4_dst->dev != tx_dev) { + return false; + } + + /* is the neighboor ready ? */ + rt = (struct rtable *)v4_dst; + nexthop = (__force u32)rt_nexthop(rt, dest); + neigh = __ipv4_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + tun_v4_dest = dest; + xmit_mode = FF_XMIT_IPV6_IN_IPV4; + + } else if (e6->manip.dst->dev == tx_dev) { + const struct in6_addr *nexthop; + struct rt6_info *rt6; + struct neighbour *neigh; + + /* is the neighboor ready ? */ + rt6 = (struct rt6_info *)e6->manip.dst; + + nexthop = rt6_nexthop(rt6, + (struct in6_addr *)e6->manip.new_dip); + if (!nexthop) + return false; + + neigh = __ipv6_neigh_lookup_noref(tx_dev, nexthop); + if (!neigh || !(neigh->nud_state & NUD_VALID)) + return false; + memcpy(dest_hw, neigh->ha, 6); + + xmit_mode = FF_XMIT_IPV6; + } else + return false; + } + + /* compute outgoing device */ + if (rx_ff_dev_idx != FF_DEV_WAN) { + tx_ff_dev = &ff.devs[FF_DEV_WAN]; + tx_ff_dev_idx = FF_DEV_WAN; + + } else if (ff.devs[FF_DEV_LAN_LAST].br_port) { + struct net_bridge_port *br_port; + struct net_bridge_fdb_entry *fdb; + + /* XXX get reference to bridge using last lan port */ + br_port = ff.devs[FF_DEV_LAN_LAST].br_port; + fdb = br_fdb_find_rcu(br_port->br, dest_hw, 0); + if (!fdb) + return false; + + tx_ff_dev = NULL; + for (i = 0; i < ARRAY_SIZE(ff.devs); i++) { + if (!ff.devs[i].active) + continue; + if (ff.devs[i].br_port == fdb->dst) { + tx_ff_dev = &ff.devs[i]; + break; + } + } + + if (!tx_ff_dev) { + return false; + } + + tx_ff_dev_idx = i; + + } else if (ff.devs[FF_DEV_LAN_LAST].fbxbr_port) { + tx_ff_dev = &ff.devs[FF_DEV_LAN_LAST]; + tx_ff_dev_idx = FF_DEV_LAN_LAST; + } else + return false; + + /* update rx statistics */ + if (rx_ff_dev_idx != FF_DEV_WAN && rx_ff_dev->br_port) { + struct net_bridge *br; + struct net_bridge_port *p; + struct pcpu_sw_netstats *stats; + + /* packet comes from a bridge, make sure we are + * allowed to ingress it */ + p = rx_ff_dev->br_port; + if (p->state != BR_STATE_FORWARDING) + return false; + + /* refresh FDB entry for this source */ + br = netdev_priv(rx_ff_dev->br_netdev); + if (!br_fdb_update_only(br, p, eth->h_source)) + return false; + + stats = this_cpu_ptr(br->stats); + stats->rx_packets++; + stats->rx_bytes += eth_len; + + } + + if (rx_ff_dev->vlan_id) { + struct vlan_dev_priv *vlan = vlan_dev_priv(rx_ff_dev->netdev); + struct vlan_pcpu_stats *stats; + stats = this_cpu_ptr(vlan->vlan_pcpu_stats); + stats->rx_packets++; + stats->rx_bytes += eth_len; + } else { + rx_ff_dev->netdev->stats.rx_packets++; + rx_ff_dev->netdev->stats.rx_bytes += eth_len; + } + + rx_desc = &rxq->rx_desc_area[rx_desc_idx]; + + /* do we have room in the tx queue ? */ + if (tx_ff_dev->is_hardware) { + tx_port = ff.ports_by_hw_id[tx_ff_dev->hw_id]; + + /* XXX: no lock here, we only race with reclaim + * thread, which will at worst make the queue non + * full */ + if (__ff_tx_queue_full(tx_port->ff_txq) && + !__ff_tx_queue_can_reclaim(tx_port->ff_txq)) { + /* just rearm descriptor and fake success */ + u32 flags; + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (rx_port->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + return true; + } + } else + tx_port = NULL; + + /* can we allocate a new fragment to replace the descriptor we + * are about to use ? */ + if (tx_ff_dev->is_hardware) { + /* remember RX desc hw address before we reload it and + * point if back to frag hw address */ + buf_addr = be32_to_cpu(rx_desc->address); + buf_addr -= offset; + new_frag = ff_reclaim_any_sent_frag(rx_port->pkt_size, + rx_ff_dev_idx, + tx_ff_dev_idx); + } else { + buf_addr = 0; + new_frag = NULL; + } + + if (rxq_refill_desc(rx_port, rxq, rx_desc_idx, true, new_frag)) { + /* just rearm descriptor and fake success */ + u32 flags; + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (rx_port->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + return true; + } + + if (ct && l4_is_tcp) { + /* don't try to track window anymore on this + * connection */ + ct->proto.tcp.no_window_track = 1; + } + + /* alter l3 & l4 content if needed (routing only) */ + if (l3_is_ipv4 && e) { + struct iphdr *iph = (struct iphdr *)l3_hdr; + + if (e->manip.alter) { + if (l4_is_tcp) { + struct tcphdr *tcph = (struct tcphdr *)l4_hdr; + tcph->source = e->manip.new_sport; + tcph->dest = e->manip.new_dport; + tcph->check = csum16_sub(tcph->check, + e->manip.l4_adjustment); + } else { + struct udphdr *udph = (struct udphdr *)l4_hdr; + udph->source = e->manip.new_sport; + udph->dest = e->manip.new_dport; + if (udph->check) { + u16 tcheck; + + tcheck = csum16_sub(udph->check, + e->manip.l4_adjustment); + udph->check = tcheck ? tcheck : 0xffff; + } + } + + iph->saddr = e->manip.new_sip; + iph->daddr = e->manip.new_dip; + } + + iph->ttl--; + iph->check = csum16_sub(iph->check, + e->manip.ip_adjustment); + + } else if (!l3_is_ipv4 && e6) { + struct ipv6hdr *ip6hdr = (struct ipv6hdr *)l3_hdr; + + if (e6->manip.alter) { + if (l4_is_tcp) { + struct tcphdr *tcph = (struct tcphdr *)l4_hdr; + tcph->source = e6->manip.new_sport; + tcph->dest = e6->manip.new_dport; + tcph->check = csum16_sub(tcph->check, + e6->manip.adjustment); + } else { + struct udphdr *udph = (struct udphdr *)l4_hdr; + udph->source = e6->manip.new_sport; + udph->dest = e6->manip.new_dport; + + if (udph->check) { + u16 tcheck; + + tcheck = csum16_sub(udph->check, + e6->manip.adjustment); + udph->check = tcheck ? tcheck : 0xffff; + } + } + + memcpy(ip6hdr->saddr.s6_addr32, e6->manip.new_sip, 16); + memcpy(ip6hdr->daddr.s6_addr32, e6->manip.new_dip, 16); + } + + ip6hdr->hop_limit--; + } + + /* packet is ready to xmit */ + switch (xmit_mode) { + case FF_XMIT_IPV4: + proto = ETH_P_IP; + break; + + case FF_XMIT_IPV6: + proto = ETH_P_IPV6; + break; + + case FF_XMIT_IPV6_IN_IPV4: + { + struct iphdr *tun_hdr; + /* prepend IPv4 */ + tun_hdr = (struct iphdr *)((u8 *)l3_hdr - sizeof (*tun_hdr)); + tun_hdr->ihl = 5; + tun_hdr->version = 4; + tun_hdr->tos = 0; + tun_hdr->tot_len = htons(pinfo.l3_plen + sizeof (*tun_hdr)); + tun_hdr->id = 0; + tun_hdr->frag_off = 0; + tun_hdr->check = 0; + tun_hdr->ttl = 64; + tun_hdr->protocol = IPPROTO_IPV6; + tun_hdr->saddr = ff.tun.u.sit.src; + tun_hdr->daddr = tun_v4_dest; + tun_hdr->check = ip_fast_csum((u8 *)tun_hdr, 5); + + l3_hdr = (u8 *)tun_hdr; + pinfo.l3_plen += sizeof (*tun_hdr); + + proto = ETH_P_IP; + break; + } + + case FF_XMIT_IPV4_IN_IPV6: + { + struct ipv6hdr *tun_6hdr; + + /* prepend IPv6 */ + tun_6hdr = (struct ipv6hdr *)((u8 *)l3_hdr - sizeof (*tun_6hdr)); + tun_6hdr->version = 6; + tun_6hdr->priority = 0; + memset(tun_6hdr->flow_lbl, 0, sizeof (tun_6hdr->flow_lbl)); + tun_6hdr->payload_len = htons(pinfo.l3_plen); + tun_6hdr->nexthdr = IPPROTO_IPIP; + tun_6hdr->hop_limit = 64; + tun_6hdr->saddr = ff.tun.u.map.src; + tun_6hdr->daddr = *tun_v6_pdest; + + l3_hdr = (u8 *)tun_6hdr; + pinfo.l3_plen += sizeof (*tun_6hdr); + + proto = ETH_P_IPV6; + break; + } + } + + /* add vlan header if any */ + l2_hdr = l3_hdr; + if (tx_ff_dev->vlan_id) { + struct vlan_hdr *vhdr; + + l2_hdr -= VLAN_HLEN; + vhdr = (struct vlan_hdr *)l2_hdr; + vhdr->h_vlan_TCI = tx_ff_dev->vlan_id; + vhdr->h_vlan_encapsulated_proto = htons(proto); + proto = ETH_P_8021Q; + } + + /* add protocol */ + l2_hdr -= sizeof (*pproto); + pproto = (u16 *)l2_hdr; + *pproto = htons(proto); + + /* add DSA header if any */ + if (tx_ff_dev->use_dsa) { + u8 *brcm_tag; + + l2_hdr -= BRCM_TAG_LEN; + brcm_tag = (u8 *)l2_hdr; + brcm_tag[0] = (1 << BRCM_OPCODE_SHIFT); + brcm_tag[1] = 0; + brcm_tag[2] = 0; + if (tx_ff_dev->dsa_port == 8) + brcm_tag[2] = (1 << 0); + brcm_tag[3] = (1 << tx_ff_dev->dsa_port); + } + + /* finally add eth dst/src */ + l2_hdr -= ETH_ALEN * 2; + eth = (struct ethhdr *)l2_hdr; + memcpy(eth->h_dest, dest_hw, 6); + memcpy(eth->h_source, tx_ff_dev->hwaddr, 6); + + /* compute final len */ + eth_len = pinfo.l3_plen + (l3_hdr - l2_hdr); + + if (tx_ff_dev->is_hardware) { + if (ff_send(tx_port, + tx_port->ff_txq, + buf_addr + (void *)eth - frag, + frag, + rx_port->pkt_size, + eth_len, + tx_ff_dev->use_dsa ? BRCM_TAG_LEN : 0)) { + skb_free_frag(frag); + return true; + } + + if (tx_ff_dev->vlan_id) { + struct vlan_dev_priv *vlan = vlan_dev_priv(tx_ff_dev->netdev); + struct vlan_pcpu_stats *stats; + stats = this_cpu_ptr(vlan->vlan_pcpu_stats); + stats->tx_packets++; + stats->tx_bytes += eth_len; + } else { + tx_ff_dev->netdev->stats.tx_packets++; + tx_ff_dev->netdev->stats.tx_bytes += eth_len; + } + + if (tx_port->netdev != tx_ff_dev->netdev) { + tx_hw_stats = &tx_port->netdev->stats; + tx_hw_stats->tx_bytes += eth_len; + tx_hw_stats->tx_packets++; + } + } else { + struct sk_buff *skb; + + skb = build_skb(frag, frag_size > PAGE_SIZE ? 0 : frag_size); + if (!skb) { + skb_free_frag(frag); + return true; + } + + skb_reserve(skb, (void *)eth - frag); + skb_put(skb, eth_len); + skb->protocol = eth->h_proto; + skb_set_network_header(skb, l3_hdr - l2_hdr); + skb->dev = tx_ff_dev->netdev; + dev_queue_xmit(skb); + } + + if (tx_ff_dev_idx != FF_DEV_WAN && tx_ff_dev->br_port) { + struct net_bridge *br; + struct pcpu_sw_netstats *stats; + br = netdev_priv(tx_ff_dev->br_netdev); + stats = this_cpu_ptr(br->stats); + stats->tx_packets++; + stats->tx_bytes += eth_len; + } + + /* refresh conntrack */ + if (ct) { + if (l4_is_tcp) + timeout = HZ * 3600 * 24 * 5; + else + timeout = HZ * 180; + + if (ct->timeout - ff.jiffies < timeout - 10 * HZ) { + unsigned long newtime = ff.jiffies + timeout; + ct->timeout = newtime; + } + } + + return true; +} + +/* + * + */ +static ssize_t ff_show_enabled(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%u\n", ff_enabled); +} + +static ssize_t ff_store_enabled(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + if (ff_enabled == val) + return len; + + printk(KERN_NOTICE "ff: fastpath now %s\n", + val ? "enabled" : "disabled"); + ff_enabled = val; + return len; +} + +static struct device_attribute dev_attr_ff = { + .attr = { .name = "ff_enabled", .mode = (S_IRUGO | S_IWUSR) }, + .show = ff_show_enabled, + .store = ff_store_enabled, +}; + +/* + * + */ +static ssize_t ff_show_tun_dev(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%s\n", ff.tun_netdev_name); +} + +static ssize_t ff_store_tun_dev(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + if (!len || buf[0] == '\n') { + ff.tun_netdev_name[0] = 0; + spin_lock_bh(&ff_lock); + __ff_tun_release(); + spin_unlock_bh(&ff_lock); + printk(KERN_NOTICE "ff: tun dev unset\n"); + return len; + } + + spin_lock_bh(&ff_lock); + __ff_tun_release(); + strncpy(ff.tun_netdev_name, buf, len); + strim(ff.tun_netdev_name); + printk(KERN_NOTICE "ff: tun dev set to %s\n", ff.tun_netdev_name); + __ff_tun_capture(); + spin_unlock_bh(&ff_lock); + return len; +} + +static struct device_attribute dev_attr_tun = { + .attr = { .name = "ff_tun_dev", .mode = (S_IRUGO | S_IWUSR) }, + .show = ff_show_tun_dev, + .store = ff_store_tun_dev, +}; + +static void ff_init(struct device *dev) +{ + static bool done; + + if (done) + return; + + device_create_file(dev, &dev_attr_ff); + device_create_file(dev, &dev_attr_tun); + printk(KERN_DEBUG "ff_init\n"); + done = true; +} +#endif + + +/* + * + */ +static void rxq_deinit(struct bcm_enet_runner_priv *priv, struct rx_queue *rxq) +{ + int i; + + for (i = 0; i < rxq->ring_size; i++) { + struct rx_desc *desc; + dma_addr_t addr; + + if (!rxq->frags || !rxq->frags[i]) + continue; + + desc = &rxq->rx_desc_area[i]; + addr = be32_to_cpu(desc->address); + dma_unmap_single(priv->netdev->dev.parent, + addr, + priv->pkt_size, + DMA_FROM_DEVICE); + skb_free_frag(rxq->frags[i]); + } + + if (rxq->rx_desc_area) + dma_free_coherent(priv->netdev->dev.parent, + rxq->rx_desc_area_size, + rxq->rx_desc_area, + rxq->rx_desc_dma); + if (rxq->frags) + kfree(rxq->frags); +} + +/* + * + */ +static int rxq_init(struct bcm_enet_runner_priv *priv, int index) +{ + struct rx_queue *rxq = priv->rxq + index; + int size; + int i; + + memset(rxq, 0, sizeof (*rxq)); + rxq->index = index; + rxq->ring_size = priv->rxq_size; + + size = rxq->ring_size * sizeof (struct rx_desc); + rxq->rx_desc_area_size = size; + rxq->rx_desc_area = dma_alloc_coherent(priv->netdev->dev.parent, + size, &rxq->rx_desc_dma, + GFP_KERNEL); + + if (rxq->rx_desc_area == NULL) { + netdev_err(priv->netdev, + "can't allocate rx ring (%d bytes)\n", size); + goto out; + } + + memset(rxq->rx_desc_area, 0, size); + + rxq->frags = kzalloc(sizeof (*rxq->frags) * rxq->ring_size, GFP_KERNEL); + if (!rxq->frags) { + netdev_err(priv->netdev, "can't allocate rx frags\n"); + goto out; + } + + for (i = 0; i < rxq->ring_size; i++) { + int ret; + + ret = rxq_refill_desc(priv, rxq, i, false, NULL); + if (ret) + goto out; + } + + return 0; + +out: + rxq_deinit(priv, rxq); + return -ENOMEM; +} + +/* + * + */ +static int bcm_runner_do_rx(struct bcm_enet_runner_priv *priv, + struct rx_queue *rxq, int budget) +{ + struct net_device_stats *stats = &priv->netdev->stats; + int rx_done; + u32 rcvd_pkts = 0; + u32 rcvd_bytes = 0; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + spin_lock(&ff_lock); +#endif + + rx_done = 0; + while (rx_done < budget) { + struct rx_desc *rx_desc; + struct sk_buff *skb; + void *frag; + u32 flags; + unsigned int idx, pkt_len; + int ret; + + idx = rxq->rx_curr_desc; + rx_desc = &rxq->rx_desc_area[idx]; + + rmb(); + + flags = be32_to_cpu(rx_desc->flags_len); + + rxdbg("bcm_runner_do_rx: idx:%u flags:0x%08x\n", + idx, flags); + + if ((flags & CPU_RX_DESC0_HW_OWNED_MASK)) + break; + + pkt_len = (flags & CPU_RX_DESC0_LEN_MASK) >> + CPU_RX_DESC0_LEN_SHIFT; + pkt_len -= ETH_FCS_LEN; + frag = rxq->frags[idx]; + + rxq->rx_curr_desc++; + rx_done++; + if (rxq->rx_curr_desc == rxq->ring_size) + rxq->rx_curr_desc = 0; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (ff_receive(priv, + rxq, + idx, + frag, + priv->frag_size, + RX_OFFSET, + pkt_len)) { + + rcvd_pkts++; + rcvd_bytes += pkt_len; + continue; + } +#endif + +#ifdef DBG_RX_DISCARD_ALL + /* re-arm with old buffer */ + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (priv->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + rcvd_pkts++; + rcvd_bytes += pkt_len; + continue; +#endif + + ret = rxq_refill_desc(priv, rxq, idx, true, NULL); + if (ret) { + netdev_err(priv->netdev, "oom while refill\n"); + stats->rx_packets++; + stats->rx_dropped++; + + /* re-arm with old buffer */ + flags = CPU_RX_DESC0_HW_OWNED_MASK | + (priv->pkt_size << CPU_RX_DESC0_LEN_SHIFT); + rx_desc->flags_len = cpu_to_be32(flags); + continue; + } + + /* descriptor is re-armed now */ + skb = build_skb(frag, + priv->frag_size > PAGE_SIZE ? + 0 : priv->frag_size); + if (!skb) { + skb_free_frag(frag); + stats->rx_dropped++; + continue; + } + + skb_reserve(skb, RX_OFFSET); + skb_put(skb, pkt_len); + + rcvd_pkts++; + rcvd_bytes += pkt_len; + skb->protocol = eth_type_trans(skb, priv->netdev); + netif_receive_skb(skb); + } + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + spin_unlock(&ff_lock); +#endif + + if (rcvd_pkts) { + stats->rx_packets += rcvd_pkts; + stats->rx_bytes += rcvd_bytes; + } + + return rx_done; +} + +/* + * try to or force reclaim of transmitted buffers + */ +static int __bcm_runner_tx_reclaim_one(struct bcm_enet_runner_priv *priv, + struct net_device *dev, + struct tx_queue *txq, + int force) +{ + struct tx_desc *desc; + void *pdata_ptr; + dma_addr_t address; + u32 flags_len; + unsigned int dirty_desc; + unsigned int pdata_len; + + if (txq->tx_dirty_desc == txq->tx_cur_desc) { + txdbg("bcm_runner_tx_reclaim[q%d]: reach end of desc to reclaim\n", + txq->index); + return 0; + } + + dirty_desc = txq->tx_dirty_desc; + desc = &txq->tx_desc_area[dirty_desc]; + flags_len = be32_to_cpu(desc->flags_len); + + if (!force && (flags_len & CPU_TX_DESC0_HW_OWNED_MASK)) { + txdbg("bcm_runner_tx_reclaim[q%d]: tx desc %u owned by hw\n", + txq->index, dirty_desc); + return 0; + } + + /* ensure other field of the descriptor were not read before + * we checked ownership */ + rmb(); + + pdata_ptr = txq->tx_desc_pdata[dirty_desc].data; + pdata_len = txq->tx_desc_pdata[dirty_desc].len; + txq->tx_desc_pdata[dirty_desc].data = NULL; + + txdbg("tx_reclaim[q%u]: dirty_desc:%u skb:%pS => free\n", + txq->index, dirty_desc, pdata_ptr); + + address = be32_to_cpu(desc->address); + + dirty_desc++; + if (unlikely(dirty_desc >= txq->ring_size)) + dirty_desc = 0; + + txq->tx_dirty_desc = dirty_desc; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (txq == priv->ff_txq) + skb_free_frag(pdata_ptr); + else +#endif + { + dma_unmap_single(dev->dev.parent, + address, pdata_len, + DMA_TO_DEVICE); + dev_kfree_skb((struct sk_buff *)pdata_ptr); + } + return 1; +} + +/* + * try to or force reclaim of transmitted buffers + */ +static int bcm_runner_tx_reclaim(struct bcm_enet_runner_priv *priv, + struct net_device *dev, + struct tx_queue *txq, + int budget, + int force) +{ + struct netdev_queue *netdev_txq; + unsigned int cur_desc, next_desc; + int released; + + txdbg("bcm_runner_tx_reclaim[q%d]: budget:%u\n", txq->index, budget); + + released = 0; + while (released < budget) { + int done; + + /* We run in a bh and fight against start_xmit, which + * is called with bh disabled */ + spin_lock(&txq->tx_lock); + done = __bcm_runner_tx_reclaim_one(priv, dev, txq, force); + spin_unlock(&txq->tx_lock); + if (!done) + break; + + released++; + } + + if (force || !released) + goto end; + + netdev_txq = netdev_get_tx_queue(dev, txq->index); + if (!netif_tx_queue_stopped(netdev_txq)) + goto end; + + /* recheck in case xmit already filled all available space */ + spin_lock(&txq->tx_lock); + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + if (next_desc != txq->tx_dirty_desc) + netif_tx_wake_queue(netdev_txq); + spin_unlock(&txq->tx_lock); + +end: + return released; +} + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF +static int ff_reclaim_threadfn(void *data) +{ + struct bcm_enet_runner_priv *priv = data; + + set_user_nice(current, MAX_NICE); + + while (!kthread_should_stop()) { + while (!kthread_should_stop()) { + int done = 0; + + if (spin_trylock_bh(&priv->ff_txq->tx_lock)) { + done = __bcm_runner_tx_reclaim_one( + priv, + priv->netdev, + priv->ff_txq, + 0); + spin_unlock_bh(&priv->ff_txq->tx_lock); + } + + if (!done) + break; + schedule(); + } + msleep(10); + } + + return 0; +} +#endif + +/* + * + */ +static u32 collect_work(struct bcm_enet_runner_priv *priv) +{ + const struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 val; + + val = bcm_xrdp_api_irq_read_status(priv->xrdp, params->rx_core_id); + val &= priv->irq_mask; + if (val) { + /* ack */ + bcm_xrdp_api_irq_write_status(priv->xrdp, params->rx_core_id, + val); + (void)bcm_xrdp_api_irq_read_status(priv->xrdp, + params->rx_core_id); + } + return val; +} + +/* + * + */ +int bcm_runner_poll(struct napi_struct *napi, int budget) +{ + struct bcm_enet_runner_priv *priv; + struct net_device *dev; + struct bcm_xrdp_enet_params *params; + int work_done; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff.jiffies = nfct_time_stamp; +#endif + + priv = container_of(napi, struct bcm_enet_runner_priv, napi); + params = &priv->xrdp_params; + dev = priv->netdev; + + work_done = 0; + + txdbg("bcm_runner_poll: enter budget:%d work_todo:%08x work_batch:%08x\n", + budget, priv->work_todo, priv->work_batch); + + while (work_done < budget) { + int small_budget, done, i; + + /* collect work todo */ + if (!priv->work_batch) { + if (!priv->work_todo) { + priv->work_todo = collect_work(priv); + txdbg("bcm_runner_poll: colloect work_todo:%08x\n", + priv->work_todo); + if (!priv->work_todo) + break; + } + + priv->work_batch = priv->work_todo; + } + + txdbg("bcm_runner_poll: loop work_todo:%08x work_batch:%08x\n", + priv->work_todo, priv->work_batch); + + small_budget = budget - work_done; + if (small_budget > 16) + small_budget = 16; + + for (i = 0; i < dev->real_num_tx_queues; i++) { + if (!(priv->work_batch & params->tx_done_irq_mask[i])) + continue; + + txdbg("bcm_runner_poll: tx done work for queue %u\n", i); + priv->work_batch &= ~params->tx_done_irq_mask[i]; + + /* reclaim sent skb */ + done = bcm_runner_tx_reclaim(priv, dev, + &priv->txq[i], + small_budget, 0); + + txdbg("bcm_runner_poll: tx reclaim done => %u\n", done); + /* if we reclaimed everything, clear the work bit */ + if (done < small_budget) + priv->work_todo &= ~params->tx_done_irq_mask[i]; + small_budget -= done; + work_done += done; + } + + if (!small_budget) + continue; + + for (i = 0; i < dev->real_num_rx_queues; i++) { + if (!(priv->work_batch & params->rx_irq_mask[i])) + continue; + + txdbg("bcm_runner_poll: rx done work for queue %u\n", i); + priv->work_batch &= ~params->rx_irq_mask[i]; + + /* do rx */ + done = bcm_runner_do_rx(priv, &priv->rxq[i], + small_budget); + + /* if we reclaimed everything, clear the work bit */ + if (done < small_budget) + priv->work_todo &= ~params->rx_irq_mask[i]; + + small_budget -= done; + work_done += done; + } + } + + if (work_done < budget && !priv->work_todo) { + txdbg("bcm_runner_poll: all work done\n"); + + /* no more packet in rx/tx queue, remove device from + * poll queue */ + napi_complete_done(napi, work_done); + + /* restore rx/tx interrupt */ + bcm_xrdp_api_irq_mask_set(priv->xrdp, + params->rx_core_id, priv->irq_mask); + } + + return work_done; +} + +/* + * + */ +static void txq_deinit(struct bcm_enet_runner_priv *priv, struct tx_queue *txq) +{ + unsigned int i; + + for (i = 0; i < txq->ring_size; i++) { + struct tx_desc *desc; + dma_addr_t addr; + void *pdata_ptr; + unsigned int pdata_len; + + if (!txq->tx_desc_pdata) + continue; + + pdata_ptr = txq->tx_desc_pdata[i].data; + if (!pdata_ptr) + continue; + + pdata_len = txq->tx_desc_pdata[i].len; + desc = &txq->tx_desc_area[i]; + addr = be32_to_cpu(desc->address); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (txq == priv->ff_txq) + skb_free_frag(pdata_ptr); + else +#endif + { + dma_unmap_single(priv->netdev->dev.parent, + addr, pdata_len, + DMA_TO_DEVICE); + dev_kfree_skb((struct sk_buff *)pdata_ptr); + } + + } + + if (txq->tx_desc_area) + dma_free_coherent(priv->netdev->dev.parent, + txq->tx_desc_area_size, + txq->tx_desc_area, + txq->tx_desc_dma); + if (txq->tx_desc_pdata) + kfree(txq->tx_desc_pdata); +} + +/* + * + */ +static int txq_init(struct bcm_enet_runner_priv *priv, int index) +{ + struct tx_queue *txq = priv->txq + index; + int size; + + memset(txq, 0, sizeof (*txq)); + spin_lock_init(&txq->tx_lock); + txq->index = index; + txq->ring_size = priv->txq_size; + + size = txq->ring_size * sizeof (struct tx_desc); + txq->tx_desc_area_size = size; + txq->tx_desc_area = dma_alloc_coherent(priv->netdev->dev.parent, + size, &txq->tx_desc_dma, + GFP_KERNEL); + + if (txq->tx_desc_area == NULL) { + netdev_err(priv->netdev, + "can't allocate tx ring (%d bytes)\n", size); + goto out; + } + + memset(txq->tx_desc_area, 0, size); + + txq->tx_desc_pdata = kzalloc(sizeof (*txq->tx_desc_pdata) * + txq->ring_size, GFP_KERNEL); + if (!txq->tx_desc_pdata) { + netdev_err(priv->netdev, "can't allocate tx skbs ring\n"); + goto out; + } + + return 0; + +out: + txq_deinit(priv, txq); + return -ENOMEM; +} + +/* + * + */ +static u16 bcm_runner_select_queue(struct net_device *dev, struct sk_buff *skb, + struct net_device *sb_dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + u16 queue = skb_get_queue_mapping(skb); + u8 index; + + if (!netdev_uses_dsa(dev)) + return netdev_pick_tx(dev, skb, NULL); + + /* DSA tagging layer will have configured the correct queue */ + index = priv->txq_port_map[BRCM_TAG_GET_PORT(queue)]; + + if (unlikely(index >= priv->txq_count)) + return netdev_pick_tx(dev, skb, NULL); + + return index; +} + +/* + * + */ +static int bcm_runner_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + struct tx_queue *txq; + struct netdev_queue *netdev_txq; + struct tx_desc *desc; + unsigned int cur_desc, next_desc; + dma_addr_t address; + u32 flags_len; + u16 queue; + + if (unlikely((priv->mode_ops->can_send && + !priv->mode_ops->can_send(priv->mode_priv, + ntohs(skb->protocol))))) { + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } + + queue = skb_get_queue_mapping(skb); + netdev_txq = netdev_get_tx_queue(dev, queue); + txq = &priv->txq[queue]; + + if (params->tx_need_batch) + sk_pacing_shift_update(skb->sk, 6); + + /* pad small packets */ + if (skb->len < 60) { + int needed = 60 - skb->len; + char *data; + + if (unlikely(skb_tailroom(skb) < needed)) { + struct sk_buff *nskb; + + nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC); + if (!nskb) + return NETDEV_TX_BUSY; + + dev_kfree_skb(skb); + skb = nskb; + } + data = skb_put_zero(skb, needed); + } + + /* map buffer */ + address = dma_map_single(dev->dev.parent, + skb->data, + skb->len, + DMA_TO_DEVICE); + + if (unlikely(dma_mapping_error(dev->dev.parent, address))) { + netdev_err(dev, "dma_map_single failed\n"); + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } + + /* lock against tx reclaim */ + spin_lock(&txq->tx_lock); + + /* make sure we have room */ + cur_desc = txq->tx_cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + txdbg("runnerxmit[q%u]: cur_desc:%u skb:%pS len:%u\n", + txq->index, + cur_desc, skb, skb->len); + + if (unlikely(next_desc == txq->tx_dirty_desc)) { + /* queue was full */ + netif_tx_stop_queue(netdev_txq); + spin_unlock(&txq->tx_lock); + + netdev_err(dev, "tx queue full unexpected\n"); + dma_unmap_single(dev->dev.parent, + address, + skb->len, + DMA_TO_DEVICE); + dev_kfree_skb(skb); + return NETDEV_TX_OK; + } + + /* point to the next available desc */ + desc = &txq->tx_desc_area[cur_desc]; + txq->tx_desc_pdata[cur_desc].data = skb; + txq->tx_desc_pdata[cur_desc].len = skb->len; + + /* update descriptor index */ + cur_desc = next_desc; + txq->tx_cur_desc = cur_desc; + next_desc = cur_desc + 1; + if (unlikely(next_desc >= txq->ring_size)) + next_desc = 0; + + /* check if queue is now full */ + if (unlikely(next_desc == txq->tx_dirty_desc)) { + txdbg("runnerxmit[q%u]: queue now full (dirty_desc %u)\n", + txq->index, + txq->tx_dirty_desc); + netif_tx_stop_queue(netdev_txq); + } + + /* fill current descriptor */ + flags_len = CPU_TX_DESC0_HW_OWNED_MASK | + (skb->len << CPU_TX_DESC0_LEN_SHIFT); + + desc->address = cpu_to_be32(address); + wmb(); + desc->flags_len = cpu_to_be32(flags_len); + wmb(); + + spin_unlock(&txq->tx_lock); + + /* kick tx dma */ + bcm_xrdp_api_wakeup(priv->xrdp, + params->tx_core_id, + params->txq_wakeup_thread[0]); + + dev->stats.tx_bytes += skb->len; + dev->stats.tx_packets++; + return NETDEV_TX_OK; +} + +/* + * + */ +static irqreturn_t bcm_enet_runner_isr(int irq, void *dev_id) +{ + struct bcm_enet_runner_priv *priv = (struct bcm_enet_runner_priv *)dev_id; + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 val; + + /* check if interrupt is for us */ + val = bcm_xrdp_api_irq_read_status(priv->xrdp, + params->rx_core_id); + txdbg("bcm_enet_runner_isr: val:%08x\n", val); + val &= priv->irq_mask; + if (!val) + return IRQ_NONE; + + /* mask irq */ + bcm_xrdp_api_irq_mask_clear(priv->xrdp, + params->rx_core_id, priv->irq_mask); + napi_schedule(&priv->napi); + return IRQ_HANDLED; +} + +/* + * called when irq affinity is changed from userspace, so we can save + * it and reapply later + */ +static void +bcm_enet_runner_irq_affinity_notify(struct irq_affinity_notify *notify, + const cpumask_t *mask) +{ + struct queue_info *txq_info = + container_of(notify, struct queue_info, affinity_notifier); + cpumask_copy(&txq_info->irq_affinity_mask, mask); +} + +/* + * release callback for irq affinity notifier + */ +static void +bcm_enet_runner_irq_affinity_release(struct kref *ref) +{ +} + +/* + * + */ +static void recalc_frag_size(struct bcm_enet_runner_priv *priv) +{ + /* + * Reserve 14 bytes for an ethernet header + 8 bytes for up + * to two VLAN tags + */ + priv->pkt_size = priv->netdev->mtu + ETH_HLEN + 4 * 2; + + /* + * add NET_SKB_PAD per build_skb() requirement, make sure we + * have room to align data to cache size after reserving + */ + priv->frag_size = priv->pkt_size + RX_OFFSET; + + /* + * per build_skb() requirement + */ + priv->frag_size = (SKB_DATA_ALIGN(priv->frag_size) + + SKB_DATA_ALIGN(sizeof (struct skb_shared_info))); +} + +/* + * + */ +static int bcm_runner_open(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + unsigned int txq_with_irq_count; + struct bcm_dsa_port *dp; + int ret, i, first_queue; + u32 val; + + recalc_frag_size(priv); + + /* cap rxq & txq count to the hardware capabilities */ + if (WARN_ON(params->rx_queue_count > ARRAY_SIZE(priv->rxq))) + return -EINVAL; + + if (WARN_ON(params->tx_queue_count > ARRAY_SIZE(priv->txq))) + return -EINVAL; + + ret = netif_set_real_num_rx_queues(dev, params->rx_queue_count); + if (ret) + return ret; + + priv->txq_count = params->tx_queue_count; + txq_with_irq_count = priv->txq_count; +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + txq_with_irq_count--; + if (WARN_ON(!txq_with_irq_count)) + return -EINVAL; +#endif + + ret = netif_set_real_num_tx_queues(dev, txq_with_irq_count); + if (ret) + return ret; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + priv->ff_reclaim_thread = kthread_create(ff_reclaim_threadfn, + priv, "ff_reclaim_%s", + dev->name); + if (IS_ERR(priv->ff_reclaim_thread)) { + ret = PTR_ERR(priv->ff_reclaim_thread); + priv->ff_reclaim_thread = NULL; + goto out; + } +#endif + + + /* allocate rx rings */ + for (i = 0; i < dev->real_num_rx_queues; i++) { + ret = rxq_init(priv, i); + if (ret) { + while (--i >= 0) + rxq_deinit(priv, priv->rxq + i); + return ret; + } + } + + /* allocate tx rings */ + for (i = 0; i < priv->txq_count; i++) { + ret = txq_init(priv, i); + if (ret) { + while (--i >= 0) + txq_deinit(priv, priv->txq + i); + goto out; + } + } + + /* + * configure txq DSA port queue mapping + * + * for now, use 1 queue per port + */ + i = 0; + list_for_each_entry(dp, &priv->dsa_ports, next) { + struct tx_queue *txq; + + if (i == dev->real_num_tx_queues) { + netdev_warn(dev, "too many DSA ports " + "vs tx queue, ACB flow control " + "will not work correctly\n"); + break; + } + + txq = &priv->txq[i]; + txq->use_dsa = true; + txq->dsa_port = dp->port; + txq->dsa_imp_port = dp->imp_port; + txq->dsa_queue = 0; + netif_set_real_num_tx_queues(dp->slave_netdev, 1); + priv->txq_port_map[dp->port] = i; + i++; + } + + /* assign same dsa data to remaining queues, but the kernel + * should not use them */ + first_queue = i; + if (first_queue) { + struct tx_queue *prev_txq = &priv->txq[first_queue - 1]; + + for (i = first_queue; i < priv->txq_count; i++) { + struct tx_queue *txq = &priv->txq[i]; + txq->use_dsa = prev_txq->use_dsa; + txq->dsa_port = prev_txq->dsa_port; + txq->dsa_imp_port = prev_txq->dsa_imp_port; + txq->dsa_queue = prev_txq->dsa_queue; + } + } + + /* interrupt clear */ + priv->irq_mask = 0; + for (i = 0; i < dev->real_num_rx_queues; i++) + priv->irq_mask |= params->rx_irq_mask[i]; + for (i = 0; i < dev->real_num_tx_queues; i++) + priv->irq_mask |= params->tx_done_irq_mask[i]; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + priv->ff_txq = &priv->txq[priv->txq_count - 1]; +#endif + + bcm_xrdp_api_irq_write_status(priv->xrdp, + params->rx_core_id, priv->irq_mask); + + for (i = 0; i < dev->real_num_rx_queues; i++) { + struct queue_info *rxq_info = &priv->rxq_info[i]; + + scnprintf(rxq_info->irq_name, + sizeof (rxq_info->irq_name), + "%s-rx%u", + dev->name, i); + + ret = request_irq(params->rx_irq[i], + bcm_enet_runner_isr, + 0, rxq_info->irq_name, priv); + if (ret) { + netdev_err(dev, "request_irq failed\n"); + return ret; + } + + rxq_info->affinity_notifier.notify = + bcm_enet_runner_irq_affinity_notify; + rxq_info->affinity_notifier.release = + bcm_enet_runner_irq_affinity_release; + irq_set_affinity_notifier(params->rx_irq[i], + &rxq_info->affinity_notifier); + irq_set_affinity_hint(params->rx_irq[i], + &rxq_info->irq_affinity_mask); + } + + for (i = 0; i < dev->real_num_tx_queues; i++) { + struct queue_info *txq_info = &priv->txq_info[i]; + + scnprintf(txq_info->irq_name, + sizeof (txq_info->irq_name), + "%s-tx%u", + dev->name, i); + + ret = request_irq(params->tx_irq[i], + bcm_enet_runner_isr, + 0, txq_info->irq_name, priv); + if (ret) { + netdev_err(dev, "request_irq failed\n"); + return ret; + } + + txq_info->affinity_notifier.notify = + bcm_enet_runner_irq_affinity_notify; + txq_info->affinity_notifier.release = + bcm_enet_runner_irq_affinity_release; + irq_set_affinity_notifier(params->tx_irq[i], + &txq_info->affinity_notifier); + irq_set_affinity_hint(params->tx_irq[i], + &txq_info->irq_affinity_mask); + } + + priv->mode_ops->mtu_set(priv->mode_priv, priv->pkt_size); + + /* setup firmware */ + for (i = 0; i < dev->real_num_rx_queues; i++) { + struct rx_queue *rxq = &priv->rxq[i]; + + /* assign rx queue pointers & size */ + fw_rx_reg_writel(priv, rxq->rx_desc_dma, RX_DESC_ADDRESS_REG); + fw_rx_reg_writel(priv, rxq->ring_size, RX_DESC_COUNT_REG); + fw_rx_reg_writel(priv, params->rx_irq_mask[i], + RX_IRQ_MASK_REG); + } + + /* setup TX */ + fw_tx_reg_writeb(priv, params->tx_bbh_bbid, + TX_BBH_BB_ID_REG); + fw_tx_reg_writeb(priv, params->tx_need_reporting, + TX_EPON_REPORTING_REG); + fw_tx_reg_writeh(priv, params->tx_bbh_pd_queue_size, + TX_BBH_PD_QUEUE_SIZE_REG); + fw_tx_reg_writeh(priv, params->tx_bbh_mdu_addr, + TX_BBH_MDU_QUEUE_ADDR_REG); + + for (i = 0; i < priv->txq_count; i++) { + struct tx_queue *txq = &priv->txq[i]; + u16 acb_control; + unsigned int imp_port_mapped; + + /* assign tx queue pointers & size */ + fw_tx_reg_writel(priv, txq->tx_desc_dma, + fw_txqoff(i, TXQ_OFF_DESC_ADDRESS_REG)); + fw_tx_reg_writel(priv, txq->ring_size, + fw_txqoff(i, TXQ_OFF_DESC_COUNT_REG)); + fw_tx_reg_writel(priv, params->tx_done_irq_mask[i], + fw_txqoff(i, TXQ_OFF_IRQ_MASK_REG)); + + + if (!txq->use_dsa) + continue; + + fw_tx_reg_writeb(priv, txq->use_dsa ? 1 : 0, + fw_txqoff(i, TXQ_OFF_ACB_ENABLED_REG)); + fw_tx_reg_writeb(priv, txq->dsa_port * 8 + txq->dsa_queue, + fw_txqoff(i, TXQ_OFF_ACB_QIDX_REG)); + + imp_port_mapped = enet_fw_imp_port_map(txq->dsa_imp_port); + acb_control = + (imp_port_mapped << TXQ_ACBCTRL_IMP_PORT_SHIFT) | + (txq->dsa_port << TXQ_ACBCTRL_EGRESS_PORT_SHIFT) | + (txq->dsa_queue << TXQ_ACBCTRL_EGRESS_QUEUE_SHIFT); + fw_tx_reg_writeh(priv, acb_control, + fw_txqoff(i, TXQ_OFF_ACB_CONTROL_REG)); + } + + /* unmask interrupt */ + bcm_xrdp_api_irq_mask_set(priv->xrdp, + params->rx_core_id, priv->irq_mask); + napi_enable(&priv->napi); + + /* start firmware RX operation */ + val = fw_rx_reg_readl(priv, RX_CONTROL_REG); + val |= RX_CONTROL_RX_EN_MASK; + fw_rx_reg_writel(priv, val, RX_CONTROL_REG); + + /* kick FQM */ + bcm_xrdp_api_wakeup(priv->xrdp, + params->rx_core_id, + params->rxq_fqm_wakeup_thread); + + /* start firmware TX operation */ + val = fw_tx_reg_readl(priv, TX_CONTROL_REG); + val |= TX_CONTROL_TX_EN_MASK; + fw_tx_reg_writel(priv, val, TX_CONTROL_REG); + + phylink_start(priv->phylink); + + netif_tx_start_all_queues(dev); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + wake_up_process(priv->ff_reclaim_thread); +#endif + return 0; + +out: +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (priv->ff_reclaim_thread) + kthread_stop(priv->ff_reclaim_thread); +#endif + for (i = 0; i < dev->real_num_rx_queues; i++) + rxq_deinit(priv, priv->rxq + i); + for (i = 0; i < priv->txq_count; i++) + txq_deinit(priv, priv->txq + i); + return ret; +} + +/* + * + */ +bool bcm_runner_fw_bbh_is_empty(struct bcm_enet_runner_priv *priv) +{ + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 bbh_id; + + bbh_id = priv->mode_ops->get_bbh_id(priv->port_priv); + return bcm_xrdp_api_bbh_txq_is_empty(priv->xrdp, + bbh_id, + params->tx_bbh_queue_id); +} + +/* + * + */ +void bcm_runner_fw_stop_tx(struct bcm_enet_runner_priv *priv) +{ + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + u32 val; + + val = fw_tx_reg_readl(priv, TX_CONTROL_REG); + val &= ~TX_CONTROL_TX_EN_MASK; + fw_tx_reg_writel(priv, val, TX_CONTROL_REG); + + bcm_xrdp_api_wakeup(priv->xrdp, + params->tx_core_id, + params->txq_wakeup_thread[0]); +} + +/* + * + */ +bool bcm_runner_fw_tx_is_stopped(struct bcm_enet_runner_priv *priv) +{ + u32 val; + + val = fw_tx_reg_readl(priv, TX_STATUS_REG); + if ((val & TX_STATUS_TX_EN_MASK)) + return false; + return true; +} + +/* + * + */ +void bcm_runner_fw_tx_stop_wait(struct bcm_enet_runner_priv *priv) +{ + unsigned int i; + bool stopped; + + bcm_runner_fw_stop_tx(priv); + for (i = 0; i < 1000; i++) { + stopped = bcm_runner_fw_tx_is_stopped(priv); + if (stopped) + break; + usleep_range(1000, 2000); + } + + if (!stopped) + netdev_err(priv->netdev, "failed to stop TX DMA"); +} + +/* + * + */ +static int bcm_runner_stop(struct net_device *dev) +{ + struct bcm_enet_runner_priv *priv = netdev_priv(dev); + struct bcm_xrdp_enet_params *params = &priv->xrdp_params; + unsigned int i, xfid; + u32 val; + + /* mask all interrupts */ + bcm_xrdp_api_irq_mask_clear(priv->xrdp, + params->rx_core_id, priv->irq_mask); + + /* prevent hardxmit from being called */ + netif_tx_disable(dev); + + /* prevent poll() from being called */ + napi_disable(&priv->napi); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (priv->ff_reclaim_thread) + kthread_stop(priv->ff_reclaim_thread); +#endif + + /* stop firmware RX operation & wait for RX enable status to + * clear */ + val = fw_rx_reg_readl(priv, RX_CONTROL_REG); + val &= ~RX_CONTROL_RX_EN_MASK; + fw_rx_reg_writel(priv, val, RX_CONTROL_REG); + + /* wait for all XF first */ + for (xfid = 0; xfid < ARRAY_SIZE(params->rxq_xf_wakeup_thread); + xfid++) { + bcm_xrdp_api_wakeup(priv->xrdp, + params->rx_core_id, + params->rxq_xf_wakeup_thread[xfid]); + + for (i = 0; i < 1000; i++) { + val = fw_rx_reg_readl(priv, + fw_rx_xf_off(xfid, RX_XF_STATUS_REG)); + if (!(val & RX_XF_STATUS_RX_EN_MASK)) + break; + + usleep_range(1000, 2000); + } + + if ((val & RX_XF_STATUS_RX_EN_MASK)) + netdev_err(dev, "failed to stop RX for xf %u", xfid); + } + + /* wait for FQM */ + bcm_xrdp_api_wakeup(priv->xrdp, + params->rx_core_id, + params->rxq_fqm_wakeup_thread); + + for (i = 0; i < 1000; i++) { + val = fw_rx_reg_readl(priv, RX_FQM_STATUS_REG); + if (!(val & RX_FQM_STATUS_RX_EN_MASK)) + break; + + usleep_range(1000, 2000); + } + + if ((val & RX_FQM_STATUS_RX_EN_MASK)) + netdev_err(dev, "failed to stop RX for FQM"); + + phylink_stop(priv->phylink); + priv->mode_ops->stop(priv->mode_priv); + + /* force reclaim of all tx buffers now that firmware does not + * use them */ + local_bh_disable(); + for (i = 0; i < priv->txq_count; i++) + bcm_runner_tx_reclaim(priv, dev, &priv->txq[i], INT_MAX, 1); + local_bh_enable(); + + for (i = 0; i < dev->real_num_rx_queues; i++) { + irq_set_affinity_notifier(params->rx_irq[i], NULL); + irq_set_affinity_hint(params->rx_irq[i], NULL); + free_irq(params->rx_irq[i], priv); + } + for (i = 0; i < dev->real_num_tx_queues; i++) { + irq_set_affinity_notifier(params->tx_irq[i], NULL); + irq_set_affinity_hint(params->tx_irq[i], NULL); + free_irq(params->tx_irq[i], priv); + } + + for (i = 0; i < dev->real_num_rx_queues; i++) + rxq_deinit(priv, priv->rxq + i); + for (i = 0; i < priv->txq_count; i++) + txq_deinit(priv, priv->txq + i); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + priv->ff_txq = NULL; +#endif + + priv->reset_scheduled = false; + return 0; +} + +/* + * + */ +void bcm_enet_runner_schedule_reset(struct bcm_enet_runner_priv *priv, + unsigned int delay_ms) +{ + priv->reset_scheduled = true; + schedule_delayed_work(&priv->reset_link_work, + msecs_to_jiffies(delay_ms)); +} + +/* + * + */ +void bcm_enet_runner_unschedule_reset(struct bcm_enet_runner_priv *priv) +{ + priv->reset_scheduled = false; +} + +/* + * + */ +static void reset_link_work(struct work_struct *w) +{ + struct delayed_work *dwork = to_delayed_work(w); + struct bcm_enet_runner_priv *priv; + + priv = container_of(dwork, struct bcm_enet_runner_priv, + reset_link_work); + + rtnl_lock(); + if (!priv->reset_scheduled || !netif_running(priv->netdev)) { + rtnl_unlock(); + return; + } + + priv->reset_scheduled = false; + netdev_info(priv->netdev, "resetting link\n"); +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_notifier_event(priv->netdev, NETDEV_GOING_DOWN); +#endif + bcm_runner_stop(priv->netdev); + if (bcm_runner_open(priv->netdev)) + netdev_err(priv->netdev, "failed to reset link\n"); +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + else + ff_notifier_event(priv->netdev, NETDEV_UP); +#endif + rtnl_unlock(); +} + + +/* + * Change the interface's MTU + */ +static int bcm_runner_change_mtu(struct net_device *dev, + int new_mtu) +{ + if (netif_running(dev)) + return -EBUSY; + + dev->mtu = new_mtu; + return 0; +} + +/* + * Change the interface's mac address. + */ +static int bcm_runner_set_mac_address(struct net_device *dev, void *p) +{ + struct sockaddr *addr = p; + + if (netif_running(dev)) + return -EBUSY; + + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + return 0; +} + +/* + * + */ +static void phylink_validate(struct phylink_config *config, + unsigned long *supported, + struct phylink_link_state *state) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + priv->mode_ops->phylink_validate(priv->port_priv, supported, state); +} + +/* + * called by phylink to apply new mac config, with rtnl held + * + * only called when netdevice is up + */ +static void phylink_mac_config(struct phylink_config *config, + unsigned int pl_mode, + const struct phylink_link_state *state) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + priv->mode_ops->phylink_mac_config(priv->mode_priv, pl_mode, state); +} + +/* + * + */ +static void phylink_mac_link_up(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phy) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + priv->mode_ops->phylink_link_up(priv->mode_priv, mode, interface, phy); +} + +/* + * + */ +static void phylink_mac_link_down(struct phylink_config *config, + unsigned int mode, + phy_interface_t interface) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + priv->mode_ops->phylink_link_down(priv->mode_priv, mode, interface); +} + +/* + * phylink callback, only for inband autoneg + */ +static void phylink_pcs_an_restart(struct phylink_config *config) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + + if (priv->mode_ops->phylink_pcs_an_restart) + priv->mode_ops->phylink_pcs_an_restart(priv->mode_priv); +} + +/* + * phylink callback, only for inband autoneg + */ +static int phylink_pcs_link_state(struct phylink_config *config, + struct phylink_link_state *state) +{ + struct net_device *ndev = to_net_dev(config->dev); + struct bcm_enet_runner_priv *priv = netdev_priv(ndev); + + if (priv->mode_ops->phylink_pcs_link_state) + priv->mode_ops->phylink_pcs_link_state(priv->mode_priv, state); + return 0; +} + +const struct phylink_mac_ops bcm_enet_runner_phylink_ops = { + .validate = phylink_validate, + .mac_config = phylink_mac_config, + .mac_link_up = phylink_mac_link_up, + .mac_link_down = phylink_mac_link_down, + .mac_link_state = phylink_pcs_link_state, + .mac_an_restart = phylink_pcs_an_restart, +}; + +const struct net_device_ops bcm_runner_ops = { + .ndo_open = bcm_runner_open, + .ndo_stop = bcm_runner_stop, + .ndo_start_xmit = bcm_runner_start_xmit, + .ndo_set_mac_address = bcm_runner_set_mac_address, + .ndo_change_mtu = bcm_runner_change_mtu, + .ndo_select_queue = bcm_runner_select_queue, +}; + +/* + * runner mib + */ +#define GEN_RUNNER_RX_STAT(reg) 4, 0, reg, 1 +#define GEN_RUNNER_RX_XF_STAT(xfid, reg) \ + GEN_RUNNER_RX_STAT(RX_IF_REGS_BASE_OFF + xfid * RX_IF_REGS_PERIF_SIZE + reg) + +#define GEN_RUNNER_TX_STAT(reg) 4, 0, reg, 2 +#define GEN_RUNNER_TXQ_STAT(q, reg) \ + GEN_RUNNER_TX_STAT(TXQ_REGS_BASE_OFF + (q) * TXQ_REGS_PERQ_SIZE + reg) + +#define GEN_RUNNER_RX_STAT16(reg) 2, 0, reg, 1 +#define GEN_RUNNER_RX_XF_STAT16(xfid, reg) \ + GEN_RUNNER_RX_STAT16(RX_IF_REGS_BASE_OFF + xfid * RX_IF_REGS_PERIF_SIZE + reg) + +#define GEN_RUNNER_TX_STAT16(reg) 2, 0, reg, 2 +#define GEN_RUNNER_TXQ_STAT16(q, reg) \ + GEN_RUNNER_TX_STAT16(TXQ_REGS_BASE_OFF + (q) * TXQ_REGS_PERQ_SIZE + reg) + +#define GEN_RUNNER_RX_STAT8(reg) 1, 0, reg, 1 +#define GEN_RUNNER_RX_XF_STAT8(xfid, reg) \ + GEN_RUNNER_RX_STAT8(RX_IF_REGS_BASE_OFF + xfid * RX_IF_REGS_PERIF_SIZE + reg) + +#define GEN_RUNNER_TX_STAT8(reg) 1, 0, reg, 2 +#define GEN_RUNNER_TXQ_STAT8(q, reg) \ + GEN_RUNNER_TX_STAT8(TXQ_REGS_BASE_OFF + (q) * TXQ_REGS_PERQ_SIZE + reg) + +const struct bcm_runner_ethtool_stat bcm_runner_fw_estat[] = { + { "rnr_rx_control", GEN_RUNNER_RX_STAT(RX_CONTROL_REG) }, + { "rnr_rx_desc_addr", GEN_RUNNER_RX_STAT(RX_DESC_ADDRESS_REG) }, + { "rnr_rx_desc_size", GEN_RUNNER_RX_STAT(RX_DESC_COUNT_REG) }, + { "rnr_rx_irq_mask", GEN_RUNNER_RX_STAT(RX_IRQ_MASK_REG) }, + + { "rnr_rx_fqm_status", GEN_RUNNER_RX_STAT(RX_FQM_STATUS_REG) }, + { "rnr_rx_fqm_dbg_task_call", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_fqm_dbg_cpu_ring_idx", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_CPU_RING_IDX_REG) }, + { "rnr_rx_fqm_dbg_full", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_FULL_REG) }, + { "rnr_rx_fqm_dbg_host_nobuf", GEN_RUNNER_RX_STAT(RX_FQM_STAT_DBG_HOST_NOBUF_REG) }, + { "rnr_rx_fqm_head_idx", GEN_RUNNER_RX_STAT8(RX_FQM_HEAD_IDX_REG) }, + { "rnr_rx_fqm_tail_idx", GEN_RUNNER_RX_STAT8(RX_FQM_TAIL_IDX_REG) }, + + { "rnr_rx_xf0_status", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STATUS_REG) }, + { "rnr_rx_xf0_cnt_pkt_count", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_PKT_REG) }, + { "rnr_rx_xf0_cnt_drop_nobuf", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_DROP_NOBUF_REG) }, + { "rnr_rx_xf0_cnt_drop_rxdis", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_DROP_RXDIS_REG) }, + { "rnr_rx_xf0_cnt_drop_rxerr", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_RX_CNT_DROP_RXERR_REG) }, + { "rnr_rx_xf0_dbg_task_call", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_xf0_dbg_last_pd0", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD0_REG) }, + { "rnr_rx_xf0_dbg_last_pd1", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD1_REG) }, + { "rnr_rx_xf0_dbg_last_pd2", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD2_REG) }, + { "rnr_rx_xf0_dbg_last_pd3", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PD3_REG) }, + { "rnr_rx_xf0_dbg_last_sn", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_SN_REG) }, + { "rnr_rx_xf0_dbg_last_bn", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_BN_REG) }, + { "rnr_rx_xf0_dbg_last_plen", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_PLEN_REG) }, + { "rnr_rx_xf0_dbg_last_cpudesc_idx", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG) }, + { "rnr_rx_xf0_dbg_cnt_invalid_pd", GEN_RUNNER_RX_XF_STAT(0, RX_XF_STAT_DBG_INVALID_PD_CNT_REG) }, + + { "rnr_rx_xf1_status", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STATUS_REG) }, + { "rnr_rx_xf1_cnt_pkt_count", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_PKT_REG) }, + { "rnr_rx_xf1_cnt_drop_nobuf", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_DROP_NOBUF_REG) }, + { "rnr_rx_xf1_cnt_drop_rxdis", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_DROP_RXDIS_REG) }, + { "rnr_rx_xf1_cnt_drop_rxerr", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_RX_CNT_DROP_RXERR_REG) }, + { "rnr_rx_xf1_dbg_task_call", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_xf1_dbg_last_pd0", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD0_REG) }, + { "rnr_rx_xf1_dbg_last_pd1", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD1_REG) }, + { "rnr_rx_xf1_dbg_last_pd2", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD2_REG) }, + { "rnr_rx_xf1_dbg_last_pd3", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PD3_REG) }, + { "rnr_rx_xf1_dbg_last_sn", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_SN_REG) }, + { "rnr_rx_xf1_dbg_last_bn", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_BN_REG) }, + { "rnr_rx_xf1_dbg_last_plen", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_PLEN_REG) }, + { "rnr_rx_xf1_dbg_last_cpudesc_idx", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG) }, + { "rnr_rx_xf1_dbg_cnt_invalid_pd", GEN_RUNNER_RX_XF_STAT(1, RX_XF_STAT_DBG_INVALID_PD_CNT_REG) }, + + { "rnr_rx_xf2_status", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STATUS_REG) }, + { "rnr_rx_xf2_cnt_pkt_count", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_PKT_REG) }, + { "rnr_rx_xf2_cnt_drop_nobuf", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_DROP_NOBUF_REG) }, + { "rnr_rx_xf2_cnt_drop_rxdis", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_DROP_RXDIS_REG) }, + { "rnr_rx_xf2_cnt_drop_rxerr", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_RX_CNT_DROP_RXERR_REG) }, + { "rnr_rx_xf2_dbg_task_call", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_TASK_CALL_REG) }, + { "rnr_rx_xf2_dbg_last_pd0", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD0_REG) }, + { "rnr_rx_xf2_dbg_last_pd1", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD1_REG) }, + { "rnr_rx_xf2_dbg_last_pd2", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD2_REG) }, + { "rnr_rx_xf2_dbg_last_pd3", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PD3_REG) }, + { "rnr_rx_xf2_dbg_last_sn", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_SN_REG) }, + { "rnr_rx_xf2_dbg_last_bn", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_BN_REG) }, + { "rnr_rx_xf2_dbg_last_plen", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_PLEN_REG) }, + { "rnr_rx_xf2_dbg_last_cpudesc_idx", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_LAST_CPUDESC_IDX_REG) }, + { "rnr_rx_xf2_dbg_cnt_invalid_pd", GEN_RUNNER_RX_XF_STAT(2, RX_XF_STAT_DBG_INVALID_PD_CNT_REG) }, + + { "rnr_tx_status", GEN_RUNNER_TX_STAT(TX_STATUS_REG) }, + { "rnr_tx_control", GEN_RUNNER_TX_STAT(TX_CONTROL_REG) }, + { "rnr_tx_bbh_id", GEN_RUNNER_TX_STAT(TX_BBH_BB_ID_REG) }, + { "rnr_tx_pd_queue_size", GEN_RUNNER_TX_STAT(TX_BBH_PD_QUEUE_SIZE_REG) }, + { "rnr_tx_cnt_drop_txdis", GEN_RUNNER_TX_STAT(TX_STAT_CNT_TX_DISABLED_REG) }, + { "rnr_tx_dbg_task_call", GEN_RUNNER_TX_STAT(TX_STAT_DBG_TASK_CALL_REG) }, + { "rnr_tx_dbg_hw_fifo_full", GEN_RUNNER_TX_STAT(TX_STAT_DBG_FIFO_FULL_REG) }, + { "rnr_tx_dbg_mdu_reclaim_idx", GEN_RUNNER_TX_STAT(TX_STAT_DBG_MDU_FW_RECLAIM_IDX_REG) }, + { "rnr_tx_dbg_mdu_push_idx", GEN_RUNNER_TX_STAT(TX_STAT_DBG_MDU_FW_PUSH_IDX_REG) }, + + { "rnr_txq0_desc_addr", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_DESC_ADDRESS_REG) }, + { "rnr_txq0_desc_count", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_DESC_COUNT_REG) }, + { "rnr_txq0_irq_mask", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_IRQ_MASK_REG) }, + { "rnr_txq0_tx_idx", GEN_RUNNER_TXQ_STAT8(0, TXQ_OFF_TX_DESC_IDX) }, + { "rnr_txq0_tx_cnt", GEN_RUNNER_TXQ_STAT8(0, TXQ_OFF_TX_DESC_CNT) }, + { "rnr_txq0_cnt_pkt", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_STAT_CNT_PKT_SENT_REG) }, + { "rnr_txq0_cnt_reclaimed", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_STAT_CNT_PKT_RECLAIMED_REG) }, + { "rnr_txq0_ring_push_idx", GEN_RUNNER_TXQ_STAT16(0, TXQ_OFF_RING_PUSH_IDX_REG) }, + { "rnr_txq0_ring_reclaim_idx", GEN_RUNNER_TXQ_STAT16(0, TXQ_OFF_RING_RECLAIM_IDX_REG) }, + { "rnr_txq0_acb_qfull", GEN_RUNNER_TXQ_STAT(0, TXQ_OFF_STAT_CNT_ACB_QFULL) }, + + { "rnr_txq1_desc_addr", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_DESC_ADDRESS_REG) }, + { "rnr_txq1_desc_count", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_DESC_COUNT_REG) }, + { "rnr_txq1_irq_mask", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_IRQ_MASK_REG) }, + { "rnr_txq1_tx_idx", GEN_RUNNER_TXQ_STAT8(1, TXQ_OFF_TX_DESC_IDX) }, + { "rnr_txq1_tx_cnt", GEN_RUNNER_TXQ_STAT8(1, TXQ_OFF_TX_DESC_CNT) }, + { "rnr_txq1_cnt_pkt", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_STAT_CNT_PKT_SENT_REG) }, + { "rnr_txq1_cnt_reclaimed", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_STAT_CNT_PKT_RECLAIMED_REG) }, + { "rnr_txq1_ring_push_idx", GEN_RUNNER_TXQ_STAT16(1, TXQ_OFF_RING_PUSH_IDX_REG) }, + { "rnr_txq1_ring_reclaim_idx", GEN_RUNNER_TXQ_STAT16(1, TXQ_OFF_RING_RECLAIM_IDX_REG) }, + { "rnr_txq1_acb_qfull", GEN_RUNNER_TXQ_STAT(1, TXQ_OFF_STAT_CNT_ACB_QFULL) }, +}; + +const size_t bcm_runner_fw_estat_count = ARRAY_SIZE(bcm_runner_fw_estat); + +u64 bcm_runner_fw_read_estat(struct bcm_enet_runner_priv *priv, int idx) +{ + const struct bcm_runner_ethtool_stat *s; + + BUG_ON(idx >=bcm_runner_fw_estat_count); + s = &bcm_runner_fw_estat[idx]; + + switch (s->type) { + case 1: + switch (s->size) { + case 1: + return fw_rx_reg_readb(priv, s->reg); + case 2: + return fw_rx_reg_readh(priv, s->reg); + case 4: + default: + return fw_rx_reg_readl(priv, s->reg); + } + case 2: + switch (s->size) { + case 1: + return fw_tx_reg_readb(priv, s->reg); + case 2: + return fw_tx_reg_readh(priv, s->reg); + case 4: + default: + return fw_tx_reg_readl(priv, s->reg); + } + } + return 0; +} + +/* + * + */ +static int __set_mode(struct bcm_enet_runner_priv *priv, + unsigned int new_mode_idx) +{ + const struct bcm_enet_mode_ops *new_mode_ops; + struct bcm_xrdp_enet_params xrdp_params; + void *mode_priv; + u32 bbh_id; + int ret; + + if (new_mode_idx >= priv->port_ops->mode_count) + return -EINVAL; + + new_mode_ops = priv->port_ops->modes[new_mode_idx]; + if (priv->port_ops->mode_count > 1) + netdev_info(priv->netdev, "switching to mode %s\n", + new_mode_ops->name); + + bbh_id = new_mode_ops->get_bbh_id(priv->port_priv); + ret = bcm_xrdp_api_get_enet_params(priv->xrdp, bbh_id, &xrdp_params); + if (ret < 0) { + netdev_err(priv->netdev, + "failed to get rdp params for bbh %u\n", bbh_id); + return ret; + } + + mode_priv = new_mode_ops->init(priv->port_priv, &xrdp_params); + if (IS_ERR(mode_priv)) { + netdev_err(priv->netdev, "failed to switch mode: %ld\n", + PTR_ERR(mode_priv)); + return PTR_ERR(mode_priv); + } + memcpy(&priv->xrdp_params, &xrdp_params, sizeof (priv->xrdp_params)); + + if (priv->mode_ops) { + priv->mode_ops->release(priv->mode_priv); + priv->mode_priv = NULL; + } + + priv->mode_idx = new_mode_idx; + priv->mode_ops = new_mode_ops; + priv->mode_priv = mode_priv; + return 0; +} + + +/* + * + */ +int bcm_enet_runner_toggle_mode(struct bcm_enet_runner_priv *priv, + unsigned int new_mode_idx) +{ + int ret; + bool restart; + + ASSERT_RTNL(); + + restart = false; + if (netif_running(priv->netdev)) { + restart = true; +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_notifier_event(priv->netdev, NETDEV_GOING_DOWN); +#endif + bcm_runner_stop(priv->netdev); + } + + ret = __set_mode(priv, new_mode_idx); + if (ret) + return ret; + + phylink_revalidate(priv->phylink); + + if (restart) { + ret = bcm_runner_open(priv->netdev); +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + if (!ret) + ff_notifier_event(priv->netdev, NETDEV_UP); +#endif + } + + return ret; +} + +/* + * callback when a new DSA slave device is using this dev as master + */ +static int +bcm_enet_runner_dsa_port_reg(struct notifier_block *nb, + struct dsa_notifier_register_info *info) +{ + struct bcm_enet_runner_priv *priv; + struct bcm_dsa_port *dp; + + priv = container_of(nb, struct bcm_enet_runner_priv, dsa_notifier); + if (priv->netdev != info->master) + return 0; + + if (info->switch_number) + return 0; + + dp = kmalloc(sizeof (*dp), GFP_ATOMIC); + if (!dp) + return 0; + + dp->port = info->port_number; + dp->imp_port = info->cpu_port_number; + dp->slave_netdev = info->info.dev; + list_add(&dp->next, &priv->dsa_ports); + /* resolve queue mapping at device open time, when actual + * number of queue is known */ + return 0; +} + +/* + * callback when a new DSA slave device is detached from this master + */ +static int +bcm_enet_runner_dsa_port_remove(struct notifier_block *nb, + struct dsa_notifier_register_info *info) +{ + struct bcm_enet_runner_priv *priv; + struct bcm_dsa_port *dp; + + priv = container_of(nb, struct bcm_enet_runner_priv, dsa_notifier); + if (priv->netdev != info->master) + return 0; + + list_for_each_entry(dp, &priv->dsa_ports, next) { + if (dp->slave_netdev == info->info.dev) { + list_del(&dp->next); + kfree(dp); + break; + } + } + + return 0; +} + +/* + * DSA slave device change notifier + */ +static int bcm_enet_runner_dsa_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + int ret = NOTIFY_DONE; + + switch (event) { + case DSA_PORT_REGISTER: + ret = bcm_enet_runner_dsa_port_reg(nb, ptr); + break; + case DSA_PORT_UNREGISTER: + ret = bcm_enet_runner_dsa_port_remove(nb, ptr); + break; + } + + return notifier_from_errno(ret); +} + +/* + * + */ +static int bcm_enet_runner_probe(struct platform_device *pdev) +{ + struct bcm_enet_runner_priv *priv; + struct device_node *xrdp_node; + struct platform_device *xrdp_pdev; + struct bcm_xrdp_priv *xrdp_priv; + struct net_device *netdev; + enum bcm_runner_port_type port_type; + const void *macaddr; + int phy_mode; + int ret; + size_t i; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_init(&pdev->dev); +#endif + + phy_mode = of_get_phy_mode(pdev->dev.of_node); + if (phy_mode < 0) { + dev_err(&pdev->dev, "incorrect phy-mode\n"); + return -ENODEV; + } + + xrdp_node = of_parse_phandle(pdev->dev.of_node, "enet-runner,xrdp", 0); + if (!xrdp_node) { + dev_err(&pdev->dev, "failed to find XRDP node\n"); + return -ENODEV; + } + + xrdp_pdev = of_find_device_by_node(xrdp_node); + of_node_put(xrdp_node); + if (!xrdp_pdev) { + dev_err(&pdev->dev, "failed to find XRDP device\n"); + return -ENODEV; + } + + xrdp_priv = platform_get_drvdata(xrdp_pdev); + if (!xrdp_priv) { + dev_dbg(&pdev->dev, "XRDP not yet initialized\n"); + return -EPROBE_DEFER; + } + + macaddr = of_get_mac_address(pdev->dev.of_node); + if (!macaddr) { + dev_err(&pdev->dev, + "failed to find address node\n"); + return -ENODEV; + } + + netdev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof (*priv), + BCM_ENET_RUNNER_MAX_TXQ, + BCM_ENET_RUNNER_MAX_RXQ); + if (!netdev) + return -ENOMEM; + + priv = netdev_priv(netdev); + priv->netdev = netdev; + priv->pdev = pdev; + priv->xrdp = xrdp_priv; + priv->rxq_size = 512; + priv->txq_size = 512; + INIT_DELAYED_WORK(&priv->reset_link_work, reset_link_work); + INIT_LIST_HEAD(&priv->dsa_ports); + for (i = 0; i < ARRAY_SIZE(priv->rxq_info); i++) + cpumask_copy(&priv->rxq_info[i].irq_affinity_mask, + cpu_all_mask); + for (i = 0; i < ARRAY_SIZE(priv->txq_info); i++) + cpumask_copy(&priv->txq_info[i].irq_affinity_mask, + cpu_all_mask); + + port_type = (uintptr_t)of_device_get_match_data(&pdev->dev); + switch (port_type) { + case BCM_RUNNER_PORT_UNIMAC: + priv->port_ops = &port_unimac_ops; + break; + case BCM_RUNNER_PORT_XPORT: + priv->port_ops = &port_xport_ops; + break; + default: + return -EINVAL; + } + + priv->port_priv = priv->port_ops->init(priv); + if (IS_ERR(priv->port_priv)) + return PTR_ERR(priv->port_priv); + + /* register netdevice */ + netdev->min_mtu = ETH_ZLEN - ETH_HLEN; + netdev->max_mtu = BCM_RUNNER_MAC_MAX_MTU; + netdev->netdev_ops = &bcm_runner_ops; + netdev->ethtool_ops = &bcm_runner_ethtool_ops; + ether_addr_copy(netdev->dev_addr, macaddr); + SET_NETDEV_DEV(netdev, &pdev->dev); + netif_napi_add(netdev, &priv->napi, bcm_runner_poll, 16); + + ret = __set_mode(priv, 0); + if (ret) + return ret; + + priv->phylink_config.dev = &netdev->dev; + priv->phylink_config.type = PHYLINK_NETDEV; + priv->phylink = phylink_create(&priv->phylink_config, + pdev->dev.fwnode, + phy_mode, + &bcm_enet_runner_phylink_ops); + if (IS_ERR(priv->phylink)) + return PTR_ERR(priv->phylink); + + ret = phylink_of_phy_connect(priv->phylink, pdev->dev.of_node, 0); + if (ret) { + dev_err(&pdev->dev, "failed to connect to PHY\n"); + goto out; + } + + priv->dsa_notifier.notifier_call = bcm_enet_runner_dsa_notifier; + ret = register_dsa_notifier(&priv->dsa_notifier); + if (ret) { + dev_err(&pdev->dev, "failed to register DSA notifier\n"); + goto out; + } + priv->dsa_notifier_registered = true; + + ret = register_netdev(netdev); + if (ret) + goto out; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + switch (port_type) { + case BCM_RUNNER_PORT_UNIMAC: + priv->ff_hw_id = FF_HWDEV_ID_UNIMAC0 + + priv->mode_ops->get_bbh_id(priv->port_priv); + break; + case BCM_RUNNER_PORT_XPORT: + priv->ff_hw_id = FF_HWDEV_ID_FTTH; + break; + default: + return -EINVAL; + } + + WARN_ON(ff.ports_by_hw_id[priv->ff_hw_id] != NULL); + ff.ports_by_hw_id[priv->ff_hw_id] = priv; +#endif + + platform_set_drvdata(pdev, priv); + return 0; + +out: + if (priv->dsa_notifier_registered) + unregister_dsa_notifier(&priv->dsa_notifier); + if (priv->mode_priv) + priv->mode_ops->release(priv->mode_priv); + if (priv->phylink) + phylink_destroy(priv->phylink); + return ret; +} + +/* + * + */ +static int bcm_enet_runner_remove(struct platform_device *pdev) +{ + struct bcm_enet_runner_priv *priv = platform_get_drvdata(pdev); + + unregister_netdev(priv->netdev); + unregister_dsa_notifier(&priv->dsa_notifier); + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff.ports_by_hw_id[priv->ff_hw_id] = NULL; + kthread_stop(priv->ff_reclaim_thread); +#endif + + priv->mode_ops->release(priv->mode_priv); + phylink_destroy(priv->phylink); + return 0; +} + +static const struct of_device_id bcm63158_enet_runner_of_match[] = { + { .compatible = "brcm,bcm63158-enet-runner-unimac", + .data = (void *)BCM_RUNNER_PORT_UNIMAC }, + { .compatible = "brcm,bcm63158-enet-runner-xport" , + .data = (void *)BCM_RUNNER_PORT_XPORT }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, bcm63158_enet_runner_of_match); + +/* + * + */ +struct platform_driver bcm63158_enet_runner_driver = { + .probe = bcm_enet_runner_probe, + .remove = bcm_enet_runner_remove, + .driver = { + .name = "bcm63158_enet_runner", + .of_match_table = bcm63158_enet_runner_of_match, + .owner = THIS_MODULE, + }, +}; + +static int __init bcm63158_enet_runner_init(void) +{ + bcm63158_dbg_root = debugfs_create_dir("bcm63158_enet_runner", NULL); + if (!bcm63158_dbg_root) + return -ENOMEM; + +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + ff_notifier.notifier_call = ff_notifier_event_cb; + register_netdevice_notifier(&ff_notifier); +#endif + return platform_driver_register(&bcm63158_enet_runner_driver); +} + +static void __exit bcm63158_enet_runner_exit(void) +{ +#ifdef CONFIG_BCM63158_ENET_RUNNER_FF + unregister_netdevice_notifier(&ff_notifier); +#endif + platform_driver_unregister(&bcm63158_enet_runner_driver); + debugfs_remove_recursive(bcm63158_dbg_root); +} + + +module_init(bcm63158_enet_runner_init); +module_exit(bcm63158_enet_runner_exit); + +MODULE_DESCRIPTION("BCM63158 ethernet runner driver"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_LICENSE("GPL"); diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/Makefile linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/Makefile --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/Makefile 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,11 @@ +obj-$(CONFIG_BCM63158_ENET_RUNNER) += bcm63158_enet_runner.o + +bcm63158_enet_runner-y := \ + ethtool.o \ + main.o \ + port_unimac.o \ + port_xport.o \ + port_xport_serdes.o \ + port_xport_epon.o \ + port_xport_epon_dbg.o \ + port_xport_xlmac.o diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.c 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,364 @@ +#include "port_unimac.h" + +#define GEN_MIB_STAT(m) \ + sizeof(((struct unimac_mib *)0)->m), \ + offsetof(struct unimac_mib, m) + +static const struct bcm_runner_ethtool_stat unimac_mib_estat[] = { + { "rx_64", GEN_MIB_STAT(rx_64), UNIMAC_MIB_GR64_REG, }, + { "rx_65_127", GEN_MIB_STAT(rx_65_127), UNIMAC_MIB_GR127_REG, }, + { "rx_128_255", GEN_MIB_STAT(rx_128_255), UNIMAC_MIB_GR255_REG, }, + { "rx_256_511", GEN_MIB_STAT(rx_256_511), UNIMAC_MIB_GR511_REG, }, + { "rx_512_1023", GEN_MIB_STAT(rx_512_1023), UNIMAC_MIB_GR1023_REG, }, + { "rx_1024_1518", GEN_MIB_STAT(rx_1024_1518), UNIMAC_MIB_GR1518_REG, }, + { "rx_1519_1522_vlan", GEN_MIB_STAT(rx_1519_1522_vlan), UNIMAC_MIB_GRMGV_REG, }, + { "rx_1519_2047", GEN_MIB_STAT(rx_1519_2047), UNIMAC_MIB_GR2047_REG, }, + { "rx_2048_4095", GEN_MIB_STAT(rx_2048_4095), UNIMAC_MIB_GR4095_REG, }, + { "rx_4096_9216", GEN_MIB_STAT(rx_4096_9216), UNIMAC_MIB_GR9216_REG, }, + { "rx_all_pkts", GEN_MIB_STAT(rx_all_pkts), UNIMAC_MIB_GRPKT_REG, }, + { "rx_all_octets", GEN_MIB_STAT(rx_all_octets), UNIMAC_MIB_GRBYT_REG, }, + { "rx_mult", GEN_MIB_STAT(rx_mult), UNIMAC_MIB_GRMCA_REG, }, + { "rx_brdcast", GEN_MIB_STAT(rx_brdcast), UNIMAC_MIB_GRBCA_REG, }, + { "rx_crc", GEN_MIB_STAT(rx_crc), UNIMAC_MIB_GRFCS_REG, }, + { "rx_cntrl", GEN_MIB_STAT(rx_cntrl), UNIMAC_MIB_GRXCF_REG, }, + { "rx_pause", GEN_MIB_STAT(rx_pause), UNIMAC_MIB_GRXPF_REG, }, + { "rx_und", GEN_MIB_STAT(rx_und), UNIMAC_MIB_GRXUO_REG, }, + { "rx_align", GEN_MIB_STAT(rx_align), UNIMAC_MIB_GRALN_REG, }, + { "rx_frame_len", GEN_MIB_STAT(rx_frame_len), UNIMAC_MIB_GRFLR_REG, }, + { "rx_code", GEN_MIB_STAT(rx_code), UNIMAC_MIB_GRCDE_REG, }, + { "rx_carrier", GEN_MIB_STAT(rx_carrier), UNIMAC_MIB_GRFCR_REG, }, + { "rx_oversize", GEN_MIB_STAT(rx_oversize), UNIMAC_MIB_GROVR_REG, }, + { "rx_jabber", GEN_MIB_STAT(rx_jabber), UNIMAC_MIB_GRJBR_REG, }, + { "rx_too_big", GEN_MIB_STAT(rx_too_big), UNIMAC_MIB_GRMTUE_REG, }, + { "rx_gd_pkts", GEN_MIB_STAT(rx_gd_pkts), UNIMAC_MIB_GRPOK_REG, }, + { "rx_unicast", GEN_MIB_STAT(rx_unicast), UNIMAC_MIB_GRUC_REG, }, + { "rx_ppp", GEN_MIB_STAT(rx_ppp), UNIMAC_MIB_GRPPP_REG, }, + { "rx_crc_match", GEN_MIB_STAT(rx_crc_match), UNIMAC_MIB_GRCRC_REG, }, + { "tx_64", GEN_MIB_STAT(tx_64), UNIMAC_MIB_TR64_REG, }, + { "tx_65_127", GEN_MIB_STAT(tx_65_127), UNIMAC_MIB_TR127_REG, }, + { "tx_128_255", GEN_MIB_STAT(tx_128_255), UNIMAC_MIB_TR255_REG, }, + { "tx_256_511", GEN_MIB_STAT(tx_256_511), UNIMAC_MIB_TR511_REG, }, + { "tx_512_1023", GEN_MIB_STAT(tx_512_1023), UNIMAC_MIB_TR1023_REG, }, + { "tx_1024_1518", GEN_MIB_STAT(tx_1024_1518), UNIMAC_MIB_TR1518_REG, }, + { "tx_1519_1522_vlan", GEN_MIB_STAT(tx_1519_1522_vlan), UNIMAC_MIB_TRMGV_REG, }, + { "tx_1523_2047", GEN_MIB_STAT(tx_1523_2047), UNIMAC_MIB_TR2047_REG, }, + { "tx_2048_4095", GEN_MIB_STAT(tx_2048_4095), UNIMAC_MIB_TR4095_REG, }, + { "tx_4096_9216", GEN_MIB_STAT(tx_4096_9216), UNIMAC_MIB_TR9216_REG, }, + { "tx_all_pkts", GEN_MIB_STAT(tx_all_pkts), UNIMAC_MIB_GTPKT_REG, }, + { "tx_mult", GEN_MIB_STAT(tx_mult), UNIMAC_MIB_GTMCA_REG, }, + { "tx_brdcast", GEN_MIB_STAT(tx_brdcast), UNIMAC_MIB_GTBCA_REG, }, + { "tx_pause", GEN_MIB_STAT(tx_pause), UNIMAC_MIB_GTXPF_REG, }, + { "tx_control", GEN_MIB_STAT(tx_control), UNIMAC_MIB_GTXCF_REG, }, + { "tx_fcs", GEN_MIB_STAT(tx_fcs), UNIMAC_MIB_GTFCS_REG, }, + { "tx_oversize", GEN_MIB_STAT(tx_oversize), UNIMAC_MIB_GTOVR_REG, }, + { "tx_defer", GEN_MIB_STAT(tx_defer), UNIMAC_MIB_GTDRF_REG, }, + { "tx_ex_defer", GEN_MIB_STAT(tx_ex_defer), UNIMAC_MIB_GTEDF_REG, }, + { "tx_1_col", GEN_MIB_STAT(tx_1_col), UNIMAC_MIB_GTSCL_REG, }, + { "tx_m_col", GEN_MIB_STAT(tx_m_col), UNIMAC_MIB_GTMCL_REG, }, + { "tx_late_col", GEN_MIB_STAT(tx_late_col), UNIMAC_MIB_GTLCL_REG, }, + { "tx_ex_col", GEN_MIB_STAT(tx_ex_col), UNIMAC_MIB_GTXCL_REG, }, + { "tx_frag", GEN_MIB_STAT(tx_frag), UNIMAC_MIB_GTFRG_REG, }, + { "tx_col", GEN_MIB_STAT(tx_col), UNIMAC_MIB_GTNCL_REG, }, + { "tx_jabber", GEN_MIB_STAT(tx_jabber), UNIMAC_MIB_GTJBR_REG, }, + { "tx_gd_octets", GEN_MIB_STAT(tx_gd_octets), UNIMAC_MIB_GTBYT_REG, }, + { "tx_gd_pkts", GEN_MIB_STAT(tx_gd_pkts), UNIMAC_MIB_GTPOK_REG, }, + { "tx_unicast", GEN_MIB_STAT(tx_unicast), UNIMAC_MIB_GTUC_REG, }, + { "rx_runt0_pkts", GEN_MIB_STAT(rx_runt0_pkts), UNIMAC_MIB_RRPKT_REG, }, + { "rx_runt1_pkts", GEN_MIB_STAT(rx_runt1_pkts), UNIMAC_MIB_RRUND_REG, }, + { "rx_runt2_pkts", GEN_MIB_STAT(rx_runt2_pkts), UNIMAC_MIB_RRFRG_REG, }, + { "rx_runt2_bytes", GEN_MIB_STAT(rx_runt2_bytes), UNIMAC_MIB_RRBYT_REG, }, +}; + +/* + * read mib data + */ +static void mode_unimac_mib_update(void *mode_priv) +{ + struct unimac_priv *port = mode_priv; + size_t i; + + for (i = 0; i < ARRAY_SIZE(unimac_mib_estat); i++) { + const struct bcm_runner_ethtool_stat *s; + u32 val; + char *p; + + s = &unimac_mib_estat[i]; + + val = mac_mib_reg_readl(port, s->reg); + p = (char *)&port->mib + s->offset; + + if (s->size == sizeof(u64)) + *(u64 *)p = val; + else + *(u32 *)p = val; + } +} + +/* + * + */ +static void *mode_unimac_mib_get_data(void *mode_priv) +{ + struct unimac_priv *port = mode_priv; + return &port->mib; +} + + +/* + * reset unimac + */ +static void unimac_reset(struct unimac_priv *port) +{ + u32 val; + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val |= UNIMAC_CFG_CMD_SW_RESET_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); + msleep(1); + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val &= ~UNIMAC_CFG_CMD_SW_RESET_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); +} + +/* + * setup unimac for given speed + */ +static void unimac_setup(struct unimac_priv *port, unsigned int speed) +{ + u32 val; + + /* set correct speed */ + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val |= UNIMAC_CFG_CMD_CTRL_FRM_EN_MASK; + val |= UNIMAC_CFG_CMD_PROMISC_EN_MASK; + val &= ~UNIMAC_CFG_CMD_SPEED_MASK; + switch (speed) { + case 10: + val |= UNIMAC_CFG_CMD_SPEED_10 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + case 100: + val |= UNIMAC_CFG_CMD_SPEED_100 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + case 1000: + val |= UNIMAC_CFG_CMD_SPEED_1000 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + case 2500: + val |= UNIMAC_CFG_CMD_SPEED_2500 << UNIMAC_CFG_CMD_SPEED_SHIFT; + break; + } + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); + + val = mac_misc_reg_readl(port, UNIMAC_MISC_CFG_REG); + val |= UNIMAC_MISC_CFG_GMII_DIRECT_MASk; + mac_misc_reg_writel(port, UNIMAC_MISC_CFG_REG, val); +} + +/* + * + */ +static void unimac_enable(struct unimac_priv *port) +{ + u32 val; + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val |= UNIMAC_CFG_CMD_RX_EN_MASK; + val |= UNIMAC_CFG_CMD_TX_EN_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); +} + +/* + * disable unimac rx/tx + */ +static void unimac_disable(struct unimac_priv *port) +{ + u32 val; + + val = mac_misc_reg_readl(port, UNIMAC_MISC_CFG_REG); + val &= ~UNIMAC_MISC_CFG_GMII_DIRECT_MASk; + mac_misc_reg_writel(port, UNIMAC_MISC_CFG_REG, val); + + val = mac_cfg_reg_readl(port, UNIMAC_CFG_CMD_REG); + val &= ~UNIMAC_CFG_CMD_RX_EN_MASK; + val &= ~UNIMAC_CFG_CMD_TX_EN_MASK; + mac_cfg_reg_writel(port, UNIMAC_CFG_CMD_REG, val); + + unimac_reset(port); +} + +/* + * + */ +static void mode_unimac_mtu_set(void *mode_priv, unsigned int size) +{ + struct unimac_priv *port = mode_priv; + u32 val; + + /* set frame len */ + val = mac_cfg_reg_readl(port, UNIMAC_CFG_FRM_LEN_REG); + val |= port->priv->pkt_size; + mac_cfg_reg_writel(port, UNIMAC_CFG_FRM_LEN_REG, val); + + mac_cfg_reg_writel(port, UNIMAC_CFG_RX_MAX_PKT_SIZE_REG, size); +} + +/* + * + */ +static void mode_phylink_validate(void *mode_priv, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + phylink_set(mask, Autoneg); + phylink_set_port_modes(mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 2500baseT_Full); + + bitmap_and(supported, supported, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +/* + * + */ +static void mode_phylink_mac_config(void *mode_priv, + unsigned int pl_mode, + const struct phylink_link_state *state) +{ + struct unimac_priv *port = mode_priv; + unimac_setup(port, state->speed); +} + +/* + * + */ +static void mode_phylink_link_up(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + struct phy_device *phy) +{ + struct unimac_priv *port = mode_priv; + unimac_enable(port); +} + +/* + * + */ +static void mode_phylink_link_down(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface) +{ + struct unimac_priv *port = mode_priv; + unimac_disable(port); +} + +/* + * + */ +static void *mode_unimac_init(void *port_priv, + const struct bcm_xrdp_enet_params *params) + +{ + struct unimac_priv *port = port_priv; + port->regs = params->mac_regs; + return port_priv; +} + +static void mode_unimac_stop(void *mode_priv) +{ + struct unimac_priv *port = mode_priv; + bcm_runner_fw_tx_stop_wait(port->priv); +} + +/* + * + */ +static u32 mode_get_bbh_id(void *port_priv) +{ + struct unimac_priv *port = port_priv; + return port->bbh_id; +} + +/* + * + */ +static void mode_unimac_release(void *mode_priv) +{ +} + +const struct bcm_enet_mode_ops unimac_mode_ops = { + .name = "gmii", + + .init = mode_unimac_init, + .stop = mode_unimac_stop, + .release = mode_unimac_release, + .get_bbh_id = mode_get_bbh_id, + .mtu_set = mode_unimac_mtu_set, + + /* mib operation */ + .mib_estat = unimac_mib_estat, + .mib_estat_count = ARRAY_SIZE(unimac_mib_estat), + .mib_update = mode_unimac_mib_update, + .mib_get_data = mode_unimac_mib_get_data, + + /* + * phylink callback + */ + .phylink_validate = mode_phylink_validate, + .phylink_mac_config = mode_phylink_mac_config, + .phylink_link_down = mode_phylink_link_down, + .phylink_link_up = mode_phylink_link_up, +}; + +/* + * + */ +static void *unimac_port_init(struct bcm_enet_runner_priv *priv) +{ + struct unimac_priv *port; + int ret; + + port = devm_kzalloc(&priv->pdev->dev, sizeof (*port), GFP_KERNEL); + if (!port) + return ERR_PTR(-ENODEV); + + port->priv = priv; + + ret = of_property_read_u32(priv->pdev->dev.of_node, + "enet-runner,bbh", + &port->bbh_id); + if (ret) + return ERR_PTR(ret); + + return port; +} + +/* + * + */ +static void unimac_port_release(void *data) +{ + struct unimac_priv *port = data; + devm_kfree(&port->priv->pdev->dev, port); +} + +const struct bcm_enet_port_ops port_unimac_ops = { + .modes = { + &unimac_mode_ops, + }, + .mode_count = 1, + + .init = unimac_port_init, + .release = unimac_port_release, +}; diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_unimac.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_unimac.h 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,119 @@ +#ifndef PORT_UNIMAC_H_ +#define PORT_UNIMAC_H_ + +#include "bcm63158_enet_runner.h" +#include "regs/unimac_regs.h" + +/* + * unimac MIB + */ +struct unimac_mib { + u32 rx_64; + u32 rx_65_127; + u32 rx_128_255; + u32 rx_256_511; + u32 rx_512_1023; + u32 rx_1024_1518; + u32 rx_1519_1522_vlan; + u32 rx_1519_2047; + u32 rx_2048_4095; + u32 rx_4096_9216; + + u32 rx_all_pkts; + u64 rx_all_octets; + u32 rx_mult; + u32 rx_brdcast; + u32 rx_crc; + u32 rx_cntrl; + u32 rx_pause; + u32 rx_und; + u32 rx_align; + u32 rx_frame_len; + u32 rx_code; + u32 rx_carrier; + u32 rx_oversize; + u32 rx_jabber; + u32 rx_too_big; + + u32 rx_gd_pkts; + u32 rx_unicast; + u32 rx_ppp; + u32 rx_crc_match; + + u32 tx_64; + u32 tx_65_127; + u32 tx_128_255; + u32 tx_256_511; + u32 tx_512_1023; + u32 tx_1024_1518; + u32 tx_1519_1522_vlan; + u32 tx_1523_2047; + u32 tx_2048_4095; + u32 tx_4096_9216; + + u32 tx_all_pkts; + u32 tx_mult; + u32 tx_brdcast; + u32 tx_pause; + u32 tx_control; + u32 tx_fcs; + u32 tx_oversize; + u32 tx_defer; + u32 tx_ex_defer; + u32 tx_1_col; + u32 tx_m_col; + u32 tx_late_col; + u32 tx_ex_col; + u32 tx_frag; + u32 tx_col; + u32 tx_jabber; + + u64 tx_gd_octets; + u32 tx_gd_pkts; + u32 tx_unicast; + + u32 rx_runt0_pkts; + u32 rx_runt1_pkts; + u32 rx_runt2_pkts; + u32 rx_runt2_bytes; +}; + +struct unimac_priv { + struct bcm_enet_runner_priv *priv; + void __iomem *regs; + struct unimac_mib mib; + u32 bbh_id; +}; + +/* + * io accessors + */ +static inline u32 mac_cfg_reg_readl(struct unimac_priv *port, u32 offset) +{ + return ioread32(port->regs + UNIMAC_CFG_OFFSET(port->bbh_id) + offset); +} + +static inline void mac_cfg_reg_writel(struct unimac_priv *port, u32 offset, + u32 val) +{ + iowrite32(val, port->regs + UNIMAC_CFG_OFFSET(port->bbh_id) + offset); +} + +static inline u32 mac_misc_reg_readl(struct unimac_priv *port, u32 offset) +{ + return ioread32(port->regs + UNIMAC_MISC_OFFSET(port->bbh_id) + offset); +} + +static inline void mac_misc_reg_writel(struct unimac_priv *port, u32 offset, + u32 val) +{ + iowrite32(val, port->regs + UNIMAC_MISC_OFFSET(port->bbh_id) + offset); +} + +static inline u32 mac_mib_reg_readl(struct unimac_priv *port, u32 offset) +{ + return ioread32(port->regs + UNIMAC_MIB_OFFSET(port->bbh_id) + offset); +} + + +#endif /* PORT_UNIMAC_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.c 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,130 @@ +#include "port_xport.h" + +/* + * + */ +static void *xport_init(struct bcm_enet_runner_priv *priv) +{ + struct resource *res_wan_top; + struct resource *res_xport; + struct resource *res_xlif; + struct resource *res_epon; + struct reset_control *wan_ae_rst; + struct xport_priv *port; + int ret; + + port = devm_kzalloc(&priv->pdev->dev, sizeof (*port), GFP_KERNEL); + if (!port) + return ERR_PTR(-ENODEV); + + port->priv = priv; + + ret = of_property_read_u32(priv->pdev->dev.of_node, + "enet-runner,xport-ae-bbh", + &port->ae_bbh_id); + if (ret) + return ERR_PTR(ret); + + ret = of_property_read_u32(priv->pdev->dev.of_node, + "enet-runner,xport-pon-bbh", + &port->pon_bbh_id); + if (ret) + return ERR_PTR(ret); + + res_wan_top = platform_get_resource_byname(priv->pdev, + IORESOURCE_MEM, "wan_top"); + if (!res_wan_top) { + dev_err(&priv->pdev->dev, "unable to get wan_top resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[0] = devm_ioremap_resource(&priv->pdev->dev, res_wan_top); + if (IS_ERR(port->regs[0])) { + dev_err(&priv->pdev->dev, "unable to ioremap regs\n"); + return port->regs[0]; + } + port->regs_size[0] = resource_size(res_wan_top); + + res_xport = platform_get_resource_byname(priv->pdev, + IORESOURCE_MEM, "xport"); + if (!res_xport) { + dev_err(&priv->pdev->dev, "unable to get xport resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[1] = devm_ioremap_resource(&priv->pdev->dev, res_xport); + if (IS_ERR(port->regs[1])) { + dev_err(&priv->pdev->dev, "unable to ioremap regs\n"); + return port->regs[1]; + } + port->regs_size[1] = resource_size(res_xport); + + res_xlif = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, + "xlif"); + if (!res_xlif) { + dev_err(&priv->pdev->dev, "unable to get xlif resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[2] = devm_ioremap_resource(&priv->pdev->dev, res_xlif); + if (IS_ERR(port->regs[2])) { + dev_err(&priv->pdev->dev, "unable to ioremap regs\n"); + return port->regs[2]; + } + port->regs_size[2] = resource_size(res_xlif); + + res_epon = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, + "epon"); + if (!res_epon) { + dev_err(&priv->pdev->dev, "unable to get epon resource\n"); + return ERR_PTR(-ENODEV); + } + + port->regs[3] = devm_ioremap_resource(&priv->pdev->dev, res_epon); + if (IS_ERR(port->regs[3])) { + dev_err(&priv->pdev->dev, "unable to ioremap epon regs\n"); + return port->regs[3]; + } + port->regs_size[3] = resource_size(res_epon); + + wan_ae_rst = devm_reset_control_get(&priv->pdev->dev, "wan_ae"); + if (IS_ERR(wan_ae_rst)) { + dev_err(&priv->pdev->dev, "missing wan_ae reset control: %ld\n", + PTR_ERR(wan_ae_rst)); + return ERR_PTR(-ENODEV); + } + port->wan_ae_rst = wan_ae_rst; + + /* + * default to forcing LBE to 1, this is connected to TX + * disabled so it will disable TX by default + * + * this is only applied by AE mode, the PON mode will disable + * it + * + */ + port->lbe_force = true; + port->lbe_force_value = true; + + return port; +} + +/* + * + */ +static void xport_release(void *data) +{ + struct xport_priv *port = data; + devm_kfree(&port->priv->pdev->dev, port); +} + +const struct bcm_enet_port_ops port_xport_ops = { + .modes = { + &xport_xlmac_mode_ops, + &xport_epon_mode_ops, + }, + .mode_count = 2, + + .init = xport_init, + .release = xport_release, +}; diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.c 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,3162 @@ +#include "port_xport_epon.h" +#include "regs/serdes_regs.h" + +/* + * maximum number of LLID supported by hardware + */ +#define BCM_LLID_COUNT 32 +#define BCM_L2_COUNT BCM_LLID_COUNT + +/* + * maximum number of pending grants per LLID for hardware + */ +#define BCM_MAX_PENDING_GRANTS 16 + +/* + * estimated time from packet xmit to actual hardware tx, used during + * discovery to avoid scheduling packet in the past + */ +#define SOFTWARE_TX_LATENCY_TQ USEC_TO_TQ(20) + +/* + * llid index we force, to ease debugging + */ +#define USER_LLID_IDX 0 +#define BROADCAST_LLID_IDX 31 + +/* + * default burst cap + */ +#define DEFAULT_BURST_CAP 1024 + +/* + * standard MPCP frame destination address + */ +static const u8 mpcp_frame_da[6] = { 0x01, 0x80, 0xc2, 0x00, 0x00, 0x01 }; + +enum epon_stat_type { + EPON_STAT_XPCS_RX, + EPON_STAT_XPCS_RX64, + EPON_STAT_XIF, + EPON_STAT_LIF, + EPON_STAT_EPN, + EPON_STAT_EPN_RAM, + EPON_STAT_EPN_L1_ACC, + EPON_STAT_LOCAL, +}; + +#define GEN_MIB_STAT(m) \ + sizeof(((struct eponmac_mib *)0)->m), \ + offsetof(struct eponmac_mib, m) + +#define GEN_EPN_RAM_STAT(m, llid, port, ram_off) \ + #m, \ + GEN_MIB_STAT(m), \ + ((llid << 24) | (port << 16) | ram_off), \ + EPON_STAT_EPN_RAM, + +#define GEN_LOCAL_STAT(m) \ + #m, \ + GEN_MIB_STAT(m), \ + 0, \ + EPON_STAT_LOCAL, + +const struct bcm_runner_ethtool_stat epon_mib_estat[] = { + { "xpcs_rx_framer_misbrst", GEN_MIB_STAT(xpcs_rx_framer_misbrst), + XPCSRX_RX_FRAMER_MISBRST_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_framer_bd_err", GEN_MIB_STAT(xpcs_rx_framer_bd_err), + XPCSRX_RX_FRAMER_BD_ERR_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_64b66b_ipg_det", GEN_MIB_STAT(xpcs_rx_64b66b_ipg_det), + XPCSRX_RX_64B66B_IPG_DET_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_nque_in", GEN_MIB_STAT(xpcs_rx_fec_nque_in), + XPCSRX_RX_FEC_NQUE_IN_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_nque_out", GEN_MIB_STAT(xpcs_rx_fec_nque_out), + XPCSRX_RX_FEC_NQUE_OUT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_start", GEN_MIB_STAT(xpcs_rx_idle_start), + XPCSRX_RX_IDLE_START_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_stop", GEN_MIB_STAT(xpcs_rx_idle_stop), + XPCSRX_RX_IDLE_STOP_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_cw_fail", GEN_MIB_STAT(xpcs_rx_fec_cw_fail), + XPCSRX_RX_FEC_CW_FAIL_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_cw_tot", GEN_MIB_STAT(xpcs_rx_fec_cw_tot), + XPCSRX_RX_FEC_CW_TOT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_fec_correct", GEN_MIB_STAT(xpcs_rx_fec_correct), + XPCSRX_RX_FEC_CORRECT_CNT_LO_REG, EPON_STAT_XPCS_RX64, }, + { "xpcs_rx_fec_ones_cor", GEN_MIB_STAT(xpcs_rx_fec_ones_cor), + XPCSRX_RX_FEC_ONES_COR_CNT_LO_REG, EPON_STAT_XPCS_RX64, }, + { "xpcs_rx_fec_zeros_cor", GEN_MIB_STAT(xpcs_rx_fec_zeros_cor), + XPCSRX_RX_FEC_ZEROS_COR_CNT_LO_REG, EPON_STAT_XPCS_RX64, }, + { "xpcs_rx_64b66b_fail", GEN_MIB_STAT(xpcs_rx_64b66b_fail), + XPCSRX_RX_64B66B_FAIL_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_frmr_bad_sh", GEN_MIB_STAT(xpcs_rx_frmr_bad_sh), + XPCSRX_RX_FRMR_BAD_SH_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_psudo", GEN_MIB_STAT(xpcs_rx_psudo), + XPCSRX_RX_PSUDO_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_prbs", GEN_MIB_STAT(xpcs_rx_prbs), + XPCSRX_RX_PRBS_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_64b66b_start", GEN_MIB_STAT(xpcs_rx_64b66b_start), + XPCSRX_RX_64B66B_START_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_good_pkt", GEN_MIB_STAT(xpcs_rx_idle_good_pkt), + XPCSRX_RX_IDLE_GOOD_PKT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_idle_err_pkt", GEN_MIB_STAT(xpcs_rx_idle_err_pkt), + XPCSRX_RX_IDLE_ERR_PKT_CNT_REG, EPON_STAT_XPCS_RX, }, + { "xpcs_rx_64b66b_stop", GEN_MIB_STAT(xpcs_rx_64b66b_stop), + XPCSRX_RX_64B66B_STOP_CNT_REG, EPON_STAT_XPCS_RX, }, + + { "xif_pmc_frame_rx", GEN_MIB_STAT(xif_pmc_frame_rx), + XIF_PMC_FRAME_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_byte_rx", GEN_MIB_STAT(xif_pmc_byte_rx), + XIF_PMC_BYTE_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_runt_rx", GEN_MIB_STAT(xif_pmc_runt_rx), + XIF_PMC_RUNT_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_cw_err_rx", GEN_MIB_STAT(xif_pmc_cw_err_rx), + XIF_PMC_CW_ERR_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_crc8_err_rx", GEN_MIB_STAT(xif_pmc_crc8_err_rx), + XIF_PMC_CRC8_ERR_RX_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_data_frm_tx", GEN_MIB_STAT(xif_xpn_data_frm), + XIF_XPN_DATA_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_data_byte_tx", GEN_MIB_STAT(xif_xpn_data_byte), + XIF_XPN_DATA_BYTE_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_mpcp_frm_tx", GEN_MIB_STAT(xif_xpn_mpcp_frm), + XIF_XPN_MPCP_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_oam_frm_tx", GEN_MIB_STAT(xif_xpn_oam_frm), + XIF_XPN_OAM_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_oam_byte_tx", GEN_MIB_STAT(xif_xpn_oam_byte), + XIF_XPN_OAM_BYTE_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_oversize_frm_tx", GEN_MIB_STAT(xif_xpn_oversize_frm), + XIF_XPN_OVERSIZE_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_sec_abort_frm_rx", GEN_MIB_STAT(xif_sec_abort_frm), + XIF_SEC_ABORT_FRM_CNT_REG, EPON_STAT_XIF, }, + { "xif_pmc_tx_neg_event", GEN_MIB_STAT(xif_pmc_tx_neg_event), + XIF_PMC_TX_NEG_EVENT_CNT_REG, EPON_STAT_XIF, }, + { "xif_xpn_idle_pkt", GEN_MIB_STAT(xif_xpn_idle_pkt), + XIF_XPN_IDLE_PKT_CNT_REG, EPON_STAT_XIF, }, + + { "lif_rx_line_code_err_cnt", GEN_MIB_STAT(lif_rx_line_code_err_cnt), + LIF_RX_LINE_CODE_ERR_CNT_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_mpcp_frm", GEN_MIB_STAT(lif_rx_agg_mpcp_frm), + LIF_RX_AGG_MPCP_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_good_frm", GEN_MIB_STAT(lif_rx_agg_good_frm), + LIF_RX_AGG_GOOD_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_good_byte", GEN_MIB_STAT(lif_rx_agg_good_byte), + LIF_RX_AGG_GOOD_BYTE_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_undersz_frm", GEN_MIB_STAT(lif_rx_agg_undersz_frm), + LIF_RX_AGG_UNDERSZ_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_oversz_frm", GEN_MIB_STAT(lif_rx_agg_oversz_frm), + LIF_RX_AGG_OVERSZ_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_crc8_frm", GEN_MIB_STAT(lif_rx_agg_crc8_frm), + LIF_RX_AGG_CRC8_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_fec_frm", GEN_MIB_STAT(lif_rx_agg_fec_frm), + LIF_RX_AGG_FEC_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_fec_byte", GEN_MIB_STAT(lif_rx_agg_fec_byte), + LIF_RX_AGG_FEC_BYTE_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_fec_exc_err_frm", + GEN_MIB_STAT(lif_rx_agg_fec_exc_err_frm), + LIF_RX_AGG_FEC_EXC_ERR_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_nonfec_good_frm", + GEN_MIB_STAT(lif_rx_agg_nonfec_good_frm), + LIF_RX_AGG_NONFEC_GOOD_FRM_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_nonfec_good_byte", + GEN_MIB_STAT(lif_rx_agg_nonfec_good_byte), + LIF_RX_AGG_NONFEC_GOOD_BYTE_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_bytes", GEN_MIB_STAT(lif_rx_agg_err_bytes), + LIF_RX_AGG_ERR_BYTES_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_zeroes", GEN_MIB_STAT(lif_rx_agg_err_zeroes), + LIF_RX_AGG_ERR_ZEROES_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_no_err_blks", GEN_MIB_STAT(lif_rx_agg_no_err_blks), + LIF_RX_AGG_NO_ERR_BLKS_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_cor_blks", GEN_MIB_STAT(lif_rx_agg_cor_blks), + LIF_RX_AGG_COR_BLKS_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_uncor_blks", GEN_MIB_STAT(lif_rx_agg_uncor_blks), + LIF_RX_AGG_UNCOR_BLKS_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_ones", GEN_MIB_STAT(lif_rx_agg_err_ones), + LIF_RX_AGG_ERR_ONES_REG, EPON_STAT_LIF, }, + { "lif_rx_agg_err_frm", GEN_MIB_STAT(lif_rx_agg_err_frm), + LIF_RX_AGG_ERR_FRM_REG, EPON_STAT_LIF, }, + { "lif_tx_pkt_cnt", GEN_MIB_STAT(lif_tx_pkt_cnt), + LIF_TX_PKT_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_byte_cnt", GEN_MIB_STAT(lif_tx_byte_cnt), + LIF_TX_BYTE_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_non_fec_pkt_cnt", GEN_MIB_STAT(lif_tx_non_fec_pkt_cnt), + LIF_TX_NON_FEC_PKT_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_non_fec_byte_cnt", GEN_MIB_STAT(lif_tx_non_fec_byte_cnt), + LIF_TX_NON_FEC_BYTE_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_fec_pkt_cnt", GEN_MIB_STAT(lif_tx_fec_pkt_cnt), + LIF_TX_FEC_PKT_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_fec_byte_cnt", GEN_MIB_STAT(lif_tx_fec_byte_cnt), + LIF_TX_FEC_BYTE_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_fec_blk_cnt", GEN_MIB_STAT(lif_tx_fec_blk_cnt), + LIF_TX_FEC_BLK_CNT_REG, EPON_STAT_LIF, }, + { "lif_tx_mpcp_pkt_cnt", GEN_MIB_STAT(lif_tx_mpcp_pkt_cnt), + LIF_TX_MPCP_PKT_CNT_REG, EPON_STAT_LIF, }, + + { GEN_EPN_RAM_STAT(epn00_rx_bytes, 0, 0, 0) }, + { GEN_EPN_RAM_STAT(epn00_rx_fcs, 0, 0, 1) }, + { GEN_EPN_RAM_STAT(epn00_rx_oam, 0, 0, 2) }, + { GEN_EPN_RAM_STAT(epn00_rx_gate, 0, 0, 3) }, + { GEN_EPN_RAM_STAT(epn00_rx_64, 0, 0, 4) }, + { GEN_EPN_RAM_STAT(epn00_rx_65_127, 0, 0, 5) }, + { GEN_EPN_RAM_STAT(epn00_rx_128_255, 0, 0, 6) }, + { GEN_EPN_RAM_STAT(epn00_rx_256_511, 0, 0, 7) }, + { GEN_EPN_RAM_STAT(epn00_rx_512_1023, 0, 0, 8) }, + { GEN_EPN_RAM_STAT(epn00_rx_1024_1518, 0, 0, 9) }, + { GEN_EPN_RAM_STAT(epn00_rx_1519_2047, 0, 0, 10) }, + { GEN_EPN_RAM_STAT(epn00_rx_2048_4095, 0, 0, 11) }, + { GEN_EPN_RAM_STAT(epn00_rx_4096_9216, 0, 0, 12) }, + { GEN_EPN_RAM_STAT(epn00_rx_gt_9216, 0, 0, 13) }, + { GEN_EPN_RAM_STAT(epn00_rx_oversize, 0, 0, 14) }, + { GEN_EPN_RAM_STAT(epn00_rx_bcast, 0, 0, 15) }, + { GEN_EPN_RAM_STAT(epn00_rx_mcast, 0, 0, 16) }, + { GEN_EPN_RAM_STAT(epn00_rx_unicast, 0, 0, 17) }, + { GEN_EPN_RAM_STAT(epn00_rx_undersized, 0, 0, 18) }, + { GEN_EPN_RAM_STAT(epn00_rx_oam_bytes, 0, 0, 19) }, + { GEN_EPN_RAM_STAT(epn00_rx_register, 0, 0, 20) }, + + { GEN_EPN_RAM_STAT(epn00_tx_bytes, 0, 1, 0) }, + { GEN_EPN_RAM_STAT(epn00_tx_oam, 0, 1, 1) }, + { GEN_EPN_RAM_STAT(epn00_tx_report, 0, 1, 2) }, + { GEN_EPN_RAM_STAT(epn00_tx_64, 0, 1, 3) }, + { GEN_EPN_RAM_STAT(epn00_tx_65_127, 0, 1, 4) }, + { GEN_EPN_RAM_STAT(epn00_tx_128_255, 0, 1, 5) }, + { GEN_EPN_RAM_STAT(epn00_tx_256_511, 0, 1, 6) }, + { GEN_EPN_RAM_STAT(epn00_tx_512_1023, 0, 1, 7) }, + { GEN_EPN_RAM_STAT(epn00_tx_1024_1518, 0, 1, 8) }, + { GEN_EPN_RAM_STAT(epn00_tx_1519_2047, 0, 1, 9) }, + { GEN_EPN_RAM_STAT(epn00_tx_2048_4095, 0, 1, 10) }, + { GEN_EPN_RAM_STAT(epn00_tx_4096_9216, 0, 1, 11) }, + { GEN_EPN_RAM_STAT(epn00_tx_gt_9216, 0, 1, 12) }, + { GEN_EPN_RAM_STAT(epn00_tx_oam_bytes, 0, 1, 13) }, + { GEN_EPN_RAM_STAT(epn00_tx_bcast, 0, 1, 14) }, + { GEN_EPN_RAM_STAT(epn00_tx_mcast, 0, 1, 15) }, + { GEN_EPN_RAM_STAT(epn00_tx_unicast, 0, 1, 16) }, + { "epn00_unused_tq", GEN_MIB_STAT(epn00_unused_tq), + 0, EPN_UNUSED_TQ_CNTx_0_7_REG(0), }, + { "epn00_l1_acc_bytes", GEN_MIB_STAT(epn00_l1_acc_bytes), + 0, EPON_STAT_EPN_L1_ACC, }, + + { GEN_EPN_RAM_STAT(epn24_rx_bytes, 24, 0, 0) }, + { GEN_EPN_RAM_STAT(epn24_rx_fcs, 24, 0, 1) }, + { GEN_EPN_RAM_STAT(epn24_rx_bcast, 24, 0, 15) }, + { GEN_EPN_RAM_STAT(epn24_rx_mcast, 24, 0, 16) }, + { GEN_EPN_RAM_STAT(epn25_rx_bytes, 25, 0, 0) }, + { GEN_EPN_RAM_STAT(epn25_rx_fcs, 25, 0, 1) }, + { GEN_EPN_RAM_STAT(epn25_rx_bcast, 25, 0, 15) }, + { GEN_EPN_RAM_STAT(epn25_rx_mcast, 25, 0, 16) }, + { GEN_EPN_RAM_STAT(epn26_rx_bytes, 26, 0, 0) }, + { GEN_EPN_RAM_STAT(epn26_rx_fcs, 26, 0, 1) }, + { GEN_EPN_RAM_STAT(epn26_rx_bcast, 26, 0, 15) }, + { GEN_EPN_RAM_STAT(epn26_rx_mcast, 26, 0, 16) }, + { GEN_EPN_RAM_STAT(epn27_rx_bytes, 27, 0, 0) }, + { GEN_EPN_RAM_STAT(epn27_rx_fcs, 27, 0, 1) }, + { GEN_EPN_RAM_STAT(epn27_rx_bcast, 27, 0, 15) }, + { GEN_EPN_RAM_STAT(epn27_rx_mcast, 27, 0, 16) }, + { GEN_EPN_RAM_STAT(epn28_rx_bytes, 28, 0, 0) }, + { GEN_EPN_RAM_STAT(epn28_rx_fcs, 28, 0, 1) }, + { GEN_EPN_RAM_STAT(epn28_rx_bcast, 28, 0, 15) }, + { GEN_EPN_RAM_STAT(epn28_rx_mcast, 28, 0, 16) }, + { GEN_EPN_RAM_STAT(epn29_rx_bytes, 29, 0, 0) }, + { GEN_EPN_RAM_STAT(epn29_rx_fcs, 29, 0, 1) }, + { GEN_EPN_RAM_STAT(epn29_rx_bcast, 29, 0, 15) }, + { GEN_EPN_RAM_STAT(epn29_rx_mcast, 29, 0, 16) }, + { GEN_EPN_RAM_STAT(epn30_rx_bytes, 30, 0, 0) }, + { GEN_EPN_RAM_STAT(epn30_rx_fcs, 30, 0, 1) }, + { GEN_EPN_RAM_STAT(epn30_rx_bcast, 30, 0, 15) }, + { GEN_EPN_RAM_STAT(epn30_rx_mcast, 30, 0, 16) }, + { GEN_EPN_RAM_STAT(epn31_rx_bytes, 31, 0, 0) }, + { GEN_EPN_RAM_STAT(epn31_rx_fcs, 31, 0, 1) }, + { GEN_EPN_RAM_STAT(epn31_rx_bcast, 31, 0, 15) }, + { GEN_EPN_RAM_STAT(epn31_rx_mcast, 31, 0, 16) }, + + { "epn_unmap_big", GEN_MIB_STAT(epn_unmap_big), + EPN_UNMAP_BIG_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_frame", GEN_MIB_STAT(epn_unmap_frame), + EPN_UNMAP_FRAME_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_fcs", GEN_MIB_STAT(epn_unmap_fcs), + EPN_UNMAP_FCS_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_gate", GEN_MIB_STAT(epn_unmap_gate), + EPN_UNMAP_GATE_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_oam", GEN_MIB_STAT(epn_unmap_oam), + EPN_UNMAP_OAM_CNT_REG, EPON_STAT_EPN, }, + { "epn_unmap_small", GEN_MIB_STAT(epn_unmap_small), + EPN_UNMAP_SMALL_CNT_REG, EPON_STAT_EPN, }, + + { GEN_LOCAL_STAT(reg_mpcp_rx) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_invalid) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_unk_opcode) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc_info_mismatch) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc_late) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_disc_last_slot) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_for_other) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_unk_flag) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_dereg) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_nack) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_reg_timeout) }, + { GEN_LOCAL_STAT(reg_mpcp_rx_other_err) }, + { GEN_LOCAL_STAT(reg_mpcp_tx_reg_req) }, + { GEN_LOCAL_STAT(reg_mpcp_tx_reg_ack) }, +}; + +/* + * + */ +static const struct serdes_params serdes_params_10g_1g = { + .misc3_if_select = 5, + .misc3_laser_mode = 0, + + .tx_pll_vco_div2 = 0x0, + .rx_pll_vco_div2 = 0x0, + .tx_pll_vco_div4 = 0x0, + .rx_pll_vco_div4 = 0x0, + .rx_pll_id = serdes_PLL_1, + .tx_pll_id = serdes_PLL_0, + + .tx_pll_force_kvh_bw = 0x1, + .rx_pll_force_kvh_bw = 0x1, + .tx_pll_kvh_force = 0x1, + .rx_pll_kvh_force = 0x1, + + .tx_pll_2rx_bw = 0x0, + .rx_pll_2rx_bw = 0x0, + + .tx_pll_fracn_sel = 0x1, + .rx_pll_fracn_sel = 0x1, + + .tx_pll_ditheren = 0x1, + .rx_pll_ditheren = 0x1, + + .rx_pll_fracn_div = 0x10000, + .rx_pll_fracn_ndiv = 0x0ce, + + .tx_pll_fracn_div = 0x00000, + .tx_pll_fracn_ndiv = 0x0c8, + + .rx_pll_mode = 0x5, + .tx_pll_mode = 0x5, + + .rx_tx_rate_ratio = 0x5, + + .rx_pon_mac_ctrl = 0x7, + .tx_pon_mac_ctrl = 0x0, + .tx_sync_e_ctrl = 0x0, + + .rx_osr_mode = 0x0, + .tx_osr_mode = 0x7, + + .do_rx_pi_spacing = true, + .clk90_offset = 32, + .p1_offset = 0, + .dsc_a_cdr_control_2 = 0x030, + + .do_pll_charge_pump = true, + .do_pll_charge_pump_10g = true, + .do_vga_rf = true, + .do_ae = false, + .do_sigdetect = false, + .serdes_ae_full_rate = false, + .serdes_ae_20b_width = false, +}; + +/* + * + */ +static u32 extract_mac_addr_lo(const u8 *addr) +{ + return ((u32)addr[2] << 24) | + ((u32)addr[3] << 16) | + ((u32)addr[4] << 8) | + ((u32)addr[5]); +} + +/* + * + */ +static u32 extract_mac_addr_hi(const u8 *addr) +{ + return ((u32)addr[0] << 8) | addr[1]; +} + +/* + * + */ +static u32 get_register_req_data_size(bool include_preambles) +{ + size_t len = 0; + + if (include_preambles) + len += PREAMBLE_LEN_BYTES; + /* ethernet payload cannot be smaller than 60 or it has to be + * padded */ + len += max_t(size_t, + ETH_HLEN + + sizeof (struct mpcp_hdr) + + sizeof (struct mpcp_register_req), + ETH_ZLEN); + if (include_preambles) { + len += ETH_FCS_LEN; + len += IPG_BYTES_1G; + } + return len; +} + +/* + * + */ +static u32 get_register_req_data_duration(struct xport_epon_priv *mode) +{ + if (mode->up_speed == 1000) + return BYTES_TO_TQ_1G(get_register_req_data_size(true)); + else { + /* FIXME: implement */ + BUG(); + } +} + +/* + * + */ +static u16 get_broadcast_llid(struct xport_epon_priv *mode) +{ + if (mode->down_speed == 10000) + return BROADCAST_LLID_10G; + else + return BROADCAST_LLID_1G; +} + +/* + * + */ +static u16 get_disc_info_caps(struct xport_epon_priv *mode, u16 *mask) +{ + u16 value = 0; + + /* OLT must support our upstream speed */ + if (mode->up_speed == 1000) { + if (mask) + *mask &= ~MPCP_DISCINFO_1G_CAP; + value |= MPCP_DISCINFO_1G_CAP; + } else { + if (mask) + *mask &= ~MPCP_DISCINFO_10G_CAP; + value |= MPCP_DISCINFO_10G_CAP; + } + + /* only use discovery window for our upstream speed */ + if (mode->up_speed == 1000) { + if (mask) + *mask &= ~MPCP_DISCINFO_1G_WINDOW; + value |= MPCP_DISCINFO_1G_WINDOW; + } else { + if (mask) + *mask &= ~MPCP_DISCINFO_10G_WINDOW; + value |= MPCP_DISCINFO_10G_WINDOW; + } + return value; +} + +/* + * + */ +static void epon_reset_modules(struct xport_epon_priv *mode, + bool active, u32 mask) +{ + u32 val; + + val = epon_top_reg_readl(mode, EPON_TOP_RESET_REG); + /* reset is active low */ + if (!active) + val |= mask; + else + val &= ~mask; + epon_top_reg_writel(mode, EPON_TOP_RESET_REG, val); +} + +/* + * + */ +static int xpcs_rx_init(struct xport_epon_priv *mode) +{ + u32 val; + size_t i; + + /* release xpcs rx reset */ + epon_reset_modules(mode, false, RESET_XPCSRXRST_N_MASK); + msleep(20); + + val = epon_xpcsrx_reg_readl(mode, XPCSRX_RX_RST_REG); + val |= RX_RST_CFGXPCSRXCLK161RSTN_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_RST_REG, val); + udelay(10); + + /* poll until ready */ + for (i = 0; i < 100; i++) { + val = epon_xpcsrx_reg_readl(mode, XPCSRX_RX_RAM_ECC_INT_STAT_REG); + if (val & RX_RAM_ECC_INT_STAT_INTRXIDLERAMINITDONE_MASK) + break; + msleep(1); + } + + if (!(val & RX_RAM_ECC_INT_STAT_INTRXIDLERAMINITDONE_MASK)) { + netdev_err(mode->port->priv->netdev, + "xpcsrx RAM init failed\n"); + return 1; + } + + /* start with FEC enabled */ + val = RX_FRAMER_CTL_CFGXPCSRXFRMREN_MASK | + RX_FRAMER_CTL_CFGXPCSRXFRAMEFEC_MASK | + RX_FRAMER_CTL_CFGXPCSRXFRMREBDVLDEN_MASK | + RX_FRAMER_CTL_CFGXPCSRXFRMRSPULKEN_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_FRAMER_CTL_REG, val); + + val = RX_FEC_CTL_CFGXPCSRXFECEN_MASK | + RX_FEC_CTL_CFGXPCSRXFECIDLEINS_MASK | + RX_FEC_CTL_CFGXPCSRXFECFAILBLKSH0_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_FEC_CTL_REG, val); + + val = RX_INT_STAT_INTRXIDLEDAJIT_MASK | + RX_INT_STAT_INTRXFRMRMISBRST_MASK | + RX_INT_STAT_INTRXIDLESOPEOPGAPBIG_MASK | + RX_INT_STAT_INTRXIDLEFRCINS_MASK | + RX_INT_STAT_INTRX64B66BMINIPGERR_MASK | + RX_INT_STAT_INTRXFECNQUECNTNEQ_MASK | + RX_INT_STAT_INTRXIDLEFIFOUNDRUN_MASK | + RX_INT_STAT_INTRXIDLEFIFOOVRRUN_MASK | + RX_INT_STAT_INTRXFECHIGHCOR_MASK | + RX_INT_STAT_INTRXFECDECSTOPONERR_MASK | + RX_INT_STAT_INTRXFECDECPASS_MASK | + RX_INT_STAT_INTRXSTATFRMRHIGHBER_MASK | + RX_INT_STAT_INTRXFRMREXITBYSP_MASK | + RX_INT_STAT_INTRXFRMRBADSHMAX_MASK | + RX_INT_STAT_INTRXDSCRAMBURSTSEQOUT_MASK | + RX_INT_STAT_INTRXTESTPSUDOLOCK_MASK | + RX_INT_STAT_INTRXTESTPSUDOTYPE_MASK | + RX_INT_STAT_INTRXTESTPSUDOERR_MASK | + RX_INT_STAT_INTRXTESTPRBSLOCK_MASK | + RX_INT_STAT_INTRXTESTPRBSERR_MASK | + RX_INT_STAT_INTRXFECPSISTDECFAIL_MASK | + RX_INT_STAT_INTRXFRAMERBADSH_MASK | + RX_INT_STAT_INTRXFRAMERCWLOSS_MASK | + RX_INT_STAT_INTRXFRAMERCWLOCK_MASK | + RX_INT_STAT_INTRXFECDECFAIL_MASK | + RX_INT_STAT_INTRX64B66BDECERR_MASK | + RX_INT_STAT_INTRXFRMRNOLOCKLOS_MASK | + RX_INT_STAT_INTRXFRMRROGUE_MASK | + RX_INT_STAT_INT_REGS_ERR_MASK; + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_INT_STAT_REG, val); + + return 0; +} + +/* + * + */ +static void xif_set_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int llid, + bool enabled) +{ + u32 val; + + val = epon_xif_reg_readl(mode, XIF_LLIDx_0_31_REG(llid_idx)); + val &= ~XIF_LLIDx_0_31_CFGONULLID0_MASK; + val |= llid << XIF_LLIDx_0_31_CFGONULLID0_SHIFT; + if (enabled) + val |= (1 << (16 + XIF_LLIDx_0_31_CFGONULLID0_SHIFT)); + else + val &= ~(1 << (16 + XIF_LLIDx_0_31_CFGONULLID0_SHIFT)); + epon_xif_reg_writel(mode, XIF_LLIDx_0_31_REG(llid_idx), val); +} + +/* + * + */ +static u32 xif_get_local_mpcp_time(struct xport_epon_priv *mode) +{ + return epon_xif_reg_readl(mode, XIF_MPCP_TIME_REG); +} + +/* + * + */ +static int xif_data_port_write(struct xport_epon_priv *mode, + unsigned int port, + u32 addr) +{ + u32 val; + size_t i; + + val = (addr << XIF_PORT_COMMAND_PORTADDRESS_SHIFT) | + (1 << XIF_PORT_COMMAND_PORTOPCODE_SHIFT) | + (port << XIF_PORT_COMMAND_PORTSELECT_SHIFT); + + epon_xif_reg_writel(mode, XIF_PORT_COMMAND_REG, val); + + for (i = 0; i < 100; i++) { + val = epon_xif_reg_readl(mode, XIF_PORT_COMMAND_REG); + if ((val & XIF_PORT_COMMAND_DATAPORTBUSY_MASK)) + break; + udelay(5); + } + + if ((val & XIF_PORT_COMMAND_DATAPORTBUSY_MASK)) { + netdev_err(mode->port->priv->netdev, + "xif data port busy does not clear\n"); + return 1; + } + + return 0; +} + +/* + * + */ +static void xif_set_down_key(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int key_idx, + const uint8_t key[16], + const uint8_t sci[8]) +{ + u32 val; + + BUG_ON(key_idx > 1); + + /* make sure decryption is enabled */ + val = epon_xif_reg_readl(mode, XIF_CTL_REG); + val &= ~XIF_CTL_RXENCRYPTMODE_MASK; + val |= XIF_CTL_RXENCRYPTEN_MASK; + epon_xif_reg_writel(mode, XIF_CTL_REG, val); + + /* load the key */ + memcpy(&val, key + 0, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(3), val); + memcpy(&val, key + 4, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(2), val); + memcpy(&val, key + 8, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(1), val); + memcpy(&val, key + 12, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(0), val); + + memcpy(&val, sci, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(5), val); + memcpy(&val, sci + 4, 4); + val = cpu_to_be32(val); + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(4), val); + + /* enable decrypt for this key */ + val = 1; + epon_xif_reg_writel(mode, XIF_PORT_DATA_REG(7), val); + + val = (llid_idx << 1) | key_idx; + /* port 0 => rx key */ + xif_data_port_write(mode, 0, val); +} + +/* + * + */ +static void +xif_get_llid_last_rx_encrypt(struct xport_epon_priv *mode, + unsigned int llid_idx, + bool *last_encrypted, + unsigned int *last_encrypted_key_id) +{ + u32 val; + + val = epon_xif_reg_readl(mode, XIF_SECRX_ENCRYPT_REG); + *last_encrypted = (val & (1 << llid_idx)); + + val = epon_xif_reg_readl(mode, XIF_SECRX_KEYNUM_REG); + *last_encrypted_key_id = (val & (1 << llid_idx)) ? 1 : 0; +} + +/* + * + */ +static int xif_init(struct xport_epon_priv *mode) +{ + u32 val; + size_t i; + + /* release xif reset */ + epon_reset_modules(mode, false, RESET_XIFRST_N_MASK); + msleep(20); + + /* xif control, RAM init */ + val = XIF_CTL_XIFDTPORTRSTN_MASK; + epon_xif_reg_writel(mode, XIF_CTL_REG, val); + udelay(10); + + for (i = 0; i < 1000; i++) { + val = epon_xif_reg_readl(mode, XIF_CTL_REG); + if (!(val & XIF_CTL_XIFNOTRDY_MASK)) + break; + msleep(1); + } + + if ((val & XIF_CTL_XIFNOTRDY_MASK)) { + netdev_err(mode->port->priv->netdev, + "xif RAM init failed\n"); + return 1; + } + + val |= XIF_CTL_CFGPMCRXENCRC8CHK_MASK; + val |= XIF_CTL_PMCRXRSTN_MASK; + val |= XIF_CTL_SECRXRSTN_MASK; + epon_xif_reg_writel(mode, XIF_CTL_REG, val); + + /* oversize */ + val = epon_xif_reg_readl(mode, XIF_XPN_OVERSIZE_THRESH_REG); + val &= ~XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_MASK; + val |= 10000 << XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_SHIFT; + epon_xif_reg_writel(mode, XIF_XPN_OVERSIZE_THRESH_REG, val); + + /* interrupt status */ + val = XIF_INT_STATUS_SECRXRPLYPRTCTABRTINT_MASK | + XIF_INT_STATUS_SECTXPKTNUMMAXINT_MASK | + XIF_INT_STATUS_TSFULLUPDINT_MASK | + XIF_INT_STATUS_TXHANGINT_MASK | + XIF_INT_STATUS_NEGTIMEINT_MASK | + XIF_INT_STATUS_PMCTSJTTRINT_MASK | + XIF_INT_STATUS_SECRXOUTFFOVRFLWINT_MASK; + epon_xif_reg_writel(mode, XIF_INT_STATUS_REG, val); + + if (mode->down_speed == 10000) { + if (xpcs_rx_init(mode)) + return 1; + } + + if (mode->up_speed == 10000) { + /* FIXME: implement */ + BUG(); + } + + return 0; +} + +/* + * + */ +static void lif_set_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int llid, + bool enabled) +{ + u32 val; + u32 reg; + + switch (llid_idx) { + case 0 ... 7: + reg = LIF_LLIDx_0_7_REG(llid_idx); + break; + case 16 ... 23: + reg = LIF_LLIDx_16_23_REG(llid_idx); + break; + case 24 ... 31: + reg = LIF_LLIDx_24_31_REG(llid_idx); + break; + default: + BUG(); + break; + } + + val = epon_lif_reg_readl(mode, reg); + val &= ~LIF_LLIDx_0_7_CFGLLID0_MASK; + val |= llid << LIF_LLIDx_0_7_CFGLLID0_SHIFT; + if (enabled) + val |= (1 << (16 + LIF_LLIDx_0_7_CFGLLID0_SHIFT)); + else + val &= ~(1 << (16 + LIF_LLIDx_0_7_CFGLLID0_SHIFT)); + epon_lif_reg_writel(mode, reg, val); +} + +/* + * + */ +static void lif_set_laser_normal_op(struct xport_epon_priv *mode, + bool normal_op) +{ + u32 val; + + val = epon_lif_reg_readl(mode, LIF_PON_CONTROL_REG); + if (normal_op) + val |= LIF_PON_CONTROL_CFLASEREN_MASK; + else + val &= ~LIF_PON_CONTROL_CFLASEREN_MASK; + epon_lif_reg_writel(mode, LIF_PON_CONTROL_REG, val); +} + +/* + * + */ +static void lif_set_idle_time(struct xport_epon_priv *mode, + unsigned int front, + unsigned int back) +{ + u32 val; + + /* 'front' idle time before sending (for non FEC mode) */ + val = front << LIF_LASER_OFF_IDLE_CFTXINITIDLE_SHIFT; + /* turn off the laser 'back' tq before end of grant */ + val |= (1 << 7) | (back << LIF_LASER_OFF_IDLE_CFTXLASEROFFDELTA_SHIFT); + epon_lif_reg_writel(mode, LIF_LASER_OFF_IDLE_REG, val); + + /* 'front' idle time before sending (for FEC mode) */ + val = front << LIF_FEC_INIT_IDLE_CFTXFECINITIDLE_SHIFT; + epon_lif_reg_writel(mode, LIF_FEC_INIT_IDLE_REG, val); + + /* fixup MPCP offset so that it corresponds to first bytes of + * DA */ + val = front + BYTES_TO_TQ_1G(PREAMBLE_LEN_BYTES); + epon_lif_reg_writel(mode, LIF_SEC_UP_MPCP_OFFSET_REG, val); +} + +/* + * + */ +static int lif_init(struct xport_epon_priv *mode) +{ + u32 val; + + /* release lif reset */ + epon_reset_modules(mode, false, RESET_LIFRST_N_MASK); + msleep(20); + + /* pon control */ + val = LIF_PON_CONTROL_CFGRXDATABITFLIP_MASK | + LIF_PON_CONTROL_CFPPSCLKRBC_MASK; + if (mode->laser_active_hi) + val |= LIF_PON_CONTROL_CFTXLASERONACTHI_MASK; + epon_lif_reg_writel(mode, LIF_PON_CONTROL_REG, val); + + /* interop control */ + val = (2 << LIF_PON_INTER_OP_CONTROL_CFTXIPGCNT_SHIFT) | + (6 << LIF_PON_INTER_OP_CONTROL_CFTXPIPEDELAY_SHIFT); + epon_lif_reg_writel(mode, LIF_PON_INTER_OP_CONTROL_REG, val); + + /* fec control, globally enable FEC, still needs to be enabled + * per llid */ + val = LIF_FEC_CONTROL_CFFECTXENABLE_MASK | + LIF_FEC_CONTROL_CFFECTXFECPERLLID_MASK | + LIF_FEC_CONTROL_CFFECRXENABLE_MASK; + epon_lif_reg_writel(mode, LIF_FEC_CONTROL_REG, val); + + /* security control */ + val = epon_lif_reg_readl(mode, LIF_SEC_CONTROL_REG); + val |= LIF_SEC_CONTROL_SECDNRSTN_PRE_MASK; + val |= LIF_SEC_CONTROL_SECUPRSTN_PRE_MASK; + epon_lif_reg_writel(mode, LIF_SEC_CONTROL_REG, val); + + /* pon control, enable tx only */ + val = epon_lif_reg_readl(mode, LIF_PON_CONTROL_REG); + val |= LIF_PON_CONTROL_LIFTXRSTN_PRE_MASK; + val |= LIF_PON_CONTROL_LIFTXEN_MASK; + epon_lif_reg_writel(mode, LIF_PON_CONTROL_REG, val); + + /* clear all interrupts */ + val = LIF_INT_STATUS_INT_SOP_SFEC_IPG_VIOLATION_MASK | + LIF_INT_STATUS_LASERONMAX_MASK | + LIF_INT_STATUS_LASEROFF_MASK | + LIF_INT_STATUS_SECDNREPLAYPROTCTABORT_MASK | + LIF_INT_STATUS_SECUPPKTNUMOVERFLOW_MASK | + LIF_INT_STATUS_INTLASEROFFDURBURST_MASK | + LIF_INT_STATUS_INTRXBERTHRESHEXC_MASK | + LIF_INT_STATUS_INTFECRXFECRECVSTATUS_MASK | + LIF_INT_STATUS_INTFECRXCORERRFIFOFULLSTATUS_MASK | + LIF_INT_STATUS_INTFECRXCORERRFIFOUNEXPEMPTY_MASK | + LIF_INT_STATUS_INTFECBUFPOPEMPTYPUSH_MASK | + LIF_INT_STATUS_INTFECBUFPOPEMPTYNOPUSH_MASK | + LIF_INT_STATUS_INTFECBUFPUSHFULL_MASK | + LIF_INT_STATUS_INTUPTIMEFULLUPDSTAT_MASK | + LIF_INT_STATUS_INTFROUTOFALIGNSTAT_MASK | + LIF_INT_STATUS_INTGRNTSTARTTIMELAGSTAT_MASK | + LIF_INT_STATUS_INTABORTRXFRMSTAT_MASK | + LIF_INT_STATUS_INTNORXCLKSTAT_MASK | + LIF_INT_STATUS_INTRXMAXLENERRSTAT_MASK | + LIF_INT_STATUS_INTRXERRAFTALIGNSTAT_MASK | + LIF_INT_STATUS_INTRXSYNCHACQSTAT_MASK | + LIF_INT_STATUS_INTRXOUTOFSYNCHSTAT_MASK; + epon_lif_reg_writel(mode, LIF_INT_STATUS_REG, val); + + if (mode->down_speed == 1000) { + /* FIXME: implement */ + BUG(); + } + + return 0; +} + +/* + * + */ +static void epon_hw_set_idle_time(struct xport_epon_priv *mode, + unsigned int laser_on_time, + unsigned int sync_time, + unsigned int laser_off_time, + bool for_discovery) +{ + unsigned int front, back, total; + unsigned int timestamp_off; + u32 val; + + /* + * sanity check, don't go below what hardware can do + */ + if (laser_on_time < DEF_LASER_ON_TIME) + laser_on_time = DEF_LASER_ON_TIME; + if (laser_off_time < DEF_LASER_OFF_TIME) + laser_off_time = DEF_LASER_OFF_TIME; + + front = sync_time + laser_on_time; + back = laser_off_time; + total = front + back; + + switch (mode->up_speed) { + case 1000: + lif_set_idle_time(mode, front, back); + break; + case 10000: + /* FIXME: implement */ + BUG(); + break; + } + + timestamp_off = BYTES_TO_TQ_1G(PREAMBLE_LEN_BYTES) + front; + val = front << UP_TIME_STAMP_OFF_TIMESTAMPOFFSETFEC_SHIFT; + val |= front << UP_TIME_STAMP_OFF_TIMESTAMPOFFSET_SHIFT; + epon_epn_reg_writel(mode, EPN_UP_TIME_STAMP_OFF_REG, val); + + if (for_discovery) { + val = total << DISC_GRANT_OVR_HD_DISCGNTOVRHD_SHIFT; + epon_epn_reg_writel(mode, EPN_DISC_GRANT_OVR_HD_REG, val); + + /* note: bcm driver accounts FEC here */ + val = (total + get_register_req_data_duration(mode)) << + DN_DISCOVERY_SIZE_CFGDISCSIZE_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_DISCOVERY_SIZE_REG, val); + } else { + val = (total << GRANT_OVR_HD_GNTOVRHDFEC_SHIFT) | + (total << GRANT_OVR_HD_GNTOVRHD_SHIFT); + epon_epn_reg_writel(mode, EPN_GRANT_OVR_HD_REG, val); + } +} + +/* + * set laser on/off + sync time to use in normal operation + */ +static void epon_hw_set_normal_idle_time(struct xport_epon_priv *mode, + unsigned int laser_on_time, + unsigned int sync_time, + unsigned int laser_off_time) +{ + epon_hw_set_idle_time(mode, + laser_on_time, + sync_time, + laser_off_time, + false); +} + +/* + * set laser on/off + sync time to use during discovery + */ +static void epon_hw_set_disc_idle_time(struct xport_epon_priv *mode, + unsigned int laser_on_time, + unsigned int sync_time, + unsigned int laser_off_time) +{ + epon_hw_set_idle_time(mode, + laser_on_time, + sync_time, + laser_off_time, + true); +} + +/* + * + */ +static void epn_init_l2_sizes(struct xport_epon_priv *mode) +{ + /* FIXME: this depends on reporting type */ + const u32 l2_size = 824; + u32 start_addr; + size_t i; + + start_addr = 0; + for (i = 0; i < 8; i++) { + u32 end_addr, val; + + end_addr = start_addr + (l2_size >> 2); + val = (end_addr << TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUEEND0_SHIFT) | + (start_addr << TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUESTART0_SHIFT); + epon_epn_reg_writel(mode, + EPN_TX_L2S_QUE_CONFIGx_0_7_REG(i), + val); + start_addr = end_addr + 1; + } + + for (i = 8; i < 32; i++) { + u32 end_addr, val; + + end_addr = start_addr + (l2_size >> 2); + val = (end_addr << TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUEEND8_SHIFT) | + (start_addr << TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUESTART8_SHIFT); + epon_epn_reg_writel(mode, + EPN_TX_L2S_QUE_CONFIGx_8_31_REG(i), + val); + start_addr = end_addr + 1; + } +} + +/* + * + */ +static void epon_hw_set_laser_normal_op(struct xport_epon_priv *mode, + bool normal_op) +{ + if (mode->up_speed == 1000) + lif_set_laser_normal_op(mode, normal_op); + else { + /* FIXME: implement */ + BUG(); + } +} + +/* + * + */ +static bool epon_hw_get_los(struct xport_epon_priv *mode) +{ + bool los; + u32 val; + + switch (mode->down_speed) { + case 10000: + { + val = epon_xpcsrx_reg_readl(mode, XPCSRX_RX_INT_STAT_REG); + los = (val & RX_INT_STAT_INTRXFRAMERCWLOSS_MASK); + if (!los) + break; + + /* clear interrupt */ + epon_xpcsrx_reg_writel(mode, XPCSRX_RX_INT_STAT_REG, + RX_INT_STAT_INTRXFRAMERCWLOSS_MASK); + break; + } + default: + BUG(); + break; + } + return los; +} + +/* + * + */ +static void epon_hw_set_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + u16 llid, + bool enabled) +{ + if (mode->up_speed == 10000 || mode->down_speed == 10000) + xif_set_llid(mode, llid_idx, llid, enabled); + + if (mode->up_speed == 1000 || mode->down_speed == 1000) + lif_set_llid(mode, llid_idx, llid, enabled); +} + +/* + * + */ +static void epon_hw_pass_gates_frames(struct xport_epon_priv *mode, + unsigned int llid_idx, + bool pass) +{ + u32 val; + + val = epon_epn_reg_readl(mode, EPN_PASS_GATES_REG); + if (pass) + val |= (1 << llid_idx); + else + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_PASS_GATES_REG, val); +} + +/* + * + */ +static u32 epon_hw_get_local_mpcp_time(struct xport_epon_priv *mode) +{ + if (mode->down_speed == 10000) + return xif_get_local_mpcp_time(mode); + else { + /* implement for LIF */ + BUG(); + return 0; + } +} + +/* + * + */ +static void epon_hw_set_down_key(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int key_idx, + const uint8_t key[16], + const uint8_t sci[8]) +{ + if (mode->down_speed == 10000) + xif_set_down_key(mode, llid_idx, key_idx, key, sci); + else { + /* implement for LIF */ + BUG(); + } +} + +/* + * + */ +static void +epon_hw_get_llid_last_rx_encrypt(struct xport_epon_priv *mode, + unsigned int llid_idx, + bool *last_encrypted, + unsigned int *last_encrypted_key_id) +{ + if (mode->down_speed == 10000) + xif_get_llid_last_rx_encrypt(mode, llid_idx, + last_encrypted, + last_encrypted_key_id); + else { + /* implement for LIF */ + BUG(); + } +} + +/* + * + */ +static int epon_hw_data_port_read(struct xport_epon_priv *mode, + unsigned int port, + unsigned int ram_offset, + u32 *ret_value) +{ + u32 val; + size_t i; + + epon_epn_reg_writel(mode, EPN_DATA_PORT_ADDR_REG, ram_offset); + + val = (port << DATA_PORT_COMMAND_DPORTSELECT_SHIFT); + epon_epn_reg_writel(mode, EPN_DATA_PORT_COMMAND_REG, val); + + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_DATA_PORT_COMMAND_REG); + if ((val & DATA_PORT_COMMAND_DPORTBUSY_MASK)) + break; + udelay(5); + } + + if ((val & DATA_PORT_COMMAND_DPORTBUSY_MASK)) { + netdev_err(mode->port->priv->netdev, + "data port busy does not clear\n"); + *ret_value = 0xdeadbeef; + return 1; + } + + *ret_value = epon_epn_reg_readl(mode, EPN_DATA_PORT_DATA_0_REG); + return 0; +} + +/* + * + */ +static void epon_hw_link_remove_llid(struct xport_epon_priv *mode, + unsigned int llid_idx) +{ + epon_hw_set_llid(mode, llid_idx, 0, false); +} + +/* + * + */ +static void epon_hw_link_update_llid(struct xport_epon_priv *mode, + unsigned int llid_idx, + unsigned int new_llid) +{ + /* FIXME: should reset grant FIFOs and maybe do other stuff */ + epon_hw_set_llid(mode, llid_idx, new_llid, true); +} + +/* + * + */ +static void epon_hw_link_start_tx(struct xport_epon_priv *mode, + unsigned int llid_idx) +{ + u32 val; + size_t i; + + /* unreset L2 & L1 fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_L2_RPT_FIFO_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L2_RPT_FIFO_REG, val); + + val = epon_epn_reg_readl(mode, EPN_RESET_L1_ACCUMULATOR_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L1_ACCUMULATOR_REG, val); + + /* start upstream processing */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_UPSTREAM_REG, val); + + /* monitor feedback */ + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_FB_REG); + if (val & (1 << llid_idx)) + break; + udelay(5); + } + + if (!(val & (1 << llid_idx))) { + netdev_err(mode->port->priv->netdev, + "upstream feedback wont toggle for llid %u\n", + llid_idx); + } + + /* unreset grant fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_GNT_FIFO_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_GNT_FIFO_REG, val); + + /* start processing grants */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_GRANTS_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_GRANTS_REG, val); +} + +/* + * + */ +static bool epon_hw_l2_queue_is_empty(struct xport_epon_priv *mode, + unsigned int l2_idx) +{ + u32 val; + + /* check that L2 is empty */ + val = epon_epn_reg_readl(mode, EPN_TX_L2S_QUE_EMPTY_REG); + if (val & (1 << l2_idx)) + return true; + return false; +} + +/* + * + */ +static void epon_hw_link_stop_tx(struct xport_epon_priv *mode, + unsigned int llid_idx) +{ + u32 val; + size_t i, j; + + /* stop processing grants */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_GRANTS_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_GRANTS_REG, val); + + /* stop upstream processing */ + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_REG); + val &= ~(1 << llid_idx); + epon_epn_reg_writel(mode, EPN_ENABLE_UPSTREAM_REG, val); + + /* monitor feedback */ + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_FB_REG); + if (!(val & (1 << llid_idx))) + break; + udelay(5); + } + + if ((val & (1 << llid_idx))) { + netdev_err(mode->port->priv->netdev, + "upstream feedback wont clear for llid %u\n", + llid_idx); + } + + for (i = 0; i < 100; i++) { + /* flush l2 FIFO until its empty */ + val = llid_idx << L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_SHIFT; + epon_epn_reg_writel(mode, + EPN_L2S_FLUSH_CONFIG_REG, + val); + val |= L2S_FLUSH_CONFIG_CFGFLUSHL2SEN_MASK; + epon_epn_reg_writel(mode, + EPN_L2S_FLUSH_CONFIG_REG, + val); + + for (j = 0; j < 100; j++) { + val = epon_epn_reg_readl(mode, + EPN_L2S_FLUSH_CONFIG_REG); + if (val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK) + break; + udelay(5); + } + + if (!(val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK)) { + netdev_err(mode->port->priv->netdev, + "L2 flush not done %u\n", llid_idx); + break; + } + + val = llid_idx << L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_SHIFT; + epon_epn_reg_writel(mode, + EPN_L2S_FLUSH_CONFIG_REG, + val); + for (j = 0; j < 100; j++) { + val = epon_epn_reg_readl(mode, + EPN_L2S_FLUSH_CONFIG_REG); + if (!(val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK)) + break; + udelay(5); + } + + if ((val & L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK)) { + netdev_err(mode->port->priv->netdev, + "L2 flush does not stop %u\n", llid_idx); + break; + } + + udelay(100); + + if (epon_hw_l2_queue_is_empty(mode, llid_idx) && + bcm_runner_fw_bbh_is_empty(mode->port->priv)) + break; + } + + if (!epon_hw_l2_queue_is_empty(mode, llid_idx)) + netdev_err(mode->port->priv->netdev, + "L2 queue %u not empty after reset\n", llid_idx); + + if (!bcm_runner_fw_bbh_is_empty(mode->port->priv)) + netdev_err(mode->port->priv->netdev, + "BBH queue %u not empty after reset\n", llid_idx); + + /* reset L2 & L1 fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_L1_ACCUMULATOR_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L1_ACCUMULATOR_REG, val); + + val = epon_epn_reg_readl(mode, EPN_RESET_L2_RPT_FIFO_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_L2_RPT_FIFO_REG, val); + + /* reset grant fifo */ + val = epon_epn_reg_readl(mode, EPN_RESET_GNT_FIFO_REG); + val |= (1 << llid_idx); + epon_epn_reg_writel(mode, EPN_RESET_GNT_FIFO_REG, val); + +} + +/* + * + */ +static void epon_hw_set_burst_cap(struct xport_epon_priv *mode, + unsigned int burst_cap) +{ + u32 val; + + /* update max grant size */ + val = epon_epn_reg_readl(mode, EPN_MAX_GNT_SIZE_REG); + val &= ~MAX_GNT_SIZE_MAXGNTSIZE_MASK; + val |= burst_cap << MAX_GNT_SIZE_MAXGNTSIZE_SHIFT; + epon_epn_reg_writel(mode, EPN_MAX_GNT_SIZE_REG, val); + + if (mode->up_speed == 1000) + epon_epn_reg_writel(mode, EPN_BURST_CAPx_0_7_REG(0), + burst_cap); + else { + /* FIXME: implement */ + BUG(); + } +} + +/* + * + */ +static void epon_hw_init(struct xport_epon_priv *mode) +{ + size_t i; + u32 val; + + /* sanity check */ + val = epon_top_reg_readl(mode, EPON_TOP_SCRATCH_REG); + if (val != 0x1baddad) { + netdev_err(mode->port->priv->netdev, + "epon module not functional\n"); + return; + } + + /* put all ePON blocks in reset */ + epon_reset_modules(mode, true, + RESET_EPNRST_N_MASK | + RESET_LIFRST_N_MASK | + RESET_NCORST_N_MASK | + RESET_CLKPRGRST_N_MASK | + RESET_TODRST_N_MASK | + RESET_XIFRST_N_MASK | + RESET_XPCSTXRST_N_MASK | + RESET_XPCSRXRST_N_MASK); + msleep(20); + + /* clear all epon top interrupts */ + val = INTERRUPT_INT_1PPS_MASK | + INTERRUPT_INT_XPCS_TX_MASK | + INTERRUPT_INT_XPCS_RX_MASK | + INTERRUPT_INT_XIF_MASK | + INTERRUPT_INT_NCO_MASK | + INTERRUPT_INT_LIF_MASK | + INTERRUPT_INT_EPN_MASK; + epon_top_reg_writel(mode, EPON_TOP_INTERRUPT_REG, val); + + /* + * set epon top rate + */ + val = 0; + switch (mode->down_speed) { + case 1000: + break; + case 10000: + val |= CONTROL_CFGTENGIGDNS_MASK; + break; + default: + BUG(); + break; + } + + switch (mode->up_speed) { + case 1000: + break; + case 10000: + val |= CONTROL_CFGTENGIGPONUP_MASK; + break; + default: + BUG(); + break; + } + epon_top_reg_writel(mode, EPON_TOP_CONTROL_REG, val); + + /* release epn reset */ + epon_reset_modules(mode, false, RESET_EPNRST_N_MASK); + msleep(20); + + /* epn control 0 */ + val = CONTROL_0_PRVDROPUNMAPPPEDLLID_MASK | + CONTROL_0_CFGREPLACEUPFCS_MASK | + CONTROL_0_CFGAPPENDUPFCS_MASK | + CONTROL_0_DRXRST_PRE_N_MASK | + CONTROL_0_DRXEN_MASK | + CONTROL_0_UTXRST_PRE_N_MASK | + CONTROL_0_UTXEN_MASK; + val &= ~CONTROL_0_RPTSELECT_MASK; + val |= (1 << CONTROL_0_RPTSELECT_SHIFT); + epon_epn_reg_writel(mode, EPN_CONTROL_0_REG, val); + + /* max grant size */ + val = epon_epn_reg_readl(mode, EPN_MAX_GNT_SIZE_REG); + val &= ~MAX_GNT_SIZE_MAXGNTSIZE_MASK; + val |= 20000 << MAX_GNT_SIZE_MAXGNTSIZE_SHIFT; + epon_epn_reg_writel(mode, EPN_MAX_GNT_SIZE_REG, val); + + /* time stamp diff */ + val = epon_epn_reg_readl(mode, EPN_TIME_STAMP_DIFF_REG); + val &= ~TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_MASK; + val |= 0x40UL << TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_SHIFT; + epon_epn_reg_writel(mode, EPN_TIME_STAMP_DIFF_REG, val); + + /* main int status */ + epon_epn_reg_writel(mode, EPN_MAIN_INT_STATUS_REG, 0xffffffff); + + /* grant time start delta */ + val = epon_epn_reg_readl(mode, EPN_GNT_TIME_START_DELTA_REG); + val &= ~GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_MASK; + val |= 0x3e8UL << GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_SHIFT; + epon_epn_reg_writel(mode, EPN_GNT_TIME_START_DELTA_REG, val); + + /* grand start time margin */ + val = epon_epn_reg_readl(mode, EPN_DN_RD_GNT_MARGIN_REG); + val &= ~DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_MASK; + val |= 0x3ffUL << DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_RD_GNT_MARGIN_REG, val); + + /* misalign threshold */ + val = epon_epn_reg_readl(mode, EPN_DN_GNT_MISALIGN_THR_REG); + val &= ~DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_MASK; + val |= 0 << DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_SHIFT; + val &= ~DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_MASK; + val |= 2 << DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_GNT_MISALIGN_THR_REG, val); + + /* misalign pause */ + val = epon_epn_reg_readl(mode, EPN_DN_GNT_MISALIGN_PAUSE_REG); + val &= ~DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_MASK; + val |= 300 << DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_GNT_MISALIGN_PAUSE_REG, val); + + /* grant interval */ + val = epon_epn_reg_readl(mode, EPN_GNT_INTERVAL_REG); + val &= ~GNT_INTERVAL_GNTINTERVAL_MASK; + /* 1 second in 262us units */ + val |= (1000000 / 262) << GNT_INTERVAL_GNTINTERVAL_SHIFT; + epon_epn_reg_writel(mode, EPN_GNT_INTERVAL_REG, val); + + /* report byte length */ + val = epon_epn_reg_readl(mode, EPN_REPORT_BYTE_LENGTH_REG); + val &= ~REPORT_BYTE_LENGTH_PRVRPTBYTELEN_MASK; + val |= 84 << REPORT_BYTE_LENGTH_PRVRPTBYTELEN_SHIFT; + epon_epn_reg_writel(mode, EPN_REPORT_BYTE_LENGTH_REG, val); + + /* minimum grant setup set */ + val = epon_epn_reg_readl(mode, EPN_MINIMUM_GRANT_SETUP_REG); + val &= ~MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_MASK; + val |= 0x64UL << MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_SHIFT; + epon_epn_reg_writel(mode, EPN_MINIMUM_GRANT_SETUP_REG, val); + + /* spare register */ + val = SPARE_CTL_ECOJIRA758ENABLE_MASK; + epon_epn_reg_writel(mode, EPN_SPARE_CTL_REG, val); + + /* put all l1/l2 queue in reset*/ + epon_epn_reg_writel(mode, EPN_RESET_L1_ACCUMULATOR_REG, 0xffffffffUL); + epon_epn_reg_writel(mode, EPN_RESET_L2_RPT_FIFO_REG, 0xffffffffUL); + + /* disable grant processing on all LLIDs */ + epon_epn_reg_writel(mode, EPN_ENABLE_GRANTS_REG, 0); + + /* keep grant fifo in reset */ + epon_epn_reg_writel(mode, EPN_RESET_GNT_FIFO_REG, 0xffffffffUL); + + /* stop upstream processing */ + epon_epn_reg_writel(mode, EPN_ENABLE_UPSTREAM_REG, 0); + + /* monitor feedback */ + for (i = 0; i < 100; i++) { + val = epon_epn_reg_readl(mode, EPN_ENABLE_UPSTREAM_FB_REG); + if (val == 0) + break; + udelay(5); + } + + if (val) + netdev_err(mode->port->priv->netdev, + "failed to disable upstream on all llid\n"); + + /* epn control 1 */ + val = CONTROL_1_CFGSTALEGNTCHK_MASK | + CONTROL_1_DISABLEDISCSCALE_MASK | + CONTROL_1_CLRONRD_MASK | + 0; + epon_epn_reg_writel(mode, EPN_CONTROL_1_REG, val); + + /* setup discovery filter so we only accept discovery gates + * for the correct upstream speed */ + if (mode->down_speed == 10000) { + u16 mask, value; + + /* default to not care */ + mask = 0xffff; + value = get_disc_info_caps(mode, &mask); + + val = (mask << DISCOVERY_FILTER_PRVDISCINFOMASK_SHIFT) | + (value << DISCOVERY_FILTER_PRVDISCINFOVALUE_SHIFT); + epon_epn_reg_writel(mode, EPN_DISCOVERY_FILTER_REG, val); + } + + /* setup DA mac address for report frames, use standard mpcp + * multicast */ + epon_epn_reg_writel(mode, EPN_OLT_MAC_ADDR_HI_REG, + extract_mac_addr_hi(mpcp_frame_da)); + epon_epn_reg_writel(mode, EPN_OLT_MAC_ADDR_LO_REG, + extract_mac_addr_lo(mpcp_frame_da)); + + /* setup our mac address on every LLID, this should be if we + * do multiple TX LLID because they have to be different */ + for (i = 0; i < 8; i++) { + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_0_7_LO_REG(i), + extract_mac_addr_lo(mode->mac_addr)); + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_0_7_HI_REG(i), + extract_mac_addr_hi(mode->mac_addr)); + } + for (i = 8; i < 32; i++) { + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_8_31_LO_REG(i), + extract_mac_addr_lo(mode->mac_addr)); + epon_epn_reg_writel(mode, + EPN_ONU_MAC_ADDRx_8_31_LO_REG(i), + extract_mac_addr_hi(mode->mac_addr)); + } + + if (mode->up_speed == 1000 || mode->down_speed == 1000) { + if (lif_init(mode)) + return; + } + + if (mode->down_speed == 10000 || mode->up_speed == 10000) { + if (xif_init(mode)) + return; + } + + epon_hw_set_laser_normal_op(mode, true); + + /* set default reporting mode using only one queue (set before + * in control_0), clear all multi-prio bits */ + val = epon_epn_reg_readl(mode, EPN_MULTI_PRI_CFG_0_REG); + val &= ~MULTI_PRI_CFG_0_CFGRPTMULTIPRI0_MASK; + val &= ~MULTI_PRI_CFG_0_CFGRPTSWAPQS0_MASK; + val &= ~MULTI_PRI_CFG_0_CFGRPTGNTSOUTST0_MASK; + val &= ~MULTI_PRI_CFG_0_CFGSHAREDL2_MASK; + val &= ~MULTI_PRI_CFG_0_CFGSHAREDBURSTCAP_MASK; + epon_epn_reg_writel(mode, EPN_MULTI_PRI_CFG_0_REG, val); + + /* setup timer to trigger an interrupt if we don't get grants + * on a llid, (unit is 262 us) */ + epon_epn_reg_writel(mode, + EPN_GNT_INTERVAL_REG, + (10 * 1000 * 1000) / 262); + + /* setup L2 sizes */ + epn_init_l2_sizes(mode); + + for (i = 0; i < 8; i++) { + /* same as typo in bcm code */ + bcm_xrdp_api_pon_flow_id_set(mode->port->priv->xrdp, + i, 1); + } + + epon_hw_set_burst_cap(mode, DEFAULT_BURST_CAP); +} + +/* + * + */ +static void mode_epon_mib_update(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + size_t i; + + for (i = 0; i < ARRAY_SIZE(epon_mib_estat); i++) { + const struct bcm_runner_ethtool_stat *s; + u64 val; + bool incr; + char *p; + + s = &epon_mib_estat[i]; + val = 0; + incr = false; + switch (s->type) { + case EPON_STAT_XPCS_RX: + val = epon_xpcsrx_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_XPCS_RX64: + val = epon_xpcsrx_reg_readl(mode, s->reg); + val |= (u64)epon_xpcsrx_reg_readl(mode, + s->reg + 0x4) << 32; + incr = true; + break; + case EPON_STAT_XIF: + val = epon_xif_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_LIF: + val = epon_lif_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_EPN: + val = epon_epn_reg_readl(mode, s->reg); + incr = true; + break; + case EPON_STAT_EPN_L1_ACC: + { + u32 val32; + unsigned int l1 = s->reg; + + val32 = (l1 << L1_ACCUMULATOR_SEL_CFGL1SUVASIZESEL_SHIFT) | + (l1 << L1_ACCUMULATOR_SEL_CFGL1SSVASIZESEL_SHIFT); + epon_epn_reg_writel(mode, EPN_L1_ACCUMULATOR_SEL_REG, + val32); + val = epon_epn_reg_readl(mode, EPN_L1_SVA_BYTES_REG); + incr = false; + break; + } + case EPON_STAT_EPN_RAM: + { + unsigned int llid, port, stat, ram_offset; + u32 val32; + + llid = (s->reg >> 24) & 0xff; + port = (s->reg >> 16) & 0xff; + stat = (s->reg) & 0xffff; + + ram_offset = 0; + switch (port) { + case 0: + ram_offset = (llid * 21) + stat; + break; + case 1: + ram_offset = (llid * 17) + stat; + break; + } + + epon_hw_data_port_read(mode, port, ram_offset, &val32); + val = val32; + incr = true; + break; + } + case EPON_STAT_LOCAL: + continue; + } + + p = (char *)&mode->mib + s->offset; + if (incr) + *(u64 *)p += val; + else + *(u64 *)p = val; + } +} + +/* + * + */ +static void *mode_epon_mib_get_data(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + return &mode->mib; +} + +/* + * + */ +static void mode_epon_mtu_set(void *mode_priv, unsigned int size) +{ + struct xport_epon_priv *mode = mode_priv; + epon_epn_reg_writel(mode, EPN_MAX_FRAME_SIZE_REG, size); +} + +/* + * + */ +static void __epon_link_start(struct xport_epon_priv *mode, + struct epon_link *link, + bool start_tx) +{ + if (!link->rx_enabled) { + epon_hw_link_update_llid(mode, link->idx, link->llid); + link->rx_enabled = true; + } + + if (start_tx) { + epon_hw_link_start_tx(mode, link->idx); + link->tx_enabled = true; + } +} + +/* + * + */ +static void epon_link_update_llid(struct xport_epon_priv *mode, + struct epon_link *link, + unsigned int llid) +{ + link->llid = llid; + epon_hw_link_update_llid(mode, link->idx, link->llid); +} + +/* + * + */ +static void epon_link_start_rx_only(struct xport_epon_priv *mode, + struct epon_link *link, + unsigned int llid) +{ + link->llid = llid; + __epon_link_start(mode, link, false); +} + +/* + * + */ +static void epon_link_start_bidir(struct xport_epon_priv *mode, + struct epon_link *link, + unsigned int llid) +{ + link->llid = llid; + __epon_link_start(mode, link, true); +} + +/* + * + */ +static void epon_link_pass_gates_frame(struct xport_epon_priv *mode, + struct epon_link *link, + bool pass) +{ + epon_hw_pass_gates_frames(mode, link->idx, pass); +} + + +/* + * + */ +static void epon_link_stop(struct xport_epon_priv *mode, + struct epon_link *link) +{ + if (link->tx_enabled) { + epon_hw_link_stop_tx(mode, link->idx); + link->tx_enabled = false; + } + + if (link->rx_enabled) { + epon_hw_link_remove_llid(mode, link->idx); + link->rx_enabled = false; + } + + epon_link_pass_gates_frame(mode, link, false); +} + +/* + * + */ +static struct epon_link *epon_link_find(struct xport_epon_priv *mode, + unsigned int llid) +{ + struct epon_link *link, *ret_link; + + ret_link = NULL; + mutex_lock(&mode->links_lock); + list_for_each_entry(link, &mode->links_list, next) { + if (link->llid == llid) { + ret_link = link; + break; + } + } + mutex_unlock(&mode->links_lock); + return ret_link; +} + +/* + * + */ +static struct epon_link *epon_link_alloc(struct xport_epon_priv *mode, + int force_idx) +{ + struct epon_link *link = NULL; + unsigned int idx; + + mutex_lock(&mode->links_lock); + + if (!mode->links_free) + goto end; + + /* choose llid idx */ + if (force_idx != -1) { + if (!(mode->links_free & (1ULL << force_idx))) { + WARN(1, "forced llid %d is not free\n", force_idx); + goto end; + } + idx = force_idx; + } else + idx = ffs(mode->links_free) - 1; + + link = kzalloc(sizeof (*link), GFP_KERNEL); + link->idx = idx; + mode->links_free &= ~(1ULL << idx); + list_add_tail(&link->next, &mode->links_list); + +end: + mutex_unlock(&mode->links_lock); + return link; +} + +/* + * + */ +static void __epon_link_release(struct xport_epon_priv *mode, + struct epon_link *link) +{ + WARN_ON(link->tx_enabled || link->rx_enabled); + list_del(&link->next); + mode->links_free |= (1ULL << link->idx); + kfree(link); +} + +/* + * + */ +static void epon_link_release(struct xport_epon_priv *mode, + struct epon_link *link) +{ + mutex_lock(&mode->links_lock); + __epon_link_release(mode, link); + mutex_unlock(&mode->links_lock); +} + +/* + * + */ +static void epon_schedule_reset_backoff(struct xport_epon_priv *mode) +{ + netdev_info(mode->port->priv->netdev, + "scheduling reset in %u ms\n", + mode->epon_reset_duration_ms); + bcm_enet_runner_schedule_reset(mode->port->priv, + mode->epon_reset_duration_ms); + mode->epon_reset_duration_ms *= 2; + if (mode->epon_reset_duration_ms > 5000) + mode->epon_reset_duration_ms = 5000; +} + +/* + * + */ +static int mpcp_rcv_handler(struct sk_buff *skb, + struct net_device *dev, + struct packet_type *pt, + struct net_device *orig_dev) +{ + struct xport_epon_priv *mode = pt->af_packet_priv; + struct mpcp_hdr *hdr; + struct sk_buff *nskb = NULL; + + /* + * do nothing if until global link status is correct + * + * not necessary per-se, but this avoids processing frames + * when the link just came up, or when it's down and we are + * waiting for manager to reset + */ + if (mode->glob_link_state != EPON_GLINK_UP) + goto drop; + + if (!pskb_may_pull(skb, sizeof (struct mpcp_hdr))) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + + hdr = (struct mpcp_hdr *)skb->data; + switch (be16_to_cpu(hdr->opcode)) { + case MPCP_OPCODE_GATE: + case MPCP_OPCODE_REGISTER: + case MPCP_OPCODE_REGISTER_ACK: + mode->mib.reg_mpcp_rx++; + break; + default: + mode->mib.reg_mpcp_rx_unk_opcode++; + goto drop; + } + + switch (mode->reg_state) { + case EPON_REG_WAIT_DISCOVERY: + { + struct mpcp_disc_gate *disc; + struct mpcp_disc_gate10g *disc_10g; + struct mpcp_hdr *rhdr; + struct mpcp_register_req *reg_req; + size_t disc_size, reg_req_size, to_pad; + u32 now, disc_start, disc_remain, disc_end, reg_req_duration; + u32 sync_time, rnd_value, window_len; + u32 slot, slot_count, slot_skip; + u32 val; + + if (be16_to_cpu(hdr->opcode) != MPCP_OPCODE_GATE) + goto drop; + + if (mode->down_speed == 10000) + disc_size = sizeof (*disc_10g); + else + disc_size = sizeof (*disc); + + if (!pskb_may_pull(skb, sizeof (*hdr) + disc_size)) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + disc = (struct mpcp_disc_gate *)(hdr + 1); + if (!(disc->nb_grants_flags & MPCP_GATE_F_IS_DISC)) + goto drop; + + if (mode->down_speed == 1000) { + sync_time = be16_to_cpu(disc->sync_time); + } else { + u16 caps = get_disc_info_caps(mode, NULL); + + disc_10g = (struct mpcp_disc_gate10g *)(disc); + if ((be16_to_cpu(disc_10g->disc_info) & caps) != caps) { + mode->mib.reg_mpcp_rx_disc_info_mismatch++; + goto drop; + } + + sync_time = be16_to_cpu(disc_10g->sync_time); + } + + mode->mib.reg_mpcp_rx_disc++; + + /* if first frame, then just capture capture synctime */ + if (!mode->reg_cfg.valid_sync_time || + mode->reg_cfg.sync_time != sync_time) { + mode->reg_cfg.valid_sync_time = true; + mode->reg_cfg.sync_time = sync_time; + epon_hw_set_disc_idle_time(mode, + DEF_LASER_ON_TIME, + mode->reg_cfg.sync_time, + DEF_LASER_OFF_TIME); + goto drop; + } + + rnd_value = get_random_int(); + + /* + * allocate reply skb now, do all costly operation + * before calculating the remaining time + */ + reg_req_size = get_register_req_data_size(false); + nskb = dev_alloc_skb(reg_req_size); + if (!nskb) { + mode->mib.reg_mpcp_rx_other_err++; + goto drop; + } + + skb_reset_network_header(nskb); + rhdr = skb_put(nskb, sizeof (*rhdr) + sizeof (*reg_req)); + rhdr->opcode = cpu_to_be16(MPCP_OPCODE_REGISTER_REQ); + /* timestamp will be updated by hardware */ + rhdr->timestamp = cpu_to_be32(0xdeadbeef); + reg_req = (struct mpcp_register_req *)(rhdr + 1); + reg_req->flags = MPCP_REGREQ_F_REGISTER; + reg_req->pending_grants = BCM_MAX_PENDING_GRANTS; + reg_req->disc_info = cpu_to_be16(get_disc_info_caps(mode, + NULL)); + reg_req->laser_on = DEF_LASER_ON_TIME; + reg_req->laser_off = DEF_LASER_OFF_TIME; + /* pad remaining bytes with zero */ + to_pad = reg_req_size - ETH_HLEN - nskb->len; + memset(skb_put(nskb, to_pad), 0, to_pad); + + nskb->dev = mode->port->priv->netdev; + nskb->protocol = htons(ETH_P_PAUSE); + dev_hard_header(nskb, nskb->dev, ETH_P_PAUSE, + mpcp_frame_da, NULL, 0); + + /* + * reply packet is ready, check time left we have to + * reply + */ + now = epon_hw_get_local_mpcp_time(mode); + window_len = be16_to_cpu(disc->length); + disc_start = be32_to_cpu(disc->start_time); + disc_end = disc_start + window_len; + if (now >= disc_end) { + /* really late */ + mode->mib.reg_mpcp_rx_disc_late++; + goto drop; + } + + /* make sure we have time to send the frame before end + * of discovery */ + disc_remain = disc_end - now; + reg_req_duration = get_register_req_data_duration(mode) + + DEF_LASER_ON_TIME + + DEF_LASER_OFF_TIME + + mode->reg_cfg.sync_time; + + /* if remaining time is too small (time for us to + * schedule tx), dont even try */ + if (disc_remain < reg_req_duration || + reg_req_duration - disc_remain < SOFTWARE_TX_LATENCY_TQ) { + mode->mib.reg_mpcp_rx_disc_late++; + goto drop; + } + + /* + * Take a random offset inside transmit inside window. + * + * Since everyone else has the same reg_req_duration + * value, divide window into equal slots so we reduce + * chance of colliding (of course, only works if + * everyone does the same...) + */ + slot_count = window_len / reg_req_duration; + slot_skip = 0; + + /* don't use slots that are already late */ + if (now + SOFTWARE_TX_LATENCY_TQ > disc_start) + slot_skip = DIV_ROUND_UP(now + SOFTWARE_TX_LATENCY_TQ - + disc_start, + reg_req_duration); + + slot = slot_skip + (rnd_value % (slot_count - slot_skip)); + mode->mib.reg_mpcp_rx_disc_last_slot = slot; + + /* program hardware to skip this number of tq before + * sending register_req */ + val = (slot * reg_req_duration) << + DN_DISCOVERY_SEED_CFGDISCSEED_SHIFT; + epon_epn_reg_writel(mode, EPN_DN_DISCOVERY_SEED_REG, val); + + /* finally send packet */ + dev_queue_xmit(nskb); + nskb = NULL; + mode->mib.reg_mpcp_tx_reg_req++; + +#if 0 + printk("DISC_WINDOW: [%u - %u], slot: count:%u " + "skip:%d chosen:%d\n", + be32_to_cpu(disc->start_time) - now, + disc_remain, + slot_count, + slot_skip, + slot); +#endif + mode->reg_state = EPON_REG_WAIT_REGISTER; + mode->reg_state_last_change = jiffies; + break; + } + + case EPON_REG_WAIT_REGISTER: + { + struct mpcp_register *reg; + struct mpcp_register10g *reg_10g; + struct mpcp_register_ack *reg_ack; + struct mpcp_hdr *rhdr; + size_t reg_size, reg_ack_size, to_pad; + + if (be16_to_cpu(hdr->opcode) != MPCP_OPCODE_REGISTER) + goto drop; + + if (mode->down_speed == 10000) + reg_size = sizeof (*reg_10g); + else + reg_size = sizeof (*reg); + + if (!pskb_may_pull(skb, sizeof (*hdr) + reg_size)) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + /* the frame is sent to us on the broadcast LLID, we + * have to make sure it's addressed to us only */ + if (skb->pkt_type != PACKET_HOST) { + mode->mib.reg_mpcp_rx_reg_for_other++; + goto drop; + } + + reg = (struct mpcp_register *)(hdr + 1); + switch (reg->flags) { + case MPCP_REG_F_REREGISTER: + case MPCP_REG_F_DEREGISTER: + /* go back to previous state */ + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + mode->reg_state_last_change = jiffies; + mode->mib.reg_mpcp_rx_reg_dereg++; + goto drop; + + case MPCP_REG_F_NACK: + /* go back to previous state, might backoff + * here */ + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + mode->reg_state_last_change = jiffies; + mode->mib.reg_mpcp_rx_reg_nack++; + goto drop; + + case MPCP_REG_F_ACK: + /* fallthrough */ + break; + + default: + mode->mib.reg_mpcp_rx_reg_unk_flag++; + goto drop; + } + + /* registration success, update LLID with assigned one */ + mode->reg_cfg.assigned_llid = be16_to_cpu(reg->assigned_port); + + /* filter gates from now */ + epon_link_pass_gates_frame(mode, mode->user_link, false); + + /* now filter the new llid */ + epon_link_update_llid(mode, + mode->user_link, + mode->reg_cfg.assigned_llid); + + /* capture and apply the OLT parameters */ + mode->reg_cfg.sync_time = be16_to_cpu(reg->sync_time); + if (mode->down_speed == 10000) { + reg_10g = (struct mpcp_register10g *)(reg); + mode->reg_cfg.laser_on_time = reg_10g->target_laser_on; + mode->reg_cfg.laser_off_time = reg_10g->target_laser_off; + } else { + mode->reg_cfg.laser_on_time = DEF_LASER_ON_TIME; + mode->reg_cfg.laser_off_time = DEF_LASER_OFF_TIME; + } + + epon_hw_set_normal_idle_time(mode, + mode->reg_cfg.laser_on_time, + mode->reg_cfg.sync_time, + mode->reg_cfg.laser_off_time); + + + /* send registration ACK */ + reg_ack_size = max_t(size_t, + ETH_HLEN + + sizeof (struct mpcp_hdr) + + sizeof (struct mpcp_register_ack), + ETH_ZLEN); + nskb = dev_alloc_skb(reg_ack_size); + if (!nskb) { + mode->mib.reg_mpcp_rx_other_err++; + goto drop; + } + + skb_reset_network_header(nskb); + rhdr = skb_put(nskb, sizeof (*rhdr) + sizeof (*reg_ack)); + rhdr->opcode = cpu_to_be16(MPCP_OPCODE_REGISTER_ACK); + /* timestamp will be updated by hardware */ + rhdr->timestamp = cpu_to_be32(0xdeadbeef); + reg_ack = (struct mpcp_register_ack *)(rhdr + 1); + reg_ack->flags = MPCP_REGACK_F_ACK; + reg_ack->echoed_assigned_port = + cpu_to_be16(mode->reg_cfg.assigned_llid); + reg_ack->echoed_sync_time = + cpu_to_be16(mode->reg_cfg.sync_time); + /* pad remaining bytes with zero */ + to_pad = reg_ack_size - ETH_HLEN - nskb->len; + memset(skb_put(nskb, to_pad), 0, to_pad); + + nskb->dev = mode->port->priv->netdev; + nskb->protocol = htons(ETH_P_PAUSE); + dev_hard_header(nskb, nskb->dev, ETH_P_PAUSE, + mpcp_frame_da, NULL, 0); + + dev_queue_xmit(nskb); + nskb = NULL; + mode->mib.reg_mpcp_tx_reg_ack++; + + /* clear some IRQs that link monitoring will be + * checking from now */ + epon_epn_reg_writel(mode, + EPN_MAIN_INT_STATUS_REG, + MAIN_INT_STATUS_INTDNOUTOFORDER_MASK | + MAIN_INT_STATUS_INTDNTIMENOTINSYNC_MASK); + epon_epn_reg_writel(mode, + EPN_GNT_INTV_INT_STATUS_REG, + ~0); + + netdev_info(mode->port->priv->netdev, + "MPCP registration complete, llid 0x%04x\n", + mode->reg_cfg.assigned_llid); + mode->reg_state = EPON_REG_COMPLETE; + mode->reg_state_last_change = jiffies; + break; + } + + case EPON_REG_COMPLETE: + { + struct mpcp_register *reg; + struct mpcp_register10g *reg_10g; + size_t reg_size; + + if (be16_to_cpu(hdr->opcode) != MPCP_OPCODE_REGISTER) + goto drop; + + if (mode->down_speed == 10000) + reg_size = sizeof (*reg_10g); + else + reg_size = sizeof (*reg); + + if (!pskb_may_pull(skb, sizeof (*hdr) + reg_size)) { + mode->mib.reg_mpcp_rx_invalid++; + goto drop; + } + + if (skb->pkt_type != PACKET_HOST) { + mode->mib.reg_mpcp_rx_reg_for_other++; + goto drop; + } + + reg = (struct mpcp_register *)(hdr + 1); + switch (reg->flags) { + case MPCP_REG_F_REREGISTER: + case MPCP_REG_F_DEREGISTER: + netdev_info(mode->port->priv->netdev, + "received MPCP deregister\n"); + mode->reg_state = EPON_REG_FAILED; + mode->reg_state_last_change = jiffies; + phylink_mac_change(mode->port->priv->phylink, false); + epon_schedule_reset_backoff(mode); + goto drop; + + default: + goto drop; + } + } + + case EPON_REG_FAILED: + goto drop; + } + + +drop: + if (nskb) + kfree_skb(nskb); + kfree_skb(skb); + return NET_RX_DROP; +} + +/* + * + */ +static void glob_link_work_resched(struct xport_epon_priv *mode) +{ + queue_delayed_work(mode->epon_wq, + &mode->glob_link_work, HZ / 5); +} + +/* + * + */ +static struct { + u32 mask; + const char *name; + bool fatal; + bool ignore_when_not_reg; +} epn_irqs[] = { + { + MAIN_INT_STATUS_INTBBHUPFRABORT_MASK, + "BBHUPFRABORT", + false, + }, + { + MAIN_INT_STATUS_INTCOL2SBURSTCAPOVERFLOWPRES_MASK, + "COL2SBURSTCAPOVERFLOWPRES", + false, + }, + { + MAIN_INT_STATUS_INTCOEMPTYRPT_MASK, + "COEMPTYRPT", + false, + }, + { + MAIN_INT_STATUS_INTCODRXERRABORTPRES_MASK, + "CODRXERRABORTPRES", + false, + }, + { + MAIN_INT_STATUS_INTL2SFIFOOVERRUN_MASK, + "L2SFIFOOVERRUN", + true, + }, + { + MAIN_INT_STATUS_INTCO1588TSINT_MASK, + "CO1588TSINT", + false, + }, + { + MAIN_INT_STATUS_INTCODELSTALEGNT_MASK, + "CODELSTALEGNT", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTNONPOLL_MASK, + "COGNTNONPOLL", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTMISALIGN_MASK, + "COGNTMISALIGN", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTTOOFAR_MASK, + "COGNTTOOFAR", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTINTERVAL_MASK, + "COGNTINTERVAL", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTMISSABORT_MASK, + "COGNTMISSABORT", + false, + }, + { + MAIN_INT_STATUS_INTCOGNTFULLABORT_MASK, + "COGNTFULLABORT", + false, + }, + { + MAIN_INT_STATUS_INTBADUPFRLEN_MASK, + "BADUPFRLEN", + true, + }, + { + MAIN_INT_STATUS_INTUPTARDYPACKET_MASK, + "UPTARDYPACKET", + false, + }, + { + MAIN_INT_STATUS_INTBIFIFOOVERRUN_MASK, + "BIFIFOOVERRUN", + true, + }, + { + MAIN_INT_STATUS_INTBURSTGNTTOOBIG_MASK, + "BURSTGNTTOOBIG", + false, + }, + { + MAIN_INT_STATUS_INTWRGNTTOOBIG_MASK, + "WRGNTTOOBIG", + false, + }, + { + MAIN_INT_STATUS_INTRCVGNTTOOBIG_MASK, + "RCVGNTTOOBIG", + false, + }, + { + MAIN_INT_STATUS_INTDNSTATSOVERRUN_MASK, + "DNSTATSOVERRUN", + false, + }, + { + MAIN_INT_STATUS_INTUPSTATSOVERRUN_MASK, + "UPSTATSOVERRUN", + false, + }, + { + MAIN_INT_STATUS_INTDNOUTOFORDER_MASK, + "DNOUTOFORDER", + false, + true, + }, + { + MAIN_INT_STATUS_INTTRUANTBBHHALT_MASK, + "TRUANTBBHHALT", + true, + }, + { + MAIN_INT_STATUS_INTCOBBHUPSFAULT_MASK, + "COBBHUPSFAULT", + true, + }, + { + MAIN_INT_STATUS_INTDNTIMENOTINSYNC_MASK, + "DNTIMENOTINSYNC", + true, + true, + }, +}; + +/* + * + */ +static bool epon_has_fatal_pending_irq(struct xport_epon_priv *mode) +{ + u32 val; + size_t i; + bool fatal; + bool reg_done; + + /* make sure we still receive grant */ + if (mode->reg_state == EPON_REG_COMPLETE) { + val = epon_epn_reg_readl(mode, EPN_GNT_INTV_INT_STATUS_REG); + if ((val & (1 << 0))) { + netdev_err(mode->port->priv->netdev, + "not receiving any grant on user " + "llid anymore\n"); + return true; + } + } + + val = epon_epn_reg_readl(mode, EPN_MAIN_INT_STATUS_REG); + if (!val) + return false; + + reg_done = (mode->reg_state == EPON_REG_COMPLETE); + fatal = false; + for (i = 0; i < ARRAY_SIZE(epn_irqs); i++) { + if (!(epn_irqs[i].mask & val)) + continue; + + if (epn_irqs[i].ignore_when_not_reg && !reg_done) + continue; + + netdev_err(mode->port->priv->netdev, + "%slink IRQ pending: %s\n", + epn_irqs[i].fatal ? "fatal " : "", + epn_irqs[i].name); + + fatal |= epn_irqs[i].fatal; + } + + epon_epn_reg_writel(mode, EPN_MAIN_INT_STATUS_REG, val); + return fatal; +} + +/* + * + */ +static void glob_link_work(struct work_struct *w) +{ + struct delayed_work *dwork = to_delayed_work(w); + struct xport_epon_priv *mode; + bool link; + + mode = container_of(dwork, struct xport_epon_priv, glob_link_work); + + switch (mode->glob_link_state) { + case EPON_GLINK_DOWN: + link = !epon_hw_get_los(mode); + if (!link) { + glob_link_work_resched(mode); + return; + } + + mode->glob_link_state = EPON_GLINK_UP; + phylink_mac_change(mode->port->priv->phylink, true); + glob_link_work_resched(mode); + break; + + case EPON_GLINK_UP: + link = !epon_hw_get_los(mode); + if (!link) { + netdev_info(mode->port->priv->netdev, + "PCS link down\n"); + mode->glob_link_state = EPON_GLINK_FAILED; + phylink_mac_change(mode->port->priv->phylink, false); + bcm_enet_runner_schedule_reset(mode->port->priv, 0); + return; + } + + if (epon_has_fatal_pending_irq(mode)) { + netdev_err(mode->port->priv->netdev, + "fatal IRQ, will reset\n"); + mode->glob_link_state = EPON_GLINK_FAILED; + phylink_mac_change(mode->port->priv->phylink, false); + epon_schedule_reset_backoff(mode); + return; + } + + if (mode->reg_state == EPON_REG_WAIT_REGISTER && + time_after(jiffies, + mode->reg_state_last_change + HZ * 5)) { + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + mode->reg_state_last_change = jiffies; + mode->mib.reg_mpcp_rx_reg_timeout++; + netdev_info(mode->port->priv->netdev, + "restart stalled registration\n"); + } + + glob_link_work_resched(mode); + break; + + case EPON_GLINK_FAILED: + break; + } +} + +/* + * + */ +static int __epon_start(struct xport_epon_priv *mode, + unsigned int down_speed, unsigned int up_speed) +{ + switch (down_speed) { + case 10000: + break; + default: + BUG(); + return -ENOTSUPP; + } + + switch (up_speed) { + case 1000: + break; + default: + BUG(); + return -ENOTSUPP; + } + + BUG_ON(mode->glob_link_state != EPON_GLINK_DOWN); + BUG_ON(mode->reg_state != EPON_REG_WAIT_DISCOVERY); + mode->reg_state_last_change = jiffies; + mode->user_cfg.burst_cap = DEFAULT_BURST_CAP; + + mode->down_speed = down_speed; + mode->up_speed = up_speed; + mode->start_count++; + + /* create static links we need */ + mode->user_link = epon_link_alloc(mode, USER_LLID_IDX); + if (!mode->user_link) + return 1; + + mode->bcast_link = epon_link_alloc(mode, BROADCAST_LLID_IDX); + if (!mode->bcast_link) { + epon_link_release(mode, mode->bcast_link); + mode->bcast_link = NULL; + return 1; + } + + /* low level hardware init */ + xport_serdes_set_params(mode->port, &serdes_params_10g_1g); + epon_hw_init(mode); + + /* start link work & enable registration */ + epon_link_start_rx_only(mode, + mode->bcast_link, + get_broadcast_llid(mode)); + epon_link_start_bidir(mode, + mode->user_link, + get_broadcast_llid(mode)); + epon_link_pass_gates_frame(mode, + mode->user_link, + true); + + dev_add_pack(&mode->reg_tap); + glob_link_work_resched(mode); + return 0; +} + +/* + * + */ +static void __epon_stop(struct xport_epon_priv *mode) +{ + struct epon_link *link; + + /* stop */ + cancel_delayed_work_sync(&mode->glob_link_work); + dev_remove_pack(&mode->reg_tap); + flush_workqueue(mode->epon_wq); + + /* make sure carrier is off */ + phylink_mac_change(mode->port->priv->phylink, false); + netif_carrier_off(mode->port->priv->netdev); + + /* try to avoid any spurious TX while we reset */ + epon_hw_set_laser_normal_op(mode, false); + + /* NOTE: netdevice queues are stopped */ + bcm_runner_fw_stop_tx(mode->port->priv); + + /* nothing is touching hardware now, stop all links */ + mutex_lock(&mode->links_lock); + list_for_each_entry(link, &mode->links_list, next) + epon_link_stop(mode, link); + mutex_unlock(&mode->links_lock); + + if (!bcm_runner_fw_tx_is_stopped(mode->port->priv)) + netdev_err(mode->port->priv->netdev, + "failed to stop TX runner DMA\n"); + + /* + * reset state + */ + mode->glob_link_state = EPON_GLINK_DOWN; + mode->reg_state = EPON_REG_WAIT_DISCOVERY; + memset(&mode->reg_cfg, 0, sizeof (mode->reg_cfg)); + memset(&mode->user_cfg, 0, sizeof (mode->user_cfg)); + + epon_link_release(mode, mode->bcast_link); + mode->bcast_link = NULL; + epon_link_release(mode, mode->user_link); + mode->user_link = NULL; + mode->down_speed = 0; + mode->up_speed = 0; +} + +/* + * + */ +static int __epon_add_mcast_llid(struct xport_epon_priv *mode, + unsigned int llid) +{ + struct epon_link *link; + + if (epon_link_find(mode, llid)) + return -EEXIST; + + link = epon_link_alloc(mode, -1); + if (!link) + return -ENOSPC; + + epon_link_start_rx_only(mode, link, llid); + mode->links_mcast |= (1 << link->idx); + return 0; +} + +/* + * + */ +static int __epon_del_mcast_llid(struct xport_epon_priv *mode, + unsigned int llid) +{ + struct epon_link *link; + + link = epon_link_find(mode, llid); + if (!link) + return -ENOENT; + + epon_link_stop(mode, link); + epon_link_release(mode, link); + mode->links_mcast &= ~(1 << link->idx); + return 0; +} + +/* + * + */ +static void __epon_del_all_mcast_llid(struct xport_epon_priv *mode) +{ + struct epon_link *link, *tmp; + + mutex_lock(&mode->links_lock); + list_for_each_entry_safe(link, tmp, &mode->links_list, next) { + if ((1 << link->idx) & mode->links_mcast) { + epon_link_stop(mode, link); + __epon_link_release(mode, link); + } + } + mutex_unlock(&mode->links_lock); + mode->links_mcast = 0; +} + +/* + * + */ +static int epon_start(struct xport_epon_priv *mode, + unsigned int down_speed, unsigned int up_speed) + +{ + int ret; + + bcm_enet_runner_unschedule_reset(mode->port->priv); + mutex_lock(&mode->epon_lock); + if (WARN_ON(mode->epon_started)) + ret = -EBUSY; + else { + ret = __epon_start(mode, down_speed, up_speed); + if (!ret) + mode->epon_started = true; + } + mutex_unlock(&mode->epon_lock); + return ret; +} + +/* + * + */ +static void epon_stop(struct xport_epon_priv *mode) +{ + mutex_lock(&mode->epon_lock); + if (mode->epon_started) + __epon_stop(mode); + mode->epon_started = false; + memset(&mode->mib, 0, sizeof (mode->mib)); + __epon_del_all_mcast_llid(mode); + mutex_unlock(&mode->epon_lock); + bcm_enet_runner_unschedule_reset(mode->port->priv); +} + +/* + * + */ +static int mode_get_epon_param(void *mode_priv, + struct ethtool_epon_param *param) +{ + struct xport_epon_priv *mode = mode_priv; + bool last_encrypted; + unsigned int last_encrypted_key_id; + + memset(param, 0, sizeof (*param)); + param->change_count = mode->start_count; + + if (!mode->epon_started) + return 0; + + mutex_lock(&mode->epon_lock); + param->burst_cap = mode->user_cfg.burst_cap; + param->discovery_rx = (mode->mib.reg_mpcp_rx_disc > 0); + param->registered = (mode->reg_state == EPON_REG_COMPLETE); + if (!param->registered) { + mutex_unlock(&mode->epon_lock); + return 0; + } + + param->llid = mode->reg_cfg.assigned_llid; + param->down_encrypt = mode->user_cfg.down_enc_enabled; + + memcpy(param->key_sci, mode->user_cfg.key_sci, + sizeof (param->key_sci)); + memcpy(param->down_key0, mode->user_cfg.down_key0, + sizeof (param->down_key0)); + memcpy(param->down_key1, mode->user_cfg.down_key1, + sizeof (param->down_key1)); + + epon_hw_get_llid_last_rx_encrypt(mode, + mode->user_link->idx, + &last_encrypted, + &last_encrypted_key_id); + param->down_last_rx_encrypted = last_encrypted; + param->down_last_rx_key_id = last_encrypted_key_id; + + mutex_unlock(&mode->epon_lock); + return 0; +} + +/* + * + */ +static int mode_set_epon_param(void *mode_priv, + const struct ethtool_epon_param *param) +{ + struct xport_epon_priv *mode = mode_priv; + int ret; + + if (!mode->epon_started) + return -ENETDOWN; + + switch (param->cmd) { + case ETHTOOL_SEPON_KEYS: + { + u8 *d; + const u8 *s; + + if (param->keys_update_id == 0) { + s = param->down_key0; + d = mode->user_cfg.down_key0; + } else if (param->keys_update_id == 1) { + s = param->down_key1; + d = mode->user_cfg.down_key1; + } else + return -EINVAL; + + memcpy(d, s, sizeof (mode->user_cfg.down_key0)); + memcpy(mode->user_cfg.key_sci, param->key_sci, + sizeof (mode->user_cfg.key_sci)); + + mutex_lock(&mode->epon_lock); + epon_hw_set_down_key(mode, + mode->user_link->idx, + param->keys_update_id, + s, + param->key_sci); + mutex_unlock(&mode->epon_lock); + break; + } + case ETHTOOL_SEPON_ENCRYPT: + mode->user_cfg.down_enc_enabled = param->down_encrypt; + break; + case ETHTOOL_SEPON_BURST: + mode->user_cfg.burst_cap = param->burst_cap; + mutex_lock(&mode->epon_lock); + epon_hw_set_burst_cap(mode, mode->user_cfg.burst_cap); + mutex_unlock(&mode->epon_lock); + break; + case ETHTOOL_SEPON_RESTART: + netdev_info(mode->port->priv->netdev, + "restart link request from userspace\n"); + bcm_enet_runner_schedule_reset(mode->port->priv, 0); + break; + case ETHTOOL_SEPON_ADD_MCLLID: + mutex_lock(&mode->epon_lock); + ret = __epon_add_mcast_llid(mode, param->mcast_llid); + mutex_unlock(&mode->epon_lock); + return ret; + case ETHTOOL_SEPON_DEL_MCLLID: + mutex_lock(&mode->epon_lock); + ret = __epon_del_mcast_llid(mode, param->mcast_llid); + mutex_unlock(&mode->epon_lock); + return ret; + case ETHTOOL_SEPON_CLR_MCLLID: + mutex_lock(&mode->epon_lock); + __epon_del_all_mcast_llid(mode); + mutex_unlock(&mode->epon_lock); + break; + default: + return -EOPNOTSUPP; + } + return 0; +} + +/* + * + */ +static void mode_phylink_mac_config(void *mode_priv, + unsigned int pl_mode, + const struct phylink_link_state *state) +{ + struct xport_epon_priv *mode = mode_priv; + + mutex_lock(&mode->epon_lock); + if (!mode->epon_started) + mutex_unlock(&mode->epon_lock); + else { + /* cannot be reconfigured while device is up, schedule + * reset if parameters changed */ + bool changed; + + switch (state->interface) { + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + changed = (mode->down_speed != 10000) || + (mode->up_speed != 1000); + break; + default: + changed = false; + break; + } + + if (changed) + bcm_enet_runner_schedule_reset(mode->port->priv, 0); + mutex_unlock(&mode->epon_lock); + return; + } + + switch (state->interface) { + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + epon_start(mode, 10000, 1000); + break; + default: + BUG(); + break; + } +} + +/* + * called for each packet during netdevice xmit + */ +static bool mode_epon_can_send(void *mode_priv, unsigned int protocol) +{ + struct xport_epon_priv *mode = mode_priv; + + switch (protocol) { + case ETH_P_PAUSE: + return true; + default: + return mode->reg_state == EPON_REG_COMPLETE; + } +} + +/* + * called each time netdevice is stopped + */ +static void mode_epon_stop(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + epon_stop(mode); +} + +/* + * + */ +static void mode_phylink_validate(void *mode_priv, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + __ETHTOOL_DECLARE_LINK_MODE_MASK(supp_only_mask) = { 0, }; + + phylink_set_port_modes(supp_only_mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + phylink_set(supp_only_mask, Autoneg); + phylink_set(supp_only_mask, 10000_1000basePRX_U_Full); + + switch (state->interface) { + case PHY_INTERFACE_MODE_NA: + /* probing, return all supported link speed */ + state->interface = PHY_INTERFACE_MODE_10000_1000_BASEPRX_U; + goto end; + + case PHY_INTERFACE_MODE_10000_1000_BASEPRX_U: + default: + break; + } + + /* select correct interface mode based on requested speed */ + if (phylink_test(state->advertising, 10000_1000basePRX_U_Full)) { + phylink_set(mask, 10000_1000basePRX_U_Full); + phylink_set(mask, Autoneg); + state->interface = PHY_INTERFACE_MODE_10000_1000_BASEPRX_U; + } else { + /* default mode */ + state->interface = PHY_INTERFACE_MODE_10000_1000_BASEPRX_U; + } + +end: + linkmode_copy(supported, supp_only_mask); + linkmode_copy(state->advertising, mask); +} + +/* + * + */ +static void mode_phylink_link_up(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + struct phy_device *phy) +{ + /* not used */ +} + +/* + * + */ +static void mode_phylink_link_down(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface) +{ + /* not used */ +} + +/* + * + */ +static void mode_phylink_pcs_an_restart(void *mode_priv) +{ + /* not supported */ +} + +/* + * + */ +static int mode_phylink_pcs_link_state(void *mode_priv, + struct phylink_link_state *state) +{ + struct xport_epon_priv *mode = mode_priv; + + /* fake link down after failed registration */ + state->link = ((mode->glob_link_state == EPON_GLINK_UP) && + (mode->reg_state != EPON_REG_FAILED)); + if (state->link) { + state->an_complete = 1; + state->speed = 10000; + state->duplex = 1; + } + + return 0; +} + +/* + * + */ +static void *mode_epon_init(void *port_priv, + const struct bcm_xrdp_enet_params *params) +{ + struct xport_priv *port = port_priv; + struct xport_epon_priv *mode; + char name[64]; + size_t i; + + mode = kzalloc(sizeof (*mode), GFP_KERNEL); + if (!mode) + return ERR_PTR(-ENOMEM); + + mode->port = port; + INIT_DELAYED_WORK(&mode->glob_link_work, glob_link_work); + mutex_init(&mode->links_lock); + INIT_LIST_HEAD(&mode->links_list); + mode->links_free = (1 << USER_LLID_IDX) | (1 << BROADCAST_LLID_IDX); + /* ethtool mib only reports llid 24 to 30 rx bytes, don't use + * other llid */ + for (i = 24; i < 31; i++) + mode->links_free |= (1 << i); + + mutex_init(&mode->epon_lock); + mode->epon_reset_duration_ms = 100; + + /* capture mac address */ + memcpy(mode->mac_addr, + mode->port->priv->netdev->dev_addr, + ETH_ALEN); + + /* set default config */ + mode->laser_active_hi = false; + + scnprintf(name, sizeof (name), "%s-epon", port->priv->netdev->name); + mode->epon_wq = create_singlethread_workqueue(name); + if (!mode->epon_wq) { + kfree(mode); + return ERR_PTR(-ENOMEM); + } + + /* setup MPCP TAP */ + mode->reg_tap.type = cpu_to_be16(ETH_P_PAUSE); + mode->reg_tap.func = mpcp_rcv_handler; + mode->reg_tap.af_packet_priv = mode; + mode->reg_tap.ignore_outgoing = true; + mode->reg_tap.dev = port->priv->netdev; + + mode_epon_dbg_init(mode); + return mode; +} + +/* + * called only when netdevice is stopped + */ +static void mode_epon_release(void *mode_priv) +{ + struct xport_epon_priv *mode = mode_priv; + mode_epon_dbg_release(mode); + destroy_workqueue(mode->epon_wq); + kfree(mode); +} + +/* + * + */ +static u32 mode_get_bbh_id(void *port_priv) +{ + struct xport_priv *port = port_priv; + return port->pon_bbh_id; +} + +const struct bcm_enet_mode_ops xport_epon_mode_ops = { + .name = "EPON", + + .init = mode_epon_init, + .release = mode_epon_release, + .can_send = mode_epon_can_send, + + .stop = mode_epon_stop, + .get_bbh_id = mode_get_bbh_id, + .mtu_set = mode_epon_mtu_set, + + /* ethtool operations*/ + .get_epon_param = mode_get_epon_param, + .set_epon_param = mode_set_epon_param, + + /* mib operation */ + .mib_estat = epon_mib_estat, + .mib_estat_count = ARRAY_SIZE(epon_mib_estat), + .mib_update = mode_epon_mib_update, + .mib_get_data = mode_epon_mib_get_data, + + /* + * phylink callback + */ + .phylink_validate = mode_phylink_validate, + .phylink_mac_config = mode_phylink_mac_config, + .phylink_link_down = mode_phylink_link_down, + .phylink_link_up = mode_phylink_link_up, + .phylink_pcs_link_state = mode_phylink_pcs_link_state, + .phylink_pcs_an_restart = mode_phylink_pcs_an_restart, +}; diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon_dbg.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon_dbg.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon_dbg.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon_dbg.c 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,537 @@ +#include "port_xport_epon.h" + +enum { + REG_XPCS_RX, + REG_XIF, + REG_LIF, + REG_EPN, +}; + +struct reg_desc { + const char *name; + u32 offset; + unsigned int type; +}; + +static const struct reg_desc epon_regs[] = { + { "EPN_CONTROL_0", EPN_CONTROL_0_REG, REG_EPN, }, + { "EPN_CONTROL_1", EPN_CONTROL_1_REG, REG_EPN, }, + { "EPN_ENABLE_GRANTS", EPN_ENABLE_GRANTS_REG, REG_EPN, }, + { "EPN_DROP_DISC_GATES", EPN_DROP_DISC_GATES_REG, REG_EPN, }, + { "EPN_DIS_FCS_CHK", EPN_DIS_FCS_CHK_REG, REG_EPN, }, + { "EPN_PASS_GATES", EPN_PASS_GATES_REG, REG_EPN, }, + { "EPN_CFG_MISALGN_FB", EPN_CFG_MISALGN_FB_REG, REG_EPN, }, + { "EPN_DISCOVERY_FILTER", EPN_DISCOVERY_FILTER_REG, REG_EPN, }, + { "EPN_MINIMUM_GRANT_SETUP", EPN_MINIMUM_GRANT_SETUP_REG, REG_EPN, }, + { "EPN_RESET_GNT_FIFO", EPN_RESET_GNT_FIFO_REG, REG_EPN, }, + { "EPN_RESET_L1_ACCUMULATOR", EPN_RESET_L1_ACCUMULATOR_REG, REG_EPN, }, + { "EPN_L1_ACCUMULATOR_SEL", EPN_L1_ACCUMULATOR_SEL_REG, REG_EPN, }, + { "EPN_L1_SVA_BYTES", EPN_L1_SVA_BYTES_REG, REG_EPN, }, + { "EPN_L1_UVA_BYTES", EPN_L1_UVA_BYTES_REG, REG_EPN, }, + { "EPN_L1_SVA_OVERFLOW", EPN_L1_SVA_OVERFLOW_REG, REG_EPN, }, + { "EPN_L1_UVA_OVERFLOW", EPN_L1_UVA_OVERFLOW_REG, REG_EPN, }, + { "EPN_RESET_RPT_PRI", EPN_RESET_RPT_PRI_REG, REG_EPN, }, + { "EPN_RESET_L2_RPT_FIFO", EPN_RESET_L2_RPT_FIFO_REG, REG_EPN, }, + { "EPN_ENABLE_UPSTREAM", EPN_ENABLE_UPSTREAM_REG, REG_EPN, }, + { "EPN_ENABLE_UPSTREAM_FB", EPN_ENABLE_UPSTREAM_FB_REG, REG_EPN, }, + { "EPN_ENABLE_UPSTREAM_FEC", EPN_ENABLE_UPSTREAM_FEC_REG, REG_EPN, }, + { "EPN_REPORT_BYTE_LENGTH", EPN_REPORT_BYTE_LENGTH_REG, REG_EPN, }, + { "EPN_MAIN_INT_STATUS", EPN_MAIN_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_FULL_INT_STATUS", EPN_GNT_FULL_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_FULL_INT_MASK", EPN_GNT_FULL_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_MISS_INT_STATUS", EPN_GNT_MISS_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_MISS_INT_MASK", EPN_GNT_MISS_INT_MASK_REG, REG_EPN, }, + { "EPN_DISC_RX_INT_STATUS", EPN_DISC_RX_INT_STATUS_REG, REG_EPN, }, + { "EPN_DISC_RX_INT_MASK", EPN_DISC_RX_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_INTV_INT_STATUS", EPN_GNT_INTV_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_INTV_INT_MASK", EPN_GNT_INTV_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_FAR_INT_STATUS", EPN_GNT_FAR_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_FAR_INT_MASK", EPN_GNT_FAR_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_MISALGN_INT_STATUS", EPN_GNT_MISALGN_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_MISALGN_INT_MASK", EPN_GNT_MISALGN_INT_MASK_REG, REG_EPN, }, + { "EPN_NP_GNT_INT_STATUS", EPN_NP_GNT_INT_STATUS_REG, REG_EPN, }, + { "EPN_NP_GNT_INT_MASK", EPN_NP_GNT_INT_MASK_REG, REG_EPN, }, + { "EPN_DEL_STALE_INT_STATUS", EPN_DEL_STALE_INT_STATUS_REG, REG_EPN, }, + { "EPN_DEL_STALE_INT_MASK", EPN_DEL_STALE_INT_MASK_REG, REG_EPN, }, + { "EPN_GNT_PRES_INT_STATUS", EPN_GNT_PRES_INT_STATUS_REG, REG_EPN, }, + { "EPN_GNT_PRES_INT_MASK", EPN_GNT_PRES_INT_MASK_REG, REG_EPN, }, + { "EPN_RPT_PRES_INT_STATUS", EPN_RPT_PRES_INT_STATUS_REG, REG_EPN, }, + { "EPN_RPT_PRES_INT_MASK", EPN_RPT_PRES_INT_MASK_REG, REG_EPN, }, + { "EPN_DRX_ABORT_INT_STATUS", EPN_DRX_ABORT_INT_STATUS_REG, REG_EPN, }, + { "EPN_DRX_ABORT_INT_MASK", EPN_DRX_ABORT_INT_MASK_REG, REG_EPN, }, + { "EPN_EMPTY_RPT_INT_STATUS", EPN_EMPTY_RPT_INT_STATUS_REG, REG_EPN, }, + { "EPN_EMPTY_RPT_INT_MASK", EPN_EMPTY_RPT_INT_MASK_REG, REG_EPN, }, + { "EPN_BCAP_OVERFLOW_INT_STATUS", EPN_BCAP_OVERFLOW_INT_STATUS_REG, REG_EPN, }, + { "EPN_BCAP_OVERFLOW_INT_MASK", EPN_BCAP_OVERFLOW_INT_MASK_REG, REG_EPN, }, + { "EPN_BBH_DNS_FAULT_INT_STATUS", EPN_BBH_DNS_FAULT_INT_STATUS_REG, REG_EPN, }, + { "EPN_BBH_DNS_FAULT_INT_MASK", EPN_BBH_DNS_FAULT_INT_MASK_REG, REG_EPN, }, + { "EPN_BBH_UPS_FAULT_INT_STATUS", EPN_BBH_UPS_FAULT_INT_STATUS_REG, REG_EPN, }, + { "EPN_BBH_UPS_FAULT_INT_MASK", EPN_BBH_UPS_FAULT_INT_MASK_REG, REG_EPN, }, + { "EPN_BBH_UPS_ABORT_INT_STATUS", EPN_BBH_UPS_ABORT_INT_STATUS_REG, REG_EPN, }, + { "EPN_BBH_UPS_ABORT_INT_MASK", EPN_BBH_UPS_ABORT_INT_MASK_REG, REG_EPN, }, + { "EPN_MAIN_INT_MASK", EPN_MAIN_INT_MASK_REG, REG_EPN, }, + { "EPN_MAX_GNT_SIZE", EPN_MAX_GNT_SIZE_REG, REG_EPN, }, + { "EPN_MAX_FRAME_SIZE", EPN_MAX_FRAME_SIZE_REG, REG_EPN, }, + { "EPN_GRANT_OVR_HD", EPN_GRANT_OVR_HD_REG, REG_EPN, }, + { "EPN_POLL_SIZE", EPN_POLL_SIZE_REG, REG_EPN, }, + { "EPN_DN_RD_GNT_MARGIN", EPN_DN_RD_GNT_MARGIN_REG, REG_EPN, }, + { "EPN_GNT_TIME_START_DELTA", EPN_GNT_TIME_START_DELTA_REG, REG_EPN, }, + { "EPN_TIME_STAMP_DIFF", EPN_TIME_STAMP_DIFF_REG, REG_EPN, }, + { "EPN_UP_TIME_STAMP_OFF", EPN_UP_TIME_STAMP_OFF_REG, REG_EPN, }, + { "EPN_GNT_INTERVAL", EPN_GNT_INTERVAL_REG, REG_EPN, }, + { "EPN_DN_GNT_MISALIGN_THR", EPN_DN_GNT_MISALIGN_THR_REG, REG_EPN, }, + { "EPN_DN_GNT_MISALIGN_PAUSE", EPN_DN_GNT_MISALIGN_PAUSE_REG, REG_EPN, }, + { "EPN_NON_POLL_INTV", EPN_NON_POLL_INTV_REG, REG_EPN, }, + { "EPN_FORCE_FCS_ERR", EPN_FORCE_FCS_ERR_REG, REG_EPN, }, + { "EPN_GRANT_OVERLAP_LIMIT", EPN_GRANT_OVERLAP_LIMIT_REG, REG_EPN, }, + { "EPN_AES_CONFIGURATION_0", EPN_AES_CFG_0_REG, REG_EPN, }, + { "EPN_DISC_GRANT_OVR_HD", EPN_DISC_GRANT_OVR_HD_REG, REG_EPN, }, + { "EPN_DN_DISCOVERY_SEED", EPN_DN_DISCOVERY_SEED_REG, REG_EPN, }, + { "EPN_DN_DISCOVERY_INC", EPN_DN_DISCOVERY_INC_REG, REG_EPN, }, + { "EPN_DN_DISCOVERY_SIZE", EPN_DN_DISCOVERY_SIZE_REG, REG_EPN, }, + { "EPN_FEC_IPG_LENGTH", EPN_FEC_IPG_LENGTH_REG, REG_EPN, }, + { "EPN_FAKE_REPORT_VALUE_EN", EPN_FAKE_REPORT_VALUE_EN_REG, REG_EPN, }, + { "EPN_FAKE_REPORT_VALUE", EPN_FAKE_REPORT_VALUE_REG, REG_EPN, }, + { "EPN_BURST_CAP_0", EPN_BURST_CAPx_0_7_REG(0), REG_EPN, }, + { "EPN_BURST_CAP_1", EPN_BURST_CAPx_0_7_REG(1), REG_EPN, }, + { "EPN_BURST_CAP_2", EPN_BURST_CAPx_0_7_REG(2), REG_EPN, }, + { "EPN_BURST_CAP_3", EPN_BURST_CAPx_0_7_REG(3), REG_EPN, }, + { "EPN_BURST_CAP_4", EPN_BURST_CAPx_0_7_REG(4), REG_EPN, }, + { "EPN_BURST_CAP_5", EPN_BURST_CAPx_0_7_REG(5), REG_EPN, }, + { "EPN_BURST_CAP_6", EPN_BURST_CAPx_0_7_REG(6), REG_EPN, }, + { "EPN_BURST_CAP_7", EPN_BURST_CAPx_0_7_REG(7), REG_EPN, }, + + { "EPN_QUEUE_LLID_MAP_0", EPN_QUEUE_LLID_MAPx_0_7_REG(0), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_1", EPN_QUEUE_LLID_MAPx_0_7_REG(1), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_2", EPN_QUEUE_LLID_MAPx_0_7_REG(2), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_3", EPN_QUEUE_LLID_MAPx_0_7_REG(3), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_4", EPN_QUEUE_LLID_MAPx_0_7_REG(4), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_5", EPN_QUEUE_LLID_MAPx_0_7_REG(5), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_6", EPN_QUEUE_LLID_MAPx_0_7_REG(6), REG_EPN, }, + { "EPN_QUEUE_LLID_MAP_7", EPN_QUEUE_LLID_MAPx_0_7_REG(7), REG_EPN, }, + + { "EPN_VALID_OPCODE_MAP", EPN_VALID_OPCODE_MAP_REG, REG_EPN, }, + { "EPN_UP_PACKET_TX_MARGIN", EPN_UP_PACKET_TX_MARGIN_REG, REG_EPN, }, + { "EPN_MULTI_PRI_CFG_0", EPN_MULTI_PRI_CFG_0_REG, REG_EPN, }, + { "EPN_SHARED_BCAP_OVRFLOW", EPN_SHARED_BCAP_OVRFLOW_REG, REG_EPN, }, + { "EPN_FORCED_REPORT_EN", EPN_FORCED_REPORT_EN_REG, REG_EPN, }, + { "EPN_FORCED_REPORT_MAX_INTERVAL", EPN_FORCED_REPORT_MAX_INTERVAL_REG, REG_EPN, }, + { "EPN_L2S_FLUSH_CONFIG", EPN_L2S_FLUSH_CONFIG_REG, REG_EPN, }, + { "EPN_DATA_PORT_COMMAND", EPN_DATA_PORT_COMMAND_REG, REG_EPN, }, + { "EPN_DATA_PORT_ADDRESS", EPN_DATA_PORT_ADDR_REG, REG_EPN, }, + { "EPN_DATA_PORT_DATA_0", EPN_DATA_PORT_DATA_0_REG, REG_EPN, }, + { "EPN_UNMAP_BIG_CNT", EPN_UNMAP_BIG_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_FRAME_CNT", EPN_UNMAP_FRAME_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_FCS_CNT", EPN_UNMAP_FCS_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_GATE_CNT", EPN_UNMAP_GATE_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_OAM_CNT", EPN_UNMAP_OAM_CNT_REG, REG_EPN, }, + { "EPN_UNMAP_SMALL_CNT", EPN_UNMAP_SMALL_CNT_REG, REG_EPN, }, + { "EPN_FIF_DEQUEUE_EVENT_CNT", EPN_FIF_DEQUEUE_EVENT_CNT_REG, REG_EPN, }, + { "EPN_UNUSED_TQ_CNT0", EPN_UNUSED_TQ_CNTx_0_7_REG(0), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT1", EPN_UNUSED_TQ_CNTx_0_7_REG(1), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT2", EPN_UNUSED_TQ_CNTx_0_7_REG(2), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT3", EPN_UNUSED_TQ_CNTx_0_7_REG(3), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT4", EPN_UNUSED_TQ_CNTx_0_7_REG(4), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT5", EPN_UNUSED_TQ_CNTx_0_7_REG(5), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT6", EPN_UNUSED_TQ_CNTx_0_7_REG(6), REG_EPN, }, + { "EPN_UNUSED_TQ_CNT7", EPN_UNUSED_TQ_CNTx_0_7_REG(7), REG_EPN, }, + + { "EPN_BBH_UP_FAULT_HALT_EN", EPN_BBH_UP_FAULT_HALT_EN_REG, REG_EPN, }, + { "EPN_BBH_UP_TARDY_HALT_EN", EPN_BBH_UP_TARDY_HALT_EN_REG, REG_EPN, }, + { "EPN_DEBUG_STATUS_0", EPN_DEBUG_STATUS_0_REG, REG_EPN, }, + { "EPN_DEBUG_STATUS_1", EPN_DEBUG_STATUS_1_REG, REG_EPN, }, + { "EPN_DEBUG_L2S_PTR_SEL", EPN_DEBUG_L2S_PTR_SEL_REG, REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_0", EPN_ONU_MAC_ADDRx_0_7_LO_REG(0), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_0", EPN_ONU_MAC_ADDRx_0_7_HI_REG(0), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_1", EPN_ONU_MAC_ADDRx_0_7_LO_REG(1), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_1", EPN_ONU_MAC_ADDRx_0_7_HI_REG(1), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_2", EPN_ONU_MAC_ADDRx_0_7_LO_REG(2), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_2", EPN_ONU_MAC_ADDRx_0_7_HI_REG(2), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_3", EPN_ONU_MAC_ADDRx_0_7_LO_REG(3), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_3", EPN_ONU_MAC_ADDRx_0_7_HI_REG(3), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_4", EPN_ONU_MAC_ADDRx_0_7_LO_REG(4), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_4", EPN_ONU_MAC_ADDRx_0_7_HI_REG(4), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_5", EPN_ONU_MAC_ADDRx_0_7_LO_REG(5), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_5", EPN_ONU_MAC_ADDRx_0_7_HI_REG(5), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_6", EPN_ONU_MAC_ADDRx_0_7_LO_REG(6), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_6", EPN_ONU_MAC_ADDRx_0_7_HI_REG(6), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_LO_7", EPN_ONU_MAC_ADDRx_0_7_LO_REG(7), REG_EPN, }, + { "EPN_ONU_MAC_ADDR_HI_7", EPN_ONU_MAC_ADDRx_0_7_HI_REG(7), REG_EPN, }, + { "EPN_OLT_MAC_ADDR_LO", EPN_OLT_MAC_ADDR_LO_REG, REG_EPN, }, + { "EPN_OLT_MAC_ADDR_HI", EPN_OLT_MAC_ADDR_HI_REG, REG_EPN, }, + + { "EPN_TX_L1S_SHP_CONFIG_0", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_0", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_1", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_1", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_2", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_2", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_3", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_3", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_4", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_4", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_5", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_5", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_6", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_6", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L1S_SHP_CONFIG_7", EPN_TX_L1S_SHP_CONFIGx_0_7_REG(7), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_EN_7", EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(7), REG_EPN, }, + + { "EPN_TX_L1S_SHP_DQU_EMPTY", EPN_TX_L1S_SHP_DQU_EMPTY_REG, REG_EPN, }, + { "EPN_TX_L1S_UNSHAPED_EMPTY", EPN_TX_L1S_UNSHAPED_EMPTY_REG, REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_0", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_1", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_2", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_3", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_4", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_5", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_6", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L1S_SHP_QUE_MASK_7", EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(7), REG_EPN, }, + + { "EPN_TX_L2S_QUE_CONFIG_0", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_1", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_2", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_3", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_4", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_5", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_6", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_L2S_QUE_CONFIG_7", EPN_TX_L2S_QUE_CONFIGx_0_7_REG(7), REG_EPN, }, + + { "EPN_TX_L2S_QUE_EMPTY", EPN_TX_L2S_QUE_EMPTY_REG, REG_EPN, }, + { "EPN_TX_L2S_QUE_FULL", EPN_TX_L2S_QUE_FULL_REG, REG_EPN, }, + { "EPN_TX_L2S_QUE_STOPPED", EPN_TX_L2S_QUE_STOPPED_REG, REG_EPN, }, + + { "EPN_TX_CTC_BURST_LIMIT_0", EPN_TX_CTC_BURST_LIMITx_0_7_REG(0), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_1", EPN_TX_CTC_BURST_LIMITx_0_7_REG(1), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_2", EPN_TX_CTC_BURST_LIMITx_0_7_REG(2), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_3", EPN_TX_CTC_BURST_LIMITx_0_7_REG(3), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_4", EPN_TX_CTC_BURST_LIMITx_0_7_REG(4), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_5", EPN_TX_CTC_BURST_LIMITx_0_7_REG(5), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_6", EPN_TX_CTC_BURST_LIMITx_0_7_REG(6), REG_EPN, }, + { "EPN_TX_CTC_BURST_LIMIT_7", EPN_TX_CTC_BURST_LIMITx_0_7_REG(7), REG_EPN, }, + + { "EPN_BBH_MAX_OUTSTANDING_TARDY_PACKETS", EPN_BBH_MAX_OUTSTANDING_TARDY_PACKETS_REG, REG_EPN, }, + { "EPN_MIN_REPORT_VALUE_DIFFERENCE", EPN_MIN_REPORT_VALUE_DIFFERENCE_REG, REG_EPN, }, + { "EPN_BBH_STATUS_FIFO_OVERFLOW", EPN_BBH_STATUS_FIFO_OVERFLOW_REG, REG_EPN, }, + { "EPN_SPARE_CTL", EPN_SPARE_CTL_REG, REG_EPN, }, + { "EPN_TS_SYNC_OFFSET", EPN_TS_SYNC_OFFSET_REG, REG_EPN, }, + { "EPN_DN_TS_OFFSET", EPN_DN_TS_OFFSET_REG, REG_EPN, }, + { "EPN_UP_TS_OFFSET_LO", EPN_UP_TS_OFFSET_LO_REG, REG_EPN, }, + { "EPN_UP_TS_OFFSET_HI", EPN_UP_TS_OFFSET_HI_REG, REG_EPN, }, + { "EPN_TWO_STEP_TS_CTL", EPN_TWO_STEP_TS_CTL_REG, REG_EPN, }, + { "EPN_TWO_STEP_TS_VALUE_LO", EPN_TWO_STEP_TS_VALUE_LO_REG, REG_EPN, }, + { "EPN_TWO_STEP_TS_VALUE_HI", EPN_TWO_STEP_TS_VALUE_HI_REG, REG_EPN, }, + { "EPN_1588_TIMESTAMP_INT_STATUS", EPN_1588_TIMESTAMP_INT_STATUS_REG, REG_EPN, }, + { "EPN_1588_TIMESTAMP_INT_MASK", EPN_1588_TIMESTAMP_INT_MASK_REG, REG_EPN, }, + { "EPN_UP_PACKET_FETCH_MARGIN", EPN_UP_PACKET_FETCH_MARGIN_REG, REG_EPN, }, + { "EPN_DN_1588_TIMESTAMP", EPN_DN_1588_TIMESTAMP_REG, REG_EPN, }, + { "EPN_PERSISTENT_REPORT_CFG", EPN_PERSISTENT_REPORT_CFG_REG, REG_EPN, }, + { "EPN_PERSISTENT_REPORT_ENABLES", EPN_PERSISTENT_REPORT_ENABLES_REG, REG_EPN, }, + { "EPN_PERSISTENT_REPORT_REQUEST_SIZE", EPN_PERSISTENT_REPORT_REQUEST_SIZE_REG, REG_EPN, }, + { "EPN_AES_CONFIGURATION_1", EPN_AES_CFG_1_REG, REG_EPN, }, + + + /* + * LIF + */ + { "LIF_PON_CONTROL", LIF_PON_CONTROL_REG, REG_LIF, }, + { "LIF_PON_INTER_OP_CONTROL", LIF_PON_INTER_OP_CONTROL_REG , REG_LIF, }, + { "LIF_FEC_CONTROL", LIF_FEC_CONTROL_REG , REG_LIF, }, + { "LIF_SEC_CONTROL", LIF_SEC_CONTROL_REG , REG_LIF, }, + { "LIF_MACSEC", LIF_MACSEC_REG , REG_LIF, }, + { "LIF_INT_STATUS", LIF_INT_STATUS_REG , REG_LIF, }, + { "LIF_INT_MASK", LIF_INT_MASK_REG , REG_LIF, }, + { "LIF_DATA_PORT_COMMAND", LIF_DATA_PORT_COMMAND_REG , REG_LIF, }, + + { "LIF_LLID_0", LIF_LLIDx_0_7_REG(0), REG_LIF, }, + { "LIF_LLID_1", LIF_LLIDx_0_7_REG(1), REG_LIF, }, + { "LIF_LLID_2", LIF_LLIDx_0_7_REG(2), REG_LIF, }, + { "LIF_LLID_3", LIF_LLIDx_0_7_REG(3), REG_LIF, }, + { "LIF_LLID_4", LIF_LLIDx_0_7_REG(4), REG_LIF, }, + { "LIF_LLID_5", LIF_LLIDx_0_7_REG(5), REG_LIF, }, + { "LIF_LLID_6", LIF_LLIDx_0_7_REG(6), REG_LIF, }, + { "LIF_LLID_7", LIF_LLIDx_0_7_REG(7), REG_LIF, }, + { "LIF_LLID_16", LIF_LLIDx_16_23_REG(0), REG_LIF, }, + { "LIF_LLID_17", LIF_LLIDx_16_23_REG(1), REG_LIF, }, + { "LIF_LLID_18", LIF_LLIDx_16_23_REG(2), REG_LIF, }, + { "LIF_LLID_19", LIF_LLIDx_16_23_REG(3), REG_LIF, }, + { "LIF_LLID_20", LIF_LLIDx_16_23_REG(4), REG_LIF, }, + { "LIF_LLID_21", LIF_LLIDx_16_23_REG(5), REG_LIF, }, + { "LIF_LLID_22", LIF_LLIDx_16_23_REG(6), REG_LIF, }, + { "LIF_LLID_23", LIF_LLIDx_16_23_REG(7), REG_LIF, }, + + { "LIF_TIME_REF_CNT", LIF_TIME_REF_CNT_REG , REG_LIF, }, + { "LIF_TIMESTAMP_UPD_PER", LIF_TIMESTAMP_UPD_PER_REG , REG_LIF, }, + { "LIF_TP_TIME", LIF_TP_TIME_REG , REG_LIF, }, + { "LIF_MPCP_TIME", LIF_MPCP_TIME_REG , REG_LIF, }, + { "LIF_MAXLEN_CTR", LIF_MAXLEN_CTR_REG , REG_LIF, }, + { "LIF_LASER_ON_DELTA", LIF_LASER_ON_DELTA_REG , REG_LIF, }, + { "LIF_LASER_OFF_IDLE", LIF_LASER_OFF_IDLE_REG , REG_LIF, }, + { "LIF_FEC_INIT_IDLE", LIF_FEC_INIT_IDLE_REG , REG_LIF, }, + { "LIF_FEC_ERR_ALLOW", LIF_FEC_ERR_ALLOW_REG , REG_LIF, }, + { "LIF_SEC_KEY_SEL", LIF_SEC_KEY_SEL_REG , REG_LIF, }, + { "LIF_DN_ENCRYPT_STAT", LIF_DN_ENCRYPT_STAT_REG , REG_LIF, }, + { "LIF_SEC_UP_KEY_STAT", LIF_SEC_UP_KEY_STAT_REG , REG_LIF, }, + { "LIF_SEC_UP_ENCRYPT_STAT", LIF_SEC_UP_ENCRYPT_STAT_REG , REG_LIF, }, + { "LIF_SEC_UP_MPCP_OFFSET", LIF_SEC_UP_MPCP_OFFSET_REG , REG_LIF, }, + { "LIF_FEC_PER_LLID", LIF_FEC_PER_LLID_REG , REG_LIF, }, + { "LIF_RX_LINE_CODE_ERR_CNT", LIF_RX_LINE_CODE_ERR_CNT_REG , REG_LIF, }, + { "LIF_RX_AGG_MPCP_FRM", LIF_RX_AGG_MPCP_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_GOOD_FRM", LIF_RX_AGG_GOOD_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_GOOD_BYTE", LIF_RX_AGG_GOOD_BYTE_REG , REG_LIF, }, + { "LIF_RX_AGG_UNDERSZ_FRM", LIF_RX_AGG_UNDERSZ_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_OVERSZ_FRM", LIF_RX_AGG_OVERSZ_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_CRC8_FRM", LIF_RX_AGG_CRC8_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_FEC_FRM", LIF_RX_AGG_FEC_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_FEC_BYTE", LIF_RX_AGG_FEC_BYTE_REG , REG_LIF, }, + { "LIF_RX_AGG_FEC_EXC_ERR_FRM", LIF_RX_AGG_FEC_EXC_ERR_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_NONFEC_GOOD_FRM", LIF_RX_AGG_NONFEC_GOOD_FRM_REG , REG_LIF, }, + { "LIF_RX_AGG_NONFEC_GOOD_BYTE", LIF_RX_AGG_NONFEC_GOOD_BYTE_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_BYTES", LIF_RX_AGG_ERR_BYTES_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_ZEROES", LIF_RX_AGG_ERR_ZEROES_REG , REG_LIF, }, + { "LIF_RX_AGG_NO_ERR_BLKS", LIF_RX_AGG_NO_ERR_BLKS_REG , REG_LIF, }, + { "LIF_RX_AGG_COR_BLKS", LIF_RX_AGG_COR_BLKS_REG , REG_LIF, }, + { "LIF_RX_AGG_UNCOR_BLKS", LIF_RX_AGG_UNCOR_BLKS_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_ONES", LIF_RX_AGG_ERR_ONES_REG , REG_LIF, }, + { "LIF_RX_AGG_ERR_FRM", LIF_RX_AGG_ERR_FRM_REG , REG_LIF, }, + { "LIF_TX_PKT_CNT", LIF_TX_PKT_CNT_REG , REG_LIF, }, + { "LIF_TX_BYTE_CNT", LIF_TX_BYTE_CNT_REG , REG_LIF, }, + { "LIF_TX_NON_FEC_PKT_CNT", LIF_TX_NON_FEC_PKT_CNT_REG , REG_LIF, }, + { "LIF_TX_NON_FEC_BYTE_CNT", LIF_TX_NON_FEC_BYTE_CNT_REG , REG_LIF, }, + { "LIF_TX_FEC_PKT_CNT", LIF_TX_FEC_PKT_CNT_REG , REG_LIF, }, + { "LIF_TX_FEC_BYTE_CNT", LIF_TX_FEC_BYTE_CNT_REG , REG_LIF, }, + { "LIF_TX_FEC_BLK_CNT", LIF_TX_FEC_BLK_CNT_REG , REG_LIF, }, + { "LIF_TX_MPCP_PKT_CNT", LIF_TX_MPCP_PKT_CNT_REG , REG_LIF, }, + { "LIF_DEBUG_TX_DATA_PKT_CNT", LIF_DEBUG_TX_DATA_PKT_CNT_REG , REG_LIF, }, + { "LIF_FEC_LLID_STATUS", LIF_FEC_LLID_STATUS_REG , REG_LIF, }, + { "LIF_SEC_RX_TEK_IG_IV_LLID", LIF_SEC_RX_TEK_IG_IV_LLID_REG , REG_LIF, }, + { "LIF_PON_BER_INTERV_THRESH", LIF_PON_BER_INTERV_THRESH_REG , REG_LIF, }, + { "LIF_LSR_MON_A_CTRL", LIF_LSR_MON_A_CTRL_REG , REG_LIF, }, + { "LIF_LSR_MON_A_MAX_THR", LIF_LSR_MON_A_MAX_THR_REG , REG_LIF, }, + { "LIF_LSR_MON_A_BST_LEN", LIF_LSR_MON_A_BST_LEN_REG , REG_LIF, }, + { "LIF_LSR_MON_A_BST_CNT", LIF_LSR_MON_A_BST_CNT_REG , REG_LIF, }, + { "LIF_DEBUG_PON_SM", LIF_DEBUG_PON_SM_REG , REG_LIF, }, + { "LIF_DEBUG_FEC_SM", LIF_DEBUG_FEC_SM_REG , REG_LIF, }, + { "LIF_AE_PKTNUM_WINDOW", LIF_AE_PKTNUM_WINDOW_REG , REG_LIF, }, + { "LIF_AE_PKTNUM_THRESH", LIF_AE_PKTNUM_THRESH_REG , REG_LIF, }, + { "LIF_AE_PKTNUM_STAT", LIF_AE_PKTNUM_STAT_REG , REG_LIF, }, + + { "LIF_LLID_8", LIF_LLIDx_8_15_REG(0), REG_LIF, }, + { "LIF_LLID_9", LIF_LLIDx_8_15_REG(1), REG_LIF, }, + { "LIF_LLID_10", LIF_LLIDx_8_15_REG(2), REG_LIF, }, + { "LIF_LLID_11", LIF_LLIDx_8_15_REG(3), REG_LIF, }, + { "LIF_LLID_12", LIF_LLIDx_8_15_REG(4), REG_LIF, }, + { "LIF_LLID_13", LIF_LLIDx_8_15_REG(5), REG_LIF, }, + { "LIF_LLID_14", LIF_LLIDx_8_15_REG(6), REG_LIF, }, + { "LIF_LLID_15", LIF_LLIDx_8_15_REG(7), REG_LIF, }, + + { "LIF_LLID_24", LIF_LLIDx_24_31_REG(0), REG_LIF, }, + { "LIF_LLID_25", LIF_LLIDx_24_31_REG(1), REG_LIF, }, + { "LIF_LLID_26", LIF_LLIDx_24_31_REG(2), REG_LIF, }, + { "LIF_LLID_27", LIF_LLIDx_24_31_REG(3), REG_LIF, }, + { "LIF_LLID_28", LIF_LLIDx_24_31_REG(4), REG_LIF, }, + { "LIF_LLID_29", LIF_LLIDx_24_31_REG(5), REG_LIF, }, + { "LIF_LLID_30", LIF_LLIDx_24_31_REG(6), REG_LIF, }, + { "LIF_LLID_31", LIF_LLIDx_24_31_REG(7), REG_LIF, }, + + { "LIF_VLAN_TYPE", LIF_VLAN_TYPE_REG , REG_LIF, }, + { "LIF_P2P_AE_SCI_EN", LIF_P2P_AE_SCI_EN_REG , REG_LIF, }, + + { "LIF_P2P_AE_SCI_LO_0", LIF_P2P_AE_SCI_LOx_REG(0) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_0", LIF_P2P_AE_SCI_HIx_REG(0) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_1", LIF_P2P_AE_SCI_LOx_REG(1) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_1", LIF_P2P_AE_SCI_HIx_REG(1) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_2", LIF_P2P_AE_SCI_LOx_REG(2) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_2", LIF_P2P_AE_SCI_HIx_REG(2) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_3", LIF_P2P_AE_SCI_LOx_REG(3) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_3", LIF_P2P_AE_SCI_HIx_REG(3) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_4", LIF_P2P_AE_SCI_LOx_REG(4) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_4", LIF_P2P_AE_SCI_HIx_REG(4) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_5", LIF_P2P_AE_SCI_LOx_REG(5) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_5", LIF_P2P_AE_SCI_HIx_REG(5) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_6", LIF_P2P_AE_SCI_LOx_REG(6) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_6", LIF_P2P_AE_SCI_HIx_REG(6) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_7", LIF_P2P_AE_SCI_LOx_REG(7) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_7", LIF_P2P_AE_SCI_HIx_REG(7) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_8", LIF_P2P_AE_SCI_LOx_REG(8) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_8", LIF_P2P_AE_SCI_HIx_REG(8) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_9", LIF_P2P_AE_SCI_LOx_REG(9) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_9", LIF_P2P_AE_SCI_HIx_REG(9) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_10", LIF_P2P_AE_SCI_LOx_REG(10) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_10", LIF_P2P_AE_SCI_HIx_REG(10) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_11", LIF_P2P_AE_SCI_LOx_REG(11) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_11", LIF_P2P_AE_SCI_HIx_REG(11) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_12", LIF_P2P_AE_SCI_LOx_REG(12) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_12", LIF_P2P_AE_SCI_HIx_REG(12) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_13", LIF_P2P_AE_SCI_LOx_REG(13) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_13", LIF_P2P_AE_SCI_HIx_REG(13) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_14", LIF_P2P_AE_SCI_LOx_REG(14) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_14", LIF_P2P_AE_SCI_HIx_REG(14) , REG_LIF, }, + { "LIF_P2P_AE_SCI_LO_15", LIF_P2P_AE_SCI_LOx_REG(15) , REG_LIF, }, + { "LIF_P2P_AE_SCI_HI_15", LIF_P2P_AE_SCI_HIx_REG(15) , REG_LIF, }, + + { "LIF_SEC_UP_KEY_STAT_1", LIF_SEC_UP_KEY_STAT_1_REG , REG_LIF, }, + { "LIF_SEC_KEY_SEL_1", LIF_SEC_KEY_SEL_1_REG , REG_LIF, }, + { "LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL", LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_REG , REG_LIF, }, + { "LIF_P2P_AUTONEG_CONTROL", LIF_P2P_AUTONEG_CONTROL_REG , REG_LIF, }, + { "LIF_P2P_AUTONEG_STATUS", LIF_P2P_AUTONEG_STATUS_REG , REG_LIF, }, + + /* + * XIF + */ + { "XIF_CTL", XIF_CTL_REG, REG_XIF, }, + { "XIF_INT_STATUS", XIF_INT_STATUS_REG, REG_XIF, }, + { "XIF_INT_MASK", XIF_INT_MASK_REG, REG_XIF, }, + { "XIF_PORT_DATA_REG_0", XIF_PORT_DATA_REG(0), REG_XIF, }, + { "XIF_PORT_DATA_REG_1", XIF_PORT_DATA_REG(1), REG_XIF, }, + { "XIF_PORT_DATA_REG_2", XIF_PORT_DATA_REG(2), REG_XIF, }, + { "XIF_PORT_DATA_REG_3", XIF_PORT_DATA_REG(3), REG_XIF, }, + { "XIF_PORT_DATA_REG_4", XIF_PORT_DATA_REG(4), REG_XIF, }, + { "XIF_PORT_DATA_REG_5", XIF_PORT_DATA_REG(5), REG_XIF, }, + { "XIF_PORT_DATA_REG_6", XIF_PORT_DATA_REG(6), REG_XIF, }, + { "XIF_PORT_DATA_REG_7", XIF_PORT_DATA_REG(7), REG_XIF, }, + { "XIF_MACSEC", XIF_MACSEC_REG, REG_XIF, }, + { "XIF_XPN_XMT_OFFSET", XIF_XPN_XMT_OFFSET_REG, REG_XIF, }, + { "XIF_XPN_TIMESTAMP_OFFSET", XIF_XPN_TIMESTAMP_OFFSET_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_CTL", XIF_XPN_PKTGEN_CTL_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_LLID", XIF_XPN_PKTGEN_LLID_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_PKT_CNT", XIF_XPN_PKTGEN_PKT_CNT_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_PKT_SIZE", XIF_XPN_PKTGEN_PKT_SIZE_REG, REG_XIF, }, + { "XIF_XPN_PKTGEN_IPG", XIF_XPN_PKTGEN_IPG_REG, REG_XIF, }, + { "XIF_TS_JITTER_THRESH", XIF_TS_JITTER_THRESH_REG, REG_XIF, }, + { "XIF_TS_UPDATE", XIF_TS_UPDATE_REG, REG_XIF, }, + { "XIF_GNT_OVERHEAD", XIF_GNT_OVERHEAD_REG, REG_XIF, }, + { "XIF_DISCOVER_OVERHEAD", XIF_DISCOVER_OVERHEAD_REG, REG_XIF, }, + { "XIF_DISCOVER_INFO", XIF_DISCOVER_INFO_REG, REG_XIF, }, + { "XIF_XPN_OVERSIZE_THRESH", XIF_XPN_OVERSIZE_THRESH_REG, REG_XIF, }, + { "XIF_SECRX_KEYNUM", XIF_SECRX_KEYNUM_REG, REG_XIF, }, + { "XIF_SECRX_ENCRYPT", XIF_SECRX_ENCRYPT_REG, REG_XIF, }, + { "XIF_PMC_FRAME_RX_CNT", XIF_PMC_FRAME_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_BYTE_RX_CNT", XIF_PMC_BYTE_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_RUNT_RX_CNT", XIF_PMC_RUNT_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_CW_ERR_RX_CNT", XIF_PMC_CW_ERR_RX_CNT_REG, REG_XIF, }, + { "XIF_PMC_CRC8_ERR_RX_CNT", XIF_PMC_CRC8_ERR_RX_CNT_REG, REG_XIF, }, + { "XIF_XPN_DATA_FRM_CNT", XIF_XPN_DATA_FRM_CNT_REG, REG_XIF, }, + { "XIF_XPN_DATA_BYTE_CNT", XIF_XPN_DATA_BYTE_CNT_REG, REG_XIF, }, + { "XIF_XPN_MPCP_FRM_CNT", XIF_XPN_MPCP_FRM_CNT_REG, REG_XIF, }, + { "XIF_XPN_OAM_FRM_CNT", XIF_XPN_OAM_FRM_CNT_REG, REG_XIF, }, + { "XIF_XPN_OAM_BYTE_CNT", XIF_XPN_OAM_BYTE_CNT_REG, REG_XIF, }, + { "XIF_XPN_OVERSIZE_FRM_CNT", XIF_XPN_OVERSIZE_FRM_CNT_REG, REG_XIF, }, + { "XIF_SEC_ABORT_FRM_CNT", XIF_SEC_ABORT_FRM_CNT_REG, REG_XIF, }, + { "XIF_PMC_TX_NEG_EVENT_CNT", XIF_PMC_TX_NEG_EVENT_CNT_REG, REG_XIF, }, + { "XIF_XPN_IDLE_PKT_CNT", XIF_XPN_IDLE_PKT_CNT_REG, REG_XIF, }, + { "XIF_MAX_MPCP_UPDATE", XIF_MAX_MPCP_UPDATE_REG, REG_XIF, }, + { "XIF_IPG_INSERTION", XIF_IPG_INSERTION_REG, REG_XIF, }, + { "XIF_TRANSPORT_TIME", XIF_TRANSPORT_TIME_REG, REG_XIF, }, + { "XIF_MPCP_TIME", XIF_MPCP_TIME_REG, REG_XIF, }, + { "XIF_OVERLAP_GNT_OH", XIF_OVERLAP_GNT_OH_REG, REG_XIF, }, + { "XIF_MAC_MODE", XIF_MAC_MODE_REG, REG_XIF, }, + { "XIF_PMCTX_CTL", XIF_PMCTX_CTL_REG, REG_XIF, }, + { "XIF_SEC_CTL", XIF_SEC_CTL_REG, REG_XIF, }, + { "XIF_AE_PKTNUM_WINDOW", XIF_AE_PKTNUM_WINDOW_REG, REG_XIF, }, + { "XIF_AE_PKTNUM_THRESH", XIF_AE_PKTNUM_THRESH_REG, REG_XIF, }, + { "XIF_SECTX_KEYNUM", XIF_SECTX_KEYNUM_REG, REG_XIF, }, + { "XIF_SECTX_ENCRYPT", XIF_SECTX_ENCRYPT_REG, REG_XIF, }, + { "XIF_AE_PKTNUM_STAT", XIF_AE_PKTNUM_STAT_REG, REG_XIF, }, + { "XIF_MPCP_UPDATE", XIF_MPCP_UPDATE_REG, REG_XIF, }, + { "XIF_BURST_PRELAUNCH_OFFSET", XIF_BURST_PRELAUNCH_OFFSET_REG, REG_XIF, }, + { "XIF_VLAN_TYPE", XIF_VLAN_TYPE_REG, REG_XIF, }, + { "XIF_P2P_AE_SCI_EN", XIF_P2P_AE_SCI_EN_REG, REG_XIF, }, + { "XIF_SECTX_KEYNUM_1", XIF_SECTX_KEYNUM_1_REG, REG_XIF, }, + { "XIF_SECRX_KEYNUM_1", XIF_SECRX_KEYNUM_1_REG, REG_XIF, }, +}; + +/* + * regs dump functions + */ +static void *regs_dump_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos < ARRAY_SIZE(epon_regs)) ? pos : NULL; +} + +static void *regs_dump_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return (++(*pos) < ARRAY_SIZE(epon_regs)) ? pos : NULL; +} + +static void regs_dump_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int regs_dump_seq_show(struct seq_file *s, void *v) +{ + struct xport_epon_priv *mode = s->private; + const struct reg_desc *rdesc; + int i = *(loff_t *)v; + u32 val; + + rdesc = &epon_regs[i]; + switch (rdesc->type) { + case REG_EPN: + val = epon_epn_reg_readl(mode, rdesc->offset); + break; + case REG_LIF: + val = epon_lif_reg_readl(mode, rdesc->offset); + break; + case REG_XIF: + val = epon_xif_reg_readl(mode, rdesc->offset); + break; + default: + BUG(); + break; + } + + seq_printf(s, "%-40s\t0x%08x\n", + rdesc->name, val); + + return 0; +} + +static const struct seq_operations regs_dump_seq_ops = { + .start = regs_dump_seq_start, + .next = regs_dump_seq_next, + .stop = regs_dump_seq_stop, + .show = regs_dump_seq_show, +}; + +static int regs_dump_open(struct inode *inode, struct file *filep) +{ + struct xport_epon_priv *mode = inode->i_private; + int ret; + + ret = seq_open(filep, ®s_dump_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = mode; + return 0; +} + +static const struct file_operations regs_dump_fops = { + .owner = THIS_MODULE, + .open = regs_dump_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +void mode_epon_dbg_init(struct xport_epon_priv *mode) +{ + char name[32]; + + snprintf(name, sizeof(name), "epon_regs"); + mode->regs_dbg = debugfs_create_file(name, 0400, + bcm63158_dbg_root, + mode, + ®s_dump_fops); + +} + +void mode_epon_dbg_release(struct xport_epon_priv *mode) +{ + if (mode->regs_dbg) + debugfs_remove(mode->regs_dbg); +} diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_epon.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_epon.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,489 @@ +#ifndef PORT_XPORT_EPON_H_ +#define PORT_XPORT_EPON_H_ + +#include + +#include "port_xport.h" + +#include "regs/epon_epon_top.h" +#include "regs/epon_epn.h" +#include "regs/epon_epn_onu_mac_addr.h" +#include "regs/epon_epn_tx_l1s_shp.h" +#include "regs/epon_epon_top.h" +#include "regs/epon_lif.h" +#include "regs/epon_nco_addr.h" +#include "regs/epon_xif.h" +#include "regs/epon_xpcsrx.h" +#include "regs/epon_xpcstx.h" + +/* + * EPON definitions + */ +#define BROADCAST_LLID_1G 0x7fff +#define BROADCAST_LLID_10G 0x7ffe + +#define NSEC_TO_TQ(x) ((x) / 16) +#define USEC_TO_TQ(x) (((x) * 1000) / 16) +#define TQ_TO_NSEC(x) ((x) * 16) +#define BYTES_TO_TQ_1G(x) ((x) / 2) +#define PREAMBLE_LEN_BYTES 8 +#define IPG_BYTES_1G 12 + +/* default laser on/off time per specification */ +#define DEF_LASER_ON_TIME 32 +#define DEF_LASER_OFF_TIME 32 + +/* + * MPCP protocol + */ +enum { + MPCP_OPCODE_PAUSE = 1, + MPCP_OPCODE_GATE = 2, + MPCP_OPCODE_REPORT = 3, + MPCP_OPCODE_REGISTER_REQ = 4, + MPCP_OPCODE_REGISTER = 5, + MPCP_OPCODE_REGISTER_ACK = 6, +}; + +struct mpcp_hdr { + __be16 opcode; + __be32 timestamp; +} __packed; + +struct mpcp_grant_hdr { + __be32 start_time; + __be16 len; +} __packed; + +struct mpcp_gate { + u8 nb_grants_flags; + struct mpcp_grant_hdr grants[0]; +} __packed; + +#define MPCP_GATE_F_IS_DISC (1 << 3) + +struct mpcp_disc_gate { + u8 nb_grants_flags; + __be32 start_time; + __be16 length; + __be16 sync_time; +} __packed; + +enum { + MPCP_DISCINFO_1G_CAP = (1 << 0), + MPCP_DISCINFO_10G_CAP = (1 << 1), + + MPCP_DISCINFO_1G_WINDOW = (1 << 4), + MPCP_DISCINFO_10G_WINDOW = (1 << 5), +}; + +struct mpcp_disc_gate10g { + u8 nb_grants_flags; + __be32 start_time; + __be16 length; + __be16 sync_time; + __be16 disc_info; +} __packed; + +enum { + MPCP_REGREQ_F_REGISTER = 1, + MPCP_REGREQ_F_DEREGISTER = 3, +}; + +struct mpcp_register_req { + u8 flags; + u8 pending_grants; + /* remaining fields only in 10G, but since framed is zero + * padded, it does not matter if they are present or not, a 1G + * OLT won't make a difference between those and padding */ + __be16 disc_info; + u8 laser_on; + u8 laser_off; +} __packed; + + +enum { + MPCP_REG_F_REREGISTER = 1, + MPCP_REG_F_DEREGISTER = 2, + MPCP_REG_F_ACK = 3, + MPCP_REG_F_NACK = 4, +}; + +struct mpcp_register { + __be16 assigned_port; + u8 flags; + __be16 sync_time; + u8 echoed_pending_grants; +} __packed; + +struct mpcp_register10g { + __be16 assigned_port; + u8 flags; + __be16 sync_time; + u8 echoed_pending_grants; + u8 target_laser_on; + u8 target_laser_off; +} __packed; + + +enum { + MPCP_REGACK_F_NACK = 0, + MPCP_REGACK_F_ACK = 1, +}; + +struct mpcp_register_ack { + u8 flags; + __be16 echoed_assigned_port; + __be16 echoed_sync_time; +} __packed; + + +/* + * eponmac MIB + */ +struct eponmac_mib { + /* + * XPCS RX + */ + u64 xpcs_rx_framer_misbrst; + u64 xpcs_rx_framer_bd_err; + u64 xpcs_rx_64b66b_ipg_det; + u64 xpcs_rx_fec_nque_in; + u64 xpcs_rx_fec_nque_out; + u64 xpcs_rx_idle_start; + u64 xpcs_rx_idle_stop; + u64 xpcs_rx_fec_cw_fail; + u64 xpcs_rx_fec_cw_tot; + u64 xpcs_rx_fec_correct; + u64 xpcs_rx_fec_ones_cor; + u64 xpcs_rx_fec_zeros_cor; + u64 xpcs_rx_64b66b_fail; + u64 xpcs_rx_frmr_bad_sh; + u64 xpcs_rx_psudo; + u64 xpcs_rx_prbs; + u64 xpcs_rx_64b66b_start; + u64 xpcs_rx_idle_good_pkt; + u64 xpcs_rx_idle_err_pkt; + u64 xpcs_rx_64b66b_stop; + + /* + * XIF + */ + u64 xif_pmc_frame_rx; + u64 xif_pmc_byte_rx; + u64 xif_pmc_runt_rx; + u64 xif_pmc_cw_err_rx; + u64 xif_pmc_crc8_err_rx; + u64 xif_xpn_data_frm; + u64 xif_xpn_data_byte; + u64 xif_xpn_mpcp_frm; + u64 xif_xpn_oam_frm; + u64 xif_xpn_oam_byte; + u64 xif_xpn_oversize_frm; + u64 xif_sec_abort_frm; + u64 xif_pmc_tx_neg_event; + u64 xif_xpn_idle_pkt; + + /* + * LIF + */ + u64 lif_rx_line_code_err_cnt; + u64 lif_rx_agg_mpcp_frm; + u64 lif_rx_agg_good_frm; + u64 lif_rx_agg_good_byte; + u64 lif_rx_agg_undersz_frm; + u64 lif_rx_agg_oversz_frm; + u64 lif_rx_agg_crc8_frm; + u64 lif_rx_agg_fec_frm; + u64 lif_rx_agg_fec_byte; + u64 lif_rx_agg_fec_exc_err_frm; + u64 lif_rx_agg_nonfec_good_frm; + u64 lif_rx_agg_nonfec_good_byte; + u64 lif_rx_agg_err_bytes; + u64 lif_rx_agg_err_zeroes; + u64 lif_rx_agg_no_err_blks; + u64 lif_rx_agg_cor_blks; + u64 lif_rx_agg_uncor_blks; + u64 lif_rx_agg_err_ones; + u64 lif_rx_agg_err_frm; + u64 lif_tx_pkt_cnt; + u64 lif_tx_byte_cnt; + u64 lif_tx_non_fec_pkt_cnt; + u64 lif_tx_non_fec_byte_cnt; + u64 lif_tx_fec_pkt_cnt; + u64 lif_tx_fec_byte_cnt; + u64 lif_tx_fec_blk_cnt; + u64 lif_tx_mpcp_pkt_cnt; + + /* + * EPN RAM + */ + u64 epn00_rx_bytes; + u64 epn00_rx_fcs; + u64 epn00_rx_oam; + u64 epn00_rx_gate; + u64 epn00_rx_64; + u64 epn00_rx_65_127; + u64 epn00_rx_128_255; + u64 epn00_rx_256_511; + u64 epn00_rx_512_1023; + u64 epn00_rx_1024_1518; + u64 epn00_rx_1519_2047; + u64 epn00_rx_2048_4095; + u64 epn00_rx_4096_9216; + u64 epn00_rx_gt_9216; + u64 epn00_rx_oversize; + u64 epn00_rx_bcast; + u64 epn00_rx_mcast; + u64 epn00_rx_unicast; + u64 epn00_rx_undersized; + u64 epn00_rx_oam_bytes; + u64 epn00_rx_register; + u64 epn00_tx_bytes; + u64 epn00_tx_oam; + u64 epn00_tx_report; + u64 epn00_tx_64; + u64 epn00_tx_65_127; + u64 epn00_tx_128_255; + u64 epn00_tx_256_511; + u64 epn00_tx_512_1023; + u64 epn00_tx_1024_1518; + u64 epn00_tx_1519_2047; + u64 epn00_tx_2048_4095; + u64 epn00_tx_4096_9216; + u64 epn00_tx_gt_9216; + u64 epn00_tx_oam_bytes; + u64 epn00_tx_bcast; + u64 epn00_tx_mcast; + u64 epn00_tx_unicast; + + /* only used for mcast/bcast */ + u64 epn24_rx_bytes; + u64 epn24_rx_fcs; + u64 epn24_rx_bcast; + u64 epn24_rx_mcast; + u64 epn25_rx_bytes; + u64 epn25_rx_fcs; + u64 epn25_rx_bcast; + u64 epn25_rx_mcast; + u64 epn26_rx_bytes; + u64 epn26_rx_fcs; + u64 epn26_rx_bcast; + u64 epn26_rx_mcast; + u64 epn27_rx_bytes; + u64 epn27_rx_fcs; + u64 epn27_rx_bcast; + u64 epn27_rx_mcast; + u64 epn28_rx_bytes; + u64 epn28_rx_fcs; + u64 epn28_rx_bcast; + u64 epn28_rx_mcast; + u64 epn29_rx_bytes; + u64 epn29_rx_fcs; + u64 epn29_rx_bcast; + u64 epn29_rx_mcast; + u64 epn30_rx_bytes; + u64 epn30_rx_fcs; + u64 epn30_rx_bcast; + u64 epn30_rx_mcast; + u64 epn31_rx_bytes; + u64 epn31_rx_fcs; + u64 epn31_rx_bcast; + u64 epn31_rx_mcast; + + /* + * EPN reg + */ + u64 epn00_l1_acc_bytes; + u64 epn00_unused_tq; + u64 epn_unmap_big; + u64 epn_unmap_frame; + u64 epn_unmap_fcs; + u64 epn_unmap_gate; + u64 epn_unmap_oam; + u64 epn_unmap_small; + + /* + * registration + */ + u64 reg_mpcp_rx; + u64 reg_mpcp_rx_invalid; + u64 reg_mpcp_rx_unk_opcode; + u64 reg_mpcp_rx_disc; + u64 reg_mpcp_rx_disc_info_mismatch; + u64 reg_mpcp_rx_disc_late; + u64 reg_mpcp_rx_disc_last_slot; + u64 reg_mpcp_rx_reg_for_other; + u64 reg_mpcp_rx_reg_unk_flag; + u64 reg_mpcp_rx_reg_dereg; + u64 reg_mpcp_rx_reg_nack; + u64 reg_mpcp_rx_reg_timeout; + u64 reg_mpcp_rx_other_err; + u64 reg_mpcp_tx_reg_req; + u64 reg_mpcp_tx_reg_ack; + u64 reg_fsm_state; +}; + +struct epon_link { + unsigned int idx; + unsigned int llid; + bool rx_enabled; + bool tx_enabled; + struct list_head next; +}; + +struct epon_reg_config { + unsigned int laser_on_time; + unsigned int laser_off_time; + + bool valid_sync_time; + unsigned int sync_time; + + u16 assigned_llid; +}; + +struct epon_user_config { + u32 burst_cap; + bool down_enc_enabled; + u8 key_sci[8]; + u8 down_key0[16]; + u8 down_key1[16]; +}; + +/* + * global link status (PCS + time sync) + */ +enum epon_global_link_state { + EPON_GLINK_DOWN, + EPON_GLINK_UP, + EPON_GLINK_FAILED, +}; + +enum epon_registration_state { + EPON_REG_WAIT_DISCOVERY, + EPON_REG_WAIT_REGISTER, + EPON_REG_COMPLETE, + EPON_REG_FAILED, +}; + +struct xport_epon_priv { + struct xport_priv *port; + struct dentry *regs_dbg; + struct eponmac_mib mib; + struct workqueue_struct *epon_wq; + struct packet_type reg_tap; + + /* + * pon configuration, cannot be changed while epon is started + */ + u8 mac_addr[6]; + bool laser_active_hi; + + /* + * link list, empty when epon is not started + */ + struct mutex links_lock; + struct list_head links_list; + u32 links_free; + u32 links_mcast; + + struct mutex epon_lock; + bool epon_started; + unsigned int epon_reset_duration_ms; + + /* + * current epon state + */ + unsigned int down_speed; + unsigned int up_speed; + u32 start_count; + struct epon_link *user_link; + struct epon_link *bcast_link; + struct delayed_work glob_link_work; + enum epon_global_link_state glob_link_state; + enum epon_registration_state reg_state; + unsigned long reg_state_last_change; + struct epon_reg_config reg_cfg; + struct epon_user_config user_cfg; +}; + +/* + * io accessors + */ +static inline u32 epon_top_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + EPON_TOP_OFFSET_0 + offset); +} + +static inline void epon_top_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + + EPON_TOP_OFFSET_0 + offset); +} + +static inline u32 epon_epn_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + EPN_OFFSET_0 + offset); +} + +static inline void epon_epn_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + EPN_OFFSET_0 + offset); +} + +static inline u32 epon_xif_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + XIF_OFFSET_0 + offset); +} + +static inline void epon_xif_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + XIF_OFFSET_0 + offset); +} + +static inline u32 epon_lif_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + LIF_OFFSET_0 + offset); +} + +static inline void epon_lif_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + LIF_OFFSET_0 + offset); +} + +static inline u32 epon_xpcsrx_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + XPCSRX_OFFSET_0 + offset); +} + +static inline void epon_xpcsrx_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + XPCSRX_OFFSET_0 + offset); +} + +static inline u32 epon_xpcstx_reg_readl(struct xport_epon_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[3] + XPCSTX_OFFSET_0 + offset); +} + +static inline void epon_xpcstx_reg_writel(struct xport_epon_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[3] + XPCSTX_OFFSET_0 + offset); +} + +void mode_epon_dbg_init(struct xport_epon_priv *mode); +void mode_epon_dbg_release(struct xport_epon_priv *mode); + +#endif /* PORT_XPORT_EPON_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport.h 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,102 @@ +#ifndef PORT_XPORT_H_ +#define PORT_XPORT_H_ + +#include "bcm63158_enet_runner.h" +#include +#include + +struct xport_priv { + struct bcm_enet_runner_priv *priv; + + void __iomem *regs[4]; + u32 regs_size[4]; + struct reset_control *wan_ae_rst; + u32 ae_bbh_id; + u32 pon_bbh_id; + + bool lbe_force; + bool lbe_force_value; +}; + +/* + * serdes utils + */ +struct serdes_params { + u32 misc3_if_select; + u32 misc3_laser_mode; + + u32 tx_pll_vco_div4; + u32 tx_pll_vco_div2; + u32 rx_pll_vco_div4; + u32 rx_pll_vco_div2; + u32 rx_pll_id; + u32 tx_pll_id; + + u32 tx_pll_force_kvh_bw; + u32 rx_pll_force_kvh_bw; + u32 tx_pll_kvh_force; + u32 rx_pll_kvh_force; + + u32 tx_pll_2rx_bw; + u32 rx_pll_2rx_bw; + + u32 rx_pll_fracn_div; + u32 rx_pll_fracn_ndiv; + + u32 tx_pll_fracn_div; + u32 tx_pll_fracn_ndiv; + + u32 tx_pll_fracn_sel; + u32 rx_pll_fracn_sel; + + u32 rx_pll_ditheren; + u32 tx_pll_ditheren; + + u32 rx_pll_mode; + u32 tx_pll_mode; + + u32 rx_tx_rate_ratio; + + u32 rx_pon_mac_ctrl; + u32 tx_pon_mac_ctrl; + u32 tx_sync_e_ctrl; + + u32 rx_osr_mode; + u32 tx_osr_mode; + + bool do_rx_pi_spacing; + u32 clk90_offset; + u32 p1_offset; + + bool do_pll_charge_pump; + bool do_pll_charge_pump_10g; + bool do_vga_rf; + bool do_sigdetect; + bool do_ae; + u32 dsc_a_cdr_control_2; + + bool serdes_ae_full_rate; + bool serdes_ae_20b_width; +}; + +int xport_serdes_set_params(struct xport_priv *port, + const struct serdes_params *params); +int xport_serdes_pcs_read_reg(struct xport_priv *port, + u16 lane, u16 address); +int xport_serdes_pcs_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask); + +void xport_serdes_lbe_force_enable(struct xport_priv *port); + +void xport_serdes_lbe_force_disable(struct xport_priv *port); + +void xport_serdes_lbe_dont_force(struct xport_priv *port); + +void xport_serdes_lbe_get_forced_state(struct xport_priv *port, + bool *force, bool *forced_value); + +extern const struct bcm_enet_mode_ops xport_xlmac_mode_ops; +extern const struct bcm_enet_mode_ops xport_epon_mode_ops; + +#endif /* PORT_XPORT_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_serdes.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_serdes.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_serdes.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_serdes.c 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,1656 @@ +#include "port_xport.h" +#include "regs/wan_top.h" +#include "regs/serdes_regs.h" + +#undef DUMP_SERDES_IO + +#ifdef DUMP_SERDES_IO +struct reg_dump_desc { + const char *name; + unsigned int reg; + bool skip_dump; + bool skip_consec; +}; + +const struct reg_dump_desc wan_top_regs[] = { + { "SCRATCH_REG", + WAN_TOP_SCRATCH_REG, }, + { "RESET_REG", + WAN_TOP_RESET_REG, }, + { "GPON_GEARBOX_0_REG", + WAN_TOP_GPON_GEARBOX_0_REG, }, + { "GPON_PATTERN_CFG1_REG", + WAN_TOP_GPON_PATTERN_CFG1_REG, }, + { "GPON_PATTERN_CFG2_REG", + WAN_TOP_GPON_PATTERN_CFG2_REG, }, + { "GPON_GEARBOX_2_REG", + WAN_TOP_GPON_GEARBOX_2_REG, }, + { "EARLY_TXEN_TXEN_REG", + WAN_TOP_EARLY_TXEN_TXEN_REG, }, + { "RESCAL_AL_CFG_REG", + WAN_TOP_RESCAL_AL_CFG_REG, }, + { "RESCAL_STATUS_0_REG", + WAN_TOP_RESCAL_STATUS_0_REG, }, + { "RESCAL_STATUS_1_REG", + WAN_TOP_RESCAL_STATUS_1_REG, }, + { "MISC_0_REG", + WAN_TOP_MISC_0_REG, }, + { "MISC_1_REG", + WAN_TOP_MISC_1_REG, }, + { "MISC_2_REG", + WAN_TOP_MISC_2_REG, }, + { "MISC_3_REG", + WAN_TOP_MISC_3_REG, }, + { "MISC_4_REG", + WAN_TOP_MISC_4_REG, }, + { "SERDES_PLL_CTL_REG", + WAN_TOP_SERDES_PLL_CTL_REG, }, + { "SERDES_TEMP_CTL_REG", + WAN_TOP_SERDES_TEMP_CTL_REG, }, + { "SERDES_PRAM_CTL_REG", + WAN_TOP_SERDES_PRAM_CTL_REG, }, + { "SERDES_PRAM_CTL_2_REG", + WAN_TOP_SERDES_PRAM_CTL_2_REG, }, + { "SERDES_PRAM_CTL_3_REG", + WAN_TOP_SERDES_PRAM_CTL_3_REG, }, + { "PMI_LP_0_REG", + WAN_TOP_PMI_LP_0_REG, true }, + { "PMI_LP_1_REG", + WAN_TOP_PMI_LP_1_REG, true }, + { "PMI_LP_2_REG", + WAN_TOP_PMI_LP_2_REG, true }, + { "PMI_LP_3_REG", + WAN_TOP_PMI_LP_3_REG, true }, + { "PMI_LP_4_REG", + WAN_TOP_PMI_LP_4_REG, true }, + { "TOD_CONFIG_0_REG", + WAN_TOP_TOD_CONFIG_0_REG, }, + { "TOD_CONFIG_1_REG", + WAN_TOP_TOD_CONFIG_1_REG, }, + { "TOD_CONFIG_2_REG", + WAN_TOP_TOD_CONFIG_2_REG, }, + { "TOD_CONFIG_3_REG", + WAN_TOP_TOD_CONFIG_3_REG, }, + { "TOD_CONFIG_4_REG", + WAN_TOP_TOD_CONFIG_4_REG, }, + { "TOD_CONFIG_5_REG", + WAN_TOP_TOD_CONFIG_5_REG, }, + { "TOD_TS48_MSB_REG", + WAN_TOP_TOD_TS48_MSB_REG, }, + { "TOD_TS48_LSB_REG", + WAN_TOP_TOD_TS48_LSB_REG, }, + { "TOD_TS64_MSB_REG", + WAN_TOP_TOD_TS64_MSB_REG, }, + { "TOD_TS64_LSB_REG", + WAN_TOP_TOD_TS64_LSB_REG, }, + { "TOD_STATUS_0_REG", + WAN_TOP_TOD_STATUS_0_REG, }, + { "TOD_STATUS_1_REG", + WAN_TOP_TOD_STATUS_1_REG, }, + { "SERDES_STATUS_REG", + WAN_TOP_SERDES_STATUS_REG, }, + { "INT_STATUS_REG", + WAN_TOP_INT_STATUS_REG, }, + { "INT_MASK_REG", + WAN_TOP_INT_MASK_REG, }, + { "CLK_DEJITTER_SAMPLING_CTL_0_REG", + WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_REG, }, + { "CLK_DEJITTER_SAMPLING_CTL_1_REG", + WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_REG, }, + { "CLK_SAMPLE_COUNTER_REG", + WAN_TOP_CLK_SAMPLE_COUNTER_REG, }, + { "SYNCE_PLL_CONFIG_REG", + WAN_TOP_SYNCE_PLL_CONFIG_REG, }, + { "OSR_CONTROL_REG", + WAN_TOP_OSR_CONTROL_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_STATUS_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_REG, }, + { "GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_REG", + WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_REG, }, + { "AE_GEARBOX_CONTROL_0_REG", + WAN_TOP_AE_GEARBOX_CONTROL_0_REG, }, + { "VOLTAGE_REGULATOR_DIVIDER_IDER_REG", + WAN_TOP_VOLTAGE_REGULATOR_DIVIDER_IDER_REG, }, + { "CLOCK_SYNC_CONFIG_REG", + WAN_TOP_CLOCK_SYNC_CONFIG_REG, }, + { "AEPCS_IEEE_REGID_REG", + WAN_TOP_AEPCS_IEEE_REGID_REG, }, + { "FORCE_LBE_CONTROL_REG", + WAN_TOP_FORCE_LBE_CONTROL_REG, }, + { "NGPON_GEARBOX_RX_CTL_0_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_0_REG, }, + { "NGPON_GEARBOX_RX_CTL_1_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_1_REG, }, + { "NGPON_GEARBOX_RX_CTL_2_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_2_REG, }, + { "NGPON_GEARBOX_RX_CTL_3_REG", + WAN_TOP_NGPON_GEARBOX_RX_CTL_3_REG, }, + { "NGPON_GEARBOX_TX_CTL_REG", + WAN_TOP_NGPON_GEARBOX_TX_CTL_REG, }, + { "NGPON_GEARBOX_STATUS_REG", + WAN_TOP_NGPON_GEARBOX_STATUS_REG, }, + { "EPON_10G_GEARBOX_REG", + WAN_TOP_EPON_10G_GEARBOX_REG, }, +}; + +const struct reg_dump_desc serdes_regs[] = { + { "DSC_A_cdr_control_0", DSC_A_cdr_control_0 }, + { "DSC_A_cdr_control_1", DSC_A_cdr_control_1 }, + { "DSC_A_cdr_control_2", DSC_A_cdr_control_2 }, + { "DSC_A_rx_pi_control", DSC_A_rx_pi_control }, + { "DSC_A_cdr_status_integ_reg", DSC_A_cdr_status_integ_reg }, + { "DSC_A_cdr_status_phase_error", DSC_A_cdr_status_phase_error }, + { "DSC_A_rx_pi_cnt_bin_d", DSC_A_rx_pi_cnt_bin_d }, + { "DSC_A_rx_pi_cnt_bin_p", DSC_A_rx_pi_cnt_bin_p }, + { "DSC_A_rx_pi_cnt_bin_m", DSC_A_rx_pi_cnt_bin_m }, + { "DSC_A_rx_pi_diff_bin", DSC_A_rx_pi_diff_bin }, + { "DSC_A_trnsum_cntl_5", DSC_A_trnsum_cntl_5 }, + { "DSC_A_dsc_uc_ctrl", DSC_A_dsc_uc_ctrl }, + { "DSC_A_dsc_scratch", DSC_A_dsc_scratch }, + { "DSC_B_dsc_sm_ctrl_0", DSC_B_dsc_sm_ctrl_0 }, + { "DSC_B_dsc_sm_ctrl_1", DSC_B_dsc_sm_ctrl_1 }, + { "DSC_B_dsc_sm_ctrl_2", DSC_B_dsc_sm_ctrl_2 }, + { "DSC_B_dsc_sm_ctrl_3", DSC_B_dsc_sm_ctrl_3 }, + { "DSC_B_dsc_sm_ctrl_4", DSC_B_dsc_sm_ctrl_4 }, + { "DSC_B_dsc_sm_ctrl_5", DSC_B_dsc_sm_ctrl_5 }, + { "DSC_B_dsc_sm_ctrl_6", DSC_B_dsc_sm_ctrl_6 }, + { "DSC_B_dsc_sm_ctrl_7", DSC_B_dsc_sm_ctrl_7 }, + { "DSC_B_dsc_sm_ctrl_8", DSC_B_dsc_sm_ctrl_8 }, + { "DSC_B_dsc_sm_ctrl_9", DSC_B_dsc_sm_ctrl_9 }, + { "DSC_B_dsc_sm_status_dsc_lock", DSC_B_dsc_sm_status_dsc_lock }, + { "DSC_B_dsc_sm_status_dsc_state_one_hot", DSC_B_dsc_sm_status_dsc_state_one_hot }, + { "DSC_B_dsc_sm_status_dsc_state_eee_one_hot", DSC_B_dsc_sm_status_dsc_state_eee_one_hot }, + { "DSC_B_dsc_sm_status_restart", DSC_B_dsc_sm_status_restart }, + { "DSC_B_dsc_sm_status_dsc_state", DSC_B_dsc_sm_status_dsc_state }, + { "DSC_C_dfe_common_ctl", DSC_C_dfe_common_ctl }, + { "DSC_C_dfe_1_ctl", DSC_C_dfe_1_ctl }, + { "DSC_C_dfe_1_pat_ctl", DSC_C_dfe_1_pat_ctl }, + { "DSC_C_dfe_2_ctl", DSC_C_dfe_2_ctl }, + { "DSC_C_dfe_2_pat_ctl", DSC_C_dfe_2_pat_ctl }, + { "DSC_C_dfe_3_ctl", DSC_C_dfe_3_ctl }, + { "DSC_C_dfe_3_pat_ctl", DSC_C_dfe_3_pat_ctl }, + { "DSC_C_dfe_4_ctl", DSC_C_dfe_4_ctl }, + { "DSC_C_dfe_4_pat_ctl", DSC_C_dfe_4_pat_ctl }, + { "DSC_C_dfe_5_ctl", DSC_C_dfe_5_ctl }, + { "DSC_C_dfe_5_pat_ctl", DSC_C_dfe_5_pat_ctl }, + { "DSC_C_dfe_vga_override", DSC_C_dfe_vga_override }, + { "DSC_C_vga_ctl", DSC_C_vga_ctl }, + { "DSC_C_vga_pat_eyediag_ctl", DSC_C_vga_pat_eyediag_ctl }, + { "DSC_C_p1_frac_offs_ctl", DSC_C_p1_frac_offs_ctl }, + { "DSC_D_trnsum_ctl_1", DSC_D_trnsum_ctl_1 }, + { "DSC_D_trnsum_ctl_2", DSC_D_trnsum_ctl_2 }, + { "DSC_D_trnsum_ctl_3", DSC_D_trnsum_ctl_3 }, + { "DSC_D_trnsum_ctl_4", DSC_D_trnsum_ctl_4 }, + { "DSC_D_trnsum_sts_1", DSC_D_trnsum_sts_1 }, + { "DSC_D_trnsum_sts_2", DSC_D_trnsum_sts_2 }, + { "DSC_D_trnsum_sts_3", DSC_D_trnsum_sts_3 }, + { "DSC_D_trnsum_sts_4", DSC_D_trnsum_sts_4 }, + { "DSC_D_trnsum_sts_5", DSC_D_trnsum_sts_5 }, + { "DSC_D_trnsum_sts_6", DSC_D_trnsum_sts_6 }, + { "DSC_D_vga_p1eyediag_sts", DSC_D_vga_p1eyediag_sts }, + { "DSC_D_dfe_1_sts", DSC_D_dfe_1_sts }, + { "DSC_D_dfe_2_sts", DSC_D_dfe_2_sts }, + { "DSC_D_dfe_3_4_5_sts", DSC_D_dfe_3_4_5_sts }, + { "DSC_D_vga_tap_bin", DSC_D_vga_tap_bin }, + { "DSC_E_dsc_e_ctrl", DSC_E_dsc_e_ctrl }, + { "DSC_E_dsc_e_pf_ctrl", DSC_E_dsc_e_pf_ctrl }, + { "DSC_E_dsc_e_pf2_lowp_ctrl", DSC_E_dsc_e_pf2_lowp_ctrl }, + { "DSC_E_dsc_e_offset_adj_data_odd", DSC_E_dsc_e_offset_adj_data_odd }, + { "DSC_E_dsc_e_offset_adj_data_even", DSC_E_dsc_e_offset_adj_data_even }, + { "DSC_E_dsc_e_offset_adj_p1_odd", DSC_E_dsc_e_offset_adj_p1_odd }, + { "DSC_E_dsc_e_offset_adj_p1_even", DSC_E_dsc_e_offset_adj_p1_even }, + { "DSC_E_dsc_e_offset_adj_m1_odd", DSC_E_dsc_e_offset_adj_m1_odd }, + { "DSC_E_dsc_e_offset_adj_m1_even", DSC_E_dsc_e_offset_adj_m1_even }, + { "DSC_E_dsc_e_dc_offset", DSC_E_dsc_e_dc_offset }, + { "DSC_F_ONU10G_looptiming_ctrl_0", DSC_F_ONU10G_looptiming_ctrl_0 }, + { "TX_PI_LBE_tx_pi_control_0", TX_PI_LBE_tx_pi_control_0 }, + { "TX_PI_LBE_tx_pi_control_1", TX_PI_LBE_tx_pi_control_1 }, + { "TX_PI_LBE_tx_pi_control_2", TX_PI_LBE_tx_pi_control_2 }, + { "TX_PI_LBE_tx_pi_control_3", TX_PI_LBE_tx_pi_control_3 }, + { "TX_PI_LBE_tx_pi_control_4", TX_PI_LBE_tx_pi_control_4 }, + { "TX_PI_LBE_tx_pi_control_6", TX_PI_LBE_tx_pi_control_6 }, + { "TX_PI_LBE_tx_pi_status_0", TX_PI_LBE_tx_pi_status_0 }, + { "TX_PI_LBE_tx_pi_status_1", TX_PI_LBE_tx_pi_status_1 }, + { "TX_PI_LBE_tx_pi_status_2", TX_PI_LBE_tx_pi_status_2 }, + { "TX_PI_LBE_tx_pi_status_3", TX_PI_LBE_tx_pi_status_3 }, + { "TX_PI_LBE_tx_lbe_control_0", TX_PI_LBE_tx_lbe_control_0 }, + { "CKRST_CTRL_OSR_MODE_CONTROL", CKRST_CTRL_OSR_MODE_CONTROL }, + { "CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL", CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL }, + { "CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL", CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL }, + { "CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL", CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL }, + { "CKRST_CTRL_LANE_DEBUG_RESET_CONTROL", CKRST_CTRL_LANE_DEBUG_RESET_CONTROL }, + { "CKRST_CTRL_UC_ACK_LANE_CONTROL", CKRST_CTRL_UC_ACK_LANE_CONTROL }, + { "CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL", CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL }, + { "CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL", CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL }, + { "CKRST_CTRL_PMD_LANE_MODE_STATUS", CKRST_CTRL_PMD_LANE_MODE_STATUS }, + { "CKRST_CTRL_LANE_DP_RESET_STATE_STATUS", CKRST_CTRL_LANE_DP_RESET_STATE_STATUS }, + { "CKRST_CTRL_LN_MASK", CKRST_CTRL_LN_MASK }, + { "CKRST_CTRL_OSR_MODE_STATUS", CKRST_CTRL_OSR_MODE_STATUS }, + { "CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS", CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS }, + { "CKRST_CTRL_PLL_SELECT_CONTROL", CKRST_CTRL_PLL_SELECT_CONTROL }, + { "CKRST_CTRL_LN_S_RSTB_CONTROL", CKRST_CTRL_LN_S_RSTB_CONTROL }, + { "AMS_RX_RX_CONTROL_0", AMS_RX_RX_CONTROL_0 }, + { "AMS_RX_RX_CONTROL_1", AMS_RX_RX_CONTROL_1 }, + { "AMS_RX_RX_CONTROL_2", AMS_RX_RX_CONTROL_2 }, + { "AMS_RX_RX_CONTROL_3", AMS_RX_RX_CONTROL_3 }, + { "AMS_RX_RX_CONTROL_4", AMS_RX_RX_CONTROL_4 }, + { "AMS_RX_RX_INTCTRL", AMS_RX_RX_INTCTRL }, + { "AMS_RX_RX_STATUS", AMS_RX_RX_STATUS }, + { "AMS_TX_TX_CONTROL_0", AMS_TX_TX_CONTROL_0 }, + { "AMS_TX_TX_CONTROL_1", AMS_TX_TX_CONTROL_1 }, + { "AMS_TX_TX_CONTROL_2", AMS_TX_TX_CONTROL_2 }, + { "AMS_TX_TX_INTCTRL", AMS_TX_TX_INTCTRL }, + { "AMS_TX_TX_STATUS", AMS_TX_TX_STATUS }, + { "AMS_COM_PLL_CONTROL_0", AMS_COM_PLL_CONTROL_0 }, + { "AMS_COM_PLL_CONTROL_1", AMS_COM_PLL_CONTROL_1 }, + { "AMS_COM_PLL_CONTROL_2", AMS_COM_PLL_CONTROL_2 }, + { "AMS_COM_PLL_CONTROL_3", AMS_COM_PLL_CONTROL_3 }, + { "AMS_COM_PLL_CONTROL_4", AMS_COM_PLL_CONTROL_4 }, + { "AMS_COM_PLL_CONTROL_5", AMS_COM_PLL_CONTROL_5 }, + { "AMS_COM_PLL_CONTROL_6", AMS_COM_PLL_CONTROL_6 }, + { "AMS_COM_PLL_CONTROL_7", AMS_COM_PLL_CONTROL_7 }, + { "AMS_COM_PLL_CONTROL_8", AMS_COM_PLL_CONTROL_8 }, + { "AMS_COM_PLL_INTCTRL", AMS_COM_PLL_INTCTRL }, + { "AMS_COM_PLL_STATUS", AMS_COM_PLL_STATUS }, + { "SIGDET_SIGDET_CTRL_0", SIGDET_SIGDET_CTRL_0 }, + { "SIGDET_SIGDET_CTRL_1", SIGDET_SIGDET_CTRL_1 }, + { "SIGDET_SIGDET_CTRL_2", SIGDET_SIGDET_CTRL_2 }, + { "SIGDET_SIGDET_CTRL_3", SIGDET_SIGDET_CTRL_3 }, + { "SIGDET_SIGDET_STATUS_0", SIGDET_SIGDET_STATUS_0 }, + { "TLB_RX_prbs_chk_cnt_config", TLB_RX_prbs_chk_cnt_config }, + { "TLB_RX_prbs_chk_config", TLB_RX_prbs_chk_config }, + { "TLB_RX_dig_lpbk_config", TLB_RX_dig_lpbk_config }, + { "TLB_RX_tlb_rx_misc_config", TLB_RX_tlb_rx_misc_config }, + { "TLB_RX_prbs_chk_en_timer_control", TLB_RX_prbs_chk_en_timer_control }, + { "TLB_RX_dig_lpbk_pd_status", TLB_RX_dig_lpbk_pd_status }, + { "TLB_RX_prbs_chk_lock_status", TLB_RX_prbs_chk_lock_status }, + { "TLB_RX_prbs_chk_err_cnt_msb_status", TLB_RX_prbs_chk_err_cnt_msb_status }, + { "TLB_RX_prbs_chk_err_cnt_lsb_status", TLB_RX_prbs_chk_err_cnt_lsb_status }, + { "TLB_RX_pmd_rx_lock_status", TLB_RX_pmd_rx_lock_status }, + { "TLB_TX_patt_gen_config", TLB_TX_patt_gen_config }, + { "TLB_TX_prbs_gen_config", TLB_TX_prbs_gen_config }, + { "TLB_TX_rmt_lpbk_config", TLB_TX_rmt_lpbk_config }, + { "TLB_TX_tlb_tx_misc_config", TLB_TX_tlb_tx_misc_config }, + { "TLB_TX_tx_pi_loop_timing_config", TLB_TX_tx_pi_loop_timing_config }, + { "TLB_TX_rmt_lpbk_pd_status", TLB_TX_rmt_lpbk_pd_status }, + { "DIG_COM_REVID0", DIG_COM_REVID0 }, + { "DIG_COM_RESET_CONTROL_PMD", DIG_COM_RESET_CONTROL_PMD }, + { "DIG_COM_RESET_CONTROL_CORE_DP", DIG_COM_RESET_CONTROL_CORE_DP }, + { "DIG_COM_DEBUG_CONTROL", DIG_COM_DEBUG_CONTROL }, + { "DIG_COM_TOP_USER_CONTROL_0", DIG_COM_TOP_USER_CONTROL_0 }, + { "DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL", DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL }, + { "DIG_COM_RST_SEQ_TIMER_CONTROL", DIG_COM_RST_SEQ_TIMER_CONTROL }, + { "DIG_COM_CORE_DP_RESET_STATE_STATUS", DIG_COM_CORE_DP_RESET_STATE_STATUS }, + { "DIG_COM_REVID1", DIG_COM_REVID1 }, + { "DIG_COM_REVID2", DIG_COM_REVID2 }, + { "PATT_GEN_patt_gen_seq_0", PATT_GEN_patt_gen_seq_0 }, + { "PATT_GEN_patt_gen_seq_1", PATT_GEN_patt_gen_seq_1 }, + { "PATT_GEN_patt_gen_seq_2", PATT_GEN_patt_gen_seq_2 }, + { "PATT_GEN_patt_gen_seq_3", PATT_GEN_patt_gen_seq_3 }, + { "PATT_GEN_patt_gen_seq_4", PATT_GEN_patt_gen_seq_4 }, + { "PATT_GEN_patt_gen_seq_5", PATT_GEN_patt_gen_seq_5 }, + { "PATT_GEN_patt_gen_seq_6", PATT_GEN_patt_gen_seq_6 }, + { "PATT_GEN_patt_gen_seq_7", PATT_GEN_patt_gen_seq_7 }, + { "PATT_GEN_patt_gen_seq_8", PATT_GEN_patt_gen_seq_8 }, + { "PATT_GEN_patt_gen_seq_9", PATT_GEN_patt_gen_seq_9 }, + { "PATT_GEN_patt_gen_seq_10", PATT_GEN_patt_gen_seq_10 }, + { "PATT_GEN_patt_gen_seq_11", PATT_GEN_patt_gen_seq_11 }, + { "PATT_GEN_patt_gen_seq_12", PATT_GEN_patt_gen_seq_12 }, + { "PATT_GEN_patt_gen_seq_13", PATT_GEN_patt_gen_seq_13 }, + { "PATT_GEN_patt_gen_seq_14", PATT_GEN_patt_gen_seq_14 }, + { "TX_FED_txfir_control1", TX_FED_txfir_control1 }, + { "TX_FED_txfir_control2", TX_FED_txfir_control2 }, + { "TX_FED_txfir_control3", TX_FED_txfir_control3 }, + { "TX_FED_txfir_status1", TX_FED_txfir_status1 }, + { "TX_FED_txfir_status2", TX_FED_txfir_status2 }, + { "TX_FED_txfir_status3", TX_FED_txfir_status3 }, + { "TX_FED_txfir_status4", TX_FED_txfir_status4 }, + { "TX_FED_micro_control", TX_FED_micro_control }, + { "TX_FED_misc_control1", TX_FED_misc_control1 }, + { "TX_FED_txfir_control4", TX_FED_txfir_control4 }, + { "TX_FED_misc_status0", TX_FED_misc_status0 }, + { "PLL_CAL_COM_CTL_0", PLL_CAL_COM_CTL_0 }, + { "PLL_CAL_COM_CTL_1", PLL_CAL_COM_CTL_1 }, + { "PLL_CAL_COM_CTL_2", PLL_CAL_COM_CTL_2 }, + { "PLL_CAL_COM_CTL_3", PLL_CAL_COM_CTL_3 }, + { "PLL_CAL_COM_CTL_4", PLL_CAL_COM_CTL_4 }, + { "PLL_CAL_COM_CTL_5", PLL_CAL_COM_CTL_5 }, + { "PLL_CAL_COM_CTL_6", PLL_CAL_COM_CTL_6 }, + { "PLL_CAL_COM_CTL_7", PLL_CAL_COM_CTL_7 }, + { "PLL_CAL_COM_CTL_STATUS_0", PLL_CAL_COM_CTL_STATUS_0, false, false }, + { "PLL_CAL_COM_CTL_STATUS_1", PLL_CAL_COM_CTL_STATUS_1, false, false }, + { "TXCOM_CL72_tap_preset_control", TXCOM_CL72_tap_preset_control }, + { "TXCOM_CL72_debug_1_register", TXCOM_CL72_debug_1_register }, + { "CORE_PLL_COM_PMD_CORE_MODE_STATUS", CORE_PLL_COM_PMD_CORE_MODE_STATUS }, + { "CORE_PLL_COM_RESET_CONTROL_PLL_DP", CORE_PLL_COM_RESET_CONTROL_PLL_DP }, + { "CORE_PLL_COM_TOP_USER_CONTROL", CORE_PLL_COM_TOP_USER_CONTROL }, + { "CORE_PLL_COM_UC_ACK_CORE_CONTROL", CORE_PLL_COM_UC_ACK_CORE_CONTROL }, + { "CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS", CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS }, + { "CORE_PLL_COM_CORE_PLL_COM_STATUS_2", CORE_PLL_COM_CORE_PLL_COM_STATUS_2 }, + { "MICRO_A_ramword", MICRO_A_ramword }, + { "MICRO_A_address", MICRO_A_address }, + { "MICRO_A_command", MICRO_A_command }, + { "MICRO_A_ram_wrdata", MICRO_A_ram_wrdata }, + { "MICRO_A_ram_rddata", MICRO_A_ram_rddata }, + { "MICRO_A_download_status", MICRO_A_download_status }, + { "MICRO_A_sfr_status", MICRO_A_sfr_status }, + { "MICRO_A_mdio_uc_mailbox_msw", MICRO_A_mdio_uc_mailbox_msw }, + { "MICRO_A_mdio_uc_mailbox_lsw", MICRO_A_mdio_uc_mailbox_lsw }, + { "MICRO_A_uc_mdio_mailbox_lsw", MICRO_A_uc_mdio_mailbox_lsw }, + { "MICRO_A_command2", MICRO_A_command2 }, + { "MICRO_A_uc_mdio_mailbox_msw", MICRO_A_uc_mdio_mailbox_msw }, + { "MICRO_A_command3", MICRO_A_command3 }, + { "MICRO_A_command4", MICRO_A_command4 }, + { "MICRO_A_temperature_status", MICRO_A_temperature_status }, + { "MICRO_B_program_ram_control1", MICRO_B_program_ram_control1 }, + { "MICRO_B_dataram_control1", MICRO_B_dataram_control1 }, + { "MICRO_B_iram_control1", MICRO_B_iram_control1 }, + { "MDIO_MMDSEL_AER_COM_mdio_maskdata", MDIO_MMDSEL_AER_COM_mdio_maskdata }, + { "MDIO_MMDSEL_AER_COM_mdio_brcst_port_addr", MDIO_MMDSEL_AER_COM_mdio_brcst_port_addr }, + { "MDIO_MMDSEL_AER_COM_mdio_mmd_select", MDIO_MMDSEL_AER_COM_mdio_mmd_select }, + { "MDIO_MMDSEL_AER_COM_mdio_aer", MDIO_MMDSEL_AER_COM_mdio_aer }, + { "MDIO_BLK_ADDR_BLK_ADDR", MDIO_BLK_ADDR_BLK_ADDR }, +}; + +/* + * + */ +static const struct reg_dump_desc *find_wan_top_reg(unsigned int reg) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(wan_top_regs); i++) { + if (reg == wan_top_regs[i].reg) + return &wan_top_regs[i]; + } + return NULL; +} + +/* + * + */ +static const struct reg_dump_desc *find_serdes_reg(unsigned int reg) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(serdes_regs); i++) { + if (reg == serdes_regs[i].reg) + return &serdes_regs[i]; + } + return NULL; +} + +/* + * + */ +static void dump_wan_top_regs(struct xport_priv *port) +{ + size_t i; + for (i = 0; i < ARRAY_SIZE(wan_top_regs); i++) { + printk("%30s: %08x\n", + wan_top_regs[i].name, + wan_top_readl(port, wan_top_regs[i].reg)); + } +} +#endif + +/* + * + */ +static __maybe_unused const char *get_serdes_lane(unsigned int lane) +{ + static char buf[64]; + + buf[0] = 0; + if (lane & serdes_PLL_1) + strcat(buf, "PLL_1/"); + else + strcat(buf, "PLL_0/"); + + switch ((lane & LANE_BRDCST)) { + case LANE_0: + strcat(buf, "L0"); + break; + case LANE_1: + strcat(buf, "L1"); + break; + case LANE_2: + strcat(buf, "L2"); + break; + case LANE_3: + strcat(buf, "L3"); + break; + case LANE_BRDCST: + strcat(buf, "LBCAST"); + break; + default: + strcat(buf, "LUNKN"); + break; + } + return buf; +} + +/* + * + */ +static u32 __wan_top_readl(struct xport_priv *port, u32 reg) +{ + BUG_ON(reg >= port->regs_size[0]); + return readl(port->regs[0] + reg); +} + +/* + * + */ +static u32 wan_top_readl(struct xport_priv *port, u32 reg) +{ +#ifdef DUMP_SERDES_IO + const struct reg_dump_desc *d; +#endif + u32 val; + +#ifdef DUMP_SERDES_IO + d = find_wan_top_reg(reg); + BUG_ON(!d); +#endif + + BUG_ON(reg >= port->regs_size[0]); + val = readl(port->regs[0] + reg); +#ifdef DUMP_SERDES_IO + if (!d->skip_dump) + printk("wan_top_readl: %s => %x\n", d->name, val); +#endif + return val; +} + +/* + * + */ +static void wan_top_writel(struct xport_priv *port, u32 reg, u32 val) +{ + u32 reread; +#ifdef DUMP_SERDES_IO + u32 before; + const struct reg_dump_desc *d; +#endif + + BUG_ON(reg >= port->regs_size[0]); + +#ifdef DUMP_SERDES_IO + d = find_wan_top_reg(reg); + BUG_ON(!d); + before = __wan_top_readl(port, reg); +#endif + writel(val, port->regs[0] + reg); + +#ifdef DUMP_SERDES_IO + if (!d->skip_dump) + printk("wan_top_write: %s <= %x (prev %x)\n", + d->name, val, before); +#endif + + reread = __wan_top_readl(port, reg); + if (reread != val) + WARN(1, "failed to reread from reg:%u %08x != %08x\n", + reg, val, reread); +} + +/* + * + */ +static void wan_top_clear(struct xport_priv *port, u32 reg, u32 mask) +{ + u32 val; + + val = wan_top_readl(port, reg); + val &= ~mask; + wan_top_writel(port, reg, val); +} + +/* + * + */ +static void wan_top_set(struct xport_priv *port, u32 reg, u32 mask) +{ + u32 val; + + val = wan_top_readl(port, reg); + val |= mask; + wan_top_writel(port, reg, val); +} + +/* + * + */ +static int serdes_op_wait(struct xport_priv *port, + u32 status_reg, u32 *ret_val) +{ + size_t i; + + for (i = 0; i < 1000; i++) { + u32 val; + + val = wan_top_readl(port, status_reg); + if (!(val & WAN_TOP_PMI_LP_3_PMI_LP_ACK_MASK)) { + udelay(1); + continue; + } + + if (val & WAN_TOP_PMI_LP_3_PMI_LP_ERR_MASK) + return 2; + + *ret_val = val & WAN_TOP_PMI_LP_3_PMI_LP_RDDATA_MASK; + return 0; + } + + return 1; +} + +/* + * + */ +static int __serdes_read_reg(struct xport_priv *port, + u16 lane, u16 address, + bool is_misc, + bool no_dump) +{ + u32 val, status_reg; + int ret, wait_ret; +#ifdef DUMP_SERDES_IO + const struct reg_dump_desc *d; + static u32 last_reg; + + d = find_serdes_reg(address); + BUG_ON(!d); +#endif + + if (is_misc) + lane |= DEVID_1; + else + lane |= DEVID_0; + val = (lane << 16) | address; + wan_top_writel(port, WAN_TOP_PMI_LP_1_REG, val); + + if (is_misc) + val = WAN_TOP_PMI_LP_0_MISC_EN_MASK; + else + val = WAN_TOP_PMI_LP_0_PCS_EN_MASK; + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, val); + + if (is_misc) + status_reg = WAN_TOP_PMI_LP_3_REG; + else + status_reg = WAN_TOP_PMI_LP_4_REG; + + wait_ret = serdes_op_wait(port, status_reg, &ret); + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, 0); + udelay(5); + + if (wait_ret) { + /* FIXME */ + /* netdev_err(port->priv->netdev, */ + /* "serdes reg read failed: " */ + /* "ret:%d tgt:%s lane:%x address:%x\n", */ + /* wait_ret, */ + /* is_misc ? "misc" : "pcs", */ + /* lane, address); */ + return -1; + } + +#ifdef DUMP_SERDES_IO + if (!no_dump && !d->skip_dump) { + if (!d->skip_consec || + last_reg != ((lane << 16) | address)) { + /* printk("serdes_readl: %s %s <= %04x\n", */ + /* get_serdes_lane(lane), d->name, ret); */ + printk("serdes_readl: %04x@%04x <= %04x\n", + lane, address, ret); + } + last_reg = (lane << 16) | address; + } +#endif + + return ret; +} + +/* + * + */ +static int __serdes_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask, + bool is_misc) +{ + u32 val, status_reg; + u16 nmask = ~mask; + int ret, wait_ret; +#ifdef DUMP_SERDES_IO + const struct reg_dump_desc *d; + int old, reread; +#endif + + if (is_misc) + lane |= DEVID_1; + else + lane |= DEVID_0; + +#ifdef DUMP_SERDES_IO + d = find_serdes_reg(address); + BUG_ON(!d); + old = __serdes_read_reg(port, lane, address, is_misc, true); +#endif + + val = (lane << 16) | address; + wan_top_writel(port, WAN_TOP_PMI_LP_1_REG, val); + + val = (wrdata << WAN_TOP_PMI_LP_2_PMI_LP_WRDATA_SHIFT); + val |= (nmask << WAN_TOP_PMI_LP_2_PMI_LP_MASKDATA_SHIFT); + wan_top_writel(port, WAN_TOP_PMI_LP_2_REG, val); + + if (is_misc) + val = WAN_TOP_PMI_LP_0_MISC_EN_MASK; + else + val = WAN_TOP_PMI_LP_0_PCS_EN_MASK; + val |= WAN_TOP_PMI_LP_0_WRITE_MASK; + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, val); + udelay(5); + + if (is_misc) + status_reg = WAN_TOP_PMI_LP_3_REG; + else + status_reg = WAN_TOP_PMI_LP_4_REG; + + wait_ret = serdes_op_wait(port, status_reg, &ret); + wan_top_writel(port, WAN_TOP_PMI_LP_0_REG, 0); + udelay(5); + + if (wait_ret) { + netdev_err(port->priv->netdev, + "serdes reg write failed: ret:%d tgt:%s lane:%x " + "address:%x val/mask:%04x/%04x\n", + wait_ret, is_misc ? "misc" : "pcs", + lane, address, wrdata, mask); + return -1; + } + +#ifdef DUMP_SERDES_IO + reread = __serdes_read_reg(port, lane, address, is_misc, true); + if (!d->skip_dump) { + /* printk("serdes_write: %s %s <= %04x / %04x\n", */ + /* get_serdes_lane(lane), d->name, wrdata, mask); */ + printk("serdes_write: %04x@%04x (%04x/%04x): %04x -> %04x\n", + lane, address, wrdata, mask, old, reread); + } +#endif + return 0; +} + +/* + * + */ +static int serdes_misc_read_reg(struct xport_priv *port, + u16 lane, u16 address) +{ + return __serdes_read_reg(port, lane, address, true, false); +} + +/* + * + */ +static int serdes_misc_check_reg(struct xport_priv *port, + u16 lane, u16 address, u16 exp_value) +{ + int ret; + + ret = serdes_misc_read_reg(port, lane, address); + if (ret < 0) + return ret; + + if ((u16)ret != exp_value) { + WARN(1, "serdes check reg failed: address:%04x %04x != %08x\n", + address, ret, exp_value); + return -1; + } + return 0; +} + +/* + * + */ +static int serdes_misc_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask) +{ + return __serdes_write_reg(port, lane, address, wrdata, mask, true); +} + +/* + * + */ +static int serdes_misc_write_check_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask, + u16 exp_value) +{ + int ret; + + ret = __serdes_write_reg(port, lane, address, wrdata, mask, true); + if (ret < 0) + return ret; + return serdes_misc_check_reg(port, lane, address, exp_value); +} + +/* + * + */ +int xport_serdes_pcs_read_reg(struct xport_priv *port, + u16 lane, u16 address) +{ + return __serdes_read_reg(port, lane, address, false, false); +} + +/* + * + */ +int xport_serdes_pcs_write_reg(struct xport_priv *port, + u16 lane, u16 address, + u16 wrdata, u16 mask) +{ + return __serdes_write_reg(port, lane, address, wrdata, mask, false); +} + +/* + * + */ +static int serdes_poll_pll_lock(struct xport_priv *port, + unsigned int pll_id) +{ + int ret; + size_t i; + + for (i = 0; i < 1000; i++) { + ret = serdes_misc_read_reg(port, pll_id, + PLL_CAL_COM_CTL_STATUS_0); + if (ret < 0) + return 1; + + if (ret & 0x0100) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "PLL %d lock timeout\n", pll_id); + return 1; +} + +/* + * + */ +static int serdes_poll_dsc_lock(struct xport_priv *port) + +{ + int ret; + size_t i; + + for (i = 0; i < 10000; i++) { + ret = serdes_misc_read_reg(port, LANE_0, + DSC_B_dsc_sm_status_dsc_lock); + if (ret < 0) + return 1; + + if (ret & 0x1) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "DSC lock timeout\n"); + return 1; +} + +/* + * + */ +static int serdes_poll_pmd_rx_lock(struct xport_priv *port) + +{ + int ret; + size_t i; + + for (i = 0; i < 10000; i++) { + ret = serdes_misc_read_reg(port, LANE_0, + TLB_RX_pmd_rx_lock_status); + if (ret < 0) + return 1; + + if (ret & 0x1) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "PMD rx lock timeout\n"); + return 1; +} + +/* + * + */ +static int wan_top_poll_pll_lock(struct xport_priv *port, + unsigned int pll_id) +{ + u32 val; + size_t i; + + for (i = 0; i < 10000; i++) { + u32 mask; + + val = wan_top_readl(port, WAN_TOP_SERDES_STATUS_REG); + + if (pll_id == serdes_PLL_0) + mask = WAN_TOP_SERDES_STATUS_PMD_PLL0_LOCK_MASK; + else + mask = WAN_TOP_SERDES_STATUS_PMD_PLL1_LOCK_MASK; + + if (val & mask) + return 0; + + udelay(1); + } + + netdev_err(port->priv->netdev, "WAN TOP PLL %d lock timeout\n", + pll_id); + return 1; +} + +/* + * + */ +static void __serdes_lbe_op(struct xport_priv *port, + bool force, bool forced_value) +{ + u32 val; + + val = wan_top_readl(port, WAN_TOP_FORCE_LBE_CONTROL_REG); + + if (!force) { + val &= ~WAN_TOP_FORCE_LBE_CONTROL_OE_MASK; + val &= ~WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK; + val &= ~WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK; + val &= ~WAN_TOP_FORCE_LBE_CONTROL_MASK; + } else { + val |= WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK; + val |= WAN_TOP_FORCE_LBE_CONTROL_OE_MASK; + val |= WAN_TOP_FORCE_LBE_CONTROL_MASK; + + if (!forced_value) + val &= ~WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK; + else + val |= WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK; + } + + wan_top_writel(port, WAN_TOP_FORCE_LBE_CONTROL_REG, val); +} + +/* + * + */ +void xport_serdes_lbe_force_enable(struct xport_priv *port) +{ + __serdes_lbe_op(port, true, true); +} + +/* + * + */ +void xport_serdes_lbe_force_disable(struct xport_priv *port) +{ + __serdes_lbe_op(port, true, false); +} + +/* + * + */ +void xport_serdes_lbe_dont_force(struct xport_priv *port) +{ + __serdes_lbe_op(port, false, false); +} + +/* + * + */ +void xport_serdes_lbe_get_forced_state(struct xport_priv *port, + bool *force, bool *forced_value) +{ + u32 val; + + val = wan_top_readl(port, WAN_TOP_FORCE_LBE_CONTROL_REG); + *force = (val & WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK); + *forced_value = (val & WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK); +} + +/* + * + */ +static void set_clk90_offset(struct xport_priv *port, + uint8_t desired_m1_d_offset) +{ + u8 steps, count, d_location, now_m1_location, next_m1_location; + u16 rd_serdes; + + desired_m1_d_offset = desired_m1_d_offset % 64; + rd_serdes = serdes_misc_read_reg(port, LANE_0, DSC_A_rx_pi_cnt_bin_m); + now_m1_location = (rd_serdes & 0x7f); + d_location = (rd_serdes & 0x7f00) >> 8; + next_m1_location = d_location + desired_m1_d_offset; + + /* calculate number of movement steps and direction */ + if (next_m1_location >= now_m1_location) { + steps = next_m1_location - now_m1_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x4401, + 0x74ff); + } else { + steps = now_m1_location - next_m1_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x4001, + 0x74ff); + } + + /* move the Slicer(P) the required steps */ + for (count = 0; count < steps; count++) + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0200, + 0x0200); + + rd_serdes = serdes_misc_read_reg(port, LANE_0, DSC_A_rx_pi_cnt_bin_m); +#if 0 + d_location = (rd_serdes & 0x7f00) >> 8; + now_m1_location = (rd_serdes & 0x7f); + printk("0xd009 = 0x%04x\n", rd_serdes); + printk("d_location = %d\n", d_location); + printk("now_m1_location = %d\n", now_m1_location); + printk("Done Slicer-M1-Adjustment\n"); +#endif +} + +/* + * + */ +static void set_clkp1_offset(struct xport_priv *port, + u8 desired_p_d_offset) +{ + u8 step, count, d_location, now_p_location, next_p_location; + u16 rd_serdes; + + desired_p_d_offset = desired_p_d_offset % 64; + rd_serdes = serdes_misc_read_reg(port, LANE_0, + DSC_A_rx_pi_cnt_bin_d); + d_location = (rd_serdes & 0x7f); + now_p_location = (rd_serdes & 0x7f00) >> 8; + next_p_location = d_location + desired_p_d_offset; + + /* calculate number of movement steps and direction */ + if (next_p_location >= now_p_location) { + step = next_p_location - now_p_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x2401, + 0x74ff); + } else { + step = now_p_location - next_p_location; + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x2001, + 0x74ff); + } + + /* move the Slicer(P) the required steps */ + for (count = 0; count < step; count++) + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0200, + 0x0200); + + rd_serdes = serdes_misc_read_reg(port, LANE_0, DSC_A_rx_pi_cnt_bin_d); +#if 0 + d_location = (rd_serdes & 0x7f); + now_p_location = (rd_serdes & 0x7f00) >> 8; + printk("0xd007 = 0x%04x\n", rd_serdes); + printk("d_location = %d\n", d_location); + printk("now_p_location = %d\n", now_p_location); + printk("Done Slicer-P-Adjustment\n"); +#endif +} + +/* + * + */ +static void rx_pi_spacing(struct xport_priv *port, + u8 desired_m1_d_offset, + u8 desired_p_d_offset) +{ + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0800, + 0x0800); + set_clk90_offset(port, desired_m1_d_offset); + set_clkp1_offset(port, desired_p_d_offset); + serdes_misc_write_reg(port, LANE_0, + DSC_A_rx_pi_control, + 0x0000, + 0x7800); +} + +/* + * + */ +int xport_serdes_set_params(struct xport_priv *port, + const struct serdes_params *params) +{ + u32 val; + u16 wr_data, wr_mask; + +#if 0 + /* FIXME: from xgae driver only */ + /* assert & deassert all reset (from bcm code) */ + val = WAN_TOP_MISC_2_PMD_POR_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_1_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_0_DP_H_RSTB_MASK; + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); + wan_top_writel(port, WAN_TOP_MISC_2_REG, 0); + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); + udelay(10); +#endif + + /* + * init WAN TOP block + */ + + /* rescal reset */ + /* FIXME: first two lines from xgae driver only */ + /* val = WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_PWRDN_MASK; */ + /* wan_top_writel(port, WAN_TOP_RESCAL_AL_CFG_REG, val); */ + val = WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_RSTB_MASK; + wan_top_writel(port, WAN_TOP_RESCAL_AL_CFG_REG, val); + udelay(100); + val = wan_top_readl(port, WAN_TOP_RESCAL_STATUS_0_REG); + if (!(val & WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_DONE_MASK)) { + netdev_err(port->priv->netdev, "rescal status is not done\n"); + return 1; + } + if (!(val & WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_VALID_MASK)) { + netdev_err(port->priv->netdev, "rescal status is not valid\n"); + return 1; + } + + /* make sure we reset forced state of LBE */ + xport_serdes_lbe_dont_force(port); + + /* test scratch registers */ + wan_top_writel(port, WAN_TOP_SCRATCH_REG, 0x01234567); + wan_top_writel(port, WAN_TOP_SCRATCH_REG, 0x89abcdef); + + /* assert all resets */ + wan_top_writel(port, WAN_TOP_MISC_2_REG, 0); + udelay(5); + + /* reset all remaining registers (xgae driver) */ + wan_top_writel(port, WAN_TOP_MISC_0_REG, 0); + wan_top_writel(port, WAN_TOP_MISC_1_REG, 0); + wan_top_writel(port, WAN_TOP_MISC_2_REG, 0); + wan_top_writel(port, WAN_TOP_MISC_3_REG, 0); + wan_top_writel(port, WAN_TOP_SERDES_PLL_CTL_REG, 0); + wan_top_writel(port, WAN_TOP_SERDES_PRAM_CTL_REG, 0); + wan_top_writel(port, WAN_TOP_OSR_CONTROL_REG, 0); + udelay(5); + + /* set correct refclk (LCREF 50Mhz refclock) */ + val = WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_REFIN_EN_MASK | + WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_REFIN_EN_MASK | + WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_LCREF_SEL_MASK; + wan_top_writel(port, WAN_TOP_SERDES_PLL_CTL_REG, val); + + /* wait for clock to be stable */ + mdelay(10); + + /* de-assert resets */ + val = WAN_TOP_MISC_2_PMD_POR_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_1_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_DP_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_LN_H_RSTB_MASK | + WAN_TOP_MISC_2_PMD_CORE_0_DP_H_RSTB_MASK; + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); + + /* disable laser while we change config */ + wan_top_clear(port, WAN_TOP_MISC_3_REG, WAN_TOP_MISC_3_LASER_OE_MASK); + + /* set oversample mode */ + val = wan_top_readl(port, WAN_TOP_MISC_2_REG); + val &= ~WAN_TOP_MISC_2_PMD_RX_OSR_MODE_MASK; + val &= ~WAN_TOP_MISC_2_PMD_TX_OSR_MODE_MASK; + val |= params->rx_osr_mode << WAN_TOP_MISC_2_PMD_RX_OSR_MODE_SHIFT; + val |= params->tx_osr_mode << WAN_TOP_MISC_2_PMD_TX_OSR_MODE_SHIFT; + /* FIXME: this is AE_25 in PON driver, dunno what it is*/ +// val |= (1 << 24); + wan_top_writel(port, WAN_TOP_MISC_2_REG, val); + + /* set correct interface */ + val = wan_top_readl(port, WAN_TOP_MISC_3_REG); + val |= params->misc3_if_select << WAN_TOP_MISC_3_WAN_IFSELECT_SHIFT; + val |= params->misc3_laser_mode << WAN_TOP_MISC_3_LASER_MODE_SHIFT; + wan_top_writel(port, WAN_TOP_MISC_3_REG, val); + + /* set epon gearbox configuration */ + if (!params->do_ae) { + val = wan_top_readl(port, WAN_TOP_EPON_10G_GEARBOX_REG); + val |= WAN_TOP_EPON_10G_GEARBOX_RX_CGEN_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_TX_CGEN_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_RX_GBOX_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_TX_GBOX_RSTN_MASK; + val |= WAN_TOP_EPON_10G_GEARBOX_CLK_EN_MASK; + wan_top_writel(port, WAN_TOP_EPON_10G_GEARBOX_REG, val); + udelay(10); + } + + /* set OSR gearbox */ + val = wan_top_readl(port, WAN_TOP_OSR_CONTROL_REG); + val &= ~WAN_TOP_OSR_CFG_GPON_RX_CLK_MASK; + val |= (2 << WAN_TOP_OSR_CFG_GPON_RX_CLK_SHIFT); + wan_top_writel(port, WAN_TOP_OSR_CONTROL_REG, val); + + /* + * now init serdes + */ + + /* sanity check */ + serdes_misc_write_check_reg(port, LANE_BRDCST, DIG_COM_REVID0, + 0x0000, 0xffff, 0x42e5); + serdes_misc_write_check_reg(port, LANE_BRDCST, DIG_COM_REVID1, + 0x0000, 0xffff, 0x1034); + serdes_misc_write_check_reg(port, LANE_BRDCST, DIG_COM_REVID2, + 0x0000, 0xffff, 0x0000); + serdes_misc_write_check_reg(port, LANE_BRDCST, + MDIO_MMDSEL_AER_COM_mdio_maskdata, + 0x0000, 0xffff, 0x0000); + serdes_misc_write_check_reg(port, LANE_BRDCST, + MDIO_MMDSEL_AER_COM_mdio_maskdata, + 0xaaaa, 0xffff, 0xaaaa); + serdes_misc_write_check_reg(port, LANE_BRDCST, + MDIO_MMDSEL_AER_COM_mdio_maskdata, + 0x5555, 0xffff, 0x5555); + + /* make sure PLL0 is used for tx and PLL1 for rx in dual pll + * mode */ + BUG_ON(params->tx_pll_id > params->rx_pll_id); + BUG_ON(params->tx_pll_id == params->rx_pll_id && + params->tx_pll_id != serdes_PLL_0); + + /* power up needed PLL */ + serdes_misc_write_reg(port, LANE_0 | params->tx_pll_id, + AMS_COM_PLL_INTCTRL, + 0, + (1 << 2)); + + if (params->rx_pll_id != params->tx_pll_id) { + serdes_misc_write_reg(port, LANE_0 | params->rx_pll_id, + AMS_COM_PLL_INTCTRL, + 0, + (1 << 2)); + } else { + /* make sure second pll is disabled */ + serdes_misc_write_reg(port, LANE_0 | serdes_PLL_1, + AMS_COM_PLL_INTCTRL, + (1 << 2), + (1 << 2)); + } + + /* select PLL for tx clock (0 => PLL0, 1 => PLL1) */ + serdes_misc_write_reg(port, LANE_BRDCST, + CKRST_CTRL_PLL_SELECT_CONTROL, + (params->tx_pll_id == serdes_PLL_1) ? (1 << 0) : 0, + (1 << 0)); + + /* select PLL for rx clock (0 => PLL0, 1 => PLL1) */ + serdes_misc_write_reg(port, LANE_BRDCST, + CKRST_CTRL_PLL_SELECT_CONTROL, + (params->rx_pll_id == serdes_PLL_1) ? (1 << 1) : 0, + (1 << 1)); + + // TX AMS_COM_PLL_CONTROL_1 + wr_data = (((params->tx_pll_vco_div4 << 7) & (0x0001 << 7)) | + ((params->tx_pll_vco_div2 << 6) & (0x0001 << 6))); + wr_mask = (0x0001 << 7) | + (0x0001 << 6); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_1, + wr_data, + wr_mask); + + // TX AMS_COM_PLL_CONTROL_4 + wr_data = (((params->tx_pll_force_kvh_bw << 14) & (0x0001 << 14)) | + ((params->tx_pll_kvh_force << 12) & (0x0003 << 12)) | + ((params->tx_pll_2rx_bw << 8) & (0x0003 << 8))); + wr_mask = (0x0001 << 14) | + (0x0003 << 12) | + (0x0003 << 8); + serdes_misc_write_reg(port, + params->tx_pll_id, + AMS_COM_PLL_CONTROL_4, + wr_data, + wr_mask); + + // TX AMS_COM_PLL_CONTROL_7 + wr_data = (((params->tx_pll_fracn_div & 0xffff) << 0) & (0xffff << 0)); + wr_mask = (0xffff << 0); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_7, + wr_data, + wr_mask); + + // TX AMS_COM_PLL_CONTROL_8 + wr_data = (((params->tx_pll_fracn_sel << 15) & (0x0001 << 15)) | + ((params->tx_pll_ditheren << 14) & (0x0001 << 14)) | + ((params->tx_pll_fracn_ndiv << 4) & (0x03ff << 4)) | + ((((params->tx_pll_fracn_div & 0x30000) >> 16) << 0) & (0x0003 << 0))); + wr_mask = (0x0001 << 15) | + (0x0001 << 14) | + (0x03ff << 4) | + (0x0003 << 0); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_8, + wr_data, + wr_mask); + + // TX PLL_CAL_COM_CTL_7 + wr_data = ((params->tx_pll_mode << 0) & (0x000f << 0)); + wr_mask = (0x000f << 0); + serdes_misc_write_reg(port, params->tx_pll_id, + PLL_CAL_COM_CTL_7, + wr_data, + wr_mask); + + if (params->rx_pll_id != params->tx_pll_id) { + // RX AMS_COM_PLL_CONTROL_1 + wr_data = (((params->rx_pll_vco_div4 << 7) & (0x0001 << 7)) | + ((params->rx_pll_vco_div2 << 6) & (0x0001 << 6))); + wr_mask = (0x0001 << 7) | + (0x0001 << 6); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_1, + wr_data, + wr_mask); + + // RX AMS_COM_PLL_CONTROL_4 + wr_data = (((params->rx_pll_force_kvh_bw << 14) & (0x0001 << 14)) | + ((params->rx_pll_kvh_force << 12) & (0x0003 << 12)) | + ((params->rx_pll_2rx_bw << 8) & (0x0003 << 8))); + wr_mask = (0x0001 << 14) | + (0x0003 << 12) | + (0x0003 << 8); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_4, + wr_data, + wr_mask); + + // RX AMS_COM_PLL_CONTROL_7 + wr_data = (((params->rx_pll_fracn_div & 0xffff) << 0) & (0xffff << 0)); + wr_mask = (0xffff << 0); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_7, + wr_data, + wr_mask); + + // RX AMS_COM_PLL_CONTROL_8 + wr_data = (((params->rx_pll_fracn_sel << 15) & (0x0001 << 15)) | + ((params->rx_pll_ditheren << 14) & (0x0001 << 14)) | + ((params->rx_pll_fracn_ndiv << 4) & (0x03ff << 4)) | + ((((params->rx_pll_fracn_div & 0x30000) >> 16) << 0) & (0x0003 << 0))); + wr_mask = (0x0001 << 15) | + (0x0001 << 14) | + (0x03ff << 4) | + (0x0003 << 0); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_8, + wr_data, + wr_mask); + + // RX PLL_CAL_COM_CTL_7 + wr_data = ((params->rx_pll_mode << 0) & (0x000f << 0)); + wr_mask = (0x000f << 0); + serdes_misc_write_reg(port, params->rx_pll_id, + PLL_CAL_COM_CTL_7, + wr_data, + wr_mask); + } + + if (params->do_pll_charge_pump) { + /* from PON driver only */ + // pll_iqp [04:01] = 0x5 = default + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x000a, 0x001e); + } + + if (params->do_pll_charge_pump_10g) { + /* from PON driver only */ + // 0xD0B2[bit0]=en_HRz<1> =1, 0xD0B0[bit11]=en_HRz<0>=1 -->>> en_HRz = 6[kOhm] + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0001, + 0x0001); + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_0, + 0x0800, + 0x0800); + + if (params->rx_pll_id != params->tx_pll_id) { + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0001, + 0x0001); + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_0, + 0x0800, + 0x0800); + } + + // set PLL-Current-ChargePump=ipq[bit4:1]= 0x0 -->>> 50[uA] + serdes_misc_write_reg(port, params->tx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0000, + 0x001e); + + if (params->rx_pll_id != params->tx_pll_id) { + serdes_misc_write_reg(port, params->rx_pll_id, + AMS_COM_PLL_CONTROL_2, + 0x0000, + 0x001e); + } + } + + /* from PON driver only */ + //* #Looptiming Control + //#(*) DSC_F_ONU10G_looptiming_ctrl_0. + // RX line rate to TX line rate ratio + // 000: 1 to 1 001: 1.25 to 1 010: 2 to 1 + // 011: 4 to 1 100: 5 to 1 101: 8.25 to 1 + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_F_ONU10G_looptiming_ctrl_0, + params->rx_tx_rate_ratio, + 0x0007); + + /* from PON driver only */ + //#(5.a) RX=OS4 and TX=OS8 // address 0xD080 = 16'hc074 + // # OSR Mode Value: 0= OSx1, 1=OSx2, 4=OSX4, 7=OSX8, A =OSx16 (revB0) + // # rx_osr_mode_frc = 1 + // # rx_osr_mode_frc_val = mode dependent + // # tx_osr_mode_frc = 1 + // # tx_osr_mode_frc_val = mode dependent + wr_data = (((params->tx_osr_mode << 4) | (0x0001 << 15)) | + (params->rx_osr_mode | (0x0001 << 14))); + serdes_misc_write_reg(port, serdes_PLL_0, + CKRST_CTRL_OSR_MODE_CONTROL, + wr_data, + 0xffff); + + /* from PON driver, value different in xgae and init is done + * later */ + /* #(*) TX Phase Interpolator Control 0 (0xD070) */ + serdes_misc_write_reg(port, LANE_BRDCST, + TX_PI_LBE_tx_pi_control_0, + 0x2003, /* 0x2000 in xgae driver */ + 0xffff); + + /* + * CDR programming + */ + // cdr_freq_en=1, cdr_integ_sat_sel=0, cdr_freq_override_en=0, cdr_phase_sat_ctrl=1 + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_A_cdr_control_0, + 0x0005, + 0x7ff7); + + /* Configure DSC_A_cdr_control_2 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_A_cdr_control_2, + params->dsc_a_cdr_control_2, + 0x1ff3); + + /* Configure DSC_B_dsc_sm_ctrl_7 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_B_dsc_sm_ctrl_7, + 0x0000, + 0xffff); + + /* Configure DSC_A_cdr_control_1 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_A_cdr_control_1, + 0x0690, + 0xffff); + + /*Configure DSC_B_dsc_sm_ctrl_8 */ + serdes_misc_write_reg(port, LANE_BRDCST, + DSC_B_dsc_sm_ctrl_8, + 0x0010, + 0xcfff); + + /* from PON driver only */ + if (params->do_vga_rf) { + // (*) Analog = VGA, and PF programming + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_E_dsc_e_pf_ctrl, + 0x0007, + 0x000F); // _set_rx_pf_main(7); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_E_dsc_e_pf2_lowp_ctrl, + 0x0003, + 0x0007); // _set_rx_pf2(3); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_C_dfe_vga_override, + 0x0000, + 0x3E00); // _set_rx_vga(32); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_C_dfe_vga_override, + 0x0100, + 0x01FF); + + serdes_misc_write_reg(port, serdes_PLL_0, + DSC_C_dfe_vga_override, + 0x8000, + 0x8000); + } + + /* + * (#11) RX-&-TX PON_MAC_CLK Division Control and SYNC_E_CLK + */ + // TX AMS_TX_TX_CONTROL_1 [ 0xD0A1 ] + wr_data = (((params->tx_pon_mac_ctrl << 4) & (0x0007 << 4)) | + ((params->tx_sync_e_ctrl << 1) & (0x0007 << 1))); + wr_mask = (0x0007 << 4) | + (0x0007 << 1); + serdes_misc_write_reg(port, LANE_BRDCST, + AMS_TX_TX_CONTROL_1, + wr_data, + wr_mask); + + // TX AMS_RX_RX_CONTROL_2 [ 0xD092 ] + wr_data = (((params->rx_pon_mac_ctrl << 0) & (0x0007 << 0))); + wr_mask = (0x0007 << 0); + serdes_misc_write_reg(port, LANE_BRDCST, + AMS_RX_RX_CONTROL_2, + wr_data, + wr_mask); + + /* + * Enable PLL's. De-assert core_dp_s_rstb --> will start the + * PLL calibration. + * + */ + + /* afe_s_pll_pwrdn=1, core_dp_s_rs=0 */ + serdes_misc_write_reg(port, params->tx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x4000, + 0x6000); + if (params->tx_pll_id != params->rx_pll_id) + serdes_misc_write_reg(port, params->rx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x4000, + 0x6000); + udelay(1); + + /* afe_s_pll_pwrdn=0, core_dp_s_rs=1 */ + serdes_misc_write_reg(port, params->tx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x2000, + 0x6000); + if (params->tx_pll_id != params->rx_pll_id) + serdes_misc_write_reg(port, params->rx_pll_id, + CORE_PLL_COM_TOP_USER_CONTROL, + 0x2000, + 0x6000); + + /* poll for PLL lock */ + if (serdes_poll_pll_lock(port, params->tx_pll_id)) + return 1; + + if (params->tx_pll_id != params->rx_pll_id) { + if (serdes_poll_pll_lock(port, params->rx_pll_id)) + return 1; + } + + /* also poll for PLL lock in wan top block */ + if (wan_top_poll_pll_lock(port, params->tx_pll_id)) + return 1; + + if (params->tx_pll_id != params->rx_pll_id) { + if (wan_top_poll_pll_lock(port, params->rx_pll_id)) + return 1; + } + + /* + * #(11) De-assert ln_dp_s_rstb + */ + + /* note: LANE_BRDCST in xgae driver only */ + // ln_dp_s_rstb = 1 = serdes data-path out of reset (0xd081) + serdes_misc_write_reg(port, LANE_BRDCST, + CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL, + 0x0002, + 0x0002); + + /* note: LANE_BRDCST in xgae driver only */ + serdes_misc_write_reg(port, LANE_BRDCST, + AMS_TX_TX_CONTROL_0, + 0x0000, + 0x00c0); + + /* + * xgae driver configures sigdetect, pon driver disable it + */ + if (params->do_sigdetect) { + serdes_misc_write_reg(port, LANE_0, + DSC_B_dsc_sm_ctrl_0, + 0x0008, + 0xffff); + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_3, + 0x0023, + 0xffff); + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_1, + 0xa00a, + 0); + } else { + /* Ignore SigDetect: 0xd010[09] = ignore_sigdet =1 */ + serdes_misc_write_reg(port, LANE_0, + DSC_B_dsc_sm_ctrl_0, + 0x0200, + 0x0200); + + // 0xD0C1 bits 6, 5 and 0 + // energy_detect_frc_val -> 1 + // energy_detect_frc -> 1 + // afe_signal_detect_dis -> 1 + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_1, + 0x0061, + 0x0061); + + + // 0xD0C2 bits 0-2 and 4-6: + // los_thresh -> 0 + // signal_detect_thresh -> 0 + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_2, + 0x0000, + 0x0077); + + // 0xD0C3 bits 6-7: + // analog_sd_override -> 1 + serdes_misc_write_reg(port, LANE_0, + SIGDET_SIGDET_CTRL_3, + 0x0040, + 0x00C0); + } + + /* check DSC lock */ + if (serdes_poll_dsc_lock(port)) + return 1; + + /* check PMD rx lock */ + if (serdes_poll_pmd_rx_lock(port)) + return 1; + + // (*) PLL PPM Adjustment for RX=10G modes + /* FIXME, only done in PON driver and 10G_10G mode, which is + * not yet implemented here */ + + /* Adjust RX PI intial location */ + if (params->do_rx_pi_spacing) + rx_pi_spacing(port, params->clk90_offset, params->p1_offset); + + /* set AE 10G gearbox */ + val = 0; + if (params->serdes_ae_full_rate) + val |= WAN_TOP_AE_GEARBOX_CONTROL_0_CR_FULL_RATE_MODE_MASK; + if (params->serdes_ae_20b_width) + val |= WAN_TOP_AE_GEARBOX_CONTROL_0_CR_WIDTH_MODE_MASK; + wan_top_writel(port, WAN_TOP_AE_GEARBOX_CONTROL_0_REG, val); + + /* reset WAN AE */ + if (params->do_ae) + reset_control_reset(port->wan_ae_rst); + + /* reset WAN TOP pcs */ + wan_top_clear(port, WAN_TOP_RESET_REG, WAN_TOP_RESET_CFG_PCS_RESET_N_MASK); + msleep(10); + wan_top_set(port, WAN_TOP_RESET_REG, WAN_TOP_RESET_CFG_PCS_RESET_N_MASK); + msleep(1); + + if (!params->do_ae) { + /* FIXME: bcm pon driver has early TX config for pon + * 1G and optics BCM_I2C_PON_OPTICS_TYPE_PMD, which + * does not seem to apply to us */ + } + + /* enable laser now that config is done */ + wan_top_set(port, WAN_TOP_MISC_3_REG, WAN_TOP_MISC_3_LASER_OE_MASK); + + return 0; +} diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.c 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,1036 @@ +#include "port_xport_xlmac.h" +#include "regs/serdes_regs.h" + +#define GEN_MIB_STAT(m) \ + sizeof(((struct xlmac_mib *)0)->m), \ + offsetof(struct xlmac_mib, m) + +const struct bcm_runner_ethtool_stat xlmac_mib_estat[] = { + { "rx_64", GEN_MIB_STAT(rx_64), XPORT_MIB_CORE_GRX64_REG, }, + { "rx_127", GEN_MIB_STAT(rx_127), XPORT_MIB_CORE_GRX127_REG, }, + { "rx_255", GEN_MIB_STAT(rx_255), XPORT_MIB_CORE_GRX255_REG, }, + { "rx_511", GEN_MIB_STAT(rx_511), XPORT_MIB_CORE_GRX511_REG, }, + { "rx_1023", GEN_MIB_STAT(rx_1023), XPORT_MIB_CORE_GRX1023_REG, }, + { "rx_1518", GEN_MIB_STAT(rx_1518), XPORT_MIB_CORE_GRX1518_REG, }, + { "rx_1522", GEN_MIB_STAT(rx_1522), XPORT_MIB_CORE_GRX1522_REG, }, + { "rx_2047", GEN_MIB_STAT(rx_2047), XPORT_MIB_CORE_GRX2047_REG, }, + { "rx_4095", GEN_MIB_STAT(rx_4095), XPORT_MIB_CORE_GRX4095_REG, }, + { "rx_9216", GEN_MIB_STAT(rx_9216), XPORT_MIB_CORE_GRX9216_REG, }, + { "rx_16383", GEN_MIB_STAT(rx_16383), XPORT_MIB_CORE_GRX16383_REG, }, + { "rx_all_pkt", GEN_MIB_STAT(rx_pkt), XPORT_MIB_CORE_GRXPKT_REG, }, + { "rx_unicast", GEN_MIB_STAT(rx_uca), XPORT_MIB_CORE_GRXUCA_REG, }, + { "rx_multicast", GEN_MIB_STAT(rx_mca), XPORT_MIB_CORE_GRXMCA_REG, }, + { "rx_bcast", GEN_MIB_STAT(rx_bca), XPORT_MIB_CORE_GRXBCA_REG, }, + { "rx_fcs", GEN_MIB_STAT(rx_fcs), XPORT_MIB_CORE_GRXFCS_REG, }, + { "rx_control", GEN_MIB_STAT(rx_cf), XPORT_MIB_CORE_GRXCF_REG, }, + { "rx_pause", GEN_MIB_STAT(rx_pf), XPORT_MIB_CORE_GRXPF_REG, }, + { "rx_pfc", GEN_MIB_STAT(rx_pp), XPORT_MIB_CORE_GRXPP_REG, }, + { "rx_unsupp_opcode", GEN_MIB_STAT(rx_uo), XPORT_MIB_CORE_GRXUO_REG, }, + { "rx_unsupp_da", GEN_MIB_STAT(rx_uda), XPORT_MIB_CORE_GRXUDA_REG, }, + { "rx_wrong_sa", GEN_MIB_STAT(rx_wsa), XPORT_MIB_CORE_GRXWSA_REG, }, + { "rx_align", GEN_MIB_STAT(rx_aln), XPORT_MIB_CORE_GRXALN_REG, }, + { "rx_length", GEN_MIB_STAT(rx_flr), XPORT_MIB_CORE_GRXFLR_REG, }, + { "rx_code_err", GEN_MIB_STAT(rx_frerr), XPORT_MIB_CORE_GRXFRERR_REG, }, + { "rx_false_carrier", GEN_MIB_STAT(rx_fcr), XPORT_MIB_CORE_GRXFCR_REG, }, + { "rx_oversize", GEN_MIB_STAT(rx_ovr), XPORT_MIB_CORE_GRXOVR_REG, }, + { "rx_jabber", GEN_MIB_STAT(rx_jbr), XPORT_MIB_CORE_GRXJBR_REG, }, + { "rx_bad_mtu", GEN_MIB_STAT(rx_mtue), XPORT_MIB_CORE_GRXMTUE_REG, }, + { "rx_matched_crc", GEN_MIB_STAT(rx_mcrc), XPORT_MIB_CORE_GRXMCRC_REG, }, + { "rx_promisc", GEN_MIB_STAT(rx_prm), XPORT_MIB_CORE_GRXPRM_REG, }, + { "rx_vlan", GEN_MIB_STAT(rx_vln), XPORT_MIB_CORE_GRXVLN_REG, }, + { "rx_dvlan", GEN_MIB_STAT(rx_dvln), XPORT_MIB_CORE_GRXDVLN_REG, }, + { "rx_trunc", GEN_MIB_STAT(rx_trfu), XPORT_MIB_CORE_GRXTRFU_REG, }, + { "rx_good", GEN_MIB_STAT(rx_pok), XPORT_MIB_CORE_GRXPOK_REG, }, + { "rx_pfcoff0", GEN_MIB_STAT(rx_pfcoff0), XPORT_MIB_CORE_GRXPFCOFF0_REG, }, + { "rx_pfcoff1", GEN_MIB_STAT(rx_pfcoff1), XPORT_MIB_CORE_GRXPFCOFF1_REG, }, + { "rx_pfcoff2", GEN_MIB_STAT(rx_pfcoff2), XPORT_MIB_CORE_GRXPFCOFF2_REG, }, + { "rx_pfcoff3", GEN_MIB_STAT(rx_pfcoff3), XPORT_MIB_CORE_GRXPFCOFF3_REG, }, + { "rx_pfcoff4", GEN_MIB_STAT(rx_pfcoff4), XPORT_MIB_CORE_GRXPFCOFF4_REG, }, + { "rx_pfcoff5", GEN_MIB_STAT(rx_pfcoff5), XPORT_MIB_CORE_GRXPFCOFF5_REG, }, + { "rx_pfcoff6", GEN_MIB_STAT(rx_pfcoff6), XPORT_MIB_CORE_GRXPFCOFF6_REG, }, + { "rx_pfcoff7", GEN_MIB_STAT(rx_pfcoff7), XPORT_MIB_CORE_GRXPFCOFF7_REG, }, + { "rx_pfcp0", GEN_MIB_STAT(rx_pfcp0), XPORT_MIB_CORE_GRXPFCP0_REG, }, + { "rx_pfcp1", GEN_MIB_STAT(rx_pfcp1), XPORT_MIB_CORE_GRXPFCP1_REG, }, + { "rx_pfcp2", GEN_MIB_STAT(rx_pfcp2), XPORT_MIB_CORE_GRXPFCP2_REG, }, + { "rx_pfcp3", GEN_MIB_STAT(rx_pfcp3), XPORT_MIB_CORE_GRXPFCP3_REG, }, + { "rx_pfcp4", GEN_MIB_STAT(rx_pfcp4), XPORT_MIB_CORE_GRXPFCP4_REG, }, + { "rx_pfcp5", GEN_MIB_STAT(rx_pfcp5), XPORT_MIB_CORE_GRXPFCP5_REG, }, + { "rx_pfcp6", GEN_MIB_STAT(rx_pfcp6), XPORT_MIB_CORE_GRXPFCP6_REG, }, + { "rx_pfcp7", GEN_MIB_STAT(rx_pfcp7), XPORT_MIB_CORE_GRXPFCP7_REG, }, + { "rx_schcrc", GEN_MIB_STAT(rx_schcrc), XPORT_MIB_CORE_GRXSCHCRC_REG, }, + { "rx_bytes", GEN_MIB_STAT(rx_byt), XPORT_MIB_CORE_GRXBYT_REG, }, + { "rx_runt", GEN_MIB_STAT(rx_rpkt), XPORT_MIB_CORE_GRXRPKT_REG, }, + { "rx_undersize", GEN_MIB_STAT(rx_und), XPORT_MIB_CORE_GRXUND_REG, }, + { "rx_frag", GEN_MIB_STAT(rx_frg), XPORT_MIB_CORE_GRXFRG_REG, }, + { "rx_runt_bytes", GEN_MIB_STAT(rx_rbyt), XPORT_MIB_CORE_GRXRBYT_REG, }, + { "tx_64", GEN_MIB_STAT(tx_64), XPORT_MIB_CORE_GTX64_REG, }, + { "tx_127", GEN_MIB_STAT(tx_127), XPORT_MIB_CORE_GTX127_REG, }, + { "tx_255", GEN_MIB_STAT(tx_255), XPORT_MIB_CORE_GTX255_REG, }, + { "tx_511", GEN_MIB_STAT(tx_511), XPORT_MIB_CORE_GTX511_REG, }, + { "tx_1023", GEN_MIB_STAT(tx_1023), XPORT_MIB_CORE_GTX1023_REG, }, + { "tx_1518", GEN_MIB_STAT(tx_1518), XPORT_MIB_CORE_GTX1518_REG, }, + { "tx_1522", GEN_MIB_STAT(tx_1522), XPORT_MIB_CORE_GTX1522_REG, }, + { "tx_2047", GEN_MIB_STAT(tx_2047), XPORT_MIB_CORE_GTX2047_REG, }, + { "tx_4095", GEN_MIB_STAT(tx_4095), XPORT_MIB_CORE_GTX4095_REG, }, + { "tx_9216", GEN_MIB_STAT(tx_9216), XPORT_MIB_CORE_GTX9216_REG, }, + { "tx_16383", GEN_MIB_STAT(tx_16383), XPORT_MIB_CORE_GTX16383_REG, }, + { "tx_good", GEN_MIB_STAT(tx_pok), XPORT_MIB_CORE_GTXPOK_REG, }, + { "tx_all_pkt", GEN_MIB_STAT(tx_pkt), XPORT_MIB_CORE_GTXPKT_REG, }, + { "tx_unicast", GEN_MIB_STAT(tx_uca), XPORT_MIB_CORE_GTXUCA_REG, }, + { "tx_multicast", GEN_MIB_STAT(tx_mca), XPORT_MIB_CORE_GTXMCA_REG, }, + { "tx_bcast", GEN_MIB_STAT(tx_bca), XPORT_MIB_CORE_GTXBCA_REG, }, + { "tx_pause", GEN_MIB_STAT(tx_pf), XPORT_MIB_CORE_GTXPF_REG, }, + { "tx_pfc", GEN_MIB_STAT(tx_pfc), XPORT_MIB_CORE_GTXPFC_REG, }, + { "tx_jabber", GEN_MIB_STAT(tx_jbr), XPORT_MIB_CORE_GTXJBR_REG, }, + { "tx_fcs", GEN_MIB_STAT(tx_fcs), XPORT_MIB_CORE_GTXFCS_REG, }, + { "tx_control", GEN_MIB_STAT(tx_cf), XPORT_MIB_CORE_GTXCF_REG, }, + { "tx_oversize", GEN_MIB_STAT(tx_ovr), XPORT_MIB_CORE_GTXOVR_REG, }, + { "tx_defer", GEN_MIB_STAT(tx_dfr), XPORT_MIB_CORE_GTXDFR_REG, }, + { "tx_multi_defer", GEN_MIB_STAT(tx_edf), XPORT_MIB_CORE_GTXEDF_REG, }, + { "tx_col", GEN_MIB_STAT(tx_scl), XPORT_MIB_CORE_GTXSCL_REG, }, + { "tx_multi_col", GEN_MIB_STAT(tx_mcl), XPORT_MIB_CORE_GTXMCL_REG, }, + { "tx_late_col", GEN_MIB_STAT(tx_lcl), XPORT_MIB_CORE_GTXLCL_REG, }, + { "tx_excess_col", GEN_MIB_STAT(tx_xcl), XPORT_MIB_CORE_GTXXCL_REG, }, + { "tx_fragment", GEN_MIB_STAT(tx_frg), XPORT_MIB_CORE_GTXFRG_REG, }, + { "tx_err", GEN_MIB_STAT(tx_err), XPORT_MIB_CORE_GTXERR_REG, }, + { "tx_vlan", GEN_MIB_STAT(tx_vln), XPORT_MIB_CORE_GTXVLN_REG, }, + { "tx_dvlan", GEN_MIB_STAT(tx_dvln), XPORT_MIB_CORE_GTXDVLN_REG, }, + { "tx_runt", GEN_MIB_STAT(tx_rpkt), XPORT_MIB_CORE_GTXRPKT_REG, }, + { "tx_underrun", GEN_MIB_STAT(tx_ufl), XPORT_MIB_CORE_GTXUFL_REG, }, + { "tx_pfcp0", GEN_MIB_STAT(tx_pfcp0), XPORT_MIB_CORE_GTXPFCP0_REG, }, + { "tx_pfcp1", GEN_MIB_STAT(tx_pfcp1), XPORT_MIB_CORE_GTXPFCP1_REG, }, + { "tx_pfcp2", GEN_MIB_STAT(tx_pfcp2), XPORT_MIB_CORE_GTXPFCP2_REG, }, + { "tx_pfcp3", GEN_MIB_STAT(tx_pfcp3), XPORT_MIB_CORE_GTXPFCP3_REG, }, + { "tx_pfcp4", GEN_MIB_STAT(tx_pfcp4), XPORT_MIB_CORE_GTXPFCP4_REG, }, + { "tx_pfcp5", GEN_MIB_STAT(tx_pfcp5), XPORT_MIB_CORE_GTXPFCP5_REG, }, + { "tx_pfcp6", GEN_MIB_STAT(tx_pfcp6), XPORT_MIB_CORE_GTXPFCP6_REG, }, + { "tx_pfcp7", GEN_MIB_STAT(tx_pfcp7), XPORT_MIB_CORE_GTXPFCP7_REG, }, + { "tx_tot_col", GEN_MIB_STAT(tx_ncl), XPORT_MIB_CORE_GTXNCL_REG, }, + { "tx_bytes", GEN_MIB_STAT(tx_byt), XPORT_MIB_CORE_GTXBYT_REG, }, + { "rx_lpi", GEN_MIB_STAT(rx_lpi), XPORT_MIB_CORE_GRXLPI_REG, }, + { "rx_dlpi", GEN_MIB_STAT(rx_dlpi), XPORT_MIB_CORE_GRXDLPI_REG, }, + { "tx_lpi", GEN_MIB_STAT(tx_lpi), XPORT_MIB_CORE_GTXLPI_REG, }, + { "tx_dlpi", GEN_MIB_STAT(tx_dlpi), XPORT_MIB_CORE_GTXDLPI_REG, }, + { "rx_ptllfc", GEN_MIB_STAT(rx_ptllfc), XPORT_MIB_CORE_GRXPTLLFC_REG, }, + { "rx_ltllfc", GEN_MIB_STAT(rx_ltllfc), XPORT_MIB_CORE_GRXLTLLFC_REG, }, + { "rx_llfcfcs", GEN_MIB_STAT(rx_llfcfcs), XPORT_MIB_CORE_GRXLLFCFCS_REG, }, + { "tx_ltllfc", GEN_MIB_STAT(tx_ltllfc), XPORT_MIB_CORE_GTXLTLLFC_REG, }, +}; + +/* + * + */ +static void mode_xlmac_mib_update(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + size_t i; + + for (i = 0; i < ARRAY_SIZE(xlmac_mib_estat); i++) { + const struct bcm_runner_ethtool_stat *s; + u64 val; + char *p; + + s = &xlmac_mib_estat[i]; + val = xport_mib_core_readl(mode, s->reg); + p = (char *)&mode->mib + s->offset; + *(u64 *)p = val; + } +} + +/* + * + */ +static void *mode_xlmac_mib_get_data(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + return &mode->mib; +} + +/* + * + */ +static void mode_xlmac_mtu_set(void *mode_priv, unsigned int size) +{ + struct xport_xlmac_priv *mode = mode_priv; + + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_RX_MAX_SIZE_REG, + size); +} + +/* + * + */ +static void xlmac_setup(struct xport_xlmac_priv *mode, unsigned int speed) +{ + u64 val64; + u32 val; + + /* release XLIF credits */ + val = xlif_reg_readl(mode, XLIF_TX_IF_SET_CREDITS_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_SET_CREDITS_EN_MASK; + xlif_reg_writel(mode, XLIF_TX_IF_SET_CREDITS_REG(mode->xlmac_id), val); + + /* Enable 2.5G/10G AE PFC_STATS_EN for Hardware work around */ + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_PFC_CTRL_REG); + val64 |= PFC_CTRL_PFC_STATS_EN_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_PFC_CTRL_REG, val64); + + val = xport_reg_readl(mode, XPORT_REG_XPORT_CNTRL_1_REG); + /* FIXME: should be set if we ever use more than 1 port */ + val &= ~XPORT_CNTRL_1_REG_MSBUS_CLK_SEL_MASK; + val &= ~XPORT_CNTRL_1_REG_TIMEOUT_RST_DISABLE_MASK; + if (speed == 10000) + val |= XPORT_CNTRL_1_REG_P0_MODE_MASK; + else + val &= ~XPORT_CNTRL_1_REG_P0_MODE_MASK; + xport_reg_writel(mode, XPORT_REG_XPORT_CNTRL_1_REG, val); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_TX_CTRL_REG); + val64 |= TX_CTRL_PAD_EN_MASK; + val64 &= ~TX_CTRL_CRC_MODE_MASK; + /* XLMAC_TX_CTRL_CRC_MODE_PER_PKT == 3 */ + val64 |= (3 << TX_CTRL_CRC_MODE_SHIFT); /* FIXME: set it back to 2 */ + val64 &= ~TX_CTRL_TX_THRESHOLD_MASK; + val64 |= (2ULL << TX_CTRL_TX_THRESHOLD_SHIFT); + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_TX_CTRL_REG, val64); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_RX_CTRL_REG); + /* CRC validated by BBH, so keep it */ + val64 &= ~RX_CTRL_STRIP_CRC_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_RX_CTRL_REG, val64); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 &= ~CTRL_EXTENDED_HIG2_EN_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_MODE_REG); + val64 &= ~MODE_SPEED_MODE_MASK; + switch (speed) { + case 1000: + val64 |= 2 << MODE_SPEED_MODE_SHIFT; + break; + case 10000: + val64 |= 4 << MODE_SPEED_MODE_SHIFT; + break; + default: + BUG(); + break; + } + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_MODE_REG, val64); + + /* release xlmac reset */ + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 &= ~CTRL_SOFT_RESET_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); + + /* setup mbus in work conserving mode, clear weight of unused + * ports */ + val = xport_mab_reg_readl(mode, XPORT_MAB_TX_WRR_CTRL_REG); + val |= TX_WRR_CTRL_ARB_MODE_MASK; + val &= ~TX_WRR_CTRL_P2_WEIGHT_MASK; + val &= ~TX_WRR_CTRL_P3_WEIGHT_MASK; + xport_mab_reg_writel(mode, XPORT_MAB_TX_WRR_CTRL_REG, val); + + /* release msbus reset */ + val = xport_mab_reg_readl(mode, XPORT_MAB_CNTRL_REG); + val &= ~(1 << (CNTRL_GMII_TX_RST_SHIFT + mode->xlmac_id)); + val &= ~(1 << (CNTRL_GMII_RX_RST_SHIFT + mode->xlmac_id)); + if (mode->xlmac_id == 0) { + val &= ~CNTRL_XGMII_TX_RST_MASK; + val &= ~CNTRL_XGMII_RX_RST_MASK; + } + xport_mab_reg_writel(mode, XPORT_MAB_CNTRL_REG, val); +} + +/* + * + */ +static void xlmac_reset(struct xport_xlmac_priv *mode) +{ + u64 val64; + u32 val; + + /* + * msbus reset + */ + val = xport_mab_reg_readl(mode, XPORT_MAB_CNTRL_REG); + val |= 1 << (CNTRL_GMII_TX_RST_SHIFT + mode->xlmac_id); + val |= 1 << (CNTRL_GMII_RX_RST_SHIFT + mode->xlmac_id); + + if (mode->xlmac_id == 0) { + val |= CNTRL_XGMII_TX_RST_MASK; + val |= CNTRL_XGMII_RX_RST_MASK; + } + xport_mab_reg_writel(mode, XPORT_MAB_CNTRL_REG, val); + + /* + * xlmac reset + */ + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 |= CTRL_SOFT_RESET_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); + + /* reset XLIF credits */ + xlif_reg_writel(mode, XLIF_TX_IF_SET_CREDITS_REG(mode->xlmac_id), + XLIF_TX_IF_SET_CREDITS_EN_MASK); +} + +/* + * + */ +static void xlmac_enable(struct xport_xlmac_priv *mode) +{ + u64 val64; + + val64 = xport_xlmcore_reg_readl(mode, XPORT_XLMAC_CORE_CTRL_REG); + val64 |= CTRL_TX_EN_MASK; + val64 |= CTRL_RX_EN_MASK; + xport_xlmcore_reg_writel(mode, XPORT_XLMAC_CORE_CTRL_REG, val64); +} + +/* + * + */ +static void xlmac_disable(struct xport_xlmac_priv *mode) +{ + xlmac_reset(mode); + mdelay(1); +} + +/* + * + */ +static void xlif_init(struct xport_xlmac_priv *mode) +{ + u32 val; + + val = xlif_reg_readl(mode, XLIF_TX_IF_IF_ENABLE_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_IF_ENABLE_DISABLE_WITH_CREDITS_MASK; + val &= ~XLIF_TX_IF_IF_ENABLE_DISABLE_WO_CREDITS_MASK; + xlif_reg_writel(mode, XLIF_TX_IF_IF_ENABLE_REG(mode->xlmac_id), val); + + val = xlif_reg_readl(mode, + XLIF_TX_IF_URUN_PORT_ENABLE_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_URUN_PORT_ENABLE_ENABLE_MASK; + xlif_reg_writel(mode, XLIF_TX_IF_URUN_PORT_ENABLE_REG(mode->xlmac_id), + val); + + val = xlif_reg_readl(mode, XLIF_TX_IF_TX_THRESHOLD_REG(mode->xlmac_id)); + val &= ~XLIF_TX_IF_TX_THRESHOLD_VALUE_MASK; + /* value from bcm code */ + val |= (0xc << XLIF_TX_IF_TX_THRESHOLD_VALUE_SHIFT); + xlif_reg_writel(mode, XLIF_TX_IF_TX_THRESHOLD_REG(mode->xlmac_id), val); + + val = xlif_reg_readl(mode, XLIF_RX_IF_IF_DIS_REG(mode->xlmac_id)); + val &= ~XLIF_RX_IF_IF_DIS_DISABLE_MASK; + xlif_reg_writel(mode, XLIF_RX_IF_IF_DIS_REG(mode->xlmac_id), val); +} + +/* + * + */ +static void serdes_setup_pcs_1000basex(struct xport_xlmac_priv *mode, + bool do_autoneg) +{ + int val; + + /* setup serdes in fiber mode */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1); + val |= SerdesDigital_FibreSgmiiModeFibre; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1, + val, 0xffff); + + /* setup autoneg */ + if (do_autoneg) + val = ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE; + else + val = 0; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_ADVERTISE, + val, 0xffff); + + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + val |= BMCR_SPEED1000 | BMCR_FULLDPLX; + if (do_autoneg) + val |= BMCR_ANENABLE | BMCR_ANRESTART; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_BMCR, + val, 0xffff); + +} + +/* + * + */ +static void serdes_setup_pcs_10g(struct xport_xlmac_priv *mode) +{ + int val; + + /* setup serdes in fiber mode */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1); + val |= SerdesDigital_FibreSgmiiModeFibre; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_Control1000X1, + val, 0xffff); + + /* no autoneg on 10Gbase-R */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + val &= ~BMCR_ANENABLE; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, MII_BMCR, + val, 0xffff); + + /* init from BCM */ + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, XGXSBLK0_XGXSCTRL, + 0x260f, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, XGXSBLK1_LANECTRL0, + 0x1011, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + SerdesDigital_misc1, + 0x6015, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + Digital5_parDetINDControl1, + 0x5015, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + Digital5_parDetINDControl2, + 0x0008, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital5_Misc7 , + 0x0008, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital5_Misc6, + 0x2a00, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital4_Misc3, + 0x8188, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, Digital4_Misc4, + 0x6000, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, tx66_Control, + 0x4041, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, tx66_Control, + 0x4001, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + rx66b1_rx66b1_Control1 , + rfifo_ptr_sw_rst, 0xffff); + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + rx66b1_rx66b1_Control1 , + 0, 0xffff); +} + +/* + * + */ +static void serdes_pcs_restart_aneg(struct xport_xlmac_priv *mode) +{ + int val; + + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, MII_BMCR); + if (val < 0) + return; + val |= BMCR_ANRESTART; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + MII_BMCR, val, 0xffff); +} + +/* + * + */ +static void serdes_pcs_get_link(struct xport_xlmac_priv *mode, + bool *link, + bool *an_complete) +{ + int ret; + + if (link) + *link = 0; + if (an_complete) + *an_complete = 0; + + /* BMSR register link is not updated... */ + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + XGXSBLK4_xgxsStatus1); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + if (link) + *link = (ret & XgxsStatus1_LinkStat); + +#if 0 + /* used to detect changed in registers */ + { + static u32 prev[256 * 6]; + + size_t i; + for (i = 0; i < 256 * 6; i++) { + u32 reg = 0x8000 + i; + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + reg); + if (ret < 0) + continue; + + if (prev[i] != ret) { + printk("%04x: %04x => %04x\n", + reg, prev[i], ret); + prev[i] = ret; + } + } + } +#endif + + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, MII_BMSR); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + if (an_complete) + *an_complete = (ret & BMSR_ANEGCOMPLETE); +} + +/* + * + */ +static void serdes_pcs_get_sync_ok(struct xport_xlmac_priv *mode, + bool *sync_ok_1g, + bool *sync_ok_10g) +{ + size_t i; + int ret; + + *sync_ok_1g = false; + *sync_ok_10g = false; + + for (i = 0; i < 3; i++) { + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + SerdesDigital_Status1000X2); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + if (i == 0) { + /* ignore first read */ + continue; + } + + if (!(ret & Status1000X2_sync_ok)) + break; + + if ((ret & Status1000X2_sync_failed)) + break; + + /* + * on 10GEPON link, sync_ok can go to 1 briefly + * + * to avoid false detection, sync failed must stay 0 + * and sync ok must stay one for two iterations + */ + if (i == 2) + *sync_ok_1g = true; + } + + ret = xport_serdes_pcs_read_reg(mode->port, LANE_0, + SerdesDigital_rx66_Status); + if (ret < 0) { + netdev_err(mode->port->priv->netdev, + "failed to read phy status\n"); + return; + } + + *sync_ok_10g = !!(ret & (1 << 3)); +} + +/* + * + */ +static void mode_phylink_validate(void *mode_priv, + unsigned long *supported, + struct phylink_link_state *state) +{ + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + __ETHTOOL_DECLARE_LINK_MODE_MASK(supp_only_mask) = { 0, }; + + phylink_set_port_modes(supp_only_mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + phylink_set(supp_only_mask, Autoneg); + phylink_set(supp_only_mask, 1000baseX_Full); + phylink_set(supp_only_mask, 10000baseSR_Full); + phylink_set(supp_only_mask, 10000baseLR_Full); + + switch (state->interface) { + case PHY_INTERFACE_MODE_NA: + default: + /* probing, return all supported link speed */ + state->interface = PHY_INTERFACE_MODE_1000BASEX; + goto end; + + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_10GKR: + break; + } + + /* select correct interface mode based on requested speed */ + if (!state->an_enabled) { + if (state->speed == 1000 && state->duplex) + state->interface = PHY_INTERFACE_MODE_1000BASEX; + else if (state->speed == 10000 && state->duplex) + state->interface = PHY_INTERFACE_MODE_10GKR; + } else { + if (phylink_test(state->advertising, 1000baseX_Full)) { + phylink_set(mask, 1000baseX_Full); + phylink_set(mask, Autoneg); + state->interface = PHY_INTERFACE_MODE_1000BASEX; + } + } + +end: + linkmode_copy(supported, supp_only_mask); + linkmode_copy(state->advertising, mask); +} + + +static const struct serdes_params serdes_params_1g = { + .misc3_if_select = 1, + .misc3_laser_mode = 0, + + .tx_pll_vco_div2 = 0, + .tx_pll_vco_div4 = 0, + .rx_pll_id = serdes_PLL_0, + .tx_pll_id = serdes_PLL_0, + + .tx_pll_force_kvh_bw = 0x1, + .tx_pll_kvh_force = 0, + + .tx_pll_2rx_bw = 0, + + .tx_pll_fracn_sel = 0x1, + + .tx_pll_ditheren = 0x1, + + .tx_pll_fracn_div = 0x00000, + .tx_pll_fracn_ndiv = 0x0c8, + + .tx_pll_mode = 0x5, + + .rx_tx_rate_ratio = 0, + + .rx_pon_mac_ctrl = 0, + .tx_pon_mac_ctrl = 0, + .tx_sync_e_ctrl = 0, + + .rx_osr_mode = 0x7, + .tx_osr_mode = 0x7, + + .do_rx_pi_spacing = false, + .clk90_offset = 0, + .p1_offset = 0, + .dsc_a_cdr_control_2 = 0x00f0, + + .do_pll_charge_pump = false, + .do_pll_charge_pump_10g = false, + .do_vga_rf = false, + .do_sigdetect = false, + .do_ae = true, + .serdes_ae_full_rate = true, + .serdes_ae_20b_width = false, +}; + +static const struct serdes_params serdes_params_10g = { + .misc3_if_select = 3, + .misc3_laser_mode = 0, + + .tx_pll_vco_div2 = 0, + .tx_pll_vco_div4 = 0, + .rx_pll_id = serdes_PLL_0, + .tx_pll_id = serdes_PLL_0, + + .tx_pll_force_kvh_bw = 0x1, + .tx_pll_kvh_force = 0, + + .tx_pll_2rx_bw = 0, + + .tx_pll_fracn_sel = 0x1, + + .tx_pll_ditheren = 0x1, + + .tx_pll_fracn_div = 0x10000, + .tx_pll_fracn_ndiv = 0x0ce, + + .tx_pll_mode = 0x2, + + .rx_tx_rate_ratio = 0, + + .rx_pon_mac_ctrl = 0x3, + .tx_pon_mac_ctrl = 0x3, + .tx_sync_e_ctrl = 0x7, + + .rx_osr_mode = 0x0, + .tx_osr_mode = 0x0, + + .do_rx_pi_spacing = false, + .clk90_offset = 0, + .p1_offset = 0, + .dsc_a_cdr_control_2 = 0x00c0, /* 0x30 in pon driver */ + + .do_pll_charge_pump = false, + .do_pll_charge_pump_10g = false, + .do_vga_rf = false, + .do_sigdetect = false, + .do_ae = true, + .serdes_ae_full_rate = true, + .serdes_ae_20b_width = true, +}; + +/* + * + */ +static void mode_phylink_mac_config(void *mode_priv, + unsigned int pl_mode, + const struct phylink_link_state *state) +{ + struct xport_xlmac_priv *mode = mode_priv; + const struct serdes_params *serdes_params; + int val; + + mode->phylink_cfg_state = *state; + if (mode->phylink_prev_link) { + xlmac_disable(mode); + phylink_mac_change(mode->port->priv->phylink, false); + mode->phylink_prev_link = false; + } + + mutex_lock(&mode->serdes_mutex); + + /* + * choose correct serdes params + */ + switch (state->interface) { + case PHY_INTERFACE_MODE_1000BASEX: + serdes_params = &serdes_params_1g; + break; + case PHY_INTERFACE_MODE_10GKR: + serdes_params = &serdes_params_10g; + break; + default: + BUG(); + break; + } + + xport_serdes_set_params(mode->port, serdes_params); + + /* + * restore LBE forced value + */ + if (!mode->port->lbe_force) + xport_serdes_lbe_dont_force(mode->port); + else if (mode->port->lbe_force_value) + xport_serdes_lbe_force_enable(mode->port); + else + xport_serdes_lbe_force_disable(mode->port); + + /* from BCM AE code */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + CL49_UserB0_Control); + val &= ~CL49_fast_lock_cya; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + CL49_UserB0_Control, + val, 0xffff); + + /* from BCM AE code */ + val = xport_serdes_pcs_read_reg(mode->port, LANE_BRDCST, + XgxsBlk10_tx_pi_control4); + val |= tx_pi_sm_enable_override_value; + xport_serdes_pcs_write_reg(mode->port, LANE_BRDCST, + XgxsBlk10_tx_pi_control4, + val, 0xffff); + + switch (state->interface) { + case PHY_INTERFACE_MODE_1000BASEX: + serdes_setup_pcs_1000basex(mode, state->an_enabled); + break; + case PHY_INTERFACE_MODE_10GKR: + serdes_setup_pcs_10g(mode); + default: + break; + } + + mutex_unlock(&mode->serdes_mutex); + + if (!mode->configured) { + schedule_delayed_work(&mode->serdes_poll_work, HZ); + mode->configured = true; + } +} + +/* + * + */ +static void mode_phylink_link_up(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface, + struct phy_device *phy) +{ + struct xport_xlmac_priv *mode = mode_priv; + int speed; + + switch (mode->phylink_cfg_state.interface) { + case PHY_INTERFACE_MODE_1000BASEX: + speed = 1000; + break; + case PHY_INTERFACE_MODE_10GKR: + speed = 10000; + break; + default: + BUG(); + break; + } + + xlmac_setup(mode, speed); + xlmac_enable(mode); +} + +/* + * + */ +static void mode_phylink_link_down(void *mode_priv, + unsigned int pl_mode, + phy_interface_t interface) +{ + struct xport_xlmac_priv *mode = mode_priv; + xlmac_disable(mode); +} + +/* + * + */ +static void mode_phylink_pcs_an_restart(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + + if (!mode->configured) + return; + + mutex_lock(&mode->serdes_mutex); + serdes_pcs_restart_aneg(mode); + mutex_unlock(&mode->serdes_mutex); +} + +/* + * + */ +static int mode_phylink_pcs_link_state(void *mode_priv, + struct phylink_link_state *state) +{ + struct xport_xlmac_priv *mode = mode_priv; + bool link, an_complete; + + state->link = 0; + if (!mode->configured) + return 0; + + mutex_lock(&mode->serdes_mutex); + serdes_pcs_get_link(mode, &link, &an_complete); + mutex_unlock(&mode->serdes_mutex); + + state->an_enabled = mode->phylink_cfg_state.an_enabled; + if (mode->phylink_cfg_state.an_enabled) { + state->an_complete = an_complete; + if (!state->an_complete) + return 0; + } else { + state->an_complete = 0; + state->speed = mode->phylink_cfg_state.speed; + state->duplex = mode->phylink_cfg_state.duplex; + } + + state->link = link; + switch (mode->phylink_cfg_state.interface) { + case PHY_INTERFACE_MODE_1000BASEX: + state->speed = 1000; + state->duplex = 1; + break; + case PHY_INTERFACE_MODE_10GKR: + state->speed = 10000; + state->duplex = 1; + break; + default: + break; + } + + return 0; +} + +/* + * + */ +static void poll_link_work(struct work_struct *w) +{ + struct delayed_work *dwork = to_delayed_work(w); + struct xport_xlmac_priv *mode; + bool link, an_complete; + + mode = container_of(dwork, struct xport_xlmac_priv, serdes_poll_work); + + mutex_lock(&mode->serdes_mutex); + serdes_pcs_get_link(mode, &link, &an_complete); + mutex_unlock(&mode->serdes_mutex); + + if (mode->phylink_cfg_state.an_enabled && !an_complete) + link = false; + + if (link != mode->phylink_prev_link) { + phylink_mac_change(mode->port->priv->phylink, link); + mode->phylink_prev_link = link; + } + + /* resched */ + schedule_delayed_work(&mode->serdes_poll_work, HZ); +} + +/* + * + */ +static u32 mode_get_priv_flags(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + bool sync_ok_1g, sync_ok_10g; + u32 val; + + val = (mode->port->lbe_force ? 1 : 0) << + PRIV_FLAGS_FORCE_LBE_OE_BIT; + val |= (mode->port->lbe_force_value ? 1 : 0) << + PRIV_FLAGS_FORCE_LBE_OE_VAL_BIT; + + mutex_lock(&mode->serdes_mutex); + serdes_pcs_get_sync_ok(mode, &sync_ok_1g, &sync_ok_10g); + mutex_unlock(&mode->serdes_mutex); + + switch (mode->phylink_cfg_state.interface) { + case PHY_INTERFACE_MODE_1000BASEX: + if (sync_ok_1g) + val |= 1 << PRIV_FLAGS_ST_SYNC_OK_BIT; + break; + case PHY_INTERFACE_MODE_10GKR: + if (sync_ok_10g) + val |= 1 << PRIV_FLAGS_ST_SYNC_OK_BIT; + break; + default: + break; + } + + return val; +} + +/* + * + */ +static int mode_set_priv_flags(void *mode_priv, u32 flags) +{ + struct xport_xlmac_priv *mode = mode_priv; + + if (!(flags & (1 << PRIV_FLAGS_FORCE_LBE_OE_BIT))) { + mode->port->lbe_force = false; + xport_serdes_lbe_dont_force(mode->port); + } else { + mode->port->lbe_force = true; + if (flags & (1 << PRIV_FLAGS_FORCE_LBE_OE_VAL_BIT)) { + mode->port->lbe_force_value = true; + xport_serdes_lbe_force_enable(mode->port); + } else { + mode->port->lbe_force_value = false; + xport_serdes_lbe_force_disable(mode->port); + } + } + + return 0; +} + +/* + * called each time netdevice is stopped + */ +static void mode_xlmac_stop(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + + bcm_runner_fw_tx_stop_wait(mode->port->priv); + if (!mode->configured) + return; + + mode->configured = false; + cancel_delayed_work_sync(&mode->serdes_poll_work); +} + +/* + * + */ +static void *mode_xlmac_init(void *port_priv, + const struct bcm_xrdp_enet_params *params) +{ + struct xport_priv *port = port_priv; + struct xport_xlmac_priv *mode; + + mode = kzalloc(sizeof (*mode), GFP_KERNEL); + if (!mode) + return ERR_PTR(-ENOMEM); + + mode->port = port; + mutex_init(&mode->serdes_mutex); + INIT_DELAYED_WORK(&mode->serdes_poll_work, poll_link_work); + + xlif_init(mode); + xlmac_reset(mode); + + return mode; +} + +/* + * called only when netdevice is stopped + */ +static void mode_xlmac_release(void *mode_priv) +{ + struct xport_xlmac_priv *mode = mode_priv; + kfree(mode); +} + +/* + * + */ +static u32 mode_get_bbh_id(void *port_priv) +{ + struct xport_priv *port = port_priv; + return port->ae_bbh_id; +} + +const struct bcm_enet_mode_ops xport_xlmac_mode_ops = { + .name = "AE", + + .init = mode_xlmac_init, + .release = mode_xlmac_release, + + .stop = mode_xlmac_stop, + .get_bbh_id = mode_get_bbh_id, + .mtu_set = mode_xlmac_mtu_set, + + /* mib operation */ + .mib_estat = xlmac_mib_estat, + .mib_estat_count = ARRAY_SIZE(xlmac_mib_estat), + .mib_update = mode_xlmac_mib_update, + .mib_get_data = mode_xlmac_mib_get_data, + + /* get/set private on netdevice */ + .get_priv_flags = mode_get_priv_flags, + .set_priv_flags = mode_set_priv_flags, + + /* + * phylink callback + */ + .phylink_validate = mode_phylink_validate, + .phylink_mac_config = mode_phylink_mac_config, + .phylink_link_down = mode_phylink_link_down, + .phylink_link_up = mode_phylink_link_up, + .phylink_pcs_link_state = mode_phylink_pcs_link_state, + .phylink_pcs_an_restart = mode_phylink_pcs_an_restart, +}; diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/port_xport_xlmac.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/port_xport_xlmac.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,257 @@ +#ifndef PORT_XPORT_XLMAC_H_ +#define PORT_XPORT_XLMAC_H_ + +#include "port_xport.h" + +#include "regs/xport_xlmac_core.h" +#include "regs/xport_xlmac_reg.h" +#include "regs/xport_mib_core.h" +#include "regs/xport_reg.h" +#include "regs/xport_mib_reg.h" +#include "regs/xport_mab.h" +#include "regs/xlif.h" + +struct xlmac_mib { + u64 rx_64; + u64 rx_127; + u64 rx_255; + u64 rx_511; + u64 rx_1023; + u64 rx_1518; + u64 rx_1522; + u64 rx_2047; + u64 rx_4095; + u64 rx_9216; + u64 rx_16383; + u64 rx_pkt; + u64 rx_uca; + u64 rx_mca; + u64 rx_bca; + u64 rx_fcs; + u64 rx_cf; + u64 rx_pf; + u64 rx_pp; + u64 rx_uo; + u64 rx_uda; + u64 rx_wsa; + u64 rx_aln; + u64 rx_flr; + u64 rx_frerr; + u64 rx_fcr; + u64 rx_ovr; + u64 rx_jbr; + u64 rx_mtue; + u64 rx_mcrc; + u64 rx_prm; + u64 rx_vln; + u64 rx_dvln; + u64 rx_trfu; + u64 rx_pok; + u64 rx_pfcoff0; + u64 rx_pfcoff1; + u64 rx_pfcoff2; + u64 rx_pfcoff3; + u64 rx_pfcoff4; + u64 rx_pfcoff5; + u64 rx_pfcoff6; + u64 rx_pfcoff7; + u64 rx_pfcp0; + u64 rx_pfcp1; + u64 rx_pfcp2; + u64 rx_pfcp3; + u64 rx_pfcp4; + u64 rx_pfcp5; + u64 rx_pfcp6; + u64 rx_pfcp7; + u64 rx_schcrc; + u64 rx_byt; + u64 rx_rpkt; + u64 rx_und; + u64 rx_frg; + u64 rx_rbyt; + u64 tx_64; + u64 tx_127; + u64 tx_255; + u64 tx_511; + u64 tx_1023; + u64 tx_1518; + u64 tx_1522; + u64 tx_2047; + u64 tx_4095; + u64 tx_9216; + u64 tx_16383; + u64 tx_pok; + u64 tx_pkt; + u64 tx_uca; + u64 tx_mca; + u64 tx_bca; + u64 tx_pf; + u64 tx_pfc; + u64 tx_jbr; + u64 tx_fcs; + u64 tx_cf; + u64 tx_ovr; + u64 tx_dfr; + u64 tx_edf; + u64 tx_scl; + u64 tx_mcl; + u64 tx_lcl; + u64 tx_xcl; + u64 tx_frg; + u64 tx_err; + u64 tx_vln; + u64 tx_dvln; + u64 tx_rpkt; + u64 tx_ufl; + u64 tx_pfcp0; + u64 tx_pfcp1; + u64 tx_pfcp2; + u64 tx_pfcp3; + u64 tx_pfcp4; + u64 tx_pfcp5; + u64 tx_pfcp6; + u64 tx_pfcp7; + u64 tx_ncl; + u64 tx_byt; + u64 rx_lpi; + u64 rx_dlpi; + u64 tx_lpi; + u64 tx_dlpi; + u64 rx_ptllfc; + u64 rx_ltllfc; + u64 rx_llfcfcs; + u64 tx_ltllfc; +}; + +struct xport_xlmac_priv { + struct xport_priv *port; + + unsigned int xlmac_id; + struct xlmac_mib mib; + + bool configured; + struct mutex serdes_mutex; + struct delayed_work serdes_poll_work; + bool phylink_prev_link; + struct phylink_link_state phylink_cfg_state; + + bool laser_active_hi; +}; + + +/* + * io accessors + */ +static inline u32 xlif_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[2] + offset); +} + +static inline void xlif_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + return iowrite32(val, mode->port->regs[2] + offset); +} + +static inline u32 xport_xlmreg_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + + XPORT_XLMAC_REG_OFFSET_0 + offset); +} + +static inline void xport_xlmreg_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + + XPORT_XLMAC_REG_OFFSET_0 + offset); +} + +static inline u64 xport_xlmcore_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + u32 val32, hold; + u64 ret; + + /* indirect access */ + val32 = ioread32(mode->port->regs[1] + + XPORT_XLMAC_CORE_OFFSET(mode->xlmac_id) + offset); + hold = xport_xlmreg_reg_readl(mode, + XPORT_XLMAC_REG_DIR_ACC_DATA_READ_REG); + + ret = (((u64)hold) << 32) | val32; + return ret; +} + +static inline void xport_xlmcore_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u64 val) +{ + u32 val32, hold; + + val32 = val & 0xffffffff; + hold = val >> 32; + + xport_xlmreg_reg_writel(mode, + XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_REG, + hold); + iowrite32(val, mode->port->regs[1] + + XPORT_XLMAC_CORE_OFFSET(mode->xlmac_id) + offset); +} + +static inline u32 xport_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + + XPORT_REG_OFFSET_0 + offset); +} + +static inline void xport_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + + XPORT_REG_OFFSET_0 + offset); +} + +static inline u32 xport_mib_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + + XPORT_MIB_REG_OFFSET_0 + offset); +} + +static inline void xport_mib_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + XPORT_MIB_REG_OFFSET_0 + offset); +} + +static inline u64 xport_mib_core_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + u32 val32, hold; + u64 ret; + + /* indirect access */ + val32 = ioread32(mode->port->regs[1] + + XPORT_MIB_CORE_OFFSET(mode->xlmac_id) + offset); + hold = xport_mib_reg_readl(mode, + XPORT_MIB_REG_DIR_ACC_DATA_READ_REG); + + ret = (((u64)hold) << 32) | val32; + return ret; +} + +static inline u32 xport_mab_reg_readl(struct xport_xlmac_priv *mode, + u32 offset) +{ + return ioread32(mode->port->regs[1] + XPORT_MAB_OFFSET_0 + offset); +} + +static inline void xport_mab_reg_writel(struct xport_xlmac_priv *mode, + u32 offset, u32 val) +{ + iowrite32(val, mode->port->regs[1] + XPORT_MAB_OFFSET_0 + offset); +} + +#endif /* PORT_XPORT_XLMAC_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,3456 @@ +#ifndef EPON_EPN_H_ +#define EPON_EPN_H_ + +/* relative to epon */ +#define EPN_OFFSET_0 0x1000 + +/* + * Register + * + * This register controls and configures the modules in the EPON block. + */ +#define EPN_CONTROL_0_REG 0x0 + +/* + * Enable IEEE 1588 packet timestamping, applicable only inpoint-to-point + * mode. +*/ +#define CONTROL_0_CFGEN1588TS_MASK 0x80000000 + +/* + * Replaces FCS of upstream packet, resulting in no change in + * packet'slength. + * Set cfgAppendUpFcs/cfgReplaceUpFcs to 0 for pass-through. +*/ +#define CONTROL_0_CFGREPLACEUPFCS_MASK 0x40000000 + +/* + * Appends FCS to upstream packet, resulting in increase of packet'slength + * +4 bytes. + * Set cfgAppendUpFcs/cfgReplaceUpFcs to 0 forpass-through. +*/ +#define CONTROL_0_CFGAPPENDUPFCS_MASK 0x20000000 + +/* + * Drops Single Copy Broadcast packets that are unmapped by the LIF. + * 0: + * Ignore LLID bit 15. + * 1: + * Drop packets that have LLID bit 15 set and have LLID index bit 5set. +*/ +#define CONTROL_0_CFGDROPSCB_MASK 0x10000000 + +/* + * Ignores the first queue set limits. + * This is only applied whenThreshold First Queue Service Discipline is + * enabled. + * 0: + * Transmit packets in the order they were last reported in thefirst queue + * set. + * 1: + * Transmit packets in the order they were last reported in theun-capped + * queue set. +*/ +#define CONTROL_0_MODUNCAPPEDREPORTLIMIT_MASK 0x8000000 + +/* + * Enables Threshold First Queue Service Discipline. + * This is onlyapplied to multi-priority reporting mode. + * 0: + * Strict priority. + * The highest priority packet is transmitted. + * This mode 'pulls' late-arriving/un-reported high priority packetsahead + * of previously reported lower priority packets. + * 1: + * Transmit packets in the order they were last reported. +*/ +#define CONTROL_0_MODMPQUESETFIRST_MASK 0x4000000 + +/* + * Propagates the ONU's local MPCP time by replacing the last fourbytes of + * a GATE frame with the MPCP time the GATE arrived at theONU. + * This only applies to downstream gate messages passed from theEpn to the + * BBH. + * 0: + * Do not propagate the local MPCP time1: + * Propagate the local MPCP time +*/ +#define CONTROL_0_PRVLOCALMPCPPROPAGATION_MASK 0x1000000 + +/* + * Allows accumulator 3 to be prefetched before accumulator 0 isemptied and + * the accumulator shift occurs. + * This eliminates the racestarting when the accumulators shift and their + * values are reported(i. + * e. + * accumulator 3 will fully represent the current queue state). + * 0: + * Do not prefetch accumulator 31: + * Prefetch accumulator 3 +*/ +#define CONTROL_0_PRVTEKMODEPREFETCH_MASK 0x800000 + +/* + * Causes non-zero accumulator values to be incremented before + * beingreported upstream. + * 0: + * No accumulator values are incremented1: + * Non-zero accumulator values are incremented +*/ +#define CONTROL_0_PRVINCNONZEROACCUM_MASK 0x200000 + +/* + * Disables FCS checking of un-mapped frames. + * This is intended to beused when passing unmapped frames to a UNI port. + * 0: + * All FCS errored un-mapped frames are discarded1: + * All un-mapped frames are passed to a UNI port +*/ +#define CONTROL_0_PRVNOUNMAPPPEDFCS_MASK 0x100000 + +/* + * Causes discovery gates for empty queues to be discarded. + * 0: + * All discovery gates are processed1: + * Discovery gates for empty queues are discarded +*/ +#define CONTROL_0_PRVSUPRESSDISCEN_MASK 0x80000 + +/* + * Overrides the value in EPON Downstream Max Size Frame register. + * 0: + * Use Downstream Max Size Frame register value1: + * The maximum frame size for non-VLAN frames is 1518 and themaximum size + * for VLAN-tagged frames is 1522 +*/ +#define CONTROL_0_CFGVLANMAX_MASK 0x40000 + +/* + * Determines which types of upstream frames are affected when + * forcingupstream FCS errors (as configured in EPON Force FCS Error + * register)0: + * Force FCS errors on all upstream frames. + * 1: + * Force FCS errors on user data frames only (not REPORT orprocessor + * frames). +*/ +#define CONTROL_0_FCSERRONLYDATAFR_MASK 0x20000 + +/* + * Determines handling of traffic not mapped to a provisioned LLID0: + * Forward unmapped packets1: + * Drop unmapped packets +*/ +#define CONTROL_0_PRVDROPUNMAPPPEDLLID_MASK 0x1000 + +/* + * Controls LLID mode bit suppression0: + * LLID mode enabled1: + * Suppress LLID mode by masking bit-15 of the LLID +*/ +#define CONTROL_0_PRVSUPPRESSLLIDMODEBIT_MASK 0x800 + +/* + * Discovery gate destination address filter enable. + * 0: + * Always ignore discovery gate DA value1: + * Process discovery gate only if the following criteria are met. + * Please keep in mind the functionality provided by the legacy + * "DropDiscovery Gate" controls. + * No discovery gate will be processed if thediscovery gate's LLID index + * has been provisioned to "Drop DiscoveryGates". + * Also, only the first 8 LLID index values are eligible fordiscovery gate + * processing. + * Discovery gates with any other LLID indexvalues received from the LIF + * will not be processed. + * When this feature is disabled the discovery DA is ignored. + * When thisfeature is enabled there are four possible scenarios: + * (1) Received broadcast LLID (0x7FFF) and a unicast (not broadcastand not + * multicast) DA. + * Discovery gate is processed if one of the provisioned ONT addressesmust + * match the discovery gate's DA. + * (2) Received broadcast LLID (0x7FFF) and a broadcast DA. + * Discovery gate is processed. + * i. + * e. + * , the discovery gate's DA isignored. + * (3) Received a non-broadcast LLID and a unicast DA. + * Discovery gate is processed if the discovery gate's LLID + * indexprovisioned ONT address matches its DA. + * (4) Received a non-broadcast LLID and a broadcast DA. + * Discovery gate is processed. + * i. + * e. + * , the discovery gate's DA isignored. + * Please remember the "Drop Discovery Gate" control takes precedenceover + * all other configuration options +*/ +#define CONTROL_0_MODDISCOVERYDAFILTEREN_MASK 0x400 + +/* + * Selects the number of Queue Sets generated for all LLID Indexes0: + * Dual queue set (default)1: + * Multi queue set ('Teknovus-style')Others: + * Reserved +*/ +#define CONTROL_0_RPTSELECT_SHIFT 8 +#define CONTROL_0_RPTSELECT_MASK 0x300 + +/* + * Disables Shaped Virtual Accumulator backpressure of BBH queue + * statusinterface. + * 0: + * SVA normal operation. + * Allows shapers to backpressure the BBHqueue status interface. + * 1: + * Disables Shaped Virtual Accumulator backpressure of BBH queuestatus + * interface. + * . +*/ +#define CONTROL_0_PRVDISABLESVAQUESTATUSBP_MASK 0x80 + +/* + * Places the upstream transmitter (UTX) in loopback mode. + * 0: + * UTX normal operation1: + * UTX is in loopback mode. + * This setting is also used for Point toPoint mode (in conjunction with + * settings in the LIF Controlregister). +*/ +#define CONTROL_0_UTXLOOPBACK_MASK 0x40 + +/* + * UTX Enable bit. + * 0: + * Disable the UTX block1: + * Enable UTX operation +*/ +#define CONTROL_0_UTXEN_MASK 0x20 + +/* + * Reset the EPN upstream transmitter (UTX) logic. + * Asserting (activelow) this bit resets all UTX state machines and + * pointers. + * Note thatthis does not reset the UTX configuration registers. + * 0: + * Hold the UTX in reset1: + * Normal UTX operation +*/ +#define CONTROL_0_UTXRST_PRE_N_MASK 0x10 + +/* + * Prevents any downstream traffic from being sent to the BBH. + * Thiscontrol is only applied between downstream packets. + * So, it can betoggled any time the drxEn bit is set. + * 0: + * Normal operation. + * 1: + * No data is sent to BBH. +*/ +#define CONTROL_0_CFGDISABLEDNS_MASK 0x8 + +/* + * Places the downstream receiver (DRX) in loopback mode. + * The loopbackmode disables the EPON processing in EPN's downstream data + * path. + * Itdoes not 'loopback' any data. + * 0: + * DRX normal operation1: + * DRX is in loopback mode +*/ +#define CONTROL_0_DRXLOOPBACK_MASK 0x4 + +/* + * DRX Enable bit. + * 0: + * Disable the DRX block1: + * Enable DRX operation +*/ +#define CONTROL_0_DRXEN_MASK 0x2 + +/* + * Reset the EPN downstream receiver (DRX) logic. + * Asserting (activelow) this bit resets all DRX state machines and + * pointers. + * Note thatthis does not reset the DRX configuration registers. + * 0: + * Hold the DRX in reset1: + * Normal DRX operation +*/ +#define CONTROL_0_DRXRST_PRE_N_MASK 0x1 + + +/* + * Register + * + * This register controls and configures the modules in the EPN block. + */ +#define EPN_CONTROL_1_REG 0x4 + +/* + * When this bit is set, the EPON MAC will tag completely tardyupstream + * packets as an idle packet by replacingthe SOF transfer type with 5'd23. + * The XIF will detect the idlepacket SOF tag and replace the entire packet + * with idles. + * In the case of 1G the 5'd23 SOF is converted to 3'd6 to get past + * theTimeStamp logic and then converted to 3'd5 so the LIFcan detect the + * idle packet SOF tag and replace the entire packetwith idles. + * Partially tardy packets are still faked and their FCS valuesreplaced + * with zeros. + * Do not enable this feature for AE or P2Poperating modes. + * Default value is 0 +*/ +#define CONTROL_1_CFGIDLEPACKETTXENABLE_MASK 0x800000 + +/* + * When this bit is set, the EPON MAC will not dither the MPCPcorrection + * values sent to the LIF. + * Default value is 0 +*/ +#define CONTROL_1_CFGDISABLEMPCPCORRECTIONDITHERING_MASK 0x400000 + +/* + * Enables adjustment of "destructively overlapped" grants. + * Destructively overlapped grants are grants that overlap by more thanthe + * provisioned grant overhead (Lon + Loff + Sync time). + * 0: + * Disable adjustment of destructively overlapped grants. + * Destuctively overlapped grants are dropped and the + * GrantMisaligninterrupt sets. + * 1: + * Destructively overlapped grants are adjusted to limit overlap tothe + * grant overhead value (which maximizes the useful length of theearlier + * grant). +*/ +#define CONTROL_1_PRVOVERLAPPEDGNTENABLE_MASK 0x200000 + +/* Reset the grant misalignment hardware */ +#define CONTROL_1_RSTMISALIGNTHR_MASK 0x100000 + +/* + * When this bit is set, the EPON MAC will check the grant FIFOs forstale + * grants, and delete them. + * A stale grant has a grant start timethat is smaller (earlier) than the + * local ONU time. + * Default value is1 +*/ +#define CONTROL_1_CFGSTALEGNTCHK_MASK 0x40000 + +/* + * Global upstream FEC enable. + * When this bit is set, the EPON MAC willtake into account FEC overhead + * when generating report frames andfilling grants. + * Please note that the per-LLID index bit must also beset. +*/ +#define CONTROL_1_FECRPTEN_MASK 0x20000 + +/* + * Enables an alternate scheme in the L1-to-L2 strict-priorityscheduler. + * This alternate scheme is useful only when bothcfgSharedBurstCap and + * cfgSharedL2 are set ("TK3715 CTCcompatibility" mode). + * Note: + * Support for this bit begins in Revision B0. + * 0: + * Default scheme. + * 1: + * Alternate mode. + * Use only in multi-priority mode whencfgSharedBurstCap is set. +*/ +#define CONTROL_1_CFGL1L2TRUESTRICT_MASK 0x80 + +/* + * Sets the number of priorities for multi-priority mode. + * The 24available L2s queues are sequentially mapped to the + * prioritieswithin each LLID index. + * For example in mode "01": + * L2s queue 0 ismapped to LLID index 0 priority 0; L2s queue 1 is mapped + * to LLIDindex 0 priority 1; L2s queue 2 is mapped to LLID index 0 + * priority2; L2s queue 3 is mapped to LLID index 1 priority 0; and so on. + * 00: + * Multi-priority mode disabled. + * 01: + * Eight LLID indexes with 3 priorities each. + * 10: + * Six LLID indexes with 4 priorities each. + * 11: + * Three LLID indexes with 8-priorities each. +*/ +#define CONTROL_1_CFGCTCRPT_SHIFT 5 +#define CONTROL_1_CFGCTCRPT_MASK 0x60 + +/* + * Disables incremental (+1, -1) correction of local downstream MPCPtime. + * When set, MPCP time is updated only when the differencebetween the local + * MPCP time and the timestamp received in an MPCPDUis different by greater + * than the EPN Time Stamp Differentialregister value. +*/ +#define CONTROL_1_CFGTSCORRDIS_MASK 0x10 + +/* When set the ONU will ignore the force report bit on discoveryframes. */ +#define CONTROL_1_CFGNODISCRPT_MASK 0x8 + +/* + * When this bit is set, the start time offset for a discovery responsewill + * be equal to the discovery seed. + * Units of the offset are 16-bittimes. +*/ +#define CONTROL_1_DISABLEDISCSCALE_MASK 0x4 + +/* All statistics RAM reads will clear the read location. */ +#define CONTROL_1_CLRONRD_MASK 0x2 + + +/* + * Register + * + * This register allows per-LLID control over whether the EPON MAC + * acceptsgrants from the OLT. + */ +#define EPN_ENABLE_GRANTS_REG 0x8 + +/* + * Enable Grants on LLID Index 0. + * Reset default is 1. +*/ +#define ENABLE_GRANTS_ENGNTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over whether the EPON MACprocesses + * Discovery Gates. + */ +#define EPN_DROP_DISC_GATES_REG 0xc + +/* Discard Discovery Gates on LLID Index 0. */ +#define DROP_DISC_GATES_SINKDISCGATESx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over Ethernet frame CRC checkingin + * the EPON downstream block. + */ +#define EPN_DIS_FCS_CHK_REG 0x10 + +/* Do not check FCS on downstream frames received on LLID index 0 */ +#define DIS_FCS_CHK_DISABLEFCSCHKx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over whether the EPON MAC + * passesdownstream gate frames to the BBH. + */ +#define EPN_PASS_GATES_REG 0x14 + +/* If set, downstream gate frames will be passed to the BBH for LLID 0 */ +#define PASS_GATES_PASSGATELLIDx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows per-LLID control over grant misalignment + * checkingand feedback. + */ +#define EPN_CFG_MISALGN_FB_REG 0x18 + +/* + * 0: + * Ignore misalignment condition1: + * Enable grant misalignment detection on LLID Index 0. + * Whendetected, EPON MAC will temporarily report empty queue status(REPORT + * frame) on the LLID Index. +*/ +#define CFG_MISALGN_FB_CFGMISALIGNFEEDBACKx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * The 10G Discovery Information field is 16 bits right after the Synctime + * in the Disc Gate. + * The 10G discovery gate filter consistes of twobit-fields: + * a 16-bit Disc Info Value and 16-bit Disc Info Mask. + * For allbits in Disc Info Value whose corresponding Mask bits are clear + * (notmasked), the bits in Disc Info Value must exactly match + * thecorresponding bits in the GATE Discovery Information field. + * If theydon't match, drop the GATE (nothing is added into the Grant + * FIFO). + * Ifthey match, the Start Time and Length are added to the Grant FIFO. + */ +#define EPN_DISCOVERY_FILTER_REG 0x1c + +/* + * Any mask bit that is set will exclude its corresponding bit from + * theabove comparison (i. + * e. + * set mask bits are considered "don't carebits). +*/ +#define DISCOVERY_FILTER_PRVDISCINFOMASK_SHIFT 16 +#define DISCOVERY_FILTER_PRVDISCINFOMASK_MASK 0xffff0000 + +/* The value to match */ +#define DISCOVERY_FILTER_PRVDISCINFOVALUE_SHIFT 0 +#define DISCOVERY_FILTER_PRVDISCINFOVALUE_MASK 0xffff + + +/* + * Register + * + * The EPN requires a minimum amount of time to process each grant. + * Thisprocessing time includes the time for the BBH to fetch a packet + * andsetup time for theupstream data to be processed by the LIF/XIF. + * It is possible forbackpressure generated by the BBH and LIF/XIF to stall + * the grantprocessing beyond the time required to process the grant. + * Any grants that are not processed this many TimeQuanta before it + * GrantStart Time will be aborted and a grant miss-abort interrupt will + * begenerated. + */ +#define EPN_MINIMUM_GRANT_SETUP_REG 0x20 + +/* + * Minimum amount of grant processing time required to guarantee + * theupstream data will be transmitted. + * The units are EPON TimeQuanta(16 nS). +*/ +#define MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_SHIFT 0 +#define MINIMUM_GRANT_SETUP_CFGMINGRANTSETUP_MASK 0xffff + + +/* + * Register + * + * This register allows resetting of the Grant FIFOs on a per-LLID basis. + */ +#define EPN_RESET_GNT_FIFO_REG 0x24 + +/* Resets the read and write pointers for grant FIFO 0. */ +#define RESET_GNT_FIFO_RSTGNTFIFOx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows resetting of the L1 accumulators. + */ +#define EPN_RESET_L1_ACCUMULATOR_REG 0x28 + +/* Set the respective bit(s) to reset L1 accumulator(s). */ +#define RESET_L1_ACCUMULATOR_CFGL1SCLRACUM_SHIFT 0 +#define RESET_L1_ACCUMULATOR_CFGL1SCLRACUM_MASK 0xffffffff + + +/* + * Register + * + * This register selects which virtual accumulator sizes are reported. + */ +#define EPN_L1_ACCUMULATOR_SEL_REG 0x2c + +/* Selects which L1S Un-shaped Virtual Accumulator size will bereported. */ +#define L1_ACCUMULATOR_SEL_CFGL1SUVASIZESEL_SHIFT 5 +#define L1_ACCUMULATOR_SEL_CFGL1SUVASIZESEL_MASK 0x3e0 + +/* Selects which L1S Shaped Virtual Accumulator size will be reported. */ +#define L1_ACCUMULATOR_SEL_CFGL1SSVASIZESEL_SHIFT 0 +#define L1_ACCUMULATOR_SEL_CFGL1SSVASIZESEL_MASK 0x1f + + +/* + * Register - read-only + * + * Signed number of bytes in the selected L1S Shaped Virtual Accumulator + */ +#define EPN_L1_SVA_BYTES_REG 0x30 + +/* + * Signed number of bytes in the selected L1S Shaped VirtualAccumulator. + * Bit-29 is the sign bit. + * A negative number indicates the Runner/BBHcreated a rounding errorBit-28 + * can be considered an overflow indication. + * Bits 27-0 are the actual number of bytes. +*/ +#define L1_SVA_BYTES_L1SSVASIZE_SHIFT 0 +#define L1_SVA_BYTES_L1SSVASIZE_MASK 0x3fffffff + + +/* + * Register - read-only + * + * Signed number of bytes in the selected L1S Un-shaped VirtualAccumulator + */ +#define EPN_L1_UVA_BYTES_REG 0x34 + +/* + * Signed number of bytes in the selected L1S Un-shaped VirtualAccumulator. + * Bit-29 is the sign bit. + * A negative number indicates the Runner/BBHcreated a rounding errorBit-28 + * can be considered an overflow indication. + * Bits 27-0 are the actual number of bytes. +*/ +#define L1_UVA_BYTES_L1SUVASIZE_SHIFT 0 +#define L1_UVA_BYTES_L1SUVASIZE_MASK 0x3fffffff + + +/* + * Register - read-only + * + * Indicates which SVAs have overflowed + */ +#define EPN_L1_SVA_OVERFLOW_REG 0x38 + +/* + * Indicates which SVAs have overflowed. + * The overflow can only becorrected by reset. +*/ +#define L1_SVA_OVERFLOW_L1SSVAOVERFLOW_SHIFT 0 +#define L1_SVA_OVERFLOW_L1SSVAOVERFLOW_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates which UVAs have overflowed + */ +#define EPN_L1_UVA_OVERFLOW_REG 0x3c + +/* + * Indicates which UVAs have overflowed. + * The overflow can only becorrected by reset. +*/ +#define L1_UVA_OVERFLOW_L1SUVAOVERFLOW_SHIFT 0 +#define L1_UVA_OVERFLOW_L1SUVAOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + * This register allows real-time forcing the per-priority report valuesto + * zero. + * This applies only to multi-priority reporting modes (CTC,NTT). + * Note: + * These bits are used for debug only. + */ +#define EPN_RESET_RPT_PRI_REG 0x40 + +/* Force priority 0 report values to zero. */ +#define RESET_RPT_PRI_NULLRPTPRIx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register allows resetting of the L2 Report FIFO pointers. + * Thecorresponding L2 accumulators are also cleared. + */ +#define EPN_RESET_L2_RPT_FIFO_REG 0x44 + +/* Set the respective bit(s) to reset L2 FIFO(s). */ +#define RESET_L2_RPT_FIFO_CFGL2SCLRQUE_SHIFT 0 +#define RESET_L2_RPT_FIFO_CFGL2SCLRQUE_MASK 0xffffffff + + +/* + * Register + * + * This register allows per-LLID enabling of upstream traffic. + * Disablingthe upstream on a particular LLID Index means that: + * 1. + * REPORT frames sent upstream on the LLID Index will report NOdata2. + * Grants on the LLID Index will be acted upon (the laser willturn on and + * any requested REPORT frame will be sent), but no userframes will be + * pulled from FIF and sent upstream. + */ +#define EPN_ENABLE_UPSTREAM_REG 0x48 + +/* Set the respective bit(s) to enable the upstream LLID(s). */ +#define ENABLE_UPSTREAM_CFGENABLEUPSTREAMREG_SHIFT 0 +#define ENABLE_UPSTREAM_CFGENABLEUPSTREAMREG_MASK 0xffffffff + + +/* + * Register - read-only + * + * Feedback register to indicate pending/complete changes in the EPNEnable + * Upstream register. + * A non-zero result from a bitwise XOR betweenthis register and EPN Enable + * Upstream indicates that a new valuewritten to EPN Enable Upstream has + * not yet taken effect. + */ +#define EPN_ENABLE_UPSTREAM_FB_REG 0x4c + +/* + * Indicates the operational state of the upstream LLIDs. + * SeeEPN_ENABLE_UPSTREAM register description for details. +*/ +#define ENABLE_UPSTREAM_FB_CFGENABLEUPSTREAMFEEDBACK_SHIFT 0 +#define ENABLE_UPSTREAM_FB_CFGENABLEUPSTREAMFEEDBACK_MASK 0xffffffff + + +/* + * Register + * + * Per-LLID index based upstream FEC enable. + * Set the bit corresponding tothe LLID index to enable FEC overhead to be + * added to the packet lengthadjustment. + * Please note that the global FEC enable in Control register1 must also be + * set. + * For 10G upstream operation, per-LLID FEC enable isnot supported; set all + * of these bits for FEC operation, and clear allof them for non-FEC. + */ +#define EPN_ENABLE_UPSTREAM_FEC_REG 0x50 + +/* Set the respective bit(s) to enable upstream FEC for LLID(s). */ +#define ENABLE_UPSTREAM_FEC_CFGENABLEUPSTREAMFEC_SHIFT 0 +#define ENABLE_UPSTREAM_FEC_CFGENABLEUPSTREAMFEC_MASK 0xffffffff + + +/* + * Register + * + * The number of bytes of 10G upstream payload that should be reserved fora + * piggy-back report. + * Note that if the "force report" is not set then this register is + * notused. + * Also, this value must be increased by 16-bytes for FEC-lessupstream 10G + * mode. + * The extra bytes are required to compensate for the10G upstream + * "scrambler sync pattern". + */ +#define EPN_REPORT_BYTE_LENGTH_REG 0x54 + +/* Number of bytes reserved for upstream report. */ +#define REPORT_BYTE_LENGTH_PRVRPTBYTELEN_SHIFT 0 +#define REPORT_BYTE_LENGTH_PRVRPTBYTELEN_MASK 0xff + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + * The Data Port Busy Interrupt indicates whether or not the data port + * isfree to do another RAM access. + * The Grant Full interrupt indicates that a grant was aborted due to + * itsgrant FIFO being full. + * The Missed Grant interrupt indicates that a grant missed its time + * totransmit and was aborted. + * This occurs from the MPCP time havingexceeded the start time when the + * grant is to be scheduled. + * (Note thatgrant start time is adjusted by the Grant Start Time Delta + * register forthis calculation)The Grant Interval interrupt indicates that + * an LLID is not receivinggates quickly enough. + * If the amount of time elapsed since receiving aGate frame exceeds a + * programmed value the interrupt will be asserted. + * See the EPON LLID Grant Interval register. + * The Discovery Gate interrupt indicates that a discovery gate + * wasreceived. + * The Local Time Not Synced interrupt is used to indicate that the + * ONU'slocal time is out of sync with EPON time. + * The time a MPCPDU framesarrives is compared with the value of its time + * stamp. + * If thisdifference is greater than value specified by the Time + * StampDifferential register the interrupt will assert. + * The Local Time Synced interrupt is used to indicate that the ONU'slocal + * time is in sync with the OLT EPON time. + * The time a MPCPDU framesarrives is compared with the value of its time + * stamp. + * If thisdifference is less than or equal to the value specified by the + * TimeStamp Differential register the interrupt will assert. + */ +#define EPN_MAIN_INT_STATUS_REG 0x58 + +/* + * Indicates the Runner/BBH aborted an upstream frame transfer. + * Pleasereference the Runner/BBH documentation for a list of events + * thatwill cause Runner/BBH to abort packets. +*/ +#define MAIN_INT_STATUS_INTBBHUPFRABORT_MASK 0x80000000 + +/* + * Coalesced per-L2 burst cap overflow event indicator. + * This istriggered when the burst cap is dynamically resized below + * respectiveL2 accumulator's value. +*/ +#define MAIN_INT_STATUS_INTCOL2SBURSTCAPOVERFLOWPRES_MASK 0x40000000 + +/* + * Coalesced Empty Report interrupt. + * One or more LLID indexes has atransmitted a report in which all time + * quanta values were zero. + * SeeEPON Empty Report Interrupt Status for per-LLID Index interruptbits. +*/ +#define MAIN_INT_STATUS_INTCOEMPTYRPT_MASK 0x20000000 + +/* + * The Drx detected an error that required the frame to be aborted. + * Culpable errors are FCS, oversize-frame, or undersize-frame. + * Note: + * The intDrxErrorAbortMask will prevent this 'coalesced bit frombeing set. + * This is in contrast to the 'individual' bits (0x41b)still being set even + * if the interrupt is masked. +*/ +#define MAIN_INT_STATUS_INTCODRXERRABORTPRES_MASK 0x10000000 + +/* + * The Level 2 structure FIFO has overflowed. + * A frame length has beenlost. + * The Runner/BBH and EPN must be reset to recover from this. +*/ +#define MAIN_INT_STATUS_INTL2SFIFOOVERRUN_MASK 0x8000000 + +/* + * Coalesced 1588 timestamp interrupt. + * SeeEPN_1588_TIMESTAMP_INT_STATUS for the interupts. +*/ +#define MAIN_INT_STATUS_INTCO1588TSINT_MASK 0x4000000 + +/* + * Coalesced Report FIFO non-empty interrupt. + * One or more LLID indiceshas a frame length present in its report FIFO. + * See EPON ReportPresent Interrupt Status for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCORPTPRES_MASK 0x2000000 + +/* + * Coalesced Grant Ready interrupt. + * One or more LLID indexes has agrant present in its Grant RAM. + * See EPON Grant Present InterruptStatus for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTPRES_MASK 0x1000000 + +/* + * Coalesced stale grant delete interrupt. + * One or more LLID indexesdeleted a grant deleted from its grant RAM. + * See EPON Deleted StaleGrant Interrupt Status for per-LLID Index + * interrupt bits. +*/ +#define MAIN_INT_STATUS_INTCODELSTALEGNT_MASK 0x800000 + +/* + * Coalesced grant non-poll interrupt. + * One or more LLID indexesexceeded the Non-poll grant interval. + * See EPON Non-Poll GrantInterrupt Status for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTNONPOLL_MASK 0x400000 + +/* + * Coalesced grant misalign interrupt. + * One or more LLID indexesreceived a grant that was not aligned on frame + * boundaries. + * See EPONGrant Misalign Interrupt Status for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTMISALIGN_MASK 0x200000 + +/* + * Coalesced grant too far abort interrupt. + * One or more LLID indexesreceived a grant for greater than 34 seconds + * into the future. + * SeeEPON Grant Too Far Interrupt Status for per-LLID Index interruptbits. + * Note: + * This interrupt can set during registration of the first LLIDIndex + * (before the local MPCP clock is synchronized to the OLT). + * Firmware should check and clear this interrupt while registering + * thefirst link. +*/ +#define MAIN_INT_STATUS_INTCOGNTTOOFAR_MASK 0x100000 + +/* + * Coalesced grant interval interrupt. + * One or more LLID indexes is notreceiving gates fast enough. + * See EPON Grant Interval InterruptStatus for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTINTERVAL_MASK 0x80000 + +/* + * Coalesced Discovery Gate received interrupt. + * One or more LLIDindexes received a Discovery Gate. + * See EPON Discovery Gate InterruptStatus for per-LLID Index interrupt + * bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTDISCOVERY_MASK 0x40000 + +/* + * Coalesced grant miss abort interrupt. + * One or more LLID indexesaborted a grant because it missed its slot time + * to transmit. + * SeeEPON Grant Miss Interrupt Status for per-LLID Index interrupt bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTMISSABORT_MASK 0x20000 + +/* + * Coalesced grant full abort interrupt. + * One or more LLID indexesaborted a grant due to its grant FIFO being + * full. + * See EPON GrantFull Interrupt Status for per-LLID Index interrupt bits. +*/ +#define MAIN_INT_STATUS_INTCOGNTFULLABORT_MASK 0x10000 + +/* + * [FATAL] The EPN received an upstream frame whose length did notmatch the + * expected frame length. + * This is a fatal event. + * The entiredata path must be reset to recover from this event. +*/ +#define MAIN_INT_STATUS_INTBADUPFRLEN_MASK 0x8000 + +/* + * The Runner/BBH upstream data path failed to deliver upstream data intime + * to meet the upPacketTxMargin requirement. +*/ +#define MAIN_INT_STATUS_INTUPTARDYPACKET_MASK 0x4000 + +/* Report frame has been transmitted by EPON MAC. */ +#define MAIN_INT_STATUS_INTUPRPTFRXMT_MASK 0x2000 + +/* + * [FATAL] The burst information FIFO over ran. + * This is a fatal eventand requires the entire device to be reset and + * re-initialized. +*/ +#define MAIN_INT_STATUS_INTBIFIFOOVERRUN_MASK 0x1000 + +/* + * A grant passed to the Upstream transmitter has size greater thanthat + * defined EPON Max Grant Size register. +*/ +#define MAIN_INT_STATUS_INTBURSTGNTTOOBIG_MASK 0x800 + +/* + * A grant written into EPON grant RAM has size greater than thatdefined + * EPON Max Grant Size register. +*/ +#define MAIN_INT_STATUS_INTWRGNTTOOBIG_MASK 0x400 + +/* + * A grant received by EPON MAC has size greater than that defined inthe + * EPON Max Grant Size register. +*/ +#define MAIN_INT_STATUS_INTRCVGNTTOOBIG_MASK 0x200 + +/* + * EPON block cannot accumulate statistics quickly enough to count + * runtframes. + * Bursts of frames less than 20 bytes in size will cause thisinterrupt. +*/ +#define MAIN_INT_STATUS_INTDNSTATSOVERRUN_MASK 0x100 + +/* EPON block was not able to process an upstream transmission event. */ +#define MAIN_INT_STATUS_INTUPSTATSOVERRUN_MASK 0x80 + +/* An out of order grant was received */ +#define MAIN_INT_STATUS_INTDNOUTOFORDER_MASK 0x40 + +/* + * [FATAL] Fatal Event. + * The Runner/BBH upstream data path stoppeddelivering packets. + * All upstream traffic for all LLID indexes hasbeen halted. + * Any upstream grants received are terminated with emptyreports (if + * requested). + * The only way to recover from this fatalevent is to reset the entire + * upstream data path. + * Check the EPN Fatal Upstream Fault Interrupt Status register to seewhich + * LLID(s) experienced the fault. +*/ +#define MAIN_INT_STATUS_INTTRUANTBBHHALT_MASK 0x20 + +/* + * Grant length is less than overhead. + * Possible configuration error. +*/ +#define MAIN_INT_STATUS_INTUPINVLDGNTLEN_MASK 0x10 + +/* + * [FATAL] Coalesced per-LLID index Runner/BBH fatal upstream deliveryfault + * indicator. + * Runner/BBH has lost coherency with the EPN. + * Thefour trigger events are: + * 1. + * Runner/BBH aborted a packet2. + * Runner/BBH transferred a packet shorter than was requested3. + * Runner/BBH transferred a packet longer than was requested4. + * Runner/BBH stopped transferring packets (as indicated + * byintTruantBbhHalt, below)Check the EPN Fatal Upstream Fault Interrupt + * Status register to seewhich LLID(s) experienced the fault. +*/ +#define MAIN_INT_STATUS_INTCOBBHUPSFAULT_MASK 0x8 + +/* ONU timer is in sync */ +#define MAIN_INT_STATUS_INTDNTIMEINSYNC_MASK 0x4 + +/* ONU timer is out of sync */ +#define MAIN_INT_STATUS_INTDNTIMENOTINSYNC_MASK 0x2 + +/* + * EPON Data Port is ready0: + * Data Port is busy1: + * Data Port is ready +*/ +#define MAIN_INT_STATUS_INTDPORTRDY_MASK 0x1 + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_FULL_INT_STATUS_REG 0x5c + +/* LLID index 0 aborted a grant due to its grant FIFO being full. */ +#define GNT_FULL_INT_STATUS_INTDNGNTFULLABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_FULL_INT_MASK_REG 0x60 + +/* + * Mask LLID index 0 aborted a grant due to its grant FIFO being + * fullinterrupt. +*/ +#define GNT_FULL_INT_MASK_MASKINTDNGNTFULLABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_MISS_INT_STATUS_REG 0x64 + +/* LLID index 0 aborted a grant because it missed its slot time totransmit. */ +#define GNT_MISS_INT_STATUS_INTDNGNTMISSABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_MISS_INT_MASK_REG 0x68 + +/* + * Mask LLID index 0 aborted a grant because it missed its slot time + * totransmit interrupt. +*/ +#define GNT_MISS_INT_MASK_MASKINTDNGNTMISSABORTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_DISC_RX_INT_STATUS_REG 0x6c + +/* LLID index 0 received a discovery gate */ +#define DISC_RX_INT_STATUS_INTDNGNTDISCOVERYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_DISC_RX_INT_MASK_REG 0x70 + +/* Mask LLID index 0 received a discovery gate interrupt. */ +#define DISC_RX_INT_MASK_MASKINTDNGNTDISCOVERYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_INTV_INT_STATUS_REG 0x74 + +/* + * LLID index 0 failed to receive a GATE within a time period definedby the + * EPN Grant Interval register. +*/ +#define GNT_INTV_INT_STATUS_INTDNGNTINTERVALx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_INTV_INT_MASK_REG 0x78 + +/* + * Mask LLID index 0 failed to receive a GATE within a time perioddefined + * by the EPN Grant Interval register interrupt. +*/ +#define GNT_INTV_INT_MASK_MASKINTDNGNTINTERVALx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_FAR_INT_STATUS_REG 0x7c + +/* + * LLID index 0 received (and aborted) a grant with a start timegreater + * than 34 sec in the future +*/ +#define GNT_FAR_INT_STATUS_INTDNGNTTOOFARx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_FAR_INT_MASK_REG 0x80 + +/* + * Mask LLID index 0 received (and aborted) a grant with a start + * timegreater than 34 sec in the future interrupt +*/ +#define GNT_FAR_INT_MASK_MASKDNGNTTOOFARx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_GNT_MISALGN_INT_STATUS_REG 0x84 + +/* LLID index 0 received a misaligned grant */ +#define GNT_MISALGN_INT_STATUS_INTDNGNTMISALIGNx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_MISALGN_INT_MASK_REG 0x88 + +/* Mask LLID index 0 received a misaligned grant interrupt */ +#define GNT_MISALGN_INT_MASK_MASKINTDNGNTMISALIGNx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_NP_GNT_INT_STATUS_REG 0x8c + +/* Non poll grant interval exceeded on LLID Index 0 */ +#define NP_GNT_INT_STATUS_INTDNGNTNONPOLLx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_NP_GNT_INT_MASK_REG 0x90 + +/* Non poll grant interval exceeded on LLID Index 0 interrupt mask */ +#define NP_GNT_INT_MASK_MASKDNGNTNONPOLLx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_DEL_STALE_INT_STATUS_REG 0x94 + +/* Stale grant deleted from LLID Index 0 grant RAM. */ +#define DEL_STALE_INT_STATUS_INTDELSTALEGNTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * Interrupt mask for EPN_DEL_STALE_INT_STATUS + */ +#define EPN_DEL_STALE_INT_MASK_REG 0x98 + +/* Stale grant deleted from LLID Index 0 grant RAM interrupt mask. */ +#define DEL_STALE_INT_MASK_MASKINTDELSTALEGNTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write a 1 to it. + */ +#define EPN_GNT_PRES_INT_STATUS_REG 0x9c + +/* Grant present in LLID Index 0 grant RAM */ +#define GNT_PRES_INT_STATUS_INTDNGNTRDYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_GNT_PRES_INT_MASK_REG 0xa0 + +/* Grant present in LLID Index 0 grant RAM interrupt mask */ +#define GNT_PRES_INT_MASK_MASKDNGNTRDYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the EPON module. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_RPT_PRES_INT_STATUS_REG 0xa4 + +/* Frame length present in LLID Index 0 report FIFO */ +#define RPT_PRES_INT_STATUS_INTUPRPTFIFOx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module. + */ +#define EPN_RPT_PRES_INT_MASK_REG 0xa8 + +/* Frame length present in LLID Index 0 report FIFO interrupt mask */ +#define RPT_PRES_INT_MASK_MASKINTUPRPTFIFOx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status for the Drx error abort events. + * These bits are sticky; to clear a bit, write 1 to it. + */ +#define EPN_DRX_ABORT_INT_STATUS_REG 0xac + +/* + * The Drx detected an error that required an LLID Index 0-31 + * (bitwise)frame be aborted in the RDP +*/ +#define DRX_ABORT_INT_STATUS_INTDRXERRABORT_SHIFT 0 +#define DRX_ABORT_INT_STATUS_INTDRXERRABORT_MASK 0xffffffff + + +/* + * Register + * + * This register contains interrupt mask for the Drx error abort events. + */ +#define EPN_DRX_ABORT_INT_MASK_REG 0xb0 + +/* + * Mask the Drx detected an error that required an LLID Index 0-31(bitwise) + * frame be aborted in the RDP interrupt. +*/ +#define DRX_ABORT_INT_MASK_MASKINTDRXERRABORT_SHIFT 0 +#define DRX_ABORT_INT_MASK_MASKINTDRXERRABORT_MASK 0xffffffff + + +/* + * Register + * + * This register contains interrupt status for the EPON module's + * emptyreport transmission. + * Any time the EPON module sends a report upstreamand all the report + * values are zero, the bit corresponding to the LLIDindex will be set. + * These bits are sticky; to clear a bit, write 1 toit. + */ +#define EPN_EMPTY_RPT_INT_STATUS_REG 0xb4 + +/* Time quanta values present in LLID Index 0 report were all zero. */ +#define EMPTY_RPT_INT_STATUS_INTEMPTYRPTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt mask for the EPON module's emptyreport + * transmission. + * Any time the EPON module sends a report upstreamand all the report + * values are zero, the bit corresponding to the LLIDindex will be set. + */ +#define EPN_EMPTY_RPT_INT_MASK_REG 0xb8 + +/* + * Mask time quanta values present in LLID Index 0 report were all + * zerointerrupt. +*/ +#define EMPTY_RPT_INT_MASK_MASKINTEMPTYRPTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * This register contains interrupt status indicating when the + * L2accumulators exceed their burst-cap values. + * These bits are sticky; toclear a bit, write 1 to it. + */ +#define EPN_BCAP_OVERFLOW_INT_STATUS_REG 0xbc + +/* + * Indicates that the L2 accumulator 0-31 (bitwise) has exceeded itsburst + * cap value. +*/ +#define BCAP_OVERFLOW_INT_STATUS_INTL2SBURSTCAPOVERFLOW_SHIFT 0 +#define BCAP_OVERFLOW_INT_STATUS_INTL2SBURSTCAPOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + * This register contains interrupt mask indicating when the L2accumulators + * exceed their burst-cap values. + */ +#define EPN_BCAP_OVERFLOW_INT_MASK_REG 0xc0 + +/* + * Mask interrupt indicating that the L2 accumulator 0-31 (bitwise) + * hasexceeded its burst cap value. +*/ +#define BCAP_OVERFLOW_INT_MASK_MASKINTL2SBURSTCAPOVERFLOW_SHIFT 0 +#define BCAP_OVERFLOW_INT_MASK_MASKINTL2SBURSTCAPOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define EPN_BBH_DNS_FAULT_INT_STATUS_REG 0xc4 + +/* + * Indicates the downstream BBH interface failed to transfer thedownstream + * fast enough. + * This occurs when the Epn dropped adownstream packet (sent abort). +*/ +#define BBH_DNS_FAULT_INT_STATUS_INTBBHDNSOVERFLOW_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_BBH_DNS_FAULT_INT_MASK_REG 0xc8 + +/* Mask downstream BBH data path overflow interrupt. */ +#define BBH_DNS_FAULT_INT_MASK_MASKINTBBHDNSOVERFLOW_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_BBH_UPS_FAULT_INT_STATUS_REG 0xcc + +/* + * Indicates upstream LLID index 0 has lost coherency with theRunner/BBH. + * This condition can be recovered by resetting the datapath associated + * with the LLID index. + * Note: + * Do not clear these interrupts until the LLID index data pathhas been + * reset or the LLID index's upstream traffic has beendisabled using 'EPN + * Enable Upstream' register. +*/ +#define BBH_UPS_FAULT_INT_STATUS_INTBBHUPSFAULTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + */ +#define EPN_BBH_UPS_FAULT_INT_MASK_REG 0xd0 + +/* + * Mask upstream LLID index 0 has lost coherency with the + * Runner/BBHinterrupt. +*/ +#define BBH_UPS_FAULT_INT_MASK_MASKINTBBHUPSFAULTx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + */ +#define EPN_BBH_UPS_ABORT_INT_STATUS_REG 0xd4 + +/* + * [FATAL] This bit indicates that BBH aborted an upstream packet at atime + * it was considered tardy by EPN. + * It is valid only if bit 31 ofregister 0x4b0 (fatalTardyBbhAbortEn) is + * set. + * 0: + * BBH has not aborted a tardy upstream packet. + * 1: + * BBH has aborted a tardy upstream packet. + * All upstream datatraffic has been disabled. + * EPN must be reset to recover from thiscondition. +*/ +#define BBH_UPS_ABORT_INT_STATUS_TARDYBBHABORT_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_BBH_UPS_ABORT_INT_MASK_REG 0xd8 + +/* + * Mask BBH aborted an upstream packet at a time it was consideredtardy by + * EPN interrupt. +*/ +#define BBH_UPS_ABORT_INT_MASK_MASKTARDYBBHABORT_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_MAIN_INT_MASK_REG 0xdc + +#define MAIN_INT_MASK_BBHUPFRABORTMASK_MASK 0x80000000 +#define MAIN_INT_MASK_INTL2SBURSTCAPOVERFLOWMASK_MASK 0x40000000 +#define MAIN_INT_MASK_INTCOEMPTYRPTMASK_MASK 0x20000000 +#define MAIN_INT_MASK_INTDRXERRABORTMASK_MASK 0x10000000 +#define MAIN_INT_MASK_INTL2SFIFOOVERRUNMASK_MASK 0x8000000 +#define MAIN_INT_MASK_INTCO1588TSMASK_MASK 0x4000000 +#define MAIN_INT_MASK_INTCORPTPRESMASK_MASK 0x2000000 +#define MAIN_INT_MASK_INTCOGNTPRESMASK_MASK 0x1000000 +#define MAIN_INT_MASK_INTCODELSTALEGNTMASK_MASK 0x800000 +#define MAIN_INT_MASK_INTCOGNTNONPOLLMASK_MASK 0x400000 +#define MAIN_INT_MASK_INTCOGNTMISALIGNMASK_MASK 0x200000 +#define MAIN_INT_MASK_INTCOGNTTOOFARMASK_MASK 0x100000 +#define MAIN_INT_MASK_INTCOGNTINTERVALMASK_MASK 0x80000 +#define MAIN_INT_MASK_INTCOGNTDISCOVERYMASK_MASK 0x40000 +#define MAIN_INT_MASK_INTCOGNTMISSABORTMASK_MASK 0x20000 +#define MAIN_INT_MASK_INTCOGNTFULLABORTMASK_MASK 0x10000 +#define MAIN_INT_MASK_BADUPFRLENMASK_MASK 0x8000 +#define MAIN_INT_MASK_UPTARDYPACKETMASK_MASK 0x4000 +#define MAIN_INT_MASK_UPRPTFRXMTMASK_MASK 0x2000 +#define MAIN_INT_MASK_INTBIFIFOOVERRUNMASK_MASK 0x1000 +#define MAIN_INT_MASK_BURSTGNTTOOBIGMASK_MASK 0x800 +#define MAIN_INT_MASK_WRGNTTOOBIGMASK_MASK 0x400 +#define MAIN_INT_MASK_RCVGNTTOOBIGMASK_MASK 0x200 +#define MAIN_INT_MASK_DNSTATSOVERRUNMASK_MASK 0x100 +#define MAIN_INT_MASK_INTUPSTATSOVERRUNMASK_MASK 0x80 +#define MAIN_INT_MASK_DNOUTOFORDERMASK_MASK 0x40 +#define MAIN_INT_MASK_TRUANTBBHHALTMASK_MASK 0x20 +#define MAIN_INT_MASK_UPINVLDGNTLENMASK_MASK 0x10 +#define MAIN_INT_MASK_INTCOBBHUPSFAULTMASK_MASK 0x8 +#define MAIN_INT_MASK_DNTIMEINSYNCMASK_MASK 0x4 +#define MAIN_INT_MASK_DNTIMENOTINSYNCMASK_MASK 0x2 +#define MAIN_INT_MASK_DPORTRDYMASK_MASK 0x1 + +/* + * Register + * + * The Maximum Grant Size register sets the threshold for the three + * GrantToo Big interrupts (in the EPN Main Interrupt Status register). + */ +#define EPN_MAX_GNT_SIZE_REG 0xe0 + +/* + * Sets the Grant Size threshold for the three Grant Too Biginterrupts. + * Units are TQ. +*/ +#define MAX_GNT_SIZE_MAXGNTSIZE_SHIFT 0 +#define MAX_GNT_SIZE_MAXGNTSIZE_MASK 0xffff + + +/* + * Register + * + * Provisions the maximum allowable downstream frame size. + * The resetdefault is 1536. + * This register is overridden by the cfgVlanMaxSize bit. + * The maximum allowable value for this register is 2000 in 1G/2G mode + * and10000 in 10G mode. + */ +#define EPN_MAX_FRAME_SIZE_REG 0xe4 + +/* + * Maximum allowable downstream frame size. + * Frames larger than thisvalue are discarded. +*/ +#define MAX_FRAME_SIZE_CFGMAXFRAMESIZE_SHIFT 0 +#define MAX_FRAME_SIZE_CFGMAXFRAMESIZE_MASK 0x3fff + + +/* + * Register + * + * Defines how much of the grant length is consumed by laser on time,laser + * off time, and idle (sync) time. + * This value is subtracted from thegrant length and the remainder is used + * to fill frames from FIF queuesinto the upstream burst. + * This register is used in both 1G and 10Gupstream modes. + * The units are in TQ. + * Reset default is 0. + * NOTE: + * In 10G mode the Xif requires 2 extra TimeQuanta for "Eob". + * Also,in FECless 10G mode the Epn's "Report Byte Length" must have an + * extra16-bytes added to its value to account for 10G "scrambler sync + * time". + */ +#define EPN_GRANT_OVR_HD_REG 0xe8 + +/* + * 1G upstream mode -> Grant length consumed by overhead when FEC + * isenabled. + * 10G upstream mode -> Not used. +*/ +#define GRANT_OVR_HD_GNTOVRHDFEC_SHIFT 16 +#define GRANT_OVR_HD_GNTOVRHDFEC_MASK 0xffff0000 + +/* + * 1G upstream mode -> Grant length consumed by overhead when FEC + * isdisabled. + * 10G upstream mode -> Grant length consumed by overhead. + * Used forboth FEC and FEC-less modes. +*/ +#define GRANT_OVR_HD_GNTOVRHD_SHIFT 0 +#define GRANT_OVR_HD_GNTOVRHD_MASK 0xffff + + +/* + * Register + * + * Sets the size of polling grants for the purpose of generating + * thednGntNonPoll interrupts. + * If a received grant's length, less EPN GrantLength Overhead, is less + * than or equal to the poll size, the grant isconsidered a poll and resets + * the poll grant interval timer for the LLIDIndex. + * Reset default is 64 decimal. + */ +#define EPN_POLL_SIZE_REG 0xec + +/* + * Size of polling grants when FEC is enabled. + * Units are TQ. + * Defaultsto 64. +*/ +#define POLL_SIZE_POLLSIZEFEC_SHIFT 16 +#define POLL_SIZE_POLLSIZEFEC_MASK 0xffff0000 + +/* + * Size of polling grants when FEC is disabled. + * Units are TQ. + * Defaultsto 64. +*/ +#define POLL_SIZE_POLLSIZE_SHIFT 0 +#define POLL_SIZE_POLLSIZE_MASK 0xffff + + +/* + * Register + * + * This register determines how far in advance of the Grant Start Timethat + * grants are considered for removal from the DRX Grant FIFO. + * Once agrant is chosen (the various LLID Indexes compete for the next + * burstslot - the Index with a grant that is within Read Grant Margin + * andclosest to its Grant Start Time wins), it is popped from its grant + * FIFOand held until it meets the Grant Start Time Delta criteria + * (seebelow). + * The units of this register are TQ. + * The reset default value is 256decimal. + */ +#define EPN_DN_RD_GNT_MARGIN_REG 0xf0 + +/* + * How far in advance of Grant Start Time to consider a grant forremoval + * from the grant FIFO. +*/ +#define DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_SHIFT 0 +#define DN_RD_GNT_MARGIN_RDGNTSTARTMARGIN_MASK 0xffff + + +/* + * Register + * + * This value determines how far in advance of the Grant Start Time thatthe + * next selected grant (already extracted from the Grant FIFO) will + * behanded to the EPN UTX (upstream transmit) logic and start to + * pre-fetchframes. + * .The units of this register are TQ. + * The reset default value is 640decimal. + */ +#define EPN_GNT_TIME_START_DELTA_REG 0xf4 + +/* + * This value determines how far in advance of the Grant Start Timethat the + * next selected grant (already extracted from the Grant FIFO)will be + * handed to the EPN UTX (upstream transmit) logic and start topre-fetch + * frames. + * .The units of this register are TQ. + * The reset default value is 640decimal. +*/ +#define GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_SHIFT 0 +#define GNT_TIME_START_DELTA_GNTSTARTTIMEDELTA_MASK 0xffff + + +/* + * Register + * + * This register sets a threshold for + * LocalTimeInSync/LocalTimeNotSyncinterrupts, and for local time reference + * updates. + * When the differencebetween the EPON MAC's local time and an MPCPDU's + * timestamp exceedsthis value the LocalTimeNotSync interrupt is asserted. + * The units ofthis register are TQ. + * Reset default is 10 decimal. + */ +#define EPN_TIME_STAMP_DIFF_REG 0xf8 + +/* + * Threshold for local time reference updates and related interrupts. + * Reset default is10 decimal. +*/ +#define TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_SHIFT 0 +#define TIME_STAMP_DIFF_TIMESTAMPDIFFDELTA_MASK 0xffff + + +/* + * Register + * + * This register helps determine the value for the Timestamp fieldinserted + * into REPORT and Processor frames. + * This value specifies anoffset from the Grant Start Time of the upstream + * burst. + * The valueprogrammed here will be roughly equivalent to the sum of + * Laser-On timeplus IDLE time plus Preamble time. + * The goal is for the Timestampinserted into a frame to match the MPCP + * time at which the first byte ofthe frame's Destination Address is + * transmitted. + */ +#define EPN_UP_TIME_STAMP_OFF_REG 0xfc + +/* + * Offset from Grant Start Time to use as the Timestamp field inREPORTs and + * processor-sent packets when FEC is enabled. + * Only used for 1G modes. + * Units are TQ. +*/ +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSETFEC_SHIFT 16 +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSETFEC_MASK 0xffff0000 + +/* + * Offset from Grant Start Time to use as the Timestamp field inREPORTs and + * processor-sent packets when FEC is disabled. + * Used for both 1G no FEC and all 10G modes. + * Units are TQ. +*/ +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSET_SHIFT 0 +#define UP_TIME_STAMP_OFF_TIMESTAMPOFFSET_MASK 0xffff + + +/* + * Register + * + * This register specifies the maximum allowed time between GATE + * messagesreceived on an LLID. + * If the time elapsed is greater than the specifiedvalue, the Gate + * Interval interrupt asserts for that LLID Index. + * Theunits of this register are 262 us. + * The maximum interval is ~17 seconds. + */ +#define EPN_GNT_INTERVAL_REG 0x100 + +/* Grant interval */ +#define GNT_INTERVAL_GNTINTERVAL_SHIFT 0 +#define GNT_INTERVAL_GNTINTERVAL_MASK 0xffff + + +/* + * Register + * + * Sets the threshold for misalignment detection and handling. + * A grant misalignment condition is detected by the ONU whenever a grantto + * the ONU cannot be used efficiently (due to the grant size notaligning to + * even frame boundaries). + * When cfgGntMisalignX bits are set, the ONU uses this register + * todetermine a misalignment condition and to take corrective action. + * prvUnusedGntThresh determines how many unused TQ there must be in agiven + * grant in order for it to be considered misaligned. + * gntMisalignThresh indicates how many consecutive misaligned grants + * mustbe received in order to trigger handling of this condition. + * The ONU handles the misaligned condition by temporarily reporting 0("no + * data") in that LLID's REPORT frames. + */ +#define EPN_DN_GNT_MISALIGN_THR_REG 0x104 + +/* + * Sets the minimum number of unused time quanta in a grant required + * inorder for it to be considered misaligned. +*/ +#define DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_SHIFT 16 +#define DN_GNT_MISALIGN_THR_PRVUNUSEDGNTTHRESHOLD_MASK 0xffff0000 + +/* + * Sets the number of misaligned grants needed to trigger + * misalignmenthandling. + * The value set here is one fewer than the desired number ofconsecutive + * misaligned grants, i. + * e. + * setting a value of 2 means thatthree misaligned grants in a row will + * trigger misalignment handling. +*/ +#define DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_SHIFT 0 +#define DN_GNT_MISALIGN_THR_GNTMISALIGNTHRESH_MASK 0x3ff + + +/* + * Register + * + * Indicates for how long after the misalignment condition is detectedthat + * the LLID Index's reporting will be "paused". + * This is achievedthrough reporting queue report values of zero. + * Units are 1 us. + */ +#define EPN_DN_GNT_MISALIGN_PAUSE_REG 0x108 + +/* How long to stall reporting of queue status. */ +#define DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_SHIFT 0 +#define DN_GNT_MISALIGN_PAUSE_GNTMISALIGNPAUSE_MASK 0xffff + + +/* + * Register + * + * Defines the amount of time required for triggering the non poll + * grantinterrupts. + */ +#define EPN_NON_POLL_INTV_REG 0x10c + +/* + * If amount of time since last non poll grant exceed this value, + * therespective LLID's interrupt will assert. + * Units of 65 us. +*/ +#define NON_POLL_INTV_NONPOLLGNTINTV_SHIFT 0 +#define NON_POLL_INTV_NONPOLLGNTINTV_MASK 0xffff + + +/* + * Register + * + * Forces upstream FCS errors on the selected LLID(s). + */ +#define EPN_FORCE_FCS_ERR_REG 0x110 + +/* Force bad FCS for frames transmitting out of LLID 0 */ +#define FORCE_FCS_ERR_FORCEFCSERRx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + * Defines how much overlap is allowed between consecutive grants to + * thesame ONU. + * Effectively this register defines how much of the grantoverhead the Epn + * should attempt to recover when processing overlappedgrants. + * Normally this register is provisioned with the same value as inthe EPN + * Grant Overhead Length register. + * However, if the Xif or Lifrequire extra overhead not associated with + * Lon/Sync/Loff, then thisregister value must be smaller than the EPN + * Grant Overhead Lengthregister value. + * This register is used in both 1G and 10G upstream modes. + * The units arein TQ. + * Reset default is 0. + * NOTE: + * In 10G upstream mode this register must be provisioned to matchthe value + * written to the XIF Overlapping Grant Overhead register(0x0364). + * The proper value is calculated as: + * EPN Grant Overlap Limit = Lon + Sync Time + Loff - 1 (start of burst) -1 + * (Idle Sync) - 3 (XIF Overlapping Grant Overhead). + */ +#define EPN_GRANT_OVERLAP_LIMIT_REG 0x114 + +/* + * Number of time quanta by which two consecutive grants are allowed + * tooverlap +*/ +#define GRANT_OVERLAP_LIMIT_PRVGRANTOVERLAPLIMIT_SHIFT 0 +#define GRANT_OVERLAP_LIMIT_PRVGRANTOVERLAPLIMIT_MASK 0xffff + + +/* + * Register + * + * Allows control over reporting the extra per-packet overhead + * associatedwith 802. + * 1AE encryption. + * The AES overhead compensation logic supportstwo overhead modes: + * implicit SCI and explicit SCI. + * The implicit SCImode increases the per-packet overhead by 24 bytes. + * Explicit SCI modeincreases the per-packet overhead by 32 bytes. + */ +#define EPN_AES_CFG_0_REG 0x118 + +/* + * LLID index 0 AES overhead mode. + * 0: + * Implicit SCI AES overhead mode. + * 1: + * Explicit SCI AES overhead mode. + * .. + * LLID index 15 AES overhead mode. + * 30: + * Implicit SCI AES overhead mode. + * 31: + * Explicit SCI AES overhead mode. +*/ +#define AES_CFG_0_PRVUPSTREAMAESMODE_0_SHIFT 0 +#define AES_CFG_0_PRVUPSTREAMAESMODE_0_MASK 0xffffffff + + +/* + * Register + * + * The amount of overhead used in discovery gates. + */ +#define EPN_DISC_GRANT_OVR_HD_REG 0x11c + +/* + * This defines the amount of overhead used for Discovery gates. + * Unitsare 16-bit words. +*/ +#define DISC_GRANT_OVR_HD_DISCGNTOVRHD_SHIFT 0 +#define DISC_GRANT_OVR_HD_DISCGNTOVRHD_MASK 0xffff + + +/* + * Register + * + * Serves as the seed for generating the random offset during + * discoverygates. + * When this register is written the discovery random offset becomethis + * value + */ +#define EPN_DN_DISCOVERY_SEED_REG 0x120 + +/* + * Specifies basis for generating the discovery offset. + * Units are TQ. +*/ +#define DN_DISCOVERY_SEED_CFGDISCSEED_SHIFT 0 +#define DN_DISCOVERY_SEED_CFGDISCSEED_MASK 0xfff + + +/* + * Register + * + * Sets the amount by which the discovery random offset is incremented. + */ +#define EPN_DN_DISCOVERY_INC_REG 0x124 + +/* Units are TQ */ +#define DN_DISCOVERY_INC_CFGDISCINC_SHIFT 0 +#define DN_DISCOVERY_INC_CFGDISCINC_MASK 0x3ff + + +/* + * Register + * + * Size of the grant for responses to Discovery Gates. + * When a DiscoveryGate is received from the PON, EPN substitutes this + * value into thegrant length as the grant goes into the Grant FIFO. + * Normally, the valueset in this register will be 42 greater than what is + * set in EPNDiscovery Gate Overhead. + */ +#define EPN_DN_DISCOVERY_SIZE_REG 0x128 + +/* + * Size of response to discovery gate. + * Units are TQ. +*/ +#define DN_DISCOVERY_SIZE_CFGDISCSIZE_SHIFT 0 +#define DN_DISCOVERY_SIZE_CFGDISCSIZE_MASK 0xffff + + +/* + * Register + * + * Specifies the IPG and REPORT frame sizes used in computating + * reportedvalues. + * cfgRptLen and cfgFecRptLen are also used to qualify grantlengths and + * generate the intInvGntLength interrupt. + * Note the operating modes in which each of these fields is used: + * cfgFecIpgLength - Used only in 1G upstream FEC. + * Note 8-bytes ofoverhead are built in to the Epn's 1G upstream FEC + * calculations. + * cfgFecRptLen - Used only in 1G upstream, for LLIDs which areFEC-enabled. + * cfgRptLen - Used in 1G upstream for non-FEC LLIDs. + * Also used in 10Gupstream, whether or not FEC is enabled (FEC is global + * at 10Gupstream). + */ +#define EPN_FEC_IPG_LENGTH_REG 0x12c + +/* + * 10G and 1G upstream: + * The number of the bytes in the sum of IPG +PREAMBLE. + * This value must be programmed before the upstream isenabled. + * It must not be modified while the upstream is active. + * Default is 20. + * Units are bytes. +*/ +#define FEC_IPG_LENGTH_MODIPGPREAMBLEBYTES_SHIFT 24 +#define FEC_IPG_LENGTH_MODIPGPREAMBLEBYTES_MASK 0x1f000000 + +/* + * 1G upstream non-FEC: + * The length of the REPORT Frame + IPG +PREAMBLE. + * Used for non-FEC LLIDs. + * Use default value of 42. + * 10G upstream FEC : + * The length of the Report Frame + IPG + PREAMBLE +FEC. + * Set to 13. + * 10G upstream non-FEC : + * The length of the Report Frame + IPG +PREAMBLE. + * Set to 5. + * Defaults to 42 for 1G non-FEC. + * Units are TQ. +*/ +#define FEC_IPG_LENGTH_CFGRPTLEN_SHIFT 16 +#define FEC_IPG_LENGTH_CFGRPTLEN_MASK 0xff0000 + +/* + * The length of the REPORT Frame + IPG + PREAMBLE + FEC. + * Used only for1G FEC upstream operation. + * Default is 58 for 1G upstream FEC. + * Units are TQ. +*/ +#define FEC_IPG_LENGTH_CFGFECRPTLENGTH_SHIFT 8 +#define FEC_IPG_LENGTH_CFGFECRPTLENGTH_MASK 0xff00 + +/* + * Length of IPG to be used in 1G upstream FEC computations. + * There are8-bytes of overhead built into the Epn's 1G upstream + * FECcalculations. + * This means that if this register is set to zero then the Epn willadd + * 8-bytes of overhead to each packet transmitted upstream. + * The size of the 1G upstream FEC IPG+preamble used by the Epn + * is(cfgFecIpgLength + 8). + * The smallest supported FEC IPG+preamble value is 8. + * To use theLIF's short preamble (7-byte minimum) capability; set the + * LIF's IPGvalue to 1 and set the Epn's cfgFecIpgLength to 0. + * Default 10. + * Units are bytes. +*/ +#define FEC_IPG_LENGTH_CFGFECIPGLENGTH_SHIFT 0 +#define FEC_IPG_LENGTH_CFGFECIPGLENGTH_MASK 0xff + + +/* + * Register + * + * Enables a mode in which an LLID Index falsely reports that it has + * data,even when it does not. + * This mode is enabled per-LLID Index. + * Enablingthis mode for an LLID Index causes it to report the value set in + * EPNFake Report Value, regardless of any actual data that is in + * itsassociated queue(s). + */ +#define EPN_FAKE_REPORT_VALUE_EN_REG 0x130 + +/* + * Per-LLID Index bits for enabling fake reporting. + * Setting a bit willcause that Index to send fake reports (when requested + * by a ForceReport grant) with the value specified in EPN Fake Report + * Value. +*/ +#define FAKE_REPORT_VALUE_EN_FAKEREPORTVALUEEN_SHIFT 0 +#define FAKE_REPORT_VALUE_EN_FAKEREPORTVALUEEN_MASK 0xffffffff + + +/* + * Register + * + * Specifies the value sent in fake reports. + */ +#define EPN_FAKE_REPORT_VALUE_REG 0x134 + +/* + * The value to be used when sending fake reports. + * This value is inunits of bytes. + * (This value is converted to TQ as necessary for theconfigured upstream + * data rate. + * ) +*/ +#define FAKE_REPORT_VALUE_FAKEREPORTVALUE_SHIFT 0 +#define FAKE_REPORT_VALUE_FAKEREPORTVALUE_MASK 0x1fffff + + +/* + * Register + * + * Specifies which of the first 16 MPCP opcode values should have theirMPCP + * time overwritten. + * Opcode values 0 and 1 are always disabled. + * The14 MPCP opcode values in the range of 2-15 can be enabled by + * settingthe corresponding bit. + * The reset default value is 0x0058. + */ +#define EPN_VALID_OPCODE_MAP_REG 0x178 + +/* + * The 14 MPCP opcode values in the range of 2-15 can be enabled bysetting + * the corresponding bit. + * Note: + * Opcode values 0 and 1 must always be disabled! +*/ +#define VALID_OPCODE_MAP_PRVVALIDMPCPOPCODES_SHIFT 0 +#define VALID_OPCODE_MAP_PRVVALIDMPCPOPCODES_MASK 0xffff + + +/* + * Register + * + * Specifies the setup time margin for upstream data transfers to LIF. + * This margin is used to police the arrival time of data from + * theRunner/BBH upstream data path. + * If BBH fails to deliver (any part of) apacket in time, EPON inserts a + * "fake packet" into the upstream burst tosubstitute for the + * late-delivered packet. + * When the actual packet iseventually delivered from BBH, EPON discards + * it. + * Fake packets arezero-padded and contain a guaranteed-bad FCS. + * The upPacketTxMargin value needs to be larger than the upstream datapath + * latency. + * The upstream data path latency is composed of LIF datapath delay + MPCP + * time jitter + EPN data path delay (upTimeStampOff +42 + 1 + 10). + * Please note that EPN's 10 TQ upstream data path latencyincludes 3 TQ for + * the LIF to respond to valid data on the upstreamEPN-to-LIF interface, + * and LIF's upstream data path latency includes theprovisioned + * upTimeStampOff value. + * This is because the LIF does notprocess a grant until it receives data + * from the EPN. + * So, the initialpacket data must arrive 42 time quanta before the Grant + * Start Time. + */ +#define EPN_UP_PACKET_TX_MARGIN_REG 0x17c + +/* + * Minimum upstream data setup time for LIF/XIF. + * Units are TQ. +*/ +#define UP_PACKET_TX_MARGIN_UPPACKETTXMARGIN_SHIFT 0 +#define UP_PACKET_TX_MARGIN_UPPACKETTXMARGIN_MASK 0xffff + + +/* + * Register + * + * This register configures Multi-Priority reporting for all LLID indices + */ +#define EPN_MULTI_PRI_CFG_0_REG 0x180 + +/* + * Enables deficit accounting in the CTC scheduler. + * Applies only whenthe CTC scheduler is configured for weighted + * round-robin operation. +*/ +#define MULTI_PRI_CFG_0_CFGCTCSCHDEFICITEN_MASK 0x1000 + +/* + * Determines an internal burst cap value for any priority/L2 which hasits + * burst cap set to zero. + * The internal burst cap value is used bythe L1-to-L2 packet transfer + * logic. + * 0: + * Use an internal burst cap value of zero. + * (Do not use. + * )1: + * Use an internal burst cap value of 2 KB. + * Reset default. + * 2: + * Use a "max value" internal burst cap: + * 128KB for 1G upstream. + * 3. + * Reserved (do not use) +*/ +#define MULTI_PRI_CFG_0_PRVZEROBURSTCAPOVERRIDEMODE_SHIFT 8 +#define MULTI_PRI_CFG_0_PRVZEROBURSTCAPOVERRIDEMODE_MASK 0x300 + +/* + * For the burst-cap limited queue set, configures whether each + * queuereport/priority uses a separate L2 queue, or a shared one. + * Settingthis bit, along with cfgSharedBurstCap, configures EPN into + * aTK3715-compatible reporting mode. + * Note: + * Using a shared L2 queue effectively disables the CTC outputscheduler, + * since packets from all priorities are merged into asingle pipe and + * scheduled (in strict priority) upon entry to the L2queue. + * 0: + * Each priority level uses its own dedicated L2 queue. + * 1: + * All priority levels use a single, shared L2 queue +*/ +#define MULTI_PRI_CFG_0_CFGSHAREDL2_MASK 0x40 + +/* + * For the burst-cap limited queue set, configures whether each + * queuereport/priority is individually limited to the Burst Cap, or + * whetherthe sum of all queue report values is limited to the Burst Cap. + * 0: + * Limit each queue report value to a Burst Cap. + * Each queuereport/priority uses the Burst Cap corresponding to its L2 + * FIFO. + * This bit has effect only when cfgRptMultiPri is 1. + * Note: + * Setting this bit, along with cfgSharedL2, configures EPN intoa + * TK3715-compatible reporting mode. + * 1: + * Limit the sum of the queue reports/priorities to the Burst Capvalue. + * (Use the Burst Cap value corresponding to the lowest L2 FIFOassigned to + * the LLID index). + * Note: + * The following offsets must be included in the burst cap valuecalculation + * when "shared burst cap mode" is enabled. + * Decrease thedesired burst cap value by 21 bytes in 1G non-FEC mode, 193 + * bytes in1G FEC mode. +*/ +#define MULTI_PRI_CFG_0_CFGSHAREDBURSTCAP_MASK 0x20 + +/* + * Configures whether Multi-Priority REPORT frames includealready-granted + * frames. + * 0: + * Report frames do NOT include frames that have already beengranted. + * This is the setting for NTT operation. + * 1: + * Report frames DO include frames that have already been granted(but not + * yet sent upstream). + * This bit has effect only when cfgRptMultiPri is 1. +*/ +#define MULTI_PRI_CFG_0_CFGRPTGNTSOUTST0_MASK 0x10 + +/* + * Determines the order within a queue set in which priorities arereported + * on. + * 0: + * Priorities are reported low to high. + * 1: + * Priorities are reported high to low. + * This bit has effect only when cfgRptMultiPri0 is 1. +*/ +#define MULTI_PRI_CFG_0_CFGRPTHIPRIFIRST0_MASK 0x8 + +/* + * Configure order of queue sets. + * 0: + * The first queue set reports the full packet buffer queue depths;the + * second queue set reports up to the T/Burst Cap 0 threshold. + * 1: + * Swap queue sets in Multi-Priority REPORT frames. + * The first Queueset reports up to the T/Burst Cap 0 threshold; the second + * queue setreports the the full packet buffer queue depths. + * This bit has effect only when cfgRptMultiPri0 is 1. +*/ +#define MULTI_PRI_CFG_0_CFGRPTSWAPQS0_MASK 0x4 + +/* + * Configure Multi-Priority mode. + * 0: + * Disable Multi-Priority mode. + * The reporting style is selected byReport Select bit (bit 8 in the EPON + * Control 0 register). + * 1: + * Configured for Multi-Priority reporting mode. +*/ +#define MULTI_PRI_CFG_0_CFGRPTMULTIPRI0_MASK 0x1 + + +/* + * Register - read-only + * + */ +#define EPN_SHARED_BCAP_OVRFLOW_REG 0x184 + +#define SHARED_BCAP_OVRFLOW_SHAREDBURSTCAPOVERFLOW_SHIFT 0 +#define SHARED_BCAP_OVRFLOW_SHAREDBURSTCAPOVERFLOW_MASK 0x7ff + +/* + * Register + * + * Option to force an upstream report for an LLID Index that has + * notreceived an upstream grant with the "force report" bit set in more + * than50 mS. + * This mode is enabled per-LLID Index. + * Discovery gates will nothave their "force report" bits set. + * This bit should not be enabledunless the LLID index is registered with + * the OLT. + */ +#define EPN_FORCED_REPORT_EN_REG 0x188 + +/* + * Per-LLID Index bits for enabling forced reporting. + * Setting a bitwill cause that Index to send a report as part of the first + * upstreamburst that occurs more than the number of mS provisioned + * incfgMaxReportInterval" after the last report was sent. +*/ +#define FORCED_REPORT_EN_CFGFORCEREPORTEN_SHIFT 0 +#define FORCED_REPORT_EN_CFGFORCEREPORTEN_MASK 0xffffffff + + +/* + * Register + * + * Option to force an upstream report for an LLID Index that has + * notreceived an upstream grant with the "force report" bit set in more + * than50 mS. + * This mode is enabled per-LLID Index. + * Discovery gates will nothave their "force report" bits set. + * This bit should not be enabledunless the LLID index is registered with + * the OLT. + */ +#define EPN_FORCED_REPORT_MAX_INTERVAL_REG 0x18c + +/* The number of mS after the last report was sent to force the report. */ +#define FORCED_REPORT_MAX_INTERVAL_CFGMAXREPORTINTERVAL_SHIFT 0 +#define FORCED_REPORT_MAX_INTERVAL_CFGMAXREPORTINTERVAL_MASK 0x3f + + +/* + * Register + * + * Provides a mechanism to flush an L2 queue. + * The associated LLID indexmust be upstream disabled (including waiting + * for the upstream LLIDindex enable feedback confirmation) before starting + * the flushmechanism. + * Once an LLID index has been disabled, the L2 queues thatcomprise it may + * be flushed one at a time via this register. + * A flush isstarted by writing the cfgFlushL2sSel field and setting + * thecfgFlushL2sEn bit. + * The flushL2sDone bit will be set by the hardwarewhen the selected L2 + * queue has been flushed. + * Note: + * Do not change thecfgFlushL2sSel value unless both "flushL2sDone" and + * "cfgFlushL2sEn" arelow. + */ +#define EPN_L2S_FLUSH_CONFIG_REG 0x190 + +/* + * Enables the selected L2 queue to be flushed. + * This configuration bitmust be forced low and "flushL2sDone" must be read + * back as low;before, "cfgFlushL2sSel" is written. + * 0: + * L2 queue flush is disabled1: + * L2 queue flush is enabled +*/ +#define L2S_FLUSH_CONFIG_CFGFLUSHL2SEN_MASK 0x80000000 + +/* + * This bit is set when the selected L2 queue has no more packets toflush. + * This bit will always be zero when the enable bit is zero. +*/ +#define L2S_FLUSH_CONFIG_FLUSHL2SDONE_MASK 0x40000000 + +/* + * Selects the L2 queue that will be flushed when the enable is set. + * Do not write this register unless both "flushL2sDone" andcfgFlushL2sEn" + * are low. +*/ +#define L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_SHIFT 0 +#define L2S_FLUSH_CONFIG_CFGFLUSHL2SSEL_MASK 0x1f + + +/* + * Register + * + * This set of registers allows processor access to RAMs controlled by + * themodules in the EPON block. + * Data Port Control indicates whether a reador write access is occurring. + * Data Port Select indicates which RAM isbeing accessed. + * Writing to the Data Port Command register (offset 0)initiates the memory + * access. + * The processor may only access the Downstream Statistics RAM andUpstream + * Statistics RAM during run time. + * Accessing the L2 queue RAM maycause the EPON to fail in an unknown and + * random way. + * The flow for a write operation is as follows. + * 1. + * Check if the Data Port Interrupt is ready. + * 2. + * Update the Data Port Address register. + * 3. + * Update the Data Port Data register4. + * Update the Data Port Command register. + * Write a "1" to the DataPort Control and the RAM's index into the Data + * Port Select. + * 5. + * The operation is completed when the Data Port Interrupt isready again. + * The flow for a read operation is as follows. + * 1. + * Check if the Data Port Interrupt is ready. + * 2. + * Update the Data Port Address register. + * 3. + * Update the Data Port Command register. + * Write a "0" to the DataPort Control and the RAM's index into the Data + * Port Select. + * 4. + * Check to see if the Data Port Interrupt is read. + * 5. + * Read the Data Port Data register to get the operation'sresults. + * RAM Name RAM Size AutoInit?Downstream Statistics 672 x 32 YesUpstream + * Statistics 1088 x 32 YesL2 Queue RAM 16384 x 22 NoThe Downstream + * Statistics RAMs accumulate statistics for 32 LLIDs. + * EachLLID occupies 21 RAM offsets. + * Downstream Statistics RAM definition areas follows : + * LLID Index RAM Locations0 0 - 201 21 - 412 42 - 62. + * .n (up to 32) (n*21) - (n*21)+20RAM Offset Description0 Total bytes + * received1 FCS Errors2 OAM frames received3 GATE frames received4 64 byte + * frames received5 65 - 127 byte frames received6 128 - 255 byte frames + * received7 256 - 511 byte frames received8 512 - 1023 byte frames + * received9 1024 - 1518 byte frames received10 1519 - 2047 byte frames + * received11 2048 - 4095 byte frames received12 4096 - 9216 byte frames + * received13 Greater than 9216 byte frames received14 Oversized frames + * received15 Broadcast frames received16 Multicast frames received17 + * Unicast frames received18 Undersized frames received19 OAM bytes + * received20 Register frames receivedThe Upstream Statistics RAMs + * accumulate statistics for 32 LLIDs. + * EachLLID occupies 17 RAM offsets. + * It is logically divided into 64segments. + * The lower 32 segments contain the normal upstream statisticsfor each of + * the 32 LLID Indexes. + * The upper 32 segments are used toreport the "fake packet" statistics. + * Fake packets are inserted intoupstream bursts to substitute for packets + * that are delivered late fromthe Runner/BBH subsystem. + * Fake packets are zero-padded and contain aguaranteed-bad FCS. + * Note that a faked packet can cause broadcast andmulticast packets to be + * reported as unicast packets, depending onwhether the Runner/BBH upstream + * data delivery failure occurred beforethe DA data was delivered. + * LLID Index RAM Locations0 0 - 161 17 - 332 34 - 50. + * .n (up to 32) (n*17) - (n*17)+16Fake packet 0 544 - 560Fake packet 1 561 + * - 577Fake packet 2 578 - 594. + * .Fake packet n [544+(n*17)] - [544+(n*17)+16]RAM Offset Description0 + * Total bytes sent1 OAM frames sent2 REPORT frames sent3 64 byte frames + * sent4 65 - 127 byte frames sent5 128 - 255 byte frames sent6 256 - 511 + * byte frames sent7 512 - 1023 byte frames sent8 1024 - 1518 byte frames + * sent9 1519 - 2047 byte frames sent10 2048 - 4095 byte frames sent11 4096 + * - 9216 byte frames sent12 Greater than 9216 byte frames sent13 OAM bytes + * sent14 Broadcast frames sent15 Multicast frames sent16 Unicast frames + * sentNotes: + * Total bytes sent do not include OAM or Report frames. + * The various frame "bucket" statistics do not include OAM or + * Reportframes. + * Oversized frames are frames that are greater than the value specifiedby + * the EPON Max Frame Size register. + * The exception is when cfgVlanMaxmode is used. + * In this case an oversized condition occurs when a frameis greater than + * 1522 byte when a VLAN tag is present, otherwise greaterthan 1518 bytesAn + * undersized frame condition occurs when the received frame is lessthan 64 + * bytes in length and has a valid FCS. + * The Unused Words counts the number of words that in a grant that theLLID + * was not able to send upstream traffic on. + * If the LLID received agrant for 2K words, but it has only 1K words of + * data, the unused wordcount will increase by 1 K. + * In most cases this condition should nothappen. + * It indicates that the OLT is granting inefficiently. + * Therecould be a problem with the ONU's EPON overhead setting + * beingincorrect. + */ +#define EPN_DATA_PORT_COMMAND_REG 0x194 + +/* + * Indicates access to RAM is in progress. + * 0: + * Data port is ready to accept a command1: + * Data port is busy +*/ +#define DATA_PORT_COMMAND_DPORTBUSY_MASK 0x80000000 + +/* + * Selects RAM to be access0: + * Downstream statistics RAM1: + * Upstream statistics RAM2: + * Reserved3: + * L2 Queue RAM4-31: + * Reserved +*/ +#define DATA_PORT_COMMAND_DPORTSELECT_SHIFT 4 +#define DATA_PORT_COMMAND_DPORTSELECT_MASK 0x1f0 + +/* + * Indicates data port operation0: + * Do a RAM read operation1: + * Do a RAM write operation +*/ +#define DATA_PORT_COMMAND_DPORTCONTROL_MASK 0x1 + + +/* + * Register + * + */ +#define EPN_DATA_PORT_ADDR_REG 0x198 + +/* Address for RAM accesses. */ +#define DATA_PORT_ADDR_DPORTADDR_SHIFT 0 +#define DATA_PORT_ADDR_DPORTADDR_MASK 0x3fff + + +/* + * Register + * + */ +#define EPN_DATA_PORT_DATA_0_REG 0x19c + +/* Low-order data dword for data port accesses */ +#define DATA_PORT_DATA_0_DPORTDATA0_SHIFT 0 +#define DATA_PORT_DATA_0_DPORTDATA0_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_BIG_CNT_REG 0x1a0 + +/* Counts illegally large frames. */ +#define UNMAP_BIG_CNT_UNMAPBIGERRCNT_SHIFT 0 +#define UNMAP_BIG_CNT_UNMAPBIGERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_FRAME_CNT_REG 0x1a4 + +/* Counts valid frames that are not Gates or OAM frames. */ +#define UNMAP_FRAME_CNT_UNMAPFRCNT_SHIFT 0 +#define UNMAP_FRAME_CNT_UNMAPFRCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_FCS_CNT_REG 0x1a8 + +/* Counts frame with FCS errors. */ +#define UNMAP_FCS_CNT_UNMAPFCSERRCNT_SHIFT 0 +#define UNMAP_FCS_CNT_UNMAPFCSERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_GATE_CNT_REG 0x1ac + +/* Counts un-mapped gate frames. */ +#define UNMAP_GATE_CNT_UNMAPGATECNT_SHIFT 0 +#define UNMAP_GATE_CNT_UNMAPGATECNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_OAM_CNT_REG 0x1b0 + +/* Counts un-mapped OAM frames. */ +#define UNMAP_OAM_CNT_UNMAPOAMCNT_SHIFT 0 +#define UNMAP_OAM_CNT_UNMAPOAMCNT_MASK 0xffffffff + + +/* + * Register + * + * Statistics register for traffic sent on unmapped LLIDs. + * This register saturates at maximum value and self-clears when read. + */ +#define EPN_UNMAP_SMALL_CNT_REG 0x1b4 + +/* Counts illegally small frames. */ +#define UNMAP_SMALL_CNT_UNMAPSMALLERRCNT_SHIFT 0 +#define UNMAP_SMALL_CNT_UNMAPSMALLERRCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define EPN_FIF_DEQUEUE_EVENT_CNT_REG 0x1b8 + +/* Debug only! */ +#define FIF_DEQUEUE_EVENT_CNT_FIFDEQUEUEEVENTCNT_SHIFT 0 +#define FIF_DEQUEUE_EVENT_CNT_FIFDEQUEUEEVENTCNT_MASK 0xffffffff + + +/* + * Register + * + * Per-LLID index Runner/BBH upstream fault halt enable. + * This allows thedefault fatal upstream fault halt behavior to be + * disabled. + * The resetdefault value is enabled (all ones). + * This register should only be usedfor debug. + * All the bits in this register must be set during normaloperation. + */ +#define EPN_BBH_UP_FAULT_HALT_EN_REG 0x1dc + +/* + * Per-LLID Index Runner/BBH upstream fault halt enable. + * 0: + * Do not disable upstream data traffic. + * 1: + * Disable upstream data traffic for LLID indexes the Runner/BBHfaulted on. +*/ +#define BBH_UP_FAULT_HALT_EN_BBHUPSFAULTHALTEN_SHIFT 0 +#define BBH_UP_FAULT_HALT_EN_BBHUPSFAULTHALTEN_MASK 0xffffffff + + +/* + * Register + * + * Per-LLID index Runner/BBH upstream fault halt enable. + * This allows thedefault fatal upstream fault halt behavior to be + * disabled. + * The resetdefault value is enabled (all ones). + * This register should only be usedfor debug. + * All the bits in this register must be set during normaloperation. + */ +#define EPN_BBH_UP_TARDY_HALT_EN_REG 0x1e0 + +/* + * Disable all upstream data traffic when the BHH aborts a tardypacket. + * 0: + * Do not disable upstream data traffic on tardy/abort1: + * Disable all upstream data traffic when the BBH aborts a tardypacket. +*/ +#define BBH_UP_TARDY_HALT_EN_FATALTARDYBBHABORTEN_MASK 0x1 + + +/* + * Register - read-only + * + * This register contains the real time status bits to aid debugging theEPN + * module. + */ +#define EPN_DEBUG_STATUS_0_REG 0x1e4 + +/* Indicates which LLID's report FIFO is full */ +#define DEBUG_STATUS_0_L2SQUEFULLDEBUG_SHIFT 8 +#define DEBUG_STATUS_0_L2SQUEFULLDEBUG_MASK 0xff00 + +#define DEBUG_STATUS_0_DNDLUFULL_MASK 0x10 +/* SEC and EPN downstream */ +#define DEBUG_STATUS_0_DNSECFULL_MASK 0x8 + +/* SEC and EPN upstream interface FIFO is full */ +#define DEBUG_STATUS_0_EPNLIFFIFOFULL_MASK 0x4 + + +/* + * Register - read-only + * + * This register contains the real time status bits to aid debugging theEPN + * module. + */ +#define EPN_DEBUG_STATUS_1_REG 0x1e8 + +/* LLID Index 0 has grant(s) pending */ +#define DEBUG_STATUS_1_GNTRDYx_MASK(x) (1 << ((x) + 1)) + + +/* + * Register + * + */ +#define EPN_DEBUG_L2S_PTR_SEL_REG 0x1ec + +#define DEBUG_L2S_PTR_SEL_CFGL2SDEBUGPTRSEL_SHIFT 16 +#define DEBUG_L2S_PTR_SEL_CFGL2SDEBUGPTRSEL_MASK 0x70000 +#define DEBUG_L2S_PTR_SEL_L2SDEBUGPTRSTATE_SHIFT 0 +#define DEBUG_L2S_PTR_SEL_L2SDEBUGPTRSTATE_MASK 0x7fff + +/* + * Register + * + * This register stores a MAC address for the OLT. + * This address isinserted as the DA in REPORT frames sent upstream. + */ +#define EPN_OLT_MAC_ADDR_LO_REG 0x230 + +/* OLT MAC Address */ +#define OLT_MAC_ADDR_LO_OLTADDRLO_SHIFT 0 +#define OLT_MAC_ADDR_LO_OLTADDRLO_MASK 0xffffffff + + +/* + * Register + * + * This register stores a MAC address for the OLT. + * This address isinserted as the DA in REPORT frames sent upstream. + */ +#define EPN_OLT_MAC_ADDR_HI_REG 0x234 + +/* OLT MAC Address */ +#define OLT_MAC_ADDR_HI_OLTADDRHI_SHIFT 0 +#define OLT_MAC_ADDR_HI_OLTADDRHI_MASK 0xffff + + +/* + * Register - read-only + * + * Indicates empty status of L1 shaped queues + */ +#define EPN_TX_L1S_SHP_DQU_EMPTY_REG 0x278 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L1 accumulator is not empty1: + * L1 accumulator is empty +*/ +#define TX_L1S_SHP_DQU_EMPTY_L1SDQUQUEEMPTY_SHIFT 0 +#define TX_L1S_SHP_DQU_EMPTY_L1SDQUQUEEMPTY_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates status of L1 unshaped-empty accumulators + */ +#define EPN_TX_L1S_UNSHAPED_EMPTY_REG 0x27c + +/* + * Each bit in this register contains the status of the + * respectiveaccumulators0: + * L1 unshaped accumulator is not empty1: + * L1 unshaped accumulator is empty +*/ +#define TX_L1S_UNSHAPED_EMPTY_L1SUNSHAPEDQUEEMPTY_SHIFT 0 +#define TX_L1S_UNSHAPED_EMPTY_L1SUNSHAPEDQUEEMPTY_MASK 0xffffffff + + +/* + * Register - read-only + * + * L2 queue empty status + */ +#define EPN_TX_L2S_QUE_EMPTY_REG 0x2c0 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L2 queue is not empty1: + * L2 queue is empty +*/ +#define TX_L2S_QUE_EMPTY_L2SQUEEMPTY_SHIFT 0 +#define TX_L2S_QUE_EMPTY_L2SQUEEMPTY_MASK 0xffffffff + + +/* + * Register - read-only + * + * L2 queue full status + */ +#define EPN_TX_L2S_QUE_FULL_REG 0x2c4 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L2 queue is not full1: + * L2 queue is full +*/ +#define TX_L2S_QUE_FULL_L2SQUEFULL_SHIFT 0 +#define TX_L2S_QUE_FULL_L2SQUEFULL_MASK 0xffffffff + + +/* + * Register - read-only + * + * L2 queue stopped status + */ +#define EPN_TX_L2S_QUE_STOPPED_REG 0x2c8 + +/* + * Each bit in this register contains the status of the respectivequeue0: + * L2 queue is not stopped1: + * L2 queue is stopped +*/ +#define TX_L2S_QUE_STOPPED_L2SSTOPPEDQUEUES_SHIFT 0 +#define TX_L2S_QUE_STOPPED_L2SSTOPPEDQUEUES_MASK 0xffffffff + + +/* + * Register + * + * Everytime the BBH fails to deliver a packet in time to be + * transmittedupstreamit is placed in failed state and the Epn increments a + * tardy packetcounter. + * Every time the BBH delivers a packetwhile it is in the failed state the + * tardy packet counter isdecremented. + * The BBH will be taken out of thefailed state when the tardy packet + * counter reaches 0. + * If the tardypacket countervalue exceeds the value of this register; then + * the BBH becomes truantand the Epn stops upstream traffic untilthe Epn is + * reset. + * It is expected the BBH, runner and Epn will be resetat the same time. + */ +#define EPN_BBH_MAX_OUTSTANDING_TARDY_PACKETS_REG 0x2ec + +/* + * Maximum number of packets outstanding tardy packet the BBH canaccumulate + * at one time. +*/ +#define BBH_MAX_OUTSTANDING_TARDY_PACKETS_CFGMAXOUTSTANDINGTARDYPACKETS_SHIFT 0 +#define BBH_MAX_OUTSTANDING_TARDY_PACKETS_CFGMAXOUTSTANDINGTARDYPACKETS_MASK 0x3ff + + +/* + * Register + * + * The Virtual Thresholds are determined from the smaller of the queue + * setshaper and the accumulated queue length. + * The Virtual Thresholds mustalso prevent pathological values from being + * reported. + * The reportedvalue should be at least one maximum frame length greater + * than theprevious queue set threshold or else it will be reported as + * zero. + * Thisprevents a head of line blocking issue if a large frame is at the + * headof the queue and also prevents from reporting illegally short + * grantlengths. + * Everytime the BBH fails to deliver a packet in time to betransmitted + * upstream + */ +#define EPN_MIN_REPORT_VALUE_DIFFERENCE_REG 0x2f0 + +/* The smallest allowable difference between ajacent non-zero queuesets. */ +#define MIN_REPORT_VALUE_DIFFERENCE_PRVMINREPORTDIFF_SHIFT 0 +#define MIN_REPORT_VALUE_DIFFERENCE_PRVMINREPORTDIFF_MASK 0x3fff + + +/* + * Register - read-only + * + * Indicates which BBH queue status interface event FIFOs have overflowed. + * Note: + * These bits are used for debug only. + */ +#define EPN_BBH_STATUS_FIFO_OVERFLOW_REG 0x2f4 + +/* + * Indicates which BBH queue status interface event FIFOs haveoverflowed. + * The overflow can only be corrected by reset. +*/ +#define BBH_STATUS_FIFO_OVERFLOW_UTXBBHSTATUSFIFOOVERFLOW_SHIFT 0 +#define BBH_STATUS_FIFO_OVERFLOW_UTXBBHSTATUSFIFOOVERFLOW_MASK 0xffffffff + + +/* + * Register + * + * Spare RW bits + */ +#define EPN_SPARE_CTL_REG 0x2f8 + +/* Spare RW bits */ +#define SPARE_CTL_CFGEPNSPARE_SHIFT 2 +#define SPARE_CTL_CFGEPNSPARE_MASK 0xfffffffc + +/* + * Set this bit to enable store and forward upstream AE operation. + * Only set this bit when operating in Point-to-Point or ActiveEthernet + * modes. +*/ +#define SPARE_CTL_ECOUTXSNFENABLE_MASK 0x2 + +/* + * Set this bit to prevent transmitting when the LLID's shapers areempty. + * This will preventthe ONU from using excess bandwidth granted to it by + * the OLT. + * Do not set this bit when operating in Point-to-Point or ActiveEthernet + * modes. +*/ +#define SPARE_CTL_ECOJIRA758ENABLE_MASK 0x1 + + +/* + * Register + * + * Timestamp synchronizer offset. + */ +#define EPN_TS_SYNC_OFFSET_REG 0x2fc + +/* + * Provides lowest 6 bits of timestamp synchronizer, from 250 MHzdomain to + * 125 MHz. +*/ +#define TS_SYNC_OFFSET_CFGTSSYNCOFFSET_SHIFT 0 +#define TS_SYNC_OFFSET_CFGTSSYNCOFFSET_MASK 0x3f + + +/* + * Register + * + * Downstream timestamp offset. + */ +#define EPN_DN_TS_OFFSET_REG 0x300 + +/* Provides signed offset for downstream packet timestamping. */ +#define DN_TS_OFFSET_CFGDNTSOFFSET_SHIFT 0 +#define DN_TS_OFFSET_CFGDNTSOFFSET_MASK 0xffffffff + + +/* + * Register + * + * Upstream timestamp offset, lower 32 bits. + */ +#define EPN_UP_TS_OFFSET_LO_REG 0x304 + +/* Provides signed offset for upstream packet timestamping. */ +#define UP_TS_OFFSET_LO_CFGUPTSOFFSET_LO_SHIFT 0 +#define UP_TS_OFFSET_LO_CFGUPTSOFFSET_LO_MASK 0xffffffff + + +/* + * Register + * + * Upstream timestamp offset, upper 16 bits. + */ +#define EPN_UP_TS_OFFSET_HI_REG 0x308 + +/* Provides signed offset for upstream packet timestamping. */ +#define UP_TS_OFFSET_HI_CFGUPTSOFFSET_HI_SHIFT 0 +#define UP_TS_OFFSET_HI_CFGUPTSOFFSET_HI_MASK 0xffff + + +/* + * Register + * + * Provides control for the reading of two step timestamp FIFO, 4 + * entriesdeep. + */ +#define EPN_TWO_STEP_TS_CTL_REG 0x30c + +/* + * Provides the reading of the two step timestamp FIFO. + * A write valueof 1 will advance the FIFO to the next entry. + * The 48-bits value isprovided by + * registersEPN_TWO_STEP_TS_VALUE_HI/EPN_TWO_STEP_TS_VALUE_LO. +*/ +#define TWO_STEP_TS_CTL_TWOSTEPFFRD_MASK 0x80000000 + +/* Indicates the number of entries in the two step timestamp FIFO. */ +#define TWO_STEP_TS_CTL_TWOSTEPFFENTRIES_SHIFT 0 +#define TWO_STEP_TS_CTL_TWOSTEPFFENTRIES_MASK 0x7 + + +/* + * Register - read-only + * + * Lower 32-bits of 48-bits timestamp value, applicable for two + * steptimestamping. + */ +#define EPN_TWO_STEP_TS_VALUE_LO_REG 0x310 + +/* Lower 32-bits of two-step timestamp value for IEEE 1588timestamping. */ +#define TWO_STEP_TS_VALUE_LO_TWOSTEPTIMESTAMP_LO_SHIFT 0 +#define TWO_STEP_TS_VALUE_LO_TWOSTEPTIMESTAMP_LO_MASK 0xffffffff + + +/* + * Register - read-only + * + * Upper 16-bits of 48-bits timestamp value, applicable for two + * steptimestamping. + */ +#define EPN_TWO_STEP_TS_VALUE_HI_REG 0x314 + +/* Upper 16-bits of two-step timestamp value for IEEE 1588timestamping. */ +#define TWO_STEP_TS_VALUE_HI_TWOSTEPTIMESTAMP_HI_SHIFT 0 +#define TWO_STEP_TS_VALUE_HI_TWOSTEPTIMESTAMP_HI_MASK 0xffff + + +/* + * Register + * + * This register contains interrupt status for 1588 timestamp. + * These bitsare sticky; to clear a bit, write 1 to it. + */ +#define EPN_1588_TIMESTAMP_INT_STATUS_REG 0x318 + +/* + * Indicated 1588 timestamp packet was aborted due to illegal checksumor + * timestamp offsets. +*/ +#define EPN_1588_TIMESTAMP_INT_STATUS_INT1588PKTABORT_MASK 0x2 + +/* + * Indicates timestamp in two step FIFO is available for reading. + * The48-bits value is provided by + * registersEPN_TWO_STEP_TS_VALUE_HI/EPN_TWO_STEP_TS_VALUE_LO. +*/ +#define EPN_1588_TIMESTAMP_INT_STATUS_INT1588TWOSTEPFFINT_MASK 0x1 + + +/* + * Register + * + * This register contains interrupt mask for 1588 timestamp interrupts. + */ +#define EPN_1588_TIMESTAMP_INT_MASK_REG 0x31c + +/* Mask 1588 timestamp packet abort. */ +#define EPN_1588_TIMESTAMP_INT_MASK_TS1588PKTABORT_MASK_MASK 0x2 + +/* Mask two step FIFO interrupt. */ +#define EPN_1588_TIMESTAMP_INT_MASK_TS1588TWOSTEPFF_MASK_MASK 0x1 + + +/* + * Register + * + * Specifies the setup time margin for the BBH to fetch upstream data + * totransfer to EPN. + * This margin MUST be used when the Epn is provisioned to delay the + * bursttermination while waiting for the Runner/BBH upstream queue status + * tobe updated. + * (see prvBbhQueStatDelay)The Power-On Reset default value of 0 will + * disable this delay. + * The units are in TimeQuanta (TQ = 16nS). + * The estimated DDR latency is2 [uS]. + * So, the minimum non-zero value for this register is 223 [TQ]. + */ +#define EPN_UP_PACKET_FETCH_MARGIN_REG 0x320 + +/* + * Minimum BBH upstream packet request latency. + * Units are TQ. +*/ +#define UP_PACKET_FETCH_MARGIN_UPPACKETFETCHMARGIN_SHIFT 0 +#define UP_PACKET_FETCH_MARGIN_UPPACKETFETCHMARGIN_MASK 0xffff + + +/* + * Register - read-only + * + * Provides real time indication of 1588 downstream timestamp. + * A changein value indicates downstream traffic to BBH. + */ +#define EPN_DN_1588_TIMESTAMP_REG 0x324 + +/* 32-bits timestamp value of downstream packet. */ +#define DN_1588_TIMESTAMP_DN_1588_TS_SHIFT 0 +#define DN_1588_TIMESTAMP_DN_1588_TS_MASK 0xffffffff + + +/* + * Register + * + * Specifies how long reports should persist. + */ +#define EPN_PERSISTENT_REPORT_CFG_REG 0x328 + +/* + * How long report persistance lasts. + * (How many report persistance timer ticks after the last non-zeroreport + * should empty reportsbe replaced with a persistant report)Units are + * report perisitance timer ticks. +*/ +#define PERSISTENT_REPORT_CFG_CFGPERSRPTDURATION_SHIFT 16 +#define PERSISTENT_REPORT_CFG_CFGPERSRPTDURATION_MASK 0x3ff0000 + +/* + * How many clock cycles are in each report persistance timer tick. + * The 125 MHz core clock rate requires 125 clocks per 1 uS tick. + * Units are core clock cycles. +*/ +#define PERSISTENT_REPORT_CFG_CFGPERSRPTTICKSIZE_SHIFT 0 +#define PERSISTENT_REPORT_CFG_CFGPERSRPTTICKSIZE_MASK 0xffff + + +/* + * Register + * + * Per LLID enable for persistent reporting. + */ +#define EPN_PERSISTENT_REPORT_ENABLES_REG 0x32c + +/* + * Per LLID enable for persistent reporting. + * Set the bit to enablepersistent reporting. + * 0: + * Disable persistent reporting. + * 1: + * Enable persistent reporting. +*/ +#define PERSISTENT_REPORT_ENABLES_CFGPERSRPTENABLE_SHIFT 0 +#define PERSISTENT_REPORT_ENABLES_CFGPERSRPTENABLE_MASK 0xffffffff + + +/* + * Register + * + * How many Time Quanta the persistent report should request. + */ +#define EPN_PERSISTENT_REPORT_REQUEST_SIZE_REG 0x330 + +/* + * How many Time Quanta the persistent report should request. + * Smallervalues waste less upstream bandwidth. + * Units are Time Quanta. +*/ +#define PERSISTENT_REPORT_REQUEST_SIZE_CFGPERSRPTREQTQ_SHIFT 0 +#define PERSISTENT_REPORT_REQUEST_SIZE_CFGPERSRPTREQTQ_MASK 0xffff + + +/* + * Register + * + * Allows control over reporting the extra per-packet overhead + * associatedwith 802. + * 1AE encryption. + * The AES overhead compensation logic supportstwo overhead modes: + * implicit SCI and explicit SCI. + * The implicit SCImode increases the per-packet overhead by 24 bytes. + * Explicit SCI modeincreases the per-packet overhead by 32 bytes. + */ +#define EPN_AES_CFG_1_REG 0x334 + +/* + * LLID index 16 AES overhead mode. + * 0: + * Implicit SCI AES overhead mode. + * 1: + * Explicit SCI AES overhead mode. + * .. + * LLID index 31 AES overhead mode. + * 30: + * Implicit SCI AES overhead mode. + * 31: + * Explicit SCI AES overhead mode. +*/ +#define AES_CFG_1_PRVUPSTREAMAESMODE_1_SHIFT 0 +#define AES_CFG_1_PRVUPSTREAMAESMODE_1_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * These registers limit how much data can be reported in REPORT frames. + * The EPON MAC reports data (that is sitting in the FIFO Queues) inbetween + * 1 and 4 "chunks". + * The size of these chunks is determined by theBurst Cap settings here. + * The units for these registers are 1 TQ for 1Gupstream mode. + * The units are one-tenth of a TQ for 10G upstream mode. + * To provision 4 TQ in 1G upstream mode, write a value of 4. + * To provision4 TQ in 10G upstream mode write a value of 40. + * Note that when register0x400 bit 21 is set that the provisioned value + * must be one time quantumless than the maximum value that should be + * reported to the OLT. + * When configured in shared burst cap mode, the burst cap value must + * bereduced by the following amounts (relative to the threshold/token + * sizevalue sent from the OLT)Mode Reduction Amount + * (bytes)---------------- -----------------------------------1G non-FEC 21 + * + number of CTC priority levels1G FEC 193 + number of CTC priority + * levels10G 20 + number of CTC priority levels10G implicit SCI 44 + number + * of CTC priority levels10G explicit SCI 52 + number of CTC priority + * levels + */ +#define EPN_BURST_CAPx_0_7_REG(x) (0x138 + (x) * 0x4) + +/* + * Defines maximum size of a report on LLID index 0 in Tek mode and onL2 0 + * in multi-priority mode. +*/ +#define BURST_CAPx_0_7_BURSTCAP0_SHIFT 0 +#define BURST_CAPx_0_7_BURSTCAP0_MASK 0xfffff + + +/* + * Registers - is [ 0 => 8 ] + * + */ +#define EPN_QUEUE_LLID_MAPx_0_7_REG(x) (0x158 + (x) * 0x4) + +/* Selects the L2 FIFO to which Queue 0 is mapped. */ +#define QUEUE_LLID_MAPx_0_7_QUELLIDMAP0_SHIFT 0 +#define QUEUE_LLID_MAPx_0_7_QUELLIDMAP0_MASK 0x1f + + +/* + * Registers - is [ 0 => 8 ] + * + * Statistics register that accumulates the number of upstream unused + * timequanta for an upstream LLID. + * The register saturates at maximum value. + * The register will clear uponread. + */ +#define EPN_UNUSED_TQ_CNTx_0_7_REG(x) (0x1bc + (x) * 0x4) + +/* The number of unused time quanta for LLID 0. */ +#define UNUSED_TQ_CNTx_0_7_UNUSEDTQCNT0_SHIFT 0 +#define UNUSED_TQ_CNTx_0_7_UNUSEDTQCNT0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * This register allows the effects of the upstream shaper 0 to be masked. + * When multiple priority queues point to a common shaping bucket, thelow + * priority traffic can use all the credits prior to a high priorityframe + * arriving. + * The high priority would then incur additional latencywaiting for credits + * to accrue. + * This adds undesirable delay to the datapath. + * This feature separates the queues that apply credit to a shaperand those + * that are masked by the shaper. + * The Shaping function has aninput that credits the shaping bucket when a + * frame is sent. + * It also hasan output that masks a queue from being eligible to transmit + * when theshaping rate is violated. + * In this case the low priority queue will bothcredit and be masked by the + * shaper as typically done. + * The high priorityon the other hand will credit the shaper, but not be + * limited by it. + * Theshaper will then be allowed to go into a deficit. + * In most cases thehigh priority is a small portion of the total + * bandwidth. + * In some caseshowever it may be desired to limit the high priority + * traffic with adifferent shaper. + */ +#define EPN_TX_L1S_SHP_QUE_MASKx_0_7_REG(x) (0x280 + (x) * 0x4) + +/* + * Each mask bit in this register controls the effect of shaper 0 onthe + * respective queue0: + * Shaper 0 can affect this queue1: + * Shaper 0 does not affect this queue +*/ +#define TX_L1S_SHP_QUE_MASKx_0_7_CFGSHPMASK0_SHIFT 0 +#define TX_L1S_SHP_QUE_MASKx_0_7_CFGSHPMASK0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * This registers configures the base addresses of the L2 structure 0. + * Internally the least significant two bits are treated as constants: + * Thetwo least significant start address bits are 0 and the two + * leastsignificant end address bits are 1. + * Therefore the queue base addressescannot be read directly from the + * register contents without performingsome mental gymnastics. + * Try to picture a 2-bit left shift and stuffoperation. + * The base address granularity is 4 entries. + * It is criticalthat the number of entries allocated for each FIFO be + * sufficient toaccommodate the worst case number of frames that can be + * contained inthe associated Fif queue. + * A general rule-of-thumb would be to dividethe number of bytes in the + * respective Fif queue by 80. + * The quotient+1will be the minimum number of entries that should be + * allocated. + * Do notforget to round up to the nearest 4-entry quanta. + * If the L2 is beingsized to match the burst cap (instead of the entire + * Fif queue size) donot forget to multiply the quotient+1 by four (or by 5 + * ifprvTekModePrefetch is set) when operating in Teknovus mode. + * There arefour burst cap values reported in Teknovus modeNote: + * This register cannot be programmed "on-the-fly". + * The queuestart/end address values should be changed only when its + * associatedclear L2 report FIFO" bit is set. + */ +#define EPN_TX_L2S_QUE_CONFIGx_0_7_REG(x) (0x2a0 + (x) * 0x4) + +/* Queue 0 End address */ +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUEEND0_SHIFT 16 +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUEEND0_MASK 0xfff0000 + +/* Queue 0 Start address */ +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUESTART0_SHIFT 0 +#define TX_L2S_QUE_CONFIGx_0_7_CFGL2SQUESTART0_MASK 0xfff + + +/* + * Registers - is [ 0 => 8 ] + * + * This register configures the maximum number of bytes that L2 queue 0can + * transmit during any given round. + * A round ends when all L2 queueshave reached their respective burst limit + * or there is no more data totransmit. + * Note that setting a burst limit to zero enables therespective L2 queue + * to transmit in strict priority. + * Also, any burstlimits that are set to 1 will cause those L2 queues to + * transmit inround-robin" fashion. + * It is possible to allocate bandwidth as apercentage. + * Simply multiply the desired percentage by 2000 bytes (themaximum frame + * length) and write that value in the associated burstlimit register. + * Example bandwidth sharing configuration: + * Priority Burst Limit Description-------- ----------- ------------0 0 + * High priority unlimited bandwidth1 0 Low priority unlimited bandwidth2 1 + * Equal priority UNI 1 unlimited bandwidth3 1 Equal priority UNI 2 + * unlimited bandwidth4 1 Equal priority UNI 3 unlimited bandwidth5 1 Equal + * priority UNI 4 unlimited bandwidth6 0 High priority best effort + * bandwidth7 0 Low priority best effort bandwidthPriority 0 is for the + * highest priority traffic. + * i. + * e. + * , ManagementtrafficPriority 1 is for real-time traffic. + * i. + * e. + * , VOIPPriorities 2, 3, 4 and 5 equally share bandwidth, i. + * e. + * Premium businesstraffic. + * Priorities 6 and 7 provide two classes of best effort traffic, i. + * e. + * twoclasses of consumer trafficPlease note that the EPN shaper is the + * mechanism used to limit theamount of traffic. + */ +#define EPN_TX_CTC_BURST_LIMITx_0_7_REG(x) (0x2cc + (x) * 0x4) + +/* L2 queue 0 CTC mode burst limit */ +#define TX_CTC_BURST_LIMITx_0_7_PRVBURSTLIMIT0_SHIFT 0 +#define TX_CTC_BURST_LIMITx_0_7_PRVBURSTLIMIT0_MASK 0x3ffff + + +/* + * Registers - is [ 0 => 24 ] + * + * These registers limit how much data can be reported in REPORT frames. + * The EPON MAC reports data (that is sitting in the FIFO Queues) inbetween + * 1 and 4 "chunks". + * The size of these chunks is determined by theBurst Cap settings here. + * The units for these registers are 1 TQ for 1Gupstream mode. + * The units are one-tenth of a TQ for 10G upstream mode. + * To provision 4 TQ in 1G upstream mode, write a value of 4. + * To provision4 TQ in 10G upstream mode write a value of 40. + * Note that when register0x400 bit 21 is set that the provisioned value + * must be one time quantumless than the maximum value that should be + * reported to the OLT. + * When configured in shared burst cap mode, the burst cap value must + * bereduced by the following amounts (relative to the threshold/token + * sizevalue sent from the OLT)Mode Reduction Amount + * (bytes)---------------- -----------------------------------1G non-FEC 21 + * + number of CTC priority levels1G FEC 193 + number of CTC priority + * levels10G 20 + number of CTC priority levels10G implicit SCI 44 + number + * of CTC priority levels10G explicit SCI 52 + number of CTC priority + * levels + */ +#define EPN_BURST_CAPx_8_31_REG(x) (0x338 + (x) * 0x4) + +/* + * Defines maximum size of a report on LLID index 8 in Tek mode and onL2 8 + * in multi-priority mode. +*/ +#define BURST_CAPx_8_31_BURSTCAP8_SHIFT 0 +#define BURST_CAPx_8_31_BURSTCAP8_MASK 0xfffff + + +/* + * Registers - is [ 0 => 24 ] + * + */ +#define EPN_QUEUE_LLID_MAPx_8_31_REG(x) (0x398 + (x) * 0x4) + +/* Selects the L2 FIFO to which Queue 8 is mapped. */ +#define QUEUE_LLID_MAPx_8_31_QUELLIDMAP8_SHIFT 0 +#define QUEUE_LLID_MAPx_8_31_QUELLIDMAP8_MASK 0x1f + + +/* + * Registers - is [ 0 => 24 ] + * + * Statistics register that accumulates the number of upstream unused + * timequanta for an upstream LLID. + * The register saturates at maximum value. + * The register will clear uponread. + */ +#define EPN_UNUSED_TQ_CNTx_8_31_REG(x) (0x3f8 + (x) * 0x4) + +/* The number of unused time quanta for LLID 8. */ +#define UNUSED_TQ_CNTx_8_31_UNUSEDTQCNT8_SHIFT 0 +#define UNUSED_TQ_CNTx_8_31_UNUSEDTQCNT8_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 24 ] + * + * This register allows the effects of the upstream shaper 8 to be masked. + * When multiple priority queues point to a common shaping bucket, thelow + * priority traffic can use all the credits prior to a high priorityframe + * arriving. + * The high priority would then incur additional latencywaiting for credits + * to accrue. + * This adds undesirable delay to the datapath. + * This feature separates the queues that apply credit to a shaperand those + * that are masked by the shaper. + * The Shaping function has aninput that credits the shaping bucket when a + * frame is sent. + * It also hasan output that masks a queue from being eligible to transmit + * when theshaping rate is violated. + * In this case the low priority queue will bothcredit and be masked by the + * shaper as typically done. + * The high priorityon the other hand will credit the shaper, but not be + * limited by it. + * Theshaper will then be allowed to go into a deficit. + * In most cases thehigh priority is a small portion of the total + * bandwidth. + * In some caseshowever it may be desired to limit the high priority + * traffic with adifferent shaper. + */ +#define EPN_TX_L1S_SHP_QUE_MASKx_8_31_REG(x) (0x5d8 + (x) * 0x4) + +/* + * Each mask bit in this register controls the effect of shaper 8 onthe + * respective queue0: + * Shaper 8 can affect this queue1: + * Shaper 8 does not affect this queue +*/ +#define TX_L1S_SHP_QUE_MASKx_8_31_CFGSHPMASK8_SHIFT 0 +#define TX_L1S_SHP_QUE_MASKx_8_31_CFGSHPMASK8_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 24 ] + * + * This registers configures the base addresses of the L2 structure 8. + * Internally the least significant two bits are treated as constants: + * Thetwo least significant start address bits are 0 and the two + * leastsignificant end address bits are 1. + * Therefore the queue base addressescannot be read directly from the + * register contents without performingsome mental gymnastics. + * Try to picture a 2-bit left shift and stuffoperation. + * The base address granularity is 4 entries. + * It is criticalthat the number of entries allocated for each FIFO be + * sufficient toaccommodate the worst case number of frames that can be + * contained inthe associated Fif queue. + * A general rule-of-thumb would be to dividethe number of bytes in the + * respective Fif queue by 80. + * The quotient+1will be the minimum number of entries that should be + * allocated. + * Do notforget to round up to the nearest 4-entry quanta. + * If the L2 is beingsized to match the burst cap (instead of the entire + * Fif queue size) donot forget to multiply the quotient+1 by four (or by 5 + * ifprvTekModePrefetch is set) when operating in Teknovus mode. + * There arefour burst cap values reported in Teknovus modeNote: + * This register cannot be programmed "on-the-fly". + * The queuestart/end address values should be changed only when its + * associatedclear L2 report FIFO" bit is set. + */ +#define EPN_TX_L2S_QUE_CONFIGx_8_31_REG(x) (0x638 + (x) * 0x4) + +/* Queue 8 End address */ +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUEEND8_SHIFT 16 +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUEEND8_MASK 0xfff0000 + +/* Queue 8 Start address */ +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUESTART8_SHIFT 0 +#define TX_L2S_QUE_CONFIGx_8_31_CFGL2SQUESTART8_MASK 0xfff + + +/* + * Registers - is [ 0 => 24 ] + * + * This register configures the maximum number of bytes that L2 queue 8can + * transmit during any given round. + * A round ends when all L2 queueshave reached their respective burst limit + * or there is no more data totransmit. + * Note that setting a burst limit to zero enables therespective L2 queue + * to transmit in strict priority. + * Also, any burstlimits that are set to 1 will cause those L2 queues to + * transmit inround-robin" fashion. + * It is possible to allocate bandwidth as apercentage. + * Simply multiply the desired percentage by 2000 bytes (themaximum frame + * length) and write that value in the associated burstlimit register. + * Example bandwidth sharing configuration: + * Priority Burst Limit Description-------- ----------- ------------0 0 + * High priority unlimited bandwidth1 0 Low priority unlimited bandwidth2 1 + * Equal priority UNI 1 unlimited bandwidth3 1 Equal priority UNI 2 + * unlimited bandwidth4 1 Equal priority UNI 3 unlimited bandwidth5 1 Equal + * priority UNI 4 unlimited bandwidth6 0 High priority best effort + * bandwidth7 0 Low priority best effort bandwidthPriority 0 is for the + * highest priority traffic. + * i. + * e. + * , ManagementtrafficPriority 1 is for real-time traffic. + * i. + * e. + * , VOIPPriorities 2, 3, 4 and 5 equally share bandwidth, i. + * e. + * Premium businesstraffic. + * Priorities 6 and 7 provide two classes of best effort traffic, i. + * e. + * twoclasses of consumer trafficPlease note that the EPN shaper is the + * mechanism used to limit theamount of traffic. + */ +#define EPN_TX_CTC_BURST_LIMITx_8_31_REG(x) (0x698 + (x) * 0x4) + +/* L2 queue 8 CTC mode burst limit */ +#define TX_CTC_BURST_LIMITx_8_31_PRVBURSTLIMIT8_SHIFT 0 +#define TX_CTC_BURST_LIMITx_8_31_PRVBURSTLIMIT8_MASK 0x3ffff + + +/* + * Registers - is [ 0 => 48 ] + * + * How many additional Time Quanta the queue sets should use in 10G mode. + * This feature is intended to be used inSIEPON mode. + */ +#define EPN_10G_ABC_SIZEx_REG(x) (0x6f8 + (x) * 0x4) + +/* + * How many additional Time Quanta LLID 0 queue set 2 should use in + * 10Gmode. + * If all three ABC registers are non-zero; this LLID's effective burstcap + * will be: + * burstCap0 + cfgAddBurstCap0_1 + cfgAddBurstCap0_2 +cfgAddBurstCap0_3. + * Units are Time Quanta. +*/ +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_2_SHIFT 16 +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_2_MASK 0xffff0000 + +/* + * How many additional Time Quanta LLID 0 queue set 1 should use in + * 10Gmode. + * If all three ABC registers are non-zero; this LLID's effective burstcap + * will be: + * burstCap0 + cfgAddBurstCap0_1 + cfgAddBurstCap0_2 +cfgAddBurstCap0_3. + * Units are Time Quanta. +*/ +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_1_SHIFT 0 +#define EPN_10G_ABC_SIZEx_CFGADDBURSTCAP0_1_MASK 0xffff + + +#endif /* ! EPON_EPN_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_onu_mac_addr.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_onu_mac_addr.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_onu_mac_addr.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_onu_mac_addr.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,22 @@ +#ifndef EPON_EPN_ONU_MAC_ADDR_H_ +#define EPON_EPN_ONU_MAC_ADDR_H_ + +/* relative to epon */ + +/* + * Register + * + * These registers store a MAC address for each bidirectional ONU LLID. + * These addresses are inserted as the SA in REPORT frames sent upstream. + * Note: + * ONU MAC Address registers 8 through 23 are used only in + * loopbackoperation. + */ + +#define EPN_ONU_MAC_ADDRx_0_7_LO_REG(x) (0x1f0 + (x) * 8) +#define EPN_ONU_MAC_ADDRx_0_7_HI_REG(x) (0x1f4 + (x) * 8) + +#define EPN_ONU_MAC_ADDRx_8_31_LO_REG(x) (0x458 + (x) * 8) +#define EPN_ONU_MAC_ADDRx_8_31_HI_REG(x) (0x45c + (x) * 8) + +#endif /* ! EPON_EPN_ONU_MAC_ADDR_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_tx_l1s_shp.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_tx_l1s_shp.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epn_tx_l1s_shp.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epn_tx_l1s_shp.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,53 @@ +#ifndef EPON_EPN_TX_L1S_SHP_H_ +#define EPON_EPN_TX_L1S_SHP_H_ + +/* relative to epon */ + +/* + * Register + * + * This register configures upstream shaper i. + * There are 32 shapersavailable for shaping upstream traffic. + * The cfgShpEn bits are bit wiseselects for enabling shaping of the + * associated queues. + * Each shaper canhave shaping enabled on select queues or on all of the + * queues. + * If thebit is set, the corresponding shaper will be used for shaping + * creditsand control of its associated queue. + * The cfgShpRate and cfgMaxBstSizedefine the shaping. + * The cfgShpRate value represents the number of bytesthat are added to the + * shaper's byte credit accumulator each clockcycle. + * Given a 125 MHz clock-cycle; the cfgShpRate is in units of 2^-19Gbps + * (~1907. + * 34863 bps). + * The maximum burst size is in units of 256bytes. + */ +#define EPN_TX_L1S_SHP_CONFIGx_0_7_REG(x) (0x238 + (x) * 8) + +/* Shaper i Rate */ +#define CONFIG_CFGSHPRATE_SHIFT 8 +#define CONFIG_CFGSHPRATE_MASK 0x7fffff00 + +/* Shaper i Maximum Burst Size */ +#define CONFIG_CFGSHPBSTSIZE_SHIFT 0 +#define CONFIG_CFGSHPBSTSIZE_MASK 0xff + + +/* + * Register + * + * The bit wise selects for enabling shaping of the associated queues. + * Each shaper can have shaping enabled on select queues or on all of + * thequeues. + * If the bit is set, the corresponding shaper will be used forshaping + * credits and control of its associated queue. + */ +#define EPN_TX_L1S_SHP_QUE_ENx_0_7_REG(x) (0x23c + (x) * 8) +#define EPN_TX_L1S_SHP_QUE_EN_REG 0x4 + +/* Set the bit(s) corresponding to the queue(s) this shaper shouldpolice. */ +#define QUE_EN_CFGSHPEN_SHIFT 0 +#define QUE_EN_CFGSHPEN_MASK 0xffffffff + + +#endif /* ! EPON_EPN_TX_L1S_SHP_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epon_top.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epon_top.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_epon_top.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_epon_top.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,306 @@ +#ifndef EPON_EPON_TOP_H_ +#define EPON_EPON_TOP_H_ + +/* relative to epon */ +#define EPON_TOP_OFFSET_0 0x0 + +/* + * Register + * + * Register used for testing read and write access into epon_top block. + */ +#define EPON_TOP_SCRATCH_REG 0x0 + +/* Scratch pad. */ +#define SCRATCH_SCRATCH_SHIFT 0 +#define SCRATCH_SCRATCH_MASK 0xffffffff + + +/* + * Register + * + */ +#define EPON_TOP_RESET_REG 0x4 + +/* Active low reset for XPcsRx module. */ +#define RESET_XPCSRXRST_N_MASK 0x80 + +/* Active low reset for XPcsTx module. */ +#define RESET_XPCSTXRST_N_MASK 0x40 + +/* Active low reset for XIF module. */ +#define RESET_XIFRST_N_MASK 0x20 + +/* Active low reset for Tod module. */ +#define RESET_TODRST_N_MASK 0x10 + +/* Active low reset for ClkPrgSwch module. */ +#define RESET_CLKPRGRST_N_MASK 0x8 + +/* Active low reset for Nco module. */ +#define RESET_NCORST_N_MASK 0x4 + +/* Active low reset for Lif module. */ +#define RESET_LIFRST_N_MASK 0x2 + +/* Active low reset for Epn module. */ +#define RESET_EPNRST_N_MASK 0x1 + + +/* + * Register + * + * Top level interrupts for all EPON blocks. + */ +#define EPON_TOP_INTERRUPT_REG 0x8 + +/* Interrupt from 1 pps input. */ +#define INTERRUPT_INT_1PPS_MASK 0x80 + +/* Interrupt from XPcsTx module. */ +#define INTERRUPT_INT_XPCS_TX_MASK 0x40 + +/* Interrupt from XPcsRx module. */ +#define INTERRUPT_INT_XPCS_RX_MASK 0x20 + +/* Interrupt from XIF module. */ +#define INTERRUPT_INT_XIF_MASK 0x10 + +/* Interrupt from NCO module. */ +#define INTERRUPT_INT_NCO_MASK 0x8 + +/* Interrupt from LIF module. */ +#define INTERRUPT_INT_LIF_MASK 0x4 + +/* Interrupt from EPN module. */ +#define INTERRUPT_INT_EPN_MASK 0x1 + + +/* + * Register + * + * Top level interrupts for all EPON blocks. + * For any bit, a value of 1will enable the interrupt, and a value of 0 + * will mask the interrupt. + * By default, all interrupts are masked. + */ +#define EPON_TOP_INTERRUPT_MASK_REG 0xc + +/* Mask for interrupt from 1 pps input. */ +#define INTERRUPT_MASK_INT_1PPS_MASK_MASK 0x80 + +/* Mask for interrupt from XPcsTx module. */ +#define INTERRUPT_MASK_INT_XPCS_TX_MASK_MASK 0x40 + +/* Mask for interrupt from XPcsRx module. */ +#define INTERRUPT_MASK_INT_XPCS_RX_MASK_MASK 0x20 + +/* Mask for interrupt from XIF module. */ +#define INTERRUPT_MASK_INT_XIF_MASK_MASK 0x10 + +/* Mask for interrupt from NCO module. */ +#define INTERRUPT_MASK_INT_NCO_MASK_MASK 0x8 + +/* Mask for interrupt from LIF module. */ +#define INTERRUPT_MASK_INT_LIF_MASK_MASK 0x4 + +/* Mask for interrupt from EPN module. */ +#define INTERRUPT_MASK_INT_EPN_MASK_MASK 0x1 + + +/* + * Register + * + * High level configuration for the EPON block. + */ +#define EPON_TOP_CONTROL_REG 0x10 + +/* + * 0:1G downstream mode + * 1:2G downstream mode +*/ +#define CONTROL_CFGTWOGIGPONDNS_MASK 0x4 + +/* + * 0: + * 1G uptream mode 1: + * 10G upstream mode +*/ +#define CONTROL_CFGTENGIGPONUP_MASK 0x2 + +/* + * 0: + * 1G downstream mode 1: + * 10G downstream mode +*/ +#define CONTROL_CFGTENGIGDNS_MASK 0x1 + + +/* + * Register + * + * High level configuration for the EPON block. + */ +#define EPON_TOP_ONE_PPS_MPCP_OFFSET_REG 0x14 + +/* Provides additional offset to MPCP sampling due to 1 pps inputassertion. */ +#define ONE_PPS_MPCP_OFFSET_CFG_1PPS_MPCP_OFFSET_SHIFT 0 +#define ONE_PPS_MPCP_OFFSET_CFG_1PPS_MPCP_OFFSET_MASK 0xffffffff + + +/* + * Register - read-only + * + * High level configuration for the EPON block. + */ +#define EPON_TOP_ONE_PPS_CAPTURED_MPCP_TIME_REG 0x18 + +/* Captured MPCP time due to 1 pps input assertion. */ +#define ONE_PPS_CAPTURED_MPCP_TIME_CAPTURE_1PPS_MPCP_TIME_SHIFT 0 +#define ONE_PPS_CAPTURED_MPCP_TIME_CAPTURE_1PPS_MPCP_TIME_MASK 0xffffffff + + +/* + * Register + * + * Register used for 48-bit timestamp Time Of Day (TOD) configuration. + */ +#define EPON_TOP_TOD_CONFIG_REG 0x1c + +/* + * When this bit is set, hardware will update the internal + * nanosecondcounter, cfg_tod_ns[31: + * 0], when the local MPCP time equalscfg_tod_mpcp[31: + * 0]. + * Software should set this bit and wait untilhardware clears it before + * setting it again. +*/ +#define TOD_CONFIG_CFG_TOD_LOAD_NS_MASK 0x80000000 + +/* + * When this bit is set, hardware will latch the internal ts48, ns, + * andseconds counters. + * Software should set this bit and wait untilhardware clears it before + * setting it again. + * Once hardware hascleared the bit, the timers are available to be read. +*/ +#define TOD_CONFIG_CFG_TOD_READ_MASK 0x800000 + +/* + * Select the block to read the timers from. + * 0: + * Reserved. + * 1: + * 1G EPON. + * 2: + * 10G EPON. + * 3: + * AE. + * This field should not be changed whilecfg_tod_read is set. +*/ +#define TOD_CONFIG_CFG_TOD_READ_SEL_SHIFT 21 +#define TOD_CONFIG_CFG_TOD_READ_SEL_MASK 0x600000 + +/* + * Allow 1PPS pulse to clear the counter if set. + * If not set, the 1PPSpulse will have no effect on the TS48. +*/ +#define TOD_CONFIG_CFG_TOD_PPS_CLEAR_MASK 0x100000 + +/* + * The rising edge will be latched, and cfg_tod_seconds will be loadedon + * the next 1PPS pulse or when the next second rolls over. +*/ +#define TOD_CONFIG_CFG_TOD_LOAD_MASK 0x80000 + +/* Number of seconds to be loaded. */ +#define TOD_CONFIG_CFG_TOD_SECONDS_SHIFT 0 +#define TOD_CONFIG_CFG_TOD_SECONDS_MASK 0x7ffff + + +/* + * Register + * + * Register used to load nanosecond counter. + */ +#define EPON_TOP_TOD_NS_REG 0x20 + +/* + * Value to be loaded when the MPCP time reaches cfg_tod_mpcp. + * Thisfield should not be updated while cfg_tod_load_ns is set. +*/ +#define TOD_NS_CFG_TOD_NS_SHIFT 0 +#define TOD_NS_CFG_TOD_NS_MASK 0xffffffff + + +/* + * Register + * + * Register used to hold MPCP value that will be used to determine whenthe + * nanosecond counter is updated. + * This field should not be updatedwhile cfg_tod_load_ns is set. + */ +#define EPON_TOP_TOD_MPCP_REG 0x24 + +/* MPCP value to wait for before loading cfg_tod_ns. */ +#define TOD_MPCP_CFG_TOD_MPCP_SHIFT 0 +#define TOD_MPCP_CFG_TOD_MPCP_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back + * fromEPON/AE block. + */ +#define EPON_TOP_TS48_MSB_REG 0x28 + +/* Upper 16-bits of TS48. */ +#define TS48_MSB_TS48_EPON_READ_MSB_SHIFT 0 +#define TS48_MSB_TS48_EPON_READ_MSB_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back + * fromEPON/AE block. + */ +#define EPON_TOP_TS48_LSB_REG 0x2c + +/* Lower 32-bits of TS48. */ +#define TS48_LSB_TS48_EPON_READ_LSB_SHIFT 0 +#define TS48_LSB_TS48_EPON_READ_LSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for seconds read back from EPON/AE block. + */ +#define EPON_TOP_TSEC_REG 0x30 + +/* + * Seconds[18: + * 0]. +*/ +#define TSEC_TSEC_EPON_READ_SHIFT 0 +#define TSEC_TSEC_EPON_READ_MASK 0x7ffff + + +/* + * Register - read-only + * + * Register used for nanoseconds read back from EPON/AE block. + */ +#define EPON_TOP_TNS_EPON_REG 0x34 + +/* + * Nanoseconds[31: + * 0]. +*/ +#define TNS_EPON_TNS_EPON_READ_SHIFT 0 +#define TNS_EPON_TNS_EPON_READ_MASK 0xffffffff + + +#endif /* ! EPON_EPON_TOP_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_lif.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_lif.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_lif.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_lif.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,2489 @@ +#ifndef EPON_LIF_H_ +#define EPON_LIF_H_ + +/* relative to epon */ +#define LIF_OFFSET_0 0x1800 + +/* + * Register + * + * This register controls and configures the LIF PON module. + * Configurationbits dealing directly with the operational mode, laser + * control, andloopback are here. + */ +#define LIF_PON_CONTROL_REG 0x0 + +/* Enable adaptive short preamble for P2P mode. */ +#define LIF_PON_CONTROL_CFP2PMODEADAPTIVESHORTPRE_MASK 0x40000000 + +/* Disable runt packet filtering. */ +#define LIF_PON_CONTROL_CFGDISRUNTFILTER_MASK 0x20000000 + +/* + * Maximum number of allowable comma errors before LOS is asserted. + * 0: + * Functionality Disabled +*/ +#define LIF_PON_CONTROL_CFMAXCOMMAERRCNT_SHIFT 25 +#define LIF_PON_CONTROL_CFMAXCOMMAERRCNT_MASK 0x1e000000 + +/* + * Selects between three 802. + * 3 synchronization state machines: + * 0: + * 802. + * 3ah-65 FEC (single code word traversal)1: + * 802. + * 3-36 non FEC (single code word traversal)2: + * Legacy (based on FEC, but traverses state machine two code wordsat a + * time). + * 3: + * Reserved +*/ +#define LIF_PON_CONTROL_CFSYNCSMSELECT_SHIFT 23 +#define LIF_PON_CONTROL_CFSYNCSMSELECT_MASK 0x1800000 + +/* + * Force aborts any NonFec frames in the PON module. + * This abort occursbefore the FecRx module; therefore any frames dropped + * at this pointwill not have statistics tabulated. + * 0: + * Disabled1: + * Enabled +*/ +#define LIF_PON_CONTROL_CFPONRXFORCENONFECABORT_MASK 0x400000 + +/* + * Force aborts any FEC frames in the PON module. + * This abort occursbefore the FecRx module; therefore any frames dropped + * at this pointwill not have statistics tabulated. + * 0: + * Disabled1: + * Enabled +*/ +#define LIF_PON_CONTROL_CFPONRXFORCEFECABORT_MASK 0x200000 + +/* + * Controls the order of the 10B/20B sent from the SERDES to the LIFmodule. + * 0: + * Receive data is unflipped. + * 1: + * Receive data is flipped. + * Default : + * 1 +*/ +#define LIF_PON_CONTROL_CFGRXDATABITFLIP_MASK 0x100000 + +/* + * Enable upstream padding of MPCP/OAM in an 802. + * 1ae encrypted link toinclude security overhead. +*/ +#define LIF_PON_CONTROL_CFGENMPCPOAMPAD_MASK 0x40000 + +/* Enable IDLE packet support to prevent upstream underrun. */ +#define LIF_PON_CONTROL_CFGENTXIDLEPKT_MASK 0x20000 + +/* + * Lock synchronization state indefinitely. + * This bit must be used inconjunction with cfEnableExtendSync. +*/ +#define LIF_PON_CONTROL_CFENABLESOFTWARESYNCHOLD_MASK 0x10000 + +/* + * Extend synchronization state. + * This can be used to improve FEC gain. +*/ +#define LIF_PON_CONTROL_CFENABLEEXTENDSYNC_MASK 0x8000 + +/* + * Allow alignment state machine to achieve code word lock in threeidles, + * as opposed to four. +*/ +#define LIF_PON_CONTROL_CFENABLEQUICKSYNC_MASK 0x4000 + +/* + * No function in this release of EPON. + * Default: + * 1 +*/ +#define LIF_PON_CONTROL_CFPPSEN_MASK 0x2000 + +/* + * 0: + * 1PPS is not aligned to the 10MHz clock. + * 1: + * 1PPS is aligned to the positive edge of the 10MHz clock. + * Default: + * 1 +*/ +#define LIF_PON_CONTROL_CFPPSCLKRBC_MASK 0x1000 + +/* + * 0: + * Disable Loop Back from Downstream to Upstream in the LIF. + * 1: + * Enable Loop Back from Downstream to Upstream in the LIF. +*/ +#define LIF_PON_CONTROL_CFRX2TXLPBACK_MASK 0x800 + +/* + * 0: + * Disable Loop Back from Upstream to Downstream in the LIF. + * 1: + * Enable Loop Back from Upstream to Downstream in the LIF. + * Note: + * Due to a bug in BCM6838A0, RX stats will not tabulatecorrectly while in + * this loopback mode. + * TX stats should be usedinstead. +*/ +#define LIF_PON_CONTROL_CFTX2RXLPBACK_MASK 0x400 + +/* + * 0: + * IDLE words continue to transmit while laser is turned off. + * 1: + * Transmitted data bus is de-asserted to zero when laser is turnedoff. +*/ +#define LIF_PON_CONTROL_CFTXDATAENDURLON_MASK 0x200 + +/* + * 0: + * LIF sends standard EPON Preamble. + * 1: + * LIF sends Ethernet Preamble for Point-to-Point operation. +*/ +#define LIF_PON_CONTROL_CFP2PMODE_MASK 0x100 + +/* + * 0: + * Send Standard P2P Ethernet Preamble. + * 1: + * Send Short (7 byte) P2P Ethernet Preamble. + * This bit must be setwith cfP2PMode if full line rate is desired with odd + * sized frames. + * If this bit is not set in P2P mode, only even sized frames arecapable of + * line rate. + * The link partner must also be short preamblereceive capable. +*/ +#define LIF_PON_CONTROL_CFP2PSHORTPRE_MASK 0x80 + +/* + * The output enable control for the 1Gbps upstream laser control(TXEN) + * pin. + * 0: + * 1G laser control pin is tri-stated1: + * 1G laser control is driven by the LIF module. +*/ +#define LIF_PON_CONTROL_CFLASEREN_MASK 0x40 + +/* + * 0: + * Laser is turned on at grant start time. + * 1: + * Laser is turned on continuously. +*/ +#define LIF_PON_CONTROL_CFTXLASERON_MASK 0x20 + +/* + * 0: + * Configures the Laser On signal as active low. + * 1: + * Configures the Laser On signal as active high. +*/ +#define LIF_PON_CONTROL_CFTXLASERONACTHI_MASK 0x10 + +/* + * Resets the transmit side of the LIF. + * 0: + * Reset LIF TX. + * 1: + * Normal operation. +*/ +#define LIF_PON_CONTROL_LIFTXRSTN_PRE_MASK 0x8 + +/* + * Resets the receive side of the LIF. + * 0: + * Reset LIF RX. + * 1: + * Normal operation. +*/ +#define LIF_PON_CONTROL_LIFRXRSTN_PRE_MASK 0x4 + +/* + * Enables LIF TX for operation. + * 0: + * Disable the external interface to and from the LIF TX. + * 1: + * Enable the external interface to and from the LIF TX. +*/ +#define LIF_PON_CONTROL_LIFTXEN_MASK 0x2 + +/* + * Enables LIF RX for operation. + * 0: + * Disable the external interface to and from the LIF RX. + * 1: + * Enable the external interface to and from the LIF RX. +*/ +#define LIF_PON_CONTROL_LIFRXEN_MASK 0x1 + + +/* + * Register + * + * This register controls and configures the LIF PON module + * specificallydealing with interoperability. + */ +#define LIF_PON_INTER_OP_CONTROL_REG 0x4 + +/* + * Units are in code group pairs (two 10b code groups). + * 0: + * Disable Ipg Filter (Legacy Behavior)1-3: + * DO NOT USE, Illegal Values, allows faster than line rateoperation. + * 4-15: + * Allow 4 to 15 code group pairs to elapse after a frame beforebecoming + * receptive to a SOP or SFEC again. + * Default: + * 5 code group pairs or "10 bytes of IPG". + * Per spec, "12bytes of IPG" is line rate, but thedefault setting allows + * for a rate that is slightly faster than linerate for tolerance purposes. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFIPGFILTER_SHIFT 27 +#define LIF_PON_INTER_OP_CONTROL_CFIPGFILTER_MASK 0x78000000 + +/* + * Allows for control of logic which blocks laser enable based oncondition + * of downstream sync. + * 0: + * Allow for los to block laser enable. + * 1: + * Laser will toggle regardless of state of downstream code groupsync +*/ +#define LIF_PON_INTER_OP_CONTROL_CFDISABLELOSLASERBLOCK_MASK 0x4000000 + +/* + * All unmapped LLIDs will be redirected and mapped to Index 0. + * 0: + * Unmapped LLIDs will appear to be unmapped to EPN. + * 1: + * Unmapped LLIDs will appear on Index 0 to EPN. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFGLLIDPROMISCUOUSMODE_MASK 0x2000000 + +/* + * Masks MSB of 16 bit raw LLID for Index translation. + * 0: + * Don't mask, look at full 16 bits. + * 1: + * Mask bit[15], map based on [14: + * 0]. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFGLLIDMODMSK_MASK 0x1000000 + +/* + * Allows SFEC to consume 4 bytes of IPG per standard. + * 0: + * 4 Additional bytes of IPG will be added for SFEC. + * 1: + * SFEC will carve 4 bytes out of existing IPG. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFUSEFECIPG_MASK 0x800000 + +/* + * Enable inverted CRC-8 checking. + * 0: + * Disable CRC-8 checking. + * Packets with inverted CRC-8 arediscarded. + * 1: + * Enable CRC-8 checking. + * Packets with inverted CRC-8 are consideredvalid. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8INVCHK_MASK 0x400000 + +/* + * 0: + * CRC-8 is checked from LSB to MSB in the downstream direction. + * 1: + * CRC-8 is checked from MSB to LSB in the downstream direction. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8BITSWAP_MASK 0x200000 + +/* + * 0: + * CRC-8 is checked by shifting data from MSB to LSB in thedownstream + * direction. + * 1: + * CRC-8 is checked by shifting data from LSB to MSB in thedownstream + * direction. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8MSB2LSB_MASK 0x100000 + +/* + * 0: + * Enable Crc-8 checking. + * 1: + * Disable Crc-8 checking. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFRXCRC8DISABLE_MASK 0x80000 + +/* + * 0: + * Bit 15 of LLID in the upstream path is zero. + * 1: + * Bit 15 of LLID in the upstream path is set. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXLLIDBIT15SET_MASK 0x20000 + +/* + * 0: + * Transmit correct Crc-81: + * Transmit inverted Crc-8 on a per packet basis. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8INV_MASK 0x10000 + +/* + * 0: + * Transmit correct Crc-81: + * Transmit bad Crc-8 +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8BAD_MASK 0x8000 + +/* + * 0: + * Generated upstream Crc-8 byte is transmitted from Lsb to Msb. + * 1: + * Generated upstream Crc-8 byte is transmitted from Msb to Lsb. + * Note: + * This feature is added to give the ONU more flexibility oftransmitting + * the Crc-8 byte. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8BITSWAP_MASK 0x4000 + +/* + * 0: + * Generate upstream Crc-8 by shifting data from Lsb to Msb. + * 1: + * Generate upstream Crc-8 by shifting data from Msb to Lsb. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXCRC8MSB2LSB_MASK 0x2000 + +/* + * 0: + * Normal operation. + * 1: + * Enable the LIF module to transmit short pre-amble in the upstreampath. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXSHORTPRE_MASK 0x1000 + +/* + * LIF upstream IPG counter. + * Each unit represents one time quanta or16ns. + * Default: + * 2 +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXIPGCNT_SHIFT 8 +#define LIF_PON_INTER_OP_CONTROL_CFTXIPGCNT_MASK 0xf00 + +/* + * 0: + * Normal OperationGreater than 0: + * This bit field is used for testing with Panasonictransceivers. + * The pattern of 10'b10_1010_1010 (2AA) will transmit atthe beginning of + * every burst. + * The number transmitted word isprogrammable based on the configuration of + * cfInitIdle in register0x10d. + * The amount transmitted is always a portion of cfInitIdle upto a maximum + * of 16. +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXAASYNCLEN_SHIFT 4 +#define LIF_PON_INTER_OP_CONTROL_CFTXAASYNCLEN_MASK 0xf0 + +/* + * Pipeline delay to be added on to laser on time and laser off + * timeDefault: + * 6 +*/ +#define LIF_PON_INTER_OP_CONTROL_CFTXPIPEDELAY_SHIFT 0 +#define LIF_PON_INTER_OP_CONTROL_CFTXPIPEDELAY_MASK 0xf + + +/* + * Register + * + * This register controls and configures the LIF FEC sub-module block. + * Configuration bits dealing directly with forward error correction + * arehere. + */ +#define LIF_FEC_CONTROL_REG 0x8 + +/* + * 0: + * Uncorrectable frames are aborted. + * 1: + * Uncorrectable frames are forwarded. +*/ +#define LIF_FEC_CONTROL_CFFECRXERRORPROP_MASK 0x20 + +/* + * Aborts non-FEC frames after the FecRx module. + * Statistics will stillbe tabulated for frames aborted through this + * manner. + * 0: + * Non-FEC frames are forwarded. + * 1: + * Non-FEC frames are aborted. +*/ +#define LIF_FEC_CONTROL_CFFECRXFORCENONFECABORT_MASK 0x10 + +/* + * Aborts FEC frames after the FecRx module. + * Statistics will still betabulated for frames aborted through this + * manner. + * 0: + * FEC frames are forwarded. + * 1: + * FEC frames are aborted. +*/ +#define LIF_FEC_CONTROL_CFFECRXFORCEFECABORT_MASK 0x8 + +/* + * Enable FEC on Receiver0: + * FEC Disabled1: + * FEC Enabled +*/ +#define LIF_FEC_CONTROL_CFFECRXENABLE_MASK 0x4 + +/* + * Enables per LLID Fec Parity Generation. + * This bit, cfFecTxEn, corresponding llid enable bit + * cfFecTxFecLlidEn#below must be set. + * 0: + * Disabled1: + * Enabled +*/ +#define LIF_FEC_CONTROL_CFFECTXFECPERLLID_MASK 0x2 + +/* + * Enable FEC on Transmitter0: + * FEC Disabled1: + * FEC Enabled +*/ +#define LIF_FEC_CONTROL_CFFECTXENABLE_MASK 0x1 + + +/* + * Register + * + * This register controls and configures the LIF SEC sub-module block. + * Configuration bits dealing directly with security encryption are here. + */ +#define LIF_SEC_CONTROL_REG 0xc + +/* Disable OAM encryption. */ +#define LIF_SEC_CONTROL_CFGDISMPCPENCRYPT_MASK 0x80000000 + +/* Disable OAM encryption. */ +#define LIF_SEC_CONTROL_CFGDISOAMENCRYPT_MASK 0x40000000 + +/* Enables downstream security short length support. */ +#define LIF_SEC_CONTROL_CFGSECENSHORTLEN_MASK 0x20000000 + +/* Enables downstream security packet number rollover. */ +#define LIF_SEC_CONTROL_CFGSECDNENPKTNUMRLOVR_MASK 0x10000000 + +/* Enables upstream security packet number rollover. */ +#define LIF_SEC_CONTROL_CFGSECUPENPKTNUMRLOVR_MASK 0x8000000 + +/* Enables replay protection on RX security. */ +#define LIF_SEC_CONTROL_CFGENAEREPLAYPRCT_MASK 0x4000000 + +/* Enables legacy RCC priority encoding mode for EPON encryption. */ +#define LIF_SEC_CONTROL_CFGENLEGACYRCC_MASK 0x2000000 + +/* + * Enables fake AES mode in the upstream for FPGA testing. + * 0: + * Normal operation. + * 1: + * Enable fake AES. +*/ +#define LIF_SEC_CONTROL_ENFAKEUPAES_MASK 0x1000000 + +/* + * Enables fake AES mode in the downstream for FPGA testing. + * 0: + * Normal operation. + * 1: + * Enable fake AES. +*/ +#define LIF_SEC_CONTROL_ENFAKEDNAES_MASK 0x800000 + +/* + * FEC IPG Len used by SEC to support certain security modes. + * Default: + * 0xa +*/ +#define LIF_SEC_CONTROL_CFGFECIPGLEN_SHIFT 13 +#define LIF_SEC_CONTROL_CFGFECIPGLEN_MASK 0x1fe000 + +/* + * Disable downstream DA/SA encryption. + * 0: + * Enable DA/SA encryption1: + * Disable DA/SA encryption +*/ +#define LIF_SEC_CONTROL_DISDNDASAENCRPT_MASK 0x1000 + +/* + * 0: + * Single Churning encryption (do not use)1: + * Triple Churning encryptionThis bit matters only when dnEncryptScheme is + * set to "CEPON". + * Default: + * 1 +*/ +#define LIF_SEC_CONTROL_ENTRIPLECHURN_MASK 0x800 + +/* + * 0: + * In EPON mode, all packets must be either encrypted ornon-encrypted; a + * mixture of both is not allowed. + * The turning on/offof encryption can be initiated only by the OLT. + * 1: + * In EPON mode, mixing of encrypted and non-encrypted packets isallowed + * for a particular LLID. + * Default: + * 1 +*/ +#define LIF_SEC_CONTROL_ENEPNMIXENCRYPT_MASK 0x400 + +/* + * Disable upstream DA/SA encryption. + * 0: + * Enable DA/SA encryption1: + * Disable DA/SA encryption +*/ +#define LIF_SEC_CONTROL_DISUPDASAENCRPT_MASK 0x200 + +/* + * Defines the upstream security decryption scheme. + * 0: + * Teknovus encryption1: + * Reserved2: + * EPON encryption +*/ +#define LIF_SEC_CONTROL_SECUPENCRYPTSCHEME_SHIFT 7 +#define LIF_SEC_CONTROL_SECUPENCRYPTSCHEME_MASK 0x180 + +/* + * Defines the downstream security decryption scheme. + * 0: + * Teknovus encryption1: + * Reserved2: + * EPON encryption3: + * CEPON encryption4: + * Zero-overhead encryption5: + * AE encryption +*/ +#define LIF_SEC_CONTROL_SECDNENCRYPTSCHEME_SHIFT 4 +#define LIF_SEC_CONTROL_SECDNENCRYPTSCHEME_MASK 0x70 + +/* + * Resets upstream SEC. + * 0: + * Reset UP SEC. + * 1: + * Normal operation +*/ +#define LIF_SEC_CONTROL_SECUPRSTN_PRE_MASK 0x8 + +/* + * Resets downstream SEC. + * 0: + * Reset DN SEC. + * 1: + * Normal operation. +*/ +#define LIF_SEC_CONTROL_SECDNRSTN_PRE_MASK 0x4 + +/* + * Global enable for upstream encryption0: + * Disable upstream encryption. + * 1: + * Enable upstream encryption. +*/ +#define LIF_SEC_CONTROL_SECENUP_MASK 0x2 + +/* + * Global enable for downstream decryption0: + * Disable downstream decryption. + * 1: + * Enable downstream decryption. +*/ +#define LIF_SEC_CONTROL_SECENDN_MASK 0x1 + + +/* + * Register + * + * This register specifies the 802. + * 1ae MacSec Ethertype to be insertedinto the packet. + */ +#define LIF_MACSEC_REG 0x10 + +/* Defines the MacSec Ethertype. */ +#define LIF_MACSEC_CFGMACSECETHERTYPE_SHIFT 0 +#define LIF_MACSEC_CFGMACSECETHERTYPE_MASK 0xffff + + +/* + * Register + * + * This register contains interrupt status for LIF modules. + * These bits are sticky; to clear a bit, write 1 to it. + */ +#define LIF_INT_STATUS_REG 0x14 + +/* + * [NON-FATAL]Indicates that an SOP or SFEC was detected in an IPG window + * inexcess of what was provisioned in cfIpgFilter. + * Please seecfIpgFilter for more details. +*/ +#define LIF_INT_STATUS_INT_SOP_SFEC_IPG_VIOLATION_MASK 0x200000 + +/* + * Indicates laser enable on time exceeed the maximum threshold, asdefined + * by register LIF_LSR_MON_A_MAX_THR. +*/ +#define LIF_INT_STATUS_LASERONMAX_MASK 0x100000 + +/* Indicates laser enable deassertion. */ +#define LIF_INT_STATUS_LASEROFF_MASK 0x80000 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thereceived packet was aborted due to replay protection. +*/ +#define LIF_INT_STATUS_SECDNREPLAYPROTCTABORT_MASK 0x40000 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thetransmit packet number exceeded the maximum threshold and + * about tooverflow. + * Threshold is programmed in register LIF_AE_PKTNUM_THRESH. +*/ +#define LIF_INT_STATUS_SECUPPKTNUMOVERFLOW_MASK 0x20000 + +/* + * [NON-FATAL]Laser was turned off in the middle of a burst. + * This usuallyindicates misconfiguration which results in EPN + * "overstuffing" aburst. + * Note: + * This interrupt will fire while in P2P or in DN2UP Loopbackmode. + * S/W is to mask this bit during those modes. + * A fix may beintroduced into later revisions of chip to fix this cosmetic + * issue(FLEXIPON-138). +*/ +#define LIF_INT_STATUS_INTLASEROFFDURBURST_MASK 0x10000 + +/* + * [NON-FATAL]Line code error threshold was exceeded. + * Program with LIF RX BER Threshold and Interval register (0x1b4) +*/ +#define LIF_INT_STATUS_INTRXBERTHRESHEXC_MASK 0x8000 + +/* The LIF detected a FEC receive frame. */ +#define LIF_INT_STATUS_INTFECRXFECRECVSTATUS_MASK 0x4000 + +/* + * [FATAL] Error location FIFO in Corrector logic has overflowed; somedata + * blocks will go uncorrected. + * This is considered a fatal interrupt because this introduces FECblock + * level inconsistencies, which may cause the correction of thewrong + * blocks. +*/ +#define LIF_INT_STATUS_INTFECRXCORERRFIFOFULLSTATUS_MASK 0x2000 + +/* + * Error location FIFO in Corrector logic has gone empty beforefinishing a + * FEC frame. + * This is considered a fatal interrupt becausethis introduces FEC block + * level inconsistencies, which may cause thecorrection of the wrong + * blocks. +*/ +#define LIF_INT_STATUS_INTFECRXCORERRFIFOUNEXPEMPTY_MASK 0x1000 + +/* + * [FATAL] Data was popped from an empty FEC Buffer pipeline, + * whichsimultaneously was having data pushed into it from the FEC + * BufferSRAM. +*/ +#define LIF_INT_STATUS_INTFECBUFPOPEMPTYPUSH_MASK 0x800 + +/* + * [FATAL] Data was popped from an empty FEC Buffer pipeline, + * whichsimultaneously no data was being pushed into the pipeline from + * theFEC Buffer SRAM. +*/ +#define LIF_INT_STATUS_INTFECBUFPOPEMPTYNOPUSH_MASK 0x400 + +/* + * [FATAL] Data was read from FEC Buffer SRAM and pushed into a fullFEC + * Buffer pipeline. + * This is fatal. + * Write a one to clear this bit. +*/ +#define LIF_INT_STATUS_INTFECBUFPUSHFULL_MASK 0x200 + +/* + * [NON-FATAL] Gate frame's MPCP timestamp vastly different thancurrent + * MPCP time. + * Triggered afull timestamp update. +*/ +#define LIF_INT_STATUS_INTUPTIMEFULLUPDSTAT_MASK 0x100 + +/* + * [FATAL] LIF detects a frame from Epn Utx that should be first frameof + * the burst but it is not. +*/ +#define LIF_INT_STATUS_INTFROUTOFALIGNSTAT_MASK 0x80 + +/* + * [FATAL] LIF detects a grant start time that is less than its + * currenttimer. +*/ +#define LIF_INT_STATUS_INTGRNTSTARTTIMELAGSTAT_MASK 0x40 + +/* [NON-FATAL] LIF had to abort frames due to misalignment. */ +#define LIF_INT_STATUS_INTABORTRXFRMSTAT_MASK 0x20 + +/* [NON-FATAL] LIF detects an idle condition for received clock. */ +#define LIF_INT_STATUS_INTNORXCLKSTAT_MASK 0x10 + +/* + * [NON-FATAL] Lif detects a runaway frame. + * LIF could not detect an endof frame character for 64K clocks. +*/ +#define LIF_INT_STATUS_INTRXMAXLENERRSTAT_MASK 0x8 + +/* + * [NON-FATAL] LIF detects code error after it has successfullyacquired + * sync. +*/ +#define LIF_INT_STATUS_INTRXERRAFTALIGNSTAT_MASK 0x4 + +/* [NON-FATAL] LIF is successfully acquired sync. */ +#define LIF_INT_STATUS_INTRXSYNCHACQSTAT_MASK 0x2 + +/* + * [NON-FATAL] LIF is out of sync. + * This condition indicates that theLIF could not align to IDLE characters + * or it detects code errors. +*/ +#define LIF_INT_STATUS_INTRXOUTOFSYNCHSTAT_MASK 0x1 + + +/* + * Register + * + * This register contains interrupt masks for LIF modules. + */ +#define LIF_INT_MASK_REG 0x18 + +/* + * [NON-FATAL]Mask for int_sop_sfec_ipg_violation interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INT_SOP_SFEC_IPG_VIOLATION_MASK_MASK 0x200000 + +/* Mask. */ +#define LIF_INT_MASK_LASERONMAXMASK_MASK 0x100000 + +/* Mask. */ +#define LIF_INT_MASK_LASEROFFMASK_MASK 0x80000 + +/* Mask for replay protection abort interrupt */ +#define LIF_INT_MASK_SECDNREPLAYPROTCTABORTMSK_MASK 0x40000 + +/* Mask for packet number overflow interrupt */ +#define LIF_INT_MASK_SECUPPKTNUMOVERFLOWMSK_MASK 0x20000 + +/* + * Mask for laserOffDurBurstMask interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTLASEROFFDURBURSTMASK_MASK 0x10000 + +/* + * Mask for rxBerThreshExc interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXBERTHRESHEXCMASK_MASK 0x8000 + +/* + * Mask for fecRxFrmRecv interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECRXFECRECVMASK_MASK 0x4000 + +/* + * Mask for fecCorrErrFifFullMask interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECRXCORERRFIFOFULLMASK_MASK 0x2000 + +/* + * Mask for FecRxCorErrFifoUnExpEmpty interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECRXCORERRFIFOUNEXPEMPTYMASK_MASK 0x1000 + +/* + * Mask for fecBufPopEmptyPush interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECBUFPOPEMPTYPUSHMASK_MASK 0x800 + +/* + * Mask for fecBufPopEmptyNoPush interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECBUFPOPEMPTYNOPUSHMASK_MASK 0x400 + +/* + * Mask for fecBufPushFull interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFECBUFPUSHFULLMASK_MASK 0x200 + +/* + * Mask for upTimeFullUpdStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTUPTIMEFULLUPDMASK_MASK 0x100 + +/* + * Mask for frmOutOfAlignStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTFROUTOFALIGNMASK_MASK 0x80 + +/* + * Mask for grntStartTimeLagStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTGRNTSTARTTIMELAGMASK_MASK 0x40 + +/* + * Mask for rxFrmAbortStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTABORTRXFRMMASK_MASK 0x20 + +/* + * Mask for noRxClkStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTNORXCLKMASK_MASK 0x10 + +/* + * Mask for noRxClkStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXMAXLENERRMASK_MASK 0x8 + +/* + * Mask for rxErrAftAlignStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXERRAFTALIGNMASK_MASK 0x4 + +/* + * Mask for rxSynchAcqStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXSYNCHACQMASK_MASK 0x2 + +/* + * Mask for rxOutOfSyncStat interrupt. + * 0: + * Disabled -- don't toggle interrupt pin. + * 1: + * Enabled -- toggle interrupt pin. + * Default : + * 1 +*/ +#define LIF_INT_MASK_INTRXOUTOFSYNCHMASK_MASK 0x1 + + +/* + * Register + * + * This set of registers allows reading the LIF per-LLID statistics. + * Italso allows general access to the LIF internal RAMs. + * All RAMs areinitialized to zero upon hardware reset. + * The following describes dataport read/write sequences: + * Write cycle: + * 1) Write the address of the RAM entry to Offset 1. + * 2) Write data to be written to Offsets 2 through 5 (as requiredfor the + * given RAM's width). + * 3) Write to Offset 0 to select the RAM and to indicate Writecycle. + * 4) Poll on Offset 0 until the dataPortBusy bit is cleared. + * Read cycle: + * 1) Write the address of the RAM entry to Offset 1. + * 2) Write to Offset 0 to select the RAM and to indicate Read cycle. + * 3) Poll on Offset 0 until the dataPortBusy bit is cleared. + * 4) Read Offsets 2 through 5 (as needed according to the width ofthe + * accessed RAM) to retrieve the RAM read data. + * The following paragraphs describe the port data format for each RAM: + * Statistics Downstream Per LLID - Stores the statistics information + * foreach downstream LLID (32 bidirectional). + * The memory is auto-initialized within the hardware, and can be + * accessedas soon as the module is brought out of reset. + * The statistics arecleared on read. + * portData0[31: + * 0] - Desired statisticLLID Index RAM LocationsBidirectional 0 0 - + * 15Bidirectional 1 16 - 31. + * .. + * Bidirectional 30 480-495Bidirectional 31 496-511Table: + * RAM Offset Description Remarks0 Bidir Downstream Good Frames Received + * Not Aborted Prior toFEC1 Bidir Downstream Good Bytes Received Not + * Aborted Prior toFEC2 Bidir Downstream Oversized Frames As defined by + * LIFSanitizer Register (0x134)3 Bidir Downstream NonFEC Good Frames + * Received NonFEC Framesregardless of FEC Enable4 Bidir Downstream NonFEC + * Good Bytes Received NonFEC Bytesregardless of FEC Enable5 Bidir + * Downstream FEC Good Frames Received Will incrementeven if FEC is + * disabled. + * 6 Bidir Downstream FEC Good Bytes Received Will incrementeven if FEC is + * disabled. + * 7 Bidir Downstream FEC Frames Exceeded Error Threshold8 Bidir Downstream + * FEC Data Blocks No Errors9 Bidir Downstream FEC Data Blocks Corrected10 + * Bidir Downstream FEC Data Blocks Uncorrected11 Bidir Downstream FEC Data + * Corrected Bytes12 Bidir Downstream FEC Data Corrected Zeroes13 Bidir + * Downstream FEC Data Corrected Ones14 Bidir Downstream Undersized + * Frames15 Bidir Downstream Errored FramesSEC Downstream Key RAM - + * specifies the security key. + * When writing tothe key RAM, the mode and encryption key MUST be + * specified. + * All keysmust be written to EVEN offsets. + * For LLID X, the corresponding RAMoffset for the even key is X*2, while + * the odd key is (X*2) + 1. + * CEPON encryption mode: + * portData0 - Specifies input to 1st churning key generation. + * Bits [15: + * 0] specify P16 - P1; and bits [23: + * 16] specify X8 - X1. + * portData1 - Specifies input to 2nd churning key generation. + * The input is byte shift of 1st churning key. + * Bits [7: + * 0]specify P16 - P8; bits [15: + * 8] specify X8 - X1; andbits [23: + * 16] specify P7 - P1. + * portData2 - Specifies input to 3rd churning key generation. + * The input is byte shift of 2nd churning key. + * Bits [7: + * 0] specify X8 -X1; and bits [23: + * 8] specify P16 - P1. + * portData3 - Specifies P-input to churning function. + * Bits [15: + * 0]specify P16 - P1. + * Same data as portData0. + * Broadcom and NTT encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * 802. + * 1ae encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits implicit SCIportData5 - Specifies bits [127: + * 64] of the 64-bits implicit SCIportData6 - Specifies bits [31: + * 64] of the initial packet number forreplay protection. + * portData7[9] - encryption enable. + * When cleared, 802. + * 1ae packets willpass through undecrypted. + * Zero-ovehead encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits implicit SCIportData5 - Specifies bits [127: + * 64] of the 64-bits implicit SCIportData6 - Specifies bits [31: + * 64] of the initial packet number forreplay protection. + * SEC Upstream Key RAM - specifies the security key. + * When writing to thekey RAM, the mode and encryption key MUST be + * specified. + * Each LLIDoccupies 2 entries (N and N+1), ie. + * LLID Index 0 corresponds to entries0 and 1, while LLID Index 1 + * corresponds to entries 2 and 3. + * Controlinformation via portData4 will need to be conveyed to indicate to + * theSEC Receiver (OLT 1G RX) which key (0/1) will need to be loaded. + * Broadcom and NTT encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData7[8] - key number. + * portData7[9] - encryption enable. + * 802. + * 1ae encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits explicit SCI. + * portData5 - Specifies bits [127: + * 64] of the 64-bits explicit SCI. + * portData6 - Specifies bits [31: + * 64] of the initial packet number. + * portData7[7: + * 0] - TCI[7: + * 0]TCI[1: + * 0] - key number. + * In PON mode, only TCI[0] is utilized foreven/odd key. + * Must match key number specified in portData7[8]. + * In P2Pmode, TCI[1: + * 0]specifies 1 of 4 keys. + * TCI[3: + * 2] - encryption mode bits : + * TCI[3] - E encryption bit; TCI[2] -C change bit. + * - E=0; C=0 : + * Authentication only. + * Data is not encryption. + * Only ICV is inserted at the end of packet. + * - E=0; C=1 : + * Reserved. + * - E=1; C=0 : + * Reserved. + * - E=1; C=1 : + * Encryption/authentication. + * Data is encryptedand ICV inserted. + * TCI[4] - single copy broadcast. + * Set to 0. + * TCI[5] - SC specifies whether SecTag's SCI isimplicit(0)/explicit(1). + * TCI[6] - ES end station byte. + * Set to 0. + * TCI[7] - V version number. + * Set to 0. + * portData7[8] - key number. + * portData7[9] - encryption enable. + * Zero-ovehead encryption modesportData0 - Specifies bits [31: + * 0] of the 128-bits Encryption key. + * portData1 - Specifies bits [63: + * 32] of the 128-bits Encryption key. + * portData2 - Specifies bits [95: + * 64] of the 128-bits Encryption key. + * portData3 - Specifies bits [127: + * 96] of the 128-bits Encryption key. + * portData4 - Specifies bits [63: + * 0] of the 64-bits implicit SCI. + * portData5 - Specifies bits [127: + * 64] of the 64-bits implicit SCI. + * portData6 - Specifies bits [31: + * 64] of the initial packet number. + * portData7[8] - key number. + * portData7[9] - encryption enable. + */ +#define LIF_DATA_PORT_COMMAND_REG 0x1c + +/* + * Indicates access to RAM is in progress. + * 0: + * Data port is ready to accept a command1: + * Data port is busy +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_BUSY_MASK 0x80000000 + +/* + * 0 = Previous Data Port Operation Successful1 = Previous Data Port + * Operation Failed +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_ERROR_MASK 0x40000000 + +/* + * Selects the internal RAM for access: + * 0: + * Downstream Statistics (per-LLID)(256 x 32 bits)1: + * SEC Downstream Key (64 x 225 bits)2: + * FEC Downstream Data (2048 x 20 bits)*3: + * SEC Upstream Key (32 x 234 bits)5: + * FEC Downstream Partial Syndrome (16 x 136 bits)*6: + * FEC Downstream Full Syndrome (16 x 136 bits) *7: + * FEC Upstream Parity (16 x 128)*See LIF Data Port Data register for bit + * descriptions of these RAMs. + * * Module level resets must be active to access these rams. +*/ +#define LIF_DATA_PORT_COMMAND_RAM_SELECT_SHIFT 24 +#define LIF_DATA_PORT_COMMAND_RAM_SELECT_MASK 0x3f000000 + +/* + * Specifies RAM read or write operation. + * 0: + * Read1: + * Write2-255: + * NO OP +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_OP_CODE_SHIFT 16 +#define LIF_DATA_PORT_COMMAND_DATA_PORT_OP_CODE_MASK 0xff0000 + +/* + * Specifies the RAM address for the port operation. + * Note: + * This field is also used by the LIF memory initializationlogic, so it has + * a non-zero value after reset. + * Default: + * 0xffff +*/ +#define LIF_DATA_PORT_COMMAND_DATA_PORT_ADDR_SHIFT 0 +#define LIF_DATA_PORT_COMMAND_DATA_PORT_ADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 7 ] + * + */ +#define LIF_DATA_PORT_DATA_REG(x) (0x20 + (x) * 0x4) + +/* + * For write operations, the data to be written to the RAM location. + * For read operations, the data read back from the RAM location. +*/ +#define LIF_DATA_PORT_DATA_PBIPORTDATA_SHIFT 0 +#define LIF_DATA_PORT_DATA_PBIPORTDATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_0_7_REG(x) (0x40 + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 0. + * In downstream P2P, 802. + * 1ae mode, registersLIF_P2P_AE_SCI_LO[0: + * 15]/LIF_P2P_AE_SCI_HI[0: + * 15]provide lookup with packet's explicit SCI to an index. +*/ +#define LIF_LLIDx_0_7_CFGLLID0_SHIFT 0 +#define LIF_LLIDx_0_7_CFGLLID0_MASK 0x1ffff + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_16_23_REG(x) (0x60 + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 16. +*/ +#define LIF_LLIDx_16_23_CFGLLID16_SHIFT 0 +#define LIF_LLIDx_16_23_CFGLLID16_MASK 0x1ffff + + +/* + * Register + * + * This register provides programmable parameters for dynamic updates tothe + * MPCP timer. + */ +#define LIF_TIME_REF_CNT_REG 0x80 + +/* + * If the (absolute) difference between the timestamp received in aGATE + * message and the MPCP timer is larger than this value, then afull update" + * occurs: + * the downstream timestamp is transferred intothe MPCP timer. + * Default: + * 0x20 +*/ +#define LIF_TIME_REF_CNT_CFFULLUPDATEVALUE_SHIFT 16 +#define LIF_TIME_REF_CNT_CFFULLUPDATEVALUE_MASK 0xff0000 + +/* + * If the difference between the timestamp received in a GATE messageand + * the MPCP timer is negative AND larger than this value (but notlarger + * than cfFullUpdate) then the MPCP timer is held for one TQ(effectively + * decrementing it). + * Default: + * 0x2 +*/ +#define LIF_TIME_REF_CNT_CFMAXNEGVALUE_SHIFT 8 +#define LIF_TIME_REF_CNT_CFMAXNEGVALUE_MASK 0xff00 + +/* + * If the difference between the timestamp received in a GATE messageand + * the MPCP timer is positive AND larger than this value (but notlarger + * than cfFullUpdate) then the MPCP timer is incremented by twoTQ. + * Default: + * 0x4 +*/ +#define LIF_TIME_REF_CNT_CFMAXPOSVALUE_SHIFT 0 +#define LIF_TIME_REF_CNT_CFMAXPOSVALUE_MASK 0xff + + +/* + * Register + * + * This register provides the LIF the ability to filter MPCP + * timecorrections when the EPON MAC requests them too frequently. + * Thisregister specifies a time period after an update during which the + * LIFwill ignore MPCP time corrections from EPN. + */ +#define LIF_TIMESTAMP_UPD_PER_REG 0x84 + +/* + * Time period after an MPCP time correction during which LIF + * ignoresfurther MPCP time corrections. + * The units are TQ. +*/ +#define LIF_TIMESTAMP_UPD_PER_CFTIMESTAMPUPDPER_SHIFT 0 +#define LIF_TIMESTAMP_UPD_PER_CFTIMESTAMPUPDPER_MASK 0xffff + + +/* + * Register + * + * The one pulse per second signal is asserted when the local MPCP + * timeincrements past the value programmed in cfTransportTime. + * Software mustupdate this register once per second. + */ +#define LIF_TP_TIME_REG 0x88 + +/* MPCP time at which the pulse per second output will be asserted. */ +#define LIF_TP_TIME_CFTRANSPORTTIME_SHIFT 0 +#define LIF_TP_TIME_CFTRANSPORTTIME_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides the receive MPCP time of the most recently received + * downstreampacket. + * It is updated only when a downstream packet is received. + */ +#define LIF_MPCP_TIME_REG 0x8c + +/* Provides the least significant 32 bits of the receive time. */ +#define LIF_MPCP_TIME_LTMPCPTIME_SHIFT 0 +#define LIF_MPCP_TIME_LTMPCPTIME_MASK 0xffffffff + + +/* + * Register + * + * Max Length setting for the receive sanitizer. + * The sanitizer ensuresthat frames entering latter LIF receive logic are + * truncated to auseable size. + */ +#define LIF_MAXLEN_CTR_REG 0x90 + +/* + * Approximately the maximum number of double words which the frame + * cancontain before being truncated by the LIF Sanitizer circuit. + * Thedefault of 1005 corresponds to a frame length of 2000 bytes. + * Default: + * 1005 +*/ +#define LIF_MAXLEN_CTR_CFRXMAXFRAMELENGTH_SHIFT 0 +#define LIF_MAXLEN_CTR_CFRXMAXFRAMELENGTH_MASK 0x3fff + + +/* + * Register + * + * Specifies an offset, before or after the grant start time, to turn onthe + * laser. + * Units are double-octet words. + */ +#define LIF_LASER_ON_DELTA_REG 0x94 + +/* + * [11: + * 0] Offset (+/-) from Grant Start time to turn laser on[12] 0: + * Positive value: + * turn on laser after the grant start time. + * 1: + * Negative value: + * turn on laser prior to the grant starttime +*/ +#define LIF_LASER_ON_DELTA_CFTXLASERONDELTA_SHIFT 0 +#define LIF_LASER_ON_DELTA_CFTXLASERONDELTA_MASK 0x1fff + + +/* + * Register + * + * Defines when to turn the laser off and the number of IDLE characters + * totransmit at the beginning of a grant of nonFEC frames. + * Units aredouble-octet words (TQ). + */ +#define LIF_LASER_OFF_IDLE_REG 0x98 + +/* + * A period during which the LIF transmits idle characters before + * thetransmission burst of non-FEC frames. +*/ +#define LIF_LASER_OFF_IDLE_CFTXINITIDLE_SHIFT 16 +#define LIF_LASER_OFF_IDLE_CFTXINITIDLE_MASK 0xffff0000 + +/* + * [6: + * 0] Offset (+/-) from Grant End time at which to turn laser off[7]: + * 0: + * Positive value: + * turn off laser after end of grant slot. + * 1: + * Negative value: + * turn off laser before end of grant slot. +*/ +#define LIF_LASER_OFF_IDLE_CFTXLASEROFFDELTA_SHIFT 0 +#define LIF_LASER_OFF_IDLE_CFTXLASEROFFDELTA_MASK 0xff + + +/* + * Register + * + * Defines the number of IDLE characters to transmit at the beginning of + * agrant of FEC frames. + * Units are double-octet words (TQ). + */ +#define LIF_FEC_INIT_IDLE_REG 0x9c + +/* + * A period during which the LIF transmits idle characters before + * thetransmission burst of FEC frames. +*/ +#define LIF_FEC_INIT_IDLE_CFTXFECINITIDLE_SHIFT 0 +#define LIF_FEC_INIT_IDLE_CFTXFECINITIDLE_MASK 0xffff + + +/* + * Register + * + * Allowed hamming distance between received SFEC/TFEC and referencevalue. + */ +#define LIF_FEC_ERR_ALLOW_REG 0xa0 + +/* + * The number of bit error allow for TFEC detection. + * Default : + * 0x5 +*/ +#define LIF_FEC_ERR_ALLOW_CFRXTFECBITERRALLOW_SHIFT 4 +#define LIF_FEC_ERR_ALLOW_CFRXTFECBITERRALLOW_MASK 0xf0 + +/* + * The number of bit error allow for SFEC detection. + * Default : + * 0x5 +*/ +#define LIF_FEC_ERR_ALLOW_CFRXSFECBITERRALLOW_SHIFT 0 +#define LIF_FEC_ERR_ALLOW_CFRXSFECBITERRALLOW_MASK 0xf + + +/* + * Register - read-only + * + * This register is a read-only status of the last downstream key + * selectedon the 32 downstream LLIDs. + * This register allows for software to detecta key switchover or to + * determine the current downstream key. + */ +#define LIF_SEC_KEY_SEL_REG 0xa4 + +/* + * [31: + * 0] Key select status for bidirectional LLIDs; bitwise encodedper LLID + * index +*/ +#define LIF_SEC_KEY_SEL_KEYSEL_SHIFT 0 +#define LIF_SEC_KEY_SEL_KEYSEL_MASK 0xffffffff + + +/* + * Register + * + * Provides per-LLID status of downstream encryption. + * Clear a bit (disable encryption on an LLID) by writing 1 to it. + */ +#define LIF_DN_ENCRYPT_STAT_REG 0xa8 + +/* + * Provides the status of the current encryption mode for each LLID. + * InEPON mode (and with bit enEpnMixEncryption set in the LIF + * ControlRegister) encryption for an LLID can be disabled only by writing + * "1to the appropriate bit in this register. + * 0: + * Encryption disabled1: + * Encryption enabledBitwise encoded per LLID index. +*/ +#define LIF_DN_ENCRYPT_STAT_ENENCRYPT_SHIFT 0 +#define LIF_DN_ENCRYPT_STAT_ENENCRYPT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides per-LLID status of upstream security key. + */ +#define LIF_SEC_UP_KEY_STAT_REG 0xac + +/* + * Provides current active key for upstream LLIDs. + * Bitwise encoded perLLID index. +*/ +#define LIF_SEC_UP_KEY_STAT_KEYUPSEL_SHIFT 0 +#define LIF_SEC_UP_KEY_STAT_KEYUPSEL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides per-LLID status of upstream security. + */ +#define LIF_SEC_UP_ENCRYPT_STAT_REG 0xb0 + +/* + * Provides per-LLID status of the current upstream encryption mode. + * 0: + * Encryption disabled1: + * Encryption enabledBitwise encoded per LLID index. +*/ +#define LIF_SEC_UP_ENCRYPT_STAT_ENUPENCRYPT_SHIFT 0 +#define LIF_SEC_UP_ENCRYPT_STAT_ENUPENCRYPT_MASK 0xffffffff + + +/* + * Register + * + * Provides MPCP correction for EPON encryption. + */ +#define LIF_SEC_UP_MPCP_OFFSET_REG 0xb4 + +/* Provides MPCP offset correction. */ +#define LIF_SEC_UP_MPCP_OFFSET_SECUPMPCPOFFSET_SHIFT 0 +#define LIF_SEC_UP_MPCP_OFFSET_SECUPMPCPOFFSET_MASK 0xffffffff + + +/* + * Register + * + * Provides upstream per LLID FEC enabling. + */ +#define LIF_FEC_PER_LLID_REG 0xb8 + +/* Per-LLID FEC Enable for LLID 0-31. */ +#define LIF_FEC_PER_LLID_CFFECTXFECENLLID_SHIFT 0 +#define LIF_FEC_PER_LLID_CFFECTXFECENLLID_MASK 0xffffffff + + +/* + * Register + * + * Aggregate statistics for the LIF receive channel. + * These registerssaturate at their maximum and clear when read. + * Note: + * These registers are also writable for test/diagnostics purposes. + */ +#define LIF_RX_LINE_CODE_ERR_CNT_REG 0xbc + +/* Counter value. */ +#define LIF_RX_LINE_CODE_ERR_CNT_RXLINECODEERRCNT_SHIFT 0 +#define LIF_RX_LINE_CODE_ERR_CNT_RXLINECODEERRCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_MPCP_FRM_REG 0xc0 + +/* Counter value. */ +#define LIF_RX_AGG_MPCP_FRM_RXAGGMPCPCNT_SHIFT 0 +#define LIF_RX_AGG_MPCP_FRM_RXAGGMPCPCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_GOOD_FRM_REG 0xc4 + +/* Counter value. */ +#define LIF_RX_AGG_GOOD_FRM_RXAGGGOODCNT_SHIFT 0 +#define LIF_RX_AGG_GOOD_FRM_RXAGGGOODCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_GOOD_BYTE_REG 0xc8 + +/* Counter value. */ +#define LIF_RX_AGG_GOOD_BYTE_RXAGGGOODBYTESCNT_SHIFT 0 +#define LIF_RX_AGG_GOOD_BYTE_RXAGGGOODBYTESCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_UNDERSZ_FRM_REG 0xcc + +/* Counter value. */ +#define LIF_RX_AGG_UNDERSZ_FRM_RXAGGUNDERSZCNT_SHIFT 0 +#define LIF_RX_AGG_UNDERSZ_FRM_RXAGGUNDERSZCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_OVERSZ_FRM_REG 0xd0 + +/* Counter value. */ +#define LIF_RX_AGG_OVERSZ_FRM_RXAGGOVERSZCNT_SHIFT 0 +#define LIF_RX_AGG_OVERSZ_FRM_RXAGGOVERSZCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_CRC8_FRM_REG 0xd4 + +/* Counter value. */ +#define LIF_RX_AGG_CRC8_FRM_RXAGGCRC8ERRCNT_SHIFT 0 +#define LIF_RX_AGG_CRC8_FRM_RXAGGCRC8ERRCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_FEC_FRM_REG 0xd8 + +/* Counter value. */ +#define LIF_RX_AGG_FEC_FRM_RXAGGFEC_SHIFT 0 +#define LIF_RX_AGG_FEC_FRM_RXAGGFEC_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_FEC_BYTE_REG 0xdc + +/* Counter value. */ +#define LIF_RX_AGG_FEC_BYTE_RXAGGFECBYTES_SHIFT 0 +#define LIF_RX_AGG_FEC_BYTE_RXAGGFECBYTES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_FEC_EXC_ERR_FRM_REG 0xe0 + +/* Counter value. */ +#define LIF_RX_AGG_FEC_EXC_ERR_FRM_RXAGGFECEXCEEDERRS_SHIFT 0 +#define LIF_RX_AGG_FEC_EXC_ERR_FRM_RXAGGFECEXCEEDERRS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_NONFEC_GOOD_FRM_REG 0xe4 + +/* Counter value. */ +#define LIF_RX_AGG_NONFEC_GOOD_FRM_RXAGGNONFECGOOD_SHIFT 0 +#define LIF_RX_AGG_NONFEC_GOOD_FRM_RXAGGNONFECGOOD_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_NONFEC_GOOD_BYTE_REG 0xe8 + +/* Counter value. */ +#define LIF_RX_AGG_NONFEC_GOOD_BYTE_RXAGGNONFECGOODBYTES_SHIFT 0 +#define LIF_RX_AGG_NONFEC_GOOD_BYTE_RXAGGNONFECGOODBYTES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_BYTES_REG 0xec + +/* Counter value. */ +#define LIF_RX_AGG_ERR_BYTES_RXAGGERRBYTES_SHIFT 0 +#define LIF_RX_AGG_ERR_BYTES_RXAGGERRBYTES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_ZEROES_REG 0xf0 + +/* Counter value. */ +#define LIF_RX_AGG_ERR_ZEROES_RXAGGERRZEROES_SHIFT 0 +#define LIF_RX_AGG_ERR_ZEROES_RXAGGERRZEROES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_NO_ERR_BLKS_REG 0xf4 + +/* Counter value. */ +#define LIF_RX_AGG_NO_ERR_BLKS_RXAGGNOERRBLKS_SHIFT 0 +#define LIF_RX_AGG_NO_ERR_BLKS_RXAGGNOERRBLKS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_COR_BLKS_REG 0xf8 + +/* Counter value. */ +#define LIF_RX_AGG_COR_BLKS_RXAGGCORRBLKS_SHIFT 0 +#define LIF_RX_AGG_COR_BLKS_RXAGGCORRBLKS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_UNCOR_BLKS_REG 0xfc + +/* Counter value. */ +#define LIF_RX_AGG_UNCOR_BLKS_RXAGGUNCORRBLKS_SHIFT 0 +#define LIF_RX_AGG_UNCOR_BLKS_RXAGGUNCORRBLKS_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_ONES_REG 0x100 + +/* Counter value. */ +#define LIF_RX_AGG_ERR_ONES_RXAGGERRONES_SHIFT 0 +#define LIF_RX_AGG_ERR_ONES_RXAGGERRONES_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_RX_AGG_ERR_FRM_REG 0x104 + +/* Counter value. */ +#define LIF_RX_AGG_ERR_FRM_RXAGGERROREDCNT_SHIFT 0 +#define LIF_RX_AGG_ERR_FRM_RXAGGERROREDCNT_MASK 0xffffffff + + +/* + * Register + * + * Aggregate statistics for the LIF transmit channel. + * These registerssaturate at their maximum value and clear when read. + * Note: + * These registers are also writable for test/diagnostics purposes. + */ +#define LIF_TX_PKT_CNT_REG 0x108 + +/* Counter value. */ +#define LIF_TX_PKT_CNT_TXFRAMECNT_SHIFT 0 +#define LIF_TX_PKT_CNT_TXFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_BYTE_CNT_REG 0x10c + +/* Counter value. */ +#define LIF_TX_BYTE_CNT_TXBYTECNT_SHIFT 0 +#define LIF_TX_BYTE_CNT_TXBYTECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_NON_FEC_PKT_CNT_REG 0x110 + +/* Counter value. */ +#define LIF_TX_NON_FEC_PKT_CNT_TXNONFECFRAMECNT_SHIFT 0 +#define LIF_TX_NON_FEC_PKT_CNT_TXNONFECFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_NON_FEC_BYTE_CNT_REG 0x114 + +/* Counter value. */ +#define LIF_TX_NON_FEC_BYTE_CNT_TXNONFECBYTECNT_SHIFT 0 +#define LIF_TX_NON_FEC_BYTE_CNT_TXNONFECBYTECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_FEC_PKT_CNT_REG 0x118 + +/* Counter value. */ +#define LIF_TX_FEC_PKT_CNT_TXFECFRAMECNT_SHIFT 0 +#define LIF_TX_FEC_PKT_CNT_TXFECFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + * Count of FEC bytes transmitted by Line-Coder. + */ +#define LIF_TX_FEC_BYTE_CNT_REG 0x11c + +/* Counter value. */ +#define LIF_TX_FEC_BYTE_CNT_TXFECBYTECNT_SHIFT 0 +#define LIF_TX_FEC_BYTE_CNT_TXFECBYTECNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_FEC_BLK_CNT_REG 0x120 + +/* Counter value. */ +#define LIF_TX_FEC_BLK_CNT_TXFECBLKSCNT_SHIFT 0 +#define LIF_TX_FEC_BLK_CNT_TXFECBLKSCNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_TX_MPCP_PKT_CNT_REG 0x124 + +/* Counter value. */ +#define LIF_TX_MPCP_PKT_CNT_TXMPCPFRAMECNT_SHIFT 0 +#define LIF_TX_MPCP_PKT_CNT_TXMPCPFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + * Count of transmitted frames. + * For debug. + */ +#define LIF_DEBUG_TX_DATA_PKT_CNT_REG 0x128 + +/* Counter value. */ +#define LIF_DEBUG_TX_DATA_PKT_CNT_TXDATAFRAMECNT_SHIFT 0 +#define LIF_DEBUG_TX_DATA_PKT_CNT_TXDATAFRAMECNT_MASK 0xffffffff + + +/* + * Register + * + * Provides sticky status of which LLIDs have received FEC-encoded frames. + * Status is provided bitwise per-LLID; each status bit can be cleared + * bywriting 1 to it. + */ +#define LIF_FEC_LLID_STATUS_REG 0x12c + +/* + * [31: + * 0] stkyFecFecvLlid Per-LLID FEC receive status forbidirectional LLIDs. + * 0: + * No FEC frames detected1: + * FEC frame reception detected +*/ +#define LIF_FEC_LLID_STATUS_STKYFECREVCLLIDBMSK_SHIFT 0 +#define LIF_FEC_LLID_STATUS_STKYFECREVCLLIDBMSK_MASK 0xffffffff + + +/* + * Register + * + * Provides a programmable LLID field that will allow for theinitialization + * vector (in TEK mode only) belonging to non-Raman framesto be preserved + * across Raman frames. + */ +#define LIF_SEC_RX_TEK_IG_IV_LLID_REG 0x130 + +/* + * [15: + * 0] cfIgIvNullLlid Program with the 16 bit LLID of theRaman generated + * random frames. + * [16] cfIgIvNullLlidEn Enable Ignore LLID functionality. +*/ +#define LIF_SEC_RX_TEK_IG_IV_LLID_CFIGIVNULLLLID_SHIFT 0 +#define LIF_SEC_RX_TEK_IG_IV_LLID_CFIGIVNULLLLID_MASK 0x1ffff + + +/* + * Register + * + * Provides control for determining when to assert an interrupt when + * adefined number of programmable errors are observed within a + * definedwindow of time. + * These parameters directly control the behavior ofintRxBerThreshExc. + */ +#define LIF_PON_BER_INTERV_THRESH_REG 0x134 + +/* + * Programmable interval of time. + * Units are in 16 ns increments, for amaximum of 1 ms. +*/ +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERINTERVAL_SHIFT 15 +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERINTERVAL_MASK 0xffff8000 + +/* + * Programmable error threshold. + * Maximum number of errors seen within aprogrammed interval. +*/ +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERTHRESHLD_SHIFT 2 +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERTHRESHLD_MASK 0x7ffc + +/* + * 0: + * Disabled1: + * Count Line Code Errors2: + * Count Corrected Symbols3: + * Count Uncorrectable Blocks (9 symbol errors) +*/ +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERCNTRL_SHIFT 0 +#define LIF_PON_BER_INTERV_THRESH_CFRXLIFBERCNTRL_MASK 0x3 + + +/* + * Register + * + * Provides control over the laser monitor. + */ +#define LIF_LSR_MON_A_CTRL_REG 0x138 + +/* Provides status of laser enable, directly from the I/O pin inputstage. */ +#define LIF_LSR_MON_A_CTRL_IOPBILASERENS1A_MASK 0x20 + +/* + * Laser monitor polarity. + * 0 - active low; 1 - active high. +*/ +#define LIF_LSR_MON_A_CTRL_CFGLSRMONACTHI_MASK 0x10 + +/* + * Main reset for laser monitor. + * 0: + * Reset1: + * Normal operation +*/ +#define LIF_LSR_MON_A_CTRL_PBILASERMONRSTA_N_PRE_MASK 0x1 + + +/* + * Register + * + * Defines a threshold for the laserOnMaxInt interrupt. + * laserOnMaxIntasserts when the laser enable signal stays active for a + * time greaterthan or equal to the laserOnMaxThresh setting. + * laserOnMaxThresh isexpressed in units of TQ. + * However, be aware that the laser monitoroperates from the core epnClk125 + * clock, so there may be some inaccuracyif the transmitter is running + * loop-timed (i. + * e. + * from the recoveredreceive clock). + * In addition, the laser-on time can jitter by 8 ns (1/2TQ) even for + * non-loop timed applications as the laser monitor on-timecounter may not + * be TQ-aligned so an off-by-one error will occur halfthe time. + */ +#define LIF_LSR_MON_A_MAX_THR_REG 0x13c + +/* + * Specifies the threshold for laserOnMaxInt. + * Units are TQ. + * Default: + * 0x80ffff +*/ +#define LIF_LSR_MON_A_MAX_THR_CFGLASERMONMAXA_SHIFT 0 +#define LIF_LSR_MON_A_MAX_THR_CFGLASERMONMAXA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates the laser-on time of the burst that set laserOffInt (i. + * e. + * thefirst burst which ended while laserOffInt was clear). + * Value is latchedupon assertion of laserOffInt. + */ +#define LIF_LSR_MON_A_BST_LEN_REG 0x140 + +/* Indicates length of most recent burst, in TQ. */ +#define LIF_LSR_MON_A_BST_LEN_LASERONTIMEA_SHIFT 0 +#define LIF_LSR_MON_A_BST_LEN_LASERONTIMEA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the number of bursts (laser-off events) since the last + * LaserMonitor reset or since the last read of this register. + * This registerclears when read. + */ +#define LIF_LSR_MON_A_BST_CNT_REG 0x144 + +/* + * This value increments on the negating edge of laser enable. + * Saturates at 0xffffffff; and clears on read. +*/ +#define LIF_LSR_MON_A_BST_CNT_LASERMONBRSTCNTA_SHIFT 0 +#define LIF_LSR_MON_A_BST_CNT_LASERMONBRSTCNTA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides status of state machines in the PON receive side of the LIF. + */ +#define LIF_DEBUG_PON_SM_REG 0x148 + +/* 10B Alignment State Machine States */ +#define LIF_DEBUG_PON_SM_ALIGNCSQQ_SHIFT 8 +#define LIF_DEBUG_PON_SM_ALIGNCSQQ_MASK 0x3f00 + +/* 8B State Machine States */ +#define LIF_DEBUG_PON_SM_RXFECIFCSQQ_SHIFT 0 +#define LIF_DEBUG_PON_SM_RXFECIFCSQQ_MASK 0x1f + + +/* + * Register - read-only + * + * Provides status of state machines in the FEC receive side of the LIF. + */ +#define LIF_DEBUG_FEC_SM_REG 0x14c + +/* FEC Receive Syndrome States */ +#define LIF_DEBUG_FEC_SM_RXSYNCSQQ_SHIFT 16 +#define LIF_DEBUG_FEC_SM_RXSYNCSQQ_MASK 0x1f0000 + +/* FEC Receive Corrector States */ +#define LIF_DEBUG_FEC_SM_RXCORCS_SHIFT 8 +#define LIF_DEBUG_FEC_SM_RXCORCS_MASK 0x300 + +/* FEC Receive Output States */ +#define LIF_DEBUG_FEC_SM_FECRXOUTCS_SHIFT 0 +#define LIF_DEBUG_FEC_SM_FECRXOUTCS_MASK 0x1f + + +/* + * Register + * + * Provides the tolerance for packet number reception in replay + * protectionmode. + * Only applicable in 802. + * 1ae security mode. + */ +#define LIF_AE_PKTNUM_WINDOW_REG 0x150 + +/* + * In replay protection, the packet number is checked against theexpected + * packet number. + * If it is greater than or equal to, packetwill be accepted. + * Otherwise, it will be discarded. + * This registerprovides the tolerance by subtracting the current expected + * packetnumber by this amount. +*/ +#define LIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_SHIFT 0 +#define LIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_MASK 0xffffffff + + +/* + * Register + * + * Provides the threshold to warn of impending packet number rollover + * ontransmit. + */ +#define LIF_AE_PKTNUM_THRESH_REG 0x154 + +/* Defines the maximum packet number rollover. */ +#define LIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_SHIFT 0 +#define LIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides the status of packet number. + */ +#define LIF_AE_PKTNUM_STAT_REG 0x158 + +/* + * Provides the LLID index whose packet number exceeded the maximumpacket + * number threhsold. +*/ +#define LIF_AE_PKTNUM_STAT_SECUPINDXWTPKTNUMMAX_SHIFT 16 +#define LIF_AE_PKTNUM_STAT_SECUPINDXWTPKTNUMMAX_MASK 0x1f0000 + +/* Provides the LLID index that was aborted due to replay protection. */ +#define LIF_AE_PKTNUM_STAT_SECDNINDXWTPKTNUMABORT_SHIFT 0 +#define LIF_AE_PKTNUM_STAT_SECDNINDXWTPKTNUMABORT_MASK 0x1f + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_8_15_REG(x) (0x15c + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 8. + * In downstream P2P, 802. + * 1ae mode, registersLIF_P2P_AE_SCI_LO[0: + * 15]/LIF_P2P_AE_SCI_HI[0: + * 15]provide lookup with packet's explicit SCI to an index. +*/ +#define LIF_LLIDx_8_15_CFGLLID8_SHIFT 0 +#define LIF_LLIDx_8_15_CFGLLID8_MASK 0x1ffff + + +/* + * Registers - is [ 0 => 8 ] + * + * Provides configuration for LLID mapping. + * LIF supports 32 bidirectionalLLIDs. + */ +#define LIF_LLIDx_24_31_REG(x) (0x17c + (x) * 0x4) + +/* + * [15: + * 0]: + * Specifies LLID Index lookup value[16]: + * Enable LLID0: + * Disable LLID1: + * Enable LLIDIn upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup with VLAN'sVID to index 24. +*/ +#define LIF_LLIDx_24_31_CFGLLID24_SHIFT 0 +#define LIF_LLIDx_24_31_CFGLLID24_MASK 0x1ffff + + +/* + * Register + * + * Provides a programmable VLAN type identifier for upstream P2P traffic. + */ +#define LIF_VLAN_TYPE_REG 0x19c + +/* Defines a VLAN type, in addition to 0x8100. */ +#define LIF_VLAN_TYPE_CFGVLANTYPE_SHIFT 0 +#define LIF_VLAN_TYPE_CFGVLANTYPE_MASK 0xffff + + +/* + * Register + * + * Enables SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define LIF_P2P_AE_SCI_EN_REG 0x1a0 + +/* + * Enables SCI lookup, viaLIF_P2P_AE_SCI_LO_[0: + * 15]/LIF_P2P_AE_SCI_HI[0: + * 15] registers. + * Each bitcorresponds to index 0 - 15. +*/ +#define LIF_P2P_AE_SCI_EN_CFGP2PSCIEN_SHIFT 0 +#define LIF_P2P_AE_SCI_EN_CFGP2PSCIEN_MASK 0xffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define LIF_P2P_AE_SCI_LOx_REG(x) (0x1a4 + (x) * 0x8) + +/* + * Defines the lower 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byLIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define LIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_SHIFT 0 +#define LIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define LIF_P2P_AE_SCI_HIx_REG(x) (0x1a8 + (x) * 0x8) + +/* + * Defines the upper 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byLIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define LIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_SHIFT 0 +#define LIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides additon per-LLID status of upstream security key for 802. + * 1aeP2P. + */ +#define LIF_SEC_UP_KEY_STAT_1_REG 0x224 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by LIF_SEC_UP_KEY_STAT. +*/ +#define LIF_SEC_UP_KEY_STAT_1_KEYUPSEL_HI_SHIFT 0 +#define LIF_SEC_UP_KEY_STAT_1_KEYUPSEL_HI_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides addition per-LLID status of downstream security key for802. + * 1ae P2P. + */ +#define LIF_SEC_KEY_SEL_1_REG 0x228 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by LIF_SEC_KEY_SEL. +*/ +#define LIF_SEC_KEY_SEL_1_KEYSEL_HI_SHIFT 0 +#define LIF_SEC_KEY_SEL_1_KEYSEL_HI_MASK 0xffffffff + + +/* + * Register + * + */ +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_REG 0x22c + +/* + * Used to pad plain text frames in 802. + * 1AE encryption mode with afixed number of IPG equivalent to theAE + * overhead. + * Overhead B is equivalent to 16TQ or 32 bytes ofpreceding IPG for + * explicit SCI. +*/ +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_B_IDLE_PAD_SHIFT 6 +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_B_IDLE_PAD_MASK 0xfc0 + +/* + * Used to pad plain text frames in 802. + * 1AE encryption mode with afixed number of IPG equivalent to theAE + * overhead. + * Overhead A is equivalent to 12TQ or 24 bytes ofpreceding IPG for + * implicit SCI. +*/ +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_A_IDLE_PAD_SHIFT 0 +#define LIF_PON_SEC_TX_PLAINTXT_AE_PAD_CONTROL_CF_PLAINTXT_OH_A_IDLE_PAD_MASK 0x3f + + +/* + * Register + * + * Autonegotiation Configuration + */ +#define LIF_P2P_AUTONEG_CONTROL_REG 0x230 + +/* + * Link Timer to allow link partner time to process current statebefore + * advancing to next stateHW Default is about 33. + * 5 msS/W should set to 0x0fff for 2. + * 0ms timer for SGMII Style Formatting +*/ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_LINKTIMER_SHIFT 16 +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_LINKTIMER_MASK 0xffff0000 + +/* + * Mode Select for Auto Neg0 = CL37 Style (33. + * 5ms link timer)1 = SGMII Style (2. + * 0ms link timer)See LP ability and advertisement registers for format +*/ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_MODE_SEL_MASK 0x4 + +/* + * 0 = Restart Disabled / Completed1 = Trigger RestartH/W will clear to 0 + * when restart occurs. +*/ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_RESTART_MASK 0x2 + +/* 0 = Disable Autonegotiation1 = Enable Autonegotiation */ +#define LIF_P2P_AUTONEG_CONTROL_CF_AUTONEG_EN_MASK 0x1 + + +/* + * Register - read-only + * + * Autonegotiation Status + */ +#define LIF_P2P_AUTONEG_STATUS_REG 0x234 + +/* + * 0 = Remote Fault Not Detected from Link Partner1 = Remote Fault Detected + * from Link PartnerWill only update after AN process. + * Will reset upon restart. +*/ +#define LIF_P2P_AUTONEG_STATUS_AN_LP_REMOTE_FAULT_MASK 0x4 + +/* + * 0 = No sync after AN complete1 = Sync after AN completeWill only update + * after AN process. + * Will reset upon restart. +*/ +#define LIF_P2P_AUTONEG_STATUS_AN_SYNC_STATUS_MASK 0x2 + +/* + * 0 = Autoneg Not Complete1 = Autoneg CompletedWill only update after AN + * process. + * Will reset upon restart. +*/ +#define LIF_P2P_AUTONEG_STATUS_AN_COMPLETE_MASK 0x1 + + +/* + * Register + * + * Autonegotiation Ability / Config Register of this device + */ +#define LIF_P2P_AUTONEG_ABILITY_CONFIG_REG_REG 0x238 + +/* + * Defines the Autonegotiation Ability / Config Register of this + * devicecf_autoneg_mode_sel = 0 (CL37)Bits[15]: + * NP, Next Page[14]: + * ACK (H/W overwrite)[13]: + * RF2, Remote Fault[12]: + * RF1, Remote Fault[11: + * 9]: + * Reserved[8]: + * PS2, Asymmetric Pause[7]: + * PS1, Symmetric Pause[6]: + * HD, Half Duplex[5]: + * FD, Full Duplex[4: + * 0]: + * Reservedcf_autoneg_mode_sel = 1 (SGMII)Bits[15]: + * Link State (HW Controlled) 1 = Link Up, 0 = Link Down[14]: + * ACK (H/W overwrite)[13]: + * Reserved[12]: + * Duplex mode: + * 1 = Full Duplex, 0 = Half Duplex[11: + * 10]: + * 11 = Reserved, 10 = 1000Mbps, 01 = 100Mbps, 00 = 10 Mbps[9: + * 1]: + * Reserved[0]: + * Set 1 to per SGMII Spec (S/W must set) +*/ +#define LIF_P2P_AUTONEG_ABILITY_CONFIG_REG_CF_LIF_P2P_AE_AUTONEG_CONFIG_ABILITY_SHIFT 0 +#define LIF_P2P_AUTONEG_ABILITY_CONFIG_REG_CF_LIF_P2P_AE_AUTONEG_CONFIG_ABILITY_MASK 0xffff + + +/* + * Register - read-only + * + * Autonegotiation Ability / Config Register of Link Partner + */ +#define LIF_P2P_AUTONEG_LINK_PARTNER_ABILITY_CONFIG_READ_REG 0x23c + +/* + * Defines the Autonegotiation Ability / Config Register of LINKPARTNEROnly + * updates when AN is completecf_autoneg_mode_sel = 0 (CL37)Bits[15]: + * NP, Next Page[14]: + * ACK (H/W overwrite)[13]: + * RF2, Remote Fault[12]: + * RF1, Remote Fault[11: + * 9]: + * Reserved[8]: + * PS2, Asymmetric Pause[7]: + * PS1, Symmetric Pause[6]: + * HD, Half Duplex[5]: + * FD, Full Duplex[4: + * 0]: + * Reservedcf_autoneg_mode_sel = 1 (SGMII)Bits[15]: + * Link State (HW Controlled) 1 = Link Up, 0 = Link Down[14]: + * ACK (H/W overwrite)[13]: + * Reserved[12]: + * Duplex mode: + * 1 = Full Duplex, 0 = Half Duplex[11: + * 10]: + * 11 = Reserved, 10 = 1000Mbps, 01 = 100Mbps, 00 = 10 Mbps[9: + * 1]: + * Reserved[0]: + * Set 1 to per SGMII Spec (S/W must set) +*/ +#define LIF_P2P_AUTONEG_LINK_PARTNER_ABILITY_CONFIG_READ_CF_LIF_P2P_AE_AUTONEG_LP_ABILITY_READ_SHIFT 0 +#define LIF_P2P_AUTONEG_LINK_PARTNER_ABILITY_CONFIG_READ_CF_LIF_P2P_AE_AUTONEG_LP_ABILITY_READ_MASK 0xffff + + +#endif /* ! EPON_LIF_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_nco_addr.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_nco_addr.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_nco_addr.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_nco_addr.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,309 @@ +#ifndef EPON_NCO_ADDR_H_ +#define EPON_NCO_ADDR_H_ + +/* relative to epon */ +#define NCO_ADDR_OFFSET_0 0x2000 + +/* + * Register + * + * This register is used to provision the Numerically ControlledOscillator + * (NCO) function. + */ +#define NCO_ADDR_NCO_CFG_REG 0x0 + +/* + * Bypass the programmable duty cycle when cfgSrcOut is set to 1 or + * 2(direct Lif/Xif pass through). + * Default : + * 1 +*/ +#define NCO_CFG_CFGBYPASS_MASK 0x80 + +/* + * Selects the 10MHz output source0: + * NCO drives 10MHz output1: + * Lif 10MHz drives 10MHz output2: + * Reserved3: + * Reserved +*/ +#define NCO_CFG_CFGSRCOUT10MHZ_SHIFT 5 +#define NCO_CFG_CFGSRCOUT10MHZ_MASK 0x60 + +/* + * Selects the one PPS output source. + * 0: + * NCO drives one PPS output1: + * lifPpsSig drives one PPS output2: + * xifPpsSig drives one PPS output3: + * Output is zeroThe output source should be set to the Lif or Xif input + * until theNCO converges. + * Only then should the NCO output be selected as theone PPS source. +*/ +#define NCO_CFG_CFGSRCOUT_SHIFT 3 +#define NCO_CFG_CFGSRCOUT_MASK 0x18 + +/* + * Selects the input reference source. + * 0: + * NCO "free runs" at 125 MHz core clock. + * 1: + * NCO tracks lifPpsSig2: + * NCO tracks xifPpsSig3: + * Reserved +*/ +#define NCO_CFG_CFGSRCIN_SHIFT 1 +#define NCO_CFG_CFGSRCIN_MASK 0x6 + +/* + * Set this bit to reset the NCO logic. + * Note: + * This does not reset the NCO configuration registers. + * 0: + * Normal NCO operation1: + * Hold the NCO logic in resetDefault: + * 1 +*/ +#define NCO_CFG_CFGNCOCLR_MASK 0x1 + + +/* + * Register + * + * This register is used to detect the presence and synchronization lockof + * the 1PPS signals. + * These bits are sticky; to clear a bit, write 1 to it. + */ +#define NCO_ADDR_NCO_INT_REG 0x4 + +/* + * The NCO has not detected a 1pps input edge within +/-1us of the + * NCOgenerated edge. +*/ +#define NCO_INT_INTNONCOSYNC_MASK 0x4 + +/* No edges of the Xif 1PPS signal have been detected over 2 NCOperiods. */ +#define NCO_INT_INTNOXIFPPS_MASK 0x2 + +/* No edges of the Lif 1PPS signal have been detected over 2 NCOperiods. */ +#define NCO_INT_INTNOLIFPPS_MASK 0x1 + + +/* + * Register + * + * This register is used to mask NCO interrupts. + */ +#define NCO_ADDR_NCO_MSK_REG 0x8 + +/* Mask for intNoNcoSync */ +#define NCO_MSK_INTNONCOSYNCMASK_MASK 0x4 + +/* Mask for intNoXifPps */ +#define NCO_MSK_INTNOXIFPPSMASK_MASK 0x2 + +/* Mask for intNoLifPps */ +#define NCO_MSK_INTNOLIFPPSMASK_MASK 0x1 + + +/* + * Register + * + * This register is used to provision the NCO's one pulse per second(1PPS) + * period. + */ +#define NCO_ADDR_NCO_1PPS_PERIOD_REG 0xc + +/* + * This register sets the period of the 1PPS signal, in units of 100ns. + * Default: + * 10,000,000 +*/ +#define NCO_1PPS_PERIOD_CFG1PPSPERIOD_SHIFT 0 +#define NCO_1PPS_PERIOD_CFG1PPSPERIOD_MASK 0xffffff + + +/* + * Register + * + * This register is used to provision the NCO's 8 KHz period. + */ +#define NCO_ADDR_NCO_8KHZ_PERIOD_REG 0x10 + +/* + * This register sets the period of the 8 KHz signal, in units of 100ns. + * Default: + * 1,250 +*/ +#define NCO_8KHZ_PERIOD_CFG8KHZPERIOD_SHIFT 0 +#define NCO_8KHZ_PERIOD_CFG8KHZPERIOD_MASK 0xffffff + + +/* + * Register + * + * This register is used to provision the NCO's initial period + * integralvalue. + * The reset default is calculated as (8nS/100nS)*(2^32) => 343,597,394 + */ +#define NCO_ADDR_NCO_CENTER_FREQUENCY_REG 0x14 + +/* + * Initial NCO period integralDefault is 343,597,394. + * The NCO Period Count register may be readto align the input frequency + * with the default to speed up lockingtime. +*/ +#define NCO_CENTER_FREQUENCY_CFGNCODEFAULT_SHIFT 0 +#define NCO_CENTER_FREQUENCY_CFGNCODEFAULT_MASK 0xffffffff + + +/* + * Register + * + * This register is used to provision the NCO's integral gain value. + * The provisioned value must be within the range of 15ppm. + * The value is in 0. + * 001 ppb units + */ +#define NCO_ADDR_NCO_INT_GAIN_REG 0x18 + +/* + * NCO integral gain in number of 0. + * 001 ppb quanta. + * The gain may be increased for faster convergence, and then decreasedfor + * increased accuracy and holdover. + * Default is 0x400. +*/ +#define NCO_INT_GAIN_CFGNCOGAIN_SHIFT 0 +#define NCO_INT_GAIN_CFGNCOGAIN_MASK 0xffff + + +/* + * Register + * + * This register is used to provision the NCO's initial period + * integralvalue. + * The reset default is calculated as (8nS/100nS)*(2^32) => 343,597,394 + */ +#define NCO_ADDR_NCO_PRO_GAIN_REG 0x1c + +/* + * NCO proportional gain in number of 0. + * 2 ppb quanta. + * The gain may be increased for faster convergence, and then decreasedfor + * increased accuracy and holdover. + * Default is 0x400 +*/ +#define NCO_PRO_GAIN_CFGNCOPROPGAIN_SHIFT 0 +#define NCO_PRO_GAIN_CFGNCOPROPGAIN_MASK 0xffff + + +/* + * Register - read-only + * + * The value in this register is the NCO's current period integral. + * The value is in xxx units. + * (This value reflects the relationship between the accuracy of + * thereference clock frequency and the accuracy of the 125 MHz core + * clockfrequency. + * The closer this value is to the ideal value calculated for the + * NCOInitial Period Integral Value in register 0x0c5,the closer the core + * 125 MHz frequency error matches the referenceclock's frequency error. + * )Note: + * Once the system has locked to a valid downstream reference andreached + * steady state,the value in this register can be transferred to the "NCO + * InitialPeriod Integral Value" in register 0x0c5. + * This will ensure that the NCO's "hold-over" frequency will closelymatch + * the reference frequency. + */ +#define NCO_ADDR_NCO_CNT_REG 0x20 + +/* Current NCO period integral value. */ +#define NCO_CNT_NCOCNT_SHIFT 0 +#define NCO_CNT_NCOCNT_MASK 0xffffffff + + +/* + * Register + * + * This register is used to set the NCO's 1PPS duty cycle. + * The provisioned value represents the "high time" of the 1PPS signal + * andis in 100 nS units. + */ +#define NCO_ADDR_NCO_1PPS_HALF_REG 0x24 + +/* + * This register sets the portion of the 1PPS period that the signal + * ishigh. + * This value should be set to the duty cycle high %% times + * thecfg1ppsPeriod (e. + * g. + * 10%% * 10,000,000 = 1,000,000). + * Default is 5,000,000 (50%% duty cycle). +*/ +#define NCO_1PPS_HALF_CFG1PPSHALFPERIOD_SHIFT 0 +#define NCO_1PPS_HALF_CFG1PPSHALFPERIOD_MASK 0xffffff + + +/* + * Register + * + * This register is used to provision the NCO's 8 KHz duty cycle. + * The provisioned value represents the "high time" of the 8 KHz signaland + * is in 100 nS units. + */ +#define NCO_ADDR_NCO_8KHZ_HALF_REG 0x28 + +/* + * This register sets the portion of the 8 KHz period that the signalis + * high. + * Reset default is 625 (50/50 duty cycle). +*/ +#define NCO_8KHZ_HALF_CFG8KHZHALFPERIOD_SHIFT 0 +#define NCO_8KHZ_HALF_CFG8KHZHALFPERIOD_MASK 0xffffff + + +/* + * Register - read-only + * + * This register is used to measure the incoming clock period in terms + * ofthe local oscillator. + */ +#define NCO_ADDR_NCO_PERIOD_CNT_REG 0x2c + +/* + * The number of 8ns clocks in one input period. + * This register willread zero until the first period is complete. + * It will be updated on each subsequent period. + * This value may beused to program the NCO default period for faster lock + * time. + * For a 1PPS, the cfgNcoDefault should equal 343,597,394 *125M/periodCnt. +*/ +#define NCO_PERIOD_CNT_PERIODCNT_SHIFT 0 +#define NCO_PERIOD_CNT_PERIODCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This register is used to measure the incoming clock phase error in 8 + * nsunits. + */ +#define NCO_ADDR_NCO_PHS_ERR_CNT_REG 0x30 + +/* + * The number of 8 ns clocks between the ppsNco rising edge and the LIFPPS + * input signal rising edge. + * This is an up/down counter: + * LIF PPS leading represents a positiveerror, and ppsNco input leading + * represents a negative error. + * The error will saturate at 0x7ff on a positive error and 0x800 on + * anegative error. + * This register is updated for each rising edge sample following thefirst + * negative edge of ppsNco at start up. +*/ +#define NCO_PHS_ERR_CNT_NCOPHSERR_SHIFT 0 +#define NCO_PHS_ERR_CNT_NCOPHSERR_MASK 0xfff + + +#endif /* ! EPON_NCO_ADDR_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xif.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xif.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xif.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xif.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,1190 @@ +#ifndef EPON_XIF_H_ +#define EPON_XIF_H_ + +/* relative to epon */ +#define XIF_OFFSET_0 0x2800 + +/* + * Register + * + * XIF control register. + */ +#define XIF_CTL_REG 0x0 + +/* + * Global downstream receive encryption enable : + * 0 - Normal operation;1 - Enable encryption. +*/ +#define XIF_CTL_RXENCRYPTEN_MASK 0x80000000 + +/* + * Disable DA/SA downstream decryption : + * 0 - Normal operation; 1 -Disable DA/SA decryption. +*/ +#define XIF_CTL_CFGDISRXDASAENCRPT_MASK 0x40000000 + +/* + * Downstream receive security mode : + * 0 - Zero overhead; 2 - 802. + * 1ae; 3- 3Churn. +*/ +#define XIF_CTL_RXENCRYPTMODE_SHIFT 28 +#define XIF_CTL_RXENCRYPTMODE_MASK 0x30000000 + +/* + * Global upstream transmit encryption enable : + * 0 - Normal operation;1 - Enable encryption. +*/ +#define XIF_CTL_TXENCRYPTEN_MASK 0x8000000 + +/* + * Disable DA/SA upstream encryption : + * 0 - Normal operation; 1 -Disable DA/SA encryption. +*/ +#define XIF_CTL_CFGDISTXDASAENCRPT_MASK 0x4000000 + +/* + * Upstream transmit security mode : + * 0 - Zero overhead; 2 - 802. + * 1ae. +*/ +#define XIF_CTL_TXENCRYPTMODE_SHIFT 24 +#define XIF_CTL_TXENCRYPTMODE_MASK 0x3000000 + +/* + * Masks MSB of 16 bit raw LLID for Index translation. + * 0: + * Don't mask, look at full 16 bits. + * 1: + * Mask bit[15], map based on [14: + * 0]. +*/ +#define XIF_CTL_CFGLLIDMODEMSK_MASK 0x400000 + +/* + * Enable bad upstream FCS generation : + * 0 - Normal operation; 1 -Enable bad FCS generation of 0's. +*/ +#define XIF_CTL_CFGXPNBADCRC32_MASK 0x200000 + +/* + * Disable Discovery Info field : + * 0 - Normal operation; 1 - DisableDISCOVERY info. +*/ +#define XIF_CTL_CFGDISDISCINFO_MASK 0x100000 + +/* + * Enable PMC loopback : + * 0 - Normal operation; 1 - Loopback. + * NOTAPPLICABLE in ONU since Tx/Rx clocks are not the same clock. +*/ +#define XIF_CTL_CFGPMCTX2RXLPBK_MASK 0x80000 + +/* + * Enable upstream bad CRC8 transmission : + * 0 - Normal operation; 1 -Enable bad CRC8 generation. +*/ +#define XIF_CTL_CFGPMCTXENCRC8BAD_MASK 0x40000 + +/* + * Enable point-2-point mode for downstream and upstream : + * 0 - PON mode. + * Upstream's preamble will be of type 0x55_55_d5_55. + * Downstream expects the same preamble type else packet will beaborted. + * CRC8 checking is configurable by bit "cfgPmcRxEnCrc8Chk". + * 1 - P2P mode. + * Upstream's preamble will be of type 0x55_55_55_55. + * Downstream expects the same preamble type else packet will beaborted. + * CRC8 checking will be disabled. +*/ +#define XIF_CTL_CFGENP2P_MASK 0x20000 + +/* + * All unmapped LLIDs will be redirected and mapped to Index 00: + * Unmapped LLIDs will appear to be unmapped to EPN;1: + * Unmapped LLIs will appear on Index 0 to EPN. + * ", +*/ +#define XIF_CTL_CFGLLIDPROMISCUOUSMODE_MASK 0x10000 + +/* Enable IDLE packet support to prevent upstream underrun. */ +#define XIF_CTL_CFGENIDLEPKTSUP_MASK 0x8000 + +/* + * Enable PMC-RX checking of CRC8 : + * 0 - Disable; 1 - Enable. +*/ +#define XIF_CTL_CFGPMCRXENCRC8CHK_MASK 0x4000 + +/* Enable 1st IDLE packet in a burst to be converted to IDLEs. */ +#define XIF_CTL_CFGEN1STIDLEPKTCONVERT_MASK 0x2000 + +/* + * Enable upstream FEC : + * 0 - no FEC. + * 1 - FEC. +*/ +#define XIF_CTL_CFGFECEN_MASK 0x1000 + +/* Enable legacy receive timestamp update. */ +#define XIF_CTL_CFGLEGACYRCVTSUPD_MASK 0x800 + +/* + * Enable FCS pass through : + * 0 - Modify packet's FCS; 1 - Pass throughwith no FCS modification. + * Feature is only supported in A0. +*/ +#define XIF_CTL_CFGXPNENCRCPASSTHRU_MASK 0x400 + +/* + * Debug function to disable timestamp modification of MPCP packet. + * 0 -Normal Operation; 1 - Disable timestamp modification. +*/ +#define XIF_CTL_CFGXPNDISTIMESTAMPMOD_MASK 0x200 + +/* + * XIF not ready indication due to RAM init : + * 1 - Not ready. + * 0 - Readyfor operation. + * All RAMs are initialized to 0's. +*/ +#define XIF_CTL_XIFNOTRDY_MASK 0x100 + +/* + * Active low reset for RAM data port. + * RAM init starts upondeassertion. + * Bit xifNotRdy is to be polled for completion +*/ +#define XIF_CTL_XIFDTPORTRSTN_MASK 0x80 + +/* + * Reset control for transmit XPN module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_XPNTXRSTN_MASK 0x40 + +/* + * Reset control for transmit PMC module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_PMCTXRSTN_MASK 0x20 + +/* + * Reset control for transmit security module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_SECTXRSTN_MASK 0x10 + +/* + * Disable OAM encryption. + * 0 - Normal Operation. + * 1 - Disable MPCPencryption. +*/ +#define XIF_CTL_CFGDISTXOAMENCRPT_MASK 0x8 + +/* + * Disable MPCP encryption. + * 0 - Normal Operation. + * 1 - Disable MPCPencryption. +*/ +#define XIF_CTL_CFGDISTXMPCPENCRPT_MASK 0x4 + +/* + * Reset control for receive PMC module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_PMCRXRSTN_MASK 0x2 + +/* + * Reset control for receive security module. + * 0 - Reset. + * 1 - NormalOperation. +*/ +#define XIF_CTL_SECRXRSTN_MASK 0x1 + + +/* + * Register + * + * Interrupts. + */ +#define XIF_INT_STATUS_REG 0x4 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thereceived packet was aborted due to replay protection. +*/ +#define XIF_INT_STATUS_SECRXRPLYPRTCTABRTINT_MASK 0x80 + +/* + * [NON-FATAL] Applicable only in 802. + * 1ae security. + * Indicates thetransmit packet number exceeded the maximum threshold and + * about tooverflow. + * Threshold is programmed in register XIF_AE_PKTNUM_THRESH. +*/ +#define XIF_INT_STATUS_SECTXPKTNUMMAXINT_MASK 0x40 + +/* + * Indicates full MPCP timestamp update due to value greater thanthreshold + * programmed into cfgTsFullUpdThr in register XIF_TS_UPDATE. +*/ +#define XIF_INT_STATUS_TSFULLUPDINT_MASK 0x10 + +/* [FATAL] Indicates request to transmit never got serviced. */ +#define XIF_INT_STATUS_TXHANGINT_MASK 0x8 + +/* + * [FATAL] Indicates scheduled transmit time is negative, relative tothe + * current MPCP time. +*/ +#define XIF_INT_STATUS_NEGTIMEINT_MASK 0x4 + +/* + * [NON-FATAL] Indicates the magnitude of the MPCP timestamp + * updatedexceeded the value programmed into XIF_TS_JITTER_THRESH register. +*/ +#define XIF_INT_STATUS_PMCTSJTTRINT_MASK 0x2 + +/* [FATAL] Indicates SEC-RX output FIFO overflowed. */ +#define XIF_INT_STATUS_SECRXOUTFFOVRFLWINT_MASK 0x1 + + +/* + * Register + * + * Interrupt masks, active low : + * 0 - mask interrupt; 1 - enable interrupt. + */ +#define XIF_INT_MASK_REG 0x8 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKSECRXREPLAYPROTCTABORT_MASK 0x80 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKPKTNUMTHRESHINT_MASK 0x40 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKTSFULLUPDINT_MASK 0x10 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKTXHANGINT_MASK 0x8 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKNEGTIMEINT_MASK 0x4 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKPMCTSJTTRINT_MASK 0x2 + +/* Interrupt mask, active low. */ +#define XIF_INT_MASK_MSKSECRXOUTFFINT_MASK 0x1 + + +/* + * Register + * + * Provides dataPort read/write access to various RAMs. + */ +#define XIF_PORT_COMMAND_REG 0xc + +/* + * Indicates dataPort access is in progress. + * Bit must be clearedbefore the next dataPort access can be issued. +*/ +#define XIF_PORT_COMMAND_DATAPORTBUSY_MASK 0x80000000 + +/* + * Selects the RAM for access : + * 0 - RX key; 2 - TX key; 4 - RX IV; 5 -TX IV. +*/ +#define XIF_PORT_COMMAND_PORTSELECT_SHIFT 24 +#define XIF_PORT_COMMAND_PORTSELECT_MASK 0x3f000000 + +/* + * Indicates write access : + * 0 - read; 1 - write. +*/ +#define XIF_PORT_COMMAND_PORTOPCODE_SHIFT 16 +#define XIF_PORT_COMMAND_PORTOPCODE_MASK 0xff0000 + +/* Specifies the RAM address for access. */ +#define XIF_PORT_COMMAND_PORTADDRESS_SHIFT 0 +#define XIF_PORT_COMMAND_PORTADDRESS_MASK 0xffff + + +/* + * Registers - is [ 0 => 7 ] + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XIF_PORT_DATA_REG(x) (0x14 + (x) * 0x4) + +/* + * TX/RX SEC key RAM, key[31: + * 0]. +*/ +#define XIF_PORT_DATA_PORTDATA_SHIFT 0 +#define XIF_PORT_DATA_PORTDATA_MASK 0xffffffff + + +/* + * Register + * + * This register specifies the 802. + * 1ae MacSec Ethertype to be insertedinto the packet. + */ +#define XIF_MACSEC_REG 0x34 + +/* Defines the MacSec Ethertype. */ +#define XIF_MACSEC_CFGMACSECETHERTYPE_SHIFT 0 +#define XIF_MACSEC_CFGMACSECETHERTYPE_MASK 0xffff + + +/* + * Register + * + * Specifies the transmit offset, relative to the current MPCP. + */ +#define XIF_XPN_XMT_OFFSET_REG 0x38 + +/* + * Specifies the transmit offset, to account for the delay throughSEC-TX + * and PMC-TX. +*/ +#define XIF_XPN_XMT_OFFSET_CFGXPNXMTOFFSET_SHIFT 0 +#define XIF_XPN_XMT_OFFSET_CFGXPNXMTOFFSET_MASK 0xffff + + +/* + * Register + * + * Specifies the offset to add to MPCP's timestamp. + */ +#define XIF_XPN_TIMESTAMP_OFFSET_REG 0x3c + +/* Debug funtion to add the offset to the regenerated MPCP's timestamp. */ +#define XIF_XPN_TIMESTAMP_OFFSET_CFGXPNMPCPTSOFFSET_SHIFT 0 +#define XIF_XPN_TIMESTAMP_OFFSET_CFGXPNMPCPTSOFFSET_MASK 0xffffffff + + +/* + * Register + * + * This register controls Xif's packet generator. + * When enabled the packetgenerator's frames will be inserted in place of + * the normal downstreamdata. + */ +#define XIF_XPN_PKTGEN_CTL_REG 0x40 + +/* Burst since, in TQ unit. */ +#define XIF_XPN_PKTGEN_CTL_CFGONUBURSTSIZE_SHIFT 16 +#define XIF_XPN_PKTGEN_CTL_CFGONUBURSTSIZE_MASK 0xffff0000 + +/* Enable back-2-back grants for overlap testing. */ +#define XIF_XPN_PKTGEN_CTL_CFGENBCK2BCKPKTGEN_MASK 0x20 + +/* Enable all MPCP packet generation. */ +#define XIF_XPN_PKTGEN_CTL_CFGENALLMPCPPKTGEN_MASK 0x10 + +/* Starts packet generator. */ +#define XIF_XPN_PKTGEN_CTL_CFGXPNSTARTPKTGEN_MASK 0x2 + +/* Enables packet generator. */ +#define XIF_XPN_PKTGEN_CTL_CFGXPNENPKTGEN_MASK 0x1 + + +/* + * Register + * + * Specifies the packet generation LLID for index 0 and 1. + */ +#define XIF_XPN_PKTGEN_LLID_REG 0x44 + +/* LLID for index 1. */ +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID1_SHIFT 16 +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID1_MASK 0xffff0000 + +/* LLID for index 0. */ +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID0_SHIFT 0 +#define XIF_XPN_PKTGEN_LLID_CFGXPNPKTGENLLID0_MASK 0xffff + + +/* + * Register + * + * Specifies the number of packet to transmit. + */ +#define XIF_XPN_PKTGEN_PKT_CNT_REG 0x48 + +/* + * Burst mode generation : + * 0 - continuous; 1 - burst mode as defined bycfgXpnPktGenBurstSize. +*/ +#define XIF_XPN_PKTGEN_PKT_CNT_CFGXPNPKTGENBURSTMODE_MASK 0x80000000 + +/* Number of packets to transmit. */ +#define XIF_XPN_PKTGEN_PKT_CNT_CFGXPNPKTGENBURSTSIZE_SHIFT 0 +#define XIF_XPN_PKTGEN_PKT_CNT_CFGXPNPKTGENBURSTSIZE_MASK 0xffffff + + +/* + * Register + * + * Specifies the size of each packet. + */ +#define XIF_XPN_PKTGEN_PKT_SIZE_REG 0x4c + +/* + * Size mode : + * 0 - fixed packet size, defined by cfgXpnPktGenSizeStart;1 - increment + * packet size, from cfgXpnPktGenSizeStart tocfgXpnPktGenSizeEnd. +*/ +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZEINCR_MASK 0x80000000 + +/* Indicates the ending size. */ +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZEEND_SHIFT 16 +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZEEND_MASK 0xfff0000 + +/* Indicates the starting size. */ +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZESTART_SHIFT 0 +#define XIF_XPN_PKTGEN_PKT_SIZE_CFGXPNPKTGENSIZESTART_MASK 0xfff + + +/* + * Register + * + * IPG insertion for packet generator. + */ +#define XIF_XPN_PKTGEN_IPG_REG 0x50 + +/* IPG insertion for back-2-back grants. */ +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENBCK2BCKIPG_SHIFT 16 +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENBCK2BCKIPG_MASK 0xffff0000 + +/* IPG insertion in between packets. */ +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENIPG_SHIFT 0 +#define XIF_XPN_PKTGEN_IPG_CFGXPNPKTGENIPG_MASK 0xffff + + +/* + * Register + * + * Specifies the threshold to generate pmcRxTsJitter interrupt. + */ +#define XIF_TS_JITTER_THRESH_REG 0x54 + +/* + * Defines the value to generate jitter interrupt when timestamp + * updateexceeds this threshold. +*/ +#define XIF_TS_JITTER_THRESH_CFGTSJTTRTHRESH_SHIFT 0 +#define XIF_TS_JITTER_THRESH_CFGTSJTTRTHRESH_MASK 0x7fffffff + + +/* + * Register + * + * Provides timestamp update control. + */ +#define XIF_TS_UPDATE_REG 0x58 + +/* + * Defines the full update threshold. + * Timestamp update is done in 1 TQincrement. + * If update is equal to or greater than threshold, fullupdate will result. +*/ +#define XIF_TS_UPDATE_CFGTSFULLUPDTHR_SHIFT 16 +#define XIF_TS_UPDATE_CFGTSFULLUPDTHR_MASK 0xffff0000 + +/* + * Provides auto timestamp update for debugging. + * This is to test fortimestamp jitter. +*/ +#define XIF_TS_UPDATE_CFGENAUTOTSUPD_MASK 0x8000 + +/* Defines the period between MPCP timestamp update. */ +#define XIF_TS_UPDATE_CFGTSUPDPER_SHIFT 0 +#define XIF_TS_UPDATE_CFGTSUPDPER_MASK 0xff + + +/* + * Register + * + * Specifies the burst overhead for normal grant. + */ +#define XIF_GNT_OVERHEAD_REG 0x5c + +/* Burst overhead of laser_on + sync_time. */ +#define XIF_GNT_OVERHEAD_CFGGNTOH_SHIFT 0 +#define XIF_GNT_OVERHEAD_CFGGNTOH_MASK 0xffff + + +/* + * Register + * + * Specifies the burst overhead for discovery grant. + */ +#define XIF_DISCOVER_OVERHEAD_REG 0x60 + +/* Burst overhead of laser_on + sync_time. */ +#define XIF_DISCOVER_OVERHEAD_CFGDISCOH_SHIFT 0 +#define XIF_DISCOVER_OVERHEAD_CFGDISCOH_MASK 0xffff + + +/* + * Register + * + * Specifies the discovery information field. + */ +#define XIF_DISCOVER_INFO_REG 0x64 + +/* + * Defines the discovery info field : + * 0 - upstream 1G; 1 - upstream10G; 4 - open 1G window; 5 - open 10G + * window. +*/ +#define XIF_DISCOVER_INFO_CFGDISCINFOFLD_SHIFT 0 +#define XIF_DISCOVER_INFO_CFGDISCINFOFLD_MASK 0xffff + + +/* + * Register + * + * Specifies the oversize threshold to increment oversize stat. + */ +#define XIF_XPN_OVERSIZE_THRESH_REG 0x68 + +/* + * Increments oversize stat when packet's size is greater than or equalto + * threshold. +*/ +#define XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_SHIFT 0 +#define XIF_XPN_OVERSIZE_THRESH_CFGXPNOVRSZTHRESH_MASK 0x3fff + + +/* + * Register - read-only + * + * Provides downstream encryption key number stat, per LLID. + */ +#define XIF_SECRX_KEYNUM_REG 0x6c + +/* Key number stat. */ +#define XIF_SECRX_KEYNUM_KEYSTATRX_SHIFT 0 +#define XIF_SECRX_KEYNUM_KEYSTATRX_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides downstream encryption stat, per LLID. + */ +#define XIF_SECRX_ENCRYPT_REG 0x70 + +/* Encryption stat. */ +#define XIF_SECRX_ENCRYPT_ENCRSTATRX_SHIFT 0 +#define XIF_SECRX_ENCRYPT_ENCRSTATRX_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX receive frame count stat. + */ +#define XIF_PMC_FRAME_RX_CNT_REG 0x78 + +/* + * Frame count stat. + * Peg at max value. +*/ +#define XIF_PMC_FRAME_RX_CNT_PMCRXFRAMECNT_SHIFT 0 +#define XIF_PMC_FRAME_RX_CNT_PMCRXFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX byte count stat. + */ +#define XIF_PMC_BYTE_RX_CNT_REG 0x7c + +/* + * Byte count stat. + * Peg at max value. +*/ +#define XIF_PMC_BYTE_RX_CNT_PMCRXBYTECNT_SHIFT 0 +#define XIF_PMC_BYTE_RX_CNT_PMCRXBYTECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX runt count stat. + */ +#define XIF_PMC_RUNT_RX_CNT_REG 0x80 + +/* + * Runt count stat. + * Peg at max value. +*/ +#define XIF_PMC_RUNT_RX_CNT_PMCRXRUNTCNT_SHIFT 0 +#define XIF_PMC_RUNT_RX_CNT_PMCRXRUNTCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX code word error stat. + */ +#define XIF_PMC_CW_ERR_RX_CNT_REG 0x84 + +/* + * Codeword error stat. + * Peg at max value. +*/ +#define XIF_PMC_CW_ERR_RX_CNT_PMCRXCWERRCNT_SHIFT 0 +#define XIF_PMC_CW_ERR_RX_CNT_PMCRXCWERRCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-RX crc8 error stat. + */ +#define XIF_PMC_CRC8_ERR_RX_CNT_REG 0x88 + +/* + * CRC-8 error stat. + * Peg at max value. +*/ +#define XIF_PMC_CRC8_ERR_RX_CNT_PMCRXCRC8ERRCNT_SHIFT 0 +#define XIF_PMC_CRC8_ERR_RX_CNT_PMCRXCRC8ERRCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit data frame count. + */ +#define XIF_XPN_DATA_FRM_CNT_REG 0x8c + +/* + * Data frame count stat, excluding MPCP/OAM. + * Peg at max. +*/ +#define XIF_XPN_DATA_FRM_CNT_XPNDTFRAMECNT_SHIFT 0 +#define XIF_XPN_DATA_FRM_CNT_XPNDTFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit data byte count. + */ +#define XIF_XPN_DATA_BYTE_CNT_REG 0x90 + +/* + * Data byte count stat, excluding MPCP/OAM. + * Peg at max. +*/ +#define XIF_XPN_DATA_BYTE_CNT_XPNDTBYTECNT_SHIFT 0 +#define XIF_XPN_DATA_BYTE_CNT_XPNDTBYTECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit MPCP frame count. + */ +#define XIF_XPN_MPCP_FRM_CNT_REG 0x94 + +/* + * MPCP frame count stat. + * Peg at max. +*/ +#define XIF_XPN_MPCP_FRM_CNT_XPNMPCPFRAMECNT_SHIFT 0 +#define XIF_XPN_MPCP_FRM_CNT_XPNMPCPFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit OAM frame count. + */ +#define XIF_XPN_OAM_FRM_CNT_REG 0x98 + +/* + * MPCP frame count stat. + * Peg at max. +*/ +#define XIF_XPN_OAM_FRM_CNT_XPNOAMFRAMECNT_SHIFT 0 +#define XIF_XPN_OAM_FRM_CNT_XPNOAMFRAMECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit OAM byte count. + */ +#define XIF_XPN_OAM_BYTE_CNT_REG 0x9c + +/* + * OAM byte count stat. + * Peg at max. +*/ +#define XIF_XPN_OAM_BYTE_CNT_XPNOAMBYTECNT_SHIFT 0 +#define XIF_XPN_OAM_BYTE_CNT_XPNOAMBYTECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * XPN transmit oversize frame stat. + */ +#define XIF_XPN_OVERSIZE_FRM_CNT_REG 0xa0 + +/* Oversize frame, as defined by XIF_XPN_OVERSIZE_THRESH register. */ +#define XIF_XPN_OVERSIZE_FRM_CNT_XPNDTOVERSIZECNT_SHIFT 0 +#define XIF_XPN_OVERSIZE_FRM_CNT_XPNDTOVERSIZECNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * SEC-RX abort frame stat. + */ +#define XIF_SEC_ABORT_FRM_CNT_REG 0xa4 + +/* + * Abort frame stat. + * Peg at max. +*/ +#define XIF_SEC_ABORT_FRM_CNT_SECRXABORTFRMCNT_SHIFT 0 +#define XIF_SEC_ABORT_FRM_CNT_SECRXABORTFRMCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * PMC-TX negative transmit time event. + */ +#define XIF_PMC_TX_NEG_EVENT_CNT_REG 0xa8 + +/* + * Negative event count stat. + * Peg at max value. +*/ +#define XIF_PMC_TX_NEG_EVENT_CNT_PMCTXNEGEVENTCNT_SHIFT 0 +#define XIF_PMC_TX_NEG_EVENT_CNT_PMCTXNEGEVENTCNT_MASK 0xff + + +/* + * Register - read-only + * + * Idle packet count. + */ +#define XIF_XPN_IDLE_PKT_CNT_REG 0xac + +/* + * Idle packet count stat. + * Peg at max value. +*/ +#define XIF_XPN_IDLE_PKT_CNT_XPNIDLEFRAMECNT_SHIFT 0 +#define XIF_XPN_IDLE_PKT_CNT_XPNIDLEFRAMECNT_MASK 0xffff + + +/* + * Registers - is [ 0 => 32 ] + * + * Configures LLID index 0 translation. + */ +#define XIF_LLIDx_0_31_REG(x) (0xc0 + (x) * 0x4) + +/* + * Defines the 16-bits LLID for index 0 : + * [15: + * 0] - LLID; [16] - enableLLID. + * In upstream P2P, 802. + * 1ae mode, bit[11: + * 0] provides lookup withVLAN's VID to index 0. + * In downstream P2P, 802. + * 1ae mode, registersXIF_P2P_AE_SCI_LO[0: + * 15]/XIF_P2P_AE_SCI_HI[0: + * 15] provide lookup withpacket's explicit SCI to an index. +*/ +#define XIF_LLIDx_0_31_CFGONULLID0_SHIFT 0 +#define XIF_LLIDx_0_31_CFGONULLID0_MASK 0x1ffff + + +/* + * Register + * + * Specifies the maximum MPCP update. + */ +#define XIF_MAX_MPCP_UPDATE_REG 0x140 + +/* Maximum MPCP update value. */ +#define XIF_MAX_MPCP_UPDATE_CFGMAXPOSMPCPUPD_SHIFT 0 +#define XIF_MAX_MPCP_UPDATE_CFGMAXPOSMPCPUPD_MASK 0xffffffff + + +/* + * Register + * + * Specifies the IPG insertion between packets. + */ +#define XIF_IPG_INSERTION_REG 0x144 + +/* + * Enable short IPG insertion, average of 8 bytes. + * Should only beenabled only in FEC mode. + * Otherwise, average of 12 bytes isinserted. +*/ +#define XIF_IPG_INSERTION_CFGSHORTIPG_MASK 0x200 + +/* Debug function to enable IPG insertion. */ +#define XIF_IPG_INSERTION_CFGINSERTIPG_MASK 0x100 + +/* + * Configure the number of IPG word (2 bytes) to insert. + * Only validwhen cfgInsertIpg is asserted. +*/ +#define XIF_IPG_INSERTION_CFGIPGWORD_SHIFT 0 +#define XIF_IPG_INSERTION_CFGIPGWORD_MASK 0x7f + + +/* + * Register + * + * Specifies the MPCP time to generate a one pulse per second (PPS)signal. + */ +#define XIF_TRANSPORT_TIME_REG 0x148 + +/* PPS is generated when the current MPCP is equal to the programmedvalue. */ +#define XIF_TRANSPORT_TIME_CFTRANSPORTTIME_SHIFT 0 +#define XIF_TRANSPORT_TIME_CFTRANSPORTTIME_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides the current MPCP time. + */ +#define XIF_MPCP_TIME_REG 0x14c + +/* Current MPCP time. */ +#define XIF_MPCP_TIME_CURMPCPTS_SHIFT 0 +#define XIF_MPCP_TIME_CURMPCPTS_MASK 0xffffffff + + +/* + * Register + * + * Provides the overhead for overlapping grant. + */ +#define XIF_OVERLAP_GNT_OH_REG 0x150 + +/* Provides the amount the laser_on time and laser_off time mayoverlap. */ +#define XIF_OVERLAP_GNT_OH_CFGOVRLPOH_SHIFT 0 +#define XIF_OVERLAP_GNT_OH_CFGOVRLPOH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the MAC mode of operation. + */ +#define XIF_MAC_MODE_REG 0x154 + +/* + * Enable point-2-point transmission without grant. + * Must also set bitcfgEnP2P. +*/ +#define XIF_MAC_MODE_CFGENNOGNTXMT_MASK 0x2 + + +/* + * Register + * + * Provides the control for PMC. + */ +#define XIF_PMCTX_CTL_REG 0x158 + +/* + * Define the MPCP update period. + * A value of 0xff disables update. +*/ +#define XIF_PMCTX_CTL_CFGMPCPUPDPERIOD_SHIFT 16 +#define XIF_PMCTX_CTL_CFGMPCPUPDPERIOD_MASK 0xff0000 + +/* + * Disable the requirement of 4 IDLEs preceeding start character toconsider + * packet valid. +*/ +#define XIF_PMCTX_CTL_CFGDIS4IDLEB4STARTCHAR_MASK 0x20 + +/* Enable upstream IDLE discard */ +#define XIF_PMCTX_CTL_CFGENIDLEDSCRD_MASK 0x10 + +/* + * Selects the source of transmit MPCP time : + * 0 - RX; 1 - TX. +*/ +#define XIF_PMCTX_CTL_CFGSELTXPONTIME_MASK 0x8 + +/* Enable continous MPCP update. */ +#define XIF_PMCTX_CTL_CFGMPCPCONTUPD_MASK 0x4 + +/* + * Enable the restriction of positive MPCP update, limitted + * bycfgMaxPosMpcpUpd value set in register XIF_MAX_MPCP_UPDATE. +*/ +#define XIF_PMCTX_CTL_CFGENMAXMPCPUPD_MASK 0x2 + +/* + * Enable the discard of packet with negative scheduled transmit + * time,relative to the current MPCP. +*/ +#define XIF_PMCTX_CTL_CFGENNEGTIMEABORT_MASK 0x1 + + +/* + * Register + * + * Provides control for security. + */ +#define XIF_SEC_CTL_REG 0x15c + +/* + * [A0 BUG] - HWBCM6858-457Enables downstream short length support. + * This feature cannot besupported inA0. + * The workaround would be to disable this feature by clearing thebit. +*/ +#define XIF_SEC_CTL_CFGSECRXENSHORTLEN_MASK 0x40 + +/* Enable fake AES on TX security. */ +#define XIF_SEC_CTL_CFGENSECTXFAKEAES_MASK 0x20 + +/* Enable fake AES on RX security. */ +#define XIF_SEC_CTL_CFGENSECRXFAKEAES_MASK 0x10 + +/* Enables packet number rollover on receive. */ +#define XIF_SEC_CTL_CFGSECRXENPKTNUMRLOVR_MASK 0x8 + +/* Enables packet number rollover on transmit. */ +#define XIF_SEC_CTL_CFGSECTXENPKTNUMRLOVR_MASK 0x2 + +/* Enables replay protection on RX security. */ +#define XIF_SEC_CTL_CFGENAEREPLAYPRCT_MASK 0x1 + + +/* + * Register + * + * Provides the tolerance for packet number reception in replay + * protectionmode. + * Only applicable in 802. + * 1ae security mode. + */ +#define XIF_AE_PKTNUM_WINDOW_REG 0x160 + +/* + * In replay protection, the packet number is checked against theexpected + * packet number. + * If it is greater than or equal to, packetwill be accepted. + * Otherwise, it will be discarded. + * This registerprovides the tolerance by subtracting the current expected + * packetnumber by this amount. +*/ +#define XIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_SHIFT 0 +#define XIF_AE_PKTNUM_WINDOW_CFGAEPKTNUMWND_MASK 0xffffffff + + +/* + * Register + * + * Provides the threshold to warn of impending packet number rollover + * ontransmit. + */ +#define XIF_AE_PKTNUM_THRESH_REG 0x164 + +/* Defines the threshold of impending packet number rollover. */ +#define XIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_SHIFT 0 +#define XIF_AE_PKTNUM_THRESH_CFGPKTNUMMAXTHRESH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides upstream encryption key number stat, per LLID. + */ +#define XIF_SECTX_KEYNUM_REG 0x168 + +/* KeyNumber stat */ +#define XIF_SECTX_KEYNUM_KEYSTATTX_SHIFT 0 +#define XIF_SECTX_KEYNUM_KEYSTATTX_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides upstream encryption stat, per LLID. + */ +#define XIF_SECTX_ENCRYPT_REG 0x16c + +/* Encryption stat. */ +#define XIF_SECTX_ENCRYPT_ENCRSTATTX_SHIFT 0 +#define XIF_SECTX_ENCRYPT_ENCRSTATTX_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides packet number status. + */ +#define XIF_AE_PKTNUM_STAT_REG 0x170 + +/* + * Provides the LLID index whose packet number exceeded the maximumpacket + * number threhsold. +*/ +#define XIF_AE_PKTNUM_STAT_SECTXINDXWTPKTNUMMAX_SHIFT 16 +#define XIF_AE_PKTNUM_STAT_SECTXINDXWTPKTNUMMAX_MASK 0x1f0000 + +/* Provides the LLID index that was aborted due to replay protection. */ +#define XIF_AE_PKTNUM_STAT_SECRXINDXWTPKTNUMABORT_SHIFT 0 +#define XIF_AE_PKTNUM_STAT_SECRXINDXWTPKTNUMABORT_MASK 0x1f + + +/* + * Register - read-only + * + * Debug register showing time between MPCP updates. + */ +#define XIF_MPCP_UPDATE_REG 0x174 + +/* Time between MPCP updates. */ +#define XIF_MPCP_UPDATE_MPCPUPDPERIOD_SHIFT 0 +#define XIF_MPCP_UPDATE_MPCPUPDPERIOD_MASK 0xffffffff + + +/* + * Register + * + * Provides prelaunch time of burst data from ONU, relative to + * thegrant-start-time. + */ +#define XIF_BURST_PRELAUNCH_OFFSET_REG 0x178 + +/* Defines the prelaunch time of burst data, in unit of TQ. */ +#define XIF_BURST_PRELAUNCH_OFFSET_CFGBURSTPRELAUNCHOFFSET_SHIFT 0 +#define XIF_BURST_PRELAUNCH_OFFSET_CFGBURSTPRELAUNCHOFFSET_MASK 0xffffffff + + +/* + * Register + * + * Provides a programmable VLAN type identifier for upstream P2P traffic. + */ +#define XIF_VLAN_TYPE_REG 0x17c + +/* Defines a VLAN type, in addition to 0x8100. */ +#define XIF_VLAN_TYPE_CFGVLANTYPE_SHIFT 0 +#define XIF_VLAN_TYPE_CFGVLANTYPE_MASK 0xffff + + +/* + * Register + * + * Enables SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define XIF_P2P_AE_SCI_EN_REG 0x180 + +/* + * Enables SCI lookup, viaXIF_P2P_AE_SCI_LO[0: + * 15]/XIF_P2P_AE_SCI_HI[0: + * 15] registers. + * Each bitcorresponds to index 0 - 15. +*/ +#define XIF_P2P_AE_SCI_EN_CFGP2PSCIEN_SHIFT 0 +#define XIF_P2P_AE_SCI_EN_CFGP2PSCIEN_MASK 0xffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define XIF_P2P_AE_SCI_LOx_REG(x) (0x184 + (x) * 0x8) + +/* + * Defines the lower 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byXIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define XIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_SHIFT 0 +#define XIF_P2P_AE_SCI_LOx_CFGP2PSCI_LO_0_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 16 ] + * + * Provides SCI lookup for 802. + * 1ae, P2P downstream traffic. + */ +#define XIF_P2P_AE_SCI_HIx_REG(x) (0x188 + (x) * 0x8) + +/* + * Defines the upper 32-bits lookup value of SCI to index 0. + * Ifimplicit SCI mode, index defaults to what was mapped byXIF_LLID_[0: + * 15] with value 0x5555. +*/ +#define XIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_SHIFT 0 +#define XIF_P2P_AE_SCI_HIx_CFGP2PSCI_HI_0_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides additon per-LLID status of upstream security key for 802. + * 1aeP2P. + */ +#define XIF_SECTX_KEYNUM_1_REG 0x204 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by XIF_SECTX_KEYNUM. +*/ +#define XIF_SECTX_KEYNUM_1_KEYSTATTX_HI_SHIFT 0 +#define XIF_SECTX_KEYNUM_1_KEYSTATTX_HI_MASK 0xffffffff + + +/* + * Register - read-only + * + * Provides addition per-LLID status of downstream security key for802. + * 1ae P2P. + */ +#define XIF_SECRX_KEYNUM_1_REG 0x208 + +/* + * In 802. + * 1ae P2P mode, the number of key supported per LLID is 4. + * This register provides the upper bit of the 2-bits key number. + * Thelower bit is provided by XIF_SECRX_KEYNUM. +*/ +#define XIF_SECRX_KEYNUM_1_KEYSTATRX_HI_SHIFT 0 +#define XIF_SECRX_KEYNUM_1_KEYSTATRX_HI_MASK 0xffffffff + + +#endif /* ! EPON_XIF_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcsrx.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcsrx.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcsrx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcsrx.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,1623 @@ +#ifndef EPON_XPCSRX_H_ +#define EPON_XPCSRX_H_ + +/* relative to epon */ +#define XPCSRX_OFFSET_0 0x3000 + +/* + * Register + * + * Provides reset for submodules within XPCS RX and XSBI. + */ +#define XPCSRX_RX_RST_REG 0x0 + +/* Active low reset for 161 MHz domain in XPCS RX. */ +#define RX_RST_CFGXPCSRXCLK161RSTN_MASK 0x1 + + +/* + * Register + * + * Interrupt status for XPcsRx module. + */ +#define XPCSRX_RX_INT_STAT_REG 0x4 + +/* DA jitter detected. */ +#define RX_INT_STAT_INTRXIDLEDAJIT_MASK 0x40000000 + +/* Missing burst detected. */ +#define RX_INT_STAT_INTRXFRMRMISBRST_MASK 0x20000000 + +/* Over size packet detected. */ +#define RX_INT_STAT_INTRXIDLESOPEOPGAPBIG_MASK 0x10000000 + +/* + * No idle insert opportunity in 2000 bytes. + * Idle insert was forced. +*/ +#define RX_INT_STAT_INTRXIDLEFRCINS_MASK 0x8000000 + +/* Min IPG error detected. */ +#define RX_INT_STAT_INTRX64B66BMINIPGERR_MASK 0x4000000 + +/* FEC CW store/foward enqueue input and output count not equal. */ +#define RX_INT_STAT_INTRXFECNQUECNTNEQ_MASK 0x2000000 + +/* + * Idle insert FIFO under run. + * Fatal +*/ +#define RX_INT_STAT_INTRXIDLEFIFOUNDRUN_MASK 0x1000000 + +/* + * Idle insert FIFO over run. + * Fatal +*/ +#define RX_INT_STAT_INTRXIDLEFIFOOVRRUN_MASK 0x800000 + +/* + * FEC high correction alarm. + * High FEC correctoin occured overcfgXPcsRxFecCorIntval +*/ +#define RX_INT_STAT_INTRXFECHIGHCOR_MASK 0x400000 + +/* FEC CW decode fail and FEC decoder is frozen percfgXPcsRxFecStopOnErr */ +#define RX_INT_STAT_INTRXFECDECSTOPONERR_MASK 0x80000 + +/* FEC CW decode passed. */ +#define RX_INT_STAT_INTRXFECDECPASS_MASK 0x40000 + +/* Framer has high BER. */ +#define RX_INT_STAT_INTRXSTATFRMRHIGHBER_MASK 0x20000 + +/* Framer exited by hitting max count on SP. */ +#define RX_INT_STAT_INTRXFRMREXITBYSP_MASK 0x10000 + +/* Framer hit bad SH max count. */ +#define RX_INT_STAT_INTRXFRMRBADSHMAX_MASK 0x8000 + +/* Burst sequence out of order. */ +#define RX_INT_STAT_INTRXDSCRAMBURSTSEQOUT_MASK 0x4000 + +/* Test pattern psudo lock. */ +#define RX_INT_STAT_INTRXTESTPSUDOLOCK_MASK 0x2000 + +/* Test pattern psudo type. */ +#define RX_INT_STAT_INTRXTESTPSUDOTYPE_MASK 0x1000 + +/* Test pattern psudo error. */ +#define RX_INT_STAT_INTRXTESTPSUDOERR_MASK 0x800 + +/* Test pattern PRBS lock. */ +#define RX_INT_STAT_INTRXTESTPRBSLOCK_MASK 0x400 + +/* Test pattern PRBS error. */ +#define RX_INT_STAT_INTRXTESTPRBSERR_MASK 0x200 + +/* Three consecative failed FEC CW decode. */ +#define RX_INT_STAT_INTRXFECPSISTDECFAIL_MASK 0x100 + +/* Framer detected bad SH while in lock. */ +#define RX_INT_STAT_INTRXFRAMERBADSH_MASK 0x80 + +/* Framer went into loss. */ +#define RX_INT_STAT_INTRXFRAMERCWLOSS_MASK 0x40 + +/* Framer went into lock. */ +#define RX_INT_STAT_INTRXFRAMERCWLOCK_MASK 0x20 + +/* FEC CW decode failed. */ +#define RX_INT_STAT_INTRXFECDECFAIL_MASK 0x10 + +/* 66b to 64b decode error has occured. */ +#define RX_INT_STAT_INTRX64B66BDECERR_MASK 0x8 + +/* No frmrCwLk before the no lock timer expired. */ +#define RX_INT_STAT_INTRXFRMRNOLOCKLOS_MASK 0x4 + +/* SP count hit max in ranging but no lock */ +#define RX_INT_STAT_INTRXFRMRROGUE_MASK 0x2 + +/* register access error has occured. */ +#define RX_INT_STAT_INT_REGS_ERR_MASK 0x1 + + +/* + * Register + * + * Interrupt mask for XPcsRx module. + */ +#define XPCSRX_RX_INT_MSK_REG 0x8 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEDAJIT_MASK 0x40000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRMISBRST_MASK 0x20000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLESOPEOPGAPBIG_MASK 0x10000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEFRCINS_MASK 0x8000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRX64B66BMINIPGERR_MASK 0x4000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECNQUECNTNEQ_MASK 0x2000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEFIFOUNDRUN_MASK 0x1000000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXIDLEFIFOOVRRUN_MASK 0x800000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECHIGHCOR_MASK 0x400000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECDECSTOPONERR_MASK 0x80000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECDECPASS_MASK 0x40000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXSTATFRMRHIGHBER_MASK 0x20000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMREXITBYSP_MASK 0x10000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRBADSHMAX_MASK 0x8000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXDSCRAMBURSTSEQOUT_MASK 0x4000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPSUDOLOCK_MASK 0x2000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPSUDOTYPE_MASK 0x1000 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPSUDOERR_MASK 0x800 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPRBSLOCK_MASK 0x400 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXTESTPRBSERR_MASK 0x200 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECPSISTDECFAIL_MASK 0x100 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRAMERBADSH_MASK 0x80 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRAMERCWLOSS_MASK 0x40 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRAMERCWLOCK_MASK 0x20 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFECDECFAIL_MASK 0x10 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRX64B66BDECERR_MASK 0x8 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRNOLOCKLOS_MASK 0x4 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSKRXFRMRROGUE_MASK 0x2 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK_MSK_INT_REGS_ERR_MASK 0x1 + + +/* + * Register + * + * Provides control over framer in XPCS RX. + */ +#define XPCSRX_RX_FRAMER_CTL_REG 0xc + +/* + * 1 = block loading ofr alingMux0Sel when spLkCntMax achievedThis wasthe + * ECO or PIONEER B2 +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRFRCEARLYALIGN_MASK 0x8000 + +/* + * 0 = use framing mode for mux select = alignMux0SelQ forbdEbdAlignedData1 + * = use framing mode for mux select = alignMux0SelQQfor bdEbdAlignedData +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRMODEA_MASK 0x4000 + +/* + * Allows framer to not require any space between EBD and BD faterframing + * once during overlaping grants. + * cfgXPcsRxFrmrOverlapGntEn must be set to use this bit. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMROVERLAPBDEBDZERO_MASK 0x2000 + +/* + * Allows framer to not require spLkCntMax (look for BD withoutpreceeding + * SP) after framing once during overlaping grants. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMROVERLAPGNTEN_MASK 0x1000 + +/* + * Enable for burst mode framing using old alignment + * (xsbiPcsRxFifoVldinstead of xsbiPcsRxFifoVldQ) for alignMuxSelQ and + * alignMuzSelQQ. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRAMEBURSTOLDALIGN_MASK 0x200 + +/* + * 0 - Use falling edge of SP count max and no framer lock to countmissing + * burst. + * 1 - Use unassigned strobe for detection of missingburst. +*/ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRMISBRSTTYPE_MASK 0x100 + +/* In burst mode only look at EBD at the end of codewords. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMREBDVLDEN_MASK 0x80 + +/* FPGA only. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRBDCNTEN_MASK 0x40 + +/* Allows framer to lose lock from 16 bad SH in 62 blocks for burstmode. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRBURSTBADSHEN_MASK 0x20 + +/* Allows framer to lose lock from detection of sync pattern. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRSPULKEN_MASK 0x10 + +/* Enable for burst mode framing. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRAMEBURST_MASK 0x8 + +/* Enable for framer. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMREN_MASK 0x4 + +/* Allows for ignoring of FEC persist decode fail in clause 76 framing. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRMRBLKFECFAIL_MASK 0x2 + +/* Enable for FEC framing. */ +#define RX_FRAMER_CTL_CFGXPCSRXFRAMEFEC_MASK 0x1 + + +/* + * Register + * + * Provides control over FEC in XPCS RX. + */ +#define XPCSRX_RX_FEC_CTL_REG 0x10 + +/* + * Freezes FEC decoder from writing and reading FEC RAM when an erroris + * decoded. + * No recovery after wards, requires that XPCS RX be reset. +*/ +#define RX_FEC_CTL_CFGXPCSRXFECSTOPONERR_MASK 0x400 + +/* + * Tells FEC stats engine to count CW enqueued insted of total FECdecoded + * CW +*/ +#define RX_FEC_CTL_CFGXPCSRXFECCNTNQUECW_MASK 0x200 + +/* Reset the store and foward FIFO. */ +#define RX_FEC_CTL_CFGXPCSRXFECNQUERST_MASK 0x100 + +/* + * 0 - Count every bit correction for the FEC CW. + * 1 - Count only a single correction per 8 bits. + * This only affects the corrected ones and corrected zero stats. + * The total corrected is not effected by this control. +*/ +#define RX_FEC_CTL_CFGXPCSRXFECONEZEROMODE_MASK 0x80 + +/* Stop FEC decoder from making corrections. */ +#define RX_FEC_CTL_CFGXPCSRXFECBLKCORRECT_MASK 0x40 + +/* Replace all FEC CW with IEEE test CW. */ +#define RX_FEC_CTL_CFGXPCSRXFECNQUETESTPAT_MASK 0x20 + +/* + * 0 - Do not blank out SH for failed FEC CW decodes. + * 1 - Blank out SHfor failed FEC CW. + * CW will pass as /E. +*/ +#define RX_FEC_CTL_CFGXPCSRXFECFAILBLKSH0_MASK 0x10 + +/* Enable stripping of FEC parity for FEC decode bypass. */ +#define RX_FEC_CTL_CFGXPCSRXFECSTRIP_MASK 0x8 + +/* Elable FEC decode bypass. */ +#define RX_FEC_CTL_CFGXPCSRXFECBYPAS_MASK 0x4 + +/* Enable idle insert to replace FEC parity lost in FEC decode. */ +#define RX_FEC_CTL_CFGXPCSRXFECIDLEINS_MASK 0x2 + +/* Enable FEC decode. */ +#define RX_FEC_CTL_CFGXPCSRXFECEN_MASK 0x1 + + +/* + * Register + * + * Provides control over descrambler in XPCS RX. + */ +#define XPCSRX_RX_DSCRAM_CTL_REG 0x14 + +/* Enable descrambler bypass. */ +#define RX_DSCRAM_CTL_CFGXPCSRXDSCRAMBYPAS_MASK 0x1 + + +/* + * Register + * + * Provides control over 64b/66b decoder in XPCS RX. + */ +#define XPCSRX_RX_64B66B_CTL_REG 0x18 + +/* Defalut to T7 to T4 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK1_SHIFT 24 +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK1_MASK 0xff000000 + +/* Defalut to T7 to T4 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK0_SHIFT 16 +#define RX_64B66B_CTL_CFGXPCSRX64B66BTMASK0_MASK 0xff0000 + +/* Defalut to S0 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK1_SHIFT 12 +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK1_MASK 0x3000 + +/* Defalut to S0 IPG vioalate det. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK0_SHIFT 8 +#define RX_64B66B_CTL_CFGXPCSRX64B66BSMASK0_MASK 0x300 + +/* Compare S one pipe behind T. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BTDLAY_SHIFT 4 +#define RX_64B66B_CTL_CFGXPCSRX64B66BTDLAY_MASK 0x30 + +/* Enable 64B/66B decoder bypass. */ +#define RX_64B66B_CTL_CFGXPCSRX64B66BDECBYPAS_MASK 0x1 + + +/* + * Register + * + * Provides control over test circuits in XPCS RX. + */ +#define XPCSRX_RX_TEST_CTL_REG 0x1c + +/* Enable PRBS test pattern detector. */ +#define RX_TEST_CTL_CFGXPCSRXTESTPRBSDETEN_MASK 0x2 + +/* Enable psudo test pattern detector. */ +#define RX_TEST_CTL_CFGXPCSRXTESTPSUDODETEN_MASK 0x1 + + +/* + * Register + * + * Sets the delay time to start read of burst from idle insert FIFO. + */ +#define XPCSRX_RX_IDLE_RD_TIMER_DLY_REG 0x20 + +/* + * The delay time to start read of burst (default is 8'd60 ticks). + * Sets the delay to 8'd232 for 10K MTU. +*/ +#define RX_IDLE_RD_TIMER_DLY_CFGXPCSRXIDLERDDELAYTIMERMAX_SHIFT 0 +#define RX_IDLE_RD_TIMER_DLY_CFGXPCSRXIDLERDDELAYTIMERMAX_MASK 0xff + + +/* + * Register + * + * Sets the size for over size frames based on delta between SOP and EOP. + */ +#define XPCSRX_RX_IDLE_GAP_SIZ_MAX_REG 0x24 + +/* + * Max size in blocks without an idle insert opportunity before idleinsert + * is forced. +*/ +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLEOVRSIZMAX_SHIFT 16 +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLEOVRSIZMAX_MASK 0x7ff0000 + +/* Max distance in blocks between SOP and EOP. */ +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLESOPEOPGAP_SHIFT 0 +#define RX_IDLE_GAP_SIZ_MAX_CFGXPCSRXIDLESOPEOPGAP_MASK 0xffff + + +/* + * Register + * + * Sets the delay for indicating lock to FEC decode circuit. + * For FEC modes use the defalut of 8'd280. + * For FEC bypass modes use the defalut of 8'd26. + */ +#define XPCSRX_RX_FRAMER_LK_MAX_REG 0x28 + +/* Max delay for framer to inditcate to FEC circuit lock has beenachieved. */ +#define RX_FRAMER_LK_MAX_CFGXPCSRXFRMRCWLKTIMERMAX_SHIFT 0 +#define RX_FRAMER_LK_MAX_CFGXPCSRXFRMRCWLKTIMERMAX_MASK 0x1ff + + +/* + * Register + * + * Sets the delay for indicating unlock to FEC decode circuit. + * For FEC modes use the defalut of 8'd280. + * For FEC bypass modes use the defalut of 8'd26. + */ +#define XPCSRX_RX_FRAMER_UNLK_MAX_REG 0x2c + +/* Max delay for framer to inditcate to FEC circuit unlock has occured. */ +#define RX_FRAMER_UNLK_MAX_CFGXPCSRXFRMRCWUNLKTIMERMAX_SHIFT 0 +#define RX_FRAMER_UNLK_MAX_CFGXPCSRXFRMRCWUNLKTIMERMAX_MASK 0x1ff + + +/* + * Register + * + * Sets the SH value for the BD for the framer. + */ +#define XPCSRX_RX_FRAMER_BD_SH_REG 0x30 + +/* BD sync header. */ +#define RX_FRAMER_BD_SH_CFGXPCSRXOLTBDSH_SHIFT 0 +#define RX_FRAMER_BD_SH_CFGXPCSRXOLTBDSH_MASK 0x3 + + +/* + * Register + * + * Sets the low 32 bit value for the BD for the framer. + */ +#define XPCSRX_RX_FRAMER_BD_LO_REG 0x34 + +/* Low 32 bit value for the BD. */ +#define RX_FRAMER_BD_LO_CFGXPCSRXOLTBDLO_SHIFT 0 +#define RX_FRAMER_BD_LO_CFGXPCSRXOLTBDLO_MASK 0xffffffff + + +/* + * Register + * + * Sets the high 32 bit value for the BD for the framer. + */ +#define XPCSRX_RX_FRAMER_BD_HI_REG 0x38 + +/* High 32 bit value for the BD. */ +#define RX_FRAMER_BD_HI_CFGXPCSRXOLTBDHI_SHIFT 0 +#define RX_FRAMER_BD_HI_CFGXPCSRXOLTBDHI_MASK 0xffffffff + + +/* + * Register + * + * Sets the SH value for the EBD for the framer. + */ +#define XPCSRX_RX_FRAMER_EBD_SH_REG 0x3c + +/* EBD sync header. */ +#define RX_FRAMER_EBD_SH_CFGXPCSRXOLTEBDSH_SHIFT 0 +#define RX_FRAMER_EBD_SH_CFGXPCSRXOLTEBDSH_MASK 0x3 + + +/* + * Register + * + * Sets the low 32 bit value for the EBD for the framer. + */ +#define XPCSRX_RX_FRAMER_EBD_LO_REG 0x40 + +/* Low 32 bit value for the EBD. */ +#define RX_FRAMER_EBD_LO_CFGXPCSRXOLTEBDLO_SHIFT 0 +#define RX_FRAMER_EBD_LO_CFGXPCSRXOLTEBDLO_MASK 0xffffffff + + +/* + * Register + * + * Sets the high 32 bit value for the EBD for the framer. + */ +#define XPCSRX_RX_FRAMER_EBD_HI_REG 0x44 + +/* High 32 bit value for the EBD. */ +#define RX_FRAMER_EBD_HI_CFGXPCSRXOLTEBDHI_SHIFT 0 +#define RX_FRAMER_EBD_HI_CFGXPCSRXOLTEBDHI_MASK 0xffffffff + + +/* + * Register - read-only + * + * Raw value for interrupt status. + */ +#define XPCSRX_RX_STATUS_REG 0x48 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEDAJIT_MASK 0x40000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRMISBRST_MASK 0x20000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLESOPEOPGAPBIG_MASK 0x10000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEFRCINS_MASK 0x8000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRX64B66BMINIPGERR_MASK 0x4000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECNQUECNTNEQ_MASK 0x2000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEFIFOUNDRUN_MASK 0x1000000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXIDLEFIFOOVRRUN_MASK 0x800000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECHIGHCOR_MASK 0x400000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECDECPASS_MASK 0x40000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXSTATFRMRHIGHBER_MASK 0x20000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMREXITBYSP_MASK 0x10000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRBADSHMAX_MASK 0x8000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXDSCRAMBURSTSEQOUT_MASK 0x4000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPSUDOLOCK_MASK 0x2000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPSUDOTYPE_MASK 0x1000 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPSUDOERR_MASK 0x800 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPRBSLOCK_MASK 0x400 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXTESTPRBSERR_MASK 0x200 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECPSISTDECFAIL_MASK 0x100 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRAMERBADSH_MASK 0x80 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRAMERCWLOSS_MASK 0x40 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRAMERCWLOCK_MASK 0x20 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFECDECFAIL_MASK 0x10 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRX64B66BDECERR_MASK 0x8 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRNOLOCKLOS_MASK 0x4 + +/* Raw status on interrups. */ +#define RX_STATUS_STATRXFRMRROGUE_MASK 0x2 + + +/* + * Register + * + * Sets number of SP detected in order to validate lock or unlock. + */ +#define XPCSRX_RX_FRAMER_LK_ULK_MAX_REG 0x4c + +/* The number of consecutive SP before a BD required to gain lock. */ +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPLKMAX_SHIFT 16 +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPLKMAX_MASK 0x1fff0000 + +/* The number of consecutive SP required to lose lock. */ +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPULKMAX_SHIFT 0 +#define RX_FRAMER_LK_ULK_MAX_CFGXPCSRXFRMRSPULKMAX_MASK 0x1fff + + +/* + * Register + * + * Sets the SH value for the SP for the framer. + */ +#define XPCSRX_RX_FRAMER_SP_SH_REG 0x50 + +/* The SH value for SP. */ +#define RX_FRAMER_SP_SH_CFGXPCSRXOLTSPSH_SHIFT 0 +#define RX_FRAMER_SP_SH_CFGXPCSRXOLTSPSH_MASK 0x3 + + +/* + * Register + * + * Sets the low 32 bit value for the SP for the framer. + */ +#define XPCSRX_RX_FRAMER_SP_LO_REG 0x54 + +/* The lowest 32 bit value for the SP. */ +#define RX_FRAMER_SP_LO_CFGXPCSRXOLTSPLO_SHIFT 0 +#define RX_FRAMER_SP_LO_CFGXPCSRXOLTSPLO_MASK 0xffffffff + + +/* + * Register + * + * Sets the high 32 bit value for the SP for the framer. + */ +#define XPCSRX_RX_FRAMER_SP_HI_REG 0x58 + +/* The highest 32 bit value for the SP. */ +#define RX_FRAMER_SP_HI_CFGXPCSRXOLTSPHI_SHIFT 0 +#define RX_FRAMER_SP_HI_CFGXPCSRXOLTSPHI_MASK 0xffffffff + + +/* + * Register - read-only + * + * The current value of framer state machine. + */ +#define XPCSRX_RX_FRAMER_STATE_REG 0x5c + +/* The state of the framer state machine. */ +#define RX_FRAMER_STATE_XPCSRXFRMRSTATE_SHIFT 0 +#define RX_FRAMER_STATE_XPCSRXFRMRSTATE_MASK 0xf + + +/* + * Register + * + * Sets the hamming distance for SP + */ +#define XPCSRX_RX_FRAMER_BD_EBD_HAM_REG 0x60 + +/* Hamming distance for SP. */ +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRSPHAM_SHIFT 8 +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRSPHAM_MASK 0xf00 + +/* Hamming distance for EBD. */ +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMREBDHAM_SHIFT 4 +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMREBDHAM_MASK 0xf0 + +/* Hamming distance for BD. */ +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRBDHAM_SHIFT 0 +#define RX_FRAMER_BD_EBD_HAM_CFGXPCSRXFRMRBDHAM_MASK 0xf + + +/* + * Register + * + * The count of the possible missing bursts that were detected. + * This isbased on SP detect and SP loss with no BD found. + */ +#define XPCSRX_RX_FRAMER_MISBRST_CNT_REG 0x64 + +/* Count of possibe missed burst. */ +#define RX_FRAMER_MISBRST_CNT_RXFRMRMISBRSTCNT_SHIFT 0 +#define RX_FRAMER_MISBRST_CNT_RXFRMRMISBRSTCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of bit errors found in the last BD when lock was declared. + */ +#define XPCSRX_RX_FRAMER_BD_ERR_REG 0x68 + +/* A count of the errors in BD when it was found. */ +#define RX_FRAMER_BD_ERR_XPCSRXSTATFRMRBDERR_SHIFT 0 +#define RX_FRAMER_BD_ERR_XPCSRXSTATFRMRBDERR_MASK 0xf + + +/* + * Register + * + * Config for LOS based on no lock during a time interval + */ +#define XPCSRX_RX_FRAMER_ROGUE_CTL_REG 0x6c + +/* + * 0 - Rogue detection is disable. + * 1 - Rogue detection is enable. +*/ +#define RX_FRAMER_ROGUE_CTL_CFGXPCSRXFRMRROGUEEN_MASK 0x80000000 + +/* + * If SP count hits treshold and the ranging window endswithout a lockthen + * a rogue detectoin alarm is set. +*/ +#define RX_FRAMER_ROGUE_CTL_CFGXPCSRXFRMRROGUESPTRESH_SHIFT 0 +#define RX_FRAMER_ROGUE_CTL_CFGXPCSRXFRMRROGUESPTRESH_MASK 0xffff + + +/* + * Register + * + * Config for LOS based on no lock during a time interval + */ +#define XPCSRX_RX_FRAMER_NOLOCK_CTL_REG 0x70 + +/* + * 0 - No lock LOS detection is disable. + * 1 - No lock LOS detection isenable. +*/ +#define RX_FRAMER_NOLOCK_CTL_CFGXPCSRXFRMRNOLOCKLOSEN_MASK 0x80000000 + +/* + * Interval for LOS based on no lock found during this time. + * These are6. + * 206 ns steps with default of 1ms. + * The counter is 24 bits with a maxinterval of 104 ms. +*/ +#define RX_FRAMER_NOLOCK_CTL_CFGXPCSRXFRMRNOLOCKLOSINTVAL_SHIFT 0 +#define RX_FRAMER_NOLOCK_CTL_CFGXPCSRXFRMRNOLOCKLOSINTVAL_MASK 0xffffff + + +/* + * Register + * + * Min IPG violation detection count. + */ +#define XPCSRX_RX_64B66B_IPG_DET_CNT_REG 0x74 + +/* + * This is the number of times that a realtionship between the EOP andSOP + * is found. + * The defalut is set to detect min-IPG violations. +*/ +#define RX_64B66B_IPG_DET_CNT_RX64B66BIPGDETCNT_SHIFT 0 +#define RX_64B66B_IPG_DET_CNT_RX64B66BIPGDETCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of FEC CW written to the store/foward enqueue FIFO. + */ +#define XPCSRX_RX_FEC_NQUE_IN_CNT_REG 0x78 + +/* The number of FEC CW written into the store/foward FIFO. */ +#define RX_FEC_NQUE_IN_CNT_RXFECNQUEINCNT_SHIFT 0 +#define RX_FEC_NQUE_IN_CNT_RXFECNQUEINCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of FEC codewrods read from the store/foward + * enqueueFIFO. + */ +#define XPCSRX_RX_FEC_NQUE_OUT_CNT_REG 0x7c + +/* The number of FEC CW read from the store/foward FIFO. */ +#define RX_FEC_NQUE_OUT_CNT_RXFECNQUEOUTCNT_SHIFT 0 +#define RX_FEC_NQUE_OUT_CNT_RXFECNQUEOUTCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of SOP detected in the IDLE insert circuit. + */ +#define XPCSRX_RX_IDLE_START_CNT_REG 0x80 + +/* The number of SOP that the idle insertion logic detected. */ +#define RX_IDLE_START_CNT_RXIDLESTARTCNT_SHIFT 0 +#define RX_IDLE_START_CNT_RXIDLESTARTCNT_MASK 0xffffffff + + +/* + * Register + * + * Counts the number of EOP detected in the IDLE insert circuit. + */ +#define XPCSRX_RX_IDLE_STOP_CNT_REG 0x84 + +/* The number of EOP that the idle insertion logic detected. */ +#define RX_IDLE_STOP_CNT_RXIDLESTOPCNT_SHIFT 0 +#define RX_IDLE_STOP_CNT_RXIDLESTOPCNT_MASK 0xffffffff + + +/* + * Register + * + * Time interval setting (in 6. + * 2 ns quanta) over which the number of FECcorrectines is counted. + * Used for creating high FEC correction alarm. + */ +#define XPCSRX_RX_FEC_COR_INTVAL_REG 0x88 + +/* Number of 161 MHz clock period for the ber interval (default is1ms). */ +#define RX_FEC_COR_INTVAL_CFGXPCSRXFECCORINTVAL_SHIFT 0 +#define RX_FEC_COR_INTVAL_CFGXPCSRXFECCORINTVAL_MASK 0xffffff + + +/* + * Register + * + * The threshold on the number of FEC correctoins made over a timerinterval + * that will cause the FEC high correction alarm. + */ +#define XPCSRX_RX_FEC_COR_TRESH_REG 0x8c + +/* + * Number of FEC corrections made over a given time interval that + * willtrigger the FEC high correction alarm (defalut = 0 = off). +*/ +#define RX_FEC_COR_TRESH_CFGXPCSRXFECCORTRESH_SHIFT 0 +#define RX_FEC_COR_TRESH_CFGXPCSRXFECCORTRESH_MASK 0xffffff + + +/* + * Register + * + * Count the number of uncorrectable FEC CW that have been recieved. + */ +#define XPCSRX_RX_FEC_CW_FAIL_CNT_REG 0x90 + +/* The number of uncorrectable FEC CW that have been recieved. */ +#define RX_FEC_CW_FAIL_CNT_RXFECDECCWFAILCNT_SHIFT 0 +#define RX_FEC_CW_FAIL_CNT_RXFECDECCWFAILCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of total FEC CW that have been recievec. + */ +#define XPCSRX_RX_FEC_CW_TOT_CNT_REG 0x94 + +/* The number of total FEC CW that have been recieved. */ +#define RX_FEC_CW_TOT_CNT_RXFECDECCWTOTCNT_SHIFT 0 +#define RX_FEC_CW_TOT_CNT_RXFECDECCWTOTCNT_MASK 0xffffffff + + +/* + * Register + * + * The number of correctoins made in the FEC CW that have been recieved. + * Lower 32 bits of a 39 bit stat. + * Read this location before reading the upper 7 bis + * atXPCSRX_FEC_CORRECT_CNT_UPERER. + */ +#define XPCSRX_RX_FEC_CORRECT_CNT_LO_REG 0x98 + +/* Lower 32 bits of number of bits that the FEC corrected. */ +#define RX_FEC_CORRECT_CNT_LO_RXFECDECERRCORCNTLOWER_SHIFT 0 +#define RX_FEC_CORRECT_CNT_LO_RXFECDECERRCORCNTLOWER_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of correctoins made in the FEC CW that have been recieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * Read this location after reading the lower 32 bits + * atXPCSRX_FEC_CORRECT_CNT_LOWER. + */ +#define XPCSRX_RX_FEC_CORRECT_CNT_HI_REG 0x9c + +/* Upper 7 bits number of bits that the FEC corrected. */ +#define RX_FEC_CORRECT_CNT_HI_RXFECDECERRCORCNTUPPER_SHIFT 0 +#define RX_FEC_CORRECT_CNT_HI_RXFECDECERRCORCNTUPPER_MASK 0xff + + +/* + * Register + * + * The number of correctoins made in the FEC CW that have been recieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * This is a HW shadow for the upper bits DO NOT USE. + */ +#define XPCSRX_RX_FEC_CORRECT_CNT_SHADOW_REG 0xa0 + +/* Upper 7 of bits that the FEC corrected. */ +#define RX_FEC_CORRECT_CNT_SHADOW_RXFECDECERRCORCNTSHADOW_SHIFT 0 +#define RX_FEC_CORRECT_CNT_SHADOW_RXFECDECERRCORCNTSHADOW_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to ones in the FEC CW that have + * beenrecieved. + * Lower 32 bits of a 39 bit stat. + * Read this location before reading the upper 7 bis + * atXPCSRX_FEC_CORRECT_CNT_UPPER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ONES_COR_CNT_LO_REG 0xa4 + +/* The number of ones that are correctd by the FEC decoder. */ +#define RX_FEC_ONES_COR_CNT_LO_RXFECDECONESCORCNTLOWER_SHIFT 0 +#define RX_FEC_ONES_COR_CNT_LO_RXFECDECONESCORCNTLOWER_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of correctoins made to ones in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * Read this location after reading the lower 32 bits + * atXPCSRX_FEC_CORRECT_CNT_LOWER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ONES_COR_CNT_HI_REG 0xa8 + +/* The number of ones that are correctd by the FEC decoder. */ +#define RX_FEC_ONES_COR_CNT_HI_RXFECDECONESCORCNTUPPER_SHIFT 0 +#define RX_FEC_ONES_COR_CNT_HI_RXFECDECONESCORCNTUPPER_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to ones in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * This is a HW shadow for the upper bits DO NOT USE. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ONES_COR_CNT_SHADOW_REG 0xac + +/* The number of ones that are correctd by the FEC decoder. */ +#define RX_FEC_ONES_COR_CNT_SHADOW_RXFECDECONESCORCNTSHADOW_SHIFT 0 +#define RX_FEC_ONES_COR_CNT_SHADOW_RXFECDECONESCORCNTSHADOW_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to zeros in the FEC CW that have + * beenrecieved. + * Lower 32 bits of a 39 bit stat. + * Read this location before reading the upper 7 bis + * atXPCSRX_FEC_CORRECT_CNT_UPPER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ZEROS_COR_CNT_LO_REG 0xb0 + +/* The number of zeros that are correctd by the FEC decoder. */ +#define RX_FEC_ZEROS_COR_CNT_LO_RXFECDECZEROSCORCNTLOWER_SHIFT 0 +#define RX_FEC_ZEROS_COR_CNT_LO_RXFECDECZEROSCORCNTLOWER_MASK 0xffffffff + + +/* + * Register - read-only + * + * The number of correctoins made to zeros in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * Read this location after reading the lower 32 bits + * atXPCSRX_FEC_CORRECT_CNT_LOWER. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ZEROS_COR_CNT_HI_REG 0xb4 + +/* The number of zeros that are correctd by the FEC decoder. */ +#define RX_FEC_ZEROS_COR_CNT_HI_RXFECDECZEROSCORCNTUPPER_SHIFT 0 +#define RX_FEC_ZEROS_COR_CNT_HI_RXFECDECZEROSCORCNTUPPER_MASK 0xff + + +/* + * Register + * + * The number of correctoins made to zeros in the FEC CW that have + * beenrecieved. + * Upper 7 bits of a 39 bit stat. + * Bit 8 of this register represents overflow of the 39 bit stat. + * This is a HW shadow for the upper bits DO NOT USE. + * NOTE: + * Covers from start of CW through the first 40 bits of the parity. + */ +#define XPCSRX_RX_FEC_ZEROS_COR_CNT_SHADOW_REG 0xb8 + +/* The number of zeros that are correctd by the FEC decoder. */ +#define RX_FEC_ZEROS_COR_CNT_SHADOW_RXFECDECZEROSCORCNTSHADOW_SHIFT 0 +#define RX_FEC_ZEROS_COR_CNT_SHADOW_RXFECDECZEROSCORCNTSHADOW_MASK 0xff + + +/* + * Register - read-only + * + * Captures the write and read pointer for the FEC decoder when a + * faildecode occurs. + */ +#define XPCSRX_RX_FEC_STOP_ON_ERR_READ_POINTER_REG 0xbc + +/* + * Captures the read pointer for the FEC decoder when a fail decodehappens. + * This is for the feature that freezes the FEC decoder when decodesfails. + * Requires cfgXPcsRxFecStopOnErr = 1. +*/ +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRRDPTR_SHIFT 8 +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRRDPTR_MASK 0xff00 + +/* + * Captures the write pointer for the FEC decoder when a fail + * decodehappens. + * This is for the feature that freezes the FEC decoder when decodesfails. + * Requires cfgXPcsRxFecStopOnErr = 1. +*/ +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRWRPTR_SHIFT 0 +#define RX_FEC_STOP_ON_ERR_READ_POINTER_RXFECSTOPONERRWRPTR_MASK 0xff + + +/* + * Register - read-only + * + * Captures the location within the burst where the stop on error occured + */ +#define XPCSRX_RX_FEC_STOP_ON_ERR_BURST_LOCATION_REG 0xc0 + +/* + * Captures the location witing hte burst where the stop on erroroccured. + * This is in ticks of 161 clocks. + * Requires cfgXPcsRxFecStopOnErr = 1. +*/ +#define RX_FEC_STOP_ON_ERR_BURST_LOCATION_RXFECSTOPONERRBRSTLOC_SHIFT 0 +#define RX_FEC_STOP_ON_ERR_BURST_LOCATION_RXFECSTOPONERRBRSTLOC_MASK 0xffffff + + +/* + * Register + * + * Count the number of 64b/66b decode errors. + */ +#define XPCSRX_RX_64B66B_FAIL_CNT_REG 0xc4 + +/* The number of 64b/66b decoed errors. */ +#define RX_64B66B_FAIL_CNT_RX64B66BDECERRCNT_SHIFT 0 +#define RX_64B66B_FAIL_CNT_RX64B66BDECERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of bad SH during CW lock. + */ +#define XPCSRX_RX_FRMR_BAD_SH_CNT_REG 0xc8 + +/* The number bad SH while in CW lock. */ +#define RX_FRMR_BAD_SH_CNT_RXFRMRBADSHCNT_SHIFT 0 +#define RX_FRMR_BAD_SH_CNT_RXFRMRBADSHCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of errors in test pattern 2 while in patter lock. + */ +#define XPCSRX_RX_PSUDO_CNT_REG 0xcc + +/* The number of errors in test pattern 2 while in pattern lock. */ +#define RX_PSUDO_CNT_RXTESTPSUDOERRCNT_SHIFT 0 +#define RX_PSUDO_CNT_RXTESTPSUDOERRCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of errors in test pattern PRBS-31 while in patternlock. + */ +#define XPCSRX_RX_PRBS_CNT_REG 0xd0 + +/* The number of errors in test pattern PRBS-31 while in patern lock. */ +#define RX_PRBS_CNT_RXTESTPRBSERRCNT_SHIFT 0 +#define RX_PRBS_CNT_RXTESTPRBSERRCNT_MASK 0xffffffff + + +/* + * Register + * + * The interval over which SH BER is mearsured in the framer. + * Used togenerate xPcsRxStatFrmrHighBer alarm. + */ +#define XPCSRX_RX_BER_INTVAL_REG 0xd4 + +/* + * Number of 161 MHz clock period for the interval over which SH BER + * iscounter in the framer(default is 256 us). +*/ +#define RX_BER_INTVAL_CFGXPCSRXFRMRBERINTVAL_SHIFT 0 +#define RX_BER_INTVAL_CFGXPCSRXFRMRBERINTVAL_MASK 0xffffff + + +/* + * Register + * + * The threshold on the number of bit errors made over a timer intervalthat + * will cause the high BER alarm. + */ +#define XPCSRX_RX_BER_TRESH_REG 0xd8 + +/* + * Number of SH error permitted over the BER interval. + * (defalut = 0 =off). +*/ +#define RX_BER_TRESH_CFGXPCSRXFRMRBERTRESH_SHIFT 0 +#define RX_BER_TRESH_CFGXPCSRXFRMRBERTRESH_MASK 0x1ff + + +/* + * Register + * + * Count the number of SOP detected in the 64b/66b decoder. + */ +#define XPCSRX_RX_64B66B_START_CNT_REG 0xdc + +/* The number of SOP that the 64b/66b decoder found. */ +#define RX_64B66B_START_CNT_RX64B66BDECSTARTCNT_SHIFT 0 +#define RX_64B66B_START_CNT_RX64B66BDECSTARTCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of good packets detected in the idle insertion logic. + * Based on finding SOP followed by EOP. + */ +#define XPCSRX_RX_IDLE_GOOD_PKT_CNT_REG 0xe0 + +/* The number of good packets found by the idle insertion logic. */ +#define RX_IDLE_GOOD_PKT_CNT_RXIDLEGOODPKTCNT_SHIFT 0 +#define RX_IDLE_GOOD_PKT_CNT_RXIDLEGOODPKTCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of bad packets detected in the idle insertion logic. + */ +#define XPCSRX_RX_IDLE_ERR_PKT_CNT_REG 0xe4 + +/* The number of errored packets found by the idle insertion logic. */ +#define RX_IDLE_ERR_PKT_CNT_RXIDLEERRPKTCNT_SHIFT 0 +#define RX_IDLE_ERR_PKT_CNT_RXIDLEERRPKTCNT_MASK 0xffffffff + + +/* + * Register + * + * Count the number of EOP detected in the 64b/66b decoder. + */ +#define XPCSRX_RX_64B66B_STOP_CNT_REG 0xe8 + +/* The number of EOP that the 64b/66b decoder found. */ +#define RX_64B66B_STOP_CNT_RX64B66BDECSTOPCNT_SHIFT 0 +#define RX_64B66B_STOP_CNT_RX64B66BDECSTOPCNT_MASK 0xffffffff + + +/* + * Register + * + * Test mode used in FPGA only. + * Count the number of burst recieved out oforder. + */ +#define XPCSRX_RX_BURST_OUT_ODR_CNT_REG 0xec + +/* The number of times recieved burst sequence number was out of order. */ +#define RX_BURST_OUT_ODR_CNT_RXBURSTSEQOUTOFORDERCNT_SHIFT 0 +#define RX_BURST_OUT_ODR_CNT_RXBURSTSEQOUTOFORDERCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Gives delay values for two different DA through the IDLE insertprocess. + */ +#define XPCSRX_RX_IDLE_DA_JIT_DLY_REG 0xf0 + +/* Previous delay for DA through the idle insert process. */ +#define RX_IDLE_DA_JIT_DLY_RXIDLELASTDACNT_SHIFT 16 +#define RX_IDLE_DA_JIT_DLY_RXIDLELASTDACNT_MASK 0x1ff0000 + +/* Current delay for DA through the idle insert process. */ +#define RX_IDLE_DA_JIT_DLY_RXIDLEDACNT_SHIFT 0 +#define RX_IDLE_DA_JIT_DLY_RXIDLEDACNT_MASK 0x1ff + + +/* + * Register + * + * Provides data port access to all XPCS RX RAMS. + * The data port functions as a means to access RAMs by way ofindirection. + * The address, commands and busy status are located in this register. + * XPCSRX_DPORT_CTLThe data to be read or written are accesses at: + * XPCSRX_DPORT_DATA0XPCSRX_DPORT_DATA1XPCSRX_DPORT_DATA2XPCSRX_DPORT_DATA3XPCSRX_DPORT_DATA4The + * control to allow this data port to access data path RAMs arelocated: + * XPCSRX_DPORT_ACCThe control to disable clear on read for XPCS RX Stats + * Ram is located: + * XPCSRX_DPORT_FEC_STATS_CTLThe capture FIFO RAM, FEC decode RAM, FEC + * enqueue RAM and idle insertRAMare data path rams. + * In order to access them a select must be set. + * Thisdisables the data path and allows the data port to have access. + * TheXPCS RXwill not function properly under these conditions. + * Accesses to theseRAMsby this data port is for test only. + * The FEC decode stats RAM also has a control bit associated with it. + * Thiscontrol bit is not associated with permitting access to this RAM. + * Accessesto this RAM by this data port is intended for both the normal + * mode ofoperation and testing. + * This bit is to disable the clear on readfunctionthat occurs with normal + * read accesses to this RAM by this data port. + * CONTRLS: + * To access the capture FIFO RAM, FEC decode RAM, FEC enqueue RAM or + * idleinsert RAM, set the data port select bit in XPCSRX_DPORT_ACC. + * To access the FEC decode stats RAM without clear on read set, set + * thedisable bit in XPCSRX_DPORT_FEC_STATS_CTL. + * Do not set this innormal operation. + * It is intended that statistics are clear on read. + * For writes, set the write values in the data registers. + * Set the address, RAM select and control fields in this register. + * Poll the busy bit in this register. + * Once the busy bit is not set the data port has completed the command. + * For reads, read the data register after the busy bit clears. + * Statistics and Data Fields descriptions for the RAMS: + * RAM | Type | Size | ecc field | + * datafield============================================================================Capture + * FIFO | PD | 256x80 | [79: + * 72] |[71: + * 0]FEC enqueue | RF | 32x80 | [79: + * 72] |[71: + * 0]FEC decode | PD | 256x80 | [79: + * 72] |[71: + * 0]FEC stats | SP | 128x151 | [150: + * 142] |[141: + * 0]Idle insert | PD | 256x82 | [81: + * 73] |[73: + * 0]Data fields descripton: + * Capture FIFO[71: + * 64] XPCS RX control[63: + * 0] XPCS RX dataFEC enqueue[71: + * 0] aligned 66b data geared up to 72bFEC decode[71: + * 0] aligned 66b data geared up to 72bFEC stats RAM[141: + * 103] ones corected statistics[102: + * 64] zeros corrected statistics[63: + * 32] code words decode fails statistics[31: + * 0] code words total statisticsIdle insert[73: + * 72] number of invalid times between valid[71: + * 68] control indication[69: + * 36] four bytes of 8b data[35: + * 32] control indication[31: + * 0] four bytes of 8b data + */ +#define XPCSRX_RX_DPORT_CTL_REG 0xf4 + +/* Data port busy. */ +#define RX_DPORT_CTL_XPCSRXDPBUSY_MASK 0x80000000 + +/* Data port error (always 0 for XPCS RX). */ +#define RX_DPORT_CTL_XPCSRXDPERR_MASK 0x40000000 + +/* Data port command (0 = read and 1 = write). */ +#define RX_DPORT_CTL_CFGXPCSRXDPCTL_SHIFT 20 +#define RX_DPORT_CTL_CFGXPCSRXDPCTL_MASK 0xff00000 + +/* + * Data port RAM select : + * 0 = capture FIFO RAM1 = FEC decode RAM2 = FEC stats RAM3 = FEC enqueue + * RAM4 = idle insert RAM +*/ +#define RX_DPORT_CTL_CFGXPCSRXDPRAMSEL_SHIFT 16 +#define RX_DPORT_CTL_CFGXPCSRXDPRAMSEL_MASK 0xf0000 + +/* + * Data port address. + * NOTE: + * all 16 bits are available but the largest ram in XPCS + * RXXPcsRxCapFifoRam. + * vbis x256. +*/ +#define RX_DPORT_CTL_CFGXPCSRXDPADDR_SHIFT 0 +#define RX_DPORT_CTL_CFGXPCSRXDPADDR_MASK 0xffff + + +/* + * Register + * + * Rreadback register and write register for data port accesses. + */ +#define XPCSRX_RX_DPORT_DATA0_REG 0xf8 + +/* Data port data bits 31 to 0. */ +#define RX_DPORT_DATA0_XPCSRXDPDATA0_SHIFT 0 +#define RX_DPORT_DATA0_XPCSRXDPDATA0_MASK 0xffffffff + + +/* + * Register + * + * Rreadback register and write register for data port accesses. + */ +#define XPCSRX_RX_DPORT_DATA1_REG 0xfc + +/* Data port data bits 63 to 32. */ +#define RX_DPORT_DATA1_XPCSRXDPDATA1_SHIFT 0 +#define RX_DPORT_DATA1_XPCSRXDPDATA1_MASK 0xffffffff + + +/* + * Register + * + * Rreadback register and write register for data port accesses. + */ +#define XPCSRX_RX_DPORT_DATA2_REG 0x100 + +/* Data port data bits 95 to 64. */ +#define RX_DPORT_DATA2_XPCSRXDPDATA2_SHIFT 0 +#define RX_DPORT_DATA2_XPCSRXDPDATA2_MASK 0xffffffff + + +/* + * Register + * + * Provides data port access to all XPCS RX RAMS. + */ +#define XPCSRX_RX_DPORT_ACC_REG 0x104 + +/* Disable data path and selects data port for RAM access. */ +#define RX_DPORT_ACC_CFGXPCSRXIDLERAMDPSEL_MASK 0x8 + +/* Disable data path and selects data port for RAM access. */ +#define RX_DPORT_ACC_CFGXPCSRXFECDECRAMDPSEL_MASK 0x4 + +/* Disable data path and selects data port for RAM access. */ +#define RX_DPORT_ACC_CFGXPCSRXFECNQUERAMDPSEL_MASK 0x2 + + +/* + * Register + * + * Interrupt status for XPcsRx RAMs ECC. + */ +#define XPCSRX_RX_RAM_ECC_INT_STAT_REG 0x108 + +/* Idle insert FIFO RAM init done interrupt. */ +#define RX_RAM_ECC_INT_STAT_INTRXIDLERAMINITDONE_MASK 0x10 + +/* FEC enqueue FIFO RAM init done interrupt. */ +#define RX_RAM_ECC_INT_STAT_INTRXFECNQUERAMINITDONE_MASK 0x8 + +/* FEC decode FIFO RAM init done interrupt. */ +#define RX_RAM_ECC_INT_STAT_INTRXFECDECRAMINITDONE_MASK 0x2 + + +/* + * Register + * + * Interrupt mask for XPcsRx RAMs ECC. + */ +#define XPCSRX_RX_RAM_ECC_INT_MSK_REG 0x10c + +/* Idle insert FIFO RAM init done interrupt mask. */ +#define RX_RAM_ECC_INT_MSK_MSKRXIDLERAMINITDONE_MASK 0x10 + +/* FEC enqueue FIFO RAM init done interrupt mask. */ +#define RX_RAM_ECC_INT_MSK_MSKRXFECNQUERAMINITDONE_MASK 0x8 + +/* FEC decode FIFO RAM init done interrupt mask. */ +#define RX_RAM_ECC_INT_MSK_MSKRXFECDECRAMINITDONE_MASK 0x2 + + +/* + * Register + * + * DFT test mode for PD RAMs + */ +#define XPCSRX_RX_DFT_TESTMODE_REG 0x110 + +/* DFT test mode for PD RAMs */ +#define RX_DFT_TESTMODE_TM_PD_SHIFT 0 +#define RX_DFT_TESTMODE_TM_PD_MASK 0x3ff + + +/* + * Register + * + * Control register to selectively power one or more rowblocks of thememory + * to acieve improved power reduction. + * There is one bit perrowblock for the specific RAM. + * All array contents are lost for therowblocks that are powered down. + * the rowblocks in operational modewill be available for read/write and + * data retention. + * 1 = power down0 = operationalNOTE: + * When powering up, do NOT power up more than one array in one RAMat a + * time. + * It may damage the RAM. + */ +#define XPCSRX_RX_RAM_POWER_PDA_CTL0_REG 0x114 + +/* Array power down control for FEC decode RAM */ +#define RX_RAM_POWER_PDA_CTL0_CFGXPCSRXIDLERAMPDA_MASK 0x8 + +/* Array power down control for FEC decode RAM */ +#define RX_RAM_POWER_PDA_CTL0_CFGXPCSRXFECDECRAMPDA_MASK 0x2 + + +/* + * Register + * + * More Interrupt status for XPcsRx module. + */ +#define XPCSRX_RX_INT_STAT1_REG 0x118 + +/* trailing start at the end of burst */ +#define RX_INT_STAT1_INTRX64B66BTRAILSTART_MASK 0x8 + +/* two stops in a row detected */ +#define RX_INT_STAT1_INTRX64B66BTWOSTOP_MASK 0x4 + +/* two starts in a row detected */ +#define RX_INT_STAT1_INTRX64B66BTWOSTART_MASK 0x2 + +/* leading stop at the start of burst */ +#define RX_INT_STAT1_INTRX64B66BLEADSTOP_MASK 0x1 + + +/* + * Register + * + * More Interrupt mask for XPcsRx module. + */ +#define XPCSRX_RX_INT_MSK1_REG 0x11c + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BTRAILSTART_MASK 0x8 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BTWOSTOP_MASK 0x4 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BTWOSTART_MASK 0x2 + +/* + * 0 - Interrupt is masked. + * 1 - Interrupt is unmasked. +*/ +#define RX_INT_MSK1_MSKRX64B66BLEADSTOP_MASK 0x1 + + +/* + * Register + * + * Spare RW bits + */ +#define XPCSRX_RX_SPARE_CTL_REG 0x120 + +/* Spare RW bits */ +#define RX_SPARE_CTL_CFGXPCSRXSPARE_SHIFT 0 +#define RX_SPARE_CTL_CFGXPCSRXSPARE_MASK 0xffffffff + + +#endif /* ! EPON_XPCSRX_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcstx.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcstx.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/epon_xpcstx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/epon_xpcstx.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,454 @@ +#ifndef EPON_XPCSTX_H_ +#define EPON_XPCSTX_H_ + +/* relative to epon */ +#define XPCSTX_OFFSET_0 0x3800 + +/* + * Register + * + * XPCS-TX control register. + */ +#define XPCSTX_TX_CONTROL_REG 0x0 + +/* Enable remote fault detection. */ +#define TX_CONTROL_CFGENRMTFAULTDET125_MASK 0x8000 + +/* Enable the laser enable tri-state output. */ +#define TX_CONTROL_CFGLSRTRISTATEEN125_MASK 0x4000 + +/* + * Debug function has been deprecated. + * It is now utilized to enableIDLE packet support : + * 0 - enable; 1 - disable. +*/ +#define TX_CONTROL_CFGENSEQNUM125_MASK 0x2000 + +/* + * Enable the scrambler to run continously. + * 0 - Only during burst; 1 -Continuosly. +*/ +#define TX_CONTROL_CFGENSCRMBCONT125_MASK 0x800 + +/* + * Laser on polarity : + * 0 - laser on active low; 1 - laser on activehigh. +*/ +#define TX_CONTROL_CFGLSRENACTHI125_MASK 0x400 + +/* Enable laser on always. */ +#define TX_CONTROL_CFGENLSRALWAYS125_MASK 0x200 + +/* Enable laser until the end-of-grant, non-strict IEEE mode. */ +#define TX_CONTROL_CFGENLSRTILENDSLOT125_MASK 0x100 + +/* Flip Gearbox's byte output to SERDES. */ +#define TX_CONTROL_CFGTXOUTBYTEFLIP125_MASK 0x80 + +/* + * Enable transmit Gearbox's output. + * 0 - disable transmit; 1 - enabletransmit. +*/ +#define TX_CONTROL_CFGENTXOUT125_MASK 0x40 + +/* + * Enable transmit scrambler. + * 0 - disable scrambler; 1 - enablescrambler. +*/ +#define TX_CONTROL_CFGENTXSCRB125_MASK 0x20 + +/* + * Enables upstream FEC : + * 0 - nonFEC; 1 - FEC. +*/ +#define TX_CONTROL_CFGENTXFEC125_MASK 0x10 + +/* Indicates XPCS-TX not ready for operation. */ +#define TX_CONTROL_PCSTXNOTRDY_MASK 0x8 + +/* + * Active low reset for RAM data port. + * RAM init starts upondeassertion. + * Bit pcstxNotRdy is to be polled for completion. +*/ +#define TX_CONTROL_PCSTXDTPORTRSTN_MASK 0x2 + +/* + * Reset control for XPCS-TX module. + * 0 - Reset. + * 1 - Normal Operation. +*/ +#define TX_CONTROL_PCSTXRSTN_MASK 0x1 + + +/* + * Register + * + */ +#define XPCSTX_TX_INT_STAT_REG 0x4 + +/* + * Indicates laser enable on time exceeed the maximum threshold, asdefined + * by register XPCS_TX_LASER_MONITOR_MAX_THRESH. +*/ +#define TX_INT_STAT_LASERONMAX_MASK 0x80 + +/* Indicates laser enable deassertion. */ +#define TX_INT_STAT_LASEROFF_MASK 0x40 + +/* [FATAL] Indicates scheduled time lagged current MPCP time. */ +#define TX_INT_STAT_GRANTLAGERR_MASK 0x20 + +/* [NON-FATAL] Indicates back-2-back grants. */ +#define TX_INT_STAT_BACK2BACKGNT_MASK 0x8 + +/* [FATAL] FEC transmit FIFO underrun. */ +#define TX_INT_STAT_FECUNDERRUN_MASK 0x4 + +/* [FATAL] Gearbox underrun. */ +#define TX_INT_STAT_GEARBOXUNDERRUN_MASK 0x2 + +/* [NON-FATAL] Indicates grant slot is too short for transfer. */ +#define TX_INT_STAT_GNTTOOSHORT_MASK 0x1 + + +/* + * Register + * + * Interrupt masks, active low : + * 0 - mask interrupt; 1 - enable interrupt. + */ +#define XPCSTX_TX_INT_MASK_REG 0x8 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_LASERONMAXMASK_MASK 0x80 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_LASEROFFMASK_MASK 0x40 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_GRANTLAGERRMSK_MASK 0x20 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_BACK2BCKGNTMSK_MASK 0x8 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_FECUNDERRUNMSK_MASK 0x4 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_GEARBOXUNDERRUNMSK_MASK 0x2 + +/* Interrupt mask, active low. */ +#define TX_INT_MASK_GNTTOOSHORTMSK_MASK 0x1 + + +/* + * Register + * + * Provides dataPort read/write access to various RAMs. + */ +#define XPCSTX_TX_PORT_COMMAND_REG 0xc + +/* + * Indicates dataPort is in progress. + * Bit must be cleared before thenext dataPort access can be issued. +*/ +#define TX_PORT_COMMAND_DATAPORTBUSY_MASK 0x80000000 + +/* + * Selects the RAM for access : + * 0 - FEC vector RAM. +*/ +#define TX_PORT_COMMAND_PORTSELECT_SHIFT 24 +#define TX_PORT_COMMAND_PORTSELECT_MASK 0x3f000000 + +/* + * Indicates write access : + * 0 - read; 1 - write. +*/ +#define TX_PORT_COMMAND_PORTOPCODE_SHIFT 16 +#define TX_PORT_COMMAND_PORTOPCODE_MASK 0xff0000 + +/* Specifies the RAM address for access. */ +#define TX_PORT_COMMAND_PORTADDRESS_SHIFT 0 +#define TX_PORT_COMMAND_PORTADDRESS_MASK 0xffff + + +/* + * Register + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XPCSTX_TX_DATA_PORT_0_REG 0x10 + +/* + * XPCSTX_VEC_RAM[31: + * 0]. +*/ +#define TX_DATA_PORT_0_PORTDATA0_SHIFT 0 +#define TX_DATA_PORT_0_PORTDATA0_MASK 0xffffffff + + +/* + * Register + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XPCSTX_TX_DATA_PORT_1_REG 0x14 + +/* + * XPCSTX_VEC_RAM[63: + * 32]. +*/ +#define TX_DATA_PORT_1_PORTDATA1_SHIFT 0 +#define TX_DATA_PORT_1_PORTDATA1_MASK 0xffffffff + + +/* + * Register + * + * Stores the pre-write data for writing; and the post-read data + * forreading. + */ +#define XPCSTX_TX_DATA_PORT_2_REG 0x18 + +/* + * [1: + * 0] - XPCSTX_VEC_RAM[66: + * 65]. +*/ +#define TX_DATA_PORT_2_PORTDATA2_SHIFT 0 +#define TX_DATA_PORT_2_PORTDATA2_MASK 0xffffffff + + +/* + * Register + * + * Specifies the sync pattern codeword. + */ +#define XPCSTX_TX_SYNC_PATT_CWORD_LO_REG 0x1c + +/* Defines the low order sync pattern codeword. */ +#define TX_SYNC_PATT_CWORD_LO_CFGSYNCPATCWL_SHIFT 0 +#define TX_SYNC_PATT_CWORD_LO_CFGSYNCPATCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the sync pattern codeword. + */ +#define XPCSTX_TX_SYNC_PATT_CWORD_HI_REG 0x20 + +/* Defines the high order sync pattern codeword. */ +#define TX_SYNC_PATT_CWORD_HI_CFGSYNCPATCWH_SHIFT 0 +#define TX_SYNC_PATT_CWORD_HI_CFGSYNCPATCWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the start-of-burst delimiter codeword. + */ +#define XPCSTX_TX_START_BURST_DEL_CWORD_LO_REG 0x24 + +/* Defines the low order start-of-burst delimiter codeword. */ +#define TX_START_BURST_DEL_CWORD_LO_CFGSTRTBRSTDLMTRCWL_SHIFT 0 +#define TX_START_BURST_DEL_CWORD_LO_CFGSTRTBRSTDLMTRCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the start-of-burst delimiter codeword. + */ +#define XPCSTX_TX_START_BURST_DEL_CWORD_HI_REG 0x28 + +/* Defines the high order start-of-burst delimiter codeword. */ +#define TX_START_BURST_DEL_CWORD_HI_CFGSTRTBRSTDLMTRCWH_SHIFT 0 +#define TX_START_BURST_DEL_CWORD_HI_CFGSTRTBRSTDLMTRCWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the end-of-burst terminating codeword. + */ +#define XPCSTX_TX_END_BURST_DEL_CWORD_LO_REG 0x2c + +/* Defines the low order terminating codeword. */ +#define TX_END_BURST_DEL_CWORD_LO_CFGENDBRSTDLMTRCWL_SHIFT 0 +#define TX_END_BURST_DEL_CWORD_LO_CFGENDBRSTDLMTRCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the end-of-burst terminating codeword. + */ +#define XPCSTX_TX_END_BURST_DEL_CWORD_HI_REG 0x30 + +/* Defines the high order terminating codeword. */ +#define TX_END_BURST_DEL_CWORD_HI_CFGENDBRSTDLMTRCWH_SHIFT 0 +#define TX_END_BURST_DEL_CWORD_HI_CFGENDBRSTDLMTRCWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the IDLE codeword. + */ +#define XPCSTX_TX_IDLE_CWORD_LO_REG 0x34 + +/* Defines the low order codeword. */ +#define TX_IDLE_CWORD_LO_CFGIDLECWL_SHIFT 0 +#define TX_IDLE_CWORD_LO_CFGIDLECWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the IDLE codeword. + */ +#define XPCSTX_TX_IDLE_CWORD_HI_REG 0x38 + +/* Defines the high order codeword. */ +#define TX_IDLE_CWORD_HI_CFGIDLECWH_SHIFT 0 +#define TX_IDLE_CWORD_HI_CFGIDLECWH_MASK 0xffffffff + + +/* + * Register + * + * Specifies the codeword in between burst. + */ +#define XPCSTX_TX_BURST_PATT_CWORD_LO_REG 0x3c + +/* Defines the low order burst delimiter codeword. */ +#define TX_BURST_PATT_CWORD_LO_CFGBURSTPATCWL_SHIFT 0 +#define TX_BURST_PATT_CWORD_LO_CFGBURSTPATCWL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the codeword in between burst. + */ +#define XPCSTX_TX_BURST_PATT_CWORD_HI_REG 0x40 + +/* Defines the high order burst delimiter codeword. */ +#define TX_BURST_PATT_CWORD_HI_CFGBURSTPATCWH_SHIFT 0 +#define TX_BURST_PATT_CWORD_HI_CFGBURSTPATCWH_MASK 0xffffffff + + +/* + * Register + * + * Provides control for the laser enable. + */ +#define XPCSTX_TX_LASER_TIME_REG 0x44 + +/* + * Specifies the laser pipeline delay, in unit of 6. + * 2ns (161 MHzclock). +*/ +#define TX_LASER_TIME_CFGLASERPIPE125_SHIFT 16 +#define TX_LASER_TIME_CFGLASERPIPE125_MASK 0x3f0000 + +/* + * Specifies the laser off delay to the actual laser off time, value X. + * Resulting delay = INT(X*2. + * 5)*6. + * 2 ns, based on 161 MHz clock. +*/ +#define TX_LASER_TIME_CFGLASEROFFDLYTQ125_SHIFT 8 +#define TX_LASER_TIME_CFGLASEROFFDLYTQ125_MASK 0xf00 + +/* + * Specifies the laser enable delay to the actual laser on time, valueX. + * Resulting delay = INT(X*2. + * 5)*6. + * 2 ns, based on 161 MHz clock . +*/ +#define TX_LASER_TIME_CFGLASERONDLYTQ125_SHIFT 0 +#define TX_LASER_TIME_CFGLASERONDLYTQ125_MASK 0xf + + +/* + * Register + * + * Specifies the MAC mode of operation. + */ +#define XPCSTX_TX_MAC_MODE_REG 0x48 + +/* Enable point-to-point transmission without grant. */ +#define TX_MAC_MODE_CFGENNOGNTXMT125_MASK 0x2 + + +/* + * Register + * + * Provides control for laser monitor. + */ +#define XPCSTX_TX_LASER_MONITOR_CTL_REG 0x4c + +/* Status of laser enable, directly from I/O pin. */ +#define TX_LASER_MONITOR_CTL_LASERENSTATUS_MASK 0x20 + +/* + * Laser monitor polarity. + * 0 - active low; 1 - active high. +*/ +#define TX_LASER_MONITOR_CTL_CFGLSRMONACTHI_MASK 0x10 + +/* + * Laser monitor reset. + * 0 - Reset; 1 - Normal operation. +*/ +#define TX_LASER_MONITOR_CTL_LASERMONRSTN_MASK 0x1 + + +/* + * Register + * + * Specifies maximum threshold of laser_on assertion before interrupt + * isgenerated. + */ +#define XPCSTX_TX_LASER_MONITOR_MAX_THRESH_REG 0x50 + +/* Maximum assertion threshold, in unit of TQ. */ +#define TX_LASER_MONITOR_MAX_THRESH_CFGLSRMONMAXTQ_SHIFT 0 +#define TX_LASER_MONITOR_MAX_THRESH_CFGLSRMONMAXTQ_MASK 0xffffffff + + +/* + * Register - read-only + * + * Indicates the burst length of current grant, in unit of TQ (16 ns). + */ +#define XPCSTX_TX_LASER_MONITOR_BURST_LEN_REG 0x54 + +/* Indicates the laser-on time of the burst that set laserOffinterrupt. */ +#define TX_LASER_MONITOR_BURST_LEN_LASERONLENGTH_SHIFT 0 +#define TX_LASER_MONITOR_BURST_LEN_LASERONLENGTH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the number of burst. + * Clear on read. + */ +#define XPCSTX_TX_LASER_MONITOR_BURST_COUNT_REG 0x58 + +/* + * This values increments on deassertion edge of laser enable. + * Peg atmax value of 0xFFFFFFFF +*/ +#define TX_LASER_MONITOR_BURST_COUNT_BURSTCNT_SHIFT 0 +#define TX_LASER_MONITOR_BURST_COUNT_BURSTCNT_MASK 0xffffffff + + +#endif /* ! EPON_XPCSTX_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/serdes_regs.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/serdes_regs.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/serdes_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/serdes_regs.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,284 @@ +/*************************************************************************** +// Serdes registers in full chip address map + ***************************************************************************/ +#define PCS_ID 0x0000 + +#define DEVID_0 0x0000 +#define DEVID_1 0x0800 + +#define serdes_PLL_0 0x0000 +#define serdes_PLL_1 0x0100 + +#define LANE_0 0x0000 +#define LANE_1 0x0001 +#define LANE_2 0x0002 +#define LANE_3 0x0003 +#define LANE_BRDCST 0x00FF +#define LANE_01 0x0200 +#define LANE_23 0x0201 + +#define DSC_A_cdr_control_0 0xD001 +#define DSC_A_cdr_control_1 0xD002 +#define DSC_A_cdr_control_2 0xD003 +#define DSC_A_rx_pi_control 0xD004 +#define DSC_A_cdr_status_integ_reg 0xD005 +#define DSC_A_cdr_status_phase_error 0xD006 +#define DSC_A_rx_pi_cnt_bin_d 0xD007 +#define DSC_A_rx_pi_cnt_bin_p 0xD008 +#define DSC_A_rx_pi_cnt_bin_m 0xD009 +#define DSC_A_rx_pi_diff_bin 0xD00A +#define DSC_A_trnsum_cntl_5 0xD00B +#define DSC_A_dsc_uc_ctrl 0xD00D +#define DSC_A_dsc_scratch 0xD00E +#define DSC_B_dsc_sm_ctrl_0 0xD010 +#define DSC_B_dsc_sm_ctrl_1 0xD011 +#define DSC_B_dsc_sm_ctrl_2 0xD012 +#define DSC_B_dsc_sm_ctrl_3 0xD013 +#define DSC_B_dsc_sm_ctrl_4 0xD014 +#define DSC_B_dsc_sm_ctrl_5 0xD015 +#define DSC_B_dsc_sm_ctrl_6 0xD016 +#define DSC_B_dsc_sm_ctrl_7 0xD017 +#define DSC_B_dsc_sm_ctrl_8 0xD018 +#define DSC_B_dsc_sm_ctrl_9 0xD019 +#define DSC_B_dsc_sm_status_dsc_lock 0xD01A +#define DSC_B_dsc_sm_status_dsc_state_one_hot 0xD01B +#define DSC_B_dsc_sm_status_dsc_state_eee_one_hot 0xD01C +#define DSC_B_dsc_sm_status_restart 0xD01D +#define DSC_B_dsc_sm_status_dsc_state 0xD01E +#define DSC_C_dfe_common_ctl 0xD020 +#define DSC_C_dfe_1_ctl 0xD021 +#define DSC_C_dfe_1_pat_ctl 0xD022 +#define DSC_C_dfe_2_ctl 0xD023 +#define DSC_C_dfe_2_pat_ctl 0xD024 +#define DSC_C_dfe_3_ctl 0xD025 +#define DSC_C_dfe_3_pat_ctl 0xD026 +#define DSC_C_dfe_4_ctl 0xD027 +#define DSC_C_dfe_4_pat_ctl 0xD028 +#define DSC_C_dfe_5_ctl 0xD029 +#define DSC_C_dfe_5_pat_ctl 0xD02A +#define DSC_C_dfe_vga_override 0xD02B +#define DSC_C_vga_ctl 0xD02C +#define DSC_C_vga_pat_eyediag_ctl 0xD02D +#define DSC_C_p1_frac_offs_ctl 0xD02E +#define DSC_D_trnsum_ctl_1 0xD030 +#define DSC_D_trnsum_ctl_2 0xD031 +#define DSC_D_trnsum_ctl_3 0xD032 +#define DSC_D_trnsum_ctl_4 0xD033 +#define DSC_D_trnsum_sts_1 0xD034 +#define DSC_D_trnsum_sts_2 0xD035 +#define DSC_D_trnsum_sts_3 0xD036 +#define DSC_D_trnsum_sts_4 0xD037 +#define DSC_D_trnsum_sts_5 0xD038 +#define DSC_D_trnsum_sts_6 0xD039 +#define DSC_D_vga_p1eyediag_sts 0xD03A +#define DSC_D_dfe_1_sts 0xD03B +#define DSC_D_dfe_2_sts 0xD03C +#define DSC_D_dfe_3_4_5_sts 0xD03D +#define DSC_D_vga_tap_bin 0xD03E +#define DSC_E_dsc_e_ctrl 0xD040 +#define DSC_E_dsc_e_pf_ctrl 0xD041 +#define DSC_E_dsc_e_pf2_lowp_ctrl 0xD042 +#define DSC_E_dsc_e_offset_adj_data_odd 0xD043 +#define DSC_E_dsc_e_offset_adj_data_even 0xD044 +#define DSC_E_dsc_e_offset_adj_p1_odd 0xD045 +#define DSC_E_dsc_e_offset_adj_p1_even 0xD046 +#define DSC_E_dsc_e_offset_adj_m1_odd 0xD047 +#define DSC_E_dsc_e_offset_adj_m1_even 0xD048 +#define DSC_E_dsc_e_dc_offset 0xD049 +#define DSC_F_ONU10G_looptiming_ctrl_0 0xD050 +#define TX_PI_LBE_tx_pi_control_0 0xD070 +#define TX_PI_LBE_tx_pi_control_1 0xD071 +#define TX_PI_LBE_tx_pi_control_2 0xD072 +#define TX_PI_LBE_tx_pi_control_3 0xD073 +#define TX_PI_LBE_tx_pi_control_4 0xD074 +#define TX_PI_LBE_tx_pi_control_6 0xD076 +#define TX_PI_LBE_tx_pi_status_0 0xD078 +#define TX_PI_LBE_tx_pi_status_1 0xD079 +#define TX_PI_LBE_tx_pi_status_2 0xD07A +#define TX_PI_LBE_tx_pi_status_3 0xD07B +#define TX_PI_LBE_tx_lbe_control_0 0xD07C +#define CKRST_CTRL_OSR_MODE_CONTROL 0xD080 +#define CKRST_CTRL_LANE_CLK_RESET_N_POWERDOWN_CONTROL 0xD081 +#define CKRST_CTRL_LANE_AFE_RESET_PWRDWN_CONTROL_CONTROL 0xD082 +#define CKRST_CTRL_LANE_RESET_N_PWRDN_PIN_KILL_CONTROL 0xD083 +#define CKRST_CTRL_LANE_DEBUG_RESET_CONTROL 0xD084 +#define CKRST_CTRL_UC_ACK_LANE_CONTROL 0xD085 +#define CKRST_CTRL_LANE_REG_RESET_OCCURRED_CONTROL 0xD086 +#define CKRST_CTRL_CLOCK_N_RESET_DEBUG_CONTROL 0xD087 +#define CKRST_CTRL_PMD_LANE_MODE_STATUS 0xD088 +#define CKRST_CTRL_LANE_DP_RESET_STATE_STATUS 0xD089 +#define CKRST_CTRL_LN_MASK 0xD08A +#define CKRST_CTRL_OSR_MODE_STATUS 0xD08B +#define CKRST_CTRL_AFE_RESET_PWRDN_OSR_MODE_PIN_STATUS 0xD08C +#define CKRST_CTRL_PLL_SELECT_CONTROL 0xD08D +#define CKRST_CTRL_LN_S_RSTB_CONTROL 0xD08E +#define AMS_RX_RX_CONTROL_0 0xD090 +#define AMS_RX_RX_CONTROL_1 0xD091 +#define AMS_RX_RX_CONTROL_2 0xD092 +#define AMS_RX_RX_CONTROL_3 0xD093 +#define AMS_RX_RX_CONTROL_4 0xD094 +#define AMS_RX_RX_INTCTRL 0xD098 +#define AMS_RX_RX_STATUS 0xD099 +#define AMS_TX_TX_CONTROL_0 0xD0A0 +#define AMS_TX_TX_CONTROL_1 0xD0A1 +#define AMS_TX_TX_CONTROL_2 0xD0A2 +#define AMS_TX_TX_INTCTRL 0xD0A8 +#define AMS_TX_TX_STATUS 0xD0A9 +#define AMS_COM_PLL_CONTROL_0 0xD0B0 +#define AMS_COM_PLL_CONTROL_1 0xD0B1 +#define AMS_COM_PLL_CONTROL_2 0xD0B2 +#define AMS_COM_PLL_CONTROL_3 0xD0B3 +#define AMS_COM_PLL_CONTROL_4 0xD0B4 +#define AMS_COM_PLL_CONTROL_5 0xD0B5 +#define AMS_COM_PLL_CONTROL_6 0xD0B6 +#define AMS_COM_PLL_CONTROL_7 0xD0B7 +#define AMS_COM_PLL_CONTROL_8 0xD0B8 +#define AMS_COM_PLL_INTCTRL 0xD0B9 +#define AMS_COM_PLL_STATUS 0xD0BA +#define SIGDET_SIGDET_CTRL_0 0xD0C0 +#define SIGDET_SIGDET_CTRL_1 0xD0C1 +#define SIGDET_SIGDET_CTRL_2 0xD0C2 +#define SIGDET_SIGDET_CTRL_3 0xD0C3 +#define SIGDET_SIGDET_STATUS_0 0xD0C8 +#define TLB_RX_prbs_chk_cnt_config 0xD0D0 +#define TLB_RX_prbs_chk_config 0xD0D1 +#define TLB_RX_dig_lpbk_config 0xD0D2 +#define TLB_RX_tlb_rx_misc_config 0xD0D3 +#define TLB_RX_prbs_chk_en_timer_control 0xD0D4 +#define TLB_RX_dig_lpbk_pd_status 0xD0D8 +#define TLB_RX_prbs_chk_lock_status 0xD0D9 +#define TLB_RX_prbs_chk_err_cnt_msb_status 0xD0DA +#define TLB_RX_prbs_chk_err_cnt_lsb_status 0xD0DB +#define TLB_RX_pmd_rx_lock_status 0xD0DC +#define TLB_TX_patt_gen_config 0xD0E0 +#define TLB_TX_prbs_gen_config 0xD0E1 +#define TLB_TX_rmt_lpbk_config 0xD0E2 +#define TLB_TX_tlb_tx_misc_config 0xD0E3 +#define TLB_TX_tx_pi_loop_timing_config 0xD0E4 +#define TLB_TX_rmt_lpbk_pd_status 0xD0E8 +#define DIG_COM_REVID0 0xD0F0 +#define DIG_COM_RESET_CONTROL_PMD 0xD0F1 +#define DIG_COM_RESET_CONTROL_CORE_DP 0xD0F2 +#define DIG_COM_DEBUG_CONTROL 0xD0F3 +#define DIG_COM_TOP_USER_CONTROL_0 0xD0F4 +#define DIG_COM_CORE_REG_RESET_OCCURRED_CONTROL 0xD0F6 +#define DIG_COM_RST_SEQ_TIMER_CONTROL 0xD0F7 +#define DIG_COM_CORE_DP_RESET_STATE_STATUS 0xD0F8 +#define DIG_COM_REVID1 0xD0FA +#define DIG_COM_REVID2 0xD0FE +#define PATT_GEN_patt_gen_seq_0 0xD100 +#define PATT_GEN_patt_gen_seq_1 0xD101 +#define PATT_GEN_patt_gen_seq_2 0xD102 +#define PATT_GEN_patt_gen_seq_3 0xD103 +#define PATT_GEN_patt_gen_seq_4 0xD104 +#define PATT_GEN_patt_gen_seq_5 0xD105 +#define PATT_GEN_patt_gen_seq_6 0xD106 +#define PATT_GEN_patt_gen_seq_7 0xD107 +#define PATT_GEN_patt_gen_seq_8 0xD108 +#define PATT_GEN_patt_gen_seq_9 0xD109 +#define PATT_GEN_patt_gen_seq_10 0xD10A +#define PATT_GEN_patt_gen_seq_11 0xD10B +#define PATT_GEN_patt_gen_seq_12 0xD10C +#define PATT_GEN_patt_gen_seq_13 0xD10D +#define PATT_GEN_patt_gen_seq_14 0xD10E +#define TX_FED_txfir_control1 0xD110 +#define TX_FED_txfir_control2 0xD111 +#define TX_FED_txfir_control3 0xD112 +#define TX_FED_txfir_status1 0xD113 +#define TX_FED_txfir_status2 0xD114 +#define TX_FED_txfir_status3 0xD115 +#define TX_FED_txfir_status4 0xD116 +#define TX_FED_micro_control 0xD117 +#define TX_FED_misc_control1 0xD118 +#define TX_FED_txfir_control4 0xD119 +#define TX_FED_misc_status0 0xD11B +#define PLL_CAL_COM_CTL_0 0xD120 +#define PLL_CAL_COM_CTL_1 0xD121 +#define PLL_CAL_COM_CTL_2 0xD122 +#define PLL_CAL_COM_CTL_3 0xD123 +#define PLL_CAL_COM_CTL_4 0xD124 +#define PLL_CAL_COM_CTL_5 0xD125 +#define PLL_CAL_COM_CTL_6 0xD126 +#define PLL_CAL_COM_CTL_7 0xD127 +#define PLL_CAL_COM_CTL_STATUS_0 0xD128 +#define PLL_CAL_COM_CTL_STATUS_1 0xD129 +#define TXCOM_CL72_tap_preset_control 0xD132 +#define TXCOM_CL72_debug_1_register 0xD133 +#define CORE_PLL_COM_PMD_CORE_MODE_STATUS 0xD150 +#define CORE_PLL_COM_RESET_CONTROL_PLL_DP 0xD152 +#define CORE_PLL_COM_TOP_USER_CONTROL 0xD154 +#define CORE_PLL_COM_UC_ACK_CORE_CONTROL 0xD155 +#define CORE_PLL_COM_PLL_DP_RESET_STATE_STATUS 0xD158 +#define CORE_PLL_COM_CORE_PLL_COM_STATUS_2 0xD159 +#define MICRO_A_ramword 0xD200 +#define MICRO_A_address 0xD201 +#define MICRO_A_command 0xD202 +#define MICRO_A_ram_wrdata 0xD203 +#define MICRO_A_ram_rddata 0xD204 +#define MICRO_A_download_status 0xD205 +#define MICRO_A_sfr_status 0xD206 +#define MICRO_A_mdio_uc_mailbox_msw 0xD207 +#define MICRO_A_mdio_uc_mailbox_lsw 0xD208 +#define MICRO_A_uc_mdio_mailbox_lsw 0xD209 +#define MICRO_A_command2 0xD20A +#define MICRO_A_uc_mdio_mailbox_msw 0xD20B +#define MICRO_A_command3 0xD20C +#define MICRO_A_command4 0xD20D +#define MICRO_A_temperature_status 0xD20E +#define MICRO_B_program_ram_control1 0xD210 +#define MICRO_B_dataram_control1 0xD214 +#define MICRO_B_iram_control1 0xD218 +#define MDIO_MMDSEL_AER_COM_mdio_maskdata 0xFFDB +#define MDIO_MMDSEL_AER_COM_mdio_brcst_port_addr 0xFFDC +#define MDIO_MMDSEL_AER_COM_mdio_mmd_select 0xFFDD +#define MDIO_MMDSEL_AER_COM_mdio_aer 0xFFDE +#define MDIO_BLK_ADDR_BLK_ADDR 0xFFDF + +#define XGXSBLK0_XGXSCTRL 0x8000 +#define XGXSBLK1_LANECTRL0 0x8015 +#define XGXSBLk1_LANECTRL1 0x8016 + +#define XgxsBlk10_tx_pi_control4 0x00008190 + #define tx_pi_sm_enable_override_value (1<<14) // RXSM Status 0x8366 Read & Clear control + +#define SerdesDigital_misc1 0x8308 +#define Digital4_Misc3 0x833c +#define Digital4_Misc4 0x833d +#define Digital5_parDetINDControl1 0x8347 +#define Digital5_parDetINDControl2 0x8348 +#define Digital5_Misc7 0x8349 +#define Digital5_Misc6 0x8345 +#define tx66_Control 0x83b0 +#define FX100_Control3 0x8402 +#define ieee0Blk_MIICntl 0x0000 +#define FX100_Control1 0x8400 +#define rx66b1_rx66b1_Control1 0x8441 + #define rfifo_ptr_sw_rst (1<<0) + +#define XGXSBLK4_xgxsStatus1 0x00008122 +#define XgxsStatus1_LinkStat (1<<9) +#define XgxsStatus1_Speed_Mask (0xf) +#define XgxsStatus1_Speed_10G (0x6) + +#define SerdesDigital_Control1000X1 0x8300 +#define SerdesDigital_SgmiiMasterMode (1<<5) +#define SerdesDigital_SgmiiAutoMode (1<<4) +#define SerdesDigital_FibreSgmiiModeFibre (1<<0) + +#define SerdesDigital_Control1000X2 0x8301 +#define SerdesDigital_AutoNegoFastTimer (1<<6) +#define SerdesDigital_DisableRemoteFaultSending (1<<4) +#define SerdesDigital_FilterForceLink (1<<2) +#define SerdesDigital_DisasbleFalseLink (1<<1) +#define SerdesDigital_EnableParallelDetection (1<<0) + +#define SerdesDigital_Control1000X3 0x8302 + +#define SerdesDigital_Status1000X2 0x8305 +#define Status1000X2_sync_failed (1 << 11) +#define Status1000X2_sync_ok (1 << 10) + +#define SerdesDigital_rx66_Status 0x83c1 + +#define CL49_UserB0_Control 0x8368 + #define CL49_fast_lock_cya (1<<5) diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/unimac_regs.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/unimac_regs.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/unimac_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/unimac_regs.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,482 @@ +#ifndef UNIMAC_REGS_H_ +#define UNIMAC_REGS_H_ + +#define UNIMAC_CFG_OFFSET(mac) (0x0000 + (mac) * 0x1000) +#define UNIMAC_MIB_OFFSET(mac) (0x8000 + (mac) * 0x400) +#define UNIMAC_MISC_OFFSET(mac) (0xa000 + (mac) * 0x400) + +/* + * configuration registers + */ + +/* UniMAC Dummy Register */ +#define UNIMAC_CFG_UMAC_DUMMY_REG (0x0000) + +/* UniMAC Half Duplex Backpressure Control Register */ +#define UNIMAC_CFG_HD_BKP_CNTL_REG (0x0004) + +/* UniMAC Command Register */ +#define UNIMAC_CFG_CMD_REG (0x0008) + +/* + * 1: The MAC transmit function is enabled. 0: The MAC transmit + * function is disabled. The enable works on packet boundary meaning + * that only on the assertion of the bit during every SOP. Reset + * value is 0x0. + */ +#define UNIMAC_CFG_CMD_TX_EN_SHIFT 0 +#define UNIMAC_CFG_CMD_TX_EN_MASK (1 << UNIMAC_CFG_CMD_TX_EN_SHIFT) + +/* + * 1: The MAC receive function is enabled. 0: The MAC receive function + * is disabled. The enable works on packet boundary meaning that only + * on the assertion on the bit during every 0->1 transition of rx_dv. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RX_EN_SHIFT 1 +#define UNIMAC_CFG_CMD_RX_EN_MASK (1 << UNIMAC_CFG_CMD_RX_EN_SHIFT) + + +/* + * 00: 10Mbps, 01: 100Mbps, 10: 1000Mbps, 11: 2500Mbps + * Reset value is 0x2. + */ +#define UNIMAC_CFG_CMD_SPEED_SHIFT 2 +#define UNIMAC_CFG_CMD_SPEED_MASK (0x3 << UNIMAC_CFG_CMD_SPEED_SHIFT) +#define UNIMAC_CFG_CMD_SPEED_10 0 +#define UNIMAC_CFG_CMD_SPEED_100 1 +#define UNIMAC_CFG_CMD_SPEED_1000 2 +#define UNIMAC_CFG_CMD_SPEED_2500 3 + +/* + * 1: All frames are received without Unicast address filtering. + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_PROMISC_EN_SHIFT 4 +#define UNIMAC_CFG_CMD_PROMISC_EN_MASK (1 << UNIMAC_CFG_CMD_PROMISC_EN_SHIFT) + +/* + * 1: Padding is removed along with crc field before the frame is sent to + * the user application. + * + * 0: No padding is removed by the MAC. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_PAD_EN_SHIFT 5 +#define UNIMAC_CFG_CMD_PAD_EN_MASK (1 << UNIMAC_CFG_CMD_PAD_EN_SHIFT) + +/* + * 1: The CRC field of received frames is transmitted to the user application. + * 0: The CRC field is stripped from the frame. + * + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_CRC_FWD_SHIFT 6 +#define UNIMAC_CFG_CMD_CRC_FWD_MASK (1 << UNIMAC_CFG_CMD_CRC_FWD_SHIFT) + +/* + * 1: PAUSE frames are forwarded to the user application. + * 0: The PAUSE frames are terminated and discarded in the MAC. + * + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_PAUSE_FWD_SHIFT 7 +#define UNIMAC_CFG_CMD_PAUSE_FWD_MASK (1 << UNIMAC_CFG_CMD_PAUSE_FWD_SHIFT) + +/* + * 1: Receive PAUSE frames are ignored by the MAC. + * + * 0: The tramsmit process is stiooed for the amount of time specified + * in the pause quanta received within the PAUSE frame. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RX_PAUSE_IGN_SHIFT 8 +#define UNIMAC_CFG_CMD_RX_PAUSE_IGN_MASK (1 << UNIMAC_CFG_CMD_RX_PAUSE_IGN_SHIFT) + +/* + * 1: The MAC overwrites the source MAC address with a programmed MAC + * address in register MAC_0 and MAC_1. + * + * 0: Not modify the source address received from the transmit + * application client. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_TX_ADDR_INSERT_SHIFT 9 +#define UNIMAC_CFG_CMD_TX_ADDR_INSERT_MASK (1 << UNIMAC_CFG_CMD_TX_ADDR_INSERT_SHIFT) + +/* + * Ignored when RTH_SPEED[1]==1, gigabit mode. + * 1: half duplex + * 0: full duplex + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_HD_ENA_SHIFT 10 +#define UNIMAC_CFG_CMD_HD_ENA_MASK (1 << UNIMAC_CFG_CMD_HD_ENA) + +/* + * 1: RX and RX engines are put in reset. + * 0: come out of SW reset. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_SW_RESET_SHIFT 13 +#define UNIMAC_CFG_CMD_SW_RESET_MASK (1 << UNIMAC_CFG_CMD_SW_RESET_SHIFT) + +/* + * Enable GMII/MII loopback + * 1: Loopback enabled. + * 0: Normal operation. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_LCL_LOOP_EN_SHIFT 15 +#define UNIMAC_CFG_CMD_LCL_LOOP_EN_MASK (1 << UNIMAC_CFG_CMD_LCL_LOOP_EN_SHIFT) + +/* + * Enable/Disable auto-configuration. + * 1: Enable + * 0: Disable + * Reset value is 0x0 + */ +#define UNIMAC_CFG_CMD_ENA_EXT_EN_SHIFT 22 +#define UNIMAC_CFG_CMD_ENA_EXT_EN_MASK (1 << UNIMAC_CFG_CMD_ENA_EXT_EN_SHIFT) + +/* + * MAC control frame enable. + * + * 1: MAC control frames with opcode other than 0x0001 are accepted + * and forwarded to the client interface. + * + * 0: MAC control frames with opcode other than 0x0000 and 0x0001 are + * silently discarded. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_CTRL_FRM_EN_SHIFT 23 +#define UNIMAC_CFG_CMD_CTRL_FRM_EN_MASK (1 << UNIMAC_CFG_CMD_CTRL_FRM_EN_SHIFT) + +/* + * Payload length check. + * 0: Check payload length with Length/Type field. + * 1: Check disabled. + * Reset value is 0x1. + */ +#define UNIMAC_CFG_CMD_DIS_LEN_CHECK_SHIFT 26 +#define UNIMAC_CFG_CMD_DIS_LEN_CHECK_IGN_MASK (1 << UNIMAC_CFG_CMD_DIS_LEN_CHECK_SHIFT) + +/* + * Enable remote loopback at the fifo system side. + * 0: Normal operation + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RMT_LOOP_EN_SHIFT 25 +#define UNIMAC_CFG_CMD_RMT_LOOP_EN_MASK (1 << UNIMAC_CFG_CMD_RMT_LOOP_EN_SHIFT) + +/* + * Enable extract/insert of EFM headers. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_PRBL_EN_SHIFT 27 +#define UNIMAC_CFG_CMD_PRBL_EN_MASK (1 << UNIMAC_CFG_CMD_PRBL_EN_SHIFT) + +/* + * Ignore TX PAUSE frame transmit request. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_TX_PAUSE_IGN_SHIFT 28 +#define UNIMAC_CFG_CMD_TX_PAUSE_IGN_MASK (1 << UNIMAC_CFG_CMD_TX_PAUSE_IGN_SHIFT) + +/* + * This mode only works in auto-config mode: + * + * 0: After auto-config, TX_ENA and RX_ENA bits are set to 1. + * + * 1: After auto-config, TX_ENA and RX_ENA bits are set to 0, meaning + * SW will have to come in and enable TX and RX. + * + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_TXRX_EN_SHIFT 29 +#define UNIMAC_CFG_CMD_TXRX_EN_MASK (1 << UNIMAC_CFG_CMD_TXRX_EN_SHIFT) + +/* + * 1: Disable RX side RUNT filtering. + * 0: Enable RUNT filtering. + * Reset value is 0x0. + */ +#define UNIMAC_CFG_CMD_RUNT_FILT_DIS_SHIFT 30 +#define UNIMAC_CFG_CMD_RUNT_FILT_DIS_MASK (1 << UNIMAC_CFG_CMD_RUNT_FILT_DIS_SHIFT) + + +/* UniMAC MAC address first 4 bytes */ +#define UNIMAC_CFG_MAC0_REG (0x000c) + +/* UniMAC MAC address 2 last bytes */ +#define UNIMAC_CFG_MAC1_REG (0x0010) + +/* UniMAC Frame Length */ +#define UNIMAC_CFG_FRM_LEN_REG (0x0014) + +/* UniMAC Pause Quanta */ +#define UNIMAC_CFG_PAUSE_QUNAT_REG (0x0018) + +/* UniMAC EFM Preamble Length */ +#define UNIMAC_CFG_SFD_OFFSET_REG (0x0040) + +/* UniMAC Mode */ +#define UNIMAC_CFG_MODE_REG (0x0044) + +/* UniMAC Preamble Outer TAG 0 */ +#define UNIMAC_CFG_FRM_TAG0_REG (0x0048) + +/* UniMAC Preamble Outer TAG 1 */ +#define UNIMAC_CFG_FRM_TAG1_REG (0x004c) + +/* UniMAC Inter Packet Gap */ +#define UNIMAC_CFG_TX_IPG_LEN_REG (0x005c) + +/* UniMAC Energy Efficient Ethernet Control */ +#define UNIMAC_CFG_EEE_CTRL_REG (0x0064) + +/* EEE LPI timer */ +#define UNIMAC_CFG_EEE_LPI_TIMER_REG (0x0068) + +/* EEE wakeup timer */ +#define UNIMAC_CFG_EEE_WAKE_TIMER_REG (0x006c) + +/* UniMAC Energy Efficient Ethernet Ref Clock Speed */ +#define UNIMAC_CFG_EEE_REF_COUNT_REG (0x0070) + +/* MII EEE LPI timer */ +#define UNIMAC_CFG_EEE_MII_LPI_TIMER_REG (0x0068) + +/* GMII EEE LPI timer */ +#define UNIMAC_CFG_EEE_GMII_LPI_TIMER_REG (0x006c) + +/* MII EEE wakeup timer */ +#define UNIMAC_CFG_EEE_MII_WAKE_TIMER_REG (0x0080) + +/* GMII EEE wakeup timer */ +#define UNIMAC_CFG_EEE_GMII_WAKE_TIMER_REG (0x0084) + +/* UniMAC Repetitive Pause Control in TX direction */ +#define UNIMAC_CFG_PAUSE_CNTRL_REG (0x0330) + +/* UniMAC RX MAX packet Size Register */ +#define UNIMAC_CFG_RX_MAX_PKT_SIZE_REG (0x0608) + + +/* + * MIB registers + */ + +/* Receive 64B Frame Counter */ +#define UNIMAC_MIB_GR64_REG (0x0000) + +/* Receive 65B to 127B Frame Counter */ +#define UNIMAC_MIB_GR127_REG (0x0004) + +/* Receive 128B to 255B Frame Counter */ +#define UNIMAC_MIB_GR255_REG (0x0008) + +/* Receive 256B to 511B Frame Counter */ +#define UNIMAC_MIB_GR511_REG (0x000c) + +/* Receive 512B to 1023B Frame Counter */ +#define UNIMAC_MIB_GR1023_REG (0x0010) + +/* Receive 1024B to 1518B Frame Counter */ +#define UNIMAC_MIB_GR1518_REG (0x0014) + +/* Receive 1519B to 1522B Good VLAN Frame Counter */ +#define UNIMAC_MIB_GRMGV_REG (0x0018) + +/* Receive 1519B to 2047B Frame Counter */ +#define UNIMAC_MIB_GR2047_REG (0x001c) + +/* Receive 2048B to 4095B Frame Counter */ +#define UNIMAC_MIB_GR4095_REG (0x0020) + +/* Receive 4096B to 9216B Frame Counter */ +#define UNIMAC_MIB_GR9216_REG (0x0024) + +/* Receive Packet Counter */ +#define UNIMAC_MIB_GRPKT_REG (0x0028) + +/* Receive Byte Counter */ +#define UNIMAC_MIB_GRBYT_REG (0x002c) + +/* Receive Multicast Frame Counter */ +#define UNIMAC_MIB_GRMCA_REG (0x0030) + +/* Receive Broadcast Frame Counter */ +#define UNIMAC_MIB_GRBCA_REG (0x0034) + +/* Receive FCS Error Counter */ +#define UNIMAC_MIB_GRFCS_REG (0x0038) + +/* Receive Control Frame Packet Counter */ +#define UNIMAC_MIB_GRXCF_REG (0x003c) + +/* Receive Pause Frame Packet Counter */ +#define UNIMAC_MIB_GRXPF_REG (0x0040) + +/* Receive Unknown OP Code Packet Counter */ +#define UNIMAC_MIB_GRXUO_REG (0x0044) + +/* Receive Alignmenet Error Counter */ +#define UNIMAC_MIB_GRALN_REG (0x0048) + +/* Receive Frame Length Out Of Range Counter */ +#define UNIMAC_MIB_GRFLR_REG (0x004c) + +/* Receive Code Error Packet Counter */ +#define UNIMAC_MIB_GRCDE_REG (0x0050) + +/* Receive Carrier Sense Error Packet Counter */ +#define UNIMAC_MIB_GRFCR_REG (0x0054) + +/* Receive Oversize Packet Counter */ +#define UNIMAC_MIB_GROVR_REG (0x0058) + +/* Receive Jabber Counter */ +#define UNIMAC_MIB_GRJBR_REG (0x005c) + +/* Receive MTU Error Packet Counter */ +#define UNIMAC_MIB_GRMTUE_REG (0x0060) + +/* Receive Good Packet Counter */ +#define UNIMAC_MIB_GRPOK_REG (0x0064) + +/* Receive Unicast Packet Counter */ +#define UNIMAC_MIB_GRUC_REG (0x0068) + +/* Receive PPP Packet Counter */ +#define UNIMAC_MIB_GRPPP_REG (0x006c) + +/* Receive CRC Match Packet Counter */ +#define UNIMAC_MIB_GRCRC_REG (0x0070) + +/* Transmit 64B Frame Counter */ +#define UNIMAC_MIB_TR64_REG (0x0080) + +/* Transmit 65B to 127B Frame Counter */ +#define UNIMAC_MIB_TR127_REG (0x0084) + +/* Transmit 128B to 255B Frame Counter */ +#define UNIMAC_MIB_TR255_REG (0x0088) + +/* Transmit 256B to 511B Frame Counter */ +#define UNIMAC_MIB_TR511_REG (0x008c) + +/* Transmit 512B to 1023B Frame Counter */ +#define UNIMAC_MIB_TR1023_REG (0x0090) + +/* Transmit 1024B to 1518B Frame Counter */ +#define UNIMAC_MIB_TR1518_REG (0x0094) + +/* Transmit 1519B to 1522B Good VLAN Frame Counter */ +#define UNIMAC_MIB_TRMGV_REG (0x0098) + +/* Transmit 1519B to 2047B Frame Counter */ +#define UNIMAC_MIB_TR2047_REG (0x009c) + +/* Transmit 2048B to 4095B Frame Counter */ +#define UNIMAC_MIB_TR4095_REG (0x00a0) + +/* Transmit 4096B to 9216B Frame Counter */ +#define UNIMAC_MIB_TR9216_REG (0x00a4) + +/* Transmit Packet Counter */ +#define UNIMAC_MIB_GTPKT_REG (0x00a8) + +/* Transmit Multicast Packet Counter */ +#define UNIMAC_MIB_GTMCA_REG (0x00ac) + +/* Transmit Broadcast Packet Counter */ +#define UNIMAC_MIB_GTBCA_REG (0x00b0) + +/* Transmit Pause Frame Packet Counter */ +#define UNIMAC_MIB_GTXPF_REG (0x00b4) + +/* Transmit Control Frame Packet Counter */ +#define UNIMAC_MIB_GTXCF_REG (0x00b8) + +/* Transmit FCS Error Counter */ +#define UNIMAC_MIB_GTFCS_REG (0x00bc) + +/* Transmit Oversize Packet Counter */ +#define UNIMAC_MIB_GTOVR_REG (0x00c0) + +/* Transmit Deferral Packet Counter */ +#define UNIMAC_MIB_GTDRF_REG (0x00c4) + +/* Transmit Excessive Deferral Packet Counter */ +#define UNIMAC_MIB_GTEDF_REG (0x00c8) + +/* Transmit Single Collision Packet Counter */ +#define UNIMAC_MIB_GTSCL_REG (0x00cc) + +/* Transmit Multiple Collision Packet Counter */ +#define UNIMAC_MIB_GTMCL_REG (0x00d0) + +/* Transmit Late Collision Packet Counter */ +#define UNIMAC_MIB_GTLCL_REG (0x00d4) + +/* Transmit Excessive Collision Packet Counter */ +#define UNIMAC_MIB_GTXCL_REG (0x00d8) + +/* Transmit Fragments Packet Counter */ +#define UNIMAC_MIB_GTFRG_REG (0x00dc) + +/* Transmit Total Collision Counter */ +#define UNIMAC_MIB_GTNCL_REG (0x00e0) + +/* Transmit Jabber Counter */ +#define UNIMAC_MIB_GTJBR_REG (0x00e4) + +/* Transmit Byte Counter */ +#define UNIMAC_MIB_GTBYT_REG (0x00e8) + +/* Transmit Good Packet Counter */ +#define UNIMAC_MIB_GTPOK_REG (0x00ec) + +/* Transmit Unicast Packet Counter */ +#define UNIMAC_MIB_GTUC_REG (0x00f0) + +/* Receive RUNT Packet Counter */ +#define UNIMAC_MIB_RRPKT_REG (0x0100) + +/* Receive RUNT Packet And Contain A Valid FCS */ +#define UNIMAC_MIB_RRUND_REG (0x0104) + +/* Receive RUNT Packet And Contain Invalid FCS or Alignment Error */ +#define UNIMAC_MIB_RRFRG_REG (0x0108) + +/* Receive RUNT Packet Byte Counter */ +#define UNIMAC_MIB_RRBYT_REG (0x010c) + +/* MIB Control Register */ +#define UNIMAC_MIB_MIB_CNTRL_REG (0x0180) + + +/* + * MISC registers + */ + +/* UNIMAC_CFG Register */ +#define UNIMAC_MISC_CFG_REG (0x0000) +#define UNIMAC_MISC_CFG_GMII_DIRECT_SHIFT 0 +#define UNIMAC_MISC_CFG_GMII_DIRECT_MASk (1 << UNIMAC_MISC_CFG_GMII_DIRECT_SHIFT) + +/* UNIMAC_EXT_CFG1 Register */ +#define UNIMAC_MISC_EXT_CFG1_REG (0x0004) +#define UNIMAC_MISC_EXT_CFG1_MAX_PKT_SIZE_SHIFT 0 +#define UNIMAC_MISC_EXT_CFG1_MAX_PKT_SIZE_MASK (0x3fff << UNIMAC_MISC_EXT_CFG1_MAX_PKT_SIZE_SHIFT) + +/* UNIMAC_EXT_CFG2 Register */ +#define UNIMAC_MISC_EXT_CFG2_REG (0x0008) + +#endif /* !UNIMAC_REGS_H */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/wan_top.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/wan_top.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/wan_top.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/wan_top.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,1918 @@ +#ifndef WAN_TOP_H_ +#define WAN_TOP_H_ + +/* relative to core */ +#define SCRATCH_OFFSET_0 0x0 + +/* + * Register + * + * Register used for testing read and write access into wan_top block. + */ +#define WAN_TOP_SCRATCH_REG 0x0 + +/* Scratch pad. */ +#define WAN_TOP_SCRATCH_SCRATCH_SHIFT 0 +#define WAN_TOP_SCRATCH_SCRATCH_MASK 0xffffffff + + +/* + * Register + * + * Various resets to be applied within wan_top. + */ +#define WAN_TOP_RESET_REG 0x4 + +/* + * Active low PCS reset. + * Set to 1 for normal operation +*/ +#define WAN_TOP_RESET_CFG_PCS_RESET_N_MASK 0x1 + + +/* + * Register + * + * Configuration for the GPON gearbox. + */ +#define WAN_TOP_GPON_GEARBOX_0_REG 0x8 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_PTG_STATUS2_SEL_MASK 0x40000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_PTG_STATUS1_SEL_MASK 0x20000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_STATUS_SEL_MASK 0x10000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TXLBE_BIT_ORDER_MASK 0x8000000 + +/* + * This field changes the bit order of the 16-bit Rx data exiting theRx + * FIFO to GPON MAC. + * 0: + * No changes1: + * Rx data is reversed from [15: + * 0] to [0: + * 15] +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_RX_16BIT_ORDER_MASK 0x4000000 + +/* + * This field changes the bit order of the 8-bit Tx data enteringthe Tx + * FIFO. + * 0: + * No changes1: + * Tx data is reversed from [7: + * 0] to [0: + * 7] +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_8BIT_ORDER_MASK 0x2000000 + +/* + * This field changes the bit order of the 16-bit Tx data exitingthe Tx + * FIFO to ONU2G PMD. + * 0: + * Bit 0 is transmitted first1: + * Bit 19 is transmitted first +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_16BIT_ORDER_MASK 0x1000000 + +/* + * Minimum distance allowed between the Tx FIFO write and readpointers. + * The TXFIFO_DRIFTED status bit is asserted ifTX_POINTER_DISTANCE goes + * below this minimum value. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MIN_SHIFT 16 +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MIN_MASK 0x1f0000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_0_FIFO_CFG_0_ASYM_LOOPBACK_MASK 0x2000 + +/* + * Maximum distance allowed between the Tx FIFO write and readpointers. + * The TXFIFO_DRIFTED status bit is asserted ifTX_POINTER_DISTANCE goes + * above this maximum value. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MAX_SHIFT 8 +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_POINTER_DISTANCE_MAX_MASK 0x1f00 + +/* This bit enables logically inversion of every Tx bit. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_BIT_INV_MASK 0x80 + +/* + * Delay Tx FIFO write pointer by 1 location (8 Tx bits). + * The pointeris adjusted on every 0 to 1 transition in this register + * field. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_WR_PTR_DLY_MASK 0x40 + +/* + * Advance Tx FIFO write pointer by 1 location (8 Tx bits). + * Thepointer is adjusted on every 0 to 1 transition in this registerfield. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_TX_WR_PTR_ADV_MASK 0x20 + +/* if 1, the TXFIFO_COLLISION status bit resets to 0. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_CLEAR_TXFIFO_COLLISION_MASK 0x10 + +/* + * If 1, the output of Rx FIFO is looped back to the input of Tx FIFO. + * In this case, the SATA PHY Tx data rate is the same as the Rx datarate + * regardless of whether Gen2 or Gen3 is selected. +*/ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_LOOPBACK_RX_MASK 0x8 + +/* If 1, the TXFIFO_DRIFTED statsu bit resets to 0. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_0_CLEAR_TXFIFO_DRIFTED_MASK 0x4 + +/* If 1, the Tx FIFO goes into reset. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_SW_RESET_TXFIFO_RESET_MASK 0x2 + +/* If 1, The Tx Pattern Generator goes into reset. */ +#define WAN_TOP_GPON_GEARBOX_0_TOP_WAN_MISC_GPON_GEARBOX_SW_RESET_TXPG_RESET_MASK 0x1 + + +/* + * Register + * + * The GPON Gearbox has a pattern generator to be used for laser + * burstenable calibration and during SATA PHY characterization/testing. + */ +#define WAN_TOP_GPON_PATTERN_CFG1_REG 0xc + +/* 8-bit pattern to placed between Tx bursts when PG_MODE is 1. */ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_FILLER_SHIFT 24 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_FILLER_MASK 0xff000000 + +/* + * 8-bit pattern to placed after the HEADER byte in every Tx burst + * whenPG_MODE is 1. +*/ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PAYLOAD_SHIFT 16 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PAYLOAD_MASK 0xff0000 + +/* 8-bit pattern to placed at the start of every Tx burst when PG_MODEis 1. */ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_HEADER_SHIFT 8 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_HEADER_MASK 0xff00 + +/* + * Pattern generator modes: + * 0: + * Pattern generator disabled. + * GPON MAC has control of Tx outputand burst enable. + * 1: + * Generate repetitive Tx bursts. + * Each burst consists of 1 headerbyte and1 or more payload bytes. + * Filler bytes are placed between Txbursts. + * 2: + * Reserved3: + * Reserved4: + * Generate PRBS7 pattern5: + * Generate PRBS15 pattern6: + * Generate PRBS23 pattern7: + * Generate PRBS31 patternMode 0 is for GPON normal operation. + * Mode 1 is for laser burstenable calibration. +*/ +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PG_MODE_SHIFT 0 +#define WAN_TOP_GPON_PATTERN_CFG1_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG1_PG_MODE_MASK 0x7 + + +/* + * Register + * + * The GPON Gearbox has a pattern generator to be used for laser + * burstenable calibration and during SATA PHY characterization/testing. + */ +#define WAN_TOP_GPON_PATTERN_CFG2_REG 0x10 + +/* Number of filler bytes to be placed between Tx bursts when PG_MODEis 1. */ +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_GAP_SIZE_SHIFT 8 +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_GAP_SIZE_MASK 0xff00 + +/* Total length of Tx burst in bytes when PG_MODE is 1. */ +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_BURST_SIZE_SHIFT 0 +#define WAN_TOP_GPON_PATTERN_CFG2_TOP_WAN_MISC_GPON_GEARBOX_PATTERN_CFG2_BURST_SIZE_MASK 0xff + + +/* + * Register + * + * Configuration for the GPON gearbox. + */ +#define WAN_TOP_GPON_GEARBOX_2_REG 0x14 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_CONFIG_BURST_DELAY_CYC_SHIFT 24 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_CONFIG_BURST_DELAY_CYC_MASK 0xf000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_TX_VLD_DELAY_CYC_SHIFT 21 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_TX_VLD_DELAY_CYC_MASK 0xe00000 + +/* + * Initial value to be loaded into Tx FIFO write pointer whenTXFIFO_RESET + * is asserted. + * Legal values are 0 to 19. +*/ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_WR_POINTER_SHIFT 16 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_WR_POINTER_MASK 0x1f0000 + +/* + * Initial value to be loaded into Tx FIFO read pointer whenTXFIFO_REET is + * asserted. + * Legal values are 0 to 31. +*/ +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_RD_POINTER_SHIFT 8 +#define WAN_TOP_GPON_GEARBOX_2_TOP_WAN_MISC_GPON_GEARBOX_FIFO_CFG_1_TX_RD_POINTER_MASK 0x1f00 + + +/* + * Register + * + * EARLY_TXEN_CFG Register valid for (EPON & GPON mode). + */ +#define WAN_TOP_EARLY_TXEN_TXEN_REG 0x18 + +/* + * Early TXEN Enable Logic Bypass. + * 0 = NO_BYPASS +*/ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_EARLY_TXEN_BYPASS_MASK 0x4000000 + +/* + * Mac TXEN input polarity. + * 0 = ACTIVE_LOW +*/ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_INPUT_TXEN_POLARITY_MASK 0x2000000 + +/* + * Mac TXEN output polarity. + * 0 = ACTIVE_LOW +*/ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_OUTPUT_TXEN_POLARITY_MASK 0x1000000 + +/* Early TXEN Toff Time */ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_TOFF_TIME_SHIFT 16 +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_TOFF_TIME_MASK 0xff0000 + +/* Early TXEN Setup Time */ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_SETUP_TIME_SHIFT 8 +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_SETUP_TIME_MASK 0xff00 + +/* Early TXEN Hold Time */ +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_HOLD_TIME_SHIFT 0 +#define WAN_TOP_EARLY_TXEN_TXEN_TOP_WAN_MISC_EARLY_TXEN_CFG_HOLD_TIME_MASK 0xff + + +/* + * Register + * + * Register used for configuring the RESCAL. + */ +#define WAN_TOP_RESCAL_AL_CFG_REG 0x1c + +/* Connects to i_rstb. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_RSTB_MASK 0x8000 + +/* Connects to i_diag_on. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_DIAG_ON_MASK 0x4000 + +/* Connects to i_pwrdn. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_PWRDN_MASK 0x2000 + +/* Connects to i_rescal_ctrl. */ +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_CTRL_SHIFT 0 +#define WAN_TOP_RESCAL_AL_CFG_WAN_RESCAL_CTRL_MASK 0x1fff + + +/* + * Register - read-only + * + * Register used for reading RESCAL status. + */ +#define WAN_TOP_RESCAL_STATUS_0_REG 0x20 + +/* Connects to o_done. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_DONE_MASK 0x4000000 + +/* Connects to o_pon. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PON_SHIFT 22 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PON_MASK 0x3c00000 + +/* Connects to o_prev_comp_cnt. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PREV_COMP_CNT_SHIFT 18 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_PREV_COMP_CNT_MASK 0x3c0000 + +/* Connects to o_rescal_ctrl_dfs. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_CTRL_DFS_SHIFT 5 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_CTRL_DFS_MASK 0x3ffe0 + +/* Connects to o_rescal_state. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_STATE_SHIFT 2 +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_STATE_MASK 0x1c + +/* Connects to o_rescalcomp. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_COMP_MASK 0x2 + +/* Connects to o_valid. */ +#define WAN_TOP_RESCAL_STATUS_0_WAN_RESCAL_VALID_MASK 0x1 + + +/* + * Register - read-only + * + * Register used for reading RESCAL status. + */ +#define WAN_TOP_RESCAL_STATUS_1_REG 0x24 + +/* Connects to o_curr_comp_cnt. */ +#define WAN_TOP_RESCAL_STATUS_1_WAN_RESCAL_CURR_COMP_CNT_SHIFT 0 +#define WAN_TOP_RESCAL_STATUS_1_WAN_RESCAL_CURR_COMP_CNT_MASK 0x3f + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_0_REG 0x28 + +/* + * Reserved mode bus for lane. + * Mode bus for lane used by the PCS tocommunicate lane info to PMD. + * This bus should only be written towhen the lane is in reset since the + * firmware will only read thisafter coming out of reset. + * This signal will be latched to a lanebased register during core_dp_rstb. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_0_PMD_LANE_MODE_SHIFT 16 +#define WAN_TOP_MISC_0_PMD_LANE_MODE_MASK 0xffff0000 + +/* + * 0: + * All other modes 1: + * Explicit 2. + * 5G Full Rate Serdes Mode +*/ +#define WAN_TOP_MISC_0_EPON_GBOX_AE_2P5_FULL_RATE_MODE_MASK 0x1000 + +/* + * 0: + * 10b mode, 1G Operation 1: + * 20b mode, 2G Operation +*/ +#define WAN_TOP_MISC_0_EPON_GBOX_PON_RX_WIDTH_MODE_MASK 0x800 + +/* + * Strap input for selecting the port address to decode on the + * mdiotransaction. +*/ +#define WAN_TOP_MISC_0_ONU2G_PHYA_SHIFT 6 +#define WAN_TOP_MISC_0_ONU2G_PHYA_MASK 0x7c0 + +/* Load vlue in cr_xgwan_top_wan_misc_epon_tx_fifo_off. */ +#define WAN_TOP_MISC_0_EPON_TX_FIFO_OFF_LD_MASK 0x20 + +/* + * Debug bit that disables the 32-bit preamble to allow mdio frames torun + * at 2x speed. +*/ +#define WAN_TOP_MISC_0_MDIO_FAST_MODE_MASK 0x10 + +/* + * MDIO transaction indicator needs to be asserted in a configurationwhere + * an external mdio controller is trying to access the internalPMD + * registers directly. +*/ +#define WAN_TOP_MISC_0_MDIO_MODE_MASK 0x8 + +/* Not used in this chip. */ +#define WAN_TOP_MISC_0_REFOUT_EN_MASK 0x4 + +/* Not used in this chip. */ +#define WAN_TOP_MISC_0_REFIN_EN_MASK 0x2 + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_1_REG 0x2c + +/* + * Reserved mode bus for the entire core. + * Mode bus for core used bythe PCS to communicate core info to PMD . + * This bus should only bewritten to when the core is in reset since the + * firmware will onlyread this after coming out of reset. + * This signal will be latched toa core register during core_dp_rstb. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_1_PMD_CORE_1_MODE_SHIFT 16 +#define WAN_TOP_MISC_1_PMD_CORE_1_MODE_MASK 0xffff0000 + +/* + * Reserved mode bus for the entire core. + * Mode bus for core used bythe PCS to communicate core info to PMD . + * This bus should only bewritten to when the core is in reset since the + * firmware will onlyread this after coming out of reset. + * This signal will be latched toa core register during core_dp_rstb. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_1_PMD_CORE_0_MODE_SHIFT 0 +#define WAN_TOP_MISC_1_PMD_CORE_0_MODE_MASK 0xffff + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_2_REG 0x30 + +/* + * Oversample mode for rx lane. + * Asynchronous signal to the PMD. + * 0 -OSR1. + * 1 - OSR2. +*/ +#define WAN_TOP_MISC_2_PMD_RX_OSR_MODE_SHIFT 20 +#define WAN_TOP_MISC_2_PMD_RX_OSR_MODE_MASK 0xf00000 + +/* + * EEE tx mode function for lane. + * Asynchronous signal to the PMD. +*/ +#define WAN_TOP_MISC_2_PMD_TX_MODE_SHIFT 16 +#define WAN_TOP_MISC_2_PMD_TX_MODE_MASK 0x30000 + +/* + * Oversample mode for tx lane. + * Asynchronous signal to the PMD. + * 0 -OSR1. + * 1 - OSR2. +*/ +#define WAN_TOP_MISC_2_PMD_TX_OSR_MODE_SHIFT 12 +#define WAN_TOP_MISC_2_PMD_TX_OSR_MODE_MASK 0xf000 + +/* Pmd_tx_disable is asserted to squelch the transmit signal for lane. */ +#define WAN_TOP_MISC_2_PMD_TX_DISABLE_MASK 0x200 + +/* + * Lane RX power down. + * Minimum assertion time: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_RX_H_PWRDN_MASK 0x100 + +/* + * Lane TX power down. + * Minimum assertion time: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_TX_H_PWRDN_MASK 0x80 + +/* + * External Loss of signal. + * LOS = 1. + * Signal presence = 0. +*/ +#define WAN_TOP_MISC_2_PMD_EXT_LOS_MASK 0x40 + +/* + * PMD main reset, resets registers, data path for entire coreincluding all + * lanes. + * Active Low. + * Minimum assertion time: + * 25 comclkperiod. +*/ +#define WAN_TOP_MISC_2_PMD_POR_H_RSTB_MASK 0x20 + +/* + * Core reset for datapath for all lanes and corresponding PLL. + * Doesnot reset registers. + * Active Low. + * Minimum assertion time: + * 25 comclkperiod. +*/ +#define WAN_TOP_MISC_2_PMD_CORE_1_DP_H_RSTB_MASK 0x10 + +/* + * Core reset for datapath for all lanes and corresponding PLL. + * Doesnot reset registers. + * Active Low. + * Minimum assertion time: + * 25 comclkperiod. +*/ +#define WAN_TOP_MISC_2_PMD_CORE_0_DP_H_RSTB_MASK 0x8 + +/* + * Lane reset registers and data path. + * Active Low. + * Minimum assertiontime: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_H_RSTB_MASK 0x4 + +/* + * Lane datapath reset, does not reset registers. + * Active Low. + * Minimumassertion time: + * 25 comclk period. +*/ +#define WAN_TOP_MISC_2_PMD_LN_DP_H_RSTB_MASK 0x2 + +/* + * EEE rx mode function for lane. + * Asynchronous signal to the PMD +*/ +#define WAN_TOP_MISC_2_PMD_RX_MODE_MASK 0x1 + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_3_REG 0x34 + +/* TXFIFO OFF LOAD signal for EPON's gearbox. */ +#define WAN_TOP_MISC_3_EPON_TX_FIFO_OFF_SHIFT 24 +#define WAN_TOP_MISC_3_EPON_TX_FIFO_OFF_MASK 0x3f000000 + +/* + * This field selects the block that the 40-bit debug bus comesfrom. + * 0: + * GPON1: + * XPORT_0 BBH RX2: + * XPORT_0 BBH TX3: + * XPORT_1 BBH RX4: + * XPORT_1 BBH TX5: + * SERDES6: + * XLIF7: + * GPON BBH RX8: + * GPON BBH TX9: + * SAR BBH RX10: + * SAR BBH TX11: + * XPORT12: + * SAR +*/ +#define WAN_TOP_MISC_3_WAN_DEBUG_SEL_SHIFT 12 +#define WAN_TOP_MISC_3_WAN_DEBUG_SEL_MASK 0x1f000 + +/* Allows the bypassing of the NTR double sync and pulse generator. */ +#define WAN_TOP_MISC_3_CFG_NTR_PERIPH_PULSE_BYPASS_MASK 0x800 + +/* Allows the bypassing of the NTR double sync and pulse generator. */ +#define WAN_TOP_MISC_3_CFG_NTR_GPIO_PULSE_BYPASS_MASK 0x400 + +/* + * Selects the source of NTR pulse : + * 0 - programmable clock; 1 - GPON;2 - GPIO, 3 - NCO. +*/ +#define WAN_TOP_MISC_3_CFG_NTR_SRC_SHIFT 8 +#define WAN_TOP_MISC_3_CFG_NTR_SRC_MASK 0x300 + +/* + * 0: + * Output enable for laser is disabled. + * 1: + * Output enable for laseris enabled. +*/ +#define WAN_TOP_MISC_3_LASER_OE_MASK 0x80 + +/* + * Selects between various speed AE modes and GPON mode 0: + * 0: 100M AE + * 1: 1G AE + * 2: 5G AE + * 3: 10G AE + * 4: GPON + * 5-7: Reserved +*/ +#define WAN_TOP_MISC_3_WAN_IFSELECT_SHIFT 4 +#define WAN_TOP_MISC_3_WAN_IFSELECT_MASK 0x70 + +/* + * Bit 0 selects the speed, and bit 1 selects the technology. + * 2: + * GPON;0,1,3 : + * Disable laser. +*/ +#define WAN_TOP_MISC_3_LASER_MODE_SHIFT 1 +#define WAN_TOP_MISC_3_LASER_MODE_MASK 0xe + +/* + * 0: + * Normal operation. + * 1: + * Invert laser enable. +*/ +#define WAN_TOP_MISC_3_LASER_INVERT_MASK 0x80000000 + +/* REB going to WAN memories. */ +#define WAN_TOP_MISC_3_MEM_REB_MASK 0x1 + + +/* + * Register + * + * Register used for wan_top configuration. + */ +#define WAN_TOP_MISC_4_REG 0xf4 + +/* Specifies the width of NTR pulse, in unit of 4 ns. */ +#define WAN_TOP_MISC_4_CFG_NTR_PULSE_WIDTH_SHIFT 16 +#define WAN_TOP_MISC_4_CFG_NTR_PULSE_WIDTH_MASK 0xffff0000 + + +/* + * Register + * + * Register used for low configuration of PLL clocks. + */ +#define WAN_TOP_SERDES_PLL_CTL_REG 0x38 + +/* + * 0 - select pll1_lcref. + * 1 - select pll0_lcref. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_LCREF_SEL_MASK 0x400 + +/* + * Enables SERDES to drive the pll1_refout pin. + * 0 - output is hiZ. + * 1- output is pad_pll1_refclk. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_REFOUT_EN_MASK 0x200 + +/* + * Reference select. + * 0 - select pad_pll1_refclkp/n. + * 1 - selectpll1_lcrefp/n. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL1_REFIN_EN_MASK 0x100 + +/* + * 0 - select pll0_lcref. + * 1 - select pll1_lcref. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_LCREF_SEL_MASK 0x4 + +/* + * Enables SERDES to drive the pll0_refout pin. + * 0 - output is hiZ. + * 1- output is pad_pll0_refclk. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_REFOUT_EN_MASK 0x2 + +/* + * Reference select. + * 0 - select pad_pll0_refclkp/n. + * 1 - selectpll0_lcrefp/n. +*/ +#define WAN_TOP_SERDES_PLL_CTL_CFG_PLL0_REFIN_EN_MASK 0x1 + + +/* + * Register - read-only + * + * Register used for temperature read. + */ +#define WAN_TOP_SERDES_TEMP_CTL_REG 0x3c + +/* + * 10-bit temperature data. + * Please refer to TMON documentation for howto convert this value to a + * useful number. +*/ +#define WAN_TOP_SERDES_TEMP_CTL_WAN_TEMPERATURE_DATA_SHIFT 0 +#define WAN_TOP_SERDES_TEMP_CTL_WAN_TEMPERATURE_DATA_MASK 0x3ff + + +/* + * Register + * + * Register used for PRAM control. + */ +#define WAN_TOP_SERDES_PRAM_CTL_REG 0x40 + +/* + * Perform pRAM operation. + * This field is only valid for the B0 orbeyond. + * Software sets and hardware clears this bit. + * Do not writeto this register if this bit is set. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_GO_MASK 0x80000000 + +/* Program RAM write strobe. */ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_WE_MASK 0x4000000 + +/* + * Program RAM chip select. + * This field is only valid for the A0 versionof the chip. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_CS_MASK 0x2000000 + +/* + * Ability to support parallel bus interface to access program RAM. + * 0- not supported. + * 1 - supported. + * This field is only valid for the A0version of the chip. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_ABILITY_MASK 0x1000000 + +/* + * Deprecated. + * Use the data field in SERDES_PRAM_CTL_2/3. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_DATAIN_SHIFT 16 +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_DATAIN_MASK 0xff0000 + +/* Program RAM address. */ +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_ADDR_SHIFT 0 +#define WAN_TOP_SERDES_PRAM_CTL_CFG_PRAM_ADDR_MASK 0xffff + + +/* + * Register + * + * Register used for PRAM control. + */ +#define WAN_TOP_SERDES_PRAM_CTL_2_REG 0x44 + +/* + * Bits [31: + * 0] of the 64-bit pRAM write data interface. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_2_CFG_PRAM_DATAIN_0_SHIFT 0 +#define WAN_TOP_SERDES_PRAM_CTL_2_CFG_PRAM_DATAIN_0_MASK 0xffffffff + + +/* + * Register + * + * Register used for PRAM control. + */ +#define WAN_TOP_SERDES_PRAM_CTL_3_REG 0x48 + +/* + * Bits [63: + * 32] of the 64-bit pRAM write data interface. +*/ +#define WAN_TOP_SERDES_PRAM_CTL_3_CFG_PRAM_DATAIN_1_SHIFT 0 +#define WAN_TOP_SERDES_PRAM_CTL_3_CFG_PRAM_DATAIN_1_MASK 0xffffffff + + +/* + * Register + * + * Register used for low priority configuration. + */ +#define WAN_TOP_PMI_LP_0_REG 0x4c + +/* + * Transaction enable control from master. + * This is treated asasynchronous to the PCS. + * The bus master should wait forpcs_pmi_lp_ack to be deasserted before + * pcs_pmi_lp_en is asserted. + * The bus master should then wait for pcs_pmi_lp_ack to be + * assertedindicating that the transaction is complete before it + * deassertspcs_pmi_lp_en. +*/ +#define WAN_TOP_PMI_LP_0_PCS_EN_MASK 0x4 + +/* + * Transaction enable control from master. + * This is treated asasynchronous to the rmic. + * The bus master should wait for pmi_lp_ackto be deasserted before + * pmi_lp_en is asserted. + * The bus master shouldthen wait for pmi_lp_ack to be asserted indicating + * that thetransaction is complete before it deasserts pmi_lp_en. +*/ +#define WAN_TOP_PMI_LP_0_MISC_EN_MASK 0x2 + +/* + * Read/Write control from master. + * 1-write, 0-read. + * This should beasserted before or with the pmi_lp_en and should be driven + * until thenext transaction. +*/ +#define WAN_TOP_PMI_LP_0_WRITE_MASK 0x1 + + +/* + * Register + * + * Register used for low priority configuration. + */ +#define WAN_TOP_PMI_LP_1_REG 0x50 + +/* + * 32-bit address driven by master for read or write transaction. + * Thisshould be asserted before or with the pmi_lp_en and should be + * drivenuntil the next transaction +*/ +#define WAN_TOP_PMI_LP_1_PMI_LP_ADDR_SHIFT 0 +#define WAN_TOP_PMI_LP_1_PMI_LP_ADDR_MASK 0xffffffff + + +/* + * Register + * + * Register used for low priority configuration. + */ +#define WAN_TOP_PMI_LP_2_REG 0x54 + +/* + * 16-bit data bus driven by master for write transaction. + * This shouldbe driven before or with the pmi_lp_en and should be driven + * untilthe next transaction. +*/ +#define WAN_TOP_PMI_LP_2_PMI_LP_WRDATA_SHIFT 16 +#define WAN_TOP_PMI_LP_2_PMI_LP_WRDATA_MASK 0xffff0000 + +/* + * 16-bit mask bus driven by master for write transaction. + * 0 means nomask (wrdata bit is written to register), 1 means mask (wrdata + * bitis ignored). + * This bus has no affect during a read operation. + * Thisshould be asserted before or with the pmi_lp_en and should be + * drivenuntil the next transaction. +*/ +#define WAN_TOP_PMI_LP_2_PMI_LP_MASKDATA_SHIFT 0 +#define WAN_TOP_PMI_LP_2_PMI_LP_MASKDATA_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for low priority read back. + */ +#define WAN_TOP_PMI_LP_3_REG 0x58 + +/* + * Error response from RMIC slave indicating an address error whichmeans + * that either the block address does not exist or that the deviddid not + * match the strap value. + * The ack signal indicates that thetransaction is complete and the error + * signal indicates that therewas an address error with this transaction. + * This signal is assertedalong with the ack signal and should be treated + * an asynchronoussignal the same way as the ack signal. +*/ +#define WAN_TOP_PMI_LP_3_PMI_LP_ERR_MASK 0x20000 + +/* + * Ack response back from the RMIC slave indicating that the write orread + * transaction is complete. + * This signal is driven in the registersblocks clock domain and should be + * treated as an asynchronous inputby the master. +*/ +#define WAN_TOP_PMI_LP_3_PMI_LP_ACK_MASK 0x10000 + +/* + * 16-bit data bus driven RMIC slave during a read transaction. + * Thisdata is latched in the register clock domain but this data + * isguaranteed to be stable by the end of the read transaction so thisdoes + * not have to metastabilized. +*/ +#define WAN_TOP_PMI_LP_3_PMI_LP_RDDATA_SHIFT 0 +#define WAN_TOP_PMI_LP_3_PMI_LP_RDDATA_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for PCS low priority read back. + */ +#define WAN_TOP_PMI_LP_4_REG 0x5c + +/* + * Error response from PCS slave indicating an address error whichmeans + * that either the block address does not exist or that the deviddid not + * match the strap value. + * The ack signal indicates that thetransaction is complete and the error + * signal indicates that therewas an address error with this transaction. + * This signal is assertedalong with the ack signal and should be treated + * an asynchronoussignal the same way as the ack signal. +*/ +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_ERR_MASK 0x20000 + +/* + * Ack response back from the PCS slave indicating that the write orread + * transaction is complete. + * This signal is driven in the registersblocks clock domain and should be + * treated as an asynchronous inputby the master. +*/ +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_ACK_MASK 0x10000 + +/* + * 16-bit data bus driven PCS slave during a read transaction. + * Thisdata is latched in the register clock domain but this data + * isguaranteed to be stable by the end of the read transaction so thisdoes + * not have to metastabilized. +*/ +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_RDDATA_SHIFT 0 +#define WAN_TOP_PMI_LP_4_PCS_PMI_LP_RDDATA_MASK 0xffff + + +/* + * Register + * + * Register used for 48-bit timestamp Time Of Day (TOD) configuration. + */ +#define WAN_TOP_TOD_CONFIG_0_REG 0x60 + +/* + * Indicates TOD read is in progress. + * Deassertive value indicatesvalid values at WAN_TOD_TS48/WAN_TOD_TS64 + * registers. +*/ +#define WAN_TOP_TOD_CONFIG_0_TOD_READ_BUSY_MASK 0x400000 + +/* + * 0: + * New mode. + * Transfer TS48 using FIFO. + * 1: + * Legacy mode. + * Transferupper TS48 bits between clock domains. +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_PRE_SYNC_FIFO_DISABLE_MASK 0x200000 + +/* Number of clock ticks between consecutive writes to the TS48 FIFO. */ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_PRE_SYNC_FIFO_LOAD_RATE_SHIFT 16 +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_PRE_SYNC_FIFO_LOAD_RATE_MASK 0x1f0000 + +/* + * Allows 1PPS pulse to load cfg_tod_1pps_ns_offset into nanosecondcounter. + * If not set, the 1PPS pulse will have no effect on theTS48. +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TOD_PPS_CLEAR_MASK 0x8000 + +/* + * Arm the reading of the TS48/TS64 timestamps. + * Values are valid atthe deassertion of tod_read_busy +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TOD_READ_MASK 0x4000 + +/* + * The TS48 offset value. + * In legacy, GPON mode (cfg_ts48_pre_sync_fifo_disable = 1), therising + * edge ofTS48/TS64's bit[9] loads cfg_ts48_offset[8: + * 0] into the lower 9 bitsof the synchronized TS48/TS64. + * In the new mode, the timestamp is transfer to the 250 MHz clockdomain + * via an asynchronousFIFO. + * The offset is added to the output of the FIFO. + * Thecfg_ts48_offset[8] is the signbit, allowing +/- adjustment to the + * timestamp value. + * It is signextended to make theoffset 48-bits. + * In AE mode, the offset is added to the current TS48 value andloading it + * back into AE TS48. + * Loading is accomplished by setting the cfg_tod_load_ts48_offset bit. + * The sign extension ofcfg_ts48_offset[8] also applies. +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_OFFSET_SHIFT 4 +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_OFFSET_MASK 0x3ff0 + +/* + * This field selects the MAC that the timestamp comes from. + * 2: + * GPON4: + * Active Ethernet0,1,3,5,6,7: + * Reserved +*/ +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_MAC_SELECT_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_0_CFG_TS48_MAC_SELECT_MASK 0x7 + + +/* + * Register + * + * Register used for 48-bit timestamp Time Of Day (TOD) configuration. + */ +#define WAN_TOP_TOD_CONFIG_1_REG 0x64 + +/* + * The rising edge will load the cfg_ts48_offset into AE TS48, subjectto a + * lockout window of 1us before and after rollover. +*/ +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_LOAD_TS48_OFFSET_MASK 0x100000 + +/* + * The rising edge will be latched, and cfg_tod_seconds will be loadedinto + * AE TS48 on the next 1PPS pulse or when the next second rollsover. +*/ +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_LOAD_MASK 0x80000 + +/* Number of seconds to be loaded into AE TS48. */ +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_SECONDS_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_1_CFG_TOD_SECONDS_MASK 0x7ffff + + +/* + * Register + * + * Register used for 16-bit timestamp configuration. + */ +#define WAN_TOP_TOD_CONFIG_2_REG 0x68 + +/* + * The TS48 offset value for TX clock timestamp. + * In legacy mode (cfg_ts48_pre_sync_fifo_disable = 1), the rising edgeof + * cfg_ts48_offset[9]loads the lower 9 bits into the 16-bits timestamp. + * In the new mode,the timestamp istransfer to the 250 MHz clock domain via + * an asynchronous FIFO. + * Theoffset is added to theoutput of the FIFO. + * The cfg_ts48_offset[8] is the sign bit,allowing +/- adjustment tothe + * timestamp value. + * It is sign extended to make the offset 48-bits. +*/ +#define WAN_TOP_TOD_CONFIG_2_CFG_TX_OFFSET_SHIFT 16 +#define WAN_TOP_TOD_CONFIG_2_CFG_TX_OFFSET_MASK 0x3ff0000 + +/* + * The TS48 offset value for RX clock timestamp. + * In legacy mode (cfg_ts48_pre_sync_fifo_disable = 1), the rising edgeof + * cfg_ts48_offset[9]loads the lower 9 bits into the 16-bits timestamp. + * In the new mode,the timestamp istransfer to the 250 MHz clock domain via + * an asynchronous FIFO. + * Theoffset is added to theoutput of the FIFO. + * The cfg_ts48_offset[8] is the sign bit,allowing +/- adjustment tothe + * timestamp value. + * It is sign extended to make the offset 48-bits. +*/ +#define WAN_TOP_TOD_CONFIG_2_CFG_RX_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_2_CFG_RX_OFFSET_MASK 0x3ff + + +/* + * Register + * + * Register used for 16-bit timestamp configuration. + */ +#define WAN_TOP_TOD_CONFIG_3_REG 0x6c + +/* + * The TS48 offset value for RX clock timestamp. + * In legacy mode (cfg_ts48_pre_sync_fifo_disable = 1), the rising edgeof + * cfg_ts48_offset[9]loads the lower 9 bits into the 16-bits timestamp. + * In the new mode,the timestamp istransfer to the 250 MHz clock domain via + * an asynchronous FIFO. + * Theoffset is added to theoutput of the FIFO. + * The cfg_ts48_offset[8] is the sign bit,allowing +/- adjustment tothe + * timestamp value. + * It is sign extended to make the offset 48-bits. +*/ +#define WAN_TOP_TOD_CONFIG_3_CFG_REF_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_3_CFG_REF_OFFSET_MASK 0x3ff + + +/* + * Register + * + * Offset for 1pps loading. + */ +#define WAN_TOP_TOD_CONFIG_4_REG 0x70 + +/* + * Value to be loaded into nanosecond counter by 1PPS pulse, + * providedcfg_tod_pps_clear is set. +*/ +#define WAN_TOP_TOD_CONFIG_4_CFG_TOD_1PPS_NS_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_4_CFG_TOD_1PPS_NS_OFFSET_MASK 0x3fffffff + + +/* + * Register + * + * Debug register, used for loading TOD nanosecond counte for + * rollovertesting. + */ +#define WAN_TOP_TOD_CONFIG_5_REG 0x74 + +/* + * Rising edge immediately load cfg_tod_ns_offset into nanosecondcounter. + * This is mainly utilized for debugging. +*/ +#define WAN_TOP_TOD_CONFIG_5_CFG_TOD_LOAD_NS_OFFSET_MASK 0x40000000 + +/* + * Value to be loaded into nanosecond counter. + * The rollover value is at0x3B9ACA00. +*/ +#define WAN_TOP_TOD_CONFIG_5_CFG_TOD_NS_OFFSET_SHIFT 0 +#define WAN_TOP_TOD_CONFIG_5_CFG_TOD_NS_OFFSET_MASK 0x3fffffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS48_MSB_REG 0x78 + +/* Upper 16-bits of TS48. */ +#define WAN_TOP_TOD_TS48_MSB_TS48_WAN_READ_MSB_SHIFT 0 +#define WAN_TOP_TOD_TS48_MSB_TS48_WAN_READ_MSB_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for 48-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS48_LSB_REG 0x7c + +/* Lower 32-bits of TS48. */ +#define WAN_TOP_TOD_TS48_LSB_TS48_WAN_READ_LSB_SHIFT 0 +#define WAN_TOP_TOD_TS48_LSB_TS48_WAN_READ_LSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 64-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS64_MSB_REG 0x80 + +/* + * Upper value of TS64 : + * AE - second = ts64_wan_read_msb[18: + * 0]GPON - second[33: + * 2] = ts64_wan_read_msb[31: + * 0] +*/ +#define WAN_TOP_TOD_TS64_MSB_TS64_WAN_READ_MSB_SHIFT 0 +#define WAN_TOP_TOD_TS64_MSB_TS64_WAN_READ_MSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 64-bit timestamp Time Of Day (TOD) read back. + */ +#define WAN_TOP_TOD_TS64_LSB_REG 0x84 + +/* + * Lower value of TS64 : + * AE - nanosecond = ts64_wan_read_lsb[31: + * 0]GPON - second[1: + * 0] = ts64_wan_read_lsb[31: + * 30]; nanosecond =ts64_wan_read_lsb[29: + * 0]; +*/ +#define WAN_TOP_TOD_TS64_LSB_TS64_WAN_READ_LSB_SHIFT 0 +#define WAN_TOP_TOD_TS64_LSB_TS64_WAN_READ_LSB_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used for 16-bit timestamp read back. + */ +#define WAN_TOP_TOD_STATUS_0_REG 0x88 + +/* REF clock timestamp. */ +#define WAN_TOP_TOD_STATUS_0_TS16_REF_SYNCE_READ_SHIFT 0 +#define WAN_TOP_TOD_STATUS_0_TS16_REF_SYNCE_READ_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for 16-bit timestamp read back. + */ +#define WAN_TOP_TOD_STATUS_1_REG 0x8c + +/* TX MAC clock timestamp. */ +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_TX_READ_SHIFT 16 +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_TX_READ_MASK 0xffff0000 + +/* RX MAC clock timestamp. */ +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_RX_READ_SHIFT 0 +#define WAN_TOP_TOD_STATUS_1_TS16_MAC_RX_READ_MASK 0xffff + + +/* + * Register - read-only + * + * Register used for various WAN status bits. + */ +#define WAN_TOP_SERDES_STATUS_REG 0x90 + +/* Assertion of this signal indicates that the pll has achieved lock. */ +#define WAN_TOP_SERDES_STATUS_PMD_PLL1_LOCK_MASK 0x400 + +/* + * If set, the SERDES is attempting to enable the laser. + * The actualstate of the laser also depends on the laser output enable. +*/ +#define WAN_TOP_SERDES_STATUS_O_LASER_BURST_EN_MASK 0x200 + +/* + * Error response from RMIC slave indicating an address error whichmeans + * that either the block address does not exist or that the deviddid not + * match the strap value. + * The ack signal indicates that thetransaction is complete and the error + * signal indicates that therewas an address error with this transaction. + * This signal is assertedalong with the ack signal and should be treated + * an asynchronoussignal the same way as the ack signal. +*/ +#define WAN_TOP_SERDES_STATUS_PMI_LP_ERROR_MASK 0x100 + +/* + * Ack response back from the RMIC slave indicating that the write orread + * transaction is complete. + * This signal is driven in the registersblocks clock domain and should be + * treated as an asynchronous inputby the master. +*/ +#define WAN_TOP_SERDES_STATUS_PMI_LP_ACKNOWLEDGE_MASK 0x80 + +/* + * Signal detect status from the analog. + * This signal is not related toany interface clock or data validity. +*/ +#define WAN_TOP_SERDES_STATUS_PMD_SIGNAL_DETECT_0_MASK 0x40 + +/* EEE energy detect. */ +#define WAN_TOP_SERDES_STATUS_PMD_ENERGY_DETECT_0_MASK 0x20 + +/* + * Receive PMD lock. + * WHen this signal is low, the receiver isacquiring lock. + * During this period, the phase of the receive clockand alignment of data + * are not reliable. +*/ +#define WAN_TOP_SERDES_STATUS_PMD_RX_LOCK_0_MASK 0x10 + +/* Transmit clock valid. */ +#define WAN_TOP_SERDES_STATUS_PMD_TX_CLK_VLD_MASK 0x8 + +/* Receive clock valid. */ +#define WAN_TOP_SERDES_STATUS_PMD_RX_CLK_VLD_0_MASK 0x4 + +/* Assertion of this signal indicates that the pll has not achievedlock. */ +#define WAN_TOP_SERDES_STATUS_PMD_RX_LOCK_0_INVERT_MASK 0x2 + +/* Assertion of this signal indicates that the pll has achieved lock. */ +#define WAN_TOP_SERDES_STATUS_PMD_PLL0_LOCK_MASK 0x1 + + +/* + * Register + * + * Interrupts. + */ +#define WAN_TOP_INT_STATUS_REG 0x98 + +/* + * Indicates the sampling of clock counter, as specified bycfg_pll_smpl_prd + * sampling period. +*/ +#define WAN_TOP_INT_STATUS_CLK_SAMPLE_INT_MASK 0x1 + + +/* + * Register + * + * Interrupt masks. + */ +#define WAN_TOP_INT_MASK_REG 0x9c + +/* Interrupt mask, active low. */ +#define WAN_TOP_INT_MASK_MSK_CLK_SAMPLE_INT_MASK 0x1 + + +/* + * Register + * + * Clock dejittering control register. + */ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_REG 0xa0 + +/* + * Specifies the sampling period of the sampling counters, running inthe + * following domains : + * PON_SERDES : + * 10G - 515. + * 625 MHz; 2. + * 5G - 312. + * 5 MHz; 1G - 125 MHz;100FX - 25 MHz; GPON - 155. + * 5 MHz. + * LAN_SERDES : + * 156. + * 25 MHzSGPHY : + * 25 MHzDSL : + * 35. + * 328 MHzThe sampling counter should be set around 100 ms. + * The unit is ineach clock domain's period. + * Hence, sampling period = X value/frequency. +*/ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_CFG_PLL_SMPL_PRD_SHIFT 0 +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_0_CFG_PLL_SMPL_PRD_MASK 0x3ffffff + + +/* + * Register + * + * Clock dejittering control register. + */ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_REG 0xa4 + +/* Enable PBI write to SyncE_PLL integer/fractional dividers. */ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_CFG_EN_PBI_WR_2_SYNCE_PLL_MASK 0x10 + +/* + * Specifies the source of the sample pulse generator : + * 0 - PON_SERDES;1 - LAN_SERDES; 2 - SGPHY; 3 - DSL; 4 - NTR. + * This samples thecounter running in SyncE_PLL's 250 MHz clock domain. +*/ +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_CFG_CLK_SMPL_SRC_SHIFT 0 +#define WAN_TOP_CLK_DEJITTER_SAMPLING_CTL_1_CFG_CLK_SMPL_SRC_MASK 0x7 + + +/* + * Register - read-only + * + * Clock counter sample register. + */ +#define WAN_TOP_CLK_SAMPLE_COUNTER_REG 0xa8 + +/* + * Sample clock counter value of SyncE_PLL's dejittering counter. + * Value should be read uponreceiving interrupt clk_sample_int. + * Difference in time is obtainedby subtracting currentvalue from previous. + * The value will be different for the differentsampling sources. +*/ +#define WAN_TOP_CLK_SAMPLE_COUNTER_PBI_CLK_CNT_SMPL_SHIFT 0 +#define WAN_TOP_CLK_SAMPLE_COUNTER_PBI_CLK_CNT_SMPL_MASK 0xffffffff + + +/* + * Register + * + * Specifies the SyncE_PLL integer/fractional dividers, applicable + * whencfg_en_pbi_wr_2_syncE_pll is set. + */ +#define WAN_TOP_SYNCE_PLL_CONFIG_REG 0xac + +/* Integer divider. */ +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_INT_SHIFT 24 +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_INT_MASK 0xff000000 + +/* Fractional divider. */ +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_FRAC_SHIFT 0 +#define WAN_TOP_SYNCE_PLL_CONFIG_CFG_SYNCE_PLL_NDIV_FRAC_MASK 0xffffff + + +/* + * Register + * + * Register used to control the oversample mode of the SERDES gearboxes. + */ +#define WAN_TOP_OSR_CONTROL_REG 0xb4 + +/* TBD */ +#define WAN_TOP_OSR_TXLBE_SER_ORDER_MASK 0x80 + +/* TBD */ +#define WAN_TOP_OSR_TXLBE_SER_INIT_VAL_SHIFT 4 +#define WAN_TOP_OSR_TXLBE_SER_INIT_VAL_MASK 0x70 + +/* TBD */ +#define WAN_TOP_OSR_TXLBE_SER_EN_MASK 0x8 + +/* + * 0: + * New oversample mode. + * 1: + * Legacy mode. +*/ +#define WAN_TOP_OSR_TXFIFO_RD_LEGACY_MODE_MASK 0x4 + +/* + * 0: + * Select div2 clock. + * 1: + * Select div4 clock. + * 2: + * Select legacy modeclocking. + * 3: + * Reserved. +*/ +#define WAN_TOP_OSR_CFG_GPON_RX_CLK_SHIFT 0 +#define WAN_TOP_OSR_CFG_GPON_RX_CLK_MASK 0x3 + + +/* + * Register - read-only + * + * Register used for various WAN status bits. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_REG 0x94 + +/* + * Status indication based on status_sel signals. + * Ifgpon_gearbox_fifo_status_sel is high, this status will + * begpon_gearbox_fifo_status. + * If gpon_gearbox_ptg_status1_sel is high,this status will be + * gpon_gearbox_ptg_status1. + * Ifgpon_gearbox_ptg_status2_sel is high, this status will + * begpon_gearbox_ptg_status2. +*/ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_CR_RD_DATA_CLX_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_STATUS_CR_RD_DATA_CLX_MASK 0xffffffff + + +/* + * Register + * + * Register used to control the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_REG 0xb0 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_SIG_PRBS_STATUS_CLR_MASK 0x2000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_INV_MASK 0x1000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_OOL_CNT_SHIFT 19 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_OOL_CNT_MASK 0xf80000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_LOCK_CNT_SHIFT 14 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_LOCK_CNT_MASK 0x7c000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_ERR_CNT_BURST_MODE_MASK 0x2000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_MODE_SEL_SHIFT 10 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_MODE_SEL_MASK 0x1c00 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMEOUT_SHIFT 2 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMEOUT_MASK 0x7c + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMER_MODE_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_0_GPON_GEARBOX_RG_PRBS_CHK_CTRL_0_EN_TIMER_MODE_MASK 0x3 + + +/* + * Register + * + * Register used to control the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_REG 0xb8 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_EN_MASK 0x80000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_MODE_SHIFT 29 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_MODE_MASK 0x60000000 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_TIMER_VAL_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_CONTROL_1_GPON_GEARBOX_RG_PRBS_CHK_CTRL_1_TIMER_VAL_MASK 0xfffff + + +/* + * Register - read-only + * + * Register used to monitor the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_REG 0xbc + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_GPON_GEARBOX_PRBS_STAT_0_VECTOR_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_0_GPON_GEARBOX_PRBS_STAT_0_VECTOR_MASK 0xffffffff + + +/* + * Register - read-only + * + * Register used to monitor the GPON gearbox PRBS checker. + */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_REG 0xc0 + +/* TBD */ +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_GPON_GEARBOX_PRBS_STAT_1_VECTOR_SHIFT 0 +#define WAN_TOP_GPON_GEARBOX_STATUS_GEARBOX_PRBS_STATUS_1_GPON_GEARBOX_PRBS_STAT_1_VECTOR_MASK 0x3 + + +/* + * Register + * + * Register used to control AE Gearbox + */ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_REG 0xc4 + +/* + * Set to 1 then 0 to load initial offset value determined + * bycr_wan_top_ae_gearbox_tx_fifo_offset reg +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_TX_FIFO_OFFSET_SHIFT 4 +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_TX_FIFO_OFFSET_MASK 0x3f0 + +/* + * Set to 1 then 0 to load initial offset value determined + * bycr_wan_top_ae_gearbox_tx_fifo_offset reg +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_TX_FIFO_OFFSET_LD_MASK 0x4 + +/* + * 0 = compatible with sub rate serdes mode1 = compatible with full rate + * serdes mode. + * 100FX - sub rate only. + * 1G - sub/full rate2. + * 5G - sub/full rate10G - full rate only. +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_FULL_RATE_MODE_MASK 0x2 + +/* + * 0 = 10b mode1 = 20b mode100FX - 10b mode1G - 10b mode2. + * 5G - 10b mode10G - 20b mode +*/ +#define WAN_TOP_AE_GEARBOX_CONTROL_0_CR_WIDTH_MODE_MASK 0x1 + + +/* + * Register + * + * Provides the divider for the voltage regulator sync output. + */ +#define WAN_TOP_VOLTAGE_REGULATOR_DIVIDER_IDER_REG 0xc8 + +/* Allows the bypassing of the N divider. */ +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_CLK_BYPASS_MASK 0x200 + +/* + * Specifies the clock source of the voltage regulator sync output : + * 1- VDSL PHY; 0 - 50 MHz XTAL clock. +*/ +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_CLK_SRC_MASK 0x100 + +/* + * N divider value of voltage regulator sync output. + * Assertive 1 valuewill be INT((N/2); and assertive 0, N - INT(N/2). +*/ +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_DIV_SHIFT 0 +#define WAN_TOP_VOLTAGEULATOR_DIVIDER_IDER_REG_CFG_VREG_DIV_MASK 0xff + + +/* + * Register + * + * Provides the configuration for clock syncing. + */ +#define WAN_TOP_CLOCK_SYNC_CONFIG_REG 0xcc + +/* + * Output enable for 1PPS output to GPIO, applicable only + * ifcfg_gpio_1pps_src is cleared. +*/ +#define WAN_TOP_CLOCK_SYNC_CONFIG_CFG_GPIO_1PPS_OEB_MASK 0x4 + +/* + * Selects the source of 1PPS output to GPIO : + * 0 - NCO; 1 - Switch. +*/ +#define WAN_TOP_CLOCK_SYNC_CONFIG_CFG_GPIO_1PPS_SRC_MASK 0x2 + +/* + * Selects the source of sync pulse output to switch : + * 0 - 1PPS; 1 -recovered PHY/SerDes clock. +*/ +#define WAN_TOP_CLOCK_SYNC_CONFIG_CFG_SWITCH_SYNCIN_SRC_MASK 0x1 + + +/* + * Register + * + * Provides the configuration for AE PCS IEEE device ID register. + */ +#define WAN_TOP_AEPCS_IEEE_REGID_REG 0xd0 + +/* The AE PCS IEEE device ID. */ +#define WAN_TOP_AEPCS_IEEEID_REG_CFG_AEPCS_IEEE_REGID_SHIFT 0 +#define WAN_TOP_AEPCS_IEEEID_REG_CFG_AEPCS_IEEE_REGID_MASK 0xffffffff + + +/* + * Register + * + * Register used to force the laser burst enable (LBE) and LBE outputenable + * signals. + */ +#define WAN_TOP_FORCE_LBE_CONTROL_REG 0xd4 + +/* + * This field is only used when cfg_force_lbe_oe is set. + * This signalis then inverted prior to connecting to the OEB pin. + * 0: + * LBE outputenable is set to 0. + * 1: + * LBE output enable is set to 1. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_OE_VALUE_MASK 0x8 + +/* + * 0: + * The MAC and cr_xgwan_top_wan_misc_wan_cfg_laser_oe control theLBE output + * enable signal. + * 1: + * The LBE output enable signal is forcedto cfg_force_lbe_oe_value. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_OE_MASK 0x4 + +/* + * This field is only used when cfg_force_lbe is set. + * 0: + * LBE is set to0. + * 1: + * LBE is set to 1. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_VALUE_MASK 0x2 + +/* + * 0: + * The MAC controls the LBE signal. + * 1: + * The LBE signal is forced tocfg_force_lbe_value. +*/ +#define WAN_TOP_FORCE_LBE_CONTROL_MASK 0x1 + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_REG 0xd8 + +/* Value for RX output RIFO read pointer. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFIFORDPTR_SHIFT 24 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFIFORDPTR_MASK 0xf000000 + +/* Disable pointer auto-load going into lock for output FIFO. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXPTRAUTOLDDIS_MASK 0x800000 + +/* Number of bad KChar to go out of lock. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXBADK_SHIFT 20 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXBADK_MASK 0x700000 + +/* + * Use only K28. + * 5 for framing. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRMK28ONLY_MASK 0x80000 + +/* Number of good KChar in a row for lock. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXGOODK_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMAXGOODK_MASK 0x70000 + +/* Force 10b framer to go to HUNT state on rising edge. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCHUNT_MASK 0x8000 + +/* Bitwise flip 32b output data. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXOUTDATAFLIP_MASK 0x4000 + +/* Force mux select to value in cfNGponGboxRxFrcMuxVal. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCMUXSEL_MASK 0x2000 + +/* + * Value that will be forced to mux select when cfNGponGboxRxFrcMuxSelis + * asserted. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCMUXVAL_SHIFT 8 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFRCMUXVAL_MASK 0x1f00 + +/* Bitwise flip RX 20b gearbox data. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRX20BDATAFLIP_MASK 0x80 + +/* Bitwise flip RX 16b data from SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXSERDATAFLIP_MASK 0x40 + +/* Bitwise invert RX 16b data from SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXSERDATAINV_MASK 0x20 + +/* + * Load value for FIFO read pointer. + * Write pointer will be loaded to0. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXFIFOPTRLD_MASK 0x10 + +/* When set, synchronization will be held indefinitely. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXSWSYNCHOLD_MASK 0x8 + +/* + * 0. + * 8B/10B decoder mode operating at 777 MHz. + * 1. + * Pass through modeoperating at 622 MHz. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXMODE_MASK 0x4 + +/* Synchronous enable for RX gearbox. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRXEN_MASK 0x2 + +/* Asynchronous, active-low, software reset for gearbox. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_0_CFNGPONGBOXRSTN_MASK 0x1 + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_1_REG 0xdc + +/* Max counter for 125 us timer. */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_1_CFNGPONGBOXRXMAXTIMERCNT_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_1_CFNGPONGBOXRXMAXTIMERCNT_MASK 0x1ffff + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_REG 0xe0 + +/* + * RD+ K28. + * 5 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDP_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDP_MASK 0x3ff0000 + +/* + * RD- K28. + * 5 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDN_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_2_CFNGPONGBOXRXK28D5RDN_MASK 0x3ff + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_REG 0xe4 + +/* + * RD+ D5. + * 7 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDP_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDP_MASK 0x3ff0000 + +/* + * RD- D5. + * 7 pattern. +*/ +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDN_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_RX_CTL_3_CFNGPONGBOXRXD5D7RDN_MASK 0x3ff + + +/* + * Register + * + * Configuration for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_REG 0xe8 + +/* + * Value for TX data FIFO read pointer. + * Steps of 2 x txClk (622 MHz),jumps of 32 bits. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFODATARDPTR_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFODATARDPTR_MASK 0xf0000 + +/* + * Value for TX valid FIFO offset. + * Steps of txClk (622 MHz), jumps of16 bits. + * 1 to 15 are advances valid vs data, valid comes out ahead. + * 1=1 clock, 2=2 clocks, 3=3 clocks. + * .. + * 31 to 16 are advances validvs data, valid comes out behind. + * 31=1 clock, 30=2 clocks, 29=3clocks. + * .. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOVLDOFF_SHIFT 8 +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOVLDOFF_MASK 0x1f00 + +/* Flip TX data valid endian on 32b input. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERVLDFLIP_MASK 0x40 + +/* Flip TX data endian on 32b input. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERDATAFLIP_MASK 0x20 + +/* Bitwise invert TX 4b valid to SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERVLDINV_MASK 0x10 + +/* Bitwise invert TX 16b data to SERDES. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXSERDATAINV_MASK 0x8 + +/* + * Load only the offset for TX valid FIFO pointer. + * This is an offsetfrom the data read pointer. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOVLDPTRLD_MASK 0x4 + +/* + * Load value for TX data FIFO read pointer and valid read pointeroffset. + * Data/valid write will be loaded to 0. +*/ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXFIFOPTRLD_MASK 0x2 + +/* Synchronous enable for TX gearbox. */ +#define WAN_TOP_NGPON_GEARBOX_TX_CTL_CFNGPONGBOXTXEN_MASK 0x1 + + +/* + * Register + * + * Status for the NGPON gearbox. + */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_REG 0xec + +/* Pointer collision. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONTXGBOXFIFOVLDPTRCOL_MASK 0x4000000 + +/* Framer state. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXSTATE_SHIFT 24 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXSTATE_MASK 0x3000000 + +/* Pointer collision. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONTXGBOXFIFODATAPTRCOL_MASK 0x800000 + +/* Number of KChar. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXKCNT_SHIFT 20 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXKCNT_MASK 0x700000 + +/* Pointer delta. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXFIFOPTRDELTA_SHIFT 16 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXFIFOPTRDELTA_MASK 0xf0000 + +/* 10b sync acquired. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXSYNCACQ_MASK 0x8000 + +/* FIFO pointer collision. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXFIFOPTRCOL_MASK 0x4000 + +/* Line errors. */ +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXCODEERRCNTSTAT_SHIFT 0 +#define WAN_TOP_NGPON_GEARBOX_STATUS_NGPONRXGBOXCODEERRCNTSTAT_MASK 0x3fff + + +/* + * Register + * + * Configuration for the 10G EPON gearbox. + */ +#define WAN_TOP_EPON_10G_GEARBOX_REG 0xf0 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_RX_CGEN_RSTN_MASK 0x1 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_CGEN_RSTN_MASK 0x2 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_RX_GBOX_RSTN_MASK 0x4 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_GBOX_RSTN_MASK 0x8 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_CLK_EN_MASK 0x10 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_RX_DATA_END_MASK 0x20 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX2RX_LOOP_EN_MASK 0x40 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_FIFO_OFF_LD_MASK 0x80 + +/* TBD */ +#define WAN_TOP_EPON_10G_GEARBOX_TX_FIFO_OFF_SHIFT 8 +#define WAN_TOP_EPON_10G_GEARBOX_TX_FIFO_OFF_MASK 0x700 + +/* Reserved */ +#define WAN_TOP_EPON_10G_GEARBOX_R0_SHIFT 11 +#define WAN_TOP_EPON_10G_GEARBOX_R0_MASK 0xfffff800 + + +#endif /* ! WAN_TOP_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xlif.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xlif.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xlif.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xlif.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,209 @@ +#ifndef XLIF_H_ +#define XLIF_H_ + +/* + * Register + * + * Interface_Disable + */ +#define XLIF_RX_IF_IF_DIS_REG(x) (0x0 + (x) * 0x200) + +/* Disable */ +#define XLIF_RX_IF_IF_DIS_DISABLE_MASK 0x1 + + +/* + * Register - read-only + * + * Indicate an overflow event (data valid while FIFO is full). + * read clear + */ +#define XLIF_RX_IF_OFLW_FLAG_REG 0x4 + +/* Overflow */ +#define XLIF_RX_IF_OFLW_FLAG_OFLW_MASK 0x1 + + +/* + * Register - read-only + * + * Indicate RX protocol Error. + * read clear + */ +#define XLIF_RX_IF_ERR_FLAG_REG 0x8 + +/* Error */ +#define XLIF_RX_IF_ERR_FLAG_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * eee indications from the XLMAC interface + */ +#define XLIF_EEE_IND_REG(r) (0x78 + (r) * 0x200) + +/* lpi_rx_detect */ +#define XLIF_EEE_IND_LPI_RX_DETECT_MASK 0x1 + +/* lpi_tx_detect */ +#define XLIF_EEE_IND_LPI_TX_DETECT_MASK 0x10 + + +/* + * Register - read-only + * + * . + */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_EN_REG(r) (0x20 + (r) * 0x200) + +/* PFC_EN */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_EN_PFC_EN_MASK 0x1 + +/* LLFC_en */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_EN_LLFC_EN_MASK 0x10 + + +/* + * Register - read-only + * + * . + */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_REG(r) (0x24 + (r) * 0x200) + +/* value */ +#define XLIF_RX_FLOW_CONTROL_COSMAP_VALUE_SHIFT 0 +#define XLIF_RX_FLOW_CONTROL_COSMAP_VALUE_MASK 0xffff + + +/* + * Register + * + * Interface_Enable + */ +#define XLIF_TX_IF_IF_ENABLE_REG(r) (0x40 + (r) * 0x200) + +/* Disable_With_Credits */ +#define XLIF_TX_IF_IF_ENABLE_DISABLE_WITH_CREDITS_MASK 0x1 + +/* Disable_WO_Credits */ +#define XLIF_TX_IF_IF_ENABLE_DISABLE_WO_CREDITS_MASK 0x2 + + +/* + * Register - read-only + * + * Read_Credits + */ +#define XLIF_TX_IF_READ_CREDITS_REG(r) (0x44 + (r) * 0x200) + +/* Value */ +#define XLIF_TX_IF_READ_CREDITS_VALUE_SHIFT 0 +#define XLIF_TX_IF_READ_CREDITS_VALUE_MASK 0x3ff + + +/* + * Register + * + * Set_CreditsThe enable bit and the new value can be set together. + * Then, the enable bit must be turned off, while the new value remain + * stable. + */ +#define XLIF_TX_IF_SET_CREDITS_REG(r) (0x48 + (r) * 0x200) + +/* Value */ +#define XLIF_TX_IF_SET_CREDITS_VALUE_SHIFT 0 +#define XLIF_TX_IF_SET_CREDITS_VALUE_MASK 0x3ff + +/* enable */ +#define XLIF_TX_IF_SET_CREDITS_EN_MASK 0x1000 + + +/* + * Register + * + * Control the values of several output signals on the XRDP -> XLMAC + * interface. + */ +#define XLIF_TX_IF_OUT_CTRL_REG(r) (0x4c + (r) * 0x200) + +/* mac_txerr */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXERR_MASK 0x1 + +/* mac_txcrcerr */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXCRCERR_MASK 0x2 + +/* mac_txosts_sinext */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXOSTS_SINEXT_MASK 0x4 + +/* mac_txcrcmode */ +#define XLIF_TX_IF_OUT_CTRL_MAC_TXCRCMODE_SHIFT 4 +#define XLIF_TX_IF_OUT_CTRL_MAC_TXCRCMODE_MASK 0x30 + + +/* + * Register + * + * Underrun_Protection_Enable + */ +#define XLIF_TX_IF_URUN_PORT_ENABLE_REG(r) (0x50 + (r) * 0x200) + +/* Enable */ +#define XLIF_TX_IF_URUN_PORT_ENABLE_ENABLE_MASK 0x1 + + +/* + * Register + * + * TX threshold for the TX CDC FIFO in units of 128 bit. + * The TX CDC FIFO is depth is 16 entries. + */ +#define XLIF_TX_IF_TX_THRESHOLD_REG(r) (0x54 + (r) * 0x200) + +/* Value */ +#define XLIF_TX_IF_TX_THRESHOLD_VALUE_SHIFT 0 +#define XLIF_TX_IF_TX_THRESHOLD_VALUE_MASK 0xf + + +/* + * Register - read-only + * + * cosmap_en indications from the XLMAC Interface + */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_EN_STAT_REG(r) (0x60 + (r) * 0x200) + +/* PFC_EN */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_EN_STAT_PFC_EN_MASK 0x1 + +/* LLFC_en */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_EN_STAT_LLFC_EN_MASK 0x10 + + +/* + * Register - read-only + * + * cosmap_status from the XLMAC Interface + */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_STAT_REG(r) (0x64 + (r) * 0x200) + +/* value */ +#define XLIF_TX_FLOW_CONTROL_COSMAP_STAT_VALUE_SHIFT 0 +#define XLIF_TX_FLOW_CONTROL_COSMAP_STAT_VALUE_MASK 0xffff + + +/* + * Register - read-only + * + * indications from the XLMAC IF + */ +#define XLIF_Q_OFF_IND_REG(r) (0x7c + (r) * 0x200) + +/* Q_OFF */ +#define XLIF_Q_OFF_IND_Q_OFF_SHIFT 0 +#define XLIF_Q_OFF_IND_Q_OFF_MASK 0xff + +/* Failover_on */ +#define XLIF_Q_OFF_IND_FAILOVER_ON_MASK 0x100 + + +#endif /* ! XLIF_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mab.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mab.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mab.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mab.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,164 @@ +#ifndef WAN_TOPXPORT_MAB_H_ +#define WAN_TOPXPORT_MAB_H_ + +/* relative to core */ +#define XPORT_MAB_OFFSET_0 0x3300 + +/* + * Register + * + */ +#define XPORT_MAB_CNTRL_REG 0x0 + +/* + * When this bit is set asynchronous RX and TX FIFOs are reset for a port + * when the link goes down that is when the local fault is detected. +*/ +#define CNTRL_LINK_DOWN_RST_EN_MASK 0x10000 + +/* + * When set resets 10G Port 0 asynchronous TX FIFO and associated logic + * (such as credit logic). +*/ +#define CNTRL_XGMII_TX_RST_MASK 0x1000 + +/* + * When a bit in this vector is set it resets corresponding port (Port 3-0) + * asynchronous TX FIFO and associated logic (such as credit logic and byte + * slicers). +*/ +#define CNTRL_GMII_TX_RST_SHIFT 8 +#define CNTRL_GMII_TX_RST_MASK 0xf00 + +/* When set resets 10G Port 0 asynchronous RX FIFO and associated logic. */ +#define CNTRL_XGMII_RX_RST_MASK 0x10 + +/* + * When a bit in this vector is set it resets corresponding port (Port 3-0) + * asynchronous RX FIFO and associated logic (such as byte packers). +*/ +#define CNTRL_GMII_RX_RST_SHIFT 0 +#define CNTRL_GMII_RX_RST_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MAB_TX_WRR_CTRL_REG 0x4 + +/* + * Arbiter Mode 1'b0 - Fixed Mode. + * TDM slots allocated regardless of the port activity. + * 1'b1 - Work-Conserving Mode. + * TDM slots allocation is affected by the port activity. +*/ +#define TX_WRR_CTRL_ARB_MODE_MASK 0x10000 + +/* P3 weight expressed in TDM time slots. */ +#define TX_WRR_CTRL_P3_WEIGHT_SHIFT 12 +#define TX_WRR_CTRL_P3_WEIGHT_MASK 0xf000 + +/* P2 weight expressed in TDM time slots. */ +#define TX_WRR_CTRL_P2_WEIGHT_SHIFT 8 +#define TX_WRR_CTRL_P2_WEIGHT_MASK 0xf00 + +/* P1 weight expressed in TDM time slots. */ +#define TX_WRR_CTRL_P1_WEIGHT_SHIFT 4 +#define TX_WRR_CTRL_P1_WEIGHT_MASK 0xf0 + +/* + * P0 weight expressed in TDM time slots. + * Note: + * Arbitration weights should not be changed from their default values due + * to XLMAC implementation specifics. + * In 4-port mode MSBUS clock should be set to 4*MAX_PORT_RATE/64. +*/ +#define TX_WRR_CTRL_P0_WEIGHT_SHIFT 0 +#define TX_WRR_CTRL_P0_WEIGHT_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MAB_TX_THRESHOLD_REG 0x8 + +/* + * XGMII0 (P0) asynchronous TX FIFO read depth at which packet dequeue + * starts. +*/ +#define TX_THRESHOLD_XGMII0_TX_THRESHOLD_SHIFT 16 +#define TX_THRESHOLD_XGMII0_TX_THRESHOLD_MASK 0xf0000 + +/* GMII P3 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII3_TX_THRESHOLD_SHIFT 12 +#define TX_THRESHOLD_GMII3_TX_THRESHOLD_MASK 0xf000 + +/* GMII P2 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII2_TX_THRESHOLD_SHIFT 8 +#define TX_THRESHOLD_GMII2_TX_THRESHOLD_MASK 0xf00 + +/* GMII P1 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII1_TX_THRESHOLD_SHIFT 4 +#define TX_THRESHOLD_GMII1_TX_THRESHOLD_MASK 0xf0 + +/* GMII P0 asynchronous TX FIFO read depth at which packet dequeue starts. */ +#define TX_THRESHOLD_GMII0_TX_THRESHOLD_SHIFT 0 +#define TX_THRESHOLD_GMII0_TX_THRESHOLD_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MAB_LINK_DOWN_TX_DATA_REG 0xc + +/* + * When LINK_DOWN_RST_EN = 1 and link is down content of this register is + * sent to serdes over XGMII interface. + * In GMII mode 0 is sent. +*/ +#define LINK_DOWN_TX_DATA_TXCTL_MASK 0x100 + +/* + * When LINK_DOWN_RST_EN = 1 and link is down content of this register is + * sent to serdes over XGMII interface. + * In GMII mode 0's are sent. +*/ +#define LINK_DOWN_TX_DATA_TXD_SHIFT 0 +#define LINK_DOWN_TX_DATA_TXD_MASK 0xff + + +/* + * Register - read-only + * + */ +#define XPORT_MAB_STATUS_REG 0x10 + +/* 10G Port 0 asynchronous RX FIFO over-run status. */ +#define STATUS_XGMII_RX_AFIFO_OVERRUN_MASK 0x8000 + +/* Port 3-0 asynchronous RX FIFO over-run status. */ +#define STATUS_GMII_RX_AFIFO_OVERRUN_VECT_SHIFT 11 +#define STATUS_GMII_RX_AFIFO_OVERRUN_VECT_MASK 0x7800 + +/* 10G Port 0 TX frame under-run status. */ +#define STATUS_XGMII_TX_FRM_UNDERRUN_MASK 0x400 + +/* 10G Port 0 TX credits under-run status. */ +#define STATUS_XGMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_MASK 0x200 + +/* Port 3-0 TX credits under-run status. */ +#define STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_SHIFT 5 +#define STATUS_GMII_OUTSTANDING_CREDITS_CNT_UNDERRUN_VECT_MASK 0x1e0 + +/* 10G Port 0 asynchronous TX FIFO over-run status. */ +#define STATUS_XGMII_TX_AFIFO_OVERRUN_MASK 0x10 + +/* Port 3-0 asynchronous TX FIFO over-run status. */ +#define STATUS_GMII_TX_AFIFO_OVERRUN_VECT_SHIFT 0 +#define STATUS_GMII_TX_AFIFO_OVERRUN_VECT_MASK 0xf + + +#endif /* ! WAN_TOPXPORT_MAB_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_core.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_core.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_core.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_core.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,117 @@ +#ifndef WAN_TOPXPORT_MIB_CORE_H_ +#define WAN_TOPXPORT_MIB_CORE_H_ + +/* relative to core */ +#define XPORT_MIB_CORE_OFFSET(x) (0x1000 + (x) * 0x400) + +#define XPORT_MIB_CORE_GRX64_REG 0x0 +#define XPORT_MIB_CORE_GRX127_REG 0x8 +#define XPORT_MIB_CORE_GRX255_REG 0x10 +#define XPORT_MIB_CORE_GRX511_REG 0x18 +#define XPORT_MIB_CORE_GRX1023_REG 0x20 +#define XPORT_MIB_CORE_GRX1518_REG 0x28 +#define XPORT_MIB_CORE_GRX1522_REG 0x30 +#define XPORT_MIB_CORE_GRX2047_REG 0x38 +#define XPORT_MIB_CORE_GRX4095_REG 0x40 +#define XPORT_MIB_CORE_GRX9216_REG 0x48 +#define XPORT_MIB_CORE_GRX16383_REG 0x50 +#define XPORT_MIB_CORE_GRXPKT_REG 0x58 +#define XPORT_MIB_CORE_GRXUCA_REG 0x60 +#define XPORT_MIB_CORE_GRXMCA_REG 0x68 +#define XPORT_MIB_CORE_GRXBCA_REG 0x70 +#define XPORT_MIB_CORE_GRXFCS_REG 0x78 +#define XPORT_MIB_CORE_GRXCF_REG 0x80 +#define XPORT_MIB_CORE_GRXPF_REG 0x88 +#define XPORT_MIB_CORE_GRXPP_REG 0x90 +#define XPORT_MIB_CORE_GRXUO_REG 0x98 +#define XPORT_MIB_CORE_GRXUDA_REG 0xa0 +#define XPORT_MIB_CORE_GRXWSA_REG 0xa8 +#define XPORT_MIB_CORE_GRXALN_REG 0xb0 +#define XPORT_MIB_CORE_GRXFLR_REG 0xb8 +#define XPORT_MIB_CORE_GRXFRERR_REG 0xc0 +#define XPORT_MIB_CORE_GRXFCR_REG 0xc8 +#define XPORT_MIB_CORE_GRXOVR_REG 0xd0 +#define XPORT_MIB_CORE_GRXJBR_REG 0xd8 +#define XPORT_MIB_CORE_GRXMTUE_REG 0xe0 +#define XPORT_MIB_CORE_GRXMCRC_REG 0xe8 +#define XPORT_MIB_CORE_GRXPRM_REG 0xf0 +#define XPORT_MIB_CORE_GRXVLN_REG 0xf8 +#define XPORT_MIB_CORE_GRXDVLN_REG 0x100 +#define XPORT_MIB_CORE_GRXTRFU_REG 0x108 +#define XPORT_MIB_CORE_GRXPOK_REG 0x110 +#define XPORT_MIB_CORE_GRXPFCOFF0_REG 0x118 +#define XPORT_MIB_CORE_GRXPFCOFF1_REG 0x120 +#define XPORT_MIB_CORE_GRXPFCOFF2_REG 0x128 +#define XPORT_MIB_CORE_GRXPFCOFF3_REG 0x130 +#define XPORT_MIB_CORE_GRXPFCOFF4_REG 0x138 +#define XPORT_MIB_CORE_GRXPFCOFF5_REG 0x140 +#define XPORT_MIB_CORE_GRXPFCOFF6_REG 0x148 +#define XPORT_MIB_CORE_GRXPFCOFF7_REG 0x150 +#define XPORT_MIB_CORE_GRXPFCP0_REG 0x158 +#define XPORT_MIB_CORE_GRXPFCP1_REG 0x160 +#define XPORT_MIB_CORE_GRXPFCP2_REG 0x168 +#define XPORT_MIB_CORE_GRXPFCP3_REG 0x170 +#define XPORT_MIB_CORE_GRXPFCP4_REG 0x178 +#define XPORT_MIB_CORE_GRXPFCP5_REG 0x180 +#define XPORT_MIB_CORE_GRXPFCP6_REG 0x188 +#define XPORT_MIB_CORE_GRXPFCP7_REG 0x190 +#define XPORT_MIB_CORE_GRXSCHCRC_REG 0x198 +#define XPORT_MIB_CORE_GRXBYT_REG 0x1a0 +#define XPORT_MIB_CORE_GRXRPKT_REG 0x1a8 +#define XPORT_MIB_CORE_GRXUND_REG 0x1b0 +#define XPORT_MIB_CORE_GRXFRG_REG 0x1b8 +#define XPORT_MIB_CORE_GRXRBYT_REG 0x1c0 +#define XPORT_MIB_CORE_GTX64_REG 0x1c8 +#define XPORT_MIB_CORE_GTX127_REG 0x1d0 +#define XPORT_MIB_CORE_GTX255_REG 0x1d8 +#define XPORT_MIB_CORE_GTX511_REG 0x1e0 +#define XPORT_MIB_CORE_GTX1023_REG 0x1e8 +#define XPORT_MIB_CORE_GTX1518_REG 0x1f0 +#define XPORT_MIB_CORE_GTX1522_REG 0x1f8 +#define XPORT_MIB_CORE_GTX2047_REG 0x200 +#define XPORT_MIB_CORE_GTX4095_REG 0x208 +#define XPORT_MIB_CORE_GTX9216_REG 0x210 +#define XPORT_MIB_CORE_GTX16383_REG 0x218 +#define XPORT_MIB_CORE_GTXPOK_REG 0x220 +#define XPORT_MIB_CORE_GTXPKT_REG 0x228 +#define XPORT_MIB_CORE_GTXUCA_REG 0x230 +#define XPORT_MIB_CORE_GTXMCA_REG 0x238 +#define XPORT_MIB_CORE_GTXBCA_REG 0x240 +#define XPORT_MIB_CORE_GTXPF_REG 0x248 +#define XPORT_MIB_CORE_GTXPFC_REG 0x250 +#define XPORT_MIB_CORE_GTXJBR_REG 0x258 +#define XPORT_MIB_CORE_GTXFCS_REG 0x260 +#define XPORT_MIB_CORE_GTXCF_REG 0x268 +#define XPORT_MIB_CORE_GTXOVR_REG 0x270 +#define XPORT_MIB_CORE_GTXDFR_REG 0x278 +#define XPORT_MIB_CORE_GTXEDF_REG 0x280 +#define XPORT_MIB_CORE_GTXSCL_REG 0x288 +#define XPORT_MIB_CORE_GTXMCL_REG 0x290 +#define XPORT_MIB_CORE_GTXLCL_REG 0x298 +#define XPORT_MIB_CORE_GTXXCL_REG 0x2a0 +#define XPORT_MIB_CORE_GTXFRG_REG 0x2a8 +#define XPORT_MIB_CORE_GTXERR_REG 0x2b0 +#define XPORT_MIB_CORE_GTXVLN_REG 0x2b8 +#define XPORT_MIB_CORE_GTXDVLN_REG 0x2c0 +#define XPORT_MIB_CORE_GTXRPKT_REG 0x2c8 +#define XPORT_MIB_CORE_GTXUFL_REG 0x2d0 +#define XPORT_MIB_CORE_GTXPFCP0_REG 0x2d8 +#define XPORT_MIB_CORE_GTXPFCP1_REG 0x2e0 +#define XPORT_MIB_CORE_GTXPFCP2_REG 0x2e8 +#define XPORT_MIB_CORE_GTXPFCP3_REG 0x2f0 +#define XPORT_MIB_CORE_GTXPFCP4_REG 0x2f8 +#define XPORT_MIB_CORE_GTXPFCP5_REG 0x300 +#define XPORT_MIB_CORE_GTXPFCP6_REG 0x308 +#define XPORT_MIB_CORE_GTXPFCP7_REG 0x310 +#define XPORT_MIB_CORE_GTXNCL_REG 0x318 +#define XPORT_MIB_CORE_GTXBYT_REG 0x320 +#define XPORT_MIB_CORE_GRXLPI_REG 0x328 +#define XPORT_MIB_CORE_GRXDLPI_REG 0x330 +#define XPORT_MIB_CORE_GTXLPI_REG 0x338 +#define XPORT_MIB_CORE_GTXDLPI_REG 0x340 +#define XPORT_MIB_CORE_GRXPTLLFC_REG 0x348 +#define XPORT_MIB_CORE_GRXLTLLFC_REG 0x350 +#define XPORT_MIB_CORE_GRXLLFCFCS_REG 0x358 +#define XPORT_MIB_CORE_GTXLTLLFC_REG 0x360 + +#endif /* ! WAN_TOPXPORT_MIB_CORE_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_reg.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_reg.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_mib_reg.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_mib_reg.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,706 @@ +#ifndef WAN_TOPXPORT_MIB_REG_H_ +#define WAN_TOPXPORT_MIB_REG_H_ + +/* relative to core */ +#define XPORT_MIB_REG_OFFSET_0 0x3100 + +/* + * Register + * + */ +#define XPORT_MIB_REG_DIR_ACC_DATA_WRITE_REG 0x0 + +/* + * Direct register access data write register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_SHIFT 0 +#define XPORT_MIB_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_DIR_ACC_DATA_READ_REG 0x4 + +/* + * Direct register access data read register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_DIR_ACC_DATA_READ_REG_READ_DATA_SHIFT 0 +#define XPORT_MIB_DIR_ACC_DATA_READ_REG_READ_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_ADDR_0_REG 0x8 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_OFFSET_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_ADDR_0_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_0_REG 0xc + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_0_REG 0x10 + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_ADDR_1_REG 0x14 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_OFFSET_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_ADDR_1_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_LOW_1_REG 0x18 + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_INDIR_ACC_DATA_HIGH_1_REG 0x1c + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_SHIFT 0 +#define XPORT_MIB_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_CNTRL_REG 0x20 + +/* + * RX and TX EEE Duration Counter Behavior 0 : + * Counter behavior is asymmetric mode (100Base-TX, for example). + * 1 : + * Counter behavior is symmetric mode (1000Base-T, for example). +*/ +#define XPORT_MIB_CNTRL_REG_EEE_CNT_MODE_SHIFT 12 +#define XPORT_MIB_CNTRL_REG_EEE_CNT_MODE_MASK 0xf000 + +/* + * When a bit in this vector is set corresponding XLMAC port statistic + * counters saturate at their respective maximum values. +*/ +#define XPORT_MIB_CNTRL_REG_SATURATE_EN_SHIFT 8 +#define XPORT_MIB_CNTRL_REG_SATURATE_EN_MASK 0xf00 + +/* + * When a bit in this vector is set corresponding XLMAC port statistic + * counters are clear-on-read. +*/ +#define XPORT_MIB_CNTRL_REG_COR_EN_SHIFT 4 +#define XPORT_MIB_CNTRL_REG_COR_EN_MASK 0xf0 + +/* + * When a bit in this vector is set corresponding XLMAC port statistic + * counters are reset. +*/ +#define XPORT_MIB_CNTRL_REG_CNT_RST_SHIFT 0 +#define XPORT_MIB_CNTRL_REG_CNT_RST_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_MIB_REG_EEE_PULSE_DURATION_CNTRL_REG 0x24 + +/* + * Timer to generate 10us pulse based on 25MHz refclk. + * Using LFSR to count up to 250 value. +*/ +#define XPORT_MIB_EEE_PULSE_DURATION_CNTRL_REG_CNT_SHIFT 0 +#define XPORT_MIB_EEE_PULSE_DURATION_CNTRL_REG_CNT_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT0_MAX_PKT_SIZE_REG 0x28 + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT0_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT0_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT1_MAX_PKT_SIZE_REG 0x2c + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT1_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT1_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT2_MAX_PKT_SIZE_REG 0x30 + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT2_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT2_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_GPORT3_MAX_PKT_SIZE_REG 0x34 + +/* + * Maximum Packet Size, defaults to 1518B. + * Packets over this size are counted by MIB as oversized. +*/ +#define XPORT_MIB_GPORT3_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_SHIFT 0 +#define XPORT_MIB_GPORT3_MAX_PKT_SIZE_REG_MAX_PKT_SIZE_MASK 0x3fff + + +/* + * Register + * + */ +#define XPORT_MIB_REG_ECC_CNTRL_REG 0x38 + +/* ECC enable for Tx MIB memories. */ +#define XPORT_MIB_ECC_CNTRL_REG_TX_MIB_ECC_EN_MASK 0x2 + +/* ECC enable for Rx MIB memories. */ +#define XPORT_MIB_ECC_CNTRL_REG_RX_MIB_ECC_EN_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_FORCE_SB_ECC_ERR_REG 0x3c + +/* + * Self-clearing. + * Force Tx MIB memory instance 3 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM3_SERR_MASK 0x100 + +/* + * Self-clearing. + * Force Tx MIB memory instance 2 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM2_SERR_MASK 0x80 + +/* + * Self-clearing. + * Force Tx MIB memory instance 1 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM1_SERR_MASK 0x40 + +/* + * Self-clearing. + * Force Tx MIB memory instance 0 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_TX_MEM0_SERR_MASK 0x20 + +/* + * Self-clearing. + * Force Rx MIB memory instance 4 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM4_SERR_MASK 0x10 + +/* + * Self-clearing. + * Force Rx MIB memory instance 3 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM3_SERR_MASK 0x8 + +/* + * Self-clearing. + * Force Rx MIB memory instance 2 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM2_SERR_MASK 0x4 + +/* + * Self-clearing. + * Force Rx MIB memory instance 1 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM1_SERR_MASK 0x2 + +/* + * Self-clearing. + * Force Rx MIB memory instance 0 single bit ECC error. + * Do not assert together with force double bit ECC error. +*/ +#define XPORT_MIB_FORCE_SB_ECC_ERR_REG_FORCE_RX_MEM0_SERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_FORCE_DB_ECC_ERR_REG 0x40 + +/* + * Self-clearing. + * Force Tx MIB memory instance 3 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM3_DERR_MASK 0x100 + +/* + * Self-clearing. + * Force Tx MIB memory instance 2 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM2_DERR_MASK 0x80 + +/* + * Self-clearing. + * Force Tx MIB memory instance 1 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM1_DERR_MASK 0x40 + +/* + * Self-clearing. + * Force Tx MIB memory instance 0 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_TX_MEM0_DERR_MASK 0x20 + +/* + * Self-clearing. + * Force Rx MIB memory instance 4 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM4_DERR_MASK 0x10 + +/* + * Self-clearing. + * Force Rx MIB memory instance 3 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM3_DERR_MASK 0x8 + +/* + * Self-clearing. + * Force Rx MIB memory instance 2 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM2_DERR_MASK 0x4 + +/* + * Self-clearing. + * Force Rx MIB memory instance 1 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM1_DERR_MASK 0x2 + +/* + * Self-clearing. + * Force Rx MIB memory instance 0 double bit ECC error. + * Do not assert together with force single bit ECC error. +*/ +#define XPORT_MIB_FORCE_DB_ECC_ERR_REG_FORCE_RX_MEM0_DERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM0_ECC_STATUS_REG 0x44 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM0_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM1_ECC_STATUS_REG 0x48 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM1_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM2_ECC_STATUS_REG 0x4c + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM2_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM3_ECC_STATUS_REG 0x50 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM3_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_RX_MEM4_ECC_STATUS_REG 0x54 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_RX_MEM4_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM0_ECC_STATUS_REG 0x58 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM0_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM1_ECC_STATUS_REG 0x5c + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM1_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM2_ECC_STATUS_REG 0x60 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM2_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_MIB_REG_TX_MEM3_ECC_STATUS_REG 0x64 + +/* + * First memory address in which single bit error or double bit error is + * detected. +*/ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_MEM_ADDR_SHIFT 3 +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_MEM_ADDR_MASK 0x78 + +/* Double Bit Error indicates an uncorrectable error occurred. */ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_DOUBLE_BIT_ECC_ERR_MASK 0x4 + +/* + * Indicates more than one single bit error or double bit error are + * detected. +*/ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_MULTI_ECC_ERR_MASK 0x2 + +/* + * Single Bit Error (correctable) or Double Bit Error (Uncorrectable) + * occurred. +*/ +#define XPORT_MIB_TX_MEM3_ECC_STATUS_REG_ECC_ERR_MASK 0x1 + + +#endif /* ! WAN_TOPXPORT_MIB_REG_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_reg.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_reg.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_reg.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_reg.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,842 @@ +#ifndef WAN_TOPXPORT_REG_H_ +#define WAN_TOPXPORT_REG_H_ + +/* relative to core */ +#define XPORT_REG_OFFSET_0 0x2004 + +/* + * Register - read-only + * + */ +#define XPORT_REG_XPORT_REVISION_REG 0x0 + +/* XPORT revision. */ +#define XPORT_XPORT_REVISION_REG_XPORT_REV_SHIFT 0 +#define XPORT_XPORT_REVISION_REG_XPORT_REV_MASK 0xffffff + + +/* + * Register + * + */ +#define XPORT_REG_LED_PWM_CNTRL_REG 0x68 + +/* When set LED intensity can be controlled using PWM. */ +#define XPORT_LED_PWM_CNTRL_REG_PWM_ENABLE_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_REG_LED_INTENSITY_CNTRL_REG 0x6c + +/* + * LED_ON_TIME PWM modulated ON (low) time. + * LED_ON_LOW and LED_ON_HIGH determine PWM duty cycle for the LED + * intensity. + * Expressed in 50us units. +*/ +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_LOW_SHIFT 16 +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_LOW_MASK 0xffff0000 + +/* + * LED_ON_TIME PWM modulated OFF (high) time. + * LED_ON_LOW and LED_ON_HIGH determine PWM duty cycle for the LED + * intensity. + * Expressed in 50us units. +*/ +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_HIGH_SHIFT 0 +#define XPORT_LED_INTENSITY_CNTRL_REG_LED_ON_HIGH_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_LED_0_CNTRL_REG 0x70 + +/* + * When this bit is set MAC/PHY provided link indication is overridden + * using lnk_status_ovrd. +*/ +#define XPORT_LED_0_CNTRL_REG_LNK_OVRD_EN_MASK 0x8000 + +/* + * When this bit is set MAC/PHY provided speed indications are overridden + * using led_spd_ovrd[2: + * 0]. +*/ +#define XPORT_LED_0_CNTRL_REG_SPD_OVRD_EN_MASK 0x4000 + +/* + * Link status override. + * Used only for LED. +*/ +#define XPORT_LED_0_CNTRL_REG_LNK_STATUS_OVRD_MASK 0x2000 + +/* + * LED speed override. + * Default encoding is: + * 000 : + * 10Mb/s. + * 001 : + * 100Mb/s. + * 010 : + * 1000Mb/s. + * 011 : + * 2. + * 5Gb/s. + * 100 : + * 10Gb/s or higher. + * 101 : + * Custom speed 1. + * 110 : + * Custom speed 2. + * 111 : + * no-link. + * Using this register LED speeds can be encoded in any way that suits + * customer application. +*/ +#define XPORT_LED_0_CNTRL_REG_LED_SPD_OVRD_SHIFT 10 +#define XPORT_LED_0_CNTRL_REG_LED_SPD_OVRD_MASK 0x1c00 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for ACT_LED. +*/ +#define XPORT_LED_0_CNTRL_REG_ACT_LED_POL_SEL_MASK 0x200 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[2]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED2_ACT_POL_SEL_MASK 0x100 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[1]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED1_ACT_POL_SEL_MASK 0x80 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[0]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED0_ACT_POL_SEL_MASK 0x40 + +/* + * Selects source of activity for ACT_LED. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_0_CNTRL_REG_ACT_LED_ACT_SEL_MASK 0x20 + +/* + * Selects source of activity for SPDLNK_LED[2]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED2_ACT_SEL_MASK 0x10 + +/* + * Selects source of activity for SPDLNK_LED[1]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED1_ACT_SEL_MASK 0x8 + +/* + * Selects source of the activity for SPDLNK_LED[0]: + * 0 : + * LED is 0 when link is up and blinks when there is activity. + * 1 : + * LED is 1 and blinks when there is activity. +*/ +#define XPORT_LED_0_CNTRL_REG_SPDLNK_LED0_ACT_SEL_MASK 0x4 + +/* Enables TX_SOP event to contribute to the activity. */ +#define XPORT_LED_0_CNTRL_REG_TX_ACT_EN_MASK 0x2 + +/* Enables RX_SOP event to contribute to the activity. */ +#define XPORT_LED_0_CNTRL_REG_RX_ACT_EN_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_REG_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG 0x74 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Gb/s and higher link speed. + * When SPDLNK_LED_SEL[x] = 1'''b0, SPDLNK_LED[x] is driven by bits [17: + * 0] of Link and Speed Encoding Register. + * When SPDLNK_LED_SEL[x] = 1'''b1, SPDLNK_LED[x] is driven by the + * activity. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_SHIFT 15 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 2500Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_SHIFT 12 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 1000Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_SHIFT 9 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_SHIFT 6 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_SHIFT 3 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_0_LINK_AND_SPEED_ENCODING_REG 0x78 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Gb/s and higherlink speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_SHIFT 15 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 2. + * 5Gb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_SHIFT 12 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 1Gb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_SHIFT 9 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_SHIFT 6 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_SHIFT 3 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_0_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_1_CNTRL_REG 0x7c + +/* + * When this bit is set MAC/PHY provided link indication is overridden + * using lnk_status_ovrd. +*/ +#define XPORT_LED_1_CNTRL_REG_LNK_OVRD_EN_MASK 0x8000 + +/* + * When this bit is set MAC/PHY provided speed indications are overridden + * using led_spd_ovrd[2: + * 0]. +*/ +#define XPORT_LED_1_CNTRL_REG_SPD_OVRD_EN_MASK 0x4000 + +/* + * Link status override. + * Used only for LED. +*/ +#define XPORT_LED_1_CNTRL_REG_LNK_STATUS_OVRD_MASK 0x2000 + +/* + * LED speed override. + * Default encoding is: + * 000 : + * 10Mb/s. + * 001 : + * 100Mb/s. + * 010 : + * 1000Mb/s. + * 011 : + * 2. + * 5Gb/s. + * 100 : + * 10Gb/s or higher. + * 101 : + * Custom speed 1. + * 110 : + * Custom speed 2. + * 111 : + * no-link. + * Using this register LED speeds can be encoded in any way that suits + * customer application. +*/ +#define XPORT_LED_1_CNTRL_REG_LED_SPD_OVRD_SHIFT 10 +#define XPORT_LED_1_CNTRL_REG_LED_SPD_OVRD_MASK 0x1c00 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for ACT_LED. +*/ +#define XPORT_LED_1_CNTRL_REG_ACT_LED_POL_SEL_MASK 0x200 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[2]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED2_ACT_POL_SEL_MASK 0x100 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[1]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED1_ACT_POL_SEL_MASK 0x80 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for SPDLNK_LED[0]. + * Applicable only when the activity drives this LED. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED0_ACT_POL_SEL_MASK 0x40 + +/* + * Selects source of activity for ACT_LED. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_1_CNTRL_REG_ACT_LED_ACT_SEL_MASK 0x20 + +/* + * Selects source of activity for SPDLNK_LED[2]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED2_ACT_SEL_MASK 0x10 + +/* + * Selects source of activity for SPDLNK_LED[1]. + * For encoding see description for spdlnk_led0_act_sel. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED1_ACT_SEL_MASK 0x8 + +/* + * Selects source of the activity for SPDLNK_LED[0]: + * 0 : + * LED is 0 when link is up and blinks when there is activity. + * 1 : + * LED is 1 and blinks when there is activity. +*/ +#define XPORT_LED_1_CNTRL_REG_SPDLNK_LED0_ACT_SEL_MASK 0x4 + +/* Enables TX_SOP event to contribute to the activity. */ +#define XPORT_LED_1_CNTRL_REG_TX_ACT_EN_MASK 0x2 + +/* Enables RX_SOP event to contribute to the activity. */ +#define XPORT_LED_1_CNTRL_REG_RX_ACT_EN_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_REG_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG 0x80 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding select. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_RSVD_SEL_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Gb/s and higher link speed. + * When SPDLNK_LED_SEL[x] = 1'''b0, SPDLNK_LED[x] is driven by bits [17: + * 0] of Link and Speed Encoding Register. + * When SPDLNK_LED_SEL[x] = 1'''b1, SPDLNK_LED[x] is driven by the + * activity. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_SHIFT 15 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 2500Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_SHIFT 12 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_2500M_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 1000Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_SHIFT 9 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_1000M_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_SHIFT 6 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_100M_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_SHIFT 3 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_10M_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED_SEL[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_SEL_REG_SEL_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_1_LINK_AND_SPEED_ENCODING_REG 0x84 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_SHIFT 21 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_2_MASK 0xe00000 + +/* + * Reserved SPDLNK_LED_SEL[2: + * 0] encoding. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_SHIFT 18 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_RSVD_SPD_ENCODE_1_MASK 0x1c0000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Gb/s and higherlink speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_SHIFT 15 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10G_ENCODE_MASK 0x38000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 2. + * 5Gb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_SHIFT 12 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M2500_ENCODE_MASK 0x7000 + +/* + * SPDLNK_LED[2: + * 0] encoding for 1Gb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_SHIFT 9 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M1000_ENCODE_MASK 0xe00 + +/* + * SPDLNK_LED[2: + * 0] encoding for 100Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_SHIFT 6 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M100_ENCODE_MASK 0x1c0 + +/* + * SPDLNK_LED[2: + * 0] encoding for 10Mb/s link speed. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_SHIFT 3 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_M10_ENCODE_MASK 0x38 + +/* + * SPDLNK_LED[2: + * 0] encoding for the no-link state. +*/ +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_SHIFT 0 +#define XPORT_LED_1_LINK_AND_SPEED_ENCODING_REG_NO_LINK_ENCODE_MASK 0x7 + + +/* + * Register + * + */ +#define XPORT_REG_LED_BLINK_RATE_CNTRL_REG 0xd0 + +/* + * Led ON time. + * Expressed in 50us units. +*/ +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_SHIFT 16 +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_MASK 0xffff0000 + +/* + * Led OFF time. + * Expressed in 50us units. +*/ +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_SHIFT 0 +#define XPORT_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_LED_SERIAL_CNTRL_REG 0xd4 + +/* + * Indicates number of LED signals per port that are shifted out: + * 11 : + * 4 LEDs per port mode (SPDLNK_LED[2: + * 0] and ACT_LED). + * 10 : + * 3 LEDs per port mode (SPDLNK_LED[2: + * 0]). + * 01 : + * 3 LEDs per port mode (SPDLNK_LED[1: + * 0] and ACT_LED). + * 00 : + * 2 LEDs per port mode (SPDLNK_LED[1: + * 0]) +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_SMODE_SHIFT 23 +#define XPORT_LED_SERIAL_CNTRL_REG_SMODE_MASK 0x1800000 + +/* + * Indicates SLED_CLK frequency. + * 0 : + * SLED_CLK is 6. + * 25Mhz. + * 1 : + * SLED_CLK is 3. + * 125Mhz. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_SLED_CLK_FREQUENCY_MASK 0x400000 + +/* + * When this bit is 1'b1 serial LED clock(SCLK) polarity is inveretd. + * Used with shift registers that trigger on the falling edge. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_SLED_CLK_POL_MASK 0x200000 + +/* + * Serial LED refresh period. + * Expressed in 5ms units. + * Value of 0 means 32x5ms period. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_REFRESH_PERIOD_SHIFT 16 +#define XPORT_LED_SERIAL_CNTRL_REG_REFRESH_PERIOD_MASK 0x1f0000 + +/* + * When the corresponding bit is set, port LEDs are shifted out. + * When all bits are cleared, serial LED interface is disabled. +*/ +#define XPORT_LED_SERIAL_CNTRL_REG_PORT_EN_SHIFT 0 +#define XPORT_LED_SERIAL_CNTRL_REG_PORT_EN_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_REFRESH_PERIOD_CNTRL_REG 0xd8 + +/* + * This register is used only in debug purposes. + * It controls REFRESH_PERIOD time unit that is based on 25MHz clock. + * default is 5 ms. +*/ +#define XPORT_REFRESH_PERIOD_CNTRL_REG_REFRESH_PERIOD_CNT_SHIFT 0 +#define XPORT_REFRESH_PERIOD_CNTRL_REG_REFRESH_PERIOD_CNT_MASK 0xffffff + + +/* + * Register + * + */ +#define XPORT_REG_AGGREGATE_LED_CNTRL_REG 0xdc + +/* + * When set to 1'b1 inverts polarity of the link signal that is used for + * aggregate LNK_LED. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_LNK_POL_SEL_MASK 0x40000 + +/* + * When set to 1'b1 inverts polarity of the activity signal that is used + * for aggregate ACT_LED. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_ACT_POL_SEL_MASK 0x20000 + +/* + * Selects behavior for aggregate ACT_LED. + * Encoded as: + * 0 : + * LED is 0 when aggregate link is up and blinks when there is activity. + * LED is 1 when aggregate link is down. + * 1 : + * LED is 1 and blinks when there is activity, regardless of the aggregate + * link status. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_ACT_SEL_MASK 0x10000 + +/* + * When the corresponding bit is set, port LEDs are included in aggregate + * LED signals. + * When all bits are cleared, aggregate LED interface is disabled. +*/ +#define XPORT_AGGREGATE_LED_CNTRL_REG_PORT_EN_SHIFT 0 +#define XPORT_AGGREGATE_LED_CNTRL_REG_PORT_EN_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_AGGREGATE_LED_BLINK_RATE_CNTRL_REG 0xe0 + +/* + * Led ON time. + * Expressed in 50us units. +*/ +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_SHIFT 16 +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_ON_TIME_MASK 0xffff0000 + +/* + * Led OFF time. + * Expressed in 50us units. +*/ +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_SHIFT 0 +#define XPORT_AGGREGATE_LED_BLINK_RATE_CNTRL_REG_LED_OFF_TIME_MASK 0xffff + + +/* + * Register + * + */ +#define XPORT_REG_SPARE_CNTRL_REG 0xe4 + +/* + * Spare register. + * Reserved for future use. +*/ +#define XPORT_SPARE_CNTRL_REG_SPARE_REG_SHIFT 0 +#define XPORT_SPARE_CNTRL_REG_SPARE_REG_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_REG_XPORT_CNTRL_1_REG 0x1fc + +/* + * MSBUS clock select. + * 0 : + * 500MHz. + * 1 : + * 644. + * 53125MHz. + * 644. + * 53125MHz clock should be used ONLY when 10G AE and SGMII serdes are + * simultaneously connected to XRDP. +*/ +#define XPORT_CNTRL_1_REG_MSBUS_CLK_SEL_MASK 0x1000 + +/* + * selects port driving WAN LED0 set. + * 0 : + * P0 drives LEDs. + * 1 : + * P1 drives LEDs. +*/ +#define XPORT_CNTRL_1_REG_WAN_LED0_SEL_MASK 0x800 + +/* + * When this bit is set, XPORT internal register bus bridges are not + * automatically reseted/reinitalized when the UBUS slave port times out. +*/ +#define XPORT_CNTRL_1_REG_TIMEOUT_RST_DISABLE_MASK 0x400 + +/* + * P0 Mode: + * 0 : + * P0 operates in GMII mode. + * 1 : + * P0 operates in XGMII mode. +*/ +#define XPORT_CNTRL_1_REG_P0_MODE_MASK 0x100 + + +/* + * Register - read-only + * + */ +#define XPORT_REG_CROSSBAR_STATUS_REG 0x200 + +/* + * When set indicates that full-duplex link is established. + * Half-duplex is not supported and indicates erroneous link. +*/ +#define XPORT_CROSSBAR_STATUS_REG_FULL_DUPLEX_MASK 0x80 + +/* When set indicates that TX PAUSE is negotiated. */ +#define XPORT_CROSSBAR_STATUS_REG_PAUSE_TX_MASK 0x40 + +/* When set indicates that RX PAUSE is negotiated. */ +#define XPORT_CROSSBAR_STATUS_REG_PAUSE_RX_MASK 0x20 + +/* + * When set indicate that link is 2. + * 5Gb. +*/ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_2500_MASK 0x10 + +/* When set indicate that link is 1Gb. */ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_1000_MASK 0x8 + +/* When set indicate that link is 100Mb. */ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_100_MASK 0x4 + +/* When set indicate that link is 10Mb. */ +#define XPORT_CROSSBAR_STATUS_REG_SPEED_10_MASK 0x2 + +/* + * Link Status. + * When 1 indicates that link is up for the selected PHY/RGMII. +*/ +#define XPORT_CROSSBAR_STATUS_REG_LINK_STATUS_MASK 0x1 + + +/* + * Register - read-only + * + */ +#define XPORT_REG_PON_AE_SERDES_STATUS_REG 0x204 + +/* When 0 indicates presence of the optical module. */ +#define XPORT_PON_AE_SERDES_STATUS_REG_MOD_DEF0_MASK 0x40 + +/* + * Non-filtered signal detect (or loss of signal) from the pin as provided + * by the external optical module. + * Please consult used optical module datasheet for polarity. + * NVRAM bit that indicates expected polarity is recommended. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_EXT_SIG_DET_MASK 0x20 + +/* + * PLL1 Lock. + * When 1'b1, indicates that single SERDES PLL1 is locked. + * Only one of PLLs (PLL0 or PLL1) is active at any time, depending on the + * operational mode. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_PLL1_LOCK_MASK 0x10 + +/* + * PLL0 Lock. + * When 1'b1, indicates that single SERDES PLL0 is locked. + * Only one of PLLs (PLL0 or PLL1) is active at any time, depending on the + * operational mode. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_PLL0_LOCK_MASK 0x8 + +/* + * Link Status. + * When 1'b1, indicates that link is up. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_LINK_STATUS_MASK 0x4 + +/* + * CDR Lock. + * When 1'b1, indicates that CDR is locked. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_CDR_LOCK_MASK 0x2 + +/* + * Filtered Rx Signal Detect. + * When 1'b1 indicates presence of the signal on Rx pins. +*/ +#define XPORT_PON_AE_SERDES_STATUS_REG_RX_SIGDET_MASK 0x1 + + +#endif /* ! WAN_TOPXPORT_REG_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_core.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_core.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_core.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_core.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,2010 @@ +#ifndef WAN_TOPXPORT_XLMAC_CORE_H_ +#define WAN_TOPXPORT_XLMAC_CORE_H_ + +/* relative to core */ +#define XPORT_XLMAC_CORE_OFFSET(x) (0x0 + (x) * 0x400) + +/* + * Register + * + * MAC control. + */ +#define XPORT_XLMAC_CORE_CTRL_REG 0x0 + +/* + * Extended Higig 2 header is also known as sirius header. + * Setting this bit to 0 will disable parsing for the extended header + * bit(5th bit of 8th header byte) in HG2 header and hence all the Higig 2 + * packets will be treated as normal Higig2 packets irrespective of + * extended header bit value. + * Default value of this field is 1 which will enable parsing extended + * header bit in every Higig 2 header. +*/ +#define CTRL_EXTENDED_HIG2_EN_MASK 0x4000 + +/* + * This configuration chooses between link status indication from software + * (SW_LINK_STATUS) or the hardware link status (hw_link_status)indication + * from the TSC. + * If reset, it selects the software link status +*/ +#define CTRL_LINK_STATUS_SELECT_MASK 0x2000 + +/* + * Link status indication from Software. + * If set, indicates that link is active. +*/ +#define CTRL_SW_LINK_STATUS_MASK 0x1000 + +/* + * If set, this will override the one column idle/sequence ordered set + * check before SOP in XGMII mode - effectively supporting reception of + * packets with 1 byte IPG in XGMII mode +*/ +#define CTRL_XGMII_IPG_CHECK_DISABLE_MASK 0x800 + +/* + * Resets the RS layer functionality - Fault detection and related + * responses are disabled and IDLEs are sent on line +*/ +#define CTRL_RS_SOFT_RESET_MASK 0x400 + +/* Reserved */ +#define CTRL_RSVD_5_MASK 0x200 + +/* + * If set, during the local loopback mode, the transmit packets are also + * sent to the transmit line interface, apart from the loopback operation +*/ +#define CTRL_LOCAL_LPBK_LEAK_ENB_MASK 0x100 + +/* Reserved */ +#define CTRL_RSVD_4_MASK 0x80 + +/* + * If set, disables the corresponding port logic and status registers only. + * Packet data and flow control logic is disabled. + * Fault handling is active and the MAC will continue to respond to credits + * from TSC. + * When the soft reset is cleared MAC will issue a fresh set of credits to + * EP in transmit side. +*/ +#define CTRL_SOFT_RESET_MASK 0x40 + +/* + * If set, enable LAG Failover. + * This bit has priority over LOCAL_LPBK. + * The lag failover kicks in when the link status selected by + * LINK_STATUS_SELECT transitions from 1 to 0. + * TSC clock and TSC credits must be active for lag failover. +*/ +#define CTRL_LAG_FAILOVER_EN_MASK 0x20 + +/* + * If set, XLMAC will move from lag failover state to normal operation. + * This bit should be set after link is up. +*/ +#define CTRL_REMOVE_FAILOVER_LPBK_MASK 0x10 + +/* Reserved */ +#define CTRL_RSVD_1_MASK 0x8 + +/* + * If set, enables local loopback from TX to RX. + * This loopback is on the line side after clock domain crossing - from the + * last TX pipeline stage to the first RX pipeline stage. + * Hence, TSC clock and TSC credits must be active for loopback. + * LAG_FAILOVER_EN should be disabled for this bit to work. +*/ +#define CTRL_LOCAL_LPBK_MASK 0x4 + +/* If set, enables MAC receive datapath and flowcontrol logic. */ +#define CTRL_RX_EN_MASK 0x2 + +/* + * If set, enables MAC transmit datapath and flowcontrol logic. + * When disabled, MAC will respond to TSC credits with IDLE codewords. +*/ +#define CTRL_TX_EN_MASK 0x1 + + +/* + * Register + * + * XLMAC Mode register + */ +#define XPORT_XLMAC_CORE_MODE_REG 0x8 + +/* Port Speed, used for LED indications and internal buffer sizing. */ +#define MODE_SPEED_MODE_SHIFT 4 +#define MODE_SPEED_MODE_MASK 0x70 + +/* If set, excludes the SOP byte for CRC calculation in HIGIG modes */ +#define MODE_NO_SOP_FOR_CRC_HG_MASK 0x8 + +/* Packet Header mode. */ +#define MODE_HDR_MODE_SHIFT 0 +#define MODE_HDR_MODE_MASK 0x7 + + +/* + * Register + * + * Spare reg 0 for ECO + */ +#define XPORT_XLMAC_CORE_SPARE0_REG 0x10 + +/* SPARE REGISTER 0 */ +#define SPARE0_RSVD_SHIFT 0 +#define SPARE0_RSVD_MASK 0xffffffff + + +/* + * Register + * + * Spare reg 1 for ECO + */ +#define XPORT_XLMAC_CORE_SPARE1_REG 0x18 + +/* SPARE REGISTER 1 */ +#define SPARE1_RSVD_SHIFT 0 +#define SPARE1_RSVD_MASK 0x3 + + +/* + * Register + * + * Transmit control. + * This XLMAC core register is 42 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_TX_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_TX_CTRL_REG 0x20 + +/* + * Indicates the number of 16-byte cells that are buffered per packet in + * the Tx CDC FIFO, before starting transmission of the packet on the line + * side. + * This setting is useful to prevent underflow issues if the EP logic pumps + * in data at port rate, rather than bursting at full rate. + * This mode will increase the overall latency. + * In quad port mode, this field should be set >= 1 and <= 4 for each port. + * In single port mode, this field should be set >= 1 and <= 16 for the + * four lane port (port0). + * In dual port mode, this field should be set >= 1 and <= 8 for each two + * lane port (port0 and port2). + * In tri1/tri2, this field should be set >= 1 and <= 4 for each single + * lane port, and >= 1 and <= 8 for the two lane port. +*/ +#define TX_CTRL_TX_THRESHOLD_SHIFT 38 +#define TX_CTRL_TX_THRESHOLD_MASK 0x3c000000000 + +/* + * If set, MAC accepts packets from the EP but does not write to the CDC + * FIFO and discards them on the core side without updating the statistics. +*/ +#define TX_CTRL_EP_DISCARD_MASK 0x2000000000 + +/* + * Number of preamble bytes for transmit IEEE packets, this value should + * include the K. + * SOP & SFD character as well +*/ +#define TX_CTRL_TX_PREAMBLE_LENGTH_SHIFT 33 +#define TX_CTRL_TX_PREAMBLE_LENGTH_MASK 0x1e00000000 + +/* + * Number of bytes to transmit before adding THROT_NUM bytes to the IPG. + * This configuration is used for WAN IPG throttling. + * Refer MAC specs for more details. +*/ +#define TX_CTRL_THROT_DENOM_SHIFT 25 +#define TX_CTRL_THROT_DENOM_MASK 0x1fe000000 + +/* + * Number of bytes of extra IPG added whenever THROT_DENOM bytes have been + * transmitted. + * This configuration is used for WAN IPG throttling. + * Refer MAC specs for more details. +*/ +#define TX_CTRL_THROT_NUM_SHIFT 19 +#define TX_CTRL_THROT_NUM_MASK 0x1f80000 + +/* + * Average interpacket gap. + * Must be programmed >= 8. + * Per packet IPG will vary based on DIC for 10G+ speeds. +*/ +#define TX_CTRL_AVERAGE_IPG_SHIFT 12 +#define TX_CTRL_AVERAGE_IPG_MASK 0x7f000 + +/* + * If padding is enabled, packets smaller than PAD_THRESHOLD are padded to + * this size. + * This must be set to a value >= 17 (decimal) +*/ +#define TX_CTRL_PAD_THRESHOLD_SHIFT 5 +#define TX_CTRL_PAD_THRESHOLD_MASK 0xfe0 + +/* If set, enable XLMAC to pad packets smaller than PAD_THRESHOLD on the Tx */ +#define TX_CTRL_PAD_EN_MASK 0x10 + +/* + * If reset, MAC forces the first byte of a packet to be /S/ character + * (0xFB) irrespective of incoming EP data at SOP location in HIGIG modes +*/ +#define TX_CTRL_TX_ANY_START_MASK 0x8 + +/* + * If set, MAC accepts packets from the EP and discards them on the line + * side. + * The statistics are updated. +*/ +#define TX_CTRL_DISCARD_MASK 0x4 + +/* CRC mode for Transmit Side */ +#define TX_CTRL_CRC_MODE_SHIFT 0 +#define TX_CTRL_CRC_MODE_MASK 0x3 + + +/* + * Register + * + * Transmit Source Address. + * This XLMAC core register is 48 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_MAC_SA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_TX_MAC_SA_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_TX_MAC_SA_REG 0x28 + +/* Source Address for PAUSE/PFC packets generated by the MAC */ +#define TX_MAC_SA_CTRL_SA_SHIFT 0 +#define TX_MAC_SA_CTRL_SA_MASK 0xffffffffffff + + +/* + * Register + * + * Receive control. + */ +#define XPORT_XLMAC_CORE_RX_CTRL_REG 0x30 + +/* + * This configuration is used to pass or drop pfc packetw when + * pfc_ether_type is not equal to 0x8808. + * If set, PFC frames are passed to system side. + * Otherwise, PFC frames are dropped in XLMAC. + * This configuration is used in Rx CDC mode only. +*/ +#define RX_CTRL_RX_PASS_PFC_MASK 0x8000 + +/* + * If set, PAUSE frames are passed to sytem side. + * Otherwise, PAUSE frames are dropped in XLMAC This configuration is used + * in Rx CDC mode only. +*/ +#define RX_CTRL_RX_PASS_PAUSE_MASK 0x4000 + +/* + * This configuration is used to drop or pass all control frames (with + * ether type 0x8808) except pause packets. + * If set, all control frames are passed to system side. + * Otherwise, control frames (including pfc frames wih ether type 0x8808) + * are dropped in XLMAC. + * This configuration is used in Rx CDC mode only. +*/ +#define RX_CTRL_RX_PASS_CTRL_MASK 0x2000 + +/* Reserved */ +#define RX_CTRL_RSVD_3_MASK 0x1000 + +/* Reserved */ +#define RX_CTRL_RSVD_2_MASK 0x800 + +/* + * The runt threshold, below which the packets are dropped (CDC mode) or + * marked as runt (Low latency mode). + * Should be programmed < 96 bytes (decimal) +*/ +#define RX_CTRL_RUNT_THRESHOLD_SHIFT 4 +#define RX_CTRL_RUNT_THRESHOLD_MASK 0x7f0 + +/* + * If set, MAC checks for IEEE Ethernet preamble - K. + * SOP + 6 "0x55" preamble bytes + "0xD5" SFD character - if this sequence + * is missing it is treated as an errored packet +*/ +#define RX_CTRL_STRICT_PREAMBLE_MASK 0x8 + +/* If set, CRC is stripped from the received packet */ +#define RX_CTRL_STRIP_CRC_MASK 0x4 + +/* If set, MAC allows any undefined control character to start a packet */ +#define RX_CTRL_RX_ANY_START_MASK 0x2 + +/* Reserved */ +#define RX_CTRL_RSVD_1_MASK 0x1 + + +/* + * Register + * + * Receive source address. + * This XLMAC core register is 48 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_RX_MAC_SA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_RX_MAC_SA_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_RX_MAC_SA_REG 0x38 + +/* + * Source Address recognized for MAC control packets in addition to the + * standard 0x0180C2000001 +*/ +#define RX_MAC_SA_RX_SA_SHIFT 0 +#define RX_MAC_SA_RX_SA_MASK 0xffffffffffff + + +/* + * Register + * + * Receive maximum packet size. + */ +#define XPORT_XLMAC_CORE_RX_MAX_SIZE_REG 0x40 + +/* + * Maximum packet size in receive direction, exclusive of preamble & CRC in + * strip mode. + * Packets greater than this size are truncated to this value. +*/ +#define RX_MAX_SIZE_RX_MAX_SIZE_SHIFT 0 +#define RX_MAX_SIZE_RX_MAX_SIZE_MASK 0x3fff + + +/* + * Register + * + * Inner and Outer VLAN tag fields This XLMAC core register is 34 bits wide + * in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_RX_VLAN_TAG) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + */ +#define XPORT_XLMAC_CORE_RX_VLAN_TAG_REG 0x48 + +/* If set, MAC enables VLAN tag detection using the OUTER_VLAN_TAG */ +#define RX_VLAN_TAG_OUTER_VLAN_TAG_ENABLE_MASK 0x200000000 + +/* If set, MAC enables VLAN tag detection using the INNER_VLAN_TAG */ +#define RX_VLAN_TAG_INNER_VLAN_TAG_ENABLE_MASK 0x100000000 + +/* TPID field for Outer VLAN tag */ +#define RX_VLAN_TAG_OUTER_VLAN_TAG_SHIFT 16 +#define RX_VLAN_TAG_OUTER_VLAN_TAG_MASK 0xffff0000 + +/* TPID field for Inner VLAN tag */ +#define RX_VLAN_TAG_INNER_VLAN_TAG_SHIFT 0 +#define RX_VLAN_TAG_INNER_VLAN_TAG_MASK 0xffff + + +/* + * Register + * + * Control for LSS (ordered set) messages + */ +#define XPORT_XLMAC_CORE_RX_LSS_CTRL_REG 0x50 + +/* + * If set, the Receive Pause, PFC & LLFC timers are reset whenever the link + * status is down, or local or remote faults are received. +*/ +#define RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_MASK 0x80 + +/* + * This bit determines the way MAC handles data during link interruption + * state, if LINK_INTERRUPTION_DISABLE is reset. + * If set, during link interruption state, MAC drops transmit-data + * (statistics are updated) and sends IDLEs on the wire. + * If reset, transmit data is stalled in the internal FIFO under link + * interruption state. +*/ +#define RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_MASK 0x40 + +/* + * This bit determines the way MAC handles data during remote fault state, + * if REMOTE_FAULT_DISABLE is reset. + * If set, during remote fault state, MAC drops transmit-data (statistics + * are updated) and sends IDLEs on the wire. + * If reset, transmit data is stalled in the internal FIFO under remote + * fault state. +*/ +#define RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_MASK 0x20 + +/* + * This bit determines the way MAC handles data during local fault state, + * if LOCAL_FAULT_DISABLE is reset. + * If set, during local fault state, MAC drops transmit-data (statistics + * are updated) and sends remote faults on the wire. + * If reset, transmit data is stalled in the internal FIFO under local + * fault state. +*/ +#define RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_MASK 0x10 + +/* + * This bit determines the transmit response during link interruption + * state. + * The LINK_INTERRUPTION_STATUS bit is always updated irrespective of this + * configuration. + * If set, MAC will continue to transmit data irrespective of + * LINK_INTERRUPTION_STATUS. + * If reset, MAC transmit behavior is governed by + * DROP_TX_DATA_ON_LINK_INTERRUPT configuration. +*/ +#define RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_MASK 0x8 + +/* + * If set, the transmit fault responses are determined from input pins + * rather than internal receive status. + * In this mode, input fault from pins (from a peer MAC) is directly + * relayed on the transmit side of this MAC. + * See specification document for more details. +*/ +#define RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_MASK 0x4 + +/* + * This bit determines the transmit response during remote fault state. + * The REMOTE_FAULT_STATUS bit is always updated irrespective of this + * configuration. + * If set, MAC will continue to transmit data irrespective of + * REMOTE_FAULT_STATUS. + * If reset, MAC transmit behavior is governed by + * DROP_TX_DATA_ON_REMOTE_FAULT configuration. +*/ +#define RX_LSS_CTRL_REMOTE_FAULT_DISABLE_MASK 0x2 + +/* + * This bit determines the transmit response during local fault state. + * The LOCAL_FAULT_STATUS bit is always updated irrespective of this + * configuration. + * If set, MAC will continue to transmit data irrespective of + * LOCAL_FAULT_STATUS. + * If reset, MAC transmit behavior is governed by + * DROP_TX_DATA_ON_LOCAL_FAULT configuration. +*/ +#define RX_LSS_CTRL_LOCAL_FAULT_DISABLE_MASK 0x1 + + +/* + * Register - read-only + * + * Status for RS layer. + * These bits are sticky by nature, and can be cleared by writing to the + * clear register + */ +#define XPORT_XLMAC_CORE_RX_LSS_STATUS_REG 0x58 + +/* + * True when link interruption state is detected as per RS layer state + * machine. + * Sticky bit is cleared by CLEAR_LINK_INTERRUPTION_STATUS. +*/ +#define RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_MASK 0x4 + +/* + * True when remote fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_REMOTE_FAULT_STATUS. +*/ +#define RX_LSS_STATUS_REMOTE_FAULT_STATUS_MASK 0x2 + +/* + * True when local fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_LOCAL_FAULT_STATUS +*/ +#define RX_LSS_STATUS_LOCAL_FAULT_STATUS_MASK 0x1 + + +/* + * Register + * + * Clear the XLMAC_RX_LSS_STATUS register, used for resetting the sticky + * status bits + */ +#define XPORT_XLMAC_CORE_CLEAR_RX_LSS_STATUS_REG 0x60 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * LINK_INTERRUPTION_STATUS bit +*/ +#define CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_MASK 0x4 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * REMOTE_FAULT_STATUS bit +*/ +#define CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_MASK 0x2 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * LOCAL_FAULT_STATUS bit +*/ +#define CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_MASK 0x1 + + +/* + * Register + * + * PAUSE control register This XLMAC core register is 37 bits wide in + * hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_PAUSE_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_PAUSE_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_PAUSE_CTRL_REG 0x68 + +/* + * Pause time value sent in the timer field for XOFF state (unit is 512 + * bit-times) +*/ +#define PAUSE_CTRL_PAUSE_XOFF_TIMER_SHIFT 21 +#define PAUSE_CTRL_PAUSE_XOFF_TIMER_MASK 0x1fffe00000 + +/* Reserved */ +#define PAUSE_CTRL_RSVD_2_MASK 0x100000 + +/* Reserved */ +#define PAUSE_CTRL_RSVD_1_MASK 0x80000 + +/* + * When set, enables detection of pause frames in the receive direction and + * pause/resume the transmit data path +*/ +#define PAUSE_CTRL_RX_PAUSE_EN_MASK 0x40000 + +/* + * When set, enables the transmission of pause frames whenever there is a + * transition on txbkp input to MAC from MMU +*/ +#define PAUSE_CTRL_TX_PAUSE_EN_MASK 0x20000 + +/* + * When set, enables the periodic re-generation of XOFF pause frames based + * on the interval specified in PAUSE_REFRESH_TIMER +*/ +#define PAUSE_CTRL_PAUSE_REFRESH_EN_MASK 0x10000 + +/* + * This field specifies the interval at which pause frames are re-generated + * during XOFF state, provided PAUSE_REFRESH_EN is set (unit is 512 + * bit-times) +*/ +#define PAUSE_CTRL_PAUSE_REFRESH_TIMER_SHIFT 0 +#define PAUSE_CTRL_PAUSE_REFRESH_TIMER_MASK 0xffff + + +/* + * Register + * + * PFC control register This XLMAC core register is 38 bits wide in + * hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_PFC_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_PFC_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_PFC_CTRL_REG 0x70 + +/* When set, enables the transmission of PFC frames */ +#define PFC_CTRL_TX_PFC_EN_MASK 0x2000000000 + +/* + * When set, enables detection of PFC frames in the receive direction and + * generation of COSMAPs to MMU based on incoming timer values +*/ +#define PFC_CTRL_RX_PFC_EN_MASK 0x1000000000 + +/* + * When set, enables the generation of receive and transmit PFC events into + * the corresponding statistics vectors (RSV and TSV) +*/ +#define PFC_CTRL_PFC_STATS_EN_MASK 0x800000000 + +/* Reserved */ +#define PFC_CTRL_RSVD_MASK 0x400000000 + +/* + * When set, forces the MAC to generate an XON indication to the MMU for + * all classes of service in the receive direction +*/ +#define PFC_CTRL_FORCE_PFC_XON_MASK 0x200000000 + +/* + * When set, enables the periodic re-generation of PFC frames based on the + * interval specified in PFC_REFRESH_TIMER +*/ +#define PFC_CTRL_PFC_REFRESH_EN_MASK 0x100000000 + +/* + * Pause time value sent in the timer field for classes in XOFF state (unit + * is 512 bit-times) +*/ +#define PFC_CTRL_PFC_XOFF_TIMER_SHIFT 16 +#define PFC_CTRL_PFC_XOFF_TIMER_MASK 0xffff0000 + +/* + * This field specifies the interval at which PFC frames are re-generated + * for a class of service in XOFF state, provided PFC_REFRESH_EN is set + * (unit is 512 bit-times) +*/ +#define PFC_CTRL_PFC_REFRESH_TIMER_SHIFT 0 +#define PFC_CTRL_PFC_REFRESH_TIMER_MASK 0xffff + + +/* + * Register + * + * PFC Ethertype + */ +#define XPORT_XLMAC_CORE_PFC_TYPE_REG 0x78 + +/* + * This field is used in the ETHERTYPE field of the PFC frame that is + * generated and transmitted by the MAC and also used for detection in the + * receive direction +*/ +#define PFC_TYPE_PFC_ETH_TYPE_SHIFT 0 +#define PFC_TYPE_PFC_ETH_TYPE_MASK 0xffff + + +/* + * Register + * + * PFC Opcode + */ +#define XPORT_XLMAC_CORE_PFC_OPCODE_REG 0x80 + +/* + * This field is used in the OPCODE field of the PFC frame that is + * generated and transmitted by the MAC and also used for detection in the + * receive direction +*/ +#define PFC_OPCODE_PFC_OPCODE_SHIFT 0 +#define PFC_OPCODE_PFC_OPCODE_MASK 0xffff + + +/* + * Register + * + * PFC Destination Address. + * This XLMAC core register is 48 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_PFC_DA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_PFC_DA_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_PFC_DA_REG 0x88 + +/* + * This field is used in the destination-address field of the PFC frame + * that is generated and transmitted by the MAC and also used for detection + * in the receive direction +*/ +#define PFC_DA_PFC_MACDA_SHIFT 0 +#define PFC_DA_PFC_MACDA_MASK 0xffffffffffff + + +/* + * Register + * + * LLFC Control Register + */ +#define XPORT_XLMAC_CORE_LLFC_CTRL_REG 0x90 + +/* + * This field indicates the minimum Inter Message Gap that is enforced by + * the MAC between 2 LLFC messages in the transmit direction (unit is 1 + * credit) +*/ +#define LLFC_CTRL_LLFC_IMG_SHIFT 6 +#define LLFC_CTRL_LLFC_IMG_MASK 0x3fc0 + +/* When set, LLFC CRC computation does not include the SOM character */ +#define LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_MASK 0x20 + +/* + * When set, disables the CRC check for LLFC messages in the receive + * direction +*/ +#define LLFC_CTRL_LLFC_CRC_IGNORE_MASK 0x10 + +/* + * When LLFC_IN_IPG_ONLY is reset, the mode of transmission of LLFC + * messages is controlled by this bit depending upon whether the LLFC + * message is XON or XOFF When LLFC_CUT_THROUGH_MODE is reset, all LLFC + * messages are transmitted pre-emptively (within a packet) When + * LLFC_CUT_THROUGH_MODE is set, only XOFF LLFC messages are transmitted + * pre-emptively, XON LLFC messages are transmitted during IPG +*/ +#define LLFC_CTRL_LLFC_CUT_THROUGH_MODE_MASK 0x8 + +/* + * When set, all LLFC messages are transmitted during IPG When reset, the + * mode of insertion of LLFC messages is controlled by + * LLFC_CUT_THROUGH_MODE +*/ +#define LLFC_CTRL_LLFC_IN_IPG_ONLY_MASK 0x4 + +/* + * When set, enables processing of LLFC frames in the receive direction and + * generation of COSMAPs to MMU +*/ +#define LLFC_CTRL_RX_LLFC_EN_MASK 0x2 + +/* + * When set, enables the generation and transmission of LLFC frames in the + * transmit direction +*/ +#define LLFC_CTRL_TX_LLFC_EN_MASK 0x1 + + +/* + * Register + * + * Programmable TX LLFC Message fields. + */ +#define XPORT_XLMAC_CORE_TX_LLFC_MSG_FIELDS_REG 0x98 + +/* + * Pause time value sent in the XOFF_TIME field of the outgoing LLFC + * message +*/ +#define TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_SHIFT 12 +#define TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_MASK 0xffff000 + +/* + * This field is used in the FC_OBJ_LOGICAL field of the outgoing LLFC + * message +*/ +#define TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_SHIFT 8 +#define TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_MASK 0xf00 + +/* + * This field is used in the MSG_TYPE_LOGICAL field of the outgoing LLFC + * message +*/ +#define TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_SHIFT 0 +#define TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_MASK 0xff + + +/* + * Register + * + * Programmable RX LLFC Message fields + */ +#define XPORT_XLMAC_CORE_RX_LLFC_MSG_FIELDS_REG 0xa0 + +/* + * This value is compared against the FC_OBJ_PHYSICAL field of an incoming + * LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_SHIFT 20 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_MASK 0xf00000 + +/* + * This value is compared against the MSG_TYPE_PHYSICAL field of an + * incoming LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_SHIFT 12 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_MASK 0xff000 + +/* + * This value is compared against the FC_OBJ_LOGICAL field of an incoming + * LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_SHIFT 8 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_MASK 0xf00 + +/* + * This value is compared against the MSG_TYPE_LOGICAL field of an incoming + * LLFC message in order to decode the message +*/ +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_SHIFT 0 +#define RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_MASK 0xff + + +/* + * Register - read-only + * + * The TimeStamp value of the Tx two-step packets. + * This XLMAC core register is 49 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_TIMESTAMP_FIFO_DATA) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + */ +#define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_DATA_REG 0xa8 + +/* Active high qualifier for the TimeStamp & SEQUENCE_ID fields. */ +#define TX_TIMESTAMP_FIFO_DATA_TS_ENTRY_VALID_MASK 0x1000000000000 + +/* + * The Sequence Identifier extracted from the Timesync packet based on the + * header offset +*/ +#define TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_SHIFT 32 +#define TX_TIMESTAMP_FIFO_DATA_SEQUENCE_ID_MASK 0xffff00000000 + +/* The TimeStamp value of the Tx two-step enabled packet. */ +#define TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_SHIFT 0 +#define TX_TIMESTAMP_FIFO_DATA_TIME_STAMP_MASK 0xffffffff + + +/* + * Register - read-only + * + * Tx TimeStamp FIFO Status. + */ +#define XPORT_XLMAC_CORE_TX_TIMESTAMP_FIFO_STATUS_REG 0xb0 + +/* + * Number of TX time stamps currently buffered in TX Time Stamp FIFO. + * A valid entry is popped out whenever XLMAC_TX_TIMESTMAP_FIFO_DATA is + * read +*/ +#define TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_SHIFT 0 +#define TX_TIMESTAMP_FIFO_STATUS_ENTRY_COUNT_MASK 0x7 + + +/* + * Register - read-only + * + * FIFO status register. + * These bits (except LINK_STATUS) are sticky by nature, and can be cleared + * by writing to the clear register. + */ +#define XPORT_XLMAC_CORE_FIFO_STATUS_REG 0xb8 + +/* + * This bit indicates the link status used by XLMAC EEE and lag-failover + * state machines. + * This reflects the live status of the link as seen by the MAC. + * If set, indicates that link is active. +*/ +#define FIFO_STATUS_LINK_STATUS_MASK 0x100 + +/* If set, indicates RX packet fifo overflow */ +#define FIFO_STATUS_RX_PKT_OVERFLOW_MASK 0x80 + +/* If set, indicates overflow occurred in TX two-step Time Stamp FIFO */ +#define FIFO_STATUS_TX_TS_FIFO_OVERFLOW_MASK 0x40 + +/* If set, indicates TX LLFC message fifo overflow */ +#define FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_MASK 0x20 + +/* Reserved */ +#define FIFO_STATUS_RSVD_2_MASK 0x10 + +/* If set, indicates tx packet fifo overflow */ +#define FIFO_STATUS_TX_PKT_OVERFLOW_MASK 0x8 + +/* If set, indicates tx packet fifo underflow */ +#define FIFO_STATUS_TX_PKT_UNDERFLOW_MASK 0x4 + +/* If set, indicates rx message fifo overflow */ +#define FIFO_STATUS_RX_MSG_OVERFLOW_MASK 0x2 + +/* Reserved */ +#define FIFO_STATUS_RSVD_1_MASK 0x1 + + +/* + * Register + * + * Clear XLMAC_FIFO_STATUS register, used for resetting the sticky status + * bits + */ +#define XPORT_XLMAC_CORE_CLEAR_FIFO_STATUS_REG 0xc0 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_PKT_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_MASK 0x80 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_TS_FIFO_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_MASK 0x40 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_LLFC_MSG_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_MASK 0x20 + +/* Reserved */ +#define CLEAR_FIFO_STATUS_RSVD_2_MASK 0x10 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_PKT_OVERFLOW status bit. +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_MASK 0x8 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_PKT_UNDERFLOW status bit +*/ +#define CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_MASK 0x4 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_MSG_OVERFLOW status bit +*/ +#define CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_MASK 0x2 + +/* Reserved */ +#define CLEAR_FIFO_STATUS_RSVD_1_MASK 0x1 + + +/* + * Register - read-only + * + * Lag Failover Status. + */ +#define XPORT_XLMAC_CORE_LAG_FAILOVER_STATUS_REG 0xc8 + +/* Reserved */ +#define LAG_FAILOVER_STATUS_RSVD_MASK 0x2 + +/* Set when XLMAC is in lag failover state */ +#define LAG_FAILOVER_STATUS_LAG_FAILOVER_LOOPBACK_MASK 0x1 + + +/* + * Register + * + * Register for EEE Control + */ +#define XPORT_XLMAC_CORE_EEE_CTRL_REG 0xd0 + +/* Reserved */ +#define EEE_CTRL_RSVD_MASK 0x2 + +/* + * When set, enables EEE state machine in the transmit direction and LPI + * detection/prediction in the receive direction +*/ +#define EEE_CTRL_EEE_EN_MASK 0x1 + + +/* + * Register + * + * EEE Timers This XLMAC core register is 64 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_EEE_TIMERS) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_EEE_TIMERS_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_EEE_TIMERS_REG 0xd8 + +/* + * This field controls clock divider used to generate ~1us reference pulses + * used by EEE timers. + * It specifies integer number of clock cycles for 1us reference using + * tsc_clk +*/ +#define EEE_TIMERS_EEE_REF_COUNT_SHIFT 48 +#define EEE_TIMERS_EEE_REF_COUNT_MASK 0xffff000000000000 + +/* + * This is the duration for which MAC must wait to go back to ACTIVE state + * from LPI state when it receives packet/flow-control frames for + * transmission. + * Unit is micro seconds +*/ +#define EEE_TIMERS_EEE_WAKE_TIMER_SHIFT 32 +#define EEE_TIMERS_EEE_WAKE_TIMER_MASK 0xffff00000000 + +/* + * This is the duration for which the MAC must wait in EMPTY state before + * transitioning to LPI state. + * Unit is micro seconds +*/ +#define EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_SHIFT 0 +#define EEE_TIMERS_EEE_DELAY_ENTRY_TIMER_MASK 0xffffffff + + +/* + * Register + * + * EEE One Second Link Status Timer + */ +#define XPORT_XLMAC_CORE_EEE_1_SEC_LINK_STATUS_TIMER_REG 0xe0 + +/* + * This is the duration for which EEE FSM must wait when Link status + * becomes active before transitioning to ACTIVE state. + * Unit is micro seconds +*/ +#define EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_SHIFT 0 +#define EEE_1_SEC_LINK_STATUS_TIMER_ONE_SECOND_TIMER_MASK 0xffffff + + +/* + * Register + * + * HiGig2 and HiHig+ header register - MS bytes This XLMAC core register is + * 64 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_HIGIG_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_HIGIG_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_HIGIG_HDR_0_REG 0xe8 + +/* + * In HiGig2 mode, this register contains bits 127: + * 64 of 16-byte HiGig2 header. + * In HiGig+ mode, bits 31: + * 0 of this register contains bits 95: + * 64 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * pause and PFC frames in the transmit direction. +*/ +#define HIGIG_HDR_0_HIGIG_HDR_0_SHIFT 0 +#define HIGIG_HDR_0_HIGIG_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * HiGig2 and HiHig+ header register - LS bytes This XLMAC core register is + * 64 bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_HIGIG_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_HIGIG_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_HIGIG_HDR_1_REG 0xf0 + +/* + * In HiGig2 mode, this register contains bits 63: + * 0 of 16-byte HiGig2 header. + * In HiGig+ mode, this register contains bits 63: + * 0 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * pause and PFC frames in the transmit direction. +*/ +#define HIGIG_HDR_1_HIGIG_HDR_1_SHIFT 0 +#define HIGIG_HDR_1_HIGIG_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * MAC EEE control in GMII mode. + */ +#define XPORT_XLMAC_CORE_GMII_EEE_CTRL_REG 0xf8 + +/* When set, enables LPI prediction */ +#define GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_MASK 0x10000 + +/* + * If GMII_LPI_PREDICT_MODE_EN is set then this field defines the number of + * IDLEs to be received before allowing LPIs to be sent to Link Partner +*/ +#define GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_SHIFT 0 +#define GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_MASK 0xffff + + +/* + * Register + * + * Timestamp Adjust register. + * Refer specification document for more details + */ +#define XPORT_XLMAC_CORE_TIMESTAMP_ADJUST_REG 0x100 + +/* + * When set, indicates that the checksum offset is referenced by input port + * checksumoffset, else checksum offset is referenced by txtsoffset +*/ +#define TIMESTAMP_ADJUST_TS_USE_CS_OFFSET_MASK 0x8000 + +/* + * This is an unsigned value to account for synchronization delay of TS + * timer from TS clk to TSC_CLK domain. + * Unit is 1ns. + * The latency is [2. + * 5 TSC_CLK period + 1 TS_CLK period]. +*/ +#define TIMESTAMP_ADJUST_TS_TSTS_ADJUST_SHIFT 9 +#define TIMESTAMP_ADJUST_TS_TSTS_ADJUST_MASK 0x7e00 + +/* + * This is a signed value which is 2s complement added to synchronized + * timestamp to account for MAC pipeline delay in OSTS. + * Unit is 1ns The latency is [6 TSC_CLK period + 1 TS_CLK period ]. +*/ +#define TIMESTAMP_ADJUST_TS_OSTS_ADJUST_SHIFT 0 +#define TIMESTAMP_ADJUST_TS_OSTS_ADJUST_MASK 0x1ff + + +/* + * Register + * + * Timestamp Byte Adjust register. + * Refer specification document for more details + */ +#define XPORT_XLMAC_CORE_TIMESTAMP_BYTE_ADJUST_REG 0x108 + +/* + * When set, enables byte based adjustment for receive timestamp capture. + * This should be enabled in GMII/MII modes only. +*/ +#define TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_EN_MASK 0x200000 + +/* + * This is a per byte unsigned value which is subtracted from sampled + * timestamp to account for timestamp jitter due to wider MSBUS interface. + * Unit is 1ns +*/ +#define TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_SHIFT 11 +#define TIMESTAMP_BYTE_ADJUST_RX_TIMER_BYTE_ADJUST_MASK 0x1ff800 + +/* + * When set, enables byte based adjustment for transmit timestamp capture + * (OSTS and TSTS). + * This should be enabled in GMII/MII modes only. +*/ +#define TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_EN_MASK 0x400 + +/* + * This is a per byte unsigned value which is added to sampled timestamp to + * account for timestamp jitter due to wider MSBUS interface. + * Unit is 1ns +*/ +#define TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_SHIFT 0 +#define TIMESTAMP_BYTE_ADJUST_TX_TIMER_BYTE_ADJUST_MASK 0x3ff + + +/* + * Register + * + * Tx CRC corrupt control register This XLMAC core register is 35 bits wide + * in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_TX_CRC_CORRUPT_CTRL) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_TX_CRC_CORRUPT_CTRL_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_TX_CRC_CORRUPT_CTRL_REG 0x110 + +/* + * Programmable CRC value used to corrupt the Tx CRC. + * The computed CRC is replaced by this programmed CRC value based on + * TX_CRC_CORRUPTION_MODE +*/ +#define TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_SHIFT 3 +#define TX_CRC_CORRUPT_CTRL_PROG_TX_CRC_MASK 0x7fffffff8 + +/* + * When set, the computed CRC is replaced with PROG_TX_CRC, else computed + * CRC is inverted +*/ +#define TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPTION_MODE_MASK 0x4 + +/* + * When set, MAC enables the CRC corruption on the transmitted packets. + * Mode of corruption is determined by TX_CRC_CORRUPTION_MODE +*/ +#define TX_CRC_CORRUPT_CTRL_TX_CRC_CORRUPT_EN_MASK 0x2 + +/* + * When set, this bit causes packets with TXERR to corrupt the CRC of the + * packet when it is transmitted. + * When reset, packets with TXERR are transmitted with /E/ termination + * character (/T/ is not enforced); packet CRC is unaffected +*/ +#define TX_CRC_CORRUPT_CTRL_TX_ERR_CORRUPTS_CRC_MASK 0x1 + + +/* + * Register + * + * Transmit E2EFC/E2ECC control register + */ +#define XPORT_XLMAC_CORE_E2E_CTRL_REG 0x118 + +/* + * When set, dual modid is enabled for E2EFC (Only 32 ports IBP is sent + * out). + * When reset, single modid is enabled for E2EFC (64 ports IBP is sent) +*/ +#define E2E_CTRL_E2EFC_DUAL_MODID_EN_MASK 0x10 + +/* + * When set, legacy E2ECC stage2 loading enabled (single stage2 buffer for + * all ports). + * When reset, new E2ECC stage2 loading enabled (per port stage2 buffer) +*/ +#define E2E_CTRL_E2ECC_LEGACY_IMP_EN_MASK 0x8 + +/* + * When set, dual modid is enabled for E2ECC. + * When reset, single modid is enabled for E2ECC +*/ +#define E2E_CTRL_E2ECC_DUAL_MODID_EN_MASK 0x4 + +/* + * When set, E2ECC/FC frames are not transmitted during pause state. + * When reset, E2ECC/FC frames are transmitted even during pause state + * similar to other flow control frames. +*/ +#define E2E_CTRL_HONOR_PAUSE_FOR_E2E_MASK 0x2 + +/* When set, MAC enables E2EFC/E2ECC frame generation and transmission. */ +#define E2E_CTRL_E2E_ENABLE_MASK 0x1 + + +/* + * Register + * + * E2ECC module header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_MODULE_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_MODULE_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_0_REG 0x120 + +/* + * In HiGig2 mode, this register contains bits 127: + * 64 of 16-byte HiGig2 header. + * In HiGig+ mode, this register contains bits 95: + * 32 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2ECC frames in the transmit direction. +*/ +#define E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_SHIFT 0 +#define E2ECC_MODULE_HDR_0_E2ECC_MODULE_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2ECC module header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_MODULE_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_MODULE_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_MODULE_HDR_1_REG 0x128 + +/* + * In HiGig2 mode, this register contains bits 63: + * 0 of 16-byte HiGig2 header. + * In HiGig+ mode, bits 63: + * 32 of this register contains bits 31: + * 0 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2ECC frames in the transmit direction. +*/ +#define E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_SHIFT 0 +#define E2ECC_MODULE_HDR_1_E2ECC_MODULE_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2ECC Ethernet header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_DATA_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_DATA_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_0_REG 0x130 + +/* + * This register contains bits 127: + * 64 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2ECC frames in the transmit direction. +*/ +#define E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_SHIFT 0 +#define E2ECC_DATA_HDR_0_E2ECC_DATA_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2ECC Ethernet header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2ECC_DATA_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2ECC_DATA_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2ECC_DATA_HDR_1_REG 0x138 + +/* + * This register contains bits 63: + * 0 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2ECC frames in the transmit direction. +*/ +#define E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_SHIFT 0 +#define E2ECC_DATA_HDR_1_E2ECC_DATA_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC module header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_MODULE_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_MODULE_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_0_REG 0x140 + +/* + * In HiGig2 mode, this register contains bits 127: + * 64 of 16-byte HiGig2 header. + * In HiGig+ mode, this register contains bits 95: + * 32 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2EFC frames in the transmit direction. +*/ +#define E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_SHIFT 0 +#define E2EFC_MODULE_HDR_0_E2EFC_MODULE_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC module header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_MODULE_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_MODULE_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_MODULE_HDR_1_REG 0x148 + +/* + * In HiGig2 mode, this register contains bits 63: + * 0 of 16-byte HiGig2 header. + * In HiGig+ mode, bits 63: + * 32 of this register contains bits 31: + * 0 of 12-byte HiGig+ header. + * This field is used for constructing the module header for HiGig2/HiGig+ + * E2EFC frames in the transmit direction. +*/ +#define E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_SHIFT 0 +#define E2EFC_MODULE_HDR_1_E2EFC_MODULE_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC Ethernet header register - MS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_DATA_HDR_0) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_DATA_HDR_0_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_0_REG 0x150 + +/* + * This register contains bits 127: + * 64 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2EFC frames in the transmit direction. +*/ +#define E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_SHIFT 0 +#define E2EFC_DATA_HDR_0_E2EFC_DATA_HDR_0_MASK 0xffffffffffffffff + + +/* + * Register + * + * E2EFC Ethernet header register - LS bytes This XLMAC core register is 64 + * bits wide in hardware. + * LPORT register reads and writes are however 32 bits per transaction. + * When reading from this address, higher XLMAC register bits are copied to + * XLMAC0 32-bit Direct Access Data Read Register, and can subsequently be + * obtained by reading from that register. + * Similarly, when writing to this address, higher XLMAC register bits are + * taken from XLMAC0 32-bit Direct Access Data Write Register, so it is + * important to ensure proper value for the higher bits is present in that + * register prior to writing to this (. + * .. + * XLMAC_E2EFC_DATA_HDR_1) register. + * Alternatively, Indirect Access mechanism can be used to access XLMAC + * core registers (see XLMACx Indirect Access registers). + * NOTE: + * THIS REGISTER HAS AN ALTERNATIVE/OVERLAY FIELD LAYOUT VIEW - see + * Type_XLMAC_E2EFC_DATA_HDR_1_OVERLAY in lport_xlmac_core_regtypes. + * rdb + */ +#define XPORT_XLMAC_CORE_E2EFC_DATA_HDR_1_REG 0x158 + +/* + * This register contains bits 63: + * 0 of 16-byte IEEE header (DA + SA + Length/Type + Opcode). + * This field is used for constructing the Ethernet header for + * HiGig2/HiGig+ E2EFC frames in the transmit direction. +*/ +#define E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_SHIFT 0 +#define E2EFC_DATA_HDR_1_E2EFC_DATA_HDR_1_MASK 0xffffffffffffffff + + +/* + * Register - read-only + * + * XLMAC TX FIFO Cell Count register + */ +#define XPORT_XLMAC_CORE_TXFIFO_CELL_CNT_REG 0x160 + +/* + * Number of cell counts in XLMAC TX FIFO. + * Should range from 0 to 32 for XLMAC core in single port mode, or 0 to 16 + * if XLMAC core is in dual port mode, or 0 to 8 if XLMAC core is in quad + * port mode during traffic. + * This should reset to 0 after the traffic has stopped for all port modes. +*/ +#define TXFIFO_CELL_CNT_CELL_CNT_SHIFT 0 +#define TXFIFO_CELL_CNT_CELL_CNT_MASK 0x3f + + +/* + * Register - read-only + * + * XLMAC TX FIFO Cell Request Count Register + */ +#define XPORT_XLMAC_CORE_TXFIFO_CELL_REQ_CNT_REG 0x168 + +/* + * Number of cell requests made to Egress Pipeline. + * Should range from 0 to 32 for XLMAC core in single port mode, or 0 to 16 + * if XLMAC core is in dual port mode, or 0 to 8 if XLMAC core is in quad + * port mode during traffic. + * This should saturate at the maximum value for the corresponding port + * mode after traffic has stopped. +*/ +#define TXFIFO_CELL_REQ_CNT_REQ_CNT_SHIFT 0 +#define TXFIFO_CELL_REQ_CNT_REQ_CNT_MASK 0x3f + + +/* + * Register + * + * Memory Control register + */ +#define XPORT_XLMAC_CORE_MEM_CTRL_REG 0x170 + +/* Test mode configuration of Tx CDC Memory */ +#define MEM_CTRL_TX_CDC_MEM_CTRL_TM_SHIFT 12 +#define MEM_CTRL_TX_CDC_MEM_CTRL_TM_MASK 0xfff000 + +/* Test mode configuration of Rx CDC Memory. */ +#define MEM_CTRL_RX_CDC_MEM_CTRL_TM_SHIFT 0 +#define MEM_CTRL_RX_CDC_MEM_CTRL_TM_MASK 0xfff + + +/* + * Register + * + * XLMAC memories ECC control register + */ +#define XPORT_XLMAC_CORE_ECC_CTRL_REG 0x178 + +/* When set, MAC enables Tx CDC memory ECC logic */ +#define ECC_CTRL_TX_CDC_ECC_CTRL_EN_MASK 0x2 + +/* When set, MAC enables Rx CDC memory ECC logic */ +#define ECC_CTRL_RX_CDC_ECC_CTRL_EN_MASK 0x1 + + +/* + * Register + * + * XLMAC memories double bit error control register + */ +#define XPORT_XLMAC_CORE_ECC_FORCE_DOUBLE_BIT_ERR_REG 0x180 + +/* + * Tx CDC memory force double bit error enable. + * The LSB 2 bits will be inverted at the next memory read. + * This should never be asserted simultaneously with + * TX_CDC_FORCE_SINGLE_BIT_ERR. + * In order to inject double bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_DOUBLE_BIT_ERR_TX_CDC_FORCE_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * Rx CDC memory force double bit error enable. + * The LSB 2 bits will be inverted at the next memory read. + * This should never be asserted simultaneously with force + * RX_CDC_FORCE_SINGLE_BIT_ERR. + * In order to inject double bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_DOUBLE_BIT_ERR_RX_CDC_FORCE_DOUBLE_BIT_ERR_MASK 0x1 + + +/* + * Register + * + * XLMAC memories single bit error control register + */ +#define XPORT_XLMAC_CORE_ECC_FORCE_SINGLE_BIT_ERR_REG 0x188 + +/* + * Tx CDC memory force single bit error enable. + * The LSB 1 bit will be inverted at the next memory read. + * This should never be asserted simultaneously with + * TX_CDC_FORCE_DOUBLE_BIT_ERR. + * In order to inject single bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_SINGLE_BIT_ERR_TX_CDC_FORCE_SINGLE_BIT_ERR_MASK 0x2 + +/* + * Rx CDC memory force single bit error enable. + * The LSB 1 bit will be inverted at the next memory read. + * This should never be asserted simultaneously with + * RX_CDC_FORCE_DOUBLE_BIT_ERR. + * In order to inject single bit error again, this bit needs to be written + * to 0 before being re-written to 1. +*/ +#define ECC_FORCE_SINGLE_BIT_ERR_RX_CDC_FORCE_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * Rx CDC memory ECC status register. + * These bits are sticky by nature, and can be cleared by writing to the + * clear register. + */ +#define XPORT_XLMAC_CORE_RX_CDC_ECC_STATUS_REG 0x190 + +/* + * This status bit indicates a double bit error occurred in the Rx CDC + * memory +*/ +#define RX_CDC_ECC_STATUS_RX_CDC_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * This status bit indicates a single bit error occurred in the Rx CDC + * memory +*/ +#define RX_CDC_ECC_STATUS_RX_CDC_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * Tx CDC memory ECC status register. + * These bits are sticky by nature, and can be cleared by writing to the + * clear register. + */ +#define XPORT_XLMAC_CORE_TX_CDC_ECC_STATUS_REG 0x198 + +/* + * This status bit indicates a double bit error occurred in the Tx CDC + * memory +*/ +#define TX_CDC_ECC_STATUS_TX_CDC_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * This status bit indicates a single bit error occurred in the Tx CDC + * memory +*/ +#define TX_CDC_ECC_STATUS_TX_CDC_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register + * + * Clear ECC status register, used to reset the sticky status bits + */ +#define XPORT_XLMAC_CORE_CLEAR_ECC_STATUS_REG 0x1a0 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_CDC_DOUBLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_TX_CDC_DOUBLE_BIT_ERR_MASK 0x8 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * TX_CDC_SINGLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_TX_CDC_SINGLE_BIT_ERR_MASK 0x4 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_CDC_DOUBLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_RX_CDC_DOUBLE_BIT_ERR_MASK 0x2 + +/* + * A rising edge on this register bit (0->1), clears the sticky + * RX_CDC_SINGLE_BIT_ERR status bit +*/ +#define CLEAR_ECC_STATUS_CLEAR_RX_CDC_SINGLE_BIT_ERR_MASK 0x1 + + +/* + * Register - read-only + * + * XLMAC interrupt status register + */ +#define XPORT_XLMAC_CORE_INTR_STATUS_REG 0x1a8 + +/* Active high qualifier for the TimeStamp & SEQUENCE_ID fields. */ +#define INTR_STATUS_SUM_TS_ENTRY_VALID_MASK 0x2000 + +/* + * True when link interruption state is detected as per RS layer state + * machine. + * Sticky bit is cleared by CLEAR_LINK_INTERRUPTION_STATUS. +*/ +#define INTR_STATUS_SUM_LINK_INTERRUPTION_STATUS_MASK 0x1000 + +/* + * True when remote fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_REMOTE_FAULT_STATUS. +*/ +#define INTR_STATUS_SUM_REMOTE_FAULT_STATUS_MASK 0x800 + +/* + * True when local fault state is detected as per RS layer state machine. + * Sticky bit is cleared by CLEAR_LOCAL_FAULT_STATUS +*/ +#define INTR_STATUS_SUM_LOCAL_FAULT_STATUS_MASK 0x400 + +/* + * This status bit indicates a double bit error occurred in the Rx CDC + * memory +*/ +#define INTR_STATUS_SUM_RX_CDC_DOUBLE_BIT_ERR_MASK 0x200 + +/* + * This status bit indicates a single bit error occurred in the Rx CDC + * memory +*/ +#define INTR_STATUS_SUM_RX_CDC_SINGLE_BIT_ERR_MASK 0x100 + +/* + * This status bit indicates a double bit error occurred in the Tx CDC + * memory +*/ +#define INTR_STATUS_SUM_TX_CDC_DOUBLE_BIT_ERR_MASK 0x80 + +/* + * This status bit indicates a single bit error occurred in the Tx CDC + * memory +*/ +#define INTR_STATUS_SUM_TX_CDC_SINGLE_BIT_ERR_MASK 0x40 + +/* If set, indicates rx message fifo overflow */ +#define INTR_STATUS_SUM_RX_MSG_OVERFLOW_MASK 0x20 + +/* If set, indicates RX packet fifo overflow */ +#define INTR_STATUS_SUM_RX_PKT_OVERFLOW_MASK 0x10 + +/* If set, indicates overflow occurred in TX two-step Time Stamp FIFO */ +#define INTR_STATUS_SUM_TX_TS_FIFO_OVERFLOW_MASK 0x8 + +/* If set, indicates TX LLFC message fifo overflow */ +#define INTR_STATUS_SUM_TX_LLFC_MSG_OVERFLOW_MASK 0x4 + +/* If set, indicates tx packet fifo overflow */ +#define INTR_STATUS_SUM_TX_PKT_OVERFLOW_MASK 0x2 + +/* If set, indicates tx packet fifo underflow */ +#define INTR_STATUS_SUM_TX_PKT_UNDERFLOW_MASK 0x1 + + +/* + * Register + * + * XLMAC interrupt enable register + */ +#define XPORT_XLMAC_CORE_INTR_ENABLE_REG 0x1b0 + +/* If set, SUM_TS_ENTRY_VALID can set mac interrupt. */ +#define INTR_ENABLE_EN_TS_ENTRY_VALID_MASK 0x2000 + +/* If set, SUM_LINK_INTERRUPTION_STATUS can set mac interrupt. */ +#define INTR_ENABLE_EN_LINK_INTERRUPTION_STATUS_MASK 0x1000 + +/* If set, SUM_REMOTE_FAULT_STATUS can set mac interrupt. */ +#define INTR_ENABLE_EN_REMOTE_FAULT_STATUS_MASK 0x800 + +/* If set, SUM_LOCAL_FAULT_STATUS can set mac interrupt. */ +#define INTR_ENABLE_EN_LOCAL_FAULT_STATUS_MASK 0x400 + +/* If set, SUM_RX_CDC_DOUBLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_CDC_DOUBLE_BIT_ERR_MASK 0x200 + +/* If set, SUM_RX_CDC_SINGLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_CDC_SINGLE_BIT_ERR_MASK 0x100 + +/* If set, SUM_TX_CDC_DOUBLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_CDC_DOUBLE_BIT_ERR_MASK 0x80 + +/* If set, SUM_TX_CDC_SINGLE_BIT_ERR can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_CDC_SINGLE_BIT_ERR_MASK 0x40 + +/* If set, SUM_RX_MSG_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_MSG_OVERFLOW_MASK 0x20 + +/* If set, SUM_RX_PKT_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_RX_PKT_OVERFLOW_MASK 0x10 + +/* If set, SUM_TX_TS_FIFO_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_TS_FIFO_OVERFLOW_MASK 0x8 + +/* If set, SUM_TX_LLFC_MSG_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_LLFC_MSG_OVERFLOW_MASK 0x4 + +/* If set, SUM_TX_PKT_OVERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_PKT_OVERFLOW_MASK 0x2 + +/* If set, SUM_TX_PKT_UNDERFLOW can set mac interrupt. */ +#define INTR_ENABLE_EN_TX_PKT_UNDERFLOW_MASK 0x1 + + +/* + * Register - read-only + * + * Version ID register + */ +#define XPORT_XLMAC_CORE_VERSION_ID_REG 0x1b8 + +/* XLMAC IP Version ID - corresponds to RTL/DV label */ +#define VERSION_ID_XLMAC_VERSION_SHIFT 0 +#define VERSION_ID_XLMAC_VERSION_MASK 0xffff + + +#endif /* ! WAN_TOPXPORT_XLMAC_CORE_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_reg.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_reg.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./enet/regs/xport_xlmac_reg.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/enet/regs/xport_xlmac_reg.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,429 @@ +#ifndef WAN_TOPXPORT_XLMAC_REG_H_ +#define WAN_TOPXPORT_XLMAC_REG_H_ + +/* relative to core */ +#define XPORT_XLMAC_REG_OFFSET_0 0x3000 + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_DIR_ACC_DATA_WRITE_REG 0x0 + +/* + * Direct register access data write register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_SHIFT 0 +#define XPORT_XLMAC_DIR_ACC_DATA_WRITE_REG_WRITE_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_DIR_ACC_DATA_READ_REG 0x4 + +/* + * Direct register access data read register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_DIR_ACC_DATA_READ_REG_READ_DATA_SHIFT 0 +#define XPORT_XLMAC_DIR_ACC_DATA_READ_REG_READ_DATA_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_ADDR_0_REG 0x8 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_OFFSET_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_ADDR_0_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_0_REG 0xc + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_0_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_0_REG 0x10 + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_0_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_ADDR_1_REG 0x14 + +/* + * Transaction Status. + * When transaction completes (START_BUSY = 0 after it was set to 1) and + * this bit is set it indicates that register transaction completed with + * error. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_ERR_MASK 0x1000 + +/* + * START_BUSY, Self-clearing. + * CPU writes this bit to 1 in order to initiate indirect register + * read/write transaction. + * When transaction completes hardware clears this bit. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_START_BUSY_MASK 0x800 + +/* + * Register transaction: + * 0 : + * Register Write. + * '1 : + * Register Read. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_R_W_MASK 0x400 + +/* Register Port ID. */ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_SHIFT 8 +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_PORT_ID_MASK 0x300 + +/* + * Register offset. + * Note: + * Bit 7 is ignored by HW. + * Write it as 0. +*/ +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_OFFSET_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_ADDR_1_REG_REG_OFFSET_MASK 0xff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_LOW_1_REG 0x18 + +/* + * Indirect register access data register, bits [31: + * 0]. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_LOW_1_REG_DATA_LOW_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INDIR_ACC_DATA_HIGH_1_REG 0x1c + +/* + * Indirect register access data register, bits [63: + * 32]. + * Used only for 64-bit register accesses. +*/ +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_SHIFT 0 +#define XPORT_XLMAC_INDIR_ACC_DATA_HIGH_1_REG_DATA_HIGH_MASK 0xffffffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_CONFIG_REG 0x20 + +/* Active high XLMAC hard reset. */ +#define XPORT_XLMAC_CONFIG_REG_XLMAC_RESET_MASK 0x200 + +/* + * When set, Rx CDC FIFO read TDM order has same port for 2 consecutive + * cycles. + * This is a strap input for the MAC core and should be changed only while + * hard reset is asserted. +*/ +#define XPORT_XLMAC_CONFIG_REG_RX_DUAL_CYCLE_TDM_EN_MASK 0x100 + +/* + * When set, RX CDC FIFO read TDM generation order for quad mode is + * 0,2,1,3. + * Otherwise, it is 0,1,2,3. + * This is a strap input for the MAC core and should be changed only while + * hard reset is asserted. +*/ +#define XPORT_XLMAC_CONFIG_REG_RX_NON_LINEAR_QUAD_TDM_EN_MASK 0x80 + +/* + * Enables non-linear TDM generation on the receive system interface, based + * on data availability in Rx FIFOs. + * 0 : + * Flex TDM Enabled. + * 1 : + * Flex TDM Disabled. +*/ +#define XPORT_XLMAC_CONFIG_REG_RX_FLEX_TDM_ENABLE_MASK 0x40 + +/* + * Number of ports supported by XLMAC. + * 000 : + * Quad Port. + * All ports are used. + * 001 : + * Tri-Port. + * Ports 0, 1 and 2 are used. + * 010 : + * Tri-Port. + * Ports 0, 2 and 3 are used. + * 011 : + * Dual Port. + * Port 0 and 2 are used. + * 1xx : + * Single Port. + * Port 0 is used. + * Note: + * Valid combinations for 63158 are single Port (P0 active) or Quad Port + * (P0 and/or P1 active). +*/ +#define XPORT_XLMAC_CONFIG_REG_MAC_MODE_SHIFT 3 +#define XPORT_XLMAC_CONFIG_REG_MAC_MODE_MASK 0x38 + +/* + * OSTS time-stamping disable. + * 0 : + * OSTS Enabled. + * 1 : + * OSTS Disabled. +*/ +#define XPORT_XLMAC_CONFIG_REG_OSTS_TIMER_DISABLE_MASK 0x4 + +/* + * Bypasses transmit OSTS functionality. + * When set, reduces Tx path latency. + * 0 : + * Do not bypass transmit OSTS function. + * 1 : + * Bypass transmit OSTS function. + * XLMAC must be reset for this bit to take effect. +*/ +#define XPORT_XLMAC_CONFIG_REG_BYPASS_OSTS_MASK 0x2 + +/* + * 1588 Egress Time-stamping mode. + * 0 : + * Legacy, sign extended 32-bit timestamp mode. + * 1 : + * 48-bit timestamp mode. + * XLMAC must be reset for this bit to take effect. +*/ +#define XPORT_XLMAC_CONFIG_REG_EGR_1588_TIMESTAMPING_MODE_MASK 0x1 + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_INTERRUPT_CHECK_REG 0x24 + +/* + * Each bit of this field corresponds to one XLMAC port. + * SW should write 1 to the corresponding bit(s) of this field any time + * XLMAC interrupt is in use and all events obtained by reading XLMAC + * status register are serviced and corresponding statuses cleared. + * Prevents XLMAC interrupt race condition. +*/ +#define XPORT_XLMAC_INTERRUPT_CHECK_REG_XLMAC_INTR_CHECK_SHIFT 0 +#define XPORT_XLMAC_INTERRUPT_CHECK_REG_XLMAC_INTR_CHECK_MASK 0xf + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_0_RXERR_MASK_REG 0x28 + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_0_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_0_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_1_RXERR_MASK_REG 0x2c + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_1_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_1_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_2_RXERR_MASK_REG 0x30 + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_2_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_2_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_PORT_3_RXERR_MASK_REG 0x34 + +/* + * The RXERR will be set if both the mask bit & the corresponding + * statistics bit in RSV[37: + * 16] are set. + * RSV[23] which indicates good packet received is excluded from generating + * RXERR. +*/ +#define XPORT_XLMAC_PORT_3_RXERR_MASK_REG_RSV_ERR_MASK_SHIFT 0 +#define XPORT_XLMAC_PORT_3_RXERR_MASK_REG_RSV_ERR_MASK_MASK 0x3fffff + + +/* + * Register + * + */ +#define XPORT_XLMAC_REG_RMT_LPBK_CNTRL_REG 0x40 + +/* + * Remote loopback logic starts reading packet data from the loopback FIFO + * only when at least READ_THRESHOLD entries are available in the FIFO. + * Used to prevent XLMAC TX underflow. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_READ_THRESHOLD_SHIFT 8 +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_READ_THRESHOLD_MASK 0x700 + +/* + * TX PORT_ID[1: + * 0]. + * Valid only when TX_PORT_SEL = 1. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_PORT_ID_SHIFT 6 +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_PORT_ID_MASK 0xc0 + +/* + * When set TX PORT_ID[1: + * 0] comes from this registers. + * When cleared TX PORT_ID[1: + * 0] equals RX PORT_ID[1: + * 0]. + * TX PORT_ID[1: + * 0] is used by remote loopback logic to monitor EP credits and to + * indicate outgoing XLMAC port. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_PORT_SEL_MASK 0x20 + +/* + * When set RXERR is propagated to TXERR. + * When cleared TXERR = 0. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_RXERR_EN_MASK 0x10 + +/* When set CRC is corrupted for the outgoing packet. */ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_CRC_ERR_MASK 0x8 + +/* + * TX CRC Mode. + * Encoded as: + * 00 : + * CRC Append. + * 01 : + * CRC Forward. + * 10 : + * CRC Replace. + * 11 : + * Reserved. + * CRC Append mode should be enabled only if XLMAC is programmed to strip + * off CRC. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_CRC_MODE_SHIFT 1 +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_TX_CRC_MODE_MASK 0x6 + +/* + * When set enables XLMAC Remote (RX to TX) loopback. + * XLMAC must be kept in reset while remote loopback is being enabled and + * released from the reset thereafter. +*/ +#define XPORT_XLMAC_RMT_LPBK_CNTRL_REG_RMT_LOOPBACK_EN_MASK 0x1 + + +#endif /* ! WAN_TOPXPORT_XLMAC_REG_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./Makefile linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/Makefile --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/Makefile 2021-03-04 13:20:59.017505610 +0100 @@ -0,0 +1,3 @@ +obj-$(CONFIG_BCM63158_SYSTEMPORT) += bcmsysport_63158.o +obj-$(CONFIG_BCM63158_ENET_RUNNER) += enet/ +obj-$(CONFIG_BCM63158_SF2) += sf2/ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/leds_top_regs.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/leds_top_regs.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/leds_top_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/leds_top_regs.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,8 @@ +#ifndef LEDS_TOP_REGS_H_ +# define LEDS_TOP_REGS_H_ + +#define LEDS_TOP_FLASH_RATE_REG(_x) (0x10 + (_x) * 4) +#define LEDS_TOP_BRIGHTNESS_REG(_x) (0x20 + (_x) * 4) +#define LEDS_TOP_POLARITY_REG (0xc0) + +#endif /* !LEDS_TOP_REGS_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/Makefile linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/Makefile --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/Makefile 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,4 @@ +obj-$(CONFIG_BCM63158_SF2) += bcm63158_sf2.o + +bcm63158_sf2-y += sf2_main.o sf2_fdb.o +bcm63158_sf2-$(CONFIG_DEBUG_FS) += sf2_debug.o diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/serdes_regs.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/serdes_regs.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/serdes_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/serdes_regs.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,7 @@ + +#define BRCM_MIIEXT_BANK 0x1f +# define BRCM_MIIEXT_BANK_MASK 0xfff0 +# define BRCM_MIIEXT_ADDR_RANGE 0xffe0 +# define BRCM_MIIEXT_DEF_BANK 0x8000 +#define BRCM_MIIEXT_OFFSET 0x10 +# define BRCM_MIIEXT_OFF_MASK 0xf diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_debug.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_debug.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_debug.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_debug.c 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,336 @@ +#include +#include +#include "sf2_priv.h" +#include "sf2_regs.h" + +static struct dentry *dbg_root; + +/* + * queues stats functions + */ +static void *queues_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos < SF2_PORT_COUNT) ? pos : NULL; +} + +static void *queues_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return (++(*pos) < SF2_PORT_COUNT) ? pos : NULL; +} + +static void queues_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int queues_seq_show(struct seq_file *s, void *arg) +{ + struct bcm_sf2_priv *priv = s->private; + int i = *(loff_t *)arg; + size_t queue; + u32 cur[SF2_NUM_EGRESS_QUEUES], peak[SF2_NUM_EGRESS_QUEUES]; + u32 v; + + if (!i) { + v = sw_core_readl(priv, SF2_CORE_FC_TOTAL_PEAK_COUNT); + seq_printf(s, "%-20s: %u\n", "total peak", v); + v = sw_core_readl(priv, SF2_CORE_FC_TOTAL_USED_COUNT); + seq_printf(s, "%-20s: %u\n", "total used", v); + seq_printf(s, "%-20s:\n", "usage per port & queue (cur/peak)"); + } + + sw_core_writel(priv, i, SF2_CORE_FC_DIAG_CTRL); + + /* clear latched peak values */ + (void)sw_core_readl(priv, SF2_CORE_FC_PEAK_RX); + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) + (void)sw_core_readl(priv, SF2_CORE_FC_QUEUE_PEAK_COUNT(queue)); + + /* give some time for peak values to adjust */ + msleep(10); + + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) + cur[queue] = sw_core_readl(priv, SF2_CORE_FC_QUEUE_CUR_COUNT(queue)); + + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) { + peak[queue] = sw_core_readw(priv, SF2_CORE_FC_QUEUE_PEAK_COUNT(queue)); + } + + seq_printf(s, "port[%u]: ", i); + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) { + seq_printf(s, "%3d/%-3d ", cur[queue], peak[queue]); + } + + v = sw_core_readw(priv, SF2_CORE_FC_PEAK_RX); + seq_printf(s, "[%3d]\n", v); + return 0; +} + +/* + * dump acb state + */ +static void *acb_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos < SF2_PORT_COUNT - 1) ? pos : NULL; +} + +static void *acb_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return (++(*pos) < SF2_PORT_COUNT - 1) ? pos : NULL; +} + +static void acb_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int acb_seq_show(struct seq_file *s, void *arg) +{ + struct bcm_sf2_priv *priv = s->private; + int i = *(loff_t *)arg; + size_t queue; + + seq_printf(s, "port[%u]: ", i); + for (queue = 0; queue < SF2_NUM_EGRESS_QUEUES; queue++) { + u32 v; + + v = sw_acb_readl(priv, SF2_ACB_QINFLIGHT_REG(i, queue)); + seq_printf(s, "%3d ", v); + } + seq_printf(s, "\n"); + return 0; +} + +static const struct seq_operations queues_seq_ops = { + .start = queues_seq_start, + .next = queues_seq_next, + .stop = queues_seq_stop, + .show = queues_seq_show, +}; + +static const struct seq_operations acb_seq_ops = { + .start = acb_seq_start, + .next = acb_seq_next, + .stop = acb_seq_stop, + .show = acb_seq_show, +}; + +static int queues_open(struct inode *inode, struct file *filep) +{ + struct reg_dump_priv *rpriv = inode->i_private; + int ret; + + ret = seq_open(filep, &queues_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = rpriv; + return 0; +} + +static int acb_open(struct inode *inode, struct file *filep) +{ + struct reg_dump_priv *rpriv = inode->i_private; + int ret; + + ret = seq_open(filep, &acb_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = rpriv; + return 0; +} + +static const struct file_operations queues_fops = { + .owner = THIS_MODULE, + .open = queues_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +static const struct file_operations acb_fops = { + .owner = THIS_MODULE, + .open = acb_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/* + * Dump ARL state + */ + +/* Show ARL table */ +static void *arl_show_seq_start(struct seq_file *s, loff_t *pos) +{ + return (*pos == 0) ? pos : NULL; +} + +static void *arl_show_seq_next(struct seq_file *s, + void __always_unused *v, + loff_t *pos) +{ + return NULL; +} + +static void arl_show_seq_stop(struct seq_file __always_unused *s, + void __always_unused *v) +{ +} + +static int arl_dump_entry(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent, + void *data) +{ + struct seq_file *s = (struct seq_file *)data; + seq_printf(s, "Mac %pM Vid: %u Port: %u Valid: %u Age: %u Static %u\n", + ent->mac, ent->vid, ent->port, ent->is_valid, + ent->is_age, ent->is_static); + return 0; +} + +static int arl_show_seq_show(struct seq_file *s, void *arg) +{ + struct bcm_sf2_priv *priv = s->private; + + seq_printf(s, "ACL: \n"); + sf2_arl_for_each(priv, arl_dump_entry, (void *)s); + return 0; +} + +static const struct seq_operations arl_show_seq_ops = { + .start = arl_show_seq_start, + .next = arl_show_seq_next, + .stop = arl_show_seq_stop, + .show = arl_show_seq_show, +}; + +static int arl_show_open(struct inode *inode, struct file *filep) +{ + struct reg_dump_priv *rpriv = inode->i_private; + int ret; + + ret = seq_open(filep, &arl_show_seq_ops); + if (ret) + return ret; + + ((struct seq_file *)filep->private_data)->private = rpriv; + return 0; +} + +static const struct file_operations arl_show_fops = { + .owner = THIS_MODULE, + .open = arl_show_open, + .read = seq_read, + .llseek = seq_lseek, + .release = seq_release, +}; + +/* Clear ARL entry */ +#define ARL_CLEAR_FILE_SZ 32 +struct arl_clear_file { + struct bcm_sf2_priv *priv; + char buf[ARL_CLEAR_FILE_SZ]; + struct mutex lock; +}; + +static ssize_t arl_clear_parse(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + struct arl_clear_file *fdata = file->private_data; + struct bcm_sf2_priv *priv = fdata->priv; + size_t size; + int ret; + u16 vid; + u8 mac[ETH_ALEN]; + + ret = mutex_lock_interruptible(&fdata->lock); + if (ret) + return ret; + + ret = -EFAULT; + size = min(sizeof(fdata->buf) - 1, len); + if (copy_from_user(fdata->buf, buf, size)) + goto out; + + fdata->buf[size] = '\0'; + ret = sscanf(fdata->buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx %hu", + &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5], + &vid); + if (ret != 7) { + ret = -EINVAL; + goto out; + } + + dev_info(&priv->pdev->dev, "Clearing mac %pM vid %u\n", mac, vid); + sf2_arl_delete(priv, mac, vid); + ret = len; +out: + mutex_unlock(&fdata->lock); + return ret; +} + +static int arl_clear_open(struct inode *inode, struct file *filep) +{ + struct arl_clear_file *fdata; + struct bcm_sf2_priv *priv = inode->i_private; + + fdata = devm_kzalloc(&priv->pdev->dev, sizeof(*fdata), GFP_KERNEL); + if (fdata == NULL) + return -ENOMEM; + + fdata->priv = priv; + mutex_init(&fdata->lock); + filep->private_data = fdata; + return nonseekable_open(inode, filep); +} + +static int arl_clear_release(struct inode *inode, struct file *file) +{ + struct bcm_sf2_priv *priv = inode->i_private; + devm_kfree(&priv->pdev->dev, file->private_data); + return 0; +} + +static const struct file_operations arl_clear_fops = { + .owner = THIS_MODULE, + .open = arl_clear_open, + .write = arl_clear_parse, + .llseek = no_llseek, + .release = arl_clear_release, +}; + +/* + * + */ +void bcm_sf2_dbg_init(struct bcm_sf2_priv *priv) +{ + struct dentry *dir; + dbg_root = debugfs_create_dir("bcm63158_sf2", NULL); + if (IS_ERR_OR_NULL(dbg_root)) + return; + + debugfs_create_file("queues", 0400, dbg_root, priv, &queues_fops); + debugfs_create_file("acb", 0400, dbg_root, priv, &acb_fops); + + dir = debugfs_create_dir("arl", dbg_root); + if (IS_ERR_OR_NULL(dir)) + return; + debugfs_create_file("show", 0400, dir, priv, &arl_show_fops); + debugfs_create_file("clear", 0200, dir, priv, &arl_clear_fops); +} + +/* + * + */ +void bcm_sf2_dbg_exit(void) +{ + if (!IS_ERR_OR_NULL(dbg_root)) + debugfs_remove_recursive(dbg_root); + dbg_root = NULL; +} diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_fdb.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_fdb.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_fdb.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_fdb.c 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,594 @@ +#include +#include +#include +#include +#include +#include + +#include "../../../net/bridge/br_private.h" +#include "sf2_priv.h" +#include "sf2_regs.h" + +#define SF2_FDB_POLL_DELAY_MS 1500 /* 1.5sec */ + +struct sf2_fdb_entry { + struct net_device *port; + struct hlist_node hlist; + struct list_head next; + u16 vid; + u8 mac[ETH_ALEN]; +}; + +/** + * Get FDB hashtable key from MAC address + * + * @mac: MAC address to compute the key from + * + * @return: The computed key + */ +static inline u64 sf2_mac_to_hkey(const u8 *mac) +{ + u64 key = 0; + ether_addr_copy((u8 *)&key, mac); + return key; +} + +/** + * Get FDB hashtable key from ARL info + * + * @ent: ARL info to compute the key from + * + * @return: The computed key + */ +static inline u64 sf2_arl_entry_to_hkey(const struct sf2_arl_entry *ent) +{ + return sf2_mac_to_hkey(ent->mac); +} + +/** + * Create a FDB entry from ARL info + * + * @priv: Common SD2 private object + * @ent: ARL info to create the FDB entry from + * + * @return: The newly created FDB entry on success, error pointer otherwise + */ +static struct sf2_fdb_entry * +sf2_fdb_add_entry(struct bcm_sf2_priv *priv, const struct sf2_arl_entry *ent) +{ + struct sf2_fdb_entry *fe; + u64 key; + + lockdep_assert_held(&priv->fdb.lock); + + fe = devm_kmalloc(&priv->pdev->dev, sizeof(*fe), GFP_KERNEL); + if (!fe) + return ERR_PTR(-ENOMEM); + ether_addr_copy(fe->mac, ent->mac); + fe->vid = ent->vid; + key = sf2_arl_entry_to_hkey(ent); + fe->port = dsa_to_port(priv->ds, ent->port)->slave; + hash_add(priv->fdb.arl_hash, &fe->hlist, key); + list_add(&fe->next, &priv->fdb.cache); + ++priv->fdb.nr_entries; + return fe; +} + +/** + * Cleanup a FDB entry + * + * @priv: Common SD2 private object + * @fe: FDB entry to clean + */ +static void sf2_fdb_del_entry(struct bcm_sf2_priv *priv, + struct sf2_fdb_entry *fe) +{ + lockdep_assert_held(&priv->fdb.lock); + + --priv->fdb.nr_entries; + hash_del(&fe->hlist); + list_del(&fe->next); + devm_kfree(&priv->pdev->dev, fe); +} + +struct sf2_vlan_notify { + enum switchdev_notifier_type type; + struct switchdev_notifier_fdb_info *info; +}; + +/** + * Notify switchdev subsystem to add/remove FDB entry for a specific vlan + * subdevice. + * + * @dev: VLAN subdevice + * @vid: VLAN ID of the subdevice + * @arg: FDB information + */ +static int _sf2_fdb_notify_vlan(struct net_device *dev, int vid, void *arg) +{ + struct sf2_vlan_notify *vn = (struct sf2_vlan_notify *)arg; + + call_switchdev_notifiers(vn->type, dev, &vn->info->info, NULL); + return 0; +} + +/** + * Notify switchdev subsystem to add/remove FDB entry. + * + * @priv: Common SF2 private structure + * @fe: FDB entry information to add to the bridge + * @added: True if the FDB should be added, false otherwise + */ +static void sf2_fdb_notify(struct bcm_sf2_priv *priv, + struct sf2_fdb_entry *fe, bool added) +{ + struct switchdev_notifier_fdb_info info = { + .addr = fe->mac, + .vid = fe->vid, + .offloaded = added, + }; + struct sf2_vlan_notify vnotify = { + .info = &info, + }; + enum switchdev_notifier_type type; + + type = added ? SWITCHDEV_FDB_ADD_TO_BRIDGE : + SWITCHDEV_FDB_DEL_TO_BRIDGE; + call_switchdev_notifiers(type, fe->port, &info.info, NULL); + vnotify.type = type; + + /* + * XXX This is hackish, vlan are not supported yet, but considering a + * setup where vlan is configured but any MAC learnt in one port could + * not be learnt in other port regardless of the packet vlan, vid + * interface could be used. + * + * Update the fdb for such sub interfaces. + */ + vlan_for_each(fe->port, _sf2_fdb_notify_vlan, &vnotify); +} + +struct sf2_arl_fdb_lookup { + struct bcm_sf2_priv *priv; + const struct sf2_arl_entry *ent; + struct net_bridge_fdb_entry *fdb; +}; + +/** + * Find if there is already a permanent FDB entry corresponding to an ARL one + * in the master bridge of a specific vlan sub interface + * + * @dev: Interface to check if a FDB entry matches in its master bridge + * @vid: Interface vlan id (not used) + * @arg: Holds ARL entry informations to match and filled in with found FDB if + * any + * + * @return: 0 if no FDB has been found, 1 otherwise + */ +static int _sf2_arl_find_permanent_fdb_rcu(struct net_device *dev, int vid, + void *arg) +{ + struct net_device *bdev = netdev_master_upper_dev_get(dev); + struct sf2_arl_fdb_lookup *afl = (struct sf2_arl_fdb_lookup *)arg; + struct net_bridge_fdb_entry *fdb; + struct net_bridge *br; + + if (!bdev || !netif_is_bridge_master(bdev)) + return 0; + + br = netdev_priv(bdev); + fdb = br_fdb_find_rcu(br, afl->ent->mac, afl->ent->vid); + if (!fdb || (!fdb->added_by_user && !fdb->is_local)) + return 0; + + afl->fdb = fdb; + return 1; +} + +/** + * Find if there is already a permanent (user added or local) FDB entry + * corresponding to an ARL one in any SF2 port's bridges + * + * @priv: Common SF2 private object + * @ent: ARL entry to search correspond FDB one with + * + * @return: Found FDB entry if any, NULL pointer otherwise + */ +static struct net_bridge_fdb_entry * +sf2_arl_find_permanent_fdb_rcu(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent) +{ + struct net_device *port = dsa_to_port(priv->ds, ent->port)->slave; + struct sf2_arl_fdb_lookup afl = { + .priv = priv, + .ent = ent, + .fdb = NULL, + }; + + _sf2_arl_find_permanent_fdb_rcu(port, 0, &afl); + if (afl.fdb) + goto out; + + vlan_for_each(port, _sf2_arl_find_permanent_fdb_rcu, &afl); +out: + return afl.fdb; +} + +/** + * Synchronize a specific ARL entry with FDB table. This is supposed to be + * called for each ARL entries, at the end of this loop, data should point to + * the actual number of FDB entries that should be purged. + * + * @priv: Common SF2 private structure + * @ent: ARL entry to convert and add into FDB table + * @data: Updated with the number of FDB entry to remove + * + * @return: 0 + */ +static int sf2_arl_sync_entry(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent, + void *data) +{ + unsigned int *nr_purge = (unsigned int *)data; + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct net_bridge_fdb_entry *bfe; + struct net_device *port, *rdev; + const struct dsa_port *dp; + struct sf2_fdb_entry *fe; + u64 key; + + lockdep_assert_held(&fdb->lock); + + if (!ent->is_valid || (ent->port >= SF2_PORT_COUNT)) + goto out; + + dp = dsa_to_port(priv->ds, ent->port); + if ((dp->type != DSA_PORT_TYPE_USER) && + (dp->type != DSA_PORT_TYPE_DSA)) + goto out; + + port = dp->slave; + + rcu_read_lock(); + bfe = sf2_arl_find_permanent_fdb_rcu(priv, ent); + if (bfe) { + rdev = (bfe->dst) ? bfe->dst->dev : NULL; + if (rdev && is_vlan_dev(rdev)) + rdev = vlan_dev_real_dev(rdev); + /* + * Only remove ARL entry if the permanent FDB is for another + * port + */ + if (rdev != port) { + dev_dbg(&priv->pdev->dev, + "Removing ARL entry %pM for permanent FDB\n", + ent->mac); + sf2_arl_delete(priv, ent->mac, ent->vid); + } + rcu_read_unlock(); + goto out; + } + rcu_read_unlock(); + + key = sf2_arl_entry_to_hkey(ent); + hash_for_each_possible(fdb->arl_hash, fe, hlist, key) { + if (ether_addr_equal(ent->mac, fe->mac) && + (ent->vid == fe->vid)) { + /* Move hit beginning of cache list so that at the end + * all unhit fdb will be at in the cache tail */ + list_move(&fe->next, &fdb->cache); + if (!(*nr_purge)) { + dev_err(&priv->pdev->dev, + "FDB cache in weird state"); + goto out; + } + *nr_purge = *nr_purge - 1; + /* update source port */ + if (fe->port != port) { + fe->port = port; + sf2_fdb_notify(priv, fe, true); + } + goto out; + } + } + + /* This is a new entry sync our fdb cache and notify switchdev */ + fe = sf2_fdb_add_entry(priv, ent); + if (IS_ERR(fe)) { + dev_err(&priv->pdev->dev, "Cannot create fdb cache entry"); + goto out; + } + sf2_fdb_notify(priv, fe, true); + +out: + return 0; +} + +/** + * ARL/FDB synchronization worker, called regularly to poll for ARL table + * modifications and synchronize the FDB accordingly. + * + * @work: work structure + */ +static void sf2_fdb_bookkeeping(struct work_struct *work) +{ + struct bcm_sf2_priv *priv = container_of(work, struct bcm_sf2_priv, + fdb.poll_wk.work); + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct sf2_fdb_entry *fe; + unsigned int i, nr_purge = fdb->nr_entries; + u32 lrn = sw_core_readl(priv, SF2_CORE_TOTAL_SA_LRN_CNTR); + + rtnl_lock(); + + if (!lrn) + goto out; + + mutex_lock(&fdb->lock); + + /* Reset SA learn limit */ + sw_core_writel(priv, SF2_CORE_TOTAL_SA_LRN_CNTR_RST_MASK, + SF2_CORE_SA_LRN_CNTR_RST); + + /* + * Insert new sf2 entries and sort the cache in such a way that entries + * that are not in ARL table anymore will be at the end of this cache. + */ + sf2_arl_for_each(priv, sf2_arl_sync_entry, &nr_purge); + + /* + * Purge the first entries which are the ones that are not in sf2's ARL + * table anymore + */ + for (i = 0; i < nr_purge; ++i) { + if (list_empty(&fdb->cache)) { + dev_err(&priv->pdev->dev, "FDB cache in weird state"); + break; + } + fe = list_last_entry(&fdb->cache, struct sf2_fdb_entry, next); + sf2_fdb_notify(priv, fe, false); + sf2_fdb_del_entry(priv, fe); + } + + mutex_unlock(&fdb->lock); +out: + queue_delayed_work(fdb->poll_wq, &fdb->poll_wk, fdb->poll_delay); + rtnl_unlock(); +} + +/** + * Retrieve a SF2 port object from its net_device pointer + * + * @priv: Common SF2 object + * @dev: net_device object to find SF2 port from + * + * @return: The SF2 port if found, NULL pointer otherwise. + */ +static inline struct sf2_port * +sf2_find_port(struct bcm_sf2_priv *priv, struct net_device *dev) +{ + const struct dsa_port *dp; + size_t i; + for (i = 0; i < SF2_PORT_COUNT; ++i) { + dp = dsa_to_port(priv->ds, i); + if (dp->slave == dev) + return &priv->ports[dp->index]; + } + return NULL; +} + +/** + * Miror ARL table according to FDB event worker, called on new FDB event, + * remove an ARL entry if an FDB has been moved from an SF2's port to another + * one not belonging to the switch + * + * @work: Scheduled work data + */ +static void sf2_fdb_update(struct work_struct *work) +{ + struct sf2_switchdev_ev_work *wk = + container_of(work, struct sf2_switchdev_ev_work, work); + struct bcm_sf2_priv *priv = wk->priv; + struct net_device *dev = wk->dev; + struct net_device *rdev = dev; + struct sf2_fdb_entry *fe; + bool found = false; + u64 key; + + rtnl_lock(); + + key = sf2_mac_to_hkey(wk->info.addr); + + if (is_vlan_dev(rdev)) + rdev = vlan_dev_real_dev(rdev); + + mutex_lock(&priv->fdb.lock); + hash_for_each_possible(priv->fdb.arl_hash, fe, hlist, key) { + if (ether_addr_equal(wk->info.addr, fe->mac) && + (wk->info.vid == fe->vid)) { + found = true; + break; + } + } + + if (!found) + goto out; + + /* We are updating the same entry */ + if (unlikely(rdev == fe->port)) { + /* + * If FDB is added_by_user, we should stop synchronizing it with + * ARL + */ + if (wk->info.added_by_user) + sf2_fdb_del_entry(priv, fe); + goto out; + } + + if (unlikely(sf2_find_port(priv, rdev))) { + dev_warn(&priv->pdev->dev, + "FDB is on invalid sf2 port %s should be %s", + dev_name(&dev->dev), dev_name(&fe->port->dev)); + goto out; + } + + /* TODO check for same bridge */ + + dev_dbg(&priv->pdev->dev, "Removing ARL for %pM on port %s", + wk->info.addr, dev_name(&fe->port->dev)); + /* Remove other for other vlan */ + sf2_fdb_notify(priv, fe, false); + sf2_arl_delete(priv, wk->info.addr, wk->info.vid); + sf2_fdb_del_entry(priv, fe); + +out: + mutex_unlock(&priv->fdb.lock); + rtnl_unlock(); + /* + * atomic_set_release is not needed, as release semantic is done by + * previous mutex_unlock() and rtnl_unlock() + */ + atomic_set(&wk->free, 1); + dev_put(dev); +} + +/** + * Switchdev event handler callback + * + * @nb: Switchdev notifier object + * @event: Switchdev event ID + * @ptr: Event data + * + * @return: NOTIFY_DONE on success, NOTIFY_BAD otherwise + */ +static int sf2_switchdev_event(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct net_device *dev = switchdev_notifier_info_to_dev(ptr); + struct switchdev_notifier_fdb_info *fdb_info; + struct sf2_switchdev_ev_work *wk = NULL; + struct bcm_sf2_priv *priv; + int err = NOTIFY_DONE; + size_t i; + + if (event != SWITCHDEV_FDB_ADD_TO_DEVICE) + goto out; + + priv = container_of(nb, struct bcm_sf2_priv, fdb.switchdev_notifier); + fdb_info = container_of(ptr, struct switchdev_notifier_fdb_info, info); + err = NOTIFY_BAD; + + /* Find a usable switchdev event object and take reference on it */ + for (i = 0; i < ARRAY_SIZE(priv->fdb.sd_ev); i++) { + if (atomic_cmpxchg(&priv->fdb.sd_ev[i].free, 1, 0)) { + /* + * atomic_cmpxchg_acquire is not needed as the acquire + * semantic is done by queue_work() + */ + wk = &priv->fdb.sd_ev[i]; + break; + } + } + if (!wk) { + dev_err(&priv->pdev->dev, + "No free switchdev event object found"); + goto out; + } + wk->priv = priv; + wk->dev = dev; + memcpy(&wk->info, fdb_info, sizeof(wk->info)); + ether_addr_copy((u8 *)wk->info.addr, fdb_info->addr); + + /* Do not free dev in the meantime between now and sf2_fdb_update */ + dev_hold(dev); + INIT_WORK(&wk->work, sf2_fdb_update); + queue_work(priv->fdb.update_wq, &wk->work); + + err = NOTIFY_DONE; +out: + return err; +} + +/** + * Init fdb management structure and start ARL polling worker + * + * @priv: Common SF2 private structure to initialize fdb from + * @return: 0 on success, negative number otherwise + */ +int sf2_fdb_init(struct bcm_sf2_priv *priv) +{ + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct device *dev = &priv->pdev->dev; + size_t i; + + fdb->poll_wq = alloc_workqueue("%s-fdb-polling", 0, 0, dev_name(dev)); + if (!fdb->poll_wq) { + dev_err(&priv->pdev->dev, "Cannot allocate poll workqueue\n"); + goto err; + } + + fdb->update_wq = alloc_ordered_workqueue("%s-fdb-update", 0, + dev_name(dev)); + if (fdb->update_wq == NULL) { + dev_err(dev, "cannot create switchdev workqueue\n"); + goto update_err; + } + + for(i = 0; i < ARRAY_SIZE(fdb->sd_ev); ++i) { + fdb->sd_ev[i].info.addr = devm_kmalloc(dev, ETH_ALEN, + GFP_KERNEL); + if (!fdb->sd_ev[i].info.addr) + goto undo_sd_ev; + atomic_set(&fdb->sd_ev[i].free, 1); + } + + hash_init(fdb->arl_hash); + INIT_LIST_HEAD(&fdb->cache); + mutex_init(&fdb->lock); + + sw_core_writel(priv, gen_lan_port_mask(priv), SF2_CORE_SA_LIMIT_ENABLE); + INIT_DELAYED_WORK(&fdb->poll_wk, sf2_fdb_bookkeeping); + fdb->poll_delay = msecs_to_jiffies(SF2_FDB_POLL_DELAY_MS); + + fdb->switchdev_notifier.notifier_call = sf2_switchdev_event; + register_switchdev_notifier(&fdb->switchdev_notifier); + + queue_delayed_work(fdb->poll_wq, &fdb->poll_wk, fdb->poll_delay); + return 0; + +undo_sd_ev: + for(;i > 0; --i) + devm_kfree(dev, fdb->sd_ev[i - 1].info.addr); + destroy_workqueue(fdb->update_wq); +update_err: + destroy_workqueue(fdb->poll_wq); +err: + return -ENOMEM; +} + +/** + * Clenup fdb management structure and stop ARL polling worker + * + * @priv: Common SF2 private structure to cleanup fdb from + */ +void sf2_fdb_exit(struct bcm_sf2_priv *priv) +{ + struct bcm_sf2_fdb *fdb = &priv->fdb; + struct sf2_fdb_entry *fe; + struct hlist_node *tmp; + size_t i; + int bkt; + + unregister_switchdev_notifier(&fdb->switchdev_notifier); + + for(i = 0; i < ARRAY_SIZE(fdb->sd_ev); ++i) + devm_kfree(&priv->pdev->dev, fdb->sd_ev[i].info.addr); + + destroy_workqueue(fdb->poll_wq); + destroy_workqueue(fdb->update_wq); + + hash_for_each_safe(fdb->arl_hash, bkt, tmp, fe, hlist) { + hash_del(&fe->hlist); + sf2_fdb_del_entry(priv, fe); + } +} diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_main.c linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_main.c --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_main.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_main.c 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,2638 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sf2_priv.h" +#include "sf2_regs.h" +#include "serdes_regs.h" +#include "leds_top_regs.h" + +static const struct sf2_port_hw_desc +bcm63158_port_descs[SF2_PORT_COUNT] = { + [0] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 0, + }, + + [1] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 1, + }, + + [2] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 2, + }, + + [3] = { + .port_type = SF2_PORT_T_XBAR_MUX1, + }, + + [4] = { + .port_type = SF2_PORT_T_XBAR_4X3, + .xbar_out_port = 0, + }, + + [5] = { + .port_type = SF2_PORT_T_UNIMAC, + }, + + [6] = { + .port_type = SF2_PORT_T_XBAR_4X3, + .xbar_out_port = 1, + }, + + [7] = { + .port_type = SF2_PORT_T_UNIMAC, + }, + + [8] = { + .port_type = SF2_PORT_T_XBAR_MUX2, + .is_imp = true, + }, +}; + +static const struct sf2_port_hw_desc +bcm63158_xbar_port_descs[SF2_XBAR_IN_PORT_COUNT] = { + [0] = { + .port_type = SF2_PORT_T_SERDES, + }, + + [1] = { + .port_type = SF2_PORT_T_SINGLE_GPHY, + }, + + [2] = { + .port_type = SF2_PORT_T_RGMII, + }, + + [3] = { + .port_type = SF2_PORT_T_RGMII, + }, +}; + +static const char * +bcm63158_xbar_in_port_names[SF2_XBAR_IN_PORT_COUNT] = { + [0] = "P9", + [1] = "P10", + [2] = "P11", + [3] = "P12", +}; + +static const char * +bcm63158_xbar_out_port_names[SF2_XBAR_OUT_PORT_COUNT] = { + [0] = "P4", + [1] = "P6", + [2] = "WAN", +}; + +static const struct sf2_port_hw_desc +bcm63158_mux1_port_descs[2] = { + [0] = { + .port_type = SF2_PORT_T_QUAD_GPHY, + .quad_gphy_port = 3, + }, + + [1] = { + .port_type = SF2_PORT_T_RGMII, + }, +}; + +static const char * +mux1_in_port_names[2] = { + "P14", + "P13", +}; + +static const char *mux1_out_port_name = "P3"; + +static const struct sf2_port_hw_desc +bcm63158_mux2_port_descs[2] = { + [0] = { + .port_type = SF2_PORT_T_SYSPORT, + }, + + [1] = { + .port_type = SF2_PORT_T_UNIMAC, + }, +}; + +static const char * +mux2_in_port_names[2] = { + "system_port", + "unimac", +}; + +static const char *mux2_out_port_name = "P8"; + + + +/* + * LEDS top helpers for led flash rate, brightness and polarity. + */ + +/* + * 4 registers, with 8 leds handled on each registers. 3 bits rate + * fields every 4 bits. + */ +static void leds_top_set_flash_rate(struct bcm_sf2_priv *priv, int led, + u8 rate) +{ + int reg_off = led / 8; + int reg_shift = (led % 8) * 4; + u32 reg; + + regmap_read(priv->leds_top_regmap, LEDS_TOP_FLASH_RATE_REG(reg_off), + ®); + reg &= ~(0x7 << reg_shift); + reg |= (rate << reg_shift); + regmap_write(priv->leds_top_regmap, LEDS_TOP_FLASH_RATE_REG(reg_off), + reg); +} + +/* + * 4 registers, with 8 leds handled on each registers. 4 bits + * brightness fields every 4 bits. + */ +static void leds_top_set_brightness(struct bcm_sf2_priv *priv, int led, + u8 brightness) +{ + int reg_off = led / 8; + int reg_shift = (led % 8) * 4; + u32 reg; + + regmap_read(priv->leds_top_regmap, LEDS_TOP_BRIGHTNESS_REG(reg_off), + ®); + reg &= ~(0xf << reg_shift); + reg |= (brightness << reg_shift); + regmap_write(priv->leds_top_regmap, LEDS_TOP_BRIGHTNESS_REG(reg_off), + reg); +} + +/* + * 1 register, with 32 leds handled on a signel register, 1 bit + * polarity fields. + */ +static void leds_top_set_polarity(struct bcm_sf2_priv *priv, int led, + int polarity) +{ + u32 reg; + + regmap_read(priv->leds_top_regmap, LEDS_TOP_POLARITY_REG, ®); + if (polarity) + reg |= (1 << led); + else + reg &= ~(1 << led); + regmap_write(priv->leds_top_regmap, LEDS_TOP_POLARITY_REG, reg); +} + +/* + * only handle link/activity leds. + */ +static void sf2_port_leds_control(struct bcm_sf2_priv *priv, + struct sf2_port *port, bool enable) +{ + if (!port->used || port->cfg.led_link_act < 0) + return; + + /* + * LEDS TOP setup + */ + leds_top_set_flash_rate(priv, port->cfg.led_link_act, 0x0); + leds_top_set_brightness(priv, port->cfg.led_link_act, + enable ? 0x8 : 0x0); + leds_top_set_polarity(priv, port->cfg.led_link_act, 0x1); + + /* + * SWITCH_REG setup + */ + if (enable) + sw_reg_writel(priv, LED_CTRL_TX_ACT_EN | LED_CTRL_RX_ACT_EN, + SF2_REG_LED_CTRL(port->id)); + else + sw_reg_writel(priv, 0x0, SF2_REG_LED_CTRL(port->id)); +} + +/* + * + */ +static void sf2_port_control(struct bcm_sf2_priv *priv, int port, bool enable) +{ + u32 reg; + + if (priv->ports[port].enabled == enable) + return; + + if (enable) + dev_info(&priv->pdev->dev, "enabling port %d\n", port); + else + dev_info(&priv->pdev->dev, "disabling port %d\n", port); + + if (bcm63158_port_descs[port].is_imp) { + reg = sw_core_readl(priv, SF2_CORE_IMP_CTL(port)); + /* FIXME */ + sw_core_writel(priv, reg, SF2_CORE_IMP_CTL(port)); + } else { + reg = sw_core_readl(priv, SF2_CORE_PCTL(port)); + if (enable) { + reg &= ~(PCTL_TXDIS | PCTL_RXDIS); + reg &= ~(PCTL_STP_MASK); + reg |= PCTL_STP_NONE; + } else { + reg |= (PCTL_TXDIS | PCTL_RXDIS); + } + sw_core_writel(priv, reg, SF2_CORE_PCTL(port)); + } + + sf2_port_leds_control(priv, &priv->ports[port], enable); + + priv->ports[port].enabled = enable; +} + + +/* + * mdio bus accessors + */ +static int __mdio_wait(struct bcm_sf2_priv *priv) +{ + u32 tries; + + /* at lowest clock speed (500khz), about 64 bits per transfer + * (32 bits preamble) => 128 us total */ + tries = 150; + while (tries) { + u32 cmd_reg; + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + if ((cmd_reg & CMD_BUSY) == 0) + break; + + --tries; + udelay(1); + } + + if (!tries) + return -ETIMEDOUT; + + return 0; +} + +/* + * + */ +static int sf2_mii_c45_addr(struct bcm_sf2_priv *priv, + int port_addr, int dev_addr, int reg) +{ + u32 cmd_reg; + int error; + + cmd_reg = OPCODE_C45_ADDR | + CMD_PHY_ADDR(port_addr) | + CMD_REG_ADDR(dev_addr) | + CMD_DATA(reg); + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + if (error) + return error; + + return 0; +} + +/* + * + */ +static int sf2_mii_read(struct mii_bus *bus, int addr, int reg) +{ + struct bcm_sf2_priv *priv = bus->priv; + u32 cmd_reg, cfg_reg; + int error; + u16 value; + + cfg_reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + if (!(reg & MII_ADDR_C45)) + cfg_reg |= MDIO_CLAUSE_22_MASK; + else + cfg_reg &= ~MDIO_CLAUSE_22_MASK; + sw_mdio_writel(priv, cfg_reg, SF2_MDIO_CFG); + + if (!(reg & MII_ADDR_C45)) { + cmd_reg = OPCODE_C22_READ | + CMD_PHY_ADDR(addr) | + CMD_REG_ADDR(reg); + } else { + u16 port_addr = addr; + u16 dev_addr = (reg & ~MII_ADDR_C45) >> 16; + u16 reg_val = (reg & 0xffff); + + /* printk("sw_mii_c45_read: port_addr:%u dev_addr:%u reg:%u\n", */ + /* port_addr, dev_addr, reg_val); */ + + error = sf2_mii_c45_addr(priv, port_addr, dev_addr, reg_val); + if (error) + return error; + + cmd_reg = OPCODE_C45_READ | + CMD_PHY_ADDR(port_addr) | + CMD_REG_ADDR(dev_addr); + } + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + + if (error) { + dev_err(&priv->pdev->dev, + "errno%d waiting for MDIO phy@%d.\n", error, addr); + return error; + } + + value = sw_mdio_readl(priv, SF2_MDIO_CMD) & CMD_REG_DATA_MASK; + /* printk("sw_mii_read: => value: %x\n", value); */ + return value; +} + +/* + * + */ +static int sf2_mii_write(struct mii_bus *bus, + int addr, int reg, u16 value) +{ + struct bcm_sf2_priv *priv = bus->priv; + u32 cmd_reg, cfg_reg; + int error; + + cfg_reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + if (!(reg & MII_ADDR_C45)) + cfg_reg |= MDIO_CLAUSE_22_MASK; + else + cfg_reg &= ~MDIO_CLAUSE_22_MASK; + sw_mdio_writel(priv, cfg_reg, SF2_MDIO_CFG); + + if (!(reg & MII_ADDR_C45)) { + cmd_reg = OPCODE_C22_WRITE | + CMD_PHY_ADDR(addr) | + CMD_REG_ADDR(reg) | + CMD_DATA(value); + } else { + u16 port_addr = addr; + u16 dev_addr = (reg & ~MII_ADDR_C45) >> 16; + u16 reg_val = (reg & 0xffff); + + /* printk("sw_mii_c45_writ: port_addr:%u dev_addr:%u reg:0x%x val:0x%x\n", */ + /* port_addr, dev_addr, reg_val, value); */ + + error = sf2_mii_c45_addr(priv, port_addr, dev_addr, reg_val); + if (error) + return error; + + cmd_reg = OPCODE_C45_WRITE | + CMD_PHY_ADDR(port_addr) | + CMD_REG_ADDR(dev_addr) | + CMD_DATA(value); + } + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + cmd_reg = sw_mdio_readl(priv, SF2_MDIO_CMD); + cmd_reg |= CMD_BUSY; + sw_mdio_writel(priv, cmd_reg, SF2_MDIO_CMD); + + error = __mdio_wait(priv); + if (error) + return error; + return 0; +} + +/* + * + */ +static int sf2_mii_bus_reset(struct mii_bus *bus) +{ + struct bcm_sf2_priv *priv = bus->priv; + + /* do a dummy mdio transfer */ + if (priv->qphy_en_mask) + (void)mdiobus_read(bus, priv->config.qphy_base_id, MII_BMSR); + if (priv->sphy_en_mask) + (void)mdiobus_read(bus, priv->config.sphy_phy_id, MII_BMSR); + if (priv->serdes_en_mask) + (void)mdiobus_read(bus, priv->config.serdes_phy_id, MII_BMSR); + + return 0; +} + +/* + * powerup workaround needed for 63158, from refsw, initial problem + * not know nor reproduced during testing + */ +static void gphy_init_power_war(struct bcm_sf2_priv *priv) +{ + u32 reg; + + /* assert both reset */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg |= QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg |= SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + /* magic register */ + sw_reg_writel(priv, 1, SF2_REG_PHY_TEST); + + /* powerup */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg &= ~(QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_EXT_PWR_DOWN_ALL); + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg &= ~(SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_EXT_PWR_DOWN); + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + /* powerdown */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg |= (QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_EXT_PWR_DOWN_ALL); + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg |= (SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_EXT_PWR_DOWN); + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + /* deassert both reset */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg &= ~QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg &= ~SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(25); + + sw_reg_writel(priv, 0, SF2_REG_PHY_TEST); +} + +/* + * QUAD GPHY block init + */ +static void quad_gphy_block_init(struct bcm_sf2_priv *priv, + unsigned int enabled_port_mask, + unsigned int base_mdio_address) +{ + u32 reg; + + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + + /* set base mdio address */ + reg &= ~QPHY_CTRL_PHY_BASE_ADDR_MASK; + reg |= base_mdio_address << QPHY_CTRL_PHY_BASE_ADDR_SHIFT; + + if (!enabled_port_mask) { + /* power down */ + reg |= QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_EXT_PWR_DOWN_ALL | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_CLK_25_DISABLE; + } else { + reg &= ~(QPHY_CTRL_IDDQ_BIAS | + QPHY_CTRL_IDDQ_GLOBAL_PWR | + QPHY_CTRL_EXT_PWR_DOWN_ALL); + + /* powerdown unused port */ + reg |= (~enabled_port_mask << QPHY_CTRL_EXT_PWR_DOWN_SHIFT) & + QPHY_CTRL_EXT_PWR_DOWN_ALL; + } + + /* toggle reset */ + reg |= QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + msleep(1); + + /* de-assert reset */ + reg = sw_reg_readl(priv, SF2_REG_QPHY_CTRL); + reg &= ~QPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_QPHY_CTRL); + msleep(1); +} + +/* + * single GPHY block init + */ +static void single_gphy_block_init(struct bcm_sf2_priv *priv, + bool used, + unsigned int mdio_address) +{ + u32 reg; + + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + + /* set mdio address */ + reg &= ~SPHY_CTRL_PHY_BASE_ADDR_MASK; + reg |= mdio_address << SPHY_CTRL_PHY_BASE_ADDR_SHIFT; + + if (!used) { + reg |= SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_EXT_PWR_DOWN | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_CLK_25_DISABLE; + } else { + reg &= ~(SPHY_CTRL_IDDQ_BIAS | + SPHY_CTRL_IDDQ_GLOBAL_PWR | + SPHY_CTRL_EXT_PWR_DOWN); + } + + /* toggle reset */ + reg |= SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(1); + + /* de-assert reset */ + reg = sw_reg_readl(priv, SF2_REG_SPHY_CTRL); + reg &= ~SPHY_CTRL_PHY_RESET; + sw_reg_writel(priv, reg, SF2_REG_SPHY_CTRL); + msleep(1); +} + +/* + * serdes phy block init + */ +static void serdes_phy_block_init(struct bcm_sf2_priv *priv, + bool used, + unsigned int mdio_address, + bool invert_signal_detect) +{ + u32 reg; + + /* configure signal detect logic */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_APD_CTRL); + if (invert_signal_detect) + reg |= SSRD_APD_CTRL_INV_SD; + else + reg &= ~SSRD_APD_CTRL_INV_SD; + + /* + * complete reset and powerdown + */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_CTRL); + reg |= SSRD_CTRL_IDDQ_EN | + SSRD_CTRL_PDOWN_EN | + SSRD_CTRL_RESET_PLL | + SSRD_CTRL_RESET_MDIO | + SSRD_CTRL_RESET_SERDES; + reg &= ~SSRD_CTRL_PHY_BASE_ADDR_MASK; + reg |= mdio_address << SSRD_CTRL_PHY_BASE_ADDR_SHIFT; + sw_reg_writel(priv, reg, SF2_REG_SSRD_CTRL); + msleep(4); + + if (!used) + return; + + /* + * clear powerdown bits. + */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_CTRL); + reg &= ~(SSRD_CTRL_IDDQ_EN | + SSRD_CTRL_PDOWN_EN); + sw_reg_writel(priv, reg, SF2_REG_SSRD_CTRL); + msleep(4); + + /* + * clear reset bits + */ + reg = sw_reg_readl(priv, SF2_REG_SSRD_CTRL); + reg &= ~(SSRD_CTRL_RESET_PLL | + SSRD_CTRL_RESET_MDIO | + SSRD_CTRL_RESET_SERDES); + sw_reg_writel(priv, reg, SF2_REG_SSRD_CTRL); + msleep(4); +} + +/* + * + */ +static void sf2_arl_to_entry(struct sf2_arl_entry *ent, + u64 mac_vid, u32 fwd_entry) +{ + memset(ent, 0, sizeof(*ent)); + ent->port = fwd_entry & ARLTBL_DATA_PORT_ID_MASK; + ent->is_valid = !!(fwd_entry & ARLTBL_VALID); + ent->is_age = !!(fwd_entry & ARLTBL_AGE); + ent->is_static = !!(fwd_entry & ARLTBL_STATIC); + u64_to_ether_addr(mac_vid, ent->mac); + ent->vid = mac_vid >> ARLTBL_VID_S; +} + +/* + * + */ +static int sf2_arl_search_wait(struct bcm_sf2_priv *priv) +{ + unsigned int timeout = 1000; + u8 reg; + + do { + reg = sw_core_readl(priv, SF2_CORE_ARL_SRCH_CTRL); + + if (!(reg & ARL_SRCH_STDN)) + return 0; + + if (reg & ARL_SRCH_VLID) + return 0; + + usleep_range(50, 100); + } while (timeout--); + + return -ETIMEDOUT; +} + +/* + * + */ +static void sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx, + struct sf2_arl_entry *ent) +{ + u64 mac_vid; + u32 fwd_entry; + + mac_vid = sw_core_readll(priv, SF2_CORE_ARL_SRCH_RSTx_MACVID(idx)); + fwd_entry = sw_core_readl(priv, SF2_CORE_ARL_SRCH_RSTx(idx)); + sf2_arl_to_entry(ent, mac_vid, fwd_entry); +} + +/* + * + */ +static int sf2_arl_op_wait(struct bcm_sf2_priv *priv) +{ + unsigned int timeout = 10; + u8 reg; + + do { + reg = sw_core_readl(priv, SF2_CORE_ARL_RWCTL); + if (!(reg & SF2_ARL_START)) + return 0; + + usleep_range(1000, 2000); + } while (timeout--); + + dev_warn(&priv->pdev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg); + return -ETIMEDOUT; +} + +/* + * + */ +static int sf2_arl_rw_op(struct bcm_sf2_priv *priv, bool is_write) +{ + u8 reg; + + reg = sw_core_readl(priv, SF2_CORE_ARL_RWCTL); + reg |= SF2_ARL_START; + if (is_write) + reg &= ~SF2_ARL_READ; + else + reg |= SF2_ARL_READ; + + sw_core_writel(priv, reg, SF2_CORE_ARL_RWCTL); + return sf2_arl_op_wait(priv); +} + +/* + * + */ +static int sf2_arl_del_entry(struct bcm_sf2_priv *priv, + const struct sf2_arl_entry *ent, void *data) +{ + u64 mac; + int ret, i; + + /* Convert the array into a 64-bit MAC */ + mac = ether_addr_to_u64(ent->mac); + + /* Perform a read for the given MAC and VID */ + sw_core_writell(priv, mac, SF2_CORE_ARL_MAC_IDX); + sw_core_writell(priv, 0, SF2_CORE_ARL_VID_IDX); + + /* Issue a read operation for this MAC */ + ret = sf2_arl_rw_op(priv, false); + if (ret) + goto out; + + /* make all fwd entries invalid */ + for (i = 0; i < 4; i++) + sw_core_writell(priv, 0, SF2_CORE_ARL_FWDENTRY(i)); + + /* write */ + ret = sf2_arl_rw_op(priv, true); + +out: + if (ret) + dev_err(&priv->pdev->dev, "failed to delete mac from ARL\n"); + return ret; +} + +static void +_sf2_arl_for_each(struct bcm_sf2_priv *priv, + int (*fn)(struct bcm_sf2_priv *, const struct sf2_arl_entry *, + void *), + void *data) +{ + unsigned int count; + int ret; + u8 reg; + + /* Start search operation */ + count = 0; + reg = ARL_SRCH_STDN; + sw_core_writel(priv, reg, SF2_CORE_ARL_SRCH_CTRL); + + do { + int i; + + ret = sf2_arl_search_wait(priv); + if (ret) + return; + + for (i = 0; i < 2; i++) { + struct sf2_arl_entry ent; + + sf2_arl_search_rd(priv, i, &ent); + if (!ent.is_valid) + continue; + + if (fn(priv, &ent, data)) + return; + + } + + } while (count++ < 1024); +} + +void +sf2_arl_for_each(struct bcm_sf2_priv *priv, + int (*fn)(struct bcm_sf2_priv *, const struct sf2_arl_entry *, + void *), + void *data) +{ + return _sf2_arl_for_each(priv, fn, data); +} + +/* + * + */ +static void sf2_arl_clear(struct bcm_sf2_priv *priv) +{ + sf2_arl_for_each(priv, sf2_arl_del_entry, NULL); +} + +/* + * + */ +int sf2_arl_delete(struct bcm_sf2_priv *priv, const u8 *mac, u16 vid) +{ + struct sf2_arl_entry ent = { + .vid = 0, /* Force vid to 0, as there is no VLAN support yet */ + }; + + memcpy(ent.mac, mac, sizeof(ent.mac)); + sf2_arl_del_entry(priv, &ent, NULL); + return 0; +} + +/* + * + */ +static void sf2_hw_init(struct bcm_sf2_priv *priv) +{ + const struct sf2_config *config = &priv->config; + u32 reg; + int loop, i; + + /* + * power up block + * + * NOTE: the bootloader leave the SF2 enabled, doing a + * powerdown is not supported and can result in the switch not + * going out of reset (external abort accessing the registers). + * + * we just deassert reset in case bootloader did not + */ + reset_control_deassert(priv->rst); + msleep(10); + + /* + * soft reset switch (no effect on 63158 :/) + */ + sw_core_writel(priv, + SF2_SOFTWARE_RESET | + SF2_EN_SW_RST, + SF2_CORE_WATCHDOG_CTRL); + for (loop = 0; loop < 10000; loop++) { + reg = sw_core_readl(priv, SF2_CORE_WATCHDOG_CTRL); + if (!(reg & SF2_SOFTWARE_RESET)) + break; + udelay(100); + } + if (loop == 10000) + printk("SF2 soft reset failed\n"); + msleep(1); + + /* make sure forwarding is disabled */ + reg = sw_core_readl(priv, SF2_CORE_SWMODE); + reg &= ~SWMODE_FWD_EN; + sw_core_writel(priv, reg, SF2_CORE_SWMODE); + + /* reset does not work on 63158, restore some registers + * changed by CFE */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + u32 reg; + + reg = (1 << SF2_PORT_COUNT) - 1; + sw_core_writel(priv, reg, SF2_CORE_Px_VLAN_CTL(i)); + } + + /* since reset is not working, handle clear the ARL */ + sf2_arl_clear(priv); + + /* setup crossbar mapping */ + reg = sw_reg_readl(priv, SF2_REG_XBAR_CTRL); + reg &= ~(XBAR_PORT_MASK << XBAR_P4_SHIFT); + reg &= ~(XBAR_PORT_MASK << XBAR_P6_SHIFT); + reg &= ~(XBAR_PORT_MASK << XBAR_WAN_SHIFT); + reg &= ~XBAR_MUX1_MASK; + reg &= ~XBAR_MUX2_MASK; + + reg |= priv->xbar_mapping[0] << XBAR_P4_SHIFT; + reg |= priv->xbar_mapping[1] << XBAR_P6_SHIFT; + reg |= priv->xbar_mapping[2] << XBAR_WAN_SHIFT; + if (priv->mux1_mapping) + reg |= XBAR_MUX1_MASK; + if (priv->mux2_mapping) + reg |= XBAR_MUX2_MASK; + sw_reg_writel(priv, reg, SF2_REG_XBAR_CTRL); + + /* + * QPHY/SPHY has a powerup workaround on 63158 + */ + gphy_init_power_war(priv); + + /* + * init QPHY/SPHY/serdes PHY block + */ + quad_gphy_block_init(priv, priv->qphy_en_mask, + config->qphy_base_id); + single_gphy_block_init(priv, priv->sphy_en_mask != 0, + config->sphy_phy_id); + serdes_phy_block_init(priv, priv->serdes_en_mask != 0, + config->serdes_phy_id, + config->serdes_inv_sd); + + /* + * set MDIO frequency to ~9.6Mhz + * freq = (250Mhz / 2 * (DIV + 1)) + * + * FIXME: should be in device tree + */ + reg = sw_mdio_readl(priv, SF2_MDIO_CFG); + reg &= ~MDIO_CLK_DIV_MASK; + reg |= (12 << MDIO_CLK_DIV_SHIFT); + sw_mdio_writel(priv, reg, SF2_MDIO_CFG); + + /* Wait until hardware enable the ports, or we will kill the + * hardware */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + for (loop = 0; loop < 10000; loop++) { + reg = sw_core_readl(priv, SF2_CORE_PCTL(i)); + if (!(reg & PCTL_RXDIS)) + break; + udelay(100); + } + if (loop == 10000) + printk("SF2 disable port %u failed\n", i); + } + + /* allow "mini jumbo" on all ports */ + reg = sw_core_readl(priv, SF2_CORE_MIB_GD_FM_MAX_SIZE); + reg &= ~SF2_GDM_FM_MAX_SIZE_MASK; + reg |= 2100; + sw_core_writel(priv, reg, SF2_CORE_MIB_GD_FM_MAX_SIZE); + + /* enable imp port to work as a normal port */ + reg = sw_core_readl(priv, SF2_CORE_CTRL); + reg &= 0xffb0; + sw_core_writel(priv, + SF2_CTRL_MII2_VOL_SEL | + SF2_CTRL_MII_DUMB_FWD_EN, + SF2_CORE_CTRL); + + /* enable unmanaged forwarding */ + reg = sw_core_readl(priv, SF2_CORE_SWMODE); + reg |= SWMODE_FWD_EN; + reg &= ~(SWMODE_FWD_MANAGED | SWMODE_RETRY_LIMIT_DIS); + sw_core_writel(priv, reg, SF2_CORE_SWMODE); +} + +/* + * internal serdes PHY access + */ +static int serdes_phy_read(struct bcm_sf2_priv *priv, u32 reg) +{ + return mdiobus_read(priv->mii_bus, priv->config.serdes_phy_id, reg); +} + +static int serdes_phy_write(struct bcm_sf2_priv *priv, u32 reg, u16 value) +{ + return mdiobus_write(priv->mii_bus, priv->config.serdes_phy_id, + reg, value); +} + +/* + * internal serdes PHY read from extended registers + */ +static __maybe_unused int serdes_ephy_read(struct bcm_sf2_priv *priv, int reg) +{ + uint32_t bank; + uint32_t offset; + int val; + int error; + + if (reg < 0x20) + return serdes_phy_read(priv, reg); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = serdes_phy_write(priv, BRCM_MIIEXT_BANK, bank); + val = serdes_phy_read(priv, offset); + if (val < 0) + error = val; + + error |= serdes_phy_write(priv, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + return (error < 0) ? error : val; +} + +/* + * internal serdes PHY write to extended registers + */ +static int serdes_ephy_write(struct bcm_sf2_priv *priv, int reg, u16 value) +{ + uint32_t bank; + uint32_t offset; + int error; + + if (reg < 0x20) + return serdes_phy_write(priv, reg, value); + + bank = reg & BRCM_MIIEXT_BANK_MASK; + offset = (reg & BRCM_MIIEXT_OFF_MASK) + BRCM_MIIEXT_OFFSET; + + error = serdes_phy_write(priv, BRCM_MIIEXT_BANK, bank); + error |= serdes_phy_write(priv, offset, value); + error |= serdes_phy_write(priv, BRCM_MIIEXT_BANK, BRCM_MIIEXT_DEF_BANK); + return error; +} + +/* + * internal serdes PHY bulk write to extended registers + */ +static int serdes_ephy_write_array(struct bcm_sf2_priv *priv, + const u16 *vals, size_t count) +{ + size_t i; + + for (i = 0; i < count; i += 2) { + int ret = serdes_ephy_write(priv, vals[i], vals[i + 1]); + if (ret < 0) + return ret; + } + return 0; +} + +/* + * reset internal serdes PHY + */ +static int serdes_reset(struct bcm_sf2_priv *priv) +{ + int retries = 100; + int ret; + + ret = serdes_phy_read(priv, MII_BMCR); + if (ret < 0) + return ret; + + ret |= BMCR_RESET; + ret = serdes_phy_write(priv, MII_BMCR, ret); + if (ret < 0) + return ret; + + do { + ret = serdes_phy_read(priv, MII_BMCR); + if (ret < 0) + return ret; + + msleep(10); + } while (ret & BMCR_RESET && --retries); + + return 0; +} + +/* + * restart aneg on internal serdes PHY + */ +static int serdes_aneg_restart(struct bcm_sf2_priv *priv) +{ + int ret; + + ret = serdes_phy_read(priv, MII_BMCR); + if (ret < 0) + return ret; + + ret |= BMCR_ANRESTART; + + ret = serdes_phy_write(priv, MII_BMCR, ret); + if (ret < 0) + return ret; + + return 0; +} + +/* + * regval + */ +static const u16 serdesRef50mVco6p25[] = { + 0x8000, 0x0c2f, + 0x8308, 0xc000, + 0x8050, 0x5740, + 0x8051, 0x01d0, + 0x8052, 0x19f0, + 0x8053, 0xaab0, + 0x8054, 0x8821, + 0x8055, 0x0044, + 0x8056, 0x8000, + 0x8057, 0x0872, + 0x8058, 0x0000, + + 0x8106, 0x0020, + 0x8054, 0x8021, + 0x8054, 0x8821, +}; + +static const u16 serdesSet2p5GFiber[] = { + 0x0010, 0x0C2F, /* disable pll start sequencer */ + 0x8300, 0x0149, /* enable fiber mode, signal_detect_en, invert signal detect(b2) */ + 0x8308, 0xC010, /* Force 2.5G Fiber, enable 50MHz refclk */ + 0x834a, 0x0001, /* Set os2 mode */ + 0x0000, 0x0140, /* disable AN, set 1G mode */ + 0x0010, 0x2C2F, /* enable pll start sequencer */ +}; + +#if 0 +static u16 serdesSet1GForcedFiber[] = { + 0x0010, 0x0c2f, /* disable pll start sequencer */ + 0x8300, 0x0109, /* Force Invert Signal Polarity */ + 0x8473, 0x1251, + 0x834a, 0x0003, + 0x0000, 0x0140, + 0x0010, 0x2c2f, /* enable pll start sequencer */ +}; +#endif + +static u16 serdesSet1GFiber [] = { + 0x0010, 0x0c2f, /* disable pll start sequencer */ + 0x8300, 0x0149, /* Force Auto Detect, Invert Signal Polarity */ + 0x8473, 0x1251, + 0x834a, 0x0003, + 0x0000, 0x1140, + 0x0010, 0x2c2f, /* enable pll start sequencer */ +}; + +static u16 serdesSet100MForcedSGMII [] = { + 0x0010, 0x0c2f, /* disable pll start sequencer */ + 0x8300, 0x0100, + 0x8301, 0x0007, + 0x8473, 0x1251, + 0x834a, 0x0003, + 0x0000, 0x2100, + 0x0010, 0x2c2f, /* enable pll start sequencer */ +}; + +static void serdes_set_1000basex(struct bcm_sf2_priv *priv) +{ +// printk("serdes_set_1000basex\n"); + serdes_reset(priv); + serdes_ephy_write_array(priv, serdesRef50mVco6p25, + ARRAY_SIZE(serdesRef50mVco6p25)); + msleep(1); + serdes_ephy_write_array(priv, serdesSet1GFiber, + ARRAY_SIZE(serdesSet1GFiber)); + serdes_aneg_restart(priv); +} + +static void serdes_set_2500basex(struct bcm_sf2_priv *priv) +{ +// printk("serdes_set_2500basex\n"); + serdes_reset(priv); + serdes_ephy_write_array(priv, serdesRef50mVco6p25, + ARRAY_SIZE(serdesRef50mVco6p25)); + msleep(1); + serdes_ephy_write_array(priv, serdesSet2p5GFiber, + ARRAY_SIZE(serdesSet2p5GFiber)); +} + +static void serdes_set_sgmii_100(struct bcm_sf2_priv *priv) +{ +// printk("serdes_set_sgmii_100\n"); + serdes_reset(priv); + msleep(1); + serdes_ephy_write_array(priv, serdesSet100MForcedSGMII, + ARRAY_SIZE(serdesSet100MForcedSGMII)); + serdes_aneg_restart(priv); +} + +/* + * + */ +static void sf2_dsa_phylink_validate(struct dsa_switch *ds, int port_id, + unsigned long *supported, + struct phylink_link_state *state) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + pr_debug("sf2_phylink_validate port:%d interface:%s\n", + port->id, phy_modes(state->interface)); + + phylink_set(mask, Autoneg); + phylink_set_port_modes(mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + + switch (port->pdesc->port_type) { + case SF2_PORT_T_RGMII: + case SF2_PORT_T_QUAD_GPHY: + case SF2_PORT_T_SINGLE_GPHY: + { + switch (state->interface) { + case PHY_INTERFACE_MODE_GMII: + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + break; + default: + goto unsupported; + } + break; + } + + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + { + switch (state->interface) { + case PHY_INTERFACE_MODE_INTERNAL: + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 2500baseT_Full); + break; + default: + goto unsupported; + } + break; + } + + case SF2_PORT_T_SERDES: + { + switch (state->interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + phylink_set(mask, 2500baseT_Full); + phylink_set(mask, 2500baseX_Full); + break; + + default: + goto unsupported; + } + break; + } + + default: + WARN(1, "invalid hw desc"); + return; + } + + bitmap_and(supported, supported, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + return; + +unsupported: + dev_err(&priv->pdev->dev, + "unsupported interface type %s for port %d", + phy_modes(state->interface), port->id); + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +/* + * + */ +static void sf2_dsa_phylink_mac_config(struct dsa_switch *ds, int port_id, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_config port:%d\n", port->id); + + switch (port->pdesc->port_type) { + case SF2_PORT_T_QUAD_GPHY: + case SF2_PORT_T_SINGLE_GPHY: + WARN_ON(mode != MLO_AN_PHY); + + /* should not happen because we check this in validate */ + WARN_ON(state->interface != PHY_INTERFACE_MODE_GMII); + + /* for internal phys, local mac config is adjusted + * automatically, nothing to do */ + return; + + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + case SF2_PORT_T_RGMII: + WARN_ON(mode != MLO_AN_PHY && mode != MLO_AN_FIXED); + + /* should not happen because we check this in validate */ + WARN_ON(state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_GMII); + + if (bcm63158_port_descs[port->id].is_imp) { + u32 reg; + + reg = sw_core_readl(priv, SF2_CORE_STS_OV_IMP_STATE); + reg |= STS_OV_IMP_LINK_MASK | + STS_OV_IMP_MII_SW_OVER_MASK; + + if (state->duplex) + reg |= STS_OV_IMP_FULL_DUPLEX_MASK; + else + reg &= ~STS_OV_IMP_FULL_DUPLEX_MASK; + + reg &= ~STS_OV_IMP_SPEED_ALL_MASK; + switch (state->speed) { + case 10: + reg |= STS_OV_IMP_SPEED_10_MASK; + break; + case 100: + reg |= STS_OV_IMP_SPEED_100_MASK; + break; + case 1000: + case 2500: + reg |= STS_OV_IMP_SPEED_1000_MASK; + break; + } + + if (state->pause & MLO_PAUSE_RX) + reg |= STS_OV_IMP_RX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_IMP_RX_FLOW_CTL_MASK; + + if (state->pause & MLO_PAUSE_TX) + reg |= STS_OV_IMP_TX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_IMP_TX_FLOW_CTL_MASK; + + sw_core_writel(priv, reg, SF2_CORE_STS_OV_IMP_STATE); + } else { + u32 reg; + + reg = sw_core_readl(priv, + SF2_CORE_STS_OV_Px_STATE(port->id)); + + reg |= STS_OV_Px_LINK_MASK | + STS_OV_Px_SW_OVER_MASK; + + if (state->duplex) + reg |= STS_OV_Px_FULL_DUPLEX_MASK; + else + reg &= ~STS_OV_Px_FULL_DUPLEX_MASK; + + reg &= ~STS_OV_Px_SPEED_ALL_MASK; + switch (state->speed) { + case 10: + reg |= STS_OV_Px_SPEED_10_MASK; + break; + case 100: + reg |= STS_OV_Px_SPEED_100_MASK; + break; + case 1000: + case 2500: + reg |= STS_OV_Px_SPEED_1000_MASK; + break; + } + + if (state->pause & MLO_PAUSE_RX) + reg |= STS_OV_Px_RX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_Px_RX_FLOW_CTL_MASK; + + if (state->pause & MLO_PAUSE_TX) + reg |= STS_OV_Px_TX_FLOW_CTL_MASK; + else + reg &= ~STS_OV_Px_TX_FLOW_CTL_MASK; + + sw_core_writel(priv, reg, + SF2_CORE_STS_OV_Px_STATE(port->id)); + } + + /* + * setup high speed IMP ports + */ + if (port->pdesc->port_type == SF2_PORT_T_UNIMAC || + port->pdesc->port_type == SF2_PORT_T_SYSPORT) { + u32 mask, spd, reg; + + switch (port_id) { + case 5: + mask = SW_CTRL_P5_SPEED_MASK; + if (state->speed == 2500) + spd = SW_CTRL_P5_SPEED_2_5G; + else + spd = SW_CTRL_P5_SPEED_1G; + break; + case 7: + mask = SW_CTRL_P7_SPEED_MASK; + if (state->speed == 2500) + spd = SW_CTRL_P7_SPEED_2_5G; + else + spd = SW_CTRL_P7_SPEED_1G; + break; + case 8: + mask = SW_CTRL_P8_SPEED_MASK; + if (state->speed == 2500) + spd = SW_CTRL_P8_SPEED_2_5G; + else + spd = SW_CTRL_P8_SPEED_1G; + break; + + default: + WARN(1, "unknown cpu port"); + mask = 0; + spd = 0; + break; + } + + reg = sw_reg_readl(priv, SF2_REG_SW_CTRL); + reg &= ~mask; + reg |= spd; + sw_reg_writel(priv, reg, SF2_REG_SW_CTRL); + } + break; + + case SF2_PORT_T_SERDES: + switch (state->interface) { + case PHY_INTERFACE_MODE_1000BASEX: + serdes_set_1000basex(priv); + break; + + case PHY_INTERFACE_MODE_SGMII: + if (state->speed == 100) + serdes_set_sgmii_100(priv); + else + serdes_set_1000basex(priv); + break; + + case PHY_INTERFACE_MODE_2500BASEX: + serdes_set_2500basex(priv); + break; + + default: + /* should not happen because we check this in + * validate */ + WARN(1, "unexpected interface mode"); + break; + } + break; + + default: + break; + } +} + +/* + * + */ +static int sf2_dsa_phylink_mac_link_state(struct dsa_switch *ds, int port_id, + struct phylink_link_state *state) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_link_state port:%d\n", port->id); + + /* only called for %MLO_AN_INBAND, so serdes only */ + if (WARN(port->pdesc->port_type != SF2_PORT_T_SERDES, + "mac_link_state called on non serdes port")) + return 0; + + return 0; +} + +/* + * + */ +static void sf2_dsa_phylink_mac_an_restart(struct dsa_switch *ds, int port_id) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_an_restart port:%d\n", port->id); + + /* only called for %MLO_AN_INBAND, so serdes only */ + if (WARN_ON(port->pdesc->port_type != SF2_PORT_T_SERDES)) + return; +} + +/* + * + */ +static void sf2_dsa_phylink_mac_link_up(struct dsa_switch *ds, int port_id, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phy) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_link_up port:%d\n", port->id); +} + +/* + * + */ +static void sf2_dsa_phylink_mac_link_down(struct dsa_switch *ds, int port_id, + unsigned int mode, + phy_interface_t interface) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct sf2_port *port = &priv->ports[port_id]; + + pr_debug("sf2_phylink_mac_link_down port:%d\n", port->id); +} + +static int sf2_dsa_port_setup(struct dsa_switch *ds, int port, + struct phy_device *phy) +{ + struct bcm_sf2_priv *priv = ds->priv; + pr_debug("sf2_dsa_port_setup port:%d", port); + sf2_port_control(priv, port, true); + return 0; +} + +static void sf2_dsa_port_disable(struct dsa_switch *ds, int port) +{ + struct bcm_sf2_priv *priv = ds->priv; + pr_debug("sf2_dsa_port_disable port:%d", port); + sf2_port_control(priv, port, false); +} + +/* + * + */ +static int sf2_dsa_setup(struct dsa_switch *ds) +{ + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + u32 lan_ports, cpu_ports, reg, reg2; + int port, ret; + + pr_debug("dsa_setup"); + + cpu_ports = gen_cpu_port_mask(priv); + lan_ports = gen_lan_port_mask(priv); + + /* resolve which cpu port to use for each port */ + for (port = 0; port < ds->num_ports; port++) { + struct dsa_port *dp = &ds->ports[port]; + + switch (dp->type) { + case DSA_PORT_TYPE_UNUSED: + continue; + + case DSA_PORT_TYPE_CPU: + if (!(cpu_ports & (1 << port))) { + dev_err(&priv->pdev->dev, + "cpu port config mismatch\n"); + return -EINVAL; + } + continue; + + default: + { + int cpu_index; + + if (WARN_ON(!dp->cpu_dp)) + return -EINVAL; + + cpu_index = dp->cpu_dp->index; + + if (cpu_index >= SF2_PORT_COUNT || + !(cpu_ports & (1 << cpu_index))) { + dev_err(&priv->pdev->dev, + "port %u points to invalid " + "cpu port %u\n", port, cpu_index); + return -EINVAL; + } + + priv->ports[port].cfg.cpu_port = cpu_index; + break; + } + } + } + + sf2_hw_init(priv); + + ret = of_mdiobus_register(priv->mii_bus, priv->mdio_np); + if (ret) { + dev_err(&priv->pdev->dev, "failed to register mdio bus"); + goto out_mdio; + } + + /* make sure all lan ports can only talk to cpu port */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + if (!(lan_ports & (1 << i))) + continue; + + sw_core_writel(priv, + (1 << i) | + (1 << priv->ports[i].cfg.cpu_port), + SF2_CORE_Px_VLAN_CTL(i)); + } + + /* enable brcm tag on all cpu ports */ + reg = reg2 = 0; + for (i = 0; i < SF2_PORT_COUNT; i++) { + if (!(cpu_ports & (1 << i))) + continue; + + switch (i) { + case 8: + reg |= SF2_BRCMTAG_P8; + break; + case 5: + reg |= SF2_BRCMTAG_P5; + break; + case 7: + reg |= SF2_BRCMTAG_P7; + break; + default: + reg2 |= SF2_BRCMTAG2_Px(i); + break; + } + } + + sw_core_writel(priv, reg, SF2_CORE_BRCMTAG_CTRL); + sw_core_writel(priv, reg2, SF2_CORE_BRCMTAG2_CTRL); + + /* enable brcmtag priority to TC (queue) mapping on cpu ports */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + unsigned int q; + + if (!(cpu_ports & (1 << i))) + continue; + + /* map 1:1 between prio number and queue id */ + reg = sw_core_readl(priv, SF2_CORE_PORT_TC2_QOS_MAP_PORT(i)); + for (q = 0; q < SF2_NUM_EGRESS_QUEUES; q++) + reg |= q << (PRT_TO_QID_SHIFT * q); + sw_core_writel(priv, reg, SF2_CORE_PORT_TC2_QOS_MAP_PORT(i)); + } + + /* configure & enable ACB */ + reg = sw_acb_readl(priv, SF2_ACB_CONTROL_REG); + reg &= ~ACB_CONTROL_EN_MASK; + reg &= ~ACB_CONTROL_FLUSHQ_MASK; + sw_acb_writel(priv, reg, SF2_ACB_CONTROL_REG); + + for (i = 0; i < SF2_PORT_COUNT; i++) { + size_t q; + + if ((cpu_ports & (1 << i))) + continue; + + for (q = 0; q < SF2_NUM_EGRESS_QUEUES; q++) { + reg = sw_acb_readl(priv, SF2_ACB_QCFG_REG(i, q)); + reg &= ~ACB_QCFG_XOFF_THRESH_MASK; + reg |= 24 << ACB_QCFG_XOFF_THRESH_SHIFT; + sw_acb_writel(priv, reg, SF2_ACB_QCFG_REG(i, q)); + } + } + + reg = sw_acb_readl(priv, SF2_ACB_CONTROL_REG); + reg |= ACB_CONTROL_FLUSHQ_MASK; + sw_acb_writel(priv, reg, SF2_ACB_CONTROL_REG); + reg &= ~ACB_CONTROL_FLUSHQ_MASK; + reg |= ACB_CONTROL_ALG2_MASK; + reg |= ACB_CONTROL_EN_MASK; + sw_acb_writel(priv, reg, SF2_ACB_CONTROL_REG); + + /* + * disable learning on cpu ports + * + * in case there are multiple CPU ports, the mac address from + * the bridge devices will keep flapping between them, since + * we can't install a mac address on multiple ports in the ATU + * we disable learning on those ports. + * + * this means all traffic coming from lan ports that should go + * to the CPU will be flooded by the switch, to avoid that we + * also change the default flood map registers to the switch + * only flood unknown unicast/multicast to the CPU port, which + * will then flood back the packets to the lan ports if + * needed. + * + * there does not seem to be a way to prevent the switch from + * flooding broadcast, so to prevent duplicate flooding, we + * mark those packets as already offloaded in the BRCM tag + * code + */ + sw_core_writel(priv, cpu_ports, SF2_CORE_DIS_LEARN); + sw_core_writel(priv, cpu_ports, SF2_CORE_UFL_FWD_MAP); + sw_core_writel(priv, cpu_ports, SF2_CORE_MFL_FWD_MAP); + sw_core_writel(priv, cpu_ports, SF2_CORE_IPMC_FWD_MAP); + + reg = sw_core_readl(priv, SF2_CORE_NEW_CTRL); + reg |= SF2_NEW_CTRL_MC_FWD_EN | + SF2_NEW_CTRL_UC_FWD_EN; + sw_core_writel(priv, reg, SF2_CORE_NEW_CTRL); + + ret = sf2_fdb_init(priv); + if (ret) { + dev_err(&priv->pdev->dev, "failed to init fdb monitoring"); + goto out_fdb; + } + + return 0; + +out_mdio: + sf2_fdb_exit(priv); +out_fdb: + mdiobus_unregister(priv->mii_bus); + return ret; +} + +/* + * + */ +static void sf2_dsa_teardown(struct dsa_switch *ds) +{ + struct bcm_sf2_priv *priv = ds->priv; + + pr_debug("dsa_teardown"); + + sf2_fdb_exit(priv); + mdiobus_unregister(priv->mii_bus); +} + +/* + * + */ +static enum dsa_tag_protocol sf2_dsa_get_tag_protocol(struct dsa_switch *ds, + int port_id) +{ + return DSA_TAG_PROTO_BRCM_FBX; +} + +struct sf2_mib_desc { + u8 size; + u8 offset; + const char *name; +}; + +static const struct sf2_mib_desc sf2_mibs[] = { + { 8, 0x00, "TxOctets" }, + { 4, 0x10, "TxBroadcastPkts" }, + { 4, 0x14, "TxMulticastPkts" }, + { 4, 0x18, "TxUnicastPKts" }, + { 4, 0x08, "TxDropPkts" }, + { 4, 0x1c, "TxCollisions" }, + { 4, 0x20, "TxSingleCollision" }, + { 4, 0x24, "TxMultipleCollision" }, + { 4, 0x28, "TxDeferredCollision" }, + { 4, 0x2c, "TxLateCollision" }, + { 4, 0x30, "TxExcessiveCollision" }, + { 4, 0x34, "TxFrameInDiscard" }, + { 4, 0x38, "TxPausePkts" }, + { 4, 0xd0, "TxPkts64Octets" }, + { 4, 0xd4, "TxPkts65to127Octets" }, + { 4, 0xd8, "TxPkts128to255Octets" }, + { 4, 0xdc, "TxPkts256to511Octets" }, + { 4, 0xe0, "TxPkts512to1023Octets" }, + { 4, 0xe4, "TxPkts1024toMaxPktOctets" }, + { 4, 0x0c, "TxQPKTQ0" }, + { 4, 0x3c, "TxQPKTQ1" }, + { 4, 0x40, "TxQPKTQ2" }, + { 4, 0x44, "TxQPKTQ3" }, + { 4, 0x48, "TxQPKTQ4" }, + { 4, 0x4c, "TxQPKTQ5" }, + { 4, 0xc8, "TxQPKTQ6" }, + { 4, 0xcc, "TxQPKTQ7" }, + { 8, 0x50, "RxOctets" }, + { 4, 0x58, "RxUndersizePkts" }, + { 4, 0x5c, "RxPausePkts" }, + { 4, 0x60, "RxPkts64Octets" }, + { 4, 0x64, "RxPkts65to127Octets" }, + { 4, 0x68, "RxPkts128to255Octets" }, + { 4, 0x6c, "RxPkts256to511Octets" }, + { 4, 0x70, "RxPkts512to1023Octets" }, + { 4, 0x74, "RxPkts1024toMaxPktsOctets" }, + { 4, 0x78, "RxOversizePkts" }, + { 4, 0x7c, "RxJabbers" }, + { 4, 0x80, "RxAlignmentErrors" }, + { 4, 0x84, "RxFCSErrors" }, + { 8, 0x88, "RxGoodOctets" }, + { 4, 0x90, "RxDropPkts" }, + { 4, 0x94, "RxUnicastPkts" }, + { 4, 0x98, "RxMulticastPkts" }, + { 4, 0x9c, "RxBroadcastPkts" }, + { 4, 0xa0, "RxSAChanges" }, + { 4, 0xa4, "RxFragments" }, + { 4, 0xa8, "RxJumboPkt" }, + { 4, 0xac, "RxSymblErr" }, + { 4, 0xc0, "RxDiscard" }, + { 4, 0xb0, "InRangeErrCount" }, + { 4, 0xb4, "OutRangeErrCount" }, + { 4, 0xb8, "EEELpiEvent" }, + { 4, 0xbc, "EEELpiDuration" }, +}; + +#define SF2_MIBS_SIZE ARRAY_SIZE(sf2_mibs) + +/* + * + */ +static int sf2_dsa_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct phy_device *phydev; + + switch (sset) { + case ETH_SS_STATS: + return SF2_MIBS_SIZE; + + case ETH_SS_PHY_STATS: + phydev = mdiobus_get_phy(priv->mii_bus, port); + if (!phydev) + return 0; + + return phy_ethtool_get_sset_count(phydev); + } + + return 0; +} + +/* + * + */ +static void sf2_dsa_get_strings(struct dsa_switch *ds, int port, + u32 sset, uint8_t *data) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct phy_device *phydev; + unsigned int i; + + switch (sset) { + case ETH_SS_STATS: + for (i = 0; i < SF2_MIBS_SIZE; i++) + strlcpy(data + i * ETH_GSTRING_LEN, + sf2_mibs[i].name, ETH_GSTRING_LEN); + break; + case ETH_SS_PHY_STATS: + phydev = mdiobus_get_phy(priv->mii_bus, port); + if (!phydev) + return; + + phy_ethtool_get_strings(phydev, data); + break; + } +} + +/* + * + */ +static void sf2_dsa_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + + for (i = 0; i < SF2_MIBS_SIZE; i++) { + const struct sf2_mib_desc *s = &sf2_mibs[i]; + u32 offset = SF2_CORE_Px_MIB(port) + s->offset * 8; + u64 val; + + if (s->size == 8) + val = sw_core_readll(priv, offset); + else + val = sw_core_readl(priv, offset); + + data[i] = val; + } +} + +/* + * + */ +static void sf2_dsa_get_ethtool_phy_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct bcm_sf2_priv *priv = ds->priv; + struct phy_device *phydev; + + phydev = mdiobus_get_phy(priv->mii_bus, port); + if (!phydev) + return; + + phy_ethtool_get_stats(phydev, NULL, data); +} + +/* + * + */ +static int sf2_dsa_port_join_pxvlan(struct dsa_switch *ds, int port, + struct net_device *br) +{ + const struct dsa_port *dp = dsa_to_port(ds, port); + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + u32 pvlan; + + + if (dp->type == DSA_PORT_TYPE_CPU) + return 0; + + /* + * add port to all others ports PBVLAN map when they share the + * same bridge + */ + pvlan = 0; + for (i = 0; i < SF2_PORT_COUNT; i++) { + u32 reg; + + if (i == port) + continue; + + + if (dsa_to_port(ds, i)->bridge_dev != br) + continue; + + reg = sw_core_readl(priv, SF2_CORE_Px_VLAN_CTL(i)); + reg |= BIT(port); + sw_core_writel(priv, reg, SF2_CORE_Px_VLAN_CTL(i)); + + pvlan |= BIT(i); + } + + pvlan |= (1 << port); + pvlan |= (1 << priv->ports[port].cfg.cpu_port); + sw_core_writel(priv, pvlan, SF2_CORE_Px_VLAN_CTL(port)); + + return 0; +} + +static int sf2_dsa_port_bridge_join(struct dsa_switch *ds, int port, + struct net_device *br) +{ + pr_debug("sf2_dsa_port_bridge_join: port:%d\n", port); + return sf2_dsa_port_join_pxvlan(ds, port, br); +} + +/* + * + */ +static void sf2_dsa_port_leave_pxvlan(struct dsa_switch *ds, int port, + struct net_device *br) +{ + const struct dsa_port *dp = dsa_to_port(ds, port); + struct bcm_sf2_priv *priv = ds->priv; + unsigned int i; + + if (dp->type == DSA_PORT_TYPE_CPU) + return; + + /* + * remove port from all others ports PBVLAN map when they + * share the same bridge + */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + u32 reg; + + if (i == port) + continue; + + if (dsa_to_port(ds, i)->bridge_dev != br) + continue; + + reg = sw_core_readl(priv, SF2_CORE_Px_VLAN_CTL(i)); + reg &= ~BIT(port); + sw_core_writel(priv, reg, SF2_CORE_Px_VLAN_CTL(i)); + } + + /* + * restore port pbvlan to its cpu port + */ + sw_core_writel(priv, + (1 << port) | + (1 << priv->ports[port].cfg.cpu_port), + SF2_CORE_Px_VLAN_CTL(port)); +} + +static void sf2_dsa_port_bridge_leave(struct dsa_switch *ds, int port, + struct net_device *br) +{ + struct bcm_sf2_priv *priv = ds->priv; + u32 reg, new; + + pr_debug("sf2_dsa_port_bridge_leave: port:%d\n", port); + + sf2_dsa_port_leave_pxvlan(ds, port, br); + + reg = sw_core_readl(priv, SF2_CORE_PCTL(port)); + new = reg & ~PCTL_STP_MASK; + new |= PCTL_STP_NONE; + sw_core_writel(priv, new, SF2_CORE_PCTL(port)); +} + +static void sf2_dsa_port_stp_state_set(struct dsa_switch *ds, int port_id, + u8 state) +{ + struct bcm_sf2_priv *priv = ds->priv; + const struct dsa_port *port = dsa_to_port(ds, port_id); + u32 hw_state; + u32 reg, new; + + if (!port->bridge_dev) + return; + + switch (state) { + case BR_STATE_DISABLED: + hw_state = PCTL_STP_DISABLE; + break; + case BR_STATE_LISTENING: + hw_state = PCTL_STP_LISTEN; + break; + case BR_STATE_LEARNING: + hw_state = PCTL_STP_LEARN; + break; + case BR_STATE_FORWARDING: + hw_state = PCTL_STP_FORWARD; + break; + case BR_STATE_BLOCKING: + hw_state = PCTL_STP_BLOCKED; + break; + default: + dev_err(ds->dev, "invalid STP state: %d\n", state); + return; + } + + reg = sw_core_readl(priv, SF2_CORE_PCTL(port_id)); + new = reg & ~PCTL_STP_MASK; + new |= hw_state; + if (new == reg) + return; + + if (state != BR_STATE_FORWARDING) + sf2_dsa_port_leave_pxvlan(ds, port_id, port->bridge_dev); + else + sf2_dsa_port_join_pxvlan(ds, port_id, port->bridge_dev); + + dev_dbg(ds->dev, "Set STP state of port %d: %d\n", port_id, state); + sw_core_writel(priv, new, SF2_CORE_PCTL(port_id)); + sf2_arl_clear(priv); +} + +static int sf2_dsa_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid) +{ + struct bcm_sf2_priv *priv = ds->priv; + /* Force vlanid to 0 as there is no ARL vlan support */ + sf2_arl_delete(priv, addr, 0); + return 0; +} + +/* + * + */ +static int sf2_fdb_copy(int port, const struct sf2_arl_entry *ent, + dsa_fdb_dump_cb_t *cb, void *data) +{ + if (!ent->is_valid) + return 0; + + if (port != ent->port) + return 0; + + return cb(ent->mac, ent->vid, ent->is_static, data); +} + +/* + * + */ +static const struct dsa_switch_ops bcm_sf2_dsa_ops = { + .get_tag_protocol = sf2_dsa_get_tag_protocol, + .setup = sf2_dsa_setup, + .teardown = sf2_dsa_teardown, + .port_enable = sf2_dsa_port_setup, + .port_disable = sf2_dsa_port_disable, + .phylink_validate = sf2_dsa_phylink_validate, + .phylink_mac_config = sf2_dsa_phylink_mac_config, + .phylink_mac_an_restart = sf2_dsa_phylink_mac_an_restart, + .phylink_mac_link_down = sf2_dsa_phylink_mac_link_down, + .phylink_mac_link_up = sf2_dsa_phylink_mac_link_up, + .phylink_mac_link_state = sf2_dsa_phylink_mac_link_state, + .get_strings = sf2_dsa_get_strings, + .get_ethtool_stats = sf2_dsa_get_ethtool_stats, + .get_sset_count = sf2_dsa_get_sset_count, + .get_ethtool_phy_stats = sf2_dsa_get_ethtool_phy_stats, + .port_bridge_join = sf2_dsa_port_bridge_join, + .port_bridge_leave = sf2_dsa_port_bridge_leave, + .port_stp_state_set = sf2_dsa_port_stp_state_set, + .port_fdb_del = sf2_dsa_fdb_del, +}; + +/* + * + */ +static void fixup_xbar_config(struct bcm_sf2_priv *priv) +{ + int xbar_in_used[SF2_XBAR_OUT_PORT_COUNT]; + size_t i; + + memset(xbar_in_used, 0, sizeof (xbar_in_used)); + + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) { + if (priv->xbar_mapping[i] == -1) + continue; + + xbar_in_used[priv->xbar_mapping[i]] = 1; + } + + /* assign unused out port to something */ + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) { + size_t j; + + if (priv->xbar_mapping[i] != -1) + continue; + + for (j = 0; j < ARRAY_SIZE(xbar_in_used); j++) { + if (xbar_in_used[j]) + continue; + + priv->xbar_mapping[i] = j; + xbar_in_used[priv->xbar_mapping[i]] = 1; + break; + } + } +} + +/* + * + */ +static int of_read_sf2_config(struct platform_device *pdev, + struct bcm_sf2_priv *priv) +{ + struct sf2_config *config = &priv->config; + bool xbar_in_used[SF2_XBAR_IN_PORT_COUNT]; + struct device_node *ports_np, *port_np, *wan_port_np; + int i, ret; + u32 val; + + /* + * fill config from device tree + */ + memset(config, 0, sizeof (*config)); + + ret = of_property_read_u32(pdev->dev.of_node, + "sf2,qphy-base-id", + &config->qphy_base_id); + ret |= of_property_read_u32(pdev->dev.of_node, + "sf2,sphy-phy-id", + &config->sphy_phy_id); + ret |= of_property_read_u32(pdev->dev.of_node, + "sf2,serdes-phy-id", + &config->serdes_phy_id); + if (ret) { + dev_err(&pdev->dev, "missing phy id properties"); + return ret; + } + + wan_port_np = of_get_child_by_name(pdev->dev.of_node, + "sf2,wan-port-config"); + if (!wan_port_np) { + dev_err(&pdev->dev, "missing sf2,wan-port-config property"); + return -ENODEV; + } + + priv->wan_port.used = of_device_is_available(wan_port_np); + if (priv->wan_port.used) { + ret = of_property_read_u32(wan_port_np, "xbar-in-port", &val); + if (ret) { + dev_err(&pdev->dev, "missing xbar-in-port " + "property for wan port"); + return -ENODEV; + } + priv->wan_port.cfg.xbar_in_port = val; + } + + ports_np = of_get_child_by_name(pdev->dev.of_node, "ports"); + if (!ports_np) { + dev_err(&pdev->dev, "missing ports property"); + return -ENODEV; + } + + priv->leds_top_regmap = + syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "leds-top"); + if (IS_ERR(priv->leds_top_regmap)) + return PTR_ERR(priv->leds_top_regmap); + + for_each_available_child_of_node(ports_np, port_np) { + struct sf2_port *port; + struct sf2_port_config *pcfg; + const struct sf2_port_hw_desc *pdesc; + u32 port_id; + + ret = of_property_read_u32(port_np, "reg", &port_id); + if (ret) + return ret; + + if (port_id >= SF2_PORT_COUNT) + return -EINVAL; + + port = &priv->ports[port_id]; + port->id = port_id; + pcfg = &port->cfg; + pcfg->cpu_port = -1; + + pdesc = &bcm63158_port_descs[port_id]; + + port->used = of_device_is_available(port_np); + if (!port->used) + continue; + + if (!of_property_read_u32(port_np, "sf2,led-link-act", &val)) + pcfg->led_link_act = val; + else + pcfg->led_link_act = -1; + + if (!of_property_read_u32(port_np, "sf2,cpu-port", &val)) { + if (val >= SF2_PORT_COUNT) { + dev_err(&pdev->dev, "bad sf2,cpu-port value " + "property for port %d", port_id); + return -EINVAL; + } + pcfg->cpu_port = val; + } + + switch (pdesc->port_type) { + case SF2_PORT_T_XBAR_4X3: + if (of_property_read_u32(port_np, "xbar-in-port", &val)) { + dev_err(&pdev->dev, "missing xbar-in-port " + "property for port %d", port_id); + return -ENODEV; + } + pcfg->xbar_in_port = val; + break; + + case SF2_PORT_T_XBAR_MUX1: + if (of_property_read_u32(port_np, "mux1-in-port", &val)) { + dev_err(&pdev->dev, "missing mux1-in-port " + "property for port %d", port_id); + return -ENODEV; + } + pcfg->mux1_in_port = val; + break; + + case SF2_PORT_T_XBAR_MUX2: + if (of_property_read_u32(port_np, "mux2-in-port", &val)) { + dev_err(&pdev->dev, "missing mux2-in-port " + "property for port %d", port_id); + return -ENODEV; + } + pcfg->mux2_in_port = val; + break; + + default: + break; + } + } + + /* + * check & compute various mappings from config + */ + priv->qphy_en_mask = 0; + priv->sphy_en_mask = 0; + priv->serdes_en_mask = 0; + memset(xbar_in_used, 0, sizeof (xbar_in_used)); + + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) + priv->xbar_mapping[i] = -1; + + /* first round to resolve real port */ + for (i = 0; i < SF2_PORT_COUNT; i++) { + struct sf2_port *port = &priv->ports[i]; + const struct sf2_port_config *pcfg = &port->cfg; + const struct sf2_port_hw_desc *pdesc = &bcm63158_port_descs[i]; + + if (!port->used) + continue; + + switch (pdesc->port_type) { + case SF2_PORT_T_UNEXISTING: + dev_err(&pdev->dev, + "configured to use non-existing port %u\n", i); + return -EINVAL; + + case SF2_PORT_T_RGMII: + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + case SF2_PORT_T_QUAD_GPHY: + case SF2_PORT_T_SINGLE_GPHY: + case SF2_PORT_T_SERDES: + port->pdesc = pdesc; + break; + + case SF2_PORT_T_XBAR_MUX1: + { + int mux_in; + + mux_in = pcfg->mux1_in_port; + + if (mux_in < 0 || mux_in > 1) { + dev_err(&pdev->dev, + "port %d use non-existing " + "mux in port %u\n", i, mux_in); + return -EINVAL; + } + + priv->mux1_mapping = mux_in; + port->pdesc = &bcm63158_mux1_port_descs[mux_in]; + break; + } + + case SF2_PORT_T_XBAR_MUX2: + { + int mux_in; + + mux_in = pcfg->mux2_in_port; + + if (mux_in < 0 || mux_in > 1) { + dev_err(&pdev->dev, + "port %d use non-existing " + "mux in port %u\n", i, mux_in); + return -EINVAL; + } + + priv->mux2_mapping = mux_in; + port->pdesc = &bcm63158_mux2_port_descs[mux_in]; + break; + } + + case SF2_PORT_T_XBAR_4X3: + { + int xbar_in; + + xbar_in = pcfg->xbar_in_port; + if (xbar_in < 0 || + xbar_in >= ARRAY_SIZE(bcm63158_xbar_port_descs)) { + dev_err(&pdev->dev, + "port %d use non-existing " + "xbar in port %u\n", i, xbar_in); + return -EINVAL; + } + + if (xbar_in_used[xbar_in]) { + dev_err(&pdev->dev, + "port %d use already used " + "xbar in port %u\n", i, xbar_in); + return -EINVAL; + } + + priv->xbar_mapping[pdesc->xbar_out_port] = xbar_in; + port->pdesc = &bcm63158_xbar_port_descs[xbar_in]; + break; + } + } + } + + for (i = 0; i < SF2_PORT_COUNT; i++) { + struct sf2_port *port = &priv->ports[i]; + const struct sf2_port_hw_desc *pdesc = port->pdesc; + + if (!pdesc) + continue; + + switch (pdesc->port_type) { + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + break; + + case SF2_PORT_T_QUAD_GPHY: + WARN_ON(priv->qphy_en_mask & + (1 << pdesc->quad_gphy_port)); + priv->qphy_en_mask |= (1 << pdesc->quad_gphy_port); + break; + + case SF2_PORT_T_SINGLE_GPHY: + WARN_ON(priv->sphy_en_mask != 0); + priv->sphy_en_mask |= 1; + break; + + case SF2_PORT_T_SERDES: + WARN_ON(priv->serdes_en_mask != 0); + priv->serdes_en_mask |= 1; + break; + + default: + break; + } + } + + if (priv->wan_port.used) { + const struct sf2_port_hw_desc *xbar_in_pdesc; + int xbar_in; + + xbar_in = priv->wan_port.cfg.xbar_in_port; + if (xbar_in < 0 || + xbar_in >= ARRAY_SIZE(bcm63158_xbar_port_descs)) { + dev_err(&pdev->dev, + "wan port use non-existing " + "xbar in port %u\n", xbar_in); + return -EINVAL; + } + + if (xbar_in_used[xbar_in]) { + dev_err(&pdev->dev, + "wan port use already used " + "xbar in port %u\n", xbar_in); + return -EINVAL; + } + + priv->xbar_mapping[2] = xbar_in; + xbar_in_pdesc = &bcm63158_xbar_port_descs[xbar_in]; + priv->wan_port.pdesc = xbar_in_pdesc; + + switch (xbar_in_pdesc->port_type) { + case SF2_PORT_T_RGMII: + break; + + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + return -EINVAL; + + case SF2_PORT_T_QUAD_GPHY: + WARN_ON(priv->qphy_en_mask & + (1 << xbar_in_pdesc->quad_gphy_port)); + priv->qphy_en_mask |= + (1 << xbar_in_pdesc->quad_gphy_port); + break; + case SF2_PORT_T_SINGLE_GPHY: + WARN_ON(priv->sphy_en_mask != 0); + priv->sphy_en_mask |= 1; + break; + case SF2_PORT_T_SERDES: + WARN_ON(priv->serdes_en_mask != 0); + priv->serdes_en_mask |= 1; + break; + default: + WARN(1, "invalid hw desc"); + return -EINVAL; + } + } + + fixup_xbar_config(priv); + + return 0; +} + +/* + * + */ +static void dump_sf2_mapping(struct bcm_sf2_priv *priv) +{ + size_t i; + + for (i = 0; i < ARRAY_SIZE(priv->xbar_mapping); i++) { + dev_dbg(&priv->pdev->dev, + "XBAR mapping: %s => %s\n", + bcm63158_xbar_in_port_names[priv->xbar_mapping[i]], + bcm63158_xbar_out_port_names[i]); + } + + dev_dbg(&priv->pdev->dev, + "MUX1 mapping: %s => %s\n", + mux1_in_port_names[priv->mux1_mapping], + mux1_out_port_name); + + dev_dbg(&priv->pdev->dev, + "MUX2 mapping: %s => %s\n", + mux2_in_port_names[priv->mux2_mapping], + mux2_out_port_name); +} + + +/* + * reserve & remap registers region + */ +static int remap_regs(struct bcm_sf2_priv *priv) +{ + static const char *regs_name[] = { + "core", + "reg", + "mdio", + "acb", + }; + struct platform_device *pdev = priv->pdev; + struct resource *res; + void *addr[ARRAY_SIZE(regs_name)]; + size_t i; + + for (i = 0; i < ARRAY_SIZE(regs_name); i++) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + regs_name[i]); + if (!res) { + dev_err(&pdev->dev, "unable to get %s register " + "resource.\n", regs_name[i]); + return -ENODEV; + } + + addr[i] = devm_ioremap_resource(&pdev->dev, res); + if (!addr[i]) { + dev_err(&pdev->dev, "unable to ioremap %s\n", + regs_name[i]); + return -ENOMEM; + } + } + + priv->regs_core = addr[0]; + priv->regs_reg = addr[1]; + priv->regs_mdio = addr[2]; + priv->regs_acb = addr[3]; + + return 0; +} + +/* + * + */ +static int bcm_sf2_probe(struct platform_device *pdev) +{ + struct bcm_sf2_priv *priv; + struct reset_control *rst; + struct mii_bus *bus; + struct dsa_switch *ds; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->pdev = pdev; + + ret = of_read_sf2_config(pdev, priv); + if (ret) { + dev_err(&pdev->dev, "invalid device tree config\n"); + return ret; + } + + ret = remap_regs(priv); + if (ret) + return ret; + + rst = devm_reset_control_get(&pdev->dev, "sf2"); + if (IS_ERR(rst)) { + if (PTR_ERR(rst) != -EPROBE_DEFER) + dev_err(&pdev->dev, "missing sf2 reset control\n"); + return PTR_ERR(rst); + } + priv->rst = rst; + + priv->mii_bus = devm_mdiobus_alloc(&pdev->dev); + if (!priv->mii_bus) + return -ENOMEM; + + /* + * find mdio bus + */ + bus = priv->mii_bus; + bus->priv = priv; + bus->name = "bcm63158_sf2 MII bus"; + bus->parent = &pdev->dev; + bus->read = sf2_mii_read; + bus->write = sf2_mii_write; + bus->reset = sf2_mii_bus_reset; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio", pdev->name); + + priv->mdio_np = of_get_child_by_name(pdev->dev.of_node, "sf2,mdio"); + if (!priv->mdio_np) { + dev_err(&pdev->dev, "missing sf2,mdio node"); + return -ENODEV; + } + + ds = dsa_switch_alloc(&pdev->dev, SF2_PORT_COUNT); + if (!ds) + return -ENOMEM; + + ds->priv = priv; + ds->dev = &pdev->dev; + ds->ops = &bcm_sf2_dsa_ops; + priv->ds = ds; + + ret = dsa_register_switch(ds); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(&pdev->dev, "dsa register switch failed: %d\n", + ret); + return ret; + } + + /* all set */ + dump_sf2_mapping(priv); + platform_set_drvdata(pdev, priv); + bcm_sf2_dbg_init(priv); + return 0; +} + +/* + * + */ +static int bcm_sf2_remove(struct platform_device *pdev) +{ + struct bcm_sf2_priv *priv; + + bcm_sf2_dbg_exit(); + priv = platform_get_drvdata(pdev); + dsa_unregister_switch(priv->ds); + platform_set_drvdata(pdev, NULL); + return 0; +} + +static const struct of_device_id bcm63158_sf2_of_match[] = { + { .compatible = "brcm,bcm63158-sf2" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, bcm63158_sf2_of_match); + +/* + * + */ +struct platform_driver bcm63158_sf2_driver = { + .probe = bcm_sf2_probe, + .remove = bcm_sf2_remove, + .driver = { + .name = "bcm63158_sf2", + .of_match_table = bcm63158_sf2_of_match, + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(bcm63158_sf2_driver); + +MODULE_DESCRIPTION("BCM63158 SF2 driver"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_LICENSE("GPL"); diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_priv.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_priv.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_priv.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_priv.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,274 @@ +#ifndef SF2_PRIV_H_ +#define SF2_PRIV_H_ + +#include +#include +#include +#include +#include + +/* + * hardware description of SF2 switch ports & crossbar for 63158 SOC + */ +#define SF2_PORT_COUNT 9 +#define SF2_XBAR_IN_PORT_COUNT 4 +#define SF2_XBAR_OUT_PORT_COUNT 3 +#define SF2_NUM_EGRESS_QUEUES 8 + +enum sf2_port_type { + SF2_PORT_T_UNEXISTING, + SF2_PORT_T_RGMII, + SF2_PORT_T_QUAD_GPHY, + SF2_PORT_T_SINGLE_GPHY, + SF2_PORT_T_SERDES, + SF2_PORT_T_UNIMAC, + SF2_PORT_T_SYSPORT, + + SF2_PORT_T_XBAR_4X3, + SF2_PORT_T_XBAR_MUX1, + SF2_PORT_T_XBAR_MUX2, +}; + +struct sf2_port_hw_desc { + enum sf2_port_type port_type; + int quad_gphy_port; + int xbar_out_port; + bool is_imp; +}; + +/* + * device tree extracted configuration + */ +struct sf2_port_config { + int xbar_in_port; + int mux1_in_port; + int mux2_in_port; + int cpu_port; + int led_link_act; +}; + +struct sf2_config { + /* base mdio address to use for QUAD gphy (will use id => id + 3) */ + unsigned int qphy_base_id; + + /* mdio address to use for single gphy */ + unsigned int sphy_phy_id; + + /* mdio address to use for serdes phy */ + unsigned int serdes_phy_id; + + /* use inverted logic for serdes signal detect */ + bool serdes_inv_sd; +}; + +struct sf2_port { + const struct sf2_port_hw_desc *pdesc; + unsigned int id; + struct sf2_port_config cfg; + bool used; + bool enabled; +}; + +struct sf2_switchdev_ev_work { + struct bcm_sf2_priv *priv; + struct net_device *dev; + struct work_struct work; + struct switchdev_notifier_fdb_info info; + atomic_t free; +}; + +#define SF2_SWITCHDEV_EVENT_POOL_SZ 32 +struct bcm_sf2_fdb { + struct workqueue_struct *poll_wq; + struct workqueue_struct *update_wq; + struct notifier_block switchdev_notifier; + struct delayed_work poll_wk; + DECLARE_HASHTABLE(arl_hash, 8); + struct list_head cache; + struct mutex lock; + struct sf2_switchdev_ev_work sd_ev[SF2_SWITCHDEV_EVENT_POOL_SZ]; + unsigned long poll_delay; + unsigned int nr_entries; +}; + +struct bcm_sf2_priv { + void __iomem *regs_core; + void __iomem *regs_reg; + void __iomem *regs_mdio; + void __iomem *regs_acb; + struct regmap *leds_top_regmap; + + struct platform_device *pdev; + struct reset_control *rst; + struct mii_bus *mii_bus; + struct device_node *mdio_np; + struct dsa_switch *ds; + + /* extract DT configuration */ + struct sf2_config config; + + /* logical state extracted from config */ + unsigned int qphy_en_mask; + unsigned int sphy_en_mask; + unsigned int serdes_en_mask; + int xbar_mapping[SF2_XBAR_OUT_PORT_COUNT]; + int mux1_mapping; + int mux2_mapping; + + struct sf2_port ports[SF2_PORT_COUNT]; + struct sf2_port wan_port; + + /* FDB book keeping */ + struct bcm_sf2_fdb fdb; +}; + +static inline u32 gen_port_mask(struct bcm_sf2_priv *priv, bool cpu) +{ + u32 mask; + int i; + + mask = 0; + for (i = 0; i < SF2_PORT_COUNT; i++) { + struct sf2_port *port = &priv->ports[i]; + + if (!port->used) + continue; + + switch (port->pdesc->port_type) { + case SF2_PORT_T_UNIMAC: + case SF2_PORT_T_SYSPORT: + if (cpu) + mask |= (1 << i); + break; + + default: + if (!cpu) + mask |= (1 << i); + break; + } + } + return mask; +} + +static inline u32 gen_cpu_port_mask(struct bcm_sf2_priv *priv) +{ + return gen_port_mask(priv, true); +} + +static inline u32 gen_lan_port_mask(struct bcm_sf2_priv *priv) +{ + return gen_port_mask(priv, false); +} + +/* + * FDB monitoring functions + */ +int sf2_fdb_init(struct bcm_sf2_priv *priv); +void sf2_fdb_exit(struct bcm_sf2_priv *priv); + +/* + * ARL functions + */ + +struct sf2_arl_entry { + u8 port; + u8 mac[ETH_ALEN]; + u16 vid; + u8 is_valid:1; + u8 is_age:1; + u8 is_static:1; +}; + +void +sf2_arl_for_each(struct bcm_sf2_priv *priv, + int (*fn)(struct bcm_sf2_priv *, const struct sf2_arl_entry *, + void *), + void *data); + +int sf2_arl_delete(struct bcm_sf2_priv *priv, const u8 *mac, u16 vid); + +/* + * register accessors + */ +static inline u16 sw_core_readw(struct bcm_sf2_priv *priv, u32 off) +{ + u16 val; + + val = ioread16(priv->regs_core + off); + return val; +} + +static inline u32 sw_core_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + + val = ioread32(priv->regs_core + off); + return val; +} + +static inline void sw_core_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_core + off); +} + +static inline void sw_core_writell(struct bcm_sf2_priv *priv, u64 val, u32 off) +{ + iowrite64(val, priv->regs_core + off); +} + +static inline u64 sw_core_readll(struct bcm_sf2_priv *priv, u32 off) +{ + u64 val; + + val = ioread64(priv->regs_core + off); + return val; +} + +static inline u32 sw_reg_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + + val = ioread32(priv->regs_reg + off); + return val; +} + +static inline void sw_reg_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_reg + off); +} + + +static inline u32 sw_mdio_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + + val = ioread32(priv->regs_mdio + off); + return val; +} + +static inline void sw_mdio_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_mdio + off); +} + +static inline u32 sw_acb_readl(struct bcm_sf2_priv *priv, u32 off) +{ + u32 val; + val = ioread32(priv->regs_acb + off); + return val; +} + +static inline void sw_acb_writel(struct bcm_sf2_priv *priv, u32 val, u32 off) +{ + iowrite32(val, priv->regs_acb + off); +} + +#ifdef CONFIG_DEBUG_FS +void bcm_sf2_dbg_init(struct bcm_sf2_priv *priv); +void bcm_sf2_dbg_exit(void); +#else +static inline void bcm_sf2_dbg_init(struct bcm_sf2_priv *priv) {} +static inline void bcm_sf2_dbg_exit(void) {} +#endif + +#endif diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_regs.h linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_regs.h --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158./sf2/sf2_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63158/sf2/sf2_regs.h 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,331 @@ +#ifndef SF2_REGS_H_ +#define SF2_REGS_H_ + +/* + * apply to bcm63158 + */ + +/* ARL Table MAC/VID Entry N Registers (64 bit) + * + * BCM5325 and BCM5365 share most definitions below + */ +#define ARLTBL_MAC_MASK 0xffffffffffffULL +#define ARLTBL_VID_S 48 +#define ARLTBL_VID_MASK_25 0xff +#define ARLTBL_VID_MASK 0xfff +#define ARLTBL_DATA_PORT_ID_S_25 48 +#define ARLTBL_DATA_PORT_ID_MASK_25 0xf +#define ARLTBL_AGE_25 BIT(61) +#define ARLTBL_STATIC_25 BIT(62) +#define ARLTBL_VALID_25 BIT(63) + +/* ARL Table Data Entry N Registers (32 bit) */ +#define ARLTBL_DATA_PORT_ID_MASK 0x1ff +#define ARLTBL_TC(tc) ((3 & tc) << 11) +#define ARLTBL_AGE BIT(14) +#define ARLTBL_STATIC BIT(15) +#define ARLTBL_VALID BIT(16) + +/* + * CORE register block + */ + +/* + * control (page 0x0) + */ +#define SF2_CORE_PCTL(__p) (__p * 8) +# define PCTL_TXDIS (1 << 0) +# define PCTL_RXDIS (1 << 1) +# define PCTL_STP_NONE (0 << 5) +# define PCTL_STP_DISABLE (1 << 5) +# define PCTL_STP_BLOCKED (2 << 5) +# define PCTL_STP_LISTEN (3 << 5) +# define PCTL_STP_LEARN (4 << 5) +# define PCTL_STP_FORWARD (5 << 5) +# define PCTL_STP_MASK (7 << 5) + +#define SF2_CORE_IMP_CTL(__p) 0x40 +#define IMP_CTL_RX_BCAST_EN (1 << 2) +#define IMP_CTL_RX_MCAST_EN (1 << 3) +#define IMP_CTL_RX_UCAST_EN (1 << 4) + +#define SF2_CORE_SWMODE 0x58 +# define SWMODE_FWD_MANAGED (1 << 0) +# define SWMODE_FWD_EN (1 << 1) +# define SWMODE_RETRY_LIMIT_DIS (1 << 2) + +#define SF2_CORE_NEW_CTRL 0x108 +#define SF2_NEW_CTRL_MC_FWD_EN (1 << 7) +#define SF2_NEW_CTRL_UC_FWD_EN (1 << 6) + +#define SF2_CORE_CTRL 0x110 +# define SF2_CTRL_MII_DUMB_FWD_EN 0x40 +# define SF2_CTRL_MII2_VOL_SEL 0x02 + +#define SF2_CORE_UFL_FWD_MAP 0x190 + +#define SF2_CORE_MFL_FWD_MAP 0x1a0 + +#define SF2_CORE_IPMC_FWD_MAP 0x1b0 + +#define SF2_CORE_DIS_LEARN 0x1e0 + +#define SF2_CORE_WATCHDOG_CTRL 0x3c8 +# define SF2_SOFTWARE_RESET (1 << 7) +# define SF2_EN_CHIP_RST (1 << 6) +# define SF2_EN_SW_RST (1 << 4) + +/* + * management (page 0x2) + */ +#define SF2_CORE_BRCMTAG_CTRL 0x1018 +# define SF2_BRCMTAG_P8 (1 << 0) +# define SF2_BRCMTAG_P5 (1 << 1) +# define SF2_BRCMTAG_P7 (1 << 2) + +#define SF2_CORE_BRCMTAG2_CTRL 0x1050 +# define SF2_BRCMTAG2_Px(x) (1 << (x)) /* for P[012346] */ + +/* + * ARL access (page 0x5) + */ +#define SF2_CORE_ARL_RWCTL (0x2800) +# define SF2_ARL_START (1 << 7) +# define SF2_ARL_READ (1 << 0) + +#define SF2_CORE_ARL_MAC_IDX (0x2810) +#define SF2_CORE_ARL_VID_IDX (0x2840) + +#define SF2_CORE_ARL_MACENTRY(x) (0x2880 + (x) * 0x80) +#define SF2_CORE_ARL_FWDENTRY(x) (0x28c0 + (x) * 0x80) + +#define SF2_CORE_ARL_SRCH_CTRL 0x2a80 +#define ARL_SRCH_VLID BIT(0) +#define ARL_SRCH_STDN BIT(7) + +#define SF2_CORE_ARL_SRCH_ADR 0x2a88 + +#define SF2_CORE_ARL_SRCH_RSTx_MACVID(x) (0x2b00 + (x) * 0x80) + +#define SF2_CORE_ARL_SRCH_RSTx(x) (0x2b40 + (x) * 0x80) + +/* + * flow control (page 0x0a) + */ +#define SF2_CORE_FC_DIAG_CTRL (0x5000) +#define SF2_CORE_FC_QUEUE_CUR_COUNT(x) (SF2_CORE_FC_DIAG_CTRL + 0x30 * 8 + (x) * 16) +#define SF2_CORE_FC_QUEUE_PEAK_COUNT(x) (SF2_CORE_FC_DIAG_CTRL + 0x40 * 8 + (x) * 16) +#define SF2_CORE_FC_TOTAL_PEAK_COUNT (SF2_CORE_FC_DIAG_CTRL + 0x50 * 8) +#define SF2_CORE_FC_TOTAL_USED_COUNT (SF2_CORE_FC_DIAG_CTRL + 0x52 * 8) + +#define SF2_CORE_FC_PEAK_RX (SF2_CORE_FC_DIAG_CTRL + 0x54 * 8) + +/* + * lan threshold regs (page 0x0b) + */ +#define SF2_CORE_LAN_THRESH (0x5800) +#define LAN_THRESH_TXQ_RESERVED(q) (SF2_CORE_LAN_THRESH + 0x00 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_HYST(q) (SF2_CORE_LAN_THRESH + 0x10 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_PAUSE(q) (SF2_CORE_LAN_THRESH + 0x20 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_DROP(q) (SF2_CORE_LAN_THRESH + 0x30 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_TOT_HYST(q) (SF2_CORE_LAN_THRESH + 0x40 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_TOT_PAUSE(q) (SF2_CORE_LAN_THRESH + 0x50 * 16 + (q) * 16) +#define LAN_THRESH_TXQ_TOT_DROP(q) (SF2_CORE_LAN_THRESH + 0x60 * 16 + (q) * 16) + +/* + * mib (page 0x20 => 0x28) + */ +#define SF2_CORE_Px_MIB(x) (0x10000 + (x) * 0x800) + +/* + * QOS (page 0x30) + */ +#define SF2_CORE_PORT_TC2_QOS_MAP_PORT(x) (0x18380 + (x) * 0x20) +#define PRT_TO_QID_SHIFT 3 + +/* + * port based vlan (page 0x31) + */ +#define SF2_CORE_Px_VLAN_CTL(x) (0x18800 + (x) * 0x10) + +#define SF2_CORE_JUMBO_PORT_MASK_REG 0x20008 +# define SF2_JUMBO_EN_10_100_MASK (1 << 24) +# define SF2_JUMBO_FM_PORT_MASK (0x1ff) + +#define SF2_CORE_MIB_GD_FM_MAX_SIZE 0x20028 +# define SF2_GDM_FM_MAX_SIZE_MASK (0x3fff << 0) + +#define SF2_CORE_SA_LIMIT_ENABLE 0x22800 +#define SF2_CORE_SA_LRN_CNTR_RST 0x22810 +# define SF2_CORE_TOTAL_SA_LRN_CNTR_RST_MASK (BIT(15)) +#define SF2_CORE_TOTAL_SA_LIMIT_CTL 0x22880 +#define SF2_CORE_SA_LIMIT_CTL_PORT(x) (0x22890 + (x) * 0x10) +#define SF2_CORE_TOTAL_SA_LRN_CNTR 0x22980 +#define SF2_CORE_SA_LRN_CNTR_PORT(x) (0x22990 + (x) * 0x10) + +/* for P0-P7 */ +#define SF2_CORE_STS_OV_Px_STATE(x) (0x72000 + (x) * 0x10) +# define STS_OV_Px_LINK_MASK (1 << 0) +# define STS_OV_Px_FULL_DUPLEX_MASK (1 << 1) +# define STS_OV_Px_SPEED_10_MASK (0x0 << 2) +# define STS_OV_Px_SPEED_100_MASK (0x1 << 2) +# define STS_OV_Px_SPEED_1000_MASK (0x2 << 2) +# define STS_OV_Px_SPEED_ALL_MASK (0x3 << 2) +# define STS_OV_Px_RX_FLOW_CTL_MASK (1 << 4) +# define STS_OV_Px_TX_FLOW_CTL_MASK (1 << 5) +# define STS_OV_Px_SW_OVER_MASK (1 << 6) + +/* for P8 only */ +#define SF2_CORE_STS_OV_IMP_STATE (0x72080) +# define STS_OV_IMP_LINK_MASK (1 << 0) +# define STS_OV_IMP_FULL_DUPLEX_MASK (1 << 1) +# define STS_OV_IMP_SPEED_10_MASK (0x0 << 2) +# define STS_OV_IMP_SPEED_100_MASK (0x1 << 2) +# define STS_OV_IMP_SPEED_1000_MASK (0x2 << 2) +# define STS_OV_IMP_SPEED_ALL_MASK (0x3 << 2) +# define STS_OV_IMP_RX_FLOW_CTL_MASK (1 << 4) +# define STS_OV_IMP_TX_FLOW_CTL_MASK (1 << 5) +# define STS_OV_IMP_MII_SW_OVER_MASK (1 << 7) + +/* + * REG register block. + */ +#define SF2_REG_SW_CTRL 0x0 +#define SW_CTRL_P5_SPEED_MASK (0x3 << 9) +#define SW_CTRL_P5_SPEED_1G (0x0 << 9) +#define SW_CTRL_P5_SPEED_2G (0x1 << 9) +#define SW_CTRL_P5_SPEED_2_5G (0x2 << 9) +#define SW_CTRL_P5_SPEED_3G (0x3 << 9) +#define SW_CTRL_P7_SPEED_MASK (0x3 << 5) +#define SW_CTRL_P7_SPEED_1G (0x0 << 5) +#define SW_CTRL_P7_SPEED_2G (0x1 << 5) +#define SW_CTRL_P7_SPEED_2_5G (0x2 << 5) +#define SW_CTRL_P7_SPEED_3G (0x3 << 5) +#define SW_CTRL_P8_SPEED_MASK (0x3 << 3) +#define SW_CTRL_P8_SPEED_1G (0x0 << 3) +#define SW_CTRL_P8_SPEED_2G (0x1 << 3) +#define SW_CTRL_P8_SPEED_2_5G (0x2 << 3) +#define SW_CTRL_P8_SPEED_3G (0x3 << 3) + +#define SF2_REG_PHY_TEST 0x18 + +#define SF2_REG_QPHY_CTRL 0x1c +# define QPHY_CTRL_IDDQ_BIAS (1 << 0) +# define QPHY_CTRL_EXT_PWR_DOWN_SHIFT 1 +# define QPHY_CTRL_EXT_PWR_DOWN(__p) (1 << ((__p) + 1)) +# define QPHY_CTRL_EXT_PWR_DOWN_ALL (0xf << QPHY_CTRL_EXT_PWR_DOWN_SHIFT) +# define QPHY_CTRL_FORCE_DLL_EN (1 << 5) +# define QPHY_CTRL_IDDQ_GLOBAL_PWR (1 << 6) +# define QPHY_CTRL_CLK_25_DISABLE (1 << 7) +# define QPHY_CTRL_PHY_RESET (1 << 8) +# define QPHY_CTRL_PHY_BASE_ADDR_SHIFT (12) +# define QPHY_CTRL_PHY_BASE_ADDR_MASK (0x1f << QPHY_CTRL_PHY_BASE_ADDR_SHIFT) + +#define SF2_REG_SPHY_CTRL 0x24 +# define SPHY_CTRL_IDDQ_BIAS (1 << 0) +# define SPHY_CTRL_EXT_PWR_DOWN (1 << 1) +# define SPHY_CTRL_FORCE_DLL_EN (1 << 2) +# define SPHY_CTRL_IDDQ_GLOBAL_PWR (1 << 3) +# define SPHY_CTRL_CLK_25_DISABLE (1 << 4) +# define SPHY_CTRL_PHY_RESET (1 << 5) +# define SPHY_CTRL_PHY_BASE_ADDR_SHIFT (8) +# define SPHY_CTRL_PHY_BASE_ADDR_MASK (0x1f << SPHY_CTRL_PHY_BASE_ADDR_SHIFT) + +#define SF2_REG_LED_CTRL(__p) (0x40 + 0xc * (__p)) +# define LED_CTRL_RX_ACT_EN (1 << 0) +# define LED_CTRL_TX_ACT_EN (1 << 1) +# define LED_CTRL_ACT_SEL (1 << 5) + +#define SF2_REG_XBAR_CTRL 0xcc + +enum { + E_XBAR_MUX_SERDES = 0x0, + E_XBAR_MUX_SGPHY = 0x1, + E_XBAR_MUX_RGMII1 = 0x2, + E_XBAR_MUX_RGMII2 = 0x3, + E_XBAR_MUX_QGPHY = 0x4, +}; + +#define XBAR_PORT_MASK 0x3 +#define XBAR_WAN_SHIFT 6 +#define XBAR_MUX2_MASK (1 << 5) +#define XBAR_MUX1_MASK (1 << 4) +#define XBAR_P6_SHIFT 2 +#define XBAR_P4_SHIFT 0 + + +#define SF2_REG_SSRD_CTRL 0x424 +# define SSRD_CTRL_IDDQ_EN (1 << 0) +# define SSRD_CTRL_PDOWN_EN (1 << 1) +# define SSRD_CTRL_RESET_PLL (1 << 3) +# define SSRD_CTRL_RESET_MDIO (1 << 4) +# define SSRD_CTRL_RESET_SERDES (1 << 5) +# define SSRD_CTRL_PHY_BASE_ADDR_SHIFT 8 +# define SSRD_CTRL_PHY_BASE_ADDR_MASK (0xf << SSRD_CTRL_PHY_BASE_ADDR_SHIFT) + + +#define SF2_REG_SSRD_STAT 0x428 +#define SSRD_STAT_LINK_UP (1 << 0) +#define SSRD_STAT_RX_SIGDET (1 << 1) +#define SSRD_STAT_RX_BITALIGN (1 << 2) +#define SSRD_STAT_RX_SGMII_MODE (1 << 3) +#define SSRD_STAT_RX_SYNC_STATUS (1 << 4) +#define SSRD_STAT_RX_PLL_LOCK (1 << 5) +#define SSRD_STAT_RX_DEBOUNCED_SIGDET (1 << 6) + + +#define SF2_REG_SSRD_APD_CTRL 0x42c +# define SSRD_APD_CTRL_INV_SD (1 << 3) + +/* + * MDIO block + */ +#define SF2_MDIO_CMD 0x0 + +# define CMD_BUSY (1 << 29) +# define CMD_LIFA (1 << 28) + +# define CMD_OPCODE_SHIFT 26 +# define CMD_OPCODE_MASK (3 << CMD_OPCODE_SHIFT) +# define OPCODE_C45_ADDR (0 << CMD_OPCODE_SHIFT) +# define OPCODE_C22_WRITE (1 << CMD_OPCODE_SHIFT) +# define OPCODE_C45_WRITE (1 << CMD_OPCODE_SHIFT) +# define OPCODE_C22_READ (2 << CMD_OPCODE_SHIFT) +# define OPCODE_C45_READ (3 << CMD_OPCODE_SHIFT) + +# define CMD_PHY_ADDR(__phy) ((__phy & 0x1f) << 21) +# define CMD_REG_ADDR(__reg) ((__reg & 0x1f) << 16) + +# define CMD_DATA(__data) ((__data & 0xffff) << 0) +# define CMD_REG_DATA_MASK 0xffff + +#define SF2_MDIO_CFG 0x4 +#define MDIO_CLAUSE_22_MASK (1 << 0) +#define MDIO_CLK_DIV_SHIFT 4 +#define MDIO_CLK_DIV_MASK (0xff << MDIO_CLK_DIV_SHIFT) + + +/* + * ACB block + */ +#define SF2_ACB_CONTROL_REG 0x0 +#define ACB_CONTROL_EN_MASK (1 << 0) +#define ACB_CONTROL_ALG2_MASK (1 << 1) +#define ACB_CONTROL_FLUSHQ_SHIFT 2 +#define ACB_CONTROL_FLUSHQ_MASK (0x7 << ACB_CONTROL_FLUSHQ_SHIFT) +#define ACB_CONTROL_EOP_DELAY_SHIFT 5 +#define ACB_CONTROL_EOP_DELAY_MASK (0xff << ACB_CONTROL_EOP_DELAY_SHIFT) + +#define SF2_ACB_XON_TRESH_REG 0x4 +#define XON_TRESH_XON_BUFS_SHIFT 0 +#define XON_TRESH_XON_BUFS_MASK (0x7ff << XON_TRESH_XON_BUFS_SHIFT) +#define XON_TRESH_TOTAL_XON_BUFS_SHIFT 11 +#define XON_TRESH_TOTAL_XON_BUFS_MASK (0x7ff << XON_TRESH_TOTAL_XON_BUFS_SHIFT) + +#define SF2_ACB_QCFG_REG(p,q) (0x8 + (p) * 8 * 4 + (q) * 4) +#define ACB_QCFG_XOFF_THRESH_SHIFT 0 +#define ACB_QCFG_XOFF_THRESH_MASK (0x7ff << ACB_QCFG_XOFF_THRESH_SHIFT) + +#define SF2_ACB_QINFLIGHT_REG(p,q) (0x108 + ((p) * 8 * 4) + (q) * 4) + +#endif /* !SF2_REGS_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner./Makefile linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner/Makefile --- linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/broadcom/bcm63xx_enet_runner/Makefile 2021-03-04 13:20:59.020838944 +0100 @@ -0,0 +1,5 @@ +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_enet_runner_mod.o +obj-$(CONFIG_BCM63XX_ENET_RUNNER) += bcm63xx_sf2.o + +bcm63xx_enet_runner_mod-y += bcm63xx_enet_runner.o +bcm63xx_enet_runner_mod-$(CONFIG_DEBUG_FS) += bcm63xx_enet_runner_debug.o diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/wintegra./Kconfig linux-5.4.60-fbx/drivers/net/ethernet/wintegra/Kconfig --- linux-5.4.60-fbx/drivers/net/ethernet/wintegra./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/wintegra/Kconfig 2021-03-04 13:20:59.274172288 +0100 @@ -0,0 +1,10 @@ +config NET_VENDOR_WINTEGRA + bool + +config WINTEGRA_WINPATH3_ETH + tristate "Wintegra Winpath3 internal mac support" + depends on WINTEGRA_WINPATH3 + select NET_VENDOR_WINTEGRA + select NET_CORE + select MII + select PHYLIB diff -Nruw linux-5.4.60-fbx/drivers/net/ethernet/wintegra./Makefile linux-5.4.60-fbx/drivers/net/ethernet/wintegra/Makefile --- linux-5.4.60-fbx/drivers/net/ethernet/wintegra./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/ethernet/wintegra/Makefile 2021-03-04 13:20:59.274172288 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_WINTEGRA_WINPATH3_ETH) += wp3_eth.o diff -Nruw linux-5.4.60-fbx/drivers/net/wireless/marvell/mwl8k_new./Makefile linux-5.4.60-fbx/drivers/net/wireless/marvell/mwl8k_new/Makefile --- linux-5.4.60-fbx/drivers/net/wireless/marvell/mwl8k_new./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/net/wireless/marvell/mwl8k_new/Makefile 2021-03-04 13:20:59.424172295 +0100 @@ -0,0 +1,12 @@ +mwl8k_new-$(CONFIG_DEBUG_FS) += debugfs.o +mwl8k_new-y += fw.o +mwl8k_new-y += main.o +mwl8k_new-y += utils.o + +mwl8k_new-y += svc_console.o +mwl8k_new-y += svc_dma_test.o +mwl8k_new-y += svc_vtty.o + +mwl8k_new-y += wifi_core.o + +obj-$(CONFIG_MWL8K_NEW) += mwl8k_new.o --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/of/configfs.c 2021-03-04 13:20:59.507505632 +0100 @@ -0,0 +1,279 @@ +/* + * Configfs entries for device-tree + * + * Copyright (C) 2013 - Pantelis Antoniou + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "of_private.h" + +struct cfs_overlay_item { + struct config_item item; + + char path[PATH_MAX]; + + const struct firmware *fw; + struct device_node *overlay; + int ov_id; + + void *dtbo; + int dtbo_size; +}; + +static inline struct cfs_overlay_item *to_cfs_overlay_item( + struct config_item *item) +{ + return item ? container_of(item, struct cfs_overlay_item, item) : NULL; +} + +static ssize_t cfs_overlay_item_path_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + return sprintf(page, "%s\n", overlay->path); +} + +static ssize_t cfs_overlay_item_path_store(struct config_item *item, + const char *page, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + const char *p = page; + char *s; + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy to path buffer (and make sure it's always zero terminated */ + count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p); + overlay->path[sizeof(overlay->path) - 1] = '\0'; + + /* strip trailing newlines */ + s = overlay->path + strlen(overlay->path); + while (s > overlay->path && *--s == '\n') + *s = '\0'; + + pr_debug("%s: path is '%s'\n", __func__, overlay->path); + + err = request_firmware(&overlay->fw, overlay->path, NULL); + if (err != 0) + goto out_err; + + err = of_overlay_fdt_apply((void *)overlay->fw->data, + overlay->fw->size, + &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + + release_firmware(overlay->fw); + overlay->fw = NULL; + + overlay->path[0] = '\0'; + return err; +} + +static ssize_t cfs_overlay_item_status_show(struct config_item *item, + char *page) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + return sprintf(page, "%s\n", + overlay->ov_id >= 0 ? "applied" : "unapplied"); +} + +CONFIGFS_ATTR(cfs_overlay_item_, path); +CONFIGFS_ATTR_RO(cfs_overlay_item_, status); + +static struct configfs_attribute *cfs_overlay_attrs[] = { + &cfs_overlay_item_attr_path, + &cfs_overlay_item_attr_status, + NULL, +}; + +ssize_t cfs_overlay_item_dtbo_read(struct config_item *item, + void *buf, size_t max_count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + pr_debug("%s: buf=%p max_count=%zu\n", __func__, + buf, max_count); + + if (overlay->dtbo == NULL) + return 0; + + /* copy if buffer provided */ + if (buf != NULL) { + /* the buffer must be large enough */ + if (overlay->dtbo_size > max_count) + return -ENOSPC; + + memcpy(buf, overlay->dtbo, overlay->dtbo_size); + } + + return overlay->dtbo_size; +} + +ssize_t cfs_overlay_item_dtbo_write(struct config_item *item, + const void *buf, size_t count) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + int err; + + /* if it's set do not allow changes */ + if (overlay->path[0] != '\0' || overlay->dtbo_size > 0) + return -EPERM; + + /* copy the contents */ + overlay->dtbo = kmemdup(buf, count, GFP_KERNEL); + if (overlay->dtbo == NULL) + return -ENOMEM; + + overlay->dtbo_size = count; + + err = of_overlay_fdt_apply((void *)overlay->fw->data, + overlay->dtbo_size, + &overlay->ov_id); + if (err != 0) + goto out_err; + + return count; + +out_err: + kfree(overlay->dtbo); + overlay->dtbo = NULL; + overlay->dtbo_size = 0; + + return err; +} + +CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M); + +static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = { + &cfs_overlay_item_attr_dtbo, + NULL, +}; + +static void cfs_overlay_release(struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + if (overlay->ov_id >= 0) + of_overlay_remove(&overlay->ov_id); + if (overlay->fw) + release_firmware(overlay->fw); + /* kfree with NULL is safe */ + kfree(overlay->dtbo); + kfree(overlay); +} + +static struct configfs_item_operations cfs_overlay_item_ops = { + .release = cfs_overlay_release, +}; + +static struct config_item_type cfs_overlay_type = { + .ct_item_ops = &cfs_overlay_item_ops, + .ct_attrs = cfs_overlay_attrs, + .ct_bin_attrs = cfs_overlay_bin_attrs, + .ct_owner = THIS_MODULE, +}; + +static struct config_item *cfs_overlay_group_make_item( + struct config_group *group, const char *name) +{ + struct cfs_overlay_item *overlay; + + overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); + if (!overlay) + return ERR_PTR(-ENOMEM); + overlay->ov_id = -1; + + config_item_init_type_name(&overlay->item, name, &cfs_overlay_type); + return &overlay->item; +} + +static void cfs_overlay_group_drop_item(struct config_group *group, + struct config_item *item) +{ + struct cfs_overlay_item *overlay = to_cfs_overlay_item(item); + + config_item_put(&overlay->item); +} + +static struct configfs_group_operations overlays_ops = { + .make_item = cfs_overlay_group_make_item, + .drop_item = cfs_overlay_group_drop_item, +}; + +static struct config_item_type overlays_type = { + .ct_group_ops = &overlays_ops, + .ct_owner = THIS_MODULE, +}; + +static struct configfs_group_operations of_cfs_ops = { + /* empty - we don't allow anything to be created */ +}; + +static struct config_item_type of_cfs_type = { + .ct_group_ops = &of_cfs_ops, + .ct_owner = THIS_MODULE, +}; + +struct config_group of_cfs_overlay_group; + +static struct configfs_subsystem of_cfs_subsys = { + .su_group = { + .cg_item = { + .ci_namebuf = "device-tree", + .ci_type = &of_cfs_type, + }, + }, + .su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex), +}; + +static int __init of_cfs_init(void) +{ + int ret; + + pr_info("%s\n", __func__); + + config_group_init(&of_cfs_subsys.su_group); + config_group_init_type_name(&of_cfs_overlay_group, "overlays", + &overlays_type); + configfs_add_default_group(&of_cfs_overlay_group, + &of_cfs_subsys.su_group); + + ret = configfs_register_subsystem(&of_cfs_subsys); + if (ret != 0) { + pr_err("%s: failed to register subsys\n", __func__); + goto out; + } + pr_info("%s: OK\n", __func__); +out: + return ret; +} +late_initcall(of_cfs_init); --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/pci/controller/pcie-bcm63xx.c 2021-03-04 13:20:59.517505633 +0100 @@ -0,0 +1,973 @@ +/* + * pcie-bcm63xx.c for pcie-bcm63x + * Created by on Wed Jun 5 14:08:58 2019 + */ + +/* + * inspired by pcie-bcm63xx.c from broadcom refsw release 5.02L.07-test9 + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "pcie-bcm63xx.h" +#include "../pci.h" + +struct port_config { + u32 speed; + u32 num_lanes; + u32 ssc; + u64 dram_size; +}; + +struct bcm63xx_pcie { + struct device *dev; + struct pci_host_bridge *host; + + unsigned long regs_phys; + void __iomem *regs; + + int irq; + struct resource io_res; + resource_size_t io_offset; + struct resource mem_res; + resource_size_t mem_offset; + struct resource bus_range; + + u32 core_speed; + struct port_config pcfg; + u32 misc_revision; + int rcal_1um_vert_value; +}; + +/* + * make it so that resource_size() return 0. + */ +static inline void make_invalid_resource(struct resource *r) +{ + r->start = 0; + r->end = -1; +} + +static inline void bcm_pcie_writel(u32 val, struct bcm63xx_pcie *pcie, + u32 offset) +{ + dev_dbg(pcie->dev, "bcm_pcie_writel: value %08x offset %08x\n", + val, offset); + writel(val, pcie->regs + offset); +} + +static inline u32 bcm_pcie_readl(struct bcm63xx_pcie *pcie, u32 offset) +{ + u32 val = readl(pcie->regs + offset); + + dev_dbg(pcie->dev, "bcm_pcie_readl: value %08x offset %08x\n", + val, offset); + return val; +} + +/* + * PCIe phy indirect read/write helpers. + */ +#define PCIE_PHY_TRIES 100 + +static int bcm_pcie_phy_read(struct bcm63xx_pcie *pcie, u32 phyaddr, u32 regaddr, + u32 *out_data) +{ + + u32 reg; + int tries = PCIE_PHY_TRIES; + + reg = PHY_ADDR_READ | + PHY_ADDR_PHY(phyaddr) | + PHY_ADDR_REG(regaddr); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PHY_ADDR); + udelay(1000); + + do { + u32 v = bcm_pcie_readl(pcie, BCM63XX_PCIE_PHY_RD_DATA); + + if (v & PHY_RD_DATA_DONE) { + *out_data = v & PHY_RD_DATA_MASK; + return 0; + } + udelay(10); + --tries; + } while (tries < PCIE_PHY_TRIES); + + dev_err(pcie->dev, "bcm_pcie_phy_read: timedout reading from " + "phy %x reg %x.\n", + phyaddr, regaddr); + return -ETIMEDOUT; +} + +static int bcm_pcie_phy_write(struct bcm63xx_pcie *pcie, u32 phyaddr, + u32 regaddr, u32 data) +{ + u32 reg; + int tries = PCIE_PHY_TRIES; + + reg = PHY_ADDR_WRITE | + PHY_ADDR_PHY(phyaddr) | + PHY_ADDR_REG(regaddr); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PHY_ADDR); + udelay(1000); + + reg = (data & PHY_WR_DATA_MASK) | PHY_WR_DATA_TRIG; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PHY_WR_DATA); + + do { + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_PHY_WR_DATA); + if (reg & PHY_WR_DATA_TRIG) + return 0; + --tries; + } while (tries < PCIE_PHY_TRIES); + + dev_err(pcie->dev, "bcm_pcie_phy_write: timedout writing from " + "phy %x reg %x.\n", + phyaddr, regaddr); + return -ETIMEDOUT; +} + +/* + * UBUS configuration + */ +static int bcm63xx_pcie_ubus_config(struct ubus4_master *m) +{ + ubus_master_apply_credits(m); + ubus_master_set_congestion_threshold(m, 0); + ubus_master_remap_port(m); + return 0; +} + +/* + * fetch various resources from device tree. + */ +static int bcm63xx_pcie_parse_ranges(struct bcm63xx_pcie *pcie) +{ + struct of_pci_range_parser parser; + struct of_pci_range range; + int error; + + error = of_pci_range_parser_init(&parser, pcie->dev->of_node); + if (error) { + dev_err(pcie->dev, "of_pci_range_parser_init failed: %d\n", + error); + return error; + } + + for_each_of_pci_range(&parser, &range){ + struct resource res; + + error = of_pci_range_to_resource(&range, pcie->dev->of_node, + &res); + if (error) + return error; + + switch (range.flags & IORESOURCE_TYPE_BITS) { + case IORESOURCE_MEM: + pcie->mem_res = res; + pcie->mem_offset = res.start - range.pci_addr; + break; + case IORESOURCE_IO: + pcie->io_offset = res.start - range.pci_addr; + pcie->io_res = res; + break; + } + } + + error = of_pci_parse_bus_range(pcie->dev->of_node, &pcie->bus_range); + if (error) { + dev_warn(pcie->dev, "unable to parse bus range. using " + "0-255.\n"); + pcie->bus_range.flags = IORESOURCE_BUS; + pcie->bus_range.start = 0x0; + pcie->bus_range.end = 0xff; + } + + dev_dbg(pcie->dev, "IO resource: %pR\n", &pcie->io_res); + dev_dbg(pcie->dev, "MEM resource: %pR\n", &pcie->mem_res); + dev_dbg(pcie->dev, "BUS resource: %pR\n", &pcie->bus_range); + + return 0; +} + +static int get_soc_dram_size(struct bcm63xx_pcie *pcie, u64 *out_dram_size) +{ + struct of_phandle_args args; + int err; + u64 reg[2]; + + err = of_parse_phandle_with_args(pcie->dev->of_node, "brcm,dram", + 0, 0, &args); + if (err) { + dev_err(pcie->dev, "unable to parse brcm,dram phandle.\n"); + return err; + } + + err = of_property_read_u64_array(args.np, "reg", reg, 2); + if (err) { + dev_err(pcie->dev, "unable to read reg from dram node: %d.\n", + err); + return err; + } + + *out_dram_size = reg[1]; + return 0; +} + +/* + * SoC specific DT configuration. speed can be overridden here, or + * left at 0 (use SoC default supported speed). + * + * SSC might be of interest for the hardware folks and CE + * certification. + * + * omitted from here: + * - phy low power mode select. + * - keep PCIe core powered on on link down during init. + * - error logging activation. + */ +static int bcm63xx_pcie_parse_dt_port_config(struct bcm63xx_pcie *pcie) +{ + int error; + + error = of_property_read_u32(pcie->dev->of_node, "brcm,speed", + &pcie->pcfg.speed); + if (error) + pcie->pcfg.speed = PCIE_SPEED_DEFAULT; + + error = of_property_read_u32(pcie->dev->of_node, "brcm,num-lanes", + &pcie->pcfg.num_lanes); + if (error) + pcie->pcfg.num_lanes = 1; + + error = of_property_read_u32(pcie->dev->of_node, "brcm,ssc", + &pcie->pcfg.ssc); + if (error) + pcie->pcfg.ssc = 0; + + error = get_soc_dram_size(pcie, &pcie->pcfg.dram_size); + if (error) + /* + * this is mandatory. + */ + return error; + + dev_dbg(pcie->dev, "speed: %d, num-lanes: %d, ssc: %d.\n", + pcie->pcfg.speed, pcie->pcfg.num_lanes, pcie->pcfg.ssc); + return 0; +} + +/* + * read vendor/device id, get chip revision from PCIe misc registers. + */ +static int bcm63xx_pcie_init(struct bcm63xx_pcie *pcie) +{ + u32 reg; + u32 link_width; + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_VENDOR_ID); + if (reg == 0xdeaddead) { + dev_err(pcie->dev, "dead read from PCIe register, is the " + "PCIe cable bad?\n"); + return -ENXIO; + } + + dev_dbg(pcie->dev, "vendor %04x, device %04x\n", + VENDOR_ID_VENDOR(reg), VENDOR_ID_DEVICE(reg)); + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_LINK_CAP); + link_width = LINK_CAP_WIDTH(reg); + pcie->core_speed = LINK_CAP_SPEED(reg); + + dev_dbg(pcie->dev, "link speed: 0x%x, width 0x%x\n", pcie->core_speed, + link_width); + + if (pcie->pcfg.num_lanes > link_width) { + dev_info(pcie->dev, "limiting num-lanes to %d\n", link_width); + pcie->pcfg.num_lanes = link_width; + } + + if (pcie->pcfg.speed > pcie->core_speed) { + dev_info(pcie->dev, "limiting speed to gen%d\n", + pcie->core_speed); + pcie->pcfg.speed = pcie->core_speed; + } + + pcie->misc_revision = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_REVISION); + dev_dbg(pcie->dev, "misc revision: 0x%04x\n", pcie->misc_revision); + + if (pcie->misc_revision < 0x320) { + /* + * chip revisions below 0x320 need access to the MISC + * register block to reset the PCIe core, which we do + * not need to support on the bcm63158. + * + * revisit later if needed. + */ + dev_err(pcie->dev, "chip revision 0x%04x unsupported. " + "can't reset PCIe chip.\n", pcie->misc_revision); + return -ENOTSUPP; + } + return 0; +} + +static int bcm63xx_pcie_phy_configure_gen2(struct bcm63xx_pcie *pcie) +{ + dev_info(pcie->dev, "configuring for GEN2 speed.\n"); + + /* + * nothing do do for bcm63158, work arounds for chip revision + * below 0x303 (everybody needs a 0x303) are fixed on chip + * revision 0x320 (available on bcm63158). + * + * we only need to configure SSC if required. + */ + if (!pcie->pcfg.ssc) + return 0; + + if (pcie->misc_revision < 0x303) { + /* + * SSC Parameters + * Workaround (for early gen2 cards): + * Block 0x1100, Register 0xA = 0xea3c + * Block 0x1100, Register 0xB = 0x04e7 + * Block 0x1100, Register 0xC = 0x0039 + *-Block 0x1100 fixed in 63148A0, 63381B0, 63138B0 + * but ok to write anyway + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x1100); + bcm_pcie_phy_write(pcie, 0, 0x0a, 0xea3c); + bcm_pcie_phy_write(pcie, 0, 0x0b, 0x04e7); + bcm_pcie_phy_write(pcie, 0, 0x0c, 0x0039); + } + + /* + * SSC Parameters + * Block 0x2200, Register 5 = 0x5044 + * // VCO parameters for fractional mode, -175ppm + * Block 0x2200, Register 6 = 0xfef1 + * // VCO parameters for fractional mode, -175ppm + * Block 0x2200, Register 7 = 0xe818 + * // VCO parameters for fractional mode, -175ppm + * + * Notes: + * - Only need to apply those fixes when enabling Spread + * Spectrum Clocking (SSC), which would likely be a flash + * option + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x2200); + bcm_pcie_phy_write(pcie, 0, 0x05, 0x5044); + bcm_pcie_phy_write(pcie, 0, 0x06, 0xfef1); + bcm_pcie_phy_write(pcie, 0, 0x07, 0xe818); + + return 0; +} + +static int bcm63xx_pcie_phy_configure_gen3(struct bcm63xx_pcie *pcie) +{ + dev_info(pcie->dev, "configuring for GEN3 speed.\n"); + + /* + * nothing do do for bcm63158, work arounds for chip revision + * below 0x320 are fixed on chip revision 0x322 (available on + * bcm63158). chip revision 0x320 seems to be found only on + * bcm63158 A0 (which we do not use). + * + * we only need to enable SSC if required. + */ + + if (!pcie->pcfg.ssc) + return 0; + + /* + * no GEN3 pcie cores on 63158, revisit later if needed. + */ + return -ENOTSUPP; +} + +/* + * resistor calibration configuration: this is fetched from the + * bcm(63158) procmon driver, and programmed to the PCIe hardware + * here. + */ +static int bcm63xx_pcie_gen12_rescal_set(struct bcm63xx_pcie *pcie) +{ + u32 data; + + if (pcie->rcal_1um_vert_value < 0) { + dev_warn(pcie->dev, "invalid rcal 1um vert value %d, " + "rescal unchanged.\n", pcie->rcal_1um_vert_value); + return 0; + } + + dev_info(pcie->dev, "bcm63xx_pcie_gen12_rescal_set: 0x%x\n", + pcie->rcal_1um_vert_value); + + /* + * Rcal Calibration Timers + * Block 0x1000, Register 1, bit 4(enable), and 3:0 (value) + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x1000); + bcm_pcie_phy_read(pcie, 0, 1, &data); + data = ((data & 0xffe0) | (pcie->rcal_1um_vert_value & 0xf) | + (1 << 4)); /* enable */ + bcm_pcie_phy_write(pcie, 0, 1, data); + + return 0; +} + +static int bcm63xx_pcie_rescal_set(struct bcm63xx_pcie *pcie) +{ + int error = 0; + + switch (pcie->core_speed) { + case PCIE_SPEED_GEN3: + return -ENOTSUPP; + default: + error = bcm63xx_pcie_gen12_rescal_set(pcie); + break; + } + + if (error) + return error; + return 0; +} + +static int bcm63xx_pcie_phy_config(struct bcm63xx_pcie *pcie) +{ + int error = 0; + + error = bcm63xx_pcie_rescal_set(pcie); + if (error) + return error; + + switch (pcie->core_speed) { + case PCIE_SPEED_GEN1: + /* nothing to do for gen1/default speed */ + break; + case PCIE_SPEED_GEN2: + error = bcm63xx_pcie_phy_configure_gen2(pcie); + break; + case PCIE_SPEED_GEN3: + error = bcm63xx_pcie_phy_configure_gen3(pcie); + break; + } + + if (error) { + dev_err(pcie->dev, "unable to configure PCIe phy for GEN%d\n", + pcie->core_speed); + return error; + } + + return 0; +} + +static int bcm63xx_pcie_phy_enable_ssc_gen2(struct bcm63xx_pcie *pcie, + bool enable) +{ + u32 data; + int timeout = 40; + + dev_info(pcie->dev, "%sabling SSC on GEN2 phy.\n", + enable ? "en" : "dis"); + + /* + * SSC disabled when PCIe core comes out of reset to allow PLL + * sync to happen write sscControl0 register + * ssc_mode_enable_ovrd & ssc_mode_enable_ovrd_val + */ + bcm_pcie_phy_write(pcie, 0, 0x1f, 0x1100); + bcm_pcie_phy_read(pcie, 0, 0x02, &data); + if (enable) + data |= 0xc000; /* bit 15:14 11'b to enable SSC */ + else + data &= ~0xc000; /* bit 15:14 00'b to disable SSC */ + bcm_pcie_phy_write(pcie, 0, 0x02, data); + + /* + * TODO: Check the status to see if SSC is set or not + */ + while (timeout) { + bcm_pcie_phy_read(pcie, 0, 0x01, &data); + + /* + * bit 10 reflects state of SSC ? Then what to make of + * the TODO comment above ? + */ + if (!!(data & (1 << 10)) == enable) + break; + --timeout; + udelay(1000); + } + + if (!timeout) + return -ETIMEDOUT; + + return 0; +} + +static int bcm63xx_pcie_phy_enable_ssc_gen3(struct bcm63xx_pcie *pcie, + bool enable) +{ + dev_info(pcie->dev, "%sabling SSC on GEN3 phy.\n", + enable ? "en" : "dis"); + + /* + * no GEN3 pcie cores on 63158, revisit later if needed. + */ + return -ENOTSUPP; +} + +static int bcm63xx_pcie_phy_enable_ssc(struct bcm63xx_pcie *pcie, bool enable) +{ + int error = 0; + + if (!pcie->pcfg.ssc) + return 0; + + switch (pcie->core_speed) { + case PCIE_SPEED_DEFAULT: + case PCIE_SPEED_GEN1: + break; + case PCIE_SPEED_GEN2: + error = bcm63xx_pcie_phy_enable_ssc_gen2(pcie, enable); + break; + case PCIE_SPEED_GEN3: + error = bcm63xx_pcie_phy_enable_ssc_gen3(pcie, enable); + break; + } + + if (error) { + dev_err(pcie->dev, "unable to %sable SSC: %d\n", + enable ? "en" : "dis", error); + return error; + } + return 0; +} + +static void __bcm63xx_pcie_set_reset(struct bcm63xx_pcie *pcie, bool assert) +{ + u32 reg; + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_CTRL); + if (assert) + reg &= ~MISC_CTRL_PCIE_RESETn; + else + reg |= MISC_CTRL_PCIE_RESETn; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_CTRL); +} + +static inline void bcm63xx_pcie_assert_reset(struct bcm63xx_pcie *pcie) +{ + __bcm63xx_pcie_set_reset(pcie, true); +} + +static inline void bcm63xx_pcie_deassert_reset(struct bcm63xx_pcie *pcie) +{ + __bcm63xx_pcie_set_reset(pcie, false); + +} + +static int bcm63xx_pcie_core_set_speed(struct bcm63xx_pcie *pcie) +{ + u32 reg; + + if (pcie->pcfg.speed == PCIE_SPEED_DEFAULT) + return 0; + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_PRIV1_LINK_CAP); + reg &= ~PRIV1_LINK_CAP_SPEED_MASK; + reg |= PRIV1_LINK_CAP_SPEED(pcie->pcfg.speed); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PRIV1_LINK_CAP); + + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_LINK_STATUS_CONTROL2); + reg &= ~LINK_STATUS_CONTROL2_SPEED_MASK; + reg |= LINK_STATUS_CONTROL2_SPEED(pcie->pcfg.speed); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_LINK_STATUS_CONTROL2); + + mdelay(10); + + return 0; +} + +/* + * reset PCIe core, configure phy, and release core reset. + */ +static int bcm63xx_pcie_reset(struct bcm63xx_pcie *pcie) +{ + int error; + + bcm63xx_pcie_assert_reset(pcie); + + error = bcm63xx_pcie_phy_config(pcie); + if (error) + return error; + + /* + * disable SSC for now, enable it after link up. + */ + error = bcm63xx_pcie_phy_enable_ssc(pcie, false); + if (error) + return error; + + /* + * TODO: enable phy low power mode here ? + */ + + error = bcm63xx_pcie_core_set_speed(pcie); + if (error) + return error; + + bcm63xx_pcie_deassert_reset(pcie); + mdelay(500); + + return 0; +} + +static bool bcm63xx_pcie_check_link_up(struct bcm63xx_pcie *pcie) +{ + u32 v = bcm_pcie_readl(pcie, BCM63XX_PCIE_DL_STATUS); + + return !!(v & DL_STATUS_LINK_UP); +} + +static int bcm63xx_pcie_request_resources(struct bcm63xx_pcie *pcie) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + + if (resource_size(&pcie->io_res)) { + dev_err(pcie->dev, "adding resource %pR as IO@#!\n", + &pcie->io_res); + pci_add_resource(&bridge->windows, &pcie->io_res); + } + pci_add_resource(&bridge->windows, &pcie->mem_res); + pci_add_resource(&bridge->windows, &pcie->bus_range); + + return devm_request_pci_bus_resources(pcie->dev, &bridge->windows); +} + +static int bcm63xx_pcie_core_config(struct bcm63xx_pcie *pcie) +{ + u32 reg; + u32 size, size_val; + + /* + * clear legacy interrupt. + */ + bcm_pcie_writel(CPU_INTR1_PCIE_INTD_CPU_INTR | + CPU_INTR1_PCIE_INTC_CPU_INTR | + CPU_INTR1_PCIE_INTB_CPU_INTR | + CPU_INTR1_PCIE_INTA_CPU_INTR, pcie, + BCM63XX_PCIE_CPU_INTR1_MASK_CLEAR); + + /* + * configure MEM window + */ + reg = WIN_LIMIT_END(pcie->mem_res.end) | + WIN_LIMIT_BASE(pcie->mem_res.start); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_WIN_LIMIT(0)); + + reg = WIN_LO_BASE_ADDR(pcie->mem_res.start); + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_WIN_LO(0)); + bcm_pcie_writel(0x0, pcie, BCM63XX_PCIE_MISC_WIN_HI(0)); + + /* + * incoming DDR memory configuration (BAR1) + * + * FIXME: are BAR2 and BAR3 configuration needed ? Or are + * BAR1/BAR2/BAR3 poor naming for DDR chip selects ? + */ + size = pcie->pcfg.dram_size >> 16; /* in 64k units */ + size_val = 0; + while (size) { + ++size_val; + size >>= 1; + } + bcm_pcie_writel(size_val, pcie, BCM63XX_PCIE_MISC_BAR_CONFIG_LO(0)); + + bcm_pcie_writel(UBUS_BAR_ACCESS_EN, pcie, + BCM63XX_PCIE_MISC_UBUS_BAR_REMAP(0)); + + /* + * setup PCI class code. + */ + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_PRIV1_ID_VAL3); + reg &= PRIV1_ID_VAL3_REV_ID_MASK; + reg |= PCI_CLASS_BRIDGE_PCI << 8; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_PRIV1_ID_VAL3); + + /* + * disable data bus error for enumeration + */ + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_MISC_CTRL); + reg |= MISC_CTRL_CFG_READ_UR_MODE; + + /* + * misc performance settings + */ + reg |= (MISC_CTRL_MAX_BURST_SIZE_128B | MISC_CTRL_PCIE_IN_WR_COMBINE | + MISC_CTRL_PCIE_RCB_MPS_MODE | MISC_CTRL_PCIE_RCB_64B_MODE); + + reg &= ~misc_ctrl_burst_align_mask(pcie->misc_revision); + if (pcie->misc_revision >= 0x320) + reg |= misc_ctrl_burst_align(pcie->misc_revision, 4); + else if (pcie->misc_revision == 0x310) + reg |= misc_ctrl_burst_align(pcie->misc_revision, 3); + else + reg |= misc_ctrl_burst_align(pcie->misc_revision, 1); + if (pcie->misc_revision == 0x310) { + /* + * workaround for UBUS4 Logic Bug in this revision + * Limit the max burst to 64B + */ + reg &= ~MISC_CTRL_MAX_BURST_SIZE_MASK; + reg |= MISC_CTRL_MAX_BURST_SIZE_64B; + } + + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_MISC_CTRL); + + /* + * wait for UBUS reply for burst writes + */ + reg = bcm_pcie_readl(pcie, BCM63XX_PCIE_MISC_UBUS_CTRL); + reg |= MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY; + bcm_pcie_writel(reg, pcie, BCM63XX_PCIE_MISC_UBUS_CTRL); + + bcm63xx_pcie_phy_enable_ssc(pcie, true); + + return 0; +} + +void __iomem *bcm63xx_pcie_map_bus(struct pci_bus *the_bus, unsigned int devfn, + int where) +{ + struct pci_host_bridge *host = pci_find_host_bridge(the_bus); + struct bcm63xx_pcie *pcie = pci_host_bridge_priv(host); + unsigned int bus = the_bus->number; + unsigned int dev = PCI_SLOT(devfn), fun = PCI_FUNC(devfn); + + if (pci_is_root_bus(the_bus) && dev > 0) + /* + * device #0 access only on the root bus. + */ + return NULL; + + if (pci_is_root_bus(the_bus)) + /* + * root bus/bridge configuration space is mapped at + * the start of the PCIe register area. + */ + return pcie->regs + where; + + bcm_pcie_writel(EXT_CFG_INDEX_BUS_NUM(bus) | + EXT_CFG_INDEX_DEV_NUM(dev) | + EXT_CFG_INDEX_FUN_NUM(fun), pcie, + BCM63XX_PCIE_EXT_CFG_INDEX); + + return pcie->regs + BCM63XX_PCIE_EXT_CONF_SPACE + where; +} + +struct pci_ops bcm63xx_pcie_ops = { + .map_bus = bcm63xx_pcie_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + +static int bcm63xx_pcie_probe(struct platform_device *pdev) +{ + struct reset_control *reset; + struct ubus4_master *master; + int error; + struct bcm63xx_pcie *pcie; + struct pci_host_bridge *host; + struct resource *res; + struct pci_bus *child; + int rcal_1um_vert_value; + + dev_dbg(&pdev->dev, "probe.\n"); + + reset = devm_reset_control_get(&pdev->dev, "pcie0"); + if (IS_ERR(reset)) { + if (PTR_ERR(reset) != -EPROBE_DEFER) + dev_err(&pdev->dev, "missing pcie0 reset control\n"); + return PTR_ERR(reset); + } + + master = ubus4_master_of_get(pdev->dev.of_node); + if (IS_ERR(master)) { + dev_err(&pdev->dev, "unable to get UBUS master: %ld.\n", + PTR_ERR(master)); + return PTR_ERR(master); + } + + rcal_1um_vert_value = procmon_get_rcal(pdev->dev.of_node); + if (rcal_1um_vert_value == -EPROBE_DEFER) + /* + * should this be fatal for non EPROBE_DEFER cases? + */ + return rcal_1um_vert_value; + + host = devm_pci_alloc_host_bridge(&pdev->dev, sizeof (*pcie)); + if (!host) + return -ENOMEM; + + pcie = pci_host_bridge_priv(host); + pcie->rcal_1um_vert_value = rcal_1um_vert_value; + + make_invalid_resource(&pcie->mem_res); + make_invalid_resource(&pcie->io_res); + make_invalid_resource(&pcie->bus_range); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to get PCIe registers resource.\n"); + return -ENOENT; + } + dev_dbg(&pdev->dev, "PCIe registers: %pR\n", res); + + pcie->dev = &pdev->dev; + pcie->regs_phys = res->start; + + error = bcm63xx_pcie_parse_ranges(pcie); + if (error) + return error; + + host->busnr = pcie->bus_range.start; + host->dev.parent = &pdev->dev; + host->ops = &bcm63xx_pcie_ops; + host->map_irq = of_irq_parse_and_map_pci; + host->swizzle_irq = pci_common_swizzle; + + pcie->irq = irq_of_parse_and_map(pcie->dev->of_node, 0); + if (!pcie->irq) { + dev_err(pcie->dev, "unable to get IRQ.\n"); + /* can only assume it's not there :( */ + return -ENOENT; + } + + error = bcm63xx_pcie_parse_dt_port_config(pcie); + if (error) + return error; + + + /* power up block */ + error = reset_control_deassert(reset); + if (error) { + dev_err(&pdev->dev, "unable to deassert reset.\n"); + return error; + } + mdelay(10); + + error = bcm63xx_pcie_ubus_config(master); + if (error) { + dev_err(&pdev->dev, "unable to configure PCIe UBUS master.\n"); + return error; + } + + pcie->regs = devm_ioremap_resource(&pdev->dev, res); + if (!pcie->regs) { + dev_err(&pdev->dev, "unable to ioremap registers.\n"); + return -ENOMEM; + } + + error = bcm63xx_pcie_init(pcie); + if (error) + return error; + + error = bcm63xx_pcie_reset(pcie); + if (error) + return error; + + if (!bcm63xx_pcie_check_link_up(pcie)) { + dev_err(pcie->dev, "PCIe link: DOWN.\n"); + return -ENXIO; + } else { + u32 link_status = bcm_pcie_readl(pcie, + BCM63XX_PCIE_LINK_STATUS); + dev_info(pcie->dev, "PCIe link: UP, GEN%d, %d lane(s).\n", + LINK_STATUS_SPEED(link_status), + LINK_STATUS_WIDTH(link_status)); + } + + error = bcm63xx_pcie_request_resources(pcie); + if (error) + return error; + + error = bcm63xx_pcie_core_config(pcie); + if (error) + return error; + + error = pci_scan_root_bus_bridge(host); + if (error) { + dev_err(&pdev->dev, "unable to scan root bus bridge: %d\n", + error); + return error; + } + + pci_bus_size_bridges(host->bus); + pci_bus_assign_resources(host->bus); + list_for_each_entry(child, &host->bus->children, node) + pcie_bus_configure_settings(child); + + pci_bus_add_devices(host->bus); + +#if 0 + /* + * now create the PCI bus proper. + */ + pcie->bus = pci_create_root_bus(&pdev->dev, pcie->bus_range.start, + &bcm63xx_pcie_ops, pcie, + &pcie->resources); + if (!pcie->bus) { + dev_err(pcie->dev, "unable to create root bus.\n"); + return -ENXIO; + } + + pci_scan_child_bus(pcie->bus); + pci_assign_unassigned_bus_resources(pcie->bus); + pci_bus_add_devices(pcie->bus); + + /* Configure PCI Express settings */ + list_for_each_entry(child, &pcie->bus->children, node) + pcie_bus_configure_settings(child); +#endif + + return 0; +} + +static const struct of_device_id bcm63xx_pcie_match[] = { + { .compatible = "brcm,bcm63xx-pcie" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63xx_pcie_of_match); + +struct platform_driver bcm63xx_pcie_driver = { + .probe = bcm63xx_pcie_probe, + .remove = NULL, /* FIXME*/ + .driver = { + .name = "bcm63xx-pcie", + .owner = THIS_MODULE, + .of_match_table = bcm63xx_pcie_match, + }, +}; + +module_platform_driver(bcm63xx_pcie_driver); + + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63XX SoCs PCIe root complex driver."); +MODULE_LICENSE("GPL v2"); --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/pci/controller/pcie-bcm63xx.h 2021-03-04 13:20:59.517505633 +0100 @@ -0,0 +1,114 @@ +/* + * pcie-bcm63xx.h for pcie-bcm63xx + * Created by on Mon Jun 10 16:54:54 2019 + */ + +#pragma once + +#define _F(_v, _s, _m) (((_v) & (_m)) << (_s)) + +/* + * TYPE 1 RC configuration registers + */ +#define BCM63XX_PCIE_VENDOR_ID 0x0000 +#define VENDOR_ID_VENDOR(x) ((x) & 0xffff) +#define VENDOR_ID_DEVICE(x) (((x) >> 16) & 0xffff) + +#define BCM63XX_PCIE_LINK_CAP 0x00b8 +#define LINK_CAP_SPEED(x) ((x) & 0xf) +#define LINK_CAP_WIDTH(x) (((x) >> 4) & 0x3f) + +#define BCM63XX_PCIE_LINK_STATUS 0x00bc +#define LINK_STATUS_WIDTH(x) (((x) >> 20) & 0x3f) +#define LINK_STATUS_SPEED(x) (((x) >> 16) & 0xf) + +#define BCM63XX_PCIE_LINK_STATUS_CONTROL2 0x00dc +#define LINK_STATUS_CONTROL2_SPEED_MASK _F(0x3, 0, 0x3) +#define LINK_STATUS_CONTROL2_SPEED(x) _F(x, 0, 0x3) + +#define BCM63XX_PCIE_PRIV1_LINK_CAP (0x0428 + 0xb4) +#define PRIV1_LINK_CAP_SPEED_MASK _F(0x3, 0, 0x3) +#define PRIV1_LINK_CAP_SPEED(x) _F(x, 0, 0x3) + +#define BCM63XX_PCIE_PRIV1_ID_VAL3 (0x428 + 0x14) +#define PRIV1_ID_VAL3_REV_ID_MASK (0xff << 24) + +#define BCM63XX_PCIE_PHY_ADDR 0x1100 +#define PHY_ADDR_READ (1 << 20) +#define PHY_ADDR_WRITE (0 << 20) +#define PHY_ADDR_PHY(x) _F(x, 16, 0xf) +#define PHY_ADDR_REG(x) _F(x, 0x0, 0x1f) + +#define BCM63XX_PCIE_DL_STATUS 0x1048 +#define DL_STATUS_LINK_UP (0x2000) + +#define BCM63XX_PCIE_PHY_WR_DATA 0x1104 +#define PHY_WR_DATA_TRIG (1 << 31) +#define PHY_WR_DATA_MASK 0xffff +#define BCM63XX_PCIE_PHY_RD_DATA 0x1108 +#define PHY_RD_DATA_DONE (1 << 31) +#define PHY_RD_DATA_MASK 0xffff + +#define BCM63XX_PCIE_MISC_MISC_CTRL (0x4008) +#define MISC_CTRL_MAX_BURST_SIZE_64B (0 << 20) +#define MISC_CTRL_MAX_BURST_SIZE_128B (1 << 20) +#define MISC_CTRL_MAX_BURST_SIZE_MASK (3 << 20) +static inline u32 misc_ctrl_burst_align_mask(u32 rev) +{ + return rev >= 0x310 ? (7 << 17) : (1 << 19); +} +static inline u32 misc_ctrl_burst_align(u32 rev, u32 b) +{ + return rev >= 0x310 ? (b << 17) : (b << 19); +} +#define MISC_CTRL_CFG_READ_UR_MODE (1 << 13) +#define MISC_CTRL_PCIE_IN_WR_COMBINE (1 << 11) +#define MISC_CTRL_PCIE_RCB_MPS_MODE (1 << 10) +#define MISC_CTRL_PCIE_RCB_64B_MODE (1 << 7) + +#define BCM63XX_PCIE_MISC_WIN_LO(win) (0x400c + (win) * 8) +#define WIN_LO_BASE_ADDR(x) ((x) & 0xfff00000) +#define BCM63XX_PCIE_MISC_WIN_HI(win) (0x4010 + (win) * 8) + +#define BCM63XX_PCIE_MISC_BAR_CONFIG_LO(bar) (0x402c + (bar) * 8) + +#define BCM63XX_PCIE_MISC_UBUS_CTRL (0x40a4) +#define MISC_UBUS_CTRL_UBUS_WR_WITH_REPLY (1 << 14) + + +#define BCM63XX_PCIE_MISC_UBUS_BAR_REMAP(bar) (0x40ac + (bar) * 8) +#define UBUS_BAR_ACCESS_EN (1 << 0) + +#define BCM63XX_PCIE_MISC_CTRL 0x4064 +#define MISC_CTRL_PCIE_RESETn (1 << 2) + +#define BCM63XX_PCIE_MISC_REVISION 0x406c + +#define BCM63XX_PCIE_MISC_WIN +#define BCM63XX_PCIE_MISC_WIN_LIMIT(win) (0x4070 + (win) * 4) +#define WIN_LIMIT_END(x) ((x) & 0xfff00000) +#define WIN_LIMIT_BASE(x) (((x) >> 16) & 0xffff0) + +#define BCM63XX_PCIE_EXT_CONF_SPACE 0x8000 + +#define BCM63XX_PCIE_EXT_CFG_INDEX 0x9000 +#define EXT_CFG_INDEX_BUS_NUM(x) _F(x, 20, 0xff) +#define EXT_CFG_INDEX_DEV_NUM(x) _F(x, 15, 0x1f) +#define EXT_CFG_INDEX_FUN_NUM(x) _F(x, 12, 0x7) + +#define BCM63XX_PCIE_CPU_INTR1_MASK_CLEAR 0x940c +#define CPU_INTR1_PCIE_INTA_CPU_INTR (1 << 1) +#define CPU_INTR1_PCIE_INTB_CPU_INTR (1 << 2) +#define CPU_INTR1_PCIE_INTC_CPU_INTR (1 << 3) +#define CPU_INTR1_PCIE_INTD_CPU_INTR (1 << 4) +#define CPU_INTR1_PCIE_INTR_CPU_INTR (1 << 5) +#define CPU_INTR1_PCIE_NMI_CPU_INTR (1 << 6) +#define CPU_INTR1_PCIE_UBUS_CPU_INTR (1 << 7) +#define CPU_INTR1_PCIE_MSI_INTR_CPU_INTR (1 << 9) + +#if 0 +#define EXT_CFG_PCIE_EXT_CFG_INDEX_OFFSET (PCIE_EXT_CFG_REGS_OFFSET+0x0000) +#define EXT_CFG_BUS_NUM_SHIFT 20 +#define EXT_CFG_DEV_NUM_SHIFT 15 +#define EXT_CFG_FUNC_NUM_SHIFT 12 +#endif --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/phy/xdsl_phy_api.c 2021-03-04 13:20:59.547505634 +0100 @@ -0,0 +1,205 @@ +#include +#include +#include +#include + +static DEFINE_MUTEX(phy_device_list_mutex); +static LIST_HEAD(phy_device_list); + +/* + * + */ +static struct xdsl_phy *__phy_lookup(struct device_node *node, + unsigned int id) +{ + struct xdsl_phy *pd; + + list_for_each_entry(pd, &phy_device_list, next) { + if (node) { + if (pd->of_node == node) + return pd; + } else { + if (pd->id == id) + return pd; + } + } + return NULL; +} + +/* + * + */ +struct xdsl_phy *xdsl_phy_attach(struct device_node *node, + unsigned int id, + void (*change_cb)(struct xdsl_phy *, + void *), + void *change_priv) +{ + struct xdsl_phy *phy_dev; + + if (!node && !id) + return ERR_PTR(-EINVAL); + + mutex_lock(&phy_device_list_mutex); + + phy_dev = __phy_lookup(node, id); + + if (!phy_dev) { + mutex_unlock(&phy_device_list_mutex); + return ERR_PTR(-EPROBE_DEFER); + } + + if (phy_dev->in_use) { + mutex_unlock(&phy_device_list_mutex); + return ERR_PTR(-EBUSY); + } + + try_module_get(phy_dev->owner); + + phy_dev->in_use = true; + phy_dev->started = false; + phy_dev->change_cb = change_cb; + phy_dev->change_priv = change_priv; + + mutex_unlock(&phy_device_list_mutex); + + return phy_dev; +} + +EXPORT_SYMBOL(xdsl_phy_attach); + +/* + * + */ +static void initial_change_work_func(struct work_struct *work) +{ + struct xdsl_phy *phy_dev = container_of(work, + struct xdsl_phy, + initial_change_work); + + mutex_lock(&phy_dev->lock); + if (!phy_dev->in_use || !phy_dev->change_cb || !phy_dev->started) { + mutex_unlock(&phy_dev->lock); + return; + } + + phy_dev->initial_change_pending = false; + phy_dev->change_cb(phy_dev, phy_dev->change_priv); + mutex_unlock(&phy_dev->lock); +} + +/* + * + */ +void xdsl_phy_start(struct xdsl_phy *phy_dev) +{ + mutex_lock(&phy_dev->lock); + phy_dev->started = true; + phy_dev->initial_change_pending = true; + schedule_work(&phy_dev->initial_change_work); + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_start); + +/* + * + */ +void xdsl_phy_stop(struct xdsl_phy *phy_dev) +{ + mutex_lock(&phy_dev->lock); + phy_dev->started = false; + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_stop); + +/* + * + */ +void xdsl_phy_detach(struct xdsl_phy *phy_dev) +{ + WARN_ON(!phy_dev->in_use); + + mutex_lock(&phy_dev->lock); + phy_dev->in_use = false; + phy_dev->started = false; + cancel_work_sync(&phy_dev->initial_change_work); + phy_dev->initial_change_pending = false; + phy_dev->change_cb = NULL; + phy_dev->change_priv = NULL; + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_detach); + +/* + * + */ +void xdsl_phy_device_notify_change(struct xdsl_phy *phy_dev) +{ + mutex_lock(&phy_dev->lock); + if (!phy_dev->in_use || !phy_dev->change_cb || !phy_dev->started) { + mutex_unlock(&phy_dev->lock); + return; + } + + cancel_work_sync(&phy_dev->initial_change_work); + phy_dev->initial_change_pending = false; + phy_dev->change_cb(phy_dev, phy_dev->change_priv); + mutex_unlock(&phy_dev->lock); +} + +EXPORT_SYMBOL(xdsl_phy_device_notify_change); + +/* + * + */ +int xdsl_phy_device_register(struct xdsl_phy *phy_dev) +{ + if (!phy_dev->ops || + !phy_dev->ops->get_status || + !phy_dev->owner) + return -EINVAL; + + mutex_lock(&phy_device_list_mutex); + + if (__phy_lookup(phy_dev->of_node, phy_dev->id)) { + mutex_unlock(&phy_device_list_mutex); + return -EEXIST; + } + + mutex_init(&phy_dev->lock); + mutex_init(&phy_dev->ops_lock); + phy_dev->in_use = false; + phy_dev->started = false; + INIT_WORK(&phy_dev->initial_change_work, initial_change_work_func); + phy_dev->initial_change_pending = false; + phy_dev->change_cb = NULL; + phy_dev->change_priv = NULL; + + list_add(&phy_dev->next, &phy_device_list); + mutex_unlock(&phy_device_list_mutex); + + return 0; +} + +EXPORT_SYMBOL(xdsl_phy_device_register); + +/* + * + */ +void xdsl_phy_device_unregister(struct xdsl_phy *phy_dev) +{ + if (WARN_ON(phy_dev->in_use)) + return; + + cancel_work_sync(&phy_dev->initial_change_work); + mutex_lock(&phy_device_list_mutex); + list_del(&phy_dev->next); + mutex_unlock(&phy_device_list_mutex); +} + +EXPORT_SYMBOL(xdsl_phy_device_unregister); + +MODULE_LICENSE("GPL"); --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/pinctrl/bcm/pinctrl-bcm63138.c 2021-03-04 13:20:59.547505634 +0100 @@ -0,0 +1,627 @@ +/* + * Driver for Broadcom BCM63138 pinctrl + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "../pinctrl-utils.h" + +#define GPIO_DIR_REG(cfg, gpio) ((gpio / 32) * 4 + cfg->gpio_dir_offset) +#define GPIO_VAL_REG(cfg, gpio) ((gpio / 32) * 4 + cfg->gpio_val_offset) + +/* + * registers relative to cfg->testport_offset. + */ +#define GPIO_TPORT_DATA_MSB_REG(cfg) (cfg->testport_offset + 0x00) +#define GPIO_TPORT_DATA_LSB_REG(cfg) (cfg->testport_offset + 0x04) +#define TPORT_DATA_PIN_SHIFT 0 +#define TPORT_DATA_FUNC_SHIFT 12 +#define TPORT_DATA_FUNC_GPIO 5 + +#define GPIO_TPORT_CMD_REG(cfg) (cfg->testport_offset + 0x08) +#define TPORT_CMD_LOAD 0x21 + +struct bcm63138_pinctrl_group { + const char *name; + unsigned long config; + unsigned pin; +}; + +struct bcm63xx_pinctrl_soc_config; + +struct bcm63138_pinctrl { + struct device *dev; + void __iomem *base; + + struct pinctrl_desc desc; + struct pinctrl_dev *pctl_dev; + + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range *range; + + struct bcm63138_pinctrl_group *groups; + unsigned ngroups; + const char **grp_names; + spinlock_t lock; + const struct bcm63xx_pinctrl_soc_config *cfg; +}; + +static const char * const bcm63138_pin_functions[] = { + "mux0", + "mux1", + "mux2", + "mux3", + "mux4", + "mux5", + "mux6", +}; + +struct bcm63xx_desc_function { + const char *name; + const unsigned char num; +}; + +struct bcm63xx_desc_pin { + struct pinctrl_pin_desc pin; + const struct bcm63xx_desc_function *functions; +}; + +struct bcm63xx_pinctrl_soc_config { + const struct bcm63xx_desc_pin *pin_descs; + size_t nr_pin_descs; + + u32 gpio_dir_offset; + u32 gpio_val_offset; + u32 testport_offset; +}; + +#define BCM63XX_PIN(_pin, ...) \ + { \ + .pin = _pin, \ + .functions = (struct bcm63xx_desc_function[]){ \ + __VA_ARGS__, { } }, \ + } + +#define BCM63XX_FUNCTION(_num, _name) \ + { \ + .num = _num, \ + .name = _name, \ + } + +#include "pindesc-bcm63138.h" +#include "pindesc-bcm63158.h" + +struct bcm63xx_pinctrl_soc_config bcm63138_soc_config = { + .pin_descs = bcm63138_desc_pins, + .nr_pin_descs = ARRAY_SIZE(bcm63138_desc_pins), + + .gpio_dir_offset = 0x00, + .gpio_val_offset = 0x14, + .testport_offset = 0x3c, +}; + +struct bcm63xx_pinctrl_soc_config bcm63158_soc_config = { + .pin_descs = bcm63158_desc_pins, + .nr_pin_descs = ARRAY_SIZE(bcm63158_desc_pins), + + .gpio_dir_offset = 0x00, + .gpio_val_offset = 0x20, + .testport_offset = 0x54, +}; + +/* Pinctrl functions */ +static struct bcm63138_pinctrl_group * +bcm63138_pctrl_find_group_by_pin(struct bcm63138_pinctrl *pctl, u32 pin) +{ + int i; + + for (i = 0; i < pctl->ngroups; i++) { + struct bcm63138_pinctrl_group *grp = pctl->groups + i; + + if (grp->pin == pin) + return grp; + } + + return NULL; +} + +static bool bcm63138_pctrl_is_function_valid(struct bcm63138_pinctrl *pctl, + u32 pin_num, u32 fnum) +{ + int i; + + for (i = 0; i < pctl->cfg->nr_pin_descs; i++) { + const struct bcm63xx_desc_pin *pin = &pctl->cfg->pin_descs[i]; + const struct bcm63xx_desc_function *func = pin->functions; + + if (pin->pin.number != pin_num) + continue; + + while (func && func->name) { + if (func->num == fnum) + return true; + func++; + } + + break; + } + + return false; +} + +static int +bcm63138_pctrl_dt_node_to_map_func(struct bcm63138_pinctrl *pctl, + u32 pin, u32 fnum, + struct bcm63138_pinctrl_group *grp, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + if (*num_maps == *reserved_maps) + return -ENOSPC; + + (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; + (*map)[*num_maps].data.mux.group = grp->name; + + if (!bcm63138_pctrl_is_function_valid(pctl, pin, fnum)) { + dev_err(pctl->dev, "invalid function %d on pin %d .\n", + fnum, pin); + return -EINVAL; + } + + (*map)[*num_maps].data.mux.function = bcm63138_pin_functions[fnum]; + (*num_maps)++; + + return 0; +} + +static int bcm63138_pctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + return pctl->ngroups; +} + +static const char *bcm63138_pctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned group) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + return pctl->groups[group].name; +} + +static int bcm63138_pctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned group, + const unsigned **pins, + unsigned *num_pins) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + *pins = (unsigned *)&pctl->groups[group].pin; + *num_pins = 1; + return 0; +} + +static int bcm63138_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, + struct device_node *node, + struct pinctrl_map **map, + unsigned *reserved_maps, + unsigned *num_maps) +{ + struct bcm63138_pinctrl *pctl; + struct bcm63138_pinctrl_group *grp; + struct property *pins; + u32 pinfunc, pin, func; + unsigned reserve = 0; + int num_pins, num_funcs, maps_per_pin, i, err; + + pctl = pinctrl_dev_get_drvdata(pctldev); + + pins = of_find_property(node, "pinmux", NULL); + if (!pins) { + dev_err(pctl->dev, "missing pins property in node %s .\n", + node->name); + return -EINVAL; + } + + num_pins = pins->length / sizeof(u32); + num_funcs = num_pins; + maps_per_pin = 0; + + if (num_funcs) + maps_per_pin++; + + if (num_pins >= 1) + maps_per_pin++; + + if (!num_pins || !maps_per_pin) + return -EINVAL; + + reserve = num_pins * maps_per_pin; + + err = pinctrl_utils_reserve_map(pctldev, map, + reserved_maps, num_maps, reserve); + if (err) + return err; + + for (i = 0; i < num_pins; i++) { + err = of_property_read_u32_index(node, "pinmux", + i, &pinfunc); + if (err) + return err; + + pin = BCM63138_GET_PIN_NO(pinfunc); + func = BCM63138_GET_PIN_FUNC(pinfunc); + + if (!bcm63138_pctrl_is_function_valid(pctl, pin, func)) { + dev_err(pctl->dev, "invalid function.\n"); + return -EINVAL; + } + + grp = bcm63138_pctrl_find_group_by_pin(pctl, pin); + if (!grp) { + dev_err(pctl->dev, "unable to match pin %d to group\n", + pin); + return -EINVAL; + } + + err = bcm63138_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, + reserved_maps, num_maps); + if (err) + return err; + } + + return 0; +} + +static int bcm63138_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, unsigned *num_maps) +{ + struct device_node *np; + unsigned reserved_maps; + int ret; + + *map = NULL; + *num_maps = 0; + reserved_maps = 0; + + for_each_child_of_node(np_config, np) { + ret = bcm63138_pctrl_dt_subnode_to_map(pctldev, np, map, + &reserved_maps, num_maps); + if (ret < 0) { + pinctrl_utils_free_map(pctldev, *map, *num_maps); + return ret; + } + } + + return 0; +} + +static const struct pinctrl_ops bcm63138_pctrl_ops = { + .dt_node_to_map = bcm63138_pctrl_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, + .get_groups_count = bcm63138_pctrl_get_groups_count, + .get_group_name = bcm63138_pctrl_get_group_name, + .get_group_pins = bcm63138_pctrl_get_group_pins, +}; + +/* Pinmux functions */ + +static int bcm63138_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(bcm63138_pin_functions); +} + +static const char *bcm63138_pmx_get_func_name(struct pinctrl_dev *pctldev, + unsigned selector) +{ + return bcm63138_pin_functions[selector]; +} + +static int bcm63138_pmx_get_func_groups(struct pinctrl_dev *pctldev, + unsigned function, + const char * const **groups, + unsigned * const num_groups) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + *groups = pctl->grp_names; + *num_groups = pctl->ngroups; + return 0; +} + +static void set_mux(struct bcm63138_pinctrl *pctl, + unsigned int pin, + unsigned int function) +{ + dev_dbg(pctl->dev, "setting mux for pin%d function%d\n", + pin, function); + + iowrite32(0, + pctl->base + GPIO_TPORT_DATA_MSB_REG(pctl->cfg)); + + iowrite32(pin << TPORT_DATA_PIN_SHIFT | + function << TPORT_DATA_FUNC_SHIFT, + pctl->base + GPIO_TPORT_DATA_LSB_REG(pctl->cfg)); + + iowrite32(TPORT_CMD_LOAD, + pctl->base + GPIO_TPORT_CMD_REG(pctl->cfg)); +} + +static int bcm63138_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned function, + unsigned group) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + struct bcm63138_pinctrl_group *g = pctl->groups + group; + + if (!bcm63138_pctrl_is_function_valid(pctl, g->pin, function)) { + dev_err(pctl->dev, "invalid function %d on group %d .\n", + function, group); + return -EINVAL; + } + + set_mux(pctl, g->pin, function); + return 0; +} + +static int bcm63138_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned offset) +{ + struct bcm63138_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); + set_mux(pctl, offset, TPORT_DATA_FUNC_GPIO); + return 0; +} + +static const struct pinmux_ops bcm63138_pmx_ops = { + .get_functions_count = bcm63138_pmx_get_funcs_cnt, + .get_function_name = bcm63138_pmx_get_func_name, + .get_function_groups = bcm63138_pmx_get_func_groups, + .set_mux = bcm63138_pmx_set_mux, + .gpio_request_enable = bcm63138_pmx_gpio_request_enable, + .strict = true, +}; + +/* + * GPIO functions + */ +static int bcm63138_gpio_get(struct gpio_chip *chip, unsigned offset) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + + val = ioread32(pctl->base + GPIO_VAL_REG(pctl->cfg, offset)); + return !!(val & (1 << (offset % 32))); +} + +static void __bcm63138_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + + val = ioread32(pctl->base + GPIO_VAL_REG(pctl->cfg, offset)); + if (value) + val |= (1 << (offset % 32)); + else + val &= ~(1 << (offset % 32)); + iowrite32(val, pctl->base + GPIO_VAL_REG(pctl->cfg, offset)); +} + +static void bcm63138_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + unsigned long flags; + + spin_lock_irqsave(&pctl->lock, flags); + + __bcm63138_gpio_set(chip, offset, value); + + spin_unlock_irqrestore(&pctl->lock, flags); +} + +static int bcm63138_gpio_direction_input(struct gpio_chip *chip, unsigned offset) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pctl->lock, flags); + + val = ioread32(pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + val &= ~(1 << (offset % 32)); + iowrite32(val, pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + + spin_unlock_irqrestore(&pctl->lock, flags); + return 0; +} + +static int bcm63138_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + unsigned long flags; + + spin_lock_irqsave(&pctl->lock, flags); + + __bcm63138_gpio_set(chip, offset, value); + + val = ioread32(pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + val |= (1 << (offset % 32)); + iowrite32(val, pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + + spin_unlock_irqrestore(&pctl->lock, flags); + return 0; +} + +static int bcm63138_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct bcm63138_pinctrl *pctl = gpiochip_get_data(chip); + u32 val; + + val = ioread32(pctl->base + GPIO_DIR_REG(pctl->cfg, offset)); + return (val & (1 << (offset % 32))) ? 0 : 1; +} + +/* + * + */ +static int bcm63138_pctrl_build_state(struct platform_device *pdev) +{ + struct bcm63138_pinctrl *pctl = platform_get_drvdata(pdev); + int i; + + pctl->ngroups = pctl->cfg->nr_pin_descs; + + /* Allocate groups */ + pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->groups), GFP_KERNEL); + if (!pctl->groups) + return -ENOMEM; + + /* We assume that one pin is one group, use pin name as group name. */ + pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, + sizeof(*pctl->grp_names), GFP_KERNEL); + if (!pctl->grp_names) + return -ENOMEM; + + for (i = 0; i < pctl->cfg->nr_pin_descs; i++) { + const struct bcm63xx_desc_pin *pin = &pctl->cfg->pin_descs[i]; + struct bcm63138_pinctrl_group *group = &pctl->groups[i]; + + group->name = pin->pin.name; + group->pin = pin->pin.number; + pctl->grp_names[i] = pin->pin.name; + } + + return 0; +} + +static const struct of_device_id bcm63138_pinctrl_match[] = { + { .compatible = "brcm,bcm63138-pinctrl", .data = &bcm63138_soc_config }, + { .compatible = "brcm,bcm63158-pinctrl", .data = &bcm63158_soc_config }, + {} +}; + +/* + * + */ +static int bcm63138_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct bcm63138_pinctrl *pctl; + struct resource *res_mem; + struct pinctrl_pin_desc *pins; + struct gpio_chip *gpio_chip; + unsigned int i; + int ret; + const struct of_device_id *match; + + match = of_match_device(bcm63138_pinctrl_match, &pdev->dev); + if (!match) + return -EINVAL; + + pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + platform_set_drvdata(pdev, pctl); + pctl->dev = dev; + pctl->cfg = match->data; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) { + dev_err(dev, "could not get IO memory\n"); + return -ENODEV; + } + + ret = bcm63138_pctrl_build_state(pdev); + if (ret) { + dev_err(dev, "build state failed: %d\n", ret); + return -EINVAL; + } + + pctl->base = devm_ioremap_resource(dev, res_mem); + if (IS_ERR(pctl->base)) + return PTR_ERR(pctl->base); + + /* prepare actual pins from desc */ + pins = devm_kcalloc(&pdev->dev, pctl->cfg->nr_pin_descs, + sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < pctl->cfg->nr_pin_descs; i++) + pins[i] = pctl->cfg->pin_descs[i].pin; + + spin_lock_init(&pctl->lock); + pctl->desc.name = dev_name(&pdev->dev); + pctl->desc.owner = THIS_MODULE; + pctl->desc.pins = pins; + pctl->desc.npins = pctl->cfg->nr_pin_descs; + pctl->desc.pctlops = &bcm63138_pctrl_ops; + pctl->desc.pmxops = &bcm63138_pmx_ops; + + pctl->pctl_dev = devm_pinctrl_register(dev, &pctl->desc, pctl); + if (IS_ERR(pctl->pctl_dev)) + return PTR_ERR(pctl->pctl_dev); + + /* add gpio chip */ + gpio_chip = &pctl->gpio_chip; + gpio_chip->base = -1; + gpio_chip->label = "bcm63138-gpio"; + gpio_chip->request = gpiochip_generic_request; + gpio_chip->free = gpiochip_generic_free; + gpio_chip->get = bcm63138_gpio_get; + gpio_chip->set = bcm63138_gpio_set; + gpio_chip->direction_input = bcm63138_gpio_direction_input; + gpio_chip->direction_output = bcm63138_gpio_direction_output; + gpio_chip->get_direction = bcm63138_gpio_get_direction; + gpio_chip->ngpio = pctl->cfg->nr_pin_descs; + gpio_chip->of_node = dev->of_node; + gpio_chip->parent = dev; + + ret = devm_gpiochip_add_data(dev, gpio_chip, pctl); + if (ret) + return ret; + + ret = gpiochip_add_pin_range(gpio_chip, pctl->desc.name, + 0, 0, pctl->cfg->nr_pin_descs); + if (ret) + return ret; + + return 0; +}; + +static struct platform_driver bcm63138_pinctrl_driver = { + .probe = bcm63138_pinctrl_probe, + .driver = { + .name = "bcm63138_pinctrl", + .of_match_table = bcm63138_pinctrl_match, + .suppress_bind_attrs = true, + }, +}; + +builtin_platform_driver(bcm63138_pinctrl_driver); --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/pinctrl/bcm/pindesc-bcm63138.h 2021-03-04 13:20:59.550838968 +0100 @@ -0,0 +1,790 @@ +static const struct bcm63xx_desc_pin bcm63138_desc_pins[] = { + BCM63XX_PIN( + PINCTRL_PIN(0, "GPIO_00"), + BCM63XX_FUNCTION(1, "SER_LED_DATA"), + BCM63XX_FUNCTION(4, "LED_00"), + BCM63XX_FUNCTION(5, "GPIO_00") + ), + BCM63XX_PIN( + PINCTRL_PIN(1, "GPIO_01"), + BCM63XX_FUNCTION(1, "SER_LED_CLK"), + BCM63XX_FUNCTION(4, "LED_01"), + BCM63XX_FUNCTION(5, "GPIO_01") + ), + BCM63XX_PIN( + PINCTRL_PIN(2, "GPIO_02"), + BCM63XX_FUNCTION(1, "SER_LED_MASK"), + BCM63XX_FUNCTION(4, "LED_02"), + BCM63XX_FUNCTION(5, "GPIO_02") + ), + BCM63XX_PIN( + PINCTRL_PIN(3, "GPIO_03"), + BCM63XX_FUNCTION(1, "UART2_CTS"), + BCM63XX_FUNCTION(2, "NTR_PULSE_IN_0"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_0"), + BCM63XX_FUNCTION(4, "LED_03"), + BCM63XX_FUNCTION(5, "GPIO_03") + ), + BCM63XX_PIN( + PINCTRL_PIN(4, "GPIO_04"), + BCM63XX_FUNCTION(1, "UART2_RTS"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_0"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_1"), + BCM63XX_FUNCTION(4, "LED_04"), + BCM63XX_FUNCTION(5, "GPIO_04") + ), + BCM63XX_PIN( + PINCTRL_PIN(5, "GPIO_05"), + BCM63XX_FUNCTION(1, "UART2_SIN"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_2"), + BCM63XX_FUNCTION(4, "LED_05"), + BCM63XX_FUNCTION(5, "GPIO_05") + ), + BCM63XX_PIN( + PINCTRL_PIN(6, "GPIO_06"), + BCM63XX_FUNCTION(1, "UART2_SOUT"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_3"), + BCM63XX_FUNCTION(4, "LED_06"), + BCM63XX_FUNCTION(5, "GPIO_06") + ), + BCM63XX_PIN( + PINCTRL_PIN(7, "GPIO_07"), + BCM63XX_FUNCTION(1, "SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_1"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_4"), + BCM63XX_FUNCTION(4, "LED_07"), + BCM63XX_FUNCTION(5, "GPIO_07") + ), + BCM63XX_PIN( + PINCTRL_PIN(8, "GPIO_08"), + BCM63XX_FUNCTION(1, "SPIM_SS4_B"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_5"), + BCM63XX_FUNCTION(4, "LED_08"), + BCM63XX_FUNCTION(5, "GPIO_08") + ), + BCM63XX_PIN( + PINCTRL_PIN(9, "GPIO_09"), + BCM63XX_FUNCTION(1, "SPIM_SS3_B"), + BCM63XX_FUNCTION(2, "LD1_DIN"), + BCM63XX_FUNCTION(4, "LED_09"), + BCM63XX_FUNCTION(5, "GPIO_09") + ), + BCM63XX_PIN( + PINCTRL_PIN(10, "GPIO_10"), + BCM63XX_FUNCTION(1, "SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "LD1_DCLK"), + BCM63XX_FUNCTION(4, "LED_10"), + BCM63XX_FUNCTION(5, "GPIO_10") + ), + BCM63XX_PIN( + PINCTRL_PIN(11, "GPIO_11"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_6"), + BCM63XX_FUNCTION(4, "LED_11"), + BCM63XX_FUNCTION(5, "GPIO_11") + ), + BCM63XX_PIN( + PINCTRL_PIN(12, "GPIO_12"), + BCM63XX_FUNCTION(1, "NTR_PULSE_IN"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_7"), + BCM63XX_FUNCTION(4, "LED_12"), + BCM63XX_FUNCTION(5, "GPIO_12") + ), + BCM63XX_PIN( + PINCTRL_PIN(13, "GPIO_13"), + BCM63XX_FUNCTION(1, "NTR_PULSE_OUT_0"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_8"), + BCM63XX_FUNCTION(4, "LED_13"), + BCM63XX_FUNCTION(5, "GPIO_13") + ), + BCM63XX_PIN( + PINCTRL_PIN(14, "GPIO_14"), + BCM63XX_FUNCTION(3, "MOCA_GPIO_9"), + BCM63XX_FUNCTION(4, "LED_14"), + BCM63XX_FUNCTION(5, "GPIO_14") + ), + BCM63XX_PIN( + PINCTRL_PIN(15, "GPIO_15"), + BCM63XX_FUNCTION(4, "LED_15"), + BCM63XX_FUNCTION(5, "GPIO_15") + ), + BCM63XX_PIN( + PINCTRL_PIN(16, "GPIO_16"), + BCM63XX_FUNCTION(3, "DECT_PD_0"), + BCM63XX_FUNCTION(4, "LED_16"), + BCM63XX_FUNCTION(5, "GPIO_16") + ), + BCM63XX_PIN( + PINCTRL_PIN(17, "GPIO_17"), + BCM63XX_FUNCTION(3, "DECT_PD_1"), + BCM63XX_FUNCTION(4, "LED_17"), + BCM63XX_FUNCTION(5, "GPIO_17") + ), + BCM63XX_PIN( + PINCTRL_PIN(18, "GPIO_18"), + BCM63XX_FUNCTION(1, "VREG_CLK"), + BCM63XX_FUNCTION(4, "LED_18"), + BCM63XX_FUNCTION(5, "GPIO_18") + ), + BCM63XX_PIN( + PINCTRL_PIN(19, "GPIO_19"), + BCM63XX_FUNCTION(4, "LED_19"), + BCM63XX_FUNCTION(5, "GPIO_19") + ), + BCM63XX_PIN( + PINCTRL_PIN(20, "GPIO_20"), + BCM63XX_FUNCTION(2, "UART2_CTS"), + BCM63XX_FUNCTION(4, "LED_20"), + BCM63XX_FUNCTION(5, "GPIO_20") + ), + BCM63XX_PIN( + PINCTRL_PIN(21, "GPIO_21"), + BCM63XX_FUNCTION(2, "UART2_RTS"), + BCM63XX_FUNCTION(4, "LED_21"), + BCM63XX_FUNCTION(5, "GPIO_21") + ), + BCM63XX_PIN( + PINCTRL_PIN(22, "GPIO_22"), + BCM63XX_FUNCTION(2, "UART2_SIN"), + BCM63XX_FUNCTION(4, "LED_22"), + BCM63XX_FUNCTION(5, "GPIO_22") + ), + BCM63XX_PIN( + PINCTRL_PIN(23, "GPIO_23"), + BCM63XX_FUNCTION(2, "UART2_SOUT"), + BCM63XX_FUNCTION(4, "LED_23"), + BCM63XX_FUNCTION(5, "GPIO_23") + ), + BCM63XX_PIN( + PINCTRL_PIN(24, "GPIO_24"), + BCM63XX_FUNCTION(1, "NTR_PULSE_OUT_1"), + BCM63XX_FUNCTION(3, "I2C_SDA"), + BCM63XX_FUNCTION(4, "LED_24"), + BCM63XX_FUNCTION(5, "GPIO_24") + ), + BCM63XX_PIN( + PINCTRL_PIN(25, "GPIO_25"), + BCM63XX_FUNCTION(1, "SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_IN"), + BCM63XX_FUNCTION(3, "I2C_SCL"), + BCM63XX_FUNCTION(4, "LED_25"), + BCM63XX_FUNCTION(5, "GPIO_25") + ), + BCM63XX_PIN( + PINCTRL_PIN(26, "GPIO_26"), + BCM63XX_FUNCTION(1, "SPIM_SS3_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_0"), + BCM63XX_FUNCTION(3, "NTR_PULSE_IN"), + BCM63XX_FUNCTION(4, "LED_26"), + BCM63XX_FUNCTION(5, "GPIO_26") + ), + BCM63XX_PIN( + PINCTRL_PIN(27, "GPIO_27"), + BCM63XX_FUNCTION(1, "SPIM_SS4_B"), + BCM63XX_FUNCTION(2, "NTR_PULSE_OUT_1"), + BCM63XX_FUNCTION(3, "UART2_SIN"), + BCM63XX_FUNCTION(4, "LED_27"), + BCM63XX_FUNCTION(5, "GPIO_27") + ), + BCM63XX_PIN( + PINCTRL_PIN(28, "GPIO_28"), + BCM63XX_FUNCTION(1, "SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "AE_LOS"), + BCM63XX_FUNCTION(3, "UART2_SOUT"), + BCM63XX_FUNCTION(4, "LED_28"), + BCM63XX_FUNCTION(5, "GPIO_28") + ), + BCM63XX_PIN( + PINCTRL_PIN(29, "GPIO_29"), + BCM63XX_FUNCTION(1, "SER_LED_DATA"), + BCM63XX_FUNCTION(4, "LED_29"), + BCM63XX_FUNCTION(5, "GPIO_29") + ), + BCM63XX_PIN( + PINCTRL_PIN(30, "GPIO_30"), + BCM63XX_FUNCTION(1, "SER_LED_CLK"), + BCM63XX_FUNCTION(4, "LED_30"), + BCM63XX_FUNCTION(5, "GPIO_30") + ), + BCM63XX_PIN( + PINCTRL_PIN(31, "GPIO_31"), + BCM63XX_FUNCTION(1, "SER_LED_MASK"), + BCM63XX_FUNCTION(4, "LED_31"), + BCM63XX_FUNCTION(5, "GPIO_31") + ), + BCM63XX_PIN( + PINCTRL_PIN(32, "GPIO_32"), + BCM63XX_FUNCTION(1, "EXT_IRQ_0"), + BCM63XX_FUNCTION(5, "GPIO_32") + ), + BCM63XX_PIN( + PINCTRL_PIN(33, "GPIO_33"), + BCM63XX_FUNCTION(1, "EXT_IRQ_1"), + BCM63XX_FUNCTION(5, "GPIO_33") + ), + BCM63XX_PIN( + PINCTRL_PIN(34, "GPIO_34"), + BCM63XX_FUNCTION(1, "EXT_IRQ_2"), + BCM63XX_FUNCTION(5, "GPIO_34") + ), + BCM63XX_PIN( + PINCTRL_PIN(35, "GPIO_35"), + BCM63XX_FUNCTION(1, "EXT_IRQ_3"), + BCM63XX_FUNCTION(2, "SYS_IRQ_OUT"), + BCM63XX_FUNCTION(5, "GPIO_35") + ), + BCM63XX_PIN( + PINCTRL_PIN(36, "GPIO_36"), + BCM63XX_FUNCTION(1, "EXT_IRQ_4"), + BCM63XX_FUNCTION(2, "AE_LOS"), + BCM63XX_FUNCTION(5, "GPIO_36") + ), + BCM63XX_PIN( + PINCTRL_PIN(37, "GPIO_37"), + BCM63XX_FUNCTION(1, "EXT_IRQ_5"), + BCM63XX_FUNCTION(2, "VREG_CLK"), + BCM63XX_FUNCTION(5, "GPIO_37") + ), + BCM63XX_PIN( + PINCTRL_PIN(38, "GPIO_38"), + BCM63XX_FUNCTION(3, "NAND_CE_B"), + BCM63XX_FUNCTION(5, "GPIO_38") + ), + BCM63XX_PIN( + PINCTRL_PIN(39, "GPIO_39"), + BCM63XX_FUNCTION(3, "NAND_RE_B"), + BCM63XX_FUNCTION(5, "GPIO_39") + ), + BCM63XX_PIN( + PINCTRL_PIN(40, "GPIO_40"), + BCM63XX_FUNCTION(3, "NAND_RB_B"), + BCM63XX_FUNCTION(5, "GPIO_40") + ), + BCM63XX_PIN( + PINCTRL_PIN(41, "GPIO_41"), + BCM63XX_FUNCTION(3, "NAND_DATA_00"), + BCM63XX_FUNCTION(5, "GPIO_41") + ), + BCM63XX_PIN( + PINCTRL_PIN(42, "GPIO_42"), + BCM63XX_FUNCTION(1, "DECT_PD_0"), + BCM63XX_FUNCTION(3, "NAND_DATA_01"), + BCM63XX_FUNCTION(5, "GPIO_42") + ), + BCM63XX_PIN( + PINCTRL_PIN(43, "GPIO_43"), + BCM63XX_FUNCTION(1, "DECT_PD_1"), + BCM63XX_FUNCTION(3, "NAND_DATA_02"), + BCM63XX_FUNCTION(5, "GPIO_43") + ), + BCM63XX_PIN( + PINCTRL_PIN(44, "GPIO_44"), + BCM63XX_FUNCTION(3, "NAND_DATA_03"), + BCM63XX_FUNCTION(5, "GPIO_44") + ), + BCM63XX_PIN( + PINCTRL_PIN(45, "GPIO_45"), + BCM63XX_FUNCTION(3, "NAND_DATA_04"), + BCM63XX_FUNCTION(5, "GPIO_45") + ), + BCM63XX_PIN( + PINCTRL_PIN(46, "GPIO_46"), + BCM63XX_FUNCTION(3, "NAND_DATA_05"), + BCM63XX_FUNCTION(5, "GPIO_46") + ), + BCM63XX_PIN( + PINCTRL_PIN(47, "GPIO_47"), + BCM63XX_FUNCTION(3, "NAND_DATA_06"), + BCM63XX_FUNCTION(5, "GPIO_47") + ), + BCM63XX_PIN( + PINCTRL_PIN(48, "GPIO_48"), + BCM63XX_FUNCTION(3, "NAND_DATA_07"), + BCM63XX_FUNCTION(5, "GPIO_48") + ), + BCM63XX_PIN( + PINCTRL_PIN(49, "GPIO_49"), + BCM63XX_FUNCTION(3, "NAND_ALE"), + BCM63XX_FUNCTION(5, "GPIO_49") + ), + BCM63XX_PIN( + PINCTRL_PIN(50, "GPIO_50"), + BCM63XX_FUNCTION(3, "NAND_WE_B"), + BCM63XX_FUNCTION(5, "GPIO_50") + ), + BCM63XX_PIN( + PINCTRL_PIN(51, "GPIO_51"), + BCM63XX_FUNCTION(3, "NAND_CLE"), + BCM63XX_FUNCTION(5, "GPIO_51") + ), + BCM63XX_PIN( + PINCTRL_PIN(52, "GPIO_52"), + BCM63XX_FUNCTION(1, "LD0_PWRUP"), + BCM63XX_FUNCTION(2, "I2C_SDA"), + BCM63XX_FUNCTION(5, "GPIO_52") + ), + BCM63XX_PIN( + PINCTRL_PIN(53, "GPIO_53"), + BCM63XX_FUNCTION(1, "LD0_DIN"), + BCM63XX_FUNCTION(2, "I2C_SCL"), + BCM63XX_FUNCTION(5, "GPIO_53") + ), + BCM63XX_PIN( + PINCTRL_PIN(54, "GPIO_54"), + BCM63XX_FUNCTION(1, "LD1_PWRUP"), + BCM63XX_FUNCTION(5, "GPIO_54") + ), + BCM63XX_PIN( + PINCTRL_PIN(55, "GPIO_55"), + BCM63XX_FUNCTION(1, "LD0_DCLK"), + BCM63XX_FUNCTION(5, "GPIO_55") + ), + BCM63XX_PIN( + PINCTRL_PIN(56, "GPIO_56"), + BCM63XX_FUNCTION(1, "PCM_SDIN"), + BCM63XX_FUNCTION(5, "GPIO_56") + ), + BCM63XX_PIN( + PINCTRL_PIN(57, "GPIO_57"), + BCM63XX_FUNCTION(1, "PCM_SDOUT"), + BCM63XX_FUNCTION(5, "GPIO_57") + ), + BCM63XX_PIN( + PINCTRL_PIN(58, "GPIO_58"), + BCM63XX_FUNCTION(1, "PCM_CLK"), + BCM63XX_FUNCTION(5, "GPIO_58") + ), + BCM63XX_PIN( + PINCTRL_PIN(59, "GPIO_59"), + BCM63XX_FUNCTION(1, "PCM_FS"), + BCM63XX_FUNCTION(5, "GPIO_59") + ), + BCM63XX_PIN( + PINCTRL_PIN(60, "MII1_COL"), + BCM63XX_FUNCTION(1, "MII1_COL"), + BCM63XX_FUNCTION(5, "GPIO_60") + ), + BCM63XX_PIN( + PINCTRL_PIN(61, "MII1_CRS"), + BCM63XX_FUNCTION(1, "MII1_CRS"), + BCM63XX_FUNCTION(5, "GPIO_61") + ), + BCM63XX_PIN( + PINCTRL_PIN(62, "MII1_RXCLK"), + BCM63XX_FUNCTION(1, "MII1_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_62") + ), + BCM63XX_PIN( + PINCTRL_PIN(63, "MII1_RXER"), + BCM63XX_FUNCTION(1, "MII1_RXER"), + BCM63XX_FUNCTION(5, "GPIO_63") + ), + BCM63XX_PIN( + PINCTRL_PIN(64, "MII1_RXDV"), + BCM63XX_FUNCTION(1, "MII1_RXDV"), + BCM63XX_FUNCTION(5, "GPIO_64") + ), + BCM63XX_PIN( + PINCTRL_PIN(65, "MII_RXD_00"), + BCM63XX_FUNCTION(1, "MII_RXD_00"), + BCM63XX_FUNCTION(5, "GPIO_65") + ), + BCM63XX_PIN( + PINCTRL_PIN(66, "MII_RXD_01"), + BCM63XX_FUNCTION(1, "MII_RXD_01"), + BCM63XX_FUNCTION(5, "GPIO_66") + ), + BCM63XX_PIN( + PINCTRL_PIN(67, "MII_RXD_02"), + BCM63XX_FUNCTION(1, "MII_RXD_02"), + BCM63XX_FUNCTION(5, "GPIO_67") + ), + BCM63XX_PIN( + PINCTRL_PIN(68, "MII_RXD_03"), + BCM63XX_FUNCTION(1, "MII_RXD_03"), + BCM63XX_FUNCTION(5, "GPIO_68") + ), + BCM63XX_PIN( + PINCTRL_PIN(69, "MII_TXCLK"), + BCM63XX_FUNCTION(1, "MII_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_69") + ), + BCM63XX_PIN( + PINCTRL_PIN(70, "MII_TXEN"), + BCM63XX_FUNCTION(1, "MII_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_70") + ), + BCM63XX_PIN( + PINCTRL_PIN(71, "MII_TXER"), + BCM63XX_FUNCTION(1, "MII_TXER"), + BCM63XX_FUNCTION(5, "GPIO_71") + ), + BCM63XX_PIN( + PINCTRL_PIN(72, "MII_TXD_00"), + BCM63XX_FUNCTION(1, "MII_TXD_00"), + BCM63XX_FUNCTION(5, "GPIO_72") + ), + BCM63XX_PIN( + PINCTRL_PIN(73, "MII_TXD_01"), + BCM63XX_FUNCTION(1, "MII_TXD_01"), + BCM63XX_FUNCTION(5, "GPIO_73") + ), + BCM63XX_PIN( + PINCTRL_PIN(74, "MII_TXD_02"), + BCM63XX_FUNCTION(1, "MII_TXD_02"), + BCM63XX_FUNCTION(5, "GPIO_74") + ), + BCM63XX_PIN( + PINCTRL_PIN(75, "MII_TXD_03"), + BCM63XX_FUNCTION(1, "MII_TXD_03"), + BCM63XX_FUNCTION(5, "GPIO_75") + ), + BCM63XX_PIN( + PINCTRL_PIN(76, "RGMII1_RXCLK"), + BCM63XX_FUNCTION(1, "RGMII1_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_76") + ), + BCM63XX_PIN( + PINCTRL_PIN(77, "RGMII1_RXCTL"), + BCM63XX_FUNCTION(1, "RGMII1_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_77") + ), + BCM63XX_PIN( + PINCTRL_PIN(78, "RGMII1_RXD_00"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_00"), + BCM63XX_FUNCTION(5, "GPIO_78") + ), + BCM63XX_PIN( + PINCTRL_PIN(79, "RGMII1_RXD_01"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_01"), + BCM63XX_FUNCTION(5, "GPIO_79") + ), + BCM63XX_PIN( + PINCTRL_PIN(80, "RGMII1_RXD_02"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_02"), + BCM63XX_FUNCTION(5, "GPIO_80") + ), + BCM63XX_PIN( + PINCTRL_PIN(81, "RGMII1_RXD_03"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_03"), + BCM63XX_FUNCTION(5, "GPIO_81") + ), + BCM63XX_PIN( + PINCTRL_PIN(82, "RGMII1_TXCLK"), + BCM63XX_FUNCTION(1, "RGMII1_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_82") + ), + BCM63XX_PIN( + PINCTRL_PIN(83, "RGMII1_TXCTL"), + BCM63XX_FUNCTION(1, "RGMII1_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_83") + ), + BCM63XX_PIN( + PINCTRL_PIN(84, "RGMII1_TXD_00"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_00"), + BCM63XX_FUNCTION(5, "GPIO_84") + ), + BCM63XX_PIN( + PINCTRL_PIN(85, "RGMII1_TXD_01"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_01"), + BCM63XX_FUNCTION(5, "GPIO_85") + ), + BCM63XX_PIN( + PINCTRL_PIN(86, "RGMII1_TXD_02"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_02"), + BCM63XX_FUNCTION(5, "GPIO_86") + ), + BCM63XX_PIN( + PINCTRL_PIN(87, "RGMII1_TXD_03"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_03"), + BCM63XX_FUNCTION(5, "GPIO_87") + ), + BCM63XX_PIN( + PINCTRL_PIN(88, "RGMII2_RXCLK"), + BCM63XX_FUNCTION(1, "RGMII2_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_88") + ), + BCM63XX_PIN( + PINCTRL_PIN(89, "RGMII2_RXCTL"), + BCM63XX_FUNCTION(1, "RGMII2_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_89") + ), + BCM63XX_PIN( + PINCTRL_PIN(90, "RGMII2_RXD_00"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_00"), + BCM63XX_FUNCTION(5, "GPIO_90") + ), + BCM63XX_PIN( + PINCTRL_PIN(91, "RGMII2_RXD_01"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_01"), + BCM63XX_FUNCTION(5, "GPIO_91") + ), + BCM63XX_PIN( + PINCTRL_PIN(92, "RGMII2_RXD_02"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_02"), + BCM63XX_FUNCTION(5, "GPIO_92") + ), + BCM63XX_PIN( + PINCTRL_PIN(93, "RGMII2_RXD_03"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_03"), + BCM63XX_FUNCTION(5, "GPIO_93") + ), + BCM63XX_PIN( + PINCTRL_PIN(94, "RGMII2_TXCLK"), + BCM63XX_FUNCTION(1, "RGMII2_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_94") + ), + BCM63XX_PIN( + PINCTRL_PIN(95, "RGMII2_TXCTL"), + BCM63XX_FUNCTION(1, "RGMII2_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_95") + ), + BCM63XX_PIN( + PINCTRL_PIN(96, "RGMII2_TXD_00"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_00"), + BCM63XX_FUNCTION(5, "GPIO_96") + ), + BCM63XX_PIN( + PINCTRL_PIN(97, "RGMII2_TXD_01"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_01"), + BCM63XX_FUNCTION(5, "GPIO_97") + ), + BCM63XX_PIN( + PINCTRL_PIN(98, "RGMII2_TXD_02"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_02"), + BCM63XX_FUNCTION(5, "GPIO_98") + ), + BCM63XX_PIN( + PINCTRL_PIN(99, "RGMII2_TXD_03"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_03"), + BCM63XX_FUNCTION(5, "GPIO_99") + ), + BCM63XX_PIN( + PINCTRL_PIN(100, "RGMII3_RXCLK"), + BCM63XX_FUNCTION(1, "RGMII3_RXCLK"), + BCM63XX_FUNCTION(4, "LED_00"), + BCM63XX_FUNCTION(5, "GPIO_100") + ), + BCM63XX_PIN( + PINCTRL_PIN(101, "RGMII3_RXCTL"), + BCM63XX_FUNCTION(1, "RGMII3_RXCTL"), + BCM63XX_FUNCTION(4, "LED_01"), + BCM63XX_FUNCTION(5, "GPIO_101") + ), + BCM63XX_PIN( + PINCTRL_PIN(102, "RGMII3_RXD_00"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_00"), + BCM63XX_FUNCTION(4, "LED_02"), + BCM63XX_FUNCTION(5, "GPIO_102") + ), + BCM63XX_PIN( + PINCTRL_PIN(103, "RGMII3_RXD_01"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_01"), + BCM63XX_FUNCTION(4, "LED_03"), + BCM63XX_FUNCTION(5, "GPIO_103") + ), + BCM63XX_PIN( + PINCTRL_PIN(104, "RGMII3_RXD_02"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_02"), + BCM63XX_FUNCTION(4, "LED_04"), + BCM63XX_FUNCTION(5, "GPIO_104") + ), + BCM63XX_PIN( + PINCTRL_PIN(105, "RGMII3_RXD_03"), + BCM63XX_FUNCTION(1, "RGMII3_RXD_03"), + BCM63XX_FUNCTION(4, "LED_05"), + BCM63XX_FUNCTION(5, "GPIO_105") + ), + BCM63XX_PIN( + PINCTRL_PIN(106, "RGMII3_TXCLK"), + BCM63XX_FUNCTION(1, "RGMII3_TXCLK"), + BCM63XX_FUNCTION(4, "LED_06"), + BCM63XX_FUNCTION(5, "GPIO_106") + ), + BCM63XX_PIN( + PINCTRL_PIN(107, "RGMII3_TXCTL"), + BCM63XX_FUNCTION(1, "RGMII3_TXCTL"), + BCM63XX_FUNCTION(4, "LED_07"), + BCM63XX_FUNCTION(5, "GPIO_107") + ), + BCM63XX_PIN( + PINCTRL_PIN(108, "RGMII3_TXD_00"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_00"), + BCM63XX_FUNCTION(4, "LED_08"), + BCM63XX_FUNCTION(5, "GPIO_108"), + BCM63XX_FUNCTION(6, "LED_20") + ), + BCM63XX_PIN( + PINCTRL_PIN(109, "RGMII3_TXD_01"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_01"), + BCM63XX_FUNCTION(4, "LED_09"), + BCM63XX_FUNCTION(5, "GPIO_109"), + BCM63XX_FUNCTION(6, "LED_21") + ), + BCM63XX_PIN( + PINCTRL_PIN(110, "RGMII3_TXD_02"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_02"), + BCM63XX_FUNCTION(4, "LED_10"), + BCM63XX_FUNCTION(5, "GPIO_110") + ), + BCM63XX_PIN( + PINCTRL_PIN(111, "RGMII3_TXD_03"), + BCM63XX_FUNCTION(1, "RGMII3_TXD_03"), + BCM63XX_FUNCTION(4, "LED_11"), + BCM63XX_FUNCTION(5, "GPIO_111") + ), + BCM63XX_PIN( + PINCTRL_PIN(112, "RGMII_MDC"), + BCM63XX_FUNCTION(1, "RGMII_MDC"), + BCM63XX_FUNCTION(5, "GPIO_112") + ), + BCM63XX_PIN( + PINCTRL_PIN(113, "RGMII_MDIO"), + BCM63XX_FUNCTION(1, "RGMII_MDIO"), + BCM63XX_FUNCTION(5, "GPIO_113") + ), + BCM63XX_PIN( + PINCTRL_PIN(114, "BMU_AC_EN"), + BCM63XX_FUNCTION(1, "BMU_AC_EN"), + BCM63XX_FUNCTION(5, "GPIO_114") + ), + BCM63XX_PIN( + PINCTRL_PIN(115, "BMU_DIS_CTRL"), + BCM63XX_FUNCTION(1, "BMU_DIS_CTRL"), + BCM63XX_FUNCTION(5, "GPIO_115") + ), + BCM63XX_PIN( + PINCTRL_PIN(116, "BMU_ENA"), + BCM63XX_FUNCTION(1, "BMU_ENA"), + BCM63XX_FUNCTION(5, "GPIO_116") + ), + BCM63XX_PIN( + PINCTRL_PIN(117, "BMU_ENB"), + BCM63XX_FUNCTION(1, "BMU_ENB"), + BCM63XX_FUNCTION(2, "I2C_SDA"), + BCM63XX_FUNCTION(5, "GPIO_117") + ), + BCM63XX_PIN( + PINCTRL_PIN(118, "BMU_OWA"), + BCM63XX_FUNCTION(1, "BMU_OWA"), + BCM63XX_FUNCTION(5, "GPIO_118") + ), + BCM63XX_PIN( + PINCTRL_PIN(119, "BMU_OWB"), + BCM63XX_FUNCTION(1, "BMU_OWB"), + BCM63XX_FUNCTION(2, "I2C_SCL"), + BCM63XX_FUNCTION(5, "GPIO_119") + ), + BCM63XX_PIN( + PINCTRL_PIN(120, "BMU_PWM_OUT"), + BCM63XX_FUNCTION(1, "BMU_PWM_OUT"), + BCM63XX_FUNCTION(5, "GPIO_120") + ), + BCM63XX_PIN( + PINCTRL_PIN(121, "UART0_SIN"), + BCM63XX_FUNCTION(1, "UART0_SIN"), + BCM63XX_FUNCTION(5, "GPIO_121") + ), + BCM63XX_PIN( + PINCTRL_PIN(122, "UART0_SOUT"), + BCM63XX_FUNCTION(1, "UART0_SOUT"), + BCM63XX_FUNCTION(5, "GPIO_122") + ), + BCM63XX_PIN( + PINCTRL_PIN(123, "SPI_CLK"), + BCM63XX_FUNCTION(0, "SPI_CLK"), + BCM63XX_FUNCTION(5, "GPIO_123") + ), + BCM63XX_PIN( + PINCTRL_PIN(124, "SPI_MOSI"), + BCM63XX_FUNCTION(0, "SPI_MOSI"), + BCM63XX_FUNCTION(5, "GPIO_124") + ), + BCM63XX_PIN( + PINCTRL_PIN(125, "SPI_MISO"), + BCM63XX_FUNCTION(0, "SPI_MISO"), + BCM63XX_FUNCTION(1, "SPI_MISO"), + BCM63XX_FUNCTION(5, "GPIO_125") + ), + BCM63XX_PIN( + PINCTRL_PIN(126, "SPI_SSB0"), + BCM63XX_FUNCTION(0, "SPI_SSB0"), + BCM63XX_FUNCTION(1, "SPI_SSB0"), + BCM63XX_FUNCTION(5, "GPIO_126") + ), + BCM63XX_PIN( + PINCTRL_PIN(127, "SPI_SSB1"), + BCM63XX_FUNCTION(0, "SPI_SSB1"), + BCM63XX_FUNCTION(1, "SPI_SSB1"), + BCM63XX_FUNCTION(5, "GPIO_127") + ), + BCM63XX_PIN( + PINCTRL_PIN(128, "PCIE0_CLKREQ_B"), + BCM63XX_FUNCTION(0, "PCIE0_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_128") + ), + BCM63XX_PIN( + PINCTRL_PIN(129, "PCIE0_RST_B"), + BCM63XX_FUNCTION(0, "PCIE0_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_129") + ), + BCM63XX_PIN( + PINCTRL_PIN(130, "PCIE1_CLKREQ_B"), + BCM63XX_FUNCTION(0, "PCIE1_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_130") + ), + BCM63XX_PIN( + PINCTRL_PIN(131, "PCIE1_RST_B"), + BCM63XX_FUNCTION(0, "PCIE1_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_131") + ), + BCM63XX_PIN( + PINCTRL_PIN(132, "USB0_PWRFLT"), + BCM63XX_FUNCTION(1, "USB0_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_132") + ), + BCM63XX_PIN( + PINCTRL_PIN(133, "USB0_PWRON"), + BCM63XX_FUNCTION(1, "USB0_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_133") + ), + BCM63XX_PIN( + PINCTRL_PIN(134, "USB1_PWRFLT"), + BCM63XX_FUNCTION(1, "USB1_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_134") + ), + BCM63XX_PIN( + PINCTRL_PIN(135, "USB1_PWRON"), + BCM63XX_FUNCTION(1, "USB1_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_135") + ), + BCM63XX_PIN( + PINCTRL_PIN(136, "RESET_OUT_B"), + BCM63XX_FUNCTION(0, "RESET_OUT_B"), + BCM63XX_FUNCTION(5, "GPIO_136") + ), + BCM63XX_PIN( + PINCTRL_PIN(137, "DECT_RDI"), + BCM63XX_FUNCTION(1, "DECT_RDI"), + BCM63XX_FUNCTION(5, "GPIO_137") + ), + BCM63XX_PIN( + PINCTRL_PIN(138, "DECT_BTDO"), + BCM63XX_FUNCTION(1, "DECT_BTDO"), + BCM63XX_FUNCTION(5, "GPIO_138") + ), + BCM63XX_PIN( + PINCTRL_PIN(139, "DECT_MWR_LE"), + BCM63XX_FUNCTION(1, "DECT_MWR_LE"), + BCM63XX_FUNCTION(5, "GPIO_139") + ), + BCM63XX_PIN( + PINCTRL_PIN(140, "DECT_MWR_SK"), + BCM63XX_FUNCTION(1, "DECT_MWR_SK"), + BCM63XX_FUNCTION(5, "GPIO_140") + ), + BCM63XX_PIN( + PINCTRL_PIN(141, "DECT_MWR_SIO"), + BCM63XX_FUNCTION(1, "DECT_MWR_SIO"), + BCM63XX_FUNCTION(5, "GPIO_141") + ), +}; --- /dev/null 2021-04-15 09:21:41.728292489 +0200 +++ linux-5.4.60-fbx/drivers/pinctrl/bcm/pindesc-bcm63158.h 2021-03-04 13:20:59.550838968 +0100 @@ -0,0 +1,759 @@ +static const struct bcm63xx_desc_pin bcm63158_desc_pins[] = { + BCM63XX_PIN( + PINCTRL_PIN(0, "GPIO_00"), + BCM63XX_FUNCTION(1, "A_SER_LED_DATA"), + BCM63XX_FUNCTION(4, "A_LED_00"), + BCM63XX_FUNCTION(5, "GPIO_00") + ), + BCM63XX_PIN( + PINCTRL_PIN(1, "GPIO_01"), + BCM63XX_FUNCTION(1, "A_SER_LED_CLK"), + BCM63XX_FUNCTION(4, "A_LED_01"), + BCM63XX_FUNCTION(5, "GPIO_01") + ), + BCM63XX_PIN( + PINCTRL_PIN(2, "GPIO_02"), + BCM63XX_FUNCTION(1, "A_SER_LED_MASK"), + BCM63XX_FUNCTION(4, "A_LED_02"), + BCM63XX_FUNCTION(5, "GPIO_02") + ), + BCM63XX_PIN( + PINCTRL_PIN(3, "GPIO_03"), + BCM63XX_FUNCTION(1, "A_UART2_CTS"), + BCM63XX_FUNCTION(2, "B_PPS_IN"), + BCM63XX_FUNCTION(4, "A_LED_03"), + BCM63XX_FUNCTION(5, "GPIO_03") + ), + BCM63XX_PIN( + PINCTRL_PIN(4, "GPIO_04"), + BCM63XX_FUNCTION(1, "A_UART2_RTS"), + BCM63XX_FUNCTION(2, "B_PPS_OUT"), + BCM63XX_FUNCTION(4, "A_LED_04"), + BCM63XX_FUNCTION(5, "GPIO_04") + ), + BCM63XX_PIN( + PINCTRL_PIN(5, "GPIO_05"), + BCM63XX_FUNCTION(1, "A_UART2_SIN"), + BCM63XX_FUNCTION(4, "A_LED_05"), + BCM63XX_FUNCTION(5, "GPIO_05") + ), + BCM63XX_PIN( + PINCTRL_PIN(6, "GPIO_06"), + BCM63XX_FUNCTION(1, "A_UART2_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_06"), + BCM63XX_FUNCTION(5, "GPIO_06") + ), + BCM63XX_PIN( + PINCTRL_PIN(7, "GPIO_07"), + BCM63XX_FUNCTION(1, "A_SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "B_NTR_OUT"), + BCM63XX_FUNCTION(4, "A_LED_07"), + BCM63XX_FUNCTION(5, "GPIO_07"), + BCM63XX_FUNCTION(6, "B_NTR_IN") + ), + BCM63XX_PIN( + PINCTRL_PIN(8, "GPIO_08"), + BCM63XX_FUNCTION(1, "A_SPIM_SS4_B"), + BCM63XX_FUNCTION(4, "A_LED_08"), + BCM63XX_FUNCTION(5, "GPIO_08") + ), + BCM63XX_PIN( + PINCTRL_PIN(9, "GPIO_09"), + BCM63XX_FUNCTION(1, "A_SPIM_SS3_B"), + BCM63XX_FUNCTION(3, "B_USBD_ID"), + BCM63XX_FUNCTION(4, "A_LED_09"), + BCM63XX_FUNCTION(5, "GPIO_09"), + BCM63XX_FUNCTION(6, "A_AE_SERDES_MOD_DEF0") + ), + BCM63XX_PIN( + PINCTRL_PIN(10, "GPIO_10"), + BCM63XX_FUNCTION(1, "A_SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "A_PMD_EXT_LOS"), + BCM63XX_FUNCTION(3, "B_USBD_VBUS_PRESENT"), + BCM63XX_FUNCTION(4, "A_LED_10"), + BCM63XX_FUNCTION(5, "GPIO_10"), + BCM63XX_FUNCTION(6, "A_AE_FIBER_DETECT") + ), + BCM63XX_PIN( + PINCTRL_PIN(11, "GPIO_11"), + BCM63XX_FUNCTION(2, "A_I2C_SDA_0"), + BCM63XX_FUNCTION(4, "A_LED_11"), + BCM63XX_FUNCTION(5, "GPIO_11") + ), + BCM63XX_PIN( + PINCTRL_PIN(12, "GPIO_12"), + BCM63XX_FUNCTION(1, "A_PPS_IN"), + BCM63XX_FUNCTION(2, "A_I2C_SCL_0"), + BCM63XX_FUNCTION(4, "A_LED_12"), + BCM63XX_FUNCTION(5, "GPIO_12"), + BCM63XX_FUNCTION(6, "C_SGMII_SERDES_MOD_DEF0") + ), + BCM63XX_PIN( + PINCTRL_PIN(13, "GPIO_13"), + BCM63XX_FUNCTION(1, "A_PPS_OUT"), + BCM63XX_FUNCTION(4, "A_LED_13"), + BCM63XX_FUNCTION(5, "GPIO_13") + ), + BCM63XX_PIN( + PINCTRL_PIN(14, "GPIO_14"), + BCM63XX_FUNCTION(1, "A_NTR_OUT"), + BCM63XX_FUNCTION(2, "I2S_RX_SDATA"), + BCM63XX_FUNCTION(4, "A_LED_14"), + BCM63XX_FUNCTION(5, "GPIO_14"), + BCM63XX_FUNCTION(6, "A_NTR_IN") + ), + BCM63XX_PIN( + PINCTRL_PIN(15, "GPIO_15"), + BCM63XX_FUNCTION(2, "SW_SPIS_CLK"), + BCM63XX_FUNCTION(4, "A_LED_15"), + BCM63XX_FUNCTION(5, "GPIO_15"), + BCM63XX_FUNCTION(6, "B_I2C_SDA_1") + ), + BCM63XX_PIN( + PINCTRL_PIN(16, "GPIO_16"), + BCM63XX_FUNCTION(2, "SW_SPIS_SS_B"), + BCM63XX_FUNCTION(4, "A_LED_16"), + BCM63XX_FUNCTION(5, "GPIO_16"), + BCM63XX_FUNCTION(6, "B_I2C_SCL_1") + ), + BCM63XX_PIN( + PINCTRL_PIN(17, "GPIO_17"), + BCM63XX_FUNCTION(2, "SW_SPIS_MISO"), + BCM63XX_FUNCTION(4, "A_LED_17"), + BCM63XX_FUNCTION(5, "GPIO_17"), + BCM63XX_FUNCTION(6, "C_UART3_SIN") + ), + BCM63XX_PIN( + PINCTRL_PIN(18, "GPIO_18"), + BCM63XX_FUNCTION(2, "SW_SPIS_MOSI"), + BCM63XX_FUNCTION(4, "A_LED_18"), + BCM63XX_FUNCTION(5, "GPIO_18"), + BCM63XX_FUNCTION(6, "C_UART3_SOUT") + ), + BCM63XX_PIN( + PINCTRL_PIN(19, "GPIO_19"), + BCM63XX_FUNCTION(2, "VREG_SYNC"), + BCM63XX_FUNCTION(4, "A_LED_19"), + BCM63XX_FUNCTION(5, "GPIO_19"), + BCM63XX_FUNCTION(6, "A_SGMII_FIBER_DETECT") + ), + BCM63XX_PIN( + PINCTRL_PIN(20, "GPIO_20"), + BCM63XX_FUNCTION(1, "SPIS_CLK"), + BCM63XX_FUNCTION(2, "B_UART2_CTS"), + BCM63XX_FUNCTION(3, "B_UART3_SIN"), + BCM63XX_FUNCTION(4, "A_LED_20"), + BCM63XX_FUNCTION(5, "GPIO_20"), + BCM63XX_FUNCTION(6, "A_SGMII_SERDES_MOD_DEF0") + ), + BCM63XX_PIN( + PINCTRL_PIN(21, "GPIO_21"), + BCM63XX_FUNCTION(1, "SPIS_SS_B"), + BCM63XX_FUNCTION(2, "B_UART2_RTS"), + BCM63XX_FUNCTION(3, "B_UART3_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_21"), + BCM63XX_FUNCTION(5, "GPIO_21"), + BCM63XX_FUNCTION(6, "C_SGMII_FIBER_DETECT") + ), + BCM63XX_PIN( + PINCTRL_PIN(22, "GPIO_22"), + BCM63XX_FUNCTION(1, "SPIS_MISO"), + BCM63XX_FUNCTION(2, "B_UART2_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_22"), + BCM63XX_FUNCTION(5, "GPIO_22") + ), + BCM63XX_PIN( + PINCTRL_PIN(23, "GPIO_23"), + BCM63XX_FUNCTION(1, "SPIS_MOSI"), + BCM63XX_FUNCTION(2, "B_UART2_SIN"), + BCM63XX_FUNCTION(4, "A_LED_23"), + BCM63XX_FUNCTION(5, "GPIO_23") + ), + BCM63XX_PIN( + PINCTRL_PIN(24, "GPIO_24"), + BCM63XX_FUNCTION(2, "B_UART1_SOUT"), + BCM63XX_FUNCTION(3, "B_I2C_SDA_0"), + BCM63XX_FUNCTION(4, "A_LED_24"), + BCM63XX_FUNCTION(5, "GPIO_24") + ), + BCM63XX_PIN( + PINCTRL_PIN(25, "GPIO_25"), + BCM63XX_FUNCTION(1, "B_SPIM_SS2_B"), + BCM63XX_FUNCTION(2, "B_UART1_SIN"), + BCM63XX_FUNCTION(3, "B_I2C_SCL_0"), + BCM63XX_FUNCTION(4, "A_LED_25"), + BCM63XX_FUNCTION(5, "GPIO_25") + ), + BCM63XX_PIN( + PINCTRL_PIN(26, "GPIO_26"), + BCM63XX_FUNCTION(1, "B_SPIM_SS3_B"), + BCM63XX_FUNCTION(2, "A_I2C_SDA_1"), + BCM63XX_FUNCTION(3, "A_UART3_SIN"), + BCM63XX_FUNCTION(4, "A_LED_26"), + BCM63XX_FUNCTION(5, "GPIO_26") + ), + BCM63XX_PIN( + PINCTRL_PIN(27, "GPIO_27"), + BCM63XX_FUNCTION(1, "B_SPIM_SS4_B"), + BCM63XX_FUNCTION(2, "A_I2C_SCL_1"), + BCM63XX_FUNCTION(3, "A_UART3_SOUT"), + BCM63XX_FUNCTION(4, "A_LED_27"), + BCM63XX_FUNCTION(5, "GPIO_27") + ), + BCM63XX_PIN( + PINCTRL_PIN(28, "GPIO_28"), + BCM63XX_FUNCTION(1, "B_SPIM_SS5_B"), + BCM63XX_FUNCTION(2, "I2S_MCLK"), + BCM63XX_FUNCTION(4, "A_LED_28"), + BCM63XX_FUNCTION(5, "GPIO_28") + ), + BCM63XX_PIN( + PINCTRL_PIN(29, "GPIO_29"), + BCM63XX_FUNCTION(1, "B_SER_LED_DATA"), + BCM63XX_FUNCTION(2, "I2S_LRCK"), + BCM63XX_FUNCTION(4, "A_LED_29"), + BCM63XX_FUNCTION(5, "GPIO_29") + ), + BCM63XX_PIN( + PINCTRL_PIN(30, "GPIO_30"), + BCM63XX_FUNCTION(1, "B_SER_LED_CLK"), + BCM63XX_FUNCTION(2, "I2S_SCLK"), + BCM63XX_FUNCTION(4, "A_LED_30"), + BCM63XX_FUNCTION(5, "GPIO_30") + ), + BCM63XX_PIN( + PINCTRL_PIN(31, "GPIO_31"), + BCM63XX_FUNCTION(1, "B_SER_LED_MASK"), + BCM63XX_FUNCTION(2, "I2S_TX_SDATA"), + BCM63XX_FUNCTION(4, "A_LED_31"), + BCM63XX_FUNCTION(5, "GPIO_31") + ), + BCM63XX_PIN( + PINCTRL_PIN(32, "GPIO_32"), + BCM63XX_FUNCTION(2, "VDSL_CTRL0"), + BCM63XX_FUNCTION(5, "GPIO_32") + ), + BCM63XX_PIN( + PINCTRL_PIN(33, "GPIO_33"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_1"), + BCM63XX_FUNCTION(3, "B_WAN_EARLY_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_33") + ), + BCM63XX_PIN( + PINCTRL_PIN(34, "GPIO_34"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_2"), + BCM63XX_FUNCTION(3, "B_ROGUE_IN"), + BCM63XX_FUNCTION(5, "GPIO_34") + ), + BCM63XX_PIN( + PINCTRL_PIN(35, "GPIO_35"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_3"), + BCM63XX_FUNCTION(3, "B_SGMII_FIBER_DETECT"), + BCM63XX_FUNCTION(5, "GPIO_35") + ), + BCM63XX_PIN( + PINCTRL_PIN(36, "GPIO_36"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_4"), + BCM63XX_FUNCTION(3, "B_SGMII_SERDES_MOD_DEF0"), + BCM63XX_FUNCTION(5, "GPIO_36") + ), + BCM63XX_PIN( + PINCTRL_PIN(37, "GPIO_37"), + BCM63XX_FUNCTION(1, "B_PMD_EXT_LOS"), + BCM63XX_FUNCTION(2, "VDSL_CTRL_5"), + BCM63XX_FUNCTION(3, "B_AE_FIBER_DETECT"), + BCM63XX_FUNCTION(5, "GPIO_37") + ), + BCM63XX_PIN( + PINCTRL_PIN(38, "GPIO_38"), + BCM63XX_FUNCTION(2, "B_VREG_SYNC"), + BCM63XX_FUNCTION(3, "B_AE_SERDES_MOD_DEF0"), + BCM63XX_FUNCTION(5, "GPIO_38") + ), + BCM63XX_PIN( + PINCTRL_PIN(39, "GPIO_39"), + BCM63XX_FUNCTION(2, "A_WAN_EARLY_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_39") + ), + BCM63XX_PIN( + PINCTRL_PIN(40, "GPIO_40"), + BCM63XX_FUNCTION(2, "A_ROGUE_IN"), + BCM63XX_FUNCTION(5, "GPIO_40") + ), + BCM63XX_PIN( + PINCTRL_PIN(41, "GPIO_41"), + BCM63XX_FUNCTION(2, "SYS_IRQ_OUT"), + BCM63XX_FUNCTION(3, "C_WAN_EARLY_TXEN"), + BCM63XX_FUNCTION(5, "GPIO_41") + ), + BCM63XX_PIN( + PINCTRL_PIN(42, "GPIO_42"), + BCM63XX_FUNCTION(1, "PCM_SDIN"), + BCM63XX_FUNCTION(4, "A_UART1_SIN"), + BCM63XX_FUNCTION(5, "GPIO_42") + ), + BCM63XX_PIN( + PINCTRL_PIN(43, "GPIO_43"), + BCM63XX_FUNCTION(1, "PCM_SDOUT"), + BCM63XX_FUNCTION(4, "A_UART1_SOUT"), + BCM63XX_FUNCTION(5, "GPIO_43") + ), + BCM63XX_PIN( + PINCTRL_PIN(44, "GPIO_44"), + BCM63XX_FUNCTION(1, "PCM_CLK"), + BCM63XX_FUNCTION(4, "A_USBD_VBUS_PRESENT"), + BCM63XX_FUNCTION(5, "GPIO_44") + ), + BCM63XX_PIN( + PINCTRL_PIN(45, "GPIO_45"), + BCM63XX_FUNCTION(1, "PCM_FS"), + BCM63XX_FUNCTION(4, "A_USBD_ID"), + BCM63XX_FUNCTION(5, "GPIO_45") + ), + BCM63XX_PIN( + PINCTRL_PIN(46, "GPIO_46"), + BCM63XX_FUNCTION(2, "C_VREG_SYNC"), + BCM63XX_FUNCTION(5, "GPIO_46") + ), + BCM63XX_PIN( + PINCTRL_PIN(47, "GPIO_47"), + BCM63XX_FUNCTION(3, "NAND_WP"), + BCM63XX_FUNCTION(5, "GPIO_47") + ), + BCM63XX_PIN( + PINCTRL_PIN(48, "GPIO_48"), + BCM63XX_FUNCTION(3, "NAND_CE_B"), + BCM63XX_FUNCTION(5, "GPIO_48") + ), + BCM63XX_PIN( + PINCTRL_PIN(49, "GPIO_49"), + BCM63XX_FUNCTION(3, "NAND_RE_B"), + BCM63XX_FUNCTION(5, "GPIO_49") + ), + BCM63XX_PIN( + PINCTRL_PIN(50, "GPIO_50"), + BCM63XX_FUNCTION(3, "NAND_RB_B"), + BCM63XX_FUNCTION(5, "GPIO_50") + ), + BCM63XX_PIN( + PINCTRL_PIN(51, "GPIO_51"), + BCM63XX_FUNCTION(3, "NAND_DATA_0"), + BCM63XX_FUNCTION(5, "GPIO_51") + ), + BCM63XX_PIN( + PINCTRL_PIN(52, "GPIO_52"), + BCM63XX_FUNCTION(3, "NAND_DATA_1"), + BCM63XX_FUNCTION(5, "GPIO_52") + ), + BCM63XX_PIN( + PINCTRL_PIN(53, "GPIO_53"), + BCM63XX_FUNCTION(3, "NAND_DATA_2"), + BCM63XX_FUNCTION(5, "GPIO_53") + ), + BCM63XX_PIN( + PINCTRL_PIN(54, "GPIO_54"), + BCM63XX_FUNCTION(3, "NAND_DATA_3"), + BCM63XX_FUNCTION(5, "GPIO_54") + ), + BCM63XX_PIN( + PINCTRL_PIN(55, "GPIO_55"), + BCM63XX_FUNCTION(3, "NAND_DATA_4"), + BCM63XX_FUNCTION(5, "GPIO_55") + ), + BCM63XX_PIN( + PINCTRL_PIN(56, "GPIO_56"), + BCM63XX_FUNCTION(3, "NAND_DATA_5"), + BCM63XX_FUNCTION(5, "GPIO_56") + ), + BCM63XX_PIN( + PINCTRL_PIN(57, "GPIO_57"), + BCM63XX_FUNCTION(3, "NAND_DATA_6"), + BCM63XX_FUNCTION(5, "GPIO_57") + ), + BCM63XX_PIN( + PINCTRL_PIN(58, "GPIO_58"), + BCM63XX_FUNCTION(3, "NAND_DATA_7"), + BCM63XX_FUNCTION(5, "GPIO_58") + ), + BCM63XX_PIN( + PINCTRL_PIN(59, "GPIO_59"), + BCM63XX_FUNCTION(3, "NAND_ALE"), + BCM63XX_FUNCTION(5, "GPIO_59") + ), + BCM63XX_PIN( + PINCTRL_PIN(60, "GPIO_60"), + BCM63XX_FUNCTION(3, "NAND_WE_B"), + BCM63XX_FUNCTION(5, "GPIO_60") + ), + BCM63XX_PIN( + PINCTRL_PIN(61, "GPIO_61"), + BCM63XX_FUNCTION(3, "NAND_CLE"), + BCM63XX_FUNCTION(5, "GPIO_61") + ), + BCM63XX_PIN( + PINCTRL_PIN(62, "GPIO_62"), + BCM63XX_FUNCTION(2, "NAND_CE2_B"), + BCM63XX_FUNCTION(3, "EMMC_CLK"), + BCM63XX_FUNCTION(5, "GPIO_62") + ), + BCM63XX_PIN( + PINCTRL_PIN(63, "GPIO_63"), + BCM63XX_FUNCTION(2, "NAND_CE1_B"), + BCM63XX_FUNCTION(3, "EMMC_CMD"), + BCM63XX_FUNCTION(5, "GPIO_63") + ), + BCM63XX_PIN( + PINCTRL_PIN(64, "GPIO_64"), + BCM63XX_FUNCTION(1, "RGMII0_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_64"), + BCM63XX_FUNCTION(6, "B_LED_00") + ), + BCM63XX_PIN( + PINCTRL_PIN(65, "GPIO_65"), + BCM63XX_FUNCTION(5, "GPIO_65"), + BCM63XX_FUNCTION(6, "B_LED_01") + ), + BCM63XX_PIN( + PINCTRL_PIN(66, "GPIO_66"), + BCM63XX_FUNCTION(1, "RGMII0_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_66"), + BCM63XX_FUNCTION(6, "B_LED_02") + ), + BCM63XX_PIN( + PINCTRL_PIN(67, "GPIO_67"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_0"), + BCM63XX_FUNCTION(5, "GPIO_67"), + BCM63XX_FUNCTION(6, "B_LED_03") + ), + BCM63XX_PIN( + PINCTRL_PIN(68, "GPIO_68"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_1"), + BCM63XX_FUNCTION(5, "GPIO_68"), + BCM63XX_FUNCTION(6, "B_LED_04") + ), + BCM63XX_PIN( + PINCTRL_PIN(69, "GPIO_69"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_2"), + BCM63XX_FUNCTION(5, "GPIO_69"), + BCM63XX_FUNCTION(6, "B_LED_05") + ), + BCM63XX_PIN( + PINCTRL_PIN(70, "GPIO_70"), + BCM63XX_FUNCTION(1, "RGMII0_RXD_3"), + BCM63XX_FUNCTION(5, "GPIO_70"), + BCM63XX_FUNCTION(6, "B_LED_06") + ), + BCM63XX_PIN( + PINCTRL_PIN(71, "GPIO_71"), + BCM63XX_FUNCTION(1, "RGMII0_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_71"), + BCM63XX_FUNCTION(6, "B_LED_07") + ), + BCM63XX_PIN( + PINCTRL_PIN(72, "GPIO_72"), + BCM63XX_FUNCTION(1, "RGMII0_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_72"), + BCM63XX_FUNCTION(6, "B_LED_08") + ), + BCM63XX_PIN( + PINCTRL_PIN(73, "GPIO_73"), + BCM63XX_FUNCTION(5, "GPIO_73"), + BCM63XX_FUNCTION(6, "B_LED_09") + ), + BCM63XX_PIN( + PINCTRL_PIN(74, "GPIO_74"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_0"), + BCM63XX_FUNCTION(5, "GPIO_74"), + BCM63XX_FUNCTION(6, "B_LED_10") + ), + BCM63XX_PIN( + PINCTRL_PIN(75, "GPIO_75"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_1"), + BCM63XX_FUNCTION(5, "GPIO_75"), + BCM63XX_FUNCTION(6, "B_LED_11") + ), + BCM63XX_PIN( + PINCTRL_PIN(76, "GPIO_76"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_2"), + BCM63XX_FUNCTION(5, "GPIO_76"), + BCM63XX_FUNCTION(6, "B_LED_12") + ), + BCM63XX_PIN( + PINCTRL_PIN(77, "GPIO_77"), + BCM63XX_FUNCTION(1, "RGMII0_TXD_3"), + BCM63XX_FUNCTION(5, "GPIO_77"), + BCM63XX_FUNCTION(6, "B_LED_13") + ), + BCM63XX_PIN( + PINCTRL_PIN(78, "GPIO_78"), + BCM63XX_FUNCTION(5, "GPIO_78"), + BCM63XX_FUNCTION(6, "B_LED_14") + ), + BCM63XX_PIN( + PINCTRL_PIN(79, "GPIO_79"), + BCM63XX_FUNCTION(5, "GPIO_79"), + BCM63XX_FUNCTION(6, "B_LED_15") + ), + BCM63XX_PIN( + PINCTRL_PIN(80, "GPIO_80"), + BCM63XX_FUNCTION(1, "RGMII1_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_80"), + BCM63XX_FUNCTION(6, "B_LED_16") + ), + BCM63XX_PIN( + PINCTRL_PIN(81, "GPIO_81"), + BCM63XX_FUNCTION(1, "RGMII1_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_81"), + BCM63XX_FUNCTION(6, "B_LED_17") + ), + BCM63XX_PIN( + PINCTRL_PIN(82, "GPIO_82"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_0"), + BCM63XX_FUNCTION(5, "GPIO_82"), + BCM63XX_FUNCTION(6, "B_LED_18") + ), + BCM63XX_PIN( + PINCTRL_PIN(83, "GPIO_83"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_1"), + BCM63XX_FUNCTION(5, "GPIO_83"), + BCM63XX_FUNCTION(6, "B_LED_19") + ), + BCM63XX_PIN( + PINCTRL_PIN(84, "GPIO_84"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_2"), + BCM63XX_FUNCTION(5, "GPIO_84"), + BCM63XX_FUNCTION(6, "B_LED_20") + ), + BCM63XX_PIN( + PINCTRL_PIN(85, "GPIO_85"), + BCM63XX_FUNCTION(1, "RGMII1_RXD_3"), + BCM63XX_FUNCTION(5, "GPIO_85"), + BCM63XX_FUNCTION(6, "B_LED_21") + ), + BCM63XX_PIN( + PINCTRL_PIN(86, "GPIO_86"), + BCM63XX_FUNCTION(1, "RGMII1_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_86"), + BCM63XX_FUNCTION(6, "B_LED_22") + ), + BCM63XX_PIN( + PINCTRL_PIN(87, "GPIO_87"), + BCM63XX_FUNCTION(1, "RGMII1_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_87"), + BCM63XX_FUNCTION(6, "B_LED_23") + ), + BCM63XX_PIN( + PINCTRL_PIN(88, "GPIO_88"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_0"), + BCM63XX_FUNCTION(5, "GPIO_88"), + BCM63XX_FUNCTION(6, "B_LED_24") + ), + BCM63XX_PIN( + PINCTRL_PIN(89, "GPIO_89"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_1"), + BCM63XX_FUNCTION(5, "GPIO_89"), + BCM63XX_FUNCTION(6, "B_LED_25") + ), + BCM63XX_PIN( + PINCTRL_PIN(90, "GPIO_90"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_2"), + BCM63XX_FUNCTION(5, "GPIO_90"), + BCM63XX_FUNCTION(6, "B_LED_26") + ), + BCM63XX_PIN( + PINCTRL_PIN(91, "GPIO_91"), + BCM63XX_FUNCTION(1, "RGMII1_TXD_3"), + BCM63XX_FUNCTION(5, "GPIO_91"), + BCM63XX_FUNCTION(6, "B_LED_27") + ), + BCM63XX_PIN( + PINCTRL_PIN(92, "GPIO_92"), + BCM63XX_FUNCTION(1, "RGMII2_RXCLK"), + BCM63XX_FUNCTION(5, "GPIO_92"), + BCM63XX_FUNCTION(6, "B_LED_28") + ), + BCM63XX_PIN( + PINCTRL_PIN(93, "GPIO_93"), + BCM63XX_FUNCTION(1, "RGMII2_RXCTL"), + BCM63XX_FUNCTION(5, "GPIO_93"), + BCM63XX_FUNCTION(6, "B_LED_29") + ), + BCM63XX_PIN( + PINCTRL_PIN(94, "GPIO_94"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_0"), + BCM63XX_FUNCTION(5, "GPIO_94"), + BCM63XX_FUNCTION(6, "B_LED_30") + ), + BCM63XX_PIN( + PINCTRL_PIN(95, "GPIO_95"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_1"), + BCM63XX_FUNCTION(5, "GPIO_95"), + BCM63XX_FUNCTION(6, "B_LED_31") + ), + BCM63XX_PIN( + PINCTRL_PIN(96, "GPIO_96"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_2"), + BCM63XX_FUNCTION(5, "GPIO_96") + ), + BCM63XX_PIN( + PINCTRL_PIN(97, "GPIO_97"), + BCM63XX_FUNCTION(1, "RGMII2_RXD_3"), + BCM63XX_FUNCTION(5, "GPIO_97") + ), + BCM63XX_PIN( + PINCTRL_PIN(98, "GPIO_98"), + BCM63XX_FUNCTION(1, "RGMII2_TXCLK"), + BCM63XX_FUNCTION(5, "GPIO_98") + ), + BCM63XX_PIN( + PINCTRL_PIN(99, "GPIO_99"), + BCM63XX_FUNCTION(1, "RGMII2_TXCTL"), + BCM63XX_FUNCTION(5, "GPIO_99") + ), + BCM63XX_PIN( + PINCTRL_PIN(100, "GPIO_100"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_0"), + BCM63XX_FUNCTION(5, "GPIO_100") + ), + BCM63XX_PIN( + PINCTRL_PIN(101, "GPIO_101"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_1"), + BCM63XX_FUNCTION(5, "GPIO_101") + ), + BCM63XX_PIN( + PINCTRL_PIN(102, "GPIO_102"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_2"), + BCM63XX_FUNCTION(5, "GPIO_102") + ), + BCM63XX_PIN( + PINCTRL_PIN(103, "GPIO_103"), + BCM63XX_FUNCTION(1, "RGMII2_TXD_3"), + BCM63XX_FUNCTION(5, "GPIO_103") + ), + BCM63XX_PIN( + PINCTRL_PIN(104, "GPIO_104"), + BCM63XX_FUNCTION(1, "RGMII_MDC"), + BCM63XX_FUNCTION(5, "GPIO_104") + ), + BCM63XX_PIN( + PINCTRL_PIN(105, "GPIO_105"), + BCM63XX_FUNCTION(1, "RGMII_MDIO"), + BCM63XX_FUNCTION(5, "GPIO_105") + ), + BCM63XX_PIN( + PINCTRL_PIN(106, "GPIO_106"), + BCM63XX_FUNCTION(1, "UART0_SDIN"), + BCM63XX_FUNCTION(5, "GPIO_106") + ), + BCM63XX_PIN( + PINCTRL_PIN(107, "GPIO_107"), + BCM63XX_FUNCTION(1, "UART0_SDOUT"), + BCM63XX_FUNCTION(5, "GPIO_107") + ), + BCM63XX_PIN( + PINCTRL_PIN(108, "GPIO_108"), + BCM63XX_FUNCTION(0, "SPIM_CLK"), + BCM63XX_FUNCTION(5, "GPIO_108") + ), + BCM63XX_PIN( + PINCTRL_PIN(109, "GPIO_109"), + BCM63XX_FUNCTION(0, "SPIM_MOSI"), + BCM63XX_FUNCTION(5, "GPIO_109") + ), + BCM63XX_PIN( + PINCTRL_PIN(110, "GPIO_110"), + BCM63XX_FUNCTION(0, "SPIM_MISO"), + BCM63XX_FUNCTION(5, "GPIO_110") + ), + BCM63XX_PIN( + PINCTRL_PIN(111, "GPIO_111"), + BCM63XX_FUNCTION(0, "SPIM_SS0_B"), + BCM63XX_FUNCTION(5, "GPIO_111") + ), + BCM63XX_PIN( + PINCTRL_PIN(112, "GPIO_112"), + BCM63XX_FUNCTION(0, "SPIM_SS1_B"), + BCM63XX_FUNCTION(5, "GPIO_112") + ), + BCM63XX_PIN( + PINCTRL_PIN(113, "GPIO_113"), + BCM63XX_FUNCTION(1, "PCIE0a_CLKREQ_B"), + BCM63XX_FUNCTION(2, "PCIE2b_CLKREQ_B"), + BCM63XX_FUNCTION(3, "PCIE1c_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_113") + ), + BCM63XX_PIN( + PINCTRL_PIN(114, "GPIO_114"), + BCM63XX_FUNCTION(1, "PCIE0a_RST_B"), + BCM63XX_FUNCTION(2, "PCIE2b_RST_B"), + BCM63XX_FUNCTION(3, "PCIE1c_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_114") + ), + BCM63XX_PIN( + PINCTRL_PIN(115, "GPIO_115"), + BCM63XX_FUNCTION(1, "PCIE1a_CLKREQ_B"), + BCM63XX_FUNCTION(2, "PCIE0b_CLKREQ_B"), + BCM63XX_FUNCTION(3, "PCIE2c_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_115") + ), + BCM63XX_PIN( + PINCTRL_PIN(116, "GPIO_116"), + BCM63XX_FUNCTION(1, "PCIE1a_RST_B"), + BCM63XX_FUNCTION(2, "PCIE0b_RST_B"), + BCM63XX_FUNCTION(3, "PCIE2c_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_116") + ), + BCM63XX_PIN( + PINCTRL_PIN(117, "GPIO_117"), + BCM63XX_FUNCTION(1, "PCIE2a_CLKREQ_B"), + BCM63XX_FUNCTION(2, "PCIE1b_CLKREQ_B"), + BCM63XX_FUNCTION(3, "PCIE0c_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_117") + ), + BCM63XX_PIN( + PINCTRL_PIN(118, "GPIO_118"), + BCM63XX_FUNCTION(1, "PCIE2a_RST_B"), + BCM63XX_FUNCTION(2, "PCIE1b_RST_B"), + BCM63XX_FUNCTION(3, "PCIE0c_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_118") + ), + BCM63XX_PIN( + PINCTRL_PIN(119, "GPIO_119"), + BCM63XX_FUNCTION(1, "PCIE3_CLKREQ_B"), + BCM63XX_FUNCTION(5, "GPIO_119") + ), + BCM63XX_PIN( + PINCTRL_PIN(120, "GPIO_120"), + BCM63XX_FUNCTION(0, "PCIE3_RST_B"), + BCM63XX_FUNCTION(5, "GPIO_120") + ), + BCM63XX_PIN( + PINCTRL_PIN(121, "GPIO_121"), + BCM63XX_FUNCTION(1, "USB0a_PWRFLT"), + BCM63XX_FUNCTION(2, "USB1b_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_121") + ), + BCM63XX_PIN( + PINCTRL_PIN(122, "GPIO_122"), + BCM63XX_FUNCTION(1, "USB0a_PWRON"), + BCM63XX_FUNCTION(2, "USB1b_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_122") + ), + BCM63XX_PIN( + PINCTRL_PIN(123, "GPIO_123"), + BCM63XX_FUNCTION(1, "USB1a_PWRFLT"), + BCM63XX_FUNCTION(2, "USB0b_PWRFLT"), + BCM63XX_FUNCTION(5, "GPIO_123") + ), + BCM63XX_PIN( + PINCTRL_PIN(124, "GPIO_124"), + BCM63XX_FUNCTION(1, "USB1a_PWRON"), + BCM63XX_FUNCTION(2, "USB0b_PWRON"), + BCM63XX_FUNCTION(5, "GPIO_124") + ), + BCM63XX_PIN( + PINCTRL_PIN(125, "GPIO_125"), + BCM63XX_FUNCTION(0, "RESET_OUT_B"), + BCM63XX_FUNCTION(5, "GPIO_125") + ), +}; diff -Nruw linux-5.4.60-fbx/drivers/platform/fbxgw7r./Kconfig linux-5.4.60-fbx/drivers/platform/fbxgw7r/Kconfig --- linux-5.4.60-fbx/drivers/platform/fbxgw7r./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/platform/fbxgw7r/Kconfig 2021-03-04 13:20:59.600838970 +0100 @@ -0,0 +1,6 @@ +config FBXGW7R_PLATFORM + bool "Freebox Gateway V7 specific drivers" + +config FBXGW7R_SWITCH + bool "Freebox Gateway V7 in kernel switch init code." + depends on FBXGW7R_PLATFORM diff -Nruw linux-5.4.60-fbx/drivers/platform/fbxgw7r./Makefile linux-5.4.60-fbx/drivers/platform/fbxgw7r/Makefile --- linux-5.4.60-fbx/drivers/platform/fbxgw7r./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/platform/fbxgw7r/Makefile 2021-03-04 13:20:59.600838970 +0100 @@ -0,0 +1 @@ +obj-$(CONFIG_FBXGW7R_SWITCH) += fbxgw7r-switch.o diff -Nruw linux-5.4.60-fbx/drivers/platform/intelce./Kconfig linux-5.4.60-fbx/drivers/platform/intelce/Kconfig --- linux-5.4.60-fbx/drivers/platform/intelce./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/platform/intelce/Kconfig 2021-03-04 13:20:59.600838970 +0100 @@ -0,0 +1,18 @@ +# +# IntelCE devices configuration +# + +menu "IntelCE devices" + +config INTELCE_GPIO + tristate "GPIO support" + select ARCH_REQUIRE_GPIOLIB + ---help--- + IntelCE 3100/4100 GPIO support. + +config INTELCE_DFX + tristate "DFX reporting support" + ---help--- + IntelCE 3100/4100 DFX fuse reporting support. + +endmenu diff -Nruw linux-5.4.60-fbx/drivers/platform/intelce./Makefile linux-5.4.60-fbx/drivers/platform/intelce/Makefile --- linux-5.4.60-fbx/drivers/platform/intelce./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/platform/intelce/Makefile 2021-03-04 13:20:59.600838970 +0100 @@ -0,0 +1,2 @@ +obj-$(CONFIG_INTELCE_GPIO) += gpio-intelce.o +obj-$(CONFIG_INTELCE_DFX) += dfx.o diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./bpcm_defs.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/bpcm_defs.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./bpcm_defs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/bpcm_defs.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,76 @@ +#ifndef BPCM_DEFS_H_ +#define BPCM_DEFS_H_ + +/* + * BPCM (Block Power Control Module) registers definitions + */ +#define _F(value, shift, mask) (((value) & mask) << shift) +#define BPCM_SR_CONTROL_REG 0x28 + +#define BPCM_ZONE_REG(z) (0x40 + 0x10 * (z)) +#define BPCM_ZONE_MANUAL_CLK_EN (1 << 0) +#define BPCM_ZONE_MANUAL_RESET_CTL (1 << 1) +#define BPCM_ZONE_FREQ_SCALE_USED (1 << 2) +#define BPCM_ZONE_DPG_CAPABLE (1 << 3) +#define BPCM_ZONE_MANUAL_MEM_PWR(x) _F(x, 4, 0x3) +#define BPCM_ZONE_MANUAL_MEM_PWR_MASK _F(0x3, 4, 0x3) +#define BPCM_ZONE_MANUAL_ISO_CTL (1 << 6) +#define BPCM_ZONE_MANUAL_CTL (1 << 7) +#define BPCM_ZONE_DPG_CTL_EN (1 << 8) +#define BPCM_ZONE_PWR_DN_REQ (1 << 9) +#define BPCM_ZONE_PWR_UP_REQ (1 << 10) +#define BPCM_ZONE_MEM_PWR_CTL_EN (1 << 11) +#define BPCM_ZONE_BLK_RESET_ASSERT (1 << 12) +#define BPCM_ZONE_PWR_CNTL_STATE(x) _F(x, 19, 0x1f) +#define BPCM_ZONE_PWR_CNTL_STATE_MASK _F(0x1f, 19, 0x1f) +#define BPCM_ZONE_FREQ_SCALAR_DYN_SEL (1 << 24) +#define BPCM_ZONE_PWR_OFF_STATE (1 << 25) +#define BPCM_ZONE_PWR_ON_STATE (1 << 26) +#define BPCM_ZONE_PWR_GOOD (1 << 27) +#define BPCM_ZONE_DPG_PWR_STATE (1 << 28) +#define BPCM_ZONE_MEM_PWR_STATE (1 << 29) +#define BPCM_ZONE_ISO_STATE (1 << 30) +#define BPCM_ZONE_RESET_STATE (1 << 31) + +#define BPCM_ARM_CONTROL_REG 0x30 +#define BPCM_ARM_PWR_CONTROL_BASE_REG 0x34 +#define BPCM_ARM_PWR_CONTROL_REG(x) (BPCM_ARM_PWR_CONTROL_BASE_REG + (x) * 0x4) +#define BPCM_ARM_NEON_L2_REG 0x3c + + +/* ARM Control register definitions */ +#define CORE_PWR_CTRL_SHIFT 0 +#define CORE_PWR_CTRL_MASK 0x3 +#define PLL_PWR_ON BIT(8) +#define PLL_LDO_PWR_ON BIT(9) +#define PLL_CLAMP_ON BIT(10) +#define CPU_RESET_N(x) BIT(13 + (x)) +#define NEON_RESET_N BIT(15) +#define PWR_CTRL_STATUS_SHIFT 28 +#define PWR_CTRL_STATUS_MASK 0x3 +#define PWR_DOWN_SHIFT 30 +#define PWR_DOWN_MASK 0x3 + +/* CPU Power control register definitions */ +#define MEM_PWR_OK BIT(0) +#define MEM_PWR_ON BIT(1) +#define MEM_CLAMP_ON BIT(2) +#define MEM_PWR_OK_STATUS BIT(4) +#define MEM_PWR_ON_STATUS BIT(5) +#define MEM_PDA_SHIFT 8 +#define MEM_PDA_MASK 0xf +#define MEM_PDA_CPU_MASK 0x1 +#define MEM_PDA_NEON_MASK 0xf +#define CLAMP_ON BIT(15) +#define PWR_OK_SHIFT 16 +#define PWR_OK_MASK 0xf +#define PWR_ON_SHIFT 20 +#define PWR_CPU_MASK 0x03 +#define PWR_NEON_MASK 0x01 +#define PWR_ON_MASK 0xf +#define PWR_OK_STATUS_SHIFT 24 +#define PWR_OK_STATUS_MASK 0xf +#define PWR_ON_STATUS_SHIFT 28 +#define PWR_ON_STATUS_MASK 0xf + +#endif /* ! BPCM_DEFS_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./Kconfig linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/Kconfig --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./Kconfig 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/Kconfig 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,35 @@ +config SOC_BCM63XX + bool "Broadcom 63xx SoC drivers" + depends on ARCH_BCM_63XX || ARM64 || COMPILE_TEST + select RESET_CONTROLLER + help + Enables drivers for the Broadcom 63XX series of chips. + This option alone enables only some support code, while the drivers + can be enabled individually within this menu. + + If unsure, say N. + +config UBUS4_BCM63158 + bool "Broadcom 63158 UBUS4 driver" + depends on SOC_BCM63XX || COMPILE_TEST + +config PROCMON_BCM63158 + bool "Broadcom 63158 PROCMON driver" + depends on SOC_BCM63XX || COMPILE_TEST + +config SOC_BCM63XX_RDP + bool "rdp subsystem" + depends on SOC_BCM63XX || COMPILE_TEST + +config SOC_BCM63XX_XRDP + bool "xrdp subsystem" + depends on SOC_BCM63XX || COMPILE_TEST + select UBUS4_BCM63158 + +config SOC_BCM63XX_XRDP_IOCTL + bool "ioctl interface" + depends on SOC_BCM63XX_XRDP + +config SOC_MEMC_BCM63158 + tristate "Broadcom 63158 MEMC driver" + depends on SOC_BCM63XX || COMPILE_TEST diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./Makefile linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/Makefile --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/Makefile 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,6 @@ +obj-y += pmc.o +obj-$(CONFIG_SOC_BCM63XX_RDP) += rdp/ +obj-$(CONFIG_SOC_BCM63XX_XRDP) += xrdp/ +obj-$(CONFIG_UBUS4_BCM63158) += ubus4-bcm63158.o +obj-$(CONFIG_PROCMON_BCM63158) += procmon-bcm63158.o +obj-$(CONFIG_SOC_MEMC_BCM63158) += memc-bcm63158.o diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./memc-bcm63158.c linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/memc-bcm63158.c --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./memc-bcm63158.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/memc-bcm63158.c 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,305 @@ +/* + * memc-bcm63158.c for memc-bcm63158 + * Created by on Mon Apr 20 18:06:35 2020 + */ + +#include +#include +#include +#include +#include +#include + +#define MEMC_IDLE_PAD_CONTROL 0x20034 +#define MEMC_IDLE_PAD_EN0 0x20038 +#define MEMC_IDLE_PAD_EN1 0x2003c + +#define MEMC_CLK_MHZ 533 +#define MEMC_IDLE_THRESH_USEC 20 + +#define MEMC_AUTO_SR_REG 0x0025c +#define MEMC_AUTO_SR_EN (1 << 31) +#define MEMC_AUTO_SR_THRESH_MASK 0x7fffffff +#define MEMC_AUTO_SR_THRESH_VAL(v) ((v) & MEMC_AUTO_SR_THRESH_MASK) + +#define MEMC_GLOBAL_CONFIG_REG 0x00004 +#define MEMC_GLOBAL_CONFIG_SLOW_CLK_EN (1 << 26) + +struct bcm63158_memc_priv { + void __iomem *regs; + struct resource regs_res; + struct platform_device *pdev; + + u32 sr_idle_thresh; + bool auto_sr_en; + + struct mutex mutex; + + struct dentry *debugfs_dir; +}; + +static inline u32 memc_readl(struct bcm63158_memc_priv *priv, u32 off) +{ + u32 ret; + + ret = readl(priv->regs + off); + dev_dbg(&priv->pdev->dev, "memc_readl(): @%08llx: %08x", + priv->regs_res.start + off, ret); + return ret; +} + +static inline void memc_writel(u32 v, struct bcm63158_memc_priv *priv, u32 off) +{ + dev_dbg(&priv->pdev->dev, "memc_writel(): @%08llx: %08x", + priv->regs_res.start + off, v); + writel(v, priv->regs + off); +} + +/* + * same init as in the refsw. + */ +static void bcm63158_memc_idle_pad_init(struct bcm63158_memc_priv *priv) +{ + mutex_lock(&priv->mutex); + + memc_writel(0xe, priv, MEMC_IDLE_PAD_CONTROL); + memc_writel(0x6df, priv, MEMC_IDLE_PAD_EN0); + memc_writel(0x3fffff, priv, MEMC_IDLE_PAD_EN1); + + mutex_unlock(&priv->mutex); +} + +/* + * set idle time in usec after which the MEMC will go automatically in + * self-refresh mode. + */ +static int bcm63158_memc_auto_sr_thresh_set(struct bcm63158_memc_priv *priv, + u32 v) +{ + u32 reg; + + v *= MEMC_CLK_MHZ; + if ((v & MEMC_AUTO_SR_THRESH_MASK) != v) + return -EINVAL; + + mutex_lock(&priv->mutex); + + reg = memc_readl(priv, MEMC_AUTO_SR_REG); + reg &= ~MEMC_AUTO_SR_THRESH_MASK; + reg |= MEMC_AUTO_SR_THRESH_VAL(v); + memc_writel(reg, priv, MEMC_AUTO_SR_REG); + + mutex_unlock(&priv->mutex); + return 0; +} + +/* + * enable or disable automatic self refresh + */ +static void bcm63158_memc_auto_sr_enable(struct bcm63158_memc_priv *priv, + bool en) +{ + u32 reg; + + mutex_lock(&priv->mutex); + + reg = memc_readl(priv, MEMC_AUTO_SR_REG); + if (en) + reg |= MEMC_AUTO_SR_EN; + else + reg &= ~MEMC_AUTO_SR_EN; + memc_writel(reg, priv, MEMC_AUTO_SR_REG); + + mutex_unlock(&priv->mutex); +} + +/* + * same as refsw. + */ +static void bcm63158_memc_enable_slow_clock(struct bcm63158_memc_priv *priv) +{ + u32 reg; + + mutex_lock(&priv->mutex); + + reg = memc_readl(priv, MEMC_GLOBAL_CONFIG_REG); + reg |= MEMC_GLOBAL_CONFIG_SLOW_CLK_EN; + memc_writel(reg, priv, MEMC_GLOBAL_CONFIG_REG); + + mutex_unlock(&priv->mutex); +} + +/* + * auto-sr-en debugfs stuff + */ +static int bcm63158_memc_autosr_en_read(void *_priv, u64 *val) +{ + struct bcm63158_memc_priv *priv = _priv; + + *val = !!(memc_readl(priv, MEMC_AUTO_SR_REG) & MEMC_AUTO_SR_EN); + return 0; +} + +static int bcm63158_memc_autosr_en_write(void *_priv, u64 val) +{ + struct bcm63158_memc_priv *priv = _priv; + + bcm63158_memc_auto_sr_enable(priv, !!val); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(memc_autosr_en_fops, bcm63158_memc_autosr_en_read, + bcm63158_memc_autosr_en_write, "%llu\n"); + +/* + * auto-sr-thresh debugfs stuff + */ +static int bcm63158_memc_autosr_thresh_read(void *_priv, u64 *val) +{ + struct bcm63158_memc_priv *priv = _priv; + + *val = (memc_readl(priv, MEMC_AUTO_SR_REG) & MEMC_AUTO_SR_THRESH_MASK) + / MEMC_CLK_MHZ; + return 0; +} + +static int bcm63158_memc_autosr_thresh_write(void *_priv, u64 val) +{ + struct bcm63158_memc_priv *priv = _priv; + + return bcm63158_memc_auto_sr_thresh_set(priv, val); +} + + +DEFINE_SIMPLE_ATTRIBUTE(memc_autosr_thresh_fops, + bcm63158_memc_autosr_thresh_read, + bcm63158_memc_autosr_thresh_write, "%llu\n"); + +/* + * create debugfs entries, always report success, as debugfs support + * may not be compiled in. + */ +static int bcm63158_memc_create_debugfs(struct bcm63158_memc_priv *priv) +{ + priv->debugfs_dir = debugfs_create_dir("bcm63158-memc", NULL); + if (IS_ERR(priv->debugfs_dir)) { + dev_warn(&priv->pdev->dev, "unable to create debugfs " + "directory"); + priv->debugfs_dir = NULL; + return 0; + } + + debugfs_create_file("auto-sr-en", S_IWUSR | S_IRUSR, + priv->debugfs_dir, priv, + &memc_autosr_en_fops); + debugfs_create_file("auto-sr-thresh", S_IWUSR | S_IRUSR, + priv->debugfs_dir, priv, + &memc_autosr_thresh_fops); + + return 0; +} + +/* + * remove debugfs entries + */ +static int bcm63158_memc_remove_debugfs(struct bcm63158_memc_priv *priv) +{ + if (priv->debugfs_dir) + debugfs_remove_recursive(priv->debugfs_dir); + + return 0; +} + + +static int bcm63158_memc_probe(struct platform_device *pdev) +{ + struct resource *res; + struct bcm63158_memc_priv *priv; + + dev_dbg(&pdev->dev, "probe"); + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "unable to get resource for MEMC " + "registers."); + return -ENXIO; + } + priv->regs_res = *res; + + priv->regs = devm_ioremap_resource(&pdev->dev, &priv->regs_res); + if (IS_ERR(priv->regs)) { + dev_err(&pdev->dev, "unable to ioremap MEMC registers"); + return PTR_ERR(priv->regs); + } + + mutex_init(&priv->mutex); + priv->pdev = pdev; + + /* + * default values, possibly overridden with OF + */ + priv->sr_idle_thresh = MEMC_IDLE_THRESH_USEC; + priv->auto_sr_en = false; + + of_property_read_u32(pdev->dev.of_node, "brcm,auto-sr-thresh", + &priv->sr_idle_thresh); + priv->auto_sr_en = of_property_read_bool(pdev->dev.of_node, + "brcm,auto-sr-en"); + + dev_info(&pdev->dev, "auto-sr-thresh: %d", priv->sr_idle_thresh); + dev_info(&pdev->dev, "auto-sr-en: %d", priv->auto_sr_en); + + /* + * init + */ + bcm63158_memc_idle_pad_init(priv); + bcm63158_memc_enable_slow_clock(priv); + + /* + * set default values or OF values. + */ + bcm63158_memc_auto_sr_thresh_set(priv, priv->sr_idle_thresh); + bcm63158_memc_auto_sr_enable(priv, priv->auto_sr_en); + + /* + * create debugfs attributes + */ + bcm63158_memc_create_debugfs(priv); + dev_set_drvdata(&pdev->dev, priv); + + return 0; +} + +static int bcm63158_memc_remove(struct platform_device *pdev) +{ + struct bcm63158_memc_priv *priv = dev_get_drvdata(&pdev->dev); + + dev_dbg(&pdev->dev, "remove"); + bcm63158_memc_remove_debugfs(priv); + return 0; +} + +static const struct of_device_id bcm63158_memc_of_match[] = { + { .compatible = "brcm,bcm63158-memc" }, + {}, +}; + +static struct platform_driver bcm63158_memc_driver = { + .probe = bcm63158_memc_probe, + .remove = bcm63158_memc_remove, + .driver = { + .name = "bcm63158-memc", + .owner = THIS_MODULE, + .of_match_table = bcm63158_memc_of_match, + } +}; + +module_platform_driver(bcm63158_memc_driver); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63158 SoC MEMC driver."); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./pmc.c linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/pmc.c --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./pmc.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/pmc.c 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,2235 @@ +/* + * drivers/soc/bcm63xx/pmc.c + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#define pr_fmt(fmt) "bcm63xx-pmc: " fmt + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "bpcm_defs.h" + +#define VERBOSE_PMC + +/* + * PMC registers offsets + */ +#define PMC_CTRL_REG (0x1000) +#define PMC_HOST_MBOX_IN_REG (0x1028) +#define PMC_HOST_MBOX_OUT_REG (0x102c) +#define PMC_ADDR2_WIN_MASK_REG (0x1078) +#define PMC_ADDR2_WIN_BASEIN_REG (0x107c) +#define PMC_ADDR2_WIN_BASEOUT_REG (0x1080) +#define PMC_TIM2CTRL_REG (0x10b4) +#define PMC_TIM2CNT_REG (0x10b8) + +#define PMC_DQM_REQ_REG(__x) (0x1c00 + 4 * __x) +#define PMC_DQM_RPL_REG(__x) (0x1c10 + 4 * __x) +#define PMC_QSTATUS (0x1f00) +#define PMC_DQM_STS_REG (0x1820) +#define PMC_DQM_STS_NOTEMPTY (1 << 1) + +enum { + PMC_RSTATE_EXECUTING_BOOTROM, + PMC_RSTATE_WAITING_BMU_COMPLETE, + PMC_RSTATE_AVS_COMPLETE_WAITING_FOR_IMAGE, + PMC_RSTATE_AUTHENTICATING_IMAGE, + PMC_RSTATE_AUTHENTICATION_FAILED, + PMC_RSTATE_RESERVED, + PMC_RSTATE_FATAL_ERROR, + PMC_RSTATE_RUNNING +}; + +/* + * list of known PMB devices & their respective "addresses" + */ +#define PMB_BUS_ID_SHIFT 8 + +enum pmc_bus_id { + PMB_BUS_SF2, + PMB_BUS_SAR, + PMB_BUS_AIP, + PMB_BUS_AFEPLL, + PMB_BUS_RDP, + PMB_BUS_RDPPLL, + PMB_BUS_USB30_2X, +}; + +struct pmc_addr_info { + bool valid; + unsigned int dev; + unsigned int bus_id; +}; + +static const struct pmc_addr_info bcm63138_pmc_addr_info[PMB_ADDR_LAST] = { + [PMB_ADDR_SF2] = { true, 1, 1 }, + [PMB_ADDR_AIP] = { true, 4, 0 }, + [PMB_ADDR_SAR] = { true, 6, 1 }, + [PMB_ADDR_RDP] = { true, 7, 1 }, + [PMB_ADDR_RDPPLL] = { true, 11, 1 }, + [PMB_ADDR_USB30_2X] = { true, 17, 1 }, + [PMB_ADDR_VDSL3_MIPS] = { true, 21, 0 }, + [PMB_ADDR_VDSL3_CORE] = { true, 22, 0 }, + [PMB_ADDR_VDSL3_CORE] = { true, 22, 0 }, + [PMB_ADDR_AFEPLL] = { true, 23, 0 }, +}; + +static const struct pmc_addr_info bcm63158_pmc_addr_info[PMB_ADDR_LAST] = { + [PMB_ADDR_SYSTEMPORT] = { true, 0, 0 }, + [PMB_ADDR_SF2] = { true, 0, 1 }, + [PMB_ADDR_PCIE0] = { true, 8, 0 }, + [PMB_ADDR_PCIE1] = { true, 9, 0 }, + [PMB_ADDR_PCIE2] = { true, 10, 0 }, + [PMB_ADDR_PCIE3] = { true, 12, 1 }, + [PMB_ADDR_USB30_2X] = { true, 13, 1 }, + [PMB_ADDR_WAN] = { true, 15, 1 }, + [PMB_ADDR_XRDP] = { true, 16, 1 }, + [PMB_ADDR_XRDP_RC0] = { true, 17, 1 }, + [PMB_ADDR_XRDP_RC1] = { true, 18, 1 }, + [PMB_ADDR_XRDP_RC2] = { true, 19, 1 }, + [PMB_ADDR_XRDP_RC3] = { true, 20, 1 }, + [PMB_ADDR_XRDP_RC4] = { true, 21, 1 }, + [PMB_ADDR_XRDP_RC5] = { true, 22, 1 }, + [PMB_ADDR_VDSL3_CORE] = { true, 23, 0 }, + [PMB_ADDR_VDSL3_PMB] = { true, 24, 0 }, + [PMB_ADDR_AFEPLL] = { true, 26, 0 }, + [PMB_ADDR_BIU_PLL] = { true, 38, 0 }, +}; + +/* + * list of known PMC commands + */ +enum { + PMC_CMD_RESERVED = 0, + PMC_CMD_GET_DEV_PRESENCE, + PMC_CMD_GET_SW_STRAP, + PMC_CMD_GET_HW_REV, + PMC_CMD_GET_NUM_ZONES, + PMC_CMD_PING, + PMC_CMD_GET_NEXT_LOG_ENTRY, + PMC_CMD_GET_RMON_AND_SIGMA, + PMC_CMD_SET_CLOCK_HIGH_GEAR, + PMC_CMD_SET_CLOCK_LOW_GEAR, + PMC_CMD_SET_CLOCK_GEAR, + + PMC_CMD_READ_BPCM_REG, + PMC_CMD_READ_ZONE_REG, + PMC_CMD_WRITE_BPCM_REG, + PMC_CMD_WRITE_ZONE_REG, + PMC_CMD_SET_RUN_STATE, + PMC_CMD_SET_POWER_STATE, + PMC_CMD_SHUTDOWN_ALLOWED, + PMC_CMD_GET_SELECT0, + PMC_CMD_GET_SELECT3, + PMC_CMD_GET_AVS_DISABLE_STATE, + + PMC_CMD_GET_PVT, + PMC_CMD_POWER_DEV_ONOFF, + PMC_CMD_POWER_ZONE_ONOFF, + PMC_CMD_RESET_DEVICE, + PMC_CMD_RESET_ZONE, + PMC_CMD_ALLOCATE_G2UDQM, + PMC_CMD_QSM_AVAILABLE, + PMC_CMD_REVISION, + PMC_CMD_REGISTER_CMD_HANDLER, + PMC_CMD_FIND_UNUSED_COMMAND, + + PMC_CMD_LOCK_CMD_TABLE, + PMC_CMD_JUMPAPP, + PMC_CMD_STALL, + PMC_CMD_CLOSEAVS, +}; + +struct pmc_command { + struct { + union { + struct { + u32 cmd_id: 8; + u32 error: 8; + u32 msgid: 8; + u32 srcport: 8; + }; + u32 all; + }; + } word0; + + struct { + union { + struct { + u32 zone_idx: 10; + u32 dev_addr: 10; + u32 island: 4; + u32 log_num: 8; + }; + u32 all; + }; + } word1; + + union { + + struct { + u32 params[2]; + } generic_params; + + struct { + u32 word2; + u32 word3; + } command_response; + + struct { + u8 reserved[2]; + u8 restore; + u8 state; + + u32 unused; + } command_power; + + struct { + u16 margin_mv_slow; + u16 max_mv; + u16 margin_mv_fast; + u16 min_mv; + } close_avs_63158; + }; +}; + +struct bcm63xx_pmc { + struct device *dev; + u32 soc_id; + void __iomem *base; + unsigned int req_sequnum; + struct mutex pmc_lock; + struct reset_controller_dev rcdev; + + bool init_done; + struct dentry *debugfs_dir; + + u16 avs_margin_ff; + u16 avs_margin_ss; +}; + +#define to_pmc_reset_priv(p) \ + container_of((p), struct bcm63xx_pmc, rcdev) + +static struct bcm63xx_pmc *pmc = &(struct bcm63xx_pmc) {}; + +/* + * + */ +static int __pmc_send_command(struct bcm63xx_pmc *priv, + struct pmc_command *cmd, + struct pmc_command *rsp) +{ + u32 tries = 50000; + + priv->req_sequnum = (priv->req_sequnum + 1) & 0xff; + cmd->word0.msgid = priv->req_sequnum; + + /* + * write request command to PMC registers. + */ + writel(cmd->word0.all, priv->base + PMC_DQM_REQ_REG(0)); + writel(cmd->word1.all, priv->base + PMC_DQM_REQ_REG(1)); + writel(cmd->generic_params.params[0], priv->base + PMC_DQM_REQ_REG(2)); + writel(cmd->generic_params.params[1], priv->base + PMC_DQM_REQ_REG(3)); + + /* + * wait for PMC to reply. + */ + while (tries) { + u32 sts; + + udelay(10); + sts = readl(priv->base + PMC_DQM_STS_REG); + if ((sts & PMC_DQM_STS_NOTEMPTY)) + goto finished; + --tries; + } + + /* timeout */ + dev_err(priv->dev, "PMC command %d (seq %d)failed.\n", + cmd->word0.cmd_id, priv->req_sequnum); + return -ETIMEDOUT; + +finished: + memset(rsp, 0, sizeof (*rsp)); + rsp->word0.all = readl(priv->base + PMC_DQM_RPL_REG(0)); + rsp->word1.all = readl(priv->base + PMC_DQM_RPL_REG(1)); + rsp->generic_params.params[0] = readl(priv->base + PMC_DQM_RPL_REG(2)); + rsp->generic_params.params[1] = readl(priv->base + PMC_DQM_RPL_REG(3)); + + if (rsp->word0.msgid == priv->req_sequnum) { + /* + * PMC replied to correct command, look into error of + * the reply. + */ + if (rsp->word0.error) { + dev_info(priv->dev, "PMC reported error: %d\n", + rsp->word0.error); + return -EIO; + } + } else { + /* + * PMC is drunk ? + */ + dev_err(priv->dev, "PMC reported completion cmd seq %d " + "(PMC drunk?)\n", rsp->word0.msgid); + return -EILSEQ; + } + + return 0; +} + +/* + * + */ +static int pmc_send_command(struct bcm63xx_pmc *priv, struct pmc_command *cmd, + struct pmc_command *rsp) +{ + int ret; + + mutex_lock(&priv->pmc_lock); + ret = __pmc_send_command(priv, cmd, rsp); + mutex_unlock(&priv->pmc_lock); + return ret; +} + +/* + * + */ +static u32 pmc_get_dev_addr(struct bcm63xx_pmc *priv, enum pmc_addr_id addr_id) +{ + const struct pmc_addr_info *info; + + switch (priv->soc_id) { + case 0x63138: + info = bcm63138_pmc_addr_info; + break; + case 0x63158: + info = bcm63158_pmc_addr_info; + break; + default: + WARN(1, "missing addr info for this soc id"); + return 0; + } + + BUG_ON(!info[addr_id].valid); + return info[addr_id].dev | (info[addr_id].bus_id << PMB_BUS_ID_SHIFT); +} + +/* + * + */ +static int pmc_power_on_cmd(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_POWER_DEV_ONOFF; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + cmd.command_power.state = 1; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + return 0; +} + +/* + * + */ +static int pmc_power_off_cmd(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_POWER_DEV_ONOFF; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + cmd.command_power.state = 0; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + return 0; +} + +/* + * + */ +int pmc_read_bpcm_register(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, + u32 word_offset, u32 *value) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_READ_BPCM_REG; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + + cmd.generic_params.params[0] = word_offset >> 2; + cmd.generic_params.params[1] = 0; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *value = rsp.command_response.word2; + + return 0; +} +EXPORT_SYMBOL_GPL(pmc_read_bpcm_register); + +/* + * + */ +int pmc_get_avs_state(struct bcm63xx_pmc *priv, int island, bool *state) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_GET_AVS_DISABLE_STATE; + cmd.word1.island = island; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *state = !rsp.command_response.word2; + return 0; +} + +/* + * + */ +static int pmc_close_avs(struct bcm63xx_pmc *pmc) +{ + struct pmc_command cmd, rsp; + int error; + + /* + * PMC_CMD_CLOSEAVS command format is different on non 63158 + * SoCs. + */ + if (pmc->soc_id != 0x63158) + return -ENXIO; + + pr_info("PMC: close AVS with %u mv (SS silicon) and " + "%u mv (FF silicon)\n", pmc->avs_margin_ss, + pmc->avs_margin_ff); + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_CLOSEAVS; + + /* + * NOTE: keep min_mv and max_mv to 0 to let the firmware use + * the default values for minimum and maximum AVS tension. + */ + cmd.close_avs_63158.margin_mv_fast = pmc->avs_margin_ff; + cmd.close_avs_63158.margin_mv_slow = pmc->avs_margin_ss; + + error = pmc_send_command(pmc, &cmd, &rsp); + if (error) { + pr_err("PMC close AVS failed: %d\n", error); + return error; + } + + return 0; +} + +/* + * + */ +int pmc_get_rmon(struct bcm63xx_pmc *priv, u32 *v) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_GET_RMON_AND_SIGMA; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *v = rsp.command_response.word3; + return 0; +} + +/* + * + */ +int pmc_write_bpcm_register(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, + u32 word_offset, u32 value) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_WRITE_BPCM_REG; + cmd.word1.dev_addr = pmc_get_dev_addr(priv, addr_id); + cmd.word1.zone_idx = 0; + cmd.generic_params.params[0] = word_offset >> 2; + cmd.generic_params.params[1] = value; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + return 0; +} +EXPORT_SYMBOL_GPL(pmc_write_bpcm_register); + +/* Perform a value write, then spin until the value shifted by shift + * is seen, masked with mask and is different from cond. + */ +static int pmc_wr_rd_bpcm_mask(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, + u32 word_offset, u32 *val, + u32 shift, u32 mask, u32 cond) +{ + int ret; + int limit = 1000; + u32 dev_addr = pmc_get_dev_addr(priv, addr_id); + + ret = pmc_write_bpcm_register(priv, dev_addr, + word_offset, *val); + if (ret) + return ret; + + do { + ret = pmc_read_bpcm_register(priv, dev_addr, + word_offset, val); + if (ret) + return ret; + + udelay(10); + + if (--limit < 0) { + ret = -ETIMEDOUT; + break; + } + + } while (((*val >> shift) & mask) != cond); + + return ret; +} + +/* + * control cpu reset/power + */ +static int pmc_cpu_power_on(struct bcm63xx_pmc *priv, unsigned int cpu) +{ + u32 ctrl, val; + int ret; + + /* Check if the CPU is already on and save the ARM_CONTROL register + * value since we will use it later for CPU de-assert once done with + * the CPU-specific power sequence + */ + ret = pmc_read_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, &ctrl); + if (ret) + goto out; + + if (ctrl & CPU_RESET_N(cpu)) { + pr_info("CPU%d is already powered on, reset it\n", cpu); + + ctrl &= ~CPU_RESET_N(cpu); + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, ctrl); + mdelay(1); + ctrl |= CPU_RESET_N(cpu); + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, ctrl); + ret = 0; + goto out; + } + + /* Power on CPU */ + ret = pmc_read_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), &val); + if (ret) + goto out; + + val |= (PWR_CPU_MASK << PWR_ON_SHIFT); + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), &val, + PWR_ON_STATUS_SHIFT, + PWR_CPU_MASK, PWR_CPU_MASK); + if (ret) + goto out; + + val |= (PWR_CPU_MASK << PWR_OK_SHIFT); + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), &val, + PWR_OK_STATUS_SHIFT, + PWR_CPU_MASK, PWR_CPU_MASK); + if (ret) + goto out; + + val &= ~CLAMP_ON; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), val); + if (ret) + goto out; + + /* Power on CPU RAM */ + val &= ~(MEM_PDA_MASK << MEM_PDA_SHIFT); + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), val); + if (ret) + goto out; + + val |= MEM_PWR_ON; + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), + &val, + 0, MEM_PWR_ON_STATUS, MEM_PWR_ON_STATUS); + if (ret) + goto out; + + val |= MEM_PWR_OK; + + ret = pmc_wr_rd_bpcm_mask(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), + &val, + 0, MEM_PWR_OK_STATUS, MEM_PWR_OK_STATUS); + if (ret) + goto out; + + val &= ~MEM_CLAMP_ON; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_PWR_CONTROL_REG(cpu), val); + if (ret) + goto out; + + /* De-assert CPU reset */ + ctrl |= CPU_RESET_N(cpu); + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_AIP, + BPCM_ARM_CONTROL_REG, ctrl); + +out: + return ret; +} + +#if 0 +static int pmc_power_off_zone(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id, int zone) +{ + u32 zone_reg; + int err; + + err = pmc_read_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + &zone_reg); + if (err) + return err; + + zone_reg &= ~BPCM_ZONE_PWR_UP_REQ; + zone_reg |= BPCM_ZONE_PWR_DN_REQ; + + err = pmc_write_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + zone_reg); + if (err) + return err; + + return 0; +} +#endif + +static int pmc_power_on_zone(struct bcm63xx_pmc *priv, enum pmc_addr_id addr_id, + int zone) +{ + u32 zone_reg; + int err; + + err = pmc_read_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + &zone_reg); + if (err) + return err; + + zone_reg &= ~BPCM_ZONE_PWR_DN_REQ; + zone_reg |= BPCM_ZONE_PWR_UP_REQ; + zone_reg |= BPCM_ZONE_DPG_CTL_EN; + zone_reg |= BPCM_ZONE_MEM_PWR_CTL_EN; + zone_reg |= BPCM_ZONE_BLK_RESET_ASSERT; + + err = pmc_write_bpcm_register(priv, addr_id, BPCM_ZONE_REG(zone), + zone_reg); + if (err) + return err; + + return 0; +} + +/* + * control StarFighter2 (switch) power + */ +static int pmc_sf2_power_on(struct bcm63xx_pmc *priv) +{ + /* FIXME: SF2 GMII CLOCK HERE ? */ + return pmc_power_on_cmd(priv, PMB_ADDR_SF2); +} + +static int pmc_sf2_power_off(struct bcm63xx_pmc *priv) +{ + return pmc_power_off_cmd(priv, PMB_ADDR_SF2); +} + +/* + * control SAR power + */ +# define PMB_SAR_SR_CONTROL 0x28 +# define PMB_SAR_SR_CONTROL_RESET 0xffffff01 +# define PMB_SAR_SR_CONTROL_UNRESET 0xffffff00 + +static int pmc_sar_soft_reset(struct bcm63xx_pmc *priv) +{ + int ret; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_SAR, + PMB_SAR_SR_CONTROL, + PMB_SAR_SR_CONTROL_RESET); + if (ret) + return ret; + + ret = pmc_write_bpcm_register(priv, PMB_ADDR_SAR, + PMB_SAR_SR_CONTROL, + PMB_SAR_SR_CONTROL_UNRESET); + if (ret) + return ret; + + return 0; +} + +static int pmc_sar_power_on(struct bcm63xx_pmc *priv) +{ + int ret; + + ret = pmc_power_on_cmd(priv, PMB_ADDR_SAR); + if (ret) + return ret; + + return pmc_sar_soft_reset(priv); +} + +static int pmc_sar_power_off(struct bcm63xx_pmc *priv) +{ + return pmc_power_off_cmd(priv, PMB_ADDR_SAR); +} + +/* + * control USB host power + */ +static int pmc_usbh_power_on(struct bcm63xx_pmc *priv) +{ + return pmc_power_on_cmd(priv, PMB_ADDR_USB30_2X); +} + +static int pmc_usbh_power_off(struct bcm63xx_pmc *priv) +{ + return pmc_power_off_cmd(priv, PMB_ADDR_USB30_2X); +} + +/* + * control Runner Data Path power + */ +# define RDP_PLL_RESETS 0x10 +# define RDP_PLL_RESET_BIT0 (1 << 0) +# define RDP_PLL_RESET_BIT1 (1 << 1) + +# define RDP_PLL_NDIV 0x1c +# define NDIV_INT_MASK 0x3ff + +# define RDP_PLL_PDIV 0x20 +# define PDIV_MASK 0x7 + +# define RDP_PLL_CH01_CFG 0x2c +# define CH01_MDIV0_MASK 0xff + +# define RDP_PLL_STATUS 0x3c +# define RDP_PLL_STATUS_READY (1 << 31) + +# define PMB_RDP_SR_CONTROL 0x28 +# define PMB_RDP_SR_CONTROL_UNRESET 0xffffffff +# define PMB_RDP_SR_CONTROL_RESET 0x0 + +static int pmc_rdp_pll_init(struct bcm63xx_pmc *priv) +{ + unsigned int tries = 100; + int ret; + u32 reg; + + /* + * powerdown PLLs. + */ + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, 0x0); + if (ret) + return ret; + + /* + * release first stage reset. + */ + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, ®); + if (ret) + return ret; + + reg |= RDP_PLL_RESET_BIT0; + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, reg); + if (ret) + return ret; + + /* + * wait for PLL ready bit. + */ + do { + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_STATUS, + ®); + if (ret) + return ret; + } while (--tries && !(reg & RDP_PLL_STATUS_READY)); + + if (!tries) { + dev_err(priv->dev, "timedout waiting for RDP PLL ready.\n"); + return -ETIMEDOUT; + } + + /* + * release second stage reset. + */ + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, ®); + if (ret) + return ret; + + reg |= RDP_PLL_RESET_BIT1; + + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_RDPPLL, + RDP_PLL_RESETS, reg); + if (ret) + return ret; + + return 0; +} + +static int pmc_rdp_power_on(struct bcm63xx_pmc *priv) +{ + int ret; + + ret = pmc_rdp_pll_init(priv); + if (ret) + return ret; + + /* + * hold RDP into reset + */ + ret = pmc_write_bpcm_register(priv, PMB_ADDR_RDP, + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_RESET); + if (ret) + return ret; + + ret = pmc_power_off_cmd(priv, PMB_ADDR_RDP); + if (ret) + return ret; + + ret = pmc_power_on_cmd(priv, PMB_ADDR_RDP); + if (ret) + return ret; + + /* + * hold RDP into reset + */ + ret = pmc_write_bpcm_register(priv, PMB_ADDR_RDP, + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_UNRESET); + if (ret) + return ret; + + return 0; +} + +static int pmc_rdp_power_off(struct bcm63xx_pmc *priv) +{ + return 0; +} + +/* + * XRDP power control + */ +static const enum pmc_addr_id xrdp_blocks[] = { + PMB_ADDR_XRDP, + PMB_ADDR_XRDP_RC0, + PMB_ADDR_XRDP_RC1, + PMB_ADDR_XRDP_RC2, + PMB_ADDR_XRDP_RC3, + PMB_ADDR_XRDP_RC4, + PMB_ADDR_XRDP_RC5, +}; + +static int pmc_xrdp_power_on(struct bcm63xx_pmc *priv) +{ + size_t i; + int ret; + + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_power_off_cmd(priv, xrdp_blocks[i]); + if (ret) + return ret; + } + + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_power_on_cmd(priv, xrdp_blocks[i]); + if (ret) + return ret; + } + + /* + * hold & release reset + */ + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_write_bpcm_register(priv, xrdp_blocks[i], + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_RESET); + if (ret) + return ret; + } + + for (i = 0; i < ARRAY_SIZE(xrdp_blocks); i++) { + ret = pmc_write_bpcm_register(priv, xrdp_blocks[i], + PMB_RDP_SR_CONTROL, + PMB_RDP_SR_CONTROL_UNRESET); + if (ret) + return ret; + } + + return 0; +} + +static int pmc_xrdp_power_off(struct bcm63xx_pmc *priv) +{ + return 0; +} + +/* + * power on single lane PCI express port. + */ +static int pmc_pcieX_power_on(struct bcm63xx_pmc *priv, + enum pmc_addr_id addr_id) +{ + int err; + + dev_dbg(priv->dev, "pcie power on address id %d.\n", addr_id); + + err = pmc_power_on_zone(priv, addr_id, 0); + if (err) + return err; + + err = pmc_write_bpcm_register(priv, addr_id, + BPCM_SR_CONTROL_REG, 0x0); + if (err) + return err; + + return 0; +} + +/* + * power on dual lane PCI express port, lanes 0-1 + */ +static int pmc_pcie01_power_on(struct bcm63xx_pmc *priv) +{ + int err; + + dev_dbg(priv->dev, "pcie01 power on.\n"); + + /* + * power on first lane + */ + err = pmc_power_on_zone(priv, PMB_ADDR_PCIE0, 0); + if (err) + return err; + + /* + * power on second lane + */ + err = pmc_power_on_zone(priv, PMB_ADDR_PCIE1, 0); + if (err) + return err; + + /* + * write all 0s in second lane SR control. + */ + err = pmc_write_bpcm_register(priv, PMB_ADDR_PCIE1, + BPCM_SR_CONTROL_REG, 0x0); + if (err) + return err; + + /* + * write 0xff to reset SR control + */ + err = pmc_write_bpcm_register(priv, PMB_ADDR_PCIE0, + BPCM_SR_CONTROL_REG, 0xff); + if (err) + return err; + mdelay(10); + + /* + * bit7: 1 - Strap override for dual lane support + * bit6: Strap value, 0 - dual lane, 1 - single lane + */ + err = pmc_write_bpcm_register(priv, PMB_ADDR_PCIE0, + BPCM_SR_CONTROL_REG, 0x80); + if (err) + return err; + + return 0; +} + +static int pmc_pcieX_power_off(struct bcm63xx_pmc *priv, enum pmc_addr_id osef) +{ + dev_info(priv->dev, "pcie0 power off.\n"); + return -ENOTSUPP; +} +static int pmc_pcie01_power_off(struct bcm63xx_pmc *priv) +{ + dev_info(priv->dev, "pcie01 power off.\n"); + return -ENOTSUPP; +} + +static inline enum pmc_addr_id reset_to_pmc_addr_id(unsigned long reset) +{ + switch (reset) { + case PMC_R_PCIE0: + return PMB_ADDR_PCIE0; + case PMC_R_PCIE1: + return PMB_ADDR_PCIE1; + case PMC_R_PCIE2: + return PMB_ADDR_PCIE2; + case PMC_R_PCIE3: + return PMB_ADDR_PCIE3; + default: + BUG(); + } +} + +/* + * WAN_AE reset + */ +#define PMB_WAN_AE_SR_CONTROL 0x28 +# define PMB_WAN_AE_SR_CTRL_RX_RCLK16_SW_RESET_MASK (1 << 12) +# define PMB_WAN_AE_SR_CTRL_RX_RBC125_SW_RESET_MASK (1 << 13) +# define PMB_WAN_AE_SR_CTRL_RX_TCLK16_SW_RESET_MASK (1 << 14) +# define PMB_WAN_AE_SR_CTRL_RX_CLK125_SW_RESET_MASK (1 << 15) + +static int pmc_wan_ae_soft_reset(struct bcm63xx_pmc *priv) +{ + u32 val; + int ret; + + ret = pmc_read_bpcm_register(priv, + PMB_ADDR_WAN, + BPCM_SR_CONTROL_REG, &val); + if (ret) + return ret; + + val |= PMB_WAN_AE_SR_CTRL_RX_RCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_RBC125_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_TCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_CLK125_SW_RESET_MASK; + + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_WAN, + BPCM_SR_CONTROL_REG, + val); + if (ret) + return ret; + + udelay(5); + + val &= ~(PMB_WAN_AE_SR_CTRL_RX_RCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_RBC125_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_TCLK16_SW_RESET_MASK | + PMB_WAN_AE_SR_CTRL_RX_CLK125_SW_RESET_MASK); + + ret = pmc_write_bpcm_register(priv, + PMB_ADDR_WAN, + BPCM_SR_CONTROL_REG, + val); + if (ret) + return ret; + + return 0; +} + +/* + * reset controller ops + */ +static int pmc_reset_op_action(struct bcm63xx_pmc *priv, + unsigned long idx, + unsigned int action) +{ + switch (idx) { + case PMC_R_CPU1: + if (action == 0) + return pmc_cpu_power_on(priv, 1); + break; + + case PMC_R_RDP: + switch (action) { + case 0: + return pmc_rdp_power_on(priv); + case 1: + return pmc_rdp_power_off(priv); + default: + break; + } + break; + + case PMC_R_XRDP: + switch (action) { + case 0: + return pmc_xrdp_power_on(priv); + case 1: + return pmc_xrdp_power_off(priv); + default: + break; + } + break; + + case PMC_R_SF2: + switch (action) { + case 0: + return pmc_sf2_power_on(priv); + case 1: + return pmc_sf2_power_off(priv); + default: + break; + } + break; + + case PMC_R_SAR: + switch (action) { + case 0: + return pmc_sar_power_on(priv); + case 1: + return pmc_sar_power_off(priv); + case 2: + return pmc_sar_soft_reset(priv); + default: + break; + } + break; + + case PMC_R_USBH: + switch (action) { + case 0: + return pmc_usbh_power_on(priv); + case 1: + return pmc_usbh_power_off(priv); + default: + break; + } + break; + + case PMC_R_PCIE0: + case PMC_R_PCIE1: + case PMC_R_PCIE2: + case PMC_R_PCIE3: + switch (action) { + case 0: + return pmc_pcieX_power_on(priv, + reset_to_pmc_addr_id(idx)); + case 1: + return pmc_pcieX_power_off(priv, + reset_to_pmc_addr_id(idx)); + } + break; + + case PMC_R_PCIE01: + switch (action) { + case 0: + return pmc_pcie01_power_on(priv); + case 1: + return pmc_pcie01_power_off(priv); + } + break; + + case PMC_R_WAN_AE: + switch (action) { + case 2: + return pmc_wan_ae_soft_reset(priv); + default: + break; + } + break; + + default: + dev_err(priv->dev, "unknown reset idx %lu", idx); + return -ENODEV; + } + + dev_err(priv->dev, "unhandled action %u for id %lu", action, idx); + return -ENOTSUPP; +} + +static int pmc_assert_op_callback(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + return pmc_reset_op_action(to_pmc_reset_priv(rcdev), idx, 1); +} + +static int pmc_deassert_op_callback(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + return pmc_reset_op_action(to_pmc_reset_priv(rcdev), idx, 0); +} + +static int pmc_reset_op_callback(struct reset_controller_dev *rcdev, + unsigned long idx) +{ + return pmc_reset_op_action(to_pmc_reset_priv(rcdev), idx, 2); +} + +static const struct reset_control_ops pmc_reset_controller_ops = { + .assert = pmc_assert_op_callback, + .deassert = pmc_deassert_op_callback, + .reset = pmc_reset_op_callback, +}; + +/* + * hwmon info + */ +static int pmc_get_pvt(struct bcm63xx_pmc *priv, + unsigned int island, + unsigned int sel, + unsigned int *value) +{ + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_GET_PVT; + cmd.word1.dev_addr = 0; + cmd.word1.zone_idx = 0; + cmd.word1.island = island; + cmd.generic_params.params[0] = sel; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + *value = rsp.command_response.word2; + return 0; +} + +static ssize_t pmc_revision_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int revision, change; + struct pmc_command cmd, rsp; + int error; + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_REVISION; + + error = pmc_send_command(priv, &cmd, &rsp); + if (error) + return error; + + change = rsp.command_response.word2; + revision = rsp.command_response.word3; + + return snprintf(buf, PAGE_SIZE, "%x-%d\n", revision, change); +} + +static SENSOR_DEVICE_ATTR(revision, 0444, pmc_revision_show, NULL, 0); + +static ssize_t pmc_thermal_show_temp(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int value, temp; + int error; + + error = pmc_get_pvt(priv, 0, 0, &value); + if (error) + return error; + + temp = (41004000 - 48705 * value) / 100; + return snprintf(buf, PAGE_SIZE, "%u\n", temp); +} + +static SENSOR_DEVICE_ATTR(temp1_input, 0444, pmc_thermal_show_temp, + NULL, 0); + +static ssize_t pmc_thermal_show_in(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int value, in, reg, island; + int sel = to_sensor_dev_attr(attr)->index; + int divider; + int error; + + island = (sel >> 8) & 0xff; + reg = sel & 0xff; + + error = pmc_get_pvt(priv, island, reg, &value); + if (error) + return error; + + switch (reg) { + case 1: + case 2: + divider = 10; + break; + case 3: + case 4: + divider = 7; + break; + case 5: + divider = 4; + break; + case 6: + divider = 2; + break; + default: + divider = 1; + break; + } + + in = (8800 * value) / (divider * 1024); + return snprintf(buf, PAGE_SIZE, "%u\n", in); +} + +/* V0.85_0 */ +static SENSOR_DEVICE_ATTR(in1_input, 0444, pmc_thermal_show_in, NULL, 0x0001); + +/* V0.85_1 */ +static SENSOR_DEVICE_ATTR(in2_input, 0444, pmc_thermal_show_in, NULL, 0x0002); + +/* Vin */ +static SENSOR_DEVICE_ATTR(in3_input, 0444, pmc_thermal_show_in, NULL, 0x0003); + +/* V1.0 */ +static SENSOR_DEVICE_ATTR(in4_input, 0444, pmc_thermal_show_in, NULL, 0x0004); + +/* V1.8 */ +static SENSOR_DEVICE_ATTR(in5_input, 0444, pmc_thermal_show_in, NULL, 0x0005); + +/* V3.3 */ +static SENSOR_DEVICE_ATTR(in6_input, 0444, pmc_thermal_show_in, NULL, 0x0006); + +/* Vin */ +static SENSOR_DEVICE_ATTR(in9_input, 0444, pmc_thermal_show_in, NULL, 0x0103); + +/* + * AFE PLL + */ +static ssize_t pmc_show_afepll(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct bcm63xx_pmc *priv = dev_get_drvdata(dev); + unsigned int offset = to_sensor_dev_attr(attr)->index; + int ret; + u32 val; + + ret = pmc_read_bpcm_register(priv, PMB_ADDR_AFEPLL, offset, &val); + if (ret) + return ret; + + return snprintf(buf, PAGE_SIZE, "0x%x\n", val); +} + +/* vdsl pll */ +static SENSOR_DEVICE_ATTR(afepll_rosc_control_input, + 0444, pmc_show_afepll, NULL, 0x10); + +static SENSOR_DEVICE_ATTR(afepll_rosc_count_input, + 0444, pmc_show_afepll, NULL, 0x1c); + +static SENSOR_DEVICE_ATTR(afepll_sr_control_input, + 0444, pmc_show_afepll, NULL, 0x28); + +static struct attribute *pmc_hwmon_attrs[] = { + &sensor_dev_attr_revision.dev_attr.attr, + + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_in1_input.dev_attr.attr, + &sensor_dev_attr_in2_input.dev_attr.attr, + &sensor_dev_attr_in3_input.dev_attr.attr, + &sensor_dev_attr_in4_input.dev_attr.attr, + &sensor_dev_attr_in5_input.dev_attr.attr, + &sensor_dev_attr_in6_input.dev_attr.attr, + &sensor_dev_attr_in9_input.dev_attr.attr, + + &sensor_dev_attr_afepll_rosc_control_input.dev_attr.attr, + &sensor_dev_attr_afepll_rosc_count_input.dev_attr.attr, + &sensor_dev_attr_afepll_sr_control_input.dev_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(pmc_hwmon); + + +/* + * called by SMP ops early in the boot process + */ +int bcm63xx_pmc_cpu_power_on(unsigned int cpu) +{ + /* make sure early init has been called */ + if (WARN_ON(!pmc->base)) + return -ENODEV; + + if (WARN_ON(cpu > 1)) + return -ENODEV; + + return pmc_cpu_power_on(pmc, cpu); +} + +/* + * load PMC firmware overlay if needed + * + * called with PMC lock held + */ +static int __pmc_init(struct bcm63xx_pmc *pmc) +{ + return 0; +} + +static int bcm63xx_pmc_probe(struct platform_device *pdev) +{ + struct reset_controller_dev *rcdev; + struct resource *res; + struct device *hwmon_dev; + void __iomem *base; + int ret; + + /* + * Early initialisation should have configured an initial + * register mapping and setup the soc data pointer. If these + * are not valid then something went badly wrong! + */ + if (WARN_ON(!pmc->base)) + return -ENODEV; + + /* take over the memory region from the early initialization */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pmc->dev = &pdev->dev; + + /* switch to newly reserved base address & init PMC */ + mutex_lock(&pmc->pmc_lock); + iounmap(pmc->base); + pmc->base = base; + + ret = __pmc_init(pmc); + if (ret) { + iounmap(pmc->base); + pmc->base = NULL; + mutex_unlock(&pmc->pmc_lock); + return ret; + } + mutex_unlock(&pmc->pmc_lock); + + /* register as reset controller */ + rcdev = &pmc->rcdev; + rcdev->ops = &pmc_reset_controller_ops; + rcdev->of_node = pdev->dev.of_node; + rcdev->of_reset_n_cells = 1; + rcdev->nr_resets = PMC_R_LAST; + + ret = devm_reset_controller_register(&pdev->dev, rcdev); + if (ret) { + pr_err("failed to register reset controller: %d", ret); + return ret; + } + + /* register as hwmon */ + if (IS_ENABLED(CONFIG_HWMON)) { + hwmon_dev = + devm_hwmon_device_register_with_groups(&pdev->dev, "pmc", + pmc, + pmc_hwmon_groups); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + } + + pmc->init_done = true; + return 0; +} + +static const struct of_device_id bcm63xx_pmc_match[] = { + { .compatible = "brcm,bcm63138-pmc", .data = (void *)0x63138 }, + { .compatible = "brcm,bcm63158-pmc", .data = (void *)0x63158 }, + { } +}; + +static struct platform_driver bcm63xx_pmc_driver = { + .driver = { + .name = "bcm63xx-pmc", + .suppress_bind_attrs = true, + .of_match_table = bcm63xx_pmc_match, + }, + .probe = bcm63xx_pmc_probe, +}; + +builtin_platform_driver(bcm63xx_pmc_driver); + +/* + * fetch PMC firmware revision and check that it matches SOC id + */ +static int pmc_check_revision(struct bcm63xx_pmc *priv) +{ + struct pmc_command cmd, rsp; + int ret; + + memset(&cmd, 0, sizeof (cmd)); + + cmd.word0.cmd_id = PMC_CMD_REVISION; + cmd.word1.dev_addr = 0; + + ret = pmc_send_command(priv, &cmd, &rsp); + if (ret) { + pr_err("failed to retrieve PMC revision\n"); + return ret; + } + + if (rsp.command_response.word2 != priv->soc_id) { + pr_err("PMC revision mismatch (0x%08x != 0x%08x)\n", + rsp.command_response.word2, priv->soc_id); + return -ENODEV; + } + + pr_debug("PMC firmware revision: 0x%08x", rsp.command_response.word3); + return 0; +} + +/* + * additionnal code to load into PMC + */ +#define PMC_IMAGE_ALIGN (1 << 13) + +static const __attribute__((aligned(PMC_IMAGE_ALIGN))) u8 pmc_63138_image[] = { + 0x27, 0xbd, 0xff, 0x10, 0x8f, 0x82, 0x06, 0x00, 0xaf, 0xb1, 0x00, 0xcc, + 0xaf, 0xb0, 0x00, 0xc8, 0x00, 0xa0, 0x88, 0x21, 0xaf, 0xbf, 0x00, 0xec, + 0xaf, 0xbe, 0x00, 0xe8, 0xaf, 0xb7, 0x00, 0xe4, 0xaf, 0xb6, 0x00, 0xe0, + 0xaf, 0xb5, 0x00, 0xdc, 0xaf, 0xb4, 0x00, 0xd8, 0xaf, 0xb3, 0x00, 0xd4, + 0xaf, 0xb2, 0x00, 0xd0, 0x00, 0x80, 0x80, 0x21, 0x00, 0x40, 0xf8, 0x09, + 0x00, 0xa0, 0x20, 0x21, 0x8e, 0x22, 0x00, 0x08, 0xaf, 0x82, 0x01, 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writel(image_link_addr & 0x1fffffff, + pmc->base + PMC_ADDR2_WIN_BASEIN_REG); + writel(virt_to_phys(image_virt_addr), + pmc->base + PMC_ADDR2_WIN_BASEOUT_REG); + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = PMC_CMD_REGISTER_CMD_HANDLER; + cmd.generic_params.params[0] = 96; + cmd.generic_params.params[1] = image_link_addr; + + ret = pmc_send_command(pmc, &cmd, &rsp); + if (ret) { + pr_err("failed to register command handler\n"); + return ret; + } + + memset(&cmd, 0, sizeof (cmd)); + cmd.word0.cmd_id = 96; + cmd.generic_params.params[0] = 75; + cmd.generic_params.params[1] = 75; + + ret = pmc_send_command(pmc, &cmd, &rsp); + if (ret) { + pr_err("failed to send cmd 96\n"); + return ret; + } + + return 0; +} + +static const char *pmc_run_state_str[] = { + [PMC_RSTATE_EXECUTING_BOOTROM] = "EXECUTING_BOOTROM", + [PMC_RSTATE_WAITING_BMU_COMPLETE] = "WAITING_BMU_COMPLETE", + [PMC_RSTATE_AVS_COMPLETE_WAITING_FOR_IMAGE] = + "AVS_COMPLETE_WAITING_FOR_IMAGE", + [PMC_RSTATE_AUTHENTICATING_IMAGE] = "AUTHENTICATING_IMAGE", + [PMC_RSTATE_AUTHENTICATION_FAILED] = "AUTHENTICATION_FAILED", + [PMC_RSTATE_RESERVED] = "RESERVED", + [PMC_RSTATE_FATAL_ERROR] = "FATAL_ERROR", + [PMC_RSTATE_RUNNING] = "RUNNING", +}; + +static int __init pmc_load_plugin(struct bcm63xx_pmc *pmc) +{ + u32 val; + + val = readl(pmc->base + PMC_HOST_MBOX_IN_REG); + val = (val >> 24) & 0x7; + pr_info("PMC state is '%s'\n", pmc_run_state_str[val]); + + switch (pmc->soc_id) { + case 0x63138: + return pmc_load_plugin_bcm63138(pmc, val); + case 0x63158: + return 0; + default: + WARN(1, "no load plugin defined"); + return 0; + } +} + +static int pmc_avs_state_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + int error; + bool state; + + error = pmc_get_avs_state(pmc, 0, &state); + if (error) + return error; + + *val = state ? 1 : 0; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_avs_state_fops, + pmc_avs_state_read, + NULL, "%llu\n"); + +static int pmc_pred_voltage_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + int error; + u32 v; + + error = pmc_get_rmon(pmc, &v); + if (error) + return error; + + *val = (v >> 16) & 0xffff; + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_pred_voltage_fops, + pmc_pred_voltage_read, + NULL, "%lld\n"); + +static int pmc_avs_margin_ss_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + + *val = pmc->avs_margin_ss; + return 0; +} + +static int pmc_avs_margin_ss_write(void *priv, u64 val) +{ + struct bcm63xx_pmc *pmc = priv; + + if (val > 0xff) + return -EINVAL; + + pmc->avs_margin_ss = val; + + if (pmc->avs_margin_ff && pmc->avs_margin_ss) + return pmc_close_avs(pmc); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_avs_margin_ss_fops, + pmc_avs_margin_ss_read, + pmc_avs_margin_ss_write, + "%lld\n"); + +static int pmc_avs_margin_ff_read(void *priv, u64 *val) +{ + struct bcm63xx_pmc *pmc = priv; + + *val = pmc->avs_margin_ff; + return 0; +} + +static int pmc_avs_margin_ff_write(void *priv, u64 val) +{ + struct bcm63xx_pmc *pmc = priv; + + if (val > 0xff) + return -EINVAL; + + pmc->avs_margin_ff = val; + + if (pmc->avs_margin_ff && pmc->avs_margin_ss) + return pmc_close_avs(pmc); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(pmc_avs_margin_ff_fops, + pmc_avs_margin_ff_read, + pmc_avs_margin_ff_write, + "%lld\n"); + +static int __init pmc_create_debugfs(struct bcm63xx_pmc *pmc) +{ + pmc->debugfs_dir = debugfs_create_dir("bcm63xx-pmc", NULL); + if (IS_ERR(pmc->debugfs_dir)) { + dev_warn(pmc->dev, "unable to create debugfs directory"); + pmc->debugfs_dir = NULL; + return 0; + } + + debugfs_create_file("avs-state", S_IRUSR, pmc->debugfs_dir, + pmc, &pmc_avs_state_fops); + debugfs_create_file("avs-pred-voltage", S_IRUSR, pmc->debugfs_dir, + pmc, &pmc_pred_voltage_fops); + debugfs_create_file("avs-margin-ss", S_IRUSR | S_IWUSR, + pmc->debugfs_dir, pmc, &pmc_avs_margin_ss_fops); + debugfs_create_file("avs-margin-ff", S_IRUSR | S_IWUSR, + pmc->debugfs_dir, pmc, &pmc_avs_margin_ff_fops); + return 0; +} + +/* + * Early initialization to allow access to registers in the very early boot + * process (mostly for SMP bootup) + */ +static int __init bcm63xx_pmc_early_init(void) +{ + const struct of_device_id *match; + struct device_node *np; + struct resource regs; + int ret; + bool avs_state; + + np = of_find_matching_node_and_match(NULL, bcm63xx_pmc_match, &match); + if (!np) { + pr_warn("DT node not found, PMC disabled\n"); + return 0; + } + + if (of_address_to_resource(np, 0, ®s) < 0) { + pr_err("failed to get PMC registers\n"); + of_node_put(np); + return -ENXIO; + } + + of_node_put(np); + + mutex_init(&pmc->pmc_lock); + pmc->soc_id = (u32)(uintptr_t)match->data; + pmc->base = ioremap_nocache(regs.start, resource_size(®s)); + if (!pmc->base) { + pr_err("failed to map PMC registers\n"); + return -ENXIO; + } + + pmc_load_plugin(pmc); + ret = pmc_check_revision(pmc); + if (ret) + goto fail; + + ret = pmc_get_avs_state(pmc, 0, &avs_state); + if (ret) + pr_err("PMC: unable to get AVS state.\n"); + else + pr_info("PMC: AVS state is %sabled\n", + avs_state ? "en" : "dis"); + + pmc_create_debugfs(pmc); + + return 0; + +fail: + pr_err("PMC init failed"); + iounmap(pmc->base); + pmc->base = NULL; + return ret; +} + +early_initcall(bcm63xx_pmc_early_init); + + +/* + * special wrappers for bcm_adsl + */ +static enum pmc_addr_id pmc_find_dev_addr_id(struct bcm63xx_pmc *priv, + unsigned int dev_addr) +{ + const struct pmc_addr_info *info; + size_t i; + + switch (priv->soc_id) { + case 0x63138: + info = bcm63138_pmc_addr_info; + break; + case 0x63158: + info = bcm63158_pmc_addr_info; + break; + default: + WARN(1, "missing addr info for this soc id"); + return 0; + } + + for (i = 0; i < PMB_ADDR_LAST; i++) { + unsigned int addr; + + if (!info[i].valid) + continue; + + addr = (info[i].dev | (info[i].bus_id << PMB_BUS_ID_SHIFT)); + if (addr == dev_addr) + return i; + } + + printk("cannot find dev addr id for dev_addr:0x%x\n", dev_addr); + BUG(); +} + +int PowerOnDevice(int devAddr) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + return pmc_power_on_cmd(pmc, id); +} +EXPORT_SYMBOL(PowerOnDevice); + +int PowerOffDevice(int devAddr) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + return pmc_power_off_cmd(pmc, id); +} +EXPORT_SYMBOL(PowerOffDevice); + +int ReadBPCMRegister(int devAddr, int wordOffset, u32 *value) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + int ret; + + ret = pmc_read_bpcm_register(pmc, id, wordOffset << 2, value); + return ret; +} + +EXPORT_SYMBOL(ReadBPCMRegister); + +int WriteBPCMRegister(int devAddr, int wordOffset, u32 value) +{ + enum pmc_addr_id id = pmc_find_dev_addr_id(pmc, devAddr); + return pmc_write_bpcm_register(pmc, id, wordOffset << 2, value); +} + +EXPORT_SYMBOL(WriteBPCMRegister); + +struct bcm63xx_pmc *pmc_of_get(struct device_node *np) +{ + return pmc->init_done ? pmc : ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL_GPL(pmc_of_get); diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./procmon-bcm63158.c linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/procmon-bcm63158.c --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./procmon-bcm63158.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/procmon-bcm63158.c 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,171 @@ +/* + * procmon-bcm63158.c for procmon-bcm63158 + * Created by on Thu Oct 3 19:14:44 2019 + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +struct bcm63158_procmon_priv { + void __iomem *regs; + struct device *dev; + struct list_head list; +}; + + +static DEFINE_MUTEX(procmon_list_mutex); +static LIST_HEAD(procmon_list); + +static int bcm63158_procmon_probe(struct platform_device *pdev) +{ + struct bcm63158_procmon_priv *priv; + + dev_info(&pdev->dev, "probe.\n"); + + priv = devm_kzalloc(&pdev->dev, sizeof (*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + priv->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, priv); + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (!priv->regs) + return -ENOMEM; + + mutex_lock(&procmon_list_mutex); + list_add_tail(&priv->list, &procmon_list); + mutex_unlock(&procmon_list_mutex); + + return 0; +} + +static const struct of_device_id bcm63158_procmon_match[] = { + { .compatible = "brcm,bcm63158-procmon" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63158_procmon_of_match); + +struct platform_driver bcm63158_procmon_driver = { + .probe = bcm63158_procmon_probe, + .remove = NULL, /* FIXME*/ + .driver = { + .name = "bcm63158-procmon", + .owner = THIS_MODULE, + .of_match_table = bcm63158_procmon_match, + }, +}; +builtin_platform_driver(bcm63158_procmon_driver); + +#define PROCMON_MISC_REG(i) (0x50 + (i) * 4) + +#define PROCMON_EXT_REG (0x50 + 0xc) +# define EXT_REG_RMON_SATURATED_VALUE 0x3a0 +# define EXT_REG_RMON_VALUE_MASK 0xffff +# define EXT_REG_RMON_VALID (1 << 16) + +/* + * this is the meaty part of this driver. calculation method comes + * directly from broadcom refsw. + */ +int bcm63158_procmon_calc_rcal(struct bcm63158_procmon_priv *priv, + int resistor) +{ + u32 res_int, res_ext; + u32 ext_reg; + int ratio, ratio1, ret; + + dev_dbg(priv->dev, "getting rcal setting for resistor %d", resistor); + + /* + * make sure the resistor selection is valid + */ + if (resistor < RCAL_0P25UM_HORZ || resistor > RCAL_1UM_VERT) + return -EINVAL; + + ext_reg = readl(priv->regs + PROCMON_EXT_REG); + if ((ext_reg & EXT_REG_RMON_VALID) == 0) { + dev_err(priv->dev, "resistor data is not collected by the " + "PMC.\n"); + return -EIO; + } + + if ((ext_reg & EXT_REG_RMON_VALUE_MASK) > + EXT_REG_RMON_SATURATED_VALUE) { + dev_err(priv->dev, "ext reg is saturated.\n"); + return -EIO; + } + + res_ext = ext_reg & EXT_REG_RMON_VALUE_MASK; + res_int = readl(priv->regs + PROCMON_MISC_REG(resistor >> 1)); + if (resistor & 1) + res_int >>= 16; + + /* + * Ratio = CLAMP((INT) (128.0 * V(REXT)/V(RINT)), 0, 255) + */ + ratio = (128 * res_ext) / res_int; + if (ratio > 255) + ratio = 255; + + /* + * Ratio1 = CLAMP(128 - (Ratio - 128) * 4, 0, 255) + */ + ratio1 = 128 - (ratio - 128) * 4; + if (ratio1 < 0) + ratio1 = 0; + if (ratio1 > 255) + ratio1 = 255; + + /* + * convert to 4 bit rcal setting value + */ + ret = (ratio1 >> 4) & 0xf; + + dev_dbg(priv->dev, "getrcal for resistor%d, int %d, ext %d, " + "ratio %d ratio1 %d, rcal %d\n", + resistor, res_int, res_ext, ratio, ratio1, ret); + + return ret; +} + +int procmon_get_rcal(struct device_node *np) +{ + int err; + struct of_phandle_args args; + struct bcm63158_procmon_priv *priv; + + err = of_parse_phandle_with_args(np, "procmon", "#procmon-cells", + 0, &args); + if (err) { + printk("unable to parse procmon phandle.\n"); + return err; + } + + if (args.args_count != 1) + return -EINVAL; + + mutex_lock(&procmon_list_mutex); + list_for_each_entry (priv, &procmon_list, list) { + if (priv->dev->of_node == args.np) { + mutex_unlock(&procmon_list_mutex); + goto found; + } + } + mutex_unlock(&procmon_list_mutex); + return -EPROBE_DEFER; + +found: + return bcm63158_procmon_calc_rcal(priv, args.args[0]); +} +EXPORT_SYMBOL(procmon_get_rcal); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63158 SoC PROCMON driver."); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./rdp/Makefile linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/rdp/Makefile --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./rdp/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/rdp/Makefile 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,9 @@ +obj-y += rdp_drv.o + +rdp_drv-y += \ + rdp.o \ + rdp_api.o \ + rdp_io.o \ + rdp_ioctl.o + +rdp_drv-$(CONFIG_DEBUG_FS) += rdp_debug.o diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./ubus4-bcm63158.c linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/ubus4-bcm63158.c --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./ubus4-bcm63158.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/ubus4-bcm63158.c 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,875 @@ +/* + * ubus4-bcm63158.c for bcm63158-soc + * Created by on Fri Jun 7 14:30:40 2019 + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * UBUS coherency port configuration registes. + */ +#define UBUS_COHERENCY_LUT(x) (0x00 + 4 * (x)) +#define UBUS_COHERENCY_QUEUE_DEPTH(x) (0x80 + 4 * (x)) +#define UBUS_COHERENCY_CBS_THRESH(x) (0x90 + 4 * (x)) +#define UBUS_COHERENCY_CIR_INCR(x) (0xb0 + 4 * (x)) +#define UBUS_COHERENCY_REF_CNT(x) (0xc0 + 4 * (x)) +#define UBUS_COHERENCY_MAX_BONUS(x) (0xd0 + 4 * (x)) + +static inline void get_lut_queue_id_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 8; + *shift = (id % 8) * 4; + *mask = 0xf; +} + +static inline void get_queue_depth_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 4; + *shift = (id % 4) * 8; + *mask = 0xff; +} + +static inline void get_cbs_thresh_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 2; + *shift = (id % 2) * 16; + *mask = 0xffff; +} + +static inline void get_cir_incr_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 4; + *shift = (id % 4) * 8; + *mask = 0xff; +} + +static inline void get_ref_cnt_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 4; + *shift = (id % 4) * 8; + *mask = 0xff; +} + +static inline void get_max_bonus_params(int id, u32 *offset, u32 *shift, + u32 *mask) +{ + *offset = id / 8; + *shift = (id % 8) * 4; + *mask = 0x7; +} + +#define UBUS_LUT_COUNT 32 +#define UBUS_QUEUE_DEPTH_COUNT 4 +#define UBUS_CBS_THRESH_COUNT 8 +#define UBUS_CIR_INCR_COUNT 4 +#define UBUS_REF_CNT_COUNT 4 +#define UBUS_MAX_BONUS_COUNT 2 + + +#define UBUS_COHERENCY_WLU_SCRPID(x) (0xd8 + 4 * (x)) +/* + * ubus masters bas addresses + */ +#define UBUS_PORT_PCIE0_OFFSET 0x00C000 +#define UBUS_PORT_DSLCPU_OFFSET 0x01C000 +#define UBUS_PORT_B53_OFFSET 0x020000 +#define UBUS_PORT_PMC_OFFSET 0x02C000 +#define UBUS_PORT_PER_OFFSET 0x034000 +#define UBUS_PORT_PER_DMA_OFFSET 0x03C000 +#define UBUS_PORT_SWH_OFFSET 0x048000 +#define UBUS_PORT_SPU_OFFSET 0x050000 +#define UBUS_PORT_DSL_OFFSET 0x05C000 +#define UBUS_PORT_PCIE2_OFFSET 0x064000 +#define UBUS_PORT_PCIE3_OFFSET 0x06C000 +#define UBUS_PORT_USB_OFFSET 0x074000 +#define UBUS_PORT_DMA0_OFFSET 0x47C000 +#define UBUS_PORT_DMA1_OFFSET 0x480000 +#define UBUS_PORT_RQ0_OFFSET 0x498000 +#define UBUS_PORT_NATC_OFFSET 0x4B8000 +#define UBUS_PORT_DQM_OFFSET 0x4BC000 +#define UBUS_PORT_QM_OFFSET 0x4C4000 + + +static DEFINE_MUTEX(ubus_list_mutex); +static LIST_HEAD(ubus_list); + +struct ubus_credit { + u32 port_id; + u32 credit; +}; + +struct ubus_master_desc { + unsigned long regs_offset; + u32 port_id; + struct ubus_credit *credits; +}; + +#define UBUS_MASTER_DESC(_reg_offset, _port_id, ...) \ + { \ + .regs_offset = _reg_offset, \ + .port_id = _port_id, \ + .credits = (struct ubus_credit[]){ \ + __VA_ARGS__, { } }, \ + } + +#define UBUS_CREDIT(_port_id, _credit) \ + { .port_id = _port_id, .credit = _credit } + +/* + * locations of each masters control registers, and SoC specific + * credits tables. + */ +struct ubus_master_desc bcm63158_masters[] = { + UBUS_MASTER_DESC(UBUS_PORT_B53_OFFSET, UBUS_PORT_ID_BIU, + UBUS_CREDIT(UBUS_PORT_ID_MEMC, 3), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PER_OFFSET, UBUS_PORT_ID_PER, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1)), + UBUS_MASTER_DESC(UBUS_PORT_USB_OFFSET, UBUS_PORT_ID_USB, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 2), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1)), + UBUS_MASTER_DESC(UBUS_PORT_SPU_OFFSET, UBUS_PORT_ID_SPU, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 5), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 4), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8)), + UBUS_MASTER_DESC(UBUS_PORT_DSL_OFFSET, UBUS_PORT_ID_DSL, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PER_DMA_OFFSET, UBUS_PORT_ID_PERDMA, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 5), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 4), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8)), + UBUS_MASTER_DESC(UBUS_PORT_PCIE0_OFFSET, UBUS_PORT_ID_PCIE0, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 4), + UBUS_CREDIT(UBUS_PORT_ID_PCIE0, 1), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PCIE2_OFFSET, UBUS_PORT_ID_PCIE2, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 3), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PCIE3_OFFSET, UBUS_PORT_ID_PCIE3, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 6), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1)), + UBUS_MASTER_DESC(UBUS_PORT_DSLCPU_OFFSET, UBUS_PORT_ID_DSLCPU, + UBUS_CREDIT(UBUS_PORT_ID_MEMC, 8), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 1)), + UBUS_MASTER_DESC(UBUS_PORT_PMC_OFFSET, UBUS_PORT_ID_PMC, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_MEMC, 1), + UBUS_CREDIT(UBUS_PORT_ID_USB, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE0, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE3, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE2, 1), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_PMC, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_SWH, 1), + UBUS_CREDIT(UBUS_PORT_ID_SPU, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 1), + UBUS_CREDIT(UBUS_PORT_ID_QM, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 1), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 1), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 1), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_SWH_OFFSET, UBUS_PORT_ID_SWH, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 8), + UBUS_CREDIT(UBUS_PORT_ID_SYS, 1), + UBUS_CREDIT(UBUS_PORT_ID_DSL, 8), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 8)), + UBUS_MASTER_DESC(UBUS_PORT_QM_OFFSET, UBUS_PORT_ID_QM, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 16), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_DQM_OFFSET, UBUS_PORT_ID_DQM, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 1), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 2), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_DMA0_OFFSET, UBUS_PORT_ID_DMA0, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 8), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_NATC_OFFSET, UBUS_PORT_ID_NATC, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 2), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), + UBUS_MASTER_DESC(UBUS_PORT_RQ0_OFFSET, UBUS_PORT_ID_RQ0, + UBUS_CREDIT(UBUS_PORT_ID_BIU, 11), + UBUS_CREDIT(UBUS_PORT_ID_USB, 1), + UBUS_CREDIT(UBUS_PORT_ID_PCIE0, 2), + UBUS_CREDIT(UBUS_PORT_ID_PCIE3, 2), + UBUS_CREDIT(UBUS_PORT_ID_PCIE2, 2), + UBUS_CREDIT(UBUS_PORT_ID_PER, 1), + UBUS_CREDIT(UBUS_PORT_ID_WAN, 1), + UBUS_CREDIT(UBUS_PORT_ID_SWH, 1), + UBUS_CREDIT(UBUS_PORT_ID_SPU, 1), + UBUS_CREDIT(UBUS_PORT_ID_QM, 10), + UBUS_CREDIT(UBUS_PORT_ID_FPM, 2), + UBUS_CREDIT(UBUS_PORT_ID_VPB, 2), + UBUS_CREDIT(UBUS_PORT_ID_PSRAM, 10), + UBUS_CREDIT(UBUS_PORT_ID_SYSXRDP, 1)), +}; + +struct biu_config { + const char *blk_name; + u32 mstr_node; + u32 src_pid; + u32 queue_id; + u32 depth; + u32 ref_cnt[4]; + u32 cir; + u32 cbs; + u32 bonus; + +}; + +enum { + E_DDR_2133_x32, + E_DDR_2133_x16, + E_DDR_1600_x32, + E_DDR_1600_x16, +}; + +#define DDR_SPEED_800_10_10_10 6 +#define DDR_SPEED_800_11_11_11 7 + +#define DDR_SPEED(mcb) ((mcb) & 0x1f) +#define DDR_DEV_WIDTH(mcb) (((mcb) >> 5) & 0x7) + +#define DDR_WIDTH_x16 0 +#define DDR_WIDTH_x32 1 +#define DDR_WIDTH_x8 2 + + +static u32 get_ddr_refcnt_index(u32 mcb) +{ + u32 speed = DDR_SPEED(mcb); + u32 width = DDR_DEV_WIDTH(mcb); + + if (speed == DDR_SPEED_800_11_11_11 || + speed == DDR_SPEED_800_10_10_10) { + switch (width) { + case DDR_WIDTH_x16: + return E_DDR_1600_x16; + case DDR_WIDTH_x32: + return E_DDR_1600_x32; + default: + BUG(); + } + } else { + switch (width) { + case DDR_WIDTH_x16: + return E_DDR_2133_x16; + case DDR_WIDTH_x32: + return E_DDR_2133_x32; + default: + BUG(); + } + } + BUG(); + return 0xaa55aa55; +} + +static struct biu_config biu_config_bcm63158[32 + 1] = { + /* queue depth will be set based on ubus credits */ + [UBUS_PORT_ID_PER] = { + .blk_name = "PCM", + .src_pid = 3, + .queue_id = 7, + .cir = 2, + .cbs = 128, + .bonus = 0, + .ref_cnt = {12, 18, 22, 40 }, + .mstr_node = UBUS_PORT_ID_PER + }, + [UBUS_PORT_ID_USB] = { + .blk_name = "USB", + .src_pid = 4, + .queue_id = 6, + .cir = 3, + .cbs = 128, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_USB + }, + [UBUS_PORT_ID_SPU] = { + .blk_name = "SPU", + .src_pid = 5, + .queue_id = 9, + .cir = 1, + .cbs = 1, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_SPU + }, + [UBUS_PORT_ID_PERDMA] = { + .blk_name = "M2M", + .src_pid = 7, + .queue_id = 8, + .cir = 1, + .cbs = 1, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PERDMA + }, + [UBUS_PORT_ID_PCIE0] = { + .blk_name = "PCIe0", + .src_pid = 8, + .queue_id = 3, + .cir = 6, + .cbs = 128, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PCIE0 + }, + [UBUS_PORT_ID_PCIE2] = { + .blk_name = "PCIe2", + .src_pid = 9, + .queue_id = 4, + .cir = 3, + .cbs = 128, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PCIE2 + }, + [UBUS_PORT_ID_PCIE3] = { + .blk_name = "PCIe3", + .src_pid = 10, + .queue_id = 5, + .cir = 9, + .cbs = 256, + .bonus = 0, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_PCIE3 + }, + [UBUS_PORT_ID_QM] = { + .blk_name = "QM", + .src_pid = 22, + .queue_id = 10, + .cir = 38, + .cbs = 512, + .bonus = 4, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_QM + }, + [UBUS_PORT_ID_DQM] = { + .blk_name = "QM_DQM", + .src_pid = 23, + .queue_id = 1, + .cir = 5, + .cbs = 256, + .bonus = 4, + .ref_cnt = {6, 9, 11, 20 }, + .mstr_node = UBUS_PORT_ID_DQM + }, + [UBUS_PORT_ID_DMA0] = { + .blk_name = "DMA0", + .src_pid = 24, + .queue_id = 11, + .cir = 39, + .cbs = 128, + .bonus = 4, + .ref_cnt = {38, 71, 90, 161}, + .mstr_node = UBUS_PORT_ID_DMA0 + }, + [UBUS_PORT_ID_NATC] = { + .blk_name = "NAT$", + .src_pid = 26, + .queue_id = 2, + .cir = 6, + .cbs = 512, + .bonus = 4, + .ref_cnt = {21, 36, 45, 81 }, + .mstr_node = UBUS_PORT_ID_NATC + }, + [UBUS_PORT_ID_RQ0] = { + .blk_name = "RNR", + .src_pid = 32, + .queue_id = 0, + .cir = 14, + .cbs = 256, + .bonus = 4, + .ref_cnt = {12, 18, 22, 40 }, + .mstr_node = UBUS_PORT_ID_RQ0 + }, +}; + +#define UBUS_MASTER_TOKEN_REG(port) (0x400 + (port) * 4) + +#define UBUS_CONG_THRESHOLD_REG (0xc) + +#define UBUS_MASTER_DECODE_CONTROL (0x600) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_MASK (0x3 << 4) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_DEF (0x0 << 4) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_INPUT (0x1 << 4) +#define UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_CFG_REG (0x2 << 4) + +#define UBUS_MASTER_DECODE_CACHE_CONFIG (0x604) + + +struct ubus4_bcm63158 { + struct device *dev; + struct list_head list; + + struct resource regs; + struct ubus4_master *masters; + size_t nr_masters; + + unsigned long coherency_control_regs_phys; + void __iomem *coherency_control_regs; + u32 ddr_mcb; +}; + +struct ubus4_master { + struct ubus4_bcm63158 *ubus; + unsigned long regs_phys; + void __iomem *regs; + u32 port_id; + + const struct ubus_credit *credits; + size_t nr_credits; +}; + +static inline u32 ubus_master_readl(struct ubus4_master *m, u32 off) +{ + u32 ret; + + ret = readl(m->regs + off); + dev_dbg(m->ubus->dev, "read %08x at %08lx\n", ret, m->regs_phys + off); + return ret; +} + +static inline void ubus_master_writel(u32 val, struct ubus4_master *m, u32 off) +{ + dev_dbg(m->ubus->dev, "write %08x at %08lx\n", val, + m->regs_phys + off); + writel(val, m->regs + off); +} + +static inline void ubus_cohcfg_writel(u32 val, struct ubus4_bcm63158 *ubus, + u32 off) +{ + dev_dbg(ubus->dev, "coherency config write %08x at %08lx\n", + val, ubus->coherency_control_regs_phys + off); + writel(val, ubus->coherency_control_regs + off); +} + +static inline u32 ubus_cohcfg_readl(struct ubus4_bcm63158 *ubus, u32 off) +{ + u32 ret; + ret = readl(ubus->coherency_control_regs + off); + dev_dbg(ubus->dev, "coherency config read %08x at %08lx\n", + ret, ubus->coherency_control_regs_phys + off); + return ret; +} + +struct ubus4_master *ubus_get_master(struct ubus4_bcm63158 *ubus, + u32 port_id) +{ + size_t i; + for (i = 0; i < ubus->nr_masters; ++i) + if (ubus->masters[i].port_id == port_id) + return &ubus->masters[i]; + return NULL; +} + +void ubus_master_apply_credits(struct ubus4_master *m) +{ + size_t i; + + for (i = 0; i < m->nr_credits; ++i) { + const struct ubus_credit *c = &m->credits[i]; + + ubus_master_writel(c->credit, m, + UBUS_MASTER_TOKEN_REG(c->port_id)); + } +} +EXPORT_SYMBOL(ubus_master_apply_credits); + +void ubus_master_set_congestion_threshold(struct ubus4_master *m, u32 v) +{ + ubus_master_writel(v, m, UBUS_CONG_THRESHOLD_REG); +} +EXPORT_SYMBOL(ubus_master_set_congestion_threshold); + +void ubus_master_remap_port(struct ubus4_master *m) +{ + u32 v; + + ubus_master_writel(0x1, m, UBUS_MASTER_DECODE_CACHE_CONFIG); + + /* + * on bcm63158, only master cache control configuration is + * needed. + */ + v = ubus_master_readl(m, UBUS_MASTER_DECODE_CONTROL); + v &= ~UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_MASK; + v |= UBUS_MASTER_DECODE_CONTROL_CONFIG_SEL_CFG_REG; + ubus_master_writel(v, m, UBUS_MASTER_DECODE_CONTROL); +} +EXPORT_SYMBOL(ubus_master_remap_port); + +static int ubus_setup_master(struct ubus4_bcm63158 *ubus, + struct ubus4_master *the, + struct ubus_master_desc *desc) +{ + struct resource res; + + the->port_id = desc->port_id; + the->credits = desc->credits; + the->nr_credits = 0; + while (the->credits[the->nr_credits].port_id && + the->credits[the->nr_credits].credit) + ++the->nr_credits; + + dev_dbg(ubus->dev, "master %d, credits %zu\n", + the->port_id, the->nr_credits); + + res.start = ubus->regs.start + desc->regs_offset; + res.end = res.start + 0x1000 - 1; + res.name = "ubus master register"; + res.flags = ubus->regs.flags; + res.desc = ubus->regs.desc; + res.parent = NULL; + + if (!resource_contains(&ubus->regs, &res)) { + dev_err(ubus->dev, "registers for master %d are outside main " + "register space.", the->port_id); + return -EINVAL; + } + + the->ubus = ubus; + the->regs_phys = res.start; + the->regs = devm_ioremap_resource(ubus->dev, &res); + if (!the->regs) + return -ENOMEM; + + dev_dbg(ubus->dev, "master%d registers %pR\n", the->port_id, &res); + return 0; +} + +static void ubus_enable_all_wlu_srcpid(struct ubus4_bcm63158 *ubus) +{ + int i; + + for (i = 0; i < 8; ++i) { + ubus_cohcfg_readl(ubus, UBUS_COHERENCY_WLU_SCRPID(i)); + ubus_cohcfg_writel(0xffffffff, ubus, + UBUS_COHERENCY_WLU_SCRPID(i)); + } +} + + +static void ubus_reset_biu_cfg(struct ubus4_bcm63158 *ubus) +{ + int i; + + for (i = 0; i < UBUS_LUT_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_LUT(i)); + for (i = 0; i < UBUS_QUEUE_DEPTH_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_QUEUE_DEPTH(i)); + for (i = 0; i < UBUS_CBS_THRESH_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_CBS_THRESH(i)); + for (i = 0; i < UBUS_CIR_INCR_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_CIR_INCR(i)); + for (i = 0; i < UBUS_REF_CNT_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_REF_CNT(i)); + for (i = 0; i < UBUS_MAX_BONUS_COUNT; ++i) + ubus_cohcfg_writel(0x0, ubus, UBUS_COHERENCY_MAX_BONUS(i)); +} + +static void ubus_configure_biu(struct ubus4_bcm63158 *ubus, + struct biu_config *biu_cfg) +{ + u32 offset, shift, mask; + u32 reg; + u32 ddr_refcount = get_ddr_refcnt_index(ubus->ddr_mcb); + + dev_dbg(ubus->dev, "configuring BIU for %s\n", biu_cfg->blk_name); + + /* + * assign queue ID + */ + get_lut_queue_id_params(biu_cfg->src_pid, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_LUT(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->queue_id << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_LUT(offset)); + + /* + * assign queue depth + */ + get_queue_depth_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_QUEUE_DEPTH(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->depth << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_QUEUE_DEPTH(offset)); + + /* + * assign CBS threshold. + */ + get_cbs_thresh_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_CBS_THRESH(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->cbs << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_CBS_THRESH(offset)); + + /* + * assign CIR increment + */ + get_cir_incr_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_CIR_INCR(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->cir << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_CIR_INCR(offset)); + + /* + * assign ref count. + */ + get_ref_cnt_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_REF_CNT(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->ref_cnt[ddr_refcount] << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_REF_CNT(offset)); + + /* + * assign max bonus + */ + get_max_bonus_params(biu_cfg->queue_id, &offset, &shift, &mask); + reg = ubus_cohcfg_readl(ubus, UBUS_COHERENCY_MAX_BONUS(offset)); + reg &= ~(mask << shift); + reg |= (biu_cfg->bonus << shift); + ubus_cohcfg_writel(reg, ubus, UBUS_COHERENCY_MAX_BONUS(offset)); +} + +static void ubus_calc_queue_depth_from_credits(struct ubus4_bcm63158 *ubus, + struct biu_config *biu_configs, + size_t nr_biu_configs) +{ + size_t i; + u32 total_depth = 0; + + for (i = 0; i < nr_biu_configs; ++i) { + struct biu_config *cfg = &biu_configs[i]; + struct ubus4_master *m; + size_t j; + + if (!cfg->blk_name) + continue ; + + m = ubus_get_master(ubus, cfg->mstr_node); + if (!m) + continue ; + + for (j = 0; j < m->nr_credits; ++j) + if (m->credits[j].port_id == UBUS_PORT_ID_BIU) + cfg->depth = m->credits[j].credit; + } + + for (i = 0; i < nr_biu_configs; ++i) { + struct biu_config *cfg = &biu_configs[i]; + + total_depth += cfg->depth; + } + if (total_depth > 64) + /* + * NOTE: the refsw invokes BUG() here which is a bit + * heavy handed. + */ + dev_warn(ubus->dev, "total depth %u is greater than 64.\n", + total_depth); + else + dev_info(ubus->dev, "total depth %u ok.\n", + total_depth); +} + +static int ubus_get_ddr_mcb(struct ubus4_bcm63158 *ubus, u32 *mcb) +{ + struct of_phandle_args args; + int err; + + err = of_parse_phandle_with_args(ubus->dev->of_node, "brcm,dram", + 0, 0, &args); + if (err) + return err; + + err = of_property_read_u32(args.np, "brcm,ddr-mcb", mcb); + if (err) + return err; + + return 0; +} + +static int bcm63158_ubus4_probe(struct platform_device *pdev) +{ + struct ubus4_bcm63158 *ubus; + struct resource *res_regs, *coh_regs; + int err; + size_t i; + + dev_dbg(&pdev->dev, "probe.\n"); + + res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_regs) { + dev_err(&pdev->dev, "unable to get registers resource.\n"); + return -ENOENT; + } + + coh_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!coh_regs) { + dev_err(&pdev->dev, "unable to get coherency control registers " + "resource.\n"); + return -ENOENT; + } + + dev_info(&pdev->dev, "registers: %pR\n", res_regs); + + + ubus = devm_kzalloc(&pdev->dev, sizeof (*ubus), GFP_KERNEL); + if (!ubus) + return -ENOMEM; + + dev_info(&pdev->dev, "coherency control registers: %pR\n", + coh_regs); + ubus->coherency_control_regs_phys = coh_regs->start; + ubus->coherency_control_regs = devm_ioremap_resource(&pdev->dev, + coh_regs); + if (!ubus->coherency_control_regs) + return -ENOMEM; + + ubus->dev = &pdev->dev; + ubus->regs = *res_regs; + + err = ubus_get_ddr_mcb(ubus, &ubus->ddr_mcb); + if (err) { + dev_err(&pdev->dev, "unable to get DDR mcb from device " + "tree.\n"); + return err; + } + + ubus->nr_masters = ARRAY_SIZE(bcm63158_masters); + ubus->masters = devm_kzalloc(&pdev->dev, + sizeof (*ubus->masters) * ubus->nr_masters, + GFP_KERNEL); + if (!ubus->masters) + return -ENOMEM; + + + for (i = 0; i < ubus->nr_masters; ++i) { + err = ubus_setup_master(ubus, + &ubus->masters[i], + &bcm63158_masters[i]); + if (err) + return err; + } + + for (i = 0; i < ubus->nr_masters; ++i) { + ubus_master_apply_credits(&ubus->masters[i]); + } + for (i = 0; i < ubus->nr_masters; ++i) { + ubus_master_remap_port(&ubus->masters[i]); + } + ubus_enable_all_wlu_srcpid(ubus); + ubus_reset_biu_cfg(ubus); + ubus_calc_queue_depth_from_credits(ubus, biu_config_bcm63158, + ARRAY_SIZE(biu_config_bcm63158)); + + for (i = 0; i < ARRAY_SIZE(biu_config_bcm63158); ++i) { + if (biu_config_bcm63158[i].blk_name) + ubus_configure_biu(ubus, &biu_config_bcm63158[i]); + } + + mutex_lock(&ubus_list_mutex); + list_add_tail(&ubus->list, &ubus_list); + mutex_unlock(&ubus_list_mutex); + + return 0; +} + +static const struct of_device_id bcm63158_ubus4_match[] = { + { .compatible = "brcm,bcm63158-ubus4" }, + {}, +}; +MODULE_DEVICE_TABLE(of, bcm63158_ubus4_of_match); + +struct platform_driver bcm63158_ubus4_driver = { + .probe = bcm63158_ubus4_probe, + .remove = NULL, /* FIXME*/ + .driver = { + .name = "bcm63158-ubus4", + .owner = THIS_MODULE, + .of_match_table = bcm63158_ubus4_match, + }, +}; + +builtin_platform_driver(bcm63158_ubus4_driver); + +struct ubus4_master *ubus4_master_of_get_index(struct device_node *np, + int index) +{ + int err; + struct of_phandle_args args; + struct ubus4_bcm63158 *ubus; + + err = of_parse_phandle_with_args(np, "ubus", "#ubus-cells", index, + &args); + if (err) { + printk("unable to parse ubus phandle.\n"); + return ERR_PTR(err); + } + + if (args.args_count != 1) + return ERR_PTR(-EINVAL); + + mutex_lock(&ubus_list_mutex); + list_for_each_entry (ubus, &ubus_list, list) { + if (ubus->dev->of_node == args.np) { + mutex_unlock(&ubus_list_mutex); + goto found; + } + } + mutex_unlock(&ubus_list_mutex); + return ERR_PTR(-EPROBE_DEFER); + +found: + return ubus_get_master(ubus, args.args[0]); +} +EXPORT_SYMBOL(ubus4_master_of_get_index); + +struct ubus4_master *ubus4_master_of_get(struct device_node *np) +{ + return ubus4_master_of_get_index(np, 0); +} +EXPORT_SYMBOL(ubus4_master_of_get); + +MODULE_AUTHOR("Nicolas Schichan "); +MODULE_DESCRIPTION("Broadcom BCM63158 SoC UBUS driver."); +MODULE_LICENSE("GPL v2"); diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/Makefile linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/Makefile --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/Makefile 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/Makefile 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,8 @@ +obj-y += xrdp_drv.o + +xrdp_drv-y += \ + xrdp.o \ + xrdp_api.o + +xrdp_drv-$(CONFIG_SOC_BCM63XX_XRDP_IOCTL) += xrdp_ioctl.o +xrdp_drv-$(CONFIG_DEBUG_FS) += xrdp_debug.o diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_acb_if.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_acb_if.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_acb_if.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_acb_if.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,131 @@ +#ifndef XRDP_REGS_ACB_IF_H_ +#define XRDP_REGS_ACB_IF_H_ + +/* relative to core */ +#define ACB_IF_OFFSET_0 0xe50800 + +/* + * Register + * + * misc configs 0 + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0 0x0 + +/* add to the len of each packet 4B of crc */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0_CRC_ADD_MASK 0x1 + +/* + * location byte for the valid bit in the result(last bit in that byte): + * 0: + * bit 7. + * .. + * 7: + * bit 63 +*/ +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0_VAL_LOC_SHIFT 4 +#define ACB_IF_ACBIF_BLOCK_ACBIF_CONFIG_CONF0_VAL_LOC_MASK 0x70 + + +/* + * Registers - is [ 0 => 2 ] - read-only + * + * Number of commands that were processed for each command type (order - + * intend, sent, stat). + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_TYPE(x) (0x100 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_TYPE_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_TYPE_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 2 ] - read-only + * + * Number of commands that were processed for each IMP(0,1,2). + * e. + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_IMP(x) (0x110 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_IMP_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_CMD_IMP_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Number of commands (for each of - intend, sent) that were for aggregated + * packets. + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_AGG(x) (0x120 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_AGG_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_AGG_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Number of buffers that were counted for each command(order - intend, + * sent). + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_BUFFS(x) (0x130 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_BUFFS_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_BUFFS_VAL_MASK 0xffffffff + + +/* + * Register + * + * bits rd_clr and wrap for the pm counters(above) + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_GEN_CFG 0x150 + +/* read clear bit */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_GEN_CFG_RD_CLR_MASK 0x1 + +/* read clear bit */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_PM_COUNTERS_GEN_CFG_WRAP_MASK 0x2 + + +/* + * Register + * + * selects the debug vecore + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGSEL 0x200 + +/* selects th debug vector */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGSEL_VS_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGSEL_VS_MASK 0x7f + + +/* + * Register - read-only + * + * the debug bus + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGBUS 0x204 + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGBUS_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_DBGBUS_VAL_MASK 0x1fffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * status register (msb, lsb) + */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_STAT(x) (0x240 + (x) * 0x4) + +/* value */ +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_STAT_VAL_SHIFT 0 +#define ACB_IF_ACBIF_BLOCK_ACBIF_DEBUG_STAT_VAL_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_ACB_IF_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_bac_if.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bac_if.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_bac_if.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bac_if.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,285 @@ +#ifndef XRDP_REGS_BAC_IF_H_ +#define XRDP_REGS_BAC_IF_H_ + +/* relative to core */ +#define BAC_IF_OFFSET(x) (0xe40000 + (x) * 0x1000) + +/* + * Register + * + * FULL threshold of result fifo for rdy indication to engine: + * If there are less words than thr left - there will be !rdy indication to + * engine, even if there is antry empty, and result will not be pushed into + * fifo. + * - NOT USED ANYMORE! + */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_RSLT_F_FULL_THR 0x0 + +/* threshold */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_RSLT_F_FULL_THR_THR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_RSLT_F_FULL_THR_THR_MASK 0xf + + +/* + * Register + * + * route override info for the route address decoder + */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE 0x4 + +/* en override route address */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_EN_MASK 0x1 + +/* id to override route address */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ID_SHIFT 4 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ID_MASK 0x3f0 + +/* addr to override route address */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ADDR_SHIFT 16 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_DEC_ROUT_OVRIDE_ADDR_MASK 0x3ff0000 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL 0xc + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define BAC_IF_BACIF_BLOCK_BACIF_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 127 ] - read-only + * + * ingress fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO(x) (0x100 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_INGFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * cmd fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO(x) (0x500 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_CMDFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * result fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO(x) (0x600 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RSLTFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * egress fifo debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO(x) (0x700 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_EGFIFO_VAL_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * reply params array debug + */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR(x) (0x800 + (x) * 0x4) + +/* lower 31b of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_ENTRY_MASK 0x7fffffff + +/* valid bit of entry */ +#define BAC_IF_BACIF_BLOCK_BACIF_FIFOS_RPPRMARR_VAL_MASK 0x80000000 + + +/* + * Register - read-only + * + * number of bb transactions that enter the ingress fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT 0xc00 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ING_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of commands (eob) that enter the command fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT 0xc04 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_CMD_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of commands (eob) that enter the engine from the accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT 0xc08 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_CMD_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of results (eob) that enter the result fifo of accl_if from the + * engine + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT 0xc10 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ENG_RSLT_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of results (eob) that leave the result fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT 0xc14 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_RSLT_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of bb transactions that leave the egress fifo of accl_if + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT 0xc18 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_EGR_F_CNT_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of commands that entered and were longer than the max command + * size for the accelerator configured in HW parameter + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C 0xc30 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_CMDLNG_C_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * reply params array is full (no free entries), and a new command has + * arrived + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C 0xc34 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_OF_C_CNTR_MASK 0xffffffff + + +/* + * Register - read-only + * + * reply params array is empty, and a new result has arrived + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C 0xc38 + +/* value of cntr */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_SHIFT 0 +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_ERR_PARAMS_UF_C_CNTR_MASK 0xffffffff + + +/* + * Register + * + * bits rd_clr and wrap for the counters + */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG 0xcfc + +/* read clear bit */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_RD_CLR_MASK 0x1 + +/* read clear bit */ +#define BAC_IF_BACIF_BLOCK_BACIF_PM_COUNTERS_GEN_CFG_WRAP_MASK 0x2 + + +#endif /* ! XRDP_REGS_BAC_IF_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_bbh_rx.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_rx.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_bbh_rx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_rx.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,1387 @@ +#ifndef XRDP_REGS_BBH_RX_H_ +#define XRDP_REGS_BBH_RX_H_ + +/* relative to core */ +#define BBH_RX_OFFSET_0 0xd94000 + +/* relative to core */ +#define BBH_RX_OFFSET_1 0xd94400 + +/* relative to core */ +#define BBH_RX_OFFSET_2 0xd94800 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_3 0x8000 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_4 0x8400 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_5 0x8800 + +/* relative to wan_top */ +#define BBH_RX_OFFSET_6 0x8c00 + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * The BB defines the Route address for the specific unit. + */ +#define BBH_RX_GENERAL_CFG_BBCFG 0x0 + +/* + * SDMA BB ID. + * This ID defines the BB ID of the SDMA that the BBH communicates with. +*/ +#define GENERAL_CFG_BBCFG_SDMABBID_SHIFT 0 +#define GENERAL_CFG_BBCFG_SDMABBID_MASK 0x3f + +/* + * Dispatcher BB ID. + * This ID defines the BB ID of the Dispatcher that the BBH communicates + * with. +*/ +#define GENERAL_CFG_BBCFG_DISPBBID_SHIFT 8 +#define GENERAL_CFG_BBCFG_DISPBBID_MASK 0x3f00 + +/* + * SBPM BB ID. + * This ID defines the BB ID of the SBPM that the BBH communicates with. +*/ +#define GENERAL_CFG_BBCFG_SBPMBBID_SHIFT 16 +#define GENERAL_CFG_BBCFG_SBPMBBID_MASK 0x3f0000 + + +/* + * Register + * + * For every reassembled packet in the PSRAM the BBH writes a packet + * descriptor (PD) into the Dispatcher. + * The PDs are arranged using a link list in the Dispatcher. + * The Dispatcher has 32 virtual queues (ingress queues) and the BBH may be + * assigned to each of the 32 virtual queues of the DispatcherThis register + * defines virtual queue for normal and exclusive packets. + */ +#define BBH_RX_GENERAL_CFG_DISPVIQ 0x4 + +/* Defines the Dispatchers Virtual Ingress Queue for normal packets */ +#define GENERAL_CFG_DISPVIQ_NORMALVIQ_SHIFT 0 +#define GENERAL_CFG_DISPVIQ_NORMALVIQ_MASK 0x1f + +/* Defines the Dispatchers Virtual Ingress Queue for exclusive packets */ +#define GENERAL_CFG_DISPVIQ_EXCLVIQ_SHIFT 8 +#define GENERAL_CFG_DISPVIQ_EXCLVIQ_MASK 0x1f00 + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNDATALSB 0x8 + +/* + * Pattern Data[31: + * 0] +*/ +#define GENERAL_CFG_PATTERNDATALSB_PATTERNDATALSB_SHIFT 0 +#define GENERAL_CFG_PATTERNDATALSB_PATTERNDATALSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNDATAMSB 0xc + +/* + * Pattern Data[63: + * 32] +*/ +#define GENERAL_CFG_PATTERNDATAMSB_PATTERNDATAMSB_SHIFT 0 +#define GENERAL_CFG_PATTERNDATAMSB_PATTERNDATAMSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNMASKLSB 0x10 + +/* + * Pattern mask[31: + * 0] +*/ +#define GENERAL_CFG_PATTERNMASKLSB_PATTERNMASKLSB_SHIFT 0 +#define GENERAL_CFG_PATTERNMASKLSB_PATTERNMASKLSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to a match in the pattern recognition. + */ +#define BBH_RX_GENERAL_CFG_PATTERNMASKMSB 0x14 + +/* + * Pattern Mask[63: + * 32] +*/ +#define GENERAL_CFG_PATTERNMASKMSB_PATTERNMASKMSB_SHIFT 0 +#define GENERAL_CFG_PATTERNMASKMSB_PATTERNMASKMSB_MASK 0xffffffff + + +/* + * Register + * + * The BBH may direct a packet into the Dispatchers exclusive VIQ (Virtual + * Ingress Queue) according to special packet types (e. + * g. + * pause). + * This register enables this function + */ +#define BBH_RX_GENERAL_CFG_EXCLQCFG 0x18 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PLOAMEN_MASK 0x1 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PRI3EN_MASK 0x2 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PAUSEEN_MASK 0x4 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_PFCEN_MASK 0x8 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_CTRLEN_MASK 0x10 + +/* Direct this packet type to Exclusive VIQ in the Dispatcher */ +#define GENERAL_CFG_EXCLQCFG_MULTEN_MASK 0x20 + +/* + * Defines the pattern recognition offset within the packet. + * Offset is 8 bytes resolution +*/ +#define GENERAL_CFG_EXCLQCFG_PATTENOFFSET_SHIFT 8 +#define GENERAL_CFG_EXCLQCFG_PATTENOFFSET_MASK 0xf00 + +/* Must be enabled if pattern recognition is used */ +#define GENERAL_CFG_EXCLQCFG_PATTERNEN_MASK 0x10000 + +/* Must be enabled if Exclusive VIQ is used */ +#define GENERAL_CFG_EXCLQCFG_EXCEN_MASK 0x100000 + + +/* + * Register + * + * The BBH reassembles the incoming data in the SRAM. + * The Data is written into the SRAM using the SDMA. + * The data is organized in a configurable number of chunks of 128 bytes. + * The BBH arranges the written data in the SDMA in these chunks. + * It arranges the data in a predefined address space in the SDMA memory + * and manages the chunks in a cyclic FIFO style. + * For every write chunk the BBH writes a write descriptor. + * The write descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style as well. + * This register defines the Data and descriptors base addresses. + */ +#define BBH_RX_GENERAL_CFG_SDMAADDR 0x1c + +/* + * The Data FIFO base address within the SDMA address space. + * The address is in chunk resolution (128 bytes). + * The value should be identical to the relevant configuration in the SDMA. +*/ +#define GENERAL_CFG_SDMAADDR_DATABASE_SHIFT 0 +#define GENERAL_CFG_SDMAADDR_DATABASE_MASK 0x3f + +/* + * The Descriptor FIFO base address within the SDMA address space. + * The address is in chunk descriptor resolution (8 bytes). + * The value should be identical to the relevant configuration in the SDMA. +*/ +#define GENERAL_CFG_SDMAADDR_DESCBASE_SHIFT 8 +#define GENERAL_CFG_SDMAADDR_DESCBASE_MASK 0x3f00 + + +/* + * Register + * + * The BBH reassembles the incoming data in the SRAM. + * The Data is written into the SRAM using the SDMA. + * The data is organized in a configurable number of chunks of 128 bytes. + * The BBH arranges the written data in the SDMA in these chunks. + * It arranges the data in a predefined address space in the SDMA memory + * and manages the chunks in a cyclic FIFO style. + * For every write chunk the BBH writes a write descriptor. + * The write descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style as well. + * The BBH handles the congestion over the SDMA write chunks according to 2 + * priorities (low + high, exclusive). + * This field defines the number of occupied write chunks for dropping + * normal or high priority packets. + * If the number of occupied chunk is lower than this threshold, then all + * packets are passed. + * If the number of occupied chunk is equal or higher than this threshold, + * then only exclusive priority packets are passed. + * This register defines the Data and descriptors FIFO sizes and the + * exclusive threshold. + */ +#define BBH_RX_GENERAL_CFG_SDMACFG 0x20 + +/* Defines the size of the Chunk descripors FIFO in the DMA. */ +#define GENERAL_CFG_SDMACFG_NUMOFCD_SHIFT 0 +#define GENERAL_CFG_SDMACFG_NUMOFCD_MASK 0x7f + +/* + * This field defines the number of occupied write chunks for dropping + * normal or high priority packets. +*/ +#define GENERAL_CFG_SDMACFG_EXCLTH_SHIFT 8 +#define GENERAL_CFG_SDMACFG_EXCLTH_MASK 0x7f00 + +/* + * BBH has two methods to keep coherency: + * 1. + * Write reply for last chunk only2. + * Write reply for each chunk1 - enables the first method0 - enables the + * second method +*/ +#define GENERAL_CFG_SDMACFG_COHERENCYEN_MASK 0x10000 + + +/* + * Register + * + * There are 4 global configuration for Minimum packet size. + * Each flow can get one out of these 4 global configurations. + * Packets shorter than this threshold will be discarded. + */ +#define BBH_RX_GENERAL_CFG_MINPKT0 0x24 + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT0_SHIFT 0 +#define GENERAL_CFG_MINPKT0_MINPKT0_MASK 0xff + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT1_SHIFT 8 +#define GENERAL_CFG_MINPKT0_MINPKT1_MASK 0xff00 + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT2_SHIFT 16 +#define GENERAL_CFG_MINPKT0_MINPKT2_MASK 0xff0000 + +/* Packets shorter than this threshold will be discarded. */ +#define GENERAL_CFG_MINPKT0_MINPKT3_SHIFT 24 +#define GENERAL_CFG_MINPKT0_MINPKT3_MASK 0xff000000 + + +/* + * Register + * + * There are 4 global configuration for Maximum packet size. + * Each flow can get one out of these 4 global configurations. + * Packets longer than this threshold will be discarded. + */ +#define BBH_RX_GENERAL_CFG_MAXPKT0 0x28 + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT0_MAXPKT0_SHIFT 0 +#define GENERAL_CFG_MAXPKT0_MAXPKT0_MASK 0x3fff + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT0_MAXPKT1_SHIFT 16 +#define GENERAL_CFG_MAXPKT0_MAXPKT1_MASK 0x3fff0000 + + +/* + * Register + * + * There are 4 global configuration for Maximum packet size. + * Each flow can get one out of these 4 global configurations. + * Packets longer than this threshold will be discarded. + */ +#define BBH_RX_GENERAL_CFG_MAXPKT1 0x2c + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT1_MAXPKT2_SHIFT 0 +#define GENERAL_CFG_MAXPKT1_MAXPKT2_MASK 0x3fff + +/* Packets longer than this threshold will be discarded. */ +#define GENERAL_CFG_MAXPKT1_MAXPKT3_SHIFT 16 +#define GENERAL_CFG_MAXPKT1_MAXPKT3_MASK 0x3fff0000 + + +/* + * Register + * + * The BBH writes the packets into the PSRAM. + * The start of data offset is configurable. + * This register defines the SOP (start of packet) offset. + */ +#define BBH_RX_GENERAL_CFG_SOPOFFSET 0x30 + +/* + * The SOP offset in bytes. + * Allowed values: + * 0-127. + * This value should match the relevant configuration in the Runner block. +*/ +#define GENERAL_CFG_SOPOFFSET_SOPOFFSET_SHIFT 0 +#define GENERAL_CFG_SOPOFFSET_SOPOFFSET_MASK 0x7f + + +/* + * Register + * + * The BBH manages a flow control indication towards the Ethernet MAC + * according to BB messages from the FW. + * Each FW command will assert the flow control indication towards the + * Ethernet MAC and will trigger a timer. + * When the timer expires, the BBH will de-assert the flow control + * indication. + * This register also disable BBH packet drop due to no space in the SDMA, + * SBPM or Dispatcher. + */ +#define BBH_RX_GENERAL_CFG_FLOWCTRL 0x34 + +/* + * Timer value before de-asserting the flow control indication. + * The duration of the time is determined according to the BBH clock + * frequency. +*/ +#define GENERAL_CFG_FLOWCTRL_TIMER_SHIFT 0 +#define GENERAL_CFG_FLOWCTRL_TIMER_MASK 0xffffff + +/* Disable dropping packets due to no space in the Dispatcher. */ +#define GENERAL_CFG_FLOWCTRL_DISPDROPDIS_MASK 0x1000000 + +/* Disable dropping packets due to no space in the SDMA. */ +#define GENERAL_CFG_FLOWCTRL_SDMADROPDIS_MASK 0x2000000 + +/* Disable dropping packets due to no space in the SBPM. */ +#define GENERAL_CFG_FLOWCTRL_SBPMDROPDIS_MASK 0x4000000 + +/* Asserting this bit will force a flow control indication towards the MAC */ +#define GENERAL_CFG_FLOWCTRL_FCFORCE_MASK 0x10000000 + + +/* + * Register + * + * The BBH omits the 4 CRC bytes of the packet for all packets except + * PLOAMs and OMCI (marked as exclusive priority). + * The configuration will disable this functionality. + */ +#define BBH_RX_GENERAL_CFG_CRCOMITDIS 0x38 + +/* Disable CRC omitting. */ +#define GENERAL_CFG_CRCOMITDIS_CRCOMITDIS_MASK 0x1 + + +/* + * Register + * + * Controls the BBH enable configuration + */ +#define BBH_RX_GENERAL_CFG_ENABLE 0x3c + +/* + * When de-asserted, the BBH will not read new fragment/packet from the + * MAC. + * The BBH will Gracefully enable/disable (on fragment boundary for + * N/X/GPON/2 and on packet boundary for the rest) +*/ +#define GENERAL_CFG_ENABLE_PKTEN_MASK 0x1 + +/* When de-asserted, the BBH will not pre-fetch SBPM buffers */ +#define GENERAL_CFG_ENABLE_SBPMEN_MASK 0x2 + + +/* + * Register + * + * When asserted, G999. + * 1 fragments are received by the BBH. + * The BBH will pass the G999. + * 1 header in the PD instead of the 1588 time-stamp. + */ +#define BBH_RX_GENERAL_CFG_G9991EN 0x40 + +/* + * Enable G999. + * 1 +*/ +#define GENERAL_CFG_G9991EN_ENABLE_MASK 0x1 + +/* + * Enable G999. + * 1 transfer of bytes 4-7 instead of bytes 0-3 +*/ +#define GENERAL_CFG_G9991EN_BYTES4_7ENABLE_MASK 0x2 + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines X. + */ +#define BBH_RX_GENERAL_CFG_PERFLOWTH 0x44 + +/* + * According to this threshold: + * Flows 32 - th will have set 0 configurations. + * Flows (th+1) - 255 will have set 1 configurations. +*/ +#define GENERAL_CFG_PERFLOWTH_FLOWTH_SHIFT 0 +#define GENERAL_CFG_PERFLOWTH_FLOWTH_MASK 0xff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the configurations sets. + */ +#define BBH_RX_GENERAL_CFG_PERFLOWSETS 0x48 + +/* + * Set 0 of the general configuration. + * Selects between 4 global minimum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL0_SHIFT 0 +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL0_MASK 0x3 + +/* + * Set 0 of the general configuration. + * Selects between 4 global maximum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL0_SHIFT 2 +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL0_MASK 0xc + +/* + * Set 1 of the general configuration. + * Selects between 4 global minimum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL1_SHIFT 4 +#define GENERAL_CFG_PERFLOWSETS_MINPKTSEL1_MASK 0x30 + +/* + * Set 1 of the general configuration. + * Selects between 4 global maximum packet size. +*/ +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL1_SHIFT 6 +#define GENERAL_CFG_PERFLOWSETS_MAXPKTSEL1_MASK 0xc0 + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the minimum packet size for flows 0-15. + */ +#define BBH_RX_GENERAL_CFG_MINPKTSEL0 0x50 + +/* + * Selects one of the 4 global configurations for minimum packet size. + * Bits {2n, 2n+1} refers to flow n. +*/ +#define GENERAL_CFG_MINPKTSEL0_MINPKTSEL_SHIFT 0 +#define GENERAL_CFG_MINPKTSEL0_MINPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the minimum packet size for flows 16-31. + */ +#define BBH_RX_GENERAL_CFG_MINPKTSEL1 0x54 + +/* + * Selects one of the 4 global configurations for minimum packet size. + * Bits {2n, 2n+1} refers to flow n+16. +*/ +#define GENERAL_CFG_MINPKTSEL1_MINPKTSEL_SHIFT 0 +#define GENERAL_CFG_MINPKTSEL1_MINPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the maximum packet size for flows 0-15. + */ +#define BBH_RX_GENERAL_CFG_MAXPKTSEL0 0x58 + +/* + * Selects one of the 4 global configurations for maximum packet size. + * Bits {2n, 2n+1} refers to flow n. +*/ +#define GENERAL_CFG_MAXPKTSEL0_MAXPKTSEL_SHIFT 0 +#define GENERAL_CFG_MAXPKTSEL0_MAXPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * The DS has 256 flows. + * Minimum packet size (2 bits) and Maximum packet size (2 bits) are + * configured per flow. + * Flows 0-31 will have full configurations. + * Flows 32-X and flows (X+1)-255 will have global set of configurations. + * X is configurable. + * This register defines the maximum packet size for flows 16-31. + */ +#define BBH_RX_GENERAL_CFG_MAXPKTSEL1 0x5c + +/* + * Selects one of the 4 global configurations for maximum packet size. + * Bits {2n, 2n+1} refers to flow n+16. +*/ +#define GENERAL_CFG_MAXPKTSEL1_MAXPKTSEL_SHIFT 0 +#define GENERAL_CFG_MAXPKTSEL1_MAXPKTSEL_MASK 0xffffffff + + +/* + * Register + * + * When the BBH functions as a PON BBH, this bit selects between N/X/GPON/2 + * and 10G/EPON functionality + */ +#define BBH_RX_GENERAL_CFG_MACMODE 0x60 + +/* + * Relevant for PON BBH only. + * Distinguish between GPON (GPON, XGPON, NGPON2) to EPON (EPON, 10GEPON): + * 0: + * N/X/GPON/21: + * 10G/EPON +*/ +#define GENERAL_CFG_MACMODE_MACMODE_MASK 0x1 + +/* + * Relevant for GPON BBH only. + * Distinguish between GPON and XGPON (XGPON, NGPON2): + * 0: + * GPON1: + * N/X/GPON/2 +*/ +#define GENERAL_CFG_MACMODE_GPONMODE_MASK 0x2 + +/* + * Relevant for VDSL BBH only. + * Distinguish between VDSL and non VDSL: + * 0: + * Non VDSL1: + * VDSL +*/ +#define GENERAL_CFG_MACMODE_MACVDSL_MASK 0x4 + + +/* + * Register + * + * Configure max on the fly requests to SBPM + */ +#define BBH_RX_GENERAL_CFG_SBPMCFG 0x64 + +/* Configure max on the fly requests to SBPM */ +#define GENERAL_CFG_SBPMCFG_MAXREQ_SHIFT 0 +#define GENERAL_CFG_SBPMCFG_MAXREQ_MASK 0xf + + +/* + * Register + * + * This register enable reset of internal units (for WA perposes). + */ +#define BBH_RX_GENERAL_CFG_RXRSTRST 0x68 + +/* + * Writing 1 to this register will reset the input buffer. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_INBUFRST_MASK 0x1 + +/* + * Writing 1 to this register will reset the Burst buffer. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_BURSTBUFRST_MASK 0x2 + +/* + * Writing 1 to this register will reset the ingress context. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_INGRESSCNTXT_MASK 0x4 + +/* + * Writing 1 to this register will reset the IH buffer enable. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_CMDFIFORST_MASK 0x8 + +/* + * Writing 1 to this register will reset the SBPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define GENERAL_CFG_RXRSTRST_SBPMFIFORST_MASK 0x10 + +/* + * Writing 1 to this register will reset the coherency FIFO. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_COHERENCYFIFORST_MASK 0x20 + +/* + * Writing 1 to this register will reset the reassembly context table. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define GENERAL_CFG_RXRSTRST_CNTXTRST_MASK 0x40 + +/* + * Writing 1 to this register will reset the SDMA write pointer. + * For a reset operation the SW should assert and then de-assert this bit. +*/ +#define GENERAL_CFG_RXRSTRST_SDMARST_MASK 0x80 + + +/* + * Register + * + * Selects one out of 10 possible debug vectors + */ +#define BBH_RX_GENERAL_CFG_RXDBGSEL 0x6c + +/* Selects one out of 10 possible debug vectors */ +#define GENERAL_CFG_RXDBGSEL_RXDBGSEL_SHIFT 0 +#define GENERAL_CFG_RXDBGSEL_RXDBGSEL_MASK 0xf + + +/* + * Register + * + * This register enables changing the route address for a specified BB ID + */ +#define BBH_RX_GENERAL_CFG_BBHRX_RADDR_DECODER 0x70 + +/* This field contains the users BB id for override */ +#define GENERAL_CFG_BBHRX_RADDR_DECODER_ID_2OVERWR_SHIFT 0 +#define GENERAL_CFG_BBHRX_RADDR_DECODER_ID_2OVERWR_MASK 0x3f + +/* The new RA */ +#define GENERAL_CFG_BBHRX_RADDR_DECODER_OVERWR_RA_SHIFT 8 +#define GENERAL_CFG_BBHRX_RADDR_DECODER_OVERWR_RA_MASK 0x3ff00 + +/* the overwr mechanism will be used only if this bit is active (1). */ +#define GENERAL_CFG_BBHRX_RADDR_DECODER_OVERWR_EN_MASK 0x1000000 + + +/* + * Register + * + * There an option to disable CRC error counting for this flow. + */ +#define BBH_RX_GENERAL_CFG_NONETH 0x74 + +/* Non Ethernet flow ID */ +#define GENERAL_CFG_NONETH_FLOWID_SHIFT 0 +#define GENERAL_CFG_NONETH_FLOWID_MASK 0xff + +/* When asserted, CRC errors will not be counted for that flow. */ +#define GENERAL_CFG_NONETH_ENABLE_MASK 0x100 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define BBH_RX_GENERAL_CFG_CLK_GATE_CNTRL 0x78 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define GENERAL_CFG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define GENERAL_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register - read-only + * + * This counter counts the number of incoming good packets. + * It counts the packets from all flows together. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_INPKT 0x100 + +/* This counter counts the number of incoming good packets. */ +#define PM_COUNTERS_INPKT_INPKT_SHIFT 0 +#define PM_COUNTERS_INPKT_INPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Third flow error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_THIRDFLOW 0x104 + +/* PM counter value. */ +#define PM_COUNTERS_THIRDFLOW_PMVALUE_SHIFT 0 +#define PM_COUNTERS_THIRDFLOW_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to SOP after SOP error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_SOPASOP 0x108 + +/* PM counter value. */ +#define PM_COUNTERS_SOPASOP_PMVALUE_SHIFT 0 +#define PM_COUNTERS_SOPASOP_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Too short error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_TOOSHORT 0x10c + +/* PM counter value. */ +#define PM_COUNTERS_TOOSHORT_PMVALUE_SHIFT 0 +#define PM_COUNTERS_TOOSHORT_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Too long error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_TOOLONG 0x110 + +/* PM counter value. */ +#define PM_COUNTERS_TOOLONG_PMVALUE_SHIFT 0 +#define PM_COUNTERS_TOOLONG_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to CRC error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_CRCERROR 0x114 + +/* PM counter value. */ +#define PM_COUNTERS_CRCERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_CRCERROR_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to XGPON encryption error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_ENCRYPTERROR 0x118 + +/* PM counter value. */ +#define PM_COUNTERS_ENCRYPTERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_ENCRYPTERROR_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Dispatcher congestion error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_DISPCONG 0x11c + +/* PM counter value. */ +#define PM_COUNTERS_DISPCONG_PMVALUE_SHIFT 0 +#define PM_COUNTERS_DISPCONG_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to NO SBPM SBN error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSBPMSBN 0x124 + +/* PM counter value. */ +#define PM_COUNTERS_NOSBPMSBN_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSBPMSBN_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to No SDMA CD error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSDMACD 0x12c + +/* PM counter value. */ +#define PM_COUNTERS_NOSDMACD_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSDMACD_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of incoming good PLOAMs. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_INPLOAM 0x130 + +/* This counter counts the number of incoming PLOAMs. */ +#define PM_COUNTERS_INPLOAM_INPLOAM_SHIFT 0 +#define PM_COUNTERS_INPLOAM_INPLOAM_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the PLOAMs drop due to CRC error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_CRCERRORPLOAM 0x134 + +/* PM counter value. */ +#define PM_COUNTERS_CRCERRORPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_CRCERRORPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to Dispatcher congestion error + * for PLOAM. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_DISPCONGPLOAM 0x138 + +/* PM counter value. */ +#define PM_COUNTERS_DISPCONGPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_DISPCONGPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the PLOAMs drop due to No SBPM SBN error. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSBPMSBNPLOAM 0x13c + +/* PM counter value. */ +#define PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSBPMSBNPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the packets drop due to No SDMA CD error for PLOAMs. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_NOSDMACDPLOAM 0x140 + +/* PM counter value. */ +#define PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_SHIFT 0 +#define PM_COUNTERS_NOSDMACDPLOAM_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the events of EPON type sequence which is wrong, + * meaning no sop after header, or sop/header in the middle of packet + * (before eop). + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_EPONTYPERROR 0x144 + +/* PM counter value. */ +#define PM_COUNTERS_EPONTYPERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_EPONTYPERROR_PMVALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of RUNT packets received from the XLMAC. + * This counter is cleared when read and freezes when reaches the maximum + * value. + */ +#define BBH_RX_PM_COUNTERS_RUNTERROR 0x148 + +/* PM counter value. */ +#define PM_COUNTERS_RUNTERROR_PMVALUE_SHIFT 0 +#define PM_COUNTERS_RUNTERROR_PMVALUE_MASK 0xffff + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX0LSB 0x200 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX0LSB_INREASS_MASK 0x1 + +/* Flow ID */ +#define DEBUG_CNTXTX0LSB_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX0LSB_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX0LSB_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX0LSB_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX0MSB 0x204 + +/* Current BN */ +#define DEBUG_CNTXTX0MSB_CURBN_SHIFT 0 +#define DEBUG_CNTXTX0MSB_CURBN_MASK 0x1fff + +/* First BN */ +#define DEBUG_CNTXTX0MSB_FIRSTBN_SHIFT 16 +#define DEBUG_CNTXTX0MSB_FIRSTBN_MASK 0x7fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX1LSB 0x208 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX1LSB_INREASS_MASK 0x1 + +/* Flow ID */ +#define DEBUG_CNTXTX1LSB_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX1LSB_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX1LSB_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX1LSB_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX1MSB 0x20c + +/* Current BN */ +#define DEBUG_CNTXTX1MSB_CURBN_SHIFT 0 +#define DEBUG_CNTXTX1MSB_CURBN_MASK 0x1fff + +/* First BN */ +#define DEBUG_CNTXTX1MSB_FIRSTBN_SHIFT 16 +#define DEBUG_CNTXTX1MSB_FIRSTBN_MASK 0x7fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX0INGRESS 0x210 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX0INGRESS_INREASS_MASK 0x1 + +/* SOP */ +#define DEBUG_CNTXTX0INGRESS_SOP_MASK 0x10 + +/* Priority */ +#define DEBUG_CNTXTX0INGRESS_PRIORITY_SHIFT 6 +#define DEBUG_CNTXTX0INGRESS_PRIORITY_MASK 0xc0 + +/* Flow ID */ +#define DEBUG_CNTXTX0INGRESS_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX0INGRESS_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX0INGRESS_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX0INGRESS_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * In the case of GPON peripheral, DS flows may arrive interleaved. + * The BBH supports parallel reassembly of up to two interleaved flows (out + * of 256). + * For the reassembly process the BBH stores a double flow context. + */ +#define BBH_RX_DEBUG_CNTXTX1INGRESS 0x214 + +/* + * In reassembly. + * Not relevant for Ethernet. +*/ +#define DEBUG_CNTXTX1INGRESS_INREASS_MASK 0x1 + +/* SOP */ +#define DEBUG_CNTXTX1INGRESS_SOP_MASK 0x10 + +/* Priority */ +#define DEBUG_CNTXTX1INGRESS_PRIORITY_SHIFT 6 +#define DEBUG_CNTXTX1INGRESS_PRIORITY_MASK 0xc0 + +/* Flow ID */ +#define DEBUG_CNTXTX1INGRESS_FLOWID_SHIFT 8 +#define DEBUG_CNTXTX1INGRESS_FLOWID_MASK 0xff00 + +/* Current offset */ +#define DEBUG_CNTXTX1INGRESS_CUROFFSET_SHIFT 16 +#define DEBUG_CNTXTX1INGRESS_CUROFFSET_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * Input buf used words + */ +#define BBH_RX_DEBUG_IBUW 0x218 + +/* Used words */ +#define DEBUG_IBUW_UW_SHIFT 0 +#define DEBUG_IBUW_UW_MASK 0x7 + + +/* + * Register - read-only + * + * Burst buf used words + */ +#define BBH_RX_DEBUG_BBUW 0x21c + +/* Used words */ +#define DEBUG_BBUW_UW_SHIFT 0 +#define DEBUG_BBUW_UW_MASK 0xf + + +/* + * Register - read-only + * + * Coherency FIFO used words + */ +#define BBH_RX_DEBUG_CFUW 0x220 + +/* Used words */ +#define DEBUG_CFUW_UW_SHIFT 0 +#define DEBUG_CFUW_UW_MASK 0x3f + + +/* + * Register - read-only + * + * The register reflects 2 ACK counters: + * SDMACONNECT + */ +#define BBH_RX_DEBUG_ACKCNT 0x224 + +/* SDMA ACK counter */ +#define DEBUG_ACKCNT_SDMA_SHIFT 0 +#define DEBUG_ACKCNT_SDMA_MASK 0x1f + +/* Connect ACK counter */ +#define DEBUG_ACKCNT_CONNECT_SHIFT 8 +#define DEBUG_ACKCNT_CONNECT_MASK 0x1f00 + + +/* + * Register - read-only + * + * The register 2 pending coherency counters: + * NormalExclusive + */ +#define BBH_RX_DEBUG_COHERENCYCNT 0x228 + +/* Normal */ +#define DEBUG_COHERENCYCNT_NORMAL_SHIFT 0 +#define DEBUG_COHERENCYCNT_NORMAL_MASK 0x1f + +/* Exclusive */ +#define DEBUG_COHERENCYCNT_EXCLUSIVE_SHIFT 8 +#define DEBUG_COHERENCYCNT_EXCLUSIVE_MASK 0x1f00 + + +/* + * Register - read-only + * + * selected debug vector + */ +#define BBH_RX_DEBUG_DBGVEC 0x22c + +/* selected debug vector */ +#define DEBUG_DBGVEC_DBGVEC_SHIFT 0 +#define DEBUG_DBGVEC_DBGVEC_MASK 0x1fffff + + +/* + * Register - read-only + * + * Upload FIFO used words + */ +#define BBH_RX_DEBUG_UFUW 0x230 + +/* Used words */ +#define DEBUG_UFUW_UW_SHIFT 0 +#define DEBUG_UFUW_UW_MASK 0x7 + + +/* + * Register - read-only + * + * This register holds 2 credit counters: + * NormalExclusive + */ +#define BBH_RX_DEBUG_CREDITCNT 0x234 + +/* Normal */ +#define DEBUG_CREDITCNT_NORMAL_SHIFT 0 +#define DEBUG_CREDITCNT_NORMAL_MASK 0x1f + +/* Exclusive */ +#define DEBUG_CREDITCNT_EXCLUSIVE_SHIFT 8 +#define DEBUG_CREDITCNT_EXCLUSIVE_MASK 0x1f00 + + +/* + * Register - read-only + * + * Number of used SDMA CDs + */ +#define BBH_RX_DEBUG_SDMACNT 0x238 + +/* Used CDs */ +#define DEBUG_SDMACNT_UCD_SHIFT 0 +#define DEBUG_SDMACNT_UCD_MASK 0x7f + + +/* + * Register - read-only + * + * CMD FIFO used words + */ +#define BBH_RX_DEBUG_CMFUW 0x23c + +/* Used words */ +#define DEBUG_CMFUW_UW_SHIFT 0 +#define DEBUG_CMFUW_UW_MASK 0x7 + + +/* + * Registers - is [ 0 => 15 ] - read-only + * + * The BBH RX hold a FIFO with 16 BN. + */ +#define BBH_RX_DEBUG_SBNFIFO(x) (0x240 + (x) * 0x4) + +/* BN */ +#define DEBUG_SBNFIFO_BNENTRY_SHIFT 0 +#define DEBUG_SBNFIFO_BNENTRY_MASK 0x3fff + +/* SBN is Valid */ +#define DEBUG_SBNFIFO_VALID_MASK 0x10000 + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * The BBH RX hold a FIFO with 8 command. + */ +#define BBH_RX_DEBUG_CMDFIFO(x) (0x280 + (x) * 0x4) + +/* CMD */ +#define DEBUG_CMDFIFO_CMDENTRY_SHIFT 0 +#define DEBUG_CMDFIFO_CMDENTRY_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * The BBH RX hold a recycle FIFO with up to 2 BN. + */ +#define BBH_RX_DEBUG_SBNRECYCLEFIFO(x) (0x290 + (x) * 0x4) + +/* BN */ +#define DEBUG_SBNRECYCLEFIFO_BNENTRY_SHIFT 0 +#define DEBUG_SBNRECYCLEFIFO_BNENTRY_MASK 0x3fff + +/* SBN is Valid */ +#define DEBUG_SBNRECYCLEFIFO_VALID_MASK 0x10000 + + +/* + * Register - read-only + * + * Read of 4 coherency counters: + * CD CMD sent (1 per flow)EOP ACK received (1 per flow) + */ +#define BBH_RX_DEBUG_COHERENCYCNT2 0x2a0 + +/* CD sent */ +#define DEBUG_COHERENCYCNT2_CDSENT_SHIFT 0 +#define DEBUG_COHERENCYCNT2_CDSENT_MASK 0x7f + +/* EOP ACK received */ +#define DEBUG_COHERENCYCNT2_ACKRECEIVED_SHIFT 8 +#define DEBUG_COHERENCYCNT2_ACKRECEIVED_MASK 0x7f00 + + +/* + * Register + * + * Information of the following: + * - Dispatcher drop due to coherency FIFO full- SDMA drop due to coherency + * method 2 counters over 63 (dec) + */ +#define BBH_RX_DEBUG_DROPSTATUS 0x2a4 + +/* + * Dispatcher drop due to coherency FIFO full. + * Writing 1 to this bit clears it +*/ +#define DEBUG_DROPSTATUS_DISPSTATUS_MASK 0x1 + +/* + * SDMA drop due to coherency method 2 counters over 63 (dec). + * Writing 1 to this bit clears it +*/ +#define DEBUG_DROPSTATUS_SDMASTATUS_MASK 0x2 + + +#endif /* ! XRDP_REGS_BBH_RX_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_bbh_tx.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_tx.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_bbh_tx.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_bbh_tx.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,2073 @@ +#ifndef XRDP_REGS_BBH_TX_H_ +#define XRDP_REGS_BBH_TX_H_ + +/* relative to core */ +#define BBH_TX_OFFSET_0 0xd90000 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_1 0x0 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_2 0x2000 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_3 0x4000 + +/* relative to wan_top */ +#define BBH_TX_OFFSET_4 0x6000 + +/* + * Register + * + * The BBH supports working with different MAC types. + * Each MAC requires different interface and features. + * This register defines the type of MAC the BBH works with. + */ +#define BBH_TX_COMMON_CFGS_MACTYPE 0x0 + +/* MAC type */ +#define COMMON_CFGS_MACTYPE_TYPE_SHIFT 0 +#define COMMON_CFGS_MACTYPE_TYPE_MASK 0x7 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define BBH_TX_COMMON_CFGS_BBCFG_1_TX 0x4 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_DMASRC_SHIFT 0 +#define COMMON_CFGS_BBCFG_1_TX_DMASRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_SDMASRC_SHIFT 8 +#define COMMON_CFGS_BBCFG_1_TX_SDMASRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_SBPMSRC_SHIFT 16 +#define COMMON_CFGS_BBCFG_1_TX_SBPMSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define COMMON_CFGS_BBCFG_1_TX_FPMSRC_SHIFT 24 +#define COMMON_CFGS_BBCFG_1_TX_FPMSRC_MASK 0x3f000000 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define BBH_TX_COMMON_CFGS_BBCFG_2_TX 0x8 + +/* + * source id. + * This id is used to determine the route to the 1st (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_SHIFT 0 +#define COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the 2nd (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_SHIFT 8 +#define COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the Runner that is responsible + * for sending status messages (WAN only). +*/ +#define COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_SHIFT 16 +#define COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the Runner which is + * responsible for sending DBR/Ghost messages (WAN only). +*/ +#define COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_SHIFT 24 +#define COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_MASK 0x3f000000 + + +/* + * Register + * + * Configurations for determining the address to read from the DDR/PSRAm + */ +#define BBH_TX_COMMON_CFGS_DDRCFG_TX 0xc + +/* The data is arranged in the DDR in a fixed size buffers. */ +#define COMMON_CFGS_DDRCFG_TX_BUFSIZE_SHIFT 0 +#define COMMON_CFGS_DDRCFG_TX_BUFSIZE_MASK 0x7 + +/* The packet offset byte resulotion. */ +#define COMMON_CFGS_DDRCFG_TX_BYTERESUL_MASK 0x8 + +/* Static offset in 8-bytes resolution for non aggregated packets in DDR */ +#define COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_SHIFT 4 +#define COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_MASK 0x1ff0 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define COMMON_CFGS_DDRCFG_TX_HNSIZE0_SHIFT 16 +#define COMMON_CFGS_DDRCFG_TX_HNSIZE0_MASK 0x7f0000 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define COMMON_CFGS_DDRCFG_TX_HNSIZE1_SHIFT 24 +#define COMMON_CFGS_DDRCFG_TX_HNSIZE1_MASK 0x7f000000 + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner +b +: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_COMMON_CFGS_RNRCFG_1(x) (0x10 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define COMMON_CFGS_RNRCFG_1_TCONTADDR_SHIFT 0 +#define COMMON_CFGS_RNRCFG_1_TCONTADDR_MASK 0xffff + +/* + * Defines the SKB free address within the Runner address space. + * The address is in 8-bytes resolution. +*/ +#define COMMON_CFGS_RNRCFG_1_SKBADDR_SHIFT 16 +#define COMMON_CFGS_RNRCFG_1_SKBADDR_MASK 0xffff0000 + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_COMMON_CFGS_RNRCFG_2(x) (0x18 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define COMMON_CFGS_RNRCFG_2_PTRADDR_SHIFT 0 +#define COMMON_CFGS_RNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define COMMON_CFGS_RNRCFG_2_TASK_SHIFT 16 +#define COMMON_CFGS_RNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Register + * + * The BBH reads the packet data from the DDR in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the DMA + * memory space. + * The read descriptors are arranged in a predefined space in the DMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define BBH_TX_COMMON_CFGS_DMACFG_TX 0x20 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define COMMON_CFGS_DMACFG_TX_DESCBASE_SHIFT 0 +#define COMMON_CFGS_DMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define COMMON_CFGS_DMACFG_TX_DESCSIZE_SHIFT 6 +#define COMMON_CFGS_DMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define COMMON_CFGS_DMACFG_TX_MAXREQ_SHIFT 16 +#define COMMON_CFGS_DMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define COMMON_CFGS_DMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on read requests of a + * jumbo packet (>2K) +*/ +#define COMMON_CFGS_DMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * The BBH reads the packet data from the PSRAM in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the SDMA + * memory space. + * The read descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define BBH_TX_COMMON_CFGS_SDMACFG_TX 0x24 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define COMMON_CFGS_SDMACFG_TX_DESCBASE_SHIFT 0 +#define COMMON_CFGS_SDMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define COMMON_CFGS_SDMACFG_TX_DESCSIZE_SHIFT 6 +#define COMMON_CFGS_SDMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define COMMON_CFGS_SDMACFG_TX_MAXREQ_SHIFT 16 +#define COMMON_CFGS_SDMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define COMMON_CFGS_SDMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on Jumbo packets (>2k) + * read requests +*/ +#define COMMON_CFGS_SDMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * When packet transmission is done, the BBH releases the SBPM buffers. + * This register defines which release command is used: + * 1. + * Normal free with context2. + * Special free with context3. + * free without context + */ +#define BBH_TX_COMMON_CFGS_SBPMCFG 0x28 + +/* When this bit is enabled, the BBH will use free without context command. */ +#define COMMON_CFGS_SBPMCFG_FREENOCNTXT_MASK 0x1 + +/* + * When this bit is enabled, the BBH will use special free with context + * command. + * This bit is relevant only if free without context_en is configured to 0. +*/ +#define COMMON_CFGS_SBPMCFG_SPECIALFREE_MASK 0x2 + +/* maximum number of pending on the fly get next commands */ +#define COMMON_CFGS_SBPMCFG_MAXGN_SHIFT 8 +#define COMMON_CFGS_SBPMCFG_MAXGN_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define BBH_TX_COMMON_CFGS_DDRTMBASEL(x) (0x2c + (x) * 0x4) + +/* + * DDR TM base. + * The address is in bytes resolution. + * The address should be aligned to 128 bytes. +*/ +#define COMMON_CFGS_DDRTMBASEL_DDRTMBASE_SHIFT 0 +#define COMMON_CFGS_DDRTMBASEL_DDRTMBASE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define BBH_TX_COMMON_CFGS_DDRTMBASEH(x) (0x34 + (x) * 0x4) + +/* MSB of DDR TM base. */ +#define COMMON_CFGS_DDRTMBASEH_DDRTMBASE_SHIFT 0 +#define COMMON_CFGS_DDRTMBASEH_DDRTMBASE_MASK 0xff + + +/* + * Register + * + * The BBH orders data both from DDR and PSRAM. + * The returned data is stored in two FIFOs for reordering. + * The two FIFOs are implemented in a single RAM. + * This register defines the division of the RAM to two FIFOs. + */ +#define BBH_TX_COMMON_CFGS_DFIFOCTRL 0x3c + +/* + * The size of the PSRAM data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the PSRAM. +*/ +#define COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_SHIFT 0 +#define COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_MASK 0x3ff + +/* + * The size of the DDR data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the DDR. +*/ +#define COMMON_CFGS_DFIFOCTRL_DDRSIZE_SHIFT 10 +#define COMMON_CFGS_DFIFOCTRL_DDRSIZE_MASK 0xffc00 + +/* + * the base address of the PSRAM data FIFO in 8 bytes resolution. + * The DDR data FIFO base address is always 0. + * In case the whole RAM is to be dedicated to PSRAM data, the base should + * be 0 as well, and the DDR FIFO size should be configured to 0. +*/ +#define COMMON_CFGS_DFIFOCTRL_PSRAMBASE_SHIFT 20 +#define COMMON_CFGS_DFIFOCTRL_PSRAMBASE_MASK 0x3ff00000 + + +/* + * Register + * + * configurations related to different arbitration processes (ordering PDs, + * ordering data) + */ +#define BBH_TX_COMMON_CFGS_ARB_CFG 0x40 + +/* + * this configuration determines whether to give high priority to a current + * transmitting queue or not. +*/ +#define COMMON_CFGS_ARB_CFG_HIGHTRXQ_MASK 0x1 + + +/* + * Register + * + * override configuration for the route of one of the peripherals + * (DMA/SDMMA/FPM/SBPM?Runners) + */ +#define BBH_TX_COMMON_CFGS_BBROUTE 0x44 + +/* route address */ +#define COMMON_CFGS_BBROUTE_ROUTE_SHIFT 0 +#define COMMON_CFGS_BBROUTE_ROUTE_MASK 0x3ff + +/* destination source id */ +#define COMMON_CFGS_BBROUTE_DEST_SHIFT 10 +#define COMMON_CFGS_BBROUTE_DEST_MASK 0xfc00 + +/* enable */ +#define COMMON_CFGS_BBROUTE_EN_MASK 0x10000 + + +/* + * Registers - is [ 0 => 19 ] + * + * configuration which queue is managed by each of the two runners. + * Each register in this array configures 2 queues. + */ +#define BBH_TX_COMMON_CFGS_Q2RNR(x) (0x48 + (x) * 0x4) + +/* Q0 configuration */ +#define COMMON_CFGS_Q2RNR_Q0_MASK 0x1 + +/* Q1 configuration */ +#define COMMON_CFGS_Q2RNR_Q1_MASK 0x2 + + +/* + * Register + * + * which task in the runner to wake-up when requesting a PD for a certain + * q. + * This register holds the task number of the first 8 queues. + * For queues 8-40 (if they exist) the task that will be waking is the one + * appearing in the PD_RNR_CFG regs, depending on which runner this queue + * is associated with. + */ +#define BBH_TX_COMMON_CFGS_PERQTASK 0xa0 + +#define COMMON_CFGS_PERQTASK_TASKx_SHIFT(x) (4 * (x)) +#define COMMON_CFGS_PERQTASK_TASKx_MASK(x) (0xf << (4 * (x))) + + +/* + * Register + * + * This register enables reset of internal units (for possible WA + * purposes). + */ +#define BBH_TX_COMMON_CFGS_TXRSTCMD 0xb0 + +/* + * Writing 1 to this register will reset the segmentation context table. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_CNTXTRST_MASK 0x1 + +/* + * Writing 1 to this register will reset the PDs FIFOs. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_PDFIFORST_MASK 0x2 + +/* + * Writing 1 to this register will reset the DMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_DMAPTRRST_MASK 0x4 + +/* + * Writing 1 to this register will reset the SDMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_SDMAPTRRST_MASK 0x8 + +/* + * Writing 1 to this register will reset the BPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_BPMFIFORST_MASK 0x10 + +/* + * Writing 1 to this register will reset the SBPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_SBPMFIFORST_MASK 0x20 + +/* + * Writing 1 to this register will reset the order keeper FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_OKFIFORST_MASK 0x40 + +/* + * Writing 1 to this register will reset the DDR data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_DDRFIFORST_MASK 0x80 + +/* + * Writing 1 to this register will reset the SRAM data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define COMMON_CFGS_TXRSTCMD_SRAMFIFORST_MASK 0x100 + +/* + * Writing 1 to this register will reset the SKB pointers. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_SKBPTRRST_MASK 0x200 + +/* + * Writing 1 to this register will reset the EPON status FIFOs (per queue + * 32 fifos). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_STSFIFORST_MASK 0x400 + +/* + * Writing 1 to this register will reset the EPON request FIFO (8 entries + * FIFO that holds the packet requests from the EPON MAC). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_REQFIFORST_MASK 0x800 + +/* + * Writing 1 to this register will reset the EPON/GPON MSG FIFOThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_MSGFIFORST_MASK 0x1000 + +/* + * Writing 1 to this register will reset the GET NEXT FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_GNXTFIFORST_MASK 0x2000 + +/* + * Writing 1 to this register will reset the FIRST BN FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define COMMON_CFGS_TXRSTCMD_FBNFIFORST_MASK 0x4000 + + +/* + * Register + * + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. + */ +#define BBH_TX_COMMON_CFGS_DBGSEL 0xb4 + +/* + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. +*/ +#define COMMON_CFGS_DBGSEL_DBGSEL_SHIFT 0 +#define COMMON_CFGS_DBGSEL_DBGSEL_MASK 0x1f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define BBH_TX_COMMON_CFGS_CLK_GATE_CNTRL 0xb8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * general purpose register + */ +#define BBH_TX_COMMON_CFGS_GPR 0xbc + +/* general purpose register */ +#define COMMON_CFGS_GPR_GPR_SHIFT 0 +#define COMMON_CFGS_GPR_GPR_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 19 ] + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the Status FIFO, 1st BN FIFO and get-next FIFO is the same + * as the size of the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PDBASE(x) (0x100 + (x) * 0x4) + +/* The base of PD FIFO for queue 0. */ +#define WAN_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define WAN_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define WAN_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define WAN_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 19 ] + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PDSIZE(x) (0x150 + (x) * 0x4) + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define WAN_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define WAN_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define WAN_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define WAN_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 19 ] + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PDWKUPH(x) (0x200 + (x) * 0x4) + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define WAN_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define WAN_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define WAN_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 16 +#define WAN_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff0000 + + +/* + * Registers - is [ 0 => 19 ] + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define BBH_TX_WAN_CFGS_PD_BYTE_TH(x) (0x250 + (x) * 0x4) + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define WAN_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define BBH_TX_WAN_CFGS_PD_BYTE_TH_EN 0x300 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define WAN_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define BBH_TX_WAN_CFGS_PDEMPTY 0x304 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define WAN_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define WAN_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner + * address. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_STSRNRCFG_1(x) (0x310 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define WAN_CFGS_STSRNRCFG_1_TCONTADDR_SHIFT 0 +#define WAN_CFGS_STSRNRCFG_1_TCONTADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_STSRNRCFG_2(x) (0x320 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define WAN_CFGS_STSRNRCFG_2_PTRADDR_SHIFT 0 +#define WAN_CFGS_STSRNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define WAN_CFGS_STSRNRCFG_2_TASK_SHIFT 16 +#define WAN_CFGS_STSRNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner + * address. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_MSGRNRCFG_1(x) (0x330 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define WAN_CFGS_MSGRNRCFG_1_TCONTADDR_SHIFT 0 +#define WAN_CFGS_MSGRNRCFG_1_TCONTADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define BBH_TX_WAN_CFGS_MSGRNRCFG_2(x) (0x340 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define WAN_CFGS_MSGRNRCFG_2_PTRADDR_SHIFT 0 +#define WAN_CFGS_MSGRNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define WAN_CFGS_MSGRNRCFG_2_TASK_SHIFT 16 +#define WAN_CFGS_MSGRNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Register + * + * Configurations related to EPON MAC. + */ +#define BBH_TX_WAN_CFGS_EPNCFG 0x350 + +/* + * In case of fatal length error - a mismatch between the request message + * from MAC and its relevant PD from Runner - the BBH can stop performing + * or continue regardless of the error. + * The error is also reflected to the SW in a counter. +*/ +#define WAN_CFGS_EPNCFG_STPLENERR_MASK 0x1 + +/* + * configures the width of the comparison of the packet ength. + * The length field in the EPON request interface is 11 bit, while it is 14 + * bit in the pd. + * If this bit is 0, then the comparison of the length will be between the + * 11 bit of the interface and the 11 lsb bits of the pd. + * If this ibt is 1, the comparison will be done between the 11 bits of the + * interface, concatenated with 3 zeros and the 14 bits of the pd +*/ +#define WAN_CFGS_EPNCFG_CMP_WIDTH_MASK 0x2 + +/* + * determines whether the BBH will consider the sts_full vector state when + * pushing STS messages to the MAC or not. + * The status fifos inside the MAC should never go full as they are mirror + * of the BBH PD FIFOs, but in cases where the MAC design behaves different + * than expected, we want the BBH to be able to operate as in 1G EPON mode +*/ +#define WAN_CFGS_EPNCFG_CONSIDERFULL_MASK 0x4 + +/* + * configuration whether to add 4 bytes per packet to the length received + * in the status message from the Runner so the MAC would know the actual + * length to be transmitted. +*/ +#define WAN_CFGS_EPNCFG_ADDCRC_MASK 0x8 + + +/* + * Register + * + * interface for SW to access the flow id to port-id table + */ +#define BBH_TX_WAN_CFGS_FLOW2PORT 0x354 + +/* + * write data. + * 15:0 - port-id - default is 0x000016 - regenerate CRC - enabled by + * default + * 17 - enc enable - disabled by default +*/ +#define WAN_CFGS_FLOW2PORT_WDATA_SHIFT 0 +#define WAN_CFGS_FLOW2PORT_WDATA_MASK 0x3ffff + +/* address */ +#define WAN_CFGS_FLOW2PORT_A_SHIFT 18 +#define WAN_CFGS_FLOW2PORT_A_MASK 0x3fc0000 + +/* rd/wr cmd */ +#define WAN_CFGS_FLOW2PORT_CMD_MASK 0x4000000 + + +/* + * Register + * + * The BBH is responsible for indicating the EPON MAC that the current + * packet that is being transmitted is a 1588 paacket. + * The BBH gets the 1588 parameters in the PD and forward it to the MAC. + * This register is used to enable this feature. + */ +#define BBH_TX_WAN_CFGS_TS 0x358 + +/* 1588 enable */ +#define WAN_CFGS_TS_EN_MASK 0x1 + + +/* + * Register + * + * VDSL max word lenrelevant only for VDSL BBH + */ +#define BBH_TX_WAN_CFGS_MAXWLEN 0x360 + +/* VDSL max word len */ +#define WAN_CFGS_MAXWLEN_MAXWLEN_SHIFT 0 +#define WAN_CFGS_MAXWLEN_MAXWLEN_MASK 0xffff + + +/* + * Register + * + * VDSL Flush indicationrelevant only for VDSL BBH + */ +#define BBH_TX_WAN_CFGS_FLUSH 0x364 + +/* VDSL flush */ +#define WAN_CFGS_FLUSH_FLUSH_SHIFT 0 +#define WAN_CFGS_FLUSH_FLUSH_MASK 0xffff + +/* soft reset */ +#define WAN_CFGS_FLUSH_SRST_N_MASK 0x80000000 + + +/* + * Register + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PDBASE 0x400 + +/* The base of PD FIFO for queue 0. */ +#define LAN_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define LAN_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define LAN_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define LAN_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PDSIZE 0x450 + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define LAN_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define LAN_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define LAN_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define LAN_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Register + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PDWKUPH 0x500 + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define LAN_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define LAN_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define LAN_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 8 +#define LAN_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff00 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define BBH_TX_LAN_CFGS_PD_BYTE_TH 0x550 + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define LAN_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define BBH_TX_LAN_CFGS_PD_BYTE_TH_EN 0x600 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define LAN_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define BBH_TX_LAN_CFGS_PDEMPTY 0x604 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define LAN_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define LAN_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Register + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the XLMAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + */ +#define BBH_TX_LAN_CFGS_TXTHRESH 0x608 + +/* DDR Transmit threshold in 8 bytes resoltion */ +#define LAN_CFGS_TXTHRESH_DDRTHRESH_SHIFT 0 +#define LAN_CFGS_TXTHRESH_DDRTHRESH_MASK 0x1ff + +/* SRAM Transmit threshold in 8 bytes resoltion */ +#define LAN_CFGS_TXTHRESH_SRAMTHRESH_SHIFT 16 +#define LAN_CFGS_TXTHRESH_SRAMTHRESH_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that no traffic is about + * to arrive so the XLMAC may try to enter power saving mode. + * This register is used to enable this feature. + */ +#define BBH_TX_LAN_CFGS_EEE 0x60c + +/* enable bit */ +#define LAN_CFGS_EEE_EN_MASK 0x1 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that it should and + * calculate timestamp for the current packet that is being transmitted. + * The BBH gets the timestamping parameters in the PD and forward it to the + * XLMAC. + * This register is used to enable this feature. + */ +#define BBH_TX_LAN_CFGS_TS 0x610 + +/* enable bit */ +#define LAN_CFGS_TS_EN_MASK 0x1 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 6 queues. + * Each queue is dedicated to one MAC interface. + * A total of 48 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 48 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PDBASE(x) (0x700 + (x) * 0x4) + +/* The base of PD FIFO for queue 0. */ +#define UNIFIED_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define UNIFIED_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define UNIFIED_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define UNIFIED_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 6 queues. + * Each queue is dedicated to one MAC interface. + * A total of 48 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 48 + * PDs. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PDSIZE(x) (0x750 + (x) * 0x4) + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define UNIFIED_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PDWKUPH(x) (0x800 + (x) * 0x4) + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 8 +#define UNIFIED_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff00 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_PD_BYTE_TH(x) (0x850 + (x) * 0x4) + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define UNIFIED_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define BBH_TX_UNIFIED_CFGS_PD_BYTE_TH_EN 0x900 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define UNIFIED_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define BBH_TX_UNIFIED_CFGS_PDEMPTY 0x904 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define UNIFIED_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define UNIFIED_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Register + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the XLMAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + * This threshold is used by the non unified BBH. + * for unified BBH it should be set to 0. + */ +#define BBH_TX_UNIFIED_CFGS_GTXTHRESH 0x908 + +/* DDR Transmit threshold in 8 bytes resoltion */ +#define UNIFIED_CFGS_GTXTHRESH_DDRTHRESH_SHIFT 0 +#define UNIFIED_CFGS_GTXTHRESH_DDRTHRESH_MASK 0x1ff + +/* SRAM Transmit threshold in 8 bytes resoltion */ +#define UNIFIED_CFGS_GTXTHRESH_SRAMTHRESH_SHIFT 16 +#define UNIFIED_CFGS_GTXTHRESH_SRAMTHRESH_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that no traffic is about + * to arrive so the XLMAC may try to enter power saving mode. + * This register is used to enable this feature per MAC + */ +#define BBH_TX_UNIFIED_CFGS_EEE 0x90c + +/* enable bit */ +#define UNIFIED_CFGS_EEE_EN_SHIFT 0 +#define UNIFIED_CFGS_EEE_EN_MASK 0xff + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that it should and + * calculate timestamp for the current packet that is being transmitted. + * The BBH gets the timestamping parameters in the PD and forward it to the + * XLMAC. + * This register is used to enable this feature per MAC + */ +#define BBH_TX_UNIFIED_CFGS_TS 0x910 + +/* enable bit */ +#define UNIFIED_CFGS_TS_EN_SHIFT 0 +#define UNIFIED_CFGS_TS_EN_MASK 0xff + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FEBASE(x) (0x920 + (x) * 0x4) + +/* The base of FE FIFO for queue 0. */ +#define UNIFIED_CFGS_FEBASE_FIFOBASE0_SHIFT 0 +#define UNIFIED_CFGS_FEBASE_FIFOBASE0_MASK 0x7ff + +/* The base of FE FIFO for queue 1. */ +#define UNIFIED_CFGS_FEBASE_FIFOBASE1_SHIFT 16 +#define UNIFIED_CFGS_FEBASE_FIFOBASE1_MASK 0x7ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FESIZE(x) (0x940 + (x) * 0x4) + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FESIZE_FIFOSIZE0_SHIFT 0 +#define UNIFIED_CFGS_FESIZE_FIFOSIZE0_MASK 0x7ff + +/* + * The size of FE FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FESIZE_FIFOSIZE1_SHIFT 16 +#define UNIFIED_CFGS_FESIZE_FIFOSIZE1_MASK 0x7ff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FEPDBASE(x) (0x960 + (x) * 0x4) + +/* The base of FE PD FIFO for queue 0. */ +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE0_SHIFT 0 +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE0_MASK 0xff + +/* The base of FE PD FIFO for queue 1. */ +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE1_SHIFT 16 +#define UNIFIED_CFGS_FEPDBASE_FIFOBASE1_MASK 0xff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define BBH_TX_UNIFIED_CFGS_FEPDSIZE(x) (0x980 + (x) * 0x4) + +/* + * The size of FE PD FIFO for queue 0. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE0_SHIFT 0 +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE0_MASK 0xff + +/* + * The size of FE PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE1_SHIFT 16 +#define UNIFIED_CFGS_FEPDSIZE_FIFOSIZE1_MASK 0xff0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * The unified BBH TX serves multiple MACs. + * The TX arbitration between these MACs is WRR. + * This register array determines the weight of each MAC. + * Each register in the array represents 2 MACs. + */ +#define BBH_TX_UNIFIED_CFGS_TXWRR(x) (0x9a0 + (x) * 0x4) + +/* weight of MAC0 */ +#define UNIFIED_CFGS_TXWRR_W0_SHIFT 0 +#define UNIFIED_CFGS_TXWRR_W0_MASK 0xf + +/* weight of MAC1 */ +#define UNIFIED_CFGS_TXWRR_W1_SHIFT 16 +#define UNIFIED_CFGS_TXWRR_W1_MASK 0xf0000 + + +/* + * Registers - is [ 0 => 3 ] + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the MAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + */ +#define BBH_TX_UNIFIED_CFGS_TXTHRESH(x) (0x9e0 + (x) * 0x4) + +/* Transmit threshold in 8 bytes resoltion for mac 0 */ +#define UNIFIED_CFGS_TXTHRESH_THRESH0_SHIFT 0 +#define UNIFIED_CFGS_TXTHRESH_THRESH0_MASK 0x1ff + +/* Transmit threshold in 8 bytes resolution for MAC1 */ +#define UNIFIED_CFGS_TXTHRESH_THRESH1_SHIFT 16 +#define UNIFIED_CFGS_TXTHRESH_THRESH1_MASK 0x1ff0000 + + +/* + * Register - read-only + * + * This counter counts the number of received PD for packets to be + * transmitted from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_SRAMPD 0xa00 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define DEBUG_COUNTERS_SRAMPD_SRAMPD_SHIFT 0 +#define DEBUG_COUNTERS_SRAMPD_SRAMPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received PDs for packets to be + * transmitted from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_DDRPD 0xa04 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define DEBUG_COUNTERS_DDRPD_DDRPD_SHIFT 0 +#define DEBUG_COUNTERS_DDRPD_DDRPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_PDDROP 0xa08 + +/* + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. +*/ +#define DEBUG_COUNTERS_PDDROP_PDDROP_SHIFT 0 +#define DEBUG_COUNTERS_PDDROP_PDDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of STS messages which were received from + * Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_STSCNT 0xa10 + +/* This counter counts the number of received status messages. */ +#define DEBUG_COUNTERS_STSCNT_STSCNT_SHIFT 0 +#define DEBUG_COUNTERS_STSCNT_STSCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of STS which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_STSDROP 0xa14 + +/* + * This counter counts the number of STS which were dropped due to PD FIFO + * full. +*/ +#define DEBUG_COUNTERS_STSDROP_STSDROP_SHIFT 0 +#define DEBUG_COUNTERS_STSDROP_STSDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG (DBR/Ghost) messages which were + * received from Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_MSGCNT 0xa18 + +/* This counter counts the number of received DBR/ghost messages. */ +#define DEBUG_COUNTERS_MSGCNT_MSGCNT_SHIFT 0 +#define DEBUG_COUNTERS_MSGCNT_MSGCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_MSGDROP 0xa1c + +/* + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. +*/ +#define DEBUG_COUNTERS_MSGDROP_MSGDROP_SHIFT 0 +#define DEBUG_COUNTERS_MSGDROP_MSGDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number Get next responses with a null BN. + * It counts the packets for all TCONTs together. + * This counter is cleared when read and freezes when maximum value is + * reached. + * This counter is relevant for Ethernet only. + */ +#define BBH_TX_DEBUG_COUNTERS_GETNEXTNULL 0xa20 + +/* This counter counts the number Get next responses with a null BN. */ +#define DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_SHIFT 0 +#define DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of packets that were flushed (bn was + * released without sending the data to the EPON MAC) due to flush request. + * The counter is global for all queues. + * The counter is read clear. + */ +#define BBH_TX_DEBUG_COUNTERS_FLUSHPKTS 0xa24 + +/* This counter counts the number of flushed packets */ +#define DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_SHIFT 0 +#define DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of times a length error (mismatch between + * a request from the MAC and a PD from the Runner) occured. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_LENERR 0xa28 + +/* This counter counts the number of times a length error occuered */ +#define DEBUG_COUNTERS_LENERR_LENERR_SHIFT 0 +#define DEBUG_COUNTERS_LENERR_LENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter Counts aggregation length error events. + * If one or more of the packets in an aggregated PD is shorter than 60 + * bytes, this counter will be incremented by 1. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_AGGRLENERR 0xa2c + +/* + * This counter counts the number of times an aggregation length error + * occuered +*/ +#define DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_SHIFT 0 +#define DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_SRAMPKT 0xa30 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define DEBUG_COUNTERS_SRAMPKT_SRAMPKT_SHIFT 0 +#define DEBUG_COUNTERS_SRAMPKT_SRAMPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_DDRPKT 0xa34 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define DEBUG_COUNTERS_DDRPKT_DDRPKT_SHIFT 0 +#define DEBUG_COUNTERS_DDRPKT_DDRPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the SRAM. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_SRAMBYTE 0xa38 + +/* This counter counts the number of transmitted bytes from the SRAM. */ +#define DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_SHIFT 0 +#define DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the DDR. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_DDRBYTE 0xa3c + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define DEBUG_COUNTERS_DDRBYTE_DDRBYTE_SHIFT 0 +#define DEBUG_COUNTERS_DDRBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Register + * + * writing to this register creates a rd_en pulse to the selected array the + * SW wants to access. + * Each bit in the register represents one of the arrays the SW can access. + * The address inside the array is determined in the previous register + * (sw_rd_address). + * When writing to this register the SW should assert only one bit. + * If more than one is asserted, The HW will return the value read from the + * lsb selected array. + */ +#define BBH_TX_DEBUG_COUNTERS_SWRDEN 0xa40 + +/* rd from the PD FIFO */ +#define DEBUG_COUNTERS_SWRDEN_PDSEL_MASK 0x1 + +/* rd from the PD valid array */ +#define DEBUG_COUNTERS_SWRDEN_PDVSEL_MASK 0x2 + +/* rd from the PD empty array */ +#define DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_MASK 0x4 + +/* rd from the PD Full array */ +#define DEBUG_COUNTERS_SWRDEN_PDFULLSEL_MASK 0x8 + +/* rd from the PD beliow empty array */ +#define DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_MASK 0x10 + +/* rd from the PD full for wakeup empty array */ +#define DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_MASK 0x20 + +/* rd from the first BN array */ +#define DEBUG_COUNTERS_SWRDEN_FBNSEL_MASK 0x40 + +/* rd from the first BN valid array */ +#define DEBUG_COUNTERS_SWRDEN_FBNVSEL_MASK 0x80 + +/* rd from the first BN empty array */ +#define DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_MASK 0x100 + +/* rd from the first BN full array */ +#define DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_MASK 0x200 + +/* rd from the first Get Next array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_MASK 0x400 + +/* rd from the get_next valid array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_MASK 0x800 + +/* rd from the get next empty array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_MASK 0x1000 + +/* rd from the get next full array */ +#define DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_MASK 0x2000 + +/* rd from the gpon context array */ +#define DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_MASK 0x4000 + +/* rd from the BPM FIFO */ +#define DEBUG_COUNTERS_SWRDEN_BPMSEL_MASK 0x8000 + +/* rd from the BPM FLUSH FIFO */ +#define DEBUG_COUNTERS_SWRDEN_BPMFSEL_MASK 0x10000 + +/* rd from the SBPM FIFO */ +#define DEBUG_COUNTERS_SWRDEN_SBPMSEL_MASK 0x20000 + +/* rd from the SBPM FLUSH FIFO */ +#define DEBUG_COUNTERS_SWRDEN_SBPMFSEL_MASK 0x40000 + +/* rd from the STS FIFO */ +#define DEBUG_COUNTERS_SWRDEN_STSSEL_MASK 0x80000 + +/* rd from the STS valid array */ +#define DEBUG_COUNTERS_SWRDEN_STSVSEL_MASK 0x100000 + +/* rd from the STS empty array */ +#define DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_MASK 0x200000 + +/* rd from the STS Full array */ +#define DEBUG_COUNTERS_SWRDEN_STSFULLSEL_MASK 0x400000 + +/* rd from the STS beliow empty array */ +#define DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_MASK 0x800000 + +/* rd from the STS full for wakeup empty array */ +#define DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_MASK 0x1000000 + +/* rd from the MSG FIFO */ +#define DEBUG_COUNTERS_SWRDEN_MSGSEL_MASK 0x2000000 + +/* rd from the msg valid array */ +#define DEBUG_COUNTERS_SWRDEN_MSGVSEL_MASK 0x4000000 + +/* rd from the epon request FIFO */ +#define DEBUG_COUNTERS_SWRDEN_EPNREQSEL_MASK 0x8000000 + +/* rd from the DATA FIFO (SRAM and DDR) */ +#define DEBUG_COUNTERS_SWRDEN_DATASEL_MASK 0x10000000 + +/* rd from the reorder FIFO */ +#define DEBUG_COUNTERS_SWRDEN_REORDERSEL_MASK 0x20000000 + +/* rd from the Timestamp Info FIFO */ +#define DEBUG_COUNTERS_SWRDEN_TSINFOSEL_MASK 0x40000000 + +/* rd from the MAC TX FIFO. */ +#define DEBUG_COUNTERS_SWRDEN_MACTXSEL_MASK 0x80000000 + + +/* + * Register + * + * the address inside the array the SW wants to read + */ +#define BBH_TX_DEBUG_COUNTERS_SWRDADDR 0xa44 + +/* The address inside the array the sw wants to read */ +#define DEBUG_COUNTERS_SWRDADDR_RDADDR_SHIFT 0 +#define DEBUG_COUNTERS_SWRDADDR_RDADDR_MASK 0x7ff + + +/* + * Register - read-only + * + * indirect memories and arrays read data + */ +#define BBH_TX_DEBUG_COUNTERS_SWRDDATA 0xa48 + +/* data */ +#define DEBUG_COUNTERS_SWRDDATA_DATA_SHIFT 0 +#define DEBUG_COUNTERS_SWRDDATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted packets through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_UNIFIEDPKT(x) (0xa50 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_SHIFT 0 +#define DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted bytes through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define BBH_TX_DEBUG_COUNTERS_UNIFIEDBYTE(x) (0xa70 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_SHIFT 0 +#define DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * an array including all the debug vectors of the BBH TX. + * entries 30 and 31 are DSL debug. + */ +#define BBH_TX_DEBUG_COUNTERS_DBGOUTREG(x) (0xa90 + (x) * 0x4) + +/* Selected debug vector. */ +#define DEBUG_COUNTERS_DBGOUTREG_DBGVEC_SHIFT 0 +#define DEBUG_COUNTERS_DBGOUTREG_DBGVEC_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * 40 bit vector in which each bit represents if the segmentation SM is + * currently handling a PD of a certain TCONT. + * first address is for TCONTS [31: + * 0]second is for TCONTS [39: + * 32] + */ +#define BBH_TX_DEBUG_COUNTERS_IN_SEGMENTATION(x) (0xb20 + (x) * 0x4) + +/* in_segmentation indication */ +#define DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_SHIFT 0 +#define DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_BBH_TX_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_cnpl.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_cnpl.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_cnpl.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_cnpl.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,405 @@ +#ifndef XRDP_REGS_CNPL_H_ +#define XRDP_REGS_CNPL_H_ + +/* relative to core */ +#define CNPL_OFFSET_0 0xe48000 + +/* + * Registers - is [ 0 => 3071 ] + * + * mem_entry + */ +#define CNPL_MEMORY_DATA(x) (0x0 + (x) * 0x4) + +/* data */ +#define MEMORY_DATA_DATA_SHIFT 0 +#define MEMORY_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * location profiles + */ +#define CNPL_COUNTERS_CFGS_CN_LOC_PROF(x) (0x4000 + (x) * 0x4) + +/* + * counters group base address (in 8B resolution: + * 0 is 0x0, 1 is 0x8, . + * .. + * ) +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_BA_SHIFT 0 +#define COUNTERS_CFGS_CN_LOC_PROF_BA_MASK 0x7ff + +/* + * number of bytes that will hold each sub-counter. + * 0: + * 1B1: + * 2B2: + * 4B +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_CN0_BYTS_SHIFT 11 +#define COUNTERS_CFGS_CN_LOC_PROF_CN0_BYTS_MASK 0x1800 + +/* + * 1: + * each counter of the group is double sub-cntr0: + * each counter of the group is single +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_DOUBLLE_MASK 0x2000 + +/* + * 1: + * wrap at max value0: + * freeze at max value +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_WRAP_MASK 0x4000 + +/* + * 1: + * read clear when reading0: + * read no-clear when reading +*/ +#define COUNTERS_CFGS_CN_LOC_PROF_CLR_MASK 0x8000 + + +/* + * Registers - is [ 0 => 1 ] + * + * 1st reg for location profiles + */ +#define CNPL_POLICERS_CFGS_PL_LOC_PROF0(x) (0x4100 + (x) * 0x4) + +/* + * buckets base address(in 8B resolution: + * 0 is 0x0, 1 is 0x8, . + * .. + * ) +*/ +#define POLICERS_CFGS_PL_LOC_PROF0_BK_BA_SHIFT 0 +#define POLICERS_CFGS_PL_LOC_PROF0_BK_BA_MASK 0x7ff + +/* + * params base address(in 8B resolution: + * 0 is 0x0, 1 is 0x8, . + * .. + * ) +*/ +#define POLICERS_CFGS_PL_LOC_PROF0_PA_BA_SHIFT 11 +#define POLICERS_CFGS_PL_LOC_PROF0_PA_BA_MASK 0x3ff800 + +/* + * 1: + * each policer is dual bucket0: + * each policer is single bucket +*/ +#define POLICERS_CFGS_PL_LOC_PROF0_DOUBLLE_MASK 0x400000 + + +/* + * Registers - is [ 0 => 1 ] + * + * 2nd reg for location profiles + */ +#define CNPL_POLICERS_CFGS_PL_LOC_PROF1(x) (0x4108 + (x) * 0x4) + +/* Index of 1st policer of the group. */ +#define POLICERS_CFGS_PL_LOC_PROF1_PL_ST_SHIFT 0 +#define POLICERS_CFGS_PL_LOC_PROF1_PL_ST_MASK 0xff + +/* Index of last policer of the group. */ +#define POLICERS_CFGS_PL_LOC_PROF1_PL_END_SHIFT 8 +#define POLICERS_CFGS_PL_LOC_PROF1_PL_END_MASK 0xff00 + + +/* + * Registers - is [ 0 => 2 ] + * + * calculation type register. + * 0: + * green, yellow, red1: + * red, yellow, green + */ +#define CNPL_POLICERS_CFGS_PL_CALC_TYPE(x) (0x4110 + (x) * 0x4) + +/* 32b vector for 32 policers */ +#define POLICERS_CFGS_PL_CALC_TYPE_VEC_SHIFT 0 +#define POLICERS_CFGS_PL_CALC_TYPE_VEC_MASK 0xffffffff + + +/* + * Register + * + * periodic update parameters + */ +#define CNPL_POLICERS_CFGS_PER_UP 0x4120 + +/* + * period in 8k cycles quanta (16. + * 384us for 500MHz) +*/ +#define POLICERS_CFGS_PER_UP_N_SHIFT 0 +#define POLICERS_CFGS_PER_UP_N_MASK 0xff + +/* + * 1: + * enable periodic update0: + * disable periodic update +*/ +#define POLICERS_CFGS_PER_UP_EN_MASK 0x100 + + +/* + * Register + * + * arbiter sw priorities + */ +#define CNPL_MISC_ARB_PRM 0x4200 + +/* + * 0: + * fixed lower1: + * rr with fw (default)2: + * fixed higher +*/ +#define MISC_ARB_PRM_SW_PRIO_SHIFT 0 +#define MISC_ARB_PRM_SW_PRIO_MASK 0x3 + + +/* + * Register + * + * command register + */ +#define CNPL_SW_IF_SW_CMD 0x4300 + +/* value of register */ +#define SW_IF_SW_CMD_VAL_SHIFT 0 +#define SW_IF_SW_CMD_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * status register + */ +#define CNPL_SW_IF_SW_STAT 0x4304 + +/* + * 0: + * DONE (ready)1: + * PROC(not ready) +*/ +#define SW_IF_SW_STAT_CN_RD_ST_MASK 0x1 + +/* + * 0: + * DONE (ready)1: + * PROC(not ready) +*/ +#define SW_IF_SW_STAT_PL_PLC_ST_MASK 0x2 + +/* + * 0: + * DONE (ready)1: + * PROC(not ready) +*/ +#define SW_IF_SW_STAT_PL_RD_ST_MASK 0x4 + + +/* + * Register - read-only + * + * rdata register - policer command result + */ +#define CNPL_SW_IF_SW_PL_RSLT 0x4310 + +/* red, yellow, green, non-active */ +#define SW_IF_SW_PL_RSLT_COL_SHIFT 30 +#define SW_IF_SW_PL_RSLT_COL_MASK 0xc0000000 + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * rdata register - policer read command result. + * 2 register for 2 buckets. + * If the group has only one bucket per policer - the policers are returned + * in the registers as a full line: + * the even policers are in reg0 (0,2,4,. + * .), and the odd are in reg1. + */ +#define CNPL_SW_IF_SW_PL_RD(x) (0x4314 + (x) * 0x4) + +/* value of read data */ +#define SW_IF_SW_PL_RD_RD_SHIFT 0 +#define SW_IF_SW_PL_RD_RD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * rdata register - counters read command result. + * 8 register for 32B batch. + * In read of single counter (burst size=1) the output will be in reg0 (the + * 32b where the counter is). + * In read of burst of counters, the counters are returned in the registers + * as a full line: + * addr[2: + * 0]=0 section of line in reg0,2,4,6 and the addr[2: + * 0]=4 are in reg1,3,5,7 (this means that if the start of burst is at + * addr[2: + * 0]=4 section of line, the wanted output should be from reg1). + */ +#define CNPL_SW_IF_SW_CNT_RD(x) (0x4320 + (x) * 0x4) + +/* value of read data */ +#define SW_IF_SW_CNT_RD_RD_SHIFT 0 +#define SW_IF_SW_CNT_RD_RD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 10 ] - read-only + * + * Number of commands that were processed by the engine. + */ +#define CNPL_PM_COUNTERS_ENG_CMDS(x) (0x4400 + (x) * 0x4) + +/* value */ +#define PM_COUNTERS_ENG_CMDS_VAL_SHIFT 0 +#define PM_COUNTERS_ENG_CMDS_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Number of wait cycles that the command waited until there was an idle + * engine. + */ +#define CNPL_PM_COUNTERS_CMD_WAIT(x) (0x4440 + (x) * 0x4) + +/* value */ +#define PM_COUNTERS_CMD_WAIT_VAL_SHIFT 0 +#define PM_COUNTERS_CMD_WAIT_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles from last read clear + */ +#define CNPL_PM_COUNTERS_TOT_CYC 0x4450 + +/* value */ +#define PM_COUNTERS_TOT_CYC_VAL_SHIFT 0 +#define PM_COUNTERS_TOT_CYC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles that there was gnt from main arbiter + */ +#define CNPL_PM_COUNTERS_GNT_CYC 0x4454 + +/* value */ +#define PM_COUNTERS_GNT_CYC_VAL_SHIFT 0 +#define PM_COUNTERS_GNT_CYC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles that there was gnt with request of more than one agent + */ +#define CNPL_PM_COUNTERS_ARB_CYC 0x4458 + +/* value */ +#define PM_COUNTERS_ARB_CYC_VAL_SHIFT 0 +#define PM_COUNTERS_ARB_CYC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * errors in policer update: + * the update period finished, and not all policers have been updated yet. + */ +#define CNPL_PM_COUNTERS_PL_UP_ERR 0x4460 + +/* value */ +#define PM_COUNTERS_PL_UP_ERR_VAL_SHIFT 0 +#define PM_COUNTERS_PL_UP_ERR_VAL_MASK 0xffffffff + + +/* + * Register + * + * bits rd_clr and wrap for the pm counters(above) + */ +#define CNPL_PM_COUNTERS_GEN_CFG 0x44fc + +/* read clear bit */ +#define PM_COUNTERS_GEN_CFG_RD_CLR_MASK 0x1 + +/* read clear bit */ +#define PM_COUNTERS_GEN_CFG_WRAP_MASK 0x2 + + +/* + * Register + * + * selects the debug vecore + */ +#define CNPL_DEBUG_DBGSEL 0x4500 + +/* selects th debug vector */ +#define DEBUG_DBGSEL_VS_SHIFT 0 +#define DEBUG_DBGSEL_VS_MASK 0x7f + + +/* + * Register - read-only + * + * the debug bus + */ +#define CNPL_DEBUG_DBGBUS 0x4504 + +/* debug vector */ +#define DEBUG_DBGBUS_VB_SHIFT 0 +#define DEBUG_DBGBUS_VB_MASK 0x1fffff + + +/* + * Register - read-only + * + * vector of all the requests of the clients (tx fifo not empty) + */ +#define CNPL_DEBUG_REQ_VEC 0x4508 + +/* still more commands for arbitration */ +#define DEBUG_REQ_VEC_REQ_SHIFT 0 +#define DEBUG_REQ_VEC_REQ_MASK 0x7f + + +/* + * Register - read-only + * + * which counter is updated, and where are we in the period cycle + */ +#define CNPL_DEBUG_POL_UP_ST 0x4510 + +/* number of iteration we are(each represent 8192 cycles) */ +#define DEBUG_POL_UP_ST_ITR_NUM_SHIFT 0 +#define DEBUG_POL_UP_ST_ITR_NUM_MASK 0xff + +/* + * number of policer now updated. + * (80 means we finished updated of all policers for this period) +*/ +#define DEBUG_POL_UP_ST_POL_NUM_SHIFT 8 +#define DEBUG_POL_UP_ST_POL_NUM_MASK 0xff00 + + +#endif /* ! XRDP_REGS_CNPL_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_dma.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dma.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_dma.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dma.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,404 @@ +#ifndef XRDP_REGS_DMA_H_ +#define XRDP_REGS_DMA_H_ + +/* relative to core */ +#define DMA_OFFSET(x) (0xd98800 + (x) * 0x400) + +/* + * Register + * + * Broadbus route override + */ +#define DMA_CONFIG_BBROUTEOVRD 0x0 + +/* destination ID */ +#define CONFIG_BBROUTEOVRD_DEST_SHIFT 0 +#define CONFIG_BBROUTEOVRD_DEST_MASK 0x3f + +/* the route to be used (override the default route) */ +#define CONFIG_BBROUTEOVRD_ROUTE_SHIFT 8 +#define CONFIG_BBROUTEOVRD_ROUTE_MASK 0x3ff00 + +/* override enable */ +#define CONFIG_BBROUTEOVRD_OVRD_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers defines the memory allocation for the + * peripherals, for upstream. + * The allocation is of number of 128byte buffers out of the total 48 + * buffers for both sdma and dma. + * The allocation is done by defining a only the number of allocated + * buffers. + * base address is calculated by HW, when base of peripheral 0 is 0. + * Note that the memory allocation should not contain wrap around. + * The number of allocated CDs is the same of data buffers. + */ +#define DMA_CONFIG_NUM_OF_WRITES(x) (0x4 + (x) * 0x4) + +/* the number of 128bytes buffers allocated to the peripheral. */ +#define CONFIG_NUM_OF_WRITES_NUMOFBUFF_SHIFT 0 +#define CONFIG_NUM_OF_WRITES_NUMOFBUFF_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers controls the number of read requests of each + * peripheral within the read requests RAM. + * total of 64 requests are divided between peripherals. + * Base address of peripheral 0 is 0, base of peripheral 1 is 0 + + * periph0_num_of_read_requests and so on. + */ +#define DMA_CONFIG_NUM_OF_READS(x) (0x24 + (x) * 0x4) + +/* number of read requests */ +#define CONFIG_NUM_OF_READS_RR_NUM_SHIFT 0 +#define CONFIG_NUM_OF_READS_RR_NUM_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * the in/out of urgent thresholds mark the number of write requests in the + * queue in which the peripherals priority is changed. + * The two thresholds should create hysteresis. + * The moving into urgent threshold must always be greater than the moving + * out of urgent threshold. + */ +#define DMA_CONFIG_U_THRESH(x) (0x44 + (x) * 0x4) + +/* moving into urgent threshold */ +#define CONFIG_U_THRESH_INTO_U_SHIFT 0 +#define CONFIG_U_THRESH_INTO_U_MASK 0x3f + +/* moving out ot urgent threshold */ +#define CONFIG_U_THRESH_OUT_OF_U_SHIFT 8 +#define CONFIG_U_THRESH_OUT_OF_U_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The arbitration between the requests of the different peripherals is + * done in two stages: + * 1. + * Strict priority - chooses the peripherals with the highest priority + * among all perpherals who have a request pending. + * 2. + * Weighted Round-Robin between all peripherals with the same priority. + * This array of registers allow configuration of the priority of each + * peripheral (both rx and tx) in the following manner: + * There are 4 levels of priorities, when each bit in the register + * represents a different level of priority. + * One should assert the relevant bit according to the desired priority + * -For the lowest - 0001For the highest - 1000 + */ +#define DMA_CONFIG_PRI(x) (0x64 + (x) * 0x4) + +/* priority of rx side (upload) of the peripheral */ +#define CONFIG_PRI_RXPRI_SHIFT 0 +#define CONFIG_PRI_RXPRI_MASK 0xf + +/* priority of tx side (download) of the peripheral */ +#define CONFIG_PRI_TXPRI_SHIFT 4 +#define CONFIG_PRI_TXPRI_MASK 0xf0 + + +/* + * Registers - is [ 0 => 7 ] + * + * Broadbus source address of the DMA peripherals. + * Register per peripheral (rx and tx). + * The source is used to determine the route address to the different + * peripherals. + */ +#define DMA_CONFIG_PERIPH_SOURCE(x) (0x84 + (x) * 0x4) + +/* bb source of rx side (upload) of the peripheral */ +#define CONFIG_PERIPH_SOURCE_RXSOURCE_SHIFT 0 +#define CONFIG_PERIPH_SOURCE_RXSOURCE_MASK 0x3f + +/* bb source of tx side (download) of the peripheral */ +#define CONFIG_PERIPH_SOURCE_TXSOURCE_SHIFT 8 +#define CONFIG_PERIPH_SOURCE_TXSOURCE_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The second phase of the arbitration between requests is weighted round + * robin between requests of peripherals with the same priority. + * This array of registers allow configurtion of the weight of each + * peripheral (rx and tx). + * The actual weight will be weight + 1, meaning configuration of 0 is + * actual weight of 1. + */ +#define DMA_CONFIG_WEIGHT(x) (0xa4 + (x) * 0x4) + +/* weight of rx side (upload) of the peripheral */ +#define CONFIG_WEIGHT_RXWEIGHT_SHIFT 0 +#define CONFIG_WEIGHT_RXWEIGHT_MASK 0x7 + +/* weight of tx side (download) of the peripheral */ +#define CONFIG_WEIGHT_TXWEIGHT_SHIFT 8 +#define CONFIG_WEIGHT_TXWEIGHT_MASK 0x700 + + +/* + * Register + * + * Resets the pointers of the peripherals FIFOs within the DMA. + * Bit per peripheral side (rx and tx). + * For rx side resets the data and CD FIFOs. + * For tx side resets the read requests FIFO. + */ +#define DMA_CONFIG_PTRRST 0xd0 + +/* + * vector in which each bit represents a peripheral. + * LSB represent RX peripherals and MSB represent TX peripherals. + * When asserted, the relevant FIFOS of the selected peripheral will be + * reset to zero +*/ +#define CONFIG_PTRRST_RSTVEC_SHIFT 0 +#define CONFIG_PTRRST_RSTVEC_MASK 0xffff + + +/* + * Register + * + * max number of on the fly read commands the DMA may issue to DDR before + * receiving any data. + */ +#define DMA_CONFIG_MAX_OTF 0xd4 + +/* max on the fly */ +#define CONFIG_MAX_OTF_MAX_SHIFT 0 +#define CONFIG_MAX_OTF_MAX_MASK 0x3f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define DMA_CONFIG_CLK_GATE_CNTRL 0xd8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define CONFIG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define CONFIG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * debug bus select + */ +#define DMA_CONFIG_DBG_SEL 0xe0 + +/* select */ +#define CONFIG_DBG_SEL_DBGSEL_SHIFT 0 +#define CONFIG_DBG_SEL_DBGSEL_MASK 0x3 + + +/* + * Register - read-only + * + * Each peripheral is represented in a bit on the not empty vector. + * LSB is for rx peripherals, MSB for tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * not empty. + * The not empty vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define DMA_DEBUG_NEMPTY 0x100 + +/* indication of the queue state */ +#define DEBUG_NEMPTY_NEMPTY_SHIFT 0 +#define DEBUG_NEMPTY_NEMPTY_MASK 0xffff + + +/* + * Register - read-only + * + * Each peripheral, a is represented in a bit on the urgent vector. + * 8 LSB are rx peripherlas, 8 MSB are tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * in urgent state. + * The urgent vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define DMA_DEBUG_URGNT 0x104 + +/* indication whether the queue is in urgent state or not */ +#define DEBUG_URGNT_URGNT_SHIFT 0 +#define DEBUG_URGNT_URGNT_MASK 0xffff + + +/* + * Register - read-only + * + * The decision of the dma schedule rand the next peripheral to be served, + * represented by its source address + */ +#define DMA_DEBUG_SELSRC 0x108 + +/* the next peripheral to be served by the dma */ +#define DEBUG_SELSRC_SEL_SRC_SHIFT 0 +#define DEBUG_SELSRC_SEL_SRC_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of write requests currently pending for each rx peripheral. + */ +#define DMA_DEBUG_REQ_CNT_RX(x) (0x110 + (x) * 0x4) + +/* the number of pending write requests */ +#define DEBUG_REQ_CNT_RX_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_RX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of read requestscurrently pending for each TX peripheral. + */ +#define DMA_DEBUG_REQ_CNT_TX(x) (0x130 + (x) * 0x4) + +/* the number of pending read requests */ +#define DEBUG_REQ_CNT_TX_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_TX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of write requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define DMA_DEBUG_REQ_CNT_RX_ACC(x) (0x150 + (x) * 0x4) + +/* the number of pending write requests */ +#define DEBUG_REQ_CNT_RX_ACC_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_RX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of read requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define DMA_DEBUG_REQ_CNT_TX_ACC(x) (0x170 + (x) * 0x4) + +/* the number of pending write requests */ +#define DEBUG_REQ_CNT_TX_ACC_REQ_CNT_SHIFT 0 +#define DEBUG_REQ_CNT_TX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Register + * + * the address and cs of the ram the user wishes to read using the indirect + * access read mechanism. + */ +#define DMA_DEBUG_RDADD 0x200 + +/* address within the ram */ +#define DEBUG_RDADD_ADDRESS_SHIFT 0 +#define DEBUG_RDADD_ADDRESS_MASK 0x3ff + +/* chip select for write data ram */ +#define DEBUG_RDADD_DATACS_MASK 0x10000 + +/* chip select for chunk descriptors ram */ +#define DEBUG_RDADD_CDCS_MASK 0x20000 + +/* chip select for read requests ram */ +#define DEBUG_RDADD_RRCS_MASK 0x40000 + + +/* + * Register + * + * After determining the address and cs, the user should assert this bit + * for indicating that the address and cs are valid. + */ +#define DMA_DEBUG_RDVALID 0x204 + +/* indirect read request is valid */ +#define DEBUG_RDVALID_VALID_MASK 0x1 + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * The returned read data from the selected RAM. + * Array of 4 registers (128 bits total). + * The width of the different memories is as follows: + * write data - 128 bitschunk descriptors - 36 bitsread requests - 42 + * bitsread data - 64 bitsThe the memories with width smaller than 128, the + * data will appear in the first registers of the array, for example: + * data from the cd RAM will appear in - {reg1[5: + * 0], reg0[31: + * 0]}. + */ +#define DMA_DEBUG_RDDATA(x) (0x208 + (x) * 0x4) + +/* read data from ram */ +#define DEBUG_RDDATA_DATA_SHIFT 0 +#define DEBUG_RDDATA_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * When assertd indicats that the data in the previous array is valid. + * Willremain asserted until the user deasserts the valid bit in regiser + * RDVALID. + */ +#define DMA_DEBUG_RDDATARDY 0x218 + +/* read data ready */ +#define DEBUG_RDDATARDY_READY_MASK 0x1 + + +#endif /* ! XRDP_REGS_DMA_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_dqm.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dqm.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_dqm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dqm.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,424 @@ +#ifndef XRDP_REGS_DQM_H_ +#define XRDP_REGS_DQM_H_ + +/* relative to core */ +#define DQM_OFFSET_0 0x180034 + +/* + * Register + * + * Maximum number of entries in words for all the queues. + */ +#define DQM_MAX_ENTRIES_WORDS 0x0 + +/* + * Represents the maximum number of entries the queue can hold (in words). + * This is a global settings. +*/ +#define MAX_ENTRIES_WORDS_MAX_SHIFT 0 +#define MAX_ENTRIES_WORDS_MAX_MASK 0x7ffff + + +/* + * Register + * + * FPM Address Register + */ +#define DQM_FPM_ADDR 0x18 + +/* + * This is the FPM address to be used by components in this module. + * The same address is used to alloc and free a token in the FPM. +*/ +#define FPM_ADDR_FPMADDRESS_SHIFT 0 +#define FPM_ADDR_FPMADDRESS_MASK 0xffffffff + + +/* + * Register + * + * DQMOL Interrupt Status Register. + */ +#define DQM_IRQ_STS 0x1c + +/* + * DQMOL Pushing a Full Queue IRQ Status (RW1C). + * This is a sticky high bit and needs to be cleared by writing to it. +*/ +#define IRQ_STS_PUSHFULLQ_MASK 0x2 + +/* + * DQMOL Popping an Empty Queue IRQ Status (RW1C). + * This is a sticky high bit and needs to be cleared by writing to it. +*/ +#define IRQ_STS_POPEMPTYQ_MASK 0x1 + + +/* + * Register + * + * DQMOL Interrupt Mask Register. + */ +#define DQM_IRQ_MSK 0x20 + +/* DQMOL Pushing a Full Queue IRQ Mask */ +#define IRQ_MSK_PUSHFULLQ_MASK 0x2 + +/* DQMOL Popping an Empty Queue IRQ Mask */ +#define IRQ_MSK_POPEMPTYQ_MASK 0x1 + + +/* + * Register + * + * Token buffer size. + */ +#define DQM_BUF_SIZE 0x24 + +/* + * Buffer Size. + * This is an encoded value. + * 0 => 256 byte buffer, 1 => 512 byte buffer, 2 => 1024 byte buffer, 3 => + * 2048 byte buffer. +*/ +#define BUF_SIZE_POOL_0_SIZE_SHIFT 0 +#define BUF_SIZE_POOL_0_SIZE_MASK 0x3 + + +/* + * Register + * + * Token buffer base address + */ +#define DQM_BUF_BASE 0x28 + +/* + * Buffer base address for bits[39: + * 8]. + * Address bits [7: + * 0] is always assumed to be 0. +*/ +#define BUF_BASE_BASE_SHIFT 0 +#define BUF_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * Shows the number of tokens used by DQMOL + */ +#define DQM_TOKENS_USED 0x30 + +/* + * Represents the current number of tokens used by the queue data + * structure. + * This count does not include tokens that are prefetched. +*/ +#define TOKENS_USED_COUNT_SHIFT 0 +#define TOKENS_USED_COUNT_MASK 0xffffffff + + +/* + * Register + * + * counter for number of pushed transactions + */ +#define DQM_NUM_PUSHED 0x34 + +/* Represents the current number of pushed transaction across all queues */ +#define NUM_PUSHED_COUNT_SHIFT 0 +#define NUM_PUSHED_COUNT_MASK 0xffffffff + + +/* + * Register + * + * counter for number of popped transactions + */ +#define DQM_NUM_POPPED 0x38 + +/* Represents the current number of popped transaction across all queues */ +#define NUM_POPPED_COUNT_SHIFT 0 +#define NUM_POPPED_COUNT_MASK 0xffffffff + + +/* + * Register + * + * MUX Select for Diags + */ +#define DQM_DIAG_SEL 0x3c + +/* MUX Select for routing diag data to the Diag Data Register */ +#define DIAG_SEL_SEL_SHIFT 0 +#define DIAG_SEL_SEL_MASK 0xff + + +/* + * Register - read-only + * + */ +#define DQM_DIAG_DATA 0x40 + +/* data presented as diag readback data. */ +#define DIAG_DATA_DATA_SHIFT 0 +#define DIAG_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * DQMOL Interrupt Test Register. + */ +#define DQM_IRQ_TST 0x44 + +/* Test the PushFullQ irq */ +#define IRQ_TST_PUSHFULLQTST_MASK 0x2 + +/* Test the PopEmptyQ irq */ +#define IRQ_TST_POPEMPTYQTST_MASK 0x1 + + +/* + * Register - read-only + * + * content from prefetch token fifo + */ +#define DQM_TOKEN_FIFO_STATUS 0x48 + +/* token fifo full */ +#define TOKEN_FIFO_STATUS_FULL_MASK 0x20000 + +/* token fifo empty */ +#define TOKEN_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* token fifo depth count */ +#define TOKEN_FIFO_STATUS_LEVEL_SHIFT 8 +#define TOKEN_FIFO_STATUS_LEVEL_MASK 0x1f00 + +/* token fifo read pointer */ +#define TOKEN_FIFO_STATUS_RD_LOC_SHIFT 0 +#define TOKEN_FIFO_STATUS_RD_LOC_MASK 0xf + + +/* + * Registers - is [ 0 => 15 ] - read-only + * + * content from prefetch token fifo + */ +#define DQM_TOKEN_FIFO(x) (0x4c + (x) * 0x4) + +/* Token value read from the token fifo */ +#define TOKEN_FIFO_TOKEN_SHIFT 0 +#define TOKEN_FIFO_TOKEN_MASK 0xffffffff + + +/* + * Register + * + * counter for number of popped with no commit transactions + */ +#define DQM_NUM_POPPED_NO_COMMIT 0x8c + +/* + * Represents the current number of popped with no-commit transaction + * across all queues +*/ +#define NUM_POPPED_NO_COMMIT_COUNT_SHIFT 0 +#define NUM_POPPED_NO_COMMIT_COUNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * Number of token unused space available on queue. + * This register is available on the DSPRAM read bus. + */ +#define DQM_STATUS(x) (0x7cc + (x) * 0x4) + +/* Queue data for the current Line is stored locally in the QSM. */ +#define STATUS_CURR_LINE_DATA_IS_LOCAL_MASK 0x80000000 + +/* Queue data for the next Line is stored locally in the QSM. */ +#define STATUS_NEXT_LINE_DATA_IS_LOCAL_MASK 0x40000000 + +/* Queue Available Unused Token Space (in words). */ +#define STATUS_Q_AVL_TKN_SPACE_SHIFT 0 +#define STATUS_Q_AVL_TKN_SPACE_MASK 0x7ffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + */ +#define DQM_HEAD_PTR(x) (0xfcc + (x) * 0x8) + +/* + * Queue Head Pointer (in words). + * This is a read-only field and will reset to 0 whenever CNTRL_CFGB is + * programmed +*/ +#define HEAD_PTR_Q_HEAD_PTR_SHIFT 0 +#define HEAD_PTR_Q_HEAD_PTR_MASK 0xfffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + */ +#define DQM_TAIL_PTR(x) (0xfd0 + (x) * 0x8) + +/* + * Queue Tail Pointer (in words). + * This is a read-only field and will reset to 0 whenever CNTRL_CFGB is + * programmed +*/ +#define TAIL_PTR_Q_TAIL_PTR_SHIFT 0 +#define TAIL_PTR_Q_TAIL_PTR_MASK 0xfffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * Number of token space available in Queue + */ +#define DQM_DQMOL_SIZE(x) (0x1fcc + (x) * 0x20) + +/* Maximum number of entries allotted to the queue before it's full */ +#define DQMOL_SIZE_MAX_ENTRIES_SHIFT 4 +#define DQMOL_SIZE_MAX_ENTRIES_MASK 0x7ffff0 + +/* + * When set, this puts the DQM OL queue into legacy DQM mode, there's no + * offloading of data. + * All queue data are stored in the QSM memory. +*/ +#define DQMOL_SIZE_Q_DISABLE_OFFLOAD_MASK 0x8 + +/* + * Queue Token Size (in words). + * This is a base-0 value. + * A value of 0 means the token is 1 word long. + * A value of 1 means the token is 2 words long. + * This maxes out at a value of 3 to mean that a token is 4 words long. +*/ +#define DQMOL_SIZE_Q_TKN_SIZE_SHIFT 0 +#define DQMOL_SIZE_Q_TKN_SIZE_MASK 0x3 + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * Starting queue address and size of memory space + */ +#define DQM_DQMOL_CFGA(x) (0x1fd0 + (x) * 0x20) + +/* + * Queue Memory Size (in words). + * It is required that the Queue Memory Size be whole multiple of the + * QUEUE_x_CNTRL_SIZE. + * Q_TKN_SIZE. + * For example, if Q_TKN_SIZE == 2 (which represents a 3 word token), then + * the Queue Memory Size must be 3, 6, 9, 12, etc. +*/ +#define DQMOL_CFGA_Q_SIZE_SHIFT 16 +#define DQMOL_CFGA_Q_SIZE_MASK 0xffff0000 + +/* + * Queue Start Address (word addr). + * The hardware takes this word address and adds the base address of the + * Queue Shared Memory (0x4000 byte addr) to form the physical address for + * the Queue. +*/ +#define DQMOL_CFGA_Q_START_ADDR_SHIFT 0 +#define DQMOL_CFGA_Q_START_ADDR_MASK 0xffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Number of tokens and low watermark setting + */ +#define DQM_DQMOL_CFGB(x) (0x1fd4 + (x) * 0x20) + +/* When set, the DQMOL is enabled and ready for use. */ +#define DQMOL_CFGB_ENABLE_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_PUSHTOKEN(x) (0x1fdc + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_PUSHTOKEN_TOKEN_SHIFT 0 +#define DQMOL_PUSHTOKEN_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_PUSHTOKENNEXT(x) (0x1fe0 + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_PUSHTOKENNEXT_TOKEN_SHIFT 0 +#define DQMOL_PUSHTOKENNEXT_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_POPTOKEN(x) (0x1fe4 + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_POPTOKEN_TOKEN_SHIFT 0 +#define DQMOL_POPTOKEN_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * Current Token Register + */ +#define DQM_DQMOL_POPTOKENNEXT(x) (0x1fe8 + (x) * 0x20) + +/* + * Queue Token. + * This is the current token the offload hardware is using for this queue. +*/ +#define DQMOL_POPTOKENNEXT_TOKEN_SHIFT 0 +#define DQMOL_POPTOKENNEXT_TOKEN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15360 ] + * + * Note that in the UTP has 48KB of memory space. + * With DFAP/GFAP/DTP,there are only 16KB of shared memory space. + * The entirememory space is carved out here as a placeholder in the + * DFAP/GFAP/DTP's case. + * QSM memory + */ +#define DQM_QueueSharedMem_qsmdata(x) (0x1ffcc + (x) * 0x4) + +/* data */ +#define QueueSharedMem_qsmdata_DATA_SHIFT 0 +#define QueueSharedMem_qsmdata_DATA_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_DQM_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_dsptchr.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dsptchr.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_dsptchr.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_dsptchr.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,2288 @@ +#ifndef XRDP_REGS_DSPTCHR_H_ +#define XRDP_REGS_DSPTCHR_H_ + +/* relative to core */ +#define DSPTCHR_OFFSET_0 0xd80000 + +/* + * Register + * + * Enable of dispatcher reorder + */ +#define DSPTCHR_REORDER_CFG_DSPTCHR_REORDR_CFG 0x0 + +/* Enable dispatcher reorder block */ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_EN_MASK 0x1 + +/* Dispatcher reorder block is RDY */ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_RDY_MASK 0x100 + +/* + * Enables parallel operation of Re-Order scheduler to Re-Order SM. + * Reduces Re-Order cycle from 16 clocks to 7. +*/ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_REORDR_PAR_MOD_MASK 0x10000 + +/* Enable per Q Egress congestion monitoring */ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_PER_Q_EGRS_CONGST_EN_MASK 0x20000 + +/* + * Enables Enhanced performance mode of Dispatcher Load balancing and + * Dispatcher SM. + * This allows Disptach of PD to RNR instead of every 14 clocks, every 11 + * clocks. +*/ +#define REORDER_CFG_DSPTCHR_REORDR_CFG_DSPTCHR_PER_ENH_POD_MASK 0x40000 + + +/* + * Register + * + * Enable control for each VIQ/VEQ + */ +#define DSPTCHR_REORDER_CFG_VQ_EN 0x4 + +/* Enable Virtual Q control - 32 bit vector. */ +#define REORDER_CFG_VQ_EN_EN_SHIFT 0 +#define REORDER_CFG_VQ_EN_EN_MASK 0xffffffff + + +/* + * Register + * + * Allow override of a specific BB destination with a new Route ADDR + */ +#define DSPTCHR_REORDER_CFG_BB_CFG 0x8 + +/* Source ID - Dispatcher */ +#define REORDER_CFG_BB_CFG_SRC_ID_SHIFT 0 +#define REORDER_CFG_BB_CFG_SRC_ID_MASK 0x3f + +/* Enable dispatcher reorder block */ +#define REORDER_CFG_BB_CFG_DST_ID_OVRIDE_SHIFT 8 +#define REORDER_CFG_BB_CFG_DST_ID_OVRIDE_MASK 0x3f00 + +/* Use this route address instead of pre-configured */ +#define REORDER_CFG_BB_CFG_ROUTE_OVRIDE_SHIFT 16 +#define REORDER_CFG_BB_CFG_ROUTE_OVRIDE_MASK 0x3ff0000 + +/* Enable dispatcher reorder block */ +#define REORDER_CFG_BB_CFG_OVRIDE_EN_MASK 0x10000000 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define DSPTCHR_REORDER_CFG_CLK_GATE_CNTRL 0xc + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define REORDER_CFG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define REORDER_CFG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 31 ] + * + * Ingress Queues congestion state. + */ +#define DSPTCHR_CONGESTION_INGRS_CONGSTN(x) (0x80 + (x) * 0x4) + +/* First Level congestion threshold. */ +#define CONGESTION_INGRS_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_INGRS_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_INGRS_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_INGRS_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_INGRS_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_INGRS_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 31 ] + * + * Egress Queues congestion state per Q. + */ +#define DSPTCHR_CONGESTION_EGRS_CONGSTN(x) (0x100 + (x) * 0x4) + +/* First Level congestion threshold. */ +#define CONGESTION_EGRS_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_EGRS_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_EGRS_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_EGRS_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_EGRS_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_EGRS_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Register + * + * Egress congestion states (Total Count) + */ +#define DSPTCHR_CONGESTION_TOTAL_EGRS_CONGSTN 0x180 + +/* First Level congestion threshold. */ +#define CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_TOTAL_EGRS_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_TOTAL_EGRS_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_TOTAL_EGRS_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Register + * + * Congestion levels of FLL state. + * Once no mode BDs are availabe congestion indication will be risen on all + * PDs. + */ +#define DSPTCHR_CONGESTION_GLBL_CONGSTN 0x184 + +/* First Level congestion threshold. */ +#define CONGESTION_GLBL_CONGSTN_FRST_LVL_SHIFT 0 +#define CONGESTION_GLBL_CONGSTN_FRST_LVL_MASK 0xfff + +/* Second Level congestion threshold. */ +#define CONGESTION_GLBL_CONGSTN_SCND_LVL_SHIFT 12 +#define CONGESTION_GLBL_CONGSTN_SCND_LVL_MASK 0xfff000 + +/* + * Hystersis value in which to stop congestion indication. + * once reachin a congestion level only after crossing the (threshold_level + * - HYST_TRSH) will the congestion indication be removed +*/ +#define CONGESTION_GLBL_CONGSTN_HYST_THRS_SHIFT 24 +#define CONGESTION_GLBL_CONGSTN_HYST_THRS_MASK 0xff000000 + + +/* + * Register - read-only + * + * This register reflects the current congestion levels in the dispatcher. + */ +#define DSPTCHR_CONGESTION_CONGSTN_STATUS 0x188 + +/* Global congestion levels (according to FLL buffer availability) */ +#define CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_SHIFT 0 +#define CONGESTION_CONGSTN_STATUS_GLBL_CONGSTN_MASK 0x3 + +/* Global Egress congestion levels */ +#define CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_SHIFT 8 +#define CONGESTION_CONGSTN_STATUS_GLBL_EGRS_CONGSTN_MASK 0x300 + +/* SBPM congestion levels according to SPBM messages */ +#define CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_SHIFT 16 +#define CONGESTION_CONGSTN_STATUS_SBPM_CONGSTN_MASK 0x30000 + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_LOW 0x18c + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_INGRS_CONGSTN_LOW_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_INGRS_CONGSTN_HIGH 0x190 + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_INGRS_CONGSTN_HIGH_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_LOW 0x194 + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_EGRS_CONGSTN_LOW_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Note that this vector is only updated during the dispatch stage + */ +#define DSPTCHR_CONGESTION_PER_Q_EGRS_CONGSTN_HIGH 0x198 + +/* 1 - Passed Threshold0 - Did not pass threshold */ +#define CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_SHIFT 0 +#define CONGESTION_PER_Q_EGRS_CONGSTN_HIGH_CONGSTN_STATE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Ingress size + */ +#define DSPTCHR_INGRS_QUEUES_Q_INGRS_SIZE(x) (0x280 + (x) * 0x4) + +/* Common number of buffers allocated to this Q. */ +#define INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_SHIFT 0 +#define INGRS_QUEUES_Q_INGRS_SIZE_CMN_CNT_MASK 0x3ff + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Ingress Limits + */ +#define DSPTCHR_INGRS_QUEUES_Q_INGRS_LIMITS(x) (0x300 + (x) * 0x4) + +/* + * Maximum number of buffers allowed to be allocated to the specific VIQ + * from the common Pool +*/ +#define INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_SHIFT 0 +#define INGRS_QUEUES_Q_INGRS_LIMITS_CMN_MAX_MASK 0x3ff + +/* + * Maximum number of buffers allowed to be allocated to the specific VIQ + * from the guaranteed Pool +*/ +#define INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_SHIFT 10 +#define INGRS_QUEUES_Q_INGRS_LIMITS_GURNTD_MAX_MASK 0xffc00 + +/* + * Holds the value of the the accumulated credits. + * this is sent to the BBH/RNR. + * BBH disregards the value. + * RNR uses it to to calculate the amount of available credits. +*/ +#define INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_SHIFT 20 +#define INGRS_QUEUES_Q_INGRS_LIMITS_CREDIT_CNT_MASK 0xfff00000 + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Coherency counter + */ +#define DSPTCHR_INGRS_QUEUES_Q_INGRS_COHRENCY(x) (0x380 + (x) * 0x4) + +/* + * Coherency counter value. + * BBH sends a coherency message per PD. + * Coherency messages are counted and only if there is at least 1 coherency + * message can a PD be forwarded to the RNR for processing. +*/ +#define INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_SHIFT 0 +#define INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_CNT_MASK 0x3ff + +/* + * Enable coherency counting. + * In case RNR is allocated to a specific VIQ it will not send coherency + * messages so there is no need to take them into consideration during PD + * dispatch +*/ +#define INGRS_QUEUES_Q_INGRS_COHRENCY_CHRNCY_EN_MASK 0x400 + +/* Reserve */ +#define INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_SHIFT 11 +#define INGRS_QUEUES_Q_INGRS_COHRENCY_RSRV_MASK 0xfffff800 + + +/* + * Registers - is [ 0 => 31 ] + * + * Configuration for each Q including BB_ID, Target address, valid + */ +#define DSPTCHR_QUEUE_MAPPING_CRDT_CFG(x) (0x400 + (x) * 0x4) + +/* + * BroadBud ID: + * To which BroadBud agent (RNR/BBH) is the current Q associated with +*/ +#define QUEUE_MAPPING_CRDT_CFG_BB_ID_SHIFT 0 +#define QUEUE_MAPPING_CRDT_CFG_BB_ID_MASK 0xff + +/* + * Target address within the BB agent where the credit message should be + * written to. + * In case of RNR: + * 27:16 - Ram address + * 31:28 - Task number to wakeup +*/ +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_SHIFT 16 +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_MASK 0xffff0000 + +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_NORMAL 2 +#define QUEUE_MAPPING_CRDT_CFG_TRGT_ADD_EXCL 2 + +/* + * Registers - is [ 0 => 15 ] + * + * Dispatched address will be calculated ADD= BASE_ADD + (TASK_NUM x OFFSET) + * + */ +#define DSPTCHR_QUEUE_MAPPING_PD_DSPTCH_ADD(x) (0x480 + (x) * 0x4) + +/* Base address within each RNR, 8 bytes unit (1 == 0x8) */ +#define QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_SHIFT 0 +#define QUEUE_MAPPING_PD_DSPTCH_ADD_BASE_ADD_MASK 0xffff + +/* + * OFFSET address, in conjunction with base address for each task there + * will be a different address to where to send the PDADD = BASE_ADD + + * (OFFSET_ADD x TASK)PD size is 128bits + * + * 8 bytes unit +*/ +#define QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_SHIFT 16 +#define QUEUE_MAPPING_PD_DSPTCH_ADD_OFFSET_ADD_MASK 0xffff0000 + + +/* + * Register + * + * What is the destination of each VIQ. + * to Dispatcher and from there to Processing RNR or Reorder and from there + * to the QM + */ +#define DSPTCHR_QUEUE_MAPPING_Q_DEST 0x4c0 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q0_MASK 0x1 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q1_MASK 0x2 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q2_MASK 0x4 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q3_MASK 0x8 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q4_MASK 0x10 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q5_MASK 0x20 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q6_MASK 0x40 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q7_MASK 0x80 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q8_MASK 0x100 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q9_MASK 0x200 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q10_MASK 0x400 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q11_MASK 0x800 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q12_MASK 0x1000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q13_MASK 0x2000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q14_MASK 0x4000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q15_MASK 0x8000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q16_MASK 0x10000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q17_MASK 0x20000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q18_MASK 0x40000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q19_MASK 0x80000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q20_MASK 0x100000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q21_MASK 0x200000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q22_MASK 0x400000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q23_MASK 0x800000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q24_MASK 0x1000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q25_MASK 0x2000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q26_MASK 0x4000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q27_MASK 0x8000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q28_MASK 0x10000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q29_MASK 0x20000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q30_MASK 0x40000000 + +/* 0- Dispatcher1- Reorder */ +#define QUEUE_MAPPING_Q_DEST_Q31_MASK 0x80000000 + + +/* + * Register + * + * common pool max size + */ +#define DSPTCHR_POOL_SIZES_CMN_POOL_LMT 0x4d0 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_CMN_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_CMN_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * common pool size + */ +#define DSPTCHR_POOL_SIZES_CMN_POOL_SIZE 0x4d4 + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_CMN_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * Guaranteed pool max size + */ +#define DSPTCHR_POOL_SIZES_GRNTED_POOL_LMT 0x4d8 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_GRNTED_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * Guaranteed pool size + */ +#define DSPTCHR_POOL_SIZES_GRNTED_POOL_SIZE 0x4dc + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_GRNTED_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * Multi Cast pool max size + */ +#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_LMT 0x4e0 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_MULTI_CST_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * Multi Cast pool size + */ +#define DSPTCHR_POOL_SIZES_MULTI_CST_POOL_SIZE 0x4e4 + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_MULTI_CST_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * This counter counts the amount of buffers taken by runner for MultiCast + * purposes (or any other the requires adding new PDs to a Virtual Egress + * Queue - VEQ + */ +#define DSPTCHR_POOL_SIZES_RNR_POOL_LMT 0x4e8 + +/* MAX number of buffers allowed in the pool */ +#define POOL_SIZES_RNR_POOL_LMT_POOL_LMT_SHIFT 0 +#define POOL_SIZES_RNR_POOL_LMT_POOL_LMT_MASK 0x3ff + + +/* + * Register + * + * This counter counts the amount of buffers taken by runner for MultiCast + * purposes (or any other the requires adding new PDs to a Virtual Egress + * Qeueu - VEQ) + */ +#define DSPTCHR_POOL_SIZES_RNR_POOL_SIZE 0x4ec + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_RNR_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Register + * + * This counter counts how many buffers are currenly being handled by all + * RNRs + */ +#define DSPTCHR_POOL_SIZES_PRCSSING_POOL_SIZE 0x4f0 + +/* Number of buffers currently in the pool */ +#define POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_SHIFT 0 +#define POOL_SIZES_PRCSSING_POOL_SIZE_POOL_SIZE_MASK 0x3ff + + +/* + * Registers - is [ 0 => 63 ] + * + * Address 0 -> 255:224 + * Address 4 -> 223:192 + * Address 8 -> 191:160 + * Address C -> 159:128 + * Address 10 -> 127:96 + * Address 14 -> 95:64 + * Address 18 -> 63:32 + * Address 1C -> 31:0 + * + * 8 RG x 8 Regs per RG = 64 registers + */ +#define DSPTCHR_MASK_MSK_TSK_255_0(x) (0x500 + (x) * 0x4) + +/* MASK */ +#define MASK_MSK_TSK_255_0_MASK_SHIFT 0 +#define MASK_MSK_TSK_255_0_MASK_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] + * + * Queue Mask: + * Per RNR group holds a vector of which tasks are related to the group + */ +#define DSPTCHR_MASK_MSK_Q(x) (0x600 + (x) * 0x4) + +/* MASK */ +#define MASK_MSK_Q_MASK_SHIFT 0 +#define MASK_MSK_Q_MASK_MASK 0xffffffff + + +/* + * Register + * + * Describes which VEQ are part of the Delay Q group. + */ +#define DSPTCHR_MASK_DLY_Q 0x620 + +/* MASK */ +#define MASK_DLY_Q_MASK_SHIFT 0 +#define MASK_DLY_Q_MASK_MASK 0xffffffff + + +/* + * Register + * + * Describes which VEQ are part of the Non-Delay Q group. + */ +#define DSPTCHR_MASK_NON_DLY_Q 0x624 + +/* MASK */ +#define MASK_NON_DLY_Q_MASK_SHIFT 0 +#define MASK_NON_DLY_Q_MASK_MASK 0xffffffff + + +/* + * Register + * + * These registers hold the available credit for the Re-Order to sent PDs + * to the QM via Delay Q. + */ +#define DSPTCHR_EGRS_QUEUES_EGRS_DLY_QM_CRDT 0x630 + +/* + * The amount of free credits the re-order can utilize to send PDs to the + * QM +*/ +#define EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_SHIFT 0 +#define EGRS_QUEUES_EGRS_DLY_QM_CRDT_DLY_CRDT_MASK 0xff + + +/* + * Register + * + * These registers hold the available credit for the Re-Order to sent PDs + * to the QM via Non-Delay Q. + */ +#define DSPTCHR_EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT 0x634 + +/* + * The amount of free credits the re-order can utilize to send PDs to the + * QM +*/ +#define EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_SHIFT 0 +#define EGRS_QUEUES_EGRS_NON_DLY_QM_CRDT_NON_DLY_CRDT_MASK 0xff + + +/* + * Register + * + * Size of all egress queues. + * affected from PDs sent to dispatch and from multicast connect + */ +#define DSPTCHR_EGRS_QUEUES_TOTAL_Q_EGRS_SIZE 0x638 + +/* + * Accumulates all buffers that are marked as egress (after dispatch and + * before sending to QM) +*/ +#define EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_SHIFT 0 +#define EGRS_QUEUES_TOTAL_Q_EGRS_SIZE_TOTAL_EGRS_SIZE_MASK 0x3ff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Size of all egress queues. + * affected from PDs sent to dispatch and from multicast connect + */ +#define DSPTCHR_EGRS_QUEUES_PER_Q_EGRS_SIZE(x) (0x680 + (x) * 0x4) + +/* + * Accumulates all buffers that are marked as egress (after dispatch and + * before sending to QM) +*/ +#define EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_SHIFT 0 +#define EGRS_QUEUES_PER_Q_EGRS_SIZE_Q_EGRS_SIZE_MASK 0x3ff + + +/* + * Register + * + * Bit per queue, wakeup request from RNR to a specific Q. + * Once a wakeup request message is sent to dsptchr it will be latched + * until the amount of credits pass a threshold + */ +#define DSPTCHR_WAKEUP_CONTROL_WKUP_REQ 0x770 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q0_MASK 0x1 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q1_MASK 0x2 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q2_MASK 0x4 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q3_MASK 0x8 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q4_MASK 0x10 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q5_MASK 0x20 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q6_MASK 0x40 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q7_MASK 0x80 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q8_MASK 0x100 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q9_MASK 0x200 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q10_MASK 0x400 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q11_MASK 0x800 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q12_MASK 0x1000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q13_MASK 0x2000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q14_MASK 0x4000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q15_MASK 0x8000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q16_MASK 0x10000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q17_MASK 0x20000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q18_MASK 0x40000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q19_MASK 0x80000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q20_MASK 0x100000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q21_MASK 0x200000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q22_MASK 0x400000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q23_MASK 0x800000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q24_MASK 0x1000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q25_MASK 0x2000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q26_MASK 0x4000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q27_MASK 0x8000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q28_MASK 0x10000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q29_MASK 0x20000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q30_MASK 0x40000000 + +/* wakeup request pending */ +#define WAKEUP_CONTROL_WKUP_REQ_Q31_MASK 0x80000000 + + +/* + * Register + * + * Wakeup Thresholds in which to indicate RNR + */ +#define DSPTCHR_WAKEUP_CONTROL_WKUP_THRSHLD 0x774 + +/* + * Wakeup threshold. + * Once number of Guaranteed buffer count crosses the threshold and there + * is a pending wakeup request, the dispatcher will issue a wakeup message + * to the appropriate runner according to a predefind address configuration +*/ +#define WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_SHIFT 0 +#define WAKEUP_CONTROL_WKUP_THRSHLD_WKUP_THRSHLD_MASK 0x3ff + + +/* + * Registers - is [ 0 => 31 ] + * + * DWRR info per Q. + * including amount of credits per Q. + * If Q has below zero credits and Quantum size + */ +#define DSPTCHR_DISPTCH_SCHEDULING_DWRR_INFO(x) (0x780 + (x) * 0x4) + +/* + * availabe credits in bytes. + * Q will not be permitted to dispatch PDs if credit levels are below zero +*/ +#define DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_SHIFT 0 +#define DISPTCH_SCHEDULING_DWRR_INFO_Q_CRDT_MASK 0xfffff + +/* + * Bit will be enabled if credit levels are below zero. + * 2 compliment +*/ +#define DISPTCH_SCHEDULING_DWRR_INFO_NGTV_MASK 0x100000 + +/* + * Quantum size. + * Should be configured according to Q rate. + * in Bytes +*/ +#define DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_SHIFT 21 +#define DISPTCH_SCHEDULING_DWRR_INFO_QUNTUM_MASK 0xffe00000 + + +/* + * Register + * + * Queues with credits above zero. + * This will allow for the Q to participate in the scheduling round + */ +#define DSPTCHR_DISPTCH_SCHEDULING_VLD_CRDT 0x800 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q0_MASK 0x1 + +/* Valid Credits. */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q1_MASK 0x2 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q2_MASK 0x4 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q3_MASK 0x8 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q4_MASK 0x10 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q5_MASK 0x20 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q6_MASK 0x40 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q7_MASK 0x80 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q8_MASK 0x100 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q9_MASK 0x200 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q10_MASK 0x400 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q11_MASK 0x800 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q12_MASK 0x1000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q13_MASK 0x2000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q14_MASK 0x4000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q15_MASK 0x8000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q16_MASK 0x10000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q17_MASK 0x20000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q18_MASK 0x40000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q19_MASK 0x80000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q20_MASK 0x100000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q21_MASK 0x200000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q22_MASK 0x400000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q23_MASK 0x800000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q24_MASK 0x1000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q25_MASK 0x2000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q26_MASK 0x4000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q27_MASK 0x8000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q28_MASK 0x10000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q29_MASK 0x20000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q30_MASK 0x40000000 + +/* Valid Credits */ +#define DISPTCH_SCHEDULING_VLD_CRDT_Q31_MASK 0x80000000 + + +/* + * Register + * + * Selects which Load Balancing mechanism to use + */ +#define DSPTCHR_LOAD_BALANCING_LB_CFG 0x850 + +/* RoundRobin = 0StrictPriority = 1 */ +#define LOAD_BALANCING_LB_CFG_LB_MODE_MASK 0x1 + +/* + * Configures the threshold in which the LB mechanism opens activates a new + * RNR +*/ +#define LOAD_BALANCING_LB_CFG_SP_THRSHLD_SHIFT 8 +#define LOAD_BALANCING_LB_CFG_SP_THRSHLD_MASK 0x1f00 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0..15 belong to RNR 0 + * Tasks 16..32 Belong to RNR 1 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_0_1 0x860 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_0_1_RNR0_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_0_1_RNR0_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_0_1_RNR1_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_0_1_RNR1_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0..15 belong to RNR 2 + * Tasks 16..32 Belong to RNR 3 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_2_3 0x864 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_2_3_RNR2_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_2_3_RNR2_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_2_3_RNR3_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_2_3_RNR3_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 4Tasks 16. + * .32 Belong to RNR 5 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_4_5 0x868 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_4_5_RNR4_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_4_5_RNR4_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_4_5_RNR5_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_4_5_RNR5_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 6Tasks 16. + * .32 Belong to RNR 7 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_6_7 0x86c + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_6_7_RNR6_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_6_7_RNR6_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_6_7_RNR7_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_6_7_RNR7_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 8Tasks 16. + * .32 Belong to RNR 9 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_8_9 0x870 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_8_9_RNR8_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_8_9_RNR8_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_8_9_RNR9_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_8_9_RNR9_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 10Tasks 16. + * .32 Belong to RNR 11 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_10_11 0x874 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_10_11_RNR10_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_10_11_RNR10_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_10_11_RNR11_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_10_11_RNR11_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 12Tasks 16. + * .32 Belong to RNR 13 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_12_13 0x878 + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_12_13_RNR12_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_12_13_RNR12_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_12_13_RNR13_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_12_13_RNR13_MASK 0xffff0000 + + +/* + * Register + * + * Each bit indicates if the Task is Free for dispatch: + * Tasks 0. + * .15 belong to RNR 14Tasks 16. + * .32 Belong to RNR 15 + */ +#define DSPTCHR_LOAD_BALANCING_FREE_TASK_14_15 0x87c + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_14_15_RNR14_SHIFT 0 +#define LOAD_BALANCING_FREE_TASK_14_15_RNR14_MASK 0xffff + +/* Each bit indicats which task is Free for dispatch */ +#define LOAD_BALANCING_FREE_TASK_14_15_RNR15_SHIFT 16 +#define LOAD_BALANCING_FREE_TASK_14_15_RNR15_MASK 0xffff0000 + + +/* + * Registers - is [ 0 => 31 ] + * + * This ram is used to map each task to which group does it belong to. + */ +#define DSPTCHR_LOAD_BALANCING_TSK_TO_RG_MAPPING(x) (0x900 + (x) * 0x4) + +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSKx_SHIFT(x) ((x) * 3) + +/* + * Can be Task 0/8/16... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_SHIFT 0 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK0_MASK 0x7 + +/* + * Can be Task 1/9/17... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_SHIFT 3 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK1_MASK 0x38 + +/* + * Can be Task 2/10/18... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_SHIFT 6 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK2_MASK 0x1c0 + +/* + * Can be Task 3/11/19... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_SHIFT 9 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK3_MASK 0xe00 + +/* + * Can be Task 4/12/20... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_SHIFT 12 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK4_MASK 0x7000 + +/* + * Can be Task 5/13/21... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_SHIFT 15 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK5_MASK 0x38000 + +/* + * Can be Task 6/14/22... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_SHIFT 18 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK6_MASK 0x1c0000 + +/* + * Can be Task 7/15/23... +*/ +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_SHIFT 21 +#define LOAD_BALANCING_TSK_TO_RG_MAPPING_TSK7_MASK 0xe00000 + + +/* + * Register + * + * Available tasks in all runners related to a RNR Group. + * In case value is zero there are no tasks available for this RNR Group + * for dispatch hence it should be excluded from the next RNR Group + * selection + */ +#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_0_3 0x980 + +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_x_SHIFT(x) ((x) * 8) + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_SHIFT 0 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_0_MASK 0xff + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_SHIFT 8 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_1_MASK 0xff00 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_SHIFT 16 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_2_MASK 0xff0000 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_SHIFT 24 +#define LOAD_BALANCING_RG_AVLABL_TSK_0_3_TSK_CNT_RG_3_MASK 0xff000000 + + +/* + * Register + * + * Available tasks in all runners related to a RNR Group. + * In case value is zero there are no tasks available for this RNR Group + * for dispatch hence it should be excluded from the next RNR Group + * selection + */ +#define DSPTCHR_LOAD_BALANCING_RG_AVLABL_TSK_4_7 0x984 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_SHIFT 0 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_4_MASK 0xff + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_SHIFT 8 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_5_MASK 0xff00 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_SHIFT 16 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_6_MASK 0xff0000 + +/* Counter the amount of available (free) tasks in a RNR Group */ +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_SHIFT 24 +#define LOAD_BALANCING_RG_AVLABL_TSK_4_7_TSK_CNT_RG_7_MASK 0xff000000 + + +/* + * Register + * + * This register contains the current active TM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR 0x990 + +/* Buffer returned to Fll */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_RETURN_BUF_MASK 0x1 + +/* Drop PD counted */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_CNT_DRP_MASK 0x2 + +/* Unknown message entered the dispatcher */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_UNKNWN_MSG_MASK 0x4 + +/* + * Number of buffers returned to FLL exceeds the pre-defined allocated + * buffer amount (due to linked list bug) +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_OVERFLOW_MASK 0x8 + +/* + * Number of buffers returned to FLL decreased under zero and reached a + * negative amount (due to linked list bug) +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISR_FLL_NEG_MASK 0x10 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM 0x994 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER 0x998 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR 0x99c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_0_ITR_IST_MASK 0xffffffff + + +/* + * Register + * + * This register contains the current active TM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR 0x9a0 + +/* New Entry added to Destination queue 0 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST0_INT_MASK 0x1 + +/* New Entry added to Destination queue 1 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST1_INT_MASK 0x2 + +/* New Entry added to Destination queue 2 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST2_INT_MASK 0x4 + +/* New Entry added to Destination queue 3 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST3_INT_MASK 0x8 + +/* New Entry added to Destination queue 4 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST4_INT_MASK 0x10 + +/* New Entry added to Destination queue 5 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST5_INT_MASK 0x20 + +/* New Entry added to Destination queue 6 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST6_INT_MASK 0x40 + +/* New Entry added to Destination queue 7 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST7_INT_MASK 0x80 + +/* New Entry added to Destination queue 8 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST8_INT_MASK 0x100 + +/* New Entry added to Destination queue 9 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST9_INT_MASK 0x200 + +/* New Entry added to Destination queue 10 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST10_INT_MASK 0x400 + +/* New Entry added to Destination queue 11 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST11_INT_MASK 0x800 + +/* New Entry added to Destination queue 12 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST12_INT_MASK 0x1000 + +/* New Entry added to Destination queue 13 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST13_INT_MASK 0x2000 + +/* New Entry added to Destination queue 14 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST14_INT_MASK 0x4000 + +/* New Entry added to Destination queue 15 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST15_INT_MASK 0x8000 + +/* New Entry added to Destination queue 16 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST16_INT_MASK 0x10000 + +/* New Entry added to Destination queue 17 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST17_INT_MASK 0x20000 + +/* New Entry added to Destination queue 18 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST18_INT_MASK 0x40000 + +/* New Entry added to Destination queue 19 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST19_INT_MASK 0x80000 + +/* New Entry added to Destination queue 20 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST20_INT_MASK 0x100000 + +/* New Entry added to Destination queue 21 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST21_INT_MASK 0x200000 + +/* New Entry added to Destination queue 22 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST22_INT_MASK 0x400000 + +/* New Entry added to Destination queue 23 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST23_INT_MASK 0x800000 + +/* New Entry added to Destination queue 24 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST24_INT_MASK 0x1000000 + +/* New Entry added to Destination queue 25 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST25_INT_MASK 0x2000000 + +/* New Entry added to Destination queue 26 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST26_INT_MASK 0x4000000 + +/* New Entry added to Destination queue 27 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST27_INT_MASK 0x8000000 + +/* New Entry added to Destination queue 28 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST28_INT_MASK 0x10000000 + +/* New Entry added to Destination queue 29 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST29_INT_MASK 0x20000000 + +/* New Entry added to Destination queue 30 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST30_INT_MASK 0x40000000 + +/* New Entry added to Destination queue 31 */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISR_QDEST31_INT_MASK 0x80000000 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM 0x9a4 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER 0x9a8 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define DSPTCHR_DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR 0x9ac + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_SHIFT 0 +#define DSPTCHER_REORDR_TOP_INTR_CTRL_1_ITR_IST_MASK 0xffffffff + + +/* + * Register + * + * Debug Bypass control + */ +#define DSPTCHR_DEBUG_DBG_BYPSS_CNTRL 0x9b0 + +/* Enable bypass mode */ +#define DEBUG_DBG_BYPSS_CNTRL_EN_BYP_MASK 0x1 + +/* What BBID to use for NON_DELAY Q when in Bypass mode */ +#define DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_SHIFT 8 +#define DEBUG_DBG_BYPSS_CNTRL_BBID_NON_DLY_MASK 0xff00 + +/* What BBID to use for DELAY Q when in Bypass mode */ +#define DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_SHIFT 16 +#define DEBUG_DBG_BYPSS_CNTRL_BBID_DLY_MASK 0xff0000 + + +/* + * Register + * + * Counts the amount of active Tasks in RNR + */ +#define DSPTCHR_DEBUG_GLBL_TSK_CNT_0_7 0x9b4 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_SHIFT 0 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_0_MASK 0xf + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_SHIFT 4 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_1_MASK 0xf0 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_SHIFT 8 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_2_MASK 0xf00 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_SHIFT 12 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_3_MASK 0xf000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_SHIFT 16 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_4_MASK 0xf0000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_SHIFT 20 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_5_MASK 0xf00000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_SHIFT 24 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_6_MASK 0xf000000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_SHIFT 28 +#define DEBUG_GLBL_TSK_CNT_0_7_TSK_CNT_RNR_7_MASK 0xf0000000 + + +/* + * Register + * + * Counts the amount of active Tasks in RNR + */ +#define DSPTCHR_DEBUG_GLBL_TSK_CNT_8_15 0x9b8 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_SHIFT 0 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_8_MASK 0xf + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_SHIFT 4 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_9_MASK 0xf0 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_SHIFT 8 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_10_MASK 0xf00 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_SHIFT 12 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_11_MASK 0xf000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_SHIFT 16 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_12_MASK 0xf0000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_SHIFT 20 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_13_MASK 0xf00000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_SHIFT 24 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_14_MASK 0xf000000 + +/* Counter the amount of active tasks */ +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_SHIFT 28 +#define DEBUG_GLBL_TSK_CNT_8_15_TSK_CNT_RNR_15_MASK 0xf0000000 + + +/* + * Register + * + * Debug bus control which vector to output to the top level + */ +#define DSPTCHR_DEBUG_DBG_BUS_CNTRL 0x9bc + +/* Selects with vector to output */ +#define DEBUG_DBG_BUS_CNTRL_DBG_SEL_SHIFT 0 +#define DEBUG_DBG_BUS_CNTRL_DBG_SEL_MASK 0x1f + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_0 0x9c0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_0_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_0_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_1 0x9c4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_1_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_1_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_2 0x9c8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_2_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_2_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_3 0x9cc + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_3_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_3_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_4 0x9d0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_4_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_4_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_5 0x9d4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_5_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_5_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_6 0x9d8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_6_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_6_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_7 0x9dc + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_7_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_7_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_8 0x9e0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_8_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_8_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_9 0x9e4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_9_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_9_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_10 0x9e8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_10_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_10_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_11 0x9ec + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_11_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_11_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_12 0x9f0 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_12_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_12_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_13 0x9f4 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_13_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_13_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_14 0x9f8 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_14_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_14_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_15 0x9fc + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_15_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_15_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_16 0xa00 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_16_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_16_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_17 0xa04 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_17_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_17_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_18 0xa08 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_18_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_18_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_19 0xa0c + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_19_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_19_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_20 0xa10 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_20_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_20_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_21 0xa14 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_21_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_21_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_22 0xa18 + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_22_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_22_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug vector mapped to registers + */ +#define DSPTCHR_DEBUG_DBG_VEC_23 0xa1c + +/* Debug bus vector value */ +#define DEBUG_DBG_VEC_23_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_DBG_VEC_23_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Register + * + * Controls which information to log + */ +#define DSPTCHR_DEBUG_STATISTICS_DBG_STTSTCS_CTRL 0xa70 + +/* Selects mode to log */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_SHIFT 0 +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_MODE_MASK 0x3 + +/* Enable statistics */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_EN_CNTRS_MASK 0x100 + +/* Clears all counters */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_CLR_CNTRS_MASK 0x200 + +/* Selects RNR to log */ +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_SHIFT 16 +#define DEBUG_STATISTICS_DBG_STTSTCS_CTRL_DBG_RNR_SEL_MASK 0xf0000 + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Debug counter + */ +#define DSPTCHR_DEBUG_STATISTICS_DBG_CNT(x) (0xa80 + (x) * 0x4) + +/* Debug bus vector value */ +#define DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_SHIFT 0 +#define DEBUG_STATISTICS_DBG_CNT_DBG_VEC_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Pointer to the first BD in the link list of this queue. + */ +#define DSPTCHR_QDES_HEAD(x) (0x2000 + (x) * 0x20) + +/* Pointer to the first BD in the link list of this queue. */ +#define QDES_HEAD_HEAD_SHIFT 0 +#define QDES_HEAD_HEAD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * 32 bit wrap around counter. + * Counts number of packets that left this queue since start of queue + * activity. + */ +#define DSPTCHR_QDES_BFOUT(x) (0x2004 + (x) * 0x20) + +/* + * 32 bit wrap around counter. + * Counts number of packets that left this queue since start of queue + * activity. +*/ +#define QDES_BFOUT_BFOUT_SHIFT 0 +#define QDES_BFOUT_BFOUT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * 32 bit wrap around counter. + * Counts number of packets that entered this queue since start of queue + * activity. + */ +#define DSPTCHR_QDES_BUFIN(x) (0x2008 + (x) * 0x20) + +/* + * 32 bit wrap around counter. + * Counts number of packets that entered this queue since start of queue + * activity. +*/ +#define QDES_BUFIN_BUFIN_SHIFT 0 +#define QDES_BUFIN_BUFIN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Pointer to the last BD in the linked list of this queue. + */ +#define DSPTCHR_QDES_TAIL(x) (0x200c + (x) * 0x20) + +/* Pointer to the last BD in the linked list of this queue. */ +#define QDES_TAIL_TAIL_SHIFT 0 +#define QDES_TAIL_TAIL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * If this bit is set then the first BD attached to this Q is a null BD. + * In this case, its Data Pointer field is not valid, but its Next BD + * pointer field is valid. + * When it is set, the NullBD field for this queue is not valid. + */ +#define DSPTCHR_QDES_FBDNULL(x) (0x2010 + (x) * 0x20) + +/* + * If this bit is set then the first BD attached to this Q is a null BD. + * In this case, its Data Pointer field is not valid, but its Next BD + * pointer field is valid. + * When it is set, the NullBD field for this queue is not valid. +*/ +#define QDES_FBDNULL_FBDNULL_MASK 0x1 + + +/* + * Registers - is [ 0 => 31 ] + * + * 32 bits index of a Null BD that belongs to this queue. + * Both the data buffer pointer and the next BD field are non valid. + * The pointer defines a memory allocation for a BD that might be used or + * not. + */ +#define DSPTCHR_QDES_NULLBD(x) (0x2014 + (x) * 0x20) + +/* + * 32 bits index of a Null BD that belongs to this queue. + * Both the data buffer pointer and the next BD field are non valid. + * The pointer defines a memory allocation for a BD that might be used or + * not. +*/ +#define QDES_NULLBD_NULLBD_SHIFT 0 +#define QDES_NULLBD_NULLBD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * number of entries available in queue. + * bufin - bfout + */ +#define DSPTCHR_QDES_BUFAVAIL(x) (0x2018 + (x) * 0x20) + +/* + * number of entries available in queue. + * bufin - bfout +*/ +#define QDES_BUFAVAIL_BUFAVAIL_SHIFT 0 +#define QDES_BUFAVAIL_BUFAVAIL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] + * + * Q Head Buffer, Used for the dispatching logic + */ +#define DSPTCHR_QDES_REG_Q_HEAD(x) (0x2600 + (x) * 0x4) + +/* Q HEAD */ +#define QDES_REG_Q_HEAD_HEAD_SHIFT 0 +#define QDES_REG_Q_HEAD_HEAD_MASK 0x3ff + + +/* + * Register + * + * This register will hold the for each VIQ if the Head of the Q is valid + * or not. + * These Queues are for Dispatch + */ +#define DSPTCHR_QDES_REG_VIQ_HEAD_VLD 0x2680 + +/* + * Q head valid. + * Each bit indicates for a specific VIQ if the head is valid or not +*/ +#define QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_SHIFT 0 +#define QDES_REG_VIQ_HEAD_VLD_VIQ_HEAD_VLD_MASK 0xffffffff + + +/* + * Register + * + * This register will hold for each VIQ if the Coherency counter is larger + * than zero. + */ +#define DSPTCHR_QDES_REG_VIQ_CHRNCY_VLD 0x2684 + +/* + * Q Coherency counter is valid. + * Each bit indicates for a specific VIQ if the there is more than one + * coherency message for that Q. + * meaning the head of the VIQ can be dispatched +*/ +#define QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_SHIFT 0 +#define QDES_REG_VIQ_CHRNCY_VLD_CHRNCY_VLD_MASK 0xffffffff + + +/* + * Register + * + * This register will hold the for each VEQ if the Head of the Q is valid + * or notThese Queues are for ReOrder + */ +#define DSPTCHR_QDES_REG_VEQ_HEAD_VLD 0x2688 + +/* + * Q head valid. + * Each bit indicates for a specific VIQ if the head is valid or not +*/ +#define QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_SHIFT 0 +#define QDES_REG_VEQ_HEAD_VLD_VIQ_HEAD_VLD_MASK 0xffffffff + + +/* + * Register + * + * Todays implementation does not require that QDES available buffer be + * different than zero. + * so this register controls whether or not to it should affect poping from + * the QDES or not + */ +#define DSPTCHR_QDES_REG_QDES_BUF_AVL_CNTRL 0x268c + +/* Should buf_avail in the QDES affect poping from head of linked list */ +#define QDES_REG_QDES_BUF_AVL_CNTRL_USE_BUF_AVL_MASK 0x1 + +/* Should buf_avail in the QDES affect poping from head of linked list */ +#define QDES_REG_QDES_BUF_AVL_CNTRL_DEC_BUFOUT_WHEN_MLTCST_MASK 0x2 + + +/* + * Register + * + * Pointer to the first BD in the link list of this queue. + */ +#define DSPTCHR_FLLDES_HEAD 0x2700 + +/* Pointer to the first BD in the link list of this queue. */ +#define FLLDES_HEAD_HEAD_SHIFT 0 +#define FLLDES_HEAD_HEAD_MASK 0xffffffff + + +/* + * Register + * + * 32 bit wrap around counter. + * Counts number of entries that left this queue since start of queue + * activity. + */ +#define DSPTCHR_FLLDES_BFOUT 0x2704 + +/* + * 32 bit wrap around counter. + * Counts number of entries that left this queue since start of queue + * activity. +*/ +#define FLLDES_BFOUT_COUNT_SHIFT 0 +#define FLLDES_BFOUT_COUNT_MASK 0xffffffff + + +/* + * Register + * + * 32 bit wrap around counter. + * Counts number of entries that entered this queue since start of queue + * activity. + */ +#define DSPTCHR_FLLDES_BFIN 0x2708 + +/* + * 32 bit wrap around counter. + * Counts number of entries that entered this queue since start of queue + * activity. +*/ +#define FLLDES_BFIN_BFIN_SHIFT 0 +#define FLLDES_BFIN_BFIN_MASK 0xffffffff + + +/* + * Register + * + * Pointer to the last BD in the linked list of this queue. + */ +#define DSPTCHR_FLLDES_TAIL 0x270c + +/* Pointer to the last BD in the linked list of this queue. */ +#define FLLDES_TAIL_TAIL_SHIFT 0 +#define FLLDES_TAIL_TAIL_MASK 0xffffffff + + +/* + * Register + * + * 32 bit counter that counts the number of packets arrived when there is + * no free BD in the FLL. + */ +#define DSPTCHR_FLLDES_FLLDROP 0x2710 + +/* + * 32 bit counter that counts the number of packets arrived when there is + * no free BD in the FLL. +*/ +#define FLLDES_FLLDROP_DRPCNT_SHIFT 0 +#define FLLDES_FLLDROP_DRPCNT_MASK 0xffffffff + + +/* + * Register + * + * Low threshold Interrupt. + * When number of bytes reach this level, then an interrupt is generated to + * the Host. + */ +#define DSPTCHR_FLLDES_LTINT 0x2714 + +/* + * Low threshold Interrupt. + * When number of bytes reach this level, then an interrupt is generated to + * the Host. +*/ +#define FLLDES_LTINT_MINBUF_SHIFT 0 +#define FLLDES_LTINT_MINBUF_MASK 0xffffffff + + +/* + * Register - read-only + * + * number of entries available in queue. + * bufin - bfout + */ +#define DSPTCHR_FLLDES_BUFAVAIL 0x2720 + +/* + * number of entries available in queue. + * bufin - bfout +*/ +#define FLLDES_BUFAVAIL_BUFAVAIL_SHIFT 0 +#define FLLDES_BUFAVAIL_BUFAVAIL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Save the MIN size of free BD in the system that has been recorded during + * work. + */ +#define DSPTCHR_FLLDES_FREEMIN 0x2724 + +/* minum value of free BD recorded */ +#define FLLDES_FREEMIN_FREEMIN_SHIFT 0 +#define FLLDES_FREEMIN_FREEMIN_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1023 ] + * + * This Memory holds the Buffer Descriptor (BD) entries. + */ +#define DSPTCHR_BDRAM_DATA(x) (0x3000 + (x) * 0x4) + +/* Data Buffer entry */ +#define BDRAM_DATA_DATA_SHIFT 2 +#define BDRAM_DATA_DATA_MASK 0xffc + + +/* + * Registers - is [ 0 => 4095 ] + * + * This memory holds the Packet descriptors. + */ +#define DSPTCHR_PDRAM_DATA(x) (0x4000 + (x) * 0x4) + +/* Data Buffer entry */ +#define PDRAM_DATA_DATA_SHIFT 0 +#define PDRAM_DATA_DATA_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_DSPTCHR_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_fpm.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_fpm.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_fpm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_fpm.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,1952 @@ +#ifndef XRDP_REGS_FPM_H_ +#define XRDP_REGS_FPM_H_ + +/* relative to core */ +#define FPM_OFFSET_0 0xa00000 + +/* + * Register + * + */ +#define FPM_FPM_CTL 0x0 + +/* + * Test port mux control bits used to drive test signals from different + * submodules. +*/ +#define FPM_CTL_TP_MUX_CNTRL_SHIFT 27 +#define FPM_CTL_TP_MUX_CNTRL_MASK 0xf8000000 + +/* + * Disabling check for index memory corrupt during alloc/free/mcast + * updates. + * This should be used for debug purposes only 0 = Enable memory corruption + * check (normal operation) 1 = Disable memory corruption check +*/ +#define FPM_CTL_MEM_CORRUPT_CHECK_DISABLE_MASK 0x2000000 + +/* + * Stop loading allocation fifo/cache with new tokens. + * This is should be used for debug purposes only 0 = Enable loading new + * tokens (normal operation) 1 = Disable loading new tokens +*/ +#define FPM_CTL_STOP_ALLOC_CACHE_LOAD_MASK 0x1000000 + +/* Enable POOL2 token allocation / deallocation 0 = Disabled 1 = Enabled */ +#define FPM_CTL_POOL2_ENABLE_MASK 0x20000 + +/* Enable POOL1 token allocation / deallocation 0 = Disabled 1 = Enabled */ +#define FPM_CTL_POOL1_ENABLE_MASK 0x10000 + +/* + * Set to 1 to hold the FPM Broadbus interface in reset. + * This is useful for maintaining a known state on that interface when + * Runner is powered down. +*/ +#define FPM_CTL_FPM_BB_SOFT_RESET_MASK 0x4000 + +/* + * Clear memory - Initialize all bits of the usage index array memory to + * zero's This is a self clearing bit. + * Once software writes a 1'b1 to enable, hardware initializes the memory + * and resets this bit back to 1'b0 at completion of initialization. + * Software can poll this bit and check for a value a zero that indicates + * initialization completion status +*/ +#define FPM_CTL_INIT_MEM_MASK 0x10 + +/* + * Clear memory - Initialize all bits of the usage index array memory to + * zero's This is a self clearing bit. + * Once software writes a 1'b1 to enable, hardware initializes the memory + * and resets this bit back to 1'b0 at completion of initialization. + * Software can poll this bit and check for a value a zero that indicates + * initialization completion status +*/ +#define FPM_CTL_INIT_MEM_POOL2_MASK 0x8 + + +/* + * Register + * + */ +#define FPM_FPM_CFG1 0x4 + +/* + * Index memory search method (For more info refer to FPM architecture wiki + * page) 0 = Method 1 1 = Method 2 +*/ +#define FPM_CFG1_POOL1_SEARCH_MODE_MASK 0x1 + + +/* + * Register + * + */ +#define FPM_FPM_WEIGHT 0x8 + +/* Weight assigned to each free to pool for DDR1 */ +#define FPM_WEIGHT_DDR1_FREE_WEIGHT_SHIFT 24 +#define FPM_WEIGHT_DDR1_FREE_WEIGHT_MASK 0xff000000 + +/* Weight assigned to each alloc from pool for DDR1 */ +#define FPM_WEIGHT_DDR1_ALLOC_WEIGHT_SHIFT 16 +#define FPM_WEIGHT_DDR1_ALLOC_WEIGHT_MASK 0xff0000 + +/* Weight assigned to each free to pool for DDR0 */ +#define FPM_WEIGHT_DDR0_FREE_WEIGHT_SHIFT 8 +#define FPM_WEIGHT_DDR0_FREE_WEIGHT_MASK 0xff00 + +/* Weight assigned to each alloc from pool for DDR0 */ +#define FPM_WEIGHT_DDR0_ALLOC_WEIGHT_SHIFT 0 +#define FPM_WEIGHT_DDR0_ALLOC_WEIGHT_MASK 0xff + + +/* + * Register + * + */ +#define FPM_FPM_BB_CFG 0xc + +/* + * Select pool/DDR to be used when FPM_BB allocates tokens 11 = reserved 10 + * = allocate from both pools 01 = pool1/DDR1 00 = pool0/DDR0 +*/ +#define FPM_BB_CFG_BB_DDR_SEL_SHIFT 0 +#define FPM_BB_CFG_BB_DDR_SEL_MASK 0x3 + + +/* + * Register + * + * Mask bits are active high and are disabled by default. + * Software enables desired bits as necessary + */ +#define FPM_POOL1_INTR_MSK 0x10 + +/* Expired token recovered interrupt mask. */ +#define POOL1_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_MASK 0x4000 + +/* Expired token detect interrupt mask. */ +#define POOL1_INTR_MSK_EXPIRED_TOKEN_DET_MSK_MASK 0x2000 + +/* Illegal token request interrupt mask. */ +#define POOL1_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_MASK 0x1000 + +/* Illegal/un-implemented register/memory space access interrupt mask. */ +#define POOL1_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_MASK 0x800 + +/* XON_STATE interrupt mask. */ +#define POOL1_INTR_MSK_XON_MSK_MASK 0x400 + +/* XOFF_STATE interrupt mask. */ +#define POOL1_INTR_MSK_XOFF_MSK_MASK 0x200 + +/* Index Memory corrupt interrupt mask. */ +#define POOL1_INTR_MSK_MEMORY_CORRUPT_MSK_MASK 0x100 + +/* Free or Mcast update on disabled pool interrupt mask . */ +#define POOL1_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_MASK 0x80 + +/* Token multi-cast value update request with index out-of-range. */ +#define POOL1_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x40 + +/* Token multi-cast value update request with invalid token. */ +#define POOL1_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_MASK 0x20 + +/* De-allocation token request with index out-of-range. */ +#define POOL1_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x10 + +/* De-allocation token request with invalid token. */ +#define POOL1_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_MASK 0x8 + +/* Usage Index Pool is fully allocated interrupt mask. */ +#define POOL1_INTR_MSK_POOL_FULL_MSK_MASK 0x4 + +/* De-Allocation FIFO Full Interrupt mask. */ +#define POOL1_INTR_MSK_FREE_FIFO_FULL_MSK_MASK 0x2 + +/* Allocation FIFO Full Interrupt mask. */ +#define POOL1_INTR_MSK_ALLOC_FIFO_FULL_MSK_MASK 0x1 + + +/* + * Register + * + * Interrupt bits are active high. + * When a bit in this register is set to 1 and the corresponding bit in + * interrupt mask register is set to 1, interrupt to CPU will occur. + * When set (1), interrupts bits can be cleared (0) by writing a 1 to the + * desired bit. + */ +#define FPM_POOL1_INTR_STS 0x14 + +/* + * Expired token recovered interrupt. + * This is set when an expired token has been recoveredand returned to pool + * as an available token. +*/ +#define POOL1_INTR_STS_EXPIRED_TOKEN_RECOV_STS_MASK 0x4000 + +/* + * Expired token detect interrupt. + * This is set when the token recovery logic detects a token that has been + * held for the entire duration of the aging timer. +*/ +#define POOL1_INTR_STS_EXPIRED_TOKEN_DET_STS_MASK 0x2000 + +/* + * Illegal token request interrupt. + * This will be active when the pool is disabled, there is a request for a + * new token and the alloc fifo for the selected token size is empty. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL1_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_MASK 0x1000 + +/* + * Illegal/un-implemented register/memory space access interrupt. + * This will be active when there is an attempt to read from an + * unimplemented register or memory space. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL1_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_MASK 0x800 + +/* + * Number of available tokens is greater than or equal to XON_THRESHOLD + * value in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL1_INTR_STS_XON_STATE_STS_MASK 0x400 + +/* + * Number of available tokens is less than or equal to XOFF_THRESHOLD value + * in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL1_INTR_STS_XOFF_STATE_STS_MASK 0x200 + +/* + * Index Memory is corrupted. + * During updates of the usage array, token manager checks if the use count + * and search tree value in the array has a legal value. + * If the use count or search tree value is not correct before updating, + * logic generates an error and interrupt. + * As long as the interrupt is active no more valid tokens will be + * allocated because this is a catastrophic error. + * Following are the two error conditions that are checked - 1. + * During search for a free token, a particular token use count value + * indicates it is allocated (use count is greater than 0), but + * corresponding upper level search tree value indicates the token is still + * available (with bit value of 1'b0, instead of 1'b1). + * This is an error. + * 2. + * During search for a free token, a particular token use count value + * indicates that it is free (use count is 0), but corresponding upper + * level search tree value indicates the token is not available (with bit + * value of 1'b1, instead of 1'b0). + * This is an error. +*/ +#define POOL1_INTR_STS_MEMORY_CORRUPT_STS_MASK 0x100 + +/* + * Free or Mcast update on disabled pool interrupt. + * This bit goes active when a free or multi-cast request is received and + * FPM is not enabled, i. + * e. + * , pool enable bit in FPM control register is not set to 1'b1. +*/ +#define POOL1_INTR_STS_POOL_DIS_FREE_MULTI_STS_MASK 0x80 + +/* + * Token multi-cast value update request with index out-of-range Interrupt. + * This is set when the token index is not aligned to the pool size. + * This is determined by examining the pool select field (bits[29: + * 28]) and the 3 lsbs of the token index (bits[14: + * 12]). + * There is no associated count for this error. + * Note: + * this error is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x40 + +/* + * Token multi-cast value update request with invalid token Interrupt. + * Invalid multi-cast token is determined when one or more the following + * conditions are met - 1. + * Incoming multi-cast request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming multi-cast request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming multi-cast request token has use count field (bit[6: + * 0]) set to zero 4. + * Incoming multi-cast request token entry in the usage array indicates it + * is not an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * 5. + * After updating the use count value, the new use count value exceeds 0x7E + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_MULTI_TOKEN_NO_VALID_STS_MASK 0x20 + +/* + * De-allocation token request with index out-of-range Interrupt. + * Free token index out of range is determined when one or more of the + * following conditions are met - 1. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 2. + * The buffer size indicated by the size field (bits[11: + * 0]) is greater than the size of the allocated token. + * There is no associated count for this error. + * Note: + * item 1 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x10 + +/* + * De-allocation token request with invalid token Interrupt. + * Invalid free token is determined when one or more the following + * conditions are met - 1. + * Incoming free request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming free request token entry in the usage array indicates it is not + * an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL1_INTR_STS_FREE_TOKEN_NO_VALID_STS_MASK 0x8 + +/* + * Usage Index Pool is fully allocated interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that token pool is fully allocated and there are no free + * tokens available. + * This bit will be active (high) as long as there no free tokens available + * to allocate. + * This bit is intended to be used for debug purpose only. +*/ +#define POOL1_INTR_STS_POOL_FULL_STS_MASK 0x4 + +/* + * De-Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that de-allocation FIFO is full with tokens needs to be + * freed and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL1_INTR_STS_FREE_FIFO_FULL_STS_MASK 0x2 + +/* + * Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that allocation FIFO is full with new tokens to be + * allocated and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL1_INTR_STS_ALLOC_FIFO_FULL_STS_MASK 0x1 + + +/* + * Register + * + * Software sets desired stall bits that upon corresponding active + * interrupt status will stall FPM from new allocation, de-allocation, and + * mcast update process. + * Listed below are the supported interrupt statuses 1. + * Invalid free token (bit[3] of interrupt status register 0x14) 2. + * Invalid free token with index out-of-range (bit[4] of interrupt status + * register 0x14) 3. + * Invalid mcast token (bit[5] of interrupt status register 0x14) 4. + * Invalid mcast token with index out-of-range (bit[6] of interrupt status + * register 0x14) 5. + * Memory corrupt status (bit[8] of interrupt status register 0x14) When + * state machine is stalled, registers and memory can still be accessed. + * Any new token allocation request will be serviced with valid tokens (if + * available in alloc cache) and invalid tokens (if alloc cache is empty). + * Any new de-allocation/mcast update requests will be either stored in + * de-allocation fifo (if there is space in free fifo) or dropped (if free + * fifo is full). + * Bit locations in this register matches the location of corrseponding + * interrupt status bits in register 0x14. + * To un-stall (enable) state machine interrupt status bits (in register + * 0x14) corresponding to these mask bits should be cleared. + * Stall mask bits are active high and are disabled by default. + * This is for debug purposes only. + */ +#define FPM_POOL1_STALL_MSK 0x18 + +/* Stall FPM on Index Memory corrupt interrupt status. */ +#define POOL1_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_MASK 0x100 + +/* + * Stall FPM on Token multi-cast value update request with index + * out-of-range interrupt status. +*/ +#define POOL1_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x40 + +/* + * Stall FPM on Token multi-cast value update request with invalid token + * interrupt status. +*/ +#define POOL1_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_MASK 0x20 + +/* + * Stall FPM on De-allocation token request with index out-of-range + * interrupt status. +*/ +#define POOL1_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x10 + +/* + * Stall FPM on De-allocation token request with invalid token interrupt + * status. +*/ +#define POOL1_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_MASK 0x8 + + +/* + * Register + * + * Mask bits are active high and are disabled by default. + * Software enables desired bits as necessary + */ +#define FPM_POOL2_INTR_MSK 0x1c + +/* Expired token recovered interrupt mask. */ +#define POOL2_INTR_MSK_EXPIRED_TOKEN_RECOV_MSK_MASK 0x4000 + +/* Expired token detect interrupt mask. */ +#define POOL2_INTR_MSK_EXPIRED_TOKEN_DET_MSK_MASK 0x2000 + +/* Illegal token request interrupt mask. */ +#define POOL2_INTR_MSK_ILLEGAL_ALLOC_REQUEST_MSK_MASK 0x1000 + +/* Illegal/un-implemented register/memory space access interrupt mask. */ +#define POOL2_INTR_MSK_ILLEGAL_ADDRESS_ACCESS_MSK_MASK 0x800 + +/* XON_STATE interrupt mask. */ +#define POOL2_INTR_MSK_XON_MSK_MASK 0x400 + +/* XOFF_STATE interrupt mask. */ +#define POOL2_INTR_MSK_XOFF_MSK_MASK 0x200 + +/* Index Memory corrupt interrupt mask. */ +#define POOL2_INTR_MSK_MEMORY_CORRUPT_MSK_MASK 0x100 + +/* Free or Mcast update on disabled pool interrupt mask . */ +#define POOL2_INTR_MSK_POOL_DIS_FREE_MULTI_MSK_MASK 0x80 + +/* Token multi-cast value update request with index out-of-range. */ +#define POOL2_INTR_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x40 + +/* Token multi-cast value update request with invalid token. */ +#define POOL2_INTR_MSK_MULTI_TOKEN_NO_VALID_MSK_MASK 0x20 + +/* De-allocation token request with index out-of-range. */ +#define POOL2_INTR_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_MSK_MASK 0x10 + +/* De-allocation token request with invalid token. */ +#define POOL2_INTR_MSK_FREE_TOKEN_NO_VALID_MSK_MASK 0x8 + +/* Usage Index Pool is fully allocated interrupt mask. */ +#define POOL2_INTR_MSK_POOL_FULL_MSK_MASK 0x4 + +/* De-Allocation FIFO Full Interrupt mask. */ +#define POOL2_INTR_MSK_FREE_FIFO_FULL_MSK_MASK 0x2 + +/* Allocation FIFO Full Interrupt mask. */ +#define POOL2_INTR_MSK_ALLOC_FIFO_FULL_MSK_MASK 0x1 + + +/* + * Register + * + * Interrupt bits are active high. + * When a bit in this register is set to 1 and the corresponding bit in + * interrupt mask register is set to 1, interrupt to CPU will occur. + * When set (1), interrupts bits can be cleared (0) by writing a 1 to the + * desired bit. + */ +#define FPM_POOL2_INTR_STS 0x20 + +/* + * Expired token recovered interrupt. + * This is set when an expired token has been recoveredand returned to pool + * as an available token. +*/ +#define POOL2_INTR_STS_EXPIRED_TOKEN_RECOV_STS_MASK 0x4000 + +/* + * Expired token detect interrupt. + * This is set when the token recovery logic detects a token that has been + * held for the entire duration of the aging timer. +*/ +#define POOL2_INTR_STS_EXPIRED_TOKEN_DET_STS_MASK 0x2000 + +/* + * Illegal token request interrupt. + * This will be active when the pool is disabled, there is a request for a + * new token and the alloc fifo for the selected token size is empty. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL2_INTR_STS_ILLEGAL_ALLOC_REQUEST_STS_MASK 0x1000 + +/* + * Illegal/un-implemented register/memory space access interrupt. + * This will be active when there is an attempt to read from an + * unimplemented register or memory space. + * Along with interrupt being sent an error reply packet will be sent out + * with o_ubus_error_out asserted. +*/ +#define POOL2_INTR_STS_ILLEGAL_ADDRESS_ACCESS_STS_MASK 0x800 + +/* + * Number of available tokens is greater than or equal to XON_THRESHOLD + * value in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL2_INTR_STS_XON_STATE_STS_MASK 0x400 + +/* + * Number of available tokens is less than or equal to XOFF_THRESHOLD value + * in XON/XOFF Threshold configuration register. + * This is a functional status bit, not an error status bit. + * Using this information FPM generates "backpressure" output signal that + * is used by other UBUS client logics to throttle its operation. + * For example, UNIMAC logic can use "backpressure" signal to transfer + * "PAUSE" Ethernet flow control packets to throttle incoming frames on + * Ethernet interface. +*/ +#define POOL2_INTR_STS_XOFF_STATE_STS_MASK 0x200 + +/* + * Index Memory is corrupted. + * During updates of the usage array, token manager checks if the use count + * and search tree value in the array has a legal value. + * If the use count or search tree value is not correct before updating, + * logic generates an error and interrupt. + * As long as the interrupt is active no more valid tokens will be + * allocated because this is a catastrophic error. + * Following are the two error conditions that are checked - 1. + * During search for a free token, a particular token use count value + * indicates it is allocated (use count is greater than 0), but + * corresponding upper level search tree value indicates the token is still + * available (with bit value of 1'b0, instead of 1'b1). + * This is an error. + * 2. + * During search for a free token, a particular token use count value + * indicates that it is free (use count is 0), but corresponding upper + * level search tree value indicates the token is not available (with bit + * value of 1'b1, instead of 1'b0). + * This is an error. +*/ +#define POOL2_INTR_STS_MEMORY_CORRUPT_STS_MASK 0x100 + +/* + * Free or Mcast update on disabled pool interrupt. + * This bit goes active when a free or multi-cast request is received and + * FPM is not enabled, i. + * e. + * , pool enable bit in FPM control register is not set to 1'b1. +*/ +#define POOL2_INTR_STS_POOL_DIS_FREE_MULTI_STS_MASK 0x80 + +/* + * Token multi-cast value update request with index out-of-range Interrupt. + * This is set when the token index is not aligned to the pool size. + * This is determined by examining the pool select field (bits[29: + * 28]) and the 3 lsbs of the token index (bits[14: + * 12]). + * There is no associated count for this error. + * Note: + * this error is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x40 + +/* + * Token multi-cast value update request with invalid token Interrupt. + * Invalid multi-cast token is determined when one or more the following + * conditions are met - 1. + * Incoming multi-cast request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming multi-cast request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming multi-cast request token has use count field (bit[6: + * 0]) set to zero 4. + * Incoming multi-cast request token entry in the usage array indicates it + * is not an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * 5. + * After updating the use count value, the new use count value exceeds 0x7E + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_MULTI_TOKEN_NO_VALID_STS_MASK 0x20 + +/* + * De-allocation token request with index out-of-range Interrupt. + * Free token index out of range is determined when one or more of the + * following conditions are met - 1. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 2. + * The buffer size indicated by the size field (bits[11: + * 0]) is greater than the size of the allocated token. + * There is no associated count for this error. + * Note: + * item 1 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_FREE_TOKEN_INDEX_OUT_OF_RANGE_STS_MASK 0x10 + +/* + * De-allocation token request with invalid token Interrupt. + * Invalid free token is determined when one or more the following + * conditions are met - 1. + * Incoming free request token has valid bit (bit[31]) set to 1'b0 2. + * Incoming free request token index is not aligned to the pool size + * indicated by the pool select field (bits[29: + * 28]) 3. + * Incoming free request token entry in the usage array indicates it is not + * an allocated token, i. + * e. + * , associated use count value for this count in the usage array is zero + * Note: + * item 2 is not checked if auto_pool_en is set. + * The auto_pool_en bit is always set when using the new token format + * without a pool select field. +*/ +#define POOL2_INTR_STS_FREE_TOKEN_NO_VALID_STS_MASK 0x8 + +/* + * Usage Index Pool is fully allocated interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that token pool is fully allocated and there are no free + * tokens available. + * This bit will be active (high) as long as there no free tokens available + * to allocate. + * This bit is intended to be used for debug purpose only. +*/ +#define POOL2_INTR_STS_POOL_FULL_STS_MASK 0x4 + +/* + * De-Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that de-allocation FIFO is full with tokens needs to be + * freed and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL2_INTR_STS_FREE_FIFO_FULL_STS_MASK 0x2 + +/* + * Allocation FIFO Full Interrupt. + * This is a functional status bit, not an error status bit. + * This indicates that allocation FIFO is full with new tokens to be + * allocated and will be active (high) as long as FIFO is full. + * This status is intended to be used for debug purpose only. +*/ +#define POOL2_INTR_STS_ALLOC_FIFO_FULL_STS_MASK 0x1 + + +/* + * Register + * + * Software sets desired stall bits that upon corresponding active + * interrupt status will stall FPM from new allocation, de-allocation, and + * mcast update process. + * Listed below are the supported interrupt statuses 1. + * Invalid free token (bit[3] of interrupt status register 0x14) 2. + * Invalid free token with index out-of-range (bit[4] of interrupt status + * register 0x14) 3. + * Invalid mcast token (bit[5] of interrupt status register 0x14) 4. + * Invalid mcast token with index out-of-range (bit[6] of interrupt status + * register 0x14) 5. + * Memory corrupt status (bit[8] of interrupt status register 0x14) When + * state machine is stalled, registers and memory can still be accessed. + * Any new token allocation request will be serviced with valid tokens (if + * available in alloc cache) and invalid tokens (if alloc cache is empty). + * Any new de-allocation/mcast update requests will be either stored in + * de-allocation fifo (if there is space in free fifo) or dropped (if free + * fifo is full). + * Bit locations in this register matches the location of corrseponding + * interrupt status bits in register 0x14. + * To un-stall (enable) state machine interrupt status bits (in register + * 0x14) corresponding to these mask bits should be cleared. + * Stall mask bits are active high and are disabled by default. + * This is for debug purposes only. + */ +#define FPM_POOL2_STALL_MSK 0x24 + +/* Stall FPM on Index Memory corrupt interrupt status. */ +#define POOL2_STALL_MSK_MEMORY_CORRUPT_STALL_MSK_MASK 0x100 + +/* + * Stall FPM on Token multi-cast value update request with index + * out-of-range interrupt status. +*/ +#define POOL2_STALL_MSK_MULTI_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x40 + +/* + * Stall FPM on Token multi-cast value update request with invalid token + * interrupt status. +*/ +#define POOL2_STALL_MSK_MULTI_TOKEN_NO_VALID_STALL_MSK_MASK 0x20 + +/* + * Stall FPM on De-allocation token request with index out-of-range + * interrupt status. +*/ +#define POOL2_STALL_MSK_FREE_TOKEN_INDEX_OUT_OF_RANGE_STALL_MSK_MASK 0x10 + +/* + * Stall FPM on De-allocation token request with invalid token interrupt + * status. +*/ +#define POOL2_STALL_MSK_FREE_TOKEN_NO_VALID_STALL_MSK_MASK 0x8 + + +/* + * Register + * + */ +#define FPM_POOL1_CFG1 0x40 + +/* + * Selects the size of the buffer to be used in the pool. + * All buffers must be the same size. + * 0 - 512 byte buffers 1 - 256 byte buffers all other values - reserved +*/ +#define POOL1_CFG1_FPM_BUF_SIZE_SHIFT 24 +#define POOL1_CFG1_FPM_BUF_SIZE_MASK 0x7000000 + + +/* + * Register + * + * This register sets the physical base address of this memory. + * The memory block should be the number of buffers times the buffer size. + * This is mainly used for multi-pool memory configuration. + * NOTE: + * POOL_BASE_ADDRESS[7: + * 2] and reserved[1: + * 0] field must be written with 0x00 in the BCM3382 because + * itstoken-to-address converter assumes the buffers start on a 2kB + * boundary. + */ +#define FPM_POOL1_CFG2 0x44 + +/* + * Buffer base address. + * 7: + * 2 must be 0x00. +*/ +#define POOL1_CFG2_POOL_BASE_ADDRESS_SHIFT 2 +#define POOL1_CFG2_POOL_BASE_ADDRESS_MASK 0xfffffffc + + +/* + * Register + * + * This register sets the physical base address of this memory. + * The memory block should be the number of buffers times the buffer size. + * This is mainly used for multi-pool memory configuration. + */ +#define FPM_POOL1_CFG3 0x48 + +/* + * Buffer base address. + * 7: + * 2 must be 0x00. +*/ +#define POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_SHIFT 2 +#define POOL1_CFG3_POOL_BASE_ADDRESS_POOL2_MASK 0xfffffffc + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free pool + * overflows and underflows. + * A overflow condition occurs when pool is empty, ie. + * , no tokens are allocated and free/mcast request is encountered. + * A underflow condition occurs when pool is full, ie. + * , there are no free tokens and a allocation request is encountered. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear both both counters. + */ +#define FPM_POOL1_STAT1 0x50 + +/* Free Pool overflow count */ +#define POOL1_STAT1_OVRFL_SHIFT 16 +#define POOL1_STAT1_OVRFL_MASK 0xffff0000 + +/* Free Pool underflow count */ +#define POOL1_STAT1_UNDRFL_SHIFT 0 +#define POOL1_STAT1_UNDRFL_MASK 0xffff + + +/* + * Register - read-only + * + * This read only register provide status of index memory, alloc & free + * cache/fifos. + * These are real time statuses and bits are not sticky. + * Write to any bits will have no effect. + */ +#define FPM_POOL1_STAT2 0x54 + +/* + * POOL is full This indicates that all tokens have been allocated and + * there no free tokens available. + * This bit will be active as long as all usage array is fully allocated. +*/ +#define POOL1_STAT2_POOL_FULL_MASK 0x80000000 + +/* FREE_FIFO is full. */ +#define POOL1_STAT2_FREE_FIFO_FULL_MASK 0x20000000 + +/* FREE_FIFO is empty */ +#define POOL1_STAT2_FREE_FIFO_EMPTY_MASK 0x10000000 + +/* ALLOC_FIFO is full */ +#define POOL1_STAT2_ALLOC_FIFO_FULL_MASK 0x8000000 + +/* ALLOC_FIFO is empty. */ +#define POOL1_STAT2_ALLOC_FIFO_EMPTY_MASK 0x4000000 + +/* + * Count of tokens available for allocation. + * This provides a count of number of free tokens that available for + * allocation in the usage array. + * This value is updated instantaneously as tokens are allocated or freed + * from the array. +*/ +#define POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_SHIFT 0 +#define POOL1_STAT2_NUM_OF_TOKENS_AVAILABLE_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free token + * requests with in-valid tokens When the counter values reaches maximum + * count, it will hold the max value and not increment the count value + * unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL1_STAT3 0x58 + +/* + * Count of de-allocate token requests with invalid tokens. + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[3] + * explanation in this document. +*/ +#define POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_SHIFT 0 +#define POOL1_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of multi-cast + * token update requests with in-valid tokens. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL1_STAT4 0x5c + +/* + * Count of multi-cast token update requests with either valid bit not set, + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[5] + * explanation in this document. +*/ +#define POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_SHIFT 0 +#define POOL1_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the alloc token that + * causes memory corrupt interrupt (intr[8]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL1_STAT5 0x60 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes memory corrupt interrupt active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value, in addition, memory corrupt + * status bit (bit[8]) in interrupt status register 0x14 should be cleared. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Buffer size in bytes +*/ +#define POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_SHIFT 0 +#define POOL1_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the free token that + * causes invalid free request or free token with index out-of-range + * interrupts (intr[3] or intr[4]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL1_STAT6 0x64 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL1_STAT6_INVALID_FREE_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[3] or intr[4] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are either zeros or + * can reflect the length of the packet associated with the freed token) + * Bit[30] - Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Reserved +*/ +#define POOL1_STAT6_INVALID_FREE_TOKEN_SHIFT 0 +#define POOL1_STAT6_INVALID_FREE_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the multi-cast token + * that causes invalid mcast request or mcast token with index out-of-range + * interrupts (intr[5] or intr[6]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL1_STAT7 0x68 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL1_STAT7_INVALID_MCAST_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[5] or intr[6] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11] - Mcast update type (refer to register 0x224[11]) + * Bit[10: + * 7] - Reserved Bit[6: + * 0] - Mcast value +*/ +#define POOL1_STAT7_INVALID_MCAST_TOKEN_SHIFT 0 +#define POOL1_STAT7_INVALID_MCAST_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This register allows software to read the lowest value the + * NUM_OF_TOKENS_AVAILABLE count reached since the last time it was + * cleared. + * Any write to this register will reset the value back to the maximum + * number of tokens (0x10000) + */ +#define FPM_POOL1_STAT8 0x6c + +/* Lowest value the NUM_OF_TOKENS_AVAIL count has reached. */ +#define POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_SHIFT 0 +#define POOL1_STAT8_TOKENS_AVAILABLE_LOW_WTMK_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free pool + * overflows and underflows. + * A overflow condition occurs when pool is empty, ie. + * , no tokens are allocated and free/mcast request is encountered. + * A underflow condition occurs when pool is full, ie. + * , there are no free tokens and a allocation request is encountered. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear both both counters. + */ +#define FPM_POOL2_STAT1 0x70 + +/* Free Pool overflow count */ +#define POOL2_STAT1_OVRFL_SHIFT 16 +#define POOL2_STAT1_OVRFL_MASK 0xffff0000 + +/* Free Pool underflow count */ +#define POOL2_STAT1_UNDRFL_SHIFT 0 +#define POOL2_STAT1_UNDRFL_MASK 0xffff + + +/* + * Register - read-only + * + * This read only register provide status of index memory, alloc & free + * cache/fifos. + * These are real time statuses and bits are not sticky. + * Write to any bits will have no effect. + */ +#define FPM_POOL2_STAT2 0x74 + +/* + * POOL is full This indicates that all tokens have been allocated and + * there no free tokens available. + * This bit will be active as long as all usage array is fully allocated. +*/ +#define POOL2_STAT2_POOL_FULL_MASK 0x80000000 + +/* FREE_FIFO is full. */ +#define POOL2_STAT2_FREE_FIFO_FULL_MASK 0x20000000 + +/* FREE_FIFO is empty */ +#define POOL2_STAT2_FREE_FIFO_EMPTY_MASK 0x10000000 + +/* ALLOC_FIFO is full */ +#define POOL2_STAT2_ALLOC_FIFO_FULL_MASK 0x8000000 + +/* ALLOC_FIFO is empty. */ +#define POOL2_STAT2_ALLOC_FIFO_EMPTY_MASK 0x4000000 + +/* + * Count of tokens available for allocation. + * This provides a count of number of free tokens that available for + * allocation in the usage array. + * This value is updated instantaneously as tokens are allocated or freed + * from the array. +*/ +#define POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_SHIFT 0 +#define POOL2_STAT2_NUM_OF_TOKENS_AVAILABLE_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of free token + * requests with in-valid tokens When the counter values reaches maximum + * count, it will hold the max value and not increment the count value + * unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL2_STAT3 0x78 + +/* + * Count of de-allocate token requests with invalid tokens. + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[3] + * explanation in this document. +*/ +#define POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_SHIFT 0 +#define POOL2_STAT3_NUM_OF_NOT_VALID_TOKEN_FREES_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the count of multi-cast + * token update requests with in-valid tokens. + * When the counter values reaches maximum count, it will hold the max + * value and not increment the count value unless it is cleared. + * Any write to this register will clear count value. + */ +#define FPM_POOL2_STAT4 0x7c + +/* + * Count of multi-cast token update requests with either valid bit not set, + * For more information on conditions under which this counter is + * incremented, refer to POOL1_INTR_STS register (offset 0x14) bit[5] + * explanation in this document. +*/ +#define POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_SHIFT 0 +#define POOL2_STAT4_NUM_OF_NOT_VALID_TOKEN_MULTI_MASK 0x3ffff + + +/* + * Register - read-only + * + * This read only register allows software to read the alloc token that + * causes memory corrupt interrupt (intr[8]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL2_STAT5 0x80 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes memory corrupt interrupt active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value, in addition, memory corrupt + * status bit (bit[8]) in interrupt status register 0x14 should be cleared. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Buffer size in bytes +*/ +#define POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_SHIFT 0 +#define POOL2_STAT5_MEM_CORRUPT_STS_RELATED_ALLOC_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the free token that + * causes invalid free request or free token with index out-of-range + * interrupts (intr[3] or intr[4]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL2_STAT6 0x84 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL2_STAT6_INVALID_FREE_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[3] or intr[4] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are either zeros or + * can reflect the length of the packet associated with the freed token) + * Bit[30] - Reserved Bit[29: + * 12] - Token Bit[11: + * 0] - Reserved +*/ +#define POOL2_STAT6_INVALID_FREE_TOKEN_SHIFT 0 +#define POOL2_STAT6_INVALID_FREE_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This read only register allows software to read the multi-cast token + * that causes invalid mcast request or mcast token with index out-of-range + * interrupts (intr[5] or intr[6]) to go active. + * This is for debug purposes only. + * Any write to this register will clear token value (makes all bits zero). + */ +#define FPM_POOL2_STAT7 0x88 + +/* + * This bit provides status of the token in bits[30: + * 0] of this register 0 = New token is not captured 1 = New token is + * captured +*/ +#define POOL2_STAT7_INVALID_MCAST_TOKEN_VALID_MASK 0x80000000 + +/* + * Token that causes intr[5] or intr[6] active. + * If there are multiple tokens that causes this error, only the first one + * is captured. + * To capture successive tokens that causes the error this register should + * be cleared by writing any random value. + * Bitmap for these bits is shown below (reserved bits are zeros) Bit[30] - + * Reserved Bit[29: + * 12] - Token Bit[11] - Mcast update type (refer to register 0x224[11]) + * Bit[10: + * 7] - Reserved Bit[6: + * 0] - Mcast value +*/ +#define POOL2_STAT7_INVALID_MCAST_TOKEN_SHIFT 0 +#define POOL2_STAT7_INVALID_MCAST_TOKEN_MASK 0x7fffffff + + +/* + * Register - read-only + * + * This register allows software to read the lowest value the + * NUM_OF_TOKENS_AVAILABLE count reached since the last time it was + * cleared. + * Any write to this register will reset the value back to the maximum + * number of tokens (0x10000) + */ +#define FPM_POOL2_STAT8 0x8c + +/* Lowest value the NUM_OF_TOKENS_AVAIL count has reached. */ +#define POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_SHIFT 0 +#define POOL2_STAT8_TOKENS_AVAILABLE_LOW_WTMK_MASK 0x3ffff + + +/* + * Register + * + */ +#define FPM_POOL1_XON_XOFF_CFG 0xc0 + +/* XON Threshold value */ +#define POOL1_XON_XOFF_CFG_XON_THRESHOLD_SHIFT 16 +#define POOL1_XON_XOFF_CFG_XON_THRESHOLD_MASK 0xffff0000 + +/* XOFF Threshold value */ +#define POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_SHIFT 0 +#define POOL1_XON_XOFF_CFG_XOFF_THRESHOLD_MASK 0xffff + + +/* + * Register + * + */ +#define FPM_FPM_NOT_EMPTY_CFG 0xd0 + +/* Threshold value for reasserting pool_not_empty to FPM_BB */ +#define FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_SHIFT 0 +#define FPM_NOT_EMPTY_CFG_NOT_EMPTY_THRESHOLD_MASK 0x3f + + +/* + * Register + * + */ +#define FPM_MEM_CTL 0x100 + +/* + * Write control bit for Usage index array memory. + * This is a self clearing bit, cleared by hardware to zero once memory + * write is complete. + * Software can write more locations if the bit value is zero +*/ +#define MEM_CTL_MEM_WR_MASK 0x80000000 + +/* + * Read control bit for Usage index array memory. + * This is a self clearing bit, cleared by hardware to zero once memory + * read is complete. + * Software can read more locations if the bit value is zero +*/ +#define MEM_CTL_MEM_RD_MASK 0x40000000 + +/* + * 2'b00 = Reserved 2'b01 = FPM Memory 2'b10 = Reserved 2'b11 = When memory + * is enabled, bit[31]=1, this value will allow a write to + * NUM_OF_TOKENS_AVAILABLE field [17: + * 0] in POOL1_STAT2 register (offset 0x54). + * This should be used for debug purposes only +*/ +#define MEM_CTL_MEM_SEL_SHIFT 28 +#define MEM_CTL_MEM_SEL_MASK 0x30000000 + +/* Memory address for write/read location This is DWord aligned address */ +#define MEM_CTL_MEM_ADDR_SHIFT 2 +#define MEM_CTL_MEM_ADDR_MASK 0x3fffc + + +/* + * Register + * + */ +#define FPM_MEM_DATA1 0x104 + +/* + * Memory Data 1 This contains the lower 32 bits (bits[31: + * 0]) of 32/64 bit data +*/ +#define MEM_DATA1_MEM_DATA1_SHIFT 0 +#define MEM_DATA1_MEM_DATA1_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_MEM_DATA2 0x108 + +/* + * Memory Data 2 This contains the upper 32 bits (bits[63: + * 32]) of 64 bit data. + * The value in this register should be ignored during 32 bit access +*/ +#define MEM_DATA2_MEM_DATA2_SHIFT 0 +#define MEM_DATA2_MEM_DATA2_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_TOKEN_RECOVER_CTL 0x130 + +/* + * This is a self-clearing bit. + * Write a 1 to the bit to reset the RECOVERED_TOKEN_COUNT to 0. +*/ +#define TOKEN_RECOVER_CTL_CLR_RECOVERED_TOKEN_COUNT_MASK 0x40 + +/* + * This is a self-clearing bit. + * Write a 1 to the bit to reset the EXPIRED_TOKEN_COUNT to 0. +*/ +#define TOKEN_RECOVER_CTL_CLR_EXPIRED_TOKEN_COUNT_MASK 0x20 + +/* + * Non-automated token recovery. + * This bit can be used when automatic token return is not enabled. + * When software gets an interrupt indicating that the token recovery + * process has detected expired tokens, it can set this bit to force the + * expired tokens to be reclaimed. + * 1 = Enabled 0 = Disabled +*/ +#define TOKEN_RECOVER_CTL_FORCE_TOKEN_RECLAIM_MASK 0x10 + +/* + * Enable automatic return of marked tokens to the freepool 1 = Enabled 0 = + * Disabled +*/ +#define TOKEN_RECOVER_CTL_TOKEN_RECLAIM_ENA_MASK 0x8 + +/* + * Enable remarking of tokens for multiple passes through the token + * recovery process. + * The mark bit is set on all tokens on the first pass through the loop. + * When this bit is set, the mark bits will be set again on all subsequent + * passes through the loop. + * It is anticipated that this bit will always be set when token recovery + * is enabled. + * It is provided as a potential debug tool. + * 1 = Enabled 0 = Disabled +*/ +#define TOKEN_RECOVER_CTL_TOKEN_REMARK_ENA_MASK 0x4 + +/* + * If token recovery is enabled, the single-pass control will indicate + * whether the hardware should perform just one iteration of the token + * recovery process or will continuously loop through the token recovery + * process. + * 1 = Single pass 0 = Auto repeat +*/ +#define TOKEN_RECOVER_CTL_SINGLE_PASS_ENA_MASK 0x2 + +/* Token recovery enable 1 = Enabled 0 = Disabled */ +#define TOKEN_RECOVER_CTL_TOKEN_RECOVER_ENA_MASK 0x1 + + +/* + * Register + * + */ +#define FPM_SHORT_AGING_TIMER 0x134 + +/* Aging timer used in token recovery */ +#define SHORT_AGING_TIMER_TIMER_SHIFT 0 +#define SHORT_AGING_TIMER_TIMER_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_LONG_AGING_TIMER 0x138 + +/* Aging timer used in token recovery */ +#define LONG_AGING_TIMER_TIMER_SHIFT 0 +#define LONG_AGING_TIMER_TIMER_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_CACHE_RECYCLE_TIMER 0x13c + +/* + * Timer used in token recovery logic. + * Upon expiration of timer, one token from the allocate cache will be + * freed. + * Over time, all cached tokens will be recycled back to the freepool. + * This will prevent the cached tokens frm being aged out by the token + * recovery logic. + * This timer should be set to a value so that all tokens can be recycled + * before the aging timer expires. +*/ +#define CACHE_RECYCLE_TIMER_RECYCLE_TIMER_SHIFT 0 +#define CACHE_RECYCLE_TIMER_RECYCLE_TIMER_MASK 0xffff + + +/* + * Register - read-only + * + */ +#define FPM_EXPIRED_TOKEN_COUNT_POOL1 0x140 + +/* + * Cumulative count of the number of expired tokens detected in the token + * recovery process. + * The count can be cleared by setting the CLR_EXPIRED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define EXPIRED_TOKEN_COUNT_POOL1_COUNT_SHIFT 0 +#define EXPIRED_TOKEN_COUNT_POOL1_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + */ +#define FPM_RECOVERED_TOKEN_COUNT_POOL1 0x144 + +/* + * Cumulative count of the number of expired tokens that were freed in the + * token recovery process. + * The count can be cleared by setting the CLR_RECOVERED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define RECOVERED_TOKEN_COUNT_POOL1_COUNT_SHIFT 0 +#define RECOVERED_TOKEN_COUNT_POOL1_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + */ +#define FPM_EXPIRED_TOKEN_COUNT_POOL2 0x148 + +/* + * Cumulative count of the number of expired tokens detected in the token + * recovery process. + * The count can be cleared by setting the CLR_EXPIRED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define EXPIRED_TOKEN_COUNT_POOL2_COUNT_SHIFT 0 +#define EXPIRED_TOKEN_COUNT_POOL2_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + */ +#define FPM_RECOVERED_TOKEN_COUNT_POOL2 0x14c + +/* + * Cumulative count of the number of expired tokens that were freed in the + * token recovery process. + * The count can be cleared by setting the CLR_RECOVERED_TOKEN_COUNT in the + * TOKEN_RECOVER_CTL register +*/ +#define RECOVERED_TOKEN_COUNT_POOL2_COUNT_SHIFT 0 +#define RECOVERED_TOKEN_COUNT_POOL2_COUNT_MASK 0xffffffff + + +/* + * Register + * + */ +#define FPM_TOKEN_RECOVER_START_END_POOL1 0x150 + +/* Start of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL1_START_INDEX_SHIFT 16 +#define TOKEN_RECOVER_START_END_POOL1_START_INDEX_MASK 0xfff0000 + +/* End of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL1_END_INDEX_SHIFT 0 +#define TOKEN_RECOVER_START_END_POOL1_END_INDEX_MASK 0xfff + + +/* + * Register + * + */ +#define FPM_TOKEN_RECOVER_START_END_POOL2 0x154 + +/* Start of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL2_START_INDEX_SHIFT 16 +#define TOKEN_RECOVER_START_END_POOL2_START_INDEX_MASK 0xfff0000 + +/* End of token index range to be used when performing token recovery. */ +#define TOKEN_RECOVER_START_END_POOL2_END_INDEX_SHIFT 0 +#define TOKEN_RECOVER_START_END_POOL2_END_INDEX_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL1_ALLOC_DEALLOC 0x400 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL1_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL1_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL1_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL1_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL1_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL1_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL2_ALLOC_DEALLOC 0x408 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL2_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL2_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL2_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL2_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL2_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL2_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL3_ALLOC_DEALLOC 0x410 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL3_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL3_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL3_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL3_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL3_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL3_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + * The free pool FIFO contains pointers to the buffers in the pool. + * To allocate a buffer from the pool, read token from this port. + * To de-allocate/free a buffer to the pool , write the token of the buffer + * to this port. + * After reset, software must initialize the FIFO. + * The buffer size is given in the control register above. + * All buffers must be of the same size and contiguous. + */ +#define FPM_POOL4_ALLOC_DEALLOC 0x418 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token is de-allocated/freed without this bit set that causes an + * error and the token will be ignored, error counter in register offset + * 0xB8 will be incremented. +*/ +#define POOL4_ALLOC_DEALLOC_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL4_ALLOC_DEALLOC_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL4_ALLOC_DEALLOC_TOKEN_INDEX_SHIFT 12 +#define POOL4_ALLOC_DEALLOC_TOKEN_INDEX_MASK 0x1ffff000 + +/* Buffer length or packet size in bytes */ +#define POOL4_ALLOC_DEALLOC_TOKEN_SIZE_SHIFT 0 +#define POOL4_ALLOC_DEALLOC_TOKEN_SIZE_MASK 0xfff + + +/* + * Register + * + */ +#define FPM_SPARE 0x420 + +#define SPARE_SPARE_BITS_SHIFT 0 +#define SPARE_SPARE_BITS_MASK 0xffffffff + +/* + * Register + * + * Update/Modify the multi-cast value of the token + */ +#define FPM_POOL_MULTI 0x424 + +/* + * Valid Token Indicator 0: + * No buffers available 1: + * A valid token index is provided. + * If a token multi-cast value is updated without this bit set, that causes + * an error and the token will be ignored, error counter in register offset + * 0xBC will be incremented. +*/ +#define POOL_MULTI_TOKEN_VALID_MASK 0x80000000 + +/* + * DDR Identifier 0: + * DDR0 1: + * DDR1 +*/ +#define POOL_MULTI_DDR_MASK 0x20000000 + +/* Buffer Index Pointer */ +#define POOL_MULTI_TOKEN_INDEX_SHIFT 12 +#define POOL_MULTI_TOKEN_INDEX_MASK 0x1ffff000 + +/* + * 1'b0 - Count value is replaced with new value in bits[6: + * 0] 1'b1 - Count value is incremented by value in bits[6: + * 0] +*/ +#define POOL_MULTI_UPDATE_TYPE_MASK 0x800 + +/* New Multi-cast Value */ +#define POOL_MULTI_TOKEN_MULTI_SHIFT 0 +#define POOL_MULTI_TOKEN_MULTI_MASK 0x7f + + +/* + * Register + * + * Write this register to force FPM_BB transaction + */ +#define FPM_FPM_BB_FORCE 0x30000 + +/* Write 1 to force BB transaction */ +#define FPM_BB_FORCE_FORCE_MASK 0x1 + + +/* + * Register + * + * Control to be sent on forced transaction + */ +#define FPM_FPM_BB_FORCED_CTRL 0x30004 + +/* Forced control */ +#define FPM_BB_FORCED_CTRL_CTRL_SHIFT 0 +#define FPM_BB_FORCED_CTRL_CTRL_MASK 0xfff + + +/* + * Register + * + * Address to be sent on forced transaction + */ +#define FPM_FPM_BB_FORCED_ADDR 0x30008 + +/* Forced TA address */ +#define FPM_BB_FORCED_ADDR_TA_ADDR_SHIFT 0 +#define FPM_BB_FORCED_ADDR_TA_ADDR_MASK 0xffff + +/* Forced destination address */ +#define FPM_BB_FORCED_ADDR_DEST_ADDR_SHIFT 16 +#define FPM_BB_FORCED_ADDR_DEST_ADDR_MASK 0x3f0000 + + +/* + * Register + * + * Data to be sent on forced transaction + */ +#define FPM_FPM_BB_FORCED_DATA 0x3000c + +/* Forced data */ +#define FPM_BB_FORCED_DATA_DATA_SHIFT 0 +#define FPM_BB_FORCED_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * set configuration for BB decoder + */ +#define FPM_FPM_BB_DECODE_CFG 0x30010 + +/* destination id */ +#define FPM_BB_DECODE_CFG_DEST_ID_SHIFT 0 +#define FPM_BB_DECODE_CFG_DEST_ID_MASK 0x3f + +/* Enable override */ +#define FPM_BB_DECODE_CFG_OVERRIDE_EN_MASK 0x40 + +/* route address */ +#define FPM_BB_DECODE_CFG_ROUTE_ADDR_SHIFT 7 +#define FPM_BB_DECODE_CFG_ROUTE_ADDR_MASK 0x1ff80 + + +/* + * Register + * + * Set SW addr to read FPM_BB FIFOs + */ +#define FPM_FPM_BB_DBG_CFG 0x30014 + +/* SW address for reading FPM BB RXFIFO */ +#define FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_SHIFT 0 +#define FPM_BB_DBG_CFG_RXFIFO_SW_ADDR_MASK 0xf + +/* SW address for reading FPM BB TXFIFO */ +#define FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_SHIFT 4 +#define FPM_BB_DBG_CFG_TXFIFO_SW_ADDR_MASK 0xf0 + +/* SW reset for FPM BB RXFIFO */ +#define FPM_BB_DBG_CFG_RXFIFO_SW_RST_MASK 0x100 + +/* SW reset for FPM BB TXFIFO */ +#define FPM_BB_DBG_CFG_TXFIFO_SW_RST_MASK 0x200 + + +/* + * Register - read-only + * + * Status of FPM BB RXFIFO + */ +#define FPM_FPM_BB_DBG_RXFIFO_STS 0x30018 + +/* FIFO is empty */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_EMPTY_MASK 0x1 + +/* FIFO is full */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_FULL_MASK 0x2 + +/* Used words */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_SHIFT 8 +#define FPM_BB_DBG_RXFIFO_STS_FIFO_USED_WORDS_MASK 0x1f00 + +/* Write counter */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_SHIFT 16 +#define FPM_BB_DBG_RXFIFO_STS_FIFO_RD_CNTR_MASK 0x1f0000 + +/* Write counter */ +#define FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_SHIFT 24 +#define FPM_BB_DBG_RXFIFO_STS_FIFO_WR_CNTR_MASK 0x1f000000 + + +/* + * Register - read-only + * + * Status of FPM BB TXFIFO + */ +#define FPM_FPM_BB_DBG_TXFIFO_STS 0x3001c + +/* FIFO is empty */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_EMPTY_MASK 0x1 + +/* FIFO is full */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_FULL_MASK 0x2 + +/* Used words */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_SHIFT 8 +#define FPM_BB_DBG_TXFIFO_STS_FIFO_USED_WORDS_MASK 0x1f00 + +/* Write counter */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_SHIFT 16 +#define FPM_BB_DBG_TXFIFO_STS_FIFO_RD_CNTR_MASK 0x1f0000 + +/* Write counter */ +#define FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_SHIFT 24 +#define FPM_BB_DBG_TXFIFO_STS_FIFO_WR_CNTR_MASK 0x1f000000 + + +/* + * Register - read-only + * + * Data from FPM BB RXFIFO bits [31: + * 0] + */ +#define FPM_FPM_BB_DBG_RXFIFO_DATA1 0x30020 + +/* data */ +#define FPM_BB_DBG_RXFIFO_DATA1_DATA_SHIFT 0 +#define FPM_BB_DBG_RXFIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB RXFIFO bits [39: + * 32] + */ +#define FPM_FPM_BB_DBG_RXFIFO_DATA2 0x30024 + +/* data */ +#define FPM_BB_DBG_RXFIFO_DATA2_DATA_SHIFT 0 +#define FPM_BB_DBG_RXFIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB TXFIFO bits [31: + * 0] + */ +#define FPM_FPM_BB_DBG_TXFIFO_DATA1 0x30028 + +/* data */ +#define FPM_BB_DBG_TXFIFO_DATA1_DATA_SHIFT 0 +#define FPM_BB_DBG_TXFIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB TXFIFO bits [63: + * 32] + */ +#define FPM_FPM_BB_DBG_TXFIFO_DATA2 0x3002c + +/* data */ +#define FPM_BB_DBG_TXFIFO_DATA2_DATA_SHIFT 0 +#define FPM_BB_DBG_TXFIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Data from FPM BB TXFIFO bits [79: + * 64] + */ +#define FPM_FPM_BB_DBG_TXFIFO_DATA3 0x30030 + +/* data */ +#define FPM_BB_DBG_TXFIFO_DATA3_DATA_SHIFT 0 +#define FPM_BB_DBG_TXFIFO_DATA3_DATA_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_FPM_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,91 @@ +#ifndef XRDP_REGS_H_ +#define XRDP_REGS_H_ + +enum { + BB_ID_FIRST = 0, + BB_ID_RNR0 = 0, /* 0x0 */ + BB_ID_RNR1 = 1, /* 0x1 */ + BB_ID_RNR2 = 2, /* 0x2 */ + BB_ID_RNR3 = 3, /* 0x3 */ + BB_ID_RNR4 = 4, /* 0x4 */ + BB_ID_RNR5 = 5, /* 0x5 */ + BB_ID_CNPL = 17, /* 0x11 */ + BB_ID_DISPATCHER_REORDER = 18, /* 0x12 */ + BB_ID_DMA0 = 19, /* 0x13 */ + BB_ID_SDMA0 = 21, /* 0x15 */ + BB_ID_SDMA1 = 22, /* 0x16 */ + BB_ID_FPM = 23, /* 0x17 */ + BB_ID_HASH = 24, /* 0x18 */ + BB_ID_NATC = 25, /* 0x19 */ + BB_ID_QM_CP_SDMA = 26, /* 0x1a */ + BB_ID_QM_RNR_GRID = 27, /* 0x1b */ + BB_ID_QM_BBHTX = 28, /* 0x1c */ + BB_ID_QM_TOP = 29, /* 0x1d */ + BB_ID_QM_CP_MACHINE = 30, /* 0x1e */ + BB_ID_RX_BBH_0 = 31, /* 0x1f */ + BB_ID_TX_LAN = 32, /* 0x20 */ + BB_ID_RX_BBH_1 = 33, /* 0x21 */ + BB_ID_RX_BBH_2 = 35, /* 0x23 */ + BB_ID_ACB = 47, /* 0x2f */ + BB_ID_SBPM = 48, /* 0x30 */ + BB_ID_TCAM_0 = 49, /* 0x31 */ + BB_ID_RX_PON = 50, /* 0x32 */ + BB_ID_TX_PON = 51, /* 0x33 */ + BB_ID_TX_PON_STAT = 52, /* 0x34 */ + BB_ID_RX_DSL = 53, /* 0x35 */ + BB_ID_TX_DSL = 54, /* 0x36 */ + BB_ID_TX_DSL_STAT = 55, /* 0x37 */ + BB_ID_RX_10G = 56, /* 0x38 */ + BB_ID_TX_10G = 57, /* 0x39 */ + BB_ID_RX_2P5 = 58, /* 0x3a */ + BB_ID_TX_2P5 = 59, /* 0x3b */ + BB_ID_LAST = 59 +}; + +#define BB_MSG_RNR_TO_BBH_TX_QUEUE_SHIFT 6 + + +enum xrdp_regs_area { + XRDP_AREA_CORE, + XRDP_AREA_WAN_TOP, +}; + +#define RNR_SRAM_OFFSET(x) (0x00c00000 + 0x20000 * (x)) +#define RNR_SRAM_SIZE (16 * 1024) + +#define RNR_INST_OFFSET(x) (0x00c10000 + 0x20000 * (x)) +#define RNR_INST_SIZE 32768 + +#define RNR_CNXT_OFFSET(x) (0x00c18000 + 0x20000 * (x)) +#define RNR_CNXT_SIZE 1536 + +#define RNR_PRED_OFFSET(x) (0x00c1c000 + 0x20000 * (x)) +#define RNR_PRED_SIZE 2048 + +#define RDP_PSRAM_OFFSET (0x600000) +#define RDP_PSRAM_SIZE (256 * 1024) + +/* relative to core */ +#define UNIMAC_OFFSET (0xda0000) + +#include "xrdp_regs_acb_if.h" +#include "xrdp_regs_bac_if.h" +#include "xrdp_regs_bbh_rx.h" +#include "xrdp_regs_bbh_tx.h" +#include "xrdp_regs_cnpl.h" +#include "xrdp_regs_dma.h" +#include "xrdp_regs_dqm.h" +#include "xrdp_regs_dsptchr.h" +#include "xrdp_regs_fpm.h" +#include "xrdp_regs_hash.h" +#include "xrdp_regs_natc.h" +#include "xrdp_regs_psram.h" +#include "xrdp_regs_qm.h" +#include "xrdp_regs_rnr_quad.h" +#include "xrdp_regs_rnr_regs.h" +#include "xrdp_regs_sbpm.h" +#include "xrdp_regs_tcam.h" +#include "xrdp_regs_ubus_mstr.h" +#include "xrdp_regs_ubus_slv.h" + +#endif /* XRDP_REGS_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_hash.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_hash.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_hash.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_hash.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,1039 @@ +#ifndef XRDP_REGS_HASH_H_ +#define XRDP_REGS_HASH_H_ + +/* relative to core */ +#define HASH_OFFSET_0 0xe20000 + +/* + * Register + * + * Power saving mode -detect that the accelerator has no activity and enter + * to power saving mode + */ +#define HASH_GENERAL_CFG_PWR_SAV_EN 0x0 + +/* . */ +#define HASH_GENERAL_CFG_PWR_SAV_EN_VALUE_MASK 0x1 + + +/* + * Register + * + * Determines the padding value added to keys according to the selected + * MASK + */ +#define HASH_GENERAL_CFG_PAD_HIGH 0x4 + +/* + * Determines the padding value added to keys according to the selected + * MASK +*/ +#define HASH_GENERAL_CFG_PAD_HIGH_VAL_SHIFT 0 +#define HASH_GENERAL_CFG_PAD_HIGH_VAL_MASK 0xfffffff + + +/* + * Register + * + * Determines the padding value added to keys according to the selected + * MASK + */ +#define HASH_GENERAL_CFG_PAD_LOW 0x8 + +/* + * Determines the padding value added to keys according to the selected + * MASK +*/ +#define HASH_GENERAL_CFG_PAD_LOW_VAL_SHIFT 0 +#define HASH_GENERAL_CFG_PAD_LOW_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * In case of multiple match this reg captures the hit indication per + * engine. + * This is a read clear reg. + */ +#define HASH_GENERAL_CFG_MULT_HIT_ERR 0xc + +/* + * In case of multiple match this reg captures the hit indication per + * engine. + * This is a read clear reg. +*/ +#define HASH_GENERAL_CFG_MULT_HIT_ERR_VAL_SHIFT 0 +#define HASH_GENERAL_CFG_MULT_HIT_ERR_VAL_MASK 0xf + + +/* + * Register + * + * Consist of chicken bit per specific fix + */ +#define HASH_GENERAL_CFG_UNDO_FIX 0x10 + +/* + * The bug fixed lacking in identification and reporting when a multiple + * hit occurs in the first search. +*/ +#define HASH_GENERAL_CFG_UNDO_FIX_FRST_MUL_HIT_MASK 0x1 + + +/* + * Register - read-only + * + * Number of key hitsThis reg is frozen when freeze bit asserted. + */ +#define HASH_PM_COUNTERS_HITS 0x100 + +/* . */ +#define HASH_PM_COUNTERS_HITS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HITS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of key searchesThis register is updated only when freeze register + * is not set + */ +#define HASH_PM_COUNTERS_SRCHS 0x104 + +/* . */ +#define HASH_PM_COUNTERS_SRCHS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_SRCHS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_MISS 0x108 + +/* . */ +#define HASH_PM_COUNTERS_MISS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_MISS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_1ST_ACS 0x10c + +/* . */ +#define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_1ST_ACS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_2ND_ACS 0x110 + +/* . */ +#define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_2ND_ACS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_3RD_ACS 0x114 + +/* . */ +#define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_3RD_ACS_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Total NUM of missesread clear registerupdated only when freeze reg is 0 + */ +#define HASH_PM_COUNTERS_HIT_4TH_ACS 0x118 + +/* . */ +#define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_SHIFT 0 +#define HASH_PM_COUNTERS_HIT_4TH_ACS_CNT_MASK 0xffffffff + + +/* + * Register + * + * Freezes counters update - used to read all relevant counters at the same + * point. + */ +#define HASH_PM_COUNTERS_FRZ_CNT 0x150 + +/* Freezes counters update */ +#define HASH_PM_COUNTERS_FRZ_CNT_VAL_MASK 0x1 + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table : + * Configuration of LUT: + * table params + main flag + */ +#define HASH_LKUP_TBL_CFG_TBL_CFG(x) (0x200 + (x) * 0x10) + +/* + * Base address of the hash ram per engine. + * Varies between 0 to 1535Indicates from which address start looking the + * key. + * Note, base address must be aligned to table size - table size of 128 + * cant get base 64 +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_SHIFT 0 +#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_BASE_ADDR_MASK 0x7ff + +/* + * Number of entries in the table per engine. + * Total entries should be multiplied with the number of engines - by 4. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_SHIFT 16 +#define HASH_LKUP_TBL_CFG_TBL_CFG_TBL_SIZE_MASK 0x70000 + +/* + * Max Search depth per engine. + * Supports up to 16 and cannot exceed table size. + * For performance requirement it should be limited to 4 +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_SHIFT 20 +#define HASH_LKUP_TBL_CFG_TBL_CFG_MAX_HOP_MASK 0xf00000 + +/* + * CAM Search is enabled. + * If the key not found in the hash table and this flag enabled the key + * will be searched in the CAm. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_CAM_EN_MASK 0x1000000 + +/* + * Direct lookup enable. + * Allows accessing the table without hash calculation- direct access. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_DIRECT_LKUP_EN_MASK 0x2000000 + +/* Hash function type */ +#define HASH_LKUP_TBL_CFG_TBL_CFG_HASH_TYPE_MASK 0x4000000 + +/* + * If the key smaller than 60 bit, then it supported to store in the + * remaining bits an internal context data 3B or 6B. +*/ +#define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_SHIFT 28 +#define HASH_LKUP_TBL_CFG_TBL_CFG_INT_CNTX_SIZE_MASK 0x30000000 + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table : + * key Mask on bits [59: + * 32]Key consist of 60-bit. + * by configuring mask the user can use different key lengths. + * if the key is smaller than 60 bit it is padded with constant value + * according the the mask register. + */ +#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH(x) (0x204 + (x) * 0x10) + +/* + * MASK HIGH applied on the 28 msb of the current part of key for the + * current search table. + * The value used for padding purpose and comparison to the hash content. +*/ +#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_SHIFT 0 +#define HASH_LKUP_TBL_CFG_KEY_MASK_HIGH_MASKH_MASK 0xfffffff + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table key Mask on bits [31: + * 0]Key consist of 60-bit. + * By configuring mask the user can use different key lengths. + * If the key is smaller than 60 bit it is padded with constant value + * according to the mask register. + */ +#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW(x) (0x208 + (x) * 0x10) + +/* + * MASK LOW applied on the 32 lsb of the current part of key for the + * current search table. + * The value used for padding purpose and comparison to the hash content. +*/ +#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_SHIFT 0 +#define HASH_LKUP_TBL_CFG_KEY_MASK_LOW_MASKL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] + * + * Look-up table: + * LUT Context Table configurations (base addr + entry context size) + */ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG(x) (0x20c + (x) * 0x10) + +/* + * Context table base address in the RAM (6Bytes X 3264entries) . + * Indicates from which address start looking at the context. + * The address varies between 0 to 3264 (including 196 CAM entries)It + * should be calculated according below formula: + * Context_base_addr[12: + * 0] = sum of (table_size_per_engine*num_of_eng*context_size)/6 for all + * preceding tables +*/ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_SHIFT 0 +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_BASE_ADDRESS_MASK 0xfff + +/* + * Indicates the first entry of the particular table in the context table. + * It should be calculated according to below formula: + * First_hash_index = sum of (table_size_per_engine*num_of_eng) for all + * preceding tables +*/ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_SHIFT 12 +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_FIRST_HASH_IDX_MASK 0x1fff000 + +/* + * Context entry size (in the context RAM). + * Varies between 0B to 12B in steps of 3BContext may also be extracted + * directly from Look-up Table (up to 6B). +*/ +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_SHIFT 28 +#define HASH_LKUP_TBL_CFG_CNTXT_CFG_CNXT_SIZE_MASK 0x70000000 + + +/* + * Register + * + * Look-up table: + * LUT Context Table configurations (base addr + entry context size) + */ +#define HASH_CAM_CFG_CNTXT_CFG 0x400 + +/* + * Context table base address in the RAM (6Bytes X 3264entries) . + * Indicates from which address start looking at the context. + * The address varies between 0 to 3264 (including 196 CAM entries)It + * should be calculated according below formula: + * Context_base_addr[12: + * 0] = sum of (table_size*context_size)/6 for all preceding tables +*/ +#define HASH_CAM_CFG_CNTXT_CFG_BASE_ADDRESS_SHIFT 0 +#define HASH_CAM_CFG_CNTXT_CFG_BASE_ADDRESS_MASK 0xfff + + +/* + * Register + * + * TCAM Operation: + * 0 - CAM READ1 - CAM Write2 - CAM Compare3 - CAM valid bit resetWriting + * to this register triggers the operation. + * All other relevant register should be ready before SW writes to this + * register. + */ +#define HASH_CAM_INDIRECT_OP 0x800 + +/* . */ +#define HASH_CAM_INDIRECT_OP_CMD_SHIFT 0 +#define HASH_CAM_INDIRECT_OP_CMD_MASK 0xf + + +/* + * Register - read-only + * + * Raised when the CAM operation is completed (cleared by HW on writing to + * the OPERATION register) + */ +#define HASH_CAM_INDIRECT_OP_DONE 0x804 + +/* . */ +#define HASH_CAM_INDIRECT_OP_DONE_VAL_MASK 0x1 + + +/* + * Register
+ * + * Key Address to be used in RD/WR opoerations. + */ +#define HASH_CAM_INDIRECT_ADDR 0x808 + +/* + * This bit indicate if the operation (RD/WR) is performed on the key0 or + * key1 part of the entry +*/ +#define HASH_CAM_INDIRECT_ADDR_KEY1_IND_MASK 0x1 + +/* Address of the entry */ +#define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_SHIFT 1 +#define HASH_CAM_INDIRECT_ADDR_ENTRY_ADDR_MASK 0x7e + + +/* + * Register + * + * Valid value to be written - this value is relevant during write + * operation on key0. + */ +#define HASH_CAM_INDIRECT_VLID_IN 0x80c + +/* . */ +#define HASH_CAM_INDIRECT_VLID_IN_VALID_MASK 0x1 + + +/* + * Register + * + * Valid value read from the CAM - this value is relevant during read + * operation on key0. + */ +#define HASH_CAM_INDIRECT_VLID_OUT 0x814 + +/* . */ +#define HASH_CAM_INDIRECT_VLID_OUT_VALID_MASK 0x1 + + +/* + * Register - read-only + * + * The result of a search operation + */ +#define HASH_CAM_INDIRECT_RSLT 0x818 + +/* indicate if a match was found */ +#define HASH_CAM_INDIRECT_RSLT_MATCH_MASK 0x1 + +/* index related to a match result */ +#define HASH_CAM_INDIRECT_RSLT_INDEX_SHIFT 4 +#define HASH_CAM_INDIRECT_RSLT_INDEX_MASK 0x3f0 + + +/* + * Registers - is [ 0 => 1 ] + * + * Key to be used in Write/Compare operations. + * The Key is 64bit long and is represented by 2 registers. + * The lower address register corresponds to the most significant bits of + * the key. + */ +#define HASH_CAM_INDIRECT_KEY_IN(x) (0x820 + (x) * 0x4) + +/* . */ +#define HASH_CAM_INDIRECT_KEY_IN_VALUE_SHIFT 0 +#define HASH_CAM_INDIRECT_KEY_IN_VALUE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Key returned from the CAM in a read operation. + * The Key is 64bit long and is represented by 2 registers. + * The lower address register correspond to the most significant bits of + * the key. + */ +#define HASH_CAM_INDIRECT_KEY_OUT(x) (0x840 + (x) * 0x4) + +/* . */ +#define HASH_CAM_INDIRECT_KEY_OUT_VALUE_SHIFT 0 +#define HASH_CAM_INDIRECT_KEY_OUT_VALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * . + */ +#define HASH_CAM_BIST_BIST_STATUS 0x900 + +/* . */ +#define HASH_CAM_BIST_BIST_STATUS_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_STATUS_VALUE_MASK 0xffffffff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN 0x904 + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_COMPARE_EN_VALUE_MASK 0x1 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_DATA 0x908 + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_DBG_DATA_VALUE_MASK 0xffffffff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL 0x90c + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_DBG_DATA_SLICE_OR_STATUS_SEL_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_DBG_DATA_VALID 0x910 + +/* . */ +#define HASH_CAM_BIST_BIST_DBG_DATA_VALID_VALUE_MASK 0x1 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_EN 0x914 + +/* . */ +#define HASH_CAM_BIST_BIST_EN_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_EN_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_MODE 0x918 + +/* . */ +#define HASH_CAM_BIST_BIST_MODE_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_MODE_VALUE_MASK 0x3 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_RST_L 0x91c + +/* . */ +#define HASH_CAM_BIST_BIST_RST_L_VALUE_MASK 0x1 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT 0x920 + +/* . */ +#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_SKIP_ERROR_CNT_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_DBG_EN 0x924 + +/* . */ +#define HASH_CAM_BIST_DBG_EN_VALUE_SHIFT 0 +#define HASH_CAM_BIST_DBG_EN_VALUE_MASK 0xff + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_CASCADE_SELECT 0x928 + +/* . */ +#define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_CASCADE_SELECT_VALUE_MASK 0x7 + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_BLOCK_SELECT 0x92c + +/* . */ +#define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_SHIFT 0 +#define HASH_CAM_BIST_BIST_BLOCK_SELECT_VALUE_MASK 0xf + + +/* + * Register + * + * . + */ +#define HASH_CAM_BIST_BIST_REPAIR_ENABLE 0x930 + +/* . */ +#define HASH_CAM_BIST_BIST_REPAIR_ENABLE_VALUE_MASK 0x1 + + +/* + * Register + * + * This register contains the current active hash interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define HASH_INTR_CTRL_ISR 0xa00 + +/* Command cfg field is invalid (equals to 0) */ +#define HASH_INTR_CTRL_ISR_INVLD_CMD_MASK 0x1 + +/* + * During the search process same key was found a valid in multiple + * engines. +*/ +#define HASH_INTR_CTRL_ISR_MULT_MATCH_MASK 0x2 + +/* hash table index over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_0_IDX_OVFLV_MASK 0x4 + +/* hash table over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_1_IDX_OVFLV_MASK 0x8 + +/* hash table index over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_2_IDX_OVFLV_MASK 0x10 + +/* hash table index over flow at hash engine */ +#define HASH_INTR_CTRL_ISR_HASH_3_IDX_OVFLV_MASK 0x20 + +/* Context table index over flow */ +#define HASH_INTR_CTRL_ISR_CNTXT_IDX_OVFLV_MASK 0x40 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define HASH_INTR_CTRL_ISM 0xa04 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define HASH_INTR_CTRL_ISM_ISM_SHIFT 0 +#define HASH_INTR_CTRL_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define HASH_INTR_CTRL_IER 0xa08 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define HASH_INTR_CTRL_IER_IEM_SHIFT 0 +#define HASH_INTR_CTRL_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define HASH_INTR_CTRL_ITR 0xa0c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define HASH_INTR_CTRL_ITR_IST_SHIFT 0 +#define HASH_INTR_CTRL_ITR_IST_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG0 0xa30 + +/* read debug register */ +#define HASH_DEBUG_DBG0_VAL_SHIFT 0 +#define HASH_DEBUG_DBG0_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG1 0xa34 + +/* read debug register */ +#define HASH_DEBUG_DBG1_VAL_SHIFT 0 +#define HASH_DEBUG_DBG1_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG2 0xa38 + +/* read debug register */ +#define HASH_DEBUG_DBG2_VAL_SHIFT 0 +#define HASH_DEBUG_DBG2_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG3 0xa3c + +/* read debug register */ +#define HASH_DEBUG_DBG3_VAL_SHIFT 0 +#define HASH_DEBUG_DBG3_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG4 0xa40 + +/* read debug register */ +#define HASH_DEBUG_DBG4_VAL_SHIFT 0 +#define HASH_DEBUG_DBG4_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG5 0xa44 + +/* read debug register */ +#define HASH_DEBUG_DBG5_VAL_SHIFT 0 +#define HASH_DEBUG_DBG5_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG6 0xa48 + +/* read debug register */ +#define HASH_DEBUG_DBG6_VAL_SHIFT 0 +#define HASH_DEBUG_DBG6_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG7 0xa4c + +/* read debug register */ +#define HASH_DEBUG_DBG7_VAL_SHIFT 0 +#define HASH_DEBUG_DBG7_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG8 0xa50 + +/* read debug register */ +#define HASH_DEBUG_DBG8_VAL_SHIFT 0 +#define HASH_DEBUG_DBG8_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG9 0xa54 + +/* read debug register */ +#define HASH_DEBUG_DBG9_VAL_SHIFT 0 +#define HASH_DEBUG_DBG9_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG10 0xa58 + +/* read debug register */ +#define HASH_DEBUG_DBG10_VAL_SHIFT 0 +#define HASH_DEBUG_DBG10_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG11 0xa5c + +/* read debug register */ +#define HASH_DEBUG_DBG11_VAL_SHIFT 0 +#define HASH_DEBUG_DBG11_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG12 0xa60 + +/* read debug register */ +#define HASH_DEBUG_DBG12_VAL_SHIFT 0 +#define HASH_DEBUG_DBG12_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG13 0xa64 + +/* read debug register */ +#define HASH_DEBUG_DBG13_VAL_SHIFT 0 +#define HASH_DEBUG_DBG13_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG14 0xa68 + +/* read debug register */ +#define HASH_DEBUG_DBG14_VAL_SHIFT 0 +#define HASH_DEBUG_DBG14_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG15 0xa6c + +/* read debug register */ +#define HASH_DEBUG_DBG15_VAL_SHIFT 0 +#define HASH_DEBUG_DBG15_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG16 0xa70 + +/* read debug register */ +#define HASH_DEBUG_DBG16_VAL_SHIFT 0 +#define HASH_DEBUG_DBG16_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG17 0xa74 + +/* read debug register */ +#define HASH_DEBUG_DBG17_VAL_SHIFT 0 +#define HASH_DEBUG_DBG17_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG18 0xa78 + +/* read debug register */ +#define HASH_DEBUG_DBG18_VAL_SHIFT 0 +#define HASH_DEBUG_DBG18_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG19 0xa7c + +/* read debug register */ +#define HASH_DEBUG_DBG19_VAL_SHIFT 0 +#define HASH_DEBUG_DBG19_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug reg + */ +#define HASH_DEBUG_DBG20 0xa80 + +/* read debug register */ +#define HASH_DEBUG_DBG20_VAL_SHIFT 0 +#define HASH_DEBUG_DBG20_VAL_MASK 0xffffffff + + +/* + * Register + * + * debug select mux + */ +#define HASH_DEBUG_DBG_SEL 0xa84 + +/* debug sel */ +#define HASH_DEBUG_DBG_SEL_VAL_SHIFT 0 +#define HASH_DEBUG_DBG_SEL_VAL_MASK 0x1f + + +/* + * Registers - is [ 0 => 65 ] + * + * Each bit in the ram represents hash/CAM entry. + * (6K hash entries + 64 CAM entries)/32= 194 rowsBit 0 at the ram + * corresponds to entry 0 (eng0), Bit 1 at the ram corresponds to entry 1 + * (eng1), and so on. + * . + */ +#define HASH_AGING_RAM_AGING(x) (0x7000 + (x) * 0x4) + +/* . */ +#define HASH_AGING_RAM_AGING_DATA_SHIFT 0 +#define HASH_AGING_RAM_AGING_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1215 ] + * + * 24 most significant bits of an entry (first 3B) + */ +#define HASH_CONTEXT_RAM_CONTEXT_47_24(x) (0x8000 + (x) * 0x8) + +/* . */ +#define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_SHIFT 0 +#define HASH_CONTEXT_RAM_CONTEXT_47_24_DATA_MASK 0xffffff + + +/* + * Registers - is [ 0 => 1215 ] + * + * 24 least significant bits of an entry (second 3B) + */ +#define HASH_CONTEXT_RAM_CONTEXT_23_0(x) (0x8004 + (x) * 0x8) + +/* . */ +#define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_SHIFT 0 +#define HASH_CONTEXT_RAM_CONTEXT_23_0_DATA_MASK 0xffffff + + +/* + * Registers - is [ 0 => 2047 ] + * + * Includes the MSB field of the hash entry + */ +#define HASH_RAM_ENG_HIGH(x) (0x10000 + (x) * 0x8) + +/* + * This field contains one of the two: + * key extension or internal context data. + * It defined by table configuration. +*/ +#define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_SHIFT 0 +#define HASH_RAM_ENG_HIGH_KEY_59_28_OR_DAT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 2047 ] + * + * Includes the MSB field of the hash entry + */ +#define HASH_RAM_ENG_LOW(x) (0x10004 + (x) * 0x8) + +/* + * Indicates not to search at this entry due to the ongoing update of the + * entry. +*/ +#define HASH_RAM_ENG_LOW_SKP_MASK 0x1 + +/* + * Determines the table config number, between 1-7. + * Config 0 is used to indicate invalid entry +*/ +#define HASH_RAM_ENG_LOW_CFG_SHIFT 1 +#define HASH_RAM_ENG_LOW_CFG_MASK 0xe + +/* + * Includes the first part of the key. + * This field is preserved for key use only. +*/ +#define HASH_RAM_ENG_LOW_KEY_11_0_SHIFT 4 +#define HASH_RAM_ENG_LOW_KEY_11_0_MASK 0xfff0 + +/* + * This field contains one of the two: + * key extension or internal context data. + * It defined by table configuration. +*/ +#define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_SHIFT 16 +#define HASH_RAM_ENG_LOW_KEY_27_12_OR_DAT_MASK 0xffff0000 + + +#endif /* ! XRDP_REGS_HASH_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_natc.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_natc.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_natc.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_natc.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,1511 @@ +#ifndef XRDP_REGS_NATC_H_ +#define XRDP_REGS_NATC_H_ + +/* relative to core */ +#define NATC_OFFSET_0 0xe50000 + + +/* + * + * register set NATC + * + */ + +/* + * Register + * + * NAT Cache Control and Status Register. + */ +#define NATC_CONTROL_STATUS 0x0 + +/* + * Enables NAT table offload to DDR functionality. + * NATC_CONTROL_STATUS2 register should be configured before enabling this + * feature. +*/ +#define CONTROL_STATUS_DDR_ENABLE_MASK 0x80000000 + +/* + * Default behavior for an ADD command is to do a LOOKUP first to see if + * the entrywith the same key already exists and replace it; this is to + * avoid having duplicatedentries in the table for ADD command. + * When this bit is set an ADD command willeither replace the entry with + * the matched key or add an entry to an empty entrydepending on whichever + * one is encountered first during multi-hash. + * Enablingthis bit speeds up the ADD command. +*/ +#define CONTROL_STATUS_NATC_ADD_COMMAND_SPEEDUP_MODE_MASK 0x40000000 + +#define CONTROL_STATUS_UNUSED4_SHIFT 28 +#define CONTROL_STATUS_UNUSED4_MASK 0x30000000 +/* + * Swap 64-bit word within 128-bit word for DDR memory read/write + * accesses(i. + * e. + * , [127: + * 0] becomes {[63: + * 0], [127: + * 64]}). + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS_DDR_64BIT_IN_128BIT_SWAP_CONTROL_MASK 0x8000000 + +/* + * Swap 32-bit word within 64-bit word for statistics (counter) memory + * accesses(i. + * e. + * , [63: + * 0] becomes {[31: + * 0], [63: + * 32]}) +*/ +#define CONTROL_STATUS_SMEM_32BIT_IN_64BIT_SWAP_CONTROL_MASK 0x4000000 + +/* + * Reverse bytes within 32-bit word for statistics (counter) memory + * accesses(i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}) +*/ +#define CONTROL_STATUS_SMEM_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x2000000 + +/* + * Swap all bytes on DDR interface. + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS_DDR_SWAP_ALL_CONTROL_MASK 0x1000000 + +#define CONTROL_STATUS_UNUSED3_MASK 0x800000 +/* + * Swap 32-bit word within 64-bit word for key_result register accesses(i. + * e. + * , [63: + * 0] becomes {[31: + * 0], [63: + * 32]}) +*/ +#define CONTROL_STATUS_REG_32BIT_IN_64BIT_SWAP_CONTROL_MASK 0x400000 + +/* + * Reverse bytes within 32-bit word for key_result register accesses(i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}) +*/ +#define CONTROL_STATUS_REG_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x200000 + +#define CONTROL_STATUS_UNUSED2_SHIFT 18 +#define CONTROL_STATUS_UNUSED2_MASK 0x1c0000 +/* + * This bit is only valid when CACHE_UPDATE_ON_DDR_MISS bit is set to 1. + * This bit determines whether pending FIFO entry will be checked + * todetermine whether cache update on DDR miss will happen or not. + * 1h: + * Enable; DDR miss entry fetched from DDR will be cached if pending + * FIFOcontains entries which have the same hash value as DDR miss entry. + * 0h: + * Disable; DDR miss entry fetched from DDR will always be cached. +*/ +#define CONTROL_STATUS_PENDING_FIFO_ENTRY_CHECK_ENABLE_MASK 0x20000 + +/* + * This bit determines whether DDR lookup will cache the entry for DDR miss + * entry. + * 1h: + * Enable; DDR miss entry fetched from DDR will be cached. + * 0h: + * Disable; DDR miss entry fetched from DDR will not be cached. +*/ +#define CONTROL_STATUS_CACHE_UPDATE_ON_DDR_MISS_MASK 0x10000 + +/* + * 0h: + * Enable DDR lookup when cache misses using register interface lookup1h: + * Disable DDR lookup when cache misses using register interface lookup +*/ +#define CONTROL_STATUS_DDR_DISABLE_ON_REG_LOOKUP_MASK 0x8000 + +/* Reset regfile_FIFO. */ +#define CONTROL_STATUS_REGFILE_FIFO_RESET_MASK 0x4000 + +/* + * Hash algorithm used for internal caching0h: + * 32-bit rolling XOR hash is used as cache hash function. + * 1h: + * CRC32 hash is used as cache hash function. + * CRC32 is reduced to 10-bit usingthe same method as in 32-bit rolling XOR + * hash. + * 2h: + * CRC32 hash is used as cache hash function. + * CRC32[9: + * 0] is used as hash value3h: + * CRC32 hash is used as cache hash function. + * CRC32[25: + * 16] is used as hash value. +*/ +#define CONTROL_STATUS_NAT_HASH_MODE_SHIFT 12 +#define CONTROL_STATUS_NAT_HASH_MODE_MASK 0x3000 + +/* + * Maximum number of multi-hash iterationsValue of 0 is 1 iteration, 1 is 2 + * iterations, 2 is 3 iterations, etc. +*/ +#define CONTROL_STATUS_MULTI_HASH_LIMIT_SHIFT 8 +#define CONTROL_STATUS_MULTI_HASH_LIMIT_MASK 0xf00 + +/* + * Decrement Count Wraparound Enable0h: + * Do not decrement counters for decrement command when counters reach 01h: + * Always decrement counters for decrement command; will wrap around from 0 + * to all 1's +*/ +#define CONTROL_STATUS_DECR_COUNT_WRAPAROUND_ENABLE_MASK 0x80 + +/* + * NAT Arbitration MechanismRound-robin arbitrationStrict priority + * arbitrationlisted from highest to lowest priority -- NAT0, NAT1, NAT2, + * NAT3, RunnerStrict priority arbitration (priority reversed from + * above)listed from highest to lowest priority -- Runner, NAT3, NAT2, + * NAT1, NAT0 +*/ +#define CONTROL_STATUS_NAT_ARB_ST_SHIFT 5 +#define CONTROL_STATUS_NAT_ARB_ST_MASK 0x60 + +/* + * Enables incrementing or decrementing hit counter by 1 and byte counter + * by PKT_LENon successful lookups using register interfaceBY default, + * counters only increment on successful lookups on Runner interface +*/ +#define CONTROL_STATUS_NATC_SMEM_INCREMENT_ON_REG_LOOKUP_MASK 0x10 + +/* + * Disables clearing counters when an existing entry is replaced by ADD + * command +*/ +#define CONTROL_STATUS_NATC_SMEM_CLEAR_BY_UPDATE_DISABLE_MASK 0x8 + +/* Disables counters from incrementing when hit */ +#define CONTROL_STATUS_NATC_SMEM_DISABLE_MASK 0x4 + +/* + * Enables all NATC state machines and input FIFO;Clearing this bit will + * halt all state machines gracefully to idle states,all outstanding + * transactions in the FIFO will remain in the FIFO and NATCwill stop + * accepting new commands; All configuration registers should beconfigured + * before enabling this bit. +*/ +#define CONTROL_STATUS_NATC_ENABLE_MASK 0x2 + +/* + * Self Clearing Block Reset (including resetting all registers to default + * values) +*/ +#define CONTROL_STATUS_NATC_RESET_MASK 0x1 + + +/* + * Register + * + * NAT Cache Control and Status Register + */ +#define NATC_CONTROL_STATUS2 0x4 + +/* Reverse bytes within 18-bit DDR hash value */ +#define CONTROL_STATUS2_DDR_HASH_SWAP_MASK 0x80000000 + +/* + * Hash algorithm used for DDR lookupHash value is DDR table size + * dependent. + * 0h: + * 32-bit rolling XOR hash is used as DDR hash function. + * It is reduced to N-bitDDR table size is 8K, N = 13. + * DDR table size is 16K, N = 14. + * DDR table size is 32K, N = 15. + * DDR table size is 64K, N = 16. + * DDR table size is 128K, N = 17. + * DDR table size is 256K, N = 18. + * 1h: + * CRC32 hash is used as DDR hash function. + * CRC32 is reduced to N-bit usingthe same method as in 32-bit rolling XOR + * hash. + * DDR table size is 8K, N = 13. + * DDR table size is 16K, N = 14. + * DDR table size is 32K, N = 15. + * DDR table size is 64K, N = 16. + * DDR table size is 128K, N = 17. + * DDR table size is 256K, N = 18. + * 2h: + * CRC32 hash is used as DDR hash function. + * CRC32[N: + * 0] is used as hash valueDDR table size is 8K, N = 12. + * DDR table size is 16K, N = 13. + * DDR table size is 32K, N = 14. + * DDR table size is 64K, N = 15. + * DDR table size is 128K, N = 16. + * DDR table size is 256K, N = 17. + * 3h: + * CRC32 hash is used as DDR hash function. + * CRC32[31: + * N] is used as hash valueDDR table size is 8K, N = 19. + * DDR table size is 16K, N = 18. + * DDR table size is 32K, N = 17. + * DDR table size is 64K, N = 16. + * DDR table size is 128K, N = 15. + * DDR table size is 256K, N = 14. +*/ +#define CONTROL_STATUS2_DDR_HASH_MODE_SHIFT 29 +#define CONTROL_STATUS2_DDR_HASH_MODE_MASK 0x60000000 + +/* + * Swap 32-bit word within 64-bit word for DDR memory read/write + * accesses(i. + * e. + * , [63: + * 0] becomes {[31: + * 0], [63: + * 32]}). + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS2_DDR_32BIT_IN_64BIT_SWAP_CONTROL_MASK 0x10000000 + +/* + * Reverse bytes within 32-bit word for DDR memory read/write accesses(i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}). + * This bit should be set to 1 in Little Endian mode. +*/ +#define CONTROL_STATUS2_DDR_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x8000000 + +/* (debug command) Do not set this bit to 1 */ +#define CONTROL_STATUS2_CACHE_LOOKUP_BLOCKING_MODE_MASK 0x4000000 + +/* + * Timer tick for pseudo-LRUTimer is incremented on every system clock + * cycleTimer is incremented on every packet arrival to NAT block +*/ +#define CONTROL_STATUS2_AGE_TIMER_TICK_MASK 0x2000000 + +/* + * Timer value used for pseudo-LRU;When timer fires the 8-bit age value of + * every entry in the cache isdecremented (cap at 0). + * The entry with lower value isthe older entry. + * The default setting keeps track of 2s age at~7ms resolution. + * 0: + * 1 tick1: + * 2 ticks2: + * 4 ticks3: + * 8 ticks4: + * 16 ticks. + * .. + * .31: + * 2^31 TICKS +*/ +#define CONTROL_STATUS2_AGE_TIMER_SHIFT 20 +#define CONTROL_STATUS2_AGE_TIMER_MASK 0x1f00000 + +/* + * Replacement algorithm for cachingLowest-multi-hash-iteration number is + * used to select the final replacemententry if multiple entries were + * chosen by the selected algorithm. + * Forinstance, if HIT_COUNT algorithm were selected, and 2nd, 3rd and + * 7thentry all have the same hit_count values, 2nd entry will be evicted. + * If CACHE_DISABLE or EVICTION_DISABLE is set, HIT_COUNT algorithmcan only + * keep track of the hit count while the entry is in the cache. + * When the entry is evicted hit count for that entry is lost. + * Replacement algorithm prioritizes pseudo-LRU over + * lowest-hit-countReplacement algorithm prioritizes lowest-hit-count over + * pseudo-LRUReplacement algorithm uses pseudo-LRUReplacement algorithm + * uses least-hit-countReplacement algorithm prioritizes pseudo-LRU over + * pseudo-randomReplacement algorithm prioritizes lowest-hit-count over + * pseudo-randomReplacement algorithm uses pseudo-random + * algorithmReplacement algorithm prioritizes highest-hit-count + * overmost-recently-useReplacement algorithm prioritizes pseudo-LRU over + * lowest-byte-countReplacement algorithm prioritizes lowest-byte-count + * over pseudo-LRUReplacement algorithm uses least-byte-countReplacement + * algorithm prioritizes lowest-byte-count over pseudo-randomReplacement + * algorithm prioritizes highest-byte-count overmost-recently-use +*/ +#define CONTROL_STATUS2_CACHE_ALGO_SHIFT 16 +#define CONTROL_STATUS2_CACHE_ALGO_MASK 0xf0000 + +#define CONTROL_STATUS2_UNUSED1_SHIFT 8 +#define CONTROL_STATUS2_UNUSED1_MASK 0xff00 +#define CONTROL_STATUS2_UNUSED0_SHIFT 6 +#define CONTROL_STATUS2_UNUSED0_MASK 0xc0 +/* + * This bit determines whether register interface lookup will cache the + * entry from DDR1h: + * Enable; entry fetched from DDR will be cached using register interface + * lookup command0h: + * Disable; entry fetched from DDR will not be cached using register + * interface lookup command +*/ +#define CONTROL_STATUS2_CACHE_UPDATE_ON_REG_DDR_LOOKUP_MASK 0x20 + +/* + * Reverse bytes within 32-bit word for DDR counters on read/write + * accesses. + * (i. + * e. + * , [31: + * 0] becomes {[7: + * 0], [15,8], [23,16], [31,24]}) +*/ +#define CONTROL_STATUS2_DDR_COUNTER_8BIT_IN_32BIT_SWAP_CONTROL_MASK 0x10 + +#define CONTROL_STATUS2_UNUSED5_MASK 0x8 +/* + * (debug command) Do not set this bit to 1Enable replacing existing cache + * counters with DDR fetched entry +*/ +#define CONTROL_STATUS2_DDR_REPLACE_DUPLICATED_CACHED_ENTRY_ENABLE_MASK 0x4 + +/* (debug command) Do not set this bit to 1 */ +#define CONTROL_STATUS2_DDR_LOOKUP_PENDING_FIFO_MODE_DISABLE_MASK 0x2 + +/* + * Disable counter eviction to DDR; this bit is effective when + * CACHE_DISABLE is 0Set this bit when counters are not used; NATC + * performance will improve dueto reduced DDR accesses; CACHE_ALGO should + * not use HIT_COUNT and BYTE_COUNT +*/ +#define CONTROL_STATUS2_EVICTION_DISABLE_MASK 0x1 + + +/* + * Register + * + * NAT Cache Table Control Register + */ +#define NATC_TABLE_CONTROL 0x8 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 7lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL7_MASK 0x800000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 6lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL6_MASK 0x400000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 5lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL5_MASK 0x200000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 4lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL4_MASK 0x100000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 3lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL3_MASK 0x80000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 2lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL2_MASK 0x40000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 1lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL1_MASK 0x20000 + +/* + * Controls the amount of context to fetch from DDR in unit of 8 bytes for + * DDR table 0lowest 4 bits of key[3: + * 0] is used to indicate the context length0=8 byte, 1=16 bytes, 2=24 + * bytes, . + * .. + * . + * 15=128 bytesNote that key length is reduced by 4 bit0h: + * Disable variable context length1h: + * Enable variable context length +*/ +#define TABLE_CONTROL_VAR_CONTEXT_LEN_EN_TBL0_MASK 0x10000 + +/* + * Length of the key for DDR table 70h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL7_MASK 0x8000 + +/* + * DDR table 7 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL7_MASK 0x4000 + +/* + * Length of the key for DDR table 60h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL6_MASK 0x2000 + +/* + * DDR table 6 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL6_MASK 0x1000 + +/* + * Length of the key for DDR table 50h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL5_MASK 0x800 + +/* + * DDR table 5 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL5_MASK 0x400 + +/* + * Length of the key for DDR table 40h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL4_MASK 0x200 + +/* + * DDR table 4 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL4_MASK 0x100 + +/* + * Length of the key for DDR table 30h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL3_MASK 0x80 + +/* + * DDR table 3 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL3_MASK 0x40 + +/* + * Length of the key for DDR table 20h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL2_MASK 0x20 + +/* + * DDR table 2 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL2_MASK 0x10 + +/* + * Length of the key for DDR table 10h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL1_MASK 0x8 + +/* + * DDR table 1 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL1_MASK 0x4 + +/* + * Length of the key for DDR table 00h: + * 16-byte key1h: + * 32-byte key +*/ +#define TABLE_CONTROL_KEY_LEN_TBL0_MASK 0x2 + +/* + * DDR table 0 non-cacheable control0h: + * DDR table is cached1h: + * DDR table is not cached; counters are updated in DDR directly +*/ +#define TABLE_CONTROL_NON_CACHEABLE_TBL0_MASK 0x1 + + + +/* + * + * register sets NATC_CFG, is [ 0 => 8 ] + * + */ + +/* + * Register + * + * Lower 32-bit of the base address of DDR key tableAddress must be 64-bit + * aligned (bit 2 through 0 are zero's)In order maximum number of key + * fetches,for 16-byte key, bit 3 should be 0 to align at 16 byte + * boundaryfor 32-byte key, bit 3 and 4 should be 0 to align at 32 bytes + * boundary + */ +#define NATC_CFG_DDR_KEY_BASE_ADDR_LO(r) (0x2d0 + (r) * 0x10) + +#define DDR_KEY_BASE_ADDR_LO_BAR_SHIFT 3 +#define DDR_KEY_BASE_ADDR_LO_BAR_MASK 0xfffffff8 +#define DDR_KEY_BASE_ADDR_LO_ZEROS_SHIFT 0 +#define DDR_KEY_BASE_ADDR_LO_ZEROS_MASK 0x7 + +/* + * Register + * + * Upper 8-bit of the base address of DDR key tableFor 32-bit system this + * field should be left as 0 + */ +#define NATC_CFG_DDR_KEY_BASE_ADDR_HI(r) (0x2d4 + (r) * 0x10) + +#define DDR_KEY_BASE_ADDR_HI_ZEROS_SHIFT 8 +#define DDR_KEY_BASE_ADDR_HI_ZEROS_MASK 0xffffff00 +#define DDR_KEY_BASE_ADDR_HI_BAR_SHIFT 0 +#define DDR_KEY_BASE_ADDR_HI_BAR_MASK 0xff + +/* + * Register + * + * Lower 32-bit of the base address of DDR context tableAddress must be + * 64-bit aligned (bit 2 through 0 are zero's) + */ +#define NATC_CFG_DDR_RESULT_BASE_ADDR_LO(r) (0x2d8 + (r) * 0x10) + +#define DDR_RESULT_BASE_ADDR_LO_BAR_SHIFT 3 +#define DDR_RESULT_BASE_ADDR_LO_BAR_MASK 0xfffffff8 +#define DDR_RESULT_BASE_ADDR_LO_ZEROS_SHIFT 0 +#define DDR_RESULT_BASE_ADDR_LO_ZEROS_MASK 0x7 + +/* + * Register + * + * Upper 8-bit of the base address of DDR context tableFor 32-bit system + * this field should be left as 0 + */ +#define NATC_CFG_DDR_RESULT_BASE_ADDR_HI(r) (0x2dc + (r) * 0x10) + +#define DDR_RESULT_BASE_ADDR_HI_ZEROS_SHIFT 8 +#define DDR_RESULT_BASE_ADDR_HI_ZEROS_MASK 0xffffff00 +#define DDR_RESULT_BASE_ADDR_HI_BAR_SHIFT 0 +#define DDR_RESULT_BASE_ADDR_HI_BAR_MASK 0xff + + +/* + * + * register sets NATC_CTRS, is [ 0 => 8 ] + * + */ + +/* + * Register + * + * NATC CACHE HIT COUNT + */ +#define NATC_CTRS_CACHE_HIT_COUNT(r) (0x350 + (r) * 0x14) + +/* 32-bit total cache hit count value for statistics collection */ +#define CACHE_HIT_COUNT_CACHE_HIT_COUNT_SHIFT 0 +#define CACHE_HIT_COUNT_CACHE_HIT_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NATC CACHE MISS COUNT + */ +#define NATC_CTRS_CACHE_MISS_COUNT(r) (0x354 + (r) * 0x14) + +/* 32-bit total cache miss count value for statistics collection */ +#define CACHE_MISS_COUNT_CACHE_MISS_COUNT_SHIFT 0 +#define CACHE_MISS_COUNT_CACHE_MISS_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NATC DDR REQUEST COUNT + */ +#define NATC_CTRS_DDR_REQUEST_COUNT(r) (0x358 + (r) * 0x14) + +/* 32-bit total DDR request count value for statistics collection */ +#define DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_SHIFT 0 +#define DDR_REQUEST_COUNT_DDR_REQUEST_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NATC DDR EVICT COUNT + */ +#define NATC_CTRS_DDR_EVICT_COUNT(r) (0x35c + (r) * 0x14) + +/* + * 32-bit total DDR evict count value for statistics collection. + * It does not include the flush command evict count. +*/ +#define DDR_EVICT_COUNT_DDR_EVICT_COUNT_SHIFT 0 +#define DDR_EVICT_COUNT_DDR_EVICT_COUNT_MASK 0xffffffff + + +/* + * Register + * + * DDR BLOCK COUNT + */ +#define NATC_CTRS_DDR_BLOCK_COUNT(r) (0x360 + (r) * 0x14) + +/* 32-bit total DDR blocked access count value for statistics collection */ +#define DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_SHIFT 0 +#define DDR_BLOCK_COUNT_DDR_BLOCK_COUNT_MASK 0xffffffff + + + +/* + * + * register set NATC_DDR_CFG + * + */ + +/* + * Register + * + * DDR Size Register + */ +#define NATC_DDR_CFG_SIZE 0x410 + +/* + * Number of entries in DDR table 7See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL7_SHIFT 21 +#define SIZE_DDR_SIZE_TBL7_MASK 0xe00000 + +/* + * Number of entries in DDR table 6See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL6_SHIFT 18 +#define SIZE_DDR_SIZE_TBL6_MASK 0x1c0000 + +/* + * Number of entries in DDR table 5See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL5_SHIFT 15 +#define SIZE_DDR_SIZE_TBL5_MASK 0x38000 + +/* + * Number of entries in DDR table 4See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL4_SHIFT 12 +#define SIZE_DDR_SIZE_TBL4_MASK 0x7000 + +/* + * Number of entries in DDR table 3See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL3_SHIFT 9 +#define SIZE_DDR_SIZE_TBL3_MASK 0xe00 + +/* + * Number of entries in DDR table 2See description of DDR_SIZE_TBL00=8k; + * 1=16k; 2=32k; 3=64k; 4=128k; 5=256k; 6=invalid; 7=invalid +*/ +#define SIZE_DDR_SIZE_TBL2_SHIFT 6 +#define SIZE_DDR_SIZE_TBL2_MASK 0x1c0 + +/* + * Number of entries in DDR table 10=8k; 1=16k; 2=32k; 3=64k; 4=128k; + * 5=256k; 6=invalid; 7=invalidSee description of DDR_SIZE_TBL0 +*/ +#define SIZE_DDR_SIZE_TBL1_SHIFT 3 +#define SIZE_DDR_SIZE_TBL1_MASK 0x38 + +/* + * Number of entries in DDR table 0Value of 6 or above is invalidTo compute + * the actual size of the table, add DDR_BINS_PER_BUCKET fieldto the table + * size selection;For instance, if DDR_BINS_PER_BUCKET is 3 (4 bins per + * bucket)and DDR_size is 3 (64k entries), the actual size of the table in + * DDR is(64*1024+3) multiply by total length (TOTAL_LEN) of key and + * context in bytesExtra 3 entries are used to store collided entries of + * the last entryvalue 256k 5256k entriesvalue 128k 4128k entriesvalue 64k + * 364k entriesvalue 32k 232k entriesvalue 16k 116k entriesvalue 8k 08k + * entriesdefault 0h +*/ +#define SIZE_DDR_SIZE_TBL0_SHIFT 0 +#define SIZE_DDR_SIZE_TBL0_MASK 0x7 + + +/* + * Register + * + * DDR Bins Per Bucket Register 0 + */ +#define NATC_DDR_CFG_BINS_PER_BUCKET_0 0x414 + +/* + * Number of entries per bucket in DDR table 3See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_SHIFT 24 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL3_MASK 0xff000000 + +/* + * Number of entries per bucket in DDR table 2See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_SHIFT 16 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL2_MASK 0xff0000 + +/* + * Number of entries per bucket in DDR table 1See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_SHIFT 8 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL1_MASK 0xff00 + +/* + * Number of entries per bucket in DDR table 0This is limited by bus max + * burst size. + * For instance, ifUBUS supports max burst size of 128 bytes, key length is + * 16bytes, maximum DDR_BINS_PER_BUCKET that can be programmedis 128 bytes + * / 16-bytes (bytes per bin) = 8 entries0h: + * 1 entry1h: + * 2 entries2h: + * 3 entries3h: + * 4 entries4h: + * 5 entries5h: + * 6 entries6h: + * 7 entries7h: + * 8 entries. + * .. + * .. + * .. + * .. + * .. + * .. +*/ +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_SHIFT 0 +#define BINS_PER_BUCKET_0_DDR_BINS_PER_BUCKET_TBL0_MASK 0xff + + +/* + * Register + * + * DDR Bins Per Bucket Register 1 + */ +#define NATC_DDR_CFG_BINS_PER_BUCKET_1 0x418 + +/* + * Number of entries per bucket in DDR table 7See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_SHIFT 24 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL7_MASK 0xff000000 + +/* + * Number of entries per bucket in DDR table 6See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_SHIFT 16 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL6_MASK 0xff0000 + +/* + * Number of entries per bucket in DDR table 5See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_SHIFT 8 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL5_MASK 0xff00 + +/* + * Number of entries per bucket in DDR table 4See description of + * DDR_BINS_PER_BUCKET_TBL0 +*/ +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_SHIFT 0 +#define BINS_PER_BUCKET_1_DDR_BINS_PER_BUCKET_TBL4_MASK 0xff + + +/* + * Register + * + * DDR TABLE Total Length Register + */ +#define NATC_DDR_CFG_TOTAL_LEN 0x41c + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 7See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL7_SHIFT 21 +#define TOTAL_LEN_TOTAL_LEN_TBL7_MASK 0xe00000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 6See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL6_SHIFT 18 +#define TOTAL_LEN_TOTAL_LEN_TBL6_MASK 0x1c0000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 5See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL5_SHIFT 15 +#define TOTAL_LEN_TOTAL_LEN_TBL5_MASK 0x38000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 4See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL4_SHIFT 12 +#define TOTAL_LEN_TOTAL_LEN_TBL4_MASK 0x7000 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 3See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL3_SHIFT 9 +#define TOTAL_LEN_TOTAL_LEN_TBL3_MASK 0xe00 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 2See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL2_SHIFT 6 +#define TOTAL_LEN_TOTAL_LEN_TBL2_MASK 0x1c0 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 1See description of TOTAL_LEN_TBL0. +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL1_SHIFT 3 +#define TOTAL_LEN_TOTAL_LEN_TBL1_MASK 0x38 + +/* + * Length of the lookup key plus context (including 8-byte counters) in DDR + * table 0The context length (including 8-byte counters) is calculated by + * TOTAL_LEN minus KEY_LENThe maximum value should not exceed hardware + * capability. + * For instance, most projects have max of 80-bytes and BCM63158 has max + * value of 144-byte. + * 0h: + * 48-byte1h: + * 64-byte2h: + * 80-byte3h: + * 96-byte4h: + * 112-byte5h: + * 128-byte6h: + * 144-byte7h: + * 160-byte +*/ +#define TOTAL_LEN_TOTAL_LEN_TBL0_SHIFT 0 +#define TOTAL_LEN_TOTAL_LEN_TBL0_MASK 0x7 + + +/* + * Register + * + * NAT State Machine Status Register + */ +#define NATC_DDR_CFG_SM_STATUS 0x420 + +/* + * Debug bus select. + * 2'b00: + * prb_nat_control. + * 2'b01: + * prb_cmd_control. + * 2'b10: + * prb_wb_control. + * 2'b11: + * prb_ddr_control. +*/ +#define SM_STATUS_DEBUG_SEL_SHIFT 24 +#define SM_STATUS_DEBUG_SEL_MASK 0x3000000 + +/* + * APB to RBUS bridge state machine. + * 2'b00: + * APB_ST_IDLE. + * 2'b01: + * APB_ST_RW. + * 2'b10: + * AOB_ST_END. +*/ +#define SM_STATUS_APB_STATE_SHIFT 22 +#define SM_STATUS_APB_STATE_MASK 0xc00000 + +/* + * DDR request state machine. + * 2'b00: + * DDR_REQ_ST_IDLE. + * 2'b01: + * DDR_REQ_ST_WRITE_HEADER. + * 2'b10: + * DDR_REQ_ST_WRITE_HEADER_DELAY. +*/ +#define SM_STATUS_DDR_REQ_STATE_SHIFT 20 +#define SM_STATUS_DDR_REQ_STATE_MASK 0x300000 + +/* + * DDR reply state machine. + * 3'b000: + * DDR_REP_ST_IDLE. + * 3'b001: + * DDR_REP_ST_READ_DATA. + * 3'b010: + * DDR_REP_ST_READ_RESULT. + * 3'b011: + * DDR_REP_ST_READ_WAIT. + * 3'b100: + * DDR_REP_ST_EVICT_WR_NON_CACHEABLE. +*/ +#define SM_STATUS_DDR_REP_STATE_SHIFT 17 +#define SM_STATUS_DDR_REP_STATE_MASK 0xe0000 + +/* + * Runner command state machine. + * 1'b0: + * RUNNER_CMD_ST_IDLE. + * 1'b1: + * RUNNER_CMD_ST_WRITE_RUNNER_FIFO. +*/ +#define SM_STATUS_RUNNER_CMD_STATE_MASK 0x10000 + +/* + * Write-back state machine. + * 1'b0: + * WB_ST_IDLE. + * 1'b1: + * WB_ST_WRITE_BACIF. +*/ +#define SM_STATUS_WB_STATE_MASK 0x8000 + +/* + * Nat state machine. + * 15'b000000000000000: + * NAT_ST_IDLE. + * 15'b000000000000001: + * NAT_ST_IDLE_WRITE_SMEM. + * 15'b000000000000010: + * NAT_ST_IDLE_DDR_PENDING. + * 15'b000000000000100: + * NAT_ST_HASH. + * 15'b000000000001000: + * NAT_ST_NAT_MEM_READ_REQ. + * 15'b000000000010000: + * NAT_ST_NAT_MEM_WRITE_REQ. + * 15'b000000000100000: + * NAT_ST_READ_SMEM. + * 15'b000000001000000: + * NAT_ST_UPDATE_DDR. + * 15'b000000010000000: + * NAT_ST_IDLE_BLOCKING_PENDING. + * 15'b000000100000000: + * NAT_ST_EVICT_WAIT. + * 15'b000001000000000: + * NAT_ST_CHECK_NON_CACHEABLE. + * 15'b000010000000000: + * NAT_ST_WAIT. + * 15'b000100000000000: + * NAT_ST_WAIT_NATC_MEM_REQ_DONE. + * 15'b001000000000000: + * NAT_ST_CACHE_FLUSH. + * 15'b010000000000000: + * NAT_ST_DDR_MISS_0. + * 15'b100000000000000: + * NAT_ST_DDR_MISS_1. +*/ +#define SM_STATUS_NAT_STATE_SHIFT 0 +#define SM_STATUS_NAT_STATE_MASK 0x7fff + + + +/* + * + * register sets NATC_ENG, is [ 0 => 4 ] + * + */ + +/* + * Register + * + * NAT Command and Status Register + */ +#define NATC_ENG_COMMAND_STATUS(r) (0x10 + (r) * 0xb0) + +/* + * This filed specifies the DDR BIN number to be compared for DEL + * commandwhen DEL_CMD_MODE is set to 1 +*/ +#define COMMAND_STATUS_DEL_CMD_DDR_BIN_SHIFT 20 +#define COMMAND_STATUS_DEL_CMD_DDR_BIN_MASK 0xff00000 + +/* + * DEL Command DDR-bin matching mode enable0h: + * DEL command deletes the cache entry with matching key1h: + * DEL command deletes the cache entry with matching key and matching DDR + * binnumber specified in DEL_CMD_DDR_BIN field +*/ +#define COMMAND_STATUS_DEL_CMD_MODE_MASK 0x20000 + +/* + * Cache Flush enableWhen set, LOOKUP command is used to flush counters + * from cache into DDR. + * This command does not use key to lookup the cache entry. + * Instead it usescache index number located in 10-MSB bits of key + * specified in NAT_KEY_RESULT register. + * For 16 bytes key, the cache index will be located in{NAT_KEY_RESULT[15], + * NAT_KEY_RESULT[14][7: + * 6]} (15th byte of NAT_KEY_RESULT register andbits 7: + * 6 of 14th byte of NAT_KEY_RESULT register). + * For 32 bytes key, the cache index will be located in{NAT_KEY_RESULT[31], + * NAT_KEY_RESULT[30][7: + * 6]} (31th byte of NAT_KEY_RESULT register andbits 7: + * 6 of 30th byte of NAT_KEY_RESULT register). + * 0h: + * LOOKUP command is used as normal lookup command. + * 1h: + * LOOKUP command is used as cache flush command. +*/ +#define COMMAND_STATUS_CACHE_FLUSH_MASK 0x10000 + +/* + * Decrement-counter mode enableWhen set, LOOKUP command will decrement hit + * counter by 1 and decrementbyte counter by the value specified in + * PKT_LEN, on a successful lookup. + * NATC_SMEM_INCREMENT_ON_REG_LOOKUP must be set to 1 for it to be + * effective0h: + * LOOKUP command will increment hit counter and byte counter1h: + * LOOKUP command will decrement hit counter and byte counter +*/ +#define COMMAND_STATUS_DECR_COUNT_MASK 0x8000 + +/* + * Select the DDR Table on which the command will operate0h: + * DDR table 01h: + * DDR table 12h: + * DDR table 23h: + * DDR table 34h: + * DDR table 45h: + * DDR table 56h: + * DDR table 67h: + * DDR table 7 +*/ +#define COMMAND_STATUS_NAT_TBL_SHIFT 12 +#define COMMAND_STATUS_NAT_TBL_MASK 0x7000 + +/* + * Cache multi-hash iteration count statusValue of 0 is iteration 1, 1 is + * iteration 2, 2 is iteration 3, etc. + * cache miss returns 0 count. +*/ +#define COMMAND_STATUS_MULTIHASH_COUNT_SHIFT 8 +#define COMMAND_STATUS_MULTIHASH_COUNT_MASK 0xf00 + +/* This bit is set when a LOOKUP command has a cache hit */ +#define COMMAND_STATUS_CACHE_HIT_MASK 0x80 + +/* This bit is set when a LOOKUP command has a miss */ +#define COMMAND_STATUS_MISS_MASK 0x40 + +/* + * This bit is set for the following 2 casesFor ADD command all multi-hash + * entries are occupied (i. + * e, no room to ADD)For DEL command entry is not found and cannot be + * deleted +*/ +#define COMMAND_STATUS_ERROR_MASK 0x20 + +/* + * Interface BusyThis bit is set when command is issued but still in + * progress been processed. + * When command completes this bit will be cleared. +*/ +#define COMMAND_STATUS_BUSY_MASK 0x10 + +#define COMMAND_STATUS_UNUSED0_MASK 0x8 +/* + * Command to be executedThis command only operates on the entries in cache + * except LOOKUP command whereentry can be fetched from DDR. + * Writing to this field causes BUSY bit to be set. + * Note: + * For all commands, key consists of all 0's indicates unused entry in + * h/wand therefore cannot be used. + * No-OperationLookupAdd (to cache only)Del (from cache only)Hash (debug + * command)Hashes are stored in different set of COMMAND_STATUS register + * (i. + * e. + * Hashes for HASH command issued using NAT0 register are returnedat NAT1 + * KEY_RESULT registers; hashes for NAT1 HASH commandare returned at NAT0 + * KEY_RESULT; hashes for NAT2 HASH command arereturned at NAT3 KEY_RESULT; + * hashes for NAT3 HASH command arereturned at NAT2 KEY_RESULT register). + * Internal Cache command (debug command)Do not use this command +*/ +#define COMMAND_STATUS_COMMAND_SHIFT 0 +#define COMMAND_STATUS_COMMAND_MASK 0x7 + + +/* + * Register - read-only + * + * NAT Hash Value + */ +#define NATC_ENG_HASH(r) (0x18 + (r) * 0xb0) + +/* + * hash value; only valid on a successful lookup/add/del commandFor cache + * hit 10-bit hash value is returned. + * For cache miss and DDR_ENABLE is 0, first hash value (10-bit) is + * returned. + * For cache miss, DDR_ENABLE is 1 and DDR is a hit, 18-bit DDR hash value + * + DDR bin count is returned. + * For cache miss, DDR_ENABLE is 1 and DDR is a miss, 18-bit DDR hash value + * is returned. +*/ +#define HASH_HASH_SHIFT 0 +#define HASH_HASH_MASK 0xffffffff + + +/* + * Register - read-only + * + * Hit Count + */ +#define NATC_ENG_HIT_COUNT(r) (0x1c + (r) * 0xb0) + +/* + * bits 27: + * 0 are 28-bit hit count value. + * bits 31: + * 28 are 4 lsb of 36-bit byte count value. + * only valid on a successful lookup or delete command. +*/ +#define HIT_COUNT_HIT_COUNT_SHIFT 0 +#define HIT_COUNT_HIT_COUNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Byte Count + */ +#define NATC_ENG_BYTE_COUNT(r) (0x20 + (r) * 0xb0) + +/* + * 32-bit msb of 36-bit byte count value. + * {BYTE_COUNT, HIT_COUNT[31: + * 28]} is the 36-bit byte count value. + * only valid on a successful lookup or delete command +*/ +#define BYTE_COUNT_BYTE_COUNT_SHIFT 0 +#define BYTE_COUNT_BYTE_COUNT_MASK 0xffffffff + + +/* + * Register + * + * NAT PKT Length + */ +#define NATC_ENG_PKT_LEN(r) (0x24 + (r) * 0xb0) + +#define PKT_LEN_UNUSED_SHIFT 16 +#define PKT_LEN_UNUSED_MASK 0xffff0000 +/* 16-bit packet length value used to increment or decrement byte counter */ +#define PKT_LEN_PKT_LEN_SHIFT 0 +#define PKT_LEN_PKT_LEN_MASK 0xffff + + +/* + * Registers - is [ 0 => 33 ] + * + * NAT key & context (excluding 8-byte counters) register; context is + * placed after the key;Key consists of all 0's indicates unused entry in + * hardware and therefore should not beused for lookup/hash/del/add + * commands; Key should contain an encoded type field(e. + * g. + * Unused=0, IPv4=1, IPv4m=2, IPv6=3, IPv6m=4, etc) to uniquely + * identifyeach key so the keys with shorter length of one type is not + * misidentifiedas the longer key of another type when the shorter key + * matches the beginningof the longer key. + * When multiple DDR table mode is used, DDR table number should builtinto + * the key so the same real key in 2 different DDR tables can be + * distinguished. + * For HASH debug command, this register stores the nth multi-hash + * value;For 256_BIT_MODE 10-bit hash value is store at bit 14: + * 5. + * For 512_BIT_MODE,9-bit hash value is stored at bit 14: + * 6; For HASH debug command,hashes for HASH command issued using NAT0 + * register are returnedat NAT1 KEY_RESULT registers; hashes for NAT1 HASH + * commandare returned at NAT0 KEY_RESULT; hashes for NAT2 HASH command + * arereturned at NAT3 KEY_RESULT; hashes for NAT3 HASH command arereturned + * at NAT2 KEY_RESULT register. + */ +#define NATC_ENG_KEY_RESULT(r, x) (0x30 + (r) * 0xb0 + (x) * 0x4) + +#define KEY_RESULT_NAT_KEY_RESULT_SHIFT 0 +#define KEY_RESULT_NAT_KEY_RESULT_MASK 0xffffffff + + +/* + * + * register set NATC_INDIR + * + */ + +/* + * Register + * + */ +#define NATC_INDIR_C_INDIR_ADDR_REG 0x700 + +/* + * NAT Cache Memory and Statics Memory Transaction. + * 1 : + * NAT Cache Memory and Statics Memory Write. + * 0 : + * NAT Cache Memory and Statics Memory Read. +*/ +#define C_INDIR_ADDR_REG_W_R_MASK 0x400 + +/* NAT Cache Entry number. */ +#define C_INDIR_ADDR_REG_NATC_ENTRY_SHIFT 0 +#define C_INDIR_ADDR_REG_NATC_ENTRY_MASK 0x3ff + + +/* + * Registers - is [ 0 => 36 ] + * + */ +#define NATC_INDIR_C_INDIR_DATA_REG(x) (0x710 + (x) * 0x4) + +/* + * Indirect register access data register, bits[31: + * 0]. + * -------------------------------------------------------For NAT Cache nd + * Statics Memory write operation,first, write all the data to Indirect + * Data Registers[N-1: + * 0],N is number of words including key, result, hit count and byte count. + * Indirect Data Register[1: + * 0] are for Statics Memory. + * Indirect Data register[0] is for hit count and 4 lsb of byte count. + * Indirect Data register[0] bits 27: + * 0 are 28-bit hit count. + * Indirect Data register[0] bits 31: + * 28 are 4 lsb of 36-bit byte count. + * Indirect Data Register[1] is for 32 msb of 36-bit byte count. + * {Indirect Data Register[1], Indirect Data register[0][31: + * 28]} is the 36-bit byte count. + * indirect Data register [N-1: + * 2] are for NAT Cache Memory (key and result), key is first,followed by + * result, followed by {ddr_miss, nat_ddr_bin, nat_tbl}then followed by a + * write to Indirect Address Register to set upNAT Cache Entry Number and + * W_R bit to 1, this will initiate the write operation. + * --------------------------------------------------------For NAT Cache + * Memory and statics Memory read operation,first, write to Indirect + * Address Register to set upNAT Cache Entry Number and W_R bit to 0, this + * will initiate the read operation. + * the read data from NAT Cache Memory and statics Memory will be loaded + * into Indirect Data Registers[N-1: + * 0]. + * then followed by read from Indirect Data Registers[N-1: + * 0] for all data. +*/ +#define C_INDIR_DATA_REG_DATA_SHIFT 0 +#define C_INDIR_DATA_REG_DATA_MASK 0xffffffff + + + +/* + * + * register sets NATC_KEY_MASK, is [ 0 => 8 ] + * + */ + +/* + * Register + * + * NAT Cache key Mask Register + */ +#define NATC_KEY_MASK(r) (0x3f0 + (r) * 0x4) + +/* + * Specifies the key mask for each byte in the key. + * each bit corresponds to one byte. + * 0 enables the compare and 1 disables the compare. + * bit 0 corresponds to byte 0bit 1 corresponds to byte 1bit 2 corresponds + * to byte 2. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .. + * .bit 31 corresponds to byte 31 +*/ +#define NATC_KEY_MASK_KEY_MASK_SHIFT 0 +#define NATC_KEY_MASK_KEY_MASK_MASK 0xffffffff + + + +/* + * + * register set NATC_REGFILE + * + */ + +/* + * Register + * + * REGFILE FIFO Start Address register 0Actual FIFO size is 2 more than the + * number programmed inthis register due to input and output holder + * registerswhich account for 2 additional depth. + * The actual FIFO 0 (DDR_KEY_REQ_FIFO) size isREGFILE_FIFO_START_ADDR_1 - + * REGFILE_FIFO_START_ADDR_0 + 2. + * The actual FIFO 1 (DDR_RESULT_REQ_FIFO) size isREGFILE_FIFO_START_ADDR_2 + * - REGFILE_FIFO_START_ADDR_1 + 2. + * The actual FIFO 2 (DDR_KEY_REQ_PIPE) size isREGFILE_FIFO_START_ADDR_3 - + * REGFILE_FIFO_START_ADDR_2 + 2. + * The actual FIFO 3 (BLOCKING_PENDING_FIFO) size + * isREGFILE_FIFO_START_ADDR_4 - REGFILE_FIFO_START_ADDR_3 + 2. + */ +#define NATC_REGFILE_FIFO_START_ADDR_0 0x424 + +/* REGFILE FIFO 2 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_SHIFT 24 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_3_MASK 0xff000000 + +/* REGFILE FIFO 2 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_SHIFT 16 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_2_MASK 0xff0000 + +/* REGFILE FIFO 1 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_SHIFT 8 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_1_MASK 0xff00 + +/* REGFILE FIFO 0 Start Address */ +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_SHIFT 0 +#define FIFO_START_ADDR_0_REGFILE_FIFO_START_ADDR_0_MASK 0xff + + +/* + * Register + * + * REGFILE FIFO Start Address register 1Actual FIFO size is 2 more than the + * number programmed inthis register due to input and output holder + * registerswhich account for 2 additional depth. + * The delta between REGFILE_FIFO_START_ADDR_4 and + * REGFILE_FIFO_START_ADDR_5,REGFILE_FIFO_START_ADDR_5 and + * REGFILE_FIFO_START_ADDR_6,REGFILE_FIFO_START_ADDR_6 and + * REGFILE_FIFO_START_ADDR_7need to be identical since these are used for + * the same wide FIFO. + * The actual FIFO 4 (DDR_WRITE_RESULT_FIFO) size + * isREGFILE_FIFO_START_ADDR_5 - REGFILE_FIFO_START_ADDR_4 + 2. + * The actual FIFO 5 (DDR_WRITE_RESULT_FIFO) size + * isREGFILE_FIFO_START_ADDR_6 - REGFILE_FIFO_START_ADDR_5 + 2. + * The actual FIFO 6 (DDR_WRITE_RESULT_FIFO) size + * isREGFILE_FIFO_START_ADDR_7 - REGFILE_FIFO_START_ADDR_6 + 2. + * The actual FIFO 7 size is the same as FIFO 4, 5, 6 + */ +#define NATC_REGFILE_FIFO_START_ADDR_1 0x428 + +/* + * REGFILE FIFO 7 Start Address -- Note that this entry is not used in + * 68460 +*/ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_SHIFT 24 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_7_MASK 0xff000000 + +/* REGFILE FIFO 6 Start Address */ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_SHIFT 16 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_6_MASK 0xff0000 + +/* REGFILE FIFO 5 Start Address */ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_SHIFT 8 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_5_MASK 0xff00 + +/* REGFILE FIFO 4 Start Address */ +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_SHIFT 0 +#define FIFO_START_ADDR_1_REGFILE_FIFO_START_ADDR_4_MASK 0xff + + +#endif /* ! XRDP_REGS_NATC_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_psram.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_psram.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_psram.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_psram.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,729 @@ +#ifndef XRDP_REGS_PSRAM_H_ +#define XRDP_REGS_PSRAM_H_ + +/* relative to core */ +#define PSRAM_OFFSET_0 0x600000 + +/* + * Registers - is [ 0 => 65535 ] + * + * psram_mem_entry + */ +#define PSRAM_MEMORY_DATA(x) (0x0 + (x) * 0x4) + +/* data */ +#define PSRAM_MEMORY_DATA_DATA_SHIFT 0 +#define PSRAM_MEMORY_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * control reg + */ +#define PSRAM_CFGS_CTRL 0x799400 + +/* + * 1: + * enable memory banks permutations0: + * disable +*/ +#define PSRAM_CFGS_CTRL_PERM_EN_MASK 0x1 + +/* + * 1: + * enable memory banks combinations0: + * disable +*/ +#define PSRAM_CFGS_CTRL_COMB_EN_MASK 0x2 + +/* + * 1: + * enable full combinations(also on same 4-banks)0: + * disable full combinations(allow only on opposite 4-banks) +*/ +#define PSRAM_CFGS_CTRL_COMB_FULL_MASK 0x4 + +/* + * 1: + * all 8 banks are active0: + * only 4 banks are active +*/ +#define PSRAM_CFGS_CTRL_BANKS8_MASK 0x8 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB0_REQIN_ESWAP_MASK 0x10 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB0_REPOUT_ESWAP_MASK 0x20 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB1_REQIN_ESWAP_MASK 0x40 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB1_REPOUT_ESWAP_MASK 0x80 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB2_REQIN_ESWAP_MASK 0x100 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB2_REPOUT_ESWAP_MASK 0x200 + +/* ub_i_reqin_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB3_REQIN_ESWAP_MASK 0x400 + +/* ub_i_repout_eswap for ubus slave port - Not connected */ +#define PSRAM_CFGS_CTRL_UB3_REPOUT_ESWAP_MASK 0x800 + +/* + * 1: + * stall ec client if wants to read same page as one of the pages in the + * ubus write buffers0: + * dont stall +*/ +#define PSRAM_CFGS_CTRL_COH_EN_EC0_MASK 0x1000 + +/* + * 1: + * stall ec client if wants to read same page as one of the pages in the + * ubus write buffers0: + * dont stall +*/ +#define PSRAM_CFGS_CTRL_COH_EN_EC1_MASK 0x2000 + +/* + * 1: + * stall ec client if wants to read same page as one of the pages in the + * ubus write buffers0: + * dont stall +*/ +#define PSRAM_CFGS_CTRL_COH_EN_EC2_MASK 0x4000 + +/* arbitration weight for client 0 - currently not used. */ +#define PSRAM_CFGS_CTRL_WT_0_SHIFT 15 +#define PSRAM_CFGS_CTRL_WT_0_MASK 0x38000 + +/* arbitration weight for client 1 - currently not used. */ +#define PSRAM_CFGS_CTRL_WT_1_SHIFT 18 +#define PSRAM_CFGS_CTRL_WT_1_MASK 0x1c0000 + +/* arbitration weight for client 2 - currently not used. */ +#define PSRAM_CFGS_CTRL_WT_2_SHIFT 21 +#define PSRAM_CFGS_CTRL_WT_2_MASK 0xe00000 + +/* + * 1: + * rr between all clients0: + * ubus is high priority (def) +*/ +#define PSRAM_CFGS_CTRL_ARB_RR_MASK 0x1000000 + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define PSRAM_CFGS_CLK_GATE_CNTRL 0x79940c + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define PSRAM_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define PSRAM_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * this register contains a bit for enable/disable of the counters. + * The counters will be reset to zero on the positive edge of the enable + * bit, and will count until the time window which is decrement counter, + * will reach zero, or until the enable bit will be de-asserted. + */ +#define PSRAM_PM_COUNTERS_MUEN 0x799500 + +/* enable monitor for client 0 */ +#define PSRAM_PM_COUNTERS_MUEN_CL0MEN_MASK 0x1 + +/* enable monitor for client 1 */ +#define PSRAM_PM_COUNTERS_MUEN_CL1MEN_MASK 0x2 + +/* enable monitor for client 2 */ +#define PSRAM_PM_COUNTERS_MUEN_CL2MEN_MASK 0x4 + +/* enable monitor for client 3 */ +#define PSRAM_PM_COUNTERS_MUEN_CL3MEN_MASK 0x8 + +/* enable monitor for client 4 */ +#define PSRAM_PM_COUNTERS_MUEN_CL4MEN_MASK 0x10 + +/* enable monitor for client 5 */ +#define PSRAM_PM_COUNTERS_MUEN_CL5MEN_MASK 0x20 + +/* enable monitor for client 6 */ +#define PSRAM_PM_COUNTERS_MUEN_CL6MEN_MASK 0x40 + + +/* + * Register + * + * determines the time window in which we perform the bandwidth + * monitoring(on cyclic mode - when cyclic_bw_check_en=1) + */ +#define PSRAM_PM_COUNTERS_BWCL 0x799504 + +/* measure time window in clock cycles */ +#define PSRAM_PM_COUNTERS_BWCL_TW_SHIFT 0 +#define PSRAM_PM_COUNTERS_BWCL_TW_MASK 0xffffffff + + +/* + * Register + * + * pm_bw_check_en - start of new monitoring session. + * resets counters on rise. + * cyclic_bw_check_en - if this enabled - when the bw period reaches its + * limit - the counters are reet. + */ +#define PSRAM_PM_COUNTERS_BWEN 0x799508 + +/* + * start of new monitoring session. + * zeroes counters on rise. +*/ +#define PSRAM_PM_COUNTERS_BWEN_BWCEN_MASK 0x1 + +/* + * if this enabled - when the bw period reaches its limit - the counters + * are reset. +*/ +#define PSRAM_PM_COUNTERS_BWEN_CBWCEN_MASK 0x100 + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the maximum time in clock cycles the client + * has waited from the moment it had a request pending to the time the + * request gained arbitration. + */ +#define PSRAM_PM_COUNTERS_MAX_TIME(x) (0x799510 + (x) * 0x4) + +/* max wait time */ +#define PSRAM_PM_COUNTERS_MAX_TIME_MAX_SHIFT 0 +#define PSRAM_PM_COUNTERS_MAX_TIME_MAX_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the accumulated time in clock cycles the + * client has waited from the moment it had a request pending to the time + * the request gained arbitration. + * For each access to arbiter, it will be at least 1 cycle. + */ +#define PSRAM_PM_COUNTERS_ACC_TIME(x) (0x799530 + (x) * 0x4) + +/* max wait time */ +#define PSRAM_PM_COUNTERS_ACC_TIME_MAX_SHIFT 0 +#define PSRAM_PM_COUNTERS_ACC_TIME_MAX_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the accumulated number of requests that was + * served per user. + */ +#define PSRAM_PM_COUNTERS_ACC_REQ(x) (0x799550 + (x) * 0x4) + +/* accumulated number of served requests */ +#define PSRAM_PM_COUNTERS_ACC_REQ_REQ_SHIFT 0 +#define PSRAM_PM_COUNTERS_ACC_REQ_REQ_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the Result of th elast measure of + * accumulated time in clock cycles the client has waited from the moment + * it had a request pending to the time the request gained arbitration. + */ +#define PSRAM_PM_COUNTERS_LAST_ACC_TIME(x) (0x799570 + (x) * 0x4) + +/* accumulated wait time */ +#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_SHIFT 0 +#define PSRAM_PM_COUNTERS_LAST_ACC_TIME_TIME_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters hold the last result of accumulated number of + * requests that was served per user on cyclic measure. + */ +#define PSRAM_PM_COUNTERS_LAST_ACC_REQ(x) (0x799590 + (x) * 0x4) + +/* accumulated number of served requests */ +#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_SHIFT 0 +#define PSRAM_PM_COUNTERS_LAST_ACC_REQ_REQ_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter holds the sum of the WR_CNT array. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC 0x7995b0 + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_ACC_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter holds the sum of the RD_CNT array. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC 0x7995b4 + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_ACC_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words written to the + * psram per client. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT(x) (0x7995b8 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words read from the + * psram per client. + * It holds the result of the current measure. + * If the measure is a single measure, the result will be kept until + * de-assertion and assertion of the SINGLE start bit. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT(x) (0x7995d8 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter is a sum of the WR_CNT_LAST counters, which holds the + * number of double words written to the psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC 0x7995f8 + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_ACC_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter is a sum of the RD_CNT_LAST counters, which holds the + * number of double words written to the psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC 0x7995fc + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_ACC_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words written to the + * psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST(x) (0x799600 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_WR_CNT_LAST_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 6 ] - read-only + * + * This array of counters holds the number of double words read from the + * psram per client. + * When the measure is cyclic, it holds the result of the last measure, + * sampled once every end of a time window. + */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST(x) (0x799620 + (x) * 0x4) + +/* Number of double words that were written to the DDR per client */ +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_SHIFT 0 +#define PSRAM_PM_COUNTERS_BW_RD_CNT_LAST_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were requests (even one) + */ +#define PSRAM_PM_COUNTERS_ARB_REQ 0x799640 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_REQ_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_REQ_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were more that 1 request for arbitration + */ +#define PSRAM_PM_COUNTERS_ARB_ARB 0x799644 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_ARB_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_ARB_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were commands combinations + */ +#define PSRAM_PM_COUNTERS_ARB_COMB 0x799648 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_COMB_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_COMB_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of cycles there were commands combinations in the same 4 banks + */ +#define PSRAM_PM_COUNTERS_ARB_COMB_4 0x79964c + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_COMB_4_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of totsl banks that were accessed during commands combinations + * cycles + */ +#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS 0x799650 + +/* value */ +#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_SHIFT 0 +#define PSRAM_PM_COUNTERS_ARB_COMB_BANKS_VAL_MASK 0xffffffff + + +/* + * Register + * + * selects the debug vecore + */ +#define PSRAM_DEBUG_DBGSEL 0x799700 + +/* selects the debug vector */ +#define PSRAM_DEBUG_DBGSEL_VS_SHIFT 0 +#define PSRAM_DEBUG_DBGSEL_VS_MASK 0xff + + +/* + * Register - read-only + * + * the debug bus + */ +#define PSRAM_DEBUG_DBGBUS 0x799704 + +/* debug vector */ +#define PSRAM_DEBUG_DBGBUS_VB_SHIFT 0 +#define PSRAM_DEBUG_DBGBUS_VB_MASK 0xffffffff + + +/* + * Register - read-only + * + * vector of all the requests of the clients + */ +#define PSRAM_DEBUG_REQ_VEC 0x799708 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_MIPSC_REQ_MASK 0x1 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_RNRA_REQ_MASK 0x2 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_RNRB_REQ_MASK 0x4 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_SDMA_REQ_MASK 0x8 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_MIPSD_REQ_MASK 0x10 + +/* still more commands in the tx fifo */ +#define PSRAM_DEBUG_REQ_VEC_MIPSDMA_REQ_MASK 0x20 + + +/* + * Register + * + * debug capture config + */ +#define PSRAM_DEBUG_DBG_CAP_CFG1 0x799780 + +/* selects bank to capture */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_SEL_MASK 0x7 + +/* selects bank address to capture */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_SHIFT 4 +#define PSRAM_DEBUG_DBG_CAP_CFG1_BANK_ADD_SEL_MASK 0xfff0 + +/* capture write enable */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_WR_EN_MASK 0x10000 + +/* capture read enable */ +#define PSRAM_DEBUG_DBG_CAP_CFG1_CAP_RD_EN_MASK 0x20000 + + +/* + * Register + * + * debug capture config + */ +#define PSRAM_DEBUG_DBG_CAP_CFG2 0x799784 + +/* + * maximum of captures for write. + * 0 means infinite. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_WR_CAP_MASK 0xff + +/* + * maximum of captures for read. + * 0 means infinite. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_SHIFT 8 +#define PSRAM_DEBUG_DBG_CAP_CFG2_MAX_RD_CAP_MASK 0xff00 + +/* + * reset the counting and start new one. + * should be asserted, then deasserted, then counting starts again. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_WR_CAP_CNT_RST_MASK 0x10000 + +/* + * reset the counting and start new one. + * should be asserted, then deasserted, then counting starts again. +*/ +#define PSRAM_DEBUG_DBG_CAP_CFG2_RD_CAP_CNT_RST_MASK 0x20000 + + +/* + * Register - read-only + * + * debug capture status + */ +#define PSRAM_DEBUG_DBG_CAP_ST 0x799788 + +/* + * actual current capture num for write. + * max is FFFF (no wrap). +*/ +#define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_ST_WR_CAP_NUM_ST_MASK 0xff + +/* + * actual current capture num for read. + * max is FFFF (no wrap). +*/ +#define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_SHIFT 8 +#define PSRAM_DEBUG_DBG_CAP_ST_RD_CAP_NUM_ST_MASK 0xff00 + + +/* + * Register - read-only + * + * debug capture write data0 register [32*1-1: + * 32*0] + */ +#define PSRAM_DEBUG_DBG_CAP_W0 0x799790 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W0_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W0_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write data1 register [32*2-1: + * 32*1] + */ +#define PSRAM_DEBUG_DBG_CAP_W1 0x799794 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W1_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W1_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write data2 register [32*3-1: + * 32*2] + */ +#define PSRAM_DEBUG_DBG_CAP_W2 0x799798 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W2_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W2_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write data3 register [32*4-1: + * 32*3] + */ +#define PSRAM_DEBUG_DBG_CAP_W3 0x79979c + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_W3_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_W3_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture write mask register (16b for 16B=128b of data in bank row) + */ +#define PSRAM_DEBUG_DBG_CAP_WMSK 0x7997a0 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_WMSK_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_WMSK_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data0 register [32*1-1: + * 32*0] + */ +#define PSRAM_DEBUG_DBG_CAP_R0 0x7997b0 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R0_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R0_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data1 register [32*2-1: + * 32*1] + */ +#define PSRAM_DEBUG_DBG_CAP_R1 0x7997b4 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R1_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R1_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data2 register [32*3-1: + * 32*2] + */ +#define PSRAM_DEBUG_DBG_CAP_R2 0x7997b8 + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R2_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R2_CV_MASK 0xffffffff + + +/* + * Register - read-only + * + * debug capture read data3 register [32*4-1: + * 32*3] + */ +#define PSRAM_DEBUG_DBG_CAP_R3 0x7997bc + +/* capture vector */ +#define PSRAM_DEBUG_DBG_CAP_R3_CV_SHIFT 0 +#define PSRAM_DEBUG_DBG_CAP_R3_CV_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_PSRAM_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_qm.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_qm.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_qm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_qm.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,4528 @@ +#ifndef XRDP_REGS_QM_H_ +#define XRDP_REGS_QM_H_ + +/* relative to core */ +#define QM_OFFSET_0 0x100000 + +/* + * Register + * + * QM Enable register + */ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL 0x0 + +/* + * FPM Prefetch Enable. + * Setting this bit to 1 will start filling up the FPM pool prefetch FIFOs. + * Seeting this bit to 0, will stop FPM prefetches. +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_FPM_PREFETCH_ENABLE_MASK 0x1 + +/* + * When this bit is set the QM will send credits to the REORDER block. + * Disabling this bit will stop sending credits to the reorder. +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_REORDER_CREDIT_ENABLE_MASK 0x2 + +/* + * When this bit is set the QM will pop PDs from the DQM and place them in + * the runner SRAM +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_POP_ENABLE_MASK 0x4 + +/* + * When this bit is set Fixed arbitration will be done in pops from the + * remote FIFOs (Non delayed highest priority). + * If this bit is cleared RR arbitration is done +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_RMT_FIXED_ARB_ENABLE_MASK 0x100 + +/* + * When this bit is set Fixed arbitration will be done in DQM pushes (CPU + * highest priority, then non-delayed queues and then normal queues. + * If this bit is cleared RR arbitration is done. +*/ +#define QM_GLOBAL_CFG_QM_ENABLE_CTRL_DQM_PUSH_FIXED_ARB_ENABLE_MASK 0x200 + + +/* + * Register + * + * QM soft reset register + */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL 0x4 + +/* FPM Prefetch FIFO0 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH0_SW_RST_MASK 0x1 + +/* FPM Prefetch FIFO1 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH1_SW_RST_MASK 0x2 + +/* FPM Prefetch FIFO2 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH2_SW_RST_MASK 0x4 + +/* FPM Prefetch FIFO3 SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_FPM_PREFETCH3_SW_RST_MASK 0x8 + +/* Normal Remote FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NORMAL_RMT_SW_RST_MASK 0x10 + +/* Non-delayed Remote FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_RMT_SW_RST_MASK 0x20 + +/* Pre Copy Machine FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_PRE_CM_FIFO_SW_RST_MASK 0x40 + +/* Copy Machine RD PD FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_RD_PD_FIFO_SW_RST_MASK 0x80 + +/* Pre Copy Machine FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_CM_WR_PD_FIFO_SW_RST_MASK 0x100 + +/* BB0 OUTPUT FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB0_OUTPUT_FIFO_SW_RST_MASK 0x200 + +/* BB1 Output FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_OUTPUT_FIFO_SW_RST_MASK 0x400 + +/* BB1 Input FIFO SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_BB1_INPUT_FIFO_SW_RST_MASK 0x800 + +/* TM FIFOs Pointers SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_TM_FIFO_PTR_SW_RST_MASK 0x1000 + +/* Non delayed output FIFO Pointers SW reset. */ +#define QM_GLOBAL_CFG_QM_SW_RST_CTRL_NON_DELAYED_OUT_FIFO_SW_RST_MASK 0x2000 + + +/* + * Register + * + * QM Enable register + */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL 0x8 + +/* Indicates whether the Drop/max_occupancy packets counter is read clear. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_PKTS_READ_CLEAR_ENABLE_MASK 0x1 + +/* Indicates whether the Drop/max_occupancy bytes counter is read clear. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_BYTES_READ_CLEAR_ENABLE_MASK 0x2 + +/* + * This bit defines the functionality of the drop packets counter. + * 0 - Functions as the drop packets counter1 - Functions as the max + * packets occupancy holder +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_PKTS_SELECT_MASK 0x4 + +/* + * This bit defines the functionality of the drop bytes counter. + * 0 - Functions as the drop bytes counter1 - Functions as the max bytes + * occupancy holder +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_MAX_OCCUPANCY_BYTES_SELECT_MASK 0x8 + +/* + * Indicates The value to put in the last_search field of the SBPM free + * with context message +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FREE_WITH_CONTEXT_LAST_SEARCH_MASK 0x10 + +/* Disables WRED influence on drop condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_WRED_DISABLE_MASK 0x20 + +/* Disables DDR_PD_CONGESTION influence on drop/bpcondition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_DISABLE_MASK 0x40 + +/* Disables DDR_BYTE_CONGESTION influence on drop/bp condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_BYTE_CONGESTION_DISABLE_MASK 0x80 + +/* Disables DDR_OCCUPANCY influence on drop/bp condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_OCCUPANCY_DISABLE_MASK 0x100 + +/* Disables DDR_FPM_CONGESTION influence on drop/bp condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_FPM_CONGESTION_DISABLE_MASK 0x200 + +/* Disables FPM_UG influence on drop condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_DISABLE_MASK 0x400 + +/* Disables QUEUE_OCCUPANCY_DDR_COPY_DECISION influence on copy condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QUEUE_OCCUPANCY_DDR_COPY_DECISION_DISABLE_MASK 0x800 + +/* Disables PSRAM_OCCUPANCY_DDR_COPY_DECISION influence on copy condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DDR_COPY_DECISION_DISABLE_MASK 0x1000 + +/* When set, the multicast bit of the PD will not be sent to BBH TX */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DONT_SEND_MC_BIT_TO_BBH_MASK 0x2000 + +/* + * When set, aggregations are not closed automatically when queue open + * aggregation time expired. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_CLOSE_AGGREGATION_ON_TIMEOUT_DISABLE_MASK 0x4000 + +/* + * When cleared, given that there is an FPM congestion situation and all + * prefetch FPM buffers are full then a min pool size buffer will be freed + * each 1us. + * This is done due to the fact that exclusive indication is received only + * togeter with buffer allocation reply and if this will not be done then a + * deadlock could occur. + * Setting this bit will disable this mechanism. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_CONGESTION_BUF_RELEASE_MECHANISM_DISABLE_MASK 0x8000 + +/* + * FPM over subscription mechanism. + * Each queue will have one out of 8 reserved byte threshold profiles. + * Each profile defines 8 bit threshold with 512byte resolution. + * Once the global FPM counter pass configurable threshold the system goes + * to buffer reservation congestion state. + * In this state any PD entering a queue which passes the reserved byte + * threshold will be dropped. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_BUFFER_GLOBAL_RES_ENABLE_MASK 0x10000 + +/* Dont drop pd with fpm allocation. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_PRESERVE_PD_WITH_FPM_MASK 0x20000 + +/* 0 for 64B/Queue1 for 128B/Queue */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_RESIDUE_PER_QUEUE_MASK 0x40000 + +/* + * Controls the timing of updating the overhead counters with packets which + * goes through aggregation. + * 0 - updates when the packets enters QM1 - updates when aggregation is + * done. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GHOST_RPT_UPDATE_AFTER_CLOSE_AGG_EN_MASK 0x80000 + +/* Disables FPM_UG influence on flow control wake up messages to FW. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_FPM_UG_FLOW_CTRL_DISABLE_MASK 0x100000 + +/* + * Enables to write packet transaction to multiple slave (unlimited), if + * disable only one ubus slave allowed. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_WRITE_MULTI_SLAVE_EN_MASK 0x200000 + +/* global priority bit to aggregated PDs which go through reprocessing. */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DDR_PD_CONGESTION_AGG_PRIORITY_MASK 0x400000 + +/* Disables PSRAM_OCCUPANCY_DROP influence on drop condition */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_PSRAM_OCCUPANCY_DROP_DISABLE_MASK 0x800000 + +/* 0 According to length1 8-byte aligned */ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_QM_DDR_WRITE_ALIGNMENT_MASK 0x1000000 + +/* + * Controls if the exclusive indication in PD marks the PD as dont drop or + * as dont drop if the fpm in exclusive state1 - global dont drop0 - FPM + * exclusive state dont drop +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_MASK 0x2000000 + +/* + * when set 1 backpressure will be applied when the DONT_DROP pd should be + * dropped. + * for example, 0 fpm buffers available and the PD should be copied to DDR. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_EXCLUSIVE_DONT_DROP_BP_EN_MASK 0x4000000 + +/* + * If the bit enable, QM round up to 4 every packet length added ghost + * counters. +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_GPON_DBR_CEIL_MASK 0x8000000 + +/* + * Drop counter counts WRED drops by color per queue. + * In order to enable this feature the drop counter should be configured to + * count drops. + * if the drop counter is configured count max occupancy per queue, it will + * override WRED drops count. + * color 0 - is written in dropped bytes field (word0)color 1 - is written + * in dropped pkts field (word1) +*/ +#define QM_GLOBAL_CFG_QM_GENERAL_CTRL_DROP_CNT_WRED_DROPS_MASK 0x10000000 + + +/* + * Register + * + * FPM Control Register + */ +#define QM_GLOBAL_CFG_FPM_CONTROL 0xc + +/* + * This field indicates whether crossing the per pool FPM buffer prefetch + * FIFO occupancy thresholds will result in dropping packets or in applying + * back pressure to the re-order. + * 0 - drop packets1 - apply back pressure +*/ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_POOL_BP_ENABLE_MASK 0x1 + +/* + * This field indicates whether crossing the FPM congestion threshold will + * result in dropping packets or in applying back pressure to the re-order. + * 0 - drop packets1 - apply back pressure +*/ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_CONGESTION_BP_ENABLE_MASK 0x2 + +/* + * FPM prefetch minimum pool size. + * The supported FPM pool sizes are derived from this value: + * * FPM_PREFETCH_MIN_POOL_SIZEx1* FPM_PREFETCH_MIN_POOL_SIZEx2* + * FPM_PREFETCH_MIN_POOL_SIZEx4* FPM_PREFETCH_MIN_POOL_SIZEx8The optional + * values for this field: + * 0 - 256Byte1 - 512Byte2 - 1024Byte3 - 2048Byte +*/ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_SHIFT 8 +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_MIN_POOL_SIZE_MASK 0x300 + +/* The allowed on the fly FPM prefetch pending Alloc requests to the FPM. */ +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_SHIFT 16 +#define QM_GLOBAL_CFG_FPM_CONTROL_FPM_PREFETCH_PENDING_REQ_LIMIT_MASK 0x7f0000 + + +/* + * Register + * + * DDR Byte Congestion Control Register + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL 0x10 + +/* + * This field indicates whether crossing the DDR bytes thresholds (the + * number of bytes waiting to be copied to DDR) will result in dropping + * packets or in applying back pressure to the re-order. + * 0 - apply back pressure1 - drop packets +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_CONTROL_DDR_BYTE_CONGESTION_DROP_ENABLE_MASK 0x1 + + +/* + * Register + * + * DDR Byte Congestion Lower Threshold + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LO_THR 0x14 + +/* + * DDR copy bytes Lower Threshold. + * When working in packet drop mode (DDR_BYTES_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then all packets + * are dropped. + * * If (DDR_BYTES_MID_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (DDR_BYTES_LOWER_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_MID_THR), then packets in low priority are dropped. + * * If (DDR copy bytes counter) <= (DDR_BYTES_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_BYTES_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_BYTES_LOWER_THR + * and DDR_BYTES_MID_THR are dont care). +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LO_THR_DDR_BYTES_LOWER_THR_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_LO_THR_DDR_BYTES_LOWER_THR_MASK 0x3fffffff + + +/* + * Register + * + * DDR Byte Congestion Middle Threshold + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR 0x18 + +/* + * DDR copy bytes Lower Threshold. + * When working in packet drop mode (DDR_BYTES_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then all packets + * are dropped. + * * If (DDR_BYTES_MID_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (DDR_BYTES_LOWER_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_MID_THR), then packets in low priority are dropped. + * * If (DDR copy bytes counter) <= (DDR_BYTES_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_BYTES_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_BYTES_LOWER_THR + * and DDR_BYTES_MID_THR are dont care). +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_MID_THR_DDR_BYTES_MID_THR_MASK 0x3fffffff + + +/* + * Register + * + * DDR Byte Congestion Higher Threshold + */ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR 0x1c + +/* + * DDR copy bytes Lower Threshold. + * When working in packet drop mode (DDR_BYTES_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then all packets + * are dropped. + * * If (DDR_BYTES_MID_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (DDR_BYTES_LOWER_THR) < (DDR copy bytes counter) <= + * (DDR_BYTES_MID_THR), then packets in low priority are dropped. + * * If (DDR copy bytes counter) <= (DDR_BYTES_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_BYTES_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy bytes counter) > (DDR_BYTES_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_BYTES_LOWER_THR + * and DDR_BYTES_MID_THR are dont care). +*/ +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_BYTE_CONGESTION_HIGHER_THR_DDR_BYTES_HIGHER_THR_MASK 0x3fffffff + + +/* + * Register + * + * DDR PD Congestion Control Register + */ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL 0x20 + +/* + * This field indicates whether crossing the DDR Pipe thresholds will + * result in dropping packets or in applying back pressure to the re-order. + * 0 - apply back pressure1 - drop packets +*/ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PD_CONGESTION_DROP_ENABLE_MASK 0x1 + +/* + * DDR copy Pipe Lower Threshold. + * When working in packet drop mode (DDR_PD_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then packets in + * low/high priority are dropped (only exclusive packets are not dropped). + * * If (DDR_PIPE_LOWER_THR) < (DDR copy pipe occupancy) <= + * (DDR_PIPE_HIGHER_THR), then packets in low priority are dropped. + * * If (DDR copy pipe occupancy) <= (DDR_PIPE_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_PD_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_PIPE_LOWER_THR is + * dont care). +*/ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_SHIFT 8 +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_LOWER_THR_MASK 0xff00 + +/* + * DDR copy Pipe Lower Threshold. + * When working in packet drop mode (DDR_PD_CONGESTION_DROP_ENABLE=1), + * Then: + * * If (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then packets in + * low/high priority are dropped (only exclusive packets are not dropped). + * * If (DDR_PIPE_LOWER_THR) < (DDR copy pipe occupancy) <= + * (DDR_PIPE_HIGHER_THR), then packets in low priority are dropped. + * * If (DDR copy pipe occupancy) <= (DDR_PIPE_LOWER_THR), then no packets + * are dropped. + * When working in backpressure mode (DDR_PD_CONGESTION_DROP_ENABLE=0), + * Then if (DDR copy pipe occupancy) > (DDR_PIPE_HIGHER_THR), then + * backpressure is applied to re-order (in this case DDR_PIPE_LOWER_THR is + * dont care). + * IMPORTANT: + * recommended maximum value is 0x7B in order to avoid performance + * degradation when working with aggregation timeout enable +*/ +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_SHIFT 16 +#define QM_GLOBAL_CFG_DDR_PD_CONGESTION_CONTROL_DDR_PIPE_HIGHER_THR_MASK 0xff0000 + + +/* + * Register + * + * QM PD Congestion Control Register + */ +#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL 0x24 + +/* + * If the number of PDs for a certain queue exceeds this value, then PDs + * will be dropped. +*/ +#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_SHIFT 0 +#define QM_GLOBAL_CFG_QM_PD_CONGESTION_CONTROL_TOTAL_PD_THR_MASK 0xfffffff + + +/* + * Register + * + * Absolute Adress drop queue + */ +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE 0x28 + +/* + * Absolute address drop queue. + * Absolute address PDs which are dropped will be redirected into this + * configured queue. + * FW will be responsible for reclaiming their DDR space. +*/ +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_SHIFT 0 +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_MASK 0x1ff + +/* + * Absolute address drop queue enable. + * Enables the mechanism in which absolute address PDs which are dropped + * are be redirected into this configured queue. + * FW will be responsible for reclaiming their DDR space. +*/ +#define QM_GLOBAL_CFG_ABS_DROP_QUEUE_ABS_DROP_QUEUE_EN_MASK 0x10000 + + +/* + * Register + * + * Aggregation Control register + */ +#define QM_GLOBAL_CFG_AGGREGATION_CTRL 0x2c + +/* This field indicates the maximum number of bytes in an aggregated PD. */ +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_SHIFT 0 +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_BYTES_MASK 0x3ff + +/* This field indicates the maximum number of packets in an aggregated PD */ +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_SHIFT 16 +#define QM_GLOBAL_CFG_AGGREGATION_CTRL_MAX_AGG_PKTS_MASK 0x30000 + + +/* + * Register + * + * FPM Base Address + */ +#define QM_GLOBAL_CFG_FPM_BASE_ADDR 0x30 + +/* + * FPM Base Address. + * This is the 32-bit MSBs out of the 40-bit address. + * Multiply this field by 256 to get the 40-bit address. + * Example: + * If desired base address is 0x0080_0000The FPM_BASE_ADDR field should be + * configured to: + * 0x0000_8000. +*/ +#define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_SHIFT 0 +#define QM_GLOBAL_CFG_FPM_BASE_ADDR_FPM_BASE_ADDR_MASK 0xffffffff + + +/* + * Register + * + * FPM Base Address for PDs that have the coherent bit set + */ +#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR 0x34 + +/* + * FPM Base Address. + * This is the 32-bit MSBs out of the 40-bit address. + * Multiply this field by 256 to get the 40-bit address. + * Example: + * If desired base address is 0x0080_0000The FPM_BASE_ADDR field should be + * configured to: + * 0x0000_8000. +*/ +#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_SHIFT 0 +#define QM_GLOBAL_CFG_FPM_COHERENT_BASE_ADDR_FPM_BASE_ADDR_MASK 0xffffffff + + +/* + * Register + * + * DDR SOP Offset options + */ +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET 0x38 + +/* DDR SOP Offset option 0 */ +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_SHIFT 0 +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET0_MASK 0x7ff + +/* DDR SOP Offset option 1 */ +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_SHIFT 16 +#define QM_GLOBAL_CFG_DDR_SOP_OFFSET_DDR_SOP_OFFSET1_MASK 0x7ff0000 + + +/* + * Register + * + * EPON Ghost reporting configuration + */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL 0x3c + +/* EPON Line Rate0 - 1G1 - 10G */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_LINE_RATE_MASK 0x1 + +/* + * If this bit is not set then 4-bytes will be added to the ghost reporting + * accumulated bytes and to the byte overhead calculation input +*/ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_EPON_CRC_ADD_DISABLE_MASK 0x2 + +/* Enables to overwrite CRC addition specified MAC FLOW in the field below. */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_EN_MASK 0x4 + +/* MAC flow ID to force disable CRC addition */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_SHIFT 3 +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_MAC_FLOW_OVERWRITE_CRC_MASK 0x7f8 + +/* FEC IPG Length */ +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_SHIFT 16 +#define QM_GLOBAL_CFG_EPON_OVERHEAD_CTRL_FEC_IPG_LENGTH_MASK 0x7ff0000 + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Queue Full indicationEach register includes a batch of 32 queues + * non-empty indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_DQM_FULL(x) (0x40 + (x) * 0x4) + +/* + * Queue Full indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_SHIFT 0 +#define QM_GLOBAL_CFG_DQM_FULL_Q_FULL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Queue Not Empty indicationEach register includes a batch of 32 queues + * non-empty indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_DQM_NOT_EMPTY(x) (0x70 + (x) * 0x4) + +/* + * Queue Not empty indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_SHIFT 0 +#define QM_GLOBAL_CFG_DQM_NOT_EMPTY_Q_NOT_EMPTY_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Queue pop ready indication (Some queues may be non-empty, but due to PD + * offload they are not immediatly ready to be popped. + * Pop can be issued, but in this case the result could be delayed). + * Each register includes a batch of 32 queues non-empty indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_DQM_POP_READY(x) (0xa0 + (x) * 0x4) + +/* + * Queue pop ready indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_SHIFT 0 +#define QM_GLOBAL_CFG_DQM_POP_READY_POP_READY_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 8 ] - read-only + * + * Aggregation context valid. + * This indicates that the queue is in the process of packet aggregation. + * Each register includes a batch of 32 queues aggregation valid + * indication. + * 9 Batches are need for 288 queues. + * First Batch is for queues 31-0 and so on until the last batch + * representing queues 287-256. + */ +#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID(x) (0xd0 + (x) * 0x4) + +/* + * QM ingress aggregation context valid indication. + * This is a 1-bit indication per queue. + * This register consists of a batch of 32 queues. +*/ +#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_SHIFT 0 +#define QM_GLOBAL_CFG_AGGREGATION_CONTEXT_VALID_CONTEXT_VALID_MASK 0xffffffff + + +/* + * Register + * + * Open aggregation will be forced to close after internal timer + * expiration. + * The first byte (0-7bits) controls the granularity of the internal + * counter (valid value 0x0-0x3)The second byte (8-15bits) controls the + * timout value (valid values 0x0-0x7), which is counted according to + * granularity cycles. + * the 16bit is enable for the mechanism + */ +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL 0x100 + +/* + * defines the granularity of the prescaler counter: + * 0 = 10bits1 = 11bits2 = 12bits3 = 13bits4 = 14bits5 = 15bits6 = + * 16bitsdebug: + * 7 = 5bits +*/ +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_SHIFT 0 +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_PRESCALER_GRANULARITY_MASK 0x7 + +/* + * Aggregation timeout value, counted in prescaler counters cycles. + * valid values = [1. + * .7] +*/ +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_SHIFT 8 +#define QM_GLOBAL_CFG_QM_AGGREGATION_TIMER_CTRL_AGGREGATION_TIMEOUT_VALUE_MASK 0x700 + + +/* + * Register + * + * FPM global user group counter: + * UG0-3 + UG7 + */ +#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT 0x118 + +/* FPM global counter */ +#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_SHIFT 0 +#define QM_GLOBAL_CFG_QM_FPM_UG_GBL_CNT_FPM_GBL_CNT_MASK 0xffff + + +/* + * Register + * + * 0-8b: + * queue to flush9b: + * enable flush + */ +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE 0x11c + +/* Queue num */ +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_SHIFT 0 +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_QUEUE_NUM_MASK 0x1ff + +/* flush queue enable */ +#define QM_GLOBAL_CFG_QM_EGRESS_FLUSH_QUEUE_FLUSH_EN_MASK 0x200 + + +/* + * Registers - is [ 0 => 3 ] + * + * Hold 2 thresholds per FPM pool for priority management + */ +#define QM_FPM_POOLS_THR(x) (0x200 + (x) * 0x20) + +/* + * FPM Lower Threshold. + * When working in packet drop mode (FPM_BP_ENABLE=0), Then: + * * If (FPM pool occupancy) <= (FPM_LOWER_THR), then packets in low/high + * priority are dropped (only exclusive packets are not dropped). + * * If (FPM_LOWER_THR) < (FPM pool occupancy) <= (FPM_HIGHER_THR), then + * packets in low priority are dropped. + * * If (FPM pool occupancy) > (FPM_HIGHER_THR), then no packets are + * dropped. + * When working in backpressure mode (FPM_BP_ENABLE=1), Then if (FPM pool + * occupancy) < (FPM_LOWER_THR), then backpressure is applied to re-order + * (in this case FPM_HIGHER_THR is dont care). +*/ +#define QM_FPM_POOLS_THR_FPM_LOWER_THR_SHIFT 0 +#define QM_FPM_POOLS_THR_FPM_LOWER_THR_MASK 0x7f + +/* + * FPM Higher Threshold. + * When working in packet drop mode (FPM_BP_ENABLE=0), Then: + * * If (FPM pool occupancy) <= (FPM_LOWER_THR), then packets in low/high + * priority are dropped (only exclusive packets are not dropped). + * * If (FPM_LOWER_THR) < (FPM pool occupancy) <= (FPM_HIGHER_THR), then + * packets in low priority are dropped. + * * If (FPM pool occupancy) > (FPM_HIGHER_THR), then no packets are + * dropped. + * When working in backpressure mode (FPM_BP_ENABLE=1), Then if (FPM pool + * occupancy) < (FPM_LOWER_THR), then backpressure is applied to re-order + * (in this case FPM_HIGHER_THR is dont care). +*/ +#define QM_FPM_POOLS_THR_FPM_HIGHER_THR_SHIFT 8 +#define QM_FPM_POOLS_THR_FPM_HIGHER_THR_MASK 0x7f00 + + +/* + * Registers - is [ 0 => 3 ] + * + * Holds FPM user group lower threshold. + */ +#define QM_FPM_USR_GRP_LO_THR(x) (0x280 + (x) * 0x20) + +/* + * FPM group Lower Threshold. + * * If (FPM User Group Counter) > (FPM_GRP_HIGHER_THR), all packets in + * this user group are dropped. + * * If (FPM_GRP_MID_THR) < (FPM User Group Counter) <= + * (FPM_GRP_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (FPM_GRP_LOWER_THR) < (FPM User Group Counter) <= + * (FPM_GRP_MID_THR), then packets in low priority are dropped. + * * If (FPM User Group Counter) <= (FPM_GRP_LOWER_THR), then no packets + * are dropped. +*/ +#define QM_FPM_USR_GRP_LO_THR_FPM_GRP_LOWER_THR_SHIFT 0 +#define QM_FPM_USR_GRP_LO_THR_FPM_GRP_LOWER_THR_MASK 0xffff + + +/* + * Registers - is [ 0 => 3 ] + * + * Holds FPM user group middle threshold. + * *IMPORTANT* if buffer reservations is enabled, the following should be + * honored: + * HIGHER_THR-MID_THR > 16 + */ +#define QM_FPM_USR_GRP_MID_THR(x) (0x284 + (x) * 0x20) + +/* + * FPM group Lower Threshold. + * * If (FPM User Group Counter) > (FPM_GRP_HIGHER_THR), all packets in + * this user group are dropped. + * * If (FPM_GRP_MID_THR) < (FPM User Group Counter) <= + * (FPM_GRP_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (FPM_GRP_LOWER_THR) < (FPM User Group Counter) <= + * (FPM_GRP_MID_THR), then packets in low priority are dropped. + * * If (FPM User Group Counter) <= (FPM_GRP_LOWER_THR), then no packets + * are dropped. +*/ +#define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_SHIFT 0 +#define QM_FPM_USR_GRP_MID_THR_FPM_GRP_MID_THR_MASK 0xffff + + +/* + * Registers - is [ 0 => 3 ] + * + * Holds FPM user group higher threshold. + * *IMPORTANT* if buffer reservations is enabled, the following should be + * honored: + * HIGHER_THR-MID_THR > 16 + */ +#define QM_FPM_USR_GRP_HIGHER_THR(x) (0x288 + (x) * 0x20) + +/* + * FPM group Lower Threshold. + * * If (FPM User Group Counter) > (FPM_GRP_HIGHER_THR), all packets in + * this user group are dropped. + * * If (FPM_GRP_MID_THR) < (FPM User Group Counter) <= + * (FPM_GRP_HIGHER_THR), then packets in low/high priority are dropped + * (only exclusive packets are not dropped). + * * If (FPM_GRP_LOWER_THR) < (FPM User Group Counter) <= + * (FPM_GRP_MID_THR), then packets in low priority are dropped. + * * If (FPM User Group Counter) <= (FPM_GRP_LOWER_THR), then no packets + * are dropped. +*/ +#define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_SHIFT 0 +#define QM_FPM_USR_GRP_HIGHER_THR_FPM_GRP_HIGHER_THR_MASK 0xffff + + +/* + * Registers - is [ 0 => 3 ] + * + * FPM user group buffer counter + */ +#define QM_FPM_USR_GRP_CNT(x) (0x28c + (x) * 0x20) + +/* FPM user group counter */ +#define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_SHIFT 0 +#define QM_FPM_USR_GRP_CNT_FPM_UG_CNT_MASK 0xffff + + +/* + * Registers - is [ 0 => 15 ] + * + * Runners Configurations + */ +#define QM_RUNNER_GRP_RNR_CONFIG(x) (0x300 + (x) * 0x10) + +/* Runner BB ID associated with this configuration. */ +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_SHIFT 0 +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_BB_ID_MASK 0x3f + +/* Runner Task number to be woken up when the update FIFO is written to. */ +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_SHIFT 8 +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_TASK_MASK 0xf00 + +/* Enable this runner interface */ +#define QM_RUNNER_GRP_RNR_CONFIG_RNR_ENABLE_MASK 0x10000 + + +/* + * Registers - is [ 0 => 15 ] + * + * Consecutive queues which are associated with this runner + */ +#define QM_RUNNER_GRP_QUEUE_CONFIG(x) (0x304 + (x) * 0x10) + +/* + * Indicates the Queue that starts this runner group. + * Queues belonging to the runner group are defined by the following + * equation: + * START_QUEUE <= runner_queues <= END_QUEUE +*/ +#define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_SHIFT 0 +#define QM_RUNNER_GRP_QUEUE_CONFIG_START_QUEUE_MASK 0x1ff + +/* + * Indicates the Queue that ends this runner group. + * Queues belonging to the runner group are defined by the following + * equation: + * START_QUEUE <= runner_queues <= END_QUEUE +*/ +#define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_SHIFT 16 +#define QM_RUNNER_GRP_QUEUE_CONFIG_END_QUEUE_MASK 0x1ff0000 + + +/* + * Registers - is [ 0 => 15 ] + * + * head of the queue PD FIFO attributes + */ +#define QM_RUNNER_GRP_PDFIFO_CONFIG(x) (0x308 + (x) * 0x10) + +/* + * PD FIFO Base Address. + * This is an 8-byte address (Byte_addr = BASE_ADDR*8). +*/ +#define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_SHIFT 3 +#define QM_RUNNER_GRP_PDFIFO_CONFIG_BASE_ADDR_MASK 0x3ff8 + +/* PD FIFO Size0 - 2 entries1 - 4 entries2 - 8 entries */ +#define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_SHIFT 16 +#define QM_RUNNER_GRP_PDFIFO_CONFIG_SIZE_MASK 0x30000 + + +/* + * Registers - is [ 0 => 15 ] + * + * Update FIFO attributes + */ +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG(x) (0x30c + (x) * 0x10) + +/* + * PD FIFO Base Address. + * This is an 8-byte address (Byte_addr = BASE_ADDR*8). +*/ +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_SHIFT 3 +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_BASE_ADDR_MASK 0x3ff8 + +/* + * PD FIFO Size0 - 8 entries1 - 16 entries2 - 32 entries3 - 64 entries4 - + * 128 entries5 - 256 entries +*/ +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_SHIFT 16 +#define QM_RUNNER_GRP_UPDATE_FIFO_CONFIG_SIZE_MASK 0x70000 + + +/* + * Register + * + * This register contains the current active QM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define QM_INTR_CTRL_ISR 0x400 + +/* HW tried to pop a PD from the DQM of an empty queue. */ +#define QM_INTR_CTRL_ISR_QM_DQM_POP_ON_EMPTY_MASK 0x1 + +/* HW tried to pop a PD into the DQM of a full queue. */ +#define QM_INTR_CTRL_ISR_QM_DQM_PUSH_ON_FULL_MASK 0x2 + +/* CPU tried to pop a PD from the DQM of an empty queue. */ +#define QM_INTR_CTRL_ISR_QM_CPU_POP_ON_EMPTY_MASK 0x4 + +/* CPU tried to push a PD into the DQM of a full queue. */ +#define QM_INTR_CTRL_ISR_QM_CPU_PUSH_ON_FULL_MASK 0x8 + +/* A PD arrived to the Normal queue without having any credits */ +#define QM_INTR_CTRL_ISR_QM_NORMAL_QUEUE_PD_NO_CREDIT_MASK 0x10 + +/* A PD arrived to the NON-delayed queue without having any credits */ +#define QM_INTR_CTRL_ISR_QM_NON_DELAYED_QUEUE_PD_NO_CREDIT_MASK 0x20 + +/* A PD arrived with a non valid queue number (>287) */ +#define QM_INTR_CTRL_ISR_QM_NON_VALID_QUEUE_MASK 0x40 + +/* + * An aggregation of PDs was done in which the coherent bit of the PD + * differs between them (The coherent bit of the first aggregated PD was + * used) +*/ +#define QM_INTR_CTRL_ISR_QM_AGG_COHERENT_INCONSISTENCY_MASK 0x80 + +/* + * A PD with force copy bit set was received on the non-delayed queue (in + * this queue the copy machine is bypassed) +*/ +#define QM_INTR_CTRL_ISR_QM_FORCE_COPY_ON_NON_DELAYED_MASK 0x100 + +/* + * A PD was marked to be copied, but there does not exist an FPM pool + * buffer large enough to hold it. +*/ +#define QM_INTR_CTRL_ISR_QM_FPM_POOL_SIZE_NONEXISTENT_MASK 0x200 + +/* + * A PD was marked with a target_mem=1 (located in PSRAM) and on the other + * hand, the absolute address indication was set. +*/ +#define QM_INTR_CTRL_ISR_QM_TARGET_MEM_ABS_CONTRADICTION_MASK 0x400 + +/* 1588 Packet is dropped when the QM PD occupancy exceeds threshold (64K) */ +#define QM_INTR_CTRL_ISR_QM_1588_DROP_MASK 0x800 + +/* A PD was marked as a 1588 and multicast together. */ +#define QM_INTR_CTRL_ISR_QM_1588_MULTICAST_CONTRADICTION_MASK 0x1000 + +/* + * The byte drop counter of one of the queues reached its maximum value and + * a new value was pushed. +*/ +#define QM_INTR_CTRL_ISR_QM_BYTE_DROP_CNT_OVERRUN_MASK 0x2000 + +/* + * The Packet drop counter of one of the queues reached its maximum value + * and a new value was pushed. +*/ +#define QM_INTR_CTRL_ISR_QM_PKT_DROP_CNT_OVERRUN_MASK 0x4000 + +/* The Total byte counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_TOTAL_BYTE_CNT_UNDERRUN_MASK 0x8000 + +/* The Total PD counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_TOTAL_PKT_CNT_UNDERRUN_MASK 0x10000 + +/* The UG0 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG0_UNDERRUN_MASK 0x20000 + +/* The UG1 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG1_UNDERRUN_MASK 0x40000 + +/* The UG2 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG2_UNDERRUN_MASK 0x80000 + +/* The UG3 counter was decremented to a negative value. */ +#define QM_INTR_CTRL_ISR_QM_FPM_UG3_UNDERRUN_MASK 0x100000 + +/* + * QM aggregation timers wraps around. + * In this case it isnt guaranteed that the aggregation will be closed on + * pre-defined timeout expiration. + * However the aggregation should be closed eventually. +*/ +#define QM_INTR_CTRL_ISR_QM_TIMER_WRAPAROUND_MASK 0x200000 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define QM_INTR_CTRL_ISM 0x404 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define QM_INTR_CTRL_ISM_ISM_SHIFT 0 +#define QM_INTR_CTRL_ISM_ISM_MASK 0x3fffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define QM_INTR_CTRL_IER 0x408 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define QM_INTR_CTRL_IER_IEM_SHIFT 0 +#define QM_INTR_CTRL_IER_IEM_MASK 0x3fffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define QM_INTR_CTRL_ITR 0x40c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define QM_INTR_CTRL_ITR_IST_SHIFT 0 +#define QM_INTR_CTRL_ITR_IST_MASK 0x3fffff + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define QM_CLK_GATE_CLK_GATE_CNTRL 0x500 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define QM_CLK_GATE_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define QM_CLK_GATE_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Access Control + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL(x) (0x600 + (x) * 0x40) + +/* Queue Number */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_QUEUE_NUM_MASK 0x1ff + +/* + * Command: + * 00 - Nothing01 - Write10 - Read11 - Read No commit (entry not + * popped)Will trigger a read/write from the selected RAMIMPORTANT: + * Read is for debug purpose only. + * shouldnt be used during regular QM work on the requested queue (HW pop). + * Popping the same queue both from CPU and HW could cause to race + * condition which will cause to incorrect data output. + * It could occur when there is only one entry in the queue which is + * accessed both from the CPU and the HW. +*/ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_SHIFT 16 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_CMD_MASK 0x30000 + +/* Indicates that read/write to DQM is done */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_DONE_MASK 0x1000000 + +/* Indicates that that an error occured (write on full or read on empty) */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_CTRL_ERROR_MASK 0x2000000 + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0(x) (0x610 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_0_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1(x) (0x614 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_1_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2(x) (0x618 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_2_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] + * + * CPU PD Indirect Write data to DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3(x) (0x61c + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_WR_DATA_3_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0(x) (0x620 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_0_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1(x) (0x624 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_1_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2(x) (0x628 + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_2_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * CPU PD Indirect Read data from DQM. + * First entry represents PD[127: + * 96] and so on until the last entry representing PD[31: + * 0]. + */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3(x) (0x62c + (x) * 0x40) + +/* Data */ +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_SHIFT 0 +#define QM_CPU_INDR_PORT_CPU_PD_INDIRECT_RD_DATA_3_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] + * + * This RAM holds all queue attributes. + * Not all of the 32-bits in the address space are implemented. + * WRED Profile 3: + * 0Copy decision profile 6: + * 4Copy to DDR 7DDR copy disable 8Aggregation Disable 9FPM User Group 11: + * 10Exclusive Priority 12802. + * 1AE 13SCI 14FEC Enable 15 + */ +#define QM_QUEUE_CONTEXT_CONTEXT(x) (0x800 + (x) * 0x4) + +/* Defines to which WRED Profile this queue belongs to. */ +#define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_SHIFT 0 +#define QM_QUEUE_CONTEXT_CONTEXT_WRED_PROFILE_MASK 0xf + +/* Defines to which Copy Decision Profile this queue belongs to. */ +#define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_SHIFT 4 +#define QM_QUEUE_CONTEXT_CONTEXT_COPY_DEC_PROFILE_MASK 0x70 + +/* Defines this queue to always copy to DDR. */ +#define QM_QUEUE_CONTEXT_CONTEXT_COPY_TO_DDR_MASK 0x80 + +/* Defines this queue never to copy to DDR. */ +#define QM_QUEUE_CONTEXT_CONTEXT_DDR_COPY_DISABLE_MASK 0x100 + +/* Defines this queue never to aggregated PDs. */ +#define QM_QUEUE_CONTEXT_CONTEXT_AGGREGATION_DISABLE_MASK 0x200 + +/* Defines to which FPM UG this queue belongs to. */ +#define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_SHIFT 10 +#define QM_QUEUE_CONTEXT_CONTEXT_FPM_UG_MASK 0x1c00 + +/* Defines this queue with exclusive priority. */ +#define QM_QUEUE_CONTEXT_CONTEXT_EXCLUSIVE_PRIORITY_MASK 0x2000 + +/* + * Defines this queue as 802. + * 1AE for EPON packet overhead calculations. +*/ +#define QM_QUEUE_CONTEXT_CONTEXT_Q_802_1AE_MASK 0x4000 + +/* Configures SCI for EPON packet overhead calculations. */ +#define QM_QUEUE_CONTEXT_CONTEXT_SCI_MASK 0x8000 + +/* FEC enable configuration for EPON packet overhead calculations. */ +#define QM_QUEUE_CONTEXT_CONTEXT_FEC_ENABLE_MASK 0x10000 + +/* + * FPM reservation profile. + * Once the QM goes over global FPM reservation threshold. + * Queue with more bytes the defined in the profile will be dropped. + * Profile 0 means no drop due to FPM reservation for the queues with this + * profile. +*/ +#define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_SHIFT 17 +#define QM_QUEUE_CONTEXT_CONTEXT_RES_PROFILE_MASK 0xe0000 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color min thresholds + */ +#define QM_WRED_PROFILE_COLOR_MIN_THR_0(x) (0x1000 + (x) * 0x30) + +/* + * WRED Color Min Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MIN_THR_0_MIN_THR_MASK 0xffffff + +/* + * 0 - flow control disable. + * regular WRED profile1 - flow control enable. + * no WRED drop, wake up appropriate runner task when crossed. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_0_FLW_CTRL_EN_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color min thresholds + */ +#define QM_WRED_PROFILE_COLOR_MIN_THR_1(x) (0x1004 + (x) * 0x30) + +/* + * WRED Color Min Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MIN_THR_1_MIN_THR_MASK 0xffffff + +/* + * 0 - flow control disable. + * regular WRED profile1 - flow control enable. + * no WRED drop, wake up appropriate runner task when crossed. +*/ +#define QM_WRED_PROFILE_COLOR_MIN_THR_1_FLW_CTRL_EN_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color max thresholds + */ +#define QM_WRED_PROFILE_COLOR_MAX_THR_0(x) (0x1010 + (x) * 0x30) + +/* + * WRED Color Max Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MAX_THR_0_MAX_THR_MASK 0xffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color max thresholds + */ +#define QM_WRED_PROFILE_COLOR_MAX_THR_1(x) (0x1014 + (x) * 0x30) + +/* + * WRED Color Max Threshold. + * This field represents the higher 24-bits of the queue occupancy byte + * threshold. + * byte_threshold = THR*64. +*/ +#define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_MAX_THR_1_MAX_THR_MASK 0xffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color slopes + */ +#define QM_WRED_PROFILE_COLOR_SLOPE_0(x) (0x1020 + (x) * 0x30) + +/* WRED Color slope mantissa. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_MANTISSA_MASK 0xff + +/* WRED Color slope exponent. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_SHIFT 8 +#define QM_WRED_PROFILE_COLOR_SLOPE_0_SLOPE_EXP_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 15 ] + * + * WRED Color slopes + */ +#define QM_WRED_PROFILE_COLOR_SLOPE_1(x) (0x1024 + (x) * 0x30) + +/* WRED Color slope mantissa. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_SHIFT 0 +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_MANTISSA_MASK 0xff + +/* WRED Color slope exponent. */ +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_SHIFT 8 +#define QM_WRED_PROFILE_COLOR_SLOPE_1_SLOPE_EXP_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * DDR Pipe and PSRAM threshold configurations for DDR copy decision logic + */ +#define QM_COPY_DECISION_PROFILE_THR(x) (0x1800 + (x) * 0x20) + +/* + * Queue Occupancy Threshold. + * When passing this threhold, packets will be copied to the DDR +*/ +#define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_SHIFT 0 +#define QM_COPY_DECISION_PROFILE_THR_QUEUE_OCCUPANCY_THR_MASK 0x3fffffff + +/* + * Indicates which of the two PSRAM threshold crossing indications coming + * from the SBPM will be used for the copy decision. + * when going over the chosen threshold, packets will be copied to the DDR. + * 0 - Lower threshold1 - Higher threshold +*/ +#define QM_COPY_DECISION_PROFILE_THR_PSRAM_THR_MASK 0x80000000 + + +/* + * Registers - is [ 0 => 639 ] + * + * Counter. + * word0: + * {15`b0,pkt_cnt[16: + * 0]}word1: + * {2`b0,byte_cnt[29: + * 0]}word2: + * {15b0,res_cnt[16: + * 0]}word3: + * reservedThere are three words per queue starting at queue0 up to queue + * 159/287. + */ +#define QM_TOTAL_VALID_COUNTER_COUNTER(x) (0x2000 + (x) * 0x4) + +/* DATA */ +#define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_SHIFT 0 +#define QM_TOTAL_VALID_COUNTER_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 319 ] + * + * Counter. + * word0: + * {15`b0,pkt_cnt[16: + * 0]}word1: + * {2`b0,byte_cnt[29: + * 0]}There are two words per queue starting at queue0 up to queue 287. + */ +#define QM_DQM_VALID_COUNTER_COUNTER(x) (0x3000 + (x) * 0x4) + +/* DATA */ +#define QM_DQM_VALID_COUNTER_COUNTER_DATA_SHIFT 0 +#define QM_DQM_VALID_COUNTER_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 319 ] - read-only + * + * Counter. + * word0: + * {6`b0,pkt_cnt[25: + * 0]}word1: + * {byte_cnt[31: + * 0]}in WRED drop mode: + * word0 - color1 dropped packetsword1 - color0 dropped packetsThere are + * two words per queue starting at queue0 up to queue 287. + */ +#define QM_DROP_COUNTER_COUNTER(x) (0x4000 + (x) * 0x4) + +/* DATA */ +#define QM_DROP_COUNTER_COUNTER_DATA_SHIFT 0 +#define QM_DROP_COUNTER_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 319 ] + * + * Counter - For each of the 32-queues in a batch, this counter stores a + * 32-bit accumulated and overhead byte counter per queue. + * word0: + * {accumulated_bytes[31: + * 0]}word1: + * {accumulated_overhead[31: + * 0}There are two words per queue starting at queue0 up to queue 127. + */ +#define QM_EPON_RPT_CNT_COUNTER(x) (0x5000 + (x) * 0x4) + +/* DATA */ +#define QM_EPON_RPT_CNT_COUNTER_DATA_SHIFT 0 +#define QM_EPON_RPT_CNT_COUNTER_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 4 ] - read-only + * + * Status bit vector - For each of the 32-queues in a batch, this status + * indicates which queue counter has been updated. + */ +#define QM_EPON_RPT_CNT_QUEUE_STATUS(x) (0x5500 + (x) * 0x4) + +/* + * Status bit vector - a bit per queue indicates if the queue has been + * updated. +*/ +#define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_SHIFT 0 +#define QM_EPON_RPT_CNT_QUEUE_STATUS_STATUS_BIT_VECTOR_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL0 0x5800 + +/* DATA */ +#define QM_RD_DATA_POOL0_DATA_SHIFT 0 +#define QM_RD_DATA_POOL0_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL1 0x5804 + +/* DATA */ +#define QM_RD_DATA_POOL1_DATA_SHIFT 0 +#define QM_RD_DATA_POOL1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL2 0x5808 + +/* DATA */ +#define QM_RD_DATA_POOL2_DATA_SHIFT 0 +#define QM_RD_DATA_POOL2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read the head of the FIFO + */ +#define QM_RD_DATA_POOL3 0x580c + +/* DATA */ +#define QM_RD_DATA_POOL3_DATA_SHIFT 0 +#define QM_RD_DATA_POOL3_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 159 ] - read-only + * + * PDFIFO per queue rd/wr pointers + */ +#define QM_PDFIFO_PTR(x) (0x6000 + (x) * 0x4) + +/* PDFIFO WR pointers */ +#define QM_PDFIFO_PTR_WR_PTR_SHIFT 0 +#define QM_PDFIFO_PTR_WR_PTR_MASK 0xf + +/* PDFIFO RD pointers */ +#define QM_PDFIFO_PTR_RD_PTR_SHIFT 8 +#define QM_PDFIFO_PTR_RD_PTR_MASK 0xf00 + + +/* + * Registers - is [ 0 => 15 ] - read-only + * + * Update FIFO rd/wr pointers + */ +#define QM_UPDATE_FIFO_PTR(x) (0x6500 + (x) * 0x4) + +/* UF WR pointers */ +#define QM_UPDATE_FIFO_PTR_WR_PTR_SHIFT 0 +#define QM_UPDATE_FIFO_PTR_WR_PTR_MASK 0x1ff + +/* UF RD pointers */ +#define QM_UPDATE_FIFO_PTR_RD_PTR_SHIFT 9 +#define QM_UPDATE_FIFO_PTR_RD_PTR_MASK 0xfe00 + + +/* + * Registers - is [ 0 => 4 ] - read-only + * + * Debug - Read the head of the FIFO + */ +#define QM_RD_DATA(x) (0x8800 + (x) * 0x4) + +/* DATA */ +#define QM_RD_DATA_DATA_SHIFT 0 +#define QM_RD_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * Pop an entry in the FIFO + */ +#define QM_POP 0x8820 + +/* Pop FIFO entry */ +#define QM_POP_POP_MASK 0x1 + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * CM Common Input FIFO - debug access + */ +#define QM_CM_COMMON_INPUT_FIFO_DATA(x) (0x9000 + (x) * 0x4) + +/* DATA */ +#define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_CM_COMMON_INPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Normal Remote FIFO - debug access + */ +#define QM_NORMAL_RMT_FIFO_DATA(x) (0x9100 + (x) * 0x4) + +/* DATA */ +#define QM_NORMAL_RMT_FIFO_DATA_DATA_SHIFT 0 +#define QM_NORMAL_RMT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Non-delayed Remote FIFO - debug access + */ +#define QM_NON_DELAYED_RMT_FIFO_DATA(x) (0x9200 + (x) * 0x4) + +/* DATA */ +#define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_SHIFT 0 +#define QM_NON_DELAYED_RMT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * Egress data FIFO - debug access + */ +#define QM_EGRESS_DATA_FIFO_DATA(x) (0x9300 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_DATA_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_DATA_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * Egress RR FIFO - debug access + */ +#define QM_EGRESS_RR_FIFO_DATA(x) (0x9400 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_RR_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_RR_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * Egress BB Input FIFO - debug access + */ +#define QM_EGRESS_BB_INPUT_FIFO_DATA(x) (0x9500 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_BB_INPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Egress BB Output FIFO - debug access + */ +#define QM_EGRESS_BB_OUTPUT_FIFO_DATA(x) (0x9600 + (x) * 0x4) + +/* DATA */ +#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_EGRESS_BB_OUTPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * QM BB Output FIFO - debug access + */ +#define QM_BB_OUTPUT_FIFO_DATA(x) (0x9700 + (x) * 0x4) + +/* DATA */ +#define QM_BB_OUTPUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_BB_OUTPUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * Non delayed output FIFO - debug access + */ +#define QM_NON_DELAYED_OUT_FIFO_DATA(x) (0x9800 + (x) * 0x4) + +/* DATA */ +#define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_SHIFT 0 +#define QM_NON_DELAYED_OUT_FIFO_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 639 ] - read-only + * + * Aggregation context - debug access + */ +#define QM_CONTEXT_DATA(x) (0xa000 + (x) * 0x4) + +/* DATA */ +#define QM_CONTEXT_DATA_DATA_SHIFT 0 +#define QM_CONTEXT_DATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] + * + * Reserved FPM buffers in units of min. + * FPM buffer. + * entry0 -> profile0. + * .. + * entry7 -> profile7 + */ +#define QM_FPM_BUFFER_RESERVATION_DATA(x) (0xc000 + (x) * 0x4) + +/* DATA */ +#define QM_FPM_BUFFER_RESERVATION_DATA_DATA_SHIFT 0 +#define QM_FPM_BUFFER_RESERVATION_DATA_DATA_MASK 0xffff + + +/* + * Register + * + * FPM user group ctrl + */ +#define QM_FLOW_CTRL_UG_CTRL 0xc100 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG0_EN_MASK 0x1 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG1_EN_MASK 0x2 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG2_EN_MASK 0x4 + +/* Flow control enable */ +#define QM_FLOW_CTRL_UG_CTRL_FLOW_CTRL_UG3_EN_MASK 0x8 + + +/* + * Register + * + * Keeps status vector of user group + wred are under flow control. + * 3: + * 0 - {ug3,ug2,ug1,ug0}, 4 - OR on wred_sourcefor UG -queues which passed + * the mid. + * thr. + * is set to 1. + * the user groups indication is de-asserted when the occupancy reaches the + * low thr. + * 4bits - bit for each user group. + * for WRED/occupancy -If one of the queues which pass color1 min occupancy + * marked as 1. + * when the occupancy is reduced to below than color0 min occupancy in all + * queues the bit is set to 0. + * FW can set/reset the value, it will updated when flow control which is + * relevant to the corresponding bit takes place. + */ +#define QM_FLOW_CTRL_STATUS 0xc104 + +/* User group 0 status */ +#define QM_FLOW_CTRL_STATUS_UG0_MASK 0x1 + +/* User group 1 status */ +#define QM_FLOW_CTRL_STATUS_UG1_MASK 0x2 + +/* User group 2 status */ +#define QM_FLOW_CTRL_STATUS_UG2_MASK 0x4 + +/* User group 3 status */ +#define QM_FLOW_CTRL_STATUS_UG3_MASK 0x8 + +/* OR on all wred flow control queues */ +#define QM_FLOW_CTRL_STATUS_WRED_MASK 0x10 + +/* reserved */ +#define QM_FLOW_CTRL_STATUS_R0_SHIFT 5 +#define QM_FLOW_CTRL_STATUS_R0_MASK 0xffffffe0 + + +/* + * Registers - is [ 0 => 4 ] + * + * Keeps status vector of queues which are under flow control: + * queues which passed the color1 low threshold is set to 1. + * the queue indication is de-asserted when the queue byte occupancy + * reaches the color0 low threshold. + * 320bits - bit for each queue number (up to 320 queues). + */ +#define QM_FLOW_CTRL_WRED_SOURCE(x) (0xc108 + (x) * 0x4) + +/* each bit represents queue */ +#define QM_FLOW_CTRL_WRED_SOURCE_SRC_SHIFT 0 +#define QM_FLOW_CTRL_WRED_SOURCE_SRC_MASK 0xffffffff + + +/* + * Register + * + * lossless flow control configuration + */ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG 0xc130 + +/* Runner BB ID */ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_SHIFT 0 +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_BB_ID_MASK 0x3f + +/* Runner task */ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_SHIFT 8 +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_TASK_MASK 0xf00 + +/* + * Runner enable. + * if disable, the lossless flow control is disabled. +*/ +#define QM_FLOW_CTRL_QM_FLOW_CTRL_RNR_CFG_RNR_ENABLE_MASK 0x10000 + + +/* + * Register + * + * Controls Debug bus select: + * 5h1: + * qm_dbg_bus = qm_bb_input_dbg_bus;5h2: + * qm_dbg_bus = qm_bb_output_dbg_bus;5h3: + * qm_dbg_bus = qm_cm_dbg_bus;5h4: + * qm_dbg_bus = qm_ddr_write_dbg_bus;5h5: + * qm_dbg_bus = qm_counters_dbg_bus;5h6: + * qm_dbg_bus = qm_cpu_if_dbg_bus;5h7: + * qm_dbg_bus = qm_dqm_push_dbg_bus;5h8: + * qm_dbg_bus = qm_egress_dbg_bus;5h9: + * qm_dbg_bus = qm_fpm_prefetch_dbg_bus;5ha: + * qm_dbg_bus = qm_ingress_dbg_bus;5hb: + * qm_dbg_bus = qm_rmt_fifos_dbg_bus;5hc: + * qm_dbg_bus = {19b0,bbh_debug_0};5hd: + * qm_dbg_bus = {19b0,bbh_debug_1};5he: + * qm_dbg_bus = {19b0,bbh_debug_2};5hf: + * qm_dbg_bus = {19b0,bbh_debug_3};5h10: + * qm_dbg_bus = {19b0,bbh_debug_4};5h11: + * qm_dbg_bus = {19b0,bbh_debug_5};5h12: + * qm_dbg_bus = {19b0,bbh_debug_6};5h13: + * qm_dbg_bus = {19b0,bbh_debug_7};5h14: + * qm_dbg_bus = {19b0,bbh_debug_8};5h15: + * qm_dbg_bus = {19b0,bbh_debug_9};5h16: + * qm_dbg_bus = {19b0,dma_debug_vec};5h17: + * qm_dbg_bus = {8b0,dqm_diag_r}; + */ +#define QM_DEBUG_SEL 0x16000 + +/* Counter */ +#define QM_DEBUG_SEL_SELECT_SHIFT 0 +#define QM_DEBUG_SEL_SELECT_MASK 0x1f + +/* Enable register controlled debug select */ +#define QM_DEBUG_SEL_ENABLE_MASK 0x80000000 + + +/* + * Register - read-only + * + * Debug Bus sampling + */ +#define QM_DEBUG_BUS_LSB 0x16004 + +/* Data */ +#define QM_DEBUG_BUS_LSB_DATA_SHIFT 0 +#define QM_DEBUG_BUS_LSB_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Debug Bus sampling + */ +#define QM_DEBUG_BUS_MSB 0x16008 + +/* Data */ +#define QM_DEBUG_BUS_MSB_DATA_SHIFT 0 +#define QM_DEBUG_BUS_MSB_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Spare configuration for ECO purposes + */ +#define QM_QM_SPARE_CONFIG 0x1600c + +/* Data */ +#define QM_QM_SPARE_CONFIG_DATA_SHIFT 0 +#define QM_QM_SPARE_CONFIG_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and non-reprocessing packets from + * all queues + */ +#define QM_GOOD_LVL1_PKTS_CNT 0x16010 + +/* Counter */ +#define QM_GOOD_LVL1_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL1_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and non-reprocessing bytes from + * all queues + */ +#define QM_GOOD_LVL1_BYTES_CNT 0x16014 + +/* Counter */ +#define QM_GOOD_LVL1_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL1_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and reprocessing packets from all + * queues + */ +#define QM_GOOD_LVL2_PKTS_CNT 0x16018 + +/* Counter */ +#define QM_GOOD_LVL2_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL2_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of non-dropped and reprocessing bytes from all + * queues + */ +#define QM_GOOD_LVL2_BYTES_CNT 0x1601c + +/* Counter */ +#define QM_GOOD_LVL2_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_GOOD_LVL2_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of copied packets to the DDR from all queues + */ +#define QM_COPIED_PKTS_CNT 0x16020 + +/* Counter */ +#define QM_COPIED_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_COPIED_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of copied bytes to the DDR from all queues + */ +#define QM_COPIED_BYTES_CNT 0x16024 + +/* Counter */ +#define QM_COPIED_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_COPIED_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of aggregated packets from all queues + */ +#define QM_AGG_PKTS_CNT 0x16028 + +/* Counter */ +#define QM_AGG_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of aggregated bytes from all queues + */ +#define QM_AGG_BYTES_CNT 0x1602c + +/* Counter */ +#define QM_AGG_BYTES_CNT_COUNTER_SHIFT 0 +#define QM_AGG_BYTES_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 1-packet PD from all + * queues + */ +#define QM_AGG_1_PKTS_CNT 0x16030 + +/* Counter */ +#define QM_AGG_1_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_1_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 2-packet PD from all + * queues + */ +#define QM_AGG_2_PKTS_CNT 0x16034 + +/* Counter */ +#define QM_AGG_2_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_2_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 3-packet PD from all + * queues + */ +#define QM_AGG_3_PKTS_CNT 0x16038 + +/* Counter */ +#define QM_AGG_3_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_3_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets aggregated in a 4-packet PD from all + * queues + */ +#define QM_AGG_4_PKTS_CNT 0x1603c + +/* Counter */ +#define QM_AGG_4_PKTS_CNT_COUNTER_SHIFT 0 +#define QM_AGG_4_PKTS_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to WRED + */ +#define QM_WRED_DROP_CNT 0x16040 + +/* Counter */ +#define QM_WRED_DROP_CNT_COUNTER_SHIFT 0 +#define QM_WRED_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to FPM + * congestion indication + */ +#define QM_FPM_CONGESTION_DROP_CNT 0x16048 + +/* Counter */ +#define QM_FPM_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to DDR PD + * congestion + */ +#define QM_DDR_PD_CONGESTION_DROP_CNT 0x16050 + +/* Counter */ +#define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_DDR_PD_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to DDR + * byte congestion (number of bytes waiting to be copied exceeded the + * thresholds) + */ +#define QM_DDR_BYTE_CONGESTION_DROP_CNT 0x16054 + +/* Counter */ +#define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_DDR_BYTE_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to QM PD + * congestion (this value is limited by the DQM) + */ +#define QM_QM_PD_CONGESTION_DROP_CNT 0x16058 + +/* Counter */ +#define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_SHIFT 0 +#define QM_QM_PD_CONGESTION_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets requeued due to absolute address + * drops from all queues + */ +#define QM_QM_ABS_REQUEUE_CNT 0x1605c + +/* Counter */ +#define QM_QM_ABS_REQUEUE_CNT_COUNTER_SHIFT 0 +#define QM_QM_ABS_REQUEUE_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO0_STATUS 0x16060 + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO0_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO0_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO0_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO1_STATUS 0x16064 + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO1_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO1_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO1_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO2_STATUS 0x16068 + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO2_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO2_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO2_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_FPM_PREFETCH_FIFO3_STATUS 0x1606c + +/* Used words */ +#define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_SHIFT 0 +#define QM_FPM_PREFETCH_FIFO3_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_FPM_PREFETCH_FIFO3_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_FPM_PREFETCH_FIFO3_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_NORMAL_RMT_FIFO_STATUS 0x16070 + +/* Used words */ +#define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_NORMAL_RMT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_NORMAL_RMT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_NORMAL_RMT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS 0x16074 + +/* Used words */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_NON_DELAYED_RMT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_NON_DELAYED_RMT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS 0x16078 + +/* Used words */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_NON_DELAYED_OUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_NON_DELAYED_OUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_PRE_CM_FIFO_STATUS 0x1607c + +/* Used words */ +#define QM_PRE_CM_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_PRE_CM_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_PRE_CM_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_PRE_CM_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_CM_RD_PD_FIFO_STATUS 0x16080 + +/* Used words */ +#define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_CM_RD_PD_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_CM_RD_PD_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_CM_RD_PD_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_CM_WR_PD_FIFO_STATUS 0x16084 + +/* Used words */ +#define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_CM_WR_PD_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_CM_WR_PD_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_CM_WR_PD_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS 0x16088 + +/* Used words */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_CM_COMMON_INPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_CM_COMMON_INPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_BB0_OUTPUT_FIFO_STATUS 0x1608c + +/* Used words */ +#define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_BB0_OUTPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_BB0_OUTPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_BB0_OUTPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_BB1_OUTPUT_FIFO_STATUS 0x16090 + +/* Used words */ +#define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_BB1_OUTPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_BB1_OUTPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_BB1_OUTPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_BB1_INPUT_FIFO_STATUS 0x16094 + +/* Used words */ +#define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_BB1_INPUT_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_BB1_INPUT_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_BB1_INPUT_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_EGRESS_DATA_FIFO_STATUS 0x16098 + +/* Used words */ +#define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_EGRESS_DATA_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_EGRESS_DATA_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_EGRESS_DATA_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Register - read-only + * + * Holds the FIFO Status + */ +#define QM_EGRESS_RR_FIFO_STATUS 0x1609c + +/* Used words */ +#define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_SHIFT 0 +#define QM_EGRESS_RR_FIFO_STATUS_USED_WORDS_MASK 0xffff + +/* Empty */ +#define QM_EGRESS_RR_FIFO_STATUS_EMPTY_MASK 0x10000 + +/* Full */ +#define QM_EGRESS_RR_FIFO_STATUS_FULL_MASK 0x20000 + + +/* + * Registers - is [ 0 => 1 ] + * + * BB ROUTE Override: + * 0 - for QM_TOP1 - for RNR_GRID + */ +#define QM_BB_ROUTE_OVR(x) (0x160a0 + (x) * 0x4) + +/* BB rout address decode Override enable */ +#define QM_BB_ROUTE_OVR_OVR_EN_MASK 0x1 + +/* Destination ID */ +#define QM_BB_ROUTE_OVR_DEST_ID_SHIFT 8 +#define QM_BB_ROUTE_OVR_DEST_ID_MASK 0x3f00 + +/* Route Address */ +#define QM_BB_ROUTE_OVR_ROUTE_ADDR_SHIFT 16 +#define QM_BB_ROUTE_OVR_ROUTE_ADDR_MASK 0x3ff0000 + + +/* + * Register - read-only + * + * Holds the Ingress Status + */ +#define QM_QM_INGRESS_STAT 0x160b0 + +/* Stat */ +#define QM_QM_INGRESS_STAT_STAT_SHIFT 0 +#define QM_QM_INGRESS_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the Egress Status + */ +#define QM_QM_EGRESS_STAT 0x160b4 + +/* Stat */ +#define QM_QM_EGRESS_STAT_STAT_SHIFT 0 +#define QM_QM_EGRESS_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the CM Status + */ +#define QM_QM_CM_STAT 0x160b8 + +/* Stat */ +#define QM_QM_CM_STAT_STAT_SHIFT 0 +#define QM_QM_CM_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Holds the FPM Prefetch Status + */ +#define QM_QM_FPM_PREFETCH_STAT 0x160bc + +/* Stat */ +#define QM_QM_FPM_PREFETCH_STAT_STAT_SHIFT 0 +#define QM_QM_FPM_PREFETCH_STAT_STAT_MASK 0xffffffff + + +/* + * Register - read-only + * + * QM connect ack counter + */ +#define QM_QM_CONNECT_ACK_COUNTER 0x160c0 + +/* Pending SBPM Connect ACKs counter */ +#define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_SHIFT 0 +#define QM_QM_CONNECT_ACK_COUNTER_CONNECT_ACK_COUNTER_MASK 0xff + + +/* + * Register - read-only + * + * QM DDR WR reply Counter + */ +#define QM_QM_DDR_WR_REPLY_COUNTER 0x160c4 + +/* Pending DDR WR Replies counter */ +#define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_SHIFT 0 +#define QM_QM_DDR_WR_REPLY_COUNTER_DDR_WR_REPLY_COUNTER_MASK 0xff + + +/* + * Register - read-only + * + * QM DDR pipe byte counter + */ +#define QM_QM_DDR_PIPE_BYTE_COUNTER 0x160c8 + +/* Pending bytes to be copied to the DDR */ +#define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_SHIFT 0 +#define QM_QM_DDR_PIPE_BYTE_COUNTER_COUNTER_MASK 0xfffffff + + +/* + * Register - read-only + * + * Indicates the number of PDs currently in the Absolute address drop + * queue. + */ +#define QM_QM_ABS_REQUEUE_VALID_COUNTER 0x160cc + +/* Counter */ +#define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_SHIFT 0 +#define QM_QM_ABS_REQUEUE_VALID_COUNTER_COUNTER_MASK 0x7fff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * PD captured when an illegal PD was detected and the relevant interrupt + * was generated. + */ +#define QM_QM_ILLEGAL_PD_CAPTURE(x) (0x160d0 + (x) * 0x4) + +/* PD */ +#define QM_QM_ILLEGAL_PD_CAPTURE_PD_SHIFT 0 +#define QM_QM_ILLEGAL_PD_CAPTURE_PD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Last ingress processed PD capture + */ +#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE(x) (0x160e0 + (x) * 0x4) + +/* PD */ +#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_SHIFT 0 +#define QM_QM_INGRESS_PROCESSED_PD_CAPTURE_PD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Last copy machine processed PD capture + */ +#define QM_QM_CM_PROCESSED_PD_CAPTURE(x) (0x160f0 + (x) * 0x4) + +/* PD */ +#define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_SHIFT 0 +#define QM_QM_CM_PROCESSED_PD_CAPTURE_PD_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Counts the total number of packets dropped for all queues due to FPM + * pool priority thresholds. + * Counter per pool + */ +#define QM_FPM_POOL_DROP_CNT(x) (0x16100 + (x) * 0x4) + +/* Counter */ +#define QM_FPM_POOL_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_POOL_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * Counts the total number of packets dropped from all queues due to FPM + * user group priority thresholds. + * Counter per UG (0-3) + */ +#define QM_FPM_GRP_DROP_CNT(x) (0x16110 + (x) * 0x4) + +/* Counter */ +#define QM_FPM_GRP_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_GRP_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to buffer + * reservation mechanism. + */ +#define QM_FPM_BUFFER_RES_DROP_CNT 0x16120 + +/* Counter */ +#define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_SHIFT 0 +#define QM_FPM_BUFFER_RES_DROP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Register - read-only + * + * Counts the total number of packets dropped from all queues due to psram + * egress congestion. + */ +#define QM_PSRAM_EGRESS_CONG_DRP_CNT 0x16124 + +/* Counter */ +#define QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_SHIFT 0 +#define QM_PSRAM_EGRESS_CONG_DRP_CNT_COUNTER_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 2559 ] - read-only + * + * CM Residue - debug access + */ +#define QM_DATA(x) (0x20000 + (x) * 0x4) + +/* DATA */ +#define QM_DATA_DATA_SHIFT 0 +#define QM_DATA_DATA_MASK 0xffffffff + + +/* + * Register + * + * VPB Base address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE 0x40004 + +/* base */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * VPB mask address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK 0x40008 + +/* mask */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_VPB_MASK_MASK_MASK 0xffffffff + + +/* + * Register + * + * APB Base address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE 0x4000c + +/* base */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * APB mask address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK 0x40010 + +/* mask */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_APB_MASK_MASK_MASK 0xffffffff + + +/* + * Register + * + * DQM Base address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE 0x40014 + +/* base */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_BASE_BASE_MASK 0xffffffff + + +/* + * Register + * + * DQM mask address + */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK 0x40018 + +/* mask */ +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_SHIFT 0 +#define QM_XRDP_UBUS_TOP_QM_XRDP_UBUS_SLV_DQM_MASK_MASK_MASK 0xffffffff + + +/* + * Register + * + * The BBH supports working with different MAC types. + * Each MAC requires different interface and features. + * This register defines the type of MAC the BBH works with. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_MACTYPE 0x50000 + +/* MAC type */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_MACTYPE_TYPE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_MACTYPE_TYPE_MASK 0x7 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX 0x50004 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_DMASRC_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_DMASRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SDMASRC_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SDMASRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SBPMSRC_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_SBPMSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the module. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_FPMSRC_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_1_TX_FPMSRC_MASK 0x3f000000 + + +/* + * Register + * + * Each BBH unit has its own position on the BB tree. + * This position defines the Route address when approaching the Runner, + * S/DMA or S/BPM. + * The route is determined by a dedicated generic logic which uses the + * source id of the destination. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX 0x50008 + +/* + * source id. + * This id is used to determine the route to the 1st (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR0SRC_MASK 0x3f + +/* + * source id. + * This id is used to determine the route to the 2nd (out of possible 2 + * runners) which are responsible for sending PDs. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_PDRNR1SRC_MASK 0x3f00 + +/* + * source id. + * This id is used to determine the route to the Runner that is responsible + * for sending status messages (WAN only). +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_STSRNRSRC_MASK 0x3f0000 + +/* + * source id. + * This id is used to determine the route to the Runner which is + * responsible for sending DBR/Ghost messages (WAN only). +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBCFG_2_TX_MSGRNRSRC_MASK 0x3f000000 + + +/* + * Register + * + * Configurations for determining the address to read from the DDR/PSRAm + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX 0x5000c + +/* The data is arranged in the DDR in a fixed size buffers. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_BUFSIZE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_BUFSIZE_MASK 0x7 + +/* The packet offset byte resulotion. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_BYTERESUL_MASK 0x8 + +/* Static offset in 8-bytes resolution for non aggregated packets in DDR */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_SHIFT 4 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_DDRTXOFFSET_MASK 0x1ff0 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE0_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE0_MASK 0x7f0000 + +/* + * The size of the HN (Header number) in bytes. + * The BBH decides between size 0 and size 1 according to a bit in the PD +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE1_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRCFG_TX_HNSIZE1_MASK 0x7f000000 + + +/* + * Registers - is [ 0 => 1 ] + * + * Queue index address: + * The BBH requests a Packet descriptor from the Runner. + * The BBH writes the queue number in a predefined address at the Runner + * SRAM. + * The message serves also as a wake-up request to the Runner. + * This register defines the queue index address within the Runner address + * space. + * SKB address: + * When the packet is transmitted from absolute address, then, instead of + * releasing the BN, the BBH writes a 6 bits read counter into the Runner + * SRAM. + * It writes it into a pre-defined address + TCONT_NUM (for Ethernet + * TCONT_NUM = 0). + * This register defines the SKB free base address within the Runner + * address. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1(x) (0x50010 + (x) * 0x4) + +/* + * Defines the TCONT address within the Runner address space. + * The address is in 8 bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_TCONTADDR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_TCONTADDR_MASK 0xffff + +/* + * Defines the SKB free address within the Runner address space. + * The address is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_SKBADDR_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_1_SKBADDR_MASK 0xffff0000 + + +/* + * Registers - is [ 0 => 1 ] + * + * PD transfer process: + * -The Runner wont ACK the BBH; therefore the BBH wont wake the TX task. + * -The Runner will push the PDs into the BBH (without any wakeup from the + * BBH). + * -Each time that the BBH reads a PD from the PD FIFO, it will write the + * read pointer into a pre-defined address in the Runner. + * The pointer is 6 bits width (one bit larger than needed to distinguish + * between full and empty). + * -The Runner should manage the congestion over the PD FIFO (in the BBH) + * by reading the BBH read pointer prior to each PD write. + * -PD drop should be done by the Runner only. + * The BBH will drop PD when the FIFO is full and will count each drop. + * The BBH wont release the BN in this case. + * -There will be a full threshold, which can be smaller than the actual + * size of the FIFO. + * When the BBH will move from full to not full state, the BBH will wakeup + * the Runner. + * Note: + * all addresses are in 8 byte resolution. + * As the Runner memory is limited to 12 bits address, use the 12 lsb bits. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2(x) (0x50018 + (x) * 0x4) + +/* + * This field defins the address in the Runner memory space to which the + * read pointer is written. + * The address is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_PTRADDR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_PTRADDR_MASK 0xffff + +/* The number of the task that is responsible for sending PDs to the BBH */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_TASK_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_RNRCFG_2_TASK_MASK 0xf0000 + + +/* + * Register + * + * The BBH reads the packet data from the DDR in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the DMA + * memory space. + * The read descriptors are arranged in a predefined space in the DMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX 0x50020 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCSIZE_SHIFT 6 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_MAXREQ_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on read requests of a + * jumbo packet (>2K) +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * The BBH reads the packet data from the PSRAM in chunks (with a maximal + * size of 128 bytes). + * For each chunk the BBH writes a read request (descriptor) into the SDMA + * memory space. + * The read descriptors are arranged in a predefined space in the SDMA + * memory and managed in a cyclic FIFO style. + * A special configuration limits the maximum number of read requests. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX 0x50024 + +/* + * Defines the base address of the read request FIFO within the DMA address + * space. + * The value should be identical to the relevant configuration in the DMA. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCBASE_MASK 0x3f + +/* The size of the BBH read requests FIFO inside the DMA */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCSIZE_SHIFT 6 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_DESCSIZE_MASK 0xfc0 + +/* Defines the maximum allowed number of on-the-fly read requests. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_MAXREQ_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_MAXREQ_MASK 0x3f0000 + +/* + * When asserted, this bit forces urgent priority on the EPON read requests + * towards the DMA (relevant only for EPON BBH) +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_EPNURGNT_MASK 0x1000000 + +/* + * When asserted, this bit forces urgent priority on Jumbo packets (>2k) + * read requests +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SDMACFG_TX_JUMBOURGNT_MASK 0x2000000 + + +/* + * Register + * + * When packet transmission is done, the BBH releases the SBPM buffers. + * This register defines which release command is used: + * 1. + * Normal free with context2. + * Special free with context3. + * free without context + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG 0x50028 + +/* When this bit is enabled, the BBH will use free without context command. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_FREENOCNTXT_MASK 0x1 + +/* + * When this bit is enabled, the BBH will use special free with context + * command. + * This bit is relevant only if free without context_en is configured to 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_SPECIALFREE_MASK 0x2 + +/* maximum number of pending on the fly get next commands */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_MAXGN_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_SBPMCFG_MAXGN_MASK 0x1f00 + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEL(x) (0x5002c + (x) * 0x4) + +/* + * DDR TM base. + * The address is in bytes resolution. + * The address should be aligned to 128 bytes. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEL_DDRTMBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEL_DDRTMBASE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] + * + * The BBH calculate the DDR physical address according to the Buffer + * number and buffer size and then adds the DDR TM base. + * The DDR TM address space is divided to two - coherent and non coherent. + * The first register in this array defines the base address of the non + * coherent space and the second is for the coherent. + * The value of this register should match the relevant registers value in + * the BBH RX, QM and the Runner. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEH(x) (0x50034 + (x) * 0x4) + +/* MSB of DDR TM base. */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEH_DDRTMBASE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DDRTMBASEH_DDRTMBASE_MASK 0xff + + +/* + * Register + * + * The BBH orders data both from DDR and PSRAM. + * The returned data is stored in two FIFOs for reordering. + * The two FIFOs are implemented in a single RAM. + * This register defines the division of the RAM to two FIFOs. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL 0x5003c + +/* + * The size of the PSRAM data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the PSRAM. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMSIZE_MASK 0x3ff + +/* + * The size of the DDR data FIFO in 8 bytes resolution. + * The BBH uses this information for determining the amount of data that + * can be ordered from the DDR. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_DDRSIZE_SHIFT 10 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_DDRSIZE_MASK 0xffc00 + +/* + * the base address of the PSRAM data FIFO in 8 bytes resolution. + * The DDR data FIFO base address is always 0. + * In case the whole RAM is to be dedicated to PSRAM data, the base should + * be 0 as well, and the DDR FIFO size should be configured to 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMBASE_SHIFT 20 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DFIFOCTRL_PSRAMBASE_MASK 0x3ff00000 + + +/* + * Register + * + * configurations related to different arbitration processes (ordering PDs, + * ordering data) + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_ARB_CFG 0x50040 + +/* + * this configuration determines whether to give high priority to a current + * transmitting queue or not. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_ARB_CFG_HIGHTRXQ_MASK 0x1 + + +/* + * Register + * + * override configuration for the route of one of the peripherals + * (DMA/SDMMA/FPM/SBPM?Runners) + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE 0x50044 + +/* route address */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_ROUTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_ROUTE_MASK 0x3ff + +/* destination source id */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_DEST_SHIFT 10 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_DEST_MASK 0xfc00 + +/* enable */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_BBROUTE_EN_MASK 0x10000 + + +/* + * Registers - is [ 0 => 19 ] + * + * configuration which queue is managed by each of the two runners. + * Each register in this array configures 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_Q2RNR(x) (0x50048 + (x) * 0x4) + +/* Q0 configuration */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_Q2RNR_Q0_MASK 0x1 + +/* Q1 configuration */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_Q2RNR_Q1_MASK 0x2 + + +/* + * Register + * + * which task in the runner to wake-up when requesting a PD for a certain + * q. + * This register holds the task number of the first 8 queues. + * For queues 8-40 (if they exist) the task that will be waking is the one + * appearing in the PD_RNR_CFG regs, depending on which runner this queue + * is associated with. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK 0x500a0 + +/* task number for queue 0 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK0_MASK 0xf + +/* task number for queue 1 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK1_SHIFT 4 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK1_MASK 0xf0 + +/* task number for queue 2 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK2_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK2_MASK 0xf00 + +/* task number for queue 3 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK3_SHIFT 12 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK3_MASK 0xf000 + +/* task number for queue 4 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK4_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK4_MASK 0xf0000 + +/* task number for queue 5 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK5_SHIFT 20 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK5_MASK 0xf00000 + +/* task number for queue 6 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK6_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK6_MASK 0xf000000 + +/* task number for queue 7 */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK7_SHIFT 28 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_PERQTASK_TASK7_MASK 0xf0000000 + + +/* + * Register + * + * This register enables reset of internal units (for possible WA + * purposes). + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD 0x500b0 + +/* + * Writing 1 to this register will reset the segmentation context table. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_CNTXTRST_MASK 0x1 + +/* + * Writing 1 to this register will reset the PDs FIFOs. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_PDFIFORST_MASK 0x2 + +/* + * Writing 1 to this register will reset the DMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_DMAPTRRST_MASK 0x4 + +/* + * Writing 1 to this register will reset the SDMA write pointer. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SDMAPTRRST_MASK 0x8 + +/* + * Writing 1 to this register will reset the BPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_BPMFIFORST_MASK 0x10 + +/* + * Writing 1 to this register will reset the SBPM FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SBPMFIFORST_MASK 0x20 + +/* + * Writing 1 to this register will reset the order keeper FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_OKFIFORST_MASK 0x40 + +/* + * Writing 1 to this register will reset the DDR data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_DDRFIFORST_MASK 0x80 + +/* + * Writing 1 to this register will reset the SRAM data FIFO. + * The reset is done immediately. + * Reading this register will always return 0. + * This register is relevalt only for Ethernet. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SRAMFIFORST_MASK 0x100 + +/* + * Writing 1 to this register will reset the SKB pointers. + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_SKBPTRRST_MASK 0x200 + +/* + * Writing 1 to this register will reset the EPON status FIFOs (per queue + * 32 fifos). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_STSFIFORST_MASK 0x400 + +/* + * Writing 1 to this register will reset the EPON request FIFO (8 entries + * FIFO that holds the packet requests from the EPON MAC). + * The reset is done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_REQFIFORST_MASK 0x800 + +/* + * Writing 1 to this register will reset the EPON/GPON MSG FIFOThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_MSGFIFORST_MASK 0x1000 + +/* + * Writing 1 to this register will reset the GET NEXT FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_GNXTFIFORST_MASK 0x2000 + +/* + * Writing 1 to this register will reset the FIRST BN FIFOsThe reset is + * done immediately. + * Reading this register will always return 0. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_TXRSTCMD_FBNFIFORST_MASK 0x4000 + + +/* + * Register + * + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DBGSEL 0x500b4 + +/* + * This register selects 1 of 8 debug vectors. + * The selected vector is reflected to DBGOUTREG. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DBGSEL_DBGSEL_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_DBGSEL_DBGSEL_MASK 0x1f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL 0x500b8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * general purpose register + */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_GPR 0x500bc + +/* general purpose register */ +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_GPR_GPR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_COMMON_CFGS_GPR_GPR_MASK 0xffffffff + + +/* + * Register + * + * The BBH manages 40 queues for GPON or 32 queus for EPON (1 for each + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these 256 + * PDs. + * The size of the 1st BN FIFO and get-next FIFO is the same as the size of + * the PD FIFO of each queue. + * each register in this array defines the PD FIFO base of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE 0x50400 + +/* The base of PD FIFO for queue 0. */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE0_MASK 0x1ff + +/* The base of PD FIFO for queue 1. */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE1_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDBASE_FIFOBASE1_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH manages 40 queues for GPON and 32 queues for EPON (FIFO per + * TCONT/LLID). + * For each queue it manages a PD FIFO. + * A total of 256 PDs are available for all queues. + * For each Queue the SW configures the base and the size within these. + * each register in this array defines the PD FIFO size of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE 0x50450 + +/* + * The size of PD FIFO for queue 0. + * A value of n refers to n+1. + * For GPON, the max value is 0x7For EPON, the max value is 0xf +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE0_MASK 0x1ff + +/* + * The size of PD FIFO for queue 1. + * A value of n refers to n+1. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE1_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDSIZE_FIFOSIZE1_MASK 0x1ff0000 + + +/* + * Register + * + * When a FIFO occupancy is above this wakeup threshold, the BBH will not + * wake-up the Runner for sending a new PD. + * This threshold does not represent the actual size of the FIFO. + * If a PD will arrive from the Runner when the FIFO is above the + * threshold, it will not be dropped unless the FIFO is actually full. + * Each register defines the threshold of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH 0x50500 + +/* + * The wakeup threshold of the PD FIFO for queue 0. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH0_MASK 0xff + +/* + * The wakeup threshold of the PD FIFO for queue 1. + * A value of n refers to n+1. + * Relevant only for EPON BBH. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH1_SHIFT 8 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDWKUPH_WKUPTHRESH1_MASK 0xff00 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration for the + * rest (TCONTs 8-39). + * Each register in this array defines the threshold of 2 queues. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH 0x50550 + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT0_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT0_MASK 0xffff + +/* + * Defines the number of bytes for PDs pre fetch limited according to the + * total number of bytes. + * The value is in 8-bytes resolution. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT1_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_PDLIMIT1_MASK 0xffff0000 + + +/* + * Register + * + * The BBH requests PDs from the Runner and maintains a pre-fetch PDs FIFO. + * The PDs pre fetch is limited either by the PD FIFO configurable size or + * according to the total number of bytes (deducting bytes already + * requested/transmitted) for preventing HOL. + * Full configuration for the first 8 TCONT and one configuration per group + * of 8 TCONTs for the rest. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_EN 0x50600 + +/* + * This bit enables the above feature (PDs pre fetch limited according to + * the total number of bytes). +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PD_BYTE_TH_EN_PDLIMITEN_MASK 0x1 + + +/* + * Register + * + * The BBH manages 32 queues for EPON (FIFO per LLID). + * For each queue it manages a PD FIFO. + * Usually, the BBH orders PDs from the Runner in RR between all queues. + * In EPON BBH, if a FIFO occupancy is below this threshold, the queue will + * have higher priority in PD ordering arbitration (with RR between all the + * empty queues). + * This configuration is global for all queues. + * Relevant only for EPON BBH. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDEMPTY 0x50604 + +/* + * EPON PD FIFO empty threshold. + * A queue which its PD FIFO occupancy is below this threshold will have + * high priority in PD ordering arbitration. +*/ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDEMPTY_EMPTY_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_PDEMPTY_EMPTY_MASK 0xff + + +/* + * Register + * + * Transmit threshold in 8 bytes resolution. + * The BBH TX will not start to transmit data towards the XLMAC until the + * amount of data in the TX FIFO is larger than the threshold or if there + * is a complete packet in the FIFO. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH 0x50608 + +/* DDR Transmit threshold in 8 bytes resoltion */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_DDRTHRESH_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_DDRTHRESH_MASK 0x1ff + +/* SRAM Transmit threshold in 8 bytes resoltion */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_SRAMTHRESH_SHIFT 16 +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TXTHRESH_SRAMTHRESH_MASK 0x1ff0000 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that no traffic is about + * to arrive so the XLMAC may try to enter power saving mode. + * This register is used to enable this feature. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_EEE 0x5060c + +/* enable bit */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_EEE_EN_MASK 0x1 + + +/* + * Register + * + * The BBH is responsible for indicating the XLMAC that it should and + * calculate timestamp for the current packet that is being transmitted. + * The BBH gets the timestamping parameters in the PD and forward it to the + * XLMAC. + * This register is used to enable this feature. + */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TS 0x50610 + +/* enable bit */ +#define QM_BBH_TX_QM_BBHTX_LAN_CFGS_TS_EN_MASK 0x1 + + +/* + * Register - read-only + * + * This counter counts the number of received PD for packets to be + * transmitted from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD 0x50a00 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPD_SRAMPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received PDs for packets to be + * transmitted from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD 0x50a04 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPD_DDRPD_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP 0x50a08 + +/* + * This counter counts the number of PDs which were dropped due to PD FIFO + * full. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_PDDROP_PDDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of STS messages which were received from + * Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT 0x50a10 + +/* This counter counts the number of received status messages. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSCNT_STSCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of STS which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP 0x50a14 + +/* + * This counter counts the number of STS which were dropped due to PD FIFO + * full. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_STSDROP_STSDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG (DBR/Ghost) messages which were + * received from Runner. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT 0x50a18 + +/* This counter counts the number of received DBR/ghost messages. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGCNT_MSGCNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP 0x50a1c + +/* + * This counter counts the number of MSG which were dropped due to PD FIFO + * full. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_MSGDROP_MSGDROP_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number Get next responses with a null BN. + * It counts the packets for all TCONTs together. + * This counter is cleared when read and freezes when maximum value is + * reached. + * This counter is relevant for Ethernet only. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL 0x50a20 + +/* This counter counts the number Get next responses with a null BN. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_GETNEXTNULL_GETNEXTNULL_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of packets that were flushed (bn was + * released without sending the data to the EPON MAC) due to flush request. + * The counter is global for all queues. + * The counter is read clear. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS 0x50a24 + +/* This counter counts the number of flushed packets */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_FLUSHPKTS_FLSHPKTS_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of times a length error (mismatch between + * a request from the MAC and a PD from the Runner) occured. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR 0x50a28 + +/* This counter counts the number of times a length error occuered */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_LENERR_LENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter Counts aggregation length error events. + * If one or more of the packets in an aggregated PD is shorter than 60 + * bytes, this counter will be incremented by 1. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR 0x50a2c + +/* + * This counter counts the number of times an aggregation length error + * occuered +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_AGGRLENERR_AGGRLENERR_MASK 0xffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the SRAM. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT 0x50a30 + +/* + * This counter counts the number of packets which were transmitted from + * the SRAM. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMPKT_SRAMPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of received packets to be transmitted + * from the DDR. + * It counts the packets for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT 0x50a34 + +/* + * This counter counts the number of packets which were transmitted from + * the DDR. +*/ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRPKT_DDRPKT_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the SRAM. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE 0x50a38 + +/* This counter counts the number of transmitted bytes from the SRAM. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SRAMBYTE_SRAMBYTE_MASK 0xffffffff + + +/* + * Register - read-only + * + * This counter counts the number of transmitted bytes from the DDR. + * It counts the bytes for all queues together. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE 0x50a3c + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DDRBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Register + * + * writing to this register creates a rd_en pulse to the selected array the + * SW wants to access. + * Each bit in the register represents one of the arrays the SW can access. + * The address inside the array is determined in the previous register + * (sw_rd_address). + * When writing to this register the SW should assert only one bit. + * If more than one is asserted, The HW will return the value read from the + * lsb selected array. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN 0x50a40 + +/* rd from the PD FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDSEL_MASK 0x1 + +/* rd from the PD valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDVSEL_MASK 0x2 + +/* rd from the PD empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDEMPTYSEL_MASK 0x4 + +/* rd from the PD Full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFULLSEL_MASK 0x8 + +/* rd from the PD beliow empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDBEMPTYSEL_MASK 0x10 + +/* rd from the PD full for wakeup empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_PDFFWKPSEL_MASK 0x20 + +/* rd from the first BN array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNSEL_MASK 0x40 + +/* rd from the first BN valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNVSEL_MASK 0x80 + +/* rd from the first BN empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNEMPTYSEL_MASK 0x100 + +/* rd from the first BN full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_FBNFULLSEL_MASK 0x200 + +/* rd from the first Get Next array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTSEL_MASK 0x400 + +/* rd from the get_next valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTVSEL_MASK 0x800 + +/* rd from the get next empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTEMPTYSEL_MASK 0x1000 + +/* rd from the get next full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GETNEXTFULLSEL_MASK 0x2000 + +/* rd from the gpon context array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_GPNCNTXTSEL_MASK 0x4000 + +/* rd from the BPM FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMSEL_MASK 0x8000 + +/* rd from the BPM FLUSH FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_BPMFSEL_MASK 0x10000 + +/* rd from the SBPM FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMSEL_MASK 0x20000 + +/* rd from the SBPM FLUSH FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_SBPMFSEL_MASK 0x40000 + +/* rd from the STS FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSSEL_MASK 0x80000 + +/* rd from the STS valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSVSEL_MASK 0x100000 + +/* rd from the STS empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSEMPTYSEL_MASK 0x200000 + +/* rd from the STS Full array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFULLSEL_MASK 0x400000 + +/* rd from the STS beliow empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSBEMPTYSEL_MASK 0x800000 + +/* rd from the STS full for wakeup empty array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_STSFFWKPSEL_MASK 0x1000000 + +/* rd from the MSG FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGSEL_MASK 0x2000000 + +/* rd from the msg valid array */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MSGVSEL_MASK 0x4000000 + +/* rd from the epon request FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_EPNREQSEL_MASK 0x8000000 + +/* rd from the DATA FIFO (SRAM and DDR) */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_DATASEL_MASK 0x10000000 + +/* rd from the reorder FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_REORDERSEL_MASK 0x20000000 + +/* rd from the Timestamp Info FIFO */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_TSINFOSEL_MASK 0x40000000 + +/* rd from the MAC TX FIFO. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDEN_MACTXSEL_MASK 0x80000000 + + +/* + * Register + * + * the address inside the array the SW wants to read + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR 0x50a44 + +/* The address inside the array the sw wants to read */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDADDR_RDADDR_MASK 0x7ff + + +/* + * Register - read-only + * + * indirect memories and arrays read data + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA 0x50a48 + +/* data */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_SWRDDATA_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted packets through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDPKT(x) (0x50a50 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDPKT_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * This counter array counts the number of transmitted bytes through each + * interface in the unified BBH. + * This counter is cleared when read and freezes when maximum value is + * reached. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDBYTE(x) (0x50a70 + (x) * 0x4) + +/* This counter counts the number of transmitted bytes from the DDr. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_UNIFIEDBYTE_DDRBYTE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 31 ] - read-only + * + * an array including all the debug vectors of the BBH TX. + * entries 30 and 31 are DSL debug. + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG(x) (0x50a90 + (x) * 0x4) + +/* Selected debug vector. */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_DBGOUTREG_DBGVEC_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 1 ] - read-only + * + * 40 bit vector in which each bit represents if the segmentation SM is + * currently handling a PD of a certain TCONT. + * first address is for TCONTS [31: + * 0]second is for TCONTS [39: + * 32] + */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_IN_SEGMENTATION(x) (0x50b20 + (x) * 0x4) + +/* in_segmentation indication */ +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_SHIFT 0 +#define QM_BBH_TX_QM_BBHTX_DEBUG_COUNTERS_IN_SEGMENTATION_IN_SEGMENTATION_MASK 0xffffffff + + +/* + * Register + * + * Broadbus route override + */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD 0x60000 + +/* destination ID */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_DEST_MASK 0x3f + +/* the route to be used (override the default route) */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_ROUTE_MASK 0x3ff00 + +/* override enable */ +#define QM_DMA_QM_DMA_CONFIG_BBROUTEOVRD_OVRD_MASK 0x1000000 + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers defines the memory allocation for the + * peripherals, for upstream. + * The allocation is of number of 128byte buffers out of the total 48 + * buffers for both sdma and dma. + * The allocation is done by defining a only the number of allocated + * buffers. + * base address is calculated by HW, when base of peripheral 0 is 0. + * Note that the memory allocation should not contain wrap around. + * The number of allocated CDs is the same of data buffers. + */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES(x) (0x60004 + (x) * 0x4) + +/* the number of 128bytes buffers allocated to the peripheral. */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_WRITES_NUMOFBUFF_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * This array of registers controls the number of read requests of each + * peripheral within the read requests RAM. + * total of 64 requests are divided between peripherals. + * Base address of peripheral 0 is 0, base of peripheral 1 is 0 + + * periph0_num_of_read_requests and so on. + */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS(x) (0x60024 + (x) * 0x4) + +/* number of read requests */ +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_NUM_OF_READS_RR_NUM_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] + * + * the in/out of urgent thresholds mark the number of write requests in the + * queue in which the peripherals priority is changed. + * The two thresholds should create hysteresis. + * The moving into urgent threshold must always be greater than the moving + * out of urgent threshold. + */ +#define QM_DMA_QM_DMA_CONFIG_U_THRESH(x) (0x60044 + (x) * 0x4) + +/* moving into urgent threshold */ +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_INTO_U_MASK 0x3f + +/* moving out ot urgent threshold */ +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_U_THRESH_OUT_OF_U_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The arbitration between the requests of the different peripherals is + * done in two stages: + * 1. + * Strict priority - chooses the peripherals with the highest priority + * among all perpherals who have a request pending. + * 2. + * Weighted Round-Robin between all peripherals with the same priority. + * This array of registers allow configuration of the priority of each + * peripheral (both rx and tx) in the following manner: + * There are 4 levels of priorities, when each bit in the register + * represents a different level of priority. + * One should assert the relevant bit according to the desired priority + * -For the lowest - 0001For the highest - 1000 + */ +#define QM_DMA_QM_DMA_CONFIG_PRI(x) (0x60064 + (x) * 0x4) + +/* priority of rx side (upload) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_PRI_RXPRI_MASK 0xf + +/* priority of tx side (download) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_SHIFT 4 +#define QM_DMA_QM_DMA_CONFIG_PRI_TXPRI_MASK 0xf0 + + +/* + * Registers - is [ 0 => 7 ] + * + * Broadbus source address of the DMA peripherals. + * Register per peripheral (rx and tx). + * The source is used to determine the route address to the different + * peripherals. + */ +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE(x) (0x60084 + (x) * 0x4) + +/* bb source of rx side (upload) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_RXSOURCE_MASK 0x3f + +/* bb source of tx side (download) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_PERIPH_SOURCE_TXSOURCE_MASK 0x3f00 + + +/* + * Registers - is [ 0 => 7 ] + * + * The second phase of the arbitration between requests is weighted round + * robin between requests of peripherals with the same priority. + * This array of registers allow configurtion of the weight of each + * peripheral (rx and tx). + * The actual weight will be weight + 1, meaning configuration of 0 is + * actual weight of 1. + */ +#define QM_DMA_QM_DMA_CONFIG_WEIGHT(x) (0x600a4 + (x) * 0x4) + +/* weight of rx side (upload) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_RXWEIGHT_MASK 0x7 + +/* weight of tx side (download) of the peripheral */ +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_WEIGHT_TXWEIGHT_MASK 0x700 + + +/* + * Register + * + * Resets the pointers of the peripherals FIFOs within the DMA. + * Bit per peripheral side (rx and tx). + * For rx side resets the data and CD FIFOs. + * For tx side resets the read requests FIFO. + */ +#define QM_DMA_QM_DMA_CONFIG_PTRRST 0x600d0 + +/* + * vector in which each bit represents a peripheral. + * LSB represent RX peripherals and MSB represent TX peripherals. + * When asserted, the relevant FIFOS of the selected peripheral will be + * reset to zero +*/ +#define QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_PTRRST_RSTVEC_MASK 0xffff + + +/* + * Register + * + * max number of on the fly read commands the DMA may issue to DDR before + * receiving any data. + */ +#define QM_DMA_QM_DMA_CONFIG_MAX_OTF 0x600d4 + +/* max on the fly */ +#define QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_MAX_OTF_MAX_MASK 0x3f + + +/* + * Register + * + * Clock Gate control register including timer config and bypass control + */ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL 0x600d8 + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_SHIFT 20 +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_INTRVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define QM_DMA_QM_DMA_CONFIG_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * debug bus select + */ +#define QM_DMA_QM_DMA_CONFIG_DBG_SEL 0x600e0 + +/* select */ +#define QM_DMA_QM_DMA_CONFIG_DBG_SEL_DBGSEL_SHIFT 0 +#define QM_DMA_QM_DMA_CONFIG_DBG_SEL_DBGSEL_MASK 0x3 + + +/* + * Register - read-only + * + * Each peripheral is represented in a bit on the not empty vector. + * LSB is for rx peripherals, MSB for tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * not empty. + * The not empty vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define QM_DMA_QM_DMA_DEBUG_NEMPTY 0x60100 + +/* indication of the queue state */ +#define QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_NEMPTY_NEMPTY_MASK 0xffff + + +/* + * Register - read-only + * + * Each peripheral, a is represented in a bit on the urgent vector. + * 8 LSB are rx peripherlas, 8 MSB are tx peripherals. + * If the bit is asserted, the requests queue of the relevant peripheral is + * in urgent state. + * The urgent vector is used by the DMA scheduler to determine which + * peripheral is the next to be served. + */ +#define QM_DMA_QM_DMA_DEBUG_URGNT 0x60104 + +/* indication whether the queue is in urgent state or not */ +#define QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_URGNT_URGNT_MASK 0xffff + + +/* + * Register - read-only + * + * The decision of the dma schedule rand the next peripheral to be served, + * represented by its source address + */ +#define QM_DMA_QM_DMA_DEBUG_SELSRC 0x60108 + +/* the next peripheral to be served by the dma */ +#define QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_SELSRC_SEL_SRC_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of write requests currently pending for each rx peripheral. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX(x) (0x60110 + (x) * 0x4) + +/* the number of pending write requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the number of read requestscurrently pending for each TX peripheral. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX(x) (0x60130 + (x) * 0x4) + +/* the number of pending read requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_REQ_CNT_MASK 0x3f + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of write requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC(x) (0x60150 + (x) * 0x4) + +/* the number of pending write requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_RX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * the accumulated number of read requests served so far for each + * peripheral. + * Wrap around on max value, not read clear. + */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC(x) (0x60170 + (x) * 0x4) + +/* the number of pending write requests */ +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_REQ_CNT_TX_ACC_REQ_CNT_MASK 0xffffffff + + +/* + * Register + * + * the address and cs of the ram the user wishes to read using the indirect + * access read mechanism. + */ +#define QM_DMA_QM_DMA_DEBUG_RDADD 0x60200 + +/* address within the ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_RDADD_ADDRESS_MASK 0x3ff + +/* chip select for write data ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_DATACS_MASK 0x10000 + +/* chip select for chunk descriptors ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_CDCS_MASK 0x20000 + +/* chip select for read requests ram */ +#define QM_DMA_QM_DMA_DEBUG_RDADD_RRCS_MASK 0x40000 + + +/* + * Register + * + * After determining the address and cs, the user should assert this bit + * for indicating that the address and cs are valid. + */ +#define QM_DMA_QM_DMA_DEBUG_RDVALID 0x60204 + +/* indirect read request is valid */ +#define QM_DMA_QM_DMA_DEBUG_RDVALID_VALID_MASK 0x1 + + +/* + * Registers - is [ 0 => 3 ] - read-only + * + * The returned read data from the selected RAM. + * Array of 4 registers (128 bits total). + * The width of the different memories is as follows: + * write data - 128 bitschunk descriptors - 36 bitsread requests - 42 + * bitsread data - 64 bitsThe the memories with width smaller than 128, the + * data will appear in the first registers of the array, for example: + * data from the cd RAM will appear in - {reg1[5: + * 0], reg0[31: + * 0]}. + */ +#define QM_DMA_QM_DMA_DEBUG_RDDATA(x) (0x60208 + (x) * 0x4) + +/* read data from ram */ +#define QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_SHIFT 0 +#define QM_DMA_QM_DMA_DEBUG_RDDATA_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * When assertd indicats that the data in the previous array is valid. + * Willremain asserted until the user deasserts the valid bit in regiser + * RDVALID. + */ +#define QM_DMA_QM_DMA_DEBUG_RDDATARDY 0x60218 + +/* read data ready */ +#define QM_DMA_QM_DMA_DEBUG_RDDATARDY_READY_MASK 0x1 + + +#endif /* ! XRDP_REGS_QM_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_rnr_quad.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_quad.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_rnr_quad.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_quad.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,1707 @@ +#ifndef XRDP_REGS_RNR_QUAD_H_ +#define XRDP_REGS_RNR_QUAD_H_ + +/* relative to core */ +#define RNR_QUAD_OFFSET_0 0xd08400 + +/* + * Register + * + * Engineering Configuration reserved for Broadlight use + */ +#define RNR_QUAD_PARSER_CORE_CFG_ENG 0x0 + +/* + * eng_cnfg[0] - IP filters on IPV6 on LSByte not MSByte + * eng_cnfg[1] - IP DAfields shows LSByte not MSbyte + * eng_cnfg[2] - enable error instead of brdcst at classifier summary word + * eng_cnfg[3] - Free + * eng_cnfg[8] - * Free + * eng_cnfg[9] - Free + * eng_cnfg[10] - Free + * eng_cnfg[11] - Free + * eng_cnfg[12] - Free + * eng_cnfg[13] - Free + * eng_cnfg[14] - mask of ah ext header excepetion + * eng_cnfg[15] - enable old mode of AH at IPV6 + * eng_cnfg[16] - enable old mode of AH at IPV4 + * eng_cnfg[17] - Free + * eng_cnfg[18] - dont allow 0xFFFF as valid ipv4 header cksum resultss +*/ +#define PARSER_CORE_CFG_ENG_CFG_SHIFT 0 +#define PARSER_CORE_CFG_ENG_CFG_MASK 0xffffffff + + +/* + * Register + * + * Parser Miscellaneous Configuration + */ +#define RNR_QUAD_PARSER_CORE_CFG_PARSER_MISC_CFG 0x4 + +/* + * Define which status bit cause exception bit in summary word to be set, + * the cuse vector is {4h0,ip fragment, ip version error, ip checksum + * error, ip_header length error} +*/ +#define PARSER_CORE_CFG_PARSER_MISC_CFG_EXCEPTION_EN_SHIFT 0 +#define PARSER_CORE_CFG_PARSER_MISC_CFG_EXCEPTION_EN_MASK 0x3fff + +/* + * Defines which TCP falgs set will cause TCP_FLAG bit in summary word to + * be set +*/ +#define PARSER_CORE_CFG_PARSER_MISC_CFG_TCP_FLAGS_FILT_SHIFT 16 +#define PARSER_CORE_CFG_PARSER_MISC_CFG_TCP_FLAGS_FILT_MASK 0xff0000 + +/* Profile US */ +#define PARSER_CORE_CFG_PARSER_MISC_CFG_PROFILE_US_SHIFT 28 +#define PARSER_CORE_CFG_PARSER_MISC_CFG_PROFILE_US_MASK 0x70000000 + + +/* + * Register + * + * Config VID Filter 0 & 1 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_0_1 0x8 + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_0_1_VID_0_SHIFT 0 +#define PARSER_CORE_CFG_VID_0_1_VID_0_MASK 0xfff + +/* VLAND ID Filter 0 Enable */ +#define PARSER_CORE_CFG_VID_0_1_VID_0_EN_MASK 0x8000 + +/* VLAN ID Filter 1 for second VLAN of register */ +#define PARSER_CORE_CFG_VID_0_1_VID_1_SHIFT 16 +#define PARSER_CORE_CFG_VID_0_1_VID_1_MASK 0xfff0000 + +/* VLAND ID Filter 1 Enable */ +#define PARSER_CORE_CFG_VID_0_1_VID_1_EN_MASK 0x80000000 + + +/* + * Register + * + * Config VID Filter 2 & 3 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_2_3 0xc + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_2_3_VID_2_SHIFT 0 +#define PARSER_CORE_CFG_VID_2_3_VID_2_MASK 0xfff + +/* VLAND ID Filter 2 Enable */ +#define PARSER_CORE_CFG_VID_2_3_VID_2_EN_MASK 0x8000 + +/* VLAN ID Filter 3 ofr second VLAN of register */ +#define PARSER_CORE_CFG_VID_2_3_VID_3_SHIFT 16 +#define PARSER_CORE_CFG_VID_2_3_VID_3_MASK 0xfff0000 + +/* VLAND ID Filter 3 Enable */ +#define PARSER_CORE_CFG_VID_2_3_VID_3_EN_MASK 0x80000000 + + +/* + * Register + * + * Config VID Filter 4 & 5 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_4_5 0x10 + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_4_5_VID_4_SHIFT 0 +#define PARSER_CORE_CFG_VID_4_5_VID_4_MASK 0xfff + +/* VLAND ID Filter 4 Enable */ +#define PARSER_CORE_CFG_VID_4_5_VID_4_EN_MASK 0x8000 + +/* VLAN ID Filter 5 ofr second VLAN of register */ +#define PARSER_CORE_CFG_VID_4_5_VID_5_SHIFT 16 +#define PARSER_CORE_CFG_VID_4_5_VID_5_MASK 0xfff0000 + +/* VLAND ID Filter 5 Enable */ +#define PARSER_CORE_CFG_VID_4_5_VID_5_EN_MASK 0x80000000 + + +/* + * Register + * + * Config VID Filter 6 & 7 + */ +#define RNR_QUAD_PARSER_CORE_CFG_VID_6_7 0x14 + +/* VLAN ID Filter for first VLAN of register */ +#define PARSER_CORE_CFG_VID_6_7_VID_6_SHIFT 0 +#define PARSER_CORE_CFG_VID_6_7_VID_6_MASK 0xfff + +/* VLAND ID Filter 6 Enable */ +#define PARSER_CORE_CFG_VID_6_7_VID_6_EN_MASK 0x8000 + +/* VLAN ID Filter 7 ofr second VLAN of register */ +#define PARSER_CORE_CFG_VID_6_7_VID_7_SHIFT 16 +#define PARSER_CORE_CFG_VID_6_7_VID_7_MASK 0xfff0000 + +/* VLAND ID Filter 7 Enable */ +#define PARSER_CORE_CFG_VID_6_7_VID_7_EN_MASK 0x80000000 + + +/* + * Register + * + * Config the IP Address filtering. + * Notice that the enable bit is located in the IP_FILTERS_CFG[4] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER0_CFG 0x18 + +/* + * 32-bit address to match SIP or DIP (according to predefined + * configuration in IP_FILTERS_CFG register) +*/ +#define PARSER_CORE_CFG_IP_FILTER0_CFG_IP_ADDRESS_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER0_CFG_IP_ADDRESS_MASK 0xffffffff + + +/* + * Register + * + * Config the IP Address filtering. + * Notice that the enable bit is located in the IP_FILTERS_CFG[5] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER1_CFG 0x1c + +/* + * 32-bit address to match SIP or DIP (according to predefined + * configuration in IP_FILTERS_CFG register) +*/ +#define PARSER_CORE_CFG_IP_FILTER1_CFG_IP_ADDRESS_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER1_CFG_IP_ADDRESS_MASK 0xffffffff + + +/* + * Register + * + * Config the IP Address masking. + * Notice that the enable bit is located in the IP_FILTERS_CFG[4] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER0_MASK_CFG 0x28 + +/* 32-bit address mask */ +#define PARSER_CORE_CFG_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER0_MASK_CFG_IP_ADDRESS_MASK_MASK 0xffffffff + + +/* + * Register + * + * Config the IP Address masking. + * Notice that the enable bit is located in the IP_FILTERS_CFG[5] + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTER1_MASK_CFG 0x2c + +/* 32-bit address mask */ +#define PARSER_CORE_CFG_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_SHIFT 0 +#define PARSER_CORE_CFG_IP_FILTER1_MASK_CFG_IP_ADDRESS_MASK_MASK 0xffffffff + + +/* + * Register + * + * IP Address Filters (0. + * .3) configurations: + * (1) SIP or DIP selection config per each filter(1) Valid bit per each + * filter + */ +#define RNR_QUAD_PARSER_CORE_CFG_IP_FILTERS_CFG 0x38 + +/* + * IP Filter0 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER0_DIP_EN_MASK 0x1 + +/* + * IP Filter1 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER1_DIP_EN_MASK 0x2 + +/* + * IP Filter2 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER2_DIP_EN_MASK 0x4 + +/* + * IP Filter3 DIP or SIP selection. + * The default is SIP, when the field is set -> DIP selection is enabled +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER3_DIP_EN_MASK 0x8 + +/* + * IP Filter0 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER0_VALID_MASK 0x10 + +/* + * IP Filter1 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER1_VALID_MASK 0x20 + +/* + * IP Filter2 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER2_VALID_MASK 0x40 + +/* + * IP Filter3 valid bit. + * When the bit valid is set, the IP filter/mask can be applied by + * hardware. +*/ +#define PARSER_CORE_CFG_IP_FILTERS_CFG_IP_FILTER3_VALID_MASK 0x80 + + +/* + * Register + * + * Identifies SNAP tunneling organization code + */ +#define RNR_QUAD_PARSER_CORE_CFG_SNAP_ORG_CODE 0x3c + +/* Used defined SNAP organization code */ +#define PARSER_CORE_CFG_SNAP_ORG_CODE_CODE_SHIFT 0 +#define PARSER_CORE_CFG_SNAP_ORG_CODE_CODE_MASK 0xffffff + +/* enable RFC1042 0x00000 organization code */ +#define PARSER_CORE_CFG_SNAP_ORG_CODE_EN_RFC1042_MASK 0x1000000 + +/* + * enables 802. + * 1Q 0x0000f8 organization code +*/ +#define PARSER_CORE_CFG_SNAP_ORG_CODE_EN_8021Q_MASK 0x2000000 + + +/* + * Register + * + * PPP Protocol Code to indicate L3 is IP + */ +#define RNR_QUAD_PARSER_CORE_CFG_PPP_IP_PROT_CODE 0x40 + +/* PPP Protocol code to identify L3 is IP */ +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_0_SHIFT 0 +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_0_MASK 0xffff + +/* PPP Protocol code to identify L3 is IP */ +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_1_SHIFT 16 +#define PARSER_CORE_CFG_PPP_IP_PROT_CODE_PPP_CODE_1_MASK 0xffff0000 + + +/* + * Register + * + * Ethertype values to identify the presence of VLAN QTAG + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_ETHTYPE 0x44 + +/* Ethertype to identify VLAN QTAG */ +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_0_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_0_MASK 0xffff + +/* Ethertype to identify VLAN QTAG */ +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_1_SHIFT 16 +#define PARSER_CORE_CFG_QTAG_ETHTYPE_ETHTYPE_QTAG_1_MASK 0xffff0000 + + +/* + * Register + * + * Configures user Ethertype values + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_ETHTYPE_0_1 0x48 + +/* User Ethertype 0 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_0_SHIFT 0 +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_0_MASK 0xffff + +/* User Ethertype 1 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_1_SHIFT 16 +#define PARSER_CORE_CFG_USER_ETHTYPE_0_1_ETHYPE_1_MASK 0xffff0000 + + +/* + * Register + * + * Configures user Ethertype values + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_ETHTYPE_2_3 0x4c + +/* User Ethertype 2 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_2_SHIFT 0 +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_2_MASK 0xffff + +/* User Ethertype 3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_3_SHIFT 16 +#define PARSER_CORE_CFG_USER_ETHTYPE_2_3_ETHYPE_3_MASK 0xffff0000 + + +/* + * Register + * + * Configure protocol and enables user Ethertype + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_ETHTYPE_CONFIG 0x50 + +/* Pointer to L3 protocol for User Ethertype 0 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_SHIFT 0 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_0_MASK 0x3 + +/* Pointer to L3 protocol for User Ethertype 1 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_SHIFT 2 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_1_MASK 0xc + +/* Pointer to L3 protocol for User Ethertype 2 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_SHIFT 4 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_2_MASK 0x30 + +/* Pointer to L3 protocol for User Ethertype 3 (0 - None, 1-IPv4, 2-IPv6) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_SHIFT 6 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_PROT_3_MASK 0xc0 + +/* Enable user Ethertype 3-0 (LSB is for user ethertype 0) */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_SHIFT 8 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_EN_MASK 0xf00 + +/* 4 byte offset for User Ethertype 0 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_SHIFT 16 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_0_MASK 0xf0000 + +/* 4 byte offset for User Ethertype 1 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_SHIFT 20 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_1_MASK 0xf00000 + +/* 4 byte offset for User Ethertype 2 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_SHIFT 24 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_2_MASK 0xf000000 + +/* 4 byte offset for User Ethertype 3 L3 */ +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_SHIFT 28 +#define PARSER_CORE_CFG_USER_ETHTYPE_CONFIG_ETHTYPE_USER_OFFSET_3_MASK 0xf0000000 + + +/* + * Register + * + * IPV6 Header Extension Filter Mask register + */ +#define RNR_QUAD_PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG 0x54 + +/* hop by hop match filter mask */ +#define PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG_HOP_BY_HOP_MATCH_MASK 0x1 + +/* Routing extension header option match filter mask */ +#define PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG_ROUTING_EH_MASK 0x2 + +/* Destination Options extension header option match filter mask */ +#define PARSER_CORE_CFG_IPV6_HDR_EXT_FLTR_MASK_CFG_DEST_OPT_EH_MASK 0x4 + + +/* + * Register + * + * Qtag Nesting config + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_NEST 0x58 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_0_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_0_MASK 0x7 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_1_SHIFT 3 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_1_MASK 0x38 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_2_SHIFT 6 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_0_PROFILE_2_MASK 0x1c0 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_0_SHIFT 9 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_0_MASK 0xe00 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_1_SHIFT 12 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_1_MASK 0x7000 + +/* + * Set to enable Ethertype_qTag 0 as outer (LSB) 2nd VLAN (2nd), 3rd VLAN + * (MSB) +*/ +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_2_SHIFT 15 +#define PARSER_CORE_CFG_QTAG_NEST_QTAG_NEST_1_PROFILE_2_MASK 0x38000 + + +/* + * Register + * + * QTAG Hard Nest Profile 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_HARD_NEST_0 0x5c + +/* + * bit 2-0: + * Enable 8100 as VLAN for outer, 2nd, and inner VLANs (inner is bit 2). + * bit 5-3: + * Enable 88a8 as VLAN for outer, 2nd, and inner VLANs. + * bit 8-6: + * Enable 9100 as VLAN for outer, 2nd, and inner VLANs. + * bit 11-9: + * Enable 9200 as VLAN for outer, 2nd, and inner VLANs. +*/ +#define PARSER_CORE_CFG_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_HARD_NEST_0_HARD_NEST_PROFILE_MASK 0xfff + + +/* + * Register + * + * QTAG Hard Nest Profile 1 + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_HARD_NEST_1 0x60 + +/* Hard Nest Profile */ +#define PARSER_CORE_CFG_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_HARD_NEST_1_HARD_NEST_PROFILE_MASK 0xfff + + +/* + * Register + * + * QTAG Hard Nest Profile 2 + */ +#define RNR_QUAD_PARSER_CORE_CFG_QTAG_HARD_NEST_2 0x64 + +/* Hard Nest Profile */ +#define PARSER_CORE_CFG_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_SHIFT 0 +#define PARSER_CORE_CFG_QTAG_HARD_NEST_2_HARD_NEST_PROFILE_MASK 0xfff + + +/* + * Register + * + * IP Protocols to be matched to IP Protocol field and to be indicated in + * the output summary word + */ +#define RNR_QUAD_PARSER_CORE_CFG_USER_IP_PROT 0x68 + +/* User defined IP protocol 0 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_0_SHIFT 0 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_0_MASK 0xff + +/* User defined IP protocol 1 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_1_SHIFT 8 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_1_MASK 0xff00 + +/* User defined IP protocol 2 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_2_SHIFT 16 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_2_MASK 0xff0000 + +/* User defined IP protocol 3 (value to be matched to IP protocol field) */ +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_3_SHIFT 24 +#define PARSER_CORE_CFG_USER_IP_PROT_USER_IP_PROT_3_MASK 0xff000000 + + +/* + * Register + * + * Config DA filter 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_VAL_L 0x70 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT0_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter0 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_VAL_H 0x74 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT0_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter1 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_VAL_L 0x78 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT1_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter1 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_VAL_H 0x7c + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT1_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter2 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT2_VAL_L 0x80 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT2_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT2_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter2 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT2_VAL_H 0x84 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT2_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT2_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter3 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT3_VAL_L 0x88 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT3_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT3_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA filter3 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT3_VAL_H 0x8c + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT3_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT3_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter4 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT4_VAL_L 0x90 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT4_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT4_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter4 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT4_VAL_H 0x94 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT4_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT4_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter5 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT5_VAL_L 0x98 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT5_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT5_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter5 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT5_VAL_H 0x9c + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT5_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT5_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter6 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT6_VAL_L 0xa0 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT6_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT6_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter6 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT6_VAL_H 0xa4 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT6_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT6_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter7 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT7_VAL_L 0xa8 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT7_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT7_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter7 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT7_VAL_H 0xac + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT7_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT7_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA filter8 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT8_VAL_L 0xb0 + +/* + * DA Filter bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT8_VAL_L_DA_FILT_LSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT8_VAL_L_DA_FILT_LSB_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter8 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT8_VAL_H 0xb4 + +/* + * Current DA Filter bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT8_VAL_H_DA_FILT_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT8_VAL_H_DA_FILT_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA Filter mask 15: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_MASK_L 0xc8 + +/* + * Current DA Filter mask bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT0_MASK_L_DA_FILT_MASK_L_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_MASK_L_DA_FILT_MASK_L_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter0 mask 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT0_MASK_H 0xcc + +/* + * Current DA Filter mask bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT0_MASK_H_DA_FILT_MASK_MSB_MASK 0xffff + + +/* + * Register + * + * Config DA Filter1 mask 31: + * 0 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_MASK_L 0xd0 + +/* + * Current DA Filter mask bits 31: + * 0 +*/ +#define PARSER_CORE_CFG_DA_FILT1_MASK_L_DA_FILT_MASK_L_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_MASK_L_DA_FILT_MASK_L_MASK 0xffffffff + + +/* + * Register + * + * Config DA Filter1 mask 47: + * 32 + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT1_MASK_H 0xd4 + +/* + * Current DA Filter mask bits 47: + * 32 +*/ +#define PARSER_CORE_CFG_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_SHIFT 0 +#define PARSER_CORE_CFG_DA_FILT1_MASK_H_DA_FILT_MASK_MSB_MASK 0xffff + + +/* + * Register + * + * Valid configuration of all DA filters: + * there is a dedicated bit per each DA filter that says if the current DA + * filter is valid or not. + * Used for on-the-fly DA filter value (mask) modifications, since the DA + * filter parameters are not assigned on single SW register. + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT_VALID_CFG_0 0xd8 + +/* DA Filter0 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT0_VALID_MASK 0x1 + +/* DA Filter1 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT1_VALID_MASK 0x2 + +/* DA Filter2 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT2_VALID_MASK 0x4 + +/* DA Filter3 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT3_VALID_MASK 0x8 + +/* DA Filter4 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT4_VALID_MASK 0x10 + +/* DA Filter5 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT5_VALID_MASK 0x20 + +/* DA Filter6 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT6_VALID_MASK 0x40 + +/* DA Filter7 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT7_VALID_MASK 0x80 + +/* DA Filter8 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_0_DA_FILT8_VALID_MASK 0x100 + + +/* + * Register + * + * Valid configuration of all DA filters: + * there is a dedicated bit per each DA filter that says if the current DA + * filter is valid or not. + * Used for on-the-fly DA filter value (mask) modifications, since the DA + * filter parameters are not assigned on single SW register. + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT_VALID_CFG_1 0xdc + +/* DA Filter0 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT0_VALID_MASK 0x1 + +/* DA Filter1 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT1_VALID_MASK 0x2 + +/* DA Filter2 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT2_VALID_MASK 0x4 + +/* DA Filter3 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT3_VALID_MASK 0x8 + +/* DA Filter4 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT4_VALID_MASK 0x10 + +/* DA Filter5 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT5_VALID_MASK 0x20 + +/* DA Filter6 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT6_VALID_MASK 0x40 + +/* DA Filter7 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT7_VALID_MASK 0x80 + +/* DA Filter8 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_1_DA_FILT8_VALID_MASK 0x100 + + +/* + * Register + * + * Valid configuration of all DA filters: + * there is a dedicated bit per each DA filter that says if the current DA + * filter is valid or not. + * Used for on-the-fly DA filter value (mask) modifications, since the DA + * filter parameters are not assigned on single SW register. + */ +#define RNR_QUAD_PARSER_CORE_CFG_DA_FILT_VALID_CFG_2 0xe0 + +/* DA Filter0 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT0_VALID_MASK 0x1 + +/* DA Filter1 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT1_VALID_MASK 0x2 + +/* DA Filter2 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT2_VALID_MASK 0x4 + +/* DA Filter3 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT3_VALID_MASK 0x8 + +/* DA Filter4 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT4_VALID_MASK 0x10 + +/* DA Filter5 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT5_VALID_MASK 0x20 + +/* DA Filter6 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT6_VALID_MASK 0x40 + +/* DA Filter7 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT7_VALID_MASK 0x80 + +/* DA Filter8 valid bit */ +#define PARSER_CORE_CFG_DA_FILT_VALID_CFG_2_DA_FILT8_VALID_MASK 0x100 + + +/* + * Register + * + * GRE Protocol + */ +#define RNR_QUAD_PARSER_CORE_CFG_GRE_PROTOCOL_CFG 0xe4 + +/* GRE_PROTOCOL */ +#define PARSER_CORE_CFG_GRE_PROTOCOL_CFG_GRE_PROTOCOL_SHIFT 0 +#define PARSER_CORE_CFG_GRE_PROTOCOL_CFG_GRE_PROTOCOL_MASK 0xffff + + +/* + * Register + * + * Prop Tag Configuration + */ +#define RNR_QUAD_PARSER_CORE_CFG_PROP_TAG_CFG 0xe8 + +/* profile 0 tag size, valid values are 0,2,4,6,8 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_0_SHIFT 0 +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_0_MASK 0x1f + +/* profile 1 tag size, valid values are 0,2,4,6,8 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_1_SHIFT 5 +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_1_MASK 0x3e0 + +/* profile 2 tag size, valid values are 0,2,4,6,8 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_2_SHIFT 10 +#define PARSER_CORE_CFG_PROP_TAG_CFG_SIZE_PROFILE_2_MASK 0x7c00 + +/* Pre-DA Profile 0 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_PRE_DA_DPROFILE_0_MASK 0x8000 + +/* Pre-DA Profile 1 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_PRE_DA_DPROFILE_1_MASK 0x10000 + +/* Pre-DA Profile 2 */ +#define PARSER_CORE_CFG_PROP_TAG_CFG_PRE_DA_DPROFILE_2_MASK 0x20000 + + +/* + * Register + * + * DMA arbiter Configuration + */ +#define RNR_QUAD_GENERAL_CONFIG_DMA_ARB_CFG 0x100 + +/* Select whether to use DDR FIFO only for DDR accesses */ +#define GENERAL_CONFIG_DMA_ARB_CFG_USE_FIFO_FOR_DDR_ONLY_MASK 0x1 + +/* Scheduling policy for token arbiter */ +#define GENERAL_CONFIG_DMA_ARB_CFG_TOKEN_ARBITER_IS_RR_MASK 0x2 + +/* + * chicken bit to disable external flow control. + * Packetw wil always be sent, no matter what token count says +*/ +#define GENERAL_CONFIG_DMA_ARB_CFG_CHICKEN_NO_FLOWCTRL_MASK 0x4 + +/* Set congestion threshold */ +#define GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_SHIFT 4 +#define GENERAL_CONFIG_DMA_ARB_CFG_CONGEST_THRESHOLD_MASK 0x1f0 + + +/* + * Register + * + * Configure PSRAM0 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_BASE 0x104 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM0_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM0_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM1 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_BASE 0x108 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM1_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM1_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM2 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_BASE 0x10c + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM2_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM2_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM3 base + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_BASE 0x110 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM3_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM3_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR0 base + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR0_BASE 0x114 + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR0_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR0_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR1 base + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR1_BASE 0x118 + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR1_BASE_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR1_BASE_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM0 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM0_MASK 0x11c + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM0_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM0_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM1 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM1_MASK 0x120 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM1_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM1_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM2 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM2_MASK 0x124 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM2_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM2_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure PSRAM3 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_PSRAM3_MASK 0x128 + +/* Value for base/mask */ +#define GENERAL_CONFIG_PSRAM3_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_PSRAM3_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR0 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR0_MASK 0x12c + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR0_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR0_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Configure DDR1 mask + */ +#define RNR_QUAD_GENERAL_CONFIG_DDR1_MASK 0x130 + +/* Value for base/mask */ +#define GENERAL_CONFIG_DDR1_MASK_VAL_SHIFT 0 +#define GENERAL_CONFIG_DDR1_MASK_VAL_MASK 0xffffffff + + +/* + * Register + * + * Profiling configuration + */ +#define RNR_QUAD_GENERAL_CONFIG_PROF_CONFIG 0x134 + +/* Select which 12-bits from 32-bit counter value to be recorded by tracer */ +#define GENERAL_CONFIG_PROF_CONFIG_COUNTER_LSB_SEL_SHIFT 0 +#define GENERAL_CONFIG_PROF_CONFIG_COUNTER_LSB_SEL_MASK 0x1f + +/* Enable tracing for core 0 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_0_MASK 0x100 + +/* Enable tracing for core 1 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_1_MASK 0x200 + +/* Enable tracing for core 2 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_2_MASK 0x400 + +/* Enable tracing for core 3 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_3_MASK 0x800 + +/* Enable tracing for core 4 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_4_MASK 0x1000 + +/* Enable tracing for core 5 */ +#define GENERAL_CONFIG_PROF_CONFIG_ENABLE_TRACE_CORE_5_MASK 0x2000 + + +/* + * Register + * + * Breakpoint 0 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_0_CFG 0x140 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_0_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_0_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_0_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_0_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 1 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_1_CFG 0x144 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_1_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_1_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_1_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_1_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 2 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_2_CFG 0x148 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_2_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_2_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_2_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_2_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 3 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_3_CFG 0x14c + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_3_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_3_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_3_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_3_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 4 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_4_CFG 0x150 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_4_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_4_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_4_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_4_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 5 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_5_CFG 0x154 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_5_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_5_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_5_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_5_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 6 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_6_CFG 0x158 + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_6_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_6_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_6_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_6_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint 7 configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_7_CFG 0x15c + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_7_CFG_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_7_CFG_ADDR_MASK 0x1fff + +/* Breakpoint address */ +#define GENERAL_CONFIG_BKPT_7_CFG_THREAD_SHIFT 16 +#define GENERAL_CONFIG_BKPT_7_CFG_THREAD_MASK 0xf0000 + + +/* + * Register + * + * Breakpoint general configuration. + */ +#define RNR_QUAD_GENERAL_CONFIG_BKPT_GEN_CFG 0x160 + +/* Breakpoint handler routine address */ +#define GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_SHIFT 0 +#define GENERAL_CONFIG_BKPT_GEN_CFG_HANDLER_ADDR_MASK 0x1fff + +/* New PC to be updated by breakpoint handler routine */ +#define GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_SHIFT 16 +#define GENERAL_CONFIG_BKPT_GEN_CFG_UPDATE_PC_VALUE_MASK 0x1fff0000 + + +/* + * Register + * + * Powersaving configuration + */ +#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_CONFIG 0x170 + +/* + * Select how many clocks to wait in IDLE condition before enetrin + * powersave state +*/ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_SHIFT 0 +#define GENERAL_CONFIG_POWERSAVE_CONFIG_TIME_COUNTER_MASK 0xff + +/* Enable powersavingfor core 0 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_0_MASK 0x100 + +/* Enable powersave for core 1 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_1_MASK 0x200 + +/* Enable powersave for core 2 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_2_MASK 0x400 + +/* Enable powersave for core 3 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_3_MASK 0x800 + +/* Enable powersave for core 4 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_4_MASK 0x1000 + +/* Enable powersave for core 5 */ +#define GENERAL_CONFIG_POWERSAVE_CONFIG_ENABLE_POWERSAVE_CORE_5_MASK 0x2000 + + +/* + * Register - read-only + * + * Powersave status indications + */ +#define RNR_QUAD_GENERAL_CONFIG_POWERSAVE_STATUS 0x174 + +/* Core 0 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_0_STATUS_MASK 0x1 + +/* Core 0 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_1_STATUS_MASK 0x2 + +/* Core 2 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_2_STATUS_MASK 0x4 + +/* Core 3 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_3_STATUS_MASK 0x8 + +/* Core 4 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_4_STATUS_MASK 0x10 + +/* Core 5 status */ +#define GENERAL_CONFIG_POWERSAVE_STATUS_CORE_5_STATUS_MASK 0x20 + + +/* + * Register + * + * FIFOs configuration + */ +#define RNR_QUAD_DEBUG_FIFO_CONFIG 0x200 + +/* Apply software reset to PSRAM header FIFO in EC arbiter */ +#define DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RST_MASK 0x1 + +/* Apply software reset to PSRAM data FIFO in EC arbiter */ +#define DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RST_MASK 0x2 + +/* Apply software reset to DDR header FIFO in EC arbiter */ +#define DEBUG_FIFO_CONFIG_DDR_HDR_SW_RST_MASK 0x4 + +/* Software read address for PSRAM header FIFO */ +#define DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_SHIFT 8 +#define DEBUG_FIFO_CONFIG_PSRAM_HDR_SW_RD_ADDR_MASK 0xf00 + +/* Software read address for PSRAM data FIFO */ +#define DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_SHIFT 12 +#define DEBUG_FIFO_CONFIG_PSRAM_DATA_SW_RD_ADDR_MASK 0xf000 + +/* Software read address for DDR header FIFO */ +#define DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_SHIFT 16 +#define DEBUG_FIFO_CONFIG_DDR_HDR_SW_RD_ADDR_MASK 0xf0000 + + +/* + * Register - read-only + * + * PSRAM Header FIFO status + */ +#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_STATUS 0x204 + +/* FIFO full indication */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Push write counter value */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_SHIFT 4 +#define DEBUG_PSRAM_HDR_FIFO_STATUS_PUSH_WR_CNTR_MASK 0x1f0 + +/* Pop read counter value */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_SHIFT 12 +#define DEBUG_PSRAM_HDR_FIFO_STATUS_POP_RD_CNTR_MASK 0x1f000 + +/* Used words value */ +#define DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_SHIFT 20 +#define DEBUG_PSRAM_HDR_FIFO_STATUS_USED_WORDS_MASK 0x1f00000 + + +/* + * Register - read-only + * + * PSRAM Data FIFO status + */ +#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_STATUS 0x208 + +/* FIFO full indication */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Almost FIFO full indication */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_ALMOST_FULL_MASK 0x4 + +/* Push write counter value */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_SHIFT 4 +#define DEBUG_PSRAM_DATA_FIFO_STATUS_PUSH_WR_CNTR_MASK 0x1f0 + +/* Pop read counter value */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_SHIFT 12 +#define DEBUG_PSRAM_DATA_FIFO_STATUS_POP_RD_CNTR_MASK 0x1f000 + +/* Used words value */ +#define DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_SHIFT 20 +#define DEBUG_PSRAM_DATA_FIFO_STATUS_USED_WORDS_MASK 0x1f00000 + + +/* + * Register - read-only + * + * DDR Header FIFO status + */ +#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_STATUS 0x20c + +/* FIFO full indication */ +#define DEBUG_DDR_HDR_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_DDR_HDR_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Push write counter value */ +#define DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_SHIFT 4 +#define DEBUG_DDR_HDR_FIFO_STATUS_PUSH_WR_CNTR_MASK 0x1f0 + +/* Pop read counter value */ +#define DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_SHIFT 12 +#define DEBUG_DDR_HDR_FIFO_STATUS_POP_RD_CNTR_MASK 0x1f000 + +/* Used words value */ +#define DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_SHIFT 20 +#define DEBUG_DDR_HDR_FIFO_STATUS_USED_WORDS_MASK 0x1f00000 + + +/* + * Register - read-only + * + * DDR Data FIFO status + */ +#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS 0x210 + +/* FIFO full indication */ +#define DEBUG_DDR_DATA_FIFO_STATUS_FULL_MASK 0x1 + +/* FIFO empty indication */ +#define DEBUG_DDR_DATA_FIFO_STATUS_EMPTY_MASK 0x2 + +/* Almost FIFO full indication */ +#define DEBUG_DDR_DATA_FIFO_STATUS_ALMOST_FULL_MASK 0x4 + +/* rite counter value */ +#define DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_SHIFT 4 +#define DEBUG_DDR_DATA_FIFO_STATUS_WR_CNTR_MASK 0x1ff0 + +/* Read counter value */ +#define DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_SHIFT 16 +#define DEBUG_DDR_DATA_FIFO_STATUS_RD_CNTR_MASK 0x1ff0000 + + +/* + * Register - read-only + * + * DDR Data FIFO status 2 + */ +#define RNR_QUAD_DEBUG_DDR_DATA_FIFO_STATUS2 0x214 + +/* Current read address */ +#define DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_SHIFT 0 +#define DEBUG_DDR_DATA_FIFO_STATUS2_READ_ADDR_MASK 0xff + +/* Used words */ +#define DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_SHIFT 8 +#define DEBUG_DDR_DATA_FIFO_STATUS2_USED_WORDS_MASK 0x1ff00 + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA1 0x220 + +/* Data */ +#define DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_SHIFT 0 +#define DEBUG_PSRAM_HDR_FIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_HDR_FIFO_DATA2 0x224 + +/* Data */ +#define DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_SHIFT 0 +#define DEBUG_PSRAM_HDR_FIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA1 0x228 + +/* Data */ +#define DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_SHIFT 0 +#define DEBUG_PSRAM_DATA_FIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_PSRAM_DATA_FIFO_DATA2 0x22c + +/* Data */ +#define DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_SHIFT 0 +#define DEBUG_PSRAM_DATA_FIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA1 0x230 + +/* Data */ +#define DEBUG_DDR_HDR_FIFO_DATA1_DATA_SHIFT 0 +#define DEBUG_DDR_HDR_FIFO_DATA1_DATA_MASK 0xffffffff + + +/* + * Register - read-only + * + * Read contents of FIFO memory + */ +#define RNR_QUAD_DEBUG_DDR_HDR_FIFO_DATA2 0x234 + +/* Data */ +#define DEBUG_DDR_HDR_FIFO_DATA2_DATA_SHIFT 0 +#define DEBUG_DDR_HDR_FIFO_DATA2_DATA_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 35 ] + * + * Token value for flow control + */ +#define RNR_QUAD_EXT_FLOWCTRL_CONFIG_TOKEN_VAL(x) (0x400 + (x) * 0x4) + +/* Value */ +#define EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_SHIFT 0 +#define EXT_FLOWCTRL_CONFIG_TOKEN_VAL_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * Decode for PSRAM Queue + */ +#define RNR_QUAD_UBUS_DECODE_CFG_PSRAM_UBUS_DECODE(x) (0x600 + (x) * 0x4) + +/* Value */ +#define UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_SHIFT 0 +#define UBUS_DECODE_CFG_PSRAM_UBUS_DECODE_VAL_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 15 ] + * + * Decode for DDR Queue + */ +#define RNR_QUAD_UBUS_DECODE_CFG_DDR_UBUS_DECODE(x) (0x640 + (x) * 0x4) + +/* Value */ +#define UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_SHIFT 0 +#define UBUS_DECODE_CFG_DDR_UBUS_DECODE_VAL_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_RNR_QUAD_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_rnr_regs.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_regs.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_rnr_regs.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_rnr_regs.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,570 @@ +#ifndef XRDP_REGS_RNR_REGS_H_ +#define XRDP_REGS_RNR_REGS_H_ + +/* relative to core */ +#define RNR_REGS_OFFSET_0 0xd00000 + +/* relative to core */ +#define RNR_REGS_OFFSET_1 0xd01000 + +/* relative to core */ +#define RNR_REGS_OFFSET_2 0xd02000 + +/* relative to core */ +#define RNR_REGS_OFFSET_3 0xd03000 + +/* relative to core */ +#define RNR_REGS_OFFSET_4 0xd04000 + +/* relative to core */ +#define RNR_REGS_OFFSET_5 0xd05000 + +/* + * Register + * + * Global control + */ +#define RNR_REGS_CFG_GLOBAL_CTRL 0x0 + +/* + * Runner enable. + * When reset runner pipe is halted, instruction memory and context memory + * can be accessed by the CPU. + * The CPU can reset or set this bitThe firmware can reset this bit by + * writing to the disable bit at the runner I/O control register. +*/ +#define CFG_GLOBAL_CTRL_EN_MASK 0x1 + +/* + * Notifies about DMA illegal access (>16 cycles on UBUS). + * Sticky bit. + * cleared by writing 1 to this bit. +*/ +#define CFG_GLOBAL_CTRL_DMA_ILLEGAL_STATUS_MASK 0x2 + +#define CFG_GLOBAL_CTRL_MICRO_SEC_VAL_SHIFT 8 +#define CFG_GLOBAL_CTRL_MICRO_SEC_VAL_MASK 0x3ff00 + +/* + * Register + * + * Writing to this register generates a request towards the runner + * scheduler. + */ +#define RNR_REGS_CFG_CPU_WAKEUP 0x4 + +/* The thread number to be invoked by the CPU. */ +#define CFG_CPU_WAKEUP_THREAD_NUM_SHIFT 0 +#define CFG_CPU_WAKEUP_THREAD_NUM_MASK 0xf + + +/* + * Register + * + * Interrupt control - UNUSED in 6858 + */ +#define RNR_REGS_CFG_INT_CTRL 0x8 + +/* + * While any of this field bits is set interrupt line 0 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT0_STS_SHIFT 0 +#define CFG_INT_CTRL_INT0_STS_MASK 0xff + +/* + * While any of this field bits is set interrupt line 0 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT1_STS_SHIFT 8 +#define CFG_INT_CTRL_INT1_STS_MASK 0xff00 + +/* + * While this bit is set interrupt line 2 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT2_STS_MASK 0x10000 + +/* + * While this bit is set interrupt line 3 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT3_STS_MASK 0x20000 + +/* + * While this bit is set interrupt line 4 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT4_STS_MASK 0x40000 + +/* + * While this bit is set interrupt line 5 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT5_STS_MASK 0x80000 + +/* + * While this bit is set interrupt line 6 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT6_STS_MASK 0x100000 + +/* + * While this bit is set interrupt line 6 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT7_STS_MASK 0x200000 + +/* + * While this bit is set interrupt line 8 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT8_STS_MASK 0x400000 + +/* + * While this bit is set interrupt line 9 is set. + * SW can write '1' to clear any bit. + * Write of '0' is ignored. +*/ +#define CFG_INT_CTRL_INT9_STS_MASK 0x800000 + +#define CFG_INT_CTRL_FIT_FAIL_STS_MASK 0x80000000 + +/* + * Register + * + * Interrupt mask - UNUSED in 6858 + */ +#define RNR_REGS_CFG_INT_MASK 0xc + +/* Mask INT0 causes */ +#define CFG_INT_MASK_INT0_MASK_SHIFT 0 +#define CFG_INT_MASK_INT0_MASK_MASK 0xff + +/* INT1 mask cause */ +#define CFG_INT_MASK_INT1_MASK_SHIFT 8 +#define CFG_INT_MASK_INT1_MASK_MASK 0xff00 + +/* INT2 mask cause */ +#define CFG_INT_MASK_INT2_MASK_MASK 0x10000 + +/* INT3 mask cause */ +#define CFG_INT_MASK_INT3_MASK_MASK 0x20000 + +/* INT4 mask cause */ +#define CFG_INT_MASK_INT4_MASK_MASK 0x40000 + +/* INT5 mask cause */ +#define CFG_INT_MASK_INT5_MASK_MASK 0x80000 + +/* INT6 mask cause */ +#define CFG_INT_MASK_INT6_MASK_MASK 0x100000 + +/* INT7 mask cause */ +#define CFG_INT_MASK_INT7_MASK_MASK 0x200000 + +/* INT8 mask cause */ +#define CFG_INT_MASK_INT8_MASK_MASK 0x400000 + +/* INT9 mask cause */ +#define CFG_INT_MASK_INT9_MASK_MASK 0x800000 + + +/* + * Register + * + * General configuration + */ +#define RNR_REGS_CFG_GEN_CFG 0x30 + +/* + * Disable DMA old flow control. + * When set to 1, DMA will not check read FIFO occupancy when issuing READ + * requests, relying instead on DMA backpressure mechanism vs read + * dispatcher block. +*/ +#define CFG_GEN_CFG_DISABLE_DMA_OLD_FLOW_CONTROL_MASK 0x1 + +/* set to 1 to test fit fail interrupt. */ +#define CFG_GEN_CFG_TEST_FIT_FAIL_MASK 0x2 + + +/* + * Register + * + * CAM configuration + */ +#define RNR_REGS_CFG_CAM_CFG 0x34 + +/* + * CAM operation is stopped when reaching an entry with a value matching + * this field. + * For a 32-bit or 64-bit CAM entries, this value is concatenated. +*/ +#define CFG_CAM_CFG_STOP_VALUE_SHIFT 0 +#define CFG_CAM_CFG_STOP_VALUE_MASK 0xffff + + +/* + * Register + * + * DMA DDR config Register. + * Contains configurations such as buffer size and ddr base address that + * are used for DDR address calculations (from buffer number) when DMA + * instruction addr_calc flag is set. + */ +#define RNR_REGS_CFG_DDR_CFG 0x40 + +/* DMA base address for ADDR_CALC */ +#define CFG_DDR_CFG_DMA_BASE_SHIFT 0 +#define CFG_DDR_CFG_DMA_BASE_MASK 0xfffff + +/* 3 bits indicating buffer size */ +#define CFG_DDR_CFG_DMA_BUF_SIZE_SHIFT 20 +#define CFG_DDR_CFG_DMA_BUF_SIZE_MASK 0x700000 + +/* DMA static offset */ +#define CFG_DDR_CFG_DMA_STATIC_OFFSET_SHIFT 24 +#define CFG_DDR_CFG_DMA_STATIC_OFFSET_MASK 0xff000000 + + +/* + * Register + * + * DMA PSRAM config Register. + * Contains configurations such as buffer size and ddr base address that + * are used for DDR address calculations (from buffer number) when DMA + * instruction addr_calc flag is set. + */ +#define RNR_REGS_CFG_PSRAM_CFG 0x44 + +/* DMA base address for ADDR_CALC */ +#define CFG_PSRAM_CFG_DMA_BASE_SHIFT 0 +#define CFG_PSRAM_CFG_DMA_BASE_MASK 0xfffff + +/* 3 bits indicating buffer size */ +#define CFG_PSRAM_CFG_DMA_BUF_SIZE_SHIFT 20 +#define CFG_PSRAM_CFG_DMA_BUF_SIZE_MASK 0x700000 + +/* DMA static offset */ +#define CFG_PSRAM_CFG_DMA_STATIC_OFFSET_SHIFT 24 +#define CFG_PSRAM_CFG_DMA_STATIC_OFFSET_MASK 0xff000000 + + +/* + * Register + * + * Ramrd mask for range search. + * The register holds 2 mask that can be chosen by runner core for range + * seraches. + */ +#define RNR_REGS_CFG_RAMRD_RANGE_MASK_CFG 0x48 + +/* + * Mask 0 for range serach. + * according to the number of 1 in the mask the cam machine can differ + * between the Key and TAG +*/ +#define CFG_RAMRD_RANGE_MASK_CFG_MASK0_SHIFT 0 +#define CFG_RAMRD_RANGE_MASK_CFG_MASK0_MASK 0xffff + +/* + * Mask 0 for range serach. + * according to the number of 1 in the mask the cam machine can differ + * between the Key and TAG +*/ +#define CFG_RAMRD_RANGE_MASK_CFG_MASK1_SHIFT 16 +#define CFG_RAMRD_RANGE_MASK_CFG_MASK1_MASK 0xffff0000 + + +/* + * Register + * + * scheduler configuration + */ +#define RNR_REGS_CFG_SCH_CFG 0x4c + +/* Configure priority mode for scheduler operation */ +#define CFG_SCH_CFG_SCHEDULER_MODE_SHIFT 0 +#define CFG_SCH_CFG_SCHEDULER_MODE_MASK 0x7 + + +/* + * Register + * + * breakpoint configuration + */ +#define RNR_REGS_CFG_BKPT_CFG 0x50 + +/* Enable breakpoint 0 */ +#define CFG_BKPT_CFG_BKPT_0_EN_MASK 0x1 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_0_USE_THREAD_MASK 0x2 + +/* Enable breakpoint 1 */ +#define CFG_BKPT_CFG_BKPT_1_EN_MASK 0x4 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_1_USE_THREAD_MASK 0x8 + +/* Enable breakpoint 2 */ +#define CFG_BKPT_CFG_BKPT_2_EN_MASK 0x10 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_2_USE_THREAD_MASK 0x20 + +/* Enable breakpoint 3 */ +#define CFG_BKPT_CFG_BKPT_3_EN_MASK 0x40 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_3_USE_THREAD_MASK 0x80 + +/* Enable breakpoint 4 */ +#define CFG_BKPT_CFG_BKPT_4_EN_MASK 0x100 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_4_USE_THREAD_MASK 0x200 + +/* Enable breakpoint 5 */ +#define CFG_BKPT_CFG_BKPT_5_EN_MASK 0x400 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_5_USE_THREAD_MASK 0x800 + +/* Enable breakpoint 6 */ +#define CFG_BKPT_CFG_BKPT_6_EN_MASK 0x1000 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_6_USE_THREAD_MASK 0x2000 + +/* Enable breakpoint 7 */ +#define CFG_BKPT_CFG_BKPT_7_EN_MASK 0x4000 + +/* Enable breakpoint for given thread only */ +#define CFG_BKPT_CFG_BKPT_7_USE_THREAD_MASK 0x8000 + +/* Configure step mode */ +#define CFG_BKPT_CFG_STEP_MODE_MASK 0x10000 + +/* Value for new flags */ +#define CFG_BKPT_CFG_NEW_FLAGS_VAL_SHIFT 20 +#define CFG_BKPT_CFG_NEW_FLAGS_VAL_MASK 0xf00000 + + +/* + * Register + * + * break point immediate + */ +#define RNR_REGS_CFG_BKPT_IMM 0x54 + +/* Enable immediate breakpoint */ +#define CFG_BKPT_IMM_ENABLE_MASK 0x1 + + +/* + * Register - read-only + * + * breakpoint status + */ +#define RNR_REGS_CFG_BKPT_STS 0x58 + +/* Breakpoint address */ +#define CFG_BKPT_STS_BKPT_ADDR_SHIFT 0 +#define CFG_BKPT_STS_BKPT_ADDR_MASK 0x1fff + +/* Breakpoint active indication */ +#define CFG_BKPT_STS_ACTIVE_MASK 0x10000 + + +/* + * Register - read-only + * + * Program counterstatus + */ +#define RNR_REGS_CFG_PC_STS 0x5c + +/* Current program counter address */ +#define CFG_PC_STS_CURRENT_PC_ADDR_SHIFT 0 +#define CFG_PC_STS_CURRENT_PC_ADDR_MASK 0x1fff + +/* Call stack return address */ +#define CFG_PC_STS_PC_RET_SHIFT 16 +#define CFG_PC_STS_PC_RET_MASK 0x1fff0000 + + +/* + * Register - read-only + * + * profiling status + */ +#define RNR_REGS_CFG_PROF_STS 0xb0 + +/* Trace write pointer */ +#define CFG_PROF_STS_TRACE_WRITE_PNT_SHIFT 0 +#define CFG_PROF_STS_TRACE_WRITE_PNT_MASK 0x1fff + +/* No active task */ +#define CFG_PROF_STS_IDLE_NO_ACTIVE_TASK_MASK 0x2000 + +/* Current thread num */ +#define CFG_PROF_STS_CURR_THREAD_NUM_SHIFT 14 +#define CFG_PROF_STS_CURR_THREAD_NUM_MASK 0x3c000 + +/* Status of profiling ON/OFF */ +#define CFG_PROF_STS_PROFILING_ACTIVE_MASK 0x40000 + +/* + * Sticky bit, indicating trace event FIFO overrun. + * Cleared by writing bit [31] of PROFILING_CFG_1 register +*/ +#define CFG_PROF_STS_TRACE_FIFO_OVERRUN_MASK 0x80000 + + +/* + * Register + * + * profiling confuguration 0 + */ +#define RNR_REGS_CFG_PROF_CFG_0 0xb4 + +/* Base address for trace buffer */ +#define CFG_PROF_CFG_0_TRACE_BASE_ADDR_SHIFT 0 +#define CFG_PROF_CFG_0_TRACE_BASE_ADDR_MASK 0x1fff + +/* Trace buffer MAX address */ +#define CFG_PROF_CFG_0_TRACE_MAX_ADDR_SHIFT 16 +#define CFG_PROF_CFG_0_TRACE_MAX_ADDR_MASK 0x1fff0000 + + +/* + * Register + * + * profiling confuguration 1 + */ +#define RNR_REGS_CFG_PROF_CFG_1 0xb8 + +/* Wraparound when writing trace buffer */ +#define CFG_PROF_CFG_1_TRACE_WRAPAROUND_MASK 0x1 + +/* Select all tasks or single task mode */ +#define CFG_PROF_CFG_1_TRACE_MODE_MASK 0x2 + +/* Select whether to log IDLE in context swap events */ +#define CFG_PROF_CFG_1_TRACE_DISABLE_IDLE_IN_MASK 0x4 + +/* + * Enable/disable logging of scheduler events (wakeups). + * Relevant only for single task mode +*/ +#define CFG_PROF_CFG_1_TRACE_DISABLE_WAKEUP_LOG_MASK 0x8 + +/* Select task for single task operation */ +#define CFG_PROF_CFG_1_TRACE_TASK_SHIFT 4 +#define CFG_PROF_CFG_1_TRACE_TASK_MASK 0xf0 + +/* Select mode for IDLE counter */ +#define CFG_PROF_CFG_1_IDLE_COUNTER_SOURCE_SEL_MASK 0x100 + +/* Apply software reset to event FIFO */ +#define CFG_PROF_CFG_1_TRACE_RESET_EVENT_FIFO_MASK 0x40000000 + +/* Write 1 to clear event FIFO overrun sticky bit */ +#define CFG_PROF_CFG_1_TRACE_CLEAR_FIFO_OVERRUN_MASK 0x80000000 + + +/* + * Register - read-only + * + * Display profiling counter value + */ +#define RNR_REGS_CFG_PROF_COUNTER 0xbc + +/* Current 32-bit value of counter */ +#define CFG_PROF_COUNTER_VAL_SHIFT 0 +#define CFG_PROF_COUNTER_VAL_MASK 0xffffffff + + +/* + * Register - read-only + * + * stall count + */ +#define RNR_REGS_CFG_STALL_CNT1 0xc0 + +/* Count load stalls */ +#define CFG_STALL_CNT1_LD_STALL_CNT_SHIFT 0 +#define CFG_STALL_CNT1_LD_STALL_CNT_MASK 0xffff + +/* Count accelerator stalls */ +#define CFG_STALL_CNT1_ACC_STALL_CNT_SHIFT 16 +#define CFG_STALL_CNT1_ACC_STALL_CNT_MASK 0xffff0000 + + +/* + * Register - read-only + * + * stall count + */ +#define RNR_REGS_CFG_STALL_CNT2 0xc4 + +/* Count load io stalls */ +#define CFG_STALL_CNT2_LDIO_STALL_CNT_SHIFT 0 +#define CFG_STALL_CNT2_LDIO_STALL_CNT_MASK 0xffff + +/* Count store stalls */ +#define CFG_STALL_CNT2_STORE_STALL_CNT_SHIFT 16 +#define CFG_STALL_CNT2_STORE_STALL_CNT_MASK 0xffff0000 + + +/* + * Register - read-only + * + * idle count + */ +#define RNR_REGS_CFG_IDLE_CNT1 0xc8 + +/* IDLE countReserved */ +#define CFG_IDLE_CNT1_IDLE_CNT_SHIFT 0 +#define CFG_IDLE_CNT1_IDLE_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Mispredicted jumps count + */ +#define RNR_REGS_CFG_JMP_CNT 0xcc + +/* Counts jumps with prediction miss, when prediction was dont jump */ +#define CFG_JMP_CNT_UNTAKEN_JMP_CNT_SHIFT 0 +#define CFG_JMP_CNT_UNTAKEN_JMP_CNT_MASK 0xffff + +/* Counts jumps with prediction miss, when prediction was jump */ +#define CFG_JMP_CNT_TAKEN_JMP_CNT_SHIFT 16 +#define CFG_JMP_CNT_TAKEN_JMP_CNT_MASK 0xffff0000 + + +/* + * Register + * + * 32 bit register for metal fixes. + */ +#define RNR_REGS_CFG_METAL_FIX_REG 0xf0 + +/* 32 bit register for metal fix */ +#define CFG_METAL_FIX_REG_METAL_FIX_SHIFT 0 +#define CFG_METAL_FIX_REG_METAL_FIX_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_RNR_REGS_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_sbpm.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_sbpm.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_sbpm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_sbpm.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,1204 @@ +#ifndef XRDP_REGS_SBPM_H_ +#define XRDP_REGS_SBPM_H_ + +/* relative to core */ +#define SBPM_OFFSET_0 0xd98000 + +/* + * Register + * + * request for building the free list using HW accelerator + */ +#define SBPM_REGS_INIT_FREE_LIST 0x0 + +/* init_base_addr */ +#define REGS_INIT_FREE_LIST_INIT_BASE_ADDR_SHIFT 0 +#define REGS_INIT_FREE_LIST_INIT_BASE_ADDR_MASK 0x3fff + +/* init_offset */ +#define REGS_INIT_FREE_LIST_INIT_OFFSET_SHIFT 14 +#define REGS_INIT_FREE_LIST_INIT_OFFSET_MASK 0xfffc000 + +/* + * The bit is used as busy indication of buffer allocation request status + * (busy status) by CPU. + * BPM asserts this bit on each valid request and de-asserts when request + * is treated. +*/ +#define REGS_INIT_FREE_LIST_BSY_MASK 0x40000000 + +/* + * The bit is used as ready indication of buffer allocation request status + * (ready status) by CPU. + * BPM asserts this bit when request is treated and de-asserts when new + * valid request is accepted, thus this is READY indication +*/ +#define REGS_INIT_FREE_LIST_RDY_MASK 0x80000000 + + +/* + * Register + * + * request for a new buffer + */ +#define SBPM_REGS_BN_ALLOC 0x4 + +/* + * Source address used by Alloc BN command (may be used for alloc on behalf + * another user) +*/ +#define REGS_BN_ALLOC_SA_SHIFT 14 +#define REGS_BN_ALLOC_SA_MASK 0xfc000 + + +/* + * Register - read-only + * + * reply for a new buffer alloc + */ +#define SBPM_REGS_BN_ALLOC_RPLY 0x8 + +/* alloc_bn_valid */ +#define REGS_BN_ALLOC_RPLY_ALLOC_BN_VALID_MASK 0x1 + +/* alloc_bn */ +#define REGS_BN_ALLOC_RPLY_ALLOC_BN_SHIFT 1 +#define REGS_BN_ALLOC_RPLY_ALLOC_BN_MASK 0x7ffe + +/* ack */ +#define REGS_BN_ALLOC_RPLY_ACK_MASK 0x8000 + +/* nack */ +#define REGS_BN_ALLOC_RPLY_NACK_MASK 0x10000 + +/* + * Exclusive bit is indication of Exclusive_high status of client with + * related Alloc request +*/ +#define REGS_BN_ALLOC_RPLY_EXCL_HIGH_MASK 0x20000 + +/* + * Exclusive bit is indication of Exclusive_low status of client with + * related Alloc request +*/ +#define REGS_BN_ALLOC_RPLY_EXCL_LOW_MASK 0x40000 + +/* busy */ +#define REGS_BN_ALLOC_RPLY_BUSY_MASK 0x40000000 + +/* rdy */ +#define REGS_BN_ALLOC_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * Request for freeing buffers of a packet offline with context (lower + * 32-bit) + */ +#define SBPM_REGS_BN_FREE_WITH_CONTXT_LOW 0xc + +/* head_bn */ +#define REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_SHIFT 0 +#define REGS_BN_FREE_WITH_CONTXT_LOW_HEAD_BN_MASK 0x3fff + +/* + * Source addres used for free comand (may be used for freeing BN on behalf + * another port) +*/ +#define REGS_BN_FREE_WITH_CONTXT_LOW_SA_SHIFT 14 +#define REGS_BN_FREE_WITH_CONTXT_LOW_SA_MASK 0xfc000 + +/* Offset (or length) = number of BNs in packet that is going to be freed */ +#define REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_SHIFT 24 +#define REGS_BN_FREE_WITH_CONTXT_LOW_OFFSET_MASK 0x7f000000 + +/* Ack request */ +#define REGS_BN_FREE_WITH_CONTXT_LOW_ACK_MASK 0x80000000 + + +/* + * Register + * + * Request for freeing buffers of a packet offline with context (higher + * 32-bit) + */ +#define SBPM_REGS_BN_FREE_WITH_CONTXT_HIGH 0x10 + +/* Last BN in packet that is going to be freed */ +#define REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_SHIFT 0 +#define REGS_BN_FREE_WITH_CONTXT_HIGH_LAST_BN_MASK 0x3fff + + +/* + * Register + * + * Multicast counter increment. + * Contains the BN, which is head of the packet to be multicast and its + * counter value + */ +#define SBPM_REGS_MCST_INC 0x14 + +/* bufer number */ +#define REGS_MCST_INC_BN_SHIFT 0 +#define REGS_MCST_INC_BN_MASK 0x3fff + +/* MCST value that should be added to current mulicast counter */ +#define REGS_MCST_INC_MCST_VAL_SHIFT 14 +#define REGS_MCST_INC_MCST_VAL_MASK 0x3fc000 + +/* Acknowledge request */ +#define REGS_MCST_INC_ACK_REQ_MASK 0x400000 + + +/* + * Register - read-only + * + * mcst_inc_rply + */ +#define SBPM_REGS_MCST_INC_RPLY 0x18 + +/* Acknowledge reply of MCST command */ +#define REGS_MCST_INC_RPLY_MCST_ACK_MASK 0x1 + +/* + * The bit is used as busy indication of MCST request status (busy status) + * by CPUSBPM asserts this bit on each valid request and de-asserts when + * request is treated: + * 1 - request is busy,0- request is not busy (ready) +*/ +#define REGS_MCST_INC_RPLY_BSY_MASK 0x40000000 + +/* + * The bit is used as ready indication of MCST request status (ready + * status) by CPU. + * SBPM asserts this bit when request is treated and de-asserts when new + * valid request is accepted, thus this is READY indication: + * 1 - request is ready,0- request is not ready (busy) +*/ +#define REGS_MCST_INC_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * request for connection between two buffers in a linked list. + * The connection request may be replied with ACK message if the ACK + * request bit is asserted. + * This command is used as write command. + */ +#define SBPM_REGS_BN_CONNECT 0x1c + +/* bn */ +#define REGS_BN_CONNECT_BN_SHIFT 0 +#define REGS_BN_CONNECT_BN_MASK 0x3fff + +/* ack_req for Connect command (should be always set) */ +#define REGS_BN_CONNECT_ACK_REQ_MASK 0x4000 + +/* Used for Direct Write (for work arround) */ +#define REGS_BN_CONNECT_WR_REQ_MASK 0x8000 + +/* pointed_bn */ +#define REGS_BN_CONNECT_POINTED_BN_SHIFT 16 +#define REGS_BN_CONNECT_POINTED_BN_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * bn_connect_rply + */ +#define SBPM_REGS_BN_CONNECT_RPLY 0x20 + +/* Acknowledge reply on Connect request */ +#define REGS_BN_CONNECT_RPLY_CONNECT_ACK_MASK 0x1 + +/* busy bit */ +#define REGS_BN_CONNECT_RPLY_BUSY_MASK 0x40000000 + +/* ready bit */ +#define REGS_BN_CONNECT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * a pointer to a buffer in a packet linked list and request for the next + * buffer in the listthis command is used as read command. + */ +#define SBPM_REGS_GET_NEXT 0x24 + +/* Get Next Buffer of current BN (used in this field) */ +#define REGS_GET_NEXT_BN_SHIFT 0 +#define REGS_GET_NEXT_BN_MASK 0x3fff + + +/* + * Register - read-only + * + * get_next_rply + */ +#define SBPM_REGS_GET_NEXT_RPLY 0x28 + +/* Used for validation of Next BN reply */ +#define REGS_GET_NEXT_RPLY_BN_VALID_MASK 0x1 + +/* Next BN - reply of Get_next command */ +#define REGS_GET_NEXT_RPLY_NEXT_BN_SHIFT 1 +#define REGS_GET_NEXT_RPLY_NEXT_BN_MASK 0x7ffe + +/* Next BN is null indication */ +#define REGS_GET_NEXT_RPLY_BN_NULL_MASK 0x8000 + +/* mcst cnt val */ +#define REGS_GET_NEXT_RPLY_MCNT_VAL_SHIFT 16 +#define REGS_GET_NEXT_RPLY_MCNT_VAL_MASK 0xff0000 + +/* Get Next command is busy */ +#define REGS_GET_NEXT_RPLY_BUSY_MASK 0x40000000 + +/* Get Next command is ready */ +#define REGS_GET_NEXT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * control for the bl_clk_control module + */ +#define SBPM_REGS_SBPM_CLK_GATE_CNTRL 0x2c + +/* + * If set to 1b1 will disable the clock gate logic such to always enable + * the clock +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_BYPASS_CLK_GATE_MASK 0x1 + +/* + * For how long should the clock stay active once all conditions for clock + * disable are met. +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_SHIFT 8 +#define REGS_SBPM_CLK_GATE_CNTRL_TIMER_VAL_MASK 0xff00 + +/* + * Enables the keep alive logic which will periodically enable the clock to + * assure that no deadlock of clock being removed completely will occur +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_EN_MASK 0x10000 + +/* + * If the KEEP alive option is enabled the field will determine for how + * many cycles should the clock be active +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_SHIFT 20 +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_INTERVL_MASK 0x700000 + +/* + * If the KEEP alive option is enabled this field will determine for how + * many cycles should the clock be disabled (minus the + * KEEP_ALIVE_INTERVAL)So KEEP_ALIVE_CYCLE must be larger than + * KEEP_ALIVE_INTERVAL. +*/ +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_SHIFT 24 +#define REGS_SBPM_CLK_GATE_CNTRL_KEEP_ALIVE_CYC_MASK 0xff000000 + + +/* + * Register + * + * bn_free_without_contxt + */ +#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT 0x38 + +/* Head BN = First BN in packet that is going to be freed */ +#define REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_SHIFT 0 +#define REGS_BN_FREE_WITHOUT_CONTXT_HEAD_BN_MASK 0x3fff + +/* + * source address used for command (may be used for performing command on + * behalf another port) +*/ +#define REGS_BN_FREE_WITHOUT_CONTXT_SA_SHIFT 14 +#define REGS_BN_FREE_WITHOUT_CONTXT_SA_MASK 0xfc000 + +/* ACK request - should be always set */ +#define REGS_BN_FREE_WITHOUT_CONTXT_ACK_REQ_MASK 0x80000000 + + +/* + * Register - read-only + * + * bn_free_without_contxt_rply + */ +#define SBPM_REGS_BN_FREE_WITHOUT_CONTXT_RPLY 0x3c + +/* Acknowledge on Free command */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_FREE_ACK_MASK 0x1 + +/* ACK status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_ACK_STAT_MASK 0x8000 + +/* NACK status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_NACK_STAT_MASK 0x10000 + +/* Exclusive_high status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_HIGH_STAT_MASK 0x20000 + +/* Exclusive_low status of CPU */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_EXCL_LOW_STAT_MASK 0x40000 + +/* Busy bit of command (command is currently in execution) */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_BSY_MASK 0x40000000 + +/* Ready bit of command (ready for new command execution) */ +#define REGS_BN_FREE_WITHOUT_CONTXT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register - read-only + * + * bn_free_with_contxt_rply + */ +#define SBPM_REGS_BN_FREE_WITH_CONTXT_RPLY 0x40 + +/* Free command acknowledge */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_FREE_ACK_MASK 0x1 + +/* ACK status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_ACK_STATE_MASK 0x8000 + +/* NACK status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_NACK_STATE_MASK 0x10000 + +/* Exclusive high status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_HIGH_STATE_MASK 0x20000 + +/* Exclusive low status of CPU */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_EXCL_LOW_STATE_MASK 0x40000 + +/* Busy bit of command */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_BUSY_MASK 0x40000000 + +/* Ready bit of command */ +#define REGS_BN_FREE_WITH_CONTXT_RPLY_RDY_MASK 0x80000000 + + +/* + * Register + * + * Global Threshold for Allocated Buffers. + * SBPM will issue BN in the accepted range upon to Global threshold setup. + * Ths register also holds global hysteresis value for ACK/NACK transition + * setting. + * We cross to Nack state if BAC equals the threshold. + * We cross down to Ack if BAC equals the thrshold minus the histeresis + * value. + */ +#define SBPM_REGS_SBPM_GL_TRSH 0x4c + +/* Global Threshold for Allocated BN = maximal total number of BNs in SBPM */ +#define REGS_SBPM_GL_TRSH_GL_BAT_SHIFT 0 +#define REGS_SBPM_GL_TRSH_GL_BAT_MASK 0x3fff + +/* + * Global Hysteresis for Allocated BN = hysteresis value related to maximal + * total threshold of SRAM BNs +*/ +#define REGS_SBPM_GL_TRSH_GL_BAH_SHIFT 16 +#define REGS_SBPM_GL_TRSH_GL_BAH_MASK 0x3fff0000 + + +/* + * Register + * + * Threshold for Allocated Buffers of UG0Ths register also holds UG0 + * hysteresis value for ACK/NACK transition setting. + * We cross to Nack state if BAC equals the threshold. + * We cross down to Ack if BAC equals the thrshold minus the histeresis + * value. + */ +#define SBPM_REGS_SBPM_UG0_TRSH 0x50 + +/* Current UG Threshold for Allocated BN */ +#define REGS_SBPM_UG0_TRSH_UG_BAT_SHIFT 0 +#define REGS_SBPM_UG0_TRSH_UG_BAT_MASK 0x3fff + +/* Current UG hysteresis Threshold for Allocated BN */ +#define REGS_SBPM_UG0_TRSH_UG_BAH_SHIFT 16 +#define REGS_SBPM_UG0_TRSH_UG_BAH_MASK 0x3fff0000 + + +/* + * Register + * + * Threshold for Allocated Buffers of UG1Ths register also holds UG1 + * hysteresis value for ACK/NACK transition setting. + * We cross to Nack state if BAC equals the threshold. + * We cross down to Ack if BAC equals the thrshold minus the histeresis + * value. + */ +#define SBPM_REGS_SBPM_UG1_TRSH 0x54 + +/* Current UG Threshold for Allocated BN */ +#define REGS_SBPM_UG1_TRSH_UG_BAT_SHIFT 0 +#define REGS_SBPM_UG1_TRSH_UG_BAT_MASK 0x3fff + +/* Current UG hysteresis delta Threshold for Allocated BN */ +#define REGS_SBPM_UG1_TRSH_UG_BAH_SHIFT 16 +#define REGS_SBPM_UG1_TRSH_UG_BAH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM select the debug bus + */ +#define SBPM_REGS_SBPM_DBG 0x74 + +/* + * select bus. + * the bus index should be mentioned in onehot writting: + * bus0 = 0001bus1 = 0010bus2 = 0100bus3 = 1000 +*/ +#define REGS_SBPM_DBG_SELECT_BUS_SHIFT 0 +#define REGS_SBPM_DBG_SELECT_BUS_MASK 0xf + + +/* + * Register - read-only + * + * SBPM UG0 allocated BN counter + */ +#define SBPM_REGS_SBPM_UG0_BAC 0x78 + +/* UG0 counter for allocated BNs */ +#define REGS_SBPM_UG0_BAC_UG0BAC_SHIFT 0 +#define REGS_SBPM_UG0_BAC_UG0BAC_MASK 0x3fff + + +/* + * Register - read-only + * + * SBPM UG1 allocated BN Counter + */ +#define SBPM_REGS_SBPM_UG1_BAC 0x7c + +/* Baffer Allocated Counter */ +#define REGS_SBPM_UG1_BAC_UG1BAC_SHIFT 0 +#define REGS_SBPM_UG1_BAC_UG1BAC_MASK 0x3fff + + +/* + * Register - read-only + * + * SBPM global BN Counter + */ +#define SBPM_REGS_SBPM_GL_BAC 0x98 + +/* Global BN counter */ +#define REGS_SBPM_GL_BAC_BAC_SHIFT 0 +#define REGS_SBPM_GL_BAC_BAC_MASK 0x3fff + + +/* + * Register + * + * SBPM UG0 Exclusive high and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG0_EXCL_HIGH_TRSH 0x9c + +/* exclusive high threshold */ +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG0_EXCL_HIGH_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM UG1 Exclusive high and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG1_EXCL_HIGH_TRSH 0x100 + +/* exclusive high threshold */ +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG1_EXCL_HIGH_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM UG0 Exclusive low and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG0_EXCL_LOW_TRSH 0x104 + +/* exclusive low threshold */ +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG0_EXCL_LOW_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register + * + * SBPM UG1 Exclusive low and hysteresis threshold. + * We cross to Excl state if BAC equals the threshold. + * We cross down to not Excl if BAC equals the thrshold minus the + * histeresis value. + */ +#define SBPM_REGS_SBPM_UG1_EXCL_LOW_TRSH 0x108 + +/* exclusive low threshold */ +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_SHIFT 0 +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLT_MASK 0x3fff + +/* exclusive histeresis threshold */ +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_SHIFT 16 +#define REGS_SBPM_UG1_EXCL_LOW_TRSH_EXCLH_MASK 0x3fff0000 + + +/* + * Register - read-only + * + * This register is status set of all 8 Ugs: + * Ack/NACK state and in addition Exclusive state pereach of 8 UGs + */ +#define SBPM_REGS_SBPM_UG_STATUS 0x11c + +/* + * Ack/Nack status per UG. + * 0 - NACK1 - ACKbit [0] in field matches UG0 ACK status,bit [1] in field + * matches UG1 ACK status,bit [2] in field matches UG2 ACK status,bit [3] + * in field matches UG3 ACK status,bit [4] in field matches UG4 ACK + * status,bit [5] in field matches UG5 ACK status,bit [6] in field matches + * UG6 ACK status,bit [7] in field matches UG7 ACK status, +*/ +#define REGS_SBPM_UG_STATUS_UG_ACK_STTS_SHIFT 0 +#define REGS_SBPM_UG_STATUS_UG_ACK_STTS_MASK 0x3 + +/* + * High EXCL/Non-Excl status per UG. + * 0 - non_exclusive1 - exclusive +*/ +#define REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_SHIFT 16 +#define REGS_SBPM_UG_STATUS_UG_EXCL_HIGH_STTS_MASK 0x30000 + +/* + * Low EXCL/Non-Excl status per UG. + * 0 - non_exclusive1 - exclusive +*/ +#define REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_SHIFT 18 +#define REGS_SBPM_UG_STATUS_UG_EXCL_LOW_STTS_MASK 0xc0000 + + +/* + * Register + * + * Parameters and thresholds used for Error handling: + * error detection, max search enable and threshold, etc. + */ +#define SBPM_REGS_ERROR_HANDLING_PARAMS 0x138 + +/* Depth (or maximal threshold) for search during Free without context */ +#define REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_SHIFT 0 +#define REGS_ERROR_HANDLING_PARAMS_SEARCH_DEPTH_MASK 0x7f + +/* Enable for max search during Free without context */ +#define REGS_ERROR_HANDLING_PARAMS_MAX_SEARCH_EN_MASK 0x80 + +/* Enable for Last BN checking during Free with context */ +#define REGS_ERROR_HANDLING_PARAMS_CHCK_LAST_EN_MASK 0x100 + +/* Freeze Ug/Global counters + mask access to SBPM RAM while in ERROR state */ +#define REGS_ERROR_HANDLING_PARAMS_FREEZE_IN_ERROR_MASK 0x200 + + +/* + * Register - read-only + * + * SBPM IIR low (Interrupt information register) + */ +#define SBPM_REGS_SBPM_IIR_LOW 0x148 + +/* Interrupt command source address (latched from BB SA or CPU code) */ +#define REGS_SBPM_IIR_LOW_CMD_SA_SHIFT 0 +#define REGS_SBPM_IIR_LOW_CMD_SA_MASK 0x3f + +/* Interrupt command target address (latched from BB TA or CPU request) */ +#define REGS_SBPM_IIR_LOW_CMD_TA_SHIFT 6 +#define REGS_SBPM_IIR_LOW_CMD_TA_MASK 0x1c0 + +/* + * Interrupt command data lowest 23-bit (latched from BB data[22: + * 0] or CPU request data) +*/ +#define REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_SHIFT 9 +#define REGS_SBPM_IIR_LOW_CMD_DATA_22TO0_MASK 0xfffffe00 + + +/* + * Register - read-only + * + * SBPM IIR high (Interrupt information register) + */ +#define SBPM_REGS_SBPM_IIR_HIGH 0x14c + +/* + * Data (bits [63: + * 23], without reserved bits) of the command that caused interrupt +*/ +#define REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_SHIFT 0 +#define REGS_SBPM_IIR_HIGH_CMD_DATA_23TO63_MASK 0xffffffff + + +/* + * Register - read-only + * + * SBPM debug vector0 includes 21 bit of control/state machine of CMD pipe + */ +#define SBPM_REGS_SBPM_DBG_VEC0 0x150 + +/* Alloc State Machine{update, rd_head_cnxt} */ +#define REGS_SBPM_DBG_VEC0_ALLOC_SM_SHIFT 0 +#define REGS_SBPM_DBG_VEC0_ALLOC_SM_MASK 0x3 + +/* Connect State Machine{update} */ +#define REGS_SBPM_DBG_VEC0_CNNCT_SM_MASK 0x4 + +/* Multicast incr State Machine{read,check,error,update} */ +#define REGS_SBPM_DBG_VEC0_MCINT_SM_SHIFT 3 +#define REGS_SBPM_DBG_VEC0_MCINT_SM_MASK 0x78 + +/* Free w cnxt State Machine{read,check,update,error} */ +#define REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_SHIFT 7 +#define REGS_SBPM_DBG_VEC0_FREE_W_CNXT_SM_MASK 0x780 + +/* Free w/o cnxt State Machine{read,check,update,error} */ +#define REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_SHIFT 11 +#define REGS_SBPM_DBG_VEC0_FREE_WO_CNXT_SM_MASK 0x7800 + +/* + * Get next State Machine: + * {read,reply} +*/ +#define REGS_SBPM_DBG_VEC0_GN_SM_SHIFT 15 +#define REGS_SBPM_DBG_VEC0_GN_SM_MASK 0x18000 + +/* + * Those are the 4 Multi get next states: + * {rd_next,error,rd_last,wait} +*/ +#define REGS_SBPM_DBG_VEC0_MULTI_GN_SM_SHIFT 17 +#define REGS_SBPM_DBG_VEC0_MULTI_GN_SM_MASK 0x1e0000 + +/* the value of the head of FREE list */ +#define REGS_SBPM_DBG_VEC0_FREE_LST_HD_SHIFT 21 +#define REGS_SBPM_DBG_VEC0_FREE_LST_HD_MASK 0xffe00000 + + +/* + * Register - read-only + * + * SBPM debug vector1 includes 21 bit of control/state machine of CMD pipe + */ +#define SBPM_REGS_SBPM_DBG_VEC1 0x154 + +/* sbpm_ingress2egress_valid bit */ +#define REGS_SBPM_DBG_VEC1_IN2E_VALID_MASK 0x1 + +/* multi_get_next_valid bits */ +#define REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_SHIFT 1 +#define REGS_SBPM_DBG_VEC1_MULTI_GN_VALID_MASK 0x1e + +/* sbpm_ug_active 2 bits */ +#define REGS_SBPM_DBG_VEC1_UG_ACTIVE_SHIFT 5 +#define REGS_SBPM_DBG_VEC1_UG_ACTIVE_MASK 0x60 + +/* sbpm_tx_cmd_fifo_full bit */ +#define REGS_SBPM_DBG_VEC1_TX_CMD_FULL_MASK 0x80 + +/* sbpm_rx_fifo_pop bit */ +#define REGS_SBPM_DBG_VEC1_RX_FIFO_POP_MASK 0x100 + +/* sbpm_ram_init_start bit */ +#define REGS_SBPM_DBG_VEC1_RAM_INIT_START_MASK 0x200 + +/* sbpm_ram_init_done bit */ +#define REGS_SBPM_DBG_VEC1_RAM_INIT_DONE_MASK 0x400 + +/* RX FIFO Data in pipe */ +#define REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_SHIFT 11 +#define REGS_SBPM_DBG_VEC1_RX_FIFO_DATA_MASK 0x1ff800 + +/* sbpm_free_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_FREE_DECODE_MASK 0x200000 + +/* sbpm_in2e_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_IN2E_DECODE_MASK 0x400000 + +/* sbpm_free_wo_cnxt_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_FREE_WO_DECODE_MASK 0x800000 + +/* sbpm_get_next_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_GET_NXT_DECODE_MASK 0x1000000 + +/* sbpm_multi_get_next_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_MULTI_GET_NXT_DECODE_MASK 0x2000000 + +/* sbpm_cnct_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_CNCT_DECODE_MASK 0x4000000 + +/* sbpm_free_w_cnxt_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_FREE_W_DECODE_MASK 0x8000000 + +/* sbpm_mcinc_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_MCIN_DECODE_MASK 0x10000000 + +/* sbpm_alloc_rqst_dec */ +#define REGS_SBPM_DBG_VEC1_ALLOC_DECODE_MASK 0x20000000 + + +/* + * Register - read-only + * + * This is one of the TX_handler debug vectors + */ +#define SBPM_REGS_SBPM_DBG_VEC2 0x174 + +/* sbpm_tx_data_fifo_full */ +#define REGS_SBPM_DBG_VEC2_TX_DATA_FULL_MASK 0x1 + +/* sbpm_tx_fifo_empty */ +#define REGS_SBPM_DBG_VEC2_TX_FIFO_EMPTY_MASK 0x2 + +/* sbpm_tx_cmd_local_stts_fifo_full */ +#define REGS_SBPM_DBG_VEC2_LCL_STTS_FULL_MASK 0x4 + +/* sbpm_tx_cmd_local_stts_fifo_empty */ +#define REGS_SBPM_DBG_VEC2_LCL_STTS_EMPTY_MASK 0x8 + +/* sbpm_tx_cmd_fifo_full */ +#define REGS_SBPM_DBG_VEC2_TX_CMD_FULL_MASK 0x10 + +/* sbpm_tx_cmd_fifo_empty */ +#define REGS_SBPM_DBG_VEC2_TX_CMD_FIFO_EMPTY_MASK 0x20 + +/* + * bb_decoder_dest_idThis is the ID of the user that will recieve a message + * from SBPM +*/ +#define REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_SHIFT 6 +#define REGS_SBPM_DBG_VEC2_BB_DECODER_DEST_ID_MASK 0xfc0 + +/* sbpm_tx_bbh_send_in_progress bit */ +#define REGS_SBPM_DBG_VEC2_TX_BBH_SEND_IN_PROGRESS_MASK 0x1000 + +/* sbpm_sp_2send - this is the user ID that is about to get stts msg */ +#define REGS_SBPM_DBG_VEC2_SP_2SEND_SHIFT 13 +#define REGS_SBPM_DBG_VEC2_SP_2SEND_MASK 0x7e000 + +/* + * sbpm_tx2data_fifo_taddr[2: + * 0] this is the opcode that describe the type of the reply +*/ +#define REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_SHIFT 19 +#define REGS_SBPM_DBG_VEC2_TX2DATA_FIFO_TADDR_MASK 0x380000 + +/* sbpm_cpu_access bit */ +#define REGS_SBPM_DBG_VEC2_CPU_ACCESS_MASK 0x400000 + +/* sbpm_bbh_access bit */ +#define REGS_SBPM_DBG_VEC2_BBH_ACCESS_MASK 0x800000 + +/* sbpm_rnr_access bit */ +#define REGS_SBPM_DBG_VEC2_RNR_ACCESS_MASK 0x1000000 + + +/* + * Register - read-only + * + * This is one of TX_handler debug vectors + */ +#define SBPM_REGS_SBPM_DBG_VEC3 0x178 + +/* ALLOC_RPLY bit */ +#define REGS_SBPM_DBG_VEC3_ALLOC_RPLY_MASK 0x1 + +/* BN_RPLY value */ +#define REGS_SBPM_DBG_VEC3_BN_RPLY_SHIFT 1 +#define REGS_SBPM_DBG_VEC3_BN_RPLY_MASK 0xffe + +/* sbpm_txfifo_alloc_ack */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_ALLOC_ACK_MASK 0x1000 + +/* sbpm_txfifo_mcinc_ack */ +#define REGS_SBPM_DBG_VEC3_TX_FIFO_MCINC_ACK_MASK 0x2000 + +/* sbpm_txfifo_cnct_ack */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_CNCT_ACK_MASK 0x4000 + +/* sbpm_txfifo_get_next_reply */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_GT_NXT_RPLY_MASK 0x8000 + +/* sbpm_txfifo_multi_get_next_reply */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_MLTI_GT_NXT_RPLY_MASK 0x10000 + +/* sbpm_tx_msg_pipe_cur_sm */ +#define REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_SHIFT 17 +#define REGS_SBPM_DBG_VEC3_TX_MSG_PIPE_SM_MASK 0x60000 + +/* sbpm_send_stat_sm_ps */ +#define REGS_SBPM_DBG_VEC3_SEND_STT_SM_MASK 0x80000 + +/* sbpm_txfifo_ingress2egress_stts_change */ +#define REGS_SBPM_DBG_VEC3_TXFIFO_IN2ESTTS_CHNG_MASK 0x100000 + + +/* + * Register + * + * This register mark all the SPs which are BBHs. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_BBH_LOW 0x17c + +/* sbpm_sp_bbh_low bit i tells us if SP #i is a BBH (1) or not (0) */ +#define REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_SHIFT 0 +#define REGS_SBPM_SP_BBH_LOW_SBPM_SP_BBH_LOW_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs which are BBHs. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_BBH_HIGH 0x180 + +/* + * Not in use in 68360!sbpm_sp_bbh_high bit i tells us if SP #i is a BBH + * (1) or not (0) +*/ +#define REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_SHIFT 0 +#define REGS_SBPM_SP_BBH_HIGH_SBPM_SP_BBH_HIGH_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs which are runners. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_RNR_LOW 0x184 + +/* sbpm_sp_rnr_low bit i tells us if SP #i is a runner (1) or not (0) */ +#define REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_SHIFT 0 +#define REGS_SBPM_SP_RNR_LOW_SBPM_SP_RNR_LOW_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs which are runners. + * Each bit in this register, refers to a SP with the same index + */ +#define SBPM_REGS_SBPM_SP_RNR_HIGH 0x188 + +/* + * Not in use in 68360!sbpm_sp_rnr_high bit i tells us if SP #i is a runner + * (1) or not (0) +*/ +#define REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_SHIFT 0 +#define REGS_SBPM_SP_RNR_HIGH_SBPM_SP_RNR_HIGH_MASK 0xffffffff + + +/* + * Register + * + * bit i value determine if SP number i belongs to UG0 (ingress) or UG1 + * (egress) + */ +#define SBPM_REGS_SBPM_UG_MAP_LOW 0x18c + +/* + * bit i value determine if SP number i belongs to UG0 (ingress) or UG1 + * (egress) +*/ +#define REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_SHIFT 0 +#define REGS_SBPM_UG_MAP_LOW_SBPM_UG_MAP_LOW_MASK 0xffffffff + + +/* + * Register + * + * bit i value determine if SP number i belongs to UG0 (ingress) or UG1 + * (egress) + */ +#define SBPM_REGS_SBPM_UG_MAP_HIGH 0x190 + +/* + * Not in use in 68360!bit i value determine if SP number i belongs to UG0 + * (ingress) or UG1 (egress) +*/ +#define REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_SHIFT 0 +#define REGS_SBPM_UG_MAP_HIGH_SBPM_UG_MAP_HIGH_MASK 0xffffffff + + +/* + * Register - read-only + * + * bit i value determine if SP number i got nack or not + */ +#define SBPM_REGS_SBPM_NACK_MASK_LOW 0x194 + +/* bit i value determine if SP number i got nack or not */ +#define REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_SHIFT 0 +#define REGS_SBPM_NACK_MASK_LOW_SBPM_NACK_MASK_LOW_MASK 0xffffffff + + +/* + * Register - read-only + * + * bit i value determine if SP number i got nack or not + */ +#define SBPM_REGS_SBPM_NACK_MASK_HIGH 0x198 + +/* bit i value determine if SP number i got nack or not */ +#define REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_SHIFT 0 +#define REGS_SBPM_NACK_MASK_HIGH_SBPM_NACK_MASK_HIGH_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs that should get exclusive messages + */ +#define SBPM_REGS_SBPM_EXCL_MASK_LOW 0x19c + +/* This register mark all the SPs that should get exclusive messagesyes no */ +#define REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_SHIFT 0 +#define REGS_SBPM_EXCL_MASK_LOW_SBPM_EXCL_MASK_LOW_MASK 0xffffffff + + +/* + * Register + * + * This register mark all the SPs that should get exclusive messages + */ +#define SBPM_REGS_SBPM_EXCL_MASK_HIGH 0x1a0 + +/* + * Not in use in 68360!This register mark all the SPs that should get + * exclusive messagesyes no +*/ +#define REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_SHIFT 0 +#define REGS_SBPM_EXCL_MASK_HIGH_SBPM_EXCL_MASK_HIGH_MASK 0xffffffff + + +/* + * Register + * + * This register let you choose one user that you would like to change its + * default RA. + */ +#define SBPM_REGS_SBPM_RADDR_DECODER 0x1a4 + +/* + * this field contains the users id that you want to override its default + * RA +*/ +#define REGS_SBPM_RADDR_DECODER_ID_2OVERWR_SHIFT 0 +#define REGS_SBPM_RADDR_DECODER_ID_2OVERWR_MASK 0x3f + +/* The new RA */ +#define REGS_SBPM_RADDR_DECODER_OVERWR_RA_SHIFT 6 +#define REGS_SBPM_RADDR_DECODER_OVERWR_RA_MASK 0xffc0 + +/* the overwr mechanism will be used only if this bit is active (1). */ +#define REGS_SBPM_RADDR_DECODER_OVERWR_VALID_MASK 0x10000 + + +/* + * Register + * + * If SW want to write a whole word into the SBPMs RAM, it needs first to + * write the data to this register and then, send connect request with the + * wr_req bit asserted, with the address (BN field). + */ +#define SBPM_REGS_SBPM_WR_DATA 0x1a8 + +/* + * If SW want to write a whole word into the SBPMs RAM, it needs first to + * write the data to this register and then, send connect request with the + * wr_req bit asserted, with the address (BN field). + * In 68360 the only the 15 LSB are used +*/ +#define REGS_SBPM_WR_DATA_SBPM_WR_DATA_SHIFT 0 +#define REGS_SBPM_WR_DATA_SBPM_WR_DATA_MASK 0x3fffff + + +/* + * Register + * + * This register tracks the max values of the UG counters. + * it can be reset/modified by SW. + */ +#define SBPM_REGS_SBPM_UG_BAC_MAX 0x1ac + +/* + * This is the maximum value that have been recorded on the UG0 counter. + * SW can write to this field in order to change the max record (for + * example write 0 to reset it) +*/ +#define REGS_SBPM_UG_BAC_MAX_UG0BACMAX_SHIFT 0 +#define REGS_SBPM_UG_BAC_MAX_UG0BACMAX_MASK 0x3fff + +/* + * This is the maximum value that have been recorded on the UG1 counter. + * SW can write to this field in order to change the max record (for + * example write 0 to reset it) +*/ +#define REGS_SBPM_UG_BAC_MAX_UG1BACMAX_SHIFT 14 +#define REGS_SBPM_UG_BAC_MAX_UG1BACMAX_MASK 0xfffc000 + + +/* + * Register + * + * sbpm spare register + */ +#define SBPM_REGS_SBPM_SPARE 0x1b0 + +/* sbpm_gl_bac_clear_en */ +#define REGS_SBPM_SPARE_GL_BAC_CLEAR_EN_MASK 0x1 + + +/* + * Register + * + * This register contains the current active TM interrupts. + * Each asserted bit represents an active interrupt source. + * The interrupt remains active until the software clears it by writing 1 + * to the corresponding bit. + */ +#define SBPM_INTR_CTRL_ISR 0x200 + +/* + * This error bit indicates underrun state of SBPM Buffer Allocated Counter + * (one of User Groups). + * SW can clear this bit by writing 1 to this field +*/ +#define INTR_CTRL_ISR_BAC_UNDERRUN_MASK 0x1 + +/* + * This error bit indicates if the Multi Cast value of a buffer is in + * overflow as a result of erroneous MCINC command +*/ +#define INTR_CTRL_ISR_MCST_OVERFLOW_MASK 0x2 + +/* + * This bit indicates error state on Last BN checking during Free with + * context request. + * SW can clear this bit by writing 1 to this field. +*/ +#define INTR_CTRL_ISR_CHECK_LAST_ERR_MASK 0x4 + +/* + * This bit indicates error state on maximal search checking during Free + * without context request. + * SW can clear this bit by writing 1 to this field. +*/ +#define INTR_CTRL_ISR_MAX_SEARCH_ERR_MASK 0x8 + +/* + * This bit indicates invalid ingress2egress command (caused BAC + * under/overrun). + * SW can clear this bit by writing 1 to this field. +*/ +#define INTR_CTRL_ISR_INVALID_IN2E_MASK 0x10 + +/* + * This bit indicates Null encounter during one of the next BNs. + * SW can clear this bit by writing 0 to this field. +*/ +#define INTR_CTRL_ISR_MULTI_GET_NEXT_NULL_MASK 0x20 + +/* + * This bit indicates connection of the NULL buffer to another buufer. + * SW can clear this bit by writing 0 to this field. +*/ +#define INTR_CTRL_ISR_CNCT_NULL_MASK 0x40 + +/* + * This bit indicates allocation of the NULL buffer. + * SW can clear this bit by writing 0 to this field. +*/ +#define INTR_CTRL_ISR_ALLOC_NULL_MASK 0x80 + + +/* + * Register - read-only + * + * This register provides only the enabled interrupts for each of the + * interrupt sources depicted in the ISR register. + */ +#define SBPM_INTR_CTRL_ISM 0x204 + +/* Status Masked of corresponding interrupt source in the ISR */ +#define INTR_CTRL_ISM_ISM_SHIFT 0 +#define INTR_CTRL_ISM_ISM_MASK 0xffffffff + + +/* + * Register + * + * This register provides an enable mask for each of the interrupt sources + * depicted in the ISR register. + */ +#define SBPM_INTR_CTRL_IER 0x208 + +/* + * Each bit in the mask controls the corresponding interrupt source in the + * IER +*/ +#define INTR_CTRL_IER_IEM_SHIFT 0 +#define INTR_CTRL_IER_IEM_MASK 0xffffffff + + +/* + * Register + * + * This register enables testing by simulating interrupt sources. + * When the software sets a bit in the ITR, the corresponding bit in the + * ISR shows an active interrupt. + * The interrupt remains active until software clears the bit in the ITR + */ +#define SBPM_INTR_CTRL_ITR 0x20c + +/* Each bit in the mask tests the corresponding interrupt source in the ISR */ +#define INTR_CTRL_ITR_IST_SHIFT 0 +#define INTR_CTRL_ITR_IST_MASK 0xffffffff + + +#endif /* ! XRDP_REGS_SBPM_H_ */ diff -Nruw linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_tcam.h linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_tcam.h --- linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx./xrdp/regs/xrdp_regs_tcam.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-5.4.60-fbx/drivers/soc/bcm/bcm63xx/xrdp/regs/xrdp_regs_tcam.h 2021-03-04 13:20:59.834172314 +0100 @@ -0,0 +1,225 @@ +#ifndef XRDP_REGS_TCAM_H_ +#define XRDP_REGS_TCAM_H_ + +/* relative to core */ +#define TCAM_OFFSET_0 0xe00000 + +/* + * Registers - is [ 0 => 2047 ] + * + * Each 64 bit entry in the context ram occupies two addresses: + * For 64bit entry number i: + * the 32 least significant bits of the context are in address 2*ithe 32 + * most significant bits of the context are in address 2*i +1 + */ +#define TCAM_CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT(x) (0x0 + (x) * 0x4) + +/* . */ +#define CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_SHIFT 0 +#define CONTEXT_RAM_TCAM_TCAM_CONTEXT_RAM_CONTEXT_DATA_MASK 0xffffffff + + +/* + * Register + * + * The TCAM is divided into 8 banks. + * banks can be disabled to save power. + * bit i correspond to addresses i*128: + * i*128+127 + */ +#define TCAM_CFG_TCAM_TCAM_CFG_BANK_EN 0x2000 + +/* . */ +#define CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_SHIFT 0 +#define CFG_TCAM_TCAM_CFG_BANK_EN_VALUE_MASK 0xff + + +/* + * Registers - is [ 0 => 7 ] + * + * Global Mask - 256bit mask for all entries. + * Default value enable all bits. + */ +#define TCAM_CFG_TCAM_TCAM_CFG_GLOBAL_MASK(x) (0x2010 + (x) * 0x4) + +/* . */ +#define CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_SHIFT 0 +#define CFG_TCAM_TCAM_CFG_GLOBAL_MASK_VALUE_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 256bit key searches + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256 0x2100 + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_256_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 256bit key hits + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_256 0x2104 + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_256_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 512it key searches + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512 0x2108 + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_SRCH_512_CNT_MASK 0xffffffff + + +/* + * Register - read-only + * + * Number of 512bit key hits + */ +#define TCAM_COUNTERS_TCAM_TCAM_COUNTERS_HIT_512 0x210c + +/* . */ +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_SHIFT 0 +#define COUNTERS_TCAM_TCAM_COUNTERS_HIT_512_CNT_MASK 0xffffffff + + +/* + * Register + * + * TCAM Operation: + * 0 - TCAM READ1 - TCAM Write2 - TCAM Compare3 - TCAM valid bit + * resetWriting to this register triggers the operation. + * All other relevant register should be ready before SW writes to this + * register. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP 0x2200 + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_SHIFT 0 +#define INDIRECT_TCAM_TCAM_INDIRECT_OP_CMD_MASK 0xf + + +/* + * Register - read-only + * + * Raised when the TCAM operation is completed (cleared by HW on write to + * the OPERATION regiser) + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE 0x2204 + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_OP_DONE_DONE_MASK 0x1 + + +/* + * Register
+ * + * Key Address to be used in RD/WR opoerations. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_ADDR 0x2208 + +/* + * This bit indicate if the operation (RD/WR) is performed on the key0 or + * key1 part of the entry +*/ +#define INDIRECT_TCAM_TCAM_INDIRECT_ADDR_KEY1_IND_MASK 0x1 + +/* Address of the entry */ +#define INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_SHIFT 1 +#define INDIRECT_TCAM_TCAM_INDIRECT_ADDR_ENTRY_ADDR_MASK 0x7fe + + +/* + * Register + * + * Valid value to be written - this value is relevant during write + * operation on key0. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN 0x220c + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_VLID_IN_VALID_MASK 0x1 + + +/* + * Register + * + * Valid value read from the TCAM - this value is relevant during read + * operation on key0. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT 0x2214 + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_VLID_OUT_VALID_MASK 0x1 + + +/* + * Register - read-only + * + * The result of a search operation + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_RSLT 0x2218 + +/* indicate if a match was found */ +#define INDIRECT_TCAM_TCAM_INDIRECT_RSLT_MATCH_MASK 0x1 + +/* index related to a match result */ +#define INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_SHIFT 4 +#define INDIRECT_TCAM_TCAM_INDIRECT_RSLT_INDEX_MASK 0x3ff0 + + +/* + * Registers - is [ 0 => 7 ] + * + * Key to be used in Write/Compare operations. + * The Key is 256bit long and is represented by 8 registers. + * The lower address register correspond to the least significant bits of + * the key. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN(x) (0x2220 + (x) * 0x4) + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_SHIFT 0 +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_IN_VALUE_MASK 0xffffffff + + +/* + * Registers - is [ 0 => 7 ] - read-only + * + * Key returned from the CAM in a read operation. + * The Key is 256bit long and is represented by 8 registers. + * The lower address register correspond to the least significant bits of + * the key. + */ +#define TCAM_INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT(x) (0x2240 + (x) * 0x4) + +/* . */ +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_SHIFT 0 +#define INDIRECT_TCAM_TCAM_INDIRECT_KEY_OUT_VALUE_MASK 0xffffffff + + +/* + * Register